diff -Nrcpad gcc-16-20251026/.editorconfig gcc-16-20251102/.editorconfig
*** gcc-16-20251026/.editorconfig	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/.editorconfig	Sun Nov  2 22:32:16 2025
*************** charset = utf-8
*** 53,58 ****
--- 53,59 ----
  charset = utf-8
  indent_style = tab
  indent_size = 2
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # GCC .def files.  These are generally C fragments that get included
*************** trim_trailing_whitespace = true
*** 61,78 ****
--- 62,82 ----
  charset = utf-8
  indent_style = tab
  indent_size = 2
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Texinfo files
  [*.texi]
  charset = utf-8
  indent_size = 2
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Expect / TCL
  [*.{exp,tcl}]
  indent_style = tab
  indent_size = 4
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Python
*************** trim_trailing_whitespace = true
*** 91,114 ****
--- 95,122 ----
  [gcc/config/**.md]
  indent_style = tab
  indent_size = 2
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Awk
  [*.awk]
  indent_style = tab
  indent_size = 2
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Autoconf
  [*.{ac,m4}]
  indent_style = tab
  indent_size = 2
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Shell scripts
  [*.sh]
  indent_style = tab
  indent_size = 4
+ tab_width = 8
  trim_trailing_whitespace = true
  
  # Ada
diff -Nrcpad gcc-16-20251026/ChangeLog gcc-16-20251102/ChangeLog
*** gcc-16-20251026/ChangeLog	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/ChangeLog	Sun Nov  2 22:32:16 2025
***************
*** 1,3 ****
--- 1,20 ----
+ 2025-10-30  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	* MAINTAINERS: Add myself to reviewers/maintainers.
+ 
+ 2025-10-28  Richard Earnshaw  <rearnsha@arm.com>
+ 
+ 	* .editorconfig: Explicitly set tab_width whenever a
+ 	config rule has indent_style = tab and indent_size != 8.
+ 
+ 2025-10-28  Artemiy Volkov  <artemiy.volkov@arm.com>
+ 
+ 	* MAINTAINERS: Add myself to write after approval.
+ 
+ 2025-10-27  Jennifer Schmitz  <jschmitz@nvidia.com>
+ 
+ 	* MAINTAINERS: Change email address.
+ 
  2025-10-24  Thomas Schwinge  <tschwinge@baylibre.com>
  
  	PR driver/81358
diff -Nrcpad gcc-16-20251026/LAST_UPDATED gcc-16-20251102/LAST_UPDATED
*** gcc-16-20251026/LAST_UPDATED	Sun Oct 26 22:33:30 2025
--- gcc-16-20251102/LAST_UPDATED	Sun Nov  2 22:34:37 2025
***************
*** 1 ****
! Obtained from git: master revision e4ab1b50e35d6a756c120d66554df8c2135b8d12
--- 1 ----
! Obtained from git: master revision d66209cee5dda39ac4add589f4535f35c5736c63
diff -Nrcpad gcc-16-20251026/MAINTAINERS gcc-16-20251102/MAINTAINERS
*** gcc-16-20251026/MAINTAINERS	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/MAINTAINERS	Sun Nov  2 22:32:16 2025
*************** powerpcspe port         Andrew Jenner
*** 109,114 ****
--- 109,115 ----
  pru port                Dimitar Dimitrov        <dimitar@dinux.eu>
  riscv port              Kito Cheng              <kito.cheng@gmail.com>
  riscv port              Palmer Dabbelt          <palmer@dabbelt.com>
+ riscv port              Robin Dapp              <rdapp.gcc@gmail.com>
  riscv port              Andrew Waterman         <andrew@sifive.com>
  riscv port              Jim Wilson              <jim.wilson.gcc@gmail.com>
  rs6000/powerpc port     David Edelsohn          <dje.gcc@gmail.com>
*************** Plugin                  Le-Chun Wu
*** 317,327 ****
  register allocation     Peter Bergner           <bergner@tenstorrent.com>
  register allocation     Kenneth Zadeck          <zadeck@naturalbridge.com>
  register allocation     Seongbae Park           <seongbae.park@gmail.com>
- riscv port              Robin Dapp              <rdapp.gcc@gmail.com>
  riscv port              Juzhe Zhong             <juzhe.zhong@rivai.ai>
  RTL optimizers          Steven Bosscher         <steven@gcc.gnu.org>
  selective scheduling    Andrey Belevantsev      <abel@ispras.ru>
  selective scheduling    Alexander Monakov       <amonakov@ispras.ru>
  wide-int                Kenneth Zadeck          <zadeck@naturalbridge.com>
  wide-int                Mike Stump              <mikestump@comcast.net>
  wide-int                Richard Sandiford       <rdsandiford@googlemail.com>
--- 318,328 ----
  register allocation     Peter Bergner           <bergner@tenstorrent.com>
  register allocation     Kenneth Zadeck          <zadeck@naturalbridge.com>
  register allocation     Seongbae Park           <seongbae.park@gmail.com>
  riscv port              Juzhe Zhong             <juzhe.zhong@rivai.ai>
  RTL optimizers          Steven Bosscher         <steven@gcc.gnu.org>
  selective scheduling    Andrey Belevantsev      <abel@ispras.ru>
  selective scheduling    Alexander Monakov       <amonakov@ispras.ru>
+ vectorizer (+ tree-if-conv) Robin Dapp          <rdapp.gcc@gmail.com>
  wide-int                Kenneth Zadeck          <zadeck@naturalbridge.com>
  wide-int                Mike Stump              <mikestump@comcast.net>
  wide-int                Richard Sandiford       <rdsandiford@googlemail.com>
*************** Roger Sayle                     sayle
*** 792,798 ****
  Tobias Schlüter                 tobi            <tobias.schlueter@physik.uni-muenchen.de>
  Bernd Schmidt                   bernds          <bernds_cb1@t-online.de>
  Will Schmidt                    willschm        <will_schmidt@vnet.ibm.com>
! Jennifer Schmitz                jschmitz        <jschmitz@nvidia.com>
  Stefan Schulze Frielinghaus     stefansf        <stefansf@linux.ibm.com>
  Andreas Schwab                  schwab          <schwab@linux-m68k.org>
  Tilo Schwarz                    tiloschwarz     <tilo@tilo-schwarz.de>
--- 793,799 ----
  Tobias Schlüter                 tobi            <tobias.schlueter@physik.uni-muenchen.de>
  Bernd Schmidt                   bernds          <bernds_cb1@t-online.de>
  Will Schmidt                    willschm        <will_schmidt@vnet.ibm.com>
! Jennifer Schmitz                jschmitz        <jschmitz@mailbox.org>
  Stefan Schulze Frielinghaus     stefansf        <stefansf@linux.ibm.com>
  Andreas Schwab                  schwab          <schwab@linux-m68k.org>
  Tilo Schwarz                    tiloschwarz     <tilo@tilo-schwarz.de>
*************** Ilya Verbin                     iverbin
*** 868,873 ****
--- 869,875 ----
  Andre Vieira                    avieira         <andre.simoesdiasvieira@arm.com>
  Rasmus Villemoes                -               <rv@rasmusvillemoes.dk>
  Kugan Vivekanandarajah          kugan           <kvivekananda@nvidia.com>
+ Artemiy Volkov                  artemiyv        <artemiy.volkov@arm.com>
  Marcel Vollweiler               -               <marcel@codesourcery.com>
  Ville Voutilainen               ville           <ville.voutilainen@gmail.com>
  Tom de Vries                    vries           <tdevries@suse.de>
*************** Navid Rahimi
*** 973,979 ****
  Rishi Raj                                       <rishiraj45035@gmail.com>
  Trevor Saunders                                 <tbsaunde+gcc@tbsaunde.org>
  Bill Schmidt                                    <bill.schmidt@fastmail.com>
- Jennifer Schmitz                                <jschmitz@nvidia.com>
  Nathaniel Shead                                 <nathanieloshead@gmail.org>
  Nathan Sidwell                                  <nathan@acm.org>
  Edward Smith-Rowland                            <esmithrowland@gmail.com>
--- 975,980 ----
diff -Nrcpad gcc-16-20251026/MD5SUMS gcc-16-20251102/MD5SUMS
*** gcc-16-20251026/MD5SUMS	Sun Oct 26 22:33:34 2025
--- gcc-16-20251102/MD5SUMS	Sun Nov  2 22:34:46 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20251026.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20251102.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
***************
*** 10,16 ****
  #
  e8eeef33ef071516ce3f689e9c71e0b5  .b4-config
  fd78d02fa55fcdb78ddb2f37a7868dbb  .dir-locals.el
! 617f425ec650450d3b979db16e73b315  .editorconfig
  b91d600742b62d1860809cb184055a3d  .forgejo/PULL_REQUEST_TEMPLATE.md
  5b2970579525915c2f5b5a104935b2af  .forgejo/workflows/sanity-checks.yaml
  5b296b32e07d2a84f4ac051ed7f95b91  .gitattributes
--- 10,16 ----
  #
  e8eeef33ef071516ce3f689e9c71e0b5  .b4-config
  fd78d02fa55fcdb78ddb2f37a7868dbb  .dir-locals.el
! c83d1c4a8d42642be0511fa89b9c3cf5  .editorconfig
  b91d600742b62d1860809cb184055a3d  .forgejo/PULL_REQUEST_TEMPLATE.md
  5b2970579525915c2f5b5a104935b2af  .forgejo/workflows/sanity-checks.yaml
  5b296b32e07d2a84f4ac051ed7f95b91  .gitattributes
*************** ac5a8807f431d3dab46a7425b96379e4  .gitig
*** 23,34 ****
  fe60d87048567d4fe8c8a0ed2448bcc8  COPYING.RUNTIME
  d32239bcb673463ab874e80d47fae504  COPYING3
  6a6a8e020838b23406c81b19c1d46df6  COPYING3.LIB
! 20decbb02b73405da2221e4656218ca8  ChangeLog
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! add82c5a8c8aa08c6ff9a066cdb06cc6  LAST_UPDATED
! 8675c6bdd00d25f1e8eff4fe5642015f  MAINTAINERS
  e4676e623f8df5efef68f36db1121a28  Makefile.def
  e602349d286d2792c339d5a6f514efde  Makefile.in
  cc2d22050d55934f814da4b15b72cef2  Makefile.tpl
--- 23,34 ----
  fe60d87048567d4fe8c8a0ed2448bcc8  COPYING.RUNTIME
  d32239bcb673463ab874e80d47fae504  COPYING3
  6a6a8e020838b23406c81b19c1d46df6  COPYING3.LIB
! e0703a4a2bb350e9a4578a0bfcb4bc72  ChangeLog
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 83738a4f900f4c3ed0a2ea2c6f479df8  LAST_UPDATED
! c4d040796ef5e08dc8d7ea898235f87e  MAINTAINERS
  e4676e623f8df5efef68f36db1121a28  Makefile.def
  e602349d286d2792c339d5a6f514efde  Makefile.in
  cc2d22050d55934f814da4b15b72cef2  Makefile.tpl
*************** e2dc6b4fd62b77bff96b7951ef74f78f  config
*** 157,163 ****
  db74a73c3c9c3cc71edec37c2436e082  config/zstd.m4
  495ed9ecf8750f1291e5cc64eb777d4e  configure
  3fd655ec08ac4a6ad2ab9bd795775aaf  configure.ac
! 7d3f8a14d6779c2dfea278b7075d68e2  contrib/ChangeLog
  5fc435c7928f858246df931ea3f3ece7  contrib/ChangeLog.jit
  7af8d2979bf1a7cfa88e30d05fa22be2  contrib/ChangeLog.tree-ssa
  13605e5ba7b533ecbe3a902b8ebe4079  contrib/analyze_brprob.py
--- 157,163 ----
  db74a73c3c9c3cc71edec37c2436e082  config/zstd.m4
  495ed9ecf8750f1291e5cc64eb777d4e  configure
  3fd655ec08ac4a6ad2ab9bd795775aaf  configure.ac
! c79879703bbd60d9b966a7770cffe1a4  contrib/ChangeLog
  5fc435c7928f858246df931ea3f3ece7  contrib/ChangeLog.jit
  7af8d2979bf1a7cfa88e30d05fa22be2  contrib/ChangeLog.tree-ssa
  13605e5ba7b533ecbe3a902b8ebe4079  contrib/analyze_brprob.py
*************** c031cdd918e93a5780aab350a42591d8  contri
*** 195,201 ****
  db03e57377f9eb202b7b783eb81fe40d  contrib/filter_knr2ansi.pl
  d577ea19d05f19a8364f73c9901223b7  contrib/filter_params.py
  1f09615feb91c049cbf46b27ea159c58  contrib/gcc-changelog/git_check_commit.py
! 6e02ba1a02f7c15add8a31bdabbdab03  contrib/gcc-changelog/git_commit.py
  6a772ce384751a560f60790681e6fc41  contrib/gcc-changelog/git_email.py
  039963086e96c2e9fdf8ae5643394a9c  contrib/gcc-changelog/git_repository.py
  5c0a44b6238e0b72cf2b5d2ad94c0e36  contrib/gcc-changelog/git_update_version.py
--- 195,201 ----
  db03e57377f9eb202b7b783eb81fe40d  contrib/filter_knr2ansi.pl
  d577ea19d05f19a8364f73c9901223b7  contrib/filter_params.py
  1f09615feb91c049cbf46b27ea159c58  contrib/gcc-changelog/git_check_commit.py
! f2b4239bdf920a0921b05e2cb7433fc1  contrib/gcc-changelog/git_commit.py
  6a772ce384751a560f60790681e6fc41  contrib/gcc-changelog/git_email.py
  039963086e96c2e9fdf8ae5643394a9c  contrib/gcc-changelog/git_repository.py
  5c0a44b6238e0b72cf2b5d2ad94c0e36  contrib/gcc-changelog/git_update_version.py
*************** a22e70b3f29292d0e628450f4bb11e62  fixinc
*** 520,526 ****
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! 4f38e66c2dc0305e415accf1260c23df  gcc/ChangeLog
  51281e73aa07fb62394bd72f3c9299ba  gcc/ChangeLog-1997
  f77af8c9ac412064886b00c5506123b5  gcc/ChangeLog-1998
  00a2e4ead1b289bf69bca0196fed6f9f  gcc/ChangeLog-1999
--- 520,526 ----
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! 2f7e6d1cb3b6603b973d2e33f48997bb  gcc/ChangeLog
  51281e73aa07fb62394bd72f3c9299ba  gcc/ChangeLog-1997
  f77af8c9ac412064886b00c5506123b5  gcc/ChangeLog-1998
  00a2e4ead1b289bf69bca0196fed6f9f  gcc/ChangeLog-1999
*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 557,563 ****
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 8f3538cf3f4ab2a86aadfa504309e43a  gcc/DATESTAMP
  deb513e591f23901188e22323bd3b1d4  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
--- 557,563 ----
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 9cd2acde05f610c32470c0fbaef4f9a3  gcc/DATESTAMP
  deb513e591f23901188e22323bd3b1d4  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
*************** ec6799501b2eb2923d5de6a66169dbd2  gcc/ON
*** 569,575 ****
  23d99b5becf269aa690a91a6f95228b9  gcc/acinclude.m4
  e74733ebf762151e601c9e0aa1461a20  gcc/aclocal.m4
  16a499934b71eb6cf7c0d6899cd6006a  gcc/ada/.gitignore
! 1fb13f55ef4ac6fb31dd978fef7667c0  gcc/ada/ChangeLog
  c2094c0d3135f9ac89917f162046ee04  gcc/ada/ChangeLog-2001
  fa410b57f5d814d5d3ac3b45f486cdcf  gcc/ada/ChangeLog-2002
  2dbefa7bdc8dc28ec746002028861278  gcc/ada/ChangeLog-2003
--- 569,575 ----
  23d99b5becf269aa690a91a6f95228b9  gcc/acinclude.m4
  e74733ebf762151e601c9e0aa1461a20  gcc/aclocal.m4
  16a499934b71eb6cf7c0d6899cd6006a  gcc/ada/.gitignore
! 43c690ea7caa06a68a702600cd89706c  gcc/ada/ChangeLog
  c2094c0d3135f9ac89917f162046ee04  gcc/ada/ChangeLog-2001
  fa410b57f5d814d5d3ac3b45f486cdcf  gcc/ada/ChangeLog-2002
  2dbefa7bdc8dc28ec746002028861278  gcc/ada/ChangeLog-2003
*************** a07518144c5203a421dbc45a7b16e04f  gcc/ad
*** 606,612 ****
  30e7387695692ce78b78ca8165fa9561  gcc/ada/adabkend.ads
  3d1fcc88d6e5624970030c0a00ed8653  gcc/ada/adadecode.c
  066612d3b34078e2a26c00cff399ed82  gcc/ada/adadecode.h
! accf7e9d7174fedb8b25677d5957bd67  gcc/ada/adaint.c
  f6a5ac54108a44c0cdc3ee5c49d836ae  gcc/ada/adaint.h
  4ef2efbae418f280f680909768eeb59d  gcc/ada/affinity.c
  a22ae88618cb2fc05cb66a79ed80efb5  gcc/ada/ali-util.adb
--- 606,612 ----
  30e7387695692ce78b78ca8165fa9561  gcc/ada/adabkend.ads
  3d1fcc88d6e5624970030c0a00ed8653  gcc/ada/adadecode.c
  066612d3b34078e2a26c00cff399ed82  gcc/ada/adadecode.h
! b0cd87f97b5a146eb21cb1ffdda62ce0  gcc/ada/adaint.c
  f6a5ac54108a44c0cdc3ee5c49d836ae  gcc/ada/adaint.h
  4ef2efbae418f280f680909768eeb59d  gcc/ada/affinity.c
  a22ae88618cb2fc05cb66a79ed80efb5  gcc/ada/ali-util.adb
*************** e86af58cfa10e3db683b44d2a2cf4c29  gcc/ad
*** 616,624 ****
  f8207765beac36c54d43698a11140afa  gcc/ada/alloc.ads
  3150d7e2a4f0018bb92d065ed3aedcc0  gcc/ada/argv-lynxos178-raven-cert.c
  5470386a6301c0323b6ee66cf06c1e42  gcc/ada/argv.c
! aab949fe9ede11d088dfe5f0493580f5  gcc/ada/aspects.adb
  8c62ffc91a61d63a863ec2627bbc388a  gcc/ada/aspects.ads
! 6ac042bab0630fbc0b61560d012db735  gcc/ada/atree.adb
  e06413c30b21b3ef9529c9b89592cca6  gcc/ada/atree.ads
  1a5f952bcb9d3c3529147729f3c4ef61  gcc/ada/atree.h
  557d2d802d51833ba752f2b05e30c591  gcc/ada/aux-io.c
--- 616,624 ----
  f8207765beac36c54d43698a11140afa  gcc/ada/alloc.ads
  3150d7e2a4f0018bb92d065ed3aedcc0  gcc/ada/argv-lynxos178-raven-cert.c
  5470386a6301c0323b6ee66cf06c1e42  gcc/ada/argv.c
! be50b0b84a57af26b228093529d8228d  gcc/ada/aspects.adb
  8c62ffc91a61d63a863ec2627bbc388a  gcc/ada/aspects.ads
! 07a8929ab2375e3afc95d4d6e5fedcf6  gcc/ada/atree.adb
  e06413c30b21b3ef9529c9b89592cca6  gcc/ada/atree.ads
  1a5f952bcb9d3c3529147729f3c4ef61  gcc/ada/atree.h
  557d2d802d51833ba752f2b05e30c591  gcc/ada/aux-io.c
*************** c8fc2a7d00b9bdf2dfb05cf0fc1c945f  gcc/ad
*** 674,680 ****
  d5cdeee41f4cce7791ad47380e922eac  gcc/ada/cstand.ads
  1812c1cc859b55d34f8be50223970490  gcc/ada/cstreams.c
  453f1af3f48533612fca76f44afc9122  gcc/ada/ctrl_c.c
! 3a318928391ad055311f7a0a7b51412d  gcc/ada/debug.adb
  c13504ec17d3c6cecfc69808385f8273  gcc/ada/debug.ads
  d5598c70c14c05fdc521df6eaab25b4c  gcc/ada/debug_a.adb
  af445affacf9cfc99e3eb8ee82b8b7f0  gcc/ada/debug_a.ads
--- 674,680 ----
  d5cdeee41f4cce7791ad47380e922eac  gcc/ada/cstand.ads
  1812c1cc859b55d34f8be50223970490  gcc/ada/cstreams.c
  453f1af3f48533612fca76f44afc9122  gcc/ada/ctrl_c.c
! d4c8212f2294ff5f7abf640b8e3ede1c  gcc/ada/debug.adb
  c13504ec17d3c6cecfc69808385f8273  gcc/ada/debug.ads
  d5598c70c14c05fdc521df6eaab25b4c  gcc/ada/debug_a.adb
  af445affacf9cfc99e3eb8ee82b8b7f0  gcc/ada/debug_a.ads
*************** cd313e8a12cdfb20b99eede7c5252f16  gcc/ad
*** 693,699 ****
  1ce2dc848df98bcbbb9d443501c48132  gcc/ada/doc/gnat_rm/implementation_of_specific_ada_features.rst
  454fb365cfb751d8e03b8e972d3abef1  gcc/ada/doc/gnat_rm/interfacing_to_other_languages.rst
  d3ffb5a905c9520d87b68e10029eb023  gcc/ada/doc/gnat_rm/intrinsic_subprograms.rst
! 99413730be6e496eacbd74d7ce317161  gcc/ada/doc/gnat_rm/obsolescent_features.rst
  952177853de529b7a2f483f0d195d2b4  gcc/ada/doc/gnat_rm/representation_clauses_and_pragmas.rst
  1813c7ae4ff4245bfbeb8dcf9e475019  gcc/ada/doc/gnat_rm/security_hardening_features.rst
  4de72a3ff83ec3e42cb0d1eaffe486dd  gcc/ada/doc/gnat_rm/specialized_needs_annexes.rst
--- 693,699 ----
  1ce2dc848df98bcbbb9d443501c48132  gcc/ada/doc/gnat_rm/implementation_of_specific_ada_features.rst
  454fb365cfb751d8e03b8e972d3abef1  gcc/ada/doc/gnat_rm/interfacing_to_other_languages.rst
  d3ffb5a905c9520d87b68e10029eb023  gcc/ada/doc/gnat_rm/intrinsic_subprograms.rst
! 3b3b1a4a300ed753e0096fbbf83db984  gcc/ada/doc/gnat_rm/obsolescent_features.rst
  952177853de529b7a2f483f0d195d2b4  gcc/ada/doc/gnat_rm/representation_clauses_and_pragmas.rst
  1813c7ae4ff4245bfbeb8dcf9e475019  gcc/ada/doc/gnat_rm/security_hardening_features.rst
  4de72a3ff83ec3e42cb0d1eaffe486dd  gcc/ada/doc/gnat_rm/specialized_needs_annexes.rst
*************** c7da61a05156d50b4888cdfaae4241d0  gcc/ad
*** 720,729 ****
  0a025bfec2a94c0fcd11a19d18f6c0c5  gcc/ada/doc/share/gnu_free_documentation_license.rst
  f1c71b64e1c84e240c7b5aea7331a32a  gcc/ada/doc/share/latex_elements.py
  90adfcde2feb6d6c090c2b18a1578145  gcc/ada/doc/share/sphinx.sty
! bf442e3478574e268c5c8caa98f59095  gcc/ada/einfo-utils.adb
  76b28b93a0162cb31366aec9f77d5717  gcc/ada/einfo-utils.ads
  4f882a8b5e78253d5838b1a83e4af5bb  gcc/ada/einfo.adb
! c62890b0c038e37ff702feede30c7cea  gcc/ada/einfo.ads
  9fb4fb23a55081d07dc554eeb3253f91  gcc/ada/elists.adb
  1d7f8772477453dee268f8697433a589  gcc/ada/elists.ads
  2d6cb36d45dda0bf32d01725709f0007  gcc/ada/elists.h
--- 720,729 ----
  0a025bfec2a94c0fcd11a19d18f6c0c5  gcc/ada/doc/share/gnu_free_documentation_license.rst
  f1c71b64e1c84e240c7b5aea7331a32a  gcc/ada/doc/share/latex_elements.py
  90adfcde2feb6d6c090c2b18a1578145  gcc/ada/doc/share/sphinx.sty
! fee3119058c19cc04299b3c13c34fb19  gcc/ada/einfo-utils.adb
  76b28b93a0162cb31366aec9f77d5717  gcc/ada/einfo-utils.ads
  4f882a8b5e78253d5838b1a83e4af5bb  gcc/ada/einfo.adb
! 045f8ecf4fefc5ba82254175189ec192  gcc/ada/einfo.ads
  9fb4fb23a55081d07dc554eeb3253f91  gcc/ada/elists.adb
  1d7f8772477453dee268f8697433a589  gcc/ada/elists.ads
  2d6cb36d45dda0bf32d01725709f0007  gcc/ada/elists.h
*************** cc3726d13e05b448f2aafd3e2d176496  gcc/ad
*** 787,793 ****
  7151f16c23b394a2f2eef990ebee4e20  gcc/ada/exp_disp.ads
  f8d7c73c2eb136405382e9f889d15683  gcc/ada/exp_dist.adb
  116919038aa6e7d0ec9ce9ab609f0bc2  gcc/ada/exp_dist.ads
! 623e2e99136d92d39e5b0f3277759f6a  gcc/ada/exp_fixd.adb
  9633ee578c6cb9ea5577a5cade68bdcc  gcc/ada/exp_fixd.ads
  c48a8396237679c48ceef2c507661e1a  gcc/ada/exp_imgv.adb
  9fc56117157205ad4de1209b42148d67  gcc/ada/exp_imgv.ads
--- 787,793 ----
  7151f16c23b394a2f2eef990ebee4e20  gcc/ada/exp_disp.ads
  f8d7c73c2eb136405382e9f889d15683  gcc/ada/exp_dist.adb
  116919038aa6e7d0ec9ce9ab609f0bc2  gcc/ada/exp_dist.ads
! d82e2d327d75e250ca7bdd5716c9bf7d  gcc/ada/exp_fixd.adb
  9633ee578c6cb9ea5577a5cade68bdcc  gcc/ada/exp_fixd.ads
  c48a8396237679c48ceef2c507661e1a  gcc/ada/exp_imgv.adb
  9fc56117157205ad4de1209b42148d67  gcc/ada/exp_imgv.ads
*************** ee769a63f7ef20a179accef0a80ef873  gcc/ad
*** 811,824 ****
  52a5741c37559d0398594d7baa1c99ac  gcc/ada/exp_tss.ads
  a55ae41c0e68be209828e4229c2bbae3  gcc/ada/exp_unst.adb
  d2f34876e61000e49299ef9b2569cbbf  gcc/ada/exp_unst.ads
! c9088f6990c221a6225fd2db9e59df2c  gcc/ada/exp_util.adb
  24baec8a8e8188bc72055a6a83ac20fb  gcc/ada/exp_util.ads
  46d0480b64db4c72cf1f08b18e3c33cf  gcc/ada/expander.adb
  53bb0eb5c4feebf8b5fbef639f5827bd  gcc/ada/expander.ads
  b38851c9b7a0167a71b96e69b7c86fb1  gcc/ada/expect.c
  df55beccdf002ea7f1c083561caee63c  gcc/ada/fe.h
  e0c5e28f92b1d5fad283ec608aceb807  gcc/ada/final.c
! 7eeeb784ce4bf239f2e60e0a5ca7cc25  gcc/ada/fmap.adb
  20a76d444ed38bb313845251679b904a  gcc/ada/fmap.ads
  13ef835624590a9ba64dd6b4d131c22a  gcc/ada/fname-sf.adb
  4132ae09b3f8d374f31e34bfa2c3c6a4  gcc/ada/fname-sf.ads
--- 811,824 ----
  52a5741c37559d0398594d7baa1c99ac  gcc/ada/exp_tss.ads
  a55ae41c0e68be209828e4229c2bbae3  gcc/ada/exp_unst.adb
  d2f34876e61000e49299ef9b2569cbbf  gcc/ada/exp_unst.ads
! 1ca4619225f7904dbe870fa84f33746f  gcc/ada/exp_util.adb
  24baec8a8e8188bc72055a6a83ac20fb  gcc/ada/exp_util.ads
  46d0480b64db4c72cf1f08b18e3c33cf  gcc/ada/expander.adb
  53bb0eb5c4feebf8b5fbef639f5827bd  gcc/ada/expander.ads
  b38851c9b7a0167a71b96e69b7c86fb1  gcc/ada/expect.c
  df55beccdf002ea7f1c083561caee63c  gcc/ada/fe.h
  e0c5e28f92b1d5fad283ec608aceb807  gcc/ada/final.c
! 3fbc96b9db4d0939c4d0bee6e1efd066  gcc/ada/fmap.adb
  20a76d444ed38bb313845251679b904a  gcc/ada/fmap.ads
  13ef835624590a9ba64dd6b4d131c22a  gcc/ada/fname-sf.adb
  4132ae09b3f8d374f31e34bfa2c3c6a4  gcc/ada/fname-sf.ads
*************** e0c5e28f92b1d5fad283ec608aceb807  gcc/ad
*** 826,832 ****
  576d7463667fc4c859a05f9e19146427  gcc/ada/fname-uf.ads
  ec7cf235c00294fe67198b9bf264f3d9  gcc/ada/fname.adb
  5ef403dc7e6540ad58ec4ccec10de65c  gcc/ada/fname.ads
! c79c1c9f404c173669ce13802612cf8f  gcc/ada/freeze.adb
  0cfb73b82bc6277eb801329c392229d2  gcc/ada/freeze.ads
  5f9e0e6d3b96540c54ba9e0ca89941e4  gcc/ada/frontend.adb
  6f776be1d84e9d8c996b576c19a4349f  gcc/ada/frontend.ads
--- 826,832 ----
  576d7463667fc4c859a05f9e19146427  gcc/ada/fname-uf.ads
  ec7cf235c00294fe67198b9bf264f3d9  gcc/ada/fname.adb
  5ef403dc7e6540ad58ec4ccec10de65c  gcc/ada/fname.ads
! 23164f1041375dce6fd4430bb4601931  gcc/ada/freeze.adb
  0cfb73b82bc6277eb801329c392229d2  gcc/ada/freeze.ads
  5f9e0e6d3b96540c54ba9e0ca89941e4  gcc/ada/frontend.adb
  6f776be1d84e9d8c996b576c19a4349f  gcc/ada/frontend.ads
*************** becebc263397cb3c5be3c7083cf21c55  gcc/ad
*** 849,855 ****
  a74b4504c5ad4ed4e963f0691c289b40  gcc/ada/gcc-interface/system.ads
  b350a6fd65cafe8bd47dc42192437310  gcc/ada/gcc-interface/targtyps.cc
  d7f5374a67a40e0ebecaf6ba95369af1  gcc/ada/gcc-interface/trans.cc
! 0754fed833cdb80b248b14e2f65c7229  gcc/ada/gcc-interface/utils.cc
  0b638ee76fd250092e4f0077d2deb899  gcc/ada/gcc-interface/utils2.cc
  7f457b4dfdc40122d286fdd928bdad0b  gcc/ada/gen_il-fields.ads
  71efadf4579df758ff3d06f657397f1f  gcc/ada/gen_il-gen-gen_entities.adb
--- 849,855 ----
  a74b4504c5ad4ed4e963f0691c289b40  gcc/ada/gcc-interface/system.ads
  b350a6fd65cafe8bd47dc42192437310  gcc/ada/gcc-interface/targtyps.cc
  d7f5374a67a40e0ebecaf6ba95369af1  gcc/ada/gcc-interface/trans.cc
! 266cd844950bb1df51718e65e78177aa  gcc/ada/gcc-interface/utils.cc
  0b638ee76fd250092e4f0077d2deb899  gcc/ada/gcc-interface/utils2.cc
  7f457b4dfdc40122d286fdd928bdad0b  gcc/ada/gen_il-fields.ads
  71efadf4579df758ff3d06f657397f1f  gcc/ada/gen_il-gen-gen_entities.adb
*************** be98a1e6f04922fb22c79c4540070fe5  gcc/ad
*** 875,881 ****
  917ea7311a30ec4c5cec3e610ca640c2  gcc/ada/gnat2.gpr
  49c5329fd360e2bf4e549bc7de93aab7  gcc/ada/gnat_cuda.adb
  de69fc271ce889490809004600fcac0f  gcc/ada/gnat_cuda.ads
! 4700c67f2df7fb60b4eee5d14061143f  gcc/ada/gnat_rm.texi
  fa1f249efe6a66c215950ac5d3c89e30  gcc/ada/gnat_ugn.texi
  957e02fdb4684d592d9172cea8dfb4cb  gcc/ada/gnatbind.adb
  fff8dfca966e9d6f779ce90e57344a0f  gcc/ada/gnatbind.ads
--- 875,881 ----
  917ea7311a30ec4c5cec3e610ca640c2  gcc/ada/gnat2.gpr
  49c5329fd360e2bf4e549bc7de93aab7  gcc/ada/gnat_cuda.adb
  de69fc271ce889490809004600fcac0f  gcc/ada/gnat_cuda.ads
! d7e1b723c1f4358fc995ff9ca981c3ad  gcc/ada/gnat_rm.texi
  fa1f249efe6a66c215950ac5d3c89e30  gcc/ada/gnat_ugn.texi
  957e02fdb4684d592d9172cea8dfb4cb  gcc/ada/gnatbind.adb
  fff8dfca966e9d6f779ce90e57344a0f  gcc/ada/gnatbind.ads
*************** b11be01de6f079f6e83c844e9fdaf759  gcc/ad
*** 1089,1095 ****
  4dea01d120792b0f35f1aec470e7fdfb  gcc/ada/libgnarl/s-taprop__linux.adb
  19097481817acd9d3de1ed84aa731c02  gcc/ada/libgnarl/s-taprop__mingw.adb
  139d97e773970f5955d60a4af95755cb  gcc/ada/libgnarl/s-taprop__posix.adb
! 4d54a3a29c5651e04fc461129e1eb163  gcc/ada/libgnarl/s-taprop__qnx.adb
  eba7cc72920c9e16506a4955d48cb118  gcc/ada/libgnarl/s-taprop__rtems.adb
  e819a6c285d9c687a6d0f49862d0ec7a  gcc/ada/libgnarl/s-taprop__solaris.adb
  2fdbab980ce8e36304f943e853487d36  gcc/ada/libgnarl/s-taprop__vxworks.adb
--- 1089,1095 ----
  4dea01d120792b0f35f1aec470e7fdfb  gcc/ada/libgnarl/s-taprop__linux.adb
  19097481817acd9d3de1ed84aa731c02  gcc/ada/libgnarl/s-taprop__mingw.adb
  139d97e773970f5955d60a4af95755cb  gcc/ada/libgnarl/s-taprop__posix.adb
! 200878ea37f01f75d839ef9be348b246  gcc/ada/libgnarl/s-taprop__qnx.adb
  eba7cc72920c9e16506a4955d48cb118  gcc/ada/libgnarl/s-taprop__rtems.adb
  e819a6c285d9c687a6d0f49862d0ec7a  gcc/ada/libgnarl/s-taprop__solaris.adb
  2fdbab980ce8e36304f943e853487d36  gcc/ada/libgnarl/s-taprop__vxworks.adb
*************** e294448193cb759e4c1e06d820888165  gcc/ad
*** 2786,2792 ****
  3c65af3e1d391a436f644e2be1ba91eb  gcc/ada/live.ads
  a6232c2c6695f3968d72a36b3644872f  gcc/ada/local_restrict.adb
  5afc39f477386bac6e37e2c654129e5b  gcc/ada/local_restrict.ads
! c0aa0ea596c2f36453ceff3b5fdcd93d  gcc/ada/locales.c
  b3d080be0b0ad10ff0b07cf73c0c08cb  gcc/ada/make.adb
  69fc7bcba1600b07c089e53bfded4000  gcc/ada/make.ads
  1788022297483d11a7ac5600bb2b5cf6  gcc/ada/make_util.adb
--- 2786,2792 ----
  3c65af3e1d391a436f644e2be1ba91eb  gcc/ada/live.ads
  a6232c2c6695f3968d72a36b3644872f  gcc/ada/local_restrict.adb
  5afc39f477386bac6e37e2c654129e5b  gcc/ada/local_restrict.ads
! 7be021f979d35c34ee456d4d45dea801  gcc/ada/locales.c
  b3d080be0b0ad10ff0b07cf73c0c08cb  gcc/ada/make.adb
  69fc7bcba1600b07c089e53bfded4000  gcc/ada/make.ads
  1788022297483d11a7ac5600bb2b5cf6  gcc/ada/make_util.adb
*************** cf568cc3ccf1e3077d0124147b5eb011  gcc/ad
*** 2831,2837 ****
  726417eeba8f4e1ae6310601195b55e4  gcc/ada/par-ch13.adb
  ed9e0f33947385dfddd6c98bc7c51a92  gcc/ada/par-ch2.adb
  20f2d1c603041e115215f1f16853c42c  gcc/ada/par-ch3.adb
! a39be401cc0a29fd9a0e8a533688c6e4  gcc/ada/par-ch4.adb
  63a4bee77501bbe0cb76503f22893cbd  gcc/ada/par-ch5.adb
  f7eb7f9dffd732f17489bd09047572f9  gcc/ada/par-ch6.adb
  156c49bfe462052c8f4cfb04419e91ee  gcc/ada/par-ch7.adb
--- 2831,2837 ----
  726417eeba8f4e1ae6310601195b55e4  gcc/ada/par-ch13.adb
  ed9e0f33947385dfddd6c98bc7c51a92  gcc/ada/par-ch2.adb
  20f2d1c603041e115215f1f16853c42c  gcc/ada/par-ch3.adb
! 8008dff554d7685ade76fc72487b4a60  gcc/ada/par-ch4.adb
  63a4bee77501bbe0cb76503f22893cbd  gcc/ada/par-ch5.adb
  f7eb7f9dffd732f17489bd09047572f9  gcc/ada/par-ch6.adb
  156c49bfe462052c8f4cfb04419e91ee  gcc/ada/par-ch7.adb
*************** ee1279472214ff7ca5b61685a2ada15f  gcc/ad
*** 2846,2852 ****
  4604f1e5c60129438742f4320d848ce8  gcc/ada/par-util.adb
  b320d7c9a2a8a1bfeb97bc4d96d18b65  gcc/ada/par.adb
  cc0b4ae85eb0edbcce886d13c925cbf3  gcc/ada/par.ads
! b0a53260cce47acbd0de8d046175c63f  gcc/ada/par_sco.adb
  2674a374e947c03703d34f6603994424  gcc/ada/par_sco.ads
  60eed5b3f55a0639b078f452fcdf5cdc  gcc/ada/pprint.adb
  d4e0d990ec706c00861a684898856c8d  gcc/ada/pprint.ads
--- 2846,2852 ----
  4604f1e5c60129438742f4320d848ce8  gcc/ada/par-util.adb
  b320d7c9a2a8a1bfeb97bc4d96d18b65  gcc/ada/par.adb
  cc0b4ae85eb0edbcce886d13c925cbf3  gcc/ada/par.ads
! ab580cbf09f85961d85ea5be3ea8e5a6  gcc/ada/par_sco.adb
  2674a374e947c03703d34f6603994424  gcc/ada/par_sco.ads
  60eed5b3f55a0639b078f452fcdf5cdc  gcc/ada/pprint.adb
  d4e0d990ec706c00861a684898856c8d  gcc/ada/pprint.ads
*************** efb8983a0d800885901944d42ede5985  gcc/ad
*** 2903,2915 ****
  6e34ce648cfc10b24c12b68e0e59dcb8  gcc/ada/sem_ch10.ads
  5980a02146588bf0e31ced2382290670  gcc/ada/sem_ch11.adb
  1b6f89866a5d427002df059be3847d62  gcc/ada/sem_ch11.ads
! c819eb1296bc32ede32c4959c26ad525  gcc/ada/sem_ch12.adb
  f981520c42b732545be8bb5c8813ccfd  gcc/ada/sem_ch12.ads
! d6ef5724397901e11d6ea6485aa07816  gcc/ada/sem_ch13.adb
  42a7b1073e168e8be85f2203fbddd148  gcc/ada/sem_ch13.ads
  14326c522718c8cb8415b13a79c07972  gcc/ada/sem_ch2.adb
  2471d629be4739ff5135aa87a2ec9166  gcc/ada/sem_ch2.ads
! 2713817f20c172e0a9f00c5360b662b8  gcc/ada/sem_ch3.adb
  76abe89b089728c6eaca6f7593348732  gcc/ada/sem_ch3.ads
  653f5332c66bb880af0f354966c2ee7d  gcc/ada/sem_ch4.adb
  adba03aae1f439b9e9db8cea05d8e03f  gcc/ada/sem_ch4.ads
--- 2903,2915 ----
  6e34ce648cfc10b24c12b68e0e59dcb8  gcc/ada/sem_ch10.ads
  5980a02146588bf0e31ced2382290670  gcc/ada/sem_ch11.adb
  1b6f89866a5d427002df059be3847d62  gcc/ada/sem_ch11.ads
! e0be4107974a73e2585447a532b6d50f  gcc/ada/sem_ch12.adb
  f981520c42b732545be8bb5c8813ccfd  gcc/ada/sem_ch12.ads
! 334e2dbdd3a003c4678f8a6afa7a65a6  gcc/ada/sem_ch13.adb
  42a7b1073e168e8be85f2203fbddd148  gcc/ada/sem_ch13.ads
  14326c522718c8cb8415b13a79c07972  gcc/ada/sem_ch2.adb
  2471d629be4739ff5135aa87a2ec9166  gcc/ada/sem_ch2.ads
! 20cf3666c4848c38abeebc0c1cd30f04  gcc/ada/sem_ch3.adb
  76abe89b089728c6eaca6f7593348732  gcc/ada/sem_ch3.ads
  653f5332c66bb880af0f354966c2ee7d  gcc/ada/sem_ch4.adb
  adba03aae1f439b9e9db8cea05d8e03f  gcc/ada/sem_ch4.ads
*************** e8573b06cd7059d6bbde030175ab1a71  gcc/ad
*** 2917,2925 ****
  ec8d5a42c27c46e4969c16d6e18ed276  gcc/ada/sem_ch5.ads
  9c8edc8418e17cd1a5fbd65b77454574  gcc/ada/sem_ch6.adb
  165c2ff9990d74ba204881b7983566c7  gcc/ada/sem_ch6.ads
! 3cd25a6cb22852e2cb118d3576b05bdc  gcc/ada/sem_ch7.adb
  24a1265e6a25756265643858abcf7ded  gcc/ada/sem_ch7.ads
! 1508bb5a232d3469fdb90c7970c4be40  gcc/ada/sem_ch8.adb
  f0b4e317e5d5515a6ec337bc5acf5fe0  gcc/ada/sem_ch8.ads
  546c616e1a0e3e76b6220644a605da51  gcc/ada/sem_ch9.adb
  7b283bd6453de444c7075a8c6f215dda  gcc/ada/sem_ch9.ads
--- 2917,2925 ----
  ec8d5a42c27c46e4969c16d6e18ed276  gcc/ada/sem_ch5.ads
  9c8edc8418e17cd1a5fbd65b77454574  gcc/ada/sem_ch6.adb
  165c2ff9990d74ba204881b7983566c7  gcc/ada/sem_ch6.ads
! 094693c34e742c148fdf5b20cf4aca98  gcc/ada/sem_ch7.adb
  24a1265e6a25756265643858abcf7ded  gcc/ada/sem_ch7.ads
! 2c9b2a1f1c1756414860aa04cd92905b  gcc/ada/sem_ch8.adb
  f0b4e317e5d5515a6ec337bc5acf5fe0  gcc/ada/sem_ch8.ads
  546c616e1a0e3e76b6220644a605da51  gcc/ada/sem_ch9.adb
  7b283bd6453de444c7075a8c6f215dda  gcc/ada/sem_ch9.ads
*************** afc0c6c63f3b4af535cbedd72c00385e  gcc/ad
*** 2929,2935 ****
  40937cb7584e45e4c545aa3e4c20fbb2  gcc/ada/sem_disp.ads
  8f677120e0bcecbdcfa5b9c4f44cb282  gcc/ada/sem_dist.adb
  a38c4ce4bc2936bd0a73c28ff1b0df61  gcc/ada/sem_dist.ads
! c2779e0f5c4cde184e5e2152bb8cb24a  gcc/ada/sem_elab.adb
  c074ec7450863300eff2a21c036a624b  gcc/ada/sem_elab.ads
  1623b94463e7ca1496ecde7010db85fc  gcc/ada/sem_elim.adb
  c837e01542a712c622bac1cd152fc080  gcc/ada/sem_elim.ads
--- 2929,2935 ----
  40937cb7584e45e4c545aa3e4c20fbb2  gcc/ada/sem_disp.ads
  8f677120e0bcecbdcfa5b9c4f44cb282  gcc/ada/sem_dist.adb
  a38c4ce4bc2936bd0a73c28ff1b0df61  gcc/ada/sem_dist.ads
! 76aa960b2bd6fb87edbadaba7d90be22  gcc/ada/sem_elab.adb
  c074ec7450863300eff2a21c036a624b  gcc/ada/sem_elab.ads
  1623b94463e7ca1496ecde7010db85fc  gcc/ada/sem_elim.adb
  c837e01542a712c622bac1cd152fc080  gcc/ada/sem_elim.ads
*************** e8e79e2a818321d7816e27eed8d17404  gcc/ad
*** 2939,2945 ****
  66ccba8e3b77fa8d6e0e13f6368d804a  gcc/ada/sem_intr.ads
  4a954a685009a9b0bcf72a8517dc3bdf  gcc/ada/sem_mech.adb
  bcb22deebc83b966e7be367087d9fd7b  gcc/ada/sem_mech.ads
! 32b2a28c2f2994ed2fcd7d6ae913b861  gcc/ada/sem_prag.adb
  d16256f1e0a8b84763e3ccc0653e1c4b  gcc/ada/sem_prag.ads
  4ec88812296adfa216b478a7141c3990  gcc/ada/sem_res.adb
  bb01f11ceaa352a8b99f95fcbcfe97d9  gcc/ada/sem_res.ads
--- 2939,2945 ----
  66ccba8e3b77fa8d6e0e13f6368d804a  gcc/ada/sem_intr.ads
  4a954a685009a9b0bcf72a8517dc3bdf  gcc/ada/sem_mech.adb
  bcb22deebc83b966e7be367087d9fd7b  gcc/ada/sem_mech.ads
! 29b8a2860cd4db4784ebf12088d434ee  gcc/ada/sem_prag.adb
  d16256f1e0a8b84763e3ccc0653e1c4b  gcc/ada/sem_prag.ads
  4ec88812296adfa216b478a7141c3990  gcc/ada/sem_res.adb
  bb01f11ceaa352a8b99f95fcbcfe97d9  gcc/ada/sem_res.ads
*************** bb01f11ceaa352a8b99f95fcbcfe97d9  gcc/ad
*** 2947,2955 ****
  db6f5a37bd59fd83ff3286e71ab985fe  gcc/ada/sem_scil.ads
  224e89cdc39291b2a52f3e96e76cc3aa  gcc/ada/sem_smem.adb
  89d73c108bd8921f6d6cd84d98726ea5  gcc/ada/sem_smem.ads
! d0a2f5b2f65a874363f7fbe2b9a79f8b  gcc/ada/sem_type.adb
  dee50852181adfada17fb5b7423ed973  gcc/ada/sem_type.ads
! dd5d990522a207bc6cb8eca47211cc5b  gcc/ada/sem_util.adb
  4c258be138ab7760a8329aa8913fe358  gcc/ada/sem_util.ads
  9668d6a37fe84f41a81a7ffcb66d5ecc  gcc/ada/sem_warn.adb
  441e0f80657ef72324e40dd20cebfc82  gcc/ada/sem_warn.ads
--- 2947,2955 ----
  db6f5a37bd59fd83ff3286e71ab985fe  gcc/ada/sem_scil.ads
  224e89cdc39291b2a52f3e96e76cc3aa  gcc/ada/sem_smem.adb
  89d73c108bd8921f6d6cd84d98726ea5  gcc/ada/sem_smem.ads
! 1f62b0ecc5ebe8e9b39be89d56094a6c  gcc/ada/sem_type.adb
  dee50852181adfada17fb5b7423ed973  gcc/ada/sem_type.ads
! 67437f4a2b6765741ec3233490f36686  gcc/ada/sem_util.adb
  4c258be138ab7760a8329aa8913fe358  gcc/ada/sem_util.ads
  9668d6a37fe84f41a81a7ffcb66d5ecc  gcc/ada/sem_warn.adb
  441e0f80657ef72324e40dd20cebfc82  gcc/ada/sem_warn.ads
*************** ceaa52edf6355622601cd30f7c096b06  gcc/ad
*** 3009,3016 ****
  7e7afcf1b2687d2270ec21617a7bb854  gcc/ada/switch.adb
  3ce7cd08e301dd2487e065308c9e9fe9  gcc/ada/switch.ads
  1c5f4065ed9bfb55ca7167c50baf2159  gcc/ada/sysdep.c
! 66a18e98cd30d5801e1325734844df88  gcc/ada/table.adb
! e8d9b41a7175ccacacbfccec989ad758  gcc/ada/table.ads
  9f45bf3ee4cf0a6b06c0b5cc6a4830a7  gcc/ada/targext.c
  597006ac6d907cb7a626caa301c78f91  gcc/ada/targparm.adb
  d9d7a0f9b8ac29d8f1e477d6b53076c1  gcc/ada/targparm.ads
--- 3009,3016 ----
  7e7afcf1b2687d2270ec21617a7bb854  gcc/ada/switch.adb
  3ce7cd08e301dd2487e065308c9e9fe9  gcc/ada/switch.ads
  1c5f4065ed9bfb55ca7167c50baf2159  gcc/ada/sysdep.c
! 69800f63276ca2e455c6b79cbfae2d07  gcc/ada/table.adb
! 6749edbf6142a410672c491892a48283  gcc/ada/table.ads
  9f45bf3ee4cf0a6b06c0b5cc6a4830a7  gcc/ada/targext.c
  597006ac6d907cb7a626caa301c78f91  gcc/ada/targparm.adb
  d9d7a0f9b8ac29d8f1e477d6b53076c1  gcc/ada/targparm.ads
*************** dc5d5c32319eb04bed4f17e183ddeeab  gcc/ba
*** 3183,3199 ****
  919e197f7b89caf16d31f0882964adfa  gcc/bbitmap.h
  bb79e5d725623239adccc4b97ad421cb  gcc/bitmap.cc
  fe292df4b7f3e3ef7c0b8305084b6844  gcc/bitmap.h
! 8ab376ca331fbf6857570a1f5f067f2f  gcc/btfout.cc
  5423cf9cfc9de5ca30bc45842efead77  gcc/builtin-attrs.def
  9b2538f67781c7ccab3891a929caaaf0  gcc/builtin-types.def
  1f5d04ed09772ef8cff71c5a2d838b85  gcc/builtins.cc
  52ff6fb92e162a8ad41a1af1dfb0171a  gcc/builtins.def
  08bacecaf5d3527bf3df15480fb78537  gcc/builtins.h
! ba96f214376e0733a4f748ae9c3f6bc5  gcc/c-family/ChangeLog
  ea3fa1f4d7390a105fa3caab4f79aaf7  gcc/c-family/ChangeLog.gimple-classes
  9c7ff39ab2ffc5f0938f59efc3657201  gcc/c-family/c-ada-spec.cc
  4e83011bee68d9607834ed5335191d65  gcc/c-family/c-ada-spec.h
! eab1507c247022223dcdc6d8d8902ff1  gcc/c-family/c-attribs.cc
  c897c985c1212b96852d374531b546a3  gcc/c-family/c-common.cc
  c273c4ad95ccdbfe677146505900c62e  gcc/c-family/c-common.def
  eef2a6baa49f9e2a37689fab581e698b  gcc/c-family/c-common.h
--- 3183,3199 ----
  919e197f7b89caf16d31f0882964adfa  gcc/bbitmap.h
  bb79e5d725623239adccc4b97ad421cb  gcc/bitmap.cc
  fe292df4b7f3e3ef7c0b8305084b6844  gcc/bitmap.h
! ab9fdb6ff2584fb7c564bdd3d5546c02  gcc/btfout.cc
  5423cf9cfc9de5ca30bc45842efead77  gcc/builtin-attrs.def
  9b2538f67781c7ccab3891a929caaaf0  gcc/builtin-types.def
  1f5d04ed09772ef8cff71c5a2d838b85  gcc/builtins.cc
  52ff6fb92e162a8ad41a1af1dfb0171a  gcc/builtins.def
  08bacecaf5d3527bf3df15480fb78537  gcc/builtins.h
! bf1ee20ba886403dce2b3c27578b231f  gcc/c-family/ChangeLog
  ea3fa1f4d7390a105fa3caab4f79aaf7  gcc/c-family/ChangeLog.gimple-classes
  9c7ff39ab2ffc5f0938f59efc3657201  gcc/c-family/c-ada-spec.cc
  4e83011bee68d9607834ed5335191d65  gcc/c-family/c-ada-spec.h
! d44a12a363aa3f6d21f2be5e2ff91306  gcc/c-family/c-attribs.cc
  c897c985c1212b96852d374531b546a3  gcc/c-family/c-common.cc
  c273c4ad95ccdbfe677146505900c62e  gcc/c-family/c-common.def
  eef2a6baa49f9e2a37689fab581e698b  gcc/c-family/c-common.h
*************** a4b7179d2e948bb7586a9143fbe05593  gcc/c-
*** 3207,3213 ****
  c80c4d6e16ab46358143d22a8a146725  gcc/c-family/c-lex.cc
  c880dc584a0fd4908e5df33dd81137b8  gcc/c-family/c-objc.h
  d21f1c18590954a9e3a2f6fe7f9b0641  gcc/c-family/c-omp.cc
! 776207393d40caae814af68da4890af6  gcc/c-family/c-opts.cc
  2f1a14531d3a436ca9f4aad2812c3898  gcc/c-family/c-pch.cc
  6e53d008a0c4738339154c353a50ff0a  gcc/c-family/c-ppoutput.cc
  cfc760e3be8b3db6dfc8fef49282c0aa  gcc/c-family/c-pragma.cc
--- 3207,3213 ----
  c80c4d6e16ab46358143d22a8a146725  gcc/c-family/c-lex.cc
  c880dc584a0fd4908e5df33dd81137b8  gcc/c-family/c-objc.h
  d21f1c18590954a9e3a2f6fe7f9b0641  gcc/c-family/c-omp.cc
! 6e8a9908a506a5d75b08c9aa99f39320  gcc/c-family/c-opts.cc
  2f1a14531d3a436ca9f4aad2812c3898  gcc/c-family/c-pch.cc
  6e53d008a0c4738339154c353a50ff0a  gcc/c-family/c-ppoutput.cc
  cfc760e3be8b3db6dfc8fef49282c0aa  gcc/c-family/c-pragma.cc
*************** be7f7be2479df6718f5fff59312996f8  gcc/c-
*** 3232,3253 ****
  ac5daa4f7d7788a3f68dde7fe7a25316  gcc/c-family/known-headers.h
  f09c431056b5138e7cfe8376e05de9a6  gcc/c-family/name-hint.h
  d71f74b5b48d9ec5e4e6463e7330121d  gcc/c-family/stub-objc.cc
! 0a856962c00bda3179d8e50ce7b2f602  gcc/c/ChangeLog
  a1ab86dd79d40d45839823afe798673a  gcc/c/Make-lang.in
  f1e5593aebd5cffb4b3cbffe6bd0860a  gcc/c/c-aux-info.cc
  178d24653bb20936d73bad078e70763c  gcc/c/c-convert.cc
! 01761947c9bd059bdc1bd87a0da2c199  gcc/c/c-decl.cc
  10e620f790089957c832097206d0d6d6  gcc/c/c-errors.cc
  837fc5f348c64d1c90a4430cc0fb3662  gcc/c/c-fold.cc
  d9c0725d061adffdf400457d91be3aed  gcc/c/c-lang.cc
  4be9de2ca25340adb8f350478db6a3d8  gcc/c/c-lang.h
  c2644975781d9f78ae4c387d01a3270e  gcc/c/c-objc-common.cc
  757f583d06a3ec98336adbfc92b4e6a8  gcc/c/c-objc-common.h
! 588e0cea349cd1808a1ebc978d205ccf  gcc/c/c-parser.cc
  4cd2bf432e96f0de530e0ea4e8b44aa2  gcc/c/c-parser.h
  9179f46b6a06c7d734278f5ce2c55883  gcc/c/c-tree.def
! 3b6b366820f49cf65c437c77b755d1f9  gcc/c/c-tree.h
! 127a518f5994e97f2bd85f26598e50df  gcc/c/c-typeck.cc
  cd371895d730dd64e947066b2e4378f8  gcc/c/config-lang.in
  1bd76a24d1322659f048abe2272a6f34  gcc/c/gccspec.cc
  1ed203cdf15f14eb7bfe0eaabf41f503  gcc/c/gimple-parser.cc
--- 3232,3253 ----
  ac5daa4f7d7788a3f68dde7fe7a25316  gcc/c-family/known-headers.h
  f09c431056b5138e7cfe8376e05de9a6  gcc/c-family/name-hint.h
  d71f74b5b48d9ec5e4e6463e7330121d  gcc/c-family/stub-objc.cc
! 7d024d3274247a7a2d34ca3bec587ee5  gcc/c/ChangeLog
  a1ab86dd79d40d45839823afe798673a  gcc/c/Make-lang.in
  f1e5593aebd5cffb4b3cbffe6bd0860a  gcc/c/c-aux-info.cc
  178d24653bb20936d73bad078e70763c  gcc/c/c-convert.cc
! f752ad8376c3c65fa3b8a8765f8c3c80  gcc/c/c-decl.cc
  10e620f790089957c832097206d0d6d6  gcc/c/c-errors.cc
  837fc5f348c64d1c90a4430cc0fb3662  gcc/c/c-fold.cc
  d9c0725d061adffdf400457d91be3aed  gcc/c/c-lang.cc
  4be9de2ca25340adb8f350478db6a3d8  gcc/c/c-lang.h
  c2644975781d9f78ae4c387d01a3270e  gcc/c/c-objc-common.cc
  757f583d06a3ec98336adbfc92b4e6a8  gcc/c/c-objc-common.h
! 1183dfb2453d4ffc484127c7bf73e3cb  gcc/c/c-parser.cc
  4cd2bf432e96f0de530e0ea4e8b44aa2  gcc/c/c-parser.h
  9179f46b6a06c7d734278f5ce2c55883  gcc/c/c-tree.def
! 2ff9ae091101b4377a806073d2e89d3f  gcc/c/c-tree.h
! c8c6332880cfcecb52041becf6633c59  gcc/c/c-typeck.cc
  cd371895d730dd64e947066b2e4378f8  gcc/c/config-lang.in
  1bd76a24d1322659f048abe2272a6f34  gcc/c/gccspec.cc
  1ed203cdf15f14eb7bfe0eaabf41f503  gcc/c/gimple-parser.cc
*************** bbad65845fcf9cdbc5137d96f92eacab  gcc/cf
*** 3277,3289 ****
  7c2358ab451ca13a153f64b7682d772a  gcc/cfgloopmanip.h
  86fd277253913430380bc5d51e4b395b  gcc/cfgrtl.cc
  132f0eb682ec622dc563cfc697da1fb8  gcc/cfgrtl.h
! 599612d60d4d908603912594ba7e7db7  gcc/cgraph.cc
! adc277e694f0339369a2de3d3e50d400  gcc/cgraph.h
  5fa2e94f261a8a6fc0d80b1c4b227d25  gcc/cgraphbuild.cc
  f260ce27ba36b1e6d964fe6ba1552cb6  gcc/cgraphclones.cc
  4e2f7703a23f2c2483098ddb6edac479  gcc/cgraphunit.cc
  bd38ef84be4e8351bde3ee96f062c357  gcc/cif-code.def
! 47a8951282e263cd72ba0b14a4d07c3f  gcc/cobol/ChangeLog
  3702fe656ebbd5b61ccb5f70dfd85ed4  gcc/cobol/Make-lang.in
  0a84e784d2bc4066654d2377fc6a2930  gcc/cobol/TODO
  b5d944951cc226cf4f33fdd1494aa7e7  gcc/cobol/cbldiag.h
--- 3277,3289 ----
  7c2358ab451ca13a153f64b7682d772a  gcc/cfgloopmanip.h
  86fd277253913430380bc5d51e4b395b  gcc/cfgrtl.cc
  132f0eb682ec622dc563cfc697da1fb8  gcc/cfgrtl.h
! 2e97f6f5f8547ba5f0cdb29ffd470a2d  gcc/cgraph.cc
! b6c3335dfa12561fab963bf22e16df60  gcc/cgraph.h
  5fa2e94f261a8a6fc0d80b1c4b227d25  gcc/cgraphbuild.cc
  f260ce27ba36b1e6d964fe6ba1552cb6  gcc/cgraphclones.cc
  4e2f7703a23f2c2483098ddb6edac479  gcc/cgraphunit.cc
  bd38ef84be4e8351bde3ee96f062c357  gcc/cif-code.def
! 79709c1784dbcec6ee6a3e22ddae41c3  gcc/cobol/ChangeLog
  3702fe656ebbd5b61ccb5f70dfd85ed4  gcc/cobol/Make-lang.in
  0a84e784d2bc4066654d2377fc6a2930  gcc/cobol/TODO
  b5d944951cc226cf4f33fdd1494aa7e7  gcc/cobol/cbldiag.h
*************** f55010fab8b9aabea82c3ac50d031028  gcc/co
*** 3343,3349 ****
  7041e62f0f582b09331732fef4bb9545  gcc/combine-stack-adj.cc
  8db32a2301bfbb3281c1cc38024ad792  gcc/combine.cc
  2b9ccf7fc2473ef7e36aee9bcf170843  gcc/common.md
! 0b6ae6ebc868fe9f9d6dca9d8080e6b4  gcc/common.opt
  ee6af2937fce4a98c406a6da277ef9a6  gcc/common.opt.urls
  26050db921f73fd87b026dc950bde97b  gcc/common/common-target-def.h
  dae02ebe59cdaaf21611ad354e939ca5  gcc/common/common-target.def
--- 3343,3349 ----
  7041e62f0f582b09331732fef4bb9545  gcc/combine-stack-adj.cc
  8db32a2301bfbb3281c1cc38024ad792  gcc/combine.cc
  2b9ccf7fc2473ef7e36aee9bcf170843  gcc/common.md
! 56d47e601720a10d018cb61d42d5a6c6  gcc/common.opt
  ee6af2937fce4a98c406a6da277ef9a6  gcc/common.opt.urls
  26050db921f73fd87b026dc950bde97b  gcc/common/common-target-def.h
  dae02ebe59cdaaf21611ad354e939ca5  gcc/common/common-target.def
*************** b824341b8f6fdb8eb1667425adf63db8  gcc/co
*** 3445,3451 ****
  7cfa3d0cdd28cdcd73a29c2c8a925548  gcc/config/aarch64/aarch64-simd-builtin-types.def
  8f28d55d0c7fc64387352822e99a37ff  gcc/config/aarch64/aarch64-simd-builtins.def
  33ce4a896b77324d9be6448637daf9ca  gcc/config/aarch64/aarch64-simd-pragma-builtins.def
! 127675253d8cfa3e769692c429632d62  gcc/config/aarch64/aarch64-simd.md
  fec3caf088f2add6cefcfb20f6dcae7f  gcc/config/aarch64/aarch64-sme.md
  fa6672290fdf9366d9919defcb7e41d7  gcc/config/aarch64/aarch64-speculation.cc
  9311f63fb41454e9c423862057e8eb6b  gcc/config/aarch64/aarch64-sve-builtins-base.cc
--- 3445,3451 ----
  7cfa3d0cdd28cdcd73a29c2c8a925548  gcc/config/aarch64/aarch64-simd-builtin-types.def
  8f28d55d0c7fc64387352822e99a37ff  gcc/config/aarch64/aarch64-simd-builtins.def
  33ce4a896b77324d9be6448637daf9ca  gcc/config/aarch64/aarch64-simd-pragma-builtins.def
! ce276543a479bdb36dbb958c4e83ce90  gcc/config/aarch64/aarch64-simd.md
  fec3caf088f2add6cefcfb20f6dcae7f  gcc/config/aarch64/aarch64-sme.md
  fa6672290fdf9366d9919defcb7e41d7  gcc/config/aarch64/aarch64-speculation.cc
  9311f63fb41454e9c423862057e8eb6b  gcc/config/aarch64/aarch64-sve-builtins-base.cc
*************** d37f092206fc4c0379cee5e5fc01b654  gcc/co
*** 3760,3768 ****
  6b425f8df921557284017d42be8efc3c  gcc/config/avr/avr-passes.def
  65447cdb57d64c621846dbfaece9c7f6  gcc/config/avr/avr-protos.h
  eb753641e5bf09dbcc2be97e61be8767  gcc/config/avr/avr-stdint.h
! 6e9d57064ae2103a9a3ede91960cf44d  gcc/config/avr/avr.cc
  bee0e6e1aecf816b3bc39ba11e67566f  gcc/config/avr/avr.h
! 8803f3f342c3d9440966c0564a0cd1a3  gcc/config/avr/avr.md
  9b16afc684b8a6d301aa731ed7683f93  gcc/config/avr/avr.opt
  eadbd4a61fec0122a6773c41bee01200  gcc/config/avr/avr.opt.urls
  e29c33fe5d0d32a0d578ef5a092a9836  gcc/config/avr/avrlibc.h
--- 3760,3768 ----
  6b425f8df921557284017d42be8efc3c  gcc/config/avr/avr-passes.def
  65447cdb57d64c621846dbfaece9c7f6  gcc/config/avr/avr-protos.h
  eb753641e5bf09dbcc2be97e61be8767  gcc/config/avr/avr-stdint.h
! 82b5402175d18b85940965f0fea60a3c  gcc/config/avr/avr.cc
  bee0e6e1aecf816b3bc39ba11e67566f  gcc/config/avr/avr.h
! b945bd3677c52afb1d50d329250126cb  gcc/config/avr/avr.md
  9b16afc684b8a6d301aa731ed7683f93  gcc/config/avr/avr.opt
  eadbd4a61fec0122a6773c41bee01200  gcc/config/avr/avr.opt.urls
  e29c33fe5d0d32a0d578ef5a092a9836  gcc/config/avr/avrlibc.h
*************** b395ed990d9e6d7c2698fdd602685d3f  gcc/co
*** 3982,3988 ****
  1dbed4e12cf62ae67464d874f1e2e9e8  gcc/config/gcn/gcn-tables.opt
  ca8c1935ac88d760dc3a5b7e97558f28  gcc/config/gcn/gcn-tables.opt.urls
  23106fa0b82354400a9c82b82a9af33a  gcc/config/gcn/gcn-tree.cc
! 654b7f66a42c9d8a31a94dddbc21e69d  gcc/config/gcn/gcn-valu.md
  f616c40e5e05c278aa8a9e801ea6ea91  gcc/config/gcn/gcn.cc
  686d66a24f66638a6a8dc76ddae3acb6  gcc/config/gcn/gcn.h
  f736fc2e3a86be8105f7e8f77e5460c1  gcc/config/gcn/gcn.md
--- 3982,3988 ----
  1dbed4e12cf62ae67464d874f1e2e9e8  gcc/config/gcn/gcn-tables.opt
  ca8c1935ac88d760dc3a5b7e97558f28  gcc/config/gcn/gcn-tables.opt.urls
  23106fa0b82354400a9c82b82a9af33a  gcc/config/gcn/gcn-tree.cc
! b8f453f14c74890d576f2a901fc2d5a7  gcc/config/gcn/gcn-valu.md
  f616c40e5e05c278aa8a9e801ea6ea91  gcc/config/gcn/gcn.cc
  686d66a24f66638a6a8dc76ddae3acb6  gcc/config/gcn/gcn.h
  f736fc2e3a86be8105f7e8f77e5460c1  gcc/config/gcn/gcn.md
*************** fde5fb5a01b2656dc490a5581799a6b2  gcc/co
*** 4178,4184 ****
  03ca94d6fcaa109c0837ebc3f067eb3f  gcc/config/i386/i386-jit.cc
  1e61c026f5b7b51c6c07bec125bf4fbe  gcc/config/i386/i386-jit.h
  09f791543c9ad5918bde13160f0de1df  gcc/config/i386/i386-modes.def
! a7baecfa5a56ae9dc975477f47e51c9a  gcc/config/i386/i386-options.cc
  636d7cce4cd0b632fee9d490d15da86b  gcc/config/i386/i386-options.h
  02c486451c524cfc143358e07b88cd70  gcc/config/i386/i386-opts.h
  3c7d0006f2f31d8607f2c9e74557fbee  gcc/config/i386/i386-passes.def
--- 4178,4184 ----
  03ca94d6fcaa109c0837ebc3f067eb3f  gcc/config/i386/i386-jit.cc
  1e61c026f5b7b51c6c07bec125bf4fbe  gcc/config/i386/i386-jit.h
  09f791543c9ad5918bde13160f0de1df  gcc/config/i386/i386-modes.def
! a9cacf6e415119ba617274c394a15b3d  gcc/config/i386/i386-options.cc
  636d7cce4cd0b632fee9d490d15da86b  gcc/config/i386/i386-options.h
  02c486451c524cfc143358e07b88cd70  gcc/config/i386/i386-opts.h
  3c7d0006f2f31d8607f2c9e74557fbee  gcc/config/i386/i386-passes.def
*************** a7baecfa5a56ae9dc975477f47e51c9a  gcc/co
*** 4186,4194 ****
  5b778b3296ea91dab0ca82338ca6828d  gcc/config/i386/i386-rust-and-jit.inc
  b19c27e8a900f9eeb7d73e2bb4b8d313  gcc/config/i386/i386-rust.cc
  24065393854cd1e08e3285bd707210fe  gcc/config/i386/i386-rust.h
! ea39365f23f9f603132fcc8d70aa9d63  gcc/config/i386/i386.cc
  532590c62b232e0546b5d8396d44c6b7  gcc/config/i386/i386.h
! 07cb47bb7a1ed7c5918026f9c7f95ced  gcc/config/i386/i386.md
  079c7adc6dcd21f8ccfb4c0135f16460  gcc/config/i386/i386.opt
  ae2f0e6cc1882dbf736469a6378cb3d1  gcc/config/i386/i386.opt.urls
  f22876926ff4a2cb67b105ac266c72ea  gcc/config/i386/i386elf.h
--- 4186,4194 ----
  5b778b3296ea91dab0ca82338ca6828d  gcc/config/i386/i386-rust-and-jit.inc
  b19c27e8a900f9eeb7d73e2bb4b8d313  gcc/config/i386/i386-rust.cc
  24065393854cd1e08e3285bd707210fe  gcc/config/i386/i386-rust.h
! 24c863315a4ba6b94189d6cf5f6a33e2  gcc/config/i386/i386.cc
  532590c62b232e0546b5d8396d44c6b7  gcc/config/i386/i386.h
! e12d1ce6a257756bf9d6328808bbfdd9  gcc/config/i386/i386.md
  079c7adc6dcd21f8ccfb4c0135f16460  gcc/config/i386/i386.opt
  ae2f0e6cc1882dbf736469a6378cb3d1  gcc/config/i386/i386.opt.urls
  f22876926ff4a2cb67b105ac266c72ea  gcc/config/i386/i386elf.h
*************** de4e89bc042c6bc7eb093bda5d33a266  gcc/co
*** 4251,4257 ****
  380f2e50c7d803059b0e7617da00460f  gcc/config/i386/sm4intrin.h
  a24296639492577352dd1309b136bc9a  gcc/config/i386/smmintrin.h
  f98c4d94bf04187a2905e9f4ce7d589b  gcc/config/i386/sol2.h
! b00a4b731f3642fa61d8b7ccd4ceed0a  gcc/config/i386/sse.md
  7c6ff828c11c2892168a2e450559dcb6  gcc/config/i386/ssemath.h
  7ada9f54207701e1d29fd03ea990e163  gcc/config/i386/stringop.def
  9f75a2e9a9bf20db0bef264cabe77a29  gcc/config/i386/subst.md
--- 4251,4257 ----
  380f2e50c7d803059b0e7617da00460f  gcc/config/i386/sm4intrin.h
  a24296639492577352dd1309b136bc9a  gcc/config/i386/smmintrin.h
  f98c4d94bf04187a2905e9f4ce7d589b  gcc/config/i386/sol2.h
! c21e362d1f99a6ed46b2e1e6cdc77022  gcc/config/i386/sse.md
  7c6ff828c11c2892168a2e450559dcb6  gcc/config/i386/ssemath.h
  7ada9f54207701e1d29fd03ea990e163  gcc/config/i386/stringop.def
  9f75a2e9a9bf20db0bef264cabe77a29  gcc/config/i386/subst.md
*************** a61fbfd9ac48f94f17ccd936a484b2c8  gcc/co
*** 4394,4404 ****
  3f45bbd3523fe62285eaea00e6ca33a5  gcc/config/loongarch/genopts/genstr.sh
  4dc5332a8742afccaccecc9435f3a90a  gcc/config/loongarch/genopts/isa-evolution.in
  f53279d5b7e936d4ca79a38f0268b4cd  gcc/config/loongarch/genopts/loongarch-strings
! c69ef27c10b319a5443289af516f40b8  gcc/config/loongarch/genopts/loongarch.opt.in
  dfcc88ca848e0510d6a048cef812a984  gcc/config/loongarch/gnu-user.h
  0214c19eeeeb90d46d358333d5381814  gcc/config/loongarch/la464.md
  2da06c6340275c1c0670ab82a7252f77  gcc/config/loongarch/larchintrin.h
! e4c7f558f2f3e9c3e521ecdb82b64b40  gcc/config/loongarch/lasx.md
  64deba47bb6c4537af9a962db8e160d1  gcc/config/loongarch/lasxintrin.h
  a11605122c3f864d3527acf829c67179  gcc/config/loongarch/linux.h
  ac0512e8b259ed63d386edaa0457a5ad  gcc/config/loongarch/loongarch-builtins.cc
--- 4394,4404 ----
  3f45bbd3523fe62285eaea00e6ca33a5  gcc/config/loongarch/genopts/genstr.sh
  4dc5332a8742afccaccecc9435f3a90a  gcc/config/loongarch/genopts/isa-evolution.in
  f53279d5b7e936d4ca79a38f0268b4cd  gcc/config/loongarch/genopts/loongarch-strings
! e3b42a852449963bd9c243b0491ada0c  gcc/config/loongarch/genopts/loongarch.opt.in
  dfcc88ca848e0510d6a048cef812a984  gcc/config/loongarch/gnu-user.h
  0214c19eeeeb90d46d358333d5381814  gcc/config/loongarch/la464.md
  2da06c6340275c1c0670ab82a7252f77  gcc/config/loongarch/larchintrin.h
! 4b8507766acb32c5fff10254b4b1b88d  gcc/config/loongarch/lasx.md
  64deba47bb6c4537af9a962db8e160d1  gcc/config/loongarch/lasxintrin.h
  a11605122c3f864d3527acf829c67179  gcc/config/loongarch/linux.h
  ac0512e8b259ed63d386edaa0457a5ad  gcc/config/loongarch/loongarch-builtins.cc
*************** ff10ba24a7f588f5d1bfbc386be0a309  gcc/co
*** 4418,4437 ****
  d7cf3f5e6d8c9402706533b8bbd7093d  gcc/config/loongarch/loongarch-modes.def
  d3ad067b1fa15bbce42fd3cc4499966e  gcc/config/loongarch/loongarch-opts.cc
  084ba7e2ad2ac804b5f596bca0df06b3  gcc/config/loongarch/loongarch-opts.h
! cc4aae9b316ff2da2b7f2cb5709c1163  gcc/config/loongarch/loongarch-protos.h
  c72c4d71f42573934ede3a3fe4e132b1  gcc/config/loongarch/loongarch-str.h
  a8cd9a4a3d712802475e91e0ec9a3274  gcc/config/loongarch/loongarch-target-attr.cc
  f539c2da7e8d7a3ef7c741bceee19eed  gcc/config/loongarch/loongarch-tune.h
! ec50e2fbf3c40c3826a6c3f37d02a59e  gcc/config/loongarch/loongarch.cc
  d4fcc746efc8475a01557c5c09179c9a  gcc/config/loongarch/loongarch.h
! 5f744a937e0a5911106cc265d8348b0b  gcc/config/loongarch/loongarch.md
! 7eb1817de89953d405ead07dfb2c5316  gcc/config/loongarch/loongarch.opt
! 3e1c4af9b4ae813a611788681e7934f1  gcc/config/loongarch/loongarch.opt.urls
! a1ceaab52de5f1950f6c6b63c5a718ea  gcc/config/loongarch/lsx.md
  429434e5f1e9f9afc839f4409102d5ea  gcc/config/loongarch/lsxintrin.h
  5a232a75001e3db7ee3e491afdfae629  gcc/config/loongarch/musl.h
  b060a0b1a295190643157fde3f8ecfc2  gcc/config/loongarch/predicates.md
! 3d93d4fcfba1009a5c6603db8dbef8a0  gcc/config/loongarch/simd.md
  0e1638a9f434cbb353f1b31e3dc6683b  gcc/config/loongarch/sync.md
  e2aad9f2fd1ee2a4668948f381da109c  gcc/config/loongarch/t-linux
  4143126e9ad08f12c1a4555c0f87948d  gcc/config/loongarch/t-loongarch
--- 4418,4437 ----
  d7cf3f5e6d8c9402706533b8bbd7093d  gcc/config/loongarch/loongarch-modes.def
  d3ad067b1fa15bbce42fd3cc4499966e  gcc/config/loongarch/loongarch-opts.cc
  084ba7e2ad2ac804b5f596bca0df06b3  gcc/config/loongarch/loongarch-opts.h
! 9b41ec5d5ef71ae3a468aab574ba2469  gcc/config/loongarch/loongarch-protos.h
  c72c4d71f42573934ede3a3fe4e132b1  gcc/config/loongarch/loongarch-str.h
  a8cd9a4a3d712802475e91e0ec9a3274  gcc/config/loongarch/loongarch-target-attr.cc
  f539c2da7e8d7a3ef7c741bceee19eed  gcc/config/loongarch/loongarch-tune.h
! 3933ee7206f08eea43a4dd60be93feb3  gcc/config/loongarch/loongarch.cc
  d4fcc746efc8475a01557c5c09179c9a  gcc/config/loongarch/loongarch.h
! c8a7e0ed33060af80085e6abfcd8720f  gcc/config/loongarch/loongarch.md
! 8f1046a4d0739e3dafbb7e4db3055397  gcc/config/loongarch/loongarch.opt
! e5595d4b88b68429f6fe778dc601f49e  gcc/config/loongarch/loongarch.opt.urls
! 33106e72929bb187a7c4f12d69d1f0bb  gcc/config/loongarch/lsx.md
  429434e5f1e9f9afc839f4409102d5ea  gcc/config/loongarch/lsxintrin.h
  5a232a75001e3db7ee3e491afdfae629  gcc/config/loongarch/musl.h
  b060a0b1a295190643157fde3f8ecfc2  gcc/config/loongarch/predicates.md
! f95be1657846ff90106e8941fbdc72de  gcc/config/loongarch/simd.md
  0e1638a9f434cbb353f1b31e3dc6683b  gcc/config/loongarch/sync.md
  e2aad9f2fd1ee2a4668948f381da109c  gcc/config/loongarch/t-linux
  4143126e9ad08f12c1a4555c0f87948d  gcc/config/loongarch/t-loongarch
*************** ccf120397e978f8cd4ed98cbe2c0d4f5  gcc/co
*** 4894,4900 ****
  3d4ef2c5571dbf0e4bb86d09917f7c07  gcc/config/riscv/arch-canonicalize
  111c94b19a4f72afc23ff2b3e44ab780  gcc/config/riscv/autovec-opt.md
  0a8d3bb5c92b40519d869bae882cf263  gcc/config/riscv/autovec.md
! e000ae44a5456f5afdaafc8accc7f582  gcc/config/riscv/bitmanip.md
  3d4917c0a2efee97aaca242060652e02  gcc/config/riscv/constraints.md
  4e0968dc35562b151fd162778542718f  gcc/config/riscv/corev.def
  d404c19d5b1a2aca0a73917bb692bd96  gcc/config/riscv/corev.md
--- 4894,4900 ----
  3d4ef2c5571dbf0e4bb86d09917f7c07  gcc/config/riscv/arch-canonicalize
  111c94b19a4f72afc23ff2b3e44ab780  gcc/config/riscv/autovec-opt.md
  0a8d3bb5c92b40519d869bae882cf263  gcc/config/riscv/autovec.md
! d4306030a8879ce9aa1e6cc18aff56eb  gcc/config/riscv/bitmanip.md
  3d4917c0a2efee97aaca242060652e02  gcc/config/riscv/constraints.md
  4e0968dc35562b151fd162778542718f  gcc/config/riscv/corev.def
  d404c19d5b1a2aca0a73917bb692bd96  gcc/config/riscv/corev.md
*************** bffa0caedd7144aff55c80a16431d1a1  gcc/co
*** 4919,4925 ****
  a3d3fa9142d4e2ed34ead146941c574a  gcc/config/riscv/pic.md
  674baa66306b2b08e1b80995759f5381  gcc/config/riscv/pipeline-checker
  89b6aff0e8d9684c1bb44093123c9eb5  gcc/config/riscv/predicates.md
! fcde47e773f1cfb9f582a606e2890c72  gcc/config/riscv/riscv-avlprop.cc
  179d92544e7a65f0ccf206e876026744  gcc/config/riscv/riscv-bclr-lowest-set-bit.cc
  e54a2d33c6fb9bb0381889dad6fa71d8  gcc/config/riscv/riscv-builtins.cc
  e282802a520f3069e108ad136bd6e2fa  gcc/config/riscv/riscv-c.cc
--- 4919,4925 ----
  a3d3fa9142d4e2ed34ead146941c574a  gcc/config/riscv/pic.md
  674baa66306b2b08e1b80995759f5381  gcc/config/riscv/pipeline-checker
  89b6aff0e8d9684c1bb44093123c9eb5  gcc/config/riscv/predicates.md
! 47128c226cbf453b9816615bc43b879b  gcc/config/riscv/riscv-avlprop.cc
  179d92544e7a65f0ccf206e876026744  gcc/config/riscv/riscv-bclr-lowest-set-bit.cc
  e54a2d33c6fb9bb0381889dad6fa71d8  gcc/config/riscv/riscv-builtins.cc
  e282802a520f3069e108ad136bd6e2fa  gcc/config/riscv/riscv-c.cc
*************** b1bc6d82a24b7b0e658a43956a37419c  gcc/co
*** 4942,4948 ****
  9638ea683767d52ade2e23fff486b0a7  gcc/config/riscv/riscv-opts.h
  c5393897179939c1b5af9631e66d78a8  gcc/config/riscv/riscv-passes.def
  121d0828b2622389b84f15f8664c88d0  gcc/config/riscv/riscv-profiles.def
! 83f06273985dc5f1ef7613b8799f69ce  gcc/config/riscv/riscv-protos.h
  446f0f39c6f980e246ea56f1233e9271  gcc/config/riscv/riscv-scalar-crypto.def
  003d5626ce3adcac7ca55401c7dec2bc  gcc/config/riscv/riscv-selftests.cc
  da4e034d23a8f2754b1dfce0122f286e  gcc/config/riscv/riscv-shorten-memrefs.cc
--- 4942,4948 ----
  9638ea683767d52ade2e23fff486b0a7  gcc/config/riscv/riscv-opts.h
  c5393897179939c1b5af9631e66d78a8  gcc/config/riscv/riscv-passes.def
  121d0828b2622389b84f15f8664c88d0  gcc/config/riscv/riscv-profiles.def
! 30f61243ed67ec80f2fb05a50475bd94  gcc/config/riscv/riscv-protos.h
  446f0f39c6f980e246ea56f1233e9271  gcc/config/riscv/riscv-scalar-crypto.def
  003d5626ce3adcac7ca55401c7dec2bc  gcc/config/riscv/riscv-selftests.cc
  da4e034d23a8f2754b1dfce0122f286e  gcc/config/riscv/riscv-shorten-memrefs.cc
*************** f565a42da3474d73faf1ea727e2d7dcb  gcc/co
*** 4953,4959 ****
  4285d6caea3cccf0e3cfcac93c1ab26e  gcc/config/riscv/riscv-v.cc
  0d419e9df116fed7ce6e0ae15131417e  gcc/config/riscv/riscv-v.h
  c5f3161dedd668dfb126ffb191cfb236  gcc/config/riscv/riscv-vect-permconst.cc
! 1d781df8fdb7dc0f6e332b3fe767ad85  gcc/config/riscv/riscv-vector-builtins-bases.cc
  689f453a4cdf7fa3e64a7f4bfba8f7dd  gcc/config/riscv/riscv-vector-builtins-bases.h
  bdc5f6caf56fd0411faf705e9c32ccd4  gcc/config/riscv/riscv-vector-builtins-functions.def
  278d45dd3b6250781b7481f0bb02266b  gcc/config/riscv/riscv-vector-builtins-shapes.cc
--- 4953,4959 ----
  4285d6caea3cccf0e3cfcac93c1ab26e  gcc/config/riscv/riscv-v.cc
  0d419e9df116fed7ce6e0ae15131417e  gcc/config/riscv/riscv-v.h
  c5f3161dedd668dfb126ffb191cfb236  gcc/config/riscv/riscv-vect-permconst.cc
! 84e4728d93f1871a385271859cdee594  gcc/config/riscv/riscv-vector-builtins-bases.cc
  689f453a4cdf7fa3e64a7f4bfba8f7dd  gcc/config/riscv/riscv-vector-builtins-bases.h
  bdc5f6caf56fd0411faf705e9c32ccd4  gcc/config/riscv/riscv-vector-builtins-functions.def
  278d45dd3b6250781b7481f0bb02266b  gcc/config/riscv/riscv-vector-builtins-shapes.cc
*************** dba94786c1a18e3f5fbcca2b5c0af496  gcc/co
*** 4965,4975 ****
  a8fdfe0455fce7cebbb65a7e70831d8a  gcc/config/riscv/riscv-vector-costs.cc
  2a441fb15ed4d774924fe163f29ccf7a  gcc/config/riscv/riscv-vector-costs.h
  f51037a9e437f8e9ce7215b2da5ad4e2  gcc/config/riscv/riscv-vector-switch.def
! 43a9d94b35a051ed390b5e2c74432d85  gcc/config/riscv/riscv-vsetvl.cc
  d120ed6eb2847b636271b3a1ef82ecbf  gcc/config/riscv/riscv-vsetvl.def
  7082a18dbfc574d47bf71f4d50dd30f9  gcc/config/riscv/riscv-zicfilp.cc
! f78a490a44b63bb125a091e360ace0b0  gcc/config/riscv/riscv.cc
! 0766a701a8c90815575fae86f92cc4a6  gcc/config/riscv/riscv.h
  d83a8ed43f14b803732bc83dfebc7c6d  gcc/config/riscv/riscv.md
  fec1c87bba727131a45d4ec4a9ae5490  gcc/config/riscv/riscv.opt
  d1d34490d8b53ec20d70ed9e2e56e3ab  gcc/config/riscv/riscv.opt.urls
--- 4965,4975 ----
  a8fdfe0455fce7cebbb65a7e70831d8a  gcc/config/riscv/riscv-vector-costs.cc
  2a441fb15ed4d774924fe163f29ccf7a  gcc/config/riscv/riscv-vector-costs.h
  f51037a9e437f8e9ce7215b2da5ad4e2  gcc/config/riscv/riscv-vector-switch.def
! 3d83e85c22d3c9da7a43e8a19a5c8232  gcc/config/riscv/riscv-vsetvl.cc
  d120ed6eb2847b636271b3a1ef82ecbf  gcc/config/riscv/riscv-vsetvl.def
  7082a18dbfc574d47bf71f4d50dd30f9  gcc/config/riscv/riscv-zicfilp.cc
! 61c2df8f149411c5c946da9918990b85  gcc/config/riscv/riscv.cc
! 4b6b168bb5f0a493f2a81f63dff567cf  gcc/config/riscv/riscv.h
  d83a8ed43f14b803732bc83dfebc7c6d  gcc/config/riscv/riscv.md
  fec1c87bba727131a45d4ec4a9ae5490  gcc/config/riscv/riscv.opt
  d1d34490d8b53ec20d70ed9e2e56e3ab  gcc/config/riscv/riscv.opt.urls
*************** fe202105dd9e81b9ce8fdcc11d52c294  gcc/co
*** 5001,5012 ****
  325f22596295559607b476e5a2a4d491  gcc/config/riscv/thead-vector-builtins-functions.def
  bcf728ad2379630774fd5bb529d4ee86  gcc/config/riscv/thead-vector.md
  48f9dcd9a5cd1980bd2db7697cdb717a  gcc/config/riscv/thead.cc
! 95f1bc0c2f6ee30eedf4736408fa4a3b  gcc/config/riscv/thead.md
  27cf4e9b6199721b239c10c84ecdc2e4  gcc/config/riscv/tt-ascalon-d8.md
  b5e46305db1116cc1758b504ea37fe74  gcc/config/riscv/vector-bfloat16.md
  88f7597398d0c8b8b87baba5fd207996  gcc/config/riscv/vector-crypto.md
  272e0e076fad4b77c195a95427b2a0d8  gcc/config/riscv/vector-iterators.md
! aad921b86850f284e3d6fd15eb5feb17  gcc/config/riscv/vector.md
  18d213c106fe52eebc74017d5ff892ce  gcc/config/riscv/xiangshan.md
  0f64aaa114ab62a1a46f7ac422d6a129  gcc/config/riscv/zc.md
  36cba2444ae9c8f107fee34492bd0ed6  gcc/config/riscv/zicond.md
--- 5001,5012 ----
  325f22596295559607b476e5a2a4d491  gcc/config/riscv/thead-vector-builtins-functions.def
  bcf728ad2379630774fd5bb529d4ee86  gcc/config/riscv/thead-vector.md
  48f9dcd9a5cd1980bd2db7697cdb717a  gcc/config/riscv/thead.cc
! 6db368570eae8b4003cba3d4eab94aa9  gcc/config/riscv/thead.md
  27cf4e9b6199721b239c10c84ecdc2e4  gcc/config/riscv/tt-ascalon-d8.md
  b5e46305db1116cc1758b504ea37fe74  gcc/config/riscv/vector-bfloat16.md
  88f7597398d0c8b8b87baba5fd207996  gcc/config/riscv/vector-crypto.md
  272e0e076fad4b77c195a95427b2a0d8  gcc/config/riscv/vector-iterators.md
! 395b25929ee906c435acae8a04bcb635  gcc/config/riscv/vector.md
  18d213c106fe52eebc74017d5ff892ce  gcc/config/riscv/xiangshan.md
  0f64aaa114ab62a1a46f7ac422d6a129  gcc/config/riscv/zc.md
  36cba2444ae9c8f107fee34492bd0ed6  gcc/config/riscv/zicond.md
*************** f154c7dc9175c4e8204205bb4fbd2cbc  gcc/co
*** 5501,5507 ****
  23de1a423f72982c1a7ec04a2cf54364  gcc/config/xtensa/xtensa-protos.h
  49d78213dc9f09252fa92ac80408f9b0  gcc/config/xtensa/xtensa.cc
  1c1ce8236bb94fc6c2784ab209bff598  gcc/config/xtensa/xtensa.h
! 26ea7100705d3ceeb130ed717e6ff1dd  gcc/config/xtensa/xtensa.md
  f0452ea712955ce21c9c149136850780  gcc/config/xtensa/xtensa.opt
  db57d7603312357e8c0cfb21c32353d1  gcc/config/xtensa/xtensa.opt.urls
  e5d39fd574064c8870895192451abcbd  gcc/configure
--- 5501,5507 ----
  23de1a423f72982c1a7ec04a2cf54364  gcc/config/xtensa/xtensa-protos.h
  49d78213dc9f09252fa92ac80408f9b0  gcc/config/xtensa/xtensa.cc
  1c1ce8236bb94fc6c2784ab209bff598  gcc/config/xtensa/xtensa.h
! b233bf2d4575c3be18c67a2b1a1e047d  gcc/config/xtensa/xtensa.md
  f0452ea712955ce21c9c149136850780  gcc/config/xtensa/xtensa.opt
  db57d7603312357e8c0cfb21c32353d1  gcc/config/xtensa/xtensa.opt.urls
  e5d39fd574064c8870895192451abcbd  gcc/configure
*************** ec3aa966ca3fe9c6f84d4378160541b6  gcc/co
*** 5510,5521 ****
  d1bde52b8dee0c0c5506d7e320b1bb61  gcc/context.h
  a9c3cddee4e237141062720b72fe38cd  gcc/convert.cc
  0bc6fd549059c635d460ac1b2be648d8  gcc/convert.h
! 4c457d2efba4a00d086cc7d17cbf9348  gcc/coretypes.h
  086834dbb33047e862ba6b6171eda392  gcc/coroutine-builtins.def
  5d31df44fc0a5b17beb74ce0ff38e214  gcc/coroutine-passes.cc
  02796caeaa2f14f72dc3c9c23cc97dfc  gcc/coverage.cc
  722fb5fda78e55c5af5da72cad78751f  gcc/coverage.h
! 56a291bb0de03a28cc4ef94d98754b21  gcc/cp/ChangeLog
  70c059f2b75a2fc1bb95a526b21b8cd7  gcc/cp/ChangeLog-1993
  7cbd106e10a0ba7c052bee3fe20671c2  gcc/cp/ChangeLog-1994
  3b1e3ed23ad4363f75e6fd2fbb583dee  gcc/cp/ChangeLog-1995
--- 5510,5521 ----
  d1bde52b8dee0c0c5506d7e320b1bb61  gcc/context.h
  a9c3cddee4e237141062720b72fe38cd  gcc/convert.cc
  0bc6fd549059c635d460ac1b2be648d8  gcc/convert.h
! 402be1cc5c0db8155504f7e7e11f469d  gcc/coretypes.h
  086834dbb33047e862ba6b6171eda392  gcc/coroutine-builtins.def
  5d31df44fc0a5b17beb74ce0ff38e214  gcc/coroutine-passes.cc
  02796caeaa2f14f72dc3c9c23cc97dfc  gcc/coverage.cc
  722fb5fda78e55c5af5da72cad78751f  gcc/coverage.h
! 852f6a6e8399c38fe8e71b82690cfec7  gcc/cp/ChangeLog
  70c059f2b75a2fc1bb95a526b21b8cd7  gcc/cp/ChangeLog-1993
  7cbd106e10a0ba7c052bee3fe20671c2  gcc/cp/ChangeLog-1994
  3b1e3ed23ad4363f75e6fd2fbb583dee  gcc/cp/ChangeLog-1995
*************** b7ae95468b0150bbe2b3cba351e96a2c  gcc/cp
*** 5575,5581 ****
  8e454e3f7746836df899a46698f5af3e  gcc/cp/cxx-pretty-print.cc
  2d4d94b8a1d1c1d26764ae93a8039dda  gcc/cp/cxx-pretty-print.h
  c5f1614ded8bb57480eb7d1afecb7c7c  gcc/cp/cxxapi-data.csv
! e83f71db41f5d3f45424a0bb82a44ca9  gcc/cp/decl.cc
  7f116fdc50b24dcb13cdcf096636aef9  gcc/cp/decl.h
  1ad50dbadddadc9085cd8c4db0602941  gcc/cp/decl2.cc
  691a10b3246d19925433648ba9a4ea9a  gcc/cp/dump.cc
--- 5575,5581 ----
  8e454e3f7746836df899a46698f5af3e  gcc/cp/cxx-pretty-print.cc
  2d4d94b8a1d1c1d26764ae93a8039dda  gcc/cp/cxx-pretty-print.h
  c5f1614ded8bb57480eb7d1afecb7c7c  gcc/cp/cxxapi-data.csv
! 42bf63dc3759bb23709892d9c600bcfd  gcc/cp/decl.cc
  7f116fdc50b24dcb13cdcf096636aef9  gcc/cp/decl.h
  1ad50dbadddadc9085cd8c4db0602941  gcc/cp/decl2.cc
  691a10b3246d19925433648ba9a4ea9a  gcc/cp/dump.cc
*************** aaf76a9b03fd0532d2904aef004fd66a  gcc/cp
*** 5595,5614 ****
  6c77b1fab5f6d146677090285a202a50  gcc/cp/mapper-client.h
  44e22b51797f89c9da996523a6d97f1c  gcc/cp/mapper-resolver.cc
  0456b59fb105d3d30371131d063a685a  gcc/cp/method.cc
! e216956d7e2a768856ae121513dc79bb  gcc/cp/module.cc
  6b11f42e6b7d506e0ec6e292677347db  gcc/cp/name-lookup.cc
  6fdcf6a217e83566683fbec935637de3  gcc/cp/name-lookup.h
  e7fe06956aada61bcaae5168ad47a9c1  gcc/cp/operators.def
  813c253a000ee20d8d6598f56edc400e  gcc/cp/optimize.cc
! d83911a43e6c3827397db319344114e1  gcc/cp/parser.cc
  db6ae85b922989f89eda229cb29e4690  gcc/cp/parser.h
  567f2a034821422fb4613e2ecb3b9441  gcc/cp/pt.cc
  b606903e35fe6806362fe4eee7a89fef  gcc/cp/ptree.cc
  ee1ddf1e1b9554bb1a10109ce8c6dee5  gcc/cp/rtti.cc
  9c5477f737d2c390510c3fe72454f657  gcc/cp/search.cc
  568947e7de30b898e3df944cffd0661a  gcc/cp/semantics.cc
! 6a6b21cead5ae3e2fdb9253649be48f4  gcc/cp/std-name-hint.gperf
! 8e02351a089af5533d09881c271f0101  gcc/cp/std-name-hint.h
  f0d5c45acade2184f63127f724233555  gcc/cp/tree.cc
  bb1304379ac1bf9a568942bc7e976e8a  gcc/cp/type-utils.h
  3c980ddb0b9ed1ed653f38de363e7f08  gcc/cp/typeck.cc
--- 5595,5614 ----
  6c77b1fab5f6d146677090285a202a50  gcc/cp/mapper-client.h
  44e22b51797f89c9da996523a6d97f1c  gcc/cp/mapper-resolver.cc
  0456b59fb105d3d30371131d063a685a  gcc/cp/method.cc
! 591e9b1b557847c9faad7479e97687c5  gcc/cp/module.cc
  6b11f42e6b7d506e0ec6e292677347db  gcc/cp/name-lookup.cc
  6fdcf6a217e83566683fbec935637de3  gcc/cp/name-lookup.h
  e7fe06956aada61bcaae5168ad47a9c1  gcc/cp/operators.def
  813c253a000ee20d8d6598f56edc400e  gcc/cp/optimize.cc
! c1221aef922ffbdf49810e8f4bc70aea  gcc/cp/parser.cc
  db6ae85b922989f89eda229cb29e4690  gcc/cp/parser.h
  567f2a034821422fb4613e2ecb3b9441  gcc/cp/pt.cc
  b606903e35fe6806362fe4eee7a89fef  gcc/cp/ptree.cc
  ee1ddf1e1b9554bb1a10109ce8c6dee5  gcc/cp/rtti.cc
  9c5477f737d2c390510c3fe72454f657  gcc/cp/search.cc
  568947e7de30b898e3df944cffd0661a  gcc/cp/semantics.cc
! 8ccc82546d801360d2ccd8fd2a48b5d6  gcc/cp/std-name-hint.gperf
! bb87dbae9e49b63a73c4afa927a9018e  gcc/cp/std-name-hint.h
  f0d5c45acade2184f63127f724233555  gcc/cp/tree.cc
  bb1304379ac1bf9a568942bc7e976e8a  gcc/cp/type-utils.h
  3c980ddb0b9ed1ed653f38de363e7f08  gcc/cp/typeck.cc
*************** acdfc663791e4321372e79932070d05d  gcc/do
*** 5988,5994 ****
  81ae745aed5479afae430c578fa29055  gcc/doc/cppinternals.texi
  1a2d44757bb0f40b09493ac3863eba93  gcc/doc/cppopts.texi
  14b0532614eb25d7d84e7efd6664ecf3  gcc/doc/cppwarnopts.texi
! 9c2abb73b7d3b0274483ebeeab7fafa4  gcc/doc/extend.texi
  ddcdbcb699f5252a1c1219d92d87ed8b  gcc/doc/fragments.texi
  cd346f0c279f68138ef08c7addc796de  gcc/doc/frontends.texi
  a28615d9873d98f0d5f4ef8dd3e4c39d  gcc/doc/gcc.texi
--- 5988,5994 ----
  81ae745aed5479afae430c578fa29055  gcc/doc/cppinternals.texi
  1a2d44757bb0f40b09493ac3863eba93  gcc/doc/cppopts.texi
  14b0532614eb25d7d84e7efd6664ecf3  gcc/doc/cppwarnopts.texi
! ad94f3d51121a84eb81b61647590ee55  gcc/doc/extend.texi
  ddcdbcb699f5252a1c1219d92d87ed8b  gcc/doc/fragments.texi
  cd346f0c279f68138ef08c7addc796de  gcc/doc/frontends.texi
  a28615d9873d98f0d5f4ef8dd3e4c39d  gcc/doc/gcc.texi
*************** ee4c7654f733cefcb73d4fd24f3e1b82  gcc/do
*** 6012,6018 ****
  e9b8122841fbfbbc30fee8ed6613c399  gcc/doc/include/texinfo.tex
  37d1ea8f3672c644c9e9c2cfa630dcf3  gcc/doc/install.texi
  0f98706361e63fac2c35c2c4491eaac4  gcc/doc/install.texi2html
! 3170b806ae9039c65a52267664654bc0  gcc/doc/invoke.texi
  47f1f55b3595acf670eb6193a0cbd933  gcc/doc/languages.texi
  8783f1b0b6c204d4417b00f3b772beea  gcc/doc/libgcc.texi
  ef4f00c423089323edef1d3cff31a4a2  gcc/doc/libgdiagnostics/Makefile
--- 6012,6018 ----
  e9b8122841fbfbbc30fee8ed6613c399  gcc/doc/include/texinfo.tex
  37d1ea8f3672c644c9e9c2cfa630dcf3  gcc/doc/install.texi
  0f98706361e63fac2c35c2c4491eaac4  gcc/doc/install.texi2html
! 1efe296832646bbf7c583df91f809a63  gcc/doc/invoke.texi
  47f1f55b3595acf670eb6193a0cbd933  gcc/doc/languages.texi
  8783f1b0b6c204d4417b00f3b772beea  gcc/doc/libgcc.texi
  ef4f00c423089323edef1d3cff31a4a2  gcc/doc/libgdiagnostics/Makefile
*************** bd20fd07c5ee8f444bf1d3f5e64e066a  gcc/do
*** 6067,6073 ****
  c6eb228a6da301194f3963b6d42729e7  gcc/doc/standards.texi
  60892135dd93bb0e6d2d4d1b1fe11cb1  gcc/doc/tm.texi
  0801b698039cc220174c1b6ec339c77c  gcc/doc/tm.texi.in
! c4168f9f01adf4dd8adc647c04107142  gcc/doc/tree-ssa.texi
  5f62752970e47d350c8cbce47123d1cf  gcc/doc/trouble.texi
  7f44041407f24d2851135ae497914475  gcc/doc/ux.texi
  a1be2415e4997dcc307935ed9a162b33  gcc/dojump.cc
--- 6067,6073 ----
  c6eb228a6da301194f3963b6d42729e7  gcc/doc/standards.texi
  60892135dd93bb0e6d2d4d1b1fe11cb1  gcc/doc/tm.texi
  0801b698039cc220174c1b6ec339c77c  gcc/doc/tm.texi.in
! f3114c1d21828ab3242b20310ee407e7  gcc/doc/tree-ssa.texi
  5f62752970e47d350c8cbce47123d1cf  gcc/doc/trouble.texi
  7f44041407f24d2851135ae497914475  gcc/doc/ux.texi
  a1be2415e4997dcc307935ed9a162b33  gcc/dojump.cc
*************** b21182651156de7779948fe8ca2c4160  gcc/dw
*** 6089,6095 ****
  186b01005d892edba3b03fc17bd0dc8f  gcc/dwarf2codeview.h
  990f627cfa0aa26758dc2ffa0422da1b  gcc/dwarf2ctf.cc
  1d0191caafac1774f50a47175d915ea0  gcc/dwarf2ctf.h
! 946a596531681e08b17c802079f23289  gcc/dwarf2out.cc
  7ff70632352b65c214e02360ed6d6aae  gcc/dwarf2out.h
  fdd976759ee89958c91a4010e53c0f02  gcc/early-remat.cc
  0fa3f12b9f441f701d99e167274a0961  gcc/emit-rtl.cc
--- 6089,6095 ----
  186b01005d892edba3b03fc17bd0dc8f  gcc/dwarf2codeview.h
  990f627cfa0aa26758dc2ffa0422da1b  gcc/dwarf2ctf.cc
  1d0191caafac1774f50a47175d915ea0  gcc/dwarf2ctf.h
! 4d4ef2caeb92d32345529af61c69e5cd  gcc/dwarf2out.cc
  7ff70632352b65c214e02360ed6d6aae  gcc/dwarf2out.h
  fdd976759ee89958c91a4010e53c0f02  gcc/early-remat.cc
  0fa3f12b9f441f701d99e167274a0961  gcc/emit-rtl.cc
*************** de4a03cd382601071e81e57cc6c2a7e1  gcc/ex
*** 6106,6112 ****
  b5fa845ff578d70e8ceae655d6affc51  gcc/explow.h
  a4ee0bae47797ce73f05daef7a07edd4  gcc/expmed.cc
  dee0d85cc89e81b4cc185f1c3102811e  gcc/expmed.h
! 3a0759a3a107749941de50ee2b943e46  gcc/expr.cc
  dfa85539f017784504ec3d884e09901f  gcc/expr.h
  7117d2d0dde87eaf1ab2853b5bfd62e2  gcc/ext-dce.cc
  2ecf474a8f5380e5027c5b7a745cd736  gcc/fibonacci_heap.cc
--- 6106,6112 ----
  b5fa845ff578d70e8ceae655d6affc51  gcc/explow.h
  a4ee0bae47797ce73f05daef7a07edd4  gcc/expmed.cc
  dee0d85cc89e81b4cc185f1c3102811e  gcc/expmed.h
! efeb17689a7453211f59099acc97a475  gcc/expr.cc
  dfa85539f017784504ec3d884e09901f  gcc/expr.h
  7117d2d0dde87eaf1ab2853b5bfd62e2  gcc/ext-dce.cc
  2ecf474a8f5380e5027c5b7a745cd736  gcc/fibonacci_heap.cc
*************** b0756a8dbbe0b39051dfda2c5e26663f  gcc/fi
*** 6120,6131 ****
  7852b04b41add4ad6cc7c7c86cb82658  gcc/fixed-value.h
  d752cd9a8d46470c7f60cd7fc3ff2cf4  gcc/flag-types.h
  e8c5838138a5e07e5716964a8284e9a1  gcc/flags.h
! ada0afb884a142f8214291990679be13  gcc/fold-const-call.cc
  182559f127e8416b9e9abcffb267d5fc  gcc/fold-const-call.h
! b58e7f3d5f5ca03427f8d15607bf798c  gcc/fold-const.cc
! e9985d4b5adb916d5a002d4e2c83d5bc  gcc/fold-const.h
  cd4e6baf5d162fbd41160606055f8297  gcc/fold-mem-offsets.cc
! c2aee55f196197c64c7327e0044e8d7f  gcc/fortran/ChangeLog
  083c53fadafdcf3be46713838a51e36c  gcc/fortran/ChangeLog-2002
  2a4ca18d211fb2603139354fd16398ed  gcc/fortran/ChangeLog-2003
  e7462609ebd0dd7c874e0fc00e2833aa  gcc/fortran/ChangeLog-2004
--- 6120,6131 ----
  7852b04b41add4ad6cc7c7c86cb82658  gcc/fixed-value.h
  d752cd9a8d46470c7f60cd7fc3ff2cf4  gcc/flag-types.h
  e8c5838138a5e07e5716964a8284e9a1  gcc/flags.h
! b7bf1ecba30babcca6fcc9e9a66bebfb  gcc/fold-const-call.cc
  182559f127e8416b9e9abcffb267d5fc  gcc/fold-const-call.h
! c6bcf556650bd15e73728fb68b1276cc  gcc/fold-const.cc
! 1d6c2807b0d1d4dbc716459c64abe92f  gcc/fold-const.h
  cd4e6baf5d162fbd41160606055f8297  gcc/fold-mem-offsets.cc
! b18a2c79addeb3c0e3ce6096054ce903  gcc/fortran/ChangeLog
  083c53fadafdcf3be46713838a51e36c  gcc/fortran/ChangeLog-2002
  2a4ca18d211fb2603139354fd16398ed  gcc/fortran/ChangeLog-2003
  e7462609ebd0dd7c874e0fc00e2833aa  gcc/fortran/ChangeLog-2004
*************** aed3aedb6378a970055dff9e11eedc2d  gcc/fo
*** 6166,6172 ****
  b7e224f665bb5044ce35ed09435bd4fb  gcc/fortran/cpp.h
  a232f4d280ad08511e2718281b3d1ab6  gcc/fortran/data.cc
  d85e2f2fc3ee4721563bd47719063fb6  gcc/fortran/data.h
! d8dd08b8139c109ba7ff58b94ff876d8  gcc/fortran/decl.cc
  917fd2716f1eef2f47d4f032e14958ad  gcc/fortran/dependency.cc
  70111b1c7592e650c281b513c3cf2f47  gcc/fortran/dependency.h
  9f708de69558a334a8fec77d40a2a376  gcc/fortran/dump-parse-tree.cc
--- 6166,6172 ----
  b7e224f665bb5044ce35ed09435bd4fb  gcc/fortran/cpp.h
  a232f4d280ad08511e2718281b3d1ab6  gcc/fortran/data.cc
  d85e2f2fc3ee4721563bd47719063fb6  gcc/fortran/data.h
! 8c54bdec3922757b4d86c50a70140220  gcc/fortran/decl.cc
  917fd2716f1eef2f47d4f032e14958ad  gcc/fortran/dependency.cc
  70111b1c7592e650c281b513c3cf2f47  gcc/fortran/dependency.h
  9f708de69558a334a8fec77d40a2a376  gcc/fortran/dump-parse-tree.cc
*************** af66ab40a5434219772b76ad10035e45  gcc/fo
*** 6182,6188 ****
  e4fe6ce0303cd182ebd328bdb0ae5743  gcc/fortran/interface.cc
  74d5cc035a8e6ee1fb5826c965c90532  gcc/fortran/intrinsic.cc
  47e0e62e0a6eaad27941f8e734cda2a2  gcc/fortran/intrinsic.h
! 429eb49bcb0cb30dc19ef3aa3a032962  gcc/fortran/intrinsic.texi
  491e0576258d33e46ed87fe37a39cc55  gcc/fortran/invoke.texi
  4a91f323761835f16a1a9b3995485379  gcc/fortran/io.cc
  d2a28ef98f6f78d1608fb52204e013a5  gcc/fortran/ioparm.def
--- 6182,6188 ----
  e4fe6ce0303cd182ebd328bdb0ae5743  gcc/fortran/interface.cc
  74d5cc035a8e6ee1fb5826c965c90532  gcc/fortran/intrinsic.cc
  47e0e62e0a6eaad27941f8e734cda2a2  gcc/fortran/intrinsic.h
! a66961d972b8324ccd45b11ecadbb3bf  gcc/fortran/intrinsic.texi
  491e0576258d33e46ed87fe37a39cc55  gcc/fortran/invoke.texi
  4a91f323761835f16a1a9b3995485379  gcc/fortran/io.cc
  d2a28ef98f6f78d1608fb52204e013a5  gcc/fortran/ioparm.def
*************** d2a28ef98f6f78d1608fb52204e013a5  gcc/fo
*** 6199,6210 ****
  763c37f838e32f5ed8ad600157a0d951  gcc/fortran/mathbuiltins.def
  6e89e2e347d7f6e1576cbda0e958b5bd  gcc/fortran/misc.cc
  27910247f948e0af2baebd9c279bec80  gcc/fortran/module.cc
! 386f2c95bbaa69fc202ab39eac5f2899  gcc/fortran/openmp.cc
! 2ac54dd304f0494202ed99c637998d1d  gcc/fortran/options.cc
  44ee980cc04645c25872621b20fc36fa  gcc/fortran/parse.cc
  c1b40e866a8bbe611aa65278fe2508d3  gcc/fortran/parse.h
! d9a8622a97bb1c593aaf8c8b8c93d74a  gcc/fortran/primary.cc
! 72f4ba4843d1a606ecf585bd6291f268  gcc/fortran/resolve.cc
  8dc2391850ee95634781b6e296a096f6  gcc/fortran/scanner.cc
  3c39e0eef946c7f557ac375f23b9f3db  gcc/fortran/scanner.h
  d78cc6d6b48b8228757fb8b674f6ad9b  gcc/fortran/simplify.cc
--- 6199,6210 ----
  763c37f838e32f5ed8ad600157a0d951  gcc/fortran/mathbuiltins.def
  6e89e2e347d7f6e1576cbda0e958b5bd  gcc/fortran/misc.cc
  27910247f948e0af2baebd9c279bec80  gcc/fortran/module.cc
! a9cab8b108323b809b370629f7f05504  gcc/fortran/openmp.cc
! 97facac1dd9ae327c6c4547b527e4527  gcc/fortran/options.cc
  44ee980cc04645c25872621b20fc36fa  gcc/fortran/parse.cc
  c1b40e866a8bbe611aa65278fe2508d3  gcc/fortran/parse.h
! 4e4d304de614df4c3283e1c5331c7c2f  gcc/fortran/primary.cc
! 5c7f928e1cb32ae1bb6266fdf13adf35  gcc/fortran/resolve.cc
  8dc2391850ee95634781b6e296a096f6  gcc/fortran/scanner.cc
  3c39e0eef946c7f557ac375f23b9f3db  gcc/fortran/scanner.h
  d78cc6d6b48b8228757fb8b674f6ad9b  gcc/fortran/simplify.cc
*************** ebfc538fb0470443c527273e8a50c2a1  gcc/fo
*** 6212,6228 ****
  72c617ddd58e2640f57a4c4a8f0fe1f0  gcc/fortran/symbol.cc
  c9238712914e77b971fde08221a31bf7  gcc/fortran/target-memory.cc
  50451f5a575ab606948f8e72d8cc4721  gcc/fortran/target-memory.h
! 057b330bc82b11660a171da644afc881  gcc/fortran/trans-array.cc
  682d93b7e921d709d88b7e5219a69d53  gcc/fortran/trans-array.h
  dfe1e1950e068389ed73663e9a11ad88  gcc/fortran/trans-common.cc
! b361aba1fe8f6c48107afcc903042c69  gcc/fortran/trans-const.cc
  857805820c2a6ac77d2652c610d23de8  gcc/fortran/trans-const.h
  4676a3ce7cc7bd4ad728303adf614548  gcc/fortran/trans-decl.cc
! 792e17e875de091d4e18aed4ce5909b1  gcc/fortran/trans-expr.cc
! 2102d9af9d6edcf59127cd0c48c8d8d0  gcc/fortran/trans-intrinsic.cc
  2d29342f65aeef2af368527483b2d4f1  gcc/fortran/trans-io.cc
  27df041e4caff610df844e7a22e291e3  gcc/fortran/trans-openmp.cc
! f5f379f67b6cf561dfb27140b41ab51b  gcc/fortran/trans-stmt.cc
  9caf8a2f93e6cf5e2a567a3aa18f957c  gcc/fortran/trans-stmt.h
  24751fdbf5162757525888384f73dfd7  gcc/fortran/trans-types.cc
  422959ab20fd75df3766a03597227fd2  gcc/fortran/trans-types.h
--- 6212,6228 ----
  72c617ddd58e2640f57a4c4a8f0fe1f0  gcc/fortran/symbol.cc
  c9238712914e77b971fde08221a31bf7  gcc/fortran/target-memory.cc
  50451f5a575ab606948f8e72d8cc4721  gcc/fortran/target-memory.h
! 085093abd52c6213fb87ca7e559f1b7d  gcc/fortran/trans-array.cc
  682d93b7e921d709d88b7e5219a69d53  gcc/fortran/trans-array.h
  dfe1e1950e068389ed73663e9a11ad88  gcc/fortran/trans-common.cc
! fa8521f4c98868ee5fa7e9dea5a35e37  gcc/fortran/trans-const.cc
  857805820c2a6ac77d2652c610d23de8  gcc/fortran/trans-const.h
  4676a3ce7cc7bd4ad728303adf614548  gcc/fortran/trans-decl.cc
! 2fc7abc1a31c7f7ad6cc9e0fe34591f6  gcc/fortran/trans-expr.cc
! 080622546de640ae05ba0bb197fa9577  gcc/fortran/trans-intrinsic.cc
  2d29342f65aeef2af368527483b2d4f1  gcc/fortran/trans-io.cc
  27df041e4caff610df844e7a22e291e3  gcc/fortran/trans-openmp.cc
! cd091509b69239b87561c8695ce522ca  gcc/fortran/trans-stmt.cc
  9caf8a2f93e6cf5e2a567a3aa18f957c  gcc/fortran/trans-stmt.h
  24751fdbf5162757525888384f73dfd7  gcc/fortran/trans-types.cc
  422959ab20fd75df3766a03597227fd2  gcc/fortran/trans-types.h
*************** f5f379f67b6cf561dfb27140b41ab51b  gcc/fo
*** 6232,6238 ****
  2ddfa7f2ac232123d67959795d85aaa6  gcc/fortran/types.def
  f574663ce227d0be2e77015c008d708b  gcc/fp-test.cc
  7d49ef8f960daad31201f864eb1933d9  gcc/function-abi.cc
! 393a04bf94846193a761ce5a84b27b91  gcc/function-abi.h
  6e9698e4411a03357b6e2b60bc91c827  gcc/function-tests.cc
  69a21b42c94c44d00d46067a5b8337da  gcc/function.cc
  da5d04420f440a4a085dc91d92c6bfbb  gcc/function.h
--- 6232,6238 ----
  2ddfa7f2ac232123d67959795d85aaa6  gcc/fortran/types.def
  f574663ce227d0be2e77015c008d708b  gcc/fp-test.cc
  7d49ef8f960daad31201f864eb1933d9  gcc/function-abi.cc
! c7aa9146bcd5c51af5dea6e3042c68d7  gcc/function-abi.h
  6e9698e4411a03357b6e2b60bc91c827  gcc/function-tests.cc
  69a21b42c94c44d00d46067a5b8337da  gcc/function.cc
  da5d04420f440a4a085dc91d92c6bfbb  gcc/function.h
*************** da09d1e31d3994eb3d6958074d7b7ce5  gcc/gi
*** 6316,6322 ****
  fea7635818b5d7cefd4c7a0b268a254c  gcc/gimple-crc-optimization.cc
  1e3c7b3ded904be69c3703ac6d27fa44  gcc/gimple-expr.cc
  7b4f02095ce9b7a43bee8570917b9dc7  gcc/gimple-expr.h
! 3ecaca8d447ec71be19fcb6e0e2e6fa2  gcc/gimple-fold.cc
  9b04ce067dded26aa256b48adea40724  gcc/gimple-fold.h
  43ad47e8cd99d438040cf6937a3cbe5e  gcc/gimple-harden-conditionals.cc
  78586a1c0ce6834da91809b77f98c6d7  gcc/gimple-harden-control-flow.cc
--- 6316,6322 ----
  fea7635818b5d7cefd4c7a0b268a254c  gcc/gimple-crc-optimization.cc
  1e3c7b3ded904be69c3703ac6d27fa44  gcc/gimple-expr.cc
  7b4f02095ce9b7a43bee8570917b9dc7  gcc/gimple-expr.h
! b52f7521af68ee0d5854c1573d8b7f91  gcc/gimple-fold.cc
  9b04ce067dded26aa256b48adea40724  gcc/gimple-fold.h
  43ad47e8cd99d438040cf6937a3cbe5e  gcc/gimple-harden-conditionals.cc
  78586a1c0ce6834da91809b77f98c6d7  gcc/gimple-harden-control-flow.cc
*************** c2d4313b79925f171bbfc932704d0d6f  gcc/gi
*** 6350,6356 ****
  db61cb44af184c491426f70b14b72f64  gcc/gimple-range-gori.h
  60c1306ed88dab1ceb0f87187653585f  gcc/gimple-range-infer.cc
  d1b8fdd0fd8c738683e5995bf45cda94  gcc/gimple-range-infer.h
! 8ce7e8f3a71589b78ed308c68dafb5dc  gcc/gimple-range-op.cc
  c33a426eeaa6da07a474caf81b43a278  gcc/gimple-range-op.h
  33d3c148e1b6f1df39688e27f3511fe1  gcc/gimple-range-path.cc
  55a80a9f04099be643d37e29c9ac7d10  gcc/gimple-range-path.h
--- 6350,6356 ----
  db61cb44af184c491426f70b14b72f64  gcc/gimple-range-gori.h
  60c1306ed88dab1ceb0f87187653585f  gcc/gimple-range-infer.cc
  d1b8fdd0fd8c738683e5995bf45cda94  gcc/gimple-range-infer.h
! afe93bca845d66d8f5c8bb4e79507028  gcc/gimple-range-op.cc
  c33a426eeaa6da07a474caf81b43a278  gcc/gimple-range-op.h
  33d3c148e1b6f1df39688e27f3511fe1  gcc/gimple-range-path.cc
  55a80a9f04099be643d37e29c9ac7d10  gcc/gimple-range-path.h
*************** d7408ac6c915c3e2f58cd40bdb6a0671  gcc/gi
*** 6408,6414 ****
  18dd241fd4e77ac61edc90586b9fb2b6  gcc/ginclude/unwind-arm-common.h
  8d9ecf0d6ef93c79623ce1d27a32a2cb  gcc/ginclude/varargs.h
  b41648f499a7db07e24806aae26998b5  gcc/glimits.h
! b62287412904be40f5aa091236357f21  gcc/go/ChangeLog
  e697a6a6e7d6942b7375c665c70d34b4  gcc/go/Make-lang.in
  60ea054548c83c7f66170073f9f3e74c  gcc/go/README.gcc
  88217f68368328f3ce651c46f0830df8  gcc/go/config-lang.in
--- 6408,6414 ----
  18dd241fd4e77ac61edc90586b9fb2b6  gcc/ginclude/unwind-arm-common.h
  8d9ecf0d6ef93c79623ce1d27a32a2cb  gcc/ginclude/varargs.h
  b41648f499a7db07e24806aae26998b5  gcc/glimits.h
! 5b432076be455f877d914253d6bb8cdd  gcc/go/ChangeLog
  e697a6a6e7d6942b7375c665c70d34b4  gcc/go/Make-lang.in
  60ea054548c83c7f66170073f9f3e74c  gcc/go/README.gcc
  88217f68368328f3ce651c46f0830df8  gcc/go/config-lang.in
*************** dd1cba65631d281511dc79ed9280dafc  gcc/go
*** 6418,6424 ****
  b36b3fa1db505d7b6ef1e18b129035a8  gcc/go/go-gcc-diagnostics.cc
  43c3ce307d5860ce73ee5069566503db  gcc/go/go-gcc.cc
  a9479832ddc20b2770e829e37ef9f9b4  gcc/go/go-gcc.h
! 8bddedd00bb083ceeba22bff8df6d40c  gcc/go/go-lang.cc
  c5d6aaa7e913ef205113a2bba2e5206f  gcc/go/go-linemap.cc
  91c7a6773e207cc086ae0888826cc3c4  gcc/go/go-location.h
  ec49aa04ab6e271ed2c9c16d80ede5fd  gcc/go/go-sha1.cc
--- 6418,6424 ----
  b36b3fa1db505d7b6ef1e18b129035a8  gcc/go/go-gcc-diagnostics.cc
  43c3ce307d5860ce73ee5069566503db  gcc/go/go-gcc.cc
  a9479832ddc20b2770e829e37ef9f9b4  gcc/go/go-gcc.h
! d0c38ba62e478ea4dc216ff9661e101d  gcc/go/go-lang.cc
  c5d6aaa7e913ef205113a2bba2e5206f  gcc/go/go-linemap.cc
  91c7a6773e207cc086ae0888826cc3c4  gcc/go/go-location.h
  ec49aa04ab6e271ed2c9c16d80ede5fd  gcc/go/go-sha1.cc
*************** b997f8373ba0004a3b0b6df43035d40d  gcc/ho
*** 6512,6518 ****
  260dd898f6b9809f71a292b793d67324  gcc/hw-doloop.h
  4769eb51982f8ccb12764424698b464f  gcc/hwint.cc
  8826410aae6a5efbb3d335e5e3dceed4  gcc/hwint.h
! fb45151009d8fb2f049bceb3944e39c6  gcc/ifcvt.cc
  1d252ebba03aa858df6822a8b59e1d4e  gcc/ifcvt.h
  55413f67957a351f7ca1b0a8a2f69a7c  gcc/inchash.cc
  f380ce65b15eedb6d55a9848beb1ec3b  gcc/inchash.h
--- 6512,6518 ----
  260dd898f6b9809f71a292b793d67324  gcc/hw-doloop.h
  4769eb51982f8ccb12764424698b464f  gcc/hwint.cc
  8826410aae6a5efbb3d335e5e3dceed4  gcc/hwint.h
! 965a6fb5f5cb4d0e1462248cc79b1554  gcc/ifcvt.cc
  1d252ebba03aa858df6822a8b59e1d4e  gcc/ifcvt.h
  55413f67957a351f7ca1b0a8a2f69a7c  gcc/inchash.cc
  f380ce65b15eedb6d55a9848beb1ec3b  gcc/inchash.h
*************** fef6f27045737cc29ebf2dbbd22dda02  gcc/ip
*** 6538,6544 ****
  a3882f8a9c03be47eb0deee0bd27e04d  gcc/ipa-free-lang-data.cc
  151286d02b3d36dcca2a63fe6ae51102  gcc/ipa-icf-gimple.cc
  9762b96eb0bd1d2d7968b5c2f51e8f43  gcc/ipa-icf-gimple.h
! 005f3683b94c9cf2ef95442dcaaa8771  gcc/ipa-icf.cc
  b2ecb607534e24bdc2bc2e02ba2199ca  gcc/ipa-icf.h
  da5a8b46913e455ff432d2110722af82  gcc/ipa-inline-analysis.cc
  3a7b210d2f26cf868f3eec1036b8a20f  gcc/ipa-inline-transform.cc
--- 6538,6544 ----
  a3882f8a9c03be47eb0deee0bd27e04d  gcc/ipa-free-lang-data.cc
  151286d02b3d36dcca2a63fe6ae51102  gcc/ipa-icf-gimple.cc
  9762b96eb0bd1d2d7968b5c2f51e8f43  gcc/ipa-icf-gimple.h
! 9806e969ff8163311801017867b9add7  gcc/ipa-icf.cc
  b2ecb607534e24bdc2bc2e02ba2199ca  gcc/ipa-icf.h
  da5a8b46913e455ff432d2110722af82  gcc/ipa-inline-analysis.cc
  3a7b210d2f26cf868f3eec1036b8a20f  gcc/ipa-inline-transform.cc
*************** a8bc23feef2d2f8a3d25702ece427f87  gcc/ip
*** 6548,6554 ****
  e1e331896b86db8a2281657bbb21ac72  gcc/ipa-locality-cloning.h
  5146e44af36aa042f1e1098a4e796065  gcc/ipa-modref-tree.cc
  5a1edb91a2b7237c3e946f040a3d9697  gcc/ipa-modref-tree.h
! 3f72461d9982b691967c88700eb6d7b8  gcc/ipa-modref.cc
  8fe1972490c1cce5a10c7cdcd57b2361  gcc/ipa-modref.h
  05a01f3b363a6f52cbd830868997624c  gcc/ipa-param-manipulation.cc
  6402305bfd352583fddaf5ceee9f6a46  gcc/ipa-param-manipulation.h
--- 6548,6554 ----
  e1e331896b86db8a2281657bbb21ac72  gcc/ipa-locality-cloning.h
  5146e44af36aa042f1e1098a4e796065  gcc/ipa-modref-tree.cc
  5a1edb91a2b7237c3e946f040a3d9697  gcc/ipa-modref-tree.h
! d4b6029d550d1c8bf41bfb44083a9843  gcc/ipa-modref.cc
  8fe1972490c1cce5a10c7cdcd57b2361  gcc/ipa-modref.h
  05a01f3b363a6f52cbd830868997624c  gcc/ipa-param-manipulation.cc
  6402305bfd352583fddaf5ceee9f6a46  gcc/ipa-param-manipulation.h
*************** e1e331896b86db8a2281657bbb21ac72  gcc/ip
*** 6556,6567 ****
  83c011375208cf1307980bcb1b18b67a  gcc/ipa-predicate.cc
  3290558dca39b32c0ca581e6c3427551  gcc/ipa-predicate.h
  cb4c87b016a31121941a3b4b6060d470  gcc/ipa-profile.cc
! d528939269f32a378db7959064093c5f  gcc/ipa-prop.cc
  00d42ec7c12a0fe53f1cce1d2ac27096  gcc/ipa-prop.h
  1c585ae593227742840d2cccb610d475  gcc/ipa-pure-const.cc
  ce0496bede6d40e2fcfbc8277856fc23  gcc/ipa-ref.cc
  ee6c4ff9a86c5d0a68fa41c8da2b5c6f  gcc/ipa-ref.h
! e02101954d14c2f0b6a7667db7690ade  gcc/ipa-reference.cc
  d4930f12a999a28238b013539b631f2f  gcc/ipa-reference.h
  6e25e7ad90c3ddb398c67560a2eddd86  gcc/ipa-split.cc
  128fc9f66e07a64e6ebecfe0e1f78765  gcc/ipa-sra.cc
--- 6556,6567 ----
  83c011375208cf1307980bcb1b18b67a  gcc/ipa-predicate.cc
  3290558dca39b32c0ca581e6c3427551  gcc/ipa-predicate.h
  cb4c87b016a31121941a3b4b6060d470  gcc/ipa-profile.cc
! c541a7e3ba53fb3fa1e3848e1c71bb29  gcc/ipa-prop.cc
  00d42ec7c12a0fe53f1cce1d2ac27096  gcc/ipa-prop.h
  1c585ae593227742840d2cccb610d475  gcc/ipa-pure-const.cc
  ce0496bede6d40e2fcfbc8277856fc23  gcc/ipa-ref.cc
  ee6c4ff9a86c5d0a68fa41c8da2b5c6f  gcc/ipa-ref.h
! d26d5182352272175a1093baac59029c  gcc/ipa-reference.cc
  d4930f12a999a28238b013539b631f2f  gcc/ipa-reference.h
  6e25e7ad90c3ddb398c67560a2eddd86  gcc/ipa-split.cc
  128fc9f66e07a64e6ebecfe0e1f78765  gcc/ipa-sra.cc
*************** ed94ab1f6976f64c8d20b7b65da14438  gcc/ir
*** 6582,6588 ****
  e02a7a08ca9acaac686d9cb897ac121b  gcc/ira.h
  101bad313081e351312c8d42e0b24b31  gcc/is-a.h
  4e832d29f0e621d177da3fa9c3e11b69  gcc/iterator-utils.h
! cb1e568561ebcbed352596712eab1f90  gcc/jit/ChangeLog
  6071bdf04fb356c5ac99a99ec00c9a12  gcc/jit/ChangeLog.jit
  222ee07ce761a3e77636dc2e76c20087  gcc/jit/Make-lang.in
  fd0d76b6467c987f813d430a35d4760a  gcc/jit/TODO.rst
--- 6582,6588 ----
  e02a7a08ca9acaac686d9cb897ac121b  gcc/ira.h
  101bad313081e351312c8d42e0b24b31  gcc/is-a.h
  4e832d29f0e621d177da3fa9c3e11b69  gcc/iterator-utils.h
! b157c19804ea9475f25320eddbb55a1d  gcc/jit/ChangeLog
  6071bdf04fb356c5ac99a99ec00c9a12  gcc/jit/ChangeLog.jit
  222ee07ce761a3e77636dc2e76c20087  gcc/jit/Make-lang.in
  fd0d76b6467c987f813d430a35d4760a  gcc/jit/TODO.rst
*************** b54054c495232a416b1cdea9032d1d9f  gcc/lo
*** 6710,6716 ****
  05bf78e6d3e36587723b1177ffcd9c6e  gcc/lower-subreg.h
  755a196fed2cd7b5878159035d75b39b  gcc/lra-assigns.cc
  0232e051e662ebb7fd2fa507d9c581b8  gcc/lra-coalesce.cc
! cb8a8878d59beba7d0552408a9a2a0d3  gcc/lra-constraints.cc
  ebe278d864d3a7e33fbcc46f02926248  gcc/lra-eliminations.cc
  c9f048755e3742fbe86e02e2b4b1eb6d  gcc/lra-int.h
  52ba28cd117bff034bd9a26fe150f692  gcc/lra-lives.cc
--- 6710,6716 ----
  05bf78e6d3e36587723b1177ffcd9c6e  gcc/lower-subreg.h
  755a196fed2cd7b5878159035d75b39b  gcc/lra-assigns.cc
  0232e051e662ebb7fd2fa507d9c581b8  gcc/lra-coalesce.cc
! 6ed82581271e048b5c121fbc188c6e23  gcc/lra-constraints.cc
  ebe278d864d3a7e33fbcc46f02926248  gcc/lra-eliminations.cc
  c9f048755e3742fbe86e02e2b4b1eb6d  gcc/lra-int.h
  52ba28cd117bff034bd9a26fe150f692  gcc/lra-lives.cc
*************** f98dc87a80f661782eacaf50d123997d  gcc/lr
*** 6718,6738 ****
  7d88a319b2eed09205d9a01cca221eb6  gcc/lra-spills.cc
  e5fef2ffe59f5bb8bf855af92be9ce6a  gcc/lra.cc
  f34f18b0bf45561aad0763e10bc1ecb1  gcc/lra.h
! e6757d768b06dab2f1c057cb7b9b0d62  gcc/lto-cgraph.cc
  3c0edd5f81587bb2a1bebb7979c19aa8  gcc/lto-compress.cc
  6081736069853cccad4e30dab7992217  gcc/lto-compress.h
  e30abe8a6f83280333eda23e196378ad  gcc/lto-ltrans-cache.cc
  ccc169e39c1de2f69a4744154373899f  gcc/lto-ltrans-cache.h
  2761a8599f5c743bf4c67dc2c3c2d347  gcc/lto-opts.cc
! 598e2e8346c0154856c5ef27e7649887  gcc/lto-section-in.cc
  f2a9985147f87fd566d4ae2dd8fceabc  gcc/lto-section-names.h
  92ad85d667fb88ca0d727d1081d5a438  gcc/lto-section-out.cc
! 022eda68922792984b6370af859619e4  gcc/lto-streamer-in.cc
! 295f167dcf44ebe2d16bceae99571c42  gcc/lto-streamer-out.cc
  8caf9a68892d64dc294b20c27291b749  gcc/lto-streamer.cc
! 89440b8d71857e40c8fa12dd9aa25491  gcc/lto-streamer.h
  4b39d90bb231d099b0fc04c8ded93cee  gcc/lto-wrapper.cc
! ce7bbfb301c21204caffe703bc7aeb78  gcc/lto/ChangeLog
  3e7816807401da2506930719e6dc8b3d  gcc/lto/Make-lang.in
  705d8eaa74b456d79367c2c42b7a2fef  gcc/lto/common.cc
  3d201b30f0538a8cfddc450739b1c8c5  gcc/lto/common.h
--- 6718,6738 ----
  7d88a319b2eed09205d9a01cca221eb6  gcc/lra-spills.cc
  e5fef2ffe59f5bb8bf855af92be9ce6a  gcc/lra.cc
  f34f18b0bf45561aad0763e10bc1ecb1  gcc/lra.h
! a184b047851ed058660ead45e7acc3e3  gcc/lto-cgraph.cc
  3c0edd5f81587bb2a1bebb7979c19aa8  gcc/lto-compress.cc
  6081736069853cccad4e30dab7992217  gcc/lto-compress.h
  e30abe8a6f83280333eda23e196378ad  gcc/lto-ltrans-cache.cc
  ccc169e39c1de2f69a4744154373899f  gcc/lto-ltrans-cache.h
  2761a8599f5c743bf4c67dc2c3c2d347  gcc/lto-opts.cc
! a17a38f054bc1a1d5251ae4e33328510  gcc/lto-section-in.cc
  f2a9985147f87fd566d4ae2dd8fceabc  gcc/lto-section-names.h
  92ad85d667fb88ca0d727d1081d5a438  gcc/lto-section-out.cc
! 6c75be9cf8c45018aae0f2d91e2411ba  gcc/lto-streamer-in.cc
! c123d330c230c1e0fe188e9143a9dcf8  gcc/lto-streamer-out.cc
  8caf9a68892d64dc294b20c27291b749  gcc/lto-streamer.cc
! a02ffd191761acac63f19c981da24abf  gcc/lto-streamer.h
  4b39d90bb231d099b0fc04c8ded93cee  gcc/lto-wrapper.cc
! fbd3fcf29f5d2197380e59583081b6a8  gcc/lto/ChangeLog
  3e7816807401da2506930719e6dc8b3d  gcc/lto/Make-lang.in
  705d8eaa74b456d79367c2c42b7a2fef  gcc/lto/common.cc
  3d201b30f0538a8cfddc450739b1c8c5  gcc/lto/common.h
*************** e09c982f34fcc53d88fb9b974a77d569  gcc/lt
*** 6743,6762 ****
  e9e3e1c53895933c30b602dfb27942ff  gcc/lto/lto-common.cc
  1bbd724bce4771513f0a356074d52d51  gcc/lto/lto-common.h
  24353553f316f6efb9d7f42253a3ec7c  gcc/lto/lto-dump.cc
! 9a5a957f50fd70274ccec05a5ac526f6  gcc/lto/lto-lang.cc
  abba0d56cf42c70d1983f247453576cd  gcc/lto/lto-object.cc
! 38c04a0ddda1a5a40c7fffc7079b0b21  gcc/lto/lto-partition.cc
  6bdee5523aaa6e7091e15f5270e1ef9f  gcc/lto/lto-partition.h
! 1fe27a12b5a9b027b47f819c6e23ed1c  gcc/lto/lto-symtab.cc
  37534ae509993637d7af9690433de15c  gcc/lto/lto-symtab.h
  b153638c23972a22ca31986c1b49348d  gcc/lto/lto-tree.h
! e44c0bf9cc0411d7bd57c6585eb6d0e4  gcc/lto/lto.cc
  46fbea4008689ba8af9f80d1cdce438a  gcc/lto/lto.h
  890758104e7697865dd110259fee0af5  gcc/m2/COPYING.FDL
  b417a4bd52371186803e70c49d24764d  gcc/m2/COPYING.RUNTIME
  8f0e2cd40e05189ec81232da84bd6e1a  gcc/m2/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/m2/COPYING3.LIB
! cfa437bc691e2c84a43cfc0c1ae4ccf8  gcc/m2/ChangeLog
  1b9fd55a4978f2f62717ca706fc999f4  gcc/m2/Make-lang.in
  e212443a3231afc28440b22d94debe50  gcc/m2/Make-maintainer.in
  6a74129fda00ca52ba9f953538250c45  gcc/m2/NEWS
--- 6743,6762 ----
  e9e3e1c53895933c30b602dfb27942ff  gcc/lto/lto-common.cc
  1bbd724bce4771513f0a356074d52d51  gcc/lto/lto-common.h
  24353553f316f6efb9d7f42253a3ec7c  gcc/lto/lto-dump.cc
! 6f7bac8568b01539cfeadad94e94aa6e  gcc/lto/lto-lang.cc
  abba0d56cf42c70d1983f247453576cd  gcc/lto/lto-object.cc
! 29cb2a19e49d9b14ca5733e55827c0c5  gcc/lto/lto-partition.cc
  6bdee5523aaa6e7091e15f5270e1ef9f  gcc/lto/lto-partition.h
! 3890271ac10891e53209884724fcb93a  gcc/lto/lto-symtab.cc
  37534ae509993637d7af9690433de15c  gcc/lto/lto-symtab.h
  b153638c23972a22ca31986c1b49348d  gcc/lto/lto-tree.h
! ed501b04d194414b59e75eba36ddbac6  gcc/lto/lto.cc
  46fbea4008689ba8af9f80d1cdce438a  gcc/lto/lto.h
  890758104e7697865dd110259fee0af5  gcc/m2/COPYING.FDL
  b417a4bd52371186803e70c49d24764d  gcc/m2/COPYING.RUNTIME
  8f0e2cd40e05189ec81232da84bd6e1a  gcc/m2/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/m2/COPYING3.LIB
! 3de9c086913b18ad11093ea946db7a1f  gcc/m2/ChangeLog
  1b9fd55a4978f2f62717ca706fc999f4  gcc/m2/Make-lang.in
  e212443a3231afc28440b22d94debe50  gcc/m2/Make-maintainer.in
  6a74129fda00ca52ba9f953538250c45  gcc/m2/NEWS
*************** fb61dc2b9faf55fe1da94c60b08cc78b  gcc/m2
*** 6796,6802 ****
  7ec6d0e1d8778b77940a35fb413cc951  gcc/m2/gm2-compiler/M2ColorString.def
  01a6ecec3ac51d7fcc8112d095cfd2b2  gcc/m2/gm2-compiler/M2ColorString.mod
  28e32ddcae091f46980874f0523fa028  gcc/m2/gm2-compiler/M2Comp.def
! fa402f91b06a7bc055c7ab91c503d47e  gcc/m2/gm2-compiler/M2Comp.mod
  fb9e43e1f35780216ba6b6e360c0e264  gcc/m2/gm2-compiler/M2Const.def
  d48c136acab402fd877d833ead85eb2c  gcc/m2/gm2-compiler/M2Const.mod
  feb013504143369554b5acc90feea3b6  gcc/m2/gm2-compiler/M2Debug.def
--- 6796,6802 ----
  7ec6d0e1d8778b77940a35fb413cc951  gcc/m2/gm2-compiler/M2ColorString.def
  01a6ecec3ac51d7fcc8112d095cfd2b2  gcc/m2/gm2-compiler/M2ColorString.mod
  28e32ddcae091f46980874f0523fa028  gcc/m2/gm2-compiler/M2Comp.def
! 5a1957bb507c44f3974d9be0d46b5139  gcc/m2/gm2-compiler/M2Comp.mod
  fb9e43e1f35780216ba6b6e360c0e264  gcc/m2/gm2-compiler/M2Const.def
  d48c136acab402fd877d833ead85eb2c  gcc/m2/gm2-compiler/M2Const.mod
  feb013504143369554b5acc90feea3b6  gcc/m2/gm2-compiler/M2Debug.def
*************** cccf272bab8c31a6af4113dc6a4e7b2d  gcc/m2
*** 6827,6833 ****
  a45ab5cf82c6f9afcaac634dd94f9e74  gcc/m2/gm2-compiler/M2LexBuf.def
  12f7883768071fdbccde614b41cd757e  gcc/m2/gm2-compiler/M2LexBuf.mod
  ebc348963369e8e9da5834ac81e9f37c  gcc/m2/gm2-compiler/M2MetaError.def
! a3a693189c0c8b5d22b610c59c1a7002  gcc/m2/gm2-compiler/M2MetaError.mod
  30199ab614068ba2ade7649d91420d13  gcc/m2/gm2-compiler/M2Optimize.def
  6b138f381fa3bee219d0c362567bbcb0  gcc/m2/gm2-compiler/M2Optimize.mod
  e56f64013f646609999ce89ae8c3084d  gcc/m2/gm2-compiler/M2Options.def
--- 6827,6833 ----
  a45ab5cf82c6f9afcaac634dd94f9e74  gcc/m2/gm2-compiler/M2LexBuf.def
  12f7883768071fdbccde614b41cd757e  gcc/m2/gm2-compiler/M2LexBuf.mod
  ebc348963369e8e9da5834ac81e9f37c  gcc/m2/gm2-compiler/M2MetaError.def
! 712e21ae753029c048f94ffb3015b7cd  gcc/m2/gm2-compiler/M2MetaError.mod
  30199ab614068ba2ade7649d91420d13  gcc/m2/gm2-compiler/M2Optimize.def
  6b138f381fa3bee219d0c362567bbcb0  gcc/m2/gm2-compiler/M2Optimize.mod
  e56f64013f646609999ce89ae8c3084d  gcc/m2/gm2-compiler/M2Options.def
*************** ffffd6bd10c2f3d61aee939845cdb397  gcc/m2
*** 6839,6845 ****
  5aae879fe93711ac462b3871f94cfdfb  gcc/m2/gm2-compiler/M2Printf.def
  2984233cca97a1078980faba9ae9c1c5  gcc/m2/gm2-compiler/M2Printf.mod
  1f3929030e3dde0bd645746be5c341d3  gcc/m2/gm2-compiler/M2Quads.def
! e66d90374675a01433fe2fd0ea22e5d4  gcc/m2/gm2-compiler/M2Quads.mod
  652e5da6749bca8b22b149208db30048  gcc/m2/gm2-compiler/M2Quiet.def
  fe82981e1fc213781973d90590cac13a  gcc/m2/gm2-compiler/M2Quiet.mod
  3a524bf1e1843ed3472cde4c27661681  gcc/m2/gm2-compiler/M2Range.def
--- 6839,6845 ----
  5aae879fe93711ac462b3871f94cfdfb  gcc/m2/gm2-compiler/M2Printf.def
  2984233cca97a1078980faba9ae9c1c5  gcc/m2/gm2-compiler/M2Printf.mod
  1f3929030e3dde0bd645746be5c341d3  gcc/m2/gm2-compiler/M2Quads.def
! 8e9af1b49d11a96dcdd885e3e2a6cccd  gcc/m2/gm2-compiler/M2Quads.mod
  652e5da6749bca8b22b149208db30048  gcc/m2/gm2-compiler/M2Quiet.def
  fe82981e1fc213781973d90590cac13a  gcc/m2/gm2-compiler/M2Quiet.mod
  3a524bf1e1843ed3472cde4c27661681  gcc/m2/gm2-compiler/M2Range.def
*************** c716fec488e5ec3c78c79fc4f8e9faa4  gcc/m2
*** 6858,6865 ****
  de5d55be0bb19508f67759a6f2ddb70d  gcc/m2/gm2-compiler/M2Size.mod
  63dd764a7f6117e3e98b0e6dedc18c3b  gcc/m2/gm2-compiler/M2StackAddress.def
  f61208b1b833c0b6155c719142094137  gcc/m2/gm2-compiler/M2StackAddress.mod
! 047fc7a18abb730ad4889a97e12fc143  gcc/m2/gm2-compiler/M2StackSpell.def
! a379e77e164d9c5a0a36d158ac69f901  gcc/m2/gm2-compiler/M2StackSpell.mod
  1bd33fb5e6f93600249af03be22b3520  gcc/m2/gm2-compiler/M2StackWord.def
  d9366c8e64396b3e7db41fa619b4f74f  gcc/m2/gm2-compiler/M2StackWord.mod
  7f7b8008a87023e5ad507a6b3afe83fd  gcc/m2/gm2-compiler/M2StateCheck.def
--- 6858,6865 ----
  de5d55be0bb19508f67759a6f2ddb70d  gcc/m2/gm2-compiler/M2Size.mod
  63dd764a7f6117e3e98b0e6dedc18c3b  gcc/m2/gm2-compiler/M2StackAddress.def
  f61208b1b833c0b6155c719142094137  gcc/m2/gm2-compiler/M2StackAddress.mod
! 06a87a4cac4f49870aaba168ea18f07f  gcc/m2/gm2-compiler/M2StackSpell.def
! 91e5806346f40968842fe7bb808ec88a  gcc/m2/gm2-compiler/M2StackSpell.mod
  1bd33fb5e6f93600249af03be22b3520  gcc/m2/gm2-compiler/M2StackWord.def
  d9366c8e64396b3e7db41fa619b4f74f  gcc/m2/gm2-compiler/M2StackWord.mod
  7f7b8008a87023e5ad507a6b3afe83fd  gcc/m2/gm2-compiler/M2StateCheck.def
*************** c29a9335f95f669068e909ae15059311  gcc/m2
*** 6883,6892 ****
  75d5730c845b3aa2829a8cdb4f568d87  gcc/m2/gm2-compiler/P0SymBuild.mod
  78893417cbfdb104585ba464af769887  gcc/m2/gm2-compiler/P0SyntaxCheck.bnf
  b347f8b97c2042773c008adffe4e54d9  gcc/m2/gm2-compiler/P0SyntaxCheck.def
! 602cc39ece2e20e647562bea41cf5716  gcc/m2/gm2-compiler/P1Build.bnf
  7f0d77f27044b69065c97e7e1f2f361b  gcc/m2/gm2-compiler/P1Build.def
  022dddb1d109a1c84112ee601cb7e4fb  gcc/m2/gm2-compiler/P1SymBuild.def
! 8a6a96a453036a590f7fd5c914348573  gcc/m2/gm2-compiler/P1SymBuild.mod
  dfc36d5f0832b9dd188d6557ffef76d3  gcc/m2/gm2-compiler/P2Build.bnf
  5d3aa3c32f62966992c31b5bd6fe9bdb  gcc/m2/gm2-compiler/P2Build.def
  7d034c383eee29111871cfe944a77b96  gcc/m2/gm2-compiler/P2SymBuild.def
--- 6883,6892 ----
  75d5730c845b3aa2829a8cdb4f568d87  gcc/m2/gm2-compiler/P0SymBuild.mod
  78893417cbfdb104585ba464af769887  gcc/m2/gm2-compiler/P0SyntaxCheck.bnf
  b347f8b97c2042773c008adffe4e54d9  gcc/m2/gm2-compiler/P0SyntaxCheck.def
! b4984ef6ed011ac3d4a4228129675f0f  gcc/m2/gm2-compiler/P1Build.bnf
  7f0d77f27044b69065c97e7e1f2f361b  gcc/m2/gm2-compiler/P1Build.def
  022dddb1d109a1c84112ee601cb7e4fb  gcc/m2/gm2-compiler/P1SymBuild.def
! aac47b78ebd2c1cbe3e547e427a9af2a  gcc/m2/gm2-compiler/P1SymBuild.mod
  dfc36d5f0832b9dd188d6557ffef76d3  gcc/m2/gm2-compiler/P2Build.bnf
  5d3aa3c32f62966992c31b5bd6fe9bdb  gcc/m2/gm2-compiler/P2Build.def
  7d034c383eee29111871cfe944a77b96  gcc/m2/gm2-compiler/P2SymBuild.def
*************** fabfc816f99fb184266e92ed4a85b7a4  gcc/m2
*** 6910,6917 ****
  eba1a056b41ce6fae1088f3d0bdd86d7  gcc/m2/gm2-compiler/SymbolConversion.mod
  7e7c5313b631435b03f974e72c20d104  gcc/m2/gm2-compiler/SymbolKey.def
  be245258e0123a45bbd9a47e859deb50  gcc/m2/gm2-compiler/SymbolKey.mod
! 925495a977549b34f2957104ea04fb81  gcc/m2/gm2-compiler/SymbolTable.def
! 30cf58002425420c9b3b8028f88cf51c  gcc/m2/gm2-compiler/SymbolTable.mod
  4e5bbaec9cd1341e4e14b9951485e75b  gcc/m2/gm2-compiler/bnflex.def
  34956a3ca2f84a677fbf711642452563  gcc/m2/gm2-compiler/bnflex.mod
  3ba721399af75ed8db2b223d9947d26d  gcc/m2/gm2-compiler/cflex.def
--- 6910,6917 ----
  eba1a056b41ce6fae1088f3d0bdd86d7  gcc/m2/gm2-compiler/SymbolConversion.mod
  7e7c5313b631435b03f974e72c20d104  gcc/m2/gm2-compiler/SymbolKey.def
  be245258e0123a45bbd9a47e859deb50  gcc/m2/gm2-compiler/SymbolKey.mod
! 76dcdb834e7988b5a5a4f09960afa1fc  gcc/m2/gm2-compiler/SymbolTable.def
! 0b90cf07a66edd7f2486fe9f98eab942  gcc/m2/gm2-compiler/SymbolTable.mod
  4e5bbaec9cd1341e4e14b9951485e75b  gcc/m2/gm2-compiler/bnflex.def
  34956a3ca2f84a677fbf711642452563  gcc/m2/gm2-compiler/bnflex.mod
  3ba721399af75ed8db2b223d9947d26d  gcc/m2/gm2-compiler/cflex.def
*************** f9608e9005487c369e6c38949ab36fa1  gcc/m2
*** 7731,7737 ****
  88e10618d6f39a411b34e2245b93307b  gcc/machmode.def
  550bdb35d0e034ca0050c574ba896d61  gcc/machmode.h
  486412acbbb6de10b080e31410a14f33  gcc/main.cc
! 21541081bbf62b5b1999dc14834023d0  gcc/match.pd
  63bf182c7c3a100e101b2129976be89b  gcc/mcf.cc
  795fbbc034a60f5af7e79dbe3bac65a0  gcc/mem-stats-traits.h
  295dcd7618653c13dcf063266752d06f  gcc/mem-stats.h
--- 7731,7737 ----
  88e10618d6f39a411b34e2245b93307b  gcc/machmode.def
  550bdb35d0e034ca0050c574ba896d61  gcc/machmode.h
  486412acbbb6de10b080e31410a14f33  gcc/main.cc
! 1661317da327a28ca6a454f554efcc62  gcc/match.pd
  63bf182c7c3a100e101b2129976be89b  gcc/mcf.cc
  795fbbc034a60f5af7e79dbe3bac65a0  gcc/mem-stats-traits.h
  295dcd7618653c13dcf063266752d06f  gcc/mem-stats.h
*************** b4c35ee2dcd91ade3c9baf0bb43c18ca  gcc/op
*** 7816,7822 ****
  6d624f6fea144bbb8e71378935b84abd  gcc/opts-diagnostic.h
  dd6379e65503d93b6eb08844e8bf2d09  gcc/opts-global.cc
  079a115ae417106f3e7f42b0272b866d  gcc/opts-jobserver.h
! eb608d05eaf65d47956a2fb09d93b90d  gcc/opts.cc
  7297ae8caf0c34afb0609151e7e3f987  gcc/opts.h
  b7a4b3edfca283f972cdeb23102a28a4  gcc/ordered-hash-map-tests.cc
  fccd951e3de91d49d3824e482c12e070  gcc/ordered-hash-map.h
--- 7816,7822 ----
  6d624f6fea144bbb8e71378935b84abd  gcc/opts-diagnostic.h
  dd6379e65503d93b6eb08844e8bf2d09  gcc/opts-global.cc
  079a115ae417106f3e7f42b0272b866d  gcc/opts-jobserver.h
! d3506b15c10420065e9694e2444a970b  gcc/opts.cc
  7297ae8caf0c34afb0609151e7e3f987  gcc/opts.h
  b7a4b3edfca283f972cdeb23102a28a4  gcc/ordered-hash-map-tests.cc
  fccd951e3de91d49d3824e482c12e070  gcc/ordered-hash-map.h
*************** cd641a4dec9a0a4cf7cf888cfa37e386  gcc/pr
*** 7887,7895 ****
  be6c71b25f10a45cfc8d05a37affe9ed  gcc/pta-andersen.cc
  06e1fae8a3a5e17b39e472f88eb11819  gcc/pta-andersen.h
  555a319d44f0f4857aa378a1691e1d27  gcc/range-op-float.cc
! 6b98a6ea5f4292196168184e5e0f4476  gcc/range-op-mixed.h
  111e7e65fb598a1d21148e1b0f23744b  gcc/range-op-ptr.cc
! 1c6382bcceecc38e3891db2679154c58  gcc/range-op.cc
  24fea5bf4be00e9dba7bbeb8d52b4677  gcc/range-op.h
  e1edfa2841ce0f9e30db7b34a3a5a6d7  gcc/range.cc
  e1ebdb36533cc50099a4b487e7c70c49  gcc/range.h
--- 7887,7895 ----
  be6c71b25f10a45cfc8d05a37affe9ed  gcc/pta-andersen.cc
  06e1fae8a3a5e17b39e472f88eb11819  gcc/pta-andersen.h
  555a319d44f0f4857aa378a1691e1d27  gcc/range-op-float.cc
! 53d455d802bac0f8785f4bad4e26dd45  gcc/range-op-mixed.h
  111e7e65fb598a1d21148e1b0f23744b  gcc/range-op-ptr.cc
! be8b28fb67b0931819808433991d33af  gcc/range-op.cc
  24fea5bf4be00e9dba7bbeb8d52b4677  gcc/range-op.h
  e1edfa2841ce0f9e30db7b34a3a5a6d7  gcc/range.cc
  e1ebdb36533cc50099a4b487e7c70c49  gcc/range.h
*************** c08edc659010d9072c249418c1be7fe6  gcc/rt
*** 7962,8026 ****
  ecb31a48caf7998f695601ec7350bdc0  gcc/run-rtl-passes.cc
  c4bc204b62fdb61848c09abf05a60a9d  gcc/run-rtl-passes.h
  add9bd82fcec23469a4d0f7df03d9589  gcc/rust/CONTRIBUTING.md
! bebc744c355a021715bb48758eee5455  gcc/rust/ChangeLog
! 02ba89c4ee11e8c39d7b0d815e7d8ab9  gcc/rust/Make-lang.in
  f3527e161e6e2827d299c1a928ebe1c6  gcc/rust/README.md
! 6dd49c79cdf3440e03fd178e413b6fb8  gcc/rust/ast/rust-ast-builder.cc
  3714514495ced2204392eef66c900c13  gcc/rust/ast/rust-ast-builder.h
! c46e463062d522330bab1d75fb8ec726  gcc/rust/ast/rust-ast-collector.cc
! 4ab6dac0cf511cddc30cafb435f87896  gcc/rust/ast/rust-ast-collector.h
  494672e10e3cd2a3c29f72147b6e42e8  gcc/rust/ast/rust-ast-dump.cc
  e21cd4002e965dd8e32f6afb373d6ead  gcc/rust/ast/rust-ast-dump.h
  4b956fa2250010f85282d2ea3339d66f  gcc/rust/ast/rust-ast-formatting.cc
! b7a6c36df2259a9397bfe9376d14915c  gcc/rust/ast/rust-ast-formatting.h
! 1520397870a21ed323db6c2e5d64107e  gcc/rust/ast/rust-ast-fragment.cc
! f419aa5c0c96c075ac096b7fc99ba81a  gcc/rust/ast/rust-ast-fragment.h
! cc7a07d0d92e6a12688528dcfbfc6511  gcc/rust/ast/rust-ast-full-decls.h
  629186b05e52e76e5b8194df9669607d  gcc/rust/ast/rust-ast-full.h
! 6ad0a6bdd47abe0267ee7e73f6f63e19  gcc/rust/ast/rust-ast-visitor.cc
! 5d8eb4bd1c324efc64e5c004d70ec172  gcc/rust/ast/rust-ast-visitor.h
! 1b87dabc22715aa5b7d2d9cf7d7d662b  gcc/rust/ast/rust-ast.cc
! 75df25fe036e3e684c533cf82f530efb  gcc/rust/ast/rust-ast.h
! 3b6b8b59b34d5d60d0c046849c558b0d  gcc/rust/ast/rust-builtin-ast-nodes.h
! 1373253305e2b8a61c239759a676b523  gcc/rust/ast/rust-collect-lang-items.cc
  d526cc472464ac531167ac67e9139d7e  gcc/rust/ast/rust-collect-lang-items.h
! 95b468bc6271487302f9ad083cd8e191  gcc/rust/ast/rust-cond-compilation.h
! 6b78d507d548189212b807fdb988df88  gcc/rust/ast/rust-desugar-apit.cc
  fdb5fa620d782dcd2f969d2037c87a9c  gcc/rust/ast/rust-desugar-apit.h
! 6b822f8ae7c6287c708f10f60c2d7814  gcc/rust/ast/rust-desugar-for-loops.cc
  483d32cf56cee90ffee11f256666d42e  gcc/rust/ast/rust-desugar-for-loops.h
! 284cff78e8d3fe7d06886f825f449d4c  gcc/rust/ast/rust-desugar-question-mark.cc
  f7fb24547286c1046273fae16bc3b40c  gcc/rust/ast/rust-desugar-question-mark.h
  ce782a41f25cb7bab408fb56d3691217  gcc/rust/ast/rust-desugar-try-block.cc
  7f083f8b90958b45346c1ede8236b34b  gcc/rust/ast/rust-desugar-try-block.h
  e6d36246282c627ce4935b5006882cde  gcc/rust/ast/rust-desugar-while-let.cc
  8962928afafa7cdb402e49863510fee6  gcc/rust/ast/rust-desugar-while-let.h
! 6f510b3675ab7c56f4c5878e63d181a5  gcc/rust/ast/rust-expr.h
! 485ff71543c8db0d90612be264d91cff  gcc/rust/ast/rust-expression-yeast.cc
! 7436289b8a48b84ec5d75c138cab6f3d  gcc/rust/ast/rust-expression-yeast.h
! 8431184a8fe616547ba53c4bec69e873  gcc/rust/ast/rust-fmt.cc
! 223a56a9cf64e5cd5cecd9735dfc92a8  gcc/rust/ast/rust-fmt.h
! 133eafd80f42be86d15e705ead7d2c0c  gcc/rust/ast/rust-item.h
  d422ca6fdef486f353c824585452e285  gcc/rust/ast/rust-macro.h
! 2711fdcec6da8db426e0ea2e044495eb  gcc/rust/ast/rust-path.cc
! 4a222d00e99ecb0e326bcc4d210edfdc  gcc/rust/ast/rust-path.h
! 4f49a09546ffc2166449496e2fd3958d  gcc/rust/ast/rust-pattern.cc
! 130a56d2d2f22b1b01328a951f989095  gcc/rust/ast/rust-pattern.h
! ed6c0cb758442b73c02cd2e9b2d457e0  gcc/rust/ast/rust-stmt.h
! d18348e9a6d3fc5f6aaee83e7614aa1c  gcc/rust/ast/rust-type.h
  39774c8ec83393047e843c9b8dff6822  gcc/rust/backend/rust-builtins.cc
  064ce3571a08f20977f4980b508ce086  gcc/rust/backend/rust-builtins.h
  f2be38c1f6b741ba160f5ddb9b550a10  gcc/rust/backend/rust-compile-asm.cc
  cfc6dfa694ca09488dbc704e558daa0d  gcc/rust/backend/rust-compile-asm.h
! cdb09ea37a7b683604774e233f5f9047  gcc/rust/backend/rust-compile-base.cc
! 1611735a729c8d6134121714be392d07  gcc/rust/backend/rust-compile-base.h
  2d5e409c84aba45bd3a18bd49fc296ef  gcc/rust/backend/rust-compile-block.cc
  d0a4f7913bccafe98174b5e4b5cebfa6  gcc/rust/backend/rust-compile-block.h
  8d754665d1c624cb4d92e1417e4b1235  gcc/rust/backend/rust-compile-context.cc
! 7faf26e77f48f6a4c342c27b2d884eeb  gcc/rust/backend/rust-compile-context.h
! c4eefe7770375970d7997afdd2a0c737  gcc/rust/backend/rust-compile-expr.cc
  5fa9d206f637b2f442ddd04db0d88346  gcc/rust/backend/rust-compile-expr.h
! bdd9c27c46d5b67cee4389fee210f33a  gcc/rust/backend/rust-compile-extern.h
  96023f10d704a5f5aa3aa2126eac4219  gcc/rust/backend/rust-compile-fnparam.cc
  e525943b8d7380cbc76915f9e460adab  gcc/rust/backend/rust-compile-fnparam.h
  1bb9958624b1c18507129a60e9be23e5  gcc/rust/backend/rust-compile-implitem.cc
--- 7962,8028 ----
  ecb31a48caf7998f695601ec7350bdc0  gcc/run-rtl-passes.cc
  c4bc204b62fdb61848c09abf05a60a9d  gcc/run-rtl-passes.h
  add9bd82fcec23469a4d0f7df03d9589  gcc/rust/CONTRIBUTING.md
! 237e16cac4fdc474a6b9f8497d83ff93  gcc/rust/ChangeLog
! 71972a823341f4ee0b2af7347ef7a633  gcc/rust/Make-lang.in
  f3527e161e6e2827d299c1a928ebe1c6  gcc/rust/README.md
! 27f492ab17f50d840e1e0fd32a89c84a  gcc/rust/ast/rust-ast-builder.cc
  3714514495ced2204392eef66c900c13  gcc/rust/ast/rust-ast-builder.h
! 21d814f35d0144aa47c15e8301b13890  gcc/rust/ast/rust-ast-collector.cc
! 2218748445677411bd6873a3c03ccd5d  gcc/rust/ast/rust-ast-collector.h
  494672e10e3cd2a3c29f72147b6e42e8  gcc/rust/ast/rust-ast-dump.cc
  e21cd4002e965dd8e32f6afb373d6ead  gcc/rust/ast/rust-ast-dump.h
  4b956fa2250010f85282d2ea3339d66f  gcc/rust/ast/rust-ast-formatting.cc
! fa22a966da9420728a72f8164b29aeef  gcc/rust/ast/rust-ast-formatting.h
! 9a53c932a6dd665e6f534655a2c1096c  gcc/rust/ast/rust-ast-fragment.cc
! 103daadfd22fca4284b640346db93bbe  gcc/rust/ast/rust-ast-fragment.h
! 992387837a52f557bacc6da44eef8c00  gcc/rust/ast/rust-ast-full-decls.h
  629186b05e52e76e5b8194df9669607d  gcc/rust/ast/rust-ast-full.h
! 637e07bd2076b6186d850a206b9ebb74  gcc/rust/ast/rust-ast-pointer-visitor.cc
! ab4843ea68c29da6b2a1c9981b059e06  gcc/rust/ast/rust-ast-pointer-visitor.h
! 9ab1d23308048adc03212cb5ea086d07  gcc/rust/ast/rust-ast-visitor.cc
! 0adfcf6a63038808c3009e74ef1c6a39  gcc/rust/ast/rust-ast-visitor.h
! 1eb26fc80399f5048ea14268eba92770  gcc/rust/ast/rust-ast.cc
! 4410fe00611edd66a36aeb28cb79ee1e  gcc/rust/ast/rust-ast.h
! 47cbbb053e5e83cfcb63e85fe1777921  gcc/rust/ast/rust-builtin-ast-nodes.h
! 6c128fd9e73db1e26ff7ddbc86f69722  gcc/rust/ast/rust-collect-lang-items.cc
  d526cc472464ac531167ac67e9139d7e  gcc/rust/ast/rust-collect-lang-items.h
! 5e1186d3e2fc2b40025f0fd702709ed6  gcc/rust/ast/rust-cond-compilation.h
! 7f01fb6a74d5d7a7207b6c71be4acd0d  gcc/rust/ast/rust-desugar-apit.cc
  fdb5fa620d782dcd2f969d2037c87a9c  gcc/rust/ast/rust-desugar-apit.h
! 59863bb08a4cdcff4a0609f1aff1ed0e  gcc/rust/ast/rust-desugar-for-loops.cc
  483d32cf56cee90ffee11f256666d42e  gcc/rust/ast/rust-desugar-for-loops.h
! aa3af3c8d8e17d1a6440be7984af6a0f  gcc/rust/ast/rust-desugar-question-mark.cc
  f7fb24547286c1046273fae16bc3b40c  gcc/rust/ast/rust-desugar-question-mark.h
  ce782a41f25cb7bab408fb56d3691217  gcc/rust/ast/rust-desugar-try-block.cc
  7f083f8b90958b45346c1ede8236b34b  gcc/rust/ast/rust-desugar-try-block.h
  e6d36246282c627ce4935b5006882cde  gcc/rust/ast/rust-desugar-while-let.cc
  8962928afafa7cdb402e49863510fee6  gcc/rust/ast/rust-desugar-while-let.h
! 3403f6d26cdb07e406b3a7231b5ae964  gcc/rust/ast/rust-expr.h
! 56b2d9b9ff0f8e730b276195a3614e07  gcc/rust/ast/rust-expression-yeast.cc
! 5738296d90ef786d16f052f0c0ed613f  gcc/rust/ast/rust-expression-yeast.h
! b0a8d5728f73b0493b0b4aae04568187  gcc/rust/ast/rust-fmt.cc
! 60e268e282585c3236c30dd4c3dd8f54  gcc/rust/ast/rust-fmt.h
! ae61b2953e90353ab3719e3f99633865  gcc/rust/ast/rust-item.h
  d422ca6fdef486f353c824585452e285  gcc/rust/ast/rust-macro.h
! 277825a1ab6df255dbe079bb8560e311  gcc/rust/ast/rust-path.cc
! 1a331eb0cd7eedec74fbb2ce3677449b  gcc/rust/ast/rust-path.h
! d9747e9282da6807a2e306f6c66c6766  gcc/rust/ast/rust-pattern.cc
! d8eee9961e4e8aa0be1ebd72b1210cce  gcc/rust/ast/rust-pattern.h
! 9525a610723ce5d0d54bac5fe0c23c2b  gcc/rust/ast/rust-stmt.h
! bb6992ee39f25d0e4ec4867b2a979c8f  gcc/rust/ast/rust-type.h
  39774c8ec83393047e843c9b8dff6822  gcc/rust/backend/rust-builtins.cc
  064ce3571a08f20977f4980b508ce086  gcc/rust/backend/rust-builtins.h
  f2be38c1f6b741ba160f5ddb9b550a10  gcc/rust/backend/rust-compile-asm.cc
  cfc6dfa694ca09488dbc704e558daa0d  gcc/rust/backend/rust-compile-asm.h
! 3c9ab5475ae60dbf39abef91e6222bcd  gcc/rust/backend/rust-compile-base.cc
! a168bb70ef7e4bd046bf704abb0e5739  gcc/rust/backend/rust-compile-base.h
  2d5e409c84aba45bd3a18bd49fc296ef  gcc/rust/backend/rust-compile-block.cc
  d0a4f7913bccafe98174b5e4b5cebfa6  gcc/rust/backend/rust-compile-block.h
  8d754665d1c624cb4d92e1417e4b1235  gcc/rust/backend/rust-compile-context.cc
! 04b8950ce8b7169cf46dee3bd66b65ad  gcc/rust/backend/rust-compile-context.h
! 49178dc9d231ca7e20c8031c5536c088  gcc/rust/backend/rust-compile-expr.cc
  5fa9d206f637b2f442ddd04db0d88346  gcc/rust/backend/rust-compile-expr.h
! 6e6bc07f0b214a00ae4af6096f07a7b0  gcc/rust/backend/rust-compile-extern.h
  96023f10d704a5f5aa3aa2126eac4219  gcc/rust/backend/rust-compile-fnparam.cc
  e525943b8d7380cbc76915f9e460adab  gcc/rust/backend/rust-compile-fnparam.h
  1bb9958624b1c18507129a60e9be23e5  gcc/rust/backend/rust-compile-implitem.cc
*************** ee0054c15512a93ccc6bec6718c95863  gcc/ru
*** 8029,8049 ****
  a1fb8689400958af8126ae9c477c873e  gcc/rust/backend/rust-compile-intrinsic.h
  baa1a06481456fc6c8d5809aa7185fc7  gcc/rust/backend/rust-compile-item.cc
  3ce37ad182e3bedbc0013ae3dcb6b0ed  gcc/rust/backend/rust-compile-item.h
! 45d1c706d5310e0c6bb1658ed5981409  gcc/rust/backend/rust-compile-pattern.cc
  cd4b0541904d2e28f01b23b2a117508e  gcc/rust/backend/rust-compile-pattern.h
  cd711182d62e81ac9cb36e89d0ab5062  gcc/rust/backend/rust-compile-proc-macro.cc
! 4a0f5bc07f53f93525bed74c33141f73  gcc/rust/backend/rust-compile-resolve-path.cc
  a02df3439a425a492f39168431dbf58b  gcc/rust/backend/rust-compile-resolve-path.h
  1146a28a080b99e199ba9103e1629866  gcc/rust/backend/rust-compile-stmt.cc
  8d042d63efac54929399df3c7b8741f9  gcc/rust/backend/rust-compile-stmt.h
  943e800783a5c6e0e934066fe1478b65  gcc/rust/backend/rust-compile-struct-field-expr.cc
  3b61313140b254e7402b2ab5ed53d760  gcc/rust/backend/rust-compile-struct-field-expr.h
! 4c7460409dbe5316108e5df693942b98  gcc/rust/backend/rust-compile-type.cc
! b509fbe19ec81374f434934bf7f1db59  gcc/rust/backend/rust-compile-type.h
! 4d8be376e4c5ea806bd47639bb857efd  gcc/rust/backend/rust-compile-var-decl.h
! bd5a2dcc98c2d6d545a18d5dc44734f1  gcc/rust/backend/rust-compile.cc
  0de4696fca9f7f20e245ed49dbd8bed7  gcc/rust/backend/rust-compile.h
! a2a3196d3c79aeb5c9cc5214db45a039  gcc/rust/backend/rust-constexpr.cc
  8b7d1489d3387b799f0272f52df62581  gcc/rust/backend/rust-constexpr.h
  bef8332d7c99228e46b17e35e62ab385  gcc/rust/backend/rust-mangle-legacy.cc
  ded63052cb7097de9c2443746c403f00  gcc/rust/backend/rust-mangle-v0.cc
--- 8031,8051 ----
  a1fb8689400958af8126ae9c477c873e  gcc/rust/backend/rust-compile-intrinsic.h
  baa1a06481456fc6c8d5809aa7185fc7  gcc/rust/backend/rust-compile-item.cc
  3ce37ad182e3bedbc0013ae3dcb6b0ed  gcc/rust/backend/rust-compile-item.h
! 47114ec5093e42104960f135079a112c  gcc/rust/backend/rust-compile-pattern.cc
  cd4b0541904d2e28f01b23b2a117508e  gcc/rust/backend/rust-compile-pattern.h
  cd711182d62e81ac9cb36e89d0ab5062  gcc/rust/backend/rust-compile-proc-macro.cc
! 01afcb5da0eaa135cbe24df78f4b7c05  gcc/rust/backend/rust-compile-resolve-path.cc
  a02df3439a425a492f39168431dbf58b  gcc/rust/backend/rust-compile-resolve-path.h
  1146a28a080b99e199ba9103e1629866  gcc/rust/backend/rust-compile-stmt.cc
  8d042d63efac54929399df3c7b8741f9  gcc/rust/backend/rust-compile-stmt.h
  943e800783a5c6e0e934066fe1478b65  gcc/rust/backend/rust-compile-struct-field-expr.cc
  3b61313140b254e7402b2ab5ed53d760  gcc/rust/backend/rust-compile-struct-field-expr.h
! d01f0546d32ee5ae0e2b0e79b12b3be8  gcc/rust/backend/rust-compile-type.cc
! bd1497a225bbe26dd01b8aef8b89cf3f  gcc/rust/backend/rust-compile-type.h
! 3a834a862ca7f5516856d25250d4f89e  gcc/rust/backend/rust-compile-var-decl.h
! 55c4d864e83808cea66fab2e7e5aee72  gcc/rust/backend/rust-compile.cc
  0de4696fca9f7f20e245ed49dbd8bed7  gcc/rust/backend/rust-compile.h
! 80c8ab121ed5ee8cc9d7e64e280aeb82  gcc/rust/backend/rust-constexpr.cc
  8b7d1489d3387b799f0272f52df62581  gcc/rust/backend/rust-constexpr.h
  bef8332d7c99228e46b17e35e62ab385  gcc/rust/backend/rust-mangle-legacy.cc
  ded63052cb7097de9c2443746c403f00  gcc/rust/backend/rust-mangle-v0.cc
*************** ad886f79708dd374dbc6a3e224533e14  gcc/ru
*** 8112,8122 ****
  fa3c76359487ca3f3346e24a4f3358e4  gcc/rust/checks/errors/borrowck/polonius/rust-polonius.h
  c2d95a91701508d9113ae71c2719d897  gcc/rust/checks/errors/borrowck/rust-bir-builder-expr-stmt.cc
  47464bc7c6a9c9362cc5bbcbbdff5a91  gcc/rust/checks/errors/borrowck/rust-bir-builder-expr-stmt.h
! 40032b8fc84237812877c47f2bfa8666  gcc/rust/checks/errors/borrowck/rust-bir-builder-internal.h
  0737404663c96140b303fcbe15c27282  gcc/rust/checks/errors/borrowck/rust-bir-builder-lazyboolexpr.h
! 9e40df5f42f7638a4a7604cf8c30b83c  gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.cc
  bbb6b401287aeefeddf82860e011dd85  gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.h
! 72bcf7ce5f56655c03f587db8e16c745  gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h
  38cef03aee9d5c550a78c56952b2791e  gcc/rust/checks/errors/borrowck/rust-bir-builder.h
  0f58055d50d4bdb56acf9a07bdf55913  gcc/rust/checks/errors/borrowck/rust-bir-dump.cc
  3d1d580931425b21ef771bb7fbc06269  gcc/rust/checks/errors/borrowck/rust-bir-dump.h
--- 8114,8124 ----
  fa3c76359487ca3f3346e24a4f3358e4  gcc/rust/checks/errors/borrowck/polonius/rust-polonius.h
  c2d95a91701508d9113ae71c2719d897  gcc/rust/checks/errors/borrowck/rust-bir-builder-expr-stmt.cc
  47464bc7c6a9c9362cc5bbcbbdff5a91  gcc/rust/checks/errors/borrowck/rust-bir-builder-expr-stmt.h
! e62afd6bedb34edce94b33992569e4e6  gcc/rust/checks/errors/borrowck/rust-bir-builder-internal.h
  0737404663c96140b303fcbe15c27282  gcc/rust/checks/errors/borrowck/rust-bir-builder-lazyboolexpr.h
! 6305f4d04481595395e6628d3dda2a6f  gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.cc
  bbb6b401287aeefeddf82860e011dd85  gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.h
! e702b3642ee54a6a9748312cb4dd019e  gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h
  38cef03aee9d5c550a78c56952b2791e  gcc/rust/checks/errors/borrowck/rust-bir-builder.h
  0f58055d50d4bdb56acf9a07bdf55913  gcc/rust/checks/errors/borrowck/rust-bir-dump.cc
  3d1d580931425b21ef771bb7fbc06269  gcc/rust/checks/errors/borrowck/rust-bir-dump.h
*************** c62ad0b7d7912fb0902b5edd26c0239a  gcc/ru
*** 8129,8176 ****
  e30cd7ae36132321a16ee23e46ef569d  gcc/rust/checks/errors/borrowck/rust-borrow-checker-diagnostics.h
  8a4b180b21798e53955cc8d26ee08af1  gcc/rust/checks/errors/borrowck/rust-borrow-checker.cc
  6998d3562ab4b5a22db0a644a774bf34  gcc/rust/checks/errors/borrowck/rust-borrow-checker.h
! f0e51dff89e63151b239454037feab78  gcc/rust/checks/errors/borrowck/rust-function-collector.h
! 32e213dff722426f97836eef4e58c492  gcc/rust/checks/errors/privacy/rust-privacy-check.cc
  3da657013b217061fe50f867abad385d  gcc/rust/checks/errors/privacy/rust-privacy-check.h
  41958e3868642abaa915c9f7ce14838f  gcc/rust/checks/errors/privacy/rust-privacy-common.h
  3a65622c9ada7db251b7cece7376f02b  gcc/rust/checks/errors/privacy/rust-privacy-ctx.cc
  17e10c312b595af4abcf477a5c0d25e0  gcc/rust/checks/errors/privacy/rust-privacy-ctx.h
! 1ce41f26165355a622514d8edc3aa575  gcc/rust/checks/errors/privacy/rust-privacy-reporter.cc
! 9469ab4d718e27ca81d8ac937c1889b6  gcc/rust/checks/errors/privacy/rust-privacy-reporter.h
  7afd2e64866a93982cf63a617444202d  gcc/rust/checks/errors/privacy/rust-pub-restricted-visitor.cc
  e089325331566be03e4a844c454d02c9  gcc/rust/checks/errors/privacy/rust-pub-restricted-visitor.h
  b3185e47f2d21f00afc3dc4a8dd2d11b  gcc/rust/checks/errors/privacy/rust-reachability.cc
  63ebea218badc639cc7db7df1d604e12  gcc/rust/checks/errors/privacy/rust-reachability.h
! 314a6d18587c6c94672ded1df3988ead  gcc/rust/checks/errors/privacy/rust-visibility-resolver.cc
! faaa6683b382177d7e39c93079648e98  gcc/rust/checks/errors/privacy/rust-visibility-resolver.h
  58e655e2eb795a961d43bad8c29f47cb  gcc/rust/checks/errors/rust-ast-validation.cc
  8b2205953da2f181b2d51187aefbffab  gcc/rust/checks/errors/rust-ast-validation.h
! a27ec1958b2cca6d3529a75f0d5e2d78  gcc/rust/checks/errors/rust-const-checker.cc
! 2139e14d0a70f35f63b8f61b22e87a62  gcc/rust/checks/errors/rust-const-checker.h
! 770d1eaeae7a9fc7f04ef62e6f33859e  gcc/rust/checks/errors/rust-feature-gate.cc
! 5a932cefc939038ecbf29a5e10b317d5  gcc/rust/checks/errors/rust-feature-gate.h
! e76320268e1edd88b6449c7e90ab12a9  gcc/rust/checks/errors/rust-feature.cc
! 94ec63b6dec3b278430e4623056b27c0  gcc/rust/checks/errors/rust-feature.h
! 601bc807ce8d648e606fc15f6676a421  gcc/rust/checks/errors/rust-hir-pattern-analysis.cc
! f68d8cfaf0a2c51ecbc91235794b43a8  gcc/rust/checks/errors/rust-hir-pattern-analysis.h
! e030624767cd717222d3626d9d62d9a9  gcc/rust/checks/errors/rust-readonly-check.cc
! 3d9c9e625336a7785ee74c5dc9dbe5db  gcc/rust/checks/errors/rust-readonly-check.h
! f22cff707283c92f3a6391ba91656e5e  gcc/rust/checks/errors/rust-readonly-check2.cc
! df77b7829b2693ebd70aee0a0ff751d7  gcc/rust/checks/errors/rust-readonly-check2.h
! 78a630d62c16e5c14d8d49a378ae921a  gcc/rust/checks/errors/rust-unsafe-checker.cc
! 386a646f3d0d23d8bc3a1da122499d01  gcc/rust/checks/errors/rust-unsafe-checker.h
! daeb95fb25e32d1dba7a700a5dd542ed  gcc/rust/checks/lints/rust-lint-marklive-base.h
  372ef6c64dc848ca737e4f258d2e9f32  gcc/rust/checks/lints/rust-lint-marklive.cc
  1014cd28f28fb3ce945cb34ad0190d8d  gcc/rust/checks/lints/rust-lint-marklive.h
  3d12ce22fc794ea9c3de54e7ab40bdb9  gcc/rust/checks/lints/rust-lint-scan-deadcode.h
  59a3222b3a126357249024c71380305a  gcc/rust/checks/lints/rust-lint-unused-var.cc
  31a28464a707538b3feb2cca81d0baca  gcc/rust/checks/lints/rust-lint-unused-var.h
  fa5872ac507a48a11a82370b396b9110  gcc/rust/config-lang.in
! 8f262f58f5d827757f0260cd79fdcc7c  gcc/rust/expand/rust-cfg-strip.cc
! bba00957626d1998cf329a5b0f7a60b4  gcc/rust/expand/rust-cfg-strip.h
! 5bf105dcc7a5563508ce8afd6d5477a8  gcc/rust/expand/rust-derive-clone.cc
  f9e74c7fa1a07a3ba930fb235c9b6000  gcc/rust/expand/rust-derive-clone.h
! 1c98aff64589f97a1709c2ddb46d3ef4  gcc/rust/expand/rust-derive-cmp-common.cc
  95468c29b0802383dba6c20505022ee6  gcc/rust/expand/rust-derive-cmp-common.h
  09be27af0eb6fd26f67529031ae051d6  gcc/rust/expand/rust-derive-copy.cc
  53d56dcba9c607680c3d23f6f39edf1e  gcc/rust/expand/rust-derive-copy.h
--- 8131,8176 ----
  e30cd7ae36132321a16ee23e46ef569d  gcc/rust/checks/errors/borrowck/rust-borrow-checker-diagnostics.h
  8a4b180b21798e53955cc8d26ee08af1  gcc/rust/checks/errors/borrowck/rust-borrow-checker.cc
  6998d3562ab4b5a22db0a644a774bf34  gcc/rust/checks/errors/borrowck/rust-borrow-checker.h
! c3cc0e0595e90d171a25b08f7f4f7234  gcc/rust/checks/errors/borrowck/rust-function-collector.h
! 770d1eaeae7a9fc7f04ef62e6f33859e  gcc/rust/checks/errors/feature/rust-feature-gate.cc
! 5a932cefc939038ecbf29a5e10b317d5  gcc/rust/checks/errors/feature/rust-feature-gate.h
! e76320268e1edd88b6449c7e90ab12a9  gcc/rust/checks/errors/feature/rust-feature.cc
! 94ec63b6dec3b278430e4623056b27c0  gcc/rust/checks/errors/feature/rust-feature.h
! 7aea75e33b055d67c484a9a5c0714b94  gcc/rust/checks/errors/privacy/rust-privacy-check.cc
  3da657013b217061fe50f867abad385d  gcc/rust/checks/errors/privacy/rust-privacy-check.h
  41958e3868642abaa915c9f7ce14838f  gcc/rust/checks/errors/privacy/rust-privacy-common.h
  3a65622c9ada7db251b7cece7376f02b  gcc/rust/checks/errors/privacy/rust-privacy-ctx.cc
  17e10c312b595af4abcf477a5c0d25e0  gcc/rust/checks/errors/privacy/rust-privacy-ctx.h
! 43a85c736d90fb5caf1a0073e0c36c9a  gcc/rust/checks/errors/privacy/rust-privacy-reporter.cc
! b8838df96e53cec4582bd9b635d433ae  gcc/rust/checks/errors/privacy/rust-privacy-reporter.h
  7afd2e64866a93982cf63a617444202d  gcc/rust/checks/errors/privacy/rust-pub-restricted-visitor.cc
  e089325331566be03e4a844c454d02c9  gcc/rust/checks/errors/privacy/rust-pub-restricted-visitor.h
  b3185e47f2d21f00afc3dc4a8dd2d11b  gcc/rust/checks/errors/privacy/rust-reachability.cc
  63ebea218badc639cc7db7df1d604e12  gcc/rust/checks/errors/privacy/rust-reachability.h
! 9b405604643cad0ac64b61e15a661eb9  gcc/rust/checks/errors/privacy/rust-visibility-resolver.cc
! 75733bdf9e6e2bac6a80f53906b2d28c  gcc/rust/checks/errors/privacy/rust-visibility-resolver.h
  58e655e2eb795a961d43bad8c29f47cb  gcc/rust/checks/errors/rust-ast-validation.cc
  8b2205953da2f181b2d51187aefbffab  gcc/rust/checks/errors/rust-ast-validation.h
! fe2962dc226b0768f5f3aa683fb688b2  gcc/rust/checks/errors/rust-const-checker.cc
! faeb5b075e128e3fc4bfd4ff53ae06d2  gcc/rust/checks/errors/rust-const-checker.h
! 92c0915329dfb1f6cc16f7f18e692efc  gcc/rust/checks/errors/rust-hir-pattern-analysis.cc
! 3bad1521f66fe645b6abab615173b468  gcc/rust/checks/errors/rust-hir-pattern-analysis.h
! 304eb5adec53738cfc9aa7d7291d49c8  gcc/rust/checks/errors/rust-readonly-check.cc
! a45e19c6f651b6f8bd13d2a4e08e4cc3  gcc/rust/checks/errors/rust-readonly-check.h
! 67fc5dadc9f40354aaea26f1ec37dc48  gcc/rust/checks/errors/rust-unsafe-checker.cc
! 9d4322b4fbef222ac097722515f88171  gcc/rust/checks/errors/rust-unsafe-checker.h
! 0dbb42584b37485114ad1f2af909b934  gcc/rust/checks/lints/rust-lint-marklive-base.h
  372ef6c64dc848ca737e4f258d2e9f32  gcc/rust/checks/lints/rust-lint-marklive.cc
  1014cd28f28fb3ce945cb34ad0190d8d  gcc/rust/checks/lints/rust-lint-marklive.h
  3d12ce22fc794ea9c3de54e7ab40bdb9  gcc/rust/checks/lints/rust-lint-scan-deadcode.h
  59a3222b3a126357249024c71380305a  gcc/rust/checks/lints/rust-lint-unused-var.cc
  31a28464a707538b3feb2cca81d0baca  gcc/rust/checks/lints/rust-lint-unused-var.h
  fa5872ac507a48a11a82370b396b9110  gcc/rust/config-lang.in
! 0060cb7035fce818864cc09fb54cbf69  gcc/rust/expand/rust-cfg-strip.cc
! 68c158af32142894a708b84d1f0a4aee  gcc/rust/expand/rust-cfg-strip.h
! 1aec8015302d678642557942531e895e  gcc/rust/expand/rust-derive-clone.cc
  f9e74c7fa1a07a3ba930fb235c9b6000  gcc/rust/expand/rust-derive-clone.h
! 8855181d2ac9f699a66425ab32e7092d  gcc/rust/expand/rust-derive-cmp-common.cc
  95468c29b0802383dba6c20505022ee6  gcc/rust/expand/rust-derive-cmp-common.h
  09be27af0eb6fd26f67529031ae051d6  gcc/rust/expand/rust-derive-copy.cc
  53d56dcba9c607680c3d23f6f39edf1e  gcc/rust/expand/rust-derive-copy.h
*************** f9e74c7fa1a07a3ba930fb235c9b6000  gcc/ru
*** 8178,8265 ****
  c3e6cc7662d1ef8947fb988077f97569  gcc/rust/expand/rust-derive-debug.h
  26a6ab59cd92661a07dc019de28a2144  gcc/rust/expand/rust-derive-default.cc
  df56b23b19c01cfc70d4a9da2069fa56  gcc/rust/expand/rust-derive-default.h
! bd18141c7f4dcb2d2ad455dcfb51dad1  gcc/rust/expand/rust-derive-eq.cc
  a49bed8382a0e447351a98fa8d1d5c31  gcc/rust/expand/rust-derive-eq.h
! dc1403097e3cdf2b51ad17931dda537a  gcc/rust/expand/rust-derive-hash.cc
  15af7b16e8b9a6a8a4359622ece14733  gcc/rust/expand/rust-derive-hash.h
! 026aef1a3c89ebeb05ff3dd4719ac9fb  gcc/rust/expand/rust-derive-ord.cc
  8717276cd5b4ffe5cd71e8b31217d4aa  gcc/rust/expand/rust-derive-ord.h
! cb6f746db41b7c98e3e053b8b60436ff  gcc/rust/expand/rust-derive-partial-eq.cc
  4c08872aac729ae411f86212487397e0  gcc/rust/expand/rust-derive-partial-eq.h
  73015c96d99d7296b592097c82981cec  gcc/rust/expand/rust-derive.cc
! 92d2e637edb856cc6872b140b26419ec  gcc/rust/expand/rust-derive.h
  2bf0b3ec8f96214e9e951a12aa0a2bb8  gcc/rust/expand/rust-expand-format-args.cc
  3212518ba7ade95bb86b3581ea623f4f  gcc/rust/expand/rust-expand-format-args.h
! 7cd200a87aff0dd4e005749ad8ee94e7  gcc/rust/expand/rust-expand-visitor.cc
! 882c99f39e6433db6c589ae49942d134  gcc/rust/expand/rust-expand-visitor.h
! edaa046e3090c352298e289c0984a0f2  gcc/rust/expand/rust-macro-builtins-asm.cc
  48269c7df7dead67e4185d80b217a76a  gcc/rust/expand/rust-macro-builtins-asm.h
! 48b3412b093621cd496f89698ee0f7b0  gcc/rust/expand/rust-macro-builtins-format-args.cc
  470ca31c9edf1792290a63da0ae3bdd7  gcc/rust/expand/rust-macro-builtins-helpers.cc
! 133f4f9b4be8b1d10da06c9ad20fe373  gcc/rust/expand/rust-macro-builtins-helpers.h
  f813ef580dce9d9b6c9a75e9577bdbe0  gcc/rust/expand/rust-macro-builtins-include.cc
  cfe6beb6d729f4b555ffc6493de34a20  gcc/rust/expand/rust-macro-builtins-location.cc
  7d4293c5bb91064c3bb11e2ec9bd1893  gcc/rust/expand/rust-macro-builtins-log-debug.cc
! a95cbaa800890b7f85cda477c6f40ce7  gcc/rust/expand/rust-macro-builtins-offset-of.cc
  277542c684eada894583030cf02b7424  gcc/rust/expand/rust-macro-builtins-test-bench.cc
  277542c684eada894583030cf02b7424  gcc/rust/expand/rust-macro-builtins-trait.cc
  e253e39de6ea2a67018f97fc8e838ef5  gcc/rust/expand/rust-macro-builtins-utility.cc
! d4f255f36b3a31c8b84d946c30dad96c  gcc/rust/expand/rust-macro-builtins.cc
  b0344bc54018de3abfa44322f6262176  gcc/rust/expand/rust-macro-builtins.h
! 0df5134d9f8c1b6565ae15f794e4b8e2  gcc/rust/expand/rust-macro-expand.cc
! e0f7a029dbe434c8fc935166b193348f  gcc/rust/expand/rust-macro-expand.h
  b4b31e238293e868394fdf9247353b30  gcc/rust/expand/rust-macro-invoc-lexer.cc
  df22bd0c18e9d6037a1dbfbd733f009a  gcc/rust/expand/rust-macro-invoc-lexer.h
! 5187e6a0563468c057d344c8935aa5b9  gcc/rust/expand/rust-macro-substitute-ctx.cc
! fbf525cd3b3ec9396b8c278d2a098d4e  gcc/rust/expand/rust-macro-substitute-ctx.h
  49dc46efca0e56504ad8787e4548f25f  gcc/rust/expand/rust-proc-macro-invoc-lexer.cc
  9a7011cdfca3c1d04ffe7ca8cd3a2537  gcc/rust/expand/rust-proc-macro-invoc-lexer.h
  7faead690d4bd47de7b4b5fe0c4fb7d7  gcc/rust/expand/rust-proc-macro.cc
  9568c3923de491cd646cd621c423458a  gcc/rust/expand/rust-proc-macro.h
  41d25dfc4b39b0ca6a0c9422ea1acdc1  gcc/rust/expand/rust-token-tree-desugar.cc
  35a7953321666f4ad8526473ae2a8db1  gcc/rust/expand/rust-token-tree-desugar.h
! c090da771aeaeb5ac71a9cdf772da9ed  gcc/rust/hir/rust-ast-lower-base.cc
! dbf0fe3e4bc1fd56bfb0ea1518ea47e4  gcc/rust/hir/rust-ast-lower-base.h
  2eecfd7677a55d9d177b5226d9a6aec1  gcc/rust/hir/rust-ast-lower-block.h
! aad603a39b27fdfad3cc2614aff9e4e4  gcc/rust/hir/rust-ast-lower-enumitem.h
! 2ccdfdbe6c49584fe194fe0a620e5a35  gcc/rust/hir/rust-ast-lower-expr.cc
  0bea9637721f19beb7661ba8cbc0eae6  gcc/rust/hir/rust-ast-lower-expr.h
! 1042b2d1a40021ea30d79101c9bd074a  gcc/rust/hir/rust-ast-lower-extern.h
  b4d59b1df9f1d6e27671a9e166c77abb  gcc/rust/hir/rust-ast-lower-format-args.cc
  1c9070543940e6d4a4dbb4d601d853ae  gcc/rust/hir/rust-ast-lower-format-args.h
! 9c43081abad3a71641876f29fb5d7786  gcc/rust/hir/rust-ast-lower-implitem.cc
! 5e7a1a73e8bcdecc0d93cade34ba477b  gcc/rust/hir/rust-ast-lower-implitem.h
! 2161e9e6d7b3686871aa9052c441b44a  gcc/rust/hir/rust-ast-lower-item.cc
  4692f2513fc1cf935117a527388b3633  gcc/rust/hir/rust-ast-lower-item.h
! de0e9f3e558d5ceb386969e6332e0a96  gcc/rust/hir/rust-ast-lower-pattern.cc
  9ed55743496bcf0607042817cfa4b0d8  gcc/rust/hir/rust-ast-lower-pattern.h
  5b0f3b0dffc07b108851141d7b749598  gcc/rust/hir/rust-ast-lower-stmt.cc
  af09b97c0baeff87520d8face05b8f05  gcc/rust/hir/rust-ast-lower-stmt.h
  b86ab6b1f3ddb71091146e2d7265bd7f  gcc/rust/hir/rust-ast-lower-struct-field-expr.h
  a3f9b9d71a7b0a056ea2218035dd8dad  gcc/rust/hir/rust-ast-lower-type.cc
  2144c5ed50fecb7465bad4f0676110be  gcc/rust/hir/rust-ast-lower-type.h
! 9bce9060147bee95c6d2d421d68f2d45  gcc/rust/hir/rust-ast-lower.cc
  dfd71f28a4e33f88e4f9f845a85eff57  gcc/rust/hir/rust-ast-lower.h
! 75212e5860b67e1da1360e70b8b1be09  gcc/rust/hir/rust-hir-dump.cc
! 7f5b736fe50fc6c1ace35c6a1826e007  gcc/rust/hir/rust-hir-dump.h
  9ae488c2548387541bb760eaff79fbe9  gcc/rust/hir/tree/rust-hir-attrs.h
  7703b12f41d395a71eb5420f6c0a7ba7  gcc/rust/hir/tree/rust-hir-bound-abstract.h
  8f81aae1c3676476d16c5c42bfdc499a  gcc/rust/hir/tree/rust-hir-bound.h
  ef8ae85d1fae88e345d454cc9cd6be61  gcc/rust/hir/tree/rust-hir-expr-abstract.h
  335d221837d49923d80289f790780f10  gcc/rust/hir/tree/rust-hir-expr.cc
  5d4cbccd2f59ef41fc3dd84351775480  gcc/rust/hir/tree/rust-hir-expr.h
! 25d013cecd36a5d8059cfb74631d80f5  gcc/rust/hir/tree/rust-hir-full-decls.h
  e872fd48a9851c4ec4c3171c007d112d  gcc/rust/hir/tree/rust-hir-full.h
  cf64af347e4de1f3259e0ba179d8e53b  gcc/rust/hir/tree/rust-hir-generic-param.cc
  43725b1aeba18092d28ebd33a73e4462  gcc/rust/hir/tree/rust-hir-generic-param.h
  605269fb7d6c0f38be45a552e2446d9b  gcc/rust/hir/tree/rust-hir-item.cc
! 0d1546380caf6d49ab67c59a7bae7d7c  gcc/rust/hir/tree/rust-hir-item.h
  9f4e7a70392e148fe75decd40598a2d9  gcc/rust/hir/tree/rust-hir-literal.h
  f40fe76efdee3810473f09205ea63119  gcc/rust/hir/tree/rust-hir-node.h
  46af2c5116f73b3da4d0bc13d9cd86f8  gcc/rust/hir/tree/rust-hir-path.cc
  d1fbad563a9af986959aeb87f576564e  gcc/rust/hir/tree/rust-hir-path.h
  ee67550806e0bdf8bb66f8d3be82d6fa  gcc/rust/hir/tree/rust-hir-pattern-abstract.h
! 881d14cd309e9397caa1f94982548a4a  gcc/rust/hir/tree/rust-hir-pattern.h
  e55c4f7404915fb3515e09a7441125a5  gcc/rust/hir/tree/rust-hir-simple-path.h
  22283c03c1dc5ac012096d395c9414c2  gcc/rust/hir/tree/rust-hir-stmt.cc
  d231530a896626f20475091e1168963d  gcc/rust/hir/tree/rust-hir-stmt.h
--- 8178,8265 ----
  c3e6cc7662d1ef8947fb988077f97569  gcc/rust/expand/rust-derive-debug.h
  26a6ab59cd92661a07dc019de28a2144  gcc/rust/expand/rust-derive-default.cc
  df56b23b19c01cfc70d4a9da2069fa56  gcc/rust/expand/rust-derive-default.h
! f18936cc2720cc1f3601c72761020cd9  gcc/rust/expand/rust-derive-eq.cc
  a49bed8382a0e447351a98fa8d1d5c31  gcc/rust/expand/rust-derive-eq.h
! 03e771e07ef5896ed17a91fe1f469360  gcc/rust/expand/rust-derive-hash.cc
  15af7b16e8b9a6a8a4359622ece14733  gcc/rust/expand/rust-derive-hash.h
! ee795bec19a1b0d9196f4ce5a7a88564  gcc/rust/expand/rust-derive-ord.cc
  8717276cd5b4ffe5cd71e8b31217d4aa  gcc/rust/expand/rust-derive-ord.h
! cee4cea0688d7fd714aa7f1f220dd3ef  gcc/rust/expand/rust-derive-partial-eq.cc
  4c08872aac729ae411f86212487397e0  gcc/rust/expand/rust-derive-partial-eq.h
  73015c96d99d7296b592097c82981cec  gcc/rust/expand/rust-derive.cc
! 81e2b0e997b5a9d4a7e99b81fa071334  gcc/rust/expand/rust-derive.h
  2bf0b3ec8f96214e9e951a12aa0a2bb8  gcc/rust/expand/rust-expand-format-args.cc
  3212518ba7ade95bb86b3581ea623f4f  gcc/rust/expand/rust-expand-format-args.h
! 61f942e3bc1c240c767f00e1be34e176  gcc/rust/expand/rust-expand-visitor.cc
! 4d58b7326148b1b5c70c40b5ba68f03e  gcc/rust/expand/rust-expand-visitor.h
! a24c9465702c5bb64a467cc4f251ec38  gcc/rust/expand/rust-macro-builtins-asm.cc
  48269c7df7dead67e4185d80b217a76a  gcc/rust/expand/rust-macro-builtins-asm.h
! b09e41a88ef4016a6294d77183668bf7  gcc/rust/expand/rust-macro-builtins-format-args.cc
  470ca31c9edf1792290a63da0ae3bdd7  gcc/rust/expand/rust-macro-builtins-helpers.cc
! dff0ef1b84e3096bd94fe2815b90981d  gcc/rust/expand/rust-macro-builtins-helpers.h
  f813ef580dce9d9b6c9a75e9577bdbe0  gcc/rust/expand/rust-macro-builtins-include.cc
  cfe6beb6d729f4b555ffc6493de34a20  gcc/rust/expand/rust-macro-builtins-location.cc
  7d4293c5bb91064c3bb11e2ec9bd1893  gcc/rust/expand/rust-macro-builtins-log-debug.cc
! 7a98e5195382adae583a972114402078  gcc/rust/expand/rust-macro-builtins-offset-of.cc
  277542c684eada894583030cf02b7424  gcc/rust/expand/rust-macro-builtins-test-bench.cc
  277542c684eada894583030cf02b7424  gcc/rust/expand/rust-macro-builtins-trait.cc
  e253e39de6ea2a67018f97fc8e838ef5  gcc/rust/expand/rust-macro-builtins-utility.cc
! 26a6c99fd51145137f378321795b869d  gcc/rust/expand/rust-macro-builtins.cc
  b0344bc54018de3abfa44322f6262176  gcc/rust/expand/rust-macro-builtins.h
! c44d9442cae032d88c3d633c3bfab2e0  gcc/rust/expand/rust-macro-expand.cc
! 7be3a6a907b3d4339bb5363c99a5f39c  gcc/rust/expand/rust-macro-expand.h
  b4b31e238293e868394fdf9247353b30  gcc/rust/expand/rust-macro-invoc-lexer.cc
  df22bd0c18e9d6037a1dbfbd733f009a  gcc/rust/expand/rust-macro-invoc-lexer.h
! b50cebfc8057c27e0e1171b5016f9c17  gcc/rust/expand/rust-macro-substitute-ctx.cc
! ca49d5b0a22f4e9b3423a8901a3998ef  gcc/rust/expand/rust-macro-substitute-ctx.h
  49dc46efca0e56504ad8787e4548f25f  gcc/rust/expand/rust-proc-macro-invoc-lexer.cc
  9a7011cdfca3c1d04ffe7ca8cd3a2537  gcc/rust/expand/rust-proc-macro-invoc-lexer.h
  7faead690d4bd47de7b4b5fe0c4fb7d7  gcc/rust/expand/rust-proc-macro.cc
  9568c3923de491cd646cd621c423458a  gcc/rust/expand/rust-proc-macro.h
  41d25dfc4b39b0ca6a0c9422ea1acdc1  gcc/rust/expand/rust-token-tree-desugar.cc
  35a7953321666f4ad8526473ae2a8db1  gcc/rust/expand/rust-token-tree-desugar.h
! 4c822771404181ffeea2971318af7f79  gcc/rust/hir/rust-ast-lower-base.cc
! fa4dc157aaddff596bb11ccaf1d7d053  gcc/rust/hir/rust-ast-lower-base.h
  2eecfd7677a55d9d177b5226d9a6aec1  gcc/rust/hir/rust-ast-lower-block.h
! 4f6ba7e8758ffceadeac085652f54915  gcc/rust/hir/rust-ast-lower-enumitem.h
! bbc43a3c52ef2d94a514a04b7bd8c2bf  gcc/rust/hir/rust-ast-lower-expr.cc
  0bea9637721f19beb7661ba8cbc0eae6  gcc/rust/hir/rust-ast-lower-expr.h
! 9cf6fa9cdaf170ac2275bbf3007c5ff1  gcc/rust/hir/rust-ast-lower-extern.h
  b4d59b1df9f1d6e27671a9e166c77abb  gcc/rust/hir/rust-ast-lower-format-args.cc
  1c9070543940e6d4a4dbb4d601d853ae  gcc/rust/hir/rust-ast-lower-format-args.h
! 5a4128a86344f4f7aec4546d699c290c  gcc/rust/hir/rust-ast-lower-implitem.cc
! 18c3dfcdc8db737aabbd1ed231a6c8cc  gcc/rust/hir/rust-ast-lower-implitem.h
! b15eb997cb7fcfecc310d0ab4d8832e6  gcc/rust/hir/rust-ast-lower-item.cc
  4692f2513fc1cf935117a527388b3633  gcc/rust/hir/rust-ast-lower-item.h
! 0f8794a9a7d7165d65a1d95743508cea  gcc/rust/hir/rust-ast-lower-pattern.cc
  9ed55743496bcf0607042817cfa4b0d8  gcc/rust/hir/rust-ast-lower-pattern.h
  5b0f3b0dffc07b108851141d7b749598  gcc/rust/hir/rust-ast-lower-stmt.cc
  af09b97c0baeff87520d8face05b8f05  gcc/rust/hir/rust-ast-lower-stmt.h
  b86ab6b1f3ddb71091146e2d7265bd7f  gcc/rust/hir/rust-ast-lower-struct-field-expr.h
  a3f9b9d71a7b0a056ea2218035dd8dad  gcc/rust/hir/rust-ast-lower-type.cc
  2144c5ed50fecb7465bad4f0676110be  gcc/rust/hir/rust-ast-lower-type.h
! f804813c101f8b007f8025dcd50455ba  gcc/rust/hir/rust-ast-lower.cc
  dfd71f28a4e33f88e4f9f845a85eff57  gcc/rust/hir/rust-ast-lower.h
! f38e6ed9d1426eaac2c1bed8f56a0bd0  gcc/rust/hir/rust-hir-dump.cc
! 9f61ffcd5016bb874c6a0829e3feb9ae  gcc/rust/hir/rust-hir-dump.h
  9ae488c2548387541bb760eaff79fbe9  gcc/rust/hir/tree/rust-hir-attrs.h
  7703b12f41d395a71eb5420f6c0a7ba7  gcc/rust/hir/tree/rust-hir-bound-abstract.h
  8f81aae1c3676476d16c5c42bfdc499a  gcc/rust/hir/tree/rust-hir-bound.h
  ef8ae85d1fae88e345d454cc9cd6be61  gcc/rust/hir/tree/rust-hir-expr-abstract.h
  335d221837d49923d80289f790780f10  gcc/rust/hir/tree/rust-hir-expr.cc
  5d4cbccd2f59ef41fc3dd84351775480  gcc/rust/hir/tree/rust-hir-expr.h
! b1f0aba9df8f454caf7e38f2dda754e9  gcc/rust/hir/tree/rust-hir-full-decls.h
  e872fd48a9851c4ec4c3171c007d112d  gcc/rust/hir/tree/rust-hir-full.h
  cf64af347e4de1f3259e0ba179d8e53b  gcc/rust/hir/tree/rust-hir-generic-param.cc
  43725b1aeba18092d28ebd33a73e4462  gcc/rust/hir/tree/rust-hir-generic-param.h
  605269fb7d6c0f38be45a552e2446d9b  gcc/rust/hir/tree/rust-hir-item.cc
! c2417789a7b0cc8ee76c4fd6254b5a18  gcc/rust/hir/tree/rust-hir-item.h
  9f4e7a70392e148fe75decd40598a2d9  gcc/rust/hir/tree/rust-hir-literal.h
  f40fe76efdee3810473f09205ea63119  gcc/rust/hir/tree/rust-hir-node.h
  46af2c5116f73b3da4d0bc13d9cd86f8  gcc/rust/hir/tree/rust-hir-path.cc
  d1fbad563a9af986959aeb87f576564e  gcc/rust/hir/tree/rust-hir-path.h
  ee67550806e0bdf8bb66f8d3be82d6fa  gcc/rust/hir/tree/rust-hir-pattern-abstract.h
! 85de3c8aafd695543adab7460e9b1485  gcc/rust/hir/tree/rust-hir-pattern.h
  e55c4f7404915fb3515e09a7441125a5  gcc/rust/hir/tree/rust-hir-simple-path.h
  22283c03c1dc5ac012096d395c9414c2  gcc/rust/hir/tree/rust-hir-stmt.cc
  d231530a896626f20475091e1168963d  gcc/rust/hir/tree/rust-hir-stmt.h
*************** c143cea24f5c3be477e96312dd276c58  gcc/ru
*** 8271,8290 ****
  ba332eda5c2e84ae8a3591891ae7adcd  gcc/rust/hir/tree/rust-hir-type.h
  32f0297511ca35b0e5d9d95841b7cb38  gcc/rust/hir/tree/rust-hir-visibility.h
  a9ce4bb18277085ac0f36fce0ab7f87f  gcc/rust/hir/tree/rust-hir-visitable.h
! 34acb21cd59a431d4670fe986d6d9167  gcc/rust/hir/tree/rust-hir-visitor.cc
! 3b9ccf4f4b6915dc29b145025d06e7ba  gcc/rust/hir/tree/rust-hir-visitor.h
! 94d18a53e8657c71cc604eb2fc540205  gcc/rust/hir/tree/rust-hir.cc
  6ea149cdd32444b93f142193c19c3930  gcc/rust/hir/tree/rust-hir.h
  fa7c267c70f0094382b7b3df35e83412  gcc/rust/lang-specs.h
  e090436833a0ec80b591d0e2b8d0276b  gcc/rust/lang.opt
  19c784c2297961588e002876d94ceea4  gcc/rust/lang.opt.urls
  4f1a01d5a1d9c4db6498642d7194185e  gcc/rust/lex/rust-input-source.h
! 682147a2ca256e569556246c3ea54e11  gcc/rust/lex/rust-lex.cc
  dff64547611254963c80197402f43560  gcc/rust/lex/rust-lex.h
! da111ac050690bd95b3f9b56dd882300  gcc/rust/lex/rust-token.cc
! 58a3e77a4ef61311f6264c776402bed6  gcc/rust/lex/rust-token.h
  fe40f8618a9f5a5f007bc1a81fe45d3a  gcc/rust/logo.png
! 8d4263de9b0c6741befffe1392cfacca  gcc/rust/metadata/rust-export-metadata.cc
  12ec7837566ee621427ed56d94422509  gcc/rust/metadata/rust-export-metadata.h
  2edf1c3452ec2edc627904170818d7fe  gcc/rust/metadata/rust-extern-crate.cc
  998f5953d66b13c97f7488faa8c315ac  gcc/rust/metadata/rust-extern-crate.h
--- 8271,8290 ----
  ba332eda5c2e84ae8a3591891ae7adcd  gcc/rust/hir/tree/rust-hir-type.h
  32f0297511ca35b0e5d9d95841b7cb38  gcc/rust/hir/tree/rust-hir-visibility.h
  a9ce4bb18277085ac0f36fce0ab7f87f  gcc/rust/hir/tree/rust-hir-visitable.h
! 171168efa9bc4130608778778ee4464b  gcc/rust/hir/tree/rust-hir-visitor.cc
! a6e7147406b59b396b29ce709fc52f1a  gcc/rust/hir/tree/rust-hir-visitor.h
! 345be3f99a4576e50a17224fadf72641  gcc/rust/hir/tree/rust-hir.cc
  6ea149cdd32444b93f142193c19c3930  gcc/rust/hir/tree/rust-hir.h
  fa7c267c70f0094382b7b3df35e83412  gcc/rust/lang-specs.h
  e090436833a0ec80b591d0e2b8d0276b  gcc/rust/lang.opt
  19c784c2297961588e002876d94ceea4  gcc/rust/lang.opt.urls
  4f1a01d5a1d9c4db6498642d7194185e  gcc/rust/lex/rust-input-source.h
! 3691537fb6f69b578191f6f0165ae7b9  gcc/rust/lex/rust-lex.cc
  dff64547611254963c80197402f43560  gcc/rust/lex/rust-lex.h
! 1f730a66d38140f8e1c34d3ed31d8128  gcc/rust/lex/rust-token.cc
! 8404a81273a40a4b226acc1d54ae58ff  gcc/rust/lex/rust-token.h
  fe40f8618a9f5a5f007bc1a81fe45d3a  gcc/rust/logo.png
! 5c936180bfa8209866029d2669648b7f  gcc/rust/metadata/rust-export-metadata.cc
  12ec7837566ee621427ed56d94422509  gcc/rust/metadata/rust-export-metadata.h
  2edf1c3452ec2edc627904170818d7fe  gcc/rust/metadata/rust-extern-crate.cc
  998f5953d66b13c97f7488faa8c315ac  gcc/rust/metadata/rust-extern-crate.h
*************** dcbc600defe89f418c72fb56de980c97  gcc/ru
*** 8296,8345 ****
  d32fa6f6e6b4f85681679a48b9143b49  gcc/rust/parse/rust-parse-impl-lexer.cc
  512507c7858c53e9bcb25b431891ced3  gcc/rust/parse/rust-parse-impl-macro.cc
  eadcb6e38b643a9b344ba845b7eaa4b0  gcc/rust/parse/rust-parse-impl-proc-macro.cc
! 8a84eada600c46c52a0667578ffdb87e  gcc/rust/parse/rust-parse-impl.h
  d60ac257492f0b2d13c8c305707dd04a  gcc/rust/parse/rust-parse.cc
! 1332d77a3ddb2a72987ee982207eabfd  gcc/rust/parse/rust-parse.h
! 2231a11c214aca73dc0b818d237de36c  gcc/rust/resolve/rust-ast-resolve-base.cc
! c8435e00d605125b87b1c2c9c259013c  gcc/rust/resolve/rust-ast-resolve-base.h
! 2e415cfc9ca6fde25ae39390cb3e87f4  gcc/rust/resolve/rust-ast-resolve-expr.cc
! 3be4db578f405ef5c2461ab8809d5144  gcc/rust/resolve/rust-ast-resolve-expr.h
! 8f68f019c34cda122cc27f3b94c06274  gcc/rust/resolve/rust-ast-resolve-implitem.h
! 8127df5d45208feade1828d4b5efba3b  gcc/rust/resolve/rust-ast-resolve-item.cc
! 8bd4783820bdf932104dde419edee6cb  gcc/rust/resolve/rust-ast-resolve-item.h
! 8cb99c5ae5b41ce08b5970a0a95c086c  gcc/rust/resolve/rust-ast-resolve-path.cc
! a8c2cd13a9e17fcd77075f298ece9bbc  gcc/rust/resolve/rust-ast-resolve-path.h
! f3b459c1c08e12f8aa4336938eef2339  gcc/rust/resolve/rust-ast-resolve-pattern.cc
! cc6a86d6d4f3b82cb0c90909786f72d0  gcc/rust/resolve/rust-ast-resolve-pattern.h
! 6fb9870e2dc236966f72710990ede295  gcc/rust/resolve/rust-ast-resolve-stmt.cc
! a01c8629827de508030d8ec5ada0f4f6  gcc/rust/resolve/rust-ast-resolve-stmt.h
! 469f217b1a5f7e8b64533a460dd7d1b5  gcc/rust/resolve/rust-ast-resolve-struct-expr-field.cc
! d6e1a39ea6b2856a3ceb1f1ad21da843  gcc/rust/resolve/rust-ast-resolve-struct-expr-field.h
! ef9539cd1ebecb0d7b169dbc11cd1bda  gcc/rust/resolve/rust-ast-resolve-toplevel.h
! 1ee9649dda0c5d95044ed73901dd5def  gcc/rust/resolve/rust-ast-resolve-type.cc
! 50092e99e4c7ac9c221561d170b60ad2  gcc/rust/resolve/rust-ast-resolve-type.h
! 9813e61543cff199a353ad5f127144d7  gcc/rust/resolve/rust-ast-resolve.cc
  d5113906116ffd33fb4c45243a97fb67  gcc/rust/resolve/rust-ast-resolve.h
  b6b01419e9dcc7774b5791b9a708466a  gcc/rust/resolve/rust-default-resolver.cc
  4320f2346a3c6f9c6e6bdec7e1901019  gcc/rust/resolve/rust-default-resolver.h
! 0346cc6ed444b1ef153fd6afeebcc812  gcc/rust/resolve/rust-early-name-resolver-2.0.cc
! 12c6430a3b99faca5ec6224c5b3fe509  gcc/rust/resolve/rust-early-name-resolver-2.0.h
! 30e0ef18177e2657adfd032c3c7eb9a3  gcc/rust/resolve/rust-early-name-resolver.cc
! a3a4b63c71c3919a1459476032f0252e  gcc/rust/resolve/rust-early-name-resolver.h
  edbd1bb79c5413f7f12c3a446bce05c1  gcc/rust/resolve/rust-finalize-imports-2.0.cc
  86cd9479354d4646ddd9942a1920cb86  gcc/rust/resolve/rust-finalize-imports-2.0.h
  dec0e54b8d4239c44cd88b409b7e74c3  gcc/rust/resolve/rust-forever-stack.cc
  17b4b5467848eca6a46985d6947d3b64  gcc/rust/resolve/rust-forever-stack.h
! 8656851b6c36eebeebd4f794157501e7  gcc/rust/resolve/rust-forever-stack.hxx
  c37894be52ba5cc4406613a60ba6b289  gcc/rust/resolve/rust-ice-finalizer.cc
  f022a4ee2cba026a3593bb6b701ae2f8  gcc/rust/resolve/rust-ice-finalizer.h
  98f1d330caf4f27bd13e2a60d632182b  gcc/rust/resolve/rust-immutable-name-resolution-context.cc
  927471efaee1f85624e6e7eb00584819  gcc/rust/resolve/rust-immutable-name-resolution-context.h
! 0cdc6d842684ce862280799d4214712e  gcc/rust/resolve/rust-late-name-resolver-2.0.cc
! b502be2edccb38a6d04184c085c753c1  gcc/rust/resolve/rust-late-name-resolver-2.0.h
  dac37149763dc8ccca753d54554514f6  gcc/rust/resolve/rust-name-resolution-context.cc
  3ea0376c3b22933ac67896d7cba8ad16  gcc/rust/resolve/rust-name-resolution-context.h
  b6983f07d81272720902833f46969469  gcc/rust/resolve/rust-name-resolver.cc
  be000221300e27326827abc1e0cad277  gcc/rust/resolve/rust-name-resolver.h
  5bd00178d4bbda0cedb3410c06aa647b  gcc/rust/resolve/rust-rib.cc
  37ca9c7e7f101104c8a4921c7898d613  gcc/rust/resolve/rust-rib.h
  ab968ccec019fc6559d933331d01cff5  gcc/rust/resolve/rust-toplevel-name-resolver-2.0.cc
--- 8296,8326 ----
  d32fa6f6e6b4f85681679a48b9143b49  gcc/rust/parse/rust-parse-impl-lexer.cc
  512507c7858c53e9bcb25b431891ced3  gcc/rust/parse/rust-parse-impl-macro.cc
  eadcb6e38b643a9b344ba845b7eaa4b0  gcc/rust/parse/rust-parse-impl-proc-macro.cc
! 17a3390b956eeab511fe97aa6a2b8d7a  gcc/rust/parse/rust-parse-impl.h
  d60ac257492f0b2d13c8c305707dd04a  gcc/rust/parse/rust-parse.cc
! efd8c95f4749b7137731fe544b287e0f  gcc/rust/parse/rust-parse.h
  d5113906116ffd33fb4c45243a97fb67  gcc/rust/resolve/rust-ast-resolve.h
  b6b01419e9dcc7774b5791b9a708466a  gcc/rust/resolve/rust-default-resolver.cc
  4320f2346a3c6f9c6e6bdec7e1901019  gcc/rust/resolve/rust-default-resolver.h
! fb7a97b2acf39381b9edeeb7e0fb2ad1  gcc/rust/resolve/rust-early-name-resolver-2.0.cc
! 25e6f0bd81461c11ef9416f263047d25  gcc/rust/resolve/rust-early-name-resolver-2.0.h
  edbd1bb79c5413f7f12c3a446bce05c1  gcc/rust/resolve/rust-finalize-imports-2.0.cc
  86cd9479354d4646ddd9942a1920cb86  gcc/rust/resolve/rust-finalize-imports-2.0.h
  dec0e54b8d4239c44cd88b409b7e74c3  gcc/rust/resolve/rust-forever-stack.cc
  17b4b5467848eca6a46985d6947d3b64  gcc/rust/resolve/rust-forever-stack.h
! 405d1b98bc153983bc73e7ba49b65b3d  gcc/rust/resolve/rust-forever-stack.hxx
  c37894be52ba5cc4406613a60ba6b289  gcc/rust/resolve/rust-ice-finalizer.cc
  f022a4ee2cba026a3593bb6b701ae2f8  gcc/rust/resolve/rust-ice-finalizer.h
  98f1d330caf4f27bd13e2a60d632182b  gcc/rust/resolve/rust-immutable-name-resolution-context.cc
  927471efaee1f85624e6e7eb00584819  gcc/rust/resolve/rust-immutable-name-resolution-context.h
! f9f3cb0f0d666cdc87307ef93c1b5f04  gcc/rust/resolve/rust-late-name-resolver-2.0.cc
! dd4621d653df40f236fecbec0b1caf48  gcc/rust/resolve/rust-late-name-resolver-2.0.h
  dac37149763dc8ccca753d54554514f6  gcc/rust/resolve/rust-name-resolution-context.cc
  3ea0376c3b22933ac67896d7cba8ad16  gcc/rust/resolve/rust-name-resolution-context.h
  b6983f07d81272720902833f46969469  gcc/rust/resolve/rust-name-resolver.cc
  be000221300e27326827abc1e0cad277  gcc/rust/resolve/rust-name-resolver.h
+ 427832e25906274c5e54ec1b19d69d3a  gcc/rust/resolve/rust-resolve-builtins.cc
+ d39b811b287d9b745260f2103f3dcebf  gcc/rust/resolve/rust-resolve-builtins.h
  5bd00178d4bbda0cedb3410c06aa647b  gcc/rust/resolve/rust-rib.cc
  37ca9c7e7f101104c8a4921c7898d613  gcc/rust/resolve/rust-rib.h
  ab968ccec019fc6559d933331d01cff5  gcc/rust/resolve/rust-toplevel-name-resolver-2.0.cc
*************** fd3aa9a65643d53243d4e7204b4ea8c7  gcc/ru
*** 8349,8472 ****
  3cb9032dbd0f19a697c1bab7cda98bfa  gcc/rust/rust-diagnostics.cc
  26cc49e4c91f569fdcc4be2e38e4cc63  gcc/rust/rust-diagnostics.h
  a29710a52aae45b7a844ae73c125e33f  gcc/rust/rust-error-codes.def
! 04ad67c9ff5f3b84d4ecb5d6390dd6f8  gcc/rust/rust-gcc.cc
  65922743531bd0f8eff57efd205900a9  gcc/rust/rust-gcc.h
! 86094a916caa45171c1b82fc09254027  gcc/rust/rust-lang.cc
  bcf57cedfa84f01311473b51a88f932c  gcc/rust/rust-linemap.cc
  a591947189b9249649cd9d0d05bb6f3b  gcc/rust/rust-linemap.h
  44c864a134b8524b6fd7e36dc13b1d12  gcc/rust/rust-location.h
  b45417b3f3262f4edcbe101bd348c5a0  gcc/rust/rust-object-export.cc
  c4892cc98a9ac5c00fb35b20592c0a82  gcc/rust/rust-object-export.h
! dcde5fb487c3b15b0d4dce6ae15d1c98  gcc/rust/rust-session-manager.cc
  036d9a7a214c0a73976981f212ca0866  gcc/rust/rust-session-manager.h
  567d0d8fd5f4f8ae4496a4212922201d  gcc/rust/rust-system.h
  ac420eeb07d0fa93baebb7cfaafe3a69  gcc/rust/rust-target-def.h
  079faeff0bcbd134ce19509fd4a7c49c  gcc/rust/rust-target.def
  78f9905f32e418612f7e3b9f0557217f  gcc/rust/rust-target.h
  969d20d0da5b3346de516605617a3bfd  gcc/rust/rustspec.cc
! ef695df53407f5a9855af773c34bb2a1  gcc/rust/typecheck/rust-autoderef.cc
  5e6eda346fc227aa5e228ac35cda0962  gcc/rust/typecheck/rust-autoderef.h
! fdf38e077e6653efdc043cf9a602b4d7  gcc/rust/typecheck/rust-casts.cc
  d33794099c6af3bc0595dbb4e77e415f  gcc/rust/typecheck/rust-casts.h
! f50fa03161a82a2216a1bc1cebf988d3  gcc/rust/typecheck/rust-coercion.cc
! e26acd7744fd715da289a7b3b2bd9238  gcc/rust/typecheck/rust-coercion.h
! ae46867451d353ef46bbee575dc8e949  gcc/rust/typecheck/rust-hir-dot-operator.cc
! 858b677b5acaadf89c3a6804d0e80178  gcc/rust/typecheck/rust-hir-dot-operator.h
  f072dca1aa4f27216c23a457a9199152  gcc/rust/typecheck/rust-hir-inherent-impl-overlap.h
! 4bfda607fe6897e2fb51660447f6e53a  gcc/rust/typecheck/rust-hir-path-probe.cc
  1fada070804e23a951644edf6b3c1d3d  gcc/rust/typecheck/rust-hir-path-probe.h
  ecf75c0b1fe9d0c8d8ea76beb7724553  gcc/rust/typecheck/rust-hir-trait-reference.cc
  d66ea5137022ea56053a46e7c3704397  gcc/rust/typecheck/rust-hir-trait-reference.h
! 0d6b05a8bb3b1bef6e8ffcddb4184764  gcc/rust/typecheck/rust-hir-trait-resolve.cc
  50b4be7ea23eb179a814bfd833fefdf1  gcc/rust/typecheck/rust-hir-trait-resolve.h
! 13aca537eec3f98b3aa8f3e9657adc17  gcc/rust/typecheck/rust-hir-type-bounds.h
! 5b5ffd193a34ba7f25c8cf7c26628522  gcc/rust/typecheck/rust-hir-type-check-base.cc
  288c2e01e024cba4622c46ac6c6f9bad  gcc/rust/typecheck/rust-hir-type-check-base.h
  3f733188e36db57e34d01019aad0aeac  gcc/rust/typecheck/rust-hir-type-check-enumitem.cc
  14b730fba367cec7b80f769e886344ae  gcc/rust/typecheck/rust-hir-type-check-enumitem.h
! 2aad25141e49cda9d718edd833ace841  gcc/rust/typecheck/rust-hir-type-check-expr.cc
  59f5cb0ba8dac0fa595b930d70f6a0b4  gcc/rust/typecheck/rust-hir-type-check-expr.h
! 645f4c08aad98d36cf930e47187efced  gcc/rust/typecheck/rust-hir-type-check-implitem.cc
  ebae3826def3f8d019935ea950afaf9a  gcc/rust/typecheck/rust-hir-type-check-implitem.h
! 0f569c086f1097da36429cdb05305fc3  gcc/rust/typecheck/rust-hir-type-check-item.cc
  b884a7eb4628421bd0b7c31329258b8c  gcc/rust/typecheck/rust-hir-type-check-item.h
! 3d2df003e91abb13c3a18145e32e4d72  gcc/rust/typecheck/rust-hir-type-check-path.cc
! e9430b2db11e4359fff753494f256121  gcc/rust/typecheck/rust-hir-type-check-pattern.cc
  f442f3356acfa69e70087f4d0a915461  gcc/rust/typecheck/rust-hir-type-check-pattern.h
  7dfde3f8d5f8afa537706a47a4204575  gcc/rust/typecheck/rust-hir-type-check-stmt.cc
  8cf233a69b1af8083328209d200778c1  gcc/rust/typecheck/rust-hir-type-check-stmt.h
  0817c84983af9fc42e486f3832232669  gcc/rust/typecheck/rust-hir-type-check-struct-field.h
! 496abbb2c8ac224ee6d58cbbef9c98b3  gcc/rust/typecheck/rust-hir-type-check-struct.cc
! c1b97fbe32b215ed40fc8c25aa2ff09e  gcc/rust/typecheck/rust-hir-type-check-type.cc
  4e713ea4973fa9fb07c655c889db01ce  gcc/rust/typecheck/rust-hir-type-check-type.h
! 333a8adbeeb9d4d88d61c265879e022a  gcc/rust/typecheck/rust-hir-type-check.cc
  56e01e94dbff3e8636e68e613618fec8  gcc/rust/typecheck/rust-hir-type-check.h
! 33e4a0f496a3ac195ab6532776b73153  gcc/rust/typecheck/rust-substitution-mapper.cc
! 28e39401e4d451291f369daf16612439  gcc/rust/typecheck/rust-substitution-mapper.h
! 32573a56c5a5d7e0661b10cd21d3e538  gcc/rust/typecheck/rust-type-util.cc
! c6009c201c635a534e03f9537d7f6156  gcc/rust/typecheck/rust-type-util.h
! f3f8d312b8f24b905036fe9b3613e8a2  gcc/rust/typecheck/rust-typecheck-context.cc
! bb9ce416c059f4c4bced027eadacd003  gcc/rust/typecheck/rust-tyty-bounds.cc
  888c9672c03e4f2a8315512a173265b6  gcc/rust/typecheck/rust-tyty-bounds.h
! 77c50800976863232115ea757e68388b  gcc/rust/typecheck/rust-tyty-call.cc
! d47d47af969d983460e32db4067a011d  gcc/rust/typecheck/rust-tyty-call.h
! 781f9faa81a60d3ee7ea2982c31f938a  gcc/rust/typecheck/rust-tyty-cmp.h
  a38838838003c6551067e8b34f582208  gcc/rust/typecheck/rust-tyty-region.h
! 2626471a9937776d3505f3779d298d3b  gcc/rust/typecheck/rust-tyty-subst.cc
  54973ca4009bf6087ad1cacc97a3dc36  gcc/rust/typecheck/rust-tyty-subst.h
! 377a200ab9d0c9f1d110b0b775d157db  gcc/rust/typecheck/rust-tyty-util.cc
! 367d76a00d05a82f8c2b5599cf359900  gcc/rust/typecheck/rust-tyty-util.h
! 543855741d700098d942ba3d9231301f  gcc/rust/typecheck/rust-tyty-variance-analysis-private.h
! fef0a04b266e8a726799600ba5d638fb  gcc/rust/typecheck/rust-tyty-variance-analysis.cc
  d745c17e84fc1621534e477f38dac840  gcc/rust/typecheck/rust-tyty-variance-analysis.h
! e02fb0ccc693b57556ac2a79632d7d2f  gcc/rust/typecheck/rust-tyty-visitor.h
! c61b7e2b2dac72bc77bd590cbac9d014  gcc/rust/typecheck/rust-tyty.cc
! 8cd3ccdac2b89488f2413b34d46cc8dd  gcc/rust/typecheck/rust-tyty.h
! 3efef3f29985e7eb4eda25f7338a232a  gcc/rust/typecheck/rust-unify.cc
! 0bb7a11b4bd0200fc019721dc3f2667d  gcc/rust/typecheck/rust-unify.h
! 0d030f94fc3d0037a80c12aee3829760  gcc/rust/util/bi-map.h
  2293b9580441efb8471b45881435c279  gcc/rust/util/expected.h
! a3d3418d24c9d7a6b012a5f0244c1cc5  gcc/rust/util/fnv-hash.h
  75694e0b09110145bd844f6fc79dded8  gcc/rust/util/make-rust-unicode.py
  5fab4ccaa5f132cbe9ca8f09047732ad  gcc/rust/util/optional.h
  28960566056dffb6dd86b0c3ad60bf39  gcc/rust/util/rust-abi.cc
  a85e112c6426c604dd9a3a9af712e53b  gcc/rust/util/rust-abi.h
! 1c751a64890b3cec625f216844b15e77  gcc/rust/util/rust-attribute-values.h
! da558d995f51e32383a86e153a061ecd  gcc/rust/util/rust-attributes.cc
! b218d550ab3e001996e0a6e5ff280e81  gcc/rust/util/rust-attributes.h
  bca452f773154b078653dfe7acf7df6d  gcc/rust/util/rust-base62.cc
  487f155c2b6c6e0bd786e45db927798e  gcc/rust/util/rust-base62.h
  52e606eb44d3f26e1fa4e3701bf1ffe8  gcc/rust/util/rust-buffered-queue.h
! 94ab22ffac2d84b52bdfa80c35617b64  gcc/rust/util/rust-canonical-path.h
  c07d4ef244db3f6ca995d16a97dde4a4  gcc/rust/util/rust-codepoint.h
  17f2c1b0a221d2381d5fa03056c86a2a  gcc/rust/util/rust-common.h
  dd3df9586c87ea18be777db0bf7d0cf2  gcc/rust/util/rust-dir-owner.cc
  fec387d494bc210ce15deb542e9f7aa1  gcc/rust/util/rust-dir-owner.h
! 48ccf41bdee2df34cf4c36f1b046ff3a  gcc/rust/util/rust-dump.h
  82c8d06a3e8bcf1b97510bdac619ec0a  gcc/rust/util/rust-edition.cc
  312caaf1a11f85ba3561fcdc63801d54  gcc/rust/util/rust-edition.h
! 1f3238d0a4045f91fbdffd311f703e08  gcc/rust/util/rust-ggc.cc
! 1e0f4eb2eb63dc12ad40eb168f58141f  gcc/rust/util/rust-ggc.h
  4ac3dc708bf421d1499e952f62377a3c  gcc/rust/util/rust-hir-map.cc
  a4737c9f24f28d26263a0aa5525aed09  gcc/rust/util/rust-hir-map.h
  88c8ae4d133ecd3a043fc12f4fe69091  gcc/rust/util/rust-identifier.h
! b886fd2a84b8b974a759d58aa85f9868  gcc/rust/util/rust-inline-visitor.h
  c8834665fd10b27b0d346b0feb8e0c75  gcc/rust/util/rust-keyword-values.cc
  7f475eb9a4edc930747ba73408e45e84  gcc/rust/util/rust-keyword-values.h
  12f22d88d5d206b938e8165b5975e99b  gcc/rust/util/rust-lang-item.cc
! f1156b2925b7a7097ec4094d5b461ec8  gcc/rust/util/rust-lang-item.h
  aeeace423f6e82b5140b307df087a853  gcc/rust/util/rust-mapping-common.h
  8efe8f2ae6c529f6e8a316637b23263c  gcc/rust/util/rust-operators.h
  3ab599b73cd39c762daa8c80df124efe  gcc/rust/util/rust-punycode.cc
  cd4867be3dbfc626ab4ed34546e60a13  gcc/rust/util/rust-punycode.h
  2c0a250a95fecf31988f998f7aac2872  gcc/rust/util/rust-stacked-contexts.h
! 1409fd43392d130dc77c0b64b6e43724  gcc/rust/util/rust-token-converter.cc
  44fad7e6f643cffd77b625c32c20515c  gcc/rust/util/rust-token-converter.h
  e9a5e546c32155ec1d162baf906b3173  gcc/rust/util/rust-unicode-data.h
  160750d9c11bf6ee2c07a88f6b10326f  gcc/rust/util/rust-unicode.cc
  b4f0c77852dde185d8745c16c0f82ac0  gcc/rust/util/rust-unicode.h
  27b9ac229553b9349504ebe465280523  gcc/rust/util/rust-unwrap-segment.cc
! 3ead66d97169e8f089cbf8ddbeb43d4e  gcc/rust/util/rust-unwrap-segment.h
  1157834f858df87f4cff12c780fe7030  gcc/sancov.cc
  f47b1babbf39168c2829bbc0997f6b9b  gcc/sanitizer.def
  1c4a31054492029cadf12999aee53d81  gcc/sanopt.cc
--- 8330,8452 ----
  3cb9032dbd0f19a697c1bab7cda98bfa  gcc/rust/rust-diagnostics.cc
  26cc49e4c91f569fdcc4be2e38e4cc63  gcc/rust/rust-diagnostics.h
  a29710a52aae45b7a844ae73c125e33f  gcc/rust/rust-error-codes.def
! 898b28bb42a305091e9e1341bda2e8a1  gcc/rust/rust-gcc.cc
  65922743531bd0f8eff57efd205900a9  gcc/rust/rust-gcc.h
! dea1c422b3aea0adea2f5557c5257a7f  gcc/rust/rust-lang.cc
  bcf57cedfa84f01311473b51a88f932c  gcc/rust/rust-linemap.cc
  a591947189b9249649cd9d0d05bb6f3b  gcc/rust/rust-linemap.h
  44c864a134b8524b6fd7e36dc13b1d12  gcc/rust/rust-location.h
  b45417b3f3262f4edcbe101bd348c5a0  gcc/rust/rust-object-export.cc
  c4892cc98a9ac5c00fb35b20592c0a82  gcc/rust/rust-object-export.h
! 22898d619df452bc13d3e295bdc23c70  gcc/rust/rust-session-manager.cc
  036d9a7a214c0a73976981f212ca0866  gcc/rust/rust-session-manager.h
  567d0d8fd5f4f8ae4496a4212922201d  gcc/rust/rust-system.h
  ac420eeb07d0fa93baebb7cfaafe3a69  gcc/rust/rust-target-def.h
  079faeff0bcbd134ce19509fd4a7c49c  gcc/rust/rust-target.def
  78f9905f32e418612f7e3b9f0557217f  gcc/rust/rust-target.h
  969d20d0da5b3346de516605617a3bfd  gcc/rust/rustspec.cc
! ea06b5d7bc8eac7d77c08607c3e04c0c  gcc/rust/typecheck/rust-autoderef.cc
  5e6eda346fc227aa5e228ac35cda0962  gcc/rust/typecheck/rust-autoderef.h
! d4138ff0941017a78fc361489690835b  gcc/rust/typecheck/rust-casts.cc
  d33794099c6af3bc0595dbb4e77e415f  gcc/rust/typecheck/rust-casts.h
! 872897c3bd25d773cffdd9df23a8f981  gcc/rust/typecheck/rust-coercion.cc
! b6f9bfb71a3ea330ee2b7909209055eb  gcc/rust/typecheck/rust-coercion.h
! f4fb08c07a164d0abb459d493f842d35  gcc/rust/typecheck/rust-hir-dot-operator.cc
! 17850b06a0b270c7dd9b792f1e728f2d  gcc/rust/typecheck/rust-hir-dot-operator.h
  f072dca1aa4f27216c23a457a9199152  gcc/rust/typecheck/rust-hir-inherent-impl-overlap.h
! ce8ad70188d2476aecbe570d3def4b90  gcc/rust/typecheck/rust-hir-path-probe.cc
  1fada070804e23a951644edf6b3c1d3d  gcc/rust/typecheck/rust-hir-path-probe.h
  ecf75c0b1fe9d0c8d8ea76beb7724553  gcc/rust/typecheck/rust-hir-trait-reference.cc
  d66ea5137022ea56053a46e7c3704397  gcc/rust/typecheck/rust-hir-trait-reference.h
! f7e76e7030840e9376f38a69a9b8807c  gcc/rust/typecheck/rust-hir-trait-resolve.cc
  50b4be7ea23eb179a814bfd833fefdf1  gcc/rust/typecheck/rust-hir-trait-resolve.h
! b4a86f011c7581b26f6472b6153b1f91  gcc/rust/typecheck/rust-hir-type-bounds.h
! 2b521eef2ecc13767dabfbdc2f2f1584  gcc/rust/typecheck/rust-hir-type-check-base.cc
  288c2e01e024cba4622c46ac6c6f9bad  gcc/rust/typecheck/rust-hir-type-check-base.h
  3f733188e36db57e34d01019aad0aeac  gcc/rust/typecheck/rust-hir-type-check-enumitem.cc
  14b730fba367cec7b80f769e886344ae  gcc/rust/typecheck/rust-hir-type-check-enumitem.h
! be7eea248410183d9b45d1e08f41b0d8  gcc/rust/typecheck/rust-hir-type-check-expr.cc
  59f5cb0ba8dac0fa595b930d70f6a0b4  gcc/rust/typecheck/rust-hir-type-check-expr.h
! 64dc68dc126e127341e0bdb7532bc0ea  gcc/rust/typecheck/rust-hir-type-check-implitem.cc
  ebae3826def3f8d019935ea950afaf9a  gcc/rust/typecheck/rust-hir-type-check-implitem.h
! 4ee2c58b0cb3b561d48dd80827cc1dee  gcc/rust/typecheck/rust-hir-type-check-item.cc
  b884a7eb4628421bd0b7c31329258b8c  gcc/rust/typecheck/rust-hir-type-check-item.h
! b8c6c90683816b55dc0bc2918c29f55d  gcc/rust/typecheck/rust-hir-type-check-path.cc
! 9efa4cb35a0e4bd16fcfb95dd433a6f2  gcc/rust/typecheck/rust-hir-type-check-pattern.cc
  f442f3356acfa69e70087f4d0a915461  gcc/rust/typecheck/rust-hir-type-check-pattern.h
  7dfde3f8d5f8afa537706a47a4204575  gcc/rust/typecheck/rust-hir-type-check-stmt.cc
  8cf233a69b1af8083328209d200778c1  gcc/rust/typecheck/rust-hir-type-check-stmt.h
  0817c84983af9fc42e486f3832232669  gcc/rust/typecheck/rust-hir-type-check-struct-field.h
! 4e3e67d84938436a77dd3819b1f87ac0  gcc/rust/typecheck/rust-hir-type-check-struct.cc
! ad4a228ff786e57d9edad4e842dc67c7  gcc/rust/typecheck/rust-hir-type-check-type.cc
  4e713ea4973fa9fb07c655c889db01ce  gcc/rust/typecheck/rust-hir-type-check-type.h
! 3a0a56b08644b22c7118757461a09cae  gcc/rust/typecheck/rust-hir-type-check.cc
  56e01e94dbff3e8636e68e613618fec8  gcc/rust/typecheck/rust-hir-type-check.h
! 185a6346f5cd7e9039f3676d268d8d30  gcc/rust/typecheck/rust-substitution-mapper.cc
! 65ef317da67f9c85d5d6aa12236e4103  gcc/rust/typecheck/rust-substitution-mapper.h
! 35c8993da1ffcf389b72f8f4a230fac3  gcc/rust/typecheck/rust-type-util.cc
! ee1a2e23854267f83989c6a2b13e32e3  gcc/rust/typecheck/rust-type-util.h
! 74fb93afc26056a5b925e229d16046d3  gcc/rust/typecheck/rust-typecheck-context.cc
! 4fb5d79d75c6dfc974be45c8538b2175  gcc/rust/typecheck/rust-tyty-bounds.cc
  888c9672c03e4f2a8315512a173265b6  gcc/rust/typecheck/rust-tyty-bounds.h
! 319ce81718bb45f8936b5d43c4fd9c97  gcc/rust/typecheck/rust-tyty-call.cc
! fe9bd81bf0e97e98a21e9e0787e7207a  gcc/rust/typecheck/rust-tyty-call.h
  a38838838003c6551067e8b34f582208  gcc/rust/typecheck/rust-tyty-region.h
! fd31bc7d5bef9c6b57e26c8c5434434e  gcc/rust/typecheck/rust-tyty-subst.cc
  54973ca4009bf6087ad1cacc97a3dc36  gcc/rust/typecheck/rust-tyty-subst.h
! c5f7447b073ad1ddccba1352fc544447  gcc/rust/typecheck/rust-tyty-util.cc
! 737d2f701f5c020c1cef24875c4630ae  gcc/rust/typecheck/rust-tyty-util.h
! fcb02130c7b685b134f835bf25092f50  gcc/rust/typecheck/rust-tyty-variance-analysis-private.h
! 4b763a53685364f24c7281fe201c9658  gcc/rust/typecheck/rust-tyty-variance-analysis.cc
  d745c17e84fc1621534e477f38dac840  gcc/rust/typecheck/rust-tyty-variance-analysis.h
! 6a4d86b2e8fd559a6bc9fa2fc8b1b2c5  gcc/rust/typecheck/rust-tyty-visitor.h
! 8b7e9c11596eea757897e57adc0637bf  gcc/rust/typecheck/rust-tyty.cc
! 7ae5c5a6d80451c3dbfbfc9bad5f9055  gcc/rust/typecheck/rust-tyty.h
! 347bfc0c453df120ae3b6bd4ec78a9eb  gcc/rust/typecheck/rust-unify.cc
! 18069389ad17eb0d4a120bf7dcaf286e  gcc/rust/typecheck/rust-unify.h
! e09d91fb613b21d220449fc5e5c591f2  gcc/rust/util/bi-map.h
  2293b9580441efb8471b45881435c279  gcc/rust/util/expected.h
! 9f5807c51b22c3e03a9c8f4e9623e0ef  gcc/rust/util/fnv-hash.h
  75694e0b09110145bd844f6fc79dded8  gcc/rust/util/make-rust-unicode.py
  5fab4ccaa5f132cbe9ca8f09047732ad  gcc/rust/util/optional.h
  28960566056dffb6dd86b0c3ad60bf39  gcc/rust/util/rust-abi.cc
  a85e112c6426c604dd9a3a9af712e53b  gcc/rust/util/rust-abi.h
! c49c4bab5705db22261b4bfac203372a  gcc/rust/util/rust-attribute-values.h
! a96160bd6595d514cfc812b45a59dacb  gcc/rust/util/rust-attributes.cc
! d0715dbc215b004eeeda32cecde13dd4  gcc/rust/util/rust-attributes.h
  bca452f773154b078653dfe7acf7df6d  gcc/rust/util/rust-base62.cc
  487f155c2b6c6e0bd786e45db927798e  gcc/rust/util/rust-base62.h
  52e606eb44d3f26e1fa4e3701bf1ffe8  gcc/rust/util/rust-buffered-queue.h
! c94845658d46e256616cb0df20cb4a59  gcc/rust/util/rust-canonical-path.h
  c07d4ef244db3f6ca995d16a97dde4a4  gcc/rust/util/rust-codepoint.h
  17f2c1b0a221d2381d5fa03056c86a2a  gcc/rust/util/rust-common.h
  dd3df9586c87ea18be777db0bf7d0cf2  gcc/rust/util/rust-dir-owner.cc
  fec387d494bc210ce15deb542e9f7aa1  gcc/rust/util/rust-dir-owner.h
! d276acba4372c6be86c88ab32a1a2e8b  gcc/rust/util/rust-dump.h
  82c8d06a3e8bcf1b97510bdac619ec0a  gcc/rust/util/rust-edition.cc
  312caaf1a11f85ba3561fcdc63801d54  gcc/rust/util/rust-edition.h
! 7066a7ab173c77ab70f790914031570a  gcc/rust/util/rust-ggc.cc
! 3232b843745603441d2d4e56e8c90abd  gcc/rust/util/rust-ggc.h
  4ac3dc708bf421d1499e952f62377a3c  gcc/rust/util/rust-hir-map.cc
  a4737c9f24f28d26263a0aa5525aed09  gcc/rust/util/rust-hir-map.h
  88c8ae4d133ecd3a043fc12f4fe69091  gcc/rust/util/rust-identifier.h
! e19359a7d7b629c25d7bda5118df43da  gcc/rust/util/rust-inline-visitor.h
  c8834665fd10b27b0d346b0feb8e0c75  gcc/rust/util/rust-keyword-values.cc
  7f475eb9a4edc930747ba73408e45e84  gcc/rust/util/rust-keyword-values.h
  12f22d88d5d206b938e8165b5975e99b  gcc/rust/util/rust-lang-item.cc
! 2bb9dcb2b487b85c9663a38aac9e3cd5  gcc/rust/util/rust-lang-item.h
  aeeace423f6e82b5140b307df087a853  gcc/rust/util/rust-mapping-common.h
  8efe8f2ae6c529f6e8a316637b23263c  gcc/rust/util/rust-operators.h
  3ab599b73cd39c762daa8c80df124efe  gcc/rust/util/rust-punycode.cc
  cd4867be3dbfc626ab4ed34546e60a13  gcc/rust/util/rust-punycode.h
  2c0a250a95fecf31988f998f7aac2872  gcc/rust/util/rust-stacked-contexts.h
! 96641cff81e21dad24b3df4b87716159  gcc/rust/util/rust-token-converter.cc
  44fad7e6f643cffd77b625c32c20515c  gcc/rust/util/rust-token-converter.h
  e9a5e546c32155ec1d162baf906b3173  gcc/rust/util/rust-unicode-data.h
  160750d9c11bf6ee2c07a88f6b10326f  gcc/rust/util/rust-unicode.cc
  b4f0c77852dde185d8745c16c0f82ac0  gcc/rust/util/rust-unicode.h
  27b9ac229553b9349504ebe465280523  gcc/rust/util/rust-unwrap-segment.cc
! 8d112f972dcbf2531c2a2b6c24bc14f6  gcc/rust/util/rust-unwrap-segment.h
  1157834f858df87f4cff12c780fe7030  gcc/sancov.cc
  f47b1babbf39168c2829bbc0997f6b9b  gcc/sanitizer.def
  1c4a31054492029cadf12999aee53d81  gcc/sanopt.cc
*************** fdc04e5af7ee387dce07c6ba9a99eaa8  gcc/se
*** 8501,8507 ****
  50d9999185408bcae454174489317b68  gcc/signop.h
  97a13c24fa48c474198b5767f228fd93  gcc/simple-diagnostic-path.cc
  4daee3acc61f789d9c4c04a27a5bb351  gcc/simple-diagnostic-path.h
! 3bec3ff60f9db94e1a58eb1f407fb7d4  gcc/simplify-rtx.cc
  456e0937ae4b3a0f49fd44fb0d05eb52  gcc/sort.cc
  599fc125220850c86939202313a6f733  gcc/sparseset.cc
  430469e71b555502fe14de847bb52093  gcc/sparseset.h
--- 8481,8487 ----
  50d9999185408bcae454174489317b68  gcc/signop.h
  97a13c24fa48c474198b5767f228fd93  gcc/simple-diagnostic-path.cc
  4daee3acc61f789d9c4c04a27a5bb351  gcc/simple-diagnostic-path.h
! 22e961880747bd72db90dd1a02f02758  gcc/simplify-rtx.cc
  456e0937ae4b3a0f49fd44fb0d05eb52  gcc/sort.cc
  599fc125220850c86939202313a6f733  gcc/sparseset.cc
  430469e71b555502fe14de847bb52093  gcc/sparseset.h
*************** ac49ee54195f30bc26eaa8fcf56ba0b1  gcc/sp
*** 8514,8520 ****
  84bd78cc881371c105169fb8707256d3  gcc/splay-tree-utils.tcc
  a3bbacd1506c9f377db1aaaa81c58912  gcc/sreal.cc
  f5e5ba1329ffae51d286f6c8932308d6  gcc/sreal.h
! 990b638cefb768afd22673a6a7144eea  gcc/ssa-iterators.h
  3f0c5b46b37a88cbf05365761c63c6cc  gcc/ssa.h
  d0b55fa9a0f86f4f03bdbfcff3e068d8  gcc/stack-ptr-mod.cc
  bbd5abaa55463a5497e6ff9d14de3a1b  gcc/statistics.cc
--- 8494,8500 ----
  84bd78cc881371c105169fb8707256d3  gcc/splay-tree-utils.tcc
  a3bbacd1506c9f377db1aaaa81c58912  gcc/sreal.cc
  f5e5ba1329ffae51d286f6c8932308d6  gcc/sreal.h
! b3fac3a9d5880bf3ffb3620c08f59c3c  gcc/ssa-iterators.h
  3f0c5b46b37a88cbf05365761c63c6cc  gcc/ssa.h
  d0b55fa9a0f86f4f03bdbfcff3e068d8  gcc/stack-ptr-mod.cc
  bbd5abaa55463a5497e6ff9d14de3a1b  gcc/statistics.cc
*************** d52852ab0122f14cd4f7658db8b9c6df  gcc/sy
*** 8542,8548 ****
  5dcfbac7f32752af3034f02319af81d7  gcc/symtab-clones.h
  f849345d69b622ff9e7b96095bc2c34e  gcc/symtab-thunks.cc
  c9829745147a0b8ec026a3c5029fe2ff  gcc/symtab-thunks.h
! 3ec24894944feb0d9329cb38bb39c378  gcc/symtab.cc
  b3a965e425e6cf7888319667faf58da9  gcc/sync-builtins.def
  b1497a03867668af210c32280876fdd7  gcc/system.h
  480d916fe042a150001ad88e88521c08  gcc/target-def.h
--- 8522,8528 ----
  5dcfbac7f32752af3034f02319af81d7  gcc/symtab-clones.h
  f849345d69b622ff9e7b96095bc2c34e  gcc/symtab-thunks.cc
  c9829745147a0b8ec026a3c5029fe2ff  gcc/symtab-thunks.h
! 1e5cd3d72b84a1e5c326ba2cce88fc91  gcc/symtab.cc
  b3a965e425e6cf7888319667faf58da9  gcc/sync-builtins.def
  b1497a03867668af210c32280876fdd7  gcc/system.h
  480d916fe042a150001ad88e88521c08  gcc/target-def.h
*************** f917b1b792e38f03fb6b295105203e25  gcc/ta
*** 8555,8561 ****
  598920a18a05f11271f5dd4aa453e76a  gcc/targhooks.cc
  96ddcc694ec42272d51a10664cd73f89  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! 7634d92b2d6a2ab0f6e0f6fbd19a8720  gcc/testsuite/ChangeLog
  47e8e29b649ead73b8a1e4797da470ed  gcc/testsuite/ChangeLog-1993-2007
  35198a9e4fd31b935de8789faabf3351  gcc/testsuite/ChangeLog-2008
  0f19934540750356d1b91595cebfd9a8  gcc/testsuite/ChangeLog-2009
--- 8535,8541 ----
  598920a18a05f11271f5dd4aa453e76a  gcc/targhooks.cc
  96ddcc694ec42272d51a10664cd73f89  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! 33aff3834b5c4e2f0ccdf03bb6c4bd7f  gcc/testsuite/ChangeLog
  47e8e29b649ead73b8a1e4797da470ed  gcc/testsuite/ChangeLog-1993-2007
  35198a9e4fd31b935de8789faabf3351  gcc/testsuite/ChangeLog-2008
  0f19934540750356d1b91595cebfd9a8  gcc/testsuite/ChangeLog-2009
*************** f77090a8c54bd7c9695bd1baea42b2ad  gcc/te
*** 19913,19919 ****
  33e222185e271580e5b1227936c867ca  gcc/testsuite/c-c++-common/ubsan/align-2.c
  fff9a866ffaa3beb1d96455b3c496362  gcc/testsuite/c-c++-common/ubsan/align-3.c
  23a589389435e7f1d0daefd5a3259770  gcc/testsuite/c-c++-common/ubsan/align-4.c
! a1c1942e4c2e6341c0f3c9ce229db3ff  gcc/testsuite/c-c++-common/ubsan/align-5.c
  8e08ee7824bcc3f0354e094285c52ae4  gcc/testsuite/c-c++-common/ubsan/align-5a.c
  90dde247618151c35b3bca50f7c3e3d0  gcc/testsuite/c-c++-common/ubsan/align-6.c
  a7a38e8a32e9f420307680f9fd7c64d0  gcc/testsuite/c-c++-common/ubsan/align-7.c
--- 19893,19899 ----
  33e222185e271580e5b1227936c867ca  gcc/testsuite/c-c++-common/ubsan/align-2.c
  fff9a866ffaa3beb1d96455b3c496362  gcc/testsuite/c-c++-common/ubsan/align-3.c
  23a589389435e7f1d0daefd5a3259770  gcc/testsuite/c-c++-common/ubsan/align-4.c
! 8b41396a13f67b4dffcda622553e0b71  gcc/testsuite/c-c++-common/ubsan/align-5.c
  8e08ee7824bcc3f0354e094285c52ae4  gcc/testsuite/c-c++-common/ubsan/align-5a.c
  90dde247618151c35b3bca50f7c3e3d0  gcc/testsuite/c-c++-common/ubsan/align-6.c
  a7a38e8a32e9f420307680f9fd7c64d0  gcc/testsuite/c-c++-common/ubsan/align-7.c
*************** fae22c7cff0bae185284077ff2e72523  gcc/te
*** 32465,32470 ****
--- 32445,32452 ----
  0a66e0a40527f0507cceaeb322c91a15  gcc/testsuite/g++.dg/modules/contracts-tpl-friend-1_b.C
  097ffafa56bf8b6bcbb8f85c58b0e187  gcc/testsuite/g++.dg/modules/convop-1_a.C
  02940f3eec05ab2c1e44ea29d72255b6  gcc/testsuite/g++.dg/modules/convop-1_b.C
+ f9fb2c7fc295df949a65ad17e27cbfe7  gcc/testsuite/g++.dg/modules/convop-2_a.H
+ f9153a236ec996492630837403e73485  gcc/testsuite/g++.dg/modules/convop-2_b.C
  a12e7250787d90ecbf8a074e29830748  gcc/testsuite/g++.dg/modules/cpp-1.C
  3bb7a96e17349f006fdc91b7d33ece61  gcc/testsuite/g++.dg/modules/cpp-10.C
  2d36bf18c705bff96fbeefdaf66de03e  gcc/testsuite/g++.dg/modules/cpp-11.C
*************** c8f6159c50d59c6586f5797b42391c86  gcc/te
*** 32806,32811 ****
--- 32788,32795 ----
  1e129f71b6c51e2bb4325ececab6e9d0  gcc/testsuite/g++.dg/modules/inst-4_b.C
  9c1e5aa4fca91a8158a8ba8a5acab036  gcc/testsuite/g++.dg/modules/inst-5_a.H
  45ff01b5a1d0276885e30fb3445f5ed3  gcc/testsuite/g++.dg/modules/inst-5_b.C
+ 60bae6f4a7bfe8ecf40c92bc84aa9a4f  gcc/testsuite/g++.dg/modules/inst-6_a.C
+ 78bafa91ce71486fc147f8fef051956f  gcc/testsuite/g++.dg/modules/inst-6_b.C
  a345a5bfe397e84c45d084024a9acbf2  gcc/testsuite/g++.dg/modules/internal-1.C
  e6b16a33fb2c85abf4f99ad0d5ad33bb  gcc/testsuite/g++.dg/modules/internal-10.C
  8fe7459b1e2ebdf33715cdab3dbafaf9  gcc/testsuite/g++.dg/modules/internal-11.C
*************** d78c1de0f7d9cac90e50c0208adc2926  gcc/te
*** 32841,32846 ****
--- 32825,32833 ----
  62e7f6f61022bc772dcc984ba06b0b3e  gcc/testsuite/g++.dg/modules/lambda-11.h
  8c9596d790271d8547290c1515a3350b  gcc/testsuite/g++.dg/modules/lambda-11_a.H
  967c2f48b085f1c18832266697fac4ee  gcc/testsuite/g++.dg/modules/lambda-11_b.C
+ 804382f5b6a9cda1fca29fc8024f66a4  gcc/testsuite/g++.dg/modules/lambda-12.h
+ f42f3f252e14bfc0ef3c1e93ea73a06d  gcc/testsuite/g++.dg/modules/lambda-12_a.H
+ 92f393f2dacc1d0ca3a6c8c35172d4a5  gcc/testsuite/g++.dg/modules/lambda-12_b.C
  d40eb3b191ce03c71ec885f4126c9c01  gcc/testsuite/g++.dg/modules/lambda-1_a.C
  0c208993fd82c4dab83fb16f53f43099  gcc/testsuite/g++.dg/modules/lambda-1_b.C
  0b364ead1b387b5505e2f7bf2e5dc3b5  gcc/testsuite/g++.dg/modules/lambda-2.h
*************** eea88cc62cf091daa90c9da3714651e9  gcc/te
*** 33073,33078 ****
--- 33060,33068 ----
  42f128106dcccfb827c0d63b8aa87a9b  gcc/testsuite/g++.dg/modules/merge-19_b.C
  c55f90e5ef6f7ab3992f6606da04c6d7  gcc/testsuite/g++.dg/modules/merge-1_a.C
  8dfdc3716d1dda6833ec359936a84a2c  gcc/testsuite/g++.dg/modules/merge-1_b.C
+ 58b4bbec16747150dd0024d73a591543  gcc/testsuite/g++.dg/modules/merge-20.h
+ 778fe9cb18c40b1afc49a8e5a2f0aef5  gcc/testsuite/g++.dg/modules/merge-20_a.H
+ 6f0d50489a391402d2cbd19055ca5d0a  gcc/testsuite/g++.dg/modules/merge-20_b.C
  4f1ab1a658f8fe8b82d453787cd70235  gcc/testsuite/g++.dg/modules/merge-2_a.H
  8cdb66c1a7c6fd5f699a54755e0262c3  gcc/testsuite/g++.dg/modules/merge-2_b.C
  bafe05354251f1f0df54dbb55d13354f  gcc/testsuite/g++.dg/modules/merge-3_a.H
*************** c60b844a013ddc3832a59b1cd376b1ad  gcc/te
*** 34196,34201 ****
--- 34186,34192 ----
  8ae5f63f132f2e69255225e052069238  gcc/testsuite/g++.dg/opt/pr119614.C
  b67c374c96c5b9bf7bfc34ab5c497627  gcc/testsuite/g++.dg/opt/pr120629.C
  9db6e9a160a496988df91d0d0b96bc85  gcc/testsuite/g++.dg/opt/pr122083-1.C
+ 46bab0272c3e399fa4db680833cb9a89  gcc/testsuite/g++.dg/opt/pr122394.C
  2896f5b1a96dd9fabb1dbb65cb4c5921  gcc/testsuite/g++.dg/opt/pr13066-1.C
  4f87f86b9f018cae74888e97468b2fe0  gcc/testsuite/g++.dg/opt/pr14029.C
  8fb7e68e9e9b5eb02628e03f5333e645  gcc/testsuite/g++.dg/opt/pr14888.C
*************** e5c358735afed9e9c54950b2b1516563  gcc/te
*** 38466,38471 ****
--- 38457,38464 ----
  48f8a1a8175e84a3573f187b018b2269  gcc/testsuite/g++.dg/tree-ssa/bvector-3.C
  713d6b942f1fdfec168122607d26adf6  gcc/testsuite/g++.dg/tree-ssa/calloc.C
  77eae20bc535d63c8ba5e78f1753ad4f  gcc/testsuite/g++.dg/tree-ssa/cond-temp1.C
+ 30b2438f1473559df105c0da4dbe8cea  gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C
+ d5faa1fd9db0537a20703336005ef3a9  gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C
  96f78e0eceff770431ee91e38866bb06  gcc/testsuite/g++.dg/tree-ssa/copyprop-1.C
  0c4762d5d27af6f799c16c66b7dd5692  gcc/testsuite/g++.dg/tree-ssa/copyprop.C
  87d33077dde5db2d1e9e001bd82dc9cd  gcc/testsuite/g++.dg/tree-ssa/counts-1.C
*************** b731b5d32c1f477ed23555d37dcf870a  gcc/te
*** 39935,39940 ****
--- 39928,39935 ----
  62fde56fd55223e0af2436edca399912  gcc/testsuite/g++.dg/warn/pr79290.C
  a57e4640a3dda500c8eb3374c6e1ae4c  gcc/testsuite/g++.dg/warn/pr80635-1.C
  00a4731317a08cb84ce3e84b766012b4  gcc/testsuite/g++.dg/warn/pr80635-2.C
+ 1efdd2404496d13f3ceb813faad94aa0  gcc/testsuite/g++.dg/warn/pr80635-3.C
+ d45e55706b6ed06ede9cf076d944cb48  gcc/testsuite/g++.dg/warn/pr80635-4.C
  b396f058eef27622b6e932e0515dc223  gcc/testsuite/g++.dg/warn/pr81119.C
  ad68bbb45548b2f681a5f0e57f41ef19  gcc/testsuite/g++.dg/warn/pr81275-1.C
  0faf646f98471e86eee5164be65067cd  gcc/testsuite/g++.dg/warn/pr81275-2.C
*************** c43ec17ecd6eea23639c975ca544d15b  gcc/te
*** 43587,43592 ****
--- 43582,43591 ----
  4b4064fa7873d4cb7157ac2a64b60aa1  gcc/testsuite/g++.target/i386/avx512vl-pr98537-1.C
  6fb49c93f0095a942a2bf1dd276425d5  gcc/testsuite/g++.target/i386/avx512vl-pr98537-2.C
  faaf8cb88bea0613c5676fb7a19296ed  gcc/testsuite/g++.target/i386/bfloat_cpp_typecheck.C
+ 60c5bf14a1938214fb6ec30c76d3922f  gcc/testsuite/g++.target/i386/cf_check-1.C
+ d308b2d49958c216374d7230f881c421  gcc/testsuite/g++.target/i386/cf_check-2.C
+ 55f763e733fe870cc5c57b8cd5dcaae6  gcc/testsuite/g++.target/i386/cf_check-3.C
+ 9443e26bf187177f51a3e072f4e83f2a  gcc/testsuite/g++.target/i386/cf_check-4.C
  7a33fea3b2ecb10736e762b211f6ae42  gcc/testsuite/g++.target/i386/crc32-4.C
  ea7a625a5c087724f70333c1b6ad80fc  gcc/testsuite/g++.target/i386/empty-class1.C
  5c480abcec0d76095612ae8099a7315e  gcc/testsuite/g++.target/i386/empty-class2.C
*************** a6a5d652323c20e5b2bbc8ea9dc8f4d7  gcc/te
*** 43997,44003 ****
  c358c32e7ca409abcc867a3b5248f5bd  gcc/testsuite/g++.target/riscv/rvv/base/pr116883.C
  979e78c5ed1d2ba91a46584480362b26  gcc/testsuite/g++.target/riscv/rvv/base/riscv_vector.h
  4a3be4db135c0350e87b0abdf4ca1ca8  gcc/testsuite/g++.target/riscv/rvv/rvv.exp
! c7172cd9252e12b67637bd9c4179611f  gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
  737eebb4901981753937ddcc65184708  gcc/testsuite/g++.target/s390/atomic-align-1.C
  74f02d12b4213817c3460e1eebfa9eae  gcc/testsuite/g++.target/s390/mi-thunk.C
  93b786c04aacd9a92606e85c55410461  gcc/testsuite/g++.target/s390/pr100281-1.C
--- 43996,44002 ----
  c358c32e7ca409abcc867a3b5248f5bd  gcc/testsuite/g++.target/riscv/rvv/base/pr116883.C
  979e78c5ed1d2ba91a46584480362b26  gcc/testsuite/g++.target/riscv/rvv/base/riscv_vector.h
  4a3be4db135c0350e87b0abdf4ca1ca8  gcc/testsuite/g++.target/riscv/rvv/rvv.exp
! 0f6d3519b642a314a2ed539fd0c405c3  gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
  737eebb4901981753937ddcc65184708  gcc/testsuite/g++.target/s390/atomic-align-1.C
  74f02d12b4213817c3460e1eebfa9eae  gcc/testsuite/g++.target/s390/mi-thunk.C
  93b786c04aacd9a92606e85c55410461  gcc/testsuite/g++.target/s390/pr100281-1.C
*************** d040792d1dd4c9dd03defd6b33b73ca3  gcc/te
*** 50023,50029 ****
  686e8a08e2ea9e8c895de2a53b5d7166  gcc/testsuite/gcc.dg/builtin-arith-overflow-4.c
  42993f464b05f08b455aede39114a000  gcc/testsuite/gcc.dg/builtin-arith-overflow-4a.c
  57438e502d4a94ddefa57cc49b25f836  gcc/testsuite/gcc.dg/builtin-arith-overflow-5.c
! 451f7ecc855ee325551342a0928e36e3  gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c
  81addba5c0e1838ae8925847f9549ba9  gcc/testsuite/gcc.dg/builtin-assume-aligned-2.c
  e37f4aca281a2c82829d2bf1650d5193  gcc/testsuite/gcc.dg/builtin-bswap-1.c
  8c6c4e4a58a4f180971e576b4fabe804  gcc/testsuite/gcc.dg/builtin-bswap-10.c
--- 50022,50028 ----
  686e8a08e2ea9e8c895de2a53b5d7166  gcc/testsuite/gcc.dg/builtin-arith-overflow-4.c
  42993f464b05f08b455aede39114a000  gcc/testsuite/gcc.dg/builtin-arith-overflow-4a.c
  57438e502d4a94ddefa57cc49b25f836  gcc/testsuite/gcc.dg/builtin-arith-overflow-5.c
! e1b404ff3b34ca8f09597bbb3eaff8bb  gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c
  81addba5c0e1838ae8925847f9549ba9  gcc/testsuite/gcc.dg/builtin-assume-aligned-2.c
  e37f4aca281a2c82829d2bf1650d5193  gcc/testsuite/gcc.dg/builtin-bswap-1.c
  8c6c4e4a58a4f180971e576b4fabe804  gcc/testsuite/gcc.dg/builtin-bswap-10.c
*************** da2226add6799fd192e2b367404d1b0b  gcc/te
*** 51246,51251 ****
--- 51245,51252 ----
  40fff02642e5e2ead0c4b58bc10042b7  gcc/testsuite/gcc.dg/complex-5.c
  c7dc328831cb2f54c434fe280fbc315a  gcc/testsuite/gcc.dg/complex-6.c
  680764f447f89f563460401a948f1554  gcc/testsuite/gcc.dg/complex-7.c
+ 3d803b4e2db8420754d245b81b5a6dab  gcc/testsuite/gcc.dg/complex-8.c
+ 14643bb2cd507c440adbd5f14eeb8c81  gcc/testsuite/gcc.dg/complex-9.c
  e4076ab8b4eaeecdcbb527dfc36e6b0a  gcc/testsuite/gcc.dg/compound-literal-1.c
  6f0c2274db9a2a034c64efad43a3d3c4  gcc/testsuite/gcc.dg/compound-literal-cast-lvalue-1.c
  0f6847b008a2fc6d389626675248c378  gcc/testsuite/gcc.dg/compound-lvalue-1.c
*************** af960c05f0a6ab2d5eb3aa99551fa658  gcc/te
*** 51481,51487 ****
  b7bb414df09ccb2077133b21ba630ce8  gcc/testsuite/gcc.dg/cpp/error-1.c
  6a2ac941bc99ce6af7ed79d05fbb5aed  gcc/testsuite/gcc.dg/cpp/escape-1.c
  3f966d736c5e8d8df46521821e7b2f3c  gcc/testsuite/gcc.dg/cpp/escape-2.c
! 8116d5cdfc324e8e41c8048443f8d089  gcc/testsuite/gcc.dg/cpp/escape-3.i
  7e09acd41fc89861253e4344afbcbae7  gcc/testsuite/gcc.dg/cpp/escape.c
  98feceff95879f1cf8369acd89081e91  gcc/testsuite/gcc.dg/cpp/expr-overflow-1.c
  f6fb6c393146f1f70bf2f1d93f98bff3  gcc/testsuite/gcc.dg/cpp/expr.c
--- 51482,51488 ----
  b7bb414df09ccb2077133b21ba630ce8  gcc/testsuite/gcc.dg/cpp/error-1.c
  6a2ac941bc99ce6af7ed79d05fbb5aed  gcc/testsuite/gcc.dg/cpp/escape-1.c
  3f966d736c5e8d8df46521821e7b2f3c  gcc/testsuite/gcc.dg/cpp/escape-2.c
! 504e24adde05d05df423940a050d7f16  gcc/testsuite/gcc.dg/cpp/escape-3.i
  7e09acd41fc89861253e4344afbcbae7  gcc/testsuite/gcc.dg/cpp/escape.c
  98feceff95879f1cf8369acd89081e91  gcc/testsuite/gcc.dg/cpp/expr-overflow-1.c
  f6fb6c393146f1f70bf2f1d93f98bff3  gcc/testsuite/gcc.dg/cpp/expr.c
*************** d88796e35daf5eabf6a8ee3cc6c5e9b7  gcc/te
*** 52092,52097 ****
--- 52093,52099 ----
  6d21f21985c2d4715c08e36712a34aec  gcc/testsuite/gcc.dg/debug/btf/btf-prune-1.c
  7ff8f5f895cbb1b4f721960ab07a3416  gcc/testsuite/gcc.dg/debug/btf/btf-prune-2.c
  bdee9d0b19533d1dd82979282e07138e  gcc/testsuite/gcc.dg/debug/btf/btf-prune-3.c
+ 3aa1cdcf5cf5e8085ce4fda769c0721c  gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c
  0b440f56eed18e1c3b4168dcff147fd6  gcc/testsuite/gcc.dg/debug/btf/btf-prune-maps.c
  ced909b2cb649c5711c59e6dcb7a9f2f  gcc/testsuite/gcc.dg/debug/btf/btf-struct-1.c
  24e60713195a1ffe04be1a29e25919c5  gcc/testsuite/gcc.dg/debug/btf/btf-struct-2.c
*************** b7cc1fa0904bcda319bf91dbe2a3a4fe  gcc/te
*** 52216,52221 ****
--- 52218,52226 ----
  8ced16aaad0cf14e389285740829dfd7  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-1.c
  6113ca1e1c16494adb2dc948aebfed6c  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-2.c
  eaa551be9dc9704721cc33f22856eef5  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-3.c
+ dbfd4c139d6c08de91de37faab7bf31f  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c
+ 3c184fbe7ebe2d2e81766c5325995284  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c
+ 5be8af3b5cd7eae8acf97ed4349673e4  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c
  aa20681eeeb6d41680a1a7954b79d8b8  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-type-tag-1.c
  bca0bce808eccec2810331b87a7fe038  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-type-tag-10.c
  d149ce442eca35321b28c54a0e42cbfe  gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-type-tag-2.c
*************** e402946ef4c438476731cd807abb0d0b  gcc/te
*** 52951,52957 ****
  8bbad26c96bd55f1858e4bdfca0ae1c7  gcc/testsuite/gcc.dg/fold-stringops-2.c
  ab16f59df61d1fa7462735be7c89e03e  gcc/testsuite/gcc.dg/fold-stringops-3.c
  4f2210865daf0cf05e105331c6f9aa8b  gcc/testsuite/gcc.dg/fold-sub.c
! ce78a769d9b55143ac9c7b2fd6ca342a  gcc/testsuite/gcc.dg/fold-vecperm-1.c
  c90dbb8934ec1b212a0e4ecc9b3ca3d5  gcc/testsuite/gcc.dg/fold-xor-1.c
  7d493f5554d1ace59edbb4ff7c5827d9  gcc/testsuite/gcc.dg/fold-xor-2.c
  df2f1c4756e53a97a67a96197444b1c1  gcc/testsuite/gcc.dg/fold-xor-3.c
--- 52956,52962 ----
  8bbad26c96bd55f1858e4bdfca0ae1c7  gcc/testsuite/gcc.dg/fold-stringops-2.c
  ab16f59df61d1fa7462735be7c89e03e  gcc/testsuite/gcc.dg/fold-stringops-3.c
  4f2210865daf0cf05e105331c6f9aa8b  gcc/testsuite/gcc.dg/fold-sub.c
! 66e88c7ea501b2ebc7bffa9b4d386d9c  gcc/testsuite/gcc.dg/fold-vecperm-1.c
  c90dbb8934ec1b212a0e4ecc9b3ca3d5  gcc/testsuite/gcc.dg/fold-xor-1.c
  7d493f5554d1ace59edbb4ff7c5827d9  gcc/testsuite/gcc.dg/fold-xor-2.c
  df2f1c4756e53a97a67a96197444b1c1  gcc/testsuite/gcc.dg/fold-xor-3.c
*************** f19ba5ec082add7d45bee659e0ca766a  gcc/te
*** 53261,53266 ****
--- 53266,53273 ----
  26801e8c9b6cda7f34e1c7d9c7458645  gcc/testsuite/gcc.dg/gimplefe-error-9.c
  a7deb2e877a1f5f71b5144b4d0e6f4ab  gcc/testsuite/gcc.dg/globalalias-2.c
  af413f2a965da90de86711f81ac54bc6  gcc/testsuite/gcc.dg/globalalias.c
+ 70b891a9648a92e71459e138df1764d9  gcc/testsuite/gcc.dg/gnu-compoundlit-1.c
+ 6c37d98c3ca3c5cd01ada8b4d1f6ae88  gcc/testsuite/gcc.dg/gnu-compoundlit-2.c
  644bbd61aaed9ff26399d6df215c0bf6  gcc/testsuite/gcc.dg/gnu-cond-expr-1.c
  b51074560898490ec9b135be86916e73  gcc/testsuite/gcc.dg/gnu-cond-expr-2.c
  dae93188c3869bbff623a97d9f7b2b08  gcc/testsuite/gcc.dg/gnu-cond-expr-3.c
*************** b667b5f1f8c62505fc01d9178b47459d  gcc/te
*** 55698,55716 ****
  a5319bd104f29d7fce777870a81fad4e  gcc/testsuite/gcc.dg/pointer-array-quals-1.c
  5c329c22bd23faf7b838de0e4cbb7af1  gcc/testsuite/gcc.dg/pointer-array-quals-2.c
  87303172cad22f129e26b5f5d00848f7  gcc/testsuite/gcc.dg/pointer-counted-by-1.c
  235b8ad4c1e8f7d345e8f9bfd0d4be3a  gcc/testsuite/gcc.dg/pointer-counted-by-2.c
  6bc63e6bb461685aa63789d592261cd1  gcc/testsuite/gcc.dg/pointer-counted-by-3.c
  55dda7861fc83456d204db29704a9e1b  gcc/testsuite/gcc.dg/pointer-counted-by-4-char.c
  0bec7f1bff0c50976006236a89c9c4e0  gcc/testsuite/gcc.dg/pointer-counted-by-4-float.c
  5f707f3db1b27de3b959ba40397d9ce6  gcc/testsuite/gcc.dg/pointer-counted-by-4-struct.c
  8fc07e8d2e760e2759c331eeab3c7a61  gcc/testsuite/gcc.dg/pointer-counted-by-4-union.c
  a0acf8d13390e8848447fc73fb2b9827  gcc/testsuite/gcc.dg/pointer-counted-by-4.c
  4fb7e10140c253ff0ffeb53bb3ad166e  gcc/testsuite/gcc.dg/pointer-counted-by-5.c
  ae7c56102b7bab6c5480c80a081567d9  gcc/testsuite/gcc.dg/pointer-counted-by-6.c
  cb2a225c4939c4a047c2574e784b9149  gcc/testsuite/gcc.dg/pointer-counted-by-7.c
  bf966c5170e7d5a196dbbed9b62c61d6  gcc/testsuite/gcc.dg/pointer-counted-by-8.c
  60dd9bdbbdf292a0cb9bf8d4a0cadb6a  gcc/testsuite/gcc.dg/pointer-counted-by-9.c
! 9c65bfd5b2e510ef103d9a584f419195  gcc/testsuite/gcc.dg/pointer-counted-by.c
  098a9eb0b304a107d7e16d34e57694dd  gcc/testsuite/gcc.dg/pointer-range-check-1.c
  f5883b8a2323e7318237e3750e037d52  gcc/testsuite/gcc.dg/pointer-range-check-2.c
  560e02ab06396c9dce71b047a8a96f79  gcc/testsuite/gcc.dg/postincr-1.c
--- 55705,55725 ----
  a5319bd104f29d7fce777870a81fad4e  gcc/testsuite/gcc.dg/pointer-array-quals-1.c
  5c329c22bd23faf7b838de0e4cbb7af1  gcc/testsuite/gcc.dg/pointer-array-quals-2.c
  87303172cad22f129e26b5f5d00848f7  gcc/testsuite/gcc.dg/pointer-counted-by-1.c
+ 91902a81aef8ffab5dc550774f889ce2  gcc/testsuite/gcc.dg/pointer-counted-by-10.c
  235b8ad4c1e8f7d345e8f9bfd0d4be3a  gcc/testsuite/gcc.dg/pointer-counted-by-2.c
  6bc63e6bb461685aa63789d592261cd1  gcc/testsuite/gcc.dg/pointer-counted-by-3.c
  55dda7861fc83456d204db29704a9e1b  gcc/testsuite/gcc.dg/pointer-counted-by-4-char.c
  0bec7f1bff0c50976006236a89c9c4e0  gcc/testsuite/gcc.dg/pointer-counted-by-4-float.c
  5f707f3db1b27de3b959ba40397d9ce6  gcc/testsuite/gcc.dg/pointer-counted-by-4-struct.c
  8fc07e8d2e760e2759c331eeab3c7a61  gcc/testsuite/gcc.dg/pointer-counted-by-4-union.c
+ bb6e049ffc6c0ec7e94a6c13bac6c792  gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c
  a0acf8d13390e8848447fc73fb2b9827  gcc/testsuite/gcc.dg/pointer-counted-by-4.c
  4fb7e10140c253ff0ffeb53bb3ad166e  gcc/testsuite/gcc.dg/pointer-counted-by-5.c
  ae7c56102b7bab6c5480c80a081567d9  gcc/testsuite/gcc.dg/pointer-counted-by-6.c
  cb2a225c4939c4a047c2574e784b9149  gcc/testsuite/gcc.dg/pointer-counted-by-7.c
  bf966c5170e7d5a196dbbed9b62c61d6  gcc/testsuite/gcc.dg/pointer-counted-by-8.c
  60dd9bdbbdf292a0cb9bf8d4a0cadb6a  gcc/testsuite/gcc.dg/pointer-counted-by-9.c
! fab3b399e4fdba4426e862fa979f170a  gcc/testsuite/gcc.dg/pointer-counted-by.c
  098a9eb0b304a107d7e16d34e57694dd  gcc/testsuite/gcc.dg/pointer-range-check-1.c
  f5883b8a2323e7318237e3750e037d52  gcc/testsuite/gcc.dg/pointer-range-check-2.c
  560e02ab06396c9dce71b047a8a96f79  gcc/testsuite/gcc.dg/postincr-1.c
*************** ebccf814e2974ae2d3fef79375fc2a74  gcc/te
*** 55959,55965 ****
  c16717b833d5db5a9a8e0b0649ed37bf  gcc/testsuite/gcc.dg/pr107262.c
  4f0d5b8c78199ceef742ba745999898c  gcc/testsuite/gcc.dg/pr107300.c
  66f99f11c840e33dae7bfe0a998c7670  gcc/testsuite/gcc.dg/pr107385.c
- 0215d2ef3b9000a72563a0a5de550edf  gcc/testsuite/gcc.dg/pr107389.c
  e93299ab13ea49e64f3354c006946b72  gcc/testsuite/gcc.dg/pr107505.c
  a7cab6b0b204764793f447272ec896a3  gcc/testsuite/gcc.dg/pr107523.c
  81bc84b5b95958eb5c2583001b6b590a  gcc/testsuite/gcc.dg/pr107547.c
--- 55968,55973 ----
*************** b7d6fb3e14f86c09ea6f178c014109c3  gcc/te
*** 56228,56233 ****
--- 56236,56242 ----
  849572df683294a5f3ad6bb81ee17c53  gcc/testsuite/gcc.dg/pr116546.c
  8a82ecc27f5e5be1a3a5e59a3465ebcf  gcc/testsuite/gcc.dg/pr116588.c
  92460a4ebec7f60dcffc9eb68058c6b8  gcc/testsuite/gcc.dg/pr116726.c
+ 4b92dd736564ce47555375b1e0f42355  gcc/testsuite/gcc.dg/pr116815.c
  3661cd7a3a7e0ed72337f96146acfa54  gcc/testsuite/gcc.dg/pr116850.c
  c1b2e797633e4c55b12e32de20ad49e3  gcc/testsuite/gcc.dg/pr116879.c
  8aed09e5b7a0e94c0ab7d89427bc9ee7  gcc/testsuite/gcc.dg/pr116887.c
*************** debe1bb0f742ad6fe5c8e1d3952c624d  gcc/te
*** 56823,56829 ****
  aa9bb852bac4875a61c8c9843bf4ef2e  gcc/testsuite/gcc.dg/pr41345.c
  5e470e4479566106d5d2e9abcb6f2094  gcc/testsuite/gcc.dg/pr41454.c
  dd22a4c4500ebaa0f16e25ca72fdacf8  gcc/testsuite/gcc.dg/pr41470.c
! b7a4c71ad7952f1747c1a5f262be146d  gcc/testsuite/gcc.dg/pr41488.c
  b676a5cec5452169bcd1a954ca680ba9  gcc/testsuite/gcc.dg/pr41551.c
  84a38326fd86393828d30ef78b78b65d  gcc/testsuite/gcc.dg/pr41573.c
  84de12865866e4c588022676af6bc79d  gcc/testsuite/gcc.dg/pr41574.c
--- 56832,56838 ----
  aa9bb852bac4875a61c8c9843bf4ef2e  gcc/testsuite/gcc.dg/pr41345.c
  5e470e4479566106d5d2e9abcb6f2094  gcc/testsuite/gcc.dg/pr41454.c
  dd22a4c4500ebaa0f16e25ca72fdacf8  gcc/testsuite/gcc.dg/pr41470.c
! 90e3f9333c2f23321b075a73f6ccf681  gcc/testsuite/gcc.dg/pr41488.c
  b676a5cec5452169bcd1a954ca680ba9  gcc/testsuite/gcc.dg/pr41551.c
  84a38326fd86393828d30ef78b78b65d  gcc/testsuite/gcc.dg/pr41573.c
  84de12865866e4c588022676af6bc79d  gcc/testsuite/gcc.dg/pr41574.c
*************** a4e31857d29e491c9e10cab0c7418999  gcc/te
*** 57542,57548 ****
  17af0c6fd22852d41bf563af796ba75d  gcc/testsuite/gcc.dg/pr67964.c
  1b92876bfdf74cd013905bc13a4e3425  gcc/testsuite/gcc.dg/pr68024.c
  bafa800c13b3f396448834609a245b9f  gcc/testsuite/gcc.dg/pr68088_1.c
! 3e58ba46cf918c627ca4d4b6df760309  gcc/testsuite/gcc.dg/pr68090.c
  69c3e3367401a89ffe9e39ef1317df1c  gcc/testsuite/gcc.dg/pr68112.c
  fe7ef582e37d9691649dc50a2e0357f2  gcc/testsuite/gcc.dg/pr68129_1.c
  18d42254aaeedf3ee06abcca146f8308  gcc/testsuite/gcc.dg/pr68134.c
--- 57551,57557 ----
  17af0c6fd22852d41bf563af796ba75d  gcc/testsuite/gcc.dg/pr67964.c
  1b92876bfdf74cd013905bc13a4e3425  gcc/testsuite/gcc.dg/pr68024.c
  bafa800c13b3f396448834609a245b9f  gcc/testsuite/gcc.dg/pr68088_1.c
! 16e50d4d6ac9f78c1bba7e261bd5a01f  gcc/testsuite/gcc.dg/pr68090.c
  69c3e3367401a89ffe9e39ef1317df1c  gcc/testsuite/gcc.dg/pr68112.c
  fe7ef582e37d9691649dc50a2e0357f2  gcc/testsuite/gcc.dg/pr68129_1.c
  18d42254aaeedf3ee06abcca146f8308  gcc/testsuite/gcc.dg/pr68134.c
*************** c4703ef02cfa1fa41deda3412f80e980  gcc/te
*** 58128,58133 ****
--- 58137,58143 ----
  ae6290a43a38f48e933c747a1d1f3299  gcc/testsuite/gcc.dg/pr91134.c
  0835b2ca75603c1c11ac781095ca851d  gcc/testsuite/gcc.dg/pr91172.c
  b3a812009694e752663ca04925320324  gcc/testsuite/gcc.dg/pr91181.c
+ 453b3243dd5e97f67c50f13b57a5677c  gcc/testsuite/gcc.dg/pr91191.c
  21693825c7ee6a622528dd5b0f082c27  gcc/testsuite/gcc.dg/pr91193-1.c
  9289e5ec8b9b1fb287c7605916ca8fae  gcc/testsuite/gcc.dg/pr91193-2.c
  196c4342cb2568a603593ef3a72ee31d  gcc/testsuite/gcc.dg/pr91195.c
*************** dd83a8b867ef8c886adacb097f55bc6b  gcc/te
*** 58342,58347 ****
--- 58352,58359 ----
  071d2ae1bd35b15c3f27a168b4050eb2  gcc/testsuite/gcc.dg/pr97955.c
  2fbd889735fcfc930838d4d0e5f735b3  gcc/testsuite/gcc.dg/pr97979.c
  25eabe894b19890870bd6364b863658a  gcc/testsuite/gcc.dg/pr97981.c
+ fa958ac207273b090e64c87c7bab9a7a  gcc/testsuite/gcc.dg/pr97986-1.c
+ d2ae17f41ffd43a3d17a1bdb3a9b4c66  gcc/testsuite/gcc.dg/pr97986-2.c
  3f8832bc33cb7145586e46cab40d393c  gcc/testsuite/gcc.dg/pr98029.c
  21a998d56f162b789d08957b34fcad4c  gcc/testsuite/gcc.dg/pr98099.c
  ec1830becced622760bda688ca2bb126  gcc/testsuite/gcc.dg/pr9814-1.c
*************** c17159dabf628310bc542029267ef6ef  gcc/te
*** 59866,59871 ****
--- 59878,59884 ----
  9e13dab25399fb10996bbceba359de9a  gcc/testsuite/gcc.dg/torture/pr107115.c
  366b77cfd22f49d273d0dcf2caf64235  gcc/testsuite/gcc.dg/torture/pr107176.c
  917ef0b6176966a68d17d6bd6285446b  gcc/testsuite/gcc.dg/torture/pr107301.c
+ e36bece3cbcac8068401f049f5db92ec  gcc/testsuite/gcc.dg/torture/pr107389.c
  478730bb4770bc629982821178a47f1f  gcc/testsuite/gcc.dg/torture/pr107407.c
  f533117b3ab96be08cf3daab9f874c30  gcc/testsuite/gcc.dg/torture/pr107435.c
  8a45c1212793c3a86f7cf259756d9723  gcc/testsuite/gcc.dg/torture/pr107447.c
*************** efa374cf4f5d41b91ecac6e1e98ac293  gcc/te
*** 60129,60134 ****
--- 60142,60149 ----
  a53ed0c2a08c21b00c8d5487bbc823d7  gcc/testsuite/gcc.dg/torture/pr122079-3.c
  d4560440fd7b3647f8780537a59e4716  gcc/testsuite/gcc.dg/torture/pr122188.c
  fcc3a6f68a967a257f515d11f06532c2  gcc/testsuite/gcc.dg/torture/pr122212.c
+ 86ec8497180b8c6845f5efb789a8d30e  gcc/testsuite/gcc.dg/torture/pr122497-1.c
+ d9ab318bf88df260c040cad6b5bc8c90  gcc/testsuite/gcc.dg/torture/pr122502.c
  ded4330fd1cd52783bd9b1761db038ef  gcc/testsuite/gcc.dg/torture/pr16104-1.c
  fc265ee05da2f29f0e92804661cd1f28  gcc/testsuite/gcc.dg/torture/pr17526.c
  01c583edb41b632b835aa892b9c1cb14  gcc/testsuite/gcc.dg/torture/pr17933-1.c
*************** b51831242139a92b34dbcd60cebb1cd5  gcc/te
*** 61790,61803 ****
  67d0a347d377cdd5876ed6d3ffc4103b  gcc/testsuite/gcc.dg/tree-ssa/cswtch-6.c
  a7ee922e30693d72b161287620162cc4  gcc/testsuite/gcc.dg/tree-ssa/cswtch-7.c
  59e69728c798843be3e7e01a41019422  gcc/testsuite/gcc.dg/tree-ssa/cswtch.c
! 3a98d5ff303f51c628fb855f94b30645  gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c
! 2693b3a5d1d97d4cb3f14fea48ab348f  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c
! 8c15d450f70c55e1df99047b1f5ebadd  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c
! 1562a40decbf6829917394385b2e15c7  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c
! 9352768f3425f32a544c025e45842abf  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c
! 9b1b0e048c8f97b78d9a81a7d35ff0cd  gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c
! bc15b035f75616d49ae3217feb655970  gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c
! 0b0b6aee09e8f5c99b5dd453262a9560  gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c
  00a5789f4787f29247de180d1f75c125  gcc/testsuite/gcc.dg/tree-ssa/cunroll-1.c
  32eb8903d0c34fb7ebbfdf653428cab1  gcc/testsuite/gcc.dg/tree-ssa/cunroll-10.c
  5e78a0f7c81199d9572e9eb72b2b9b6c  gcc/testsuite/gcc.dg/tree-ssa/cunroll-11.c
--- 61805,61819 ----
  67d0a347d377cdd5876ed6d3ffc4103b  gcc/testsuite/gcc.dg/tree-ssa/cswtch-6.c
  a7ee922e30693d72b161287620162cc4  gcc/testsuite/gcc.dg/tree-ssa/cswtch-7.c
  59e69728c798843be3e7e01a41019422  gcc/testsuite/gcc.dg/tree-ssa/cswtch.c
! d828b3c3b47559f668395b6499bae8f7  gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c
! 0c2e8b89d38d92078d06d1cdf2afb596  gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c
! dcd8e98ed7d206d39eae19ea623d2985  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c
! 8040629cefe8139efef7e9b6c12bd92c  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c
! 1e484fb4ddedc4a228416ca6a9660a31  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c
! e3ad70e4e3c4aea531b751d7029d71cf  gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c
! 927bdbb7181c03596675da8973ddd620  gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c
! 228d7880ca99b024c05fdb8caf55b0bd  gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c
! 47d23689fc9ca5f4e36d43d15c42aec9  gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c
  00a5789f4787f29247de180d1f75c125  gcc/testsuite/gcc.dg/tree-ssa/cunroll-1.c
  32eb8903d0c34fb7ebbfdf653428cab1  gcc/testsuite/gcc.dg/tree-ssa/cunroll-10.c
  5e78a0f7c81199d9572e9eb72b2b9b6c  gcc/testsuite/gcc.dg/tree-ssa/cunroll-11.c
*************** fc8efeaf2ed7c9bba5d4f1717e7e356b  gcc/te
*** 61905,61910 ****
--- 61921,61927 ----
  cb909e7812f73f90414b63042c95d199  gcc/testsuite/gcc.dg/tree-ssa/forwprop-4.c
  eb894750e8c2c762096d861a6009f51a  gcc/testsuite/gcc.dg/tree-ssa/forwprop-40.c
  de3171692db53449fdcaa8f1c1e1676c  gcc/testsuite/gcc.dg/tree-ssa/forwprop-41.c
+ 4c3d8a17c3c05c47aeb8205fb8aca518  gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c
  d56422e63543fcf4bf4b78d825c534da  gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c
  0f6dc2b3b3469af9cd27d5b5cd97353c  gcc/testsuite/gcc.dg/tree-ssa/forwprop-6.c
  a9096c4b5b756bdc9dcc196398730d73  gcc/testsuite/gcc.dg/tree-ssa/forwprop-7.c
*************** d995b9152fb033c1efa90b7c0930e6f9  gcc/te
*** 62432,62438 ****
  ce036f14fca174d66f05f8e0619e160f  gcc/testsuite/gcc.dg/tree-ssa/pr110637-3.c
  972f1ff8349023459362c48f1ddff426  gcc/testsuite/gcc.dg/tree-ssa/pr110753.c
  04fd298aa9bd6b97a889de59aa8af394  gcc/testsuite/gcc.dg/tree-ssa/pr110923.c
! d5180ea60b2d8b5f25bfa5a4c0dc247a  gcc/testsuite/gcc.dg/tree-ssa/pr111003.c
  9867ac011ab80a4d47fae1c84e82017b  gcc/testsuite/gcc.dg/tree-ssa/pr111150-1.c
  6c360e4c7d3378333636b2800b27479f  gcc/testsuite/gcc.dg/tree-ssa/pr111150.c
  b9c5a68b2233aa836355012fa917a7b5  gcc/testsuite/gcc.dg/tree-ssa/pr111294.c
--- 62449,62455 ----
  ce036f14fca174d66f05f8e0619e160f  gcc/testsuite/gcc.dg/tree-ssa/pr110637-3.c
  972f1ff8349023459362c48f1ddff426  gcc/testsuite/gcc.dg/tree-ssa/pr110753.c
  04fd298aa9bd6b97a889de59aa8af394  gcc/testsuite/gcc.dg/tree-ssa/pr110923.c
! 51baeb9644850777d1f7c201cd4b0858  gcc/testsuite/gcc.dg/tree-ssa/pr111003.c
  9867ac011ab80a4d47fae1c84e82017b  gcc/testsuite/gcc.dg/tree-ssa/pr111150-1.c
  6c360e4c7d3378333636b2800b27479f  gcc/testsuite/gcc.dg/tree-ssa/pr111150.c
  b9c5a68b2233aa836355012fa917a7b5  gcc/testsuite/gcc.dg/tree-ssa/pr111294.c
*************** ef9f94de68c006babcf9169489ed1b51  gcc/te
*** 62490,62495 ****
--- 62507,62513 ----
  f4c56a02709c699f81b07b81dd1a2c1e  gcc/testsuite/gcc.dg/tree-ssa/pr122033-1.c
  1f4ed1b8fa56e5300281263805887fd0  gcc/testsuite/gcc.dg/tree-ssa/pr122033-2.c
  6564cdc8a2e0bef445546d4a4df278f9  gcc/testsuite/gcc.dg/tree-ssa/pr122153-1.c
+ 73226ac793de9237622d64ee6a7399cc  gcc/testsuite/gcc.dg/tree-ssa/pr122478.c
  78e6c5fe63f7305009c8a79840fe20dc  gcc/testsuite/gcc.dg/tree-ssa/pr13146.c
  eab19e0c04884cd782c9879cbe292109  gcc/testsuite/gcc.dg/tree-ssa/pr14341.c
  9945ed7002a5f7d4918e8ff5eb4cb647  gcc/testsuite/gcc.dg/tree-ssa/pr14490-1.c
*************** c5ffd6d4bede70b5bdd0e2b785a79766  gcc/te
*** 62956,62962 ****
  a102dbb914eaebfac7b2a2226a1b25c8  gcc/testsuite/gcc.dg/tree-ssa/pr92712-3.c
  a11359c472cb26b9988e9e82b35093c5  gcc/testsuite/gcc.dg/tree-ssa/pr92734-2.c
  3663a39ac9a69a1ff68fb0de1ecf2840  gcc/testsuite/gcc.dg/tree-ssa/pr92734.c
! 8edbd6e66e0161b4832f9cec2bcfec47  gcc/testsuite/gcc.dg/tree-ssa/pr92834.c
  7dfc09abf1b28ac3735cb4bd89a16ccd  gcc/testsuite/gcc.dg/tree-ssa/pr92930.c
  ca014276e5f9cd1e1500f2830781f240  gcc/testsuite/gcc.dg/tree-ssa/pr93118.c
  019fdc71b1f5726bb310324278d3460f  gcc/testsuite/gcc.dg/tree-ssa/pr93121-1.c
--- 62974,62980 ----
  a102dbb914eaebfac7b2a2226a1b25c8  gcc/testsuite/gcc.dg/tree-ssa/pr92712-3.c
  a11359c472cb26b9988e9e82b35093c5  gcc/testsuite/gcc.dg/tree-ssa/pr92734-2.c
  3663a39ac9a69a1ff68fb0de1ecf2840  gcc/testsuite/gcc.dg/tree-ssa/pr92734.c
! e900263f883f27e1d8ac80e9006235c6  gcc/testsuite/gcc.dg/tree-ssa/pr92834.c
  7dfc09abf1b28ac3735cb4bd89a16ccd  gcc/testsuite/gcc.dg/tree-ssa/pr92930.c
  ca014276e5f9cd1e1500f2830781f240  gcc/testsuite/gcc.dg/tree-ssa/pr93118.c
  019fdc71b1f5726bb310324278d3460f  gcc/testsuite/gcc.dg/tree-ssa/pr93121-1.c
*************** c696d7723e6935b64e8868efdada71d9  gcc/te
*** 63427,63432 ****
--- 63445,63451 ----
  1c8adc8ead2883bcec8e9fb990e55c8e  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-109.c
  5561c38451474a42839647e4e156c010  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-11.c
  78f5b94faf6fa73b44dd51964967e5c2  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-110.c
+ e17e18c4987b53f256b8271310af6347  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c
  5561c38451474a42839647e4e156c010  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-12.c
  b95088c9ed88a484349d681f36871312  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-13.c
  87ba541be7f38ef117b8b5cc09ff4932  gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-14.c
*************** f1a49246f84d8fbab3d2b6aa5c89949e  gcc/te
*** 64958,64963 ****
--- 64977,64983 ----
  67399a1e5fca0d02800db020357f3722  gcc/testsuite/gcc.dg/vect/pr121949_3.c
  8cbd2daa28dcf298c1e79004b6ec12cf  gcc/testsuite/gcc.dg/vect/pr122023.c
  08c808506725be00bdf4d84893d5e2e2  gcc/testsuite/gcc.dg/vect/pr122158.c
+ 98753a41f3e4540c72096a83675cd6cc  gcc/testsuite/gcc.dg/vect/pr122419.c
  42d48d2ecd5682545b12ac42f879a831  gcc/testsuite/gcc.dg/vect/pr16105.c
  231c99dba9475fe09525bbf6f4374124  gcc/testsuite/gcc.dg/vect/pr18308.c
  915cf38408eaa7fee5013d90ec1c3251  gcc/testsuite/gcc.dg/vect/pr18400.c
*************** e75c09f3eb5fab5920e6bbe5a24c7bd6  gcc/te
*** 65454,65459 ****
--- 65474,65480 ----
  f611850bdcf6c79cc21bf0f12c5469e8  gcc/testsuite/gcc.dg/vect/slp-reduc-10e.c
  72470473142b614c9abbb4961ae363e0  gcc/testsuite/gcc.dg/vect/slp-reduc-11.c
  2b55baa2aeb47417a231e321d018033f  gcc/testsuite/gcc.dg/vect/slp-reduc-12.c
+ efeaa043d177e194cd96123499e925b1  gcc/testsuite/gcc.dg/vect/slp-reduc-13.c
  13f8e9309546363711eaedb177e2c8b9  gcc/testsuite/gcc.dg/vect/slp-reduc-2.c
  f51f95ff41057eaf23cde404d8d413fa  gcc/testsuite/gcc.dg/vect/slp-reduc-3.c
  89c86f9f96410c8bc70b4ce593a92d1e  gcc/testsuite/gcc.dg/vect/slp-reduc-4.c
*************** df438928392b81c11f2a1e3220ae04a3  gcc/te
*** 65466,65476 ****
  066c96f1ae2a9f0f0508e5f06659427c  gcc/testsuite/gcc.dg/vect/slp-reduc-sad.c
  bce659f36d2c583cb99462b31ce124ad  gcc/testsuite/gcc.dg/vect/slp-simd-clone-1.c
  b0a87850d8d88048ac704db35dcc2459  gcc/testsuite/gcc.dg/vect/slp-simd-clone-2.c
! 8bdc194c5dbf3576077b33bb90449c00  gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
  582f4de89dcf598a96b7dabf673209dd  gcc/testsuite/gcc.dg/vect/slp-widen-mult-s16.c
  cbfea86deb7a2172db8304b50540da0c  gcc/testsuite/gcc.dg/vect/slp-widen-mult-u8.c
  d38a6ca365de8c64ad051edd81d62d6b  gcc/testsuite/gcc.dg/vect/trapv-vect-reduc-4.c
! 0d80df321da1e267172df96267f9af63  gcc/testsuite/gcc.dg/vect/tree-vect.h
  e89cc050a04f95cc194e9469aa72808f  gcc/testsuite/gcc.dg/vect/tsvc/license.txt
  2bded60305772f7de251bb70ce5ae96f  gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h
  9f6419b4c50931a4103f67c8213f8a60  gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s000.c
--- 65487,65497 ----
  066c96f1ae2a9f0f0508e5f06659427c  gcc/testsuite/gcc.dg/vect/slp-reduc-sad.c
  bce659f36d2c583cb99462b31ce124ad  gcc/testsuite/gcc.dg/vect/slp-simd-clone-1.c
  b0a87850d8d88048ac704db35dcc2459  gcc/testsuite/gcc.dg/vect/slp-simd-clone-2.c
! af29abb65e6b1d76eb0832249ab100f7  gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
  582f4de89dcf598a96b7dabf673209dd  gcc/testsuite/gcc.dg/vect/slp-widen-mult-s16.c
  cbfea86deb7a2172db8304b50540da0c  gcc/testsuite/gcc.dg/vect/slp-widen-mult-u8.c
  d38a6ca365de8c64ad051edd81d62d6b  gcc/testsuite/gcc.dg/vect/trapv-vect-reduc-4.c
! ef2ac77de2fba07b5997a1a10b11f73f  gcc/testsuite/gcc.dg/vect/tree-vect.h
  e89cc050a04f95cc194e9469aa72808f  gcc/testsuite/gcc.dg/vect/tsvc/license.txt
  2bded60305772f7de251bb70ce5ae96f  gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h
  9f6419b4c50931a4103f67c8213f8a60  gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s000.c
*************** b4f31e51d7444b0dbc43aff2dc3d5426  gcc/te
*** 66534,66551 ****
  28cfda3bc854be355322e26b1cadc604  gcc/testsuite/gcc.dg/vect/vect-widen-mult-2.c
  c409a040921012445ba61789d66778ab  gcc/testsuite/gcc.dg/vect/vect-widen-mult-3.c
  6928783caf5a4aaf0261975fe55ca576  gcc/testsuite/gcc.dg/vect/vect-widen-mult-4.c
! b8d465b886de8f059bcf419385dfa565  gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c
! 6d5435b75eea3429d44a61b22d96dea7  gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c
  9297df8190d814d4a7e82544e483ca78  gcc/testsuite/gcc.dg/vect/vect-widen-mult-extern-1.c
! 611f9bbbf3e4c95565b2232c8fbc80be  gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
! 1f445f4e00fabf096f808f689b53397e  gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
  0ca4cfa6145afbdc4b13e3ca575fe327  gcc/testsuite/gcc.dg/vect/vect-widen-mult-s16.c
  ef6123bca5b0e71a26d4094e2c7ab7e2  gcc/testsuite/gcc.dg/vect/vect-widen-mult-s8.c
  4d8384a6755a406e8a0acfa99c50425e  gcc/testsuite/gcc.dg/vect/vect-widen-mult-sum.c
! 821f75c53b8b7fc52d6a748921350808  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c
! 4f6079115944850e56fe66afdfbe3762  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c
! 72c5fffdc3e8d1e48e931707a796b379  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c
! 9d064300c8131a8b12d42e840a0218ef  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c
  3f152091dccbd974d6c65fe6f1a3e9eb  gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c
  57a16ece134220af9fcef6f72f220c2d  gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c
  5b67f59c833986f08bd4b40c60f69162  gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c
--- 66555,66572 ----
  28cfda3bc854be355322e26b1cadc604  gcc/testsuite/gcc.dg/vect/vect-widen-mult-2.c
  c409a040921012445ba61789d66778ab  gcc/testsuite/gcc.dg/vect/vect-widen-mult-3.c
  6928783caf5a4aaf0261975fe55ca576  gcc/testsuite/gcc.dg/vect/vect-widen-mult-4.c
! 4f98687a598882780fd6e66f32a316e2  gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c
! dcf32e10eadcb638f464b7b3dac6b5e4  gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c
  9297df8190d814d4a7e82544e483ca78  gcc/testsuite/gcc.dg/vect/vect-widen-mult-extern-1.c
! 1610f5b8739467a0ce76ee64012183b1  gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
! 19a2e1f6c8cfac84103282469dfdfc5a  gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
  0ca4cfa6145afbdc4b13e3ca575fe327  gcc/testsuite/gcc.dg/vect/vect-widen-mult-s16.c
  ef6123bca5b0e71a26d4094e2c7ab7e2  gcc/testsuite/gcc.dg/vect/vect-widen-mult-s8.c
  4d8384a6755a406e8a0acfa99c50425e  gcc/testsuite/gcc.dg/vect/vect-widen-mult-sum.c
! 80bc92e96ec3650799d9a3bcb7d17769  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c
! dd358cf9949b492d8381a5c5da511117  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c
! caec8b8c2f8388721c36040b6b6122ae  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c
! 3ed0e6fbf3cc8b5c041dd1014fec56a7  gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c
  3f152091dccbd974d6c65fe6f1a3e9eb  gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c
  57a16ece134220af9fcef6f72f220c2d  gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c
  5b67f59c833986f08bd4b40c60f69162  gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c
*************** e24d0f20e739156ac3cf1c83cb940873  gcc/te
*** 66617,66624 ****
  18f8fa8a55cbcb4e18bf8230f6f1d37f  gcc/testsuite/gcc.dg/vla-init-1.c
  0cc7ec34ad1b21fe811a038e5f9a3f15  gcc/testsuite/gcc.dg/vla-init-2.c
  3ebc83a0a0f2edba6c53937797fcfaef  gcc/testsuite/gcc.dg/vla-init-3.c
! 943b40322a964bc97313e85b4eb158b6  gcc/testsuite/gcc.dg/vla-init-4.c
! 17d2fd5480a0274dbb802302e84e1945  gcc/testsuite/gcc.dg/vla-init-5.c
  606eab8fad2be2d932462e287e1844f9  gcc/testsuite/gcc.dg/vla-stexp-1.c
  4c105c3cc03ecd8a5cd52eb50fbbc5b6  gcc/testsuite/gcc.dg/vla-stexp-2.c
  42e032d18ea40563e277a533aed62bf7  gcc/testsuite/gcc.dg/vla-stexp-3.c
--- 66638,66645 ----
  18f8fa8a55cbcb4e18bf8230f6f1d37f  gcc/testsuite/gcc.dg/vla-init-1.c
  0cc7ec34ad1b21fe811a038e5f9a3f15  gcc/testsuite/gcc.dg/vla-init-2.c
  3ebc83a0a0f2edba6c53937797fcfaef  gcc/testsuite/gcc.dg/vla-init-3.c
! b6af5789aab1e4a210dcd7fd3471a0e6  gcc/testsuite/gcc.dg/vla-init-4.c
! 00259120ba3ce394259501452fe828c7  gcc/testsuite/gcc.dg/vla-init-5.c
  606eab8fad2be2d932462e287e1844f9  gcc/testsuite/gcc.dg/vla-stexp-1.c
  4c105c3cc03ecd8a5cd52eb50fbbc5b6  gcc/testsuite/gcc.dg/vla-stexp-2.c
  42e032d18ea40563e277a533aed62bf7  gcc/testsuite/gcc.dg/vla-stexp-3.c
*************** cf174bb4218a2ff6650d0ab674702881  gcc/te
*** 68713,68718 ****
--- 68734,68741 ----
  83ac293146b05a62ec4a19e52751ebd1  gcc/testsuite/gcc.target/aarch64/pr121253.c
  a67b71d65cb6bd7b6c05a378464741e6  gcc/testsuite/gcc.target/aarch64/pr121290.c
  64cb9b1e14577523fd3ff2306b1eaa44  gcc/testsuite/gcc.target/aarch64/pr121300.c
+ c34d772e393da040a9ab73442d231d49  gcc/testsuite/gcc.target/aarch64/pr121853_1.c
+ bf526d120c538bd714985ac66c46f7bb  gcc/testsuite/gcc.target/aarch64/pr121853_2.c
  4821dff6c48b3d6689b8fe50feaeb1c0  gcc/testsuite/gcc.target/aarch64/pr122069_1.c
  4c7c0d46a40719aecb2fdb238a2c596c  gcc/testsuite/gcc.target/aarch64/pr122069_2.c
  fd8128a2ace2daef0e57c5d400699061  gcc/testsuite/gcc.target/aarch64/pr122069_3.c
*************** d40889fae1768a14cef6690dad5cc3e8  gcc/te
*** 73021,73026 ****
--- 73044,73051 ----
  0e217a64581eaba808cbf7c5b4739165  gcc/testsuite/gcc.target/aarch64/sve/div_1_run.c
  94f88ced71e77ab0242f6df5be71452d  gcc/testsuite/gcc.target/aarch64/sve/div_const_run.c
  b756b55bf45e469c93050878d9bef905  gcc/testsuite/gcc.target/aarch64/sve/dot_1.c
+ a3c2384d6eb0f93991acb4c6b23fee98  gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c
+ 4368190aeea11dd122ed02d629622b24  gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c
  59d027478629ce67c63b59da21b266c8  gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c
  657769d7a7292850421bf9c9f489ce6b  gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1_run.c
  79f15d195cc9087e1d6665345a3f5123  gcc/testsuite/gcc.target/aarch64/sve/dup_lane_1.c
*************** b61291f78078147f21c923a3c8b81a63  gcc/te
*** 80066,80071 ****
--- 80091,80097 ----
  c2fc6d1ea97f22057cf58d7025837704  gcc/testsuite/gcc.target/avr/pr115830-lsr.c
  a221ce1cf8f087e1b841edfdc50cf1d1  gcc/testsuite/gcc.target/avr/pr115830-sub-ext.c
  6f031744eb7ae87b9e251bb5492208f6  gcc/testsuite/gcc.target/avr/pr115830-sub.c
+ b4c1968ee63a61f92dc6808c44852bd9  gcc/testsuite/gcc.target/avr/pr121198.c
  c8dee67a2567af17cd08c345a4ef3aea  gcc/testsuite/gcc.target/avr/pr122220.c
  abbae4b0f7390ccdb0c5394f5172173a  gcc/testsuite/gcc.target/avr/pr122222-sitod.c
  8d351de18b6ca99f76c43eaa14213d53  gcc/testsuite/gcc.target/avr/pr46779-1.c
*************** ab53af0eb6dbfe2791a8ac1bbaf0c11f  gcc/te
*** 80212,80218 ****
  a173627a728a3a28f74aa74c158b1ec4  gcc/testsuite/gcc.target/avr/torture/pr77326.c
  906790488711dd165991fe5b616d5188  gcc/testsuite/gcc.target/avr/torture/pr83729.c
  1367dacfc14196df93b1652cd803474b  gcc/testsuite/gcc.target/avr/torture/pr83801.c
! 86d5641d62f909052432204bd3f47770  gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c
  02a618f0714d48ef7ec2f35b995a706c  gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-2.c
  690d69546d72db49fcb1141d42087a75  gcc/testsuite/gcc.target/avr/torture/pr85624.c
  a09e14ca01139fcd5c0b1d1207a7dfe0  gcc/testsuite/gcc.target/avr/torture/pr87376.c
--- 80238,80244 ----
  a173627a728a3a28f74aa74c158b1ec4  gcc/testsuite/gcc.target/avr/torture/pr77326.c
  906790488711dd165991fe5b616d5188  gcc/testsuite/gcc.target/avr/torture/pr83729.c
  1367dacfc14196df93b1652cd803474b  gcc/testsuite/gcc.target/avr/torture/pr83801.c
! 0ee2d1c29e2c413f092fb7ed58bd42a6  gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c
  02a618f0714d48ef7ec2f35b995a706c  gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-2.c
  690d69546d72db49fcb1141d42087a75  gcc/testsuite/gcc.target/avr/torture/pr85624.c
  a09e14ca01139fcd5c0b1d1207a7dfe0  gcc/testsuite/gcc.target/avr/torture/pr87376.c
*************** fa6ebeb8a38629b307b197117b388ef7  gcc/te
*** 85490,85496 ****
  28a4a0d6bd0e09a7f1da7f5515db9c70  gcc/testsuite/gcc.target/i386/builtin-copysign-6.c
  eeb2c795579e4b693eed6b471e041925  gcc/testsuite/gcc.target/i386/builtin-copysign-7.c
  4dde22c7279c7c8e684af5f718431d7d  gcc/testsuite/gcc.target/i386/builtin-copysign-8a.c
! a6cac29ed0855c52ab4ab6fa01911e5f  gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c
  04d6147486a507d49f5d165aac499b5d  gcc/testsuite/gcc.target/i386/builtin-copysign.c
  7c1badccd4856954ccba2139093860d2  gcc/testsuite/gcc.target/i386/builtin-fabs-1.c
  eb024e3b157728adf6d4f14b1bd4c69d  gcc/testsuite/gcc.target/i386/builtin-fabs-2.c
--- 85516,85522 ----
  28a4a0d6bd0e09a7f1da7f5515db9c70  gcc/testsuite/gcc.target/i386/builtin-copysign-6.c
  eeb2c795579e4b693eed6b471e041925  gcc/testsuite/gcc.target/i386/builtin-copysign-7.c
  4dde22c7279c7c8e684af5f718431d7d  gcc/testsuite/gcc.target/i386/builtin-copysign-8a.c
! 19fe0cd1992bc2d71db601dda2c2bd34  gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c
  04d6147486a507d49f5d165aac499b5d  gcc/testsuite/gcc.target/i386/builtin-copysign.c
  7c1badccd4856954ccba2139093860d2  gcc/testsuite/gcc.target/i386/builtin-fabs-1.c
  eb024e3b157728adf6d4f14b1bd4c69d  gcc/testsuite/gcc.target/i386/builtin-fabs-2.c
*************** a2960f70e9092f35ab7846d97bc2cd2a  gcc/te
*** 85547,85557 ****
--- 85573,85588 ----
  d9248423c9f1c716a36c066054a7f5b9  gcc/testsuite/gcc.target/i386/cet-switch-2.c
  b20d49e3df7ecba263d6a023f199461f  gcc/testsuite/gcc.target/i386/cet-switch-3.c
  5f04987af425e4bdd6af970c8dbd52c7  gcc/testsuite/gcc.target/i386/cf_check-1.c
+ f4872e03d1c7304a4bec272a2fe13dce  gcc/testsuite/gcc.target/i386/cf_check-10.c
+ da7afaa484f59e8dbdf4c68edba73d50  gcc/testsuite/gcc.target/i386/cf_check-11.c
  509c1c95f3a1096c762b7fd019e83e4e  gcc/testsuite/gcc.target/i386/cf_check-2.c
  77f13ccc769fbeb31556af0dea458693  gcc/testsuite/gcc.target/i386/cf_check-3.c
  5c3b7040795451a42f588086b955b02d  gcc/testsuite/gcc.target/i386/cf_check-4.c
  365b20e670ddcffaf52fe6a4f718095f  gcc/testsuite/gcc.target/i386/cf_check-5.c
  e3bc6bdf24f38e69ec436864405bc65d  gcc/testsuite/gcc.target/i386/cf_check-6.c
+ cdcd52464119162fae9929d9eb5230fe  gcc/testsuite/gcc.target/i386/cf_check-7.c
+ 5c8d09cd4849698374e9325b9233a400  gcc/testsuite/gcc.target/i386/cf_check-8.c
+ 89c6eae337ef104e2bfd58d5fabdc05b  gcc/testsuite/gcc.target/i386/cf_check-9.c
  d236bc684017e128d2809e943a21a577  gcc/testsuite/gcc.target/i386/cldemote-1.c
  993cba0e31e78353b3247fbc2d6ab5e5  gcc/testsuite/gcc.target/i386/cleanup-1.c
  661baae059c4a949fc8987d711d9be61  gcc/testsuite/gcc.target/i386/cleanup-2.c
*************** a7f204e20c0df5dad30eac30c4a089ab  gcc/te
*** 86325,86331 ****
  30f81baa74eb17e2f287e035925477c6  gcc/testsuite/gcc.target/i386/no-callee-saved-1.c
  4db6dbf3a78ed414f7c6ea5b1cad2d77  gcc/testsuite/gcc.target/i386/no-callee-saved-10.c
  f3e395b65622feac99889a0a7b3407ca  gcc/testsuite/gcc.target/i386/no-callee-saved-11.c
! e5188370fac870f1044da14bdbfa0928  gcc/testsuite/gcc.target/i386/no-callee-saved-12.c
  42bd97eb7c2cc9b7ea74515a0c4cf3ce  gcc/testsuite/gcc.target/i386/no-callee-saved-13.c
  ce847ee191adcc1a562b86eae8463fe1  gcc/testsuite/gcc.target/i386/no-callee-saved-14.c
  28070df22cbeb8bdda40326e1f3db379  gcc/testsuite/gcc.target/i386/no-callee-saved-15.c
--- 86356,86362 ----
  30f81baa74eb17e2f287e035925477c6  gcc/testsuite/gcc.target/i386/no-callee-saved-1.c
  4db6dbf3a78ed414f7c6ea5b1cad2d77  gcc/testsuite/gcc.target/i386/no-callee-saved-10.c
  f3e395b65622feac99889a0a7b3407ca  gcc/testsuite/gcc.target/i386/no-callee-saved-11.c
! b0015a9bcc0c4efd0261a58f3798d964  gcc/testsuite/gcc.target/i386/no-callee-saved-12.c
  42bd97eb7c2cc9b7ea74515a0c4cf3ce  gcc/testsuite/gcc.target/i386/no-callee-saved-13.c
  ce847ee191adcc1a562b86eae8463fe1  gcc/testsuite/gcc.target/i386/no-callee-saved-14.c
  28070df22cbeb8bdda40326e1f3db379  gcc/testsuite/gcc.target/i386/no-callee-saved-15.c
*************** a006d0528b5396c949ad41d70bbe59d3  gcc/te
*** 87189,87194 ****
--- 87220,87226 ----
  b032673fbd5ea0fa71ec43f67e37cd44  gcc/testsuite/gcc.target/i386/pr116621.c
  204f68736fb9dcb0b78a56062fcbeff7  gcc/testsuite/gcc.target/i386/pr116675.c
  ea223879616e9328b5dc0fdff9dfb021  gcc/testsuite/gcc.target/i386/pr116725.c
+ b0ca893acbcebd62e1a629d54c72cdfe  gcc/testsuite/gcc.target/i386/pr116815.c
  15bae7870bdfe5399b1490ea96088982  gcc/testsuite/gcc.target/i386/pr116839.c
  575b8c9325e05d9cc8bf9da40157ca6c  gcc/testsuite/gcc.target/i386/pr116896.c
  5ec9d676bcac04a40f99ae0d3f4b483a  gcc/testsuite/gcc.target/i386/pr116921.c
*************** ae9cefa4d949ae63e9380aeb14fae221  gcc/te
*** 87394,87399 ****
--- 87426,87433 ----
  ff0a586f8aaac7078fb79402d3f0df4b  gcc/testsuite/gcc.target/i386/pr122320-mask4.c
  9a861d0f957f59a5dc5e7cafeddd1343  gcc/testsuite/gcc.target/i386/pr122320-mask64.c
  f6a03ec739c3c632b84006aa8e240dae  gcc/testsuite/gcc.target/i386/pr122320-mask8.c
+ beaa59876937a489a8ce9f276a586c83  gcc/testsuite/gcc.target/i386/pr122457.c
+ b5fef8fb540e17f32442a50d6ee40f1e  gcc/testsuite/gcc.target/i386/pr122518.c
  f99f88a6e994ad6e55e065e41bc58f8f  gcc/testsuite/gcc.target/i386/pr12329.c
  8951a1fa31f2d45ef9eacfff6a733f77  gcc/testsuite/gcc.target/i386/pr13366.c
  9a752a4b3b77930d91d3c8b0c8897b90  gcc/testsuite/gcc.target/i386/pr13685.c
*************** af443a637b1bbe94c00fa9497d96f7bb  gcc/te
*** 89356,89362 ****
  f57a82588645a68210589a6abc683ddb  gcc/testsuite/gcc.target/i386/preserve-none-14.c
  b6a1cde1548013b66be47a3cd36c9945  gcc/testsuite/gcc.target/i386/preserve-none-15.c
  6f0b161e274978fc465705acdebb3969  gcc/testsuite/gcc.target/i386/preserve-none-16.c
! 2a363e5704fe55548d7ba10d2285e825  gcc/testsuite/gcc.target/i386/preserve-none-17.c
  39b85791a1f4d96f8f6146862340680f  gcc/testsuite/gcc.target/i386/preserve-none-18.c
  21024146d5998abe9f0de92fd6da0b0f  gcc/testsuite/gcc.target/i386/preserve-none-19.c
  4d774ef666e5d98759b5daea23ae8434  gcc/testsuite/gcc.target/i386/preserve-none-2.c
--- 89390,89396 ----
  f57a82588645a68210589a6abc683ddb  gcc/testsuite/gcc.target/i386/preserve-none-14.c
  b6a1cde1548013b66be47a3cd36c9945  gcc/testsuite/gcc.target/i386/preserve-none-15.c
  6f0b161e274978fc465705acdebb3969  gcc/testsuite/gcc.target/i386/preserve-none-16.c
! f85582df9bec9b4c497c5bb05affa30b  gcc/testsuite/gcc.target/i386/preserve-none-17.c
  39b85791a1f4d96f8f6146862340680f  gcc/testsuite/gcc.target/i386/preserve-none-18.c
  21024146d5998abe9f0de92fd6da0b0f  gcc/testsuite/gcc.target/i386/preserve-none-19.c
  4d774ef666e5d98759b5daea23ae8434  gcc/testsuite/gcc.target/i386/preserve-none-2.c
*************** bde7ba2405e4971efe4fb79faf6333ec  gcc/te
*** 90678,90685 ****
  d984aef61afc8f09af4c880507f6c6e6  gcc/testsuite/gcc.target/loongarch/cmodel-func-attr-1.c
  50ab91c6f8ea866c2cdb3d64e26052d2  gcc/testsuite/gcc.target/loongarch/cmodel-pragma-attr-1.c
  6c4891b18c6bd1154b7ea8237dc05a30  gcc/testsuite/gcc.target/loongarch/cmov_ii.c
! 8372ae2166ed011a23a10b6a6415bc98  gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
! e47b1f0d85db9f65f76cc6e828f1d7a3  gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
  d714312bcf2901d8e4e91206a319c6bb  gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c
  c794f526430241ad83fd3ca5415524f0  gcc/testsuite/gcc.target/loongarch/crc-sext.c
  2ea39544bfe26567ec668ca7a33a8a5e  gcc/testsuite/gcc.target/loongarch/direct-extern-1.c
--- 90712,90721 ----
  d984aef61afc8f09af4c880507f6c6e6  gcc/testsuite/gcc.target/loongarch/cmodel-func-attr-1.c
  50ab91c6f8ea866c2cdb3d64e26052d2  gcc/testsuite/gcc.target/loongarch/cmodel-pragma-attr-1.c
  6c4891b18c6bd1154b7ea8237dc05a30  gcc/testsuite/gcc.target/loongarch/cmov_ii.c
! 9efb1cedf311f58b73a175fae939dc78  gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c
! 1faf96722faacc0ff389b62bf83b34ea  gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
! 9f48ac8201f97bdbd1ec5edcd8f2984e  gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
! 5f9e7145f8a500557b5629f8d93ad860  gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c
  d714312bcf2901d8e4e91206a319c6bb  gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c
  c794f526430241ad83fd3ca5415524f0  gcc/testsuite/gcc.target/loongarch/crc-sext.c
  2ea39544bfe26567ec668ca7a33a8a5e  gcc/testsuite/gcc.target/loongarch/direct-extern-1.c
*************** c9d08bb72896d9b4861ce4073ec5e57f  gcc/te
*** 90716,90721 ****
--- 90752,90758 ----
  f72ce6aeb8beb0eff27354c07ef71cd1  gcc/testsuite/gcc.target/loongarch/flt-abi-isa-3.c
  ab6db876a44193a92b0a1625c65eb4e7  gcc/testsuite/gcc.target/loongarch/flt-abi-isa-4.c
  aaaf53a882a8a0ae0583d851021e03cc  gcc/testsuite/gcc.target/loongarch/fmax-fmin.c
+ ba1f9cd7776de398eabc15fb6f7d523b  gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c
  fee1bedd25e7db9b4e91f3ede9e05608  gcc/testsuite/gcc.target/loongarch/frint.c
  2f79a7482d38a9632f39b484c09a8f2f  gcc/testsuite/gcc.target/loongarch/fscaleb.c
  40d69683116e216d2295e4600c830736  gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c
*************** acf1fac916847c2064b8d2bbb6535828  gcc/te
*** 90806,90811 ****
--- 90843,90849 ----
  754f11f1533603a4d550b593afc0c673  gcc/testsuite/gcc.target/loongarch/pr121634.c
  d1eee63ffd26f53d2b788cb0eb55f5a6  gcc/testsuite/gcc.target/loongarch/pr121875.c
  1dd25b33f6fd8d4c4dc750865d86f404  gcc/testsuite/gcc.target/loongarch/pr121906.c
+ 4fb67de6ceaa4d3d0dfff318541b470b  gcc/testsuite/gcc.target/loongarch/pr122097.c
  1eac553341d725c6e59615b593aedb0d  gcc/testsuite/gcc.target/loongarch/pragma-push-pop.c
  3adba2a8ae6f671eb22ec8228777c1ac  gcc/testsuite/gcc.target/loongarch/prolog-opt.c
  1bfa30f99dc5f04f569fbff68640ab19  gcc/testsuite/gcc.target/loongarch/recip-divf.c
*************** f46bb4d68c80f94cd959f7aefc8389e4  gcc/te
*** 90831,90836 ****
--- 90869,90875 ----
  294f8a20e4eec5c0c40de71226677399  gcc/testsuite/gcc.target/loongarch/sign-extend-1.c
  ff53d68fc0f97e1b389fbdfc6b733d9e  gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
  503978ebbda9df9f9d2896d9898ab7b0  gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
+ 6f84ea4a3d11d3be47a589d544ec42f5  gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c
  969f8c63d5313b0ef2802d00df27886a  gcc/testsuite/gcc.target/loongarch/slt-sign-extend.c
  bf64f97d74ef11f20bfde63932d56667  gcc/testsuite/gcc.target/loongarch/smuldi3_highpart.c
  e1615ec0889043a33798fc33df9c0c5e  gcc/testsuite/gcc.target/loongarch/smulsi3_highpart.c
*************** d3511a1f030e8253dbf6b20c73d33105  gcc/te
*** 90864,90869 ****
--- 90903,90910 ----
  59f8afcb4e93c86d7da2ab3c90529db3  gcc/testsuite/gcc.target/loongarch/tls-ie-norelax.c
  2a0b997731ed1ae360413e97d22d1e5c  gcc/testsuite/gcc.target/loongarch/tls-ie-relax.c
  273aefb7dcb812b056ec4f65efdd49ff  gcc/testsuite/gcc.target/loongarch/tls-le-relax.c
+ 5476461186e33f60cdf514b4363e881a  gcc/testsuite/gcc.target/loongarch/trap-1.c
+ 75db51c40cf15cf674f98cd2664252bd  gcc/testsuite/gcc.target/loongarch/trap-default.c
  bb57d24452eb2fea309f990edfa5de1c  gcc/testsuite/gcc.target/loongarch/umulsi3_highpart.c
  20592e6b1e8a0f3b8742b7beb0f51ae2  gcc/testsuite/gcc.target/loongarch/va_arg.c
  bbbc51cc2b6669a160c181fc1ab12412  gcc/testsuite/gcc.target/loongarch/vec_pack_unpack_128.c
*************** c08e307370de6dd5122f517ca9b88bd3  gcc/te
*** 91323,91328 ****
--- 91364,91371 ----
  6ec0b39b5b4b1a97f39db6ffa8466e62  gcc/testsuite/gcc.target/loongarch/vrepli.c
  a005b26aa548eee07a39a18e458d0abc  gcc/testsuite/gcc.target/loongarch/wide-mul-reduc-1.c
  c1d9bd83ec7fb2ffe482949572f2b0d3  gcc/testsuite/gcc.target/loongarch/wide-mul-reduc-2.c
+ 435ecc6bf3bdf44b71d9d56c8d3fc036  gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c
+ 85b7855a23d37a98585aa5df332a0722  gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c
  10ce9c8f9619651c9d46b51e45ae26da  gcc/testsuite/gcc.target/loongarch/xorsign-run.c
  9b099d473b8bfb835da7cb656ac3e3f3  gcc/testsuite/gcc.target/loongarch/xorsign.c
  390ebfd9588a71fef795823e622f6c10  gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c
*************** a21d4b9178b49fb0fb65552af24e2832  gcc/te
*** 96263,96269 ****
  5eae803c1b040dbbb059ce96fc1b5474  gcc/testsuite/gcc.target/riscv/pr120333.c
  4f37f1ab5c897b7d856cd69b7a0d1b97  gcc/testsuite/gcc.target/riscv/pr120368.c
  2c1cc888103a7f151db04550ea30ea67  gcc/testsuite/gcc.target/riscv/pr120553-1.c
! 0ff65635e9e0b44b38fbc73432466a4d  gcc/testsuite/gcc.target/riscv/pr120553-2.c
  3e9602da76e5cd67c12dd17c3d623ac4  gcc/testsuite/gcc.target/riscv/pr120553-3.c
  913f1e0524de5446a17d2300da55b54e  gcc/testsuite/gcc.target/riscv/pr120553-4.c
  b2e2688bf4539077ba541a5c6d72fc5d  gcc/testsuite/gcc.target/riscv/pr120553-5.c
--- 96306,96312 ----
  5eae803c1b040dbbb059ce96fc1b5474  gcc/testsuite/gcc.target/riscv/pr120333.c
  4f37f1ab5c897b7d856cd69b7a0d1b97  gcc/testsuite/gcc.target/riscv/pr120368.c
  2c1cc888103a7f151db04550ea30ea67  gcc/testsuite/gcc.target/riscv/pr120553-1.c
! 75188b477b9af85016e8bd0515f31112  gcc/testsuite/gcc.target/riscv/pr120553-2.c
  3e9602da76e5cd67c12dd17c3d623ac4  gcc/testsuite/gcc.target/riscv/pr120553-3.c
  913f1e0524de5446a17d2300da55b54e  gcc/testsuite/gcc.target/riscv/pr120553-4.c
  b2e2688bf4539077ba541a5c6d72fc5d  gcc/testsuite/gcc.target/riscv/pr120553-5.c
*************** bc59de83765bb844925a1922677b3910  gcc/te
*** 96289,96294 ****
--- 96332,96339 ----
  cddeabddc47c1e2e434be321884dbb80  gcc/testsuite/gcc.target/riscv/pr122147.c
  37a08389ba95284cc27832767dfc1430  gcc/testsuite/gcc.target/riscv/pr43644.c
  db206807e7e87fc388e039471812c6e0  gcc/testsuite/gcc.target/riscv/pr58727.c
+ ae7832d0dbfbabb51f555f2e9c3138bc  gcc/testsuite/gcc.target/riscv/pr64345.c
+ 9a44cd39f0fe595fcf632b001e4b7d12  gcc/testsuite/gcc.target/riscv/pr67731.c
  10400130cc47973d43925669f3c795ed  gcc/testsuite/gcc.target/riscv/pr84660.c
  c2ac0b53d6af56f5ec5bded3d252dddc  gcc/testsuite/gcc.target/riscv/pr93202.c
  01c8227bf1b5efa52e434a407c33930d  gcc/testsuite/gcc.target/riscv/pr93304.c
*************** cbc44c5c7fa77e3f0d3efc55779bba4b  gcc/te
*** 97139,97144 ****
--- 97184,97191 ----
  ca9ef4de6ed36716b972a6b4efc63e85  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121845.c
  357366e34138686786040d7711285496  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121910.c
  505e3d028e24b575ded98597fbccdbfd  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122124.c
+ e990c042b373d09f16b69f4b30f0ac20  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c
+ a46c21828339f41cac3054a662eefb70  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c
  ee8bcba5f6876f2027f0f263f81465aa  gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
  7ff884bfa2e6cf9bc4c6172466538515  gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
  b2792e9264dcd6fa2e88f495d51677e6  gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
*************** eaed30eccbeb952165411cfd2c789b72  gcc/te
*** 99716,99721 ****
--- 99763,99769 ----
  b8ddadeddd15bd6f079e943b9036825d  gcc/testsuite/gcc.target/riscv/rvv/base/pr119115.c
  abe5cb852d5c8b368720c2010f7dde5c  gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c
  3086321c9a12d3eecd8f1f9ad8ecac7a  gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c
+ 250f19182eb5aac9b6a01d7c594e8f5f  gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c
  c05efbdfaafc64ad34b3d1c4b60a38eb  gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c
  be75fd39ea9b3d01e3e22294359fb482  gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
  20a3b581af8087da2c1170d56ff52971  gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
*************** c408b1a7f84e4b815e85476963221ae9  gcc/te
*** 99950,99955 ****
--- 99998,100409 ----
  2865ee85ce614d77ff279bf2235dfe51  gcc/testsuite/gcc.target/riscv/rvv/pr120297.c
  999cc44bdd25aaa38b1dfd62ba9b84ab  gcc/testsuite/gcc.target/riscv/rvv/pr121073.c
  f91a64dedf252b9913f60c269855a824  gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+ 5478c0c8327ff5286acd21adf7801a3b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c
+ 7474e3b118ab01afd89adaf5d29c7e26  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c
+ b0ad6114de72318c274762ca3a6f767b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c
+ 7e9ec5a2da14b05732bed143b69a4636  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c
+ 541280295666f9512b838b5429929d57  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c
+ 9bbd1b78c5bc17ebfa5368400a8cb1fe  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c
+ 111e782212bd1809a62e53ef4d33241c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c
+ 25846eff84bc60cc7d9abaf90f698ff7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c
+ 4bbd167dc1bb6e4cd750ab4f6e7ee570  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c
+ 199e86a48014de090ea51ff1ce92c8c9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c
+ 2856676d7bbcd9727a6fad3c81058624  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c
+ eea8dcc6cd95613a7149e59355fc6be3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c
+ 7ea344e10546d70a7e92bee8154f8cfb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c
+ e69214563f73f872edddb111942f7a87  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c
+ 1fa31682fcf5131814898601fa016e92  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c
+ 83c686cb872627ce8f57fbb67d872e07  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c
+ 77885e9e0d91dc965807e324298090ed  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c
+ 1fda6b4f65108534c1e9967bdb424796  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c
+ a9b2ee4d55bfd0e36f27b22300a04772  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c
+ bb7964e2a98216faf703785c33a2c407  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c
+ da8d24a47ca04e39b9ed568225610595  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c
+ eb9f985161bb6da6319c4bfce811f0f3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c
+ 099be1ff9a28a22972d161568460fe98  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c
+ f2b6de3df030ac9343a4ed7ddda87479  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c
+ 33bd7da38fbed940e43967a370b27811  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c
+ 7a8c1b58ae81dbf36340edd57a03471b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c
+ 66eb7c5fd79659f92a8a8e5db5e29902  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c
+ 8f151310bbc16d1573f70c26ad4d4a46  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c
+ 783b26083641ff6496ce98e60f03f08d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c
+ b8dea25f4236c2922f58dc8082facc56  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c
+ 9a028907f0eb3163150e67d4a3675dfe  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c
+ 6d53dd6cf305b4b2b8bc038fc15aec95  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c
+ 65d2d9d9a211b7999cbd8244741828a8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c
+ 47becaf99e673537762df1f73c70c567  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c
+ 596eccf89f42254e375eb50be7964290  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c
+ d4d6b876af2e231e1f0c1e22154a8ca9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c
+ 47b21f14bf3a8b9fa3b8fed8d03c7d70  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c
+ 1bf0fd99a1a8e9062e0180f4f399e248  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c
+ a0e2f67770887e1cb422cae18d2d6366  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c
+ a6a30eb0151d447199548825773d0d12  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c
+ c6045ca74e49e0636fb2ba108f844004  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c
+ adefbf6dc9a60f069a3bb3b3a9616781  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c
+ d04fe8b2547b6cf9886549294ffc1374  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c
+ 0dccdcfb59e601d20f10c86cdfc8596f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c
+ 627b2ddd443e1e91415d484572d0e1eb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c
+ ec18864d2e4460cdd11a1b5ea0a44ebd  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c
+ b4327304a7a74765a44a9e9b0ad48860  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c
+ 8ce84ed7eebc8439889601d932e592f9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c
+ 07f5c17d5f2e6eea2ae3710cfb14306d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c
+ 48a43a296eeec308eb7e7a85c656dbf7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c
+ fd41639aaac4827d5af2fed7c17270ee  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c
+ 37cb2186b8d9d7bb38713847d095fcd4  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c
+ 0be369635887cb5a854ad14c48b57b5f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c
+ abaf8065dd10773d34a0f2dfd0927607  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c
+ 6254c818e5edb9c153885cfe74a05000  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c
+ f408732f0e4ae7aea06a483eff3b1843  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c
+ e2d90315d0c5a4c40c1dbea8d7b4eaed  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c
+ c7fd642cb7cfd6664494ec865baa7540  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c
+ 59e23eb3308e403418980784117bcf6d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c
+ 809ae81cafe0c31958d16ebe9c7eac86  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c
+ 818aeb910160b056d87f57ab13d41bc4  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c
+ 3b7a8fec1a2208ba9a323716bcecb055  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c
+ bd951dea40fcee8c28567885ccdef761  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c
+ 54f425c26233eb013dd52b94519360c2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c
+ 416d5ad48de5c38ba7b507576d827d07  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c
+ 1f5cb9b19a95a7f6914f3c3d99f78388  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c
+ 65343a798ae5e6e72fd99c2dbc499509  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c
+ 1b5c4d50ff203108316f630e226378ab  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c
+ 84983a1edc79caebf9155dc7e83e5ea0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c
+ 0634550fb8b0cdfaf456b2699efa69bb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c
+ 4fc1271d4ada5ad825d0e62a63e889b0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c
+ 4cbe5fdca552432bc57f0773defeadb7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c
+ ddab59d25be90d1ebb0aa5d48bdf6690  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c
+ e88f6e059543afe309c06e8187f4f299  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c
+ 7b9e907ced4ee6b53d3d58b96ab9a9ee  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c
+ 77b6ad45d3ffd814d8c3f53f669e0761  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c
+ 15f9591f2b8584319117a25b337d369e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c
+ d0a8e683ec42bedeb8773ebec06be9bd  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c
+ 4ea0edfdae33f5653f12e94d43d8d3d2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c
+ 2060bc46d6ca8fd7f59d3709e619f736  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c
+ 1520b1e29dc78f334965a311776a8941  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c
+ f19fe9f535f23183fa6db7fd9da32768  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c
+ f8f39612baad29b5cf52a1611a37aa7c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c
+ c652628c9089e05a92d4c5688c49248d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c
+ 78d9919db6c060869b88b28e25595b8d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c
+ d3fde8ed08793d9488d22e7fe6e34e9a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c
+ ef46a95e41d9a5c745a820ab6dd52230  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c
+ 10874283f0ff7b13b63f86e29d41bbbb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c
+ e718b95149f48a32b8aceeede0784287  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c
+ 26d01e6b8ba69168a6c8ebde80bd7fa1  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c
+ 6bd493256a1d6313be15ba82fe398ad6  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c
+ 93272df38a396eaf42a4d94074485e2d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c
+ 9084727f789a73a3e961531e314ae587  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c
+ 3677bcf88a9a58a8ac983d84f96752ee  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c
+ 7a6a595af8e381e03983e5a5c5295e9a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c
+ ac570668c8ed60b421e3902a82e88a73  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c
+ ef1249c6731568c324cabd1f5829b1a6  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c
+ fa46d30ad339710e506ee85b1dab5305  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c
+ 1b81826deacd466c3fb6caedc18402b9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c
+ 2242bc485c22465b6dfc3e0c4f430cdb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c
+ 42bb0b1243fe31f7cf348ce1ff0d5c61  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c
+ 7093b7b40e0e93f305cbdedf8b52c515  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c
+ 344a78e1341594ed8f64a0e5dfe7cd9f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c
+ daeeca91ac739e078e30de0ee86bd188  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c
+ 7985ef368e6abf61be2cb85274fa4e45  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c
+ 7fce8b38b5846487db7666095d6e2a68  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c
+ 0acb224c78253bbd3d00c894e0f3c5ef  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c
+ 896bc78be86065361f6241d2df6647b2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c
+ a4d51739d08ea60ccbfe31f8b1330e52  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c
+ b84086a8b194b3a8dcd6816419eeee4d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c
+ de16213d5a10b3afbad6d5ac8c34351d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c
+ a041118041a60d8037011b86d7a5b3fc  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c
+ 229c4aa231cc5388a1160b34196cec50  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c
+ b6281d639c0adcff8b60f0bfa5185e24  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c
+ 997d8a40972f095c91dbac89e70ed2f9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c
+ d0fd6507f01ba7b7dff9ac3979de9b65  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c
+ 2707002c9fcef336ee66c89c56d44118  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c
+ a3ca50dd9e75b6bc7f44a6bb0f163f65  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c
+ fdeddfc66cb9f43fa892f8f4555fcab2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c
+ c11f4e6a9ce52313a44b2732560dde1f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c
+ 443644fc2bd182597e1c18651ada81db  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c
+ 84c256a4e8ad0ff8cfe515dc75f15341  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c
+ 47c616d0853b7f3ad27b4ce9f54e42bc  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c
+ a0dba3ba0a12011fb6d8ccaad6bf2135  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c
+ 71e0c271a83ffdec1ba0b13dcafc4d5d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c
+ 8942f7e3305cfe844ffc1702af2894e8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c
+ 751c8b56e162b0b758f256b86c881563  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c
+ 71208f8e8413566278754904f0d85fb1  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c
+ 44ee30472317cde3c0c1fc80366b2001  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c
+ d7b29a926a69c04512ca3c27d6dccd76  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c
+ 8dd85abf66185999b1b6bb1930f55c40  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c
+ 1010bf6711a692d069c59bc7ca80cbbb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c
+ 13356a84b79e14cac940637408b97890  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c
+ 150390c372aeefdbc869e36dbc7555f2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c
+ c5b0ef6f51bb61ef0f62f9bebd2f314b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c
+ c93c414875e55eb0db2d4ad59c3b999f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c
+ a8d6c9e225d5f2a2fa3dbb4722470adf  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c
+ a115ec6594dc7a43f9c6250046dc3ed8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c
+ 9e4586058adea224b0a77ee907410568  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c
+ 5bbe3aa9a3c41213cd48a9cb4a7f3344  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c
+ 9a43f3dc57bf0a86bbbbcf81f503f9d0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c
+ d3fd2f41ce73eb8feed771014676129b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c
+ b23f5634327ef3a894ef7c5f8d75e24b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c
+ f8903861ea9c0e7de2de9a06eba843f4  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c
+ bfe54cd7e0107f6987537e8e86a46592  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c
+ 9084105adcf73961c996443c86fdfc70  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c
+ 02a18860e3eb8d9063d646f019f1b4d1  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c
+ ba1a6f162fa39933a5bc0935ee036b30  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c
+ 991cb3f24be457585740c0fb28139549  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c
+ 319f39656b0ca2cf7a21b7e56e161c2d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c
+ e2ed861e647f20ae271d6abcefe9b91a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c
+ 19c1e5342f3aae6c2a565a5f4b5e5972  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c
+ 2ef68ac8c7c4d26340dc5f4eb6c06809  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c
+ 31d177972854d088c8ef960ac32dc33d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c
+ d73d295a48bdf91f690ef7653b50f0c7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c
+ 480b6d636b8e8e453acf228a2d08260b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c
+ 6b72344bc649dc28b6b478dce6604b9e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c
+ ee6686c31f69219339047aa0f2e91126  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c
+ 9e0d212ff69b9e7fac63fe5396089d68  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c
+ 8787699fbf7b117d50c49912cfcd0ffa  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c
+ 26287ceaa63e757fc2970f6ca1ff9f03  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c
+ f4b8818006c31ffc16e9d491bba221a7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c
+ 9cb749e5315470bf336f4f659b31b3ed  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c
+ b8e01c97c002d4b6b5e824b84f4afa4e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c
+ 0367497c4c05d9f4f0967a521d922c5d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c
+ d876422c760e5fcdb8b610be9139d432  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c
+ a454a936f65bc4ecb0d7e26b309a5fdf  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c
+ 9f8a27f6000d7343d72e4bbb9a6fb3b7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c
+ 60aca0e3919bb1aae2dcc52a8a85ae06  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c
+ f2e912594ef3d8dec057ef5382b14e10  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c
+ 23df487dddd50064c386633347f0de0d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c
+ 21185351ac79d313e5de413a1be78650  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c
+ 1c72ecc806cf26938b38df93a3d44f32  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c
+ 7534b57d26fa04915d51b68206c9d06f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c
+ 7b32ec03ff9cf0e8261320e6d3e24131  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c
+ 395a903107ec50dabaab5d4a7f32838f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c
+ aa146beb84d752a712a9f69fcf249be9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c
+ 1c93bcb1a75e25c4d08e36023b2dd884  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c
+ e0ff040ee680578dff61ac9d87e251aa  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c
+ b5cc948a96e4d871e2e3eb9e88651f9b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c
+ d8e004119505c74ccbfc4c7c14ff6da6  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c
+ 5413786ac3b69a81c81c9769edb38252  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c
+ 761118abbba98f468a0c15af5ff5558d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c
+ 10cfa383635f0d75d23db35c749bedc3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c
+ ffa92eecab70649d3dfed2e2768114e8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c
+ 3ba29520b644f22530324f5358f630c7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c
+ 2ba79304b2bd769448ca16f49410a0d1  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c
+ b2c76d5f0ab3e1c02d22aecff8791912  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c
+ b247106aae9e036a08307f075d0fddc4  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c
+ 37a7dfe115c3a8b94fb55020a5767e13  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c
+ f058e6f73dbdbbc9564da8902393a9bd  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c
+ ece40446a8bef38a699405c1683f09b8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c
+ 25b0ecb12745de9ba9bd936b274faa37  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c
+ 1e5d20c3670e83cc5592eafd6a9b94c2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c
+ d235d51899e1fbbfc2a4dbc8790c40d9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c
+ f476125d3930c36133126992c9ff73b0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c
+ fb52bab0938bafa2950e22796390a4fb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c
+ 8b2bc2d9c80f9adcd6c3d0c566c05f75  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c
+ d18c1a53fe15ac71792a13726bc735c3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c
+ a2d98b8283d338278cbc72fd181acdb7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c
+ 292e121b303b45870f65529dfd237f37  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c
+ f7364a9171a43d999c7fa288a22ee318  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c
+ f5e6e2334f6f182e5961b504cede0450  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c
+ 9cb3750d1fc5047526f076b58558dcea  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c
+ f8ee80fb71bbebd9f15be868c04d6eb8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c
+ cc698b17af087aee5aded163f7b79880  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c
+ 5a2140c0703733928241abaebde47a46  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c
+ d717fc6c6f42e3a7fcff69954e18ca6b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c
+ 9ff45755f176aa941d4fbebe9906f026  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c
+ 246399ad229b389d4c012d1cdf773044  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c
+ 649b02beaf3fdd78461b5a36dcdee023  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c
+ bb98f3fe5537d38f7c87238a33cd251a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c
+ 88668f1975cb4f9f7bee3ba57576eb14  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c
+ de5d6d8e9bb01de1eacb5a165cb8969a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c
+ 13d0a41323903e904794bb94b3f253a6  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c
+ d806c72e96a4228449a6ae818f05b86c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c
+ 95c4e99c83e5ab2e7ef6777906509cd5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c
+ ccb813d38776db172d95d6eab10f3850  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c
+ da6166d588a37eb5bccc2a221e4abe6f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c
+ 691b36c127f21b687367743997f278e8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c
+ 17c3bb6e100cd67df1d4a8a494b12c92  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c
+ ac77da88e3a3997fde1bbb2abdb20a15  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c
+ 10e262e3ae142ad405d32644cdba485c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c
+ 8396546d79e73b31b2527ab7b6813c4a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c
+ f010901b9fe1e76e395711d59cba147a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c
+ eb12870aaad47704b9d260697093c016  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c
+ 74a2dfa7411d52edc869a0e0cf07d0df  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c
+ a1629f026b733fa8be4c4b1290b0c262  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c
+ a53de99e2cc81596b41a76b5c064d6cf  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c
+ bc79def279f7ef923ede770cc0fe697c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c
+ fac96865b4a41a4c2a2333d5adf1f419  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c
+ dcbff4d42a3f0a72e5f4088b8668502b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c
+ f50c783e26a6395f1aec036fef1d27a8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c
+ 9370f23b0335bbb9451a6900eeb895de  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c
+ 81f6ded68b513ee7f8ae827d949c8890  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c
+ 3a5c3c191580d114397a1bd0b89d2fd2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c
+ 0827de3c9526aeb805be4bbc4f2e41a0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c
+ acd75cd1a44871e28d95628f6a39d403  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c
+ e03c4f74010e1c7e374c98918e2ab5fd  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c
+ a9ec49dc33ef1733a23e95d96ef1a353  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c
+ 6a2847516f96298f96dec7697d934cad  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c
+ 4ed40351b0e80583790abef14e497f67  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c
+ ebf34ee2645133fa307d9a4004906406  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c
+ d4a5a13e18cb22cdca5b6eb55aede2e2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c
+ b67cf45afdabab83adc227d7fffebf86  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c
+ 73b622c678fc22959009d0c8eb68e205  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c
+ adf6fd5380cf2530302ba6cac6567a0c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c
+ ec9c9307c79e5792ed7113895e503f7a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c
+ 55da6e7a27569f3de68a172c68954894  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c
+ de6f0ace8c3f190c29db008b50d4e142  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c
+ 4289b19a27224a0e437bf7d15b35995d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c
+ 095240967b579da4786e8c0a33063ab4  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c
+ 0d340f1c093ef42d2b28067a763ccf97  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c
+ 97b9b86cf7e270dce2b0b13cbb4e12d5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c
+ beaec68c53a8618de2821a8810d8b9f9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c
+ dd084a1629886928215b965255fe0561  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c
+ d3776e4dc6376a6cdfe9d0cc3077d4dc  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c
+ ff1f02d74ca026521c4b186ee3b83eb0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c
+ ad7bd94d790e7335e00038edcf066924  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c
+ 68cf9b3520c9f2717aba3bdc61d8e5f0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c
+ ec85a1f6534eaf31a58e0ead0451cb2b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c
+ 891881a9988ee91e9fbd6252c96d98fa  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c
+ c3510c6f0bc2e77be726748f6a6bdbe2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c
+ e6768ae7465645857ff7e34cafe1c0cd  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c
+ 3c2e86950fe1025ef3ece06647812644  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c
+ 57bd2f84f888ddcfd4e3a5e5cf854123  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c
+ 3c96f1daff3def648c038132b8941023  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c
+ afbd6ba1af4efb98a005e8db12c61b1b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c
+ d34e250a76d9c134a54c9c5b5e8d664b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c
+ eb5cdf915631647224f512b8bf3cc7a2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c
+ 6151296f5a89a9e7e7e71bbebcfb8603  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c
+ 514e25e516eef8c7406c4f1589cd82d5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c
+ debe7267397c9941004465520157bc0f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c
+ c5510eb613a7146747a5a0b03a8944d4  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c
+ 90f9ceb24203c17df50cdcf8bb840831  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c
+ 9f4613042c0880e9e644ccf635b47c89  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c
+ 35061b1c10ae5f2c9b62449d3db40678  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c
+ b458d634b9dd14b27c9e9543613d66cb  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c
+ fc47fc8484ff0c15446219f72c9f634f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c
+ 8e4ee359599a39599ddde3d9b7573d36  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c
+ 5868f3edbe0b0a827601cc0650fb9d61  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c
+ 9d237c3f24c4c9b4d96574a0bdc0553d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c
+ 2bbdfa16c7c25ffb189302c558e164a0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c
+ 7f21f8d5e3214b210e99bdd0611a4000  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c
+ 8a9579308e2170ae63e9032072597c70  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c
+ 17f4927b7bbfe807823f385910dd6485  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c
+ e22293ebf92d9385df5d709978dc08e8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c
+ 2e52dc8e187e8d57a5d3866718c724d5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c
+ d8764d117f573b2007c3ee92ebec110a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c
+ c7d56d9deb9fe42fe9c8f2126a36db46  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c
+ dacf0acc912592f12a461b41bc816e7b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c
+ 99fa94c83ca155a20d153944c784c55a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c
+ 1e058b0eb6c830e6c4c60080c29ed8e2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c
+ fa465a969b320d011481d62ea8f53fab  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c
+ 051148c84212c613a33f4c4c7d02faec  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c
+ 0c3b71f3d1b0b9d2f8605b87c9966048  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c
+ 35b579407c644b69c305796fa53ca9f0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c
+ c3e8b7916892b587d3c726bf7d863267  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c
+ 30a3505485b9284278f22d65b277ab7f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c
+ 963fa836aa9729e8d96fb41c6453d17b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c
+ d1915b28ac6b6534925b78fd1b6d18ab  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c
+ b890cb69087663db1c067337754a3d87  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c
+ 68e4444f45ced776fd9477f669f5b101  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c
+ 80f56c495d002af09f999e0ef4f49a6a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c
+ 179b70b663d6e0e84efacc8774d91ea2  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c
+ 303924ab9fc538815b0e75f0048d56bd  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c
+ ae98a20038487912e18f63c37c3ec696  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c
+ 53fcad501d43c55190b4395e5eb09d75  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c
+ 21e4d2b488eecdddff6b3f77e97f3530  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c
+ b007589f27ea9e605fd0ea0d6b70889f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c
+ d34938e84e77ec59dd11a608d06f10cf  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c
+ e18de44a0ece195d5ef13e634c542f62  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c
+ 5bc2a60a5dcad949696b09d92117656c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c
+ 3f6eafa977d32e8af37d82e5d571a25b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c
+ 8525ec35caf0bfb936d7fb14187acbbf  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c
+ 53ce2647107bc53d21e5502b219b778b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c
+ 4b591ade492c3c631268029e3883cc80  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c
+ cf55c2c50331b6e49e6b06652d181976  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c
+ b7562d7e4eed9ea4a2552681b5137779  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c
+ d58aaa6a0189033176d8a6c6f5d75a98  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c
+ c6e2da72b7e9ed5cee2fe596930167e8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c
+ 68c8ef9bfd19b97b515c2c491bd27b67  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c
+ 0d4ec39e3b5213b56f2382f5aa1f263f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c
+ 5d24492538fdc27cbe6eed3003d48bab  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c
+ 9de907100438fa1810f2b81d71bc8bca  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c
+ 553354ead23403d45bf816d430a71626  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c
+ ee5ac7177abda4beb3227b6b7564d9e5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c
+ a9a40888bde22006e250ca3432cbdc2a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c
+ 6611710ecaa152a328bb7c7d12d284c0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c
+ d3004ff3c7631ca97a641fd797f7b52c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c
+ 79754fcdce221a60e8f057025e3c4581  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c
+ 2f3b91d71540fed84dd05f80fa22be5b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c
+ 60a9352f87c5b790abc48b708155f821  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c
+ 5c3763fb8ed83868d76d4c623fd89722  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c
+ 4582f4b359cee4dad59ea6d2dae8bc71  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c
+ cb01be42eeaaf283e4329b2d21fcfba5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c
+ 8ede2ab9960efd273d79089d9e16295c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c
+ 949a6ba463f5cf12278b57de00a9dcac  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c
+ d4d75e05ca6dc318eb75564c6958fd64  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c
+ 0e76d35c4995022cb3e5db8f2cb9afac  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c
+ cb3bd5e4750aee6a4796ee3818ce6bd7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c
+ 0f4542de3fe96c14caa1aa3c254df8d5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c
+ 22d0ae1aa2ff768d35556e19b8bdc062  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c
+ 46677cde5dc8136e93715cf18a4f28a8  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c
+ 1a5ee2408ce0e87d9e109e35e84a9c01  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c
+ a20acdd97ce2c14085a8a6767c950a46  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c
+ 08737380ccb1040495a160646b346ad3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c
+ 419b5f42f5d77f4e39bfdecfa0d46dfe  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c
+ 15ff891829c7121aa72bf918f8598f70  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c
+ 359ed536886a2b5e3a1e391d2c369811  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c
+ 007d9e28366999cae732b359c90e3d7e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c
+ a1ae98a7d514fb6e30340ec8769a357e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c
+ d07fe86874b1d9bd0048f1fbedb913e5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c
+ 4f2c869c1f0dc770e0fe47d1171f0a8f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c
+ 1094d7b8738bfa6c825b37169976d46a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c
+ 3f5e3f4718de5829e0d52b16a611eda6  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c
+ 0d0b0d4f3ebe509c648fed717ae211e7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c
+ c2c5e89456dd564f3a00ba20023b40b7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c
+ 4de3d2172579e0127679cb90b45c8f1e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c
+ 936e05629aee5cd6323901085bd93b39  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c
+ 888eefbb3f466a6f9e2ec718072ac134  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h
+ ef86b52fd0021f0c611c83edaaf5da87  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h
+ bb5d374bfcb55006598021195003d105  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h
+ 7148437864df54cd475428fe6e5fe517  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h
+ 60dea62695f65d6fa89e0ecfc4957852  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h
+ ba57f7b3a122cea807a5c39d7c5dd92c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h
+ b10cabfeb6be9972792e3bc144ae9cee  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h
+ 2b46959eacdeae05b518f5d576979140  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h
+ e2c8bb738d6681ed56b1e7c5149fbe43  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h
+ e4bb04b20b2b2f33c86aea9c3ee45a54  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h
+ c4de682e008ed0d4baaf1999858b102f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h
+ ddada2e696b01e83da17f2aff85c3784  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h
+ 034ce9afd2801416b0b61b986c183791  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h
+ 88f5e39e9864e52f54c0cf8d2c7810e1  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h
+ 0548228b6d4a204970384b0e318c6c6f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h
+ a47c8ecb6a351515689bd561e6b6d958  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h
+ 8c11151e441fd8e932e1f753a1583059  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h
+ be600053d4023bf2ea6049f0e15ca32a  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h
+ a5774eaded1c81534e29062e41366acf  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h
+ d3cbd8bb35f3f3032225dfaa816f97ca  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h
+ 105a948991bfc207068415b3a911c4a3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h
+ 0ec6b908f9ac05720639c851c53674c0  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h
+ 3aa00f3f5058c1b806cfade4dd63a688  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h
+ eadbe3d8b7aad01ca532a33526867ee7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h
+ 089ac3062c46bbfd6b79730c75516750  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h
+ aaa919c949e76bcccd13991bfdeb4ab9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h
+ ff60449d539a15dd1e48c498c1af2a4b  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h
+ 81cf60dc03fb065fb9a2e7c672845bcc  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h
+ c7a93a4f50f1171508a6761decdcd4b7  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h
+ 729af74038871a86786ea3f2aec739e9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h
+ 4a1fe605f3b33083563e2bc9e31d8bed  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h
+ af9424f2e0fb816623eabd06ff445cd6  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h
+ 2165e1835b83027b7d20157723d8cdbe  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h
+ 4e6ad7e1eb54bfb1831df3a873bb834e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h
+ 6edebadc51d685154461e38fea7093d3  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h
+ 586dd7b5fbb7ee4cd0443e5f5a8b4e27  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h
+ 6afb648ed1487a1daf3c402f6054f0d9  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp
+ d765ff8ee76981e10c3f6bfc4185f76e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c
+ a2af258497515d741c81bc5f2338252e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c
+ ebd99929633e4a76ea1875a335c40e91  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c
+ 51e999e239970ac411ce6178eb143b11  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c
+ 002bd0fd1761be63f378b742e9acd7f5  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c
+ 7b1db05fa45d187c3e13b96dfa8ea53e  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c
+ f9e4db696e4e65f444ae6c79d8c5555c  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c
+ 6935161a755ae18bcbc98e96bb08ab3d  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c
+ c8b42d8f89f7472e8d75ba5bfb15156f  gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h
  3031ac06b49f9e9c72d0902a20286c30  gcc/testsuite/gcc.target/riscv/rvv/vls-type-rvv-max-lmul-autovec.c
  4aa5bc6baedf8ea5084481a3ed9f82f4  gcc/testsuite/gcc.target/riscv/rvv/vls-type-rvv-max-lmul.c
  ecf4c4ab418350831d4471534a47d02a  gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c
*************** ee390913829a46a6ce5004198d82bb62  gcc/te
*** 101449,101456 ****
  1e372c3919a67ae0d4e075b9c20347e5  gcc/testsuite/gcc.target/riscv/zba-slliuw.c
  7897a2dc924c5d59e2471445e59414f7  gcc/testsuite/gcc.target/riscv/zba-zextw.c
  6c5397671f66bec010860dfbc4625631  gcc/testsuite/gcc.target/riscv/zba_zbs_and-1.c
! e5b7fbdf358cbf214660b7e3b239e748  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c
! e9490e711fc56b6a96c339184a7a19a5  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c
  1631a0846b45d351dfd85d51d24d1e0a  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
  5dbae90a34a2a69760f83a81cd1339e7  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
  631834ee0d029b2cdbfa2459fe9543fc  gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
--- 101903,101910 ----
  1e372c3919a67ae0d4e075b9c20347e5  gcc/testsuite/gcc.target/riscv/zba-slliuw.c
  7897a2dc924c5d59e2471445e59414f7  gcc/testsuite/gcc.target/riscv/zba-zextw.c
  6c5397671f66bec010860dfbc4625631  gcc/testsuite/gcc.target/riscv/zba_zbs_and-1.c
! a051ed98697d928f921972ad228d616d  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c
! cc1048ad15d6f0a5bad76a5c0525c334  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c
  1631a0846b45d351dfd85d51d24d1e0a  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
  5dbae90a34a2a69760f83a81cd1339e7  gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
  631834ee0d029b2cdbfa2459fe9543fc  gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
*************** bb895226639a1aae7be7b56a7158df50  gcc/te
*** 102601,102606 ****
--- 103055,103061 ----
  7cf900944e15c19b0347cf838fc4aa68  gcc/testsuite/gcc.target/sh/pr64851-4.c
  1e560b149f127fbbe8e19a0786737e83  gcc/testsuite/gcc.target/sh/pr6526.c
  96ccc21c08a032884c88704b49d3a916  gcc/testsuite/gcc.target/sh/pr67675.c
+ 954cde0ffb96f31618f11766e0a02713  gcc/testsuite/gcc.target/sh/pr67731.c
  3f7b73faf0fd1d90a4ea83808baabeda  gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c
  4f89e60f52b3ae8a20bde13055248307  gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
  db7a02bef0ea1d74a99297c9ee53c525  gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
*************** beb5f32bbfe67092637981daab63c0e9  gcc/te
*** 102679,102686 ****
  51da71a9631e2769588765c1734024be  gcc/testsuite/gcc.target/sparc/bmaskbshuf-1.c
  2fde479e25184fdcc6f9e94d0b5c15ad  gcc/testsuite/gcc.target/sparc/bmaskbshuf-2.c
  019da970597edf6187323a8e6d8d3fd7  gcc/testsuite/gcc.target/sparc/cas64.c
! d221487dd70d0c776eff96c67b8adc06  gcc/testsuite/gcc.target/sparc/cbcond-1.c
! 4e0309e28118036178fe963e1c3da82a  gcc/testsuite/gcc.target/sparc/cbcond-2.c
  8b7e178ec9569253b3b34020d323079f  gcc/testsuite/gcc.target/sparc/cmask.c
  61fdcc3e39deca7e4f123378b814dd0f  gcc/testsuite/gcc.target/sparc/combined-1.c
  be4e8621f0151086de802a20702cd1af  gcc/testsuite/gcc.target/sparc/combined-2.c
--- 103134,103141 ----
  51da71a9631e2769588765c1734024be  gcc/testsuite/gcc.target/sparc/bmaskbshuf-1.c
  2fde479e25184fdcc6f9e94d0b5c15ad  gcc/testsuite/gcc.target/sparc/bmaskbshuf-2.c
  019da970597edf6187323a8e6d8d3fd7  gcc/testsuite/gcc.target/sparc/cas64.c
! c3668404ae0a813bc8180945066174cd  gcc/testsuite/gcc.target/sparc/cbcond-1.c
! fad6c23fce09da74b193fe540d9797ee  gcc/testsuite/gcc.target/sparc/cbcond-2.c
  8b7e178ec9569253b3b34020d323079f  gcc/testsuite/gcc.target/sparc/cmask.c
  61fdcc3e39deca7e4f123378b814dd0f  gcc/testsuite/gcc.target/sparc/combined-1.c
  be4e8621f0151086de802a20702cd1af  gcc/testsuite/gcc.target/sparc/combined-2.c
*************** a6501f830b7d1b9e944beb9e5db075f6  gcc/te
*** 102744,102752 ****
  27bc21317eeddefa4b9cc41e1c4e363c  gcc/testsuite/gcc.target/sparc/noresult.c
  a54091faea7a1abd6cd4fbd0ef1b4336  gcc/testsuite/gcc.target/sparc/overflow-1.c
  d0fc65bbbe891276a96818aa810ee61a  gcc/testsuite/gcc.target/sparc/overflow-2.c
! 444e8beace1b4de7dfc39e780fc67fac  gcc/testsuite/gcc.target/sparc/overflow-3.c
! 2d8b17d688d100fd3cb6453f855222b0  gcc/testsuite/gcc.target/sparc/overflow-4.c
! 8475c91c4d278191b81ca429107475b1  gcc/testsuite/gcc.target/sparc/overflow-5.c
  49458c6e2cd69ad6620fa55db5d3621f  gcc/testsuite/gcc.target/sparc/overflow-6.c
  0e446c8782cfda1bf1b2b7467cdf43af  gcc/testsuite/gcc.target/sparc/pdist-2.c
  77281e86e797be1ef8a0784c9a4db58a  gcc/testsuite/gcc.target/sparc/pdist-3.c
--- 103199,103207 ----
  27bc21317eeddefa4b9cc41e1c4e363c  gcc/testsuite/gcc.target/sparc/noresult.c
  a54091faea7a1abd6cd4fbd0ef1b4336  gcc/testsuite/gcc.target/sparc/overflow-1.c
  d0fc65bbbe891276a96818aa810ee61a  gcc/testsuite/gcc.target/sparc/overflow-2.c
! 929fac4de5794cc7dd75063b7cd5643e  gcc/testsuite/gcc.target/sparc/overflow-3.c
! 2b280b8f1ebeda91133b6198d7023607  gcc/testsuite/gcc.target/sparc/overflow-4.c
! 45415694e5915a0b26b450975729e990  gcc/testsuite/gcc.target/sparc/overflow-5.c
  49458c6e2cd69ad6620fa55db5d3621f  gcc/testsuite/gcc.target/sparc/overflow-6.c
  0e446c8782cfda1bf1b2b7467cdf43af  gcc/testsuite/gcc.target/sparc/pdist-2.c
  77281e86e797be1ef8a0784c9a4db58a  gcc/testsuite/gcc.target/sparc/pdist-3.c
*************** e5c267912e5c8f2e18ebb9ce814789ba  gcc/te
*** 102768,102774 ****
  c51a16c76fd1df5c182c5e6b77d1acfa  gcc/testsuite/gcc.target/sparc/setcc-9.c
  90b1f7b71b95624e3baf3a7c71e032b5  gcc/testsuite/gcc.target/sparc/setjmp-1.c
  438ea8b2cc3dd028f6b33b12541b2b7f  gcc/testsuite/gcc.target/sparc/sibcall-dslot.c
! b7889b31cd2ce76e65842ca26b253777  gcc/testsuite/gcc.target/sparc/small-struct-1.c
  9ffd7b94418f62e4bc1700c00a93b9ff  gcc/testsuite/gcc.target/sparc/sparc-align-1.c
  0fdc378e88ad378a181a8f7ba247889f  gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
  eb9fea9eb3ccdd5fb4d85ac011c10dc5  gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
--- 103223,103229 ----
  c51a16c76fd1df5c182c5e6b77d1acfa  gcc/testsuite/gcc.target/sparc/setcc-9.c
  90b1f7b71b95624e3baf3a7c71e032b5  gcc/testsuite/gcc.target/sparc/setjmp-1.c
  438ea8b2cc3dd028f6b33b12541b2b7f  gcc/testsuite/gcc.target/sparc/sibcall-dslot.c
! 86b61b1c570605c6bd99309aaee7206b  gcc/testsuite/gcc.target/sparc/small-struct-1.c
  9ffd7b94418f62e4bc1700c00a93b9ff  gcc/testsuite/gcc.target/sparc/sparc-align-1.c
  0fdc378e88ad378a181a8f7ba247889f  gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
  eb9fea9eb3ccdd5fb4d85ac011c10dc5  gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
*************** f1eebb736461b5a966e9f19ca27855c5  gcc/te
*** 103467,103473 ****
  67f6bc3272f355380928a1c0a5bf2049  gcc/testsuite/gcc.target/xtensa/funnel_shifter.c
  5dd88a67050813a2722e394515530667  gcc/testsuite/gcc.target/xtensa/mabi-call0.c
  55cb36db164b6243fa3041628937695c  gcc/testsuite/gcc.target/xtensa/mabi-windowed.c
- a15a47e169752fa5ceea299d07d5f088  gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c
  b7bda6f199a1b6771b9270aa47b61b64  gcc/testsuite/gcc.target/xtensa/pr108919.c
  678c937a9da1921d2e37ae1471198265  gcc/testsuite/gcc.target/xtensa/pr120888-1.c
  1352d54a13d6537d0f0db9de52bee213  gcc/testsuite/gcc.target/xtensa/pr120888-2.c
--- 103922,103927 ----
*************** f3b8d83af012a8804b15f5016664e973  gcc/te
*** 109708,109714 ****
  b2f376eece4fd9267305268634b9ef98  gcc/testsuite/gfortran.dg/coarray_atomic_2.f90
  1d7342a16f42a3d440e6d6622646093f  gcc/testsuite/gfortran.dg/coarray_atomic_3.f90
  0bbe63eed5e9eda2a1fbaac162978ea0  gcc/testsuite/gfortran.dg/coarray_atomic_4.f90
! 7fdda7f05c78a75b1c1f77af8274488b  gcc/testsuite/gfortran.dg/coarray_atomic_5.f90
  53606f253145ffe43df39cc61fe5aef2  gcc/testsuite/gfortran.dg/coarray_atomic_6.f90
  47af4614d0edd5061b2696b16ddcf85a  gcc/testsuite/gfortran.dg/coarray_class_1.f90
  ead5277cf75b1f10e47a668cb257f485  gcc/testsuite/gfortran.dg/coarray_class_2.f90
--- 110162,110168 ----
  b2f376eece4fd9267305268634b9ef98  gcc/testsuite/gfortran.dg/coarray_atomic_2.f90
  1d7342a16f42a3d440e6d6622646093f  gcc/testsuite/gfortran.dg/coarray_atomic_3.f90
  0bbe63eed5e9eda2a1fbaac162978ea0  gcc/testsuite/gfortran.dg/coarray_atomic_4.f90
! 93a1d1dba7982219d9830aa797a2ebce  gcc/testsuite/gfortran.dg/coarray_atomic_5.f90
  53606f253145ffe43df39cc61fe5aef2  gcc/testsuite/gfortran.dg/coarray_atomic_6.f90
  47af4614d0edd5061b2696b16ddcf85a  gcc/testsuite/gfortran.dg/coarray_class_1.f90
  ead5277cf75b1f10e47a668cb257f485  gcc/testsuite/gfortran.dg/coarray_class_2.f90
*************** dfae0584c34f174386746029a2bbf0b1  gcc/te
*** 113698,113703 ****
--- 114152,114162 ----
  a5070ccaa9b85c10608985b219421c39  gcc/testsuite/gfortran.dg/pdt_59.f03
  65d2ad728417ad3174fc1ce2b51a458d  gcc/testsuite/gfortran.dg/pdt_6.f03
  9dbc08fbae591c5a9da5818dd56b234e  gcc/testsuite/gfortran.dg/pdt_60.f03
+ e8c4c8bb9c03a99a4368a372096fdfb9  gcc/testsuite/gfortran.dg/pdt_61.f03
+ 44e4aa2dabc782efe50146abb024d7ce  gcc/testsuite/gfortran.dg/pdt_62.f03
+ a4dd26f2891055a5842e6732191c51f8  gcc/testsuite/gfortran.dg/pdt_63.f03
+ bd24b2acc55e464c3c06d5812e34478e  gcc/testsuite/gfortran.dg/pdt_64.f03
+ 9d6cb27f1bfd7fd4a30c1c828a28b2d6  gcc/testsuite/gfortran.dg/pdt_65.f03
  d2c9dae0c6e2385c5712aba8e12a70ba  gcc/testsuite/gfortran.dg/pdt_7.f03
  e21f38a2db39f95405441b61c12cf1e6  gcc/testsuite/gfortran.dg/pdt_8.f03
  c621629f10feffbfa9fef1441a610e53  gcc/testsuite/gfortran.dg/pdt_9.f03
*************** e9e87e079e88e1bdbe28a6f7713a7a67  gcc/te
*** 115059,115064 ****
--- 115518,115524 ----
  705e27cebf71096beecc3e95d1e9d6f5  gcc/testsuite/gfortran.dg/pure_initializer_1.f90
  e004777cc16d5ca611aa373cfeb2476d  gcc/testsuite/gfortran.dg/pure_initializer_2.f90
  78598283a1854329ecefb2cb4f92fead  gcc/testsuite/gfortran.dg/pure_initializer_3.f90
+ 543bc5f0aa252f9446e08c49a605c1e4  gcc/testsuite/gfortran.dg/pure_result.f90
  b2cfcc9d08774d6140c45f9ef26bf787  gcc/testsuite/gfortran.dg/quad_1.f90
  fbd7c496dd01e2a55c3629660efbc939  gcc/testsuite/gfortran.dg/quad_2.f90
  e60be2de79803cde8c8bb591d7bc648a  gcc/testsuite/gfortran.dg/quad_3.f90
*************** ae44913762018fc6abc0d71eaefa7118  gcc/te
*** 115668,115674 ****
  0579b6f7a7af90ba1e08bb037b5df71a  gcc/testsuite/gfortran.dg/team_end_3.f90
  a579a2ebae177c6c8937cb2a5faa8bb7  gcc/testsuite/gfortran.dg/team_form_1.f90
  e214774323eb8f7cb55483f3c6d28c7f  gcc/testsuite/gfortran.dg/team_form_2.f90
! 6e76b4c3c1ffcc8c2f78cbbb34814bc4  gcc/testsuite/gfortran.dg/team_form_3.f90
  d7ffe31f6d9cca347398b492cd545696  gcc/testsuite/gfortran.dg/team_get_1.f90
  133f909212e2f9312b1c3c8163bd2cfb  gcc/testsuite/gfortran.dg/team_number_1.f90
  4dd2f060153431695f3d811e20879ce4  gcc/testsuite/gfortran.dg/team_sync_1.f90
--- 116128,116134 ----
  0579b6f7a7af90ba1e08bb037b5df71a  gcc/testsuite/gfortran.dg/team_end_3.f90
  a579a2ebae177c6c8937cb2a5faa8bb7  gcc/testsuite/gfortran.dg/team_form_1.f90
  e214774323eb8f7cb55483f3c6d28c7f  gcc/testsuite/gfortran.dg/team_form_2.f90
! cea49456ead7a613d2cd9d4dfdb7b3b6  gcc/testsuite/gfortran.dg/team_form_3.f90
  d7ffe31f6d9cca347398b492cd545696  gcc/testsuite/gfortran.dg/team_get_1.f90
  133f909212e2f9312b1c3c8163bd2cfb  gcc/testsuite/gfortran.dg/team_number_1.f90
  4dd2f060153431695f3d811e20879ce4  gcc/testsuite/gfortran.dg/team_sync_1.f90
*************** e3ed6ec2719e9380031e3e22af66563e  gcc/te
*** 116183,116188 ****
--- 116643,116649 ----
  e908da4224e8c1e801b93e3fde2381b1  gcc/testsuite/gfortran.dg/vect/pr69882.f90
  8be888cc0b6731a3a012553b4bf9398b  gcc/testsuite/gfortran.dg/vect/pr69980.f90
  cefc2799ac1f1f0963931200eb469fc0  gcc/testsuite/gfortran.dg/vect/pr70043.f90
+ 175fe6cf2d2426897e9641b896ed9db4  gcc/testsuite/gfortran.dg/vect/pr70102.f
  44e4c7039bf8aa2059bc3842f955c44d  gcc/testsuite/gfortran.dg/vect/pr77848.f
  abf68e470c0aa7bc77cac4f589082522  gcc/testsuite/gfortran.dg/vect/pr81303.f
  677875c22fcbdaacf0630aebbf7740ee  gcc/testsuite/gfortran.dg/vect/pr83232.f90
*************** bc764eca2f460bc6fb657fb675420237  gcc/te
*** 116740,116745 ****
--- 117201,117208 ----
  eabee42e1a561616023ffd1f4d1a64e2  gcc/testsuite/gfortran.fortran-torture/execute/write_logical.f90
  e37afcf68e701a2324e777ab5f6054bf  gcc/testsuite/gfortran.target/aarch64/aarch64.exp
  c37460d9fc2ef94382053354df0c3ef3  gcc/testsuite/gfortran.target/aarch64/pr116234.f
+ f49a9e5ed9144077a6174c71610d8918  gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90
+ 6890252516b3245a15477e317869c38e  gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90
  ae00a4e2372b755ec611b96aaff6a49b  gcc/testsuite/gfortran.target/riscv/rvv/pr111395.f90
  284fdebd0dafabcd770080ec38c8109a  gcc/testsuite/gfortran.target/riscv/rvv/pr111566.f90
  803fa495544cb97b2d47fa3c10b273ce  gcc/testsuite/gfortran.target/riscv/rvv/pr118182.f
*************** e6f3c702e8ca5bfbe627dcb752971fdb  gcc/te
*** 116759,116764 ****
--- 117222,117231 ----
  ec56bce7bdde9ba4515172d6349ed250  gcc/testsuite/gm2.dg/pim/fail/dg-pim-fail.exp
  4e88623298e1e2e2a0a5e56077e5f006  gcc/testsuite/gm2.dg/pim/fail/opaquedefs.def
  27a1f5c9aed629a98954f37c54a84552  gcc/testsuite/gm2.dg/pim/fail/opaquedefs.mod
+ de4ede524274f9710ef8bf904fe6ec06  gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod
+ 0683e282cbd968a6f1dfa78c956bd80d  gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod
+ 6109d687a613909b86fef68d3b2436b1  gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod
+ dad8856ff49fe71a7752d5bad615ab0a  gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod
  bac3b2f6653a8c5706652acb80672851  gcc/testsuite/gm2.dg/spell/iso/fail/badspellabs.mod
  629a261c471eee1fd867cb40ab126a66  gcc/testsuite/gm2.dg/spell/iso/fail/badspelladr.mod
  36f7e140b207b9b84c44ebecea4be888  gcc/testsuite/gm2.dg/spell/iso/fail/badspellcap.mod
*************** b3a316ada43c24ff36cbe71860fae91c  gcc/te
*** 119017,119022 ****
--- 119484,119492 ----
  26bbb4b239255e447bbe6c32ccb6f5f3  gcc/testsuite/gnat.dg/aggr30.adb
  3c5d0783cbdc3181db59d9f27a9e1a2d  gcc/testsuite/gnat.dg/aggr30.ads
  4c012319986c2dce532428fea4934ee2  gcc/testsuite/gnat.dg/aggr31.adb
+ f202185bfd0a21aad1b2b2a3c53f0530  gcc/testsuite/gnat.dg/aggr32.adb
+ c08e4f7d35898f0bc9c4996849adc409  gcc/testsuite/gnat.dg/aggr32_pkg-child.ads
+ 1057b1221f0bd9331d17412ee8c29e1d  gcc/testsuite/gnat.dg/aggr32_pkg.ads
  35168b6dce753ec723ff0dcf21d977d0  gcc/testsuite/gnat.dg/aggr4.adb
  a12ec40d7ebc1ab08b05b0d1f6a57bc4  gcc/testsuite/gnat.dg/aggr7.adb
  39fba9f7f4870b15e9c37bcf9a358858  gcc/testsuite/gnat.dg/aggr8.adb
*************** c3d551a8416dc4b2870263e10877307e  gcc/te
*** 120878,120883 ****
--- 121348,121374 ----
  84bbd54b835597ff50d8d9c0c1ed6128  gcc/testsuite/gnat.dg/specs/generic_inst2-child1.ads
  acb50fb5dcaeadfaa1d06f3a291ad5ac  gcc/testsuite/gnat.dg/specs/generic_inst2-child2.ads
  26c02326292bb6ec71f4f8278f140bff  gcc/testsuite/gnat.dg/specs/generic_inst2.ads
+ 5d5cb7a49acfaa5943a6da3c8556db44  gcc/testsuite/gnat.dg/specs/generic_inst3.ads
+ 5eb74ab82203e9ec8672d15f0b59e0cc  gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb
+ 9f946cfeaca1a840772cb64a3c3379f8  gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads
+ cef73f5a59a44c65840f3e48ae81a8fc  gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads
+ d0330f791cc618e6684cc4b6018cbe6f  gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads
+ 31297f964710ac609d21fff9fa351082  gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads
+ 98f234b5baedaad42b85458c439275a2  gcc/testsuite/gnat.dg/specs/generic_inst4-child1.ads
+ 6b7ec4192e6648cf92a404b6f3f1ff19  gcc/testsuite/gnat.dg/specs/generic_inst4-child2.ads
+ 8ce552b8e7cb10cc5d28cbd647a45dbc  gcc/testsuite/gnat.dg/specs/generic_inst4.ads
+ e5bd592b729f3a221c44b1d47e431798  gcc/testsuite/gnat.dg/specs/generic_inst5.ads
+ 029ecd56dca31aed4b0ad9438b349541  gcc/testsuite/gnat.dg/specs/generic_inst5_pkg1.ads
+ ec3147943e1840cf222e233c36c34282  gcc/testsuite/gnat.dg/specs/generic_inst5_pkg2.ads
+ fb3162e1e6a376d7c08844580159f732  gcc/testsuite/gnat.dg/specs/generic_inst6.ads
+ 9bda5b7e44ed4f01f0e559e1943fd498  gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads
+ 7e754595cb8016d3ac6ba12350b8164c  gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads
+ 2a3afc99517f6165c9816587c95b6af7  gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads
+ 4b588264880adac8f16b828ce46aba7c  gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads
+ 6f19af274252b7522e1d8c842971808e  gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads
+ d0cb31bf0b8e3cd0e3dc700f0accb597  gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads
+ 6f8060e304c62d67ba464421147c0dc2  gcc/testsuite/gnat.dg/specs/generic_inst7.ads
+ 3c9c5180751fdabe5a5c34ad71c62a0d  gcc/testsuite/gnat.dg/specs/generic_inst8.ads
  484402f090540a3714934de7a830cc2f  gcc/testsuite/gnat.dg/specs/genericppc.ads
  5fadbbff25531c82473d756d722cd174  gcc/testsuite/gnat.dg/specs/gnati.ads
  f0f859863b2bb6251359cf35dc6ffbf5  gcc/testsuite/gnat.dg/specs/iface_eq_test-child.ads
*************** e5ba939d3c279c5b6a8f745c0873635b  gcc/te
*** 120946,120951 ****
--- 121437,121444 ----
  1ffc926f5fa0093e97a56785f5de974e  gcc/testsuite/gnat.dg/specs/private1.ads
  8789c55b908f87861cc84839fcf5c8e8  gcc/testsuite/gnat.dg/specs/private2.ads
  1a54485794dbb614c393e5e7884acc69  gcc/testsuite/gnat.dg/specs/private2_pkg.ads
+ 7b27b6bdd1df4f3312e7f8c1e8faf020  gcc/testsuite/gnat.dg/specs/private3-child.ads
+ a84edadaee1ab9facb33753c1ef587df  gcc/testsuite/gnat.dg/specs/private3.ads
  fc55b1bcb0c272bc29027f58c8607f74  gcc/testsuite/gnat.dg/specs/private_with.ads
  38c51300d90d115072862fad182112ba  gcc/testsuite/gnat.dg/specs/renaming1.ads
  3b6772c48920aaa7f63a032ce18244a2  gcc/testsuite/gnat.dg/specs/renaming2.ads
*************** de366240409b1c3413cd274333487fb7  gcc/te
*** 121000,121005 ****
--- 121493,121503 ----
  a013922e8c147a09784a5aca21aa3a65  gcc/testsuite/gnat.dg/specs/unchecked_union1.ads
  fbc11dba24887c4af40c8660f7168a67  gcc/testsuite/gnat.dg/specs/unchecked_union2.ads
  c8cf8a4c8db78f809bd3550ca820e6a5  gcc/testsuite/gnat.dg/specs/universal_fixed.ads
+ d3a5054f56a79aec493b187a6ce64653  gcc/testsuite/gnat.dg/specs/unknown_discr1.ads
+ 5238a0473015a85e1ecb51e38ef41fac  gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads
+ 310a21f02e107b0cd4abbae5e441e047  gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads
+ df80ee104d6cfa84009bc5ebe09950d3  gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads
+ 5e9cc0b2e65ed848874fcb6d9fb08525  gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads
  956da2e940d0e7706607f91ce39d70ad  gcc/testsuite/gnat.dg/specs/variant_part.ads
  12e2e0159b45a86a40c49bc020048d43  gcc/testsuite/gnat.dg/specs/varsize_return.ads
  8bea113f401f2dd5575f665633d17e57  gcc/testsuite/gnat.dg/specs/varsize_return2.ads
*************** cd1ae8bd0a64f513e4a2f5cf6f3ddf35  gcc/te
*** 121354,121359 ****
--- 121852,121858 ----
  0c380665cb8866e926609d97d60e74d3  gcc/testsuite/gnat.dg/use_type1.adb
  2ff25aab3331ed26139d02e26ef160d7  gcc/testsuite/gnat.dg/use_type2.adb
  ca0cc4af1afd7c89b8c00147944eface  gcc/testsuite/gnat.dg/use_type3.adb
+ 6d0aca8baae14ff48033848e1e8f6c56  gcc/testsuite/gnat.dg/use_type4.adb
  9e88b7ce099b1d8cf08618b19708a2f3  gcc/testsuite/gnat.dg/valid1.adb
  b9b78fbd058ac9dfd657617df5ab8b4c  gcc/testsuite/gnat.dg/valid4.adb
  978b7483f1bef09979e22217b25587be  gcc/testsuite/gnat.dg/valid4_pkg.adb
*************** ec15ff347aa69c536e7e791163bb9e73  gcc/te
*** 124870,124879 ****
--- 125369,125381 ----
  4d9cb4f27492d0e9e7915172cfa058d1  gcc/testsuite/rust/compile/arrays1.rs
  a50f83c7d5e7ebc8dba9c772baf38b47  gcc/testsuite/rust/compile/arrays2.rs
  07cc7e7ee38e972eb2ab6058ab910205  gcc/testsuite/rust/compile/assume.rs
+ 8ab13ed24f21de637e3717d6e8e00c47  gcc/testsuite/rust/compile/attr-macro.rs
  6d43a3c855de9a784b5daf14d332bb2c  gcc/testsuite/rust/compile/attr-mismatch-crate-name.rs
  e3c9ec33d7df70539fa80809be2ce0c9  gcc/testsuite/rust/compile/attr_cold.rs
  d9be47bf725d64b4d76c4e5de43dd2da  gcc/testsuite/rust/compile/attr_deprecated.rs
  3a6cf40fed3e72fa67e9861964d3f4f8  gcc/testsuite/rust/compile/attr_deprecated_2.rs
+ ac2bf5f892c4e2c945604e00191ad73c  gcc/testsuite/rust/compile/attr_malformed_doc.rs
+ f555ab8bfe9efe1ebc6a30beabba0b9e  gcc/testsuite/rust/compile/attr_malformed_path.rs
  16f9a2d92f2d818a2805160b81e5cbf4  gcc/testsuite/rust/compile/auto_trait.rs
  285d2a6251c3beede3a80d6bce086007  gcc/testsuite/rust/compile/auto_trait_invalid.rs
  10958953946fbdde105431e2937a1695  gcc/testsuite/rust/compile/auto_trait_super_trait.rs
*************** b669ba48ac5e60d6d2fe212ead01eb4d  gcc/te
*** 124922,124927 ****
--- 125424,125430 ----
  0ade7c1bac955f1b03af6464186073fc  gcc/testsuite/rust/compile/cfg-attr.rs
  a75268078027e4027a1c1f8b374e58c2  gcc/testsuite/rust/compile/cfg-core1.rs
  70f80e73e71174a8c4e1c8791f40099a  gcc/testsuite/rust/compile/cfg-core2.rs
+ 88da6d39d39cebd3c829b88d6ec7c635  gcc/testsuite/rust/compile/cfg-test.rs
  2648512ce6f2397fa9b2b9b663774782  gcc/testsuite/rust/compile/cfg1.rs
  39df3ad8f1d7a8d1cabbc2a028bca689  gcc/testsuite/rust/compile/cfg2.rs
  c73d64b77895517ecd6f3c68791c8a69  gcc/testsuite/rust/compile/cfg3.rs
*************** d41d8cd98f00b204e9800998ecf8427e  gcc/te
*** 125012,125017 ****
--- 125515,125521 ----
  46fa9cf76f8ad21f88d3360570229a80  gcc/testsuite/rust/compile/empty_union.rs
  1dcf6277650dd744a3d566444a316aa0  gcc/testsuite/rust/compile/enum_discriminant1.rs
  83a2384c9b68e56f0376e65eb9c9e6bc  gcc/testsuite/rust/compile/enum_discriminant2.rs
+ 931948d5206813703de5d9aa73357239  gcc/testsuite/rust/compile/enum_discriminant3.rs
  43d08354ccf563eb58fe9931afc4a3a6  gcc/testsuite/rust/compile/enum_variant_name.rs
  6db02af4f7c9eb1367785df801782bbc  gcc/testsuite/rust/compile/exclusive_range_pattern.rs
  9c04cedc1f1c9ec425a75c21dbaff743  gcc/testsuite/rust/compile/exclusive_range_pattern_feature_gate.rs
*************** b129c59cb9340d86c151685156da3f0c  gcc/te
*** 125036,125041 ****
--- 125540,125546 ----
  5ee6657185ec67299ef2ace853f873b7  gcc/testsuite/rust/compile/for_expr.rs
  e41c2cabd63dba549da749a8fed6ca7a  gcc/testsuite/rust/compile/for_lifetimes.rs
  3121e6022ec6fd6781b3bb2218a41bee  gcc/testsuite/rust/compile/format_args_basic_expansion.rs
+ 095f89847ace805fa9378dcf0d277ef3  gcc/testsuite/rust/compile/format_args_concat.rs
  444951ca92739bdbdc74317738c2a855  gcc/testsuite/rust/compile/format_args_extra_comma.rs
  9c06b22a10dcf3a218bb690997175a3f  gcc/testsuite/rust/compile/found_struct.rs
  03ce7bc2c5e3478be586fcc302a8200f  gcc/testsuite/rust/compile/frust-compile-until.rs
*************** eb85bcea53e38d14f7bcc7f982cc4140  gcc/te
*** 125062,125077 ****
--- 125567,125585 ----
  060d22d6e7f679a78be3e794571d067f  gcc/testsuite/rust/compile/generics8.rs
  9aa765e066290dc262e89eb48abc6f28  gcc/testsuite/rust/compile/generics9.rs
  9e631ea0ca0d4c58b5f20bdf78414c7e  gcc/testsuite/rust/compile/glob_import_enum.rs
+ 88f9d490b9687075686515d220144c0d  gcc/testsuite/rust/compile/global-path-array.rs
  2e2238492198d9ef7c0141722cead0a3  gcc/testsuite/rust/compile/if-without-else.rs
  bc84abac17812c46c39363b8ae9a8ad9  gcc/testsuite/rust/compile/if_let_expr.rs
  bcb7125cf04603fb905af55075f3c8b9  gcc/testsuite/rust/compile/if_let_expr_simple.rs
  b38301cec7d4b035fa6efa8eb15100bf  gcc/testsuite/rust/compile/iflet.rs
+ 3fdd918c7c90e378ac4790739aebb5b6  gcc/testsuite/rust/compile/impl_fnptr.rs
  8eae850c4702b6718eaaa35c514b1457  gcc/testsuite/rust/compile/impl_trait_diag.rs
  f3d4caa9d92a54f8a1417df4bd0823d6  gcc/testsuite/rust/compile/impl_trait_generic_arg.rs
  c7d60400964e3621102e44ba4cef69f9  gcc/testsuite/rust/compile/implicit_returns_err1.rs
  effa05530ec2bc9508c522bddd5e2b38  gcc/testsuite/rust/compile/implicit_returns_err2.rs
  4f820dabf53d65a41cbe62abc9094e12  gcc/testsuite/rust/compile/implicit_returns_err3.rs
  57564c88d8277457b1b56c8de206a9b3  gcc/testsuite/rust/compile/implicit_returns_err4.rs
+ 2fb3589509010f4f08feaa1662d38a4f  gcc/testsuite/rust/compile/import_wildcards.rs
  f5a0d22fb97460ebf5ec424228131615  gcc/testsuite/rust/compile/include_empty.rs
  bdcf4ee0d9c01755816b4b4cfd686a81  gcc/testsuite/rust/compile/infer-crate-name.rs
  d1c354b6a0b4fc8d599d65fd14e29373  gcc/testsuite/rust/compile/inline_1.rs
*************** c5fa22f9b64f1ed3638ff08ee2604990  gcc/te
*** 125130,125136 ****
  95b616180b39bcdf627de4a88d7f6b8c  gcc/testsuite/rust/compile/issue-1525.rs
  b436c410b33bf1a4a8345bcc091c9a93  gcc/testsuite/rust/compile/issue-1589.rs
  40bfcf112fd1480b00d3d4858254154a  gcc/testsuite/rust/compile/issue-1725-1.rs
! cd4c7414f38eda546be79f8fae5cdb0e  gcc/testsuite/rust/compile/issue-1725-2.rs
  0e1d074590d2b9f2a4070df6ac25de28  gcc/testsuite/rust/compile/issue-1773.rs
  a27cbcf495ce6fabb51f8978e36c8576  gcc/testsuite/rust/compile/issue-1786.rs
  d26d80b504c5b7aceaa2fef4dec88320  gcc/testsuite/rust/compile/issue-1807.rs
--- 125638,125644 ----
  95b616180b39bcdf627de4a88d7f6b8c  gcc/testsuite/rust/compile/issue-1525.rs
  b436c410b33bf1a4a8345bcc091c9a93  gcc/testsuite/rust/compile/issue-1589.rs
  40bfcf112fd1480b00d3d4858254154a  gcc/testsuite/rust/compile/issue-1725-1.rs
! cb3ba74e97e2ec40f4b5911b7a1b825a  gcc/testsuite/rust/compile/issue-1725-2.rs
  0e1d074590d2b9f2a4070df6ac25de28  gcc/testsuite/rust/compile/issue-1773.rs
  a27cbcf495ce6fabb51f8978e36c8576  gcc/testsuite/rust/compile/issue-1786.rs
  d26d80b504c5b7aceaa2fef4dec88320  gcc/testsuite/rust/compile/issue-1807.rs
*************** f016c98a316a423cbe9110749bb60df8  gcc/te
*** 125183,125189 ****
  9305a2873b28168b52f4519a9889d44f  gcc/testsuite/rust/compile/issue-2369.rs
  8ab718258c1a331e258d5fa140812639  gcc/testsuite/rust/compile/issue-2375.rs
  c978074de410f3710470187bdc917f4b  gcc/testsuite/rust/compile/issue-2391.rs
! b76da66b2264ea9a5e1aabb05e471852  gcc/testsuite/rust/compile/issue-2394.rs
  327d620bf438ac1ff1393dfc76ecc0d6  gcc/testsuite/rust/compile/issue-2421_str.rs
  204e9b043ccb1cba225f9859f0fa82af  gcc/testsuite/rust/compile/issue-2423.rs
  572e79cc2733b6ad48fb030aba698641  gcc/testsuite/rust/compile/issue-2431.rs
--- 125691,125697 ----
  9305a2873b28168b52f4519a9889d44f  gcc/testsuite/rust/compile/issue-2369.rs
  8ab718258c1a331e258d5fa140812639  gcc/testsuite/rust/compile/issue-2375.rs
  c978074de410f3710470187bdc917f4b  gcc/testsuite/rust/compile/issue-2391.rs
! 29321f6c75b7d162c5c0508e4fdc620e  gcc/testsuite/rust/compile/issue-2394.rs
  327d620bf438ac1ff1393dfc76ecc0d6  gcc/testsuite/rust/compile/issue-2421_str.rs
  204e9b043ccb1cba225f9859f0fa82af  gcc/testsuite/rust/compile/issue-2423.rs
  572e79cc2733b6ad48fb030aba698641  gcc/testsuite/rust/compile/issue-2431.rs
*************** ea87eb5dd98fc440678cbfc183368898  gcc/te
*** 125262,125267 ****
--- 125770,125776 ----
  d1eacc10be9cd3eb212ceee0226cf0bb  gcc/testsuite/rust/compile/issue-3525.rs
  9c32fb3d820cc1289bd30f7b91250129  gcc/testsuite/rust/compile/issue-3530-1.rs
  c7919a109aede82f1914922ecb4e4c91  gcc/testsuite/rust/compile/issue-3530-2.rs
+ 59d495366774e48adafa75d4dd37d324  gcc/testsuite/rust/compile/issue-3538.rs
  51368e372b4ae4949ed42a12880375bc  gcc/testsuite/rust/compile/issue-3541-1.rs
  a16fac448d52ecc36f845f158322f7b4  gcc/testsuite/rust/compile/issue-3541-2.rs
  6c43194fbbe3e88e45c70087448b280d  gcc/testsuite/rust/compile/issue-3546.rs
*************** cccfe17fac6ad050f5a21f250c83d9bc  gcc/te
*** 125271,125276 ****
--- 125780,125786 ----
  844e28af629e8aaa74e31dca339d140c  gcc/testsuite/rust/compile/issue-3553.rs
  2e9e39ce283620e50ccd623e5758e6fd  gcc/testsuite/rust/compile/issue-3554-1.rs
  89ae87e8c1e981b83ca8a9c23e184312  gcc/testsuite/rust/compile/issue-3554-2.rs
+ 92e0537fcd15f7747426645bd484ab53  gcc/testsuite/rust/compile/issue-3556.rs
  8ed9f05b0580f69cc8cbdd55969abf3a  gcc/testsuite/rust/compile/issue-3563.rs
  a183cd8a8a21fd3792bc6c25a0593dc3  gcc/testsuite/rust/compile/issue-3566-1.rs
  1e881f3d39a6401c4531e184680546e9  gcc/testsuite/rust/compile/issue-3566-2.rs
*************** c03fabc8909fdf74b1e0ac91674acf95  gcc/te
*** 125279,125284 ****
--- 125789,125795 ----
  27be33d9e4815f94f0759d60b77c8b14  gcc/testsuite/rust/compile/issue-3581-1.rs
  b790a48d62804a4138b4fbcdf0e2d96b  gcc/testsuite/rust/compile/issue-3581-2.rs
  3cd26856f36e846540fccbbf818b4684  gcc/testsuite/rust/compile/issue-3588.rs
+ 3e6f4e428fb3c361858e39aa3ef67681  gcc/testsuite/rust/compile/issue-3592.rs
  bd3f5f5421f7412556d571aaed504e87  gcc/testsuite/rust/compile/issue-3599.rs
  397a757997946ab15af47e9fad31284c  gcc/testsuite/rust/compile/issue-3605.rs
  61beaa24a09b8012dce7ddadbce604a1  gcc/testsuite/rust/compile/issue-3606.rs
*************** c68fac7e04fd77c1639ea1fd3277409c  gcc/te
*** 125291,125296 ****
--- 125802,125808 ----
  b73bff1144b326261fd3bce5eddb22d3  gcc/testsuite/rust/compile/issue-3628.rs
  806d9b49fd25931d59857f798a217248  gcc/testsuite/rust/compile/issue-3642.rs
  5953d50711d31ae6f6b26e3727986881  gcc/testsuite/rust/compile/issue-3643.rs
+ ee89f9a1a77884e7520601ab049cb4d1  gcc/testsuite/rust/compile/issue-3645.rs
  d690a668cb1a4d9fe94ee30b4e2a967b  gcc/testsuite/rust/compile/issue-3646.rs
  67240263fa4bb8b82dfc90d1836012aa  gcc/testsuite/rust/compile/issue-3647.rs
  752cb28fa8bc90f6206905c610a7acd0  gcc/testsuite/rust/compile/issue-3648.rs
*************** a82f3bb8e730a6249c2d9d547940590a  gcc/te
*** 125308,125325 ****
--- 125820,125863 ----
  10cacd69cdbb198a37f27ed27a03a585  gcc/testsuite/rust/compile/issue-3667.rs
  d7a0aa61ac6ea480aa470031428550d2  gcc/testsuite/rust/compile/issue-3671.rs
  157c904f67c2f79161fef218c5808562  gcc/testsuite/rust/compile/issue-3711.rs
+ b6cc4ab95094c5e9f54084f73495560d  gcc/testsuite/rust/compile/issue-3726.rs
  7113190e90e883d0006ceaeb866eeb73  gcc/testsuite/rust/compile/issue-3836.rs
  f70238abf05e340d48ee9e6ab5020409  gcc/testsuite/rust/compile/issue-3874.rs
  94a2cfe870fb37b0f022125bd7ab65bf  gcc/testsuite/rust/compile/issue-3876.rs
  34b52236ae1c3de76ae9436257bdb690  gcc/testsuite/rust/compile/issue-3885.rs
+ 608e58447c72c19a5ba9eb55aac478d2  gcc/testsuite/rust/compile/issue-3898.rs
  95ccc1677372d00599c0fc411c72c3c8  gcc/testsuite/rust/compile/issue-3915.rs
  34fad78a84e55b89af8044a8b659a986  gcc/testsuite/rust/compile/issue-3916.rs
+ 5ef50466b281b79b756d304bb2847797  gcc/testsuite/rust/compile/issue-3922.rs
+ 30f649417291a08af7919e5f172ed925  gcc/testsuite/rust/compile/issue-3924.rs
+ 9739ae3375716648c0ef55647edfe0f8  gcc/testsuite/rust/compile/issue-3928.rs
+ 51807f72c769c43c2df60fda6cd31b34  gcc/testsuite/rust/compile/issue-3929-1.rs
+ 48f720cdf5d69153c25fb65830c8125b  gcc/testsuite/rust/compile/issue-3929-2.rs
+ a3bdcdba8bf2415b9ee0895e613614f0  gcc/testsuite/rust/compile/issue-3930.rs
+ 0be83dfcaff3b9905f9e0e15e674b304  gcc/testsuite/rust/compile/issue-3947.rs
+ 4b5155fe83f41293c318a8187d1b5c68  gcc/testsuite/rust/compile/issue-3958.rs
  29c99b4246eb0ef9079be8d65e0eb0c3  gcc/testsuite/rust/compile/issue-3960.rs
+ c6dad6212003d86822c4f3310ff3bffa  gcc/testsuite/rust/compile/issue-3965-1.rs
+ c021443c771857518a064a621fe4002f  gcc/testsuite/rust/compile/issue-3965-2.rs
+ 6f333c9b92dd63189b661de715f2bef6  gcc/testsuite/rust/compile/issue-3966.rs
+ c93fa26f2668b4381f716f05b1e6d0df  gcc/testsuite/rust/compile/issue-3969.rs
+ 60241c6cc63c4504e54468c2ce6c06b6  gcc/testsuite/rust/compile/issue-3974.rs
  d4479cd16fd0fe4348b1bdbfb2f4d527  gcc/testsuite/rust/compile/issue-3978.rs
  b600c0395dbcbda7eda163bb57bf1b72  gcc/testsuite/rust/compile/issue-4006.rs
  89033d8c6cdd3bc5792c06ce52a288f2  gcc/testsuite/rust/compile/issue-402.rs
  b614f59c05840eb45c25f4c6455c316d  gcc/testsuite/rust/compile/issue-407-2.rs
  a96ecff7ebddf1b3d15a3e3eed146c07  gcc/testsuite/rust/compile/issue-407.rs
+ 736a2ee937fe6dba1ca51f9f5c5c9362  gcc/testsuite/rust/compile/issue-4090-1.rs
+ 6a4caad70e136d5944c8be9c0ca1e6fa  gcc/testsuite/rust/compile/issue-4090-2.rs
+ 813e772ce6c019a3e4129348c7561276  gcc/testsuite/rust/compile/issue-4139.rs
+ 992b0482f919976b48b8c59f06198652  gcc/testsuite/rust/compile/issue-4145.rs
+ 192eb2bd0b392ae1910cc848e0324baf  gcc/testsuite/rust/compile/issue-4146.rs
+ 6559995996d8b61db8b4090629e0c41e  gcc/testsuite/rust/compile/issue-4148.rs
+ 9a90a5823b2fac9dbc891be63a808346  gcc/testsuite/rust/compile/issue-4155.rs
+ f84fe23c1ba8b2db0d2401b4fddc498f  gcc/testsuite/rust/compile/issue-4165.rs
+ 295eeee71b2b9b6c1be4c0ad05c1e862  gcc/testsuite/rust/compile/issue-4168.rs
+ f868147efac03c3d68cc22f4e37523f5  gcc/testsuite/rust/compile/issue-4212.rs
+ 581cc0ff9159a5a7b1c18ed81c2264ff  gcc/testsuite/rust/compile/issue-4231.rs
  229b98c45f842adf4958f0a3abd8e500  gcc/testsuite/rust/compile/issue-557.rs
  f8f243df4bb6d8ad64bad3b19771c416  gcc/testsuite/rust/compile/issue-635-1.rs
  4ebac20282b976fe52f1017d59feaccb  gcc/testsuite/rust/compile/issue-635-2.rs
*************** df1b8a97ae68cf8e9eac8408a743fa64  gcc/te
*** 125380,125385 ****
--- 125918,125924 ----
  43dad45281aa225d0529ba4d322586eb  gcc/testsuite/rust/compile/macros/mbe/macro-issue3708.rs
  135abba02ca556e90f3518bbc2322024  gcc/testsuite/rust/compile/macros/mbe/macro-issue3709-1.rs
  ca2dbfd2a07a0ca57a96128dd762d8d5  gcc/testsuite/rust/compile/macros/mbe/macro-issue3709-2.rs
+ ab03a560e812b16e59522dcd2f0dae54  gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs
  bc850c4ba48b08af8788867050a975a6  gcc/testsuite/rust/compile/macros/mbe/macro1.rs
  ac95e4402432bd69656d1ee0d52210ab  gcc/testsuite/rust/compile/macros/mbe/macro10.rs
  43306e2bad2235ff677beff538262cbb  gcc/testsuite/rust/compile/macros/mbe/macro11.rs
*************** e9910f8de2ae3032c9b77fdc6fa16d0c  gcc/te
*** 125422,125428 ****
  8a9c7aa5f77919dfbd071ece74c1ddad  gcc/testsuite/rust/compile/macros/mbe/macro46.rs
  41407bd52a2f99ff811b674df5d2b718  gcc/testsuite/rust/compile/macros/mbe/macro47.rs
  d2bab26b4f2d917ba51ca239028dc234  gcc/testsuite/rust/compile/macros/mbe/macro48.rs
! 68cb5cb50b2cf8ad56c8425848abade9  gcc/testsuite/rust/compile/macros/mbe/macro49.rs
  cea6b447d14844469e6a66daab2ef606  gcc/testsuite/rust/compile/macros/mbe/macro5.rs
  b302559ca62aed1d6bc27155de88c055  gcc/testsuite/rust/compile/macros/mbe/macro50.rs
  9bfa519d74b039a71bf5fe0b4cd8326b  gcc/testsuite/rust/compile/macros/mbe/macro51.rs
--- 125961,125967 ----
  8a9c7aa5f77919dfbd071ece74c1ddad  gcc/testsuite/rust/compile/macros/mbe/macro46.rs
  41407bd52a2f99ff811b674df5d2b718  gcc/testsuite/rust/compile/macros/mbe/macro47.rs
  d2bab26b4f2d917ba51ca239028dc234  gcc/testsuite/rust/compile/macros/mbe/macro48.rs
! fe4af8ff292812b55c264d84b45bce1a  gcc/testsuite/rust/compile/macros/mbe/macro49.rs
  cea6b447d14844469e6a66daab2ef606  gcc/testsuite/rust/compile/macros/mbe/macro5.rs
  b302559ca62aed1d6bc27155de88c055  gcc/testsuite/rust/compile/macros/mbe/macro50.rs
  9bfa519d74b039a71bf5fe0b4cd8326b  gcc/testsuite/rust/compile/macros/mbe/macro51.rs
*************** c14be03a4c0ad9d8d9bb574301accefd  gcc/te
*** 125432,125437 ****
--- 125971,125977 ----
  ca850e23b6b7c81edc9053233d083b47  gcc/testsuite/rust/compile/macros/mbe/macro55.rs
  d1cad6e9a95fe096eb686831198c622f  gcc/testsuite/rust/compile/macros/mbe/macro56.rs
  ad1d9b6db0e590cab45d2df94e6b4774  gcc/testsuite/rust/compile/macros/mbe/macro57.rs
+ e221c65fc7671a329c75c309eb8d84b0  gcc/testsuite/rust/compile/macros/mbe/macro58.rs
  e375367173e252dadfe42d6abd643862  gcc/testsuite/rust/compile/macros/mbe/macro6.rs
  fd673f9260f234aee491e8d2fcc55acd  gcc/testsuite/rust/compile/macros/mbe/macro7.rs
  06bb53602d66838d4c8109b831eeb7db  gcc/testsuite/rust/compile/macros/mbe/macro8.rs
*************** fc9b7d2d4bb9963302a68226e9c08458  gcc/te
*** 125474,125479 ****
--- 126014,126022 ----
  2e43a4d187d7e27aa06e3927e65a583f  gcc/testsuite/rust/compile/match-slicepattern-array.rs
  cfb7e6aa9801425986a22d8e15a8a528  gcc/testsuite/rust/compile/match-slicepattern-slice.rs
  afef148eac95e4333a352ea481e9a27e  gcc/testsuite/rust/compile/match-struct-path.rs
+ fdf4f2b9d47351cc51821aa5cac1085a  gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs
+ 7214233ae105a590c6e5c648d1a538df  gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs
+ 61a8498607376116778cc1f39fcdf462  gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs
  74bb15616e5ded212bf30b18162ffbd8  gcc/testsuite/rust/compile/match-tuplestructpattern.rs
  72c0d2982b1ab36cffb0350603371eca  gcc/testsuite/rust/compile/match1.rs
  1b91ba46251a89048af8618b291df12e  gcc/testsuite/rust/compile/match2.rs
*************** a10eb4517b48647e195976dbe08ce7d3  gcc/te
*** 125549,125557 ****
--- 126092,126102 ----
  6030c60f7b74c803068d451cb9ced7e5  gcc/testsuite/rust/compile/parse_associated_type_as_generic_arg.rs
  090d2f2bf747a624502f3ee033467544  gcc/testsuite/rust/compile/parse_associated_type_as_generic_arg2.rs
  938014f84c9261ed6b113bc617d40919  gcc/testsuite/rust/compile/parse_associated_type_as_generic_arg3.rs
+ 5a6a2e1d5328334fea920eeb7ce95a89  gcc/testsuite/rust/compile/parse_closure_bind.rs
  1bd2c1a4dbfa8382bcaf5f76daa62080  gcc/testsuite/rust/compile/parse_complex_generic_application.rs
  544d5b140c46a68a1b223a58fed49c32  gcc/testsuite/rust/compile/parse_complex_generic_application2.rs
  ac7d528f48d6a84b3e60f20a514d6cf7  gcc/testsuite/rust/compile/parse_empty_tuple_pattern.rs
+ 40079a8e05b34d028238d8927bd7d372  gcc/testsuite/rust/compile/parse_float_dot.rs
  7b85f8417fcc86423cfe4746076018be  gcc/testsuite/rust/compile/parse_generic_path_expr.rs
  37c7aff5159b5715fc8cd7a7745826e1  gcc/testsuite/rust/compile/parse_global_path_generic.rs
  211a4d8d85277f4b17c185612ae9d99e  gcc/testsuite/rust/compile/parse_invalid_specialization.rs
*************** fa1b080c05380ac0134d408be302d780  gcc/te
*** 125567,125572 ****
--- 126112,126118 ----
  d79a8f788f3a9207ed678cbc58ca5c82  gcc/testsuite/rust/compile/pattern-struct.rs
  423d1017eea48611d7e71642d906a3d6  gcc/testsuite/rust/compile/pattern_variadic.rs
  42996b9a980ff76ec1eada1676d8da78  gcc/testsuite/rust/compile/prelude_import.rs
+ 38fa1110c8ad5fec81be79f68e2b5ef6  gcc/testsuite/rust/compile/primitive-import.rs
  daea204ee4a93b0de9f17381a08f8137  gcc/testsuite/rust/compile/privacy1.rs
  4da8baa4cd281d900c7d76ef49e2094f  gcc/testsuite/rust/compile/privacy2.rs
  eba63e34bf4a3d4997147475917fcb15  gcc/testsuite/rust/compile/privacy3.rs
*************** ce60d6c14138123e0c27ee626b14c1b2  gcc/te
*** 125616,125622 ****
  078f0a4edb2fd7624f70f3c53250431f  gcc/testsuite/rust/compile/silly-order-bug.rs
  26a750cf312f91f5f35658b8da415d03  gcc/testsuite/rust/compile/sized-stub.rs
  b9677fdb68fdeadc3f105590b7fe34c9  gcc/testsuite/rust/compile/sizeof-stray-infer-var-bug.rs
! cc55ba48071b2e36726a272bec14ac7e  gcc/testsuite/rust/compile/slice_rest_pattern.rs
  3d9403599fa65b5b6f55bf030e5f937c  gcc/testsuite/rust/compile/slicepattern-size-mismatch.rs
  c76cd68ebcf9bb89b67b55d54a10cee5  gcc/testsuite/rust/compile/specify-crate-name.rs
  f0310c328b1fddc85d5bebedce0cf769  gcc/testsuite/rust/compile/static_var1.rs
--- 126162,126168 ----
  078f0a4edb2fd7624f70f3c53250431f  gcc/testsuite/rust/compile/silly-order-bug.rs
  26a750cf312f91f5f35658b8da415d03  gcc/testsuite/rust/compile/sized-stub.rs
  b9677fdb68fdeadc3f105590b7fe34c9  gcc/testsuite/rust/compile/sizeof-stray-infer-var-bug.rs
! 8db81b3f57fdb3aaac697db6f3cd5442  gcc/testsuite/rust/compile/slice_rest_pattern.rs
  3d9403599fa65b5b6f55bf030e5f937c  gcc/testsuite/rust/compile/slicepattern-size-mismatch.rs
  c76cd68ebcf9bb89b67b55d54a10cee5  gcc/testsuite/rust/compile/specify-crate-name.rs
  f0310c328b1fddc85d5bebedce0cf769  gcc/testsuite/rust/compile/static_var1.rs
*************** e5ba2705e4db9becf9b15f55ae4c2045  gcc/te
*** 125943,125952 ****
--- 126489,126501 ----
  418f71863496e6a7341ca0b843e40f1c  gcc/testsuite/rust/compile/try_block1.rs
  d0dd22fa3a3a512431403c19da377d75  gcc/testsuite/rust/compile/tuple1.rs
  3e11ad929fc91de98602e9b2a827b85c  gcc/testsuite/rust/compile/tuple_float_index.rs
+ 19f5a9f2ca0e23f16b06edd22c250bde  gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs
  59c04689778748d13166c52f19d04f8f  gcc/testsuite/rust/compile/tuple_mismatch.rs
  a1ac7edeb898356a609ab5f448f8106d  gcc/testsuite/rust/compile/tuple_struct1.rs
  3a1197db3bd55512ebf6f3f6c9cc82b4  gcc/testsuite/rust/compile/tuple_struct2.rs
  0b343c17e414c8d5569ccaf48abff3c6  gcc/testsuite/rust/compile/tuple_struct3.rs
+ ffa73f47d2229f341adda66e96732b6f  gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs
+ 8a7025a646eb1e1024bf917d7b472e23  gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs
  5845cf816be4b72d5badd371e2ffba04  gcc/testsuite/rust/compile/tupple_struct_pattern_tuple.rs
  146a99b5e95da275ac9f3aa327f5113f  gcc/testsuite/rust/compile/type-alias1.rs
  872853973f8258921389204e8eadb56b  gcc/testsuite/rust/compile/type-bindings1.rs
*************** f840f4287f5740ac4854b2f4195dbfbe  gcc/te
*** 125975,125980 ****
--- 126524,126532 ----
  7c830dd0a2ec3525c6da4bc67b44f331  gcc/testsuite/rust/compile/unterminated_c_comment.rs
  4be9ad073e00747e5ffe46175988b56e  gcc/testsuite/rust/compile/use_1.rs
  9fc32e79fcf7466f1df1c8e1f5615b56  gcc/testsuite/rust/compile/use_2.rs
+ dfa73aa7120ddff81f720be1afb6d4e8  gcc/testsuite/rust/compile/use_3.rs
+ 9508f3e1b9be217e1163c87013266022  gcc/testsuite/rust/compile/use_self_alone.rs
+ 049d72c9a061c5c318ca8571600ff869  gcc/testsuite/rust/compile/use_self_alone_in_list.rs
  bb66b71d9e02e842378a5f1a6113a4de  gcc/testsuite/rust/compile/usize1.rs
  4ba93adcc306a982a169bf9d8fc0e09c  gcc/testsuite/rust/compile/v0-mangle1.rs
  63dc292fd1579604dc888db846d521f6  gcc/testsuite/rust/compile/v0-mangle2.rs
*************** c7d793e2850d119364ecbefff6f25e6a  gcc/te
*** 125990,125995 ****
--- 126542,126548 ----
  f219c902f8bbb7747064aa57b2247406  gcc/testsuite/rust/compile/xfail/struct_field_vis.rs
  6cac77bead9a159370fe05c2e4be2550  gcc/testsuite/rust/compile/xfail/xfail.exp
  3218ecaec34cb9248c2d6ea5e9a19e62  gcc/testsuite/rust/compile/zero_sized_slice.rs
+ 6409eb53fa7987e4e6d9ea0d348b8d73  gcc/testsuite/rust/core/core.exp
  cf84f07cfe0ecfb071b976dc80fea9b2  gcc/testsuite/rust/debug/chartype.rs
  faa029c0320aae395036255789ed154c  gcc/testsuite/rust/debug/custom_link_section.rs
  2af64fa0368515022042a3fcb6118659  gcc/testsuite/rust/debug/debug.exp
*************** d5d8788f3a670487fb051714384ab2a1  gcc/te
*** 126002,126009 ****
  252f7f8fd334d8f3d2cc69a2b8b31c2e  gcc/testsuite/rust/execute/black_box.rs
  36f6ff07e76f000052781ec6324b4dff  gcc/testsuite/rust/execute/crate-metavar1.rs
  a955f443b22ec1f728412795c6504609  gcc/testsuite/rust/execute/execute.exp
! 8e47a1bc8e9935068eb4dde0883aea17  gcc/testsuite/rust/execute/inline_asm_inout_ident.rs
! ea10404403216cd1d1ddc7a404ac401a  gcc/testsuite/rust/execute/inline_asm_inout_var.rs
  94c13baa4b458105f3e2204c8d4d1e17  gcc/testsuite/rust/execute/torture/arrays.rs
  eca15726fcabf7e7620037e020ee686f  gcc/testsuite/rust/execute/torture/atomic_load.rs
  08a045beac132b26b7d1b09ee02a7bd4  gcc/testsuite/rust/execute/torture/atomic_store.rs
--- 126555,126562 ----
  252f7f8fd334d8f3d2cc69a2b8b31c2e  gcc/testsuite/rust/execute/black_box.rs
  36f6ff07e76f000052781ec6324b4dff  gcc/testsuite/rust/execute/crate-metavar1.rs
  a955f443b22ec1f728412795c6504609  gcc/testsuite/rust/execute/execute.exp
! fdc391d276e1f1fa9f056edffd0476f1  gcc/testsuite/rust/execute/inline_asm_inout_ident.rs
! ec6207f32c715c36caeeb0fa641702a0  gcc/testsuite/rust/execute/inline_asm_inout_var.rs
  94c13baa4b458105f3e2204c8d4d1e17  gcc/testsuite/rust/execute/torture/arrays.rs
  eca15726fcabf7e7620037e020ee686f  gcc/testsuite/rust/execute/torture/atomic_load.rs
  08a045beac132b26b7d1b09ee02a7bd4  gcc/testsuite/rust/execute/torture/atomic_store.rs
*************** f7a4dec5c495bdc2a5580c6b2ff9a054  gcc/te
*** 126110,126116 ****
--- 126663,126671 ----
  449e42630eb5fd571755658ebbb341c4  gcc/testsuite/rust/execute/torture/issue-976.rs
  a7f4a565f46d8c8589434308e7968386  gcc/testsuite/rust/execute/torture/issue-995.rs
  372b5ab0b0565ead0b200dc760731544  gcc/testsuite/rust/execute/torture/iter1.rs
+ 58e6d4e2e10974545dcb38e56ab711d4  gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs
  e5d4fd47103c9b2ec08ec98416082eb9  gcc/testsuite/rust/execute/torture/let-pattern-1.rs
+ 3b24a17a7ebb32561ec8e5ad521f06a0  gcc/testsuite/rust/execute/torture/link-name.rs
  b9e7dd193296598753c75fbfaae447bd  gcc/testsuite/rust/execute/torture/loop-condition-eval.rs
  d7e1088b7c9ae3714d6c9ac6aeb13b18  gcc/testsuite/rust/execute/torture/macro-issue1426.rs
  6fcd51511bc08d2f26a63f6e5ce98020  gcc/testsuite/rust/execute/torture/macro_use1.rs
*************** a162d48d44f2ab3e7366e4fcd9aba1d3  gcc/te
*** 126147,126153 ****
--- 126702,126712 ----
  689951c24d422ee0af8a391bac29de71  gcc/testsuite/rust/execute/torture/match-identifierpattern.rs
  5176a660e070f5219983faf6aade8bb1  gcc/testsuite/rust/execute/torture/match-restpattern-tuple.rs
  6fe41f4e67a073ce971d39a214f170ee  gcc/testsuite/rust/execute/torture/match-slicepattern-array-1.rs
+ 43e59ce9f1f04867d865abddd3a15ef7  gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs
  fc16bd0ec2ec1f434c04a9734eb6cd06  gcc/testsuite/rust/execute/torture/match-slicepattern-slice-1.rs
+ 88931d862a25827c5027910fb0304f1e  gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs
+ 6f6d95c2d72e59c21651b2b47c0809a5  gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs
+ 022d64d0c1de1da93f5e3f5142fc84ed  gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs
  01b927e144874f1d853a6daba14b5212  gcc/testsuite/rust/execute/torture/match-tuplestructpattern.rs
  14d4601e2d037806196aad97cb37c69f  gcc/testsuite/rust/execute/torture/match1.rs
  bc6b669a3a8b1821d1dd4520934053ef  gcc/testsuite/rust/execute/torture/match2.rs
*************** beaa17685ead93eee17f6373d004c4c4  gcc/tr
*** 126394,126400 ****
  75f7536de821e165a3a39bbd1cdfe9d8  gcc/tree-pretty-print.cc
  fd4dd1219acc650a4f7855faa0097964  gcc/tree-pretty-print.h
  7c11aa147a6d02acce5170cb35aed445  gcc/tree-profile.cc
! b11826e48aec543cca8379767ccc052f  gcc/tree-scalar-evolution.cc
  dddd950fe463803c41bc0c7cddf0fe44  gcc/tree-scalar-evolution.h
  b72513bb0f4b53e7bfa5353836a30feb  gcc/tree-sra.cc
  c022e816e38c8f399e6a16163c56d6db  gcc/tree-sra.h
--- 126953,126959 ----
  75f7536de821e165a3a39bbd1cdfe9d8  gcc/tree-pretty-print.cc
  fd4dd1219acc650a4f7855faa0097964  gcc/tree-pretty-print.h
  7c11aa147a6d02acce5170cb35aed445  gcc/tree-profile.cc
! 9a3f079d9aca3a34c2385cad4bb3a4b0  gcc/tree-scalar-evolution.cc
  dddd950fe463803c41bc0c7cddf0fe44  gcc/tree-scalar-evolution.h
  b72513bb0f4b53e7bfa5353836a30feb  gcc/tree-sra.cc
  c022e816e38c8f399e6a16163c56d6db  gcc/tree-sra.h
*************** b9ccca93dfe789389d268eca6dbec62f  gcc/tr
*** 126414,126420 ****
  0046e212ff1b9f3f4d27d055aa299c47  gcc/tree-ssa-dom.h
  6ddd79e7a349847a539144d422bf5a49  gcc/tree-ssa-dse.cc
  a6d83be241a72da1740cf6c5b2ce7d52  gcc/tree-ssa-dse.h
! 14045a15d5320421ac43d76f1df1ad10  gcc/tree-ssa-forwprop.cc
  0915c4bbeb42abdda8799c2b27e5db12  gcc/tree-ssa-ifcombine.cc
  edab16a20512b0146482bb2120696d6a  gcc/tree-ssa-live.cc
  cf4bde43ab3b843eff45bac243d4116d  gcc/tree-ssa-live.h
--- 126973,126979 ----
  0046e212ff1b9f3f4d27d055aa299c47  gcc/tree-ssa-dom.h
  6ddd79e7a349847a539144d422bf5a49  gcc/tree-ssa-dse.cc
  a6d83be241a72da1740cf6c5b2ce7d52  gcc/tree-ssa-dse.h
! 3fc08aeff7beeed6957ee026138427e3  gcc/tree-ssa-forwprop.cc
  0915c4bbeb42abdda8799c2b27e5db12  gcc/tree-ssa-ifcombine.cc
  edab16a20512b0146482bb2120696d6a  gcc/tree-ssa-live.cc
  cf4bde43ab3b843eff45bac243d4116d  gcc/tree-ssa-live.h
*************** ec0ea4b2fca8f29ceacc9fa4130673d0  gcc/tr
*** 126425,126436 ****
  1f70c217ef5bd5f655512b9232754870  gcc/tree-ssa-loop-ivopts.h
  71ebf1f6c8d82b1fdbca6c7aa3bd14cb  gcc/tree-ssa-loop-manip.cc
  fbcc93539b376489c1256eb8cf2d4800  gcc/tree-ssa-loop-manip.h
! 0b91f16e78815f04eee45fba6d85dca0  gcc/tree-ssa-loop-niter.cc
  189317c0b965ddd0ee491f8e45af4b0d  gcc/tree-ssa-loop-niter.h
  523a4b7c5b7113009b3b1f0f514d0cd3  gcc/tree-ssa-loop-prefetch.cc
  00d71257ae0536e64bdea226f1e5ef5f  gcc/tree-ssa-loop-split.cc
  414aadddf1510c47773d045bc3e2800f  gcc/tree-ssa-loop-unswitch.cc
! 2f97e7f187f4f4cce48b71489ef542a0  gcc/tree-ssa-loop.cc
  538146c17730f67ffcc58afdfcc93712  gcc/tree-ssa-loop.h
  422e15102e032e44507602b4d265e573  gcc/tree-ssa-math-opts.cc
  c0b0549adb2c1140cf285901abb5a78c  gcc/tree-ssa-math-opts.h
--- 126984,126995 ----
  1f70c217ef5bd5f655512b9232754870  gcc/tree-ssa-loop-ivopts.h
  71ebf1f6c8d82b1fdbca6c7aa3bd14cb  gcc/tree-ssa-loop-manip.cc
  fbcc93539b376489c1256eb8cf2d4800  gcc/tree-ssa-loop-manip.h
! eac4baefd969552f7f0da3b63cab5bba  gcc/tree-ssa-loop-niter.cc
  189317c0b965ddd0ee491f8e45af4b0d  gcc/tree-ssa-loop-niter.h
  523a4b7c5b7113009b3b1f0f514d0cd3  gcc/tree-ssa-loop-prefetch.cc
  00d71257ae0536e64bdea226f1e5ef5f  gcc/tree-ssa-loop-split.cc
  414aadddf1510c47773d045bc3e2800f  gcc/tree-ssa-loop-unswitch.cc
! 5642645ad7837b2cc3422fa4adf40a37  gcc/tree-ssa-loop.cc
  538146c17730f67ffcc58afdfcc93712  gcc/tree-ssa-loop.h
  422e15102e032e44507602b4d265e573  gcc/tree-ssa-math-opts.cc
  c0b0549adb2c1140cf285901abb5a78c  gcc/tree-ssa-math-opts.h
*************** fbb4dbd95b07fb6744745c6d010a7341  gcc/tr
*** 126443,126449 ****
  ec25a5b6fd6b05135faa83b07eca7e91  gcc/tree-ssa-propagate.h
  128e45b0a401ad495d13d7de1062bd6e  gcc/tree-ssa-reassoc.cc
  258492cd7ef04be49374ea1e670f3b5b  gcc/tree-ssa-reassoc.h
! 117d2a484c92d24ea615d38abecb9f62  gcc/tree-ssa-sccvn.cc
  952cb2484413ce2cf094a52b596dc078  gcc/tree-ssa-sccvn.h
  a27c58eccc3d8929767feb76dc99399f  gcc/tree-ssa-scopedtables.cc
  aa25adbcb019dd38a66ce237df54ae1d  gcc/tree-ssa-scopedtables.h
--- 127002,127008 ----
  ec25a5b6fd6b05135faa83b07eca7e91  gcc/tree-ssa-propagate.h
  128e45b0a401ad495d13d7de1062bd6e  gcc/tree-ssa-reassoc.cc
  258492cd7ef04be49374ea1e670f3b5b  gcc/tree-ssa-reassoc.h
! 0bbbe2a0347f381c92098ba698393a33  gcc/tree-ssa-sccvn.cc
  952cb2484413ce2cf094a52b596dc078  gcc/tree-ssa-sccvn.h
  a27c58eccc3d8929767feb76dc99399f  gcc/tree-ssa-scopedtables.cc
  aa25adbcb019dd38a66ce237df54ae1d  gcc/tree-ssa-scopedtables.h
*************** fbd423299c28bb3b3577ec61aba45439  gcc/tr
*** 126464,126471 ****
  c071186b46f37cd7acd76a679deb3f9d  gcc/tree-ssa-uninit.cc
  0cb7cabeb68ef8727724158e83e6c89e  gcc/tree-ssa.cc
  95d033c8a4bc14c898459494486fd902  gcc/tree-ssa.h
! a158ddca5c4525544dfaae5f1f6e4e1c  gcc/tree-ssanames.cc
! 339bce59375d7679ec019cf010b6bcbc  gcc/tree-ssanames.h
  5fa0d7c6143cd9e39c30840b9996fa30  gcc/tree-stdarg.cc
  9817789b6289e73955015beb57c609b1  gcc/tree-stdarg.h
  af4c63760c432f66b1c6c8e7e7666699  gcc/tree-streamer-in.cc
--- 127023,127030 ----
  c071186b46f37cd7acd76a679deb3f9d  gcc/tree-ssa-uninit.cc
  0cb7cabeb68ef8727724158e83e6c89e  gcc/tree-ssa.cc
  95d033c8a4bc14c898459494486fd902  gcc/tree-ssa.h
! 2325853c2bb97e8a5f81424993ac2cab  gcc/tree-ssanames.cc
! 6ab32249b70e72b4d8b9d4abc134aa6d  gcc/tree-ssanames.h
  5fa0d7c6143cd9e39c30840b9996fa30  gcc/tree-stdarg.cc
  9817789b6289e73955015beb57c609b1  gcc/tree-stdarg.h
  af4c63760c432f66b1c6c8e7e7666699  gcc/tree-streamer-in.cc
*************** fc4b4f80b4c39a4bf73ced787dec927c  gcc/tr
*** 126476,126487 ****
  ebb8ac3717c1bf5db4371da2f3cf6af7  gcc/tree-switch-conversion.h
  c98debbdc978c10e8934f3b4fb7e2504  gcc/tree-tailcall.cc
  6e5dcb1a1ea95d85fd88114bca11a78a  gcc/tree-vect-data-refs.cc
! 5d8bb0df796ceea958fd65c5aedb5bce  gcc/tree-vect-generic.cc
! f840a486e62fde7baf6f487e0c0912bb  gcc/tree-vect-loop-manip.cc
  7808985af23240ed3f8b9165d8a70946  gcc/tree-vect-loop.cc
  04a82f888445c931e0ace82b02b3230b  gcc/tree-vect-patterns.cc
! f0e64752211e2caf975148f28e7b4caf  gcc/tree-vect-slp-patterns.cc
! 216acb496de32b4dbaf3a62bfdcc514c  gcc/tree-vect-slp.cc
  eaef715b393a023fab053a3f3b478097  gcc/tree-vect-stmts.cc
  c8efeee600d612c4bae8dda4bd45ee54  gcc/tree-vector-builder.cc
  258611ff1e83cc7680e8c9f033499665  gcc/tree-vector-builder.h
--- 127035,127046 ----
  ebb8ac3717c1bf5db4371da2f3cf6af7  gcc/tree-switch-conversion.h
  c98debbdc978c10e8934f3b4fb7e2504  gcc/tree-tailcall.cc
  6e5dcb1a1ea95d85fd88114bca11a78a  gcc/tree-vect-data-refs.cc
! 57d12d2c747f6be0d70a875abae6c3e3  gcc/tree-vect-generic.cc
! 68f9460ebe49ce21a4b55cb0b0357ac0  gcc/tree-vect-loop-manip.cc
  7808985af23240ed3f8b9165d8a70946  gcc/tree-vect-loop.cc
  04a82f888445c931e0ace82b02b3230b  gcc/tree-vect-patterns.cc
! 588899232babed9c67e61795ff405608  gcc/tree-vect-slp-patterns.cc
! f1a62b3eef5c42402f69bc4866422997  gcc/tree-vect-slp.cc
  eaef715b393a023fab053a3f3b478097  gcc/tree-vect-stmts.cc
  c8efeee600d612c4bae8dda4bd45ee54  gcc/tree-vector-builder.cc
  258611ff1e83cc7680e8c9f033499665  gcc/tree-vector-builder.h
*************** cd4e6196ea1c7eb134b4d7cbadb9dcb3  gcc/va
*** 126523,126529 ****
  db99ee82ab71b58820d60f9863e62aac  gcc/var-tracking.cc
  63e6a64533514c36d9e6e1bd510a2c21  gcc/varasm.cc
  69f8e035a8548037bc8c8f7f854253c4  gcc/varasm.h
! e96ee31ef62fd5574909f9328fb29af9  gcc/varpool.cc
  5958f38d462c8e23023f7b272b8b969c  gcc/vec-perm-indices.cc
  d9c4840a497d0e1f2063865edafe6e97  gcc/vec-perm-indices.h
  49e92de0554d55d6fb8db9734d0f76d1  gcc/vec.cc
--- 127082,127088 ----
  db99ee82ab71b58820d60f9863e62aac  gcc/var-tracking.cc
  63e6a64533514c36d9e6e1bd510a2c21  gcc/varasm.cc
  69f8e035a8548037bc8c8f7f854253c4  gcc/varasm.h
! 2f869cb153fe0c8c605d1271668c9d45  gcc/varpool.cc
  5958f38d462c8e23023f7b272b8b969c  gcc/vec-perm-indices.cc
  d9c4840a497d0e1f2063865edafe6e97  gcc/vec-perm-indices.h
  49e92de0554d55d6fb8db9734d0f76d1  gcc/vec.cc
*************** f017ba40c4699f1549cd341ad688007f  libgcc
*** 128916,128922 ****
  804399bda5c6c23cd3e0cd78c21bc2fd  libgcc/vtv_end_preinit.c
  407de23229097d9b9a4d00e2e9c60c70  libgcc/vtv_start.c
  ba13e8c1385837f9a736ead153be6251  libgcc/vtv_start_preinit.c
! 8dad3111905a20866f3a65b045de9e3e  libgcobol/ChangeLog
  b227feb8ac8df349788743a8ade3e840  libgcobol/LICENSE
  f9f96109d649d17aa66f416364289e35  libgcobol/Makefile.am
  ce6793d8276df5edf60e0c25b277c4b4  libgcobol/Makefile.in
--- 129475,129481 ----
  804399bda5c6c23cd3e0cd78c21bc2fd  libgcc/vtv_end_preinit.c
  407de23229097d9b9a4d00e2e9c60c70  libgcc/vtv_start.c
  ba13e8c1385837f9a736ead153be6251  libgcc/vtv_start_preinit.c
! bbadee5fb34f36b93025894a9db020bf  libgcobol/ChangeLog
  b227feb8ac8df349788743a8ade3e840  libgcobol/LICENSE
  f9f96109d649d17aa66f416364289e35  libgcobol/Makefile.am
  ce6793d8276df5edf60e0c25b277c4b4  libgcobol/Makefile.in
*************** feda976b2ecc3ba909f736aeb43feb48  libgco
*** 128955,128961 ****
  179156ad95afd403a9316969a95142f7  libgcobol/stringbin.h
  22c49caac6a8d133de67b63e2cd769d4  libgcobol/valconv.cc
  bf52fdaed06effba57a10e8157bc6930  libgcobol/valconv.h
! c37e1eaa544154df2818d5a9cb35d6bc  libgcobol/xmlparse.cc
  6520ed01bbed88782faed4ce1922e024  libgfortran/ChangeLog
  d99469a76bfe825683f8d94fe07b508c  libgfortran/ChangeLog-2002
  522fdb2df6cefe6bcaed3c7c7311eae1  libgfortran/ChangeLog-2003
--- 129514,129520 ----
  179156ad95afd403a9316969a95142f7  libgcobol/stringbin.h
  22c49caac6a8d133de67b63e2cd769d4  libgcobol/valconv.cc
  bf52fdaed06effba57a10e8157bc6930  libgcobol/valconv.h
! e3cbddb33236e6676f4b7be4e400a795  libgcobol/xmlparse.cc
  6520ed01bbed88782faed4ce1922e024  libgfortran/ChangeLog
  d99469a76bfe825683f8d94fe07b508c  libgfortran/ChangeLog-2002
  522fdb2df6cefe6bcaed3c7c7311eae1  libgfortran/ChangeLog-2003
*************** a3a7e9ca6057da9ca42e03e41e1c73f7  libgo/
*** 135519,135525 ****
  dcdf1b680b15b372bdb64cc5107d51b6  libgo/testsuite/libgo-test-support.exp.in
  bf162aa572f7b96b25dbd2b027845d32  libgo/testsuite/libgo.testmain/testmain.exp
  cc9d2a0e34e31ba866a8caf9f46f48f3  libgomp/.gitattributes
! d099e9f994b2ec90f5a78502c5a57856  libgomp/ChangeLog
  0d55aa862aee66efdc5f8d62c94ff8fb  libgomp/ChangeLog.graphite
  714e3b9c0810a61df01246c2a97e825a  libgomp/Makefile.am
  3c91d539fc9934b5095923265d09ec8f  libgomp/Makefile.in
--- 136078,136084 ----
  dcdf1b680b15b372bdb64cc5107d51b6  libgo/testsuite/libgo-test-support.exp.in
  bf162aa572f7b96b25dbd2b027845d32  libgo/testsuite/libgo.testmain/testmain.exp
  cc9d2a0e34e31ba866a8caf9f46f48f3  libgomp/.gitattributes
! ee183e649fd42fc682208aaa40fbeb25  libgomp/ChangeLog
  0d55aa862aee66efdc5f8d62c94ff8fb  libgomp/ChangeLog.graphite
  714e3b9c0810a61df01246c2a97e825a  libgomp/Makefile.am
  3c91d539fc9934b5095923265d09ec8f  libgomp/Makefile.in
*************** af41d1d04a4112345554ca8b8a072ed9  libgom
*** 135649,135655 ****
  250e49a5865485507899765bf69913a0  libgomp/configure.ac
  0eb9aa41c92e30c6fb1494575b1c8daa  libgomp/configure.tgt
  bdbd19a4ded46698d600a262cfc20343  libgomp/critical.c
! 8b0ce7c0a49c71670812fee324284192  libgomp/env.c
  de6d218010cbf7859c6b94615b21f35a  libgomp/error.c
  d98fb492b4e4c1c04a41a6bc6433de2b  libgomp/fortran.c
  7f54b43cb86dd02741d33a360f1dbbe2  libgomp/hashtab.h
--- 136208,136214 ----
  250e49a5865485507899765bf69913a0  libgomp/configure.ac
  0eb9aa41c92e30c6fb1494575b1c8daa  libgomp/configure.tgt
  bdbd19a4ded46698d600a262cfc20343  libgomp/critical.c
! 4dc278a7fdb55d723893cf791ea57169  libgomp/env.c
  de6d218010cbf7859c6b94615b21f35a  libgomp/error.c
  d98fb492b4e4c1c04a41a6bc6433de2b  libgomp/fortran.c
  7f54b43cb86dd02741d33a360f1dbbe2  libgomp/hashtab.h
*************** e8a3245c095430c8ef2413afe2ee4c48  libgom
*** 138301,138307 ****
  1d2e2e1ab9f0d92351625f2c5661dbb8  libgomp/testsuite/libgomp.oacc-fortran/update-dt-array.f90
  989e6535f20045be32e9e91643a0b08f  libgomp/testsuite/libgomp.oacc-fortran/vector-routine.f90
  9b8b2dd0e3a57784ab6771591edb6c3b  libgomp/work.c
! 52e3bd1986d2034786048b6cf001cf2a  libgrust/ChangeLog
  e61ce18b1a86e6764b3436d0638ec4d2  libgrust/Makefile.am
  4d65d186378f0d15c49ae12508c6f970  libgrust/Makefile.in
  721420f55c97c79b3d7ecacfc67a0714  libgrust/aclocal.m4
--- 138860,138866 ----
  1d2e2e1ab9f0d92351625f2c5661dbb8  libgomp/testsuite/libgomp.oacc-fortran/update-dt-array.f90
  989e6535f20045be32e9e91643a0b08f  libgomp/testsuite/libgomp.oacc-fortran/vector-routine.f90
  9b8b2dd0e3a57784ab6771591edb6c3b  libgomp/work.c
! 4397542ba8ad9c91b633edadaf661961  libgrust/ChangeLog
  e61ce18b1a86e6764b3436d0638ec4d2  libgrust/Makefile.am
  4d65d186378f0d15c49ae12508c6f970  libgrust/Makefile.in
  721420f55c97c79b3d7ecacfc67a0714  libgrust/aclocal.m4
*************** d41d8cd98f00b204e9800998ecf8427e  libgru
*** 138316,138322 ****
  d46e74a82de14dbc715373e35f96f887  libgrust/libformat_parser/generic_format_parser/Cargo.toml
  4e430c3e81671de7622b56885413e152  libgrust/libformat_parser/generic_format_parser/src/lib.rs
  5b8c4f2c68e7e368ebf5dfe691f123cc  libgrust/libformat_parser/src/bin.rs
! 0bb7db29ef9484901df9c8432f3111be  libgrust/libformat_parser/src/lib.rs
  5de0997e16db9a44190def85f9f13dfb  libgrust/libformat_parser/vendor.NOTES
  52049d8cbe8ad32f775d60e1735bbc8a  libgrust/libformat_parser/vendor/libc/.cargo-checksum.json
  51dc481112b59ff0e0e202e0ce38fe9a  libgrust/libformat_parser/vendor/libc/CONTRIBUTING.md
--- 138875,138881 ----
  d46e74a82de14dbc715373e35f96f887  libgrust/libformat_parser/generic_format_parser/Cargo.toml
  4e430c3e81671de7622b56885413e152  libgrust/libformat_parser/generic_format_parser/src/lib.rs
  5b8c4f2c68e7e368ebf5dfe691f123cc  libgrust/libformat_parser/src/bin.rs
! 8e702412da53963585d8f7bc36ea7267  libgrust/libformat_parser/src/lib.rs
  5de0997e16db9a44190def85f9f13dfb  libgrust/libformat_parser/vendor.NOTES
  52049d8cbe8ad32f775d60e1735bbc8a  libgrust/libformat_parser/vendor/libc/.cargo-checksum.json
  51dc481112b59ff0e0e202e0ce38fe9a  libgrust/libformat_parser/vendor/libc/CONTRIBUTING.md
*************** c446d3459d2c18f8c3b7e9523a64042e  libgru
*** 138609,138614 ****
--- 139168,139618 ----
  c3634c948119513d0f58255c48992ca2  libgrust/libproc_macro_internal/tokenstream.h
  7c20b6718d183fdde5dfb2d8af4aec23  libgrust/libproc_macro_internal/tokentree.cc
  4d27195db5805ea05b982a2971711c94  libgrust/libproc_macro_internal/tokentree.h
+ 22a53954e4e0ec258dfce4391e905dac  libgrust/rustc-lib/LICENSE-APACHE
+ b377b220f43d747efdec40d69fcaa69d  libgrust/rustc-lib/LICENSE-MIT
+ ff613b023fb29e5882e0d88acddaae7d  libgrust/rustc-lib/core/Cargo.toml
+ e3c178b58c85a74db5d3f5cd5b5e44bf  libgrust/rustc-lib/core/benches/any.rs
+ 0a268c711c4dc4d970f6e66974807416  libgrust/rustc-lib/core/benches/ascii.rs
+ c057fb481a15854538c25c77a4339179  libgrust/rustc-lib/core/benches/ascii/is_ascii.rs
+ c7674a643af6c62183b5d673b179263d  libgrust/rustc-lib/core/benches/char/methods.rs
+ 0e93470a2c6386cfc7d97cc82ca7c9bf  libgrust/rustc-lib/core/benches/char/mod.rs
+ 6f28ef7e24d9a2a68ae6b99816b0700e  libgrust/rustc-lib/core/benches/fmt.rs
+ 314a5bba8baf056cb77c90a8fe0cc2c2  libgrust/rustc-lib/core/benches/hash/mod.rs
+ 43190d834201c04ac5dccdf60fc8bf7b  libgrust/rustc-lib/core/benches/hash/sip.rs
+ 12985f329acc9bc46ca81814fe4491d5  libgrust/rustc-lib/core/benches/iter.rs
+ 363f5b7a9845f76b2222b849ef8dae78  libgrust/rustc-lib/core/benches/lib.rs
+ 996482e19f6df9edec3322a58483a302  libgrust/rustc-lib/core/benches/num/dec2flt/mod.rs
+ 054071c399f7b1f3fc1c5701885c66d1  libgrust/rustc-lib/core/benches/num/flt2dec/mod.rs
+ 5e5893f18c55ae40760ccf94b35212ab  libgrust/rustc-lib/core/benches/num/flt2dec/strategy/dragon.rs
+ b341f4a1a184a6204d0d9f64c77c531c  libgrust/rustc-lib/core/benches/num/flt2dec/strategy/grisu.rs
+ 8f61b869f068d554d8e46f29f372d9e7  libgrust/rustc-lib/core/benches/num/mod.rs
+ bd8eac8cfb50829c815769345489ef8d  libgrust/rustc-lib/core/benches/ops.rs
+ f72b62322d90486d6790bf2b4777a70a  libgrust/rustc-lib/core/benches/pattern.rs
+ 26d358f572253719a1a16b70ff39d882  libgrust/rustc-lib/core/benches/slice.rs
+ 4292b1ff731089b946266dca13260fd6  libgrust/rustc-lib/core/src/alloc/global.rs
+ f5bc2189674425151d27a3ecbf1cdd35  libgrust/rustc-lib/core/src/alloc/layout.rs
+ 8fb299c8da0b704b24f9180bb93c1549  libgrust/rustc-lib/core/src/alloc/mod.rs
+ 849af563b7f3603eebd06e04fc6d82a4  libgrust/rustc-lib/core/src/any.rs
+ 8ad1f3de019faa1b63e0199b5ff66b78  libgrust/rustc-lib/core/src/array/iter.rs
+ a6d681b12ab40a9a542ba78f54fbb5ac  libgrust/rustc-lib/core/src/array/mod.rs
+ 831209d6d3874dbd7f1b524390084178  libgrust/rustc-lib/core/src/ascii.rs
+ 208b8ad6ea5f8d7aac03af8e863579b0  libgrust/rustc-lib/core/src/bool.rs
+ 0f344b91650a735041dbc20ade2e0f72  libgrust/rustc-lib/core/src/borrow.rs
+ 6c1b694a0ba87821867ec0babfb2f7eb  libgrust/rustc-lib/core/src/cell.rs
+ 970263ff2bea26ee57ae2ba631143a91  libgrust/rustc-lib/core/src/char/convert.rs
+ f6a482b1453975be5baf913dfe3bed71  libgrust/rustc-lib/core/src/char/decode.rs
+ 503a6e5ed48e3328b7574ebf203364f9  libgrust/rustc-lib/core/src/char/methods.rs
+ ff783edb157b66761beccb74c95c189d  libgrust/rustc-lib/core/src/char/mod.rs
+ ac8d71a1ea6619659fbd99e3ca3df933  libgrust/rustc-lib/core/src/clone.rs
+ 57bd45807ecbb6290b513bf3d34ba7f1  libgrust/rustc-lib/core/src/cmp.rs
+ 169b8674df1758bab7bd822a53d5b187  libgrust/rustc-lib/core/src/convert/mod.rs
+ 0701f2b47fedbb1a64d3b77cc6155832  libgrust/rustc-lib/core/src/convert/num.rs
+ f72b3a4969d3998cf7732f2a4a518abd  libgrust/rustc-lib/core/src/default.rs
+ 14087c3d44f3354550c3c8ce63623fab  libgrust/rustc-lib/core/src/ffi.rs
+ 4c37f9e2af02de65dbf37c9014c2fba8  libgrust/rustc-lib/core/src/fmt/builders.rs
+ 4e9fba9db4a3bd1ba91bd856966493b4  libgrust/rustc-lib/core/src/fmt/float.rs
+ 8383a2f1b977481a5e40ad3226309813  libgrust/rustc-lib/core/src/fmt/mod.rs
+ 7951d16ca52785c539c4c2c829418c58  libgrust/rustc-lib/core/src/fmt/num.rs
+ 303d571f6ce6dcdb32ba01f797e1523c  libgrust/rustc-lib/core/src/fmt/rt/v1.rs
+ 346dfc03c1743e09bc5003da9b92d8cd  libgrust/rustc-lib/core/src/future/future.rs
+ e51f6a39dacd2a5dbe97885065898906  libgrust/rustc-lib/core/src/future/into_future.rs
+ f4323d9b964dd60ed2b0a50fcd11d962  libgrust/rustc-lib/core/src/future/mod.rs
+ 7ea315c4fba1f9be19b28d4809124f7f  libgrust/rustc-lib/core/src/future/pending.rs
+ 4f19cce0065887edb225662001b2f9d6  libgrust/rustc-lib/core/src/future/poll_fn.rs
+ bd0e152c29af8b248a1f6ed8866ae487  libgrust/rustc-lib/core/src/future/ready.rs
+ ab50f9c92193125c5609724d261c1ebb  libgrust/rustc-lib/core/src/hash/mod.rs
+ d12c185bb78dc2f1add0137fa4e0f1bf  libgrust/rustc-lib/core/src/hash/sip.rs
+ 7d98876a74ab56d91ea54c537ec9a84f  libgrust/rustc-lib/core/src/hint.rs
+ 19e7cd64f36dfce31ae7708aef53e184  libgrust/rustc-lib/core/src/internal_macros.rs
+ b53a02ce6b8b693f340d3cc526067597  libgrust/rustc-lib/core/src/intrinsics.rs
+ 93dbab8d03ecf492e107f1e1bf2695a0  libgrust/rustc-lib/core/src/iter/adapters/chain.rs
+ 201d6ba373ea72762192c0c7fb9f7820  libgrust/rustc-lib/core/src/iter/adapters/flatten.rs
+ c6035f3dd2c7e912ca32a5439df3f19c  libgrust/rustc-lib/core/src/iter/adapters/fuse.rs
+ 3e35e1b0d819c267b5b719cf88efe169  libgrust/rustc-lib/core/src/iter/adapters/mod.rs
+ d6b2b707ceac682117643bbfc15b79c0  libgrust/rustc-lib/core/src/iter/adapters/zip.rs
+ eaf326a2621a0c3c16eb2393c04fbeac  libgrust/rustc-lib/core/src/iter/mod.rs
+ 9483e436ab6c8b11f7d613e75292a323  libgrust/rustc-lib/core/src/iter/range.rs
+ d4fca886810dc4822d2854a98025124c  libgrust/rustc-lib/core/src/iter/sources.rs
+ 8d6d3359cea4f565271413105db5b30c  libgrust/rustc-lib/core/src/iter/traits/accum.rs
+ 3854390627f76d1db63c99cc13806055  libgrust/rustc-lib/core/src/iter/traits/collect.rs
+ d6fbcd0359acd52b16a35add52a47006  libgrust/rustc-lib/core/src/iter/traits/double_ended.rs
+ d52370cc7fd0c784854969d8751faabe  libgrust/rustc-lib/core/src/iter/traits/exact_size.rs
+ 2246b2ab1d200c5d629e18f1378650cb  libgrust/rustc-lib/core/src/iter/traits/iterator.rs
+ 391a8f3a9745289e1fdf665b63f983a0  libgrust/rustc-lib/core/src/iter/traits/marker.rs
+ e082de025de2135d416b07032a3b755a  libgrust/rustc-lib/core/src/iter/traits/mod.rs
+ 26673cd69b214763fc247e4c85d0deb7  libgrust/rustc-lib/core/src/lazy.rs
+ b8cf382a69ec7375d3efdf59b0a39054  libgrust/rustc-lib/core/src/lib.rs
+ ead8e07287cc34a89a7b9431b09054f8  libgrust/rustc-lib/core/src/macros/mod.rs
+ 94d9d105c25bc240b06ef3227f0b4ade  libgrust/rustc-lib/core/src/macros/panic.md
+ cba66d1e738accce8ce177e2b6d5c5ea  libgrust/rustc-lib/core/src/marker.rs
+ 1ebb77b55900bbb941b074f7b36dbdc1  libgrust/rustc-lib/core/src/mem/manually_drop.rs
+ 300aed6867bd15c76b87b5d536a83ced  libgrust/rustc-lib/core/src/mem/maybe_uninit.rs
+ dbfa04d8c7d483c7e53a23f06e2071ce  libgrust/rustc-lib/core/src/mem/mod.rs
+ 6aef62b62597a3dd8821967cb65e0d3c  libgrust/rustc-lib/core/src/num/bignum.rs
+ b2fb043b45e7637488258d0ef038d0ab  libgrust/rustc-lib/core/src/num/dec2flt/algorithm.rs
+ f674ae35097b59670de51a699e6ddbc2  libgrust/rustc-lib/core/src/num/dec2flt/mod.rs
+ e9951816bd5e318fdda54ee1f98fb7f0  libgrust/rustc-lib/core/src/num/dec2flt/num.rs
+ df301976a00844eadda9f5d01a9004e6  libgrust/rustc-lib/core/src/num/dec2flt/parse.rs
+ fdc791badb46181f6d29b248a274a82f  libgrust/rustc-lib/core/src/num/dec2flt/rawfp.rs
+ 1f16823da1a50cc2ff00305f9c3c863b  libgrust/rustc-lib/core/src/num/dec2flt/table.rs
+ 425d3bccd4dfad60dde1aebe9a98aa84  libgrust/rustc-lib/core/src/num/diy_float.rs
+ e1f128b5d14293546222f03c5fcf2653  libgrust/rustc-lib/core/src/num/error.rs
+ 598d5d85534872b661e0093754adff05  libgrust/rustc-lib/core/src/num/f32.rs
+ 4e66f15b390b7e20a75e8fa818ee293e  libgrust/rustc-lib/core/src/num/f64.rs
+ df8b34c92d873ea4b81b503686098f26  libgrust/rustc-lib/core/src/num/flt2dec/decoder.rs
+ e878d63299bfe95fcfdd6ab394eb43f6  libgrust/rustc-lib/core/src/num/flt2dec/estimator.rs
+ 18041332405d9b84492c3b8436aa4395  libgrust/rustc-lib/core/src/num/flt2dec/mod.rs
+ 18c590832852d6fb217dfaf031f5b74a  libgrust/rustc-lib/core/src/num/flt2dec/strategy/dragon.rs
+ 6463c37aebce099dc1167b4ef21c0f40  libgrust/rustc-lib/core/src/num/flt2dec/strategy/grisu.rs
+ 16cd40b4992086a36b6c14d5b93b4af5  libgrust/rustc-lib/core/src/num/int_macros.rs
+ bd1e954a4be48e4671ea8f8addd5bba8  libgrust/rustc-lib/core/src/num/mod.rs
+ 9690ee935df7aa81854618b290294215  libgrust/rustc-lib/core/src/num/nonzero.rs
+ 84788aca098df425d6cd3d74efebae3d  libgrust/rustc-lib/core/src/num/shells/i128.rs
+ 3acaf9965b6241c5f1c070146acccc43  libgrust/rustc-lib/core/src/num/shells/i16.rs
+ adc247d512b397780353e87de798884e  libgrust/rustc-lib/core/src/num/shells/i32.rs
+ 613305699a5821ecaddfb6aaaf35a7b1  libgrust/rustc-lib/core/src/num/shells/i64.rs
+ 62aed5642e936fd6c9115ade3f18a77e  libgrust/rustc-lib/core/src/num/shells/i8.rs
+ e1b1746124aa3fc41308a7a20d0f6864  libgrust/rustc-lib/core/src/num/shells/int_macros.rs
+ 011dc5fdb61968558f87091053287a31  libgrust/rustc-lib/core/src/num/shells/isize.rs
+ b60aafa25c7627cdaa6711bec68513fa  libgrust/rustc-lib/core/src/num/shells/u128.rs
+ 2fbe7a3a955fac19971981eeb4f331da  libgrust/rustc-lib/core/src/num/shells/u16.rs
+ d0e585062b7637889a8662750e114975  libgrust/rustc-lib/core/src/num/shells/u32.rs
+ 9b971d81eeb79b17a2e2c1c1cc16b134  libgrust/rustc-lib/core/src/num/shells/u64.rs
+ f24189b40970f5a1e2dde55e18c91356  libgrust/rustc-lib/core/src/num/shells/u8.rs
+ 59e9fff76644c198e2e83ed8c8ff7b1b  libgrust/rustc-lib/core/src/num/shells/usize.rs
+ 4ae28f9a1e4cd0bf998b529f229e6973  libgrust/rustc-lib/core/src/num/uint_macros.rs
+ 7360aa5b88aeba5e01151d9194a35faa  libgrust/rustc-lib/core/src/num/wrapping.rs
+ 06ad3b24a5552b7324fc4580f3116982  libgrust/rustc-lib/core/src/ops/arith.rs
+ e6ff7c7d630b4dee0a8f3cdb86b7cf4d  libgrust/rustc-lib/core/src/ops/bit.rs
+ c098a509eb62def5923eafbfc8d5a5ee  libgrust/rustc-lib/core/src/ops/control_flow.rs
+ 412f18312e796f991f0807727b132401  libgrust/rustc-lib/core/src/ops/deref.rs
+ 47074dbcd293130c908bbbd1bf081499  libgrust/rustc-lib/core/src/ops/drop.rs
+ e7b2206724943b8a8140f7c1065997a3  libgrust/rustc-lib/core/src/ops/function.rs
+ f341a7fcaca03efcc0140473f726918d  libgrust/rustc-lib/core/src/ops/generator.rs
+ cb222b9879d34c13c2afafc5fad5eebb  libgrust/rustc-lib/core/src/ops/index.rs
+ 17b08cbd7c6a5bc58ba94ed5a622dbed  libgrust/rustc-lib/core/src/ops/mod.rs
+ ae54f124f7c7d75598c374f58c7d96b6  libgrust/rustc-lib/core/src/ops/range.rs
+ 8ea26b19fa3b0379436999a7ee04da88  libgrust/rustc-lib/core/src/ops/try.rs
+ 280a6cc8db548a73002d5672ad8e08a9  libgrust/rustc-lib/core/src/ops/unsize.rs
+ 7127e19d96b7d0abbf43e911a446d373  libgrust/rustc-lib/core/src/option.rs
+ e93ac26f37637cb6f5cbb00cf20629a8  libgrust/rustc-lib/core/src/panic.rs
+ d805035fae4ee56fe348cc2945235915  libgrust/rustc-lib/core/src/panicking.rs
+ 6d0fb4387975e0dcee486d04d909f772  libgrust/rustc-lib/core/src/pin.rs
+ ed414d64f06310640a08d4569cde4e04  libgrust/rustc-lib/core/src/prelude/mod.rs
+ 488e111a892fae3be4185b12d9800de3  libgrust/rustc-lib/core/src/prelude/v1.rs
+ ecd3208162cfda9b6e107768a2356c04  libgrust/rustc-lib/core/src/primitive.rs
+ 51dc75f7789168a1bcd46f16dcedd354  libgrust/rustc-lib/core/src/ptr/const_ptr.rs
+ bf70e18d158273dc8de1d85e0ec8a93c  libgrust/rustc-lib/core/src/ptr/mod.rs
+ dda9ae18bb6549b620716f0659a0f2af  libgrust/rustc-lib/core/src/ptr/mut_ptr.rs
+ 6f668d2b15cd51a533d11eee138a93b9  libgrust/rustc-lib/core/src/ptr/non_null.rs
+ a83acd9c3d0e6cc1331d6a0f78f4f2e9  libgrust/rustc-lib/core/src/ptr/unique.rs
+ acdf832b9a2e066b668a962ef3e53c27  libgrust/rustc-lib/core/src/raw.rs
+ bd3620ada0bcd222363f4d29ed22ad0c  libgrust/rustc-lib/core/src/result.rs
+ 444c14e8ed1573a963cd0f440538c9fb  libgrust/rustc-lib/core/src/slice/ascii.rs
+ fe0ecbce493b6bf143b008ca63972f34  libgrust/rustc-lib/core/src/slice/cmp.rs
+ 05d32fa54efed7351250bd83b0024732  libgrust/rustc-lib/core/src/slice/index.rs
+ 098ecf4640e22848d7a2a781fc081fd0  libgrust/rustc-lib/core/src/slice/iter.rs
+ 266ebb44ab377576d1a98b8489d2e376  libgrust/rustc-lib/core/src/slice/iter/macros.rs
+ 4ab7bdbb159299735fa28454d25dbd33  libgrust/rustc-lib/core/src/slice/memchr.rs
+ b8358067513c2480eba93643db4e5200  libgrust/rustc-lib/core/src/slice/mod.rs
+ d0e9b17e0227fbf23a77d5fac39af89d  libgrust/rustc-lib/core/src/slice/raw.rs
+ 81b52a6354fe06603ad811f81dbbceeb  libgrust/rustc-lib/core/src/slice/rotate.rs
+ 0a8860fd8db39cc2725272c4b16fcbdd  libgrust/rustc-lib/core/src/slice/sort.rs
+ f82be904785ecfb1a0d2d1c924e850f2  libgrust/rustc-lib/core/src/str/converts.rs
+ f800ca81e4cf864086f15bce676422b6  libgrust/rustc-lib/core/src/str/error.rs
+ e93a79f926bd9b9db8ede1568d080add  libgrust/rustc-lib/core/src/str/iter.rs
+ ca6f121ffd72adaee44536f1646fd38e  libgrust/rustc-lib/core/src/str/lossy.rs
+ 34cfeda1b67ab45b9fdf81a5abeae482  libgrust/rustc-lib/core/src/str/mod.rs
+ 77c5fdacb174bd1fc03ea319385dc2f2  libgrust/rustc-lib/core/src/str/pattern.rs
+ 3b697248333519e13151d770feb6eae5  libgrust/rustc-lib/core/src/str/traits.rs
+ 805ed4c29da848f65f0affc2dd1a2618  libgrust/rustc-lib/core/src/str/validations.rs
+ a702c232b5011972cc264ef7f32694ec  libgrust/rustc-lib/core/src/sync/atomic.rs
+ 36d239143c5973526cee9a1b13efd84b  libgrust/rustc-lib/core/src/sync/mod.rs
+ 05af6806f7665724936b2009544f30f0  libgrust/rustc-lib/core/src/task/mod.rs
+ cd5ddb25543bfa16e5da8528371b035b  libgrust/rustc-lib/core/src/task/poll.rs
+ 1114e8f8ddab426441626d29c5ff8b21  libgrust/rustc-lib/core/src/task/ready.rs
+ b6166f2d8de857987e613fc6f9e3184d  libgrust/rustc-lib/core/src/task/wake.rs
+ 73ad6c385fd086387e90fafcf86949cc  libgrust/rustc-lib/core/src/time.rs
+ 28ab65aa4153df2bc22ed17789c235dd  libgrust/rustc-lib/core/src/tuple.rs
+ 388bfce250f8289b9ab9d96b9ccbb007  libgrust/rustc-lib/core/src/unicode/mod.rs
+ 67cb6090f02fc9b10cdeae530d88e083  libgrust/rustc-lib/core/src/unicode/printable.py
+ d293ad70e086cb54fad81eb1f1c38b76  libgrust/rustc-lib/core/src/unicode/printable.rs
+ 3d3286da2cf669ad7fdbae2442cd3321  libgrust/rustc-lib/core/src/unicode/unicode_data.rs
+ 2ec6bdb7e32f5a91e9ce29c3ae0abd1c  libgrust/rustc-lib/core/src/unit.rs
+ 4ae10e8f7c780c626fcfcae4ab72429a  libgrust/rustc-lib/core/tests/alloc.rs
+ a1ba8a8b2bcbc1c0fa6be82f7cfd8d98  libgrust/rustc-lib/core/tests/any.rs
+ f2e084a160689549e663b71cadbffb5f  libgrust/rustc-lib/core/tests/array.rs
+ 6105ed6a6e83795acd73469d221e7a5f  libgrust/rustc-lib/core/tests/ascii.rs
+ 41f146d3b4b3dffc695eff82436d6b3f  libgrust/rustc-lib/core/tests/atomic.rs
+ aabb0e9acd4c9545b91fee936530e355  libgrust/rustc-lib/core/tests/bool.rs
+ 29a1294885bea47ac49a5ad4178d37e1  libgrust/rustc-lib/core/tests/cell.rs
+ 9e4cd0afe9e647dc911a6f38ce059ee2  libgrust/rustc-lib/core/tests/char.rs
+ 72fe975a274ab29643e6f0bd0f255526  libgrust/rustc-lib/core/tests/clone.rs
+ c499d112d43a6ea40a4f7a6e9ec67252  libgrust/rustc-lib/core/tests/cmp.rs
+ 7b10c9de2151859c83fa827554db318b  libgrust/rustc-lib/core/tests/fmt/builders.rs
+ 86c2a7372f037e0c865255b24850368e  libgrust/rustc-lib/core/tests/fmt/float.rs
+ bd8d2bd7b5420da72bd37f938264c330  libgrust/rustc-lib/core/tests/fmt/mod.rs
+ 72e0cee3f8856db4215f2ac2b1192297  libgrust/rustc-lib/core/tests/fmt/num.rs
+ 5636828dc334b576cee15738469d604b  libgrust/rustc-lib/core/tests/hash/mod.rs
+ 6cfda38e0a8deb26095915835f84a85b  libgrust/rustc-lib/core/tests/hash/sip.rs
+ 932cdaed2b159e083c30c5cdf0ad28a5  libgrust/rustc-lib/core/tests/intrinsics.rs
+ 0146a599d85c3f48eaa67d5d7f418174  libgrust/rustc-lib/core/tests/iter.rs
+ 2c1025baad66c62336d663375190c655  libgrust/rustc-lib/core/tests/lazy.rs
+ b04c0215d0f55710112bd5aefba0597a  libgrust/rustc-lib/core/tests/lib.rs
+ 6a0fb4bb3cd6b8578696abb658172acd  libgrust/rustc-lib/core/tests/manually_drop.rs
+ 771a88c2990d49c119de9744498f615f  libgrust/rustc-lib/core/tests/mem.rs
+ d55a522d87190455b0ed8d8846b70c7d  libgrust/rustc-lib/core/tests/nonzero.rs
+ cdc8f57ea8fc921632df24100999c60f  libgrust/rustc-lib/core/tests/num/bignum.rs
+ 1ae0998b0aae3f832114b69b7d489a36  libgrust/rustc-lib/core/tests/num/dec2flt/mod.rs
+ fe7a2749b893306ae231acf09d6e869a  libgrust/rustc-lib/core/tests/num/dec2flt/parse.rs
+ be713dbb2f3e8210616ba3362bfd8211  libgrust/rustc-lib/core/tests/num/dec2flt/rawfp.rs
+ fe4d20eccd78c2c149927f253b002f46  libgrust/rustc-lib/core/tests/num/flt2dec/estimator.rs
+ 298ee728e2d7b1a8c62d22629af9425f  libgrust/rustc-lib/core/tests/num/flt2dec/mod.rs
+ 0813657b212fc8677ecf2c32be0abcaa  libgrust/rustc-lib/core/tests/num/flt2dec/random.rs
+ d905a099e9bc3c21f25ee014fa4fbe99  libgrust/rustc-lib/core/tests/num/flt2dec/strategy/dragon.rs
+ 58a3d360ccec59120548b78ac65e902d  libgrust/rustc-lib/core/tests/num/flt2dec/strategy/grisu.rs
+ 8a7d4ade2af795ab4ee2bd2e8e89a1a8  libgrust/rustc-lib/core/tests/num/i16.rs
+ 378ca0d5f9aa4d1d6ea12f0ab149e2b5  libgrust/rustc-lib/core/tests/num/i32.rs
+ 8199ecb35f8c012c686f18539c412e6c  libgrust/rustc-lib/core/tests/num/i64.rs
+ ef3e4aecabed7a9eb1886183d5fa1286  libgrust/rustc-lib/core/tests/num/i8.rs
+ 7e3275c0faec893457c6a686e0eac1b9  libgrust/rustc-lib/core/tests/num/int_macros.rs
+ 3bdf92c3c9942860850edb8cd0705491  libgrust/rustc-lib/core/tests/num/mod.rs
+ ec3a4e8e7fbcb27657ea9b30b44de3a8  libgrust/rustc-lib/core/tests/num/nan.rs
+ 40a1d373d3fcf1f71e458e2ef5e77627  libgrust/rustc-lib/core/tests/num/u16.rs
+ 8bb810b986647faab38940ae977ce012  libgrust/rustc-lib/core/tests/num/u32.rs
+ 84ca7028a9df94a3321a6747c09935c2  libgrust/rustc-lib/core/tests/num/u64.rs
+ 9c084319cc0d227331a19ba0f5fd595a  libgrust/rustc-lib/core/tests/num/u8.rs
+ 4d919cb16dd928941c58bf56bb0fed5f  libgrust/rustc-lib/core/tests/num/uint_macros.rs
+ 0be1774d2f5b6a35a83e8ba1bb4c0d28  libgrust/rustc-lib/core/tests/num/wrapping.rs
+ 26ccc6436fb88b88521e095552979e1f  libgrust/rustc-lib/core/tests/ops.rs
+ b2e1ede7a51b0486f3d2a824aeb96fab  libgrust/rustc-lib/core/tests/option.rs
+ d21f64fe8310b8e2d0a9ff5cc7a554e1  libgrust/rustc-lib/core/tests/pattern.rs
+ dc9a7fcc402cdb13af15896830898adc  libgrust/rustc-lib/core/tests/pin.rs
+ 27932e99ff7fd667968ea01c73abbbd6  libgrust/rustc-lib/core/tests/ptr.rs
+ 5b8d34e42e4a418e4f71306586aa1c3c  libgrust/rustc-lib/core/tests/result.rs
+ 3ebafe376b496ebe6cc00b9877552abc  libgrust/rustc-lib/core/tests/slice.rs
+ 9ba1f52ce325e7230b9b359004233bc6  libgrust/rustc-lib/core/tests/str.rs
+ dd7f2e99b67da47174154edf00b58849  libgrust/rustc-lib/core/tests/str_lossy.rs
+ 87c94bd80250f78f2752206a7fd70179  libgrust/rustc-lib/core/tests/task.rs
+ bb6a0fd99e3e7eb028176778d2f0e5f6  libgrust/rustc-lib/core/tests/time.rs
+ 62f928aa90acc6be8fb408ef589627ad  libgrust/rustc-lib/core/tests/tuple.rs
+ 39e8f87d6cb99aa0981ccb603603a0d6  libgrust/rustc-lib/stdarch/.cirrus.yml
+ 5662d14ec121234763cc983c6d79d655  libgrust/rustc-lib/stdarch/.github/workflows/main.yml
+ d9b3acfb58274e5b8c1a33f355622659  libgrust/rustc-lib/stdarch/.gitignore
+ 5636c3cbfe8dba989735343dd4224ca6  libgrust/rustc-lib/stdarch/CONTRIBUTING.md
+ fe3532310218e2ce28c700a6966ac70a  libgrust/rustc-lib/stdarch/Cargo.toml
+ 1836efb2eb779966696f473ee8540542  libgrust/rustc-lib/stdarch/LICENSE-APACHE
+ c63582cd30ce8fb1e644659e900d5433  libgrust/rustc-lib/stdarch/LICENSE-MIT
+ c94c263eead91a9b0749c737dac6c777  libgrust/rustc-lib/stdarch/README.md
+ 3de88f98d532e59a2ced29dace4de474  libgrust/rustc-lib/stdarch/ci/android-install-ndk.sh
+ c398a5014a07c0c49fa4ad8c984c156e  libgrust/rustc-lib/stdarch/ci/android-install-sdk.sh
+ b9699210a19ea1b1f6292b6cd9d4e7e6  libgrust/rustc-lib/stdarch/ci/android-sysimage.sh
+ ba4d4a9db881d4225c1ac9c1130bcd26  libgrust/rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile
+ 3fc8bdf94723db226f80d8f7adb5a708  libgrust/rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
+ 7c41a09ec540e4bc0997832945eb1fdd  libgrust/rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile
+ 3e84fc34d4fba8d82743af8bf98ead71  libgrust/rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile
+ be78cc77bb3702dfb37dd19b222b5997  libgrust/rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile
+ 23355cd4ab7179d635a3815ce53e5f39  libgrust/rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile
+ 23355cd4ab7179d635a3815ce53e5f39  libgrust/rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile
+ 4328e629403e86bef252b47e58eb8eda  libgrust/rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile
+ ace5473567d7c48909f2a1fc68648186  libgrust/rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile
+ 732e75a801a252e72d7b6ced075cfbc3  libgrust/rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile
+ ee37cbf7626599740c55921af70b8322  libgrust/rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile
+ 9ece5ad81c03ab1ed561ecabf2232d6b  libgrust/rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile
+ 587a6270650cf9c5025256bda4a7a824  libgrust/rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile
+ 572e2d72383ac5b4436a3625853c44a4  libgrust/rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile
+ 65a88e5380c1fbfdb0051f3791a0013c  libgrust/rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile
+ 720295414d93ff538b7ea915f5abfcaa  libgrust/rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile
+ 73484ed80a5e8ee2100601ba2f6f5b77  libgrust/rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile
+ 91274e350591f8232af2f0500310edfd  libgrust/rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile
+ 9b487cf8e894c3bdc469bbe634720f7d  libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile
+ f982c6ee0e1dc6af057301df057736ca  libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
+ 45809ebd1b92c62cb5ac57e331fa48ea  libgrust/rustc-lib/stdarch/ci/dox.sh
+ a65895b68d2039d007be3bd0fe985cb7  libgrust/rustc-lib/stdarch/ci/gba.json
+ ceb55ee77c7e89a126e7176a775752ee  libgrust/rustc-lib/stdarch/ci/run-docker.sh
+ 39faa92b23cd84c99791c4764074d45b  libgrust/rustc-lib/stdarch/ci/run.sh
+ 0d27985ee25a982604924f8b81eaf427  libgrust/rustc-lib/stdarch/ci/runtest-android.rs
+ 8ab7256ba56c105e106d08b98823c0af  libgrust/rustc-lib/stdarch/ci/style.sh
+ 65be562ce972311be63e025398ea90b2  libgrust/rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml
+ 337fb7764460cd45addb6587631046dc  libgrust/rustc-lib/stdarch/crates/assert-instr-macro/build.rs
+ 0f2dac42401c7f2f817cadcde563f14e  libgrust/rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs
+ c79647fe755c34ce2c67c97721d6c75d  libgrust/rustc-lib/stdarch/crates/core_arch/Cargo.toml
+ 1836efb2eb779966696f473ee8540542  libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE
+ c63582cd30ce8fb1e644659e900d5433  libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-MIT
+ 217a7234bf23641e2984d99ae2671510  libgrust/rustc-lib/stdarch/crates/core_arch/README.md
+ 68af5894c6bdb8e846372d2256b98096  libgrust/rustc-lib/stdarch/crates/core_arch/avx512f.md
+ 15c9bb63bc3d96adb70ecce051401cf5  libgrust/rustc-lib/stdarch/crates/core_arch/build.rs
+ 7732030ceddd670dbfc7e20e0f9e7f93  libgrust/rustc-lib/stdarch/crates/core_arch/rustfmt.toml
+ 66a5cd4874d019e5f8243b6b67b45815  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs
+ 8d17d83a5726495f7d58f8d21bde379d  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs
+ cbfc65aaf9199530598695f449636aff  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs
+ e461c74b5d0598f70de65a256ebba46f  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+ 936c07a5919d620459832ff41ea63ab7  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs
+ 90db0fb4da5cc93af1ccb284ad75eba9  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs
+ 8de7988db0f99b9275cf36c3361aca26  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs
+ 63640a80ce219fce129bbcf848be8423  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs
+ 59f43527cdc705daab72636c19be9366  libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs
+ 6651ec33dc000fbaf64fc2175bb2636b  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs
+ eb8304a2d1dbf86fe1d67bf600c80890  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs
+ b7ed28cbe898c26bf7d87675b75985fb  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs
+ 38741640253caca53f1690f51be00a57  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs
+ 32781b612f6fa85a951020e1e0a3dca5  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs
+ 04203500f934cbb399f405605d1b8667  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs
+ 47ca85f57dbde166f0e5d9fd410d2b86  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs
+ 5174dd81610bffa4eabd6a0d628d86fe  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs
+ 826cd3184a988ef8e624e61b6fdf1058  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs
+ ada96102f57a57dbc14a2481adc6299f  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs
+ 821dfbbd5933c7ddc47d217285c2f0de  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs
+ c8255b58b04ddbc5ba8fa10498e648aa  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs
+ 0ef272cea90dd3899299b9f9dad8c8ab  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs
+ 709999efbb8a02ed22235eb2aade25ec  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs
+ a0776dc53cd677e96e5df54e31b42778  libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs
+ bab46738c27c05e123c83669256a61d8  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs
+ 3e5f0e718bf007f25e768f21104fdab0  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs
+ b668df6f1c1cf6b216c9263911a1d8b9  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs
+ d8c78dd8127d2bd3fce377088c9acc1b  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs
+ f446b1ba5454e8796d7099b6aea548f3  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs
+ 180660fd7be01c28a740dea569f96133  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs
+ e55b1bb73730306f0ac70bac2ff27d50  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs
+ 24fc94d1f641915a26ea91f805c3b686  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v6.rs
+ 775b864a98b69748322c04ead500872c  libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v7.rs
+ 9c917a30672780d61801a82c762e94e5  libgrust/rustc-lib/stdarch/crates/core_arch/src/core_arch_docs.md
+ 6717d2a2ab31fce7d5745bfec7fe8d74  libgrust/rustc-lib/stdarch/crates/core_arch/src/lib.rs
+ 763ec531842e32f22b9ccdd7c8ad2fcd  libgrust/rustc-lib/stdarch/crates/core_arch/src/macros.rs
+ c0444839c4f0ed612efe2aa6ef0ce29f  libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/mod.rs
+ c1a54a4602b5cba23932a81668395354  libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa.rs
+ b5107d5a1e3b2e260c6faff1b491e4d3  libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa/macros.rs
+ 5e866d5c8dc4a13ee7e4fbd2c7b177b6  libgrust/rustc-lib/stdarch/crates/core_arch/src/mod.rs
+ 652c4801b80d1f14fee4196d4b0078cd  libgrust/rustc-lib/stdarch/crates/core_arch/src/nvptx/mod.rs
+ 3cf1c35bd6b484be81dcbf8b6a2139e1  libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/altivec.rs
+ bdc39c5c00c3d700199723b9f72a83e3  libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/mod.rs
+ 7cfbc3568e46d1b7c0c325c938440814  libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/vsx.rs
+ c280d6713cc8efafd7486840c3fa8668  libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc64/mod.rs
+ 01a6146e5ff69a8a2f5d69d8045a8d16  libgrust/rustc-lib/stdarch/crates/core_arch/src/simd.rs
+ 2682d401b50e48023295defe960e7480  libgrust/rustc-lib/stdarch/crates/core_arch/src/simd_llvm.rs
+ ccad3a7577d29f3ba2a4152f49241316  libgrust/rustc-lib/stdarch/crates/core_arch/src/v64.rs
+ ec4cadd9ef2a2501d7413e26af8a3ef9  libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/atomic.rs
+ 39f27963888127b58367d7071a8141d3  libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/memory.rs
+ 18a82f777442529cebf806f586bcf086  libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/mod.rs
+ f5f6713e8755a5ceb4c0db9ebd95227f  libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/simd128.rs
+ 6bb92848ef63646300630fd51cc52c60  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/abm.rs
+ 2c58fdc71b31d8123026eea5d63cf935  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/adx.rs
+ 0d23dd94d8963297741b8b1e89cef655  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/aes.rs
+ eda99a9659c58c494d9ed1bb682a32b6  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx.rs
+ 840956cce7aefcacb263931821f9d5e5  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx2.rs
+ 572c11fde03fbdd83c8dd4f6836a43cc  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512f.rs
+ ff11ae0195ea08b5667d4a286cac3006  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs
+ 91484378051bfa5c0cfba80812368c62  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi1.rs
+ 7474d5c8886f27edf72fb0e9b5478c56  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi2.rs
+ f17dc2b020c2ecce14345204124c35f3  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bswap.rs
+ f9e314a56e2dc2b9c1d84feb4609ede1  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bt.rs
+ 5073f4498e9f449c31666f9b2e1cd242  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/cpuid.rs
+ be00bc7e843c2a777c75f2a8e6837703  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/eflags.rs
+ 7add315bc46ab6f5558c3062833c330c  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/f16c.rs
+ e2f3df807b42e8040566487b09d2940b  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fma.rs
+ 39debef1eccf710507680ade3992a4f6  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fxsr.rs
+ 589443b5133390c96b5b109666d009a7  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/macros.rs
+ ee56727910b3a9635b1816ccf4c3fd7c  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/mod.rs
+ 95f59affd1eb9581a6ce2e8f8ea8acf9  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/pclmulqdq.rs
+ e4da44cd8f0d027b14d32b8dcb1ff9ad  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdrand.rs
+ 52474dd9f9e8d6cd11ae412794a83dda  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdtsc.rs
+ 7edb68003a9b54dda3281e1dbe577390  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rtm.rs
+ 1d00ce2a4c9a2ad7b60b73846f2f5685  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sha.rs
+ b893ff77c66767b985366e89ed23356d  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse.rs
+ a360ee3a6fc1b65c36d35f2c319031c4  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse2.rs
+ 70b02dd55f31a1d6eec261c342c6ca9a  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse3.rs
+ b83eb69235a2e2cfd711166c3c12f6f2  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse41.rs
+ b5dda9a3893f4550ae089aeda587571d  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse42.rs
+ 9103dd1366ba37edb18b3a3bac6a8f80  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse4a.rs
+ e8b7df62b82786cf60ac055c86704602  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs
+ 3bb9b2158b3775392c2ea8a027ecfeaf  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs
+ 3993be6319f7d6a561ce1934c07f5903  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/test.rs
+ 83d49df1f4003e09ce4f67d127be458a  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/xsave.rs
+ 6cd067b2c762810e31d53e9490ae4d79  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs
+ 67349bc5b03194fd2b30b35a1bcf082c  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/adx.rs
+ 548c151c0d5ed691551d5664e1e809cc  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs
+ 7bf63e63f3ff75af0a93d70eb79e365d  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx2.rs
+ d2e0e797edea81b4fbe2e6512cfcb63b  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs
+ 8f409c9e0273ebd60c3aed32c817c464  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs
+ 7661e2fb068091a593c133aa1b00dfad  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs
+ 71c60289ddbfb61662760169d8548547  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs
+ 41ab85e4b0fc61c1d6a403a365b6efad  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs
+ a042b91171d7bf242f125e49082481dd  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs
+ 499797348920f7241f78dfb49b65eb39  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs
+ 917db03baaa26dd885c7260000fc8fed  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs
+ b10996bb06f7c9c4c31e06c7e443ee89  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs
+ 35de891f60c53b9d38ecedc365d4cc22  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs
+ d11ead85cc953345699055a258cbcd25  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse2.rs
+ 595e003ab2df4a417441d639527bbb84  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs
+ c8d442974c2eb4788cd79cb9e17ee1f3  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs
+ 51b01956f595df2b117a2c453b373917  libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs
+ acecf6f4a5547d88c71eb9396cfbff52  libgrust/rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs
+ ad80ef87e3e08e71e8c183d92d342bc9  libgrust/rustc-lib/stdarch/crates/simd-test-macro/Cargo.toml
+ e294905f637618ad12ea049b16341cf8  libgrust/rustc-lib/stdarch/crates/simd-test-macro/src/lib.rs
+ b267feb038a25a95bdf7d8c76983cc3c  libgrust/rustc-lib/stdarch/crates/std_detect/Cargo.toml
+ 1836efb2eb779966696f473ee8540542  libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-APACHE
+ c63582cd30ce8fb1e644659e900d5433  libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-MIT
+ 94dd9b519ccdb191d575f6f0840a8cc4  libgrust/rustc-lib/stdarch/crates/std_detect/README.md
+ 7d80a56514436de3ee4dd34927aa8fc7  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs
+ b8048b2b91e727d8dafc45f3d36734da  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/arm.rs
+ b0f3182c39a9ae674f3e926f5af85fd2  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs
+ 9b51ec16ea3ea0a39b3624446cbf6309  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs
+ 83841d031e1fae86db2eac2d0a4f89ac  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs
+ 6a5ce9291ee3c2b4dee7cedf0e1cb7e5  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs
+ b3e2b39827df24eb89d311f0b103e0fd  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs
+ 97f514e92e5a636970c2845c1a74c7c0  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs
+ 1f46a996f7cb4eee96a283657d0ae932  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs
+ 3431fa9c3c292778e4a95661fe9fd426  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs
+ cf0445feccdb6801b8ad25229631afaa  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs
+ e03d88564fbd67afd25a31c2a4196f6b  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs
+ d011afd23a3b9ffd141157b299d50a8d  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs
+ b7cb9a2426326d541f2943b6fd7d1f77  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs
+ efba972a27992b457d8b2c51b1c755a9  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs
+ 3f5ba2caf2629f7d471ed4f3b559d7ec  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs
+ 0b8794c1355cc8925e2a9c7215f89a22  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs
+ a5ad10b4334c6b517e17f76b6d3de14d  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs
+ c6fa0174a697fd2cfd0eef967da44a32  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs
+ eb1122be726f6355d446f73ddd55426d  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs
+ 613e02b1abd85f5d1f42d9644412266c  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs
+ 4be7d82cc046e0e28b3b2863dff6a366  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs
+ 8e974f8a2baf945038dde5026b7d388e  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs
+ 3f860be38ad4efb2396b2c503d740453  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs
+ d68dea4767a7c05cb505177f4902f49c  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs
+ 41cecb5cc50f55fc52596b0728680aef  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs
+ 2c11eaf4a27f4ae34a6e8c7396977652  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs
+ 5c1f2b965db5e7fa1bfbe2d6ef1bd00b  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs
+ 640969bf1f979d99b2fa39dee063c6ae  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv
+ 392b5fc6de117084070d557df6ab50d3  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-x64-i7-6850k.auxv
+ 26f63aaaead9e1d06a055dcd151dd326  libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv
+ d3579eebd3fe55b2547dafb447188edd  libgrust/rustc-lib/stdarch/crates/std_detect/src/lib.rs
+ 29a94dfcb446103b4dcb4a0630a15c4c  libgrust/rustc-lib/stdarch/crates/std_detect/src/mod.rs
+ 5684560f2f150b3180b561e55bce70b4  libgrust/rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs
+ 58381af1ede8ea33b81e0d1082fec192  libgrust/rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs
+ 7564bc40c0ffc87e51072d18003247ee  libgrust/rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs
+ c5fb6562d3d0cf908377a21a4553a623  libgrust/rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml
+ ec54df374b3589ca81bd022211641fca  libgrust/rustc-lib/stdarch/crates/stdarch-gen/README.md
+ 838314a08e8903ba5a88096c5dfb9fff  libgrust/rustc-lib/stdarch/crates/stdarch-gen/neon.spec
+ a9b0b73f9730202fbac71a9bc5e1a0ea  libgrust/rustc-lib/stdarch/crates/stdarch-gen/src/main.rs
+ d360e527c2a645395623deb19012041b  libgrust/rustc-lib/stdarch/crates/stdarch-test/Cargo.toml
+ c24a7697656dea74bfca3a5531c9dc41  libgrust/rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs
+ ca1e45a573d373dcb13bb79831dec9b8  libgrust/rustc-lib/stdarch/crates/stdarch-test/src/lib.rs
+ e506f9c8939b863152c49c60f40e9689  libgrust/rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs
+ 39888d36a1cbd23d4bf5192b26804e3a  libgrust/rustc-lib/stdarch/crates/stdarch-verify/.gitattributes
+ 6ce9ca31f8d8633990f24d5140843d70  libgrust/rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml
+ 69f73c020db60d58f1ddaf17bd703959  libgrust/rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html
+ 0e26d225c722735f9172cdb942df4469  libgrust/rustc-lib/stdarch/crates/stdarch-verify/build.rs
+ 39e645b2d02cf3f54c41923ffbb941d5  libgrust/rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h
+ 05a1f6510c868d299acf6c1bf1bd33a0  libgrust/rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs
+ 2b63d4309851bfc584a833049ce2ef79  libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs
+ d493ed0f8d0b948161e8644ac3187950  libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs
+ bcbfe4252c8ea613579fa9c3eacec0c1  libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs
+ 9bf10797870612c8a6d5d1264254a8de  libgrust/rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml
+ b4884283bab95158a603eebee635a7f0  libgrust/rustc-lib/stdarch/examples/Cargo.toml
+ d1c33a8b5e0f3d9a19ffe583f8e72f56  libgrust/rustc-lib/stdarch/examples/hex.rs
+ 1dad0f581d8f157df08da55bdd5393e7  libgrust/rustc-lib/stdarch/examples/wasm.rs
+ 187462b06a35e0e4d6fdb0f22ad39817  libgrust/rustc-lib/stdarch/triagebot.toml
+ 68562b202746f3330f030d8da94e78eb  libgrust/rustc-lib/stdarch/vendor.yml
+ c21183b1df7f7afb240d765035277db1  libgrust/rustc-lib/version-info
  99c2e5e712b990ee07be10f53e41f3fb  libiberty/.gitignore
  a916467b91076e631dd8edb7424769c7  libiberty/COPYING.LIB
  9d555625ec32f4f8ac536b5e9cc8098d  libiberty/ChangeLog
*************** d680e7307fb59fe24f8431e179191f16  libssp
*** 140607,140613 ****
  534c3fb4a88e5c1f70db35c12b7742c3  libssp/vsnprintf-chk.c
  34daeb04a522ee796098df4446d6ce61  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! 4f340cb0553e8e3e545eaff87dc4b073  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
--- 141611,141617 ----
  534c3fb4a88e5c1f70db35c12b7742c3  libssp/vsnprintf-chk.c
  34daeb04a522ee796098df4446d6ce61  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! 0a2e1785527933d722e219b480cf0122  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
*************** b6d83aa40f63760f6b5a58810aabfae9  libstd
*** 141366,141372 ****
  1d1c887295c693bce1fe28dc004684af  libstdc++-v3/include/bits/ranges_util.h
  222a1067e3c63fb19ed0996234a84884  libstdc++-v3/include/bits/refwrap.h
  5b95e35539d0071176396cd82a6072b7  libstdc++-v3/include/bits/regex.h
! b5ae25c0469c7fb23c0914fcebced654  libstdc++-v3/include/bits/regex.tcc
  8574b29ef7f78afa13942ca1525502d5  libstdc++-v3/include/bits/regex_automaton.h
  1a5c4b076e644644ecb038a6c2e76ca3  libstdc++-v3/include/bits/regex_automaton.tcc
  880962cfcb3932b3a277cfa83a2cd955  libstdc++-v3/include/bits/regex_compiler.h
--- 142370,142376 ----
  1d1c887295c693bce1fe28dc004684af  libstdc++-v3/include/bits/ranges_util.h
  222a1067e3c63fb19ed0996234a84884  libstdc++-v3/include/bits/refwrap.h
  5b95e35539d0071176396cd82a6072b7  libstdc++-v3/include/bits/regex.h
! d0ff506cfa0d3f2d14ebceb08faac4dd  libstdc++-v3/include/bits/regex.tcc
  8574b29ef7f78afa13942ca1525502d5  libstdc++-v3/include/bits/regex_automaton.h
  1a5c4b076e644644ecb038a6c2e76ca3  libstdc++-v3/include/bits/regex_automaton.tcc
  880962cfcb3932b3a277cfa83a2cd955  libstdc++-v3/include/bits/regex_compiler.h
*************** b1d749b2cc7775f0628c7d0c25d7d95e  libstd
*** 141431,141444 ****
  cb099c347fbdf946e779aed229ce490a  libstdc++-v3/include/bits/unordered_set.h
  a29de34311f884bb0a7bb8854fe4ce34  libstdc++-v3/include/bits/uses_allocator.h
  b9489856439b8ba5238cd45b2f65370a  libstdc++-v3/include/bits/uses_allocator_args.h
! dba47031679780cdbde61e6e83854035  libstdc++-v3/include/bits/utility.h
  a462fb6c466b34fa25624b7fab6323e3  libstdc++-v3/include/bits/valarray_after.h
! a229b5c8ad2904a3b3173239225596c4  libstdc++-v3/include/bits/valarray_array.h
  3ddbcccf58411251c2825ae41b697844  libstdc++-v3/include/bits/valarray_array.tcc
  a4c99020fc6d28e94d24a3f60a71b6ec  libstdc++-v3/include/bits/valarray_before.h
  6adf2ccea897e9d5fc8e7650eceac96f  libstdc++-v3/include/bits/vector.tcc
! c8ed4dd1823de639d469ab2d591170e9  libstdc++-v3/include/bits/version.def
! 6857bbb75fc262ffe484082f2b7ee3b9  libstdc++-v3/include/bits/version.h
  602b081d70553843ef4511ca8ec803c9  libstdc++-v3/include/bits/version.tpl
  6ccd70c0c36dd38ba559c1fc5a05fbd0  libstdc++-v3/include/c/cassert
  c31b54f25b2f8c7ca3ca3eec930d4e1d  libstdc++-v3/include/c/cctype
--- 142435,142448 ----
  cb099c347fbdf946e779aed229ce490a  libstdc++-v3/include/bits/unordered_set.h
  a29de34311f884bb0a7bb8854fe4ce34  libstdc++-v3/include/bits/uses_allocator.h
  b9489856439b8ba5238cd45b2f65370a  libstdc++-v3/include/bits/uses_allocator_args.h
! ab592fcc2ea11f10c6822a826d63d5ec  libstdc++-v3/include/bits/utility.h
  a462fb6c466b34fa25624b7fab6323e3  libstdc++-v3/include/bits/valarray_after.h
! f82756dba1eb6b3ea0ca4d3ed0da3773  libstdc++-v3/include/bits/valarray_array.h
  3ddbcccf58411251c2825ae41b697844  libstdc++-v3/include/bits/valarray_array.tcc
  a4c99020fc6d28e94d24a3f60a71b6ec  libstdc++-v3/include/bits/valarray_before.h
  6adf2ccea897e9d5fc8e7650eceac96f  libstdc++-v3/include/bits/vector.tcc
! 8608a7a394e026d5dbc7329380f89f45  libstdc++-v3/include/bits/version.def
! fc91e5b811fd1b5700aeeb013bbcc23e  libstdc++-v3/include/bits/version.h
  602b081d70553843ef4511ca8ec803c9  libstdc++-v3/include/bits/version.tpl
  6ccd70c0c36dd38ba559c1fc5a05fbd0  libstdc++-v3/include/c/cassert
  c31b54f25b2f8c7ca3ca3eec930d4e1d  libstdc++-v3/include/c/cctype
*************** ba14be3c6ffe74b2ec997245d3a94e3d  libstd
*** 142036,142042 ****
  553e2f4fd74c3e0258a774ab683470fd  libstdc++-v3/include/std/random
  83e2be1a27094f36ebe067f1b410258f  libstdc++-v3/include/std/ranges
  a28bf4bed6789b61535d4b05ff48ba76  libstdc++-v3/include/std/ratio
! 400d95a1fd416911b5c47562d7a586cf  libstdc++-v3/include/std/regex
  1bad2aed72c4537e7f08d24c1bf7d375  libstdc++-v3/include/std/scoped_allocator
  91c6fab351369373bcb191b27bc13900  libstdc++-v3/include/std/semaphore
  9b8d5c4868a64371c6591ccd2d8ae5f0  libstdc++-v3/include/std/set
--- 143040,143046 ----
  553e2f4fd74c3e0258a774ab683470fd  libstdc++-v3/include/std/random
  83e2be1a27094f36ebe067f1b410258f  libstdc++-v3/include/std/ranges
  a28bf4bed6789b61535d4b05ff48ba76  libstdc++-v3/include/std/ratio
! 7d864de507d428ace2b6886ab9bb2610  libstdc++-v3/include/std/regex
  1bad2aed72c4537e7f08d24c1bf7d375  libstdc++-v3/include/std/scoped_allocator
  91c6fab351369373bcb191b27bc13900  libstdc++-v3/include/std/semaphore
  9b8d5c4868a64371c6591ccd2d8ae5f0  libstdc++-v3/include/std/set
*************** b9cf79d1edae688927d40109f321047a  libstd
*** 142057,142069 ****
  21988a8b4bf87b01fc566fe8659ab2cc  libstdc++-v3/include/std/system_error
  608edef7344e2e25c7b00170df6fa9e6  libstdc++-v3/include/std/text_encoding
  0ed8103f880c65d72326076bb36a84d2  libstdc++-v3/include/std/thread
! 2edc4f11cac1e8041949b063fc20d943  libstdc++-v3/include/std/tuple
! 5ea768fa6c707d59799120d2c8762c2a  libstdc++-v3/include/std/type_traits
  237682577d22ec3f9f5046abf0acd8e7  libstdc++-v3/include/std/typeindex
  520c52362f53e18f20838693cfd131bf  libstdc++-v3/include/std/unordered_map
  c82be32edefaa23cc1228b092d319315  libstdc++-v3/include/std/unordered_set
  667666c43061458376aeaee7dfc78a59  libstdc++-v3/include/std/utility
! e0096e013b19127692d1ed454892142d  libstdc++-v3/include/std/valarray
  6dfedd974a960950b7ce23a1bbb999f2  libstdc++-v3/include/std/variant
  e6dcc9a7721cf0dd849d0c48a2f1768a  libstdc++-v3/include/std/vector
  1c10633087657ad7a31f6c3569a3ebe0  libstdc++-v3/include/std/version
--- 143061,143073 ----
  21988a8b4bf87b01fc566fe8659ab2cc  libstdc++-v3/include/std/system_error
  608edef7344e2e25c7b00170df6fa9e6  libstdc++-v3/include/std/text_encoding
  0ed8103f880c65d72326076bb36a84d2  libstdc++-v3/include/std/thread
! 8456c84295d4d092b0b55a359845078d  libstdc++-v3/include/std/tuple
! 5d4f004889a4f12ced42e3559d06fef4  libstdc++-v3/include/std/type_traits
  237682577d22ec3f9f5046abf0acd8e7  libstdc++-v3/include/std/typeindex
  520c52362f53e18f20838693cfd131bf  libstdc++-v3/include/std/unordered_map
  c82be32edefaa23cc1228b092d319315  libstdc++-v3/include/std/unordered_set
  667666c43061458376aeaee7dfc78a59  libstdc++-v3/include/std/utility
! 14c64f3107d654e98e9cad7d2b1a2bac  libstdc++-v3/include/std/valarray
  6dfedd974a960950b7ce23a1bbb999f2  libstdc++-v3/include/std/variant
  e6dcc9a7721cf0dd849d0c48a2f1768a  libstdc++-v3/include/std/vector
  1c10633087657ad7a31f6c3569a3ebe0  libstdc++-v3/include/std/version
*************** ba1de75ac9c1bb7d2506c503fe17708a  libstd
*** 142371,142377 ****
  ea41b659ccf9f3e1850802e2fddaba52  libstdc++-v3/src/c++23/print.cc
  15f6b28b71ad24bc5b6d33c21048e59a  libstdc++-v3/src/c++23/stacktrace.cc
  c319163994652e23066095eded5869f0  libstdc++-v3/src/c++23/std-clib.cc.in
! eb4547a8640586c199c26fbc28917563  libstdc++-v3/src/c++23/std.cc.in
  ef2786c62e1aa27a5405d7bf70e5212c  libstdc++-v3/src/c++23/std.compat.cc.in
  757f1e829f27dedf5e8d7d83b358ad27  libstdc++-v3/src/c++26/Makefile.am
  7bb4fc4ec0d17bf1e304be661919aad7  libstdc++-v3/src/c++26/Makefile.in
--- 143375,143381 ----
  ea41b659ccf9f3e1850802e2fddaba52  libstdc++-v3/src/c++23/print.cc
  15f6b28b71ad24bc5b6d33c21048e59a  libstdc++-v3/src/c++23/stacktrace.cc
  c319163994652e23066095eded5869f0  libstdc++-v3/src/c++23/std-clib.cc.in
! 1bef68f90dc2e17700ce828fe45fb451  libstdc++-v3/src/c++23/std.cc.in
  ef2786c62e1aa27a5405d7bf70e5212c  libstdc++-v3/src/c++23/std.compat.cc.in
  757f1e829f27dedf5e8d7d83b358ad27  libstdc++-v3/src/c++26/Makefile.am
  7bb4fc4ec0d17bf1e304be661919aad7  libstdc++-v3/src/c++26/Makefile.in
*************** b8a53b2b8da32d102d69cbedea3d2216  libstd
*** 142453,142459 ****
  68efb122e218e910a6f9b1452b33e77c  libstdc++-v3/testsuite/17_intro/headers/c++1998/stdc++.cc
  aef041bae3719f48d004f53439beca16  libstdc++-v3/testsuite/17_intro/headers/c++1998/stdc++_assert_neg.cc
  1a348612e7f9f2ad8a052e7a6b99f080  libstdc++-v3/testsuite/17_intro/headers/c++1998/stdc++_multiple_inclusion.cc
! 93ddf5b5e6075e3edb22691d2cc89d62  libstdc++-v3/testsuite/17_intro/headers/c++2011/42319.cc
  bfe44018342421d38a0ae7c466c6964e  libstdc++-v3/testsuite/17_intro/headers/c++2011/67309.cc
  e10b210cba53e419fbc754d7b2a6f19d  libstdc++-v3/testsuite/17_intro/headers/c++2011/linkage.cc
  b6d193d1eb4c0d4cd56ee5e63e31800e  libstdc++-v3/testsuite/17_intro/headers/c++2011/parallel_mode.cc
--- 143457,143463 ----
  68efb122e218e910a6f9b1452b33e77c  libstdc++-v3/testsuite/17_intro/headers/c++1998/stdc++.cc
  aef041bae3719f48d004f53439beca16  libstdc++-v3/testsuite/17_intro/headers/c++1998/stdc++_assert_neg.cc
  1a348612e7f9f2ad8a052e7a6b99f080  libstdc++-v3/testsuite/17_intro/headers/c++1998/stdc++_multiple_inclusion.cc
! 4562c8eaa5f4cf23ec00694ed16211f4  libstdc++-v3/testsuite/17_intro/headers/c++2011/42319.cc
  bfe44018342421d38a0ae7c466c6964e  libstdc++-v3/testsuite/17_intro/headers/c++2011/67309.cc
  e10b210cba53e419fbc754d7b2a6f19d  libstdc++-v3/testsuite/17_intro/headers/c++2011/linkage.cc
  b6d193d1eb4c0d4cd56ee5e63e31800e  libstdc++-v3/testsuite/17_intro/headers/c++2011/parallel_mode.cc
*************** ef314c08bd7a5b34f764c545ce84dfe2  libstd
*** 143312,143317 ****
--- 144316,144323 ----
  949cb8b4df5c7ecaccbc0c2a6bacd48f  libstdc++-v3/testsuite/20_util/is_fundamental/requirements/explicit_instantiation.cc
  96005635102ccd03db221fd3fc8953d8  libstdc++-v3/testsuite/20_util/is_fundamental/requirements/typedefs.cc
  373db358b865e693f68e7ec98ccd75fe  libstdc++-v3/testsuite/20_util/is_fundamental/value.cc
+ 610427c51b5850df70316cac8969b93b  libstdc++-v3/testsuite/20_util/is_implicit_lifetime/value.cc
+ 2134595386c7aaceddaa8a126d3fcfcb  libstdc++-v3/testsuite/20_util/is_implicit_lifetime/version.cc
  d3547bda272766318da8619b4e121bdb  libstdc++-v3/testsuite/20_util/is_implicitly_default_constructible/requirements/explicit_instantiation.cc
  8e5506f359172e965cf6094dfdc9d0cc  libstdc++-v3/testsuite/20_util/is_implicitly_default_constructible/requirements/typedefs.cc
  99eec75693146f737f64e63ecad63d46  libstdc++-v3/testsuite/20_util/is_implicitly_default_constructible/value.cc
*************** da9145a0185055b61b241cc561abd20a  libstd
*** 143831,143837 ****
  cc8f100514fc776c44855526cd4c4f98  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/2.cc
  f0aa77432ff68dc1bc3bb39abb798574  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/3.cc
  218bfa15322cbf3d4699fd75868ce542  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/atomic_shared_ptr.cc
! e5115f89864cd471491ade4b30107235  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/pr118757.cc
  0ed58f781f6defac8f2adf9165c5b843  libstdc++-v3/testsuite/20_util/shared_ptr/casts/1.cc
  f71b39c4f3422ca74560b507e3238d70  libstdc++-v3/testsuite/20_util/shared_ptr/casts/reinterpret.cc
  66b0af9f169e4254c6e08f75f365502c  libstdc++-v3/testsuite/20_util/shared_ptr/casts/rval.cc
--- 144837,144843 ----
  cc8f100514fc776c44855526cd4c4f98  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/2.cc
  f0aa77432ff68dc1bc3bb39abb798574  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/3.cc
  218bfa15322cbf3d4699fd75868ce542  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/atomic_shared_ptr.cc
! d062f610d8deb3a502b4f910b95955be  libstdc++-v3/testsuite/20_util/shared_ptr/atomic/pr118757.cc
  0ed58f781f6defac8f2adf9165c5b843  libstdc++-v3/testsuite/20_util/shared_ptr/casts/1.cc
  f71b39c4f3422ca74560b507e3238d70  libstdc++-v3/testsuite/20_util/shared_ptr/casts/reinterpret.cc
  66b0af9f169e4254c6e08f75f365502c  libstdc++-v3/testsuite/20_util/shared_ptr/casts/rval.cc
*************** c7189ba7b664b74191b9f4e28b5c9940  libstd
*** 144135,144140 ****
--- 145141,145147 ----
  4400d6ca0a17478edfaf976996b94876  libstdc++-v3/testsuite/20_util/tuple/p2321r2.cc
  3244ebd23c35360f15435952a5d771c3  libstdc++-v3/testsuite/20_util/tuple/requirements/dr2367.cc
  52b5b988bb33a29c9b7c1549994ef2b2  libstdc++-v3/testsuite/20_util/tuple/requirements/dr801.cc
+ 5ad953608acc5c9ed6aaa1aea449256c  libstdc++-v3/testsuite/20_util/tuple/requirements/empty_trivial.cc
  258626493913ff952c40a6cd5db7d5cc  libstdc++-v3/testsuite/20_util/tuple/requirements/explicit_instantiation.cc
  38e4d0ea3881b0bf1b486da4ad59f68c  libstdc++-v3/testsuite/20_util/tuple/swap.cc
  cd376663e3dd2f5dbae94a2e6a708738  libstdc++-v3/testsuite/20_util/tuple/swap_cxx17.cc
*************** d474ab3de86472b091cb5e1eb977e148  libstd
*** 144295,144301 ****
  81caf89f5d2508b4ffd2bbeeb2fcefa5  libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc
  2f3b9591e0251d9b1629799d582d140a  libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_equal.cc
  29bb5a9dc38591c43c42b4358dcb686a  libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_hash.cc
! 4d85562f83f12d0679f0a48545bf118f  libstdc++-v3/testsuite/20_util/weak_ptr/pr118757.cc
  1dab19854741ecc627d9ec99f37870cf  libstdc++-v3/testsuite/20_util/weak_ptr/requirements/explicit_instantiation/1.cc
  a610c0786f4a061921c8ff0f20be9f5d  libstdc++-v3/testsuite/20_util/weak_ptr/requirements/explicit_instantiation/2.cc
  9ea3217672cce0af4c51c9cbae0c9b97  libstdc++-v3/testsuite/21_strings/basic_string/40160.cc
--- 145302,145308 ----
  81caf89f5d2508b4ffd2bbeeb2fcefa5  libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc
  2f3b9591e0251d9b1629799d582d140a  libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_equal.cc
  29bb5a9dc38591c43c42b4358dcb686a  libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_hash.cc
! 2b851e2610bf26140f3cf90b7dd7cc0d  libstdc++-v3/testsuite/20_util/weak_ptr/pr118757.cc
  1dab19854741ecc627d9ec99f37870cf  libstdc++-v3/testsuite/20_util/weak_ptr/requirements/explicit_instantiation/1.cc
  a610c0786f4a061921c8ff0f20be9f5d  libstdc++-v3/testsuite/20_util/weak_ptr/requirements/explicit_instantiation/2.cc
  9ea3217672cce0af4c51c9cbae0c9b97  libstdc++-v3/testsuite/21_strings/basic_string/40160.cc
*************** eae00516950607c685e378a89490d58a  libstd
*** 146357,146362 ****
--- 147364,147370 ----
  b66bcfae0b08efa092a933f5fe5f3c8f  libstdc++-v3/testsuite/23_containers/stack/requirements/typedefs.cc
  7c1d12ad44406aeb78b3ade48a98809e  libstdc++-v3/testsuite/23_containers/stack/requirements/uses_allocator.cc
  dc380b1b03a5539c127b54a32a8d85b8  libstdc++-v3/testsuite/23_containers/tuple/comparison_operators/119721.cc
+ 1ea6046a71b855ab94e7f5203be0c8cd  libstdc++-v3/testsuite/23_containers/tuple/cons/119721.cc
  8095490ebaf0100077d254e713821ec0  libstdc++-v3/testsuite/23_containers/unordered_map/104174.cc
  156b154caf5f9ae3faee45845e073878  libstdc++-v3/testsuite/23_containers/unordered_map/115420.cc
  f9ade43cfbd598c0df31fad70de89cb8  libstdc++-v3/testsuite/23_containers/unordered_map/115939.cc
*************** ddded97f8b58f9e50bbc4370585073f6  libstd
*** 148573,148578 ****
--- 149581,149587 ----
  7e36579ad1a51af4f24628bbc8643ee7  libstdc++-v3/testsuite/26_numerics/transform_reduce/1.cc
  f80993352e92bc9bb185f3a73f29cd8a  libstdc++-v3/testsuite/26_numerics/transform_reduce/constexpr.cc
  525e5798867d708e7cc13551760f93c8  libstdc++-v3/testsuite/26_numerics/valarray/103022.cc
+ 0a2f8038a6a96aba34c3e42154fc61ce  libstdc++-v3/testsuite/26_numerics/valarray/108951.cc
  7d4de27ec326547be82a019a237a8466  libstdc++-v3/testsuite/26_numerics/valarray/27867.cc
  15eeb7b65bd3548741bb52a6fe01deb2  libstdc++-v3/testsuite/26_numerics/valarray/28277.cc
  983eedc1113fec3a1465bf15cd53f73b  libstdc++-v3/testsuite/26_numerics/valarray/30416.cc
*************** e4356096911c61dc2d410c486d4bfbfa  libstd
*** 150101,150107 ****
  fda513aa57b58ec8ae495a3e37a6b741  libstdc++-v3/testsuite/30_threads/condition_variable/cons/copy_neg.cc
  0f490f659fdd6710c43edb49ad4a8f23  libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc
  a22ffec2ff77db41215e429fe83d58ac  libstdc++-v3/testsuite/30_threads/condition_variable/members/103382.cc
! dca21798dbbc52d3274ffeaa3622480d  libstdc++-v3/testsuite/30_threads/condition_variable/members/116586.cc
  21078e84f52823d7f9c94acbea81af30  libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc
  3aed92976d281053bc431a346d0de030  libstdc++-v3/testsuite/30_threads/condition_variable/members/3.cc
  c4bfd4842c673512f72f2d9fe332a218  libstdc++-v3/testsuite/30_threads/condition_variable/members/53841.cc
--- 151110,151116 ----
  fda513aa57b58ec8ae495a3e37a6b741  libstdc++-v3/testsuite/30_threads/condition_variable/cons/copy_neg.cc
  0f490f659fdd6710c43edb49ad4a8f23  libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc
  a22ffec2ff77db41215e429fe83d58ac  libstdc++-v3/testsuite/30_threads/condition_variable/members/103382.cc
! e60ebe3b3ca4a349b6f9de9bab33aff4  libstdc++-v3/testsuite/30_threads/condition_variable/members/116586.cc
  21078e84f52823d7f9c94acbea81af30  libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc
  3aed92976d281053bc431a346d0de030  libstdc++-v3/testsuite/30_threads/condition_variable/members/3.cc
  c4bfd4842c673512f72f2d9fe332a218  libstdc++-v3/testsuite/30_threads/condition_variable/members/53841.cc
*************** e01fe847062c2bfd6ed37031f9ca2ff8  libstd
*** 150128,150134 ****
  b4923d7ca0c8c0104802bc08d5e1c2ae  libstdc++-v3/testsuite/30_threads/future/cons/default.cc
  ec49e5336cb3c45afbf2ddddf5583473  libstdc++-v3/testsuite/30_threads/future/cons/move.cc
  cf15d4f41297a7f05235f6491cd35c3b  libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
! de73ab82d1be416f6ff09608be40857d  libstdc++-v3/testsuite/30_threads/future/members/116586.cc
  558c2f7e2a442daebbbc612ba05b66c5  libstdc++-v3/testsuite/30_threads/future/members/118093.cc
  f88638743807ef6884b09ef6b56cc393  libstdc++-v3/testsuite/30_threads/future/members/45133.cc
  a372a9c3e841573c8df7d991b892f56f  libstdc++-v3/testsuite/30_threads/future/members/93456.cc
--- 151137,151143 ----
  b4923d7ca0c8c0104802bc08d5e1c2ae  libstdc++-v3/testsuite/30_threads/future/cons/default.cc
  ec49e5336cb3c45afbf2ddddf5583473  libstdc++-v3/testsuite/30_threads/future/cons/move.cc
  cf15d4f41297a7f05235f6491cd35c3b  libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
! 8d96b84c0fc61d2be6423edb404fbd7a  libstdc++-v3/testsuite/30_threads/future/members/116586.cc
  558c2f7e2a442daebbbc612ba05b66c5  libstdc++-v3/testsuite/30_threads/future/members/118093.cc
  f88638743807ef6884b09ef6b56cc393  libstdc++-v3/testsuite/30_threads/future/members/45133.cc
  a372a9c3e841573c8df7d991b892f56f  libstdc++-v3/testsuite/30_threads/future/members/93456.cc
*************** c4741bd0338ec7cec54d5b61c96ac0c1  libstd
*** 150270,150276 ****
  f2759cbb0122645741437d53d0c3d79e  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/2.cc
  946ea647b882005c7260176e523bbdd1  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/3.cc
  3e2a19730f6e8d7b2331586580f4ccc8  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/1.cc
! 6c711124a4c86b79e6ef8bf59fc311fa  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/116586.cc
  f6e332e0da5679ff09b7bdefac8dd227  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/2.cc
  65ceb0dce688f7d22f2c0ac2db4de262  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/3.cc
  c08ecc556763caa8424e75d0366adda3  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/clock_neg.cc
--- 151279,151285 ----
  f2759cbb0122645741437d53d0c3d79e  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/2.cc
  946ea647b882005c7260176e523bbdd1  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_for/3.cc
  3e2a19730f6e8d7b2331586580f4ccc8  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/1.cc
! 4c9f923441df09b7eea365ee5af99cae  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/116586.cc
  f6e332e0da5679ff09b7bdefac8dd227  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/2.cc
  65ceb0dce688f7d22f2c0ac2db4de262  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/3.cc
  c08ecc556763caa8424e75d0366adda3  libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_lock_until/clock_neg.cc
*************** b67dbc60a5b0d5e68b3301d42c89d370  libstd
*** 150342,150348 ****
  7f25c665770f98206c485d5d7f18e115  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock/2.cc
  a27f2488c39a2a0bcf060befdd7c5e7e  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock/3.cc
  03a4955f029924a2d0eb6f2d31110f26  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/1.cc
! 5d2d05f6e1f411d1978f431757a3551f  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/116586.cc
  b2646746018971b2f7502408ba69b812  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/2.cc
  bef525fe56599b2234510898b1e956af  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/clock_neg.cc
  033af8991cda03faee5e75cb045b81f7  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/unlock/1.cc
--- 151351,151357 ----
  7f25c665770f98206c485d5d7f18e115  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock/2.cc
  a27f2488c39a2a0bcf060befdd7c5e7e  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock/3.cc
  03a4955f029924a2d0eb6f2d31110f26  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/1.cc
! d447566e3b2073bde36e0dd5e2d7708b  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/116586.cc
  b2646746018971b2f7502408ba69b812  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/2.cc
  bef525fe56599b2234510898b1e956af  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_until/clock_neg.cc
  033af8991cda03faee5e75cb045b81f7  libstdc++-v3/testsuite/30_threads/shared_timed_mutex/unlock/1.cc
*************** d15cdcf55f49de39c4fdefc419be3fea  libstd
*** 150405,150411 ****
  28a4cc72497e4561703020d1cc93f90a  libstdc++-v3/testsuite/30_threads/thread/members/hardware_concurrency.cc
  96c8307cdf633de4f51db02425271ebe  libstdc++-v3/testsuite/30_threads/thread/native_handle/cancel.cc
  8fff897afa187580148ceece57bbcb70  libstdc++-v3/testsuite/30_threads/thread/native_handle/typesizes.cc
! 679cf57e4a61942ecaa9210578320dff  libstdc++-v3/testsuite/30_threads/thread/swap/1.cc
  ec30d5440c1422ca4216d48631bf8250  libstdc++-v3/testsuite/30_threads/timed_mutex/121496.cc
  c5b715fd07d0ce109f0f584a1f179b22  libstdc++-v3/testsuite/30_threads/timed_mutex/cons/1.cc
  d54d8adc4826a7b1e97afcd4d9b8f264  libstdc++-v3/testsuite/30_threads/timed_mutex/cons/assign_neg.cc
--- 151414,151420 ----
  28a4cc72497e4561703020d1cc93f90a  libstdc++-v3/testsuite/30_threads/thread/members/hardware_concurrency.cc
  96c8307cdf633de4f51db02425271ebe  libstdc++-v3/testsuite/30_threads/thread/native_handle/cancel.cc
  8fff897afa187580148ceece57bbcb70  libstdc++-v3/testsuite/30_threads/thread/native_handle/typesizes.cc
! 07f384279011412ea66c8c5381145496  libstdc++-v3/testsuite/30_threads/thread/swap/1.cc
  ec30d5440c1422ca4216d48631bf8250  libstdc++-v3/testsuite/30_threads/timed_mutex/121496.cc
  c5b715fd07d0ce109f0f584a1f179b22  libstdc++-v3/testsuite/30_threads/timed_mutex/cons/1.cc
  d54d8adc4826a7b1e97afcd4d9b8f264  libstdc++-v3/testsuite/30_threads/timed_mutex/cons/assign_neg.cc
*************** b1902a39654ce0d4060ffd1a74c8e381  libstd
*** 150422,150428 ****
  6b1831573e79689f5a49f446bce2592c  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/2.cc
  fc48623baac54f5a09dc5e613e2ae69c  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc
  51c77818442245e20c5e53c64e4e0567  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/1.cc
! eeda88837dc57edf51d837dde82faf9c  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/116586.cc
  31ce608d68b642f713059eda18ef9a18  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc
  34de6efad334dd0925a8b9651ec7b771  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/3.cc
  efcc6326f2e872928c4939e867ffab24  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/4.cc
--- 151431,151437 ----
  6b1831573e79689f5a49f446bce2592c  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/2.cc
  fc48623baac54f5a09dc5e613e2ae69c  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc
  51c77818442245e20c5e53c64e4e0567  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/1.cc
! 0d238afb1e5c8095b1d9c7163ef9c1e6  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/116586.cc
  31ce608d68b642f713059eda18ef9a18  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc
  34de6efad334dd0925a8b9651ec7b771  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/3.cc
  efcc6326f2e872928c4939e867ffab24  libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/4.cc
*************** cb881a046fa222c9587b45063ce4773c  libstd
*** 151067,151072 ****
--- 152076,152082 ----
  6310624721d382134456abe416638575  libstdc++-v3/testsuite/ext/forced_error/cons_virtual_derivation.cc
  e3ca1ba09d1815a4fb606942a8937f8e  libstdc++-v3/testsuite/ext/headers.cc
  6e9f4a80f7f540292ec13fdbfcde7e55  libstdc++-v3/testsuite/ext/iota/cxx0x.cc
+ 658cf6b1c91739418d6b5e2a12d990f4  libstdc++-v3/testsuite/ext/iotaarray.cc
  dbd8f1ba75a7bf1d9a520aff8a76e1ed  libstdc++-v3/testsuite/ext/is_heap/1.cc
  34e356c0efb2a2e2e261777d7dcdd41f  libstdc++-v3/testsuite/ext/is_heap/47709.cc
  a23fe1791b48ff3d865a3f0a2177b561  libstdc++-v3/testsuite/ext/is_heap/check_type.cc
*************** aa52b04bf095d0226a1314474cb5c3c4  libstd
*** 152639,152645 ****
  3d3f95e4c126c7714834db5c046f0867  libstdc++-v3/testsuite/util/testsuite_hooks.cc
  c08d7419962b291852dd827d7d78f678  libstdc++-v3/testsuite/util/testsuite_hooks.h
  2cc9d485ece15882c52d8b6a9c1094e8  libstdc++-v3/testsuite/util/testsuite_io.h
! ba7ebea1dd36e6d7a9945f836f828353  libstdc++-v3/testsuite/util/testsuite_iterators.h
  bb471f730bbdca73a1658e3b1e4295c0  libstdc++-v3/testsuite/util/testsuite_new_operators.h
  cb452b2ea9afe9f303a9f003d3d6412b  libstdc++-v3/testsuite/util/testsuite_performance.h
  9e7f7529d1423cbb841bf18d5251891d  libstdc++-v3/testsuite/util/testsuite_random.h
--- 153649,153655 ----
  3d3f95e4c126c7714834db5c046f0867  libstdc++-v3/testsuite/util/testsuite_hooks.cc
  c08d7419962b291852dd827d7d78f678  libstdc++-v3/testsuite/util/testsuite_hooks.h
  2cc9d485ece15882c52d8b6a9c1094e8  libstdc++-v3/testsuite/util/testsuite_io.h
! 34556190ebaddca8dd2a1c214b659ba2  libstdc++-v3/testsuite/util/testsuite_iterators.h
  bb471f730bbdca73a1658e3b1e4295c0  libstdc++-v3/testsuite/util/testsuite_new_operators.h
  cb452b2ea9afe9f303a9f003d3d6412b  libstdc++-v3/testsuite/util/testsuite_performance.h
  9e7f7529d1423cbb841bf18d5251891d  libstdc++-v3/testsuite/util/testsuite_random.h
diff -Nrcpad gcc-16-20251026/contrib/ChangeLog gcc-16-20251102/contrib/ChangeLog
*** gcc-16-20251026/contrib/ChangeLog	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/contrib/ChangeLog	Sun Nov  2 22:32:16 2025
***************
*** 1,3 ****
--- 1,8 ----
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* gcc-changelog/git_commit.py (ignored_prefixes): Add
+ 	'libgrust/rustc-lib/core/'.
+ 
  2025-10-16  David Malcolm  <dmalcolm@redhat.com>
  
  	* gcc.doxy (INPUT): Add gcc/custom-sarif-properties
diff -Nrcpad gcc-16-20251026/contrib/gcc-changelog/git_commit.py gcc-16-20251102/contrib/gcc-changelog/git_commit.py
*** gcc-16-20251026/contrib/gcc-changelog/git_commit.py	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/contrib/gcc-changelog/git_commit.py	Sun Nov  2 22:32:16 2025
*************** ignored_prefixes = {
*** 150,155 ****
--- 150,156 ----
      'gcc/testsuite/go.test/test/',
      'libffi/',
      'libgo/',
+     'libgrust/rustc-lib/core/',
      'libphobos/libdruntime/',
      'libphobos/src/',
      'libsanitizer/',
diff -Nrcpad gcc-16-20251026/gcc/ChangeLog gcc-16-20251102/gcc/ChangeLog
*** gcc-16-20251026/gcc/ChangeLog	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ChangeLog	Sun Nov  2 22:32:16 2025
***************
*** 1,3 ****
--- 1,606 ----
+ 2025-11-01  Shreya Munnangi  <smunnangi1@ventanamicro.com>
+ 
+ 	PR target/67731
+ 	* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
+ 	Handle IOR of single bit bitfields from the same object.
+ 
+ 2025-11-01  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	* config/riscv/riscv-protos.h (has_vtype_op): Add prototype.
+ 	(mask_agnostic_p, get_avl, vsetvl_insn_p): Likewise.
+ 	* config/riscv/riscv-vsetvl.cc (has_vtype_op): No longer static.
+ 	(vsetvl_insn_p, get_avl_mask_agnostic_p): Likewise.
+ 	* config/riscv/riscv.cc (struct last_vcofnig): New structure.
+ 	(clear_vconfig): New function.
+ 	(compatible_with_last_vconfig, riscv_sched_init): Likewise.
+ 	(riscv_sched_reorder): Likewise.
+ 	(TARGET_SCHED_INIT, TARGET_SCHED_REORDER): Define.
+ 	* config/riscv/vector.md ("*mov<mode>"): Set has_vtype_op, has_vl_op
+ 	attributes.
+ 	* .simplify-rtx.cc.swo: New file.
+ 
+ 2025-11-01  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR rtl-optimization/122321
+ 	* lra-constraints.cc (update_equiv): Make sure REGNO is in
+ 	ira_reg_equiv before trying to update ira_reg_equiv.
+ 
+ 2025-11-01  Martin Uecker  <uecker@tugraz.at>
+ 
+ 	* doc/extend.texi: Document new extension.
+ 
+ 2025-11-01  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+ 
+ 	* config/xtensa/xtensa.md (negsf2):
+ 	Add another insn pattern that is valid when TARGET_DENSITY is
+ 	enabled and both the source and destination are address registers.
+ 
+ 2025-11-01  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+ 
+ 	* config/xtensa/xtensa.md
+ 	(c_enum "unspec", int_iterator ANY_ROUND): Add UNSPEC_ROUND.
+ 	(int_attr m_round): Add a pair of UNSPEC_ROUND and "round".
+ 	(int_attr c_round): New integer iterator attribute, that expands
+ 	to "flag_unsafe_math_optimizations" in the case of UNSPEC_ROUND,
+ 	and to "1" otherwise.
+ 	(l<m_round>sfsi2, *l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled):
+ 	Append " && <c_round>" to the conditions.
+ 
+ 2025-11-01  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+ 
+ 	* config/xtensa/xtensa.md (*fix<s_fix>_truncsfsi2_scaled,
+ 	*float<s_float>sisf2_scaled, *l<m_round>sfsi2_scaled):
+ 	Remove 'F'-constraint.
+ 
+ 2025-11-01  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR ipa/122512
+ 	* cgraph.h (enum toplevel_type): Add TOPLEVEL_MAX. Add comment
+ 	about keeping toplevel_type_names in sync.
+ 	* symtab.cc (symtab_type_names): Rename to ...
+ 	(toplevel_type_names): Add new types and add an assert about
+ 	the size.
+ 	(symtab_node::get_symtab_type_string): Use toplevel_type_names
+ 	instead of symtab_type_names.
+ 	(symtab_node::dump_base): Likewise.
+ 
+ 2025-10-31  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122437
+ 	* fold-const.h (div_if_zero_remainder): Remove.
+ 
+ 2025-10-31  Tamar Christina  <tamar.christina@arm.com>
+ 
+ 	PR target/121853
+ 	* config/aarch64/aarch64-simd.md (extendbfsf2): New.
+ 
+ 2025-10-31  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/122502
+ 	* tree-scalar-evolution.cc (final_value_replacement_loop):
+ 	Avoid folding from within FOR_EACH_IMM_USE_STMT due to active
+ 	ranger.
+ 
+ 2025-10-31  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122437
+ 	* fold-const.cc (div_if_zero_remainder): Remove.
+ 
+ 2025-10-31  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122497
+ 	* tree-scalar-evolution.cc (final_value_replacement_loop): Call replace_uses_by
+ 	only after the replacement statement was created.
+ 
+ 2025-10-31  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	* config/loongarch/lasx.md: Support.
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_expand_vec_widen_hilo): Remove unused code.
+ 	* config/loongarch/lsx.md: Support.
+ 
+ 2025-10-31  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	* config/loongarch/lasx.md (ILASX_HB): Move to ...
+ 	* config/loongarch/lsx.md (ILSX_HB): Move to ...
+ 	* config/loongarch/simd.md (ILSX_HB): ... here.
+ 	(ILASX_HB): ... here.
+ 	(IVEC_HB): New iterator.
+ 	(WVEC_QUARTER): New attr.
+ 	(wvec_quarter): Likewise.
+ 	(simdfmt_qw): Likewise.
+ 	(<su>dot_prod<wvec_quarter><mode>): New template.
+ 
+ 2025-10-31  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	* config/loongarch/lasx.md (hi_lo): Move to ...
+ 	* config/loongarch/simd.md (hi_lo): ... here.
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_expand_vec_widen_hilo): Add 128-bit data processing.
+ 	* config/loongarch/lsx.md
+ 	(vec_widen_<su><optab>_<hi_lo>_<mode>):	New define_expand.
+ 	(vec_widen_<su>mult_<hi_lo>_<mode>): Likewise.
+ 
+ 2025-10-31  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	* config/loongarch/lasx.md (vec_widen_<su>add_hi_<mode>):
+ 	Move.
+ 	(vec_widen_<su>add_lo_<mode>): Move.
+ 	(vec_widen_<su>sub_hi_<mode>): Move.
+ 	(vec_widen_<su>sub_lo_<mode>): Move.
+ 	(vec_widen_<su>mult_hi_<mode>): Move.
+ 	(vec_widen_<su>mult_lo_<mode>): Move.
+ 	(hi_lo): New define_int_attr.
+ 	(vec_widen_<su><optab>_<hi_lo>_<mode>): New define_expand.
+ 	(vec_widen_<su>mult_<hi_lo>_<mode>): Likewise.
+ 	* config/loongarch/loongarch-protos.h
+ 	(loongarch_expand_vec_widen_hilo): Modify the function
+ 	parameter list.
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_expand_vec_widen_hilo): Optimized.
+ 
+ 2025-10-30  David Faust  <david.faust@oracle.com>
+ 
+ 	PR debug/122248
+ 	* dwarf2out.cc (gen_btf_tag_dies): Always replace an existing
+ 	AT_GNU_annotation on the target die.
+ 
+ 2025-10-30  David Faust  <david.faust@oracle.com>
+ 
+ 	* btfout.cc (btf_add_used_type_1): Do not consider creating
+ 	fixups at typedefs.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-cgraph.cc (output_symtab): Remove asm_nodes_out.
+ 	* lto-streamer-out.cc (lto_output_toplevel_asms): Use
+ 	partitioning.
+ 	(create_order_remap): Remove asm_nodes_out.
+ 	(lto_output): In LGEN add asm_nodes into partition.
+ 	* lto-streamer.h (lto_output_toplevel_asms): Add encoder.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-cgraph.cc (compute_ltrans_boundary): Add asm_node.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* ipa-icf.cc (sem_item_optimizer::write_summary): Use
+ 	toplevel_node.
+ 	(sem_item_optimizer::read_section): Likewise.
+ 	* ipa-modref.cc (modref_write): Likewise.
+ 	* ipa-prop.cc (ipa_write_return_summaries): Likewise.
+ 	(ipcp_write_transformation_summaries): Likewise.
+ 	* ipa-reference.cc (ipa_reference_write_optimization_summary):
+ 	Likewise.
+ 	* lto-cgraph.cc (lto_symtab_encoder_new): Likewise.
+ 	(lto_symtab_encoder_encode): Likewise.
+ 	(lto_symtab_encoder_delete_node): Likewise.
+ 	(lto_symtab_encoder_in_partition_p): Likewise.
+ 	(lto_set_symtab_encoder_in_partition): Likewise.
+ 	(output_refs): Likewise.
+ 	(compute_ltrans_boundary): Likewise.
+ 	(output_symtab): Likewise.
+ 	(output_cgraph_opt_summary): Likewise.
+ 	* lto-streamer-out.cc (lto_output): Likewise.
+ 	(produce_symtab): Likewise.
+ 	(produce_symtab_extension): Likewise.
+ 	* lto-streamer.h (struct lto_encoder_entry): Likewise.
+ 	(struct lto_symtab_encoder_d): Likewise.
+ 	(lto_symtab_encoder_encode): Likewise.
+ 	(lto_symtab_encoder_delete_node): Likewise.
+ 	(lto_symtab_encoder_in_partition_p): Likewise.
+ 	(lto_symtab_encoder_lookup): Likewise.
+ 	(lsei_next): Likewise.
+ 	(lsei_varpool_node): Likewise.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* cgraph.h (enum symtab_type): Replace with toplevel_type.
+ 	(enum toplevel_type): New.
+ 	(struct toplevel_node): New.
+ 	(struct asm_node): Inherits from toplevel_node.
+ 	(test): New.
+ 	(symbol_table::finalize_toplevel_asm): Use constructor.
+ 	* coretypes.h (struct toplevel_node): New.
+ 	(struct asm_node): New.
+ 	* lto-streamer-in.cc (lto_input_toplevel_asms): Add
+ 	lto_file_data.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* cgraph.cc (cgraph_node::release_body): Keep lto_file_data.
+ 	(cgraph_node::remove): likewise.
+ 	* lto-section-in.cc (lto_free_function_in_decl_state_for_node):
+ 	likewise.
+ 	* varpool.cc (varpool_node::remove): likewise.
+ 
+ 2025-10-30  Qing Zhao  <qing.zhao@oracle.com>
+ 
+ 	* doc/extend.texi: Clarification when the counted_by attribute is applied
+ 	on a void pointer.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR target/116075
+ 	* fold-const-call.cc (fold_const_vec_shl_insert): New function.
+ 	(fold_const_call): Call fold_const_vec_shl_insert for CFN_VEC_SHL_INSERT.
+ 	* match.pd (`VEC_SHL_INSERT (dup (A), A)`): New pattern.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122247
+ 	* tree-ssa-forwprop.cc (do_simple_agr_dse): Allow phi node for the usage
+ 	if the usage of the phi result is just the "same" as the original clobber.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122247
+ 	* tree-ssa-forwprop.cc (do_simple_agr_dse): Allow
+ 	use to be a clobber of the same kind to the same lhs.
+ 
+ 2025-10-30  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	* tree-ssa-loop-niter.cc (shifted_range_nonzero_p): New
+ 	function.
+ 	(number_of_iterations_cltz): Call new function.
+ 	* tree-ssa-loop.cc (pass_scev_cprop::execute): Enable ranger.
+ 
+ 2025-10-30  Robin Dapp  <rdapp.gcc@gmail.com>
+ 
+ 	PR target/122445
+ 	* config/riscv/riscv-avlprop.cc (pass_avlprop::get_vlmax_ta_preferred_avl):
+ 	Scale AVL of subreg uses.
+ 
+ 2025-10-30  Artemiy Volkov  <artemiy.volkov@arm.com>
+ 
+ 	PR tree-optimization/122478
+ 	* match.pd: Fix the view_convert (BIT_FIELD_REF) pattern.
+ 
+ 2025-10-30  Richard Biener  <rguenther@suse.de>
+ 
+ 	* config/i386/i386-options.cc (ix86_option_override_internal):
+ 	Fix check during opts->x_ix86_move_max initialization.
+ 
+ 2025-10-30  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR rtl-optimization/121198
+ 	* lra-constraints.cc (process_alt_operands): Compute least upper
+ 	bound of all register classes over all required registers in
+ 	order to determine register class for a hard register constraint.
+ 
+ 2025-10-30  Richard Biener  <rguenther@suse.de>
+ 	    Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* tree-vect-slp.cc (vect_get_operand_map): Handle commutative
+ 	operands when swapping is requested.
+ 	(vect_build_slp_tree_1): Allow STMT_VINFO_REDUC_IDX differences
+ 	when operand swapping makes them match and request swapping.
+ 	(vect_build_slp_instance): Indicate we have successfully
+ 	discovered a SLP reduction group.
+ 
+ 2025-10-30  Uros Bizjak  <ubizjak@gmail.com>
+ 
+ 	PR target/116815
+ 	* config/i386/i386.md (ovf_add_cmp): New code attribute.
+ 	(udf_sub_cmp): Ditto.
+ 	(ovf_comm): New int iterator.
+ 	(*plus_within_<code><mode>3_<ovf_comm>): New insn and split pattern.
+ 	(*minus_within_<code><mode>3): Ditto.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	* gimple-fold.cc (gimple_fold_builtin_assume_aligned): Remove.
+ 	(gimple_fold_builtin): Don't fold __builtin_assume_aligned
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Revert:
+ 	2025-10-27  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR middle-end/107389
+ 	PR tree-optimization/122086
+ 	* tree-ssa-forwprop.cc (forwprop_may_propagate_copy): New function.
+ 	(pass_forwprop::execute):  Use forwprop_may_propagate_copy
+ 	instead of may_propagate_copy.
+ 
+ 2025-10-30  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/120687
+ 	* tree-vect-slp.cc (vect_optimize_slp_pass::is_compatible_layout):
+ 	New overload for checking a whole partition.
+ 	(vect_optimize_slp_pass::legitimize): New function trying
+ 	a single layout for all partitions for now.
+ 	(vect_optimize_slp_pass::run): Try legitimizing to a single
+ 	layout before propagating.
+ 	(vect_slp_analyze_operations): For dumping deal with
+ 	SLP_TREE_SCALAR_STMTS being empty or element zero being NULL.
+ 
+ 2025-10-30  liuhongt  <hongtao.liu@intel.com>
+ 
+ 	PR target/122457
+ 	* config/i386/sse.md (VI2_AVX10_2): New mode iterator.
+ 	(usdot_prod<sseunpackmodelower><mode>): Use VI2_AVX10_2
+ 	instead of VI2_AVX512F.
+ 	(udot_prod<sseunpackmodelower><mode>): Ditto.
+ 
+ 2025-10-30  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* config/loongarch/lasx.md (fnma<mode>4): Remove.
+ 	* config/loongarch/lsx.md (fnma<mode>4): Remove.
+ 	* config/loongarch/simd.md (fnma<mode>4): Simplify and correct.
+ 
+ 2025-10-30  Jinyang He  <hejinyang@loongson.cn>
+ 	    Peng Fan  <fanpeng@loongson.cn>
+ 
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_expand_conditional_move): Only allow valid binary
+ 	op when optimize conditional move.
+ 
+ 2025-10-29  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Revert:
+ 	2025-10-29  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR target/116662
+ 	* config/riscv/riscv.cc (riscv_option_override): Override
+ 	default value for destructive interference size.
+ 
+ 2025-10-29  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Revert:
+ 	2025-10-29  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR target/116662
+ 	* config/riscv/riscv.cc (riscv_option_override): Apply correct version
+ 	of the patch.
+ 
+ 2025-10-29  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR target/116662
+ 	* config/riscv/riscv.cc (riscv_option_override): Apply correct version
+ 	of the patch.
+ 
+ 2025-10-29  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR target/116662
+ 	* config/riscv/riscv.cc (riscv_option_override): Override
+ 	default value for destructive interference size.
+ 
+ 2025-10-29  Andrew MacLeod  <amacleod@redhat.com>
+ 
+ 	PR tree-optimization/91191
+ 	* gimple-range-op.cc (gimple_range_op_handler): Descend one
+ 	operand lower for a VIEW_CONVERT_EXPR.
+ 	* range-op-mixed.h (class operator_view): New.
+ 	* range-op.cc (range_op_table): Add VIEW_CONVERT_EXPR case.
+ 	(operator_view::fold_range): New.
+ 	(operator_view::op1_range): New.
+ 	(operator_view::update_bitmask): New.
+ 
+ 2025-10-29  Richard Biener  <rguenther@suse.de>
+ 
+ 	* tree-vect-slp.cc (vect_analyze_slp): Mark stmts in BB roots
+ 	as released after vect_build_slp_instance.
+ 	(vect_build_slp_instance): Release scalar_stmts when exiting
+ 	early.
+ 
+ 2025-10-29  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	PR target/122097
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_const_vector_bitimm_set_p): Add support for vector float.
+ 	(loongarch_const_vector_bitimm_clr_p): Likewise.
+ 	(loongarch_print_operand): Likewise.
+ 	* config/loongarch/simd.md (and<mode>3): Likewise.
+ 
+ 2025-10-29  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	* config/loongarch/lasx.md (xor<mode>3): Delete.
+ 	(ior<mode>3): Delete.
+ 	(and<mode>3): Delete.
+ 	* config/loongarch/lsx.md (xor<mode>3): Delete.
+ 	(ior<mode>3): Delete.
+ 	(and<mode>3): Delete.
+ 	* config/loongarch/simd.md (xor<mode>3): Define.
+ 	(ior<mode>3): Likewise.
+ 	(and<mode>3): Likewise.
+ 
+ 2025-10-29  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	* config/loongarch/genopts/loongarch.opt.in (-mbreak-code=):
+ 	New.
+ 	* config/loongarch/loongarch.opt: Regenerate.
+ 	* config/loongarch/loongarch.md (trap): Separate to a
+ 	define_insn and a define_expand which takes la_break_code.
+ 	* doc/invoke.texi (-mbreak-code=): Document.
+ 	* config/loongarch/loongarch.opt.urls: Regenerate.
+ 
+ 2025-10-28  Richard Biener  <rguenther@suse.de>
+ 
+ 	* tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer):
+ 	Avoid explicit LOOP_VINFO_IV_EXIT reference.
+ 
+ 2025-10-28  Artemiy Volkov  <artemiy.volkov@arm.com>
+ 
+ 	* match.pd: Add pattern to simplify view_convert (BIT_FIELD_REF).
+ 
+ 2025-10-28  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	* config/riscv/riscv.cc (riscv_get_vls_cc_attr): Fix error message
+ 	parameter order and add check_only condition.  Improve diagnostic
+ 	message formatting with proper quoting.
+ 	(riscv_handle_rvv_vls_cc_attribute): Anonymize unused node parameter.
+ 
+ 2025-10-28  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	PR tree-optimization/122065
+ 	* tree-vect-generic.cc (add_rshift): Update name and add code parameter.
+ 	(add_shift): Update name.
+ 	(expand_vector_mult): New lowering for MULT_EXPR.
+ 	(expand_vector_divmod): Use updated function name.
+ 	(expand_vector_operation): Use updated function name.
+ 
+ 2025-10-27  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	* expr.cc (expr_has_boolean_range): New function.
+ 	(expand_expr_real_2): Use expr_has_boolean_range instead of
+ 	gimple_zero_one_valued_p.
+ 	* tree-ssanames.cc (ssa_name_has_boolean_range): Update to take
+ 	a gimple STMT.
+ 	* tree-ssanames.h (ssa_name_has_boolean_range): Update for the new
+ 	argument and default to nullptr.
+ 
+ 2025-10-27  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/105749
+ 	PR tree-optimization/80635
+ 	* match.pd (`VCE<bool>(zero_one_valued_p) ==\!= 0`): New pattern.
+ 
+ 2025-10-27  Tamar Christina  <tamar.christina@arm.com>
+ 
+ 	PR tree-optimization/122408
+ 	* tree-vect-slp-patterns.cc (vect_validate_multiplication): Cleanup and
+ 	document interface.
+ 	(complex_mul_pattern::matches, complex_fms_pattern::matches): Update to
+ 	new interface.
+ 
+ 2025-10-27  Andrew Stubbs  <ams@baylibre.com>
+ 
+ 	PR tree-optimization/104116
+ 	* config/gcn/gcn-valu.md (abs<mode>2): New define_expand for
+ 	integer vector modes.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/122325
+ 	* common.opt (flag_default_complex_method): Remove.
+ 	* opts.cc (init_options_struct): Default to fortran rules
+ 	for complex evaluations.
+ 	(finish_options): Remove (re-)instantiating of the frontend
+ 	default of the complex evaluation method.
+ 
+ 2025-10-27  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Add
+ 	bool parameter.
+ 	* config/riscv/riscv.h (enum riscv_cc): Add RISCV_CC_VLS_V_32,
+ 	RISCV_CC_VLS_V_64, RISCV_CC_VLS_V_128, RISCV_CC_VLS_V_256,
+ 	RISCV_CC_VLS_V_512, RISCV_CC_VLS_V_1024, RISCV_CC_VLS_V_2048,
+ 	RISCV_CC_VLS_V_4096, RISCV_CC_VLS_V_8192, RISCV_CC_VLS_V_16384.
+ 	(CUMULATIVE_ARGS): Add abi_vlen field.
+ 	* config/riscv/riscv.cc (riscv_handle_rvv_vls_cc_attribute): New
+ 	function.
+ 	(riscv_gnu_attributes): Add vls_cc attribute entry.
+ 	(riscv_attributes): Add riscv_vls_cc attribute entry.
+ 	(riscv_flatten_aggregate_field): Add vls_p and abi_vlen parameters
+ 	to handle VLS vector types.
+ 	(riscv_flatten_aggregate_argument): Update call to
+ 	riscv_flatten_aggregate_field.
+ 	(riscv_get_vector_arg): Add vls_p parameter for VLS handling.
+ 	(riscv_vls_cc_p): New function.
+ 	(riscv_get_cc_abi_vlen): New function.
+ 	(riscv_valid_abi_vlen_vls_cc_p): New function.
+ 	(riscv_get_riscv_cc_by_abi_vlen): New function.
+ 	(riscv_get_vls_container_type): New function.
+ 	(riscv_pass_vls_in_vr): New function.
+ 	(riscv_pass_aggregate_in_vr): New function.
+ 	(riscv_get_arg_info): Add VLS calling convention handling.
+ 	(riscv_function_arg_advance): Update for VLS calling convention.
+ 	(riscv_return_in_memory): Add fntype parameter and initialize
+ 	cumulative args properly.
+ 	(riscv_v_abi): Add abi parameter.
+ 	(riscv_get_vls_cc_attr): New function.
+ 	(riscv_vls_cc_function_abi): New function.
+ 	(riscv_fntype_abi): Add VLS calling convention detection.
+ 	(riscv_asm_output_variant_cc): Update for VLS calling convention.
+ 
+ 2025-10-27  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR target/64345
+ 	PR tree-optimization/80770
+ 	* config/riscv/bitmanip.md (<optab>_not_const<mode>): Turn into a
+ 	peephole2 to avoid matching prior to combine.
+ 	* ifcvt.cc (noce_try_sign_bit_splat): When costs are equal steer
+ 	towards an AND based sequence.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/122419
+ 	* tree-vect-slp.cc (vect_analyze_slp_reduc_chain): Only
+ 	skip noop conversions.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/122435
+ 	* tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt):
+ 	Also match noop conversions when detecting redundant stores.
+ 
+ 2025-10-27  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* config/loongarch/loongarch.cc (loongarch_rtx_costs):
+ 	Ignore the cost impact of SIGN_EXTEND/ZERO_EXTEND.
+ 
+ 2025-10-27  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* config/loongarch/loongarch.md (both_non_zero): New combiner.
+ 	(both_non_zero_subreg): Ditto.
+ 
+ 2025-10-27  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* config/loongarch/loongarch.md
+ 	(sign_extend_ashift<GPR:mode><SHORT:mode>): New combiner.
+ 
+ 2025-10-27  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	* function-abi.h (NUM_ABI_IDS): Increase from 8 to 12.
+ 
+ 2025-10-27  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+ 
+ 	* config/xtensa/xtensa.md (one_cmplsi2):
+ 	Rearrange back as an expand pattern.
+ 
+ 2025-10-27  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR middle-end/107389
+ 	PR tree-optimization/122086
+ 	* tree-ssa-forwprop.cc (forwprop_may_propagate_copy): New function.
+ 	(pass_forwprop::execute):  Use forwprop_may_propagate_copy
+ 	instead of may_propagate_copy.
+ 
+ 2025-10-26  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR target/122270
+ 	* config/riscv/riscv-vector-builtins-bases.cc (vset::fold): Use the
+ 	unshare_expr for the statement that will be added seperately rather
+ 	the one which will be used for the replacement.
+ 
+ 2025-10-26  James K. Lowden  <jklowden@cobolworx.com>
+ 
+ 	* doc/install.texi: Add libxml2 dependency for COBOL
+ 	library. Clarify 128-bit numeric dependency.
+ 
+ 2025-10-26  Gerald Pfeifer  <gerald@pfeifer.com>
+ 
+ 	* poly-int.h: Change struct poly_int to class poly_int.
+ 
+ 2025-10-26  LIU Hao  <lh_mouse@126.com>
+ 
+ 	PR target/119079
+ 	* config/i386/i386.md: Use `movsxd` to perform SI-to-DI extension in Intel
+ 	syntax.
+ 
+ 2025-10-26  Kuan-Lin Chen  <rufus@andestech.com>
+ 
+ 	* config/riscv/riscv.cc (riscv_legitimize_move): Append extend.
+ 
+ 2025-10-26  Osama Abdelkader  <osama.abdelkader@gmail.com>
+ 
+ 	* wide-int.h: Fix typo "accomodate" to "accommodate" in comment.
+ 	* value-range-storage.h: Likewise.
+ 	* tree-vectorizer.h (dr_set_safe_speculative_read_required):
+ 	Fix duplicate "the the" to "the" in comment.
+ 
  2025-10-25  Sam James  <sam@gentoo.org>
  
  	* doc/extend.texi (nocf_check): Fix syntax errors in example.
diff -Nrcpad gcc-16-20251026/gcc/DATESTAMP gcc-16-20251102/gcc/DATESTAMP
*** gcc-16-20251026/gcc/DATESTAMP	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/DATESTAMP	Sun Nov  2 22:32:17 2025
***************
*** 1 ****
! 20251026
--- 1 ----
! 20251102
diff -Nrcpad gcc-16-20251026/gcc/ada/ChangeLog gcc-16-20251102/gcc/ada/ChangeLog
*** gcc-16-20251026/gcc/ada/ChangeLog	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/ChangeLog	Sun Nov  2 22:32:17 2025
***************
*** 1,3 ****
--- 1,174 ----
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/15610
+ 	* sem_type.adb (Collect_Interps): Apply the same visibility
+ 	criterion to expanded names as Find_Expanded_Name.
+ 
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/54178
+ 	* sem_ch12.adb (Instantiate_Object): Strip qualification to detect
+ 	aggregates used as actuals.
+ 
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/16214
+ 	* sem_ch8.adb (Find_Expanded_Name): Consolidate and streamline the
+ 	processing required for references to instances within themselves.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/48039
+ 	* sem_ch12.adb (Analyze_Subprogram_Instantiation): Call
+ 	Remove_Homonym to remove the enclosing package from visibility.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* exp_util.adb (Remove_Side_Effects): Use separately the Etype of
+ 	the expression to build new nodes and its Underlying_Type to drive
+ 	part of the processing.
+ 
+ 2025-10-28  Johannes Kliemann  <kliemann@adacore.com>
+ 
+ 	* adaint.c: Remove __gnat_enable_signals, __gnat_disable_signals
+ 	and related code for QNX.
+ 	* libgnarl/s-taprop__qnx.adb: Disable and enable
+ 	signals in Ada.
+ 
+ 2025-10-28  Alexandre Oliva  <oliva@adacore.com>
+ 
+ 	* sem_ch13.adb (Analyze_Aspect_Export_Import): Skip
+ 	Set_Is_Imported on E_Exception.
+ 	* sem_prag.adb (Process_Import_Or_Interface): Explain
+ 	why not Set_Is_Imported.
+ 
+ 2025-10-28  Denis Mazzucato  <mazzucato@adacore.com>
+ 
+ 	* sem_util.adb (Collect_Primitive_Operations): Avoid setting
+ 	Is_Primitive for noninherited and nonoverriding subprograms not
+ 	declared immediately within a package specification.
+ 	* sem_ch13.adb (Check_Nonoverridable_Aspect_Subprograms): Better
+ 	error posting to allow multiple errors on same type but different
+ 	aggregate subprogram.
+ 
+ 2025-10-28  Ronan Desplanques  <desplanques@adacore.com>
+ 
+ 	* table.ads (Clear, Is_Empty): New subprograms.
+ 	* table.adb (Clear, Is_Empty): Likewise.
+ 	(Init): Use new subprogram.
+ 	* atree.adb (Traverse_Func_With_Parent): Use new subprograms.
+ 	* fmap.adb (Empty_Tables): Use new subprogram.
+ 	* par_sco.adb (Process_Pending_Decisions): Likewise.
+ 	* sem_elab.adb (Check_Elab_Call): Likewise.
+ 	* sem_ch12.adb (Build_Local_Package, Analyze_Package_Instantiation,
+ 	Analyze_Subprogram_Instantiation): Likewise.
+ 	(Save_And_Reset): Use Table.Table.First.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/122063
+ 	* exp_fixd.adb (Build_Double_Divide_Code): Convert the result of the
+ 	multiply.
+ 	(Build_Multiply): Use base types of operands to size the operation.
+ 	(Build_Rem): Likewise.
+ 	(Build_Scaled_Divide_Code): Convert the result of the multiply.
+ 
+ 2025-10-28  Tonu Naks  <naks@adacore.com>
+ 
+ 	* doc/gnat_rm/obsolescent_features.rst: typo
+ 	* gnat_rm.texi: Regenerate.
+ 
+ 2025-10-28  Javier Miranda  <miranda@adacore.com>
+ 
+ 	* aspects.adb (Get_Aspect_Id): Enable aspect Unsigned_Base_Range
+ 	using -gnatd.u
+ 	* debug.adb (Debug_Flag_Dot_U): Document this switch.
+ 	* einfo-utils.adb (Is_Modular_Integer_Type): Return True if
+ 	the entity is a modular integer type and its base type does
+ 	not have the attribute has_unsigned_base_range_aspect.
+ 	(Is_Signed_Integer_Type): Return True if the entity is a signed
+ 	integer type, or it is a modular integer type and its base type
+ 	has the attribute has_unsigned_base_range_aspect.
+ 	* einfo.ads (E_Modular_Integer_Type): Add documentation of
+ 	Has_Unsigned_Base_Range_Aspect.
+ 	* par-ch4.adb (Scan_Apostrophe): Enable attribute Unsigned_Base_Range
+ 	using -gnatd.u
+ 	* sem_ch13.adb (Analyze_One_Aspect): Check general language
+ 	restrictions on aspect Unsigned_Base_Range. For Unsigned_Base_Range
+ 	aspect, do not delay the generation of the pragma becase we need
+ 	to process it before any type or subtype derivation is analyzed.
+ 	* sem_ch3.adb (Build_Scalar_Bound): Disable code analyzing the
+ 	bound with the base type of the parent type because, for unsigned
+ 	base range types, their base type is a modular type but their
+ 	type is a signed integer type.
+ 	* sem_prag.adb (Analyze_Pragma): Enable pragma Unsigned_Base_Range
+ 	using -gnatd.u. Check more errors on Unsigned_Base_Range pragma,
+ 	and create the new base type only when required.
+ 
+ 2025-10-28  Ronan Desplanques  <desplanques@adacore.com>
+ 
+ 	* sem_ch12.adb (Build_Local_Package)
+ 	(Analyze_Package_Instantiation, Analyze_Subprogram_Instantiation):
+ 	Fix Set_Last calls.
+ 	(Set_Instance_Of): Use Table.Table.Append.
+ 	(Save_And_Reset): Remove useless call. Remove defensive code.
+ 	(Restore): Remove incorrect Set_Last call and adapt to
+ 	Set_Instance_Of change.
+ 
+ 2025-10-28  Denis Mazzucato  <mazzucato@adacore.com>
+ 
+ 	* sem_prag.adb (Analyze_Pragma): Add enclosing quotation when the
+ 	invalid switch ends with a space.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/59234
+ 	* sem_ch12.adb (Analyze_Formal_Package_Declaration): Mark the
+ 	special name built for the formal in the parent of a child unit
+ 	as internal.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/34511
+ 	* sem_ch12.adb (Analyze_Associations): Add Parent_Installed formal
+ 	parameter and pass it in call to Analyze_One_Association.
+ 	(Analyze_One_Association): Add Parent_Installed formal parameter
+ 	and pass it in call to Instantiate_Formal_Subprogram.
+ 	(Analyze_Formal_Package_Declaration): Pass Parent_Installed in call
+ 	to Analyze_Associations.
+ 	(Analyze_Package_Instantiation): Likewise.
+ 	(Analyze_Subprogram_Instantiation): Likewise.
+ 	(Instantiate_Formal_Subprogram): Add Parent_Installed formal
+ 	parameter and prune references to the parent unit(s) only if
+ 	it is true.
+ 
+ 2025-10-27  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/29958
+ 	* sem_ch7.adb (Declare_Inherited_Private_Subprograms): Deal with
+ 	formal types specially.
+ 
+ 2025-10-27  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/25988
+ 	* sem_ch12.adb (Save_Global_References.Reset_Entity): Also call
+ 	Save_Global_Defaults for instances with an expanded name.
+ 	(Save_Global_References.Save_References): Minor code cleanup.
+ 
+ 2025-10-27  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/15800
+ 	* freeze.adb (Freeze_Entity.Freeze_Record_Type): Small cleanup
+ 	in code and comments.
+ 	* gcc-interface/utils.cc (create_field_decl): Assert that the type
+ 	of the field is frozen at this point.
+ 
+ 2025-10-26  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/13370
+ 	* sem_prag.adb (Analyze_Pragma) <Pragma_Machine_Attribute>: Set the
+ 	Has_Delayed_Freeze flag if the argument is not a literal.
+ 
  2025-10-24  Eric Botcazou  <ebotcazou@adacore.com>
  
  	PR ada/80033
diff -Nrcpad gcc-16-20251026/gcc/ada/adaint.c gcc-16-20251102/gcc/ada/adaint.c
*** gcc-16-20251026/gcc/ada/adaint.c	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/adaint.c	Sun Nov  2 22:32:17 2025
***************
*** 107,113 ****
  #ifdef __QNX__
  #include <sys/syspage.h>
  #include <sys/time.h>
- #include <signal.h>
  #endif
  
  #ifdef IN_RTS
--- 107,112 ----
*************** void __gnat_killprocesstree (int pid, in
*** 3720,3787 ****
    */
  }
  
- #if defined (__QNX__)
- 
- static __thread sigset_t set;
- static __thread sigset_t oset;
- static __thread int signals_disabled = 0;
- 
- int __gnat_disable_signals(void)
- {
-     sigemptyset(&set);
-     sigaddset(&set, SIGHUP);
-     sigaddset(&set, SIGINT);
-     sigaddset(&set, SIGQUIT);
-     sigaddset(&set, SIGILL);
-     sigaddset(&set, SIGTRAP);
-     sigaddset(&set, SIGIOT);
-     sigaddset(&set, SIGABRT);
-     sigaddset(&set, SIGEMT);
-     sigaddset(&set, SIGDEADLK);
-     sigaddset(&set, SIGFPE);
-     sigaddset(&set, SIGKILL);
-     sigaddset(&set, SIGBUS);
-     sigaddset(&set, SIGSEGV);
-     sigaddset(&set, SIGSYS);
-     sigaddset(&set, SIGPIPE);
-     sigaddset(&set, SIGALRM);
-     sigaddset(&set, SIGTERM);
-     sigaddset(&set, SIGUSR1);
-     sigaddset(&set, SIGUSR2);
-     sigaddset(&set, SIGCHLD);
-     sigaddset(&set, SIGCLD);
-     sigaddset(&set, SIGPWR);
-     sigaddset(&set, SIGWINCH);
-     sigaddset(&set, SIGURG);
-     sigaddset(&set, SIGPOLL);
-     sigaddset(&set, SIGIO);
-     sigaddset(&set, SIGSTOP);
-     sigaddset(&set, SIGTSTP);
-     sigaddset(&set, SIGCONT);
-     sigaddset(&set, SIGTTIN);
-     sigaddset(&set, SIGTTOU);
-     sigaddset(&set, SIGVTALRM);
-     sigaddset(&set, SIGPROF);
-     sigaddset(&set, SIGXCPU);
-     sigaddset(&set, SIGXFSZ);
-     sigaddset(&set, SIGDOOM);
- 
-     int ret = sigprocmask(SIG_BLOCK, &set, &oset);
-     signals_disabled = !ret;
-     return ret;
- }
- 
- int __gnat_enable_signals(void)
- {
-     if (!signals_disabled) {
-         return 0;
-     }
-     signals_disabled = 0;
-     return sigprocmask(SIG_SETMASK, &oset, 0);
- }
- 
- #endif
- 
  #ifdef __cplusplus
  }
  #endif
--- 3719,3724 ----
diff -Nrcpad gcc-16-20251026/gcc/ada/aspects.adb gcc-16-20251102/gcc/ada/aspects.adb
*** gcc-16-20251026/gcc/ada/aspects.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/aspects.adb	Sun Nov  2 22:32:17 2025
***************
*** 24,29 ****
--- 24,30 ----
  ------------------------------------------------------------------------------
  
  with Atree;          use Atree;
+ with Debug;          use Debug;
  with Einfo;          use Einfo;
  with Einfo.Entities; use Einfo.Entities;
  with Einfo.Utils;    use Einfo.Utils;
*************** package body Aspects is
*** 282,288 ****
     begin
        --  Aspect Unsigned_Base_Range temporarily disabled
  
!       if Name = Name_Unsigned_Base_Range then
           return No_Aspect;
        end if;
  
--- 283,291 ----
     begin
        --  Aspect Unsigned_Base_Range temporarily disabled
  
!       if Name = Name_Unsigned_Base_Range
!         and then not Debug_Flag_Dot_U
!       then
           return No_Aspect;
        end if;
  
diff -Nrcpad gcc-16-20251026/gcc/ada/atree.adb gcc-16-20251102/gcc/ada/atree.adb
*** gcc-16-20251026/gcc/ada/atree.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/atree.adb	Sun Nov  2 22:32:17 2025
*************** package body Atree is
*** 2766,2779 ****
        --  it is global and hence a tree traversal with parents must be finished
        --  before the next tree traversal with parents starts.
  
!       pragma Assert (Parents_Stack.Last = 0);
!       Parents_Stack.Set_Last (0);
  
        Parents_Stack.Append (Parent (Node));
        Result := Traverse (Node);
        Parents_Stack.Decrement_Last;
  
!       pragma Assert (Parents_Stack.Last = 0);
  
        return Result;
     end Traverse_Func_With_Parent;
--- 2766,2779 ----
        --  it is global and hence a tree traversal with parents must be finished
        --  before the next tree traversal with parents starts.
  
!       pragma Assert (Parents_Stack.Is_Empty);
!       Parents_Stack.Clear;
  
        Parents_Stack.Append (Parent (Node));
        Result := Traverse (Node);
        Parents_Stack.Decrement_Last;
  
!       pragma Assert (Parents_Stack.Is_Empty);
  
        return Result;
     end Traverse_Func_With_Parent;
diff -Nrcpad gcc-16-20251026/gcc/ada/debug.adb gcc-16-20251102/gcc/ada/debug.adb
*** gcc-16-20251026/gcc/ada/debug.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/debug.adb	Sun Nov  2 22:32:17 2025
*************** package body Debug is
*** 105,111 ****
     --  d.r  Disable reordering of components in record types
     --  d.s  Strict secondary stack management
     --  d.t  Disable static allocation of library level dispatch tables
!    --  d.u
     --  d.v  Enforce SPARK elaboration rules in SPARK code
     --  d.w  Do not check for infinite loops
     --  d.x  No exception handlers
--- 105,111 ----
     --  d.r  Disable reordering of components in record types
     --  d.s  Strict secondary stack management
     --  d.t  Disable static allocation of library level dispatch tables
!    --  d.u  Enable Unsigned_Base_Range aspect language extension
     --  d.v  Enforce SPARK elaboration rules in SPARK code
     --  d.w  Do not check for infinite loops
     --  d.x  No exception handlers
*************** package body Debug is
*** 800,806 ****
     --       previous dynamic construction of tables. It is there as a possible
     --       work around if we run into trouble with the new implementation.
  
!    --  d.u
  
     --  d.v  This flag enforces the elaboration rules defined in the SPARK
     --       Reference Manual, chapter 7.7, to all SPARK code within a unit. As
--- 800,807 ----
     --       previous dynamic construction of tables. It is there as a possible
     --       work around if we run into trouble with the new implementation.
  
!    --  d.u  Enable the support for Unsigned_Base_Range aspect, attribute, and
!    --       pragma.
  
     --  d.v  This flag enforces the elaboration rules defined in the SPARK
     --       Reference Manual, chapter 7.7, to all SPARK code within a unit. As
diff -Nrcpad gcc-16-20251026/gcc/ada/doc/gnat_rm/obsolescent_features.rst gcc-16-20251102/gcc/ada/doc/gnat_rm/obsolescent_features.rst
*** gcc-16-20251026/gcc/ada/doc/gnat_rm/obsolescent_features.rst	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/doc/gnat_rm/obsolescent_features.rst	Sun Nov  2 22:32:17 2025
*************** historical compatibility purposes.
*** 14,20 ****
  PolyORB
  ========
  
! AWS is a deprecated product. It will be baselined with the GNAT Pro
  release 28. After this release, there will be no new versions of this
  product. Contact your sales representative or send a message to
  sales@adacore.com to get recommendations for replacements.
--- 14,20 ----
  PolyORB
  ========
  
! PolyORB is a deprecated product. It will be baselined with the GNAT Pro
  release 28. After this release, there will be no new versions of this
  product. Contact your sales representative or send a message to
  sales@adacore.com to get recommendations for replacements.
diff -Nrcpad gcc-16-20251026/gcc/ada/einfo-utils.adb gcc-16-20251102/gcc/ada/einfo-utils.adb
*** gcc-16-20251026/gcc/ada/einfo-utils.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/einfo-utils.adb	Sun Nov  2 22:32:17 2025
*************** package body Einfo.Utils is
*** 333,339 ****
  
     function Is_Modular_Integer_Type             (Id : E) return B is
     begin
!       return Ekind (Id) in Modular_Integer_Kind;
     end Is_Modular_Integer_Type;
  
     function Is_Named_Access_Type                (Id : E) return B is
--- 333,340 ----
  
     function Is_Modular_Integer_Type             (Id : E) return B is
     begin
!       return Ekind (Id) in Modular_Integer_Kind
!         and then not Has_Unsigned_Base_Range_Aspect (Base_Type (Id));
     end Is_Modular_Integer_Type;
  
     function Is_Named_Access_Type                (Id : E) return B is
*************** package body Einfo.Utils is
*** 393,399 ****
  
     function Is_Signed_Integer_Type              (Id : E) return B is
     begin
!       return Ekind (Id) in Signed_Integer_Kind;
     end Is_Signed_Integer_Type;
  
     function Is_Subprogram                       (Id : E) return B is
--- 394,403 ----
  
     function Is_Signed_Integer_Type              (Id : E) return B is
     begin
!       return Ekind (Id) in Signed_Integer_Kind
!         or else
!           (Ekind (Id) in Modular_Integer_Kind
!              and then Has_Unsigned_Base_Range_Aspect (Base_Type (Id)));
     end Is_Signed_Integer_Type;
  
     function Is_Subprogram                       (Id : E) return B is
diff -Nrcpad gcc-16-20251026/gcc/ada/einfo.ads gcc-16-20251102/gcc/ada/einfo.ads
*** gcc-16-20251026/gcc/ada/einfo.ads	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/einfo.ads	Sun Nov  2 22:32:17 2025
*************** package Einfo is
*** 5757,5762 ****
--- 5757,5763 ----
     --    Non_Binary_Modulus                   (base type only)
     --    Has_Biased_Representation
     --    Has_Shift_Operator                   (base type only)
+    --    Has_Unsigned_Base_Range_Aspect       (base type only)
     --    No_Predicate_On_Actual
     --    No_Dynamic_Predicate_On_Actual
     --    Type_Low_Bound                       (synth)
diff -Nrcpad gcc-16-20251026/gcc/ada/exp_fixd.adb gcc-16-20251102/gcc/ada/exp_fixd.adb
*** gcc-16-20251026/gcc/ada/exp_fixd.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/exp_fixd.adb	Sun Nov  2 22:32:17 2025
*************** package body Exp_Fixd is
*** 595,601 ****
               Defining_Identifier => Dnn,
               Object_Definition   => New_Occurrence_Of (QR_Typ, Loc),
               Constant_Present    => True,
!              Expression          => Build_Multiply (N, Y, Z)));
  
           Quo :=
             Build_Divide (N,
--- 595,602 ----
               Defining_Identifier => Dnn,
               Object_Definition   => New_Occurrence_Of (QR_Typ, Loc),
               Constant_Present    => True,
!              Expression          =>
!                Build_Conversion (N, QR_Typ, Build_Multiply (N, Y, Z))));
  
           Quo :=
             Build_Divide (N,
*************** package body Exp_Fixd is
*** 656,663 ****
  
     function Build_Multiply (N : Node_Id; L, R : Node_Id) return Node_Id is
        Loc         : constant Source_Ptr := Sloc (N);
!       Left_Type   : constant Entity_Id  := Etype (L);
!       Right_Type  : constant Entity_Id  := Etype (R);
        Left_Size   : Int;
        Right_Size  : Int;
        Result_Type : Entity_Id;
--- 657,664 ----
  
     function Build_Multiply (N : Node_Id; L, R : Node_Id) return Node_Id is
        Loc         : constant Source_Ptr := Sloc (N);
!       Left_Type   : constant Entity_Id  := Base_Type (Etype (L));
!       Right_Type  : constant Entity_Id  := Base_Type (Etype (R));
        Left_Size   : Int;
        Right_Size  : Int;
        Result_Type : Entity_Id;
*************** package body Exp_Fixd is
*** 746,753 ****
  
     function Build_Rem (N : Node_Id; L, R : Node_Id) return Node_Id is
        Loc         : constant Source_Ptr := Sloc (N);
!       Left_Type   : constant Entity_Id  := Etype (L);
!       Right_Type  : constant Entity_Id  := Etype (R);
        Result_Type : Entity_Id;
        Rnode       : Node_Id;
  
--- 747,754 ----
  
     function Build_Rem (N : Node_Id; L, R : Node_Id) return Node_Id is
        Loc         : constant Source_Ptr := Sloc (N);
!       Left_Type   : constant Entity_Id  := Base_Type (Etype (L));
!       Right_Type  : constant Entity_Id  := Base_Type (Etype (R));
        Result_Type : Entity_Id;
        Rnode       : Node_Id;
  
*************** package body Exp_Fixd is
*** 959,965 ****
               Defining_Identifier => Nnn,
               Object_Definition   => New_Occurrence_Of (QR_Typ, Loc),
               Constant_Present    => True,
!              Expression          => Build_Multiply (N, X, Y)),
  
             Make_Object_Declaration (Loc,
               Defining_Identifier => Dnn,
--- 960,967 ----
               Defining_Identifier => Nnn,
               Object_Definition   => New_Occurrence_Of (QR_Typ, Loc),
               Constant_Present    => True,
!              Expression          =>
!                Build_Conversion (N, QR_Typ, Build_Multiply (N, X, Y))),
  
             Make_Object_Declaration (Loc,
               Defining_Identifier => Dnn,
diff -Nrcpad gcc-16-20251026/gcc/ada/exp_util.adb gcc-16-20251102/gcc/ada/exp_util.adb
*** gcc-16-20251026/gcc/ada/exp_util.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/exp_util.adb	Sun Nov  2 22:32:17 2025
*************** package body Exp_Util is
*** 12613,12620 ****
        --  Local variables
  
        Loc          : constant Source_Ptr      := Sloc (Exp);
-       Exp_Type     : constant Entity_Id       := Etype (Exp);
        Svg_Suppress : constant Suppress_Record := Scope_Suppress;
        Def_Id       : Entity_Id;
        E            : Node_Id;
        New_Exp      : Node_Id;
--- 12613,12624 ----
        --  Local variables
  
        Loc          : constant Source_Ptr      := Sloc (Exp);
        Svg_Suppress : constant Suppress_Record := Scope_Suppress;
+       Typ          : constant Entity_Id       := Etype (Exp);
+       Und_Typ      : constant Entity_Id       :=
+         (if Present (Typ) then Underlying_Type (Typ) else Typ);
+       --  The underlying type that drives part of the processing
+ 
        Def_Id       : Entity_Id;
        E            : Node_Id;
        New_Exp      : Node_Id;
*************** package body Exp_Util is
*** 12640,12647 ****
        --  (this happens because routines Duplicate_Subexpr_XX implicitly invoke
        --  Remove_Side_Effects).
  
!       elsif No (Exp_Type)
!         or else Ekind (Exp_Type) = E_Access_Attribute_Type
        then
           return;
  
--- 12644,12652 ----
        --  (this happens because routines Duplicate_Subexpr_XX implicitly invoke
        --  Remove_Side_Effects).
  
!       elsif No (Typ)
!         or else No (Und_Typ)
!         or else Ekind (Und_Typ) = E_Access_Attribute_Type
        then
           return;
  
*************** package body Exp_Util is
*** 12690,12701 ****
        --  anyway, see below). Also do it if we have a volatile reference and
        --  Name_Req is not set (see comments for Side_Effect_Free).
  
!       elsif (Is_Elementary_Type (Exp_Type)
!               or else (Is_Record_Type (Exp_Type)
!                         and then Known_Static_RM_Size (Exp_Type)
!                         and then RM_Size (Exp_Type) <= System_Max_Integer_Size
!                         and then not Has_Discriminants (Exp_Type)
!                         and then not Is_By_Reference_Type (Exp_Type)))
          and then (Variable_Ref
                     or else (not Is_Name_Reference (Exp)
                               and then Nkind (Exp) /= N_Type_Conversion)
--- 12695,12706 ----
        --  anyway, see below). Also do it if we have a volatile reference and
        --  Name_Req is not set (see comments for Side_Effect_Free).
  
!       elsif (Is_Elementary_Type (Und_Typ)
!               or else (Is_Record_Type (Und_Typ)
!                         and then Known_Static_RM_Size (Und_Typ)
!                         and then RM_Size (Und_Typ) <= System_Max_Integer_Size
!                         and then not Has_Discriminants (Und_Typ)
!                         and then not Is_By_Reference_Type (Und_Typ)))
          and then (Variable_Ref
                     or else (not Is_Name_Reference (Exp)
                               and then Nkind (Exp) /= N_Type_Conversion)
*************** package body Exp_Util is
*** 12703,12709 ****
                               and then Is_Volatile_Reference (Exp)))
        then
           Def_Id := Build_Temporary (Loc, 'R', Exp);
!          Set_Etype (Def_Id, Exp_Type);
           Res := New_Occurrence_Of (Def_Id, Loc);
  
           --  If the expression is a packed reference, it must be reanalyzed and
--- 12708,12714 ----
                               and then Is_Volatile_Reference (Exp)))
        then
           Def_Id := Build_Temporary (Loc, 'R', Exp);
!          Set_Etype (Def_Id, Typ);
           Res := New_Occurrence_Of (Def_Id, Loc);
  
           --  If the expression is a packed reference, it must be reanalyzed and
*************** package body Exp_Util is
*** 12719,12725 ****
           end if;
  
           --  Generate:
!          --    Rnn : Exp_Type renames Expr;
  
           --  In GNATprove mode, we prefer to use renamings for intermediate
           --  variables to definition of constants, due to the implicit move
--- 12724,12730 ----
           end if;
  
           --  Generate:
!          --    Rnn : Typ renames Expr;
  
           --  In GNATprove mode, we prefer to use renamings for intermediate
           --  variables to definition of constants, due to the implicit move
*************** package body Exp_Util is
*** 12730,12751 ****
           if Renaming_Req
             or else (GNATprove_Mode
                       and then Is_Object_Reference (Exp)
!                      and then not Is_Scalar_Type (Exp_Type))
           then
              E :=
                Make_Object_Renaming_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Subtype_Mark        => New_Occurrence_Of (Exp_Type, Loc),
                  Name                => Relocate_Node (Exp));
  
           --  Generate:
!          --    Rnn : constant Exp_Type := Expr;
  
           else
              E :=
                Make_Object_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Object_Definition   => New_Occurrence_Of (Exp_Type, Loc),
                  Constant_Present    => True,
                  Expression          => Relocate_Node (Exp));
  
--- 12735,12756 ----
           if Renaming_Req
             or else (GNATprove_Mode
                       and then Is_Object_Reference (Exp)
!                      and then not Is_Scalar_Type (Und_Typ))
           then
              E :=
                Make_Object_Renaming_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Subtype_Mark        => New_Occurrence_Of (Typ, Loc),
                  Name                => Relocate_Node (Exp));
  
           --  Generate:
!          --    Rnn : constant Typ := Expr;
  
           else
              E :=
                Make_Object_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Object_Definition   => New_Occurrence_Of (Typ, Loc),
                  Constant_Present    => True,
                  Expression          => Relocate_Node (Exp));
  
*************** package body Exp_Util is
*** 12801,12807 ****
        elsif Nkind (Exp) = N_Unchecked_Type_Conversion
          and then not Safe_Unchecked_Type_Conversion (Exp)
        then
!          if CW_Or_Needs_Finalization (Exp_Type) then
  
              --  Use a renaming to capture the expression, rather than create
              --  a controlled temporary.
--- 12806,12812 ----
        elsif Nkind (Exp) = N_Unchecked_Type_Conversion
          and then not Safe_Unchecked_Type_Conversion (Exp)
        then
!          if CW_Or_Needs_Finalization (Und_Typ) then
  
              --  Use a renaming to capture the expression, rather than create
              --  a controlled temporary.
*************** package body Exp_Util is
*** 12812,12829 ****
              Insert_Action (Exp,
                Make_Object_Renaming_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Subtype_Mark        => New_Occurrence_Of (Exp_Type, Loc),
                  Name                => Relocate_Node (Exp)));
  
           else
              Def_Id := Build_Temporary (Loc, 'R', Exp);
!             Set_Etype (Def_Id, Exp_Type);
              Res    := New_Occurrence_Of (Def_Id, Loc);
  
              E :=
                Make_Object_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Object_Definition   => New_Occurrence_Of (Exp_Type, Loc),
                  Constant_Present    => not Is_Variable (Exp),
                  Expression          => Relocate_Node (Exp));
  
--- 12817,12834 ----
              Insert_Action (Exp,
                Make_Object_Renaming_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Subtype_Mark        => New_Occurrence_Of (Typ, Loc),
                  Name                => Relocate_Node (Exp)));
  
           else
              Def_Id := Build_Temporary (Loc, 'R', Exp);
!             Set_Etype (Def_Id, Typ);
              Res    := New_Occurrence_Of (Def_Id, Loc);
  
              E :=
                Make_Object_Declaration (Loc,
                  Defining_Identifier => Def_Id,
!                 Object_Definition   => New_Occurrence_Of (Typ, Loc),
                  Constant_Present    => not Is_Variable (Exp),
                  Expression          => Relocate_Node (Exp));
  
*************** package body Exp_Util is
*** 12853,12859 ****
            --  type and we do not have Name_Req set true (see comments for
            --  Side_Effect_Free).
  
!           and then (Name_Req or else not Treat_As_Volatile (Exp_Type)))
        then
           Def_Id := Build_Temporary (Loc, 'R', Exp);
           Res := New_Occurrence_Of (Def_Id, Loc);
--- 12858,12864 ----
            --  type and we do not have Name_Req set true (see comments for
            --  Side_Effect_Free).
  
!           and then (Name_Req or else not Treat_As_Volatile (Und_Typ)))
        then
           Def_Id := Build_Temporary (Loc, 'R', Exp);
           Res := New_Occurrence_Of (Def_Id, Loc);
*************** package body Exp_Util is
*** 12861,12867 ****
           Insert_Action (Exp,
             Make_Object_Renaming_Declaration (Loc,
               Defining_Identifier => Def_Id,
!              Subtype_Mark        => New_Occurrence_Of (Exp_Type, Loc),
               Name                => Relocate_Node (Exp)));
  
        --  Avoid generating a variable-sized temporary, by generating the
--- 12866,12872 ----
           Insert_Action (Exp,
             Make_Object_Renaming_Declaration (Loc,
               Defining_Identifier => Def_Id,
!              Subtype_Mark        => New_Occurrence_Of (Typ, Loc),
               Name                => Relocate_Node (Exp)));
  
        --  Avoid generating a variable-sized temporary, by generating the
*************** package body Exp_Util is
*** 12871,12877 ****
  
        elsif Nkind (Exp) = N_Selected_Component
          and then Nkind (Prefix (Exp)) = N_Function_Call
!         and then Is_Array_Type (Exp_Type)
        then
           Remove_Side_Effects (Prefix (Exp), Name_Req, Variable_Ref);
           goto Leave;
--- 12876,12882 ----
  
        elsif Nkind (Exp) = N_Selected_Component
          and then Nkind (Prefix (Exp)) = N_Function_Call
!         and then Is_Array_Type (Und_Typ)
        then
           Remove_Side_Effects (Prefix (Exp), Name_Req, Variable_Ref);
           goto Leave;
*************** package body Exp_Util is
*** 12890,12898 ****
           --  to the object in the latter case.
  
           if Nkind (Exp) = N_Function_Call
!            and then (Is_Build_In_Place_Result_Type (Exp_Type)
                        or else
!                      Is_Constr_Array_Subt_Of_Unc_With_Controlled (Exp_Type))
             and then Nkind (Parent (Exp)) /= N_Object_Declaration
             and then not Is_Expression_Of_Func_Return (Exp)
           then
--- 12895,12903 ----
           --  to the object in the latter case.
  
           if Nkind (Exp) = N_Function_Call
!            and then (Is_Build_In_Place_Result_Type (Und_Typ)
                        or else
!                      Is_Constr_Array_Subt_Of_Unc_With_Controlled (Und_Typ))
             and then Nkind (Parent (Exp)) /= N_Object_Declaration
             and then not Is_Expression_Of_Func_Return (Exp)
           then
*************** package body Exp_Util is
*** 12904,12914 ****
                 Decl :=
                   Make_Object_Declaration (Loc,
                     Defining_Identifier => Obj,
!                    Object_Definition   => New_Occurrence_Of (Exp_Type, Loc),
                     Expression          => Relocate_Node (Exp));
  
                 Insert_Action (Exp, Decl);
!                Set_Etype (Obj, Exp_Type);
                 Rewrite (Exp, New_Occurrence_Of (Obj, Loc));
                 goto Leave;
              end;
--- 12909,12919 ----
                 Decl :=
                   Make_Object_Declaration (Loc,
                     Defining_Identifier => Obj,
!                    Object_Definition   => New_Occurrence_Of (Typ, Loc),
                     Expression          => Relocate_Node (Exp));
  
                 Insert_Action (Exp, Decl);
!                Set_Etype (Obj, Typ);
                 Rewrite (Exp, New_Occurrence_Of (Obj, Loc));
                 goto Leave;
              end;
*************** package body Exp_Util is
*** 12924,12930 ****
  
           if GNATprove_Mode then
              Res := New_Occurrence_Of (Def_Id, Loc);
!             Ref_Type := Exp_Type;
  
           --  Regular expansion utilizing an access type and 'reference
  
--- 12929,12935 ----
  
           if GNATprove_Mode then
              Res := New_Occurrence_Of (Def_Id, Loc);
!             Ref_Type := Typ;
  
           --  Regular expansion utilizing an access type and 'reference
  
*************** package body Exp_Util is
*** 12934,12940 ****
                  Prefix => New_Occurrence_Of (Def_Id, Loc));
  
              --  Generate:
!             --    type Ann is access all <Exp_Type>;
  
              Ref_Type := Make_Temporary (Loc, 'A');
  
--- 12939,12945 ----
                  Prefix => New_Occurrence_Of (Def_Id, Loc));
  
              --  Generate:
!             --    type Ann is access all Typ;
  
              Ref_Type := Make_Temporary (Loc, 'A');
  
*************** package body Exp_Util is
*** 12944,12951 ****
                  Type_Definition     =>
                    Make_Access_To_Object_Definition (Loc,
                      All_Present        => True,
!                     Subtype_Indication =>
!                       New_Occurrence_Of (Exp_Type, Loc)));
  
              Insert_Action (Exp, Ptr_Typ_Decl);
           end if;
--- 12949,12955 ----
                  Type_Definition     =>
                    Make_Access_To_Object_Definition (Loc,
                      All_Present        => True,
!                     Subtype_Indication => New_Occurrence_Of (Typ, Loc)));
  
              Insert_Action (Exp, Ptr_Typ_Decl);
           end if;
*************** package body Exp_Util is
*** 12974,12989 ****
  
                 if not Analyzed (Exp)
                   and then Nkind (Exp) = N_Aggregate
!                  and then (Is_Array_Type (Exp_Type)
!                            or else Has_Discriminants (Exp_Type))
!                  and then Is_Constrained (Exp_Type)
                 then
                    --  Do not suppress checks associated with the qualified
                    --  expression we are about to introduce (unless those
                    --  checks were already suppressed when Remove_Side_Effects
                    --  was called).
  
!                   if Is_Array_Type (Exp_Type) then
                       Scope_Suppress.Suppress (Length_Check) :=
                         Svg_Suppress.Suppress (Length_Check);
                    else
--- 12978,12993 ----
  
                 if not Analyzed (Exp)
                   and then Nkind (Exp) = N_Aggregate
!                  and then (Is_Array_Type (Und_Typ)
!                             or else Has_Discriminants (Und_Typ))
!                  and then Is_Constrained (Und_Typ)
                 then
                    --  Do not suppress checks associated with the qualified
                    --  expression we are about to introduce (unless those
                    --  checks were already suppressed when Remove_Side_Effects
                    --  was called).
  
!                   if Is_Array_Type (Und_Typ) then
                       Scope_Suppress.Suppress (Length_Check) :=
                         Svg_Suppress.Suppress (Length_Check);
                    else
*************** package body Exp_Util is
*** 12991,12999 ****
                         Svg_Suppress.Suppress (Discriminant_Check);
                    end if;
  
!                   E := Make_Qualified_Expression (Loc,
!                          Subtype_Mark => New_Occurrence_Of (Exp_Type, Loc),
!                          Expression => E);
                 end if;
  
                 New_Exp := Make_Reference (Loc, E);
--- 12995,13004 ----
                         Svg_Suppress.Suppress (Discriminant_Check);
                    end if;
  
!                   E :=
!                     Make_Qualified_Expression (Loc,
!                       Subtype_Mark => New_Occurrence_Of (Typ, Loc),
!                       Expression   => E);
                 end if;
  
                 New_Exp := Make_Reference (Loc, E);
*************** package body Exp_Util is
*** 13041,13047 ****
        --  Finally rewrite the original expression and we are done
  
        Rewrite (Exp, Res);
!       Analyze_And_Resolve (Exp, Exp_Type);
  
     <<Leave>>
        Scope_Suppress := Svg_Suppress;
--- 13046,13052 ----
        --  Finally rewrite the original expression and we are done
  
        Rewrite (Exp, Res);
!       Analyze_And_Resolve (Exp, Typ);
  
     <<Leave>>
        Scope_Suppress := Svg_Suppress;
diff -Nrcpad gcc-16-20251026/gcc/ada/fmap.adb gcc-16-20251102/gcc/ada/fmap.adb
*** gcc-16-20251026/gcc/ada/fmap.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/fmap.adb	Sun Nov  2 22:32:17 2025
*************** package body Fmap is
*** 191,198 ****
        begin
           Unit_Hash_Table.Reset;
           File_Hash_Table.Reset;
!          Path_Mapping.Set_Last (0);
!          File_Mapping.Set_Last (0);
           Last_In_Table := 0;
        end Empty_Tables;
  
--- 191,198 ----
        begin
           Unit_Hash_Table.Reset;
           File_Hash_Table.Reset;
!          Path_Mapping.Clear;
!          File_Mapping.Clear;
           Last_In_Table := 0;
        end Empty_Tables;
  
diff -Nrcpad gcc-16-20251026/gcc/ada/freeze.adb gcc-16-20251102/gcc/ada/freeze.adb
*** gcc-16-20251026/gcc/ada/freeze.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/freeze.adb	Sun Nov  2 22:32:17 2025
*************** package body Freeze is
*** 5646,5659 ****
  
              --  If the component is an access type with an allocator as default
              --  value, the designated type will be frozen by the corresponding
!             --  expression in init_proc. In order to place the freeze node for
!             --  the designated type before that for the current record type,
!             --  freeze it now.
! 
!             --  Same process if the component is an array of access types,
!             --  initialized with an aggregate. If the designated type is
!             --  private, it cannot contain allocators, and it is premature
!             --  to freeze the type, so we check for this as well.
  
              elsif Is_Access_Type (Etype (Comp))
                and then Present (Parent (Comp))
--- 5646,5654 ----
  
              --  If the component is an access type with an allocator as default
              --  value, the designated type will be frozen by the corresponding
!             --  expression in the initialization procedure. In order to place
!             --  the freeze node for the designated type ahead of that for the
!             --  current record type, freeze the designated type right now.
  
              elsif Is_Access_Type (Etype (Comp))
                and then Present (Parent (Comp))
*************** package body Freeze is
*** 5665,5681 ****
                 declare
                    Alloc : constant Node_Id :=
                              Unqualify (Expression (Parent (Comp)));
! 
                 begin
                    if Nkind (Alloc) = N_Allocator then
- 
                       --  If component is pointer to a class-wide type, freeze
                       --  the specific type in the expression being allocated.
                       --  The expression may be a subtype indication, in which
                       --  case freeze the subtype mark.
  
!                      if Is_Class_Wide_Type (Designated_Type (Etype (Comp)))
!                      then
                          if Is_Entity_Name (Expression (Alloc)) then
                             Freeze_And_Append
                               (Entity (Expression (Alloc)), N, Result);
--- 5660,5675 ----
                 declare
                    Alloc : constant Node_Id :=
                              Unqualify (Expression (Parent (Comp)));
!                   Desig_Typ : constant Entity_Id :=
!                                 Designated_Type (Etype (Comp));
                 begin
                    if Nkind (Alloc) = N_Allocator then
                       --  If component is pointer to a class-wide type, freeze
                       --  the specific type in the expression being allocated.
                       --  The expression may be a subtype indication, in which
                       --  case freeze the subtype mark.
  
!                      if Is_Class_Wide_Type (Desig_Typ) then
                          if Is_Entity_Name (Expression (Alloc)) then
                             Freeze_And_Append
                               (Entity (Expression (Alloc)), N, Result);
*************** package body Freeze is
*** 5686,5706 ****
                              (Entity (Subtype_Mark (Expression (Alloc))),
                               N, Result);
                          end if;
!                      elsif Is_Itype (Designated_Type (Etype (Comp))) then
                          Check_Itype (Etype (Comp));
                       else
!                         Freeze_And_Append
!                           (Designated_Type (Etype (Comp)), N, Result);
                       end if;
                    end if;
                 end;
              elsif Is_Access_Type (Etype (Comp))
                and then Is_Itype (Designated_Type (Etype (Comp)))
              then
                 Check_Itype (Etype (Comp));
  
!             --  Freeze the designated type when initializing a component with
!             --  an aggregate in case the aggregate contains allocators.
  
              --     type T is ...;
              --     type T_Ptr is access all T;
--- 5680,5703 ----
                              (Entity (Subtype_Mark (Expression (Alloc))),
                               N, Result);
                          end if;
!                      elsif Is_Itype (Desig_Typ) then
                          Check_Itype (Etype (Comp));
                       else
!                         Freeze_And_Append (Desig_Typ, N, Result);
                       end if;
                    end if;
                 end;
+ 
              elsif Is_Access_Type (Etype (Comp))
                and then Is_Itype (Designated_Type (Etype (Comp)))
              then
                 Check_Itype (Etype (Comp));
  
!             --  Likewise if the component is an array of access types that is
!             --  initialized with an aggregate, in case the aggregate contains
!             --  allocators. But if the designated type is private, it cannot
!             --  contain allocators, and it is premature to freeze the type,
!             --  so we check for this as well.
  
              --     type T is ...;
              --     type T_Ptr is access all T;
*************** package body Freeze is
*** 5712,5724 ****
  
              elsif Is_Array_Type (Etype (Comp))
                and then Is_Access_Type (Component_Type (Etype (Comp)))
              then
                 declare
-                   Comp_Par  : constant Node_Id   := Parent (Comp);
                    Desig_Typ : constant Entity_Id :=
                                  Designated_Type
                                    (Component_Type (Etype (Comp)));
- 
                 begin
                    --  The only case when this sort of freezing is not done is
                    --  when the designated type is class-wide and the root type
--- 5709,5723 ----
  
              elsif Is_Array_Type (Etype (Comp))
                and then Is_Access_Type (Component_Type (Etype (Comp)))
+               and then Present (Parent (Comp))
+               and then Nkind (Parent (Comp)) = N_Component_Declaration
+               and then Present (Expression (Parent (Comp)))
+               and then Nkind (Expression (Parent (Comp))) = N_Aggregate
              then
                 declare
                    Desig_Typ : constant Entity_Id :=
                                  Designated_Type
                                    (Component_Type (Etype (Comp)));
                 begin
                    --  The only case when this sort of freezing is not done is
                    --  when the designated type is class-wide and the root type
*************** package body Freeze is
*** 5740,5751 ****
                    then
                       null;
  
!                   elsif Is_Fully_Defined (Desig_Typ)
!                     and then Present (Comp_Par)
!                     and then Nkind (Comp_Par) = N_Component_Declaration
!                     and then Present (Expression (Comp_Par))
!                     and then Nkind (Expression (Comp_Par)) = N_Aggregate
!                   then
                       Freeze_And_Append (Desig_Typ, N, Result);
                    end if;
                 end;
--- 5739,5745 ----
                    then
                       null;
  
!                   elsif Is_Fully_Defined (Desig_Typ) then
                       Freeze_And_Append (Desig_Typ, N, Result);
                    end if;
                 end;
diff -Nrcpad gcc-16-20251026/gcc/ada/gcc-interface/utils.cc gcc-16-20251102/gcc/ada/gcc-interface/utils.cc
*** gcc-16-20251026/gcc/ada/gcc-interface/utils.cc	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/gcc-interface/utils.cc	Sun Nov  2 22:32:17 2025
*************** create_field_decl (tree name, tree type,
*** 3226,3231 ****
--- 3226,3234 ----
  {
    tree field_decl = build_decl (input_location, FIELD_DECL, name, type);
  
+   /* The type must be frozen at this point.  */
+   gcc_assert (COMPLETE_TYPE_P (type));
+ 
    DECL_CONTEXT (field_decl) = record_type;
    TREE_READONLY (field_decl) = TYPE_READONLY (type);
  
diff -Nrcpad gcc-16-20251026/gcc/ada/gnat_rm.texi gcc-16-20251102/gcc/ada/gnat_rm.texi
*** gcc-16-20251026/gcc/ada/gnat_rm.texi	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/gnat_rm.texi	Sun Nov  2 22:32:17 2025
***************
*** 19,25 ****
  
  @copying
  @quotation
! GNAT Reference Manual , Sep 29, 2025
  
  AdaCore
  
--- 19,25 ----
  
  @copying
  @quotation
! GNAT Reference Manual , Oct 17, 2025
  
  AdaCore
  
*************** historical compatibility purposes.
*** 33627,33633 ****
  @section PolyORB
  
  
! AWS is a deprecated product. It will be baselined with the GNAT Pro
  release 28. After this release, there will be no new versions of this
  product. Contact your sales representative or send a message to
  @email{sales@@adacore.com} to get recommendations for replacements.
--- 33627,33633 ----
  @section PolyORB
  
  
! PolyORB is a deprecated product. It will be baselined with the GNAT Pro
  release 28. After this release, there will be no new versions of this
  product. Contact your sales representative or send a message to
  @email{sales@@adacore.com} to get recommendations for replacements.
diff -Nrcpad gcc-16-20251026/gcc/ada/libgnarl/s-taprop__qnx.adb gcc-16-20251102/gcc/ada/libgnarl/s-taprop__qnx.adb
*** gcc-16-20251026/gcc/ada/libgnarl/s-taprop__qnx.adb	Sun Oct 26 22:32:31 2025
--- gcc-16-20251102/gcc/ada/libgnarl/s-taprop__qnx.adb	Sun Nov  2 22:32:17 2025
*************** package body System.Task_Primitives.Oper
*** 96,101 ****
--- 96,117 ----
     Unblocked_Signal_Mask : aliased sigset_t;
     --  The set of signals that should unblocked in all tasks
  
+    Default_Signal_Mask : aliased sigset_t;
+    --  Default signal mask, used to restore signal mask after thread creation
+ 
+    Default_Signal_Mask_Initialized : Boolean := False;
+    --  Allow to not enable default signals if the default signal mask failed to
+    --  initialize.
+ 
+    procedure Disable_Signals;
+    --  Disable signals before calling pthread_create to avoid a potential
+    --  memory leak on QNX.
+ 
+    procedure Enable_Signals;
+    --  Enable signals after pthread_create and in the created task. Since the
+    --  created task inherits the disabled signals from the parent they have to
+    --  be enabled for each task separately.
+ 
     --  The followings are internal configuration constants needed
  
     Next_Serial_Number : Task_Serial_Number := 100;
*************** package body System.Task_Primitives.Oper
*** 654,659 ****
--- 670,676 ----
  
     procedure Enter_Task (Self_ID : Task_Id) is
     begin
+       Enable_Signals;
        Self_ID.Common.LL.LWP := lwp_self;
  
        Specific.Set (Self_ID);
*************** package body System.Task_Primitives.Oper
*** 765,781 ****
  
        function Thread_Body_Access is new
          Ada.Unchecked_Conversion (System.Address, Thread_Body);
- 
-       function Disable_Signals return Interfaces.C.int with
-         Import,
-         Convention    => C,
-         External_Name => "__gnat_disable_signals";
- 
-       function Enable_Signals return Interfaces.C.int with
-         Import,
-         Convention    => C,
-         External_Name => "__gnat_enable_signals";
- 
     begin
        Adjusted_Stack_Size :=
           Interfaces.C.size_t (Stack_Size + Alternate_Stack_Size);
--- 782,787 ----
*************** package body System.Task_Primitives.Oper
*** 862,881 ****
        --  Restricted.Stages is used). One can verify that by inspecting the
        --  Task_Wrapper procedures.
  
!       Result := Disable_Signals;
!       pragma Assert (Result = 0);
        Result := pthread_create
          (T.Common.LL.Thread'Access,
           Attributes'Access,
           Thread_Body_Access (Wrapper),
           To_Address (T));
        pragma Assert (Result = 0 or else Result = EAGAIN);
  
        Succeeded := Result = 0;
  
-       Result := Enable_Signals;
-       pragma Assert (Result = 0);
- 
        Result := pthread_attr_destroy (Attributes'Access);
        pragma Assert (Result = 0);
     end Create_Task;
--- 868,884 ----
        --  Restricted.Stages is used). One can verify that by inspecting the
        --  Task_Wrapper procedures.
  
!       Disable_Signals;
        Result := pthread_create
          (T.Common.LL.Thread'Access,
           Attributes'Access,
           Thread_Body_Access (Wrapper),
           To_Address (T));
        pragma Assert (Result = 0 or else Result = EAGAIN);
+       Enable_Signals;
  
        Succeeded := Result = 0;
  
        Result := pthread_attr_destroy (Attributes'Access);
        pragma Assert (Result = 0);
     end Create_Task;
*************** package body System.Task_Primitives.Oper
*** 1292,1297 ****
--- 1295,1304 ----
           end if;
        end loop;
  
+       Result := pthread_sigmask
+          (SIG_SETMASK, null, Default_Signal_Mask'Access);
+       Default_Signal_Mask_Initialized := Result = 0;
+ 
        --  Initialize the lock used to synchronize chain of all ATCBs
  
        Initialize_Lock (Single_RTS_Lock'Access, RTS_Lock_Level);
*************** package body System.Task_Primitives.Oper
*** 1378,1381 ****
--- 1385,1440 ----
        pragma Assert (Result = 0);
     end Set_Task_Affinity;
  
+    ---------------------
+    -- Disable_Signals --
+    ---------------------
+ 
+    procedure Disable_Signals
+    is
+       Set    : aliased sigset_t;
+       Result : Interfaces.C.int;
+    begin
+       --  If the default signal mask is not initialized there is no point in
+       --  disabling signals since we can't enable them again. Not enabling them
+       --  might impact the runtimes functionality so we rather accept the
+       --  possible memory leak.
+       if not Default_Signal_Mask_Initialized then
+          return;
+       end if;
+ 
+       --  If any of the operations of setting up the signal mask fails we abort
+       --  disabling the signals. The function to enable the signals doesn't
+       --  need to care about this. It will simply restore the default signal
+       --  mask if it was successfully initialized. If the signals are not
+       --  disabled this is a no-op.
+       Result := sigemptyset (Set'Access);
+       if Result /= 0 then
+          return;
+       end if;
+       for S in SIGHUP .. SIGXFSZ loop
+          Result := sigaddset (Set'Access, Signal (S));
+          if Result /= 0 then
+             return;
+          end if;
+       end loop;
+       Result := pthread_sigmask (SIG_BLOCK, Set'Access, null);
+       pragma Assert (Result = 0);
+    end Disable_Signals;
+ 
+    --------------------
+    -- Enable_Signals --
+    --------------------
+ 
+    procedure Enable_Signals
+    is
+       Result : Interfaces.C.int;
+    begin
+       if not Default_Signal_Mask_Initialized then
+          return;
+       end if;
+       Result := pthread_sigmask
+          (SIG_SETMASK, Default_Signal_Mask'Access, null);
+       pragma Assert (Result = 0);
+    end Enable_Signals;
+ 
  end System.Task_Primitives.Operations;
diff -Nrcpad gcc-16-20251026/gcc/ada/locales.c gcc-16-20251102/gcc/ada/locales.c
*** gcc-16-20251026/gcc/ada/locales.c	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/locales.c	Sun Nov  2 22:32:18 2025
*************** str_get_last_byte (char *lc_all) {
*** 646,652 ****
    return last_byte;
  }
  
! /* Utility function to search in the iso_639_1 table for an iso-639-1 code;
     returns the corresponding iso-639-3 code or NULL if not found. */
  
  static char*
--- 646,652 ----
    return last_byte;
  }
  
! /* Utility function to search in the iso_639 table for an iso-639-1 code;
     returns the corresponding iso-639-3 code or NULL if not found. */
  
  static char*
*************** iso_639_1_to_639_3(char* iso_639_1_code)
*** 670,676 ****
    return NULL;
  }
  
! /* Utility function to search in the iso_639_1 table for a language name;
     returns the corresponding iso-639-3 code or NULL if not found. */
  
  static char*
--- 670,699 ----
    return NULL;
  }
  
! /* Utility function to search in the iso_639 table for an iso-639-3 code;
!    returns 1 if found or 0 if not found. */
! 
! static int
! is_iso_639_3(char* iso_639_3_code) {
!   int len = ARRAY_SIZE (iso_639);
!   char **p = iso_639;
!   int j;
! 
!   p = p + 1;
!   for (j=0; j < len/3; j++) {
!     char* s1 = iso_639_3_code;
!     char* s2 = *p;
! 
!     if (s1[0]==s2[0] && s1[1]==s2[1] && s1[2]==s2[2])
!       return 1;
! 
!     p = p + 3;
!   }
! 
!   return 0;
! }
! 
! /* Utility function to search in the iso_639 table for a language name;
     returns the corresponding iso-639-3 code or NULL if not found. */
  
  static char*
*************** c_get_language_code (char4 p) {
*** 772,778 ****
      /* Copy the ISO-639-3 code (adding a null terminator) */
  
      } else if (lang_length == 3) {
!       str_copy(iso_639_3_code, lc_all, lang_length);
  
      /* Handle conversion of language name to ISO-639-3 */
  
--- 795,802 ----
      /* Copy the ISO-639-3 code (adding a null terminator) */
  
      } else if (lang_length == 3) {
!       if (is_iso_639_3(lc_all))
!         str_copy(iso_639_3_code, lc_all, lang_length);
  
      /* Handle conversion of language name to ISO-639-3 */
  
diff -Nrcpad gcc-16-20251026/gcc/ada/par-ch4.adb gcc-16-20251102/gcc/ada/par-ch4.adb
*** gcc-16-20251026/gcc/ada/par-ch4.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/par-ch4.adb	Sun Nov  2 22:32:18 2025
*************** package body Ch4 is
*** 485,491 ****
              --  Attribute Unsigned_Base_Range temporarily disabled
  
              if not Is_Attribute_Name (Attr_Name)
!               or else Attr_Name = Name_Unsigned_Base_Range
              then
                 if Apostrophe_Should_Be_Semicolon then
                    Expr_Form := EF_Name;
--- 485,492 ----
              --  Attribute Unsigned_Base_Range temporarily disabled
  
              if not Is_Attribute_Name (Attr_Name)
!               or else (Attr_Name = Name_Unsigned_Base_Range
!                          and then not Debug_Flag_Dot_U)
              then
                 if Apostrophe_Should_Be_Semicolon then
                    Expr_Form := EF_Name;
diff -Nrcpad gcc-16-20251026/gcc/ada/par_sco.adb gcc-16-20251102/gcc/ada/par_sco.adb
*** gcc-16-20251026/gcc/ada/par_sco.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/par_sco.adb	Sun Nov  2 22:32:18 2025
*************** package body Par_SCO is
*** 2888,2895 ****
              end;
           end loop;
  
!          --  Clear the pending decisions list
!          Pending_Decisions.Set_Last (0);
        end Process_Pending_Decisions;
  
        -----------------------------
--- 2888,2894 ----
              end;
           end loop;
  
!          Pending_Decisions.Clear;
        end Process_Pending_Decisions;
  
        -----------------------------
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_ch12.adb gcc-16-20251102/gcc/ada/sem_ch12.adb
*** gcc-16-20251026/gcc/ada/sem_ch12.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_ch12.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Ch12 is
*** 480,493 ****
     --  Create a new access type with the given designated type
  
     function Analyze_Associations
!      (N       : Node_Id;
!       Formals : List_Id;
!       F_Copy  : List_Id) return List_Id;
     --  At instantiation time, build the list of associations between formals
     --  and actuals. Each association becomes a renaming declaration for the
     --  formal entity. N is the instantiation node. Formals is the list of
!    --  unanalyzed formals. F_Copy is the analyzed list of formals in the
!    --  generic copy.
  
     procedure Analyze_Subprogram_Instantiation
       (N : Node_Id;
--- 480,495 ----
     --  Create a new access type with the given designated type
  
     function Analyze_Associations
!      (N                : Node_Id;
!       Formals          : List_Id;
!       F_Copy           : List_Id;
!       Parent_Installed : Boolean) return List_Id;
     --  At instantiation time, build the list of associations between formals
     --  and actuals. Each association becomes a renaming declaration for the
     --  formal entity. N is the instantiation node. Formals is the list of
!    --  unanalyzed formals. F_Copy is the list of analyzed formals in the
!    --  generic copy. Parent_Installed is True if the parent has been installed
!    --  during the instantiation.
  
     procedure Analyze_Subprogram_Instantiation
       (N : Node_Id;
*************** package body Sem_Ch12 is
*** 838,846 ****
     --  the same list it is passing to Actual_Decls.
  
     function Instantiate_Formal_Subprogram
!      (Formal          : Node_Id;
!       Actual          : Node_Id;
!       Analyzed_Formal : Node_Id) return Node_Id;
  
     function Instantiate_Formal_Package
       (Formal          : Node_Id;
--- 840,851 ----
     --  the same list it is passing to Actual_Decls.
  
     function Instantiate_Formal_Subprogram
!      (Formal           : Node_Id;
!       Actual           : Node_Id;
!       Analyzed_Formal  : Node_Id;
!       Parent_Installed : Boolean) return Node_Id;
!    --  Parent_Installed is True if the parent has been installed during the
!    --  instantiation.
  
     function Instantiate_Formal_Package
       (Formal          : Node_Id;
*************** package body Sem_Ch12 is
*** 1283,1294 ****
     procedure Analyze_One_Association
       (N                 : Node_Id;
        Assoc             : Associations.Assoc_Rec;
        Result_Renamings  : List_Id;
        Default_Actuals   : List_Id;
        Actuals_To_Freeze : Elist_Id);
!    --  Called by Analyze_Associations for each association. The renamings
!    --  are appended onto Result_Renamings. Defaulted actuals are appended
!    --  onto Default_Actuals, and actuals that require freezing are
     --  appended onto Actuals_To_Freeze.
  
     procedure Analyze_Structural_Associations
--- 1288,1301 ----
     procedure Analyze_One_Association
       (N                 : Node_Id;
        Assoc             : Associations.Assoc_Rec;
+       Parent_Installed  : Boolean;
        Result_Renamings  : List_Id;
        Default_Actuals   : List_Id;
        Actuals_To_Freeze : Elist_Id);
!    --  Called by Analyze_Associations for each association. Parent_Installed
!    --  is True if the parent has been installed during the instantiation. The
!    --  renamings are appended onto Result_Renamings. The defaulted actuals are
!    --  appended onto Default_Actuals, and actuals that require freezing are
     --  appended onto Actuals_To_Freeze.
  
     procedure Analyze_Structural_Associations
*************** package body Sem_Ch12 is
*** 2362,2370 ****
     --------------------------
  
     function Analyze_Associations
!      (N       : Node_Id;
!       Formals : List_Id;
!       F_Copy  : List_Id) return List_Id
     is
        use Associations;
  
--- 2369,2378 ----
     --------------------------
  
     function Analyze_Associations
!      (N                : Node_Id;
!       Formals          : List_Id;
!       F_Copy           : List_Id;
!       Parent_Installed : Boolean) return List_Id
     is
        use Associations;
  
*************** package body Sem_Ch12 is
*** 2412,2417 ****
--- 2420,2426 ----
                 Analyze_One_Association
                   (N,
                    Assoc,
+                   Parent_Installed,
                    Result_Renamings,
                    Default_Actuals,
                    Actuals_To_Freeze);
*************** package body Sem_Ch12 is
*** 2470,2475 ****
--- 2479,2485 ----
     procedure Analyze_One_Association
       (N                 : Node_Id;
        Assoc             : Associations.Assoc_Rec;
+       Parent_Installed  : Boolean;
        Result_Renamings  : List_Id;
        Default_Actuals   : List_Id;
        Actuals_To_Freeze : Elist_Id)
*************** package body Sem_Ch12 is
*** 2736,2742 ****
              else
                 Append_To (Result_Renamings,
                   Instantiate_Formal_Subprogram
!                    (Assoc.Un_Formal, Match, Assoc.An_Formal));
  
                 --  If formal subprogram has contracts, create wrappers
                 --  for it. This is an expansion activity that cannot
--- 2746,2755 ----
              else
                 Append_To (Result_Renamings,
                   Instantiate_Formal_Subprogram
!                    (Assoc.Un_Formal,
!                     Match,
!                     Assoc.An_Formal,
!                     Parent_Installed));
  
                 --  If formal subprogram has contracts, create wrappers
                 --  for it. This is an expansion activity that cannot
*************** package body Sem_Ch12 is
*** 3557,3563 ****
        --  List of primitives made temporarily visible in the instantiation
        --  to match the visibility of the formal type.
  
!       function Build_Local_Package return Node_Id;
        --  The formal package is rewritten so that its parameters are replaced
        --  with corresponding declarations. For parameters with bona fide
        --  associations these declarations are created by Analyze_Associations
--- 3570,3576 ----
        --  List of primitives made temporarily visible in the instantiation
        --  to match the visibility of the formal type.
  
!       function Build_Local_Package (Parent_Installed : Boolean) return Node_Id;
        --  The formal package is rewritten so that its parameters are replaced
        --  with corresponding declarations. For parameters with bona fide
        --  associations these declarations are created by Analyze_Associations
*************** package body Sem_Ch12 is
*** 3569,3575 ****
        -- Build_Local_Package --
        -------------------------
  
!       function Build_Local_Package return Node_Id is
           Decls     : List_Id;
           Pack_Decl : Node_Id;
  
--- 3582,3589 ----
        -- Build_Local_Package --
        -------------------------
  
!       function Build_Local_Package (Parent_Installed : Boolean) return Node_Id
!       is
           Decls     : List_Id;
           Pack_Decl : Node_Id;
  
*************** package body Sem_Ch12 is
*** 3639,3653 ****
                                 Instantiating => True);
  
              begin
!                Generic_Renamings.Set_Last (0);
                 Generic_Renamings_HTable.Reset;
                 Instantiation_Node := N;
  
                 Decls :=
                   Analyze_Associations
!                    (N       => Original_Node (N),
!                     Formals => Generic_Formal_Declarations (Act_Tree),
!                     F_Copy  => Generic_Formal_Declarations (Gen_Decl));
  
                 Vis_Prims_List := Check_Hidden_Primitives (Decls);
              end;
--- 3653,3668 ----
                                 Instantiating => True);
  
              begin
!                Generic_Renamings.Clear;
                 Generic_Renamings_HTable.Reset;
                 Instantiation_Node := N;
  
                 Decls :=
                   Analyze_Associations
!                    (N                => Original_Node (N),
!                     Formals          => Generic_Formal_Declarations (Act_Tree),
!                     F_Copy           => Generic_Formal_Declarations (Gen_Decl),
!                     Parent_Installed => Parent_Installed);
  
                 Vis_Prims_List := Check_Hidden_Primitives (Decls);
              end;
*************** package body Sem_Ch12 is
*** 3782,3788 ****
        --  internal declarations.
  
        begin
!          New_N := Build_Local_Package;
  
        --  If there are errors in the parameter list, Analyze_Associations
        --  raises Instantiation_Error. Patch the declaration to prevent further
--- 3797,3803 ----
        --  internal declarations.
  
        begin
!          New_N := Build_Local_Package (Parent_Installed);
  
        --  If there are errors in the parameter list, Analyze_Associations
        --  raises Instantiation_Error. Patch the declaration to prevent further
*************** package body Sem_Ch12 is
*** 3868,3873 ****
--- 3883,3889 ----
           Renaming_In_Par :=
             Make_Defining_Identifier (Loc, Chars (Gen_Unit));
           Mutate_Ekind (Renaming_In_Par, E_Package);
+          Set_Is_Internal (Renaming_In_Par);
           Set_Is_Not_Self_Hidden (Renaming_In_Par);
           Set_Etype (Renaming_In_Par, Standard_Void_Type);
           Set_Scope (Renaming_In_Par, Parent_Instance);
*************** package body Sem_Ch12 is
*** 4998,5004 ****
        --  inherited from formal packages of parent units, and these are
        --  constructed when the parents are installed.
  
!       Generic_Renamings.Set_Last (0);
        Generic_Renamings_HTable.Reset;
  
        --  Except for an abbreviated instance created to check a formal package,
--- 5014,5020 ----
        --  inherited from formal packages of parent units, and these are
        --  constructed when the parents are installed.
  
!       Generic_Renamings.Clear;
        Generic_Renamings_HTable.Reset;
  
        --  Except for an abbreviated instance created to check a formal package,
*************** package body Sem_Ch12 is
*** 5159,5167 ****
  
           Renamings :=
             Analyze_Associations
!              (N       => N,
!               Formals => Generic_Formal_Declarations (Act_Tree),
!               F_Copy  => Generic_Formal_Declarations (Gen_Decl));
  
           --  Bail out if the instantiation has been turned into something else
  
--- 5175,5184 ----
  
           Renamings :=
             Analyze_Associations
!              (N                => N,
!               Formals          => Generic_Formal_Declarations (Act_Tree),
!               F_Copy           => Generic_Formal_Declarations (Gen_Decl),
!               Parent_Installed => Parent_Installed);
  
           --  Bail out if the instantiation has been turned into something else
  
*************** package body Sem_Ch12 is
*** 6718,6724 ****
              --  Remove package itself from visibility, so it does not
              --  conflict with subprogram.
  
!             Set_Name_Entity_Id (Chars (Pack_Id), Homonym (Pack_Id));
  
              --  Set name and scope of internal subprogram so that the proper
              --  external name will be generated. The proper scope is the scope
--- 6735,6741 ----
              --  Remove package itself from visibility, so it does not
              --  conflict with subprogram.
  
!             Remove_Homonym (Pack_Id);
  
              --  Set name and scope of internal subprogram so that the proper
              --  external name will be generated. The proper scope is the scope
*************** package body Sem_Ch12 is
*** 6962,6968 ****
  
           --  Initialize renamings map, for error checking
  
!          Generic_Renamings.Set_Last (0);
           Generic_Renamings_HTable.Reset;
  
           Create_Instantiation_Source (N, Gen_Unit, S_Adjustment);
--- 6979,6985 ----
  
           --  Initialize renamings map, for error checking
  
!          Generic_Renamings.Clear;
           Generic_Renamings_HTable.Reset;
  
           Create_Instantiation_Source (N, Gen_Unit, S_Adjustment);
*************** package body Sem_Ch12 is
*** 6981,6989 ****
  
           Renamings :=
             Analyze_Associations
!              (N       => N,
!               Formals => Generic_Formal_Declarations (Act_Tree),
!               F_Copy  => Generic_Formal_Declarations (Gen_Decl));
  
           --  Bail out if the instantiation has been turned into something else
  
--- 6998,7007 ----
  
           Renamings :=
             Analyze_Associations
!              (N                => N,
!               Formals          => Generic_Formal_Declarations (Act_Tree),
!               F_Copy           => Generic_Formal_Declarations (Gen_Decl),
!               Parent_Installed => Parent_Installed);
  
           --  Bail out if the instantiation has been turned into something else
  
*************** package body Sem_Ch12 is
*** 7236,7242 ****
           Restore_Hidden_Primitives (Vis_Prims_List);
           Restore_Env;
           Env_Installed := False;
!          Generic_Renamings.Set_Last (0);
           Generic_Renamings_HTable.Reset;
        end if;
  
--- 7254,7260 ----
           Restore_Hidden_Primitives (Vis_Prims_List);
           Restore_Env;
           Env_Installed := False;
!          Generic_Renamings.Clear;
           Generic_Renamings_HTable.Reset;
        end if;
  
*************** package body Sem_Ch12 is
*** 12538,12546 ****
     -----------------------------------
  
     function Instantiate_Formal_Subprogram
!      (Formal          : Node_Id;
!       Actual          : Node_Id;
!       Analyzed_Formal : Node_Id) return Node_Id
     is
        Analyzed_S : constant Entity_Id :=
                       Defining_Unit_Name (Specification (Analyzed_Formal));
--- 12556,12565 ----
     -----------------------------------
  
     function Instantiate_Formal_Subprogram
!      (Formal           : Node_Id;
!       Actual           : Node_Id;
!       Analyzed_Formal  : Node_Id;
!       Parent_Installed : Boolean) return Node_Id
     is
        Analyzed_S : constant Entity_Id :=
                       Defining_Unit_Name (Specification (Analyzed_Formal));
*************** package body Sem_Ch12 is
*** 12548,12560 ****
                       Defining_Unit_Name (Specification (Formal));
  
        function From_Parent_Scope (Subp : Entity_Id) return Boolean;
!       --  If the generic is a child unit, the parent has been installed on the
!       --  scope stack, but a default subprogram cannot resolve to something
!       --  on the parent because that parent is not really part of the visible
!       --  context (it is there to resolve explicit local entities). If the
!       --  default has resolved in this way, we remove the entity from immediate
!       --  visibility and analyze the node again to emit an error message or
!       --  find another visible candidate.
  
        procedure Valid_Actual_Subprogram (Act : Node_Id);
        --  Perform legality check and raise exception on failure
--- 12567,12573 ----
                       Defining_Unit_Name (Specification (Formal));
  
        function From_Parent_Scope (Subp : Entity_Id) return Boolean;
!       --  Return true if Subp is declared in a parent scope of Analyzed_S
  
        procedure Valid_Actual_Subprogram (Act : Node_Id);
        --  Perform legality check and raise exception on failure
*************** package body Sem_Ch12 is
*** 12812,12832 ****
        end if;
  
        --  Gather possible interpretations for the actual before analyzing the
!       --  instance. If overloaded, it will be resolved when analyzing the
!       --  renaming declaration.
  
        if Box_Present (Formal) and then No (Actual) then
           Analyze (Nam);
  
!          if Is_Child_Unit (Scope (Analyzed_S))
!            and then Present (Entity (Nam))
           then
              if not Is_Overloaded (Nam) then
                 if From_Parent_Scope (Entity (Nam)) then
                    Set_Is_Immediately_Visible (Entity (Nam), False);
                    Set_Entity (Nam, Empty);
                    Set_Etype (Nam, Empty);
- 
                    Analyze (Nam);
                    Set_Is_Immediately_Visible (Entity (Nam));
                 end if;
--- 12825,12855 ----
        end if;
  
        --  Gather possible interpretations for the actual before analyzing the
!       --  instance. If the actual is overloaded, then it will be resolved when
!       --  the renaming declaration is analyzed.
  
        if Box_Present (Formal) and then No (Actual) then
           Analyze (Nam);
  
!          --  If the generic is a child unit and the parent has been installed
!          --  during this instantiation (as opposed to having been installed in
!          --  the context of the instantiation at some earlier point), a default
!          --  subprogram cannot resolve to something in the parent because the
!          --  parent is not really part of the visible context (it is there to
!          --  resolve explicit local entities). If the default subprogram has
!          --  been resolved in this way, we remove the entity from immediate
!          --  visibility and analyze the node again to emit an error message
!          --  or find another visible candidate.
! 
!          if Present (Entity (Nam))
!            and then Is_Child_Unit (Scope (Analyzed_S))
!            and then Parent_Installed
           then
              if not Is_Overloaded (Nam) then
                 if From_Parent_Scope (Entity (Nam)) then
                    Set_Is_Immediately_Visible (Entity (Nam), False);
                    Set_Entity (Nam, Empty);
                    Set_Etype (Nam, Empty);
                    Analyze (Nam);
                    Set_Is_Immediately_Visible (Entity (Nam));
                 end if;
*************** package body Sem_Ch12 is
*** 13200,13206 ****
                 --  to capture local names that may be hidden if the generic is
                 --  a child unit.
  
!                if Nkind (Actual) = N_Aggregate then
                    Preanalyze_And_Resolve (Actual, Typ);
                 end if;
  
--- 13223,13229 ----
                 --  to capture local names that may be hidden if the generic is
                 --  a child unit.
  
!                if Nkind (Unqualify (Actual)) = N_Aggregate then
                    Preanalyze_And_Resolve (Actual, Typ);
                 end if;
  
*************** package body Sem_Ch12 is
*** 17639,17644 ****
--- 17662,17669 ----
                 Set_Etype  (N2, E);
              end if;
  
+             --  If the entity is global, save its type in the generic node
+ 
              if Is_Global (E) then
                 Set_Global_Type (N, N2);
  
*************** package body Sem_Ch12 is
*** 17659,17670 ****
--- 17684,17707 ----
                 Set_Etype (N, Empty);
              end if;
  
+             --  If default actuals have been added to a generic instantiation
+             --  and they are global, save them in the generic node.
+ 
              if Nkind (Parent (N)) in N_Generic_Instantiation
                and then N = Name (Parent (N))
              then
                 Save_Global_Defaults (Parent (N), Parent (N2));
              end if;
  
+             if Nkind (Parent (N)) = N_Selected_Component
+               and then N = Selector_Name (Parent (N))
+               and then Nkind (Parent (Parent (N))) in N_Generic_Instantiation
+               and then Parent (N) = Name (Parent (Parent (N)))
+             then
+                Save_Global_Defaults
+                  (Parent (Parent (N)), Parent (Parent (N2)));
+             end if;
+ 
           elsif Nkind (Parent (N)) = N_Selected_Component
             and then Nkind (Parent (N2)) = N_Expanded_Name
           then
*************** package body Sem_Ch12 is
*** 18488,18499 ****
           elsif Nkind (N) = N_Pragma then
              Save_References_In_Pragma (N);
  
           elsif Nkind (N) =  N_Aspect_Specification then
              declare
                 P : constant Node_Id := Parent (N);
-                Expr : Node_Id;
-             begin
  
                 if Permits_Aspect_Specifications (P) then
  
                    --  The capture of global references within aspects
--- 18525,18537 ----
           elsif Nkind (N) = N_Pragma then
              Save_References_In_Pragma (N);
  
+          --  Aspects
+ 
           elsif Nkind (N) =  N_Aspect_Specification then
              declare
                 P : constant Node_Id := Parent (N);
  
+             begin
                 if Permits_Aspect_Specifications (P) then
  
                    --  The capture of global references within aspects
*************** package body Sem_Ch12 is
*** 18505,18519 ****
                    if Requires_Delayed_Save (Original_Node (P)) then
                       null;
  
!                      --  Otherwise save all global references within the
!                      --  aspects
! 
!                   else
!                      Expr := Expression (N);
  
!                      if Present (Expr) then
!                         Save_Global_References (Expr);
!                      end if;
                    end if;
                 end if;
              end;
--- 18543,18553 ----
                    if Requires_Delayed_Save (Original_Node (P)) then
                       null;
  
!                   --  Otherwise save all global references within the
!                   --  expression of the aspect.
  
!                   elsif Present (Expression (N)) then
!                      Save_Global_References (Expression (N));
                    end if;
                 end if;
              end;
*************** package body Sem_Ch12 is
*** 18523,18532 ****
           elsif Nkind (N) = N_Implicit_Label_Declaration then
              null;
  
           else
              Save_References_In_Descendants (N);
           end if;
- 
        end Save_References;
  
        ---------------------
--- 18557,18567 ----
           elsif Nkind (N) = N_Implicit_Label_Declaration then
              null;
  
+          --  Other nodes
+ 
           else
              Save_References_In_Descendants (N);
           end if;
        end Save_References;
  
        ---------------------
*************** package body Sem_Ch12 is
*** 18686,18694 ****
  
     procedure Set_Instance_Of (A : Entity_Id; B : Entity_Id) is
     begin
!       Generic_Renamings.Table (Generic_Renamings.Last) := (A, B, Assoc_Null);
        Generic_Renamings_HTable.Set (Generic_Renamings.Last);
-       Generic_Renamings.Increment_Last;
     end Set_Instance_Of;
  
     --------------------
--- 18721,18728 ----
  
     procedure Set_Instance_Of (A : Entity_Id; B : Entity_Id) is
     begin
!       Generic_Renamings.Append ((A, B, Assoc_Null));
        Generic_Renamings_HTable.Set (Generic_Renamings.Last);
     end Set_Instance_Of;
  
     --------------------
*************** package body Sem_Ch12 is
*** 19321,19359 ****
        --------------------
  
        function Save_And_Reset return Context is
        begin
!          return Result : Context (0 .. Integer (Generic_Renamings.Last)) do
              for Index in Result'Range loop
                 declare
                    Indexed_Assoc : Assoc renames Generic_Renamings.Table
                                                    (Assoc_Ptr (Index));
                    Result_Pair : Binding_Pair renames Result (Index);
                 begin
!                   --  If we have called Increment_Last but have not yet
!                   --  initialized the new last element of the table, then
!                   --  that last element might be invalid. Saving and
!                   --  restoring (especially restoring, it turns out) invalid
!                   --  values can result in exceptions if predicate checking
!                   --  is enabled, so replace invalid values with Empty.
! 
!                   if Indexed_Assoc.Gen_Id'Valid then
!                      Result_Pair.Formal_Id := Indexed_Assoc.Gen_Id;
!                   else
!                      pragma Assert (Index = Result'Last);
!                      Result_Pair.Formal_Id := Empty;
!                   end if;
! 
!                   if Indexed_Assoc.Act_Id'Valid then
!                      Result_Pair.Actual_Id := Indexed_Assoc.Act_Id;
!                   else
!                      pragma Assert (Index = Result'Last);
!                      Result_Pair.Actual_Id := Empty;
!                   end if;
                 end;
              end loop;
  
              Generic_Renamings.Init;
-             Generic_Renamings.Set_Last (-1);
              Generic_Renamings_HTable.Reset;
           end return;
        end Save_And_Reset;
--- 19355,19376 ----
        --------------------
  
        function Save_And_Reset return Context is
+          First : constant Integer := Integer (Generic_Renamings.First);
+          Last  : constant Integer := Integer (Generic_Renamings.Last);
        begin
!          return Result : Context (First .. Last) do
              for Index in Result'Range loop
                 declare
                    Indexed_Assoc : Assoc renames Generic_Renamings.Table
                                                    (Assoc_Ptr (Index));
                    Result_Pair : Binding_Pair renames Result (Index);
                 begin
!                   Result_Pair.Formal_Id := Indexed_Assoc.Gen_Id;
!                   Result_Pair.Actual_Id := Indexed_Assoc.Act_Id;
                 end;
              end loop;
  
              Generic_Renamings.Init;
              Generic_Renamings_HTable.Reset;
           end return;
        end Save_And_Reset;
*************** package body Sem_Ch12 is
*** 19365,19377 ****
        procedure Restore (Saved : Context) is
        begin
           Generic_Renamings.Init;
-          Generic_Renamings.Set_Last (0);
           Generic_Renamings_HTable.Reset;
-          Generic_Renamings.Increment_Last;
           for Pair of Saved loop
              Set_Instance_Of (Pair.Formal_Id, Pair.Actual_Id);
           end loop;
-          Generic_Renamings.Decrement_Last;
        end Restore;
  
     end Instance_Context;
--- 19382,19391 ----
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_ch13.adb gcc-16-20251102/gcc/ada/sem_ch13.adb
*** gcc-16-20251026/gcc/ada/sem_ch13.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_ch13.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Ch13 is
*** 1406,1412 ****
                 Error_Msg_N ("nonoverridable aspect % of type % requires % "
                              & Operation_Kind
                              & "# to be a primitive operation",
!                             Original);
              end;
           end if;
        end Check_Nonoverridable_Aspect_Subprograms;
--- 1406,1412 ----
                 Error_Msg_N ("nonoverridable aspect % of type % requires % "
                              & Operation_Kind
                              & "# to be a primitive operation",
!                             Expr);
              end;
           end if;
        end Check_Nonoverridable_Aspect_Subprograms;
*************** package body Sem_Ch13 is
*** 2372,2378 ****
                 then
                    if A_Id = Aspect_Import then
                       Set_Has_Completion (E);
!                      Set_Is_Imported (E);
  
                       --  An imported object cannot be explicitly initialized
  
--- 2372,2384 ----
                 then
                    if A_Id = Aspect_Import then
                       Set_Has_Completion (E);
! 
!                      --  Do not set Is_Imported on Exceptions, similarly
!                      --  to Sem_Prag.Process_Import_Or_Interface.
! 
!                      if Ekind (E) /= E_Exception then
!                         Set_Is_Imported (E);
!                      end if;
  
                       --  An imported object cannot be explicitly initialized
  
*************** package body Sem_Ch13 is
*** 3590,3595 ****
--- 3596,3602 ----
                              | Aspect_Effective_Reads
                              | Aspect_Effective_Writes
                              | Aspect_Preelaborable_Initialization
+                             | Aspect_Unsigned_Base_Range
              then
                 Error_Msg_Name_1 := Nam;
  
*************** package body Sem_Ch13 is
*** 3703,3708 ****
--- 3710,3722 ----
                    then
                       Delay_Required := False;
  
+                   --  For Unsigned_Base_Range aspect, do not delay becase we
+                   --  need to process it before any type or subtype derivation
+                   --  is analyzed.
+ 
+                   elsif A_Id in Aspect_Unsigned_Base_Range then
+                      Delay_Required := False;
+ 
                    --  All other cases are delayed
  
                    else
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_ch3.adb gcc-16-20251102/gcc/ada/sem_ch3.adb
*** gcc-16-20251026/gcc/ada/sem_ch3.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_ch3.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Ch3 is
*** 8500,8525 ****
           Full_P := Full_View (Parent_Type);
  
           --  A type extension of a type with unknown discriminants is an
!          --  indefinite type that the back-end cannot handle directly.
           --  We treat it as a private type, and build a completion that is
           --  derived from the full view of the parent, and hopefully has
!          --  known discriminants.
  
           --  If the full view of the parent type has an underlying record view,
!          --  use it to generate the underlying record view of this derived type
           --  (required for chains of derivations with unknown discriminants).
  
!          --  Minor optimization: we avoid the generation of useless underlying
!          --  record view entities if the private type declaration has unknown
!          --  discriminants but its corresponding full view has no
!          --  discriminants.
  
           if Has_Unknown_Discriminants (Parent_Type)
             and then Present (Full_P)
             and then (Has_Discriminants (Full_P)
                        or else Present (Underlying_Record_View (Full_P)))
!            and then not In_Open_Scopes (Par_Scope)
!            and then Expander_Active
           then
              declare
                 Full_Der : constant Entity_Id := Make_Temporary (Loc, 'T');
--- 8500,8527 ----
           Full_P := Full_View (Parent_Type);
  
           --  A type extension of a type with unknown discriminants is an
!          --  indefinite type that the back end cannot handle directly.
           --  We treat it as a private type, and build a completion that is
           --  derived from the full view of the parent, and hopefully has
!          --  known discriminants. Note that the type will nevertheless be
!          --  turned into a public type in Build_Derived_Record_Type as for
!          --  any other extension; the only difference is the completion.
  
           --  If the full view of the parent type has an underlying record view,
!          --  use it to generate the underlying record view of the derived type
           --  (required for chains of derivations with unknown discriminants).
  
!          --  Minor optimization: we avoid creating useless underlying record
!          --  view entities when the private type has unknown discriminants but
!          --  its corresponding full view has no discriminants.
  
           if Has_Unknown_Discriminants (Parent_Type)
             and then Present (Full_P)
             and then (Has_Discriminants (Full_P)
                        or else Present (Underlying_Record_View (Full_P)))
!            and then (not In_Open_Scopes (Par_Scope)
!                       or else not (In_Package_Body (Par_Scope)
!                                     or else In_Private_Part (Par_Scope)))
           then
              declare
                 Full_Der : constant Entity_Id := Make_Temporary (Loc, 'T');
*************** package body Sem_Ch3 is
*** 8534,8540 ****
  
                 --  Build anonymous completion, as a derivation from the full
                 --  view of the parent. This is not a completion in the usual
!                --  sense, because the current type is not private.
  
                 Decl :=
                   Make_Full_Type_Declaration (Loc,
--- 8536,8542 ----
  
                 --  Build anonymous completion, as a derivation from the full
                 --  view of the parent. This is not a completion in the usual
!                --  sense, because the derived type is no longer private.
  
                 Decl :=
                   Make_Full_Type_Declaration (Loc,
*************** package body Sem_Ch3 is
*** 8557,8564 ****
--- 8559,8576 ----
                      Underlying_Record_View (Full_P));
                 end if;
  
+                --  If the extension is done in the public part of the scope of
+                --  the parent, its visible declarations have been installed, so
+                --  we first need to uninstall them before reinstalling both the
+                --  private and the visible declarations in this order.
+ 
+                if In_Open_Scopes (Par_Scope) then
+                   Uninstall_Declarations (Par_Scope);
+                end if;
+ 
                 Install_Private_Declarations (Par_Scope);
                 Install_Visible_Declarations (Par_Scope);
+ 
                 Insert_Before (N, Decl);
  
                 --  Mark entity as an underlying record view before analysis,
*************** package body Sem_Ch3 is
*** 8582,8587 ****
--- 8594,8606 ----
  
                 Uninstall_Declarations (Par_Scope);
  
+                --  If the extension is done in the public part of the scope of
+                --  the parent, reinstall the visible declarations only.
+ 
+                if In_Open_Scopes (Par_Scope) then
+                   Install_Visible_Declarations (Par_Scope);
+                end if;
+ 
                 if Etype (Full_Der) = Any_Type then
                    pragma Assert (Serious_Errors_Detected > 0);
                    return;
*************** package body Sem_Ch3 is
*** 10007,10019 ****
                   or else Unknown_Discriminants_Present (N));
  
           --  The partial view of the parent may have unknown discriminants,
!          --  but if the full view has discriminants and the parent type is
!          --  in scope they must be inherited.
  
           elsif Has_Unknown_Discriminants (Parent_Type)
             and then
              (not Has_Discriminants (Parent_Type)
!               or else not In_Open_Scopes (Scope (Parent_Base)))
           then
              Set_Has_Unknown_Discriminants (Derived_Type);
           end if;
--- 10026,10040 ----
                   or else Unknown_Discriminants_Present (N));
  
           --  The partial view of the parent may have unknown discriminants,
!          --  but when its full view has discriminants and is visible, then
!          --  these discriminants must be inherited.
  
           elsif Has_Unknown_Discriminants (Parent_Type)
             and then
              (not Has_Discriminants (Parent_Type)
!               or else not In_Open_Scopes (Scope (Parent_Base))
!               or else not (In_Package_Body (Scope (Parent_Base))
!                             or else In_Private_Part (Scope (Parent_Base))))
           then
              Set_Has_Unknown_Discriminants (Derived_Type);
           end if;
*************** package body Sem_Ch3 is
*** 11287,11293 ****
        --  not. It is OK for the new bound we are creating, but not for
        --  the old one??? Still if it never happens, no problem.
  
!       Analyze_And_Resolve (Bound, Base_Type (Par_T));
  
        if Nkind (Bound) in N_Integer_Literal | N_Real_Literal then
           New_Bound := New_Copy (Bound);
--- 11308,11320 ----
        --  not. It is OK for the new bound we are creating, but not for
        --  the old one??? Still if it never happens, no problem.
  
!       --  This must be disabled on unsigned base range types because their
!       --  base type is a modular type, and their type is a signed integer
!       --  type.
! 
!       if not Has_Unsigned_Base_Range_Aspect (Base_Type (Par_T)) then
!          Analyze_And_Resolve (Bound, Base_Type (Par_T));
!       end if;
  
        if Nkind (Bound) in N_Integer_Literal | N_Real_Literal then
           New_Bound := New_Copy (Bound);
*************** package body Sem_Ch3 is
*** 15138,15156 ****
           Fixup_Bad_Constraint;
           return;
  
!       --  Check that the type has visible discriminants. The type may be
!       --  a private type with unknown discriminants whose full view has
!       --  discriminants which are invisible.
  
!       elsif not Has_Discriminants (T)
!         or else
!           (Has_Unknown_Discriminants (T)
!              and then Is_Private_Type (T))
!       then
           Error_Msg_N ("invalid constraint: type has no discriminant", C);
           Fixup_Bad_Constraint;
           return;
  
        elsif Is_Constrained (E)
          or else (Ekind (E) = E_Class_Wide_Subtype
                    and then Present (Discriminant_Constraint (E)))
--- 15165,15184 ----
           Fixup_Bad_Constraint;
           return;
  
!       --  Check that the type has known discriminants
  
!       elsif Has_Unknown_Discriminants (T) then
!          Error_Msg_N ("invalid constraint: type has unknown discriminants", C);
!          Fixup_Bad_Constraint;
!          return;
! 
!       elsif not Has_Discriminants (T) then
           Error_Msg_N ("invalid constraint: type has no discriminant", C);
           Fixup_Bad_Constraint;
           return;
  
+       --  And is not already constrained
+ 
        elsif Is_Constrained (E)
          or else (Ekind (E) = E_Class_Wide_Subtype
                    and then Present (Discriminant_Constraint (E)))
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_ch7.adb gcc-16-20251102/gcc/ada/sem_ch7.adb
*** gcc-16-20251026/gcc/ada/sem_ch7.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_ch7.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Ch7 is
*** 2266,2272 ****
                          Next_Elmt (Op_Elmt_2);
                       end loop;
  
!                      --  Case 2: We have not found any explicit overriding and
                       --  hence we need to declare the operation (i.e., make it
                       --  visible).
  
--- 2266,2297 ----
                          Next_Elmt (Op_Elmt_2);
                       end loop;
  
!                      --  Case 2: For a formal type, we need to explicitly check
!                      --  whether a local subprogram hides from all visibility
!                      --  the implicitly declared primitive, because subprograms
!                      --  declared in a generic package specification are never
!                      --  primitive for a formal type, even if they happen to
!                      --  override an operation of the type (RM 3.2.3(7.d/2)).
! 
!                      if Is_Generic_Type (E) then
!                         declare
!                            S : Entity_Id;
! 
!                         begin
!                            S := E;
!                            while Present (S) loop
!                               if Chars (S) = Chars (Parent_Subp)
!                                 and then Type_Conformant (Prim_Op, S)
!                               then
!                                  goto Next_Primitive;
!                               end if;
! 
!                               Next_Entity (S);
!                            end loop;
!                         end;
!                      end if;
! 
!                      --  Case 3: We have not found any explicit overriding and
                       --  hence we need to declare the operation (i.e., make it
                       --  visible).
  
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_ch8.adb gcc-16-20251102/gcc/ada/sem_ch8.adb
*** gcc-16-20251026/gcc/ada/sem_ch8.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_ch8.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Ch8 is
*** 5330,5340 ****
     ---------------------
  
     procedure End_Use_Package (N : Node_Id) is
-       Pack      : Entity_Id;
-       Pack_Name : Node_Id;
-       Id        : Entity_Id;
-       Elmt      : Elmt_Id;
- 
        function Type_In_Use (T : Entity_Id; P : Entity_Id) return Boolean;
        --  Check whether type T is declared in P and appears in an active
        --  use_type clause.
--- 5330,5335 ----
*************** package body Sem_Ch8 is
*** 5349,5354 ****
--- 5344,5357 ----
           return Scope (BT) = P and then (In_Use (T) or else In_Use (BT));
        end Type_In_Use;
  
+       --  Local variables
+ 
+       Elmt      : Elmt_Id;
+       Id        : Entity_Id;
+       Pack      : Entity_Id;
+       Pack_Name : Node_Id;
+       Scop      : Entity_Id;
+ 
     --  Start of processing for End_Use_Package
  
     begin
*************** package body Sem_Ch8 is
*** 5373,5389 ****
  
                 --  Preserve use-visibility of operators that are primitive
                 --  operators of a type that is use-visible through an active
!                --  use_type_clause.
  
                 if Nkind (Id) = N_Defining_Operator_Symbol
                   and then
!                    (Type_In_Use (Etype (Id), Pack)
!                      or else Type_In_Use (Etype (First_Formal (Id)), Pack)
                       or else
                         (Present (Next_Formal (First_Formal (Id)))
                           and then
                             Type_In_Use
!                              (Etype (Next_Formal (First_Formal (Id))), Pack)))
                 then
                    null;
                 else
--- 5376,5395 ----
  
                 --  Preserve use-visibility of operators that are primitive
                 --  operators of a type that is use-visible through an active
!                --  use_type_clause. Note that we compare with the scope of
!                --  the operator and not Pack itself, lest Pack be a renaming.
! 
!                Scop := Scope (Id);
  
                 if Nkind (Id) = N_Defining_Operator_Symbol
                   and then
!                    (Type_In_Use (Etype (Id), Scop)
!                      or else Type_In_Use (Etype (First_Formal (Id)), Scop)
                       or else
                         (Present (Next_Formal (First_Formal (Id)))
                           and then
                             Type_In_Use
!                              (Etype (Next_Formal (First_Formal (Id))), Scop)))
                 then
                    null;
                 else
*************** package body Sem_Ch8 is
*** 7225,7230 ****
--- 7231,7238 ----
  
        begin
           while Present (Id) loop
+             --  The immediate case is when Id is an entity of the prefix
+ 
              if Scope (Id) = P_Name then
                 Candidate        := Id;
                 Is_New_Candidate := True;
*************** package body Sem_Ch8 is
*** 7250,7255 ****
--- 7258,7310 ----
                    end if;
                 end if;
  
+             --  If the name of a generic child unit appears within an instance
+             --  of itself, then it is resolved to the renaming of the name of
+             --  the instance built in Sem_Ch12, so we get to the generic parent
+             --  through the renaming.
+ 
+             elsif Ekind (Id) in E_Function | E_Package | E_Procedure
+               and then Present (Renamed_Entity (Id))
+               and then Is_Generic_Instance (Renamed_Entity (Id))
+               and then In_Open_Scopes (Renamed_Entity (Id))
+             then
+                declare
+                   Gen_Inst : constant Entity_Id := Renamed_Entity (Id);
+                   Gen_Par  : constant Entity_Id :=
+                     Generic_Parent
+                       (Specification (Unit_Declaration_Node (Gen_Inst)));
+ 
+                begin
+                   --  The easy case is when Gen_Par is an entity of the prefix
+ 
+                   if Scope (Gen_Par) = P_Name then
+                      Is_New_Candidate := True;
+ 
+                   --  Now the prefix may also be within an instance of itself,
+                   --  but we do not need to go through the renaming for it, as
+                   --  this was done on entry to the procedure.
+ 
+                   elsif Is_Generic_Instance (P_Name)
+                     and then In_Open_Scopes (P_Name)
+                   then
+                      declare
+                         Gen_Par_P : constant Entity_Id :=
+                           Generic_Parent
+                             (Specification (Unit_Declaration_Node (P_Name)));
+ 
+                      begin
+                         if Scope (Gen_Par) = Gen_Par_P then
+                            Is_New_Candidate := True;
+                         else
+                            Is_New_Candidate := False;
+                         end if;
+                      end;
+ 
+                   else
+                      Is_New_Candidate := False;
+                   end if;
+                end;
+ 
              --  Ada 2005 (AI-217): Handle shadow entities associated with
              --  types declared in limited-withed nested packages. We don't need
              --  to handle E_Incomplete_Subtype entities because the entities
*************** package body Sem_Ch8 is
*** 7284,7305 ****
                 Candidate        := Get_Full_View (Id);
                 Is_New_Candidate := True;
  
-             --  An unusual case arises with a fully qualified name for an
-             --  entity local to a generic child unit package, within an
-             --  instantiation of that package. The name of the unit now
-             --  denotes the renaming created within the instance. This is
-             --  only relevant in an instance body, see below.
- 
-             elsif Is_Generic_Instance (Scope (Id))
-               and then In_Open_Scopes (Scope (Id))
-               and then In_Instance_Body
-               and then Ekind (Scope (Id)) = E_Package
-               and then Ekind (Id) = E_Package
-               and then Renamed_Entity (Id) = Scope (Id)
-               and then Is_Immediately_Visible (P_Name)
-             then
-                Is_New_Candidate := True;
- 
              else
                 Is_New_Candidate := False;
              end if;
--- 7339,7344 ----
*************** package body Sem_Ch8 is
*** 7434,7488 ****
                 end if;
  
              else
-                --  Within the instantiation of a child unit, the prefix may
-                --  denote the parent instance, but the selector has the name
-                --  of the original child. That is to say, when A.B appears
-                --  within an instantiation of generic child unit B, the scope
-                --  stack includes an instance of A (P_Name) and an instance
-                --  of B under some other name. We scan the scope to find this
-                --  child instance, which is the desired entity.
-                --  Note that the parent may itself be a child instance, if
-                --  the reference is of the form A.B.C, in which case A.B has
-                --  already been rewritten with the proper entity.
- 
-                if In_Open_Scopes (P_Name)
-                  and then Is_Generic_Instance (P_Name)
-                then
-                   declare
-                      Gen_Par : constant Entity_Id :=
-                                  Generic_Parent (Specification
-                                    (Unit_Declaration_Node (P_Name)));
-                      S : Entity_Id := Current_Scope;
-                      P : Entity_Id;
- 
-                   begin
-                      for J in reverse 0 .. Scope_Stack.Last loop
-                         S := Scope_Stack.Table (J).Entity;
- 
-                         exit when S = Standard_Standard;
- 
-                         if Ekind (S) in E_Function | E_Package | E_Procedure
-                         then
-                            P :=
-                              Generic_Parent (Specification
-                                (Unit_Declaration_Node (S)));
- 
-                            --  Check that P is a generic child of the generic
-                            --  parent of the prefix.
- 
-                            if Present (P)
-                              and then Chars (P) = Chars (Selector)
-                              and then Scope (P) = Gen_Par
-                            then
-                               Id := S;
-                               goto Found;
-                            end if;
-                         end if;
- 
-                      end loop;
-                   end;
-                end if;
- 
                 --  If this is a selection from Ada, System or Interfaces, then
                 --  we assume a missing with for the corresponding package.
  
--- 7473,7478 ----
*************** package body Sem_Ch8 is
*** 7589,7595 ****
           end if;
        end if;
  
-       <<Found>>
        if Comes_From_Source (N)
          and then Is_Remote_Access_To_Subprogram_Type (Id)
          and then Ekind (Id) = E_Access_Subprogram_Type
--- 7579,7584 ----
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_elab.adb gcc-16-20251102/gcc/ada/sem_elab.adb
*** gcc-16-20251026/gcc/ada/sem_elab.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_elab.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Elab is
*** 17469,17475 ****
        --  Stuff that happens only at the outer level
  
        if No (Outer_Scope) then
!          Elab_Visited.Set_Last (0);
  
           --  Nothing to do if current scope is Standard (this is a bit odd, but
           --  it happens in the case of generic instantiations).
--- 17469,17475 ----
        --  Stuff that happens only at the outer level
  
        if No (Outer_Scope) then
!          Elab_Visited.Clear;
  
           --  Nothing to do if current scope is Standard (this is a bit odd, but
           --  it happens in the case of generic instantiations).
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_prag.adb gcc-16-20251102/gcc/ada/sem_prag.adb
*** gcc-16-20251026/gcc/ada/sem_prag.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_prag.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Prag is
*** 10699,10704 ****
--- 10699,10707 ----
              --  the External_Name). For exceptions, the External_Name is the
              --  name of the RTTI structure.
  
+             --  Do not call Set_Is_Imported as that would disable the output
+             --  of the needed exception data structures.
+ 
              --  ??? Emit an error if pragma Import/Export_Exception is present
  
           elsif Nkind (Parent (Def_Id)) = N_Incomplete_Type_Declaration then
*************** package body Sem_Prag is
*** 12690,12696 ****
        --  Pragma Unsigned_Base_Range temporarily disabled
  
        if not Is_Pragma_Name (Pname)
!         or else Pname = Name_Unsigned_Base_Range
        then
           declare
              Msg_Issued : Boolean := False;
--- 12693,12700 ----
        --  Pragma Unsigned_Base_Range temporarily disabled
  
        if not Is_Pragma_Name (Pname)
!         or else (Pname = Name_Unsigned_Base_Range
!                   and then not Debug_Flag_Dot_U)
        then
           declare
              Msg_Issued : Boolean := False;
*************** package body Sem_Prag is
*** 28154,28165 ****
              then
                 Error_Pragma_Arg
                   ("cannot apply pragma %",
!                   "\& is not a signed integer type",
!                   Arg1);
  
              elsif Is_Derived_Type (E) then
                 Error_Pragma_Arg
                   ("pragma % cannot apply to derived type", Arg1);
              end if;
  
              Check_First_Subtype (Arg1);
--- 28158,28180 ----
              then
                 Error_Pragma_Arg
                   ("cannot apply pragma %",
!                   "\& is not a signed integer type", Arg1);
  
              elsif Is_Derived_Type (E) then
                 Error_Pragma_Arg
                   ("pragma % cannot apply to derived type", Arg1);
+ 
+             elsif Is_Generic_Type (E) then
+                Error_Pragma_Arg
+                  ("pragma % cannot apply to formal type", Arg1);
+ 
+             elsif Present (Expr)
+               and then Is_False (Expr_Value (Expr))
+               and then Ekind (Base_Type (E)) = E_Modular_Integer_Type
+               and then Has_Unsigned_Base_Range_Aspect (Base_Type (E))
+             then
+                Error_Pragma_Arg
+                  ("pragma % can only confirm previous True value", Arg1);
              end if;
  
              Check_First_Subtype (Arg1);
*************** package body Sem_Prag is
*** 28167,28183 ****
              --  Create the new unsigned integer base type entity, and apply
              --  the constraint to create the first subtype of E.
  
!             Unsigned_Base_Range_Type_Declaration (E,
!               Def => Type_Definition (Parent (E)));
  
!             Set_Direct_Primitive_Operations (Base_Type (E), New_Elmt_List);
!             Set_Direct_Primitive_Operations (E,
!               Direct_Primitive_Operations (Base_Type (E)));
!             Ensure_Freeze_Node (Base_Type (E));
!             Set_First_Subtype_Link (Freeze_Node (Base_Type (E)), E);
!             Set_Has_Delayed_Freeze (E);
  
!             Set_Has_Unsigned_Base_Range_Aspect (Base_Type (E));
           end Unsigned_Base_Range;
  
           ----------------
--- 28182,28200 ----
              --  Create the new unsigned integer base type entity, and apply
              --  the constraint to create the first subtype of E.
  
!             if No (Expr) or else Is_True (Expr_Value (Expr)) then
!                Unsigned_Base_Range_Type_Declaration (E,
!                  Def => Type_Definition (Parent (E)));
  
!                Set_Direct_Primitive_Operations (Base_Type (E), New_Elmt_List);
!                Set_Direct_Primitive_Operations (E,
!                  Direct_Primitive_Operations (Base_Type (E)));
!                Ensure_Freeze_Node (Base_Type (E));
!                Set_First_Subtype_Link (Freeze_Node (Base_Type (E)), E);
!                Set_Has_Delayed_Freeze (E);
  
!                Set_Has_Unsigned_Base_Range_Aspect (Base_Type (E));
!             end if;
           end Unsigned_Base_Range;
  
           ----------------
*************** package body Sem_Prag is
*** 28770,28775 ****
--- 28787,28803 ----
                          OK  : Boolean;
                          Chr : Character;
  
+                         function Enclose_Ending_Space
+                            (Raw_Str : String) return String
+                         is (if Raw_Str (Raw_Str'Last) = ' '
+                               then '"' & Raw_Str & '"'
+                               else Raw_Str);
+                         function Enclose_Ending_Space
+                            (Raw_Chr : Character) return String
+                         is (Enclose_Ending_Space ((1 => Raw_Chr)));
+                         --  This function ensures that no error message ends
+                         --  with a space, in case we enclose it within quotes.
+ 
                       begin
                          J := 1;
                          while J <= Len loop
*************** package body Sem_Prag is
*** 28801,28807 ****
                                   if not Set_Warning_Switch ('.', Chr) then
                                      Error_Pragma_Arg
                                        ("invalid warning switch character "
!                                        & '.' & Chr, Arg1);
                                   end if;
  
                                --  Non-Dot case
--- 28829,28836 ----
                                   if not Set_Warning_Switch ('.', Chr) then
                                      Error_Pragma_Arg
                                        ("invalid warning switch character "
!                                        & Enclose_Ending_Space ('.' & Chr),
!                                        Arg1);
                                   end if;
  
                                --  Non-Dot case
*************** package body Sem_Prag is
*** 28812,28818 ****
  
                                if not OK then
                                   Error_Pragma_Arg
!                                    ("invalid warning switch character " & Chr,
                                      Arg1);
                                end if;
  
--- 28841,28848 ----
  
                                if not OK then
                                   Error_Pragma_Arg
!                                    ("invalid warning switch character "
!                                     & Enclose_Ending_Space (Chr),
                                      Arg1);
                                end if;
  
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_type.adb gcc-16-20251102/gcc/ada/sem_type.adb
*** gcc-16-20251026/gcc/ada/sem_type.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_type.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Type is
*** 610,623 ****
        First_Interp := All_Interp.Last;
        Add_One_Interp (N, Ent, Etype (N));
  
!       --  For expanded name, pick up all additional entities from the
!       --  same scope, since these are obviously also visible. Note that
!       --  these are not necessarily contiguous on the homonym chain.
  
        if Nkind (N) = N_Expanded_Name then
           H := Homonym (Ent);
           while Present (H) loop
!             if Scope (H) = Scope (Entity (N)) then
                 Add_One_Interp (N, H, Etype (H));
              end if;
  
--- 610,626 ----
        First_Interp := All_Interp.Last;
        Add_One_Interp (N, Ent, Etype (N));
  
!       --  For an expanded name, pick up additional visible entities from
!       --  the same scope. Note that these are not necessarily contiguous
!       --  on the homonym chain.
  
        if Nkind (N) = N_Expanded_Name then
           H := Homonym (Ent);
           while Present (H) loop
!             if Scope (H) = Scope (Entity (N))
!               and then (not Is_Hidden (H)
!                          or else Is_Immediately_Visible (H))
!             then
                 Add_One_Interp (N, H, Etype (H));
              end if;
  
diff -Nrcpad gcc-16-20251026/gcc/ada/sem_util.adb gcc-16-20251102/gcc/ada/sem_util.adb
*** gcc-16-20251026/gcc/ada/sem_util.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/sem_util.adb	Sun Nov  2 22:32:18 2025
*************** package body Sem_Util is
*** 5881,5898 ****
  
              --  Test whether the result type or any of the parameter types of
              --  each subprogram following the type match that type when the
!             --  type is declared in a package spec, is a derived type, or the
!             --  subprogram is marked as primitive. (The Is_Primitive test is
!             --  needed to find primitives of nonderived types in declarative
!             --  parts that happen to override the predefined "=" operator.)
! 
!             --  Note that generic formal subprograms are not considered to be
!             --  primitive operations and thus are never inherited.
  
              if Is_Overloadable (Id)
                and then (Is_Type_In_Pkg
!                          or else Is_Derived_Type (B_Type)
!                          or else Is_Primitive (Id))
                and then Parent_Kind (Parent (Id))
                                      not in N_Formal_Subprogram_Declaration
                and then not Is_Child_Unit (Id)
--- 5881,5900 ----
  
              --  Test whether the result type or any of the parameter types of
              --  each subprogram following the type match that type when the
!             --  type is declared in a package spec, the subprogram is marked as
!             --  primitive, or the subprogram is inherited. Note that the
!             --  Is_Primitive test is needed to find primitives of nonderived
!             --  types in declarative parts that happen to override the
!             --  predefined "=" operator.
  
              if Is_Overloadable (Id)
                and then (Is_Type_In_Pkg
!                          or else Is_Primitive (Id)
!                          or else not Comes_From_Source (Id))
! 
!             --  Generic formal subprograms are not considered to be primitive
!             --  operations and thus are never inherited.
! 
                and then Parent_Kind (Parent (Id))
                                      not in N_Formal_Subprogram_Declaration
                and then not Is_Child_Unit (Id)
diff -Nrcpad gcc-16-20251026/gcc/ada/table.adb gcc-16-20251102/gcc/ada/table.adb
*** gcc-16-20251026/gcc/ada/table.adb	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/table.adb	Sun Nov  2 22:32:19 2025
*************** package body Table is
*** 130,136 ****
  
        begin
           Locked   := False;
!          Last_Val := Min - 1;
           Max      := Min + (Table_Initial * Table_Factor) - 1;
           Length   := Max - Min + 1;
  
--- 130,136 ----
  
        begin
           Locked   := False;
!          Clear;
           Max      := Min + (Table_Initial * Table_Factor) - 1;
           Length   := Max - Min + 1;
  
*************** package body Table is
*** 372,377 ****
--- 372,395 ----
           end if;
        end Set_Item;
  
+       -----------
+       -- Clear --
+       -----------
+ 
+       procedure Clear is
+       begin
+          Last_Val := Min - 1;
+       end Clear;
+ 
+       --------------
+       -- Is_Empty --
+       --------------
+ 
+       function Is_Empty return Boolean is
+       begin
+          return Last_Val = Min - 1;
+       end Is_Empty;
+ 
        --------------
        -- Set_Last --
        --------------
diff -Nrcpad gcc-16-20251026/gcc/ada/table.ads gcc-16-20251102/gcc/ada/table.ads
*** gcc-16-20251026/gcc/ada/table.ads	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/ada/table.ads	Sun Nov  2 22:32:19 2025
*************** package Table is
*** 204,209 ****
--- 204,216 ----
        --  to Index. Item will replace any value already present in the table
        --  at this position.
  
+       procedure Clear;
+       --  Resets Last to its initial value, making the table have no elements.
+       --  No memory deallocation is performed.
+ 
+       function Is_Empty return Boolean;
+       --  Returns whether the table is empty
+ 
        type Saved_Table is private;
        --  Type used for Save/Restore subprograms
  
diff -Nrcpad gcc-16-20251026/gcc/btfout.cc gcc-16-20251102/gcc/btfout.cc
*** gcc-16-20251026/gcc/btfout.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/btfout.cc	Sun Nov  2 22:32:19 2025
*************** btf_add_used_type_1 (ctf_container_ref c
*** 1138,1144 ****
  
  	/* Try to avoid chasing pointers to struct/union types if the
  	   underlying type isn't used.  */
! 	if (check_ptr && seen_ptr && create_fixups)
  	  {
  	    ctf_dtdef_ref ref = dtd->ref_type;
  	    uint32_t ref_kind = btf_dtd_kind (ref);
--- 1138,1145 ----
  
  	/* Try to avoid chasing pointers to struct/union types if the
  	   underlying type isn't used.  */
! 	if (check_ptr && seen_ptr && create_fixups
! 	    && kind != BTF_KIND_TYPEDEF)
  	  {
  	    ctf_dtdef_ref ref = dtd->ref_type;
  	    uint32_t ref_kind = btf_dtd_kind (ref);
diff -Nrcpad gcc-16-20251026/gcc/c/ChangeLog gcc-16-20251102/gcc/c/ChangeLog
*** gcc-16-20251026/gcc/c/ChangeLog	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c/ChangeLog	Sun Nov  2 22:32:19 2025
***************
*** 1,3 ****
--- 1,33 ----
+ 2025-11-01  Martin Uecker  <uecker@tugraz.at>
+ 
+ 	* c-decl.cc (build_compound_literal): Add error.
+ 	* c-parser.cc (c_parser_braced_init): Take bool argument for
+ 	variable size instead of DECL.
+ 	(c_parser_initializer,c_parser_initval): Adapt.
+ 	(c_parser_postfix_expression_after_paren_type): Change
+ 	error to pedwarn.
+ 	* c-typeck.cc (process_init_element): Add error for
+ 	variable-size compound literal with static or constexpr.
+ 
+ 2025-11-01  Martin Uecker  <uecker@tugraz.at>
+ 
+ 	PR c/97986
+ 	* c-parser.cc (c_parser_postfix_expression): Adapt.
+ 	* c-tree.h (c_build_va_arg): Adapt prototype.
+ 	* c-typeck.cc (c_build_va_arg): Handle UB.
+ 
+ 2025-10-30  Qing Zhao  <qing.zhao@oracle.com>
+ 
+ 	* c-typeck.cc (build_access_with_size_for_counted_by): When the element
+ 	type is void, assign size one as the element_size.
+ 
+ 2025-10-27  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR c/122427
+ 	* c-decl.cc (diagnose_mismatched_decls): For FUNCTION_DECL, if
+ 	OLDDECL has TYPE_ATTRIBUTES and NEWDECL doesn't, try the type
+ 	with the OLDDECL attributes.
+ 
  2025-10-24  Joseph Myers  <josmyers@redhat.com>
  
  	* c-parser.cc (c_parser_next_tokens_start_typename)
diff -Nrcpad gcc-16-20251026/gcc/c/c-decl.cc gcc-16-20251102/gcc/c/c-decl.cc
*** gcc-16-20251026/gcc/c/c-decl.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c/c-decl.cc	Sun Nov  2 22:32:19 2025
*************** diagnose_mismatched_decls (tree newdecl,
*** 2337,2346 ****
  		error ("conflicting type qualifiers for %q+D", newdecl);
  	    }
  	  else
! 	    error ("conflicting types for %q+D; have %qT", newdecl, newtype);
! 	  diagnose_arglist_conflict (newdecl, olddecl, newtype, oldtype);
! 	  locate_old_decl (olddecl);
! 	  return false;
  	}
      }
    /* Warn about enum/integer type mismatches.  They are compatible types
--- 2337,2376 ----
  		error ("conflicting type qualifiers for %q+D", newdecl);
  	    }
  	  else
! 	    {
! 	      if (TREE_CODE (olddecl) == FUNCTION_DECL)
! 		{
! 		  tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (olddecl));
! 		  if (attrs && !TYPE_ATTRIBUTES (TREE_TYPE (newdecl)))
! 		    {
! 		      /* Similar to the C++ front-end, for FUNCTION_DECL,
! 			 if OLDDECL has attributes and NEWDECL doesn't,
! 			 try the type with OLDDECL attributes.  */
! 		      tree rettype = TREE_TYPE (newtype);
! 		      tree tryargs = TYPE_ARG_TYPES (newtype);
! 		      tree trytype = c_build_function_type (rettype,
! 							    tryargs);
! 		      trytype = c_build_type_attribute_variant (trytype,
! 								attrs);
! 		      if (comptypes (oldtype, trytype))
! 			{
! 			  *newtypep = newtype = trytype;
! 			  comptypes_result = 1;
! 			}
! 		    }
! 		}
! 
! 	      if (!comptypes_result)
! 		error ("conflicting types for %q+D; have %qT", newdecl,
! 		       newtype);
! 	    }
! 	  if (!comptypes_result)
! 	    {
! 	      diagnose_arglist_conflict (newdecl, olddecl, newtype,
! 					 oldtype);
! 	      locate_old_decl (olddecl);
! 	      return false;
! 	    }
  	}
      }
    /* Warn about enum/integer type mismatches.  They are compatible types
*************** build_compound_literal (location_t loc,
*** 6506,6511 ****
--- 6536,6545 ----
        return error_mark_node;
      }
  
+   if ((TREE_STATIC (decl) || C_DECL_DECLARED_CONSTEXPR (decl))
+       && C_TYPE_VARIABLE_SIZE (type))
+     error_at (loc, "storage size isn%'t constant");
+ 
    if (TREE_STATIC (decl)
        && !verify_type_context (loc, TCTX_STATIC_STORAGE, type))
      return error_mark_node;
diff -Nrcpad gcc-16-20251026/gcc/c/c-parser.cc gcc-16-20251102/gcc/c/c-parser.cc
*** gcc-16-20251026/gcc/c/c-parser.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c/c-parser.cc	Sun Nov  2 22:32:19 2025
*************** static tree c_parser_simple_asm_expr (c_
*** 1767,1773 ****
  static tree c_parser_gnu_attributes (c_parser *);
  static struct c_expr c_parser_initializer (c_parser *, tree);
  static struct c_expr c_parser_braced_init (c_parser *, tree, bool,
! 					   struct obstack *, tree);
  static void c_parser_initelt (c_parser *, struct obstack *);
  static void c_parser_initval (c_parser *, struct c_expr *,
  			      struct obstack *);
--- 1767,1773 ----
  static tree c_parser_gnu_attributes (c_parser *);
  static struct c_expr c_parser_initializer (c_parser *, tree);
  static struct c_expr c_parser_braced_init (c_parser *, tree, bool,
! 					   struct obstack *, bool);
  static void c_parser_initelt (c_parser *, struct obstack *);
  static void c_parser_initval (c_parser *, struct c_expr *,
  			      struct obstack *);
*************** static struct c_expr
*** 6459,6465 ****
  c_parser_initializer (c_parser *parser, tree decl)
  {
    if (c_parser_next_token_is (parser, CPP_OPEN_BRACE))
!     return c_parser_braced_init (parser, NULL_TREE, false, NULL, decl);
    else
      {
        struct c_expr ret;
--- 6459,6467 ----
  c_parser_initializer (c_parser *parser, tree decl)
  {
    if (c_parser_next_token_is (parser, CPP_OPEN_BRACE))
!     return c_parser_braced_init (parser, NULL_TREE, false, NULL,
! 				 decl != error_mark_node
! 				 && C_DECL_VARIABLE_SIZE (decl));
    else
      {
        struct c_expr ret;
*************** location_t last_init_list_comma;
*** 6499,6510 ****
     compound literal, and NULL_TREE for other initializers and for
     nested braced lists.  NESTED_P is true for nested braced lists,
     false for the list of a compound literal or the list that is the
!    top-level initializer in a declaration.  DECL is the declaration for
!    the top-level initializer for a declaration, otherwise NULL_TREE.  */
  
  static struct c_expr
  c_parser_braced_init (c_parser *parser, tree type, bool nested_p,
! 		      struct obstack *outer_obstack, tree decl)
  {
    struct c_expr ret;
    struct obstack braced_init_obstack;
--- 6501,6512 ----
     compound literal, and NULL_TREE for other initializers and for
     nested braced lists.  NESTED_P is true for nested braced lists,
     false for the list of a compound literal or the list that is the
!    top-level initializer in a declaration.  VARSIZE_P indicates
!    wether the object to be initialized has a variable size.  */
  
  static struct c_expr
  c_parser_braced_init (c_parser *parser, tree type, bool nested_p,
! 		      struct obstack *outer_obstack, bool varsize_p)
  {
    struct c_expr ret;
    struct obstack braced_init_obstack;
*************** c_parser_braced_init (c_parser *parser,
*** 6532,6538 ****
      }
    else
      {
!       if (decl && decl != error_mark_node && C_DECL_VARIABLE_SIZE (decl))
  	error_at (brace_loc,
  		  "variable-sized object may not be initialized except "
  		  "with an empty initializer");
--- 6534,6540 ----
      }
    else
      {
!       if (varsize_p)
  	error_at (brace_loc,
  		  "variable-sized object may not be initialized except "
  		  "with an empty initializer");
*************** c_parser_initval (c_parser *parser, stru
*** 6826,6832 ****
  
    if (c_parser_next_token_is (parser, CPP_OPEN_BRACE) && !after)
      init = c_parser_braced_init (parser, NULL_TREE, true,
! 				 braced_init_obstack, NULL_TREE);
    else
      {
        init = c_parser_expr_no_commas (parser, after);
--- 6828,6834 ----
  
    if (c_parser_next_token_is (parser, CPP_OPEN_BRACE) && !after)
      init = c_parser_braced_init (parser, NULL_TREE, true,
! 				 braced_init_obstack, false);
    else
      {
        init = c_parser_expr_no_commas (parser, after);
*************** c_parser_postfix_expression (c_parser *p
*** 11793,11807 ****
  	    else
  	      {
  		tree type_expr = NULL_TREE;
  		expr.value = c_build_va_arg (start_loc, e1.value, loc,
! 					     groktypename (t1, &type_expr, NULL));
! 		if (type_expr)
! 		  {
! 		    expr.value = build2 (C_MAYBE_CONST_EXPR,
! 					 TREE_TYPE (expr.value), type_expr,
! 					 expr.value);
! 		    C_MAYBE_CONST_EXPR_NON_CONST (expr.value) = true;
! 		  }
  		set_c_expr_source_range (&expr, start_loc, end_loc);
  	      }
  	  }
--- 11795,11803 ----
  	    else
  	      {
  		tree type_expr = NULL_TREE;
+ 		tree type = groktypename (t1, &type_expr, NULL);
  		expr.value = c_build_va_arg (start_loc, e1.value, loc,
! 					     type, type_expr);
  		set_c_expr_source_range (&expr, start_loc, end_loc);
  	      }
  	  }
*************** c_parser_postfix_expression_after_paren_
*** 13516,13525 ****
  	       || (scspecs && scspecs->storage_class == csc_static)
  	       || constexpr_p), constexpr_p, &richloc);
    type = groktypename (type_name, &type_expr, &type_expr_const);
    if (type != error_mark_node && C_TYPE_VARIABLE_SIZE (type))
      {
!       error_at (type_loc, "compound literal has variable size");
!       type = error_mark_node;
      }
    else if (TREE_CODE (type) == FUNCTION_TYPE)
      {
--- 13512,13522 ----
  	       || (scspecs && scspecs->storage_class == csc_static)
  	       || constexpr_p), constexpr_p, &richloc);
    type = groktypename (type_name, &type_expr, &type_expr_const);
+   bool varsize_p = false;
    if (type != error_mark_node && C_TYPE_VARIABLE_SIZE (type))
      {
!       pedwarn (type_loc, OPT_Wpedantic, "compound literal has variable size");
!       varsize_p = true;
      }
    else if (TREE_CODE (type) == FUNCTION_TYPE)
      {
*************** c_parser_postfix_expression_after_paren_
*** 13544,13550 ****
  				     (TYPE_QUALS (type_no_array)
  				      | TYPE_QUAL_CONST));
      }
!   init = c_parser_braced_init (parser, type, false, NULL, NULL_TREE);
    if (constexpr_p)
      finish_underspecified_init (NULL_TREE, underspec_state);
    finish_init ();
--- 13541,13547 ----
  				     (TYPE_QUALS (type_no_array)
  				      | TYPE_QUAL_CONST));
      }
!   init = c_parser_braced_init (parser, type, false, NULL, varsize_p);
    if (constexpr_p)
      finish_underspecified_init (NULL_TREE, underspec_state);
    finish_init ();
diff -Nrcpad gcc-16-20251026/gcc/c/c-tree.h gcc-16-20251102/gcc/c/c-tree.h
*** gcc-16-20251026/gcc/c/c-tree.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c/c-tree.h	Sun Nov  2 22:32:19 2025
*************** extern tree c_omp_finish_mapper_clauses
*** 917,923 ****
  extern tree c_omp_mapper_lookup (tree, tree);
  extern tree c_omp_extract_mapper_directive (tree);
  extern tree c_omp_map_array_section (location_t, tree);
! extern tree c_build_va_arg (location_t, tree, location_t, tree);
  extern tree c_finish_transaction (location_t, tree, int);
  extern bool c_tree_equal (tree, tree);
  extern tree c_build_function_call_vec (location_t, const vec<location_t>&,
--- 917,923 ----
  extern tree c_omp_mapper_lookup (tree, tree);
  extern tree c_omp_extract_mapper_directive (tree);
  extern tree c_omp_map_array_section (location_t, tree);
! extern tree c_build_va_arg (location_t, tree, location_t, tree, tree);
  extern tree c_finish_transaction (location_t, tree, int);
  extern bool c_tree_equal (tree, tree);
  extern tree c_build_function_call_vec (location_t, const vec<location_t>&,
diff -Nrcpad gcc-16-20251026/gcc/c/c-typeck.cc gcc-16-20251102/gcc/c/c-typeck.cc
*** gcc-16-20251026/gcc/c/c-typeck.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c/c-typeck.cc	Sun Nov  2 22:32:19 2025
*************** build_access_with_size_for_counted_by (l
*** 3179,3185 ****
    tree result_type = is_fam ? c_build_pointer_type (TREE_TYPE (ref))
  		     : TREE_TYPE (ref);
  
!   tree element_size = TYPE_SIZE_UNIT (TREE_TYPE (TREE_TYPE (ref)));
  
    tree first_param = is_fam
  		     ? c_fully_fold (array_to_pointer_conversion (loc, ref),
--- 3179,3188 ----
    tree result_type = is_fam ? c_build_pointer_type (TREE_TYPE (ref))
  		     : TREE_TYPE (ref);
  
!   tree element_type = TREE_TYPE (TREE_TYPE (ref));
!   tree element_size = VOID_TYPE_P (element_type)
! 		      ? build_one_cst (size_type_node)
! 		      : TYPE_SIZE_UNIT (element_type);
  
    tree first_param = is_fam
  		     ? c_fully_fold (array_to_pointer_conversion (loc, ref),
*************** retry:
*** 12731,12737 ****
  
  	  if (constructor_max_index != NULL_TREE
  	      && (tree_int_cst_lt (constructor_max_index, constructor_index)
! 		  || integer_all_onesp (constructor_max_index)))
  	    {
  	      pedwarn_init (loc, 0,
  			    "excess elements in array initializer");
--- 12734,12742 ----
  
  	  if (constructor_max_index != NULL_TREE
  	      && (tree_int_cst_lt (constructor_max_index, constructor_index)
! 		  || integer_all_onesp (constructor_max_index))
! 	      /* For VLA we got an error already.  */
! 	      && !C_TYPE_VARIABLE_SIZE (constructor_type))
  	    {
  	      pedwarn_init (loc, 0,
  			    "excess elements in array initializer");
*************** c_build_qualified_type (tree type, int t
*** 18432,18438 ****
  /* Build a VA_ARG_EXPR for the C parser.  */
  
  tree
! c_build_va_arg (location_t loc1, tree expr, location_t loc2, tree type)
  {
    if (error_operand_p (type))
      return error_mark_node;
--- 18437,18444 ----
  /* Build a VA_ARG_EXPR for the C parser.  */
  
  tree
! c_build_va_arg (location_t loc1, tree expr, location_t loc2, tree type,
! 		tree type_expr)
  {
    if (error_operand_p (type))
      return error_mark_node;
*************** c_build_va_arg (location_t loc1, tree ex
*** 18456,18465 ****
  		type);
        return error_mark_node;
      }
    else if (warn_cxx_compat && TREE_CODE (type) == ENUMERAL_TYPE)
      warning_at (loc2, OPT_Wc___compat,
  		"C++ requires promoted type, not enum type, in %<va_arg%>");
!   return build_va_arg (loc2, expr, type);
  }
  
  /* Return truthvalue of whether T1 is the same tree structure as T2.
--- 18462,18497 ----
  		type);
        return error_mark_node;
      }
+   else if (TREE_CODE (type) == ARRAY_TYPE && C_TYPE_VARIABLE_SIZE (type)
+ 	   && !flag_isoc99)
+     {
+       error_at (loc2, "second argument to %<va_arg%> is an array type %qT",
+ 		type);
+       return error_mark_node;
+     }
    else if (warn_cxx_compat && TREE_CODE (type) == ENUMERAL_TYPE)
      warning_at (loc2, OPT_Wc___compat,
  		"C++ requires promoted type, not enum type, in %<va_arg%>");
! 
!   if (flag_isoc99 && TREE_CODE (type) == ARRAY_TYPE)
!     {
!       warning_at (loc2, 0, "second argument to %<va_arg%> is an array type %qT",
! 		  type);
!       /* We create a trap but evaluate side effects first.  */
!       tree trapfn = builtin_decl_explicit (BUILT_IN_TRAP);
!       trapfn = build_call_expr_loc (loc2, trapfn, 0);
!       tree e2 = build2 (COMPOUND_EXPR, void_type_node, expr, trapfn);
!       /* Return a compound literal of the right type.  */
!       tree e1 = build_compound_literal (loc2, type, NULL, true, 0, NULL);
!       expr = build2 (COMPOUND_EXPR, type, e2, e1);
!     }
!   else
!     expr = build_va_arg (loc2, expr, type);
! 
!   if (type_expr)
!     expr = build2 (COMPOUND_EXPR, TREE_TYPE (expr), type_expr, expr);
! 
!   return expr;
  }
  
  /* Return truthvalue of whether T1 is the same tree structure as T2.
diff -Nrcpad gcc-16-20251026/gcc/c-family/ChangeLog gcc-16-20251102/gcc/c-family/ChangeLog
*** gcc-16-20251026/gcc/c-family/ChangeLog	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c-family/ChangeLog	Sun Nov  2 22:32:19 2025
***************
*** 1,3 ****
--- 1,14 ----
+ 2025-10-30  Qing Zhao  <qing.zhao@oracle.com>
+ 
+ 	* c-attribs.cc (handle_counted_by_attribute): Allow counted_by for
+ 	void pointer. Issue warnings when -Wpointer-arith is present.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/122325
+ 	* c-opts.cc (c_common_init_options_struct): Remove set of
+ 	flag_default_complex_method.
+ 
  2025-10-22  Jakub Jelinek  <jakub@redhat.com>
  
  	PR c++/122302
diff -Nrcpad gcc-16-20251026/gcc/c-family/c-attribs.cc gcc-16-20251102/gcc/c-family/c-attribs.cc
*** gcc-16-20251026/gcc/c-family/c-attribs.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c-family/c-attribs.cc	Sun Nov  2 22:32:19 2025
*************** handle_counted_by_attribute (tree *node,
*** 2963,2976 ****
  		" array member field", name);
        *no_add_attrs = true;
      }
!   /* This attribute cannot be applied to a pointer to void type.  */
    else if (TREE_CODE (TREE_TYPE (decl)) == POINTER_TYPE
  	   && TREE_CODE (TREE_TYPE (TREE_TYPE (decl))) == VOID_TYPE)
      {
!       error_at (DECL_SOURCE_LOCATION (decl),
! 		"%qE attribute is not allowed for a pointer to void",
! 		name);
!       *no_add_attrs = true;
      }
    /* This attribute cannot be applied to a pointer to function type.  */
    else if (TREE_CODE (TREE_TYPE (decl)) == POINTER_TYPE
--- 2963,2978 ----
  		" array member field", name);
        *no_add_attrs = true;
      }
!   /* This attribute can be applied to a pointer to void type, but issue
!      warning when -Wpointer-arith is presenting.  */
    else if (TREE_CODE (TREE_TYPE (decl)) == POINTER_TYPE
  	   && TREE_CODE (TREE_TYPE (TREE_TYPE (decl))) == VOID_TYPE)
      {
!       if (warn_pointer_arith)
! 	warning_at (DECL_SOURCE_LOCATION (decl),
! 		    OPT_Wpointer_arith,
! 		    "%qE attribute is used for a pointer to void",
! 		    name);
      }
    /* This attribute cannot be applied to a pointer to function type.  */
    else if (TREE_CODE (TREE_TYPE (decl)) == POINTER_TYPE
diff -Nrcpad gcc-16-20251026/gcc/c-family/c-opts.cc gcc-16-20251102/gcc/c-family/c-opts.cc
*** gcc-16-20251026/gcc/c-family/c-opts.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/c-family/c-opts.cc	Sun Nov  2 22:32:19 2025
*************** c_common_init_options_struct (struct gcc
*** 230,236 ****
  
    /* By default, C99-like requirements for complex multiply and divide.  */
    opts->x_flag_complex_method = 2;
-   opts->x_flag_default_complex_method = opts->x_flag_complex_method;
  }
  
  /* Common initialization before calling option handlers.  */
--- 230,235 ----
diff -Nrcpad gcc-16-20251026/gcc/cgraph.cc gcc-16-20251102/gcc/cgraph.cc
*** gcc-16-20251026/gcc/cgraph.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cgraph.cc	Sun Nov  2 22:32:19 2025
*************** cgraph_node::release_body (bool keep_arg
*** 2220,2230 ****
    if (!used_as_abstract_origin && DECL_INITIAL (decl))
      DECL_INITIAL (decl) = error_mark_node;
    release_function_body (decl);
!   if (lto_file_data)
!     {
!       lto_free_function_in_decl_state_for_node (this);
!       lto_file_data = NULL;
!     }
    if (flag_checking && clones)
      {
        /* It is invalid to release body before materializing clones except
--- 2220,2226 ----
    if (!used_as_abstract_origin && DECL_INITIAL (decl))
      DECL_INITIAL (decl) = error_mark_node;
    release_function_body (decl);
!   lto_free_function_in_decl_state_for_node (this);
    if (flag_checking && clones)
      {
        /* It is invalid to release body before materializing clones except
*************** cgraph_node::remove (void)
*** 2336,2345 ****
  	release_body ();
      }
    else
!     {
!       lto_free_function_in_decl_state_for_node (this);
!       lto_file_data = NULL;
!     }
  
    decl = NULL;
    if (call_site_hash)
--- 2332,2338 ----
  	release_body ();
      }
    else
!     lto_free_function_in_decl_state_for_node (this);
  
    decl = NULL;
    if (call_site_hash)
diff -Nrcpad gcc-16-20251026/gcc/cgraph.h gcc-16-20251102/gcc/cgraph.h
*** gcc-16-20251026/gcc/cgraph.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cgraph.h	Sun Nov  2 22:32:19 2025
*************** extern void debuginfo_early_stop (void);
*** 37,49 ****
  class ipa_opt_pass_d;
  typedef ipa_opt_pass_d *ipa_opt_pass;
  
! /* Symbol table consists of functions and variables.
     TODO: add labels and CONST_DECLs.  */
! enum symtab_type
  {
    SYMTAB_SYMBOL,
    SYMTAB_FUNCTION,
!   SYMTAB_VARIABLE
  };
  
  /* Section names are stored as reference counted strings in GGC safe hashtable
--- 37,54 ----
  class ipa_opt_pass_d;
  typedef ipa_opt_pass_d *ipa_opt_pass;
  
! /* Toplevel consists of functions, variables and assembly.
!    Make sure toplevel_type_names in symtab.cc is kept in sync
!    with this.
     TODO: add labels and CONST_DECLs.  */
! enum toplevel_type
  {
+   TOPLEVEL_BASE,
+   TOPLEVEL_ASM,
    SYMTAB_SYMBOL,
    SYMTAB_FUNCTION,
!   SYMTAB_VARIABLE,
!   TOPLEVEL_MAX
  };
  
  /* Section names are stored as reference counted strings in GGC safe hashtable
*************** enum symbol_partitioning_class
*** 100,117 ****
     SYMBOL_DUPLICATE
  };
  
  /* Base of all entries in the symbol table.
     The symtab_node is inherited by cgraph and varpol nodes.  */
! struct GTY((desc ("%h.type"), tag ("SYMTAB_SYMBOL"),
  	    chain_next ("%h.next"), chain_prev ("%h.previous")))
!   symtab_node
  {
  public:
    friend class symbol_table;
  
    /* Constructor.  */
!   explicit symtab_node (symtab_type t)
!     : type (t), resolution (LDPR_UNKNOWN), definition (false), alias (false),
        transparent_alias (false), weakref (false), cpp_implicit_alias (false),
        symver (false), analyzed (false), writeonly (false),
        refuse_visibility_changes (false), externally_visible (false),
--- 105,141 ----
     SYMBOL_DUPLICATE
  };
  
+ /* Base of all toplevel entries.
+    Inherited by symtab_node and asm_node.  */
+ struct GTY ((desc ("%h.type"), tag ("TOPLEVEL_BASE"))) toplevel_node {
+   /* Constructor.  */
+   explicit toplevel_node (toplevel_type t)
+     : lto_file_data (NULL), order (-1), type (t)
+   {}
+ 
+   /* File stream where this node is being written to.  */
+   struct lto_file_decl_data * lto_file_data;
+ 
+   /* Ordering of all cgraph nodes.  */
+   int order;
+ 
+   /* Type of the node.  */
+   ENUM_BITFIELD (toplevel_type) type : 8;
+ };
+ 
  /* Base of all entries in the symbol table.
     The symtab_node is inherited by cgraph and varpol nodes.  */
! struct GTY ((tag ("SYMTAB_SYMBOL"),
  	    chain_next ("%h.next"), chain_prev ("%h.previous")))
!   symtab_node: public toplevel_node
  {
  public:
    friend class symbol_table;
  
    /* Constructor.  */
!   explicit symtab_node (toplevel_type t)
!     : toplevel_node (t),
!       resolution (LDPR_UNKNOWN), definition (false), alias (false),
        transparent_alias (false), weakref (false), cpp_implicit_alias (false),
        symver (false), analyzed (false), writeonly (false),
        refuse_visibility_changes (false), externally_visible (false),
*************** public:
*** 121,129 ****
        used_from_other_partition (false), in_other_partition (false),
        address_taken (false), in_init_priority_hash (false),
        need_lto_streaming (false), offloadable (false), ifunc_resolver (false),
!       order (-1), next_sharing_asm_name (NULL),
        previous_sharing_asm_name (NULL), same_comdat_group (NULL), ref_list (),
!       alias_target (NULL), lto_file_data (NULL), aux (NULL),
        x_comdat_group (NULL_TREE), x_section (NULL), m_uid (-1)
    {}
  
--- 145,153 ----
        used_from_other_partition (false), in_other_partition (false),
        address_taken (false), in_init_priority_hash (false),
        need_lto_streaming (false), offloadable (false), ifunc_resolver (false),
!       next_sharing_asm_name (NULL),
        previous_sharing_asm_name (NULL), same_comdat_group (NULL), ref_list (),
!       alias_target (NULL), aux (NULL),
        x_comdat_group (NULL_TREE), x_section (NULL), m_uid (-1)
    {}
  
*************** public:
*** 498,506 ****
      return m_uid;
    }
  
-   /* Type of the symbol.  */
-   ENUM_BITFIELD (symtab_type) type : 8;
- 
    /* The symbols resolution.  */
    ENUM_BITFIELD (ld_plugin_symbol_resolution) resolution : 8;
  
--- 522,527 ----
*************** public:
*** 609,617 ****
    unsigned ifunc_resolver : 1;
  
  
-   /* Ordering of all symtab entries.  */
-   int order;
- 
    /* Declaration representing the symbol.  */
    tree decl;
  
--- 630,635 ----
*************** public:
*** 642,650 ****
       Once alias is resolved, this pointer become NULL.  */
    tree alias_target;
  
-   /* File stream where this node is being written to.  */
-   struct lto_file_decl_data * lto_file_data;
- 
    void *GTY ((skip)) aux;
  
    /* Comdat group the symbol is in.  Can be private if GGC allowed that.  */
--- 660,665 ----
*************** private:
*** 2224,2236 ****
  
  /* Every top level asm statement is put into a asm_node.  */
  
! struct GTY(()) asm_node {
    /* Next asm node.  */
    asm_node *next;
    /* String for this asm node.  */
    tree asm_str;
-   /* Ordering of all cgraph nodes.  */
-   int order;
  };
  
  /* Report whether or not THIS symtab node is a function, aka cgraph_node.  */
--- 2239,2252 ----
  
  /* Every top level asm statement is put into a asm_node.  */
  
! struct GTY ((tag ("TOPLEVEL_ASM"))) asm_node: public toplevel_node {
!   explicit asm_node (tree asm_str)
!     : toplevel_node (TOPLEVEL_ASM), next (NULL), asm_str (asm_str)
!   {}
    /* Next asm node.  */
    asm_node *next;
    /* String for this asm node.  */
    tree asm_str;
  };
  
  /* Report whether or not THIS symtab node is a function, aka cgraph_node.  */
*************** is_a_helper <varpool_node *>::test (symt
*** 2253,2258 ****
--- 2269,2315 ----
    return p && p->type == SYMTAB_VARIABLE;
  }
  
+ /* Report whether or not THIS toplevel node is a function, aka cgraph_node.  */
+ 
+ template <>
+ template <>
+ inline bool
+ is_a_helper <cgraph_node *>::test (toplevel_node *p)
+ {
+   return p && p->type == SYMTAB_FUNCTION;
+ }
+ 
+ /* Report whether or not THIS toplevel node is a variable, aka varpool_node.  */
+ 
+ template <>
+ template <>
+ inline bool
+ is_a_helper <varpool_node *>::test (toplevel_node *p)
+ {
+   return p && p->type == SYMTAB_VARIABLE;
+ }
+ 
+ /* Report whether or not THIS toplevel node is a symtab_node.  */
+ 
+ template <>
+ template <>
+ inline bool
+ is_a_helper <symtab_node *>::test (toplevel_node *p)
+ {
+   return p && p->type >= SYMTAB_SYMBOL;
+ }
+ 
+ /* Report whether or not THIS toplevel node is a toplevel assembly, aka
+    asm_node.  */
+ 
+ template <>
+ template <>
+ inline bool
+ is_a_helper <asm_node *>::test (toplevel_node *p)
+ {
+   return p && p->type == TOPLEVEL_ASM;
+ }
+ 
  typedef void (*cgraph_edge_hook)(cgraph_edge *, void *);
  typedef void (*cgraph_node_hook)(cgraph_node *, void *);
  typedef void (*varpool_node_hook)(varpool_node *, void *);
*************** symbol_table::finalize_toplevel_asm (tre
*** 2919,2928 ****
  {
    asm_node *node;
  
!   node = ggc_cleared_alloc<asm_node> ();
!   node->asm_str = asm_str;
    node->order = order++;
-   node->next = NULL;
  
    if (asmnodes == NULL)
      asmnodes = node;
--- 2976,2983 ----
  {
    asm_node *node;
  
!   node = new (ggc_cleared_alloc<asm_node> ()) asm_node (asm_str);
    node->order = order++;
  
    if (asmnodes == NULL)
      asmnodes = node;
diff -Nrcpad gcc-16-20251026/gcc/cobol/ChangeLog gcc-16-20251102/gcc/cobol/ChangeLog
*** gcc-16-20251026/gcc/cobol/ChangeLog	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cobol/ChangeLog	Sun Nov  2 22:32:19 2025
***************
*** 1,3 ****
--- 1,7 ----
+ 2025-10-26  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* Make-lang.in ($(srcdir)/cobol/token_names.h): Silence recipe.
+ 
  2025-10-23  Robert Dubner  <rdubner@symas.com>
  
  	* genapi.cc (parser_alphabet): Alphabet encoding.
diff -Nrcpad gcc-16-20251026/gcc/common.opt gcc-16-20251102/gcc/common.opt
*** gcc-16-20251026/gcc/common.opt	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/common.opt	Sun Nov  2 22:32:19 2025
*************** bool in_lto_p = false
*** 53,61 ****
  Variable
  enum incremental_link flag_incremental_link = INCREMENTAL_LINK_NONE
  
- Variable
- int flag_default_complex_method = 1
- 
  ; Language specific warning pass for unused results.
  Variable
  bool flag_warn_unused_result = false
--- 53,58 ----
diff -Nrcpad gcc-16-20251026/gcc/config/aarch64/aarch64-simd.md gcc-16-20251102/gcc/config/aarch64/aarch64-simd.md
*** gcc-16-20251026/gcc/config/aarch64/aarch64-simd.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/aarch64/aarch64-simd.md	Sun Nov  2 22:32:19 2025
***************
*** 3223,3228 ****
--- 3223,3229 ----
      DONE;
    }
  )
+ 
  (define_insn "extend<mode><Vwide>2"
    [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
  	(float_extend:<VWIDE>
***************
*** 3232,3237 ****
--- 3233,3261 ----
    [(set_attr "type" "neon_fp_cvt_widen_s")]
  )
  
+ /* A BF->SF is a shift left of 16, however shifts are expensive and the generic
+    middle-end expansion would force through DI move.  Instead use EXT to do the
+    shift to get better throughput and don't go through GPRs.  */
+ 
+ (define_expand "extendbfsf2"
+   [(set (match_operand:SF 0 "register_operand" "=w")
+ 	(float_extend:SF
+ 	  (match_operand:BF 1 "register_operand" "w")))]
+   "TARGET_SIMD"
+ {
+   rtx tmp0 = aarch64_gen_shareable_zero (V8BFmode);
+   rtx op0 = force_lowpart_subreg (V8BFmode, operands[1], BFmode);
+   rtx res = gen_reg_rtx (V8BFmode);
+   emit_insn (gen_aarch64_extv8bf (res, tmp0, op0, gen_int_mode (7, SImode)));
+   /* Subregs between floating point modes aren't allowed to change size, so go
+      through V4SFmode.  */
+   res = force_lowpart_subreg (V4SFmode, res, V8BFmode);
+   res = force_lowpart_subreg (SFmode, res, V4SFmode);
+   emit_move_insn (operands[0], res);
+   DONE;
+ })
+ 
+ 
  ;; Float narrowing operations.
  
  (define_insn "aarch64_float_trunc_rodd_df"
diff -Nrcpad gcc-16-20251026/gcc/config/avr/avr.cc gcc-16-20251102/gcc/config/avr/avr.cc
*** gcc-16-20251026/gcc/config/avr/avr.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/avr/avr.cc	Sun Nov  2 22:32:19 2025
*************** avr_load_libgcc_p (rtx op)
*** 3272,3278 ****
  
    return (n_bytes > 2
  	  && !AVR_HAVE_LPMX
! 	  && avr_mem_flash_p (op));
  }
  
  
--- 3272,3279 ----
  
    return (n_bytes > 2
  	  && !AVR_HAVE_LPMX
! 	  && avr_mem_flash_p (op)
! 	  && MEM_ADDR_SPACE (op) == ADDR_SPACE_FLASH);
  }
  
  
*************** avr_out_lpm_no_lpmx (rtx_insn *insn, rtx
*** 3624,3629 ****
--- 3625,3670 ----
  	    avr_asm_len ("sbiw %2,1", xop, plen, 1);
  
  	  break; /* 2 */
+ 
+ 	/* cases 3 and 4 are only needed with ELPM but no ELPMx.  */
+ 
+ 	case 3:
+ 	  if (REGNO (dest) == REG_Z - 2
+ 	      && !reg_unused_after (insn, all_regs_rtx[REG_31]))
+ 	    avr_asm_len ("push r31", xop, plen, 1);
+ 
+ 	  avr_asm_len ("%4lpm $ mov %A0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  avr_asm_len ("%4lpm $ mov %B0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  avr_asm_len ("%4lpm $ mov %C0,%3", xop, plen, 2);
+ 
+ 	  if (REGNO (dest) == REG_Z - 2)
+ 	    {
+ 	      if (!reg_unused_after (insn, all_regs_rtx[REG_31]))
+ 		avr_asm_len ("pop r31", xop, plen, 1);
+ 	    }
+ 	  else if (!reg_unused_after (insn, addr))
+ 	    avr_asm_len ("sbiw %2,2", xop, plen, 1);
+ 
+ 	  break; /* 3 */
+ 
+ 	case 4:
+ 	  avr_asm_len ("%4lpm $ mov %A0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  avr_asm_len ("%4lpm $ mov %B0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  if (REGNO (dest) != REG_Z - 2)
+ 	    {
+ 	      avr_asm_len ("%4lpm $ mov %C0,%3 $ adiw %2,1", xop, plen, 3);
+ 	      avr_asm_len ("%4lpm $ mov %D0,%3", xop, plen, 2);
+ 	      if (!reg_unused_after (insn, addr))
+ 		avr_asm_len ("sbiw %2,3", xop, plen, 1);
+ 	    }
+ 	  else
+ 	    {
+ 	      avr_asm_len ("%4lpm $ push %3 $ adiw %2,1", xop, plen, 3);
+ 	      avr_asm_len ("%4lpm $ mov %D0,%3", xop, plen, 2);
+ 	      avr_asm_len ("pop $C0", xop, plen, 1);
+ 	    }
+ 
+ 	  break; /* 4 */
  	}
  
        break; /* REG */
diff -Nrcpad gcc-16-20251026/gcc/config/avr/avr.md gcc-16-20251102/gcc/config/avr/avr.md
*** gcc-16-20251026/gcc/config/avr/avr.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/avr/avr.md	Sun Nov  2 22:32:19 2025
***************
*** 3947,3955 ****
                               (match_operand:PSI 2 "nonmemory_operand" "")))
                (clobber (reg:HI 26))
                (clobber (reg:DI 18))])]
!   "AVR_HAVE_MUL"
    {
!     if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
--- 3947,3963 ----
                               (match_operand:PSI 2 "nonmemory_operand" "")))
                (clobber (reg:HI 26))
                (clobber (reg:DI 18))])]
!   "AVR_HAVE_MUL
!    || (avropt_pr118012
!        /* AVR_TINY passes args on the stack, so we cannot work
!           around PR118012 like this. */
!        && ! AVR_TINY)"
    {
!     if (!AVR_HAVE_MUL)
!       {
!         operands[2] = force_reg (PSImode, operands[2]);
!       }
!     else if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
***************
*** 4038,4044 ****
                    (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
     (clobber (reg:HI 26))
     (clobber (reg:DI 18))]
!   "AVR_HAVE_MUL && !reload_completed"
    { gcc_unreachable(); }
    "&& 1"
    [(set (reg:PSI 18)
--- 4046,4054 ----
                    (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
     (clobber (reg:HI 26))
     (clobber (reg:DI 18))]
!   "!reload_completed
!    && (AVR_HAVE_MUL
!        || (avropt_pr118012 && !AVR_TINY))"
    { gcc_unreachable(); }
    "&& 1"
    [(set (reg:PSI 18)
***************
*** 4048,4060 ****
     (parallel [(set (reg:PSI 22)
                     (mult:PSI (reg:PSI 22)
                               (reg:PSI 18)))
!               (clobber (reg:QI 21))
!               (clobber (reg:QI 25))
!               (clobber (reg:HI 26))])
     (set (match_dup 0)
          (reg:PSI 22))]
    {
!     if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
--- 4058,4087 ----
     (parallel [(set (reg:PSI 22)
                     (mult:PSI (reg:PSI 22)
                               (reg:PSI 18)))
!               (clobber (match_dup 3))
!               (clobber (match_dup 4))
!               (clobber (match_dup 5))])
     (set (match_dup 0)
          (reg:PSI 22))]
    {
!     if (AVR_HAVE_MUL)
!       {
!         operands[3] = gen_rtx_REG (QImode, REG_21);
!         operands[4] = gen_rtx_REG (QImode, REG_25);
!         operands[5] = gen_rtx_REG (HImode, REG_26);
!       }
!     else
!       {
!         operands[3] = gen_rtx_REG (SImode, REG_18);
!         operands[4] = gen_rtx_SCRATCH (QImode);
!         operands[5] = gen_rtx_SCRATCH (HImode);
!       }
! 
!     if (!AVR_HAVE_MUL)
!       {
!         operands[2] = force_reg (PSImode, operands[2]);
!       }
!     else if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
***************
*** 4106,4111 ****
--- 4133,4164 ----
    "%~call __mulpsi3"
    [(set_attr "type" "xcall")])
  
+ (define_insn_and_split "*mulpsi3-nomul.libgcc_split"
+   [(set (reg:PSI 22)
+         (mult:PSI (reg:PSI 22)
+                   (reg:PSI 18)))
+    (clobber (reg:SI 18))
+    (clobber (scratch:QI))
+    (clobber (scratch:HI))]
+   "!AVR_HAVE_MUL && avropt_pr118012 && !AVR_TINY"
+   "#"
+   "&& reload_completed"
+   [(scratch)]
+   { DONE_ADD_CCC })
+ 
+ (define_insn "*mulpsi3-nomul.libgcc"
+   [(set (reg:PSI 22)
+         (mult:PSI (reg:PSI 22)
+                   (reg:PSI 18)))
+    (clobber (reg:SI 18))
+    (clobber (scratch:QI))
+    (clobber (scratch:HI))
+    (clobber (reg:CC REG_CC))]
+   "reload_completed
+    && !AVR_HAVE_MUL && avropt_pr118012 && !AVR_TINY"
+   "%~call __mulpsi3"
+   [(set_attr "type" "xcall")])
+ 
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  ;; 24-bit signed/unsigned division and modulo.
diff -Nrcpad gcc-16-20251026/gcc/config/gcn/gcn-valu.md gcc-16-20251102/gcc/config/gcn/gcn-valu.md
*** gcc-16-20251026/gcc/config/gcn/gcn-valu.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/gcn/gcn-valu.md	Sun Nov  2 22:32:19 2025
***************
*** 3128,3133 ****
--- 3128,3147 ----
    }
    [(set_attr "type" "mult")])
  
+ (define_expand "abs<mode>2"
+   [(set (match_operand:V_INT 0 "register_operand")
+         (abs:V_INT (match_operand:V_INT 1 "register_operand")))]
+   ""
+   {
+     rtx vcc = gen_reg_rtx (DImode);
+     rtx zero = gcn_vec_constant (<MODE>mode, 0);
+     emit_insn (gen_vec_cmp<mode>di (vcc, gen_rtx_LT (VOIDmode, 0, 0),
+ 				    operands[1], zero));
+     emit_insn (gen_sub<mode>3_exec (operands[0], zero, operands[1],
+ 				    operands[1], vcc));
+     DONE;
+   })
+ 
  ;; }}}
  ;; {{{ FP binops - special cases
  
diff -Nrcpad gcc-16-20251026/gcc/config/i386/i386-options.cc gcc-16-20251102/gcc/config/i386/i386-options.cc
*** gcc-16-20251026/gcc/config/i386/i386-options.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/i386/i386-options.cc	Sun Nov  2 22:32:20 2025
*************** ix86_option_override_internal (bool main
*** 2917,2923 ****
        else
  	{
  	  opts->x_ix86_move_max = opts->x_prefer_vector_width_type;
! 	  if (opts_set->x_ix86_move_max == PVW_NONE)
  	    {
  	      if (TARGET_AVX512F_P (opts->x_ix86_isa_flags))
  		opts->x_ix86_move_max = PVW_AVX512;
--- 2917,2923 ----
        else
  	{
  	  opts->x_ix86_move_max = opts->x_prefer_vector_width_type;
! 	  if (opts->x_ix86_move_max == PVW_NONE)
  	    {
  	      if (TARGET_AVX512F_P (opts->x_ix86_isa_flags))
  		opts->x_ix86_move_max = PVW_AVX512;
diff -Nrcpad gcc-16-20251026/gcc/config/i386/i386.cc gcc-16-20251102/gcc/config/i386/i386.cc
*** gcc-16-20251026/gcc/config/i386/i386.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/i386/i386.cc	Sun Nov  2 22:32:20 2025
*************** ix86_canonicalize_comparison (int *code,
*** 598,603 ****
--- 598,617 ----
  	}
      }
  
+   /* SUB (a, b) underflows precisely when a < b.  Convert
+      (compare (minus (a b)) a) to (compare (a b))
+      to match *sub<mode>_3 pattern.  */
+   if (!op0_preserve_value
+       && (*code == GTU || *code == LEU)
+       && GET_CODE (*op0) == MINUS
+       && rtx_equal_p (XEXP (*op0, 0), *op1))
+     {
+       *op1 = XEXP (*op0, 1);
+       *op0 = XEXP (*op0, 0);
+       *code = (int) swap_condition ((enum rtx_code) *code);
+       return;
+     }
+ 
    /* Swap operands of GTU comparison to canonicalize
       addcarry/subborrow comparison.  */
    if (!op0_preserve_value
diff -Nrcpad gcc-16-20251026/gcc/config/i386/i386.md gcc-16-20251102/gcc/config/i386/i386.md
*** gcc-16-20251026/gcc/config/i386/i386.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/i386/i386.md	Sun Nov  2 22:32:20 2025
***************
*** 27353,27358 ****
--- 27353,27424 ----
  	(match_dup 0))]
    "peep2_reg_dead_p (2, operands[0])"
    [(set (match_dup 2) (match_dup 1))])
+ 
+ ;; umax (a, add (a, b)) => [sum, ovf] = add (a, b); ovf ? a : sum
+ ;; umin (a, add (a, b)) => [sum, ovf] = add (a, b); ovf ? sum : a
+ 
+ (define_code_attr ovf_add_cmp [(umax "geu") (umin "ltu")])
+ 
+ (define_int_iterator ovf_comm [1 2])
+ 
+ (define_insn_and_split "*plus_within_<code><mode>3_<ovf_comm>"
+   [(set (match_operand:SWI248 0 "register_operand")
+ 	(umaxmin:SWI248
+ 	  (plus:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
+ 		       (match_operand:SWI248 2 "<general_operand>"))
+ 	  (match_dup ovf_comm)))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_CMOVE
+    && ix86_pre_reload_split ()"
+   "#"
+   "&& 1"
+   [(parallel
+      [(set (reg:CCC FLAGS_REG)
+ 	   (compare:CCC
+ 	     (plus:SWI248 (match_dup 1) (match_dup 2))
+ 	     (match_dup ovf_comm)))
+       (set (match_dup 3)
+ 	   (plus:SWI248 (match_dup 1) (match_dup 2)))])
+    (set (match_dup 0)
+ 	(if_then_else:SWI248
+ 	  (<ovf_add_cmp> (reg:CCC FLAGS_REG) (const_int 0))
+ 	  (match_dup 3)
+ 	  (match_dup ovf_comm)))]
+ {
+   operands[<ovf_comm>] = force_reg (<MODE>mode, operands[<ovf_comm>]);
+   operands[3] = gen_reg_rtx (<MODE>mode);
+ })
+ 
+ ;; umax (a, sub (a, b)) => [diff, udf] = sub (a, b); udf ? diff : a
+ ;; umin (a, sub (a, b)) => [diff, udf] = sub (a, b); udf ? a : diff
+ 
+ (define_code_attr udf_sub_cmp [(umax "ltu") (umin "geu")])
+ 
+ (define_insn_and_split "*minus_within_<code><mode>3"
+   [(set (match_operand:SWI248 0 "register_operand")
+ 	(umaxmin:SWI248
+ 	  (minus:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
+ 			(match_operand:SWI248 2 "<general_operand>"))
+ 	  (match_dup 1)))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_CMOVE
+    && ix86_pre_reload_split ()"
+   "#"
+   "&& 1"
+   [(parallel
+      [(set (reg:CC FLAGS_REG)
+ 	   (compare:CC (match_dup 1) (match_dup 2)))
+       (set (match_dup 3)
+ 	   (minus:SWI248 (match_dup 1) (match_dup 2)))])
+    (set (match_dup 0)
+ 	(if_then_else:SWI248
+ 	  (<udf_sub_cmp> (reg:CC FLAGS_REG) (const_int 0))
+ 	  (match_dup 3)
+ 	  (match_dup 1)))]
+ {
+   operands[1] = force_reg (<MODE>mode, operands[1]);
+   operands[3] = gen_reg_rtx (<MODE>mode);
+ })
  
  ;; Misc patterns (?)
  
diff -Nrcpad gcc-16-20251026/gcc/config/i386/sse.md gcc-16-20251102/gcc/config/i386/sse.md
*** gcc-16-20251026/gcc/config/i386/sse.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/i386/sse.md	Sun Nov  2 22:32:20 2025
***************
*** 643,648 ****
--- 643,651 ----
  (define_mode_iterator VI2_AVX512F
    [(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI])
  
+ (define_mode_iterator VI2_AVX10_2
+   [(V32HI "TARGET_AVX10_2") (V16HI "TARGET_AVX2") V8HI])
+ 
  (define_mode_iterator VI2_AVX512VNNIBW
    [(V32HI "TARGET_AVX512BW || TARGET_AVX512VNNI")
     (V16HI "TARGET_AVX2") V8HI])
***************
*** 32334,32341 ****
  
  (define_expand "usdot_prod<sseunpackmodelower><mode>"
    [(match_operand:<sseunpackmode> 0 "register_operand")
!    (match_operand:VI2_AVX512F 1 "register_operand")
!    (match_operand:VI2_AVX512F 2 "register_operand")
     (match_operand:<sseunpackmode> 3 "register_operand")]
    "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
  {
--- 32337,32344 ----
  
  (define_expand "usdot_prod<sseunpackmodelower><mode>"
    [(match_operand:<sseunpackmode> 0 "register_operand")
!    (match_operand:VI2_AVX10_2 1 "register_operand")
!    (match_operand:VI2_AVX10_2 2 "register_operand")
     (match_operand:<sseunpackmode> 3 "register_operand")]
    "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
  {
***************
*** 32352,32359 ****
  
  (define_expand "udot_prod<sseunpackmodelower><mode>"
    [(match_operand:<sseunpackmode> 0 "register_operand")
!    (match_operand:VI2_AVX512F 1 "register_operand")
!    (match_operand:VI2_AVX512F 2 "register_operand")
     (match_operand:<sseunpackmode> 3 "register_operand")]
    "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
  {
--- 32355,32362 ----
  
  (define_expand "udot_prod<sseunpackmodelower><mode>"
    [(match_operand:<sseunpackmode> 0 "register_operand")
!    (match_operand:VI2_AVX10_2 1 "register_operand")
!    (match_operand:VI2_AVX10_2 2 "register_operand")
     (match_operand:<sseunpackmode> 3 "register_operand")]
    "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
  {
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/genopts/loongarch.opt.in gcc-16-20251102/gcc/config/loongarch/genopts/loongarch.opt.in
*** gcc-16-20251026/gcc/config/loongarch/genopts/loongarch.opt.in	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/genopts/loongarch.opt.in	Sun Nov  2 22:32:20 2025
*************** mmax-inline-memcpy-size=
*** 205,210 ****
--- 205,214 ----
  Target Joined RejectNegative UInteger Var(la_max_inline_memcpy_size) Init(1024) Save
  -mmax-inline-memcpy-size=SIZE	Set the max size of memcpy to inline, default is 1024.
  
+ mbreak-code=
+ Target Joined UInteger Var(la_break_code) Init(-1) Save
+ -mbreak-code=CODE	Use 'break CODE' for traps supposed to be unrecoverable, or an 'amswap.w' instruction leading to INE if CODE is out of range.
+ 
  Enum
  Name(explicit_relocs) Type(int)
  The code model option names for -mexplicit-relocs:
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/lasx.md gcc-16-20251102/gcc/config/loongarch/lasx.md
*** gcc-16-20251026/gcc/config/loongarch/lasx.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/lasx.md	Sun Nov  2 22:32:20 2025
***************
*** 146,154 ****
  ;; Only integer modes equal or larger than a word.
  (define_mode_iterator ILASX_DW  [V4DI V8SI])
  
- ;; Only integer modes smaller than a word.
- (define_mode_iterator ILASX_HB  [V16HI V32QI])
- 
  ;; Only used for immediate set shuffle elements instruction.
  (define_mode_iterator LASX_WHB_W [V8SI V16HI V32QI V8SF])
  
--- 146,151 ----
***************
*** 834,892 ****
    [(set_attr "type" "simd_div")
     (set_attr "mode" "<MODE>")])
  
- (define_insn "xor<mode>3"
-   [(set (match_operand:LASX 0 "register_operand" "=f,f,f")
- 	(xor:LASX
- 	  (match_operand:LASX 1 "register_operand" "f,f,f")
- 	  (match_operand:LASX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
-   "ISA_HAS_LASX"
-   "@
-    xvxor.v\t%u0,%u1,%u2
-    xvbitrevi.%v0\t%u0,%u1,%V2
-    xvxori.b\t%u0,%u1,%B2"
-   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
-    (set_attr "mode" "<MODE>")])
- 
- (define_insn "ior<mode>3"
-   [(set (match_operand:LASX 0 "register_operand" "=f,f,f")
- 	(ior:LASX
- 	  (match_operand:LASX 1 "register_operand" "f,f,f")
- 	  (match_operand:LASX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
-   "ISA_HAS_LASX"
-   "@
-    xvor.v\t%u0,%u1,%u2
-    xvbitseti.%v0\t%u0,%u1,%V2
-    xvori.b\t%u0,%u1,%B2"
-   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
-    (set_attr "mode" "<MODE>")])
- 
- (define_insn "and<mode>3"
-   [(set (match_operand:LASX 0 "register_operand" "=f,f,f")
- 	(and:LASX
- 	  (match_operand:LASX 1 "register_operand" "f,f,f")
- 	  (match_operand:LASX 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
-   "ISA_HAS_LASX"
- {
-   switch (which_alternative)
-     {
-     case 0:
-       return "xvand.v\t%u0,%u1,%u2";
-     case 1:
-       {
- 	rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
- 	unsigned HOST_WIDE_INT val = ~UINTVAL (elt0);
- 	operands[2] = loongarch_gen_const_int_vector (<MODE>mode, val & (-val));
- 	return "xvbitclri.%v0\t%u0,%u1,%V2";
-       }
-     case 2:
-       return "xvandi.b\t%u0,%u1,%B2";
-     default:
-       gcc_unreachable ();
-     }
- }
-   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
-    (set_attr "mode" "<MODE>")])
- 
  (define_insn "one_cmpl<mode>2"
    [(set (match_operand:ILASX 0 "register_operand" "=f")
  	(not:ILASX (match_operand:ILASX 1 "register_operand" "f")))]
--- 831,836 ----
***************
*** 1035,1050 ****
    [(set_attr "type" "simd_fmadd")
     (set_attr "mode" "<MODE>")])
  
- (define_insn "fnma<mode>4"
-   [(set (match_operand:FLASX 0 "register_operand" "=f")
- 	(fma:FLASX (neg:FLASX (match_operand:FLASX 1 "register_operand" "f"))
- 		   (match_operand:FLASX 2 "register_operand" "f")
- 		   (match_operand:FLASX 3 "register_operand" "0")))]
-   "ISA_HAS_LASX"
-   "xvfnmsub.<flasxfmt>\t%u0,%u1,%u2,%u0"
-   [(set_attr "type" "simd_fmadd")
-    (set_attr "mode" "<MODE>")])
- 
  (define_expand "sqrt<mode>2"
    [(set (match_operand:FLASX 0 "register_operand")
      (sqrt:FLASX (match_operand:FLASX 1 "register_operand")))]
--- 979,984 ----
***************
*** 3633,3701 ****
    [(set_attr "type" "simd_store")
     (set_attr "mode" "DI")])
  
! (define_expand "vec_widen_<su>add_hi_<mode>"
!   [(match_operand:<VDMODE256> 0 "register_operand")
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 1 "register_operand"))
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 2 "register_operand"))]
!   "ISA_HAS_LASX"
! {
!   loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <u_bool>, true, "add");
!   DONE;
! })
! 
! (define_expand "vec_widen_<su>add_lo_<mode>"
!   [(match_operand:<VDMODE256> 0 "register_operand")
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 1 "register_operand"))
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 2 "register_operand"))]
!   "ISA_HAS_LASX"
! {
!   loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <u_bool>, false, "add");
!   DONE;
! })
! 
! (define_expand "vec_widen_<su>sub_hi_<mode>"
!   [(match_operand:<VDMODE256> 0 "register_operand")
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 1 "register_operand"))
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 2 "register_operand"))]
!   "ISA_HAS_LASX"
! {
!   loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <u_bool>, true, "sub");
!   DONE;
! })
! 
! (define_expand "vec_widen_<su>sub_lo_<mode>"
!   [(match_operand:<VDMODE256> 0 "register_operand")
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 1 "register_operand"))
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 2 "register_operand"))]
!   "ISA_HAS_LASX"
! {
!   loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <u_bool>, false, "sub");
!   DONE;
! })
! 
! (define_expand "vec_widen_<su>mult_hi_<mode>"
    [(match_operand:<VDMODE256> 0 "register_operand")
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 1 "register_operand"))
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 2 "register_operand"))]
    "ISA_HAS_LASX"
  {
    loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <u_bool>, true, "mult");
    DONE;
  })
  
! (define_expand "vec_widen_<su>mult_lo_<mode>"
    [(match_operand:<VDMODE256> 0 "register_operand")
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 1 "register_operand"))
!    (any_extend:<VDMODE256> (match_operand:ILASX_HB 2 "register_operand"))]
    "ISA_HAS_LASX"
  {
    loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <u_bool>, false, "mult");
    DONE;
  })
  
--- 3567,3604 ----
    [(set_attr "type" "simd_store")
     (set_attr "mode" "DI")])
  
! (define_expand "vec_widen_<su><optab>_<hi_lo>_<mode>"
    [(match_operand:<VDMODE256> 0 "register_operand")
!    (match_operand:ILASX_WHB 1 "register_operand")
!    (match_operand:ILASX_WHB 2 "register_operand")
!    (any_extend (const_int 0))
!    (addsub (const_int 0) (const_int 0))
!    (const_int zero_one)]
    "ISA_HAS_LASX"
  {
+   rtx (*fn_even) (rtx, rtx, rtx) =
+ gen_lasx_xv<optab>wev_<dlasxfmt>_<lasxfmt><u>;
+   rtx (*fn_odd) (rtx, rtx, rtx) =
+ gen_lasx_xv<optab>wod_<dlasxfmt>_<lasxfmt><u>;
    loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <zero_one>, fn_even, fn_odd);
    DONE;
  })
  
! (define_expand "vec_widen_<su>mult_<hi_lo>_<mode>"
    [(match_operand:<VDMODE256> 0 "register_operand")
!    (match_operand:ILASX_WHB 1 "register_operand")
!    (match_operand:ILASX_WHB 2 "register_operand")
!    (any_extend (const_int 0))
!    (const_int zero_one)]
    "ISA_HAS_LASX"
  {
+   rtx (*fn_even) (rtx, rtx, rtx) =
+ gen_lasx_xvmulwev_<dlasxfmt>_<lasxfmt><u>;
+   rtx (*fn_odd) (rtx, rtx, rtx) =
+ gen_lasx_xvmulwod_<dlasxfmt>_<lasxfmt><u>;
    loongarch_expand_vec_widen_hilo (operands[0], operands[1], operands[2],
!                         <zero_one>, fn_even, fn_odd);
    DONE;
  })
  
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/loongarch-protos.h gcc-16-20251102/gcc/config/loongarch/loongarch-protos.h
*** gcc-16-20251026/gcc/config/loongarch/loongarch-protos.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/loongarch-protos.h	Sun Nov  2 22:32:20 2025
*************** extern void loongarch_register_frame_hea
*** 198,204 ****
  extern void loongarch_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
  extern void loongarch_expand_vec_cond_mask_expr (machine_mode, machine_mode,
  						 rtx *);
! extern void loongarch_expand_vec_widen_hilo (rtx, rtx, rtx, bool, bool, const char *);
  
  /* Routines implemented in loongarch-c.c.  */
  void loongarch_cpu_cpp_builtins (cpp_reader *);
--- 198,205 ----
  extern void loongarch_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
  extern void loongarch_expand_vec_cond_mask_expr (machine_mode, machine_mode,
  						 rtx *);
! extern void loongarch_expand_vec_widen_hilo (rtx, rtx, rtx, bool,
! 	rtx (*)(rtx, rtx, rtx), rtx (*)(rtx, rtx, rtx));
  
  /* Routines implemented in loongarch-c.c.  */
  void loongarch_cpu_cpp_builtins (cpp_reader *);
*************** extern void loongarch_emit_swdivsf (rtx,
*** 217,223 ****
  extern bool loongarch_explicit_relocs_p (enum loongarch_symbol_type);
  extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type);
  extern bool loongarch_option_valid_attribute_p (tree, tree, tree, int);
! extern void loongarch_option_override_internal (struct loongarch_target *, struct gcc_options *, struct gcc_options *);
  extern void loongarch_reset_previous_fndecl (void);
  extern void loongarch_save_restore_target_globals (tree new_tree);
  extern void loongarch_register_pragmas (void);
--- 218,225 ----
  extern bool loongarch_explicit_relocs_p (enum loongarch_symbol_type);
  extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type);
  extern bool loongarch_option_valid_attribute_p (tree, tree, tree, int);
! extern void loongarch_option_override_internal (struct loongarch_target *,
! 	struct gcc_options *, struct gcc_options *);
  extern void loongarch_reset_previous_fndecl (void);
  extern void loongarch_save_restore_target_globals (tree new_tree);
  extern void loongarch_register_pragmas (void);
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/loongarch.cc gcc-16-20251102/gcc/config/loongarch/loongarch.cc
*** gcc-16-20251026/gcc/config/loongarch/loongarch.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/loongarch.cc	Sun Nov  2 22:32:20 2025
*************** loongarch_symbol_binds_local_p (const_rt
*** 1718,1731 ****
  bool
  loongarch_const_vector_bitimm_set_p (rtx op, machine_mode mode)
  {
!   if (GET_CODE (op) == CONST_VECTOR && op != CONST0_RTX (mode))
      {
!       unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
        int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
  
        if (vlog2 != -1)
  	{
- 	  gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
  	  gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1);
  	  return loongarch_const_vector_same_val_p (op, mode);
  	}
--- 1718,1753 ----
  bool
  loongarch_const_vector_bitimm_set_p (rtx op, machine_mode mode)
  {
!   if (GET_CODE (op) == CONST_VECTOR
!       && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
! 	  || GET_MODE_CLASS (mode) == MODE_VECTOR_INT))
      {
!       unsigned HOST_WIDE_INT val;
! 
!       if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
! 	{
! 	  rtx val_s = CONST_VECTOR_ELT (op, 0);
! 	  const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s);
! 	  if (GET_MODE (val_s) == DFmode)
! 	    {
! 	      long tmp[2];
! 	      REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 	      val = (unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0];
! 	    }
! 	  else
! 	    {
! 	      long tmp;
! 	      REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 	      val = (unsigned HOST_WIDE_INT) tmp;
! 	    }
! 	}
!       else
! 	val = UINTVAL (CONST_VECTOR_ELT (op, 0));
! 
        int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
  
        if (vlog2 != -1)
  	{
  	  gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1);
  	  return loongarch_const_vector_same_val_p (op, mode);
  	}
*************** loongarch_const_vector_bitimm_set_p (rtx
*** 1740,1753 ****
  bool
  loongarch_const_vector_bitimm_clr_p (rtx op, machine_mode mode)
  {
!   if (GET_CODE (op) == CONST_VECTOR && op != CONSTM1_RTX (mode))
      {
!       unsigned HOST_WIDE_INT val = ~UINTVAL (CONST_VECTOR_ELT (op, 0));
        int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
  
        if (vlog2 != -1)
  	{
- 	  gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
  	  gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1);
  	  return loongarch_const_vector_same_val_p (op, mode);
  	}
--- 1762,1796 ----
  bool
  loongarch_const_vector_bitimm_clr_p (rtx op, machine_mode mode)
  {
!   if (GET_CODE (op) == CONST_VECTOR
!       && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
! 	  || GET_MODE_CLASS (mode) == MODE_VECTOR_INT))
      {
!       unsigned HOST_WIDE_INT val;
!       if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
! 	{
! 	  rtx val_s = CONST_VECTOR_ELT (op, 0);
! 	  const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s);
! 	  if (GET_MODE (val_s) == DFmode)
! 	    {
! 	      long tmp[2];
! 	      REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 	      val = ~((unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0]);
! 	    }
! 	  else
! 	    {
! 	      long tmp;
! 	      REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 	      val = ~((unsigned HOST_WIDE_INT) tmp);
! 	    }
! 	}
!       else
! 	val = ~UINTVAL (CONST_VECTOR_ELT (op, 0));
! 
        int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
  
        if (vlog2 != -1)
  	{
  	  gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1);
  	  return loongarch_const_vector_same_val_p (op, mode);
  	}
*************** loongarch_rtx_costs (rtx x, machine_mode
*** 4056,4061 ****
--- 4099,4115 ----
  	*total = loongarch_cost->int_mult_di;
        else
  	*total = loongarch_cost->int_mult_si;
+ 
+       /* Check for mul_widen.  */
+       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
+ 	   && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
+ 	  || (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+ 	      && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND))
+ 	{
+ 	  *total += (set_src_cost (XEXP (XEXP (x, 0), 0), mode, speed)
+ 		     + set_src_cost (XEXP (XEXP (x, 1), 0), mode, speed));
+ 	  return true;
+ 	}
        return false;
  
      case DIV:
*************** loongarch_expand_conditional_move (rtx *
*** 5479,5490 ****
  	    }
  	}
  
        /* Check if the optimization conditions are met.  */
        if (value_if_true_insn
  	  && value_if_false_insn
! 	  /* Make sure that value_if_false and var are the same.  */
! 	  && BINARY_P (value_if_true_insn_src
! 		       = SET_SRC (single_set (value_if_true_insn)))
  	  /* Make sure that both value_if_true and value_if_false
  	     has the same var.  */
  	  && rtx_equal_p (XEXP (value_if_true_insn_src, 0),
--- 5533,5564 ----
  	    }
  	}
  
+       auto is_binary_op_0_keep_orig = [](enum rtx_code code)
+ 	{
+ 	  switch (code)
+ 	    {
+ 	    case PLUS:
+ 	    case MINUS:
+ 	    case IOR:
+ 	    case XOR:
+ 	    case ROTATE:
+ 	    case ROTATERT:
+ 	    case ASHIFT:
+ 	    case ASHIFTRT:
+ 	    case LSHIFTRT:
+ 	      return true;
+ 	    default:
+ 	      return false;
+ 	    }
+ 	};
+ 
        /* Check if the optimization conditions are met.  */
        if (value_if_true_insn
  	  && value_if_false_insn
! 	  /* Make sure that the orig value OP 0 keep orig.  */
! 	  && (value_if_true_insn_src
! 	      = SET_SRC (single_set (value_if_true_insn)))
! 	  && is_binary_op_0_keep_orig ( GET_CODE (value_if_true_insn_src))
  	  /* Make sure that both value_if_true and value_if_false
  	     has the same var.  */
  	  && rtx_equal_p (XEXP (value_if_true_insn_src, 0),
*************** loongarch_print_operand (FILE *file, rtx
*** 6439,6445 ****
        if (CONST_VECTOR_P (op))
  	{
  	  machine_mode mode = GET_MODE_INNER (GET_MODE (op));
! 	  unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
  	  int vlog2 = exact_log2 (val & GET_MODE_MASK (mode));
  	  if (vlog2 != -1)
  	    fprintf (file, "%d", vlog2);
--- 6513,6540 ----
        if (CONST_VECTOR_P (op))
  	{
  	  machine_mode mode = GET_MODE_INNER (GET_MODE (op));
! 	  rtx val_s = CONST_VECTOR_ELT (op, 0);
! 	  unsigned HOST_WIDE_INT val;
! 
! 	  if (GET_MODE_CLASS (mode) == MODE_FLOAT)
! 	    {
! 	      const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s);
! 	      if (GET_MODE (val_s) == DFmode)
! 		{
! 		  long tmp[2];
! 		  REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 		  val = (unsigned HOST_WIDE_INT) (tmp[1] << 32 | tmp[0]);
! 		}
! 	      else
! 		{
! 		  long tmp;
! 		  REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 		  val = (unsigned HOST_WIDE_INT) tmp;
! 		}
! 	    }
! 	  else
! 	    val = UINTVAL (val_s);
! 
  	  int vlog2 = exact_log2 (val & GET_MODE_MASK (mode));
  	  if (vlog2 != -1)
  	    fprintf (file, "%d", vlog2);
*************** loongarch_expand_vec_interleave (rtx tar
*** 8808,8912 ****
  
  void
  loongarch_expand_vec_widen_hilo (rtx dest, rtx op1, rtx op2,
! 				 bool uns_p, bool high_p, const char *optab)
  {
    machine_mode wmode = GET_MODE (dest);
    machine_mode mode = GET_MODE (op1);
-   rtx t1, t2, t3;
  
!   t1 = gen_reg_rtx (wmode);
!   t2 = gen_reg_rtx (wmode);
!   t3 = gen_reg_rtx (wmode);
!   switch (mode)
!     {
!     case V16HImode:
!       if (!strcmp (optab, "add"))
! 	{
! 	  if (!uns_p)
! 	    {
! 	      emit_insn (gen_lasx_xvaddwev_w_h (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvaddwod_w_h (t2, op1, op2));
! 	    }
! 	  else
! 	    {
! 	      emit_insn (gen_lasx_xvaddwev_w_hu (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvaddwod_w_hu (t2, op1, op2));
! 	    }
! 	}
!       else if (!strcmp (optab, "mult"))
! 	{
! 	  if (!uns_p)
! 	    {
! 	      emit_insn (gen_lasx_xvmulwev_w_h (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvmulwod_w_h (t2, op1, op2));
! 	    }
! 	  else
! 	    {
! 	      emit_insn (gen_lasx_xvmulwev_w_hu (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvmulwod_w_hu (t2, op1, op2));
! 	    }
! 	}
!       else if (!strcmp (optab, "sub"))
! 	{
! 	  if (!uns_p)
! 	    {
! 	      emit_insn (gen_lasx_xvsubwev_w_h (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvsubwod_w_h (t2, op1, op2));
! 	    }
! 	  else
! 	    {
! 	      emit_insn (gen_lasx_xvsubwev_w_hu (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvsubwod_w_hu (t2, op1, op2));
! 	    }
! 	}
!       break;
! 
!     case V32QImode:
!       if (!strcmp (optab, "add"))
! 	{
! 	  if (!uns_p)
! 	    {
! 	      emit_insn (gen_lasx_xvaddwev_h_b (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvaddwod_h_b (t2, op1, op2));
! 	    }
! 	  else
! 	    {
! 	      emit_insn (gen_lasx_xvaddwev_h_bu (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvaddwod_h_bu (t2, op1, op2));
! 	    }
! 	}
!       else if (!strcmp (optab, "mult"))
! 	{
! 	  if (!uns_p)
! 	    {
! 	      emit_insn (gen_lasx_xvmulwev_h_b (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvmulwod_h_b (t2, op1, op2));
! 	    }
! 	  else
! 	    {
! 	      emit_insn (gen_lasx_xvmulwev_h_bu (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvmulwod_h_bu (t2, op1, op2));
! 	    }
! 	}
!       else if (!strcmp (optab, "sub"))
! 	{
! 	  if (!uns_p)
! 	    {
! 	      emit_insn (gen_lasx_xvsubwev_h_b (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvsubwod_h_b (t2, op1, op2));
! 	    }
! 	  else
! 	    {
! 	      emit_insn (gen_lasx_xvsubwev_h_bu (t1, op1, op2));
! 	      emit_insn (gen_lasx_xvsubwod_h_bu (t2, op1, op2));
! 	    }
! 	}
!       break;
  
!     default:
!       gcc_unreachable ();
!     }
  
    loongarch_expand_vec_interleave (t3, t1, t2, high_p);
    emit_move_insn (dest, gen_lowpart (wmode, t3));
  }
--- 8903,8924 ----
  
  void
  loongarch_expand_vec_widen_hilo (rtx dest, rtx op1, rtx op2,
! 				 bool high_p, rtx (*fn_even) (rtx, rtx, rtx),
! 				 rtx (*fn_odd) (rtx, rtx, rtx))
  {
    machine_mode wmode = GET_MODE (dest);
    machine_mode mode = GET_MODE (op1);
  
!   gcc_assert (ISA_HAS_LASX
! 	      && GET_MODE_SIZE (mode) == 32
! 	      && mode != V4DImode);
  
!   rtx t1 = gen_reg_rtx (wmode);
!   rtx t2 = gen_reg_rtx (wmode);
!   rtx t3 = gen_reg_rtx (wmode);
  
+   emit_insn (fn_even (t1, op1, op2));
+   emit_insn (fn_odd (t2, op1, op2));
    loongarch_expand_vec_interleave (t3, t1, t2, high_p);
    emit_move_insn (dest, gen_lowpart (wmode, t3));
  }
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/loongarch.md gcc-16-20251102/gcc/config/loongarch/loongarch.md
*** gcc-16-20251026/gcc/config/loongarch/loongarch.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/loongarch.md	Sun Nov  2 22:32:20 2025
***************
*** 679,692 ****
  ;;  ....................
  ;;
  
! (define_insn "trap"
!   [(trap_if (const_int 1) (const_int 0))]
    ""
  {
!   return "break\t0";
  }
    [(set_attr "type" "trap")])
  
  
  
  ;;
--- 679,700 ----
  ;;  ....................
  ;;
  
! (define_insn "*trap"
!   [(trap_if (const_int 1) (match_operand 0 "const_int_operand"))]
    ""
  {
!   return (const_uimm15_operand (operands[0], VOIDmode)
! 	  ? "break\t%0"
! 	  : "amswap.w\t$r0,$r1,$r0");
  }
    [(set_attr "type" "trap")])
  
+ (define_expand "trap"
+   [(trap_if (const_int 1) (match_dup 0))]
+   ""
+ {
+   operands[0] = GEN_INT (la_break_code);
+ })
  
  
  ;;
***************
*** 2523,2528 ****
--- 2531,2568 ----
    [(set_attr "type" "condmove")
     (set_attr "mode" "<GPR:MODE>")])
  
+ (define_insn_and_split "both_non_zero"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(and:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
+ 		       (const_int 0))
+ 		(ne:DI (match_operand:DI 2 "register_operand" "r")
+ 		       (const_int 0))))]
+   "TARGET_64BIT"
+   "#"
+   "&& true"
+   [(set (match_dup 0)
+ 	(ne:DI (match_dup 1) (const_int 0)))
+    (set (match_dup 0)
+ 	(if_then_else:DI (ne:DI (match_dup 2) (const_int 0))
+ 			 (match_dup 0)
+ 			 (const_int 0)))])
+ 
+ (define_insn_and_split "both_non_zero_subreg"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(and:DI (subreg:DI (ne:SI (match_operand:DI 1 "register_operand" "r")
+ 				  (const_int 0)) 0)
+ 		(subreg:DI (ne:SI (match_operand:DI 2 "register_operand" "r")
+ 				  (const_int 0)) 0)))]
+   "TARGET_64BIT"
+   "#"
+   "&& true"
+   [(set (match_dup 0)
+ 	(ne:DI (match_dup 1) (const_int 0)))
+    (set (match_dup 0)
+ 	(if_then_else:DI (ne:DI (match_dup 2) (const_int 0))
+ 			 (match_dup 0)
+ 			 (const_int 0)))])
+ 
  ;; fsel copies the 3rd argument when the 1st is non-zero and the 2nd
  ;; argument if the 1st is zero.  This means operand 2 and 3 are
  ;; inverted in the instruction.
***************
*** 3041,3046 ****
--- 3081,3096 ----
    [(set_attr "type" "shift")
     (set_attr "mode" "SI")])
  
+ (define_insn "sign_extend_ashift<GPR:mode><SHORT:mode>"
+   [(set (match_operand:GPR 0 "register_operand" "=r")
+ 	(ashift:GPR
+ 	   (sign_extend:GPR (match_operand:SHORT 1 "register_operand" "r"))
+ 	   (match_operand:SI 2 "const_uimm5_operand")))]
+   "(GET_MODE_BITSIZE (<SHORT:MODE>mode) + INTVAL (operands[2])) == 32"
+   "slli.w\t%0,%1,%2"
+   [(set_attr "type" "shift")
+    (set_attr "mode" "<GPR:MODE>")])
+ 
  (define_insn "*rotr<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=r,r")
  	(rotatert:GPR (match_operand:GPR 1 "register_operand" "r,r")
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/loongarch.opt gcc-16-20251102/gcc/config/loongarch/loongarch.opt
*** gcc-16-20251026/gcc/config/loongarch/loongarch.opt	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/loongarch.opt	Sun Nov  2 22:32:20 2025
*************** mmax-inline-memcpy-size=
*** 213,218 ****
--- 213,222 ----
  Target Joined RejectNegative UInteger Var(la_max_inline_memcpy_size) Init(1024) Save
  -mmax-inline-memcpy-size=SIZE	Set the max size of memcpy to inline, default is 1024.
  
+ mbreak-code=
+ Target Joined UInteger Var(la_break_code) Init(-1) Save
+ -mbreak-code=CODE	Use 'break CODE' for traps supposed to be unrecoverable, or an 'amswap.w' instruction leading to INE if CODE is out of range.
+ 
  Enum
  Name(explicit_relocs) Type(int)
  The code model option names for -mexplicit-relocs:
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/loongarch.opt.urls gcc-16-20251102/gcc/config/loongarch/loongarch.opt.urls
*** gcc-16-20251026/gcc/config/loongarch/loongarch.opt.urls	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/loongarch.opt.urls	Sun Nov  2 22:32:20 2025
*************** UrlSuffix(gcc/LoongArch-Options.html#ind
*** 48,53 ****
--- 48,56 ----
  mmax-inline-memcpy-size=
  UrlSuffix(gcc/LoongArch-Options.html#index-mmax-inline-memcpy-size)
  
+ mbreak-code=
+ UrlSuffix(gcc/LoongArch-Options.html#index-mbreak-code)
+ 
  mexplicit-relocs=
  UrlSuffix(gcc/LoongArch-Options.html#index-mexplicit-relocs-1)
  
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/lsx.md gcc-16-20251102/gcc/config/loongarch/lsx.md
*** gcc-16-20251026/gcc/config/loongarch/lsx.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/lsx.md	Sun Nov  2 22:32:20 2025
***************
*** 145,153 ****
  ;; Only integer modes equal or larger than a word.
  (define_mode_iterator ILSX_DW  [V2DI V4SI])
  
- ;; Only integer modes smaller than a word.
- (define_mode_iterator ILSX_HB  [V8HI V16QI])
- 
  ;;;; Only integer modes for fixed-point madd_q/maddr_q.
  ;;(define_mode_iterator ILSX_WH  [V4SI V8HI])
  
--- 145,150 ----
***************
*** 654,712 ****
    [(set_attr "type" "simd_div")
     (set_attr "mode" "<MODE>")])
  
- (define_insn "xor<mode>3"
-   [(set (match_operand:LSX 0 "register_operand" "=f,f,f")
- 	(xor:LSX
- 	  (match_operand:LSX 1 "register_operand" "f,f,f")
- 	  (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
-   "ISA_HAS_LSX"
-   "@
-    vxor.v\t%w0,%w1,%w2
-    vbitrevi.%v0\t%w0,%w1,%V2
-    vxori.b\t%w0,%w1,%B2"
-   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
-    (set_attr "mode" "<MODE>")])
- 
- (define_insn "ior<mode>3"
-   [(set (match_operand:LSX 0 "register_operand" "=f,f,f")
- 	(ior:LSX
- 	  (match_operand:LSX 1 "register_operand" "f,f,f")
- 	  (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
-   "ISA_HAS_LSX"
-   "@
-    vor.v\t%w0,%w1,%w2
-    vbitseti.%v0\t%w0,%w1,%V2
-    vori.b\t%w0,%w1,%B2"
-   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
-    (set_attr "mode" "<MODE>")])
- 
- (define_insn "and<mode>3"
-   [(set (match_operand:LSX 0 "register_operand" "=f,f,f")
- 	(and:LSX
- 	  (match_operand:LSX 1 "register_operand" "f,f,f")
- 	  (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
-   "ISA_HAS_LSX"
- {
-   switch (which_alternative)
-     {
-     case 0:
-       return "vand.v\t%w0,%w1,%w2";
-     case 1:
-       {
- 	rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
- 	unsigned HOST_WIDE_INT val = ~UINTVAL (elt0);
- 	operands[2] = loongarch_gen_const_int_vector (<MODE>mode, val & (-val));
- 	return "vbitclri.%v0\t%w0,%w1,%V2";
-       }
-     case 2:
-       return "vandi.b\t%w0,%w1,%B2";
-     default:
-       gcc_unreachable ();
-     }
- }
-   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
-    (set_attr "mode" "<MODE>")])
- 
  (define_insn "one_cmpl<mode>2"
    [(set (match_operand:ILSX 0 "register_operand" "=f")
  	(not:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
--- 651,656 ----
***************
*** 852,867 ****
    [(set_attr "type" "simd_fmadd")
     (set_attr "mode" "<MODE>")])
  
- (define_insn "fnma<mode>4"
-   [(set (match_operand:FLSX 0 "register_operand" "=f")
- 	(fma:FLSX (neg:FLSX (match_operand:FLSX 1 "register_operand" "f"))
- 		  (match_operand:FLSX 2 "register_operand" "f")
- 		  (match_operand:FLSX 3 "register_operand" "0")))]
-   "ISA_HAS_LSX"
-   "vfnmsub.<flsxfmt>\t%w0,%w1,%w2,%w0"
-   [(set_attr "type" "simd_fmadd")
-    (set_attr "mode" "<MODE>")])
- 
  (define_expand "sqrt<mode>2"
    [(set (match_operand:FLSX 0 "register_operand")
      (sqrt:FLSX (match_operand:FLSX 1 "register_operand")))]
--- 796,801 ----
***************
*** 3220,3222 ****
--- 3154,3201 ----
    [(set (match_dup 0)
  	(vec_duplicate:V2DI (match_dup 1)))]
    "")
+ 
+ (define_expand "vec_widen_<su><optab>_<hi_lo>_<mode>"
+   [(match_operand:<VDMODE> 0 "register_operand")
+    (match_operand:ILSX_WHB 1 "register_operand")
+    (match_operand:ILSX_WHB 2 "register_operand")
+    (any_extend (const_int 0))
+    (addsub (const_int 0) (const_int 0))
+    (const_int zero_one)]
+   "ISA_HAS_LSX"
+ {
+   rtx t_even = gen_reg_rtx (<VDMODE>mode);
+   rtx t_odd = gen_reg_rtx (<VDMODE>mode);
+   emit_insn (gen_lsx_v<optab>wev_<dlsxfmt>_<lsxfmt><u> (t_even, operands[1],
+ 	operands[2]));
+   emit_insn (gen_lsx_v<optab>wod_<dlsxfmt>_<lsxfmt><u> (t_odd, operands[1],
+ 	operands[2]));
+   if (<zero_one>)
+     emit_insn (gen_lsx_vilvh_<dlsxfmt> (operands[0], t_even, t_odd));
+   else
+     emit_insn (gen_lsx_vilvl_<dlsxfmt> (operands[0], t_even, t_odd));
+ 
+   DONE;
+ })
+ 
+ (define_expand "vec_widen_<su>mult_<hi_lo>_<mode>"
+   [(match_operand:<VDMODE> 0 "register_operand")
+    (match_operand:ILSX_WHB 1 "register_operand")
+    (match_operand:ILSX_WHB 2 "register_operand")
+    (any_extend (const_int 0))
+    (const_int zero_one)]
+   "ISA_HAS_LSX"
+ {
+   rtx t_even = gen_reg_rtx (<VDMODE>mode);
+   rtx t_odd = gen_reg_rtx (<VDMODE>mode);
+   emit_insn (gen_lsx_vmulwev_<dlsxfmt>_<lsxfmt><u> (t_even, operands[1],
+ 	operands[2]));
+   emit_insn (gen_lsx_vmulwod_<dlsxfmt>_<lsxfmt><u> (t_odd, operands[1],
+ 	operands[2]));
+   if (<zero_one>)
+     emit_insn (gen_lsx_vilvh_<dlsxfmt> (operands[0], t_even, t_odd));
+   else
+     emit_insn (gen_lsx_vilvl_<dlsxfmt> (operands[0], t_even, t_odd));
+ 
+   DONE;
+ })
diff -Nrcpad gcc-16-20251026/gcc/config/loongarch/simd.md gcc-16-20251102/gcc/config/loongarch/simd.md
*** gcc-16-20251026/gcc/config/loongarch/simd.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/loongarch/simd.md	Sun Nov  2 22:32:20 2025
***************
*** 23,28 ****
--- 23,32 ----
  ;; Integer modes supported by LASX.
  (define_mode_iterator ILASX   [V4DI V8SI V16HI V32QI])
  
+ ;; Only integer modes smaller than a word.
+ (define_mode_iterator ILSX_HB  [V8HI V16QI])
+ (define_mode_iterator ILASX_HB  [V16HI V32QI])
+ 
  ;; FP modes supported by LSX
  (define_mode_iterator FLSX    [V2DF V4SF])
  
***************
*** 38,43 ****
--- 42,51 ----
  ;; All integer modes available
  (define_mode_iterator IVEC    [(ILSX "ISA_HAS_LSX") (ILASX "ISA_HAS_LASX")])
  
+ ;; All integer modes smaller than a word.
+ (define_mode_iterator IVEC_HB [(ILSX_HB "ISA_HAS_LSX")
+ 			       (ILASX_HB "ISA_HAS_LASX")])
+ 
  ;; All FP modes available
  (define_mode_iterator FVEC    [(FLSX "ISA_HAS_LSX") (FLASX "ISA_HAS_LASX")])
  
***************
*** 90,101 ****
--- 98,115 ----
  			     (V8HI "V4SI") (V16HI "V8SI")
  			     (V16QI "V8HI") (V32QI "V16HI")])
  
+ (define_mode_attr WVEC_QUARTER [(V8HI "V2DI") (V16HI "V4DI")
+ 				(V16QI "V4SI") (V32QI "V8SI")])
+ 
  ;; Lower-case version.
  (define_mode_attr wvec_half [(V2DI "v1ti") (V4DI "v2ti")
  			     (V4SI "v2di") (V8SI "v4di")
  			     (V8HI "v4si") (V16HI "v8si")
  			     (V16QI "v8hi") (V32QI "v16hi")])
  
+ (define_mode_attr wvec_quarter [(V8HI "v2di") (V16HI "v4di")
+ 				(V16QI "v4si") (V32QI "v8si")])
+ 
  ;; Integer vector modes with the same length and unit size as a mode.
  (define_mode_attr VIMODE [(V2DI "V2DI") (V4SI "V4SI")
  			  (V8HI "V8HI") (V16QI "V16QI")
***************
*** 124,135 ****
  			   (V8HI "h") (V16HI "h")
  			   (V16QI "b") (V32QI "b")])
  
! ;; Suffix for widening LSX or LASX instructions.
  (define_mode_attr simdfmt_w [(V2DI "q") (V4DI "q")
  			     (V4SI "d") (V8SI "d")
  			     (V8HI "w") (V16HI "w")
  			     (V16QI "h") (V32QI "h")])
  
  ;; Suffix for integer mode in LSX or LASX instructions with FP input but
  ;; integer output.
  (define_mode_attr simdifmt_for_f [(V2DF "l") (V4DF "l")
--- 138,153 ----
  			   (V8HI "h") (V16HI "h")
  			   (V16QI "b") (V32QI "b")])
  
! ;; Suffix for double widening LSX or LASX instructions.
  (define_mode_attr simdfmt_w [(V2DI "q") (V4DI "q")
  			     (V4SI "d") (V8SI "d")
  			     (V8HI "w") (V16HI "w")
  			     (V16QI "h") (V32QI "h")])
  
+ ;; Suffix for quadruple widening LSX or LASX instructions.
+ (define_mode_attr simdfmt_qw [(V8HI "d") (V16HI "d")
+ 			     (V16QI "w") (V32QI "w")])
+ 
  ;; Suffix for integer mode in LSX or LASX instructions with FP input but
  ;; integer output.
  (define_mode_attr simdifmt_for_f [(V2DF "l") (V4DF "l")
***************
*** 169,174 ****
--- 187,194 ----
  			  (V4SI  "uimm5") (V8SI "uimm5")
  			  (V2DI  "uimm6") (V4DI "uimm6")])
  
+ (define_int_attr hi_lo [(0 "lo") (1 "hi")])
+ 
  ;; =======================================================================
  ;; For many LASX instructions, the only difference of it from the LSX
  ;; counterpart is the length of vector operands.  Describe these LSX/LASX
***************
*** 431,436 ****
--- 451,467 ----
    [(set_attr "type" "simd_int_arith")
     (set_attr "mode" "<MODE>")])
  
+ ;; <x>vfnmsub.{s/d}
+ (define_insn "fnma<mode>4"
+   [(set (match_operand:FVEC 0 "register_operand" "=f")
+ 	(fma:FVEC (neg:FVEC (match_operand:FVEC 1 "register_operand" "f"))
+ 		  (match_operand:FVEC 2 "register_operand" "f")
+ 		  (match_operand:FVEC 3 "register_operand" "f")))]
+   "!HONOR_SIGNED_ZEROS (<MODE>mode)"
+   "<x>vfnmsub.<simdfmt>\t%<wu>0,%<wu>1,%<wu>2,%<wu>3"
+   [(set_attr "type" "simd_fmadd")
+    (set_attr "mode" "<MODE>")])
+ 
  ;; <x>vfcmp.*.{s/d} with defined RTX code
  ;; There are no fcmp.{sugt/suge/cgt/cge}.{s/d} menmonics in GAS, so we have
  ;; to reverse the operands ourselves :(.
***************
*** 826,831 ****
--- 857,895 ----
    DONE;
  })
  
+ (define_expand "<su>dot_prod<wvec_quarter><mode>"
+  [(match_operand:<WVEC_QUARTER> 0 "register_operand" "=f,f")
+   (match_operand:IVEC_HB 1 "register_operand" "f,f")
+   (match_operand:IVEC_HB 2 "register_operand" "f,f")
+   (match_operand:<WVEC_QUARTER> 3 "reg_or_0_operand" "f, YG")
+   (any_extend (const_int 0))]
+   ""
+ {
+   rtx *op = operands;
+   rtx res_mulev = gen_reg_rtx (<WVEC_HALF>mode);
+   rtx res_mulod = gen_reg_rtx (<WVEC_HALF>mode);
+   rtx res_addev = gen_reg_rtx (<WVEC_QUARTER>mode);
+   rtx res_addod = gen_reg_rtx (<WVEC_QUARTER>mode);
+   emit_insn (gen_<simd_isa>_<x>vmulwev_<simdfmt_w>_<simdfmt><u>
+ 	      (res_mulev, op[1], op[2]));
+   emit_insn (gen_<simd_isa>_<x>vmulwod_<simdfmt_w>_<simdfmt><u>
+ 	      (res_mulod, op[1], op[2]));
+   emit_insn (gen_<simd_isa>_<x>vhaddw_<simdfmt_qw><u>_<simdfmt_w><u>
+               (res_addev, res_mulev, res_mulev));
+   emit_insn (gen_<simd_isa>_<x>vhaddw_<simdfmt_qw><u>_<simdfmt_w><u>
+ 	      (res_addod, res_mulod, res_mulod));
+   if (op[3] == CONST0_RTX (<WVEC_QUARTER>mode))
+     emit_insn (gen_add<wvec_quarter>3 (op[0], res_addev,
+ 				       res_addod));
+   else
+     {
+       emit_insn (gen_add<wvec_quarter>3 (res_addev, res_addev,
+ 					 res_addod));
+       emit_insn (gen_add<wvec_quarter>3 (op[0], res_addev, op[3]));
+     }
+   DONE;
+ })
+ 
  (define_insn "simd_maddw_evod_<mode>_hetero"
    [(set (match_operand:<WVEC_HALF> 0 "register_operand" "=f")
  	(plus:<WVEC_HALF>
***************
*** 972,977 ****
--- 1036,1112 ----
    DONE;
  })
  
+ (define_insn "xor<mode>3"
+   [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f")
+ 	(xor:ALLVEC
+ 	  (match_operand:ALLVEC 1 "register_operand" "f,f,f")
+ 	  (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
+   ""
+   "@
+    <x>vxor.v\t%<wu>0,%<wu>1,%<wu>2
+    <x>vbitrevi.%v0\t%<wu>0,%<wu>1,%V2
+    <x>vxori.b\t%<wu>0,%<wu>1,%B2"
+   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
+    (set_attr "mode" "<MODE>")])
+ 
+ (define_insn "ior<mode>3"
+   [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f")
+ 	(ior:ALLVEC
+ 	  (match_operand:ALLVEC 1 "register_operand" "f,f,f")
+ 	  (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
+   ""
+   "@
+    <x>vor.v\t%<wu>0,%<wu>1,%<wu>2
+    <x>vbitseti.%v0\t%<wu>0,%<wu>1,%V2
+    <x>vori.b\t%<wu>0,%<wu>1,%B2"
+   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
+    (set_attr "mode" "<MODE>")])
+ 
+ (define_insn "and<mode>3"
+   [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f")
+ 	(and:ALLVEC
+ 	  (match_operand:ALLVEC 1 "register_operand" "f,f,f")
+ 	  (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
+   ""
+ {
+   switch (which_alternative)
+     {
+     case 0:
+       return "<x>vand.v\t%<wu>0,%<wu>1,%<wu>2";
+     case 1:
+       {
+ 	rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
+ 	unsigned HOST_WIDE_INT val;
+ 	if (GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT)
+ 	  {
+ 	  const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (elt0);
+ 	  if (GET_MODE (elt0) == DFmode)
+ 	    {
+ 	      long tmp[2];
+ 	      REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
+ 	      val = ~((unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0]);
+ 	    }
+ 	  else
+ 	    {
+ 	      long tmp;
+ 	      REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
+ 	      val = ~((unsigned HOST_WIDE_INT) tmp);
+ 	    }
+ 	  }
+ 	else
+ 	  val = ~UINTVAL (elt0);
+ 	operands[2] = loongarch_gen_const_int_vector (<VIMODE>mode, val & (-val));
+ 	return "<x>vbitclri.%v0\t%<wu>0,%<wu>1,%V2";
+       }
+     case 2:
+       return "<x>vandi.b\t%<wu>0,%<wu>1,%B2";
+     default:
+       gcc_unreachable ();
+     }
+ }
+   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
+    (set_attr "mode" "<MODE>")])
+ 
  ; The LoongArch SX Instructions.
  (include "lsx.md")
  
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/bitmanip.md gcc-16-20251102/gcc/config/riscv/bitmanip.md
*** gcc-16-20251026/gcc/config/riscv/bitmanip.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/bitmanip.md	Sun Nov  2 22:32:20 2025
***************
*** 1,4 ****
! ;); Machine description for RISC-V Bit Manipulation operations.
  ;; Copyright (C) 2021-2025 Free Software Foundation, Inc.
  
  ;; This file is part of GCC.
--- 1,4 ----
! ;; Machine description for RISC-V Bit Manipulation operations.
  ;; Copyright (C) 2021-2025 Free Software Foundation, Inc.
  
  ;; This file is part of GCC.
***************
*** 237,255 ****
    [(set_attr "type" "bitmanip")
     (set_attr "mode" "<X:MODE>")])
  
! (define_insn_and_split "*<optab>_not_const<mode>"
!   [(set (match_operand:X 0 "register_operand" "=r")
!        (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
!               (match_operand:X 2 "const_arith_operand" "I")))
!   (clobber (match_scratch:X 3 "=&r"))]
    "(TARGET_ZBB || TARGET_ZBKB) && !TARGET_ZCB
!    && !optimize_function_for_size_p (cfun)"
!   "#"
!   "&& reload_completed"
!   [(set (match_dup 3) (match_dup 2))
!    (set (match_dup 0) (bitmanip_bitwise:X (not:X (match_dup 1)) (match_dup 3)))]
!   ""
!   [(set_attr "type" "bitmanip")])
  
  ;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion).  Without a
  ;; bit of extra help for combine (i.e., the below split), we end up emitting
--- 237,256 ----
    [(set_attr "type" "bitmanip")
     (set_attr "mode" "<X:MODE>")])
  
! (define_peephole2
!   [(match_scratch:X 4 "r")
!    (set (match_operand:X 0 "register_operand")
! 	(not:X (match_operand:X 1 "register_operand")))
!    (set (match_operand:X 2 "register_operand")
! 	(bitmanip_bitwise:X (match_dup 0)
! 			    (match_operand 3 "const_int_operand")))
!    (match_dup 4)]
    "(TARGET_ZBB || TARGET_ZBKB) && !TARGET_ZCB
!    && !optimize_function_for_size_p (cfun)
!    && rtx_equal_p (operands[0], operands[2])
!    && riscv_const_insns (operands[3], false) == 1"
!   [(set (match_dup 4) (match_dup 3))
!    (set (match_dup 0) (bitmanip_bitwise:X (not:X (match_dup 1)) (match_dup 4)))])
  
  ;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion).  Without a
  ;; bit of extra help for combine (i.e., the below split), we end up emitting
***************
*** 356,362 ****
  {
    if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
      FAIL;
!   if (TARGET_64BIT && register_operand (operands[2], QImode))
      {
        rtx t = gen_reg_rtx (DImode);
        emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2]));
--- 357,363 ----
  {
    if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
      FAIL;
!   if (TARGET_64BIT)
      {
        rtx t = gen_reg_rtx (DImode);
        emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2]));
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/riscv-avlprop.cc gcc-16-20251102/gcc/config/riscv/riscv-avlprop.cc
*** gcc-16-20251026/gcc/config/riscv/riscv-avlprop.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/riscv-avlprop.cc	Sun Nov  2 22:32:20 2025
*************** along with GCC; see the file COPYING3.
*** 77,82 ****
--- 77,83 ----
  #include "tree-pass.h"
  #include "df.h"
  #include "rtl-ssa.h"
+ #include "rtl-iter.h"
  #include "cfgcleanup.h"
  #include "insn-attr.h"
  #include "tm-constrs.h"
*************** pass_avlprop::get_vlmax_ta_preferred_avl
*** 412,417 ****
--- 413,458 ----
  		  && def1->insn ()->compare_with (insn) >= 0)
  		return NULL_RTX;
  	    }
+ 	  else
+ 	    {
+ 	      /* If the use is in a subreg e.g. in a store it is possible that
+ 		 we punned the vector mode with a larger mode like
+ 		   (subreg:V1SI (reg:V4QI 123)).
+ 		 For an AVL of 1 that means we actually store one SImode
+ 		 element and not 1 QImode elements.  But the latter is what we
+ 		 would propagate if we took the AVL operand literally.
+ 		 Instead we scale it by the ratio of inner and outer mode
+ 		 (4 in the example above).  */
+ 	      int factor = 1;
+ 	      if (use->includes_subregs ())
+ 		{
+ 		  subrtx_iterator::array_type array;
+ 		  FOR_EACH_SUBRTX (iter, array, use_insn->rtl (), NONCONST)
+ 		    {
+ 		      const_rtx x = *iter;
+ 		      if (x
+ 			  && SUBREG_P (x)
+ 			  && REG_P (SUBREG_REG (x))
+ 			  && REGNO (SUBREG_REG (x)) == use->regno ()
+ 			  && known_eq (GET_MODE_SIZE (use->mode ()),
+ 				       GET_MODE_SIZE (GET_MODE (x))))
+ 			{
+ 			  if (can_div_trunc_p (GET_MODE_NUNITS (use->mode ()),
+ 					       GET_MODE_NUNITS (GET_MODE (x)),
+ 					       &factor))
+ 			    {
+ 			      gcc_assert (factor > 0);
+ 			      break;
+ 			    }
+ 			  else
+ 			    return NULL_RTX;
+ 			}
+ 		    }
+ 		}
+ 
+ 	      if (factor > 1)
+ 		new_use_avl = GEN_INT (INTVAL (new_use_avl) * factor);
+ 	    }
  
  	  if (!use_avl)
  	    use_avl = new_use_avl;
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/riscv-protos.h gcc-16-20251102/gcc/config/riscv/riscv-protos.h
*** gcc-16-20251026/gcc/config/riscv/riscv-protos.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/riscv-protos.h	Sun Nov  2 22:32:20 2025
*************** rtl_opt_pass * make_pass_insert_landing_
*** 209,214 ****
--- 209,219 ----
  rtl_opt_pass * make_pass_vector_permconst (gcc::context *ctxt);
  rtl_opt_pass * make_pass_bclr_lowest_set_bit (gcc::context *ctxt);
  
+ /* Routines implemented in riscv-vsetvl.cc.  */
+ extern bool has_vtype_op (rtx_insn *);
+ extern bool mask_agnostic_p (rtx_insn *);
+ extern rtx get_avl (rtx_insn *);
+ extern bool vsetvl_insn_p (rtx_insn *);
  
  /* Routines implemented in riscv-string.c.  */
  extern bool riscv_expand_block_compare (rtx, rtx, rtx, rtx);
*************** extern bool th_print_operand_address (FI
*** 834,840 ****
  extern bool strided_load_broadcast_p (void);
  extern bool riscv_prefer_agnostic_p (void);
  extern bool riscv_use_divmod_expander (void);
! void riscv_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, tree, int);
  extern bool
  riscv_option_valid_attribute_p (tree, tree, tree, int);
  extern bool
--- 839,846 ----
  extern bool strided_load_broadcast_p (void);
  extern bool riscv_prefer_agnostic_p (void);
  extern bool riscv_use_divmod_expander (void);
! void riscv_init_cumulative_args (CUMULATIVE_ARGS *, const_tree,
! 				 rtx, tree, int, bool);
  extern bool
  riscv_option_valid_attribute_p (tree, tree, tree, int);
  extern bool
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/riscv-vector-builtins-bases.cc gcc-16-20251102/gcc/config/riscv/riscv-vector-builtins-bases.cc
*** gcc-16-20251026/gcc/config/riscv/riscv-vector-builtins-bases.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/riscv-vector-builtins-bases.cc	Sun Nov  2 22:32:20 2025
*************** public:
*** 1793,1804 ****
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (unshare_expr (f.lhs), rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array
!       = build3 (COMPONENT_REF, TREE_TYPE (field), f.lhs, field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector), lhs_array,
  			      index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
--- 1793,1805 ----
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (f.lhs, rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array
!       = build3 (COMPONENT_REF, TREE_TYPE (field), unshare_expr (f.lhs),
! 		field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector), lhs_array,
  			      index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/riscv-vsetvl.cc gcc-16-20251102/gcc/config/riscv/riscv-vsetvl.cc
*** gcc-16-20251026/gcc/config/riscv/riscv-vsetvl.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/riscv-vsetvl.cc	Sun Nov  2 22:32:20 2025
*************** policy_to_str (bool agnostic_p)
*** 258,264 ****
  
  /* Return true if it is an RVV instruction depends on VTYPE global
     status register.  */
! static bool
  has_vtype_op (rtx_insn *rinsn)
  {
    return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn);
--- 258,264 ----
  
  /* Return true if it is an RVV instruction depends on VTYPE global
     status register.  */
! bool
  has_vtype_op (rtx_insn *rinsn)
  {
    return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn);
*************** vector_config_insn_p (rtx_insn *rinsn)
*** 306,312 ****
  }
  
  /* Return true if it is vsetvldi or vsetvlsi.  */
! static bool
  vsetvl_insn_p (rtx_insn *rinsn)
  {
    if (!rinsn || !vector_config_insn_p (rinsn))
--- 306,312 ----
  }
  
  /* Return true if it is vsetvldi or vsetvlsi.  */
! bool
  vsetvl_insn_p (rtx_insn *rinsn)
  {
    if (!rinsn || !vector_config_insn_p (rinsn))
*************** get_vl (rtx_insn *rinsn)
*** 386,392 ****
  }
  
  /* Helper function to get AVL operand.  */
! static rtx
  get_avl (rtx_insn *rinsn)
  {
    if (vsetvl_insn_p (rinsn) || vsetvl_discard_result_insn_p (rinsn))
--- 386,392 ----
  }
  
  /* Helper function to get AVL operand.  */
! rtx
  get_avl (rtx_insn *rinsn)
  {
    if (vsetvl_insn_p (rinsn) || vsetvl_discard_result_insn_p (rinsn))
*************** get_default_ma ()
*** 411,417 ****
  }
  
  /* Helper function to get MA operand.  */
! static bool
  mask_agnostic_p (rtx_insn *rinsn)
  {
    /* If it doesn't have MA, we return agnostic by default.  */
--- 411,417 ----
  }
  
  /* Helper function to get MA operand.  */
! bool
  mask_agnostic_p (rtx_insn *rinsn)
  {
    /* If it doesn't have MA, we return agnostic by default.  */
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/riscv.cc gcc-16-20251102/gcc/config/riscv/riscv.cc
*** gcc-16-20251026/gcc/config/riscv/riscv.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/riscv.cc	Sun Nov  2 22:32:20 2025
*************** static tree riscv_handle_fndecl_attribut
*** 740,745 ****
--- 740,746 ----
  static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
  static tree riscv_handle_rvv_vector_bits_attribute (tree *, tree, tree, int,
  						    bool *);
+ static tree riscv_handle_rvv_vls_cc_attribute (tree *, tree, tree, int, bool *);
  
  /* Defining target-specific uses of __attribute__.  */
  static const attribute_spec riscv_gnu_attributes[] =
*************** static const attribute_spec riscv_gnu_at
*** 763,768 ****
--- 764,771 ----
      standard vector calling convention variant. Syntax:
      __attribute__((riscv_vector_cc)). */
    {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL},
+   {"riscv_vls_cc", 0, 1, false, true, true, true,
+    riscv_handle_rvv_vls_cc_attribute, NULL},
    /* This attribute is used to declare a new type, to appoint the exactly
       bits size of the type.  For example:
  
*************** static const attribute_spec riscv_attrib
*** 790,795 ****
--- 793,800 ----
       standard vector calling convention variant. Syntax:
       [[riscv::vector_cc]]. */
    {"vector_cc", 0, 0, false, true, true, true, NULL, NULL},
+   {"vls_cc", 0, 1, false, true, true, true, riscv_handle_rvv_vls_cc_attribute,
+    NULL},
    /* This attribute is used to declare a new type, to appoint the exactly
       bits size of the type.  For example:
  
*************** typedef struct {
*** 5878,5888 ****
     floating-point registers.  */
  
  static int
! riscv_flatten_aggregate_field (const_tree type,
! 			       riscv_aggregate_field fields[2],
  			       int n, HOST_WIDE_INT offset,
! 			       bool ignore_zero_width_bit_field_p)
  {
    switch (TREE_CODE (type))
      {
      case RECORD_TYPE:
--- 5883,5894 ----
     floating-point registers.  */
  
  static int
! riscv_flatten_aggregate_field (const_tree type, riscv_aggregate_field *fields,
  			       int n, HOST_WIDE_INT offset,
! 			       bool ignore_zero_width_bit_field_p,
! 			       bool vls_p = false, unsigned abi_vlen = 0)
  {
+   int max_aggregate_field = vls_p ? 8 : 2;
    switch (TREE_CODE (type))
      {
      case RECORD_TYPE:
*************** riscv_flatten_aggregate_field (const_tre
*** 5909,5917 ****
  	    else
  	      {
  		HOST_WIDE_INT pos = offset + int_byte_position (f);
! 		n = riscv_flatten_aggregate_field (TREE_TYPE (f),
! 						   fields, n, pos,
! 						   ignore_zero_width_bit_field_p);
  	      }
  	    if (n < 0)
  	      return -1;
--- 5915,5923 ----
  	    else
  	      {
  		HOST_WIDE_INT pos = offset + int_byte_position (f);
! 		n = riscv_flatten_aggregate_field (
! 		  TREE_TYPE (f), fields, n, pos, ignore_zero_width_bit_field_p,
! 		  vls_p, abi_vlen);
  	      }
  	    if (n < 0)
  	      return -1;
*************** riscv_flatten_aggregate_field (const_tre
*** 5921,5933 ****
      case ARRAY_TYPE:
        {
  	HOST_WIDE_INT n_elts;
! 	riscv_aggregate_field subfields[2];
  	tree index = TYPE_DOMAIN (type);
  	tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type));
! 	int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type),
! 							 subfields, 0, offset,
! 							 ignore_zero_width_bit_field_p);
! 
  	/* Can't handle incomplete types nor sizes that are not fixed.  */
  	if (n_subfields <= 0
  	    || !COMPLETE_TYPE_P (type)
--- 5927,5940 ----
      case ARRAY_TYPE:
        {
  	HOST_WIDE_INT n_elts;
! 	riscv_aggregate_field subfields[8];
  	tree index = TYPE_DOMAIN (type);
  	tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type));
! 	int n_subfields
! 	  = riscv_flatten_aggregate_field (TREE_TYPE (type), subfields, 0,
! 					   offset,
! 					   ignore_zero_width_bit_field_p, vls_p,
! 					   abi_vlen);
  	/* Can't handle incomplete types nor sizes that are not fixed.  */
  	if (n_subfields <= 0
  	    || !COMPLETE_TYPE_P (type)
*************** riscv_flatten_aggregate_field (const_tre
*** 5947,5953 ****
  	for (HOST_WIDE_INT i = 0; i < n_elts; i++)
  	  for (int j = 0; j < n_subfields; j++)
  	    {
! 	      if (n >= 2)
  		return -1;
  
  	      fields[n] = subfields[j];
--- 5954,5960 ----
  	for (HOST_WIDE_INT i = 0; i < n_elts; i++)
  	  for (int j = 0; j < n_subfields; j++)
  	    {
! 	      if (n >= max_aggregate_field)
  		return -1;
  
  	      fields[n] = subfields[j];
*************** riscv_flatten_aggregate_field (const_tre
*** 5979,5996 ****
        }
  
      default:
!       if (n < 2
! 	  && ((SCALAR_FLOAT_TYPE_P (type)
! 	       && GET_MODE_SIZE (TYPE_MODE (type)).to_constant () <= UNITS_PER_FP_ARG)
! 	      || (INTEGRAL_TYPE_P (type)
! 		  && GET_MODE_SIZE (TYPE_MODE (type)).to_constant () <= UNITS_PER_WORD)))
  	{
! 	  fields[n].type = type;
! 	  fields[n].offset = offset;
! 	  return n + 1;
  	}
        else
! 	return -1;
      }
  }
  
--- 5986,6021 ----
        }
  
      default:
!       poly_uint64 mode_size = GET_MODE_SIZE (TYPE_MODE (type));
!       if (vls_p)
  	{
! 	  gcc_assert (abi_vlen != 0);
! 	  if (n < max_aggregate_field
! 	      && (VECTOR_TYPE_P (type) && mode_size.is_constant ()
! 		  && (mode_size.to_constant () <= abi_vlen * 8)))
! 	    {
! 	      fields[n].type = type;
! 	      fields[n].offset = offset;
! 	      return n + 1;
! 	    }
! 	  else
! 	    return -1;
  	}
        else
! 	{
! 	  if (n < max_aggregate_field
! 	      && ((SCALAR_FLOAT_TYPE_P (type)
! 		   && mode_size.to_constant () <= UNITS_PER_FP_ARG)
! 		  || (INTEGRAL_TYPE_P (type)
! 		      && mode_size.to_constant () <= UNITS_PER_WORD)))
! 	    {
! 	      fields[n].type = type;
! 	      fields[n].offset = offset;
! 	      return n + 1;
! 	    }
! 	  else
! 	    return -1;
! 	}
      }
  }
  
*************** riscv_flatten_aggregate_field (const_tre
*** 5999,6012 ****
  
  static int
  riscv_flatten_aggregate_argument (const_tree type,
! 				  riscv_aggregate_field fields[2],
! 				  bool ignore_zero_width_bit_field_p)
  {
    if (!type || TREE_CODE (type) != RECORD_TYPE)
      return -1;
  
    return riscv_flatten_aggregate_field (type, fields, 0, 0,
! 					ignore_zero_width_bit_field_p);
  }
  
  /* See whether TYPE is a record whose fields should be returned in one or
--- 6024,6039 ----
  
  static int
  riscv_flatten_aggregate_argument (const_tree type,
! 				  riscv_aggregate_field *fields,
! 				  bool ignore_zero_width_bit_field_p,
! 				  bool vls_p = false, unsigned abi_vlen = 0)
  {
    if (!type || TREE_CODE (type) != RECORD_TYPE)
      return -1;
  
    return riscv_flatten_aggregate_field (type, fields, 0, 0,
! 					ignore_zero_width_bit_field_p, vls_p,
! 					abi_vlen);
  }
  
  /* See whether TYPE is a record whose fields should be returned in one or
*************** riscv_pass_vls_aggregate_in_gpr (struct
*** 6169,6186 ****
    return gen_rtx_PARALLEL (mode, gen_rtvec (1, x));
  }
  
  /* Initialize a variable CUM of type CUMULATIVE_ARGS
     for a call to a function whose data type is FNTYPE.
     For a library call, FNTYPE is 0.  */
  
  void
  riscv_init_cumulative_args (CUMULATIVE_ARGS *cum, const_tree fntype,
! 			    rtx, tree, int)
  {
    memset (cum, 0, sizeof (*cum));
  
    if (fntype)
!     cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
    else
      cum->variant_cc = RISCV_CC_BASE;
  }
--- 6196,6217 ----
    return gen_rtx_PARALLEL (mode, gen_rtvec (1, x));
  }
  
+ static const predefined_function_abi &
+ riscv_fntype_abi_1 (const_tree fntype, bool check_only);
+ 
  /* Initialize a variable CUM of type CUMULATIVE_ARGS
     for a call to a function whose data type is FNTYPE.
     For a library call, FNTYPE is 0.  */
  
  void
  riscv_init_cumulative_args (CUMULATIVE_ARGS *cum, const_tree fntype,
! 			    rtx, tree, int, bool check_only)
  {
    memset (cum, 0, sizeof (*cum));
  
    if (fntype)
!     cum->variant_cc =
!       (riscv_cc) riscv_fntype_abi_1 (fntype, check_only).id ();
    else
      cum->variant_cc = RISCV_CC_BASE;
  }
*************** riscv_hard_regno_nregs (unsigned int reg
*** 6203,6209 ****
  
  static rtx
  riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
! 		      machine_mode mode, bool return_p)
  {
    gcc_assert (riscv_v_ext_mode_p (mode));
  
--- 6234,6240 ----
  
  static rtx
  riscv_get_vector_arg (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
! 		      machine_mode mode, bool return_p, bool vls_p = false)
  {
    gcc_assert (riscv_v_ext_mode_p (mode));
  
*************** riscv_get_vector_arg (struct riscv_arg_i
*** 6239,6246 ****
    int arg_reg_end = V_ARG_LAST - V_REG_FIRST;
    int aligned_reg_start = ROUND_UP (arg_reg_start, LMUL);
  
!   /* For scalable data and scalable tuple return value.  */
!   if (return_p)
      return gen_rtx_REG (mode, aligned_reg_start + V_REG_FIRST);
  
    /* Iterate through the USED_VRS array to find vector register groups that have
--- 6270,6278 ----
    int arg_reg_end = V_ARG_LAST - V_REG_FIRST;
    int aligned_reg_start = ROUND_UP (arg_reg_start, LMUL);
  
!   /* For scalable data and scalable tuple return value.
!      For VLS CC, we may pass struct like tuple, so need defer the handling.  */
!   if (return_p && !vls_p)
      return gen_rtx_REG (mode, aligned_reg_start + V_REG_FIRST);
  
    /* Iterate through the USED_VRS array to find vector register groups that have
*************** riscv_get_vector_arg (struct riscv_arg_i
*** 6277,6282 ****
--- 6309,6532 ----
    return NULL_RTX;
  }
  
+ 
+ #define RISCV_ALL_VALID_ABI_VLEN(F) \
+   F (32) \
+   F (64) \
+   F (128) \
+   F (256) \
+   F (512) \
+   F (1024) \
+   F (2048) \
+   F (4096) \
+   F (8192) \
+   F (16384)
+ 
+ /* Return true if CC is a variant of VLS CC.  */
+ 
+ static bool
+ riscv_vls_cc_p (riscv_cc cc)
+ {
+   switch (cc)
+     {
+ #define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \
+   case RISCV_CC_VLS_V_##ABI_VLEN:
+     RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE)
+ 
+ #undef VLS_CC_ABI_VLEN_CASE
+       return true;
+     default:
+       return false;
+     }
+ }
+ 
+ /* Get ABI_VLEN from cc.  */
+ 
+ static unsigned int
+ riscv_get_cc_abi_vlen (riscv_cc cc)
+ {
+   switch (cc)
+     {
+ #define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \
+       case RISCV_CC_VLS_V_##ABI_VLEN: \
+ 	return ABI_VLEN;
+     RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE)
+ 
+ #undef VLS_CC_ABI_VLEN_CASE
+     default:
+       gcc_unreachable ();
+     }
+ }
+ 
+ /* Return true if ABI_VLEN is a valid for VLS_CC.  */
+ 
+ static bool
+ riscv_valid_abi_vlen_vls_cc_p (unsigned abi_vlen)
+ {
+   switch (abi_vlen)
+     {
+ #define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \
+   case ABI_VLEN:
+     RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE)
+ 
+ #undef VLS_CC_ABI_VLEN_CASE
+       return true;
+     default:
+       return false;
+     }
+ }
+ 
+ static riscv_cc
+ riscv_get_riscv_cc_by_abi_vlen (unsigned abi_vlen)
+ {
+   switch (abi_vlen)
+     {
+ #define VLS_CC_ABI_VLEN_CASE(ABI_VLEN) \
+       case ABI_VLEN: \
+ 	return RISCV_CC_VLS_V_##ABI_VLEN;
+     RISCV_ALL_VALID_ABI_VLEN (VLS_CC_ABI_VLEN_CASE)
+ 
+ #undef VLS_CC_ABI_VLEN_CASE
+     default:
+       gcc_unreachable ();
+     }
+ }
+ 
+ /* Get a VLS type has same size as MODE in ABI_VLEN, but element is always
+    in integer mode.  */
+ 
+ static machine_mode
+ riscv_get_vls_container_type (machine_mode mode, unsigned abi_vlen)
+ {
+   machine_mode element_mode = GET_MODE_INNER (mode);
+   unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();
+   unsigned int lmul = ROUND_UP (mode_size * 8, abi_vlen) / abi_vlen;
+ 
+   /* Always use integer mode to pass to simplify the logic - we allow pass
+      unsupported vector type in vector register, e.g. float16x4_t even no vector
+      fp16 support.  */
+   switch (GET_MODE_SIZE (element_mode).to_constant ())
+     {
+     case 1:
+       element_mode = QImode;
+       break;
+     case 2:
+       element_mode = HImode;
+       break;
+     case 4:
+       element_mode = SImode;
+       break;
+     case 8:
+       element_mode = DImode;
+       break;
+     default:
+       gcc_unreachable ();
+     }
+ 
+   scalar_mode smode = as_a<scalar_mode> (element_mode);
+   return get_lmul_mode (smode, lmul).require ();
+ }
+ 
+ /* Pass VLS type argument in vector argument register.  */
+ 
+ static rtx
+ riscv_pass_vls_in_vr (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
+ 		      machine_mode mode, bool return_p)
+ {
+   gcc_assert (riscv_v_ext_vls_mode_p (mode));
+ 
+   unsigned int abi_vlen = riscv_get_cc_abi_vlen (cum->variant_cc);
+   unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();
+   unsigned int lmul = ROUND_UP (mode_size * 8, abi_vlen) / abi_vlen;
+ 
+   /* Put into memory if it need more than 8 registers (> LMUL 8).  */
+   if (lmul > 8)
+     return NULL_RTX;
+ 
+   machine_mode vla_mode = riscv_get_vls_container_type (mode, abi_vlen);
+   rtx reg = riscv_get_vector_arg (info, cum, vla_mode,
+ 				  return_p, /* vls_p */ true);
+ 
+   /* Can't get vector register to pass, pass by memory.  */
+   if (!reg)
+     return NULL_RTX;
+ 
+   PUT_MODE (reg, mode);
+ 
+   return reg;
+ }
+ 
+ /* Pass aggregate with VLS type argument in vector argument registers.  */
+ 
+ static rtx
+ riscv_pass_aggregate_in_vr (struct riscv_arg_info *info,
+ 			    const CUMULATIVE_ARGS *cum, const_tree type,
+ 			    bool return_p)
+ {
+   riscv_aggregate_field fields[8];
+   unsigned int abi_vlen = riscv_get_cc_abi_vlen (cum->variant_cc);
+   int i;
+   int n = riscv_flatten_aggregate_argument (type, fields, true,
+ 					    /* vls_p */ true, abi_vlen);
+ 
+   if (n == -1)
+     return NULL_RTX;
+ 
+   /* Check all field has same size.  */
+   unsigned int mode_size
+     = GET_MODE_SIZE (TYPE_MODE (fields[0].type)).to_constant ();
+   for (int i = 1; i < n; i++)
+     if (GET_MODE_SIZE (TYPE_MODE (fields[i].type)).to_constant () != mode_size)
+       return NULL_RTX; /* Return NULL_RTX if we cannot find a suitable reg.  */
+ 
+   /* Check total size is <= abi_vlen * 8, we use up to 8 vector register to
+      pass argument.  */
+   if (mode_size * 8 > abi_vlen)
+     return NULL_RTX; /* Return NULL_RTX if we cannot find a suitable reg.  */
+ 
+   /* Backup cum->used_vrs since we will defer the update until
+      riscv_function_arg_advance.  */
+   CUMULATIVE_ARGS local_cum;
+   memcpy (&local_cum, cum, sizeof (local_cum));
+ 
+   unsigned num_vrs = 0;
+ 
+   /* Allocate vector registers for the arguments.  */
+   rtx expr_list[8];
+   for (i = 0; i < n; i++)
+     {
+       machine_mode mode = TYPE_MODE (fields[i].type);
+       machine_mode vla_mode = riscv_get_vls_container_type (mode, abi_vlen);
+       /* Use riscv_get_vector_arg with VLA type to simplify the calling
+ 	 convention implementation.  */
+       rtx reg
+ 	= riscv_get_vector_arg (info, &local_cum, vla_mode,
+ 				return_p, /* vls_p */true);
+ 
+       /* Can't get vector register to pass, pass by memory.  */
+       if (!reg)
+ 	return NULL_RTX;
+ 
+       PUT_MODE (reg, mode);
+ 
+       expr_list[i]
+ 	= gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (fields[i].offset));
+ 
+       num_vrs += info->num_vrs;
+ 
+       /* Set the corresponding register in USED_VRS to used status.  */
+       for (unsigned int i = 0; i < info->num_vrs; i++)
+ 	{
+ 	  gcc_assert (!local_cum.used_vrs[info->vr_offset + i]);
+ 	  local_cum.used_vrs[info->vr_offset + i] = true;
+ 	}
+     }
+ 
+   info->num_vrs = num_vrs;
+ 
+   return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (n, expr_list));
+ }
+ 
  /* Fill INFO with information about a single argument, and return an RTL
     pattern to pass or return the argument. Return NULL_RTX if argument cannot
     pass or return in registers, then the argument may be passed by reference or
*************** riscv_get_arg_info (struct riscv_arg_inf
*** 6369,6375 ****
        if (riscv_vector_type_p (type) && riscv_v_ext_mode_p (mode))
  	return riscv_get_vector_arg (info, cum, mode, return_p);
  
!       /* For vls mode aggregated in gpr.  */
        if (riscv_v_ext_vls_mode_p (mode))
  	return riscv_pass_vls_aggregate_in_gpr (info, mode, gpr_base);
      }
--- 6619,6635 ----
        if (riscv_vector_type_p (type) && riscv_v_ext_mode_p (mode))
  	return riscv_get_vector_arg (info, cum, mode, return_p);
  
!       if (riscv_vls_cc_p (cum->variant_cc))
! 	{
! 	  if (riscv_v_ext_vls_mode_p (mode))
! 	    return riscv_pass_vls_in_vr (info, cum, mode, return_p);
! 
! 	  rtx ret = riscv_pass_aggregate_in_vr (info, cum, type, return_p);
! 	  if (ret)
! 	    return ret;
! 	}
! 
!       /* For vls mode aggregated in gpr (for non-VLS-CC).  */
        if (riscv_v_ext_vls_mode_p (mode))
  	return riscv_pass_vls_aggregate_in_gpr (info, mode, gpr_base);
      }
*************** riscv_function_arg_advance (cumulative_a
*** 6426,6432 ****
        cum->used_vrs[info.vr_offset + i] = true;
      }
  
!   if ((info.num_vrs > 0 || info.num_mrs > 0) && cum->variant_cc != RISCV_CC_V)
      {
        error ("RVV type %qT cannot be passed to an unprototyped function",
  	     arg.type);
--- 6686,6693 ----
        cum->used_vrs[info.vr_offset + i] = true;
      }
  
!   if ((info.num_vrs > 0 || info.num_mrs > 0) && cum->variant_cc != RISCV_CC_V
!       && !riscv_vls_cc_p (cum->variant_cc))
      {
        error ("RVV type %qT cannot be passed to an unprototyped function",
  	     arg.type);
*************** riscv_function_value (const_tree ret_typ
*** 6469,6475 ****
      {
        const_tree fntype = TREE_CODE (fn_decl_or_type) == FUNCTION_DECL ?
  			    TREE_TYPE (fn_decl_or_type) : fn_decl_or_type;
!       riscv_init_cumulative_args (&args, fntype, NULL_RTX, NULL_TREE, 0);
      }
    else
      memset (&args, 0, sizeof args);
--- 6730,6737 ----
      {
        const_tree fntype = TREE_CODE (fn_decl_or_type) == FUNCTION_DECL ?
  			    TREE_TYPE (fn_decl_or_type) : fn_decl_or_type;
!       riscv_init_cumulative_args (&args, fntype, NULL_RTX, NULL_TREE, 0,
! 				  /* check_only */true);
      }
    else
      memset (&args, 0, sizeof args);
*************** riscv_pass_by_reference (cumulative_args
*** 6538,6551 ****
  /* Implement TARGET_RETURN_IN_MEMORY.  */
  
  static bool
! riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
  {
    CUMULATIVE_ARGS args;
    cumulative_args_t cum = pack_cumulative_args (&args);
  
-   /* The rules for returning in memory are the same as for passing the
-      first named argument by reference.  */
-   memset (&args, 0, sizeof args);
    function_arg_info arg (const_cast<tree> (type), /*named=*/true);
    return riscv_pass_by_reference (cum, arg);
  }
--- 6800,6819 ----
  /* Implement TARGET_RETURN_IN_MEMORY.  */
  
  static bool
! riscv_return_in_memory (const_tree type, const_tree fntype)
  {
    CUMULATIVE_ARGS args;
+ 
+   if (fntype)
+     riscv_init_cumulative_args (&args, fntype, NULL_RTX, NULL_TREE, 0,
+ 				/* check_only */true);
+   else
+     /* The rules for returning in memory are the same as for passing the
+        first named argument by reference.  */
+     memset (&args, 0, sizeof args);
+ 
    cumulative_args_t cum = pack_cumulative_args (&args);
  
    function_arg_info arg (const_cast<tree> (type), /*named=*/true);
    return riscv_pass_by_reference (cum, arg);
  }
*************** riscv_setup_incoming_varargs (cumulative
*** 6589,6597 ****
  /* Return the descriptor of the Standard Vector Calling Convention Variant.  */
  
  static const predefined_function_abi &
! riscv_v_abi ()
  {
!   predefined_function_abi &v_abi = function_abis[RISCV_CC_V];
    if (!v_abi.initialized_p ())
      {
        HARD_REG_SET full_reg_clobbers
--- 6857,6865 ----
  /* Return the descriptor of the Standard Vector Calling Convention Variant.  */
  
  static const predefined_function_abi &
! riscv_v_abi (riscv_cc abi)
  {
!   predefined_function_abi &v_abi = function_abis[abi];
    if (!v_abi.initialized_p ())
      {
        HARD_REG_SET full_reg_clobbers
*************** riscv_v_abi ()
*** 6601,6607 ****
  	CLEAR_HARD_REG_BIT (full_reg_clobbers, regno);
        for (int regno = V_REG_FIRST + 24; regno <= V_REG_FIRST + 31; regno += 1)
  	CLEAR_HARD_REG_BIT (full_reg_clobbers, regno);
!       v_abi.initialize (RISCV_CC_V, full_reg_clobbers);
      }
    return v_abi;
  }
--- 6869,6875 ----
  	CLEAR_HARD_REG_BIT (full_reg_clobbers, regno);
        for (int regno = V_REG_FIRST + 24; regno <= V_REG_FIRST + 31; regno += 1)
  	CLEAR_HARD_REG_BIT (full_reg_clobbers, regno);
!       v_abi.initialize (abi, full_reg_clobbers);
      }
    return v_abi;
  }
*************** riscv_validate_vector_type (const_tree t
*** 6762,6774 ****
     RISC-V V registers.  */
  
  static bool
! riscv_return_value_is_vector_type_p (const_tree fntype)
  {
    tree return_type = TREE_TYPE (fntype);
  
    if (riscv_vector_type_p (return_type))
      {
!       riscv_validate_vector_type (return_type, "return type");
        return true;
      }
    else
--- 7030,7043 ----
     RISC-V V registers.  */
  
  static bool
! riscv_return_value_is_vector_type_p (const_tree fntype, bool check_only)
  {
    tree return_type = TREE_TYPE (fntype);
  
    if (riscv_vector_type_p (return_type))
      {
!       if (!check_only)
! 	riscv_validate_vector_type (return_type, "return type");
        return true;
      }
    else
*************** riscv_return_value_is_vector_type_p (con
*** 6779,6785 ****
     RISC-V V registers.  */
  
  static bool
! riscv_arguments_is_vector_type_p (const_tree fntype)
  {
    for (tree chain = TYPE_ARG_TYPES (fntype); chain && chain != void_list_node;
         chain = TREE_CHAIN (chain))
--- 7048,7054 ----
     RISC-V V registers.  */
  
  static bool
! riscv_arguments_is_vector_type_p (const_tree fntype, bool check_only)
  {
    for (tree chain = TYPE_ARG_TYPES (fntype); chain && chain != void_list_node;
         chain = TREE_CHAIN (chain))
*************** riscv_arguments_is_vector_type_p (const_
*** 6787,6793 ****
        tree arg_type = TREE_VALUE (chain);
        if (riscv_vector_type_p (arg_type))
  	{
! 	  riscv_validate_vector_type (arg_type, "argument type");
  	  return true;
  	}
      }
--- 7056,7063 ----
        tree arg_type = TREE_VALUE (chain);
        if (riscv_vector_type_p (arg_type))
  	{
! 	  if (!check_only)
! 	    riscv_validate_vector_type (arg_type, "argument type");
  	  return true;
  	}
      }
*************** riscv_arguments_is_vector_type_p (const_
*** 6798,6811 ****
  /* Return true if FUNC is a riscv_vector_cc function.
     For more details please reference the below link.
     https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
  static bool
! riscv_vector_cc_function_p (const_tree fntype)
  {
    tree attr = TYPE_ATTRIBUTES (fntype);
    bool vector_cc_p = lookup_attribute ("vector_cc", attr) != NULL_TREE
      || lookup_attribute ("riscv_vector_cc", attr) != NULL_TREE;
  
!   if (vector_cc_p && !TARGET_VECTOR)
      error_at (input_location,
  	      "function attribute %qs requires the V ISA extension",
  	      "riscv_vector_cc");
--- 7068,7082 ----
  /* Return true if FUNC is a riscv_vector_cc function.
     For more details please reference the below link.
     https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
+ 
  static bool
! riscv_vector_cc_function_p (const_tree fntype, bool check_only)
  {
    tree attr = TYPE_ATTRIBUTES (fntype);
    bool vector_cc_p = lookup_attribute ("vector_cc", attr) != NULL_TREE
      || lookup_attribute ("riscv_vector_cc", attr) != NULL_TREE;
  
!   if (vector_cc_p && !TARGET_VECTOR && !check_only)
      error_at (input_location,
  	      "function attribute %qs requires the V ISA extension",
  	      "riscv_vector_cc");
*************** riscv_vector_cc_function_p (const_tree f
*** 6813,6838 ****
    return vector_cc_p;
  }
  
! /* Implement TARGET_FNTYPE_ABI.  */
  
  static const predefined_function_abi &
! riscv_fntype_abi (const_tree fntype)
  {
    /* Implement the vector calling convention.  For more details please
       reference the below link.
       https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389  */
    bool validate_v_abi_p = false;
  
!   validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype);
!   validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype);
!   validate_v_abi_p |= riscv_vector_cc_function_p (fntype);
  
    if (validate_v_abi_p)
!     return riscv_v_abi ();
  
    return default_function_abi;
  }
  
  /* Return riscv calling convention of call_insn.  */
  riscv_cc
  get_riscv_cc (const rtx use)
--- 7084,7174 ----
    return vector_cc_p;
  }
  
! /* Return the riscv_cc value according to the attribute arguments.
!    If the attribute arguments are invalid, return RISCV_CC_UNKNOWN
!    and emit an error message.  */
! 
! static riscv_cc
! riscv_get_vls_cc_attr (const_tree args, bool check_only = false)
! {
!   /* Default ABI_VLEN is 128.  */
!   int abi_vlen = 128;
! 
!   if (args && TREE_CODE (args) == TREE_LIST)
!     {
!       tree vlen_arg = TREE_VALUE (args);
!       if (vlen_arg && TREE_CODE (vlen_arg) == INTEGER_CST)
! 	abi_vlen = TREE_INT_CST_LOW (vlen_arg);
!     }
! 
!   if (!riscv_valid_abi_vlen_vls_cc_p (abi_vlen) && !check_only)
!     {
!       error_at (input_location,
! 		"unsupported %<ABI_VLEN%> value %d for %qs attribute;"
! 		"%<ABI_VLEN must%> be in the range [32, 16384] and must be "
! 		"a power of 2",
! 		abi_vlen, "riscv_vls_cc");
!       return RISCV_CC_UNKNOWN;
!     }
! 
!   return riscv_get_riscv_cc_by_abi_vlen (abi_vlen);
! }
! 
! /* Return true if FUNC is a riscv_vector_cc function.
!    For more details please reference the below link.
!    https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
! static riscv_cc
! riscv_vls_cc_function_abi (const_tree fntype, bool check_only)
! {
!   tree attr = TYPE_ATTRIBUTES (fntype);
!   bool vls_cc_p = lookup_attribute ("vls_cc", attr) != NULL_TREE
! 		  || lookup_attribute ("riscv_vls_cc", attr) != NULL_TREE;
! 
!   if (!vls_cc_p)
!     return RISCV_CC_UNKNOWN;
! 
!   if (!TARGET_VECTOR && !check_only)
!     error_at (input_location,
! 	      "function attribute %qs requires the vector ISA extension",
! 	      "riscv_vls_cc");
! 
!   tree args = TREE_VALUE (attr);
!   return riscv_get_vls_cc_attr (args);
! }
! 
! /* Implemention of TARGET_FNTYPE_ABI, but one extra parameter `check_only`
!    to suppress warning message.  */
  
  static const predefined_function_abi &
! riscv_fntype_abi_1 (const_tree fntype, bool check_only)
  {
    /* Implement the vector calling convention.  For more details please
       reference the below link.
       https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389  */
    bool validate_v_abi_p = false;
  
!   validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype, check_only);
!   validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype, check_only);
!   validate_v_abi_p |= riscv_vector_cc_function_p (fntype, check_only);
  
    if (validate_v_abi_p)
!     return riscv_v_abi (RISCV_CC_V);
! 
!   riscv_cc abi = riscv_vls_cc_function_abi (fntype, check_only);
!   if (abi != RISCV_CC_UNKNOWN)
!     return riscv_v_abi (abi);
  
    return default_function_abi;
  }
  
+ /* Implement TARGET_FNTYPE_ABI.  */
+ 
+ static const predefined_function_abi &
+ riscv_fntype_abi (const_tree fntype)
+ {
+   return riscv_fntype_abi_1 (fntype, /* check_only */true);
+ }
+ 
  /* Return riscv calling convention of call_insn.  */
  riscv_cc
  get_riscv_cc (const rtx use)
*************** riscv_handle_type_attribute (tree *node
*** 6922,6927 ****
--- 7258,7282 ----
  }
  
  static tree
+ riscv_handle_rvv_vls_cc_attribute (tree *, tree name, tree args,
+ 				   ATTRIBUTE_UNUSED int flags,
+ 				   bool *no_add_attrs)
+ {
+   bool vls_cc_p = is_attribute_p ("vls_cc", name)
+ 		  || is_attribute_p ("riscv_vls_cc", name);
+ 
+   if (!vls_cc_p)
+     return NULL_TREE;
+ 
+   riscv_cc cc = riscv_get_vls_cc_attr (args);
+ 
+   if (cc == RISCV_CC_UNKNOWN)
+     *no_add_attrs = true;
+ 
+   return NULL_TREE;
+ }
+ 
+ static tree
  riscv_handle_rvv_vector_bits_attribute (tree *node, tree name, tree args,
  					ATTRIBUTE_UNUSED int flags,
  					bool *no_add_attrs)
*************** riscv_issue_rate (void)
*** 10221,10226 ****
--- 10576,10646 ----
    return tune_param->issue_rate;
  }
  
+ /* Structure for very basic vector configuration tracking in the scheduler.  */
+ struct last_vconfig
+ {
+   bool valid;
+   bool ta;
+   bool ma;
+   uint8_t sew;
+   uint8_t vlmul;
+   rtx avl;
+ } last_vconfig;
+ 
+ /* Clear LAST_VCONFIG so we have no known state.  */
+ static void
+ clear_vconfig (void)
+ {
+   memset (&last_vconfig, 0, sizeof (last_vconfig));
+ }
+ 
+ /* Return TRUE if INSN is a vector insn needing a particular
+    vector configuration that is trivially equal to the last
+    vector insn issued.  Return FALSE otherwise.  */
+ static bool
+ compatible_with_last_vconfig (rtx_insn *insn)
+ {
+   /* We might be able to extract the data from a preexisting vsetvl.  */
+   if (vsetvl_insn_p (insn))
+     return false;
+ 
+   /* Nothing to do for these cases.  */
+   if (!NONDEBUG_INSN_P (insn) || !has_vtype_op (insn))
+     return false;
+ 
+   extract_insn_cached (insn);
+ 
+   rtx avl = get_avl (insn);
+   if (avl != last_vconfig.avl)
+     return false;
+ 
+   if (get_sew (insn) != last_vconfig.sew)
+     return false;
+ 
+   if (get_vlmul (insn) != last_vconfig.vlmul)
+     return false;
+ 
+   if (tail_agnostic_p (insn) != last_vconfig.ta)
+     return false;
+ 
+   if (mask_agnostic_p (insn) != last_vconfig.ma)
+     return false;
+ 
+   /* No differences found, they're trivially compatible.  */
+   return true;
+ }
+ 
+ /* Implement TARGET_SCHED_INIT, we use this to track the vector configuration
+    of the last issued vector instruction.  We can then use that information
+    to potentially adjust the ready queue to issue instructions of a compatible
+    vector configuration instead of a conflicting configuration.  That will
+    reduce the number of vsetvl instructions we ultimately emit.  */
+ static void
+ riscv_sched_init (FILE *, int, int)
+ {
+   clear_vconfig ();
+ }
+ 
  /* Implement TARGET_SCHED_VARIABLE_ISSUE.  */
  static int
  riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
*************** riscv_sched_variable_issue (FILE *, int,
*** 10245,10253 ****
--- 10665,10752 ----
       an assert so we can find and fix this problem.  */
    gcc_assert (insn_has_dfa_reservation_p (insn));
  
+   /* If this is a vector insn with vl/vtype info, then record the last
+      vector configuration.  */
+   if (vsetvl_insn_p (insn))
+     clear_vconfig ();
+   else if (NONDEBUG_INSN_P (insn) && has_vtype_op (insn))
+     {
+       extract_insn_cached (insn);
+ 
+       rtx avl = get_avl (insn);
+       if (avl == RVV_VLMAX)
+        avl = const0_rtx;
+ 
+       if (!avl || !CONST_INT_P (avl))
+        clear_vconfig ();
+       else
+ 	{
+ 	  last_vconfig.valid = true;
+ 	  last_vconfig.avl = avl;
+ 	  last_vconfig.sew = get_sew (insn);
+ 	  last_vconfig.vlmul = get_vlmul (insn);
+ 	  last_vconfig.ta = tail_agnostic_p (insn);
+ 	  last_vconfig.ma = mask_agnostic_p (insn);
+ 	}
+     }
+ 
    return more - 1;
  }
  
+ /* Implement TARGET_SCHED_REORDER.  The goal here is to look at the ready
+    queue and reorder it ever so slightly to encourage issing an insn with
+    the same vector configuration as the most recently issued vector
+    instruction.  That will reduce vsetvl instructions.  */
+ static int
+ riscv_sched_reorder (FILE *, int, rtx_insn **ready, int *nreadyp, int)
+ {
+   /* If we don't have a valid prior vector configuration, then there is
+      no point in reordering the ready queue, similarly if there is
+      just one entry in the queue.  */
+   if (!last_vconfig.valid || *nreadyp == 1)
+     return riscv_issue_rate ();
+ 
+   return riscv_issue_rate ();
+   int nready = *nreadyp;
+   int priority = INSN_PRIORITY (ready[nready - 1]);
+   for (int i = nready - 1; i >= 0; i--)
+     {
+       rtx_insn *insn = ready[i];
+ 
+       /* On a high performance core, vsetvl instructions should be
+ 	 inexpensive.  Removing them is very much a secondary concern, so
+ 	 be extremely conservative with reordering, essentially only
+ 	 allowing reordering within the highest priority value.
+ 
+ 	 Lower end cores may benefit from more flexibility here.  That
+ 	 tuning is left to those who understand their core's behavior
+ 	 and can thoroughly benchmark the result.  Assuming such
+ 	 designs appear, we can probably put an entry in the tuning
+ 	 structure to indicate how much difference in priority to allow.  */
+       if (INSN_PRIORITY (insn) < priority)
+ 	break;
+ 
+       if (compatible_with_last_vconfig (insn))
+ 	{
+ 	  /* This entry is compatible with the last vconfig and has
+ 	     the same priority as the most important insn.  So swap
+ 	     it so that we keep the vector configuration as-is and
+ 	     ultimately eliminate a vsetvl.
+ 
+ 	     Note no need to swap if this is the first entry in the
+ 	     queue.  */
+ 	  if (i == nready - 1)
+ 	    break;
+ 
+ 	  std::swap (ready[i], ready[nready - 1]);
+ 	  break;
+ 	}
+     }
+ 
+   return riscv_issue_rate ();
+ }
+ 
+ 
  /* Implement TARGET_SCHED_MACRO_FUSION_P.  Return true if target supports
     instruction fusion of some sort.  */
  
*************** riscv_asm_output_variant_cc (FILE *strea
*** 11088,11094 ****
    if (TREE_CODE (decl) == FUNCTION_DECL)
      {
        riscv_cc cc = (riscv_cc) fndecl_abi (decl).id ();
!       if (cc == RISCV_CC_V)
  	{
  	  fprintf (stream, "\t.variant_cc\t");
  	  assemble_name (stream, name);
--- 11587,11593 ----
    if (TREE_CODE (decl) == FUNCTION_DECL)
      {
        riscv_cc cc = (riscv_cc) fndecl_abi (decl).id ();
!       if (cc == RISCV_CC_V || riscv_vls_cc_p (cc))
  	{
  	  fprintf (stream, "\t.variant_cc\t");
  	  assemble_name (stream, name);
*************** riscv_prefetch_offset_address_p (rtx x,
*** 15656,15664 ****
--- 16155,16169 ----
  #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
  #define TARGET_SCHED_MACRO_FUSION_PAIR_P riscv_macro_fusion_pair_p
  
+ #undef TARGET_SCHED_INIT
+ #define TARGET_SCHED_INIT riscv_sched_init
+ 
  #undef  TARGET_SCHED_VARIABLE_ISSUE
  #define TARGET_SCHED_VARIABLE_ISSUE riscv_sched_variable_issue
  
+ #undef  TARGET_SCHED_REORDER
+ #define TARGET_SCHED_REORDER riscv_sched_reorder
+ 
  #undef  TARGET_SCHED_ADJUST_COST
  #define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost
  
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/riscv.h gcc-16-20251102/gcc/config/riscv/riscv.h
*** gcc-16-20251026/gcc/config/riscv/riscv.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/riscv.h	Sun Nov  2 22:32:20 2025
*************** enum riscv_cc
*** 779,784 ****
--- 779,795 ----
  {
    RISCV_CC_BASE = 0, /* Base standard RISC-V ABI.  */
    RISCV_CC_V, /* For functions that pass or return values in V registers.  */
+   /* For functions that pass or return values in V registers.  */
+   RISCV_CC_VLS_V_32,
+   RISCV_CC_VLS_V_64,
+   RISCV_CC_VLS_V_128,
+   RISCV_CC_VLS_V_256,
+   RISCV_CC_VLS_V_512,
+   RISCV_CC_VLS_V_1024,
+   RISCV_CC_VLS_V_2048,
+   RISCV_CC_VLS_V_4096,
+   RISCV_CC_VLS_V_8192,
+   RISCV_CC_VLS_V_16384,
    RISCV_CC_UNKNOWN
  };
  
*************** typedef struct {
*** 786,791 ****
--- 797,804 ----
    /* The calling convention that current function used.  */
    enum riscv_cc variant_cc;
  
+   unsigned int abi_vlen;
+ 
    /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
    unsigned int num_gprs;
  
*************** extern enum riscv_cc get_riscv_cc (const
*** 809,815 ****
  
  #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
    riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
! 			(N_NAMED_ARGS) != -1)
  
  #define EPILOGUE_USES(REGNO)	riscv_epilogue_uses (REGNO)
  
--- 822,828 ----
  
  #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
    riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
! 			(N_NAMED_ARGS) != -1, /* check_only */false)
  
  #define EPILOGUE_USES(REGNO)	riscv_epilogue_uses (REGNO)
  
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/thead.md gcc-16-20251102/gcc/config/riscv/thead.md
*** gcc-16-20251026/gcc/config/riscv/thead.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/thead.md	Sun Nov  2 22:32:20 2025
***************
*** 34,40 ****
  (define_insn "*th_srri<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=r")
  	(rotatert:GPR (match_operand:GPR 1 "register_operand" "r")
! 		     (match_operand 2 "const_int_operand" "n")))]
    "TARGET_XTHEADBB && (TARGET_64BIT || <MODE>mode == SImode)"
    {
      bool wform = TARGET_64BIT && (<MODE>mode == SImode);
--- 34,40 ----
  (define_insn "*th_srri<mode>3"
    [(set (match_operand:GPR 0 "register_operand" "=r")
  	(rotatert:GPR (match_operand:GPR 1 "register_operand" "r")
! 		      (match_operand 2 "const_int_operand" "n")))]
    "TARGET_XTHEADBB && (TARGET_64BIT || <MODE>mode == SImode)"
    {
      bool wform = TARGET_64BIT && (<MODE>mode == SImode);
***************
*** 45,50 ****
--- 45,66 ----
    [(set_attr "type" "bitmanip")
     (set_attr "mode" "<GPR:MODE>")])
  
+ ;; Version with explicit sign extension to facilitate sign extension
+ ;; removal.
+ (define_insn "*th_srrisi3_extended"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(sign_extend:DI
+ 	  (rotatert:SI (match_operand:SI 1 "register_operand" "r")
+ 		       (match_operand 2 "const_int_operand" "n"))))]
+   "TARGET_XTHEADBB && TARGET_64BIT"
+   {
+     operands[2] = GEN_INT (INTVAL (operands[2])
+ 			   & (GET_MODE_BITSIZE (SImode) - 1));
+     return "th.srriw\t%0,%1,%2";
+   }
+   [(set_attr "type" "bitmanip")
+    (set_attr "mode" "SI")])
+ 
  (define_insn "*th_ext<mode>4"
    [(set (match_operand:GPR 0 "register_operand" "=r")
  	(sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
diff -Nrcpad gcc-16-20251026/gcc/config/riscv/vector.md gcc-16-20251102/gcc/config/riscv/vector.md
*** gcc-16-20251026/gcc/config/riscv/vector.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/riscv/vector.md	Sun Nov  2 22:32:20 2025
***************
*** 1437,1442 ****
--- 1437,1444 ----
    [(set_attr "type" "vlde,vste,vmov")
     (set_attr "mode" "<MODE>")
     (set (attr "merge_op_idx") (const_int INVALID_ATTRIBUTE))
+    (set (attr "has_vl_op") (const_string "false"))
+    (set (attr "has_vtype_op") (const_string "false"))
     (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
     (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]
  )
diff -Nrcpad gcc-16-20251026/gcc/config/xtensa/xtensa.md gcc-16-20251102/gcc/config/xtensa/xtensa.md
*** gcc-16-20251026/gcc/config/xtensa/xtensa.md	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/config/xtensa/xtensa.md	Sun Nov  2 22:32:20 2025
***************
*** 43,48 ****
--- 43,49 ----
    UNSPEC_FRAME_BLOCKAGE
    UNSPEC_CEIL
    UNSPEC_FLOOR
+   UNSPEC_ROUND
  ])
  
  (define_c_enum "unspecv" [
***************
*** 104,111 ****
  
  ;; This iterator and attribute allow FP-to-integer rounding of two types
  ;; to be generated from one template.
! (define_int_iterator ANY_ROUND [UNSPEC_CEIL UNSPEC_FLOOR])
! (define_int_attr m_round [(UNSPEC_CEIL "ceil") (UNSPEC_FLOOR "floor")])
  
  
  ;; Attributes.
--- 105,115 ----
  
  ;; This iterator and attribute allow FP-to-integer rounding of two types
  ;; to be generated from one template.
! (define_int_iterator ANY_ROUND [UNSPEC_CEIL UNSPEC_FLOOR UNSPEC_ROUND])
! (define_int_attr m_round [(UNSPEC_CEIL "ceil") (UNSPEC_FLOOR "floor")
! 			  (UNSPEC_ROUND "round")])
! (define_int_attr c_round [(UNSPEC_CEIL "1") (UNSPEC_FLOOR "1")
! 			  (UNSPEC_ROUND "flag_unsafe_math_optimizations")])
  
  
  ;; Attributes.
***************
*** 680,714 ****
     (set_attr "mode"	"SI")
     (set_attr "length"	"3")])
  
! (define_insn_and_split "one_cmplsi2"
!   [(set (match_operand:SI 0 "register_operand" "=a")
! 	(not:SI (match_operand:SI 1 "register_operand" "r")))]
    ""
-   "#"
-   "&& can_create_pseudo_p ()"
-   [(set (match_dup 2)
- 	(const_int -1))
-    (set (match_dup 0)
- 	(xor:SI (match_dup 1)
- 		(match_dup 2)))]
  {
!   operands[2] = gen_reg_rtx (SImode);
! }
!   [(set_attr "type"	"arith")
!    (set_attr "mode"	"SI")
!    (set (attr "length")
! 	(if_then_else (match_test "TARGET_DENSITY")
! 		      (const_int 5)
! 		      (const_int 6)))])
  
  (define_insn "negsf2"
!   [(set (match_operand:SF 0 "register_operand" "=f")
! 	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
    "TARGET_HARD_FLOAT"
!   "neg.s\t%0, %1"
!   [(set_attr "type"	"farith")
!    (set_attr "mode"	"SF")
!    (set_attr "length"	"3")])
  
  
  ;; Logical instructions.
--- 684,709 ----
     (set_attr "mode"	"SI")
     (set_attr "length"	"3")])
  
! (define_expand "one_cmplsi2"
!   [(set (match_operand:SI 0 "register_operand")
! 	(not:SI (match_operand:SI 1 "register_operand")))]
    ""
  {
!   emit_insn (gen_xorsi3 (operands[0], operands[1],
! 			 force_reg (SImode, constm1_rtx)));
!   DONE;
! })
  
  (define_insn "negsf2"
!   [(set (match_operand:SF 0 "register_operand")
!         (neg:SF (match_operand:SF 1 "register_operand")))
!    (clobber (match_scratch:SI 2))]
    "TARGET_HARD_FLOAT"
!   {@ [cons: =0, 1, =2; attrs: type, length]
!      [D, D, &a; arith , 7] movi.n\t%2, 1\;slli\t%2, %2, 31\;add.n\t%0, %1, %2
!      [f, f,  X; farith, 3] neg.s\t%0, %1
!   }
!   [(set_attr "mode" "SF")])
  
  
  ;; Logical instructions.
***************
*** 1150,1156 ****
  (define_insn "*fix<s_fix>_truncsfsi2_scaled"
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(any_fix:SI (mult:SF (match_operand:SF 1 "register_operand" "f")
! 			     (match_operand:SF 2 "fix_scaling_operand" "F"))))]
    "TARGET_HARD_FLOAT"
    "<m_fix>.s\t%0, %1, %U2"
    [(set_attr "type"	"fconv")
--- 1145,1151 ----
  (define_insn "*fix<s_fix>_truncsfsi2_scaled"
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(any_fix:SI (mult:SF (match_operand:SF 1 "register_operand" "f")
! 			     (match_operand:SF 2 "fix_scaling_operand" ""))))]
    "TARGET_HARD_FLOAT"
    "<m_fix>.s\t%0, %1, %U2"
    [(set_attr "type"	"fconv")
***************
*** 1169,1175 ****
  (define_insn "*float<s_float>sisf2_scaled"
    [(set (match_operand:SF 0 "register_operand" "=f")
  	(mult:SF (any_float:SF (match_operand:SI 1 "register_operand" "a"))
! 		 (match_operand:SF 2 "float_scaling_operand" "F")))]
    "TARGET_HARD_FLOAT"
    "<m_float>.s\t%0, %1, %V2"
    [(set_attr "type"	"fconv")
--- 1164,1170 ----
  (define_insn "*float<s_float>sisf2_scaled"
    [(set (match_operand:SF 0 "register_operand" "=f")
  	(mult:SF (any_float:SF (match_operand:SI 1 "register_operand" "a"))
! 		 (match_operand:SF 2 "float_scaling_operand" "")))]
    "TARGET_HARD_FLOAT"
    "<m_float>.s\t%0, %1, %V2"
    [(set_attr "type"	"fconv")
***************
*** 1179,1185 ****
  (define_insn "l<m_round>sfsi2"
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(unspec:SI [(match_operand:SF 1 "register_operand" "f")] ANY_ROUND))]
!   "TARGET_HARD_FLOAT"
    "<m_round>.s\t%0, %1, 0"
    [(set_attr "type"	"fconv")
     (set_attr "mode"	"SF")
--- 1174,1180 ----
  (define_insn "l<m_round>sfsi2"
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(unspec:SI [(match_operand:SF 1 "register_operand" "f")] ANY_ROUND))]
!   "TARGET_HARD_FLOAT && <c_round>"
    "<m_round>.s\t%0, %1, 0"
    [(set_attr "type"	"fconv")
     (set_attr "mode"	"SF")
***************
*** 1189,1195 ****
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(unspec:SI [(plus:SF (match_operand:SF 1 "register_operand" "f")
  			     (match_dup 1))] ANY_ROUND))]
!   "TARGET_HARD_FLOAT"
    "<m_round>.s\t%0, %1, 1"
    [(set_attr "type"	"fconv")
     (set_attr "mode"	"SF")
--- 1184,1190 ----
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(unspec:SI [(plus:SF (match_operand:SF 1 "register_operand" "f")
  			     (match_dup 1))] ANY_ROUND))]
!   "TARGET_HARD_FLOAT && <c_round>"
    "<m_round>.s\t%0, %1, 1"
    [(set_attr "type"	"fconv")
     (set_attr "mode"	"SF")
***************
*** 1198,1205 ****
  (define_insn "*l<m_round>sfsi2_scaled"
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(unspec:SI [(mult:SF (match_operand:SF 1 "register_operand" "f")
! 			     (match_operand:SF 2 "fix_scaling_operand" "F"))] ANY_ROUND))]
!   "TARGET_HARD_FLOAT"
    "<m_round>.s\t%0, %1, %U2"
    [(set_attr "type"	"fconv")
     (set_attr "mode"	"SF")
--- 1193,1200 ----
  (define_insn "*l<m_round>sfsi2_scaled"
    [(set (match_operand:SI 0 "register_operand" "=a")
  	(unspec:SI [(mult:SF (match_operand:SF 1 "register_operand" "f")
! 			     (match_operand:SF 2 "fix_scaling_operand" ""))] ANY_ROUND))]
!   "TARGET_HARD_FLOAT && <c_round>"
    "<m_round>.s\t%0, %1, %U2"
    [(set_attr "type"	"fconv")
     (set_attr "mode"	"SF")
diff -Nrcpad gcc-16-20251026/gcc/coretypes.h gcc-16-20251102/gcc/coretypes.h
*** gcc-16-20251026/gcc/coretypes.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/coretypes.h	Sun Nov  2 22:32:20 2025
*************** using dw_cfi_ref = struct dw_cfi_node *;
*** 147,158 ****
  enum dw_cfi_oprnd_type: int;
  enum dwarf_call_frame_info: int;
  
! /* Subclasses of symtab_node, using indentation to show the class
     hierarchy.  */
  
! struct symtab_node;
!   struct cgraph_node;
!   struct varpool_node;
  struct cgraph_edge;
  
  union section;
--- 147,160 ----
  enum dw_cfi_oprnd_type: int;
  enum dwarf_call_frame_info: int;
  
! /* Subclasses of toplevel_node, using indentation to show the class
     hierarchy.  */
  
! struct toplevel_node;
!   struct asm_node;
!   struct symtab_node;
!     struct cgraph_node;
!     struct varpool_node;
  struct cgraph_edge;
  
  union section;
diff -Nrcpad gcc-16-20251026/gcc/cp/ChangeLog gcc-16-20251102/gcc/cp/ChangeLog
*** gcc-16-20251026/gcc/cp/ChangeLog	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cp/ChangeLog	Sun Nov  2 22:32:20 2025
***************
*** 1,3 ****
--- 1,42 ----
+ 2025-11-01  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122381
+ 	* module.cc (trees_out::core_vals): Write BASELINK_OPTYPE (aka
+ 	TREE_CHAIN).
+ 	(trees_in::core_vals): Read it.
+ 
+ 2025-10-30  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	* std-name-hint.gperf: Remove duplicate entries for ispanstream
+ 	and istringstream.
+ 	* std-name-hint.h: Regenerate.
+ 
+ 2025-10-28  Marek Polacek  <polacek@redhat.com>
+ 	    Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	* decl.cc (finish_enum_value_list): Use fold_convert instead of
+ 	copy_node.
+ 
+ 2025-10-27  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122422
+ 	* decl.cc (maybe_deduce_size_from_array_init): Propagate type to
+ 	corresponding TEMPLATE_DECL.
+ 
+ 2025-10-27  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122310
+ 	* module.cc (get_keyed_decl_scope): New function.
+ 	(trees_out::get_merge_kind): Use it.
+ 	(trees_out::key_mergeable): Use it.
+ 	(maybe_key_decl): Key to the containing type for all members.
+ 
+ 2025-10-27  Paul-Antoine Arras  <parras@baylibre.com>
+ 
+ 	PR c++/122378
+ 	* parser.cc (cp_parser_label_declaration): Mangle label declaration in a
+ 	metadirective region.
+ 
  2025-10-21  Jakub Jelinek  <jakub@redhat.com>
  
  	* cp-tree.h: Implement C++23 P2674R1 - A trait for implicit lifetime
diff -Nrcpad gcc-16-20251026/gcc/cp/decl.cc gcc-16-20251102/gcc/cp/decl.cc
*** gcc-16-20251026/gcc/cp/decl.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cp/decl.cc	Sun Nov  2 22:32:20 2025
*************** maybe_deduce_size_from_array_init (tree
*** 7096,7101 ****
--- 7096,7109 ----
        cp_apply_type_quals_to_decl (cp_type_quals (TREE_TYPE (decl)), decl);
  
        relayout_decl (decl);
+ 
+       /* Update the type of the corresponding TEMPLATE_DECL to match.  */
+       if (DECL_LANG_SPECIFIC (decl) && DECL_TEMPLATE_INFO (decl))
+ 	{
+ 	  tree tmpl = template_for_substitution (decl);
+ 	  if (DECL_TEMPLATE_RESULT (tmpl) == decl)
+ 	    TREE_TYPE (tmpl) = TREE_TYPE (decl);
+ 	}
      }
  }
  
*************** finish_enum_value_list (tree enumtype)
*** 18950,18962 ****
          value = perform_implicit_conversion (underlying_type,
                                               DECL_INITIAL (decl),
                                               tf_warning_or_error);
!       /* Do not clobber shared ints.  */
!       if (value != error_mark_node)
! 	{
! 	  value = copy_node (value);
  
- 	  TREE_TYPE (value) = enumtype;
- 	}
        DECL_INITIAL (decl) = value;
        if (export_p)
  	DECL_MODULE_EXPORT_P (decl) = true;
--- 18958,18966 ----
          value = perform_implicit_conversion (underlying_type,
                                               DECL_INITIAL (decl),
                                               tf_warning_or_error);
!       /* Do not clobber shared ints.  But do share identical enumerators.  */
!       value = fold_convert (enumtype, value);
  
        DECL_INITIAL (decl) = value;
        if (export_p)
  	DECL_MODULE_EXPORT_P (decl) = true;
diff -Nrcpad gcc-16-20251026/gcc/cp/module.cc gcc-16-20251102/gcc/cp/module.cc
*** gcc-16-20251026/gcc/cp/module.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cp/module.cc	Sun Nov  2 22:32:20 2025
*************** vec<tree, va_heap, vl_embed> *post_load_
*** 2798,2803 ****
--- 2798,2805 ----
  typedef hash_map<tree, auto_vec<tree>> keyed_map_t;
  static keyed_map_t *keyed_table;
  
+ static tree get_keyed_decl_scope (tree);
+ 
  /* Instantiations of temploid friends imported from another module
     need to be attached to the same module as the temploid.  This maps
     these decls to the temploid they are instantiated from, as there is
*************** trees_out::core_vals (tree t)
*** 6731,6736 ****
--- 6733,6739 ----
        WT (((lang_tree_node *)t)->baselink.binfo);
        WT (((lang_tree_node *)t)->baselink.functions);
        WT (((lang_tree_node *)t)->baselink.access_binfo);
+       WT (((lang_tree_node *)t)->baselink.common.chain);
        break;
  
      case CONSTRAINT_INFO:
*************** trees_in::core_vals (tree t)
*** 7300,7305 ****
--- 7303,7309 ----
        RT (((lang_tree_node *)t)->baselink.binfo);
        RTU (((lang_tree_node *)t)->baselink.functions);
        RT (((lang_tree_node *)t)->baselink.access_binfo);
+       RT (((lang_tree_node *)t)->baselink.common.chain);
        break;
  
      case CONSTRAINT_INFO:
*************** trees_out::get_merge_kind (tree decl, de
*** 11464,11483 ****
  	    if (DECL_IMPLICIT_TYPEDEF_P (STRIP_TEMPLATE (decl))
  		&& LAMBDA_TYPE_P (TREE_TYPE (decl)))
  	      {
! 		if (tree scope = LAMBDA_TYPE_EXTRA_SCOPE (TREE_TYPE (decl)))
! 		  {
! 		    /* Lambdas attached to fields are keyed to its class.  */
! 		    if (TREE_CODE (scope) == FIELD_DECL)
! 		      scope = TYPE_NAME (DECL_CONTEXT (scope));
! 		    if (DECL_LANG_SPECIFIC (scope)
! 			&& DECL_MODULE_KEYED_DECLS_P (scope))
! 		      {
! 			mk = MK_keyed;
! 			break;
! 		      }
! 		  }
! 		/* Lambdas not attached to any mangling scope are TU-local.  */
! 		mk = MK_unique;
  		break;
  	      }
  
--- 11468,11479 ----
  	    if (DECL_IMPLICIT_TYPEDEF_P (STRIP_TEMPLATE (decl))
  		&& LAMBDA_TYPE_P (TREE_TYPE (decl)))
  	      {
! 		if (get_keyed_decl_scope (decl))
! 		  mk = MK_keyed;
! 		else
! 		  /* Lambdas not attached to any mangling scope are TU-local
! 		     and so cannot be deduplicated.  */
! 		  mk = MK_unique;
  		break;
  	      }
  
*************** trees_out::key_mergeable (int tag, merge
*** 11778,11793 ****
  
  	case MK_keyed:
  	  {
! 	    gcc_checking_assert (LAMBDA_TYPE_P (TREE_TYPE (inner)));
! 	    tree scope = LAMBDA_TYPE_EXTRA_SCOPE (TREE_TYPE (inner));
! 	    gcc_checking_assert (TREE_CODE (scope) == VAR_DECL
! 				 || TREE_CODE (scope) == FIELD_DECL
! 				 || TREE_CODE (scope) == PARM_DECL
! 				 || TREE_CODE (scope) == TYPE_DECL
! 				 || TREE_CODE (scope) == CONCEPT_DECL);
! 	    /* Lambdas attached to fields are keyed to the class.  */
! 	    if (TREE_CODE (scope) == FIELD_DECL)
! 	      scope = TYPE_NAME (DECL_CONTEXT (scope));
  	    auto *root = keyed_table->get (scope);
  	    unsigned ix = root->length ();
  	    /* If we don't find it, we'll write a really big number
--- 11774,11782 ----
  
  	case MK_keyed:
  	  {
! 	    tree scope = get_keyed_decl_scope (inner);
! 	    gcc_checking_assert (scope);
! 
  	    auto *root = keyed_table->get (scope);
  	    unsigned ix = root->length ();
  	    /* If we don't find it, we'll write a really big number
*************** trees_in::read_var_def (tree decl, tree
*** 13059,13070 ****
  	  if (DECL_EXPLICIT_INSTANTIATION (decl)
  	      && !DECL_EXTERNAL (decl))
  	    setup_explicit_instantiation_definition_linkage (decl);
! 	  if (DECL_IMPLICIT_INSTANTIATION (decl)
! 	      || (DECL_EXPLICIT_INSTANTIATION (decl)
! 		  && !DECL_EXTERNAL (decl))
! 	      || (DECL_CLASS_SCOPE_P (decl)
! 		  && !DECL_VTABLE_OR_VTT_P (decl)
! 		  && !DECL_TEMPLATE_INFO (decl)))
  	    note_vague_linkage_variable (decl);
  	}
        if (!dyn_init)
--- 13048,13058 ----
  	  if (DECL_EXPLICIT_INSTANTIATION (decl)
  	      && !DECL_EXTERNAL (decl))
  	    setup_explicit_instantiation_definition_linkage (decl);
! 	  /* Class static data members are handled in read_class_def.  */
! 	  if (!DECL_CLASS_SCOPE_P (decl)
! 	      && (DECL_IMPLICIT_INSTANTIATION (decl)
! 		  || (DECL_EXPLICIT_INSTANTIATION (decl)
! 		      && !DECL_EXTERNAL (decl))))
  	    note_vague_linkage_variable (decl);
  	}
        if (!dyn_init)
*************** trees_in::read_class_def (tree defn, tre
*** 13478,13483 ****
--- 13466,13475 ----
  			DECL_ACCESS (d) = tree_cons (type, access, list);
  		    }
  		}
+ 
+ 	      if (TREE_CODE (decl) == VAR_DECL
+ 		  && TREE_CODE (maybe_template) != TEMPLATE_DECL)
+ 		note_vague_linkage_variable (decl);
  	    }
  	}
  
*************** maybe_key_decl (tree ctx, tree decl)
*** 21511,21519 ****
        && TREE_CODE (ctx) != CONCEPT_DECL)
      return;
  
!   /* For fields, key it to the containing type to handle deduplication
!      correctly.  */
!   if (TREE_CODE (ctx) == FIELD_DECL)
      ctx = TYPE_NAME (DECL_CONTEXT (ctx));
  
    if (!keyed_table)
--- 21503,21523 ----
        && TREE_CODE (ctx) != CONCEPT_DECL)
      return;
  
!   /* For members, key it to the containing type to handle deduplication
!      correctly.  For fields, this is necessary as FIELD_DECLs have no
!      dep and so would only be streamed after the lambda type, defeating
!      our ability to merge them.
! 
!      Other class-scope key decls might depend on the type of the lambda
!      but be within the same cluster; we need to ensure that we never
!      first see the key decl while streaming the lambda type as merging
!      would then fail when comparing the partially-streamed lambda type
!      of the key decl with the existing (PR c++/122310).
! 
!      Perhaps sort_cluster can be adjusted to handle this better, but
!      this is a simple workaround (and might down on the number of
!      entries in keyed_table as a bonus).  */
!   while (DECL_CLASS_SCOPE_P (ctx))
      ctx = TYPE_NAME (DECL_CONTEXT (ctx));
  
    if (!keyed_table)
*************** maybe_key_decl (tree ctx, tree decl)
*** 21528,21533 ****
--- 21532,21561 ----
    vec.safe_push (decl);
  }
  
+ /* Find the scope that the lambda DECL is keyed to, if any.  */
+ 
+ static tree
+ get_keyed_decl_scope (tree decl)
+ {
+   gcc_checking_assert (LAMBDA_TYPE_P (TREE_TYPE (decl)));
+   tree scope = LAMBDA_TYPE_EXTRA_SCOPE (TREE_TYPE (decl));
+   if (!scope)
+     return NULL_TREE;
+ 
+   gcc_checking_assert (TREE_CODE (scope) == VAR_DECL
+ 		       || TREE_CODE (scope) == FIELD_DECL
+ 		       || TREE_CODE (scope) == PARM_DECL
+ 		       || TREE_CODE (scope) == TYPE_DECL
+ 		       || TREE_CODE (scope) == CONCEPT_DECL);
+ 
+   while (DECL_CLASS_SCOPE_P (scope))
+     scope = TYPE_NAME (DECL_CONTEXT (scope));
+ 
+   gcc_checking_assert (DECL_LANG_SPECIFIC (scope)
+ 		       && DECL_MODULE_KEYED_DECLS_P (scope));
+   return scope;
+ }
+ 
  /* DECL is an instantiated friend that should be attached to the same
     module that ORIG is.  */
  
diff -Nrcpad gcc-16-20251026/gcc/cp/parser.cc gcc-16-20251102/gcc/cp/parser.cc
*** gcc-16-20251026/gcc/cp/parser.cc	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cp/parser.cc	Sun Nov  2 22:32:20 2025
*************** cp_parser_label_declaration (cp_parser*
*** 32724,32729 ****
--- 32724,32731 ----
        /* If we failed, stop.  */
        if (identifier == error_mark_node)
  	break;
+       if (parser->omp_metadirective_state)
+ 	identifier = mangle_metadirective_region_label (parser, identifier);
        /* Declare it as a label.  */
        finish_label_decl (identifier);
        /* If the next token is a `;', stop.  */
diff -Nrcpad gcc-16-20251026/gcc/cp/std-name-hint.gperf gcc-16-20251102/gcc/cp/std-name-hint.gperf
*** gcc-16-20251026/gcc/cp/std-name-hint.gperf	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cp/std-name-hint.gperf	Sun Nov  2 22:32:20 2025
*************** basic_ospanstream, "<spanstream>", cxx23
*** 420,426 ****
  basic_spanbuf, "<spanstream>", cxx23
  basic_spanstream, "<spanstream>", cxx23
  ispanstream, "<spanstream>", cxx23
- ispanstream, "<spanstream>", cxx23
  ospanstream, "<spanstream>", cxx23
  spanbuf, "<spanstream>", cxx23
  spanstream, "<spanstream>", cxx23
--- 420,425 ----
*************** basic_ostringstream, "<sstream>", cxx98
*** 433,439 ****
  basic_stringbuf, "<sstream>", cxx98
  basic_stringstream, "<sstream>", cxx98
  istringstream, "<sstream>", cxx98
- istringstream, "<sstream>", cxx98
  ostringstream, "<sstream>", cxx98
  stringbuf, "<sstream>", cxx98
  stringstream, "<sstream>", cxx98
--- 432,437 ----
diff -Nrcpad gcc-16-20251026/gcc/cp/std-name-hint.h gcc-16-20251102/gcc/cp/std-name-hint.h
*** gcc-16-20251026/gcc/cp/std-name-hint.h	Sun Oct 26 22:32:32 2025
--- gcc-16-20251102/gcc/cp/std-name-hint.h	Sun Nov  2 22:32:20 2025
*************** struct std_name_hint
*** 61,67 ****
    /* The dialect of C++ in which this was added.  */
    enum cxx_dialect min_dialect;
  };
! /* maximum key range = 2080, duplicates = 7 */
  
  class std_name_hint_lookup
  {
--- 61,67 ----
    /* The dialect of C++ in which this was added.  */
    enum cxx_dialect min_dialect;
  };
! /* maximum key range = 2080, duplicates = 5 */
  
  class std_name_hint_lookup
  {
*************** std_name_hint_lookup::find (const char *
*** 135,141 ****
  {
    enum
      {
!       TOTAL_KEYWORDS = 488,
        MIN_WORD_LENGTH = 2,
        MAX_WORD_LENGTH = 39,
        MIN_HASH_VALUE = 7,
--- 135,141 ----
  {
    enum
      {
!       TOTAL_KEYWORDS = 486,
        MIN_WORD_LENGTH = 2,
        MAX_WORD_LENGTH = 39,
        MIN_HASH_VALUE = 7,
*************** std_name_hint_lookup::find (const char *
*** 148,154 ****
        {"regular", "<concepts>", cxx20},
  #line 292 "std-name-hint.gperf"
        {"reverse_iterator", "<iterator>", cxx98},
! #line 454 "std-name-hint.gperf"
        {"range_error", "<stdexcept>", cxx98},
  #line 408 "std-name-hint.gperf"
        {"set", "<set>", cxx98},
--- 148,154 ----
        {"regular", "<concepts>", cxx20},
  #line 292 "std-name-hint.gperf"
        {"reverse_iterator", "<iterator>", cxx98},
! #line 452 "std-name-hint.gperf"
        {"range_error", "<stdexcept>", cxx98},
  #line 408 "std-name-hint.gperf"
        {"set", "<set>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 164,176 ****
        {"formatter", "<format>", cxx20},
  #line 196 "std-name-hint.gperf"
        {"basic_filebuf", "<fstream>", cxx98},
! #line 575 "std-name-hint.gperf"
        {"pair", "<utility>", cxx98},
  #line 276 "std-name-hint.gperf"
        {"begin", "<iterator>", cxx11},
  #line 179 "std-name-hint.gperf"
        {"formattable", "<format>", cxx23},
! #line 541 "std-name-hint.gperf"
        {"bad_cast", "<typeinfo>", cxx98},
  #line 233 "std-name-hint.gperf"
        {"setiosflags", "<iomanip>", cxx98},
--- 164,176 ----
        {"formatter", "<format>", cxx20},
  #line 196 "std-name-hint.gperf"
        {"basic_filebuf", "<fstream>", cxx98},
! #line 573 "std-name-hint.gperf"
        {"pair", "<utility>", cxx98},
  #line 276 "std-name-hint.gperf"
        {"begin", "<iterator>", cxx11},
  #line 179 "std-name-hint.gperf"
        {"formattable", "<format>", cxx23},
! #line 539 "std-name-hint.gperf"
        {"bad_cast", "<typeinfo>", cxx98},
  #line 233 "std-name-hint.gperf"
        {"setiosflags", "<iomanip>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 178,184 ****
        {"print", "<print>", cxx23},
  #line 221 "std-name-hint.gperf"
        {"promise", "<future>", cxx11},
! #line 582 "std-name-hint.gperf"
        {"bad_variant_access", "<variant>", cxx17},
  #line 328 "std-name-hint.gperf"
        {"to_address", "<memory>", cxx20},
--- 178,184 ----
        {"print", "<print>", cxx23},
  #line 221 "std-name-hint.gperf"
        {"promise", "<future>", cxx11},
! #line 580 "std-name-hint.gperf"
        {"bad_variant_access", "<variant>", cxx17},
  #line 328 "std-name-hint.gperf"
        {"to_address", "<memory>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 196,204 ****
        {"nouppercase", "<ios>", cxx98},
  #line 250 "std-name-hint.gperf"
        {"nounitbuf", "<ios>", cxx98},
! #line 433 "std-name-hint.gperf"
        {"basic_stringbuf", "<sstream>", cxx98},
! #line 593 "std-name-hint.gperf"
        {"vector", "<vector>", cxx98},
  #line 246 "std-name-hint.gperf"
        {"noshowbase", "<ios>", cxx98},
--- 196,204 ----
        {"nouppercase", "<ios>", cxx98},
  #line 250 "std-name-hint.gperf"
        {"nounitbuf", "<ios>", cxx98},
! #line 432 "std-name-hint.gperf"
        {"basic_stringbuf", "<sstream>", cxx98},
! #line 591 "std-name-hint.gperf"
        {"vector", "<vector>", cxx98},
  #line 246 "std-name-hint.gperf"
        {"noshowbase", "<ios>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 210,218 ****
        {"pmr::get_default_resource", "<memory_resource>", cxx17},
  #line 343 "std-name-hint.gperf"
        {"pmr::set_default_resource", "<memory_resource>", cxx17},
! #line 455 "std-name-hint.gperf"
        {"runtime_error", "<stdexcept>", cxx98},
! #line 516 "std-name-hint.gperf"
        {"tuple", "<tuple>", cxx11},
  #line 132 "std-name-hint.gperf"
        {"regular_invocable", "<concepts>", cxx20},
--- 210,218 ----
        {"pmr::get_default_resource", "<memory_resource>", cxx17},
  #line 343 "std-name-hint.gperf"
        {"pmr::set_default_resource", "<memory_resource>", cxx17},
! #line 453 "std-name-hint.gperf"
        {"runtime_error", "<stdexcept>", cxx98},
! #line 514 "std-name-hint.gperf"
        {"tuple", "<tuple>", cxx11},
  #line 132 "std-name-hint.gperf"
        {"regular_invocable", "<concepts>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 224,238 ****
        {"not_fn", "<functional>", cxx17},
  #line 142 "std-name-hint.gperf"
        {"byte", "<cstddef>", cxx17},
! #line 518 "std-name-hint.gperf"
        {"tuple_element", "<tuple>", cxx11},
! #line 519 "std-name-hint.gperf"
        {"tuple_element_t", "<tuple>", cxx14},
! #line 585 "std-name-hint.gperf"
        {"variant", "<variant>", cxx17},
  #line 386 "std-name-hint.gperf"
        {"ends", "<ostream>", cxx98},
! #line 520 "std-name-hint.gperf"
        {"tuple_size", "<tuple>", cxx11},
  #line 123 "std-name-hint.gperf"
        {"equality_comparable", "<concepts>", cxx20},
--- 224,238 ----
        {"not_fn", "<functional>", cxx17},
  #line 142 "std-name-hint.gperf"
        {"byte", "<cstddef>", cxx17},
! #line 516 "std-name-hint.gperf"
        {"tuple_element", "<tuple>", cxx11},
! #line 517 "std-name-hint.gperf"
        {"tuple_element_t", "<tuple>", cxx14},
! #line 583 "std-name-hint.gperf"
        {"variant", "<variant>", cxx17},
  #line 386 "std-name-hint.gperf"
        {"ends", "<ostream>", cxx98},
! #line 518 "std-name-hint.gperf"
        {"tuple_size", "<tuple>", cxx11},
  #line 123 "std-name-hint.gperf"
        {"equality_comparable", "<concepts>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 244,280 ****
        {"noshowpos", "<ios>", cxx98},
  #line 388 "std-name-hint.gperf"
        {"flush_emit", "<ostream>", cxx20},
! #line 586 "std-name-hint.gperf"
        {"variant_alternative", "<variant>", cxx17},
! #line 537 "std-name-hint.gperf"
        {"void_t", "<type_traits>", cxx17},
! #line 587 "std-name-hint.gperf"
        {"variant_alternative_t", "<variant>", cxx17},
  #line 134 "std-name-hint.gperf"
        {"relation", "<concepts>", cxx20},
- #line 461 "std-name-hint.gperf"
-       {"float32_t", "<stdfloat>", cxx23},
  #line 459 "std-name-hint.gperf"
        {"float128_t", "<stdfloat>", cxx23},
  #line 381 "std-name-hint.gperf"
        {"nullopt", "<optional>", cxx17},
  #line 291 "std-name-hint.gperf"
        {"prev", "<iterator>", cxx11},
! #line 425 "std-name-hint.gperf"
        {"spanbuf", "<spanstream>", cxx23},
! #line 513 "std-name-hint.gperf"
        {"make_from_tuple", "<tuple>", cxx17},
  #line 253 "std-name-hint.gperf"
        {"right", "<ios>", cxx98},
  #line 210 "std-name-hint.gperf"
        {"mem_fn", "<functional>", cxx11},
! #line 515 "std-name-hint.gperf"
        {"tie", "<tuple>", cxx11},
  #line 197 "std-name-hint.gperf"
        {"basic_fstream", "<fstream>", cxx98},
! #line 573 "std-name-hint.gperf"
        {"move", "<utility>", cxx11},
! #line 462 "std-name-hint.gperf"
        {"float64_t", "<stdfloat>", cxx23},
  #line 127 "std-name-hint.gperf"
        {"movable", "<concepts>", cxx20},
--- 244,280 ----
        {"noshowpos", "<ios>", cxx98},
  #line 388 "std-name-hint.gperf"
        {"flush_emit", "<ostream>", cxx20},
! #line 584 "std-name-hint.gperf"
        {"variant_alternative", "<variant>", cxx17},
! #line 535 "std-name-hint.gperf"
        {"void_t", "<type_traits>", cxx17},
! #line 585 "std-name-hint.gperf"
        {"variant_alternative_t", "<variant>", cxx17},
  #line 134 "std-name-hint.gperf"
        {"relation", "<concepts>", cxx20},
  #line 459 "std-name-hint.gperf"
+       {"float32_t", "<stdfloat>", cxx23},
+ #line 457 "std-name-hint.gperf"
        {"float128_t", "<stdfloat>", cxx23},
  #line 381 "std-name-hint.gperf"
        {"nullopt", "<optional>", cxx17},
  #line 291 "std-name-hint.gperf"
        {"prev", "<iterator>", cxx11},
! #line 424 "std-name-hint.gperf"
        {"spanbuf", "<spanstream>", cxx23},
! #line 511 "std-name-hint.gperf"
        {"make_from_tuple", "<tuple>", cxx17},
  #line 253 "std-name-hint.gperf"
        {"right", "<ios>", cxx98},
  #line 210 "std-name-hint.gperf"
        {"mem_fn", "<functional>", cxx11},
! #line 513 "std-name-hint.gperf"
        {"tie", "<tuple>", cxx11},
  #line 197 "std-name-hint.gperf"
        {"basic_fstream", "<fstream>", cxx98},
! #line 571 "std-name-hint.gperf"
        {"move", "<utility>", cxx11},
! #line 460 "std-name-hint.gperf"
        {"float64_t", "<stdfloat>", cxx23},
  #line 127 "std-name-hint.gperf"
        {"movable", "<concepts>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 282,294 ****
        {"front_inserter", "<iterator>", cxx98},
  #line 296 "std-name-hint.gperf"
        {"map", "<map>", cxx98},
! #line 460 "std-name-hint.gperf"
        {"float16_t", "<stdfloat>", cxx23},
  #line 56 "std-name-hint.gperf"
        {"bitset", "<bitset>", cxx11},
  #line 205 "std-name-hint.gperf"
        {"bind_front", "<functional>", cxx20},
! #line 574 "std-name-hint.gperf"
        {"move_if_noexcept", "<utility>", cxx11},
  #line 274 "std-name-hint.gperf"
        {"advance", "<iterator>", cxx98},
--- 282,294 ----
        {"front_inserter", "<iterator>", cxx98},
  #line 296 "std-name-hint.gperf"
        {"map", "<map>", cxx98},
! #line 458 "std-name-hint.gperf"
        {"float16_t", "<stdfloat>", cxx23},
  #line 56 "std-name-hint.gperf"
        {"bitset", "<bitset>", cxx11},
  #line 205 "std-name-hint.gperf"
        {"bind_front", "<functional>", cxx20},
! #line 572 "std-name-hint.gperf"
        {"move_if_noexcept", "<utility>", cxx11},
  #line 274 "std-name-hint.gperf"
        {"advance", "<iterator>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 296,302 ****
        {"move_iterator", "<iterator>", cxx11},
  #line 161 "std-name-hint.gperf"
        {"terminate", "<exception>", cxx98},
! #line 531 "std-name-hint.gperf"
        {"negation", "<type_traits>", cxx17},
  #line 318 "std-name-hint.gperf"
        {"make_obj_using_allocator", "<memory>", cxx20},
--- 296,302 ----
        {"move_iterator", "<iterator>", cxx11},
  #line 161 "std-name-hint.gperf"
        {"terminate", "<exception>", cxx98},
! #line 529 "std-name-hint.gperf"
        {"negation", "<type_traits>", cxx17},
  #line 318 "std-name-hint.gperf"
        {"make_obj_using_allocator", "<memory>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 310,316 ****
        {"range_formatter", "<format>", cxx23},
  #line 299 "std-name-hint.gperf"
        {"addressof", "<memory>", cxx11},
! #line 571 "std-name-hint.gperf"
        {"make_integer_sequence", "<utility>", cxx14},
  #line 184 "std-name-hint.gperf"
        {"range_format", "<format>", cxx23},
--- 310,316 ----
        {"range_formatter", "<format>", cxx23},
  #line 299 "std-name-hint.gperf"
        {"addressof", "<memory>", cxx11},
! #line 569 "std-name-hint.gperf"
        {"make_integer_sequence", "<utility>", cxx14},
  #line 184 "std-name-hint.gperf"
        {"range_format", "<format>", cxx23},
*************** std_name_hint_lookup::find (const char *
*** 320,344 ****
        {"basic_spanstream", "<spanstream>", cxx23},
  #line 257 "std-name-hint.gperf"
        {"showpos", "<ios>", cxx98},
! #line 550 "std-name-hint.gperf"
        {"as_const", "<utility>", cxx17},
  #line 308 "std-name-hint.gperf"
        {"bad_weak_ptr", "<memory>", cxx11},
  #line 168 "std-name-hint.gperf"
        {"basic_format_context", "<format>", cxx20},
! #line 434 "std-name-hint.gperf"
        {"basic_stringstream", "<sstream>", cxx98},
! #line 539 "std-name-hint.gperf"
        {"type_index", "<typeindex>", cxx11},
  #line 169 "std-name-hint.gperf"
        {"basic_format_parse_context", "<format>", cxx20},
  #line 160 "std-name-hint.gperf"
        {"make_exception_ptr", "<exception>", cxx11},
! #line 468 "std-name-hint.gperf"
        {"basic_streambuf", "<streambuf>", cxx98},
  #line 167 "std-name-hint.gperf"
        {"basic_format_args", "<format>", cxx20},
! #line 589 "std-name-hint.gperf"
        {"variant_size", "<variant>", cxx17},
  #line 407 "std-name-hint.gperf"
        {"multiset", "<set>", cxx98},
--- 320,344 ----
        {"basic_spanstream", "<spanstream>", cxx23},
  #line 257 "std-name-hint.gperf"
        {"showpos", "<ios>", cxx98},
! #line 548 "std-name-hint.gperf"
        {"as_const", "<utility>", cxx17},
  #line 308 "std-name-hint.gperf"
        {"bad_weak_ptr", "<memory>", cxx11},
  #line 168 "std-name-hint.gperf"
        {"basic_format_context", "<format>", cxx20},
! #line 433 "std-name-hint.gperf"
        {"basic_stringstream", "<sstream>", cxx98},
! #line 537 "std-name-hint.gperf"
        {"type_index", "<typeindex>", cxx11},
  #line 169 "std-name-hint.gperf"
        {"basic_format_parse_context", "<format>", cxx20},
  #line 160 "std-name-hint.gperf"
        {"make_exception_ptr", "<exception>", cxx11},
! #line 466 "std-name-hint.gperf"
        {"basic_streambuf", "<streambuf>", cxx98},
  #line 167 "std-name-hint.gperf"
        {"basic_format_args", "<format>", cxx20},
! #line 587 "std-name-hint.gperf"
        {"variant_size", "<variant>", cxx17},
  #line 407 "std-name-hint.gperf"
        {"multiset", "<set>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 350,372 ****
        {"recursive_timed_mutex", "<mutex>", cxx11},
  #line 399 "std-name-hint.gperf"
        {"ranges::enable_borrowed_range", "<ranges>", cxx20},
! #line 533 "std-name-hint.gperf"
        {"remove_cvref", "<type_traits>", cxx20},
  #line 206 "std-name-hint.gperf"
        {"function", "<functional>", cxx11},
! #line 532 "std-name-hint.gperf"
        {"negation_v", "<type_traits>", cxx17},
! #line 534 "std-name-hint.gperf"
        {"remove_cvref_t", "<type_traits>", cxx20},
  #line 289 "std-name-hint.gperf"
        {"ostream_iterator", "<iterator>", cxx98},
! #line 588 "std-name-hint.gperf"
        {"variant_npos", "<variant>", cxx17},
  #line 244 "std-name-hint.gperf"
        {"left", "<ios>", cxx98},
  #line 200 "std-name-hint.gperf"
        {"fstream", "<fstream>", cxx98},
! #line 591 "std-name-hint.gperf"
        {"visit", "<variant>", cxx17},
  #line 208 "std-name-hint.gperf"
        {"invoke", "<functional>", cxx17},
--- 350,372 ----
        {"recursive_timed_mutex", "<mutex>", cxx11},
  #line 399 "std-name-hint.gperf"
        {"ranges::enable_borrowed_range", "<ranges>", cxx20},
! #line 531 "std-name-hint.gperf"
        {"remove_cvref", "<type_traits>", cxx20},
  #line 206 "std-name-hint.gperf"
        {"function", "<functional>", cxx11},
! #line 530 "std-name-hint.gperf"
        {"negation_v", "<type_traits>", cxx17},
! #line 532 "std-name-hint.gperf"
        {"remove_cvref_t", "<type_traits>", cxx20},
  #line 289 "std-name-hint.gperf"
        {"ostream_iterator", "<iterator>", cxx98},
! #line 586 "std-name-hint.gperf"
        {"variant_npos", "<variant>", cxx17},
  #line 244 "std-name-hint.gperf"
        {"left", "<ios>", cxx98},
  #line 200 "std-name-hint.gperf"
        {"fstream", "<fstream>", cxx98},
! #line 589 "std-name-hint.gperf"
        {"visit", "<variant>", cxx17},
  #line 208 "std-name-hint.gperf"
        {"invoke", "<functional>", cxx17},
*************** std_name_hint_lookup::find (const char *
*** 388,394 ****
        {"pointer_traits", "<memory>", cxx11},
  #line 131 "std-name-hint.gperf"
        {"invocable", "<concepts>", cxx20},
! #line 426 "std-name-hint.gperf"
        {"spanstream", "<spanstream>", cxx23},
  #line 182 "std-name-hint.gperf"
        {"make_format_args", "<format>", cxx20},
--- 388,394 ----
        {"pointer_traits", "<memory>", cxx11},
  #line 131 "std-name-hint.gperf"
        {"invocable", "<concepts>", cxx20},
! #line 425 "std-name-hint.gperf"
        {"spanstream", "<spanstream>", cxx23},
  #line 182 "std-name-hint.gperf"
        {"make_format_args", "<format>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 400,408 ****
        {"skipws", "<ios>", cxx98},
  #line 241 "std-name-hint.gperf"
        {"hex", "<ios>", cxx98},
! #line 568 "std-name-hint.gperf"
        {"index_sequence_for", "<utility>", cxx14},
! #line 567 "std-name-hint.gperf"
        {"index_sequence", "<utility>", cxx14},
  #line 350 "std-name-hint.gperf"
        {"mutex", "<mutex>", cxx11},
--- 400,408 ----
        {"skipws", "<ios>", cxx98},
  #line 241 "std-name-hint.gperf"
        {"hex", "<ios>", cxx98},
! #line 566 "std-name-hint.gperf"
        {"index_sequence_for", "<utility>", cxx14},
! #line 565 "std-name-hint.gperf"
        {"index_sequence", "<utility>", cxx14},
  #line 350 "std-name-hint.gperf"
        {"mutex", "<mutex>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 412,418 ****
        {"weak_ptr", "<memory>", cxx11},
  #line 173 "std-name-hint.gperf"
        {"format_context", "<format>", cxx20},
! #line 451 "std-name-hint.gperf"
        {"logic_error", "<stdexcept>", cxx98},
  #line 372 "std-name-hint.gperf"
        {"numbers::ln2_v", "<numbers>", cxx20},
--- 412,418 ----
        {"weak_ptr", "<memory>", cxx11},
  #line 173 "std-name-hint.gperf"
        {"format_context", "<format>", cxx20},
! #line 449 "std-name-hint.gperf"
        {"logic_error", "<stdexcept>", cxx98},
  #line 372 "std-name-hint.gperf"
        {"numbers::ln2_v", "<numbers>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 444,454 ****
        {"pmr::polymorphic_allocator", "<memory_resource>", cxx17},
  #line 419 "std-name-hint.gperf"
        {"basic_ospanstream", "<spanstream>", cxx23},
! #line 572 "std-name-hint.gperf"
        {"make_pair", "<utility>", cxx98},
  #line 172 "std-name-hint.gperf"
        {"format_args", "<format>", cxx20},
! #line 475 "std-name-hint.gperf"
        {"stof", "<string>", cxx11},
  #line 339 "std-name-hint.gperf"
        {"pmr::monotonic_buffer_resource", "<memory_resource>", cxx17},
--- 444,454 ----
        {"pmr::polymorphic_allocator", "<memory_resource>", cxx17},
  #line 419 "std-name-hint.gperf"
        {"basic_ospanstream", "<spanstream>", cxx23},
! #line 570 "std-name-hint.gperf"
        {"make_pair", "<utility>", cxx98},
  #line 172 "std-name-hint.gperf"
        {"format_args", "<format>", cxx20},
! #line 473 "std-name-hint.gperf"
        {"stof", "<string>", cxx11},
  #line 339 "std-name-hint.gperf"
        {"pmr::monotonic_buffer_resource", "<memory_resource>", cxx17},
*************** std_name_hint_lookup::find (const char *
*** 456,464 ****
        {"pmr::pool_options", "<memory_resource>", cxx17},
  #line 256 "std-name-hint.gperf"
        {"showpoint", "<ios>", cxx98},
! #line 446 "std-name-hint.gperf"
        {"stacktrace", "<stacktrace>", cxx23},
! #line 590 "std-name-hint.gperf"
        {"variant_size_v", "<variant>", cxx17},
  #line 212 "std-name-hint.gperf"
        {"reference_wrapper", "<functional>", cxx11},
--- 456,464 ----
        {"pmr::pool_options", "<memory_resource>", cxx17},
  #line 256 "std-name-hint.gperf"
        {"showpoint", "<ios>", cxx98},
! #line 444 "std-name-hint.gperf"
        {"stacktrace", "<stacktrace>", cxx23},
! #line 588 "std-name-hint.gperf"
        {"variant_size_v", "<variant>", cxx17},
  #line 212 "std-name-hint.gperf"
        {"reference_wrapper", "<functional>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 466,484 ****
        {"cerr", "<iostream>", cxx98},
  #line 300 "std-name-hint.gperf"
        {"align", "<memory>", cxx11},
! #line 438 "std-name-hint.gperf"
        {"stringbuf", "<sstream>", cxx98},
! #line 469 "std-name-hint.gperf"
        {"streambuf", "<streambuf>", cxx98},
  #line 306 "std-name-hint.gperf"
        {"allocator_traits", "<memory>", cxx11},
  #line 183 "std-name-hint.gperf"
        {"make_wformat_args", "<format>", cxx20},
! #line 584 "std-name-hint.gperf"
        {"monostate", "<variant>", cxx17},
  #line 387 "std-name-hint.gperf"
        {"flush", "<ostream>", cxx98},
! #line 527 "std-name-hint.gperf"
        {"enable_if", "<type_traits>", cxx11},
  #line 352 "std-name-hint.gperf"
        {"recursive_mutex", "<mutex>", cxx11},
--- 466,484 ----
        {"cerr", "<iostream>", cxx98},
  #line 300 "std-name-hint.gperf"
        {"align", "<memory>", cxx11},
! #line 436 "std-name-hint.gperf"
        {"stringbuf", "<sstream>", cxx98},
! #line 467 "std-name-hint.gperf"
        {"streambuf", "<streambuf>", cxx98},
  #line 306 "std-name-hint.gperf"
        {"allocator_traits", "<memory>", cxx11},
  #line 183 "std-name-hint.gperf"
        {"make_wformat_args", "<format>", cxx20},
! #line 582 "std-name-hint.gperf"
        {"monostate", "<variant>", cxx17},
  #line 387 "std-name-hint.gperf"
        {"flush", "<ostream>", cxx98},
! #line 525 "std-name-hint.gperf"
        {"enable_if", "<type_traits>", cxx11},
  #line 352 "std-name-hint.gperf"
        {"recursive_mutex", "<mutex>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 490,504 ****
        {"pmr::memory_resource", "<memory_resource>", cxx17},
  #line 124 "std-name-hint.gperf"
        {"equality_comparable_with", "<concepts>", cxx20},
! #line 493 "std-name-hint.gperf"
        {"errc", "<system_error>", cxx11},
  #line 344 "std-name-hint.gperf"
        {"pmr::synchronized_pool_resource", "<memory_resource>", cxx17},
  #line 385 "std-name-hint.gperf"
        {"endl", "<ostream>", cxx98},
! #line 495 "std-name-hint.gperf"
        {"error_code", "<system_error>", cxx11},
! #line 528 "std-name-hint.gperf"
        {"enable_if_t", "<type_traits>", cxx14},
  #line 390 "std-name-hint.gperf"
        {"ostream", "<ostream>", cxx98},
--- 490,504 ----
        {"pmr::memory_resource", "<memory_resource>", cxx17},
  #line 124 "std-name-hint.gperf"
        {"equality_comparable_with", "<concepts>", cxx20},
! #line 491 "std-name-hint.gperf"
        {"errc", "<system_error>", cxx11},
  #line 344 "std-name-hint.gperf"
        {"pmr::synchronized_pool_resource", "<memory_resource>", cxx17},
  #line 385 "std-name-hint.gperf"
        {"endl", "<ostream>", cxx98},
! #line 493 "std-name-hint.gperf"
        {"error_code", "<system_error>", cxx11},
! #line 526 "std-name-hint.gperf"
        {"enable_if_t", "<type_traits>", cxx14},
  #line 390 "std-name-hint.gperf"
        {"ostream", "<ostream>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 508,534 ****
        {"numbers::log10e_v", "<numbers>", cxx20},
  #line 364 "std-name-hint.gperf"
        {"nothrow_t", "<new>", cxx98},
! #line 512 "std-name-hint.gperf"
        {"ignore", "<tuple>", cxx11},
  #line 360 "std-name-hint.gperf"
        {"hardware_constructive_interference_size", "<new>", cxx17},
  #line 396 "std-name-hint.gperf"
        {"priority_queue", "<queue>", cxx98},
! #line 424 "std-name-hint.gperf"
        {"ospanstream", "<spanstream>", cxx23},
  #line 316 "std-name-hint.gperf"
        {"enable_shared_from_this", "<memory>", cxx11},
  #line 265 "std-name-hint.gperf"
        {"cout", "<iostream>", cxx98},
! #line 552 "std-name-hint.gperf"
        {"cmp_greater", "<utility>", cxx20},
! #line 490 "std-name-hint.gperf"
        {"basic_string_view", "<string_view>", cxx17},
  #line 249 "std-name-hint.gperf"
        {"noskipws", "<ios>", cxx98},
  #line 177 "std-name-hint.gperf"
        {"format_to", "<format>", cxx20},
! #line 502 "std-name-hint.gperf"
        {"make_error_code", "<system_error>", cxx11},
  #line 174 "std-name-hint.gperf"
        {"format_error", "<format>", cxx20},
--- 508,534 ----
        {"numbers::log10e_v", "<numbers>", cxx20},
  #line 364 "std-name-hint.gperf"
        {"nothrow_t", "<new>", cxx98},
! #line 510 "std-name-hint.gperf"
        {"ignore", "<tuple>", cxx11},
  #line 360 "std-name-hint.gperf"
        {"hardware_constructive_interference_size", "<new>", cxx17},
  #line 396 "std-name-hint.gperf"
        {"priority_queue", "<queue>", cxx98},
! #line 423 "std-name-hint.gperf"
        {"ospanstream", "<spanstream>", cxx23},
  #line 316 "std-name-hint.gperf"
        {"enable_shared_from_this", "<memory>", cxx11},
  #line 265 "std-name-hint.gperf"
        {"cout", "<iostream>", cxx98},
! #line 550 "std-name-hint.gperf"
        {"cmp_greater", "<utility>", cxx20},
! #line 488 "std-name-hint.gperf"
        {"basic_string_view", "<string_view>", cxx17},
  #line 249 "std-name-hint.gperf"
        {"noskipws", "<ios>", cxx98},
  #line 177 "std-name-hint.gperf"
        {"format_to", "<format>", cxx20},
! #line 500 "std-name-hint.gperf"
        {"make_error_code", "<system_error>", cxx11},
  #line 174 "std-name-hint.gperf"
        {"format_error", "<format>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 542,548 ****
        {"hexfloat", "<ios>", cxx11},
  #line 326 "std-name-hint.gperf"
        {"shared_ptr", "<memory>", cxx11},
! #line 569 "std-name-hint.gperf"
        {"integer_sequence", "<utility>", cxx14},
  #line 271 "std-name-hint.gperf"
        {"istream", "<istream>", cxx98},
--- 542,548 ----
        {"hexfloat", "<ios>", cxx11},
  #line 326 "std-name-hint.gperf"
        {"shared_ptr", "<memory>", cxx11},
! #line 567 "std-name-hint.gperf"
        {"integer_sequence", "<utility>", cxx14},
  #line 271 "std-name-hint.gperf"
        {"istream", "<istream>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 552,570 ****
        {"unitbuf", "<ios>", cxx98},
  #line 294 "std-name-hint.gperf"
        {"list", "<list>", cxx98},
! #line 554 "std-name-hint.gperf"
        {"cmp_less", "<utility>", cxx20},
  #line 422 "std-name-hint.gperf"
        {"ispanstream", "<spanstream>", cxx23},
! #line 423 "std-name-hint.gperf"
!       {"ispanstream", "<spanstream>", cxx23},
! #line 470 "std-name-hint.gperf"
        {"wstreambuf", "<streambuf>", cxx98},
! #line 432 "std-name-hint.gperf"
        {"basic_ostringstream", "<sstream>", cxx98},
! #line 503 "std-name-hint.gperf"
        {"make_error_condition", "<system_error>", cxx11},
! #line 570 "std-name-hint.gperf"
        {"make_index_sequence", "<utility>", cxx14},
  #line 405 "std-name-hint.gperf"
        {"counting_semaphore", "<semaphore>", cxx20},
--- 552,568 ----
        {"unitbuf", "<ios>", cxx98},
  #line 294 "std-name-hint.gperf"
        {"list", "<list>", cxx98},
! #line 552 "std-name-hint.gperf"
        {"cmp_less", "<utility>", cxx20},
  #line 422 "std-name-hint.gperf"
        {"ispanstream", "<spanstream>", cxx23},
! #line 468 "std-name-hint.gperf"
        {"wstreambuf", "<streambuf>", cxx98},
! #line 431 "std-name-hint.gperf"
        {"basic_ostringstream", "<sstream>", cxx98},
! #line 501 "std-name-hint.gperf"
        {"make_error_condition", "<system_error>", cxx11},
! #line 568 "std-name-hint.gperf"
        {"make_index_sequence", "<utility>", cxx14},
  #line 405 "std-name-hint.gperf"
        {"counting_semaphore", "<semaphore>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 578,594 ****
        {"const_pointer_cast", "<memory>", cxx11},
  #line 45 "std-name-hint.gperf"
        {"make_any", "<any>", cxx17},
! #line 465 "std-name-hint.gperf"
        {"stop_source", "<stop_token>", cxx20},
! #line 548 "std-name-hint.gperf"
        {"unordered_set", "<unordered_set>", cxx11},
! #line 583 "std-name-hint.gperf"
        {"holds_alternative", "<variant>", cxx17},
! #line 514 "std-name-hint.gperf"
        {"make_tuple", "<tuple>", cxx11},
  #line 47 "std-name-hint.gperf"
        {"array", "<array>", cxx11},
! #line 517 "std-name-hint.gperf"
        {"tuple_cat", "<tuple>", cxx11},
  #line 323 "std-name-hint.gperf"
        {"owner_less", "<memory>", cxx11},
--- 576,592 ----
        {"const_pointer_cast", "<memory>", cxx11},
  #line 45 "std-name-hint.gperf"
        {"make_any", "<any>", cxx17},
! #line 463 "std-name-hint.gperf"
        {"stop_source", "<stop_token>", cxx20},
! #line 546 "std-name-hint.gperf"
        {"unordered_set", "<unordered_set>", cxx11},
! #line 581 "std-name-hint.gperf"
        {"holds_alternative", "<variant>", cxx17},
! #line 512 "std-name-hint.gperf"
        {"make_tuple", "<tuple>", cxx11},
  #line 47 "std-name-hint.gperf"
        {"array", "<array>", cxx11},
! #line 515 "std-name-hint.gperf"
        {"tuple_cat", "<tuple>", cxx11},
  #line 323 "std-name-hint.gperf"
        {"owner_less", "<memory>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 598,612 ****
        {"exception_ptr", "<exception>", cxx11},
  #line 207 "std-name-hint.gperf"
        {"hash", "<functional>", cxx11},
! #line 521 "std-name-hint.gperf"
        {"tuple_size_v", "<tuple>", cxx17},
! #line 431 "std-name-hint.gperf"
        {"basic_istringstream", "<sstream>", cxx98},
  #line 153 "std-name-hint.gperf"
        {"uintptr_t", "<cstdint>", cxx11},
! #line 476 "std-name-hint.gperf"
        {"stoi", "<string>", cxx11},
! #line 466 "std-name-hint.gperf"
        {"stop_token", "<stop_token>", cxx20},
  #line 151 "std-name-hint.gperf"
        {"uint_least8_t", "<cstdint>", cxx11},
--- 596,610 ----
        {"exception_ptr", "<exception>", cxx11},
  #line 207 "std-name-hint.gperf"
        {"hash", "<functional>", cxx11},
! #line 519 "std-name-hint.gperf"
        {"tuple_size_v", "<tuple>", cxx17},
! #line 430 "std-name-hint.gperf"
        {"basic_istringstream", "<sstream>", cxx98},
  #line 153 "std-name-hint.gperf"
        {"uintptr_t", "<cstdint>", cxx11},
! #line 474 "std-name-hint.gperf"
        {"stoi", "<string>", cxx11},
! #line 464 "std-name-hint.gperf"
        {"stop_token", "<stop_token>", cxx20},
  #line 151 "std-name-hint.gperf"
        {"uint_least8_t", "<cstdint>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 622,628 ****
        {"shared_mutex", "<shared_mutex>", cxx17},
  #line 375 "std-name-hint.gperf"
        {"numbers::phi_v", "<numbers>", cxx20},
! #line 499 "std-name-hint.gperf"
        {"is_error_code_enum_v", "<system_error>", cxx17},
  #line 155 "std-name-hint.gperf"
        {"deque", "<deque>", cxx98},
--- 620,626 ----
        {"shared_mutex", "<shared_mutex>", cxx17},
  #line 375 "std-name-hint.gperf"
        {"numbers::phi_v", "<numbers>", cxx20},
! #line 497 "std-name-hint.gperf"
        {"is_error_code_enum_v", "<system_error>", cxx17},
  #line 155 "std-name-hint.gperf"
        {"deque", "<deque>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 630,636 ****
        {"shared_timed_mutex", "<shared_mutex>", cxx14},
  #line 290 "std-name-hint.gperf"
        {"ostreambuf_iterator", "<iterator>", cxx98},
! #line 501 "std-name-hint.gperf"
        {"is_error_condition_enum_v", "<system_error>", cxx17},
  #line 148 "std-name-hint.gperf"
        {"uint_least16_t", "<cstdint>", cxx11},
--- 628,634 ----
        {"shared_timed_mutex", "<shared_mutex>", cxx14},
  #line 290 "std-name-hint.gperf"
        {"ostreambuf_iterator", "<iterator>", cxx98},
! #line 499 "std-name-hint.gperf"
        {"is_error_condition_enum_v", "<system_error>", cxx17},
  #line 148 "std-name-hint.gperf"
        {"uint_least16_t", "<cstdint>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 640,646 ****
        {"numbers::e_v", "<numbers>", cxx20},
  #line 209 "std-name-hint.gperf"
        {"invoke_r", "<functional>", cxx23},
! #line 441 "std-name-hint.gperf"
        {"wostringstream", "<sstream>", cxx98},
  #line 122 "std-name-hint.gperf"
        {"copy_constructible", "<concepts>", cxx20},
--- 638,644 ----
        {"numbers::e_v", "<numbers>", cxx20},
  #line 209 "std-name-hint.gperf"
        {"invoke_r", "<functional>", cxx23},
! #line 439 "std-name-hint.gperf"
        {"wostringstream", "<sstream>", cxx98},
  #line 122 "std-name-hint.gperf"
        {"copy_constructible", "<concepts>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 650,662 ****
        {"convertible_to", "<concepts>", cxx20},
  #line 234 "std-name-hint.gperf"
        {"setprecision", "<iomanip>", cxx98},
! #line 498 "std-name-hint.gperf"
        {"is_error_code_enum", "<system_error>", cxx11},
! #line 453 "std-name-hint.gperf"
        {"overflow_error", "<stdexcept>", cxx98},
  #line 414 "std-name-hint.gperf"
        {"source_location", "<source_location>", cxx20},
! #line 500 "std-name-hint.gperf"
        {"is_error_condition_enum", "<system_error>", cxx11},
  #line 400 "std-name-hint.gperf"
        {"ranges::enable_view", "<ranges>", cxx20},
--- 648,660 ----
        {"convertible_to", "<concepts>", cxx20},
  #line 234 "std-name-hint.gperf"
        {"setprecision", "<iomanip>", cxx98},
! #line 496 "std-name-hint.gperf"
        {"is_error_code_enum", "<system_error>", cxx11},
! #line 451 "std-name-hint.gperf"
        {"overflow_error", "<stdexcept>", cxx98},
  #line 414 "std-name-hint.gperf"
        {"source_location", "<source_location>", cxx20},
! #line 498 "std-name-hint.gperf"
        {"is_error_condition_enum", "<system_error>", cxx11},
  #line 400 "std-name-hint.gperf"
        {"ranges::enable_view", "<ranges>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 672,678 ****
        {"chrono::parse", "<chrono>", cxx20},
  #line 285 "std-name-hint.gperf"
        {"istreambuf_iterator", "<iterator>", cxx98},
! #line 473 "std-name-hint.gperf"
        {"char_traits", "<string>", cxx98},
  #line 263 "std-name-hint.gperf"
        {"cin", "<iostream>", cxx98},
--- 670,676 ----
        {"chrono::parse", "<chrono>", cxx20},
  #line 285 "std-name-hint.gperf"
        {"istreambuf_iterator", "<iterator>", cxx98},
! #line 471 "std-name-hint.gperf"
        {"char_traits", "<string>", cxx98},
  #line 263 "std-name-hint.gperf"
        {"cin", "<iostream>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 692,728 ****
        {"chrono::get_tzdb", "<chrono>", cxx20},
  #line 302 "std-name-hint.gperf"
        {"allocate_shared_for_overwrite", "<memory>", cxx20},
! #line 547 "std-name-hint.gperf"
        {"unordered_multiset", "<unordered_set>", cxx11},
  #line 194 "std-name-hint.gperf"
        {"forward_list", "<forward_list>", cxx11},
! #line 496 "std-name-hint.gperf"
        {"error_condition", "<system_error>", cxx11},
! #line 542 "std-name-hint.gperf"
        {"bad_typeid", "<typeinfo>", cxx98},
  #line 60 "std-name-hint.gperf"
        {"chrono::duration", "<chrono>", cxx11},
! #line 510 "std-name-hint.gperf"
        {"apply", "<tuple>", cxx17},
  #line 95 "std-name-hint.gperf"
        {"chrono::zoned_time", "<chrono>", cxx20},
! #line 477 "std-name-hint.gperf"
        {"stol", "<string>", cxx11},
! #line 479 "std-name-hint.gperf"
        {"stoll", "<string>", cxx11},
! #line 480 "std-name-hint.gperf"
        {"stoul", "<string>", cxx11},
! #line 481 "std-name-hint.gperf"
        {"stoull", "<string>", cxx11},
  #line 220 "std-name-hint.gperf"
        {"packaged_task", "<future>", cxx11},
! #line 544 "std-name-hint.gperf"
        {"unordered_map", "<unordered_map>", cxx11},
  #line 77 "std-name-hint.gperf"
        {"chrono::months", "<chrono>", cxx20},
  #line 76 "std-name-hint.gperf"
        {"chrono::minutes", "<chrono>", cxx11},
! #line 545 "std-name-hint.gperf"
        {"unordered_multimap", "<unordered_map>", cxx11},
  #line 78 "std-name-hint.gperf"
        {"chrono::nanoseconds", "<chrono>", cxx11},
--- 690,726 ----
        {"chrono::get_tzdb", "<chrono>", cxx20},
  #line 302 "std-name-hint.gperf"
        {"allocate_shared_for_overwrite", "<memory>", cxx20},
! #line 545 "std-name-hint.gperf"
        {"unordered_multiset", "<unordered_set>", cxx11},
  #line 194 "std-name-hint.gperf"
        {"forward_list", "<forward_list>", cxx11},
! #line 494 "std-name-hint.gperf"
        {"error_condition", "<system_error>", cxx11},
! #line 540 "std-name-hint.gperf"
        {"bad_typeid", "<typeinfo>", cxx98},
  #line 60 "std-name-hint.gperf"
        {"chrono::duration", "<chrono>", cxx11},
! #line 508 "std-name-hint.gperf"
        {"apply", "<tuple>", cxx17},
  #line 95 "std-name-hint.gperf"
        {"chrono::zoned_time", "<chrono>", cxx20},
! #line 475 "std-name-hint.gperf"
        {"stol", "<string>", cxx11},
! #line 477 "std-name-hint.gperf"
        {"stoll", "<string>", cxx11},
! #line 478 "std-name-hint.gperf"
        {"stoul", "<string>", cxx11},
! #line 479 "std-name-hint.gperf"
        {"stoull", "<string>", cxx11},
  #line 220 "std-name-hint.gperf"
        {"packaged_task", "<future>", cxx11},
! #line 542 "std-name-hint.gperf"
        {"unordered_map", "<unordered_map>", cxx11},
  #line 77 "std-name-hint.gperf"
        {"chrono::months", "<chrono>", cxx20},
  #line 76 "std-name-hint.gperf"
        {"chrono::minutes", "<chrono>", cxx11},
! #line 543 "std-name-hint.gperf"
        {"unordered_multimap", "<unordered_map>", cxx11},
  #line 78 "std-name-hint.gperf"
        {"chrono::nanoseconds", "<chrono>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 732,752 ****
        {"binary_semaphore", "<semaphore>", cxx20},
  #line 281 "std-name-hint.gperf"
        {"end", "<iterator>", cxx11},
! #line 429 "std-name-hint.gperf"
        {"wspanbuf", "<spanstream>", cxx23},
  #line 252 "std-name-hint.gperf"
        {"oct", "<ios>", cxx98},
  #line 245 "std-name-hint.gperf"
        {"noboolalpha", "<ios>", cxx98},
! #line 450 "std-name-hint.gperf"
        {"length_error", "<stdexcept>", cxx98},
! #line 560 "std-name-hint.gperf"
        {"in_place", "<utility>", cxx17},
! #line 563 "std-name-hint.gperf"
        {"in_place_t", "<utility>", cxx17},
  #line 384 "std-name-hint.gperf"
        {"emit_on_flush", "<ostream>", cxx20},
! #line 440 "std-name-hint.gperf"
        {"wistringstream", "<sstream>", cxx98},
  #line 327 "std-name-hint.gperf"
        {"static_pointer_cast", "<memory>", cxx11},
--- 730,750 ----
        {"binary_semaphore", "<semaphore>", cxx20},
  #line 281 "std-name-hint.gperf"
        {"end", "<iterator>", cxx11},
! #line 428 "std-name-hint.gperf"
        {"wspanbuf", "<spanstream>", cxx23},
  #line 252 "std-name-hint.gperf"
        {"oct", "<ios>", cxx98},
  #line 245 "std-name-hint.gperf"
        {"noboolalpha", "<ios>", cxx98},
! #line 448 "std-name-hint.gperf"
        {"length_error", "<stdexcept>", cxx98},
! #line 558 "std-name-hint.gperf"
        {"in_place", "<utility>", cxx17},
! #line 561 "std-name-hint.gperf"
        {"in_place_t", "<utility>", cxx17},
  #line 384 "std-name-hint.gperf"
        {"emit_on_flush", "<ostream>", cxx20},
! #line 438 "std-name-hint.gperf"
        {"wistringstream", "<sstream>", cxx98},
  #line 327 "std-name-hint.gperf"
        {"static_pointer_cast", "<memory>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 762,768 ****
        {"wostream", "<ostream>", cxx98},
  #line 348 "std-name-hint.gperf"
        {"lock", "<mutex>", cxx11},
! #line 504 "std-name-hint.gperf"
        {"system_category", "<system_error>", cxx11},
  #line 128 "std-name-hint.gperf"
        {"copyable", "<concepts>", cxx20},
--- 760,766 ----
        {"wostream", "<ostream>", cxx98},
  #line 348 "std-name-hint.gperf"
        {"lock", "<mutex>", cxx11},
! #line 502 "std-name-hint.gperf"
        {"system_category", "<system_error>", cxx11},
  #line 128 "std-name-hint.gperf"
        {"copyable", "<concepts>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 770,790 ****
        {"condition_variable", "<condition_variable>", cxx11},
  #line 240 "std-name-hint.gperf"
        {"fixed", "<ios>", cxx98},
! #line 553 "std-name-hint.gperf"
        {"cmp_greater_equal", "<utility>", cxx20},
! #line 508 "std-name-hint.gperf"
        {"thread", "<thread>", cxx11},
! #line 439 "std-name-hint.gperf"
        {"stringstream", "<sstream>", cxx98},
  #line 58 "std-name-hint.gperf"
        {"chrono::clock_cast", "<chrono>", cxx20},
! #line 579 "std-name-hint.gperf"
        {"unreachable", "<utility>", cxx23},
! #line 428 "std-name-hint.gperf"
        {"wospanstream", "<spanstream>", cxx23},
  #line 330 "std-name-hint.gperf"
        {"unique_ptr", "<memory>", cxx11},
! #line 562 "std-name-hint.gperf"
        {"in_place_index_t", "<utility>", cxx17},
  #line 363 "std-name-hint.gperf"
        {"nothrow", "<new>", cxx98},
--- 768,788 ----
        {"condition_variable", "<condition_variable>", cxx11},
  #line 240 "std-name-hint.gperf"
        {"fixed", "<ios>", cxx98},
! #line 551 "std-name-hint.gperf"
        {"cmp_greater_equal", "<utility>", cxx20},
! #line 506 "std-name-hint.gperf"
        {"thread", "<thread>", cxx11},
! #line 437 "std-name-hint.gperf"
        {"stringstream", "<sstream>", cxx98},
  #line 58 "std-name-hint.gperf"
        {"chrono::clock_cast", "<chrono>", cxx20},
! #line 577 "std-name-hint.gperf"
        {"unreachable", "<utility>", cxx23},
! #line 427 "std-name-hint.gperf"
        {"wospanstream", "<spanstream>", cxx23},
  #line 330 "std-name-hint.gperf"
        {"unique_ptr", "<memory>", cxx11},
! #line 560 "std-name-hint.gperf"
        {"in_place_index_t", "<utility>", cxx17},
  #line 363 "std-name-hint.gperf"
        {"nothrow", "<new>", cxx98},
*************** std_name_hint_lookup::find (const char *
*** 800,806 ****
        {"uint_fast32_t", "<cstdint>", cxx11},
  #line 87 "std-name-hint.gperf"
        {"chrono::time_point", "<chrono>", cxx11},
! #line 444 "std-name-hint.gperf"
        {"stack", "<stack>", cxx98},
  #line 215 "std-name-hint.gperf"
        {"unwrap_reference", "<functional>", cxx20},
--- 798,804 ----
        {"uint_fast32_t", "<cstdint>", cxx11},
  #line 87 "std-name-hint.gperf"
        {"chrono::time_point", "<chrono>", cxx11},
! #line 442 "std-name-hint.gperf"
        {"stack", "<stack>", cxx98},
  #line 215 "std-name-hint.gperf"
        {"unwrap_reference", "<functional>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 814,820 ****
        {"optional", "<optional>", cxx17},
  #line 112 "std-name-hint.gperf"
        {"signed_integral", "<concepts>", cxx20},
! #line 456 "std-name-hint.gperf"
        {"underflow_error", "<stdexcept>", cxx98},
  #line 239 "std-name-hint.gperf"
        {"defaultfloat", "<ios>", cxx11},
--- 812,818 ----
        {"optional", "<optional>", cxx17},
  #line 112 "std-name-hint.gperf"
        {"signed_integral", "<concepts>", cxx20},
! #line 454 "std-name-hint.gperf"
        {"underflow_error", "<stdexcept>", cxx98},
  #line 239 "std-name-hint.gperf"
        {"defaultfloat", "<ios>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 832,850 ****
        {"uninitialized_construct_using_allocator", "<memory>", cxx20},
  #line 81 "std-name-hint.gperf"
        {"chrono::remote_version", "<chrono>", cxx20},
! #line 458 "std-name-hint.gperf"
        {"bfloat16_t", "<stdfloat>", cxx23},
! #line 576 "std-name-hint.gperf"
        {"piecewise_construct", "<utility>", cxx11},
! #line 577 "std-name-hint.gperf"
        {"piecewise_construct_t", "<utility>", cxx11},
  #line 278 "std-name-hint.gperf"
        {"const_iterator", "<iterator>", cxx23},
! #line 484 "std-name-hint.gperf"
        {"to_wstring", "<string>", cxx17},
  #line 356 "std-name-hint.gperf"
        {"try_lock", "<mutex>", cxx11},
! #line 561 "std-name-hint.gperf"
        {"in_place_index", "<utility>", cxx17},
  #line 51 "std-name-hint.gperf"
        {"atomic_ref", "<atomic>", cxx20},
--- 830,848 ----
        {"uninitialized_construct_using_allocator", "<memory>", cxx20},
  #line 81 "std-name-hint.gperf"
        {"chrono::remote_version", "<chrono>", cxx20},
! #line 456 "std-name-hint.gperf"
        {"bfloat16_t", "<stdfloat>", cxx23},
! #line 574 "std-name-hint.gperf"
        {"piecewise_construct", "<utility>", cxx11},
! #line 575 "std-name-hint.gperf"
        {"piecewise_construct_t", "<utility>", cxx11},
  #line 278 "std-name-hint.gperf"
        {"const_iterator", "<iterator>", cxx23},
! #line 482 "std-name-hint.gperf"
        {"to_wstring", "<string>", cxx17},
  #line 356 "std-name-hint.gperf"
        {"try_lock", "<mutex>", cxx11},
! #line 559 "std-name-hint.gperf"
        {"in_place_index", "<utility>", cxx17},
  #line 51 "std-name-hint.gperf"
        {"atomic_ref", "<atomic>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 862,868 ****
        {"uncaught_exceptions", "<exception>", cxx17},
  #line 331 "std-name-hint.gperf"
        {"uses_allocator", "<memory>", cxx11},
! #line 472 "std-name-hint.gperf"
        {"basic_string", "<string>", cxx98},
  #line 311 "std-name-hint.gperf"
        {"default_delete", "<memory>", cxx11},
--- 860,866 ----
        {"uncaught_exceptions", "<exception>", cxx17},
  #line 331 "std-name-hint.gperf"
        {"uses_allocator", "<memory>", cxx11},
! #line 470 "std-name-hint.gperf"
        {"basic_string", "<string>", cxx98},
  #line 311 "std-name-hint.gperf"
        {"default_delete", "<memory>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 870,886 ****
        {"expected", "<expected>", cxx23},
  #line 313 "std-name-hint.gperf"
        {"destroy_at", "<memory>", cxx20},
! #line 536 "std-name-hint.gperf"
        {"type_identity_t", "<type_traits>", cxx20},
  #line 63 "std-name-hint.gperf"
        {"chrono::from_stream", "<chrono>", cxx20},
! #line 427 "std-name-hint.gperf"
        {"wispanstream", "<spanstream>", cxx23},
  #line 52 "std-name-hint.gperf"
        {"atomic_signed_lock_free", "<atomic>", cxx11},
  #line 266 "std-name-hint.gperf"
        {"wcerr", "<iostream>", cxx98},
! #line 511 "std-name-hint.gperf"
        {"forward_as_tuple", "<tuple>", cxx11},
  #line 187 "std-name-hint.gperf"
        {"vformat", "<format>", cxx20},
--- 868,884 ----
        {"expected", "<expected>", cxx23},
  #line 313 "std-name-hint.gperf"
        {"destroy_at", "<memory>", cxx20},
! #line 534 "std-name-hint.gperf"
        {"type_identity_t", "<type_traits>", cxx20},
  #line 63 "std-name-hint.gperf"
        {"chrono::from_stream", "<chrono>", cxx20},
! #line 426 "std-name-hint.gperf"
        {"wispanstream", "<spanstream>", cxx23},
  #line 52 "std-name-hint.gperf"
        {"atomic_signed_lock_free", "<atomic>", cxx11},
  #line 266 "std-name-hint.gperf"
        {"wcerr", "<iostream>", cxx98},
! #line 509 "std-name-hint.gperf"
        {"forward_as_tuple", "<tuple>", cxx11},
  #line 187 "std-name-hint.gperf"
        {"vformat", "<format>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 892,916 ****
        {"destroy_n", "<memory>", cxx20},
  #line 226 "std-name-hint.gperf"
        {"get_time", "<iomanip>", cxx11},
! #line 555 "std-name-hint.gperf"
        {"cmp_less_equal", "<utility>", cxx20},
  #line 80 "std-name-hint.gperf"
        {"chrono::reload_tzdb", "<chrono>", cxx20},
! #line 523 "std-name-hint.gperf"
        {"conjunction", "<type_traits>", cxx17},
  #line 75 "std-name-hint.gperf"
        {"chrono::milliseconds", "<chrono>", cxx11},
  #line 59 "std-name-hint.gperf"
        {"chrono::days", "<chrono>", cxx20},
! #line 474 "std-name-hint.gperf"
        {"stod", "<string>", cxx11},
! #line 478 "std-name-hint.gperf"
        {"stold", "<string>", cxx11},
  #line 267 "std-name-hint.gperf"
        {"wcin", "<iostream>", cxx98},
! #line 529 "std-name-hint.gperf"
        {"invoke_result", "<type_traits>", cxx17},
! #line 530 "std-name-hint.gperf"
        {"invoke_result_t", "<type_traits>", cxx17},
  #line 50 "std-name-hint.gperf"
        {"atomic", "<atomic>", cxx11},
--- 890,914 ----
        {"destroy_n", "<memory>", cxx20},
  #line 226 "std-name-hint.gperf"
        {"get_time", "<iomanip>", cxx11},
! #line 553 "std-name-hint.gperf"
        {"cmp_less_equal", "<utility>", cxx20},
  #line 80 "std-name-hint.gperf"
        {"chrono::reload_tzdb", "<chrono>", cxx20},
! #line 521 "std-name-hint.gperf"
        {"conjunction", "<type_traits>", cxx17},
  #line 75 "std-name-hint.gperf"
        {"chrono::milliseconds", "<chrono>", cxx11},
  #line 59 "std-name-hint.gperf"
        {"chrono::days", "<chrono>", cxx20},
! #line 472 "std-name-hint.gperf"
        {"stod", "<string>", cxx11},
! #line 476 "std-name-hint.gperf"
        {"stold", "<string>", cxx11},
  #line 267 "std-name-hint.gperf"
        {"wcin", "<iostream>", cxx98},
! #line 527 "std-name-hint.gperf"
        {"invoke_result", "<type_traits>", cxx17},
! #line 528 "std-name-hint.gperf"
        {"invoke_result_t", "<type_traits>", cxx17},
  #line 50 "std-name-hint.gperf"
        {"atomic", "<atomic>", cxx11},
*************** std_name_hint_lookup::find (const char *
*** 930,946 ****
        {"chrono::hours", "<chrono>", cxx11},
  #line 109 "std-name-hint.gperf"
        {"common_reference_with", "<concepts>", cxx20},
! #line 483 "std-name-hint.gperf"
        {"to_string", "<string>", cxx17},
! #line 524 "std-name-hint.gperf"
        {"conjunction_v", "<type_traits>", cxx17},
! #line 578 "std-name-hint.gperf"
        {"to_underlying", "<utility>", cxx23},
  #line 402 "std-name-hint.gperf"
        {"scoped_allocator_adaptor", "<scoped_allocator>", cxx11},
  #line 310 "std-name-hint.gperf"
        {"construct_at", "<memory>", cxx20},
! #line 564 "std-name-hint.gperf"
        {"in_place_type", "<utility>", cxx17},
  #line 320 "std-name-hint.gperf"
        {"make_shared_for_overwrite", "<memory>", cxx20},
--- 928,944 ----
        {"chrono::hours", "<chrono>", cxx11},
  #line 109 "std-name-hint.gperf"
        {"common_reference_with", "<concepts>", cxx20},
! #line 481 "std-name-hint.gperf"
        {"to_string", "<string>", cxx17},
! #line 522 "std-name-hint.gperf"
        {"conjunction_v", "<type_traits>", cxx17},
! #line 576 "std-name-hint.gperf"
        {"to_underlying", "<utility>", cxx23},
  #line 402 "std-name-hint.gperf"
        {"scoped_allocator_adaptor", "<scoped_allocator>", cxx11},
  #line 310 "std-name-hint.gperf"
        {"construct_at", "<memory>", cxx20},
! #line 562 "std-name-hint.gperf"
        {"in_place_type", "<utility>", cxx17},
  #line 320 "std-name-hint.gperf"
        {"make_shared_for_overwrite", "<memory>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 952,966 ****
        {"chrono::local_t", "<chrono>", cxx20},
  #line 170 "std-name-hint.gperf"
        {"basic_format_string", "<format>", cxx20},
! #line 565 "std-name-hint.gperf"
        {"in_place_type_t", "<utility>", cxx17},
  #line 279 "std-name-hint.gperf"
        {"counted_iterator", "<iterator>", cxx20},
! #line 448 "std-name-hint.gperf"
        {"domain_error", "<stdexcept>", cxx98},
  #line 84 "std-name-hint.gperf"
        {"chrono::steady_clock", "<chrono>", cxx11},
! #line 580 "std-name-hint.gperf"
        {"observable_checkpoint", "<utility>", cxx26},
  #line 188 "std-name-hint.gperf"
        {"vformat_to", "<format>", cxx20},
--- 950,964 ----
        {"chrono::local_t", "<chrono>", cxx20},
  #line 170 "std-name-hint.gperf"
        {"basic_format_string", "<format>", cxx20},
! #line 563 "std-name-hint.gperf"
        {"in_place_type_t", "<utility>", cxx17},
  #line 279 "std-name-hint.gperf"
        {"counted_iterator", "<iterator>", cxx20},
! #line 446 "std-name-hint.gperf"
        {"domain_error", "<stdexcept>", cxx98},
  #line 84 "std-name-hint.gperf"
        {"chrono::steady_clock", "<chrono>", cxx11},
! #line 578 "std-name-hint.gperf"
        {"observable_checkpoint", "<utility>", cxx26},
  #line 188 "std-name-hint.gperf"
        {"vformat_to", "<format>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 982,1032 ****
        {"unwrap_ref_decay_t", "<functional>", cxx20},
  #line 136 "std-name-hint.gperf"
        {"strict_weak_order", "<concepts>", cxx20},
! #line 437 "std-name-hint.gperf"
        {"ostringstream", "<sstream>", cxx98},
  #line 317 "std-name-hint.gperf"
        {"get_deleter", "<memory>", cxx11},
  #line 367 "std-name-hint.gperf"
        {"numbers::egamma_v", "<numbers>", cxx20},
! #line 566 "std-name-hint.gperf"
        {"in_range", "<utility>", cxx20},
! #line 558 "std-name-hint.gperf"
        {"exchange", "<utility>", cxx14},
! #line 551 "std-name-hint.gperf"
        {"cmp_equal", "<utility>", cxx20},
! #line 556 "std-name-hint.gperf"
        {"cmp_not_equal", "<utility>", cxx20},
! #line 435 "std-name-hint.gperf"
!       {"istringstream", "<sstream>", cxx98},
! #line 436 "std-name-hint.gperf"
        {"istringstream", "<sstream>", cxx98},
! #line 442 "std-name-hint.gperf"
        {"wstringbuf", "<sstream>", cxx98},
  #line 225 "std-name-hint.gperf"
        {"get_money", "<iomanip>", cxx11},
  #line 191 "std-name-hint.gperf"
        {"wformat_parse_context", "<format>", cxx20},
! #line 482 "std-name-hint.gperf"
        {"string", "<string>", cxx98},
  #line 280 "std-name-hint.gperf"
        {"distance", "<iterator>", cxx98},
! #line 557 "std-name-hint.gperf"
        {"declval", "<utility>", cxx11},
  #line 254 "std-name-hint.gperf"
        {"scientific", "<ios>", cxx98},
  #line 98 "std-name-hint.gperf"
        {"strong_equality", "<compare>", cxx20},
! #line 487 "std-name-hint.gperf"
        {"u8string", "<string>", cxx20},
  #line 190 "std-name-hint.gperf"
        {"wformat_context", "<format>", cxx20},
  #line 312 "std-name-hint.gperf"
        {"destroy", "<memory>", cxx20},
! #line 559 "std-name-hint.gperf"
        {"forward", "<utility>", cxx11},
! #line 535 "std-name-hint.gperf"
        {"type_identity", "<type_traits>", cxx20},
! #line 464 "std-name-hint.gperf"
        {"stop_callback", "<stop_token>", cxx20},
  #line 86 "std-name-hint.gperf"
        {"chrono::tai_clock", "<chrono>", cxx20},
--- 980,1028 ----
        {"unwrap_ref_decay_t", "<functional>", cxx20},
  #line 136 "std-name-hint.gperf"
        {"strict_weak_order", "<concepts>", cxx20},
! #line 435 "std-name-hint.gperf"
        {"ostringstream", "<sstream>", cxx98},
  #line 317 "std-name-hint.gperf"
        {"get_deleter", "<memory>", cxx11},
  #line 367 "std-name-hint.gperf"
        {"numbers::egamma_v", "<numbers>", cxx20},
! #line 564 "std-name-hint.gperf"
        {"in_range", "<utility>", cxx20},
! #line 556 "std-name-hint.gperf"
        {"exchange", "<utility>", cxx14},
! #line 549 "std-name-hint.gperf"
        {"cmp_equal", "<utility>", cxx20},
! #line 554 "std-name-hint.gperf"
        {"cmp_not_equal", "<utility>", cxx20},
! #line 434 "std-name-hint.gperf"
        {"istringstream", "<sstream>", cxx98},
! #line 440 "std-name-hint.gperf"
        {"wstringbuf", "<sstream>", cxx98},
  #line 225 "std-name-hint.gperf"
        {"get_money", "<iomanip>", cxx11},
  #line 191 "std-name-hint.gperf"
        {"wformat_parse_context", "<format>", cxx20},
! #line 480 "std-name-hint.gperf"
        {"string", "<string>", cxx98},
  #line 280 "std-name-hint.gperf"
        {"distance", "<iterator>", cxx98},
! #line 555 "std-name-hint.gperf"
        {"declval", "<utility>", cxx11},
  #line 254 "std-name-hint.gperf"
        {"scientific", "<ios>", cxx98},
  #line 98 "std-name-hint.gperf"
        {"strong_equality", "<compare>", cxx20},
! #line 485 "std-name-hint.gperf"
        {"u8string", "<string>", cxx20},
  #line 190 "std-name-hint.gperf"
        {"wformat_context", "<format>", cxx20},
  #line 312 "std-name-hint.gperf"
        {"destroy", "<memory>", cxx20},
! #line 557 "std-name-hint.gperf"
        {"forward", "<utility>", cxx11},
! #line 533 "std-name-hint.gperf"
        {"type_identity", "<type_traits>", cxx20},
! #line 462 "std-name-hint.gperf"
        {"stop_callback", "<stop_token>", cxx20},
  #line 86 "std-name-hint.gperf"
        {"chrono::tai_clock", "<chrono>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 1038,1044 ****
        {"chrono::tzdb", "<chrono>", cxx20},
  #line 126 "std-name-hint.gperf"
        {"totally_ordered_with", "<concepts>", cxx20},
! #line 525 "std-name-hint.gperf"
        {"disjunction", "<type_traits>", cxx17},
  #line 110 "std-name-hint.gperf"
        {"common_with", "<concepts>", cxx20},
--- 1034,1040 ----
        {"chrono::tzdb", "<chrono>", cxx20},
  #line 126 "std-name-hint.gperf"
        {"totally_ordered_with", "<concepts>", cxx20},
! #line 523 "std-name-hint.gperf"
        {"disjunction", "<type_traits>", cxx17},
  #line 110 "std-name-hint.gperf"
        {"common_with", "<concepts>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 1058,1080 ****
        {"weak_ordering", "<compare>", cxx20},
  #line 201 "std-name-hint.gperf"
        {"ifstream", "<fstream>", cxx98},
! #line 452 "std-name-hint.gperf"
        {"out_of_range", "<stdexcept>", cxx98},
  #line 264 "std-name-hint.gperf"
        {"clog", "<iostream>", cxx98},
  #line 62 "std-name-hint.gperf"
        {"chrono::file_clock", "<chrono>", cxx20},
! #line 526 "std-name-hint.gperf"
        {"disjunction_v", "<type_traits>", cxx17},
! #line 485 "std-name-hint.gperf"
        {"u16string", "<string>", cxx11},
  #line 351 "std-name-hint.gperf"
        {"once_flag", "<mutex>", cxx11},
! #line 491 "std-name-hint.gperf"
        {"string_view", "<string_view>", cxx17},
  #line 304 "std-name-hint.gperf"
        {"allocator_arg", "<memory>", cxx11},
! #line 486 "std-name-hint.gperf"
        {"u32string", "<string>", cxx11},
  #line 213 "std-name-hint.gperf"
        {"unwrap_ref_decay", "<functional>", cxx20},
--- 1054,1076 ----
        {"weak_ordering", "<compare>", cxx20},
  #line 201 "std-name-hint.gperf"
        {"ifstream", "<fstream>", cxx98},
! #line 450 "std-name-hint.gperf"
        {"out_of_range", "<stdexcept>", cxx98},
  #line 264 "std-name-hint.gperf"
        {"clog", "<iostream>", cxx98},
  #line 62 "std-name-hint.gperf"
        {"chrono::file_clock", "<chrono>", cxx20},
! #line 524 "std-name-hint.gperf"
        {"disjunction_v", "<type_traits>", cxx17},
! #line 483 "std-name-hint.gperf"
        {"u16string", "<string>", cxx11},
  #line 351 "std-name-hint.gperf"
        {"once_flag", "<mutex>", cxx11},
! #line 489 "std-name-hint.gperf"
        {"string_view", "<string_view>", cxx17},
  #line 304 "std-name-hint.gperf"
        {"allocator_arg", "<memory>", cxx11},
! #line 484 "std-name-hint.gperf"
        {"u32string", "<string>", cxx11},
  #line 213 "std-name-hint.gperf"
        {"unwrap_ref_decay", "<functional>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 1086,1096 ****
        {"derived_from", "<concepts>", cxx20},
  #line 99 "std-name-hint.gperf"
        {"strong_ordering", "<compare>", cxx20},
! #line 497 "std-name-hint.gperf"
        {"generic_category", "<system_error>", cxx11},
  #line 125 "std-name-hint.gperf"
        {"totally_ordered", "<concepts>", cxx20},
! #line 494 "std-name-hint.gperf"
        {"error_category", "<system_error>", cxx11},
  #line 82 "std-name-hint.gperf"
        {"chrono::round", "<chrono>", cxx17},
--- 1082,1092 ----
        {"derived_from", "<concepts>", cxx20},
  #line 99 "std-name-hint.gperf"
        {"strong_ordering", "<compare>", cxx20},
! #line 495 "std-name-hint.gperf"
        {"generic_category", "<system_error>", cxx11},
  #line 125 "std-name-hint.gperf"
        {"totally_ordered", "<concepts>", cxx20},
! #line 492 "std-name-hint.gperf"
        {"error_category", "<system_error>", cxx11},
  #line 82 "std-name-hint.gperf"
        {"chrono::round", "<chrono>", cxx17},
*************** std_name_hint_lookup::find (const char *
*** 1098,1112 ****
        {"unique_lock", "<mutex>", cxx11},
  #line 319 "std-name-hint.gperf"
        {"make_shared", "<memory>", cxx11},
! #line 507 "std-name-hint.gperf"
        {"this_thread", "<thread>", cxx11},
! #line 449 "std-name-hint.gperf"
        {"invalid_argument", "<stdexcept>", cxx98},
  #line 354 "std-name-hint.gperf"
        {"scoped_lock", "<mutex>", cxx17},
  #line 268 "std-name-hint.gperf"
        {"wclog", "<iostream>", cxx98},
! #line 506 "std-name-hint.gperf"
        {"jthread", "<thread>", cxx20},
  #line 97 "std-name-hint.gperf"
        {"partial_ordering", "<compare>", cxx20},
--- 1094,1108 ----
        {"unique_lock", "<mutex>", cxx11},
  #line 319 "std-name-hint.gperf"
        {"make_shared", "<memory>", cxx11},
! #line 505 "std-name-hint.gperf"
        {"this_thread", "<thread>", cxx11},
! #line 447 "std-name-hint.gperf"
        {"invalid_argument", "<stdexcept>", cxx98},
  #line 354 "std-name-hint.gperf"
        {"scoped_lock", "<mutex>", cxx17},
  #line 268 "std-name-hint.gperf"
        {"wclog", "<iostream>", cxx98},
! #line 504 "std-name-hint.gperf"
        {"jthread", "<thread>", cxx20},
  #line 97 "std-name-hint.gperf"
        {"partial_ordering", "<compare>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 1114,1120 ****
        {"chrono::high_resolution_clock", "<chrono>", cxx11},
  #line 307 "std-name-hint.gperf"
        {"assume_aligned", "<memory>", cxx20},
! #line 488 "std-name-hint.gperf"
        {"wstring", "<string>", cxx98},
  #line 192 "std-name-hint.gperf"
        {"wformat_string", "<format>", cxx20},
--- 1110,1116 ----
        {"chrono::high_resolution_clock", "<chrono>", cxx11},
  #line 307 "std-name-hint.gperf"
        {"assume_aligned", "<memory>", cxx20},
! #line 486 "std-name-hint.gperf"
        {"wstring", "<string>", cxx98},
  #line 192 "std-name-hint.gperf"
        {"wformat_string", "<format>", cxx20},
*************** std_name_hint_lookup::find (const char *
*** 1144,1150 ****
           -1,    -1,    24,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    25,    26,    27,    -1,
           -1,    -1,    28,    29,    -1,    -1,    30,
!        -630,  -457,    -2,    33,    -1,    34,    -1,
           35,    -1,    36,    -1,    -1,    -1,    -1,
           37,    -1,    38,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    39,    -1,    -1,    -1,
--- 1140,1146 ----
           -1,    -1,    24,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    25,    26,    27,    -1,
           -1,    -1,    28,    29,    -1,    -1,    30,
!        -628,  -455,    -2,    33,    -1,    34,    -1,
           35,    -1,    36,    -1,    -1,    -1,    -1,
           37,    -1,    38,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    39,    -1,    -1,    -1,
*************** std_name_hint_lookup::find (const char *
*** 1186,1193 ****
           -1,   152,   153,    -1,    -1,    -1,    -1,
           -1,    -1,   154,    -1,   155,   156,    -1,
           -1,    -1,   157,    -1,    -1,   158,    -1,
!         159,   160,    -1,    -1,    -1,  -934,    -1,
!         163,   164,    -1,   165,  -327,    -2,    -1,
           -1,   166,    -1,    -1,    -1,    -1,   167,
          168,    -1,   169,    -1,    -1,    -1,   170,
          171,   172,   173,    -1,    -1,    -1,   174,
--- 1182,1189 ----
           -1,   152,   153,    -1,    -1,    -1,    -1,
           -1,    -1,   154,    -1,   155,   156,    -1,
           -1,    -1,   157,    -1,    -1,   158,    -1,
!         159,   160,    -1,    -1,    -1,  -932,    -1,
!         163,   164,    -1,   165,  -325,    -2,    -1,
           -1,   166,    -1,    -1,    -1,    -1,   167,
          168,    -1,   169,    -1,    -1,    -1,   170,
          171,   172,   173,    -1,    -1,    -1,   174,
*************** std_name_hint_lookup::find (const char *
*** 1197,1353 ****
           -1,   185,    -1,   186,   187,    -1,   188,
          189,   190,   191,   192,    -1,   193,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   194,    -1, -1006,  -293,
           -2,    -1,    -1,    -1,   197,    -1,    -1,
          198,   199,   200,   201,    -1,    -1,    -1,
          202,   203,    -1,    -1,    -1,    -1,   204,
!          -1,    -1, -1031,  -283,    -2,    -1,   207,
!          -1,    -1,    -1,   208,   209,    -1,    -1,
!          -1,   210,    -1,    -1,    -1,   211,    -1,
!         212,    -1,    -1,   213,    -1,    -1,   214,
!          -1,   215,    -1,   216,   217,    -1,   218,
!          -1,    -1,   219,    -1,    -1,    -1,   220,
!          -1,   221,    -1,   222,   223,   224,    -1,
!          -1,    -1,   225,    -1,   226,    -1,    -1,
!          -1,    -1,   227,    -1,   228,    -1,    -1,
!          -1,   229,   230,    -1,    -1,    -1,    -1,
!          -1,   231,    -1,   232,   233,    -1,    -1,
!          -1,    -1,   234,    -1,   235,   236,   237,
!         238,    -1,   239,    -1,   240,   241,   242,
!         243,    -1,    -1,   244,    -1,   245,    -1,
!         246,   247,   248,    -1,    -1,    -1,   249,
!          -1,    -1,    -1,    -1,   250,   251,    -1,
!          -1,    -1,    -1,    -1,    -1,    -1,   252,
!         253,   254,   255,    -1,    -1,   256,   257,
!         258,    -1,   259,   260,    -1,    -1,    -1,
!         261,    -1,    -1,    -1,    -1,    -1,   262,
!         263,    -1,   264,   265,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   266,    -1,
!         267,    -1,   268,    -1,    -1,    -1,   269,
!          -1,   270,    -1,   271,    -1,    -1,   272,
!          -1,   273,    -1,    -1,    -1,    -1,   274,
!         275,   276,    -1,   277,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   278,    -1,
!          -1,    -1,    -1,    -1,   279,   280,   281,
!       -1226,   284,  -206,    -2,    -1,    -1,    -1,
!          -1,   285,    -1,    -1,    -1,    -1,   286,
!         287,   288,    -1,    -1,   289,   290,   291,
!          -1,    -1,    -1,    -1,   292,    -1,    -1,
!          -1,    -1,   293,    -1,    -1,   294,    -1,
!         295,   296,   297,   298,    -1,    -1,    -1,
!          -1,    -1,    -1,   299,    -1,    -1,    -1,
!          -1,    -1,    -1,   300,   301,   302,    -1,
!          -1,    -1,    -1,   303,   304,    -1,    -1,
!         305,   306,    -1,    -1,    -1,   307,    -1,
!          -1,    -1,    -1,    -1,   308,    -1,    -1,
!         309,   310,    -1,    -1,    -1,    -1,   311,
!          -1,    -1,   312,   313,   314,    -1,    -1,
!          -1,   315,   316,    -1,   317,    -1,   318,
!          -1,    -1,   319,   320,   321,   322,    -1,
!         323,    -1,   324,   325,    -1,    -1,    -1,
!         326,   327,    -1,   328,   329,    -1,   330,
!          -1,    -1,   331,    -1,   332,    -1,    -1,
!          -1,    -1,   333,   334,   335,    -1,    -1,
!          -1,   336,    -1,    -1,   337,   338,    -1,
!          -1,    -1,    -1, -1368,  -149,    -2,    -1,
!         341,    -1,    -1,    -1,    -1,    -1,    -1,
!         342,    -1,    -1,   343,    -1,    -1,    -1,
!          -1,   344,   345,    -1,   346,    -1,    -1,
!          -1,   347,    -1,    -1,   348,   349,    -1,
!          -1,    -1,    -1,    -1,   350,   351,    -1,
!         352,   353,    -1,    -1,    -1,    -1,   354,
!          -1,   355,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   356,    -1,   357,    -1,
!          -1,    -1,    -1,    -1,   358,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   359,    -1,
!         360,   361,    -1,   362,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   363,    -1,   364,
!          -1,   365,    -1,   366,    -1,    -1,    -1,
!         367,   368,   369,    -1,    -1,   370,    -1,
!          -1,    -1,    -1,   371,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         372,    -1,   373,    -1,    -1,    -1,   374,
!          -1,    -1,    -1,    -1,   375,    -1,   376,
!          -1,    -1,    -1,   377,    -1,    -1,    -1,
!         378,    -1,   379,   380,    -1,    -1,    -1,
!         381,    -1,   382,    -1,   383,   384,    -1,
!          -1,   385,    -1,    -1,    -1,    -1,    -1,
!         386,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   387,   388,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   389,   390,    -1,
           -1,    -1,    -1,    -1,    -1,   391,    -1,
!          -1,    -1,    -1,    -1,    -1,   392,    -1,
!          -1,    -1,    -1,    -1,   393,    -1,   394,
!          -1,    -1,    -1,    -1,    -1,    -1,   395,
!         396,   397,    -1,    -1,   398,   399,    -1,
!         400,   401,   402,   403,   404,   405,   406,
!         407,   408,   409,    -1,    -1,   410,   411,
!          -1,    -1,    -1,   412,    -1,    -1,    -1,
!          -1,   413,    -1,   414,    -1,    -1,   415,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   416,    -1,    -1,    -1,   417,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         418,    -1,    -1,   419,    -1,    -1,   420,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   421,   422,    -1,    -1,
           -1,    -1,    -1,    -1,   423,    -1,    -1,
-          -1,    -1,    -1,    -1,   424,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,   425,    -1,    -1,
!          -1,    -1,    -1,    -1, -1705,   -62,    -2,
!          -1,    -1,    -1,    -1,   428,    -1,    -1,
!          -1,    -1,    -1,   429,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   430,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         431,    -1,    -1,    -1,    -1,    -1,   432,
!          -1,    -1,    -1,    -1,   433,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   434,    -1,
!          -1,    -1,    -1,   435,    -1,    -1,   436,
!          -1,    -1,    -1,    -1,    -1,    -1,   437,
!         438,    -1,    -1,   439,    -1,    -1,    -1,
!          -1,    -1,   440,   441,    -1,    -1,    -1,
!         442,    -1,   443,    -1,   444,    -1,    -1,
!         445,    -1,    -1,    -1,   446,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,    -1,   447,
!          -1,   448,    -1,    -1,    -1,    -1,    -1,
!         449,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   450,    -1,   451,    -1,
!          -1,    -1,    -1,    -1,   452,    -1,    -1,
!          -1,    -1,    -1,   453,    -1,    -1,    -1,
!          -1,    -1,   454,    -1,    -1,   455,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   456,    -1,    -1,    -1,   457,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   458,    -1,   459,   460,
!          -1,    -1,    -1,    -1,    -1,    -1,   461,
           -1,    -1,    -1,    -1,   462,    -1,    -1,
!          -1,    -1,   463,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   464,    -1,    -1,
!          -1,    -1,    -1,   465,    -1,    -1,    -1,
!          -1,    -1,    -1,   466,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   467,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,   468,    -1,    -1,    -1,   469,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,    -1,   470,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
--- 1193,1349 ----
           -1,   185,    -1,   186,   187,    -1,   188,
          189,   190,   191,   192,    -1,   193,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   194,    -1, -1004,  -291,
           -2,    -1,    -1,    -1,   197,    -1,    -1,
          198,   199,   200,   201,    -1,    -1,    -1,
          202,   203,    -1,    -1,    -1,    -1,   204,
!          -1,    -1,   205,    -1,    -1,    -1,   206,
!          -1,    -1,    -1,   207,   208,    -1,    -1,
!          -1,   209,    -1,    -1,    -1,   210,    -1,
!         211,    -1,    -1,   212,    -1,    -1,   213,
!          -1,   214,    -1,   215,   216,    -1,   217,
!          -1,    -1,   218,    -1,    -1,    -1,   219,
!          -1,   220,    -1,   221,   222,   223,    -1,
!          -1,    -1,   224,    -1,   225,    -1,    -1,
!          -1,    -1,   226,    -1,   227,    -1,    -1,
!          -1,   228,   229,    -1,    -1,    -1,    -1,
!          -1,   230,    -1,   231,   232,    -1,    -1,
!          -1,    -1,   233,    -1,   234,   235,   236,
!         237,    -1,   238,    -1,   239,   240,   241,
!         242,    -1,    -1,   243,    -1,   244,    -1,
!         245,   246,   247,    -1,    -1,    -1,   248,
!          -1,    -1,    -1,    -1,   249,   250,    -1,
!          -1,    -1,    -1,    -1,    -1,    -1,   251,
!         252,   253,   254,    -1,    -1,   255,   256,
!         257,    -1,   258,   259,    -1,    -1,    -1,
!         260,    -1,    -1,    -1,    -1,    -1,   261,
!         262,    -1,   263,   264,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   265,    -1,
!         266,    -1,   267,    -1,    -1,    -1,   268,
!          -1,   269,    -1,   270,    -1,    -1,   271,
!          -1,   272,    -1,    -1,    -1,    -1,   273,
!         274,   275,    -1,   276,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   277,    -1,
!          -1,    -1,    -1,    -1,   278,   279,   280,
!       -1224,   283,  -205,    -2,    -1,    -1,    -1,
!          -1,   284,    -1,    -1,    -1,    -1,   285,
!         286,   287,    -1,    -1,   288,   289,   290,
!          -1,    -1,    -1,    -1,   291,    -1,    -1,
!          -1,    -1,   292,    -1,    -1,   293,    -1,
!         294,   295,   296,   297,    -1,    -1,    -1,
!          -1,    -1,    -1,   298,    -1,    -1,    -1,
!          -1,    -1,    -1,   299,   300,   301,    -1,
!          -1,    -1,    -1,   302,   303,    -1,    -1,
!         304,   305,    -1,    -1,    -1,   306,    -1,
!          -1,    -1,    -1,    -1,   307,    -1,    -1,
!         308,   309,    -1,    -1,    -1,    -1,   310,
!          -1,    -1,   311,   312,   313,    -1,    -1,
!          -1,   314,   315,    -1,   316,    -1,   317,
!          -1,    -1,   318,   319,   320,   321,    -1,
!         322,    -1,   323,   324,    -1,    -1,    -1,
!         325,   326,    -1,   327,   328,    -1,   329,
!          -1,    -1,   330,    -1,   331,    -1,    -1,
!          -1,    -1,   332,   333,   334,    -1,    -1,
!          -1,   335,    -1,    -1,   336,   337,    -1,
!          -1,    -1,    -1, -1366,  -148,    -2,    -1,
!         340,    -1,    -1,    -1,    -1,    -1,    -1,
!         341,    -1,    -1,   342,    -1,    -1,    -1,
!          -1,   343,   344,    -1,   345,    -1,    -1,
!          -1,   346,    -1,    -1,   347,   348,    -1,
!          -1,    -1,    -1,    -1,   349,   350,    -1,
!         351,   352,    -1,    -1,    -1,    -1,   353,
!          -1,   354,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   355,    -1,   356,    -1,
!          -1,    -1,    -1,    -1,   357,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   358,    -1,
!         359,   360,    -1,   361,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   362,    -1,   363,
!          -1,   364,    -1,   365,    -1,    -1,    -1,
!         366,   367,   368,    -1,    -1,   369,    -1,
!          -1,    -1,    -1,   370,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         371,    -1,   372,    -1,    -1,    -1,   373,
!          -1,    -1,    -1,    -1,   374,    -1,   375,
!          -1,    -1,    -1,   376,    -1,    -1,    -1,
!         377,    -1,   378,   379,    -1,    -1,    -1,
!         380,    -1,   381,    -1,   382,   383,    -1,
!          -1,   384,    -1,    -1,    -1,    -1,    -1,
!         385,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   386,   387,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   388,   389,    -1,
!          -1,    -1,    -1,    -1,    -1,   390,    -1,
           -1,    -1,    -1,    -1,    -1,   391,    -1,
!          -1,    -1,    -1,    -1,   392,    -1,   393,
!          -1,    -1,    -1,    -1,    -1,    -1,   394,
!         395,   396,    -1,    -1,   397,   398,    -1,
!         399,   400,   401,   402,   403,   404,   405,
!         406,   407,   408,    -1,    -1,   409,   410,
!          -1,    -1,    -1,   411,    -1,    -1,    -1,
!          -1,   412,    -1,   413,    -1,    -1,   414,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   415,    -1,    -1,    -1,   416,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         417,    -1,    -1,   418,    -1,    -1,   419,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   420,   421,    -1,    -1,
!          -1,    -1,    -1,    -1,   422,    -1,    -1,
           -1,    -1,    -1,    -1,   423,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
+          -1,    -1,    -1,    -1,   424,    -1,    -1,
           -1,    -1,    -1,    -1,   425,    -1,    -1,
!          -1,    -1,    -1,    -1,   426,    -1,    -1,
!          -1,    -1,    -1,   427,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   428,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         429,    -1,    -1,    -1,    -1,    -1,   430,
!          -1,    -1,    -1,    -1,   431,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   432,    -1,
!          -1,    -1,    -1,   433,    -1,    -1,   434,
!          -1,    -1,    -1,    -1,    -1,    -1,   435,
!         436,    -1,    -1,   437,    -1,    -1,    -1,
!          -1,    -1,   438,   439,    -1,    -1,    -1,
!         440,    -1,   441,    -1,   442,    -1,    -1,
!         443,    -1,    -1,    -1,   444,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,    -1,   445,
!          -1,   446,    -1,    -1,    -1,    -1,    -1,
!         447,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   448,    -1,   449,    -1,
!          -1,    -1,    -1,    -1,   450,    -1,    -1,
!          -1,    -1,    -1,   451,    -1,    -1,    -1,
!          -1,    -1,   452,    -1,    -1,   453,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   454,    -1,    -1,    -1,   455,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   456,    -1,   457,   458,
!          -1,    -1,    -1,    -1,    -1,    -1,   459,
!          -1,    -1,    -1,    -1,   460,    -1,    -1,
!          -1,    -1,   461,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,   462,    -1,    -1,
!          -1,    -1,    -1,   463,    -1,    -1,    -1,
!          -1,    -1,    -1,   464,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   465,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,   466,    -1,    -1,    -1,   467,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,    -1,   468,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
*************** std_name_hint_lookup::find (const char *
*** 1356,1377 ****
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   471,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   472,    -1,   473,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,   474,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   475,    -1,
!          -1,   476,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         477,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
--- 1352,1373 ----
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   469,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   470,    -1,   471,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,   472,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   473,    -1,
!          -1,   474,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         475,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
*************** std_name_hint_lookup::find (const char *
*** 1382,1395 ****
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   478,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   479,   480,   481,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   482,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
--- 1378,1391 ----
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,   476,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   477,   478,   479,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   480,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
*************** std_name_hint_lookup::find (const char *
*** 1404,1415 ****
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   483,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   484,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
--- 1400,1411 ----
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,   481,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,   482,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
*************** std_name_hint_lookup::find (const char *
*** 1417,1428 ****
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   485,    -1,
!          -1,    -1,    -1,    -1,    -1,   486,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         487
      };
  
    if (len <= MAX_WORD_LENGTH && len >= MIN_WORD_LENGTH)
--- 1413,1424 ----
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!          -1,    -1,    -1,    -1,    -1,   483,    -1,
!          -1,    -1,    -1,    -1,    -1,   484,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
           -1,    -1,    -1,    -1,    -1,    -1,    -1,
!         485
      };
  
    if (len <= MAX_WORD_LENGTH && len >= MIN_WORD_LENGTH)
diff -Nrcpad gcc-16-20251026/gcc/doc/extend.texi gcc-16-20251102/gcc/doc/extend.texi
*** gcc-16-20251026/gcc/doc/extend.texi	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/doc/extend.texi	Sun Nov  2 22:32:20 2025
*************** such an initializer, as shown here:
*** 1131,1136 ****
--- 1131,1144 ----
  char **foo = (char *[]) @{ "x", "y", "z" @};
  @end smallexample
  
+ As a GNU extension, GCC allows compound literals with a variable size.
+ In this case, only empty initialization is allowed.
+ 
+ @smallexample
+ int n = 4;
+ char (*p)[n] = &(char[n])@{ @};
+ @end smallexample
+ 
  Compound literals for scalar types and union types are also allowed.  In
  the following example the variable @code{i} is initialized to the value
  @code{2}, the result of incrementing the unnamed object created by
*************** the attribute.
*** 7311,7321 ****
  When the field that represents the number of the elements is assigned a
  negative integer value, the compiler treats the value as zero.
  
! The @code{counted_by} attribute is not allowed for a pointer to @code{void},
! a pointer to function, or a pointer to a structure or union that includes
! a flexible array member.  However, it is allowed for a pointer to
! non-void incomplete structure or union types, as long as the type could
! be completed before the first reference to the pointer.
  
  An explicit @code{counted_by} annotation defines a relationship between
  two objects, @code{p->array} and @code{p->count}, and there are the
--- 7319,7334 ----
  When the field that represents the number of the elements is assigned a
  negative integer value, the compiler treats the value as zero.
  
! The @code{counted_by} attribute is not allowed for a pointer to function,
! or a pointer to a structure or union that includes a flexible array member.
! However, it is allowed for a pointer to non-void incomplete structure
! or union types, as long as the type could be completed before the first
! reference to the pointer.
! 
! The attribute is allowed for a pointer to @code{void}.  However,
! warnings will be issued for such cases when @option{-Wpointer-arith} is
! specified.  When this attribute is applied on a pointer to @code{void},
! the size of each element of this pointer array is treated as 1.
  
  An explicit @code{counted_by} annotation defines a relationship between
  two objects, @code{p->array} and @code{p->count}, and there are the
diff -Nrcpad gcc-16-20251026/gcc/doc/invoke.texi gcc-16-20251102/gcc/doc/invoke.texi
*** gcc-16-20251026/gcc/doc/invoke.texi	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/doc/invoke.texi	Sun Nov  2 22:32:20 2025
*************** Objective-C and Objective-C++ Dialects}.
*** 1097,1103 ****
  -mfpu=@var{fpu-type} -msimd=@var{simd-type}
  -msoft-float -msingle-float -mdouble-float -mlsx -mno-lsx -mlasx -mno-lasx
  -mbranch-cost=@var{n} -maddr-reg-reg-cost=@var{n}  -mcheck-zero-division
! -mno-check-zero-division
  -mcond-move-int  -mno-cond-move-int
  -mcond-move-float  -mno-cond-move-float
  -memcpy  -mno-memcpy -mstrict-align -mno-strict-align -G @var{num}
--- 1097,1103 ----
  -mfpu=@var{fpu-type} -msimd=@var{simd-type}
  -msoft-float -msingle-float -mdouble-float -mlsx -mno-lsx -mlasx -mno-lasx
  -mbranch-cost=@var{n} -maddr-reg-reg-cost=@var{n}  -mcheck-zero-division
! -mno-check-zero-division -mbreak-code=@var{code}
  -mcond-move-int  -mno-cond-move-int
  -mcond-move-float  -mno-cond-move-float
  -memcpy  -mno-memcpy -mstrict-align -mno-strict-align -G @var{num}
*************** Trap (do not trap) on integer division b
*** 28457,28462 ****
--- 28457,28473 ----
  @option{-mcheck-zero-division} for @option{-O0} or @option{-Og}, and
  @option{-mno-check-zero-division} for other optimization levels.
  
+ @opindex mbreak-code
+ @item -mbreak-code=@var{code}
+ Emit a @code{break} @var{code} instruction for irrecoverable traps
+ from @code{__builtin_trap} or inserted by the compiler (for example
+ an erroneous path isolated with
+ @option{-fisolate-erroneous-paths-dereference}), or an
+ @code{amswap.w $r0, $r1, $r0} instruction which will cause the hardware
+ to trigger an Instruction Not-defined Exception if @var{code} is negative
+ or greater than 32767.  The default is -1, meaning to use the
+ @code{amswap.w} instruction.
+ 
  @opindex mcond-move-int
  @item -mcond-move-int
  @itemx -mno-cond-move-int
diff -Nrcpad gcc-16-20251026/gcc/doc/tree-ssa.texi gcc-16-20251102/gcc/doc/tree-ssa.texi
*** gcc-16-20251026/gcc/doc/tree-ssa.texi	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/doc/tree-ssa.texi	Sun Nov  2 22:32:20 2025
*************** FOR_EACH_PHI_OR_STMT_DEF (def_operand_p,
*** 355,361 ****
  
  Immediate use information is now always available.  Using the immediate use
  iterators, you may examine every use of any @code{SSA_NAME}. For instance,
! to change each use of @code{ssa_var} to @code{ssa_var2} and call fold_stmt on
  each stmt after that is done:
  
  @smallexample
--- 355,361 ----
  
  Immediate use information is now always available.  Using the immediate use
  iterators, you may examine every use of any @code{SSA_NAME}. For instance,
! to change each use of @code{ssa_var} to @code{val} and call fold_stmt on
  each stmt after that is done:
  
  @smallexample
*************** each stmt after that is done:
*** 367,374 ****
    FOR_EACH_IMM_USE_STMT (stmt, iterator, ssa_var)
      @{
        FOR_EACH_IMM_USE_ON_STMT (imm_use_p, iterator)
!         SET_USE (imm_use_p, ssa_var_2);
        fold_stmt (stmt);
      @}
  @end smallexample
  
--- 367,375 ----
    FOR_EACH_IMM_USE_STMT (stmt, iterator, ssa_var)
      @{
        FOR_EACH_IMM_USE_ON_STMT (imm_use_p, iterator)
!         SET_USE (imm_use_p, val);
        fold_stmt (stmt);
+       update_stmt (stmt);
      @}
  @end smallexample
  
*************** terminated early; a destructor takes car
*** 389,397 ****
  @code{FOR_EACH_IMM_USE_STMT} scope.
  
  There are checks in @code{verify_ssa} which verify that the immediate use list
! is up to date, as well as checking that an optimization didn't break from the
! loop without using this macro.  It is safe to simply 'break'; from a
! @code{FOR_EACH_IMM_USE_FAST} traverse.
  
  Some useful functions and macros:
  @enumerate
--- 390,396 ----
  @code{FOR_EACH_IMM_USE_STMT} scope.
  
  There are checks in @code{verify_ssa} which verify that the immediate use list
! is up to date.
  
  Some useful functions and macros:
  @enumerate
*************** isn't located in a @code{PHI} node.
*** 412,418 ****
  @end enumerate
  
  Note that uses are not put into an immediate use list until their statement is
! actually inserted into the instruction stream via a @code{bsi_*} routine.
  
  It is also still possible to utilize lazy updating of statements, but this
  should be used only when absolutely required.  Both alias analysis and the
--- 411,419 ----
  @end enumerate
  
  Note that uses are not put into an immediate use list until their statement is
! actually inserted into the instruction stream via a @code{gsi_*} routine
! which calls @code{update_stmt} to re-scan SSA operands and update the
! immediate use lists.
  
  It is also still possible to utilize lazy updating of statements, but this
  should be used only when absolutely required.  Both alias analysis and the
diff -Nrcpad gcc-16-20251026/gcc/dwarf2out.cc gcc-16-20251102/gcc/dwarf2out.cc
*** gcc-16-20251026/gcc/dwarf2out.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/dwarf2out.cc	Sun Nov  2 22:32:20 2025
*************** gen_btf_tag_dies (tree attr, dw_die_ref
*** 13842,13855 ****
  
    if (die)
      {
!       /* Add AT_GNU_annotation referring to the annotation DIE.
! 	 It may have already been added, some global declarations are processed
! 	 twice, but if so it must be the same or we have a bug.  */
!       dw_die_ref existing = get_AT_ref (die, DW_AT_GNU_annotation);
!       if (existing)
! 	gcc_checking_assert (existing == tag_die);
!       else
! 	add_AT_die_ref (die, DW_AT_GNU_annotation, tag_die);
      }
  
    return tag_die;
--- 13842,13855 ----
  
    if (die)
      {
!       /* Add (or replace) AT_GNU_annotation referring to the annotation DIE.
! 	 Replacement may happen for example when 'die' is a global variable
! 	 which has been re-declared multiple times.  In any case, the set of
! 	 input attributes is the one that ought to be reflected.  For global
! 	 variable re-declarations which add additional decl tags, they will
! 	 have been accumulated in the variable's DECL_ATTRIBUTES for us.  */
!       remove_AT (die, DW_AT_GNU_annotation);
!       add_AT_die_ref (die, DW_AT_GNU_annotation, tag_die);
      }
  
    return tag_die;
diff -Nrcpad gcc-16-20251026/gcc/expr.cc gcc-16-20251102/gcc/expr.cc
*** gcc-16-20251026/gcc/expr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/expr.cc	Sun Nov  2 22:32:20 2025
*************** expand_expr_divmod (tree_code code, mach
*** 9802,9807 ****
--- 9802,9830 ----
    return expand_divmod (mod_p, code, mode, op0, op1, target, unsignedp);
  }
  
+ /* Return true if EXP has a range of values [0..1], false
+    otherwise. This works for constants and ssa names, calling back into the ranger.  */
+ static bool
+ expr_has_boolean_range (tree exp, gimple *stmt)
+ {
+   /* An integral type with a single bit of precision.  */
+   if (INTEGRAL_TYPE_P (TREE_TYPE (exp))
+       && TYPE_UNSIGNED (TREE_TYPE (exp))
+       && TYPE_PRECISION (TREE_TYPE (exp)) == 1)
+     return true;
+ 
+   /* Signed 1 bit integers are not boolean ranges. */
+   if (!INTEGRAL_TYPE_P (TREE_TYPE (exp))
+       || TYPE_PRECISION (TREE_TYPE (exp)) <= 1)
+     return false;
+ 
+   if (TREE_CODE (exp) == SSA_NAME)
+     return ssa_name_has_boolean_range (exp, stmt);
+   if (TREE_CODE (exp) == INTEGER_CST)
+     return wi::leu_p (wi::to_wide (exp), 1);
+   return false;
+ }
+ 
  rtx
  expand_expr_real_2 (const_sepops ops, rtx target, machine_mode tmode,
  		    enum expand_modifier modifier)
*************** expand_expr_real_2 (const_sepops ops, rt
*** 10460,10468 ****
        /* Expand X*Y as X&-Y when Y must be zero or one.  */
        if (SCALAR_INT_MODE_P (mode))
  	{
! 	  bool gimple_zero_one_valued_p (tree, tree (*)(tree));
! 	  bool bit0_p = gimple_zero_one_valued_p (treeop0, nullptr);
! 	  bool bit1_p = gimple_zero_one_valued_p (treeop1, nullptr);
  
  	  /* Expand X*Y as X&Y when both X and Y must be zero or one.  */
  	  if (bit0_p && bit1_p)
--- 10483,10490 ----
        /* Expand X*Y as X&-Y when Y must be zero or one.  */
        if (SCALAR_INT_MODE_P (mode))
  	{
! 	  bool bit0_p = expr_has_boolean_range (treeop0, currently_expanding_gimple_stmt);
! 	  bool bit1_p = expr_has_boolean_range (treeop1, currently_expanding_gimple_stmt);
  
  	  /* Expand X*Y as X&Y when both X and Y must be zero or one.  */
  	  if (bit0_p && bit1_p)
diff -Nrcpad gcc-16-20251026/gcc/fold-const-call.cc gcc-16-20251102/gcc/fold-const-call.cc
*** gcc-16-20251026/gcc/fold-const-call.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fold-const-call.cc	Sun Nov  2 22:32:20 2025
*************** fold_const_fold_left (tree type, tree ar
*** 1440,1445 ****
--- 1440,1464 ----
    return arg0;
  }
  
+ /* Fold a call to IFN_VEC_SHL_INSERT (ARG0, ARG1), returning a value
+    of type TYPE.  */
+ 
+ static tree
+ fold_const_vec_shl_insert (tree, tree arg0, tree arg1)
+ {
+   if (TREE_CODE (arg0) != VECTOR_CST)
+     return NULL_TREE;
+ 
+   /* vec_shl_insert ( dup(CST), CST) -> dup (CST). */
+   if (tree elem = uniform_vector_p (arg0))
+     {
+       if (operand_equal_p (elem, arg1))
+ 	return arg0;
+     }
+ 
+   return NULL_TREE;
+ }
+ 
  /* Try to evaluate:
  
        *RESULT = FN (*ARG0, *ARG1)
*************** fold_const_call (combined_fn fn, tree ty
*** 1843,1848 ****
--- 1862,1870 ----
      case CFN_FOLD_LEFT_PLUS:
        return fold_const_fold_left (type, arg0, arg1, PLUS_EXPR);
  
+     case CFN_VEC_SHL_INSERT:
+       return fold_const_vec_shl_insert (type, arg0, arg1);
+ 
      case CFN_UBSAN_CHECK_ADD:
      case CFN_ADD_OVERFLOW:
        subcode = PLUS_EXPR;
diff -Nrcpad gcc-16-20251026/gcc/fold-const.cc gcc-16-20251102/gcc/fold-const.cc
*** gcc-16-20251026/gcc/fold-const.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fold-const.cc	Sun Nov  2 22:32:20 2025
*************** protected_set_expr_location_unshare (tre
*** 264,285 ****
    return x;
  }
  
- /* If ARG2 divides ARG1 with zero remainder, carries out the exact
-    division and returns the quotient.  Otherwise returns
-    NULL_TREE.  */
- 
- tree
- div_if_zero_remainder (const_tree arg1, const_tree arg2)
- {
-   widest_int quo;
- 
-   if (wi::multiple_of_p (wi::to_widest (arg1), wi::to_widest (arg2),
- 			 SIGNED, &quo))
-     return wide_int_to_tree (TREE_TYPE (arg1), quo);
- 
-   return NULL_TREE;
- }
- 
  /* This is nonzero if we should defer warnings about undefined
     overflow.  This facility exists because these warnings are a
     special case.  The code to estimate loop iterations does not want
--- 264,269 ----
diff -Nrcpad gcc-16-20251026/gcc/fold-const.h gcc-16-20251102/gcc/fold-const.h
*** gcc-16-20251026/gcc/fold-const.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fold-const.h	Sun Nov  2 22:32:20 2025
*************** extern tree build_simple_mem_ref_loc (lo
*** 153,159 ****
  extern poly_offset_int mem_ref_offset (const_tree);
  extern tree build_invariant_address (tree, tree, poly_int64);
  extern tree constant_boolean_node (bool, tree);
- extern tree div_if_zero_remainder (const_tree, const_tree);
  
  extern bool tree_swap_operands_p (const_tree, const_tree);
  extern enum tree_code swap_tree_comparison (enum tree_code);
--- 153,158 ----
diff -Nrcpad gcc-16-20251026/gcc/fortran/ChangeLog gcc-16-20251102/gcc/fortran/ChangeLog
*** gcc-16-20251026/gcc/fortran/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/ChangeLog	Sun Nov  2 22:32:21 2025
***************
*** 1,3 ****
--- 1,95 ----
+ 2025-11-01  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/78640
+ 	* resolve.cc (resolve_fl_procedure): Check function result of a
+ 	pure function against F2018:C1585.
+ 
+ 2025-10-31  Yuao Ma  <c8ef@outlook.com>
+ 
+ 	* intrinsic.texi: Fix typo.
+ 	* trans-intrinsic.cc (conv_intrinsic_atomic_cas): Remove unreachable
+ 	code.
+ 
+ 2025-10-31  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122452
+ 	* primary.cc (gfc_match_rvalue): Give priority to specific
+ 	procedures in a generic interface with the same name as a
+ 	PDT template. If found, use as the procedure instead of the
+ 	constructor generated from the PDT template.
+ 
+ 2025-10-30  Mikael Morin  <mikael@gcc.gnu.org>
+ 
+ 	* trans-array.cc: Cleanup obsolete comment.
+ 
+ 2025-10-29  Yuao Ma  <c8ef@outlook.com>
+ 
+ 	* trans-expr.cc (gfc_conv_gfc_desc_to_cfi_desc): Remove unreachable
+ 	code.
+ 
+ 2025-10-29  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122165
+ 	* primary.cc (gfc_match_varspec): If the previous component ref
+ 	was a type specification parameter, a type inquiry ref cannot
+ 	follow.
+ 
+ 2025-10-29  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122433
+ 	PR fortran/122434
+ 	* decl.cc (gfc_get_pdt_instance): Prevent a PDT component of
+ 	the same type as the template from being converted into an
+ 	instance.
+ 	* resolve.cc (gfc_impure_variable): The result of a pure
+ 	function is a valid allocate object since it is pure.
+ 
+ 2025-10-28  Yuao Ma  <c8ef@outlook.com>
+ 
+ 	PR fortran/122342
+ 	* trans-const.cc (gfc_conv_constant): Create a variable for the
+ 	non-char pointer.
+ 
+ 2025-10-28  Paul-Antoine Arras  <parras@baylibre.com>
+ 
+ 	PR fortran/122439
+ 	* openmp.cc (gfc_resolve_omp_context_selector): Skip selectors that have
+ 	OMP_TRAIT_INVALID.
+ 
+ 2025-10-27  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/922290
+ 	PR fortran/95541
+ 	* resolve.cc (resolve_typebound_intrinsic_op): Add pdt_template
+ 	to the list of preemted specifics.
+ 	* trans-stmt.cc (trans_associate_var): PDT array and string
+ 	components are separately allocated for each element of a PDT
+ 	array, so copy in and copy out the selector expression.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/122325
+ 	* options.cc (gfc_init_options_struct): Set flag_complex_method
+ 	to fortran rules.
+ 
+ 2025-10-26  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122290
+ 	* decl.cc (variable_decl): Matching component initializer
+ 	expressions in PDT templates should be done with gfc_match_expr
+ 	to avoid reduction too early. If the expression type is unknown
+ 	copy the component typespec.
+ 	(gfc_get_pdt_instance): Change comment from a TODO to an
+ 	explanation. Insert parameter values in initializers. For
+ 	components that are not marked with PDT attributes, do the
+ 	full reduction for init expressions.
+ 	* primary.cc (gfc_match_actual_arglist): Convert PDT kind exprs
+ 	using the component initializer.
+ 	* resolve.cc (resolve_typebound_intrinsic_op): Preempt
+ 	gfc_check_new_interface for pdt_types as well as entities used
+ 	in submodules.
+ 	* simplify.cc (get_kind): Remove PDT kind conversion.
+ 
  2025-10-25  Harald Anlauf  <anlauf@gmx.de>
  
  	PR fortran/114023
diff -Nrcpad gcc-16-20251026/gcc/fortran/decl.cc gcc-16-20251102/gcc/fortran/decl.cc
*** gcc-16-20251026/gcc/fortran/decl.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/decl.cc	Sun Nov  2 22:32:21 2025
*************** gfc_get_pdt_instance (gfc_actual_arglist
*** 3938,3943 ****
--- 3938,3957 ----
    actual_param = param_list;
    sprintf (name, "Pdt%s", pdt->name);
  
+   /* Prevent a PDT component of the same type as the template from being
+      converted into an instance. Doing this results in the component being
+      lost.  */
+   if (gfc_current_state () == COMP_DERIVED
+       && !(gfc_state_stack->previous
+ 	   && gfc_state_stack->previous->state == COMP_DERIVED)
+       && gfc_current_block ()->attr.pdt_template
+       && !strcmp (gfc_current_block ()->name, (*sym)->name))
+     {
+       if (ext_param_list)
+ 	*ext_param_list = gfc_copy_actual_arglist (param_list);
+       return MATCH_YES;
+     }
+ 
    /* Run through the parameter name list and pick up the actual
       parameter values or use the default values in the PDT declaration.  */
    for (; type_param_name_list;
diff -Nrcpad gcc-16-20251026/gcc/fortran/intrinsic.texi gcc-16-20251102/gcc/fortran/intrinsic.texi
*** gcc-16-20251026/gcc/fortran/intrinsic.texi	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/intrinsic.texi	Sun Nov  2 22:32:21 2025
*************** is different, the value is converted to
*** 2239,2245 ****
  program atomic
    use iso_fortran_env
    logical(atomic_logical_kind) :: atom[*], prev
!   call atomic_cas (atom[1], prev, .false., .true.))
  end program atomic
  @end smallexample
  
--- 2239,2245 ----
  program atomic
    use iso_fortran_env
    logical(atomic_logical_kind) :: atom[*], prev
!   call atomic_cas (atom[1], prev, .false., .true.)
  end program atomic
  @end smallexample
  
diff -Nrcpad gcc-16-20251026/gcc/fortran/openmp.cc gcc-16-20251102/gcc/fortran/openmp.cc
*** gcc-16-20251026/gcc/fortran/openmp.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/openmp.cc	Sun Nov  2 22:32:21 2025
*************** gfc_resolve_omp_context_selector (gfc_om
*** 12236,12241 ****
--- 12236,12243 ----
  	      }
  	  }
  
+ 	if (os->code == OMP_TRAIT_INVALID)
+ 	  break;
  	enum omp_tp_type property_kind = omp_ts_map[os->code].tp_type;
  	gfc_omp_trait_property *otp = os->properties;
  
diff -Nrcpad gcc-16-20251026/gcc/fortran/options.cc gcc-16-20251102/gcc/fortran/options.cc
*** gcc-16-20251026/gcc/fortran/options.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/options.cc	Sun Nov  2 22:32:21 2025
*************** gfc_init_options_struct (struct gcc_opti
*** 133,138 ****
--- 133,139 ----
    opts->frontend_set_flag_errno_math = true;
    opts->x_flag_associative_math = -1;
    opts->frontend_set_flag_associative_math = true;
+   opts->x_flag_complex_method = 1;
  }
  
  /* Get ready for options handling. Keep in sync with
diff -Nrcpad gcc-16-20251026/gcc/fortran/primary.cc gcc-16-20251102/gcc/fortran/primary.cc
*** gcc-16-20251026/gcc/fortran/primary.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/primary.cc	Sun Nov  2 22:32:21 2025
*************** gfc_match_varspec (gfc_expr *primary, in
*** 2690,2695 ****
--- 2690,2703 ----
        else
  	component = NULL;
  
+       if (previous && inquiry
+ 	  && (previous->attr.pdt_kind || previous->attr.pdt_len))
+ 	{
+ 	  gfc_error_now ("R901: A type parameter ref is not a designtor and "
+ 		     "cannot be followed by the type inquiry ref at %C");
+ 	  return MATCH_ERROR;
+ 	}
+ 
        if (intrinsic && !inquiry)
  	{
  	  if (previous)
*************** gfc_match_rvalue (gfc_expr **result)
*** 3827,3832 ****
--- 3835,3843 ----
    gfc_typespec *ts;
    bool implicit_char;
    gfc_ref *ref;
+   gfc_symtree *pdt_st;
+   gfc_symbol *found_specific = NULL;
+ 
  
    m = gfc_match ("%%loc");
    if (m == MATCH_YES)
*************** gfc_match_rvalue (gfc_expr **result)
*** 4074,4095 ****
  	  break;
  	}
  
        /* Check to see if this is a PDT constructor.  The format of these
  	 constructors is rather unusual:
  		name [(type_params)](component_values)
  	 where, component_values excludes the type_params. With the present
  	 gfortran representation this is rather awkward because the two are not
  	 distinguished, other than by their attributes.  */
!       if (sym->attr.generic)
  	{
- 	  gfc_symtree *pdt_st;
  	  gfc_symbol *pdt_sym;
  	  gfc_actual_arglist *ctr_arglist = NULL, *tmp;
  	  gfc_component *c;
  
! 	  /* Obtain the template.  */
! 	  gfc_find_sym_tree (gfc_dt_upper_string (name), NULL, 1, &pdt_st);
! 	  if (pdt_st && pdt_st->n.sym && pdt_st->n.sym->attr.pdt_template)
  	    {
  	      bool type_spec_list = false;
  	      pdt_sym = pdt_st->n.sym;
--- 4085,4120 ----
  	  break;
  	}
  
+       gfc_gobble_whitespace ();
+       found_specific = NULL;
+ 
+       /* Even if 'name' is that of a PDT template, priority has to be given to
+ 	 possible specific procedures in the generic interface.  */
+       gfc_find_sym_tree (gfc_dt_upper_string (name), NULL, 1, &pdt_st);
+       if (sym->generic && sym->generic->next
+ 	  && gfc_peek_ascii_char() != '(')
+ 	{
+ 	  gfc_actual_arglist *arg = actual_arglist;
+ 	  for (; arg && pdt_st; arg = arg->next)
+ 	    gfc_resolve_expr (arg->expr);
+ 	  found_specific = gfc_search_interface (sym->generic, 0,
+ 						 &actual_arglist);
+ 	}
+ 
        /* Check to see if this is a PDT constructor.  The format of these
  	 constructors is rather unusual:
  		name [(type_params)](component_values)
  	 where, component_values excludes the type_params. With the present
  	 gfortran representation this is rather awkward because the two are not
  	 distinguished, other than by their attributes.  */
!       if (sym->attr.generic && pdt_st != NULL && found_specific == NULL)
  	{
  	  gfc_symbol *pdt_sym;
  	  gfc_actual_arglist *ctr_arglist = NULL, *tmp;
  	  gfc_component *c;
  
! 	  /* Use the template.  */
! 	  if (pdt_st->n.sym && pdt_st->n.sym->attr.pdt_template)
  	    {
  	      bool type_spec_list = false;
  	      pdt_sym = pdt_st->n.sym;
*************** gfc_match_rvalue (gfc_expr **result)
*** 4147,4154 ****
  		  tmp = tmp->next;
  		}
  
! 	      gfc_find_sym_tree (gfc_dt_lower_string (pdt_sym->name),
! 				 NULL, 1, &symtree);
  	      if (!symtree)
  		{
  		  gfc_get_ha_sym_tree (gfc_dt_lower_string (pdt_sym->name) ,
--- 4172,4183 ----
  		  tmp = tmp->next;
  		}
  
! 	      if (found_specific)
! 		gfc_find_sym_tree (found_specific->name,
! 				   NULL, 1, &symtree);
! 	      else
! 		gfc_find_sym_tree (gfc_dt_lower_string (pdt_sym->name),
! 				   NULL, 1, &symtree);
  	      if (!symtree)
  		{
  		  gfc_get_ha_sym_tree (gfc_dt_lower_string (pdt_sym->name) ,
diff -Nrcpad gcc-16-20251026/gcc/fortran/resolve.cc gcc-16-20251102/gcc/fortran/resolve.cc
*** gcc-16-20251026/gcc/fortran/resolve.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/resolve.cc	Sun Nov  2 22:32:21 2025
*************** resolve_fl_procedure (gfc_symbol *sym, i
*** 15385,15390 ****
--- 15385,15423 ----
        return false;
      }
  
+   /* F2018:C1585: "The function result of a pure function shall not be both
+      polymorphic and allocatable, or have a polymorphic allocatable ultimate
+      component."  */
+   if (sym->attr.pure && sym->result && sym->ts.u.derived)
+     {
+       if (sym->ts.type == BT_CLASS
+ 	  && sym->attr.class_ok
+ 	  && CLASS_DATA (sym->result)
+ 	  && CLASS_DATA (sym->result)->attr.allocatable)
+ 	{
+ 	  gfc_error ("Result variable %qs of pure function at %L is "
+ 		     "polymorphic allocatable",
+ 		     sym->result->name, &sym->result->declared_at);
+ 	  return false;
+ 	}
+ 
+       if (sym->ts.type == BT_DERIVED && sym->ts.u.derived->components)
+ 	{
+ 	  gfc_component *c = sym->ts.u.derived->components;
+ 	  for (; c; c = c->next)
+ 	    if (c->ts.type == BT_CLASS
+ 		&& CLASS_DATA (c)
+ 		&& CLASS_DATA (c)->attr.allocatable)
+ 	      {
+ 		gfc_error ("Result variable %qs of pure function at %L has "
+ 			   "polymorphic allocatable component %qs",
+ 			   sym->result->name, &sym->result->declared_at,
+ 			   c->name);
+ 		return false;
+ 	      }
+ 	}
+     }
+ 
    if (sym->attr.is_bind_c && sym->attr.is_c_interop != 1)
      {
        gfc_formal_arglist *curr_arg;
*************** resolve_typebound_intrinsic_op (gfc_symb
*** 16083,16089 ****
  	  for (intr = derived->ns->op[op]; intr; intr = intr->next)
  	    if (intr->sym == target_proc
  		&& (target_proc->attr.used_in_submodule
! 		    || derived->attr.pdt_type))
  	      return true;
  
  	  if (!gfc_check_new_interface (derived->ns->op[op],
--- 16116,16123 ----
  	  for (intr = derived->ns->op[op]; intr; intr = intr->next)
  	    if (intr->sym == target_proc
  		&& (target_proc->attr.used_in_submodule
! 		    || derived->attr.pdt_type
! 		    || derived->attr.pdt_template))
  	      return true;
  
  	  if (!gfc_check_new_interface (derived->ns->op[op],
*************** gfc_impure_variable (gfc_symbol *sym)
*** 18955,18961 ****
      {
        if (ns == sym->ns)
  	break;
!       if (ns->proc_name->attr.flavor == FL_PROCEDURE && !sym->attr.function)
  	return 1;
      }
  
--- 18989,18996 ----
      {
        if (ns == sym->ns)
  	break;
!       if (ns->proc_name->attr.flavor == FL_PROCEDURE
! 	  && !(sym->attr.function || sym->attr.result))
  	return 1;
      }
  
diff -Nrcpad gcc-16-20251026/gcc/fortran/trans-array.cc gcc-16-20251102/gcc/fortran/trans-array.cc
*** gcc-16-20251026/gcc/fortran/trans-array.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/trans-array.cc	Sun Nov  2 22:32:21 2025
*************** gfc_conv_descriptor_data_get (tree desc)
*** 268,280 ****
    return fold_convert (GFC_TYPE_ARRAY_DATAPTR_TYPE (type), field);
  }
  
! /* This provides WRITE access to the data field.
! 
!    TUPLES_P is true if we are generating tuples.
! 
!    This function gets called through the following macros:
!      gfc_conv_descriptor_data_set
!      gfc_conv_descriptor_data_set.  */
  
  void
  gfc_conv_descriptor_data_set (stmtblock_t *block, tree desc, tree value)
--- 268,274 ----
    return fold_convert (GFC_TYPE_ARRAY_DATAPTR_TYPE (type), field);
  }
  
! /* This provides WRITE access to the data field.  */
  
  void
  gfc_conv_descriptor_data_set (stmtblock_t *block, tree desc, tree value)
diff -Nrcpad gcc-16-20251026/gcc/fortran/trans-const.cc gcc-16-20251102/gcc/fortran/trans-const.cc
*** gcc-16-20251026/gcc/fortran/trans-const.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/trans-const.cc	Sun Nov  2 22:32:21 2025
*************** gfc_conv_constant (gfc_se * se, gfc_expr
*** 444,449 ****
        if (expr->ts.type == BT_CHARACTER)
  	gfc_conv_string_parameter (se);
        else
! 	se->expr = gfc_build_addr_expr (NULL_TREE, se->expr);
      }
  }
--- 444,451 ----
        if (expr->ts.type == BT_CHARACTER)
  	gfc_conv_string_parameter (se);
        else
! 	se->expr
! 	  = gfc_build_addr_expr (NULL_TREE,
! 				 gfc_trans_force_lval (&se->pre, se->expr));
      }
  }
diff -Nrcpad gcc-16-20251026/gcc/fortran/trans-expr.cc gcc-16-20251102/gcc/fortran/trans-expr.cc
*** gcc-16-20251026/gcc/fortran/trans-expr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/trans-expr.cc	Sun Nov  2 22:32:21 2025
*************** gfc_conv_gfc_desc_to_cfi_desc (gfc_se *p
*** 6090,6098 ****
        se.want_pointer = 1;
        gfc_conv_expr (&se, e);
        gfc = se.expr;
-       /* gfc_conv_constant ignores se.want_poiner, e.g. for string_cst.  */
-       if (!POINTER_TYPE_P (TREE_TYPE (gfc)))
- 	gfc = gfc_build_addr_expr (NULL, gfc);
      }
    else
      {
--- 6090,6095 ----
diff -Nrcpad gcc-16-20251026/gcc/fortran/trans-intrinsic.cc gcc-16-20251102/gcc/fortran/trans-intrinsic.cc
*** gcc-16-20251026/gcc/fortran/trans-intrinsic.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/trans-intrinsic.cc	Sun Nov  2 22:32:21 2025
*************** conv_intrinsic_atomic_cas (gfc_code *cod
*** 12844,12857 ****
            new_val = gfc_build_addr_expr (NULL_TREE, tmp);
  	}
  
-       /* Convert a constant to a pointer.  */
-       if (!POINTER_TYPE_P (TREE_TYPE (comp)))
- 	{
- 	  tmp = gfc_create_var (TREE_TYPE (TREE_TYPE (old)), "comp");
- 	  gfc_add_modify (&block, tmp, fold_convert (TREE_TYPE (tmp), comp));
-           comp = gfc_build_addr_expr (NULL_TREE, tmp);
- 	}
- 
        gfc_init_se (&argse, NULL);
        gfc_get_caf_token_offset (&argse, &token, &offset, caf_decl, atom,
  				atom_expr);
--- 12844,12849 ----
diff -Nrcpad gcc-16-20251026/gcc/fortran/trans-stmt.cc gcc-16-20251102/gcc/fortran/trans-stmt.cc
*** gcc-16-20251026/gcc/fortran/trans-stmt.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/fortran/trans-stmt.cc	Sun Nov  2 22:32:21 2025
*************** trans_associate_var (gfc_symbol *sym, gf
*** 2092,2097 ****
--- 2092,2113 ----
        gfc_free_expr (expr1);
        gfc_free_expr (expr2);
      }
+   /* PDT array and string components are separately allocated for each element
+      of a PDT array. Therefore, there is no choice but to copy in and copy out
+      the target expression.  */
+   else if (e && is_subref_array (e)
+ 	   && (gfc_expr_attr (e).pdt_array || gfc_expr_attr (e).pdt_string))
+     {
+       gfc_se init;
+       gcc_assert (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (sym->backend_decl)));
+       gfc_init_se (&init, NULL);
+       gfc_conv_subref_array_arg (&init, e, false, INTENT_INOUT,
+ 				 sym && sym->attr.pointer);
+       init.expr = build_fold_indirect_ref_loc (input_location, init.expr);
+       gfc_add_modify (&init.pre, sym->backend_decl, init.expr);
+       gfc_add_init_cleanup (block, gfc_finish_block (&init.pre),
+ 			    gfc_finish_block (&init.post));
+     }
    else if ((sym->attr.dimension || sym->attr.codimension) && !class_target
  	   && (sym->as->type == AS_DEFERRED || sym->assoc->variable))
      {
diff -Nrcpad gcc-16-20251026/gcc/function-abi.h gcc-16-20251102/gcc/function-abi.h
*** gcc-16-20251026/gcc/function-abi.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/function-abi.h	Sun Nov  2 22:32:21 2025
*************** along with GCC; see the file COPYING3.
*** 28,34 ****
     NUM_ABI_IDS is the maximum number of such ABIs that GCC can handle at once.
     A bitfield with this number of bits can represent any combinaion of the
     supported ABIs.  */
! const size_t NUM_ABI_IDS = 8;
  
  /* Information about one of the target's predefined ABIs.  */
  class predefined_function_abi
--- 28,34 ----
     NUM_ABI_IDS is the maximum number of such ABIs that GCC can handle at once.
     A bitfield with this number of bits can represent any combinaion of the
     supported ABIs.  */
! const size_t NUM_ABI_IDS = 12;
  
  /* Information about one of the target's predefined ABIs.  */
  class predefined_function_abi
diff -Nrcpad gcc-16-20251026/gcc/gimple-fold.cc gcc-16-20251102/gcc/gimple-fold.cc
*** gcc-16-20251026/gcc/gimple-fold.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/gimple-fold.cc	Sun Nov  2 22:32:21 2025
*************** gimple_fold_builtin_constant_p (gimple_s
*** 5233,5256 ****
    return true;
  }
  
- /* Fold __builtin_assume_aligned builtin.  */
- 
- static bool
- gimple_fold_builtin_assume_aligned (gimple_stmt_iterator *gsi)
- {
-   if (!fold_before_rtl_expansion_p ())
-     return false;
- 
-   gcall *call = as_a<gcall*>(gsi_stmt (*gsi));
- 
-   if (gimple_call_num_args (call) < 2)
-     return false;
- 
-   gimplify_and_update_call_from_tree (gsi, gimple_call_arg (call, 0));
- 
-   return true;
- }
- 
  /* If va_list type is a simple pointer and nothing special is needed,
     optimize __builtin_va_start (&ap, 0) into ap = __builtin_next_arg (0),
     __builtin_va_end (&ap) out as NOP and __builtin_va_copy into a simple
--- 5233,5238 ----
*************** gimple_fold_builtin (gimple_stmt_iterato
*** 5548,5556 ****
      case BUILT_IN_CONSTANT_P:
        return gimple_fold_builtin_constant_p (gsi);
  
-     case BUILT_IN_ASSUME_ALIGNED:
-       return gimple_fold_builtin_assume_aligned (gsi);
- 
      default:;
      }
  
--- 5530,5535 ----
diff -Nrcpad gcc-16-20251026/gcc/gimple-range-op.cc gcc-16-20251102/gcc/gimple-range-op.cc
*** gcc-16-20251026/gcc/gimple-range-op.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/gimple-range-op.cc	Sun Nov  2 22:32:21 2025
*************** gimple_range_op_handler::gimple_range_op
*** 150,155 ****
--- 150,159 ----
  	      if (TREE_CODE (ssa) == SSA_NAME)
  		m_op1 = ssa;
  	    }
+ 	  // VIEW_CONVERT_EXPR needs to descend one level deeper to pick
+ 	  // up the symbolic operand.
+ 	  if (TREE_CODE (m_op1) == VIEW_CONVERT_EXPR)
+ 	    m_op1 = TREE_OPERAND (m_op1, 0);
  	  if (gimple_num_ops (m_stmt) >= 3)
  	    m_op2 = gimple_assign_rhs2 (m_stmt);
  	  // Check that operands are supported types.  One check is enough.
diff -Nrcpad gcc-16-20251026/gcc/go/ChangeLog gcc-16-20251102/gcc/go/ChangeLog
*** gcc-16-20251026/gcc/go/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/go/ChangeLog	Sun Nov  2 22:32:21 2025
***************
*** 1,3 ****
--- 1,9 ----
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/122325
+ 	* go-lang.cc (go_langhook_init_options_struct): Remove set of
+ 	flag_default_complex_method.
+ 
  2025-07-15  Jakub Jelinek  <jakub@redhat.com>
  	    Jason Merrill  <jason@redhat.com>
  
diff -Nrcpad gcc-16-20251026/gcc/go/go-lang.cc gcc-16-20251102/gcc/go/go-lang.cc
*** gcc-16-20251026/gcc/go/go-lang.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/go/go-lang.cc	Sun Nov  2 22:32:21 2025
*************** go_langhook_init_options_struct (struct
*** 173,179 ****
    /* Default to avoiding range issues for complex multiply and
       divide.  */
    opts->x_flag_complex_method = 2;
-   opts->x_flag_default_complex_method = opts->x_flag_complex_method;
  
    /* The builtin math functions should not set errno.  */
    opts->x_flag_errno_math = 0;
--- 173,178 ----
diff -Nrcpad gcc-16-20251026/gcc/ifcvt.cc gcc-16-20251102/gcc/ifcvt.cc
*** gcc-16-20251026/gcc/ifcvt.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/ifcvt.cc	Sun Nov  2 22:32:21 2025
*************** noce_try_sign_bit_splat (struct noce_if_
*** 1289,1301 ****
        bool speed_p = optimize_insn_for_speed_p ();
        if (exact_log2 (val_a + 1) >= 0
  	  && (rtx_cost (shift_right, mode, SET, 1, speed_p)
! 	      <= rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, LSHIFTRT, temp,
  				    GEN_INT (rshift_count),
  				    if_info->x, false, OPTAB_WIDEN);
        else if (exact_log2 (~val_a + 1) >= 0
  	       && (rtx_cost (shift_left, mode, SET, 1, speed_p)
! 		   <= rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, ASHIFT, temp,
  				    GEN_INT (ctz_hwi (val_a)),
  				    if_info->x, false, OPTAB_WIDEN);
--- 1289,1301 ----
        bool speed_p = optimize_insn_for_speed_p ();
        if (exact_log2 (val_a + 1) >= 0
  	  && (rtx_cost (shift_right, mode, SET, 1, speed_p)
! 	      < rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, LSHIFTRT, temp,
  				    GEN_INT (rshift_count),
  				    if_info->x, false, OPTAB_WIDEN);
        else if (exact_log2 (~val_a + 1) >= 0
  	       && (rtx_cost (shift_left, mode, SET, 1, speed_p)
! 		   < rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, ASHIFT, temp,
  				    GEN_INT (ctz_hwi (val_a)),
  				    if_info->x, false, OPTAB_WIDEN);
*************** noce_try_sign_bit_splat (struct noce_if_
*** 1341,1353 ****
        bool speed_p = optimize_insn_for_speed_p ();
        if (exact_log2 (val_b + 1) >= 0
  	  && (rtx_cost (shift_right, mode, SET, 1, speed_p)
! 	      <= rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, LSHIFTRT, temp,
  				    GEN_INT (rshift_count),
  				    if_info->x, false, OPTAB_WIDEN);
        else if (exact_log2 (~val_b + 1) >= 0
  	       && (rtx_cost (shift_left, mode, SET, 1, speed_p)
! 		   <= rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, ASHIFT, temp,
  				    GEN_INT (ctz_hwi (val_b)),
  				    if_info->x, false, OPTAB_WIDEN);
--- 1341,1353 ----
        bool speed_p = optimize_insn_for_speed_p ();
        if (exact_log2 (val_b + 1) >= 0
  	  && (rtx_cost (shift_right, mode, SET, 1, speed_p)
! 	      < rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, LSHIFTRT, temp,
  				    GEN_INT (rshift_count),
  				    if_info->x, false, OPTAB_WIDEN);
        else if (exact_log2 (~val_b + 1) >= 0
  	       && (rtx_cost (shift_left, mode, SET, 1, speed_p)
! 		   < rtx_cost (and_form, mode, SET, 1, speed_p)))
  	temp = expand_simple_binop (mode, ASHIFT, temp,
  				    GEN_INT (ctz_hwi (val_b)),
  				    if_info->x, false, OPTAB_WIDEN);
diff -Nrcpad gcc-16-20251026/gcc/ipa-icf.cc gcc-16-20251102/gcc/ipa-icf.cc
*** gcc-16-20251026/gcc/ipa-icf.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/ipa-icf.cc	Sun Nov  2 22:32:21 2025
*************** sem_item_optimizer::write_summary (void)
*** 2166,2172 ****
         !lsei_end_p (lsei);
         lsei_next_in_partition (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
        if (m_symtab_node_map.get (node))
  	count++;
--- 2166,2174 ----
         !lsei_end_p (lsei);
         lsei_next_in_partition (&lsei))
      {
!       symtab_node *node = dyn_cast <symtab_node *> (lsei_node (lsei));
!       if (!node)
! 	continue;
  
        if (m_symtab_node_map.get (node))
  	count++;
*************** sem_item_optimizer::write_summary (void)
*** 2179,2185 ****
         !lsei_end_p (lsei);
         lsei_next_in_partition (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
        sem_item **item = m_symtab_node_map.get (node);
  
--- 2181,2189 ----
         !lsei_end_p (lsei);
         lsei_next_in_partition (&lsei))
      {
!       symtab_node *node = dyn_cast <symtab_node *> (lsei_node (lsei));
!       if (!node)
! 	continue;
  
        sem_item **item = m_symtab_node_map.get (node);
  
*************** sem_item_optimizer::read_section (lto_fi
*** 2233,2239 ****
    for (i = 0; i < count; i++)
      {
        unsigned int index;
!       symtab_node *node;
        lto_symtab_encoder_t encoder;
  
        index = streamer_read_uhwi (&ib_main);
--- 2237,2243 ----
    for (i = 0; i < count; i++)
      {
        unsigned int index;
!       toplevel_node *node;
        lto_symtab_encoder_t encoder;
  
        index = streamer_read_uhwi (&ib_main);
*************** sem_item_optimizer::read_section (lto_fi
*** 2241,2252 ****
        node = lto_symtab_encoder_deref (encoder, index);
  
        hashval_t hash = streamer_read_uhwi (&ib_main);
!       gcc_assert (node->definition);
  
!       if (is_a<cgraph_node *> (node))
  	{
- 	  cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
- 
  	  sem_function *fn = new sem_function (cnode, &m_bmstack);
  	  unsigned count = streamer_read_uhwi (&ib_main);
  	  inchash::hash hstate (0);
--- 2245,2255 ----
        node = lto_symtab_encoder_deref (encoder, index);
  
        hashval_t hash = streamer_read_uhwi (&ib_main);
!       if (symtab_node *snode = dyn_cast <symtab_node *> (node))
! 	gcc_assert (snode->definition);
  
!       if (cgraph_node *cnode = dyn_cast <cgraph_node *> (node))
  	{
  	  sem_function *fn = new sem_function (cnode, &m_bmstack);
  	  unsigned count = streamer_read_uhwi (&ib_main);
  	  inchash::hash hstate (0);
*************** sem_item_optimizer::read_section (lto_fi
*** 2263,2272 ****
  	  fn->set_hash (hash);
  	  m_items.safe_push (fn);
  	}
!       else
  	{
- 	  varpool_node *vnode = dyn_cast <varpool_node *> (node);
- 
  	  sem_variable *var = new sem_variable (vnode, &m_bmstack);
  	  var->set_hash (hash);
  	  m_items.safe_push (var);
--- 2266,2273 ----
  	  fn->set_hash (hash);
  	  m_items.safe_push (fn);
  	}
!       else if (varpool_node *vnode = dyn_cast <varpool_node *> (node))
  	{
  	  sem_variable *var = new sem_variable (vnode, &m_bmstack);
  	  var->set_hash (hash);
  	  m_items.safe_push (var);
diff -Nrcpad gcc-16-20251026/gcc/ipa-modref.cc gcc-16-20251102/gcc/ipa-modref.cc
*** gcc-16-20251026/gcc/ipa-modref.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/ipa-modref.cc	Sun Nov  2 22:32:22 2025
*************** modref_write ()
*** 3752,3759 ****
  
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
        modref_summary_lto *r;
  
        if (cnode && cnode->definition && !cnode->alias
--- 3752,3759 ----
  
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
        modref_summary_lto *r;
  
        if (cnode && cnode->definition && !cnode->alias
*************** modref_write ()
*** 3765,3772 ****
  
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
  
        if (cnode && cnode->definition && !cnode->alias)
  	{
--- 3765,3772 ----
  
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
  
        if (cnode && cnode->definition && !cnode->alias)
  	{
diff -Nrcpad gcc-16-20251026/gcc/ipa-prop.cc gcc-16-20251102/gcc/ipa-prop.cc
*** gcc-16-20251026/gcc/ipa-prop.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/ipa-prop.cc	Sun Nov  2 22:32:22 2025
*************** ipa_write_return_summaries (output_block
*** 5576,5583 ****
    unsigned int count = 0;
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
        ipa_return_value_summary *v;
  
        if (cnode && cnode->definition && !cnode->alias
--- 5576,5583 ----
    unsigned int count = 0;
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
        ipa_return_value_summary *v;
  
        if (cnode && cnode->definition && !cnode->alias
*************** ipa_write_return_summaries (output_block
*** 5589,5596 ****
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
        ipa_return_value_summary *v;
  
        if (cnode && cnode->definition && !cnode->alias
--- 5589,5596 ----
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
        ipa_return_value_summary *v;
  
        if (cnode && cnode->definition && !cnode->alias
*************** ipcp_write_transformation_summaries (voi
*** 5865,5872 ****
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
        if (!cnode)
  	continue;
        ipcp_transformation *ts = ipcp_get_transformation_summary (cnode);
--- 5865,5872 ----
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
        if (!cnode)
  	continue;
        ipcp_transformation *ts = ipcp_get_transformation_summary (cnode);
*************** ipcp_write_transformation_summaries (voi
*** 5879,5886 ****
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
        if (!cnode)
  	continue;
        ipcp_transformation *ts = ipcp_get_transformation_summary (cnode);
--- 5879,5886 ----
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
        if (!cnode)
  	continue;
        ipcp_transformation *ts = ipcp_get_transformation_summary (cnode);
diff -Nrcpad gcc-16-20251026/gcc/ipa-reference.cc gcc-16-20251102/gcc/ipa-reference.cc
*** gcc-16-20251026/gcc/ipa-reference.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/ipa-reference.cc	Sun Nov  2 22:32:22 2025
*************** ipa_reference_write_optimization_summary
*** 1070,1077 ****
    /* See what variables we are interested in.  */
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       varpool_node *vnode = dyn_cast <varpool_node *> (snode);
        int id;
  
        if (vnode
--- 1070,1077 ----
    /* See what variables we are interested in.  */
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       varpool_node *vnode = dyn_cast <varpool_node *> (tnode);
        int id;
  
        if (vnode
*************** ipa_reference_write_optimization_summary
*** 1089,1096 ****
    if (ltrans_statics_bitcount)
      for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
        {
! 	symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
! 	cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
  	if (cnode && write_node_summary_p (cnode, encoder, ltrans_statics))
  	  count++;
        }
--- 1089,1096 ----
    if (ltrans_statics_bitcount)
      for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
        {
! 	toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
! 	cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
  	if (cnode && write_node_summary_p (cnode, encoder, ltrans_statics))
  	  count++;
        }
*************** ipa_reference_write_optimization_summary
*** 1104,1118 ****
    if (ltrans_statics_bitcount)
      for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
        {
! 	symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
! 	cgraph_node *cnode = dyn_cast <cgraph_node *> (snode);
  	if (cnode && write_node_summary_p (cnode, encoder, ltrans_statics))
  	  {
  	    ipa_reference_optimization_summary_t info;
  	    int node_ref;
  
  	    info = get_reference_optimization_summary (cnode);
! 	    node_ref = lto_symtab_encoder_encode (encoder, snode);
  	    streamer_write_uhwi_stream (ob->main_stream, node_ref);
  
  	    stream_out_bitmap (ob, info->statics_read, ltrans_statics,
--- 1104,1118 ----
    if (ltrans_statics_bitcount)
      for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
        {
! 	toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
! 	cgraph_node *cnode = dyn_cast <cgraph_node *> (tnode);
  	if (cnode && write_node_summary_p (cnode, encoder, ltrans_statics))
  	  {
  	    ipa_reference_optimization_summary_t info;
  	    int node_ref;
  
  	    info = get_reference_optimization_summary (cnode);
! 	    node_ref = lto_symtab_encoder_encode (encoder, tnode);
  	    streamer_write_uhwi_stream (ob->main_stream, node_ref);
  
  	    stream_out_bitmap (ob, info->statics_read, ltrans_statics,
diff -Nrcpad gcc-16-20251026/gcc/jit/ChangeLog gcc-16-20251102/gcc/jit/ChangeLog
*** gcc-16-20251026/gcc/jit/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/jit/ChangeLog	Sun Nov  2 22:32:22 2025
***************
*** 1,3 ****
--- 1,9 ----
+ 2025-10-26  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+ 
+ 	* jit-recording.cc (recording::array_type::make_debug_string,
+ 	recording::array_type::write_reproducer): Use PRIu64 format
+ 	specifier for uint64_t.
+ 
  2025-10-22  Antoni Boucher  <bouanto@zoho.com>
  
  	* docs/topics/types.rst: Document new types.
diff -Nrcpad gcc-16-20251026/gcc/lra-constraints.cc gcc-16-20251102/gcc/lra-constraints.cc
*** gcc-16-20251026/gcc/lra-constraints.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lra-constraints.cc	Sun Nov  2 22:32:22 2025
*************** update_equiv (int regno)
*** 523,528 ****
--- 523,533 ----
  {
    rtx x;
  
+   /* If REGNO is beyond the length of the equivalence array structure,
+      then there's nothing to update.  */
+   if (regno >= ira_reg_equiv_len)
+     return;
+ 
    if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
      ira_reg_equiv[regno].memory
        = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
*************** process_alt_operands (int only_alternati
*** 2552,2558 ****
  		    {
  		      int regno = decode_hard_reg_constraint (p);
  		      gcc_assert (regno >= 0);
! 		      cl = REGNO_REG_CLASS (regno);
  		      CLEAR_HARD_REG_SET (hard_reg_constraint);
  		      SET_HARD_REG_BIT (hard_reg_constraint, regno);
  		      cl_filter = &hard_reg_constraint;
--- 2557,2566 ----
  		    {
  		      int regno = decode_hard_reg_constraint (p);
  		      gcc_assert (regno >= 0);
! 		      cl = NO_REGS;
! 		      int nregs = hard_regno_nregs (regno, mode);
! 		      for (int i = 0; i < nregs; ++i)
! 			cl = reg_class_superunion[cl][REGNO_REG_CLASS (regno + i)];
  		      CLEAR_HARD_REG_SET (hard_reg_constraint);
  		      SET_HARD_REG_BIT (hard_reg_constraint, regno);
  		      cl_filter = &hard_reg_constraint;
diff -Nrcpad gcc-16-20251026/gcc/lto/ChangeLog gcc-16-20251102/gcc/lto/ChangeLog
*** gcc-16-20251026/gcc/lto/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto/ChangeLog	Sun Nov  2 22:32:22 2025
***************
*** 1,3 ****
--- 1,46 ----
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto.cc (stream_out_partitions): Remove asm_nodes_out.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-partition.cc (create_partition_if_empty): New.
+ 	(node_into_file_partition): Break out from ...
+ 	(lto_1_to_1_map): ... here. Partition toplevel assembly.
+ 	(create_asm_partition): New.
+ 	(lto_max_map): Use create_asm_partition.
+ 	(lto_balanced_map): Likewise.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-partition.cc (add_symbol_to_partition): Use toplevel_node.
+ 	(undo_partition): Likewise.
+ 	(join_partitions): Likewise.
+ 	(split_partition_into_nodes): Likewise.
+ 	(is_partition_reorder): Likewise.
+ 	(lto_balanced_map): Likewise.
+ 	(lto_promote_cross_file_statics): Likewise.
+ 	* lto.cc (lto_wpa_write_files): Likewise.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-partition.cc (lto_balanced_map): Simplify.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-symtab.cc (lto_symtab_merge_symbols_1): likewise.
+ 
+ 2025-10-30  Michal Jires  <mjires@suse.cz>
+ 
+ 	* lto-partition.cc (cmp_partitions_order): Reverse sort.
+ 	(node_cmp): Reverse sort.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/122325
+ 	* lto-lang.cc (lto_init_options_struct): Remove set of
+ 	flag_default_complex_method.
+ 
  2025-10-01  Jan Hubicka  <hubicka@ucw.cz>
  
  	* Make-lang.in: Add lto_FDAS; enable FDA collection
diff -Nrcpad gcc-16-20251026/gcc/lto/lto-lang.cc gcc-16-20251102/gcc/lto/lto-lang.cc
*** gcc-16-20251026/gcc/lto/lto-lang.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto/lto-lang.cc	Sun Nov  2 22:32:22 2025
*************** lto_init_options_struct (struct gcc_opti
*** 841,847 ****
       safe choice.  This will pessimize Fortran code with LTO unless
       people specify a complex method manually or use -ffast-math.  */
    opts->x_flag_complex_method = 2;
-   opts->x_flag_default_complex_method = opts->x_flag_complex_method;
  }
  
  /* Handle command-line option SCODE.  If the option takes an argument, it is
--- 841,846 ----
diff -Nrcpad gcc-16-20251026/gcc/lto/lto-partition.cc gcc-16-20251102/gcc/lto/lto-partition.cc
*** gcc-16-20251026/gcc/lto/lto-partition.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto/lto-partition.cc	Sun Nov  2 22:32:22 2025
*************** along with GCC; see the file COPYING3.
*** 43,49 ****
  
  vec<ltrans_partition> ltrans_partitions;
  
! static void add_symbol_to_partition (ltrans_partition part, symtab_node *node);
  
  
  /* Helper for qsort; compare partitions and return one with smaller order.  */
--- 43,50 ----
  
  vec<ltrans_partition> ltrans_partitions;
  
! static void add_symbol_to_partition (ltrans_partition part,
! 				     toplevel_node *node);
  
  
  /* Helper for qsort; compare partitions and return one with smaller order.  */
*************** cmp_partitions_order (const void *a, con
*** 61,67 ****
      ordera = lto_symtab_encoder_deref (pa->encoder, 0)->order;
    if (lto_symtab_encoder_size (pb->encoder))
      orderb = lto_symtab_encoder_deref (pb->encoder, 0)->order;
!   return orderb - ordera;
  }
  
  /* Create new partition with name NAME.
--- 62,68 ----
      ordera = lto_symtab_encoder_deref (pa->encoder, 0)->order;
    if (lto_symtab_encoder_size (pb->encoder))
      orderb = lto_symtab_encoder_deref (pb->encoder, 0)->order;
!   return ordera - orderb;
  }
  
  /* Create new partition with name NAME.
*************** new_partition (const char *name)
*** 87,92 ****
--- 88,102 ----
    return part;
  }
  
+ /* If the cgraph is empty, create one cgraph node set so that there is still
+    an output file for any variables that need to be exported in a DSO.  */
+ static void
+ create_partition_if_empty ()
+ {
+   if (!ltrans_partitions.length ())
+     new_partition ("empty");
+ }
+ 
  /* Free memory used by ltrans partition.
     Encoder can be kept to be freed after streaming.  */
  static void
*************** contained_in_symbol (symtab_node *node)
*** 266,274 ****
     of other symbol definition, add the other symbol, too.  */
  
  static void
! add_symbol_to_partition (ltrans_partition part, symtab_node *node)
  {
    symtab_node *node1;
  
    /* Verify that we do not try to duplicate something that cannot be.  */
    gcc_checking_assert (node->get_partitioning_class () == SYMBOL_DUPLICATE
--- 276,290 ----
     of other symbol definition, add the other symbol, too.  */
  
  static void
! add_symbol_to_partition (ltrans_partition part, toplevel_node *tnode)
  {
    symtab_node *node1;
+   symtab_node* node = dyn_cast <symtab_node*> (tnode);
+   if (!node)
+     {
+       lto_set_symtab_encoder_in_partition (part->encoder, tnode);
+       return;
+     }
  
    /* Verify that we do not try to duplicate something that cannot be.  */
    gcc_checking_assert (node->get_partitioning_class () == SYMBOL_DUPLICATE
*************** undo_partition (ltrans_partition partiti
*** 299,322 ****
  {
    while (lto_symtab_encoder_size (partition->encoder) > (int)n_nodes)
      {
!       symtab_node *node = lto_symtab_encoder_deref (partition->encoder,
! 						   n_nodes);
!       partition->symbols--;
!       cgraph_node *cnode;
  
        /* After UNDO we no longer know what was visited.  */
        if (partition->initializers_visited)
  	delete partition->initializers_visited;
        partition->initializers_visited = NULL;
  
!       if (!node->alias && (cnode = dyn_cast <cgraph_node *> (node))
!           && node->get_partitioning_class () == SYMBOL_PARTITION)
! 	partition->insns -= ipa_size_summaries->get (cnode)->size;
!       lto_symtab_encoder_delete_node (partition->encoder, node);
!       node->aux = (void *)((size_t)node->aux - 1);
      }
  }
  
  /* Group cgrah nodes by input files.  This is used mainly for testing
     right now.  */
  
--- 315,369 ----
  {
    while (lto_symtab_encoder_size (partition->encoder) > (int)n_nodes)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (partition->encoder,
! 						       n_nodes);
  
        /* After UNDO we no longer know what was visited.  */
        if (partition->initializers_visited)
  	delete partition->initializers_visited;
        partition->initializers_visited = NULL;
  
!       lto_symtab_encoder_delete_node (partition->encoder, tnode);
! 
!       if (symtab_node* node = dyn_cast <symtab_node *> (tnode))
! 	{
! 	  partition->symbols--;
! 	  cgraph_node *cnode;
! 	  if (!node->alias && (cnode = dyn_cast <cgraph_node *> (node))
! 	      && node->get_partitioning_class () == SYMBOL_PARTITION)
! 	    partition->insns -= ipa_size_summaries->get (cnode)->size;
! 	  node->aux = (void *)((size_t)node->aux - 1);
! 	}
      }
  }
  
+ /* Insert node into its file partition.  */
+ static void
+ node_into_file_partition (toplevel_node* node,
+ 			  hash_map<lto_file_decl_data *,
+ 				   ltrans_partition>& pmap)
+ {
+   ltrans_partition partition;
+ 
+   struct lto_file_decl_data *file_data = node->lto_file_data;
+ 
+   if (file_data)
+     {
+       ltrans_partition *slot = &pmap.get_or_insert (file_data);
+       if (*slot)
+ 	partition = *slot;
+       else
+ 	{
+ 	  partition = new_partition (file_data->file_name);
+ 	  *slot = partition;
+ 	}
+     }
+   else
+     partition = new_partition ("");
+ 
+   add_symbol_to_partition (partition, node);
+ }
+ 
  /* Group cgrah nodes by input files.  This is used mainly for testing
     right now.  */
  
*************** void
*** 324,333 ****
  lto_1_to_1_map (void)
  {
    symtab_node *node;
-   struct lto_file_decl_data *file_data;
    hash_map<lto_file_decl_data *, ltrans_partition> pmap;
-   ltrans_partition partition;
-   int npartitions = 0;
  
    FOR_EACH_SYMBOL (node)
      {
--- 371,377 ----
*************** lto_1_to_1_map (void)
*** 335,375 ****
  	  || symbol_partitioned_p (node))
  	continue;
  
!       file_data = node->lto_file_data;
! 
!       if (file_data)
! 	{
!           ltrans_partition *slot = &pmap.get_or_insert (file_data);
!           if (*slot)
! 	    partition = *slot;
! 	  else
! 	    {
! 	      partition = new_partition (file_data->file_name);
! 	      *slot = partition;
! 	      npartitions++;
! 	    }
! 	}
!       else if (!file_data && ltrans_partitions.length ())
! 	partition = ltrans_partitions[0];
!       else
! 	{
! 	  partition = new_partition ("");
! 	  npartitions++;
! 	}
! 
!       add_symbol_to_partition (partition, node);
      }
  
!   /* If the cgraph is empty, create one cgraph node set so that there is still
!      an output file for any variables that need to be exported in a DSO.  */
!   if (!npartitions)
!     new_partition ("empty");
  
    /* Order partitions by order of symbols because they are linked into binary
       that way.  */
    ltrans_partitions.qsort (cmp_partitions_order);
  }
  
  /* Maximal partitioning.  Put every new symbol into new partition if possible.  */
  
  void
--- 379,416 ----
  	  || symbol_partitioned_p (node))
  	continue;
  
!       node_into_file_partition (node, pmap);
      }
  
!   struct asm_node *anode;
!   for (anode = symtab->first_asm_symbol (); anode; anode = anode->next)
!     node_into_file_partition (anode, pmap);
! 
!   create_partition_if_empty ();
  
    /* Order partitions by order of symbols because they are linked into binary
       that way.  */
    ltrans_partitions.qsort (cmp_partitions_order);
  }
  
+ /* Creates partition with all toplevel assembly.
+ 
+    Before toplevel asm could be partitioned, all toplevel asm was inserted
+    into first partition.
+    This function achieves similar behavior for partitionings that cannot
+    easily satisfy requirements of toplevel asm.  */
+ static void
+ create_asm_partition (void)
+ {
+   struct asm_node *anode = symtab->first_asm_symbol ();
+   if (anode)
+     {
+       ltrans_partition partition = new_partition ("asm_nodes");
+       for (; anode; anode = anode->next)
+ 	add_symbol_to_partition (partition, anode);
+     }
+ }
+ 
  /* Maximal partitioning.  Put every new symbol into new partition if possible.  */
  
  void
*************** lto_max_map (void)
*** 377,383 ****
  {
    symtab_node *node;
    ltrans_partition partition;
-   int npartitions = 0;
  
    FOR_EACH_SYMBOL (node)
      {
--- 418,423 ----
*************** lto_max_map (void)
*** 386,395 ****
  	continue;
        partition = new_partition (node->asm_name ());
        add_symbol_to_partition (partition, node);
-       npartitions++;
      }
!   if (!npartitions)
!     new_partition ("empty");
  }
  
  /* Helper function for qsort; sort nodes by order.  */
--- 426,435 ----
  	continue;
        partition = new_partition (node->asm_name ());
        add_symbol_to_partition (partition, node);
      }
! 
!   create_asm_partition ();
!   create_partition_if_empty ();
  }
  
  /* Helper function for qsort; sort nodes by order.  */
*************** node_cmp (const void *pa, const void *pb
*** 398,404 ****
  {
    const symtab_node *a = *static_cast<const symtab_node * const *> (pa);
    const symtab_node *b = *static_cast<const symtab_node * const *> (pb);
!   return b->order - a->order;
  }
  
  /* Add all symtab nodes from NEXT_NODE to PARTITION in order.  */
--- 438,444 ----
  {
    const symtab_node *a = *static_cast<const symtab_node * const *> (pa);
    const symtab_node *b = *static_cast<const symtab_node * const *> (pb);
!   return a->order - b->order;
  }
  
  /* Add all symtab nodes from NEXT_NODE to PARTITION in order.  */
*************** join_partitions (ltrans_partition into,
*** 467,482 ****
       before adding any symbols to other partition.  */
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
!       node->aux = (void *)((size_t)node->aux - 1);
      }
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
!       if (symbol_partitioned_p (node))
! 	continue;
  
        add_symbol_to_partition (into, node);
      }
--- 507,523 ----
       before adding any symbols to other partition.  */
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       if (symtab_node *node = dyn_cast <symtab_node*> (lsei_node (lsei)))
! 	node->aux = (void *)((size_t)node->aux - 1);
      }
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       toplevel_node *node = lsei_node (lsei);
  
!       if (symtab_node *snode = dyn_cast <symtab_node*> (node))
! 	if (symbol_partitioned_p (snode))
! 	  continue;
  
        add_symbol_to_partition (into, node);
      }
*************** split_partition_into_nodes (ltrans_parti
*** 498,513 ****
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
!       node->aux = (void *)((size_t)node->aux - 1);
      }
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
!       if (node->get_partitioning_class () != SYMBOL_PARTITION
! 	  || symbol_partitioned_p (node))
  	continue;
  
        ltrans_partition new_part = new_partition_no_push (part->name);
--- 539,555 ----
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       if (symtab_node *node = dyn_cast <symtab_node*> (lsei_node (lsei)))
! 	node->aux = (void *)((size_t)node->aux - 1);
      }
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       toplevel_node *node = lsei_node (lsei);
  
!       symtab_node *snode = dyn_cast <symtab_node*> (node);
!       if (snode->get_partitioning_class () != SYMBOL_PARTITION
! 	  || symbol_partitioned_p (snode))
  	continue;
  
        ltrans_partition new_part = new_partition_no_push (part->name);
*************** is_partition_reorder (ltrans_partition p
*** 527,534 ****
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
!       if (node->no_reorder)
  	return false;
      }
    return true;
--- 569,576 ----
  
    for (lsei = lsei_start (encoder); !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = dyn_cast <symtab_node*> (lsei_node (lsei));
!       if (!node || node->no_reorder)
  	return false;
      }
    return true;
*************** lto_balanced_map (int n_lto_partitions,
*** 1167,1186 ****
           callgraph or IPA reference edge leaving the partition contributes into
           COST.  Every edge inside partition was earlier computed as one leaving
  	 it and thus we need to subtract it from COST.  */
!       while (last_visited_node < lto_symtab_encoder_size (partition->encoder))
  	{
  	  int j;
  	  struct ipa_ref *ref = NULL;
! 	  symtab_node *snode = lto_symtab_encoder_deref (partition->encoder,
! 							last_visited_node);
  
  	  if (cgraph_node *node = dyn_cast <cgraph_node *> (snode))
  	    {
  	      struct cgraph_edge *edge;
  
- 
- 	      last_visited_node++;
- 
  	      gcc_assert (node->definition || node->weakref);
  
  	      /* Compute boundary cost of callgraph edges.  */
--- 1209,1230 ----
           callgraph or IPA reference edge leaving the partition contributes into
           COST.  Every edge inside partition was earlier computed as one leaving
  	 it and thus we need to subtract it from COST.  */
!       for (; last_visited_node < lto_symtab_encoder_size (partition->encoder);
! 	   last_visited_node++)
  	{
  	  int j;
  	  struct ipa_ref *ref = NULL;
! 	  toplevel_node *tnode = lto_symtab_encoder_deref (partition->encoder,
! 							   last_visited_node);
! 
! 	  symtab_node* snode = dyn_cast <symtab_node*> (tnode);
! 	  if (!snode)
! 	    continue;
  
  	  if (cgraph_node *node = dyn_cast <cgraph_node *> (snode))
  	    {
  	      struct cgraph_edge *edge;
  
  	      gcc_assert (node->definition || node->weakref);
  
  	      /* Compute boundary cost of callgraph edges.  */
*************** lto_balanced_map (int n_lto_partitions,
*** 1197,1204 ****
  		    gcc_assert (edge_cost > 0);
  		    index = lto_symtab_encoder_lookup (partition->encoder,
  						       edge->callee);
! 		    if (index != LCC_NOT_FOUND
! 		        && index < last_visited_node - 1)
  		      cost -= edge_cost, internal += edge_cost;
  		    else
  		      cost += edge_cost;
--- 1241,1247 ----
  		    gcc_assert (edge_cost > 0);
  		    index = lto_symtab_encoder_lookup (partition->encoder,
  						       edge->callee);
! 		    if (index != LCC_NOT_FOUND && index < last_visited_node)
  		      cost -= edge_cost, internal += edge_cost;
  		    else
  		      cost += edge_cost;
*************** lto_balanced_map (int n_lto_partitions,
*** 1216,1230 ****
  		  gcc_assert (edge_cost > 0);
  		  index = lto_symtab_encoder_lookup (partition->encoder,
  						     edge->caller);
! 		  if (index != LCC_NOT_FOUND
! 		      && index < last_visited_node - 1)
  		    cost -= edge_cost, internal += edge_cost;
  		  else
  		    cost += edge_cost;
  		}
  	    }
- 	  else
- 	    last_visited_node++;
  
  	  /* Compute boundary cost of IPA REF edges and at the same time look into
  	     variables referenced from current partition and try to add them.  */
--- 1259,1270 ----
  		  gcc_assert (edge_cost > 0);
  		  index = lto_symtab_encoder_lookup (partition->encoder,
  						     edge->caller);
! 		  if (index != LCC_NOT_FOUND && index < last_visited_node)
  		    cost -= edge_cost, internal += edge_cost;
  		  else
  		    cost += edge_cost;
  		}
  	    }
  
  	  /* Compute boundary cost of IPA REF edges and at the same time look into
  	     variables referenced from current partition and try to add them.  */
*************** lto_balanced_map (int n_lto_partitions,
*** 1242,1249 ****
  		  add_symbol_to_partition (partition, vnode);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   vnode);
! 		if (index != LCC_NOT_FOUND
! 		    && index < last_visited_node - 1)
  		  cost--, internal++;
  		else
  		  cost++;
--- 1282,1288 ----
  		  add_symbol_to_partition (partition, vnode);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   vnode);
! 		if (index != LCC_NOT_FOUND && index < last_visited_node)
  		  cost--, internal++;
  		else
  		  cost++;
*************** lto_balanced_map (int n_lto_partitions,
*** 1255,1262 ****
  		node = dyn_cast <cgraph_node *> (ref->referred);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   node);
! 		if (index != LCC_NOT_FOUND
! 		    && index < last_visited_node - 1)
  		  cost--, internal++;
  		else
  		  cost++;
--- 1294,1300 ----
  		node = dyn_cast <cgraph_node *> (ref->referred);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   node);
! 		if (index != LCC_NOT_FOUND && index < last_visited_node)
  		  cost--, internal++;
  		else
  		  cost++;
*************** lto_balanced_map (int n_lto_partitions,
*** 1281,1288 ****
  		  add_symbol_to_partition (partition, vnode);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   vnode);
! 		if (index != LCC_NOT_FOUND
! 		    && index < last_visited_node - 1)
  		  cost--, internal++;
  		else
  		  cost++;
--- 1319,1325 ----
  		  add_symbol_to_partition (partition, vnode);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   vnode);
! 		if (index != LCC_NOT_FOUND && index < last_visited_node)
  		  cost--, internal++;
  		else
  		  cost++;
*************** lto_balanced_map (int n_lto_partitions,
*** 1295,1302 ****
  		gcc_assert (node->definition);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   node);
! 		if (index != LCC_NOT_FOUND
! 		    && index < last_visited_node - 1)
  		  cost--, internal++;
  		else
  		  cost++;
--- 1332,1338 ----
  		gcc_assert (node->definition);
  		index = lto_symtab_encoder_lookup (partition->encoder,
  						   node);
! 		if (index != LCC_NOT_FOUND && index < last_visited_node)
  		  cost--, internal++;
  		else
  		  cost++;
*************** lto_balanced_map (int n_lto_partitions,
*** 1401,1406 ****
--- 1437,1444 ----
    gcc_assert (next_nodes.length () || npartitions != 1 || !best_cost || best_cost == -1);
    add_sorted_nodes (next_nodes, partition);
  
+   create_asm_partition ();
+ 
    if (dump_file)
      {
        fprintf (dump_file, "\nPartition sizes:\n");
*************** lto_promote_cross_file_statics (void)
*** 1872,1878 ****
        for (lsei = lsei_start (encoder); !lsei_end_p (lsei);
  	   lsei_next (&lsei))
          {
!           symtab_node *node = lsei_node (lsei);
  
  	  /* If symbol is static, rename it if its assembler name
  	     clashes with anything else in this unit.  */
--- 1910,1919 ----
        for (lsei = lsei_start (encoder); !lsei_end_p (lsei);
  	   lsei_next (&lsei))
          {
! 	  toplevel_node *tnode = lsei_node (lsei);
! 	  symtab_node *node = dyn_cast <symtab_node*> (tnode);
! 	  if (!node)
! 	    continue;
  
  	  /* If symbol is static, rename it if its assembler name
  	     clashes with anything else in this unit.  */
diff -Nrcpad gcc-16-20251026/gcc/lto/lto-symtab.cc gcc-16-20251102/gcc/lto/lto-symtab.cc
*** gcc-16-20251026/gcc/lto/lto-symtab.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto/lto-symtab.cc	Sun Nov  2 22:32:22 2025
*************** lto_symtab_merge_symbols_1 (symtab_node
*** 953,963 ****
  	  else
  	    {
  	      DECL_INITIAL (e->decl) = error_mark_node;
! 	      if (e->lto_file_data)
! 		{
! 		  lto_free_function_in_decl_state_for_node (e);
! 		  e->lto_file_data = NULL;
! 		}
  	      symtab->call_varpool_removal_hooks (dyn_cast<varpool_node *> (e));
  	    }
  	  e->remove_all_references ();
--- 953,959 ----
  	  else
  	    {
  	      DECL_INITIAL (e->decl) = error_mark_node;
! 	      lto_free_function_in_decl_state_for_node (e);
  	      symtab->call_varpool_removal_hooks (dyn_cast<varpool_node *> (e));
  	    }
  	  e->remove_all_references ();
diff -Nrcpad gcc-16-20251026/gcc/lto/lto.cc gcc-16-20251102/gcc/lto/lto.cc
*** gcc-16-20251026/gcc/lto/lto.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto/lto.cc	Sun Nov  2 22:32:22 2025
*************** stream_out_partitions (char *temp_filena
*** 267,273 ****
  	      {
  		/* There are no free tokens, lets do the job outselves.  */
  		stream_out_partitions_1 (temp_filename, blen, min, max);
- 		asm_nodes_output = true;
  		return;
  	      }
  	  }
--- 267,272 ----
*************** stream_out_partitions (char *temp_filena
*** 296,302 ****
        if (jinfo != NULL && jinfo->is_connected)
  	jinfo->disconnect ();
      }
-   asm_nodes_output = true;
  #else
    stream_out_partitions_1 (temp_filename, blen, min, max);
  #endif
--- 295,300 ----
*************** lto_wpa_write_files (void)
*** 381,394 ****
  	       !lsei_end_p (lsei);
  	       lsei_next_in_partition (&lsei))
  	    {
! 	      symtab_node *node = lsei_node (lsei);
! 	      fprintf (symtab->dump_file, "%s ", node->dump_asm_name ());
  	    }
  	  fprintf (symtab->dump_file, "\n  Symbols in boundary: ");
  	  for (lsei = lsei_start (part->encoder); !lsei_end_p (lsei);
  	       lsei_next (&lsei))
  	    {
! 	      symtab_node *node = lsei_node (lsei);
  	      if (!lto_symtab_encoder_in_partition_p (part->encoder, node))
  		{
  		  fprintf (symtab->dump_file, "%s ", node->dump_asm_name ());
--- 379,395 ----
  	       !lsei_end_p (lsei);
  	       lsei_next_in_partition (&lsei))
  	    {
! 	      symtab_node *node = dyn_cast<symtab_node*> (lsei_node (lsei));
! 	      if (node)
! 		fprintf (symtab->dump_file, "%s ", node->dump_asm_name ());
  	    }
  	  fprintf (symtab->dump_file, "\n  Symbols in boundary: ");
  	  for (lsei = lsei_start (part->encoder); !lsei_end_p (lsei);
  	       lsei_next (&lsei))
  	    {
! 	      symtab_node *node = dyn_cast<symtab_node*> (lsei_node (lsei));
! 	      if (!node)
! 		continue;
  	      if (!lto_symtab_encoder_in_partition_p (part->encoder, node))
  		{
  		  fprintf (symtab->dump_file, "%s ", node->dump_asm_name ());
diff -Nrcpad gcc-16-20251026/gcc/lto-cgraph.cc gcc-16-20251102/gcc/lto-cgraph.cc
*** gcc-16-20251026/gcc/lto-cgraph.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto-cgraph.cc	Sun Nov  2 22:32:22 2025
*************** along with GCC; see the file COPYING3.
*** 45,53 ****
  #include "symtab-thunks.h"
  #include "symtab-clones.h"
  
- /* True when asm nodes has been output.  */
- bool asm_nodes_output = false;
- 
  static void output_cgraph_opt_summary (void);
  static void input_cgraph_opt_summary (vec<symtab_node *>  nodes);
  
--- 45,50 ----
*************** lto_symtab_encoder_new (bool for_input)
*** 82,88 ****
    lto_symtab_encoder_t encoder = XCNEW (struct lto_symtab_encoder_d);
  
    if (!for_input)
!     encoder->map = new hash_map<symtab_node *, size_t>;
    encoder->nodes.create (0);
    return encoder;
  }
--- 79,85 ----
    lto_symtab_encoder_t encoder = XCNEW (struct lto_symtab_encoder_d);
  
    if (!for_input)
!     encoder->map = new hash_map<toplevel_node *, size_t>;
    encoder->nodes.create (0);
    return encoder;
  }
*************** lto_symtab_encoder_delete (lto_symtab_en
*** 108,114 ****
  
  int
  lto_symtab_encoder_encode (lto_symtab_encoder_t encoder,
! 			   symtab_node *node)
  {
    int ref;
  
--- 105,111 ----
  
  int
  lto_symtab_encoder_encode (lto_symtab_encoder_t encoder,
! 			   toplevel_node *node)
  {
    int ref;
  
*************** lto_symtab_encoder_encode (lto_symtab_en
*** 140,146 ****
  
  bool
  lto_symtab_encoder_delete_node (lto_symtab_encoder_t encoder,
! 			        symtab_node *node)
  {
    int index;
  
--- 137,143 ----
  
  bool
  lto_symtab_encoder_delete_node (lto_symtab_encoder_t encoder,
! 				toplevel_node *node)
  {
    int index;
  
*************** lto_set_symtab_encoder_encode_initialize
*** 214,220 ****
  
  bool
  lto_symtab_encoder_in_partition_p (lto_symtab_encoder_t encoder,
! 				   symtab_node *node)
  {
    int index = lto_symtab_encoder_lookup (encoder, node);
    if (index == LCC_NOT_FOUND)
--- 211,217 ----
  
  bool
  lto_symtab_encoder_in_partition_p (lto_symtab_encoder_t encoder,
! 				   toplevel_node *node)
  {
    int index = lto_symtab_encoder_lookup (encoder, node);
    if (index == LCC_NOT_FOUND)
*************** lto_symtab_encoder_in_partition_p (lto_s
*** 226,236 ****
  
  void
  lto_set_symtab_encoder_in_partition (lto_symtab_encoder_t encoder,
! 				     symtab_node *node)
  {
    int index = lto_symtab_encoder_encode (encoder, node);
    if (dump_file)
!     fprintf(dump_file, "Node %s, index %d\n", node->asm_name(), index);
    encoder->nodes[index].in_partition = true;
  }
  
--- 223,238 ----
  
  void
  lto_set_symtab_encoder_in_partition (lto_symtab_encoder_t encoder,
! 				     toplevel_node *node)
  {
    int index = lto_symtab_encoder_encode (encoder, node);
    if (dump_file)
!     {
!       if (symtab_node* snode = dyn_cast<symtab_node*> (node))
! 	fprintf (dump_file, "Node %s, index %d\n", snode->asm_name (), index);
!       else
! 	fprintf (dump_file, "Asm node, index %d\n", index);
!     }
    encoder->nodes[index].in_partition = true;
  }
  
*************** output_refs (lto_symtab_encoder_t encode
*** 770,776 ****
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *node = lto_symtab_encoder_deref (encoder, i);
  
        /* IPA_REF_ALIAS references are always preserved
  	 in the boundary.  Alias node can't have other references and
--- 772,781 ----
  
    for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       symtab_node *node = dyn_cast <symtab_node *> (tnode);
!       if (!node)
! 	continue;
  
        /* IPA_REF_ALIAS references are always preserved
  	 in the boundary.  Alias node can't have other references and
*************** compute_ltrans_boundary (lto_symtab_enco
*** 895,901 ****
       pickle those too.  */
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *node = lto_symtab_encoder_deref (encoder, i);
        if (varpool_node *vnode = dyn_cast <varpool_node *> (node))
  	{
  	  if (!lto_symtab_encoder_encode_initializer_p (encoder,
--- 900,906 ----
       pickle those too.  */
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *node = lto_symtab_encoder_deref (encoder, i);
        if (varpool_node *vnode = dyn_cast <varpool_node *> (node))
  	{
  	  if (!lto_symtab_encoder_encode_initializer_p (encoder,
*************** compute_ltrans_boundary (lto_symtab_enco
*** 962,968 ****
       to stay to aid local calling conventions.  */
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       symtab_node *node = lto_symtab_encoder_deref (encoder, i);
        cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
  
        if (node->alias && node->analyzed)
--- 967,977 ----
       to stay to aid local calling conventions.  */
    for (i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       symtab_node *node = dyn_cast <symtab_node *> (tnode);
!       if (!node)
! 	continue;
! 
        cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
  
        if (node->alias && node->analyzed)
*************** compute_ltrans_boundary (lto_symtab_enco
*** 980,985 ****
--- 989,1001 ----
  	    lto_symtab_encoder_encode (encoder, node);
  	}
      }
+ 
+   for (lsei = lsei_start (in_encoder); !lsei_end_p (lsei); lsei_next (&lsei))
+     {
+       toplevel_node *tnode = lsei_node (lsei);
+       if (asm_node* node = dyn_cast <asm_node*> (tnode))
+ 	lto_set_symtab_encoder_in_partition (encoder, node);
+     }
    lto_symtab_encoder_delete (in_encoder);
    return encoder;
  }
*************** output_symtab (void)
*** 1012,1022 ****
    n_nodes = lto_symtab_encoder_size (encoder);
    for (i = 0; i < n_nodes; i++)
      {
!       symtab_node *node = lto_symtab_encoder_deref (encoder, i);
        if (cgraph_node *cnode = dyn_cast <cgraph_node *> (node))
          lto_output_node (ob, cnode, encoder);
!       else
! 	lto_output_varpool_node (ob, dyn_cast<varpool_node *> (node), encoder);
      }
  
    /* Go over the nodes in SET again to write edges.  */
--- 1028,1038 ----
    n_nodes = lto_symtab_encoder_size (encoder);
    for (i = 0; i < n_nodes; i++)
      {
!       toplevel_node *node = lto_symtab_encoder_deref (encoder, i);
        if (cgraph_node *cnode = dyn_cast <cgraph_node *> (node))
          lto_output_node (ob, cnode, encoder);
!       else if (varpool_node *vnode = dyn_cast <varpool_node *> (node))
! 	lto_output_varpool_node (ob, vnode, encoder);
      }
  
    /* Go over the nodes in SET again to write edges.  */
*************** output_symtab (void)
*** 1036,1050 ****
  
    lto_destroy_simple_output_block (ob);
  
!   /* Emit toplevel asms.
!      When doing WPA we must output every asm just once.  Since we do not partition asm
!      nodes at all, output them to first output.  This is kind of hack, but should work
!      well.  */
!   if (!asm_nodes_output && !lto_stream_offload_p)
!     {
!       asm_nodes_output = true;
!       lto_output_toplevel_asms ();
!     }
  
    output_refs (encoder);
  }
--- 1052,1060 ----
  
    lto_destroy_simple_output_block (ob);
  
!   /* Emit toplevel asms.  */
!   if (!lto_stream_offload_p)
!     lto_output_toplevel_asms (encoder);
  
    output_refs (encoder);
  }
*************** output_cgraph_opt_summary (void)
*** 2111,2117 ****
    n_nodes = lto_symtab_encoder_size (encoder);
    for (i = 0; i < n_nodes; i++)
      {
!       symtab_node *node = lto_symtab_encoder_deref (encoder, i);
        cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
        if (cnode && output_cgraph_opt_summary_p (cnode))
  	count++;
--- 2121,2127 ----
    n_nodes = lto_symtab_encoder_size (encoder);
    for (i = 0; i < n_nodes; i++)
      {
!       toplevel_node *node = lto_symtab_encoder_deref (encoder, i);
        cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
        if (cnode && output_cgraph_opt_summary_p (cnode))
  	count++;
*************** output_cgraph_opt_summary (void)
*** 2119,2125 ****
    streamer_write_uhwi (ob, count);
    for (i = 0; i < n_nodes; i++)
      {
!       symtab_node *node = lto_symtab_encoder_deref (encoder, i);
        cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
        if (cnode && output_cgraph_opt_summary_p (cnode))
  	{
--- 2129,2135 ----
    streamer_write_uhwi (ob, count);
    for (i = 0; i < n_nodes; i++)
      {
!       toplevel_node *node = lto_symtab_encoder_deref (encoder, i);
        cgraph_node *cnode = dyn_cast <cgraph_node *> (node);
        if (cnode && output_cgraph_opt_summary_p (cnode))
  	{
diff -Nrcpad gcc-16-20251026/gcc/lto-section-in.cc gcc-16-20251102/gcc/lto-section-in.cc
*** gcc-16-20251026/gcc/lto-section-in.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto-section-in.cc	Sun Nov  2 22:32:22 2025
*************** lto_free_function_in_decl_state_for_node
*** 448,454 ****
        lto_free_function_in_decl_state (*slot);
        node->lto_file_data->function_decl_states->clear_slot (slot);
      }
-   node->lto_file_data = NULL;
  }
  
  
--- 448,453 ----
diff -Nrcpad gcc-16-20251026/gcc/lto-streamer-in.cc gcc-16-20251102/gcc/lto-streamer-in.cc
*** gcc-16-20251026/gcc/lto-streamer-in.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto-streamer-in.cc	Sun Nov  2 22:32:22 2025
*************** lto_input_toplevel_asms (struct lto_file
*** 2004,2009 ****
--- 2004,2010 ----
      {
        asm_node *node = symtab->finalize_toplevel_asm (str);
        node->order = streamer_read_hwi (&ib) + order_base;
+       node->lto_file_data = file_data;
        if (node->order >= symtab->order)
  	symtab->order = node->order + 1;
      }
diff -Nrcpad gcc-16-20251026/gcc/lto-streamer-out.cc gcc-16-20251102/gcc/lto-streamer-out.cc
*** gcc-16-20251026/gcc/lto-streamer-out.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto-streamer-out.cc	Sun Nov  2 22:32:22 2025
*************** output_constructor (struct varpool_node
*** 2554,2567 ****
  /* Emit toplevel asms.  */
  
  void
! lto_output_toplevel_asms (void)
  {
    struct output_block *ob;
-   struct asm_node *can;
    char *section_name;
    struct lto_simple_header_with_strings header;
  
!   if (!symtab->first_asm_symbol ())
      return;
  
    ob = create_output_block (LTO_section_asm);
--- 2554,2571 ----
  /* Emit toplevel asms.  */
  
  void
! lto_output_toplevel_asms (lto_symtab_encoder_t encoder)
  {
    struct output_block *ob;
    char *section_name;
    struct lto_simple_header_with_strings header;
  
!   bool any_asm = false;
!   for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
!     if (is_a <asm_node*> (lto_symtab_encoder_deref (encoder, i)))
!       any_asm = true;
! 
!   if (!any_asm)
      return;
  
    ob = create_output_block (LTO_section_asm);
*************** lto_output_toplevel_asms (void)
*** 2569,2585 ****
    /* Make string 0 be a NULL string.  */
    streamer_write_char_stream (ob->string_stream, 0);
  
!   for (can = symtab->first_asm_symbol (); can; can = can->next)
      {
!       if (TREE_CODE (can->asm_str) != STRING_CST)
  	{
! 	  sorry_at (EXPR_LOCATION (can->asm_str),
  		    "LTO streaming of toplevel extended %<asm%> "
  		    "unimplemented");
  	  continue;
  	}
!       streamer_write_string_cst (ob, ob->main_stream, can->asm_str);
!       streamer_write_hwi (ob, can->order);
      }
  
    streamer_write_string_cst (ob, ob->main_stream, NULL_TREE);
--- 2573,2594 ----
    /* Make string 0 be a NULL string.  */
    streamer_write_char_stream (ob->string_stream, 0);
  
!   for (int i = 0; i < lto_symtab_encoder_size (encoder); i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       asm_node *anode = dyn_cast <asm_node*> (tnode);
!       if (!anode)
! 	continue;
! 
!       if (TREE_CODE (anode->asm_str) != STRING_CST)
  	{
! 	  sorry_at (EXPR_LOCATION (anode->asm_str),
  		    "LTO streaming of toplevel extended %<asm%> "
  		    "unimplemented");
  	  continue;
  	}
!       streamer_write_string_cst (ob, ob->main_stream, anode->asm_str);
!       streamer_write_hwi (ob, anode->order);
      }
  
    streamer_write_string_cst (ob, ob->main_stream, NULL_TREE);
*************** create_order_remap (lto_symtab_encoder_t
*** 2783,2801 ****
  {
    auto_vec<int> orders;
    unsigned i;
-   struct asm_node* anode;
    encoder->order_remap = new hash_map<int_hash<int, -1, -2>, int>;
    unsigned n_nodes = lto_symtab_encoder_size (encoder);
  
    for (i = 0; i < n_nodes; i++)
      orders.safe_push (lto_symtab_encoder_deref (encoder, i)->order);
  
-   if (!asm_nodes_output)
-     {
-       for (anode = symtab->first_asm_symbol (); anode; anode = anode->next)
- 	orders.safe_push (anode->order);
-     }
- 
    orders.qsort (cmp_int);
    int ord = 0;
    int last_order = -1;
--- 2792,2803 ----
*************** create_order_remap (lto_symtab_encoder_t
*** 2809,2822 ****
  	  ord++;
  	}
      }
- 
-   /* Asm nodes are currently always output only into first partition.
-      We can remap already here.  */
-   if (!asm_nodes_output)
-     {
-       for (anode = symtab->first_asm_symbol (); anode; anode = anode->next)
- 	anode->order = *encoder->order_remap->get (anode->order);
-     }
  }
  
  /* Main entry point from the pass manager.  */
--- 2811,2816 ----
*************** lto_output (void)
*** 2831,2836 ****
--- 2825,2837 ----
    lto_symtab_encoder_t encoder = lto_get_out_decl_state ()->symtab_node_encoder;
    auto_vec<symtab_node *> symbols_to_copy;
  
+   if (!flag_wpa)
+     {
+       asm_node *anode;
+       for (anode = symtab->first_asm_symbol (); anode; anode = anode->next)
+ 	lto_set_symtab_encoder_in_partition (encoder, anode);
+     }
+ 
    create_order_remap (encoder);
  
    prune_offload_funcs ();
*************** lto_output (void)
*** 2851,2866 ****
       section copying.  */
    for (i = 0; i < n_nodes; i++)
      {
!       symtab_node *snode = lto_symtab_encoder_deref (encoder, i);
!       if (snode->alias)
  	continue;
!       if (cgraph_node *node = dyn_cast <cgraph_node *> (snode))
  	{
  	  if (lto_symtab_encoder_encode_body_p (encoder, node)
  	      && !node->clone_of)
  	    symbols_to_copy.safe_push (node);
  	}
!       else if (varpool_node *node = dyn_cast <varpool_node *> (snode))
  	{
  	  /* Wrap symbol references inside the ctor in a type
  	     preserving MEM_REF.  */
--- 2852,2869 ----
       section copying.  */
    for (i = 0; i < n_nodes; i++)
      {
!       toplevel_node *tnode = lto_symtab_encoder_deref (encoder, i);
!       symtab_node *node = dyn_cast <symtab_node *> (tnode);
!       if (!node || node->alias)
  	continue;
! 
!       if (cgraph_node *node = dyn_cast <cgraph_node *> (tnode))
  	{
  	  if (lto_symtab_encoder_encode_body_p (encoder, node)
  	      && !node->clone_of)
  	    symbols_to_copy.safe_push (node);
  	}
!       else if (varpool_node *node = dyn_cast <varpool_node *> (tnode))
  	{
  	  /* Wrap symbol references inside the ctor in a type
  	     preserving MEM_REF.  */
*************** produce_symtab (struct output_block *ob)
*** 3202,3208 ****
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
        if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
--- 3205,3214 ----
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       toplevel_node *tnode = lsei_node (lsei);
!       symtab_node *node = dyn_cast<symtab_node*> (tnode);
!       if (!node)
! 	continue;
  
        if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
*************** produce_symtab (struct output_block *ob)
*** 3212,3218 ****
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
        if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
--- 3218,3227 ----
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       toplevel_node *tnode = lsei_node (lsei);
!       symtab_node *node = dyn_cast<symtab_node*> (tnode);
!       if (!node)
! 	continue;
  
        if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
*************** produce_symtab_extension (struct output_
*** 3253,3259 ****
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
        if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
--- 3262,3271 ----
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       toplevel_node *tnode = lsei_node (lsei);
!       symtab_node *node = dyn_cast<symtab_node*> (tnode);
!       if (!node)
! 	continue;
  
        if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
*************** produce_symtab_extension (struct output_
*** 3263,3269 ****
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       symtab_node *node = lsei_node (lsei);
  
        if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
--- 3275,3284 ----
    for (lsei = lsei_start (encoder);
         !lsei_end_p (lsei); lsei_next (&lsei))
      {
!       toplevel_node *tnode = lsei_node (lsei);
!       symtab_node *node = dyn_cast<symtab_node*> (tnode);
!       if (!node)
! 	continue;
  
        if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
  	continue;
diff -Nrcpad gcc-16-20251026/gcc/lto-streamer.h gcc-16-20251102/gcc/lto-streamer.h
*** gcc-16-20251026/gcc/lto-streamer.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/lto-streamer.h	Sun Nov  2 22:32:22 2025
*************** struct lto_stats_d
*** 444,455 ****
  struct lto_encoder_entry
  {
    /* Constructor.  */
!   lto_encoder_entry (symtab_node* n)
      : node (n), in_partition (false), body (false), only_for_inlining (true),
        initializer (false)
    {}
  
!   symtab_node *node;
    /* Is the node in this partition (i.e. ltrans of this partition will
       be responsible for outputting it)? */
    unsigned int in_partition:1;
--- 444,455 ----
  struct lto_encoder_entry
  {
    /* Constructor.  */
!   lto_encoder_entry (toplevel_node* n)
      : node (n), in_partition (false), body (false), only_for_inlining (true),
        initializer (false)
    {}
  
!   toplevel_node *node;
    /* Is the node in this partition (i.e. ltrans of this partition will
       be responsible for outputting it)? */
    unsigned int in_partition:1;
*************** struct lto_encoder_entry
*** 468,474 ****
  struct lto_symtab_encoder_d
  {
    vec<lto_encoder_entry> nodes;
!   hash_map<symtab_node *, size_t> *map;
  
    /* Mapping of input order of nodes onto output order.  */
    hash_map<int_hash<int, -1, -2>, int> *order_remap;
--- 468,474 ----
  struct lto_symtab_encoder_d
  {
    vec<lto_encoder_entry> nodes;
!   hash_map<toplevel_node *, size_t> *map;
  
    /* Mapping of input order of nodes onto output order.  */
    hash_map<int_hash<int, -1, -2>, int> *order_remap;
*************** extern void lto_output_fn_decl_ref (stru
*** 897,903 ****
  				    struct lto_output_stream *, tree);
  extern tree lto_input_var_decl_ref (lto_input_block *, lto_file_decl_data *);
  extern tree lto_input_fn_decl_ref (lto_input_block *, lto_file_decl_data *);
! extern void lto_output_toplevel_asms (void);
  extern void produce_asm (struct output_block *ob);
  extern void lto_output ();
  extern void produce_asm_for_decls ();
--- 897,903 ----
  				    struct lto_output_stream *, tree);
  extern tree lto_input_var_decl_ref (lto_input_block *, lto_file_decl_data *);
  extern tree lto_input_fn_decl_ref (lto_input_block *, lto_file_decl_data *);
! extern void lto_output_toplevel_asms (lto_symtab_encoder_t);
  extern void produce_asm (struct output_block *ob);
  extern void lto_output ();
  extern void produce_asm_for_decls ();
*************** void lto_prepare_function_for_streaming
*** 916,934 ****
  
  
  /* In lto-cgraph.cc  */
- extern bool asm_nodes_output;
  lto_symtab_encoder_t lto_symtab_encoder_new (bool);
! int lto_symtab_encoder_encode (lto_symtab_encoder_t, symtab_node *);
  void lto_symtab_encoder_delete (lto_symtab_encoder_t);
! bool lto_symtab_encoder_delete_node (lto_symtab_encoder_t, symtab_node *);
  bool lto_symtab_encoder_encode_body_p (lto_symtab_encoder_t,
  				       struct cgraph_node *);
  bool lto_symtab_encoder_only_for_inlining_p (lto_symtab_encoder_t,
  					     struct cgraph_node *);
  bool lto_symtab_encoder_in_partition_p (lto_symtab_encoder_t,
! 					symtab_node *);
  void lto_set_symtab_encoder_in_partition (lto_symtab_encoder_t,
! 					  symtab_node *);
  
  bool lto_symtab_encoder_encode_initializer_p (lto_symtab_encoder_t,
  					      varpool_node *);
--- 916,933 ----
  
  
  /* In lto-cgraph.cc  */
  lto_symtab_encoder_t lto_symtab_encoder_new (bool);
! int lto_symtab_encoder_encode (lto_symtab_encoder_t, toplevel_node *);
  void lto_symtab_encoder_delete (lto_symtab_encoder_t);
! bool lto_symtab_encoder_delete_node (lto_symtab_encoder_t, toplevel_node *);
  bool lto_symtab_encoder_encode_body_p (lto_symtab_encoder_t,
  				       struct cgraph_node *);
  bool lto_symtab_encoder_only_for_inlining_p (lto_symtab_encoder_t,
  					     struct cgraph_node *);
  bool lto_symtab_encoder_in_partition_p (lto_symtab_encoder_t,
! 					toplevel_node *);
  void lto_set_symtab_encoder_in_partition (lto_symtab_encoder_t,
! 					  toplevel_node *);
  
  bool lto_symtab_encoder_encode_initializer_p (lto_symtab_encoder_t,
  					      varpool_node *);
*************** lto_symtab_encoder_size (lto_symtab_enco
*** 1104,1110 ****
  
  inline int
  lto_symtab_encoder_lookup (lto_symtab_encoder_t encoder,
! 			   symtab_node *node)
  {
    size_t *slot = encoder->map->get (node);
    return (slot && *slot ? *(slot) - 1 : LCC_NOT_FOUND);
--- 1103,1109 ----
  
  inline int
  lto_symtab_encoder_lookup (lto_symtab_encoder_t encoder,
! 			   toplevel_node *node)
  {
    size_t *slot = encoder->map->get (node);
    return (slot && *slot ? *(slot) - 1 : LCC_NOT_FOUND);
*************** lsei_next (lto_symtab_encoder_iterator *
*** 1125,1131 ****
  }
  
  /* Return the node pointed to by LSI.  */
! inline symtab_node *
  lsei_node (lto_symtab_encoder_iterator lsei)
  {
    return lsei.encoder->nodes[lsei.index].node;
--- 1124,1130 ----
  }
  
  /* Return the node pointed to by LSI.  */
! inline toplevel_node *
  lsei_node (lto_symtab_encoder_iterator lsei)
  {
    return lsei.encoder->nodes[lsei.index].node;
*************** lsei_varpool_node (lto_symtab_encoder_it
*** 1147,1153 ****
  
  /* Return the cgraph node corresponding to REF using ENCODER.  */
  
! inline symtab_node *
  lto_symtab_encoder_deref (lto_symtab_encoder_t encoder, int ref)
  {
    if (ref == LCC_NOT_FOUND)
--- 1146,1152 ----
  
  /* Return the cgraph node corresponding to REF using ENCODER.  */
  
! inline toplevel_node *
  lto_symtab_encoder_deref (lto_symtab_encoder_t encoder, int ref)
  {
    if (ref == LCC_NOT_FOUND)
diff -Nrcpad gcc-16-20251026/gcc/m2/ChangeLog gcc-16-20251102/gcc/m2/ChangeLog
*** gcc-16-20251026/gcc/m2/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/ChangeLog	Sun Nov  2 22:32:22 2025
***************
*** 1,3 ****
--- 1,24 ----
+ 2025-10-30  Gaius Mulley  <gaiusmod2@gmail.com>
+ 
+ 	PR modula2/122485
+ 	* gm2-compiler/M2Comp.mod (Pass0CheckDef): Add spell check
+ 	format specifier filtering on module names.
+ 	* gm2-compiler/M2MetaError.mod (errorBlock): New field
+ 	filterDef.
+ 	(initErrorBlock): Initialize filterDef.
+ 	(continuation): Add 'D' filter on definition module specifier.
+ 	(SpellHint): Rewrite to check for filterDef and defimp symbols.
+ 	(FilterOnDefinitionModule): New procedure.
+ 	* gm2-compiler/M2Quads.mod (BuildSizeFunction): Rewrite to
+ 	ensure variables are initialized.
+ 	* gm2-compiler/M2StackSpell.def (GetDefModuleSpellHint): New
+ 	procedure function.
+ 	* gm2-compiler/M2StackSpell.mod (GetDefModuleSpellHint): New
+ 	procedure function.
+ 	(CandidatePushName): New procedure.
+ 	(BuildHintStr): New procedure.
+ 	(CheckForHintStr): Rewrite.
+ 
  2025-10-24  Gaius Mulley  <gaiusmod2@gmail.com>
  
  	PR modula2/122407
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/M2Comp.mod gcc-16-20251102/gcc/m2/gm2-compiler/M2Comp.mod
*** gcc-16-20251026/gcc/m2/gm2-compiler/M2Comp.mod	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/M2Comp.mod	Sun Nov  2 22:32:22 2025
*************** BEGIN
*** 851,862 ****
              MergeDeps (DepContent, ChildDep, LibName)
           ELSE
              (* Unrecoverable error.  *)
!             MetaErrorString1 (Sprintf1 (InitString ('file {%%1EUAF%s} containing module {%%1a} cannot be found'),
                                          FileName), sym)
           END
        ELSE
!          (* Unrecoverable error.  *)
!          MetaError1 ('the file containing the definition module {%1EMAa} cannot be found', sym)
        END ;
        ModuleType := Implementation
     ELSE
--- 851,861 ----
              MergeDeps (DepContent, ChildDep, LibName)
           ELSE
              (* Unrecoverable error.  *)
!             MetaErrorString1 (Sprintf1 (InitString ('file {%%1EUAF%s} containing module {%%1a} cannot be found {%%1&Ds}'),
                                          FileName), sym)
           END
        ELSE
!          MetaError1 ('the file containing the definition module {%1EMAa} cannot be found {%1&Ds}', sym)
        END ;
        ModuleType := Implementation
     ELSE
*************** BEGIN
*** 928,942 ****
              qprintf0 ('\n') ;
              CloseSource
           ELSE
!             (* It is quite legitimate to implement a module in C (and pretend it was a M2
                 implementation) providing that it is not the main program module and the
                 definition module does not declare a hidden type when -fextended-opaque
                 is used.  *)
              IF (NOT WholeProgram) OR (sym = Main) OR IsHiddenTypeDeclared (sym)
              THEN
                 (* Unrecoverable error.  *)
!                MetaErrorString1 (Sprintf1 (InitString ('file {%%1EUAF%s} containing module {%%1a} cannot be found'),
!                                            FileName), sym) ;
              END
           END
        END
--- 927,941 ----
              qprintf0 ('\n') ;
              CloseSource
           ELSE
!             (* It is legitimate to implement a module in C (and pretend it was a M2
                 implementation) providing that it is not the main program module and the
                 definition module does not declare a hidden type when -fextended-opaque
                 is used.  *)
              IF (NOT WholeProgram) OR (sym = Main) OR IsHiddenTypeDeclared (sym)
              THEN
                 (* Unrecoverable error.  *)
!                MetaErrorString1 (Sprintf1 (InitString ('file {%%1EUAF%s} containing module {%%1a} cannot be found {%%1&Ds}'),
!                                            FileName), sym)
              END
           END
        END
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/M2MetaError.mod gcc-16-20251102/gcc/m2/gm2-compiler/M2MetaError.mod
*** gcc-16-20251026/gcc/m2/gm2-compiler/M2MetaError.mod	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/M2MetaError.mod	Sun Nov  2 22:32:22 2025
*************** FROM SYSTEM IMPORT ADDRESS ;
*** 42,48 ****
  FROM M2Error IMPORT MoveError ;
  FROM M2Debug IMPORT Assert ;
  FROM Storage IMPORT ALLOCATE ;
- FROM M2StackSpell IMPORT GetSpellHint ;
  
  FROM Indexing IMPORT Index, InitIndex, KillIndex, GetIndice, PutIndice,
                       DeleteIndice, HighIndice ;
--- 42,47 ----
*************** IMPORT M2Error ;
*** 74,79 ****
--- 73,79 ----
  IMPORT FilterError ;
  
  FROM FilterError IMPORT Filter, AddSymError, IsSymError ;
+ FROM M2StackSpell IMPORT GetDefModuleSpellHint, GetSpellHint ;
  
  
  CONST
*************** TYPE
*** 100,105 ****
--- 100,106 ----
                     len,
                     ini       : INTEGER ;
                     vowel,
+                    filterDef,
                     importHint,
                     exportHint,
                     withStackHint,
*************** BEGIN
*** 533,538 ****
--- 534,540 ----
        ini        := 0 ;
        glyph      := FALSE ;  (* Nothing to output yet.  *)
        vowel      := FALSE ;  (* Check for a vowel when outputing string?  *)
+       filterDef  := FALSE ;  (* Filter on definition module list?  *)
        importHint := FALSE;
        exportHint := FALSE ;
        withStackHint := FALSE ;
*************** END op ;
*** 1840,1846 ****
  
  
  (*
!    continuation := {':'|'1'|'2'|'3'|'4'|'i'|'s'|'x'|'w'} =:
  *)
  
  PROCEDURE continuation (VAR eb: errorBlock;
--- 1842,1848 ----
  
  
  (*
!    continuation := {':'|'1'|'2'|'3'|'4'|'i'|'s'|'x'|'w'|'D'} =:
  *)
  
  PROCEDURE continuation (VAR eb: errorBlock;
*************** BEGIN
*** 1860,1866 ****
        'i':  AddImportsHint (eb) |
        's':  SpellHint (eb, sym, bol) |
        'x':  AddExportsHint (eb) |
!       'w':  AddWithStackHint (eb)
  
        ELSE
           InternalFormat (eb, 'expecting one of [:1234isxw]',
--- 1862,1869 ----
        'i':  AddImportsHint (eb) |
        's':  SpellHint (eb, sym, bol) |
        'x':  AddExportsHint (eb) |
!       'w':  AddWithStackHint (eb) |
!       'D':  FilterOnDefinitionModule (eb)
  
        ELSE
           InternalFormat (eb, 'expecting one of [:1234isxw]',
*************** END JoinSentances ;
*** 1956,1964 ****
  
  PROCEDURE SpellHint (VAR eb: errorBlock; sym: ARRAY OF CARDINAL; bol: CARDINAL) ;
  BEGIN
!    IF (bol <= HIGH (sym)) AND IsUnknown (sym[bol])
     THEN
!       JoinSentances (eb, GetSpellHint (sym[bol]))
     END
  END SpellHint ;
  
--- 1959,1973 ----
  
  PROCEDURE SpellHint (VAR eb: errorBlock; sym: ARRAY OF CARDINAL; bol: CARDINAL) ;
  BEGIN
!    IF bol <= HIGH (sym)
     THEN
!       IF eb.filterDef AND IsDefImp (sym[bol])
!       THEN
!          JoinSentances (eb, GetDefModuleSpellHint (sym[bol]))
!       ELSIF IsUnknown (sym[bol])
!       THEN
!          JoinSentances (eb, GetSpellHint (sym[bol]))
!       END
     END
  END SpellHint ;
  
*************** END AddWithStackHint ;
*** 1994,1999 ****
--- 2003,2018 ----
  
  
  (*
+    FilterOnDefinitionModule - turn on filtering and include all the definition modules.
+ *)
+ 
+ PROCEDURE FilterOnDefinitionModule (VAR eb: errorBlock) ;
+ BEGIN
+    eb.filterDef := TRUE
+ END FilterOnDefinitionModule ;
+ 
+ 
+ (*
     changeColor - changes to color, c.
  *)
  
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/M2Quads.mod gcc-16-20251102/gcc/m2/gm2-compiler/M2Quads.mod
*** gcc-16-20251026/gcc/m2/gm2-compiler/M2Quads.mod	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/M2Quads.mod	Sun Nov  2 22:32:22 2025
*************** BEGIN
*** 10697,10740 ****
                     NoOfParam) ;
        resulttok := functok ;
        ReturnVar := MakeConstLit (resulttok, MakeKey('0'), Cardinal)
!    ELSIF IsAModula2Type (OperandT (1))
!    THEN
!       paramtok := OperandTok (1) ;
!       resulttok := MakeVirtualTok (functok, functok, paramtok) ;
!       BuildSizeCheckEnd (ProcSym) ;   (* Quadruple generation now on.  *)
!       ReturnVar := MakeTemporary (resulttok, ImmediateValue) ;
!       GenQuadO (resulttok, SizeOp, ReturnVar, NulSym, OperandT(1), TRUE)
!    ELSIF IsVar (OperandT (1))
!    THEN
!       BuildSizeCheckEnd (ProcSym) ;   (* Quadruple generation now on.  *)
!       Type := GetSType (OperandT (1)) ;
        paramtok := OperandTok (1) ;
        resulttok := MakeVirtualTok (functok, functok, paramtok) ;
!       IF IsUnbounded (Type)
        THEN
!          (* Eg. SIZE(a) ; where a is unbounded dereference HIGH and multiply by the TYPE.  *)
!          dim := OperandD (1) ;
!          IF dim = 0
           THEN
!             ReturnVar := calculateMultipicand (resulttok, OperandT (1), Type, dim)
           ELSE
!             ReturnVar := calculateMultipicand (resulttok, OperandA (1), Type, dim)
           END
        ELSE
!          ReturnVar := MakeTemporary (resulttok, ImmediateValue) ;
!          IF Type = NulSym
!          THEN
!             MetaErrorT1 (resulttok,
!                          'cannot get the type and size of {%1Ead}', OperandT (1))
!          END ;
!          GenQuadO (resulttok, SizeOp, ReturnVar, NulSym, Type, TRUE)
        END
-    ELSE
-       paramtok := OperandTok (1) ;
-       MetaErrorT1 (paramtok,
-                    '{%E}SYSTEM procedure {%kSIZE} expects a variable or type as its parameter, seen {%1Ed} {%1&s}',
-                    OperandT (1)) ;
-       ReturnVar := MakeConstLit (resulttok, MakeKey('0'), Cardinal)
     END ;
     PopN (NoOfParam+1) ;       (* Destroy the arguments and function.  *)
     PushTFtok (ReturnVar, GetSType(ProcSym), resulttok)
--- 10697,10739 ----
                     NoOfParam) ;
        resulttok := functok ;
        ReturnVar := MakeConstLit (resulttok, MakeKey('0'), Cardinal)
!    ELSE
        paramtok := OperandTok (1) ;
        resulttok := MakeVirtualTok (functok, functok, paramtok) ;
!       IF IsAModula2Type (OperandT (1))
        THEN
!          BuildSizeCheckEnd (ProcSym) ;   (* Quadruple generation now on.  *)
!          ReturnVar := MakeTemporary (resulttok, ImmediateValue) ;
!          GenQuadO (resulttok, SizeOp, ReturnVar, NulSym, OperandT(1), TRUE)
!       ELSIF IsVar (OperandT (1))
!       THEN
!          BuildSizeCheckEnd (ProcSym) ;   (* Quadruple generation now on.  *)
!          Type := GetSType (OperandT (1)) ;
!          IF IsUnbounded (Type)
           THEN
!             (* Eg. SIZE(a) ; where a is unbounded dereference HIGH and multiply by the TYPE.  *)
!             dim := OperandD (1) ;
!             IF dim = 0
!             THEN
!                ReturnVar := calculateMultipicand (resulttok, OperandT (1), Type, dim)
!             ELSE
!                ReturnVar := calculateMultipicand (resulttok, OperandA (1), Type, dim)
!             END
           ELSE
!             ReturnVar := MakeTemporary (resulttok, ImmediateValue) ;
!             IF Type = NulSym
!             THEN
!                MetaErrorT1 (resulttok,
!                             'cannot get the type and size of {%1Ead}', OperandT (1))
!             END ;
!             GenQuadO (resulttok, SizeOp, ReturnVar, NulSym, Type, TRUE)
           END
        ELSE
!          MetaErrorT1 (paramtok,
!                       '{%E}SYSTEM procedure {%kSIZE} expects a variable or type as its parameter, seen {%1Ed} {%1&s}',
!                       OperandT (1)) ;
!          ReturnVar := MakeConstLit (paramtok, MakeKey('0'), Cardinal)
        END
     END ;
     PopN (NoOfParam+1) ;       (* Destroy the arguments and function.  *)
     PushTFtok (ReturnVar, GetSType(ProcSym), resulttok)
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/M2StackSpell.def gcc-16-20251102/gcc/m2/gm2-compiler/M2StackSpell.def
*** gcc-16-20251026/gcc/m2/gm2-compiler/M2StackSpell.def	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/M2StackSpell.def	Sun Nov  2 22:32:22 2025
*************** PROCEDURE GetRecordField (tokno: CARDINA
*** 59,62 ****
--- 59,72 ----
                            fieldName: Name) : CARDINAL ;
  
  
+ (*
+    GetDefModuleSpellHint - return a string describing a spelling
+                            hint for the definition module name
+                            similiar to unknown.  NIL is returned
+                            if no hint can be given.
+ *)
+ 
+ PROCEDURE GetDefModuleSpellHint (defimp: CARDINAL) : String ;
+ 
+ 
  END M2StackSpell.
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/M2StackSpell.mod gcc-16-20251102/gcc/m2/gm2-compiler/M2StackSpell.mod
*** gcc-16-20251026/gcc/m2/gm2-compiler/M2StackSpell.mod	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/M2StackSpell.mod	Sun Nov  2 22:32:22 2025
*************** IMPLEMENTATION MODULE M2StackSpell ;
*** 23,37 ****
  
  FROM SymbolTable IMPORT NulSym, IsModule, IsDefImp, IsRecord,
                          IsEnumeration, IsProcedure, GetNth,
!                         GetSymName, GetSym, GetLocalSym,
!                         UnknownReported,
                          ForeachProcedureDo, ForeachLocalSymDo,
                          ForeachFieldEnumerationDo ;
  
  FROM SymbolKey IMPORT PerformOperation ;
  FROM DynamicStrings IMPORT InitStringCharStar, InitString, Mark, string, ConCat ;
  FROM FormatStrings IMPORT Sprintf1, Sprintf2, Sprintf3 ;
! FROM NameKey IMPORT KeyToCharStar ;
  FROM M2MetaError IMPORT MetaErrorStringT0 ;
  
  FROM M2StackWord IMPORT StackOfWord, PushWord, PopWord,
--- 23,39 ----
  
  FROM SymbolTable IMPORT NulSym, IsModule, IsDefImp, IsRecord,
                          IsEnumeration, IsProcedure, GetNth,
!                         GetSymName, GetSym, GetLocalSym, GetScope,
!                         UnknownReported, IsUnknown,
!                         GetUnknownOnImport, GetUnknownDeclScope,
!                         ForeachExportedDo,
                          ForeachProcedureDo, ForeachLocalSymDo,
                          ForeachFieldEnumerationDo ;
  
  FROM SymbolKey IMPORT PerformOperation ;
  FROM DynamicStrings IMPORT InitStringCharStar, InitString, Mark, string, ConCat ;
  FROM FormatStrings IMPORT Sprintf1, Sprintf2, Sprintf3 ;
! FROM NameKey IMPORT KeyToCharStar, NulName ;
  FROM M2MetaError IMPORT MetaErrorStringT0 ;
  
  FROM M2StackWord IMPORT StackOfWord, PushWord, PopWord,
*************** FROM M2StackWord IMPORT StackOfWord, Pus
*** 39,44 ****
--- 41,47 ----
                          NoOfItemsInStackWord, PeepWord ;
  
  FROM CDataTypes IMPORT ConstCharStar ;
+ FROM M2Batch IMPORT GetModuleNo ;
  
  IMPORT m2spellcheck ;
  FROM m2spellcheck IMPORT Candidates ;
*************** END GetRecordField ;
*** 97,102 ****
--- 100,159 ----
  
  
  (*
+    CandidatePushName - push a symbol name to the candidate list.
+ *)
+ 
+ PROCEDURE CandidatePushName (cand: Candidates; sym: CARDINAL) ;
+ VAR
+    str: String ;
+ BEGIN
+    str := InitStringCharStar (KeyToCharStar (GetSymName (sym))) ;
+    m2spellcheck.Push (cand, string (str)) ;
+    INC (PushCount)
+ END CandidatePushName ;
+ 
+ 
+ (*
+    GetDefModuleSpellHint - return a string describing a spelling
+                            hint for the definition module name
+                            similiar to defimp.  The premise is that
+                            defimp has been misspelt.  NIL is returned
+                            if no hint can be given.
+ *)
+ 
+ PROCEDURE GetDefModuleSpellHint (defimp: CARDINAL) : String ;
+ VAR
+    i        : CARDINAL ;
+    sym      : CARDINAL ;
+    cand     : Candidates ;
+    misspell,
+    content  : ConstCharStar ;
+    HintStr  : String ;
+ BEGIN
+    HintStr := NIL ;
+    IF GetSymName (defimp) # NulName
+    THEN
+       misspell := KeyToCharStar (GetSymName (defimp)) ;
+       i := 1 ;
+       sym := GetModuleNo (i) ;
+       cand := m2spellcheck.InitCandidates () ;
+       WHILE sym # NulSym DO
+          IF sym # defimp
+          THEN
+             CandidatePushName (cand, sym)
+          END ;
+          INC (i) ;
+          sym := GetModuleNo (i)
+       END ;
+       content := m2spellcheck.FindClosestCharStar (cand, misspell) ;
+       HintStr := BuildHintStr (HintStr, content) ;
+       m2spellcheck.KillCandidates (cand)
+    END ;
+    RETURN AddPunctuation (HintStr, '?')
+ END GetDefModuleSpellHint ;
+ 
+ 
+ (*
     Push - push a scope onto the spelling stack.
            sym might be a ModSym, DefImpSym or a varsym
            of a record type denoting a with statement.
*************** VAR
*** 124,131 ****
     PushCount    : CARDINAL ;
     PushCandidate: Candidates ;
  
  (*
!    PushName -
  *)
  
  PROCEDURE PushName (sym: CARDINAL) ;
--- 181,189 ----
     PushCount    : CARDINAL ;
     PushCandidate: Candidates ;
  
+ 
  (*
!    PushName - push a name to the candidate vec.
  *)
  
  PROCEDURE PushName (sym: CARDINAL) ;
*************** END PushCandidates ;
*** 184,189 ****
--- 242,271 ----
  
  
  (*
+    BuildHintStr - create the did you mean hint and return it
+                   if HintStr is NIL.  Otherwise append a hint
+                   to HintStr.  If content is NIL then return NIL.
+ *)
+ 
+ PROCEDURE BuildHintStr (HintStr: String; content: ConstCharStar) : String ;
+ VAR
+    str: String ;
+ BEGIN
+    IF content # NIL
+    THEN
+       str := InitStringCharStar (content) ;
+       IF HintStr = NIL
+       THEN
+          RETURN Sprintf1 (Mark (InitString (", did you mean %s")), str)
+       ELSE
+          RETURN Sprintf2 (Mark (InitString ("%s or %s")), HintStr, str)
+       END
+    END ;
+    RETURN NIL
+ END BuildHintStr ;
+ 
+ 
+ (*
     CheckForHintStr - lookup a spell hint matching misspelt.  If one exists
                       then append it to HintStr.  Return HintStr.
  *)
*************** PROCEDURE CheckForHintStr (sym: CARDINAL
*** 193,199 ****
  VAR
     cand   : Candidates ;
     content: ConstCharStar ;
-    str    : String ;
  BEGIN
     IF IsModule (sym) OR IsDefImp (sym) OR IsProcedure (sym) OR
        IsRecord (sym) OR IsEnumeration (sym)
--- 275,280 ----
*************** BEGIN
*** 201,221 ****
        cand := m2spellcheck.InitCandidates () ;
        IF PushCandidates (cand, sym) > 1
        THEN
!          content := m2spellcheck.FindClosestCharStar (cand, string (misspelt)) ;
        ELSE
           content := NIL
        END ;
        m2spellcheck.KillCandidates (cand) ;
!       IF content # NIL
!       THEN
!          str := InitStringCharStar (content) ;
!          IF HintStr = NIL
!          THEN
!             RETURN Sprintf1 (Mark (InitString (", did you mean %s")), str)
!          ELSE
!             RETURN Sprintf2 (Mark (InitString ("%s or %s")), HintStr, str)
!          END
!       END
     END ;
     RETURN HintStr
  END CheckForHintStr ;
--- 282,293 ----
        cand := m2spellcheck.InitCandidates () ;
        IF PushCandidates (cand, sym) > 1
        THEN
!          content := m2spellcheck.FindClosestCharStar (cand, string (misspelt))
        ELSE
           content := NIL
        END ;
        m2spellcheck.KillCandidates (cand) ;
!       HintStr := BuildHintStr (HintStr, content)
     END ;
     RETURN HintStr
  END CheckForHintStr ;
*************** END AddPunctuation ;
*** 241,246 ****
--- 313,364 ----
  *)
  
  PROCEDURE GetSpellHint (unknown: CARDINAL) : String ;
+ BEGIN
+    IF IsUnknown (unknown) AND
+       GetUnknownOnImport (unknown) AND
+       (GetUnknownDeclScope (unknown) # GetScope (unknown))
+    THEN
+       (* It was created during an import statement.  *)
+       RETURN GetExportedSpellHint (unknown, GetUnknownDeclScope (unknown))
+    END ;
+    RETURN GetScopeSpellHint (unknown)
+ END GetSpellHint ;
+ 
+ 
+ (*
+    GetExportedSpellHint - return a string describing a spelling hint
+                           using the module exported identifiers.
+ *)
+ 
+ PROCEDURE GetExportedSpellHint (unknown, module: CARDINAL) : String ;
+ VAR
+    content : ConstCharStar ;
+    misspell,
+    HintStr : String ;
+ BEGIN
+    misspell := InitStringCharStar (KeyToCharStar (GetSymName (unknown))) ;
+    HintStr := NIL ;
+    PushCount := 0 ;
+    PushCandidate := m2spellcheck.InitCandidates () ;
+    ForeachExportedDo (module, PushName) ;
+    ForeachLocalSymDo (module, PushName) ;
+    IF PushCount > 0
+    THEN
+       content := m2spellcheck.FindClosestCharStar (PushCandidate,
+                                                    string (misspell)) ;
+       HintStr := BuildHintStr (HintStr, content)
+    END ;
+    m2spellcheck.KillCandidates (PushCandidate) ;
+    RETURN AddPunctuation (HintStr, '?')
+ END GetExportedSpellHint ;
+ 
+ 
+ (*
+    GetScopeSpellHint - return a string describing a spelling hint
+                        using the visible scopes.
+ *)
+ 
+ PROCEDURE GetScopeSpellHint (unknown: CARDINAL) : String ;
  VAR
     i, n     : CARDINAL ;
     sym      : CARDINAL ;
*************** BEGIN
*** 262,268 ****
        INC (i)
     END ;
     RETURN AddPunctuation (HintStr, '?')
! END GetSpellHint ;
  
  
  (*
--- 380,386 ----
        INC (i)
     END ;
     RETURN AddPunctuation (HintStr, '?')
! END GetScopeSpellHint ;
  
  
  (*
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/P1Build.bnf gcc-16-20251102/gcc/m2/gm2-compiler/P1Build.bnf
*** gcc-16-20251026/gcc/m2/gm2-compiler/P1Build.bnf	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/P1Build.bnf	Sun Nov  2 22:32:22 2025
*************** END Ident ;
*** 358,366 ****
  *)
  
  PROCEDURE IdentScope (stopset0: SetOfStop0; stopset1: SetOfStop1; stopset2: SetOfStop2) ;
  BEGIN
!    Ident(stopset0, stopset1, stopset2) ;
!    AddNameToScope(LastIdent)
  END IdentScope ;
  
  
--- 358,369 ----
  *)
  
  PROCEDURE IdentScope (stopset0: SetOfStop0; stopset1: SetOfStop1; stopset2: SetOfStop2) ;
+ VAR
+    tokpos: CARDINAL ;
  BEGIN
!    tokpos := GetTokenNo () ;
!    Ident (stopset0, stopset1, stopset2) ;
!    AddNameToScope (tokpos, LastIdent)
  END IdentScope ;
  
  
*************** PROCEDURE PossiblyExportIdent (stopset0:
*** 374,387 ****
  VAR
     nothing: CARDINAL ;
  BEGIN
!    AddNameToScope(makekey(currentstring)) ;
!    PushTFtok(makekey(currentstring), identtok, GetTokenNo()) ;
     CheckExplicitExported ;
!    IF NOT IsAutoPushOn()
     THEN
!       PopT(nothing)
     END ;
!    Expect(identtok, stopset0, stopset1, stopset2)
  END PossiblyExportIdent ;
  
  
--- 377,390 ----
  VAR
     nothing: CARDINAL ;
  BEGIN
!    AddNameToScope (GetTokenNo (), makekey (currentstring)) ;
!    PushTFtok (makekey (currentstring), identtok, GetTokenNo ()) ;
     CheckExplicitExported ;
!    IF NOT IsAutoPushOn ()
     THEN
!       PopT (nothing)
     END ;
!    Expect (identtok, stopset0, stopset1, stopset2)
  END PossiblyExportIdent ;
  
  
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/P1SymBuild.mod gcc-16-20251102/gcc/m2/gm2-compiler/P1SymBuild.mod
*** gcc-16-20251026/gcc/m2/gm2-compiler/P1SymBuild.mod	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/P1SymBuild.mod	Sun Nov  2 22:32:22 2025
*************** FROM M2Reserved IMPORT ImportTok, Export
*** 39,44 ****
--- 39,45 ----
  
  FROM FifoQueue IMPORT PutEnumerationIntoFifoQueue ;
  FROM P0SymBuild IMPORT EnterBlock, LeaveBlock ;
+ FROM libc IMPORT printf ;
  
  FROM SymbolTable IMPORT NulSym,
                          ModeOfAddr,
*************** BEGIN
*** 472,480 ****
                               OperandT(n+1)) ;
        i := 1 ;
        WHILE i<=n DO
- (*
-          WriteString('Importing ') ; WriteKey(Operand(j)) ; WriteString(' from ') ; WriteKey(GetSymName(ModSym)) ; WriteLn ;
- *)
           Sym := GetExported (OperandTok (n+1-i),
                               ModSym, OperandT (n+1-i)) ;
           PutImported (Sym) ;
--- 473,478 ----
*************** BEGIN
*** 619,625 ****
        (* Ident List contains list of objects *)
        i := 1 ;
        WHILE i<=n DO
!          AddNameToImportList (OperandT (i)) ;
           INC (i)
        END
     ELSE
--- 617,623 ----
        (* Ident List contains list of objects *)
        i := 1 ;
        WHILE i<=n DO
!          AddNameToImportList (OperandTok (i), OperandT (i)) ;
           INC (i)
        END
     ELSE
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/SymbolTable.def gcc-16-20251102/gcc/m2/gm2-compiler/SymbolTable.def
*** gcc-16-20251026/gcc/m2/gm2-compiler/SymbolTable.def	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/SymbolTable.def	Sun Nov  2 22:32:22 2025
*************** PROCEDURE UnknownReported (sym: CARDINAL
*** 2136,2141 ****
--- 2136,2155 ----
  
  
  (*
+    GetUnknownOnImport - returns the onimport field of unknown sym.
+ *)
+ 
+ PROCEDURE GetUnknownOnImport (sym: CARDINAL) : BOOLEAN ;
+ 
+ 
+ (*
+    GetUnknownDeclScope - returns the decl scope of unknown sym.
+ *)
+ 
+ PROCEDURE GetUnknownDeclScope (sym: CARDINAL) : CARDINAL ;
+ 
+ 
+ (*
     IsReallyPointer - returns TRUE is sym is a pointer, address or a
                       type declared as a pointer or address.
  *)
*************** PROCEDURE ResolveConstructorTypes ;
*** 2613,2619 ****
                      current scope.
  *)
  
! PROCEDURE AddNameToScope (n: Name) ;
  
  
  (*
--- 2627,2633 ----
                      current scope.
  *)
  
! PROCEDURE AddNameToScope (tok: CARDINAL; n: Name) ;
  
  
  (*
*************** PROCEDURE AddNameToScope (n: Name) ;
*** 2621,2627 ****
                           module.
  *)
  
! PROCEDURE AddNameToImportList (n: Name) ;
  
  
  (*
--- 2635,2641 ----
                           module.
  *)
  
! PROCEDURE AddNameToImportList (tok: CARDINAL; n: Name) ;
  
  
  (*
diff -Nrcpad gcc-16-20251026/gcc/m2/gm2-compiler/SymbolTable.mod gcc-16-20251102/gcc/m2/gm2-compiler/SymbolTable.mod
*** gcc-16-20251026/gcc/m2/gm2-compiler/SymbolTable.mod	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/m2/gm2-compiler/SymbolTable.mod	Sun Nov  2 22:32:22 2025
*************** TYPE
*** 230,235 ****
--- 230,239 ----
     SymUndefined = RECORD
                       name      : Name ;       (* Index into name array, name *)
                                                (* of record.                  *)
+                      declScope : CARDINAL ;   (* Scope where unknown is      *)
+                                               (* created.                    *)
+                      onImport  : BOOLEAN ;    (* Was it created during an    *)
+                                               (* import?                     *)
                       oafamily  : CARDINAL ;   (* The oafamily for this sym   *)
                       errorScope: ErrorScope ; (* Title scope used if an      *)
                                                (* error is emitted.           *)
*************** END IsError ;
*** 1591,1597 ****
     MakeObject - creates an object node.
  *)
  
! PROCEDURE MakeObject (name: Name) : CARDINAL ;
  VAR
     pSym: PtrToSymbol ;
     Sym : CARDINAL ;
--- 1595,1601 ----
     MakeObject - creates an object node.
  *)
  
! PROCEDURE MakeObject (tok: CARDINAL; name: Name) : CARDINAL ;
  VAR
     pSym: PtrToSymbol ;
     Sym : CARDINAL ;
*************** BEGIN
*** 1601,1608 ****
     WITH pSym^ DO
        SymbolType := ObjectSym ;
        Object.name := name ;
!       InitWhereDeclared(Object.At) ;
!       InitWhereFirstUsed(Object.At)
     END ;
     RETURN( Sym )
  END MakeObject ;
--- 1605,1612 ----
     WITH pSym^ DO
        SymbolType := ObjectSym ;
        Object.name := name ;
!       InitWhereDeclaredTok (tok, Object.At) ;
!       InitWhereFirstUsedTok (tok, Object.At)
     END ;
     RETURN( Sym )
  END MakeObject ;
*************** BEGIN
*** 8647,8653 ****
        THEN
           (* Make unknown *)
           NewSym (Sym) ;
!          FillInUnknownFields (tok, Sym, SymName) ;
           (* Add to unknown tree *)
           AddSymToUnknownTree (ScopePtr, SymName, Sym)
           (*
--- 8651,8657 ----
        THEN
           (* Make unknown *)
           NewSym (Sym) ;
!          FillInUnknownFields (tok, Sym, SymName, NulSym, FALSE) ;
           (* Add to unknown tree *)
           AddSymToUnknownTree (ScopePtr, SymName, Sym)
           (*
*************** BEGIN
*** 8684,8690 ****
        THEN
           (* Make unknown.  *)
           NewSym (Sym) ;
!          FillInUnknownFields (tok, Sym, SymName) ;
           (* Add to unknown tree *)
           AddSymToUnknownTree (ScopePtr, SymName, Sym)
           (*
--- 8688,8694 ----
        THEN
           (* Make unknown.  *)
           NewSym (Sym) ;
!          FillInUnknownFields (tok, Sym, SymName, NulSym, FALSE) ;
           (* Add to unknown tree *)
           AddSymToUnknownTree (ScopePtr, SymName, Sym)
           (*
*************** BEGIN
*** 9252,9258 ****
                         IF Sym=NulSym
                         THEN
                            NewSym (Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName) ;
                            PutSymKey (Unresolved, SymName, Sym)
                         END
                      END
--- 9256,9262 ----
                         IF Sym=NulSym
                         THEN
                            NewSym (Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName, ModSym, TRUE) ;
                            PutSymKey (Unresolved, SymName, Sym)
                         END
                      END
*************** BEGIN
*** 9283,9289 ****
                         IF Sym=NulSym
                         THEN
                            NewSym(Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName) ;
                            PutSymKey (Unresolved, SymName, Sym)
                         END
                      END
--- 9287,9293 ----
                         IF Sym=NulSym
                         THEN
                            NewSym(Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName, ModSym, TRUE) ;
                            PutSymKey (Unresolved, SymName, Sym)
                         END
                      END
*************** BEGIN
*** 9310,9316 ****
                         IF Sym=NulSym
                         THEN
                            NewSym(Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName) ;
                            PutSymKey(Unresolved, SymName, Sym)
                         END
                      END |
--- 9314,9320 ----
                         IF Sym=NulSym
                         THEN
                            NewSym(Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName, scope, TRUE) ;
                            PutSymKey(Unresolved, SymName, Sym)
                         END
                      END |
*************** BEGIN
*** 9319,9325 ****
                         IF Sym=NulSym
                         THEN
                            NewSym(Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName) ;
                            PutSymKey(Unresolved, SymName, Sym)
                         END
                      END |
--- 9323,9329 ----
                         IF Sym=NulSym
                         THEN
                            NewSym(Sym) ;
!                           FillInUnknownFields (tok, Sym, SymName, scope, TRUE) ;
                            PutSymKey(Unresolved, SymName, Sym)
                         END
                      END |
*************** BEGIN
*** 9328,9334 ****
                            IF Sym=NulSym
                            THEN
                               NewSym(Sym) ;
!                              FillInUnknownFields (tok, Sym, SymName) ;
                               PutSymKey(Unresolved, SymName, Sym)
                            END
                         END
--- 9332,9338 ----
                            IF Sym=NulSym
                            THEN
                               NewSym(Sym) ;
!                              FillInUnknownFields (tok, Sym, SymName, NulSym, FALSE) ;
                               PutSymKey(Unresolved, SymName, Sym)
                            END
                         END
*************** BEGIN
*** 9599,9605 ****
                      CheckForUnknowns (tokno, name, ExportUnQualifiedTree,
                                        'EXPORT UNQUALIFIED') ;
                      CheckForSymbols (ExportRequest,
!                                      'requested by another modules import (symbols have not been exported by the appropriate definition module)') ;
                      CheckForUnknowns (tokno, name, Unresolved, 'unresolved') ;
                      CheckForUnknowns (tokno, name, LocalSymbols, 'locally used')
                   END |
--- 9603,9610 ----
                      CheckForUnknowns (tokno, name, ExportUnQualifiedTree,
                                        'EXPORT UNQUALIFIED') ;
                      CheckForSymbols (ExportRequest,
!                                      'requested by another module import' +
!                                      ' and the symbol has not been exported by the appropriate definition module') ;
                      CheckForUnknowns (tokno, name, Unresolved, 'unresolved') ;
                      CheckForUnknowns (tokno, name, LocalSymbols, 'locally used')
                   END |
*************** PROCEDURE CheckForSymbols (Tree: SymbolT
*** 9752,9763 ****
  VAR
     s: String ;
  BEGIN
!    IF NOT IsEmptyTree(Tree)
     THEN
        s := InitString ("the symbols are unknown at the end of module {%1Ea} when ") ;
        s := ConCat (s, Mark(InitString(a))) ;
        MetaErrorString1 (s, MainModule) ;
!       ForeachNodeDo(Tree, SymbolError)
     END
  END CheckForSymbols ;
  
--- 9757,9768 ----
  VAR
     s: String ;
  BEGIN
!    IF DoesTreeContainAny (Tree, IsUnreportedUnknown)
     THEN
        s := InitString ("the symbols are unknown at the end of module {%1Ea} when ") ;
        s := ConCat (s, Mark(InitString(a))) ;
        MetaErrorString1 (s, MainModule) ;
!       ForeachNodeDo (Tree, SymbolError)
     END
  END CheckForSymbols ;
  
*************** END IsProcedureAnyNoReturn ;
*** 11708,11717 ****
  
  
  (*
!    FillInUnknownFields -
  *)
  
! PROCEDURE FillInUnknownFields (tok: CARDINAL; sym: CARDINAL; SymName: Name) ;
  VAR
     pSym: PtrToSymbol ;
  BEGIN
--- 11713,11723 ----
  
  
  (*
!    FillInUnknownFields - fills in all fields for the undefined sym.
  *)
  
! PROCEDURE FillInUnknownFields (tok: CARDINAL; sym: CARDINAL; SymName: Name;
!                                descscope: CARDINAL; onimport: BOOLEAN) ;
  VAR
     pSym: PtrToSymbol ;
  BEGIN
*************** BEGIN
*** 11722,11727 ****
--- 11728,11735 ----
           name     := SymName ;
           oafamily := NulSym ;
           errorScope := GetCurrentErrorScope () ;
+          declScope := descscope ;
+          onImport := onimport ;
           InitWhereFirstUsedTok (tok, At)
        END
     END
*************** END FillInUnknownFields ;
*** 11729,11734 ****
--- 11737,11770 ----
  
  
  (*
+    GetUnknownOnImport - returns the onimport field of unknown sym.
+ *)
+ 
+ PROCEDURE GetUnknownOnImport (sym: CARDINAL) : BOOLEAN ;
+ VAR
+    pSym: PtrToSymbol ;
+ BEGIN
+    Assert (IsUnknown (sym)) ;
+    pSym := GetPsym (sym) ;
+    RETURN pSym^.Undefined.onImport
+ END GetUnknownOnImport ;
+ 
+ 
+ (*
+    GetUnknownDeclScope - returns the decl scope of unknown sym.
+ *)
+ 
+ PROCEDURE GetUnknownDeclScope (sym: CARDINAL) : CARDINAL ;
+ VAR
+    pSym: PtrToSymbol ;
+ BEGIN
+    Assert (IsUnknown (sym)) ;
+    pSym := GetPsym (sym) ;
+    RETURN pSym^.Undefined.declScope
+ END GetUnknownDeclScope ;
+ 
+ 
+ (*
     FillInPointerFields - given a new symbol, sym, make it a pointer symbol
                           and initialize its fields.
  *)
*************** END AddNameTo ;
*** 12985,12991 ****
                      current scope.
  *)
  
! PROCEDURE AddNameToScope (n: Name) ;
  VAR
     pSym : PtrToSymbol ;
     scope: CARDINAL ;
--- 13021,13027 ----
                      current scope.
  *)
  
! PROCEDURE AddNameToScope (tok: CARDINAL; n: Name) ;
  VAR
     pSym : PtrToSymbol ;
     scope: CARDINAL ;
*************** BEGIN
*** 12995,13003 ****
     WITH pSym^ DO
        CASE SymbolType OF
  
!       ProcedureSym:  AddNameTo(Procedure.NamedObjects, MakeObject(n)) |
!       ModuleSym   :  AddNameTo(Module.NamedObjects, MakeObject(n)) |
!       DefImpSym   :  AddNameTo(DefImp.NamedObjects, MakeObject(n))
  
        ELSE
           InternalError ('expecting - DefImp')
--- 13031,13039 ----
     WITH pSym^ DO
        CASE SymbolType OF
  
!       ProcedureSym:  AddNameTo(Procedure.NamedObjects, MakeObject (tok, n)) |
!       ModuleSym   :  AddNameTo(Module.NamedObjects, MakeObject (tok, n)) |
!       DefImpSym   :  AddNameTo(DefImp.NamedObjects, MakeObject (tok, n))
  
        ELSE
           InternalError ('expecting - DefImp')
*************** END AddNameToScope ;
*** 13011,13017 ****
                           module.
  *)
  
! PROCEDURE AddNameToImportList (n: Name) ;
  VAR
     pSym : PtrToSymbol ;
     scope: CARDINAL ;
--- 13047,13053 ----
                           module.
  *)
  
! PROCEDURE AddNameToImportList (tok: CARDINAL; n: Name) ;
  VAR
     pSym : PtrToSymbol ;
     scope: CARDINAL ;
*************** BEGIN
*** 13021,13028 ****
     WITH pSym^ DO
        CASE SymbolType OF
  
!       ModuleSym:  AddNameTo(Module.NamedImports, MakeObject(n)) |
!       DefImpSym:  AddNameTo(DefImp.NamedImports, MakeObject(n))
  
        ELSE
           InternalError ('expecting - DefImp or Module symbol')
--- 13057,13064 ----
     WITH pSym^ DO
        CASE SymbolType OF
  
!       ModuleSym:  AddNameTo (Module.NamedImports, MakeObject (tok, n)) |
!       DefImpSym:  AddNameTo (DefImp.NamedImports, MakeObject (tok, n))
  
        ELSE
           InternalError ('expecting - DefImp or Module symbol')
diff -Nrcpad gcc-16-20251026/gcc/match.pd gcc-16-20251102/gcc/match.pd
*** gcc-16-20251026/gcc/match.pd	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/match.pd	Sun Nov  2 22:32:22 2025
*************** DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
*** 2429,2434 ****
--- 2429,2445 ----
  	  || TYPE_PRECISION (type) > 1)
        && wi::leu_p (tree_nonzero_bits (@1), 1))))
  
+ /* VCE<bool>(zero_one) ==/!= false -> zero_one ==/!= 0.
+    This is done as SRA likes to create VCE for boolean accesses
+    and it helps code gneration and uninitialized variable warnings.  */
+ (for neeq (ne eq)
+  (simplify
+   (neeq (view_convert@0 zero_one_valued_p@1) integer_zerop)
+   (if (TREE_CODE (TREE_TYPE (@0)) == BOOLEAN_TYPE
+        && TYPE_PRECISION (TREE_TYPE (@0)) == 1
+        && TYPE_UNSIGNED (TREE_TYPE (@0)))
+    (neeq @1 { build_zero_cst (TREE_TYPE (@1)); } ))))
+ 
  /* Transform { 0 or 1 } * { 0 or 1 } into { 0 or 1 } & { 0 or 1 }.  */
  (simplify
   (mult zero_one_valued_p@0 zero_one_valued_p@1)
*************** DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
*** 5645,5650 ****
--- 5656,5671 ----
    (view_convert (view_convert @0))
    (view_convert @0))
  
+ /* Squash view_converts of BFRs if no precision is lost.  */
+ (simplify
+   (view_convert (BIT_FIELD_REF@0 @1 @2 @3))
+   (if (is_gimple_reg_type (type)
+        && (!INTEGRAL_TYPE_P (type)
+ 	   || !INTEGRAL_TYPE_P (TREE_TYPE (@0))
+ 	   || (type_has_mode_precision_p (type)
+ 	       && type_has_mode_precision_p (TREE_TYPE (@0)))))
+    (BIT_FIELD_REF:type @1 @2 @3)))
+ 
  /* For integral conversions with the same precision or pointer
     conversions use a NOP_EXPR instead.  */
  (simplify
*************** and,
*** 12002,12004 ****
--- 12023,12030 ----
        && direct_internal_fn_supported_p (IFN_AVG_CEIL, type, OPTIMIZE_FOR_BOTH))
        (IFN_AVG_CEIL @0 @2)))
  #endif
+ 
+ /* vec shift left insert (dup (A), A) -> dup(A) */
+ (simplify
+  (IFN_VEC_SHL_INSERT (vec_duplicate@1 @0) @0)
+   @1)
diff -Nrcpad gcc-16-20251026/gcc/opts.cc gcc-16-20251102/gcc/opts.cc
*** gcc-16-20251026/gcc/opts.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/opts.cc	Sun Nov  2 22:32:22 2025
*************** init_options_struct (struct gcc_options
*** 454,459 ****
--- 454,462 ----
    /* Some targets have ABI-specified unwind tables.  */
    opts->x_flag_unwind_tables = targetm_common.unwind_tables_default;
  
+   /* Languages not explicitly specifying a default get fortran rules.  */
+   opts->x_flag_complex_method = 1;
+ 
    /* Some targets have other target-specific initialization.  */
    targetm_common.option_init_struct (opts);
  }
*************** finish_options (struct gcc_options *opts
*** 1393,1402 ****
           || opts->x_flag_peel_loops
           || opts->x_optimize >= 3);
  
-   /* Use a frontend provided default for the complex eval method.  */
-   if (!opts_set->x_flag_complex_method)
-     opts->x_flag_complex_method = opts->x_flag_default_complex_method;
- 
    /* Use -fvect-cost-model=cheap instead of -fvect-cost-mode=very-cheap
       by default with explicit -ftree-{loop,slp}-vectorize.  */
    if (opts->x_optimize == 2
--- 1396,1401 ----
diff -Nrcpad gcc-16-20251026/gcc/range-op-mixed.h gcc-16-20251102/gcc/range-op-mixed.h
*** gcc-16-20251026/gcc/range-op-mixed.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/range-op-mixed.h	Sun Nov  2 22:32:23 2025
*************** private:
*** 527,532 ****
--- 527,573 ----
  			   const irange &outer) const;
  };
  
+ 
+ class operator_view : public range_operator
+ {
+ public:
+   using range_operator::fold_range;
+   using range_operator::op1_range;
+   using range_operator::update_bitmask;
+   bool fold_range (irange &r, tree type,
+ 		   const irange &op1, const irange &op2,
+ 		   relation_trio rel = TRIO_VARYING) const override;
+   bool fold_range (prange &r, tree type,
+ 		   const prange &op1, const prange &op2,
+ 		   relation_trio rel = TRIO_VARYING) const final override;
+   bool fold_range (irange &r, tree type,
+ 		   const prange &op1, const irange &op2,
+ 		   relation_trio rel = TRIO_VARYING) const final override;
+   bool fold_range (prange &r, tree type,
+ 		   const irange &op1, const prange &op2,
+ 		   relation_trio rel = TRIO_VARYING) const final override;
+ 
+   bool op1_range (irange &r, tree type,
+ 		  const irange &lhs, const irange &op2,
+ 		  relation_trio rel = TRIO_VARYING) const override;
+   bool op1_range (prange &r, tree type,
+ 		  const prange &lhs, const prange &op2,
+ 		  relation_trio rel = TRIO_VARYING) const final override;
+   bool op1_range (irange &r, tree type,
+ 		  const prange &lhs, const irange &op2,
+ 		  relation_trio rel = TRIO_VARYING) const final override;
+   bool op1_range (prange &r, tree type,
+ 		  const irange &lhs, const prange &op2,
+ 		  relation_trio rel = TRIO_VARYING) const final override;
+ 
+   void update_bitmask (irange &r, const irange &lh,
+ 		       const irange &) const final override;
+ private:
+ // VIEW_CONVERT_EXPR works much like a cast between integral values, so use
+ // the cast operator.  Non-integrals are not handled as yet.
+   operator_cast m_cast;
+ };
+ 
  class operator_plus : public range_operator
  {
  public:
diff -Nrcpad gcc-16-20251026/gcc/range-op.cc gcc-16-20251102/gcc/range-op.cc
*** gcc-16-20251026/gcc/range-op.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/range-op.cc	Sun Nov  2 22:32:23 2025
*************** operator_ge op_ge;
*** 60,65 ****
--- 60,66 ----
  operator_identity op_ident;
  operator_cst op_cst;
  operator_cast op_cast;
+ operator_view op_view;
  operator_plus op_plus;
  operator_abs op_abs;
  operator_minus op_minus;
*************** range_op_table::range_op_table ()
*** 97,102 ****
--- 98,104 ----
    set (INTEGER_CST, op_cst);
    set (NOP_EXPR, op_cast);
    set (CONVERT_EXPR, op_cast);
+   set (VIEW_CONVERT_EXPR, op_view);
    set (FLOAT_EXPR, op_cast);
    set (FIX_TRUNC_EXPR, op_cast);
    set (PLUS_EXPR, op_plus);
*************** operator_cast::op1_range (irange &r, tre
*** 3247,3252 ****
--- 3249,3328 ----
    return true;
  }
  
+ // VIEW_CONVERT_EXPR works like a cast between integral values.
+ // If the number of bits are not the same, behaviour is undefined,
+ // so cast behaviour still works.
+ 
+ bool
+ operator_view::fold_range (irange &r, tree type,
+ 			   const irange &op1, const irange &op2,
+ 			   relation_trio rel) const
+ {
+   return m_cast.fold_range (r, type, op1, op2, rel);
+ }
+ 
+ bool
+ operator_view::fold_range (prange &r, tree type,
+ 			   const prange &op1, const prange &op2,
+ 			   relation_trio rel) const
+ {
+   return m_cast.fold_range (r, type, op1, op2, rel);
+ }
+ bool
+ operator_view::fold_range (irange &r, tree type,
+ 			   const prange &op1, const irange &op2,
+ 			   relation_trio rel) const
+ {
+   return m_cast.fold_range (r, type, op1, op2, rel);
+ }
+ 
+ bool
+ operator_view::fold_range (prange &r, tree type,
+ 			   const irange &op1, const prange &op2,
+ 			   relation_trio rel) const
+ {
+   return m_cast.fold_range (r, type, op1, op2, rel);
+ }
+ 
+ bool
+ operator_view::op1_range (irange &r, tree type,
+ 			  const irange &lhs, const irange &op2,
+ 			  relation_trio rel) const
+ {
+   return m_cast.op1_range (r, type, lhs, op2, rel);
+ }
+ 
+ bool
+ operator_view::op1_range (prange &r, tree type,
+ 			  const prange &lhs, const prange &op2,
+ 			  relation_trio rel) const
+ {
+   return m_cast.op1_range (r, type, lhs, op2, rel);
+ }
+ 
+ bool
+ operator_view::op1_range (irange &r, tree type,
+ 			  const prange &lhs, const irange &op2,
+ 			  relation_trio rel) const
+ {
+   return m_cast.op1_range (r, type, lhs, op2, rel);
+ }
+ 
+ bool
+ operator_view::op1_range (prange &r, tree type,
+ 			  const irange &lhs, const prange &op2,
+ 			  relation_trio rel) const
+ {
+   return m_cast.op1_range (r, type, lhs, op2, rel);
+ }
+ 
+ void
+ operator_view::update_bitmask (irange &r, const irange &lh,
+ 			       const irange &rh) const
+ {
+   m_cast.update_bitmask (r, lh, rh);
+ }
+ 
  
  class operator_logical_and : public range_operator
  {
diff -Nrcpad gcc-16-20251026/gcc/rust/ChangeLog gcc-16-20251102/gcc/rust/ChangeLog
*** gcc-16-20251026/gcc/rust/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ChangeLog	Sun Nov  2 22:32:23 2025
***************
*** 1,3 ****
--- 1,1446 ----
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* ast/rust-ast-pointer-visitor.cc (PointerVisitor::visit):
+ 	Handle the expression contained in an ErrorPropagationExpr.
+ 	* ast/rust-ast-visitor.cc (DefaultASTVisitor::visit): Likewise.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-pattern.cc (visit(TuplePattern)): Update HAS_REST
+ 	case to continue to attempt to resolve pattern items after emitting size error.
+ 
+ 2025-10-30  Ryo Yoshida  <low.ryoshida@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-pattern.cc (TypeCheckPattern::visit): Emit
+ 	an error when the path refers to an enum itself rather than its variant.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-base.cc (parse_repr_options): Changed TOKEN_TREE
+ 	assert into error, update malformed repr attribute error message to be inline
+ 	with other attribute error messages.
+ 
+ 2025-10-30  Lucas Ly Ba  <lucas.ly-ba@outlook.fr>
+ 
+ 	* ast/rust-ast.cc (Attribute::is_derive):
+ 	Change string derive to its definition.
+ 	* util/rust-attribute-values.h:
+ 	Add attribute definition derive.
+ 	* util/rust-attributes.cc (AttributeChecker::visit):
+ 	Add method check_inner_attributes.
+ 	(AttributeChecker::check_inner_attributes):
+ 	Check if there is a bad inner attribute.
+ 	* util/rust-attributes.h:
+ 	Add method check_inner_attributes in .h.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* typecheck/rust-tyty-util.cc (TyVar::TyVar): Add null check to avoid ICE.
+ 	(TyVar::get_tyty): Return nullptr when lookup fails.
+ 	(TyVar::clone): Handle null base type safely.
+ 	(TyVar::monomorphized_clone): Add fallback for error types.
+ 
+ 2025-10-30  Ryo Yoshida  <low.ryoshida@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): check
+ 	and properly emit an error when the tuple index is on a non-tuple-struct.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-compile-expr.cc (CompileExpr::array_copied_expr): refactor to new classes
+ 	* backend/rust-compile-pattern.cc (CompilePatternCheckExpr::visit): likewise
+ 	(CompilePatternBindings::visit): likewise
+ 	* backend/rust-compile-type.cc (TyTyResolveCompile::visit): likewise
+ 	* backend/rust-compile-type.h: likewise
+ 	* typecheck/rust-hir-type-check-base.cc (TypeCheckBase::resolve_literal): likewise
+ 	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): likewise
+ 	* typecheck/rust-hir-type-check-pattern.cc (TypeCheckPattern::visit): likewise
+ 	* typecheck/rust-hir-type-check-type.cc (TypeCheckType::visit): likewise
+ 	* typecheck/rust-substitution-mapper.cc (SubstMapperInternal::visit): likewise
+ 	* typecheck/rust-substitution-mapper.h: likewise
+ 	* typecheck/rust-type-util.cc (unify_site_and): remove bad delete (alpine32)
+ 	* typecheck/rust-tyty-call.h: refactor to new classes
+ 	* typecheck/rust-tyty-subst.cc (SubstitutionParamMapping::clone): likewise
+ 	(SubstitutionRef::infer_substitions): likewise
+ 	* typecheck/rust-tyty-util.cc (TyVar::get_implicit_const_infer_var): likewise
+ 	* typecheck/rust-tyty-util.h: likewise
+ 	* typecheck/rust-tyty-variance-analysis-private.h: likewise
+ 	* typecheck/rust-tyty-visitor.h: likewise
+ 	* typecheck/rust-tyty.cc (BaseType::destructure): likewise
+ 	(BaseType::monomorphized_clone): likewise
+ 	(BaseType::is_concrete): likewise
+ 	(VariantDef::clone): likewise
+ 	(VariantDef::monomorphized_clone): likewise
+ 	(ArrayType::as_string): likewise
+ 	(ArrayType::get_capacity): likewise
+ 	(ArrayType::handle_substitions): likewise
+ 	(generate_tree_str): likewise
+ 	(ConstType::ConstType): likewise
+ 	(ConstParamType::ConstParamType): likewise
+ 	(ConstType::accept_vis): likewise
+ 	(ConstParamType::const_kind): likewise
+ 	(ConstParamType::get_symbol): likewise
+ 	(ConstParamType::can_resolve): likewise
+ 	(ConstParamType::resolve): likewise
+ 	(ConstParamType::accept_vis): likewise
+ 	(ConstType::set_value): likewise
+ 	(ConstType::as_string): likewise
+ 	(ConstParamType::as_string): likewise
+ 	(ConstType::clone): likewise
+ 	(ConstParamType::clone): likewise
+ 	(ConstType::get_symbol): likewise
+ 	(ConstParamType::get_name): likewise
+ 	(ConstType::can_resolve): likewise
+ 	(ConstParamType::is_equal): likewise
+ 	(ConstType::resolve): likewise
+ 	(ConstValueType::ConstValueType): likewise
+ 	(ConstValueType::const_kind): likewise
+ 	(ConstValueType::accept_vis): likewise
+ 	(ConstValueType::as_string): likewise
+ 	(ConstValueType::clone): likewise
+ 	(ConstValueType::get_name): likewise
+ 	(ConstValueType::is_equal): likewise
+ 	(ConstValueType::get_value): likewise
+ 	(ConstInferType::ConstInferType): likewise
+ 	(ConstInferType::const_kind): likewise
+ 	(ConstInferType::accept_vis): likewise
+ 	(ConstType::get_name): likewise
+ 	(ConstInferType::as_string): likewise
+ 	(ConstInferType::clone): likewise
+ 	(ConstInferType::get_name): likewise
+ 	(ConstType::is_equal): likewise
+ 	(ConstInferType::is_equal): likewise
+ 	(ConstErrorType::ConstErrorType): likewise
+ 	(ConstErrorType::const_kind): likewise
+ 	(ConstType::handle_substitions): likewise
+ 	(ConstErrorType::accept_vis): likewise
+ 	(ConstErrorType::as_string): likewise
+ 	(ConstErrorType::clone): likewise
+ 	(ConstErrorType::get_name): likewise
+ 	(ConstErrorType::is_equal): likewise
+ 	* typecheck/rust-tyty.h (class BaseConstType): likewise
+ 	(class ConstType): likewise
+ 	(class ConstParamType): likewise
+ 	(class ConstValueType): likewise
+ 	(class ConstInferType): likewise
+ 	(class ConstErrorType): likewise
+ 	* typecheck/rust-unify.cc (UnifyRules::commit): likewise
+ 	(UnifyRules::go): likewise
+ 	(UnifyRules::expect_array): likewise
+ 	(UnifyRules::expect_const): likewise
+ 	* typecheck/rust-unify.h: likewise
+ 
+ 2025-10-30  0xllx0  <github+elle@weathered-steel.dev>
+ 
+ 	* ast/rust-ast.cc (Module::process_file_path): empty module early return
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* util/rust-attributes.cc (check_doc_attribute): Change message.
+ 	(AttributeChecker::visit): Add doc attribute checking on traits.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-ast.cc (AttrInputMetaItemContainer::separate_cfg_attrs):
+ 	Avoid malformed attributes.
+ 	* util/rust-attributes.cc (AttributeChecker::visit): Change location.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-expr.h: Force crash when retrieving locus.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-ast.h: Add missing override modifier.
+ 	* ast/rust-path.h: Likewise.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* util/rust-attributes.cc (AttributeChecker::check_attribute): Recurse
+ 	within attr input for additional attribute checking.
+ 	(AttributeChecker::visit): Remove empty definition in favor of default
+ 	ast visitor definition.
+ 	* util/rust-attributes.h: Remove now unused prototypes.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-pattern.cc (visit(TupleStructPattern)):
+ 	Update error for mismatched number of fields to use rich_location.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* backend/rust-compile-pattern.cc: Add compilation support for TupleStructItemsHasRest
+ 	in CompilePatternCheckExpr(TupleStructPattern) & CompilePatternBindings(TupleStructPattern)
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* hir/rust-ast-lower-pattern.cc (ASTLoweringPattern::visit(TupleStructPattern)):
+ 	Implement lowering of AST::TupleStructItemsHasRest to HIR.
+ 	* typecheck/rust-hir-type-check-pattern.cc (TypeCheckPattern::visit(TupleStructPattern)):
+ 	Add the respective type checking for AST::TupleStructItemsHasRest
+ 	* checks/errors/rust-hir-pattern-analysis.cc (lower_tuple_pattern):
+ 	Add respective pattern for HAS_REST case.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-pattern.cc (visit(StructPattern)): Add type check
+ 	support for StructPatterns matching against a TUPLE type ADT.
+ 	* backend/rust-compile-pattern.cc(CompilePatternBindings::visit(StructPattern)):
+ 	Update assert to allow TUPLE type ADTs.
+ 	* hir/tree/rust-hir.cc (StructPatternField::as_string()): Improve info dumped.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* ast/rust-pattern.h (StructPatternElements): Rename has_struct_pattern_etc
+ 	to has_rest_pattern, and has_etc to has_rest to signify presense of rest
+ 	patterns more clearly.
+ 	* ast/rust-pattern.cc (StructPatternElements::as_string): Rename variables
+ 	accordingly.
+ 	* ast/rust-ast-collector.cc: Rename variables accordingly.
+ 	* expand/rust-cfg-strip.cc: Rename variables accordingly.
+ 	* parse/rust-parse-impl.h: Rename variable accordingly.
+ 	* hir/tree/rust-hir-pattern.h (StructPatternElements): Add a boolean to track
+ 	presense of rest pattern.
+ 	* hir/rust-ast-lower-pattern.cc (visit(StructPattern)): Add support for
+ 	lowering rest pattern to HIR.
+ 	* typecheck/rust-hir-type-check-pattern.cc (visit(StructPattern)): Remove
+ 	size check when rest pattern is present.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* backend/rust-compile-extern.h: Add includes.
+ 	(CompileExternItem::visit): Use get_link_name.
+ 	(CompileExternItem::get_link_name): New static member function.
+ 	* util/rust-attribute-values.h (Attributes::LINK_NAME): New
+ 	static constexpr member variable.
+ 	* util/rust-attributes.cc (__definitions): New entry for
+ 	LINK_NAME.
+ 	* util/rust-ggc.cc: Include "rust-ast.h".
+ 	(Ident::Ident): Add overload for Rust::Identifier.
+ 	* util/rust-ggc.h (class Identifier): Forward declare.
+ 	(Ident::Ident): Add overload for Rust::Identifier.
+ 
+ 2025-10-30  Arthur Cohen  <arthur.cohen@embecosm.com>
+ 
+ 	* expand/rust-expand-visitor.cc: Remove old visitors.
+ 	* expand/rust-expand-visitor.h: Likewise, plus inherit from PointerVisitor.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* expand/rust-macro-expand.cc: Forward invocation tree locus to
+ 	substitution context.
+ 	* expand/rust-macro-substitute-ctx.cc: Use origin location for expanded
+ 	tokens.
+ 	* expand/rust-macro-substitute-ctx.h (class SubstituteCtx): Save
+ 	invocation location.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* expand/rust-macro-expand.cc (transcribe_expression): Emit error
+ 	early.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* expand/rust-macro-substitute-ctx.cc (is_builtin_metavariable): Add
+ 	function to check builtin metavars knowledge.
+ 	(SubstituteCtx::check_repetition_amount): Do not process missing
+ 	fragment.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-compile-resolve-path.cc: add error diag
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* hir/rust-ast-lower-item.cc (ASTLoweringItem::visit): add error diagnostic
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): check for error
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-hir-type-check-expr.cc: remove old hack
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-substitution-mapper.cc (SubstMapperInternal::visit): handle fnptr
+ 	* typecheck/rust-tyty.cc (FnPtr::handle_substitions): new
+ 	* typecheck/rust-tyty.h: likewise
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* ast/rust-fmt.h (class FFIOpt): Adjust internal structure to
+ 	match a repr(C) rust enum.
+ 
+ 2025-10-30  Magnus-Mage  <romescha123@gmail.com>
+ 
+ 	* ast/rust-ast-collector.cc (TokenCollector::visit): Implement
+ 	FormatArgs visitor to reconstruct format_args! macro syntax.
+ 	* ast/rust-builtin-ast-nodes.h (FormatArguments): Add get_args(),
+ 	size(), and empty() accessor methods.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-hir-type-check-type.cc (TypeCheckType::visit): check for invalid capacity
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-constexpr.cc (eval_constant_expression): port over missing bits
+ 	(eval_store_expression): likewise
+ 	(eval_call_expression): likewise
+ 	(eval_binary_expression): likewise
+ 	(eval_bit_field_ref): likewise
+ 	(eval_check_shift_p): likewise
+ 	(fold_pointer_plus_expression): likewise
+ 	(maybe_fold_addr_pointer_plus): likewise
+ 	(fold_expr): likewise
+ 	(union_active_member): likewise
+ 	(fold_indirect_ref_1): likewise
+ 	(rs_fold_indirect_ref): likewise
+ 	(rs_eval_indirect_ref): likewise
+ 	(eval_logical_expression): likewise
+ 	(eval_vector_conditional_expression): likewise
+ 	(eval_bare_aggregate): likewise
+ 	(cxx_eval_trinary_expression): likewise
+ 	(eval_and_check_array_index): likewise
+ 	(eval_array_reference): likewise
+ 	(eval_component_reference): likewise
+ 	(rs_bind_parameters_in_call): likewise
+ 	(eval_builtin_function_call): likewise
+ 	(constexpr_fn_retval): likewise
+ 	(verify_constant): likewise
+ 	(get_array_or_vector_nelts): likewise
+ 	(eval_conditional_expression): likewise
+ 	(eval_switch_expr): likewise
+ 	(eval_unary_expression): likewise
+ 	(cxx_eval_outermost_constant_expr): likewise
+ 	(potential_constant_expression_1): likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-compile-expr.cc (CompileExpr::compile_integer_literal): cleanup
+ 	* backend/rust-constexpr.cc (struct constexpr_global_ctx): port over c++ helpers
+ 	(decl_really_constant_value): likewise
+ 	(eval_constant_expression): likewise
+ 	(non_const_var_error): likewise
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* parse/rust-parse-impl.h (Parser::parse_pattern): Ignore
+ 	inner patterns which fail to parse.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* ast/rust-ast-collector.cc (TokenCollector::visit): Remove
+ 	overload for TraitItemConst.
+ 	* ast/rust-ast-collector.h (TokenCollector::visit): Likewise.
+ 	* ast/rust-ast-pointer-visitor.cc (PointerVisitor::visit):
+ 	Likewise.
+ 	* ast/rust-ast-pointer-visitor.h (PointerVisitor::visit):
+ 	Likewise.
+ 	* ast/rust-ast-visitor.cc (DefaultASTVisitor::visit): Likewise.
+ 	* ast/rust-ast-visitor.h (ASTVisitor::visit): Likewise.
+ 	(DefaultASTVisitor::visit): Likewise.
+ 	* expand/rust-cfg-strip.cc (CfgStrip::visit): Likewise.
+ 	* expand/rust-cfg-strip.h (CfgStrip::visit): Likewise.
+ 	* expand/rust-derive.h (DeriveVisitor::visit): Likewise.
+ 	* expand/rust-expand-visitor.cc (ExpandVisitor::visit):
+ 	Likewise.
+ 	* expand/rust-expand-visitor.h (ExpandVisitor::visit): Likewise.
+ 	* hir/rust-ast-lower-base.cc (ASTLoweringBase::visit): Likewise.
+ 	* hir/rust-ast-lower-base.h (ASTLoweringBase::visit): Likewise.
+ 	* util/rust-attributes.cc (AttributeChecker::visit): Likewise.
+ 	* util/rust-attributes.h (AttributeChecker::visit): Likewise.
+ 	* ast/rust-ast.cc (ConstantItem::as_string): Handle missing
+ 	expression.
+ 	(TraitItemConst::as_string): Remove function definition.
+ 	(TraitItemConst::accept_vis): Remove function definition.
+ 	* ast/rust-item.h (ConstantItem::mark_for_strip): Adjust
+ 	comment.
+ 	(ConstantItem::has_expr): Make const.
+ 	(class TraitItemConst): Remove definition.
+ 	* ast/rust-ast-full-decls.h (class TraitItemConst): Remove
+ 	declaration.
+ 	* hir/rust-ast-lower-implitem.cc (ASTLowerTraitItem::visit):
+ 	Handle ConstantItem instead of TraitItemConst.
+ 	* hir/rust-ast-lower-implitem.h (ASTLowerTraitItem::visit):
+ 	Likewise.
+ 	* parse/rust-parse-impl.h (Parser::parse_trait_const): Return
+ 	pointer to ConstantItem instead of TraitItemConst.
+ 	* parse/rust-parse.h (Parser::parse_trait_const): Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* Make-lang.in: Handle source files in checks/errors/feature.
+ 	* checks/errors/rust-feature-gate.cc: Move to...
+ 	* checks/errors/feature/rust-feature-gate.cc: ...here.
+ 	* checks/errors/rust-feature-gate.h: Move to...
+ 	* checks/errors/feature/rust-feature-gate.h: ...here.
+ 	* checks/errors/rust-feature.cc: Move to...
+ 	* checks/errors/feature/rust-feature.cc: ...here.
+ 	* checks/errors/rust-feature.h: Move to...
+ 	* checks/errors/feature/rust-feature.h: ...here.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* Make-lang.in (GRS_OBJS): Remove rust-early-name-resolver.o.
+ 	* expand/rust-macro-builtins-helpers.h: Remove inclusion of
+ 	rust-early-name-resolver.h.
+ 	* expand/rust-macro-builtins.cc: Likewise.
+ 	* expand/rust-macro-expand.cc: Likewise.
+ 	* expand/rust-macro-expand.h: Likewise.
+ 	* resolve/rust-early-name-resolver.cc: Removed.
+ 	* resolve/rust-early-name-resolver.h: Removed.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* hir/tree/rust-hir-item.h: add unsafe helper
+ 	* typecheck/rust-hir-type-check-type.cc (TypeCheckType::visit): pass in abi and unsafe
+ 	* typecheck/rust-tyty.cc (BaseType::monomorphized_clone): likewise
+ 	(FnPtr::as_string): emit more info
+ 	(FnPtr::clone): update ctor call
+ 	* typecheck/rust-tyty.h: new ctor params
+ 	* typecheck/rust-unify.cc (UnifyRules::expect_fnptr): check abi and unsafe
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-unify.cc (UnifyRules::expect_reference): remove clone
+ 	(UnifyRules::expect_pointer): likewise
+ 	(UnifyRules::expect_slice): likewise
+ 	(UnifyRules::expect_tuple): likewise
+ 	(UnifyRules::expect_int): likewise
+ 	(UnifyRules::expect_uint): likewise
+ 	(UnifyRules::expect_float): likewise
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* Make-lang.in (GRS_OBJS): Remove entries.
+ 	* rust-lang.cc: Remove inclusion of "rust-ast-resolve-item.h".
+ 	(run_rust_tests): Remove call to rust_simple_path_resolve_test.
+ 	* resolve/rust-ast-resolve-base.cc: Removed.
+ 	* resolve/rust-ast-resolve-base.h: Removed.
+ 	* resolve/rust-ast-resolve-expr.cc: Removed.
+ 	* resolve/rust-ast-resolve-expr.h: Removed.
+ 	* resolve/rust-ast-resolve-implitem.h: Removed.
+ 	* resolve/rust-ast-resolve-item.cc: Removed.
+ 	* resolve/rust-ast-resolve-item.h: Removed.
+ 	* resolve/rust-ast-resolve-path.cc: Removed.
+ 	* resolve/rust-ast-resolve-path.h: Removed.
+ 	* resolve/rust-ast-resolve-pattern.cc: Removed.
+ 	* resolve/rust-ast-resolve-pattern.h: Removed.
+ 	* resolve/rust-ast-resolve-stmt.cc: Removed.
+ 	* resolve/rust-ast-resolve-stmt.h: Removed.
+ 	* resolve/rust-ast-resolve-struct-expr-field.cc: Removed.
+ 	* resolve/rust-ast-resolve-struct-expr-field.h: Removed.
+ 	* resolve/rust-ast-resolve-toplevel.h: Removed.
+ 	* resolve/rust-ast-resolve-type.cc: Removed.
+ 	* resolve/rust-ast-resolve-type.h: Removed.
+ 	* resolve/rust-ast-resolve.cc: Removed.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* resolve/rust-late-name-resolver-2.0.cc (Late::visit): Use
+ 	resolve_type_path_like in overloads for TypePath,
+ 	StructExprStruct, StructExprStructBase, and
+ 	StructExprStructFields.
+ 	(resolve_type_path_like): New static function based off
+ 	Late::visit overload for TypePath.
+ 	* util/rust-unwrap-segment.h (unwrap_segment_error_string): New
+ 	inline static function definitions.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-compile-expr.cc (CompileExpr::visit): add guard
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-compile-context.h: add assertions for context peeks
+ 	* backend/rust-compile-expr.cc (CompileExpr::visit): check for valid loop context
+ 	(CompileExpr::array_copied_expr): just reuse array tyty capacity value
+ 	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): catch error
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* checks/errors/rust-readonly-check.cc (collect_assignment_tuple): Implement
+ 	read-only checker for tuple patterns with rest pattern.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* backend/rust-compile-var-decl.h (CompileVarDecl::visit(TuplePattern)): Implement
+ 	variable declaration bindings for tuple patterns with rest pattern (i.e.
+ 	TuplePatternItemsHasRest).
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* util/rust-attribute-values.h
+ 	(Attributes::RUSTC_ALLOW_CONST_FN_UNSTABLE): New static
+ 	constexpr member variable.
+ 	* util/rust-attributes.cc (__definitions): Add entry for
+ 	RUSTC_ALLOW_CONST_FN_UNSTABLE.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-unify.cc (UnifyRules::commit): commit hook update
+ 	(UnifyRules::go): insert implicit infer const types
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-unify.cc (UnifyRules::go): unwrap the const type
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-hir-type-check-base.cc (walk_types_to_constrain): track the ref as well
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-tyty-subst.cc: const generic arguments dont have a value yet
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-tyty.cc (VariantDef::clone): fix formatting
+ 	(VariantDef::monomorphized_clone): likewise
+ 	* typecheck/rust-tyty.h: likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-tyty.cc (InferType::can_eq): remove
+ 	(ErrorType::can_eq): likewise
+ 	(ADTType::can_eq): likewise
+ 	(TupleType::can_eq): likewise
+ 	(FnType::can_eq): likewise
+ 	(FnPtr::can_eq): likewise
+ 	(ClosureType::can_eq): likewise
+ 	(ArrayType::can_eq): likewise
+ 	(SliceType::can_eq): likewise
+ 	(BoolType::can_eq): likewise
+ 	(IntType::can_eq): likewise
+ 	(UintType::can_eq): likewise
+ 	(FloatType::can_eq): likewise
+ 	(USizeType::can_eq): likewise
+ 	(ISizeType::can_eq): likewise
+ 	(CharType::can_eq): likewise
+ 	(ReferenceType::can_eq): likewise
+ 	(PointerType::can_eq): likewise
+ 	(ParamType::can_eq): likewise
+ 	(ConstType::can_eq): likewise
+ 	(OpaqueType::can_eq): likewise
+ 	(StrType::can_eq): likewise
+ 	(NeverType::can_eq): likewise
+ 	(PlaceholderType::can_eq): likewise
+ 	(ProjectionType::can_eq): likewise
+ 	(DynamicObjectType::can_eq): likewise
+ 	* typecheck/rust-tyty.h: remove can_eq
+ 	* typecheck/rust-tyty-cmp.h: Removed.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-tyty.cc (ParamType::is_equal): uses types_compatable
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-unify.cc (unify_error_type_node): new static node
+ 	(UnifyRules::go): likewise
+ 	(UnifyRules::expect_inference_variable): likewise
+ 	(UnifyRules::expect_adt): likewise
+ 	(UnifyRules::expect_str): likewise
+ 	(UnifyRules::expect_reference): likewise
+ 	(UnifyRules::expect_pointer): likewise
+ 	(UnifyRules::expect_param): likewise
+ 	(UnifyRules::expect_array): likewise
+ 	(UnifyRules::expect_slice): likewise
+ 	(UnifyRules::expect_fndef): likewise
+ 	(UnifyRules::expect_fnptr): likewise
+ 	(UnifyRules::expect_tuple): likewise
+ 	(UnifyRules::expect_bool): likewise
+ 	(UnifyRules::expect_char): likewise
+ 	(UnifyRules::expect_int): likewise
+ 	(UnifyRules::expect_uint): likewise
+ 	(UnifyRules::expect_float): likewise
+ 	(UnifyRules::expect_isize): likewise
+ 	(UnifyRules::expect_usize): likewise
+ 	(UnifyRules::expect_never): likewise
+ 	(UnifyRules::expect_placeholder): likewise
+ 	(UnifyRules::expect_projection): likewise
+ 	(UnifyRules::expect_dyn): likewise
+ 	(UnifyRules::expect_closure): likewise
+ 	(UnifyRules::expect_opaque): likewise
+ 	(UnifyRules::expect_const): likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-unify.cc (UnifyRules::Resolve): check for success
+ 	(UnifyRules::expect_inference_variable): dont clone
+ 	(UnifyRules::expect_adt): likewise
+ 	(UnifyRules::expect_str): likewise
+ 	(UnifyRules::expect_reference): likewise
+ 	(UnifyRules::expect_pointer): likewise
+ 	(UnifyRules::expect_param): likewise
+ 	(UnifyRules::expect_array): likewise
+ 	(UnifyRules::expect_slice): likewise
+ 	(UnifyRules::expect_fndef): likewise
+ 	(UnifyRules::expect_fnptr): likewise
+ 	(UnifyRules::expect_tuple): likewise
+ 	(UnifyRules::expect_bool): likewise
+ 	(UnifyRules::expect_char): likewise
+ 	(UnifyRules::expect_int): likewise
+ 	(UnifyRules::expect_uint): likewise
+ 	(UnifyRules::expect_float): likewise
+ 	(UnifyRules::expect_isize): likewise
+ 	(UnifyRules::expect_usize): likewise
+ 	(UnifyRules::expect_never): likewise
+ 	(UnifyRules::expect_placeholder): likewise
+ 	(UnifyRules::expect_projection): likewise
+ 	(UnifyRules::expect_dyn): likewise
+ 	(UnifyRules::expect_closure): likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-tyty.cc (BaseType::satisfies_bound): use types_compatable instead
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-type-util.cc (types_compatable):  add check bounds flag
+ 	(unify_site_and): likewise
+ 	* typecheck/rust-type-util.h (types_compatable): likewise
+ 	(unify_site_and): likewise
+ 	* typecheck/rust-tyty-bounds.cc: likewise
+ 	* typecheck/rust-unify.cc (UnifyRules::UnifyRules): likewise
+ 	(UnifyRules::Resolve): likewise
+ 	(UnifyRules::resolve_subtype): likewise
+ 	(UnifyRules::go): likewise
+ 	* typecheck/rust-unify.h: likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-hir-path-probe.cc (PathProbeType::process_impl_item_candidate):
+ 	refactor to types_compatable
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-unify.cc (UnifyRules::expect_inference_variable): dont commit
+ 	(UnifyRules::expect_adt): likewise
+ 	(UnifyRules::expect_bool): likewise
+ 	(UnifyRules::expect_char): likewise
+ 	(UnifyRules::expect_int): likewise
+ 	(UnifyRules::expect_uint): likewise
+ 	(UnifyRules::expect_float): likewise
+ 	(UnifyRules::expect_isize): likewise
+ 	(UnifyRules::expect_usize): likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* backend/rust-compile-base.h: remove const
+ 	* backend/rust-compile-expr.cc: likewise
+ 	* backend/rust-compile.cc (HIRCompileBase::coerce_to_dyn_object): likewise
+ 	* typecheck/rust-hir-type-bounds.h: likewise
+ 	* typecheck/rust-type-util.cc (lookup_associated_impl_block): likewise
+ 	* typecheck/rust-type-util.h (lookup_associated_impl_block): likewise
+ 	* typecheck/rust-tyty-bounds.cc (TypeBoundsProbe::TypeBoundsProbe): likewise
+ 	(TypeBoundsProbe::Probe): likewise
+ 	* typecheck/rust-tyty-cmp.h: likewise
+ 	* typecheck/rust-tyty-subst.cc (SubstitutionRef::monomorphize): likewise
+ 	* typecheck/rust-tyty.cc (BaseType::satisfies_bound): likewise
+ 	(BaseType::bounds_compatible): likewise
+ 	(VariantDef::clone): likewise
+ 	(VariantDef::monomorphized_clone): likewise
+ 	(OpaqueType::is_equal): likewise
+ 	(DynamicObjectType::is_equal): likewise
+ 	* typecheck/rust-tyty.h: likewise
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* typecheck/rust-coercion.cc (TypeCoercionRules::select): respect try flag
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* resolve/rust-early-name-resolver-2.0.cc (Early::finalize_rebind_import):
+ 	Replace assert with early break and remove early return.
+ 	(Early::visit): Check for unsuffixed lower self list.
+ 	* resolve/rust-early-name-resolver-2.0.h: Add visit function prototype.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* resolve/rust-early-name-resolver-2.0.cc (Early::visit): Emit an error
+ 	on top level rebind self use declaration.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* Make-lang.in (GRS_OBJS): Add "rust-resolve-builtins.o".
+ 	* resolve/rust-late-name-resolver-2.0.cc: Include
+ 	"rust-resolve-builtins.h".
+ 	(next_node_id): Remove function.
+ 	(next_hir_id): Likewise.
+ 	(Late::setup_builtin_types): Likewise.
+ 	(Late::go): Use Builtins::setup_type_ctx instead of
+ 	Late::setup_builtin_types.
+ 	* resolve/rust-late-name-resolver-2.0.h
+ 	(Late::setup_builtin_types): Remove function.
+ 	* rust-session-manager.cc: Include "rust-resolve-builtins.h".
+ 	(Session::expansion): Call Builtins::setup_lang_prelude.
+ 	* resolve/rust-resolve-builtins.cc: New file.
+ 	* resolve/rust-resolve-builtins.h: New file.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* parse/rust-parse-impl.h (Parser::left_denotation): Remove
+ 	usage of parse_tuple_index_expr_float.
+ 	(Parser::parse_closure_expr_pratt): Remove function.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust-session-manager.cc (Session::compile_crate): Move the AST dump
+ 	after parser error check.
+ 
+ 2025-10-30  Arthur Cohen  <arthur.cohen@embecosm.com>
+ 
+ 	* ast/rust-expression-yeast.cc (ExpressionYeast::dispatch): Rename to...
+ 	(ExpressionYeast::reseat): ...this.
+ 	(ExpressionYeast::visit): Remove.
+ 	* ast/rust-expression-yeast.h: Inherit from PointerVisitor, override reseat instead
+ 	of declaring dispatch.
+ 
+ 2025-10-30  Arthur Cohen  <arthur.cohen@embecosm.com>
+ 
+ 	* Make-lang.in: Compile it.
+ 	* ast/rust-builtin-ast-nodes.h: Add missing methods for getting pointers.
+ 	* ast/rust-expr.h: Likewise.
+ 	* ast/rust-item.h: Likewise.
+ 	* ast/rust-path.h: Likewise.
+ 	* ast/rust-pattern.h: Likewise.
+ 	* ast/rust-type.h: Likewise.
+ 	* ast/rust-ast-pointer-visitor.cc: New file.
+ 	* ast/rust-ast-pointer-visitor.h: New file.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-expr.h (class TupleIndexExpr): Store strip information.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* checks/errors/borrowck/rust-bir-builder-internal.h: Remove
+ 	inclusion of "rust-name-resolver.h".
+ 	(BuilderContext::resolver): Change type to nr2.0 resolver.
+ 	(BuilderContext::BuilderContext): Change initialization of
+ 	resolver reference.
+ 	(AbstractBuilder::resolve_label): Assume name resolution 2.0 is
+ 	enabled.
+ 	(AbstractBuilder::resolve_variable): Likewise.
+ 	(AbstractBuilder::resolve_variable_or_fn): Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* checks/errors/rust-hir-pattern-analysis.cc: Remove inclusion
+ 	of "options.h".
+ 	(PatternChecker::PatternChecker): Change initialization of
+ 	resolver reference.
+ 	(PatternChecker::visit): Assume name resolution 2.0 is enabled.
+ 	* checks/errors/rust-hir-pattern-analysis.h: Include nr2.0
+ 	header instead of nr1.0 header.
+ 	(PatternChecker::resolver): Change type to nr2.0 resolver.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust-session-manager.cc: Remove inclusion of name resolution
+ 	1.0 headers.
+ 	(Session::compile_crate): Assume name resolution 2.0 is enabled.
+ 	(Session::expansion): Likewise.
+ 	(Session::load_extern_crate): Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* checks/errors/privacy/rust-privacy-check.cc: Adjust includes.
+ 	(Resolver::resolve): Pass 2.0 name resolution context to
+ 	VisibilityResolver and PrivacyReporter.
+ 	* checks/errors/privacy/rust-privacy-reporter.cc
+ 	(PrivacyReporter::PrivacyReporter): Change type of resolver
+ 	parameter.
+ 	(is_child_module): Remove static function.
+ 	(PrivacyReporter::check_for_privacy_violation): Assume nr2.0 is
+ 	enabled and handle removal of is_child_module.
+ 	* checks/errors/privacy/rust-privacy-reporter.h: Adjust
+ 	includes.
+ 	(PrivacyReporter::PrivacyReporter): Change type of resolver
+ 	parameter.
+ 	(PrivacyReporter::resolver): Change member variable type.
+ 	* checks/errors/privacy/rust-visibility-resolver.cc: Adjust
+ 	includes.
+ 	(VisibilityResolver::VisibilityResolver): Change type of
+ 	resolver parameter.
+ 	(VisibilityResolver::resolve_module_path): Assume nr2.0 is
+ 	enabled.
+ 	* checks/errors/privacy/rust-visibility-resolver.h: Adjust
+ 	includes.
+ 	(VisibilityResolver::VisibilityResolver): Change type of
+ 	resolver parameter.
+ 	(VisibilityResolver::resolver): Change member variable type.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* ast/rust-pattern.h:
+ 		- Add a new base abstract class `PatternItems` which are used by pattern items class
+ 		class derivatives for `TuplePattern`, `TupleStructPattern` & `SlicePattern`.
+ 		- Standardized the derived class names to have `HasRest` or `NoRest` as suffixes.
+ 		 - Values for the common `ItemType` enum is updated to `HAS_REST` or `NO_REST`.
+ 	* ast/rust-pattern.cc: Renamed the classes accordingly.
+ 	* ast/rust-ast-collector.cc: Renamed the classes accordingly.
+ 	* ast/rust-ast-collector.h: Renamed the classes accordingly.
+ 	* ast/rust-ast-full-decls.h: Renamed the classes accordingly.
+ 	* ast/rust-ast-visitor.cc: Renamed the classes accordingly.
+ 	* ast/rust-ast-visitor.h: Renamed the classes accordingly.
+ 	* ast/rust-desugar-for-loops.cc: Renamed the classes accordingly.
+ 	* ast/rust-desugar-question-mark.cc: Renamed the classes accordingly.
+ 	* expand/rust-cfg-strip.cc: Renamed the classes accordingly.
+ 	* expand/rust-cfg-strip.h: Renamed the classes accordingly.
+ 	* expand/rust-derive-clone.cc: Renamed the classes accordingly.
+ 	* expand/rust-derive-cmp-common.cc: Renamed the classes accordingly.
+ 	* expand/rust-derive-hash.cc: Renamed the classes accordingly.
+ 	* expand/rust-derive-ord.cc: Renamed the classes accordingly.
+ 	* expand/rust-derive-partial-eq.cc: Renamed the classes accordingly.
+ 	* expand/rust-derive.h: Renamed the classes accordingly.
+ 	* expand/rust-expand-visitor.cc: Renamed the classes accordingly.
+ 	* expand/rust-expand-visitor.h: Renamed the classes accordingly.
+ 	* hir/rust-ast-lower-base.cc: Renamed the classes accordingly.
+ 	* hir/rust-ast-lower-base.h: Renamed the classes accordingly.
+ 	* hir/rust-ast-lower-pattern.cc: Renamed the classes accordingly.
+ 	* hir/tree/rust-hir-pattern.h: Renamed the classes accordingly.
+ 	* parse/rust-parse-impl.h: Renamed the classes accordingly.
+ 	* resolve/rust-ast-resolve-base.cc: Renamed the classes accordingly.
+ 	* resolve/rust-ast-resolve-base.h: Renamed the classes accordingly.
+ 	* resolve/rust-ast-resolve-pattern.cc: Renamed the classes accordingly.
+ 	* util/rust-attributes.cc: Renamed the classes accordingly.
+ 	* util/rust-attributes.h: Renamed the classes accordingly.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* ast/rust-ast-collector.cc (TokenCollector::visit): Use
+ 	should_have_str instead of has_str.
+ 	* ast/rust-ast.cc (Token::as_string): Likewise.
+ 	* expand/rust-macro-builtins-offset-of.cc
+ 	(MacroBuiltin::offset_of_handler): Likewise.
+ 	* lex/rust-lex.cc (Lexer::dump_and_skip): Likewise.
+ 	* ast/rust-ast.h (class Token): Remove dead code.
+ 	(Token::has_str): Remove function.
+ 	(Token::should_have_str): New function.
+ 	* lex/rust-token.cc (Token::get_str): Remove function
+ 	definition.
+ 	* lex/rust-token.h: Include "rust-diagnostics.h".
+ 	(Token::str): Change type from std::unique_ptr<std::string> to
+ 	std::string.
+ 	(Token::Token): Adjust initialization of str member variable and
+ 	the type of the parameter used to initialize it.
+ 	(Token::make_identifier): Accept std::string instead of rvalue
+ 	reference to std::string.
+ 	(Token::make_int): Likewise.
+ 	(Token::make_float): Likewise.
+ 	(Token::make_string): Likewise.
+ 	(Token::make_byte_string): Likewise.
+ 	(Token::make_raw_string): Likewise.
+ 	(Token::make_inner_doc_comment): Likewise.
+ 	(Token::make_outer_doc_comment): Likewise.
+ 	(Token::make_lifetime): Likewise.
+ 	(Token::get_str): Add definition to function declaration.
+ 	(Token::has_str): Remove member function.
+ 	(Token::should_have_str): Handle INNER_DOC_COMMENT and
+ 	OUTER_DOC_COMMENT.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* expand/rust-macro-builtins-format-args.cc
+ 	(format_args_parse_arguments): Split format expression parsing
+ 	into...
+ 	(format_args_parse_expr): ...a new function here, while handling
+ 	eager expansion.
+ 	(MacroBuiltin::format_args_handler): Use format_args_parse_expr.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* parse/rust-parse-impl.h (Parser::parse_expr): Avoid skipping
+ 	or splitting tokens.
+ 	(Parser::null_denotation): Assume initial token was not skipped
+ 	and adjust function signature to match. Use
+ 	parse_path_in_expression instead of
+ 	parse_path_in_expression_pratt and handle SCOPE_RESOLUTION.
+ 	(Parser::parse_path_in_expression_pratt): Remove function.
+ 	* parse/rust-parse.h (null_denotation): Remove initial token
+ 	parameter.
+ 	(parse_path_in_expression_pratt): Remove function.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-coercion.cc (TypeCoercionRules::do_coercion): Use as
+ 	member function.
+ 	(TypeCoercionRules::coerce_borrowed_pointer): Likewise.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-coercion.cc (TypeCoercionRules::do_coercion):
+ 	Move nevertype coercion from here...
+ 	(TypeCoercionRules::coerce_never): ... to here.
+ 	* typecheck/rust-coercion.h: Add function prototype.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-coercion.cc (TypeCoercionRules::do_coercion): Adapt
+ 	call to new return type.
+ 	(TypeCoercionRules::coerce_unsized): Change error handling.
+ 	* typecheck/rust-coercion.h: Update function prototype and add new
+ 	CoerceUnsizedError error type.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-coercion.cc (TypeCoercionRules::do_coercion): Refactor
+ 	common return statement.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): Remove
+ 	unused assignment.
+ 	* typecheck/rust-hir-type-check-path.cc (TypeCheckExpr::resolve_segments):
+ 	Likewise.
+ 	* typecheck/rust-tyty.cc (ParamType::handle_substitions): Likewise.
+ 	* typecheck/rust-unify.cc (UnifyRules::go): Likewise.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-hir-trait-resolve.cc (TraitResolver::resolve_trait):
+ 	Construct value in place.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* resolve/rust-ast-resolve-stmt.cc (ResolveStmt::visit): Remove
+ 	unused copy.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* backend/rust-compile-expr.cc (CompileExpr::generate_closure_fntype):
+ 	Unwrap the optional.
+ 	* backend/rust-compile.cc: Change return type container. Adapt code to
+ 	new return type.
+ 	* typecheck/rust-hir-dot-operator.cc: Likewise.
+ 	* typecheck/rust-hir-path-probe.cc: Likewise.
+ 	* typecheck/rust-hir-type-check-implitem.cc (TypeCheckImplItemWithTrait::visit):
+ 	Likewise.
+ 	* typecheck/rust-hir-type-check-type.cc (TypeCheckType::visit):
+ 	Likewise.
+ 	* typecheck/rust-tyty-bounds.cc (TypeBoundPredicate::contains_item):
+ 	Likewise.
+ 	(TypeBoundPredicate::lookup_associated_item): Likewise.
+ 	(TypeBoundPredicateItem::get_parent): Likewise.
+ 	(TypeBoundPredicate::lookup_associated_type): Likewise.
+ 	* typecheck/rust-tyty.cc (BaseType::satisfies_bound): Likewise.
+ 	* typecheck/rust-hir-type-check-path.cc (TypeCheckExpr::visit): Change
+ 	return type.
+ 	* typecheck/rust-tyty.h: Likewise.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-casts.cc (TypeCastRules::cast_rules): Authorize
+ 	cast from function pointer to integer like type.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* typecheck/rust-hir-type-check-base.cc (walk_type_to_constrain): Walk
+ 	through all kind of type to collect ty leaves.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-type.h: Prevent reconstruction on null pointers.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* util/rust-attribute-values.h (Attributes::SIMD_TEST): Remove
+ 	static constexpr member variable.
+ 	* util/rust-attributes.cc (__definitions): Remove entry for
+ 	SIMD_TEST.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* parse/rust-parse-impl.h (Parser::parse_identifier_pattern):
+ 	Use parse_pattern_no_alt to parse identifier pattern
+ 	subpatterns.
+ 	(Parser::parse_ident_leading_pattern): Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* ast/rust-fmt.cc (Pieces::collect): Handle changes to ffi
+ 	interface.
+ 	(Pieces::~Pieces): Remove function definition.
+ 	(Pieces::Pieces): Likewise.
+ 	(Pieces::operator=): Likewise.
+ 	* ast/rust-fmt.h: Include "optional.h".
+ 	(rust_ffi_alloc): New extern "C" function declaration.
+ 	(rust_ffi_dealloc): Likewise.
+ 	(class FFIVec): New class.
+ 	(class FFIOpt): Likewise.
+ 	(RustHamster::RustHamster): New constructor accepting const
+ 	std::string reference.
+ 	(struct FormatSpec): Use FFIOpt.
+ 	(struct PieceSlice): Remove struct.
+ 	(struct RustString): Likewise.
+ 	(struct FormatArgsHandle): Likewise.
+ 	(collect_pieces): Change function signature.
+ 	(clone_pieces): Likewise.
+ 	(destroy_pieces): Remove extern "C" function declaration.
+ 	(Pieces::~Pieces): Remove function declaration.
+ 	(Pieces::operator=): Likewise.
+ 	(Pieces::get_pieces): Handle changes to class fields.
+ 	(Pieces::Pieces): Remove copy and move constructor declarations,
+ 	adjust signature of remaining constructor declaration.
+ 	(Pieces::pieces_vector): Remove member variable.
+ 	(Pieces::handle): Likewise.
+ 	(Pieces::data): Add member variable.
+ 	* expand/rust-macro-builtins-asm.cc (expand_inline_asm_strings):
+ 	Use references to avoid copying.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* backend/rust-compile-pattern.cc (CompilePatternLet::visit):
+ 	Handle tuple destructuring containing by-ref.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* hir/tree/rust-hir-pattern.h: Add SlicePatternItems base class and
+ 	SlicePatternItemsNoRest/SlicePatternItemsHasRest derived classes.
+ 	Update SlicePattern to hold patterns using the new classes.
+ 	* hir/tree/rust-hir-full-decls.h: Declare new classes.
+ 	* hir/tree/rust-hir.cc: Add visits for new classes.
+ 	* hir/tree/rust-hir-visitor.h: Add visits for new classes.
+ 	* hir/tree/rust-hir-visitor.cc: Implement visits for new classes.
+ 	* hir/rust-hir-dump.h: Add visits for new classes.
+ 	* hir/rust-hir-dump.cc: Implement Dump::visit for new classes.
+ 	* hir/rust-ast-lower-base.h: Declare new lower_slice_pattern_no_rest/has_rest
+ 	methods.
+ 	* hir/rust-ast-lower-base.cc: Implement lower_slice_pattern_no_rest/has_rest
+ 	to lower AST slice pattern items to HIR.
+ 	* hir/rust-ast-lower-pattern.cc: Update ASTLoweringPattern::visit for
+ 	SlicePattern to use new lowering methods.
+ 	* backend/rust-compile-pattern.cc: Update CompilePatternCheckExpr::visit
+ 	and CompilePatternBindings::visit for SlicePattern to handle
+ 	SlicePatternItemsNoRest/HasRest.
+ 	* checks/errors/borrowck/rust-bir-builder-pattern.cc: Update
+ 	PatternBindingBuilder::visit for SlicePattern to iterate members correctly.
+ 	* checks/errors/borrowck/rust-bir-builder-struct.h: Add visits for new
+ 	classes.
+ 	* checks/errors/borrowck/rust-function-collector.h: Add visits for new
+ 	classes.
+ 	* checks/errors/rust-const-checker.h: Add visits for new classes.
+ 	* checks/errors/rust-const-checker.cc: Implement empty visits for new classes.
+ 	* checks/errors/rust-hir-pattern-analysis.h: Add visits for new classes.
+ 	* checks/errors/rust-hir-pattern-analysis.cc: Implement empty visits for new
+ 	classes.
+ 	* checks/errors/rust-unsafe-checker.h: Add visits for new classes.
+ 	* checks/errors/rust-unsafe-checker.cc: Implement empty visits for new
+ 	classes.
+ 	* typecheck/rust-hir-type-check-pattern.cc: Update TypeCheckPattern::visit
+ 	for SlicePattern to handle SlicePatternItemsNoRest/HasRest.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust-session-manager.cc (Session::compile_crate): Collect lang
+ 	items after expansion.
+ 
+ 2025-10-30  Ryutaro Okada  <1015ryu88@gmail.com>
+ 
+ 	* Make-lang.in: Replace old read-only checker with new implementation.
+ 	* checks/errors/rust-readonly-check.cc (ReadonlyChecker::ReadonlyChecker):
+ 	Replace old read-only checker with new implementation.
+ 	* checks/errors/rust-readonly-check.h:
+ 	Replace old read-only checker with new implementation.
+ 	* rust-session-manager.cc (Session::compile_crate):
+ 	Switch to new read-only checker.
+ 	* checks/errors/rust-readonly-check2.cc: Removed.
+ 	* checks/errors/rust-readonly-check2.h: Removed.
+ 
+ 2025-10-30  Ryutaro Okada  <1015ryu88@gmail.com>
+ 
+ 	* checks/errors/rust-readonly-check2.cc (ReadonlyChecker::check_variable):
+ 	Read-only check if the variable is mutable type.
+ 	(ReadonlyChecker::is_mutable_type): Read-only check if the variable is mutable type.
+ 	* checks/errors/rust-readonly-check2.h: Read-only check if the variable is mutable type.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* typecheck/rust-hir-type-check-pattern.cc(ClosureParamInfer(IdentifierPattern)):
+ 	Resolve subpattern types for IdentifierPattern.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* backend/rust-compile-pattern.cc(CompilePatternLet::visit(IdentifierPattern)):
+ 	Add support for subpatterns.
+ 	* backend/rust-compile-var-decl.h(CompileVarDecl::visit(IdentifierPattern)):
+ 	Implement compilation for subpatterns.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* typecheck/rust-hir-dot-operator.cc (MethodResolver::Select):
+ 	Skip asserts by checking candidate type and using early-continue.
+ 	(MethodResolver::try_select_predicate_candidates):
+ 	Skip invalid candidates.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* rust-gcc.cc (constructor_expression):
+ 	Ensure vec_alloc reserves at least one element.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-ast.cc (Attribute::check_cfg_predicate): Emit an error with
+ 	empty cfg_attr input.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* resolve/rust-forever-stack.hxx
+ 	(ForeverStack::resolve_segments): Remove usage of optional
+ 	reference, allow non-final path segments to resolve to types
+ 	even outside the type namespace, and allow resolution to
+ 	progress past non-final path segments which resolve to modules.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* parse/rust-parse-impl.h (Parser::parse_stmt_or_expr): Add null check
+ 	on parse_macro_invocation_partial call.
+ 	* ast/rust-path.cc (Path::convert_to_simple_path): Do not exclude
+ 	capitalized "Self".
+ 
+ 2025-10-30  Arthur Cohen  <arthur.cohen@embecosm.com>
+ 
+ 	* ast/rust-ast-fragment.cc (Fragment::is_pattern_fragment): New function.
+ 	(Fragment::take_pattern_fragment): Likewise.
+ 	(Fragment::assert_single_fragment): Likewise.
+ 	* ast/rust-ast-fragment.h: Declare them.
+ 	* ast/rust-ast.cc (SingleASTNode::SingleASTNode): Add new constructor for pattern
+ 	single AST nodes.
+ 	(SingleASTNode::operator=): Handle patterns.
+ 	(SingleASTNode::accept_vis): Likewise.
+ 	(SingleASTNode::is_error): Likewise.
+ 	(SingleASTNode::as_string): Likewise.
+ 	* ast/rust-ast.h: Add get_pattern_ptr() functions.
+ 	* ast/rust-expr.h: Likewise.
+ 	* ast/rust-item.h: Likewise.
+ 	* ast/rust-pattern.h: Likewise.
+ 	* ast/rust-stmt.h: Likewise.
+ 	* expand/rust-expand-visitor.cc (derive_item): Use new API enum values.
+ 	(expand_item_attribute): Likewise.
+ 	(expand_stmt_attribute): Likewise.
+ 	(ExpandVisitor::maybe_expand_pattern): New function.
+ 	(ExpandVisitor::expand_closure_params): Handle patterns.
+ 	(ExpandVisitor::visit): Add new visitors for patterns and missed exprs.
+ 	* expand/rust-expand-visitor.h: Declare them.
+ 	* expand/rust-macro-expand.cc (transcribe_pattern): New function.
+ 	(transcribe_context): Call it.
+ 	* expand/rust-macro-expand.h (struct MacroExpander): New Context type.
+ 
+ 2025-10-30  Arthur Cohen  <arthur.cohen@embecosm.com>
+ 
+ 	* ast/rust-ast.h: Change NodeType to enum class Kind.
+ 	* ast/rust-ast-fragment.cc: Use new names.
+ 	* ast/rust-ast-fragment.h: Likewise.
+ 	* ast/rust-ast.cc (SingleASTNode::SingleASTNode): Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* parse/rust-parse-impl.h
+ 	(Parser::parse_identifier_or_keyword_token): Record error on
+ 	failure.
+ 
+ 2025-10-30  Ryutaro Okada  <1015ryu88@gmail.com>
+ 
+ 	* resolve/rust-ast-resolve-stmt.h:
+ 	Add name resolution processing for discriminant values.
+ 
+ 2025-10-30  Ryutaro Okada  <1015ryu88@gmail.com>
+ 
+ 	* typecheck/rust-tyty-call.cc (TypeCheckCallExpr::visit): fix error code
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* expand/rust-cfg-strip.cc: Include "rust-macro-expand.h".
+ 	(fails_cfg): Rename to...
+ 	(CfgStrip::fails_cfg): ...here and handle test attributes.
+ 	(fails_cfg_with_expand): Rename to...
+ 	(CfgStrip::fails_cfg_with_expand): ...here and handle test
+ 	attributes.
+ 	* expand/rust-cfg-strip.h (struct ExpansionCfg): Forward
+ 	declare.
+ 	(CfgStrip::fails_cfg): New member function.
+ 	(CfgStrip::fails_cfg_with_expand): Likewise.
+ 	(CfgStrip::CfgStrip): Accept reference to ExpansionCfg.
+ 	(CfgStrip::expansion_cfg): New member variable.
+ 	* rust-session-manager.cc (Session::expansion): Pass
+ 	ExpansionCfg instance to CfgStrip constructor.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* resolve/rust-early-name-resolver-2.0.cc (Early::finalize_rebind_import):
+ 	Do not abort on wildcard patterns.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-expr.h: Add const getters to llvm members.
+ 	* hir/rust-ast-lower-expr.cc (check_llvm_asm_support): Check llvm_asm
+ 	usage validity.
+ 	(ASTLoweringExpr::visit): Emit an error message instead of aborting.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* expand/rust-macro-builtins-asm.cc (parse_llvm_clobbers): Expect a
+ 	comma between clobbers.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* expand/rust-macro-builtins-asm.cc (parse_asm): Simplify expression.
+ 	(parse_llvm_asm): Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* ast/rust-ast.h (Stmt::get_node_id): Make virtual.
+ 	(Type::get_node_id): Likewise.
+ 	(AssociatedItem::get_node_id): New virtual member function.
+ 	* ast/rust-expr.h (TypeCastExpr::get_casted_expr_ptr): New
+ 	member function.
+ 	(TypeCastExpr::get_type_to_cast_to_ptr): Likewise.
+ 	(ClosureExprInner::get_definition_expr_ptr): Likewise.
+ 	* ast/rust-item.h (TypeAlias::get_node_id): New member function
+ 	to override AssociatedItem::get_node_id.
+ 	(ConstantItem::get_node_id): Likewise.
+ 	* expand/rust-expand-visitor.cc
+ 	(ExpandVisitor::maybe_expand_expr): Adjust
+ 	macro_invoc_expect_id.
+ 	(ExpandVisitor::maybe_expand_type): Likewise and add an overload
+ 	for std::unique_ptr<TypeNoBounds>.
+ 	(ExpandVisitor::visit): Check macro_invoc_expect_id and
+ 	generally improve visitors so that the testsuite will still
+ 	pass.
+ 	* expand/rust-expand-visitor.h (ExpandVisitor::ExpandVisitor):
+ 	Initialize member variable macro_invoc_expect_id.
+ 	(ExpandVisitor::maybe_expand_type): Add an overload for
+ 	std::unique_ptr<TypeNoBounds>.
+ 	(ExpandVisitor::expand_macro_children): Adjust
+ 	macro_invoc_expect_id.
+ 	(ExpandVisitor::visit): Add an overload for TypeCastExpr.
+ 	(ExpandVisitor::macro_invoc_expect_id): New member variable.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* backend/rust-compile-pattern.cc (CompilePatternCheckExpr::visit):
+ 	Check upper compare operator.
+ 	* hir/rust-ast-lower-pattern.cc (ASTLoweringPattern::visit):
+ 	Handle lowering of exclusive range pattern.
+ 	* hir/tree/rust-hir-pattern.h (class RangePattern):
+ 	Add support for exclusive ranges in HIR representation.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* expand/rust-macro-expand.cc (transcribe_expression): Parse any
+ 	outer attributes before parsing an expression.
+ 	* parse/rust-parse.h (Parser::parse_outer_attributes): Make
+ 	public.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-expr.h (struct TupleClobber): Add constructor.
+ 	* backend/rust-compile-context.h (struct fncontext): Likewise.
+ 	* typecheck/rust-hir-dot-operator.h: Likewise.
+ 	* typecheck/rust-tyty-variance-analysis-private.h (struct Constraint):
+ 	Likewise.
+ 	* typecheck/rust-unify.h: Likewise.
+ 	* ast/rust-ast-builder.cc (Builder::new_lifetime_param): Add memory
+ 	reservation and construct in place.
+ 	(Builder::new_generic_args): Likewise.
+ 	* ast/rust-ast-collector.cc (TokenCollector::newline): Likewise.
+ 	(TokenCollector::indentation): Likewise.
+ 	(TokenCollector::comment): Likewise.
+ 	* ast/rust-desugar-apit.cc: Likewise.
+ 	* ast/rust-path.cc (Path::convert_to_simple_path): Likewise.
+ 	(TypePath::as_simple_path): Likewise.
+ 	* ast/rust-path.h: Likewise.
+ 	* backend/rust-compile-type.cc (TyTyResolveCompile::visit): Likewise.
+ 	(TyTyResolveCompile::create_dyn_obj_record): Likewise.
+ 	* checks/errors/rust-hir-pattern-analysis.cc (Matrix::specialize):
+ 	Likewise.
+ 	(WitnessMatrix::apply_constructor): Likewise.
+ 	(check_match_usefulness): Likewise.
+ 	* expand/rust-derive-clone.cc (DeriveClone::clone_fn): Likewise.
+ 	* expand/rust-macro-builtins-asm.cc (parse_clobber_abi): Likewise.
+ 	* expand/rust-macro-expand.cc (MacroExpander::parse_proc_macro_output):
+ 	Likewise.
+ 	* hir/rust-ast-lower-base.cc (ASTLoweringBase::lower_generic_args):
+ 	Likewise.
+ 	(ASTLoweringBase::lower_extern_block): Likewise.
+ 	* hir/rust-ast-lower-enumitem.h: Likewise.
+ 	* hir/rust-ast-lower-expr.cc (ASTLoweringExpr::visit): Likewise.
+ 	* hir/rust-ast-lower-extern.h: Likewise.
+ 	* hir/rust-ast-lower-implitem.cc (ASTLowerImplItem::visit): Likewise.
+ 	(ASTLowerTraitItem::visit): Likewise.
+ 	* hir/rust-ast-lower-item.cc (ASTLoweringItem::visit): Likewise.
+ 	* hir/rust-ast-lower-pattern.cc (ASTLoweringPattern::visit): Likewise.
+ 	* hir/rust-ast-lower.cc (ASTLowering::go): Likewise.
+ 	(ASTLoweringBlock::visit): Likewise.
+ 	(ASTLoweringIfLetBlock::desugar_iflet): Likewise.
+ 	(ASTLoweringExprWithBlock::visit): Likewise.
+ 	(ASTLowerPathInExpression::visit): Likewise.
+ 	(ASTLowerQualPathInExpression::visit): Likewise.
+ 	* hir/tree/rust-hir.cc (PathPattern::convert_to_simple_path): Likewise.
+ 	(TypePath::as_simple_path): Likewise.
+ 	* metadata/rust-export-metadata.cc (ExportContext::emit_function):
+ 	Likewise.
+ 	* parse/rust-parse-impl.h (Parser::parse_decl_macro_def): Likewise.
+ 	(Parser::parse_lifetime_params): Likewise.
+ 	* resolve/rust-ast-resolve-item.cc (ResolveTraitItems::visit):
+ 	Likewise.
+ 	(ResolveItem::visit): Likewise.
+ 	(flatten_list): Likewise.
+ 	* resolve/rust-ast-resolve-pattern.cc (PatternDeclaration::visit):
+ 	Likewise.
+ 	* typecheck/rust-autoderef.cc (AutoderefCycle::try_autoderefed):
+ 	Likewise.
+ 	* typecheck/rust-coercion.cc (TypeCoercionRules::coerce_unsized):
+ 	Likewise.
+ 	* typecheck/rust-hir-dot-operator.cc: Likewise.
+ 	* typecheck/rust-hir-path-probe.cc: Likewise.
+ 	* typecheck/rust-hir-trait-resolve.cc (TraitResolver::resolve_trait):
+ 	Likewise.
+ 	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit):
+ 	Likewise.
+ 	(TypeCheckExpr::resolve_fn_trait_call): Likewise.
+ 	* typecheck/rust-hir-type-check-implitem.cc (TypeCheckTopLevelExternItem::visit):
+ 	Likewise.
+ 	(TypeCheckImplItem::visit): Likewise.
+ 	* typecheck/rust-hir-type-check-item.cc (TypeCheckItem::visit):
+ 	Likewise.
+ 	* typecheck/rust-hir-type-check-pattern.cc (TypeCheckPattern::visit):
+ 	Likewise.
+ 	* typecheck/rust-hir-type-check-struct.cc (TypeCheckStructExpr::resolve):
+ 	Likewise.
+ 	* typecheck/rust-hir-type-check-type.cc (TypeCheckType::visit):
+ 	Likewise.
+ 	* typecheck/rust-hir-type-check.cc (TraitItemReference::get_type_from_fn):
+ 	Likewise.
+ 	* typecheck/rust-typecheck-context.cc (TypeCheckContext::push_return_type):
+ 	Likewise.
+ 	(TypeCheckContext::insert_associated_impl_mapping): Likewise.
+ 	* typecheck/rust-tyty-bounds.cc (TypeBoundsProbe::scan): Likewise.
+ 	(TypeBoundsProbe::add_trait_bound): Likewise.
+ 	(TypeBoundPredicate::operator=): Likewise.
+ 	(TypeBoundPredicateItem::get_tyty_for_receiver): Likewise.
+ 	(TypeBoundPredicate::get_associated_type_items): Likewise.
+ 	* typecheck/rust-tyty-call.cc (TypeCheckMethodCallExpr::go): Likewise.
+ 	* typecheck/rust-tyty-subst.cc (SubstitutionRef::clone_substs):
+ 	Likewise.
+ 	(SubstitutionRef::infer_substitions): Likewise.
+ 	(SubstitutionRef::are_mappings_bound): Likewise.
+ 	* typecheck/rust-tyty-variance-analysis.cc (GenericTyPerCrateCtx::query_generic_variance):
+ 	Likewise.
+ 	(GenericTyVisitorCtx::add_constraint): Likewise.
+ 	* typecheck/rust-tyty.cc (FnPtr::clone): Likewise.
+ 	(DynamicObjectType::get_object_items): Likewise.
+ 	* typecheck/rust-unify.cc (UnifyRules::Resolve): Likewise.
+ 	(UnifyRules::go): Likewise.
+ 	(UnifyRules::expect_tuple): Likewise.
+ 	* util/rust-canonical-path.h: Likewise.
+ 	* util/rust-token-converter.cc (convert): Likewise.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* util/bi-map.h: Add include directive for required declarations.
+ 	* util/fnv-hash.h: Likewise.
+ 	* util/rust-dump.h: Likewise.
+ 	* util/rust-inline-visitor.h: Likewise.
+ 	* util/rust-unwrap-segment.h: Likewise.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* util/rust-lang-item.h (RUST_LANG_ITEM_H): Add header guards.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* parse/rust-parse.h: Change class to struct for friend qualification.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* checks/lints/rust-lint-marklive-base.h (RUST_HIR_LIVENESS_BASE):
+ 	Remove header includes.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-cond-compilation.h: Delete copy constructor for
+ 	ConfigurationAll and ConfigurationAny.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-type.h: Update member instead of parameter
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-cond-compilation.h: Move vector instead of passing it by
+ 	value.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-pattern.h: Include header directly.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-cond-compilation.h: Copy cfg_attrs
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* ast/rust-ast-formatting.h (RUST_AST_FORMATTING_H): Include required
+ 	headers directly.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* util/rust-attributes.cc (Attributes::extract_string_literal):
+ 	New function definition.
+ 	* util/rust-attributes.h (Attributes::extract_string_literal):
+ 	New function declaration.
+ 	* ast/rust-collect-lang-items.cc (get_lang_item_attr): Use
+ 	extract_string_literal.
+ 	* backend/rust-compile-base.cc: Include "rust-attributes.h".
+ 	(HIRCompileBase::handle_link_section_attribute_on_fndecl):
+ 	Use extract_string_literal.
+ 	(HIRCompileBase::handle_must_use_attribute_on_fndecl): Likewise.
+ 	* hir/rust-ast-lower-base.cc
+ 	(ASTLoweringBase::handle_lang_item_attribute): Likewise.
+ 	* rust-session-manager.cc (Session::handle_crate_name):
+ 	Likewise.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* hir/tree/rust-hir-pattern.h:
+ 		- Rename TupleItems to PatternItems.
+ 		- Rename TuplePatternItemsMultiple/Ranged & TupleStructItemsRange/NoRange to
+ 		TuplePatternItemsNoRest/HasRest and TupleStructItemsNoRest/HasRest.
+ 		- Update enum values to NO_REST/HAS_REST.
+ 		- Rename clone_tuple_items_impl to clone_pattern_items_impl.
+ 	* hir/tree/rust-hir-full-decls.h: Renamed the classes accordingly.
+ 	* hir/tree/rust-hir-visitor.h: Renamed the classes accordingly.
+ 	* hir/tree/rust-hir-visitor.cc: Renamed the classes accordingly.
+ 	* hir/rust-hir-dump.h: Renamed the classes accordingly.
+ 	* hir/rust-hir-dump.cc: Renamed the classes accordingly.
+ 	* hir/tree/rust-hir.cc: Renamed the classes accordingly.
+ 	* hir/rust-ast-lower-base.cc: Renamed the classes accordingly.
+ 	* hir/rust-ast-lower-pattern.cc: Renamed the classes accordingly.
+ 	* backend/rust-compile-pattern.cc: Renamed the classes accordingly.
+ 	* backend/rust-compile-var-decl.h: Renamed the classes accordingly.
+ 	* checks/errors/borrowck/rust-bir-builder-pattern.cc: Renamed the classes accordingly.
+ 	* checks/errors/borrowck/rust-bir-builder-struct.h: Renamed the classes accordingly.
+ 	* checks/errors/borrowck/rust-function-collector.h: Renamed the classes accordingly.
+ 	* checks/errors/rust-const-checker.cc: Renamed the classes accordingly.
+ 	* checks/errors/rust-const-checker.h: Renamed the classes accordingly.
+ 	* checks/errors/rust-hir-pattern-analysis.cc: Renamed the classes accordingly.
+ 	* checks/errors/rust-hir-pattern-analysis.h: Renamed the classes accordingly.
+ 	* checks/errors/rust-unsafe-checker.cc: Renamed the classes accordingly.
+ 	* checks/errors/rust-unsafe-checker.h: Renamed the classes accordingly.
+ 	* checks/errors/rust-readonly-check2.cc: Renamed the classes accordingly.
+ 	* typecheck/rust-hir-type-check-pattern.cc: Update references to renamed classes and enum
+ 	values.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* expand/rust-derive-eq.cc: Use empty vector explicitly.
+ 
  2025-08-05  Ryutaro Okada  <1015ryu88@gmail.com>
  
  	* Make-lang.in (rust-readonly-check2.cc):
***************
*** 5197,5203 ****
  
  2025-03-21  Owen Avery  <powerboat9.gamer@gmail.com>
  
! 	* resolve/rust-name-resolver.cc: Include options.txt.
  	(Resolver::insert_resolved_name): Assert that name resolution
  	2.0 is disabled.
  	(Resolver::lookup_resolved_name): Likewise.
--- 6640,6646 ----
  
  2025-03-21  Owen Avery  <powerboat9.gamer@gmail.com>
  
! 	* resolve/rust-name-resolver.cc: Include options.h.
  	(Resolver::insert_resolved_name): Assert that name resolution
  	2.0 is disabled.
  	(Resolver::lookup_resolved_name): Likewise.
diff -Nrcpad gcc-16-20251026/gcc/rust/Make-lang.in gcc-16-20251102/gcc/rust/Make-lang.in
*** gcc-16-20251026/gcc/rust/Make-lang.in	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/Make-lang.in	Sun Nov  2 22:32:23 2025
*************** GRS_OBJS = \
*** 84,89 ****
--- 84,90 ----
      rust/rust-ast-dump.o \
      rust/rust-ast-collector.o \
      rust/rust-ast-visitor.o \
+     rust/rust-ast-pointer-visitor.o \
      rust/rust-hir-visitor.o \
      rust/rust-hir-dump.o \
      rust/rust-session-manager.o \
*************** GRS_OBJS = \
*** 147,163 ****
  	rust/rust-ice-finalizer.o \
      rust/rust-late-name-resolver-2.0.o \
  	rust/rust-immutable-name-resolution-context.o \
-     rust/rust-early-name-resolver.o \
      rust/rust-name-resolver.o \
!     rust/rust-ast-resolve.o \
!     rust/rust-ast-resolve-base.o \
!     rust/rust-ast-resolve-item.o \
!     rust/rust-ast-resolve-pattern.o \
!     rust/rust-ast-resolve-expr.o \
!     rust/rust-ast-resolve-type.o \
!     rust/rust-ast-resolve-path.o \
!     rust/rust-ast-resolve-stmt.o \
!     rust/rust-ast-resolve-struct-expr-field.o \
      rust/rust-forever-stack.o \
      rust/rust-hir-type-check.o \
      rust/rust-privacy-check.o \
--- 148,155 ----
  	rust/rust-ice-finalizer.o \
      rust/rust-late-name-resolver-2.0.o \
  	rust/rust-immutable-name-resolution-context.o \
      rust/rust-name-resolver.o \
!     rust/rust-resolve-builtins.o \
      rust/rust-forever-stack.o \
      rust/rust-hir-type-check.o \
      rust/rust-privacy-check.o \
*************** GRS_OBJS = \
*** 209,215 ****
      rust/rust-lint-marklive.o \
      rust/rust-lint-unused-var.o \
      rust/rust-readonly-check.o \
-     rust/rust-readonly-check2.o \
      rust/rust-hir-type-check-path.o \
      rust/rust-unsafe-checker.o \
      rust/rust-hir-pattern-analysis.o \
--- 201,206 ----
*************** RUST_INCLUDES = -I $(srcdir)/rust \
*** 443,448 ****
--- 434,440 ----
  	-I $(srcdir)/rust/checks/errors \
  	-I $(srcdir)/rust/checks/errors/privacy \
  	-I $(srcdir)/rust/checks/errors/borrowck \
+ 	-I $(srcdir)/rust/checks/errors/feature \
  	-I $(srcdir)/rust/util \
          -I $(srcdir)/rust/metadata \
  		-I $(srcdir)/../libgrust
*************** rust/%.o: rust/checks/errors/%.cc
*** 515,520 ****
--- 507,517 ----
  	$(COMPILE) $(RUST_CXXFLAGS) $(RUST_INCLUDES) $<
  	$(POSTCOMPILE)
  
+ # build feature related files in rust folder
+ rust/%.o: rust/checks/errors/feature/%.cc
+ 	$(COMPILE) $(RUST_CXXFLAGS) $(RUST_INCLUDES) $<
+ 	$(POSTCOMPILE)
+ 
  # build privacy pass files in rust folder
  rust/%.o: rust/checks/errors/privacy/%.cc
  	$(COMPILE) $(RUST_CXXFLAGS) $(RUST_INCLUDES) $<
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-builder.cc gcc-16-20251102/gcc/rust/ast/rust-ast-builder.cc
*** gcc-16-20251026/gcc/rust/ast/rust-ast-builder.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-builder.cc	Sun Nov  2 22:32:23 2025
*************** std::unique_ptr<GenericParam>
*** 554,565 ****
  Builder::new_lifetime_param (LifetimeParam &param)
  {
    Lifetime l = new_lifetime (param.get_lifetime ());
    std::vector<Lifetime> lifetime_bounds;
    for (auto b : param.get_lifetime_bounds ())
!     {
!       Lifetime bl = new_lifetime (b);
!       lifetime_bounds.push_back (bl);
!     }
  
    auto p = new LifetimeParam (l, std::move (lifetime_bounds),
  			      param.get_outer_attrs (), param.get_locus ());
--- 554,565 ----
  Builder::new_lifetime_param (LifetimeParam &param)
  {
    Lifetime l = new_lifetime (param.get_lifetime ());
+ 
    std::vector<Lifetime> lifetime_bounds;
+   lifetime_bounds.reserve (param.get_lifetime_bounds ().size ());
+ 
    for (auto b : param.get_lifetime_bounds ())
!     lifetime_bounds.emplace_back (new_lifetime (b));
  
    auto p = new LifetimeParam (l, std::move (lifetime_bounds),
  			      param.get_outer_attrs (), param.get_locus ());
*************** Builder::new_type_param (
*** 605,615 ****
  	    for (const auto &lifetime : tb.get_for_lifetimes ())
  	      {
  		std::vector<Lifetime> lifetime_bounds;
  		for (const auto &b : lifetime.get_lifetime_bounds ())
! 		  {
! 		    Lifetime bl = new_lifetime (b);
! 		    lifetime_bounds.push_back (std::move (bl));
! 		  }
  
  		Lifetime nl = new_lifetime (lifetime.get_lifetime ());
  		LifetimeParam p (std::move (nl), std::move (lifetime_bounds),
--- 605,615 ----
  	    for (const auto &lifetime : tb.get_for_lifetimes ())
  	      {
  		std::vector<Lifetime> lifetime_bounds;
+ 		lifetime_bounds.reserve (
+ 		  lifetime.get_lifetime_bounds ().size ());
+ 
  		for (const auto &b : lifetime.get_lifetime_bounds ())
! 		  lifetime_bounds.emplace_back (new_lifetime (b));
  
  		Lifetime nl = new_lifetime (lifetime.get_lifetime ());
  		LifetimeParam p (std::move (nl), std::move (lifetime_bounds),
*************** Builder::new_type_param (
*** 626,637 ****
  		    {
  		      const TypePathSegment &segment
  			= (const TypePathSegment &) (*seg.get ());
! 		      TypePathSegment *s = new TypePathSegment (
  			segment.get_ident_segment (),
  			segment.get_separating_scope_resolution (),
! 			segment.get_locus ());
! 		      std::unique_ptr<TypePathSegment> sg (s);
! 		      segments.push_back (std::move (sg));
  		    }
  		    break;
  
--- 626,636 ----
  		    {
  		      const TypePathSegment &segment
  			= (const TypePathSegment &) (*seg.get ());
! 
! 		      segments.emplace_back (new TypePathSegment (
  			segment.get_ident_segment (),
  			segment.get_separating_scope_resolution (),
! 			segment.get_locus ()));
  		    }
  		    break;
  
*************** Builder::new_type_param (
*** 642,652 ****
  
  		      GenericArgs args
  			= new_generic_args (generic.get_generic_args ());
! 		      TypePathSegmentGeneric *s = new TypePathSegmentGeneric (
  			generic.get_ident_segment (), false, std::move (args),
! 			generic.get_locus ());
! 		      std::unique_ptr<TypePathSegment> sg (s);
! 		      segments.push_back (std::move (sg));
  		    }
  		    break;
  
--- 641,650 ----
  
  		      GenericArgs args
  			= new_generic_args (generic.get_generic_args ());
! 
! 		      segments.emplace_back (new TypePathSegmentGeneric (
  			generic.get_ident_segment (), false, std::move (args),
! 			generic.get_locus ()));
  		    }
  		    break;
  
*************** Builder::new_type_param (
*** 664,675 ****
  	    TypePath p (std::move (segments), path.get_locus (),
  			path.has_opening_scope_resolution_op ());
  
! 	    TraitBound *b = new TraitBound (std::move (p), tb.get_locus (),
! 					    tb.is_in_parens (),
! 					    tb.has_opening_question_mark (),
! 					    std::move (for_lifetimes));
! 	    std::unique_ptr<TypeParamBound> bound (b);
! 	    type_param_bounds.push_back (std::move (bound));
  	  }
  	  break;
  
--- 662,670 ----
  	    TypePath p (std::move (segments), path.get_locus (),
  			path.has_opening_scope_resolution_op ());
  
! 	    type_param_bounds.emplace_back (new TraitBound (
! 	      std::move (p), tb.get_locus (), tb.is_in_parens (),
! 	      tb.has_opening_question_mark (), std::move (for_lifetimes)));
  	  }
  	  break;
  
*************** Builder::new_type_param (
*** 677,686 ****
  	  {
  	    const Lifetime &l = (const Lifetime &) *b.get ();
  
! 	    auto bl = new Lifetime (l.get_lifetime_type (),
! 				    l.get_lifetime_name (), l.get_locus ());
! 	    std::unique_ptr<TypeParamBound> bound (bl);
! 	    type_param_bounds.push_back (std::move (bound));
  	  }
  	  break;
  	}
--- 672,680 ----
  	  {
  	    const Lifetime &l = (const Lifetime &) *b.get ();
  
! 	    type_param_bounds.emplace_back (
! 	      new Lifetime (l.get_lifetime_type (), l.get_lifetime_name (),
! 			    l.get_locus ()));
  	  }
  	  break;
  	}
*************** Builder::new_generic_args (GenericArgs &
*** 709,726 ****
    location_t locus = args.get_locus ();
  
    for (const auto &lifetime : args.get_lifetime_args ())
!     {
!       Lifetime l = new_lifetime (lifetime);
!       lifetime_args.push_back (std::move (l));
!     }
  
    for (auto &binding : args.get_binding_args ())
      {
        Type &t = *binding.get_type_ptr ().get ();
        std::unique_ptr<Type> ty = t.reconstruct ();
!       GenericArgsBinding b (binding.get_identifier (), std::move (ty),
! 			    binding.get_locus ());
!       binding_args.push_back (std::move (b));
      }
  
    for (auto &arg : args.get_generic_args ())
--- 703,716 ----
    location_t locus = args.get_locus ();
  
    for (const auto &lifetime : args.get_lifetime_args ())
!     lifetime_args.push_back (new_lifetime (lifetime));
  
    for (auto &binding : args.get_binding_args ())
      {
        Type &t = *binding.get_type_ptr ().get ();
        std::unique_ptr<Type> ty = t.reconstruct ();
!       binding_args.emplace_back (binding.get_identifier (), std::move (ty),
! 				 binding.get_locus ());
      }
  
    for (auto &arg : args.get_generic_args ())
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-collector.cc gcc-16-20251102/gcc/rust/ast/rust-ast-collector.cc
*** gcc-16-20251026/gcc/rust/ast/rust-ast-collector.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-collector.cc	Sun Nov  2 22:32:23 2025
*************** TokenCollector::trailing_comma ()
*** 76,88 ****
  void
  TokenCollector::newline ()
  {
!   tokens.push_back ({CollectItem::Kind::Newline});
  }
  
  void
  TokenCollector::indentation ()
  {
!   tokens.push_back ({indent_level});
  }
  
  void
--- 76,88 ----
  void
  TokenCollector::newline ()
  {
!   tokens.emplace_back (CollectItem::Kind::Newline);
  }
  
  void
  TokenCollector::indentation ()
  {
!   tokens.emplace_back (indent_level);
  }
  
  void
*************** TokenCollector::decrement_indentation ()
*** 101,107 ****
  void
  TokenCollector::comment (std::string comment)
  {
!   tokens.push_back ({comment});
  }
  
  void
--- 101,107 ----
  void
  TokenCollector::comment (std::string comment)
  {
!   tokens.emplace_back (comment);
  }
  
  void
*************** TokenCollector::visit (MaybeNamedParam &
*** 355,361 ****
  void
  TokenCollector::visit (Token &tok)
  {
!   std::string data = tok.get_tok_ptr ()->has_str () ? tok.get_str () : "";
    switch (tok.get_id ())
      {
      case IDENTIFIER:
--- 355,362 ----
  void
  TokenCollector::visit (Token &tok)
  {
!   std::string data
!     = tok.get_tok_ptr ()->should_have_str () ? tok.get_str () : "";
    switch (tok.get_id ())
      {
      case IDENTIFIER:
*************** TokenCollector::visit (SelfParam &param)
*** 2171,2189 ****
  }
  
  void
- TokenCollector::visit (TraitItemConst &item)
- {
-   auto id = item.get_identifier ().as_string ();
-   indentation ();
-   push (Rust::Token::make (CONST, item.get_locus ()));
-   push (Rust::Token::make_identifier (UNDEF_LOCATION, std::move (id)));
-   push (Rust::Token::make (COLON, UNDEF_LOCATION));
-   visit (item.get_type ());
-   push (Rust::Token::make (SEMICOLON, UNDEF_LOCATION));
-   newline ();
- }
- 
- void
  TokenCollector::visit (TraitItemType &item)
  {
    visit_items_as_lines (item.get_outer_attrs ());
--- 2172,2177 ----
*************** TokenCollector::visit (StructPattern &pa
*** 2632,2638 ****
    if (elems.has_struct_pattern_fields ())
      {
        visit_items_joined_by_separator (elems.get_struct_pattern_fields ());
!       if (elems.has_etc ())
  	{
  	  push (Rust::Token::make (COMMA, UNDEF_LOCATION));
  	  visit_items_as_lines (elems.get_etc_outer_attrs ());
--- 2620,2626 ----
    if (elems.has_struct_pattern_fields ())
      {
        visit_items_joined_by_separator (elems.get_struct_pattern_fields ());
!       if (elems.has_rest ())
  	{
  	  push (Rust::Token::make (COMMA, UNDEF_LOCATION));
  	  visit_items_as_lines (elems.get_etc_outer_attrs ());
*************** TokenCollector::visit (StructPattern &pa
*** 2649,2661 ****
  // void TokenCollector::visit(TupleStructItems& ){}
  
  void
! TokenCollector::visit (TupleStructItemsNoRange &pattern)
  {
    visit_items_joined_by_separator (pattern.get_patterns ());
  }
  
  void
! TokenCollector::visit (TupleStructItemsRange &pattern)
  {
    for (auto &lower : pattern.get_lower_patterns ())
      {
--- 2637,2649 ----
  // void TokenCollector::visit(TupleStructItems& ){}
  
  void
! TokenCollector::visit (TupleStructItemsNoRest &pattern)
  {
    visit_items_joined_by_separator (pattern.get_patterns ());
  }
  
  void
! TokenCollector::visit (TupleStructItemsHasRest &pattern)
  {
    for (auto &lower : pattern.get_lower_patterns ())
      {
*************** TokenCollector::visit (TupleStructPatter
*** 2682,2694 ****
  // {}
  
  void
! TokenCollector::visit (TuplePatternItemsMultiple &pattern)
  {
    visit_items_joined_by_separator (pattern.get_patterns (), COMMA);
  }
  
  void
! TokenCollector::visit (TuplePatternItemsRanged &pattern)
  {
    for (auto &lower : pattern.get_lower_patterns ())
      {
--- 2670,2682 ----
  // {}
  
  void
! TokenCollector::visit (TuplePatternItemsNoRest &pattern)
  {
    visit_items_joined_by_separator (pattern.get_patterns (), COMMA);
  }
  
  void
! TokenCollector::visit (TuplePatternItemsHasRest &pattern)
  {
    for (auto &lower : pattern.get_lower_patterns ())
      {
*************** TokenCollector::visit (BareFunctionType
*** 3009,3016 ****
  void
  TokenCollector::visit (AST::FormatArgs &fmt)
  {
!   rust_sorry_at (fmt.get_locus (), "%s:%u: unimplemented FormatArgs visitor",
! 		 __FILE__, __LINE__);
  }
  
  void
--- 2997,3212 ----
  void
  TokenCollector::visit (AST::FormatArgs &fmt)
  {
!   push (Rust::Token::make_identifier (fmt.get_locus (), "format_args"));
!   push (Rust::Token::make (EXCLAM, fmt.get_locus ()));
!   push (Rust::Token::make (LEFT_PAREN, fmt.get_locus ()));
! 
!   std::string reconstructed_template = "\"";
!   const auto &template_pieces = fmt.get_template ();
! 
!   for (const auto &piece : template_pieces.get_pieces ())
!     {
!       if (piece.tag == Fmt::ffi::Piece::Tag::String)
! 	{
! 	  std::string literal = piece.string._0.to_string ();
! 	  for (char c : literal)
! 	    {
! 	      if (c == '"' || c == '\\')
! 		{
! 		  reconstructed_template += '\\';
! 		}
! 	      else if (c == '\n')
! 		{
! 		  reconstructed_template += "\\n";
! 		  continue;
! 		}
! 	      else if (c == '\r')
! 		{
! 		  reconstructed_template += "\\r";
! 		  continue;
! 		}
! 	      else if (c == '\t')
! 		{
! 		  reconstructed_template += "\\t";
! 		  continue;
! 		}
! 	      reconstructed_template += c;
! 	    }
! 	}
!       else if (piece.tag == Fmt::ffi::Piece::Tag::NextArgument)
! 	{
! 	  reconstructed_template += "{";
! 
! 	  const auto &argument = piece.next_argument._0;
! 	  const auto &position = argument.position;
! 
! 	  switch (position.tag)
! 	    {
! 	    case Fmt::ffi::Position::Tag::ArgumentImplicitlyIs:
! 	      break;
! 	    case Fmt::ffi::Position::Tag::ArgumentIs:
! 	      reconstructed_template
! 		+= std::to_string (position.argument_is._0);
! 	      break;
! 	    case Fmt::ffi::Position::Tag::ArgumentNamed:
! 	      reconstructed_template += position.argument_named._0.to_string ();
! 	      break;
! 	    }
! 
! 	  // Add format specifiers if any (like :?, :x, etc.)
! 	  const auto &format_spec = argument.format;
! 
! 	  bool has_format_spec = false;
! 	  std::string format_part;
! 
! 	  // For now, skipping the complex format specifications that use FFIOpt
! 	  // since FFIOpt::get_opt() has a bug.
! 
! 	  // Alignment
! 	  if (format_spec.align != Fmt::ffi::Alignment::AlignUnknown)
! 	    {
! 	      has_format_spec = true;
! 	      switch (format_spec.align)
! 		{
! 		case Fmt::ffi::Alignment::AlignLeft:
! 		  format_part += "<";
! 		  break;
! 		case Fmt::ffi::Alignment::AlignRight:
! 		  format_part += ">";
! 		  break;
! 		case Fmt::ffi::Alignment::AlignCenter:
! 		  format_part += "^";
! 		  break;
! 		case Fmt::ffi::Alignment::AlignUnknown:
! 		  break;
! 		}
! 	    }
! 
! 	  // Alternate flag
! 	  if (format_spec.alternate)
! 	    {
! 	      has_format_spec = true;
! 	      format_part += "#";
! 	    }
! 
! 	  // Zero pad flag
! 	  if (format_spec.zero_pad)
! 	    {
! 	      has_format_spec = true;
! 	      format_part += "0";
! 	    }
! 
! 	  // Width
! 	  if (format_spec.width.tag != Fmt::ffi::Count::Tag::CountImplied)
! 	    {
! 	      has_format_spec = true;
! 	      switch (format_spec.width.tag)
! 		{
! 		case Fmt::ffi::Count::Tag::CountIs:
! 		  format_part += std::to_string (format_spec.width.count_is._0);
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountIsParam:
! 		  format_part
! 		    += std::to_string (format_spec.width.count_is_param._0)
! 		       + "$";
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountIsName:
! 		  format_part
! 		    += format_spec.width.count_is_name._0.to_string () + "$";
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountIsStar:
! 		  format_part += "*";
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountImplied:
! 		  break;
! 		}
! 	    }
! 
! 	  // Precision
! 	  if (format_spec.precision.tag != Fmt::ffi::Count::Tag::CountImplied)
! 	    {
! 	      has_format_spec = true;
! 	      format_part += ".";
! 	      switch (format_spec.precision.tag)
! 		{
! 		case Fmt::ffi::Count::Tag::CountIs:
! 		  format_part
! 		    += std::to_string (format_spec.precision.count_is._0);
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountIsParam:
! 		  format_part
! 		    += std::to_string (format_spec.precision.count_is_param._0)
! 		       + "$";
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountIsName:
! 		  format_part
! 		    += format_spec.precision.count_is_name._0.to_string ()
! 		       + "$";
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountIsStar:
! 		  format_part += "*";
! 		  break;
! 		case Fmt::ffi::Count::Tag::CountImplied:
! 		  break;
! 		}
! 	    }
! 
! 	  // Type/trait (like ?, x, X, etc.)
! 	  std::string type_str = format_spec.ty.to_string ();
! 	  if (!type_str.empty ())
! 	    {
! 	      has_format_spec = true;
! 	      format_part += type_str;
! 	    }
! 
! 	  // Add the format specification if any
! 	  if (has_format_spec)
! 	    {
! 	      reconstructed_template += ":";
! 	      reconstructed_template += format_part;
! 	    }
! 
! 	  reconstructed_template += "}";
! 	}
!     }
!   reconstructed_template += "\"";
! 
!   push (Rust::Token::make_string (fmt.get_locus (), reconstructed_template));
! 
!   // Visit format arguments if any exist
!   auto &arguments = fmt.get_arguments ();
!   if (!arguments.empty ())
!     {
!       push (Rust::Token::make (COMMA, fmt.get_locus ()));
! 
!       auto &args = arguments.get_args ();
!       for (size_t i = 0; i < args.size (); ++i)
! 	{
! 	  if (i > 0)
! 	    {
! 	      push (Rust::Token::make (COMMA, fmt.get_locus ()));
! 	    }
! 
! 	  auto kind = args[i].get_kind ();
! 
! 	  // Handle named arguments: name = expr
! 	  if (kind.kind == FormatArgumentKind::Kind::Named)
! 	    {
! 	      auto ident = kind.get_ident ().as_string ();
! 	      push (Rust::Token::make_identifier (fmt.get_locus (),
! 						  std::move (ident)));
! 	      push (Rust::Token::make (EQUAL, fmt.get_locus ()));
! 	    }
! 	  // Note: Captured arguments are handled implicitly in the template
! 	  // reconstruction They don't need explicit "name =" syntax in the
! 	  // reconstructed macro call
! 
! 	  auto &expr = args[i].get_expr ();
! 	  expr.accept_vis (*this);
! 	}
!     }
! 
!   push (Rust::Token::make (RIGHT_PAREN, fmt.get_locus ()));
  }
  
  void
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-collector.h gcc-16-20251102/gcc/rust/ast/rust-ast-collector.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast-collector.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-collector.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 330,336 ****
    void visit (ConstantItem &const_item);
    void visit (StaticItem &static_item);
    void visit (SelfParam &param);
-   void visit (TraitItemConst &item);
    void visit (TraitItemType &item);
    void visit (Trait &trait);
    void visit (InherentImpl &impl);
--- 330,335 ----
*************** public:
*** 370,381 ****
    void visit (StructPatternFieldIdent &field);
    void visit (StructPattern &pattern);
    // void visit(TupleStructItems& tuple_items);
!   void visit (TupleStructItemsNoRange &tuple_items);
!   void visit (TupleStructItemsRange &tuple_items);
    void visit (TupleStructPattern &pattern);
    // void visit(TuplePatternItems& tuple_items);
!   void visit (TuplePatternItemsMultiple &tuple_items);
!   void visit (TuplePatternItemsRanged &tuple_items);
    void visit (TuplePattern &pattern);
    void visit (GroupedPattern &pattern);
    void visit (SlicePatternItemsNoRest &items);
--- 369,380 ----
    void visit (StructPatternFieldIdent &field);
    void visit (StructPattern &pattern);
    // void visit(TupleStructItems& tuple_items);
!   void visit (TupleStructItemsNoRest &tuple_items);
!   void visit (TupleStructItemsHasRest &tuple_items);
    void visit (TupleStructPattern &pattern);
    // void visit(TuplePatternItems& tuple_items);
!   void visit (TuplePatternItemsNoRest &tuple_items);
!   void visit (TuplePatternItemsHasRest &tuple_items);
    void visit (TuplePattern &pattern);
    void visit (GroupedPattern &pattern);
    void visit (SlicePatternItemsNoRest &items);
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-formatting.h gcc-16-20251102/gcc/rust/ast/rust-ast-formatting.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast-formatting.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-formatting.h	Sun Nov  2 22:32:23 2025
***************
*** 19,24 ****
--- 19,27 ----
  #ifndef RUST_AST_FORMATTING_H
  #define RUST_AST_FORMATTING_H
  
+ #include "rust-ast.h"
+ #include "rust-system.h"
+ 
  namespace Rust {
  namespace AST {
  
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-fragment.cc gcc-16-20251102/gcc/rust/ast/rust-ast-fragment.cc
*** gcc-16-20251026/gcc/rust/ast/rust-ast-fragment.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-fragment.cc	Sun Nov  2 22:32:23 2025
*************** Fragment::should_expand () const
*** 107,135 ****
  bool
  Fragment::is_expression_fragment () const
  {
!   return is_single_fragment_of_kind (SingleASTNode::NodeType::EXPRESSION);
  }
  
  bool
  Fragment::is_type_fragment () const
  {
!   return is_single_fragment_of_kind (SingleASTNode::NodeType::TYPE);
  }
  
  std::unique_ptr<Expr>
  Fragment::take_expression_fragment ()
  {
!   assert_single_fragment (SingleASTNode::NodeType::EXPRESSION);
    return nodes[0].take_expr ();
  }
  
  std::unique_ptr<Type>
  Fragment::take_type_fragment ()
  {
!   assert_single_fragment (SingleASTNode::NodeType::TYPE);
    return nodes[0].take_type ();
  }
  
  void
  Fragment::accept_vis (ASTVisitor &vis)
  {
--- 107,148 ----
  bool
  Fragment::is_expression_fragment () const
  {
!   return is_single_fragment_of_kind (SingleASTNode::Kind::Expr);
  }
  
  bool
  Fragment::is_type_fragment () const
  {
!   return is_single_fragment_of_kind (SingleASTNode::Kind::Type);
! }
! 
! bool
! Fragment::is_pattern_fragment () const
! {
!   return is_single_fragment_of_kind (SingleASTNode::Kind::Pattern);
  }
  
  std::unique_ptr<Expr>
  Fragment::take_expression_fragment ()
  {
!   assert_single_fragment (SingleASTNode::Kind::Expr);
    return nodes[0].take_expr ();
  }
  
  std::unique_ptr<Type>
  Fragment::take_type_fragment ()
  {
!   assert_single_fragment (SingleASTNode::Kind::Type);
    return nodes[0].take_type ();
  }
  
+ std::unique_ptr<Pattern>
+ Fragment::take_pattern_fragment ()
+ {
+   assert_single_fragment (SingleASTNode::Kind::Pattern);
+   return nodes[0].take_pattern ();
+ }
+ 
  void
  Fragment::accept_vis (ASTVisitor &vis)
  {
*************** Fragment::is_single_fragment () const
*** 144,164 ****
  }
  
  bool
! Fragment::is_single_fragment_of_kind (SingleASTNode::NodeType expected) const
  {
    return is_single_fragment () && nodes[0].get_kind () == expected;
  }
  
  void
! Fragment::assert_single_fragment (SingleASTNode::NodeType expected) const
  {
!   static const std::map<SingleASTNode::NodeType, const char *> str_map = {
!     {SingleASTNode::NodeType::ASSOC_ITEM, "associated item"},
!     {SingleASTNode::NodeType::ITEM, "item"},
!     {SingleASTNode::NodeType::TYPE, "type"},
!     {SingleASTNode::NodeType::EXPRESSION, "expr"},
!     {SingleASTNode::NodeType::STMT, "stmt"},
!     {SingleASTNode::NodeType::EXTERN, "extern"},
    };
  
    auto actual = nodes[0].get_kind ();
--- 157,178 ----
  }
  
  bool
! Fragment::is_single_fragment_of_kind (SingleASTNode::Kind expected) const
  {
    return is_single_fragment () && nodes[0].get_kind () == expected;
  }
  
  void
! Fragment::assert_single_fragment (SingleASTNode::Kind expected) const
  {
!   static const std::map<SingleASTNode::Kind, const char *> str_map = {
!     {SingleASTNode::Kind::Assoc, "associated item"},
!     {SingleASTNode::Kind::Item, "item"},
!     {SingleASTNode::Kind::Type, "type"},
!     {SingleASTNode::Kind::Expr, "expr"},
!     {SingleASTNode::Kind::Stmt, "stmt"},
!     {SingleASTNode::Kind::Extern, "extern"},
!     {SingleASTNode::Kind::Pattern, "pattern"},
    };
  
    auto actual = nodes[0].get_kind ();
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-fragment.h gcc-16-20251102/gcc/rust/ast/rust-ast-fragment.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast-fragment.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-fragment.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 86,94 ****
--- 86,96 ----
  
    bool is_expression_fragment () const;
    bool is_type_fragment () const;
+   bool is_pattern_fragment () const;
  
    std::unique_ptr<Expr> take_expression_fragment ();
    std::unique_ptr<Type> take_type_fragment ();
+   std::unique_ptr<Pattern> take_pattern_fragment ();
  
    void accept_vis (ASTVisitor &vis);
  
*************** private:
*** 119,126 ****
     * one Node will be extracted from the `nodes` vector
     */
    bool is_single_fragment () const;
!   bool is_single_fragment_of_kind (SingleASTNode::NodeType expected) const;
!   void assert_single_fragment (SingleASTNode::NodeType expected) const;
  };
  
  enum class InvocKind
--- 121,128 ----
     * one Node will be extracted from the `nodes` vector
     */
    bool is_single_fragment () const;
!   bool is_single_fragment_of_kind (SingleASTNode::Kind expected) const;
!   void assert_single_fragment (SingleASTNode::Kind expected) const;
  };
  
  enum class InvocKind
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-full-decls.h gcc-16-20251102/gcc/rust/ast/rust-ast-full-decls.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast-full-decls.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-full-decls.h	Sun Nov  2 22:32:23 2025
*************** class Enum;
*** 195,201 ****
  class Union;
  class ConstantItem;
  class StaticItem;
- class TraitItemConst;
  class TraitItemType;
  class Trait;
  class Impl;
--- 195,200 ----
*************** class StructPatternFieldIdent;
*** 240,251 ****
  class StructPatternElements;
  class StructPattern;
  class TupleStructItems;
! class TupleStructItemsNoRange;
! class TupleStructItemsRange;
  class TupleStructPattern;
  class TuplePatternItems;
! class TuplePatternItemsMultiple;
! class TuplePatternItemsRanged;
  class TuplePattern;
  class GroupedPattern;
  class SlicePatternItemsNoRest;
--- 239,250 ----
  class StructPatternElements;
  class StructPattern;
  class TupleStructItems;
! class TupleStructItemsNoRest;
! class TupleStructItemsHasRest;
  class TupleStructPattern;
  class TuplePatternItems;
! class TuplePatternItemsNoRest;
! class TuplePatternItemsHasRest;
  class TuplePattern;
  class GroupedPattern;
  class SlicePatternItemsNoRest;
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-pointer-visitor.cc gcc-16-20251102/gcc/rust/ast/rust-ast-pointer-visitor.cc
*** gcc-16-20251026/gcc/rust/ast/rust-ast-pointer-visitor.cc	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/ast/rust-ast-pointer-visitor.cc	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,1475 ----
+ // Copyright (C) 2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "rust-ast-pointer-visitor.h"
+ #include "rust-ast-visitor.h"
+ #include "rust-ast-full.h"
+ 
+ namespace Rust {
+ namespace AST {
+ 
+ void
+ PointerVisitor::visit (AST::Crate &crate)
+ {
+   visit_inner_attrs (crate);
+   for (auto &item : crate.items)
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AttrInputMetaItemContainer &input)
+ {
+   // FIXME: I think we might actually have to reseat sub-items for macro
+   // invocations within attributes correct?
+ 
+   for (auto &item : input.get_items ())
+     visit (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::IdentifierExpr &ident_expr)
+ {
+   visit_outer_attrs (ident_expr);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LifetimeParam &lifetime_param)
+ {
+   visit_outer_attrs (lifetime_param);
+ 
+   // Nothing to do for lifetimes right?
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ConstGenericParam &const_param)
+ {
+   visit_outer_attrs (const_param);
+   if (const_param.has_type ())
+     reseat (const_param.get_type_ptr ());
+ 
+   if (const_param.has_default_value ())
+     visit (const_param.get_default_value_unchecked ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::PathInExpression &path)
+ {
+   visit_outer_attrs (path);
+ 
+   if (!path.is_lang_item ())
+     for (auto &segment : path.get_segments ())
+       visit (segment);
+ }
+ 
+ void
+ PointerVisitor::visit (GenericArgsBinding &binding)
+ {
+   reseat (binding.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypePathSegmentGeneric &segment)
+ {
+   if (segment.has_generic_args ())
+     visit (segment.get_generic_args ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypePathFunction &tpf)
+ {
+   for (auto &input : tpf.get_params ())
+     reseat (input);
+   if (tpf.has_return_type ())
+     reseat (tpf.get_return_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypePathSegmentFunction &segment)
+ {
+   // FIXME: No reseating here correct? No macros possible or desugar?
+   visit (segment.get_type_path_function ());
+   visit (segment.get_ident_segment ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::GenericArgs &args)
+ {
+   // Nothing to do for lifetimes?
+   // for (auto &lifetime : args.get_lifetime_args ())
+   //   reseat (lifetime);
+ 
+   // FIXME: Actually this can probably be a macro invocation, so we need to
+   // reseat them?
+   for (auto &generic : args.get_generic_args ())
+     visit (generic);
+ 
+   for (auto &binding : args.get_binding_args ())
+     visit (binding);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::PathExprSegment &segment)
+ {
+   visit (segment.get_ident_segment ());
+   if (segment.has_generic_args ())
+     visit (segment.get_generic_args ());
+ }
+ void
+ PointerVisitor::visit (AST::TypePath &path)
+ {
+   for (auto &segment : path.get_segments ())
+     visit (segment);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::QualifiedPathInExpression &path)
+ {
+   visit_outer_attrs (path);
+   visit (path.get_qualified_path_type ());
+ 
+   for (auto &segment : path.get_segments ())
+     visit (segment);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::QualifiedPathType &path)
+ {
+   reseat (path.get_type_ptr ());
+   if (path.has_as_clause ())
+     visit (path.get_as_type_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::QualifiedPathInType &path)
+ {
+   visit (path.get_qualified_path_type ());
+   visit (path.get_associated_segment ());
+ 
+   for (auto &segment : path.get_segments ())
+     visit (segment);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LiteralExpr &expr)
+ {
+   visit_outer_attrs (expr);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AttrInputLiteral &attr_input)
+ {
+   visit (attr_input.get_literal ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AttrInputMacro &attr_input)
+ {
+   visit (attr_input.get_macro ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MetaItemLitExpr &meta_item)
+ {
+   visit (meta_item.get_literal ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::SimplePath &path)
+ {
+   for (auto &segment : path.get_segments ())
+     visit (segment);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MetaItemPathExpr &meta_item)
+ {
+   visit (meta_item.get_path ());
+   reseat (meta_item.get_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::BorrowExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_borrowed_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::DereferenceExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_dereferenced_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ErrorPropagationExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_propagating_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::NegationExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_negated_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ArithmeticOrLogicalExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_left_expr_ptr ());
+   reseat (expr.get_right_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ComparisonExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_left_expr_ptr ());
+   reseat (expr.get_right_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LazyBooleanExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_left_expr_ptr ());
+   reseat (expr.get_right_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypeCastExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_casted_expr_ptr ());
+   reseat (expr.get_type_to_cast_to_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AssignmentExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_left_expr_ptr ());
+   reseat (expr.get_right_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::CompoundAssignmentExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_left_expr_ptr ());
+   reseat (expr.get_right_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::GroupedExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   reseat (expr.get_expr_in_parens_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ArrayElemsValues &elems)
+ {
+   for (auto &value : elems.get_values ())
+     reseat (value);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ArrayElemsCopied &elems)
+ {
+   reseat (elems.get_elem_to_copy_ptr ());
+   reseat (elems.get_num_copies_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ArrayExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   visit (expr.get_array_elems ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ArrayIndexExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_array_expr_ptr ());
+   reseat (expr.get_index_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   for (auto &elem : expr.get_tuple_elems ())
+     reseat (elem);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleIndexExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_tuple_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructExprStruct &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   visit (expr.get_struct_name ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructExprFieldIdentifier &field)
+ {}
+ 
+ void
+ PointerVisitor::visit (AST::StructExprFieldIdentifierValue &field)
+ {
+   reseat (field.get_value_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructExprFieldIndexValue &field)
+ {
+   reseat (field.get_value_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructBase &base)
+ {
+   reseat (base.get_base_struct_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructExprStructFields &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   visit (expr.get_struct_name ());
+   if (expr.has_struct_base ())
+     visit (expr.get_struct_base ());
+   for (auto &field : expr.get_fields ())
+     visit (field);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructExprStructBase &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   visit (expr.get_struct_name ());
+   visit (expr.get_struct_base ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::CallExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_function_expr_ptr ());
+   for (auto &param : expr.get_params ())
+     reseat (param);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MethodCallExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_receiver_expr_ptr ());
+   visit (expr.get_method_name ());
+   for (auto &param : expr.get_params ())
+     reseat (param);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::FieldAccessExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_receiver_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ClosureExprInner &expr)
+ {
+   visit_outer_attrs (expr);
+ 
+   // TODO: Actually we need to handle macro invocations as closure parameters so
+   // this needs to be a reseat
+   for (auto &param : expr.get_params ())
+     visit (param);
+ 
+   reseat (expr.get_definition_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::BlockExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+ 
+   if (expr.has_label ())
+     visit (expr.get_label ());
+ 
+   for (auto &stmt : expr.get_statements ())
+     reseat (stmt);
+ 
+   if (expr.has_tail_expr ())
+     reseat (expr.get_tail_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ConstBlock &expr)
+ {
+   visit (expr.get_const_expr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AnonConst &expr)
+ {
+   if (!expr.is_deferred ())
+     reseat (expr.get_inner_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ClosureExprInnerTyped &expr)
+ {
+   visit_outer_attrs (expr);
+ 
+   // TODO: Same as ClosureExprInner
+   for (auto &param : expr.get_params ())
+     visit (param);
+ 
+   reseat (expr.get_return_type_ptr ());
+ 
+   reseat (expr.get_definition_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ClosureParam &param)
+ {
+   visit_outer_attrs (param);
+   reseat (param.get_pattern_ptr ());
+   if (param.has_type_given ())
+     reseat (param.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ContinueExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   if (expr.has_label ())
+     visit (expr.get_label_unchecked ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::BreakExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   if (expr.has_label ())
+     visit (expr.get_label_unchecked ());
+ 
+   if (expr.has_break_expr ())
+     reseat (expr.get_break_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangeFromToExpr &expr)
+ {
+   reseat (expr.get_from_expr_ptr ());
+   reseat (expr.get_to_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangeFromExpr &expr)
+ {
+   reseat (expr.get_from_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangeToExpr &expr)
+ {
+   reseat (expr.get_to_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangeFullExpr &expr)
+ {}
+ 
+ void
+ PointerVisitor::visit (AST::RangeFromToInclExpr &expr)
+ {
+   reseat (expr.get_from_expr_ptr ());
+   reseat (expr.get_to_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangeToInclExpr &expr)
+ {
+   reseat (expr.get_to_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ReturnExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   if (expr.has_returned_expr ())
+     reseat (expr.get_returned_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TryExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_block_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::BoxExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_boxed_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::UnsafeBlockExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_block_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LoopLabel &label)
+ {
+   visit (label.get_lifetime ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LoopExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   if (expr.has_loop_label ())
+     visit (expr.get_loop_label ());
+   reseat (expr.get_loop_block_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::WhileLoopExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   if (expr.has_loop_label ())
+     visit (expr.get_loop_label ());
+   reseat (expr.get_predicate_expr_ptr ());
+   reseat (expr.get_loop_block_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::WhileLetLoopExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   for (auto &pattern : expr.get_patterns ())
+     reseat (pattern);
+ 
+   if (expr.has_loop_label ())
+     visit (expr.get_loop_label ());
+ 
+   reseat (expr.get_scrutinee_expr_ptr ());
+   reseat (expr.get_loop_block_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ForLoopExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_pattern_ptr ());
+   reseat (expr.get_iterator_expr_ptr ());
+   if (expr.has_loop_label ())
+     visit (expr.get_loop_label ());
+   reseat (expr.get_loop_block_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::IfExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_condition_expr_ptr ());
+   visit (expr.get_if_block ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::IfExprConseqElse &expr)
+ {
+   visit (reinterpret_cast<AST::IfExpr &> (expr));
+   visit (expr.get_else_block ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::IfLetExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   for (auto &pattern : expr.get_patterns ())
+     reseat (pattern);
+   reseat (expr.get_value_expr_ptr ());
+   visit (expr.get_if_block ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::IfLetExprConseqElse &expr)
+ {
+   visit (reinterpret_cast<AST::IfLetExpr &> (expr));
+   visit (expr.get_else_block ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MatchArm &arm)
+ {
+   visit_outer_attrs (arm);
+   for (auto &pattern : arm.get_patterns ())
+     reseat (pattern);
+   if (arm.has_match_arm_guard ())
+     reseat (arm.get_guard_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MatchCase &arm)
+ {
+   visit (arm.get_arm ());
+   reseat (arm.get_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MatchExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   visit_inner_attrs (expr);
+   reseat (expr.get_scrutinee_expr_ptr ());
+   for (auto &arm : expr.get_match_cases ())
+     visit (arm);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AwaitExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_awaited_expr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AsyncBlockExpr &expr)
+ {
+   visit_outer_attrs (expr);
+   reseat (expr.get_block_expr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::InlineAsm &expr)
+ {
+   visit_outer_attrs (expr);
+   using RegisterType = AST::InlineAsmOperand::RegisterType;
+   for (auto &operand : expr.get_operands ())
+     {
+       switch (operand.get_register_type ())
+ 	{
+ 	case RegisterType::In:
+ 	  {
+ 	    reseat (operand.get_in ().expr);
+ 	    break;
+ 	  }
+ 	case RegisterType::Out:
+ 	  {
+ 	    reseat (operand.get_out ().expr);
+ 	    break;
+ 	  }
+ 	case RegisterType::InOut:
+ 	  {
+ 	    reseat (operand.get_in_out ().expr);
+ 	    break;
+ 	  }
+ 	case RegisterType::SplitInOut:
+ 	  {
+ 	    auto split = operand.get_split_in_out ();
+ 	    reseat (split.in_expr);
+ 	    reseat (split.out_expr);
+ 	    break;
+ 	  }
+ 	case RegisterType::Const:
+ 	  {
+ 	    reseat (operand.get_const ().anon_const.get_inner_expr_ptr ());
+ 	    break;
+ 	  }
+ 	case RegisterType::Sym:
+ 	  {
+ 	    reseat (operand.get_sym ().expr);
+ 	    break;
+ 	  }
+ 	case RegisterType::Label:
+ 	  {
+ 	    reseat (operand.get_label ().expr);
+ 	    break;
+ 	  }
+ 	}
+     }
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LlvmInlineAsm &expr)
+ {
+   for (auto &output : expr.get_outputs ())
+     reseat (output.expr);
+ 
+   for (auto &input : expr.get_inputs ())
+     reseat (input.expr);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypeParam &param)
+ {
+   visit_outer_attrs (param);
+   // FIXME: Can we do macro expansion here?
+   for (auto &bound : param.get_type_param_bounds ())
+     visit (bound);
+   if (param.has_type ())
+     reseat (param.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::LifetimeWhereClauseItem &item)
+ {
+   visit (item.get_lifetime ());
+   for (auto &bound : item.get_lifetime_bounds ())
+     visit (bound);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypeBoundWhereClauseItem &item)
+ {
+   for (auto &lifetime : item.get_for_lifetimes ())
+     visit (lifetime);
+   reseat (item.get_type_ptr ());
+   // FIXME: Likewise?
+   for (auto &param : item.get_type_param_bounds ())
+     visit (param);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::Visibility &vis)
+ {
+   if (vis.has_path ())
+     visit (vis.get_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::WhereClause &where)
+ {
+   for (auto &item : where.get_items ())
+     visit (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::FunctionParam &param)
+ {
+   visit_outer_attrs (param);
+   if (param.has_name ())
+     reseat (param.get_pattern_ptr ());
+ 
+   reseat (param.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::SelfParam &param)
+ {
+   visit_outer_attrs (param);
+ 
+   if (param.has_lifetime ())
+     visit (param.get_lifetime ());
+ 
+   if (param.has_type ())
+     reseat (param.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::Module &module)
+ {
+   visit_outer_attrs (module);
+   visit (module.get_visibility ());
+   visit_inner_attrs (module);
+   for (auto &item : module.get_items ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ExternCrate &crate)
+ {
+   visit_outer_attrs (crate);
+   visit (crate.get_visibility ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::UseTreeGlob &use_tree)
+ {
+   visit (use_tree.get_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::UseTreeList &use_tree)
+ {
+   visit (use_tree.get_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::UseTreeRebind &use_tree)
+ {
+   visit (use_tree.get_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::UseDeclaration &use_decl)
+ {
+   visit (use_decl.get_visibility ());
+   visit (use_decl.get_tree ());
+ }
+ 
+ void
+ PointerVisitor::visit_function_params (AST::Function &function)
+ {
+   for (auto &param : function.get_function_params ())
+     visit (param);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::Function &function)
+ {
+   visit_outer_attrs (function);
+   visit (function.get_visibility ());
+   visit (function.get_qualifiers ());
+   for (auto &generic : function.get_generic_params ())
+     visit (generic);
+ 
+   visit_function_params (function);
+ 
+   if (function.has_return_type ())
+     reseat (function.get_return_type_ptr ());
+   if (function.has_where_clause ())
+     visit (function.get_where_clause ());
+   if (function.has_body ())
+     reseat (*function.get_definition ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TypeAlias &type_alias)
+ {
+   visit_outer_attrs (type_alias);
+   visit (type_alias.get_visibility ());
+   for (auto &generic : type_alias.get_generic_params ())
+     visit (generic);
+   if (type_alias.has_where_clause ())
+     visit (type_alias.get_where_clause ());
+   reseat (type_alias.get_type_aliased_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructField &field)
+ {
+   visit_outer_attrs (field);
+   visit (field.get_visibility ());
+   reseat (field.get_field_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructStruct &struct_item)
+ {
+   visit_outer_attrs (struct_item);
+   visit (struct_item.get_visibility ());
+   for (auto &generic : struct_item.get_generic_params ())
+     visit (generic);
+   if (struct_item.has_where_clause ())
+     visit (struct_item.get_where_clause ());
+   for (auto &field : struct_item.get_fields ())
+     visit (field);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleField &field)
+ {
+   visit_outer_attrs (field);
+   visit (field.get_visibility ());
+   reseat (field.get_field_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleStruct &tuple_struct)
+ {
+   visit_outer_attrs (tuple_struct);
+   visit (tuple_struct.get_visibility ());
+   for (auto &generic : tuple_struct.get_generic_params ())
+     visit (generic);
+   if (tuple_struct.has_where_clause ())
+     visit (tuple_struct.get_where_clause ());
+   for (auto &field : tuple_struct.get_fields ())
+     visit (field);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::EnumItem &item)
+ {
+   visit_outer_attrs (item);
+   visit (item.get_visibility ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::EnumItemTuple &item)
+ {
+   PointerVisitor::visit (static_cast<EnumItem &> (item));
+   for (auto &field : item.get_tuple_fields ())
+     visit (field);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::EnumItemStruct &item)
+ {
+   PointerVisitor::visit (static_cast<EnumItem &> (item));
+   for (auto &field : item.get_struct_fields ())
+     visit (field);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::EnumItemDiscriminant &item)
+ {
+   PointerVisitor::visit (static_cast<EnumItem &> (item));
+   reseat (item.get_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::Enum &enum_item)
+ {
+   visit_outer_attrs (enum_item);
+   visit (enum_item.get_visibility ());
+   for (auto &generic : enum_item.get_generic_params ())
+     visit (generic);
+   if (enum_item.has_where_clause ())
+     visit (enum_item.get_where_clause ());
+   for (auto &item : enum_item.get_variants ())
+     visit (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::Union &union_item)
+ {
+   visit_outer_attrs (union_item);
+   visit (union_item.get_visibility ());
+   for (auto &generic : union_item.get_generic_params ())
+     visit (generic);
+   if (union_item.has_where_clause ())
+     visit (union_item.get_where_clause ());
+   for (auto &variant : union_item.get_variants ())
+     visit (variant);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ConstantItem &const_item)
+ {
+   visit_outer_attrs (const_item);
+   visit (const_item.get_visibility ());
+   reseat (const_item.get_type_ptr ());
+   if (const_item.has_expr ())
+     reseat (const_item.get_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StaticItem &static_item)
+ {
+   visit_outer_attrs (static_item);
+   visit (static_item.get_visibility ());
+   reseat (static_item.get_type_ptr ());
+   reseat (static_item.get_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TraitItemType &item)
+ {
+   visit_outer_attrs (item);
+   for (auto &bound : item.get_type_param_bounds ())
+     visit (bound);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::Trait &trait)
+ {
+   visit_outer_attrs (trait);
+   visit (trait.get_visibility ());
+ 
+   visit_inner_attrs (trait);
+ 
+   visit (trait.get_implicit_self ());
+ 
+   for (auto &generic : trait.get_generic_params ())
+     visit (generic);
+ 
+   if (trait.has_where_clause ())
+     visit (trait.get_where_clause ());
+ 
+   for (auto &bound : trait.get_type_param_bounds ())
+     visit (bound);
+ 
+   for (auto &item : trait.get_trait_items ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::InherentImpl &impl)
+ {
+   visit_outer_attrs (impl);
+   visit (impl.get_visibility ());
+ 
+   for (auto &generic : impl.get_generic_params ())
+     visit (generic);
+   if (impl.has_where_clause ())
+     visit (impl.get_where_clause ());
+   reseat (impl.get_type_ptr ());
+   visit_inner_attrs (impl);
+   for (auto &item : impl.get_impl_items ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TraitImpl &impl)
+ {
+   visit_outer_attrs (impl);
+   visit (impl.get_visibility ());
+ 
+   for (auto &generic : impl.get_generic_params ())
+     visit (generic);
+   if (impl.has_where_clause ())
+     visit (impl.get_where_clause ());
+   reseat (impl.get_type_ptr ());
+   visit (impl.get_trait_path ());
+   visit_inner_attrs (impl);
+   for (auto &item : impl.get_impl_items ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ExternalTypeItem &item)
+ {
+   visit_outer_attrs (item);
+   visit (item.get_visibility ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ExternalStaticItem &item)
+ {
+   visit_outer_attrs (item);
+   visit (item.get_visibility ());
+   reseat (item.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ExternBlock &block)
+ {
+   visit_outer_attrs (block);
+   visit (block.get_visibility ());
+   visit_inner_attrs (block);
+   for (auto &item : block.get_extern_items ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroMatchFragment &match)
+ {}
+ 
+ void
+ PointerVisitor::visit (AST::MacroMatchRepetition &match)
+ {
+   for (auto &m : match.get_matches ())
+     visit (m);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroMatcher &matcher)
+ {
+   for (auto &m : matcher.get_matches ())
+     visit (m);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroTranscriber &transcriber)
+ {
+   visit (transcriber.get_token_tree ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroRule &rule)
+ {
+   visit (rule.get_matcher ());
+   visit (rule.get_transcriber ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroRulesDefinition &rules_def)
+ {
+   visit_outer_attrs (rules_def);
+   for (auto &rule : rules_def.get_macro_rules ())
+     visit (rule);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroInvocData &data)
+ {
+   visit (data.get_path ());
+   visit (data.get_delim_tok_tree ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MacroInvocation &macro_invoc)
+ {
+   visit_outer_attrs (macro_invoc);
+   visit (macro_invoc.get_invoc_data ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MetaItemPath &meta_item)
+ {
+   visit (meta_item.get_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MetaItemSeq &meta_item)
+ {
+   visit (meta_item.get_path ());
+   for (auto &inner : meta_item.get_seq ())
+     visit (inner);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MetaListPaths &meta_item)
+ {
+   for (auto &path : meta_item.get_paths ())
+     visit (path);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::MetaListNameValueStr &meta_item)
+ {
+   for (auto &str : meta_item.get_values ())
+     visit (str);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::IdentifierPattern &pattern)
+ {
+   if (pattern.has_subpattern ())
+     reseat (pattern.get_subpattern_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangePatternBoundPath &bound)
+ {
+   visit (bound.get_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangePatternBoundQualPath &bound)
+ {
+   visit (bound.get_qualified_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::RangePattern &pattern)
+ {
+   // FIXME: So should this be reseat() instead? Can we have macro invocations as
+   // patterns in range patterns?
+   if (pattern.get_has_lower_bound ())
+     visit (pattern.get_lower_bound ());
+   if (pattern.get_has_upper_bound ())
+     visit (pattern.get_upper_bound ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ReferencePattern &pattern)
+ {
+   reseat (pattern.get_referenced_pattern_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructPatternFieldTuplePat &field)
+ {
+   visit_outer_attrs (field);
+   reseat (field.get_index_pattern_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructPatternFieldIdentPat &field)
+ {
+   visit_outer_attrs (field);
+   reseat (field.get_ident_pattern_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructPatternFieldIdent &field)
+ {
+   visit_outer_attrs (field);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructPatternElements &spe)
+ {
+   for (auto &field : spe.get_struct_pattern_fields ())
+     visit (field);
+   for (auto &attribute : spe.get_etc_outer_attrs ())
+     visit (attribute);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::StructPattern &pattern)
+ {
+   visit (pattern.get_path ());
+   visit (pattern.get_struct_pattern_elems ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleStructItemsNoRest &tuple_items)
+ {
+   for (auto &pattern : tuple_items.get_patterns ())
+     reseat (pattern);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleStructItemsHasRest &tuple_items)
+ {
+   for (auto &lower : tuple_items.get_lower_patterns ())
+     reseat (lower);
+   for (auto &upper : tuple_items.get_upper_patterns ())
+     reseat (upper);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleStructPattern &pattern)
+ {
+   visit (pattern.get_path ());
+   visit (pattern.get_items ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TuplePatternItemsNoRest &tuple_items)
+ {
+   for (auto &pattern : tuple_items.get_patterns ())
+     reseat (pattern);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TuplePatternItemsHasRest &tuple_items)
+ {
+   for (auto &lower : tuple_items.get_lower_patterns ())
+     reseat (lower);
+   for (auto &upper : tuple_items.get_upper_patterns ())
+     reseat (upper);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TuplePattern &pattern)
+ {
+   visit (pattern.get_items ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::GroupedPattern &pattern)
+ {
+   reseat (pattern.get_pattern_in_parens_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::SlicePatternItemsNoRest &items)
+ {
+   for (auto &item : items.get_patterns ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::SlicePatternItemsHasRest &items)
+ {
+   for (auto &item : items.get_lower_patterns ())
+     reseat (item);
+   for (auto &item : items.get_upper_patterns ())
+     reseat (item);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::SlicePattern &pattern)
+ {
+   visit (pattern.get_items ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::AltPattern &pattern)
+ {
+   for (auto &alt : pattern.get_alts ())
+     reseat (alt);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::EmptyStmt &stmt)
+ {}
+ 
+ void
+ PointerVisitor::visit (AST::LetStmt &stmt)
+ {
+   visit_outer_attrs (stmt);
+   reseat (stmt.get_pattern_ptr ());
+   if (stmt.has_type ())
+     reseat (stmt.get_type_ptr ());
+   if (stmt.has_init_expr ())
+     reseat (stmt.get_init_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ExprStmt &stmt)
+ {
+   reseat (stmt.get_expr_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TraitBound &bound)
+ {
+   for (auto &lifetime : bound.get_for_lifetimes ())
+     visit (lifetime);
+   visit (bound.get_type_path ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ImplTraitType &type)
+ {
+   for (auto &bound : type.get_type_param_bounds ())
+     visit (bound);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TraitObjectType &type)
+ {
+   for (auto &bound : type.get_type_param_bounds ())
+     visit (bound);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ParenthesisedType &type)
+ {
+   reseat (type.get_type_in_parens ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ImplTraitTypeOneBound &type)
+ {
+   // FIXME: Do we need to reseat here?
+   visit (type.get_trait_bound ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TraitObjectTypeOneBound &type)
+ {
+   // FIXME: Do we need to reseat here?
+   visit (type.get_trait_bound ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::TupleType &type)
+ {
+   for (auto &elem : type.get_elems ())
+     reseat (elem);
+ }
+ 
+ void
+ PointerVisitor::visit (AST::NeverType &type)
+ {}
+ 
+ void
+ PointerVisitor::visit (AST::RawPointerType &type)
+ {
+   reseat (type.get_type_pointed_to_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ReferenceType &type)
+ {
+   visit (type.get_lifetime ());
+   reseat (type.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::ArrayType &type)
+ {
+   reseat (type.get_elem_type_ptr ());
+   visit (type.get_size_expr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::SliceType &type)
+ {
+   reseat (type.get_elem_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::InferredType &type)
+ {}
+ 
+ void
+ PointerVisitor::visit (AST::MaybeNamedParam &param)
+ {
+   visit_outer_attrs (param);
+   reseat (param.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::BareFunctionType &type)
+ {
+   for (auto &lifetime : type.get_for_lifetimes ())
+     visit (lifetime);
+   visit (type.get_function_qualifiers ());
+   for (auto &param : type.get_function_params ())
+     visit (param);
+   if (type.is_variadic ())
+     for (auto attr : type.get_variadic_attr ())
+       visit (attr);
+   if (type.has_return_type ())
+     reseat (type.get_return_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::FormatArgs &)
+ {
+   // FIXME: Do we have anything to do? any subnodes to visit? Probably, right?
+ }
+ 
+ void
+ PointerVisitor::visit (AST::OffsetOf &offset_of)
+ {
+   reseat (offset_of.get_type_ptr ());
+ }
+ 
+ void
+ PointerVisitor::visit (AST::VariadicParam &param)
+ {
+   if (param.has_pattern ())
+     reseat (param.get_pattern_ptr ());
+ }
+ 
+ } // namespace AST
+ } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-pointer-visitor.h gcc-16-20251102/gcc/rust/ast/rust-ast-pointer-visitor.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast-pointer-visitor.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/ast/rust-ast-pointer-visitor.h	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,234 ----
+ // Copyright (C) 2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #ifndef RUST_AST_POINTER_VISITOR_H
+ #define RUST_AST_POINTER_VISITOR_H
+ 
+ #include "rust-ast-visitor.h"
+ #include "rust-ast.h"
+ #include "rust-item.h"
+ 
+ namespace Rust {
+ namespace AST {
+ 
+ /**
+  * Regular AST visitor which may reseat pointers when necessary.
+  */
+ class PointerVisitor : public DefaultASTVisitor
+ {
+ public:
+   using DefaultASTVisitor::visit;
+ 
+   virtual void reseat (std::unique_ptr<AST::Expr> &ptr) { visit (ptr); }
+   virtual void reseat (std::unique_ptr<AST::BlockExpr> &ptr) { visit (ptr); }
+ 
+   virtual void reseat (std::unique_ptr<AST::Stmt> &ptr) { visit (ptr); }
+ 
+   virtual void reseat (std::unique_ptr<AST::Item> &ptr) { visit (ptr); }
+ 
+   virtual void reseat (std::unique_ptr<AST::AssociatedItem> &ptr)
+   {
+     visit (ptr);
+   }
+ 
+   virtual void reseat (std::unique_ptr<AST::ExternalItem> &ptr) { visit (ptr); }
+ 
+   virtual void reseat (std::unique_ptr<AST::Type> &ptr) { visit (ptr); }
+ 
+   virtual void reseat (std::unique_ptr<AST::TypeNoBounds> &ptr) { visit (ptr); }
+ 
+   virtual void reseat (std::unique_ptr<AST::Pattern> &ptr) { visit (ptr); }
+ 
+   void visit (AST::Crate &crate) override;
+   void visit (AST::AttrInputMetaItemContainer &input) override;
+   void visit (AST::IdentifierExpr &ident_expr) override;
+   void visit (AST::LifetimeParam &lifetime_param) override;
+   void visit (AST::ConstGenericParam &const_param) override;
+   void visit (AST::PathInExpression &path) override;
+   void visit (GenericArgsBinding &binding) override;
+   void visit (AST::TypePathSegmentGeneric &segment) override;
+   void visit (AST::TypePathFunction &tpf) override;
+   void visit (AST::TypePathSegmentFunction &segment) override;
+   void visit (AST::GenericArgs &args) override;
+   void visit (AST::PathExprSegment &segment) override;
+   void visit (AST::TypePath &path) override;
+   void visit (AST::QualifiedPathInExpression &path) override;
+   void visit (AST::QualifiedPathType &path) override;
+   void visit (AST::QualifiedPathInType &path) override;
+   void visit (AST::LiteralExpr &expr) override;
+   void visit (AST::AttrInputLiteral &attr_input) override;
+   void visit (AST::AttrInputMacro &attr_input) override;
+   void visit (AST::MetaItemLitExpr &meta_item) override;
+   void visit (AST::SimplePath &path) override;
+   void visit (AST::MetaItemPathExpr &meta_item) override;
+   void visit (AST::BorrowExpr &expr) override;
+   void visit (AST::DereferenceExpr &expr) override;
+   void visit (AST::ErrorPropagationExpr &expr) override;
+   void visit (AST::NegationExpr &expr) override;
+   void visit (AST::ArithmeticOrLogicalExpr &expr) override;
+   void visit (AST::ComparisonExpr &expr) override;
+   void visit (AST::LazyBooleanExpr &expr) override;
+   void visit (AST::TypeCastExpr &expr) override;
+   void visit (AST::AssignmentExpr &expr) override;
+   void visit (AST::CompoundAssignmentExpr &expr) override;
+   void visit (AST::GroupedExpr &expr) override;
+   void visit (AST::ArrayElemsValues &elems) override;
+   void visit (AST::ArrayElemsCopied &elems) override;
+   void visit (AST::ArrayExpr &expr) override;
+   void visit (AST::ArrayIndexExpr &expr) override;
+   void visit (AST::TupleExpr &expr) override;
+   void visit (AST::TupleIndexExpr &expr) override;
+   void visit (AST::StructExprStruct &expr) override;
+   void visit (AST::StructExprFieldIdentifier &field) override;
+   void visit (AST::StructExprFieldIdentifierValue &field) override;
+   void visit (AST::StructExprFieldIndexValue &field) override;
+   void visit (AST::StructBase &base) override;
+   void visit (AST::StructExprStructFields &expr) override;
+   void visit (AST::StructExprStructBase &expr) override;
+   void visit (AST::CallExpr &expr) override;
+   void visit (AST::MethodCallExpr &expr) override;
+   void visit (AST::FieldAccessExpr &expr) override;
+   void visit (AST::ClosureExprInner &expr) override;
+   void visit (AST::BlockExpr &expr) override;
+   void visit (AST::ConstBlock &expr) override;
+   void visit (AST::AnonConst &expr) override;
+   void visit (AST::ClosureExprInnerTyped &expr) override;
+   void visit (AST::ClosureParam &param) override;
+   void visit (AST::ContinueExpr &expr) override;
+   void visit (AST::BreakExpr &expr) override;
+   void visit (AST::RangeFromToExpr &expr) override;
+   void visit (AST::RangeFromExpr &expr) override;
+   void visit (AST::RangeToExpr &expr) override;
+   void visit (AST::RangeFullExpr &expr) override;
+   void visit (AST::RangeFromToInclExpr &expr) override;
+   void visit (AST::RangeToInclExpr &expr) override;
+   void visit (AST::ReturnExpr &expr) override;
+   void visit (AST::TryExpr &expr) override;
+   void visit (AST::BoxExpr &expr) override;
+   void visit (AST::UnsafeBlockExpr &expr) override;
+   void visit (AST::LoopLabel &label) override;
+   void visit (AST::LoopExpr &expr) override;
+   void visit (AST::WhileLoopExpr &expr) override;
+   void visit (AST::WhileLetLoopExpr &expr) override;
+   void visit (AST::ForLoopExpr &expr) override;
+   void visit (AST::IfExpr &expr) override;
+   void visit (AST::IfExprConseqElse &expr) override;
+   void visit (AST::IfLetExpr &expr) override;
+   void visit (AST::IfLetExprConseqElse &expr) override;
+   void visit (AST::MatchArm &arm) override;
+   void visit (AST::MatchCase &arm) override;
+   void visit (AST::MatchExpr &expr) override;
+   void visit (AST::AwaitExpr &expr) override;
+   void visit (AST::AsyncBlockExpr &expr) override;
+   void visit (AST::InlineAsm &expr) override;
+   void visit (AST::LlvmInlineAsm &expr) override;
+   void visit (AST::TypeParam &param) override;
+   void visit (AST::LifetimeWhereClauseItem &item) override;
+   void visit (AST::TypeBoundWhereClauseItem &item) override;
+   void visit (AST::Visibility &vis) override;
+   void visit (AST::WhereClause &where) override;
+   void visit (AST::FunctionParam &param) override;
+   void visit (AST::SelfParam &param) override;
+   void visit (AST::Module &module) override;
+   void visit (AST::ExternCrate &crate) override;
+   void visit (AST::UseTreeGlob &use_tree) override;
+   void visit (AST::UseTreeList &use_tree) override;
+   void visit (AST::UseTreeRebind &use_tree) override;
+   void visit (AST::UseDeclaration &use_decl) override;
+   void visit_function_params (AST::Function &function) override;
+   void visit (AST::Function &function) override;
+   void visit (AST::TypeAlias &type_alias) override;
+   void visit (AST::StructField &field) override;
+   void visit (AST::StructStruct &struct_item) override;
+   void visit (AST::TupleField &field) override;
+   void visit (AST::TupleStruct &tuple_struct) override;
+   void visit (AST::EnumItem &item) override;
+   void visit (AST::EnumItemTuple &item) override;
+   void visit (AST::EnumItemStruct &item) override;
+   void visit (AST::EnumItemDiscriminant &item) override;
+   void visit (AST::Enum &enum_item) override;
+   void visit (AST::Union &union_item) override;
+   void visit (AST::ConstantItem &const_item) override;
+   void visit (AST::StaticItem &static_item) override;
+   void visit (AST::TraitItemType &item) override;
+   void visit (AST::Trait &trait) override;
+   void visit (AST::InherentImpl &impl) override;
+   void visit (AST::TraitImpl &impl) override;
+   void visit (AST::ExternalTypeItem &item) override;
+   void visit (AST::ExternalStaticItem &item) override;
+   void visit (AST::ExternBlock &block) override;
+   void visit (AST::MacroMatchFragment &match) override;
+   void visit (AST::MacroMatchRepetition &match) override;
+   void visit (AST::MacroMatcher &matcher) override;
+   void visit (AST::MacroTranscriber &transcriber) override;
+   void visit (AST::MacroRule &rule) override;
+   void visit (AST::MacroRulesDefinition &rules_def) override;
+   void visit (AST::MacroInvocData &data) override;
+   void visit (AST::MacroInvocation &macro_invoc) override;
+   void visit (AST::MetaItemPath &meta_item) override;
+   void visit (AST::MetaItemSeq &meta_item) override;
+   void visit (AST::MetaListPaths &meta_item) override;
+   void visit (AST::MetaListNameValueStr &meta_item) override;
+   void visit (AST::IdentifierPattern &pattern) override;
+   void visit (AST::RangePatternBoundPath &bound) override;
+   void visit (AST::RangePatternBoundQualPath &bound) override;
+   void visit (AST::RangePattern &pattern) override;
+   void visit (AST::ReferencePattern &pattern) override;
+   void visit (AST::StructPatternFieldTuplePat &field) override;
+   void visit (AST::StructPatternFieldIdentPat &field) override;
+   void visit (AST::StructPatternFieldIdent &field) override;
+   void visit (AST::StructPatternElements &spe) override;
+   void visit (AST::StructPattern &pattern) override;
+   void visit (AST::TupleStructItemsNoRest &tuple_items) override;
+   void visit (AST::TupleStructItemsHasRest &tuple_items) override;
+   void visit (AST::TupleStructPattern &pattern) override;
+   void visit (AST::TuplePatternItemsNoRest &tuple_items) override;
+   void visit (AST::TuplePatternItemsHasRest &tuple_items) override;
+   void visit (AST::TuplePattern &pattern) override;
+   void visit (AST::GroupedPattern &pattern) override;
+   void visit (AST::SlicePatternItemsNoRest &items) override;
+   void visit (AST::SlicePatternItemsHasRest &items) override;
+   void visit (AST::SlicePattern &pattern) override;
+   void visit (AST::AltPattern &pattern) override;
+   void visit (AST::EmptyStmt &stmt) override;
+   void visit (AST::LetStmt &stmt) override;
+   void visit (AST::ExprStmt &stmt) override;
+   void visit (AST::TraitBound &bound) override;
+   void visit (AST::ImplTraitType &type) override;
+   void visit (AST::TraitObjectType &type) override;
+   void visit (AST::ParenthesisedType &type) override;
+   void visit (AST::ImplTraitTypeOneBound &type) override;
+   void visit (AST::TraitObjectTypeOneBound &type) override;
+   void visit (AST::TupleType &type) override;
+   void visit (AST::NeverType &type) override;
+   void visit (AST::RawPointerType &type) override;
+   void visit (AST::ReferenceType &type) override;
+   void visit (AST::ArrayType &type) override;
+   void visit (AST::SliceType &type) override;
+   void visit (AST::InferredType &type) override;
+   void visit (AST::MaybeNamedParam &param) override;
+   void visit (AST::BareFunctionType &type) override;
+   void visit (AST::FormatArgs &) override;
+   void visit (AST::OffsetOf &offset_of) override;
+   void visit (AST::VariadicParam &param) override;
+ };
+ 
+ } // namespace AST
+ } // namespace Rust
+ 
+ #endif
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-visitor.cc gcc-16-20251102/gcc/rust/ast/rust-ast-visitor.cc
*** gcc-16-20251026/gcc/rust/ast/rust-ast-visitor.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-visitor.cc	Sun Nov  2 22:32:23 2025
*************** void
*** 248,253 ****
--- 248,254 ----
  DefaultASTVisitor::visit (AST::ErrorPropagationExpr &expr)
  {
    visit_outer_attrs (expr);
+   visit (expr.get_propagating_expr ());
  }
  
  void
*************** DefaultASTVisitor::visit (AST::StaticIte
*** 1025,1039 ****
  }
  
  void
- DefaultASTVisitor::visit (AST::TraitItemConst &item)
- {
-   visit_outer_attrs (item);
-   visit (item.get_type ());
-   if (item.has_expr ())
-     visit (item.get_expr ());
- }
- 
- void
  DefaultASTVisitor::visit (AST::TraitItemType &item)
  {
    visit_outer_attrs (item);
--- 1026,1031 ----
*************** DefaultASTVisitor::visit (AST::StructPat
*** 1296,1309 ****
  }
  
  void
! DefaultASTVisitor::visit (AST::TupleStructItemsNoRange &tuple_items)
  {
    for (auto &pattern : tuple_items.get_patterns ())
      visit (pattern);
  }
  
  void
! DefaultASTVisitor::visit (AST::TupleStructItemsRange &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      visit (lower);
--- 1288,1301 ----
  }
  
  void
! DefaultASTVisitor::visit (AST::TupleStructItemsNoRest &tuple_items)
  {
    for (auto &pattern : tuple_items.get_patterns ())
      visit (pattern);
  }
  
  void
! DefaultASTVisitor::visit (AST::TupleStructItemsHasRest &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      visit (lower);
*************** DefaultASTVisitor::visit (AST::TupleStru
*** 1319,1332 ****
  }
  
  void
! DefaultASTVisitor::visit (AST::TuplePatternItemsMultiple &tuple_items)
  {
    for (auto &pattern : tuple_items.get_patterns ())
      visit (pattern);
  }
  
  void
! DefaultASTVisitor::visit (AST::TuplePatternItemsRanged &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      visit (lower);
--- 1311,1324 ----
  }
  
  void
! DefaultASTVisitor::visit (AST::TuplePatternItemsNoRest &tuple_items)
  {
    for (auto &pattern : tuple_items.get_patterns ())
      visit (pattern);
  }
  
  void
! DefaultASTVisitor::visit (AST::TuplePatternItemsHasRest &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      visit (lower);
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast-visitor.h gcc-16-20251102/gcc/rust/ast/rust-ast-visitor.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast-visitor.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast-visitor.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 164,170 ****
    virtual void visit (Union &union_item) = 0;
    virtual void visit (ConstantItem &const_item) = 0;
    virtual void visit (StaticItem &static_item) = 0;
-   virtual void visit (TraitItemConst &item) = 0;
    virtual void visit (TraitItemType &item) = 0;
    virtual void visit (Trait &trait) = 0;
    virtual void visit (InherentImpl &impl) = 0;
--- 164,169 ----
*************** public:
*** 204,215 ****
    virtual void visit (StructPatternFieldIdent &field) = 0;
    virtual void visit (StructPattern &pattern) = 0;
    // virtual void visit(TupleStructItems& tuple_items) = 0;
!   virtual void visit (TupleStructItemsNoRange &tuple_items) = 0;
!   virtual void visit (TupleStructItemsRange &tuple_items) = 0;
    virtual void visit (TupleStructPattern &pattern) = 0;
    // virtual void visit(TuplePatternItems& tuple_items) = 0;
!   virtual void visit (TuplePatternItemsMultiple &tuple_items) = 0;
!   virtual void visit (TuplePatternItemsRanged &tuple_items) = 0;
    virtual void visit (TuplePattern &pattern) = 0;
    virtual void visit (GroupedPattern &pattern) = 0;
    virtual void visit (SlicePatternItemsNoRest &items) = 0;
--- 203,214 ----
    virtual void visit (StructPatternFieldIdent &field) = 0;
    virtual void visit (StructPattern &pattern) = 0;
    // virtual void visit(TupleStructItems& tuple_items) = 0;
!   virtual void visit (TupleStructItemsNoRest &tuple_items) = 0;
!   virtual void visit (TupleStructItemsHasRest &tuple_items) = 0;
    virtual void visit (TupleStructPattern &pattern) = 0;
    // virtual void visit(TuplePatternItems& tuple_items) = 0;
!   virtual void visit (TuplePatternItemsNoRest &tuple_items) = 0;
!   virtual void visit (TuplePatternItemsHasRest &tuple_items) = 0;
    virtual void visit (TuplePattern &pattern) = 0;
    virtual void visit (GroupedPattern &pattern) = 0;
    virtual void visit (SlicePatternItemsNoRest &items) = 0;
*************** public:
*** 349,355 ****
    virtual void visit (AST::Union &union_item) override;
    virtual void visit (AST::ConstantItem &const_item) override;
    virtual void visit (AST::StaticItem &static_item) override;
-   virtual void visit (AST::TraitItemConst &item) override;
    virtual void visit (AST::TraitItemType &item) override;
    virtual void visit (AST::Trait &trait) override;
    virtual void visit (AST::InherentImpl &impl) override;
--- 348,353 ----
*************** public:
*** 381,391 ****
    virtual void visit (AST::StructPatternFieldIdentPat &field) override;
    virtual void visit (AST::StructPatternFieldIdent &field) override;
    virtual void visit (AST::StructPattern &pattern) override;
!   virtual void visit (AST::TupleStructItemsNoRange &tuple_items) override;
!   virtual void visit (AST::TupleStructItemsRange &tuple_items) override;
    virtual void visit (AST::TupleStructPattern &pattern) override;
!   virtual void visit (AST::TuplePatternItemsMultiple &tuple_items) override;
!   virtual void visit (AST::TuplePatternItemsRanged &tuple_items) override;
    virtual void visit (AST::TuplePattern &pattern) override;
    virtual void visit (AST::GroupedPattern &pattern) override;
    virtual void visit (AST::SlicePatternItemsNoRest &items) override;
--- 379,389 ----
    virtual void visit (AST::StructPatternFieldIdentPat &field) override;
    virtual void visit (AST::StructPatternFieldIdent &field) override;
    virtual void visit (AST::StructPattern &pattern) override;
!   virtual void visit (AST::TupleStructItemsNoRest &tuple_items) override;
!   virtual void visit (AST::TupleStructItemsHasRest &tuple_items) override;
    virtual void visit (AST::TupleStructPattern &pattern) override;
!   virtual void visit (AST::TuplePatternItemsNoRest &tuple_items) override;
!   virtual void visit (AST::TuplePatternItemsHasRest &tuple_items) override;
    virtual void visit (AST::TuplePattern &pattern) override;
    virtual void visit (AST::GroupedPattern &pattern) override;
    virtual void visit (AST::SlicePatternItemsNoRest &items) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast.cc gcc-16-20251102/gcc/rust/ast/rust-ast.cc
*** gcc-16-20251026/gcc/rust/ast/rust-ast.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast.cc	Sun Nov  2 22:32:23 2025
*************** SingleASTNode::SingleASTNode (SingleASTN
*** 48,76 ****
    kind = other.kind;
    switch (kind)
      {
!     case EXPRESSION:
        expr = other.expr->clone_expr ();
        break;
  
!     case ITEM:
        item = other.item->clone_item ();
        break;
  
!     case STMT:
        stmt = other.stmt->clone_stmt ();
        break;
  
!     case EXTERN:
        external_item = other.external_item->clone_external_item ();
        break;
  
!     case ASSOC_ITEM:
        assoc_item = other.assoc_item->clone_associated_item ();
        break;
  
!     case TYPE:
        type = other.type->clone_type ();
        break;
      }
  }
  
--- 48,80 ----
    kind = other.kind;
    switch (kind)
      {
!     case Kind::Expr:
        expr = other.expr->clone_expr ();
        break;
  
!     case Kind::Item:
        item = other.item->clone_item ();
        break;
  
!     case Kind::Stmt:
        stmt = other.stmt->clone_stmt ();
        break;
  
!     case Kind::Extern:
        external_item = other.external_item->clone_external_item ();
        break;
  
!     case Kind::Assoc:
        assoc_item = other.assoc_item->clone_associated_item ();
        break;
  
!     case Kind::Type:
        type = other.type->clone_type ();
        break;
+ 
+     case Kind::Pattern:
+       pattern = other.pattern->clone_pattern ();
+       break;
      }
  }
  
*************** SingleASTNode::operator= (SingleASTNode
*** 80,108 ****
    kind = other.kind;
    switch (kind)
      {
!     case EXPRESSION:
        expr = other.expr->clone_expr ();
        break;
  
!     case ITEM:
        item = other.item->clone_item ();
        break;
  
!     case STMT:
        stmt = other.stmt->clone_stmt ();
        break;
  
!     case EXTERN:
        external_item = other.external_item->clone_external_item ();
        break;
  
!     case ASSOC_ITEM:
        assoc_item = other.assoc_item->clone_associated_item ();
        break;
  
!     case TYPE:
        type = other.type->clone_type ();
        break;
      }
    return *this;
  }
--- 84,116 ----
    kind = other.kind;
    switch (kind)
      {
!     case Kind::Expr:
        expr = other.expr->clone_expr ();
        break;
  
!     case Kind::Item:
        item = other.item->clone_item ();
        break;
  
!     case Kind::Stmt:
        stmt = other.stmt->clone_stmt ();
        break;
  
!     case Kind::Extern:
        external_item = other.external_item->clone_external_item ();
        break;
  
!     case Kind::Assoc:
        assoc_item = other.assoc_item->clone_associated_item ();
        break;
  
!     case Kind::Type:
        type = other.type->clone_type ();
        break;
+ 
+     case Kind::Pattern:
+       pattern = other.pattern->clone_pattern ();
+       break;
      }
    return *this;
  }
*************** SingleASTNode::accept_vis (ASTVisitor &v
*** 112,140 ****
  {
    switch (kind)
      {
!     case EXPRESSION:
        expr->accept_vis (vis);
        break;
  
!     case ITEM:
        item->accept_vis (vis);
        break;
  
!     case STMT:
        stmt->accept_vis (vis);
        break;
  
!     case EXTERN:
        external_item->accept_vis (vis);
        break;
  
!     case ASSOC_ITEM:
        assoc_item->accept_vis (vis);
        break;
  
!     case TYPE:
        type->accept_vis (vis);
        break;
      }
  }
  
--- 120,152 ----
  {
    switch (kind)
      {
!     case Kind::Expr:
        expr->accept_vis (vis);
        break;
  
!     case Kind::Item:
        item->accept_vis (vis);
        break;
  
!     case Kind::Stmt:
        stmt->accept_vis (vis);
        break;
  
!     case Kind::Extern:
        external_item->accept_vis (vis);
        break;
  
!     case Kind::Assoc:
        assoc_item->accept_vis (vis);
        break;
  
!     case Kind::Type:
        type->accept_vis (vis);
        break;
+ 
+     case Kind::Pattern:
+       pattern->accept_vis (vis);
+       break;
      }
  }
  
*************** SingleASTNode::is_error ()
*** 143,160 ****
  {
    switch (kind)
      {
!     case EXPRESSION:
        return expr == nullptr;
!     case ITEM:
        return item == nullptr;
!     case STMT:
        return stmt == nullptr;
!     case EXTERN:
        return external_item == nullptr;
!     case ASSOC_ITEM:
        return assoc_item == nullptr;
!     case TYPE:
        return type == nullptr;
      }
  
    rust_unreachable ();
--- 155,174 ----
  {
    switch (kind)
      {
!     case Kind::Expr:
        return expr == nullptr;
!     case Kind::Item:
        return item == nullptr;
!     case Kind::Stmt:
        return stmt == nullptr;
!     case Kind::Extern:
        return external_item == nullptr;
!     case Kind::Assoc:
        return assoc_item == nullptr;
!     case Kind::Type:
        return type == nullptr;
+     case Kind::Pattern:
+       return pattern == nullptr;
      }
  
    rust_unreachable ();
*************** SingleASTNode::as_string () const
*** 166,183 ****
  {
    switch (kind)
      {
!     case EXPRESSION:
        return "Expr: " + expr->as_string ();
!     case ITEM:
        return "Item: " + item->as_string ();
!     case STMT:
        return "Stmt: " + stmt->as_string ();
!     case EXTERN:
        return "External Item: " + external_item->as_string ();
!     case ASSOC_ITEM:
        return "Associated Item: " + assoc_item->as_string ();
!     case TYPE:
        return "Type: " + type->as_string ();
      }
  
    rust_unreachable ();
--- 180,199 ----
  {
    switch (kind)
      {
!     case Kind::Expr:
        return "Expr: " + expr->as_string ();
!     case Kind::Item:
        return "Item: " + item->as_string ();
!     case Kind::Stmt:
        return "Stmt: " + stmt->as_string ();
!     case Kind::Extern:
        return "External Item: " + external_item->as_string ();
!     case Kind::Assoc:
        return "Associated Item: " + assoc_item->as_string ();
!     case Kind::Type:
        return "Type: " + type->as_string ();
+     case Kind::Pattern:
+       return "Pattern: " + pattern->as_string ();
      }
  
    rust_unreachable ();
*************** Attribute::as_string () const
*** 232,238 ****
  bool
  Attribute::is_derive () const
  {
!   return has_attr_input () && get_path () == "derive";
  }
  
  /**
--- 248,254 ----
  bool
  Attribute::is_derive () const
  {
!   return has_attr_input () && get_path () == Values::Attributes::DERIVE;
  }
  
  /**
*************** DelimTokenTree::as_string () const
*** 389,395 ****
  std::string
  Token::as_string () const
  {
!   if (tok_ref->has_str ())
      {
        std::string str = tok_ref->get_str ();
  
--- 405,411 ----
  std::string
  Token::as_string () const
  {
!   if (tok_ref->should_have_str ())
      {
        std::string str = tok_ref->get_str ();
  
*************** ConstantItem::as_string () const
*** 636,649 ****
      }
    str += "\n  Type: " + type->as_string ();
  
!   // DEBUG: null pointer check
!   if (const_expr == nullptr)
!     {
!       rust_debug ("something really terrible has gone wrong - null "
! 		  "pointer expr in const item.");
!       return "NULL_POINTER_MARK";
!     }
!   str += "\n  Expression: " + const_expr->as_string ();
  
    return str + "\n";
  }
--- 652,659 ----
      }
    str += "\n  Type: " + type->as_string ();
  
!   if (has_expr ())
!     str += "\n  Expression: " + const_expr->as_string ();
  
    return str + "\n";
  }
*************** ExternalStaticItem::as_string () const
*** 3034,3053 ****
  }
  
  std::string
- TraitItemConst::as_string () const
- {
-   // TODO: rewrite to work with non-linearisable exprs
-   std::string str = append_attributes (outer_attrs, OUTER);
- 
-   str += "\nconst " + name.as_string () + " : " + type->as_string ();
- 
-   if (has_expression ())
-     str += " = " + expr->as_string ();
- 
-   return str;
- }
- 
- std::string
  TraitItemType::as_string () const
  {
    std::string str = append_attributes (outer_attrs, OUTER);
--- 3044,3049 ----
*************** void
*** 3367,3373 ****
  Module::process_file_path ()
  {
    rust_assert (kind == Module::ModuleKind::UNLOADED);
!   rust_assert (module_file.empty ());
  
    // This corresponds to the path of the file 'including' the module. So the
    // file that contains the 'mod <file>;' directive
--- 3363,3375 ----
  Module::process_file_path ()
  {
    rust_assert (kind == Module::ModuleKind::UNLOADED);
! 
!   if (!module_file.empty ())
!     {
!       rust_error_at (locus, "error handling module file for %qs",
! 		     module_name.as_string ().c_str ());
!       return;
!     }
  
    // This corresponds to the path of the file 'including' the module. So the
    // file that contains the 'mod <file>;' directive
*************** AttrInputMetaItemContainer::separate_cfg
*** 4132,4137 ****
--- 4134,4145 ----
  
    for (auto it = items.begin () + 1; it != items.end (); ++it)
      {
+       if ((*it)->get_kind () == MetaItemInner::Kind::MetaItem
+ 	  && static_cast<MetaItem &> (**it).get_item_kind ()
+ 	       == MetaItem::ItemKind::PathExpr
+ 	  && !static_cast<MetaItemPathExpr &> (**it).get_expr ().is_literal ())
+ 	continue;
+ 
        Attribute attr = (*it)->to_attribute ();
        if (attr.is_empty ())
  	{
*************** AttrInputMetaItemContainer::separate_cfg
*** 4149,4159 ****
  bool
  Attribute::check_cfg_predicate (const Session &session) const
  {
    /* assume that cfg predicate actually can exist, i.e. attribute has cfg or
     * cfg_attr path */
    if (!has_attr_input ()
!       || (path.as_string () != Values::Attributes::CFG
! 	  && path.as_string () != Values::Attributes::CFG_ATTR))
      {
        // DEBUG message
        rust_debug (
--- 4157,4168 ----
  bool
  Attribute::check_cfg_predicate (const Session &session) const
  {
+   auto string_path = path.as_string ();
    /* assume that cfg predicate actually can exist, i.e. attribute has cfg or
     * cfg_attr path */
    if (!has_attr_input ()
!       || (string_path != Values::Attributes::CFG
! 	  && string_path != Values::Attributes::CFG_ATTR))
      {
        // DEBUG message
        rust_debug (
*************** Attribute::check_cfg_predicate (const Se
*** 4169,4174 ****
--- 4178,4190 ----
      return false;
  
    auto &meta_item = static_cast<AttrInputMetaItemContainer &> (*attr_input);
+   if (meta_item.get_items ().empty ()
+       && string_path == Values::Attributes::CFG_ATTR)
+     {
+       rust_error_at (path.get_locus (),
+ 		     "malformed %<cfg_attr%> attribute input");
+       return false;
+     }
    return meta_item.get_items ().front ()->check_cfg_predicate (session);
  }
  
*************** StaticItem::accept_vis (ASTVisitor &vis)
*** 4738,4749 ****
  {
    vis.visit (*this);
  }
- 
- void
- TraitItemConst::accept_vis (ASTVisitor &vis)
- {
-   vis.visit (*this);
- }
  
  void
  TraitItemType::accept_vis (ASTVisitor &vis)
--- 4754,4759 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-ast.h gcc-16-20251102/gcc/rust/ast/rust-ast.h
*** gcc-16-20251026/gcc/rust/ast/rust-ast.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-ast.h	Sun Nov  2 22:32:23 2025
*************** class Token : public TokenTree, public M
*** 184,200 ****
  {
    // A token is a kind of token tree (except delimiter tokens)
    // A token is a kind of MacroMatch (except $ and delimiter tokens)
- #if 0
-   // TODO: improve member variables - current ones are the same as lexer token
-   // Token kind.
-   TokenId token_id;
-   // Token location.
-   location_t locus;
-   // Associated text (if any) of token.
-   std::string str;
-   // Token type hint (if any).
-   PrimitiveCoreType type_hint;
- #endif
  
    const_TokenPtr tok_ref;
  
--- 184,189 ----
*************** public:
*** 209,261 ****
      return std::unique_ptr<Token> (clone_token_impl ());
    }
  
- #if 0
-   /* constructor from general text - avoid using if lexer const_TokenPtr is
-    * available */
-   Token (TokenId token_id, location_t locus, std::string str,
- 	 PrimitiveCoreType type_hint)
-     : token_id (token_id), locus (locus), str (std::move (str)),
-       type_hint (type_hint)
-   {}
- #endif
-   // not doable with new implementation - will have to make a const_TokenPtr
- 
    // Constructor from lexer const_TokenPtr
- #if 0
-   /* TODO: find workaround for std::string being nullptr - probably have to
-    * introduce new method in lexer Token, or maybe make conversion method
-    * there */
-   Token (const_TokenPtr lexer_token_ptr)
-     : token_id (lexer_token_ptr->get_id ()),
-       locus (lexer_token_ptr->get_locus ()), str (""),
-       type_hint (lexer_token_ptr->get_type_hint ())
-   {
-     // FIXME: change to "should have str" later?
-     if (lexer_token_ptr->has_str ())
-       {
- 	str = lexer_token_ptr->get_str ();
- 
- 	// DEBUG
- 	rust_debug ("ast token created with str '%s'", str.c_str ());
-       }
-     else
-       {
- 	// FIXME: is this returning correct thing?
- 	str = lexer_token_ptr->get_token_description ();
- 
- 	// DEBUG
- 	rust_debug ("ast token created with string '%s'", str.c_str ());
-       }
- 
-     // DEBUG
-     if (lexer_token_ptr->should_have_str () && !lexer_token_ptr->has_str ())
-       {
- 	rust_debug (
- 		 "BAD: for token '%s', should have string but does not!",
- 		 lexer_token_ptr->get_token_description ());
-       }
-   }
- #endif
    Token (const_TokenPtr lexer_tok_ptr) : tok_ref (std::move (lexer_tok_ptr)) {}
  
    bool is_string_lit () const
--- 198,204 ----
*************** public:
*** 283,289 ****
    std::vector<std::unique_ptr<Token>> to_token_stream () const override;
  
    TokenId get_id () const { return tok_ref->get_id (); }
!   bool has_str () const { return tok_ref->has_str (); }
    const std::string &get_str () const { return tok_ref->get_str (); }
  
    location_t get_locus () const { return tok_ref->get_locus (); }
--- 226,232 ----
    std::vector<std::unique_ptr<Token>> to_token_stream () const override;
  
    TokenId get_id () const { return tok_ref->get_id (); }
!   bool should_have_str () const { return tok_ref->should_have_str (); }
    const std::string &get_str () const { return tok_ref->get_str (); }
  
    location_t get_locus () const { return tok_ref->get_locus (); }
*************** public:
*** 1137,1143 ****
  
    virtual void mark_for_strip () = 0;
    virtual bool is_marked_for_strip () const = 0;
!   NodeId get_node_id () const { return node_id; }
  
    virtual Kind get_stmt_kind () = 0;
  
--- 1080,1088 ----
  
    virtual void mark_for_strip () = 0;
    virtual bool is_marked_for_strip () const = 0;
! 
!   // TODO: put this in a virtual base class?
!   virtual NodeId get_node_id () const { return node_id; }
  
    virtual Kind get_stmt_kind () = 0;
  
*************** public:
*** 1536,1542 ****
  
    virtual location_t get_locus () const = 0;
  
!   NodeId get_node_id () const { return node_id; }
    virtual Type *reconstruct_impl () const = 0;
  
  protected:
--- 1481,1488 ----
  
    virtual location_t get_locus () const = 0;
  
!   // TODO: put this in a virtual base class?
!   virtual NodeId get_node_id () const { return node_id; }
    virtual Type *reconstruct_impl () const = 0;
  
  protected:
*************** public:
*** 1799,1804 ****
--- 1745,1752 ----
    virtual bool is_marked_for_strip () const = 0;
  
    virtual location_t get_locus () const = 0;
+ 
+   virtual NodeId get_node_id () const = 0;
  };
  
  // Item used in trait declarations - abstract base class
*************** public:
*** 1829,1835 ****
      return std::unique_ptr<TraitItem> (clone_associated_item_impl ());
    }
  
!   NodeId get_node_id () const { return node_id; }
    location_t get_locus () const override { return locus; }
  };
  
--- 1777,1783 ----
      return std::unique_ptr<TraitItem> (clone_associated_item_impl ());
    }
  
!   NodeId get_node_id () const override { return node_id; }
    location_t get_locus () const override { return locus; }
  };
  
*************** public:
*** 1957,1974 ****
  class SingleASTNode : public Visitable
  {
  public:
!   enum NodeType
    {
!     EXPRESSION,
!     ITEM,
!     STMT,
!     EXTERN,
!     ASSOC_ITEM,
!     TYPE,
    };
  
  private:
!   NodeType kind;
  
    // FIXME make this a union
    std::unique_ptr<Expr> expr;
--- 1905,1923 ----
  class SingleASTNode : public Visitable
  {
  public:
!   enum class Kind
    {
!     Expr,
!     Item,
!     Stmt,
!     Extern,
!     Assoc,
!     Type,
!     Pattern,
    };
  
  private:
!   Kind kind;
  
    // FIXME make this a union
    std::unique_ptr<Expr> expr;
*************** private:
*** 1977,2006 ****
    std::unique_ptr<ExternalItem> external_item;
    std::unique_ptr<AssociatedItem> assoc_item;
    std::unique_ptr<Type> type;
  
  public:
    SingleASTNode (std::unique_ptr<Expr> expr)
!     : kind (EXPRESSION), expr (std::move (expr))
    {}
  
    SingleASTNode (std::unique_ptr<Item> item)
!     : kind (ITEM), item (std::move (item))
    {}
  
    SingleASTNode (std::unique_ptr<Stmt> stmt)
!     : kind (STMT), stmt (std::move (stmt))
    {}
  
    SingleASTNode (std::unique_ptr<ExternalItem> item)
!     : kind (EXTERN), external_item (std::move (item))
    {}
  
    SingleASTNode (std::unique_ptr<AssociatedItem> item)
!     : kind (ASSOC_ITEM), assoc_item (std::move (item))
    {}
  
    SingleASTNode (std::unique_ptr<Type> type)
!     : kind (TYPE), type (std::move (type))
    {}
  
    SingleASTNode (SingleASTNode const &other);
--- 1926,1960 ----
    std::unique_ptr<ExternalItem> external_item;
    std::unique_ptr<AssociatedItem> assoc_item;
    std::unique_ptr<Type> type;
+   std::unique_ptr<Pattern> pattern;
  
  public:
    SingleASTNode (std::unique_ptr<Expr> expr)
!     : kind (Kind::Expr), expr (std::move (expr))
    {}
  
    SingleASTNode (std::unique_ptr<Item> item)
!     : kind (Kind::Item), item (std::move (item))
    {}
  
    SingleASTNode (std::unique_ptr<Stmt> stmt)
!     : kind (Kind::Stmt), stmt (std::move (stmt))
    {}
  
    SingleASTNode (std::unique_ptr<ExternalItem> item)
!     : kind (Kind::Extern), external_item (std::move (item))
    {}
  
    SingleASTNode (std::unique_ptr<AssociatedItem> item)
!     : kind (Kind::Assoc), assoc_item (std::move (item))
    {}
  
    SingleASTNode (std::unique_ptr<Type> type)
!     : kind (Kind::Type), type (std::move (type))
!   {}
! 
!   SingleASTNode (std::unique_ptr<Pattern> pattern)
!     : kind (Kind::Pattern), pattern (std::move (pattern))
    {}
  
    SingleASTNode (SingleASTNode const &other);
*************** public:
*** 2010,2032 ****
    SingleASTNode (SingleASTNode &&other) = default;
    SingleASTNode &operator= (SingleASTNode &&other) = default;
  
!   NodeType get_kind () const { return kind; }
  
    std::unique_ptr<Expr> &get_expr ()
    {
!     rust_assert (kind == EXPRESSION);
      return expr;
    }
  
    std::unique_ptr<Item> &get_item ()
    {
!     rust_assert (kind == ITEM);
      return item;
    }
  
    std::unique_ptr<Stmt> &get_stmt ()
    {
!     rust_assert (kind == STMT);
      return stmt;
    }
  
--- 1964,1986 ----
    SingleASTNode (SingleASTNode &&other) = default;
    SingleASTNode &operator= (SingleASTNode &&other) = default;
  
!   Kind get_kind () const { return kind; }
  
    std::unique_ptr<Expr> &get_expr ()
    {
!     rust_assert (kind == Kind::Expr);
      return expr;
    }
  
    std::unique_ptr<Item> &get_item ()
    {
!     rust_assert (kind == Kind::Item);
      return item;
    }
  
    std::unique_ptr<Stmt> &get_stmt ()
    {
!     rust_assert (kind == Kind::Stmt);
      return stmt;
    }
  
*************** public:
*** 2071,2076 ****
--- 2025,2036 ----
      return std::move (type);
    }
  
+   std::unique_ptr<Pattern> take_pattern ()
+   {
+     rust_assert (!is_error ());
+     return std::move (pattern);
+   }
+ 
    void accept_vis (ASTVisitor &vis) override;
  
    bool is_error ();
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-builtin-ast-nodes.h gcc-16-20251102/gcc/rust/ast/rust-builtin-ast-nodes.h
*** gcc-16-20251026/gcc/rust/ast/rust-builtin-ast-nodes.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-builtin-ast-nodes.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 134,139 ****
--- 134,140 ----
  
    FormatArgumentKind get_kind () const { return kind; }
    const Expr &get_expr () const { return *expr; }
+   Expr &get_expr () { return *expr; }
  
  private:
    FormatArgument (FormatArgumentKind::Kind kind, tl::optional<Identifier> ident,
*************** public:
*** 164,169 ****
--- 165,175 ----
    void push (FormatArgument &&elt) { args.emplace_back (std::move (elt)); }
    const FormatArgument at (size_t idx) const { return args.at (idx); }
  
+   const std::vector<FormatArgument> &get_args () const { return args; }
+   std::vector<FormatArgument> &get_args () { return args; }
+   size_t size () const { return args.size (); }
+   bool empty () const { return args.empty (); }
+ 
  private:
    std::vector<FormatArgument> args;
  };
*************** public:
*** 200,205 ****
--- 206,212 ----
  
    const Fmt::Pieces &get_template () const { return template_pieces; }
    const FormatArguments &get_arguments () const { return arguments; }
+   FormatArguments &get_arguments () { return arguments; }
    virtual location_t get_locus () const override;
  
    Expr::Kind get_expr_kind () const override { return Expr::Kind::FormatArgs; }
*************** public:
*** 255,260 ****
--- 262,268 ----
    virtual location_t get_locus () const override { return loc; }
    const Type &get_type () const { return *type; }
    Type &get_type () { return *type; }
+   std::unique_ptr<Type> &get_type_ptr () { return type; }
    const Identifier &get_field () const { return field; }
  
    bool is_expr_without_block () const override { return false; }
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-collect-lang-items.cc gcc-16-20251102/gcc/rust/ast/rust-collect-lang-items.cc
*** gcc-16-20251026/gcc/rust/ast/rust-collect-lang-items.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-collect-lang-items.cc	Sun Nov  2 22:32:23 2025
*************** get_lang_item_attr (const T &maybe_lang_
*** 43,60 ****
  	  continue;
  	}
  
!       bool is_lang_item = str_path == Values::Attributes::LANG
! 			  && attr.has_attr_input ()
! 			  && attr.get_attr_input ().get_attr_input_type ()
! 			       == AST::AttrInput::AttrInputType::LITERAL;
  
        if (is_lang_item)
  	{
! 	  auto &literal
! 	    = static_cast<AST::AttrInputLiteral &> (attr.get_attr_input ());
! 	  const auto &lang_item_type_str = literal.get_literal ().as_string ();
  
! 	  return LangItem::Parse (lang_item_type_str);
  	}
      }
  
--- 43,58 ----
  	  continue;
  	}
  
!       bool is_lang_item = str_path == Values::Attributes::LANG;
  
        if (is_lang_item)
  	{
! 	  auto lang_item_type_str
! 	    = Analysis::Attributes::extract_string_literal (attr);
  
! 	  rust_assert (lang_item_type_str.has_value ());
! 
! 	  return LangItem::Parse (*lang_item_type_str);
  	}
      }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-cond-compilation.h gcc-16-20251102/gcc/rust/ast/rust-cond-compilation.h
*** gcc-16-20251026/gcc/rust/ast/rust-cond-compilation.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-cond-compilation.h	Sun Nov  2 22:32:23 2025
*************** class ConfigurationAll : public Configur
*** 91,99 ****
      predicate_list; // inlined form
  
  public:
    ConfigurationAll (
      std::vector<std::unique_ptr<ConfigurationPredicate>> predicate_list)
!     : predicate_list (predicate_list)
    {}
  
    void accept_vis (ASTVisitor &vis) override;
--- 91,103 ----
      predicate_list; // inlined form
  
  public:
+   ConfigurationAll (const ConfigurationAll &) = delete;
+ 
+   ConfigurationAll (ConfigurationAll &&) = default;
+ 
    ConfigurationAll (
      std::vector<std::unique_ptr<ConfigurationPredicate>> predicate_list)
!     : predicate_list (std::move (predicate_list))
    {}
  
    void accept_vis (ASTVisitor &vis) override;
*************** protected:
*** 103,109 ****
     * than base */
    ConfigurationAll *clone_configuration_predicate_impl () const override
    {
!     return new ConfigurationAll (*this);
    }
  };
  
--- 107,120 ----
     * than base */
    ConfigurationAll *clone_configuration_predicate_impl () const override
    {
!     decltype (predicate_list) predicate_list_clone = {};
!     predicate_list_clone.reserve (predicate_list.size ());
! 
!     for (const auto &predicate : predicate_list)
!       predicate_list_clone.push_back (
! 	predicate->clone_configuration_predicate ());
! 
!     return new ConfigurationAll (std::move (predicate_list_clone));
    }
  };
  
*************** class ConfigurationAny : public Configur
*** 114,122 ****
      predicate_list; // inlined form
  
  public:
    ConfigurationAny (
      std::vector<std::unique_ptr<ConfigurationPredicate>> predicate_list)
!     : predicate_list (predicate_list)
    {}
  
    void accept_vis (ASTVisitor &vis) override;
--- 125,137 ----
      predicate_list; // inlined form
  
  public:
+   ConfigurationAny (const ConfigurationAny &) = delete;
+ 
+   ConfigurationAny (ConfigurationAny &&) = default;
+ 
    ConfigurationAny (
      std::vector<std::unique_ptr<ConfigurationPredicate>> predicate_list)
!     : predicate_list (std::move (predicate_list))
    {}
  
    void accept_vis (ASTVisitor &vis) override;
*************** protected:
*** 126,132 ****
     * than base */
    ConfigurationAny *clone_configuration_predicate_impl () const override
    {
!     return new ConfigurationAny (*this);
    }
  };
  
--- 141,154 ----
     * than base */
    ConfigurationAny *clone_configuration_predicate_impl () const override
    {
!     decltype (predicate_list) predicate_list_clone = {};
!     predicate_list_clone.reserve (predicate_list.size ());
! 
!     for (const auto &predicate : predicate_list)
!       predicate_list_clone.push_back (
! 	predicate->clone_configuration_predicate ());
! 
!     return new ConfigurationAny (std::move (predicate_list_clone));
    }
  };
  
*************** public:
*** 226,232 ****
    CfgAttrAttribute (CfgAttrAttribute const &other)
      : config_to_include (
        other.config_to_include->clone_configuration_predicate ()),
!       cfg_attrs (cfg_attrs)
    {}
  
    // Overloaded assignment operator to clone
--- 248,254 ----
    CfgAttrAttribute (CfgAttrAttribute const &other)
      : config_to_include (
        other.config_to_include->clone_configuration_predicate ()),
!       cfg_attrs (other.cfg_attrs)
    {}
  
    // Overloaded assignment operator to clone
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-desugar-apit.cc gcc-16-20251102/gcc/rust/ast/rust-desugar-apit.cc
*** gcc-16-20251026/gcc/rust/ast/rust-desugar-apit.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-desugar-apit.cc	Sun Nov  2 22:32:23 2025
*************** public:
*** 188,196 ****
  
      // Convert to TypePath by creating path segments
      std::vector<std::unique_ptr<TypePathSegment>> segments;
!     segments.push_back (std::unique_ptr<TypePathSegment> (new TypePathSegment (
!       PathIdentSegment (ident.as_string (), type.get_locus ()), false,
!       type.get_locus ())));
  
      // Create TypePath from segments
      auto type_path
--- 188,197 ----
  
      // Convert to TypePath by creating path segments
      std::vector<std::unique_ptr<TypePathSegment>> segments;
!     segments.emplace_back (
!       new TypePathSegment (PathIdentSegment (ident.as_string (),
! 					     type.get_locus ()),
! 			   false, type.get_locus ()));
  
      // Create TypePath from segments
      auto type_path
*************** public:
*** 198,203 ****
--- 199,206 ----
  
      // Convert bounds from impl trait to generic parameter bounds
      std::vector<std::unique_ptr<TypeParamBound>> bounds;
+     bounds.reserve (type.get_type_param_bounds ().size ());
+ 
      for (auto &bound : type.get_type_param_bounds ())
        bounds.push_back (bound->clone_type_param_bound ());
  
*************** public:
*** 228,236 ****
  
      // Convert to TypePath by creating path segments
      std::vector<std::unique_ptr<TypePathSegment>> segments;
!     segments.push_back (std::unique_ptr<TypePathSegment> (new TypePathSegment (
!       PathIdentSegment (ident.as_string (), type.get_locus ()), false,
!       type.get_locus ())));
  
      // Create TypePath from segments
      auto type_path
--- 231,240 ----
  
      // Convert to TypePath by creating path segments
      std::vector<std::unique_ptr<TypePathSegment>> segments;
!     segments.emplace_back (
!       new TypePathSegment (PathIdentSegment (ident.as_string (),
! 					     type.get_locus ()),
! 			   false, type.get_locus ()));
  
      // Create TypePath from segments
      auto type_path
*************** private:
*** 407,412 ****
--- 411,419 ----
  
  		  std::vector<std::unique_ptr<TypeParamBound>>
  		    type_param_bounds;
+ 		  type_param_bounds.reserve (
+ 		    tp.get_type_param_bounds ().size ());
+ 
  		  for (auto &b : tp.get_type_param_bounds ())
  		    type_param_bounds.push_back (std::move (b));
  		  tp.get_type_param_bounds ().clear ();
*************** private:
*** 459,467 ****
      std::vector<SimplePathSegment> simple_segs = {simple_seg};
      auto simple_path = SimplePath (simple_segs, false, ident.get_locus ());
      std::vector<std::unique_ptr<TypePathSegment>> segments;
!     segments.push_back (std::unique_ptr<TypePathSegment> (new TypePathSegment (
!       PathIdentSegment (ident.as_string (), ident.get_locus ()), false,
!       ident.get_locus ())));
      auto type_path = new TypePath (std::move (segments), ident.get_locus ());
      return std::unique_ptr<Type> (type_path);
    }
--- 466,475 ----
      std::vector<SimplePathSegment> simple_segs = {simple_seg};
      auto simple_path = SimplePath (simple_segs, false, ident.get_locus ());
      std::vector<std::unique_ptr<TypePathSegment>> segments;
!     segments.emplace_back (
!       new TypePathSegment (PathIdentSegment (ident.as_string (),
! 					     ident.get_locus ()),
! 			   false, ident.get_locus ()));
      auto type_path = new TypePath (std::move (segments), ident.get_locus ());
      return std::unique_ptr<Type> (type_path);
    }
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-desugar-for-loops.cc gcc-16-20251102/gcc/rust/ast/rust-desugar-for-loops.cc
*** gcc-16-20251026/gcc/rust/ast/rust-desugar-for-loops.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-desugar-for-loops.cc	Sun Nov  2 22:32:23 2025
*************** DesugarForLoops::DesugarCtx::make_contin
*** 51,57 ****
    patterns.emplace_back (std::move (val));
  
    auto pattern_item = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (patterns)));
    auto pattern = std::unique_ptr<Pattern> (new TupleStructPattern (
      builder.path_in_expression (LangItem::Kind::OPTION_SOME),
      std::move (pattern_item)));
--- 51,57 ----
    patterns.emplace_back (std::move (val));
  
    auto pattern_item = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (patterns)));
    auto pattern = std::unique_ptr<Pattern> (new TupleStructPattern (
      builder.path_in_expression (LangItem::Kind::OPTION_SOME),
      std::move (pattern_item)));
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-desugar-question-mark.cc gcc-16-20251102/gcc/rust/ast/rust-desugar-question-mark.cc
*** gcc-16-20251026/gcc/rust/ast/rust-desugar-question-mark.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-desugar-question-mark.cc	Sun Nov  2 22:32:23 2025
*************** ok_case (Builder &builder)
*** 55,61 ****
    patterns.emplace_back (std::move (val));
  
    auto pattern_item = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (patterns)));
    auto pattern = std::unique_ptr<Pattern> (new TupleStructPattern (
      builder.path_in_expression (LangItem::Kind::RESULT_OK),
      std::move (pattern_item)));
--- 55,61 ----
    patterns.emplace_back (std::move (val));
  
    auto pattern_item = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (patterns)));
    auto pattern = std::unique_ptr<Pattern> (new TupleStructPattern (
      builder.path_in_expression (LangItem::Kind::RESULT_OK),
      std::move (pattern_item)));
*************** err_case (Builder &builder)
*** 82,88 ****
    patterns.emplace_back (std::move (val));
  
    auto pattern_item = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (patterns)));
    auto pattern = std::unique_ptr<Pattern> (new TupleStructPattern (
      builder.path_in_expression (LangItem::Kind::RESULT_ERR),
      std::move (pattern_item)));
--- 82,88 ----
    patterns.emplace_back (std::move (val));
  
    auto pattern_item = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (patterns)));
    auto pattern = std::unique_ptr<Pattern> (new TupleStructPattern (
      builder.path_in_expression (LangItem::Kind::RESULT_ERR),
      std::move (pattern_item)));
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-expr.h gcc-16-20251102/gcc/rust/ast/rust-expr.h
*** gcc-16-20251026/gcc/rust/ast/rust-expr.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-expr.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 282,287 ****
--- 282,289 ----
  
    Expr &get_expr () { return *expr; }
  
+   std::unique_ptr<Expr> &get_expr_ptr () { return expr; }
+ 
    std::string as_string () const override
    {
      return path.as_string () + " = " + expr->as_string ();
*************** public:
*** 296,302 ****
    //  we have no idea use which of them, just simply return UNKNOWN_LOCATION
    //  now.
    // Maybe we will figure out when we really need the location in the future.
!   location_t get_locus () const override { return UNKNOWN_LOCATION; }
  
    void accept_vis (ASTVisitor &vis) override;
  
--- 298,308 ----
    //  we have no idea use which of them, just simply return UNKNOWN_LOCATION
    //  now.
    // Maybe we will figure out when we really need the location in the future.
!   location_t get_locus () const override
!   {
!     rust_unreachable ();
!     return UNKNOWN_LOCATION;
!   }
  
    void accept_vis (ASTVisitor &vis) override;
  
*************** public:
*** 414,419 ****
--- 420,431 ----
      return *main_or_left_expr;
    }
  
+   std::unique_ptr<Expr> &get_borrowed_expr_ptr ()
+   {
+     rust_assert (main_or_left_expr != nullptr);
+     return main_or_left_expr;
+   }
+ 
    bool has_borrow_expr () const { return main_or_left_expr != nullptr; }
  
    bool get_is_mut () const { return mutability == Mutability::Mut; }
*************** public:
*** 455,460 ****
--- 467,478 ----
      return *main_or_left_expr;
    }
  
+   std::unique_ptr<Expr> &get_dereferenced_expr_ptr ()
+   {
+     rust_assert (main_or_left_expr != nullptr);
+     return main_or_left_expr;
+   }
+ 
    Expr::Kind get_expr_kind () const override { return Expr::Kind::Dereference; }
  
  protected:
*************** public:
*** 488,493 ****
--- 506,517 ----
      return *main_or_left_expr;
    }
  
+   std::unique_ptr<Expr> &get_propagating_expr_ptr ()
+   {
+     rust_assert (main_or_left_expr != nullptr);
+     return main_or_left_expr;
+   }
+ 
    Expr::Kind get_expr_kind () const override
    {
      return Expr::Kind::ErrorPropagation;
*************** public:
*** 536,541 ****
--- 560,571 ----
      return *main_or_left_expr;
    }
  
+   std::unique_ptr<Expr> &get_negated_expr_ptr ()
+   {
+     rust_assert (main_or_left_expr != nullptr);
+     return main_or_left_expr;
+   }
+ 
    Expr::Kind get_expr_kind () const override { return Expr::Kind::Negation; }
  
  protected:
*************** public:
*** 865,870 ****
--- 895,906 ----
      return *main_or_left_expr;
    }
  
+   std::unique_ptr<Expr> &get_casted_expr_ptr ()
+   {
+     rust_assert (main_or_left_expr != nullptr);
+     return main_or_left_expr;
+   }
+ 
    // TODO: is this better? Or is a "vis_block" better?
    TypeNoBounds &get_type_to_cast_to ()
    {
*************** public:
*** 872,877 ****
--- 908,919 ----
      return *type_to_convert_to;
    }
  
+   std::unique_ptr<TypeNoBounds> &get_type_to_cast_to_ptr ()
+   {
+     rust_assert (type_to_convert_to != nullptr);
+     return type_to_convert_to;
+   }
+ 
    Expr::Kind get_expr_kind () const override { return Expr::Kind::TypeCast; }
  
  protected:
*************** public:
*** 1282,1287 ****
--- 1324,1335 ----
      return *elem_to_copy;
    }
  
+   std::unique_ptr<Expr> &get_elem_to_copy_ptr ()
+   {
+     rust_assert (elem_to_copy != nullptr);
+     return elem_to_copy;
+   }
+ 
    // TODO: is this better? Or is a "vis_block" better?
    Expr &get_num_copies ()
    {
*************** public:
*** 1289,1294 ****
--- 1337,1348 ----
      return *num_copies;
    }
  
+   std::unique_ptr<Expr> &get_num_copies_ptr ()
+   {
+     rust_assert (num_copies != nullptr);
+     return num_copies;
+   }
+ 
  protected:
    ArrayElemsCopied *clone_array_elems_impl () const override
    {
*************** public:
*** 1468,1473 ****
--- 1522,1533 ----
      return *array_expr;
    }
  
+   std::unique_ptr<Expr> &get_array_expr_ptr ()
+   {
+     rust_assert (array_expr != nullptr);
+     return array_expr;
+   }
+ 
    // TODO: is this better? Or is a "vis_block" better?
    Expr &get_index_expr ()
    {
*************** public:
*** 1475,1480 ****
--- 1535,1546 ----
      return *index_expr;
    }
  
+   std::unique_ptr<Expr> &get_index_expr_ptr ()
+   {
+     rust_assert (index_expr != nullptr);
+     return index_expr;
+   }
+ 
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
  
*************** class TupleIndexExpr : public ExprWithou
*** 1599,1604 ****
--- 1665,1671 ----
    TupleIndex tuple_index;
  
    location_t locus;
+   bool to_strip;
  
    // i.e. pair.0
  
*************** public:
*** 1610,1622 ****
    TupleIndexExpr (std::unique_ptr<Expr> tuple_expr, TupleIndex index,
  		  std::vector<Attribute> outer_attribs, location_t locus)
      : outer_attrs (std::move (outer_attribs)),
!       tuple_expr (std::move (tuple_expr)), tuple_index (index), locus (locus)
    {}
  
    // Copy constructor requires a clone for tuple_expr
    TupleIndexExpr (TupleIndexExpr const &other)
      : ExprWithoutBlock (other), outer_attrs (other.outer_attrs),
!       tuple_index (other.tuple_index), locus (other.locus)
    {
      // guard to prevent null dereference (only required if error state)
      if (other.tuple_expr != nullptr)
--- 1677,1691 ----
    TupleIndexExpr (std::unique_ptr<Expr> tuple_expr, TupleIndex index,
  		  std::vector<Attribute> outer_attribs, location_t locus)
      : outer_attrs (std::move (outer_attribs)),
!       tuple_expr (std::move (tuple_expr)), tuple_index (index), locus (locus),
!       to_strip (false)
    {}
  
    // Copy constructor requires a clone for tuple_expr
    TupleIndexExpr (TupleIndexExpr const &other)
      : ExprWithoutBlock (other), outer_attrs (other.outer_attrs),
!       tuple_index (other.tuple_index), locus (other.locus),
!       to_strip (other.to_strip)
    {
      // guard to prevent null dereference (only required if error state)
      if (other.tuple_expr != nullptr)
*************** public:
*** 1630,1635 ****
--- 1699,1705 ----
      tuple_index = other.tuple_index;
      locus = other.locus;
      outer_attrs = other.outer_attrs;
+     to_strip = other.to_strip;
  
      // guard to prevent null dereference (only required if error state)
      if (other.tuple_expr != nullptr)
*************** public:
*** 1649,1656 ****
    void accept_vis (ASTVisitor &vis) override;
  
    // Invalid if tuple expr is null, so base stripping on that.
!   void mark_for_strip () override { tuple_expr = nullptr; }
!   bool is_marked_for_strip () const override { return tuple_expr == nullptr; }
  
    // TODO: is this better? Or is a "vis_block" better?
    Expr &get_tuple_expr ()
--- 1719,1726 ----
    void accept_vis (ASTVisitor &vis) override;
  
    // Invalid if tuple expr is null, so base stripping on that.
!   void mark_for_strip () override { to_strip = true; }
!   bool is_marked_for_strip () const override { return to_strip; }
  
    // TODO: is this better? Or is a "vis_block" better?
    Expr &get_tuple_expr ()
*************** public:
*** 1659,1664 ****
--- 1729,1740 ----
      return *tuple_expr;
    }
  
+   std::unique_ptr<Expr> &get_tuple_expr_ptr ()
+   {
+     rust_assert (tuple_expr != nullptr);
+     return tuple_expr;
+   }
+ 
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
  
*************** public:
*** 1807,1812 ****
--- 1883,1894 ----
      rust_assert (base_struct != nullptr);
      return *base_struct;
    }
+ 
+   std::unique_ptr<Expr> &get_base_struct_ptr ()
+   {
+     rust_assert (base_struct != nullptr);
+     return base_struct;
+   }
  };
  
  /* Base AST node for a single struct expression field (in struct instance
*************** public:
*** 1923,1928 ****
--- 2005,2016 ----
      rust_assert (value != nullptr);
      return *value;
    }
+ 
+   std::unique_ptr<Expr> &get_value_ptr ()
+   {
+     rust_assert (value != nullptr);
+     return value;
+   }
  };
  
  // Identifier and value variant of StructExprField AST node
*************** public:
*** 2293,2298 ****
--- 2381,2392 ----
      return *receiver;
    }
  
+   std::unique_ptr<Expr> &get_receiver_expr_ptr ()
+   {
+     rust_assert (receiver != nullptr);
+     return receiver;
+   }
+ 
    const PathExprSegment &get_method_name () const { return method_name; }
    PathExprSegment &get_method_name () { return method_name; }
  
*************** public:
*** 2381,2386 ****
--- 2475,2486 ----
      return *receiver;
    }
  
+   std::unique_ptr<Expr> &get_receiver_expr_ptr ()
+   {
+     rust_assert (receiver != nullptr);
+     return receiver;
+   }
+ 
    Identifier get_field_name () const { return field; }
  
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
*************** public:
*** 2480,2485 ****
--- 2580,2591 ----
      return *pattern;
    }
  
+   std::unique_ptr<Pattern> &get_pattern_ptr ()
+   {
+     rust_assert (pattern != nullptr);
+     return pattern;
+   }
+ 
    Type &get_type ()
    {
      rust_assert (has_type_given ());
*************** public:
*** 2532,2537 ****
--- 2638,2644 ----
    Expr::Kind get_expr_kind () const override { return Expr::Kind::Closure; }
  
    virtual Expr &get_definition_expr () = 0;
+   virtual std::unique_ptr<Expr> &get_definition_expr_ptr () = 0;
  };
  
  // Represents a non-type-specified closure expression AST node
*************** public:
*** 2597,2602 ****
--- 2704,2715 ----
      return *closure_inner;
    }
  
+   std::unique_ptr<Expr> &get_definition_expr_ptr () override
+   {
+     rust_assert (closure_inner != nullptr);
+     return closure_inner;
+   }
+ 
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
*************** public:
*** 2827,2832 ****
--- 2940,2951 ----
      return *expr.value ();
    }
  
+   std::unique_ptr<Expr> &get_inner_expr_ptr ()
+   {
+     rust_assert (expr.has_value ());
+     return expr.value ();
+   }
+ 
    NodeId get_node_id () const override { return node_id; }
  
    /* FIXME: AnonConst are always "internal" and should not have outer attributes
*************** class ClosureExprInnerTyped : public Clo
*** 2922,2929 ****
  {
    // TODO: spec says typenobounds
    std::unique_ptr<Type> return_type;
!   std::unique_ptr<BlockExpr>
!     expr; // only used because may be polymorphic in future
  
  public:
    std::string as_string () const override;
--- 3041,3047 ----
  {
    // TODO: spec says typenobounds
    std::unique_ptr<Type> return_type;
!   std::unique_ptr<Expr> expr; // only used because may be polymorphic in future
  
  public:
    std::string as_string () const override;
*************** public:
*** 2947,2953 ****
    {
      // guard to prevent null dereference (only required if error state)
      if (other.expr != nullptr)
!       expr = other.expr->clone_block_expr ();
      if (other.return_type != nullptr)
        return_type = other.return_type->clone_type ();
    }
--- 3065,3071 ----
    {
      // guard to prevent null dereference (only required if error state)
      if (other.expr != nullptr)
!       expr = other.expr->clone_expr ();
      if (other.return_type != nullptr)
        return_type = other.return_type->clone_type ();
    }
*************** public:
*** 2962,2968 ****
  
      // guard to prevent null dereference (only required if error state)
      if (other.expr != nullptr)
!       expr = other.expr->clone_block_expr ();
      else
        expr = nullptr;
      if (other.return_type != nullptr)
--- 3080,3086 ----
  
      // guard to prevent null dereference (only required if error state)
      if (other.expr != nullptr)
!       expr = other.expr->clone_expr ();
      else
        expr = nullptr;
      if (other.return_type != nullptr)
*************** public:
*** 2985,2996 ****
    bool is_marked_for_strip () const override { return expr == nullptr; }
  
    // TODO: is this better? Or is a "vis_block" better?
!   BlockExpr &get_definition_expr () override
    {
      rust_assert (expr != nullptr);
      return *expr;
    }
  
    // TODO: is this better? Or is a "vis_block" better?
    Type &get_return_type ()
    {
--- 3103,3121 ----
    bool is_marked_for_strip () const override { return expr == nullptr; }
  
    // TODO: is this better? Or is a "vis_block" better?
!   Expr &get_definition_expr () override
    {
      rust_assert (expr != nullptr);
      return *expr;
    }
  
+   std::unique_ptr<Expr> &get_definition_expr_ptr () override
+   {
+     rust_assert (expr != nullptr);
+ 
+     return expr;
+   }
+ 
    // TODO: is this better? Or is a "vis_block" better?
    Type &get_return_type ()
    {
*************** public:
*** 3147,3152 ****
--- 3272,3283 ----
      return *break_expr;
    }
  
+   std::unique_ptr<Expr> &get_break_expr_ptr ()
+   {
+     rust_assert (has_break_expr ());
+     return break_expr;
+   }
+ 
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
  
*************** public:
*** 3274,3279 ****
--- 3405,3422 ----
      return *to;
    }
  
+   std::unique_ptr<Expr> &get_from_expr_ptr ()
+   {
+     rust_assert (from != nullptr);
+     return from;
+   }
+ 
+   std::unique_ptr<Expr> &get_to_expr_ptr ()
+   {
+     rust_assert (to != nullptr);
+     return to;
+   }
+ 
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
*************** public:
*** 3335,3340 ****
--- 3478,3489 ----
      return *from;
    }
  
+   std::unique_ptr<Expr> &get_from_expr_ptr ()
+   {
+     rust_assert (from != nullptr);
+     return from;
+   }
+ 
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
*************** public:
*** 3397,3402 ****
--- 3546,3557 ----
      return *to;
    }
  
+   std::unique_ptr<Expr> &get_to_expr_ptr ()
+   {
+     rust_assert (to != nullptr);
+     return to;
+   }
+ 
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
*************** public:
*** 3510,3515 ****
--- 3665,3682 ----
      return *to;
    }
  
+   std::unique_ptr<Expr> &get_from_expr_ptr ()
+   {
+     rust_assert (from != nullptr);
+     return from;
+   }
+ 
+   std::unique_ptr<Expr> &get_to_expr_ptr ()
+   {
+     rust_assert (to != nullptr);
+     return to;
+   }
+ 
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
*************** public:
*** 3572,3577 ****
--- 3739,3750 ----
      return *to;
    }
  
+   std::unique_ptr<Expr> &get_to_expr_ptr ()
+   {
+     rust_assert (to != nullptr);
+     return to;
+   }
+ 
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
*************** public:
*** 3645,3650 ****
--- 3818,3829 ----
      return *expr;
    }
  
+   std::unique_ptr<Expr> &get_boxed_expr_ptr ()
+   {
+     rust_assert (expr != nullptr);
+     return expr;
+   }
+ 
    Expr::Kind get_expr_kind () const override { return Expr::Kind::Box; }
  
  protected:
*************** public:
*** 3726,3731 ****
--- 3905,3916 ----
      return *return_expr;
    }
  
+   std::unique_ptr<Expr> &get_returned_expr_ptr ()
+   {
+     rust_assert (return_expr != nullptr);
+     return return_expr;
+   }
+ 
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
  
*************** public:
*** 3801,3806 ****
--- 3986,3992 ----
  
    // TODO: is this better? Or is a "vis_block" better?
    BlockExpr &get_block_expr () { return *block_expr; }
+   std::unique_ptr<BlockExpr> &get_block_expr_ptr () { return block_expr; }
  
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
*************** public:
*** 3886,3891 ****
--- 4072,4083 ----
      return *expr;
    }
  
+   std::unique_ptr<BlockExpr> &get_block_expr_ptr ()
+   {
+     rust_assert (expr != nullptr);
+     return expr;
+   }
+ 
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
  
*************** public:
*** 3978,3983 ****
--- 4170,4181 ----
      return *loop_block;
    }
  
+   std::unique_ptr<BlockExpr> &get_loop_block_ptr ()
+   {
+     rust_assert (loop_block != nullptr);
+     return loop_block;
+   }
+ 
    const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
    std::vector<Attribute> &get_outer_attrs () override { return outer_attrs; }
  
*************** public:
*** 4078,4083 ****
--- 4276,4287 ----
      return *condition;
    }
  
+   std::unique_ptr<Expr> &get_predicate_expr_ptr ()
+   {
+     rust_assert (condition != nullptr);
+     return condition;
+   }
+ 
    BaseLoopExpr::Kind get_loop_kind () const override
    {
      return BaseLoopExpr::Kind::While;
*************** public:
*** 4156,4161 ****
--- 4360,4371 ----
      return *scrutinee;
    }
  
+   std::unique_ptr<Expr> &get_scrutinee_expr_ptr ()
+   {
+     rust_assert (scrutinee != nullptr);
+     return scrutinee;
+   }
+ 
    // TODO: this mutable getter seems really dodgy. Think up better way.
    const std::vector<std::unique_ptr<Pattern>> &get_patterns () const
    {
*************** public:
*** 4233,4238 ****
--- 4443,4454 ----
      return *iterator_expr;
    }
  
+   std::unique_ptr<Expr> &get_iterator_expr_ptr ()
+   {
+     rust_assert (iterator_expr != nullptr);
+     return iterator_expr;
+   }
+ 
    // TODO: is this better? Or is a "vis_block" better?
    Pattern &get_pattern ()
    {
*************** public:
*** 4240,4245 ****
--- 4456,4467 ----
      return *pattern;
    }
  
+   std::unique_ptr<Pattern> &get_pattern_ptr ()
+   {
+     rust_assert (pattern != nullptr);
+     return pattern;
+   }
+ 
    BaseLoopExpr::Kind get_loop_kind () const override
    {
      return BaseLoopExpr::Kind::For;
*************** public:
*** 4892,4897 ****
--- 5114,5125 ----
      return *branch_value;
    }
  
+   std::unique_ptr<Expr> &get_scrutinee_expr_ptr ()
+   {
+     rust_assert (branch_value != nullptr);
+     return branch_value;
+   }
+ 
    const std::vector<MatchCase> &get_match_cases () const { return match_arms; }
    std::vector<MatchCase> &get_match_cases () { return match_arms; }
  
*************** struct InlineAsmTemplatePiece
*** 5494,5499 ****
--- 5722,5729 ----
  
  struct TupleClobber
  {
+   TupleClobber (std::string symbol, location_t loc) : symbol (symbol), loc (loc)
+   {}
    // as gccrs still doesn't contain a symbol class I have put them as strings
    std::string symbol;
    location_t loc;
*************** public:
*** 5667,5672 ****
--- 5897,5906 ----
    }
  
    std::vector<TupleTemplateStr> &get_templates () { return templates; }
+   const std::vector<TupleTemplateStr> &get_templates () const
+   {
+     return templates;
+   }
  
    Expr::Kind get_expr_kind () const override
    {
*************** public:
*** 5685,5693 ****
--- 5919,5930 ----
    void set_outputs (std::vector<LlvmOperand> operands) { outputs = operands; }
  
    std::vector<LlvmOperand> &get_inputs () { return inputs; }
+   const std::vector<LlvmOperand> &get_inputs () const { return inputs; }
    std::vector<LlvmOperand> &get_outputs () { return outputs; }
+   const std::vector<LlvmOperand> &get_outputs () const { return outputs; }
  
    std::vector<TupleClobber> &get_clobbers () { return clobbers; }
+   const std::vector<TupleClobber> &get_clobbers () const { return clobbers; }
  };
  
  } // namespace AST
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-expression-yeast.cc gcc-16-20251102/gcc/rust/ast/rust-expression-yeast.cc
*** gcc-16-20251026/gcc/rust/ast/rust-expression-yeast.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-expression-yeast.cc	Sun Nov  2 22:32:23 2025
***************
*** 21,30 ****
  #include "rust-desugar-question-mark.h"
  #include "rust-desugar-try-block.h"
  #include "rust-desugar-for-loops.h"
- #include "rust-ast-full.h"
  #include "rust-desugar-while-let.h"
  #include "rust-expr.h"
- #include "rust-stmt.h"
  
  namespace Rust {
  namespace AST {
--- 21,28 ----
*************** namespace AST {
*** 32,38 ****
  void
  ExpressionYeast::go (AST::Crate &crate)
  {
!   DefaultASTVisitor::visit (crate);
  }
  
  void
--- 30,36 ----
  void
  ExpressionYeast::go (AST::Crate &crate)
  {
!   PointerVisitor::visit (crate);
  }
  
  void
*************** ExpressionYeast::dispatch_loops (std::un
*** 54,60 ****
  }
  
  void
! ExpressionYeast::dispatch (std::unique_ptr<Expr> &expr)
  {
    switch (expr->get_expr_kind ())
      {
--- 52,58 ----
  }
  
  void
! ExpressionYeast::reseat (std::unique_ptr<Expr> &expr)
  {
    switch (expr->get_expr_kind ())
      {
*************** ExpressionYeast::dispatch (std::unique_p
*** 71,117 ****
      default:
        break;
      }
- }
- 
- void
- ExpressionYeast::visit (ExprStmt &stmt)
- {
-   dispatch (stmt.get_expr_ptr ());
  
!   DefaultASTVisitor::visit (stmt);
! }
! 
! void
! ExpressionYeast::visit (CallExpr &call)
! {
!   dispatch (call.get_function_expr_ptr ());
! 
!   for (auto &arg : call.get_params ())
!     dispatch (arg);
! 
!   DefaultASTVisitor::visit (call);
! }
! 
! void
! ExpressionYeast::visit (BlockExpr &block)
! {
!   for (auto &stmt : block.get_statements ())
!     if (stmt->get_stmt_kind () == Stmt::Kind::Expr)
!       dispatch (static_cast<ExprStmt &> (*stmt).get_expr_ptr ());
! 
!   if (block.has_tail_expr ())
!     dispatch (block.get_tail_expr_ptr ());
! 
!   DefaultASTVisitor::visit (block);
! }
! 
! void
! ExpressionYeast::visit (LetStmt &stmt)
! {
!   if (stmt.has_init_expr ())
!     dispatch (stmt.get_init_expr_ptr ());
! 
!   DefaultASTVisitor::visit (stmt);
  }
  
  } // namespace AST
--- 69,76 ----
      default:
        break;
      }
  
!   visit (expr);
  }
  
  } // namespace AST
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-expression-yeast.h gcc-16-20251102/gcc/rust/ast/rust-expression-yeast.h
*** gcc-16-20251026/gcc/rust/ast/rust-expression-yeast.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-expression-yeast.h	Sun Nov  2 22:32:23 2025
***************
*** 19,25 ****
  #ifndef RUST_EXPRESSION_YEAST
  #define RUST_EXPRESSION_YEAST
  
! #include "rust-ast-visitor.h"
  #include "rust-ast.h"
  #include "rust-desugar-question-mark.h"
  
--- 19,25 ----
  #ifndef RUST_EXPRESSION_YEAST
  #define RUST_EXPRESSION_YEAST
  
! #include "rust-ast-pointer-visitor.h"
  #include "rust-ast.h"
  #include "rust-desugar-question-mark.h"
  
*************** namespace AST {
*** 28,49 ****
  
  // This visitor takes care of all the expression desugars: try-blocks,
  // error-propagation, etc.
! class ExpressionYeast : public AST::DefaultASTVisitor
  {
!   using AST::DefaultASTVisitor::visit;
  
  public:
    void go (AST::Crate &);
  
  private:
    // Dispatch to the proper desugar
!   void dispatch (std::unique_ptr<Expr> &expr);
!   void dispatch_loops (std::unique_ptr<Expr> &loop_expr);
  
!   void visit (AST::ExprStmt &) override;
!   void visit (AST::CallExpr &) override;
!   void visit (AST::LetStmt &) override;
!   void visit (AST::BlockExpr &) override;
  };
  
  } // namespace AST
--- 28,46 ----
  
  // This visitor takes care of all the expression desugars: try-blocks,
  // error-propagation, etc.
! class ExpressionYeast : public AST::PointerVisitor
  {
!   using AST::PointerVisitor::reseat;
!   using AST::PointerVisitor::visit;
  
  public:
    void go (AST::Crate &);
  
  private:
    // Dispatch to the proper desugar
!   void reseat (std::unique_ptr<Expr> &expr) override;
  
!   void dispatch_loops (std::unique_ptr<Expr> &loop_expr);
  };
  
  } // namespace AST
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-fmt.cc gcc-16-20251102/gcc/rust/ast/rust-fmt.cc
*** gcc-16-20251026/gcc/rust/ast/rust-fmt.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-fmt.cc	Sun Nov  2 22:32:23 2025
*************** Pieces
*** 32,72 ****
  Pieces::collect (const std::string &to_parse, bool append_newline,
  		 ffi::ParseMode parse_mode)
  {
!   auto handle
!     = ffi::collect_pieces (to_parse.c_str (), append_newline, parse_mode);
! 
!   // this performs multiple copies, can we avoid them maybe?
!   // TODO: Instead of just creating a vec of, basically, `ffi::Piece`s, we
!   // should transform them into the proper C++ type which we can work with. so
!   // transform all the strings into C++ strings? all the Option<T> into
!   // tl::optional<T>?
!   auto pieces_vector = std::vector<ffi::Piece> (handle.piece_slice.base_ptr,
! 						handle.piece_slice.base_ptr
! 						  + handle.piece_slice.len);
! 
!   return Pieces (handle, std::move (pieces_vector));
! }
! 
! Pieces::~Pieces () { ffi::destroy_pieces (handle); }
! 
! Pieces::Pieces (const Pieces &other) : pieces_vector (other.pieces_vector)
! {
!   handle = ffi::clone_pieces (other.handle);
! }
! 
! Pieces &
! Pieces::operator= (const Pieces &other)
! {
!   handle = ffi::clone_pieces (other.handle);
!   pieces_vector = other.pieces_vector;
! 
!   return *this;
  }
  
- Pieces::Pieces (Pieces &&other)
-   : pieces_vector (std::move (other.pieces_vector)),
-     handle (clone_pieces (other.handle))
- {}
- 
  } // namespace Fmt
  } // namespace Rust
--- 32,42 ----
  Pieces::collect (const std::string &to_parse, bool append_newline,
  		 ffi::ParseMode parse_mode)
  {
!   Pieces ret (to_parse, ffi::FFIVec<ffi::Piece> ());
!   ret.data->second = ffi::collect_pieces (ffi::RustHamster (ret.data->first),
! 					  append_newline, parse_mode);
!   return ret;
  }
  
  } // namespace Fmt
  } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-fmt.h gcc-16-20251102/gcc/rust/ast/rust-fmt.h
*** gcc-16-20251026/gcc/rust/ast/rust-fmt.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-fmt.h	Sun Nov  2 22:32:23 2025
***************
*** 20,39 ****
  #define RUST_FMT_H
  
  #include "rust-system.h"
! 
! // FIXME: How to encode Option?
  
  namespace Rust {
  namespace Fmt {
  
  namespace ffi {
  
  struct RustHamster
  {
    const char *ptr;
    size_t len;
  
    std::string to_string () const;
  };
  
  /// Enum of alignments which are supported.
--- 20,190 ----
  #define RUST_FMT_H
  
  #include "rust-system.h"
! #include "optional.h"
  
  namespace Rust {
  namespace Fmt {
  
  namespace ffi {
  
+ extern "C" {
+ 
+ unsigned char *rust_ffi_alloc (size_t count, size_t elem_size, size_t align);
+ 
+ void rust_ffi_dealloc (unsigned char *data, size_t count, size_t elem_size,
+ 		       size_t align);
+ 
+ } // extern "C"
+ 
+ template <typename T> class FFIVec
+ {
+   T *data;
+   size_t len;
+   size_t cap;
+ 
+ public:
+   FFIVec () : data ((T *) alignof (T)), len (0), cap (0) {}
+ 
+   FFIVec (const FFIVec &) = delete;
+   FFIVec &operator= (const FFIVec &) = delete;
+ 
+   FFIVec (FFIVec &&other) : data (other.data), len (other.len), cap (other.cap)
+   {
+     other.data = (T *) alignof (T);
+     other.len = 0;
+     other.cap = 0;
+   }
+ 
+   FFIVec &operator= (FFIVec &&other)
+   {
+     this->~FFIVec ();
+     new (this) FFIVec (std::move (other));
+     return *this;
+   }
+ 
+   ~FFIVec ()
+   {
+     // T can't be zero-sized
+     if (cap)
+       rust_ffi_dealloc ((unsigned char *) data, cap, sizeof (T), alignof (T));
+   }
+ 
+   size_t size () const { return len; }
+ 
+   const T &operator[] (size_t idx) const
+   {
+     rust_assert (idx <= len);
+     return data[idx];
+   }
+ 
+   T *begin () { return data; }
+   const T *begin () const { return data; }
+   T *end () { return data + len; }
+   const T *end () const { return data + len; }
+ };
+ 
+ // https://github.com/rust-lang/rfcs/blob/master/text/2195-really-tagged-unions.md
+ template <typename T,
+ 	  typename =
+ 	    typename std::enable_if<std::is_standard_layout<T>::value>::type>
+ class FFIOpt
+ {
+ public:
+   template <typename U>
+   FFIOpt (U &&val) : some{Some::KIND, std::forward<U> (val)}
+   {}
+ 
+   FFIOpt () : none{None::KIND} {}
+ 
+   FFIOpt (const FFIOpt &other)
+   {
+     if (other.has_value ())
+       new (&some) Some{Some::KIND, other.some.val};
+     else
+       new (&none) None{None::KIND};
+   }
+ 
+   FFIOpt (FFIOpt &&other)
+   {
+     if (other.has_value ())
+       new (&some) Some{Some::KIND, std::move (other.some.val)};
+     else
+       new (&none) None{None::KIND};
+   }
+ 
+   ~FFIOpt ()
+   {
+     if (has_value ())
+       some.~Some ();
+     else
+       none.~None ();
+   }
+ 
+   FFIOpt &operator= (const FFIOpt &other)
+   {
+     this->~FFIOpt ();
+     new (this) FFIOpt (other);
+     return *this;
+   }
+ 
+   FFIOpt &operator= (FFIOpt &&other)
+   {
+     this->~FFIOpt ();
+     new (this) FFIOpt (std::move (other));
+     return *this;
+   }
+ 
+   tl::optional<std::reference_wrapper<T>> get_opt ()
+   {
+     if (has_value ())
+       return std::ref (some.val);
+     else
+       return tl::nullopt;
+   }
+ 
+   tl::optional<std::reference_wrapper<const T>> get_opt () const
+   {
+     if (has_value ())
+       return std::ref (some.val);
+     else
+       return tl::nullopt;
+   }
+ 
+   bool has_value () const { return some.kind == Some::KIND; }
+ 
+   operator bool () const { return has_value (); }
+ 
+ private:
+   struct Some
+   {
+     static constexpr uint8_t KIND = 0;
+     uint8_t kind;
+     T val;
+   };
+ 
+   struct None
+   {
+     static constexpr uint8_t KIND = 1;
+     uint8_t kind;
+   };
+ 
+   union
+   {
+     Some some;
+     None none;
+   };
+ };
+ 
  struct RustHamster
  {
    const char *ptr;
    size_t len;
  
    std::string to_string () const;
+ 
+   explicit RustHamster (const std::string &str)
+     : ptr (str.data ()), len (str.size ())
+   {}
  };
  
  /// Enum of alignments which are supported.
*************** struct Count
*** 166,198 ****
  struct FormatSpec
  {
    /// Optionally specified character to fill alignment with.
!   const uint32_t *fill;
    /// Span of the optionally specified fill character.
!   const InnerSpan *fill_span;
    /// Optionally specified alignment.
    Alignment align;
    /// The `+` or `-` flag.
!   const Sign *sign;
    /// The `#` flag.
    bool alternate;
    /// The `0` flag.
    bool zero_pad;
    /// The `x` or `X` flag. (Only for `Debug`.)
!   const DebugHex *debug_hex;
    /// The integer precision to use.
    Count precision;
    /// The span of the precision formatting flag (for diagnostics).
!   const InnerSpan *precision_span;
    /// The string width requested for the resulting format.
    Count width;
    /// The span of the width formatting flag (for diagnostics).
!   const InnerSpan *width_span;
    /// The descriptor string representing the name of the format desired for
    /// this argument, this can be empty or any number of characters, although
    /// it is required to be one word.
    RustHamster ty;
    /// The span of the descriptor string (for diagnostics).
!   const InnerSpan *ty_span;
  };
  
  /// Representation of an argument specification.
--- 317,349 ----
  struct FormatSpec
  {
    /// Optionally specified character to fill alignment with.
!   FFIOpt<uint32_t> fill;
    /// Span of the optionally specified fill character.
!   FFIOpt<InnerSpan> fill_span;
    /// Optionally specified alignment.
    Alignment align;
    /// The `+` or `-` flag.
!   FFIOpt<Sign> sign;
    /// The `#` flag.
    bool alternate;
    /// The `0` flag.
    bool zero_pad;
    /// The `x` or `X` flag. (Only for `Debug`.)
!   FFIOpt<DebugHex> debug_hex;
    /// The integer precision to use.
    Count precision;
    /// The span of the precision formatting flag (for diagnostics).
!   FFIOpt<InnerSpan> precision_span;
    /// The string width requested for the resulting format.
    Count width;
    /// The span of the width formatting flag (for diagnostics).
!   FFIOpt<InnerSpan> width_span;
    /// The descriptor string representing the name of the format desired for
    /// this argument, this can be empty or any number of characters, although
    /// it is required to be one word.
    RustHamster ty;
    /// The span of the descriptor string (for diagnostics).
!   FFIOpt<InnerSpan> ty_span;
  };
  
  /// Representation of an argument specification.
*************** struct Piece
*** 238,263 ****
    };
  };
  
- struct PieceSlice
- {
-   const Piece *base_ptr;
-   size_t len;
-   size_t cap;
- };
- 
- struct RustString
- {
-   const unsigned char *ptr;
-   size_t len;
-   size_t cap;
- };
- 
- struct FormatArgsHandle
- {
-   PieceSlice piece_slice;
-   RustString rust_string;
- };
- 
  enum ParseMode
  {
    Format = 0,
--- 389,394 ----
*************** enum ParseMode
*** 266,277 ****
  
  extern "C" {
  
! FormatArgsHandle collect_pieces (const char *input, bool append_newline,
! 				 ParseMode parse_mode);
! 
! FormatArgsHandle clone_pieces (const FormatArgsHandle &);
  
! void destroy_pieces (FormatArgsHandle);
  
  } // extern "C"
  
--- 397,406 ----
  
  extern "C" {
  
! FFIVec<Piece> collect_pieces (RustHamster input, bool append_newline,
! 			      ParseMode parse_mode);
  
! FFIVec<Piece> clone_pieces (const FFIVec<Piece> &);
  
  } // extern "C"
  
*************** struct Pieces
*** 281,313 ****
  {
    static Pieces collect (const std::string &to_parse, bool append_newline,
  			 ffi::ParseMode parse_mode);
-   ~Pieces ();
  
!   Pieces (const Pieces &other);
!   Pieces &operator= (const Pieces &other);
! 
!   Pieces (Pieces &&other);
! 
!   const std::vector<ffi::Piece> &get_pieces () const { return pieces_vector; }
! 
!   // {
!   //   slice = clone_pieces (&other.slice);
!   //   to_parse = other.to_parse;
! 
!   //   return *this;
!   // }
  
  private:
!   Pieces (ffi::FormatArgsHandle handle, std::vector<ffi::Piece> &&pieces_vector)
!     : pieces_vector (std::move (pieces_vector)), handle (handle)
    {}
  
!   std::vector<ffi::Piece> pieces_vector;
! 
!   // this memory is held for FFI reasons - it needs to be released and cloned
!   // precisely, so try to not access it/modify it if possible. you should
!   // instead work with `pieces_vector`
!   ffi::FormatArgsHandle handle;
  };
  
  } // namespace Fmt
--- 410,429 ----
  {
    static Pieces collect (const std::string &to_parse, bool append_newline,
  			 ffi::ParseMode parse_mode);
  
!   const ffi::FFIVec<ffi::Piece> &get_pieces () const { return data->second; }
  
  private:
!   Pieces (std::string str, ffi::FFIVec<ffi::Piece> pieces)
!     : data (
!       std::make_shared<decltype (data)::element_type> (std::move (str),
! 						       std::move (pieces)))
    {}
  
!   // makes copying simpler
!   // also, we'd need to keep the parsed string in a shared_ptr anyways
!   // since we store pointers into the parsed string
!   std::shared_ptr<std::pair<std::string, ffi::FFIVec<ffi::Piece>>> data;
  };
  
  } // namespace Fmt
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-item.h gcc-16-20251102/gcc/rust/ast/rust-item.h
*** gcc-16-20251026/gcc/rust/ast/rust-item.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-item.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 631,636 ****
--- 631,642 ----
      return *param_name;
    }
  
+   std::unique_ptr<Pattern> &get_pattern_ptr ()
+   {
+     rust_assert (param_name != nullptr);
+     return param_name;
+   }
+ 
    const Pattern &get_pattern () const
    {
      rust_assert (param_name != nullptr);
*************** public:
*** 714,719 ****
--- 720,731 ----
      return *param_name;
    }
  
+   std::unique_ptr<Pattern> &get_pattern_ptr ()
+   {
+     rust_assert (param_name != nullptr);
+     return param_name;
+   }
+ 
    bool has_name () const { return param_name != nullptr; }
  
    // TODO: is this better? Or is a "vis_block" better?
*************** public:
*** 1567,1572 ****
--- 1579,1587 ----
  
    location_t get_locus () const override final { return locus; }
  
+   // needed to override AssociatedItem::get_node_id
+   NodeId get_node_id () const override final { return VisItem::get_node_id (); }
+ 
    void accept_vis (ASTVisitor &vis) override;
  
    // Invalid if existing type is null, so base stripping on that.
*************** public:
*** 1595,1600 ****
--- 1610,1621 ----
      return *existing_type;
    }
  
+   std::unique_ptr<Type> &get_type_aliased_ptr ()
+   {
+     rust_assert (existing_type != nullptr);
+     return existing_type;
+   }
+ 
    Identifier get_new_type_name () const { return new_type_name; }
  
    Item::Kind get_item_kind () const override { return Item::Kind::TypeAlias; }
*************** public:
*** 2515,2523 ****
  
    location_t get_locus () const override final { return locus; }
  
    void accept_vis (ASTVisitor &vis) override;
  
!   // Invalid if type or expression are null, so base stripping on that.
    void mark_for_strip () override
    {
      type = nullptr;
--- 2536,2547 ----
  
    location_t get_locus () const override final { return locus; }
  
+   // needed to override AssociatedItem::get_node_id
+   NodeId get_node_id () const override final { return VisItem::get_node_id (); }
+ 
    void accept_vis (ASTVisitor &vis) override;
  
!   // Invalid if type and expression are null, so base stripping on that.
    void mark_for_strip () override
    {
      type = nullptr;
*************** public:
*** 2528,2534 ****
      return type == nullptr && const_expr == nullptr;
    }
  
!   bool has_expr () { return const_expr != nullptr; }
  
    // TODO: is this better? Or is a "vis_block" better?
    Expr &get_expr ()
--- 2552,2558 ----
      return type == nullptr && const_expr == nullptr;
    }
  
!   bool has_expr () const { return const_expr != nullptr; }
  
    // TODO: is this better? Or is a "vis_block" better?
    Expr &get_expr ()
*************** protected:
*** 2695,2817 ****
    }
  };
  
- // Constant item within traits
- class TraitItemConst : public TraitItem
- {
-   std::vector<Attribute> outer_attrs;
-   Identifier name;
-   std::unique_ptr<Type> type;
- 
-   // bool has_expression;
-   std::unique_ptr<Expr> expr;
- 
- public:
-   // Whether the constant item has an associated expression.
-   bool has_expression () const { return expr != nullptr; }
- 
-   TraitItemConst (Identifier name, std::unique_ptr<Type> type,
- 		  std::unique_ptr<Expr> expr,
- 		  std::vector<Attribute> outer_attrs, location_t locus)
-     : TraitItem (locus), outer_attrs (std::move (outer_attrs)),
-       name (std::move (name)), type (std::move (type)), expr (std::move (expr))
-   {}
- 
-   // Copy constructor with clones
-   TraitItemConst (TraitItemConst const &other)
-     : TraitItem (other.locus), outer_attrs (other.outer_attrs),
-       name (other.name)
-   {
-     node_id = other.node_id;
- 
-     // guard to prevent null dereference
-     if (other.expr != nullptr)
-       expr = other.expr->clone_expr ();
- 
-     // guard to prevent null dereference (only for error state)
-     if (other.type != nullptr)
-       type = other.type->clone_type ();
-   }
- 
-   // Overloaded assignment operator to clone
-   TraitItemConst &operator= (TraitItemConst const &other)
-   {
-     TraitItem::operator= (other);
-     outer_attrs = other.outer_attrs;
-     name = other.name;
-     locus = other.locus;
-     node_id = other.node_id;
- 
-     // guard to prevent null dereference
-     if (other.expr != nullptr)
-       expr = other.expr->clone_expr ();
-     else
-       expr = nullptr;
- 
-     // guard to prevent null dereference (only for error state)
-     if (other.type != nullptr)
-       type = other.type->clone_type ();
-     else
-       type = nullptr;
- 
-     return *this;
-   }
- 
-   // move constructors
-   TraitItemConst (TraitItemConst &&other) = default;
-   TraitItemConst &operator= (TraitItemConst &&other) = default;
- 
-   std::string as_string () const override;
- 
-   location_t get_locus () const override { return locus; }
- 
-   void accept_vis (ASTVisitor &vis) override;
- 
-   // Invalid if type is null, so base stripping on that.
-   void mark_for_strip () override { type = nullptr; }
-   bool is_marked_for_strip () const override { return type == nullptr; }
- 
-   // TODO: this mutable getter seems really dodgy. Think up better way.
-   std::vector<Attribute> &get_outer_attrs () { return outer_attrs; }
-   const std::vector<Attribute> &get_outer_attrs () const { return outer_attrs; }
- 
-   bool has_expr () const { return expr != nullptr; }
- 
-   // TODO: is this better? Or is a "vis_block" better?
-   Expr &get_expr ()
-   {
-     rust_assert (has_expr ());
-     return *expr;
-   }
- 
-   std::unique_ptr<Expr> &get_expr_ptr ()
-   {
-     rust_assert (has_expr ());
-     return expr;
-   }
- 
-   // TODO: is this better? Or is a "vis_block" better?
-   Type &get_type ()
-   {
-     rust_assert (type != nullptr);
-     return *type;
-   }
- 
-   std::unique_ptr<Type> &get_type_ptr ()
-   {
-     rust_assert (type != nullptr);
-     return type;
-   }
- 
-   Identifier get_identifier () const { return name; }
- 
- protected:
-   // Clone function implementation as (not pure) virtual method
-   TraitItemConst *clone_associated_item_impl () const override
-   {
-     return new TraitItemConst (*this);
-   }
- };
- 
  // Type items within traits
  class TraitItemType : public TraitItem
  {
--- 2719,2724 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-path.cc gcc-16-20251102/gcc/rust/ast/rust-path.cc
*** gcc-16-20251026/gcc/rust/ast/rust-path.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-path.cc	Sun Nov  2 22:32:23 2025
*************** Path::convert_to_simple_path (bool with_
*** 167,180 ****
    for (const auto &segment : segments)
      {
        // return empty path if doesn't meet simple path segment requirements
!       if (segment.is_error () || segment.has_generic_args ()
! 	  || segment.as_string () == "Self")
  	return SimplePath::create_empty ();
  
        // create segment and add to vector
        std::string segment_str = segment.as_string ();
!       simple_segments.push_back (
! 	SimplePathSegment (std::move (segment_str), segment.get_locus ()));
      }
  
    // kind of a HACK to get locus depending on opening scope resolution
--- 167,179 ----
    for (const auto &segment : segments)
      {
        // return empty path if doesn't meet simple path segment requirements
!       if (segment.is_error () || segment.has_generic_args ())
  	return SimplePath::create_empty ();
  
        // create segment and add to vector
        std::string segment_str = segment.as_string ();
!       simple_segments.emplace_back (std::move (segment_str),
! 				    segment.get_locus ());
      }
  
    // kind of a HACK to get locus depending on opening scope resolution
*************** TypePath::as_simple_path () const
*** 258,265 ****
  
        // create segment and add to vector
        std::string segment_str = segment->as_string ();
!       simple_segments.push_back (
! 	SimplePathSegment (std::move (segment_str), segment->get_locus ()));
      }
  
    return SimplePath (std::move (simple_segments), has_opening_scope_resolution,
--- 257,264 ----
  
        // create segment and add to vector
        std::string segment_str = segment->as_string ();
!       simple_segments.emplace_back (std::move (segment_str),
! 				    segment->get_locus ());
      }
  
    return SimplePath (std::move (simple_segments), has_opening_scope_resolution,
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-path.h gcc-16-20251102/gcc/rust/ast/rust-path.h
*** gcc-16-20251026/gcc/rust/ast/rust-path.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-path.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 377,382 ****
--- 377,389 ----
      return *type;
    }
  
+   std::unique_ptr<AST::Type> &get_type_ptr ()
+   {
+     rust_assert (has_type ());
+ 
+     return type;
+   }
+ 
    GenericArg &get_default_value_unchecked ()
    {
      rust_assert (has_default_value ());
*************** public:
*** 448,456 ****
      generic_args.clear ();
      generic_args.reserve (other.generic_args.size ());
      for (const auto &arg : other.generic_args)
!       {
! 	generic_args.push_back (GenericArg (arg));
!       }
    }
  
    ~GenericArgs () = default;
--- 455,461 ----
      generic_args.clear ();
      generic_args.reserve (other.generic_args.size ());
      for (const auto &arg : other.generic_args)
!       generic_args.emplace_back (arg);
    }
  
    ~GenericArgs () = default;
*************** public:
*** 465,473 ****
      generic_args.clear ();
      generic_args.reserve (other.generic_args.size ());
      for (const auto &arg : other.generic_args)
!       {
! 	generic_args.push_back (GenericArg (arg));
!       }
  
      return *this;
    }
--- 470,476 ----
      generic_args.clear ();
      generic_args.reserve (other.generic_args.size ());
      for (const auto &arg : other.generic_args)
!       generic_args.emplace_back (arg);
  
      return *this;
    }
*************** public:
*** 1252,1258 ****
    TraitBound *to_trait_bound (bool in_parens) const override;
  
    location_t get_locus () const override final { return locus; }
!   NodeId get_node_id () const { return node_id; }
  
    void mark_for_strip () override {}
    bool is_marked_for_strip () const override { return false; }
--- 1255,1261 ----
    TraitBound *to_trait_bound (bool in_parens) const override;
  
    location_t get_locus () const override final { return locus; }
!   NodeId get_node_id () const override { return node_id; }
  
    void mark_for_strip () override {}
    bool is_marked_for_strip () const override { return false; }
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-pattern.cc gcc-16-20251102/gcc/rust/ast/rust-pattern.cc
*** gcc-16-20251026/gcc/rust/ast/rust-pattern.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-pattern.cc	Sun Nov  2 22:32:23 2025
*************** StructPatternElements::as_string () cons
*** 186,193 ****
  	str += "\n   " + field->as_string ();
      }
  
!   str += "\n  Etc: ";
!   if (has_struct_pattern_etc)
      str += "true";
    else
      str += "false";
--- 186,193 ----
  	str += "\n   " + field->as_string ();
      }
  
!   str += "\n  Has rest: ";
!   if (has_rest_pattern)
      str += "true";
    else
      str += "false";
*************** StructPattern::as_string () const
*** 212,218 ****
  }
  
  std::string
! TupleStructItemsNoRange::as_string () const
  {
    std::string str;
  
--- 212,218 ----
  }
  
  std::string
! TupleStructItemsNoRest::as_string () const
  {
    std::string str;
  
*************** TupleStructItemsNoRange::as_string () co
*** 223,229 ****
  }
  
  std::string
! TupleStructItemsRange::as_string () const
  {
    std::string str ("\n  Lower patterns: ");
  
--- 223,229 ----
  }
  
  std::string
! TupleStructItemsHasRest::as_string () const
  {
    std::string str ("\n  Lower patterns: ");
  
*************** TupleStructPattern::as_string () const
*** 264,270 ****
  }
  
  std::string
! TuplePatternItemsMultiple::as_string () const
  {
    std::string str;
  
--- 264,270 ----
  }
  
  std::string
! TuplePatternItemsNoRest::as_string () const
  {
    std::string str;
  
*************** TuplePatternItemsMultiple::as_string ()
*** 275,281 ****
  }
  
  std::string
! TuplePatternItemsRanged::as_string () const
  {
    std::string str;
  
--- 275,281 ----
  }
  
  std::string
! TuplePatternItemsHasRest::as_string () const
  {
    std::string str;
  
*************** SlicePattern::accept_vis (ASTVisitor &vi
*** 421,427 ****
  }
  
  void
! TuplePatternItemsRanged::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
--- 421,427 ----
  }
  
  void
! TuplePatternItemsHasRest::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
*************** TuplePattern::accept_vis (ASTVisitor &vi
*** 433,439 ****
  }
  
  void
! TuplePatternItemsMultiple::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
--- 433,439 ----
  }
  
  void
! TuplePatternItemsNoRest::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
*************** StructPattern::accept_vis (ASTVisitor &v
*** 517,529 ****
  }
  
  void
! TupleStructItemsNoRange::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! TupleStructItemsRange::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
--- 517,529 ----
  }
  
  void
! TupleStructItemsNoRest::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! TupleStructItemsHasRest::accept_vis (ASTVisitor &vis)
  {
    vis.visit (*this);
  }
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-pattern.h gcc-16-20251102/gcc/rust/ast/rust-pattern.h
*** gcc-16-20251026/gcc/rust/ast/rust-pattern.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-pattern.h	Sun Nov  2 22:32:23 2025
***************
*** 20,25 ****
--- 20,26 ----
  #define RUST_AST_PATTERN_H
  
  #include "rust-ast.h"
+ #include "rust-path.h"
  
  namespace Rust {
  namespace AST {
*************** public:
*** 143,148 ****
--- 144,155 ----
      return *subpattern;
    }
  
+   std::unique_ptr<Pattern> &get_subpattern_ptr ()
+   {
+     rust_assert (has_subpattern ());
+     return subpattern;
+   }
+ 
    Identifier get_ident () const { return variable_ident; }
  
    bool get_is_mut () const { return is_mut; }
*************** public:
*** 518,523 ****
--- 525,536 ----
      return *pattern;
    }
  
+   std::unique_ptr<Pattern> &get_referenced_pattern_ptr ()
+   {
+     rust_assert (pattern != nullptr);
+     return pattern;
+   }
+ 
    bool is_double_reference () const { return has_two_amps; }
  
    bool get_is_mut () const { return is_mut; }
*************** public:
*** 681,686 ****
--- 694,705 ----
      return *tuple_pattern;
    }
  
+   std::unique_ptr<Pattern> &get_index_pattern_ptr ()
+   {
+     rust_assert (tuple_pattern != nullptr);
+     return tuple_pattern;
+   }
+ 
    ItemType get_item_type () const override final { return ItemType::TUPLE_PAT; }
  
  protected:
*************** public:
*** 761,766 ****
--- 780,791 ----
      return *ident_pattern;
    }
  
+   std::unique_ptr<Pattern> &get_ident_pattern_ptr ()
+   {
+     rust_assert (ident_pattern != nullptr);
+     return ident_pattern;
+   }
+ 
    ItemType get_item_type () const override final { return ItemType::IDENT_PAT; }
  
  protected:
*************** class StructPatternElements
*** 818,824 ****
    // bool has_struct_pattern_fields;
    std::vector<std::unique_ptr<StructPatternField>> fields;
  
!   bool has_struct_pattern_etc;
    std::vector<Attribute> struct_pattern_etc_attrs;
    // StructPatternEtc etc;
  
--- 843,849 ----
    // bool has_struct_pattern_fields;
    std::vector<std::unique_ptr<StructPatternField>> fields;
  
!   bool has_rest_pattern;
    std::vector<Attribute> struct_pattern_etc_attrs;
    // StructPatternEtc etc;
  
*************** public:
*** 834,862 ****
     * no etc). */
    bool is_empty () const
    {
!     return !has_struct_pattern_fields () && !has_struct_pattern_etc;
    }
  
!   bool has_etc () const { return has_struct_pattern_etc; }
  
    // Constructor for StructPatternElements with both (potentially)
    StructPatternElements (
      std::vector<std::unique_ptr<StructPatternField>> fields,
      std::vector<Attribute> etc_attrs)
!     : fields (std::move (fields)), has_struct_pattern_etc (true),
        struct_pattern_etc_attrs (std::move (etc_attrs))
    {}
  
    // Constructor for StructPatternElements with no StructPatternEtc
    StructPatternElements (
      std::vector<std::unique_ptr<StructPatternField>> fields)
!     : fields (std::move (fields)), has_struct_pattern_etc (false),
        struct_pattern_etc_attrs ()
    {}
  
    // Copy constructor with vector clone
    StructPatternElements (StructPatternElements const &other)
!     : has_struct_pattern_etc (other.has_struct_pattern_etc),
        struct_pattern_etc_attrs (other.struct_pattern_etc_attrs)
    {
      fields.reserve (other.fields.size ());
--- 859,887 ----
     * no etc). */
    bool is_empty () const
    {
!     return !has_struct_pattern_fields () && !has_rest_pattern;
    }
  
!   bool has_rest () const { return has_rest_pattern; }
  
    // Constructor for StructPatternElements with both (potentially)
    StructPatternElements (
      std::vector<std::unique_ptr<StructPatternField>> fields,
      std::vector<Attribute> etc_attrs)
!     : fields (std::move (fields)), has_rest_pattern (true),
        struct_pattern_etc_attrs (std::move (etc_attrs))
    {}
  
    // Constructor for StructPatternElements with no StructPatternEtc
    StructPatternElements (
      std::vector<std::unique_ptr<StructPatternField>> fields)
!     : fields (std::move (fields)), has_rest_pattern (false),
        struct_pattern_etc_attrs ()
    {}
  
    // Copy constructor with vector clone
    StructPatternElements (StructPatternElements const &other)
!     : has_rest_pattern (other.has_rest_pattern),
        struct_pattern_etc_attrs (other.struct_pattern_etc_attrs)
    {
      fields.reserve (other.fields.size ());
*************** public:
*** 868,874 ****
    StructPatternElements &operator= (StructPatternElements const &other)
    {
      struct_pattern_etc_attrs = other.struct_pattern_etc_attrs;
!     has_struct_pattern_etc = other.has_struct_pattern_etc;
  
      fields.clear ();
      fields.reserve (other.fields.size ());
--- 893,899 ----
    StructPatternElements &operator= (StructPatternElements const &other)
    {
      struct_pattern_etc_attrs = other.struct_pattern_etc_attrs;
!     has_rest_pattern = other.has_rest_pattern;
  
      fields.clear ();
      fields.reserve (other.fields.size ());
*************** public:
*** 913,919 ****
  
    void strip_etc ()
    {
!     has_struct_pattern_etc = false;
      struct_pattern_etc_attrs.clear ();
      struct_pattern_etc_attrs.shrink_to_fit ();
    }
--- 938,944 ----
  
    void strip_etc ()
    {
!     has_rest_pattern = false;
      struct_pattern_etc_attrs.clear ();
      struct_pattern_etc_attrs.shrink_to_fit ();
    }
*************** protected:
*** 975,1023 ****
    }
  };
  
! // Base abstract class for patterns used in TupleStructPattern
! class TupleStructItems
  {
  public:
    enum ItemType
    {
!     RANGE,
!     NO_RANGE
    };
  
!   virtual ~TupleStructItems () {}
  
    // TODO: should this store location data?
  
    // Unique pointer custom clone function
!   std::unique_ptr<TupleStructItems> clone_tuple_struct_items () const
    {
!     return std::unique_ptr<TupleStructItems> (clone_tuple_struct_items_impl ());
    }
  
    virtual std::string as_string () const = 0;
! 
    virtual void accept_vis (ASTVisitor &vis) = 0;
  
!   virtual ItemType get_item_type () const = 0;
  
  protected:
    // pure virtual clone implementation
!   virtual TupleStructItems *clone_tuple_struct_items_impl () const = 0;
  };
  
  // Class for non-ranged tuple struct pattern patterns
! class TupleStructItemsNoRange : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TupleStructItemsNoRange (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsNoRange (TupleStructItemsNoRange const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
--- 1000,1061 ----
    }
  };
  
! // Base abstract class for TupleStructItems, TuplePatternItems &
! // SlicePatternItems
! class PatternItems
  {
  public:
    enum ItemType
    {
!     NO_REST,
!     HAS_REST,
    };
  
!   virtual ~PatternItems () {}
  
    // TODO: should this store location data?
  
    // Unique pointer custom clone function
!   std::unique_ptr<PatternItems> clone_pattern_items () const
    {
!     return std::unique_ptr<PatternItems> (clone_pattern_items_impl ());
    }
  
    virtual std::string as_string () const = 0;
!   virtual ItemType get_item_type () const = 0;
    virtual void accept_vis (ASTVisitor &vis) = 0;
  
! protected:
!   virtual PatternItems *clone_pattern_items_impl () const = 0;
! };
! 
! // Base abstract class for patterns used in TupleStructPattern
! class TupleStructItems : public PatternItems
! {
! public:
!   // Unique pointer custom clone function
!   std::unique_ptr<TupleStructItems> clone_tuple_struct_items () const
!   {
!     return std::unique_ptr<TupleStructItems> (clone_pattern_items_impl ());
!   }
  
  protected:
    // pure virtual clone implementation
!   virtual TupleStructItems *clone_pattern_items_impl () const = 0;
  };
  
  // Class for non-ranged tuple struct pattern patterns
! class TupleStructItemsNoRest : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TupleStructItemsNoRest (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsNoRest (TupleStructItemsNoRest const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
*************** public:
*** 1025,1031 ****
    }
  
    // Overloaded assignment operator with vector clone
!   TupleStructItemsNoRange &operator= (TupleStructItemsNoRange const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
--- 1063,1069 ----
    }
  
    // Overloaded assignment operator with vector clone
!   TupleStructItemsNoRest &operator= (TupleStructItemsNoRest const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
*************** public:
*** 1036,1044 ****
    }
  
    // move constructors
!   TupleStructItemsNoRange (TupleStructItemsNoRange &&other) = default;
!   TupleStructItemsNoRange &operator= (TupleStructItemsNoRange &&other)
!     = default;
  
    std::string as_string () const override;
  
--- 1074,1081 ----
    }
  
    // move constructors
!   TupleStructItemsNoRest (TupleStructItemsNoRest &&other) = default;
!   TupleStructItemsNoRest &operator= (TupleStructItemsNoRest &&other) = default;
  
    std::string as_string () const override;
  
*************** public:
*** 1051,1082 ****
      return patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::NO_RANGE; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsNoRange *clone_tuple_struct_items_impl () const override
    {
!     return new TupleStructItemsNoRange (*this);
    }
  };
  
  // Class for ranged tuple struct pattern patterns
! class TupleStructItemsRange : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TupleStructItemsRange (std::vector<std::unique_ptr<Pattern>> lower_patterns,
! 			 std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsRange (TupleStructItemsRange const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
--- 1088,1119 ----
      return patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::NO_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsNoRest *clone_pattern_items_impl () const override
    {
!     return new TupleStructItemsNoRest (*this);
    }
  };
  
  // Class for ranged tuple struct pattern patterns
! class TupleStructItemsHasRest : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TupleStructItemsHasRest (std::vector<std::unique_ptr<Pattern>> lower_patterns,
! 			   std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsHasRest (TupleStructItemsHasRest const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
*************** public:
*** 1088,1094 ****
    }
  
    // Overloaded assignment operator to clone
!   TupleStructItemsRange &operator= (TupleStructItemsRange const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
--- 1125,1131 ----
    }
  
    // Overloaded assignment operator to clone
!   TupleStructItemsHasRest &operator= (TupleStructItemsHasRest const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
*************** public:
*** 1104,1111 ****
    }
  
    // move constructors
!   TupleStructItemsRange (TupleStructItemsRange &&other) = default;
!   TupleStructItemsRange &operator= (TupleStructItemsRange &&other) = default;
  
    std::string as_string () const override;
  
--- 1141,1149 ----
    }
  
    // move constructors
!   TupleStructItemsHasRest (TupleStructItemsHasRest &&other) = default;
!   TupleStructItemsHasRest &operator= (TupleStructItemsHasRest &&other)
!     = default;
  
    std::string as_string () const override;
  
*************** public:
*** 1131,1144 ****
      return upper_patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::RANGE; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsRange *clone_tuple_struct_items_impl () const override
    {
!     return new TupleStructItemsRange (*this);
    }
  };
  
--- 1169,1182 ----
      return upper_patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::HAS_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsHasRest *clone_pattern_items_impl () const override
    {
!     return new TupleStructItemsHasRest (*this);
    }
  };
  
*************** protected:
*** 1221,1269 ****
  };
  
  // Base abstract class representing TuplePattern patterns
! class TuplePatternItems
  {
  public:
-   enum TuplePatternItemType
-   {
-     MULTIPLE,
-     RANGED,
-   };
- 
-   virtual ~TuplePatternItems () {}
- 
-   // TODO: should this store location data?
- 
    // Unique pointer custom clone function
    std::unique_ptr<TuplePatternItems> clone_tuple_pattern_items () const
    {
!     return std::unique_ptr<TuplePatternItems> (
!       clone_tuple_pattern_items_impl ());
    }
  
-   virtual std::string as_string () const = 0;
- 
-   virtual void accept_vis (ASTVisitor &vis) = 0;
- 
-   virtual TuplePatternItemType get_pattern_type () const = 0;
- 
  protected:
    // pure virtual clone implementation
!   virtual TuplePatternItems *clone_tuple_pattern_items_impl () const = 0;
  };
  
! // Class representing TuplePattern patterns where there are multiple patterns
! class TuplePatternItemsMultiple : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TuplePatternItemsMultiple (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsMultiple (TuplePatternItemsMultiple const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
--- 1259,1290 ----
  };
  
  // Base abstract class representing TuplePattern patterns
! class TuplePatternItems : public PatternItems
  {
  public:
    // Unique pointer custom clone function
    std::unique_ptr<TuplePatternItems> clone_tuple_pattern_items () const
    {
!     return std::unique_ptr<TuplePatternItems> (clone_pattern_items_impl ());
    }
  
  protected:
    // pure virtual clone implementation
!   virtual TuplePatternItems *clone_pattern_items_impl () const = 0;
  };
  
! // Class representing TuplePattern patterns which contains no rest pattern
! class TuplePatternItemsNoRest : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TuplePatternItemsNoRest (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsNoRest (TuplePatternItemsNoRest const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
*************** public:
*** 1271,1277 ****
    }
  
    // Overloaded assignment operator to vector clone
!   TuplePatternItemsMultiple &operator= (TuplePatternItemsMultiple const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
--- 1292,1298 ----
    }
  
    // Overloaded assignment operator to vector clone
!   TuplePatternItemsNoRest &operator= (TuplePatternItemsNoRest const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
*************** public:
*** 1282,1289 ****
    }
  
    // move constructors
!   TuplePatternItemsMultiple (TuplePatternItemsMultiple &&other) = default;
!   TuplePatternItemsMultiple &operator= (TuplePatternItemsMultiple &&other)
      = default;
  
    std::string as_string () const override;
--- 1303,1310 ----
    }
  
    // move constructors
!   TuplePatternItemsNoRest (TuplePatternItemsNoRest &&other) = default;
!   TuplePatternItemsNoRest &operator= (TuplePatternItemsNoRest &&other)
      = default;
  
    std::string as_string () const override;
*************** public:
*** 1297,1331 ****
      return patterns;
    }
  
!   TuplePatternItemType get_pattern_type () const override
!   {
!     return TuplePatternItemType::MULTIPLE;
!   }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsMultiple *clone_tuple_pattern_items_impl () const override
    {
!     return new TuplePatternItemsMultiple (*this);
    }
  };
  
! // Class representing TuplePattern patterns where there are a range of patterns
! class TuplePatternItemsRanged : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TuplePatternItemsRanged (std::vector<std::unique_ptr<Pattern>> lower_patterns,
! 			   std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsRanged (TuplePatternItemsRanged const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
--- 1318,1350 ----
      return patterns;
    }
  
!   ItemType get_item_type () const override { return ItemType::NO_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsNoRest *clone_pattern_items_impl () const override
    {
!     return new TuplePatternItemsNoRest (*this);
    }
  };
  
! // Class representing TuplePattern patterns which contains a rest pattern
! class TuplePatternItemsHasRest : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TuplePatternItemsHasRest (
!     std::vector<std::unique_ptr<Pattern>> lower_patterns,
!     std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsHasRest (TuplePatternItemsHasRest const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
*************** public:
*** 1337,1343 ****
    }
  
    // Overloaded assignment operator to clone
!   TuplePatternItemsRanged &operator= (TuplePatternItemsRanged const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
--- 1356,1362 ----
    }
  
    // Overloaded assignment operator to clone
!   TuplePatternItemsHasRest &operator= (TuplePatternItemsHasRest const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
*************** public:
*** 1353,1360 ****
    }
  
    // move constructors
!   TuplePatternItemsRanged (TuplePatternItemsRanged &&other) = default;
!   TuplePatternItemsRanged &operator= (TuplePatternItemsRanged &&other)
      = default;
  
    std::string as_string () const override;
--- 1372,1379 ----
    }
  
    // move constructors
!   TuplePatternItemsHasRest (TuplePatternItemsHasRest &&other) = default;
!   TuplePatternItemsHasRest &operator= (TuplePatternItemsHasRest &&other)
      = default;
  
    std::string as_string () const override;
*************** public:
*** 1381,1397 ****
      return upper_patterns;
    }
  
!   TuplePatternItemType get_pattern_type () const override
!   {
!     return TuplePatternItemType::RANGED;
!   }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsRanged *clone_tuple_pattern_items_impl () const override
    {
!     return new TuplePatternItemsRanged (*this);
    }
  };
  
--- 1400,1413 ----
      return upper_patterns;
    }
  
!   ItemType get_item_type () const override { return ItemType::HAS_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsHasRest *clone_pattern_items_impl () const override
    {
!     return new TuplePatternItemsHasRest (*this);
    }
  };
  
*************** public:
*** 1508,1513 ****
--- 1524,1535 ----
      return *pattern_in_parens;
    }
  
+   std::unique_ptr<Pattern> &get_pattern_in_parens_ptr ()
+   {
+     rust_assert (pattern_in_parens != nullptr);
+     return pattern_in_parens;
+   }
+ 
    NodeId get_node_id () const override { return node_id; }
  
    Pattern::Kind get_pattern_kind () override { return Pattern::Kind::Grouped; }
*************** protected:
*** 1522,1556 ****
  };
  
  // Base abstract class representing patterns in a SlicePattern
! class SlicePatternItems
  {
  public:
-   enum SlicePatternItemType
-   {
-     NO_REST,
-     HAS_REST,
-   };
- 
-   virtual ~SlicePatternItems () {}
- 
-   // TODO: should this store location data?
- 
    // Unique pointer custom clone function
    std::unique_ptr<SlicePatternItems> clone_slice_pattern_items () const
    {
!     return std::unique_ptr<SlicePatternItems> (
!       clone_slice_pattern_items_impl ());
    }
  
-   virtual std::string as_string () const = 0;
- 
-   virtual void accept_vis (ASTVisitor &vis) = 0;
- 
-   virtual SlicePatternItemType get_pattern_type () const = 0;
- 
  protected:
    // pure virtual clone implementation
!   virtual SlicePatternItems *clone_slice_pattern_items_impl () const = 0;
  };
  
  // Class representing the patterns in a SlicePattern without `..`
--- 1544,1561 ----
  };
  
  // Base abstract class representing patterns in a SlicePattern
! class SlicePatternItems : public PatternItems
  {
  public:
    // Unique pointer custom clone function
    std::unique_ptr<SlicePatternItems> clone_slice_pattern_items () const
    {
!     return std::unique_ptr<SlicePatternItems> (clone_pattern_items_impl ());
    }
  
  protected:
    // pure virtual clone implementation
!   virtual SlicePatternItems *clone_pattern_items_impl () const = 0;
  };
  
  // Class representing the patterns in a SlicePattern without `..`
*************** public:
*** 1598,1612 ****
      return patterns;
    }
  
!   SlicePatternItemType get_pattern_type () const override
!   {
!     return SlicePatternItemType::NO_REST;
!   }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   SlicePatternItemsNoRest *clone_slice_pattern_items_impl () const override
    {
      return new SlicePatternItemsNoRest (*this);
    }
--- 1603,1614 ----
      return patterns;
    }
  
!   ItemType get_item_type () const override { return ItemType::NO_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   SlicePatternItemsNoRest *clone_pattern_items_impl () const override
    {
      return new SlicePatternItemsNoRest (*this);
    }
*************** public:
*** 1683,1697 ****
      return upper_patterns;
    }
  
!   SlicePatternItemType get_pattern_type () const override
!   {
!     return SlicePatternItemType::HAS_REST;
!   }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   SlicePatternItemsHasRest *clone_slice_pattern_items_impl () const override
    {
      return new SlicePatternItemsHasRest (*this);
    }
--- 1685,1696 ----
      return upper_patterns;
    }
  
!   ItemType get_item_type () const override { return ItemType::HAS_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   SlicePatternItemsHasRest *clone_pattern_items_impl () const override
    {
      return new SlicePatternItemsHasRest (*this);
    }
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-stmt.h gcc-16-20251102/gcc/rust/ast/rust-stmt.h
*** gcc-16-20251026/gcc/rust/ast/rust-stmt.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-stmt.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 201,206 ****
--- 201,212 ----
      return *variables_pattern;
    }
  
+   std::unique_ptr<Pattern> &get_pattern_ptr ()
+   {
+     rust_assert (variables_pattern != nullptr);
+     return variables_pattern;
+   }
+ 
    Type &get_type ()
    {
      rust_assert (has_type ());
diff -Nrcpad gcc-16-20251026/gcc/rust/ast/rust-type.h gcc-16-20251102/gcc/rust/ast/rust-type.h
*** gcc-16-20251026/gcc/rust/ast/rust-type.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/ast/rust-type.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 571,576 ****
--- 571,582 ----
      return *type;
    }
  
+   std::unique_ptr<TypeNoBounds> &get_type_pointed_to_ptr ()
+   {
+     rust_assert (type != nullptr);
+     return type;
+   }
+ 
    // Getter for direct access to the type unique_ptr
    std::unique_ptr<TypeNoBounds> &get_type_ptr () { return type; }
  
*************** public:
*** 646,651 ****
--- 652,663 ----
      return *type;
    }
  
+   std::unique_ptr<TypeNoBounds> &get_type_referenced_ptr ()
+   {
+     rust_assert (type != nullptr);
+     return type;
+   }
+ 
    bool get_has_mut () const { return has_mut; }
  
    Lifetime &get_lifetime () { return lifetime.value (); }
*************** public:
*** 720,725 ****
--- 732,743 ----
      return *elem_type;
    }
  
+   std::unique_ptr<Type> &get_elem_type_ptr ()
+   {
+     rust_assert (elem_type != nullptr);
+     return elem_type;
+   }
+ 
    // TODO: would a "vis_expr" be better?
    AnonConst &get_size_expr ()
    {
*************** public:
*** 986,992 ****
        return_type (std::move (type)), locus (locus)
    {
      if (!variadic_attrs.empty ())
!       is_variadic = true;
    }
  
    // Copy constructor with clone
--- 1004,1010 ----
        return_type (std::move (type)), locus (locus)
    {
      if (!variadic_attrs.empty ())
!       _is_variadic = true;
    }
  
    // Copy constructor with clone
*************** public:
*** 1044,1057 ****
      return *return_type;
    }
  
    FunctionQualifiers &get_function_qualifiers () { return function_qualifiers; }
  
    BareFunctionType *reconstruct_impl () const override
    {
      return new BareFunctionType (
        for_lifetimes, function_qualifiers, params,
        /* FIXME: Should params be reconstruct() as well? */
!       _is_variadic, variadic_attrs, return_type->reconstruct (), locus);
    }
  
  protected:
--- 1062,1085 ----
      return *return_type;
    }
  
+   std::unique_ptr<TypeNoBounds> &get_return_type_ptr ()
+   {
+     rust_assert (has_return_type ());
+     return return_type;
+   }
+ 
    FunctionQualifiers &get_function_qualifiers () { return function_qualifiers; }
  
    BareFunctionType *reconstruct_impl () const override
    {
+     std::unique_ptr<TypeNoBounds> ret_type = nullptr;
+     if (return_type != nullptr)
+       ret_type = return_type->reconstruct ();
+ 
      return new BareFunctionType (
        for_lifetimes, function_qualifiers, params,
        /* FIXME: Should params be reconstruct() as well? */
!       _is_variadic, variadic_attrs, std::move (ret_type), locus);
    }
  
  protected:
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-base.cc gcc-16-20251102/gcc/rust/backend/rust-compile-base.cc
*** gcc-16-20251026/gcc/rust/backend/rust-compile-base.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-base.cc	Sun Nov  2 22:32:23 2025
***************
*** 32,37 ****
--- 32,38 ----
  #include "rust-type-util.h"
  #include "rust-compile-implitem.h"
  #include "rust-attribute-values.h"
+ #include "rust-attributes.h"
  #include "rust-immutable-name-resolution-context.h"
  
  #include "fold-const.h"
*************** void
*** 251,275 ****
  HIRCompileBase::handle_link_section_attribute_on_fndecl (
    tree fndecl, const AST::Attribute &attr)
  {
!   if (!attr.has_attr_input ())
      {
        rust_error_at (attr.get_locus (),
! 		     "%<link_section%> expects exactly one argment");
        return;
      }
  
-   rust_assert (attr.get_attr_input ().get_attr_input_type ()
- 	       == AST::AttrInput::AttrInputType::LITERAL);
- 
-   auto &literal = static_cast<AST::AttrInputLiteral &> (attr.get_attr_input ());
-   const auto &msg_str = literal.get_literal ().as_string ();
- 
    if (decl_section_name (fndecl))
      {
        rust_warning_at (attr.get_locus (), 0, "section name redefined");
      }
  
!   set_decl_section_name (fndecl, msg_str.c_str ());
  }
  
  void
--- 252,272 ----
  HIRCompileBase::handle_link_section_attribute_on_fndecl (
    tree fndecl, const AST::Attribute &attr)
  {
!   auto msg_str = Analysis::Attributes::extract_string_literal (attr);
! 
!   if (!msg_str.has_value ())
      {
        rust_error_at (attr.get_locus (),
! 		     "malformed %<link_section%> attribute input");
        return;
      }
  
    if (decl_section_name (fndecl))
      {
        rust_warning_at (attr.get_locus (), 0, "section name redefined");
      }
  
!   set_decl_section_name (fndecl, msg_str->c_str ());
  }
  
  void
*************** HIRCompileBase::handle_must_use_attribut
*** 416,428 ****
  
    if (attr.has_attr_input ())
      {
!       rust_assert (attr.get_attr_input ().get_attr_input_type ()
! 		   == AST::AttrInput::AttrInputType::LITERAL);
  
!       auto &literal
! 	= static_cast<AST::AttrInputLiteral &> (attr.get_attr_input ());
!       const auto &msg_str = literal.get_literal ().as_string ();
!       tree message = build_string (msg_str.size (), msg_str.c_str ());
  
        value = tree_cons (nodiscard, message, NULL_TREE);
      }
--- 413,422 ----
  
    if (attr.has_attr_input ())
      {
!       auto msg_str = Analysis::Attributes::extract_string_literal (attr);
!       rust_assert (msg_str.has_value ());
  
!       tree message = build_string (msg_str->size (), msg_str->c_str ());
  
        value = tree_cons (nodiscard, message, NULL_TREE);
      }
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-base.h gcc-16-20251102/gcc/rust/backend/rust-compile-base.h
*** gcc-16-20251026/gcc/rust/backend/rust-compile-base.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-base.h	Sun Nov  2 22:32:23 2025
*************** protected:
*** 56,62 ****
  		       TyTy::BaseType *expected, location_t lvalue_locus,
  		       location_t rvalue_locus);
  
!   tree coerce_to_dyn_object (tree compiled_ref, const TyTy::BaseType *actual,
  			     const TyTy::DynamicObjectType *ty,
  			     location_t locus);
  
--- 56,62 ----
  		       TyTy::BaseType *expected, location_t lvalue_locus,
  		       location_t rvalue_locus);
  
!   tree coerce_to_dyn_object (tree compiled_ref, TyTy::BaseType *actual,
  			     const TyTy::DynamicObjectType *ty,
  			     location_t locus);
  
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-context.h gcc-16-20251102/gcc/rust/backend/rust-compile-context.h
*** gcc-16-20251026/gcc/rust/backend/rust-compile-context.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-context.h	Sun Nov  2 22:32:23 2025
*************** namespace Compile {
*** 34,39 ****
--- 34,43 ----
  
  struct fncontext
  {
+   fncontext (tree fndecl, ::Bvariable *ret_addr, TyTy::BaseType *retty)
+     : fndecl (fndecl), ret_addr (ret_addr), retty (retty)
+   {}
+ 
    tree fndecl;
    ::Bvariable *ret_addr;
    TyTy::BaseType *retty;
*************** public:
*** 154,160 ****
      if (it == mono_fns.end ())
        mono_fns[dId] = {};
  
!     mono_fns[dId].push_back ({ref, fn});
    }
  
    void insert_closure_decl (const TyTy::ClosureType *ref, tree fn)
--- 158,164 ----
      if (it == mono_fns.end ())
        mono_fns[dId] = {};
  
!     mono_fns[dId].emplace_back (ref, fn);
    }
  
    void insert_closure_decl (const TyTy::ClosureType *ref, tree fn)
*************** public:
*** 164,170 ****
      if (it == mono_closure_fns.end ())
        mono_closure_fns[dId] = {};
  
!     mono_closure_fns[dId].push_back ({ref, fn});
    }
  
    tree lookup_closure_decl (const TyTy::ClosureType *ref)
--- 168,174 ----
      if (it == mono_closure_fns.end ())
        mono_closure_fns[dId] = {};
  
!     mono_closure_fns[dId].emplace_back (ref, fn);
    }
  
    tree lookup_closure_decl (const TyTy::ClosureType *ref)
*************** public:
*** 279,285 ****
  
    void push_fn (tree fn, ::Bvariable *ret_addr, TyTy::BaseType *retty)
    {
!     fn_stack.push_back (fncontext{fn, ret_addr, retty});
    }
    void pop_fn () { fn_stack.pop_back (); }
  
--- 283,289 ----
  
    void push_fn (tree fn, ::Bvariable *ret_addr, TyTy::BaseType *retty)
    {
!     fn_stack.emplace_back (fn, ret_addr, retty);
    }
    void pop_fn () { fn_stack.pop_back (); }
  
*************** public:
*** 318,324 ****
  
    void push_loop_context (Bvariable *var) { loop_value_stack.push_back (var); }
  
!   Bvariable *peek_loop_context () { return loop_value_stack.back (); }
  
    Bvariable *pop_loop_context ()
    {
--- 322,334 ----
  
    void push_loop_context (Bvariable *var) { loop_value_stack.push_back (var); }
  
!   bool have_loop_context () const { return !loop_value_stack.empty (); }
! 
!   Bvariable *peek_loop_context ()
!   {
!     rust_assert (!loop_value_stack.empty ());
!     return loop_value_stack.back ();
!   }
  
    Bvariable *pop_loop_context ()
    {
*************** public:
*** 332,338 ****
      loop_begin_labels.push_back (label);
    }
  
!   tree peek_loop_begin_label () { return loop_begin_labels.back (); }
  
    tree pop_loop_begin_label ()
    {
--- 342,352 ----
      loop_begin_labels.push_back (label);
    }
  
!   tree peek_loop_begin_label ()
!   {
!     rust_assert (!loop_begin_labels.empty ());
!     return loop_begin_labels.back ();
!   }
  
    tree pop_loop_begin_label ()
    {
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-expr.cc gcc-16-20251102/gcc/rust/backend/rust-compile-expr.cc
*** gcc-16-20251026/gcc/rust/backend/rust-compile-expr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-expr.cc	Sun Nov  2 22:32:23 2025
*************** CompileExpr::visit (HIR::BreakExpr &expr
*** 828,833 ****
--- 828,837 ----
      {
        tree compiled_expr = CompileExpr::Compile (expr.get_expr (), ctx);
  
+       translated = error_mark_node;
+       if (!ctx->have_loop_context ())
+ 	return;
+ 
        Bvariable *loop_result_holder = ctx->peek_loop_context ();
        tree result_reference
  	= Backend::var_expression (loop_result_holder,
*************** CompileExpr::visit (HIR::BreakExpr &expr
*** 891,896 ****
--- 895,904 ----
  void
  CompileExpr::visit (HIR::ContinueExpr &expr)
  {
+   translated = error_mark_node;
+   if (!ctx->have_loop_context ())
+     return;
+ 
    tree label = ctx->peek_loop_begin_label ();
    if (expr.has_label ())
      {
*************** CompileExpr::compile_integer_literal (co
*** 1647,1683 ****
  				      const TyTy::BaseType *tyty)
  {
    rust_assert (expr.get_lit_type () == HIR::Literal::INT);
!   const auto literal_value = expr.get_literal ();
! 
    tree type = TyTyResolveCompile::compile (ctx, tyty);
  
    mpz_t ival;
!   if (mpz_init_set_str (ival, literal_value.as_string ().c_str (), 10) != 0)
      {
!       rust_error_at (expr.get_locus (), "bad number in literal");
        return error_mark_node;
      }
  
!   mpz_t type_min;
!   mpz_t type_max;
    mpz_init (type_min);
    mpz_init (type_max);
    get_type_static_bounds (type, type_min, type_max);
  
-   if (expr.is_negative ())
-     {
-       mpz_neg (ival, ival);
-     }
    if (mpz_cmp (ival, type_min) < 0 || mpz_cmp (ival, type_max) > 0)
      {
        rust_error_at (expr.get_locus (),
  		     "integer overflows the respective type %qs",
  		     tyty->get_name ().c_str ());
        return error_mark_node;
      }
  
    tree result = wide_int_to_tree (type, wi::from_mpz (type, ival, true));
- 
    mpz_clear (type_min);
    mpz_clear (type_max);
    mpz_clear (ival);
--- 1655,1693 ----
  				      const TyTy::BaseType *tyty)
  {
    rust_assert (expr.get_lit_type () == HIR::Literal::INT);
!   const auto &literal_value = expr.get_literal ();
    tree type = TyTyResolveCompile::compile (ctx, tyty);
  
+   std::string s = literal_value.as_string ();
+   s.erase (std::remove (s.begin (), s.end (), '_'), s.end ());
+ 
+   int base = 0;
    mpz_t ival;
!   if (mpz_init_set_str (ival, s.c_str (), base) != 0)
      {
!       rust_error_at (expr.get_locus (), "failed to load number literal");
        return error_mark_node;
      }
+   if (expr.is_negative ())
+     mpz_neg (ival, ival);
  
!   mpz_t type_min, type_max;
    mpz_init (type_min);
    mpz_init (type_max);
    get_type_static_bounds (type, type_min, type_max);
  
    if (mpz_cmp (ival, type_min) < 0 || mpz_cmp (ival, type_max) > 0)
      {
        rust_error_at (expr.get_locus (),
  		     "integer overflows the respective type %qs",
  		     tyty->get_name ().c_str ());
+       mpz_clear (type_min);
+       mpz_clear (type_max);
+       mpz_clear (ival);
        return error_mark_node;
      }
  
    tree result = wide_int_to_tree (type, wi::from_mpz (type, ival, true));
    mpz_clear (type_min);
    mpz_clear (type_max);
    mpz_clear (ival);
*************** CompileExpr::array_copied_expr (location
*** 2000,2012 ****
        return error_mark_node;
      }
  
!   ctx->push_const_context ();
!   tree capacity_expr = CompileExpr::Compile (elems.get_num_copies_expr (), ctx);
!   ctx->pop_const_context ();
  
!   if (!TREE_CONSTANT (capacity_expr))
      {
!       rust_error_at (expr_locus, "non const num copies %qT", array_type);
        return error_mark_node;
      }
  
--- 2010,2034 ----
        return error_mark_node;
      }
  
!   auto capacity_ty = array_tyty.get_capacity ();
  
!   // Check if capacity is a const type
!   if (capacity_ty->get_kind () != TyTy::TypeKind::CONST)
      {
!       rust_error_at (array_tyty.get_locus (),
! 		     "array capacity is not a const type");
!       return error_mark_node;
!     }
! 
!   auto *capacity_const = capacity_ty->as_const_type ();
! 
!   rust_assert (capacity_const->const_kind ()
! 	       == TyTy::BaseConstType::ConstKind::Value);
!   auto &capacity_value = *static_cast<TyTy::ConstValueType *> (capacity_const);
!   auto cap_tree = capacity_value.get_value ();
!   if (error_operand_p (cap_tree) || !TREE_CONSTANT (cap_tree))
!     {
!       rust_error_at (expr_locus, "non const num copies %qT", cap_tree);
        return error_mark_node;
      }
  
*************** CompileExpr::array_copied_expr (location
*** 2059,2067 ****
        ctx->push_block (init_block);
  
        tree tmp;
!       tree stmts = Backend::array_initializer (fndecl, init_block, array_type,
! 					       capacity_expr, translated_expr,
! 					       &tmp, expr_locus);
        ctx->add_statement (stmts);
  
        tree block = ctx->pop_block ();
--- 2081,2089 ----
        ctx->push_block (init_block);
  
        tree tmp;
!       tree stmts
! 	= Backend::array_initializer (fndecl, init_block, array_type, cap_tree,
! 				      translated_expr, &tmp, expr_locus);
        ctx->add_statement (stmts);
  
        tree block = ctx->pop_block ();
*************** HIRCompileBase::resolve_unsized_dyn_adju
*** 2209,2219 ****
    tree rvalue = expression;
    location_t rvalue_locus = locus;
  
!   const TyTy::BaseType *actual = adjustment.get_actual ();
!   const TyTy::BaseType *expected = adjustment.get_expected ();
  
!   const TyTy::DynamicObjectType *dyn
!     = static_cast<const TyTy::DynamicObjectType *> (expected);
  
    rust_debug ("resolve_unsized_dyn_adjustment actual={%s} dyn={%s}",
  	      actual->debug_str ().c_str (), dyn->debug_str ().c_str ());
--- 2231,2240 ----
    tree rvalue = expression;
    location_t rvalue_locus = locus;
  
!   auto actual = adjustment.get_actual ();
!   auto expected = adjustment.get_expected ();
  
!   const auto dyn = static_cast<const TyTy::DynamicObjectType *> (expected);
  
    rust_debug ("resolve_unsized_dyn_adjustment actual={%s} dyn={%s}",
  	      actual->debug_str ().c_str (), dyn->debug_str ().c_str ());
*************** CompileExpr::generate_closure_fntype (HI
*** 2617,2631 ****
    TyTy::TypeBoundPredicateItem item = TyTy::TypeBoundPredicateItem::error ();
    if (predicate.get_name ().compare ("FnOnce") == 0)
      {
!       item = predicate.lookup_associated_item ("call_once");
      }
    else if (predicate.get_name ().compare ("FnMut") == 0)
      {
!       item = predicate.lookup_associated_item ("call_mut");
      }
    else if (predicate.get_name ().compare ("Fn") == 0)
      {
!       item = predicate.lookup_associated_item ("call");
      }
    else
      {
--- 2638,2652 ----
    TyTy::TypeBoundPredicateItem item = TyTy::TypeBoundPredicateItem::error ();
    if (predicate.get_name ().compare ("FnOnce") == 0)
      {
!       item = predicate.lookup_associated_item ("call_once").value ();
      }
    else if (predicate.get_name ().compare ("FnMut") == 0)
      {
!       item = predicate.lookup_associated_item ("call_mut").value ();
      }
    else if (predicate.get_name ().compare ("Fn") == 0)
      {
!       item = predicate.lookup_associated_item ("call").value ();
      }
    else
      {
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-extern.h gcc-16-20251102/gcc/rust/backend/rust-compile-extern.h
*** gcc-16-20251026/gcc/rust/backend/rust-compile-extern.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-extern.h	Sun Nov  2 22:32:23 2025
***************
*** 24,29 ****
--- 24,31 ----
  #include "rust-compile-type.h"
  #include "rust-diagnostics.h"
  #include "rust-hir-full-decls.h"
+ #include "rust-attributes.h"
+ #include "rust-attribute-values.h"
  
  namespace Rust {
  namespace Compile {
*************** public:
*** 57,64 ****
      rust_assert (ok);
  
      std::string name = item.get_item_name ().as_string ();
!     // FIXME this is assuming C ABI
!     std::string asm_name = name;
  
      tree type = TyTyResolveCompile::compile (ctx, resolved_type);
      bool is_external = true;
--- 59,65 ----
      rust_assert (ok);
  
      std::string name = item.get_item_name ().as_string ();
!     GGC::Ident asm_name = get_link_name (item);
  
      tree type = TyTyResolveCompile::compile (ctx, resolved_type);
      bool is_external = true;
*************** public:
*** 124,139 ****
  
      tree compiled_fn_type = TyTyResolveCompile::compile (ctx, fntype);
      std::string ir_symbol_name = function.get_item_name ().as_string ();
!     std::string asm_name = function.get_item_name ().as_string ();
!     if (fntype->get_abi () == ABI::RUST)
!       {
! 	// then we need to get the canonical path of it and mangle it
! 	auto canonical_path = ctx->get_mappings ().lookup_canonical_path (
! 	  function.get_mappings ().get_nodeid ());
! 
! 	ir_symbol_name = canonical_path->get () + fntype->subst_as_string ();
! 	asm_name = ctx->mangle_item (fntype, *canonical_path);
!       }
  
      const unsigned int flags = Backend::function_is_declaration;
      tree fndecl = Backend::function (compiled_fn_type, ir_symbol_name, asm_name,
--- 125,131 ----
  
      tree compiled_fn_type = TyTyResolveCompile::compile (ctx, fntype);
      std::string ir_symbol_name = function.get_item_name ().as_string ();
!     GGC::Ident asm_name = get_link_name (function);
  
      const unsigned int flags = Backend::function_is_declaration;
      tree fndecl = Backend::function (compiled_fn_type, ir_symbol_name, asm_name,
*************** private:
*** 158,163 ****
--- 150,185 ----
        ref_locus (ref_locus)
    {}
  
+   template <typename T> static GGC::Ident get_link_name (T &obj)
+   {
+     AST::Attribute *use_attr = nullptr;
+ 
+     for (auto &attr : obj.get_outer_attrs ())
+       {
+ 	if (attr.get_path ().as_string () == Values::Attributes::LINK_NAME)
+ 	  {
+ 	    // later attributes override earlier ones
+ 	    // TODO: add warning -- should duplicate
+ 	    //       attributes be folded elsewhere?
+ 	    use_attr = &attr;
+ 	  }
+       }
+ 
+     if (use_attr)
+       {
+ 	auto link_name
+ 	  = Analysis::Attributes::extract_string_literal (*use_attr);
+ 
+ 	if (!link_name.has_value ())
+ 	  rust_error_at (use_attr->get_locus (),
+ 			 "malformed %<link_name%> attribute input");
+ 	else
+ 	  return *link_name;
+       }
+ 
+     return obj.get_item_name ();
+   }
+ 
    TyTy::BaseType *concrete;
    tree reference;
    location_t ref_locus;
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-pattern.cc gcc-16-20251102/gcc/rust/backend/rust-compile-pattern.cc
*** gcc-16-20251026/gcc/rust/backend/rust-compile-pattern.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-pattern.cc	Sun Nov  2 22:32:23 2025
***************
*** 27,32 ****
--- 27,33 ----
  #include "rust-hir-pattern.h"
  #include "rust-system.h"
  #include "rust-tyty.h"
+ #include "tree.h"
  
  namespace Rust {
  namespace Compile {
*************** CompilePatternCheckExpr::visit (HIR::Ran
*** 158,170 ****
  					    pattern.get_mappings (),
  					    pattern.get_locus (), ctx);
  
    tree check_lower
      = Backend::comparison_expression (ComparisonOperator::GREATER_OR_EQUAL,
  				      match_scrutinee_expr, lower,
  				      pattern.get_locus ());
    tree check_upper
!     = Backend::comparison_expression (ComparisonOperator::LESS_OR_EQUAL,
! 				      match_scrutinee_expr, upper,
  				      pattern.get_locus ());
    check_expr = Backend::arithmetic_or_logical_expression (
      ArithmeticOrLogicalOperator::BITWISE_AND, check_lower, check_upper,
--- 159,173 ----
  					    pattern.get_mappings (),
  					    pattern.get_locus (), ctx);
  
+   ComparisonOperator upper_cmp = pattern.is_inclusive_range ()
+ 				   ? ComparisonOperator::LESS_OR_EQUAL
+ 				   : ComparisonOperator::LESS_THAN;
    tree check_lower
      = Backend::comparison_expression (ComparisonOperator::GREATER_OR_EQUAL,
  				      match_scrutinee_expr, lower,
  				      pattern.get_locus ());
    tree check_upper
!     = Backend::comparison_expression (upper_cmp, match_scrutinee_expr, upper,
  				      pattern.get_locus ());
    check_expr = Backend::arithmetic_or_logical_expression (
      ArithmeticOrLogicalOperator::BITWISE_AND, check_lower, check_upper,
*************** CompilePatternCheckExpr::visit (HIR::Tup
*** 354,370 ****
    HIR::TupleStructItems &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case HIR::TupleStructItems::RANGED:
        {
! 	// TODO
! 	rust_unreachable ();
        }
        break;
  
!     case HIR::TupleStructItems::MULTIPLE:
        {
! 	HIR::TupleStructItemsNoRange &items_no_range
! 	  = static_cast<HIR::TupleStructItemsNoRange &> (items);
  
  	rust_assert (items_no_range.get_patterns ().size ()
  		     == variant->num_fields ());
--- 357,407 ----
    HIR::TupleStructItems &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case HIR::TupleStructItems::HAS_REST:
        {
! 	HIR::TupleStructItemsHasRest &items_has_rest
! 	  = static_cast<HIR::TupleStructItemsHasRest &> (items);
! 	size_t num_patterns = items_has_rest.get_lower_patterns ().size ()
! 			      + items_has_rest.get_upper_patterns ().size ();
! 
! 	// enums cases shouldn't reach here
! 	rust_assert (num_patterns <= variant->num_fields ()
! 		     && (!adt->is_enum ()));
! 
! 	size_t tuple_field_index = 0;
! 	for (auto &pattern : items_has_rest.get_lower_patterns ())
! 	  {
! 	    tree field_expr
! 	      = Backend::struct_field_expression (match_scrutinee_expr,
! 						  tuple_field_index++,
! 						  pattern->get_locus ());
! 	    tree check_expr_sub
! 	      = CompilePatternCheckExpr::Compile (*pattern, field_expr, ctx);
! 	    check_expr = Backend::arithmetic_or_logical_expression (
! 	      ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
! 	      check_expr_sub, pattern->get_locus ());
! 	  }
! 	tuple_field_index = variant->num_fields ()
! 			    - items_has_rest.get_upper_patterns ().size ();
! 	for (auto &pattern : items_has_rest.get_upper_patterns ())
! 	  {
! 	    tree field_expr
! 	      = Backend::struct_field_expression (match_scrutinee_expr,
! 						  tuple_field_index++,
! 						  pattern->get_locus ());
! 	    tree check_expr_sub
! 	      = CompilePatternCheckExpr::Compile (*pattern, field_expr, ctx);
! 	    check_expr = Backend::arithmetic_or_logical_expression (
! 	      ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
! 	      check_expr_sub, pattern->get_locus ());
! 	  }
        }
        break;
  
!     case HIR::TupleStructItems::NO_REST:
        {
! 	HIR::TupleStructItemsNoRest &items_no_range
! 	  = static_cast<HIR::TupleStructItemsNoRest &> (items);
  
  	rust_assert (items_no_range.get_patterns ().size ()
  		     == variant->num_fields ());
*************** CompilePatternCheckExpr::visit (HIR::Tup
*** 428,437 ****
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::RANGED:
        {
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsRanged &> (pattern.get_items ());
  	size_t tuple_field_index = 0;
  
  	// lookup the type to find out number of fields
--- 465,474 ----
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::HAS_REST:
        {
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsHasRest &> (pattern.get_items ());
  	size_t tuple_field_index = 0;
  
  	// lookup the type to find out number of fields
*************** CompilePatternCheckExpr::visit (HIR::Tup
*** 477,486 ****
        }
        break;
  
!     case HIR::TuplePatternItems::MULTIPLE:
        {
! 	auto &items = static_cast<HIR::TuplePatternItemsMultiple &> (
! 	  pattern.get_items ());
  	size_t tuple_field_index = 0;
  
  	for (auto &pat : items.get_patterns ())
--- 514,523 ----
        }
        break;
  
!     case HIR::TuplePatternItems::NO_REST:
        {
! 	auto &items
! 	  = static_cast<HIR::TuplePatternItemsNoRest &> (pattern.get_items ());
  	size_t tuple_field_index = 0;
  
  	for (auto &pat : items.get_patterns ())
*************** CompilePatternCheckExpr::visit (HIR::Sli
*** 532,556 ****
  	       || lookup->get_kind () == TyTy::TypeKind::SLICE
  	       || lookup->get_kind () == TyTy::REF);
  
!   size_t array_element_index = 0;
    switch (lookup->get_kind ())
      {
      case TyTy::TypeKind::ARRAY:
!       for (auto &pattern_member : pattern.get_items ())
! 	{
! 	  tree array_index_tree
! 	    = Backend::size_constant_expression (array_element_index++);
! 	  tree element_expr
! 	    = Backend::array_index_expression (match_scrutinee_expr,
! 					       array_index_tree,
! 					       pattern.get_locus ());
! 	  tree check_expr_sub
! 	    = CompilePatternCheckExpr::Compile (*pattern_member, element_expr,
! 						ctx);
! 	  check_expr = Backend::arithmetic_or_logical_expression (
! 	    ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
! 	    check_expr_sub, pattern.get_locus ());
! 	}
        break;
      case TyTy::TypeKind::SLICE:
        rust_sorry_at (
--- 569,582 ----
  	       || lookup->get_kind () == TyTy::TypeKind::SLICE
  	       || lookup->get_kind () == TyTy::REF);
  
!   // function ptr that points to either array_index_expression or
!   // slice_index_expression depending on the scrutinee's type
!   tree (*scrutinee_index_expr_func) (tree, tree, location_t) = nullptr;
! 
    switch (lookup->get_kind ())
      {
      case TyTy::TypeKind::ARRAY:
!       scrutinee_index_expr_func = Backend::array_index_expression;
        break;
      case TyTy::TypeKind::SLICE:
        rust_sorry_at (
*************** CompilePatternCheckExpr::visit (HIR::Sli
*** 560,584 ****
      case TyTy::TypeKind::REF:
        {
  	rust_assert (RS_DST_FLAG_P (TREE_TYPE (match_scrutinee_expr)));
  	tree size_field
  	  = Backend::struct_field_expression (match_scrutinee_expr, 1,
  					      pattern.get_locus ());
  
! 	// First compare the size
! 	check_expr = Backend::comparison_expression (
! 	  ComparisonOperator::EQUAL, size_field,
! 	  build_int_cst (size_type_node, pattern.get_items ().size ()),
! 	  pattern.get_locus ());
  
! 	// Then compare each element in the slice pattern
! 	for (auto &pattern_member : pattern.get_items ())
  	  {
! 	    tree slice_index_tree
! 	      = Backend::size_constant_expression (array_element_index++);
  	    tree element_expr
! 	      = Backend::slice_index_expression (match_scrutinee_expr,
! 						 slice_index_tree,
! 						 pattern.get_locus ());
  	    tree check_expr_sub
  	      = CompilePatternCheckExpr::Compile (*pattern_member, element_expr,
  						  ctx);
--- 586,646 ----
      case TyTy::TypeKind::REF:
        {
  	rust_assert (RS_DST_FLAG_P (TREE_TYPE (match_scrutinee_expr)));
+ 	scrutinee_index_expr_func = Backend::slice_index_expression;
  	tree size_field
  	  = Backend::struct_field_expression (match_scrutinee_expr, 1,
  					      pattern.get_locus ());
  
! 	// for slices, generate a dynamic size comparison expression tree
! 	// because size checking is done at runtime.
! 	switch (pattern.get_items ().get_item_type ())
! 	  {
! 	  case HIR::SlicePatternItems::ItemType::NO_REST:
! 	    {
! 	      auto &items = static_cast<HIR::SlicePatternItemsNoRest &> (
! 		pattern.get_items ());
! 	      check_expr = Backend::comparison_expression (
! 		ComparisonOperator::EQUAL, size_field,
! 		build_int_cst (size_type_node, items.get_patterns ().size ()),
! 		pattern.get_locus ());
! 	    }
! 	    break;
! 	  case HIR::SlicePatternItems::ItemType::HAS_REST:
! 	    {
! 	      auto &items = static_cast<HIR::SlicePatternItemsHasRest &> (
! 		pattern.get_items ());
! 	      auto pattern_min_cap = items.get_lower_patterns ().size ()
! 				     + items.get_upper_patterns ().size ();
! 	      check_expr = Backend::comparison_expression (
! 		ComparisonOperator::GREATER_OR_EQUAL, size_field,
! 		build_int_cst (size_type_node, pattern_min_cap),
! 		pattern.get_locus ());
! 	    }
! 	    break;
! 	  }
!       }
!       break;
!     default:
!       rust_unreachable ();
!     }
  
!   rust_assert (scrutinee_index_expr_func != nullptr);
! 
!   // Generate tree to compare every element within array/slice
!   size_t element_index = 0;
!   switch (pattern.get_items ().get_item_type ())
!     {
!     case HIR::SlicePatternItems::ItemType::NO_REST:
!       {
! 	auto &items
! 	  = static_cast<HIR::SlicePatternItemsNoRest &> (pattern.get_items ());
! 	for (auto &pattern_member : items.get_patterns ())
  	  {
! 	    tree index_tree
! 	      = Backend::size_constant_expression (element_index++);
  	    tree element_expr
! 	      = scrutinee_index_expr_func (match_scrutinee_expr, index_tree,
! 					   pattern.get_locus ());
  	    tree check_expr_sub
  	      = CompilePatternCheckExpr::Compile (*pattern_member, element_expr,
  						  ctx);
*************** CompilePatternCheckExpr::visit (HIR::Sli
*** 586,595 ****
  	      ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
  	      check_expr_sub, pattern.get_locus ());
  	  }
        }
        break;
-     default:
-       rust_unreachable ();
      }
  }
  
--- 648,749 ----
  	      ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
  	      check_expr_sub, pattern.get_locus ());
  	  }
+ 	break;
+       }
+     case HIR::SlicePatternItems::ItemType::HAS_REST:
+       {
+ 	auto &items
+ 	  = static_cast<HIR::SlicePatternItemsHasRest &> (pattern.get_items ());
+ 	for (auto &pattern_member : items.get_lower_patterns ())
+ 	  {
+ 	    tree index_tree
+ 	      = Backend::size_constant_expression (element_index++);
+ 	    tree element_expr
+ 	      = scrutinee_index_expr_func (match_scrutinee_expr, index_tree,
+ 					   pattern.get_locus ());
+ 	    tree check_expr_sub
+ 	      = CompilePatternCheckExpr::Compile (*pattern_member, element_expr,
+ 						  ctx);
+ 	    check_expr = Backend::arithmetic_or_logical_expression (
+ 	      ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
+ 	      check_expr_sub, pattern.get_locus ());
+ 	  }
+ 
+ 	// handle codegen for upper patterns differently for both types
+ 	switch (lookup->get_kind ())
+ 	  {
+ 	  case TyTy::TypeKind::ARRAY:
+ 	    {
+ 	      // for array type scrutinee, we can simply get the capacity as a
+ 	      // const and calculate how many elements to skip
+ 	      auto array_ty = static_cast<TyTy::ArrayType *> (lookup);
+ 	      auto capacity_ty = array_ty->get_capacity ();
+ 
+ 	      rust_assert (capacity_ty->get_kind () == TyTy::TypeKind::CONST);
+ 	      auto *capacity_const = capacity_ty->as_const_type ();
+ 	      rust_assert (capacity_const->const_kind ()
+ 			   == TyTy::BaseConstType::ConstKind::Value);
+ 	      auto &capacity_value
+ 		= *static_cast<TyTy::ConstValueType *> (capacity_const);
+ 	      auto cap_tree = capacity_value.get_value ();
+ 
+ 	      rust_assert (!error_operand_p (cap_tree));
+ 
+ 	      size_t cap_wi = (size_t) wi::to_wide (cap_tree).to_uhwi ();
+ 	      element_index = cap_wi - items.get_upper_patterns ().size ();
+ 	      for (auto &pattern_member : items.get_upper_patterns ())
+ 		{
+ 		  tree index_tree
+ 		    = Backend::size_constant_expression (element_index++);
+ 		  tree element_expr
+ 		    = scrutinee_index_expr_func (match_scrutinee_expr,
+ 						 index_tree,
+ 						 pattern.get_locus ());
+ 		  tree check_expr_sub
+ 		    = CompilePatternCheckExpr::Compile (*pattern_member,
+ 							element_expr, ctx);
+ 		  check_expr = Backend::arithmetic_or_logical_expression (
+ 		    ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
+ 		    check_expr_sub, pattern.get_locus ());
+ 		}
+ 	    }
+ 	    break;
+ 	  case TyTy::TypeKind::REF:
+ 	    {
+ 	      // for slice type scrutinee, size is dyanamic, so number of
+ 	      // elements to skip is calculated during runtime
+ 	      tree slice_size
+ 		= Backend::struct_field_expression (match_scrutinee_expr, 1,
+ 						    pattern.get_locus ());
+ 	      tree upper_patterns_size = Backend::size_constant_expression (
+ 		items.get_upper_patterns ().size ());
+ 	      tree index_tree = Backend::arithmetic_or_logical_expression (
+ 		ArithmeticOrLogicalOperator::SUBTRACT, slice_size,
+ 		upper_patterns_size, pattern.get_locus ());
+ 	      for (auto &pattern_member : items.get_upper_patterns ())
+ 		{
+ 		  tree element_expr
+ 		    = scrutinee_index_expr_func (match_scrutinee_expr,
+ 						 index_tree,
+ 						 pattern.get_locus ());
+ 		  tree check_expr_sub
+ 		    = CompilePatternCheckExpr::Compile (*pattern_member,
+ 							element_expr, ctx);
+ 		  check_expr = Backend::arithmetic_or_logical_expression (
+ 		    ArithmeticOrLogicalOperator::BITWISE_AND, check_expr,
+ 		    check_expr_sub, pattern.get_locus ());
+ 		  index_tree = Backend::arithmetic_or_logical_expression (
+ 		    ArithmeticOrLogicalOperator::ADD, index_tree,
+ 		    Backend::size_constant_expression (1),
+ 		    pattern.get_locus ());
+ 		}
+ 	    }
+ 	    break;
+ 	  default:
+ 	    rust_unreachable ();
+ 	  }
        }
        break;
      }
  }
  
*************** CompilePatternBindings::visit (HIR::Tupl
*** 628,652 ****
    HIR::TupleStructItems &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case HIR::TupleStructItems::RANGED:
        {
! 	// TODO
! 	rust_unreachable ();
        }
        break;
  
!     case HIR::TupleStructItems::MULTIPLE:
        {
! 	HIR::TupleStructItemsNoRange &items_no_range
! 	  = static_cast<HIR::TupleStructItemsNoRange &> (items);
! 
! 	rust_assert (items_no_range.get_patterns ().size ()
  		     == variant->num_fields ());
  
  	if (adt->is_enum ())
  	  {
  	    size_t tuple_field_index = 0;
! 	    for (auto &pattern : items_no_range.get_patterns ())
  	      {
  		tree payload_accessor_union
  		  = Backend::struct_field_expression (match_scrutinee_expr, 1,
--- 782,835 ----
    HIR::TupleStructItems &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case HIR::TupleStructItems::HAS_REST:
        {
! 	HIR::TupleStructItemsHasRest &items_has_rest
! 	  = static_cast<HIR::TupleStructItemsHasRest &> (items);
! 	size_t num_patterns = items_has_rest.get_lower_patterns ().size ()
! 			      + items_has_rest.get_upper_patterns ().size ();
! 
! 	// enums cases shouldn't reach here
! 	rust_assert (num_patterns <= variant->num_fields ()
! 		     && (!adt->is_enum ()));
! 
! 	size_t tuple_field_index = 0;
! 	for (auto &pattern : items_has_rest.get_lower_patterns ())
! 	  {
! 	    tree binding
! 	      = Backend::struct_field_expression (match_scrutinee_expr,
! 						  tuple_field_index++,
! 						  pattern->get_locus ());
! 
! 	    CompilePatternBindings::Compile (*pattern, binding, ctx);
! 	  }
! 
! 	tuple_field_index = variant->num_fields ()
! 			    - items_has_rest.get_upper_patterns ().size ();
! 
! 	for (auto &pattern : items_has_rest.get_upper_patterns ())
! 	  {
! 	    tree binding
! 	      = Backend::struct_field_expression (match_scrutinee_expr,
! 						  tuple_field_index++,
! 						  pattern->get_locus ());
! 
! 	    CompilePatternBindings::Compile (*pattern, binding, ctx);
! 	  }
        }
        break;
  
!     case HIR::TupleStructItems::NO_REST:
        {
! 	HIR::TupleStructItemsNoRest &items_no_rest
! 	  = static_cast<HIR::TupleStructItemsNoRest &> (items);
! 	rust_assert (items_no_rest.get_patterns ().size ()
  		     == variant->num_fields ());
  
  	if (adt->is_enum ())
  	  {
  	    size_t tuple_field_index = 0;
! 	    for (auto &pattern : items_no_rest.get_patterns ())
  	      {
  		tree payload_accessor_union
  		  = Backend::struct_field_expression (match_scrutinee_expr, 1,
*************** CompilePatternBindings::visit (HIR::Tupl
*** 668,679 ****
  	else
  	  {
  	    size_t tuple_field_index = 0;
! 	    for (auto &pattern : items_no_range.get_patterns ())
  	      {
- 		tree variant_accessor = match_scrutinee_expr;
- 
  		tree binding
! 		  = Backend::struct_field_expression (variant_accessor,
  						      tuple_field_index++,
  						      pattern->get_locus ());
  
--- 851,860 ----
  	else
  	  {
  	    size_t tuple_field_index = 0;
! 	    for (auto &pattern : items_no_rest.get_patterns ())
  	      {
  		tree binding
! 		  = Backend::struct_field_expression (match_scrutinee_expr,
  						      tuple_field_index++,
  						      pattern->get_locus ());
  
*************** CompilePatternBindings::visit (HIR::Stru
*** 777,784 ****
        rust_assert (ok);
      }
  
!   rust_assert (variant->get_variant_type ()
! 	       == TyTy::VariantDef::VariantType::STRUCT);
  
    auto &struct_pattern_elems = pattern.get_struct_pattern_elems ();
    for (auto &field : struct_pattern_elems.get_struct_pattern_fields ())
--- 958,966 ----
        rust_assert (ok);
      }
  
!   rust_assert (
!     variant->get_variant_type () == TyTy::VariantDef::VariantType::STRUCT
!     || variant->get_variant_type () == TyTy::VariantDef::VariantType::TUPLE);
  
    auto &struct_pattern_elems = pattern.get_struct_pattern_elems ();
    for (auto &field : struct_pattern_elems.get_struct_pattern_fields ())
*************** CompilePatternBindings::visit (HIR::Tupl
*** 843,853 ****
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::RANGED:
        {
  	size_t tuple_idx = 0;
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsRanged &> (pattern.get_items ());
  
  	auto &items_lower = items.get_lower_patterns ();
  	auto &items_upper = items.get_upper_patterns ();
--- 1025,1035 ----
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::HAS_REST:
        {
  	size_t tuple_idx = 0;
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsHasRest &> (pattern.get_items ());
  
  	auto &items_lower = items.get_lower_patterns ();
  	auto &items_upper = items.get_upper_patterns ();
*************** CompilePatternBindings::visit (HIR::Tupl
*** 887,897 ****
  
  	return;
        }
!     case HIR::TuplePatternItems::ItemType::MULTIPLE:
        {
  	size_t tuple_idx = 0;
! 	auto &items = static_cast<HIR::TuplePatternItemsMultiple &> (
! 	  pattern.get_items ());
  
  	for (auto &sub : items.get_patterns ())
  	  {
--- 1069,1079 ----
  
  	return;
        }
!     case HIR::TuplePatternItems::ItemType::NO_REST:
        {
  	size_t tuple_idx = 0;
! 	auto &items
! 	  = static_cast<HIR::TuplePatternItemsNoRest &> (pattern.get_items ());
  
  	for (auto &sub : items.get_patterns ())
  	  {
*************** CompilePatternBindings::visit (HIR::Slic
*** 930,972 ****
  	       || lookup->get_kind () == TyTy::TypeKind::SLICE
  	       || lookup->get_kind () == TyTy::REF);
  
!   size_t array_element_index = 0;
    switch (lookup->get_kind ())
      {
      case TyTy::TypeKind::ARRAY:
!       for (auto &pattern_member : pattern.get_items ())
! 	{
! 	  tree array_index_tree
! 	    = Backend::size_constant_expression (array_element_index++);
! 	  tree element_expr
! 	    = Backend::array_index_expression (match_scrutinee_expr,
! 					       array_index_tree,
! 					       pattern.get_locus ());
! 	  CompilePatternBindings::Compile (*pattern_member, element_expr, ctx);
! 	}
        break;
      case TyTy::TypeKind::SLICE:
!       rust_sorry_at (
! 	pattern.get_locus (),
! 	"SlicePattern matching against non-ref slices are not yet supported");
        break;
      case TyTy::TypeKind::REF:
        {
! 	for (auto &pattern_member : pattern.get_items ())
  	  {
! 	    tree slice_index_tree
! 	      = Backend::size_constant_expression (array_element_index++);
  	    tree element_expr
! 	      = Backend::slice_index_expression (match_scrutinee_expr,
! 						 slice_index_tree,
! 						 pattern.get_locus ());
  	    CompilePatternBindings::Compile (*pattern_member, element_expr,
  					     ctx);
  	  }
- 	break;
        }
!     default:
!       rust_unreachable ();
      }
  }
  
--- 1112,1243 ----
  	       || lookup->get_kind () == TyTy::TypeKind::SLICE
  	       || lookup->get_kind () == TyTy::REF);
  
!   // function ptr that points to either array_index_expression or
!   // slice_index_expression depending on the scrutinee's type
!   tree (*scrutinee_index_expr_func) (tree, tree, location_t) = nullptr;
! 
    switch (lookup->get_kind ())
      {
      case TyTy::TypeKind::ARRAY:
!       scrutinee_index_expr_func = Backend::array_index_expression;
        break;
      case TyTy::TypeKind::SLICE:
!       rust_sorry_at (pattern.get_locus (),
! 		     "SlicePattern matching against non-ref slices are "
! 		     "not yet supported");
        break;
      case TyTy::TypeKind::REF:
+       scrutinee_index_expr_func = Backend::slice_index_expression;
+       break;
+     default:
+       rust_unreachable ();
+     }
+ 
+   rust_assert (scrutinee_index_expr_func != nullptr);
+ 
+   size_t element_index = 0;
+ 
+   switch (pattern.get_items ().get_item_type ())
+     {
+     case HIR::SlicePatternItems::ItemType::NO_REST:
        {
! 	auto &items
! 	  = static_cast<HIR::SlicePatternItemsNoRest &> (pattern.get_items ());
! 	for (auto &pattern_member : items.get_patterns ())
  	  {
! 	    tree index_tree
! 	      = Backend::size_constant_expression (element_index++);
  	    tree element_expr
! 	      = scrutinee_index_expr_func (match_scrutinee_expr, index_tree,
! 					   pattern.get_locus ());
  	    CompilePatternBindings::Compile (*pattern_member, element_expr,
  					     ctx);
  	  }
        }
!       break;
!     case HIR::SlicePatternItems::ItemType::HAS_REST:
!       {
! 	auto &items
! 	  = static_cast<HIR::SlicePatternItemsHasRest &> (pattern.get_items ());
! 	for (auto &pattern_member : items.get_lower_patterns ())
! 	  {
! 	    tree index_tree
! 	      = Backend::size_constant_expression (element_index++);
! 	    tree element_expr
! 	      = scrutinee_index_expr_func (match_scrutinee_expr, index_tree,
! 					   pattern.get_locus ());
! 	    CompilePatternBindings::Compile (*pattern_member, element_expr,
! 					     ctx);
! 	  }
! 
! 	// handle codegen for upper patterns differently for both types
! 	switch (lookup->get_kind ())
! 	  {
! 	  case TyTy::TypeKind::ARRAY:
! 	    {
! 	      auto array_ty = static_cast<TyTy::ArrayType *> (lookup);
! 	      auto capacity_ty = array_ty->get_capacity ();
! 
! 	      rust_assert (capacity_ty->get_kind () == TyTy::TypeKind::CONST);
! 	      auto *capacity_const = capacity_ty->as_const_type ();
! 	      rust_assert (capacity_const->const_kind ()
! 			   == TyTy::BaseConstType::ConstKind::Value);
! 	      auto &capacity_value
! 		= *static_cast<TyTy::ConstValueType *> (capacity_const);
! 	      auto cap_tree = capacity_value.get_value ();
! 
! 	      rust_assert (!error_operand_p (cap_tree));
! 
! 	      size_t cap_wi = (size_t) wi::to_wide (cap_tree).to_uhwi ();
! 	      element_index = cap_wi - items.get_upper_patterns ().size ();
! 	      for (auto &pattern_member : items.get_upper_patterns ())
! 		{
! 		  tree index_tree
! 		    = Backend::size_constant_expression (element_index++);
! 		  tree element_expr
! 		    = scrutinee_index_expr_func (match_scrutinee_expr,
! 						 index_tree,
! 						 pattern.get_locus ());
! 		  CompilePatternBindings::Compile (*pattern_member,
! 						   element_expr, ctx);
! 		}
! 	    }
! 	    break;
! 	  case TyTy::TypeKind::SLICE:
! 	    rust_sorry_at (pattern.get_locus (),
! 			   "SlicePattern matching against non-ref slices are "
! 			   "not yet supported");
! 	    break;
! 	  case TyTy::TypeKind::REF:
! 	    {
! 	      tree slice_size
! 		= Backend::struct_field_expression (match_scrutinee_expr, 1,
! 						    pattern.get_locus ());
! 	      tree upper_patterns_size = Backend::size_constant_expression (
! 		items.get_upper_patterns ().size ());
! 	      tree index_tree = Backend::arithmetic_or_logical_expression (
! 		ArithmeticOrLogicalOperator::SUBTRACT, slice_size,
! 		upper_patterns_size, pattern.get_locus ());
! 	      for (auto &pattern_member : items.get_upper_patterns ())
! 		{
! 		  tree element_expr
! 		    = scrutinee_index_expr_func (match_scrutinee_expr,
! 						 index_tree,
! 						 pattern.get_locus ());
! 		  CompilePatternBindings::Compile (*pattern_member,
! 						   element_expr, ctx);
! 		  index_tree = Backend::arithmetic_or_logical_expression (
! 		    ArithmeticOrLogicalOperator::ADD, index_tree,
! 		    Backend::size_constant_expression (1),
! 		    pattern.get_locus ());
! 		}
! 	    }
! 	    break;
! 	  default:
! 	    rust_unreachable ();
! 	  }
!       }
!       break;
      }
  }
  
*************** CompilePatternLet::visit (HIR::Identifie
*** 979,984 ****
--- 1250,1260 ----
    rust_assert (
      ctx->lookup_var_decl (pattern.get_mappings ().get_hirid (), &var));
  
+   if (pattern.get_is_ref ())
+     {
+       init_expr = address_expression (init_expr, EXPR_LOCATION (init_expr));
+     }
+ 
    auto fnctx = ctx->peek_fn ();
    if (ty->is_unit ())
      {
*************** CompilePatternLet::visit (HIR::Identifie
*** 990,995 ****
--- 1266,1276 ----
      }
    else
      {
+       if (pattern.has_subpattern ())
+ 	{
+ 	  CompilePatternLet::Compile (&pattern.get_subpattern (), init_expr, ty,
+ 				      rval_locus, ctx);
+ 	}
        auto s = Backend::init_statement (fnctx.fndecl, var, init_expr);
        ctx->add_statement (s);
      }
*************** CompilePatternLet::visit (HIR::TuplePatt
*** 1013,1034 ****
  {
    rust_assert (pattern.has_tuple_pattern_items ());
  
!   tree tuple_type = TyTyResolveCompile::compile (ctx, ty);
    tree init_stmt;
    Bvariable *tmp_var
      = Backend::temporary_variable (ctx->peek_fn ().fndecl, NULL_TREE,
! 				   tuple_type, init_expr, false,
  				   pattern.get_locus (), &init_stmt);
    tree access_expr = Backend::var_expression (tmp_var, pattern.get_locus ());
    ctx->add_statement (init_stmt);
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::RANGED:
        {
  	size_t tuple_idx = 0;
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsRanged &> (pattern.get_items ());
  
  	auto &items_lower = items.get_lower_patterns ();
  	auto &items_upper = items.get_upper_patterns ();
--- 1294,1358 ----
  {
    rust_assert (pattern.has_tuple_pattern_items ());
  
!   bool has_by_ref = false;
!   auto check_refs
!     = [] (const std::vector<std::unique_ptr<HIR::Pattern>> &patterns) {
! 	for (const auto &sub : patterns)
! 	  {
! 	    switch (sub->get_pattern_type ())
! 	      {
! 	      case HIR::Pattern::PatternType::IDENTIFIER:
! 		{
! 		  auto id = static_cast<HIR::IdentifierPattern *> (sub.get ());
! 		  if (id->get_is_ref ())
! 		    return true;
! 		  break;
! 		}
! 	      case HIR::Pattern::PatternType::REFERENCE:
! 		return true;
! 	      default:
! 		break;
! 	      }
! 	  }
! 	return false;
!       };
!   switch (pattern.get_items ().get_item_type ())
!     {
!     case HIR::TuplePatternItems::ItemType::NO_REST:
!       {
! 	auto &items
! 	  = static_cast<HIR::TuplePatternItemsNoRest &> (pattern.get_items ());
! 	has_by_ref = check_refs (items.get_patterns ());
! 	break;
!       }
!     case HIR::TuplePatternItems::ItemType::HAS_REST:
!       {
! 	auto &items
! 	  = static_cast<HIR::TuplePatternItemsHasRest &> (pattern.get_items ());
! 	has_by_ref = check_refs (items.get_lower_patterns ())
! 		     || check_refs (items.get_upper_patterns ());
! 	break;
!       }
!     default:
!       break;
!     }
! 
!   tree rhs_tuple_type = TYPE_MAIN_VARIANT (TREE_TYPE (init_expr));
    tree init_stmt;
    Bvariable *tmp_var
      = Backend::temporary_variable (ctx->peek_fn ().fndecl, NULL_TREE,
! 				   rhs_tuple_type, init_expr, has_by_ref,
  				   pattern.get_locus (), &init_stmt);
    tree access_expr = Backend::var_expression (tmp_var, pattern.get_locus ());
    ctx->add_statement (init_stmt);
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::HAS_REST:
        {
  	size_t tuple_idx = 0;
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsHasRest &> (pattern.get_items ());
  
  	auto &items_lower = items.get_lower_patterns ();
  	auto &items_upper = items.get_upper_patterns ();
*************** CompilePatternLet::visit (HIR::TuplePatt
*** 1069,1079 ****
  
  	return;
        }
!     case HIR::TuplePatternItems::ItemType::MULTIPLE:
        {
  	size_t tuple_idx = 0;
! 	auto &items = static_cast<HIR::TuplePatternItemsMultiple &> (
! 	  pattern.get_items ());
  
  	for (auto &sub : items.get_patterns ())
  	  {
--- 1393,1403 ----
  
  	return;
        }
!     case HIR::TuplePatternItems::ItemType::NO_REST:
        {
  	size_t tuple_idx = 0;
! 	auto &items
! 	  = static_cast<HIR::TuplePatternItemsNoRest &> (pattern.get_items ());
  
  	for (auto &sub : items.get_patterns ())
  	  {
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-resolve-path.cc gcc-16-20251102/gcc/rust/backend/rust-compile-resolve-path.cc
*** gcc-16-20251026/gcc/rust/backend/rust-compile-resolve-path.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-resolve-path.cc	Sun Nov  2 22:32:23 2025
*************** ResolvePathRef::attempt_constructor_expr
*** 97,104 ****
  
    // this can only be for discriminant variants the others are built up
    // using call-expr or struct-init
!   rust_assert (variant->get_variant_type ()
! 	       == TyTy::VariantDef::VariantType::NUM);
  
    // we need the actual gcc type
    tree compiled_adt_type = TyTyResolveCompile::compile (ctx, adt);
--- 97,107 ----
  
    // this can only be for discriminant variants the others are built up
    // using call-expr or struct-init
!   if (variant->get_variant_type () != TyTy::VariantDef::VariantType::NUM)
!     {
!       rust_error_at (expr_locus, "variant expected constructor call");
!       return error_mark_node;
!     }
  
    // we need the actual gcc type
    tree compiled_adt_type = TyTyResolveCompile::compile (ctx, adt);
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-type.cc gcc-16-20251102/gcc/rust/backend/rust-compile-type.cc
*** gcc-16-20251026/gcc/rust/backend/rust-compile-type.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-type.cc	Sun Nov  2 22:32:23 2025
*************** TyTyResolveCompile::visit (const TyTy::I
*** 136,148 ****
  }
  
  void
! TyTyResolveCompile::visit (const TyTy::ParamType &)
  {
    translated = error_mark_node;
  }
  
  void
! TyTyResolveCompile::visit (const TyTy::ConstType &)
  {
    translated = error_mark_node;
  }
--- 136,166 ----
  }
  
  void
! TyTyResolveCompile::visit (const TyTy::ParamType &type)
  {
    translated = error_mark_node;
  }
  
  void
! TyTyResolveCompile::visit (const TyTy::ConstParamType &type)
! {
!   translated = error_mark_node;
! }
! 
! void
! TyTyResolveCompile::visit (const TyTy::ConstValueType &type)
! {
!   translated = error_mark_node;
! }
! 
! void
! TyTyResolveCompile::visit (const TyTy::ConstInferType &type)
! {
!   translated = error_mark_node;
! }
! 
! void
! TyTyResolveCompile::visit (const TyTy::ConstErrorType &type)
  {
    translated = error_mark_node;
  }
*************** TyTyResolveCompile::visit (const TyTy::C
*** 186,193 ****
        // this should be based on the closure move-ability
        tree decl_type = TyTyResolveCompile::compile (ctx, lookup);
        tree capture_type = build_reference_type (decl_type);
!       fields.push_back (Backend::typed_identifier (mappings_name, capture_type,
! 						   type.get_ident ().locus));
      }
  
    tree type_record = Backend::struct_type (fields);
--- 204,211 ----
        // this should be based on the closure move-ability
        tree decl_type = TyTyResolveCompile::compile (ctx, lookup);
        tree capture_type = build_reference_type (decl_type);
!       fields.emplace_back (mappings_name, capture_type,
! 			   type.get_ident ().locus);
      }
  
    tree type_record = Backend::struct_type (fields);
*************** TyTyResolveCompile::visit (const TyTy::F
*** 217,224 ****
        auto ret = TyTyResolveCompile::compile (ctx, hir_type, trait_object_mode);
        location_t return_type_locus
  	= ctx->get_mappings ().lookup_location (hir_type->get_ref ());
!       results.push_back (
! 	Backend::typed_identifier ("_", ret, return_type_locus));
      }
  
    for (auto &param_pair : type.get_params ())
--- 235,241 ----
        auto ret = TyTyResolveCompile::compile (ctx, hir_type, trait_object_mode);
        location_t return_type_locus
  	= ctx->get_mappings ().lookup_location (hir_type->get_ref ());
!       results.emplace_back ("_", ret, return_type_locus);
      }
  
    for (auto &param_pair : type.get_params ())
*************** TyTyResolveCompile::visit (const TyTy::F
*** 227,237 ****
        auto compiled_param_type
  	= TyTyResolveCompile::compile (ctx, param_tyty, trait_object_mode);
  
!       auto compiled_param = Backend::typed_identifier (
! 	param_pair.get_pattern ().as_string (), compiled_param_type,
! 	ctx->get_mappings ().lookup_location (param_tyty->get_ref ()));
! 
!       parameters.push_back (compiled_param);
      }
  
    if (!type.is_variadic ())
--- 244,253 ----
        auto compiled_param_type
  	= TyTyResolveCompile::compile (ctx, param_tyty, trait_object_mode);
  
!       parameters.emplace_back (param_pair.get_pattern ().as_string (),
! 			       compiled_param_type,
! 			       ctx->get_mappings ().lookup_location (
! 				 param_tyty->get_ref ()));
      }
  
    if (!type.is_variadic ())
*************** TyTyResolveCompile::visit (const TyTy::A
*** 277,286 ****
  	  tree compiled_field_ty
  	    = TyTyResolveCompile::compile (ctx, field->get_field_type ());
  
! 	  Backend::typed_identifier f (field->get_name (), compiled_field_ty,
! 				       ctx->get_mappings ().lookup_location (
! 					 type.get_ty_ref ()));
! 	  fields.push_back (std::move (f));
  	}
  
        type_record = type.is_union () ? Backend::union_type (fields, false)
--- 293,301 ----
  	  tree compiled_field_ty
  	    = TyTyResolveCompile::compile (ctx, field->get_field_type ());
  
! 	  fields.emplace_back (field->get_name (), compiled_field_ty,
! 			       ctx->get_mappings ().lookup_location (
! 				 type.get_ty_ref ()));
  	}
  
        type_record = type.is_union () ? Backend::union_type (fields, false)
*************** TyTyResolveCompile::visit (const TyTy::A
*** 357,366 ****
  		  == TyTy::VariantDef::VariantType::TUPLE)
  		field_name = "__" + field->get_name ();
  
! 	      Backend::typed_identifier f (
! 		field_name, compiled_field_ty,
! 		ctx->get_mappings ().lookup_location (type.get_ty_ref ()));
! 	      fields.push_back (std::move (f));
  	    }
  
  	  tree variant_record = Backend::struct_type (fields);
--- 372,380 ----
  		  == TyTy::VariantDef::VariantType::TUPLE)
  		field_name = "__" + field->get_name ();
  
! 	      fields.emplace_back (field_name, compiled_field_ty,
! 				   ctx->get_mappings ().lookup_location (
! 				     type.get_ty_ref ()));
  	    }
  
  	  tree variant_record = Backend::struct_type (fields);
*************** TyTyResolveCompile::visit (const TyTy::A
*** 382,391 ****
  	  TyTy::VariantDef *variant = type.get_variants ().at (i++);
  	  std::string implicit_variant_name = variant->get_identifier ();
  
! 	  Backend::typed_identifier f (implicit_variant_name, variant_record,
! 				       ctx->get_mappings ().lookup_location (
! 					 type.get_ty_ref ()));
! 	  enum_fields.push_back (std::move (f));
  	}
  
        //
--- 396,404 ----
  	  TyTy::VariantDef *variant = type.get_variants ().at (i++);
  	  std::string implicit_variant_name = variant->get_identifier ();
  
! 	  enum_fields.emplace_back (implicit_variant_name, variant_record,
! 				    ctx->get_mappings ().lookup_location (
! 				      type.get_ty_ref ()));
  	}
  
        //
*************** TyTyResolveCompile::visit (const TyTy::T
*** 460,469 ****
        // this, rather than simply emitting the integer, is that this
        // approach makes it simpler to use a C-only debugger, or
        // GDB's C mode, when debugging Rust.
!       Backend::typed_identifier f ("__" + std::to_string (i), compiled_field_ty,
! 				   ctx->get_mappings ().lookup_location (
! 				     type.get_ty_ref ()));
!       fields.push_back (std::move (f));
      }
  
    tree struct_type_record = Backend::struct_type (fields);
--- 473,481 ----
        // this, rather than simply emitting the integer, is that this
        // approach makes it simpler to use a C-only debugger, or
        // GDB's C mode, when debugging Rust.
!       fields.emplace_back ("__" + std::to_string (i), compiled_field_ty,
! 			   ctx->get_mappings ().lookup_location (
! 			     type.get_ty_ref ()));
      }
  
    tree struct_type_record = Backend::struct_type (fields);
*************** TyTyResolveCompile::visit (const TyTy::A
*** 476,483 ****
  {
    tree element_type
      = TyTyResolveCompile::compile (ctx, type.get_element_type ());
!   TyTy::ConstType *const_capacity = type.get_capacity ();
!   tree folded_capacity_expr = const_capacity->get_value ();
  
    // build_index_type takes the maximum index, which is one less than
    // the length.
--- 488,509 ----
  {
    tree element_type
      = TyTyResolveCompile::compile (ctx, type.get_element_type ());
!   auto const_capacity = type.get_capacity ();
! 
!   // Check if capacity is a const type
!   if (const_capacity->get_kind () != TyTy::TypeKind::CONST)
!     {
!       rust_error_at (type.get_locus (), "array capacity is not a const type");
!       translated = error_mark_node;
!       return;
!     }
! 
!   auto *capacity_const = const_capacity->as_const_type ();
! 
!   rust_assert (capacity_const->const_kind ()
! 	       == TyTy::BaseConstType::ConstKind::Value);
!   auto &capacity_value = *static_cast<TyTy::ConstValueType *> (capacity_const);
!   auto folded_capacity_expr = capacity_value.get_value ();
  
    // build_index_type takes the maximum index, which is one less than
    // the length.
*************** TyTyResolveCompile::create_dyn_obj_recor
*** 772,788 ****
    tree uint = Backend::integer_type (true, Backend::get_pointer_size ());
    tree uintptr_ty = build_pointer_type (uint);
  
!   Backend::typed_identifier f ("pointer", uintptr_ty,
! 			       ctx->get_mappings ().lookup_location (
! 				 type.get_ty_ref ()));
!   fields.push_back (std::move (f));
  
    tree vtable_size = build_int_cst (size_type_node, items.size ());
    tree vtable_type = Backend::array_type (uintptr_ty, vtable_size);
!   Backend::typed_identifier vtf ("vtable", vtable_type,
! 				 ctx->get_mappings ().lookup_location (
! 				   type.get_ty_ref ()));
!   fields.push_back (std::move (vtf));
  
    tree record = Backend::struct_type (fields);
    RS_DST_FLAG (record) = 1;
--- 798,812 ----
    tree uint = Backend::integer_type (true, Backend::get_pointer_size ());
    tree uintptr_ty = build_pointer_type (uint);
  
!   fields.emplace_back ("pointer", uintptr_ty,
! 		       ctx->get_mappings ().lookup_location (
! 			 type.get_ty_ref ()));
  
    tree vtable_size = build_int_cst (size_type_node, items.size ());
    tree vtable_type = Backend::array_type (uintptr_ty, vtable_size);
!   fields.emplace_back ("vtable", vtable_type,
! 		       ctx->get_mappings ().lookup_location (
! 			 type.get_ty_ref ()));
  
    tree record = Backend::struct_type (fields);
    RS_DST_FLAG (record) = 1;
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-type.h gcc-16-20251102/gcc/rust/backend/rust-compile-type.h
*** gcc-16-20251026/gcc/rust/backend/rust-compile-type.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-type.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 50,56 ****
    void visit (const TyTy::ReferenceType &) override;
    void visit (const TyTy::PointerType &) override;
    void visit (const TyTy::ParamType &) override;
!   void visit (const TyTy::ConstType &) override;
    void visit (const TyTy::StrType &) override;
    void visit (const TyTy::NeverType &) override;
    void visit (const TyTy::PlaceholderType &) override;
--- 50,59 ----
    void visit (const TyTy::ReferenceType &) override;
    void visit (const TyTy::PointerType &) override;
    void visit (const TyTy::ParamType &) override;
!   void visit (const TyTy::ConstParamType &) override;
!   void visit (const TyTy::ConstValueType &) override;
!   void visit (const TyTy::ConstInferType &) override;
!   void visit (const TyTy::ConstErrorType &) override;
    void visit (const TyTy::StrType &) override;
    void visit (const TyTy::NeverType &) override;
    void visit (const TyTy::PlaceholderType &) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile-var-decl.h gcc-16-20251102/gcc/rust/backend/rust-compile-var-decl.h
*** gcc-16-20251026/gcc/rust/backend/rust-compile-var-decl.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile-var-decl.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 64,94 ****
      ctx->insert_var_decl (stmt_id, var);
  
      vars.push_back (var);
    }
  
    void visit (HIR::TuplePattern &pattern) override
    {
      switch (pattern.get_items ().get_item_type ())
        {
!       case HIR::TuplePatternItems::ItemType::MULTIPLE:
  	{
! 	  rust_assert (TREE_CODE (translated_type) == RECORD_TYPE);
! 	  auto &items = static_cast<HIR::TuplePatternItemsMultiple &> (
  	    pattern.get_items ());
  
! 	  size_t offs = 0;
! 	  for (auto &sub : items.get_patterns ())
  	    {
! 	      tree sub_ty = error_mark_node;
! 	      tree field = TYPE_FIELDS (translated_type);
! 	      for (size_t i = 0; i < offs; i++)
  		{
  		  field = DECL_CHAIN (field);
  		  gcc_assert (field != NULL_TREE);
  		}
! 	      sub_ty = TREE_TYPE (field);
! 	      CompileVarDecl::compile (fndecl, sub_ty, sub.get (), ctx);
! 	      offs++;
  	    }
  	}
  	break;
--- 64,142 ----
      ctx->insert_var_decl (stmt_id, var);
  
      vars.push_back (var);
+ 
+     if (pattern.has_subpattern ())
+       {
+ 	auto subpattern_vars
+ 	  = CompileVarDecl::compile (fndecl, translated_type,
+ 				     &pattern.get_subpattern (), ctx);
+ 	vars.insert (vars.end (), subpattern_vars.begin (),
+ 		     subpattern_vars.end ());
+       }
    }
  
    void visit (HIR::TuplePattern &pattern) override
    {
+     rust_assert (TREE_CODE (translated_type) == RECORD_TYPE);
      switch (pattern.get_items ().get_item_type ())
        {
!       case HIR::TuplePatternItems::ItemType::NO_REST:
  	{
! 	  auto &items_no_rest = static_cast<HIR::TuplePatternItemsNoRest &> (
  	    pattern.get_items ());
  
! 	  tree field = TYPE_FIELDS (translated_type);
! 	  for (auto &sub : items_no_rest.get_patterns ())
  	    {
! 	      gcc_assert (field != NULL_TREE);
! 	      tree sub_ty = TREE_TYPE (field);
! 	      CompileVarDecl::compile (fndecl, sub_ty, sub.get (), ctx);
! 	      field = DECL_CHAIN (field);
! 	    }
! 	}
! 	break;
! 
!       case HIR::TuplePatternItems::ItemType::HAS_REST:
! 	{
! 	  auto &items_has_rest = static_cast<HIR::TuplePatternItemsHasRest &> (
! 	    pattern.get_items ());
! 
! 	  // count total fields in translated_type
! 	  size_t total_fields = 0;
! 	  for (tree t = TYPE_FIELDS (translated_type); t; t = DECL_CHAIN (t))
! 	    {
! 	      total_fields++;
! 	    }
! 
! 	  // process lower patterns
! 	  tree field = TYPE_FIELDS (translated_type);
! 	  for (auto &sub : items_has_rest.get_lower_patterns ())
! 	    {
! 	      gcc_assert (field != NULL_TREE);
! 	      tree sub_ty = TREE_TYPE (field);
! 	      CompileVarDecl::compile (fndecl, sub_ty, sub.get (), ctx);
! 	      field = DECL_CHAIN (field);
! 	    }
! 
! 	  // process upper patterns
! 	  if (!items_has_rest.get_upper_patterns ().empty ())
! 	    {
! 	      size_t upper_start
! 		= total_fields - items_has_rest.get_upper_patterns ().size ();
! 	      field = TYPE_FIELDS (translated_type);
! 	      for (size_t i = 0; i < upper_start; i++)
  		{
  		  field = DECL_CHAIN (field);
  		  gcc_assert (field != NULL_TREE);
  		}
! 
! 	      for (auto &sub : items_has_rest.get_upper_patterns ())
! 		{
! 		  gcc_assert (field != NULL_TREE);
! 		  tree sub_ty = TREE_TYPE (field);
! 		  CompileVarDecl::compile (fndecl, sub_ty, sub.get (), ctx);
! 		  field = DECL_CHAIN (field);
! 		}
  	    }
  	}
  	break;
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-compile.cc gcc-16-20251102/gcc/rust/backend/rust-compile.cc
*** gcc-16-20251026/gcc/rust/backend/rust-compile.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-compile.cc	Sun Nov  2 22:32:23 2025
*************** HIRCompileBase::coercion_site1 (tree rva
*** 183,190 ****
  }
  
  tree
! HIRCompileBase::coerce_to_dyn_object (tree compiled_ref,
! 				      const TyTy::BaseType *actual,
  				      const TyTy::DynamicObjectType *ty,
  				      location_t locus)
  {
--- 183,189 ----
  }
  
  tree
! HIRCompileBase::coerce_to_dyn_object (tree compiled_ref, TyTy::BaseType *actual,
  				      const TyTy::DynamicObjectType *ty,
  				      location_t locus)
  {
*************** HIRCompileBase::coerce_to_dyn_object (tr
*** 201,209 ****
    // __trait_object_ptr
    // [list of function ptrs]
  
!   std::vector<std::pair<Resolver::TraitReference *, HIR::ImplBlock *>>
!     probed_bounds_for_receiver = Resolver::TypeBoundsProbe::Probe (actual);
! 
    tree address_of_compiled_ref = null_pointer_node;
    if (!actual->is_unit ())
      address_of_compiled_ref = address_expression (compiled_ref, locus);
--- 200,206 ----
    // __trait_object_ptr
    // [list of function ptrs]
  
!   auto probed_bounds_for_receiver = Resolver::TypeBoundsProbe::Probe (actual);
    tree address_of_compiled_ref = null_pointer_node;
    if (!actual->is_unit ())
      address_of_compiled_ref = address_expression (compiled_ref, locus);
*************** HIRCompileBase::compute_address_for_trai
*** 241,252 ****
      &receiver_bounds,
    const TyTy::BaseType *receiver, const TyTy::BaseType *root, location_t locus)
  {
!   TyTy::TypeBoundPredicateItem predicate_item
      = predicate->lookup_associated_item (ref->get_identifier ());
!   rust_assert (!predicate_item.is_error ());
  
    // This is the expected end type
!   TyTy::BaseType *trait_item_type = predicate_item.get_tyty_for_receiver (root);
    rust_assert (trait_item_type->get_kind () == TyTy::TypeKind::FNDEF);
    TyTy::FnType *trait_item_fntype
      = static_cast<TyTy::FnType *> (trait_item_type);
--- 238,250 ----
      &receiver_bounds,
    const TyTy::BaseType *receiver, const TyTy::BaseType *root, location_t locus)
  {
!   tl::optional<TyTy::TypeBoundPredicateItem> predicate_item
      = predicate->lookup_associated_item (ref->get_identifier ());
!   rust_assert (predicate_item.has_value ());
  
    // This is the expected end type
!   TyTy::BaseType *trait_item_type
!     = predicate_item->get_tyty_for_receiver (root);
    rust_assert (trait_item_type->get_kind () == TyTy::TypeKind::FNDEF);
    TyTy::FnType *trait_item_fntype
      = static_cast<TyTy::FnType *> (trait_item_type);
diff -Nrcpad gcc-16-20251026/gcc/rust/backend/rust-constexpr.cc gcc-16-20251102/gcc/rust/backend/rust-constexpr.cc
*** gcc-16-20251026/gcc/rust/backend/rust-constexpr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/backend/rust-constexpr.cc	Sun Nov  2 22:32:23 2025
*************** struct constexpr_global_ctx
*** 101,112 ****
--- 101,154 ----
    auto_vec<tree, 16> heap_vars;
    /* Cleanups that need to be evaluated at the end of CLEANUP_POINT_EXPR.  */
    vec<tree> *cleanups;
+   /* If non-null, only allow modification of existing values of the variables
+      in this set.  Set by modifiable_tracker, below.  */
+   hash_set<tree> *modifiable;
    /* Number of heap VAR_DECL deallocations.  */
    unsigned heap_dealloc_count;
    /* Constructor.  */
    constexpr_global_ctx ()
      : constexpr_ops_count (0), cleanups (NULL), heap_dealloc_count (0)
    {}
+ 
+   tree get_value (tree t)
+   {
+     if (tree *p = values.get (t))
+       if (*p != void_node)
+ 	return *p;
+     return NULL_TREE;
+   }
+   tree *get_value_ptr (tree t, bool initializing)
+   {
+     if (modifiable && !modifiable->contains (t))
+       return nullptr;
+     if (tree *p = values.get (t))
+       {
+ 	if (*p != void_node)
+ 	  return p;
+ 	else if (initializing)
+ 	  {
+ 	    *p = NULL_TREE;
+ 	    return p;
+ 	  }
+       }
+     return nullptr;
+   }
+   void put_value (tree t, tree v)
+   {
+     bool already_in_map = values.put (t, v);
+     if (!already_in_map && modifiable)
+       modifiable->add (t);
+   }
+   void destroy_value (tree t)
+   {
+     if (TREE_CODE (t) == VAR_DECL || TREE_CODE (t) == PARM_DECL
+ 	|| TREE_CODE (t) == RESULT_DECL)
+       values.put (t, void_node);
+     else
+       values.remove (t);
+   }
+   void clear_value (tree t) { values.remove (t); }
  };
  
  /* In constexpr.cc */
*************** save_fundef_copy (tree fun, tree copy)
*** 457,479 ****
  
  static tree constant_value_1 (tree decl, bool strict_p,
  			      bool return_aggregate_cst_ok_p, bool unshare_p);
  tree decl_constant_value (tree decl, bool unshare_p);
  
  static void non_const_var_error (location_t loc, tree r);
  
  static tree eval_constant_expression (const constexpr_ctx *ctx, tree, bool,
! 				      bool *, bool *, tree * = NULL);
  
  static tree constexpr_fn_retval (const constexpr_ctx *ctx, tree r);
  
  static tree eval_store_expression (const constexpr_ctx *ctx, tree r, bool,
! 				   bool *, bool *);
  
  static tree eval_call_expression (const constexpr_ctx *ctx, tree r, bool,
! 				  bool *, bool *);
  
  static tree eval_binary_expression (const constexpr_ctx *ctx, tree r, bool,
! 				    bool *, bool *);
  
  static tree get_function_named_in_call (tree t);
  
--- 499,522 ----
  
  static tree constant_value_1 (tree decl, bool strict_p,
  			      bool return_aggregate_cst_ok_p, bool unshare_p);
+ static tree decl_really_constant_value (tree decl, bool unshare_p /*= true*/);
  tree decl_constant_value (tree decl, bool unshare_p);
  
  static void non_const_var_error (location_t loc, tree r);
  
  static tree eval_constant_expression (const constexpr_ctx *ctx, tree, bool,
! 				      bool *, bool *, tree *jump_target);
  
  static tree constexpr_fn_retval (const constexpr_ctx *ctx, tree r);
  
  static tree eval_store_expression (const constexpr_ctx *ctx, tree r, bool,
! 				   bool *, bool *, tree *jump_target);
  
  static tree eval_call_expression (const constexpr_ctx *ctx, tree r, bool,
! 				  bool *, bool *, tree *);
  
  static tree eval_binary_expression (const constexpr_ctx *ctx, tree r, bool,
! 				    bool *, bool *, tree *jump_target);
  
  static tree get_function_named_in_call (tree t);
  
*************** static tree eval_conditional_expression
*** 488,494 ****
  					 bool *overflow_p, tree *jump_target);
  
  static tree eval_bit_field_ref (const constexpr_ctx *ctx, tree t, bool lval,
! 				bool *non_constant_p, bool *overflow_p);
  
  static tree eval_loop_expr (const constexpr_ctx *ctx, tree t,
  			    bool *non_constant_p, bool *overflow_p,
--- 531,538 ----
  					 bool *overflow_p, tree *jump_target);
  
  static tree eval_bit_field_ref (const constexpr_ctx *ctx, tree t, bool lval,
! 				bool *non_constant_p, bool *overflow_p,
! 				tree *jump_target);
  
  static tree eval_loop_expr (const constexpr_ctx *ctx, tree t,
  			    bool *non_constant_p, bool *overflow_p,
*************** static tree eval_switch_expr (const cons
*** 500,506 ****
  
  static tree eval_unary_expression (const constexpr_ctx *ctx, tree t,
  				   bool /*lval*/, bool *non_constant_p,
! 				   bool *overflow_p);
  
  /* Variables and functions to manage constexpr call expansion context.
     These do not need to be marked for PCH or GC.  */
--- 544,558 ----
  
  static tree eval_unary_expression (const constexpr_ctx *ctx, tree t,
  				   bool /*lval*/, bool *non_constant_p,
! 				   bool *overflow_p, tree *jump_target);
! static bool eval_check_shift_p (location_t loc, const constexpr_ctx *ctx,
! 				enum tree_code code, tree type, tree lhs,
! 				tree rhs);
! static tree fold_pointer_plus_expression (const constexpr_ctx *ctx, tree t,
! 					  tree lhs, tree rhs,
! 					  bool *non_constant_p,
! 					  bool *overflow_p, tree *jump_target);
! static tree maybe_fold_addr_pointer_plus (tree t);
  
  /* Variables and functions to manage constexpr call expansion context.
     These do not need to be marked for PCH or GC.  */
*************** fold_expr (tree expr)
*** 562,569 ****
    bool non_constant_p = false;
    bool overflow_p = false;
  
    tree folded = eval_constant_expression (&ctx, expr, false, &non_constant_p,
! 					  &overflow_p);
    rust_assert (folded != NULL_TREE);
  
    // more logic here to possibly port
--- 614,622 ----
    bool non_constant_p = false;
    bool overflow_p = false;
  
+   tree jump_target = NULL_TREE;
    tree folded = eval_constant_expression (&ctx, expr, false, &non_constant_p,
! 					  &overflow_p, &jump_target);
    rust_assert (folded != NULL_TREE);
  
    // more logic here to possibly port
*************** same_type_ignoring_tlq_and_bounds_p (tre
*** 589,601 ****
     otherwise return NULL_TREE.  */
  
  static tree
! union_active_member (const constexpr_ctx *ctx, tree t)
  {
    constexpr_ctx new_ctx = *ctx;
    new_ctx.quiet = true;
    bool non_constant_p = false, overflow_p = false;
    tree ctor = eval_constant_expression (&new_ctx, t, false, &non_constant_p,
! 					&overflow_p);
    if (TREE_CODE (ctor) == CONSTRUCTOR && CONSTRUCTOR_NELTS (ctor) == 1
        && CONSTRUCTOR_ELT (ctor, 0)->index
        && TREE_CODE (CONSTRUCTOR_ELT (ctor, 0)->index) == FIELD_DECL)
--- 642,654 ----
     otherwise return NULL_TREE.  */
  
  static tree
! union_active_member (const constexpr_ctx *ctx, tree t, tree *jump_target)
  {
    constexpr_ctx new_ctx = *ctx;
    new_ctx.quiet = true;
    bool non_constant_p = false, overflow_p = false;
    tree ctor = eval_constant_expression (&new_ctx, t, false, &non_constant_p,
! 					&overflow_p, jump_target);
    if (TREE_CODE (ctor) == CONSTRUCTOR && CONSTRUCTOR_NELTS (ctor) == 1
        && CONSTRUCTOR_ELT (ctor, 0)->index
        && TREE_CODE (CONSTRUCTOR_ELT (ctor, 0)->index) == FIELD_DECL)
*************** union_active_member (const constexpr_ctx
*** 607,613 ****
  
  static tree
  fold_indirect_ref_1 (const constexpr_ctx *ctx, location_t loc, tree type,
! 		     tree op, unsigned HOST_WIDE_INT off, bool *empty_base)
  {
    tree optype = TREE_TYPE (op);
    unsigned HOST_WIDE_INT const_nunits;
--- 660,667 ----
  
  static tree
  fold_indirect_ref_1 (const constexpr_ctx *ctx, location_t loc, tree type,
! 		     tree op, unsigned HOST_WIDE_INT off, bool *empty_base,
! 		     tree *jump_target)
  {
    tree optype = TREE_TYPE (op);
    unsigned HOST_WIDE_INT const_nunits;
*************** fold_indirect_ref_1 (const constexpr_ctx
*** 654,660 ****
  	  tree index = size_int (idx + tree_to_uhwi (min_val));
  	  op = build4_loc (loc, ARRAY_REF, TREE_TYPE (optype), op, index,
  			   NULL_TREE, NULL_TREE);
! 	  return fold_indirect_ref_1 (ctx, loc, type, op, rem, empty_base);
  	}
      }
    /* ((foo *)&struct_with_foo_field)[x] => COMPONENT_REF */
--- 708,715 ----
  	  tree index = size_int (idx + tree_to_uhwi (min_val));
  	  op = build4_loc (loc, ARRAY_REF, TREE_TYPE (optype), op, index,
  			   NULL_TREE, NULL_TREE);
! 	  return fold_indirect_ref_1 (ctx, loc, type, op, rem, empty_base,
! 				      jump_target);
  	}
      }
    /* ((foo *)&struct_with_foo_field)[x] => COMPONENT_REF */
*************** fold_indirect_ref_1 (const constexpr_ctx
*** 663,669 ****
      {
        if (TREE_CODE (optype) == UNION_TYPE)
  	/* For unions prefer the currently active member.  */
! 	if (tree field = union_active_member (ctx, op))
  	  {
  	    unsigned HOST_WIDE_INT el_sz
  	      = tree_to_uhwi (TYPE_SIZE_UNIT (TREE_TYPE (field)));
--- 718,724 ----
      {
        if (TREE_CODE (optype) == UNION_TYPE)
  	/* For unions prefer the currently active member.  */
! 	if (tree field = union_active_member (ctx, op, jump_target))
  	  {
  	    unsigned HOST_WIDE_INT el_sz
  	      = tree_to_uhwi (TYPE_SIZE_UNIT (TREE_TYPE (field)));
*************** fold_indirect_ref_1 (const constexpr_ctx
*** 672,678 ****
  		tree cop = build3 (COMPONENT_REF, TREE_TYPE (field), op, field,
  				   NULL_TREE);
  		if (tree ret = fold_indirect_ref_1 (ctx, loc, type, cop, off,
! 						    empty_base))
  		  return ret;
  	      }
  	  }
--- 727,733 ----
  		tree cop = build3 (COMPONENT_REF, TREE_TYPE (field), op, field,
  				   NULL_TREE);
  		if (tree ret = fold_indirect_ref_1 (ctx, loc, type, cop, off,
! 						    empty_base, jump_target))
  		  return ret;
  	      }
  	  }
*************** fold_indirect_ref_1 (const constexpr_ctx
*** 691,698 ****
  	      {
  		tree cop = build3 (COMPONENT_REF, TREE_TYPE (field), op, field,
  				   NULL_TREE);
! 		if (tree ret = fold_indirect_ref_1 (ctx, loc, type, cop,
! 						    off - upos, empty_base))
  		  return ret;
  	      }
  	  }
--- 746,754 ----
  	      {
  		tree cop = build3 (COMPONENT_REF, TREE_TYPE (field), op, field,
  				   NULL_TREE);
! 		if (tree ret
! 		    = fold_indirect_ref_1 (ctx, loc, type, cop, off - upos,
! 					   empty_base, jump_target))
  		  return ret;
  	      }
  	  }
*************** fold_indirect_ref_1 (const constexpr_ctx
*** 721,727 ****
  
  static tree
  rs_fold_indirect_ref (const constexpr_ctx *ctx, location_t loc, tree type,
! 		      tree op0, bool *empty_base)
  {
    tree sub = op0;
    tree subtype;
--- 777,783 ----
  
  static tree
  rs_fold_indirect_ref (const constexpr_ctx *ctx, location_t loc, tree type,
! 		      tree op0, bool *empty_base, tree *jump_target)
  {
    tree sub = op0;
    tree subtype;
*************** rs_fold_indirect_ref (const constexpr_ct
*** 780,786 ****
  	  tree off = integer_zero_node;
  	  canonicalize_obj_off (op, off);
  	  gcc_assert (integer_zerop (off));
! 	  return fold_indirect_ref_1 (ctx, loc, type, op, 0, empty_base);
  	}
      }
    else if (TREE_CODE (sub) == POINTER_PLUS_EXPR
--- 836,843 ----
  	  tree off = integer_zero_node;
  	  canonicalize_obj_off (op, off);
  	  gcc_assert (integer_zerop (off));
! 	  return fold_indirect_ref_1 (ctx, loc, type, op, 0, empty_base,
! 				      jump_target);
  	}
      }
    else if (TREE_CODE (sub) == POINTER_PLUS_EXPR
*************** rs_fold_indirect_ref (const constexpr_ct
*** 795,801 ****
  	  tree obj = TREE_OPERAND (op00, 0);
  	  canonicalize_obj_off (obj, off);
  	  return fold_indirect_ref_1 (ctx, loc, type, obj, tree_to_uhwi (off),
! 				      empty_base);
  	}
      }
    /* *(foo *)fooarrptr => (*fooarrptr)[0] */
--- 852,858 ----
  	  tree obj = TREE_OPERAND (op00, 0);
  	  canonicalize_obj_off (obj, off);
  	  return fold_indirect_ref_1 (ctx, loc, type, obj, tree_to_uhwi (off),
! 				      empty_base, jump_target);
  	}
      }
    /* *(foo *)fooarrptr => (*fooarrptr)[0] */
*************** rs_fold_indirect_ref (const constexpr_ct
*** 804,811 ****
      {
        tree type_domain;
        tree min_val = size_zero_node;
!       tree newsub
! 	= rs_fold_indirect_ref (ctx, loc, TREE_TYPE (subtype), sub, NULL);
        if (newsub)
  	sub = newsub;
        else
--- 861,868 ----
      {
        tree type_domain;
        tree min_val = size_zero_node;
!       tree newsub = rs_fold_indirect_ref (ctx, loc, TREE_TYPE (subtype), sub,
! 					  NULL, jump_target);
        if (newsub)
  	sub = newsub;
        else
*************** rs_fold_indirect_ref (const constexpr_ct
*** 824,830 ****
  
  static tree
  rs_eval_indirect_ref (const constexpr_ctx *ctx, tree t, bool lval,
! 		      bool *non_constant_p, bool *overflow_p)
  {
    tree orig_op0 = TREE_OPERAND (t, 0);
    bool empty_base = false;
--- 881,887 ----
  
  static tree
  rs_eval_indirect_ref (const constexpr_ctx *ctx, tree t, bool lval,
! 		      bool *non_constant_p, bool *overflow_p, tree *jump_target)
  {
    tree orig_op0 = TREE_OPERAND (t, 0);
    bool empty_base = false;
*************** rs_eval_indirect_ref (const constexpr_ct
*** 842,854 ****
  
    /* First try to simplify it directly.  */
    tree r = rs_fold_indirect_ref (ctx, EXPR_LOCATION (t), TREE_TYPE (t),
! 				 orig_op0, &empty_base);
    if (!r)
      {
        /* If that didn't work, evaluate the operand first.  */
!       tree op0
! 	= eval_constant_expression (ctx, orig_op0,
! 				    /*lval*/ false, non_constant_p, overflow_p);
        /* Don't VERIFY_CONSTANT here.  */
        if (*non_constant_p)
  	return t;
--- 899,911 ----
  
    /* First try to simplify it directly.  */
    tree r = rs_fold_indirect_ref (ctx, EXPR_LOCATION (t), TREE_TYPE (t),
! 				 orig_op0, &empty_base, jump_target);
    if (!r)
      {
        /* If that didn't work, evaluate the operand first.  */
!       tree op0 = eval_constant_expression (ctx, orig_op0,
! 					   /*lval*/ false, non_constant_p,
! 					   overflow_p, jump_target);
        /* Don't VERIFY_CONSTANT here.  */
        if (*non_constant_p)
  	return t;
*************** rs_eval_indirect_ref (const constexpr_ct
*** 862,868 ****
  	}
  
        r = rs_fold_indirect_ref (ctx, EXPR_LOCATION (t), TREE_TYPE (t), op0,
! 				&empty_base);
        if (r == NULL_TREE)
  	{
  	  /* We couldn't fold to a constant value.  Make sure it's not
--- 919,925 ----
  	}
  
        r = rs_fold_indirect_ref (ctx, EXPR_LOCATION (t), TREE_TYPE (t), op0,
! 				&empty_base, jump_target);
        if (r == NULL_TREE)
  	{
  	  /* We couldn't fold to a constant value.  Make sure it's not
*************** rs_eval_indirect_ref (const constexpr_ct
*** 891,897 ****
  	}
      }
  
!   r = eval_constant_expression (ctx, r, lval, non_constant_p, overflow_p);
    if (*non_constant_p)
      return t;
  
--- 948,955 ----
  	}
      }
  
!   r = eval_constant_expression (ctx, r, lval, non_constant_p, overflow_p,
! 				jump_target);
    if (*non_constant_p)
      return t;
  
*************** rs_eval_indirect_ref (const constexpr_ct
*** 917,933 ****
  static tree
  eval_logical_expression (const constexpr_ctx *ctx, tree t, tree bailout_value,
  			 tree continue_value, bool lval, bool *non_constant_p,
! 			 bool *overflow_p)
  {
    tree r;
    tree lhs = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 				       non_constant_p, overflow_p);
    VERIFY_CONSTANT (lhs);
    if (tree_int_cst_equal (lhs, bailout_value))
      return lhs;
    gcc_assert (tree_int_cst_equal (lhs, continue_value));
    r = eval_constant_expression (ctx, TREE_OPERAND (t, 1), lval, non_constant_p,
! 				overflow_p);
    VERIFY_CONSTANT (r);
    return r;
  }
--- 975,991 ----
  static tree
  eval_logical_expression (const constexpr_ctx *ctx, tree t, tree bailout_value,
  			 tree continue_value, bool lval, bool *non_constant_p,
! 			 bool *overflow_p, tree *jump_target)
  {
    tree r;
    tree lhs = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 				       non_constant_p, overflow_p, jump_target);
    VERIFY_CONSTANT (lhs);
    if (tree_int_cst_equal (lhs, bailout_value))
      return lhs;
    gcc_assert (tree_int_cst_equal (lhs, continue_value));
    r = eval_constant_expression (ctx, TREE_OPERAND (t, 1), lval, non_constant_p,
! 				overflow_p, jump_target);
    VERIFY_CONSTANT (r);
    return r;
  }
*************** get_or_insert_ctor_field (tree ctor, tre
*** 1243,1261 ****
  
  static tree
  eval_vector_conditional_expression (const constexpr_ctx *ctx, tree t,
! 				    bool *non_constant_p, bool *overflow_p)
  {
!   tree arg1
!     = eval_constant_expression (ctx, TREE_OPERAND (t, 0),
! 				/*lval*/ false, non_constant_p, overflow_p);
    VERIFY_CONSTANT (arg1);
!   tree arg2
!     = eval_constant_expression (ctx, TREE_OPERAND (t, 1),
! 				/*lval*/ false, non_constant_p, overflow_p);
    VERIFY_CONSTANT (arg2);
!   tree arg3
!     = eval_constant_expression (ctx, TREE_OPERAND (t, 2),
! 				/*lval*/ false, non_constant_p, overflow_p);
    VERIFY_CONSTANT (arg3);
    location_t loc = EXPR_LOCATION (t);
    tree type = TREE_TYPE (t);
--- 1301,1320 ----
  
  static tree
  eval_vector_conditional_expression (const constexpr_ctx *ctx, tree t,
! 				    bool *non_constant_p, bool *overflow_p,
! 				    tree *jump_target)
  {
!   tree arg1 = eval_constant_expression (ctx, TREE_OPERAND (t, 0),
! 					/*lval*/ false, non_constant_p,
! 					overflow_p, jump_target);
    VERIFY_CONSTANT (arg1);
!   tree arg2 = eval_constant_expression (ctx, TREE_OPERAND (t, 1),
! 					/*lval*/ false, non_constant_p,
! 					overflow_p, jump_target);
    VERIFY_CONSTANT (arg2);
!   tree arg3 = eval_constant_expression (ctx, TREE_OPERAND (t, 2),
! 					/*lval*/ false, non_constant_p,
! 					overflow_p, jump_target);
    VERIFY_CONSTANT (arg3);
    location_t loc = EXPR_LOCATION (t);
    tree type = TREE_TYPE (t);
*************** eval_vector_conditional_expression (cons
*** 1280,1286 ****
  
  static tree
  eval_bare_aggregate (const constexpr_ctx *ctx, tree t, bool lval,
! 		     bool *non_constant_p, bool *overflow_p)
  {
    vec<constructor_elt, va_gc> *v = CONSTRUCTOR_ELTS (t);
    bool changed = false;
--- 1339,1345 ----
  
  static tree
  eval_bare_aggregate (const constexpr_ctx *ctx, tree t, bool lval,
! 		     bool *non_constant_p, bool *overflow_p, tree *jump_target)
  {
    vec<constructor_elt, va_gc> *v = CONSTRUCTOR_ELTS (t);
    bool changed = false;
*************** eval_bare_aggregate (const constexpr_ctx
*** 1331,1338 ****
  	   the active union member now so that we can later detect and diagnose
  	   if its initializer attempts to activate another member.  */
  	get_or_insert_ctor_field (ctx->ctor, index);
!       tree elt = eval_constant_expression (&new_ctx, value, lval,
! 					   non_constant_p, overflow_p);
        /* Don't VERIFY_CONSTANT here.  */
        if (ctx->quiet && *non_constant_p)
  	break;
--- 1390,1398 ----
  	   the active union member now so that we can later detect and diagnose
  	   if its initializer attempts to activate another member.  */
  	get_or_insert_ctor_field (ctx->ctor, index);
!       tree elt
! 	= eval_constant_expression (&new_ctx, value, lval, non_constant_p,
! 				    overflow_p, jump_target);
        /* Don't VERIFY_CONSTANT here.  */
        if (ctx->quiet && *non_constant_p)
  	break;
*************** eval_bare_aggregate (const constexpr_ctx
*** 1401,1407 ****
  
  static tree
  cxx_eval_trinary_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 			     bool *non_constant_p, bool *overflow_p)
  {
    int i;
    tree args[3];
--- 1461,1468 ----
  
  static tree
  cxx_eval_trinary_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 			     bool *non_constant_p, bool *overflow_p,
! 			     tree *jump_target)
  {
    int i;
    tree args[3];
*************** cxx_eval_trinary_expression (const const
*** 1409,1416 ****
  
    for (i = 0; i < 3; i++)
      {
!       args[i] = eval_constant_expression (ctx, TREE_OPERAND (t, i), lval,
! 					  non_constant_p, overflow_p);
        VERIFY_CONSTANT (args[i]);
      }
  
--- 1470,1478 ----
  
    for (i = 0; i < 3; i++)
      {
!       args[i]
! 	= eval_constant_expression (ctx, TREE_OPERAND (t, i), lval,
! 				    non_constant_p, overflow_p, jump_target);
        VERIFY_CONSTANT (args[i]);
      }
  
*************** free_constructor (tree t)
*** 1555,1561 ****
  
  static tree eval_and_check_array_index (const constexpr_ctx *ctx, tree t,
  					bool allow_one_past,
! 					bool *non_constant_p, bool *overflow_p);
  
  // forked from gcc/cp/constexpr.cc cxx_eval_array_reference
  
--- 1617,1624 ----
  
  static tree eval_and_check_array_index (const constexpr_ctx *ctx, tree t,
  					bool allow_one_past,
! 					bool *non_constant_p, bool *overflow_p,
! 					tree *jump_target);
  
  // forked from gcc/cp/constexpr.cc cxx_eval_array_reference
  
*************** static tree eval_and_check_array_index (
*** 1564,1574 ****
  
  static tree
  eval_array_reference (const constexpr_ctx *ctx, tree t, bool lval,
! 		      bool *non_constant_p, bool *overflow_p)
  {
    tree oldary = TREE_OPERAND (t, 0);
!   tree ary
!     = eval_constant_expression (ctx, oldary, lval, non_constant_p, overflow_p);
    if (*non_constant_p)
      return t;
    if (!lval && TREE_CODE (ary) == VIEW_CONVERT_EXPR
--- 1627,1637 ----
  
  static tree
  eval_array_reference (const constexpr_ctx *ctx, tree t, bool lval,
! 		      bool *non_constant_p, bool *overflow_p, tree *jump_target)
  {
    tree oldary = TREE_OPERAND (t, 0);
!   tree ary = eval_constant_expression (ctx, oldary, lval, non_constant_p,
! 				       overflow_p, jump_target);
    if (*non_constant_p)
      return t;
    if (!lval && TREE_CODE (ary) == VIEW_CONVERT_EXPR
*************** eval_array_reference (const constexpr_ct
*** 1577,1584 ****
      ary = TREE_OPERAND (ary, 0);
  
    tree oldidx = TREE_OPERAND (t, 1);
!   tree index
!     = eval_and_check_array_index (ctx, t, lval, non_constant_p, overflow_p);
    if (*non_constant_p)
      return t;
  
--- 1640,1647 ----
      ary = TREE_OPERAND (ary, 0);
  
    tree oldidx = TREE_OPERAND (t, 1);
!   tree index = eval_and_check_array_index (ctx, t, lval, non_constant_p,
! 					   overflow_p, jump_target);
    if (*non_constant_p)
      return t;
  
*************** eval_array_reference (const constexpr_ct
*** 1680,1686 ****
        new_ctx.ctor = build_constructor (elem_type, NULL);
        ctx = &new_ctx;
      }
!   t = eval_constant_expression (ctx, val, lval, non_constant_p, overflow_p);
    if (!SCALAR_TYPE_P (elem_type) && t != ctx->ctor)
      free_constructor (ctx->ctor);
    return t;
--- 1743,1750 ----
        new_ctx.ctor = build_constructor (elem_type, NULL);
        ctx = &new_ctx;
      }
!   t = eval_constant_expression (ctx, val, lval, non_constant_p, overflow_p,
! 				jump_target);
    if (!SCALAR_TYPE_P (elem_type) && t != ctx->ctor)
      free_constructor (ctx->ctor);
    return t;
*************** eval_array_reference (const constexpr_ct
*** 1693,1699 ****
  
  static tree
  eval_component_reference (const constexpr_ctx *ctx, tree t, bool lval,
! 			  bool *non_constant_p, bool *overflow_p)
  {
    unsigned HOST_WIDE_INT i;
    tree field;
--- 1757,1764 ----
  
  static tree
  eval_component_reference (const constexpr_ctx *ctx, tree t, bool lval,
! 			  bool *non_constant_p, bool *overflow_p,
! 			  tree *jump_target)
  {
    unsigned HOST_WIDE_INT i;
    tree field;
*************** eval_component_reference (const constexp
*** 1701,1707 ****
    tree part = TREE_OPERAND (t, 1);
    tree orig_whole = TREE_OPERAND (t, 0);
    tree whole = eval_constant_expression (ctx, orig_whole, lval, non_constant_p,
! 					 overflow_p);
    if (INDIRECT_REF_P (whole) && integer_zerop (TREE_OPERAND (whole, 0)))
      {
        if (!ctx->quiet)
--- 1766,1772 ----
    tree part = TREE_OPERAND (t, 1);
    tree orig_whole = TREE_OPERAND (t, 0);
    tree whole = eval_constant_expression (ctx, orig_whole, lval, non_constant_p,
! 					 overflow_p, jump_target);
    if (INDIRECT_REF_P (whole) && integer_zerop (TREE_OPERAND (whole, 0)))
      {
        if (!ctx->quiet)
*************** eval_component_reference (const constexp
*** 1790,1797 ****
    // back to handle this to assign suitable value to value before sending it in
    // eval_constant_expression below
    // value = build_value_init (TREE_TYPE (t), tf_warning_or_error);
!   return eval_constant_expression (ctx, value, lval, non_constant_p,
! 				   overflow_p);
  }
  
  /* Subroutine of cxx_eval_statement_list.  Determine whether the statement
--- 1855,1862 ----
    // back to handle this to assign suitable value to value before sending it in
    // eval_constant_expression below
    // value = build_value_init (TREE_TYPE (t), tf_warning_or_error);
!   return eval_constant_expression (ctx, value, lval, non_constant_p, overflow_p,
! 				   jump_target);
  }
  
  /* Subroutine of cxx_eval_statement_list.  Determine whether the statement
*************** label_matches (const constexpr_ctx *ctx,
*** 1850,1856 ****
  static tree
  eval_constant_expression (const constexpr_ctx *ctx, tree t, bool lval,
  			  bool *non_constant_p, bool *overflow_p,
! 			  tree *jump_target /* = NULL */)
  {
    if (jump_target && *jump_target)
      {
--- 1915,1921 ----
  static tree
  eval_constant_expression (const constexpr_ctx *ctx, tree t, bool lval,
  			  bool *non_constant_p, bool *overflow_p,
! 			  tree *jump_target)
  {
    if (jump_target && *jump_target)
      {
*************** eval_constant_expression (const constexp
*** 1921,1954 ****
  	{
  	  r = DECL_VALUE_EXPR (t);
  	  return eval_constant_expression (ctx, r, lval, non_constant_p,
! 					   overflow_p);
  	}
      /* fall through */
      case CONST_DECL:
!       {
! 	/* We used to not check lval for CONST_DECL, but darwin.cc uses
! 	   CONST_DECL for aggregate constants.  */
! 	if (lval)
! 	  return t;
! 	else if (t == ctx->object)
! 	  return ctx->ctor;
! 	if (VAR_P (t))
! 	  if (tree *p = ctx->global->values.get (t))
! 	    if (*p != NULL_TREE)
! 	      {
! 		r = *p;
! 		break;
! 	      }
  	r = decl_constant_value (t, /*unshare_p=*/false);
! 	if (TREE_CODE (r) == TARGET_EXPR
! 	    && TREE_CODE (TARGET_EXPR_INITIAL (r)) == CONSTRUCTOR)
! 	  r = TARGET_EXPR_INITIAL (r);
! 	if (DECL_P (r))
! 	  {
  	    non_const_var_error (loc, r);
! 	    return r;
! 	  }
!       }
        break;
  
      case PARM_DECL:
--- 1986,2029 ----
  	{
  	  r = DECL_VALUE_EXPR (t);
  	  return eval_constant_expression (ctx, r, lval, non_constant_p,
! 					   overflow_p, jump_target);
  	}
      /* fall through */
      case CONST_DECL:
!       /* We used to not check lval for CONST_DECL, but darwin.cc uses
! 	 CONST_DECL for aggregate constants.  */
!       if (lval)
! 	return t;
!       else if (t == ctx->object)
! 	return ctx->ctor;
!       if (VAR_P (t))
! 	{
! 	  if (tree v = ctx->global->get_value (t))
! 	    {
! 	      r = v;
! 	      break;
! 	    }
! 	}
!       if (COMPLETE_TYPE_P (TREE_TYPE (t))
! 	  && is_really_empty_class (TREE_TYPE (t), /*ignore_vptr*/ false))
! 	{
! 	  /* If the class is empty, we aren't actually loading anything.  */
! 	  r = build_constructor (TREE_TYPE (t), NULL);
! 	  TREE_CONSTANT (r) = true;
! 	}
!       else if (ctx->strict)
! 	r = decl_really_constant_value (t, /*unshare_p=*/false);
!       else
  	r = decl_constant_value (t, /*unshare_p=*/false);
!       if (TREE_CODE (r) == TARGET_EXPR
! 	  && TREE_CODE (TARGET_EXPR_INITIAL (r)) == CONSTRUCTOR)
! 	r = TARGET_EXPR_INITIAL (r);
!       if (DECL_P (r) && !(VAR_P (t) && TYPE_REF_P (TREE_TYPE (t))))
! 	{
! 	  if (!ctx->quiet)
  	    non_const_var_error (loc, r);
! 	  *non_constant_p = true;
! 	}
        break;
  
      case PARM_DECL:
*************** eval_constant_expression (const constexp
*** 2014,2020 ****
      case LTGT_EXPR:
      case RANGE_EXPR:
      case COMPLEX_EXPR:
!       r = eval_binary_expression (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
        /* fold can introduce non-IF versions of these; still treat them as
--- 2089,2096 ----
      case LTGT_EXPR:
      case RANGE_EXPR:
      case COMPLEX_EXPR:
!       r = eval_binary_expression (ctx, t, lval, non_constant_p, overflow_p,
! 				  jump_target);
        break;
  
        /* fold can introduce non-IF versions of these; still treat them as
*************** eval_constant_expression (const constexp
*** 2023,2036 ****
      case TRUTH_ANDIF_EXPR:
        r = eval_logical_expression (ctx, t, boolean_false_node,
  				   boolean_true_node, lval, non_constant_p,
! 				   overflow_p);
        break;
  
      case TRUTH_OR_EXPR:
      case TRUTH_ORIF_EXPR:
        r = eval_logical_expression (ctx, t, boolean_true_node,
  				   boolean_false_node, lval, non_constant_p,
! 				   overflow_p);
        break;
  
      case TARGET_EXPR:
--- 2099,2112 ----
      case TRUTH_ANDIF_EXPR:
        r = eval_logical_expression (ctx, t, boolean_false_node,
  				   boolean_true_node, lval, non_constant_p,
! 				   overflow_p, jump_target);
        break;
  
      case TRUTH_OR_EXPR:
      case TRUTH_ORIF_EXPR:
        r = eval_logical_expression (ctx, t, boolean_true_node,
  				   boolean_false_node, lval, non_constant_p,
! 				   overflow_p, jump_target);
        break;
  
      case TARGET_EXPR:
*************** eval_constant_expression (const constexp
*** 2079,2085 ****
  	/* Pass false for 'lval' because this indicates
  	   initialization of a temporary.  */
  	r = eval_constant_expression (ctx, TREE_OPERAND (t, 1), false,
! 				      non_constant_p, overflow_p);
  	if (*non_constant_p)
  	  break;
  	/* Adjust the type of the result to the type of the temporary.  */
--- 2155,2161 ----
  	/* Pass false for 'lval' because this indicates
  	   initialization of a temporary.  */
  	r = eval_constant_expression (ctx, TREE_OPERAND (t, 1), false,
! 				      non_constant_p, overflow_p, jump_target);
  	if (*non_constant_p)
  	  break;
  	/* Adjust the type of the result to the type of the temporary.  */
*************** eval_constant_expression (const constexp
*** 2096,2108 ****
        break;
  
      case CALL_EXPR:
!       r = eval_call_expression (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
      case RETURN_EXPR:
        if (TREE_OPERAND (t, 0) != NULL_TREE)
  	r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 				      non_constant_p, overflow_p);
        /* FALLTHRU */
      case BREAK_STMT:
      case CONTINUE_STMT:
--- 2172,2185 ----
        break;
  
      case CALL_EXPR:
!       r = eval_call_expression (ctx, t, lval, non_constant_p, overflow_p,
! 				jump_target);
        break;
  
      case RETURN_EXPR:
        if (TREE_OPERAND (t, 0) != NULL_TREE)
  	r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 				      non_constant_p, overflow_p, jump_target);
        /* FALLTHRU */
      case BREAK_STMT:
      case CONTINUE_STMT:
*************** eval_constant_expression (const constexp
*** 2135,2141 ****
  	if (tree init = DECL_INITIAL (r))
  	  {
  	    init = eval_constant_expression (ctx, init, false, non_constant_p,
! 					     overflow_p);
  	    /* Don't share a CONSTRUCTOR that might be changed.  */
  	    init = unshare_constructor (init);
  	    /* Remember that a constant object's constructor has already
--- 2212,2218 ----
  	if (tree init = DECL_INITIAL (r))
  	  {
  	    init = eval_constant_expression (ctx, init, false, non_constant_p,
! 					     overflow_p, jump_target);
  	    /* Don't share a CONSTRUCTOR that might be changed.  */
  	    init = unshare_constructor (init);
  	    /* Remember that a constant object's constructor has already
*************** eval_constant_expression (const constexp
*** 2156,2167 ****
  	 constant without its operand being, and vice versa.  */
      case MEM_REF:
      case INDIRECT_REF:
!       r = rs_eval_indirect_ref (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
      case VEC_PERM_EXPR:
!       r = cxx_eval_trinary_expression (ctx, t, lval, non_constant_p,
! 				       overflow_p);
        break;
  
      case PAREN_EXPR:
--- 2233,2245 ----
  	 constant without its operand being, and vice versa.  */
      case MEM_REF:
      case INDIRECT_REF:
!       r = rs_eval_indirect_ref (ctx, t, lval, non_constant_p, overflow_p,
! 				jump_target);
        break;
  
      case VEC_PERM_EXPR:
!       r = cxx_eval_trinary_expression (ctx, t, lval, non_constant_p, overflow_p,
! 				       jump_target);
        break;
  
      case PAREN_EXPR:
*************** eval_constant_expression (const constexp
*** 2169,2179 ****
        /* A PAREN_EXPR resulting from __builtin_assoc_barrier has no effect in
  	 constant expressions since it's unaffected by -fassociative-math.  */
        r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 				    non_constant_p, overflow_p);
        break;
  
      case MODIFY_EXPR:
!       r = eval_store_expression (ctx, t, false, non_constant_p, overflow_p);
        break;
  
      case STATEMENT_LIST:
--- 2247,2258 ----
        /* A PAREN_EXPR resulting from __builtin_assoc_barrier has no effect in
  	 constant expressions since it's unaffected by -fassociative-math.  */
        r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 				    non_constant_p, overflow_p, jump_target);
        break;
  
      case MODIFY_EXPR:
!       r = eval_store_expression (ctx, t, false, non_constant_p, overflow_p,
! 				 jump_target);
        break;
  
      case STATEMENT_LIST:
*************** eval_constant_expression (const constexp
*** 2189,2201 ****
      case OBJ_TYPE_REF:
        /* Virtual function lookup.  We don't need to do anything fancy.  */
        return eval_constant_expression (ctx, OBJ_TYPE_REF_EXPR (t), lval,
! 				       non_constant_p, overflow_p);
  
      case EXIT_EXPR:
        {
  	tree cond = TREE_OPERAND (t, 0);
! 	cond = eval_constant_expression (ctx, cond, /*lval*/ false,
! 					 non_constant_p, overflow_p);
  	VERIFY_CONSTANT (cond);
  	if (integer_nonzerop (cond))
  	  *jump_target = t;
--- 2268,2281 ----
      case OBJ_TYPE_REF:
        /* Virtual function lookup.  We don't need to do anything fancy.  */
        return eval_constant_expression (ctx, OBJ_TYPE_REF_EXPR (t), lval,
! 				       non_constant_p, overflow_p, jump_target);
  
      case EXIT_EXPR:
        {
  	tree cond = TREE_OPERAND (t, 0);
! 	cond
! 	  = eval_constant_expression (ctx, cond, /*lval*/ false, non_constant_p,
! 				      overflow_p, jump_target);
  	VERIFY_CONSTANT (cond);
  	if (integer_nonzerop (cond))
  	  *jump_target = t;
*************** eval_constant_expression (const constexp
*** 2225,2231 ****
        else
  	{
  	  r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), false,
! 					non_constant_p, overflow_p);
  	  if (*non_constant_p)
  	    break;
  	  ctx->global->values.put (t, r);
--- 2305,2312 ----
        else
  	{
  	  r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), false,
! 					non_constant_p, overflow_p,
! 					jump_target);
  	  if (*non_constant_p)
  	    break;
  	  ctx->global->values.put (t, r);
*************** eval_constant_expression (const constexp
*** 2239,2245 ****
  	tree oldop = TREE_OPERAND (t, 0);
  	tree op = eval_constant_expression (ctx, oldop,
  					    /*lval*/ true, non_constant_p,
! 					    overflow_p);
  	/* Don't VERIFY_CONSTANT here.  */
  	if (*non_constant_p)
  	  return t;
--- 2320,2326 ----
  	tree oldop = TREE_OPERAND (t, 0);
  	tree op = eval_constant_expression (ctx, oldop,
  					    /*lval*/ true, non_constant_p,
! 					    overflow_p, jump_target);
  	/* Don't VERIFY_CONSTANT here.  */
  	if (*non_constant_p)
  	  return t;
*************** eval_constant_expression (const constexp
*** 2284,2290 ****
        if (lval)
  	{
  	  r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 					non_constant_p, overflow_p);
  	  if (r == error_mark_node)
  	    ;
  	  else if (r == TREE_OPERAND (t, 0))
--- 2365,2372 ----
        if (lval)
  	{
  	  r = eval_constant_expression (ctx, TREE_OPERAND (t, 0), lval,
! 					non_constant_p, overflow_p,
! 					jump_target);
  	  if (r == error_mark_node)
  	    ;
  	  else if (r == TREE_OPERAND (t, 0))
*************** eval_constant_expression (const constexp
*** 2303,2309 ****
      case BIT_NOT_EXPR:
      case TRUTH_NOT_EXPR:
      case FIXED_CONVERT_EXPR:
!       r = eval_unary_expression (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
      case LOOP_EXPR:
--- 2385,2392 ----
      case BIT_NOT_EXPR:
      case TRUTH_NOT_EXPR:
      case FIXED_CONVERT_EXPR:
!       r = eval_unary_expression (ctx, t, lval, non_constant_p, overflow_p,
! 				 jump_target);
        break;
  
      case LOOP_EXPR:
*************** eval_constant_expression (const constexp
*** 2318,2324 ****
        break;
  
      case ARRAY_REF:
!       r = eval_array_reference (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
      case COMPONENT_REF:
--- 2401,2408 ----
        break;
  
      case ARRAY_REF:
!       r = eval_array_reference (ctx, t, lval, non_constant_p, overflow_p,
! 				jump_target);
        break;
  
      case COMPONENT_REF:
*************** eval_constant_expression (const constexp
*** 2332,2342 ****
  	  *non_constant_p = true;
  	  return t;
  	}
!       r = eval_component_reference (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
      case BIT_FIELD_REF:
!       r = eval_bit_field_ref (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
      case COND_EXPR:
--- 2416,2428 ----
  	  *non_constant_p = true;
  	  return t;
  	}
!       r = eval_component_reference (ctx, t, lval, non_constant_p, overflow_p,
! 				    jump_target);
        break;
  
      case BIT_FIELD_REF:
!       r = eval_bit_field_ref (ctx, t, lval, non_constant_p, overflow_p,
! 			      jump_target);
        break;
  
      case COND_EXPR:
*************** eval_constant_expression (const constexp
*** 2381,2387 ****
  
      case VEC_COND_EXPR:
        r = eval_vector_conditional_expression (ctx, t, non_constant_p,
! 					      overflow_p);
        break;
  
      case TRY_CATCH_EXPR:
--- 2467,2473 ----
  
      case VEC_COND_EXPR:
        r = eval_vector_conditional_expression (ctx, t, non_constant_p,
! 					      overflow_p, jump_target);
        break;
  
      case TRY_CATCH_EXPR:
*************** eval_constant_expression (const constexp
*** 2407,2413 ****
  	/* Evaluate the cleanups.  */
  	FOR_EACH_VEC_ELT_REVERSE (cleanups, i, cleanup)
  	  eval_constant_expression (ctx, cleanup, false, non_constant_p,
! 				    overflow_p);
        }
        break;
  
--- 2493,2499 ----
  	/* Evaluate the cleanups.  */
  	FOR_EACH_VEC_ELT_REVERSE (cleanups, i, cleanup)
  	  eval_constant_expression (ctx, cleanup, false, non_constant_p,
! 				    overflow_p, jump_target);
        }
        break;
  
*************** eval_constant_expression (const constexp
*** 2417,2423 ****
        if (!*non_constant_p)
  	/* Also evaluate the cleanup.  */
  	eval_constant_expression (ctx, TREE_OPERAND (t, 1), true,
! 				  non_constant_p, overflow_p);
        break;
  
      case CONSTRUCTOR:
--- 2503,2509 ----
        if (!*non_constant_p)
  	/* Also evaluate the cleanup.  */
  	eval_constant_expression (ctx, TREE_OPERAND (t, 1), true,
! 				  non_constant_p, overflow_p, jump_target);
        break;
  
      case CONSTRUCTOR:
*************** eval_constant_expression (const constexp
*** 2429,2435 ****
  	  if (TREE_CONSTANT (t))
  	    return fold (t);
  	}
!       r = eval_bare_aggregate (ctx, t, lval, non_constant_p, overflow_p);
        break;
  
        /* FALLTHROUGH.  */
--- 2515,2522 ----
  	  if (TREE_CONSTANT (t))
  	    return fold (t);
  	}
!       r = eval_bare_aggregate (ctx, t, lval, non_constant_p, overflow_p,
! 			       jump_target);
        break;
  
        /* FALLTHROUGH.  */
*************** eval_constant_expression (const constexp
*** 2440,2446 ****
  	tree oldop = TREE_OPERAND (t, 0);
  
  	tree op = eval_constant_expression (ctx, oldop, lval, non_constant_p,
! 					    overflow_p);
  	if (*non_constant_p)
  	  return t;
  	tree type = TREE_TYPE (t);
--- 2527,2533 ----
  	tree oldop = TREE_OPERAND (t, 0);
  
  	tree op = eval_constant_expression (ctx, oldop, lval, non_constant_p,
! 					    overflow_p, jump_target);
  	if (*non_constant_p)
  	  return t;
  	tree type = TREE_TYPE (t);
*************** eval_constant_expression (const constexp
*** 2571,2577 ****
  	    return ctor;
  	  else
  	    return eval_constant_expression (ctx, ctor, lval, non_constant_p,
! 					     overflow_p);
  	}
        /* A placeholder without a referent.  We can get here when
  	 checking whether NSDMIs are noexcept, or in massage_init_elt;
--- 2658,2664 ----
  	    return ctor;
  	  else
  	    return eval_constant_expression (ctx, ctor, lval, non_constant_p,
! 					     overflow_p, jump_target);
  	}
        /* A placeholder without a referent.  We can get here when
  	 checking whether NSDMIs are noexcept, or in massage_init_elt;
*************** is_empty_field (tree decl)
*** 2632,2638 ****
  
  static tree
  eval_store_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 		       bool *non_constant_p, bool *overflow_p)
  {
    constexpr_ctx new_ctx = *ctx;
  
--- 2719,2726 ----
  
  static tree
  eval_store_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 		       bool *non_constant_p, bool *overflow_p,
! 		       tree *jump_target)
  {
    constexpr_ctx new_ctx = *ctx;
  
*************** eval_store_expression (const constexpr_c
*** 2653,2659 ****
        if (!SCALAR_TYPE_P (type))
  	new_ctx.ctor = new_ctx.object = NULL_TREE;
        init = eval_constant_expression (&new_ctx, init, false, non_constant_p,
! 				       overflow_p);
        if (*non_constant_p)
  	return t;
      }
--- 2741,2747 ----
        if (!SCALAR_TYPE_P (type))
  	new_ctx.ctor = new_ctx.object = NULL_TREE;
        init = eval_constant_expression (&new_ctx, init, false, non_constant_p,
! 				       overflow_p, jump_target);
        if (*non_constant_p)
  	return t;
      }
*************** eval_store_expression (const constexpr_c
*** 2665,2671 ****
  	 as a whole; otherwise, only evaluate the innermost piece to avoid
  	 building up unnecessary *_REFs.  */
        target = eval_constant_expression (ctx, target, true, non_constant_p,
! 					 overflow_p);
        evaluated = true;
        if (*non_constant_p)
  	return t;
--- 2753,2759 ----
  	 as a whole; otherwise, only evaluate the innermost piece to avoid
  	 building up unnecessary *_REFs.  */
        target = eval_constant_expression (ctx, target, true, non_constant_p,
! 					 overflow_p, jump_target);
        evaluated = true;
        if (*non_constant_p)
  	return t;
*************** eval_store_expression (const constexpr_c
*** 2694,2700 ****
  	    if (TREE_CODE (probe) == ARRAY_REF)
  	      {
  		elt = eval_and_check_array_index (ctx, probe, false,
! 						  non_constant_p, overflow_p);
  		if (*non_constant_p)
  		  return t;
  	      }
--- 2782,2789 ----
  	    if (TREE_CODE (probe) == ARRAY_REF)
  	      {
  		elt = eval_and_check_array_index (ctx, probe, false,
! 						  non_constant_p, overflow_p,
! 						  jump_target);
  		if (*non_constant_p)
  		  return t;
  	      }
*************** eval_store_expression (const constexpr_c
*** 2718,2725 ****
  	    object = probe;
  	  else
  	    {
! 	      probe = eval_constant_expression (ctx, probe, true,
! 						non_constant_p, overflow_p);
  	      evaluated = true;
  	      if (*non_constant_p)
  		return t;
--- 2807,2815 ----
  	    object = probe;
  	  else
  	    {
! 	      probe
! 		= eval_constant_expression (ctx, probe, true, non_constant_p,
! 					    overflow_p, jump_target);
  	      evaluated = true;
  	      if (*non_constant_p)
  		return t;
*************** eval_store_expression (const constexpr_c
*** 2910,2916 ****
  	if (tree tinit = TARGET_EXPR_INITIAL (init))
  	  init = tinit;
        init = eval_constant_expression (&new_ctx, init, false, non_constant_p,
! 				       overflow_p);
        /* The hash table might have moved since the get earlier, and the
  	 initializer might have mutated the underlying CONSTRUCTORs, so we must
  	 recompute VALP. */
--- 3000,3006 ----
  	if (tree tinit = TARGET_EXPR_INITIAL (init))
  	  init = tinit;
        init = eval_constant_expression (&new_ctx, init, false, non_constant_p,
! 				       overflow_p, jump_target);
        /* The hash table might have moved since the get earlier, and the
  	 initializer might have mutated the underlying CONSTRUCTORs, so we must
  	 recompute VALP. */
*************** eval_store_expression (const constexpr_c
*** 3012,3033 ****
   Like cxx_eval_unary_expression, except for binary expressions.  */
  static tree
  eval_binary_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 			bool *non_constant_p, bool *overflow_p)
  {
    tree orig_lhs = TREE_OPERAND (t, 0);
    tree orig_rhs = TREE_OPERAND (t, 1);
    tree lhs, rhs;
- 
    lhs = eval_constant_expression (ctx, orig_lhs, lval, non_constant_p,
! 				  overflow_p);
    rhs = eval_constant_expression (ctx, orig_rhs, lval, non_constant_p,
! 				  overflow_p);
  
    location_t loc = EXPR_LOCATION (t);
    enum tree_code code = TREE_CODE (t);
    tree type = TREE_TYPE (t);
  
!   return fold_binary_loc (loc, code, type, lhs, rhs);
  }
  
  /* Helper function of cxx_bind_parameters_in_call.  Return non-NULL
--- 3102,3216 ----
   Like cxx_eval_unary_expression, except for binary expressions.  */
  static tree
  eval_binary_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 			bool *non_constant_p, bool *overflow_p,
! 			tree *jump_target)
  {
+   tree r = NULL_TREE;
    tree orig_lhs = TREE_OPERAND (t, 0);
    tree orig_rhs = TREE_OPERAND (t, 1);
    tree lhs, rhs;
    lhs = eval_constant_expression (ctx, orig_lhs, lval, non_constant_p,
! 				  overflow_p, jump_target);
!   /* Don't VERIFY_CONSTANT here, it's unnecessary and will break pointer
!      subtraction.  */
!   if (*non_constant_p)
!     return t;
!   if (*jump_target)
!     return NULL_TREE;
! 
    rhs = eval_constant_expression (ctx, orig_rhs, lval, non_constant_p,
! 				  overflow_p, jump_target);
!   if (*non_constant_p)
!     return t;
!   if (*jump_target)
!     return NULL_TREE;
  
    location_t loc = EXPR_LOCATION (t);
    enum tree_code code = TREE_CODE (t);
    tree type = TREE_TYPE (t);
  
!   if (code == EQ_EXPR || code == NE_EXPR)
!     {
!       bool is_code_eq = (code == EQ_EXPR);
! 
!       if (TREE_CODE (lhs) == PTRMEM_CST && TREE_CODE (rhs) == PTRMEM_CST)
! 	{
! 	  tree lmem = PTRMEM_CST_MEMBER (lhs);
! 	  tree rmem = PTRMEM_CST_MEMBER (rhs);
! 	  bool eq;
! 	  if (TREE_CODE (lmem) == TREE_CODE (rmem)
! 	      && TREE_CODE (lmem) == FIELD_DECL
! 	      && TREE_CODE (DECL_CONTEXT (lmem)) == UNION_TYPE
! 	      && same_type_p (DECL_CONTEXT (lmem), DECL_CONTEXT (rmem)))
! 	    /* If both refer to (possibly different) members of the same union
! 	       (12.3), they compare equal. */
! 	    eq = true;
! 	  // else
! 	  //   eq = cp_tree_equal (lhs, rhs);
! 	  r = constant_boolean_node (eq == is_code_eq, type);
! 	}
!       else if ((TREE_CODE (lhs) == PTRMEM_CST || TREE_CODE (rhs) == PTRMEM_CST)
! 	       && (null_member_pointer_value_p (lhs)
! 		   || null_member_pointer_value_p (rhs)))
! 	r = constant_boolean_node (!is_code_eq, type);
!     }
!   if (r == NULL_TREE && TREE_CODE_CLASS (code) == tcc_comparison
!       && POINTER_TYPE_P (TREE_TYPE (lhs)))
!     {
!       if (tree lhso = maybe_fold_addr_pointer_plus (lhs))
! 	lhs = fold_convert (TREE_TYPE (lhs), lhso);
!       if (tree rhso = maybe_fold_addr_pointer_plus (rhs))
! 	rhs = fold_convert (TREE_TYPE (rhs), rhso);
!     }
!   if (code == POINTER_PLUS_EXPR && !*non_constant_p && integer_zerop (lhs)
!       && !integer_zerop (rhs))
!     {
!       if (!ctx->quiet)
! 	error ("arithmetic involving a null pointer in %qE", lhs);
!       *non_constant_p = true;
!       return t;
!     }
!   else if (code == POINTER_PLUS_EXPR)
!     {
!       r = fold_pointer_plus_expression (ctx, t, lhs, rhs, non_constant_p,
! 					overflow_p, jump_target);
!       if (*jump_target)
! 	return NULL_TREE;
!     }
! 
!   if (r == NULL_TREE)
!     {
!       r = fold_binary_loc (loc, code, type, lhs, rhs);
!     }
! 
!   if (r == NULL_TREE && (code == LSHIFT_EXPR || code == RSHIFT_EXPR)
!       && TREE_CODE (lhs) == INTEGER_CST && TREE_CODE (rhs) == INTEGER_CST
!       && wi::neg_p (wi::to_wide (rhs)))
!     {
!       /* For diagnostics and -fpermissive emulate previous behavior of
! 	 handling shifts by negative amount.  */
!       tree nrhs = const_unop (NEGATE_EXPR, TREE_TYPE (rhs), rhs);
!       if (nrhs)
! 	r = fold_binary_loc (loc,
! 			     code == LSHIFT_EXPR ? RSHIFT_EXPR : LSHIFT_EXPR,
! 			     type, lhs, nrhs);
!     }
! 
!   if (r == NULL_TREE)
!     {
!       if (lhs == orig_lhs && rhs == orig_rhs)
! 	r = t;
!       else
! 	r = build2_loc (loc, code, type, lhs, rhs);
!     }
!   else if (eval_check_shift_p (loc, ctx, code, type, lhs, rhs))
!     *non_constant_p = true;
!   /* Don't VERIFY_CONSTANT if this might be dealing with a pointer to
!      a local array in a constexpr function.  */
!   bool ptr = INDIRECT_TYPE_P (TREE_TYPE (lhs));
!   if (!ptr)
!     VERIFY_CONSTANT (r);
!   return r;
  }
  
  /* Helper function of cxx_bind_parameters_in_call.  Return non-NULL
*************** addr_of_non_const_var (tree *tp, int *wa
*** 3065,3071 ****
  static tree
  rs_bind_parameters_in_call (const constexpr_ctx *ctx, tree t, tree fun,
  			    bool *non_constant_p, bool *overflow_p,
! 			    bool *non_constant_args)
  {
    const int nargs = call_expr_nargs (t);
    tree parms = DECL_ARGUMENTS (fun);
--- 3248,3254 ----
  static tree
  rs_bind_parameters_in_call (const constexpr_ctx *ctx, tree t, tree fun,
  			    bool *non_constant_p, bool *overflow_p,
! 			    bool *non_constant_args, tree *jump_target)
  {
    const int nargs = call_expr_nargs (t);
    tree parms = DECL_ARGUMENTS (fun);
*************** rs_bind_parameters_in_call (const conste
*** 3089,3095 ****
  	 such as this, but here we do the elision differently: we keep the
  	 TARGET_EXPR, and use its CONSTRUCTOR as the value of the parm.  */
        arg = eval_constant_expression (ctx, x, /*lval=*/false, non_constant_p,
! 				      overflow_p);
        /* Don't VERIFY_CONSTANT here.  */
        if (*non_constant_p && ctx->quiet)
  	break;
--- 3272,3278 ----
  	 such as this, but here we do the elision differently: we keep the
  	 TARGET_EXPR, and use its CONSTRUCTOR as the value of the parm.  */
        arg = eval_constant_expression (ctx, x, /*lval=*/false, non_constant_p,
! 				      overflow_p, jump_target);
        /* Don't VERIFY_CONSTANT here.  */
        if (*non_constant_p && ctx->quiet)
  	break;
*************** rs_bind_parameters_in_call (const conste
*** 3155,3161 ****
  
  static tree
  eval_builtin_function_call (const constexpr_ctx *ctx, tree t, tree fun,
! 			    bool lval, bool *non_constant_p, bool *overflow_p)
  {
    const int nargs = call_expr_nargs (t);
    tree *args = (tree *) alloca (nargs * sizeof (tree));
--- 3338,3345 ----
  
  static tree
  eval_builtin_function_call (const constexpr_ctx *ctx, tree t, tree fun,
! 			    bool lval, bool *non_constant_p, bool *overflow_p,
! 			    tree *jump_target)
  {
    const int nargs = call_expr_nargs (t);
    tree *args = (tree *) alloca (nargs * sizeof (tree));
*************** eval_builtin_function_call (const conste
*** 3258,3265 ****
  	  || potential_constant_expression (arg))
  	{
  	  bool dummy1 = false, dummy2 = false;
! 	  arg
! 	    = eval_constant_expression (&new_ctx, arg, false, &dummy1, &dummy2);
  	}
  
        if (bi_const_p)
--- 3442,3450 ----
  	  || potential_constant_expression (arg))
  	{
  	  bool dummy1 = false, dummy2 = false;
! 	  tree dummy_jump_target = NULL_TREE;
! 	  arg = eval_constant_expression (&new_ctx, arg, false, &dummy1,
! 					  &dummy2, &dummy_jump_target);
  	}
  
        if (bi_const_p)
*************** eval_builtin_function_call (const conste
*** 3355,3361 ****
      }
  
    return eval_constant_expression (&new_ctx, new_call, lval, non_constant_p,
! 				   overflow_p);
  }
  
  // Subroutine of cxx_eval_constant_expression.
--- 3540,3546 ----
      }
  
    return eval_constant_expression (&new_ctx, new_call, lval, non_constant_p,
! 				   overflow_p, jump_target);
  }
  
  // Subroutine of cxx_eval_constant_expression.
*************** eval_builtin_function_call (const conste
*** 3363,3369 ****
  // evaluation.
  static tree
  eval_call_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 		      bool *non_constant_p, bool *overflow_p)
  {
    location_t loc = EXPR_LOCATION (t);
    tree fun = get_function_named_in_call (t);
--- 3548,3554 ----
  // evaluation.
  static tree
  eval_call_expression (const constexpr_ctx *ctx, tree t, bool lval,
! 		      bool *non_constant_p, bool *overflow_p, tree *jump_target)
  {
    location_t loc = EXPR_LOCATION (t);
    tree fun = get_function_named_in_call (t);
*************** eval_call_expression (const constexpr_ct
*** 3392,3403 ****
  
    if (fndecl_built_in_p (fun))
      return eval_builtin_function_call (ctx, t, fun, lval, non_constant_p,
! 				       overflow_p);
  
    bool non_constant_args = false;
    new_call.bindings
      = rs_bind_parameters_in_call (ctx, t, fun, non_constant_p, overflow_p,
! 				  &non_constant_args);
  
    /* We build up the bindings list before we know whether we already have this
     call cached.  If we don't end up saving these bindings, ggc_free them when
--- 3577,3588 ----
  
    if (fndecl_built_in_p (fun))
      return eval_builtin_function_call (ctx, t, fun, lval, non_constant_p,
! 				       overflow_p, jump_target);
  
    bool non_constant_args = false;
    new_call.bindings
      = rs_bind_parameters_in_call (ctx, t, fun, non_constant_p, overflow_p,
! 				  &non_constant_args, jump_target);
  
    /* We build up the bindings list before we know whether we already have this
     call cached.  If we don't end up saving these bindings, ggc_free them when
*************** constexpr_fn_retval (const constexpr_ctx
*** 3960,3966 ****
  	bool non_constant_p = false;
  	bool overflow_p = false;
  	return eval_constant_expression (ctx, body, false, &non_constant_p,
! 					 &overflow_p);
        }
      case DECL_EXPR:
        {
--- 4145,4151 ----
  	bool non_constant_p = false;
  	bool overflow_p = false;
  	return eval_constant_expression (ctx, body, false, &non_constant_p,
! 					 &overflow_p, NULL);
        }
      case DECL_EXPR:
        {
*************** constant_value_1 (tree decl, bool, bool,
*** 4024,4029 ****
--- 4209,4225 ----
    return unshare_p ? unshare_expr (decl) : decl;
  }
  
+ /* Like scalar_constant_value, but can also return aggregate initializers.
+  If UNSHARE_P, return an unshared copy of the initializer.  */
+ 
+ tree
+ decl_really_constant_value (tree decl, bool unshare_p /*= true*/)
+ {
+   return constant_value_1 (decl, /*strict_p=*/true,
+ 			   /*return_aggregate_cst_ok_p=*/true,
+ 			   /*unshare_p=*/unshare_p);
+ }
+ 
  // A more relaxed version of decl_really_constant_value, used by the
  // common C/C++ code.
  tree
*************** decl_constant_value (tree decl, bool uns
*** 4037,4051 ****
  static void
  non_const_var_error (location_t loc, tree r)
  {
!   error_at (loc,
! 	    "the value of %qD is not usable in a constant "
! 	    "expression",
! 	    r);
    /* Avoid error cascade.  */
    if (DECL_INITIAL (r) == error_mark_node)
      return;
! 
!   // more in cp/constexpr.cc
  }
  
  static tree
--- 4233,4270 ----
  static void
  non_const_var_error (location_t loc, tree r)
  {
!   tree type = TREE_TYPE (r);
! 
    /* Avoid error cascade.  */
    if (DECL_INITIAL (r) == error_mark_node)
      return;
!   if (DECL_DECLARED_CONSTEXPR_P (r))
!     inform (DECL_SOURCE_LOCATION (r), "%qD used in its own initializer", r);
!   else if (INTEGRAL_OR_ENUMERATION_TYPE_P (type))
!     {
!       if (!DECL_INITIAL (r) || !TREE_CONSTANT (DECL_INITIAL (r))
! 	  || !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (r))
! 	inform (DECL_SOURCE_LOCATION (r),
! 		"%qD was not initialized with a constant "
! 		"expression",
! 		r);
!       else
! 	gcc_unreachable ();
!     }
!   else if (TYPE_REF_P (type))
!     inform (DECL_SOURCE_LOCATION (r),
! 	    "%qD was not initialized with a constant "
! 	    "expression",
! 	    r);
!   else
!     {
!       if (!DECL_DECLARED_CONSTEXPR_P (r))
! 	inform (DECL_SOURCE_LOCATION (r), "%qD was not declared %<constexpr%>",
! 		r);
!       else
! 	inform (DECL_SOURCE_LOCATION (r),
! 		"%qD does not have integral or enumeration type", r);
!     }
  }
  
  static tree
*************** verify_constant (tree t, bool allow_non_
*** 4322,4328 ****
    if (!*non_constant_p && !reduced_constant_expression_p (t) && t != void_node)
      {
        if (!allow_non_constant)
! 	error ("%q+E is not a constant expression", t);
        *non_constant_p = true;
      }
    if (TREE_OVERFLOW_P (t))
--- 4541,4547 ----
    if (!*non_constant_p && !reduced_constant_expression_p (t) && t != void_node)
      {
        if (!allow_non_constant)
! 	error_at (EXPR_LOCATION (t), "is not a constant expression");
        *non_constant_p = true;
      }
    if (TREE_OVERFLOW_P (t))
*************** diag_array_subscript (location_t loc, co
*** 4427,4433 ****
  
  static tree
  get_array_or_vector_nelts (const constexpr_ctx *ctx, tree type,
! 			   bool *non_constant_p, bool *overflow_p)
  {
    tree nelts;
    if (TREE_CODE (type) == ARRAY_TYPE)
--- 4646,4653 ----
  
  static tree
  get_array_or_vector_nelts (const constexpr_ctx *ctx, tree type,
! 			   bool *non_constant_p, bool *overflow_p,
! 			   tree *jump_target)
  {
    tree nelts;
    if (TREE_CODE (type) == ARRAY_TYPE)
*************** get_array_or_vector_nelts (const constex
*** 4443,4450 ****
      rust_unreachable ();
  
    /* For VLAs, the number of elements won't be an integer constant.  */
!   nelts
!     = eval_constant_expression (ctx, nelts, false, non_constant_p, overflow_p);
    return nelts;
  }
  
--- 4663,4670 ----
      rust_unreachable ();
  
    /* For VLAs, the number of elements won't be an integer constant.  */
!   nelts = eval_constant_expression (ctx, nelts, false, non_constant_p,
! 				    overflow_p, jump_target);
    return nelts;
  }
  
*************** get_array_or_vector_nelts (const constex
*** 4456,4468 ****
  static tree
  eval_and_check_array_index (const constexpr_ctx *ctx, tree t,
  			    bool allow_one_past, bool *non_constant_p,
! 			    bool *overflow_p)
  {
    location_t loc = rs_expr_loc_or_input_loc (t);
    tree ary = TREE_OPERAND (t, 0);
    t = TREE_OPERAND (t, 1);
    tree index = eval_constant_expression (ctx, t, allow_one_past, non_constant_p,
! 					 overflow_p);
    VERIFY_CONSTANT (index);
  
    if (!tree_fits_shwi_p (index) || tree_int_cst_sgn (index) < 0)
--- 4676,4688 ----
  static tree
  eval_and_check_array_index (const constexpr_ctx *ctx, tree t,
  			    bool allow_one_past, bool *non_constant_p,
! 			    bool *overflow_p, tree *jump_target)
  {
    location_t loc = rs_expr_loc_or_input_loc (t);
    tree ary = TREE_OPERAND (t, 0);
    t = TREE_OPERAND (t, 1);
    tree index = eval_constant_expression (ctx, t, allow_one_past, non_constant_p,
! 					 overflow_p, jump_target);
    VERIFY_CONSTANT (index);
  
    if (!tree_fits_shwi_p (index) || tree_int_cst_sgn (index) < 0)
*************** eval_and_check_array_index (const conste
*** 4473,4479 ****
      }
  
    tree nelts = get_array_or_vector_nelts (ctx, TREE_TYPE (ary), non_constant_p,
! 					  overflow_p);
    VERIFY_CONSTANT (nelts);
    if (allow_one_past ? !tree_int_cst_le (index, nelts)
  		     : !tree_int_cst_lt (index, nelts))
--- 4693,4699 ----
      }
  
    tree nelts = get_array_or_vector_nelts (ctx, TREE_TYPE (ary), non_constant_p,
! 					  overflow_p, jump_target);
    VERIFY_CONSTANT (nelts);
    if (allow_one_past ? !tree_int_cst_le (index, nelts)
  		     : !tree_int_cst_lt (index, nelts))
*************** eval_conditional_expression (const const
*** 4683,4691 ****
  			     bool *non_constant_p, bool *overflow_p,
  			     tree *jump_target)
  {
!   tree val
!     = eval_constant_expression (ctx, TREE_OPERAND (t, 0),
! 				/*lval*/ false, non_constant_p, overflow_p);
    VERIFY_CONSTANT (val);
    if (TREE_CODE (t) == IF_STMT && IF_STMT_CONSTEVAL_P (t))
      {
--- 4903,4911 ----
  			     bool *non_constant_p, bool *overflow_p,
  			     tree *jump_target)
  {
!   tree val = eval_constant_expression (ctx, TREE_OPERAND (t, 0),
! 				       /*lval*/ false, non_constant_p,
! 				       overflow_p, jump_target);
    VERIFY_CONSTANT (val);
    if (TREE_CODE (t) == IF_STMT && IF_STMT_CONSTEVAL_P (t))
      {
*************** eval_conditional_expression (const const
*** 4722,4735 ****
  
  static tree
  eval_bit_field_ref (const constexpr_ctx *ctx, tree t, bool lval,
! 		    bool *non_constant_p, bool *overflow_p)
  {
    tree orig_whole = TREE_OPERAND (t, 0);
    tree retval, fldval, utype, mask;
    bool fld_seen = false;
    HOST_WIDE_INT istart, isize;
    tree whole = eval_constant_expression (ctx, orig_whole, lval, non_constant_p,
! 					 overflow_p);
    tree start, field, value;
    unsigned HOST_WIDE_INT i;
  
--- 4942,4955 ----
  
  static tree
  eval_bit_field_ref (const constexpr_ctx *ctx, tree t, bool lval,
! 		    bool *non_constant_p, bool *overflow_p, tree *jump_target)
  {
    tree orig_whole = TREE_OPERAND (t, 0);
    tree retval, fldval, utype, mask;
    bool fld_seen = false;
    HOST_WIDE_INT istart, isize;
    tree whole = eval_constant_expression (ctx, orig_whole, lval, non_constant_p,
! 					 overflow_p, jump_target);
    tree start, field, value;
    unsigned HOST_WIDE_INT i;
  
*************** eval_switch_expr (const constexpr_ctx *c
*** 4960,4967 ****
  {
    tree cond
      = TREE_CODE (t) == SWITCH_STMT ? SWITCH_STMT_COND (t) : SWITCH_COND (t);
!   cond
!     = eval_constant_expression (ctx, cond, false, non_constant_p, overflow_p);
    VERIFY_CONSTANT (cond);
    *jump_target = cond;
  
--- 5180,5187 ----
  {
    tree cond
      = TREE_CODE (t) == SWITCH_STMT ? SWITCH_STMT_COND (t) : SWITCH_COND (t);
!   cond = eval_constant_expression (ctx, cond, false, non_constant_p, overflow_p,
! 				   jump_target);
    VERIFY_CONSTANT (cond);
    *jump_target = cond;
  
*************** eval_switch_expr (const constexpr_ctx *c
*** 4995,5006 ****
  
  static tree
  eval_unary_expression (const constexpr_ctx *ctx, tree t, bool /*lval*/,
! 		       bool *non_constant_p, bool *overflow_p)
  {
    tree r;
    tree orig_arg = TREE_OPERAND (t, 0);
    tree arg = eval_constant_expression (ctx, orig_arg, /*lval*/ false,
! 				       non_constant_p, overflow_p);
    VERIFY_CONSTANT (arg);
    location_t loc = EXPR_LOCATION (t);
    enum tree_code code = TREE_CODE (t);
--- 5215,5227 ----
  
  static tree
  eval_unary_expression (const constexpr_ctx *ctx, tree t, bool /*lval*/,
! 		       bool *non_constant_p, bool *overflow_p,
! 		       tree *jump_target)
  {
    tree r;
    tree orig_arg = TREE_OPERAND (t, 0);
    tree arg = eval_constant_expression (ctx, orig_arg, /*lval*/ false,
! 				       non_constant_p, overflow_p, jump_target);
    VERIFY_CONSTANT (arg);
    location_t loc = EXPR_LOCATION (t);
    enum tree_code code = TREE_CODE (t);
*************** cxx_eval_outermost_constant_expr (tree t
*** 5136,5142 ****
  
    if (manifestly_const_eval)
      instantiate_constexpr_fns (r);
!   r = eval_constant_expression (&ctx, r, false, &non_constant_p, &overflow_p);
  
    if (!constexpr_dtor)
      verify_constant (r, allow_non_constant, &non_constant_p, &overflow_p);
--- 5357,5365 ----
  
    if (manifestly_const_eval)
      instantiate_constexpr_fns (r);
!   tree jump_target = NULL_TREE;
!   r = eval_constant_expression (&ctx, r, false, &non_constant_p, &overflow_p,
! 				&jump_target);
  
    if (!constexpr_dtor)
      verify_constant (r, allow_non_constant, &non_constant_p, &overflow_p);
*************** cxx_eval_outermost_constant_expr (tree t
*** 5148,5154 ****
    /* Evaluate the cleanups.  */
    FOR_EACH_VEC_ELT_REVERSE (cleanups, i, cleanup)
      eval_constant_expression (&ctx, cleanup, false, &non_constant_p,
! 			      &overflow_p);
  
    /* Mutable logic is a bit tricky: we want to allow initialization of
       constexpr variables with mutable members, but we can't copy those
--- 5371,5377 ----
    /* Evaluate the cleanups.  */
    FOR_EACH_VEC_ELT_REVERSE (cleanups, i, cleanup)
      eval_constant_expression (&ctx, cleanup, false, &non_constant_p,
! 			      &overflow_p, NULL);
  
    /* Mutable logic is a bit tricky: we want to allow initialization of
       constexpr variables with mutable members, but we can't copy those
*************** potential_constant_expression_1 (tree t,
*** 5908,5914 ****
  	/* A pointer-to-member constant.  */
  	return true;
  
- 	// handle_addr_expr:
  #if 0
        /* FIXME adjust when issue 1197 is fully resolved.  For now don't do
           any checking here, as we might dereference the pointer later.  If
--- 6131,6136 ----
*************** fold_non_dependent_init (tree t, tsubst_
*** 6484,6489 ****
--- 6706,6875 ----
    return maybe_constant_init (t, object, manifestly_const_eval);
  }
  
+ /* Check whether the shift operation with code CODE and type TYPE on LHS
+    and RHS is undefined.  If it is, give an error with an explanation,
+    and return true; return false otherwise.  */
+ 
+ static bool
+ eval_check_shift_p (location_t loc, const constexpr_ctx *ctx,
+ 		    enum tree_code code, tree type, tree lhs, tree rhs)
+ {
+   if ((code != LSHIFT_EXPR && code != RSHIFT_EXPR)
+       || TREE_CODE (lhs) != INTEGER_CST || TREE_CODE (rhs) != INTEGER_CST)
+     return false;
+ 
+   tree lhstype = TREE_TYPE (lhs);
+   unsigned HOST_WIDE_INT uprec = TYPE_PRECISION (TREE_TYPE (lhs));
+ 
+   /* [expr.shift] The behavior is undefined if the right operand
+      is negative, or greater than or equal to the length in bits
+      of the promoted left operand.  */
+   if (tree_int_cst_sgn (rhs) == -1)
+     {
+       if (!ctx->quiet)
+ 	permerror (loc, "right operand of shift expression %q+E is negative",
+ 		   build2_loc (loc, code, type, lhs, rhs));
+       return (!flag_permissive || ctx->quiet);
+     }
+   if (compare_tree_int (rhs, uprec) >= 0)
+     {
+       if (!ctx->quiet)
+ 	permerror (loc,
+ 		   "right operand of shift expression %q+E is greater "
+ 		   "than or equal to the precision %wu of the left operand",
+ 		   build2_loc (loc, code, type, lhs, rhs), uprec);
+       return (!flag_permissive || ctx->quiet);
+     }
+ 
+   /* The value of E1 << E2 is E1 left-shifted E2 bit positions; [...]
+      if E1 has a signed type and non-negative value, and E1x2^E2 is
+      representable in the corresponding unsigned type of the result type,
+      then that value, converted to the result type, is the resulting value;
+      otherwise, the behavior is undefined.
+      For C++20:
+      The value of E1 << E2 is the unique value congruent to E1 x 2^E2 modulo
+      2^N, where N is the range exponent of the type of the result.  */
+   if (code == LSHIFT_EXPR && !TYPE_OVERFLOW_WRAPS (lhstype))
+     {
+       if (tree_int_cst_sgn (lhs) == -1)
+ 	{
+ 	  if (!ctx->quiet)
+ 	    permerror (loc, "left operand of shift expression %q+E is negative",
+ 		       build2_loc (loc, code, type, lhs, rhs));
+ 	  return (!flag_permissive || ctx->quiet);
+ 	}
+       /* For signed x << y the following:
+ 	 (unsigned) x >> ((prec (lhs) - 1) - y)
+ 	 if > 1, is undefined.  The right-hand side of this formula
+ 	 is the highest bit of the LHS that can be set (starting from 0),
+ 	 so that the shift doesn't overflow.  We then right-shift the LHS
+ 	 to see whether any other bit is set making the original shift
+ 	 undefined -- the result is not representable in the corresponding
+ 	 unsigned type.  */
+       tree t = build_int_cst (unsigned_type_node, uprec - 1);
+       t = fold_build2 (MINUS_EXPR, unsigned_type_node, t, rhs);
+       tree ulhs = fold_convert (unsigned_type_for (lhstype), lhs);
+       t = fold_build2 (RSHIFT_EXPR, TREE_TYPE (ulhs), ulhs, t);
+       if (tree_int_cst_lt (integer_one_node, t))
+ 	{
+ 	  if (!ctx->quiet)
+ 	    permerror (loc, "shift expression %q+E overflows",
+ 		       build2_loc (loc, code, type, lhs, rhs));
+ 	  return (!flag_permissive || ctx->quiet);
+ 	}
+     }
+   return false;
+ }
+ 
+ /* Helper function for cxx_eval_binary_expression.  Try to optimize
+    original POINTER_PLUS_EXPR T, LHS p+ RHS, return NULL_TREE if the
+    generic folding should be used.  */
+ 
+ static tree
+ fold_pointer_plus_expression (const constexpr_ctx *ctx, tree t, tree lhs,
+ 			      tree rhs, bool *non_constant_p, bool *overflow_p,
+ 			      tree *jump_target)
+ {
+   STRIP_NOPS (lhs);
+   if (TREE_CODE (lhs) != ADDR_EXPR)
+     return NULL_TREE;
+ 
+   lhs = TREE_OPERAND (lhs, 0);
+ 
+   /* &A[i] p+ j => &A[i + j] */
+   if (TREE_CODE (lhs) == ARRAY_REF
+       && TREE_CODE (TREE_OPERAND (lhs, 1)) == INTEGER_CST
+       && TREE_CODE (rhs) == INTEGER_CST && TYPE_SIZE_UNIT (TREE_TYPE (lhs))
+       && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST)
+     {
+       tree orig_type = TREE_TYPE (t);
+       location_t loc = EXPR_LOCATION (t);
+       tree type = TREE_TYPE (lhs);
+ 
+       t = fold_convert_loc (loc, ssizetype, TREE_OPERAND (lhs, 1));
+       tree nelts = array_type_nelts_top (TREE_TYPE (TREE_OPERAND (lhs, 0)));
+       nelts = eval_constant_expression (ctx, nelts, true, non_constant_p,
+ 					overflow_p, jump_target);
+       if (*non_constant_p)
+ 	return NULL_TREE;
+       if (*jump_target)
+ 	return NULL_TREE;
+       /* Don't fold an out-of-bound access.  */
+       if (!tree_int_cst_le (t, nelts))
+ 	return NULL_TREE;
+       rhs = fold_convert (ssizetype, rhs);
+       /* Don't fold if rhs can't be divided exactly by TYPE_SIZE_UNIT.
+ 	 constexpr int A[1]; ... (char *)&A[0] + 1 */
+       if (!integer_zerop (fold_build2_loc (loc, TRUNC_MOD_EXPR, sizetype, rhs,
+ 					   TYPE_SIZE_UNIT (type))))
+ 	return NULL_TREE;
+       /* Make sure to treat the second operand of POINTER_PLUS_EXPR
+ 	 as signed.  */
+       rhs = fold_build2_loc (loc, EXACT_DIV_EXPR, ssizetype, rhs,
+ 			     TYPE_SIZE_UNIT (type));
+       t = size_binop_loc (loc, PLUS_EXPR, rhs, t);
+       t = build4_loc (loc, ARRAY_REF, type, TREE_OPERAND (lhs, 0), t, NULL_TREE,
+ 		      NULL_TREE);
+       t = build_fold_addr_expr (t);
+       t = fold_convert (orig_type, t);
+       return eval_constant_expression (ctx, t, true, non_constant_p, overflow_p,
+ 				       jump_target);
+     }
+ 
+   return NULL_TREE;
+ }
+ 
+ /* Try to fold expressions like
+    (struct S *) (&a[0].D.2378 + 12)
+    into
+    &MEM <struct T> [(void *)&a + 12B]
+    This is something normally done by gimple_fold_stmt_to_constant_1
+    on GIMPLE, but is undesirable on GENERIC if we are e.g. going to
+    dereference the address because some details are lost.
+    For pointer comparisons we want such folding though so that
+    match.pd address_compare optimization works.  */
+ 
+ static tree
+ maybe_fold_addr_pointer_plus (tree t)
+ {
+   while (CONVERT_EXPR_P (t) && POINTER_TYPE_P (TREE_TYPE (TREE_OPERAND (t, 0))))
+     t = TREE_OPERAND (t, 0);
+   if (TREE_CODE (t) != POINTER_PLUS_EXPR)
+     return NULL_TREE;
+   tree op0 = TREE_OPERAND (t, 0);
+   tree op1 = TREE_OPERAND (t, 1);
+   if (TREE_CODE (op1) != INTEGER_CST)
+     return NULL_TREE;
+   while (CONVERT_EXPR_P (op0)
+ 	 && POINTER_TYPE_P (TREE_TYPE (TREE_OPERAND (op0, 0))))
+     op0 = TREE_OPERAND (op0, 0);
+   if (TREE_CODE (op0) != ADDR_EXPR)
+     return NULL_TREE;
+   op1 = fold_convert (ptr_type_node, op1);
+   tree r = fold_build2 (MEM_REF, TREE_TYPE (TREE_TYPE (op0)), op0, op1);
+   return build1_loc (EXPR_LOCATION (t), ADDR_EXPR, TREE_TYPE (op0), r);
+ }
+ 
  } // namespace Compile
  } // namespace Rust
  
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-bir-builder-internal.h gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-bir-builder-internal.h
*** gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-bir-builder-internal.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-bir-builder-internal.h	Sun Nov  2 22:32:23 2025
***************
*** 24,30 ****
  #include "rust-hir-item.h"
  #include "rust-hir-type-check.h"
  #include "rust-hir-visitor.h"
- #include "rust-name-resolver.h"
  #include "rust-bir.h"
  #include "rust-bir-free-region.h"
  #include "rust-immutable-name-resolution-context.h"
--- 24,29 ----
*************** struct BuilderContext
*** 75,81 ****
  
    // External context.
    Resolver::TypeCheckContext &tyctx;
!   Resolver::Resolver &resolver;
  
    // BIR output
    BasicBlocks basic_blocks;
--- 74,80 ----
  
    // External context.
    Resolver::TypeCheckContext &tyctx;
!   const Resolver2_0::NameResolutionContext &resolver;
  
    // BIR output
    BasicBlocks basic_blocks;
*************** struct BuilderContext
*** 104,110 ****
  public:
    BuilderContext ()
      : tyctx (*Resolver::TypeCheckContext::get ()),
!       resolver (*Resolver::Resolver::get ())
    {
      basic_blocks.emplace_back (); // StartBB
    }
--- 103,109 ----
  public:
    BuilderContext ()
      : tyctx (*Resolver::TypeCheckContext::get ()),
!       resolver (Resolver2_0::ImmutableNameResolutionContext::get ().resolver ())
    {
      basic_blocks.emplace_back (); // StartBB
    }
*************** protected: // HIR resolution helpers
*** 403,471 ****
  
    template <typename T> NodeId resolve_label (T &expr)
    {
!     NodeId resolved_label;
!     if (flag_name_resolution_2_0)
!       {
! 	auto &nr_ctx
! 	  = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
! 	auto res = nr_ctx.lookup (expr.get_mappings ().get_nodeid ());
! 	rust_assert (res.has_value ());
! 	resolved_label = res.value ();
!       }
!     else
!       {
! 	bool ok = ctx.resolver.lookup_resolved_label (
! 	  expr.get_mappings ().get_nodeid (), &resolved_label);
! 	rust_assert (ok);
!       }
!     return resolved_label;
    }
  
    template <typename T> PlaceId resolve_variable (T &variable)
    {
!     NodeId variable_id;
!     if (flag_name_resolution_2_0)
!       {
! 	auto &nr_ctx
! 	  = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
! 	auto res = nr_ctx.lookup (variable.get_mappings ().get_nodeid ());
! 	rust_assert (res.has_value ());
! 	variable_id = res.value ();
!       }
!     else
!       {
! 	bool ok = ctx.resolver.lookup_resolved_name (
! 	  variable.get_mappings ().get_nodeid (), &variable_id);
! 	rust_assert (ok);
!       }
!     return ctx.place_db.lookup_variable (variable_id);
    }
  
    template <typename T>
    PlaceId resolve_variable_or_fn (T &variable, TyTy::BaseType *ty)
    {
      ty = (ty) ? ty : lookup_type (variable);
      // Unlike variables,
      // functions do not have to be declared in PlaceDB before use.
-     NodeId variable_id;
-     if (flag_name_resolution_2_0)
-       {
- 	auto &nr_ctx
- 	  = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
- 	auto res = nr_ctx.lookup (variable.get_mappings ().get_nodeid ());
- 	rust_assert (res.has_value ());
- 	variable_id = res.value ();
-       }
-     else
-       {
- 	bool ok = ctx.resolver.lookup_resolved_name (
- 	  variable.get_mappings ().get_nodeid (), &variable_id);
- 	rust_assert (ok);
-       }
      if (ty->is<TyTy::FnType> ())
        return ctx.place_db.get_constant (ty);
!     else
!       return ctx.place_db.lookup_or_add_variable (variable_id, ty);
    }
  
  protected: // Implicit conversions.
--- 402,432 ----
  
    template <typename T> NodeId resolve_label (T &expr)
    {
!     auto res = ctx.resolver.lookup (expr.get_mappings ().get_nodeid ());
!     rust_assert (res.has_value ());
!     return res.value ();
    }
  
    template <typename T> PlaceId resolve_variable (T &variable)
    {
!     auto res = ctx.resolver.lookup (variable.get_mappings ().get_nodeid ());
!     rust_assert (res.has_value ());
!     return ctx.place_db.lookup_variable (res.value ());
    }
  
    template <typename T>
    PlaceId resolve_variable_or_fn (T &variable, TyTy::BaseType *ty)
    {
      ty = (ty) ? ty : lookup_type (variable);
+ 
      // Unlike variables,
      // functions do not have to be declared in PlaceDB before use.
      if (ty->is<TyTy::FnType> ())
        return ctx.place_db.get_constant (ty);
! 
!     auto res = ctx.resolver.lookup (variable.get_mappings ().get_nodeid ());
!     rust_assert (res.has_value ());
!     return ctx.place_db.lookup_or_add_variable (res.value (), ty);
    }
  
  protected: // Implicit conversions.
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.cc gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.cc
*** gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-bir-builder-pattern.cc	Sun Nov  2 22:32:23 2025
*************** PatternBindingBuilder::visit (HIR::Slice
*** 70,80 ****
      return ty->as<TyTy::SliceType> ()->get_element_type ();
    });
  
!   // Regions are unchnaged.
  
!   for (auto &item : pattern.get_items ())
      {
!       item->accept_vis (*this);
      }
  }
  
--- 70,103 ----
      return ty->as<TyTy::SliceType> ()->get_element_type ();
    });
  
!   // Regions are unchanged.
  
!   switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::SlicePatternItems::NO_REST:
!       {
! 	auto &items
! 	  = static_cast<HIR::SlicePatternItemsNoRest &> (pattern.get_items ());
! 	for (auto &member : items.get_patterns ())
! 	  {
! 	    member->accept_vis (*this);
! 	  }
! 	break;
!       }
!     case HIR::SlicePatternItems::HAS_REST:
!       {
! 	auto &items
! 	  = static_cast<HIR::SlicePatternItemsHasRest &> (pattern.get_items ());
! 	for (auto &member : items.get_lower_patterns ())
! 	  {
! 	    member->accept_vis (*this);
! 	  }
! 	for (auto &member : items.get_upper_patterns ())
! 	  {
! 	    member->accept_vis (*this);
! 	  }
! 	break;
!       }
      }
  }
  
*************** PatternBindingBuilder::visit (HIR::Tuple
*** 202,218 ****
    size_t index = 0;
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::MULTIPLE:
        {
! 	auto &items = static_cast<HIR::TuplePatternItemsMultiple &> (
! 	  pattern.get_items ());
  	visit_tuple_fields (items.get_patterns (), saved, index);
  	break;
        }
!     case HIR::TuplePatternItems::RANGED:
        {
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsRanged &> (pattern.get_items ());
  
  	auto tyty = ctx.place_db[init.value ()].tyty;
  	rust_assert (tyty->get_kind () == TyTy::TUPLE);
--- 225,241 ----
    size_t index = 0;
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::NO_REST:
        {
! 	auto &items
! 	  = static_cast<HIR::TuplePatternItemsNoRest &> (pattern.get_items ());
  	visit_tuple_fields (items.get_patterns (), saved, index);
  	break;
        }
!     case HIR::TuplePatternItems::HAS_REST:
        {
  	auto &items
! 	  = static_cast<HIR::TuplePatternItemsHasRest &> (pattern.get_items ());
  
  	auto tyty = ctx.place_db[init.value ()].tyty;
  	rust_assert (tyty->get_kind () == TyTy::TUPLE);
*************** PatternBindingBuilder::visit (HIR::Tuple
*** 249,258 ****
    size_t index = 0;
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TupleStructItems::RANGED:
        {
  	auto &items
! 	  = static_cast<HIR::TupleStructItemsRange &> (pattern.get_items ());
  
  	rust_assert (type->get_kind () == TyTy::ADT);
  	auto adt_ty = static_cast<TyTy::ADTType *> (type);
--- 272,281 ----
    size_t index = 0;
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TupleStructItems::HAS_REST:
        {
  	auto &items
! 	  = static_cast<HIR::TupleStructItemsHasRest &> (pattern.get_items ());
  
  	rust_assert (type->get_kind () == TyTy::ADT);
  	auto adt_ty = static_cast<TyTy::ADTType *> (type);
*************** PatternBindingBuilder::visit (HIR::Tuple
*** 267,276 ****
  	visit_tuple_fields (items.get_upper_patterns (), saved, index);
  	break;
        }
!     case HIR::TupleStructItems::MULTIPLE:
        {
  	auto &items
! 	  = static_cast<HIR::TupleStructItemsNoRange &> (pattern.get_items ());
  	visit_tuple_fields (items.get_patterns (), saved, index);
  	break;
        }
--- 290,299 ----
  	visit_tuple_fields (items.get_upper_patterns (), saved, index);
  	break;
        }
!     case HIR::TupleStructItems::NO_REST:
        {
  	auto &items
! 	  = static_cast<HIR::TupleStructItemsNoRest &> (pattern.get_items ());
  	visit_tuple_fields (items.get_patterns (), saved, index);
  	break;
        }
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h
*** gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-bir-builder-struct.h	Sun Nov  2 22:32:23 2025
*************** protected:
*** 225,235 ****
      rust_unreachable ();
    }
    void visit (HIR::StructPattern &pattern) override { rust_unreachable (); }
!   void visit (HIR::TupleStructItemsNoRange &tuple_items) override
    {
      rust_unreachable ();
    }
!   void visit (HIR::TupleStructItemsRange &tuple_items) override
    {
      rust_unreachable ();
    }
--- 225,235 ----
      rust_unreachable ();
    }
    void visit (HIR::StructPattern &pattern) override { rust_unreachable (); }
!   void visit (HIR::TupleStructItemsNoRest &tuple_items) override
    {
      rust_unreachable ();
    }
!   void visit (HIR::TupleStructItemsHasRest &tuple_items) override
    {
      rust_unreachable ();
    }
*************** protected:
*** 237,251 ****
    {
      rust_unreachable ();
    }
!   void visit (HIR::TuplePatternItemsMultiple &tuple_items) override
    {
      rust_unreachable ();
    }
!   void visit (HIR::TuplePatternItemsRanged &tuple_items) override
    {
      rust_unreachable ();
    }
    void visit (HIR::TuplePattern &pattern) override { rust_unreachable (); }
    void visit (HIR::SlicePattern &pattern) override { rust_unreachable (); }
    void visit (HIR::AltPattern &pattern) override { rust_unreachable (); }
    void visit (HIR::EmptyStmt &stmt) override { rust_unreachable (); }
--- 237,259 ----
    {
      rust_unreachable ();
    }
!   void visit (HIR::TuplePatternItemsNoRest &tuple_items) override
    {
      rust_unreachable ();
    }
!   void visit (HIR::TuplePatternItemsHasRest &tuple_items) override
    {
      rust_unreachable ();
    }
    void visit (HIR::TuplePattern &pattern) override { rust_unreachable (); }
+   void visit (HIR::SlicePatternItemsNoRest &tuple_items) override
+   {
+     rust_unreachable ();
+   }
+   void visit (HIR::SlicePatternItemsHasRest &tuple_items) override
+   {
+     rust_unreachable ();
+   }
    void visit (HIR::SlicePattern &pattern) override { rust_unreachable (); }
    void visit (HIR::AltPattern &pattern) override { rust_unreachable (); }
    void visit (HIR::EmptyStmt &stmt) override { rust_unreachable (); }
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-function-collector.h gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-function-collector.h
*** gcc-16-20251026/gcc/rust/checks/errors/borrowck/rust-function-collector.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/borrowck/rust-function-collector.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 170,181 ****
    void visit (HIR::StructPatternFieldIdentPat &field) override {}
    void visit (HIR::StructPatternFieldIdent &field) override {}
    void visit (HIR::StructPattern &pattern) override {}
!   void visit (HIR::TupleStructItemsNoRange &tuple_items) override {}
!   void visit (HIR::TupleStructItemsRange &tuple_items) override {}
    void visit (HIR::TupleStructPattern &pattern) override {}
!   void visit (HIR::TuplePatternItemsMultiple &tuple_items) override {}
!   void visit (HIR::TuplePatternItemsRanged &tuple_items) override {}
    void visit (HIR::TuplePattern &pattern) override {}
    void visit (HIR::SlicePattern &pattern) override {}
    void visit (HIR::AltPattern &pattern) override {}
    void visit (HIR::EmptyStmt &stmt) override {}
--- 170,183 ----
    void visit (HIR::StructPatternFieldIdentPat &field) override {}
    void visit (HIR::StructPatternFieldIdent &field) override {}
    void visit (HIR::StructPattern &pattern) override {}
!   void visit (HIR::TupleStructItemsNoRest &tuple_items) override {}
!   void visit (HIR::TupleStructItemsHasRest &tuple_items) override {}
    void visit (HIR::TupleStructPattern &pattern) override {}
!   void visit (HIR::TuplePatternItemsNoRest &tuple_items) override {}
!   void visit (HIR::TuplePatternItemsHasRest &tuple_items) override {}
    void visit (HIR::TuplePattern &pattern) override {}
+   void visit (HIR::SlicePatternItemsNoRest &tuple_items) override {}
+   void visit (HIR::SlicePatternItemsHasRest &tuple_items) override {}
    void visit (HIR::SlicePattern &pattern) override {}
    void visit (HIR::AltPattern &pattern) override {}
    void visit (HIR::EmptyStmt &stmt) override {}
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature-gate.cc gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature-gate.cc
*** gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature-gate.cc	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature-gate.cc	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,246 ----
+ // Copyright (C) 2020-2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "rust-feature-gate.h"
+ #include "rust-abi.h"
+ #include "rust-attribute-values.h"
+ #include "rust-ast-visitor.h"
+ #include "rust-feature.h"
+ #include "rust-ast-full.h"
+ 
+ namespace Rust {
+ 
+ void
+ FeatureGate::check (AST::Crate &crate)
+ {
+   visit (crate);
+ }
+ 
+ void
+ FeatureGate::visit (AST::Crate &crate)
+ {
+   valid_features.clear ();
+ 
+   for (const auto &attr : crate.inner_attrs)
+     {
+       if (attr.get_path ().as_string () == "feature")
+ 	{
+ 	  // check for empty feature, such as `#![feature], this is an error
+ 	  if (attr.empty_input ())
+ 	    {
+ 	      rust_error_at (attr.get_locus (), ErrorCode::E0556,
+ 			     "malformed %<feature%> attribute input");
+ 	      continue;
+ 	    }
+ 	  const auto &attr_input = attr.get_attr_input ();
+ 	  auto type = attr_input.get_attr_input_type ();
+ 	  if (type == AST::AttrInput::AttrInputType::TOKEN_TREE)
+ 	    {
+ 	      const auto &option = static_cast<const AST::DelimTokenTree &> (
+ 		attr.get_attr_input ());
+ 	      std::unique_ptr<AST::AttrInputMetaItemContainer> meta_item (
+ 		option.parse_to_meta_item ());
+ 	      for (const auto &item : meta_item->get_items ())
+ 		{
+ 		  const auto &name_str = item->as_string ();
+ 		  auto tname = Feature::as_name (name_str);
+ 		  if (tname.has_value ())
+ 		    {
+ 		      auto name = tname.value ();
+ 		      valid_features.insert (name);
+ 		    }
+ 
+ 		  else
+ 		    rust_error_at (item->get_locus (), ErrorCode::E0635,
+ 				   "unknown feature %qs", name_str.c_str ());
+ 		}
+ 	    }
+ 	}
+     }
+ 
+   AST::DefaultASTVisitor::visit (crate);
+ }
+ 
+ void
+ FeatureGate::gate (Feature::Name name, location_t loc,
+ 		   const std::string &error_msg)
+ {
+   if (!valid_features.count (name))
+     {
+       auto feature = Feature::create (name);
+       if (auto issue = feature.issue ())
+ 	{
+ 	  auto issue_number = issue.value ();
+ 	  const char *fmt_str
+ 	    = "%s. see issue %u "
+ 	      "<https://github.com/rust-lang/rust/issues/%u> for more "
+ 	      "information. add `#![feature(%s)]` to the crate attributes to "
+ 	      "enable.";
+ 	  rust_error_at (loc, ErrorCode::E0658, fmt_str, error_msg.c_str (),
+ 			 issue_number, issue_number,
+ 			 feature.as_string ().c_str ());
+ 	}
+       else
+ 	{
+ 	  const char *fmt_str
+ 	    = "%s. add `#![feature(%s)]` to the crate attributes to enable.";
+ 	  rust_error_at (loc, ErrorCode::E0658, fmt_str, error_msg.c_str (),
+ 			 feature.as_string ().c_str ());
+ 	}
+     }
+ }
+ 
+ void
+ FeatureGate::visit (AST::ExternBlock &block)
+ {
+   if (block.has_abi ())
+     {
+       const auto abi = block.get_abi ();
+ 
+       if (get_abi_from_string (abi) == ABI::INTRINSIC)
+ 	gate (Feature::Name::INTRINSICS, block.get_locus (),
+ 	      "intrinsics are subject to change");
+     }
+   AST::DefaultASTVisitor::visit (block);
+ }
+ 
+ void
+ FeatureGate::check_rustc_attri (const std::vector<AST::Attribute> &attributes)
+ {
+   for (const AST::Attribute &attr : attributes)
+     {
+       auto name = attr.get_path ().as_string ();
+       if (name.rfind ("rustc_", 0) == 0)
+ 	{
+ 	  gate (Feature::Name::RUSTC_ATTRS, attr.get_locus (),
+ 		"internal implementation detail");
+ 	}
+     }
+ }
+ 
+ void
+ FeatureGate::check_may_dangle_attribute (
+   const std::vector<AST::Attribute> &attributes)
+ {
+   for (const AST::Attribute &attr : attributes)
+     {
+       if (attr.get_path ().as_string () == Values::Attributes::MAY_DANGLE)
+ 	gate (Feature::Name::DROPCK_EYEPATCH, attr.get_locus (),
+ 	      "`may_dangle` has unstable semantics and may be removed in the "
+ 	      "future");
+     }
+ }
+ 
+ void
+ FeatureGate::visit (AST::MacroRulesDefinition &rules_def)
+ {
+   check_rustc_attri (rules_def.get_outer_attrs ());
+ }
+ 
+ void
+ FeatureGate::visit (AST::Function &function)
+ {
+   if (!function.is_external ())
+     check_rustc_attri (function.get_outer_attrs ());
+ 
+   AST::DefaultASTVisitor::visit (function);
+ }
+ 
+ void
+ FeatureGate::visit (AST::ExternalTypeItem &item)
+ {
+   // TODO(mxlol233): The gating needs a complete visiting chain to activate
+   // `AST::ExternalTypeItem`.
+   gate (Feature::Name::EXTERN_TYPES, item.get_locus (),
+ 	"extern types are experimental");
+ }
+ 
+ void
+ FeatureGate::visit (AST::TraitImpl &impl)
+ {
+   if (impl.is_exclam ())
+     gate (Feature::Name::NEGATIVE_IMPLS, impl.get_locus (),
+ 	  "negative_impls are not yet implemented");
+ 
+   AST::DefaultASTVisitor::visit (impl);
+ }
+ 
+ void
+ FeatureGate::visit (AST::Trait &trait)
+ {
+   if (trait.is_auto ())
+     gate (Feature::Name::AUTO_TRAITS, trait.get_locus (),
+ 	  "auto traits are experimental and possibly buggy");
+   AST::DefaultASTVisitor::visit (trait);
+ }
+ 
+ void
+ FeatureGate::visit (AST::BoxExpr &expr)
+ {
+   gate (
+     Feature::Name::BOX_SYNTAX, expr.get_locus (),
+     "box expression syntax is experimental; you can call `Box::new` instead");
+   AST::DefaultASTVisitor::visit (expr);
+ }
+ 
+ void
+ FeatureGate::visit (AST::LifetimeParam &lifetime_param)
+ {
+   check_may_dangle_attribute (lifetime_param.get_outer_attrs ());
+   AST::DefaultASTVisitor::visit (lifetime_param);
+ }
+ 
+ void
+ FeatureGate::visit (AST::ConstGenericParam &const_param)
+ {
+   check_may_dangle_attribute (const_param.get_outer_attrs ());
+   AST::DefaultASTVisitor::visit (const_param);
+ }
+ 
+ void
+ FeatureGate::visit (AST::TypeParam &param)
+ {
+   check_may_dangle_attribute (param.get_outer_attrs ());
+   AST::DefaultASTVisitor::visit (param);
+ }
+ 
+ void
+ FeatureGate::visit (AST::BorrowExpr &expr)
+ {
+   if (expr.is_raw_borrow ())
+     gate (Feature::Name::RAW_REF_OP, expr.get_locus (),
+ 	  "raw address of syntax is experimental");
+ }
+ 
+ void
+ FeatureGate::visit (AST::RangePattern &pattern)
+ {
+   if (pattern.get_range_kind () == AST::RangeKind::EXCLUDED)
+     gate (Feature::Name::EXCLUSIVE_RANGE_PATTERN, pattern.get_locus (),
+ 	  "exclusive range pattern syntax is experimental");
+ }
+ 
+ void
+ FeatureGate::visit (AST::UseTreeGlob &use)
+ {
+   // At the moment, UseTrees do not have outer attributes, but they should. we
+   // need to eventually gate `#[prelude_import]` on use-trees based on the
+   // #[feature(prelude_import)]
+ }
+ 
+ } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature-gate.h gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature-gate.h
*** gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature-gate.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature-gate.h	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,59 ----
+ // Copyright (C) 2020-2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #ifndef RUST_FEATURE_GATE_H
+ #define RUST_FEATURE_GATE_H
+ 
+ #include "rust-ast-visitor.h"
+ #include "rust-feature.h"
+ 
+ namespace Rust {
+ 
+ class FeatureGate : public AST::DefaultASTVisitor
+ {
+ public:
+   FeatureGate () {}
+ 
+   using AST::DefaultASTVisitor::visit;
+ 
+   void check (AST::Crate &crate);
+   void visit (AST::Crate &crate) override;
+ 
+   void visit (AST::LifetimeParam &lifetime_param) override;
+   void visit (AST::ConstGenericParam &const_param) override;
+   void visit (AST::BorrowExpr &expr) override;
+   void visit (AST::BoxExpr &expr) override;
+   void visit (AST::TypeParam &param) override;
+   void visit (AST::UseTreeGlob &use_tree) override;
+   void visit (AST::Function &function) override;
+   void visit (AST::TraitImpl &impl) override;
+   void visit (AST::Trait &trait) override;
+   void visit (AST::ExternalTypeItem &item) override;
+   void visit (AST::ExternBlock &block) override;
+   void visit (AST::MacroRulesDefinition &rules_def) override;
+   void visit (AST::RangePattern &pattern) override;
+ 
+ private:
+   void gate (Feature::Name name, location_t loc, const std::string &error_msg);
+   void check_rustc_attri (const std::vector<AST::Attribute> &attributes);
+   void
+   check_may_dangle_attribute (const std::vector<AST::Attribute> &attributes);
+   std::set<Feature::Name> valid_features;
+ };
+ } // namespace Rust
+ #endif
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature.cc gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature.cc
*** gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature.cc	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature.cc	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,98 ----
+ // Copyright (C) 2020-2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "rust-feature.h"
+ 
+ namespace Rust {
+ 
+ Feature
+ Feature::create (Feature::Name f)
+ {
+   switch (f)
+     {
+     case Feature::Name::ASSOCIATED_TYPE_BOUNDS:
+       return Feature (Feature::Name::ASSOCIATED_TYPE_BOUNDS,
+ 		      Feature::State::ACCEPTED, "associated_type_bounds",
+ 		      "1.34.0", 52662);
+     case Feature::Name::INTRINSICS:
+       return Feature (f, Feature::State::ACCEPTED, "intrinsics", "1.0.0");
+     case Feature::Name::RUSTC_ATTRS:
+       return Feature (f, Feature::State::ACCEPTED, "rustc_attrs", "1.0.0");
+     case Feature::Name::DECL_MACRO:
+       return Feature (f, Feature::State::ACCEPTED, "decl_macro", "1.0.0",
+ 		      39412);
+     case Feature::Name::EXTERN_TYPES:
+       return Feature (f, Feature::State::ACTIVE, "extern_types", "1.23.0",
+ 		      43467);
+     case Feature::Name::NEGATIVE_IMPLS:
+       return Feature (f, Feature::State::ACTIVE, "negative_impls", "1.0.0",
+ 		      68318);
+     case Feature::Name::BOX_SYNTAX:
+       return Feature (f, Feature::State::ACTIVE, "box_syntax", "1.0.0", 49733);
+     case Feature::Name::DROPCK_EYEPATCH:
+       return Feature (f, Feature::State::ACTIVE, "dropck_eyepatch", "1.10.0",
+ 		      34761);
+     case Feature::Name::RAW_REF_OP:
+       return Feature (f, Feature::State::ACTIVE, "raw_ref_op", "1.41.0", 64490);
+     case Feature::Name::EXCLUSIVE_RANGE_PATTERN:
+       return Feature (Feature::Name::EXCLUSIVE_RANGE_PATTERN,
+ 		      Feature::State::ACTIVE, "exclusive_range_pattern",
+ 		      "1.11.0", 37854);
+     case Feature::Name::PRELUDE_IMPORT:
+       return Feature (f, Feature::State::ACTIVE, "prelude_import", "1.0.0");
+     case Feature::Name::MIN_SPECIALIZATION:
+       return Feature (f, Feature::State::ACTIVE, "min_specialization",
+ 		      "1.0.0" /* FIXME: What version here? */, 31844);
+     case Feature::Name::AUTO_TRAITS:
+       return Feature (f, Feature::State::ACTIVE, "optin_builtin_traits",
+ 		      "1.0.0", 13231);
+     default:
+       rust_unreachable ();
+     }
+ }
+ 
+ const std::map<std::string, Feature::Name> Feature::name_hash_map = {
+   {"associated_type_bounds", Feature::Name::ASSOCIATED_TYPE_BOUNDS},
+   {"intrinsics", Feature::Name::INTRINSICS},
+   {"rustc_attrs", Feature::Name::RUSTC_ATTRS},
+   {"decl_macro", Feature::Name::DECL_MACRO},
+   {"negative_impls", Feature::Name::NEGATIVE_IMPLS},
+   // TODO: Rename to "auto_traits" when supporting
+   // later Rust versions
+   {"optin_builtin_traits", Feature::Name::AUTO_TRAITS},
+   {"extern_types", Feature::Name::EXTERN_TYPES},
+   {"lang_items", Feature::Name::LANG_ITEMS},
+   {"no_core", Feature::Name::NO_CORE},
+   {"box_syntax", Feature::Name::BOX_SYNTAX},
+   {"dropck_eyepatch", Feature::Name::DROPCK_EYEPATCH},
+   {"raw_ref_op", Feature::Name::RAW_REF_OP},
+   {"exclusive_range_pattern", Feature::Name::EXCLUSIVE_RANGE_PATTERN},
+   {"prelude_import", Feature::Name::PRELUDE_IMPORT},
+   {"min_specialization", Feature::Name::MIN_SPECIALIZATION},
+ };
+ 
+ tl::optional<Feature::Name>
+ Feature::as_name (const std::string &name)
+ {
+   if (Feature::name_hash_map.count (name))
+     return Feature::name_hash_map.at (name);
+ 
+   return tl::nullopt;
+ }
+ 
+ } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature.h gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature.h
*** gcc-16-20251026/gcc/rust/checks/errors/feature/rust-feature.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/checks/errors/feature/rust-feature.h	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,89 ----
+ // Copyright (C) 2020-2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #ifndef RUST_FEATURE_H
+ #define RUST_FEATURE_H
+ 
+ #include "rust-edition.h"
+ #include "optional.h"
+ 
+ namespace Rust {
+ 
+ class Feature
+ {
+ public:
+   enum class State
+   {
+     ACCEPTED,
+     ACTIVE,
+     REMOVED,
+     STABILIZED,
+   };
+ 
+   enum class Name
+   {
+     ASSOCIATED_TYPE_BOUNDS,
+     INTRINSICS,
+     NEGATIVE_IMPLS,
+     RUSTC_ATTRS,
+     DECL_MACRO,
+     AUTO_TRAITS,
+     EXTERN_TYPES,
+     LANG_ITEMS,
+     NO_CORE,
+     BOX_SYNTAX,
+     DROPCK_EYEPATCH,
+     RAW_REF_OP,
+     EXCLUSIVE_RANGE_PATTERN,
+     PRELUDE_IMPORT,
+     MIN_SPECIALIZATION,
+   };
+ 
+   const std::string &as_string () { return m_name_str; }
+   Name name () { return m_name; }
+   const std::string &description () { return m_description; }
+   State state () { return m_state; }
+   tl::optional<unsigned> issue () { return m_issue; }
+ 
+   static tl::optional<Name> as_name (const std::string &name);
+   static Feature create (Name name);
+ 
+ private:
+   Feature (Name name, State state, const char *name_str,
+ 	   const char *rustc_since,
+ 	   tl::optional<unsigned> issue_number = tl::nullopt,
+ 	   const tl::optional<Edition> &edition = tl::nullopt,
+ 	   const char *description = "")
+     : m_state (state), m_name (name), m_name_str (name_str),
+       m_rustc_since (rustc_since), m_issue (issue_number), edition (edition),
+       m_description (description)
+   {}
+ 
+   State m_state;
+   Name m_name;
+   std::string m_name_str;
+   std::string m_rustc_since;
+   tl::optional<unsigned> m_issue;
+   tl::optional<Edition> edition;
+   std::string m_description; // TODO: Switch to optional?
+ 
+   static const std::map<std::string, Name> name_hash_map;
+ };
+ 
+ } // namespace Rust
+ #endif
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-privacy-check.cc gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-privacy-check.cc
*** gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-privacy-check.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-privacy-check.cc	Sun Nov  2 22:32:23 2025
***************
*** 20,26 ****
  #include "rust-reachability.h"
  #include "rust-hir-type-check.h"
  #include "rust-hir-map.h"
! #include "rust-name-resolver.h"
  #include "rust-visibility-resolver.h"
  #include "rust-pub-restricted-visitor.h"
  #include "rust-privacy-reporter.h"
--- 20,26 ----
  #include "rust-reachability.h"
  #include "rust-hir-type-check.h"
  #include "rust-hir-map.h"
! #include "rust-immutable-name-resolution-context.h"
  #include "rust-visibility-resolver.h"
  #include "rust-pub-restricted-visitor.h"
  #include "rust-privacy-reporter.h"
*************** Resolver::resolve (HIR::Crate &crate)
*** 35,46 ****
  {
    PrivacyContext ctx;
    auto &mappings = Analysis::Mappings::get ();
!   auto resolver = Rust::Resolver::Resolver::get ();
    auto ty_ctx = ::Rust::Resolver::TypeCheckContext::get ();
  
!   VisibilityResolver (mappings, *resolver).go (crate);
    PubRestrictedVisitor (mappings).go (crate);
!   PrivacyReporter (mappings, *resolver, *ty_ctx).go (crate);
  
    auto visitor = ReachabilityVisitor (ctx, *ty_ctx);
  
--- 35,47 ----
  {
    PrivacyContext ctx;
    auto &mappings = Analysis::Mappings::get ();
!   auto &resolver
!     = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
    auto ty_ctx = ::Rust::Resolver::TypeCheckContext::get ();
  
!   VisibilityResolver (mappings, resolver).go (crate);
    PubRestrictedVisitor (mappings).go (crate);
!   PrivacyReporter (mappings, resolver, *ty_ctx).go (crate);
  
    auto visitor = ReachabilityVisitor (ctx, *ty_ctx);
  
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-privacy-reporter.cc gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-privacy-reporter.cc
*** gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-privacy-reporter.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-privacy-reporter.cc	Sun Nov  2 22:32:23 2025
*************** namespace Rust {
*** 28,34 ****
  namespace Privacy {
  
  PrivacyReporter::PrivacyReporter (
!   Analysis::Mappings &mappings, Resolver::Resolver &resolver,
    const Rust::Resolver::TypeCheckContext &ty_ctx)
    : mappings (mappings), resolver (resolver), ty_ctx (ty_ctx),
      current_module (tl::nullopt)
--- 28,35 ----
  namespace Privacy {
  
  PrivacyReporter::PrivacyReporter (
!   Analysis::Mappings &mappings,
!   const Resolver2_0::NameResolutionContext &resolver,
    const Rust::Resolver::TypeCheckContext &ty_ctx)
    : mappings (mappings), resolver (resolver), ty_ctx (ty_ctx),
      current_module (tl::nullopt)
*************** PrivacyReporter::go (HIR::Crate &crate)
*** 90,148 ****
      }
  }
  
- static bool
- is_child_module (Analysis::Mappings &mappings, NodeId parent,
- 		 NodeId possible_child)
- {
-   if (flag_name_resolution_2_0)
-     {
-       auto &nr_ctx
- 	= Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
- 
-       return nr_ctx.values.is_module_descendant (parent, possible_child);
-     }
- 
-   auto children = mappings.lookup_module_children (parent);
- 
-   if (!children)
-     return false;
- 
-   // Visit all toplevel children
-   for (auto &child : *children)
-     if (child == possible_child)
-       return true;
- 
-   // Now descend recursively in the child module tree
-   for (auto &child : *children)
-     if (is_child_module (mappings, child, possible_child))
-       return true;
- 
-   return false;
- }
- 
  // FIXME: This function needs a lot of refactoring
  void
  PrivacyReporter::check_for_privacy_violation (const NodeId &use_id,
  					      const location_t locus)
  {
!   NodeId ref_node_id = UNKNOWN_NODEID;
! 
!   if (flag_name_resolution_2_0)
!     {
!       auto &nr_ctx
! 	= Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
! 
!       if (auto id = nr_ctx.lookup (use_id))
! 	ref_node_id = *id;
!     }
!   // FIXME: Don't assert here - we might be dealing with a type
!   else if (!resolver.lookup_resolved_name (use_id, &ref_node_id))
!     resolver.lookup_resolved_type (use_id, &ref_node_id);
  
    // FIXME: Assert here. For now, we return since this causes issues when
    // checking inferred types (#1260)
!   // rust_assert (ref_node_id != UNKNOWN_NODEID);
!   if (ref_node_id == UNKNOWN_NODEID)
      return;
  
    auto vis = mappings.lookup_visibility (ref_node_id);
--- 91,108 ----
      }
  }
  
  // FIXME: This function needs a lot of refactoring
  void
  PrivacyReporter::check_for_privacy_violation (const NodeId &use_id,
  					      const location_t locus)
  {
!   NodeId ref_node_id;
  
    // FIXME: Assert here. For now, we return since this causes issues when
    // checking inferred types (#1260)
!   if (auto id = resolver.lookup (use_id))
!     ref_node_id = *id;
!   else
      return;
  
    auto vis = mappings.lookup_visibility (ref_node_id);
*************** PrivacyReporter::check_for_privacy_viola
*** 175,181 ****
  
  	// FIXME: This needs a LOT of TLC: hinting about the definition, a
  	// string to say if it's a module, function, type, etc...
! 	if (!is_child_module (mappings, mod_node_id, current_module.value ()))
  	  valid = false;
        }
        break;
--- 135,143 ----
  
  	// FIXME: This needs a LOT of TLC: hinting about the definition, a
  	// string to say if it's a module, function, type, etc...
! 
! 	if (!resolver.values.is_module_descendant (mod_node_id,
! 						   current_module.value ()))
  	  valid = false;
        }
        break;
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-privacy-reporter.h gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-privacy-reporter.h
*** gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-privacy-reporter.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-privacy-reporter.h	Sun Nov  2 22:32:23 2025
***************
*** 22,29 ****
  #include "rust-hir-expr.h"
  #include "rust-hir-map.h"
  #include "rust-hir-visitor.h"
  #include "rust-mapping-common.h"
! #include "rust-name-resolver.h"
  
  namespace Rust {
  namespace Privacy {
--- 22,30 ----
  #include "rust-hir-expr.h"
  #include "rust-hir-map.h"
  #include "rust-hir-visitor.h"
+ #include "rust-hir-type-check.h"
  #include "rust-mapping-common.h"
! #include "rust-name-resolution-context.h"
  
  namespace Rust {
  namespace Privacy {
*************** class PrivacyReporter : public HIR::HIRE
*** 38,44 ****
  {
  public:
    PrivacyReporter (Analysis::Mappings &mappings,
! 		   Rust::Resolver::Resolver &resolver,
  		   const Rust::Resolver::TypeCheckContext &ty_ctx);
  
    /**
--- 39,45 ----
  {
  public:
    PrivacyReporter (Analysis::Mappings &mappings,
! 		   const Resolver2_0::NameResolutionContext &resolver,
  		   const Rust::Resolver::TypeCheckContext &ty_ctx);
  
    /**
*************** types
*** 157,163 ****
    virtual void visit (HIR::ExprStmt &stmt);
  
    Analysis::Mappings &mappings;
!   Rust::Resolver::Resolver &resolver;
    const Rust::Resolver::TypeCheckContext &ty_ctx;
  
    // `None` means we're in the root module - the crate
--- 158,164 ----
    virtual void visit (HIR::ExprStmt &stmt);
  
    Analysis::Mappings &mappings;
!   const Resolver2_0::NameResolutionContext &resolver;
    const Rust::Resolver::TypeCheckContext &ty_ctx;
  
    // `None` means we're in the root module - the crate
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-visibility-resolver.cc gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-visibility-resolver.cc
*** gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-visibility-resolver.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-visibility-resolver.cc	Sun Nov  2 22:32:23 2025
***************
*** 20,35 ****
  #include "rust-ast.h"
  #include "rust-hir.h"
  #include "rust-hir-item.h"
! #include "rust-immutable-name-resolution-context.h"
! 
! // for flag_name_resolution_2_0
! #include "options.h"
  
  namespace Rust {
  namespace Privacy {
  
! VisibilityResolver::VisibilityResolver (Analysis::Mappings &mappings,
! 					Resolver::Resolver &resolver)
    : mappings (mappings), resolver (resolver)
  {}
  
--- 20,33 ----
  #include "rust-ast.h"
  #include "rust-hir.h"
  #include "rust-hir-item.h"
! #include "rust-name-resolution-context.h"
  
  namespace Rust {
  namespace Privacy {
  
! VisibilityResolver::VisibilityResolver (
!   Analysis::Mappings &mappings,
!   const Resolver2_0::NameResolutionContext &resolver)
    : mappings (mappings), resolver (resolver)
  {}
  
*************** VisibilityResolver::resolve_module_path
*** 64,86 ****
      = Error (restriction.get_locus (),
  	     "cannot use non-module path as privacy restrictor");
  
!   NodeId ref_node_id = UNKNOWN_NODEID;
!   if (flag_name_resolution_2_0)
      {
!       auto &nr_ctx
! 	= Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
! 
!       if (auto id = nr_ctx.lookup (ast_node_id))
! 	{
! 	  ref_node_id = *id;
! 	}
!       else
! 	{
! 	  invalid_path.emit ();
! 	  return false;
! 	}
      }
!   else if (!resolver.lookup_resolved_name (ast_node_id, &ref_node_id))
      {
        invalid_path.emit ();
        return false;
--- 62,73 ----
      = Error (restriction.get_locus (),
  	     "cannot use non-module path as privacy restrictor");
  
!   NodeId ref_node_id;
!   if (auto id = resolver.lookup (ast_node_id))
      {
!       ref_node_id = *id;
      }
!   else
      {
        invalid_path.emit ();
        return false;
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-visibility-resolver.h gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-visibility-resolver.h
*** gcc-16-20251026/gcc/rust/checks/errors/privacy/rust-visibility-resolver.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/privacy/rust-visibility-resolver.h	Sun Nov  2 22:32:23 2025
***************
*** 24,30 ****
  #include "rust-hir-stmt.h"
  #include "rust-hir-item.h"
  #include "rust-hir-map.h"
! #include "rust-name-resolver.h"
  #include "rust-hir-visitor.h"
  
  namespace Rust {
--- 24,30 ----
  #include "rust-hir-stmt.h"
  #include "rust-hir-item.h"
  #include "rust-hir-map.h"
! #include "rust-name-resolution-context.h"
  #include "rust-hir-visitor.h"
  
  namespace Rust {
*************** class VisibilityResolver : public HIR::H
*** 34,40 ****
  {
  public:
    VisibilityResolver (Analysis::Mappings &mappings,
! 		      Rust::Resolver::Resolver &resolver);
  
    /**
     * Perform visibility resolving on an entire crate
--- 34,40 ----
  {
  public:
    VisibilityResolver (Analysis::Mappings &mappings,
! 		      const Resolver2_0::NameResolutionContext &resolver);
  
    /**
     * Perform visibility resolving on an entire crate
*************** public:
*** 93,99 ****
  
  private:
    Analysis::Mappings &mappings;
!   Rust::Resolver::Resolver &resolver;
    DefId current_module;
  };
  
--- 93,99 ----
  
  private:
    Analysis::Mappings &mappings;
!   const Resolver2_0::NameResolutionContext &resolver;
    DefId current_module;
  };
  
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-const-checker.cc gcc-16-20251102/gcc/rust/checks/errors/rust-const-checker.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-const-checker.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-const-checker.cc	Sun Nov  2 22:32:23 2025
*************** ConstChecker::visit (StructPattern &)
*** 813,823 ****
  {}
  
  void
! ConstChecker::visit (TupleStructItemsNoRange &)
  {}
  
  void
! ConstChecker::visit (TupleStructItemsRange &)
  {}
  
  void
--- 813,823 ----
  {}
  
  void
! ConstChecker::visit (TupleStructItemsNoRest &)
  {}
  
  void
! ConstChecker::visit (TupleStructItemsHasRest &)
  {}
  
  void
*************** ConstChecker::visit (TupleStructPattern
*** 825,835 ****
  {}
  
  void
! ConstChecker::visit (TuplePatternItemsMultiple &)
  {}
  
  void
! ConstChecker::visit (TuplePatternItemsRanged &)
  {}
  
  void
--- 825,835 ----
  {}
  
  void
! ConstChecker::visit (TuplePatternItemsNoRest &)
  {}
  
  void
! ConstChecker::visit (TuplePatternItemsHasRest &)
  {}
  
  void
*************** ConstChecker::visit (TuplePattern &)
*** 837,842 ****
--- 837,850 ----
  {}
  
  void
+ ConstChecker::visit (SlicePatternItemsNoRest &)
+ {}
+ 
+ void
+ ConstChecker::visit (SlicePatternItemsHasRest &)
+ {}
+ 
+ void
  ConstChecker::visit (SlicePattern &)
  {}
  
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-const-checker.h gcc-16-20251102/gcc/rust/checks/errors/rust-const-checker.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-const-checker.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-const-checker.h	Sun Nov  2 22:32:23 2025
*************** private:
*** 180,191 ****
    virtual void visit (StructPatternFieldIdentPat &field) override;
    virtual void visit (StructPatternFieldIdent &field) override;
    virtual void visit (StructPattern &pattern) override;
!   virtual void visit (TupleStructItemsNoRange &tuple_items) override;
!   virtual void visit (TupleStructItemsRange &tuple_items) override;
    virtual void visit (TupleStructPattern &pattern) override;
!   virtual void visit (TuplePatternItemsMultiple &tuple_items) override;
!   virtual void visit (TuplePatternItemsRanged &tuple_items) override;
    virtual void visit (TuplePattern &pattern) override;
    virtual void visit (SlicePattern &pattern) override;
    virtual void visit (AltPattern &pattern) override;
    virtual void visit (EmptyStmt &stmt) override;
--- 180,193 ----
    virtual void visit (StructPatternFieldIdentPat &field) override;
    virtual void visit (StructPatternFieldIdent &field) override;
    virtual void visit (StructPattern &pattern) override;
!   virtual void visit (TupleStructItemsNoRest &tuple_items) override;
!   virtual void visit (TupleStructItemsHasRest &tuple_items) override;
    virtual void visit (TupleStructPattern &pattern) override;
!   virtual void visit (TuplePatternItemsNoRest &tuple_items) override;
!   virtual void visit (TuplePatternItemsHasRest &tuple_items) override;
    virtual void visit (TuplePattern &pattern) override;
+   virtual void visit (SlicePatternItemsNoRest &items) override;
+   virtual void visit (SlicePatternItemsHasRest &items) override;
    virtual void visit (SlicePattern &pattern) override;
    virtual void visit (AltPattern &pattern) override;
    virtual void visit (EmptyStmt &stmt) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-feature-gate.cc gcc-16-20251102/gcc/rust/checks/errors/rust-feature-gate.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-feature-gate.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-feature-gate.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,246 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-feature-gate.h"
- #include "rust-abi.h"
- #include "rust-attribute-values.h"
- #include "rust-ast-visitor.h"
- #include "rust-feature.h"
- #include "rust-ast-full.h"
- 
- namespace Rust {
- 
- void
- FeatureGate::check (AST::Crate &crate)
- {
-   visit (crate);
- }
- 
- void
- FeatureGate::visit (AST::Crate &crate)
- {
-   valid_features.clear ();
- 
-   for (const auto &attr : crate.inner_attrs)
-     {
-       if (attr.get_path ().as_string () == "feature")
- 	{
- 	  // check for empty feature, such as `#![feature], this is an error
- 	  if (attr.empty_input ())
- 	    {
- 	      rust_error_at (attr.get_locus (), ErrorCode::E0556,
- 			     "malformed %<feature%> attribute input");
- 	      continue;
- 	    }
- 	  const auto &attr_input = attr.get_attr_input ();
- 	  auto type = attr_input.get_attr_input_type ();
- 	  if (type == AST::AttrInput::AttrInputType::TOKEN_TREE)
- 	    {
- 	      const auto &option = static_cast<const AST::DelimTokenTree &> (
- 		attr.get_attr_input ());
- 	      std::unique_ptr<AST::AttrInputMetaItemContainer> meta_item (
- 		option.parse_to_meta_item ());
- 	      for (const auto &item : meta_item->get_items ())
- 		{
- 		  const auto &name_str = item->as_string ();
- 		  auto tname = Feature::as_name (name_str);
- 		  if (tname.has_value ())
- 		    {
- 		      auto name = tname.value ();
- 		      valid_features.insert (name);
- 		    }
- 
- 		  else
- 		    rust_error_at (item->get_locus (), ErrorCode::E0635,
- 				   "unknown feature %qs", name_str.c_str ());
- 		}
- 	    }
- 	}
-     }
- 
-   AST::DefaultASTVisitor::visit (crate);
- }
- 
- void
- FeatureGate::gate (Feature::Name name, location_t loc,
- 		   const std::string &error_msg)
- {
-   if (!valid_features.count (name))
-     {
-       auto feature = Feature::create (name);
-       if (auto issue = feature.issue ())
- 	{
- 	  auto issue_number = issue.value ();
- 	  const char *fmt_str
- 	    = "%s. see issue %u "
- 	      "<https://github.com/rust-lang/rust/issues/%u> for more "
- 	      "information. add `#![feature(%s)]` to the crate attributes to "
- 	      "enable.";
- 	  rust_error_at (loc, ErrorCode::E0658, fmt_str, error_msg.c_str (),
- 			 issue_number, issue_number,
- 			 feature.as_string ().c_str ());
- 	}
-       else
- 	{
- 	  const char *fmt_str
- 	    = "%s. add `#![feature(%s)]` to the crate attributes to enable.";
- 	  rust_error_at (loc, ErrorCode::E0658, fmt_str, error_msg.c_str (),
- 			 feature.as_string ().c_str ());
- 	}
-     }
- }
- 
- void
- FeatureGate::visit (AST::ExternBlock &block)
- {
-   if (block.has_abi ())
-     {
-       const auto abi = block.get_abi ();
- 
-       if (get_abi_from_string (abi) == ABI::INTRINSIC)
- 	gate (Feature::Name::INTRINSICS, block.get_locus (),
- 	      "intrinsics are subject to change");
-     }
-   AST::DefaultASTVisitor::visit (block);
- }
- 
- void
- FeatureGate::check_rustc_attri (const std::vector<AST::Attribute> &attributes)
- {
-   for (const AST::Attribute &attr : attributes)
-     {
-       auto name = attr.get_path ().as_string ();
-       if (name.rfind ("rustc_", 0) == 0)
- 	{
- 	  gate (Feature::Name::RUSTC_ATTRS, attr.get_locus (),
- 		"internal implementation detail");
- 	}
-     }
- }
- 
- void
- FeatureGate::check_may_dangle_attribute (
-   const std::vector<AST::Attribute> &attributes)
- {
-   for (const AST::Attribute &attr : attributes)
-     {
-       if (attr.get_path ().as_string () == Values::Attributes::MAY_DANGLE)
- 	gate (Feature::Name::DROPCK_EYEPATCH, attr.get_locus (),
- 	      "`may_dangle` has unstable semantics and may be removed in the "
- 	      "future");
-     }
- }
- 
- void
- FeatureGate::visit (AST::MacroRulesDefinition &rules_def)
- {
-   check_rustc_attri (rules_def.get_outer_attrs ());
- }
- 
- void
- FeatureGate::visit (AST::Function &function)
- {
-   if (!function.is_external ())
-     check_rustc_attri (function.get_outer_attrs ());
- 
-   AST::DefaultASTVisitor::visit (function);
- }
- 
- void
- FeatureGate::visit (AST::ExternalTypeItem &item)
- {
-   // TODO(mxlol233): The gating needs a complete visiting chain to activate
-   // `AST::ExternalTypeItem`.
-   gate (Feature::Name::EXTERN_TYPES, item.get_locus (),
- 	"extern types are experimental");
- }
- 
- void
- FeatureGate::visit (AST::TraitImpl &impl)
- {
-   if (impl.is_exclam ())
-     gate (Feature::Name::NEGATIVE_IMPLS, impl.get_locus (),
- 	  "negative_impls are not yet implemented");
- 
-   AST::DefaultASTVisitor::visit (impl);
- }
- 
- void
- FeatureGate::visit (AST::Trait &trait)
- {
-   if (trait.is_auto ())
-     gate (Feature::Name::AUTO_TRAITS, trait.get_locus (),
- 	  "auto traits are experimental and possibly buggy");
-   AST::DefaultASTVisitor::visit (trait);
- }
- 
- void
- FeatureGate::visit (AST::BoxExpr &expr)
- {
-   gate (
-     Feature::Name::BOX_SYNTAX, expr.get_locus (),
-     "box expression syntax is experimental; you can call `Box::new` instead");
-   AST::DefaultASTVisitor::visit (expr);
- }
- 
- void
- FeatureGate::visit (AST::LifetimeParam &lifetime_param)
- {
-   check_may_dangle_attribute (lifetime_param.get_outer_attrs ());
-   AST::DefaultASTVisitor::visit (lifetime_param);
- }
- 
- void
- FeatureGate::visit (AST::ConstGenericParam &const_param)
- {
-   check_may_dangle_attribute (const_param.get_outer_attrs ());
-   AST::DefaultASTVisitor::visit (const_param);
- }
- 
- void
- FeatureGate::visit (AST::TypeParam &param)
- {
-   check_may_dangle_attribute (param.get_outer_attrs ());
-   AST::DefaultASTVisitor::visit (param);
- }
- 
- void
- FeatureGate::visit (AST::BorrowExpr &expr)
- {
-   if (expr.is_raw_borrow ())
-     gate (Feature::Name::RAW_REF_OP, expr.get_locus (),
- 	  "raw address of syntax is experimental");
- }
- 
- void
- FeatureGate::visit (AST::RangePattern &pattern)
- {
-   if (pattern.get_range_kind () == AST::RangeKind::EXCLUDED)
-     gate (Feature::Name::EXCLUSIVE_RANGE_PATTERN, pattern.get_locus (),
- 	  "exclusive range pattern syntax is experimental");
- }
- 
- void
- FeatureGate::visit (AST::UseTreeGlob &use)
- {
-   // At the moment, UseTrees do not have outer attributes, but they should. we
-   // need to eventually gate `#[prelude_import]` on use-trees based on the
-   // #[feature(prelude_import)]
- }
- 
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-feature-gate.h gcc-16-20251102/gcc/rust/checks/errors/rust-feature-gate.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-feature-gate.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-feature-gate.h	Thu Jan  1 00:00:00 1970
***************
*** 1,59 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_FEATURE_GATE_H
- #define RUST_FEATURE_GATE_H
- 
- #include "rust-ast-visitor.h"
- #include "rust-feature.h"
- 
- namespace Rust {
- 
- class FeatureGate : public AST::DefaultASTVisitor
- {
- public:
-   FeatureGate () {}
- 
-   using AST::DefaultASTVisitor::visit;
- 
-   void check (AST::Crate &crate);
-   void visit (AST::Crate &crate) override;
- 
-   void visit (AST::LifetimeParam &lifetime_param) override;
-   void visit (AST::ConstGenericParam &const_param) override;
-   void visit (AST::BorrowExpr &expr) override;
-   void visit (AST::BoxExpr &expr) override;
-   void visit (AST::TypeParam &param) override;
-   void visit (AST::UseTreeGlob &use_tree) override;
-   void visit (AST::Function &function) override;
-   void visit (AST::TraitImpl &impl) override;
-   void visit (AST::Trait &trait) override;
-   void visit (AST::ExternalTypeItem &item) override;
-   void visit (AST::ExternBlock &block) override;
-   void visit (AST::MacroRulesDefinition &rules_def) override;
-   void visit (AST::RangePattern &pattern) override;
- 
- private:
-   void gate (Feature::Name name, location_t loc, const std::string &error_msg);
-   void check_rustc_attri (const std::vector<AST::Attribute> &attributes);
-   void
-   check_may_dangle_attribute (const std::vector<AST::Attribute> &attributes);
-   std::set<Feature::Name> valid_features;
- };
- } // namespace Rust
- #endif
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-feature.cc gcc-16-20251102/gcc/rust/checks/errors/rust-feature.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-feature.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-feature.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,98 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-feature.h"
- 
- namespace Rust {
- 
- Feature
- Feature::create (Feature::Name f)
- {
-   switch (f)
-     {
-     case Feature::Name::ASSOCIATED_TYPE_BOUNDS:
-       return Feature (Feature::Name::ASSOCIATED_TYPE_BOUNDS,
- 		      Feature::State::ACCEPTED, "associated_type_bounds",
- 		      "1.34.0", 52662);
-     case Feature::Name::INTRINSICS:
-       return Feature (f, Feature::State::ACCEPTED, "intrinsics", "1.0.0");
-     case Feature::Name::RUSTC_ATTRS:
-       return Feature (f, Feature::State::ACCEPTED, "rustc_attrs", "1.0.0");
-     case Feature::Name::DECL_MACRO:
-       return Feature (f, Feature::State::ACCEPTED, "decl_macro", "1.0.0",
- 		      39412);
-     case Feature::Name::EXTERN_TYPES:
-       return Feature (f, Feature::State::ACTIVE, "extern_types", "1.23.0",
- 		      43467);
-     case Feature::Name::NEGATIVE_IMPLS:
-       return Feature (f, Feature::State::ACTIVE, "negative_impls", "1.0.0",
- 		      68318);
-     case Feature::Name::BOX_SYNTAX:
-       return Feature (f, Feature::State::ACTIVE, "box_syntax", "1.0.0", 49733);
-     case Feature::Name::DROPCK_EYEPATCH:
-       return Feature (f, Feature::State::ACTIVE, "dropck_eyepatch", "1.10.0",
- 		      34761);
-     case Feature::Name::RAW_REF_OP:
-       return Feature (f, Feature::State::ACTIVE, "raw_ref_op", "1.41.0", 64490);
-     case Feature::Name::EXCLUSIVE_RANGE_PATTERN:
-       return Feature (Feature::Name::EXCLUSIVE_RANGE_PATTERN,
- 		      Feature::State::ACTIVE, "exclusive_range_pattern",
- 		      "1.11.0", 37854);
-     case Feature::Name::PRELUDE_IMPORT:
-       return Feature (f, Feature::State::ACTIVE, "prelude_import", "1.0.0");
-     case Feature::Name::MIN_SPECIALIZATION:
-       return Feature (f, Feature::State::ACTIVE, "min_specialization",
- 		      "1.0.0" /* FIXME: What version here? */, 31844);
-     case Feature::Name::AUTO_TRAITS:
-       return Feature (f, Feature::State::ACTIVE, "optin_builtin_traits",
- 		      "1.0.0", 13231);
-     default:
-       rust_unreachable ();
-     }
- }
- 
- const std::map<std::string, Feature::Name> Feature::name_hash_map = {
-   {"associated_type_bounds", Feature::Name::ASSOCIATED_TYPE_BOUNDS},
-   {"intrinsics", Feature::Name::INTRINSICS},
-   {"rustc_attrs", Feature::Name::RUSTC_ATTRS},
-   {"decl_macro", Feature::Name::DECL_MACRO},
-   {"negative_impls", Feature::Name::NEGATIVE_IMPLS},
-   // TODO: Rename to "auto_traits" when supporting
-   // later Rust versions
-   {"optin_builtin_traits", Feature::Name::AUTO_TRAITS},
-   {"extern_types", Feature::Name::EXTERN_TYPES},
-   {"lang_items", Feature::Name::LANG_ITEMS},
-   {"no_core", Feature::Name::NO_CORE},
-   {"box_syntax", Feature::Name::BOX_SYNTAX},
-   {"dropck_eyepatch", Feature::Name::DROPCK_EYEPATCH},
-   {"raw_ref_op", Feature::Name::RAW_REF_OP},
-   {"exclusive_range_pattern", Feature::Name::EXCLUSIVE_RANGE_PATTERN},
-   {"prelude_import", Feature::Name::PRELUDE_IMPORT},
-   {"min_specialization", Feature::Name::MIN_SPECIALIZATION},
- };
- 
- tl::optional<Feature::Name>
- Feature::as_name (const std::string &name)
- {
-   if (Feature::name_hash_map.count (name))
-     return Feature::name_hash_map.at (name);
- 
-   return tl::nullopt;
- }
- 
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-feature.h gcc-16-20251102/gcc/rust/checks/errors/rust-feature.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-feature.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-feature.h	Thu Jan  1 00:00:00 1970
***************
*** 1,89 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_FEATURE_H
- #define RUST_FEATURE_H
- 
- #include "rust-edition.h"
- #include "optional.h"
- 
- namespace Rust {
- 
- class Feature
- {
- public:
-   enum class State
-   {
-     ACCEPTED,
-     ACTIVE,
-     REMOVED,
-     STABILIZED,
-   };
- 
-   enum class Name
-   {
-     ASSOCIATED_TYPE_BOUNDS,
-     INTRINSICS,
-     NEGATIVE_IMPLS,
-     RUSTC_ATTRS,
-     DECL_MACRO,
-     AUTO_TRAITS,
-     EXTERN_TYPES,
-     LANG_ITEMS,
-     NO_CORE,
-     BOX_SYNTAX,
-     DROPCK_EYEPATCH,
-     RAW_REF_OP,
-     EXCLUSIVE_RANGE_PATTERN,
-     PRELUDE_IMPORT,
-     MIN_SPECIALIZATION,
-   };
- 
-   const std::string &as_string () { return m_name_str; }
-   Name name () { return m_name; }
-   const std::string &description () { return m_description; }
-   State state () { return m_state; }
-   tl::optional<unsigned> issue () { return m_issue; }
- 
-   static tl::optional<Name> as_name (const std::string &name);
-   static Feature create (Name name);
- 
- private:
-   Feature (Name name, State state, const char *name_str,
- 	   const char *rustc_since,
- 	   tl::optional<unsigned> issue_number = tl::nullopt,
- 	   const tl::optional<Edition> &edition = tl::nullopt,
- 	   const char *description = "")
-     : m_state (state), m_name (name), m_name_str (name_str),
-       m_rustc_since (rustc_since), m_issue (issue_number), edition (edition),
-       m_description (description)
-   {}
- 
-   State m_state;
-   Name m_name;
-   std::string m_name_str;
-   std::string m_rustc_since;
-   tl::optional<unsigned> m_issue;
-   tl::optional<Edition> edition;
-   std::string m_description; // TODO: Switch to optional?
- 
-   static const std::map<std::string, Name> name_hash_map;
- };
- 
- } // namespace Rust
- #endif
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-hir-pattern-analysis.cc gcc-16-20251102/gcc/rust/checks/errors/rust-hir-pattern-analysis.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-hir-pattern-analysis.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-hir-pattern-analysis.cc	Sun Nov  2 22:32:23 2025
***************
*** 28,42 ****
  #include "rust-tyty.h"
  #include "rust-immutable-name-resolution-context.h"
  
- // for flag_name_resolution_2_0
- #include "options.h"
- 
  namespace Rust {
  namespace Analysis {
  
  PatternChecker::PatternChecker ()
    : tyctx (*Resolver::TypeCheckContext::get ()),
!     resolver (*Resolver::Resolver::get ()),
      mappings (Analysis::Mappings::get ())
  {}
  
--- 28,39 ----
  #include "rust-tyty.h"
  #include "rust-immutable-name-resolution-context.h"
  
  namespace Rust {
  namespace Analysis {
  
  PatternChecker::PatternChecker ()
    : tyctx (*Resolver::TypeCheckContext::get ()),
!     resolver (Resolver2_0::ImmutableNameResolutionContext::get ().resolver ()),
      mappings (Analysis::Mappings::get ())
  {}
  
*************** PatternChecker::visit (CallExpr &expr)
*** 238,254 ****
  
    NodeId ast_node_id = expr.get_fnexpr ().get_mappings ().get_nodeid ();
    NodeId ref_node_id;
!   if (flag_name_resolution_2_0)
!     {
!       auto &nr_ctx
! 	= Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
! 
!       if (auto id = nr_ctx.lookup (ast_node_id))
! 	ref_node_id = *id;
!       else
! 	return;
!     }
!   else if (!resolver.lookup_resolved_name (ast_node_id, &ref_node_id))
      return;
  
    if (auto definition_id = mappings.lookup_node_to_hir (ref_node_id))
--- 235,243 ----
  
    NodeId ast_node_id = expr.get_fnexpr ().get_mappings ().get_nodeid ();
    NodeId ref_node_id;
!   if (auto id = resolver.lookup (ast_node_id))
!     ref_node_id = *id;
!   else
      return;
  
    if (auto definition_id = mappings.lookup_node_to_hir (ref_node_id))
*************** PatternChecker::visit (StructPattern &)
*** 640,650 ****
  {}
  
  void
! PatternChecker::visit (TupleStructItemsNoRange &)
  {}
  
  void
! PatternChecker::visit (TupleStructItemsRange &)
  {}
  
  void
--- 629,639 ----
  {}
  
  void
! PatternChecker::visit (TupleStructItemsNoRest &)
  {}
  
  void
! PatternChecker::visit (TupleStructItemsHasRest &)
  {}
  
  void
*************** PatternChecker::visit (TupleStructPatter
*** 652,662 ****
  {}
  
  void
! PatternChecker::visit (TuplePatternItemsMultiple &)
  {}
  
  void
! PatternChecker::visit (TuplePatternItemsRanged &)
  {}
  
  void
--- 641,651 ----
  {}
  
  void
! PatternChecker::visit (TuplePatternItemsNoRest &)
  {}
  
  void
! PatternChecker::visit (TuplePatternItemsHasRest &)
  {}
  
  void
*************** PatternChecker::visit (TuplePattern &)
*** 664,669 ****
--- 653,666 ----
  {}
  
  void
+ PatternChecker::visit (SlicePatternItemsNoRest &)
+ {}
+ 
+ void
+ PatternChecker::visit (SlicePatternItemsHasRest &)
+ {}
+ 
+ void
  PatternChecker::visit (SlicePattern &)
  {}
  
*************** Matrix::specialize (const Constructor &c
*** 980,986 ****
        if (ctor.is_covered_by (hd.ctor ()))
  	{
  	  pats.pop_head_constructor (ctor, subfields_place_info.size ());
! 	  new_rows.push_back (MatrixRow (pats, row.is_under_guard ()));
  	}
      }
  
--- 977,983 ----
        if (ctor.is_covered_by (hd.ctor ()))
  	{
  	  pats.pop_head_constructor (ctor, subfields_place_info.size ());
! 	  new_rows.emplace_back (pats, row.is_under_guard ());
  	}
      }
  
*************** WitnessMatrix::apply_constructor (const
*** 1186,1192 ****
  	    }
  	}
  
!       stack.push_back (WitnessPat (ctor, subfield, ty));
      }
  }
  
--- 1183,1189 ----
  	    }
  	}
  
!       stack.emplace_back (ctor, subfield, ty);
      }
  }
  
*************** lower_tuple_pattern (Resolver::TypeCheck
*** 1213,1239 ****
    std::vector<DeconstructedPat> fields;
    switch (elems.get_item_type ())
      {
!     case HIR::TupleStructItems::ItemType::MULTIPLE:
        {
! 	HIR::TupleStructItemsNoRange &multiple
! 	  = static_cast<HIR::TupleStructItemsNoRange &> (elems);
  
  	rust_assert (variant->get_fields ().size ()
! 		     == multiple.get_patterns ().size ());
  
! 	for (size_t i = 0; i < multiple.get_patterns ().size (); i++)
  	  {
  	    fields.push_back (
! 	      lower_pattern (ctx, *multiple.get_patterns ().at (i),
  			     variant->get_fields ().at (i)->get_field_type ()));
  	  }
  	return DeconstructedPat (ctor, arity, fields, pattern.get_locus ());
        }
        break;
!     case HIR::TupleStructItems::ItemType::RANGED:
        {
! 	// TODO: ranged tuple struct items
! 	rust_unreachable ();
        }
        break;
      default:
--- 1210,1263 ----
    std::vector<DeconstructedPat> fields;
    switch (elems.get_item_type ())
      {
!     case HIR::TupleStructItems::ItemType::NO_REST:
        {
! 	HIR::TupleStructItemsNoRest &items_no_rest
! 	  = static_cast<HIR::TupleStructItemsNoRest &> (elems);
  
  	rust_assert (variant->get_fields ().size ()
! 		     == items_no_rest.get_patterns ().size ());
  
! 	for (size_t i = 0; i < items_no_rest.get_patterns ().size (); i++)
  	  {
  	    fields.push_back (
! 	      lower_pattern (ctx, *items_no_rest.get_patterns ().at (i),
  			     variant->get_fields ().at (i)->get_field_type ()));
  	  }
  	return DeconstructedPat (ctor, arity, fields, pattern.get_locus ());
        }
        break;
!     case HIR::TupleStructItems::ItemType::HAS_REST:
        {
! 	HIR::TupleStructItemsHasRest &items_has_rest
! 	  = static_cast<HIR::TupleStructItemsHasRest &> (elems);
! 
! 	size_t num_patterns = items_has_rest.get_lower_patterns ().size ()
! 			      + items_has_rest.get_upper_patterns ().size ();
! 
! 	rust_assert (num_patterns <= variant->num_fields ());
! 
! 	size_t i = 0;
! 	for (auto &pattern_member : items_has_rest.get_lower_patterns ())
! 	  {
! 	    fields.push_back (lower_pattern (
! 	      ctx, *pattern_member,
! 	      variant->get_fields ().at (i++)->get_field_type ()));
! 	  }
! 	while (i < variant->num_fields ()
! 		     - items_has_rest.get_upper_patterns ().size ())
! 	  {
! 	    fields.push_back (
! 	      DeconstructedPat::make_wildcard (pattern.get_locus ()));
! 	    i++;
! 	  }
! 	for (auto &pattern_member : items_has_rest.get_upper_patterns ())
! 	  {
! 	    fields.push_back (lower_pattern (
! 	      ctx, *pattern_member,
! 	      variant->get_fields ().at (i++)->get_field_type ()));
! 	  }
! 	return DeconstructedPat (ctor, arity, fields, pattern.get_locus ());
        }
        break;
      default:
*************** check_match_usefulness (Resolver::TypeCh
*** 1597,1603 ****
        MatchArm lowered = lower_arm (ctx, arm, scrutinee_ty);
        PatOrWild pat = PatOrWild::make_pattern (lowered.get_pat ());
        pats.push (pat);
!       rows.push_back (MatrixRow (pats, lowered.has_guard ()));
      }
  
    std::vector<PlaceInfo> place_infos = {{PlaceInfo (scrutinee_ty)}};
--- 1621,1627 ----
        MatchArm lowered = lower_arm (ctx, arm, scrutinee_ty);
        PatOrWild pat = PatOrWild::make_pattern (lowered.get_pat ());
        pats.push (pat);
!       rows.emplace_back (pats, lowered.has_guard ());
      }
  
    std::vector<PlaceInfo> place_infos = {{PlaceInfo (scrutinee_ty)}};
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-hir-pattern-analysis.h gcc-16-20251102/gcc/rust/checks/errors/rust-hir-pattern-analysis.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-hir-pattern-analysis.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-hir-pattern-analysis.h	Sun Nov  2 22:32:23 2025
***************
*** 26,32 ****
  #include "rust-tyty.h"
  #include "optional.h"
  #include "rust-hir-visitor.h"
! #include "rust-name-resolver.h"
  
  namespace Rust {
  namespace Analysis {
--- 26,32 ----
  #include "rust-tyty.h"
  #include "optional.h"
  #include "rust-hir-visitor.h"
! #include "rust-immutable-name-resolution-context.h"
  
  namespace Rust {
  namespace Analysis {
*************** public:
*** 46,52 ****
  
  private:
    Resolver::TypeCheckContext &tyctx;
!   Resolver::Resolver &resolver;
    Analysis::Mappings &mappings;
  
    virtual void visit (Lifetime &lifetime) override;
--- 46,52 ----
  
  private:
    Resolver::TypeCheckContext &tyctx;
!   const Resolver2_0::NameResolutionContext &resolver;
    Analysis::Mappings &mappings;
  
    virtual void visit (Lifetime &lifetime) override;
*************** private:
*** 153,164 ****
    virtual void visit (StructPatternFieldIdentPat &field) override;
    virtual void visit (StructPatternFieldIdent &field) override;
    virtual void visit (StructPattern &pattern) override;
!   virtual void visit (TupleStructItemsNoRange &tuple_items) override;
!   virtual void visit (TupleStructItemsRange &tuple_items) override;
    virtual void visit (TupleStructPattern &pattern) override;
!   virtual void visit (TuplePatternItemsMultiple &tuple_items) override;
!   virtual void visit (TuplePatternItemsRanged &tuple_items) override;
    virtual void visit (TuplePattern &pattern) override;
    virtual void visit (SlicePattern &pattern) override;
    virtual void visit (AltPattern &pattern) override;
    virtual void visit (EmptyStmt &stmt) override;
--- 153,166 ----
    virtual void visit (StructPatternFieldIdentPat &field) override;
    virtual void visit (StructPatternFieldIdent &field) override;
    virtual void visit (StructPattern &pattern) override;
!   virtual void visit (TupleStructItemsNoRest &tuple_items) override;
!   virtual void visit (TupleStructItemsHasRest &tuple_items) override;
    virtual void visit (TupleStructPattern &pattern) override;
!   virtual void visit (TuplePatternItemsNoRest &tuple_items) override;
!   virtual void visit (TuplePatternItemsHasRest &tuple_items) override;
    virtual void visit (TuplePattern &pattern) override;
+   virtual void visit (SlicePatternItemsNoRest &items) override;
+   virtual void visit (SlicePatternItemsHasRest &items) override;
    virtual void visit (SlicePattern &pattern) override;
    virtual void visit (AltPattern &pattern) override;
    virtual void visit (EmptyStmt &stmt) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check.cc gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check.cc	Sun Nov  2 22:32:23 2025
***************
*** 1,4 ****
! // Copyright (C) 2021-2025 Free Software Foundation, Inc.
  
  // This file is part of GCC.
  
--- 1,4 ----
! // Copyright (C) 2025 Free Software Foundation, Inc.
  
  // This file is part of GCC.
  
***************
*** 17,200 ****
  // <http://www.gnu.org/licenses/>.
  
  #include "rust-readonly-check.h"
! #include "rust-tree.h"
! #include "rust-gcc.h"
! #include "print-tree.h"
  
  namespace Rust {
! namespace Analysis {
  
! static std::map<tree, int> assignment_map = {};
  
- // ported over from c-family/c-warn.cc
  void
! readonly_error (location_t loc, tree arg, enum lvalue_use use)
  {
!   gcc_assert (use == lv_assign || use == lv_increment || use == lv_decrement
! 	      || use == lv_asm);
!   STRIP_ANY_LOCATION_WRAPPER (arg);
!   /* Using this macro rather than (for example) arrays of messages
!      ensures that all the format strings are checked at compile
!      time.  */
! #define READONLY_MSG(A, I, D, AS)                                              \
!   (use == lv_assign                                                            \
!      ? (A)                                                                     \
!      : (use == lv_increment ? (I) : (use == lv_decrement ? (D) : (AS))))
!   if (TREE_CODE (arg) == COMPONENT_REF)
      {
!       if (TYPE_READONLY (TREE_TYPE (TREE_OPERAND (arg, 0))))
! 	error_at (loc,
! 		  READONLY_MSG (G_ ("assignment of member "
! 				    "%qD in read-only object"),
! 				G_ ("increment of member "
! 				    "%qD in read-only object"),
! 				G_ ("decrement of member "
! 				    "%qD in read-only object"),
! 				G_ ("member %qD in read-only object "
! 				    "used as %<asm%> output")),
! 		  TREE_OPERAND (arg, 1));
!       else
! 	error_at (
! 	  loc,
! 	  READONLY_MSG (G_ ("assignment of read-only member %qD"),
! 			G_ ("increment of read-only member %qD"),
! 			G_ ("decrement of read-only member %qD"),
! 			G_ ("read-only member %qD used as %<asm%> output")),
! 	  TREE_OPERAND (arg, 1));
      }
!   else if (VAR_P (arg))
!     error_at (loc,
! 	      READONLY_MSG (G_ ("assignment of read-only variable %qD"),
! 			    G_ ("increment of read-only variable %qD"),
! 			    G_ ("decrement of read-only variable %qD"),
! 			    G_ (
! 			      "read-only variable %qD used as %<asm%> output")),
! 	      arg);
!   else if (TREE_CODE (arg) == PARM_DECL)
!     error_at (loc,
! 	      READONLY_MSG (G_ ("assignment of read-only parameter %qD"),
! 			    G_ ("increment of read-only parameter %qD"),
! 			    G_ ("decrement of read-only parameter %qD"),
! 			    G_ (
! 			      "read-only parameter %qD use as %<asm%> output")),
! 	      arg);
!   else if (TREE_CODE (arg) == RESULT_DECL)
      {
!       error_at (loc,
! 		READONLY_MSG (G_ ("assignment of "
! 				  "read-only named return value %qD"),
! 			      G_ ("increment of "
! 				  "read-only named return value %qD"),
! 			      G_ ("decrement of "
! 				  "read-only named return value %qD"),
! 			      G_ ("read-only named return value %qD "
! 				  "used as %<asm%>output")),
! 		arg);
      }
-   else if (TREE_CODE (arg) == FUNCTION_DECL)
-     error_at (loc,
- 	      READONLY_MSG (G_ ("assignment of function %qD"),
- 			    G_ ("increment of function %qD"),
- 			    G_ ("decrement of function %qD"),
- 			    G_ ("function %qD used as %<asm%> output")),
- 	      arg);
-   else
-     error_at (loc,
- 	      READONLY_MSG (G_ ("assignment of read-only location %qE"),
- 			    G_ ("increment of read-only location %qE"),
- 			    G_ ("decrement of read-only location %qE"),
- 			    G_ (
- 			      "read-only location %qE used as %<asm%> output")),
- 	      arg);
  }
  
! static void
! emit_error (tree *t, tree lhs, enum lvalue_use use)
  {
!   readonly_error (EXPR_LOCATION (*t), lhs, use);
!   TREE_OPERAND (*t, 0) = error_mark_node;
  }
  
! static void
! check_modify_expr (tree *t)
  {
!   tree lhs = TREE_OPERAND (*t, 0);
!   if (TREE_CODE (lhs) == ARRAY_REF || TREE_CODE (lhs) == COMPONENT_REF)
!     lhs = TREE_OPERAND (lhs, 0);
! 
!   tree lhs_type = TREE_TYPE (lhs);
!   if (TYPE_READONLY (lhs_type) || TREE_READONLY (lhs) || TREE_CONSTANT (lhs))
      {
!       if (TREE_CODE (lhs) != VAR_DECL)
! 	emit_error (t, lhs, lv_assign);
!       else if (!DECL_ARTIFICIAL (lhs))
! 	{
! 	  if (DECL_INITIAL (lhs) != NULL)
! 	    emit_error (t, lhs, lv_assign);
! 	  else
! 	    {
! 	      if (assignment_map.find (lhs) == assignment_map.end ())
! 		{
! 		  assignment_map.insert ({lhs, 0});
! 		}
! 	      assignment_map[lhs]++;
! 
! 	      if (assignment_map[lhs] > 1)
! 		emit_error (t, lhs, lv_assign);
! 	    }
! 	}
      }
  }
  
! static void
! check_decl (tree *t)
  {
!   switch (TREE_CODE (*t))
      {
!     case MODIFY_EXPR:
!       check_modify_expr (t);
        break;
  
      default:
        break;
      }
  }
  
! static tree
! readonly_walk_fn (tree *t, int *, void *)
  {
!   check_decl (t);
!   return NULL_TREE;
  }
  
  void
! ReadonlyCheck::Lint (Compile::Context &ctx)
  {
!   assignment_map.clear ();
!   for (auto &fndecl : ctx.get_func_decls ())
      {
!       for (tree p = DECL_ARGUMENTS (fndecl); p != NULL_TREE; p = DECL_CHAIN (p))
! 	{
! 	  check_decl (&p);
! 	}
  
!       walk_tree_without_duplicates (&DECL_SAVED_TREE (fndecl),
! 				    &readonly_walk_fn, &ctx);
      }
  
!   assignment_map.clear ();
!   for (auto &var : ctx.get_var_decls ())
      {
!       tree decl = var->get_decl ();
!       check_decl (&decl);
      }
  
!   assignment_map.clear ();
!   for (auto &const_decl : ctx.get_const_decls ())
      {
!       check_decl (&const_decl);
      }
  }
  
! } // namespace Analysis
  } // namespace Rust
--- 17,268 ----
  // <http://www.gnu.org/licenses/>.
  
  #include "rust-readonly-check.h"
! #include "rust-hir-expr.h"
! #include "rust-hir-node.h"
! #include "rust-hir-path.h"
! #include "rust-hir-map.h"
! #include "rust-hir-pattern.h"
! #include "rust-mapping-common.h"
! #include "rust-system.h"
! #include "rust-immutable-name-resolution-context.h"
! #include "rust-tyty.h"
  
  namespace Rust {
! namespace HIR {
  
! static std::set<HirId> already_assigned_variables = {};
! 
! ReadonlyChecker::ReadonlyChecker ()
!   : resolver (*Resolver::Resolver::get ()),
!     mappings (Analysis::Mappings::get ()),
!     context (*Resolver::TypeCheckContext::get ())
! {}
  
  void
! ReadonlyChecker::go (Crate &crate)
  {
!   for (auto &item : crate.get_items ())
!     item->accept_vis (*this);
! }
! 
! void
! ReadonlyChecker::visit (AssignmentExpr &expr)
! {
!   Expr &lhs = expr.get_lhs ();
!   mutable_context.enter (expr.get_mappings ().get_hirid ());
!   lhs.accept_vis (*this);
!   mutable_context.exit ();
! }
! 
! void
! ReadonlyChecker::visit (PathInExpression &expr)
! {
!   if (!mutable_context.is_in_context ())
!     return;
! 
!   NodeId ast_node_id = expr.get_mappings ().get_nodeid ();
!   NodeId def_id;
! 
!   auto &nr_ctx
!     = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
!   if (auto id = nr_ctx.lookup (ast_node_id))
!     def_id = *id;
!   else
!     return;
! 
!   auto hir_id = mappings.lookup_node_to_hir (def_id);
!   if (!hir_id)
!     return;
! 
!   // Check if the local variable is mutable.
!   auto maybe_pattern = mappings.lookup_hir_pattern (*hir_id);
!   if (maybe_pattern
!       && maybe_pattern.value ()->get_pattern_type ()
! 	   == HIR::Pattern::PatternType::IDENTIFIER)
!     check_variable (static_cast<IdentifierPattern *> (maybe_pattern.value ()),
! 		    expr.get_locus ());
! 
!   // Check if the static item is mutable.
!   auto maybe_item = mappings.lookup_hir_item (*hir_id);
!   if (maybe_item
!       && maybe_item.value ()->get_item_kind () == HIR::Item::ItemKind::Static)
      {
!       auto static_item = static_cast<HIR::StaticItem *> (*maybe_item);
!       if (!static_item->is_mut ())
! 	rust_error_at (expr.get_locus (),
! 		       "assignment of read-only location '%s'",
! 		       static_item->get_identifier ().as_string ().c_str ());
      }
! 
!   // Check if the constant item is mutable.
!   if (maybe_item
!       && maybe_item.value ()->get_item_kind () == HIR::Item::ItemKind::Constant)
      {
!       auto const_item = static_cast<HIR::ConstantItem *> (*maybe_item);
!       rust_error_at (expr.get_locus (), "assignment of read-only location '%s'",
! 		     const_item->get_identifier ().as_string ().c_str ());
      }
  }
  
! void
! ReadonlyChecker::check_variable (IdentifierPattern *pattern,
! 				 location_t assigned_loc)
  {
!   if (!mutable_context.is_in_context ())
!     return;
! 
!   TyTy::BaseType *type;
!   if (context.lookup_type (pattern->get_mappings ().get_hirid (), &type)
!       && is_mutable_type (type))
!     return;
!   if (pattern->is_mut ())
!     return;
! 
!   auto hir_id = pattern->get_mappings ().get_hirid ();
!   if (already_assigned_variables.count (hir_id) > 0)
!     rust_error_at (assigned_loc, "assignment of read-only variable '%s'",
! 		   pattern->as_string ().c_str ());
!   already_assigned_variables.insert (hir_id);
  }
  
! void
! ReadonlyChecker::collect_assignment_identifier (IdentifierPattern &pattern,
! 						bool has_init_expr)
  {
!   if (has_init_expr)
      {
!       HirId pattern_id = pattern.get_mappings ().get_hirid ();
!       already_assigned_variables.insert (pattern_id);
      }
  }
  
! void
! ReadonlyChecker::collect_assignment_tuple (TuplePattern &tuple_pattern,
! 					   bool has_init_expr)
  {
!   switch (tuple_pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::NO_REST:
!       {
! 	auto &items_no_rest = static_cast<HIR::TuplePatternItemsNoRest &> (
! 	  tuple_pattern.get_items ());
! 	for (auto &sub : items_no_rest.get_patterns ())
! 	  {
! 	    collect_assignment (*sub, has_init_expr);
! 	  }
!       }
!       break;
!     case HIR::TuplePatternItems::ItemType::HAS_REST:
!       {
! 	auto &items_has_rest = static_cast<HIR::TuplePatternItemsHasRest &> (
! 	  tuple_pattern.get_items ());
! 	for (auto &sub : items_has_rest.get_lower_patterns ())
! 	  collect_assignment (*sub, has_init_expr);
! 	for (auto &sub : items_has_rest.get_upper_patterns ())
! 	  collect_assignment (*sub, has_init_expr);
!       }
!       break;
!     default:
        break;
+     }
+ }
  
+ void
+ ReadonlyChecker::collect_assignment (Pattern &pattern, bool has_init_expr)
+ {
+   switch (pattern.get_pattern_type ())
+     {
+     case HIR::Pattern::PatternType::IDENTIFIER:
+       {
+ 	collect_assignment_identifier (static_cast<IdentifierPattern &> (
+ 					 pattern),
+ 				       has_init_expr);
+       }
+       break;
+     case HIR::Pattern::PatternType::TUPLE:
+       {
+ 	auto &tuple_pattern = static_cast<HIR::TuplePattern &> (pattern);
+ 	collect_assignment_tuple (tuple_pattern, has_init_expr);
+       }
+       break;
      default:
        break;
      }
  }
  
! void
! ReadonlyChecker::visit (LetStmt &stmt)
  {
!   HIR::Pattern &pattern = stmt.get_pattern ();
!   collect_assignment (pattern, stmt.has_init_expr ());
  }
  
  void
! ReadonlyChecker::visit (FieldAccessExpr &expr)
  {
!   if (mutable_context.is_in_context ())
      {
!       expr.get_receiver_expr ().accept_vis (*this);
!     }
! }
  
! void
! ReadonlyChecker::visit (TupleIndexExpr &expr)
! {
!   if (mutable_context.is_in_context ())
!     {
!       expr.get_tuple_expr ().accept_vis (*this);
      }
+ }
  
! void
! ReadonlyChecker::visit (ArrayIndexExpr &expr)
! {
!   if (mutable_context.is_in_context ())
      {
!       expr.get_array_expr ().accept_vis (*this);
      }
+ }
  
! void
! ReadonlyChecker::visit (TupleExpr &expr)
! {
!   if (mutable_context.is_in_context ())
      {
!       // TODO: Add check for tuple expression
      }
  }
  
! void
! ReadonlyChecker::visit (LiteralExpr &expr)
! {
!   if (mutable_context.is_in_context ())
!     {
!       rust_error_at (expr.get_locus (), "assignment of read-only location");
!     }
! }
! 
! void
! ReadonlyChecker::visit (DereferenceExpr &expr)
! {
!   if (!mutable_context.is_in_context ())
!     return;
!   TyTy::BaseType *to_deref_type;
!   auto to_deref = expr.get_expr ().get_mappings ().get_hirid ();
!   if (!context.lookup_type (to_deref, &to_deref_type))
!     return;
!   if (!is_mutable_type (to_deref_type))
!     rust_error_at (expr.get_locus (), "assignment of read-only location");
! }
! 
! bool
! ReadonlyChecker::is_mutable_type (TyTy::BaseType *type)
! {
!   if (type->get_kind () == TyTy::TypeKind::REF)
!     return static_cast<TyTy::ReferenceType *> (type)->is_mutable ();
!   if (type->get_kind () == TyTy::TypeKind::POINTER)
!     return static_cast<TyTy::PointerType *> (type)->is_mutable ();
!   return false;
! }
! } // namespace HIR
  } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check.h gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check.h	Sun Nov  2 22:32:23 2025
***************
*** 1,4 ****
! // Copyright (C) 2021-2025 Free Software Foundation, Inc.
  
  // This file is part of GCC.
  
--- 1,4 ----
! // Copyright (C) 2025 Free Software Foundation, Inc.
  
  // This file is part of GCC.
  
***************
*** 16,36 ****
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
  
! #ifndef RUST_READONLY_CHECK
! #define RUST_READONLY_CHECK
! 
! #include "rust-compile-context.h"
  
  namespace Rust {
! namespace Analysis {
! 
! class ReadonlyCheck
  {
  public:
!   static void Lint (Compile::Context &ctx);
! };
  
! } // namespace Analysis
! } // namespace Rust
  
! #endif // RUST_READONLY_CHECK
--- 16,69 ----
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
  
! #include "rust-hir-visitor.h"
! #include "rust-name-resolver.h"
! #include "rust-stacked-contexts.h"
! #include "rust-hir-type-check.h"
  
  namespace Rust {
! namespace HIR {
! class ReadonlyChecker : public DefaultHIRVisitor
  {
  public:
!   ReadonlyChecker ();
  
!   void go (HIR::Crate &crate);
  
! private:
!   enum class lvalue_use
!   {
!     assign,
!     increment,
!     decrement,
!   };
! 
!   Resolver::Resolver &resolver;
!   Analysis::Mappings &mappings;
!   Resolver::TypeCheckContext &context;
!   StackedContexts<HirId> mutable_context;
! 
!   using DefaultHIRVisitor::visit;
! 
!   virtual void visit (AssignmentExpr &expr) override;
!   virtual void visit (PathInExpression &expr) override;
!   virtual void visit (FieldAccessExpr &expr) override;
!   virtual void visit (ArrayIndexExpr &expr) override;
!   virtual void visit (TupleExpr &expr) override;
!   virtual void visit (TupleIndexExpr &expr) override;
!   virtual void visit (LetStmt &stmt) override;
!   virtual void visit (LiteralExpr &expr) override;
!   virtual void visit (DereferenceExpr &expr) override;
! 
!   void collect_assignment (Pattern &pattern, bool has_init_expr);
!   void collect_assignment_identifier (IdentifierPattern &pattern,
! 				      bool has_init_expr);
!   void collect_assignment_tuple (TuplePattern &pattern, bool has_init_expr);
! 
!   void check_variable (IdentifierPattern *pattern, location_t assigned_loc);
! 
!   bool is_mutable_type (TyTy::BaseType *type);
! };
! 
! } // namespace HIR
! } // namespace Rust
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check2.cc gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check2.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check2.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check2.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,253 ****
- // Copyright (C) 2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-readonly-check2.h"
- #include "rust-hir-expr.h"
- #include "rust-hir-node.h"
- #include "rust-hir-path.h"
- #include "rust-hir-map.h"
- #include "rust-hir-pattern.h"
- #include "rust-mapping-common.h"
- #include "rust-system.h"
- #include "rust-immutable-name-resolution-context.h"
- #include "rust-tyty.h"
- 
- namespace Rust {
- namespace HIR {
- 
- static std::set<HirId> already_assigned_variables = {};
- 
- ReadonlyChecker::ReadonlyChecker ()
-   : resolver (*Resolver::Resolver::get ()),
-     mappings (Analysis::Mappings::get ()),
-     context (*Resolver::TypeCheckContext::get ())
- {}
- 
- void
- ReadonlyChecker::go (Crate &crate)
- {
-   for (auto &item : crate.get_items ())
-     item->accept_vis (*this);
- }
- 
- void
- ReadonlyChecker::visit (AssignmentExpr &expr)
- {
-   Expr &lhs = expr.get_lhs ();
-   mutable_context.enter (expr.get_mappings ().get_hirid ());
-   lhs.accept_vis (*this);
-   mutable_context.exit ();
- }
- 
- void
- ReadonlyChecker::visit (PathInExpression &expr)
- {
-   if (!mutable_context.is_in_context ())
-     return;
- 
-   NodeId ast_node_id = expr.get_mappings ().get_nodeid ();
-   NodeId def_id;
- 
-   auto &nr_ctx
-     = Resolver2_0::ImmutableNameResolutionContext::get ().resolver ();
-   if (auto id = nr_ctx.lookup (ast_node_id))
-     def_id = *id;
-   else
-     return;
- 
-   auto hir_id = mappings.lookup_node_to_hir (def_id);
-   if (!hir_id)
-     return;
- 
-   // Check if the local variable is mutable.
-   auto maybe_pattern = mappings.lookup_hir_pattern (*hir_id);
-   if (maybe_pattern
-       && maybe_pattern.value ()->get_pattern_type ()
- 	   == HIR::Pattern::PatternType::IDENTIFIER)
-     check_variable (static_cast<IdentifierPattern *> (maybe_pattern.value ()),
- 		    expr.get_locus ());
- 
-   // Check if the static item is mutable.
-   auto maybe_item = mappings.lookup_hir_item (*hir_id);
-   if (maybe_item
-       && maybe_item.value ()->get_item_kind () == HIR::Item::ItemKind::Static)
-     {
-       auto static_item = static_cast<HIR::StaticItem *> (*maybe_item);
-       if (!static_item->is_mut ())
- 	rust_error_at (expr.get_locus (),
- 		       "assignment of read-only location '%s'",
- 		       static_item->get_identifier ().as_string ().c_str ());
-     }
- 
-   // Check if the constant item is mutable.
-   if (maybe_item
-       && maybe_item.value ()->get_item_kind () == HIR::Item::ItemKind::Constant)
-     {
-       auto const_item = static_cast<HIR::ConstantItem *> (*maybe_item);
-       rust_error_at (expr.get_locus (), "assignment of read-only location '%s'",
- 		     const_item->get_identifier ().as_string ().c_str ());
-     }
- }
- 
- void
- ReadonlyChecker::check_variable (IdentifierPattern *pattern,
- 				 location_t assigned_loc)
- {
-   if (!mutable_context.is_in_context ())
-     return;
-   if (pattern->is_mut ())
-     return;
- 
-   auto hir_id = pattern->get_mappings ().get_hirid ();
-   if (already_assigned_variables.count (hir_id) > 0)
-     rust_error_at (assigned_loc, "assignment of read-only variable '%s'",
- 		   pattern->as_string ().c_str ());
-   already_assigned_variables.insert (hir_id);
- }
- 
- void
- ReadonlyChecker::collect_assignment_identifier (IdentifierPattern &pattern,
- 						bool has_init_expr)
- {
-   if (has_init_expr)
-     {
-       HirId pattern_id = pattern.get_mappings ().get_hirid ();
-       already_assigned_variables.insert (pattern_id);
-     }
- }
- 
- void
- ReadonlyChecker::collect_assignment_tuple (TuplePattern &tuple_pattern,
- 					   bool has_init_expr)
- {
-   switch (tuple_pattern.get_items ().get_item_type ())
-     {
-     case HIR::TuplePatternItems::ItemType::MULTIPLE:
-       {
- 	auto &items = static_cast<HIR::TuplePatternItemsMultiple &> (
- 	  tuple_pattern.get_items ());
- 	for (auto &sub : items.get_patterns ())
- 	  {
- 	    collect_assignment (*sub, has_init_expr);
- 	  }
-       }
-       break;
-     default:
-       break;
-     }
- }
- 
- void
- ReadonlyChecker::collect_assignment (Pattern &pattern, bool has_init_expr)
- {
-   switch (pattern.get_pattern_type ())
-     {
-     case HIR::Pattern::PatternType::IDENTIFIER:
-       {
- 	collect_assignment_identifier (static_cast<IdentifierPattern &> (
- 					 pattern),
- 				       has_init_expr);
-       }
-       break;
-     case HIR::Pattern::PatternType::TUPLE:
-       {
- 	auto &tuple_pattern = static_cast<HIR::TuplePattern &> (pattern);
- 	collect_assignment_tuple (tuple_pattern, has_init_expr);
-       }
-       break;
-     default:
-       break;
-     }
- }
- 
- void
- ReadonlyChecker::visit (LetStmt &stmt)
- {
-   HIR::Pattern &pattern = stmt.get_pattern ();
-   collect_assignment (pattern, stmt.has_init_expr ());
- }
- 
- void
- ReadonlyChecker::visit (FieldAccessExpr &expr)
- {
-   if (mutable_context.is_in_context ())
-     {
-       expr.get_receiver_expr ().accept_vis (*this);
-     }
- }
- 
- void
- ReadonlyChecker::visit (TupleIndexExpr &expr)
- {
-   if (mutable_context.is_in_context ())
-     {
-       expr.get_tuple_expr ().accept_vis (*this);
-     }
- }
- 
- void
- ReadonlyChecker::visit (ArrayIndexExpr &expr)
- {
-   if (mutable_context.is_in_context ())
-     {
-       expr.get_array_expr ().accept_vis (*this);
-     }
- }
- 
- void
- ReadonlyChecker::visit (TupleExpr &expr)
- {
-   if (mutable_context.is_in_context ())
-     {
-       // TODO: Add check for tuple expression
-     }
- }
- 
- void
- ReadonlyChecker::visit (LiteralExpr &expr)
- {
-   if (mutable_context.is_in_context ())
-     {
-       rust_error_at (expr.get_locus (), "assignment of read-only location");
-     }
- }
- 
- void
- ReadonlyChecker::visit (DereferenceExpr &expr)
- {
-   if (!mutable_context.is_in_context ())
-     return;
-   TyTy::BaseType *to_deref_type;
-   auto to_deref = expr.get_expr ().get_mappings ().get_hirid ();
-   if (!context.lookup_type (to_deref, &to_deref_type))
-     return;
-   if (to_deref_type->get_kind () == TyTy::TypeKind::REF)
-     {
-       auto ref_type = static_cast<TyTy::ReferenceType *> (to_deref_type);
-       if (!ref_type->is_mutable ())
- 	rust_error_at (expr.get_locus (), "assignment of read-only location");
-     }
-   if (to_deref_type->get_kind () == TyTy::TypeKind::POINTER)
-     {
-       auto ptr_type = static_cast<TyTy::PointerType *> (to_deref_type);
-       if (!ptr_type->is_mutable ())
- 	rust_error_at (expr.get_locus (), "assignment of read-only location");
-     }
- }
- } // namespace HIR
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check2.h gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check2.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-readonly-check2.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-readonly-check2.h	Thu Jan  1 00:00:00 1970
***************
*** 1,67 ****
- // Copyright (C) 2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-hir-visitor.h"
- #include "rust-name-resolver.h"
- #include "rust-stacked-contexts.h"
- #include "rust-hir-type-check.h"
- 
- namespace Rust {
- namespace HIR {
- class ReadonlyChecker : public DefaultHIRVisitor
- {
- public:
-   ReadonlyChecker ();
- 
-   void go (HIR::Crate &crate);
- 
- private:
-   enum class lvalue_use
-   {
-     assign,
-     increment,
-     decrement,
-   };
- 
-   Resolver::Resolver &resolver;
-   Analysis::Mappings &mappings;
-   Resolver::TypeCheckContext &context;
-   StackedContexts<HirId> mutable_context;
- 
-   using DefaultHIRVisitor::visit;
- 
-   virtual void visit (AssignmentExpr &expr) override;
-   virtual void visit (PathInExpression &expr) override;
-   virtual void visit (FieldAccessExpr &expr) override;
-   virtual void visit (ArrayIndexExpr &expr) override;
-   virtual void visit (TupleExpr &expr) override;
-   virtual void visit (TupleIndexExpr &expr) override;
-   virtual void visit (LetStmt &stmt) override;
-   virtual void visit (LiteralExpr &expr) override;
-   virtual void visit (DereferenceExpr &expr) override;
- 
-   void collect_assignment (Pattern &pattern, bool has_init_expr);
-   void collect_assignment_identifier (IdentifierPattern &pattern,
- 				      bool has_init_expr);
-   void collect_assignment_tuple (TuplePattern &pattern, bool has_init_expr);
- 
-   void check_variable (IdentifierPattern *pattern, location_t assigned_loc);
- };
- 
- } // namespace HIR
- } // namespace Rust
\ No newline at end of file
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-unsafe-checker.cc gcc-16-20251102/gcc/rust/checks/errors/rust-unsafe-checker.cc
*** gcc-16-20251026/gcc/rust/checks/errors/rust-unsafe-checker.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-unsafe-checker.cc	Sun Nov  2 22:32:23 2025
*************** UnsafeChecker::visit (StructPattern &)
*** 926,936 ****
  {}
  
  void
! UnsafeChecker::visit (TupleStructItemsNoRange &)
  {}
  
  void
! UnsafeChecker::visit (TupleStructItemsRange &)
  {}
  
  void
--- 926,936 ----
  {}
  
  void
! UnsafeChecker::visit (TupleStructItemsNoRest &)
  {}
  
  void
! UnsafeChecker::visit (TupleStructItemsHasRest &)
  {}
  
  void
*************** UnsafeChecker::visit (TupleStructPattern
*** 938,948 ****
  {}
  
  void
! UnsafeChecker::visit (TuplePatternItemsMultiple &)
  {}
  
  void
! UnsafeChecker::visit (TuplePatternItemsRanged &)
  {}
  
  void
--- 938,948 ----
  {}
  
  void
! UnsafeChecker::visit (TuplePatternItemsNoRest &)
  {}
  
  void
! UnsafeChecker::visit (TuplePatternItemsHasRest &)
  {}
  
  void
*************** UnsafeChecker::visit (TuplePattern &)
*** 950,955 ****
--- 950,963 ----
  {}
  
  void
+ UnsafeChecker::visit (SlicePatternItemsNoRest &)
+ {}
+ 
+ void
+ UnsafeChecker::visit (SlicePatternItemsHasRest &)
+ {}
+ 
+ void
  UnsafeChecker::visit (SlicePattern &)
  {}
  
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/errors/rust-unsafe-checker.h gcc-16-20251102/gcc/rust/checks/errors/rust-unsafe-checker.h
*** gcc-16-20251026/gcc/rust/checks/errors/rust-unsafe-checker.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/errors/rust-unsafe-checker.h	Sun Nov  2 22:32:23 2025
*************** private:
*** 161,172 ****
    virtual void visit (StructPatternFieldIdentPat &field) override;
    virtual void visit (StructPatternFieldIdent &field) override;
    virtual void visit (StructPattern &pattern) override;
!   virtual void visit (TupleStructItemsNoRange &tuple_items) override;
!   virtual void visit (TupleStructItemsRange &tuple_items) override;
    virtual void visit (TupleStructPattern &pattern) override;
!   virtual void visit (TuplePatternItemsMultiple &tuple_items) override;
!   virtual void visit (TuplePatternItemsRanged &tuple_items) override;
    virtual void visit (TuplePattern &pattern) override;
    virtual void visit (SlicePattern &pattern) override;
    virtual void visit (AltPattern &pattern) override;
    virtual void visit (EmptyStmt &stmt) override;
--- 161,174 ----
    virtual void visit (StructPatternFieldIdentPat &field) override;
    virtual void visit (StructPatternFieldIdent &field) override;
    virtual void visit (StructPattern &pattern) override;
!   virtual void visit (TupleStructItemsNoRest &tuple_items) override;
!   virtual void visit (TupleStructItemsHasRest &tuple_items) override;
    virtual void visit (TupleStructPattern &pattern) override;
!   virtual void visit (TuplePatternItemsNoRest &tuple_items) override;
!   virtual void visit (TuplePatternItemsHasRest &tuple_items) override;
    virtual void visit (TuplePattern &pattern) override;
+   virtual void visit (SlicePatternItemsNoRest &items) override;
+   virtual void visit (SlicePatternItemsHasRest &items) override;
    virtual void visit (SlicePattern &pattern) override;
    virtual void visit (AltPattern &pattern) override;
    virtual void visit (EmptyStmt &stmt) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/checks/lints/rust-lint-marklive-base.h gcc-16-20251102/gcc/rust/checks/lints/rust-lint-marklive-base.h
*** gcc-16-20251026/gcc/rust/checks/lints/rust-lint-marklive-base.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/checks/lints/rust-lint-marklive-base.h	Sun Nov  2 22:32:23 2025
***************
*** 19,27 ****
  #ifndef RUST_HIR_LIVENESS_BASE
  #define RUST_HIR_LIVENESS_BASE
  
- #include "rust-diagnostics.h"
- #include "rust-lint-marklive.h"
- #include "rust-lint-marklive-base.h"
  #include "rust-hir-visitor.h"
  #include "rust-hir-map.h"
  
--- 19,24 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-cfg-strip.cc gcc-16-20251102/gcc/rust/expand/rust-cfg-strip.cc
*** gcc-16-20251026/gcc/rust/expand/rust-cfg-strip.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-cfg-strip.cc	Sun Nov  2 22:32:23 2025
***************
*** 22,27 ****
--- 22,28 ----
  #include "rust-path.h"
  #include "rust-session-manager.h"
  #include "rust-attribute-values.h"
+ #include "rust-macro-expand.h"
  
  namespace Rust {
  
*************** namespace Rust {
*** 30,36 ****
   * should be stripped. Note that attributes must be expanded before calling.
   */
  bool
! fails_cfg (const AST::AttrVec &attrs)
  {
    auto &session = Session::get_instance ();
  
--- 31,37 ----
   * should be stripped. Note that attributes must be expanded before calling.
   */
  bool
! CfgStrip::fails_cfg (const AST::AttrVec &attrs) const
  {
    auto &session = Session::get_instance ();
  
*************** fails_cfg (const AST::AttrVec &attrs)
*** 39,44 ****
--- 40,48 ----
        if (attr.get_path () == Values::Attributes::CFG
  	  && !attr.check_cfg_predicate (session))
  	return true;
+       else if (!expansion_cfg.should_test
+ 	       && attr.get_path () == Values::Attributes::TEST)
+ 	return true;
      }
    return false;
  }
*************** fails_cfg (const AST::AttrVec &attrs)
*** 48,54 ****
   * should be stripped. Will expand attributes as well.
   */
  bool
! fails_cfg_with_expand (AST::AttrVec &attrs)
  {
    auto &session = Session::get_instance ();
  
--- 52,58 ----
   * should be stripped. Will expand attributes as well.
   */
  bool
! CfgStrip::fails_cfg_with_expand (AST::AttrVec &attrs) const
  {
    auto &session = Session::get_instance ();
  
*************** fails_cfg_with_expand (AST::AttrVec &att
*** 85,90 ****
--- 89,97 ----
  			  attr.as_string ().c_str ());
  	    }
  	}
+       else if (!expansion_cfg.should_test
+ 	       && attr.get_path () == Values::Attributes::TEST)
+ 	return true;
      }
    return false;
  }
*************** CfgStrip::visit (AST::StaticItem &static
*** 2062,2099 ****
  }
  
  void
- CfgStrip::visit (AST::TraitItemConst &item)
- {
-   // initial test based on outer attrs
-   expand_cfg_attrs (item.get_outer_attrs ());
-   if (fails_cfg_with_expand (item.get_outer_attrs ()))
-     {
-       item.mark_for_strip ();
-       return;
-     }
- 
-   AST::DefaultASTVisitor::visit (item);
- 
-   // strip any sub-types
-   auto &type = item.get_type ();
- 
-   if (type.is_marked_for_strip ())
-     rust_error_at (type.get_locus (), "cannot strip type in this position");
- 
-   /* strip any internal sub-expressions - expression itself isn't
-    * allowed to have external attributes in this position so can't be
-    * stripped */
-   if (item.has_expression ())
-     {
-       auto &expr = item.get_expr ();
-       if (expr.is_marked_for_strip ())
- 	rust_error_at (expr.get_locus (),
- 		       "cannot strip expression in this position - outer "
- 		       "attributes not allowed");
-     }
- }
- 
- void
  CfgStrip::visit (AST::TraitItemType &item)
  {
    // initial test based on outer attrs
--- 2069,2074 ----
*************** CfgStrip::visit (AST::StructPattern &pat
*** 2374,2380 ****
    maybe_strip_pointer_allow_strip (elems.get_struct_pattern_fields ());
  
    // assuming you can strip the ".." part
!   if (elems.has_etc ())
      {
        expand_cfg_attrs (elems.get_etc_outer_attrs ());
        if (fails_cfg_with_expand (elems.get_etc_outer_attrs ()))
--- 2349,2355 ----
    maybe_strip_pointer_allow_strip (elems.get_struct_pattern_fields ());
  
    // assuming you can strip the ".." part
!   if (elems.has_rest ())
      {
        expand_cfg_attrs (elems.get_etc_outer_attrs ());
        if (fails_cfg_with_expand (elems.get_etc_outer_attrs ()))
*************** CfgStrip::visit (AST::StructPattern &pat
*** 2383,2389 ****
  }
  
  void
! CfgStrip::visit (AST::TupleStructItemsNoRange &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
    // can't strip individual patterns, only sub-patterns
--- 2358,2364 ----
  }
  
  void
! CfgStrip::visit (AST::TupleStructItemsNoRest &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
    // can't strip individual patterns, only sub-patterns
*************** CfgStrip::visit (AST::TupleStructItemsNo
*** 2396,2402 ****
      }
  }
  void
! CfgStrip::visit (AST::TupleStructItemsRange &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
    // can't strip individual patterns, only sub-patterns
--- 2371,2377 ----
      }
  }
  void
! CfgStrip::visit (AST::TupleStructItemsHasRest &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
    // can't strip individual patterns, only sub-patterns
*************** CfgStrip::visit (AST::TupleStructPattern
*** 2429,2435 ****
  }
  
  void
! CfgStrip::visit (AST::TuplePatternItemsMultiple &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
  
--- 2404,2410 ----
  }
  
  void
! CfgStrip::visit (AST::TuplePatternItemsNoRest &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
  
*************** CfgStrip::visit (AST::TuplePatternItemsM
*** 2444,2450 ****
  }
  
  void
! CfgStrip::visit (AST::TuplePatternItemsRanged &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
  
--- 2419,2425 ----
  }
  
  void
! CfgStrip::visit (AST::TuplePatternItemsHasRest &tuple_items)
  {
    AST::DefaultASTVisitor::visit (tuple_items);
  
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-cfg-strip.h gcc-16-20251102/gcc/rust/expand/rust-cfg-strip.h
*** gcc-16-20251026/gcc/rust/expand/rust-cfg-strip.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-cfg-strip.h	Sun Nov  2 22:32:23 2025
***************
*** 23,36 ****
  #include "rust-item.h"
  
  namespace Rust {
  // Visitor used to maybe_strip attributes.
  class CfgStrip : public AST::DefaultASTVisitor
  {
  private:
  public:
    using DefaultASTVisitor::visit;
  
!   CfgStrip () {}
  
    /* Run the AttrVisitor on an entire crate */
    void go (AST::Crate &crate);
--- 23,45 ----
  #include "rust-item.h"
  
  namespace Rust {
+ 
+ // forward declare
+ struct ExpansionCfg;
+ 
  // Visitor used to maybe_strip attributes.
  class CfgStrip : public AST::DefaultASTVisitor
  {
  private:
+   bool fails_cfg (const AST::AttrVec &attrs) const;
+ 
+   bool fails_cfg_with_expand (AST::AttrVec &attrs) const;
+ 
  public:
    using DefaultASTVisitor::visit;
  
!   CfgStrip (const ExpansionCfg &expansion_cfg) : expansion_cfg (expansion_cfg)
!   {}
  
    /* Run the AttrVisitor on an entire crate */
    void go (AST::Crate &crate);
*************** public:
*** 147,153 ****
    void visit (AST::Union &union_item) override;
    void visit (AST::ConstantItem &const_item) override;
    void visit (AST::StaticItem &static_item) override;
-   void visit (AST::TraitItemConst &item) override;
    void visit (AST::TraitItemType &item) override;
    void visit (AST::Trait &trait) override;
    void visit (AST::InherentImpl &impl) override;
--- 156,161 ----
*************** public:
*** 166,176 ****
    void visit (AST::StructPatternFieldIdentPat &field) override;
    void visit (AST::StructPatternFieldIdent &field) override;
    void visit (AST::StructPattern &pattern) override;
!   void visit (AST::TupleStructItemsNoRange &tuple_items) override;
!   void visit (AST::TupleStructItemsRange &tuple_items) override;
    void visit (AST::TupleStructPattern &pattern) override;
!   void visit (AST::TuplePatternItemsMultiple &tuple_items) override;
!   void visit (AST::TuplePatternItemsRanged &tuple_items) override;
    void visit (AST::GroupedPattern &pattern) override;
    void visit (AST::SlicePatternItemsNoRest &items) override;
    void visit (AST::SlicePatternItemsHasRest &items) override;
--- 174,184 ----
    void visit (AST::StructPatternFieldIdentPat &field) override;
    void visit (AST::StructPatternFieldIdent &field) override;
    void visit (AST::StructPattern &pattern) override;
!   void visit (AST::TupleStructItemsNoRest &tuple_items) override;
!   void visit (AST::TupleStructItemsHasRest &tuple_items) override;
    void visit (AST::TupleStructPattern &pattern) override;
!   void visit (AST::TuplePatternItemsNoRest &tuple_items) override;
!   void visit (AST::TuplePatternItemsHasRest &tuple_items) override;
    void visit (AST::GroupedPattern &pattern) override;
    void visit (AST::SlicePatternItemsNoRest &items) override;
    void visit (AST::SlicePatternItemsHasRest &items) override;
*************** public:
*** 194,199 ****
--- 202,210 ----
    {
      DefaultASTVisitor::visit (item);
    }
+ 
+ private:
+   const ExpansionCfg &expansion_cfg;
  };
  } // namespace Rust
  
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive-clone.cc gcc-16-20251102/gcc/rust/expand/rust-derive-clone.cc
*** gcc-16-20251026/gcc/rust/expand/rust-derive-clone.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive-clone.cc	Sun Nov  2 22:32:23 2025
*************** DeriveClone::clone_fn (std::unique_ptr<E
*** 64,74 ****
      new BlockExpr ({}, std::move (clone_expr), {}, {}, tl::nullopt, loc, loc));
    auto big_self_type = builder.single_type_path ("Self");
  
-   std::unique_ptr<SelfParam> self (new SelfParam (tl::nullopt,
- 						  /* is_mut */ false, loc));
- 
    std::vector<std::unique_ptr<Param>> params;
!   params.push_back (std::move (self));
  
    return std::unique_ptr<AssociatedItem> (
      new Function ({"clone"}, builder.fn_qualifiers (), /* generics */ {},
--- 64,73 ----
      new BlockExpr ({}, std::move (clone_expr), {}, {}, tl::nullopt, loc, loc));
    auto big_self_type = builder.single_type_path ("Self");
  
    std::vector<std::unique_ptr<Param>> params;
! 
!   params.emplace_back (new SelfParam (tl::nullopt,
! 				      /* is_mut */ false, loc));
  
    return std::unique_ptr<AssociatedItem> (
      new Function ({"clone"}, builder.fn_qualifiers (), /* generics */ {},
*************** DeriveClone::clone_enum_tuple (PathInExp
*** 211,217 ****
      }
  
    auto pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (patterns)));
  
    auto pattern = std::unique_ptr<Pattern> (new ReferencePattern (
      std::unique_ptr<Pattern> (new TupleStructPattern (
--- 210,216 ----
      }
  
    auto pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (patterns)));
  
    auto pattern = std::unique_ptr<Pattern> (new ReferencePattern (
      std::unique_ptr<Pattern> (new TupleStructPattern (
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive-cmp-common.cc gcc-16-20251102/gcc/rust/expand/rust-derive-cmp-common.cc
*** gcc-16-20251026/gcc/rust/expand/rust-derive-cmp-common.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive-cmp-common.cc	Sun Nov  2 22:32:23 2025
*************** EnumMatchBuilder::tuple (EnumItem &varia
*** 101,109 ****
    auto other_variant_path = builder.variant_path (enum_path, variant_path);
  
    auto self_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (self_patterns)));
    auto other_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (other_patterns)));
  
    auto self_pattern = std::unique_ptr<Pattern> (
      new ReferencePattern (std::unique_ptr<Pattern> (new TupleStructPattern (
--- 101,109 ----
    auto other_variant_path = builder.variant_path (enum_path, variant_path);
  
    auto self_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (self_patterns)));
    auto other_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (other_patterns)));
  
    auto self_pattern = std::unique_ptr<Pattern> (
      new ReferencePattern (std::unique_ptr<Pattern> (new TupleStructPattern (
*************** EnumMatchBuilder::tuple (EnumItem &varia
*** 114,120 ****
        other_variant_path, std::move (other_pattern_items))),
      false, false, builder.loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsMultiple> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern
--- 114,120 ----
        other_variant_path, std::move (other_pattern_items))),
      false, false, builder.loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsNoRest> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern
*************** EnumMatchBuilder::strukt (EnumItem &vari
*** 176,182 ****
  					       std::move (other_elts))),
  			  false, false, builder.loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsMultiple> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern
--- 176,182 ----
  					       std::move (other_elts))),
  			  false, false, builder.loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsNoRest> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive-eq.cc gcc-16-20251102/gcc/rust/expand/rust-derive-eq.cc
*** gcc-16-20251026/gcc/rust/expand/rust-derive-eq.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive-eq.cc	Sun Nov  2 22:32:23 2025
*************** DeriveEq::eq_impls (
*** 128,136 ****
    auto eq_impl = builder.trait_impl (eq, std::move (eq_generics.self_type),
  				     std::move (trait_items),
  				     std::move (eq_generics.impl));
    auto steq_impl
      = builder.trait_impl (steq, std::move (steq_generics.self_type),
! 			  std::move (trait_items),
  			  std::move (steq_generics.impl));
  
    return vec (std::move (eq_impl), std::move (steq_impl));
--- 128,140 ----
    auto eq_impl = builder.trait_impl (eq, std::move (eq_generics.self_type),
  				     std::move (trait_items),
  				     std::move (eq_generics.impl));
+ 
+   // StructuralEq is a marker trait
+   decltype (trait_items) steq_trait_items = {};
+ 
    auto steq_impl
      = builder.trait_impl (steq, std::move (steq_generics.self_type),
! 			  std::move (steq_trait_items),
  			  std::move (steq_generics.impl));
  
    return vec (std::move (eq_impl), std::move (steq_impl));
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive-hash.cc gcc-16-20251102/gcc/rust/expand/rust-derive-hash.cc
*** gcc-16-20251026/gcc/rust/expand/rust-derive-hash.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive-hash.cc	Sun Nov  2 22:32:23 2025
*************** DeriveHash::match_enum_tuple (PathInExpr
*** 151,157 ****
      }
  
    auto patterns_elts = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (self_patterns)));
    auto pattern = std::unique_ptr<Pattern> (
      new ReferencePattern (std::unique_ptr<Pattern> (new TupleStructPattern (
  			    variant_path, std::move (patterns_elts))),
--- 151,157 ----
      }
  
    auto patterns_elts = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (self_patterns)));
    auto pattern = std::unique_ptr<Pattern> (
      new ReferencePattern (std::unique_ptr<Pattern> (new TupleStructPattern (
  			    variant_path, std::move (patterns_elts))),
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive-ord.cc gcc-16-20251102/gcc/rust/expand/rust-derive-ord.cc
*** gcc-16-20251026/gcc/rust/expand/rust-derive-ord.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive-ord.cc	Sun Nov  2 22:32:23 2025
*************** DeriveOrd::make_equal ()
*** 120,126 ****
    if (ordering == Ordering::Partial)
      {
        auto pattern_items = std::unique_ptr<TupleStructItems> (
! 	new TupleStructItemsNoRange (vec (std::move (equal))));
  
        equal
  	= std::make_unique<TupleStructPattern> (builder.path_in_expression (
--- 120,126 ----
    if (ordering == Ordering::Partial)
      {
        auto pattern_items = std::unique_ptr<TupleStructItems> (
! 	new TupleStructItemsNoRest (vec (std::move (equal))));
  
        equal
  	= std::make_unique<TupleStructPattern> (builder.path_in_expression (
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive-partial-eq.cc gcc-16-20251102/gcc/rust/expand/rust-derive-partial-eq.cc
*** gcc-16-20251026/gcc/rust/expand/rust-derive-partial-eq.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive-partial-eq.cc	Sun Nov  2 22:32:23 2025
*************** DerivePartialEq::match_enum_identifier (
*** 146,152 ****
  	   builder.ref_pattern (
  	     std::unique_ptr<Pattern> (new PathInExpression (variant_path))));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsMultiple> (
      std::move (inner_ref_patterns));
  
    auto pattern = std::make_unique<TuplePattern> (std::move (tuple_items), loc);
--- 146,152 ----
  	   builder.ref_pattern (
  	     std::unique_ptr<Pattern> (new PathInExpression (variant_path))));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsNoRest> (
      std::move (inner_ref_patterns));
  
    auto pattern = std::make_unique<TuplePattern> (std::move (tuple_items), loc);
*************** DerivePartialEq::match_enum_tuple (PathI
*** 186,194 ****
      }
  
    auto self_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (self_patterns)));
    auto other_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRange (std::move (other_patterns)));
  
    auto self_pattern = std::unique_ptr<Pattern> (
      new ReferencePattern (std::unique_ptr<Pattern> (new TupleStructPattern (
--- 186,194 ----
      }
  
    auto self_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (self_patterns)));
    auto other_pattern_items = std::unique_ptr<TupleStructItems> (
!     new TupleStructItemsNoRest (std::move (other_patterns)));
  
    auto self_pattern = std::unique_ptr<Pattern> (
      new ReferencePattern (std::unique_ptr<Pattern> (new TupleStructPattern (
*************** DerivePartialEq::match_enum_tuple (PathI
*** 199,205 ****
  			    variant_path, std::move (other_pattern_items))),
  			  false, false, loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsMultiple> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern = std::make_unique<TuplePattern> (std::move (tuple_items), loc);
--- 199,205 ----
  			    variant_path, std::move (other_pattern_items))),
  			  false, false, loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsNoRest> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern = std::make_unique<TuplePattern> (std::move (tuple_items), loc);
*************** DerivePartialEq::match_enum_struct (Path
*** 254,260 ****
  			    variant_path, loc, std::move (other_elts))),
  			  false, false, loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsMultiple> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern = std::make_unique<TuplePattern> (std::move (tuple_items), loc);
--- 254,260 ----
  			    variant_path, loc, std::move (other_elts))),
  			  false, false, loc));
  
!   auto tuple_items = std::make_unique<TuplePatternItemsNoRest> (
      vec (std::move (self_pattern), std::move (other_pattern)));
  
    auto pattern = std::make_unique<TuplePattern> (std::move (tuple_items), loc);
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-derive.h gcc-16-20251102/gcc/rust/expand/rust-derive.h
*** gcc-16-20251026/gcc/rust/expand/rust-derive.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-derive.h	Sun Nov  2 22:32:23 2025
*************** private:
*** 192,198 ****
    virtual void visit (EnumItemDiscriminant &item) override final{};
    virtual void visit (ConstantItem &const_item) override final{};
    virtual void visit (StaticItem &static_item) override final{};
-   virtual void visit (TraitItemConst &item) override final{};
    virtual void visit (TraitItemType &item) override final{};
    virtual void visit (Trait &trait) override final{};
    virtual void visit (InherentImpl &impl) override final{};
--- 192,197 ----
*************** private:
*** 224,234 ****
    virtual void visit (StructPatternFieldIdentPat &field) override final{};
    virtual void visit (StructPatternFieldIdent &field) override final{};
    virtual void visit (StructPattern &pattern) override final{};
!   virtual void visit (TupleStructItemsNoRange &tuple_items) override final{};
!   virtual void visit (TupleStructItemsRange &tuple_items) override final{};
    virtual void visit (TupleStructPattern &pattern) override final{};
!   virtual void visit (TuplePatternItemsMultiple &tuple_items) override final{};
!   virtual void visit (TuplePatternItemsRanged &tuple_items) override final{};
    virtual void visit (TuplePattern &pattern) override final{};
    virtual void visit (GroupedPattern &pattern) override final{};
    virtual void visit (SlicePatternItemsNoRest &items) override final{};
--- 223,233 ----
    virtual void visit (StructPatternFieldIdentPat &field) override final{};
    virtual void visit (StructPatternFieldIdent &field) override final{};
    virtual void visit (StructPattern &pattern) override final{};
!   virtual void visit (TupleStructItemsNoRest &tuple_items) override final{};
!   virtual void visit (TupleStructItemsHasRest &tuple_items) override final{};
    virtual void visit (TupleStructPattern &pattern) override final{};
!   virtual void visit (TuplePatternItemsNoRest &tuple_items) override final{};
!   virtual void visit (TuplePatternItemsHasRest &tuple_items) override final{};
    virtual void visit (TuplePattern &pattern) override final{};
    virtual void visit (GroupedPattern &pattern) override final{};
    virtual void visit (SlicePatternItemsNoRest &items) override final{};
*************** private:
*** 262,265 ****
  } // namespace AST
  } // namespace Rust
  
! #endif // DERIVE_VISITOR_H
--- 261,264 ----
  } // namespace AST
  } // namespace Rust
  
! #endif // DERIVE_VISITOR_H
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-expand-visitor.cc gcc-16-20251102/gcc/rust/expand/rust-expand-visitor.cc
*** gcc-16-20251026/gcc/rust/expand/rust-expand-visitor.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-expand-visitor.cc	Sun Nov  2 22:32:23 2025
***************
*** 18,23 ****
--- 18,24 ----
  
  #include "rust-expand-visitor.h"
  #include "rust-ast-fragment.h"
+ #include "rust-item.h"
  #include "rust-proc-macro.h"
  #include "rust-attributes.h"
  #include "rust-ast.h"
*************** derive_item (AST::Item &item, AST::Simpl
*** 62,68 ****
  	{
  	  switch (node.get_kind ())
  	    {
! 	    case AST::SingleASTNode::ITEM:
  	      result.push_back (node.take_item ());
  	      break;
  	    default:
--- 63,69 ----
  	{
  	  switch (node.get_kind ())
  	    {
! 	    case AST::SingleASTNode::Kind::Item:
  	      result.push_back (node.take_item ());
  	      break;
  	    default:
*************** expand_item_attribute (AST::Item &item,
*** 85,91 ****
  	{
  	  switch (node.get_kind ())
  	    {
! 	    case AST::SingleASTNode::ITEM:
  	      result.push_back (node.take_item ());
  	      break;
  	    default:
--- 86,92 ----
  	{
  	  switch (node.get_kind ())
  	    {
! 	    case AST::SingleASTNode::Kind::Item:
  	      result.push_back (node.take_item ());
  	      break;
  	    default:
*************** expand_stmt_attribute (T &statement, AST
*** 114,120 ****
  	{
  	  switch (node.get_kind ())
  	    {
! 	    case AST::SingleASTNode::STMT:
  	      result.push_back (node.take_stmt ());
  	      break;
  	    default:
--- 115,121 ----
  	{
  	  switch (node.get_kind ())
  	    {
! 	    case AST::SingleASTNode::Kind::Stmt:
  	      result.push_back (node.take_stmt ());
  	      break;
  	    default:
*************** ExpandVisitor::expand_inner_stmts (AST::
*** 329,338 ****
--- 330,344 ----
  void
  ExpandVisitor::maybe_expand_expr (std::unique_ptr<AST::Expr> &expr)
  {
+   NodeId old_expect = expr->get_node_id ();
+   std::swap (macro_invoc_expect_id, old_expect);
+ 
    expander.push_context (MacroExpander::ContextType::EXPR);
    expr->accept_vis (*this);
    expander.pop_context ();
  
+   std::swap (macro_invoc_expect_id, old_expect);
+ 
    auto final_fragment = expander.take_expanded_fragment ();
    if (final_fragment.should_expand ()
        && final_fragment.is_expression_fragment ())
*************** ExpandVisitor::maybe_expand_expr (std::u
*** 342,355 ****
  void
  ExpandVisitor::maybe_expand_type (std::unique_ptr<AST::Type> &type)
  {
!   expander.push_context (MacroExpander::ContextType::TYPE);
  
    type->accept_vis (*this);
    auto final_fragment = expander.take_expanded_fragment ();
    if (final_fragment.should_expand () && final_fragment.is_type_fragment ())
      type = final_fragment.take_type_fragment ();
  
    expander.pop_context ();
  }
  
  // FIXME: Can this be refactored into a `scoped` method? Which takes a
--- 348,401 ----
  void
  ExpandVisitor::maybe_expand_type (std::unique_ptr<AST::Type> &type)
  {
!   NodeId old_expect = type->get_node_id ();
!   std::swap (macro_invoc_expect_id, old_expect);
  
+   expander.push_context (MacroExpander::ContextType::TYPE);
    type->accept_vis (*this);
+   expander.pop_context ();
+ 
+   std::swap (macro_invoc_expect_id, old_expect);
+ 
    auto final_fragment = expander.take_expanded_fragment ();
    if (final_fragment.should_expand () && final_fragment.is_type_fragment ())
      type = final_fragment.take_type_fragment ();
+ }
+ 
+ // HACK: maybe we shouldn't have TypeNoBounds as a base class
+ void
+ ExpandVisitor::maybe_expand_type (std::unique_ptr<AST::TypeNoBounds> &type)
+ {
+   NodeId old_expect = type->get_node_id ();
+   std::swap (macro_invoc_expect_id, old_expect);
+ 
+   expander.push_context (MacroExpander::ContextType::TYPE);
+   type->accept_vis (*this);
+   expander.pop_context ();
+ 
+   std::swap (macro_invoc_expect_id, old_expect);
+ 
+   auto final_fragment = expander.take_expanded_fragment ();
+   if (final_fragment.should_expand () && final_fragment.is_type_fragment ())
+     type = std::make_unique<AST::ParenthesisedType> (
+       final_fragment.take_type_fragment (), BUILTINS_LOCATION);
+ }
+ 
+ void
+ ExpandVisitor::maybe_expand_pattern (std::unique_ptr<AST::Pattern> &pattern)
+ {
+   NodeId old_expect = pattern->get_node_id ();
+   std::swap (macro_invoc_expect_id, old_expect);
  
+   expander.push_context (MacroExpander::ContextType::PATTERN);
+   pattern->accept_vis (*this);
    expander.pop_context ();
+ 
+   std::swap (macro_invoc_expect_id, old_expect);
+ 
+   auto final_fragment = expander.take_expanded_fragment ();
+   if (final_fragment.should_expand () && final_fragment.is_pattern_fragment ())
+     pattern = final_fragment.take_pattern_fragment ();
  }
  
  // FIXME: Can this be refactored into a `scoped` method? Which takes a
*************** ExpandVisitor::expand_closure_params (st
*** 424,429 ****
--- 470,477 ----
  {
    for (auto &param : params)
      {
+       maybe_expand_pattern (param.get_pattern_ptr ());
+ 
        if (param.has_type_given ())
  	maybe_expand_type (param.get_type_ptr ());
      }
*************** ExpandVisitor::visit (AST::ConstGenericP
*** 465,470 ****
--- 513,526 ----
  void
  ExpandVisitor::visit (AST::MacroInvocation &macro_invoc)
  {
+   if (macro_invoc_expect_id != macro_invoc.get_node_id ())
+     {
+       rust_internal_error_at (
+ 	macro_invoc.get_locus (),
+ 	"attempting to expand node with id %d into position with node id %d",
+ 	(int) macro_invoc.get_node_id (), (int) macro_invoc_expect_id);
+     }
+ 
    // TODO: Can we do the AST fragment replacing here? Probably not, right?
    expander.expand_invoc (macro_invoc, macro_invoc.has_semicolon ()
  					? AST::InvocKind::Semicoloned
*************** ExpandVisitor::visit (AST::MetaItemPathE
*** 542,553 ****
  {}
  
  void
- ExpandVisitor::visit (AST::ErrorPropagationExpr &expr)
- {
-   visit (expr.get_propagating_expr ());
- }
- 
- void
  ExpandVisitor::visit (AST::ArithmeticOrLogicalExpr &expr)
  {
    maybe_expand_expr (expr.get_left_expr_ptr ());
--- 598,603 ----
*************** ExpandVisitor::visit (AST::LazyBooleanEx
*** 569,574 ****
--- 619,631 ----
  }
  
  void
+ ExpandVisitor::visit (AST::TypeCastExpr &expr)
+ {
+   maybe_expand_expr (expr.get_casted_expr_ptr ());
+   maybe_expand_type (expr.get_type_to_cast_to_ptr ());
+ }
+ 
+ void
  ExpandVisitor::visit (AST::AssignmentExpr &expr)
  {
    maybe_expand_expr (expr.get_left_expr_ptr ());
*************** ExpandVisitor::visit (AST::CallExpr &exp
*** 602,621 ****
  }
  
  void
- ExpandVisitor::visit (AST::MethodCallExpr &expr)
- {
-   visit (expr.get_receiver_expr ());
- 
-   for (auto &param : expr.get_params ())
-     maybe_expand_expr (param);
- }
- 
- void
  ExpandVisitor::visit (AST::ClosureExprInner &expr)
  {
    expand_closure_params (expr.get_params ());
  
!   visit (expr.get_definition_expr ());
  }
  
  void
--- 659,669 ----
  }
  
  void
  ExpandVisitor::visit (AST::ClosureExprInner &expr)
  {
    expand_closure_params (expr.get_params ());
  
!   maybe_expand_expr (expr.get_definition_expr_ptr ());
  }
  
  void
*************** ExpandVisitor::visit (AST::IfLetExprCons
*** 677,698 ****
  }
  
  void
! ExpandVisitor::visit (AST::MatchExpr &expr)
  {
!   visit (expr.get_scrutinee_expr ());
! 
!   for (auto &match_case : expr.get_match_cases ())
!     {
!       auto &arm = match_case.get_arm ();
! 
!       for (auto &pattern : arm.get_patterns ())
! 	visit (pattern);
! 
!       if (arm.has_match_arm_guard ())
! 	maybe_expand_expr (arm.get_guard_expr_ptr ());
! 
!       maybe_expand_expr (match_case.get_expr_ptr ());
!     }
  }
  
  void
--- 725,734 ----
  }
  
  void
! ExpandVisitor::visit (AST::TupleExpr &expr)
  {
!   for (auto &sub : expr.get_tuple_elems ())
!     maybe_expand_expr (sub);
  }
  
  void
*************** ExpandVisitor::visit (AST::StaticItem &s
*** 838,852 ****
  }
  
  void
- ExpandVisitor::visit (AST::TraitItemConst &const_item)
- {
-   maybe_expand_type (const_item.get_type_ptr ());
- 
-   if (const_item.has_expr ())
-     maybe_expand_expr (const_item.get_expr_ptr ());
- }
- 
- void
  ExpandVisitor::visit (AST::Trait &trait)
  {
    for (auto &generic : trait.get_generic_params ())
--- 874,879 ----
*************** ExpandVisitor::visit (AST::StructPattern
*** 970,982 ****
  void
  ExpandVisitor::visit (AST::GroupedPattern &pattern)
  {
!   visit (pattern.get_pattern_in_parens ());
  }
  
  void
  ExpandVisitor::visit (AST::LetStmt &stmt)
  {
!   visit (stmt.get_pattern ());
  
    if (stmt.has_type ())
      maybe_expand_type (stmt.get_type_ptr ());
--- 997,1066 ----
  void
  ExpandVisitor::visit (AST::GroupedPattern &pattern)
  {
!   maybe_expand_pattern (pattern.get_pattern_in_parens_ptr ());
! }
! 
! void
! ExpandVisitor::visit (AST::SlicePatternItemsNoRest &items)
! {
!   for (auto &sub : items.get_patterns ())
!     maybe_expand_pattern (sub);
! }
! 
! void
! ExpandVisitor::visit (AST::SlicePatternItemsHasRest &items)
! {
!   for (auto &sub : items.get_lower_patterns ())
!     maybe_expand_pattern (sub);
!   for (auto &sub : items.get_upper_patterns ())
!     maybe_expand_pattern (sub);
! }
! 
! void
! ExpandVisitor::visit (AST::AltPattern &pattern)
! {
!   for (auto &alt : pattern.get_alts ())
!     maybe_expand_pattern (alt);
! }
! 
! void
! ExpandVisitor::visit (AST::TupleStructItemsNoRest &tuple_items)
! {
!   for (auto &sub : tuple_items.get_patterns ())
!     maybe_expand_pattern (sub);
! }
! 
! void
! ExpandVisitor::visit (AST::TupleStructItemsHasRest &tuple_items)
! {
!   for (auto &sub : tuple_items.get_lower_patterns ())
!     maybe_expand_pattern (sub);
! 
!   for (auto &sub : tuple_items.get_upper_patterns ())
!     maybe_expand_pattern (sub);
! }
! 
! void
! ExpandVisitor::visit (AST::TuplePatternItemsNoRest &tuple_items)
! {
!   for (auto &sub : tuple_items.get_patterns ())
!     maybe_expand_pattern (sub);
! }
! 
! void
! ExpandVisitor::visit (AST::TuplePatternItemsHasRest &tuple_items)
! {
!   for (auto &sub : tuple_items.get_lower_patterns ())
!     maybe_expand_pattern (sub);
! 
!   for (auto &sub : tuple_items.get_upper_patterns ())
!     maybe_expand_pattern (sub);
  }
  
  void
  ExpandVisitor::visit (AST::LetStmt &stmt)
  {
!   maybe_expand_pattern (stmt.get_pattern_ptr ());
  
    if (stmt.has_type ())
      maybe_expand_type (stmt.get_type_ptr ());
*************** ExpandVisitor::visit (AST::BareFunctionT
*** 1006,1015 ****
--- 1090,1107 ----
  void
  ExpandVisitor::visit (AST::FunctionParam &param)
  {
+   maybe_expand_pattern (param.get_pattern_ptr ());
    maybe_expand_type (param.get_type_ptr ());
  }
  
  void
+ ExpandVisitor::visit (AST::VariadicParam &param)
+ {
+   if (param.has_pattern ())
+     maybe_expand_pattern (param.get_pattern_ptr ());
+ }
+ 
+ void
  ExpandVisitor::visit (AST::SelfParam &param)
  {
    /* TODO: maybe check for invariants being violated - e.g. both type and
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-expand-visitor.h gcc-16-20251102/gcc/rust/expand/rust-expand-visitor.h
*** gcc-16-20251026/gcc/rust/expand/rust-expand-visitor.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-expand-visitor.h	Sun Nov  2 22:32:23 2025
***************
*** 19,25 ****
--- 19,27 ----
  #ifndef RUST_EXPAND_VISITOR_H
  #define RUST_EXPAND_VISITOR_H
  
+ #include "rust-ast-pointer-visitor.h"
  #include "rust-ast-visitor.h"
+ #include "rust-item.h"
  #include "rust-macro-expand.h"
  #include "rust-proc-macro.h"
  
*************** bool is_derive (AST::Attribute &attr);
*** 35,61 ****
   */
  bool is_builtin (AST::Attribute &attr);
  
! class ExpandVisitor : public AST::DefaultASTVisitor
  {
  public:
!   ExpandVisitor (MacroExpander &expander) : expander (expander) {}
  
    /* Expand all of the macro invocations currently contained in a crate */
    void go (AST::Crate &crate);
  
!   using AST::DefaultASTVisitor::visit;
  
!   /*
!      Maybe expand a macro invocation in lieu of an expression
!      expr : Core guidelines R33, this function reseat the pointer.
!   */
!   void maybe_expand_expr (std::unique_ptr<AST::Expr> &expr);
  
!   /*
!      Maybe expand a macro invocation in lieu of a type
!      type : Core guidelines R33, this function reseat the pointer.
     */
!   void maybe_expand_type (std::unique_ptr<AST::Type> &type);
  
    /**
     * Expand all macro invocations in lieu of types within a vector of struct
--- 37,84 ----
   */
  bool is_builtin (AST::Attribute &attr);
  
! class ExpandVisitor : public AST::PointerVisitor
  {
  public:
!   ExpandVisitor (MacroExpander &expander)
!     : expander (expander), macro_invoc_expect_id (UNKNOWN_NODEID)
!   {}
  
    /* Expand all of the macro invocations currently contained in a crate */
    void go (AST::Crate &crate);
  
!   using AST::PointerVisitor::reseat;
!   using AST::PointerVisitor::visit;
  
!   void reseat (std::unique_ptr<AST::Expr> &ptr) override
!   {
!     maybe_expand_expr (ptr);
!   }
  
!   void reseat (std::unique_ptr<AST::Type> &ptr) override
!   {
!     maybe_expand_type (ptr);
!   }
! 
!   void reseat (std::unique_ptr<AST::TypeNoBounds> &ptr) override
!   {
!     maybe_expand_type (ptr);
!   }
! 
!   void reseat (std::unique_ptr<AST::Pattern> &ptr) override
!   {
!     maybe_expand_pattern (ptr);
!   }
! 
!   /**
!    * Maybe expand a macro invocation in lieu of an expression, type or pattern.
!    *
!    * @ptr Core guidelines R33, this function reseats the pointer.
     */
!   void maybe_expand_expr (std::unique_ptr<AST::Expr> &ptr);
!   void maybe_expand_type (std::unique_ptr<AST::Type> &ptr);
!   void maybe_expand_type (std::unique_ptr<AST::TypeNoBounds> &type);
!   void maybe_expand_pattern (std::unique_ptr<AST::Pattern> &ptr);
  
    /**
     * Expand all macro invocations in lieu of types within a vector of struct
*************** public:
*** 128,134 ****
--- 151,160 ----
  	auto &value = *it;
  
  	// Perform expansion
+ 	NodeId old_expect = value->get_node_id ();
+ 	std::swap (macro_invoc_expect_id, old_expect);
  	value->accept_vis (*this);
+ 	std::swap (macro_invoc_expect_id, old_expect);
  
  	auto final_fragment = expander.take_expanded_fragment ();
  
*************** public:
*** 210,226 ****
    void visit (AST::AttrInputMacro &) override;
    void visit (AST::MetaItemLitExpr &) override;
    void visit (AST::MetaItemPathExpr &) override;
-   void visit (AST::ErrorPropagationExpr &expr) override;
    void visit (AST::ArithmeticOrLogicalExpr &expr) override;
    void visit (AST::ComparisonExpr &expr) override;
    void visit (AST::LazyBooleanExpr &expr) override;
    void visit (AST::AssignmentExpr &expr) override;
    void visit (AST::CompoundAssignmentExpr &expr) override;
    void visit (AST::GroupedExpr &expr) override;
    void visit (AST::StructExprStruct &expr) override;
  
    void visit (AST::CallExpr &expr) override;
-   void visit (AST::MethodCallExpr &expr) override;
    void visit (AST::ClosureExprInner &expr) override;
  
    void visit (AST::BlockExpr &expr) override;
--- 236,251 ----
    void visit (AST::AttrInputMacro &) override;
    void visit (AST::MetaItemLitExpr &) override;
    void visit (AST::MetaItemPathExpr &) override;
    void visit (AST::ArithmeticOrLogicalExpr &expr) override;
    void visit (AST::ComparisonExpr &expr) override;
    void visit (AST::LazyBooleanExpr &expr) override;
+   void visit (AST::TypeCastExpr &expr) override;
    void visit (AST::AssignmentExpr &expr) override;
    void visit (AST::CompoundAssignmentExpr &expr) override;
    void visit (AST::GroupedExpr &expr) override;
    void visit (AST::StructExprStruct &expr) override;
  
    void visit (AST::CallExpr &expr) override;
    void visit (AST::ClosureExprInner &expr) override;
  
    void visit (AST::BlockExpr &expr) override;
*************** public:
*** 231,237 ****
    void visit (AST::IfExprConseqElse &expr) override;
    void visit (AST::IfLetExpr &expr) override;
    void visit (AST::IfLetExprConseqElse &expr) override;
!   void visit (AST::MatchExpr &expr) override;
    void visit (AST::TypeParam &param) override;
    void visit (AST::LifetimeWhereClauseItem &) override;
    void visit (AST::TypeBoundWhereClauseItem &item) override;
--- 256,262 ----
    void visit (AST::IfExprConseqElse &expr) override;
    void visit (AST::IfLetExpr &expr) override;
    void visit (AST::IfLetExprConseqElse &expr) override;
!   void visit (AST::TupleExpr &expr) override;
    void visit (AST::TypeParam &param) override;
    void visit (AST::LifetimeWhereClauseItem &) override;
    void visit (AST::TypeBoundWhereClauseItem &item) override;
*************** public:
*** 251,257 ****
    void visit (AST::Union &union_item) override;
    void visit (AST::ConstantItem &const_item) override;
    void visit (AST::StaticItem &static_item) override;
-   void visit (AST::TraitItemConst &item) override;
    void visit (AST::Trait &trait) override;
    void visit (AST::InherentImpl &impl) override;
    void visit (AST::TraitImpl &impl) override;
--- 276,281 ----
*************** public:
*** 269,280 ****
    void visit (AST::MetaListNameValueStr &) override;
    void visit (AST::StructPatternFieldIdent &field) override;
    void visit (AST::GroupedPattern &pattern) override;
  
    void visit (AST::LetStmt &stmt) override;
    void visit (AST::ExprStmt &stmt) override;
  
    void visit (AST::BareFunctionType &type) override;
!   void visit (AST::FunctionParam &type) override;
    void visit (AST::SelfParam &type) override;
  
    template <typename T>
--- 293,312 ----
    void visit (AST::MetaListNameValueStr &) override;
    void visit (AST::StructPatternFieldIdent &field) override;
    void visit (AST::GroupedPattern &pattern) override;
+   void visit (AST::SlicePatternItemsNoRest &items) override;
+   void visit (AST::SlicePatternItemsHasRest &items) override;
+   void visit (AST::AltPattern &pattern) override;
+   void visit (AST::TupleStructItemsNoRest &tuple_items) override;
+   void visit (AST::TupleStructItemsHasRest &tuple_items) override;
+   void visit (AST::TuplePatternItemsNoRest &tuple_items) override;
+   void visit (AST::TuplePatternItemsHasRest &tuple_items) override;
  
    void visit (AST::LetStmt &stmt) override;
    void visit (AST::ExprStmt &stmt) override;
  
    void visit (AST::BareFunctionType &type) override;
!   void visit (AST::FunctionParam &param) override;
!   void visit (AST::VariadicParam &param) override;
    void visit (AST::SelfParam &type) override;
  
    template <typename T>
*************** public:
*** 287,292 ****
--- 319,325 ----
  
  private:
    MacroExpander &expander;
+   NodeId macro_invoc_expect_id;
  };
  
  } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-asm.cc gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-asm.cc
*** gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-asm.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-asm.cc	Sun Nov  2 22:32:23 2025
*************** parse_clobber_abi (InlineAsmContext inli
*** 101,107 ****
        if (token->get_id () == STRING_LITERAL)
  	{
  	  // TODO: Caring for span in here.
! 	  new_abis.push_back ({token->as_string (), token->get_locus ()});
  	}
        else
  	{
--- 101,107 ----
        if (token->get_id () == STRING_LITERAL)
  	{
  	  // TODO: Caring for span in here.
! 	  new_abis.emplace_back (token->as_string (), token->get_locus ());
  	}
        else
  	{
*************** expand_inline_asm_strings (InlineAsmCont
*** 787,798 ****
  
        auto pieces = Fmt::Pieces::collect (template_str.symbol, false,
  					  Fmt::ffi::ParseMode::InlineAsm);
!       auto pieces_vec = pieces.get_pieces ();
  
        std::string transformed_template_str = "";
        for (size_t i = 0; i < pieces_vec.size (); i++)
  	{
! 	  auto piece = pieces_vec[i];
  	  if (piece.tag == Fmt::ffi::Piece::Tag::String)
  	    {
  	      transformed_template_str += piece.string._0.to_string ();
--- 787,798 ----
  
        auto pieces = Fmt::Pieces::collect (template_str.symbol, false,
  					  Fmt::ffi::ParseMode::InlineAsm);
!       auto &pieces_vec = pieces.get_pieces ();
  
        std::string transformed_template_str = "";
        for (size_t i = 0; i < pieces_vec.size (); i++)
  	{
! 	  auto &piece = pieces_vec[i];
  	  if (piece.tag == Fmt::ffi::Piece::Tag::String)
  	    {
  	      transformed_template_str += piece.string._0.to_string ();
*************** parse_asm (location_t invoc_locus, AST::
*** 880,886 ****
    // context.
    if (resulting_context)
      {
!       auto node = (*resulting_context).inline_asm.clone_expr_without_block ();
  
        std::vector<AST::SingleASTNode> single_vec = {};
  
--- 880,887 ----
    // context.
    if (resulting_context)
      {
!       auto resulting_ctx = resulting_context.value ();
!       auto node = resulting_ctx.inline_asm.clone_expr_without_block ();
  
        std::vector<AST::SingleASTNode> single_vec = {};
  
*************** parse_llvm_clobbers (LlvmAsmContext &ctx
*** 1124,1131 ****
  	{
  	  ctx.llvm_asm.get_clobbers ().push_back (
  	    {strip_double_quotes (token->as_string ()), token->get_locus ()});
  	}
!       parser.skip_token (STRING_LITERAL);
        token = parser.peek_current_token ();
      }
  }
--- 1125,1135 ----
  	{
  	  ctx.llvm_asm.get_clobbers ().push_back (
  	    {strip_double_quotes (token->as_string ()), token->get_locus ()});
+ 
+ 	  parser.skip_token (STRING_LITERAL);
  	}
! 
!       parser.maybe_skip_token (COMMA);
        token = parser.peek_current_token ();
      }
  }
*************** parse_llvm_asm (location_t invoc_locus,
*** 1177,1188 ****
  
    auto asm_ctx = LlvmAsmContext (llvm_asm, parser, last_token_id);
  
!   auto resulting_context
      = parse_llvm_templates (asm_ctx).and_then (parse_llvm_arguments);
  
    if (resulting_context)
      {
!       auto node = (*resulting_context).llvm_asm.clone_expr_without_block ();
  
        std::vector<AST::SingleASTNode> single_vec = {};
  
--- 1181,1193 ----
  
    auto asm_ctx = LlvmAsmContext (llvm_asm, parser, last_token_id);
  
!   tl::optional<LlvmAsmContext> resulting_context
      = parse_llvm_templates (asm_ctx).and_then (parse_llvm_arguments);
  
    if (resulting_context)
      {
!       auto resulting_ctx = resulting_context.value ();
!       auto node = resulting_ctx.llvm_asm.clone_expr_without_block ();
  
        std::vector<AST::SingleASTNode> single_vec = {};
  
*************** parse_llvm_asm (location_t invoc_locus,
*** 1190,1201 ****
        // need to make it a statement. This way, it will be expanded
        // properly.
        if (semicolon == AST::InvocKind::Semicoloned)
! 	single_vec.emplace_back (AST::SingleASTNode (
! 	  std::make_unique<AST::ExprStmt> (std::move (node), invoc_locus,
! 					   semicolon
! 					     == AST::InvocKind::Semicoloned)));
        else
! 	single_vec.emplace_back (AST::SingleASTNode (std::move (node)));
  
        AST::Fragment fragment_ast
  	= AST::Fragment (single_vec,
--- 1195,1207 ----
        // need to make it a statement. This way, it will be expanded
        // properly.
        if (semicolon == AST::InvocKind::Semicoloned)
! 	{
! 	  single_vec.emplace_back (
! 	    std::make_unique<AST::ExprStmt> (std::move (node), invoc_locus,
! 					     true /* has semicolon */));
! 	}
        else
! 	single_vec.emplace_back (std::move (node));
  
        AST::Fragment fragment_ast
  	= AST::Fragment (single_vec,
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-format-args.cc gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-format-args.cc
*** gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-format-args.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-format-args.cc	Sun Nov  2 22:32:23 2025
*************** struct FormatArgsParseError
*** 37,75 ****
    } kind;
  };
  
! static tl::expected<FormatArgsInput, FormatArgsParseError>
! format_args_parse_arguments (AST::MacroInvocData &invoc)
  {
!   MacroInvocLexer lex (invoc.get_delim_tok_tree ().to_token_stream ());
!   Parser<MacroInvocLexer> parser (lex);
! 
!   // TODO: check if EOF - return that format_args!() requires at least one
!   // argument
! 
!   auto args = AST::FormatArguments ();
!   auto last_token_id = macro_end_token (invoc.get_delim_tok_tree (), parser);
!   std::unique_ptr<AST::Expr> format_expr = nullptr;
  
!   // TODO: Handle the case where we're not parsing a string literal (macro
!   // invocation for e.g.)
!   switch (parser.peek_current_token ()->get_id ())
      {
!     case STRING_LITERAL:
!     case RAW_STRING_LITERAL:
!       format_expr = parser.parse_literal_expr ();
!     default:
!       // do nothing
!       ;
      }
  
-   rust_assert (format_expr);
- 
    // TODO(Arthur): Clean this up - if we haven't parsed a string literal but a
    // macro invocation, what do we do here? return a tl::unexpected?
!   auto format_str = static_cast<AST::LiteralExpr &> (*format_expr)
! 		      .get_literal ()
! 		      .as_string ();
  
    // TODO: Allow implicit captures ONLY if the the first arg is a string literal
    // and not a macro invocation
  
--- 37,78 ----
    } kind;
  };
  
! static inline tl::expected<std::string, AST::Fragment>
! format_args_parse_expr (location_t invoc_locus, AST::MacroInvocData &invoc,
! 			Parser<MacroInvocLexer> &parser,
! 			BuiltinMacro macro_kind)
  {
!   std::unique_ptr<AST::Expr> format_expr = parser.parse_expr ();
!   rust_assert (format_expr);
  
!   if (format_expr->get_expr_kind () == AST::Expr::Kind::MacroInvocation)
      {
!       std::vector<std::unique_ptr<AST::MacroInvocation>> pending;
!       pending.emplace_back (
! 	static_cast<AST::MacroInvocation *> (format_expr.release ()));
!       return tl::unexpected<AST::Fragment> (
! 	make_eager_builtin_invocation (macro_kind, invoc_locus,
! 				       invoc.get_delim_tok_tree (),
! 				       std::move (pending)));
      }
  
    // TODO(Arthur): Clean this up - if we haven't parsed a string literal but a
    // macro invocation, what do we do here? return a tl::unexpected?
!   rust_assert (format_expr->is_literal ());
!   return static_cast<AST::LiteralExpr &> (*format_expr)
!     .get_literal ()
!     .as_string ();
! }
! 
! static inline tl::expected<AST::FormatArguments, FormatArgsParseError>
! format_args_parse_arguments (AST::MacroInvocData &invoc,
! 			     Parser<MacroInvocLexer> &parser,
! 			     TokenId last_token_id)
! {
!   // TODO: check if EOF - return that format_args!() requires at least one
!   // argument
  
+   auto args = AST::FormatArguments ();
    // TODO: Allow implicit captures ONLY if the the first arg is a string literal
    // and not a macro invocation
  
*************** format_args_parse_arguments (AST::MacroI
*** 126,132 ****
        // we need to skip commas, don't we?
      }
  
!   return FormatArgsInput{std::move (format_str), std::move (args)};
  }
  
  tl::optional<AST::Fragment>
--- 129,135 ----
        // we need to skip commas, don't we?
      }
  
!   return args;
  }
  
  tl::optional<AST::Fragment>
*************** MacroBuiltin::format_args_handler (locat
*** 135,143 ****
  				   AST::InvocKind semicolon,
  				   AST::FormatArgs::Newline nl)
  {
!   auto input = format_args_parse_arguments (invoc);
  
!   if (!input)
      {
        rust_error_at (invoc_locus,
  		     "could not parse arguments to %<format_args!()%>");
--- 138,161 ----
  				   AST::InvocKind semicolon,
  				   AST::FormatArgs::Newline nl)
  {
!   MacroInvocLexer lex (invoc.get_delim_tok_tree ().to_token_stream ());
!   Parser<MacroInvocLexer> parser (lex);
  
!   auto last_token_id = macro_end_token (invoc.get_delim_tok_tree (), parser);
! 
!   auto format_str = format_args_parse_expr (invoc_locus, invoc, parser,
! 					    nl == AST::FormatArgs::Newline::Yes
! 					      ? BuiltinMacro::FormatArgsNl
! 					      : BuiltinMacro::FormatArgs);
! 
!   if (!format_str)
!     {
!       return std::move (format_str.error ());
!     }
! 
!   auto args = format_args_parse_arguments (invoc, parser, last_token_id);
! 
!   if (!args)
      {
        rust_error_at (invoc_locus,
  		     "could not parse arguments to %<format_args!()%>");
*************** MacroBuiltin::format_args_handler (locat
*** 173,179 ****
  
    bool append_newline = nl == AST::FormatArgs::Newline::Yes;
  
!   auto fmt_str = std::move (input->format_str);
    if (append_newline)
      fmt_str += '\n';
  
--- 191,197 ----
  
    bool append_newline = nl == AST::FormatArgs::Newline::Yes;
  
!   auto fmt_str = std::move (format_str.value ());
    if (append_newline)
      fmt_str += '\n';
  
*************** MacroBuiltin::format_args_handler (locat
*** 189,195 ****
    // for creating the `template`
  
    auto fmt_args_node = AST::FormatArgs (invoc_locus, std::move (pieces),
! 					std::move (input->args));
  
    auto expanded
      = Fmt::expand_format_args (fmt_args_node,
--- 207,213 ----
    // for creating the `template`
  
    auto fmt_args_node = AST::FormatArgs (invoc_locus, std::move (pieces),
! 					std::move (args.value ()));
  
    auto expanded
      = Fmt::expand_format_args (fmt_args_node,
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-helpers.h gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-helpers.h
*** gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-helpers.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-helpers.h	Sun Nov  2 22:32:23 2025
***************
*** 22,28 ****
  #include "rust-ast.h"
  #include "rust-cfg-strip.h"
  #include "rust-diagnostics.h"
- #include "rust-early-name-resolver.h"
  #include "rust-expr.h"
  #include "rust-lex.h"
  #include "rust-macro-builtins.h"
--- 22,27 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-offset-of.cc gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-offset-of.cc
*** gcc-16-20251026/gcc/rust/expand/rust-macro-builtins-offset-of.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-builtins-offset-of.cc	Sun Nov  2 22:32:23 2025
*************** MacroBuiltin::offset_of_handler (locatio
*** 56,62 ****
    parser.skip_token (COMMA);
  
    auto field_tok = parser.parse_identifier_or_keyword_token ();
!   auto invalid_field = !field_tok || !field_tok->has_str ();
  
    if (invalid_field)
      rust_error_at (invoc_locus, "could not parse field argument for %qs",
--- 56,62 ----
    parser.skip_token (COMMA);
  
    auto field_tok = parser.parse_identifier_or_keyword_token ();
!   auto invalid_field = !field_tok || !field_tok->should_have_str ();
  
    if (invalid_field)
      rust_error_at (invoc_locus, "could not parse field argument for %qs",
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-builtins.cc gcc-16-20251102/gcc/rust/expand/rust-macro-builtins.cc
*** gcc-16-20251026/gcc/rust/expand/rust-macro-builtins.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-builtins.cc	Sun Nov  2 22:32:23 2025
***************
*** 29,35 ****
  #include "rust-ast.h"
  #include "rust-cfg-strip.h"
  #include "rust-diagnostics.h"
- #include "rust-early-name-resolver.h"
  #include "rust-expr.h"
  #include "rust-lex.h"
  #include "rust-macro-invoc-lexer.h"
--- 29,34 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-expand.cc gcc-16-20251102/gcc/rust/expand/rust-macro-expand.cc
*** gcc-16-20251026/gcc/rust/expand/rust-macro-expand.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-expand.cc	Sun Nov  2 22:32:23 2025
***************
*** 27,33 ****
  #include "rust-macro.h"
  #include "rust-parse.h"
  #include "rust-cfg-strip.h"
- #include "rust-early-name-resolver.h"
  #include "rust-proc-macro.h"
  #include "rust-token-tree-desugar.h"
  
--- 27,32 ----
*************** transcribe_expression (Parser<MacroInvoc
*** 961,969 ****
    auto &lexer = parser.get_token_source ();
    auto start = lexer.get_offs ();
  
!   auto expr = parser.parse_expr ();
    if (expr == nullptr)
!     return AST::Fragment::create_error ();
  
    // FIXME: make this an error for some edititons
    if (parser.peek_current_token ()->get_id () == SEMICOLON)
--- 960,973 ----
    auto &lexer = parser.get_token_source ();
    auto start = lexer.get_offs ();
  
!   auto attrs = parser.parse_outer_attributes ();
!   auto expr = parser.parse_expr (std::move (attrs));
    if (expr == nullptr)
!     {
!       for (auto error : parser.get_errors ())
! 	error.emit ();
!       return AST::Fragment::create_error ();
!     }
  
    // FIXME: make this an error for some edititons
    if (parser.peek_current_token ()->get_id () == SEMICOLON)
*************** transcribe_type (Parser<MacroInvocLexer>
*** 999,1004 ****
--- 1003,1029 ----
    return AST::Fragment ({std::move (type)}, lexer.get_token_slice (start, end));
  }
  
+ /**
+  * Transcribe one pattern from a macro invocation
+  *
+  * @param parser Parser to extract statements from
+  */
+ static AST::Fragment
+ transcribe_pattern (Parser<MacroInvocLexer> &parser)
+ {
+   auto &lexer = parser.get_token_source ();
+   auto start = lexer.get_offs ();
+ 
+   auto pattern = parser.parse_pattern ();
+   for (auto err : parser.get_errors ())
+     err.emit ();
+ 
+   auto end = lexer.get_offs ();
+ 
+   return AST::Fragment ({std::move (pattern)},
+ 			lexer.get_token_slice (start, end));
+ }
+ 
  static AST::Fragment
  transcribe_context (MacroExpander::ContextType ctx,
  		    Parser<MacroInvocLexer> &parser, bool semicolon,
*************** transcribe_context (MacroExpander::Conte
*** 1011,1016 ****
--- 1036,1042 ----
    //     -- Trait --> parser.parse_trait_item();
    //     -- Impl --> parser.parse_impl_item();
    //     -- Extern --> parser.parse_extern_item();
+   //     -- Pattern --> parser.parse_pattern();
    //     -- None --> [has semicolon?]
    //                 -- Yes --> parser.parse_stmt();
    //                 -- No --> [switch invocation.delimiter()]
*************** transcribe_context (MacroExpander::Conte
*** 1039,1044 ****
--- 1065,1072 ----
        break;
      case MacroExpander::ContextType::TYPE:
        return transcribe_type (parser);
+     case MacroExpander::ContextType::PATTERN:
+       return transcribe_pattern (parser);
        break;
      case MacroExpander::ContextType::STMT:
        return transcribe_many_stmts (parser, last_token_id, semicolon);
*************** MacroExpander::transcribe_rule (
*** 1080,1087 ****
    auto invoc_stream = invoc_token_tree.to_token_stream ();
    auto macro_rule_tokens = transcribe_tree.to_token_stream ();
  
!   auto substitute_context = SubstituteCtx (invoc_stream, macro_rule_tokens,
! 					   matched_fragments, definition);
    std::vector<std::unique_ptr<AST::Token>> substituted_tokens
      = substitute_context.substitute_tokens ();
  
--- 1108,1116 ----
    auto invoc_stream = invoc_token_tree.to_token_stream ();
    auto macro_rule_tokens = transcribe_tree.to_token_stream ();
  
!   auto substitute_context
!     = SubstituteCtx (invoc_stream, macro_rule_tokens, matched_fragments,
! 		     definition, invoc_token_tree.get_locus ());
    std::vector<std::unique_ptr<AST::Token>> substituted_tokens
      = substitute_context.substitute_tokens ();
  
*************** MacroExpander::transcribe_rule (
*** 1128,1138 ****
  
    // emit any errors
    if (parser.has_errors ())
!     {
!       for (auto &err : parser.get_errors ())
! 	rust_error_at (err.locus, "%s", err.message.c_str ());
!       return AST::Fragment::create_error ();
!     }
  
    // are all the tokens used?
    bool did_delimit = parser.skip_token (last_token_id);
--- 1157,1163 ----
  
    // emit any errors
    if (parser.has_errors ())
!     return AST::Fragment::create_error ();
  
    // are all the tokens used?
    bool did_delimit = parser.skip_token (last_token_id);
*************** MacroExpander::parse_proc_macro_output (
*** 1165,1171 ****
  	  auto result = parser.parse_item (false);
  	  if (result == nullptr)
  	    break;
! 	  nodes.push_back ({std::move (result)});
  	}
        break;
      case ContextType::STMT:
--- 1190,1196 ----
  	  auto result = parser.parse_item (false);
  	  if (result == nullptr)
  	    break;
! 	  nodes.emplace_back (std::move (result));
  	}
        break;
      case ContextType::STMT:
*************** MacroExpander::parse_proc_macro_output (
*** 1174,1180 ****
  	  auto result = parser.parse_stmt ();
  	  if (result == nullptr)
  	    break;
! 	  nodes.push_back ({std::move (result)});
  	}
        break;
      case ContextType::TRAIT:
--- 1199,1205 ----
  	  auto result = parser.parse_stmt ();
  	  if (result == nullptr)
  	    break;
! 	  nodes.emplace_back (std::move (result));
  	}
        break;
      case ContextType::TRAIT:
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-expand.h gcc-16-20251102/gcc/rust/expand/rust-macro-expand.h
*** gcc-16-20251026/gcc/rust/expand/rust-macro-expand.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-expand.h	Sun Nov  2 22:32:23 2025
***************
*** 27,33 ****
  #include "rust-ast.h"
  #include "rust-macro.h"
  #include "rust-hir-map.h"
- #include "rust-early-name-resolver.h"
  #include "rust-name-resolver.h"
  #include "rust-macro-invoc-lexer.h"
  #include "rust-proc-macro-invoc-lexer.h"
--- 27,32 ----
*************** struct MacroExpander
*** 291,296 ****
--- 290,296 ----
      TRAIT,
      IMPL,
      TRAIT_IMPL,
+     PATTERN,
    };
  
    ExpansionCfg cfg;
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-substitute-ctx.cc gcc-16-20251102/gcc/rust/expand/rust-macro-substitute-ctx.cc
*** gcc-16-20251026/gcc/rust/expand/rust-macro-substitute-ctx.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-substitute-ctx.cc	Sun Nov  2 22:32:23 2025
*************** SubstituteCtx::substitute_dollar_crate (
*** 40,46 ****
    if (*def_crate == current_crate)
      {
        expanded.push_back (std::make_unique<AST::Token> (
! 	Rust::Token::make_identifier (UNKNOWN_LOCATION, "crate")));
      }
    else
      {
--- 40,46 ----
    if (*def_crate == current_crate)
      {
        expanded.push_back (std::make_unique<AST::Token> (
! 	Rust::Token::make_identifier (origin, "crate")));
      }
    else
      {
*************** SubstituteCtx::substitute_dollar_crate (
*** 49,57 ****
        rust_assert (name);
  
        expanded.push_back (std::make_unique<AST::Token> (
! 	Rust::Token::make (SCOPE_RESOLUTION, UNKNOWN_LOCATION)));
        expanded.push_back (std::make_unique<AST::Token> (
! 	Rust::Token::make_identifier (UNKNOWN_LOCATION, std::string (*name))));
      }
  
    return true;
--- 49,57 ----
        rust_assert (name);
  
        expanded.push_back (std::make_unique<AST::Token> (
! 	Rust::Token::make (SCOPE_RESOLUTION, origin)));
        expanded.push_back (std::make_unique<AST::Token> (
! 	Rust::Token::make_identifier (origin, std::string (*name))));
      }
  
    return true;
*************** SubstituteCtx::substitute_metavar (
*** 108,113 ****
--- 108,119 ----
    return true;
  }
  
+ static bool
+ is_builtin_metavariable (AST::Token &token)
+ {
+   return token.get_id () == CRATE;
+ }
+ 
  bool
  SubstituteCtx::check_repetition_amount (size_t pattern_start,
  					size_t pattern_end,
*************** SubstituteCtx::check_repetition_amount (
*** 125,130 ****
--- 131,140 ----
  	      || frag_token->get_id () == IDENTIFIER)
  	    {
  	      auto it = fragments.find (frag_token->get_str ());
+ 
+ 	      if (is_builtin_metavariable (*frag_token))
+ 		continue;
+ 
  	      if (it == fragments.end ())
  		{
  		  // If the repetition is not anything we know (ie no declared
*************** SubstituteCtx::check_repetition_amount (
*** 136,141 ****
--- 146,152 ----
  				 frag_token->get_str ().c_str ());
  
  		  is_valid = false;
+ 		  continue;
  		}
  
  	      auto &fragment = *it->second;
*************** SubstituteCtx::substitute_repetition (
*** 226,232 ****
  	}
  
        auto substitute_context
! 	= SubstituteCtx (input, new_macro, sub_map, definition);
        auto new_tokens = substitute_context.substitute_tokens ();
  
        // Skip the first repetition, but add the separator to the expanded
--- 237,243 ----
  	}
  
        auto substitute_context
! 	= SubstituteCtx (input, new_macro, sub_map, definition, origin);
        auto new_tokens = substitute_context.substitute_tokens ();
  
        // Skip the first repetition, but add the separator to the expanded
diff -Nrcpad gcc-16-20251026/gcc/rust/expand/rust-macro-substitute-ctx.h gcc-16-20251102/gcc/rust/expand/rust-macro-substitute-ctx.h
*** gcc-16-20251026/gcc/rust/expand/rust-macro-substitute-ctx.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/expand/rust-macro-substitute-ctx.h	Sun Nov  2 22:32:23 2025
*************** class SubstituteCtx
*** 27,32 ****
--- 27,34 ----
    std::vector<std::unique_ptr<AST::Token>> &macro;
    std::map<std::string, MatchedFragmentContainer *> &fragments;
    AST::MacroRulesDefinition &definition;
+   // Macro invocation location
+   location_t origin;
  
    /**
     * Find the repetition amount to use when expanding a repetition, and
*************** public:
*** 43,51 ****
    SubstituteCtx (std::vector<std::unique_ptr<AST::Token>> &input,
  		 std::vector<std::unique_ptr<AST::Token>> &macro,
  		 std::map<std::string, MatchedFragmentContainer *> &fragments,
! 		 AST::MacroRulesDefinition &definition)
      : input (input), macro (macro), fragments (fragments),
!       definition (definition)
    {}
  
    /**
--- 45,53 ----
    SubstituteCtx (std::vector<std::unique_ptr<AST::Token>> &input,
  		 std::vector<std::unique_ptr<AST::Token>> &macro,
  		 std::map<std::string, MatchedFragmentContainer *> &fragments,
! 		 AST::MacroRulesDefinition &definition, location_t origin)
      : input (input), macro (macro), fragments (fragments),
!       definition (definition), origin (origin)
    {}
  
    /**
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-base.cc gcc-16-20251102/gcc/rust/hir/rust-ast-lower-base.cc
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-base.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-base.cc	Sun Nov  2 22:32:23 2025
*************** void
*** 372,380 ****
  ASTLoweringBase::visit (AST::StaticItem &)
  {}
  void
- ASTLoweringBase::visit (AST::TraitItemConst &)
- {}
- void
  ASTLoweringBase::visit (AST::TraitItemType &)
  {}
  void
--- 372,377 ----
*************** ASTLoweringBase::visit (AST::StructPatte
*** 473,492 ****
  {}
  //  void ASTLoweringBase::visit(TupleStructItemstuple_items) {}
  void
! ASTLoweringBase::visit (AST::TupleStructItemsNoRange &)
  {}
  void
! ASTLoweringBase::visit (AST::TupleStructItemsRange &)
  {}
  void
  ASTLoweringBase::visit (AST::TupleStructPattern &)
  {}
  //  void ASTLoweringBase::visit(TuplePatternItemstuple_items) {}
  void
! ASTLoweringBase::visit (AST::TuplePatternItemsMultiple &)
  {}
  void
! ASTLoweringBase::visit (AST::TuplePatternItemsRanged &)
  {}
  void
  ASTLoweringBase::visit (AST::TuplePattern &)
--- 470,489 ----
  {}
  //  void ASTLoweringBase::visit(TupleStructItemstuple_items) {}
  void
! ASTLoweringBase::visit (AST::TupleStructItemsNoRest &)
  {}
  void
! ASTLoweringBase::visit (AST::TupleStructItemsHasRest &)
  {}
  void
  ASTLoweringBase::visit (AST::TupleStructPattern &)
  {}
  //  void ASTLoweringBase::visit(TuplePatternItemstuple_items) {}
  void
! ASTLoweringBase::visit (AST::TuplePatternItemsNoRest &)
  {}
  void
! ASTLoweringBase::visit (AST::TuplePatternItemsHasRest &)
  {}
  void
  ASTLoweringBase::visit (AST::TuplePattern &)
*************** ASTLoweringBase::lower_generic_params (
*** 622,632 ****
    std::vector<std::unique_ptr<AST::GenericParam>> &params)
  {
    std::vector<std::unique_ptr<HIR::GenericParam>> lowered;
    for (auto &ast_param : params)
!     {
!       auto hir_param = ASTLowerGenericParam::translate (*ast_param);
!       lowered.push_back (std::unique_ptr<HIR::GenericParam> (hir_param));
!     }
  
    return lowered;
  }
--- 619,628 ----
    std::vector<std::unique_ptr<AST::GenericParam>> &params)
  {
    std::vector<std::unique_ptr<HIR::GenericParam>> lowered;
+   lowered.reserve (params.size ());
+ 
    for (auto &ast_param : params)
!     lowered.emplace_back (ASTLowerGenericParam::translate (*ast_param));
  
    return lowered;
  }
*************** HIR::GenericArgs
*** 659,676 ****
  ASTLoweringBase::lower_generic_args (AST::GenericArgs &args)
  {
    std::vector<HIR::GenericArgsBinding> binding_args;
    for (auto &binding : args.get_binding_args ())
!     {
!       HIR::GenericArgsBinding b = lower_binding (binding);
!       binding_args.push_back (std::move (b));
!     }
  
    std::vector<HIR::Lifetime> lifetime_args;
    for (auto &lifetime : args.get_lifetime_args ())
!     {
!       HIR::Lifetime l = lower_lifetime (lifetime);
!       lifetime_args.push_back (std::move (l));
!     }
  
    std::vector<std::unique_ptr<HIR::Type>> type_args;
    std::vector<HIR::ConstGenericArg> const_args;
--- 655,670 ----
  ASTLoweringBase::lower_generic_args (AST::GenericArgs &args)
  {
    std::vector<HIR::GenericArgsBinding> binding_args;
+   binding_args.reserve (args.get_binding_args ().size ());
+ 
    for (auto &binding : args.get_binding_args ())
!     binding_args.emplace_back (lower_binding (binding));
  
    std::vector<HIR::Lifetime> lifetime_args;
+   lifetime_args.reserve (args.get_lifetime_args ().size ());
+ 
    for (auto &lifetime : args.get_lifetime_args ())
!     lifetime_args.emplace_back (lower_lifetime (lifetime));
  
    std::vector<std::unique_ptr<HIR::Type>> type_args;
    std::vector<HIR::ConstGenericArg> const_args;
*************** ASTLoweringBase::lower_generic_args (AST
*** 681,696 ****
  	{
  	case AST::GenericArg::Kind::Type:
  	  {
! 	    auto type = ASTLoweringType::translate (arg.get_type ());
! 	    type_args.emplace_back (std::unique_ptr<HIR::Type> (type));
  	    break;
  	  }
  	case AST::GenericArg::Kind::Const:
  	  {
  	    auto expr = ASTLoweringExpr::translate (arg.get_expression ());
! 	    const_args.emplace_back (
! 	      HIR::ConstGenericArg (std::unique_ptr<HIR::Expr> (expr),
! 				    expr->get_locus ()));
  	    break;
  	  }
  	default:
--- 675,689 ----
  	{
  	case AST::GenericArg::Kind::Type:
  	  {
! 	    type_args.emplace_back (
! 	      ASTLoweringType::translate (arg.get_type ()));
  	    break;
  	  }
  	case AST::GenericArg::Kind::Const:
  	  {
  	    auto expr = ASTLoweringExpr::translate (arg.get_expression ());
! 	    const_args.emplace_back (std::unique_ptr<HIR::Expr> (expr),
! 				     expr->get_locus ());
  	    break;
  	  }
  	default:
*************** void
*** 850,858 ****
  ASTLoweringBase::handle_lang_item_attribute (const ItemWrapper &item,
  					     const AST::Attribute &attr)
  {
!   auto &literal = static_cast<AST::AttrInputLiteral &> (attr.get_attr_input ());
!   const auto &lang_item_type_str = literal.get_literal ().as_string ();
!   auto lang_item_type = LangItem::Parse (lang_item_type_str);
  
    if (lang_item_type)
      mappings.insert_lang_item (*lang_item_type,
--- 843,852 ----
  ASTLoweringBase::handle_lang_item_attribute (const ItemWrapper &item,
  					     const AST::Attribute &attr)
  {
!   auto lang_item_type_str = Analysis::Attributes::extract_string_literal (attr);
!   rust_assert (lang_item_type_str.has_value ());
! 
!   auto lang_item_type = LangItem::Parse (*lang_item_type_str);
  
    if (lang_item_type)
      mappings.insert_lang_item (*lang_item_type,
*************** ASTLoweringBase::attribute_handled_in_an
*** 877,917 ****
  
  std::unique_ptr<HIR::TuplePatternItems>
  ASTLoweringBase::lower_tuple_pattern_multiple (
!   AST::TuplePatternItemsMultiple &pattern)
  {
    std::vector<std::unique_ptr<HIR::Pattern>> patterns;
    for (auto &p : pattern.get_patterns ())
!     {
!       HIR::Pattern *translated = ASTLoweringPattern::translate (*p);
!       patterns.push_back (std::unique_ptr<HIR::Pattern> (translated));
!     }
  
    return std::unique_ptr<HIR::TuplePatternItems> (
!     new HIR::TuplePatternItemsMultiple (std::move (patterns)));
  }
  
  std::unique_ptr<TuplePatternItems>
  ASTLoweringBase::lower_tuple_pattern_ranged (
!   AST::TuplePatternItemsRanged &pattern)
  {
    std::vector<std::unique_ptr<HIR::Pattern>> lower_patterns;
    std::vector<std::unique_ptr<HIR::Pattern>> upper_patterns;
  
    for (auto &p : pattern.get_lower_patterns ())
!     {
!       HIR::Pattern *translated = ASTLoweringPattern::translate (*p);
!       lower_patterns.push_back (std::unique_ptr<HIR::Pattern> (translated));
!     }
  
    for (auto &p : pattern.get_upper_patterns ())
!     {
!       HIR::Pattern *translated = ASTLoweringPattern::translate (*p);
!       upper_patterns.push_back (std::unique_ptr<HIR::Pattern> (translated));
!     }
  
    return std::unique_ptr<HIR::TuplePatternItems> (
!     new HIR::TuplePatternItemsRanged (std::move (lower_patterns),
! 				      std::move (upper_patterns)));
  }
  
  std::unique_ptr<HIR::RangePatternBound>
--- 871,941 ----
  
  std::unique_ptr<HIR::TuplePatternItems>
  ASTLoweringBase::lower_tuple_pattern_multiple (
!   AST::TuplePatternItemsNoRest &pattern)
  {
    std::vector<std::unique_ptr<HIR::Pattern>> patterns;
+   patterns.reserve (pattern.get_patterns ().size ());
+ 
    for (auto &p : pattern.get_patterns ())
!     patterns.emplace_back (ASTLoweringPattern::translate (*p));
  
    return std::unique_ptr<HIR::TuplePatternItems> (
!     new HIR::TuplePatternItemsNoRest (std::move (patterns)));
  }
  
  std::unique_ptr<TuplePatternItems>
  ASTLoweringBase::lower_tuple_pattern_ranged (
!   AST::TuplePatternItemsHasRest &pattern)
  {
    std::vector<std::unique_ptr<HIR::Pattern>> lower_patterns;
+   lower_patterns.reserve (pattern.get_lower_patterns ().size ());
    std::vector<std::unique_ptr<HIR::Pattern>> upper_patterns;
+   upper_patterns.reserve (pattern.get_upper_patterns ().size ());
  
    for (auto &p : pattern.get_lower_patterns ())
!     lower_patterns.emplace_back (ASTLoweringPattern::translate (*p));
  
    for (auto &p : pattern.get_upper_patterns ())
!     upper_patterns.emplace_back (ASTLoweringPattern::translate (*p));
  
    return std::unique_ptr<HIR::TuplePatternItems> (
!     new HIR::TuplePatternItemsHasRest (std::move (lower_patterns),
! 				       std::move (upper_patterns)));
! }
! 
! std::unique_ptr<HIR::SlicePatternItems>
! ASTLoweringBase::lower_slice_pattern_no_rest (
!   AST::SlicePatternItemsNoRest &pattern)
! {
!   std::vector<std::unique_ptr<HIR::Pattern>> patterns;
!   patterns.reserve (pattern.get_patterns ().size ());
!   for (auto &p : pattern.get_patterns ())
!     patterns.emplace_back (ASTLoweringPattern::translate (*p));
! 
!   return std::unique_ptr<HIR::SlicePatternItems> (
!     new HIR::SlicePatternItemsNoRest (std::move (patterns)));
! }
! 
! std::unique_ptr<HIR::SlicePatternItems>
! ASTLoweringBase::lower_slice_pattern_has_rest (
!   AST::SlicePatternItemsHasRest &pattern)
! {
!   std::vector<std::unique_ptr<HIR::Pattern>> lower_patterns;
!   lower_patterns.reserve (pattern.get_lower_patterns ().size ());
!   std::vector<std::unique_ptr<HIR::Pattern>> upper_patterns;
!   upper_patterns.reserve (pattern.get_upper_patterns ().size ());
! 
!   for (auto &p : pattern.get_lower_patterns ())
!     lower_patterns.emplace_back (
!       std::unique_ptr<HIR::Pattern> (ASTLoweringPattern::translate (*p)));
! 
!   for (auto &p : pattern.get_upper_patterns ())
!     upper_patterns.emplace_back (
!       std::unique_ptr<HIR::Pattern> (ASTLoweringPattern::translate (*p)));
! 
!   return std::unique_ptr<HIR::SlicePatternItems> (
!     new HIR::SlicePatternItemsHasRest (std::move (lower_patterns),
! 				       std::move (upper_patterns)));
  }
  
  std::unique_ptr<HIR::RangePatternBound>
*************** ASTLoweringBase::lower_extern_block (AST
*** 1008,1021 ****
  				 mappings.get_next_localdef_id (crate_num));
  
    std::vector<std::unique_ptr<HIR::ExternalItem>> extern_items;
    for (auto &item : extern_block.get_extern_items ())
      {
        if (item->is_marked_for_strip ())
  	continue;
  
!       HIR::ExternalItem *lowered
! 	= ASTLoweringExternItem::translate (item.get (), mapping.get_hirid ());
!       extern_items.push_back (std::unique_ptr<HIR::ExternalItem> (lowered));
      }
  
    ABI abi = ABI::C;
--- 1032,1046 ----
  				 mappings.get_next_localdef_id (crate_num));
  
    std::vector<std::unique_ptr<HIR::ExternalItem>> extern_items;
+   extern_items.reserve (extern_block.get_extern_items ().size ());
+ 
    for (auto &item : extern_block.get_extern_items ())
      {
        if (item->is_marked_for_strip ())
  	continue;
  
!       extern_items.emplace_back (
! 	ASTLoweringExternItem::translate (item.get (), mapping.get_hirid ()));
      }
  
    ABI abi = ABI::C;
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-base.h gcc-16-20251102/gcc/rust/hir/rust-ast-lower-base.h
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-base.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-base.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 189,195 ****
    virtual void visit (AST::Union &union_item) override;
    virtual void visit (AST::ConstantItem &const_item) override;
    virtual void visit (AST::StaticItem &static_item) override;
-   virtual void visit (AST::TraitItemConst &item) override;
    virtual void visit (AST::TraitItemType &item) override;
    virtual void visit (AST::Trait &trait) override;
    virtual void visit (AST::InherentImpl &impl) override;
--- 189,194 ----
*************** public:
*** 228,239 ****
    virtual void visit (AST::StructPatternFieldIdent &field) override;
    virtual void visit (AST::StructPattern &pattern) override;
    //  virtual void visit(TupleStructItems& tuple_items) override;
!   virtual void visit (AST::TupleStructItemsNoRange &tuple_items) override;
!   virtual void visit (AST::TupleStructItemsRange &tuple_items) override;
    virtual void visit (AST::TupleStructPattern &pattern) override;
    //  virtual void visit(TuplePatternItems& tuple_items) override;
!   virtual void visit (AST::TuplePatternItemsMultiple &tuple_items) override;
!   virtual void visit (AST::TuplePatternItemsRanged &tuple_items) override;
    virtual void visit (AST::TuplePattern &pattern) override;
    virtual void visit (AST::GroupedPattern &pattern) override;
    virtual void visit (AST::SlicePatternItemsNoRest &items) override;
--- 227,238 ----
    virtual void visit (AST::StructPatternFieldIdent &field) override;
    virtual void visit (AST::StructPattern &pattern) override;
    //  virtual void visit(TupleStructItems& tuple_items) override;
!   virtual void visit (AST::TupleStructItemsNoRest &tuple_items) override;
!   virtual void visit (AST::TupleStructItemsHasRest &tuple_items) override;
    virtual void visit (AST::TupleStructPattern &pattern) override;
    //  virtual void visit(TuplePatternItems& tuple_items) override;
!   virtual void visit (AST::TuplePatternItemsNoRest &tuple_items) override;
!   virtual void visit (AST::TuplePatternItemsHasRest &tuple_items) override;
    virtual void visit (AST::TuplePattern &pattern) override;
    virtual void visit (AST::GroupedPattern &pattern) override;
    virtual void visit (AST::SlicePatternItemsNoRest &items) override;
*************** protected:
*** 317,326 ****
    attribute_handled_in_another_pass (const std::string &attribute_path) const;
  
    std::unique_ptr<TuplePatternItems>
!   lower_tuple_pattern_multiple (AST::TuplePatternItemsMultiple &pattern);
  
    std::unique_ptr<TuplePatternItems>
!   lower_tuple_pattern_ranged (AST::TuplePatternItemsRanged &pattern);
  
    std::unique_ptr<HIR::RangePatternBound>
    lower_range_pattern_bound (AST::RangePatternBound &bound);
--- 316,331 ----
    attribute_handled_in_another_pass (const std::string &attribute_path) const;
  
    std::unique_ptr<TuplePatternItems>
!   lower_tuple_pattern_multiple (AST::TuplePatternItemsNoRest &pattern);
  
    std::unique_ptr<TuplePatternItems>
!   lower_tuple_pattern_ranged (AST::TuplePatternItemsHasRest &pattern);
! 
!   std::unique_ptr<SlicePatternItems>
!   lower_slice_pattern_no_rest (AST::SlicePatternItemsNoRest &pattern);
! 
!   std::unique_ptr<SlicePatternItems>
!   lower_slice_pattern_has_rest (AST::SlicePatternItemsHasRest &pattern);
  
    std::unique_ptr<HIR::RangePatternBound>
    lower_range_pattern_bound (AST::RangePatternBound &bound);
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-enumitem.h gcc-16-20251102/gcc/rust/hir/rust-ast-lower-enumitem.h
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-enumitem.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-enumitem.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 80,85 ****
--- 80,87 ----
  		     item.get_visibility ().as_string ().c_str ());
  
      std::vector<HIR::TupleField> fields;
+     fields.reserve (item.get_tuple_fields ().size ());
+ 
      for (auto &field : item.get_tuple_fields ())
        {
  	HIR::Visibility vis = translate_visibility (field.get_visibility ());
*************** public:
*** 90,100 ****
  	  crate_num, field.get_node_id (), mappings.get_next_hir_id (crate_num),
  	  mappings.get_next_localdef_id (crate_num));
  
! 	HIR::TupleField translated_field (field_mapping,
! 					  std::unique_ptr<HIR::Type> (type),
! 					  vis, field.get_locus (),
! 					  field.get_outer_attrs ());
! 	fields.push_back (std::move (translated_field));
        }
  
      translated
--- 92,99 ----
  	  crate_num, field.get_node_id (), mappings.get_next_hir_id (crate_num),
  	  mappings.get_next_localdef_id (crate_num));
  
! 	fields.emplace_back (field_mapping, std::unique_ptr<HIR::Type> (type),
! 			     vis, field.get_locus (), field.get_outer_attrs ());
        }
  
      translated
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-expr.cc gcc-16-20251102/gcc/rust/hir/rust-ast-lower-expr.cc
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-expr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-expr.cc	Sun Nov  2 22:32:23 2025
*************** void
*** 81,91 ****
  ASTLoweringExpr::visit (AST::TupleExpr &expr)
  {
    std::vector<std::unique_ptr<HIR::Expr>> tuple_elements;
    for (auto &e : expr.get_tuple_elems ())
!     {
!       HIR::Expr *t = ASTLoweringExpr::translate (*e);
!       tuple_elements.push_back (std::unique_ptr<HIR::Expr> (t));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
--- 81,90 ----
  ASTLoweringExpr::visit (AST::TupleExpr &expr)
  {
    std::vector<std::unique_ptr<HIR::Expr>> tuple_elements;
+   tuple_elements.reserve (expr.get_tuple_elems ().size ());
+ 
    for (auto &e : expr.get_tuple_elems ())
!     tuple_elements.emplace_back (ASTLoweringExpr::translate (*e));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
*************** ASTLoweringExpr::visit (AST::CallExpr &e
*** 221,232 ****
    HIR::Expr *func = ASTLoweringExpr::translate (expr.get_function_expr ());
  
    auto const &in_params = expr.get_params ();
    std::vector<std::unique_ptr<HIR::Expr>> params;
    for (auto &param : in_params)
!     {
!       auto trans = ASTLoweringExpr::translate (*param);
!       params.push_back (std::unique_ptr<HIR::Expr> (trans));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (
--- 220,231 ----
    HIR::Expr *func = ASTLoweringExpr::translate (expr.get_function_expr ());
  
    auto const &in_params = expr.get_params ();
+ 
    std::vector<std::unique_ptr<HIR::Expr>> params;
+   params.reserve (in_params.size ());
+ 
    for (auto &param : in_params)
!     params.emplace_back (ASTLoweringExpr::translate (*param));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (
*************** ASTLoweringExpr::visit (AST::MethodCallE
*** 248,258 ****
  
    auto const &in_params = expr.get_params ();
    std::vector<std::unique_ptr<HIR::Expr>> params;
    for (auto &param : in_params)
!     {
!       auto trans = ASTLoweringExpr::translate (*param);
!       params.push_back (std::unique_ptr<HIR::Expr> (trans));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
--- 247,256 ----
  
    auto const &in_params = expr.get_params ();
    std::vector<std::unique_ptr<HIR::Expr>> params;
+   params.reserve (in_params.size ());
+ 
    for (auto &param : in_params)
!     params.emplace_back (ASTLoweringExpr::translate (*param));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
*************** void
*** 338,348 ****
  ASTLoweringExpr::visit (AST::ArrayElemsValues &elems)
  {
    std::vector<std::unique_ptr<HIR::Expr>> elements;
    for (auto &elem : elems.get_values ())
!     {
!       HIR::Expr *translated_elem = ASTLoweringExpr::translate (*elem);
!       elements.push_back (std::unique_ptr<HIR::Expr> (translated_elem));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (mappings.get_current_crate (),
--- 336,345 ----
  ASTLoweringExpr::visit (AST::ArrayElemsValues &elems)
  {
    std::vector<std::unique_ptr<HIR::Expr>> elements;
+   elements.reserve (elems.get_values ().size ());
+ 
    for (auto &elem : elems.get_values ())
!     elements.emplace_back (ASTLoweringExpr::translate (*elem));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (mappings.get_current_crate (),
*************** ASTLoweringExpr::visit (AST::StructExprS
*** 569,581 ****
      }
  
    auto const &in_fields = struct_expr.get_fields ();
    std::vector<std::unique_ptr<HIR::StructExprField>> fields;
    for (auto &field : in_fields)
!     {
!       HIR::StructExprField *translated
! 	= ASTLowerStructExprField::translate (*field);
!       fields.push_back (std::unique_ptr<HIR::StructExprField> (translated));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, struct_expr.get_node_id (),
--- 566,577 ----
      }
  
    auto const &in_fields = struct_expr.get_fields ();
+ 
    std::vector<std::unique_ptr<HIR::StructExprField>> fields;
+   fields.reserve (in_fields.size ());
+ 
    for (auto &field : in_fields)
!     fields.emplace_back (ASTLowerStructExprField::translate (*field));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, struct_expr.get_node_id (),
*************** ASTLoweringExpr::visit (AST::ClosureExpr
*** 814,824 ****
      = ASTLoweringExpr::translate (expr.get_definition_expr ());
  
    std::vector<HIR::ClosureParam> closure_params;
    for (auto &param : expr.get_params ())
!     {
!       HIR::ClosureParam p = lower_closure_param (param);
!       closure_params.push_back (std::move (p));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
--- 810,819 ----
      = ASTLoweringExpr::translate (expr.get_definition_expr ());
  
    std::vector<HIR::ClosureParam> closure_params;
+   closure_params.reserve (expr.get_params ().size ());
+ 
    for (auto &param : expr.get_params ())
!     closure_params.emplace_back (lower_closure_param (param));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
*************** ASTLoweringExpr::visit (AST::ClosureExpr
*** 841,851 ****
      = ASTLoweringExpr::translate (expr.get_definition_expr ());
  
    std::vector<HIR::ClosureParam> closure_params;
    for (auto &param : expr.get_params ())
!     {
!       HIR::ClosureParam p = lower_closure_param (param);
!       closure_params.push_back (std::move (p));
!     }
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
--- 836,845 ----
      = ASTLoweringExpr::translate (expr.get_definition_expr ());
  
    std::vector<HIR::ClosureParam> closure_params;
+   closure_params.reserve (expr.get_params ().size ());
+ 
    for (auto &param : expr.get_params ())
!     closure_params.emplace_back (lower_closure_param (param));
  
    auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, expr.get_node_id (),
*************** ASTLoweringExpr::visit (AST::InlineAsm &
*** 1000,1005 ****
--- 994,1016 ----
  			  expr.get_options (), mapping);
  }
  
+ namespace {
+ // We're not really supporting llvm_asm, only the bare minimum for libcore's
+ // blackbox
+ // llvm_asm!("" : : "r"(&mut dummy) : "memory" : "volatile");
+ bool
+ check_llvm_asm_support (const std::vector<LlvmOperand> &inputs,
+ 			const std::vector<LlvmOperand> &outputs,
+ 			const AST::LlvmInlineAsm &expr)
+ {
+   return outputs.size () == 0 && inputs.size () <= 1
+ 	 && expr.get_clobbers ().size () <= 1
+ 	 && expr.get_templates ().size () == 1
+ 	 && expr.get_templates ()[0].symbol == "";
+ }
+ 
+ } // namespace
+ 
  void
  ASTLoweringExpr::visit (AST::LlvmInlineAsm &expr)
  {
*************** ASTLoweringExpr::visit (AST::LlvmInlineA
*** 1009,1015 ****
--- 1020,1029 ----
  				 mappings.get_next_localdef_id (crate_num));
  
    std::vector<LlvmOperand> inputs;
+   inputs.reserve (expr.get_inputs ().size ());
+ 
    std::vector<LlvmOperand> outputs;
+   outputs.reserve (expr.get_outputs ().size ());
  
    for (auto i : expr.get_inputs ())
      {
*************** ASTLoweringExpr::visit (AST::LlvmInlineA
*** 1029,1041 ****
  				      expr.is_stack_aligned (),
  				      expr.get_dialect ()};
  
!   // We're not really supporting llvm_asm, only the bare minimum
!   // we're quite conservative here as the current code support more usecase.
!   rust_assert (outputs.size () == 0);
!   rust_assert (inputs.size () <= 1);
!   rust_assert (expr.get_clobbers ().size () <= 1);
!   rust_assert (expr.get_templates ().size () == 1);
!   rust_assert (expr.get_templates ()[0].symbol == "");
  
    translated
      = new HIR::LlvmInlineAsm (expr.get_locus (), inputs, outputs,
--- 1043,1057 ----
  				      expr.is_stack_aligned (),
  				      expr.get_dialect ()};
  
!   if (!check_llvm_asm_support (inputs, outputs, expr))
!     {
!       rust_error_at (expr.get_locus (), "unsupported %qs construct",
! 		     "llvm_asm");
!       rust_inform (
! 	expr.get_locus (),
! 	"%<llvm_asm%> has been replaced with %<asm%>, gccrs only supports a "
! 	"subset of %<llvm_asm%> to compile libcore");
!     }
  
    translated
      = new HIR::LlvmInlineAsm (expr.get_locus (), inputs, outputs,
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-extern.h gcc-16-20251102/gcc/rust/hir/rust-ast-lower-extern.h
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-extern.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-extern.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 109,117 ****
  				       mappings.get_next_localdef_id (
  					 crate_num));
  
! 	function_params.push_back (
! 	  HIR::NamedFunctionParam (mapping, param_name,
! 				   std::unique_ptr<HIR::Type> (param_type)));
        }
  
      auto crate_num = mappings.get_current_crate ();
--- 109,116 ----
  				       mappings.get_next_localdef_id (
  					 crate_num));
  
! 	function_params.emplace_back (mapping, param_name,
! 				      std::unique_ptr<HIR::Type> (param_type));
        }
  
      auto crate_num = mappings.get_current_crate ();
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-implitem.cc gcc-16-20251102/gcc/rust/hir/rust-ast-lower-implitem.cc
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-implitem.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-implitem.cc	Sun Nov  2 22:32:23 2025
*************** ASTLowerImplItem::visit (AST::Function &
*** 115,121 ****
      {
        HIR::WhereClauseItem *i
  	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
      }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
--- 115,121 ----
      {
        HIR::WhereClauseItem *i
  	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.emplace_back (i);
      }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
*************** ASTLowerImplItem::visit (AST::Function &
*** 162,171 ****
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       auto hir_param
! 	= HIR::FunctionParam (mapping, std::move (translated_pattern),
! 			      std::move (translated_type), param.get_locus ());
!       function_params.push_back (std::move (hir_param));
      }
  
    bool terminated = false;
--- 162,170 ----
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       function_params.emplace_back (mapping, std::move (translated_pattern),
! 				    std::move (translated_type),
! 				    param.get_locus ());
      }
  
    bool terminated = false;
*************** ASTLowerTraitItem::visit (AST::Function
*** 272,281 ****
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       auto hir_param
! 	= HIR::FunctionParam (mapping, std::move (translated_pattern),
! 			      std::move (translated_type), param.get_locus ());
!       function_params.push_back (std::move (hir_param));
      }
  
    if (func.has_self_param ())
--- 271,279 ----
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       function_params.emplace_back (mapping, std::move (translated_pattern),
! 				    std::move (translated_type),
! 				    param.get_locus ());
      }
  
    if (func.has_self_param ())
*************** ASTLowerTraitItem::visit (AST::Function
*** 320,329 ****
  }
  
  void
! ASTLowerTraitItem::visit (AST::TraitItemConst &constant)
  {
    HIR::Type *type = ASTLoweringType::translate (constant.get_type ());
!   HIR::Expr *expr = constant.has_expression ()
  		      ? ASTLoweringExpr::translate (constant.get_expr ())
  		      : nullptr;
  
--- 318,327 ----
  }
  
  void
! ASTLowerTraitItem::visit (AST::ConstantItem &constant)
  {
    HIR::Type *type = ASTLoweringType::translate (constant.get_type ());
!   HIR::Expr *expr = constant.has_expr ()
  		      ? ASTLoweringExpr::translate (constant.get_expr ())
  		      : nullptr;
  
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-implitem.h gcc-16-20251102/gcc/rust/hir/rust-ast-lower-implitem.h
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-implitem.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-implitem.h	Sun Nov  2 22:32:23 2025
*************** class ASTLowerTraitItem : public ASTLowe
*** 49,55 ****
  public:
    static HIR::TraitItem *translate (AST::AssociatedItem &item);
    void visit (AST::Function &func) override;
!   void visit (AST::TraitItemConst &constant) override;
    void visit (AST::TraitItemType &type) override;
  
  private:
--- 49,55 ----
  public:
    static HIR::TraitItem *translate (AST::AssociatedItem &item);
    void visit (AST::Function &func) override;
!   void visit (AST::ConstantItem &constant) override;
    void visit (AST::TraitItemType &type) override;
  
  private:
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-item.cc gcc-16-20251102/gcc/rust/hir/rust-ast-lower-item.cc
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-item.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-item.cc	Sun Nov  2 22:32:23 2025
*************** ASTLoweringItem::visit (AST::Module &mod
*** 72,78 ****
        // The item may be null if it doesn't need to live in the HIR - for
        // example, macro rules definitions
        if (transitem)
! 	items.push_back (std::unique_ptr<Item> (transitem));
      }
  
    // should be lowered/copied from module.get_in/outer_attrs()
--- 72,78 ----
        // The item may be null if it doesn't need to live in the HIR - for
        // example, macro rules definitions
        if (transitem)
! 	items.emplace_back (transitem);
      }
  
    // should be lowered/copied from module.get_in/outer_attrs()
*************** void
*** 90,101 ****
  ASTLoweringItem::visit (AST::TypeAlias &alias)
  {
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : alias.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (alias.get_visibility ());
--- 90,100 ----
  ASTLoweringItem::visit (AST::TypeAlias &alias)
  {
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (alias.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : alias.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (alias.get_visibility ());
*************** ASTLoweringItem::visit (AST::TupleStruct
*** 130,146 ****
      }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : struct_decl.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (struct_decl.get_visibility ());
  
    std::vector<HIR::TupleField> fields;
    for (AST::TupleField &field : struct_decl.get_fields ())
      {
        if (field.get_field_type ().is_marked_for_strip ())
--- 129,147 ----
      }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     struct_decl.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : struct_decl.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (struct_decl.get_visibility ());
  
    std::vector<HIR::TupleField> fields;
+   fields.reserve (struct_decl.get_fields ().size ());
+ 
    for (AST::TupleField &field : struct_decl.get_fields ())
      {
        if (field.get_field_type ().is_marked_for_strip ())
*************** ASTLoweringItem::visit (AST::TupleStruct
*** 155,165 ****
  				     mappings.get_next_hir_id (crate_num),
  				     mappings.get_next_localdef_id (crate_num));
  
!       HIR::TupleField translated_field (mapping,
! 					std::unique_ptr<HIR::Type> (type), vis,
! 					field.get_locus (),
! 					field.get_outer_attrs ());
!       fields.push_back (std::move (translated_field));
      }
  
    auto crate_num = mappings.get_current_crate ();
--- 156,163 ----
  				     mappings.get_next_hir_id (crate_num),
  				     mappings.get_next_localdef_id (crate_num));
  
!       fields.emplace_back (mapping, std::unique_ptr<HIR::Type> (type), vis,
! 			   field.get_locus (), field.get_outer_attrs ());
      }
  
    auto crate_num = mappings.get_current_crate ();
*************** ASTLoweringItem::visit (AST::StructStruc
*** 185,196 ****
      }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : struct_decl.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
  
--- 183,194 ----
      }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     struct_decl.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : struct_decl.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
  
*************** ASTLoweringItem::visit (AST::Enum &enum_
*** 245,269 ****
      }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : enum_decl.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (enum_decl.get_visibility ());
  
    // bool is_unit = enum_decl.is_zero_variant ();
    std::vector<std::unique_ptr<HIR::EnumItem>> items;
    for (auto &variant : enum_decl.get_variants ())
      {
        if (variant->is_marked_for_strip ())
  	continue;
  
!       HIR::EnumItem *hir_item = ASTLoweringEnumItem::translate (variant.get ());
!       items.push_back (std::unique_ptr<HIR::EnumItem> (hir_item));
      }
  
    auto crate_num = mappings.get_current_crate ();
--- 243,268 ----
      }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     enum_decl.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : enum_decl.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (enum_decl.get_visibility ());
  
    // bool is_unit = enum_decl.is_zero_variant ();
    std::vector<std::unique_ptr<HIR::EnumItem>> items;
+   items.reserve (enum_decl.get_variants ().size ());
+ 
    for (auto &variant : enum_decl.get_variants ())
      {
        if (variant->is_marked_for_strip ())
  	continue;
  
!       items.emplace_back (ASTLoweringEnumItem::translate (variant.get ()));
      }
  
    auto crate_num = mappings.get_current_crate ();
*************** ASTLoweringItem::visit (AST::Union &unio
*** 288,304 ****
  {
    std::vector<std::unique_ptr<HIR::GenericParam>> generic_params;
    if (union_decl.has_generics ())
!     {
!       generic_params = lower_generic_params (union_decl.get_generic_params ());
!     }
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : union_decl.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (union_decl.get_visibility ());
  
--- 287,302 ----
  {
    std::vector<std::unique_ptr<HIR::GenericParam>> generic_params;
    if (union_decl.has_generics ())
!     generic_params = lower_generic_params (union_decl.get_generic_params ());
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     union_decl.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : union_decl.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
! 
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (union_decl.get_visibility ());
  
*************** ASTLoweringItem::visit (AST::Function &f
*** 390,401 ****
      return;
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : function.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::FunctionQualifiers qualifiers
--- 388,399 ----
      return;
  
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     function.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : function.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::FunctionQualifiers qualifiers
*************** ASTLoweringItem::visit (AST::Function &f
*** 418,427 ****
  				  : nullptr;
  
    std::vector<HIR::FunctionParam> function_params;
    for (auto &p : function.get_function_params ())
      {
!       if (p->is_variadic () || p->is_self ())
  	continue;
        auto param = static_cast<AST::FunctionParam &> (*p);
  
        auto translated_pattern = std::unique_ptr<HIR::Pattern> (
--- 416,456 ----
  				  : nullptr;
  
    std::vector<HIR::FunctionParam> function_params;
+   function_params.reserve (function.get_function_params ().size ());
+ 
+   auto crate_num = mappings.get_current_crate ();
    for (auto &p : function.get_function_params ())
      {
!       if (p->is_variadic ())
  	continue;
+       if (p->is_self ())
+ 	{
+ 	  rich_location r (line_table, p->get_locus ());
+ 	  r.add_range (function.get_locus ());
+ 	  rust_error_at (
+ 	    r, "%<self%> parameter is only allowed in associated functions");
+ 
+ 	  // rustc creates a synthetic regular fn-param here pointing to a
+ 	  // generic Self as far as i can see but that seems over the top for
+ 	  // now.
+ 	  //
+ 	  // see this example (invalid code):
+ 	  //
+ 	  // pub trait X {
+ 	  //   fn x() {
+ 	  //     fn f(&mut self) {}
+ 	  //     f();
+ 	  //   }
+ 	  // }
+ 	  //
+ 	  // without a synthetic param we wont get the number of args error as
+ 	  // well but i think this is fine for now.
+ 	  //
+ 	  // problem is what we make the param type to become...
+ 
+ 	  continue;
+ 	}
+ 
        auto param = static_cast<AST::FunctionParam &> (*p);
  
        auto translated_pattern = std::unique_ptr<HIR::Pattern> (
*************** ASTLoweringItem::visit (AST::Function &f
*** 434,443 ****
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       auto hir_param
! 	= HIR::FunctionParam (mapping, std::move (translated_pattern),
! 			      std::move (translated_type), param.get_locus ());
!       function_params.push_back (std::move (hir_param));
      }
  
    bool terminated = false;
--- 463,471 ----
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       function_params.emplace_back (mapping, std::move (translated_pattern),
! 				    std::move (translated_type),
! 				    param.get_locus ());
      }
  
    bool terminated = false;
*************** ASTLoweringItem::visit (AST::Function &f
*** 446,452 ****
        ASTLoweringBlock::translate (*function.get_definition ().value (),
  				   &terminated));
  
-   auto crate_num = mappings.get_current_crate ();
    Analysis::NodeMapping mapping (crate_num, function.get_node_id (),
  				 mappings.get_next_hir_id (crate_num),
  				 mappings.get_next_localdef_id (crate_num));
--- 474,479 ----
*************** void
*** 479,489 ****
  ASTLoweringItem::visit (AST::InherentImpl &impl_block)
  {
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : impl_block.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i = ASTLowerWhereClauseItem::translate (*item);
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (impl_block.get_visibility ());
--- 506,517 ----
  ASTLoweringItem::visit (AST::InherentImpl &impl_block)
  {
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     impl_block.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : impl_block.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item));
  
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (impl_block.get_visibility ());
*************** ASTLoweringItem::visit (AST::InherentImp
*** 540,546 ****
        HIR::ImplItem *lowered
  	= ASTLowerImplItem::translate (*impl_item, mapping.get_hirid ());
        rust_assert (lowered != nullptr);
!       impl_items.push_back (std::unique_ptr<HIR::ImplItem> (lowered));
        impl_item_ids.push_back (lowered->get_impl_mappings ().get_hirid ());
      }
  
--- 568,574 ----
        HIR::ImplItem *lowered
  	= ASTLowerImplItem::translate (*impl_item, mapping.get_hirid ());
        rust_assert (lowered != nullptr);
!       impl_items.emplace_back (lowered);
        impl_item_ids.push_back (lowered->get_impl_mappings ().get_hirid ());
      }
  
*************** void
*** 563,574 ****
  ASTLoweringItem::visit (AST::Trait &trait)
  {
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    for (auto &item : trait.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i
! 	= ASTLowerWhereClauseItem::translate (*item.get ());
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
    HIR::WhereClause where_clause (std::move (where_clause_items));
  
    HIR::Visibility vis = translate_visibility (trait.get_visibility ());
--- 591,602 ----
  ASTLoweringItem::visit (AST::Trait &trait)
  {
    std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (trait.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : trait.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item.get ()));
! 
    HIR::WhereClause where_clause (std::move (where_clause_items));
  
    HIR::Visibility vis = translate_visibility (trait.get_visibility ());
*************** ASTLoweringItem::visit (AST::Trait &trai
*** 589,611 ****
    if (trait.has_type_param_bounds ())
      {
        for (auto &bound : trait.get_type_param_bounds ())
! 	{
! 	  HIR::TypeParamBound *b = lower_bound (*bound);
! 	  type_param_bounds.push_back (
! 	    std::unique_ptr<HIR::TypeParamBound> (b));
! 	}
      }
  
    std::vector<std::unique_ptr<HIR::TraitItem>> trait_items;
    std::vector<HirId> trait_item_ids;
    for (auto &item : trait.get_trait_items ())
      {
        if (item->is_marked_for_strip ())
  	continue;
  
        HIR::TraitItem *lowered = ASTLowerTraitItem::translate (*item);
-       trait_items.push_back (std::unique_ptr<HIR::TraitItem> (lowered));
        trait_item_ids.push_back (lowered->get_mappings ().get_hirid ());
      }
  
    auto crate_num = mappings.get_current_crate ();
--- 617,640 ----
    if (trait.has_type_param_bounds ())
      {
        for (auto &bound : trait.get_type_param_bounds ())
! 	type_param_bounds.emplace_back (lower_bound (*bound));
      }
  
+   auto trait_item_size = trait.get_trait_items ().size ();
+ 
    std::vector<std::unique_ptr<HIR::TraitItem>> trait_items;
+   trait_items.reserve (trait_item_size);
    std::vector<HirId> trait_item_ids;
+   trait_item_ids.reserve (trait_item_size);
+ 
    for (auto &item : trait.get_trait_items ())
      {
        if (item->is_marked_for_strip ())
  	continue;
  
        HIR::TraitItem *lowered = ASTLowerTraitItem::translate (*item);
        trait_item_ids.push_back (lowered->get_mappings ().get_hirid ());
+       trait_items.emplace_back (lowered);
      }
  
    auto crate_num = mappings.get_current_crate ();
*************** ASTLoweringItem::visit (AST::Trait &trai
*** 636,648 ****
  void
  ASTLoweringItem::visit (AST::TraitImpl &impl_block)
  {
-   std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
    bool unsafe = impl_block.is_unsafe ();
    for (auto &item : impl_block.get_where_clause ().get_items ())
!     {
!       HIR::WhereClauseItem *i = ASTLowerWhereClauseItem::translate (*item);
!       where_clause_items.push_back (std::unique_ptr<HIR::WhereClauseItem> (i));
!     }
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (impl_block.get_visibility ());
  
--- 665,680 ----
  void
  ASTLoweringItem::visit (AST::TraitImpl &impl_block)
  {
    bool unsafe = impl_block.is_unsafe ();
+ 
+   std::vector<std::unique_ptr<HIR::WhereClauseItem>> where_clause_items;
+   where_clause_items.reserve (
+     impl_block.get_where_clause ().get_items ().size ());
+ 
    for (auto &item : impl_block.get_where_clause ().get_items ())
!     where_clause_items.emplace_back (
!       ASTLowerWhereClauseItem::translate (*item));
! 
    HIR::WhereClause where_clause (std::move (where_clause_items));
    HIR::Visibility vis = translate_visibility (impl_block.get_visibility ());
  
*************** ASTLoweringItem::visit (AST::TraitImpl &
*** 690,697 ****
--- 722,734 ----
  				 mappings.get_next_hir_id (crate_num),
  				 mappings.get_next_localdef_id (crate_num));
  
+   auto impl_items_size = impl_block.get_impl_items ().size ();
+ 
    std::vector<std::unique_ptr<HIR::ImplItem>> impl_items;
+   impl_items.reserve (impl_items_size);
    std::vector<HirId> impl_item_ids;
+   impl_item_ids.reserve (impl_items_size);
+ 
    for (auto &impl_item : impl_block.get_impl_items ())
      {
        if (impl_item->is_marked_for_strip ())
*************** ASTLoweringItem::visit (AST::TraitImpl &
*** 700,707 ****
        HIR::ImplItem *lowered
  	= ASTLowerImplItem::translate (*impl_item, mapping.get_hirid ());
        rust_assert (lowered != nullptr);
-       impl_items.push_back (std::unique_ptr<HIR::ImplItem> (lowered));
        impl_item_ids.push_back (lowered->get_impl_mappings ().get_hirid ());
      }
  
    BoundPolarity polarity = impl_block.is_exclam ()
--- 737,744 ----
        HIR::ImplItem *lowered
  	= ASTLowerImplItem::translate (*impl_item, mapping.get_hirid ());
        rust_assert (lowered != nullptr);
        impl_item_ids.push_back (lowered->get_impl_mappings ().get_hirid ());
+       impl_items.emplace_back (lowered);
      }
  
    BoundPolarity polarity = impl_block.is_exclam ()
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower-pattern.cc gcc-16-20251102/gcc/rust/hir/rust-ast-lower-pattern.cc
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower-pattern.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower-pattern.cc	Sun Nov  2 22:32:23 2025
*************** ASTLoweringPattern::visit (AST::TupleStr
*** 81,106 ****
    auto &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case AST::TupleStructItems::RANGE:
        {
! 	// TODO
! 	rust_unreachable ();
        }
        break;
  
!     case AST::TupleStructItems::NO_RANGE:
        {
! 	AST::TupleStructItemsNoRange &items_no_range
! 	  = static_cast<AST::TupleStructItemsNoRange &> (items);
  
  	std::vector<std::unique_ptr<HIR::Pattern>> patterns;
! 	for (auto &inner_pattern : items_no_range.get_patterns ())
! 	  {
! 	    HIR::Pattern *p = ASTLoweringPattern::translate (*inner_pattern);
! 	    patterns.push_back (std::unique_ptr<HIR::Pattern> (p));
! 	  }
  
! 	lowered = new HIR::TupleStructItemsNoRange (std::move (patterns));
        }
        break;
      }
--- 81,125 ----
    auto &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case AST::TupleStructItems::HAS_REST:
        {
! 	AST::TupleStructItemsHasRest &items_has_rest
! 	  = static_cast<AST::TupleStructItemsHasRest &> (items);
! 
! 	std::vector<std::unique_ptr<HIR::Pattern>> lower_patterns;
! 	lower_patterns.reserve (items_has_rest.get_lower_patterns ().size ());
! 	for (auto &pattern_member : items_has_rest.get_lower_patterns ())
! 	  {
! 	    lower_patterns.emplace_back (
! 	      ASTLoweringPattern::translate (*pattern_member));
! 	  }
! 
! 	std::vector<std::unique_ptr<HIR::Pattern>> upper_patterns;
! 	upper_patterns.reserve (items_has_rest.get_upper_patterns ().size ());
! 	for (auto &pattern_member : items_has_rest.get_upper_patterns ())
! 	  {
! 	    upper_patterns.emplace_back (
! 	      ASTLoweringPattern::translate (*pattern_member));
! 	  }
! 
! 	lowered = new HIR::TupleStructItemsHasRest (std::move (lower_patterns),
! 						    std::move (upper_patterns));
        }
        break;
  
!     case AST::TupleStructItems::NO_REST:
        {
! 	AST::TupleStructItemsNoRest &items_no_rest
! 	  = static_cast<AST::TupleStructItemsNoRest &> (items);
  
  	std::vector<std::unique_ptr<HIR::Pattern>> patterns;
! 	patterns.reserve (items_no_rest.get_patterns ().size ());
  
! 	for (auto &inner_pattern : items_no_rest.get_patterns ())
! 	  patterns.emplace_back (
! 	    ASTLoweringPattern::translate (*inner_pattern));
! 
! 	lowered = new HIR::TupleStructItemsNoRest (std::move (patterns));
        }
        break;
      }
*************** ASTLoweringPattern::visit (AST::StructPa
*** 121,127 ****
      = ASTLowerPathInExpression::translate (pattern.get_path ());
  
    auto &raw_elems = pattern.get_struct_pattern_elems ();
-   rust_assert (!raw_elems.has_etc ());
  
    std::vector<std::unique_ptr<HIR::StructPatternField>> fields;
    for (auto &field : raw_elems.get_struct_pattern_fields ())
--- 140,145 ----
*************** ASTLoweringPattern::visit (AST::StructPa
*** 196,202 ****
        mappings.insert_node_to_hir (field_node_id, field_id);
  
        // add it to the lowered fields list
!       fields.push_back (std::unique_ptr<HIR::StructPatternField> (f));
      }
  
    auto crate_num = mappings.get_current_crate ();
--- 214,220 ----
        mappings.insert_node_to_hir (field_node_id, field_id);
  
        // add it to the lowered fields list
!       fields.emplace_back (f);
      }
  
    auto crate_num = mappings.get_current_crate ();
*************** ASTLoweringPattern::visit (AST::StructPa
*** 204,210 ****
  				 mappings.get_next_hir_id (crate_num),
  				 UNKNOWN_LOCAL_DEFID);
  
!   HIR::StructPatternElements elems (std::move (fields));
    translated = new HIR::StructPattern (mapping, *path, std::move (elems));
  }
  
--- 222,229 ----
  				 mappings.get_next_hir_id (crate_num),
  				 UNKNOWN_LOCAL_DEFID);
  
!   HIR::StructPatternElements elems (
!     std::move (fields), pattern.get_struct_pattern_elems ().has_rest ());
    translated = new HIR::StructPattern (mapping, *path, std::move (elems));
  }
  
*************** void
*** 223,243 ****
  ASTLoweringPattern::visit (AST::TuplePattern &pattern)
  {
    std::unique_ptr<HIR::TuplePatternItems> items;
!   switch (pattern.get_items ().get_pattern_type ())
      {
!     case AST::TuplePatternItems::TuplePatternItemType::MULTIPLE:
        {
! 	AST::TuplePatternItemsMultiple &ref
! 	  = static_cast<AST::TuplePatternItemsMultiple &> (
! 	    pattern.get_items ());
  	items = lower_tuple_pattern_multiple (ref);
        }
        break;
  
!     case AST::TuplePatternItems::TuplePatternItemType::RANGED:
        {
! 	AST::TuplePatternItemsRanged &ref
! 	  = static_cast<AST::TuplePatternItemsRanged &> (pattern.get_items ());
  	items = lower_tuple_pattern_ranged (ref);
        }
        break;
--- 242,261 ----
  ASTLoweringPattern::visit (AST::TuplePattern &pattern)
  {
    std::unique_ptr<HIR::TuplePatternItems> items;
!   switch (pattern.get_items ().get_item_type ())
      {
!     case AST::TuplePatternItems::ItemType::NO_REST:
        {
! 	AST::TuplePatternItemsNoRest &ref
! 	  = static_cast<AST::TuplePatternItemsNoRest &> (pattern.get_items ());
  	items = lower_tuple_pattern_multiple (ref);
        }
        break;
  
!     case AST::TuplePatternItems::ItemType::HAS_REST:
        {
! 	AST::TuplePatternItemsHasRest &ref
! 	  = static_cast<AST::TuplePatternItemsHasRest &> (pattern.get_items ());
  	items = lower_tuple_pattern_ranged (ref);
        }
        break;
*************** ASTLoweringPattern::visit (AST::LiteralP
*** 268,275 ****
  void
  ASTLoweringPattern::visit (AST::RangePattern &pattern)
  {
-   if (pattern.get_range_kind () == AST::RangeKind::EXCLUDED)
-     rust_unreachable (); // Not supported yet
    auto upper_bound = lower_range_pattern_bound (pattern.get_upper_bound ());
    auto lower_bound = lower_range_pattern_bound (pattern.get_lower_bound ());
  
--- 286,291 ----
*************** ASTLoweringPattern::visit (AST::RangePat
*** 278,286 ****
  				 mappings.get_next_hir_id (crate_num),
  				 UNKNOWN_LOCAL_DEFID);
  
!   translated
!     = new HIR::RangePattern (mapping, std::move (lower_bound),
! 			     std::move (upper_bound), pattern.get_locus ());
  }
  
  void
--- 294,304 ----
  				 mappings.get_next_hir_id (crate_num),
  				 UNKNOWN_LOCAL_DEFID);
  
!   bool is_inclusive = (pattern.get_range_kind () == AST::RangeKind::INCLUDED);
! 
!   translated = new HIR::RangePattern (mapping, std::move (lower_bound),
! 				      std::move (upper_bound),
! 				      pattern.get_locus (), is_inclusive);
  }
  
  void
*************** ASTLoweringPattern::visit (AST::Referenc
*** 322,347 ****
  void
  ASTLoweringPattern::visit (AST::SlicePattern &pattern)
  {
!   std::vector<std::unique_ptr<HIR::Pattern>> items;
  
!   switch (pattern.get_items ().get_pattern_type ())
      {
!     case AST::SlicePatternItems::SlicePatternItemType::NO_REST:
        {
! 	AST::SlicePatternItemsNoRest &ref
  	  = static_cast<AST::SlicePatternItemsNoRest &> (pattern.get_items ());
! 	for (auto &p : ref.get_patterns ())
! 	  {
! 	    HIR::Pattern *item = ASTLoweringPattern::translate (*p);
! 	    items.push_back (std::unique_ptr<HIR::Pattern> (item));
! 	  }
        }
        break;
!     case AST::SlicePatternItems::SlicePatternItemType::HAS_REST:
        {
! 	rust_error_at (pattern.get_locus (),
! 		       "lowering of slice patterns with rest elements are not "
! 		       "supported yet");
        }
        break;
      }
--- 340,361 ----
  void
  ASTLoweringPattern::visit (AST::SlicePattern &pattern)
  {
!   std::unique_ptr<HIR::SlicePatternItems> items;
  
!   switch (pattern.get_items ().get_item_type ())
      {
!     case AST::SlicePatternItems::ItemType::NO_REST:
        {
! 	auto &ref
  	  = static_cast<AST::SlicePatternItemsNoRest &> (pattern.get_items ());
! 	items = ASTLoweringBase::lower_slice_pattern_no_rest (ref);
        }
        break;
!     case AST::SlicePatternItems::ItemType::HAS_REST:
        {
! 	auto &ref
! 	  = static_cast<AST::SlicePatternItemsHasRest &> (pattern.get_items ());
! 	items = ASTLoweringBase::lower_slice_pattern_has_rest (ref);
        }
        break;
      }
*************** ASTLoweringPattern::visit (AST::AltPatte
*** 364,375 ****
  				 UNKNOWN_LOCAL_DEFID);
  
    std::vector<std::unique_ptr<HIR::Pattern>> alts;
  
    for (auto &alt : pattern.get_alts ())
!     {
!       alts.push_back (
! 	std::unique_ptr<HIR::Pattern> (ASTLoweringPattern::translate (*alt)));
!     }
  
    translated
      = new HIR::AltPattern (mapping, std::move (alts), pattern.get_locus ());
--- 378,387 ----
  				 UNKNOWN_LOCAL_DEFID);
  
    std::vector<std::unique_ptr<HIR::Pattern>> alts;
+   alts.reserve (pattern.get_alts ().size ());
  
    for (auto &alt : pattern.get_alts ())
!     alts.emplace_back (ASTLoweringPattern::translate (*alt));
  
    translated
      = new HIR::AltPattern (mapping, std::move (alts), pattern.get_locus ());
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-ast-lower.cc gcc-16-20251102/gcc/rust/hir/rust-ast-lower.cc
*** gcc-16-20251026/gcc/rust/hir/rust-ast-lower.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-ast-lower.cc	Sun Nov  2 22:32:23 2025
*************** ASTLowering::go ()
*** 80,86 ****
      {
        auto translated = ASTLoweringItem::translate (*item);
        if (translated != nullptr)
! 	items.push_back (std::unique_ptr<HIR::Item> (translated));
      }
  
    auto &mappings = Analysis::Mappings::get ();
--- 80,86 ----
      {
        auto translated = ASTLoweringItem::translate (*item);
        if (translated != nullptr)
! 	items.emplace_back (translated);
      }
  
    auto &mappings = Analysis::Mappings::get ();
*************** ASTLoweringBlock::visit (AST::BlockExpr
*** 127,133 ****
        block_did_terminate |= terminated;
  
        if (translated_stmt)
! 	block_stmts.push_back (std::unique_ptr<HIR::Stmt> (translated_stmt));
      }
  
    if (expr.has_tail_expr () && block_did_terminate)
--- 127,133 ----
        block_did_terminate |= terminated;
  
        if (translated_stmt)
! 	block_stmts.emplace_back (translated_stmt);
      }
  
    if (expr.has_tail_expr () && block_did_terminate)
*************** ASTLoweringIfLetBlock::desugar_iflet (AS
*** 231,236 ****
--- 231,237 ----
  {
    HIR::Expr *kase_expr;
    std::vector<std::unique_ptr<HIR::Pattern>> match_arm_patterns;
+   match_arm_patterns.reserve (expr.get_patterns ().size ());
  
    *branch_value = ASTLoweringExpr::translate (expr.get_value_expr ());
    kase_expr = ASTLoweringExpr::translate (expr.get_if_block ());
*************** ASTLoweringIfLetBlock::desugar_iflet (AS
*** 241,250 ****
    rust_assert (expr.get_patterns ().size () == 1);
  
    for (auto &pattern : expr.get_patterns ())
!     {
!       HIR::Pattern *ptrn = ASTLoweringPattern::translate (*pattern);
!       match_arm_patterns.push_back (std::unique_ptr<HIR::Pattern> (ptrn));
!     }
  
    // The match arm corresponding to the if let pattern when it matches.
    HIR::MatchArm arm (std::move (match_arm_patterns), expr.get_locus (), nullptr,
--- 242,248 ----
    rust_assert (expr.get_patterns ().size () == 1);
  
    for (auto &pattern : expr.get_patterns ())
!     match_arm_patterns.emplace_back (ASTLoweringPattern::translate (*pattern));
  
    // The match arm corresponding to the if let pattern when it matches.
    HIR::MatchArm arm (std::move (match_arm_patterns), expr.get_locus (), nullptr,
*************** ASTLoweringIfLetBlock::desugar_iflet (AS
*** 255,263 ****
  				 mappings.get_next_hir_id (crate_num),
  				 UNKNOWN_LOCAL_DEFID);
  
!   HIR::MatchCase kase (std::move (mapping), std::move (arm),
! 		       std::unique_ptr<HIR::Expr> (kase_expr));
!   match_arms.push_back (std::move (kase));
  
    // The default match arm when the if let pattern does not match
    std::vector<std::unique_ptr<HIR::Pattern>> match_arm_patterns_wildcard;
--- 253,260 ----
  				 mappings.get_next_hir_id (crate_num),
  				 UNKNOWN_LOCAL_DEFID);
  
!   match_arms.emplace_back (std::move (mapping), std::move (arm),
! 			   std::unique_ptr<HIR::Expr> (kase_expr));
  
    // The default match arm when the if let pattern does not match
    std::vector<std::unique_ptr<HIR::Pattern>> match_arm_patterns_wildcard;
*************** ASTLoweringIfLetBlock::desugar_iflet (AS
*** 265,283 ****
  					 mappings.get_next_hir_id (crate_num),
  					 UNKNOWN_LOCAL_DEFID);
  
!   std::unique_ptr<HIR::WildcardPattern> wc
!     = std::unique_ptr<HIR::WildcardPattern> (
!       new HIR::WildcardPattern (mapping_default, expr.get_locus ()));
! 
!   match_arm_patterns_wildcard.push_back (std::move (wc));
  
    HIR::MatchArm arm_default (std::move (match_arm_patterns_wildcard),
  			     expr.get_locus (), nullptr, {});
  
!   HIR::MatchCase kase_else (std::move (mapping_default),
! 			    std::move (arm_default),
! 			    std::unique_ptr<HIR::Expr> (kase_else_expr));
!   match_arms.push_back (std::move (kase_else));
  }
  
  void
--- 262,275 ----
  					 mappings.get_next_hir_id (crate_num),
  					 UNKNOWN_LOCAL_DEFID);
  
!   match_arm_patterns_wildcard.emplace_back (
!     new HIR::WildcardPattern (mapping_default, expr.get_locus ()));
  
    HIR::MatchArm arm_default (std::move (match_arm_patterns_wildcard),
  			     expr.get_locus (), nullptr, {});
  
!   match_arms.emplace_back (std::move (mapping_default), std::move (arm_default),
! 			   std::unique_ptr<HIR::Expr> (kase_else_expr));
  }
  
  void
*************** ASTLoweringExprWithBlock::visit (AST::Ma
*** 442,452 ****
  	}
  
        std::vector<std::unique_ptr<HIR::Pattern>> match_arm_patterns;
        for (auto &pattern : match_case.get_arm ().get_patterns ())
! 	{
! 	  HIR::Pattern *ptrn = ASTLoweringPattern::translate (*pattern);
! 	  match_arm_patterns.push_back (std::unique_ptr<HIR::Pattern> (ptrn));
! 	}
  
        HIR::MatchArm arm (std::move (match_arm_patterns), expr.get_locus (),
  			 std::unique_ptr<HIR::Expr> (kase_guard_expr),
--- 434,445 ----
  	}
  
        std::vector<std::unique_ptr<HIR::Pattern>> match_arm_patterns;
+       match_arm_patterns.reserve (
+ 	match_case.get_arm ().get_patterns ().size ());
+ 
        for (auto &pattern : match_case.get_arm ().get_patterns ())
! 	match_arm_patterns.emplace_back (
! 	  ASTLoweringPattern::translate (*pattern));
  
        HIR::MatchArm arm (std::move (match_arm_patterns), expr.get_locus (),
  			 std::unique_ptr<HIR::Expr> (kase_guard_expr),
*************** ASTLoweringExprWithBlock::visit (AST::Ma
*** 457,465 ****
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       HIR::MatchCase kase (std::move (mapping), std::move (arm),
! 			   std::unique_ptr<HIR::Expr> (kase_expr));
!       match_arms.push_back (std::move (kase));
      }
  
    auto crate_num = mappings.get_current_crate ();
--- 450,457 ----
  				     mappings.get_next_hir_id (crate_num),
  				     UNKNOWN_LOCAL_DEFID);
  
!       match_arms.emplace_back (std::move (mapping), std::move (arm),
! 			       std::unique_ptr<HIR::Expr> (kase_expr));
      }
  
    auto crate_num = mappings.get_current_crate ();
*************** ASTLowerPathInExpression::visit (AST::Pa
*** 490,497 ****
        return;
      }
  
-   std::vector<HIR::PathExprSegment> path_segments;
    auto &segments = expr.get_segments ();
    for (auto &s : segments)
      {
        path_segments.push_back (lower_path_expr_seg ((s)));
--- 482,492 ----
        return;
      }
  
    auto &segments = expr.get_segments ();
+ 
+   std::vector<HIR::PathExprSegment> path_segments;
+   path_segments.reserve (segments.size ());
+ 
    for (auto &s : segments)
      {
        path_segments.push_back (lower_path_expr_seg ((s)));
*************** ASTLowerQualPathInExpression::visit (AST
*** 531,538 ****
    HIR::QualifiedPathType qual_path_type
      = lower_qual_path_type (expr.get_qualified_path_type ());
  
-   std::vector<HIR::PathExprSegment> path_segments;
    auto &segments = expr.get_segments ();
    for (auto &s : segments)
      {
        path_segments.push_back (lower_path_expr_seg ((s)));
--- 526,536 ----
    HIR::QualifiedPathType qual_path_type
      = lower_qual_path_type (expr.get_qualified_path_type ());
  
    auto &segments = expr.get_segments ();
+ 
+   std::vector<HIR::PathExprSegment> path_segments;
+   path_segments.reserve (segments.size ());
+ 
    for (auto &s : segments)
      {
        path_segments.push_back (lower_path_expr_seg ((s)));
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-hir-dump.cc gcc-16-20251102/gcc/rust/hir/rust-hir-dump.cc
*** gcc-16-20251026/gcc/rust/hir/rust-hir-dump.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-hir-dump.cc	Sun Nov  2 22:32:23 2025
*************** Dump::visit (StructPattern &e)
*** 2307,2326 ****
  }
  
  void
! Dump::visit (TupleStructItemsNoRange &e)
  {
!   begin ("TupleStructItemsNoRange");
    visit_collection ("patterns", e.get_patterns ());
!   end ("TupleStructItemsNoRange");
  }
  
  void
! Dump::visit (TupleStructItemsRange &e)
  {
!   begin ("TupleStructItemsRange");
    visit_collection ("lower_patterns", e.get_lower_patterns ());
    visit_collection ("upper_patterns", e.get_upper_patterns ());
!   end ("TupleStructItemsRange");
  }
  
  void
--- 2307,2326 ----
  }
  
  void
! Dump::visit (TupleStructItemsNoRest &e)
  {
!   begin ("TupleStructItemsNoRest");
    visit_collection ("patterns", e.get_patterns ());
!   end ("TupleStructItemsNoRest");
  }
  
  void
! Dump::visit (TupleStructItemsHasRest &e)
  {
!   begin ("TupleStructItemsHasRest");
    visit_collection ("lower_patterns", e.get_lower_patterns ());
    visit_collection ("upper_patterns", e.get_upper_patterns ());
!   end ("TupleStructItemsHasRest");
  }
  
  void
*************** Dump::visit (TupleStructPattern &e)
*** 2337,2356 ****
  }
  
  void
! Dump::visit (TuplePatternItemsMultiple &e)
  {
!   begin ("TuplePatternItemsMultiple");
    visit_collection ("patterns", e.get_patterns ());
!   end ("TuplePatternItemsMultiple");
  }
  
  void
! Dump::visit (TuplePatternItemsRanged &e)
  {
!   begin ("TuplePatternItemsRanged");
    visit_collection ("lower_patterns", e.get_lower_patterns ());
    visit_collection ("upper_patterns", e.get_upper_patterns ());
!   end ("TuplePatternItemsRanged");
  }
  
  void
--- 2337,2356 ----
  }
  
  void
! Dump::visit (TuplePatternItemsNoRest &e)
  {
!   begin ("TuplePatternItemsNoRest");
    visit_collection ("patterns", e.get_patterns ());
!   end ("TuplePatternItemsNoRest");
  }
  
  void
! Dump::visit (TuplePatternItemsHasRest &e)
  {
!   begin ("TuplePatternItemsHasRest");
    visit_collection ("lower_patterns", e.get_lower_patterns ());
    visit_collection ("upper_patterns", e.get_upper_patterns ());
!   end ("TuplePatternItemsHasRest");
  }
  
  void
*************** Dump::visit (TuplePattern &e)
*** 2363,2373 ****
  }
  
  void
  Dump::visit (SlicePattern &e)
  {
    begin ("SlicePattern");
    do_mappings (e.get_mappings ());
!   visit_collection ("items", e.get_items ());
    end ("SlicePattern");
  }
  
--- 2363,2390 ----
  }
  
  void
+ Dump::visit (SlicePatternItemsNoRest &e)
+ {
+   begin ("SlicePatternItemsNoRest");
+   visit_collection ("patterns", e.get_patterns ());
+   end ("SlicePatternItemsNoRest");
+ }
+ 
+ void
+ Dump::visit (SlicePatternItemsHasRest &e)
+ {
+   begin ("SlicePatternItemsHasRest");
+   visit_collection ("lower_patterns", e.get_lower_patterns ());
+   visit_collection ("upper_patterns", e.get_upper_patterns ());
+   end ("SlicePatternItemsHasRest");
+ }
+ 
+ void
  Dump::visit (SlicePattern &e)
  {
    begin ("SlicePattern");
    do_mappings (e.get_mappings ());
!   visit_field ("items", e.get_items ());
    end ("SlicePattern");
  }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/rust-hir-dump.h gcc-16-20251102/gcc/rust/hir/rust-hir-dump.h
*** gcc-16-20251026/gcc/rust/hir/rust-hir-dump.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/rust-hir-dump.h	Sun Nov  2 22:32:23 2025
*************** private:
*** 223,236 ****
    virtual void visit (StructPatternFieldIdent &) override;
    virtual void visit (StructPattern &) override;
  
!   virtual void visit (TupleStructItemsNoRange &) override;
!   virtual void visit (TupleStructItemsRange &) override;
    virtual void visit (TupleStructPattern &) override;
  
!   virtual void visit (TuplePatternItemsMultiple &) override;
!   virtual void visit (TuplePatternItemsRanged &) override;
    virtual void visit (TuplePattern &) override;
    virtual void visit (SlicePattern &) override;
    virtual void visit (AltPattern &) override;
  
    virtual void visit (EmptyStmt &) override;
--- 223,240 ----
    virtual void visit (StructPatternFieldIdent &) override;
    virtual void visit (StructPattern &) override;
  
!   virtual void visit (TupleStructItemsNoRest &) override;
!   virtual void visit (TupleStructItemsHasRest &) override;
    virtual void visit (TupleStructPattern &) override;
  
!   virtual void visit (TuplePatternItemsNoRest &) override;
!   virtual void visit (TuplePatternItemsHasRest &) override;
    virtual void visit (TuplePattern &) override;
+ 
+   virtual void visit (SlicePatternItemsNoRest &) override;
+   virtual void visit (SlicePatternItemsHasRest &) override;
    virtual void visit (SlicePattern &) override;
+ 
    virtual void visit (AltPattern &) override;
  
    virtual void visit (EmptyStmt &) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/tree/rust-hir-full-decls.h gcc-16-20251102/gcc/rust/hir/tree/rust-hir-full-decls.h
*** gcc-16-20251026/gcc/rust/hir/tree/rust-hir-full-decls.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/tree/rust-hir-full-decls.h	Sun Nov  2 22:32:23 2025
*************** class StructPatternFieldIdentPat;
*** 199,211 ****
  class StructPatternFieldIdent;
  class StructPattern;
  class TupleStructItems;
! class TupleStructItemsNoRange;
! class TupleStructItemsRange;
  class TupleStructPattern;
  class TuplePatternItems;
! class TuplePatternItemsMultiple;
! class TuplePatternItemsRanged;
  class TuplePattern;
  class SlicePattern;
  class AltPattern;
  
--- 199,213 ----
  class StructPatternFieldIdent;
  class StructPattern;
  class TupleStructItems;
! class TupleStructItemsNoRest;
! class TupleStructItemsHasRest;
  class TupleStructPattern;
  class TuplePatternItems;
! class TuplePatternItemsNoRest;
! class TuplePatternItemsHasRest;
  class TuplePattern;
+ class SlicePatternItemsNoRest;
+ class SlicePatternItemsHasRest;
  class SlicePattern;
  class AltPattern;
  
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/tree/rust-hir-item.h gcc-16-20251102/gcc/rust/hir/tree/rust-hir-item.h
*** gcc-16-20251026/gcc/rust/hir/tree/rust-hir-item.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/tree/rust-hir-item.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 452,457 ****
--- 452,458 ----
    bool is_unsafe () const { return unsafety == Unsafety::Unsafe; }
    bool is_async () const { return async_status == Async::Yes; }
  
+   Unsafety get_unsafety () const { return unsafety; }
    ABI get_abi () const { return abi; }
  };
  
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/tree/rust-hir-pattern.h gcc-16-20251102/gcc/rust/hir/tree/rust-hir-pattern.h
*** gcc-16-20251026/gcc/rust/hir/tree/rust-hir-pattern.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/tree/rust-hir-pattern.h	Sun Nov  2 22:32:23 2025
*************** class RangePattern : public Pattern
*** 350,355 ****
--- 350,356 ----
    /* location only stored to avoid a dereference - lower pattern should give
     * correct location so maybe change in future */
    location_t locus;
+   bool is_inclusive;
    Analysis::NodeMapping mappings;
  
  public:
*************** public:
*** 359,368 ****
    RangePattern (Analysis::NodeMapping mappings,
  		std::unique_ptr<RangePatternBound> lower,
  		std::unique_ptr<RangePatternBound> upper, location_t locus,
! 		bool has_ellipsis_syntax = false)
      : lower (std::move (lower)), upper (std::move (upper)),
        has_ellipsis_syntax (has_ellipsis_syntax), locus (locus),
!       mappings (mappings)
    {}
  
    // Copy constructor with clone
--- 360,369 ----
    RangePattern (Analysis::NodeMapping mappings,
  		std::unique_ptr<RangePatternBound> lower,
  		std::unique_ptr<RangePatternBound> upper, location_t locus,
! 		bool is_inclusive, bool has_ellipsis_syntax = false)
      : lower (std::move (lower)), upper (std::move (upper)),
        has_ellipsis_syntax (has_ellipsis_syntax), locus (locus),
!       is_inclusive (is_inclusive), mappings (mappings)
    {}
  
    // Copy constructor with clone
*************** public:
*** 370,376 ****
      : lower (other.lower->clone_range_pattern_bound ()),
        upper (other.upper->clone_range_pattern_bound ()),
        has_ellipsis_syntax (other.has_ellipsis_syntax), locus (other.locus),
!       mappings (other.mappings)
    {}
  
    // Overloaded assignment operator to clone
--- 371,377 ----
      : lower (other.lower->clone_range_pattern_bound ()),
        upper (other.upper->clone_range_pattern_bound ()),
        has_ellipsis_syntax (other.has_ellipsis_syntax), locus (other.locus),
!       is_inclusive (other.is_inclusive), mappings (other.mappings)
    {}
  
    // Overloaded assignment operator to clone
*************** public:
*** 380,385 ****
--- 381,387 ----
      upper = other.upper->clone_range_pattern_bound ();
      has_ellipsis_syntax = other.has_ellipsis_syntax;
      locus = other.locus;
+     is_inclusive = other.is_inclusive;
      mappings = other.mappings;
  
      return *this;
*************** public:
*** 395,400 ****
--- 397,403 ----
    void accept_vis (HIRPatternVisitor &vis) override;
  
    bool get_has_ellipsis_syntax () { return has_ellipsis_syntax; };
+   bool is_inclusive_range () const { return is_inclusive; }
  
    const Analysis::NodeMapping &get_mappings () const override final
    {
*************** protected:
*** 680,685 ****
--- 683,689 ----
  class StructPatternElements
  {
    std::vector<std::unique_ptr<StructPatternField>> fields;
+   bool has_rest_pattern;
  
  public:
    // Returns whether there are any struct pattern fields
*************** public:
*** 689,698 ****
     * no etc). */
    bool is_empty () const { return !has_struct_pattern_fields (); }
  
    // Constructor for StructPatternElements with both (potentially)
    StructPatternElements (
      std::vector<std::unique_ptr<StructPatternField>> fields)
!     : fields (std::move (fields))
    {}
  
    // Copy constructor with vector clone
--- 693,710 ----
     * no etc). */
    bool is_empty () const { return !has_struct_pattern_fields (); }
  
+   bool has_rest () const { return has_rest_pattern; }
+ 
    // Constructor for StructPatternElements with both (potentially)
    StructPatternElements (
      std::vector<std::unique_ptr<StructPatternField>> fields)
!     : fields (std::move (fields)), has_rest_pattern (false)
!   {}
! 
!   StructPatternElements (
!     std::vector<std::unique_ptr<StructPatternField>> fields,
!     bool has_rest_pattern)
!     : fields (std::move (fields)), has_rest_pattern (has_rest_pattern)
    {}
  
    // Copy constructor with vector clone
*************** public:
*** 700,706 ****
    {
      fields.reserve (other.fields.size ());
      for (const auto &e : other.fields)
!       fields.push_back (e->clone_struct_pattern_field ());
    }
  
    // Overloaded assignment operator with vector clone
--- 712,719 ----
    {
      fields.reserve (other.fields.size ());
      for (const auto &e : other.fields)
!       fields.emplace_back (e->clone_struct_pattern_field ());
!     has_rest_pattern = other.has_rest_pattern;
    }
  
    // Overloaded assignment operator with vector clone
*************** public:
*** 709,716 ****
      fields.clear ();
      fields.reserve (other.fields.size ());
      for (const auto &e : other.fields)
!       fields.push_back (e->clone_struct_pattern_field ());
! 
      return *this;
    }
  
--- 722,729 ----
      fields.clear ();
      fields.reserve (other.fields.size ());
      for (const auto &e : other.fields)
!       fields.emplace_back (e->clone_struct_pattern_field ());
!     has_rest_pattern = other.has_rest_pattern;
      return *this;
    }
  
*************** protected:
*** 778,801 ****
    }
  };
  
! // Base abstract class for TupleStructItems and TuplePatternItems
! class TupleItems : public FullVisitable
  {
  public:
    enum ItemType
    {
!     MULTIPLE,
!     RANGED,
    };
  
!   virtual ~TupleItems () {}
  
    // TODO: should this store location data?
  
    // Unique pointer custom clone function
!   std::unique_ptr<TupleItems> clone_tuple_items () const
    {
!     return std::unique_ptr<TupleItems> (clone_tuple_items_impl ());
    }
  
    virtual ItemType get_item_type () const = 0;
--- 791,815 ----
    }
  };
  
! // Base abstract class for TupleStructItems, TuplePatternItems &
! // SlicePatternItems
! class PatternItems : public FullVisitable
  {
  public:
    enum ItemType
    {
!     NO_REST,
!     HAS_REST,
    };
  
!   virtual ~PatternItems () {}
  
    // TODO: should this store location data?
  
    // Unique pointer custom clone function
!   std::unique_ptr<PatternItems> clone_pattern_items () const
    {
!     return std::unique_ptr<PatternItems> (clone_pattern_items_impl ());
    }
  
    virtual ItemType get_item_type () const = 0;
*************** public:
*** 804,839 ****
  
  protected:
    // pure virtual clone implementation
!   virtual TupleItems *clone_tuple_items_impl () const = 0;
  };
  
  // Base abstract class for patterns used in TupleStructPattern
! class TupleStructItems : public TupleItems
  {
  public:
    // Unique pointer custom clone function
    std::unique_ptr<TupleStructItems> clone_tuple_struct_items () const
    {
!     return std::unique_ptr<TupleStructItems> (clone_tuple_items_impl ());
    }
  
  protected:
    // pure virtual clone implementation
!   virtual TupleStructItems *clone_tuple_items_impl () const override = 0;
  };
  
! // Class for non-ranged tuple struct pattern patterns
! class TupleStructItemsNoRange : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TupleStructItemsNoRange (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsNoRange (TupleStructItemsNoRange const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
--- 818,853 ----
  
  protected:
    // pure virtual clone implementation
!   virtual PatternItems *clone_pattern_items_impl () const = 0;
  };
  
  // Base abstract class for patterns used in TupleStructPattern
! class TupleStructItems : public PatternItems
  {
  public:
    // Unique pointer custom clone function
    std::unique_ptr<TupleStructItems> clone_tuple_struct_items () const
    {
!     return std::unique_ptr<TupleStructItems> (clone_pattern_items_impl ());
    }
  
  protected:
    // pure virtual clone implementation
!   virtual TupleStructItems *clone_pattern_items_impl () const override = 0;
  };
  
! // Class for patterns within a tuple struct pattern, without a rest pattern
! class TupleStructItemsNoRest : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TupleStructItemsNoRest (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsNoRest (TupleStructItemsNoRest const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
*************** public:
*** 841,847 ****
    }
  
    // Overloaded assignment operator with vector clone
!   TupleStructItemsNoRange &operator= (TupleStructItemsNoRange const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
--- 855,861 ----
    }
  
    // Overloaded assignment operator with vector clone
!   TupleStructItemsNoRest &operator= (TupleStructItemsNoRest const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
*************** public:
*** 852,860 ****
    }
  
    // move constructors
!   TupleStructItemsNoRange (TupleStructItemsNoRange &&other) = default;
!   TupleStructItemsNoRange &operator= (TupleStructItemsNoRange &&other)
!     = default;
  
    std::string as_string () const override;
  
--- 866,873 ----
    }
  
    // move constructors
!   TupleStructItemsNoRest (TupleStructItemsNoRest &&other) = default;
!   TupleStructItemsNoRest &operator= (TupleStructItemsNoRest &&other) = default;
  
    std::string as_string () const override;
  
*************** public:
*** 866,897 ****
      return patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::MULTIPLE; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsNoRange *clone_tuple_items_impl () const override
    {
!     return new TupleStructItemsNoRange (*this);
    }
  };
  
! // Class for ranged tuple struct pattern patterns
! class TupleStructItemsRange : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TupleStructItemsRange (std::vector<std::unique_ptr<Pattern>> lower_patterns,
! 			 std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsRange (TupleStructItemsRange const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
--- 879,911 ----
      return patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::NO_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsNoRest *clone_pattern_items_impl () const override
    {
!     return new TupleStructItemsNoRest (*this);
    }
  };
  
! // Class for patterns within a tuple struct pattern, with a rest pattern
! // included
! class TupleStructItemsHasRest : public TupleStructItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TupleStructItemsHasRest (std::vector<std::unique_ptr<Pattern>> lower_patterns,
! 			   std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TupleStructItemsHasRest (TupleStructItemsHasRest const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
*************** public:
*** 903,909 ****
    }
  
    // Overloaded assignment operator to clone
!   TupleStructItemsRange &operator= (TupleStructItemsRange const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
--- 917,923 ----
    }
  
    // Overloaded assignment operator to clone
!   TupleStructItemsHasRest &operator= (TupleStructItemsHasRest const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
*************** public:
*** 919,926 ****
    }
  
    // move constructors
!   TupleStructItemsRange (TupleStructItemsRange &&other) = default;
!   TupleStructItemsRange &operator= (TupleStructItemsRange &&other) = default;
  
    std::string as_string () const override;
  
--- 933,941 ----
    }
  
    // move constructors
!   TupleStructItemsHasRest (TupleStructItemsHasRest &&other) = default;
!   TupleStructItemsHasRest &operator= (TupleStructItemsHasRest &&other)
!     = default;
  
    std::string as_string () const override;
  
*************** public:
*** 945,958 ****
      return upper_patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::RANGED; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsRange *clone_tuple_items_impl () const override
    {
!     return new TupleStructItemsRange (*this);
    }
  };
  
--- 960,973 ----
      return upper_patterns;
    }
  
!   ItemType get_item_type () const override final { return ItemType::HAS_REST; }
  
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TupleStructItemsHasRest *clone_pattern_items_impl () const override
    {
!     return new TupleStructItemsHasRest (*this);
    }
  };
  
*************** protected:
*** 1025,1056 ****
  };
  
  // Base abstract class representing TuplePattern patterns
! class TuplePatternItems : public TupleItems
  {
  public:
    // Unique pointer custom clone function
    std::unique_ptr<TuplePatternItems> clone_tuple_pattern_items () const
    {
!     return std::unique_ptr<TuplePatternItems> (clone_tuple_items_impl ());
    }
  
  protected:
    // pure virtual clone implementation
!   virtual TuplePatternItems *clone_tuple_items_impl () const override = 0;
  };
  
! // Class representing TuplePattern patterns where there are multiple patterns
! class TuplePatternItemsMultiple : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TuplePatternItemsMultiple (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsMultiple (TuplePatternItemsMultiple const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
--- 1040,1071 ----
  };
  
  // Base abstract class representing TuplePattern patterns
! class TuplePatternItems : public PatternItems
  {
  public:
    // Unique pointer custom clone function
    std::unique_ptr<TuplePatternItems> clone_tuple_pattern_items () const
    {
!     return std::unique_ptr<TuplePatternItems> (clone_pattern_items_impl ());
    }
  
  protected:
    // pure virtual clone implementation
!   virtual TuplePatternItems *clone_pattern_items_impl () const override = 0;
  };
  
! // Class representing patterns within a TuplePattern, without a rest pattern
! class TuplePatternItemsNoRest : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> patterns;
  
  public:
!   TuplePatternItemsNoRest (std::vector<std::unique_ptr<Pattern>> patterns)
      : patterns (std::move (patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsNoRest (TuplePatternItemsNoRest const &other)
    {
      patterns.reserve (other.patterns.size ());
      for (const auto &e : other.patterns)
*************** public:
*** 1058,1064 ****
    }
  
    // Overloaded assignment operator to vector clone
!   TuplePatternItemsMultiple &operator= (TuplePatternItemsMultiple const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
--- 1073,1079 ----
    }
  
    // Overloaded assignment operator to vector clone
!   TuplePatternItemsNoRest &operator= (TuplePatternItemsNoRest const &other)
    {
      patterns.clear ();
      patterns.reserve (other.patterns.size ());
*************** public:
*** 1069,1083 ****
    }
  
    // move constructors
!   TuplePatternItemsMultiple (TuplePatternItemsMultiple &&other) = default;
!   TuplePatternItemsMultiple &operator= (TuplePatternItemsMultiple &&other)
      = default;
  
    std::string as_string () const override;
  
    void accept_vis (HIRFullVisitor &vis) override;
  
!   ItemType get_item_type () const override { return ItemType::MULTIPLE; }
  
    std::vector<std::unique_ptr<Pattern>> &get_patterns () { return patterns; }
    const std::vector<std::unique_ptr<Pattern>> &get_patterns () const
--- 1084,1098 ----
    }
  
    // move constructors
!   TuplePatternItemsNoRest (TuplePatternItemsNoRest &&other) = default;
!   TuplePatternItemsNoRest &operator= (TuplePatternItemsNoRest &&other)
      = default;
  
    std::string as_string () const override;
  
    void accept_vis (HIRFullVisitor &vis) override;
  
!   ItemType get_item_type () const override { return ItemType::NO_REST; }
  
    std::vector<std::unique_ptr<Pattern>> &get_patterns () { return patterns; }
    const std::vector<std::unique_ptr<Pattern>> &get_patterns () const
*************** public:
*** 1088,1114 ****
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsMultiple *clone_tuple_items_impl () const override
    {
!     return new TuplePatternItemsMultiple (*this);
    }
  };
  
! // Class representing TuplePattern patterns where there are a range of patterns
! class TuplePatternItemsRanged : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TuplePatternItemsRanged (std::vector<std::unique_ptr<Pattern>> lower_patterns,
! 			   std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsRanged (TuplePatternItemsRanged const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
--- 1103,1131 ----
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsNoRest *clone_pattern_items_impl () const override
    {
!     return new TuplePatternItemsNoRest (*this);
    }
  };
  
! // Class representing patterns within a TuplePattern, with a rest pattern
! // included
! class TuplePatternItemsHasRest : public TuplePatternItems
  {
    std::vector<std::unique_ptr<Pattern>> lower_patterns;
    std::vector<std::unique_ptr<Pattern>> upper_patterns;
  
  public:
!   TuplePatternItemsHasRest (
!     std::vector<std::unique_ptr<Pattern>> lower_patterns,
!     std::vector<std::unique_ptr<Pattern>> upper_patterns)
      : lower_patterns (std::move (lower_patterns)),
        upper_patterns (std::move (upper_patterns))
    {}
  
    // Copy constructor with vector clone
!   TuplePatternItemsHasRest (TuplePatternItemsHasRest const &other)
    {
      lower_patterns.reserve (other.lower_patterns.size ());
      for (const auto &e : other.lower_patterns)
*************** public:
*** 1120,1126 ****
    }
  
    // Overloaded assignment operator to clone
!   TuplePatternItemsRanged &operator= (TuplePatternItemsRanged const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
--- 1137,1143 ----
    }
  
    // Overloaded assignment operator to clone
!   TuplePatternItemsHasRest &operator= (TuplePatternItemsHasRest const &other)
    {
      lower_patterns.clear ();
      lower_patterns.reserve (other.lower_patterns.size ());
*************** public:
*** 1136,1150 ****
    }
  
    // move constructors
!   TuplePatternItemsRanged (TuplePatternItemsRanged &&other) = default;
!   TuplePatternItemsRanged &operator= (TuplePatternItemsRanged &&other)
      = default;
  
    std::string as_string () const override;
  
    void accept_vis (HIRFullVisitor &vis) override;
  
!   ItemType get_item_type () const override { return ItemType::RANGED; }
  
    std::vector<std::unique_ptr<Pattern>> &get_lower_patterns ()
    {
--- 1153,1167 ----
    }
  
    // move constructors
!   TuplePatternItemsHasRest (TuplePatternItemsHasRest &&other) = default;
!   TuplePatternItemsHasRest &operator= (TuplePatternItemsHasRest &&other)
      = default;
  
    std::string as_string () const override;
  
    void accept_vis (HIRFullVisitor &vis) override;
  
!   ItemType get_item_type () const override { return ItemType::HAS_REST; }
  
    std::vector<std::unique_ptr<Pattern>> &get_lower_patterns ()
    {
*************** public:
*** 1167,1175 ****
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsRanged *clone_tuple_items_impl () const override
    {
!     return new TuplePatternItemsRanged (*this);
    }
  };
  
--- 1184,1192 ----
  protected:
    /* Use covariance to implement clone function as returning this object rather
     * than base */
!   TuplePatternItemsHasRest *clone_pattern_items_impl () const override
    {
!     return new TuplePatternItemsHasRest (*this);
    }
  };
  
*************** protected:
*** 1234,1243 ****
    }
  };
  
  // HIR node representing patterns that can match slices and arrays
  class SlicePattern : public Pattern
  {
!   std::vector<std::unique_ptr<Pattern>> items;
    location_t locus;
    Analysis::NodeMapping mappings;
  
--- 1251,1411 ----
    }
  };
  
+ // Base abstract class representing SlicePattern patterns
+ class SlicePatternItems : public PatternItems
+ {
+ public:
+   // Unique pointer custom clone function
+   std::unique_ptr<SlicePatternItems> clone_slice_pattern_items () const
+   {
+     return std::unique_ptr<SlicePatternItems> (clone_pattern_items_impl ());
+   }
+ 
+ protected:
+   // pure virtual clone implementation
+   virtual SlicePatternItems *clone_pattern_items_impl () const override = 0;
+ };
+ 
+ // Class representing patterns within a SlicePattern, without a rest pattern
+ class SlicePatternItemsNoRest : public SlicePatternItems
+ {
+   std::vector<std::unique_ptr<Pattern>> patterns;
+ 
+ public:
+   SlicePatternItemsNoRest (std::vector<std::unique_ptr<Pattern>> patterns)
+     : patterns (std::move (patterns))
+   {}
+ 
+   // Copy constructor with vector clone
+   SlicePatternItemsNoRest (SlicePatternItemsNoRest const &other)
+   {
+     patterns.reserve (other.patterns.size ());
+     for (const auto &e : other.patterns)
+       patterns.push_back (e->clone_pattern ());
+   }
+ 
+   // Overloaded assignment operator to vector clone
+   SlicePatternItemsNoRest &operator= (SlicePatternItemsNoRest const &other)
+   {
+     patterns.clear ();
+     patterns.reserve (other.patterns.size ());
+     for (const auto &e : other.patterns)
+       patterns.push_back (e->clone_pattern ());
+ 
+     return *this;
+   }
+ 
+   // move constructors
+   SlicePatternItemsNoRest (SlicePatternItemsNoRest &&other) = default;
+   SlicePatternItemsNoRest &operator= (SlicePatternItemsNoRest &&other)
+     = default;
+ 
+   std::string as_string () const override;
+ 
+   void accept_vis (HIRFullVisitor &vis) override;
+ 
+   ItemType get_item_type () const override { return ItemType::NO_REST; }
+ 
+   std::vector<std::unique_ptr<Pattern>> &get_patterns () { return patterns; }
+   const std::vector<std::unique_ptr<Pattern>> &get_patterns () const
+   {
+     return patterns;
+   }
+ 
+ protected:
+   /* Use covariance to implement clone function as returning this object rather
+    * than base */
+   SlicePatternItemsNoRest *clone_pattern_items_impl () const override
+   {
+     return new SlicePatternItemsNoRest (*this);
+   }
+ };
+ 
+ // Class representing patterns within a SlicePattern, with a rest pattern
+ // included
+ class SlicePatternItemsHasRest : public SlicePatternItems
+ {
+   std::vector<std::unique_ptr<Pattern>> lower_patterns;
+   std::vector<std::unique_ptr<Pattern>> upper_patterns;
+ 
+ public:
+   SlicePatternItemsHasRest (
+     std::vector<std::unique_ptr<Pattern>> lower_patterns,
+     std::vector<std::unique_ptr<Pattern>> upper_patterns)
+     : lower_patterns (std::move (lower_patterns)),
+       upper_patterns (std::move (upper_patterns))
+   {}
+ 
+   // Copy constructor with vector clone
+   SlicePatternItemsHasRest (SlicePatternItemsHasRest const &other)
+   {
+     lower_patterns.reserve (other.lower_patterns.size ());
+     for (const auto &e : other.lower_patterns)
+       lower_patterns.push_back (e->clone_pattern ());
+ 
+     upper_patterns.reserve (other.upper_patterns.size ());
+     for (const auto &e : other.upper_patterns)
+       upper_patterns.push_back (e->clone_pattern ());
+   }
+ 
+   // Overloaded assignment operator to clone
+   SlicePatternItemsHasRest &operator= (SlicePatternItemsHasRest const &other)
+   {
+     lower_patterns.clear ();
+     lower_patterns.reserve (other.lower_patterns.size ());
+     for (const auto &e : other.lower_patterns)
+       lower_patterns.push_back (e->clone_pattern ());
+ 
+     lower_patterns.clear ();
+     upper_patterns.reserve (other.upper_patterns.size ());
+     for (const auto &e : other.upper_patterns)
+       upper_patterns.push_back (e->clone_pattern ());
+ 
+     return *this;
+   }
+ 
+   // move constructors
+   SlicePatternItemsHasRest (SlicePatternItemsHasRest &&other) = default;
+   SlicePatternItemsHasRest &operator= (SlicePatternItemsHasRest &&other)
+     = default;
+ 
+   std::string as_string () const override;
+ 
+   void accept_vis (HIRFullVisitor &vis) override;
+ 
+   ItemType get_item_type () const override { return ItemType::HAS_REST; }
+ 
+   std::vector<std::unique_ptr<Pattern>> &get_lower_patterns ()
+   {
+     return lower_patterns;
+   }
+   const std::vector<std::unique_ptr<Pattern>> &get_lower_patterns () const
+   {
+     return lower_patterns;
+   }
+ 
+   std::vector<std::unique_ptr<Pattern>> &get_upper_patterns ()
+   {
+     return upper_patterns;
+   }
+   const std::vector<std::unique_ptr<Pattern>> &get_upper_patterns () const
+   {
+     return upper_patterns;
+   }
+ 
+ protected:
+   /* Use covariance to implement clone function as returning this object rather
+    * than base */
+   SlicePatternItemsHasRest *clone_pattern_items_impl () const override
+   {
+     return new SlicePatternItemsHasRest (*this);
+   }
+ };
+ 
  // HIR node representing patterns that can match slices and arrays
  class SlicePattern : public Pattern
  {
!   std::unique_ptr<SlicePatternItems> items;
    location_t locus;
    Analysis::NodeMapping mappings;
  
*************** public:
*** 1245,1274 ****
    std::string as_string () const override;
  
    SlicePattern (Analysis::NodeMapping mappings,
! 		std::vector<std::unique_ptr<Pattern>> items, location_t locus)
      : items (std::move (items)), locus (locus), mappings (mappings)
    {}
  
!   // Copy constructor with vector clone
    SlicePattern (SlicePattern const &other)
!     : locus (other.locus), mappings (other.mappings)
!   {
!     items.reserve (other.items.size ());
!     for (const auto &e : other.items)
!       items.push_back (e->clone_pattern ());
!   }
  
    // Overloaded assignment operator to vector clone
    SlicePattern &operator= (SlicePattern const &other)
    {
      locus = other.locus;
      mappings = other.mappings;
  
-     items.clear ();
-     items.reserve (other.items.size ());
-     for (const auto &e : other.items)
-       items.push_back (e->clone_pattern ());
- 
      return *this;
    }
  
--- 1413,1435 ----
    std::string as_string () const override;
  
    SlicePattern (Analysis::NodeMapping mappings,
! 		std::unique_ptr<SlicePatternItems> items, location_t locus)
      : items (std::move (items)), locus (locus), mappings (mappings)
    {}
  
!   // Copy constructor requires clone
    SlicePattern (SlicePattern const &other)
!     : items (other.items->clone_slice_pattern_items ()), locus (other.locus),
!       mappings (other.mappings)
!   {}
  
    // Overloaded assignment operator to vector clone
    SlicePattern &operator= (SlicePattern const &other)
    {
+     items = other.items->clone_slice_pattern_items ();
      locus = other.locus;
      mappings = other.mappings;
  
      return *this;
    }
  
*************** public:
*** 1276,1286 ****
    SlicePattern (SlicePattern &&other) = default;
    SlicePattern &operator= (SlicePattern &&other) = default;
  
!   std::vector<std::unique_ptr<Pattern>> &get_items () { return items; }
!   const std::vector<std::unique_ptr<Pattern>> &get_items () const
!   {
!     return items;
!   }
  
    location_t get_locus () const override { return locus; }
  
--- 1437,1444 ----
    SlicePattern (SlicePattern &&other) = default;
    SlicePattern &operator= (SlicePattern &&other) = default;
  
!   SlicePatternItems &get_items () { return *items; }
!   const SlicePatternItems &get_items () const { return *items; }
  
    location_t get_locus () const override { return locus; }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/tree/rust-hir-visitor.cc gcc-16-20251102/gcc/rust/hir/tree/rust-hir-visitor.cc
*** gcc-16-20251026/gcc/rust/hir/tree/rust-hir-visitor.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/tree/rust-hir-visitor.cc	Sun Nov  2 22:32:23 2025
*************** DefaultHIRVisitor::walk (StructPattern &
*** 1023,1036 ****
  }
  
  void
! DefaultHIRVisitor::walk (TupleStructItemsNoRange &tuple_items)
  {
    for (auto &item : tuple_items.get_patterns ())
      item->accept_vis (*this);
  }
  
  void
! DefaultHIRVisitor::walk (TupleStructItemsRange &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      lower->accept_vis (*this);
--- 1023,1036 ----
  }
  
  void
! DefaultHIRVisitor::walk (TupleStructItemsNoRest &tuple_items)
  {
    for (auto &item : tuple_items.get_patterns ())
      item->accept_vis (*this);
  }
  
  void
! DefaultHIRVisitor::walk (TupleStructItemsHasRest &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      lower->accept_vis (*this);
*************** DefaultHIRVisitor::walk (TupleStructPatt
*** 1046,1059 ****
  }
  
  void
! DefaultHIRVisitor::walk (TuplePatternItemsMultiple &tuple_items)
  {
    for (auto &pattern : tuple_items.get_patterns ())
      pattern->accept_vis (*this);
  }
  
  void
! DefaultHIRVisitor::walk (TuplePatternItemsRanged &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      lower->accept_vis (*this);
--- 1046,1059 ----
  }
  
  void
! DefaultHIRVisitor::walk (TuplePatternItemsNoRest &tuple_items)
  {
    for (auto &pattern : tuple_items.get_patterns ())
      pattern->accept_vis (*this);
  }
  
  void
! DefaultHIRVisitor::walk (TuplePatternItemsHasRest &tuple_items)
  {
    for (auto &lower : tuple_items.get_lower_patterns ())
      lower->accept_vis (*this);
*************** DefaultHIRVisitor::walk (TuplePattern &p
*** 1068,1077 ****
  }
  
  void
  DefaultHIRVisitor::walk (SlicePattern &pattern)
  {
!   for (auto &item : pattern.get_items ())
!     item->accept_vis (*this);
  }
  
  void
--- 1068,1092 ----
  }
  
  void
+ DefaultHIRVisitor::walk (SlicePatternItemsNoRest &items)
+ {
+   for (auto &pattern : items.get_patterns ())
+     pattern->accept_vis (*this);
+ }
+ 
+ void
+ DefaultHIRVisitor::walk (SlicePatternItemsHasRest &items)
+ {
+   for (auto &lower : items.get_lower_patterns ())
+     lower->accept_vis (*this);
+   for (auto &upper : items.get_upper_patterns ())
+     upper->accept_vis (*this);
+ }
+ 
+ void
  DefaultHIRVisitor::walk (SlicePattern &pattern)
  {
!   pattern.get_items ().accept_vis (*this);
  }
  
  void
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/tree/rust-hir-visitor.h gcc-16-20251102/gcc/rust/hir/tree/rust-hir-visitor.h
*** gcc-16-20251026/gcc/rust/hir/tree/rust-hir-visitor.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/tree/rust-hir-visitor.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 132,143 ****
    virtual void visit (StructPatternFieldIdentPat &field) = 0;
    virtual void visit (StructPatternFieldIdent &field) = 0;
    virtual void visit (StructPattern &pattern) = 0;
!   virtual void visit (TupleStructItemsNoRange &tuple_items) = 0;
!   virtual void visit (TupleStructItemsRange &tuple_items) = 0;
    virtual void visit (TupleStructPattern &pattern) = 0;
!   virtual void visit (TuplePatternItemsMultiple &tuple_items) = 0;
!   virtual void visit (TuplePatternItemsRanged &tuple_items) = 0;
    virtual void visit (TuplePattern &pattern) = 0;
    virtual void visit (SlicePattern &pattern) = 0;
    virtual void visit (AltPattern &pattern) = 0;
    virtual void visit (EmptyStmt &stmt) = 0;
--- 132,145 ----
    virtual void visit (StructPatternFieldIdentPat &field) = 0;
    virtual void visit (StructPatternFieldIdent &field) = 0;
    virtual void visit (StructPattern &pattern) = 0;
!   virtual void visit (TupleStructItemsNoRest &tuple_items) = 0;
!   virtual void visit (TupleStructItemsHasRest &tuple_items) = 0;
    virtual void visit (TupleStructPattern &pattern) = 0;
!   virtual void visit (TuplePatternItemsNoRest &tuple_items) = 0;
!   virtual void visit (TuplePatternItemsHasRest &tuple_items) = 0;
    virtual void visit (TuplePattern &pattern) = 0;
+   virtual void visit (SlicePatternItemsNoRest &items) = 0;
+   virtual void visit (SlicePatternItemsHasRest &items) = 0;
    virtual void visit (SlicePattern &pattern) = 0;
    virtual void visit (AltPattern &pattern) = 0;
    virtual void visit (EmptyStmt &stmt) = 0;
*************** public:
*** 305,316 ****
    }
    virtual void visit (StructPatternFieldIdent &node) override { walk (node); }
    virtual void visit (StructPattern &node) override { walk (node); }
!   virtual void visit (TupleStructItemsNoRange &node) override { walk (node); }
!   virtual void visit (TupleStructItemsRange &node) override { walk (node); }
    virtual void visit (TupleStructPattern &node) override { walk (node); }
!   virtual void visit (TuplePatternItemsMultiple &node) override { walk (node); }
!   virtual void visit (TuplePatternItemsRanged &node) override { walk (node); }
    virtual void visit (TuplePattern &node) override { walk (node); }
    virtual void visit (SlicePattern &node) override { walk (node); }
    virtual void visit (AltPattern &node) override { walk (node); }
    virtual void visit (EmptyStmt &node) override { walk (node); }
--- 307,320 ----
    }
    virtual void visit (StructPatternFieldIdent &node) override { walk (node); }
    virtual void visit (StructPattern &node) override { walk (node); }
!   virtual void visit (TupleStructItemsNoRest &node) override { walk (node); }
!   virtual void visit (TupleStructItemsHasRest &node) override { walk (node); }
    virtual void visit (TupleStructPattern &node) override { walk (node); }
!   virtual void visit (TuplePatternItemsNoRest &node) override { walk (node); }
!   virtual void visit (TuplePatternItemsHasRest &node) override { walk (node); }
    virtual void visit (TuplePattern &node) override { walk (node); }
+   virtual void visit (SlicePatternItemsNoRest &node) override { walk (node); }
+   virtual void visit (SlicePatternItemsHasRest &node) override { walk (node); }
    virtual void visit (SlicePattern &node) override { walk (node); }
    virtual void visit (AltPattern &node) override { walk (node); }
    virtual void visit (EmptyStmt &node) override { walk (node); }
*************** protected:
*** 438,449 ****
    virtual void walk (StructPatternFieldIdentPat &) final;
    virtual void walk (StructPatternFieldIdent &) final;
    virtual void walk (StructPattern &) final;
!   virtual void walk (TupleStructItemsNoRange &) final;
!   virtual void walk (TupleStructItemsRange &) final;
    virtual void walk (TupleStructPattern &) final;
!   virtual void walk (TuplePatternItemsMultiple &) final;
!   virtual void walk (TuplePatternItemsRanged &) final;
    virtual void walk (TuplePattern &) final;
    virtual void walk (SlicePattern &) final;
    virtual void walk (AltPattern &) final;
    virtual void walk (EmptyStmt &) final;
--- 442,455 ----
    virtual void walk (StructPatternFieldIdentPat &) final;
    virtual void walk (StructPatternFieldIdent &) final;
    virtual void walk (StructPattern &) final;
!   virtual void walk (TupleStructItemsNoRest &) final;
!   virtual void walk (TupleStructItemsHasRest &) final;
    virtual void walk (TupleStructPattern &) final;
!   virtual void walk (TuplePatternItemsNoRest &) final;
!   virtual void walk (TuplePatternItemsHasRest &) final;
    virtual void walk (TuplePattern &) final;
+   virtual void walk (SlicePatternItemsNoRest &) final;
+   virtual void walk (SlicePatternItemsHasRest &) final;
    virtual void walk (SlicePattern &) final;
    virtual void walk (AltPattern &) final;
    virtual void walk (EmptyStmt &) final;
*************** public:
*** 586,598 ****
    virtual void visit (StructPatternFieldIdent &) override {}
    virtual void visit (StructPattern &) override {}
  
!   virtual void visit (TupleStructItemsNoRange &) override {}
!   virtual void visit (TupleStructItemsRange &) override {}
    virtual void visit (TupleStructPattern &) override {}
  
!   virtual void visit (TuplePatternItemsMultiple &) override {}
!   virtual void visit (TuplePatternItemsRanged &) override {}
    virtual void visit (TuplePattern &) override {}
    virtual void visit (SlicePattern &) override {}
    virtual void visit (AltPattern &) override {}
  
--- 592,607 ----
    virtual void visit (StructPatternFieldIdent &) override {}
    virtual void visit (StructPattern &) override {}
  
!   virtual void visit (TupleStructItemsNoRest &) override {}
!   virtual void visit (TupleStructItemsHasRest &) override {}
    virtual void visit (TupleStructPattern &) override {}
  
!   virtual void visit (TuplePatternItemsNoRest &) override {}
!   virtual void visit (TuplePatternItemsHasRest &) override {}
    virtual void visit (TuplePattern &) override {}
+ 
+   virtual void visit (SlicePatternItemsNoRest &) override {}
+   virtual void visit (SlicePatternItemsHasRest &) override {}
    virtual void visit (SlicePattern &) override {}
    virtual void visit (AltPattern &) override {}
  
diff -Nrcpad gcc-16-20251026/gcc/rust/hir/tree/rust-hir.cc gcc-16-20251102/gcc/rust/hir/tree/rust-hir.cc
*** gcc-16-20251026/gcc/rust/hir/tree/rust-hir.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/hir/tree/rust-hir.cc	Sun Nov  2 22:32:23 2025
*************** PathPattern::convert_to_simple_path (boo
*** 2239,2246 ****
  
        // create segment and add to vector
        std::string segment_str = segment.as_string ();
!       simple_segments.push_back (
! 	AST::SimplePathSegment (std::move (segment_str), segment.get_locus ()));
      }
  
    // kind of a HACK to get locus depending on opening scope resolution
--- 2239,2246 ----
  
        // create segment and add to vector
        std::string segment_str = segment.as_string ();
!       simple_segments.emplace_back (std::move (segment_str),
! 				    segment.get_locus ());
      }
  
    // kind of a HACK to get locus depending on opening scope resolution
*************** TypePath::as_simple_path () const
*** 2281,2289 ****
  
        // create segment and add to vector
        std::string segment_str = segment->as_string ();
!       simple_segments.push_back (
! 	AST::SimplePathSegment (std::move (segment_str),
! 				segment->get_locus ()));
      }
  
    return AST::SimplePath (std::move (simple_segments),
--- 2281,2288 ----
  
        // create segment and add to vector
        std::string segment_str = segment->as_string ();
!       simple_segments.emplace_back (std::move (segment_str),
! 				    segment->get_locus ());
      }
  
    return AST::SimplePath (std::move (simple_segments),
*************** RangePatternBoundLiteral::as_string () c
*** 2387,2397 ****
  }
  
  std::string
! SlicePattern::as_string () const
  {
!   std::string str ("SlicePattern: ");
  
!   for (const auto &pattern : items)
      {
        str += "\n " + pattern->as_string ();
      }
--- 2386,2396 ----
  }
  
  std::string
! SlicePatternItemsNoRest::as_string () const
  {
!   std::string str;
  
!   for (const auto &pattern : patterns)
      {
        str += "\n " + pattern->as_string ();
      }
*************** SlicePattern::as_string () const
*** 2400,2405 ****
--- 2399,2444 ----
  }
  
  std::string
+ SlicePatternItemsHasRest::as_string () const
+ {
+   std::string str;
+ 
+   str += "\n Lower patterns: ";
+   if (lower_patterns.empty ())
+     {
+       str += "none";
+     }
+   else
+     {
+       for (const auto &lower : lower_patterns)
+ 	{
+ 	  str += "\n  " + lower->as_string ();
+ 	}
+     }
+ 
+   str += "\n Upper patterns: ";
+   if (upper_patterns.empty ())
+     {
+       str += "none";
+     }
+   else
+     {
+       for (const auto &upper : upper_patterns)
+ 	{
+ 	  str += "\n  " + upper->as_string ();
+ 	}
+     }
+ 
+   return str;
+ }
+ 
+ std::string
+ SlicePattern::as_string () const
+ {
+   return "SlicePattern: " + items->as_string ();
+ }
+ 
+ std::string
  AltPattern::as_string () const
  {
    std::string str ("AltPattern: ");
*************** AltPattern::as_string () const
*** 2413,2419 ****
  }
  
  std::string
! TuplePatternItemsMultiple::as_string () const
  {
    std::string str;
  
--- 2452,2458 ----
  }
  
  std::string
! TuplePatternItemsNoRest::as_string () const
  {
    std::string str;
  
*************** TuplePatternItemsMultiple::as_string ()
*** 2426,2432 ****
  }
  
  std::string
! TuplePatternItemsRanged::as_string () const
  {
    std::string str;
  
--- 2465,2471 ----
  }
  
  std::string
! TuplePatternItemsHasRest::as_string () const
  {
    std::string str;
  
*************** StructPatternField::as_string () const
*** 2480,2489 ****
         * just the body */
        for (const auto &attr : outer_attrs)
  	{
! 	  str += "\n  " + attr.as_string ();
  	}
      }
  
    return str;
  }
  
--- 2519,2547 ----
         * just the body */
        for (const auto &attr : outer_attrs)
  	{
! 	  str += "\n    " + attr.as_string ();
  	}
      }
  
+   str += "\n   item type: ";
+   switch (get_item_type ())
+     {
+     case ItemType::TUPLE_PAT:
+       str += "TUPLE_PAT";
+       break;
+     case ItemType::IDENT_PAT:
+       str += "IDENT_PAT";
+       break;
+     case ItemType::IDENT:
+       str += "IDENT";
+       break;
+     default:
+       str += "UNKNOWN";
+       break;
+     }
+ 
+   str += "\n   mapping: " + mappings.as_string ();
+ 
    return str;
  }
  
*************** IdentifierPattern::as_string () const
*** 2620,2626 ****
  }
  
  std::string
! TupleStructItemsNoRange::as_string () const
  {
    std::string str;
  
--- 2678,2684 ----
  }
  
  std::string
! TupleStructItemsNoRest::as_string () const
  {
    std::string str;
  
*************** TupleStructItemsNoRange::as_string () co
*** 2633,2639 ****
  }
  
  std::string
! TupleStructItemsRange::as_string () const
  {
    std::string str ("\n  Lower patterns: ");
  
--- 2691,2697 ----
  }
  
  std::string
! TupleStructItemsHasRest::as_string () const
  {
    std::string str ("\n  Lower patterns: ");
  
*************** StructPattern::accept_vis (HIRFullVisito
*** 4471,4483 ****
  }
  
  void
! TupleStructItemsNoRange::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! TupleStructItemsRange::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
--- 4529,4541 ----
  }
  
  void
! TupleStructItemsNoRest::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! TupleStructItemsHasRest::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
*************** TupleStructPattern::accept_vis (HIRFullV
*** 4489,4501 ****
  }
  
  void
! TuplePatternItemsMultiple::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! TuplePatternItemsRanged::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
--- 4547,4559 ----
  }
  
  void
! TuplePatternItemsNoRest::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! TuplePatternItemsHasRest::accept_vis (HIRFullVisitor &vis)
  {
    vis.visit (*this);
  }
*************** TuplePattern::accept_vis (HIRFullVisitor
*** 4505,4510 ****
--- 4563,4580 ----
  {
    vis.visit (*this);
  }
+ 
+ void
+ SlicePatternItemsNoRest::accept_vis (HIRFullVisitor &vis)
+ {
+   vis.visit (*this);
+ }
+ 
+ void
+ SlicePatternItemsHasRest::accept_vis (HIRFullVisitor &vis)
+ {
+   vis.visit (*this);
+ }
  
  void
  SlicePattern::accept_vis (HIRFullVisitor &vis)
diff -Nrcpad gcc-16-20251026/gcc/rust/lex/rust-lex.cc gcc-16-20251102/gcc/rust/lex/rust-lex.cc
*** gcc-16-20251026/gcc/rust/lex/rust-lex.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/lex/rust-lex.cc	Sun Nov  2 22:32:23 2025
*************** Lexer::dump_and_skip (int n)
*** 236,245 ****
  
  	  out << "<id=";
  	  out << tok->token_id_to_str ();
! 	  out << (tok->has_str () ? (std::string (", text=") + tok->get_str ()
! 				     + std::string (", typehint=")
! 				     + std::string (tok->get_type_hint_str ()))
! 				  : "")
  	      << " ";
  	  out << Linemap::location_to_string (loc) << '\n';
  	}
--- 236,246 ----
  
  	  out << "<id=";
  	  out << tok->token_id_to_str ();
! 	  out << (tok->should_have_str ()
! 		    ? (std::string (", text=") + tok->get_str ()
! 		       + std::string (", typehint=")
! 		       + std::string (tok->get_type_hint_str ()))
! 		    : "")
  	      << " ";
  	  out << Linemap::location_to_string (loc) << '\n';
  	}
diff -Nrcpad gcc-16-20251026/gcc/rust/lex/rust-token.cc gcc-16-20251102/gcc/rust/lex/rust-token.cc
*** gcc-16-20251026/gcc/rust/lex/rust-token.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/lex/rust-token.cc	Sun Nov  2 22:32:23 2025
*************** nfc_normalize_token_string (location_t l
*** 178,206 ****
      return str;
  }
  
- const std::string &
- Token::get_str () const
- {
-   if (token_id_is_keyword (token_id))
-     return token_id_keyword_string (token_id);
- 
-   // FIXME: attempt to return null again
-   // gcc_assert(str != NULL);
- 
-   // HACK: allow referencing an empty string
-   static const std::string empty = "";
- 
-   if (str == NULL)
-     {
-       rust_error_at (get_locus (),
- 		     "attempted to get string for %qs, which has no string. "
- 		     "returning empty string instead",
- 		     get_token_description ());
-       return empty;
-     }
-   return *str;
- }
- 
  namespace {
  enum class Context
  {
--- 178,183 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/lex/rust-token.h gcc-16-20251102/gcc/rust/lex/rust-token.h
*** gcc-16-20251026/gcc/rust/lex/rust-token.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/lex/rust-token.h	Sun Nov  2 22:32:23 2025
***************
*** 22,27 ****
--- 22,28 ----
  #include "rust-system.h"
  #include "rust-linemap.h"
  #include "rust-unicode.h"
+ #include "rust-diagnostics.h"
  
  namespace Rust {
  
*************** private:
*** 249,255 ****
    // Token location.
    location_t locus;
    // Associated text (if any) of token.
!   std::unique_ptr<std::string> str;
    // TODO: maybe remove issues and just store std::string as value?
    /* Type hint for token based on lexer data (e.g. type suffix). Does not exist
     * for most tokens. */
--- 250,256 ----
    // Token location.
    location_t locus;
    // Associated text (if any) of token.
!   std::string str;
    // TODO: maybe remove issues and just store std::string as value?
    /* Type hint for token based on lexer data (e.g. type suffix). Does not exist
     * for most tokens. */
*************** private:
*** 257,279 ****
  
    // Token constructor from token id and location. Has a null string.
    Token (TokenId token_id, location_t location)
!     : token_id (token_id), locus (location), str (nullptr),
!       type_hint (CORETYPE_UNKNOWN)
    {}
  
    // Token constructor from token id, location, and a string.
!   Token (TokenId token_id, location_t location, std::string &&paramStr)
      : token_id (token_id), locus (location), type_hint (CORETYPE_UNKNOWN)
    {
      // Normalize identifier tokens
!     str = std::make_unique<std::string> (
!       nfc_normalize_token_string (location, token_id, paramStr));
    }
  
    // Token constructor from token id, location, and a char.
    Token (TokenId token_id, location_t location, char paramChar)
!     : token_id (token_id), locus (location),
!       str (new std::string (1, paramChar)), type_hint (CORETYPE_UNKNOWN)
    {
      // Do not need to normalize 1byte char
    }
--- 258,278 ----
  
    // Token constructor from token id and location. Has a null string.
    Token (TokenId token_id, location_t location)
!     : token_id (token_id), locus (location), type_hint (CORETYPE_UNKNOWN)
    {}
  
    // Token constructor from token id, location, and a string.
!   Token (TokenId token_id, location_t location, std::string paramStr)
      : token_id (token_id), locus (location), type_hint (CORETYPE_UNKNOWN)
    {
      // Normalize identifier tokens
!     str = nfc_normalize_token_string (location, token_id, std::move (paramStr));
    }
  
    // Token constructor from token id, location, and a char.
    Token (TokenId token_id, location_t location, char paramChar)
!     : token_id (token_id), locus (location), str (1, paramChar),
!       type_hint (CORETYPE_UNKNOWN)
    {
      // Do not need to normalize 1byte char
    }
*************** private:
*** 283,301 ****
      : token_id (token_id), locus (location), type_hint (CORETYPE_UNKNOWN)
    {
      // Normalize identifier tokens
!     str = std::make_unique<std::string> (
!       nfc_normalize_token_string (location, token_id,
! 				  paramCodepoint.as_string ()));
    }
  
    // Token constructor from token id, location, a string, and type hint.
!   Token (TokenId token_id, location_t location, std::string &&paramStr,
  	 PrimitiveCoreType parType)
      : token_id (token_id), locus (location), type_hint (parType)
    {
      // Normalize identifier tokens
!     str = std::make_unique<std::string> (
!       nfc_normalize_token_string (location, token_id, paramStr));
    }
  
  public:
--- 282,298 ----
      : token_id (token_id), locus (location), type_hint (CORETYPE_UNKNOWN)
    {
      // Normalize identifier tokens
!     str = nfc_normalize_token_string (location, token_id,
! 				      paramCodepoint.as_string ());
    }
  
    // Token constructor from token id, location, a string, and type hint.
!   Token (TokenId token_id, location_t location, std::string paramStr,
  	 PrimitiveCoreType parType)
      : token_id (token_id), locus (location), type_hint (parType)
    {
      // Normalize identifier tokens
!     str = nfc_normalize_token_string (location, token_id, std::move (paramStr));
    }
  
  public:
*************** public:
*** 322,328 ****
    }
  
    // Makes and returns a new TokenPtr of type IDENTIFIER.
!   static TokenPtr make_identifier (location_t locus, std::string &&str)
    {
      // return std::make_shared<Token> (IDENTIFIER, locus, str);
      return TokenPtr (new Token (IDENTIFIER, locus, std::move (str)));
--- 319,325 ----
    }
  
    // Makes and returns a new TokenPtr of type IDENTIFIER.
!   static TokenPtr make_identifier (location_t locus, std::string str)
    {
      // return std::make_shared<Token> (IDENTIFIER, locus, str);
      return TokenPtr (new Token (IDENTIFIER, locus, std::move (str)));
*************** public:
*** 331,337 ****
    static TokenPtr make_identifier (const Identifier &ident);
  
    // Makes and returns a new TokenPtr of type INT_LITERAL.
!   static TokenPtr make_int (location_t locus, std::string &&str,
  			    PrimitiveCoreType type_hint = CORETYPE_UNKNOWN)
    {
      // return std::make_shared<Token> (INT_LITERAL, locus, str, type_hint);
--- 328,334 ----
    static TokenPtr make_identifier (const Identifier &ident);
  
    // Makes and returns a new TokenPtr of type INT_LITERAL.
!   static TokenPtr make_int (location_t locus, std::string str,
  			    PrimitiveCoreType type_hint = CORETYPE_UNKNOWN)
    {
      // return std::make_shared<Token> (INT_LITERAL, locus, str, type_hint);
*************** public:
*** 340,346 ****
    }
  
    // Makes and returns a new TokenPtr of type FLOAT_LITERAL.
!   static TokenPtr make_float (location_t locus, std::string &&str,
  			      PrimitiveCoreType type_hint = CORETYPE_UNKNOWN)
    {
      // return std::make_shared<Token> (FLOAT_LITERAL, locus, str, type_hint);
--- 337,343 ----
    }
  
    // Makes and returns a new TokenPtr of type FLOAT_LITERAL.
!   static TokenPtr make_float (location_t locus, std::string str,
  			      PrimitiveCoreType type_hint = CORETYPE_UNKNOWN)
    {
      // return std::make_shared<Token> (FLOAT_LITERAL, locus, str, type_hint);
*************** public:
*** 349,355 ****
    }
  
    // Makes and returns a new TokenPtr of type STRING_LITERAL.
!   static TokenPtr make_string (location_t locus, std::string &&str)
    {
      // return std::make_shared<Token> (STRING_LITERAL, locus, str,
      // CORETYPE_STR);
--- 346,352 ----
    }
  
    // Makes and returns a new TokenPtr of type STRING_LITERAL.
!   static TokenPtr make_string (location_t locus, std::string str)
    {
      // return std::make_shared<Token> (STRING_LITERAL, locus, str,
      // CORETYPE_STR);
*************** public:
*** 372,403 ****
    }
  
    // Makes and returns a new TokenPtr of type BYTE_STRING_LITERAL (fix).
!   static TokenPtr make_byte_string (location_t locus, std::string &&str)
    {
      // return std::make_shared<Token> (BYTE_STRING_LITERAL, locus, str);
      return TokenPtr (new Token (BYTE_STRING_LITERAL, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type RAW_STRING_LITERAL.
!   static TokenPtr make_raw_string (location_t locus, std::string &&str)
    {
      return TokenPtr (new Token (RAW_STRING_LITERAL, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type INNER_DOC_COMMENT.
!   static TokenPtr make_inner_doc_comment (location_t locus, std::string &&str)
    {
      return TokenPtr (new Token (INNER_DOC_COMMENT, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type OUTER_DOC_COMMENT.
!   static TokenPtr make_outer_doc_comment (location_t locus, std::string &&str)
    {
      return TokenPtr (new Token (OUTER_DOC_COMMENT, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type LIFETIME.
!   static TokenPtr make_lifetime (location_t locus, std::string &&str)
    {
      // return std::make_shared<Token> (LIFETIME, locus, str);
      return TokenPtr (new Token (LIFETIME, locus, std::move (str)));
--- 369,400 ----
    }
  
    // Makes and returns a new TokenPtr of type BYTE_STRING_LITERAL (fix).
!   static TokenPtr make_byte_string (location_t locus, std::string str)
    {
      // return std::make_shared<Token> (BYTE_STRING_LITERAL, locus, str);
      return TokenPtr (new Token (BYTE_STRING_LITERAL, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type RAW_STRING_LITERAL.
!   static TokenPtr make_raw_string (location_t locus, std::string str)
    {
      return TokenPtr (new Token (RAW_STRING_LITERAL, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type INNER_DOC_COMMENT.
!   static TokenPtr make_inner_doc_comment (location_t locus, std::string str)
    {
      return TokenPtr (new Token (INNER_DOC_COMMENT, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type OUTER_DOC_COMMENT.
!   static TokenPtr make_outer_doc_comment (location_t locus, std::string str)
    {
      return TokenPtr (new Token (OUTER_DOC_COMMENT, locus, std::move (str)));
    }
  
    // Makes and returns a new TokenPtr of type LIFETIME.
!   static TokenPtr make_lifetime (location_t locus, std::string str)
    {
      // return std::make_shared<Token> (LIFETIME, locus, str);
      return TokenPtr (new Token (LIFETIME, locus, std::move (str)));
*************** public:
*** 413,428 ****
    void set_locus (location_t locus) { this->locus = locus; }
  
    // Gets string description of the token.
!   const std::string &
!   get_str () const; /*{
! // FIXME: put in header again when fix null problem
! //gcc_assert(str != nullptr);
! if (str == nullptr) {
! error_at(get_locus(), "attempted to get string for '%s', which has no string.
! returning empty string instead.", get_token_description()); return "";
! }
! return *str;
! }*/
  
    // Gets token's type hint info.
    PrimitiveCoreType get_type_hint () const
--- 410,427 ----
    void set_locus (location_t locus) { this->locus = locus; }
  
    // Gets string description of the token.
!   const std::string &get_str () const
!   {
!     if (token_id_is_keyword (token_id))
!       return token_id_keyword_string (token_id);
! 
!     if (!should_have_str ())
!       rust_internal_error_at (
! 	locus, "attempting to get string for %qs, which should have no string",
! 	get_token_description ());
! 
!     return str;
!   }
  
    // Gets token's type hint info.
    PrimitiveCoreType get_type_hint () const
*************** return *str;
*** 464,477 ****
        }
    }
  
-   /* Returns whether the token actually has a string (regardless of whether it
-    * should or not). */
-   bool has_str () const { return str != nullptr; }
- 
    // Returns whether the token should have a string.
    bool should_have_str () const
    {
!     return is_literal () || token_id == IDENTIFIER || token_id == LIFETIME;
    }
  
    // Returns whether the token is a pure decimal int literal
--- 463,473 ----
        }
    }
  
    // Returns whether the token should have a string.
    bool should_have_str () const
    {
!     return is_literal () || token_id == IDENTIFIER || token_id == LIFETIME
! 	   || token_id == INNER_DOC_COMMENT || token_id == OUTER_DOC_COMMENT;
    }
  
    // Returns whether the token is a pure decimal int literal
diff -Nrcpad gcc-16-20251026/gcc/rust/metadata/rust-export-metadata.cc gcc-16-20251102/gcc/rust/metadata/rust-export-metadata.cc
*** gcc-16-20251026/gcc/rust/metadata/rust-export-metadata.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/metadata/rust-export-metadata.cc	Sun Nov  2 22:32:23 2025
*************** ExportContext::emit_function (const HIR:
*** 91,98 ****
        AST::Function &function = static_cast<AST::Function &> (vis_item);
  
        std::vector<std::unique_ptr<AST::ExternalItem>> external_items;
!       external_items.push_back (std::unique_ptr<AST::ExternalItem> (
! 	static_cast<AST::ExternalItem *> (&function)));
  
        AST::ExternBlock extern_block (get_string_from_abi (Rust::ABI::RUST),
  				     std::move (external_items),
--- 91,98 ----
        AST::Function &function = static_cast<AST::Function &> (vis_item);
  
        std::vector<std::unique_ptr<AST::ExternalItem>> external_items;
!       external_items.emplace_back (
! 	static_cast<AST::ExternalItem *> (&function));
  
        AST::ExternBlock extern_block (get_string_from_abi (Rust::ABI::RUST),
  				     std::move (external_items),
diff -Nrcpad gcc-16-20251026/gcc/rust/parse/rust-parse-impl.h gcc-16-20251102/gcc/rust/parse/rust-parse-impl.h
*** gcc-16-20251026/gcc/rust/parse/rust-parse-impl.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/parse/rust-parse-impl.h	Sun Nov  2 22:32:23 2025
*************** Parser<ManagedTokenSource>::parse_identi
*** 1053,1058 ****
--- 1053,1059 ----
      }
    else
      {
+       add_error (Error (t->get_locus (), "expected keyword or identifier"));
        return nullptr;
      }
  }
*************** Parser<ManagedTokenSource>::parse_decl_m
*** 1716,1725 ****
  	  return nullptr;
  	}
  
-       AST::MacroRule macro_rule
- 	= AST::MacroRule (std::move (matcher), std::move (transcriber), locus);
        std::vector<AST::MacroRule> macro_rules;
!       macro_rules.push_back (macro_rule);
  
        return std::unique_ptr<AST::MacroRulesDefinition> (
  	AST::MacroRulesDefinition::decl_macro (std::move (rule_name),
--- 1717,1725 ----
  	  return nullptr;
  	}
  
        std::vector<AST::MacroRule> macro_rules;
!       macro_rules.emplace_back (std::move (matcher), std::move (transcriber),
! 				locus);
  
        return std::unique_ptr<AST::MacroRulesDefinition> (
  	AST::MacroRulesDefinition::decl_macro (std::move (rule_name),
*************** Parser<ManagedTokenSource>::parse_lifeti
*** 3316,3323 ****
  	  break;
  	}
  
!       lifetime_params.push_back (std::unique_ptr<AST::LifetimeParam> (
! 	new AST::LifetimeParam (std::move (lifetime_param.value ()))));
  
        if (lexer.peek_token ()->get_id () != COMMA)
  	break;
--- 3316,3323 ----
  	  break;
  	}
  
!       lifetime_params.emplace_back (
! 	new AST::LifetimeParam (std::move (lifetime_param.value ())));
  
        if (lexer.peek_token ()->get_id () != COMMA)
  	break;
*************** Parser<ManagedTokenSource>::parse_lifeti
*** 3356,3363 ****
  	  return {};
  	}
  
!       lifetime_params.push_back (std::unique_ptr<AST::LifetimeParam> (
! 	new AST::LifetimeParam (std::move (lifetime_param))));
  
        if (lexer.peek_token ()->get_id () != COMMA)
  	break;
--- 3356,3363 ----
  	  return {};
  	}
  
!       lifetime_params.emplace_back (
! 	new AST::LifetimeParam (std::move (lifetime_param)));
  
        if (lexer.peek_token ()->get_id () != COMMA)
  	break;
*************** Parser<ManagedTokenSource>::parse_trait_
*** 5219,5225 ****
  
  // Parses a constant trait item.
  template <typename ManagedTokenSource>
! std::unique_ptr<AST::TraitItemConst>
  Parser<ManagedTokenSource>::parse_trait_const (AST::AttrVec outer_attrs)
  {
    location_t locus = lexer.peek_token ()->get_locus ();
--- 5219,5225 ----
  
  // Parses a constant trait item.
  template <typename ManagedTokenSource>
! std::unique_ptr<AST::ConstantItem>
  Parser<ManagedTokenSource>::parse_trait_const (AST::AttrVec outer_attrs)
  {
    location_t locus = lexer.peek_token ()->get_locus ();
*************** Parser<ManagedTokenSource>::parse_trait_
*** 5257,5266 ****
        return nullptr;
      }
  
!   return std::unique_ptr<AST::TraitItemConst> (
!     new AST::TraitItemConst (std::move (ident), std::move (type),
! 			     std::move (const_body), std::move (outer_attrs),
! 			     locus));
  }
  
  /* Parses a struct "impl" item (both inherent impl and trait impl can be
--- 5257,5265 ----
        return nullptr;
      }
  
!   return std::unique_ptr<AST::ConstantItem> (new AST::ConstantItem (
!     std::move (ident), AST::Visibility::create_private (), std::move (type),
!     std::move (const_body), std::move (outer_attrs), locus));
  }
  
  /* Parses a struct "impl" item (both inherent impl and trait impl can be
*************** Parser<ManagedTokenSource>::parse_patter
*** 10484,10499 ****
      return first;
  
    std::vector<std::unique_ptr<AST::Pattern>> alts;
!   alts.push_back (std::move (first));
  
    do
      {
        lexer.skip_token ();
!       alts.push_back (parse_pattern_no_alt ());
      }
  
    while (lexer.peek_token ()->get_id () == PIPE);
  
    /* alternates */
    return std::unique_ptr<AST::Pattern> (
      new AST::AltPattern (std::move (alts), start_locus));
--- 10483,10504 ----
      return first;
  
    std::vector<std::unique_ptr<AST::Pattern>> alts;
!   if (first != nullptr)
!     alts.push_back (std::move (first));
  
    do
      {
        lexer.skip_token ();
!       auto follow = parse_pattern_no_alt ();
!       if (follow != nullptr)
! 	alts.push_back (std::move (follow));
      }
  
    while (lexer.peek_token ()->get_id () == PIPE);
  
+   if (alts.empty ())
+     return nullptr;
+ 
    /* alternates */
    return std::unique_ptr<AST::Pattern> (
      new AST::AltPattern (std::move (alts), start_locus));
*************** Parser<ManagedTokenSource>::parse_groupe
*** 10812,10820 ****
  	  return nullptr;
  	}
  
!       // create ranged tuple pattern items with only upper items
!       std::unique_ptr<AST::TuplePatternItemsRanged> items (
! 	new AST::TuplePatternItemsRanged (
  	  std::vector<std::unique_ptr<AST::Pattern>> (), std::move (patterns)));
        return std::unique_ptr<AST::TuplePattern> (
  	new AST::TuplePattern (std::move (items), paren_locus));
--- 10817,10825 ----
  	  return nullptr;
  	}
  
!       // create tuple pattern items with only upper pattern items
!       std::unique_ptr<AST::TuplePatternItemsHasRest> items (
! 	new AST::TuplePatternItemsHasRest (
  	  std::vector<std::unique_ptr<AST::Pattern>> (), std::move (patterns)));
        return std::unique_ptr<AST::TuplePattern> (
  	new AST::TuplePattern (std::move (items), paren_locus));
*************** Parser<ManagedTokenSource>::parse_groupe
*** 10822,10829 ****
    else if (lexer.peek_token ()->get_id () == RIGHT_PAREN)
      {
        skip_token (RIGHT_PAREN);
!       auto items = std::unique_ptr<AST::TuplePatternItemsMultiple> (
! 	new AST::TuplePatternItemsMultiple (
  	  std::vector<std::unique_ptr<AST::Pattern>> ()));
        return std::unique_ptr<AST::TuplePattern> (
  	new AST::TuplePattern (std::move (items), paren_locus));
--- 10827,10834 ----
    else if (lexer.peek_token ()->get_id () == RIGHT_PAREN)
      {
        skip_token (RIGHT_PAREN);
!       auto items = std::unique_ptr<AST::TuplePatternItemsNoRest> (
! 	new AST::TuplePatternItemsNoRest (
  	  std::vector<std::unique_ptr<AST::Pattern>> ()));
        return std::unique_ptr<AST::TuplePattern> (
  	new AST::TuplePattern (std::move (items), paren_locus));
*************** Parser<ManagedTokenSource>::parse_groupe
*** 10887,10894 ****
  	    // non-ranged tuple pattern
  	    lexer.skip_token ();
  
! 	    std::unique_ptr<AST::TuplePatternItemsMultiple> items (
! 	      new AST::TuplePatternItemsMultiple (std::move (patterns)));
  	    return std::unique_ptr<AST::TuplePattern> (
  	      new AST::TuplePattern (std::move (items), paren_locus));
  	  }
--- 10892,10899 ----
  	    // non-ranged tuple pattern
  	    lexer.skip_token ();
  
! 	    std::unique_ptr<AST::TuplePatternItemsNoRest> items (
! 	      new AST::TuplePatternItemsNoRest (std::move (patterns)));
  	    return std::unique_ptr<AST::TuplePattern> (
  	      new AST::TuplePattern (std::move (items), paren_locus));
  	  }
*************** Parser<ManagedTokenSource>::parse_groupe
*** 10928,10936 ****
  		return nullptr;
  	      }
  
! 	    std::unique_ptr<AST::TuplePatternItemsRanged> items (
! 	      new AST::TuplePatternItemsRanged (std::move (patterns),
! 						std::move (upper_patterns)));
  	    return std::unique_ptr<AST::TuplePattern> (
  	      new AST::TuplePattern (std::move (items), paren_locus));
  	  }
--- 10933,10941 ----
  		return nullptr;
  	      }
  
! 	    std::unique_ptr<AST::TuplePatternItemsHasRest> items (
! 	      new AST::TuplePatternItemsHasRest (std::move (patterns),
! 						 std::move (upper_patterns)));
  	    return std::unique_ptr<AST::TuplePattern> (
  	      new AST::TuplePattern (std::move (items), paren_locus));
  	  }
*************** Parser<ManagedTokenSource>::parse_identi
*** 11113,11119 ****
        lexer.skip_token ();
  
        // parse required pattern to bind
!       bind_pattern = parse_pattern ();
        if (bind_pattern == nullptr)
  	{
  	  Error error (lexer.peek_token ()->get_locus (),
--- 11118,11124 ----
        lexer.skip_token ();
  
        // parse required pattern to bind
!       bind_pattern = parse_pattern_no_alt ();
        if (bind_pattern == nullptr)
  	{
  	  Error error (lexer.peek_token ()->get_locus (),
*************** Parser<ManagedTokenSource>::parse_ident_
*** 11240,11246 ****
  	    // identifier with pattern bind
  	    lexer.skip_token ();
  
! 	    std::unique_ptr<AST::Pattern> bind_pattern = parse_pattern ();
  	    if (bind_pattern == nullptr)
  	      {
  		Error error (
--- 11245,11252 ----
  	    // identifier with pattern bind
  	    lexer.skip_token ();
  
! 	    std::unique_ptr<AST::Pattern> bind_pattern
! 	      = parse_pattern_no_alt ();
  	    if (bind_pattern == nullptr)
  	      {
  		Error error (
*************** Parser<ManagedTokenSource>::parse_tuple_
*** 11325,11333 ****
        rust_debug (
  	"finished parsing tuple struct items ranged (upper/none only)");
  
!       return std::unique_ptr<AST::TupleStructItemsRange> (
! 	new AST::TupleStructItemsRange (std::move (lower_patterns),
! 					std::move (upper_patterns)));
      }
  
    // has at least some lower patterns
--- 11331,11339 ----
        rust_debug (
  	"finished parsing tuple struct items ranged (upper/none only)");
  
!       return std::unique_ptr<AST::TupleStructItemsHasRest> (
! 	new AST::TupleStructItemsHasRest (std::move (lower_patterns),
! 					  std::move (upper_patterns)));
      }
  
    // has at least some lower patterns
*************** Parser<ManagedTokenSource>::parse_tuple_
*** 11369,11376 ****
    switch (t->get_id ())
      {
      case RIGHT_PAREN:
!       return std::unique_ptr<AST::TupleStructItemsNoRange> (
! 	new AST::TupleStructItemsNoRange (std::move (lower_patterns)));
      case DOT_DOT:
        {
  	// has an upper range that must be parsed separately
--- 11375,11382 ----
    switch (t->get_id ())
      {
      case RIGHT_PAREN:
!       return std::unique_ptr<AST::TupleStructItemsNoRest> (
! 	new AST::TupleStructItemsNoRest (std::move (lower_patterns)));
      case DOT_DOT:
        {
  	// has an upper range that must be parsed separately
*************** Parser<ManagedTokenSource>::parse_tuple_
*** 11402,11410 ****
  	    t = lexer.peek_token ();
  	  }
  
! 	return std::unique_ptr<AST::TupleStructItemsRange> (
! 	  new AST::TupleStructItemsRange (std::move (lower_patterns),
! 					  std::move (upper_patterns)));
        }
      default:
        // error
--- 11408,11416 ----
  	    t = lexer.peek_token ();
  	  }
  
! 	return std::unique_ptr<AST::TupleStructItemsHasRest> (
! 	  new AST::TupleStructItemsHasRest (std::move (lower_patterns),
! 					    std::move (upper_patterns)));
        }
      default:
        // error
*************** Parser<ManagedTokenSource>::parse_struct
*** 11424,11430 ****
    std::vector<std::unique_ptr<AST::StructPatternField>> fields;
  
    AST::AttrVec etc_attrs;
!   bool has_etc = false;
  
    // try parsing struct pattern fields
    const_TokenPtr t = lexer.peek_token ();
--- 11430,11436 ----
    std::vector<std::unique_ptr<AST::StructPatternField>> fields;
  
    AST::AttrVec etc_attrs;
!   bool has_rest = false;
  
    // try parsing struct pattern fields
    const_TokenPtr t = lexer.peek_token ();
*************** Parser<ManagedTokenSource>::parse_struct
*** 11437,11443 ****
  	{
  	  lexer.skip_token ();
  	  etc_attrs = std::move (outer_attrs);
! 	  has_etc = true;
  	  break;
  	}
  
--- 11443,11449 ----
  	{
  	  lexer.skip_token ();
  	  etc_attrs = std::move (outer_attrs);
! 	  has_rest = true;
  	  break;
  	}
  
*************** Parser<ManagedTokenSource>::parse_struct
*** 11462,11468 ****
        t = lexer.peek_token ();
      }
  
!   if (has_etc)
      return AST::StructPatternElements (std::move (fields),
  				       std::move (etc_attrs));
    else
--- 11468,11474 ----
        t = lexer.peek_token ();
      }
  
!   if (has_rest)
      return AST::StructPatternElements (std::move (fields),
  				       std::move (etc_attrs));
    else
*************** Parser<ManagedTokenSource>::parse_stmt_o
*** 11761,11766 ****
--- 11767,11774 ----
  	    std::unique_ptr<AST::MacroInvocation> invoc
  	      = parse_macro_invocation_partial (std::move (path),
  						std::move (outer_attrs));
+ 	    if (invoc == nullptr)
+ 	      return ExprOrStmt::create_error ();
  
  	    if (restrictions.consume_semi && maybe_skip_token (SEMICOLON))
  	      {
*************** Parser<ManagedTokenSource>::parse_stmt_o
*** 11772,11780 ****
  
  	    TokenId after_macro = lexer.peek_token ()->get_id ();
  
! 	    if (invoc->get_invoc_data ().get_delim_tok_tree ().get_delim_type ()
! 		  == AST::CURLY
! 		&& after_macro != DOT && after_macro != QUESTION_MARK)
  	      {
  		rust_debug ("braced macro statement");
  		return ExprOrStmt (
--- 11780,11791 ----
  
  	    TokenId after_macro = lexer.peek_token ()->get_id ();
  
! 	    AST::DelimType delim_type = invoc->get_invoc_data ()
! 					  .get_delim_tok_tree ()
! 					  .get_delim_type ();
! 
! 	    if (delim_type == AST::CURLY && after_macro != DOT
! 		&& after_macro != QUESTION_MARK)
  	      {
  		rust_debug ("braced macro statement");
  		return ExprOrStmt (
*************** Parser<ManagedTokenSource>::parse_expr (
*** 12149,12168 ****
  	return nullptr;
      }
  
-   if (current_token->get_id () == LEFT_SHIFT)
-     {
-       lexer.split_current_token (LEFT_ANGLE, LEFT_ANGLE);
-       current_token = lexer.peek_token ();
-     }
- 
-   lexer.skip_token ();
- 
    ParseRestrictions null_denotation_restrictions = restrictions;
    null_denotation_restrictions.expr_can_be_stmt = false;
  
    // parse null denotation (unary part of expression)
    std::unique_ptr<AST::Expr> expr
!     = null_denotation (current_token, {}, null_denotation_restrictions);
  
    return left_denotations (std::move (expr), right_binding_power,
  			   std::move (outer_attrs), restrictions);
--- 12160,12171 ----
  	return nullptr;
      }
  
    ParseRestrictions null_denotation_restrictions = restrictions;
    null_denotation_restrictions.expr_can_be_stmt = false;
  
    // parse null denotation (unary part of expression)
    std::unique_ptr<AST::Expr> expr
!     = null_denotation ({}, null_denotation_restrictions);
  
    return left_denotations (std::move (expr), right_binding_power,
  			   std::move (outer_attrs), restrictions);
*************** Parser<ManagedTokenSource>::parse_expr (
*** 12230,12237 ****
  /* Determines action to take when finding token at beginning of expression. */
  template <typename ManagedTokenSource>
  std::unique_ptr<AST::Expr>
! Parser<ManagedTokenSource>::null_denotation (const_TokenPtr tok,
! 					     AST::AttrVec outer_attrs,
  					     ParseRestrictions restrictions)
  {
    /* note: tok is previous character in input stream, not current one, as
--- 12233,12239 ----
  /* Determines action to take when finding token at beginning of expression. */
  template <typename ManagedTokenSource>
  std::unique_ptr<AST::Expr>
! Parser<ManagedTokenSource>::null_denotation (AST::AttrVec outer_attrs,
  					     ParseRestrictions restrictions)
  {
    /* note: tok is previous character in input stream, not current one, as
*************** Parser<ManagedTokenSource>::null_denotat
*** 12241,12246 ****
--- 12243,12250 ----
     * denotation and then a left denotation), null denotations handle primaries
     * and unary operands (but only prefix unary operands) */
  
+   auto tok = lexer.peek_token ();
+ 
    switch (tok->get_id ())
      {
      case IDENTIFIER:
*************** Parser<ManagedTokenSource>::null_denotat
*** 12249,12276 ****
      case DOLLAR_SIGN:
      case CRATE:
      case SUPER:
        {
  	// DEBUG
  	rust_debug ("beginning null denotation identifier handling");
  
  	/* best option: parse as path, then extract identifier, macro,
  	 * struct/enum, or just path info from it */
! 	AST::PathInExpression path = parse_path_in_expression_pratt (tok);
  
  	return null_denotation_path (std::move (path), std::move (outer_attrs),
  				     restrictions);
        }
-     case SCOPE_RESOLUTION:
-       {
- 	// TODO: fix: this is for global paths, i.e. std::string::whatever
- 	Error error (tok->get_locus (),
- 		     "found null denotation scope resolution operator, and "
- 		     "have not written handling for it");
- 	add_error (std::move (error));
- 
- 	return nullptr;
-       }
      default:
        return null_denotation_not_path (std::move (tok), std::move (outer_attrs),
  				       restrictions);
      }
--- 12253,12278 ----
      case DOLLAR_SIGN:
      case CRATE:
      case SUPER:
+     case SCOPE_RESOLUTION:
        {
  	// DEBUG
  	rust_debug ("beginning null denotation identifier handling");
  
  	/* best option: parse as path, then extract identifier, macro,
  	 * struct/enum, or just path info from it */
! 	AST::PathInExpression path = parse_path_in_expression ();
  
  	return null_denotation_path (std::move (path), std::move (outer_attrs),
  				     restrictions);
        }
      default:
+       if (tok->get_id () == LEFT_SHIFT)
+ 	{
+ 	  lexer.split_current_token (LEFT_ANGLE, LEFT_ANGLE);
+ 	  tok = lexer.peek_token ();
+ 	}
+ 
+       lexer.skip_token ();
        return null_denotation_not_path (std::move (tok), std::move (outer_attrs),
  				       restrictions);
      }
*************** Parser<ManagedTokenSource>::left_denotat
*** 13035,13046 ****
        // array or slice index expression (pseudo binary infix)
        return parse_index_expr (tok, std::move (left), std::move (outer_attrs),
  			       restrictions);
-     case FLOAT_LITERAL:
-       /* HACK: get around lexer mis-identifying '.0' or '.1' or whatever as a
-        * float literal - TODO does this happen anymore? It shouldn't. */
-       return parse_tuple_index_expr_float (tok, std::move (left),
- 					   std::move (outer_attrs),
- 					   restrictions);
      default:
        add_error (Error (tok->get_locus (),
  			"found unexpected token %qs in left denotation",
--- 13037,13042 ----
*************** Parser<ManagedTokenSource>::parse_struct
*** 14436,14554 ****
  		       std::move (outer_attrs), path_locus));
  }
  
- /* Parses a path in expression with the first token passed as a parameter (as
-  * it is skipped in token stream). Note that this only parses segment-first
-  * paths, not global ones. */
- template <typename ManagedTokenSource>
- AST::PathInExpression
- Parser<ManagedTokenSource>::parse_path_in_expression_pratt (const_TokenPtr tok)
- {
-   // HACK-y way of making up for pratt-parsing consuming first token
- 
-   // DEBUG
-   rust_debug ("current peek token when starting path pratt parse: '%s'",
- 	      lexer.peek_token ()->get_token_description ());
- 
-   // create segment vector
-   std::vector<AST::PathExprSegment> segments;
- 
-   std::string initial_str;
- 
-   switch (tok->get_id ())
-     {
-     case IDENTIFIER:
-       initial_str = tok->get_str ();
-       break;
-     case SUPER:
-       initial_str = Values::Keywords::SUPER;
-       break;
-     case SELF:
-       initial_str = Values::Keywords::SELF;
-       break;
-     case SELF_ALIAS:
-       initial_str = Values::Keywords::SELF_ALIAS;
-       break;
-     case CRATE:
-       initial_str = Values::Keywords::CRATE;
-       break;
-     case DOLLAR_SIGN:
-       if (lexer.peek_token ()->get_id () == CRATE)
- 	{
- 	  initial_str = "$crate";
- 	  break;
- 	}
-       gcc_fallthrough ();
-     default:
-       add_error (Error (tok->get_locus (),
- 			"unrecognised token %qs in path in expression",
- 			tok->get_token_description ()));
- 
-       return AST::PathInExpression::create_error ();
-     }
- 
-   // parse required initial segment
-   AST::PathExprSegment initial_segment (initial_str, tok->get_locus ());
-   // parse generic args (and turbofish), if they exist
-   /* use lookahead to determine if they actually exist (don't want to
-    * accidently parse over next ident segment) */
-   if (lexer.peek_token ()->get_id () == SCOPE_RESOLUTION
-       && lexer.peek_token (1)->get_id () == LEFT_ANGLE)
-     {
-       // skip scope resolution
-       lexer.skip_token ();
- 
-       AST::GenericArgs generic_args = parse_path_generic_args ();
- 
-       initial_segment
- 	= AST::PathExprSegment (AST::PathIdentSegment (initial_str,
- 						       tok->get_locus ()),
- 				tok->get_locus (), std::move (generic_args));
-     }
-   if (initial_segment.is_error ())
-     {
-       // skip after somewhere?
-       // don't necessarily throw error but yeah
- 
-       // DEBUG
-       rust_debug ("initial segment is error - returning null");
- 
-       return AST::PathInExpression::create_error ();
-     }
-   segments.push_back (std::move (initial_segment));
- 
-   // parse optional segments (as long as scope resolution operator exists)
-   const_TokenPtr t = lexer.peek_token ();
-   while (t->get_id () == SCOPE_RESOLUTION)
-     {
-       // skip scope resolution operator
-       lexer.skip_token ();
- 
-       // parse the actual segment - it is an error if it doesn't exist now
-       AST::PathExprSegment segment = parse_path_expr_segment ();
-       if (segment.is_error ())
- 	{
- 	  // skip after somewhere?
- 	  Error error (t->get_locus (),
- 		       "could not parse path expression segment");
- 	  add_error (std::move (error));
- 
- 	  return AST::PathInExpression::create_error ();
- 	}
- 
-       segments.push_back (std::move (segment));
- 
-       t = lexer.peek_token ();
-     }
- 
-   // DEBUG:
-   rust_debug (
-     "current token (just about to return path to null denotation): '%s'",
-     lexer.peek_token ()->get_token_description ());
- 
-   return AST::PathInExpression (std::move (segments), {}, tok->get_locus (),
- 				false);
- }
- 
  // Parses a closure expression with pratt parsing (from null denotation).
  template <typename ManagedTokenSource>
  std::unique_ptr<AST::ClosureExpr>
--- 14432,14437 ----
*************** Parser<ManagedTokenSource>::parse_closur
*** 14686,14720 ****
      }
  }
  
- /* Parses a tuple index expression (pratt-parsed) from a 'float' token as a
-  * result of lexer misidentification. */
- template <typename ManagedTokenSource>
- std::unique_ptr<AST::TupleIndexExpr>
- Parser<ManagedTokenSource>::parse_tuple_index_expr_float (
-   const_TokenPtr tok, std::unique_ptr<AST::Expr> tuple_expr,
-   AST::AttrVec outer_attrs, ParseRestrictions restrictions ATTRIBUTE_UNUSED)
- {
-   // only works on float literals
-   if (tok->get_id () != FLOAT_LITERAL)
-     return nullptr;
- 
-   // DEBUG:
-   rust_debug ("exact string form of float: '%s'", tok->get_str ().c_str ());
- 
-   // get float string and remove dot and initial 0
-   std::string index_str = tok->get_str ();
-   index_str.erase (index_str.begin ());
- 
-   // get int from string
-   int index = atoi (index_str.c_str ());
- 
-   location_t locus = tuple_expr->get_locus ();
- 
-   return std::unique_ptr<AST::TupleIndexExpr> (
-     new AST::TupleIndexExpr (std::move (tuple_expr), index,
- 			     std::move (outer_attrs), locus));
- }
- 
  // Returns true if the next token is END, ELSE, or EOF;
  template <typename ManagedTokenSource>
  bool
--- 14569,14574 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/parse/rust-parse.h gcc-16-20251102/gcc/rust/parse/rust-parse.h
*** gcc-16-20251026/gcc/rust/parse/rust-parse.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/parse/rust-parse.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 212,217 ****
--- 212,222 ----
    std::unique_ptr<AST::MacroInvocation>
    parse_macro_invocation (AST::AttrVec outer_attrs);
  
+   /*
+    * This has to be public for parsing expressions with outer attributes
+    */
+   AST::AttrVec parse_outer_attributes ();
+ 
  private:
    void skip_after_semicolon ();
    void skip_after_end ();
*************** private:
*** 228,234 ****
  
    // AST-related stuff - maybe move or something?
    AST::Attribute parse_inner_attribute ();
-   AST::AttrVec parse_outer_attributes ();
    AST::Attribute parse_outer_attribute ();
    std::unique_ptr<AST::AttrInput> parse_attr_input ();
    std::tuple<AST::SimplePath, std::unique_ptr<AST::AttrInput>, location_t>
--- 233,238 ----
*************** private:
*** 368,374 ****
  					   AST::AttrVec outer_attrs);
    std::unique_ptr<AST::TraitItemType>
    parse_trait_type (AST::AttrVec outer_attrs, AST::Visibility);
!   std::unique_ptr<AST::TraitItemConst>
    parse_trait_const (AST::AttrVec outer_attrs);
  
    tl::expected<std::unique_ptr<AST::Param>, ParseSelfError> parse_self_param ();
--- 372,378 ----
  					   AST::AttrVec outer_attrs);
    std::unique_ptr<AST::TraitItemType>
    parse_trait_type (AST::AttrVec outer_attrs, AST::Visibility);
!   std::unique_ptr<AST::ConstantItem>
    parse_trait_const (AST::AttrVec outer_attrs);
  
    tl::expected<std::unique_ptr<AST::Param>, ParseSelfError> parse_self_param ();
*************** private:
*** 393,399 ****
  	      AST::AttrVec outer_attrs = AST::AttrVec (),
  	      ParseRestrictions restrictions = ParseRestrictions ());
    std::unique_ptr<AST::Expr>
!   null_denotation (const_TokenPtr t, AST::AttrVec outer_attrs = AST::AttrVec (),
  		   ParseRestrictions restrictions = ParseRestrictions ());
    std::unique_ptr<AST::Expr>
    null_denotation_path (AST::PathInExpression path, AST::AttrVec outer_attrs,
--- 397,403 ----
  	      AST::AttrVec outer_attrs = AST::AttrVec (),
  	      ParseRestrictions restrictions = ParseRestrictions ());
    std::unique_ptr<AST::Expr>
!   null_denotation (AST::AttrVec outer_attrs = AST::AttrVec (),
  		   ParseRestrictions restrictions = ParseRestrictions ());
    std::unique_ptr<AST::Expr>
    null_denotation_path (AST::PathInExpression path, AST::AttrVec outer_attrs,
*************** private:
*** 598,604 ****
    std::unique_ptr<AST::CallExpr>
    parse_struct_expr_tuple_partial (AST::PathInExpression path,
  				   AST::AttrVec outer_attrs);
-   AST::PathInExpression parse_path_in_expression_pratt (const_TokenPtr tok);
    std::unique_ptr<AST::ClosureExpr>
    parse_closure_expr_pratt (const_TokenPtr tok,
  			    AST::AttrVec outer_attrs = AST::AttrVec ());
--- 602,607 ----
*************** private:
*** 782,788 ****
  
    // don't want to make things *only* AttributeParser uses public
    // TODO: fold more of AttributeParser into Parser?
!   friend class ::Rust::AST::AttributeParser;
  };
  
  std::string extract_module_path (const AST::AttrVec &inner_attrs,
--- 785,791 ----
  
    // don't want to make things *only* AttributeParser uses public
    // TODO: fold more of AttributeParser into Parser?
!   friend struct ::Rust::AST::AttributeParser;
  };
  
  std::string extract_module_path (const AST::AttrVec &inner_attrs,
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-base.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-base.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-base.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-base.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,691 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast-resolve-expr.h"
- #include "rust-ast-resolve-path.h"
- #include "rust-item.h"
- #include "rust-path.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- bool
- ResolverBase::resolve_visibility (const AST::Visibility &vis)
- {
-   if (vis.has_path ())
-     {
-       auto path = vis.get_path ();
-       ResolvePath::go (path);
- 
-       // Do we need to lookup something here?
-       // Is it just about resolving the names correctly so we can look them up
-       // later?
-     }
- 
-   return true;
- }
- 
- // Default visitors implementations
- 
- void
- ResolverBase::visit (AST::Token &)
- {}
- 
- void
- ResolverBase::visit (AST::DelimTokenTree &)
- {}
- 
- void
- ResolverBase::visit (AST::AttrInputMetaItemContainer &)
- {}
- 
- void
- ResolverBase::visit (AST::IdentifierExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::Lifetime &)
- {}
- 
- void
- ResolverBase::visit (AST::LifetimeParam &)
- {}
- 
- void
- ResolverBase::visit (AST::ConstGenericParam &)
- {}
- 
- void
- ResolverBase::visit (AST::PathInExpression &)
- {}
- 
- void
- ResolverBase::visit (AST::TypePathSegment &)
- {}
- 
- void
- ResolverBase::visit (AST::TypePathSegmentGeneric &)
- {}
- 
- void
- ResolverBase::visit (AST::TypePathSegmentFunction &)
- {}
- 
- void
- ResolverBase::visit (AST::TypePath &)
- {}
- 
- void
- ResolverBase::visit (AST::QualifiedPathInExpression &)
- {}
- 
- void
- ResolverBase::visit (AST::QualifiedPathInType &)
- {}
- 
- void
- ResolverBase::visit (AST::LiteralExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::AttrInputLiteral &)
- {}
- 
- void
- ResolverBase::visit (AST::AttrInputMacro &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaItemLitExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaItemPathExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::BorrowExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::DereferenceExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ErrorPropagationExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::NegationExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ArithmeticOrLogicalExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ComparisonExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::LazyBooleanExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::TypeCastExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::AssignmentExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::CompoundAssignmentExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::GroupedExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ArrayElemsValues &)
- {}
- 
- void
- ResolverBase::visit (AST::ArrayElemsCopied &)
- {}
- 
- void
- ResolverBase::visit (AST::ArrayExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ArrayIndexExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleIndexExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::StructExprStruct &)
- {}
- 
- void
- ResolverBase::visit (AST::StructExprFieldIdentifier &)
- {}
- 
- void
- ResolverBase::visit (AST::StructExprFieldIdentifierValue &)
- {}
- 
- void
- ResolverBase::visit (AST::StructExprFieldIndexValue &)
- {}
- 
- void
- ResolverBase::visit (AST::StructExprStructFields &)
- {}
- 
- void
- ResolverBase::visit (AST::StructExprStructBase &)
- {}
- 
- void
- ResolverBase::visit (AST::CallExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::MethodCallExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::FieldAccessExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ClosureExprInner &)
- {}
- 
- void
- ResolverBase::visit (AST::BlockExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::AnonConst &)
- {}
- 
- void
- ResolverBase::visit (AST::ConstBlock &)
- {}
- 
- void
- ResolverBase::visit (AST::ClosureExprInnerTyped &)
- {}
- 
- void
- ResolverBase::visit (AST::ContinueExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::BreakExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::RangeFromToExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::RangeFromExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::RangeToExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::RangeFullExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::RangeFromToInclExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::RangeToInclExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::BoxExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ReturnExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::TryExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::UnsafeBlockExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::LoopExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::WhileLoopExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::WhileLetLoopExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::ForLoopExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::IfExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::IfExprConseqElse &)
- {}
- 
- void
- ResolverBase::visit (AST::IfLetExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::IfLetExprConseqElse &)
- {}
- 
- void
- ResolverBase::visit (AST::MatchExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::AwaitExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::AsyncBlockExpr &)
- {}
- 
- void
- ResolverBase::visit (AST::InlineAsm &)
- {}
- 
- void
- ResolverBase::visit (AST::LlvmInlineAsm &)
- {}
- 
- void
- ResolverBase::visit (AST::TypeParam &)
- {}
- 
- void
- ResolverBase::visit (AST::LifetimeWhereClauseItem &)
- {}
- 
- void
- ResolverBase::visit (AST::TypeBoundWhereClauseItem &)
- {}
- 
- void
- ResolverBase::visit (AST::Module &)
- {}
- 
- void
- ResolverBase::visit (AST::ExternCrate &)
- {}
- 
- void
- ResolverBase::visit (AST::UseTreeGlob &)
- {}
- 
- void
- ResolverBase::visit (AST::UseTreeList &)
- {}
- 
- void
- ResolverBase::visit (AST::UseTreeRebind &)
- {}
- 
- void
- ResolverBase::visit (AST::UseDeclaration &)
- {}
- 
- void
- ResolverBase::visit (AST::Function &)
- {}
- 
- void
- ResolverBase::visit (AST::TypeAlias &)
- {}
- 
- void
- ResolverBase::visit (AST::StructStruct &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleStruct &)
- {}
- 
- void
- ResolverBase::visit (AST::EnumItem &)
- {}
- 
- void
- ResolverBase::visit (AST::EnumItemTuple &)
- {}
- 
- void
- ResolverBase::visit (AST::EnumItemStruct &)
- {}
- 
- void
- ResolverBase::visit (AST::EnumItemDiscriminant &)
- {}
- 
- void
- ResolverBase::visit (AST::Enum &)
- {}
- 
- void
- ResolverBase::visit (AST::Union &)
- {}
- 
- void
- ResolverBase::visit (AST::ConstantItem &)
- {}
- 
- void
- ResolverBase::visit (AST::StaticItem &)
- {}
- 
- void
- ResolverBase::visit (AST::TraitItemConst &)
- {}
- 
- void
- ResolverBase::visit (AST::TraitItemType &)
- {}
- 
- void
- ResolverBase::visit (AST::Trait &)
- {}
- 
- void
- ResolverBase::visit (AST::InherentImpl &)
- {}
- 
- void
- ResolverBase::visit (AST::TraitImpl &)
- {}
- 
- void
- ResolverBase::visit (AST::ExternalTypeItem &)
- {}
- 
- void
- ResolverBase::visit (AST::ExternalStaticItem &)
- {}
- 
- void
- ResolverBase::visit (AST::ExternBlock &)
- {}
- 
- void
- ResolverBase::visit (AST::MacroMatchFragment &)
- {}
- 
- void
- ResolverBase::visit (AST::MacroMatchRepetition &)
- {}
- 
- void
- ResolverBase::visit (AST::MacroMatcher &)
- {}
- 
- void
- ResolverBase::visit (AST::MacroRulesDefinition &)
- {}
- 
- void
- ResolverBase::visit (AST::MacroInvocation &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaItemPath &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaItemSeq &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaWord &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaNameValueStr &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaListPaths &)
- {}
- 
- void
- ResolverBase::visit (AST::MetaListNameValueStr &)
- {}
- 
- void
- ResolverBase::visit (AST::LiteralPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::IdentifierPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::WildcardPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::RestPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::RangePatternBoundLiteral &)
- {}
- 
- void
- ResolverBase::visit (AST::RangePatternBoundPath &)
- {}
- 
- void
- ResolverBase::visit (AST::RangePatternBoundQualPath &)
- {}
- 
- void
- ResolverBase::visit (AST::RangePattern &)
- {}
- 
- void
- ResolverBase::visit (AST::ReferencePattern &)
- {}
- 
- void
- ResolverBase::visit (AST::StructPatternFieldTuplePat &)
- {}
- 
- void
- ResolverBase::visit (AST::StructPatternFieldIdentPat &)
- {}
- 
- void
- ResolverBase::visit (AST::StructPatternFieldIdent &)
- {}
- 
- void
- ResolverBase::visit (AST::StructPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleStructItemsNoRange &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleStructItemsRange &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleStructPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::TuplePatternItemsMultiple &)
- {}
- 
- void
- ResolverBase::visit (AST::TuplePatternItemsRanged &)
- {}
- 
- void
- ResolverBase::visit (AST::TuplePattern &)
- {}
- 
- void
- ResolverBase::visit (AST::GroupedPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::SlicePatternItemsNoRest &)
- {}
- 
- void
- ResolverBase::visit (AST::SlicePatternItemsHasRest &)
- {}
- 
- void
- ResolverBase::visit (AST::SlicePattern &)
- {}
- 
- void
- ResolverBase::visit (AST::AltPattern &)
- {}
- 
- void
- ResolverBase::visit (AST::EmptyStmt &)
- {}
- 
- void
- ResolverBase::visit (AST::LetStmt &)
- {}
- 
- void
- ResolverBase::visit (AST::ExprStmt &)
- {}
- 
- void
- ResolverBase::visit (AST::TraitBound &)
- {}
- 
- void
- ResolverBase::visit (AST::ImplTraitType &)
- {}
- 
- void
- ResolverBase::visit (AST::TraitObjectType &)
- {}
- 
- void
- ResolverBase::visit (AST::ParenthesisedType &)
- {}
- 
- void
- ResolverBase::visit (AST::ImplTraitTypeOneBound &)
- {}
- 
- void
- ResolverBase::visit (AST::TraitObjectTypeOneBound &)
- {}
- 
- void
- ResolverBase::visit (AST::TupleType &)
- {}
- 
- void
- ResolverBase::visit (AST::NeverType &)
- {}
- 
- void
- ResolverBase::visit (AST::RawPointerType &)
- {}
- 
- void
- ResolverBase::visit (AST::ReferenceType &)
- {}
- 
- void
- ResolverBase::visit (AST::ArrayType &)
- {}
- 
- void
- ResolverBase::visit (AST::SliceType &)
- {}
- 
- void
- ResolverBase::visit (AST::InferredType &)
- {}
- 
- void
- ResolverBase::visit (AST::BareFunctionType &)
- {}
- 
- void
- ResolverBase::visit (AST::SelfParam &)
- {}
- 
- void
- ResolverBase::visit (AST::VariadicParam &)
- {}
- 
- void
- ResolverBase::visit (AST::FunctionParam &)
- {}
- 
- void
- ResolverBase::visit (AST::FormatArgs &fmt)
- {}
- 
- void
- ResolverBase::visit (AST::OffsetOf &offset_of)
- {}
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-base.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-base.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-base.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-base.h	Thu Jan  1 00:00:00 1970
***************
*** 1,238 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_BASE_H
- #define RUST_AST_RESOLVE_BASE_H
- 
- #include "rust-ast-visitor.h"
- #include "rust-ast.h"
- #include "rust-builtin-ast-nodes.h"
- #include "rust-expr.h"
- #include "rust-name-resolver.h"
- #include "rust-diagnostics.h"
- #include "rust-location.h"
- 
- namespace Rust {
- namespace Resolver {
- inline void
- redefined_error (const rich_location &loc)
- {
-   rust_error_at (loc, "redefined multiple times");
- }
- 
- class ResolverBase : public AST::ASTVisitor
- {
- public:
-   virtual ~ResolverBase () {}
- 
-   void visit (AST::Token &);
-   void visit (AST::DelimTokenTree &);
-   void visit (AST::AttrInputMetaItemContainer &);
-   void visit (AST::IdentifierExpr &);
-   void visit (AST::Lifetime &);
-   void visit (AST::LifetimeParam &);
-   void visit (AST::ConstGenericParam &);
-   void visit (AST::PathInExpression &);
-   void visit (AST::TypePathSegment &);
-   void visit (AST::TypePathSegmentGeneric &);
-   void visit (AST::TypePathSegmentFunction &);
-   void visit (AST::TypePath &);
-   void visit (AST::QualifiedPathInExpression &);
-   void visit (AST::QualifiedPathInType &);
-   void visit (AST::LiteralExpr &);
-   void visit (AST::AttrInputLiteral &);
-   void visit (AST::AttrInputMacro &);
-   void visit (AST::MetaItemLitExpr &);
-   void visit (AST::MetaItemPathExpr &);
-   void visit (AST::BorrowExpr &);
-   void visit (AST::DereferenceExpr &);
-   void visit (AST::ErrorPropagationExpr &);
-   void visit (AST::NegationExpr &);
-   void visit (AST::ArithmeticOrLogicalExpr &);
-   void visit (AST::ComparisonExpr &);
-   void visit (AST::LazyBooleanExpr &);
-   void visit (AST::TypeCastExpr &);
-   void visit (AST::AssignmentExpr &);
-   void visit (AST::CompoundAssignmentExpr &);
-   void visit (AST::GroupedExpr &);
-   void visit (AST::ArrayElemsValues &);
-   void visit (AST::ArrayElemsCopied &);
-   void visit (AST::ArrayExpr &);
-   void visit (AST::ArrayIndexExpr &);
-   void visit (AST::TupleExpr &);
-   void visit (AST::TupleIndexExpr &);
-   void visit (AST::StructExprStruct &);
-   void visit (AST::StructExprFieldIdentifier &);
-   void visit (AST::StructExprFieldIdentifierValue &);
-   void visit (AST::StructExprFieldIndexValue &);
-   void visit (AST::StructExprStructFields &);
-   void visit (AST::StructExprStructBase &);
-   void visit (AST::CallExpr &);
-   void visit (AST::MethodCallExpr &);
-   void visit (AST::FieldAccessExpr &);
-   void visit (AST::ClosureExprInner &);
-   void visit (AST::BlockExpr &);
-   void visit (AST::AnonConst &);
-   void visit (AST::ConstBlock &);
-   void visit (AST::ClosureExprInnerTyped &);
-   void visit (AST::ContinueExpr &);
-   void visit (AST::BreakExpr &);
-   void visit (AST::RangeFromToExpr &);
-   void visit (AST::RangeFromExpr &);
-   void visit (AST::RangeToExpr &);
-   void visit (AST::RangeFullExpr &);
-   void visit (AST::RangeFromToInclExpr &);
-   void visit (AST::RangeToInclExpr &);
-   void visit (AST::BoxExpr &);
-   void visit (AST::ReturnExpr &);
-   void visit (AST::TryExpr &);
-   void visit (AST::UnsafeBlockExpr &);
-   void visit (AST::LoopExpr &);
-   void visit (AST::WhileLoopExpr &);
-   void visit (AST::WhileLetLoopExpr &);
-   void visit (AST::ForLoopExpr &);
-   void visit (AST::IfExpr &);
-   void visit (AST::IfExprConseqElse &);
-   void visit (AST::IfLetExpr &);
-   void visit (AST::IfLetExprConseqElse &);
- 
-   void visit (AST::MatchExpr &);
-   void visit (AST::AwaitExpr &);
-   void visit (AST::AsyncBlockExpr &);
-   void visit (AST::InlineAsm &);
-   void visit (AST::LlvmInlineAsm &);
- 
-   void visit (AST::TypeParam &);
- 
-   void visit (AST::LifetimeWhereClauseItem &);
-   void visit (AST::TypeBoundWhereClauseItem &);
-   void visit (AST::Module &);
-   void visit (AST::ExternCrate &);
- 
-   void visit (AST::UseTreeGlob &);
-   void visit (AST::UseTreeList &);
-   void visit (AST::UseTreeRebind &);
-   void visit (AST::UseDeclaration &);
-   void visit (AST::Function &);
-   void visit (AST::TypeAlias &);
-   void visit (AST::StructStruct &);
-   void visit (AST::TupleStruct &);
-   void visit (AST::EnumItem &);
-   void visit (AST::EnumItemTuple &);
-   void visit (AST::EnumItemStruct &);
-   void visit (AST::EnumItemDiscriminant &);
-   void visit (AST::Enum &);
-   void visit (AST::Union &);
-   void visit (AST::ConstantItem &);
-   void visit (AST::StaticItem &);
-   void visit (AST::TraitItemConst &);
-   void visit (AST::TraitItemType &);
-   void visit (AST::Trait &);
-   void visit (AST::InherentImpl &);
-   void visit (AST::TraitImpl &);
- 
-   void visit (AST::ExternalTypeItem &);
-   void visit (AST::ExternalStaticItem &);
-   void visit (AST::ExternBlock &);
- 
-   void visit (AST::MacroMatchFragment &);
-   void visit (AST::MacroMatchRepetition &);
-   void visit (AST::MacroMatcher &);
-   void visit (AST::MacroRulesDefinition &);
-   void visit (AST::MacroInvocation &);
-   void visit (AST::MetaItemPath &);
-   void visit (AST::MetaItemSeq &);
-   void visit (AST::MetaWord &);
-   void visit (AST::MetaNameValueStr &);
-   void visit (AST::MetaListPaths &);
-   void visit (AST::MetaListNameValueStr &);
- 
-   void visit (AST::LiteralPattern &);
-   void visit (AST::IdentifierPattern &);
-   void visit (AST::WildcardPattern &);
-   void visit (AST::RestPattern &);
- 
-   void visit (AST::RangePatternBoundLiteral &);
-   void visit (AST::RangePatternBoundPath &);
-   void visit (AST::RangePatternBoundQualPath &);
-   void visit (AST::RangePattern &);
-   void visit (AST::ReferencePattern &);
- 
-   void visit (AST::StructPatternFieldTuplePat &);
-   void visit (AST::StructPatternFieldIdentPat &);
-   void visit (AST::StructPatternFieldIdent &);
-   void visit (AST::StructPattern &);
- 
-   void visit (AST::TupleStructItemsNoRange &);
-   void visit (AST::TupleStructItemsRange &);
-   void visit (AST::TupleStructPattern &);
- 
-   void visit (AST::TuplePatternItemsMultiple &);
-   void visit (AST::TuplePatternItemsRanged &);
-   void visit (AST::TuplePattern &);
-   void visit (AST::GroupedPattern &);
-   void visit (AST::SlicePatternItemsNoRest &);
-   void visit (AST::SlicePatternItemsHasRest &);
-   void visit (AST::SlicePattern &);
-   void visit (AST::AltPattern &);
- 
-   void visit (AST::EmptyStmt &);
-   void visit (AST::LetStmt &);
-   void visit (AST::ExprStmt &);
- 
-   void visit (AST::TraitBound &);
-   void visit (AST::ImplTraitType &);
-   void visit (AST::TraitObjectType &);
-   void visit (AST::ParenthesisedType &);
-   void visit (AST::ImplTraitTypeOneBound &);
-   void visit (AST::TraitObjectTypeOneBound &);
-   void visit (AST::TupleType &);
-   void visit (AST::NeverType &);
-   void visit (AST::RawPointerType &);
-   void visit (AST::ReferenceType &);
-   void visit (AST::ArrayType &);
-   void visit (AST::SliceType &);
-   void visit (AST::InferredType &);
-   void visit (AST::BareFunctionType &);
-   void visit (AST::FunctionParam &param);
-   void visit (AST::VariadicParam &param);
-   void visit (AST::SelfParam &param);
- 
-   void visit (AST::FormatArgs &fmt);
-   void visit (AST::OffsetOf &offset_of);
- 
- protected:
-   ResolverBase ()
-     : resolver (Resolver::get ()), mappings (Analysis::Mappings::get ()),
-       resolved_node (UNKNOWN_NODEID)
-   {}
- 
-   /**
-    * Resolve a visibility's path through the name resolver
-    */
-   bool resolve_visibility (const AST::Visibility &vis);
- 
-   Resolver *resolver;
-   Analysis::Mappings &mappings;
-   NodeId resolved_node;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_BASE_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-expr.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-expr.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-expr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-expr.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,816 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-expr.h"
- #include "rust-ast-resolve-stmt.h"
- #include "rust-ast-resolve-struct-expr-field.h"
- #include "rust-ast-resolve-type.h"
- #include "rust-ast-resolve-pattern.h"
- #include "rust-ast-resolve-path.h"
- #include "rust-expr.h"
- #include "rust-ice-finalizer.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- void
- ResolveExpr::go (AST::Expr &expr, const CanonicalPath &prefix,
- 		 const CanonicalPath &canonical_prefix, bool funny_error)
- {
-   ResolveExpr resolver (prefix, canonical_prefix, funny_error);
-   expr.accept_vis (resolver);
- }
- 
- void
- ResolveExpr::visit (AST::TupleIndexExpr &expr)
- {
-   ResolveExpr::go (expr.get_tuple_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::TupleExpr &expr)
- {
-   if (expr.is_unit ())
-     return;
- 
-   for (auto &elem : expr.get_tuple_elems ())
-     ResolveExpr::go (*elem, prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::PathInExpression &expr)
- {
-   ResolvePath::go (expr);
- }
- 
- void
- ResolveExpr::visit (AST::QualifiedPathInExpression &expr)
- {
-   ResolvePath::go (expr);
- }
- 
- void
- ResolveExpr::visit (AST::ReturnExpr &expr)
- {
-   if (expr.has_returned_expr ())
-     ResolveExpr::go (expr.get_returned_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::CallExpr &expr)
- {
-   ResolveExpr::go (expr.get_function_expr (), prefix, canonical_prefix);
-   for (auto &param : expr.get_params ())
-     ResolveExpr::go (*param, prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::MethodCallExpr &expr)
- {
-   ResolveExpr::go (expr.get_receiver_expr (), prefix, canonical_prefix);
- 
-   if (expr.get_method_name ().has_generic_args ())
-     {
-       AST::GenericArgs &args = expr.get_method_name ().get_generic_args ();
-       ResolveGenericArgs::go (args, prefix, canonical_prefix);
-     }
- 
-   auto const &in_params = expr.get_params ();
-   for (auto &param : in_params)
-     ResolveExpr::go (*param, prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ErrorPropagationExpr &expr)
- {
-   ResolveExpr::go (expr.get_propagating_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::AssignmentExpr &expr)
- {
-   ResolveExpr::go (expr.get_left_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_right_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::IdentifierExpr &expr)
- {
-   if (resolver->get_name_scope ().lookup (
- 	CanonicalPath::new_seg (expr.get_node_id (), expr.as_string ()),
- 	&resolved_node))
-     {
-       resolver->insert_resolved_name (expr.get_node_id (), resolved_node);
-     }
-   else if (resolver->get_type_scope ().lookup (
- 	     CanonicalPath::new_seg (expr.get_node_id (), expr.as_string ()),
- 	     &resolved_node))
-     {
-       resolver->insert_resolved_type (expr.get_node_id (), resolved_node);
-     }
-   else if (funny_error)
-     {
-       /* This was a "break rust" or "break gcc", and the identifier failed to
- 	 resolve.  Emit a funny ICE.  We set the finalizer to our custom one,
- 	 and use the lower-level emit_diagnostic () instead of the more common
- 	 internal_error_no_backtrace () in order to pass our locus.  */
-       diagnostics::text_finalizer (global_dc) = funny_ice_text_finalizer;
-       emit_diagnostic (diagnostics::kind::ice_nobt, expr.get_locus (), -1,
- 		       "are you trying to break %s? how dare you?",
- 		       expr.as_string ().c_str ());
-     }
-   else
-     {
-       rust_error_at (expr.get_locus (), ErrorCode::E0425,
- 		     "cannot find value %qs in this scope",
- 		     expr.as_string ().c_str ());
-     }
- }
- 
- void
- ResolveExpr::visit (AST::ArithmeticOrLogicalExpr &expr)
- {
-   ResolveExpr::go (expr.get_left_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_right_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::CompoundAssignmentExpr &expr)
- {
-   ResolveExpr::go (expr.get_left_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_right_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ComparisonExpr &expr)
- {
-   ResolveExpr::go (expr.get_left_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_right_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::LazyBooleanExpr &expr)
- {
-   ResolveExpr::go (expr.get_left_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_right_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::NegationExpr &expr)
- {
-   ResolveExpr::go (expr.get_negated_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::TypeCastExpr &expr)
- {
-   ResolveType::go (expr.get_type_to_cast_to ());
-   ResolveExpr::go (expr.get_casted_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::IfExpr &expr)
- {
-   ResolveExpr::go (expr.get_condition_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_if_block (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::IfExprConseqElse &expr)
- {
-   ResolveExpr::go (expr.get_condition_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_if_block (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_else_block (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::IfLetExpr &expr)
- {
-   ResolveExpr::go (expr.get_value_expr (), prefix, canonical_prefix);
- 
-   NodeId scope_node_id = expr.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   // We know expr.get_patterns () has one pattern at most
-   // so there's no reason to handle it like an AltPattern.
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-   for (auto &pattern : expr.get_patterns ())
-     {
-       PatternDeclaration::go (*pattern, Rib::ItemType::Var, bindings);
-     }
- 
-   ResolveExpr::go (expr.get_if_block (), prefix, canonical_prefix);
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExpr::visit (AST::IfLetExprConseqElse &expr)
- {
-   ResolveExpr::go (expr.get_value_expr (), prefix, canonical_prefix);
- 
-   NodeId scope_node_id = expr.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   // We know expr.get_patterns () has one pattern at most
-   // so there's no reason to handle it like an AltPattern.
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-   for (auto &pattern : expr.get_patterns ())
-     {
-       PatternDeclaration::go (*pattern, Rib::ItemType::Var, bindings);
-     }
- 
-   ResolveExpr::go (expr.get_if_block (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_else_block (), prefix, canonical_prefix);
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExpr::visit (AST::BlockExpr &expr)
- {
-   NodeId scope_node_id = expr.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   if (expr.has_label ())
-     {
-       auto label = expr.get_label ();
-       if (label.get_lifetime ().get_lifetime_type ()
- 	  != AST::Lifetime::LifetimeType::NAMED)
- 	{
- 	  rust_error_at (label.get_locus (),
- 			 "Labels must be a named lifetime value");
- 	  return;
- 	}
- 
-       auto label_name = label.get_lifetime ().get_lifetime_name ();
-       auto label_lifetime_node_id = label.get_lifetime ().get_node_id ();
-       resolver->get_label_scope ().insert (
- 	CanonicalPath::new_seg (label.get_node_id (), label_name),
- 	label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
- 	[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	  rust_error_at (label.get_locus (), "label defined multiple times");
- 	  rust_error_at (locus, "was defined here");
- 	});
-     }
- 
-   for (auto &s : expr.get_statements ())
-     {
-       if (s->is_item ())
- 	ResolveStmt::go (*s, prefix, canonical_prefix,
- 			 CanonicalPath::create_empty ());
-     }
- 
-   for (auto &s : expr.get_statements ())
-     {
-       if (!s->is_item ())
- 	ResolveStmt::go (*s, prefix, canonical_prefix,
- 			 CanonicalPath::create_empty ());
-     }
- 
-   if (expr.has_tail_expr ())
-     ResolveExpr::go (expr.get_tail_expr (), prefix, canonical_prefix);
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExpr::visit (AST::AnonConst &expr)
- {
-   ResolveExpr::go (expr.get_inner_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ConstBlock &expr)
- {
-   ResolveExpr::go (expr.get_const_expr (), prefix, canonical_prefix);
- }
- 
- void
- translate_operand (AST::InlineAsm &expr, const CanonicalPath &prefix,
- 		   const CanonicalPath &canonical_prefix)
- {
-   const auto &operands = expr.get_operands ();
-   using RegisterType = AST::InlineAsmOperand::RegisterType;
-   for (auto &operand : operands)
-     {
-       switch (operand.get_register_type ())
- 	{
- 	case RegisterType::In:
- 	  {
- 	    auto in = operand.get_in ();
- 	    ResolveExpr::go (*in.expr, prefix, canonical_prefix);
- 	    break;
- 	  }
- 	case RegisterType::Out:
- 	  {
- 	    auto out = operand.get_out ();
- 	    ResolveExpr::go (*out.expr, prefix, canonical_prefix);
- 	    break;
- 	  }
- 	case RegisterType::InOut:
- 	  {
- 	    auto in_out = operand.get_in_out ();
- 	    ResolveExpr::go (*in_out.expr, prefix, canonical_prefix);
- 	    break;
- 	  }
- 	case RegisterType::SplitInOut:
- 	  {
- 	    auto split_in_out = operand.get_split_in_out ();
- 	    ResolveExpr::go (*split_in_out.in_expr, prefix, canonical_prefix);
- 	    ResolveExpr::go (*split_in_out.out_expr, prefix, canonical_prefix);
- 	    break;
- 	  }
- 	case RegisterType::Const:
- 	  {
- 	    auto anon_const = operand.get_const ().anon_const;
- 	    ResolveExpr::go (anon_const.get_inner_expr (), prefix,
- 			     canonical_prefix);
- 	    break;
- 	  }
- 	case RegisterType::Sym:
- 	  {
- 	    auto sym = operand.get_sym ();
- 	    ResolveExpr::go (*sym.expr, prefix, canonical_prefix);
- 	    break;
- 	  }
- 	case RegisterType::Label:
- 	  {
- 	    auto label = operand.get_label ();
- 	    ResolveExpr::go (*label.expr, prefix, canonical_prefix);
- 	    break;
- 	  }
- 	}
-     }
- }
- void
- ResolveExpr::visit (AST::InlineAsm &expr)
- {
-   translate_operand (expr, prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::LlvmInlineAsm &expr)
- {
-   for (auto &output : expr.get_outputs ())
-     ResolveExpr::go (*output.expr, prefix, canonical_prefix);
- 
-   for (auto &input : expr.get_inputs ())
-     ResolveExpr::go (*input.expr, prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::UnsafeBlockExpr &expr)
- {
-   expr.get_block_expr ().accept_vis (*this);
- }
- 
- void
- ResolveExpr::visit (AST::ArrayElemsValues &elems)
- {
-   for (auto &elem : elems.get_values ())
-     ResolveExpr::go (*elem, prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ArrayExpr &expr)
- {
-   expr.get_array_elems ()->accept_vis (*this);
- }
- 
- void
- ResolveExpr::visit (AST::ArrayIndexExpr &expr)
- {
-   ResolveExpr::go (expr.get_array_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_index_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ArrayElemsCopied &expr)
- {
-   ResolveExpr::go (expr.get_num_copies (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_elem_to_copy (), prefix, canonical_prefix);
- }
- 
- // this this an empty struct constructor like 'S {}'
- void
- ResolveExpr::visit (AST::StructExprStruct &struct_expr)
- {
-   ResolveExpr::go (struct_expr.get_struct_name (), prefix, canonical_prefix);
- }
- 
- // this this a struct constructor with fields
- void
- ResolveExpr::visit (AST::StructExprStructFields &struct_expr)
- {
-   ResolveExpr::go (struct_expr.get_struct_name (), prefix, canonical_prefix);
- 
-   if (struct_expr.has_struct_base ())
-     {
-       AST::StructBase &base = struct_expr.get_struct_base ();
-       ResolveExpr::go (base.get_base_struct (), prefix, canonical_prefix);
-     }
- 
-   auto const &struct_fields = struct_expr.get_fields ();
-   for (auto &struct_field : struct_fields)
-     {
-       ResolveStructExprField::go (*struct_field, prefix, canonical_prefix);
-     }
- }
- 
- void
- ResolveExpr::visit (AST::GroupedExpr &expr)
- {
-   ResolveExpr::go (expr.get_expr_in_parens (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::FieldAccessExpr &expr)
- {
-   ResolveExpr::go (expr.get_receiver_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::LoopExpr &expr)
- {
-   if (expr.has_loop_label ())
-     {
-       auto label = expr.get_loop_label ();
-       if (label.get_lifetime ().get_lifetime_type ()
- 	  != AST::Lifetime::LifetimeType::NAMED)
- 	{
- 	  rust_error_at (label.get_locus (),
- 			 "Labels must be a named lifetime value");
- 	  return;
- 	}
- 
-       auto label_name = label.get_lifetime ().get_lifetime_name ();
-       auto label_lifetime_node_id = label.get_lifetime ().get_node_id ();
-       resolver->get_label_scope ().insert (
- 	CanonicalPath::new_seg (expr.get_node_id (), label_name),
- 	label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
- 	[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	  rust_error_at (label.get_locus (), "label defined multiple times");
- 	  rust_error_at (locus, "was defined here");
- 	});
-     }
-   ResolveExpr::go (expr.get_loop_block (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::BreakExpr &expr)
- {
-   if (expr.has_label ())
-     {
-       auto label = expr.get_label_unchecked ().get_lifetime ();
-       if (label.get_lifetime_type () != AST::Lifetime::LifetimeType::NAMED)
- 	{
- 	  rust_error_at (label.get_locus (),
- 			 "Labels must be a named lifetime value");
- 	  return;
- 	}
- 
-       NodeId resolved_node = UNKNOWN_NODEID;
-       if (!resolver->get_label_scope ().lookup (
- 	    CanonicalPath::new_seg (label.get_node_id (),
- 				    label.get_lifetime_name ()),
- 	    &resolved_node))
- 	{
- 	  rust_error_at (label.get_locus (), ErrorCode::E0426,
- 			 "use of undeclared label %qs",
- 			 label.as_string ().c_str ());
- 	  return;
- 	}
-       resolver->insert_resolved_label (label.get_node_id (), resolved_node);
-     }
- 
-   if (expr.has_break_expr ())
-     {
-       bool funny_error = false;
-       auto &break_expr = expr.get_break_expr ();
-       if (break_expr.get_expr_kind () == AST::Expr::Kind::Identifier)
- 	{
- 	  /* This is a break with an expression, and the expression is
- 	     just a single identifier.  See if the identifier is either
- 	     "rust" or "gcc", in which case we have "break rust" or "break
- 	     gcc", and so may need to emit our funny error.  We cannot yet
- 	     emit the error here though, because the identifier may still
- 	     be in scope, and ICE'ing on valid programs would not be very
- 	     funny.  */
- 	  std::string ident
- 	    = static_cast<AST::IdentifierExpr &> (break_expr).as_string ();
- 	  if (ident == "rust" || ident == "gcc")
- 	    funny_error = true;
- 	}
-       ResolveExpr::go (break_expr, prefix, canonical_prefix, funny_error);
-     }
- }
- 
- void
- ResolveExpr::visit (AST::WhileLoopExpr &expr)
- {
-   if (expr.has_loop_label ())
-     {
-       auto label = expr.get_loop_label ();
-       if (label.get_lifetime ().get_lifetime_type ()
- 	  != AST::Lifetime::LifetimeType::NAMED)
- 	{
- 	  rust_error_at (label.get_locus (),
- 			 "Labels must be a named lifetime value");
- 	  return;
- 	}
- 
-       auto label_name = label.get_lifetime ().get_lifetime_name ();
-       auto label_lifetime_node_id = label.get_lifetime ().get_node_id ();
-       resolver->get_label_scope ().insert (
- 	CanonicalPath::new_seg (label.get_node_id (), label_name),
- 	label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
- 	[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	  rust_error_at (label.get_locus (), "label defined multiple times");
- 	  rust_error_at (locus, "was defined here");
- 	});
-     }
- 
-   ResolveExpr::go (expr.get_predicate_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_loop_block (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ForLoopExpr &expr)
- {
-   if (expr.has_loop_label ())
-     {
-       auto label = expr.get_loop_label ();
-       if (label.get_lifetime ().get_lifetime_type ()
- 	  != AST::Lifetime::LifetimeType::NAMED)
- 	{
- 	  rust_error_at (label.get_locus (),
- 			 "Labels must be a named lifetime value");
- 	  return;
- 	}
- 
-       auto label_name = label.get_lifetime ().get_lifetime_name ();
-       auto label_lifetime_node_id = label.get_lifetime ().get_node_id ();
-       resolver->get_label_scope ().insert (
- 	CanonicalPath::new_seg (label.get_node_id (), label_name),
- 	label_lifetime_node_id, label.get_locus (), false, Rib::ItemType::Label,
- 	[&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	  rust_error_at (label.get_locus (), "label defined multiple times");
- 	  rust_error_at (locus, "was defined here");
- 	});
-     }
- 
-   // this needs a new rib to contain the pattern
-   NodeId scope_node_id = expr.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   // resolve the expression
-   PatternDeclaration::go (expr.get_pattern (), Rib::ItemType::Var);
-   ResolveExpr::go (expr.get_iterator_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_loop_block (), prefix, canonical_prefix);
- 
-   // done
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExpr::visit (AST::ContinueExpr &expr)
- {
-   if (expr.has_label ())
-     {
-       auto label = expr.get_label_unchecked ();
-       if (label.get_lifetime_type () != AST::Lifetime::LifetimeType::NAMED)
- 	{
- 	  rust_error_at (label.get_locus (),
- 			 "Labels must be a named lifetime value");
- 	  return;
- 	}
- 
-       NodeId resolved_node = UNKNOWN_NODEID;
-       if (!resolver->get_label_scope ().lookup (
- 	    CanonicalPath::new_seg (label.get_node_id (),
- 				    label.get_lifetime_name ()),
- 	    &resolved_node))
- 	{
- 	  rust_error_at (expr.get_label_unchecked ().get_locus (),
- 			 ErrorCode::E0426, "use of undeclared label %qs",
- 			 label.as_string ().c_str ());
- 	  return;
- 	}
-       resolver->insert_resolved_label (label.get_node_id (), resolved_node);
-     }
- }
- 
- void
- ResolveExpr::visit (AST::BorrowExpr &expr)
- {
-   ResolveExpr::go (expr.get_borrowed_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::DereferenceExpr &expr)
- {
-   ResolveExpr::go (expr.get_dereferenced_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::MatchExpr &expr)
- {
-   ResolveExpr::go (expr.get_scrutinee_expr (), prefix, canonical_prefix);
-   for (auto &match_case : expr.get_match_cases ())
-     {
-       // each arm is in its own scope
-       NodeId scope_node_id = match_case.get_node_id ();
-       resolver->get_name_scope ().push (scope_node_id);
-       resolver->get_type_scope ().push (scope_node_id);
-       resolver->get_label_scope ().push (scope_node_id);
-       resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-       resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-       resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-       // resolve
-       AST::MatchArm &arm = match_case.get_arm ();
-       if (arm.has_match_arm_guard ())
- 	ResolveExpr::go (arm.get_guard_expr (), prefix, canonical_prefix);
- 
-       // We know expr.get_patterns () has one pattern at most
-       // so there's no reason to handle it like an AltPattern.
-       std::vector<PatternBinding> bindings
- 	= {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-       // insert any possible new patterns
-       for (auto &pattern : arm.get_patterns ())
- 	{
- 	  PatternDeclaration::go (*pattern, Rib::ItemType::Var, bindings);
- 	}
- 
-       // resolve the body
-       ResolveExpr::go (match_case.get_expr (), prefix, canonical_prefix);
- 
-       // done
-       resolver->get_name_scope ().pop ();
-       resolver->get_type_scope ().pop ();
-       resolver->get_label_scope ().pop ();
-     }
- }
- 
- void
- ResolveExpr::visit (AST::RangeFromToExpr &expr)
- {
-   ResolveExpr::go (expr.get_from_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_to_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::RangeFromExpr &expr)
- {
-   ResolveExpr::go (expr.get_from_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::RangeToExpr &expr)
- {
-   ResolveExpr::go (expr.get_to_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::RangeFullExpr &)
- {
-   // nothing to do
- }
- 
- void
- ResolveExpr::visit (AST::RangeFromToInclExpr &expr)
- {
-   ResolveExpr::go (expr.get_from_expr (), prefix, canonical_prefix);
-   ResolveExpr::go (expr.get_to_expr (), prefix, canonical_prefix);
- }
- 
- void
- ResolveExpr::visit (AST::ClosureExprInner &expr)
- {
-   NodeId scope_node_id = expr.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-   for (auto &p : expr.get_params ())
-     {
-       resolve_closure_param (p, bindings);
-     }
- 
-   resolver->push_closure_context (expr.get_node_id ());
- 
-   ResolveExpr::go (expr.get_definition_expr (), prefix, canonical_prefix);
- 
-   resolver->pop_closure_context ();
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExpr::visit (AST::ClosureExprInnerTyped &expr)
- {
-   NodeId scope_node_id = expr.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-   for (auto &p : expr.get_params ())
-     {
-       resolve_closure_param (p, bindings);
-     }
- 
-   ResolveType::go (expr.get_return_type ());
- 
-   resolver->push_closure_context (expr.get_node_id ());
- 
-   ResolveExpr::go (expr.get_definition_expr (), prefix, canonical_prefix);
- 
-   resolver->pop_closure_context ();
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExpr::resolve_closure_param (AST::ClosureParam &param,
- 				    std::vector<PatternBinding> &bindings)
- {
-   PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param, bindings);
- 
-   if (param.has_type_given ())
-     ResolveType::go (param.get_type ());
- }
- 
- ResolveExpr::ResolveExpr (const CanonicalPath &prefix,
- 			  const CanonicalPath &canonical_prefix,
- 			  bool funny_error)
-   : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix),
-     funny_error (funny_error)
- {}
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-expr.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-expr.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-expr.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-expr.h	Thu Jan  1 00:00:00 1970
***************
*** 1,105 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_EXPR_H
- #define RUST_AST_RESOLVE_EXPR_H
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast.h"
- #include "rust-ast-resolve-pattern.h"
- #include "rust-expr.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolveExpr : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::Expr &expr, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix,
- 		  bool funny_error = false);
- 
-   void visit (AST::TupleIndexExpr &expr) override;
-   void visit (AST::TupleExpr &expr) override;
-   void visit (AST::PathInExpression &expr) override;
-   void visit (AST::QualifiedPathInExpression &expr) override;
-   void visit (AST::ReturnExpr &expr) override;
-   void visit (AST::CallExpr &expr) override;
-   void visit (AST::MethodCallExpr &expr) override;
-   void visit (AST::AssignmentExpr &expr) override;
-   void visit (AST::IdentifierExpr &expr) override;
-   void visit (AST::ArithmeticOrLogicalExpr &expr) override;
-   void visit (AST::CompoundAssignmentExpr &expr) override;
-   void visit (AST::ComparisonExpr &expr) override;
-   void visit (AST::LazyBooleanExpr &expr) override;
-   void visit (AST::NegationExpr &expr) override;
-   void visit (AST::TypeCastExpr &expr) override;
-   void visit (AST::IfExpr &expr) override;
-   void visit (AST::IfExprConseqElse &expr) override;
-   void visit (AST::IfLetExpr &expr) override;
-   void visit (AST::IfLetExprConseqElse &expr) override;
-   void visit (AST::BlockExpr &expr) override;
-   void visit (AST::AnonConst &expr) override;
-   void visit (AST::ConstBlock &expr) override;
-   void visit (AST::InlineAsm &expr) override;
-   void visit (AST::LlvmInlineAsm &expr) override;
-   void visit (AST::UnsafeBlockExpr &expr) override;
-   void visit (AST::ArrayElemsValues &elems) override;
-   void visit (AST::ArrayExpr &expr) override;
-   void visit (AST::ArrayIndexExpr &expr) override;
-   void visit (AST::ArrayElemsCopied &elems) override;
-   void visit (AST::StructExprStruct &struct_expr) override;
-   void visit (AST::StructExprStructFields &struct_expr) override;
-   void visit (AST::GroupedExpr &expr) override;
-   void visit (AST::FieldAccessExpr &expr) override;
-   void visit (AST::LoopExpr &expr) override;
-   void visit (AST::BreakExpr &expr) override;
-   void visit (AST::WhileLoopExpr &expr) override;
-   void visit (AST::ForLoopExpr &expr) override;
-   void visit (AST::ContinueExpr &expr) override;
-   void visit (AST::BorrowExpr &expr) override;
-   void visit (AST::DereferenceExpr &expr) override;
-   void visit (AST::MatchExpr &expr) override;
-   void visit (AST::RangeFromToExpr &expr) override;
-   void visit (AST::RangeFromExpr &expr) override;
-   void visit (AST::RangeToExpr &expr) override;
-   void visit (AST::RangeFullExpr &expr) override;
-   void visit (AST::RangeFromToInclExpr &expr) override;
-   void visit (AST::ClosureExprInner &expr) override;
-   void visit (AST::ClosureExprInnerTyped &expr) override;
-   void visit (AST::ErrorPropagationExpr &expr) override;
- 
- protected:
-   void resolve_closure_param (AST::ClosureParam &param,
- 			      std::vector<PatternBinding> &bindings);
- 
- private:
-   ResolveExpr (const CanonicalPath &prefix,
- 	       const CanonicalPath &canonical_prefix, bool funny_error);
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
-   bool funny_error;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_EXPR_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-implitem.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-implitem.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-implitem.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-implitem.h	Thu Jan  1 00:00:00 1970
***************
*** 1,260 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_IMPLITEM_H
- #define RUST_AST_RESOLVE_IMPLITEM_H
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast-resolve-type.h"
- #include "rust-ast-full.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolveToplevelImplItem : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::AssociatedItem &item, const CanonicalPath &prefix)
-   {
-     if (item.is_marked_for_strip ())
-       return;
- 
-     ResolveToplevelImplItem resolver (prefix);
-     item.accept_vis (resolver);
-   }
- 
-   void visit (AST::TypeAlias &type) override
-   {
-     auto decl = CanonicalPath::new_seg (type.get_node_id (),
- 					type.get_new_type_name ().as_string ());
-     auto path = prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, type.get_node_id (), type.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, type.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
-   }
- 
-   void visit (AST::ConstantItem &constant) override
-   {
-     auto decl = CanonicalPath::new_seg (constant.get_node_id (),
- 					constant.get_identifier ());
-     auto path = prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, constant.get_node_id (), constant.get_locus (), false,
-       Rib::ItemType::Const,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, constant.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
-   }
- 
-   void visit (AST::Function &function) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (function.get_node_id (),
- 				function.get_function_name ().as_string ());
-     auto path = prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, function.get_node_id (), function.get_locus (), false,
-       Rib::ItemType::Function,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, function.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
-   }
- 
- private:
-   ResolveToplevelImplItem (const CanonicalPath &prefix)
-     : ResolverBase (), prefix (prefix)
-   {
-     rust_assert (!prefix.is_empty ());
-   }
- 
-   const CanonicalPath &prefix;
- };
- 
- class ResolveTopLevelTraitItems : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::AssociatedItem *item, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix)
-   {
-     ResolveTopLevelTraitItems resolver (prefix, canonical_prefix);
-     item->accept_vis (resolver);
-   };
- 
-   void visit (AST::Function &function) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (function.get_node_id (),
- 				function.get_function_name ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, function.get_node_id (), function.get_locus (), false,
-       Rib::ItemType::Function,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, function.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (function.get_node_id (), cpath);
-   }
- 
-   void visit (AST::TraitItemConst &constant) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (constant.get_node_id (),
- 				constant.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, constant.get_node_id (), constant.get_locus (), false,
-       Rib::ItemType::Const,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, constant.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (constant.get_node_id (), cpath);
-   }
- 
-   void visit (AST::TraitItemType &type) override
-   {
-     auto decl = CanonicalPath::new_seg (type.get_node_id (),
- 					type.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, type.get_node_id (), type.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, type.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (type.get_node_id (), cpath);
-   }
- 
- private:
-   ResolveTopLevelTraitItems (const CanonicalPath &prefix,
- 			     const CanonicalPath &canonical_prefix)
-     : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
-   {}
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- class ResolveToplevelExternItem : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::ExternalItem &item, const CanonicalPath &prefix)
-   {
-     ResolveToplevelExternItem resolver (prefix);
-     item.accept_vis (resolver);
-   };
- 
-   void visit (AST::Function &function) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (function.get_node_id (),
- 				function.get_function_name ().as_string ());
-     auto path = prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, function.get_node_id (), function.get_locus (), false,
-       Rib::ItemType::Function,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, function.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-   }
- 
-   void visit (AST::ExternalStaticItem &item) override
-   {
-     auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 					item.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false,
-       Rib::ItemType::Static,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-   }
- 
-   void visit (AST::ExternalTypeItem &type) override
-   {
-     auto decl = CanonicalPath::new_seg (type.get_node_id (),
- 					type.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, type.get_node_id (), type.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, type.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-   }
- 
- private:
-   ResolveToplevelExternItem (const CanonicalPath &prefix)
-     : ResolverBase (), prefix (prefix)
-   {}
- 
-   const CanonicalPath &prefix;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_IMPLITEM_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-item.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-item.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-item.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-item.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,1247 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-item.h"
- #include "rust-ast-full-decls.h"
- #include "rust-ast-resolve-toplevel.h"
- #include "rust-ast-resolve-type.h"
- #include "rust-ast-resolve-pattern.h"
- #include "rust-ast-resolve-path.h"
- 
- #include "rust-item.h"
- #include "selftest.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- ResolveTraitItems::ResolveTraitItems (const CanonicalPath &prefix,
- 				      const CanonicalPath &canonical_prefix)
-   : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
- {}
- 
- void
- ResolveTraitItems::go (AST::AssociatedItem *item, const CanonicalPath &prefix,
- 		       const CanonicalPath &canonical_prefix)
- {
-   if (item->is_marked_for_strip ())
-     return;
- 
-   ResolveTraitItems resolver (prefix, canonical_prefix);
-   item->accept_vis (resolver);
- }
- 
- void
- ResolveTraitItems::visit (AST::Function &function)
- {
-   auto decl
-     = CanonicalPath::new_seg (function.get_node_id (),
- 			      function.get_function_name ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (function.get_node_id (), cpath);
- 
-   NodeId scope_node_id = function.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   if (function.has_generics ())
-     ResolveGenericParams::go (function.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (function.has_return_type ())
-     ResolveType::go (function.get_return_type ());
- 
-   // self turns into (self: Self) as a function param
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-   // we make a new scope so the names of parameters are resolved and shadowed
-   // correctly
-   for (auto &p : function.get_function_params ())
-     {
-       if (p->is_variadic ())
- 	{
- 	  auto param = static_cast<AST::VariadicParam &> (*p);
- 	  PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param,
- 				  bindings);
- 	}
-       else if (p->is_self ())
- 	{
- 	  auto &param = static_cast<AST::SelfParam &> (*p);
- 	  // FIXME: which location should be used for Rust::Identifier `self`?
- 	  AST::IdentifierPattern self_pattern (
- 	    param.get_node_id (), {"self"}, param.get_locus (),
- 	    param.get_has_ref (), param.get_is_mut (),
- 	    std::unique_ptr<AST::Pattern> (nullptr));
- 
- 	  PatternDeclaration::go (self_pattern, Rib::ItemType::Param);
- 
- 	  if (param.has_type ())
- 	    {
- 	      // This shouldn't happen the parser should already error for this
- 	      rust_assert (!param.get_has_ref ());
- 	      ResolveType::go (param.get_type ());
- 	    }
- 	  else
- 	    {
- 	      // here we implicitly make self have a type path of Self
- 	      std::vector<std::unique_ptr<AST::TypePathSegment>> segments;
- 	      segments.push_back (std::unique_ptr<AST::TypePathSegment> (
- 		new AST::TypePathSegment ("Self", false, param.get_locus ())));
- 
- 	      AST::TypePath self_type_path (std::move (segments),
- 					    param.get_locus ());
- 	      ResolveType::go (self_type_path);
- 	    }
- 	}
-       else
- 	{
- 	  auto &param = static_cast<AST::FunctionParam &> (*p);
- 	  ResolveType::go (param.get_type ());
- 	  PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param,
- 				  bindings);
- 	}
-     }
- 
-   if (function.has_where_clause ())
-     ResolveWhereClause::Resolve (function.get_where_clause ());
- 
-   // trait items have an optional body
-   if (function.has_body ())
-     ResolveExpr::go (*function.get_definition ().value (), path, cpath);
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- void
- ResolveTraitItems::visit (AST::TraitItemType &type)
- {
-   auto decl = CanonicalPath::new_seg (type.get_node_id (),
- 				      type.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (type.get_node_id (), cpath);
- 
-   for (auto &bound : type.get_type_param_bounds ())
-     ResolveTypeBound::go (*bound);
- }
- 
- void
- ResolveTraitItems::visit (AST::TraitItemConst &constant)
- {
-   auto decl = CanonicalPath::new_seg (constant.get_node_id (),
- 				      constant.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (constant.get_node_id (), cpath);
- 
-   ResolveType::go (constant.get_type ());
- 
-   if (constant.has_expr ())
-     ResolveExpr::go (constant.get_expr (), path, cpath);
- }
- 
- ResolveItem::ResolveItem (const CanonicalPath &prefix,
- 			  const CanonicalPath &canonical_prefix)
-   : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
- {}
- 
- void
- ResolveItem::go (AST::Item &item, const CanonicalPath &prefix,
- 		 const CanonicalPath &canonical_prefix)
- {
-   ResolveItem resolver (prefix, canonical_prefix);
-   item.accept_vis (resolver);
- }
- 
- void
- ResolveItem::visit (AST::TypeAlias &alias)
- {
-   auto talias
-     = CanonicalPath::new_seg (alias.get_node_id (),
- 			      alias.get_new_type_name ().as_string ());
-   auto path = prefix.append (talias);
-   auto cpath = canonical_prefix.append (talias);
-   mappings.insert_canonical_path (alias.get_node_id (), cpath);
- 
-   NodeId scope_node_id = alias.get_node_id ();
-   resolver->get_type_scope ().push (scope_node_id);
- 
-   if (alias.has_generics ())
-     ResolveGenericParams::go (alias.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (alias.has_where_clause ())
-     ResolveWhereClause::Resolve (alias.get_where_clause ());
- 
-   ResolveType::go (alias.get_type_aliased ());
- 
-   resolver->get_type_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::Module &module)
- {
-   auto mod = CanonicalPath::new_seg (module.get_node_id (),
- 				     module.get_name ().as_string ());
-   auto path = prefix.append (mod);
-   auto cpath = canonical_prefix.append (mod);
-   mappings.insert_canonical_path (module.get_node_id (), cpath);
- 
-   resolve_visibility (module.get_visibility ());
- 
-   NodeId scope_node_id = module.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   // FIXME: Should we reinsert a child here? Any reason we ResolveTopLevel::go
-   // in ResolveTopLevel::visit (AST::Module) as well as here?
-   for (auto &item : module.get_items ())
-     ResolveTopLevel::go (*item, CanonicalPath::create_empty (), cpath);
- 
-   resolver->push_new_module_scope (module.get_node_id ());
-   for (auto &item : module.get_items ())
-     ResolveItem::go (*item, path, cpath);
- 
-   resolver->pop_module_scope ();
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::TupleStruct &struct_decl)
- {
-   auto decl
-     = CanonicalPath::new_seg (struct_decl.get_node_id (),
- 			      struct_decl.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (struct_decl.get_node_id (), cpath);
- 
-   resolve_visibility (struct_decl.get_visibility ());
- 
-   NodeId scope_node_id = struct_decl.get_node_id ();
-   resolver->get_type_scope ().push (scope_node_id);
- 
-   if (struct_decl.has_generics ())
-     ResolveGenericParams::go (struct_decl.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (struct_decl.has_where_clause ())
-     ResolveWhereClause::Resolve (struct_decl.get_where_clause ());
- 
-   for (AST::TupleField &field : struct_decl.get_fields ())
-     {
-       if (field.get_field_type ().is_marked_for_strip ())
- 	continue;
- 
-       resolve_visibility (field.get_visibility ());
- 
-       ResolveType::go (field.get_field_type ());
-     }
- 
-   resolver->get_type_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::Enum &enum_decl)
- {
-   auto decl = CanonicalPath::new_seg (enum_decl.get_node_id (),
- 				      enum_decl.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (enum_decl.get_node_id (), cpath);
- 
-   resolve_visibility (enum_decl.get_visibility ());
- 
-   NodeId scope_node_id = enum_decl.get_node_id ();
-   resolver->get_type_scope ().push (scope_node_id);
- 
-   if (enum_decl.has_generics ())
-     ResolveGenericParams::go (enum_decl.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (enum_decl.has_where_clause ())
-     ResolveWhereClause::Resolve (enum_decl.get_where_clause ());
- 
-   /* The actual fields are inside the variants.  */
-   for (auto &variant : enum_decl.get_variants ())
-     ResolveItem::go (*variant, path, cpath);
- 
-   resolver->get_type_scope ().pop ();
- }
- 
- /* EnumItem doesn't need to be handled, no fields.  */
- void
- ResolveItem::visit (AST::EnumItem &item)
- {
-   // Since at this point we cannot have visibilities on enum items anymore, we
-   // can skip handling them
- 
-   auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 				      item.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (item.get_node_id (), cpath);
- }
- 
- void
- ResolveItem::visit (AST::EnumItemTuple &item)
- {
-   auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 				      item.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-   for (auto &field : item.get_tuple_fields ())
-     {
-       if (field.get_field_type ().is_marked_for_strip ())
- 	continue;
- 
-       ResolveType::go (field.get_field_type ());
-     }
- }
- 
- void
- ResolveItem::visit (AST::EnumItemStruct &item)
- {
-   auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 				      item.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-   for (auto &field : item.get_struct_fields ())
-     {
-       if (field.get_field_type ().is_marked_for_strip ())
- 	continue;
- 
-       ResolveType::go (field.get_field_type ());
-     }
- }
- 
- void
- ResolveItem::visit (AST::EnumItemDiscriminant &item)
- {
-   auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 				      item.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
- 
-   mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-   ResolveExpr::go (item.get_expr (), path, cpath);
- }
- 
- void
- ResolveItem::visit (AST::StructStruct &struct_decl)
- {
-   auto decl
-     = CanonicalPath::new_seg (struct_decl.get_node_id (),
- 			      struct_decl.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (struct_decl.get_node_id (), cpath);
- 
-   resolve_visibility (struct_decl.get_visibility ());
- 
-   NodeId scope_node_id = struct_decl.get_node_id ();
-   resolver->get_type_scope ().push (scope_node_id);
- 
-   if (struct_decl.has_generics ())
-     ResolveGenericParams::go (struct_decl.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (struct_decl.has_where_clause ())
-     ResolveWhereClause::Resolve (struct_decl.get_where_clause ());
- 
-   for (AST::StructField &field : struct_decl.get_fields ())
-     {
-       if (field.get_field_type ().is_marked_for_strip ())
- 	continue;
- 
-       resolve_visibility (field.get_visibility ());
- 
-       ResolveType::go (field.get_field_type ());
-     }
- 
-   resolver->get_type_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::Union &union_decl)
- {
-   auto decl
-     = CanonicalPath::new_seg (union_decl.get_node_id (),
- 			      union_decl.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (union_decl.get_node_id (), cpath);
- 
-   resolve_visibility (union_decl.get_visibility ());
- 
-   NodeId scope_node_id = union_decl.get_node_id ();
-   resolver->get_type_scope ().push (scope_node_id);
- 
-   if (union_decl.has_generics ())
-     ResolveGenericParams::go (union_decl.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (union_decl.has_where_clause ())
-     ResolveWhereClause::Resolve (union_decl.get_where_clause ());
- 
-   for (AST::StructField &field : union_decl.get_variants ())
-     {
-       if (field.get_field_type ().is_marked_for_strip ())
- 	continue;
- 
-       ResolveType::go (field.get_field_type ());
-     }
- 
-   resolver->get_type_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::StaticItem &var)
- {
-   auto decl = CanonicalPath::new_seg (var.get_node_id (),
- 				      var.get_identifier ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (var.get_node_id (), cpath);
- 
-   ResolveType::go (var.get_type ());
-   ResolveExpr::go (var.get_expr (), path, cpath);
- }
- 
- void
- ResolveItem::visit (AST::ConstantItem &constant)
- {
-   auto decl = CanonicalPath::new_seg (constant.get_node_id (),
- 				      constant.get_identifier ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (constant.get_node_id (), cpath);
- 
-   resolve_visibility (constant.get_visibility ());
- 
-   ResolveType::go (constant.get_type ());
-   if (constant.has_expr ())
-     ResolveExpr::go (constant.get_expr (), path, cpath);
- }
- 
- void
- ResolveItem::visit (AST::Function &function)
- {
-   auto decl
-     = CanonicalPath::new_seg (function.get_node_id (),
- 			      function.get_function_name ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
- 
-   mappings.insert_canonical_path (function.get_node_id (), cpath);
- 
-   resolve_visibility (function.get_visibility ());
- 
-   NodeId scope_node_id = function.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   if (function.has_generics ())
-     ResolveGenericParams::go (function.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   // resolve any where clause items
-   if (function.has_where_clause ())
-     ResolveWhereClause::Resolve (function.get_where_clause ());
- 
-   if (function.has_return_type ())
-     ResolveType::go (function.get_return_type ());
- 
-   if (function.has_self_param ())
-     {
-       // self turns into (self: Self) as a function param
-       AST::Param &s_param = function.get_self_param ();
-       auto &self_param = static_cast<AST::SelfParam &> (s_param);
- 
-       // FIXME: which location should be used for Rust::Identifier `self`?
-       AST::IdentifierPattern self_pattern (
- 	self_param.get_node_id (), {"self"}, self_param.get_locus (),
- 	self_param.get_has_ref (), self_param.get_is_mut (),
- 	std::unique_ptr<AST::Pattern> (nullptr));
-       PatternDeclaration::go (self_pattern, Rib::ItemType::Param);
- 
-       if (self_param.has_type ())
- 	{
- 	  // This shouldn't happen the parser should already error for this
- 	  rust_assert (!self_param.get_has_ref ());
- 	  ResolveType::go (self_param.get_type ());
- 	}
-       else
- 	{
- 	  // here we implicitly make self have a type path of Self
- 	  std::vector<std::unique_ptr<AST::TypePathSegment>> segments;
- 	  segments.push_back (std::unique_ptr<AST::TypePathSegment> (
- 	    new AST::TypePathSegment ("Self", false, self_param.get_locus ())));
- 
- 	  AST::TypePath self_type_path (std::move (segments),
- 					self_param.get_locus ());
- 	  ResolveType::go (self_type_path);
- 	}
-     }
- 
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-   // we make a new scope so the names of parameters are resolved and shadowed
-   // correctly
-   for (auto &p : function.get_function_params ())
-     {
-       if (p->is_variadic ())
- 	{
- 	  auto &param = static_cast<AST::VariadicParam &> (*p);
- 	  if (param.has_pattern ())
- 	    PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param,
- 				    bindings);
- 	}
-       else if (p->is_self ())
- 	{
- 	  auto &param = static_cast<AST::SelfParam &> (*p);
- 	  if (param.has_type ())
- 	    ResolveType::go (param.get_type ());
- 	}
-       else
- 	{
- 	  auto &param = static_cast<AST::FunctionParam &> (*p);
- 	  ResolveType::go (param.get_type ());
- 	  PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param,
- 				  bindings);
- 	}
-     }
- 
-   // resolve the function body
-   ResolveExpr::go (*function.get_definition ().value (), path, cpath);
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::InherentImpl &impl_block)
- {
-   NodeId scope_node_id = impl_block.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
- 
-   resolve_visibility (impl_block.get_visibility ());
- 
-   if (impl_block.has_generics ())
-     ResolveGenericParams::go (impl_block.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   // resolve any where clause items
-   if (impl_block.has_where_clause ())
-     ResolveWhereClause::Resolve (impl_block.get_where_clause ());
- 
-   // FIXME this needs to be protected behind nominal type-checks see:
-   // rustc --explain E0118
-   // issue #2634
-   ResolveType::go (impl_block.get_type ());
- 
-   // Setup paths
-   CanonicalPath self_cpath = CanonicalPath::create_empty ();
-   bool ok = ResolveTypeToCanonicalPath::go (impl_block.get_type (), self_cpath);
-   if (!ok)
-     {
-       resolver->get_name_scope ().pop ();
-       resolver->get_type_scope ().pop ();
-       resolver->get_label_scope ().pop ();
-       return;
-     }
- 
-   rust_debug ("AST::InherentImpl resolve Self: {%s}",
- 	      self_cpath.get ().c_str ());
- 
-   CanonicalPath impl_type = self_cpath;
-   CanonicalPath impl_type_seg
-     = CanonicalPath::inherent_impl_seg (impl_block.get_node_id (), impl_type);
-   CanonicalPath impl_prefix = prefix.append (impl_type_seg);
- 
-   // see https://godbolt.org/z/a3vMbsT6W
-   CanonicalPath cpath = CanonicalPath::create_empty ();
-   if (canonical_prefix.size () <= 1)
-     {
-       cpath = impl_prefix;
-     }
-   else
-     {
-       cpath = canonical_prefix.append (impl_type_seg);
-     }
- 
-   // done setup paths
- 
-   auto Self
-     = CanonicalPath::get_big_self (impl_block.get_type ().get_node_id ());
- 
-   resolver->get_type_scope ().insert (Self,
- 				      impl_block.get_type ().get_node_id (),
- 				      impl_block.get_type ().get_locus ());
- 
-   for (auto &impl_item : impl_block.get_impl_items ())
-     {
-       rust_debug (
- 	"AST::InherentImpl resolve_impl_item: impl_prefix={%s} cpath={%s}",
- 	impl_prefix.get ().c_str (), cpath.get ().c_str ());
-       resolve_impl_item (*impl_item, impl_prefix, cpath);
-     }
- 
-   resolver->get_type_scope ().peek ()->clear_name (
-     Self, impl_block.get_type ().get_node_id ());
- 
-   resolver->get_type_scope ().pop ();
-   resolver->get_name_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::TraitImpl &impl_block)
- {
-   NodeId scope_node_id = impl_block.get_node_id ();
- 
-   resolve_visibility (impl_block.get_visibility ());
- 
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   if (impl_block.has_generics ())
-     ResolveGenericParams::go (impl_block.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   // resolve any where clause items
-   if (impl_block.has_where_clause ())
-     ResolveWhereClause::Resolve (impl_block.get_where_clause ());
- 
-   // CanonicalPath canonical_trait_type = CanonicalPath::create_empty ();
-   NodeId trait_resolved_node = ResolveType::go (impl_block.get_trait_path ());
-   if (trait_resolved_node == UNKNOWN_NODEID)
-     {
-       resolver->get_name_scope ().pop ();
-       resolver->get_type_scope ().pop ();
-       resolver->get_label_scope ().pop ();
-       return;
-     }
- 
-   //   CanonicalPath canonical_impl_type = CanonicalPath::create_empty ();
-   NodeId type_resolved_node = ResolveType::go (impl_block.get_type ());
-   if (type_resolved_node == UNKNOWN_NODEID)
-     {
-       resolver->get_name_scope ().pop ();
-       resolver->get_type_scope ().pop ();
-       resolver->get_label_scope ().pop ();
-       return;
-     }
- 
-   bool ok = true;
- 
-   // setup paths
-   CanonicalPath canonical_trait_type = CanonicalPath::create_empty ();
- 
-   ok = ResolveTypeToCanonicalPath::go (impl_block.get_trait_path (),
- 				       canonical_trait_type);
-   if (!ok)
-     {
-       resolver->get_name_scope ().pop ();
-       resolver->get_type_scope ().pop ();
-       resolver->get_label_scope ().pop ();
-       return;
-     }
- 
-   rust_debug ("AST::TraitImpl resolve trait type: {%s}",
- 	      canonical_trait_type.get ().c_str ());
- 
-   CanonicalPath canonical_impl_type = CanonicalPath::create_empty ();
-   ok = ResolveTypeToCanonicalPath::go (impl_block.get_type (),
- 				       canonical_impl_type);
-   if (!ok)
-     {
-       resolver->get_name_scope ().pop ();
-       resolver->get_type_scope ().pop ();
-       resolver->get_label_scope ().pop ();
-       return;
-     }
- 
-   rust_debug ("AST::TraitImpl resolve self: {%s}",
- 	      canonical_impl_type.get ().c_str ());
- 
-   // raw paths
-   CanonicalPath impl_type_seg = canonical_impl_type;
-   CanonicalPath trait_type_seg = canonical_trait_type;
-   CanonicalPath projection
-     = CanonicalPath::trait_impl_projection_seg (impl_block.get_node_id (),
- 						trait_type_seg, impl_type_seg);
-   CanonicalPath impl_prefix = prefix.append (projection);
- 
-   // setup canonical-path
-   CanonicalPath canonical_projection
-     = CanonicalPath::trait_impl_projection_seg (impl_block.get_node_id (),
- 						canonical_trait_type,
- 						canonical_impl_type);
-   CanonicalPath cpath = CanonicalPath::create_empty ();
-   if (canonical_prefix.size () <= 1)
-     {
-       cpath = canonical_projection;
-     }
-   else
-     {
-       cpath = canonical_prefix.append (canonical_projection);
-     }
- 
-   // DONE setup canonical-path
- 
-   auto Self
-     = CanonicalPath::get_big_self (impl_block.get_type ().get_node_id ());
- 
-   resolver->get_type_scope ().insert (Self,
- 				      impl_block.get_type ().get_node_id (),
- 				      impl_block.get_type ().get_locus ());
- 
-   for (auto &impl_item : impl_block.get_impl_items ())
-     {
-       rust_debug (
- 	"AST::TraitImpl resolve_impl_item: impl_prefix={%s} cpath={%s}",
- 	impl_prefix.get ().c_str (), cpath.get ().c_str ());
-       resolve_impl_item (*impl_item, impl_prefix, cpath);
-     }
- 
-   Rib *r = resolver->get_type_scope ().peek ();
-   r->clear_name (Self, impl_block.get_type ().get_node_id ());
- 
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::Trait &trait)
- {
-   NodeId scope_node_id = trait.get_node_id ();
- 
-   resolve_visibility (trait.get_visibility ());
- 
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
- 
-   ResolveGenericParams::go_single (trait.get_implicit_self (), prefix,
- 				   canonical_prefix);
-   ResolveGenericParams::go (trait.get_generic_params (), prefix,
- 			    canonical_prefix);
- 
-   // Self is an implicit TypeParam so lets mark it as such
-   resolver->get_type_scope ().append_reference_for_def (
-     trait.get_node_id (), trait.get_implicit_self ().get_node_id ());
- 
-   if (trait.has_type_param_bounds ())
-     {
-       for (auto &bound : trait.get_type_param_bounds ())
- 	{
- 	  ResolveTypeBound::go (*bound);
- 	}
-     }
- 
-   // resolve any where clause items
-   if (trait.has_where_clause ())
-     ResolveWhereClause::Resolve (trait.get_where_clause ());
- 
-   // resolve the paths
-   CanonicalPath path = CanonicalPath::create_empty ();
-   CanonicalPath cpath = CanonicalPath::create_empty ();
-   //
- 
-   for (auto &item : trait.get_trait_items ())
-     {
-       ResolveTraitItems::go (item.get (), path, cpath);
-     }
- 
-   resolver->get_type_scope ().pop ();
-   resolver->get_name_scope ().pop ();
- }
- 
- void
- ResolveItem::visit (AST::ExternBlock &extern_block)
- {
-   resolve_visibility (extern_block.get_visibility ());
- 
-   for (auto &item : extern_block.get_extern_items ())
-     {
-       resolve_extern_item (*item);
-     }
- }
- 
- void
- ResolveItem::resolve_impl_item (AST::AssociatedItem &item,
- 				const CanonicalPath &prefix,
- 				const CanonicalPath &canonical_prefix)
- {
-   ResolveImplItems::go (item, prefix, canonical_prefix);
- }
- 
- void
- ResolveItem::resolve_extern_item (AST::ExternalItem &item)
- {
-   ResolveExternItem::go (item, prefix, canonical_prefix);
- }
- 
- static void flatten_glob (const AST::UseTreeGlob &glob,
- 			  std::vector<Import> &imports);
- static void flatten_rebind (const AST::UseTreeRebind &glob,
- 			    std::vector<Import> &imports);
- static void flatten_list (const AST::UseTreeList &glob,
- 			  std::vector<Import> &imports);
- 
- static void
- flatten (const AST::UseTree *tree, std::vector<Import> &imports)
- {
-   switch (tree->get_kind ())
-     {
-     case AST::UseTree::Glob:
-       {
- 	auto glob = static_cast<const AST::UseTreeGlob *> (tree);
- 	flatten_glob (*glob, imports);
- 	break;
-       }
-     case AST::UseTree::Rebind:
-       {
- 	auto rebind = static_cast<const AST::UseTreeRebind *> (tree);
- 	flatten_rebind (*rebind, imports);
- 	break;
-       }
-     case AST::UseTree::List:
-       {
- 	auto list = static_cast<const AST::UseTreeList *> (tree);
- 	flatten_list (*list, imports);
- 	break;
-       }
-       break;
-     }
- }
- 
- static void
- flatten_glob (const AST::UseTreeGlob &glob, std::vector<Import> &imports)
- {
-   if (glob.has_path ())
-     imports.emplace_back (glob.get_path (), true, std::string ());
- }
- 
- static void
- flatten_rebind (const AST::UseTreeRebind &rebind, std::vector<Import> &imports)
- {
-   auto path = rebind.get_path ();
- 
-   std::string label;
-   if (rebind.has_identifier ())
-     label = rebind.get_identifier ().as_string ();
-   else
-     label = path.get_final_segment ().as_string ();
- 
-   imports.emplace_back (path, false, label);
- }
- 
- static void
- flatten_list (const AST::UseTreeList &list, std::vector<Import> &imports)
- {
-   auto prefix = AST::SimplePath::create_empty ();
-   if (list.has_path ())
-     prefix = list.get_path ();
- 
-   for (const auto &tree : list.get_trees ())
-     {
-       // append imports to the main list, then modify them in-place
-       auto start_idx = imports.size ();
-       flatten (tree.get (), imports);
- 
-       for (auto import = imports.begin () + start_idx; import != imports.end ();
- 	   import++)
- 	{
- 	  // avoid duplicate node ids
- 	  auto prefix_copy
- 	    = AST::SimplePath ({}, prefix.has_opening_scope_resolution (),
- 			       prefix.get_locus ());
- 	  for (auto &seg : prefix.get_segments ())
- 	    prefix_copy.get_segments ().push_back (
- 	      AST::SimplePathSegment (seg.get_segment_name (),
- 				      seg.get_locus ()));
- 
- 	  import->add_prefix (std::move (prefix_copy));
- 	}
-     }
- }
- 
- void
- Import::add_prefix (AST::SimplePath prefix)
- {
-   AST::SimplePath old_path (std::move (path));
-   path = std::move (prefix);
-   std::move (old_path.get_segments ().begin (), old_path.get_segments ().end (),
- 	     std::back_inserter (path.get_segments ()));
- }
- 
- /**
-  * Flatten a UseDeclaration's UseTree into multiple simple paths to resolve.
-  *
-  * Given the following use declarations:
-  * ```
-  * use some::path::to_resolve; #1
-  * use some::path::to_glob::*; #2
-  * use some::path::{one, two}; #2
-  * ```
-  *
-  * In the first case, we simply want to return a vector with a single
-  * SimplePath:
-  * [some::path::to_resolve]
-  *
-  * In the second case, we want to resolve the glob's "origin path":
-  * [some::path::to_glob]
-  *
-  * Finally in the third case, we want to create two SimplePaths to resolve:
-  * [some::path::one, some::path::two]
-  */
- static std::vector<Import>
- flatten_use_dec_to_imports (const AST::UseDeclaration &use_item)
- {
-   auto imports = std::vector<Import> ();
- 
-   const auto &tree = use_item.get_tree ();
-   flatten (tree.get (), imports);
- 
-   return imports;
- }
- 
- void
- ResolveItem::visit (AST::UseDeclaration &use_item)
- {
-   std::vector<Import> to_resolve = flatten_use_dec_to_imports (use_item);
- 
-   // FIXME: I think this does not actually resolve glob use-decls and is going
-   // the wrong way about it. RFC #1560 specifies the following:
-   //
-   // > When we find a glob import, we have to record a 'back link', so that when
-   // a public name is added for the supplying module, we can add it for the
-   // importing module.
-   //
-   // Which is the opposite of what we're doing if I understand correctly?
- 
-   NodeId current_module = resolver->peek_current_module_scope ();
-   for (auto &import : to_resolve)
-     {
-       auto &path = import.get_path ();
- 
-       rust_debug ("resolving use-decl path: [%s]", path.as_string ().c_str ());
-       NodeId resolved_node_id = ResolvePath::go (path);
-       bool ok = resolved_node_id != UNKNOWN_NODEID;
-       if (!ok)
- 	continue;
- 
-       if (import.is_glob ())
- 	continue;
- 
-       auto decl = CanonicalPath::new_seg (resolved_node_id, import.get_name ());
-       mappings.insert_module_child_item (current_module, decl);
- 
-       resolver->get_type_scope ().insert (decl, resolved_node_id,
- 					  path.get_locus (),
- 					  Rib::ItemType::Type);
-       rust_debug ("use-decl rexporting: [%s]", decl.get ().c_str ());
-     }
- }
- 
- ResolveImplItems::ResolveImplItems (const CanonicalPath &prefix,
- 				    const CanonicalPath &canonical_prefix)
-   : ResolveItem (prefix, canonical_prefix)
- {}
- 
- void
- ResolveImplItems::go (AST::AssociatedItem &item, const CanonicalPath &prefix,
- 		      const CanonicalPath &canonical_prefix)
- {
-   if (item.is_marked_for_strip ())
-     return;
- 
-   ResolveImplItems resolver (prefix, canonical_prefix);
-   item.accept_vis (resolver);
- }
- 
- void
- ResolveImplItems::visit (AST::TypeAlias &alias)
- {
-   ResolveItem::visit (alias);
- 
-   resolve_visibility (alias.get_visibility ());
- 
-   // FIXME this stops the erronious unused decls which will be fixed later on
-   resolver->get_type_scope ().append_reference_for_def (alias.get_node_id (),
- 							alias.get_node_id ());
- }
- 
- void
- ResolveExternItem::go (AST::ExternalItem &item, const CanonicalPath &prefix,
- 		       const CanonicalPath &canonical_prefix)
- {
-   ResolveExternItem resolver (prefix, canonical_prefix);
-   item.accept_vis (resolver);
- }
- 
- void
- ResolveExternItem::visit (AST::Function &function)
- {
-   NodeId scope_node_id = function.get_node_id ();
-   auto decl
-     = CanonicalPath::new_seg (function.get_node_id (),
- 			      function.get_function_name ().as_string ());
-   auto path = prefix.append (decl);
-   auto cpath = canonical_prefix.append (decl);
- 
-   mappings.insert_canonical_path (function.get_node_id (), cpath);
- 
-   resolve_visibility (function.get_visibility ());
- 
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   // resolve the generics
-   if (function.has_generics ())
-     ResolveGenericParams::go (function.get_generic_params (), prefix,
- 			      canonical_prefix);
- 
-   if (function.has_return_type ())
-     ResolveType::go (function.get_return_type ());
- 
-   // we make a new scope so the names of parameters are resolved and shadowed
-   // correctly
-   for (auto &param : function.get_function_params ())
-     if (!param->is_variadic ())
-       {
- 	auto &p = static_cast<AST::FunctionParam &> (*param);
- 	ResolveType::go (p.get_type ());
-       }
- 
-   // done
-   resolver->get_name_scope ().pop ();
-   resolver->get_type_scope ().pop ();
-   resolver->get_label_scope ().pop ();
- }
- 
- void
- ResolveExternItem::visit (AST::ExternalStaticItem &item)
- {
-   resolve_visibility (item.get_visibility ());
- 
-   ResolveType::go (item.get_type ());
- }
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #if CHECKING_P
- 
- namespace selftest {
- 
- static void
- rust_flatten_nested_glob (void)
- {
-   auto foo = Rust::AST::SimplePathSegment ("foo", UNDEF_LOCATION);
-   auto bar = Rust::AST::SimplePathSegment ("bar", UNDEF_LOCATION);
-   auto foobar = Rust::AST::SimplePath ({foo, bar});
- 
-   auto glob
-     = Rust::AST::UseTreeGlob (Rust::AST::UseTreeGlob::PathType::PATH_PREFIXED,
- 			      foobar, UNDEF_LOCATION);
- 
-   auto imports = std::vector<Rust::Resolver::Import> ();
-   Rust::Resolver::flatten_glob (glob, imports);
- 
-   ASSERT_TRUE (!imports.empty ());
-   ASSERT_EQ (imports.size (), 1);
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[0].as_string (), "foo");
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[1].as_string (), "bar");
- }
- 
- static void
- rust_flatten_glob (void)
- {
-   auto frob = Rust::AST::SimplePath::from_str ("frobulator", UNDEF_LOCATION);
- 
-   auto glob
-     = Rust::AST::UseTreeGlob (Rust::AST::UseTreeGlob::PathType::PATH_PREFIXED,
- 			      frob, UNDEF_LOCATION);
- 
-   auto imports = std::vector<Rust::Resolver::Import> ();
-   Rust::Resolver::flatten_glob (glob, imports);
- 
-   ASSERT_TRUE (!imports.empty ());
-   ASSERT_EQ (imports.size (), 1);
-   ASSERT_EQ (imports[0].get_path (), "frobulator");
- }
- 
- static void
- rust_flatten_rebind_none (void)
- {
-   auto foo = Rust::AST::SimplePathSegment ("foo", UNDEF_LOCATION);
-   auto bar = Rust::AST::SimplePathSegment ("bar", UNDEF_LOCATION);
-   auto foobar = Rust::AST::SimplePath ({foo, bar});
- 
-   auto rebind = Rust::AST::UseTreeRebind (Rust::AST::UseTreeRebind::NONE,
- 					  foobar, UNDEF_LOCATION);
- 
-   auto imports = std::vector<Rust::Resolver::Import> ();
-   Rust::Resolver::flatten_rebind (rebind, imports);
- 
-   ASSERT_TRUE (!imports.empty ());
-   ASSERT_EQ (imports.size (), 1);
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[0].as_string (), "foo");
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[1].as_string (), "bar");
- }
- 
- static void
- rust_flatten_rebind (void)
- {
-   auto frob = Rust::AST::SimplePath::from_str ("frobulator", UNDEF_LOCATION);
- 
-   auto rebind = Rust::AST::UseTreeRebind (Rust::AST::UseTreeRebind::IDENTIFIER,
- 					  frob, UNDEF_LOCATION, {"saindoux"});
- 
-   auto imports = std::vector<Rust::Resolver::Import> ();
-   Rust::Resolver::flatten_rebind (rebind, imports);
- 
-   ASSERT_TRUE (!imports.empty ());
-   ASSERT_EQ (imports.size (), 1);
-   ASSERT_EQ (imports[0].get_path (), "frobulator");
-   ASSERT_EQ (imports[0].get_name (), "saindoux");
- }
- 
- static void
- rust_flatten_rebind_nested (void)
- {
-   auto foo = Rust::AST::SimplePathSegment ("foo", UNDEF_LOCATION);
-   auto bar = Rust::AST::SimplePathSegment ("bar", UNDEF_LOCATION);
-   auto baz = Rust::AST::SimplePathSegment ("baz", UNDEF_LOCATION);
- 
-   auto foo_bar_baz = Rust::AST::SimplePath ({foo, bar, baz});
- 
-   auto rebind
-     = Rust::AST::UseTreeRebind (Rust::AST::UseTreeRebind::IDENTIFIER,
- 				foo_bar_baz, UNDEF_LOCATION, {"saindoux"});
- 
-   auto imports = std::vector<Rust::Resolver::Import> ();
-   Rust::Resolver::flatten_rebind (rebind, imports);
- 
-   ASSERT_TRUE (!imports.empty ());
-   ASSERT_EQ (imports.size (), 1);
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[0].as_string (), "foo");
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[1].as_string (), "bar");
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[2].as_string (), "baz");
-   ASSERT_EQ (imports[0].get_name (), "saindoux");
- }
- 
- static void
- rust_flatten_list (void)
- {
-   auto foo = Rust::AST::SimplePathSegment ("foo", UNDEF_LOCATION);
-   auto bar = Rust::AST::SimplePathSegment ("bar", UNDEF_LOCATION);
-   auto foo_bar = Rust::AST::SimplePath ({foo, bar});
- 
-   auto baz = Rust::AST::SimplePath::from_str ("baz", UNDEF_LOCATION);
-   auto bul = Rust::AST::SimplePath::from_str ("bul", UNDEF_LOCATION);
- 
-   // use foo::bar::{baz, bul};
- 
-   auto use0 = std::unique_ptr<Rust::AST::UseTree> (
-     new Rust::AST::UseTreeRebind (Rust::AST::UseTreeRebind::NONE, baz,
- 				  UNDEF_LOCATION));
-   auto use1 = std::unique_ptr<Rust::AST::UseTree> (
-     new Rust::AST::UseTreeRebind (Rust::AST::UseTreeRebind::NONE, bul,
- 				  UNDEF_LOCATION));
- 
-   auto uses = std::vector<std::unique_ptr<Rust::AST::UseTree>> ();
-   uses.emplace_back (std::move (use0));
-   uses.emplace_back (std::move (use1));
- 
-   auto list
-     = Rust::AST::UseTreeList (Rust::AST::UseTreeList::PATH_PREFIXED, foo_bar,
- 			      std::move (uses), UNDEF_LOCATION);
- 
-   auto imports = std::vector<Rust::Resolver::Import> ();
-   Rust::Resolver::flatten_list (list, imports);
- 
-   ASSERT_TRUE (!imports.empty ());
-   ASSERT_EQ (imports.size (), 2);
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[0].as_string (), "foo");
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[1].as_string (), "bar");
-   ASSERT_EQ (imports[0].get_path ().get_segments ()[2].as_string (), "baz");
-   ASSERT_EQ (imports[1].get_path ().get_segments ()[0].as_string (), "foo");
-   ASSERT_EQ (imports[1].get_path ().get_segments ()[1].as_string (), "bar");
-   ASSERT_EQ (imports[1].get_path ().get_segments ()[2].as_string (), "bul");
- }
- 
- static void
- rust_use_dec_flattening (void)
- {
-   rust_flatten_glob ();
-   rust_flatten_nested_glob ();
-   rust_flatten_rebind_none ();
-   rust_flatten_rebind ();
-   rust_flatten_rebind_nested ();
-   rust_flatten_list ();
- }
- 
- void
- rust_simple_path_resolve_test (void)
- {
-   rust_use_dec_flattening ();
- }
- 
- } // namespace selftest
- 
- #endif // CHECKING_P
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-item.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-item.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-item.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-item.h	Thu Jan  1 00:00:00 1970
***************
*** 1,161 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_ITEM_H
- #define RUST_AST_RESOLVE_ITEM_H
- 
- #include "rust-ast-full-decls.h"
- #include "rust-ast-resolve-base.h"
- 
- #include "config.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolveTraitItems : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::AssociatedItem *item, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix);
- 
-   void visit (AST::Function &type) override;
-   void visit (AST::TraitItemType &type) override;
-   void visit (AST::TraitItemConst &constant) override;
- 
- private:
-   ResolveTraitItems (const CanonicalPath &prefix,
- 		     const CanonicalPath &canonical_prefix);
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- class ResolveItem : public ResolverBase
- {
- public:
-   using Rust::Resolver::ResolverBase::visit;
- 
-   static void go (AST::Item &item, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix);
- 
-   void visit (AST::TypeAlias &alias) override;
-   void visit (AST::Module &module) override;
-   void visit (AST::TupleStruct &struct_decl) override;
-   void visit (AST::Enum &enum_decl) override;
-   /* EnumItem doesn't need to be handled, no fields.  */
-   void visit (AST::EnumItem &item) override;
-   void visit (AST::EnumItemTuple &item) override;
-   void visit (AST::EnumItemStruct &item) override;
-   void visit (AST::EnumItemDiscriminant &item) override;
-   void visit (AST::StructStruct &struct_decl) override;
-   void visit (AST::Union &union_decl) override;
-   void visit (AST::StaticItem &var) override;
-   void visit (AST::ConstantItem &constant) override;
-   void visit (AST::Function &function) override;
-   void visit (AST::InherentImpl &impl_block) override;
-   void visit (AST::TraitImpl &impl_block) override;
-   void visit (AST::Trait &trait) override;
-   void visit (AST::ExternBlock &extern_block) override;
-   void visit (AST::UseDeclaration &) override;
- 
- protected:
-   void resolve_impl_item (AST::AssociatedItem &item,
- 			  const CanonicalPath &prefix,
- 			  const CanonicalPath &canonical_prefix);
-   void resolve_extern_item (AST::ExternalItem &item);
- 
-   ResolveItem (const CanonicalPath &prefix,
- 	       const CanonicalPath &canonical_prefix);
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- class ResolveImplItems : public ResolveItem
- {
-   using Rust::Resolver::ResolveItem::visit;
- 
- public:
-   static void go (AST::AssociatedItem &item, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix);
- 
-   void visit (AST::TypeAlias &alias) override;
- 
- private:
-   ResolveImplItems (const CanonicalPath &prefix,
- 		    const CanonicalPath &canonical_prefix);
- };
- 
- class ResolveExternItem : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::ExternalItem &item, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix);
- 
-   void visit (AST::Function &function) override;
-   void visit (AST::ExternalStaticItem &item) override;
- 
- private:
-   ResolveExternItem (const CanonicalPath &prefix,
- 		     const CanonicalPath &canonical_prefix)
-     : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
-   {}
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- class Import
- {
- public:
-   Import (AST::SimplePath path, bool is_glob, std::string name)
-     : path (path), is_glob_f (is_glob), name (name)
-   {}
- 
-   AST::SimplePath &get_path () { return path; }
- 
-   const AST::SimplePath &get_path () const { return path; }
- 
-   bool is_glob () const { return is_glob_f; }
- 
-   const std::string &get_name () const { return name; }
- 
-   void add_prefix (AST::SimplePath prefix);
- 
- private:
-   AST::SimplePath path;
-   bool is_glob_f;
-   std::string name;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #if CHECKING_P
- 
- namespace selftest {
- extern void rust_simple_path_resolve_test (void);
- } // namespace selftest
- 
- #endif // CHECKING_P
- 
- #endif // RUST_AST_RESOLVE_ITEM_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-path.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-path.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-path.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-path.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,558 ****
- // Copyright (C) 2020-2024 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-path.h"
- #include "rust-ast-resolve-type.h"
- #include "rust-hir-map.h"
- #include "rust-path.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- ResolvePath::ResolvePath () : ResolverBase () {}
- 
- NodeId
- ResolvePath::go (AST::PathInExpression &expr)
- {
-   ResolvePath resolver;
-   return resolver.resolve_path (expr);
- }
- 
- NodeId
- ResolvePath::go (AST::QualifiedPathInExpression &expr)
- {
-   ResolvePath resolver;
-   return resolver.resolve_path (expr);
- }
- 
- NodeId
- ResolvePath::go (AST::SimplePath &expr)
- {
-   ResolvePath resolver;
-   return resolver.resolve_path (expr);
- }
- 
- NodeId
- ResolvePath::resolve_path (AST::PathInExpression &expr)
- {
-   if (expr.is_lang_item ())
-     return Analysis::Mappings::get ().get_lang_item_node (
-       expr.get_lang_item ());
- 
-   NodeId resolved_node_id = UNKNOWN_NODEID;
-   NodeId module_scope_id = resolver->peek_current_module_scope ();
-   NodeId previous_resolved_node_id = module_scope_id;
-   for (size_t i = 0; i < expr.get_segments ().size (); i++)
-     {
-       auto &segment = expr.get_segments ().at (i);
-       const AST::PathIdentSegment &ident_seg = segment.get_ident_segment ();
-       bool is_first_segment = i == 0;
-       resolved_node_id = UNKNOWN_NODEID;
- 
-       bool in_middle_of_path = i > 0;
-       if (in_middle_of_path && segment.is_lower_self_seg ())
- 	{
- 	  rust_error_at (segment.get_locus (), ErrorCode::E0433,
- 			 "%qs in paths can only be used in start position",
- 			 segment.as_string ().c_str ());
- 	  return UNKNOWN_NODEID;
- 	}
- 
-       NodeId crate_scope_id = resolver->peek_crate_module_scope ();
-       if (segment.is_crate_path_seg ())
- 	{
- 	  // what is the current crate scope node id?
- 	  module_scope_id = crate_scope_id;
- 	  previous_resolved_node_id = module_scope_id;
- 
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 						    &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == module_scope_id);
- 	  else
- 	    resolver->insert_resolved_name (segment.get_node_id (),
- 					    module_scope_id);
- 	  continue;
- 	}
-       else if (segment.is_super_path_seg ())
- 	{
- 	  if (module_scope_id == crate_scope_id)
- 	    {
- 	      rust_error_at (segment.get_locus (),
- 			     "cannot use %<super%> at the crate scope");
- 	      return UNKNOWN_NODEID;
- 	    }
- 
- 	  module_scope_id = resolver->peek_parent_module_scope ();
- 	  previous_resolved_node_id = module_scope_id;
- 
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 						    &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == module_scope_id);
- 	  else
- 	    resolver->insert_resolved_name (segment.get_node_id (),
- 					    module_scope_id);
- 	  continue;
- 	}
- 
-       // resolve any generic args
-       if (segment.has_generic_args ())
- 	ResolveGenericArgs::go (segment.get_generic_args ());
- 
-       // logic is awkward here there are a few cases
-       //
-       // T::Default
-       // mod::foo::impl_item
-       // super::super::module::item
-       // self
-       // self::foo
-       // self::foo::baz
-       //
-       // T::Default we can only resolve the T and cant do anything about Default
-       // its dependant on associated types
-       //
-       // mod::foo::impl_item
-       // we can resolve mod::foo but nothing about impl_item but we need to
-       // _always resolve generic arguments
-       //
-       // self is a simple single lookup
-       //
-       // we have module_scope_id for the next module_scope to lookup
-       // resolved_node_id is the thing we have resolve this segment to
-       //
-       // new algo?
-       // we can only use module resolution when the previous segment is either
-       // unknown or equal to this module_scope_id
-       //
-       // can only use old resolution when previous segment is unkown
- 
-       if (is_first_segment)
- 	{
- 	  // name scope first
- 	  NodeId resolved_node = UNKNOWN_NODEID;
- 	  const CanonicalPath path
- 	    = CanonicalPath::new_seg (segment.get_node_id (),
- 				      ident_seg.as_string ());
- 	  if (resolver->get_name_scope ().lookup (path, &resolved_node))
- 	    {
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_name (segment.get_node_id (),
- 						resolved_node);
- 	      resolved_node_id = resolved_node;
- 	    }
- 	  // check the type scope
- 	  else if (resolver->get_type_scope ().lookup (path, &resolved_node))
- 	    {
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_type (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_type (segment.get_node_id (),
- 						resolved_node);
- 	      resolved_node_id = resolved_node;
- 	    }
- 	  else if (segment.is_lower_self_seg ())
- 	    {
- 	      module_scope_id = crate_scope_id;
- 	      previous_resolved_node_id = module_scope_id;
- 
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == module_scope_id);
- 	      else
- 		resolver->insert_resolved_name (segment.get_node_id (),
- 						module_scope_id);
- 	      continue;
- 	    }
- 	  else
- 	    {
- 	      // no error handling here since we might be able to resolve via
- 	      // the module hierarchy and handle errors at the end
- 	    }
- 	}
- 
-       if (resolved_node_id == UNKNOWN_NODEID
- 	  && previous_resolved_node_id == module_scope_id)
- 	{
- 	  tl::optional<CanonicalPath &> resolved_child
- 	    = mappings.lookup_module_child (module_scope_id,
- 					    ident_seg.as_string ());
- 	  if (resolved_child.has_value ())
- 	    {
- 	      NodeId resolved_node = resolved_child->get_node_id ();
- 	      if (resolver->get_name_scope ().decl_was_declared_here (
- 		    resolved_node))
- 		{
- 		  resolved_node_id = resolved_node;
- 
- 		  NodeId existing = UNKNOWN_NODEID;
- 		  bool ok
- 		    = resolver->lookup_resolved_name (segment.get_node_id (),
- 						      &existing);
- 
- 		  if (ok)
- 		    rust_assert (existing == resolved_node);
- 		  else
- 		    resolver->insert_resolved_name (segment.get_node_id (),
- 						    resolved_node);
- 		}
- 	      else if (resolver->get_type_scope ().decl_was_declared_here (
- 			 resolved_node))
- 		{
- 		  resolved_node_id = resolved_node;
- 
- 		  NodeId existing = UNKNOWN_NODEID;
- 		  bool ok
- 		    = resolver->lookup_resolved_type (segment.get_node_id (),
- 						      &existing);
- 
- 		  if (ok)
- 		    rust_assert (existing == resolved_node);
- 		  else
- 		    resolver->insert_resolved_type (segment.get_node_id (),
- 						    resolved_node);
- 		}
- 	      else
- 		{
- 		  rust_error_at (segment.get_locus (),
- 				 "Cannot find path %<%s%> in this scope",
- 				 segment.as_string ().c_str ());
- 		  return UNKNOWN_NODEID;
- 		}
- 	    }
- 	}
- 
-       bool did_resolve_segment = resolved_node_id != UNKNOWN_NODEID;
-       if (did_resolve_segment)
- 	{
- 	  if (mappings.node_is_module (resolved_node_id)
- 	      || mappings.node_is_crate (resolved_node_id))
- 	    {
- 	      module_scope_id = resolved_node_id;
- 	    }
- 	  previous_resolved_node_id = resolved_node_id;
- 	}
-       else if (is_first_segment)
- 	{
- 	  rust_error_at (segment.get_locus (), ErrorCode::E0433,
- 			 "Cannot find path %<%s%> in this scope",
- 			 segment.as_string ().c_str ());
- 	  return UNKNOWN_NODEID;
- 	}
-     }
- 
-   resolved_node = resolved_node_id;
-   if (resolved_node_id != UNKNOWN_NODEID)
-     {
-       // name scope first
-       if (resolver->get_name_scope ().decl_was_declared_here (resolved_node_id))
- 	{
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok
- 	    = resolver->lookup_resolved_name (expr.get_node_id (), &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == resolved_node_id);
- 	  else
- 	    resolver->insert_resolved_name (expr.get_node_id (),
- 					    resolved_node_id);
- 	}
-       // check the type scope
-       else if (resolver->get_type_scope ().decl_was_declared_here (
- 		 resolved_node_id))
- 	{
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok
- 	    = resolver->lookup_resolved_type (expr.get_node_id (), &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == resolved_node_id);
- 	  else
- 	    resolver->insert_resolved_type (expr.get_node_id (),
- 					    resolved_node_id);
- 	}
-       else
- 	{
- 	  rust_unreachable ();
- 	}
-     }
-   return resolved_node_id;
- }
- 
- NodeId
- ResolvePath::resolve_path (AST::QualifiedPathInExpression &expr)
- {
-   auto &root_segment = expr.get_qualified_path_type ();
-   ResolveType::go (root_segment.get_type ());
-   if (root_segment.has_as_clause ())
-     ResolveType::go (root_segment.get_as_type_path ());
- 
-   for (auto &segment : expr.get_segments ())
-     {
-       // we cant actually do anything with the segment itself since this is all
-       // the job of the type system to figure it out but we can resolve any
-       // generic arguments used
-       if (segment.has_generic_args ())
- 	ResolveGenericArgs::go (segment.get_generic_args ());
-     }
- 
-   // cannot fully resolve a qualified path as it is dependant on associated
-   // items
-   return UNKNOWN_NODEID;
- }
- 
- NodeId
- ResolvePath::resolve_path (AST::SimplePath &expr)
- {
-   NodeId crate_scope_id = resolver->peek_crate_module_scope ();
-   NodeId module_scope_id = resolver->peek_current_module_scope ();
- 
-   NodeId previous_resolved_node_id = UNKNOWN_NODEID;
-   NodeId resolved_node_id = UNKNOWN_NODEID;
-   for (size_t i = 0; i < expr.get_segments ().size (); i++)
-     {
-       AST::SimplePathSegment &segment = expr.get_segments ().at (i);
-       bool is_first_segment = i == 0;
-       bool is_final_segment = i >= (expr.get_segments ().size () - 1);
-       resolved_node_id = UNKNOWN_NODEID;
- 
-       if (segment.is_crate_path_seg ())
- 	{
- 	  // what is the current crate scope node id?
- 	  module_scope_id = crate_scope_id;
- 	  previous_resolved_node_id = module_scope_id;
- 
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 						    &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == module_scope_id);
- 	  else
- 	    resolver->insert_resolved_name (segment.get_node_id (),
- 					    module_scope_id);
- 	  resolved_node_id = module_scope_id;
- 
- 	  continue;
- 	}
-       else if (segment.is_super_path_seg ())
- 	{
- 	  if (!is_first_segment)
- 	    {
- 	      rust_error_at (
- 		segment.get_locus (), ErrorCode::E0433,
- 		"%<super%> in paths can only be used in start position");
- 	      return UNKNOWN_NODEID;
- 	    }
- 	  if (module_scope_id == crate_scope_id)
- 	    {
- 	      rust_error_at (segment.get_locus (),
- 			     "cannot use %<super%> at the crate scope");
- 	      return UNKNOWN_NODEID;
- 	    }
- 
- 	  module_scope_id = resolver->peek_parent_module_scope ();
- 	  previous_resolved_node_id = module_scope_id;
- 
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 						    &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == module_scope_id);
- 	  else
- 	    resolver->insert_resolved_name (segment.get_node_id (),
- 					    module_scope_id);
- 	  resolved_node_id = module_scope_id;
- 
- 	  continue;
- 	}
- 
-       tl::optional<CanonicalPath &> resolved_child
- 	= mappings.lookup_module_child (module_scope_id,
- 					segment.get_segment_name ());
-       if (resolved_child.has_value ())
- 	{
- 	  NodeId resolved_node = resolved_child->get_node_id ();
- 	  if (resolver->get_name_scope ().decl_was_declared_here (
- 		resolved_node))
- 	    {
- 	      resolved_node_id = resolved_node;
- 
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_name (segment.get_node_id (),
- 						resolved_node);
- 	    }
- 	  else if (resolver->get_type_scope ().decl_was_declared_here (
- 		     resolved_node))
- 	    {
- 	      resolved_node_id = resolved_node;
- 
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_type (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_type (segment.get_node_id (),
- 						resolved_node);
- 	    }
- 	  else
- 	    {
- 	      rust_error_at (segment.get_locus (),
- 			     "Cannot find path %<%s%> in this scope",
- 			     segment.as_string ().c_str ());
- 	      return UNKNOWN_NODEID;
- 	    }
- 	}
- 
-       if (resolved_node_id == UNKNOWN_NODEID && is_first_segment)
- 	{
- 	  // name scope first
- 	  NodeId resolved_node = UNKNOWN_NODEID;
- 	  const CanonicalPath path
- 	    = CanonicalPath::new_seg (segment.get_node_id (),
- 				      segment.get_segment_name ());
- 	  if (resolver->get_name_scope ().lookup (path, &resolved_node))
- 	    {
- 	      resolved_node_id = resolved_node;
- 
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_name (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_name (segment.get_node_id (),
- 						resolved_node);
- 	    }
- 	  // check the type scope
- 	  else if (resolver->get_type_scope ().lookup (path, &resolved_node))
- 	    {
- 	      resolved_node_id = resolved_node;
- 
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_type (segment.get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_type (segment.get_node_id (),
- 						resolved_node);
- 	    }
- 	}
- 
-       // if we still have not resolved and this is the final segment and the
-       // final segment is self its likely the case: pub use
-       //
-       // result::Result::{self, Err, Ok};
-       //
-       // Then the resolved_node_id is just the previous one so long as it is a
-       // resolved node id
-       // rust_debug_loc (segment.get_locus (),
-       //   	      "trying to resolve seg: [%s] first [%s] last [%s]",
-       //   	      segment.get_segment_name ().c_str (),
-       //   	      is_first_segment ? "true" : "false",
-       //   	      is_final_segment ? "true" : "false");
-       if (resolved_node_id == UNKNOWN_NODEID && !is_first_segment
- 	  && is_final_segment && segment.is_lower_self_seg ())
- 	resolved_node_id = previous_resolved_node_id;
- 
-       // final check
-       if (resolved_node_id == UNKNOWN_NODEID)
- 	{
- 	  rust_error_at (segment.get_locus (),
- 			 "cannot find simple path segment %<%s%> in this scope",
- 			 segment.as_string ().c_str ());
- 	  return UNKNOWN_NODEID;
- 	}
- 
-       if (mappings.node_is_module (resolved_node_id))
- 	{
- 	  module_scope_id = resolved_node_id;
- 	}
- 
-       previous_resolved_node_id = resolved_node_id;
-     }
- 
-   resolved_node = resolved_node_id;
-   if (resolved_node_id != UNKNOWN_NODEID)
-     {
-       // name scope first
-       if (resolver->get_name_scope ().decl_was_declared_here (resolved_node_id))
- 	{
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok
- 	    = resolver->lookup_resolved_name (expr.get_node_id (), &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == resolved_node_id);
- 	  else
- 	    resolver->insert_resolved_name (expr.get_node_id (),
- 					    resolved_node_id);
- 	}
-       // check the type scope
-       else if (resolver->get_type_scope ().decl_was_declared_here (
- 		 resolved_node_id))
- 	{
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok
- 	    = resolver->lookup_resolved_type (expr.get_node_id (), &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == resolved_node_id);
- 	  else
- 	    resolver->insert_resolved_type (expr.get_node_id (),
- 					    resolved_node_id);
- 	}
-       else
- 	{
- 	  rust_unreachable ();
- 	}
-     }
-   return resolved_node_id;
- }
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-path.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-path.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-path.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-path.h	Thu Jan  1 00:00:00 1970
***************
*** 1,52 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_PATH_H
- #define RUST_AST_RESOLVE_PATH_H
- 
- #include "rust-ast-resolve-base.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolvePath : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static NodeId go (AST::PathInExpression &expr);
-   static NodeId go (AST::QualifiedPathInExpression &expr);
-   static NodeId go (AST::SimplePath &expr);
- 
- private:
-   ResolvePath ();
- 
-   NodeId resolve_path (AST::PathInExpression &expr);
-   NodeId resolve_path (AST::QualifiedPathInExpression &expr);
-   NodeId resolve_path (AST::SimplePath &expr);
- 
-   void
-   resolve_simple_path_segments (CanonicalPath prefix, size_t offs,
- 				const std::vector<AST::SimplePathSegment> &segs,
- 				NodeId expr_node_id, location_t expr_locus);
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // !RUST_AST_RESOLVE_PATH_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-pattern.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-pattern.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-pattern.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-pattern.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,419 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-pattern.h"
- #include "rust-ast-resolve-path.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- void
- PatternDeclaration::go (AST::Pattern &pattern, Rib::ItemType type)
- {
-   std::vector<PatternBinding> bindings
-     = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
-   PatternDeclaration::go (pattern, type, bindings);
- }
- 
- void
- PatternDeclaration::go (AST::Pattern &pattern, Rib::ItemType type,
- 			std::vector<PatternBinding> &bindings)
- {
-   PatternDeclaration resolver (bindings, type);
-   pattern.accept_vis (resolver);
- 
-   for (auto &map_entry : resolver.missing_bindings)
-     {
-       auto ident = map_entry.first; // key
-       auto info = map_entry.second; // value
- 
-       rust_error_at (info.get_locus (), ErrorCode::E0408,
- 		     "variable '%s' is not bound in all patterns",
- 		     ident.as_string ().c_str ());
-     }
- 
-   for (auto &map_entry : resolver.inconsistent_bindings)
-     {
-       auto ident = map_entry.first; // key
-       auto info = map_entry.second; // value
- 
-       rust_error_at (
- 	info.get_locus (), ErrorCode::E0409,
- 	"variable '%s' is bound inconsistently across pattern alternatives",
- 	ident.as_string ().c_str ());
-     }
- }
- 
- void
- PatternDeclaration::visit (AST::IdentifierPattern &pattern)
- {
-   if (pattern.has_subpattern ())
-     {
-       pattern.get_subpattern ().accept_vis (*this);
-     }
- 
-   Mutability mut = pattern.get_is_mut () ? Mutability::Mut : Mutability::Imm;
-   add_new_binding (pattern.get_ident (), pattern.get_node_id (),
- 		   BindingTypeInfo (mut, pattern.get_is_ref (),
- 				    pattern.get_locus ()));
- }
- 
- void
- PatternDeclaration::visit (AST::GroupedPattern &pattern)
- {
-   pattern.get_pattern_in_parens ().accept_vis (*this);
- }
- 
- void
- PatternDeclaration::visit (AST::ReferencePattern &pattern)
- {
-   pattern.get_referenced_pattern ().accept_vis (*this);
- }
- 
- void
- PatternDeclaration::visit (AST::PathInExpression &pattern)
- {
-   ResolvePath::go (pattern);
- }
- 
- void
- PatternDeclaration::visit (AST::TupleStructPattern &pattern)
- {
-   ResolvePath::go (pattern.get_path ());
- 
-   AST::TupleStructItems &items = pattern.get_items ();
-   switch (items.get_item_type ())
-     {
-     case AST::TupleStructItems::RANGE:
-       {
- 	// TODO
- 	rust_unreachable ();
-       }
-       break;
- 
-     case AST::TupleStructItems::NO_RANGE:
-       {
- 	auto &items_no_range
- 	  = static_cast<AST::TupleStructItemsNoRange &> (items);
- 
- 	for (auto &inner_pattern : items_no_range.get_patterns ())
- 	  {
- 	    inner_pattern->accept_vis (*this);
- 	  }
-       }
-       break;
-     }
- }
- 
- void
- PatternDeclaration::visit (AST::StructPattern &pattern)
- {
-   ResolvePath::go (pattern.get_path ());
- 
-   auto &struct_pattern_elems = pattern.get_struct_pattern_elems ();
-   for (auto &field : struct_pattern_elems.get_struct_pattern_fields ())
-     {
-       switch (field->get_item_type ())
- 	{
- 	case AST::StructPatternField::ItemType::TUPLE_PAT:
- 	  {
- 	    AST::StructPatternFieldTuplePat &tuple
- 	      = static_cast<AST::StructPatternFieldTuplePat &> (*field);
- 
- 	    tuple.get_index_pattern ().accept_vis (*this);
- 	  }
- 	  break;
- 
- 	case AST::StructPatternField::ItemType::IDENT_PAT:
- 	  {
- 	    AST::StructPatternFieldIdentPat &ident
- 	      = static_cast<AST::StructPatternFieldIdentPat &> (*field);
- 
- 	    ident.get_ident_pattern ().accept_vis (*this);
- 	  }
- 	  break;
- 
- 	case AST::StructPatternField::ItemType::IDENT:
- 	  {
- 	    auto &ident = static_cast<AST::StructPatternFieldIdent &> (*field);
- 
- 	    Mutability mut
- 	      = ident.is_mut () ? Mutability::Mut : Mutability::Imm;
- 
- 	    add_new_binding (ident.get_identifier (), ident.get_node_id (),
- 			     BindingTypeInfo (mut, ident.is_ref (),
- 					      ident.get_locus ()));
- 	  }
- 	  break;
- 	}
-     }
- }
- 
- void
- PatternDeclaration::visit (AST::TuplePattern &pattern)
- {
-   auto &items = pattern.get_items ();
-   switch (items.get_pattern_type ())
-     {
-     case AST::TuplePatternItems::TuplePatternItemType::MULTIPLE:
-       {
- 	auto &ref = static_cast<AST::TuplePatternItemsMultiple &> (
- 	  pattern.get_items ());
- 
- 	for (auto &p : ref.get_patterns ())
- 	  p->accept_vis (*this);
-       }
-       break;
- 
-     case AST::TuplePatternItems::TuplePatternItemType::RANGED:
-       {
- 	auto &ref
- 	  = static_cast<AST::TuplePatternItemsRanged &> (pattern.get_items ());
- 
- 	for (auto &p : ref.get_lower_patterns ())
- 	  p->accept_vis (*this);
- 	for (auto &p : ref.get_upper_patterns ())
- 	  p->accept_vis (*this);
-       }
-       break;
-     }
- }
- 
- void
- PatternDeclaration::visit (AST::AltPattern &pattern)
- {
-   // push a new set of 'Or' bindings to the stack. Accounts for the
-   // alternatives. e.g. in `p_0 | p_1`, bindings to the same identifier between
-   // p_0 and p_1 shouldn't cause an error.
-   bindings_with_ctx.push_back (
-     PatternBinding (PatternBoundCtx::Or, std::set<Identifier> ()));
- 
-   // This is a hack to avoid creating a separate visitor class for the
-   // consistency checks. We empty out the binding_info_map before each iteration
-   // to separate between the alts' binding_maps. And right after the alt
-   // visit...
-   auto tmp_binding_map = binding_info_map;
-   binding_info_map.clear ();
- 
-   std::vector<BindingMap> alts_binding_maps;
- 
-   for (auto &alt : pattern.get_alts ())
-     {
-       // before this visit, the binding_info_map is guaranteed to be empty
-       rust_assert (binding_info_map.empty ());
- 
-       // push a new `Product` context to correctly reject multiple bindings
-       // within this single alt.
-       bindings_with_ctx.push_back (
- 	PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ()));
- 
-       alt->accept_vis (*this);
- 
-       // ...the binding_info_map is (potentially) populated. We copy it to the
-       // vector, and empty it out to be ready for the next iteration. And after
-       // all the iterations are finished...
-       alts_binding_maps.push_back (binding_info_map);
-       binding_info_map.clear ();
- 
-       // Remove the last (i.e. `Product`) context and add the bindings from the
-       // visited alt to the one before last (i.e. `Or`). Now (after checking
-       // with the alt internally), the bindings from this alt will reside in the
-       // `Or` context.
-       auto last_bound_idents = bindings_with_ctx.back ().idents;
-       bindings_with_ctx.pop_back ();
- 
-       for (auto &ident : last_bound_idents)
- 	{
- 	  bindings_with_ctx.back ().idents.insert (ident);
- 	}
-     }
- 
-   // Now we can finally check for consistency.
-   check_bindings_consistency (alts_binding_maps);
- 
-   // Now we remove the `Or` context we pushed earlier.
-   // e.g. in `(a, (p_0 | p_1), c)`: after finishing up inside the alt pattern,
-   // we return to the tuple (`Product`) context and push the new bindings.
-   auto idents = bindings_with_ctx.back ().idents;
-   bindings_with_ctx.pop_back ();
-   for (auto &ident : idents)
-     bindings_with_ctx.back ().idents.insert (ident.as_string ());
- 
-   // ...we repopulate the binding_info_map correctly (the initial bindings
-   // stored in the tmp_binding_map + all the bindings from all the alts)
-   binding_info_map = tmp_binding_map;
-   for (auto &alt_map : alts_binding_maps)
-     for (auto &map_entry : alt_map)
-       binding_info_map.insert (map_entry);
- }
- 
- void
- PatternDeclaration::add_new_binding (Identifier ident, NodeId node_id,
- 				     BindingTypeInfo info)
- {
-   bool has_binding_ctx = bindings_with_ctx.size () > 0;
-   rust_assert (has_binding_ctx);
- 
-   bool identifier_or_bound = false, identifier_product_bound = false;
- 
-   for (auto binding : bindings_with_ctx)
-     {
-       bool identifier_bound_here
- 	= (binding.idents.find (ident) != binding.idents.end ());
-       if (identifier_bound_here)
- 	{
- 	  identifier_product_bound |= binding.ctx == PatternBoundCtx::Product;
- 	  identifier_or_bound |= binding.ctx == PatternBoundCtx::Or;
- 	}
-     }
- 
-   if (identifier_product_bound)
-     {
-       if (type == Rib::ItemType::Param)
- 	{
- 	  rust_error_at (info.get_locus (), ErrorCode::E0415,
- 			 "identifier '%s' is bound more than once in the "
- 			 "same parameter list",
- 			 ident.as_string ().c_str ());
- 	}
-       else
- 	{
- 	  rust_error_at (
- 	    info.get_locus (), ErrorCode::E0416,
- 	    "identifier '%s' is bound more than once in the same pattern",
- 	    ident.as_string ().c_str ());
- 	}
- 
-       return;
-     }
- 
-   if (!identifier_or_bound)
-     {
-       bindings_with_ctx.back ().idents.insert (ident);
-       resolver->get_name_scope ().insert (
- 	CanonicalPath::new_seg (node_id, ident.as_string ()), node_id,
- 	info.get_locus (), type);
-     }
- 
-   binding_info_map.insert ({ident, info});
- }
- 
- // Verifies that all the alts in an AltPattern have the same set of bindings
- // with the same mutability and reference states.
- void
- PatternDeclaration::check_bindings_consistency (
-   std::vector<BindingMap> &binding_maps)
- {
-   for (size_t i = 0; i < binding_maps.size (); i++)
-     {
-       auto &outer_bindings_map = binding_maps[i];
- 
-       for (size_t j = 0; j < binding_maps.size (); j++)
- 	{
- 	  // skip comparing the current outer map with itself.
- 	  if (j == i)
- 	    continue;
- 
- 	  auto &inner_bindings_map = binding_maps[j];
- 
- 	  // iterate over the inner map entries and check if they exist in outer
- 	  // map
- 	  for (auto map_entry : inner_bindings_map)
- 	    {
- 	      auto ident = map_entry.first;	  // key
- 	      auto inner_info = map_entry.second; // value
- 	      bool ident_is_outer_bound = outer_bindings_map.count (ident);
- 
- 	      if (!ident_is_outer_bound && !missing_bindings.count (ident))
- 		missing_bindings.insert ({ident, inner_info});
- 
- 	      else if (outer_bindings_map.count (ident)
- 		       && outer_bindings_map[ident] != inner_info
- 		       && !inconsistent_bindings.count (ident))
- 		inconsistent_bindings.insert ({ident, inner_info});
- 	    }
- 	}
-     }
- }
- 
- static void
- resolve_range_pattern_bound (AST::RangePatternBound &bound)
- {
-   switch (bound.get_bound_type ())
-     {
-     case AST::RangePatternBound::RangePatternBoundType::LITERAL:
-       // Nothing to resolve for a literal.
-       break;
- 
-     case AST::RangePatternBound::RangePatternBoundType::PATH:
-       {
- 	auto &ref = static_cast<AST::RangePatternBoundPath &> (bound);
- 
- 	ResolvePath::go (ref.get_path ());
-       }
-       break;
- 
-     case AST::RangePatternBound::RangePatternBoundType::QUALPATH:
-       {
- 	auto &ref = static_cast<AST::RangePatternBoundQualPath &> (bound);
- 
- 	ResolvePath::go (ref.get_qualified_path ());
-       }
-       break;
-     }
- }
- 
- void
- PatternDeclaration::visit (AST::RangePattern &pattern)
- {
-   resolve_range_pattern_bound (pattern.get_upper_bound ());
-   resolve_range_pattern_bound (pattern.get_lower_bound ());
- }
- 
- void
- PatternDeclaration::visit (AST::SlicePattern &pattern)
- {
-   auto &items = pattern.get_items ();
-   switch (items.get_pattern_type ())
-     {
-     case AST::SlicePatternItems::SlicePatternItemType::NO_REST:
-       {
- 	auto &ref
- 	  = static_cast<AST::SlicePatternItemsNoRest &> (pattern.get_items ());
- 
- 	for (auto &p : ref.get_patterns ())
- 	  p->accept_vis (*this);
-       }
-       break;
- 
-     case AST::SlicePatternItems::SlicePatternItemType::HAS_REST:
-       {
- 	auto &ref
- 	  = static_cast<AST::SlicePatternItemsHasRest &> (pattern.get_items ());
- 
- 	for (auto &p : ref.get_lower_patterns ())
- 	  p->accept_vis (*this);
- 	for (auto &p : ref.get_upper_patterns ())
- 	  p->accept_vis (*this);
-       }
-       break;
-     }
- }
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-pattern.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-pattern.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-pattern.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-pattern.h	Thu Jan  1 00:00:00 1970
***************
*** 1,146 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_PATTERN_H
- #define RUST_AST_RESOLVE_PATTERN_H
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast-full.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- // Specifies whether the set of already bound patterns are related by 'Or' or
- // 'Product'. Used to check for multiple bindings to the same identifier.
- enum PatternBoundCtx
- {
-   // A product pattern context (e.g. struct and tuple patterns)
-   Product,
-   // An or-pattern context (e.g. p_0 | p_1 | ...)
-   Or,
- };
- 
- struct PatternBinding
- {
-   PatternBoundCtx ctx;
-   std::set<Identifier> idents;
- 
-   PatternBinding (PatternBoundCtx ctx, std::set<Identifier> idents)
-     : ctx (ctx), idents (idents)
-   {}
- };
- 
- // Info that gets stored in the map. Helps us detect if two bindings to the same
- // identifier have different mutability or ref states.
- class BindingTypeInfo
- {
-   Mutability mut;
-   bool is_ref;
-   location_t locus;
- 
- public:
-   BindingTypeInfo (Mutability mut, bool is_ref, location_t locus)
-     : mut (mut), is_ref (is_ref), locus (locus)
-   {}
- 
-   BindingTypeInfo (BindingTypeInfo const &other)
-     : mut (other.mut), is_ref (other.is_ref), locus (other.get_locus ())
-   {}
- 
-   BindingTypeInfo (){};
- 
-   location_t get_locus () const { return locus; }
-   Mutability get_mut () const { return mut; }
-   bool get_is_ref () const { return is_ref; }
- 
-   BindingTypeInfo operator= (BindingTypeInfo const &other)
-   {
-     mut = other.mut;
-     is_ref = other.is_ref;
-     locus = other.get_locus ();
- 
-     return *this;
-   }
- 
-   bool operator== (BindingTypeInfo const &other)
-   {
-     return mut == other.mut && is_ref == other.is_ref;
-   }
- 
-   bool operator!= (BindingTypeInfo const &other)
-   {
-     return !BindingTypeInfo::operator== (other);
-   }
- };
- 
- typedef std::map<Identifier, BindingTypeInfo> BindingMap;
- 
- class PatternDeclaration : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::Pattern &pattern, Rib::ItemType type);
-   static void go (AST::Pattern &pattern, Rib::ItemType type,
- 		  std::vector<PatternBinding> &bindings);
- 
-   void visit (AST::IdentifierPattern &pattern) override;
-   void visit (AST::GroupedPattern &pattern) override;
-   void visit (AST::ReferencePattern &pattern) override;
-   void visit (AST::PathInExpression &pattern) override;
-   void visit (AST::StructPattern &pattern) override;
-   void visit (AST::TupleStructPattern &pattern) override;
-   void visit (AST::TuplePattern &pattern) override;
-   void visit (AST::RangePattern &pattern) override;
-   void visit (AST::AltPattern &pattern) override;
-   void visit (AST::SlicePattern &pattern) override;
- 
-   void add_new_binding (Identifier ident, NodeId node_id, BindingTypeInfo info);
-   void check_bindings_consistency (std::vector<BindingMap> &binding_maps);
- 
- private:
-   PatternDeclaration (std::vector<PatternBinding> &bindings_with_ctx,
- 		      Rib::ItemType type)
-     : ResolverBase (), bindings_with_ctx (bindings_with_ctx), type (type)
-   {}
- 
-   // To avoid having a separate visitor for consistency checks, we store
-   // bindings in two forms:
- 
-   // 1) Bindings as a vector of context-related sets.
-   // Used for checking multiple bindings to the same identifier (i.e. E0415,
-   // E0416).
-   std::vector<PatternBinding> &bindings_with_ctx;
- 
-   // 2) Bindings as a map between identifiers and binding info.
-   // Used for checking consistency between alt patterns (i.e. E0408, E0409).
-   BindingMap binding_info_map;
- 
-   // we need to insert the missing and inconsistent bindings (found in
-   // check_bindings_consistency) into maps to avoid duplication of error
-   // messages.
-   BindingMap inconsistent_bindings;
-   BindingMap missing_bindings;
- 
-   Rib::ItemType type;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_PATTERN_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-stmt.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-stmt.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-stmt.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-stmt.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,81 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-toplevel.h"
- #include "rust-ast-resolve-item.h"
- #include "rust-ast-resolve-stmt.h"
- #include "rust-ast-resolve-implitem.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- void
- ResolveStmt::visit (AST::ExternBlock &extern_block)
- {
-   resolve_visibility (extern_block.get_visibility ());
-   for (auto &item : extern_block.get_extern_items ())
-     {
-       ResolveToplevelExternItem::go (*item, CanonicalPath::create_empty ());
-       ResolveExternItem::go (*item, prefix, canonical_prefix);
-     }
- }
- 
- void
- ResolveStmt::visit (AST::Trait &trait)
- {
-   ResolveTopLevel::go (trait, prefix, canonical_prefix);
-   ResolveItem::go (trait, prefix, canonical_prefix);
- }
- 
- void
- ResolveStmt::visit (AST::InherentImpl &impl_block)
- {
-   ResolveTopLevel::go (impl_block, prefix, canonical_prefix);
-   ResolveItem::go (impl_block, prefix, canonical_prefix);
- }
- 
- void
- ResolveStmt::visit (AST::TraitImpl &impl_block)
- {
-   ResolveTopLevel::go (impl_block, prefix, canonical_prefix);
-   ResolveItem::go (impl_block, prefix, canonical_prefix);
- }
- 
- void
- ResolveStmt::visit (AST::StaticItem &var)
- {
-   auto decl = CanonicalPath::new_seg (var.get_node_id (),
- 				      var.get_identifier ().as_string ());
-   auto path = decl;
-   auto cpath = canonical_prefix.append (decl);
-   mappings.insert_canonical_path (var.get_node_id (), cpath);
- 
-   resolver->get_name_scope ().insert (
-     path, var.get_node_id (), var.get_locus (), false, Rib::ItemType::Static,
-     [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
-       rich_location r (line_table, var.get_locus ());
-       r.add_range (locus);
-       redefined_error (r);
-     });
- 
-   ResolveType::go (var.get_type ());
-   ResolveExpr::go (var.get_expr (), path, cpath);
- }
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-stmt.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-stmt.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-stmt.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-stmt.h	Thu Jan  1 00:00:00 1970
***************
*** 1,408 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_STMT_H
- #define RUST_AST_RESOLVE_STMT_H
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast-resolve-type.h"
- #include "rust-ast-resolve-pattern.h"
- #include "rust-ast-resolve-expr.h"
- #include "rust-item.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolveStmt : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::Stmt &stmt, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix,
- 		  const CanonicalPath &enum_prefix)
-   {
-     if (stmt.is_marked_for_strip ())
-       return;
- 
-     ResolveStmt resolver (prefix, canonical_prefix, enum_prefix);
-     stmt.accept_vis (resolver);
-   }
- 
-   void visit (AST::ExprStmt &stmt) override
-   {
-     ResolveExpr::go (stmt.get_expr (), prefix, canonical_prefix);
-   }
- 
-   void visit (AST::ConstantItem &constant) override
-   {
-     auto decl = CanonicalPath::new_seg (constant.get_node_id (),
- 					constant.get_identifier ());
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (constant.get_node_id (), cpath);
- 
-     resolver->get_name_scope ().insert (
-       path, constant.get_node_id (), constant.get_locus (), false,
-       Rib::ItemType::Const,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, constant.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     ResolveType::go (constant.get_type ());
-     if (constant.has_expr ())
-       ResolveExpr::go (constant.get_expr (), prefix, canonical_prefix);
-   }
- 
-   void visit (AST::LetStmt &stmt) override
-   {
-     if (stmt.has_init_expr ())
-       ResolveExpr::go (stmt.get_init_expr (), prefix, canonical_prefix);
- 
-     if (stmt.has_else_expr ())
-       ResolveExpr::go (stmt.get_else_expr (), prefix, canonical_prefix);
- 
-     PatternDeclaration::go (stmt.get_pattern (), Rib::ItemType::Var);
-     if (stmt.has_type ())
-       ResolveType::go (stmt.get_type ());
-   }
- 
-   void visit (AST::TupleStruct &struct_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (struct_decl.get_node_id (),
- 				struct_decl.get_identifier ().as_string ());
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (struct_decl.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, struct_decl.get_node_id (), struct_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, struct_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId scope_node_id = struct_decl.get_node_id ();
-     resolver->get_type_scope ().push (scope_node_id);
- 
-     if (struct_decl.has_generics ())
-       ResolveGenericParams::go (struct_decl.get_generic_params (), prefix,
- 				canonical_prefix);
- 
-     for (AST::TupleField &field : struct_decl.get_fields ())
-       ResolveType::go (field.get_field_type ());
- 
-     resolver->get_type_scope ().pop ();
-   }
- 
-   void visit (AST::Enum &enum_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (enum_decl.get_node_id (),
- 				enum_decl.get_identifier ().as_string ());
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (enum_decl.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, enum_decl.get_node_id (), enum_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, enum_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId scope_node_id = enum_decl.get_node_id ();
-     resolver->get_type_scope ().push (scope_node_id);
- 
-     if (enum_decl.has_generics ())
-       ResolveGenericParams::go (enum_decl.get_generic_params (), prefix,
- 				canonical_prefix);
- 
-     for (auto &variant : enum_decl.get_variants ())
-       ResolveStmt::go (*variant, path, canonical_prefix, path);
- 
-     resolver->get_type_scope ().pop ();
-   }
- 
-   void visit (AST::EnumItem &item) override
-   {
-     auto decl = enum_prefix.append (
-       CanonicalPath::new_seg (item.get_node_id (),
- 			      item.get_identifier ().as_string ()));
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     // Done, no fields.
-   }
- 
-   void visit (AST::EnumItemTuple &item) override
-   {
-     auto decl = enum_prefix.append (
-       CanonicalPath::new_seg (item.get_node_id (),
- 			      item.get_identifier ().as_string ()));
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     for (auto &field : item.get_tuple_fields ())
-       {
- 	if (field.get_field_type ().is_marked_for_strip ())
- 	  continue;
- 
- 	ResolveType::go (field.get_field_type ());
-       }
-   }
- 
-   void visit (AST::EnumItemStruct &item) override
-   {
-     auto decl = enum_prefix.append (
-       CanonicalPath::new_seg (item.get_node_id (),
- 			      item.get_identifier ().as_string ()));
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     for (auto &field : item.get_struct_fields ())
-       {
- 	if (field.get_field_type ().is_marked_for_strip ())
- 	  continue;
- 
- 	ResolveType::go (field.get_field_type ());
-       }
-   }
- 
-   void visit (AST::EnumItemDiscriminant &item) override
-   {
-     auto decl = enum_prefix.append (
-       CanonicalPath::new_seg (item.get_node_id (),
- 			      item.get_identifier ().as_string ()));
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     // Done, no fields.
-   }
- 
-   void visit (AST::StructStruct &struct_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (struct_decl.get_node_id (),
- 				struct_decl.get_identifier ().as_string ());
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (struct_decl.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, struct_decl.get_node_id (), struct_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, struct_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId scope_node_id = struct_decl.get_node_id ();
-     resolver->get_type_scope ().push (scope_node_id);
- 
-     if (struct_decl.has_generics ())
-       ResolveGenericParams::go (struct_decl.get_generic_params (), prefix,
- 				canonical_prefix);
- 
-     for (AST::StructField &field : struct_decl.get_fields ())
-       {
- 	if (field.get_field_type ().is_marked_for_strip ())
- 	  continue;
- 
- 	ResolveType::go (field.get_field_type ());
-       }
- 
-     resolver->get_type_scope ().pop ();
-   }
- 
-   void visit (AST::Union &union_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (union_decl.get_node_id (),
- 				union_decl.get_identifier ().as_string ());
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (union_decl.get_node_id (), cpath);
- 
-     resolver->get_type_scope ().insert (
-       path, union_decl.get_node_id (), union_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, union_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId scope_node_id = union_decl.get_node_id ();
-     resolver->get_type_scope ().push (scope_node_id);
- 
-     if (union_decl.has_generics ())
-       ResolveGenericParams::go (union_decl.get_generic_params (), prefix,
- 				canonical_prefix);
- 
-     for (AST::StructField &field : union_decl.get_variants ())
-       {
- 	if (field.get_field_type ().is_marked_for_strip ())
- 	  continue;
- 
- 	ResolveType::go (field.get_field_type ());
-       }
- 
-     resolver->get_type_scope ().pop ();
-   }
- 
-   void visit (AST::Function &function) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (function.get_node_id (),
- 				function.get_function_name ().as_string ());
-     auto path = decl; // this ensures we have the correct relative resolution
-     auto cpath = canonical_prefix.append (decl);
-     mappings.insert_canonical_path (function.get_node_id (), cpath);
- 
-     resolver->get_name_scope ().insert (
-       path, function.get_node_id (), function.get_locus (), false,
-       Rib::ItemType::Function,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, function.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId scope_node_id = function.get_node_id ();
-     resolver->get_name_scope ().push (scope_node_id);
-     resolver->get_type_scope ().push (scope_node_id);
-     resolver->get_label_scope ().push (scope_node_id);
-     resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-     resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-     resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-     if (function.has_generics ())
-       ResolveGenericParams::go (function.get_generic_params (), prefix,
- 				canonical_prefix);
- 
-     if (function.has_return_type ())
-       ResolveType::go (function.get_return_type ());
- 
-     std::vector<PatternBinding> bindings
-       = {PatternBinding (PatternBoundCtx::Product, std::set<Identifier> ())};
- 
-     // we make a new scope so the names of parameters are resolved and shadowed
-     // correctly
-     for (auto &p : function.get_function_params ())
-       {
- 	if (p->is_variadic ())
- 	  {
- 	    auto &param = static_cast<AST::VariadicParam &> (*p);
- 	    PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param,
- 				    bindings);
- 	  }
- 
- 	else if (p->is_self ())
- 	  {
- 	    auto &param = static_cast<AST::SelfParam &> (*p);
- 	    ResolveType::go (param.get_type ());
- 	  }
- 	else
- 	  {
- 	    auto &param = static_cast<AST::FunctionParam &> (*p);
- 
- 	    ResolveType::go (param.get_type ());
- 	    PatternDeclaration::go (param.get_pattern (), Rib::ItemType::Param,
- 				    bindings);
- 	  }
-       }
- 
-     // resolve the function body
-     ResolveExpr::go (*function.get_definition ().value (), path, cpath);
- 
-     resolver->get_name_scope ().pop ();
-     resolver->get_type_scope ().pop ();
-     resolver->get_label_scope ().pop ();
-   }
- 
-   void visit (AST::ExternBlock &extern_block) override;
-   void visit (AST::Trait &trait) override;
-   void visit (AST::InherentImpl &impl_block) override;
-   void visit (AST::TraitImpl &impl_block) override;
-   void visit (AST::StaticItem &var) override;
- 
- private:
-   ResolveStmt (const CanonicalPath &prefix,
- 	       const CanonicalPath &canonical_prefix,
- 	       const CanonicalPath &enum_prefix)
-     : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix),
-       enum_prefix (enum_prefix)
-   {}
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- 
-   /* item declaration statements are not given a canonical path, but enum items
-    * (variants) do inherit the enum path/identifier name.  */
-   const CanonicalPath &enum_prefix;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_STMT_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,61 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-struct-expr-field.h"
- #include "rust-ast-resolve-expr.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- void
- ResolveStructExprField::go (AST::StructExprField &field,
- 			    const CanonicalPath &prefix,
- 			    const CanonicalPath &canonical_prefix)
- {
-   ResolveStructExprField resolver (prefix, canonical_prefix);
-   field.accept_vis (resolver);
- }
- 
- ResolveStructExprField::ResolveStructExprField (
-   const CanonicalPath &prefix, const CanonicalPath &canonical_prefix)
-   : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
- {}
- 
- void
- ResolveStructExprField::visit (AST::StructExprFieldIdentifierValue &field)
- {
-   ResolveExpr::go (field.get_value (), prefix, canonical_prefix);
- }
- 
- void
- ResolveStructExprField::visit (AST::StructExprFieldIndexValue &field)
- {
-   ResolveExpr::go (field.get_value (), prefix, canonical_prefix);
- }
- 
- void
- ResolveStructExprField::visit (AST::StructExprFieldIdentifier &field)
- {
-   AST::IdentifierExpr expr (field.get_field_name (), {}, field.get_locus ());
-   expr.set_node_id (field.get_node_id ());
- 
-   ResolveExpr::go (expr, prefix, canonical_prefix);
- }
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-struct-expr-field.h	Thu Jan  1 00:00:00 1970
***************
*** 1,54 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_STRUCT_EXPR_FIELD
- #define RUST_AST_RESOLVE_STRUCT_EXPR_FIELD
- 
- #include "rust-ast-resolve-base.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- // this resolves values being assigned not that the field actually exists yet.
- 
- class ResolveStructExprField : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::StructExprField &field, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix);
- 
-   void visit (AST::StructExprFieldIdentifierValue &field) override;
- 
-   void visit (AST::StructExprFieldIndexValue &field) override;
- 
-   void visit (AST::StructExprFieldIdentifier &field) override;
- 
- private:
-   ResolveStructExprField (const CanonicalPath &prefix,
- 			  const CanonicalPath &canonical_prefix);
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_STRUCT_EXPR_FIELD
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-toplevel.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-toplevel.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-toplevel.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-toplevel.h	Thu Jan  1 00:00:00 1970
***************
*** 1,500 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_TOPLEVEL_H
- #define RUST_AST_RESOLVE_TOPLEVEL_H
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast-resolve-implitem.h"
- #include "rust-name-resolver.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolveTopLevel : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::Item &item, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix)
-   {
-     if (item.is_marked_for_strip ())
-       return;
- 
-     ResolveTopLevel resolver (prefix, canonical_prefix);
-     item.accept_vis (resolver);
- 
-     NodeId current_module = resolver.resolver->peek_current_module_scope ();
-     resolver.mappings.insert_child_item_to_parent_module_mapping (
-       item.get_node_id (), current_module);
-   }
- 
-   void visit (AST::Module &module) override
-   {
-     auto mod = CanonicalPath::new_seg (module.get_node_id (),
- 				       module.get_name ().as_string ());
-     auto path = prefix.append (mod);
-     auto cpath = canonical_prefix.append (mod);
- 
-     resolver->get_name_scope ().insert (
-       path, module.get_node_id (), module.get_locus (), false,
-       Rib::ItemType::Module,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, module.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, mod);
-     mappings.insert_module_child (current_module, module.get_node_id ());
- 
-     resolver->push_new_module_scope (module.get_node_id ());
-     for (auto &item : module.get_items ())
-       ResolveTopLevel::go (*item, path, cpath);
- 
-     resolver->pop_module_scope ();
- 
-     mappings.insert_canonical_path (module.get_node_id (), cpath);
-   }
- 
-   void visit (AST::TypeAlias &alias) override
-   {
-     auto talias
-       = CanonicalPath::new_seg (alias.get_node_id (),
- 				alias.get_new_type_name ().as_string ());
-     auto path = prefix.append (talias);
-     auto cpath = canonical_prefix.append (talias);
- 
-     resolver->get_type_scope ().insert (
-       path, alias.get_node_id (), alias.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, alias.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, talias);
-     mappings.insert_canonical_path (alias.get_node_id (), cpath);
-   }
- 
-   void visit (AST::TupleStruct &struct_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (struct_decl.get_node_id (),
- 				struct_decl.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, struct_decl.get_node_id (), struct_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, struct_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (struct_decl.get_node_id (), cpath);
-   }
- 
-   void visit (AST::Enum &enum_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (enum_decl.get_node_id (),
- 				enum_decl.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, enum_decl.get_node_id (), enum_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, enum_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     resolver->push_new_module_scope (enum_decl.get_node_id ());
-     for (auto &variant : enum_decl.get_variants ())
-       ResolveTopLevel::go (*variant, path, cpath);
- 
-     resolver->pop_module_scope ();
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (enum_decl.get_node_id (), cpath);
-   }
- 
-   void visit (AST::EnumItem &item) override
-   {
-     auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 					item.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_module_child (current_module, item.get_node_id ());
-   }
- 
-   void visit (AST::EnumItemTuple &item) override
-   {
-     auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 					item.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_module_child (current_module, item.get_node_id ());
-   }
- 
-   void visit (AST::EnumItemStruct &item) override
-   {
-     auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 					item.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_module_child (current_module, item.get_node_id ());
-   }
- 
-   void visit (AST::EnumItemDiscriminant &item) override
-   {
-     auto decl = CanonicalPath::new_seg (item.get_node_id (),
- 					item.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, item.get_node_id (), item.get_locus (), false, Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, item.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     mappings.insert_canonical_path (item.get_node_id (), cpath);
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_module_child (current_module, item.get_node_id ());
-   }
- 
-   void visit (AST::StructStruct &struct_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (struct_decl.get_node_id (),
- 				struct_decl.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     auto duplicate_item
-       = [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
-       rich_location r (line_table, struct_decl.get_locus ());
-       r.add_range (locus);
-       redefined_error (r);
-     };
- 
-     resolver->get_type_scope ().insert (path, struct_decl.get_node_id (),
- 					struct_decl.get_locus (), false,
- 					Rib::ItemType::Type, duplicate_item);
- 
-     if (struct_decl.is_unit_struct ())
-       resolver->get_name_scope ().insert (path, struct_decl.get_node_id (),
- 					  struct_decl.get_locus (), false,
- 					  Rib::ItemType::Type, duplicate_item);
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (struct_decl.get_node_id (), cpath);
-   }
- 
-   void visit (AST::Union &union_decl) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (union_decl.get_node_id (),
- 				union_decl.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, union_decl.get_node_id (), union_decl.get_locus (), false,
-       Rib::ItemType::Type,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, union_decl.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (union_decl.get_node_id (), cpath);
-   }
- 
-   void visit (AST::StaticItem &var) override
-   {
-     auto decl = CanonicalPath::new_seg (var.get_node_id (),
- 					var.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, var.get_node_id (), var.get_locus (), false, Rib::ItemType::Static,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, var.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (var.get_node_id (), cpath);
-   }
- 
-   void visit (AST::ConstantItem &constant) override
-   {
-     auto decl = CanonicalPath::new_seg (constant.get_node_id (),
- 					constant.get_identifier ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, constant.get_node_id (), constant.get_locus (), false,
-       Rib::ItemType::Const,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, constant.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (constant.get_node_id (), cpath);
-   }
- 
-   void visit (AST::Function &function) override
-   {
-     auto decl
-       = CanonicalPath::new_seg (function.get_node_id (),
- 				function.get_function_name ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_name_scope ().insert (
-       path, function.get_node_id (), function.get_locus (), false,
-       Rib::ItemType::Function,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, function.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (function.get_node_id (), cpath);
-   }
- 
-   void visit (AST::InherentImpl &impl_block) override
-   {
-     std::string raw_impl_type_path = impl_block.get_type ().as_string ();
-     CanonicalPath impl_type_seg
-       = CanonicalPath::new_seg (impl_block.get_type ().get_node_id (),
- 				raw_impl_type_path);
- 
-     CanonicalPath impl_type
-       = CanonicalPath::inherent_impl_seg (impl_block.get_node_id (),
- 					  impl_type_seg);
-     CanonicalPath impl_prefix = prefix.append (impl_type_seg);
- 
-     for (auto &impl_item : impl_block.get_impl_items ())
-       ResolveToplevelImplItem::go (*impl_item, impl_prefix);
-   }
- 
-   void visit (AST::TraitImpl &impl_block) override
-   {
-     std::string raw_impl_type_path = impl_block.get_type ().as_string ();
-     CanonicalPath impl_type_seg
-       = CanonicalPath::new_seg (impl_block.get_type ().get_node_id (),
- 				raw_impl_type_path);
- 
-     std::string raw_trait_type_path = impl_block.get_trait_path ().as_string ();
-     CanonicalPath trait_type_seg
-       = CanonicalPath::new_seg (impl_block.get_trait_path ().get_node_id (),
- 				raw_trait_type_path);
- 
-     CanonicalPath projection
-       = CanonicalPath::trait_impl_projection_seg (impl_block.get_node_id (),
- 						  trait_type_seg,
- 						  impl_type_seg);
-     CanonicalPath impl_prefix = prefix.append (projection);
- 
-     resolver->get_name_scope ().insert (
-       impl_prefix, impl_block.get_node_id (), impl_block.get_locus (), false,
-       Rib::ItemType::TraitImpl,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, impl_block.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     for (auto &impl_item : impl_block.get_impl_items ())
-       ResolveToplevelImplItem::go (*impl_item, impl_prefix);
-   }
- 
-   void visit (AST::Trait &trait) override
-   {
-     auto decl = CanonicalPath::new_seg (trait.get_node_id (),
- 					trait.get_identifier ().as_string ());
-     auto path = prefix.append (decl);
-     auto cpath = canonical_prefix.append (decl);
- 
-     resolver->get_type_scope ().insert (
-       path, trait.get_node_id (), trait.get_locus (), false,
-       Rib::ItemType::Trait,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, trait.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
- 
-     for (auto &item : trait.get_trait_items ())
-       ResolveTopLevelTraitItems::go (item.get (), path, cpath);
- 
-     NodeId current_module = resolver->peek_current_module_scope ();
-     mappings.insert_module_child_item (current_module, decl);
-     mappings.insert_canonical_path (trait.get_node_id (), cpath);
-   }
- 
-   void visit (AST::ExternBlock &extern_block) override
-   {
-     for (auto &item : extern_block.get_extern_items ())
-       {
- 	ResolveToplevelExternItem::go (*item, prefix);
-       }
-   }
- 
-   void visit (AST::ExternCrate &extern_crate) override
-   {
-     if (extern_crate.is_marked_for_strip ())
-       return;
- 
-     NodeId resolved_crate = UNKNOWN_NODEID;
-     if (extern_crate.references_self ())
-       {
- 	CrateNum crate_num = mappings.get_current_crate ();
- 	resolved_crate = mappings.crate_num_to_nodeid (crate_num).value ();
-       }
-     else
-       {
- 	auto cnum
- 	  = mappings.lookup_crate_name (extern_crate.get_referenced_crate ());
- 	if (!cnum)
- 	  {
- 	    rust_error_at (extern_crate.get_locus (), "unknown crate %qs",
- 			   extern_crate.get_referenced_crate ().c_str ());
- 	    return;
- 	  }
- 	if (auto resolved = mappings.crate_num_to_nodeid (*cnum))
- 	  resolved_crate = resolved.value ();
- 	else
- 	  {
- 	    rust_internal_error_at (extern_crate.get_locus (),
- 				    "failed to resolve crate to nodeid");
- 	    return;
- 	  }
-       }
- 
-     if (resolved_crate == UNKNOWN_NODEID)
-       {
- 	rust_error_at (extern_crate.get_locus (), "failed to resolve crate");
- 	return;
-       }
- 
-     // mark the node as resolved
-     resolver->insert_resolved_name (extern_crate.get_node_id (),
- 				    resolved_crate);
-     CanonicalPath decl
-       = extern_crate.has_as_clause ()
- 	  ? CanonicalPath::new_seg (extern_crate.get_node_id (),
- 				    extern_crate.get_as_clause ())
- 	  : CanonicalPath::new_seg (extern_crate.get_node_id (),
- 				    extern_crate.get_referenced_crate ());
- 
-     resolver->get_type_scope ().insert (
-       decl, resolved_crate, extern_crate.get_locus (), false,
-       Rib::ItemType::ExternCrate,
-       [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	rich_location r (line_table, extern_crate.get_locus ());
- 	r.add_range (locus);
- 	redefined_error (r);
-       });
-   }
- 
- private:
-   ResolveTopLevel (const CanonicalPath &prefix,
- 		   const CanonicalPath &canonical_prefix)
-     : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
-   {}
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_TOPLEVEL_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-type.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-type.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-type.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-type.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,785 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve-type.h"
- #include "rust-ast-resolve-expr.h"
- #include "rust-canonical-path.h"
- #include "rust-type.h"
- #include "rust-hir-map.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- // rust-ast-resolve-type.h
- 
- NodeId
- ResolveType::go (AST::Type &type)
- {
-   ResolveType resolver;
-   type.accept_vis (resolver);
-   return resolver.resolved_node;
- }
- 
- void
- ResolveType::visit (AST::BareFunctionType &fntype)
- {
-   for (auto &param : fntype.get_function_params ())
-     ResolveType::go (param.get_type ());
- 
-   if (fntype.has_return_type ())
-     ResolveType::go (fntype.get_return_type ());
- }
- 
- void
- ResolveType::visit (AST::TupleType &tuple)
- {
-   if (tuple.is_unit_type ())
-     {
-       resolved_node = resolver->get_unit_type_node_id ();
-       return;
-     }
- 
-   for (auto &elem : tuple.get_elems ())
-     ResolveType::go (*elem);
- }
- 
- void
- ResolveType::visit (AST::TypePath &path)
- {
-   ResolveRelativeTypePath::go (path, resolved_node);
- }
- 
- void
- ResolveType::visit (AST::QualifiedPathInType &path)
- {
-   ResolveRelativeQualTypePath::go (path);
- }
- 
- void
- ResolveType::visit (AST::ArrayType &type)
- {
-   type.get_elem_type ().accept_vis (*this);
-   ResolveExpr::go (type.get_size_expr (), CanonicalPath::create_empty (),
- 		   CanonicalPath::create_empty ());
- }
- 
- void
- ResolveType::visit (AST::TraitObjectTypeOneBound &type)
- {
-   ResolveTypeBound::go (type.get_trait_bound ());
- }
- 
- void
- ResolveType::visit (AST::TraitObjectType &type)
- {
-   for (auto &bound : type.get_type_param_bounds ())
-     {
-       /* NodeId bound_resolved_id = */
-       ResolveTypeBound::go (*bound);
-     }
- }
- 
- void
- ResolveType::visit (AST::ParenthesisedType &type)
- {
-   resolved_node = ResolveType::go (*type.get_type_in_parens ());
- }
- 
- void
- ResolveType::visit (AST::ReferenceType &type)
- {
-   resolved_node = ResolveType::go (type.get_type_referenced ());
- }
- 
- void
- ResolveType::visit (AST::RawPointerType &type)
- {
-   resolved_node = ResolveType::go (type.get_type_pointed_to ());
- }
- 
- void
- ResolveType::visit (AST::InferredType &)
- {
-   // nothing to do
- }
- 
- void
- ResolveType::visit (AST::NeverType &)
- {
-   resolved_node = resolver->get_never_type_node_id ();
- }
- 
- void
- ResolveType::visit (AST::SliceType &type)
- {
-   resolved_node = ResolveType::go (type.get_elem_type ());
- }
- 
- void
- ResolveType::visit (AST::ImplTraitType &type)
- {
-   for (auto &bound : type.get_type_param_bounds ())
-     ResolveTypeBound::go (*bound);
- }
- 
- void
- ResolveType::visit (AST::ImplTraitTypeOneBound &type)
- {
-   ResolveTypeBound::go (*type.get_trait_bound ().get ());
- }
- 
- // resolve relative type-paths
- 
- bool
- ResolveRelativeTypePath::go (AST::TypePath &path, NodeId &resolved_node_id)
- {
-   auto resolver = Resolver::get ();
-   auto &mappings = Analysis::Mappings::get ();
- 
-   NodeId module_scope_id = resolver->peek_current_module_scope ();
-   NodeId previous_resolved_node_id = module_scope_id;
-   for (size_t i = 0; i < path.get_segments ().size (); i++)
-     {
-       auto &segment = path.get_segments ().at (i);
-       bool is_first_segment = i == 0;
-       NodeId crate_scope_id = resolver->peek_crate_module_scope ();
-       auto ident_string = segment->is_lang_item ()
- 			    ? LangItem::PrettyString (segment->get_lang_item ())
- 			    : segment->get_ident_segment ().as_string ();
- 
-       resolved_node_id = UNKNOWN_NODEID;
- 
-       if (segment->is_lang_item ())
- 	{
- 	  resolved_node_id = Analysis::Mappings::get ().get_lang_item_node (
- 	    segment->get_lang_item ());
- 	  previous_resolved_node_id = resolved_node_id;
- 	}
-       else
- 	{
- 	  bool in_middle_of_path = i > 0;
- 	  if (in_middle_of_path && segment->is_lower_self_seg ())
- 	    {
- 	      rust_error_at (segment->get_locus (), ErrorCode::E0433,
- 			     "%qs in paths can only be used in start position",
- 			     segment->as_string ().c_str ());
- 	      return false;
- 	    }
- 
- 	  if (segment->is_crate_path_seg ())
- 	    {
- 	      // what is the current crate scope node id?
- 	      module_scope_id = crate_scope_id;
- 	      previous_resolved_node_id = module_scope_id;
- 	      resolver->insert_resolved_name (segment->get_node_id (),
- 					      module_scope_id);
- 
- 	      continue;
- 	    }
- 	  else if (segment->is_super_path_seg ())
- 	    {
- 	      if (module_scope_id == crate_scope_id)
- 		{
- 		  rust_error_at (segment->get_locus (),
- 				 "cannot use super at the crate scope");
- 		  return false;
- 		}
- 
- 	      module_scope_id = resolver->peek_parent_module_scope ();
- 	      previous_resolved_node_id = module_scope_id;
- 	      resolver->insert_resolved_name (segment->get_node_id (),
- 					      module_scope_id);
- 	      continue;
- 	    }
- 	}
- 
-       switch (segment->get_type ())
- 	{
- 	case AST::TypePathSegment::SegmentType::GENERIC:
- 	  {
- 	    AST::TypePathSegmentGeneric *s
- 	      = static_cast<AST::TypePathSegmentGeneric *> (segment.get ());
- 	    if (s->has_generic_args ())
- 	      ResolveGenericArgs::go (s->get_generic_args ());
- 	  }
- 	  break;
- 
- 	case AST::TypePathSegment::SegmentType::REG:
- 	  // nothing to do
- 	  break;
- 
- 	case AST::TypePathSegment::SegmentType::FUNCTION:
- 	  AST::TypePathSegmentFunction *fnseg
- 	    = static_cast<AST::TypePathSegmentFunction *> (segment.get ());
- 
- 	  AST::TypePathFunction &fn = fnseg->get_type_path_function ();
- 	  for (auto &param : fn.get_params ())
- 	    {
- 	      ResolveType::go (*param);
- 	    }
- 
- 	  if (fn.has_return_type ())
- 	    {
- 	      ResolveType::go (fn.get_return_type ());
- 	    }
- 
- 	  break;
- 	}
- 
-       if (is_first_segment)
- 	{
- 	  // name scope first
- 	  NodeId resolved_node = UNKNOWN_NODEID;
- 	  const CanonicalPath path
- 	    = CanonicalPath::new_seg (segment->get_node_id (), ident_string);
- 	  if (resolver->get_type_scope ().lookup (path, &resolved_node))
- 	    {
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_type (segment->get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_type (segment->get_node_id (),
- 						resolved_node);
- 	      resolved_node_id = resolved_node;
- 	    }
- 	  else if (resolver->get_name_scope ().lookup (path, &resolved_node))
- 	    {
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_name (segment->get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == resolved_node);
- 	      else
- 		resolver->insert_resolved_name (segment->get_node_id (),
- 						resolved_node);
- 	      resolved_node_id = resolved_node;
- 	    }
- 	  else if (!segment->is_lang_item () && segment->is_lower_self_seg ())
- 	    {
- 	      // what is the current crate scope node id?
- 	      module_scope_id = crate_scope_id;
- 	      previous_resolved_node_id = module_scope_id;
- 
- 	      NodeId existing = UNKNOWN_NODEID;
- 	      bool ok = resolver->lookup_resolved_name (segment->get_node_id (),
- 							&existing);
- 
- 	      if (ok)
- 		rust_assert (existing == module_scope_id);
- 	      else
- 		resolver->insert_resolved_name (segment->get_node_id (),
- 						module_scope_id);
- 
- 	      continue;
- 	    }
- 	}
- 
-       if (resolved_node_id == UNKNOWN_NODEID
- 	  && previous_resolved_node_id == module_scope_id)
- 	{
- 	  tl::optional<CanonicalPath &> resolved_child
- 	    = mappings.lookup_module_child (module_scope_id, ident_string);
- 	  if (resolved_child.has_value ())
- 	    {
- 	      NodeId resolved_node = resolved_child->get_node_id ();
- 	      if (resolver->get_name_scope ().decl_was_declared_here (
- 		    resolved_node))
- 		{
- 		  resolved_node_id = resolved_node;
- 
- 		  NodeId existing = UNKNOWN_NODEID;
- 		  bool ok
- 		    = resolver->lookup_resolved_name (segment->get_node_id (),
- 						      &existing);
- 
- 		  if (ok)
- 		    rust_assert (existing == resolved_node);
- 		  else
- 		    resolver->insert_resolved_name (segment->get_node_id (),
- 						    resolved_node);
- 		}
- 	      else if (resolver->get_type_scope ().decl_was_declared_here (
- 			 resolved_node))
- 		{
- 		  resolved_node_id = resolved_node;
- 
- 		  NodeId existing = UNKNOWN_NODEID;
- 		  bool ok
- 		    = resolver->lookup_resolved_type (segment->get_node_id (),
- 						      &existing);
- 
- 		  if (ok)
- 		    rust_assert (existing == resolved_node);
- 		  else
- 		    resolver->insert_resolved_type (segment->get_node_id (),
- 						    resolved_node);
- 		}
- 	      else
- 		{
- 		  rust_error_at (segment->get_locus (),
- 				 "Cannot find path %qs in this scope",
- 				 segment->as_string ().c_str ());
- 		  return false;
- 		}
- 	    }
- 	}
- 
-       bool did_resolve_segment = resolved_node_id != UNKNOWN_NODEID;
-       if (did_resolve_segment)
- 	{
- 	  if (mappings.node_is_module (resolved_node_id)
- 	      || mappings.node_is_crate (resolved_node_id))
- 	    {
- 	      module_scope_id = resolved_node_id;
- 	    }
- 	  previous_resolved_node_id = resolved_node_id;
- 	}
-       else if (is_first_segment)
- 	{
- 	  rust_error_at (segment->get_locus (), ErrorCode::E0412,
- 			 "could not resolve type path %qs",
- 			 segment->get_ident_segment ().as_string ().c_str ());
- 	  return false;
- 	}
-     }
- 
-   if (resolved_node_id != UNKNOWN_NODEID)
-     {
-       // name scope first
-       if (resolver->get_name_scope ().decl_was_declared_here (resolved_node_id))
- 	{
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok
- 	    = resolver->lookup_resolved_name (path.get_node_id (), &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == resolved_node_id);
- 	  else
- 	    resolver->insert_resolved_name (path.get_node_id (),
- 					    resolved_node_id);
- 	}
-       // check the type scope
-       else if (resolver->get_type_scope ().decl_was_declared_here (
- 		 resolved_node_id))
- 	{
- 	  NodeId existing = UNKNOWN_NODEID;
- 	  bool ok
- 	    = resolver->lookup_resolved_type (path.get_node_id (), &existing);
- 
- 	  if (ok)
- 	    rust_assert (existing == resolved_node_id);
- 	  else
- 	    resolver->insert_resolved_type (path.get_node_id (),
- 					    resolved_node_id);
- 	}
-       else
- 	{
- 	  rust_unreachable ();
- 	}
-     }
- 
-   return true;
- }
- 
- // qualified type paths
- 
- ResolveRelativeQualTypePath::ResolveRelativeQualTypePath ()
-   : failure_flag (false)
- {}
- 
- bool
- ResolveRelativeQualTypePath::go (AST::QualifiedPathInType &path)
- {
-   ResolveRelativeQualTypePath o;
- 
-   // resolve the type and trait path
-   auto &qualified_path = path.get_qualified_path_type ();
-   if (!o.resolve_qual_seg (qualified_path))
-     return false;
- 
-   // qualified types are similar to other paths in that we cannot guarantee
-   // that we can resolve the path at name resolution. We must look up
-   // associated types and type information to figure this out properly
- 
-   std::unique_ptr<AST::TypePathSegment> &associated
-     = path.get_associated_segment ();
- 
-   associated->accept_vis (o);
-   if (o.failure_flag)
-     return false;
- 
-   for (auto &seg : path.get_segments ())
-     {
-       seg->accept_vis (o);
-       if (o.failure_flag)
- 	return false;
-     }
- 
-   return true;
- }
- 
- bool
- ResolveRelativeQualTypePath::resolve_qual_seg (AST::QualifiedPathType &seg)
- {
-   if (seg.is_error ())
-     {
-       rust_error_at (seg.get_locus (), "segment has error: %s",
- 		     seg.as_string ().c_str ());
-       return false;
-     }
- 
-   auto &type = seg.get_type ();
-   ResolveType::go (type);
- 
-   if (seg.has_as_clause ())
-     ResolveType::go (seg.get_as_type_path ());
- 
-   return true;
- }
- 
- void
- ResolveRelativeQualTypePath::visit (AST::TypePathSegmentGeneric &seg)
- {
-   if (seg.is_error ())
-     {
-       failure_flag = true;
-       rust_error_at (seg.get_locus (), "segment has error: %s",
- 		     seg.as_string ().c_str ());
-       return;
-     }
- 
-   ResolveGenericArgs::go (seg.get_generic_args ());
- }
- 
- void
- ResolveRelativeQualTypePath::visit (AST::TypePathSegment &seg)
- {
-   if (seg.is_error ())
-     {
-       failure_flag = true;
-       rust_error_at (seg.get_locus (), "segment has error: %s",
- 		     seg.as_string ().c_str ());
-       return;
-     }
- }
- 
- // resolve to canonical path
- 
- bool
- ResolveTypeToCanonicalPath::go (AST::Type &type, CanonicalPath &result)
- {
-   ResolveTypeToCanonicalPath resolver;
-   type.accept_vis (resolver);
-   result = resolver.result;
-   return !resolver.result.is_empty ();
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::TypePath &path)
- {
-   NodeId resolved_node = UNKNOWN_NODEID;
-   if (!resolver->lookup_resolved_name (path.get_node_id (), &resolved_node))
-     {
-       resolver->lookup_resolved_type (path.get_node_id (), &resolved_node);
-     }
- 
-   if (resolved_node == UNKNOWN_NODEID)
-     return;
- 
-   if (auto type_path = mappings.lookup_canonical_path (resolved_node))
-     {
-       auto &final_seg = path.get_segments ().back ();
-       switch (final_seg->get_type ())
- 	{
- 	case AST::TypePathSegment::SegmentType::GENERIC:
- 	  {
- 	    AST::TypePathSegmentGeneric *s
- 	      = static_cast<AST::TypePathSegmentGeneric *> (final_seg.get ());
- 
- 	    std::vector<CanonicalPath> args;
- 	    if (s->has_generic_args ())
- 	      {
- 		ResolveGenericArgs::go (s->get_generic_args ());
- 		for (auto &generic : s->get_generic_args ().get_generic_args ())
- 		  {
- 		    // FIXME: What do we want to do here in case there is a
- 		    // constant or an ambiguous const generic?
- 		    // TODO: At that point, will all generics have been
- 		    // disambiguated? Can we thus canonical resolve types and
- 		    // const and `rust_unreachable` on ambiguous types?
- 		    // This is probably fine as we just want to canonicalize
- 		    // types, right?
- 		    if (generic.get_kind () == AST::GenericArg::Kind::Type)
- 		      {
- 			CanonicalPath arg = CanonicalPath::create_empty ();
- 			bool ok
- 			  = ResolveTypeToCanonicalPath::go (generic.get_type (),
- 							    arg);
- 			if (ok)
- 			  args.push_back (std::move (arg));
- 		      }
- 		  }
- 	      }
- 
- 	    result = *type_path;
- 	    if (!args.empty ())
- 	      {
- 		// append this onto the path
- 		std::string buf;
- 		for (size_t i = 0; i < args.size (); i++)
- 		  {
- 		    bool has_next = (i + 1) < args.size ();
- 		    const auto &arg = args.at (i);
- 
- 		    buf += arg.get ();
- 		    if (has_next)
- 		      buf += ", ";
- 		  }
- 
- 		std::string arg_seg = "<" + buf + ">";
- 		CanonicalPath argument_seg
- 		  = CanonicalPath::new_seg (s->get_node_id (), arg_seg);
- 		result = result.append (argument_seg);
- 	      }
- 	  }
- 	  break;
- 
- 	default:
- 	  result = *type_path;
- 	  break;
- 	}
-     }
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::ReferenceType &type)
- {
-   CanonicalPath path = CanonicalPath::create_empty ();
-   bool ok = ResolveTypeToCanonicalPath::go (type.get_type_referenced (), path);
-   if (ok)
-     {
-       std::string ref_type_str = type.is_mut () ? "mut" : "";
-       std::string ref_path = "&" + ref_type_str + " " + path.get ();
-       result = CanonicalPath::new_seg (type.get_node_id (), ref_path);
-     }
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::RawPointerType &type)
- {
-   CanonicalPath path = CanonicalPath::create_empty ();
-   bool ok = ResolveTypeToCanonicalPath::go (type.get_type_pointed_to (), path);
-   if (ok)
-     {
-       std::string ptr_type_str
- 	= type.get_pointer_type () == AST::RawPointerType::CONST ? "const"
- 								 : "mut";
-       std::string ptr_path = "*" + ptr_type_str + " " + path.get ();
-       result = CanonicalPath::new_seg (type.get_node_id (), ptr_path);
-     }
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::SliceType &type)
- {
-   CanonicalPath path = CanonicalPath::create_empty ();
-   bool ok = ResolveTypeToCanonicalPath::go (type.get_elem_type (), path);
-   if (ok)
-     {
-       std::string slice_path = "[" + path.get () + "]";
-       result = CanonicalPath::new_seg (type.get_node_id (), slice_path);
-     }
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::TraitObjectTypeOneBound &type)
- {
-   CanonicalPath path = CanonicalPath::create_empty ();
-   bool ok
-     = ResolveTypeToCanonicalPath::go (type.get_trait_bound ().get_type_path (),
- 				      path);
-   if (ok)
-     {
-       std::string slice_path = "<dyn " + path.get () + ">";
-       result = CanonicalPath::new_seg (type.get_node_id (), slice_path);
-     }
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::TraitObjectType &type)
- {
-   rust_assert (!type.get_type_param_bounds ().empty ());
- 
-   auto &first_bound = type.get_type_param_bounds ().front ();
- 
-   // Is it allowed or even possible to have a lifetime bound as a first bound?
-   if (first_bound->get_bound_type () == AST::TraitBound::LIFETIME)
-     rust_unreachable ();
- 
-   auto &trait = static_cast<AST::TraitBound &> (*first_bound);
- 
-   CanonicalPath path = CanonicalPath::create_empty ();
-   bool ok = ResolveTypeToCanonicalPath::go (trait.get_type_path (), path);
- 
-   // right?
-   rust_assert (ok);
- 
-   auto slice_path = "<dyn " + path.get ();
- 
-   for (size_t idx = 1; idx < type.get_type_param_bounds ().size (); idx++)
-     {
-       auto &additional_bound = type.get_type_param_bounds ()[idx];
- 
-       std::string str;
- 
-       switch (additional_bound->get_bound_type ())
- 	{
- 	case AST::TypeParamBound::TRAIT:
- 	  {
- 	    auto bound_path = CanonicalPath::create_empty ();
- 
- 	    auto &bound_type_path
- 	      = static_cast<AST::TraitBound &> (*additional_bound)
- 		  .get_type_path ();
- 	    bool ok
- 	      = ResolveTypeToCanonicalPath::go (bound_type_path, bound_path);
- 
- 	    if (!ok)
- 	      continue;
- 
- 	    str = bound_path.get ();
- 	    break;
- 	  }
- 	case AST::TypeParamBound::LIFETIME:
- 	  rust_unreachable ();
- 	  break;
- 	}
-       slice_path += " + " + str;
-     }
- 
-   slice_path += ">";
- 
-   result = CanonicalPath::new_seg (type.get_node_id (), slice_path);
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::NeverType &type)
- {
-   result = CanonicalPath::new_seg (type.get_node_id (), "!");
- }
- 
- void
- ResolveTypeToCanonicalPath::visit (AST::TupleType &type)
- {
-   if (!type.is_unit_type ())
-     rust_unreachable ();
- 
-   result = CanonicalPath::new_seg (type.get_node_id (), "()");
- }
- 
- ResolveTypeToCanonicalPath::ResolveTypeToCanonicalPath ()
-   : ResolverBase (), result (CanonicalPath::create_empty ())
- {}
- 
- bool
- ResolveGenericArgs::is_const_value_name (const CanonicalPath &path)
- {
-   NodeId resolved;
-   auto found = resolver->get_name_scope ().lookup (path, &resolved);
- 
-   return found;
- }
- 
- bool
- ResolveGenericArgs::is_type_name (const CanonicalPath &path)
- {
-   NodeId resolved;
-   auto found = resolver->get_type_scope ().lookup (path, &resolved);
- 
-   return found;
- }
- 
- void
- ResolveGenericArgs::disambiguate (AST::GenericArg &arg)
- {
-   auto path = canonical_prefix.append (
-     CanonicalPath::new_seg (UNKNOWN_NODEID, arg.get_path ()));
- 
-   auto is_type = is_type_name (path);
-   auto is_value = is_const_value_name (path);
- 
-   // In case we cannot find anything, we resolve the ambiguity to a type.
-   // This causes the typechecker to error out properly and when necessary.
-   // But types also take priority over const values in the case of
-   // ambiguities, hence the weird control flow
-   if (is_type || (!is_type && !is_value))
-     arg = arg.disambiguate_to_type ();
-   else if (is_value)
-     arg = arg.disambiguate_to_const ();
- }
- 
- void
- ResolveGenericArgs::resolve_disambiguated_generic (AST::GenericArg &arg)
- {
-   switch (arg.get_kind ())
-     {
-     case AST::GenericArg::Kind::Const:
-       ResolveExpr::go (arg.get_expression (), prefix, canonical_prefix);
-       break;
-     case AST::GenericArg::Kind::Type:
-       ResolveType::go (arg.get_type ());
-       break;
-     default:
-       rust_unreachable ();
-     }
- }
- void
- ResolveGenericArgs::go (AST::GenericArgs &generic_args)
- {
-   auto empty = CanonicalPath::create_empty ();
- 
-   go (generic_args, empty, empty);
- }
- 
- void
- ResolveGenericArgs::go (AST::GenericArgs &generic_args,
- 			const CanonicalPath &prefix,
- 			const CanonicalPath &canonical_prefix)
- {
-   auto resolver = ResolveGenericArgs (prefix, canonical_prefix);
- 
-   for (auto &arg : generic_args.get_generic_args ())
-     {
-       if (arg.get_kind () == AST::GenericArg::Kind::Either)
- 	resolver.disambiguate (arg);
- 
-       resolver.resolve_disambiguated_generic (arg);
-     }
- 
-   for (auto &binding : generic_args.get_binding_args ())
-     {
-       ResolveType::go (binding.get_type ());
-     }
- }
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-type.h gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-type.h
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve-type.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve-type.h	Thu Jan  1 00:00:00 1970
***************
*** 1,280 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_AST_RESOLVE_TYPE_H
- #define RUST_AST_RESOLVE_TYPE_H
- 
- #include "rust-ast-resolve-base.h"
- #include "rust-ast-resolve-expr.h"
- #include "rust-diagnostics.h"
- #include "rust-hir-map.h"
- #include "rust-path.h"
- #include "rust-type.h"
- #include "util/rust-hir-map.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class ResolveRelativeTypePath
- {
- public:
-   static bool go (AST::TypePath &path, NodeId &resolved_node_id);
- };
- 
- class ResolveRelativeQualTypePath : public ResolverBase
- {
-   using ResolverBase::visit;
- 
- public:
-   static bool go (AST::QualifiedPathInType &path);
- 
-   void visit (AST::TypePathSegmentGeneric &seg) override;
- 
-   void visit (AST::TypePathSegment &seg) override;
- 
- protected:
-   bool resolve_qual_seg (AST::QualifiedPathType &seg);
- 
- private:
-   ResolveRelativeQualTypePath ();
- 
-   bool failure_flag;
- };
- 
- class ResolveType : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static NodeId go (AST::Type &type);
- 
-   void visit (AST::BareFunctionType &fntype) override;
-   void visit (AST::TupleType &tuple) override;
-   void visit (AST::TypePath &path) override;
-   void visit (AST::QualifiedPathInType &path) override;
-   void visit (AST::ArrayType &type) override;
-   void visit (AST::ReferenceType &type) override;
-   void visit (AST::InferredType &type) override;
-   void visit (AST::NeverType &type) override;
-   void visit (AST::RawPointerType &type) override;
-   void visit (AST::TraitObjectTypeOneBound &type) override;
-   void visit (AST::TraitObjectType &type) override;
-   void visit (AST::ParenthesisedType &type) override;
-   void visit (AST::SliceType &type) override;
-   void visit (AST::ImplTraitType &type) override;
-   void visit (AST::ImplTraitTypeOneBound &type) override;
- 
- private:
-   ResolveType () : ResolverBase () {}
- };
- 
- class ResolveTypeBound : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static NodeId go (AST::TypeParamBound &type)
-   {
-     ResolveTypeBound resolver;
-     type.accept_vis (resolver);
-     return resolver.resolved_node;
-   };
- 
-   void visit (AST::TraitBound &bound) override
-   {
-     resolved_node = ResolveType::go (bound.get_type_path ());
-   }
- 
- private:
-   ResolveTypeBound () : ResolverBase () {}
- };
- 
- class ResolveGenericParams : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (std::vector<std::unique_ptr<AST::GenericParam>> &params,
- 		  const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix)
-   {
-     ResolveGenericParams resolver (prefix, canonical_prefix);
- 
-     // this needs to be done in two phases as they can be used and defined later
-     // in bounds
-     for (auto &param : params)
-       param->accept_vis (resolver);
- 
-     resolver.first_pass = false;
- 
-     for (auto &param : params)
-       param->accept_vis (resolver);
-   }
- 
-   static void go_single (AST::GenericParam &param, const CanonicalPath &prefix,
- 			 const CanonicalPath &canonical_prefix)
-   {
-     ResolveGenericParams resolver (prefix, canonical_prefix);
- 
-     param.accept_vis (resolver);
-     resolver.first_pass = false;
-     param.accept_vis (resolver);
-   }
- 
-   void visit (AST::ConstGenericParam &param) override
-   {
-     if (first_pass)
-       ResolveType::go (param.get_type ());
-     else if (param.has_default_value ())
-       ResolveExpr::go (param.get_default_value_unchecked ().get_expression (),
- 		       prefix, canonical_prefix);
-   }
- 
-   void visit (AST::TypeParam &param) override
-   {
-     if (first_pass)
-       {
- 	// if it has a type lets resolve it
- 	if (param.has_type ())
- 	  ResolveType::go (param.get_type ());
- 
- 	auto seg = CanonicalPath::new_seg (
- 	  param.get_node_id (), param.get_type_representation ().as_string ());
- 	resolver->get_type_scope ().insert (
- 	  seg, param.get_node_id (), param.get_locus (), false,
- 	  Rib::ItemType::Type,
- 	  [&] (const CanonicalPath &, NodeId, location_t locus) -> void {
- 	    rust_error_at (param.get_locus (),
- 			   "generic param defined multiple times");
- 	    rust_error_at (locus, "was defined here");
- 	  });
- 
- 	mappings.insert_canonical_path (param.get_node_id (), seg);
-       }
-     else if (param.has_type_param_bounds ())
-       {
- 	for (auto &bound : param.get_type_param_bounds ())
- 	  ResolveTypeBound::go (*bound);
-       }
-   }
- 
- private:
-   ResolveGenericParams (const CanonicalPath &prefix,
- 			const CanonicalPath &canonical_prefix)
-     : ResolverBase (), first_pass (true), prefix (prefix),
-       canonical_prefix (canonical_prefix)
-   {}
- 
-   bool first_pass;
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- class ResolveWhereClause : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void Resolve (AST::WhereClause &where_clause)
-   {
-     ResolveWhereClause r;
-     for (auto &clause : where_clause.get_items ())
-       clause->accept_vis (r);
-   }
- 
-   void visit (AST::TypeBoundWhereClauseItem &item) override
-   {
-     ResolveType::go (item.get_type ());
-     if (item.has_type_param_bounds ())
-       {
- 	for (auto &bound : item.get_type_param_bounds ())
- 	  {
- 	    ResolveTypeBound::go (*bound);
- 	  }
-       }
-   }
- 
- private:
-   ResolveWhereClause () : ResolverBase () {}
- };
- 
- class ResolveTypeToCanonicalPath : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static bool go (AST::Type &type, CanonicalPath &result);
- 
-   void visit (AST::TypePath &path) override;
- 
-   void visit (AST::ReferenceType &type) override;
- 
-   void visit (AST::RawPointerType &type) override;
- 
-   void visit (AST::SliceType &type) override;
- 
-   void visit (AST::TraitObjectTypeOneBound &type) override;
- 
-   void visit (AST::TraitObjectType &type) override;
- 
-   void visit (AST::NeverType &type) override;
- 
-   void visit (AST::TupleType &type) override;
- 
- private:
-   ResolveTypeToCanonicalPath ();
- 
-   CanonicalPath result;
- };
- 
- class ResolveGenericArgs : public ResolverBase
- {
-   using Rust::Resolver::ResolverBase::visit;
- 
- public:
-   static void go (AST::GenericArgs &generic_args);
-   static void go (AST::GenericArgs &generic_args, const CanonicalPath &prefix,
- 		  const CanonicalPath &canonical_prefix);
- 
- private:
-   ResolveGenericArgs (const CanonicalPath &prefix,
- 		      const CanonicalPath &canonical_prefix)
-     : ResolverBase (), prefix (prefix), canonical_prefix (canonical_prefix)
-   {}
- 
-   bool is_type_name (const CanonicalPath &path);
-   bool is_const_value_name (const CanonicalPath &path);
- 
-   /**
-    * Resolve a disambiguated generic arg
-    */
-   void disambiguate (AST::GenericArg &arg);
- 
-   /**
-    * Resolve a disambiguated generic arg
-    */
-   void resolve_disambiguated_generic (AST::GenericArg &arg);
- 
-   const CanonicalPath &prefix;
-   const CanonicalPath &canonical_prefix;
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_AST_RESOLVE_TYPE_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve.cc gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-ast-resolve.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-ast-resolve.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,114 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-ast-resolve.h"
- #include "rust-ast-full.h"
- #include "rust-tyty.h"
- #include "rust-ast-resolve-toplevel.h"
- #include "rust-ast-resolve-item.h"
- #include "rust-ast-resolve-expr.h"
- #include "rust-ast-resolve-struct-expr-field.h"
- 
- extern bool saw_errors (void);
- 
- namespace Rust {
- namespace Resolver {
- 
- // NameResolution
- 
- NameResolution *
- NameResolution::get ()
- {
-   static NameResolution *instance;
-   if (instance == nullptr)
-     instance = new NameResolution ();
- 
-   return instance;
- }
- 
- NameResolution::NameResolution ()
-   : resolver (Resolver::get ()), mappings (Analysis::Mappings::get ())
- {
-   // these are global
-   resolver->get_type_scope ().push (mappings.get_next_node_id ());
-   resolver->insert_builtin_types (resolver->get_type_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
- }
- 
- void
- NameResolution::Resolve (AST::Crate &crate)
- {
-   auto resolver = get ();
-   resolver->go (crate);
- }
- 
- void
- NameResolution::go (AST::Crate &crate)
- {
-   // lookup current crate name
-   CrateNum cnum = mappings.get_current_crate ();
- 
-   // Clones the crate name instead of references due to gcc's possibly
-   // dangling references warnings
-   const auto crate_name = mappings.get_crate_name (cnum).value ();
- 
-   // setup the ribs
-   NodeId scope_node_id = crate.get_node_id ();
-   resolver->get_name_scope ().push (scope_node_id);
-   resolver->get_type_scope ().push (scope_node_id);
-   resolver->get_label_scope ().push (scope_node_id);
-   resolver->push_new_name_rib (resolver->get_name_scope ().peek ());
-   resolver->push_new_type_rib (resolver->get_type_scope ().peek ());
-   resolver->push_new_label_rib (resolver->get_label_scope ().peek ());
- 
-   // get the root segment
-   CanonicalPath crate_prefix
-     = CanonicalPath::new_seg (scope_node_id, crate_name);
-   crate_prefix.set_crate_num (cnum);
- 
-   // setup a dummy crate node
-   resolver->get_name_scope ().insert (
-     CanonicalPath::new_seg (crate.get_node_id (), "__$$crate__"),
-     crate.get_node_id (), UNDEF_LOCATION);
- 
-   // setup the root scope
-   resolver->push_new_module_scope (scope_node_id);
- 
-   // first gather the top-level namespace names then we drill down so this
-   // allows for resolving forward declarations since an impl block might have
-   // a Self type Foo which is defined after the impl block for example.
-   for (auto &item : crate.items)
-     ResolveTopLevel::go (*item, CanonicalPath::create_empty (), crate_prefix);
- 
-   // FIXME remove this
-   if (saw_errors ())
-     {
-       resolver->pop_module_scope ();
-       return;
-     }
- 
-   // next we can drill down into the items and their scopes
-   for (auto &item : crate.items)
-     ResolveItem::go (*item, CanonicalPath::create_empty (), crate_prefix);
- 
-   // done
-   resolver->pop_module_scope ();
- }
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver-2.0.cc gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver-2.0.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver-2.0.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver-2.0.cc	Sun Nov  2 22:32:23 2025
*************** Early::finalize_rebind_import (const Ear
*** 438,444 ****
  	// We don't want to insert `self` with `use module::self`
  	if (path.get_final_segment ().is_lower_self_seg ())
  	  {
! 	    rust_assert (segments.size () > 1);
  	    declared_name = segments[segments.size () - 2].as_string ();
  	  }
  	else
--- 438,446 ----
  	// We don't want to insert `self` with `use module::self`
  	if (path.get_final_segment ().is_lower_self_seg ())
  	  {
! 	    // Erroneous `self` or `{self}` use declaration
! 	    if (segments.size () == 1)
! 	      break;
  	    declared_name = segments[segments.size () - 2].as_string ();
  	  }
  	else
*************** Early::finalize_rebind_import (const Ear
*** 447,454 ****
  	break;
        }
      case AST::UseTreeRebind::NewBindType::WILDCARD:
!       rust_unreachable ();
!       break;
      }
  
    for (auto &&definition : data.definitions ())
--- 449,456 ----
  	break;
        }
      case AST::UseTreeRebind::NewBindType::WILDCARD:
!       // We don't want to insert it into the trie
!       return;
      }
  
    for (auto &&definition : data.definitions ())
*************** Early::finalize_rebind_import (const Ear
*** 459,464 ****
--- 461,479 ----
  void
  Early::visit (AST::UseDeclaration &decl)
  {
+   // We do not want to visit the use trees, we're only looking for top level
+   // rebind. eg. `use something;` or `use something::other;`
+   if (decl.get_tree ()->get_kind () == AST::UseTree::Kind::Rebind)
+     {
+       auto &rebind = static_cast<AST::UseTreeRebind &> (*decl.get_tree ());
+       if (rebind.get_path ().get_final_segment ().is_lower_self_seg ())
+ 	{
+ 	  collect_error (
+ 	    Error (decl.get_locus (), ErrorCode::E0429,
+ 		   "%<self%> imports are only allowed within a { } list"));
+ 	}
+     }
+ 
    auto &imports = toplevel.get_imports_to_resolve ();
    auto current_import = imports.find (decl.get_node_id ());
    if (current_import != imports.end ())
*************** Early::visit (AST::UseDeclaration &decl)
*** 484,488 ****
--- 499,529 ----
    DefaultResolver::visit (decl);
  }
  
+ void
+ Early::visit (AST::UseTreeList &use_list)
+ {
+   if (!use_list.has_path ())
+     {
+       for (auto &&tree : use_list.get_trees ())
+ 	{
+ 	  if (tree->get_kind () == AST::UseTree::Kind::Rebind)
+ 	    {
+ 	      auto &rebind = static_cast<AST::UseTreeRebind &> (*tree);
+ 	      auto path_size = rebind.get_path ().get_segments ().size ();
+ 	      if (path_size == 1
+ 		  && rebind.get_path ()
+ 		       .get_final_segment ()
+ 		       .is_lower_self_seg ())
+ 		{
+ 		  collect_error (Error (rebind.get_locus (), ErrorCode::E0431,
+ 					"%<self%> import can only appear in an "
+ 					"import list with a non-empty prefix"));
+ 		}
+ 	    }
+ 	}
+     }
+   DefaultResolver::visit (use_list);
+ }
+ 
  } // namespace Resolver2_0
  } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver-2.0.h gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver-2.0.h
*** gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver-2.0.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver-2.0.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 61,66 ****
--- 61,67 ----
    void visit (AST::Function &) override;
    void visit (AST::StructStruct &) override;
    void visit (AST::UseDeclaration &) override;
+   void visit (AST::UseTreeList &) override;
  
    struct ImportData
    {
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver.cc gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver.cc	Thu Jan  1 00:00:00 1970
***************
*** 1,589 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #include "rust-early-name-resolver.h"
- #include "rust-pattern.h"
- #include "rust-name-resolver.h"
- #include "rust-macro-builtins.h"
- #include "rust-attribute-values.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- // Check if a module contains the `#[macro_use]` attribute
- static bool
- is_macro_use_module (const AST::Module &mod)
- {
-   for (const auto &attr : mod.get_outer_attrs ())
-     if (attr.get_path ().as_string () == Values::Attributes::MACRO_USE)
-       return true;
- 
-   return false;
- }
- 
- std::vector<std::unique_ptr<AST::Item>>
- EarlyNameResolver::accumulate_escaped_macros (AST::Module &module)
- {
-   if (!is_macro_use_module (module))
-     return {};
- 
-   // Parse the module's items if they haven't been expanded and the file
-   // should be parsed (i.e isn't hidden behind an untrue or impossible cfg
-   // directive)
-   if (module.get_kind () == AST::Module::UNLOADED)
-     module.load_items ();
- 
-   std::vector<std::unique_ptr<AST::Item>> escaped_macros;
- 
-   scoped (module.get_node_id (), [&module, &escaped_macros, this] {
-     for (auto &item : module.get_items ())
-       {
- 	if (item->get_item_kind () == AST::Item::Kind::Module)
- 	  {
- 	    auto &module = *static_cast<AST::Module *> (item.get ());
- 	    auto new_macros = accumulate_escaped_macros (module);
- 
- 	    std::move (new_macros.begin (), new_macros.end (),
- 		       std::back_inserter (escaped_macros));
- 
- 	    continue;
- 	  }
- 
- 	if (item->get_item_kind () == AST::Item::Kind::MacroRulesDefinition)
- 	  escaped_macros.emplace_back (item->clone_item ());
-       }
-   });
- 
-   return escaped_macros;
- }
- 
- EarlyNameResolver::EarlyNameResolver ()
-   : current_scope (UNKNOWN_NODEID), resolver (*Resolver::get ()),
-     mappings (Analysis::Mappings::get ())
- {}
- 
- void
- EarlyNameResolver::go (AST::Crate &crate)
- {
-   visit (crate);
- }
- 
- void
- EarlyNameResolver::resolve_generic_args (AST::GenericArgs &generic_args)
- {
-   for (auto &arg : generic_args.get_generic_args ())
-     arg.accept_vis (*this);
- 
-   for (auto &arg : generic_args.get_binding_args ())
-     arg.get_type ().accept_vis (*this);
- }
- 
- void
- EarlyNameResolver::resolve_qualified_path_type (AST::QualifiedPathType &path)
- {
-   path.get_type ().accept_vis (*this);
- 
-   if (path.has_as_clause ())
-     path.get_as_type_path ().accept_vis (*this);
- }
- 
- void
- EarlyNameResolver::visit (AST::Crate &crate)
- {
-   std::vector<std::unique_ptr<AST::Item>> new_items;
-   auto items = crate.take_items ();
- 
-   scoped (crate.get_node_id (), [&items, &new_items, this] {
-     for (auto &&item : items)
-       {
- 	auto new_macros = std::vector<std::unique_ptr<AST::Item>> ();
- 
- 	if (item->get_item_kind () == AST::Item::Kind::Module)
- 	  new_macros = accumulate_escaped_macros (
- 	    *static_cast<AST::Module *> (item.get ()));
- 
- 	new_items.emplace_back (std::move (item));
- 	std::move (new_macros.begin (), new_macros.end (),
- 		   std::back_inserter (new_items));
-       }
-   });
- 
-   crate.set_items (std::move (new_items));
- 
-   scoped (crate.get_node_id (), [&crate, this] () {
-     for (auto &item : crate.items)
-       item->accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::DelimTokenTree &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::AttrInputMetaItemContainer &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::IdentifierExpr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::LifetimeParam &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::ConstGenericParam &)
- {}
- 
- // FIXME: ARTHUR: Do we need to perform macro resolution for paths as well?
- // std::arch::asm!()?
- void
- EarlyNameResolver::visit (AST::PathInExpression &path)
- {
-   if (!path.is_lang_item ())
-     for (auto &segment : path.get_segments ())
-       if (segment.has_generic_args ())
- 	resolve_generic_args (segment.get_generic_args ());
- }
- 
- void
- EarlyNameResolver::visit (AST::TypePathSegmentGeneric &segment)
- {
-   if (segment.has_generic_args ())
-     resolve_generic_args (segment.get_generic_args ());
- }
- 
- void
- EarlyNameResolver::visit (AST::QualifiedPathInExpression &path)
- {
-   resolve_qualified_path_type (path.get_qualified_path_type ());
- 
-   for (auto &segment : path.get_segments ())
-     if (segment.has_generic_args ())
-       resolve_generic_args (segment.get_generic_args ());
- }
- 
- void
- EarlyNameResolver::visit (AST::QualifiedPathInType &path)
- {
-   resolve_qualified_path_type (path.get_qualified_path_type ());
- 
-   for (auto &segment : path.get_segments ())
-     segment->accept_vis (*this);
- }
- 
- void
- EarlyNameResolver::visit (AST::LiteralExpr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::AttrInputLiteral &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::AttrInputMacro &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MetaItemLitExpr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MetaItemPathExpr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::StructExprStruct &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::StructExprFieldIdentifier &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::StructExprStructBase &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::BlockExpr &expr)
- {
-   scoped (expr.get_node_id (), [&expr, this] () {
-     for (auto &stmt : expr.get_statements ())
-       stmt->accept_vis (*this);
- 
-     if (expr.has_tail_expr ())
-       expr.get_tail_expr ().accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::ContinueExpr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::RangeFullExpr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::ForLoopExpr &expr)
- {
-   scoped (expr.get_node_id (), [&expr, this] () {
-     expr.get_pattern ().accept_vis (*this);
-     expr.get_iterator_expr ().accept_vis (*this);
-     expr.get_loop_block ().accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::IfLetExpr &expr)
- {
-   expr.get_value_expr ().accept_vis (*this);
- 
-   scoped (expr.get_node_id (),
- 	  [&expr, this] () { expr.get_if_block ().accept_vis (*this); });
- }
- 
- void
- EarlyNameResolver::visit (AST::MatchExpr &expr)
- {
-   expr.get_scrutinee_expr ().accept_vis (*this);
- 
-   scoped (expr.get_node_id (), [&expr, this] () {
-     for (auto &arm : expr.get_match_cases ())
-       {
- 	scoped (arm.get_node_id (), [&arm, this] () {
- 	  if (arm.get_arm ().has_match_arm_guard ())
- 	    arm.get_arm ().get_guard_expr ().accept_vis (*this);
- 
- 	  for (auto &pattern : arm.get_arm ().get_patterns ())
- 	    pattern->accept_vis (*this);
- 
- 	  arm.get_expr ().accept_vis (*this);
- 	});
-       }
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::LifetimeWhereClauseItem &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::Module &module)
- {
-   if (module.get_kind () == AST::Module::UNLOADED)
-     module.load_items ();
- 
-   // so we need to only go "one scope down" for fetching macros. Macros within
-   // functions are still scoped only within that function. But we have to be
-   // careful because nested modules with #[macro_use] actually works!
-   std::vector<std::unique_ptr<AST::Item>> new_items;
-   auto items = module.take_items ();
- 
-   scoped (module.get_node_id (), [&items, &new_items, this] {
-     for (auto &&item : items)
-       {
- 	auto new_macros = std::vector<std::unique_ptr<AST::Item>> ();
- 
- 	if (item->get_item_kind () == AST::Item::Kind::Module)
- 	  new_macros = accumulate_escaped_macros (
- 	    *static_cast<AST::Module *> (item.get ()));
- 
- 	new_items.emplace_back (std::move (item));
- 	std::move (new_macros.begin (), new_macros.end (),
- 		   std::back_inserter (new_items));
-       }
-   });
- 
-   module.set_items (std::move (new_items));
- 
-   scoped (module.get_node_id (), [&module, this] () {
-     for (auto &item : module.get_items ())
-       item->accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::ExternCrate &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::UseTreeGlob &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::UseTreeList &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::UseTreeRebind &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::UseDeclaration &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::EnumItem &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::Union &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::TraitItemType &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::Trait &trait)
- {
-   // shouldn't need to visit trait.get_implicit_self ()
- 
-   for (auto &generic : trait.get_generic_params ())
-     generic->accept_vis (*this);
- 
-   scoped (trait.get_node_id (), [&trait, this] () {
-     for (auto &item : trait.get_trait_items ())
-       item->accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::InherentImpl &impl)
- {
-   impl.get_type ().accept_vis (*this);
- 
-   for (auto &generic : impl.get_generic_params ())
-     generic->accept_vis (*this);
- 
-   scoped (impl.get_node_id (), [&impl, this] () {
-     for (auto &item : impl.get_impl_items ())
-       item->accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::TraitImpl &impl)
- {
-   impl.get_type ().accept_vis (*this);
- 
-   for (auto &generic : impl.get_generic_params ())
-     generic->accept_vis (*this);
- 
-   scoped (impl.get_node_id (), [&impl, this] () {
-     for (auto &item : impl.get_impl_items ())
-       item->accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::ExternalTypeItem &item)
- {
-   // nothing to do?
- }
- 
- void
- EarlyNameResolver::visit (AST::ExternBlock &block)
- {
-   scoped (block.get_node_id (), [&block, this] () {
-     for (auto &item : block.get_extern_items ())
-       item->accept_vis (*this);
-   });
- }
- 
- void
- EarlyNameResolver::visit (AST::MacroMatchRepetition &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MacroMatcher &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MacroRulesDefinition &rules_def)
- {
-   auto path = CanonicalPath::new_seg (rules_def.get_node_id (),
- 				      rules_def.get_rule_name ().as_string ());
-   resolver.get_macro_scope ().insert (path, rules_def.get_node_id (),
- 				      rules_def.get_locus ());
- 
-   /* Since the EarlyNameResolver runs multiple time (fixed point algorithm)
-    * we could be inserting the same macro def over and over again until we
-    * implement some optimizations */
-   // FIXME: ARTHUR: Remove that lookup and add proper optimizations instead
-   if (mappings.lookup_macro_def (rules_def.get_node_id ()))
-     return;
- 
-   mappings.insert_macro_def (&rules_def);
-   rust_debug_loc (rules_def.get_locus (), "inserting macro def: [%s]",
- 		  path.get ().c_str ());
- }
- 
- void
- EarlyNameResolver::visit (AST::MacroInvocation &invoc)
- {
-   auto &invoc_data = invoc.get_invoc_data ();
-   auto has_semicolon = invoc.has_semicolon ();
- 
-   if (invoc.get_kind () == AST::MacroInvocation::InvocKind::Builtin)
-     for (auto &pending_invoc : invoc.get_pending_eager_invocations ())
-       pending_invoc->accept_vis (*this);
- 
-   // ??
-   // switch on type of macro:
-   //  - '!' syntax macro (inner switch)
-   //      - procedural macro - "A token-based function-like macro"
-   //      - 'macro_rules' (by example/pattern-match) macro? or not? "an
-   // AST-based function-like macro"
-   //      - else is unreachable
-   //  - attribute syntax macro (inner switch)
-   //  - procedural macro attribute syntax - "A token-based attribute
-   // macro"
-   //      - legacy macro attribute syntax? - "an AST-based attribute macro"
-   //      - non-macro attribute: mark known
-   //      - else is unreachable
-   //  - derive macro (inner switch)
-   //      - derive or legacy derive - "token-based" vs "AST-based"
-   //      - else is unreachable
-   //  - derive container macro - unreachable
- 
-   // lookup the rules for this macro
-   NodeId resolved_node = UNKNOWN_NODEID;
-   NodeId source_node = UNKNOWN_NODEID;
-   if (has_semicolon)
-     source_node = invoc.get_macro_node_id ();
-   else
-     source_node = invoc.get_node_id ();
-   auto seg
-     = CanonicalPath::new_seg (source_node, invoc_data.get_path ().as_string ());
- 
-   bool found = resolver.get_macro_scope ().lookup (seg, &resolved_node);
-   if (!found)
-     {
-       rust_error_at (invoc.get_locus (), ErrorCode::E0433,
- 		     "could not resolve macro invocation %qs",
- 		     seg.get ().c_str ());
-       return;
-     }
- 
-   // lookup the rules
-   auto rules_def = mappings.lookup_macro_def (resolved_node);
- 
-   auto &outer_attrs = rules_def.value ()->get_outer_attrs ();
-   bool is_builtin
-     = std::any_of (outer_attrs.begin (), outer_attrs.end (),
- 		   [] (AST::Attribute attr) {
- 		     return attr.get_path ()
- 			    == Values::Attributes::RUSTC_BUILTIN_MACRO;
- 		   });
- 
-   if (is_builtin)
-     {
-       auto builtin_kind = builtin_macro_from_string (
- 	rules_def.value ()->get_rule_name ().as_string ());
-       invoc.map_to_builtin (builtin_kind.value ());
-     }
- 
-   auto attributes = rules_def.value ()->get_outer_attrs ();
- 
-   /* Since the EarlyNameResolver runs multiple time (fixed point algorithm)
-    * we could be inserting the same macro def over and over again until we
-    * implement some optimizations */
-   // FIXME: ARTHUR: Remove that lookup and add proper optimizations instead
-   if (mappings.lookup_macro_invocation (invoc))
-     return;
- 
-   mappings.insert_macro_invocation (invoc, *rules_def);
- }
- 
- // FIXME: ARTHUR: Do we need to resolve these as well here?
- 
- void
- EarlyNameResolver::visit (AST::MetaItemPath &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MetaItemSeq &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MetaNameValueStr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MetaListPaths &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::MetaListNameValueStr &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::RangePatternBoundLiteral &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::RangePatternBoundPath &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::RangePatternBoundQualPath &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::StructPatternFieldIdent &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::StructPattern &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::TupleStructPattern &pattern)
- {
-   pattern.get_items ().accept_vis (*this);
- }
- 
- void
- EarlyNameResolver::visit (AST::TupleType &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::RawPointerType &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::ReferenceType &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::ArrayType &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::SliceType &)
- {}
- 
- void
- EarlyNameResolver::visit (AST::InferredType &)
- {}
- 
- } // namespace Resolver
- } // namespace Rust
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver.h gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver.h
*** gcc-16-20251026/gcc/rust/resolve/rust-early-name-resolver.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-early-name-resolver.h	Thu Jan  1 00:00:00 1970
***************
*** 1,196 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_EARLY_NAME_RESOLVER_H
- #define RUST_EARLY_NAME_RESOLVER_H
- 
- #include "rust-name-resolver.h"
- #include "rust-system.h"
- #include "rust-ast.h"
- #include "rust-ast-visitor.h"
- 
- namespace Rust {
- namespace Resolver {
- 
- class EarlyNameResolver : public AST::DefaultASTVisitor
- {
- public:
-   EarlyNameResolver ();
- 
-   void go (AST::Crate &crate);
- 
- private:
-   using AST::DefaultASTVisitor::visit;
- 
-   /**
-    * Execute a lambda within a scope. This is equivalent to calling
-    * `enter_scope` before your code and `exit_scope` after. This ensures
-    * no errors can be committed
-    */
-   void scoped (NodeId scope_id, std::function<void ()> fn)
-   {
-     auto old_scope = current_scope;
-     current_scope = scope_id;
-     resolver.get_macro_scope ().push (scope_id);
-     resolver.push_new_macro_rib (resolver.get_macro_scope ().peek ());
- 
-     fn ();
- 
-     resolver.get_macro_scope ().pop ();
-     current_scope = old_scope;
-   }
- 
-   /**
-    * Accumulate all of the nested macros which escape their module through the
-    * use of the #[macro_use] attribute.
-    *
-    * This function recursively accumulates macros in all of the nested modules
-    * of an item container (an AST::Crate or an AST::Module) and returns this new
-    * list of items. You can then use the `take_items` and `set_items` functions
-    * on these containers to replace their list of items.
-    */
-   std::vector<std::unique_ptr<AST::Item>>
-   accumulate_escaped_macros (AST::Module &module);
- 
-   /**
-    * The "scope" we are currently in.
-    *
-    * This involves lexical scopes:
-    *
-    * ```rust
-    * // current_scope = crate_id;
-    * macro_rules! foo { () => {} )
-    *
-    * {
-    *     // current_scope = current_block_id;
-    *     macro_rules! foo { () => { something!(); } }
-    * }
-    * // current_scope = crate_id;
-    * ```
-    *
-    * as well as any sort of scope-like structure that might impact import name
-    * resolution or macro name resolution:
-    *
-    * ```rust
-    * macro_rules! foo {
-    *     () => { fn empty() {} }
-    * }
-    *
-    *
-    * trait Foo {
-    *     fn foo() {
-    *         fn inner_foo() {
-    *             macro_rules! foo { () => {} )
-    *
-    *             foo!();
-    *         }
-    *
-    *         foo!();
-    *     }
-    *
-    *     foo!();
-    * }
-    *
-    * foo!();
-    * ```
-    */
-   NodeId current_scope;
- 
-   /* The crate's scope */
-   NodeId crate_scope;
- 
-   Resolver &resolver;
-   Analysis::Mappings &mappings;
- 
-   /**
-    * Early name-resolve generic args, which can be macro invocations
-    */
-   void resolve_generic_args (AST::GenericArgs &generic_args);
- 
-   /**
-    * Early name-resolve a qualified path type, which can contain macro
-    * invocations
-    */
-   void resolve_qualified_path_type (AST::QualifiedPathType &path);
- 
-   virtual void visit (AST::Crate &crate);
-   virtual void visit (AST::DelimTokenTree &delim_tok_tree);
-   virtual void visit (AST::AttrInputMetaItemContainer &input);
-   virtual void visit (AST::IdentifierExpr &ident_expr);
-   virtual void visit (AST::LifetimeParam &lifetime_param);
-   virtual void visit (AST::ConstGenericParam &const_param);
-   virtual void visit (AST::PathInExpression &path);
-   virtual void visit (AST::TypePathSegmentGeneric &segment);
-   virtual void visit (AST::QualifiedPathInExpression &path);
-   virtual void visit (AST::QualifiedPathInType &path);
-   virtual void visit (AST::LiteralExpr &expr);
-   virtual void visit (AST::AttrInputLiteral &attr_input);
-   virtual void visit (AST::AttrInputMacro &attr_input);
-   virtual void visit (AST::MetaItemLitExpr &meta_item);
-   virtual void visit (AST::MetaItemPathExpr &meta_item);
-   virtual void visit (AST::StructExprStruct &expr);
-   virtual void visit (AST::StructExprFieldIdentifier &field);
-   virtual void visit (AST::StructExprStructBase &expr);
-   virtual void visit (AST::BlockExpr &expr);
-   virtual void visit (AST::ContinueExpr &expr);
-   virtual void visit (AST::RangeFullExpr &expr);
-   virtual void visit (AST::ForLoopExpr &expr);
-   virtual void visit (AST::IfLetExpr &expr);
-   virtual void visit (AST::MatchExpr &expr);
-   virtual void visit (AST::LifetimeWhereClauseItem &item);
-   virtual void visit (AST::Module &module);
-   virtual void visit (AST::ExternCrate &crate);
-   virtual void visit (AST::UseTreeGlob &use_tree);
-   virtual void visit (AST::UseTreeList &use_tree);
-   virtual void visit (AST::UseTreeRebind &use_tree);
-   virtual void visit (AST::UseDeclaration &use_decl);
-   virtual void visit (AST::EnumItem &item);
-   virtual void visit (AST::Union &union_item);
-   virtual void visit (AST::TraitItemType &item);
-   virtual void visit (AST::Trait &trait);
-   virtual void visit (AST::InherentImpl &impl);
-   virtual void visit (AST::TraitImpl &impl);
-   virtual void visit (AST::ExternalTypeItem &item);
-   virtual void visit (AST::ExternBlock &block);
-   virtual void visit (AST::MacroMatchRepetition &match);
-   virtual void visit (AST::MacroMatcher &matcher);
-   virtual void visit (AST::MacroRulesDefinition &rules_def);
-   virtual void visit (AST::MacroInvocation &macro_invoc);
-   virtual void visit (AST::MetaItemPath &meta_item);
-   virtual void visit (AST::MetaItemSeq &meta_item);
-   virtual void visit (AST::MetaNameValueStr &meta_item);
-   virtual void visit (AST::MetaListPaths &meta_item);
-   virtual void visit (AST::MetaListNameValueStr &meta_item);
-   virtual void visit (AST::RangePatternBoundLiteral &bound);
-   virtual void visit (AST::RangePatternBoundPath &bound);
-   virtual void visit (AST::RangePatternBoundQualPath &bound);
-   virtual void visit (AST::StructPatternFieldIdent &field);
-   virtual void visit (AST::StructPattern &pattern);
-   virtual void visit (AST::TupleStructPattern &pattern);
-   virtual void visit (AST::TupleType &type);
-   virtual void visit (AST::RawPointerType &type);
-   virtual void visit (AST::ReferenceType &type);
-   virtual void visit (AST::ArrayType &type);
-   virtual void visit (AST::SliceType &type);
-   virtual void visit (AST::InferredType &type);
- };
- 
- } // namespace Resolver
- } // namespace Rust
- 
- #endif // RUST_EARLY_NAME_RESOLVER_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-forever-stack.hxx gcc-16-20251102/gcc/rust/resolve/rust-forever-stack.hxx
*** gcc-16-20251026/gcc/rust/resolve/rust-forever-stack.hxx	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-forever-stack.hxx	Sun Nov  2 22:32:23 2025
*************** ForeverStack<N>::resolve_segments (
*** 531,537 ****
  				       || seg.is_lower_self_seg ()))
  	return tl::nullopt;
  
!       tl::optional<typename ForeverStack<N>::Node &> child = tl::nullopt;
  
        /*
         * On every iteration this loop either
--- 531,537 ----
  				       || seg.is_lower_self_seg ()))
  	return tl::nullopt;
  
!       tl::optional<std::reference_wrapper<Node>> child = tl::nullopt;
  
        /*
         * On every iteration this loop either
*************** ForeverStack<N>::resolve_segments (
*** 583,592 ****
  	      break;
  	    }
  
! 	  if (N == Namespace::Types)
  	    {
! 	      auto rib_lookup = current_node->rib.get (seg.as_string ());
! 	      if (rib_lookup && !rib_lookup->is_ambiguous ())
  		{
  		  insert_segment_resolution (outer_seg,
  					     rib_lookup->get_node_id ());
--- 583,599 ----
  	      break;
  	    }
  
! 	  auto rib_lookup = current_node->rib.get (seg.as_string ());
! 	  if (rib_lookup && !rib_lookup->is_ambiguous ())
  	    {
! 	      if (Analysis::Mappings::get ()
! 		    .lookup_glob_container (rib_lookup->get_node_id ())
! 		    .has_value ())
! 		{
! 		  child = dfs_node (root, rib_lookup->get_node_id ()).value ();
! 		  break;
! 		}
! 	      else
  		{
  		  insert_segment_resolution (outer_seg,
  					     rib_lookup->get_node_id ());
*************** ForeverStack<N>::resolve_segments (
*** 611,619 ****
  	  current_node = &current_node->parent.value ();
  	}
  
!       // if child didn't contain a value
!       // the while loop above should have return'd or kept looping
!       current_node = &child.value ();
        insert_segment_resolution (outer_seg, current_node->id);
      }
  
--- 618,626 ----
  	  current_node = &current_node->parent.value ();
  	}
  
!       // if child didn't point to a value
!       // the while loop above would have returned or kept looping
!       current_node = &child->get ();
        insert_segment_resolution (outer_seg, current_node->id);
      }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-late-name-resolver-2.0.cc gcc-16-20251102/gcc/rust/resolve/rust-late-name-resolver-2.0.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-late-name-resolver-2.0.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-late-name-resolver-2.0.cc	Sun Nov  2 22:32:23 2025
***************
*** 24,29 ****
--- 24,30 ----
  #include "rust-late-name-resolver-2.0.h"
  #include "rust-default-resolver.h"
  #include "rust-name-resolution-context.h"
+ #include "rust-resolve-builtins.h"
  #include "rust-path.h"
  #include "rust-system.h"
  #include "rust-tyty.h"
*************** Late::Late (NameResolutionContext &ctx)
*** 38,121 ****
    : DefaultResolver (ctx), funny_error (false), block_big_self (false)
  {}
  
- static NodeId
- next_node_id ()
- {
-   return Analysis::Mappings::get ().get_next_node_id ();
- };
- 
- static HirId
- next_hir_id ()
- {
-   return Analysis::Mappings::get ().get_next_hir_id ();
- };
- 
- void
- Late::setup_builtin_types ()
- {
-   // access the global type context to setup the TyTys
-   auto &ty_ctx = *Resolver::TypeCheckContext::get ();
- 
-   // Late builtin type struct helper
-   struct LType
-   {
-     std::string name;
-     NodeId node_id;
-     NodeId hir_id;
-     TyTy::BaseType *type;
- 
-     explicit LType (std::string name, TyTy::BaseType *type)
-       : name (name), node_id (next_node_id ()), hir_id (type->get_ref ()),
- 	type (type)
-     {}
-   };
- 
-   static const LType builtins[] = {
-     {LType ("bool", new TyTy::BoolType (next_hir_id ()))},
-     {LType ("u8", new TyTy::UintType (next_hir_id (), TyTy::UintType::U8))},
-     {LType ("u16", new TyTy::UintType (next_hir_id (), TyTy::UintType::U16))},
-     {LType ("u32", new TyTy::UintType (next_hir_id (), TyTy::UintType::U32))},
-     {LType ("u64", new TyTy::UintType (next_hir_id (), TyTy::UintType::U64))},
-     {LType ("u128", new TyTy::UintType (next_hir_id (), TyTy::UintType::U128))},
-     {LType ("i8", new TyTy::IntType (next_hir_id (), TyTy::IntType::I8))},
-     {LType ("i16", new TyTy::IntType (next_hir_id (), TyTy::IntType::I16))},
-     {LType ("i32", new TyTy::IntType (next_hir_id (), TyTy::IntType::I32))},
-     {LType ("i64", new TyTy::IntType (next_hir_id (), TyTy::IntType::I64))},
-     {LType ("i128", new TyTy::IntType (next_hir_id (), TyTy::IntType::I128))},
-     {LType ("f32", new TyTy::FloatType (next_hir_id (), TyTy::FloatType::F32))},
-     {LType ("f64", new TyTy::FloatType (next_hir_id (), TyTy::FloatType::F64))},
-     {LType ("usize", new TyTy::USizeType (next_hir_id ()))},
-     {LType ("isize", new TyTy::ISizeType (next_hir_id ()))},
-     {LType ("char", new TyTy::CharType (next_hir_id ()))},
-     {LType ("str", new TyTy::StrType (next_hir_id ()))},
-     {LType ("!", new TyTy::NeverType (next_hir_id ()))},
- 
-     // the unit type `()` does not play a part in name-resolution - so we only
-     // insert it in the type context...
-   };
- 
-   // There's a special Rib for putting prelude items, since prelude items need
-   // to satisfy certain special rules.
-   ctx.scoped (Rib::Kind::Prelude, 0, [this, &ty_ctx] (void) -> void {
-     for (const auto &builtin : builtins)
-       {
- 	auto ok = ctx.types.insert (builtin.name, builtin.node_id);
- 	rust_assert (ok);
- 
- 	ctx.mappings.insert_node_to_hir (builtin.node_id, builtin.hir_id);
- 	ty_ctx.insert_builtin (builtin.hir_id, builtin.node_id, builtin.type);
-       }
-   });
- 
-   // ...here!
-   auto *unit_type = TyTy::TupleType::get_unit_type ();
-   ty_ctx.insert_builtin (unit_type->get_ref (), next_node_id (), unit_type);
- }
- 
  void
  Late::go (AST::Crate &crate)
  {
!   setup_builtin_types ();
  
    visit (crate);
  }
--- 39,48 ----
    : DefaultResolver (ctx), funny_error (false), block_big_self (false)
  {}
  
  void
  Late::go (AST::Crate &crate)
  {
!   Builtins::setup_type_ctx ();
  
    visit (crate);
  }
*************** Late::visit_impl_type (AST::Type &type)
*** 521,540 ****
    block_big_self = false;
  }
  
! void
! Late::visit (AST::TypePath &type)
  {
    // should we add type path resolution in `ForeverStack` directly? Since it's
    // quite more complicated.
    // maybe we can overload `resolve_path<Namespace::Types>` to only do
    // typepath-like path resolution? that sounds good
  
-   DefaultResolver::visit (type);
- 
    // prevent "impl Self {}" and similar
    if (type.get_segments ().size () == 1
!       && !type.get_segments ().front ()->is_lang_item ()
!       && type.get_segments ().front ()->is_big_self_seg () && block_big_self)
      {
        rust_error_at (type.get_locus (),
  		     "%<Self%> is not valid in the self type of an impl block");
--- 448,469 ----
    block_big_self = false;
  }
  
! template <typename P>
! static void
! resolve_type_path_like (NameResolutionContext &ctx, bool block_big_self,
! 			P &type)
  {
    // should we add type path resolution in `ForeverStack` directly? Since it's
    // quite more complicated.
    // maybe we can overload `resolve_path<Namespace::Types>` to only do
    // typepath-like path resolution? that sounds good
  
    // prevent "impl Self {}" and similar
    if (type.get_segments ().size () == 1
!       && !unwrap_segment_get_lang_item (type.get_segments ().front ())
! 	    .has_value ()
!       && unwrap_type_segment (type.get_segments ().front ()).is_big_self_seg ()
!       && block_big_self)
      {
        rust_error_at (type.get_locus (),
  		     "%<Self%> is not valid in the self type of an impl block");
*************** Late::visit (AST::TypePath &type)
*** 547,563 ****
  
    if (!resolved.has_value ())
      {
!       if (!ctx.lookup (type.get_segments ().front ()->get_node_id ()))
  	rust_error_at (type.get_locus (), ErrorCode::E0412,
  		       "could not resolve type path %qs",
! 		       type.make_debug_string ().c_str ());
        return;
      }
  
    if (resolved->is_ambiguous ())
      {
        rust_error_at (type.get_locus (), ErrorCode::E0659, "%qs is ambiguous",
! 		     type.make_debug_string ().c_str ());
        return;
      }
  
--- 476,492 ----
  
    if (!resolved.has_value ())
      {
!       if (!ctx.lookup (unwrap_segment_node_id (type.get_segments ().front ())))
  	rust_error_at (type.get_locus (), ErrorCode::E0412,
  		       "could not resolve type path %qs",
! 		       unwrap_segment_error_string (type).c_str ());
        return;
      }
  
    if (resolved->is_ambiguous ())
      {
        rust_error_at (type.get_locus (), ErrorCode::E0659, "%qs is ambiguous",
! 		     unwrap_segment_error_string (type).c_str ());
        return;
      }
  
*************** Late::visit (AST::TypePath &type)
*** 574,579 ****
--- 503,516 ----
  }
  
  void
+ Late::visit (AST::TypePath &type)
+ {
+   DefaultResolver::visit (type);
+ 
+   resolve_type_path_like (ctx, block_big_self, type);
+ }
+ 
+ void
  Late::visit (AST::Visibility &vis)
  {
    if (!vis.has_path ())
*************** Late::visit (AST::StructExprStruct &s)
*** 649,658 ****
    visit_inner_attrs (s);
    DefaultResolver::visit (s.get_struct_name ());
  
!   auto resolved = ctx.resolve_path (s.get_struct_name (), Namespace::Types);
! 
!   ctx.map_usage (Usage (s.get_struct_name ().get_node_id ()),
! 		 Definition (resolved->get_node_id ()));
  }
  
  void
--- 586,592 ----
    visit_inner_attrs (s);
    DefaultResolver::visit (s.get_struct_name ());
  
!   resolve_type_path_like (ctx, block_big_self, s.get_struct_name ());
  }
  
  void
*************** Late::visit (AST::StructExprStructBase &
*** 663,672 ****
    DefaultResolver::visit (s.get_struct_name ());
    visit (s.get_struct_base ());
  
!   auto resolved = ctx.resolve_path (s.get_struct_name (), Namespace::Types);
! 
!   ctx.map_usage (Usage (s.get_struct_name ().get_node_id ()),
! 		 Definition (resolved->get_node_id ()));
  }
  
  void
--- 597,603 ----
    DefaultResolver::visit (s.get_struct_name ());
    visit (s.get_struct_base ());
  
!   resolve_type_path_like (ctx, block_big_self, s.get_struct_name ());
  }
  
  void
*************** Late::visit (AST::StructExprStructFields
*** 680,689 ****
    for (auto &field : s.get_fields ())
      visit (field);
  
!   auto resolved = ctx.resolve_path (s.get_struct_name (), Namespace::Types);
! 
!   ctx.map_usage (Usage (s.get_struct_name ().get_node_id ()),
! 		 Definition (resolved->get_node_id ()));
  }
  
  // needed because Late::visit (AST::GenericArg &) is non-virtual
--- 611,617 ----
    for (auto &field : s.get_fields ())
      visit (field);
  
!   resolve_type_path_like (ctx, block_big_self, s.get_struct_name ());
  }
  
  // needed because Late::visit (AST::GenericArg &) is non-virtual
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-late-name-resolver-2.0.h gcc-16-20251102/gcc/rust/resolve/rust-late-name-resolver-2.0.h
*** gcc-16-20251026/gcc/rust/resolve/rust-late-name-resolver-2.0.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/resolve/rust-late-name-resolver-2.0.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 75,83 ****
  private:
    void resolve_label (AST::Lifetime &lifetime);
  
-   /* Setup Rust's builtin types (u8, i32, !...) in the resolver */
-   void setup_builtin_types ();
- 
    bool funny_error;
  
    /* used to prevent "impl Self {}", "impl (Self, i32) {}", etc */
--- 75,80 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-resolve-builtins.cc gcc-16-20251102/gcc/rust/resolve/rust-resolve-builtins.cc
*** gcc-16-20251026/gcc/rust/resolve/rust-resolve-builtins.cc	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/resolve/rust-resolve-builtins.cc	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,125 ----
+ // Copyright (C) 2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "rust-resolve-builtins.h"
+ #include "rust-name-resolution-context.h"
+ #include "rust-tyty.h"
+ #include "rust-hir-type-check.h"
+ 
+ namespace Rust {
+ namespace Resolver2_0 {
+ namespace Builtins {
+ 
+ // Use X-macros
+ 
+ #define TYPE_UINT(n, enum_ident) TYPE1 (n, UintType, UintType::enum_ident)
+ #define TYPE_INT(n, enum_ident) TYPE1 (n, IntType, IntType::enum_ident)
+ 
+ #define BUILTIN_TYPES                                                          \
+   TYPE0 ("bool", BoolType)                                                     \
+   TYPE_UINT ("u8", U8)                                                         \
+   TYPE_UINT ("u16", U16)                                                       \
+   TYPE_UINT ("u32", U32)                                                       \
+   TYPE_UINT ("u64", U64)                                                       \
+   TYPE_UINT ("u128", U128)                                                     \
+   TYPE_INT ("i8", I8)                                                          \
+   TYPE_INT ("i16", I16)                                                        \
+   TYPE_INT ("i32", I32)                                                        \
+   TYPE_INT ("i64", I64)                                                        \
+   TYPE_INT ("i128", I128)                                                      \
+   TYPE1 ("f32", FloatType, FloatType::F32)                                     \
+   TYPE1 ("f64", FloatType, FloatType::F64)                                     \
+   TYPE0 ("usize", USizeType)                                                   \
+   TYPE0 ("isize", ISizeType)                                                   \
+   TYPE0 ("char", CharType)                                                     \
+   TYPE0 ("str", StrType)                                                       \
+   TYPE0 ("!", NeverType)
+ 
+ // Define constants using X macros
+ 
+ #define TYPE0(...) 1 +
+ #define TYPE1(...) 1 +
+ static constexpr size_t builtin_count = BUILTIN_TYPES 0;
+ #undef TYPE0
+ #undef TYPE1
+ 
+ #define TYPE0(n, ...) n,
+ #define TYPE1(n, ...) n,
+ static constexpr const char *builtin_names[] = {BUILTIN_TYPES};
+ #undef TYPE0
+ #undef TYPE1
+ 
+ static NodeId builtin_node_ids[builtin_count];
+ 
+ void
+ setup_lang_prelude (NameResolutionContext &ctx)
+ {
+   auto &mappings = Analysis::Mappings::get ();
+ 
+   // insert into prelude rib
+   ctx.scoped (Rib::Kind::Prelude, 0, [&mappings, &ctx] (void) -> void {
+     for (size_t i = 0; i < builtin_count; i++)
+       {
+ 	NodeId node_id = mappings.get_next_node_id ();
+ 	rust_assert (ctx.types.insert (Identifier (builtin_names[i]), node_id));
+ 	builtin_node_ids[i] = node_id;
+       }
+   });
+ }
+ 
+ void
+ setup_type_ctx ()
+ {
+   auto &mappings = Analysis::Mappings::get ();
+   auto &ty_ctx = *Resolver::TypeCheckContext::get ();
+ 
+   HirId hir_ids[builtin_count];
+   for (size_t i = 0; i < builtin_count; i++)
+     hir_ids[i] = mappings.get_next_hir_id ();
+ 
+   TyTy::BaseType *types[builtin_count];
+   {
+     size_t i = 0;
+ #define TYPE_BASE(stub)                                                        \
+   types[i] = new TyTy::stub;                                                   \
+   i++;
+ #define TYPE0(n, ty) TYPE_BASE (ty (hir_ids[i]))
+ #define TYPE1(n, ty, p1) TYPE_BASE (ty (hir_ids[i], TyTy::p1))
+     BUILTIN_TYPES
+ #undef TYPE_BASE
+ #undef TYPE0
+ #undef TYPE1
+   }
+ 
+   for (size_t i = 0; i < builtin_count; i++)
+     {
+       NodeId node_id = builtin_node_ids[i];
+       HirId hir_id = hir_ids[i];
+       mappings.insert_node_to_hir (node_id, hir_id);
+       ty_ctx.insert_builtin (hir_id, node_id, types[i]);
+     }
+ 
+   // handle unit type separately
+   auto *unit_type = TyTy::TupleType::get_unit_type ();
+   ty_ctx.insert_builtin (unit_type->get_ref (), mappings.get_next_node_id (),
+ 			 unit_type);
+ }
+ 
+ } // namespace Builtins
+ } // namespace Resolver2_0
+ } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/rust/resolve/rust-resolve-builtins.h gcc-16-20251102/gcc/rust/resolve/rust-resolve-builtins.h
*** gcc-16-20251026/gcc/rust/resolve/rust-resolve-builtins.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/rust/resolve/rust-resolve-builtins.h	Sun Nov  2 22:32:23 2025
***************
*** 0 ****
--- 1,37 ----
+ // Copyright (C) 2025 Free Software Foundation, Inc.
+ 
+ // This file is part of GCC.
+ 
+ // GCC is free software; you can redistribute it and/or modify it under
+ // the terms of the GNU General Public License as published by the Free
+ // Software Foundation; either version 3, or (at your option) any later
+ // version.
+ 
+ // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+ // WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ // for more details.
+ 
+ // You should have received a copy of the GNU General Public License
+ // along with GCC; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+ #ifndef RUST_RESOLVE_BUILTINS_H
+ #define RUST_RESOLVE_BUILTINS_H
+ 
+ namespace Rust {
+ namespace Resolver2_0 {
+ 
+ // forward declare
+ class NameResolutionContext;
+ 
+ namespace Builtins {
+ 
+ void setup_lang_prelude (NameResolutionContext &ctx);
+ void setup_type_ctx ();
+ 
+ } // namespace Builtins
+ } // namespace Resolver2_0
+ } // namespace Rust
+ 
+ #endif // RUST_RESOLVE_BUILTINS_H
diff -Nrcpad gcc-16-20251026/gcc/rust/rust-gcc.cc gcc-16-20251102/gcc/rust/rust-gcc.cc
*** gcc-16-20251026/gcc/rust/rust-gcc.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/rust-gcc.cc	Sun Nov  2 22:32:23 2025
*************** constructor_expression (tree type_tree,
*** 1258,1264 ****
      return error_mark_node;
  
    vec<constructor_elt, va_gc> *init;
!   vec_alloc (init, vals.size ());
  
    tree sink = NULL_TREE;
    bool is_constant = true;
--- 1258,1264 ----
      return error_mark_node;
  
    vec<constructor_elt, va_gc> *init;
!   vec_alloc (init, union_index != -1 ? 1 : vals.size ());
  
    tree sink = NULL_TREE;
    bool is_constant = true;
diff -Nrcpad gcc-16-20251026/gcc/rust/rust-lang.cc gcc-16-20251102/gcc/rust/rust-lang.cc
*** gcc-16-20251026/gcc/rust/rust-lang.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/rust-lang.cc	Sun Nov  2 22:32:23 2025
***************
*** 34,40 ****
  #include "selftest.h"
  #include "rust-cfg-parser.h"
  #include "rust-privacy-ctx.h"
- #include "rust-ast-resolve-item.h"
  #include "rust-lex.h"
  #include "optional.h"
  #include "rust-unicode.h"
--- 34,39 ----
*************** run_rust_tests ()
*** 442,448 ****
    rust_cfg_parser_test ();
    rust_privacy_ctx_test ();
    rust_crate_name_validation_test ();
-   rust_simple_path_resolve_test ();
  }
  } // namespace selftest
  
--- 441,446 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/rust-session-manager.cc gcc-16-20251102/gcc/rust/rust-session-manager.cc
*** gcc-16-20251026/gcc/rust/rust-session-manager.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/rust-session-manager.cc	Sun Nov  2 22:32:23 2025
***************
*** 29,35 ****
  #include "rust-lex.h"
  #include "rust-parse.h"
  #include "rust-macro-expand.h"
- #include "rust-ast-resolve.h"
  #include "rust-ast-lower.h"
  #include "rust-hir-type-check.h"
  #include "rust-privacy-check.h"
--- 29,34 ----
***************
*** 46,55 ****
  #include "rust-imports.h"
  #include "rust-extern-crate.h"
  #include "rust-attributes.h"
- #include "rust-early-name-resolver.h"
  #include "rust-name-resolution-context.h"
  #include "rust-early-name-resolver-2.0.h"
  #include "rust-late-name-resolver-2.0.h"
  #include "rust-cfg-strip.h"
  #include "rust-expand-visitor.h"
  #include "rust-unicode.h"
--- 45,54 ----
  #include "rust-imports.h"
  #include "rust-extern-crate.h"
  #include "rust-attributes.h"
  #include "rust-name-resolution-context.h"
  #include "rust-early-name-resolver-2.0.h"
  #include "rust-late-name-resolver-2.0.h"
+ #include "rust-resolve-builtins.h"
  #include "rust-cfg-strip.h"
  #include "rust-expand-visitor.h"
  #include "rust-unicode.h"
*************** Session::handle_crate_name (const char *
*** 422,453 ****
      {
        if (attr.get_path () != "crate_name")
  	continue;
!       if (!attr.has_attr_input ())
  	{
  	  rust_error_at (attr.get_locus (),
! 			 "%<crate_name%> accepts one argument");
  	  continue;
  	}
  
!       auto &literal
! 	= static_cast<AST::AttrInputLiteral &> (attr.get_attr_input ());
!       const auto &msg_str = literal.get_literal ().as_string ();
!       if (!validate_crate_name (msg_str, error))
  	{
  	  error.locus = attr.get_locus ();
  	  error.emit ();
  	  continue;
  	}
  
!       if (options.crate_name_set_manually && (options.crate_name != msg_str))
  	{
  	  rust_error_at (attr.get_locus (),
  			 "%<-frust-crate-name%> and %<#[crate_name]%> are "
  			 "required to match, but %qs does not match %qs",
! 			 options.crate_name.c_str (), msg_str.c_str ());
  	}
        crate_name_found = true;
!       options.set_crate_name (msg_str);
      }
  
    options.crate_name_set_manually |= crate_name_found;
--- 421,451 ----
      {
        if (attr.get_path () != "crate_name")
  	continue;
! 
!       auto msg_str = Analysis::Attributes::extract_string_literal (attr);
!       if (!msg_str.has_value ())
  	{
  	  rust_error_at (attr.get_locus (),
! 			 "malformed %<crate_name%> attribute input");
  	  continue;
  	}
  
!       if (!validate_crate_name (*msg_str, error))
  	{
  	  error.locus = attr.get_locus ();
  	  error.emit ();
  	  continue;
  	}
  
!       if (options.crate_name_set_manually && (options.crate_name != *msg_str))
  	{
  	  rust_error_at (attr.get_locus (),
  			 "%<-frust-crate-name%> and %<#[crate_name]%> are "
  			 "required to match, but %qs does not match %qs",
! 			 options.crate_name.c_str (), msg_str->c_str ());
  	}
        crate_name_found = true;
!       options.set_crate_name (*msg_str);
      }
  
    options.crate_name_set_manually |= crate_name_found;
*************** Session::compile_crate (const char *file
*** 551,560 ****
    handle_crate_name (filename, *ast_crate.get ());
  
    // dump options except lexer dump
-   if (options.dump_option_enabled (CompileOptions::AST_DUMP_PRETTY))
-     {
-       dump_ast_pretty (*ast_crate.get ());
-     }
    if (options.dump_option_enabled (CompileOptions::TARGET_OPTION_DUMP))
      {
        options.target_data.dump_target_options ();
--- 549,554 ----
*************** Session::compile_crate (const char *file
*** 563,568 ****
--- 557,567 ----
    if (saw_errors ())
      return;
  
+   if (options.dump_option_enabled (CompileOptions::AST_DUMP_PRETTY))
+     {
+       dump_ast_pretty (*ast_crate.get ());
+     }
+ 
    // setup the mappings for this AST
    CrateNum current_crate = mappings.get_current_crate ();
    AST::Crate &parsed_crate
*************** Session::compile_crate (const char *file
*** 613,625 ****
    if (last_step == CompileOptions::CompileStep::Expansion)
      return;
  
-   AST::CollectLangItems ().go (parsed_crate);
- 
    auto name_resolution_ctx = Resolver2_0::NameResolutionContext ();
    // expansion pipeline stage
  
    expansion (parsed_crate, name_resolution_ctx);
  
    rust_debug ("\033[0;31mSUCCESSFULLY FINISHED EXPANSION \033[0m");
    if (options.dump_option_enabled (CompileOptions::EXPANSION_DUMP))
      {
--- 612,624 ----
    if (last_step == CompileOptions::CompileStep::Expansion)
      return;
  
    auto name_resolution_ctx = Resolver2_0::NameResolutionContext ();
    // expansion pipeline stage
  
    expansion (parsed_crate, name_resolution_ctx);
  
+   AST::CollectLangItems ().go (parsed_crate);
+ 
    rust_debug ("\033[0;31mSUCCESSFULLY FINISHED EXPANSION \033[0m");
    if (options.dump_option_enabled (CompileOptions::EXPANSION_DUMP))
      {
*************** Session::compile_crate (const char *file
*** 644,653 ****
      return;
  
    // resolution pipeline stage
!   if (flag_name_resolution_2_0)
!     Resolver2_0::Late (name_resolution_ctx).go (parsed_crate);
!   else
!     Resolver::NameResolution::Resolve (parsed_crate);
  
    if (options.dump_option_enabled (CompileOptions::RESOLUTION_DUMP))
      dump_name_resolution (name_resolution_ctx);
--- 643,649 ----
      return;
  
    // resolution pipeline stage
!   Resolver2_0::Late (name_resolution_ctx).go (parsed_crate);
  
    if (options.dump_option_enabled (CompileOptions::RESOLUTION_DUMP))
      dump_name_resolution (name_resolution_ctx);
*************** Session::compile_crate (const char *file
*** 738,744 ****
        // lints
        Analysis::ScanDeadcode::Scan (hir);
        Analysis::UnusedVariables::Lint (*ctx);
!       Analysis::ReadonlyCheck::Lint (*ctx);
  
        // metadata
        bool specified_emit_metadata
--- 734,740 ----
        // lints
        Analysis::ScanDeadcode::Scan (hir);
        Analysis::UnusedVariables::Lint (*ctx);
!       HIR::ReadonlyChecker ().go (hir);
  
        // metadata
        bool specified_emit_metadata
*************** Session::compile_crate (const char *file
*** 758,763 ****
--- 754,762 ----
  	}
      }
  
+   if (saw_errors ())
+     return;
+ 
    // pass to GCC middle-end
    ctx->write_to_backend ();
  }
*************** Session::expansion (AST::Crate &crate, R
*** 937,964 ****
    MacroExpander expander (crate, cfg, *this);
    std::vector<Error> macro_errors;
  
    while (!fixed_point_reached && iterations < cfg.recursion_limit)
      {
!       CfgStrip ().go (crate);
        // Errors might happen during cfg strip pass
-       bool visitor_dirty = false;
  
!       if (flag_name_resolution_2_0)
! 	{
! 	  Resolver2_0::Early early (ctx);
! 	  early.go (crate);
! 	  macro_errors = early.get_macro_resolve_errors ();
! 	  visitor_dirty = early.is_dirty ();
! 	}
!       else
! 	Resolver::EarlyNameResolver ().go (crate);
  
        if (saw_errors ())
  	break;
  
        ExpandVisitor (expander).go (crate);
  
!       fixed_point_reached = !expander.has_changed () && !visitor_dirty;
        expander.reset_changed_state ();
        iterations++;
  
--- 936,958 ----
    MacroExpander expander (crate, cfg, *this);
    std::vector<Error> macro_errors;
  
+   Resolver2_0::Builtins::setup_lang_prelude (ctx);
+ 
    while (!fixed_point_reached && iterations < cfg.recursion_limit)
      {
!       CfgStrip (cfg).go (crate);
        // Errors might happen during cfg strip pass
  
!       Resolver2_0::Early early (ctx);
!       early.go (crate);
!       macro_errors = early.get_macro_resolve_errors ();
  
        if (saw_errors ())
  	break;
  
        ExpandVisitor (expander).go (crate);
  
!       fixed_point_reached = !expander.has_changed () && !early.is_dirty ();
        expander.reset_changed_state ();
        iterations++;
  
*************** Session::expansion (AST::Crate &crate, R
*** 993,1000 ****
        // HACK: we may need a final TopLevel pass
        // however, this should not count towards the recursion limit
        // and we don't need a full Early pass
!       if (flag_name_resolution_2_0)
! 	Resolver2_0::TopLevel (ctx).go (crate);
      }
  
    // error reporting - check unused macros, get missing fragment specifiers
--- 987,993 ----
        // HACK: we may need a final TopLevel pass
        // however, this should not count towards the recursion limit
        // and we don't need a full Early pass
!       Resolver2_0::TopLevel (ctx).go (crate);
      }
  
    // error reporting - check unused macros, get missing fragment specifiers
*************** Session::load_extern_crate (const std::s
*** 1190,1203 ****
    mappings.insert_bang_proc_macros (crate_num, bang_macros);
    mappings.insert_derive_proc_macros (crate_num, derive_macros);
  
-   // if flag_name_resolution_2_0 is enabled
-   // then we perform resolution later
-   if (!flag_name_resolution_2_0)
-     {
-       // name resolve it
-       Resolver::NameResolution::Resolve (parsed_crate);
-     }
- 
    // always restore the crate_num
    mappings.set_current_crate (saved_crate_num);
  
--- 1183,1188 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-autoderef.cc gcc-16-20251102/gcc/rust/typecheck/rust-autoderef.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-autoderef.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-autoderef.cc	Sun Nov  2 22:32:23 2025
*************** AutoderefCycle::try_autoderefed (TyTy::B
*** 425,432 ****
    TyTy::ReferenceType *r1
      = new TyTy::ReferenceType (r->get_ref (), TyTy::TyVar (r->get_ref ()),
  			       Mutability::Imm);
!   adjustments.push_back (
!     Adjustment (Adjustment::AdjustmentType::IMM_REF, r, r1));
    if (select (*r1))
      return true;
  
--- 425,431 ----
    TyTy::ReferenceType *r1
      = new TyTy::ReferenceType (r->get_ref (), TyTy::TyVar (r->get_ref ()),
  			       Mutability::Imm);
!   adjustments.emplace_back (Adjustment::AdjustmentType::IMM_REF, r, r1);
    if (select (*r1))
      return true;
  
*************** AutoderefCycle::try_autoderefed (TyTy::B
*** 436,443 ****
    TyTy::ReferenceType *r2
      = new TyTy::ReferenceType (r->get_ref (), TyTy::TyVar (r->get_ref ()),
  			       Mutability::Mut);
!   adjustments.push_back (
!     Adjustment (Adjustment::AdjustmentType::MUT_REF, r, r2));
    if (select (*r2))
      return true;
  
--- 435,441 ----
    TyTy::ReferenceType *r2
      = new TyTy::ReferenceType (r->get_ref (), TyTy::TyVar (r->get_ref ()),
  			       Mutability::Mut);
!   adjustments.emplace_back (Adjustment::AdjustmentType::MUT_REF, r, r2);
    if (select (*r2))
      return true;
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-casts.cc gcc-16-20251102/gcc/rust/typecheck/rust-casts.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-casts.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-casts.cc	Sun Nov  2 22:32:23 2025
*************** TypeCastRules::cast_rules ()
*** 277,282 ****
--- 277,283 ----
        break;
  
      case TyTy::TypeKind::REF:
+     case TyTy::TypeKind::FNPTR:
      case TyTy::TypeKind::POINTER:
        switch (to.get_ty ()->get_kind ())
  	{
*************** TypeCastRules::cast_rules ()
*** 286,293 ****
  	case TyTy::TypeKind::INT:
  	  {
  	    // refs should not cast to numeric type
! 	    bool from_ptr
! 	      = from.get_ty ()->get_kind () == TyTy::TypeKind::POINTER;
  	    if (from_ptr)
  	      {
  		return TypeCoercionRules::CoercionResult{
--- 287,295 ----
  	case TyTy::TypeKind::INT:
  	  {
  	    // refs should not cast to numeric type
! 	    auto kind = from.get_ty ()->get_kind ();
! 	    bool from_ptr = kind == TyTy::TypeKind::POINTER
! 			    || kind == TyTy::TypeKind::FNPTR;
  	    if (from_ptr)
  	      {
  		return TypeCoercionRules::CoercionResult{
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-coercion.cc gcc-16-20251102/gcc/rust/typecheck/rust-coercion.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-coercion.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-coercion.cc	Sun Nov  2 22:32:23 2025
*************** TypeCoercionRules::do_coercion (TyTy::Ba
*** 61,120 ****
    // see:
    // https://github.com/rust-lang/rust/blob/7eac88abb2e57e752f3302f02be5f3ce3d7adfb4/compiler/rustc_typeck/src/check/coercion.rs
  
-   // handle never
-   // https://github.com/rust-lang/rust/blob/7eac88abb2e57e752f3302f02be5f3ce3d7adfb4/compiler/rustc_typeck/src/check/coercion.rs#L155
    if (receiver->get_kind () == TyTy::TypeKind::NEVER)
      {
!       // Subtle: If we are coercing from `!` to `?T`, where `?T` is an unbound
!       // type variable, we want `?T` to fallback to `!` if not
!       // otherwise constrained. An example where this arises:
!       //
!       //     let _: Option<?T> = Some({ return; });
!       //
!       // here, we would coerce from `!` to `?T`.
!       if (expected->has_substitutions_defined () && !expected->is_concrete ())
! 	{
! 	  location_t locus = mappings.lookup_location (receiver->get_ref ());
! 	  TyTy::TyVar implicit_var
! 	    = TyTy::TyVar::get_implicit_infer_var (locus);
! 	  try_result = CoercionResult{{}, implicit_var.get_tyty ()};
! 	  return true;
! 	}
!       else
! 	{
! 	  bool expected_is_infer_var
! 	    = expected->get_kind () == TyTy::TypeKind::INFER;
! 	  bool expected_is_general_infer_var
! 	    = expected_is_infer_var
! 	      && (static_cast<TyTy::InferType *> (expected)->get_infer_kind ()
! 		  == TyTy::InferType::InferTypeKind::GENERAL);
! 
! 	  // FIXME this 'expected_is_general_infer_var' case needs to eventually
! 	  // should go away see: compile/never_type_err1.rs
! 	  //
! 	  // I think we need inference obligations to say that yes we have a
! 	  // general inference variable but we add the oligation to the expected
! 	  // type that it could default to '!'
! 	  if (expected_is_general_infer_var)
! 	    try_result = CoercionResult{{}, receiver};
! 	  else
! 	    try_result = CoercionResult{{}, expected->clone ()};
! 
! 	  return true;
! 	}
      }
  
    // unsize
!   bool unsafe_error = false;
!   CoercionResult unsize_coercion
!     = coerce_unsized (receiver, expected, unsafe_error);
!   bool valid_unsize_coercion = !unsize_coercion.is_error ();
!   if (valid_unsize_coercion)
      {
!       try_result = unsize_coercion;
        return true;
      }
!   else if (unsafe_error)
      {
        // location_t lhs = mappings.lookup_location (receiver->get_ref ());
        // location_t rhs = mappings.lookup_location (expected->get_ref ());
--- 61,81 ----
    // see:
    // https://github.com/rust-lang/rust/blob/7eac88abb2e57e752f3302f02be5f3ce3d7adfb4/compiler/rustc_typeck/src/check/coercion.rs
  
    if (receiver->get_kind () == TyTy::TypeKind::NEVER)
      {
!       try_result = coerce_never (receiver);
!       return true;
      }
  
    // unsize
!   tl::expected<CoercionResult, CoerceUnsizedError> unsize_coercion
!     = coerce_unsized (receiver, expected);
!   if (unsize_coercion)
      {
!       try_result = unsize_coercion.value ();
        return true;
      }
!   else if (unsize_coercion.error () == CoerceUnsizedError::Unsafe)
      {
        // location_t lhs = mappings.lookup_location (receiver->get_ref ());
        // location_t rhs = mappings.lookup_location (expected->get_ref ());
*************** TypeCoercionRules::do_coercion (TyTy::Ba
*** 127,141 ****
      {
      case TyTy::TypeKind::POINTER:
        {
! 	TyTy::PointerType *ptr = static_cast<TyTy::PointerType *> (expected);
  	try_result = coerce_unsafe_ptr (receiver, ptr, ptr->mutability ());
  	return !try_result.is_error ();
        }
  
      case TyTy::TypeKind::REF:
        {
! 	TyTy::ReferenceType *ptr
! 	  = static_cast<TyTy::ReferenceType *> (expected);
  	try_result
  	  = coerce_borrowed_pointer (receiver, ptr, ptr->mutability ());
  	return !try_result.is_error ();
--- 88,101 ----
      {
      case TyTy::TypeKind::POINTER:
        {
! 	auto *ptr = expected->as<TyTy::PointerType> ();
  	try_result = coerce_unsafe_ptr (receiver, ptr, ptr->mutability ());
  	return !try_result.is_error ();
        }
  
      case TyTy::TypeKind::REF:
        {
! 	auto *ptr = expected->as<TyTy::ReferenceType> ();
  	try_result
  	  = coerce_borrowed_pointer (receiver, ptr, ptr->mutability ());
  	return !try_result.is_error ();
*************** TypeCoercionRules::do_coercion (TyTy::Ba
*** 174,179 ****
--- 134,177 ----
  }
  
  TypeCoercionRules::CoercionResult
+ TypeCoercionRules::coerce_never (TyTy::BaseType *receiver)
+ {
+   // handle never
+   // https://github.com/rust-lang/rust/blob/7eac88abb2e57e752f3302f02be5f3ce3d7adfb4/compiler/rustc_typeck/src/check/coercion.rs#L155
+ 
+   // Subtle: If we are coercing from `!` to `?T`, where `?T` is an unbound
+   // type variable, we want `?T` to fallback to `!` if not
+   // otherwise constrained. An example where this arises:
+   //
+   //     let _: Option<?T> = Some({ return; });
+   //
+   // here, we would coerce from `!` to `?T`.
+   if (expected->has_substitutions_defined () && !expected->is_concrete ())
+     {
+       location_t locus = mappings.lookup_location (receiver->get_ref ());
+       TyTy::TyVar implicit_var = TyTy::TyVar::get_implicit_infer_var (locus);
+       return CoercionResult{{}, implicit_var.get_tyty ()};
+     }
+ 
+   bool expected_is_infer_var = expected->get_kind () == TyTy::TypeKind::INFER;
+   bool expected_is_general_infer_var
+     = expected_is_infer_var
+       && (static_cast<TyTy::InferType *> (expected)->get_infer_kind ()
+ 	  == TyTy::InferType::InferTypeKind::GENERAL);
+ 
+   // FIXME this 'expected_is_general_infer_var' case needs to eventually
+   // should go away see: compile/never_type_err1.rs
+   //
+   // I think we need inference obligations to say that yes we have a
+   // general inference variable but we add the oligation to the expected
+   // type that it could default to '!'
+   if (expected_is_general_infer_var)
+     return CoercionResult{{}, receiver};
+   else
+     return CoercionResult{{}, expected->clone ()};
+ }
+ 
+ TypeCoercionRules::CoercionResult
  TypeCoercionRules::coerce_unsafe_ptr (TyTy::BaseType *receiver,
  				      TyTy::PointerType *expected,
  				      Mutability to_mutbl)
*************** TypeCoercionRules::coerce_borrowed_point
*** 273,284 ****
      {
      case TyTy::TypeKind::REF:
        {
! 	TyTy::ReferenceType *from
! 	  = static_cast<TyTy::ReferenceType *> (receiver);
! 	from_mutbl = from->mutability ();
        }
        break;
- 
      default:
        {
  	rust_debug ("coerce_borrowed_pointer -- unify");
--- 271,279 ----
      {
      case TyTy::TypeKind::REF:
        {
! 	from_mutbl = receiver->as<TyTy::ReferenceType> ()->mutability ();
        }
        break;
      default:
        {
  	rust_debug ("coerce_borrowed_pointer -- unify");
*************** TypeCoercionRules::coerce_borrowed_point
*** 318,326 ****
  // &[T; n] or &mut [T; n] -> &[T]
  // or &mut [T; n] -> &mut [T]
  // or &Concrete -> &Trait, etc.
! TypeCoercionRules::CoercionResult
  TypeCoercionRules::coerce_unsized (TyTy::BaseType *source,
! 				   TyTy::BaseType *target, bool &unsafe_error)
  {
    rust_debug ("coerce_unsized(source={%s}, target={%s})",
  	      source->debug_str ().c_str (), target->debug_str ().c_str ());
--- 313,322 ----
  // &[T; n] or &mut [T; n] -> &[T]
  // or &mut [T; n] -> &mut [T]
  // or &Concrete -> &Trait, etc.
! tl::expected<TypeCoercionRules::CoercionResult,
! 	     TypeCoercionRules::CoerceUnsizedError>
  TypeCoercionRules::coerce_unsized (TyTy::BaseType *source,
! 				   TyTy::BaseType *target)
  {
    rust_debug ("coerce_unsized(source={%s}, target={%s})",
  	      source->debug_str ().c_str (), target->debug_str ().c_str ());
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 344,354 ****
        Mutability to_mutbl = target_ref->mutability ();
        if (!coerceable_mutability (from_mutbl, to_mutbl))
  	{
- 	  unsafe_error = true;
  	  location_t lhs = mappings.lookup_location (source->get_ref ());
  	  location_t rhs = mappings.lookup_location (target->get_ref ());
  	  mismatched_mutability_error (locus, lhs, rhs);
! 	  return TypeCoercionRules::CoercionResult::get_error ();
  	}
  
        ty_a = source_ref->get_base ();
--- 340,350 ----
        Mutability to_mutbl = target_ref->mutability ();
        if (!coerceable_mutability (from_mutbl, to_mutbl))
  	{
  	  location_t lhs = mappings.lookup_location (source->get_ref ());
  	  location_t rhs = mappings.lookup_location (target->get_ref ());
  	  mismatched_mutability_error (locus, lhs, rhs);
! 	  return tl::unexpected<CoerceUnsizedError> (
! 	    CoerceUnsizedError::Unsafe);
  	}
  
        ty_a = source_ref->get_base ();
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 356,363 ****
        needs_reborrow = true;
        expected_mutability = to_mutbl;
  
!       adjustments.push_back (
! 	Adjustment (Adjustment::AdjustmentType::INDIRECTION, source_ref, ty_a));
      }
    else if (source_is_ref && target_is_ptr)
      {
--- 352,359 ----
        needs_reborrow = true;
        expected_mutability = to_mutbl;
  
!       adjustments.emplace_back (Adjustment::AdjustmentType::INDIRECTION,
! 				source_ref, ty_a);
      }
    else if (source_is_ref && target_is_ptr)
      {
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 369,379 ****
        Mutability to_mutbl = target_ref->mutability ();
        if (!coerceable_mutability (from_mutbl, to_mutbl))
  	{
- 	  unsafe_error = true;
  	  location_t lhs = mappings.lookup_location (source->get_ref ());
  	  location_t rhs = mappings.lookup_location (target->get_ref ());
  	  mismatched_mutability_error (locus, lhs, rhs);
! 	  return TypeCoercionRules::CoercionResult::get_error ();
  	}
  
        ty_a = source_ref->get_base ();
--- 365,375 ----
        Mutability to_mutbl = target_ref->mutability ();
        if (!coerceable_mutability (from_mutbl, to_mutbl))
  	{
  	  location_t lhs = mappings.lookup_location (source->get_ref ());
  	  location_t rhs = mappings.lookup_location (target->get_ref ());
  	  mismatched_mutability_error (locus, lhs, rhs);
! 	  return tl::unexpected<CoerceUnsizedError> (
! 	    CoerceUnsizedError::Unsafe);
  	}
  
        ty_a = source_ref->get_base ();
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 381,388 ****
        needs_reborrow = true;
        expected_mutability = to_mutbl;
  
!       adjustments.push_back (
! 	Adjustment (Adjustment::AdjustmentType::INDIRECTION, source_ref, ty_a));
      }
  
    // FIXME
--- 377,384 ----
        needs_reborrow = true;
        expected_mutability = to_mutbl;
  
!       adjustments.emplace_back (Adjustment::AdjustmentType::INDIRECTION,
! 				source_ref, ty_a);
      }
  
    // FIXME
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 401,417 ****
      {
        bool bounds_compatible = b->bounds_compatible (*a, locus, false);
        if (!bounds_compatible)
! 	{
! 	  unsafe_error = true;
! 	  return TypeCoercionRules::CoercionResult::get_error ();
! 	}
  
        // return the unsize coercion
        TyTy::BaseType *result = b->clone ();
        // result->set_ref (a->get_ref ());
  
        // append a dyn coercion adjustment
!       adjustments.push_back (Adjustment (Adjustment::UNSIZE, a, result));
  
        // reborrow if needed
        if (needs_reborrow)
--- 397,410 ----
      {
        bool bounds_compatible = b->bounds_compatible (*a, locus, false);
        if (!bounds_compatible)
! 	return tl::unexpected<CoerceUnsizedError> (CoerceUnsizedError::Unsafe);
  
        // return the unsize coercion
        TyTy::BaseType *result = b->clone ();
        // result->set_ref (a->get_ref ());
  
        // append a dyn coercion adjustment
!       adjustments.emplace_back (Adjustment::UNSIZE, a, result);
  
        // reborrow if needed
        if (needs_reborrow)
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 424,430 ****
  	  Adjustment::AdjustmentType borrow_type
  	    = expected_mutability == Mutability::Imm ? Adjustment::IMM_REF
  						     : Adjustment::MUT_REF;
! 	  adjustments.push_back (Adjustment (borrow_type, result, reborrow));
  	  result = reborrow;
  	}
  
--- 417,423 ----
  	  Adjustment::AdjustmentType borrow_type
  	    = expected_mutability == Mutability::Imm ? Adjustment::IMM_REF
  						     : Adjustment::MUT_REF;
! 	  adjustments.emplace_back (borrow_type, result, reborrow);
  	  result = reborrow;
  	}
  
*************** TypeCoercionRules::coerce_unsized (TyTy:
*** 432,438 ****
      }
  
    adjustments.clear ();
!   return TypeCoercionRules::CoercionResult::get_error ();
  }
  
  bool
--- 425,431 ----
      }
  
    adjustments.clear ();
!   return tl::unexpected<CoerceUnsizedError> (CoerceUnsizedError::Regular);
  }
  
  bool
*************** TypeCoercionRules::select (TyTy::BaseTyp
*** 446,452 ****
      = unify_site_and (autoderefed.get_ref (), TyTy::TyWithLocation (expected),
  		      TyTy::TyWithLocation (&autoderefed),
  		      UNDEF_LOCATION /* locus */, false /*emit_errors*/,
! 		      false /*commit_if_ok*/, true /*infer*/, true /*cleanup*/);
    bool ok = result->get_kind () != TyTy::TypeKind::ERROR;
    if (!ok)
      return false;
--- 439,446 ----
      = unify_site_and (autoderefed.get_ref (), TyTy::TyWithLocation (expected),
  		      TyTy::TyWithLocation (&autoderefed),
  		      UNDEF_LOCATION /* locus */, false /*emit_errors*/,
! 		      !try_flag /*commit_if_ok*/, try_flag /*infer*/,
! 		      try_flag /*cleanup*/);
    bool ok = result->get_kind () != TyTy::TypeKind::ERROR;
    if (!ok)
      return false;
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-coercion.h gcc-16-20251102/gcc/rust/typecheck/rust-coercion.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-coercion.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-coercion.h	Sun Nov  2 22:32:23 2025
***************
*** 21,26 ****
--- 21,27 ----
  
  #include "rust-autoderef.h"
  #include "rust-hir-type-check.h"
+ #include "expected.h"
  
  namespace Rust {
  namespace Resolver {
*************** namespace Resolver {
*** 28,33 ****
--- 29,40 ----
  class TypeCoercionRules : protected AutoderefCycle
  {
  public:
+   enum class CoerceUnsizedError
+   {
+     Regular,
+     Unsafe
+   };
+ 
    struct CoercionResult
    {
      std::vector<Adjustment> adjustments;
*************** public:
*** 51,56 ****
--- 58,64 ----
  				   bool allow_autoderef,
  				   bool is_cast_site = false);
  
+   CoercionResult coerce_never (TyTy::BaseType *receiver);
    CoercionResult coerce_unsafe_ptr (TyTy::BaseType *receiver,
  				    TyTy::PointerType *expected,
  				    Mutability mutability);
*************** public:
*** 59,66 ****
  					  TyTy::ReferenceType *expected,
  					  Mutability mutability);
  
!   CoercionResult coerce_unsized (TyTy::BaseType *receiver,
! 				 TyTy::BaseType *expected, bool &unsafe_error);
  
    static bool coerceable_mutability (Mutability from_mutbl,
  				     Mutability to_mutbl);
--- 67,74 ----
  					  TyTy::ReferenceType *expected,
  					  Mutability mutability);
  
!   tl::expected<CoercionResult, CoerceUnsizedError>
!   coerce_unsized (TyTy::BaseType *receiver, TyTy::BaseType *expected);
  
    static bool coerceable_mutability (Mutability from_mutbl,
  				     Mutability to_mutbl);
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-dot-operator.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-dot-operator.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-dot-operator.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-dot-operator.cc	Sun Nov  2 22:32:23 2025
*************** MethodResolver::Select (std::set<MethodC
*** 51,56 ****
--- 51,59 ----
      {
        TyTy::BaseType *candidate_type = candidate.candidate.ty;
        rust_assert (candidate_type->get_kind () == TyTy::TypeKind::FNDEF);
+       if (candidate_type == nullptr
+ 	  || candidate_type->get_kind () != TyTy::TypeKind::FNDEF)
+ 	continue;
        TyTy::FnType &fn = *static_cast<TyTy::FnType *> (candidate_type);
  
        // match the number of arguments
*************** MethodResolver::assemble_inherent_impl_c
*** 136,146 ****
        TyTy::BaseType *ty = nullptr;
        if (!query_type (func->get_mappings ().get_hirid (), &ty))
  	return true;
!       rust_assert (ty != nullptr);
!       if (ty->get_kind () == TyTy::TypeKind::ERROR)
  	return true;
  
-       rust_assert (ty->get_kind () == TyTy::TypeKind::FNDEF);
        TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
        const TyTy::BaseType *impl_self
  	= TypeCheckItem::ResolveImplBlockSelf (*impl);
--- 139,149 ----
        TyTy::BaseType *ty = nullptr;
        if (!query_type (func->get_mappings ().get_hirid (), &ty))
  	return true;
!       if (ty == nullptr || ty->get_kind () == TyTy::TypeKind::ERROR)
! 	return true;
!       if (ty->get_kind () != TyTy::TypeKind::FNDEF)
  	return true;
  
        TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
        const TyTy::BaseType *impl_self
  	= TypeCheckItem::ResolveImplBlockSelf (*impl);
*************** MethodResolver::assemble_inherent_impl_c
*** 175,181 ****
  	    return true;
  	}
  
!       inherent_impl_fns.push_back ({func, impl, fnty});
  
        return true;
      });
--- 178,184 ----
  	    return true;
  	}
  
!       inherent_impl_fns.emplace_back (func, impl, fnty);
  
        return true;
      });
*************** MethodResolver::assemble_trait_impl_cand
*** 220,229 ****
  	TyTy::BaseType *ty = nullptr;
  	if (!query_type (func->get_mappings ().get_hirid (), &ty))
  	  continue;
! 	if (ty->get_kind () == TyTy::TypeKind::ERROR)
  	  continue;
  
- 	rust_assert (ty->get_kind () == TyTy::TypeKind::FNDEF);
  	TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
  	const TyTy::BaseType *impl_self
  	  = TypeCheckItem::ResolveImplBlockSelf (*impl);
--- 223,233 ----
  	TyTy::BaseType *ty = nullptr;
  	if (!query_type (func->get_mappings ().get_hirid (), &ty))
  	  continue;
! 	if (ty == nullptr || ty->get_kind () == TyTy::TypeKind::ERROR)
! 	  continue;
! 	if (ty->get_kind () != TyTy::TypeKind::FNDEF)
  	  continue;
  
  	TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
  	const TyTy::BaseType *impl_self
  	  = TypeCheckItem::ResolveImplBlockSelf (*impl);
*************** MethodResolver::assemble_trait_impl_cand
*** 259,265 ****
  	      continue;
  	  }
  
! 	impl_candidates.push_back ({func, impl, fnty});
  	return true;
        }
  
--- 263,269 ----
  	      continue;
  	  }
  
! 	impl_candidates.emplace_back (func, impl, fnty);
  	return true;
        }
  
*************** MethodResolver::assemble_trait_impl_cand
*** 282,292 ****
        return true;
  
      TyTy::BaseType *ty = item_ref->get_tyty ();
!     rust_assert (ty->get_kind () == TyTy::TypeKind::FNDEF);
      TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
  
!     trait_item_candidate candidate{func, trait, fnty, trait_ref, item_ref};
!     trait_candidates.push_back (candidate);
  
      return true;
    });
--- 286,296 ----
        return true;
  
      TyTy::BaseType *ty = item_ref->get_tyty ();
!     if (ty == nullptr || ty->get_kind () != TyTy::TypeKind::FNDEF)
!       return true;
      TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
  
!     trait_candidates.emplace_back (func, trait, fnty, trait_ref, item_ref);
  
      return true;
    });
*************** MethodResolver::try_select_predicate_can
*** 299,305 ****
    for (const auto &predicate : predicate_items)
      {
        const TyTy::FnType *fn = predicate.fntype;
!       rust_assert (fn->is_method ());
  
        TyTy::BaseType *fn_self = fn->get_self_type ();
        rust_debug ("dot-operator predicate fn_self={%s} can_eq receiver={%s}",
--- 303,310 ----
    for (const auto &predicate : predicate_items)
      {
        const TyTy::FnType *fn = predicate.fntype;
!       if (!fn->is_method ())
! 	continue;
  
        TyTy::BaseType *fn_self = fn->get_self_type ();
        rust_debug ("dot-operator predicate fn_self={%s} can_eq receiver={%s}",
*************** MethodResolver::try_select_inherent_impl
*** 346,352 ****
  	continue;
  
        TyTy::FnType *fn = impl_item.ty;
!       rust_assert (fn->is_method ());
  
        TyTy::BaseType *fn_self = fn->get_self_type ();
  
--- 351,358 ----
  	continue;
  
        TyTy::FnType *fn = impl_item.ty;
!       if (!fn->is_method ())
! 	continue;
  
        TyTy::BaseType *fn_self = fn->get_self_type ();
  
*************** MethodResolver::try_select_trait_impl_ca
*** 384,390 ****
    for (auto trait_item : candidates)
      {
        TyTy::FnType *fn = trait_item.ty;
!       rust_assert (fn->is_method ());
  
        TyTy::BaseType *fn_self = fn->get_self_type ();
        rust_debug ("dot-operator trait_item fn_self={%s} can_eq receiver={%s}",
--- 390,397 ----
    for (auto trait_item : candidates)
      {
        TyTy::FnType *fn = trait_item.ty;
!       if (!fn->is_method ())
! 	continue;
  
        TyTy::BaseType *fn_self = fn->get_self_type ();
        rust_debug ("dot-operator trait_item fn_self={%s} can_eq receiver={%s}",
*************** MethodResolver::get_predicate_items (
*** 464,483 ****
    std::vector<predicate_candidate> predicate_items;
    for (auto &bound : specified_bounds)
      {
!       TyTy::TypeBoundPredicateItem lookup
  	= bound.lookup_associated_item (segment_name.as_string ());
!       if (lookup.is_error ())
  	continue;
  
!       TyTy::BaseType *ty = lookup.get_tyty_for_receiver (&receiver);
        if (ty->get_kind () == TyTy::TypeKind::FNDEF)
  	{
  	  TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
  	  if (fnty->is_method ())
! 	    {
! 	      predicate_candidate candidate{lookup, fnty};
! 	      predicate_items.push_back (candidate);
! 	    }
  	}
      }
  
--- 471,487 ----
    std::vector<predicate_candidate> predicate_items;
    for (auto &bound : specified_bounds)
      {
!       tl::optional<TyTy::TypeBoundPredicateItem> lookup
  	= bound.lookup_associated_item (segment_name.as_string ());
!       if (!lookup.has_value ())
  	continue;
  
!       TyTy::BaseType *ty = lookup->get_tyty_for_receiver (&receiver);
        if (ty->get_kind () == TyTy::TypeKind::FNDEF)
  	{
  	  TyTy::FnType *fnty = static_cast<TyTy::FnType *> (ty);
  	  if (fnty->is_method ())
! 	    predicate_items.emplace_back (lookup.value (), fnty);
  	}
      }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-dot-operator.h gcc-16-20251102/gcc/rust/typecheck/rust-hir-dot-operator.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-dot-operator.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-dot-operator.h	Sun Nov  2 22:32:23 2025
*************** class MethodResolver : private TypeCheck
*** 49,54 ****
--- 49,58 ----
  public:
    struct predicate_candidate
    {
+     predicate_candidate (TyTy::TypeBoundPredicateItem lookup,
+ 			 TyTy::FnType *fntype)
+       : lookup (lookup), fntype (fntype)
+     {}
      TyTy::TypeBoundPredicateItem lookup;
      TyTy::FnType *fntype;
    };
*************** public:
*** 67,72 ****
--- 71,81 ----
  
    struct impl_item_candidate
    {
+     impl_item_candidate (HIR::Function *item, HIR::ImplBlock *impl_block,
+ 			 TyTy::FnType *ty)
+       : item (item), impl_block (impl_block), ty (ty)
+     {}
+ 
      HIR::Function *item;
      HIR::ImplBlock *impl_block;
      TyTy::FnType *ty;
*************** public:
*** 74,79 ****
--- 83,95 ----
  
    struct trait_item_candidate
    {
+     trait_item_candidate (const HIR::TraitItemFunc *item,
+ 			  const HIR::Trait *trait, TyTy::FnType *ty,
+ 			  const TraitReference *reference,
+ 			  const TraitItemReference *item_ref)
+       : item (item), trait (trait), ty (ty), reference (reference),
+ 	item_ref (item_ref)
+     {}
      const HIR::TraitItemFunc *item;
      const HIR::Trait *trait;
      TyTy::FnType *ty;
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-path-probe.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-path-probe.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-path-probe.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-path-probe.cc	Sun Nov  2 22:32:23 2025
*************** PathProbeType::process_impl_item_candida
*** 302,312 ****
    if (!query_type (impl_ty_id, &impl_block_ty))
      return;
  
!   if (!receiver->can_eq (impl_block_ty, false))
!     {
!       if (!impl_block_ty->can_eq (receiver, false))
! 	return;
!     }
  
    // lets visit the impl_item
    item->accept_vis (*this);
--- 302,311 ----
    if (!query_type (impl_ty_id, &impl_block_ty))
      return;
  
!   if (!types_compatable (TyTy::TyWithLocation (receiver),
! 			 TyTy::TyWithLocation (impl_block_ty),
! 			 impl->get_locus (), false))
!     return;
  
    // lets visit the impl_item
    item->accept_vis (*this);
*************** PathProbeType::process_predicate_for_can
*** 367,381 ****
  {
    const TraitReference *trait_ref = predicate.get ();
  
!   TyTy::TypeBoundPredicateItem item
      = predicate.lookup_associated_item (search.as_string ());
!   if (item.is_error ())
      return;
  
!   if (ignore_mandatory_trait_items && item.needs_implementation ())
      return;
  
!   const TraitItemReference *trait_item_ref = item.get_raw_item ();
    PathProbeCandidate::CandidateType candidate_type;
    switch (trait_item_ref->get_trait_item_type ())
      {
--- 366,380 ----
  {
    const TraitReference *trait_ref = predicate.get ();
  
!   tl::optional<TyTy::TypeBoundPredicateItem> item
      = predicate.lookup_associated_item (search.as_string ());
!   if (!item.has_value ())
      return;
  
!   if (ignore_mandatory_trait_items && item->needs_implementation ())
      return;
  
!   const TraitItemReference *trait_item_ref = item->get_raw_item ();
    PathProbeCandidate::CandidateType candidate_type;
    switch (trait_item_ref->get_trait_item_type ())
      {
*************** PathProbeType::process_predicate_for_can
*** 395,403 ****
        break;
      }
  
!   TyTy::BaseType *trait_item_tyty = item.get_raw_item ()->get_tyty ();
    if (receiver->get_kind () != TyTy::DYNAMIC)
!     trait_item_tyty = item.get_tyty_for_receiver (receiver);
  
    PathProbeCandidate::TraitItemCandidate trait_item_candidate{trait_ref,
  							      trait_item_ref,
--- 394,402 ----
        break;
      }
  
!   TyTy::BaseType *trait_item_tyty = item->get_raw_item ()->get_tyty ();
    if (receiver->get_kind () != TyTy::DYNAMIC)
!     trait_item_tyty = item->get_tyty_for_receiver (receiver);
  
    PathProbeCandidate::TraitItemCandidate trait_item_candidate{trait_ref,
  							      trait_item_ref,
*************** PathProbeType::union_bounds (
*** 425,434 ****
      }
  
    std::vector<std::pair<const TraitReference *, HIR::ImplBlock *>> union_set;
    for (auto it = mapper.begin (); it != mapper.end (); it++)
!     {
!       union_set.push_back ({it->second.first, it->second.second});
!     }
    return union_set;
  }
  
--- 424,433 ----
      }
  
    std::vector<std::pair<const TraitReference *, HIR::ImplBlock *>> union_set;
+ 
    for (auto it = mapper.begin (); it != mapper.end (); it++)
!     union_set.emplace_back (it->second.first, it->second.second);
! 
    return union_set;
  }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-trait-resolve.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-trait-resolve.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-trait-resolve.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-trait-resolve.cc	Sun Nov  2 22:32:23 2025
*************** TraitResolver::resolve_trait (HIR::Trait
*** 224,231 ****
  						  apply_sized);
  
  	    context->insert_type (generic_param->get_mappings (), param_type);
! 	    substitutions.push_back (
! 	      TyTy::SubstitutionParamMapping (typaram, param_type));
  
  	    if (is_self)
  	      {
--- 224,230 ----
  						  apply_sized);
  
  	    context->insert_type (generic_param->get_mappings (), param_type);
! 	    substitutions.emplace_back (typaram, param_type);
  
  	    if (is_self)
  	      {
*************** TraitResolver::resolve_trait (HIR::Trait
*** 247,263 ****
  
    // copy the substitition mappings
    std::vector<TyTy::SubstitutionParamMapping> self_subst_copy;
    for (auto &sub : substitutions)
      self_subst_copy.push_back (sub.clone ());
  
    // They also inherit themselves as a bound this enables a trait item to
    // reference other Self::trait_items
!   auto self_hrtb
!     = TyTy::TypeBoundPredicate (trait_reference->get_mappings ().get_defid (),
! 				std::move (self_subst_copy),
! 				BoundPolarity::RegularBound,
! 				trait_reference->get_locus ());
!   specified_bounds.push_back (self_hrtb);
  
    // look for any
    std::vector<TyTy::TypeBoundPredicate> super_traits;
--- 246,262 ----
  
    // copy the substitition mappings
    std::vector<TyTy::SubstitutionParamMapping> self_subst_copy;
+   self_subst_copy.reserve (substitutions.size ());
+ 
    for (auto &sub : substitutions)
      self_subst_copy.push_back (sub.clone ());
  
    // They also inherit themselves as a bound this enables a trait item to
    // reference other Self::trait_items
!   specified_bounds.emplace_back (trait_reference->get_mappings ().get_defid (),
! 				 std::move (self_subst_copy),
! 				 BoundPolarity::RegularBound,
! 				 trait_reference->get_locus ());
  
    // look for any
    std::vector<TyTy::TypeBoundPredicate> super_traits;
*************** TraitResolver::resolve_trait (HIR::Trait
*** 291,296 ****
--- 290,297 ----
      {
        // make a copy of the substs
        std::vector<TyTy::SubstitutionParamMapping> item_subst;
+       item_subst.reserve (substitutions.size ());
+ 
        for (auto &sub : substitutions)
  	item_subst.push_back (sub.clone ());
  
*************** AssociatedImplTrait::setup_associated_ty
*** 553,561 ****
  	      generic_param->get_mappings ().get_hirid (), &l);
  	    if (ok && l->get_kind () == TyTy::TypeKind::PARAM)
  	      {
! 		substitutions.push_back (TyTy::SubstitutionParamMapping (
! 		  static_cast<HIR::TypeParam &> (*generic_param),
! 		  static_cast<TyTy::ParamType *> (l)));
  	      }
  	  }
  	  break;
--- 554,562 ----
  	      generic_param->get_mappings ().get_hirid (), &l);
  	    if (ok && l->get_kind () == TyTy::TypeKind::PARAM)
  	      {
! 		substitutions.emplace_back (static_cast<HIR::TypeParam &> (
! 					      *generic_param),
! 					    static_cast<TyTy::ParamType *> (l));
  	      }
  	  }
  	  break;
*************** AssociatedImplTrait::setup_associated_ty
*** 579,592 ****
        if (p.needs_substitution () && infer)
  	{
  	  TyTy::TyVar infer_var = TyTy::TyVar::get_implicit_infer_var (locus);
! 	  subst_args.push_back (
! 	    TyTy::SubstitutionArg (&p, infer_var.get_tyty ()));
  	}
        else
  	{
  	  auto param = p.get_param_ty ();
  	  auto resolved = param->destructure ();
! 	  subst_args.push_back (TyTy::SubstitutionArg (&p, resolved));
  	  param_mappings[param->get_symbol ()] = resolved->get_ref ();
  	}
      }
--- 580,592 ----
        if (p.needs_substitution () && infer)
  	{
  	  TyTy::TyVar infer_var = TyTy::TyVar::get_implicit_infer_var (locus);
! 	  subst_args.emplace_back (&p, infer_var.get_tyty ());
  	}
        else
  	{
  	  auto param = p.get_param_ty ();
  	  auto resolved = param->destructure ();
! 	  subst_args.emplace_back (&p, resolved);
  	  param_mappings[param->get_symbol ()] = resolved->get_ref ();
  	}
      }
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-bounds.h gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-bounds.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-bounds.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-bounds.h	Sun Nov  2 22:32:23 2025
*************** class TypeBoundsProbe : public TypeCheck
*** 30,36 ****
  {
  public:
    static std::vector<std::pair<TraitReference *, HIR::ImplBlock *>>
!   Probe (const TyTy::BaseType *receiver);
  
    static bool is_bound_satisfied_for_type (TyTy::BaseType *receiver,
  					   TraitReference *ref);
--- 30,36 ----
  {
  public:
    static std::vector<std::pair<TraitReference *, HIR::ImplBlock *>>
!   Probe (TyTy::BaseType *receiver);
  
    static bool is_bound_satisfied_for_type (TyTy::BaseType *receiver,
  					   TraitReference *ref);
*************** private:
*** 46,54 ****
    void assemble_builtin_candidate (LangItem::Kind item);
  
  private:
!   TypeBoundsProbe (const TyTy::BaseType *receiver);
  
!   const TyTy::BaseType *receiver;
    std::vector<std::pair<TraitReference *, HIR::ImplBlock *>> trait_references;
  };
  
--- 46,54 ----
    void assemble_builtin_candidate (LangItem::Kind item);
  
  private:
!   TypeBoundsProbe (TyTy::BaseType *receiver);
  
!   TyTy::BaseType *receiver;
    std::vector<std::pair<TraitReference *, HIR::ImplBlock *>> trait_references;
  };
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-base.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-base.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-base.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-base.cc	Sun Nov  2 22:32:23 2025
*************** walk_types_to_constrain (std::set<HirId>
*** 56,62 ****
--- 56,64 ----
        if (arg != nullptr)
  	{
  	  const auto p = arg->get_root ();
+ 	  constrained_symbols.insert (p->get_ref ());
  	  constrained_symbols.insert (p->get_ty_ref ());
+ 
  	  if (p->has_substitutions_defined ())
  	    {
  	      walk_types_to_constrain (constrained_symbols,
*************** walk_types_to_constrain (std::set<HirId>
*** 66,71 ****
--- 68,150 ----
      }
  }
  
+ static void
+ walk_type_to_constrain (std::set<HirId> &constrained_symbols, TyTy::BaseType &r)
+ {
+   switch (r.get_kind ())
+     {
+     case TyTy::TypeKind::POINTER:
+       {
+ 	auto &p = static_cast<TyTy::PointerType &> (r);
+ 	walk_type_to_constrain (constrained_symbols, *p.get_base ());
+       }
+       break;
+     case TyTy::TypeKind::REF:
+       {
+ 	auto &ref = static_cast<TyTy::ReferenceType &> (r);
+ 	walk_type_to_constrain (constrained_symbols, *ref.get_base ());
+       }
+       break;
+     case TyTy::TypeKind::ARRAY:
+       {
+ 	auto &arr = static_cast<TyTy::ArrayType &> (r);
+ 	walk_type_to_constrain (constrained_symbols, *arr.get_element_type ());
+       }
+       break;
+     case TyTy::TypeKind::FNDEF:
+       {
+ 	auto &fn = static_cast<TyTy::FnType &> (r);
+ 	for (auto &param : fn.get_params ())
+ 	  walk_type_to_constrain (constrained_symbols, *param.get_type ());
+ 	walk_type_to_constrain (constrained_symbols, *fn.get_return_type ());
+       }
+       break;
+     case TyTy::TypeKind::PARAM:
+       {
+ 	auto &param = static_cast<TyTy::ParamType &> (r);
+ 	constrained_symbols.insert (param.get_ty_ref ());
+       }
+       break;
+     case TyTy::SLICE:
+       {
+ 	auto &slice = static_cast<TyTy::SliceType &> (r);
+ 	walk_type_to_constrain (constrained_symbols,
+ 				*slice.get_element_type ());
+       }
+       break;
+     case TyTy::FNPTR:
+       {
+ 	auto &ptr = static_cast<TyTy::FnPtr &> (r);
+ 	for (auto &param : ptr.get_params ())
+ 	  walk_type_to_constrain (constrained_symbols, *param.get_tyty ());
+ 	walk_type_to_constrain (constrained_symbols, *ptr.get_return_type ());
+       }
+       break;
+     case TyTy::TUPLE:
+       {
+ 	auto &tuple = static_cast<TyTy::TupleType &> (r);
+ 	for (auto &ty : tuple.get_fields ())
+ 	  walk_type_to_constrain (constrained_symbols, *ty.get_tyty ());
+       }
+       break;
+     case TyTy::DYNAMIC:
+       {
+ 	auto &dyn = static_cast<TyTy::DynamicObjectType &> (r);
+ 	constrained_symbols.insert (dyn.get_ty_ref ());
+       }
+       break;
+     case TyTy::CLOSURE:
+       {
+ 	auto &clos = static_cast<TyTy::ClosureType &> (r);
+ 	walk_type_to_constrain (constrained_symbols, clos.get_parameters ());
+ 	walk_type_to_constrain (constrained_symbols, *clos.get_return_type ());
+       }
+       break;
+     default:
+       break;
+     }
+ }
+ 
  bool
  TypeCheckBase::check_for_unconstrained (
    const std::vector<TyTy::SubstitutionParamMapping> &params_to_constrain,
*************** TypeCheckBase::check_for_unconstrained (
*** 87,107 ****
        HirId ref = p.get_param_ty ()->get_ref ();
        symbols_to_constrain.insert (ref);
        symbol_to_location.insert ({ref, p.get_param_locus ()});
- 
-       rust_debug_loc (p.get_param_locus (), "XX constrain THIS");
      }
  
    // set up the set of constrained symbols
    std::set<HirId> constrained_symbols;
    walk_types_to_constrain (constrained_symbols, constraint_a);
    walk_types_to_constrain (constrained_symbols, constraint_b);
! 
!   const auto root = reference->get_root ();
!   if (root->get_kind () == TyTy::TypeKind::PARAM)
!     {
!       const TyTy::ParamType *p = static_cast<const TyTy::ParamType *> (root);
!       constrained_symbols.insert (p->get_ty_ref ());
!     }
  
    // check for unconstrained
    bool unconstrained = false;
--- 166,178 ----
        HirId ref = p.get_param_ty ()->get_ref ();
        symbols_to_constrain.insert (ref);
        symbol_to_location.insert ({ref, p.get_param_locus ()});
      }
  
    // set up the set of constrained symbols
    std::set<HirId> constrained_symbols;
    walk_types_to_constrain (constrained_symbols, constraint_a);
    walk_types_to_constrain (constrained_symbols, constraint_b);
!   walk_type_to_constrain (constrained_symbols, *reference);
  
    // check for unconstrained
    bool unconstrained = false;
*************** TypeCheckBase::resolve_literal (const An
*** 296,312 ****
  	tree capacity = Compile::HIRCompileBase::query_compile_const_expr (
  	  ctx, expected_ty, *literal_capacity);
  
! 	TyTy::ConstType *capacity_expr
! 	  = new TyTy::ConstType (TyTy::ConstType::ConstKind::Value, "",
! 				 expected_ty, capacity, {},
! 				 literal_capacity->get_locus (),
! 				 literal_capacity->get_mappings ().get_hirid (),
! 				 literal_capacity->get_mappings ().get_hirid (),
! 				 {});
  
! 	TyTy::ArrayType *array
! 	  = new TyTy::ArrayType (array_mapping.get_hirid (), locus,
! 				 capacity_expr, TyTy::TyVar (u8->get_ref ()));
  	context->insert_type (array_mapping, array);
  
  	infered = new TyTy::ReferenceType (expr_mappings.get_hirid (),
--- 367,383 ----
  	tree capacity = Compile::HIRCompileBase::query_compile_const_expr (
  	  ctx, expected_ty, *literal_capacity);
  
! 	HirId capacity_expr_id = literal_capacity->get_mappings ().get_hirid ();
! 	auto capacity_expr
! 	  = new TyTy::ConstValueType (capacity, expected_ty, capacity_expr_id,
! 				      capacity_expr_id);
! 	context->insert_type (literal_capacity->get_mappings (),
! 			      capacity_expr->as_base_type ());
  
! 	TyTy::ArrayType *array = new TyTy::ArrayType (
! 	  array_mapping.get_hirid (), locus,
! 	  TyTy::TyVar (capacity_expr->as_base_type ()->get_ty_ref ()),
! 	  TyTy::TyVar (u8->get_ref ()));
  	context->insert_type (array_mapping, array);
  
  	infered = new TyTy::ReferenceType (expr_mappings.get_hirid (),
*************** TypeCheckBase::parse_repr_options (const
*** 341,347 ****
        bool is_repr = attr.get_path ().as_string () == Values::Attributes::REPR;
        if (is_repr && !attr.has_attr_input ())
  	{
! 	  rust_error_at (attr.get_locus (), "malformed %qs attribute", "repr");
  	  continue;
  	}
  
--- 412,418 ----
        bool is_repr = attr.get_path ().as_string () == Values::Attributes::REPR;
        if (is_repr && !attr.has_attr_input ())
  	{
! 	  rust_error_at (attr.get_locus (), "malformed %<repr%> attribute");
  	  continue;
  	}
  
*************** TypeCheckBase::parse_repr_options (const
*** 350,356 ****
  	  const AST::AttrInput &input = attr.get_attr_input ();
  	  bool is_token_tree = input.get_attr_input_type ()
  			       == AST::AttrInput::AttrInputType::TOKEN_TREE;
! 	  rust_assert (is_token_tree);
  	  const auto &option = static_cast<const AST::DelimTokenTree &> (input);
  	  AST::AttrInputMetaItemContainer *meta_items
  	    = option.parse_to_meta_item ();
--- 421,431 ----
  	  const AST::AttrInput &input = attr.get_attr_input ();
  	  bool is_token_tree = input.get_attr_input_type ()
  			       == AST::AttrInput::AttrInputType::TOKEN_TREE;
! 	  if (!is_token_tree)
! 	    {
! 	      rust_error_at (attr.get_locus (), "malformed %<repr%> attribute");
! 	      continue;
! 	    }
  	  const auto &option = static_cast<const AST::DelimTokenTree &> (input);
  	  AST::AttrInputMetaItemContainer *meta_items
  	    = option.parse_to_meta_item ();
*************** TypeCheckBase::resolve_generic_params (
*** 526,547 ****
  		  = Compile::HIRCompileBase::query_compile_const_expr (
  		    ctx, specified_type, expr);
  
! 		TyTy::ConstType *default_const_decl
! 		  = new TyTy::ConstType (TyTy::ConstType::ConstKind::Value,
! 					 param.get_name (), specified_type,
! 					 default_value, {}, param.get_locus (),
! 					 expr.get_mappings ().get_hirid (),
! 					 expr.get_mappings ().get_hirid (), {});
  
  		context->insert_type (expr.get_mappings (), default_const_decl);
  	      }
  
! 	    TyTy::ConstType *const_decl
! 	      = new TyTy::ConstType (TyTy::ConstType::ConstKind::Decl,
! 				     param.get_name (), specified_type,
! 				     error_mark_node, {}, param.get_locus (),
! 				     param.get_mappings ().get_hirid (),
! 				     param.get_mappings ().get_hirid (), {});
  
  	    context->insert_type (generic_param->get_mappings (), const_decl);
  	    TyTy::SubstitutionParamMapping p (*generic_param, const_decl);
--- 601,621 ----
  		  = Compile::HIRCompileBase::query_compile_const_expr (
  		    ctx, specified_type, expr);
  
! 		auto default_const_decl
! 		  = new TyTy::ConstValueType (default_value, specified_type,
! 					      expr.get_mappings ().get_hirid (),
! 					      expr.get_mappings ().get_hirid (),
! 					      {});
  
  		context->insert_type (expr.get_mappings (), default_const_decl);
  	      }
  
! 	    TyTy::BaseGeneric *const_decl
! 	      = new TyTy::ConstParamType (param.get_name (), param.get_locus (),
! 					  specified_type,
! 					  param.get_mappings ().get_hirid (),
! 					  param.get_mappings ().get_hirid (),
! 					  {});
  
  	    context->insert_type (generic_param->get_mappings (), const_decl);
  	    TyTy::SubstitutionParamMapping p (*generic_param, const_decl);
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-expr.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-expr.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-expr.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-expr.cc	Sun Nov  2 22:32:23 2025
***************
*** 34,39 ****
--- 34,40 ----
  #include "rust-immutable-name-resolution-context.h"
  #include "rust-compile-base.h"
  #include "rust-tyty-util.h"
+ #include "rust-tyty.h"
  #include "tree.h"
  
  namespace Rust {
*************** TypeCheckExpr::visit (HIR::TupleIndexExp
*** 125,131 ****
      }
  
    TyTy::ADTType *adt = static_cast<TyTy::ADTType *> (resolved);
!   rust_assert (!adt->is_enum ());
    rust_assert (adt->number_of_variants () == 1);
  
    TyTy::VariantDef *variant = adt->get_variants ().at (0);
--- 126,138 ----
      }
  
    TyTy::ADTType *adt = static_cast<TyTy::ADTType *> (resolved);
!   if (!adt->is_tuple_struct ())
!     {
!       rust_error_at (expr.get_locus (),
! 		     "expected tuple or tuple struct, found %qs",
! 		     adt->get_name ().c_str ());
!       return;
!     }
    rust_assert (adt->number_of_variants () == 1);
  
    TyTy::VariantDef *variant = adt->get_variants ().at (0);
*************** TypeCheckExpr::visit (HIR::TupleExpr &ex
*** 160,166 ****
    for (auto &elem : expr.get_tuple_elems ())
      {
        auto field_ty = TypeCheckExpr::Resolve (*elem);
!       fields.push_back (TyTy::TyVar (field_ty->get_ref ()));
      }
    infered = new TyTy::TupleType (expr.get_mappings ().get_hirid (),
  				 expr.get_locus (), fields);
--- 167,173 ----
    for (auto &elem : expr.get_tuple_elems ())
      {
        auto field_ty = TypeCheckExpr::Resolve (*elem);
!       fields.emplace_back (field_ty->get_ref ());
      }
    infered = new TyTy::TupleType (expr.get_mappings ().get_hirid (),
  				 expr.get_locus (), fields);
*************** TypeCheckExpr::visit (HIR::BlockExpr &ex
*** 629,638 ****
        if (s->is_unit_check_needed () && !resolved->is_unit ())
  	{
  	  auto unit = TyTy::TupleType::get_unit_type ();
! 	  resolved
! 	    = unify_site (s->get_mappings ().get_hirid (),
! 			  TyTy::TyWithLocation (unit),
! 			  TyTy::TyWithLocation (resolved), s->get_locus ());
  	}
      }
  
--- 636,644 ----
        if (s->is_unit_check_needed () && !resolved->is_unit ())
  	{
  	  auto unit = TyTy::TupleType::get_unit_type ();
! 	  unify_site (s->get_mappings ().get_hirid (),
! 		      TyTy::TyWithLocation (unit),
! 		      TyTy::TyWithLocation (resolved), s->get_locus ());
  	}
      }
  
*************** TypeCheckExpr::visit (HIR::AnonConst &ex
*** 669,684 ****
        return;
      }
  
!   auto locus = expr.get_locus ();
!   auto infer_ty_var = TyTy::TyVar::get_implicit_infer_var (locus);
! 
!   HirId next = mappings.get_next_hir_id ();
!   infered = new TyTy::ConstType (TyTy::ConstType::ConstKind::Infer, "",
! 				 infer_ty_var.get_tyty (), error_mark_node, {},
! 				 locus, next, next, {});
! 
!   context->insert_implicit_type (infered->get_ref (), infered);
!   mappings.insert_location (infered->get_ref (), locus);
  }
  
  void
--- 675,683 ----
        return;
      }
  
!   TyTy::TyVar var
!     = TyTy::TyVar::get_implicit_const_infer_var (expr.get_locus ());
!   infered = var.get_tyty ();
  }
  
  void
*************** TypeCheckExpr::visit (HIR::RangeFromToEx
*** 730,736 ****
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.push_back (TyTy::SubstitutionArg (param_ref, unified));
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
--- 729,735 ----
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.emplace_back (param_ref, unified);
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
*************** TypeCheckExpr::visit (HIR::RangeFromExpr
*** 774,780 ****
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.push_back (TyTy::SubstitutionArg (param_ref, from_ty));
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
--- 773,779 ----
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.emplace_back (param_ref, from_ty);
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
*************** TypeCheckExpr::visit (HIR::RangeToExpr &
*** 818,824 ****
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.push_back (TyTy::SubstitutionArg (param_ref, from_ty));
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
--- 817,823 ----
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.emplace_back (param_ref, from_ty);
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
*************** TypeCheckExpr::visit (HIR::RangeFromToIn
*** 991,997 ****
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.push_back (TyTy::SubstitutionArg (param_ref, unified));
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
--- 990,996 ----
    // substitute it in
    std::vector<TyTy::SubstitutionArg> subst_mappings;
    const TyTy::SubstitutionParamMapping *param_ref = &adt->get_substs ().at (0);
!   subst_mappings.emplace_back (param_ref, unified);
  
    TyTy::SubstitutionArgumentMappings subst (
      subst_mappings, {}, adt->get_substitution_arguments ().get_regions (),
*************** TypeCheckExpr::visit (HIR::ArrayExpr &ex
*** 1091,1105 ****
  
  	auto capacity_expr_ty
  	  = TypeCheckExpr::Resolve (elems.get_num_copies_expr ());
  
  	context->insert_type (elems.get_num_copies_expr ().get_mappings (),
  			      expected_ty);
  
! 	unify_site (
  	  expr.get_mappings ().get_hirid (), TyTy::TyWithLocation (expected_ty),
  	  TyTy::TyWithLocation (capacity_expr_ty,
  				elems.get_num_copies_expr ().get_locus ()),
  	  expr.get_locus ());
  
  	capacity_expr = &elems.get_num_copies_expr ();
  	capacity_type = expected_ty;
--- 1090,1108 ----
  
  	auto capacity_expr_ty
  	  = TypeCheckExpr::Resolve (elems.get_num_copies_expr ());
+ 	if (capacity_expr_ty->is<TyTy::ErrorType> ())
+ 	  return;
  
  	context->insert_type (elems.get_num_copies_expr ().get_mappings (),
  			      expected_ty);
  
! 	auto result = unify_site (
  	  expr.get_mappings ().get_hirid (), TyTy::TyWithLocation (expected_ty),
  	  TyTy::TyWithLocation (capacity_expr_ty,
  				elems.get_num_copies_expr ().get_locus ()),
  	  expr.get_locus ());
+ 	if (result->is<TyTy::ErrorType> ())
+ 	  return;
  
  	capacity_expr = &elems.get_num_copies_expr ();
  	capacity_type = expected_ty;
*************** TypeCheckExpr::visit (HIR::ArrayExpr &ex
*** 1152,1165 ****
    tree capacity_value
      = Compile::HIRCompileBase::query_compile_const_expr (ctx, capacity_type,
  							 *capacity_expr);
!   HirId size_id = capacity_expr->get_mappings ().get_hirid ();
!   TyTy::ConstType *const_type
!     = new TyTy::ConstType (TyTy::ConstType::ConstKind::Value, "", expected_ty,
! 			   capacity_value, {}, capacity_expr->get_locus (),
! 			   size_id, size_id);
    infered
      = new TyTy::ArrayType (expr.get_mappings ().get_hirid (), expr.get_locus (),
! 			   const_type, TyTy::TyVar (element_type->get_ref ()));
  }
  
  // empty struct
--- 1155,1177 ----
    tree capacity_value
      = Compile::HIRCompileBase::query_compile_const_expr (ctx, capacity_type,
  							 *capacity_expr);
! 
!   // Create ConstValueType with ref == ty_ref (both pointing to capacity_expr)
!   // ty_ref gets updated during substitution via set_ty_ref()
!   HirId capacity_expr_id = capacity_expr->get_mappings ().get_hirid ();
!   auto const_type
!     = new TyTy::ConstValueType (capacity_value, expected_ty, capacity_expr_id,
! 				capacity_expr_id);
! 
!   // Insert the ConstValueType at its ref
!   context->insert_type (capacity_expr->get_mappings (),
! 			const_type->as_base_type ());
! 
    infered
      = new TyTy::ArrayType (expr.get_mappings ().get_hirid (), expr.get_locus (),
! 			   TyTy::TyVar (
! 			     const_type->as_base_type ()->get_ty_ref ()),
! 			   TyTy::TyVar (element_type->get_ref ()));
  }
  
  // empty struct
*************** TypeCheckExpr::visit (HIR::ClosureExpr &
*** 1888,1894 ****
  			     // auto resolve because the hir id's match
  			  ,
  			  expr.get_locus ());
!   args.get_type_args ().push_back (std::unique_ptr<HIR::Type> (implicit_tuple));
  
    // apply the arguments
    predicate.apply_generic_arguments (&args, false, false);
--- 1900,1906 ----
  			     // auto resolve because the hir id's match
  			  ,
  			  expr.get_locus ());
!   args.get_type_args ().emplace_back (implicit_tuple);
  
    // apply the arguments
    predicate.apply_generic_arguments (&args, false, false);
*************** TypeCheckExpr::resolve_operator_overload
*** 1974,1986 ****
  
        std::vector<TyTy::SubstitutionArg> mappings;
        auto &self_param_mapping = trait_subst[0];
!       mappings.push_back (TyTy::SubstitutionArg (&self_param_mapping, lhs));
  
        if (rhs != nullptr)
  	{
  	  rust_assert (trait_subst.size () == 2);
  	  auto &rhs_param_mapping = trait_subst[1];
! 	  mappings.push_back (TyTy::SubstitutionArg (&rhs_param_mapping, lhs));
  	}
  
        std::map<std::string, TyTy::BaseType *> binding_args;
--- 1986,1998 ----
  
        std::vector<TyTy::SubstitutionArg> mappings;
        auto &self_param_mapping = trait_subst[0];
!       mappings.emplace_back (&self_param_mapping, lhs);
  
        if (rhs != nullptr)
  	{
  	  rust_assert (trait_subst.size () == 2);
  	  auto &rhs_param_mapping = trait_subst[1];
! 	  mappings.emplace_back (&rhs_param_mapping, lhs);
  	}
  
        std::map<std::string, TyTy::BaseType *> binding_args;
*************** TypeCheckExpr::resolve_operator_overload
*** 2033,2056 ****
    rust_debug ("is_impl_item_candidate: %s",
  	      resolved_candidate.is_impl_candidate () ? "true" : "false");
  
-   if (resolved_candidate.is_impl_candidate ())
-     {
-       auto infer_arguments = TyTy::SubstitutionArgumentMappings::error ();
-       HIR::ImplBlock &impl = *resolved_candidate.item.impl.parent;
-       TyTy::BaseType *impl_self_infer
- 	= TypeCheckItem::ResolveImplBlockSelfWithInference (impl,
- 							    expr.get_locus (),
- 							    &infer_arguments);
-       if (impl_self_infer->get_kind () == TyTy::TypeKind::ERROR)
- 	{
- 	  return false;
- 	}
-       if (!infer_arguments.is_empty ())
- 	{
- 	  lookup = SubstMapperInternal::Resolve (lookup, infer_arguments);
- 	}
-     }
- 
    // in the case where we resolve to a trait bound we have to be careful we are
    // able to do so there is a case where we are currently resolving the deref
    // operator overload function which is generic and this might resolve to the
--- 2045,2050 ----
*************** TypeCheckExpr::resolve_fn_trait_call (HI
*** 2312,2318 ****
    for (auto &arg : expr.get_arguments ())
      {
        TyTy::BaseType *a = TypeCheckExpr::Resolve (*arg);
!       call_args.push_back (TyTy::TyVar (a->get_ref ()));
      }
  
    // crate implicit tuple
--- 2306,2312 ----
    for (auto &arg : expr.get_arguments ())
      {
        TyTy::BaseType *a = TypeCheckExpr::Resolve (*arg);
!       call_args.emplace_back (a->get_ref ());
      }
  
    // crate implicit tuple
*************** TypeCheckExpr::resolve_fn_trait_call (HI
*** 2325,2333 ****
    context->insert_implicit_type (implicit_arg_id, tuple);
  
    std::vector<TyTy::Argument> args;
!   TyTy::Argument a (mapping, tuple,
! 		    expr.get_locus () /*FIXME is there a better location*/);
!   args.push_back (std::move (a));
  
    TyTy::BaseType *function_ret_tyty
      = TyTy::TypeCheckMethodCallExpr::go (fn, expr.get_mappings (), args,
--- 2319,2326 ----
    context->insert_implicit_type (implicit_arg_id, tuple);
  
    std::vector<TyTy::Argument> args;
!   args.emplace_back (mapping, tuple,
! 		     expr.get_locus () /*FIXME is there a better location*/);
  
    TyTy::BaseType *function_ret_tyty
      = TyTy::TypeCheckMethodCallExpr::go (fn, expr.get_mappings (), args,
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-implitem.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-implitem.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-implitem.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-implitem.cc	Sun Nov  2 22:32:23 2025
*************** TypeCheckTopLevelExternItem::visit (HIR:
*** 121,127 ****
  				UNDEF_LOCATION, false, Mutability::Imm,
  				std::unique_ptr<HIR::Pattern> (nullptr)));
  
!       params.push_back (TyTy::FnParam (std::move (param_pattern), param_tyty));
  
        context->insert_type (param.get_mappings (), param_tyty);
  
--- 121,127 ----
  				UNDEF_LOCATION, false, Mutability::Imm,
  				std::unique_ptr<HIR::Pattern> (nullptr)));
  
!       params.emplace_back (std::move (param_pattern), param_tyty);
  
        context->insert_type (param.get_mappings (), param_tyty);
  
*************** TypeCheckImplItem::visit (HIR::Function
*** 324,330 ****
  	}
  
        context->insert_type (self_param.get_mappings (), self_type);
!       params.push_back (TyTy::FnParam (std::move (self_pattern), self_type));
      }
  
    for (auto &param : function.get_function_params ())
--- 324,330 ----
  	}
  
        context->insert_type (self_param.get_mappings (), self_type);
!       params.emplace_back (std::move (self_pattern), self_type);
      }
  
    for (auto &param : function.get_function_params ())
*************** TypeCheckImplItem::visit (HIR::Function
*** 335,342 ****
        context->insert_type (param.get_mappings (), param_tyty);
        TypeCheckPattern::Resolve (param.get_param_name (), param_tyty);
  
!       params.push_back (
! 	TyTy::FnParam (param.get_param_name ().clone_pattern (), param_tyty));
      }
  
    auto &nr_ctx
--- 335,342 ----
        context->insert_type (param.get_mappings (), param_tyty);
        TypeCheckPattern::Resolve (param.get_param_name (), param_tyty);
  
!       params.emplace_back (param.get_param_name ().clone_pattern (),
! 			   param_tyty);
      }
  
    auto &nr_ctx
*************** TypeCheckImplItemWithTrait::visit (HIR::
*** 469,476 ****
      }
  
    // get the item from the predicate
!   resolved_trait_item = trait_reference.lookup_associated_item (raw_trait_item);
!   rust_assert (!resolved_trait_item.is_error ());
  
    // merge the attributes
    const HIR::TraitItem *hir_trait_item
--- 469,476 ----
      }
  
    // get the item from the predicate
!   resolved_trait_item
!     = trait_reference.lookup_associated_item (raw_trait_item).value ();
  
    // merge the attributes
    const HIR::TraitItem *hir_trait_item
*************** TypeCheckImplItemWithTrait::visit (HIR::
*** 519,526 ****
      }
  
    // get the item from the predicate
!   resolved_trait_item = trait_reference.lookup_associated_item (raw_trait_item);
!   rust_assert (!resolved_trait_item.is_error ());
  
    // merge the attributes
    const HIR::TraitItem *hir_trait_item
--- 519,526 ----
      }
  
    // get the item from the predicate
!   resolved_trait_item
!     = trait_reference.lookup_associated_item (raw_trait_item).value ();
  
    // merge the attributes
    const HIR::TraitItem *hir_trait_item
*************** TypeCheckImplItemWithTrait::visit (HIR::
*** 578,585 ****
      }
  
    // get the item from the predicate
!   resolved_trait_item = trait_reference.lookup_associated_item (raw_trait_item);
!   rust_assert (!resolved_trait_item.is_error ());
  
    // merge the attributes
    const HIR::TraitItem *hir_trait_item
--- 578,585 ----
      }
  
    // get the item from the predicate
!   resolved_trait_item
!     = trait_reference.lookup_associated_item (raw_trait_item).value ();
  
    // merge the attributes
    const HIR::TraitItem *hir_trait_item
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-item.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-item.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-item.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-item.cc	Sun Nov  2 22:32:23 2025
*************** TypeCheckItem::ResolveImplBlockSelfWithI
*** 115,127 ****
        if (p.needs_substitution ())
  	{
  	  TyTy::TyVar infer_var = TyTy::TyVar::get_implicit_infer_var (locus);
! 	  args.push_back (TyTy::SubstitutionArg (&p, infer_var.get_tyty ()));
  	}
        else
  	{
  	  auto param = p.get_param_ty ();
  	  auto resolved = param->destructure ();
! 	  args.push_back (TyTy::SubstitutionArg (&p, resolved));
  	}
      }
  
--- 115,127 ----
        if (p.needs_substitution ())
  	{
  	  TyTy::TyVar infer_var = TyTy::TyVar::get_implicit_infer_var (locus);
! 	  args.emplace_back (&p, infer_var.get_tyty ());
  	}
        else
  	{
  	  auto param = p.get_param_ty ();
  	  auto resolved = param->destructure ();
! 	  args.emplace_back (&p, resolved);
  	}
      }
  
*************** TypeCheckItem::visit (HIR::Function &fun
*** 554,561 ****
        auto param_tyty = TypeCheckType::Resolve (param.get_type ());
        context->insert_type (param.get_mappings (), param_tyty);
        TypeCheckPattern::Resolve (param.get_param_name (), param_tyty);
!       params.push_back (
! 	TyTy::FnParam (param.get_param_name ().clone_pattern (), param_tyty));
      }
  
    auto &nr_ctx
--- 554,561 ----
        auto param_tyty = TypeCheckType::Resolve (param.get_type ());
        context->insert_type (param.get_mappings (), param_tyty);
        TypeCheckPattern::Resolve (param.get_param_name (), param_tyty);
!       params.emplace_back (param.get_param_name ().clone_pattern (),
! 			   param_tyty);
      }
  
    auto &nr_ctx
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-path.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-path.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-path.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-path.cc	Sun Nov  2 22:32:23 2025
*************** TypeCheckExpr::visit (HIR::QualifiedPath
*** 77,85 ****
    // lookup the associated item from the specified bound
    HIR::PathExprSegment &item_seg = expr.get_segments ().at (0);
    HIR::PathIdentSegment item_seg_identifier = item_seg.get_segment ();
!   TyTy::TypeBoundPredicateItem item
      = specified_bound.lookup_associated_item (item_seg_identifier.as_string ());
!   if (item.is_error ())
      {
        rust_error_at (item_seg.get_locus (), "unknown associated item");
        return;
--- 77,85 ----
    // lookup the associated item from the specified bound
    HIR::PathExprSegment &item_seg = expr.get_segments ().at (0);
    HIR::PathIdentSegment item_seg_identifier = item_seg.get_segment ();
!   tl::optional<TyTy::TypeBoundPredicateItem> item
      = specified_bound.lookup_associated_item (item_seg_identifier.as_string ());
!   if (!item.has_value ())
      {
        rust_error_at (item_seg.get_locus (), "unknown associated item");
        return;
*************** TypeCheckExpr::visit (HIR::QualifiedPath
*** 116,124 ****
        // and we dont need to worry if the trait item is actually implemented or
        // not because this will have already been validated as part of the trait
        // impl block
!       infered = item.get_tyty_for_receiver (root);
        root_resolved_node_id
! 	= item.get_raw_item ()->get_mappings ().get_nodeid ();
      }
    else
      {
--- 116,124 ----
        // and we dont need to worry if the trait item is actually implemented or
        // not because this will have already been validated as part of the trait
        // impl block
!       infered = item->get_tyty_for_receiver (root);
        root_resolved_node_id
! 	= item->get_raw_item ()->get_mappings ().get_nodeid ();
      }
    else
      {
*************** TypeCheckExpr::resolve_segments (NodeId
*** 517,525 ****
  	      const auto &predicate
  		= impl_block_ty->lookup_predicate (trait_ref.get_defid ());
  	      if (!predicate.is_error ())
! 		impl_block_ty
! 		  = associated->setup_associated_types (prev_segment, predicate,
! 							nullptr, false);
  	    }
  	}
  
--- 517,524 ----
  	      const auto &predicate
  		= impl_block_ty->lookup_predicate (trait_ref.get_defid ());
  	      if (!predicate.is_error ())
! 		associated->setup_associated_types (prev_segment, predicate,
! 						    nullptr, false);
  	    }
  	}
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-pattern.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-pattern.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-pattern.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-pattern.cc	Sun Nov  2 22:32:23 2025
***************
*** 21,26 ****
--- 21,28 ----
  #include "rust-hir-type-check-expr.h"
  #include "rust-type-util.h"
  #include "rust-immutable-name-resolution-context.h"
+ #include "rust-tyty.h"
+ #include "tree.h"
  
  namespace Rust {
  namespace Resolver {
*************** TypeCheckPattern::visit (HIR::TupleStruc
*** 160,178 ****
  
    infered = pattern_ty;
    TyTy::ADTType *adt = static_cast<TyTy::ADTType *> (infered);
-   rust_assert (adt->number_of_variants () > 0);
  
!   TyTy::VariantDef *variant = adt->get_variants ().at (0);
    if (adt->is_enum ())
      {
        HirId variant_id = UNKNOWN_HIRID;
        bool ok = context->lookup_variant_definition (
  	pattern.get_path ().get_mappings ().get_hirid (), &variant_id);
!       rust_assert (ok);
  
        ok = adt->lookup_variant_by_id (variant_id, &variant);
        rust_assert (ok);
      }
  
    // error[E0532]: expected tuple struct or tuple variant, found struct
    // variant `Foo::D`, E0532 by rustc 1.49.0 , E0164 by rustc 1.71.0
--- 162,193 ----
  
    infered = pattern_ty;
    TyTy::ADTType *adt = static_cast<TyTy::ADTType *> (infered);
  
!   TyTy::VariantDef *variant = nullptr;
    if (adt->is_enum ())
      {
        HirId variant_id = UNKNOWN_HIRID;
        bool ok = context->lookup_variant_definition (
  	pattern.get_path ().get_mappings ().get_hirid (), &variant_id);
!       if (!ok)
! 	{
! 	  rust_error_at (
! 	    pattern.get_locus (), ErrorCode::E0532,
! 	    "expected tuple struct or tuple variant, found enum %qs",
! 	    pattern_ty->get_name ().c_str ());
! 	  return;
! 	}
  
        ok = adt->lookup_variant_by_id (variant_id, &variant);
        rust_assert (ok);
      }
+   else
+     {
+       rust_assert (adt->number_of_variants () > 0);
+       variant = adt->get_variants ().at (0);
+     }
+ 
+   rust_assert (variant != nullptr);
  
    // error[E0532]: expected tuple struct or tuple variant, found struct
    // variant `Foo::D`, E0532 by rustc 1.49.0 , E0164 by rustc 1.71.0
*************** TypeCheckPattern::visit (HIR::TupleStruc
*** 200,232 ****
    auto &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case HIR::TupleStructItems::RANGED:
        {
! 	// TODO
! 	rust_unreachable ();
        }
        break;
  
!     case HIR::TupleStructItems::MULTIPLE:
        {
! 	HIR::TupleStructItemsNoRange &items_no_range
! 	  = static_cast<HIR::TupleStructItemsNoRange &> (items);
  
! 	if (items_no_range.get_patterns ().size () != variant->num_fields ())
  	  {
! 	    rust_error_at (
! 	      pattern.get_locus (), ErrorCode::E0023,
! 	      "this pattern has %lu fields but the corresponding "
! 	      "tuple variant has %lu field",
! 	      (unsigned long) items_no_range.get_patterns ().size (),
! 	      (unsigned long) variant->num_fields ());
  	    // we continue on to try and setup the types as best we can for
  	    // type checking
  	  }
  
  	// iterate the fields and set them up, I wish we had ZIP
  	size_t i = 0;
! 	for (auto &pattern : items_no_range.get_patterns ())
  	  {
  	    if (i >= variant->num_fields ())
  	      break;
--- 215,358 ----
    auto &items = pattern.get_items ();
    switch (items.get_item_type ())
      {
!     case HIR::TupleStructItems::HAS_REST:
        {
! 	HIR::TupleStructItemsHasRest &items_has_rest
! 	  = static_cast<HIR::TupleStructItemsHasRest &> (items);
! 	auto &lower_patterns = items_has_rest.get_lower_patterns ();
! 	auto &upper_patterns = items_has_rest.get_upper_patterns ();
! 	size_t pattern_min_cap
! 	  = lower_patterns.size () + upper_patterns.size ();
! 	if (variant->num_fields () < pattern_min_cap)
! 	  {
! 	    if (!lower_patterns.empty ())
! 	      {
! 		// TODO initialize rich_locus with loc of ADT definition instead
! 		rich_location rich_locus (line_table,
! 					  lower_patterns[0]->get_locus ());
! 		for (auto &pattern : lower_patterns)
! 		  {
! 		    if (pattern == lower_patterns[0])
! 		      continue;
! 		    rich_locus.add_range (pattern->get_locus (),
! 					  SHOW_RANGE_WITH_CARET);
! 		  }
! 		for (auto &pattern : upper_patterns)
! 		  {
! 		    rich_locus.add_range (pattern->get_locus (),
! 					  SHOW_RANGE_WITH_CARET);
! 		  }
! 		rust_error_at (rich_locus, ErrorCode::E0023,
! 			       "this pattern has %lu %s but the corresponding "
! 			       "tuple variant has %lu %s",
! 			       (unsigned long) (pattern_min_cap),
! 			       pattern_min_cap == 1 ? "field" : "fields",
! 			       (unsigned long) variant->num_fields (),
! 			       variant->num_fields () == 1 ? "field"
! 							   : "fields");
! 	      }
! 	    else
! 	      {
! 		// TODO initialize rich_locus with loc of ADT definition instead
! 		rich_location rich_locus (line_table,
! 					  upper_patterns[0]->get_locus ());
! 		for (auto &pattern : upper_patterns)
! 		  {
! 		    if (pattern == upper_patterns[0])
! 		      continue;
! 		    rich_locus.add_range (pattern->get_locus (),
! 					  SHOW_RANGE_WITH_CARET);
! 		  }
! 		rust_error_at (rich_locus, ErrorCode::E0023,
! 			       "this pattern has %lu %s but the corresponding "
! 			       "tuple variant has %lu %s",
! 			       (unsigned long) (pattern_min_cap),
! 			       pattern_min_cap == 1 ? "field" : "fields",
! 			       (unsigned long) variant->num_fields (),
! 			       variant->num_fields () == 1 ? "field"
! 							   : "fields");
! 	      }
! 	    // we continue on to try and setup the types as best we can for
! 	    // type checking
! 	  }
! 
! 	// iterate the fields manually to set them up
! 	size_t i = 0;
! 	for (auto &pattern : lower_patterns)
! 	  {
! 	    if (i >= variant->num_fields ())
! 	      break;
! 
! 	    TyTy::StructFieldType *field = variant->get_field_at_index (i++);
! 	    TyTy::BaseType *fty = field->get_field_type ();
! 
! 	    // setup the type on this pattern type
! 	    context->insert_type (pattern->get_mappings (), fty);
! 	    TypeCheckPattern::Resolve (*pattern, fty);
! 	  }
! 
! 	i = variant->num_fields () - upper_patterns.size ();
! 	for (auto &pattern : upper_patterns)
! 	  {
! 	    if (i >= variant->num_fields ())
! 	      break;
! 
! 	    TyTy::StructFieldType *field = variant->get_field_at_index (i++);
! 	    TyTy::BaseType *fty = field->get_field_type ();
! 
! 	    // setup the type on this pattern type
! 	    context->insert_type (pattern->get_mappings (), fty);
! 	    TypeCheckPattern::Resolve (*pattern, fty);
! 	  }
        }
        break;
  
!     case HIR::TupleStructItems::NO_REST:
        {
! 	HIR::TupleStructItemsNoRest &items_no_rest
! 	  = static_cast<HIR::TupleStructItemsNoRest &> (items);
! 	auto &patterns = items_no_rest.get_patterns ();
  
! 	if (patterns.size () != variant->num_fields ())
  	  {
! 	    if (patterns.empty ())
! 	      {
! 		rust_error_at (pattern.get_locus (), ErrorCode::E0023,
! 			       "this pattern has %lu %s but the corresponding "
! 			       "tuple variant has %lu %s",
! 			       (unsigned long) patterns.size (),
! 			       patterns.size () == 1 ? "field" : "fields",
! 			       (unsigned long) variant->num_fields (),
! 			       variant->num_fields () == 1 ? "field"
! 							   : "fields");
! 	      }
! 	    else
! 	      {
! 		rich_location rich_locus (line_table,
! 					  patterns[0]->get_locus ());
! 		for (auto &pattern : items_no_rest.get_patterns ())
! 		  {
! 		    if (pattern == patterns[0])
! 		      continue;
! 		    rich_locus.add_range (pattern->get_locus (),
! 					  SHOW_RANGE_WITH_CARET);
! 		  }
! 		rust_error_at (rich_locus, ErrorCode::E0023,
! 			       "this pattern has %lu %s but the corresponding "
! 			       "tuple variant has %lu %s",
! 			       (unsigned long) patterns.size (),
! 			       patterns.size () == 1 ? "field" : "fields",
! 			       (unsigned long) variant->num_fields (),
! 			       variant->num_fields () == 1 ? "field"
! 							   : "fields");
! 	      }
  	    // we continue on to try and setup the types as best we can for
  	    // type checking
  	  }
  
  	// iterate the fields and set them up, I wish we had ZIP
  	size_t i = 0;
! 	for (auto &pattern : items_no_rest.get_patterns ())
  	  {
  	    if (i >= variant->num_fields ())
  	      break;
*************** TypeCheckPattern::visit (HIR::StructPatt
*** 299,305 ****
  
    // error[E0532]: expected tuple struct or tuple variant, found struct
    // variant `Foo::D`
!   if (variant->get_variant_type () != TyTy::VariantDef::VariantType::STRUCT)
      {
        std::string variant_type
  	= TyTy::VariantDef::variant_type_string (variant->get_variant_type ());
--- 425,454 ----
  
    // error[E0532]: expected tuple struct or tuple variant, found struct
    // variant `Foo::D`
!   bool error_E0532 = false;
!   if (variant->get_variant_type () == TyTy::VariantDef::VariantType::TUPLE)
!     {
!       // Tuple structs can still be matched with struct patterns via index
!       // numbers e.g. Foo {0: a, .., 3: b}, so check whether the fields are of
!       // type TUPLE_PAT. Throw E0532 if not.
!       auto &struct_pattern_elems = pattern.get_struct_pattern_elems ();
!       for (auto &field : struct_pattern_elems.get_struct_pattern_fields ())
! 	{
! 	  if (field->get_item_type ()
! 	      != HIR::StructPatternField::ItemType::TUPLE_PAT)
! 	    {
! 	      error_E0532 = true;
! 	      break;
! 	    }
! 	}
!     }
!   else if (variant->get_variant_type ()
! 	   != TyTy::VariantDef::VariantType::STRUCT)
!     {
!       error_E0532 = true;
!     }
! 
!   if (error_E0532)
      {
        std::string variant_type
  	= TyTy::VariantDef::variant_type_string (variant->get_variant_type ());
*************** TypeCheckPattern::visit (HIR::StructPatt
*** 407,413 ****
        // Expects enum struct or struct struct.
        // error[E0027]: pattern does not mention fields `x`, `y`
        // error[E0026]: variant `Foo::D` does not have a field named `b`
!       if (named_fields.size () != variant->num_fields ())
  	{
  	  std::map<std::string, bool> missing_names;
  
--- 556,563 ----
        // Expects enum struct or struct struct.
        // error[E0027]: pattern does not mention fields `x`, `y`
        // error[E0026]: variant `Foo::D` does not have a field named `b`
!       if (!pattern.get_struct_pattern_elems ().has_rest ()
! 	  && named_fields.size () != variant->num_fields ())
  	{
  	  std::map<std::string, bool> missing_names;
  
*************** TypeCheckPattern::visit (HIR::TuplePatte
*** 463,472 ****
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::MULTIPLE:
        {
! 	auto &ref = static_cast<HIR::TuplePatternItemsMultiple &> (
! 	  pattern.get_items ());
  
  	const auto &patterns = ref.get_patterns ();
  	size_t nitems_to_resolve = patterns.size ();
--- 613,622 ----
  
    switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::TuplePatternItems::ItemType::NO_REST:
        {
! 	auto &ref
! 	  = static_cast<HIR::TuplePatternItemsNoRest &> (pattern.get_items ());
  
  	const auto &patterns = ref.get_patterns ();
  	size_t nitems_to_resolve = patterns.size ();
*************** TypeCheckPattern::visit (HIR::TuplePatte
*** 486,502 ****
  	    TyTy::BaseType *par_type = par.get_field (i);
  
  	    TyTy::BaseType *elem = TypeCheckPattern::Resolve (*p, par_type);
! 	    pattern_elems.push_back (TyTy::TyVar (elem->get_ref ()));
  	  }
  	infered = new TyTy::TupleType (pattern.get_mappings ().get_hirid (),
  				       pattern.get_locus (), pattern_elems);
        }
        break;
  
!     case HIR::TuplePatternItems::ItemType::RANGED:
        {
! 	HIR::TuplePatternItemsRanged &ref
! 	  = static_cast<HIR::TuplePatternItemsRanged &> (pattern.get_items ());
  
  	const auto &lower = ref.get_lower_patterns ();
  	const auto &upper = ref.get_upper_patterns ();
--- 636,652 ----
  	    TyTy::BaseType *par_type = par.get_field (i);
  
  	    TyTy::BaseType *elem = TypeCheckPattern::Resolve (*p, par_type);
! 	    pattern_elems.emplace_back (elem->get_ref ());
  	  }
  	infered = new TyTy::TupleType (pattern.get_mappings ().get_hirid (),
  				       pattern.get_locus (), pattern_elems);
        }
        break;
  
!     case HIR::TuplePatternItems::ItemType::HAS_REST:
        {
! 	HIR::TuplePatternItemsHasRest &ref
! 	  = static_cast<HIR::TuplePatternItemsHasRest &> (pattern.get_items ());
  
  	const auto &lower = ref.get_lower_patterns ();
  	const auto &upper = ref.get_upper_patterns ();
*************** TypeCheckPattern::visit (HIR::TuplePatte
*** 507,543 ****
  	  {
  	    emit_pattern_size_error (pattern, par.get_fields ().size (),
  				     min_size_required);
! 	    // TODO attempt to continue to do typechecking even after wrong size
! 	    break;
  	  }
  
  	// Resolve lower patterns
  	std::vector<TyTy::TyVar> pattern_elems;
! 	for (size_t i = 0; i < lower.size (); i++)
  	  {
  	    auto &p = lower[i];
  	    TyTy::BaseType *par_type = par.get_field (i);
  
  	    TyTy::BaseType *elem = TypeCheckPattern::Resolve (*p, par_type);
! 	    pattern_elems.push_back (TyTy::TyVar (elem->get_ref ()));
  	  }
  
  	// Pad pattern_elems until needing to resolve upper patterns
! 	size_t rest_end = par.get_fields ().size () - upper.size ();
  	for (size_t i = lower.size (); i < rest_end; i++)
  	  {
  	    TyTy::BaseType *par_type = par.get_field (i);
! 	    pattern_elems.push_back (TyTy::TyVar (par_type->get_ref ()));
  	  }
  
  	// Resolve upper patterns
! 	for (size_t i = 0; i < upper.size (); i++)
  	  {
  	    auto &p = upper[i];
  	    TyTy::BaseType *par_type = par.get_field (rest_end + i);
  
  	    TyTy::BaseType *elem = TypeCheckPattern::Resolve (*p, par_type);
! 	    pattern_elems.push_back (TyTy::TyVar (elem->get_ref ()));
  	  }
  
  	infered = new TyTy::TupleType (pattern.get_mappings ().get_hirid (),
--- 657,701 ----
  	  {
  	    emit_pattern_size_error (pattern, par.get_fields ().size (),
  				     min_size_required);
! 	    // continue and attempt to resolve individual items in the pattern
  	  }
  
  	// Resolve lower patterns
  	std::vector<TyTy::TyVar> pattern_elems;
! 	size_t nlower_items_to_resolve
! 	  = std::min (lower.size (), par.get_fields ().size ());
! 	for (size_t i = 0; i < nlower_items_to_resolve; i++)
  	  {
  	    auto &p = lower[i];
  	    TyTy::BaseType *par_type = par.get_field (i);
  
  	    TyTy::BaseType *elem = TypeCheckPattern::Resolve (*p, par_type);
! 	    pattern_elems.emplace_back (elem->get_ref ());
  	  }
  
+ 	if (lower.size () > par.get_fields ().size ())
+ 	  break;
+ 
  	// Pad pattern_elems until needing to resolve upper patterns
! 	size_t rest_end
! 	  = std::max (par.get_fields ().size () - upper.size (), lower.size ());
  	for (size_t i = lower.size (); i < rest_end; i++)
  	  {
  	    TyTy::BaseType *par_type = par.get_field (i);
! 	    pattern_elems.emplace_back (par_type->get_ref ());
  	  }
  
+ 	size_t nupper_items_to_resolve
+ 	  = std::min (upper.size (),
+ 		      par.get_fields ().size () - pattern_elems.size ());
  	// Resolve upper patterns
! 	for (size_t i = 0; i < nupper_items_to_resolve; i++)
  	  {
  	    auto &p = upper[i];
  	    TyTy::BaseType *par_type = par.get_field (rest_end + i);
  
  	    TyTy::BaseType *elem = TypeCheckPattern::Resolve (*p, par_type);
! 	    pattern_elems.emplace_back (elem->get_ref ());
  	  }
  
  	infered = new TyTy::TupleType (pattern.get_mappings ().get_hirid (),
*************** TypeCheckPattern::visit (HIR::SlicePatte
*** 642,648 ****
  	auto &array_ty_ty = static_cast<TyTy::ArrayType &> (*parent);
  	parent_element_ty = array_ty_ty.get_element_type ();
  	auto capacity = array_ty_ty.get_capacity ();
! 	tree cap = capacity->get_value ();
  	if (error_operand_p (cap))
  	  {
  	    rust_error_at (parent->get_locus (),
--- 800,831 ----
  	auto &array_ty_ty = static_cast<TyTy::ArrayType &> (*parent);
  	parent_element_ty = array_ty_ty.get_element_type ();
  	auto capacity = array_ty_ty.get_capacity ();
! 
! 	tree cap = error_mark_node;
! 	if (capacity->get_kind () != TyTy::TypeKind::CONST)
! 	  {
! 	    // Error case - capacity is not a const type
! 	    break;
! 	  }
! 
! 	auto *capacity_const = capacity->as_const_type ();
! 	switch (capacity_const->const_kind ())
! 	  {
! 	  case TyTy::BaseConstType::ConstKind::Value:
! 	    {
! 	      const auto &const_value
! 		= *static_cast<TyTy::ConstValueType *> (capacity);
! 	      cap = const_value.get_value ();
! 	    }
! 	    break;
! 
! 	  case TyTy::BaseConstType::ConstKind::Decl:
! 	  case TyTy::BaseConstType::ConstKind::Infer:
! 	  case TyTy::BaseConstType::ConstKind::Error:
! 	    cap = error_mark_node;
! 	    break;
! 	  }
! 
  	if (error_operand_p (cap))
  	  {
  	    rust_error_at (parent->get_locus (),
*************** TypeCheckPattern::visit (HIR::SlicePatte
*** 651,664 ****
  	    break;
  	  }
  	auto cap_wi = wi::to_wide (cap).to_uhwi ();
! 	if (cap_wi != pattern.get_items ().size ())
  	  {
! 	    rust_error_at (pattern.get_locus (), ErrorCode::E0527,
! 			   "pattern requires %lu elements but array has %lu",
! 			   (unsigned long) pattern.get_items ().size (),
! 			   (unsigned long) cap_wi);
  	    break;
  	  }
  	break;
        }
      case TyTy::SLICE:
--- 834,878 ----
  	    break;
  	  }
  	auto cap_wi = wi::to_wide (cap).to_uhwi ();
! 
! 	// size check during compile time
! 	switch (pattern.get_items ().get_item_type ())
  	  {
! 	  case HIR::SlicePatternItems::ItemType::NO_REST:
! 	    {
! 	      auto &ref = static_cast<HIR::SlicePatternItemsNoRest &> (
! 		pattern.get_items ());
! 	      if (cap_wi != ref.get_patterns ().size ())
! 		{
! 		  rust_error_at (
! 		    pattern.get_locus (), ErrorCode::E0527,
! 		    "pattern requires %lu elements but array has %lu",
! 		    (unsigned long) ref.get_patterns ().size (),
! 		    (unsigned long) cap_wi);
! 		  break;
! 		}
! 	    }
! 	    break;
! 	  case HIR::SlicePatternItems::ItemType::HAS_REST:
! 	    {
! 	      auto &ref = static_cast<HIR::SlicePatternItemsHasRest &> (
! 		pattern.get_items ());
! 	      auto pattern_min_cap = ref.get_lower_patterns ().size ()
! 				     + ref.get_upper_patterns ().size ();
! 
! 	      if (cap_wi < pattern_min_cap)
! 		{
! 		  rust_error_at (pattern.get_locus (), ErrorCode::E0528,
! 				 "pattern requires at least %lu elements but "
! 				 "array has %lu",
! 				 (unsigned long) pattern_min_cap,
! 				 (unsigned long) cap_wi);
! 		  break;
! 		}
! 	    }
  	    break;
  	  }
+ 
  	break;
        }
      case TyTy::SLICE:
*************** TypeCheckPattern::visit (HIR::SlicePatte
*** 694,703 ****
    infered->set_ref (pattern.get_mappings ().get_hirid ());
  
    // Type check every item in the SlicePattern against parent's element ty
!   // TODO update this after adding support for RestPattern in SlicePattern
!   for (const auto &item : pattern.get_items ())
      {
!       TypeCheckPattern::Resolve (*item, parent_element_ty);
      }
  }
  
--- 908,939 ----
    infered->set_ref (pattern.get_mappings ().get_hirid ());
  
    // Type check every item in the SlicePattern against parent's element ty
!   switch (pattern.get_items ().get_item_type ())
      {
!     case HIR::SlicePatternItems::ItemType::NO_REST:
!       {
! 	auto &ref
! 	  = static_cast<HIR::SlicePatternItemsNoRest &> (pattern.get_items ());
! 	for (const auto &pattern_member : ref.get_patterns ())
! 	  {
! 	    TypeCheckPattern::Resolve (*pattern_member, parent_element_ty);
! 	  }
! 	break;
!       }
!     case HIR::SlicePatternItems::ItemType::HAS_REST:
!       {
! 	auto &ref
! 	  = static_cast<HIR::SlicePatternItemsHasRest &> (pattern.get_items ());
! 	for (const auto &pattern_member : ref.get_lower_patterns ())
! 	  {
! 	    TypeCheckPattern::Resolve (*pattern_member, parent_element_ty);
! 	  }
! 	for (const auto &pattern_member : ref.get_upper_patterns ())
! 	  {
! 	    TypeCheckPattern::Resolve (*pattern_member, parent_element_ty);
! 	  }
! 	break;
!       }
      }
  }
  
*************** ClosureParamInfer::visit (HIR::WildcardP
*** 814,819 ****
--- 1050,1060 ----
  void
  ClosureParamInfer::visit (HIR::IdentifierPattern &pattern)
  {
+   if (pattern.has_subpattern ())
+     {
+       ClosureParamInfer::Resolve (pattern.get_subpattern ());
+     }
+ 
    HirId id = pattern.get_mappings ().get_hirid ();
    infered = new TyTy::InferType (id, TyTy::InferType::InferTypeKind::GENERAL,
  				 TyTy::InferType::TypeHint::Default (),
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-struct.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-struct.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-struct.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-struct.cc	Sun Nov  2 22:32:23 2025
*************** TypeCheckStructExpr::resolve (HIR::Struc
*** 214,221 ****
  	      rust_assert (ok);
  
  	      adtFieldIndexToField[field_index] = implicit_field;
! 	      struct_expr.get_fields ().push_back (
! 		std::unique_ptr<HIR::StructExprField> (implicit_field));
  	    }
  	}
      }
--- 214,220 ----
  	      rust_assert (ok);
  
  	      adtFieldIndexToField[field_index] = implicit_field;
! 	      struct_expr.get_fields ().emplace_back (implicit_field);
  	    }
  	}
      }
*************** TypeCheckStructExpr::resolve (HIR::Struc
*** 245,255 ****
  	field.release ();
  
        std::vector<std::unique_ptr<HIR::StructExprField> > ordered_fields;
        for (size_t i = 0; i < adtFieldIndexToField.size (); i++)
! 	{
! 	  ordered_fields.push_back (
! 	    std::unique_ptr<HIR::StructExprField> (adtFieldIndexToField[i]));
! 	}
        struct_expr.set_fields_as_owner (std::move (ordered_fields));
      }
  
--- 244,254 ----
  	field.release ();
  
        std::vector<std::unique_ptr<HIR::StructExprField> > ordered_fields;
+       ordered_fields.reserve (adtFieldIndexToField.size ());
+ 
        for (size_t i = 0; i < adtFieldIndexToField.size (); i++)
! 	ordered_fields.emplace_back (adtFieldIndexToField[i]);
! 
        struct_expr.set_fields_as_owner (std::move (ordered_fields));
      }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-type.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-type.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check-type.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check-type.cc	Sun Nov  2 22:32:23 2025
*************** TypeCheckType::visit (HIR::BareFunctionT
*** 97,111 ****
      }
  
    std::vector<TyTy::TyVar> params;
    for (auto &param : fntype.get_function_params ())
      {
        TyTy::BaseType *ptype = TypeCheckType::Resolve (param.get_type ());
!       params.push_back (TyTy::TyVar (ptype->get_ref ()));
      }
  
!   translated = new TyTy::FnPtr (fntype.get_mappings ().get_hirid (),
! 				fntype.get_locus (), std::move (params),
! 				TyTy::TyVar (return_type->get_ref ()));
  }
  
  void
--- 97,116 ----
      }
  
    std::vector<TyTy::TyVar> params;
+   params.reserve (fntype.get_function_params ().size ());
+ 
    for (auto &param : fntype.get_function_params ())
      {
        TyTy::BaseType *ptype = TypeCheckType::Resolve (param.get_type ());
!       params.emplace_back (ptype->get_ref ());
      }
  
!   translated
!     = new TyTy::FnPtr (fntype.get_mappings ().get_hirid (), fntype.get_locus (),
! 		       std::move (params),
! 		       TyTy::TyVar (return_type->get_ref ()),
! 		       fntype.get_function_qualifiers ().get_abi (),
! 		       fntype.get_function_qualifiers ().get_unsafety ());
  }
  
  void
*************** TypeCheckType::visit (HIR::TupleType &tu
*** 118,127 ****
      }
  
    std::vector<TyTy::TyVar> fields;
    for (auto &elem : tuple.get_elems ())
      {
        auto field_ty = TypeCheckType::Resolve (*elem);
!       fields.push_back (TyTy::TyVar (field_ty->get_ref ()));
      }
  
    translated = new TyTy::TupleType (tuple.get_mappings ().get_hirid (),
--- 123,134 ----
      }
  
    std::vector<TyTy::TyVar> fields;
+   fields.reserve (tuple.get_elems ().size ());
+ 
    for (auto &elem : tuple.get_elems ())
      {
        auto field_ty = TypeCheckType::Resolve (*elem);
!       fields.emplace_back (field_ty->get_ref ());
      }
  
    translated = new TyTy::TupleType (tuple.get_mappings ().get_hirid (),
*************** TypeCheckType::visit (HIR::QualifiedPath
*** 207,215 ****
    // lookup the associated item from the specified bound
    HIR::TypePathSegment &item_seg = path.get_associated_segment ();
    HIR::PathIdentSegment item_seg_identifier = item_seg.get_ident_segment ();
!   TyTy::TypeBoundPredicateItem item
      = specified_bound.lookup_associated_item (item_seg_identifier.as_string ());
!   if (item.is_error ())
      {
        std::string item_seg_ident_name, rich_msg;
        item_seg_ident_name = qual_path_type.get_trait ().as_string ();
--- 214,222 ----
    // lookup the associated item from the specified bound
    HIR::TypePathSegment &item_seg = path.get_associated_segment ();
    HIR::PathIdentSegment item_seg_identifier = item_seg.get_ident_segment ();
!   tl::optional<TyTy::TypeBoundPredicateItem> item
      = specified_bound.lookup_associated_item (item_seg_identifier.as_string ());
!   if (!item.has_value ())
      {
        std::string item_seg_ident_name, rich_msg;
        item_seg_ident_name = qual_path_type.get_trait ().as_string ();
*************** TypeCheckType::visit (HIR::QualifiedPath
*** 261,267 ****
        // and we dont need to worry if the trait item is actually implemented or
        // not because this will have already been validated as part of the trait
        // impl block
!       translated = item.get_tyty_for_receiver (root);
      }
    else
      {
--- 268,274 ----
        // and we dont need to worry if the trait item is actually implemented or
        // not because this will have already been validated as part of the trait
        // impl block
!       translated = item->get_tyty_for_receiver (root);
      }
    else
      {
*************** TypeCheckType::visit (HIR::ArrayType &ty
*** 699,736 ****
    rust_assert (ok);
    context->insert_type (type.get_size_expr ().get_mappings (), expected_ty);
  
!   TyTy::ConstType *const_type = nullptr;
    if (capacity_type->get_kind () == TyTy::TypeKind::CONST)
      {
!       const_type = static_cast<TyTy::ConstType *> (capacity_type);
  
        unify_site (type.get_size_expr ().get_mappings ().get_hirid (),
  		  TyTy::TyWithLocation (expected_ty),
! 		  TyTy::TyWithLocation (const_type->get_ty (),
  					type.get_size_expr ().get_locus ()),
  		  type.get_size_expr ().get_locus ());
      }
    else
      {
        HirId size_id = type.get_size_expr ().get_mappings ().get_hirid ();
!       unify_site (size_id, TyTy::TyWithLocation (expected_ty),
! 		  TyTy::TyWithLocation (capacity_type,
! 					type.get_size_expr ().get_locus ()),
! 		  type.get_size_expr ().get_locus ());
  
!       auto ctx = Compile::Context::get ();
!       tree capacity_expr = Compile::HIRCompileBase::query_compile_const_expr (
! 	ctx, capacity_type, type.get_size_expr ());
  
!       const_type = new TyTy::ConstType (TyTy::ConstType::ConstKind::Value, "",
! 					expected_ty, capacity_expr, {},
! 					type.get_size_expr ().get_locus (),
! 					size_id, size_id);
      }
  
    translated
      = new TyTy::ArrayType (type.get_mappings ().get_hirid (), type.get_locus (),
! 			   const_type, TyTy::TyVar (element_type->get_ref ()));
  }
  
  void
--- 706,752 ----
    rust_assert (ok);
    context->insert_type (type.get_size_expr ().get_mappings (), expected_ty);
  
!   TyTy::BaseConstType *const_type = nullptr;
    if (capacity_type->get_kind () == TyTy::TypeKind::CONST)
      {
!       const_type = capacity_type->as_const_type ();
  
        unify_site (type.get_size_expr ().get_mappings ().get_hirid (),
  		  TyTy::TyWithLocation (expected_ty),
! 		  TyTy::TyWithLocation (const_type->get_specified_type (),
  					type.get_size_expr ().get_locus ()),
  		  type.get_size_expr ().get_locus ());
      }
    else
      {
        HirId size_id = type.get_size_expr ().get_mappings ().get_hirid ();
!       TyTy::BaseType *result
! 	= unify_site (size_id, TyTy::TyWithLocation (expected_ty),
! 		      TyTy::TyWithLocation (capacity_type,
! 					    type.get_size_expr ().get_locus ()),
! 		      type.get_size_expr ().get_locus ());
  
!       if (result->is<TyTy::ErrorType> ())
! 	const_type = new TyTy::ConstErrorType (expected_ty, size_id, size_id);
!       else
! 	{
! 	  auto ctx = Compile::Context::get ();
! 	  tree capacity_expr
! 	    = Compile::HIRCompileBase::query_compile_const_expr (
! 	      ctx, capacity_type, type.get_size_expr ());
  
! 	  const_type = new TyTy::ConstValueType (capacity_expr, expected_ty,
! 						 size_id, size_id);
! 	  context->insert_type (type.get_size_expr ().get_mappings (),
! 				const_type->as_base_type ());
! 	}
      }
  
    translated
      = new TyTy::ArrayType (type.get_mappings ().get_hirid (), type.get_locus (),
! 			   TyTy::TyVar (
! 			     const_type->as_base_type ()->get_ty_ref ()),
! 			   TyTy::TyVar (element_type->get_ref ()));
  }
  
  void
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check.cc gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-hir-type-check.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-hir-type-check.cc	Sun Nov  2 22:32:23 2025
*************** TraitItemReference::get_type_from_fn (/*
*** 260,266 ****
  	}
  
        context->insert_type (self_param.get_mappings (), self_type);
!       params.push_back (TyTy::FnParam (std::move (self_pattern), self_type));
      }
  
    for (auto &param : function.get_function_params ())
--- 260,266 ----
  	}
  
        context->insert_type (self_param.get_mappings (), self_type);
!       params.emplace_back (std::move (self_pattern), self_type);
      }
  
    for (auto &param : function.get_function_params ())
*************** TraitItemReference::get_type_from_fn (/*
*** 270,277 ****
        context->insert_type (param.get_mappings (), param_tyty);
        TypeCheckPattern::Resolve (param.get_param_name (), param_tyty);
        // FIXME: Should we take the name ? Use a shared pointer instead ?
!       params.push_back (
! 	TyTy::FnParam (param.get_param_name ().clone_pattern (), param_tyty));
      }
  
    auto &nr_ctx
--- 270,277 ----
        context->insert_type (param.get_mappings (), param_tyty);
        TypeCheckPattern::Resolve (param.get_param_name (), param_tyty);
        // FIXME: Should we take the name ? Use a shared pointer instead ?
!       params.emplace_back (param.get_param_name ().clone_pattern (),
! 			   param_tyty);
      }
  
    auto &nr_ctx
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-substitution-mapper.cc gcc-16-20251102/gcc/rust/typecheck/rust-substitution-mapper.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-substitution-mapper.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-substitution-mapper.cc	Sun Nov  2 22:32:23 2025
*************** SubstMapperInternal::visit (TyTy::ParamT
*** 268,279 ****
  }
  
  void
! SubstMapperInternal::visit (TyTy::ConstType &type)
  {
    resolved = type.handle_substitions (mappings);
  }
  
  void
  SubstMapperInternal::visit (TyTy::PlaceholderType &type)
  {
    rust_assert (type.can_resolve ());
--- 268,297 ----
  }
  
  void
! SubstMapperInternal::visit (TyTy::ConstParamType &type)
  {
    resolved = type.handle_substitions (mappings);
  }
  
  void
+ SubstMapperInternal::visit (TyTy::ConstValueType &type)
+ {
+   resolved = type.clone ();
+ }
+ 
+ void
+ SubstMapperInternal::visit (TyTy::ConstInferType &type)
+ {
+   resolved = type.clone ();
+ }
+ 
+ void
+ SubstMapperInternal::visit (TyTy::ConstErrorType &type)
+ {
+   resolved = type.clone ();
+ }
+ 
+ void
  SubstMapperInternal::visit (TyTy::PlaceholderType &type)
  {
    rust_assert (type.can_resolve ());
*************** SubstMapperInternal::visit (TyTy::SliceT
*** 310,324 ****
  {
    resolved = type.handle_substitions (mappings);
  }
- 
- // nothing to do for these
  void
! SubstMapperInternal::visit (TyTy::InferType &type)
  {
!   resolved = type.clone ();
  }
  void
! SubstMapperInternal::visit (TyTy::FnPtr &type)
  {
    resolved = type.clone ();
  }
--- 328,342 ----
  {
    resolved = type.handle_substitions (mappings);
  }
  void
! SubstMapperInternal::visit (TyTy::FnPtr &type)
  {
!   resolved = type.handle_substitions (mappings);
  }
+ 
+ // nothing to do for these
  void
! SubstMapperInternal::visit (TyTy::InferType &type)
  {
    resolved = type.clone ();
  }
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-substitution-mapper.h gcc-16-20251102/gcc/rust/typecheck/rust-substitution-mapper.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-substitution-mapper.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-substitution-mapper.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 61,67 ****
    void visit (TyTy::ReferenceType &) override { rust_unreachable (); }
    void visit (TyTy::PointerType &) override { rust_unreachable (); }
    void visit (TyTy::ParamType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstType &) override { rust_unreachable (); }
    void visit (TyTy::StrType &) override { rust_unreachable (); }
    void visit (TyTy::NeverType &) override { rust_unreachable (); }
    void visit (TyTy::DynamicObjectType &) override { rust_unreachable (); }
--- 61,70 ----
    void visit (TyTy::ReferenceType &) override { rust_unreachable (); }
    void visit (TyTy::PointerType &) override { rust_unreachable (); }
    void visit (TyTy::ParamType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstParamType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstValueType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstInferType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstErrorType &) override { rust_unreachable (); }
    void visit (TyTy::StrType &) override { rust_unreachable (); }
    void visit (TyTy::NeverType &) override { rust_unreachable (); }
    void visit (TyTy::DynamicObjectType &) override { rust_unreachable (); }
*************** public:
*** 93,99 ****
    void visit (TyTy::ReferenceType &type) override;
    void visit (TyTy::PointerType &type) override;
    void visit (TyTy::ParamType &type) override;
!   void visit (TyTy::ConstType &type) override;
    void visit (TyTy::PlaceholderType &type) override;
    void visit (TyTy::ProjectionType &type) override;
    void visit (TyTy::ClosureType &type) override;
--- 96,105 ----
    void visit (TyTy::ReferenceType &type) override;
    void visit (TyTy::PointerType &type) override;
    void visit (TyTy::ParamType &type) override;
!   void visit (TyTy::ConstParamType &type) override;
!   void visit (TyTy::ConstValueType &type) override;
!   void visit (TyTy::ConstInferType &type) override;
!   void visit (TyTy::ConstErrorType &type) override;
    void visit (TyTy::PlaceholderType &type) override;
    void visit (TyTy::ProjectionType &type) override;
    void visit (TyTy::ClosureType &type) override;
*************** public:
*** 147,159 ****
    void visit (TyTy::ReferenceType &) override { rust_unreachable (); }
    void visit (TyTy::PointerType &) override { rust_unreachable (); }
    void visit (TyTy::ParamType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstType &) override { rust_unreachable (); }
    void visit (TyTy::StrType &) override { rust_unreachable (); }
    void visit (TyTy::NeverType &) override { rust_unreachable (); }
    void visit (TyTy::PlaceholderType &) override { rust_unreachable (); }
    void visit (TyTy::ProjectionType &) override { rust_unreachable (); }
    void visit (TyTy::DynamicObjectType &) override { rust_unreachable (); }
!   void visit (TyTy::OpaqueType &type) override { rust_unreachable (); }
  
  private:
    SubstMapperFromExisting (TyTy::BaseType *concrete, TyTy::BaseType *receiver);
--- 153,168 ----
    void visit (TyTy::ReferenceType &) override { rust_unreachable (); }
    void visit (TyTy::PointerType &) override { rust_unreachable (); }
    void visit (TyTy::ParamType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstParamType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstValueType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstInferType &) override { rust_unreachable (); }
!   void visit (TyTy::ConstErrorType &) override { rust_unreachable (); }
    void visit (TyTy::StrType &) override { rust_unreachable (); }
    void visit (TyTy::NeverType &) override { rust_unreachable (); }
    void visit (TyTy::PlaceholderType &) override { rust_unreachable (); }
    void visit (TyTy::ProjectionType &) override { rust_unreachable (); }
    void visit (TyTy::DynamicObjectType &) override { rust_unreachable (); }
!   void visit (TyTy::OpaqueType &) override { rust_unreachable (); }
  
  private:
    SubstMapperFromExisting (TyTy::BaseType *concrete, TyTy::BaseType *receiver);
*************** public:
*** 188,194 ****
    void visit (const TyTy::ReferenceType &) override {}
    void visit (const TyTy::PointerType &) override {}
    void visit (const TyTy::ParamType &) override {}
!   void visit (const TyTy::ConstType &) override {}
    void visit (const TyTy::StrType &) override {}
    void visit (const TyTy::NeverType &) override {}
    void visit (const TyTy::PlaceholderType &) override {}
--- 197,206 ----
    void visit (const TyTy::ReferenceType &) override {}
    void visit (const TyTy::PointerType &) override {}
    void visit (const TyTy::ParamType &) override {}
!   void visit (const TyTy::ConstParamType &) override {}
!   void visit (const TyTy::ConstValueType &) override {}
!   void visit (const TyTy::ConstInferType &) override {}
!   void visit (const TyTy::ConstErrorType &) override {}
    void visit (const TyTy::StrType &) override {}
    void visit (const TyTy::NeverType &) override {}
    void visit (const TyTy::PlaceholderType &) override {}
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-type-util.cc gcc-16-20251102/gcc/rust/typecheck/rust-type-util.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-type-util.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-type-util.cc	Sun Nov  2 22:32:23 2025
*************** query_type (HirId reference, TyTy::BaseT
*** 152,162 ****
  
  bool
  types_compatable (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
! 		  location_t unify_locus, bool emit_errors)
  {
    TyTy::BaseType *result
      = unify_site_and (UNKNOWN_HIRID, lhs, rhs, unify_locus, emit_errors,
! 		      false /*commit*/, true /*infer*/, true /*cleanup*/);
    return result->get_kind () != TyTy::TypeKind::ERROR;
  }
  
--- 152,163 ----
  
  bool
  types_compatable (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
! 		  location_t unify_locus, bool emit_errors, bool check_bounds)
  {
    TyTy::BaseType *result
      = unify_site_and (UNKNOWN_HIRID, lhs, rhs, unify_locus, emit_errors,
! 		      false /*commit*/, true /*infer*/, true /*cleanup*/,
! 		      check_bounds);
    return result->get_kind () != TyTy::TypeKind::ERROR;
  }
  
*************** unify_site (HirId id, TyTy::TyWithLocati
*** 173,204 ****
    std::vector<UnifyRules::CommitSite> commits;
    std::vector<UnifyRules::InferenceSite> infers;
    return UnifyRules::Resolve (lhs, rhs, unify_locus, true /*commit*/,
! 			      true /*emit_error*/, false /*infer*/, commits,
! 			      infers);
  }
  
  TyTy::BaseType *
  unify_site_and (HirId id, TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  		location_t unify_locus, bool emit_errors, bool commit_if_ok,
! 		bool implicit_infer_vars, bool cleanup)
  {
    TypeCheckContext &context = *TypeCheckContext::get ();
  
    TyTy::BaseType *expected = lhs.get_ty ();
    TyTy::BaseType *expr = rhs.get_ty ();
  
!   rust_debug_loc (
!     unify_locus,
!     "begin unify_site_and commit %s infer %s id={%u} expected={%s} expr={%s}",
!     commit_if_ok ? "true" : "false", implicit_infer_vars ? "true" : "false",
!     id == UNKNOWN_HIRID ? 0 : id, expected->debug_str ().c_str (),
!     expr->debug_str ().c_str ());
  
    std::vector<UnifyRules::CommitSite> commits;
    std::vector<UnifyRules::InferenceSite> infers;
    TyTy::BaseType *result
      = UnifyRules::Resolve (lhs, rhs, unify_locus, false /*commit inline*/,
! 			   emit_errors, implicit_infer_vars, commits, infers);
    bool ok = result->get_kind () != TyTy::TypeKind::ERROR;
  
    rust_debug_loc (unify_locus,
--- 174,207 ----
    std::vector<UnifyRules::CommitSite> commits;
    std::vector<UnifyRules::InferenceSite> infers;
    return UnifyRules::Resolve (lhs, rhs, unify_locus, true /*commit*/,
! 			      true /*emit_error*/, false /*infer*/,
! 			      true /*check_bounds*/, commits, infers);
  }
  
  TyTy::BaseType *
  unify_site_and (HirId id, TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  		location_t unify_locus, bool emit_errors, bool commit_if_ok,
! 		bool implicit_infer_vars, bool cleanup, bool check_bounds)
  {
    TypeCheckContext &context = *TypeCheckContext::get ();
  
    TyTy::BaseType *expected = lhs.get_ty ();
    TyTy::BaseType *expr = rhs.get_ty ();
  
!   rust_debug_loc (unify_locus,
! 		  "begin unify_site_and commit %s infer %s check_bounds %s "
! 		  "id={%u} expected={%s} expr={%s}",
! 		  commit_if_ok ? "true" : "false",
! 		  implicit_infer_vars ? "true" : "false",
! 		  check_bounds ? "true" : "false", id == UNKNOWN_HIRID ? 0 : id,
! 		  expected->debug_str ().c_str (), expr->debug_str ().c_str ());
  
    std::vector<UnifyRules::CommitSite> commits;
    std::vector<UnifyRules::InferenceSite> infers;
    TyTy::BaseType *result
      = UnifyRules::Resolve (lhs, rhs, unify_locus, false /*commit inline*/,
! 			   emit_errors, implicit_infer_vars, check_bounds,
! 			   commits, infers);
    bool ok = result->get_kind () != TyTy::TypeKind::ERROR;
  
    rust_debug_loc (unify_locus,
*************** unify_site_and (HirId id, TyTy::TyWithLo
*** 228,234 ****
  
  	  // remove the inference variable
  	  context.clear_type (i.infer);
! 	  delete i.infer;
  	}
      }
    return result;
--- 231,238 ----
  
  	  // remove the inference variable
  	  context.clear_type (i.infer);
! 	  // FIXME: Don't delete - result might point to this
! 	  // delete i.infer;
  	}
      }
    return result;
*************** cast_site (HirId id, TyTy::TyWithLocatio
*** 325,331 ****
  
  AssociatedImplTrait *
  lookup_associated_impl_block (const TyTy::TypeBoundPredicate &bound,
! 			      const TyTy::BaseType *binding, bool *ambigious)
  {
    auto context = TypeCheckContext::get ();
  
--- 329,335 ----
  
  AssociatedImplTrait *
  lookup_associated_impl_block (const TyTy::TypeBoundPredicate &bound,
! 			      TyTy::BaseType *binding, bool *ambigious)
  {
    auto context = TypeCheckContext::get ();
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-type-util.h gcc-16-20251102/gcc/rust/typecheck/rust-type-util.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-type-util.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-type-util.h	Sun Nov  2 22:32:23 2025
*************** namespace Resolver {
*** 28,34 ****
  bool query_type (HirId reference, TyTy::BaseType **result);
  
  bool types_compatable (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
! 		       location_t unify_locus, bool emit_errors);
  
  TyTy::BaseType *unify_site (HirId id, TyTy::TyWithLocation lhs,
  			    TyTy::TyWithLocation rhs, location_t unify_locus);
--- 28,35 ----
  bool query_type (HirId reference, TyTy::BaseType **result);
  
  bool types_compatable (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
! 		       location_t unify_locus, bool emit_errors,
! 		       bool check_bounds = true);
  
  TyTy::BaseType *unify_site (HirId id, TyTy::TyWithLocation lhs,
  			    TyTy::TyWithLocation rhs, location_t unify_locus);
*************** TyTy::BaseType *unify_site_and (HirId id
*** 37,43 ****
  				TyTy::TyWithLocation rhs,
  				location_t unify_locus, bool emit_errors,
  				bool commit_if_ok, bool implicit_infer_vars,
! 				bool cleanup);
  
  TyTy::BaseType *coercion_site (HirId id, TyTy::TyWithLocation lhs,
  			       TyTy::TyWithLocation rhs,
--- 38,44 ----
  				TyTy::TyWithLocation rhs,
  				location_t unify_locus, bool emit_errors,
  				bool commit_if_ok, bool implicit_infer_vars,
! 				bool cleanup, bool check_bounds = true);
  
  TyTy::BaseType *coercion_site (HirId id, TyTy::TyWithLocation lhs,
  			       TyTy::TyWithLocation rhs,
*************** TyTy::BaseType *cast_site (HirId id, TyT
*** 52,58 ****
  
  AssociatedImplTrait *
  lookup_associated_impl_block (const TyTy::TypeBoundPredicate &bound,
! 			      const TyTy::BaseType *binding,
  			      bool *ambigious = nullptr);
  
  } // namespace Resolver
--- 53,59 ----
  
  AssociatedImplTrait *
  lookup_associated_impl_block (const TyTy::TypeBoundPredicate &bound,
! 			      TyTy::BaseType *binding,
  			      bool *ambigious = nullptr);
  
  } // namespace Resolver
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-typecheck-context.cc gcc-16-20251102/gcc/rust/typecheck/rust-typecheck-context.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-typecheck-context.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-typecheck-context.cc	Sun Nov  2 22:32:23 2025
*************** void
*** 154,160 ****
  TypeCheckContext::push_return_type (TypeCheckContextItem item,
  				    TyTy::BaseType *return_type)
  {
!   return_type_stack.push_back ({std::move (item), return_type});
  }
  
  void
--- 154,160 ----
  TypeCheckContext::push_return_type (TypeCheckContextItem item,
  				    TyTy::BaseType *return_type)
  {
!   return_type_stack.emplace_back (std::move (item), return_type);
  }
  
  void
*************** TypeCheckContext::insert_associated_impl
*** 310,316 ****
        associated_traits_to_impls[trait_id] = {};
      }
  
!   associated_traits_to_impls[trait_id].push_back ({impl_type, impl_id});
  }
  
  bool
--- 310,316 ----
        associated_traits_to_impls[trait_id] = {};
      }
  
!   associated_traits_to_impls[trait_id].emplace_back (impl_type, impl_id);
  }
  
  bool
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-bounds.cc gcc-16-20251102/gcc/rust/typecheck/rust-tyty-bounds.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-bounds.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-bounds.cc	Sun Nov  2 22:32:23 2025
***************
*** 26,37 ****
  namespace Rust {
  namespace Resolver {
  
! TypeBoundsProbe::TypeBoundsProbe (const TyTy::BaseType *receiver)
    : TypeCheckBase (), receiver (receiver)
  {}
  
  std::vector<std::pair<TraitReference *, HIR::ImplBlock *>>
! TypeBoundsProbe::Probe (const TyTy::BaseType *receiver)
  {
    TypeBoundsProbe probe (receiver);
    probe.scan ();
--- 26,37 ----
  namespace Rust {
  namespace Resolver {
  
! TypeBoundsProbe::TypeBoundsProbe (TyTy::BaseType *receiver)
    : TypeCheckBase (), receiver (receiver)
  {}
  
  std::vector<std::pair<TraitReference *, HIR::ImplBlock *>>
! TypeBoundsProbe::Probe (TyTy::BaseType *receiver)
  {
    TypeBoundsProbe probe (receiver);
    probe.scan ();
*************** TypeBoundsProbe::process_impl_block (
*** 75,96 ****
    HIR::Trait *t = TraitResolver::ResolveHirItem (impl->get_trait_ref ());
    if (t == nullptr)
      return true;
-   // DefId trait_id = t->get_mappings ().get_defid ();
-   // if (context->trait_query_in_progress (trait_id))
-   //   return true;
  
    HirId impl_ty_id = impl->get_type ().get_mappings ().get_hirid ();
    TyTy::BaseType *impl_type = nullptr;
    if (!query_type (impl_ty_id, &impl_type))
      return true;
  
!   if (!receiver->can_eq (impl_type, false))
!     {
!       if (!impl_type->can_eq (receiver, false))
! 	return true;
!     }
  
!   possible_trait_paths.push_back ({&impl->get_trait_ref (), impl});
    return true;
  }
  
--- 75,92 ----
    HIR::Trait *t = TraitResolver::ResolveHirItem (impl->get_trait_ref ());
    if (t == nullptr)
      return true;
  
    HirId impl_ty_id = impl->get_type ().get_mappings ().get_hirid ();
    TyTy::BaseType *impl_type = nullptr;
    if (!query_type (impl_ty_id, &impl_type))
      return true;
  
!   if (!types_compatable (TyTy::TyWithLocation (receiver),
! 			 TyTy::TyWithLocation (impl_type), impl->get_locus (),
! 			 false /*emit_errors*/, false /*check-bounds*/))
!     return true;
  
!   possible_trait_paths.emplace_back (&impl->get_trait_ref (), impl);
    return true;
  }
  
*************** TypeBoundsProbe::scan ()
*** 110,116 ****
        TraitReference *trait_ref = TraitResolver::Resolve (*trait_path);
  
        if (!trait_ref->is_error ())
! 	trait_references.push_back ({trait_ref, path.second});
      }
  
    // marker traits...
--- 106,112 ----
        TraitReference *trait_ref = TraitResolver::Resolve (*trait_path);
  
        if (!trait_ref->is_error ())
! 	trait_references.emplace_back (trait_ref, path.second);
      }
  
    // marker traits...
*************** TypeBoundsProbe::add_trait_bound (HIR::T
*** 185,191 ****
  {
    auto trait_ref = TraitResolver::Resolve (*trait);
  
!   trait_references.push_back ({trait_ref, mappings.lookup_builtin_marker ()});
  }
  
  void
--- 181,187 ----
  {
    auto trait_ref = TraitResolver::Resolve (*trait);
  
!   trait_references.emplace_back (trait_ref, mappings.lookup_builtin_marker ());
  }
  
  void
*************** TypeCheckBase::get_predicate_from_bound
*** 306,316 ****
  
  	std::vector<HIR::GenericArgsBinding> bindings;
  	location_t output_locus = fn.get_return_type ().get_locus ();
! 	HIR::GenericArgsBinding binding (Identifier (
! 					   trait_item->trait_identifier ()),
! 					 fn.get_return_type ().clone_type (),
! 					 output_locus);
! 	bindings.push_back (std::move (binding));
  
  	args = HIR::GenericArgs ({} /* lifetimes */,
  				 std::move (inputs) /* type_args*/,
--- 302,310 ----
  
  	std::vector<HIR::GenericArgsBinding> bindings;
  	location_t output_locus = fn.get_return_type ().get_locus ();
! 	bindings.emplace_back (Identifier (trait_item->trait_identifier ()),
! 			       fn.get_return_type ().clone_type (),
! 			       output_locus);
  
  	args = HIR::GenericArgs ({} /* lifetimes */,
  				 std::move (inputs) /* type_args*/,
*************** TypeBoundPredicate::operator= (const Typ
*** 468,475 ****
      {
        TyTy::BaseType *argument
  	= m.get_tyty () == nullptr ? nullptr : m.get_tyty ()->clone ();
!       SubstitutionArg c (&substitutions.at (i++), argument);
!       copied_arg_mappings.push_back (std::move (c));
      }
  
    used_arguments
--- 462,469 ----
      {
        TyTy::BaseType *argument
  	= m.get_tyty () == nullptr ? nullptr : m.get_tyty ()->clone ();
! 
!       copied_arg_mappings.emplace_back (&substitutions.at (i++), argument);
      }
  
    used_arguments
*************** TypeBoundPredicate::apply_argument_mappi
*** 577,586 ****
        std::string identifier = it.first;
        TyTy::BaseType *type = it.second;
  
!       TypeBoundPredicateItem item = lookup_associated_item (identifier);
!       rust_assert (!item.is_error ());
  
!       const auto item_ref = item.get_raw_item ();
        item_ref->associated_type_set (type);
      }
  
--- 571,583 ----
        std::string identifier = it.first;
        TyTy::BaseType *type = it.second;
  
!       tl::optional<TypeBoundPredicateItem> item
! 	= lookup_associated_item (identifier);
  
!       if (!item.has_value ())
! 	continue;
! 
!       const auto item_ref = item->get_raw_item ();
        item_ref->associated_type_set (type);
      }
  
*************** TypeBoundPredicate::contains_item (const
*** 601,607 ****
    return trait_ref->lookup_trait_item (search, &trait_item_ref);
  }
  
! TypeBoundPredicateItem
  TypeBoundPredicate::lookup_associated_item (const std::string &search) const
  {
    auto trait_ref = get ();
--- 598,604 ----
    return trait_ref->lookup_trait_item (search, &trait_item_ref);
  }
  
! tl::optional<TypeBoundPredicateItem>
  TypeBoundPredicate::lookup_associated_item (const std::string &search) const
  {
    auto trait_ref = get ();
*************** TypeBoundPredicate::lookup_associated_it
*** 613,623 ****
    for (auto &super_trait : super_traits)
      {
        auto lookup = super_trait.lookup_associated_item (search);
!       if (!lookup.is_error ())
  	return lookup;
      }
  
!   return TypeBoundPredicateItem::error ();
  }
  
  TypeBoundPredicateItem::TypeBoundPredicateItem (
--- 610,620 ----
    for (auto &super_trait : super_traits)
      {
        auto lookup = super_trait.lookup_associated_item (search);
!       if (lookup.has_value ())
  	return lookup;
      }
  
!   return tl::nullopt;
  }
  
  TypeBoundPredicateItem::TypeBoundPredicateItem (
*************** TypeBoundPredicateItem::get_parent () co
*** 658,664 ****
    return &parent;
  }
  
! TypeBoundPredicateItem
  TypeBoundPredicate::lookup_associated_item (
    const Resolver::TraitItemReference *ref) const
  {
--- 655,661 ----
    return &parent;
  }
  
! tl::optional<TypeBoundPredicateItem>
  TypeBoundPredicate::lookup_associated_item (
    const Resolver::TraitItemReference *ref) const
  {
*************** TypeBoundPredicateItem::get_tyty_for_rec
*** 691,698 ****
        TyTy::BaseType *argument
  	= is_implicit_self ? receiver->clone () : mapping.get_tyty ();
  
!       SubstitutionArg arg (mapping.get_param_mapping (), argument);
!       adjusted_mappings.push_back (std::move (arg));
      }
  
    SubstitutionArgumentMappings adjusted (adjusted_mappings, {},
--- 688,694 ----
        TyTy::BaseType *argument
  	= is_implicit_self ? receiver->clone () : mapping.get_tyty ();
  
!       adjusted_mappings.emplace_back (mapping.get_param_mapping (), argument);
      }
  
    SubstitutionArgumentMappings adjusted (adjusted_mappings, {},
*************** TypeBoundPredicate::handle_substitions (
*** 735,744 ****
        std::string identifier = it.first;
        TyTy::BaseType *type = it.second;
  
!       TypeBoundPredicateItem item = lookup_associated_item (identifier);
!       if (!item.is_error ())
  	{
! 	  const auto item_ref = item.get_raw_item ();
  	  item_ref->associated_type_set (type);
  	}
      }
--- 731,741 ----
        std::string identifier = it.first;
        TyTy::BaseType *type = it.second;
  
!       tl::optional<TypeBoundPredicateItem> item
! 	= lookup_associated_item (identifier);
!       if (item.has_value ())
  	{
! 	  const auto item_ref = item->get_raw_item ();
  	  item_ref->associated_type_set (type);
  	}
      }
*************** TypeBoundPredicate::get_trait_hierachy (
*** 802,819 ****
  TypeBoundPredicateItem
  TypeBoundPredicate::lookup_associated_type (const std::string &search)
  {
!   TypeBoundPredicateItem item = lookup_associated_item (search);
  
    // only need to check that it is infact an associated type because other
    // wise if it was not found it will just be an error node anyway
!   if (!item.is_error ())
      {
!       const auto raw = item.get_raw_item ();
        if (raw->get_trait_item_type ()
  	  != Resolver::TraitItemReference::TraitItemType::TYPE)
  	return TypeBoundPredicateItem::error ();
      }
!   return item;
  }
  
  std::vector<TypeBoundPredicateItem>
--- 799,816 ----
  TypeBoundPredicateItem
  TypeBoundPredicate::lookup_associated_type (const std::string &search)
  {
!   tl::optional<TypeBoundPredicateItem> item = lookup_associated_item (search);
  
    // only need to check that it is infact an associated type because other
    // wise if it was not found it will just be an error node anyway
!   if (item.has_value ())
      {
!       const auto raw = item->get_raw_item ();
        if (raw->get_trait_item_type ()
  	  != Resolver::TraitItemReference::TraitItemType::TYPE)
  	return TypeBoundPredicateItem::error ();
      }
!   return item.value ();
  }
  
  std::vector<TypeBoundPredicateItem>
*************** TypeBoundPredicate::get_associated_type_
*** 827,836 ****
  	= trait_item.get_trait_item_type ()
  	  == Resolver::TraitItemReference::TraitItemType::TYPE;
        if (is_associated_type)
! 	{
! 	  TypeBoundPredicateItem item (*this, &trait_item);
! 	  items.push_back (std::move (item));
! 	}
      }
    return items;
  }
--- 824,830 ----
  	= trait_item.get_trait_item_type ()
  	  == Resolver::TraitItemReference::TraitItemType::TYPE;
        if (is_associated_type)
! 	items.emplace_back (*this, &trait_item);
      }
    return items;
  }
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-call.cc gcc-16-20251102/gcc/rust/typecheck/rust-tyty-call.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-call.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-call.cc	Sun Nov  2 22:32:23 2025
*************** TypeCheckCallExpr::visit (ADTType &type)
*** 59,65 ****
    if (variant.get_variant_type () != TyTy::VariantDef::VariantType::TUPLE)
      {
        rust_error_at (
! 	call.get_locus (), ErrorCode::E0423,
  	"expected function, tuple struct or tuple variant, found struct %qs",
  	type.get_name ().c_str ());
        return;
--- 59,65 ----
    if (variant.get_variant_type () != TyTy::VariantDef::VariantType::TUPLE)
      {
        rust_error_at (
! 	call.get_locus (), ErrorCode::E0618,
  	"expected function, tuple struct or tuple variant, found struct %qs",
  	type.get_name ().c_str ());
        return;
*************** TypeCheckMethodCallExpr::go (FnType *ref
*** 327,334 ****
  	  return new ErrorType (ref->get_ref ());
  	}
  
!       Argument a (arg->get_mappings (), argument_expr_tyty, arg->get_locus ());
!       args.push_back (std::move (a));
      }
  
    TypeCheckMethodCallExpr checker (call.get_mappings (), args,
--- 327,334 ----
  	  return new ErrorType (ref->get_ref ());
  	}
  
!       args.emplace_back (arg->get_mappings (), argument_expr_tyty,
! 			 arg->get_locus ());
      }
  
    TypeCheckMethodCallExpr checker (call.get_mappings (), args,
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-call.h gcc-16-20251102/gcc/rust/typecheck/rust-tyty-call.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-call.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-call.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 60,68 ****
    void visit (PlaceholderType &) override { rust_unreachable (); }
    void visit (ProjectionType &) override { rust_unreachable (); }
    void visit (DynamicObjectType &) override { rust_unreachable (); }
!   void visit (ClosureType &type) override { rust_unreachable (); }
!   void visit (OpaqueType &type) override { rust_unreachable (); }
!   void visit (ConstType &type) override { rust_unreachable (); }
  
    // tuple-structs
    void visit (ADTType &type) override;
--- 60,71 ----
    void visit (PlaceholderType &) override { rust_unreachable (); }
    void visit (ProjectionType &) override { rust_unreachable (); }
    void visit (DynamicObjectType &) override { rust_unreachable (); }
!   void visit (ClosureType &) override { rust_unreachable (); }
!   void visit (OpaqueType &) override { rust_unreachable (); }
!   void visit (ConstParamType &) override { rust_unreachable (); }
!   void visit (ConstValueType &) override { rust_unreachable (); }
!   void visit (ConstInferType &) override { rust_unreachable (); }
!   void visit (ConstErrorType &) override { rust_unreachable (); }
  
    // tuple-structs
    void visit (ADTType &type) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-cmp.h gcc-16-20251102/gcc/rust/typecheck/rust-tyty-cmp.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-cmp.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-cmp.h	Thu Jan  1 00:00:00 1970
***************
*** 1,1645 ****
- // Copyright (C) 2020-2025 Free Software Foundation, Inc.
- 
- // This file is part of GCC.
- 
- // GCC is free software; you can redistribute it and/or modify it under
- // the terms of the GNU General Public License as published by the Free
- // Software Foundation; either version 3, or (at your option) any later
- // version.
- 
- // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- // WARRANTY; without even the implied warranty of MERCHANTABILITY or
- // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- // for more details.
- 
- // You should have received a copy of the GNU General Public License
- // along with GCC; see the file COPYING3.  If not see
- // <http://www.gnu.org/licenses/>.
- 
- #ifndef RUST_TYTY_CMP_H
- #define RUST_TYTY_CMP_H
- 
- #include "rust-diagnostics.h"
- #include "rust-tyty.h"
- #include "rust-tyty-visitor.h"
- #include "rust-hir-map.h"
- #include "rust-hir-type-check.h"
- 
- namespace Rust {
- namespace TyTy {
- 
- class BaseCmp : public TyConstVisitor
- {
- public:
-   virtual bool can_eq (const BaseType *other)
-   {
-     if (other->get_kind () == TypeKind::PARAM)
-       {
- 	const ParamType *p = static_cast<const ParamType *> (other);
- 	other = p->resolve ();
-       }
-     if (other->get_kind () == TypeKind::PLACEHOLDER)
-       {
- 	const PlaceholderType *p = static_cast<const PlaceholderType *> (other);
- 	if (p->can_resolve ())
- 	  {
- 	    other = p->resolve ();
- 	  }
-       }
-     if (other->get_kind () == TypeKind::PROJECTION)
-       {
- 	const ProjectionType *p = static_cast<const ProjectionType *> (other);
- 	other = p->get ();
-       }
- 
-     other->accept_vis (*this);
-     return ok;
-   }
- 
-   virtual void visit (const TupleType &type) override
-   {
-     ok = false;
- 
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ADTType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const InferType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const FnType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const FnPtr &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ArrayType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const SliceType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const BoolType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const IntType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const UintType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const USizeType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ISizeType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const FloatType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ErrorType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const CharType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ReferenceType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const PointerType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const StrType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const NeverType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ProjectionType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const PlaceholderType &type) override
-   {
-     // it is ok for types to can eq to a placeholder
-     ok = true;
-   }
- 
-   virtual void visit (const ParamType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const DynamicObjectType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ClosureType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const OpaqueType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
-   virtual void visit (const ConstType &type) override
-   {
-     ok = false;
-     if (emit_error_flag)
-       {
- 	location_t ref_locus = mappings.lookup_location (type.get_ref ());
- 	location_t base_locus
- 	  = mappings.lookup_location (get_base ()->get_ref ());
- 	rich_location r (line_table, ref_locus);
- 	r.add_range (base_locus);
- 	rust_error_at (r, "expected [%s] got [%s]",
- 		       get_base ()->as_string ().c_str (),
- 		       type.as_string ().c_str ());
-       }
-   }
- 
- protected:
-   BaseCmp (const BaseType *base, bool emit_errors)
-     : mappings (Analysis::Mappings::get ()),
-       context (Resolver::TypeCheckContext::get ()), ok (false),
-       emit_error_flag (emit_errors)
-   {}
- 
-   Analysis::Mappings &mappings;
-   Resolver::TypeCheckContext *context;
- 
-   bool ok;
-   bool emit_error_flag;
- 
- private:
-   /* Returns a pointer to the ty that created this rule. */
-   virtual const BaseType *get_base () const = 0;
- };
- 
- class InferCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   InferCmp (const InferType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const BoolType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const IntType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL)
- 	|| (base->get_infer_kind ()
- 	    == TyTy::InferType::InferTypeKind::INTEGRAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const UintType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL)
- 	|| (base->get_infer_kind ()
- 	    == TyTy::InferType::InferTypeKind::INTEGRAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const USizeType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL)
- 	|| (base->get_infer_kind ()
- 	    == TyTy::InferType::InferTypeKind::INTEGRAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const ISizeType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL)
- 	|| (base->get_infer_kind ()
- 	    == TyTy::InferType::InferTypeKind::INTEGRAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const FloatType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL)
- 	|| (base->get_infer_kind () == TyTy::InferType::InferTypeKind::FLOAT);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const ArrayType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const SliceType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const ADTType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const TupleType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const InferType &type) override
-   {
-     switch (base->get_infer_kind ())
-       {
-       case InferType::InferTypeKind::GENERAL:
- 	ok = true;
- 	return;
- 
-       case InferType::InferTypeKind::INTEGRAL:
- 	{
- 	  if (type.get_infer_kind () == InferType::InferTypeKind::INTEGRAL)
- 	    {
- 	      ok = true;
- 	      return;
- 	    }
- 	  else if (type.get_infer_kind () == InferType::InferTypeKind::GENERAL)
- 	    {
- 	      ok = true;
- 	      return;
- 	    }
- 	}
- 	break;
- 
-       case InferType::InferTypeKind::FLOAT:
- 	{
- 	  if (type.get_infer_kind () == InferType::InferTypeKind::FLOAT)
- 	    {
- 	      ok = true;
- 	      return;
- 	    }
- 	  else if (type.get_infer_kind () == InferType::InferTypeKind::GENERAL)
- 	    {
- 	      ok = true;
- 	      return;
- 	    }
- 	}
- 	break;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const CharType &type) override
-   {
-     {
-       bool is_valid
- 	= (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-       if (is_valid)
- 	{
- 	  ok = true;
- 	  return;
- 	}
- 
-       BaseCmp::visit (type);
-     }
-   }
- 
-   void visit (const ReferenceType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const PointerType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const ParamType &) override { ok = true; }
- 
-   void visit (const DynamicObjectType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
-   void visit (const ClosureType &type) override
-   {
-     bool is_valid
-       = (base->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL);
-     if (is_valid)
-       {
- 	ok = true;
- 	return;
-       }
- 
-     BaseCmp::visit (type);
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const InferType *base;
- };
- 
- class FnCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   FnCmp (const FnType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () == InferType::InferTypeKind::GENERAL;
-   }
- 
-   void visit (const FnType &type) override
-   {
-     if (base->num_params () != type.num_params ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     for (size_t i = 0; i < base->num_params (); i++)
-       {
- 	auto a = base->param_at (i).get_type ();
- 	auto b = type.param_at (i).get_type ();
- 
- 	if (!a->can_eq (b, emit_error_flag))
- 	  {
- 	    emit_error_flag = false;
- 	    BaseCmp::visit (type);
- 	    return;
- 	  }
-       }
- 
-     if (!base->get_return_type ()->can_eq (type.get_return_type (),
- 					   emit_error_flag))
-       {
- 	emit_error_flag = false;
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const FnType *base;
- };
- 
- class FnptrCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   FnptrCmp (const FnPtr *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const FnPtr &type) override
-   {
-     if (base->num_params () != type.num_params ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     auto this_ret_type = base->get_return_type ();
-     auto other_ret_type = type.get_return_type ();
-     if (!this_ret_type->can_eq (other_ret_type, emit_error_flag))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     for (size_t i = 0; i < base->num_params (); i++)
-       {
- 	auto this_param = base->get_param_type_at (i);
- 	auto other_param = type.get_param_type_at (i);
- 	if (!this_param->can_eq (other_param, emit_error_flag))
- 	  {
- 	    BaseCmp::visit (type);
- 	    return;
- 	  }
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const FnType &type) override
-   {
-     if (base->num_params () != type.num_params ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     auto this_ret_type = base->get_return_type ();
-     auto other_ret_type = type.get_return_type ();
-     if (!this_ret_type->can_eq (other_ret_type, emit_error_flag))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     for (size_t i = 0; i < base->num_params (); i++)
-       {
- 	auto this_param = base->get_param_type_at (i);
- 	auto other_param = type.param_at (i).get_type ();
- 	if (!this_param->can_eq (other_param, emit_error_flag))
- 	  {
- 	    BaseCmp::visit (type);
- 	    return;
- 	  }
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const FnPtr *base;
- };
- 
- class ClosureCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ClosureCmp (const ClosureType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const ClosureType &type) override
-   {
-     if (base->get_def_id () != type.get_def_id ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     if (!base->get_parameters ().can_eq (&type.get_parameters (), false))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     if (!base->get_result_type ().can_eq (&type.get_result_type (), false))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const ClosureType *base;
- };
- 
- class ArrayCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ArrayCmp (const ArrayType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const ArrayType &type) override
-   {
-     // check base type
-     const BaseType *base_element = base->get_element_type ();
-     const BaseType *other_element = type.get_element_type ();
-     if (!base_element->can_eq (other_element, emit_error_flag))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const ArrayType *base;
- };
- 
- class SliceCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   SliceCmp (const SliceType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const SliceType &type) override
-   {
-     // check base type
-     const BaseType *base_element = base->get_element_type ();
-     const BaseType *other_element = type.get_element_type ();
-     if (!base_element->can_eq (other_element, emit_error_flag))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const SliceType *base;
- };
- 
- class BoolCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   BoolCmp (const BoolType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const BoolType &type) override { ok = true; }
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () == InferType::InferTypeKind::GENERAL;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const BoolType *base;
- };
- 
- class IntCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   IntCmp (const IntType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () != InferType::InferTypeKind::FLOAT;
-   }
- 
-   void visit (const IntType &type) override
-   {
-     ok = type.get_int_kind () == base->get_int_kind ();
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const IntType *base;
- };
- 
- class UintCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   UintCmp (const UintType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () != InferType::InferTypeKind::FLOAT;
-   }
- 
-   void visit (const UintType &type) override
-   {
-     ok = type.get_uint_kind () == base->get_uint_kind ();
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const UintType *base;
- };
- 
- class FloatCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   FloatCmp (const FloatType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () != InferType::InferTypeKind::INTEGRAL;
-   }
- 
-   void visit (const FloatType &type) override
-   {
-     ok = type.get_float_kind () == base->get_float_kind ();
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const FloatType *base;
- };
- 
- class ADTCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ADTCmp (const ADTType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const ADTType &type) override
-   {
-     if (base->get_adt_kind () != type.get_adt_kind ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     if (base->get_identifier ().compare (type.get_identifier ()) != 0)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     if (base->number_of_variants () != type.number_of_variants ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     for (size_t i = 0; i < type.number_of_variants (); ++i)
-       {
- 	TyTy::VariantDef *a = base->get_variants ().at (i);
- 	TyTy::VariantDef *b = type.get_variants ().at (i);
- 
- 	if (a->num_fields () != b->num_fields ())
- 	  {
- 	    BaseCmp::visit (type);
- 	    return;
- 	  }
- 
- 	for (size_t j = 0; j < a->num_fields (); j++)
- 	  {
- 	    TyTy::StructFieldType *base_field = a->get_field_at_index (j);
- 	    TyTy::StructFieldType *other_field = b->get_field_at_index (j);
- 
- 	    TyTy::BaseType *this_field_ty = base_field->get_field_type ();
- 	    TyTy::BaseType *other_field_ty = other_field->get_field_type ();
- 
- 	    if (!this_field_ty->can_eq (other_field_ty, emit_error_flag))
- 	      {
- 		BaseCmp::visit (type);
- 		return;
- 	      }
- 	  }
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const ADTType *base;
- };
- 
- class TupleCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   TupleCmp (const TupleType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const TupleType &type) override
-   {
-     if (base->num_fields () != type.num_fields ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     for (size_t i = 0; i < base->num_fields (); i++)
-       {
- 	BaseType *bo = base->get_field (i);
- 	BaseType *fo = type.get_field (i);
- 
- 	if (!bo->can_eq (fo, emit_error_flag))
- 	  {
- 	    BaseCmp::visit (type);
- 	    return;
- 	  }
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const TupleType *base;
- };
- 
- class USizeCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   USizeCmp (const USizeType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () != InferType::InferTypeKind::FLOAT;
-   }
- 
-   void visit (const USizeType &type) override { ok = true; }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const USizeType *base;
- };
- 
- class ISizeCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ISizeCmp (const ISizeType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () != InferType::InferTypeKind::FLOAT;
-   }
- 
-   void visit (const ISizeType &type) override { ok = true; }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const ISizeType *base;
- };
- 
- class CharCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   CharCmp (const CharType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const InferType &type) override
-   {
-     ok = type.get_infer_kind () == InferType::InferTypeKind::GENERAL;
-   }
- 
-   void visit (const CharType &type) override { ok = true; }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const CharType *base;
- };
- 
- class ReferenceCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ReferenceCmp (const ReferenceType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const ReferenceType &type) override
-   {
-     auto base_type = base->get_base ();
-     auto other_base_type = type.get_base ();
- 
-     bool mutability_ok = base->is_mutable () ? type.is_mutable () : true;
-     if (!mutability_ok)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     if (!base_type->can_eq (other_base_type, emit_error_flag))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const ReferenceType *base;
- };
- 
- class PointerCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   PointerCmp (const PointerType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const PointerType &type) override
-   {
-     auto base_type = base->get_base ();
-     auto other_base_type = type.get_base ();
- 
-     bool mutability_ok = base->is_mutable () ? type.is_mutable () : true;
-     if (!mutability_ok)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     if (!base_type->can_eq (other_base_type, emit_error_flag))
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const PointerType *base;
- };
- 
- class ParamCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ParamCmp (const ParamType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   // param types are a placeholder we shouldn't have cases where we unify
-   // against it. eg: struct foo<T> { a: T }; When we invoke it we can do either:
-   //
-   // foo<i32>{ a: 123 }.
-   // Then this enforces the i32 type to be referenced on the
-   // field via an hirid.
-   //
-   // rust also allows for a = foo{a:123}; Where we can use an Inference Variable
-   // to handle the typing of the struct
-   bool can_eq (const BaseType *other) override
-   {
-     if (!base->can_resolve ())
-       return BaseCmp::can_eq (other);
- 
-     auto lookup = base->resolve ();
-     return lookup->can_eq (other, emit_error_flag);
-   }
- 
-   // imagine the case where we have:
-   // struct Foo<T>(T);
-   // Then we declare a generic impl block
-   // impl <X>Foo<X> { ... }
-   // both of these types are compatible so we mostly care about the number of
-   // generic arguments
-   void visit (const ParamType &) override { ok = true; }
- 
-   void visit (const TupleType &) override { ok = true; }
- 
-   void visit (const InferType &) override { ok = true; }
- 
-   void visit (const FnType &) override { ok = true; }
- 
-   void visit (const FnPtr &) override { ok = true; }
- 
-   void visit (const ADTType &) override { ok = true; }
- 
-   void visit (const ArrayType &) override { ok = true; }
- 
-   void visit (const SliceType &) override { ok = true; }
- 
-   void visit (const BoolType &) override { ok = true; }
- 
-   void visit (const IntType &) override { ok = true; }
- 
-   void visit (const UintType &) override { ok = true; }
- 
-   void visit (const USizeType &) override { ok = true; }
- 
-   void visit (const ISizeType &) override { ok = true; }
- 
-   void visit (const FloatType &) override { ok = true; }
- 
-   void visit (const CharType &) override { ok = true; }
- 
-   void visit (const ReferenceType &) override { ok = true; }
- 
-   void visit (const PointerType &) override { ok = true; }
- 
-   void visit (const StrType &) override { ok = true; }
- 
-   void visit (const NeverType &) override { ok = true; }
- 
-   void visit (const DynamicObjectType &) override { ok = true; }
- 
-   void visit (const PlaceholderType &type) override
-   {
-     ok = base->get_symbol ().compare (type.get_symbol ()) == 0;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const ParamType *base;
- };
- 
- class StrCmp : public BaseCmp
- {
-   // FIXME we will need a enum for the StrType like ByteBuf etc..
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   StrCmp (const StrType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const StrType &type) override { ok = true; }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const StrType *base;
- };
- 
- class NeverCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   NeverCmp (const NeverType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const NeverType &type) override { ok = true; }
- 
-   void visit (const InferType &type) override
-   {
-     if (type.get_infer_kind () != InferType::InferTypeKind::GENERAL)
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     ok = true;
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
-   const NeverType *base;
- };
- 
- class PlaceholderCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   PlaceholderCmp (const PlaceholderType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   bool can_eq (const BaseType *other) override
-   {
-     if (!base->can_resolve ())
-       return BaseCmp::can_eq (other);
- 
-     BaseType *lookup = base->resolve ();
-     return lookup->can_eq (other, emit_error_flag);
-   }
- 
-   void visit (const TupleType &) override { ok = true; }
- 
-   void visit (const ADTType &) override { ok = true; }
- 
-   void visit (const InferType &) override { ok = true; }
- 
-   void visit (const FnType &) override { ok = true; }
- 
-   void visit (const FnPtr &) override { ok = true; }
- 
-   void visit (const ArrayType &) override { ok = true; }
- 
-   void visit (const BoolType &) override { ok = true; }
- 
-   void visit (const IntType &) override { ok = true; }
- 
-   void visit (const UintType &) override { ok = true; }
- 
-   void visit (const USizeType &) override { ok = true; }
- 
-   void visit (const ISizeType &) override { ok = true; }
- 
-   void visit (const FloatType &) override { ok = true; }
- 
-   void visit (const ErrorType &) override { ok = true; }
- 
-   void visit (const CharType &) override { ok = true; }
- 
-   void visit (const ReferenceType &) override { ok = true; }
- 
-   void visit (const ParamType &) override { ok = true; }
- 
-   void visit (const StrType &) override { ok = true; }
- 
-   void visit (const NeverType &) override { ok = true; }
- 
-   void visit (const SliceType &) override { ok = true; }
- 
- private:
-   const BaseType *get_base () const override { return base; }
- 
-   const PlaceholderType *base;
- };
- 
- class DynamicCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   DynamicCmp (const DynamicObjectType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   void visit (const DynamicObjectType &type) override
-   {
-     if (base->num_specified_bounds () != type.num_specified_bounds ())
-       {
- 	BaseCmp::visit (type);
- 	return;
-       }
- 
-     location_t ref_locus = mappings.lookup_location (type.get_ref ());
-     ok = base->bounds_compatible (type, ref_locus, false);
-   }
- 
- private:
-   const BaseType *get_base () const override { return base; }
- 
-   const DynamicObjectType *base;
- };
- 
- class OpaqueCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   OpaqueCmp (const OpaqueType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   // TODO
- 
- private:
-   const BaseType *get_base () const override { return base; }
- 
-   const OpaqueType *base;
- };
- 
- class ConstCmp : public BaseCmp
- {
-   using Rust::TyTy::BaseCmp::visit;
- 
- public:
-   ConstCmp (const ConstType *base, bool emit_errors)
-     : BaseCmp (base, emit_errors), base (base)
-   {}
- 
-   // TODO
- 
- private:
-   const BaseType *get_base () const override { return base; }
- 
-   const ConstType *base;
- };
- 
- } // namespace TyTy
- } // namespace Rust
- 
- #endif // RUST_TYTY_CMP_H
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-subst.cc gcc-16-20251102/gcc/rust/typecheck/rust-tyty-subst.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-subst.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-subst.cc	Sun Nov  2 22:32:23 2025
*************** SubstitutionParamMapping::as_string () c
*** 54,61 ****
  SubstitutionParamMapping
  SubstitutionParamMapping::clone () const
  {
!   return SubstitutionParamMapping (generic,
! 				   static_cast<ParamType *> (param->clone ()));
  }
  
  BaseGeneric *
--- 54,61 ----
  SubstitutionParamMapping
  SubstitutionParamMapping::clone () const
  {
!   return SubstitutionParamMapping (generic, static_cast<BaseGeneric *> (
! 					      param->clone ()));
  }
  
  BaseGeneric *
*************** SubstitutionParamMapping::fill_param_ty
*** 167,173 ****
      }
    else if (type.get_kind () == TyTy::TypeKind::CONST)
      {
!       param = static_cast<BaseGeneric *> (type.clone ());
      }
    else if (param->get_kind () == TypeKind::PARAM)
      {
--- 167,178 ----
      }
    else if (type.get_kind () == TyTy::TypeKind::CONST)
      {
!       rust_assert (param->get_kind () == TyTy::TypeKind::CONST);
!       auto *const_type = type.as_const_type ();
!       if (const_type->const_kind () == TyTy::BaseConstType::ConstKind::Decl)
! 	param = static_cast<BaseGeneric *> (type.clone ());
!       else
! 	param->set_ty_ref (type.get_ref ());
      }
    else if (param->get_kind () == TypeKind::PARAM)
      {
*************** std::vector<SubstitutionParamMapping>
*** 554,559 ****
--- 559,565 ----
  SubstitutionRef::clone_substs () const
  {
    std::vector<SubstitutionParamMapping> clone;
+   clone.reserve (substitutions.size ());
  
    for (auto &sub : substitutions)
      clone.push_back (sub.clone ());
*************** SubstitutionRef::get_mappings_from_gener
*** 767,773 ****
  	}
        else if (generic.get_kind () == HIR::GenericParam::GenericKind::CONST)
  	{
! 	  if (!resolved->is<ConstType> ())
  	    {
  	      rich_location r (line_table, arg->get_locus ());
  	      r.add_fixit_remove (arg->get_locus ());
--- 773,779 ----
  	}
        else if (generic.get_kind () == HIR::GenericParam::GenericKind::CONST)
  	{
! 	  if (resolved->get_kind () != TyTy::TypeKind::CONST)
  	    {
  	      rich_location r (line_table, arg->get_locus ());
  	      r.add_fixit_remove (arg->get_locus ());
*************** SubstitutionRef::get_mappings_from_gener
*** 777,785 ****
  	    }
  	}
  
!       SubstitutionArg subst_arg (&param_mapping, resolved);
        offs++;
-       mappings.push_back (std::move (subst_arg));
      }
  
    for (auto &arg : args.get_const_args ())
--- 783,790 ----
  	    }
  	}
  
!       mappings.emplace_back (&param_mapping, resolved);
        offs++;
      }
  
    for (auto &arg : args.get_const_args ())
*************** SubstitutionRef::get_mappings_from_gener
*** 802,841 ****
  
        // get the const generic specified type
        const auto base_generic = param_mapping.get_param_ty ();
!       rust_assert (base_generic->is<ConstType> ());
        const auto const_param
! 	= static_cast<const TyTy::ConstType *> (base_generic);
!       auto specified_type = const_param->get_ty ();
  
        // validate this const generic is of the correct type
!       auto coereced_type
! 	= Resolver::coercion_site (expr.get_mappings ().get_hirid (),
! 				   TyTy::TyWithLocation (specified_type),
! 				   TyTy::TyWithLocation (expr_type,
! 							 expr.get_locus ()),
! 				   arg.get_locus ());
!       if (coereced_type->is<ErrorType> ())
  	return SubstitutionArgumentMappings::error ();
  
!       // const fold it
!       auto ctx = Compile::Context::get ();
!       tree folded
! 	= Compile::HIRCompileBase::query_compile_const_expr (ctx, coereced_type,
! 							     expr);
  
!       if (folded == error_mark_node)
! 	return SubstitutionArgumentMappings::error ();
  
!       // create const type
!       auto const_value
! 	= new TyTy::ConstType (TyTy::ConstType::ConstKind::Value, "",
! 			       coereced_type, folded, {}, expr.get_locus (),
! 			       expr.get_mappings ().get_hirid (),
! 			       expr.get_mappings ().get_hirid (), {});
  
!       SubstitutionArg subst_arg (&param_mapping, const_value);
        offs++;
-       mappings.push_back (std::move (subst_arg));
      }
  
    // we must need to fill out defaults
--- 807,879 ----
  
        // get the const generic specified type
        const auto base_generic = param_mapping.get_param_ty ();
!       rust_assert (base_generic->get_kind () == TyTy::TypeKind::CONST);
        const auto const_param
! 	= static_cast<const TyTy::ConstParamType *> (base_generic);
!       auto specified_type = const_param->get_specified_type ();
  
        // validate this const generic is of the correct type
!       TyTy::BaseType *coereced_type = nullptr;
!       if (expr_type->get_kind () == TyTy::TypeKind::CONST)
! 	{
! 	  auto const_expr_type = expr_type->as_const_type ();
! 	  auto const_value_type = const_expr_type->get_specified_type ();
! 	  coereced_type
! 	    = Resolver::coercion_site (expr.get_mappings ().get_hirid (),
! 				       TyTy::TyWithLocation (specified_type),
! 				       TyTy::TyWithLocation (const_value_type,
! 							     expr.get_locus ()),
! 				       arg.get_locus ());
! 	}
!       else
! 	{
! 	  coereced_type
! 	    = Resolver::coercion_site (expr.get_mappings ().get_hirid (),
! 				       TyTy::TyWithLocation (specified_type),
! 				       TyTy::TyWithLocation (expr_type,
! 							     expr.get_locus ()),
! 				       arg.get_locus ());
! 	}
! 
!       if (coereced_type == nullptr || coereced_type->is<ErrorType> ())
  	return SubstitutionArgumentMappings::error ();
  
!       TyTy::BaseType *const_value_ty = nullptr;
!       if (expr_type->get_kind () == TyTy::TypeKind::CONST)
! 	const_value_ty = expr_type;
!       else
! 	{
! 	  // const fold it if available
! 	  auto ctx = Compile::Context::get ();
! 	  tree folded
! 	    = Compile::HIRCompileBase::query_compile_const_expr (ctx,
! 								 coereced_type,
! 								 expr);
  
! 	  if (folded == error_mark_node)
! 	    {
! 	      rich_location r (line_table, arg.get_locus ());
! 	      r.add_range (expr.get_locus ());
! 	      rust_error_at (r, "failed to resolve const expression");
! 	      return SubstitutionArgumentMappings::error ();
! 	    }
  
! 	  // Use a fresh HirId to avoid conflicts with the expr's type
! 	  auto &global_mappings = Analysis::Mappings::get ();
! 	  HirId const_value_id = global_mappings.get_next_hir_id ();
! 	  const_value_ty
! 	    = new TyTy::ConstValueType (folded, coereced_type, const_value_id,
! 					const_value_id, {});
  
! 	  // Insert the ConstValueType into the context so it can be looked up
! 	  auto context = Resolver::TypeCheckContext::get ();
! 	  context->insert_type (
! 	    Analysis::NodeMapping (0, 0, const_value_ty->get_ref (), 0),
! 	    const_value_ty);
! 	}
! 
!       mappings.emplace_back (&param_mapping, const_value_ty);
        offs++;
      }
  
    // we must need to fill out defaults
*************** SubstitutionRef::get_mappings_from_gener
*** 865,872 ****
  		return SubstitutionArgumentMappings::error ();
  	    }
  
! 	  SubstitutionArg subst_arg (&param, resolved);
! 	  mappings.push_back (std::move (subst_arg));
  	}
      }
  
--- 903,909 ----
  		return SubstitutionArgumentMappings::error ();
  	    }
  
! 	  mappings.emplace_back (&param, resolved);
  	}
      }
  
*************** SubstitutionRef::infer_substitions (loca
*** 892,921 ****
  
  	  if (have_mapping)
  	    {
! 	      args.push_back (SubstitutionArg (&p, it->second));
  	    }
  	  else if (generic.get_kind () == HIR::GenericParam::GenericKind::TYPE)
  	    {
  	      TyVar infer_var = TyVar::get_implicit_infer_var (locus);
! 	      args.push_back (SubstitutionArg (&p, infer_var.get_tyty ()));
  	      argument_mappings[symbol] = infer_var.get_tyty ();
  	    }
  	  else if (generic.get_kind () == HIR::GenericParam::GenericKind::CONST)
  	    {
! 	      const auto const_param = p.get_param_ty ();
! 	      rust_assert (const_param->is<TyTy::ConstType> ());
! 	      const auto &const_type
! 		= *static_cast<const TyTy::ConstType *> (const_param);
! 
! 	      TyVar infer_var
! 		= TyVar::get_implicit_const_infer_var (const_type, locus);
! 	      args.push_back (SubstitutionArg (&p, infer_var.get_tyty ()));
  	      argument_mappings[symbol] = infer_var.get_tyty ();
  	    }
  	}
        else
  	{
! 	  args.push_back (SubstitutionArg (&p, p.get_param_ty ()->resolve ()));
  	}
      }
  
--- 929,952 ----
  
  	  if (have_mapping)
  	    {
! 	      args.emplace_back (&p, it->second);
  	    }
  	  else if (generic.get_kind () == HIR::GenericParam::GenericKind::TYPE)
  	    {
  	      TyVar infer_var = TyVar::get_implicit_infer_var (locus);
! 	      args.emplace_back (&p, infer_var.get_tyty ());
  	      argument_mappings[symbol] = infer_var.get_tyty ();
  	    }
  	  else if (generic.get_kind () == HIR::GenericParam::GenericKind::CONST)
  	    {
! 	      TyVar infer_var = TyVar::get_implicit_const_infer_var (locus);
! 	      args.emplace_back (&p, infer_var.get_tyty ());
  	      argument_mappings[symbol] = infer_var.get_tyty ();
  	    }
  	}
        else
  	{
! 	  args.emplace_back (&p, p.get_param_ty ()->resolve ());
  	}
      }
  
*************** SubstitutionRef::adjust_mappings_for_thi
*** 961,970 ****
  
        bool ok = !arg.is_error ();
        if (ok || (trait_mode && i == 0))
! 	{
! 	  SubstitutionArg adjusted (&subst, arg.get_tyty ());
! 	  resolved_mappings.push_back (std::move (adjusted));
! 	}
      }
  
    if (resolved_mappings.empty ())
--- 992,998 ----
  
        bool ok = !arg.is_error ();
        if (ok || (trait_mode && i == 0))
! 	resolved_mappings.emplace_back (&subst, arg.get_tyty ());
      }
  
    if (resolved_mappings.empty ())
*************** SubstitutionRef::are_mappings_bound (Sub
*** 1008,1017 ****
  
        bool ok = !arg.is_error ();
        if (ok)
! 	{
! 	  SubstitutionArg adjusted (&subst, arg.get_tyty ());
! 	  resolved_mappings.push_back (std::move (adjusted));
! 	}
      }
  
    return !resolved_mappings.empty ();
--- 1036,1042 ----
  
        bool ok = !arg.is_error ();
        if (ok)
! 	resolved_mappings.emplace_back (&subst, arg.get_tyty ());
      }
  
    return !resolved_mappings.empty ();
*************** SubstitutionRef::solve_mappings_from_rec
*** 1032,1041 ****
        SubstitutionArg &arg = mappings.get_mappings ().at (i);
  
        if (param_mapping.needs_substitution ())
! 	{
! 	  SubstitutionArg adjusted (&param_mapping, arg.get_tyty ());
! 	  resolved_mappings.push_back (std::move (adjusted));
! 	}
      }
  
    return SubstitutionArgumentMappings (resolved_mappings,
--- 1057,1063 ----
        SubstitutionArg &arg = mappings.get_mappings ().at (i);
  
        if (param_mapping.needs_substitution ())
! 	resolved_mappings.emplace_back (&param_mapping, arg.get_tyty ());
      }
  
    return SubstitutionArgumentMappings (resolved_mappings,
*************** SubstitutionRef::monomorphize ()
*** 1067,1073 ****
        if (!pty->can_resolve ())
  	continue;
  
!       const TyTy::BaseType *binding = pty->resolve ();
        if (binding->get_kind () == TyTy::TypeKind::PARAM)
  	continue;
  
--- 1089,1095 ----
        if (!pty->can_resolve ())
  	continue;
  
!       TyTy::BaseType *binding = pty->resolve ();
        if (binding->get_kind () == TyTy::TypeKind::PARAM)
  	continue;
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-util.cc gcc-16-20251102/gcc/rust/typecheck/rust-tyty-util.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-util.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-util.cc	Sun Nov  2 22:32:23 2025
*************** TyVar::TyVar (HirId ref) : ref (ref)
*** 30,36 ****
    auto context = Resolver::TypeCheckContext::get ();
    BaseType *lookup = nullptr;
    bool ok = context->lookup_type (ref, &lookup);
!   rust_assert (ok);
  }
  
  BaseType *
--- 30,37 ----
    auto context = Resolver::TypeCheckContext::get ();
    BaseType *lookup = nullptr;
    bool ok = context->lookup_type (ref, &lookup);
!   if (!ok || lookup == nullptr || lookup->get_kind () == TypeKind::ERROR)
!     return;
  }
  
  BaseType *
*************** TyVar::get_tyty () const
*** 39,45 ****
    auto context = Resolver::TypeCheckContext::get ();
    BaseType *lookup = nullptr;
    bool ok = context->lookup_type (ref, &lookup);
!   rust_assert (ok);
    return lookup;
  }
  
--- 40,47 ----
    auto context = Resolver::TypeCheckContext::get ();
    BaseType *lookup = nullptr;
    bool ok = context->lookup_type (ref, &lookup);
!   if (!ok || lookup == nullptr)
!     return nullptr;
    return lookup;
  }
  
*************** TyVar::get_implicit_infer_var (location_
*** 60,76 ****
  }
  
  TyVar
! TyVar::get_implicit_const_infer_var (const ConstType &const_type,
! 				     location_t locus)
  {
    auto &mappings = Analysis::Mappings::get ();
    auto context = Resolver::TypeCheckContext::get ();
  
    HirId next = mappings.get_next_hir_id ();
!   auto infer
!     = new ConstType (ConstType::ConstKind::Infer, const_type.get_symbol (),
! 		     const_type.get_ty (), error_mark_node,
! 		     const_type.get_specified_bounds (), locus, next, next, {});
  
    context->insert_implicit_type (infer->get_ref (), infer);
    mappings.insert_location (infer->get_ref (), locus);
--- 62,75 ----
  }
  
  TyVar
! TyVar::get_implicit_const_infer_var (location_t locus)
  {
    auto &mappings = Analysis::Mappings::get ();
    auto context = Resolver::TypeCheckContext::get ();
  
+   TyVar ty_infer = get_implicit_infer_var (locus);
    HirId next = mappings.get_next_hir_id ();
!   auto infer = new ConstInferType (ty_infer.get_tyty (), next, next, {});
  
    context->insert_implicit_type (infer->get_ref (), infer);
    mappings.insert_location (infer->get_ref (), locus);
*************** TyVar::subst_covariant_var (TyTy::BaseTy
*** 98,104 ****
  TyVar
  TyVar::clone () const
  {
!   TyTy::BaseType *c = get_tyty ()->clone ();
    return TyVar (c->get_ref ());
  }
  
--- 97,106 ----
  TyVar
  TyVar::clone () const
  {
!   TyTy::BaseType *base = get_tyty ();
!   if (base == nullptr || base->get_kind () == TypeKind::ERROR)
!     return TyVar::get_implicit_infer_var (UNKNOWN_LOCATION);
!   TyTy::BaseType *c = base->clone ();
    return TyVar (c->get_ref ());
  }
  
*************** TyVar::monomorphized_clone () const
*** 108,113 ****
--- 110,119 ----
    auto &mappings = Analysis::Mappings::get ();
    auto context = Resolver::TypeCheckContext::get ();
  
+   TyTy::BaseType *base = get_tyty ();
+   if (base == nullptr || base->get_kind () == TypeKind::ERROR)
+     return TyVar::get_implicit_infer_var (UNKNOWN_LOCATION);
+ 
    // this needs a new hirid
    TyTy::BaseType *c = get_tyty ()->monomorphized_clone ();
    c->set_ref (mappings.get_next_hir_id ());
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-util.h gcc-16-20251102/gcc/rust/typecheck/rust-tyty-util.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-util.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-util.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 43,50 ****
  
    static TyVar get_implicit_infer_var (location_t locus);
  
!   static TyVar get_implicit_const_infer_var (const TyTy::ConstType &const_type,
! 					     location_t locus);
  
    static TyVar subst_covariant_var (TyTy::BaseType *orig,
  				    TyTy::BaseType *subst);
--- 43,49 ----
  
    static TyVar get_implicit_infer_var (location_t locus);
  
!   static TyVar get_implicit_const_infer_var (location_t locus);
  
    static TyVar subst_covariant_var (TyTy::BaseType *orig,
  				    TyTy::BaseType *subst);
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-variance-analysis-private.h gcc-16-20251102/gcc/rust/typecheck/rust-tyty-variance-analysis-private.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-variance-analysis-private.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-variance-analysis-private.h	Sun Nov  2 22:32:23 2025
*************** struct Term
*** 47,52 ****
--- 47,56 ----
  /** Variance constraint of a type parameter. */
  struct Constraint
  {
+   Constraint (SolutionIndex target_index, Term *term)
+     : target_index (target_index), term (term)
+   {}
+ 
    SolutionIndex target_index;
    Term *term;
  };
*************** public:
*** 171,177 ****
  
    void visit (OpaqueType &type) override {}
  
!   void visit (ConstType &type) override {}
  };
  
  /** Per crate context for generic type variance analysis. */
--- 175,184 ----
  
    void visit (OpaqueType &type) override {}
  
!   void visit (TyTy::ConstParamType &) override {}
!   void visit (TyTy::ConstValueType &) override {}
!   void visit (TyTy::ConstInferType &) override {}
!   void visit (TyTy::ConstErrorType &) override {}
  };
  
  /** Per crate context for generic type variance analysis. */
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-variance-analysis.cc gcc-16-20251102/gcc/rust/typecheck/rust-tyty-variance-analysis.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-variance-analysis.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-variance-analysis.cc	Sun Nov  2 22:32:23 2025
*************** GenericTyPerCrateCtx::query_generic_vari
*** 321,326 ****
--- 321,328 ----
    auto num_types = type.get_num_type_params ();
  
    std::vector<Variance> result;
+   result.reserve (num_lifetimes + num_types);
+ 
    for (size_t i = 0; i < num_lifetimes + num_types; ++i)
      {
        result.push_back (solutions[solution_index.value () + i]);
*************** GenericTyVisitorCtx::add_constraint (Sol
*** 410,416 ****
      }
    else
      {
!       ctx.constraints.push_back ({index, new Term (term)});
      }
  }
  
--- 412,418 ----
      }
    else
      {
!       ctx.constraints.emplace_back (index, new Term (term));
      }
  }
  
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty-visitor.h gcc-16-20251102/gcc/rust/typecheck/rust-tyty-visitor.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty-visitor.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty-visitor.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 45,51 ****
    virtual void visit (ReferenceType &type) = 0;
    virtual void visit (PointerType &type) = 0;
    virtual void visit (ParamType &type) = 0;
!   virtual void visit (ConstType &type) = 0;
    virtual void visit (StrType &type) = 0;
    virtual void visit (NeverType &type) = 0;
    virtual void visit (PlaceholderType &type) = 0;
--- 45,54 ----
    virtual void visit (ReferenceType &type) = 0;
    virtual void visit (PointerType &type) = 0;
    virtual void visit (ParamType &type) = 0;
!   virtual void visit (ConstParamType &type) = 0;
!   virtual void visit (ConstValueType &type) = 0;
!   virtual void visit (ConstInferType &type) = 0;
!   virtual void visit (ConstErrorType &type) = 0;
    virtual void visit (StrType &type) = 0;
    virtual void visit (NeverType &type) = 0;
    virtual void visit (PlaceholderType &type) = 0;
*************** public:
*** 76,82 ****
    virtual void visit (const ReferenceType &type) = 0;
    virtual void visit (const PointerType &type) = 0;
    virtual void visit (const ParamType &type) = 0;
!   virtual void visit (const ConstType &type) = 0;
    virtual void visit (const StrType &type) = 0;
    virtual void visit (const NeverType &type) = 0;
    virtual void visit (const PlaceholderType &type) = 0;
--- 79,88 ----
    virtual void visit (const ReferenceType &type) = 0;
    virtual void visit (const PointerType &type) = 0;
    virtual void visit (const ParamType &type) = 0;
!   virtual void visit (const ConstParamType &type) = 0;
!   virtual void visit (const ConstValueType &type) = 0;
!   virtual void visit (const ConstInferType &type) = 0;
!   virtual void visit (const ConstErrorType &type) = 0;
    virtual void visit (const StrType &type) = 0;
    virtual void visit (const NeverType &type) = 0;
    virtual void visit (const PlaceholderType &type) = 0;
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty.cc gcc-16-20251102/gcc/rust/typecheck/rust-tyty.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty.cc	Sun Nov  2 22:32:23 2025
***************
*** 16,44 ****
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
  
  #include "rust-tyty.h"
- 
- #include "optional.h"
  #include "rust-tyty-subst.h"
  #include "rust-tyty-visitor.h"
  #include "rust-hir-map.h"
  #include "rust-location.h"
! #include "rust-linemap.h"
! 
  #include "rust-substitution-mapper.h"
  #include "rust-hir-trait-reference.h"
  #include "rust-hir-trait-resolve.h"
- #include "rust-tyty-cmp.h"
- #include "rust-type-util.h"
- #include "rust-hir-type-bounds.h"
- #include "print-tree.h"
  #include "tree-pretty-print.h"
  
  #include "options.h"
- #include "rust-system.h"
  #include "tree.h"
  #include "fold-const.h"
- #include <string>
  
  namespace Rust {
  namespace TyTy {
--- 16,38 ----
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
  
+ #include "rust-system.h"
  #include "rust-tyty.h"
  #include "rust-tyty-subst.h"
  #include "rust-tyty-visitor.h"
  #include "rust-hir-map.h"
  #include "rust-location.h"
! #include "rust-type-util.h"
! #include "rust-hir-type-bounds.h"
  #include "rust-substitution-mapper.h"
  #include "rust-hir-trait-reference.h"
  #include "rust-hir-trait-resolve.h"
  #include "tree-pretty-print.h"
  
+ #include "optional.h"
  #include "options.h"
  #include "tree.h"
  #include "fold-const.h"
  
  namespace Rust {
  namespace TyTy {
*************** BaseType::get_locus () const
*** 295,302 ****
  
  // FIXME this is missing locus
  bool
! BaseType::satisfies_bound (const TypeBoundPredicate &predicate,
! 			   bool emit_error) const
  {
    const Resolver::TraitReference *query = predicate.get ();
    for (const auto &bound : specified_bounds)
--- 289,295 ----
  
  // FIXME this is missing locus
  bool
! BaseType::satisfies_bound (const TypeBoundPredicate &predicate, bool emit_error)
  {
    const Resolver::TraitReference *query = predicate.get ();
    for (const auto &bound : specified_bounds)
*************** BaseType::satisfies_bound (const TypeBou
*** 351,391 ****
  	    return false;
  
  	  std::string item_name = item->get_impl_item_name ();
! 	  TypeBoundPredicateItem lookup
  	    = predicate.lookup_associated_item (item_name);
! 	  if (lookup.is_error ())
  	    return false;
  
! 	  const auto *item_ref = lookup.get_raw_item ();
  	  TyTy::BaseType *bound_ty = item_ref->get_tyty ();
  
! 	  // compare the types
! 	  if (!bound_ty->can_eq (impl_item_ty, false))
! 	    {
! 	      if (!impl_item_ty->can_eq (bound_ty, false))
! 		{
! 		  if (emit_error)
! 		    {
! 		      rich_location r (line_table,
! 				       mappings.lookup_location (get_ref ()));
! 		      r.add_range (predicate.get_locus ());
! 		      r.add_range (mappings.lookup_location (i.get_hirid ()));
! 
! 		      std::string rich_msg
! 			= "expected " + bound_ty->destructure ()->get_name ()
! 			  + ", found "
! 			  + impl_item_ty->destructure ()->get_name ();
! 		      r.add_fixit_replace (rich_msg.c_str ());
! 
! 		      rust_error_at (
! 			r, ErrorCode::E0271,
! 			"type mismatch, expected %qs but got %qs",
! 			bound_ty->destructure ()->get_name ().c_str (),
! 			impl_item_ty->destructure ()->get_name ().c_str ());
! 		    }
! 		  return false;
! 		}
! 	    }
  	}
  
        return true;
--- 344,363 ----
  	    return false;
  
  	  std::string item_name = item->get_impl_item_name ();
! 	  tl::optional<TypeBoundPredicateItem> lookup
  	    = predicate.lookup_associated_item (item_name);
! 	  if (!lookup.has_value ())
  	    return false;
  
! 	  const auto *item_ref = lookup->get_raw_item ();
  	  TyTy::BaseType *bound_ty = item_ref->get_tyty ();
  
! 	  if (!Resolver::types_compatable (
! 		TyTy::TyWithLocation (bound_ty, predicate.get_locus ()),
! 		TyTy::TyWithLocation (impl_item_ty, item->get_locus ()),
! 		mappings.lookup_location (get_ref ()), false /*emit-error*/,
! 		false /*check-bounds*/))
! 	    return false;
  	}
  
        return true;
*************** BaseType::satisfies_bound (const TypeBou
*** 395,402 ****
  }
  
  bool
! BaseType::bounds_compatible (const BaseType &other, location_t locus,
! 			     bool emit_error) const
  {
    std::vector<std::reference_wrapper<const TypeBoundPredicate>>
      unsatisfied_bounds;
--- 367,373 ----
  }
  
  bool
! BaseType::bounds_compatible (BaseType &other, location_t locus, bool emit_error)
  {
    std::vector<std::reference_wrapper<const TypeBoundPredicate>>
      unsatisfied_bounds;
*************** BaseType::destructure ()
*** 501,506 ****
--- 472,494 ----
  
  	  x = pr;
  	}
+       else if (x->get_kind () == TypeKind::CONST)
+ 	{
+ 	  auto p = x->as_const_type ();
+ 	  if (p->const_kind () == BaseConstType::ConstKind::Decl)
+ 	    {
+ 	      auto decl = static_cast<ConstParamType *> (p);
+ 	      auto pr = decl->resolve ();
+ 	      if (pr == x)
+ 		return pr;
+ 
+ 	      x = pr;
+ 	    }
+ 	  else
+ 	    {
+ 	      return x;
+ 	    }
+ 	}
        else if (auto p = x->try_as<PlaceholderType> ())
  	{
  	  if (!p->can_resolve ())
*************** BaseType::destructure () const
*** 546,551 ****
--- 534,556 ----
  
  	  x = pr;
  	}
+       else if (x->get_kind () == TypeKind::CONST)
+ 	{
+ 	  auto p = x->as_const_type ();
+ 	  if (p->const_kind () == BaseConstType::ConstKind::Decl)
+ 	    {
+ 	      auto decl = static_cast<const ConstParamType *> (p);
+ 	      auto pr = decl->resolve ();
+ 	      if (pr == x)
+ 		return pr;
+ 
+ 	      x = pr;
+ 	    }
+ 	  else
+ 	    {
+ 	      return x;
+ 	    }
+ 	}
        else if (auto p = x->try_as<const PlaceholderType> ())
  	{
  	  if (!p->can_resolve ())
*************** BaseType::monomorphized_clone () const
*** 583,589 ****
      {
        TyVar elm = arr->get_var_element_type ().monomorphized_clone ();
        return new ArrayType (arr->get_ref (), arr->get_ty_ref (), ident.locus,
! 			    arr->get_capacity (), elm,
  			    arr->get_combined_refs ());
      }
    else if (auto slice = x->try_as<const SliceType> ())
--- 588,594 ----
      {
        TyVar elm = arr->get_var_element_type ().monomorphized_clone ();
        return new ArrayType (arr->get_ref (), arr->get_ty_ref (), ident.locus,
! 			    arr->get_capacity_var (), elm,
  			    arr->get_combined_refs ());
      }
    else if (auto slice = x->try_as<const SliceType> ())
*************** BaseType::monomorphized_clone () const
*** 637,644 ****
  
        TyVar retty = fn->get_var_return_type ().monomorphized_clone ();
        return new FnPtr (fn->get_ref (), fn->get_ty_ref (), ident.locus,
! 			std::move (cloned_params), retty,
! 			fn->get_combined_refs ());
      }
    else if (auto adt = x->try_as<const ADTType> ())
      {
--- 642,649 ----
  
        TyVar retty = fn->get_var_return_type ().monomorphized_clone ();
        return new FnPtr (fn->get_ref (), fn->get_ty_ref (), ident.locus,
! 			std::move (cloned_params), retty, fn->get_abi (),
! 			fn->get_unsafety (), fn->get_combined_refs ());
      }
    else if (auto adt = x->try_as<const ADTType> ())
      {
*************** BaseType::is_concrete () const
*** 780,786 ****
  {
    const TyTy::BaseType *x = destructure ();
  
!   if (x->is<ParamType> () || x->is<ProjectionType> ())
      {
        return false;
      }
--- 785,792 ----
  {
    const TyTy::BaseType *x = destructure ();
  
!   if (x->is<ParamType> () || x->is<ProjectionType> ()
!       || x->is<ConstParamType> ())
      {
        return false;
      }
*************** BaseType::is_concrete () const
*** 862,871 ****
  	return false;
        return closure->get_result_type ().is_concrete ();
      }
-   else if (auto const_type = x->try_as<const ConstType> ())
-     {
-       return const_type->get_value () != error_mark_node;
-     }
    else if (x->is<InferType> () || x->is<BoolType> () || x->is<CharType> ()
  	   || x->is<IntType> () || x->is<UintType> () || x->is<FloatType> ()
  	   || x->is<USizeType> () || x->is<ISizeType> () || x->is<NeverType> ()
--- 868,873 ----
*************** InferType::as_string () const
*** 1113,1125 ****
    return "<infer::error>";
  }
  
- bool
- InferType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   InferCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  InferType::clone () const
  {
--- 1115,1120 ----
*************** ErrorType::as_string () const
*** 1410,1421 ****
    return "<tyty::error>";
  }
  
- bool
- ErrorType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   return get_kind () == other->get_kind ();
- }
- 
  BaseType *
  ErrorType::clone () const
  {
--- 1405,1410 ----
*************** ADTType::as_string () const
*** 1800,1812 ****
  }
  
  bool
- ADTType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   ADTCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  ADTType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
--- 1789,1794 ----
*************** TupleType::get_field (size_t index) cons
*** 2037,2049 ****
  }
  
  bool
- TupleType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   TupleCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  TupleType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
--- 2019,2024 ----
*************** FnType::as_string () const
*** 2126,2138 ****
  }
  
  bool
- FnType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   FnCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  FnType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
--- 2101,2106 ----
*************** FnPtr::as_string () const
*** 2331,2344 ****
        params_str += p.get_tyty ()->as_string () + " ,";
      }
  
!   return "fnptr (" + params_str + ") -> " + get_return_type ()->as_string ();
! }
  
! bool
! FnPtr::can_eq (const BaseType *other, bool emit_errors) const
! {
!   FnptrCmp r (this, emit_errors);
!   return r.can_eq (other);
  }
  
  bool
--- 2299,2311 ----
        params_str += p.get_tyty ()->as_string () + " ,";
      }
  
!   std::string unsafety = "";
!   if (get_unsafety () == Unsafety::Unsafe)
!     unsafety = "unsafe ";
  
!   std::string abi = get_string_from_abi (get_abi ());
!   return unsafety + "abi:" + abi + " " + "fnptr (" + params_str + ") -> "
! 	 + get_return_type ()->as_string ();
  }
  
  bool
*************** BaseType *
*** 2368,2379 ****
  FnPtr::clone () const
  {
    std::vector<TyVar> cloned_params;
    for (auto &p : params)
!     cloned_params.push_back (TyVar (p.get_ref ()));
  
    return new FnPtr (get_ref (), get_ty_ref (), ident.locus,
! 		    std::move (cloned_params), result_type,
! 		    get_combined_refs ());
  }
  
  void
--- 2335,2382 ----
  FnPtr::clone () const
  {
    std::vector<TyVar> cloned_params;
+   cloned_params.reserve (params.size ());
+ 
    for (auto &p : params)
!     cloned_params.emplace_back (p.get_ref ());
  
    return new FnPtr (get_ref (), get_ty_ref (), ident.locus,
! 		    std::move (cloned_params), result_type, get_abi (),
! 		    get_unsafety (), get_combined_refs ());
! }
! 
! FnPtr *
! FnPtr::handle_substitions (SubstitutionArgumentMappings &mappings)
! {
!   auto &mappings_table = Analysis::Mappings::get ();
! 
!   auto fn = clone ()->as<FnPtr> ();
!   fn->set_ref (mappings_table.get_next_hir_id ());
!   fn->set_ty_ref (mappings_table.get_next_hir_id ());
! 
!   if (!fn->result_type.get_tyty ()->is_concrete ())
!     {
!       BaseType *concrete
! 	= Resolver::SubstMapperInternal::Resolve (fn->result_type.get_tyty (),
! 						  mappings);
!       fn->result_type
! 	= TyVar::subst_covariant_var (fn->result_type.get_tyty (), concrete);
!     }
! 
!   for (size_t i = 0; i < fn->params.size (); i++)
!     {
!       TyVar &field = fn->params.at (i);
!       if (!field.get_tyty ()->is_concrete ())
! 	{
! 	  BaseType *concrete
! 	    = Resolver::SubstMapperInternal::Resolve (field.get_tyty (),
! 						      mappings);
! 	  fn->params[i]
! 	    = TyVar::subst_covariant_var (field.get_tyty (), concrete);
! 	}
!     }
! 
!   return fn;
  }
  
  void
*************** ClosureType::as_string () const
*** 2396,2408 ****
  }
  
  bool
- ClosureType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   ClosureCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  ClosureType::is_equal (const BaseType &other) const
  {
    if (other.get_kind () != TypeKind::CLOSURE)
--- 2399,2404 ----
*************** ArrayType::accept_vis (TyConstVisitor &v
*** 2499,2513 ****
  std::string
  ArrayType::as_string () const
  {
!   return "[" + get_element_type ()->as_string () + "; " + capacity->as_string ()
! 	 + "]";
! }
  
! bool
! ArrayType::can_eq (const BaseType *other, bool emit_errors) const
! {
!   ArrayCmp r (this, emit_errors);
!   return r.can_eq (other);
  }
  
  bool
--- 2495,2504 ----
  std::string
  ArrayType::as_string () const
  {
!   auto cap = get_capacity ();
!   std::string capacity_str = cap->as_string ();
  
!   return "[" + get_element_type ()->as_string () + "; " + capacity_str + "]";
  }
  
  bool
*************** ArrayType::get_var_element_type () const
*** 2537,2542 ****
--- 2528,2539 ----
  }
  
  BaseType *
+ ArrayType::get_capacity () const
+ {
+   return capacity.get_tyty ();
+ }
+ 
+ BaseType *
  ArrayType::clone () const
  {
    return new ArrayType (get_ref (), get_ty_ref (), ident.locus, capacity,
*************** ArrayType::handle_substitions (Substitut
*** 2561,2567 ****
    BaseType *concrete_cap
      = Resolver::SubstMapperInternal::Resolve (cap, mappings);
    rust_assert (concrete_cap->get_kind () == TyTy::TypeKind::CONST);
!   ref->capacity = static_cast<TyTy::ConstType *> (concrete_cap);
  
    return ref;
  }
--- 2558,2564 ----
    BaseType *concrete_cap
      = Resolver::SubstMapperInternal::Resolve (cap, mappings);
    rust_assert (concrete_cap->get_kind () == TyTy::TypeKind::CONST);
!   ref->capacity = TyVar::subst_covariant_var (cap, concrete_cap);
  
    return ref;
  }
*************** SliceType::as_string () const
*** 2585,2597 ****
  }
  
  bool
- SliceType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   SliceCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  SliceType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
--- 2582,2587 ----
*************** BoolType::as_string () const
*** 2678,2690 ****
    return "bool";
  }
  
- bool
- BoolType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   BoolCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  BoolType::clone () const
  {
--- 2668,2673 ----
*************** IntType::as_string () const
*** 2751,2763 ****
    return "__unknown_int_type";
  }
  
- bool
- IntType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   IntCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  IntType::clone () const
  {
--- 2734,2739 ----
*************** UintType::as_string () const
*** 2836,2848 ****
    return "__unknown_uint_type";
  }
  
- bool
- UintType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   UintCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  UintType::clone () const
  {
--- 2812,2817 ----
*************** FloatType::as_string () const
*** 2915,2927 ****
    return "__unknown_float_type";
  }
  
- bool
- FloatType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   FloatCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  FloatType::clone () const
  {
--- 2884,2889 ----
*************** USizeType::as_string () const
*** 2977,2989 ****
    return "usize";
  }
  
- bool
- USizeType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   USizeCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  USizeType::clone () const
  {
--- 2939,2944 ----
*************** ISizeType::as_string () const
*** 3028,3040 ****
    return "isize";
  }
  
- bool
- ISizeType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   ISizeCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  ISizeType::clone () const
  {
--- 2983,2988 ----
*************** CharType::as_string () const
*** 3079,3091 ****
    return "char";
  }
  
- bool
- CharType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   CharCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  CharType::clone () const
  {
--- 3027,3032 ----
*************** ReferenceType::get_name () const
*** 3200,3212 ****
  }
  
  bool
- ReferenceType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   ReferenceCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  ReferenceType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
--- 3141,3146 ----
*************** PointerType::get_name () const
*** 3362,3374 ****
  }
  
  bool
- PointerType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   PointerCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  PointerType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
--- 3296,3301 ----
*************** ParamType::get_name () const
*** 3478,3490 ****
    return destructure ()->get_name ();
  }
  
- bool
- ParamType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   ParamCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  ParamType::clone () const
  {
--- 3405,3410 ----
*************** ParamType::is_equal (const BaseType &oth
*** 3543,3549 ****
      return false;
  
    if (can_resolve ())
!     return resolve ()->can_eq (other2.resolve (), false);
  
    return get_symbol ().compare (other2.get_symbol ()) == 0;
  }
--- 3463,3471 ----
      return false;
  
    if (can_resolve ())
!     return Resolver::types_compatable (TyTy::TyWithLocation (resolve ()),
! 				       TyTy::TyWithLocation (other2.resolve ()),
! 				       UNKNOWN_LOCATION, false, false);
  
    return get_symbol ().compare (other2.get_symbol ()) == 0;
  }
*************** ParamType::handle_substitions (Substitut
*** 3564,3570 ****
      {
        const ParamType &pp = *static_cast<const ParamType *> (resolved);
        if (pp.can_resolve ())
! 	resolved = pp.resolve ();
      }
  
    // this is the new subst that this needs to pass
--- 3486,3492 ----
      {
        const ParamType &pp = *static_cast<const ParamType *> (resolved);
        if (pp.can_resolve ())
! 	pp.resolve ();
      }
  
    // this is the new subst that this needs to pass
*************** ParamType::is_implicit_self_trait () con
*** 3586,3740 ****
    return is_trait_self;
  }
  
! // ConstType
  
! ConstType::ConstType (ConstKind kind, std::string symbol, TyTy::BaseType *ty,
! 		      tree value,
! 		      std::vector<TypeBoundPredicate> specified_bounds,
! 		      location_t locus, HirId ref, HirId ty_ref,
! 		      std::set<HirId> refs)
!   : BaseGeneric (ref, ty_ref, KIND,
! 		 {Resolver::CanonicalPath::new_seg (UNKNOWN_NODEID,
! 						    symbol.empty () ? "<n/a>"
! 								    : symbol),
  		  locus},
! 		 specified_bounds, refs),
!     const_kind (kind), ty (ty), value (value), symbol (symbol)
  {}
  
  void
! ConstType::accept_vis (TyVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! ConstType::accept_vis (TyConstVisitor &vis) const
  {
    vis.visit (*this);
  }
  
! void
! ConstType::set_value (tree v)
  {
!   value = v;
!   const_kind = ConstType::ConstKind::Value;
  }
  
  std::string
! ConstType::as_string () const
  {
!   return get_name ();
  }
  
  bool
! ConstType::can_eq (const BaseType *other, bool emit_errors) const
  {
!   ConstCmp r (this, emit_errors);
!   return r.can_eq (other);
  }
  
  BaseType *
! ConstType::clone () const
  {
!   return new ConstType (const_kind, symbol, ty, value, get_specified_bounds (),
! 			ident.locus, ref, ty_ref, get_combined_refs ());
  }
  
! std::string
! ConstType::get_symbol () const
  {
!   return symbol;
  }
  
! bool
! ConstType::can_resolve () const
  {
!   return false;
  }
  
  BaseType *
! ConstType::resolve () const
  {
!   rust_unreachable ();
!   return nullptr;
  }
  
! static std::string
! generate_tree_str (tree value)
  {
!   char *buf = nullptr;
!   size_t size = 0;
  
!   FILE *stream = open_memstream (&buf, &size);
!   if (!stream)
!     return "<error>";
  
!   print_generic_stmt (stream, value, TDF_NONE);
!   fclose (stream);
  
!   std::string result = (buf ? std::string (buf, size) : "<error>");
!   free (buf);
  
!   if (!result.empty () && result.back () == '\n')
!     result.pop_back ();
  
!   return result;
  }
  
  std::string
! ConstType::get_name () const
  {
!   if (value == error_mark_node)
!     {
!       switch (get_const_kind ())
! 	{
! 	case Rust::TyTy::ConstType::Decl:
! 	  return "ConstType:<" + get_ty ()->get_name () + " " + get_symbol ()
! 		 + ">";
  
! 	case Rust::TyTy::ConstType::Infer:
! 	  return "ConstType:<" + get_ty ()->get_name () + " ?" + ">";
  
! 	default:
! 	  return "ConstType:<" + get_ty ()->get_name () + " - <error>" + ">";
! 	}
!     }
  
!   return generate_tree_str (value);
  }
  
  bool
! ConstType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
!     {
!       return false;
!     }
  
!   const ConstType &rhs = static_cast<const ConstType &> (other);
!   if (!get_ty ()->is_equal (*rhs.get_ty ()))
      return false;
  
!   tree lv = get_value ();
!   tree rv = rhs.get_value ();
  
!   return operand_equal_p (lv, rv, 0);
  }
  
! ConstType *
! ConstType::handle_substitions (SubstitutionArgumentMappings &mappings)
  {
!   SubstitutionArg arg = SubstitutionArg::error ();
!   bool found = mappings.get_argument_for_symbol (this, &arg);
!   if (found && !arg.is_error ())
!     {
!       TyTy::BaseType *subst = arg.get_tyty ();
!       rust_assert (subst->is<TyTy::ConstType> ());
!       return static_cast<TyTy::ConstType *> (subst);
!     }
  
!   return this;
  }
  
  // OpaqueType
--- 3508,3889 ----
    return is_trait_self;
  }
  
! static std::string
! generate_tree_str (tree value)
! {
!   char *buf = nullptr;
!   size_t size = 0;
  
!   FILE *stream = open_memstream (&buf, &size);
!   if (!stream)
!     return "<error>";
! 
!   print_generic_stmt (stream, value, TDF_NONE);
!   fclose (stream);
! 
!   std::string result = (buf ? std::string (buf, size) : "<error>");
!   free (buf);
! 
!   if (!result.empty () && result.back () == '\n')
!     result.pop_back ();
! 
!   return result;
! }
! 
! // ---
! 
! ConstParamType::ConstParamType (std::string symbol, location_t locus,
! 				BaseType *type, HirId ref, HirId ty_ref,
! 				std::set<HirId> refs)
!   : BaseConstType (type),
!     BaseGeneric (ref, ty_ref, KIND,
! 		 {Resolver::CanonicalPath::new_seg (UNKNOWN_NODEID, symbol),
  		  locus},
! 		 {}, refs),
!     symbol (symbol)
  {}
  
+ BaseConstType::ConstKind
+ ConstParamType::const_kind () const
+ {
+   return BaseConstType::ConstKind::Decl;
+ }
+ 
+ std::string
+ ConstParamType::get_symbol () const
+ {
+   return symbol;
+ }
+ 
+ bool
+ ConstParamType::can_resolve () const
+ {
+   return get_ref () != get_ty_ref ();
+ }
+ 
+ BaseType *
+ ConstParamType::resolve () const
+ {
+   TyVar var (get_ty_ref ());
+   BaseType *r = var.get_tyty ();
+ 
+   while (r->get_kind () == TypeKind::CONST)
+     {
+       TyVar v (r->get_ty_ref ());
+       BaseType *n = v.get_tyty ();
+ 
+       // fix infinite loop
+       if (r == n)
+ 	break;
+ 
+       r = n;
+     }
+ 
+   if (r->get_kind () == TypeKind::CONST && (r->get_ref () == r->get_ty_ref ()))
+     {
+       auto *const_type = r->as_const_type ();
+       if (const_type->const_kind () != BaseConstType::ConstKind::Value)
+ 	return TyVar (r->get_ty_ref ()).get_tyty ();
+     }
+ 
+   return r;
+ }
+ 
  void
! ConstParamType::accept_vis (TyVisitor &vis)
  {
    vis.visit (*this);
  }
  
  void
! ConstParamType::accept_vis (TyConstVisitor &vis) const
  {
    vis.visit (*this);
  }
  
! std::string
! ConstParamType::as_string () const
  {
!   if (!can_resolve ())
!     {
!       return get_symbol () + " CONST_REF: " + std::to_string (get_ref ());
!     }
! 
!   BaseType *lookup = resolve ();
!   // Avoid infinite recursion if resolve() returns this same type
!   if (lookup == this->as_base_type ())
!     {
!       return get_symbol () + " CONST_REF: " + std::to_string (get_ref ());
!     }
! 
!   return get_symbol () + "=" + lookup->as_string ();
! }
! 
! BaseType *
! ConstParamType::clone () const
! {
!   return new ConstParamType (get_symbol (), ident.locus, specified_type,
! 			     get_ref (), get_ty_ref (), get_combined_refs ());
  }
  
  std::string
! ConstParamType::get_name () const
  {
!   if (!can_resolve ())
!     return get_symbol ();
! 
!   BaseType *lookup = resolve ();
!   // Avoid infinite recursion if resolve() returns this same type
!   if (lookup == this->as_base_type ())
!     return get_symbol ();
! 
!   return lookup->get_name ();
  }
  
  bool
! ConstParamType::is_equal (const BaseType &other) const
  {
!   if (get_kind () != other.get_kind ())
!     {
!       if (!can_resolve ())
! 	return false;
! 
!       return resolve ()->is_equal (other);
!     }
! 
!   auto other_const = other.as_const_type ();
!   if (other_const->const_kind () != BaseConstType::ConstKind::Decl)
!     return false;
! 
!   auto &other2 = static_cast<const ConstParamType &> (*other_const);
!   if (can_resolve () != other2.can_resolve ())
!     return false;
! 
!   if (can_resolve ())
!     return Resolver::types_compatable (TyTy::TyWithLocation (resolve ()),
! 				       TyTy::TyWithLocation (other2.resolve ()),
! 				       ident.locus, false);
! 
!   return get_symbol ().compare (other2.get_symbol ()) == 0;
  }
  
  BaseType *
! ConstParamType::handle_substitions (
!   SubstitutionArgumentMappings &subst_mappings)
  {
!   SubstitutionArg arg = SubstitutionArg::error ();
!   bool ok = subst_mappings.get_argument_for_symbol (this, &arg);
!   if (!ok || arg.is_error ())
!     return this;
! 
!   ConstParamType *p = static_cast<ConstParamType *> (clone ());
!   const BaseType *resolved = arg.get_tyty ();
! 
!   // this is the new subst that this needs to pass
!   p->set_ref (mappings.get_next_hir_id ());
!   p->set_ty_ref (resolved->get_ref ());
! 
!   return p;
  }
  
! // --- ConstValueType
! 
! ConstValueType::ConstValueType (tree value, BaseType *type, HirId ref,
! 				HirId ty_ref, std::set<HirId> refs)
!   : BaseType (ref, ty_ref, KIND,
! 	      {Resolver::CanonicalPath::create_empty (), UNKNOWN_LOCATION},
! 	      refs),
!     BaseConstType (type), folded_val (value)
! {}
! 
! BaseConstType::ConstKind
! ConstValueType::const_kind () const
  {
!   return BaseConstType::ConstKind::Value;
  }
  
! void
! ConstValueType::accept_vis (TyVisitor &vis)
  {
!   vis.visit (*this);
! }
! 
! void
! ConstValueType::accept_vis (TyConstVisitor &vis) const
! {
!   vis.visit (*this);
! }
! 
! std::string
! ConstValueType::as_string () const
! {
!   return generate_tree_str (folded_val);
  }
  
  BaseType *
! ConstValueType::clone () const
  {
!   return new ConstValueType (folded_val, specified_type, get_ref (),
! 			     get_ty_ref (), get_combined_refs ());
  }
  
! std::string
! ConstValueType::get_name () const
  {
!   return as_string ();
! }
  
! bool
! ConstValueType::is_equal (const BaseType &other) const
! {
!   if (get_kind () != other.get_kind ())
!     return false;
  
!   auto other_const = other.as_const_type ();
!   if (other_const->const_kind () != BaseConstType::ConstKind::Value)
!     return false;
  
!   auto &other2 = static_cast<const ConstValueType &> (*other_const);
!   return folded_val == other2.folded_val;
! }
  
! tree
! ConstValueType::get_value () const
! {
!   return folded_val;
! }
  
! // --- ConstInferType
! 
! ConstInferType::ConstInferType (BaseType *type, HirId ref, HirId ty_ref,
! 				std::set<HirId> refs)
!   : BaseType (ref, ty_ref, KIND,
! 	      {Resolver::CanonicalPath::create_empty (), UNKNOWN_LOCATION},
! 	      refs),
!     BaseConstType (type)
! {}
! 
! BaseConstType::ConstKind
! ConstInferType::const_kind () const
! {
!   return BaseConstType::ConstKind::Infer;
! }
! 
! void
! ConstInferType::accept_vis (TyVisitor &vis)
! {
!   vis.visit (*this);
! }
! 
! void
! ConstInferType::accept_vis (TyConstVisitor &vis) const
! {
!   vis.visit (*this);
  }
  
  std::string
! ConstInferType::as_string () const
  {
!   return specified_type->get_name () + "-?";
! }
  
! BaseType *
! ConstInferType::clone () const
! {
!   auto &mappings = Analysis::Mappings::get ();
!   auto context = Resolver::TypeCheckContext::get ();
  
!   ConstInferType *clone
!     = new ConstInferType (specified_type, mappings.get_next_hir_id (),
! 			  get_ty_ref (), get_combined_refs ());
  
!   context->insert_type (Analysis::NodeMapping (mappings.get_current_crate (),
! 					       UNKNOWN_NODEID,
! 					       clone->get_ref (),
! 					       UNKNOWN_LOCAL_DEFID),
! 			clone);
!   mappings.insert_location (clone->get_ref (),
! 			    mappings.lookup_location (get_ref ()));
! 
!   clone->append_reference (get_ref ());
! 
!   return clone;
! }
! 
! std::string
! ConstInferType::get_name () const
! {
!   return as_string ();
  }
  
  bool
! ConstInferType::is_equal (const BaseType &other) const
  {
    if (get_kind () != other.get_kind ())
!     return false;
  
!   auto other_const = other.as_const_type ();
!   if (other_const->const_kind () != BaseConstType::ConstKind::Infer)
      return false;
  
!   return get_ref () == other.get_ref ();
! }
  
! // --- ConstErrorType
! 
! ConstErrorType::ConstErrorType (BaseType *type, HirId ref, HirId ty_ref,
! 				std::set<HirId> refs)
!   : BaseType (ref, ty_ref, KIND,
! 	      {Resolver::CanonicalPath::create_empty (), UNKNOWN_LOCATION},
! 	      refs),
!     BaseConstType (type)
! {}
! 
! BaseConstType::ConstKind
! ConstErrorType::const_kind () const
! {
!   return BaseConstType::ConstKind::Error;
  }
  
! void
! ConstErrorType::accept_vis (TyVisitor &vis)
  {
!   vis.visit (*this);
! }
  
! void
! ConstErrorType::accept_vis (TyConstVisitor &vis) const
! {
!   vis.visit (*this);
! }
! 
! std::string
! ConstErrorType::as_string () const
! {
!   return "<const_error>";
! }
! 
! BaseType *
! ConstErrorType::clone () const
! {
!   return new ConstErrorType (specified_type, get_ref (), get_ty_ref (),
! 			     get_combined_refs ());
! }
! 
! std::string
! ConstErrorType::get_name () const
! {
!   return as_string ();
! }
! 
! bool
! ConstErrorType::is_equal (const BaseType &other) const
! {
!   if (get_kind () != other.get_kind ())
!     return false;
! 
!   auto other_const = other.as_const_type ();
!   return other_const->const_kind () == BaseConstType::ConstKind::Error;
  }
  
  // OpaqueType
*************** OpaqueType::get_name () const
*** 3787,3799 ****
    return "impl " + raw_bounds_as_name ();
  }
  
- bool
- OpaqueType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   OpaqueCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  OpaqueType::clone () const
  {
--- 3936,3941 ----
*************** OpaqueType::is_equal (const BaseType &ot
*** 3815,3821 ****
    if (can_resolve () != other2.can_resolve ())
      return false;
  
!   return bounds_compatible (other, UNDEF_LOCATION, false);
  }
  
  // StrType
--- 3957,3980 ----
    if (can_resolve () != other2.can_resolve ())
      return false;
  
!   if (num_specified_bounds () != other.num_specified_bounds ())
!     return false;
! 
!   for (const auto &pred : specified_bounds)
!     {
!       bool found = false;
!       for (const auto &opred : other.get_specified_bounds ())
! 	{
! 	  found = pred.is_equal (opred);
! 	  if (found)
! 	    break;
! 	}
! 
!       if (!found)
! 	return false;
!     }
! 
!   return true;
  }
  
  // StrType
*************** StrType::as_string () const
*** 3863,3875 ****
  }
  
  bool
- StrType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   StrCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
- bool
  StrType::is_equal (const BaseType &other) const
  {
    return get_kind () == other.get_kind ();
--- 4022,4027 ----
*************** NeverType::as_string () const
*** 3913,3925 ****
    return "!";
  }
  
- bool
- NeverType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   NeverCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  NeverType::clone () const
  {
--- 4065,4070 ----
*************** PlaceholderType::as_string () const
*** 3975,3987 ****
  	 + ">";
  }
  
- bool
- PlaceholderType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   PlaceholderCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  PlaceholderType::clone () const
  {
--- 4120,4125 ----
*************** ProjectionType::as_string () const
*** 4118,4129 ****
    return "<Projection=" + subst_as_string () + "::" + base->as_string () + ">";
  }
  
- bool
- ProjectionType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   return base->can_eq (other, emit_errors);
- }
- 
  BaseType *
  ProjectionType::clone () const
  {
--- 4256,4261 ----
*************** DynamicObjectType::as_string () const
*** 4237,4249 ****
    return "dyn [" + raw_bounds_as_string () + "]";
  }
  
- bool
- DynamicObjectType::can_eq (const BaseType *other, bool emit_errors) const
- {
-   DynamicCmp r (this, emit_errors);
-   return r.can_eq (other);
- }
- 
  BaseType *
  DynamicObjectType::clone () const
  {
--- 4369,4374 ----
*************** DynamicObjectType::is_equal (const BaseT
*** 4266,4272 ****
    if (num_specified_bounds () != other.num_specified_bounds ())
      return false;
  
!   return bounds_compatible (other, UNDEF_LOCATION, false);
  }
  
  const std::vector<
--- 4391,4411 ----
    if (num_specified_bounds () != other.num_specified_bounds ())
      return false;
  
!   for (const auto &pred : specified_bounds)
!     {
!       bool found = false;
!       for (const auto &opred : other.get_specified_bounds ())
! 	{
! 	  found = pred.is_equal (opred);
! 	  if (found)
! 	    break;
! 	}
! 
!       if (!found)
! 	return false;
!     }
! 
!   return true;
  }
  
  const std::vector<
*************** DynamicObjectType::get_object_items () c
*** 4287,4293 ****
  	  if (item->get_trait_item_type ()
  		== Resolver::TraitItemReference::TraitItemType::FN
  	      && item->is_object_safe ())
! 	    items.push_back ({item, &bound});
  	}
      }
    return items;
--- 4426,4432 ----
  	  if (item->get_trait_item_type ()
  		== Resolver::TraitItemReference::TraitItemType::FN
  	      && item->is_object_safe ())
! 	    items.emplace_back (item, &bound);
  	}
      }
    return items;
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-tyty.h gcc-16-20251102/gcc/rust/typecheck/rust-tyty.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-tyty.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-tyty.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 91,96 ****
--- 91,97 ----
  
  class TyVisitor;
  class TyConstVisitor;
+ class BaseConstType;
  class BaseType : public TypeBoundsMappings
  {
  public:
*************** public:
*** 110,138 ****
    virtual std::string as_string () const = 0;
    virtual std::string get_name () const = 0;
  
-   // similar to unify but does not actually perform type unification but
-   // determines whether they are compatible. Consider the following
-   //
-   // fn foo<T>() -> T { ... }
-   // fn foo() -> i32 { ... }
-   //
-   // when the function has been substituted they can be considered equal.
-   //
-   // It can also be used to optional emit errors for trait item compatibility
-   // checks
-   virtual bool can_eq (const BaseType *other, bool emit_errors) const = 0;
- 
    // Check value equality between two ty. Type inference rules are ignored. Two
    //   ty are considered equal if they're of the same kind, and
    //     1. (For ADTs, arrays, tuples, refs) have the same underlying ty
    //     2. (For functions) have the same signature
    virtual bool is_equal (const BaseType &other) const;
  
!   bool satisfies_bound (const TypeBoundPredicate &predicate,
! 			bool emit_error) const;
  
!   bool bounds_compatible (const BaseType &other, location_t locus,
! 			  bool emit_error) const;
  
    void inherit_bounds (const BaseType &other);
  
--- 111,125 ----
    virtual std::string as_string () const = 0;
    virtual std::string get_name () const = 0;
  
    // Check value equality between two ty. Type inference rules are ignored. Two
    //   ty are considered equal if they're of the same kind, and
    //     1. (For ADTs, arrays, tuples, refs) have the same underlying ty
    //     2. (For functions) have the same signature
    virtual bool is_equal (const BaseType &other) const;
  
!   bool satisfies_bound (const TypeBoundPredicate &predicate, bool emit_error);
  
!   bool bounds_compatible (BaseType &other, location_t locus, bool emit_error);
  
    void inherit_bounds (const BaseType &other);
  
*************** public:
*** 240,245 ****
--- 227,237 ----
      return static_cast<T *> (this);
    }
  
+   // Helper to get BaseConstType interface for CONST types
+   // Overridden by const types that also inherit from BaseConstType
+   virtual BaseConstType *as_const_type () { return nullptr; }
+   virtual const BaseConstType *as_const_type () const { return nullptr; }
+ 
  protected:
    BaseType (HirId ref, HirId ty_ref, TypeKind kind, RustIdent ident,
  	    std::set<HirId> refs = std::set<HirId> ());
*************** public:
*** 327,334 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    InferTypeKind get_infer_kind () const;
--- 319,324 ----
*************** public:
*** 359,366 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    std::string get_name () const override final;
--- 349,354 ----
*************** public:
*** 402,409 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    std::string get_symbol () const override final;
--- 390,395 ----
*************** private:
*** 426,432 ****
    std::string symbol;
  };
  
! class ConstType : public BaseGeneric
  {
  public:
    static constexpr auto KIND = TypeKind::CONST;
--- 412,418 ----
    std::string symbol;
  };
  
! class BaseConstType
  {
  public:
    static constexpr auto KIND = TypeKind::CONST;
*************** public:
*** 439,463 ****
      Error
    };
  
!   ConstType (ConstKind kind, std::string symbol, TyTy::BaseType *ty, tree value,
! 	     std::vector<TypeBoundPredicate> specified_bounds, location_t locus,
! 	     HirId ref, HirId ty_ref,
! 	     std::set<HirId> refs = std::set<HirId> ());
  
!   void accept_vis (TyVisitor &vis) override;
!   void accept_vis (TyConstVisitor &vis) const override;
  
!   ConstKind get_const_kind () const { return const_kind; }
!   TyTy::BaseType *get_ty () const { return ty; }
!   tree get_value () const { return value; }
  
!   void set_value (tree value);
  
!   std::string as_string () const override;
  
!   bool can_eq (const BaseType *other, bool emit_errors) const override final;
  
!   BaseType *clone () const final override;
  
    std::string get_symbol () const override final;
  
--- 425,454 ----
      Error
    };
  
!   virtual ConstKind const_kind () const = 0;
  
!   BaseType *get_specified_type () const { return specified_type; }
  
!   // Helper to get BaseType interface (all const types also inherit BaseType)
!   // This must be implemented by concrete classes since BaseConstType doesn't
!   // inherit from BaseType, but all concrete const types do.
!   virtual BaseType *as_base_type () = 0;
!   virtual const BaseType *as_base_type () const = 0;
  
! protected:
!   BaseConstType (BaseType *type) : specified_type (type) {}
  
!   BaseType *specified_type;
! };
  
! class ConstParamType : public BaseConstType, public BaseGeneric
! {
! public:
!   ConstParamType (std::string symbol, location_t locus, BaseType *type,
! 		  HirId ref, HirId ty_ref,
! 		  std::set<HirId> refs = std::set<HirId> ());
  
!   ConstKind const_kind () const override final;
  
    std::string get_symbol () const override final;
  
*************** public:
*** 465,483 ****
  
    BaseType *resolve () const override final;
  
    std::string get_name () const override final;
  
    bool is_equal (const BaseType &other) const override;
  
!   ConstType *handle_substitions (SubstitutionArgumentMappings &mappings);
  
  private:
-   ConstKind const_kind;
-   TyTy::BaseType *ty;
-   tree value;
    std::string symbol;
  };
  
  class OpaqueType : public BaseType
  {
  public:
--- 456,581 ----
  
    BaseType *resolve () const override final;
  
+   void accept_vis (TyVisitor &vis) override;
+   void accept_vis (TyConstVisitor &vis) const override;
+ 
+   std::string as_string () const override;
+ 
+   BaseType *clone () const final override;
    std::string get_name () const override final;
  
    bool is_equal (const BaseType &other) const override;
  
!   BaseType *handle_substitions (SubstitutionArgumentMappings &mappings);
! 
!   BaseType *as_base_type () override { return static_cast<BaseType *> (this); }
!   const BaseType *as_base_type () const override
!   {
!     return static_cast<const BaseType *> (this);
!   }
! 
!   BaseConstType *as_const_type () override { return this; }
!   const BaseConstType *as_const_type () const override { return this; }
  
  private:
    std::string symbol;
  };
  
+ class ConstValueType : public BaseType, public BaseConstType
+ {
+ public:
+   static constexpr auto KIND = TypeKind::CONST;
+ 
+   ConstValueType (tree value, BaseType *type, HirId ref, HirId ty_ref,
+ 		  std::set<HirId> refs = std::set<HirId> ());
+ 
+   ConstKind const_kind () const override final;
+ 
+   void accept_vis (TyVisitor &vis) override;
+   void accept_vis (TyConstVisitor &vis) const override;
+ 
+   std::string as_string () const override;
+ 
+   BaseType *clone () const final override;
+   std::string get_name () const override final;
+ 
+   bool is_equal (const BaseType &other) const override;
+ 
+   tree get_value () const;
+ 
+   BaseType *as_base_type () override { return static_cast<BaseType *> (this); }
+   const BaseType *as_base_type () const override
+   {
+     return static_cast<const BaseType *> (this);
+   }
+ 
+   BaseConstType *as_const_type () override { return this; }
+   const BaseConstType *as_const_type () const override { return this; }
+ 
+ private:
+   tree folded_val;
+ };
+ 
+ class ConstInferType : public BaseType, public BaseConstType
+ {
+ public:
+   static constexpr auto KIND = TypeKind::CONST;
+ 
+   ConstInferType (BaseType *type, HirId ref, HirId ty_ref,
+ 		  std::set<HirId> refs = std::set<HirId> ());
+ 
+   ConstKind const_kind () const override final;
+ 
+   void accept_vis (TyVisitor &vis) override;
+   void accept_vis (TyConstVisitor &vis) const override;
+ 
+   std::string as_string () const override;
+ 
+   BaseType *clone () const final override;
+   std::string get_name () const override final;
+ 
+   bool is_equal (const BaseType &other) const override;
+ 
+   BaseType *as_base_type () override { return static_cast<BaseType *> (this); }
+   const BaseType *as_base_type () const override
+   {
+     return static_cast<const BaseType *> (this);
+   }
+ 
+   BaseConstType *as_const_type () override { return this; }
+   const BaseConstType *as_const_type () const override { return this; }
+ };
+ 
+ class ConstErrorType : public BaseType, public BaseConstType
+ {
+ public:
+   static constexpr auto KIND = TypeKind::CONST;
+ 
+   ConstErrorType (BaseType *type, HirId ref, HirId ty_ref,
+ 		  std::set<HirId> refs = std::set<HirId> ());
+ 
+   ConstKind const_kind () const override final;
+ 
+   void accept_vis (TyVisitor &vis) override;
+   void accept_vis (TyConstVisitor &vis) const override;
+ 
+   std::string as_string () const override;
+ 
+   BaseType *clone () const final override;
+   std::string get_name () const override final;
+ 
+   bool is_equal (const BaseType &other) const override;
+ 
+   BaseType *as_base_type () override { return static_cast<BaseType *> (this); }
+   const BaseType *as_base_type () const override
+   {
+     return static_cast<const BaseType *> (this);
+   }
+ 
+   BaseConstType *as_const_type () override { return this; }
+   const BaseConstType *as_const_type () const override { return this; }
+ };
+ 
  class OpaqueType : public BaseType
  {
  public:
*************** public:
*** 496,503 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    bool can_resolve () const;
--- 594,599 ----
*************** public:
*** 557,564 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    size_t num_fields () const;
--- 653,658 ----
*************** public:
*** 589,595 ****
  
    TypeBoundPredicate (const TypeBoundPredicate &other);
  
!   virtual ~TypeBoundPredicate (){};
  
    TypeBoundPredicate &operator= (const TypeBoundPredicate &other);
  
--- 683,689 ----
  
    TypeBoundPredicate (const TypeBoundPredicate &other);
  
!   virtual ~TypeBoundPredicate () {}
  
    TypeBoundPredicate &operator= (const TypeBoundPredicate &other);
  
*************** public:
*** 617,626 ****
  
    bool contains_item (const std::string &search) const;
  
!   TypeBoundPredicateItem
    lookup_associated_item (const std::string &search) const;
  
!   TypeBoundPredicateItem
    lookup_associated_item (const Resolver::TraitItemReference *ref) const;
  
    // WARNING THIS WILL ALWAYS RETURN NULLPTR
--- 711,720 ----
  
    bool contains_item (const std::string &search) const;
  
!   tl::optional<TypeBoundPredicateItem>
    lookup_associated_item (const std::string &search) const;
  
!   tl::optional<TypeBoundPredicateItem>
    lookup_associated_item (const Resolver::TraitItemReference *ref) const;
  
    // WARNING THIS WILL ALWAYS RETURN NULLPTR
*************** public:
*** 851,858 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    std::string get_identifier () const { return identifier; }
--- 945,950 ----
*************** public:
*** 1003,1010 ****
  
    std::string get_identifier () const { return identifier; }
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    size_t num_params () const { return params.size (); }
--- 1095,1100 ----
*************** public:
*** 1076,1094 ****
    static constexpr auto KIND = TypeKind::FNPTR;
  
    FnPtr (HirId ref, location_t locus, std::vector<TyVar> params,
! 	 TyVar result_type, std::set<HirId> refs = std::set<HirId> ())
      : CallableTypeInterface (ref, ref, TypeKind::FNPTR,
  			     {Resolver::CanonicalPath::create_empty (), locus},
  			     refs),
!       params (std::move (params)), result_type (result_type)
    {}
  
    FnPtr (HirId ref, HirId ty_ref, location_t locus, std::vector<TyVar> params,
! 	 TyVar result_type, std::set<HirId> refs = std::set<HirId> ())
      : CallableTypeInterface (ref, ty_ref, TypeKind::FNPTR,
  			     {Resolver::CanonicalPath::create_empty (), locus},
  			     refs),
!       params (params), result_type (result_type)
    {}
  
    std::string get_name () const override final { return as_string (); }
--- 1166,1187 ----
    static constexpr auto KIND = TypeKind::FNPTR;
  
    FnPtr (HirId ref, location_t locus, std::vector<TyVar> params,
! 	 TyVar result_type, ABI abi, Unsafety unsafety,
! 	 std::set<HirId> refs = std::set<HirId> ())
      : CallableTypeInterface (ref, ref, TypeKind::FNPTR,
  			     {Resolver::CanonicalPath::create_empty (), locus},
  			     refs),
!       params (std::move (params)), result_type (result_type), abi (abi),
!       unsafety (unsafety)
    {}
  
    FnPtr (HirId ref, HirId ty_ref, location_t locus, std::vector<TyVar> params,
! 	 TyVar result_type, ABI abi, Unsafety unsafety,
! 	 std::set<HirId> refs = std::set<HirId> ())
      : CallableTypeInterface (ref, ty_ref, TypeKind::FNPTR,
  			     {Resolver::CanonicalPath::create_empty (), locus},
  			     refs),
!       params (params), result_type (result_type), abi (abi), unsafety (unsafety)
    {}
  
    std::string get_name () const override final { return as_string (); }
*************** public:
*** 1117,1124 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *clone () const final override;
--- 1210,1215 ----
*************** public:
*** 1126,1134 ****
--- 1217,1233 ----
    std::vector<TyVar> &get_params () { return params; }
    const std::vector<TyVar> &get_params () const { return params; }
  
+   ABI get_abi () const { return abi; }
+ 
+   Unsafety get_unsafety () const { return unsafety; }
+ 
+   FnPtr *handle_substitions (SubstitutionArgumentMappings &mappings);
+ 
  private:
    std::vector<TyVar> params;
    TyVar result_type;
+   ABI abi;
+   Unsafety unsafety;
  };
  
  class ClosureType : public CallableTypeInterface, public SubstitutionRef
*************** public:
*** 1194,1201 ****
    std::string as_string () const override;
    std::string get_name () const override final { return as_string (); }
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *clone () const final override;
--- 1293,1298 ----
*************** class ArrayType : public BaseType
*** 1224,1237 ****
  public:
    static constexpr auto KIND = TypeKind::ARRAY;
  
!   ArrayType (HirId ref, location_t locus, ConstType *capacity, TyVar base,
  	     std::set<HirId> refs = std::set<HirId> ())
      : BaseType (ref, ref, TypeKind::ARRAY,
  		{Resolver::CanonicalPath::create_empty (), locus}, refs),
        element_type (base), capacity (capacity)
    {}
  
!   ArrayType (HirId ref, HirId ty_ref, location_t locus, ConstType *capacity,
  	     TyVar base, std::set<HirId> refs = std::set<HirId> ())
      : BaseType (ref, ty_ref, TypeKind::ARRAY,
  		{Resolver::CanonicalPath::create_empty (), locus}, refs),
--- 1321,1334 ----
  public:
    static constexpr auto KIND = TypeKind::ARRAY;
  
!   ArrayType (HirId ref, location_t locus, TyVar capacity, TyVar base,
  	     std::set<HirId> refs = std::set<HirId> ())
      : BaseType (ref, ref, TypeKind::ARRAY,
  		{Resolver::CanonicalPath::create_empty (), locus}, refs),
        element_type (base), capacity (capacity)
    {}
  
!   ArrayType (HirId ref, HirId ty_ref, location_t locus, TyVar capacity,
  	     TyVar base, std::set<HirId> refs = std::set<HirId> ())
      : BaseType (ref, ty_ref, TypeKind::ARRAY,
  		{Resolver::CanonicalPath::create_empty (), locus}, refs),
*************** public:
*** 1245,1252 ****
  
    std::string get_name () const override final { return as_string (); }
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *get_element_type () const;
--- 1342,1347 ----
*************** public:
*** 1254,1266 ****
  
    BaseType *clone () const final override;
  
!   ConstType *get_capacity () const { return capacity; }
  
    ArrayType *handle_substitions (SubstitutionArgumentMappings &mappings);
  
  private:
    TyVar element_type;
!   ConstType *capacity;
  };
  
  class SliceType : public BaseType
--- 1349,1362 ----
  
    BaseType *clone () const final override;
  
!   BaseType *get_capacity () const;
!   const TyVar &get_capacity_var () const { return capacity; }
  
    ArrayType *handle_substitions (SubstitutionArgumentMappings &mappings);
  
  private:
    TyVar element_type;
!   TyVar capacity;
  };
  
  class SliceType : public BaseType
*************** public:
*** 1289,1296 ****
  
    std::string get_name () const override final { return as_string (); }
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *get_element_type () const;
--- 1385,1390 ----
*************** public:
*** 1319,1326 ****
  
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  };
  
--- 1413,1418 ----
*************** public:
*** 1349,1356 ****
  
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    IntKind get_int_kind () const;
  
    BaseType *clone () const final override;
--- 1441,1446 ----
*************** public:
*** 1387,1394 ****
  
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    UintKind get_uint_kind () const;
  
    BaseType *clone () const final override;
--- 1477,1482 ----
*************** public:
*** 1421,1428 ****
    std::string as_string () const override;
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    FloatKind get_float_kind () const;
  
    BaseType *clone () const final override;
--- 1509,1514 ----
*************** public:
*** 1448,1455 ****
    std::string as_string () const override;
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  };
  
--- 1534,1539 ----
*************** public:
*** 1468,1475 ****
    std::string as_string () const override;
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  };
  
--- 1552,1557 ----
*************** public:
*** 1487,1494 ****
    std::string as_string () const override;
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  };
  
--- 1569,1574 ----
*************** public:
*** 1507,1514 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *clone () const final override;
--- 1587,1592 ----
*************** public:
*** 1532,1539 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *clone () const final override;
--- 1610,1615 ----
*************** public:
*** 1568,1575 ****
  
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *clone () const final override;
--- 1644,1649 ----
*************** public:
*** 1612,1619 ****
    std::string as_string () const override;
    std::string get_name () const override final;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    bool is_equal (const BaseType &other) const override;
  
    BaseType *clone () const final override;
--- 1686,1691 ----
*************** public:
*** 1659,1666 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    std::string get_name () const override final;
--- 1731,1736 ----
*************** public:
*** 1683,1690 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    std::string get_name () const override final;
--- 1753,1758 ----
*************** public:
*** 1734,1741 ****
  
    std::string as_string () const override;
  
-   bool can_eq (const BaseType *other, bool emit_errors) const override final;
- 
    BaseType *clone () const final override;
  
    std::string get_name () const override final;
--- 1802,1807 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-unify.cc gcc-16-20251102/gcc/rust/typecheck/rust-unify.cc
*** gcc-16-20251026/gcc/rust/typecheck/rust-unify.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-unify.cc	Sun Nov  2 22:32:23 2025
***************
*** 24,54 ****
  namespace Rust {
  namespace Resolver {
  
  UnifyRules::UnifyRules (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  			location_t locus, bool commit_flag, bool emit_error,
! 			bool infer, std::vector<CommitSite> &commits,
  			std::vector<InferenceSite> &infers)
    : lhs (lhs), rhs (rhs), locus (locus), commit_flag (commit_flag),
!     emit_error (emit_error), infer_flag (infer), commits (commits),
!     infers (infers), mappings (Analysis::Mappings::get ()),
!     context (*TypeCheckContext::get ())
  {}
  
  TyTy::BaseType *
  UnifyRules::Resolve (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  		     location_t locus, bool commit_flag, bool emit_error,
! 		     bool infer, std::vector<CommitSite> &commits,
  		     std::vector<InferenceSite> &infers)
  {
!   UnifyRules r (lhs, rhs, locus, commit_flag, emit_error, infer, commits,
! 		infers);
  
    TyTy::BaseType *result = r.go ();
-   commits.push_back ({lhs.get_ty (), rhs.get_ty (), result});
-   if (r.commit_flag)
-     UnifyRules::commit (lhs.get_ty (), rhs.get_ty (), result);
- 
    bool failed = result->get_kind () == TyTy::TypeKind::ERROR;
    if (failed && r.emit_error)
      r.emit_type_mismatch ();
  
--- 24,69 ----
  namespace Rust {
  namespace Resolver {
  
+ static TyTy::BaseType *
+ unify_error_type_node ()
+ {
+   static TyTy::BaseType *error = nullptr;
+   if (error == nullptr)
+     error = new TyTy::ErrorType (0);
+   return error;
+ }
+ 
  UnifyRules::UnifyRules (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  			location_t locus, bool commit_flag, bool emit_error,
! 			bool check_bounds, bool infer,
! 			std::vector<CommitSite> &commits,
  			std::vector<InferenceSite> &infers)
    : lhs (lhs), rhs (rhs), locus (locus), commit_flag (commit_flag),
!     emit_error (emit_error), infer_flag (infer),
!     check_bounds_flag (check_bounds), commits (commits), infers (infers),
!     mappings (Analysis::Mappings::get ()), context (*TypeCheckContext::get ())
  {}
  
  TyTy::BaseType *
  UnifyRules::Resolve (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  		     location_t locus, bool commit_flag, bool emit_error,
! 		     bool check_bounds, bool infer,
! 		     std::vector<CommitSite> &commits,
  		     std::vector<InferenceSite> &infers)
  {
!   UnifyRules r (lhs, rhs, locus, commit_flag, emit_error, infer, check_bounds,
! 		commits, infers);
  
    TyTy::BaseType *result = r.go ();
    bool failed = result->get_kind () == TyTy::TypeKind::ERROR;
+ 
+   commits.emplace_back (lhs.get_ty (), rhs.get_ty (), result);
+   if (r.commit_flag && !failed)
+     {
+       result = result->clone ();
+       UnifyRules::commit (lhs.get_ty (), rhs.get_ty (), result);
+     }
+ 
    if (failed && r.emit_error)
      r.emit_type_mismatch ();
  
*************** UnifyRules::resolve_subtype (TyTy::TyWit
*** 60,66 ****
  {
    TyTy::BaseType *result
      = UnifyRules::Resolve (lhs, rhs, locus, commit_flag, emit_error, infer_flag,
! 			   commits, infers);
  
    // If the recursive call resulted in an error and would have emitted an error
    // message, disable error emission for the current level to avoid duplicate
--- 75,81 ----
  {
    TyTy::BaseType *result
      = UnifyRules::Resolve (lhs, rhs, locus, commit_flag, emit_error, infer_flag,
! 			   check_bounds_flag, commits, infers);
  
    // If the recursive call resulted in an error and would have emitted an error
    // message, disable error emission for the current level to avoid duplicate
*************** UnifyRules::commit (TyTy::BaseType *base
*** 104,127 ****
    b->append_reference (resolved->get_ref ());
    b->append_reference (o->get_ref ());
  
!   bool result_resolved = resolved->get_kind () != TyTy::TypeKind::INFER;
!   bool result_is_infer_var = resolved->get_kind () == TyTy::TypeKind::INFER;
!   bool results_is_non_general_infer_var
!     = (result_is_infer_var
!        && (static_cast<TyTy::InferType *> (resolved))->get_infer_kind ()
! 	    != TyTy::InferType::GENERAL);
!   if (result_resolved || results_is_non_general_infer_var)
      {
!       for (auto &ref : resolved->get_combined_refs ())
  	{
! 	  TyTy::BaseType *ref_tyty = nullptr;
! 	  bool ok = context.lookup_type (ref, &ref_tyty);
! 	  if (!ok)
! 	    continue;
  
! 	  // if any of the types are inference variables lets fix them
! 	  if (ref_tyty->is<TyTy::InferType> ())
! 	    context.insert_implicit_type (ref, resolved);
  	}
      }
  }
--- 119,177 ----
    b->append_reference (resolved->get_ref ());
    b->append_reference (o->get_ref ());
  
!   if (resolved->get_kind () != TyTy::TypeKind::CONST)
      {
!       bool result_resolved = resolved->get_kind () != TyTy::TypeKind::INFER;
!       bool result_is_infer_var = resolved->get_kind () == TyTy::TypeKind::INFER;
!       bool results_is_non_general_infer_var
! 	= (result_is_infer_var
! 	   && (static_cast<TyTy::InferType *> (resolved))->get_infer_kind ()
! 		!= TyTy::InferType::GENERAL);
!       if (result_resolved || results_is_non_general_infer_var)
  	{
! 	  for (auto &ref : resolved->get_combined_refs ())
! 	    {
! 	      TyTy::BaseType *ref_tyty = nullptr;
! 	      bool ok = context.lookup_type (ref, &ref_tyty);
! 	      if (!ok)
! 		continue;
  
! 	      // if any of the types are inference variables lets fix them
! 	      if (ref_tyty->is<TyTy::InferType> ())
! 		context.insert_implicit_type (ref, resolved);
! 	    }
! 	}
!     }
!   else
!     {
!       auto base_const = resolved->as_const_type ();
!       if (base_const->const_kind () == TyTy::BaseConstType::ConstKind::Value)
! 	{
! 	  rust_debug ("UnifyRules::commit const value, resolved_ref=%u "
! 		      "resolved_ty_ref=%u combined_refs.size=%zu",
! 		      resolved->get_ref (), resolved->get_ty_ref (),
! 		      resolved->get_combined_refs ().size ());
! 
! 	  for (auto &ref : resolved->get_combined_refs ())
! 	    {
! 	      TyTy::BaseType *ref_tyty = nullptr;
! 	      bool ok = context.lookup_type (ref, &ref_tyty);
! 	      if (!ok)
! 		continue;
! 	      if (ref_tyty->get_kind () != TyTy::TypeKind::CONST)
! 		continue;
! 
! 	      auto ref_base_const = ref_tyty->as_const_type ();
! 	      if (ref_base_const->const_kind ()
! 		    == TyTy::BaseConstType::ConstKind::Infer
! 		  || ref_base_const->const_kind ()
! 		       == TyTy::BaseConstType::ConstKind::Decl)
! 		{
! 		  rust_debug ("  committing to ref=%u kind=%d", ref,
! 			      (int) ref_base_const->const_kind ());
! 		  context.insert_implicit_type (ref, resolved);
! 		}
! 	    }
  	}
      }
  }
*************** UnifyRules::emit_abi_mismatch (const TyT
*** 155,193 ****
  TyTy::BaseType *
  UnifyRules::go ()
  {
!   TyTy::BaseType *ltype = lhs.get_ty ();
!   TyTy::BaseType *rtype = rhs.get_ty ();
! 
!   ltype = lhs.get_ty ()->destructure ();
!   rtype = rhs.get_ty ()->destructure ();
  
    rust_debug ("unify::go ltype={%s} rtype={%s}", ltype->debug_str ().c_str (),
  	      rtype->debug_str ().c_str ());
  
!   // check bounds
!   bool ltype_is_placeholder = ltype->get_kind () == TyTy::TypeKind::PLACEHOLDER;
!   bool rtype_is_placeholder = rtype->get_kind () == TyTy::TypeKind::PLACEHOLDER;
!   bool types_equal = ltype->is_equal (*rtype);
!   bool should_check_bounds
!     = !types_equal && !(ltype_is_placeholder || rtype_is_placeholder);
!   if (should_check_bounds)
      {
!       if (ltype->num_specified_bounds () > 0)
  	{
! 	  if (!ltype->bounds_compatible (*rtype, locus, emit_error))
  	    {
! 	      // already emitted an error
! 	      emit_error = false;
! 	      return new TyTy::ErrorType (0);
  	    }
! 	}
!       else if (rtype->num_specified_bounds () > 0)
! 	{
! 	  if (!rtype->bounds_compatible (*ltype, locus, emit_error))
  	    {
! 	      // already emitted an error
! 	      emit_error = false;
! 	      return new TyTy::ErrorType (0);
  	    }
  	}
      }
--- 205,244 ----
  TyTy::BaseType *
  UnifyRules::go ()
  {
!   TyTy::BaseType *ltype = lhs.get_ty ()->destructure ();
!   TyTy::BaseType *rtype = rhs.get_ty ()->destructure ();
  
    rust_debug ("unify::go ltype={%s} rtype={%s}", ltype->debug_str ().c_str (),
  	      rtype->debug_str ().c_str ());
  
!   if (check_bounds_flag)
      {
!       bool ltype_is_placeholder
! 	= ltype->get_kind () == TyTy::TypeKind::PLACEHOLDER;
!       bool rtype_is_placeholder
! 	= rtype->get_kind () == TyTy::TypeKind::PLACEHOLDER;
!       bool types_equal = ltype->is_equal (*rtype);
!       bool should_check_bounds
! 	= !types_equal && !(ltype_is_placeholder || rtype_is_placeholder);
!       if (should_check_bounds)
  	{
! 	  if (ltype->num_specified_bounds () > 0)
  	    {
! 	      if (!ltype->bounds_compatible (*rtype, locus, emit_error))
! 		{
! 		  // already emitted an error
! 		  emit_error = false;
! 		  return unify_error_type_node ();
! 		}
  	    }
! 	  else if (rtype->num_specified_bounds () > 0)
  	    {
! 	      if (!rtype->bounds_compatible (*ltype, locus, emit_error))
! 		{
! 		  // already emitted an error
! 		  emit_error = false;
! 		  return unify_error_type_node ();
! 		}
  	    }
  	}
      }
*************** UnifyRules::go ()
*** 222,228 ****
  	  rust_assert (iv.get_tyty ()->get_kind () == TyTy::TypeKind::INFER);
  	  TyTy::InferType *i = static_cast<TyTy::InferType *> (iv.get_tyty ());
  
! 	  infers.push_back ({p->get_ref (), p->get_ty_ref (), p, i});
  
  	  // FIXME
  	  // this is hacky to set the implicit param lets make this a function
--- 273,279 ----
  	  rust_assert (iv.get_tyty ()->get_kind () == TyTy::TypeKind::INFER);
  	  TyTy::InferType *i = static_cast<TyTy::InferType *> (iv.get_tyty ());
  
! 	  infers.emplace_back (p->get_ref (), p->get_ty_ref (), p, i);
  
  	  // FIXME
  	  // this is hacky to set the implicit param lets make this a function
*************** UnifyRules::go ()
*** 239,245 ****
  	  rust_assert (iv.get_tyty ()->get_kind () == TyTy::TypeKind::INFER);
  	  TyTy::InferType *i = static_cast<TyTy::InferType *> (iv.get_tyty ());
  
! 	  infers.push_back ({p->get_ref (), p->get_ty_ref (), p, i});
  
  	  // FIXME
  	  // this is hacky to set the implicit param lets make this a function
--- 290,296 ----
  	  rust_assert (iv.get_tyty ()->get_kind () == TyTy::TypeKind::INFER);
  	  TyTy::InferType *i = static_cast<TyTy::InferType *> (iv.get_tyty ());
  
! 	  infers.emplace_back (p->get_ref (), p->get_ty_ref (), p, i);
  
  	  // FIXME
  	  // this is hacky to set the implicit param lets make this a function
*************** UnifyRules::go ()
*** 248,253 ****
--- 299,334 ----
  	  // set the rtype now to the new inference var
  	  ltype = i;
  	}
+       else if (ltype->get_kind () == TyTy::TypeKind::CONST
+ 	       && rtype->get_kind () == TyTy::TypeKind::CONST)
+ 	{
+ 	  const auto &lhs = *ltype->as_const_type ();
+ 	  const auto &rhs = *rtype->as_const_type ();
+ 
+ 	  bool both_are_decls
+ 	    = lhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl
+ 	      && rhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl;
+ 	  bool have_decls
+ 	    = lhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl
+ 	      || rhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl;
+ 
+ 	  if (have_decls && !both_are_decls)
+ 	    {
+ 	      if (lhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl)
+ 		{
+ 		  TyTy::TyVar iv = TyTy::TyVar::get_implicit_const_infer_var (
+ 		    lhs.as_base_type ()->get_locus ());
+ 		  ltype = iv.get_tyty ();
+ 		}
+ 	      else if (rhs.const_kind ()
+ 		       == TyTy::BaseConstType::ConstKind::Decl)
+ 		{
+ 		  TyTy::TyVar iv = TyTy::TyVar::get_implicit_const_infer_var (
+ 		    rhs.as_base_type ()->get_locus ());
+ 		  rtype = iv.get_tyty ();
+ 		}
+ 	    }
+ 	}
      }
  
    switch (ltype->get_kind ())
*************** UnifyRules::go ()
*** 329,341 ****
        return expect_opaque (static_cast<TyTy::OpaqueType *> (ltype), rtype);
  
      case TyTy::CONST:
!       return expect_const (static_cast<TyTy::ConstType *> (ltype), rtype);
  
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
  
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 410,422 ----
        return expect_opaque (static_cast<TyTy::OpaqueType *> (ltype), rtype);
  
      case TyTy::CONST:
!       return expect_const (ltype->as_const_type (), rtype);
  
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
  
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_inference_variable (T
*** 350,356 ****
  	switch (ltype->get_infer_kind ())
  	  {
  	  case TyTy::InferType::InferTypeKind::GENERAL:
! 	    return rtype->clone ();
  
  	  case TyTy::InferType::InferTypeKind::INTEGRAL:
  	    {
--- 431,437 ----
  	switch (ltype->get_infer_kind ())
  	  {
  	  case TyTy::InferType::InferTypeKind::GENERAL:
! 	    return rtype;
  
  	  case TyTy::InferType::InferTypeKind::INTEGRAL:
  	    {
*************** UnifyRules::expect_inference_variable (T
*** 388,394 ****
  			    == TyTy::InferType::InferTypeKind::INTEGRAL);
  	if (is_valid)
  	  {
! 	    ltype->apply_primitive_type_hint (*rtype);
  	    return rtype;
  	  }
        }
--- 469,476 ----
  			    == TyTy::InferType::InferTypeKind::INTEGRAL);
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      ltype->apply_primitive_type_hint (*rtype);
  	    return rtype;
  	  }
        }
*************** UnifyRules::expect_inference_variable (T
*** 402,408 ****
  			    == TyTy::InferType::InferTypeKind::FLOAT);
  	if (is_valid)
  	  {
! 	    ltype->apply_primitive_type_hint (*rtype);
  	    return rtype;
  	  }
        }
--- 484,491 ----
  			    == TyTy::InferType::InferTypeKind::FLOAT);
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      ltype->apply_primitive_type_hint (*rtype);
  	    return rtype;
  	  }
        }
*************** UnifyRules::expect_inference_variable (T
*** 431,445 ****
  	bool is_valid = (ltype->get_infer_kind ()
  			 == TyTy::InferType::InferTypeKind::GENERAL);
  	if (is_valid)
! 	  return rtype->clone ();
        }
        break;
  
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
  
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 514,528 ----
  	bool is_valid = (ltype->get_infer_kind ()
  			 == TyTy::InferType::InferTypeKind::GENERAL);
  	if (is_valid)
! 	  return rtype;
        }
        break;
  
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
  
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_adt (TyTy::ADTType *l
*** 453,459 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 536,542 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_adt (TyTy::ADTType *l
*** 462,478 ****
  	TyTy::ADTType &type = *static_cast<TyTy::ADTType *> (rtype);
  	if (ltype->get_adt_kind () != type.get_adt_kind ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	if (ltype->get_identifier ().compare (type.get_identifier ()) != 0)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	if (ltype->number_of_variants () != type.number_of_variants ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	for (size_t i = 0; i < type.number_of_variants (); ++i)
--- 545,561 ----
  	TyTy::ADTType &type = *static_cast<TyTy::ADTType *> (rtype);
  	if (ltype->get_adt_kind () != type.get_adt_kind ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	if (ltype->get_identifier ().compare (type.get_identifier ()) != 0)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	if (ltype->number_of_variants () != type.number_of_variants ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	for (size_t i = 0; i < type.number_of_variants (); ++i)
*************** UnifyRules::expect_adt (TyTy::ADTType *l
*** 482,488 ****
  
  	    if (a->num_fields () != b->num_fields ())
  	      {
! 		return new TyTy::ErrorType (0);
  	      }
  
  	    for (size_t j = 0; j < a->num_fields (); j++)
--- 565,571 ----
  
  	    if (a->num_fields () != b->num_fields ())
  	      {
! 		return unify_error_type_node ();
  	      }
  
  	    for (size_t j = 0; j < a->num_fields (); j++)
*************** UnifyRules::expect_adt (TyTy::ADTType *l
*** 498,504 ****
  				     TyTy::TyWithLocation (other_field_ty));
  		if (unified_ty->get_kind () == TyTy::TypeKind::ERROR)
  		  {
! 		    return new TyTy::ErrorType (0);
  		  }
  	      }
  	  }
--- 581,587 ----
  				     TyTy::TyWithLocation (other_field_ty));
  		if (unified_ty->get_kind () == TyTy::TypeKind::ERROR)
  		  {
! 		    return unify_error_type_node ();
  		  }
  	      }
  	  }
*************** UnifyRules::expect_adt (TyTy::ADTType *l
*** 521,532 ****
  					    TyTy::TyWithLocation (pb));
  		if (res->get_kind () == TyTy::TypeKind::ERROR)
  		  {
! 		    return new TyTy::ErrorType (0);
  		  }
  	      }
  	  }
  
! 	return type.clone ();
        }
        break;
  
--- 604,615 ----
  					    TyTy::TyWithLocation (pb));
  		if (res->get_kind () == TyTy::TypeKind::ERROR)
  		  {
! 		    return unify_error_type_node ();
  		  }
  	      }
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_adt (TyTy::ADTType *l
*** 554,562 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 637,645 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_str (TyTy::StrType *l
*** 570,581 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
      case TyTy::STR:
!       return rtype->clone ();
  
      case TyTy::ADT:
      case TyTy::REF:
--- 653,664 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
      case TyTy::STR:
!       return rtype;
  
      case TyTy::ADT:
      case TyTy::REF:
*************** UnifyRules::expect_str (TyTy::StrType *l
*** 601,609 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 684,692 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_reference (TyTy::Refe
*** 617,623 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 700,706 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_reference (TyTy::Refe
*** 632,638 ****
  			     TyTy::TyWithLocation (other_base_type));
  	if (base_resolved->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	// rust is permissive about mutablity here you can always go from
--- 715,721 ----
  			     TyTy::TyWithLocation (other_base_type));
  	if (base_resolved->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	// rust is permissive about mutablity here you can always go from
*************** UnifyRules::expect_reference (TyTy::Refe
*** 640,651 ****
  	bool mutability_ok = ltype->is_mutable () ? type.is_mutable () : true;
  	if (!mutability_ok)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
! 	return new TyTy::ReferenceType (ltype->get_ref (), ltype->get_ty_ref (),
! 					TyTy::TyVar (base_resolved->get_ref ()),
! 					ltype->mutability ());
        }
        break;
  
--- 723,732 ----
  	bool mutability_ok = ltype->is_mutable () ? type.is_mutable () : true;
  	if (!mutability_ok)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_reference (TyTy::Refe
*** 673,681 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 754,762 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_pointer (TyTy::Pointe
*** 689,695 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 770,776 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_pointer (TyTy::Pointe
*** 704,710 ****
  			     TyTy::TyWithLocation (other_base_type));
  	if (base_resolved->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	// rust is permissive about mutablity here you can always go from
--- 785,791 ----
  			     TyTy::TyWithLocation (other_base_type));
  	if (base_resolved->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	// rust is permissive about mutablity here you can always go from
*************** UnifyRules::expect_pointer (TyTy::Pointe
*** 712,723 ****
  	bool mutability_ok = ltype->is_mutable () ? type.is_mutable () : true;
  	if (!mutability_ok)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
! 	return new TyTy::PointerType (ltype->get_ref (), ltype->get_ty_ref (),
! 				      TyTy::TyVar (base_resolved->get_ref ()),
! 				      ltype->mutability ());
        }
        break;
  
--- 793,802 ----
  	bool mutability_ok = ltype->is_mutable () ? type.is_mutable () : true;
  	if (!mutability_ok)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_pointer (TyTy::Pointe
*** 745,753 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 824,832 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_param (TyTy::ParamTyp
*** 761,767 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 840,846 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_param (TyTy::ParamTyp
*** 810,818 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 889,897 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_array (TyTy::ArrayTyp
*** 826,832 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 905,911 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_array (TyTy::ArrayTyp
*** 838,861 ****
  			     TyTy::TyWithLocation (type.get_element_type ()));
  
  	if (element_unify->get_kind () == TyTy::TypeKind::ERROR)
! 	  return new TyTy::ErrorType (0);
  
  	bool save_emit_error = emit_error;
  	emit_error = false;
  	TyTy::BaseType *capacity_unify
! 	  = resolve_subtype (TyTy::TyWithLocation (ltype->get_capacity ()),
! 			     TyTy::TyWithLocation (type.get_capacity ()));
  	emit_error = save_emit_error;
  
  	if (capacity_unify->get_kind () != TyTy::TypeKind::CONST)
! 	  return new TyTy::ErrorType (0);
  
! 	TyTy::ConstType *capacity_type_unify
! 	  = static_cast<TyTy::ConstType *> (capacity_unify);
! 	return new TyTy::ArrayType (type.get_ref (), type.get_ty_ref (),
! 				    type.get_ident ().locus,
! 				    capacity_type_unify,
! 				    TyTy::TyVar (element_unify->get_ref ()));
        }
        break;
  
--- 917,951 ----
  			     TyTy::TyWithLocation (type.get_element_type ()));
  
  	if (element_unify->get_kind () == TyTy::TypeKind::ERROR)
! 	  return unify_error_type_node ();
! 
! 	auto ltype_cap = ltype->get_capacity ();
! 	auto rtype_cap = type.get_capacity ();
! 
! 	// If either capacity is not a const type, return error
! 	if (ltype_cap->get_kind () != TyTy::TypeKind::CONST
! 	    || rtype_cap->get_kind () != TyTy::TypeKind::CONST)
! 	  return unify_error_type_node ();
  
  	bool save_emit_error = emit_error;
  	emit_error = false;
  	TyTy::BaseType *capacity_unify
! 	  = resolve_subtype (TyTy::TyWithLocation (ltype_cap),
! 			     TyTy::TyWithLocation (rtype_cap));
  	emit_error = save_emit_error;
  
  	if (capacity_unify->get_kind () != TyTy::TypeKind::CONST)
! 	  return unify_error_type_node ();
  
! 	auto capacity_type_unify = capacity_unify->as_const_type ();
! 	if (capacity_type_unify->const_kind ()
! 	    == TyTy::BaseConstType::ConstKind::Error)
! 	  return unify_error_type_node ();
! 
! 	return new TyTy::ArrayType (
! 	  type.get_ref (), type.get_ty_ref (), type.get_ident ().locus,
! 	  TyTy::TyVar (capacity_type_unify->as_base_type ()->get_ref ()),
! 	  TyTy::TyVar (element_unify->get_ref ()));
        }
        break;
  
*************** UnifyRules::expect_array (TyTy::ArrayTyp
*** 883,891 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 973,981 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_slice (TyTy::SliceTyp
*** 899,905 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 989,995 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_slice (TyTy::SliceTyp
*** 911,922 ****
  			     TyTy::TyWithLocation (type.get_element_type ()));
  
  	if (element_unify->get_kind () != TyTy::TypeKind::ERROR)
! 	  {
! 	    return new TyTy::SliceType (type.get_ref (), type.get_ty_ref (),
! 					type.get_ident ().locus,
! 					TyTy::TyVar (
! 					  element_unify->get_ref ()));
! 	  }
        }
        break;
  
--- 1001,1007 ----
  			     TyTy::TyWithLocation (type.get_element_type ()));
  
  	if (element_unify->get_kind () != TyTy::TypeKind::ERROR)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_slice (TyTy::SliceTyp
*** 944,952 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1029,1037 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_fndef (TyTy::FnType *
*** 960,966 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 1045,1051 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_fndef (TyTy::FnType *
*** 969,975 ****
  	TyTy::FnType &type = *static_cast<TyTy::FnType *> (rtype);
  	if (ltype->num_params () != type.num_params ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
--- 1054,1060 ----
  	TyTy::FnType &type = *static_cast<TyTy::FnType *> (rtype);
  	if (ltype->num_params () != type.num_params ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
*************** UnifyRules::expect_fndef (TyTy::FnType *
*** 981,987 ****
  						  TyTy::TyWithLocation (b));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return new TyTy::ErrorType (0);
  	      }
  	  }
  
--- 1066,1072 ----
  						  TyTy::TyWithLocation (b));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return unify_error_type_node ();
  	      }
  	  }
  
*************** UnifyRules::expect_fndef (TyTy::FnType *
*** 990,996 ****
  			     TyTy::TyWithLocation (type.get_return_type ()));
  	if (unified_return->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	// ABI match? see
--- 1075,1081 ----
  			     TyTy::TyWithLocation (type.get_return_type ()));
  	if (unified_return->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	// ABI match? see
*************** UnifyRules::expect_fndef (TyTy::FnType *
*** 1001,1012 ****
  	      {
  		emit_abi_mismatch (*ltype, type);
  	      }
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	// DEF Id match? see https://github.com/Rust-GCC/gccrs/issues/2053
  
! 	return ltype->clone ();
        }
        break;
  
--- 1086,1097 ----
  	      {
  		emit_abi_mismatch (*ltype, type);
  	      }
! 	    return unify_error_type_node ();
  	  }
  
  	// DEF Id match? see https://github.com/Rust-GCC/gccrs/issues/2053
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_fndef (TyTy::FnType *
*** 1034,1042 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1119,1127 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1050,1056 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 1135,1141 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1059,1065 ****
  	TyTy::FnPtr &type = *static_cast<TyTy::FnPtr *> (rtype);
  	if (ltype->num_params () != type.num_params ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
--- 1144,1150 ----
  	TyTy::FnPtr &type = *static_cast<TyTy::FnPtr *> (rtype);
  	if (ltype->num_params () != type.num_params ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1071,1077 ****
  						  TyTy::TyWithLocation (b));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return new TyTy::ErrorType (0);
  	      }
  	  }
  
--- 1156,1162 ----
  						  TyTy::TyWithLocation (b));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return unify_error_type_node ();
  	      }
  	  }
  
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1080,1089 ****
  			     TyTy::TyWithLocation (type.get_return_type ()));
  	if (unified_return->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
! 	return ltype->clone ();
        }
        break;
  
--- 1165,1184 ----
  			     TyTy::TyWithLocation (type.get_return_type ()));
  	if (unified_return->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
! 	if (ltype->get_abi () != type.get_abi ())
! 	  {
! 	    return unify_error_type_node ();
! 	  }
! 
! 	if (ltype->get_unsafety () != type.get_unsafety ())
! 	  {
! 	    return unify_error_type_node ();
! 	  }
! 
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1098,1109 ****
  			     TyTy::TyWithLocation (other_ret_type));
  	if (unified_result->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	if (ltype->num_params () != type.num_params ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
--- 1193,1204 ----
  			     TyTy::TyWithLocation (other_ret_type));
  	if (unified_result->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	if (ltype->num_params () != type.num_params ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1116,1126 ****
  				 TyTy::TyWithLocation (other_param));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return new TyTy::ErrorType (0);
  	      }
  	  }
  
! 	return ltype->clone ();
        }
        break;
  
--- 1211,1240 ----
  				 TyTy::TyWithLocation (other_param));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return unify_error_type_node ();
  	      }
  	  }
  
! 	// FIXME
! 	//
! 	// there is a bug in:
! 	// testsuite/rust/compile/try-catch-unwind-{new,old}.rs I think the test
! 	//
! 	// case is wrong because it should be taking an FnOnce which probably
! 	// didnt exist at the time in gccrs
! 	//
! 	// if (ltype->get_abi () != type.get_abi ())
! 	//   {
! 	//     return unify_error_type_node ();
! 	//   }
! 
! 	// FIXME fntype needs to track unsafe or not
! 	// if (ltype->get_unsafety () != type.get_unsafety ())
! 	//   {
! 	//     return unify_error_type_node ();
! 	//   }
! 
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1135,1146 ****
  			     TyTy::TyWithLocation (other_ret_type));
  	if (unified_result->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	if (ltype->num_params () != type.get_num_params ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
--- 1249,1260 ----
  			     TyTy::TyWithLocation (other_ret_type));
  	if (unified_result->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	if (ltype->num_params () != type.get_num_params ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	for (size_t i = 0; i < ltype->num_params (); i++)
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1153,1163 ****
  				 TyTy::TyWithLocation (other_param));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return new TyTy::ErrorType (0);
  	      }
  	  }
  
! 	return ltype->clone ();
        }
        break;
  
--- 1267,1277 ----
  				 TyTy::TyWithLocation (other_param));
  	    if (unified_param->get_kind () == TyTy::TypeKind::ERROR)
  	      {
! 		return unify_error_type_node ();
  	      }
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_fnptr (TyTy::FnPtr *l
*** 1183,1191 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1297,1305 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_tuple (TyTy::TupleTyp
*** 1199,1205 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 1313,1319 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_tuple (TyTy::TupleTyp
*** 1208,1214 ****
  	TyTy::TupleType &type = *static_cast<TyTy::TupleType *> (rtype);
  	if (ltype->num_fields () != type.num_fields ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	std::vector<TyTy::TyVar> fields;
--- 1322,1328 ----
  	TyTy::TupleType &type = *static_cast<TyTy::TupleType *> (rtype);
  	if (ltype->num_fields () != type.num_fields ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	std::vector<TyTy::TyVar> fields;
*************** UnifyRules::expect_tuple (TyTy::TupleTyp
*** 1221,1233 ****
  	      = resolve_subtype (TyTy::TyWithLocation (bo),
  				 TyTy::TyWithLocation (fo));
  	    if (unified_ty->get_kind () == TyTy::TypeKind::ERROR)
! 	      return new TyTy::ErrorType (0);
  
! 	    fields.push_back (TyTy::TyVar (unified_ty->get_ref ()));
  	  }
  
! 	return new TyTy::TupleType (type.get_ref (), type.get_ty_ref (),
! 				    type.get_ident ().locus, fields);
        }
        break;
  
--- 1335,1346 ----
  	      = resolve_subtype (TyTy::TyWithLocation (bo),
  				 TyTy::TyWithLocation (fo));
  	    if (unified_ty->get_kind () == TyTy::TypeKind::ERROR)
! 	      return unify_error_type_node ();
  
! 	    fields.emplace_back (unified_ty->get_ref ());
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_tuple (TyTy::TupleTyp
*** 1255,1263 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1368,1376 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_bool (TyTy::BoolType
*** 1272,1285 ****
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
  
      case TyTy::BOOL:
!       return rtype->clone ();
  
      case TyTy::CHAR:
      case TyTy::INT:
--- 1385,1399 ----
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
  
      case TyTy::BOOL:
!       return rtype;
  
      case TyTy::CHAR:
      case TyTy::INT:
*************** UnifyRules::expect_bool (TyTy::BoolType
*** 1305,1313 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1419,1427 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_char (TyTy::CharType
*** 1322,1335 ****
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
  
      case TyTy::CHAR:
!       return rtype->clone ();
  
      case TyTy::INT:
      case TyTy::FLOAT:
--- 1436,1450 ----
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
  
      case TyTy::CHAR:
!       return rtype;
  
      case TyTy::INT:
      case TyTy::FLOAT:
*************** UnifyRules::expect_char (TyTy::CharType
*** 1355,1363 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1470,1478 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_int (TyTy::IntType *l
*** 1373,1380 ****
  	    || r->get_infer_kind () == TyTy::InferType::InferTypeKind::INTEGRAL;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
--- 1488,1496 ----
  	    || r->get_infer_kind () == TyTy::InferType::InferTypeKind::INTEGRAL;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
*************** UnifyRules::expect_int (TyTy::IntType *l
*** 1384,1391 ****
  	TyTy::IntType &type = *static_cast<TyTy::IntType *> (rtype);
  	bool is_valid = ltype->get_int_kind () == type.get_int_kind ();
  	if (is_valid)
! 	  return new TyTy::IntType (type.get_ref (), type.get_ty_ref (),
! 				    type.get_int_kind ());
        }
        break;
  
--- 1500,1506 ----
  	TyTy::IntType &type = *static_cast<TyTy::IntType *> (rtype);
  	bool is_valid = ltype->get_int_kind () == type.get_int_kind ();
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_int (TyTy::IntType *l
*** 1413,1421 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1528,1536 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_uint (TyTy::UintType
*** 1431,1438 ****
  	    || r->get_infer_kind () == TyTy::InferType::InferTypeKind::INTEGRAL;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
--- 1546,1554 ----
  	    || r->get_infer_kind () == TyTy::InferType::InferTypeKind::INTEGRAL;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
*************** UnifyRules::expect_uint (TyTy::UintType
*** 1442,1449 ****
  	TyTy::UintType &type = *static_cast<TyTy::UintType *> (rtype);
  	bool is_valid = ltype->get_uint_kind () == type.get_uint_kind ();
  	if (is_valid)
! 	  return new TyTy::UintType (type.get_ref (), type.get_ty_ref (),
! 				     type.get_uint_kind ());
        }
        break;
  
--- 1558,1564 ----
  	TyTy::UintType &type = *static_cast<TyTy::UintType *> (rtype);
  	bool is_valid = ltype->get_uint_kind () == type.get_uint_kind ();
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_uint (TyTy::UintType
*** 1471,1479 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1586,1594 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_float (TyTy::FloatTyp
*** 1489,1496 ****
  	    || r->get_infer_kind () == TyTy::InferType::InferTypeKind::FLOAT;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
--- 1604,1612 ----
  	    || r->get_infer_kind () == TyTy::InferType::InferTypeKind::FLOAT;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
*************** UnifyRules::expect_float (TyTy::FloatTyp
*** 1500,1507 ****
  	TyTy::FloatType &type = *static_cast<TyTy::FloatType *> (rtype);
  	bool is_valid = ltype->get_float_kind () == type.get_float_kind ();
  	if (is_valid)
! 	  return new TyTy::FloatType (type.get_ref (), type.get_ty_ref (),
! 				      type.get_float_kind ());
        }
        break;
  
--- 1616,1622 ----
  	TyTy::FloatType &type = *static_cast<TyTy::FloatType *> (rtype);
  	bool is_valid = ltype->get_float_kind () == type.get_float_kind ();
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_float (TyTy::FloatTyp
*** 1529,1537 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1644,1652 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_isize (TyTy::ISizeTyp
*** 1546,1559 ****
  	  = r->get_infer_kind () != TyTy::InferType::InferTypeKind::FLOAT;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
  
      case TyTy::ISIZE:
!       return rtype->clone ();
  
      case TyTy::ADT:
      case TyTy::STR:
--- 1661,1675 ----
  	  = r->get_infer_kind () != TyTy::InferType::InferTypeKind::FLOAT;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
  
      case TyTy::ISIZE:
!       return rtype;
  
      case TyTy::ADT:
      case TyTy::STR:
*************** UnifyRules::expect_isize (TyTy::ISizeTyp
*** 1579,1587 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1695,1703 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_usize (TyTy::USizeTyp
*** 1596,1609 ****
  	  = r->get_infer_kind () != TyTy::InferType::InferTypeKind::FLOAT;
  	if (is_valid)
  	  {
! 	    r->apply_primitive_type_hint (*ltype);
! 	    return ltype->clone ();
  	  }
        }
        break;
  
      case TyTy::USIZE:
!       return rtype->clone ();
  
      case TyTy::ADT:
      case TyTy::STR:
--- 1712,1726 ----
  	  = r->get_infer_kind () != TyTy::InferType::InferTypeKind::FLOAT;
  	if (is_valid)
  	  {
! 	    if (commit_flag)
! 	      r->apply_primitive_type_hint (*ltype);
! 	    return ltype;
  	  }
        }
        break;
  
      case TyTy::USIZE:
!       return rtype;
  
      case TyTy::ADT:
      case TyTy::STR:
*************** UnifyRules::expect_usize (TyTy::USizeTyp
*** 1629,1637 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1746,1754 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_never (TyTy::NeverTyp
*** 1645,1658 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
      default:
!       return rtype->clone ();
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1762,1775 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
      default:
!       return rtype;
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_placeholder (TyTy::Pl
*** 1667,1678 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
      case TyTy::PLACEHOLDER:
!       return ltype->clone ();
  
      case TyTy::PROJECTION:
      case TyTy::DYNAMIC:
--- 1784,1795 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
      case TyTy::PLACEHOLDER:
!       return ltype;
  
      case TyTy::PROJECTION:
      case TyTy::DYNAMIC:
*************** UnifyRules::expect_placeholder (TyTy::Pl
*** 1697,1710 ****
      case TyTy::NEVER:
      case TyTy::OPAQUE:
        if (infer_flag)
! 	return rtype->clone ();
        gcc_fallthrough ();
  
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1814,1827 ----
      case TyTy::NEVER:
      case TyTy::OPAQUE:
        if (infer_flag)
! 	return rtype;
        gcc_fallthrough ();
  
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_projection (TyTy::Pro
*** 1719,1725 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 1836,1842 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_projection (TyTy::Pro
*** 1752,1760 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1869,1877 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_dyn (TyTy::DynamicObj
*** 1768,1774 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 1885,1891 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_dyn (TyTy::DynamicObj
*** 1778,1792 ****
  	  = *static_cast<TyTy::DynamicObjectType *> (rtype);
  	if (ltype->num_specified_bounds () != type.num_specified_bounds ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	if (!ltype->bounds_compatible (type, locus, true))
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
! 	return ltype->clone ();
        }
        break;
  
--- 1895,1909 ----
  	  = *static_cast<TyTy::DynamicObjectType *> (rtype);
  	if (ltype->num_specified_bounds () != type.num_specified_bounds ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	if (!ltype->bounds_compatible (type, locus, true))
  	  {
! 	    return unify_error_type_node ();
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_dyn (TyTy::DynamicObj
*** 1814,1822 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 1931,1939 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_closure (TyTy::Closur
*** 1830,1836 ****
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype->clone ();
        }
        break;
  
--- 1947,1953 ----
  	bool is_valid
  	  = r->get_infer_kind () == TyTy::InferType::InferTypeKind::GENERAL;
  	if (is_valid)
! 	  return ltype;
        }
        break;
  
*************** UnifyRules::expect_closure (TyTy::Closur
*** 1839,1845 ****
  	TyTy::ClosureType &type = *static_cast<TyTy::ClosureType *> (rtype);
  	if (ltype->get_def_id () != type.get_def_id ())
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	TyTy::BaseType *args_res
--- 1956,1962 ----
  	TyTy::ClosureType &type = *static_cast<TyTy::ClosureType *> (rtype);
  	if (ltype->get_def_id () != type.get_def_id ())
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	TyTy::BaseType *args_res
*************** UnifyRules::expect_closure (TyTy::Closur
*** 1847,1853 ****
  			     TyTy::TyWithLocation (&type.get_parameters ()));
  	if (args_res->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
  	TyTy::BaseType *res
--- 1964,1970 ----
  			     TyTy::TyWithLocation (&type.get_parameters ()));
  	if (args_res->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
  	TyTy::BaseType *res
*************** UnifyRules::expect_closure (TyTy::Closur
*** 1855,1864 ****
  			     TyTy::TyWithLocation (&type.get_result_type ()));
  	if (res == nullptr || res->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return new TyTy::ErrorType (0);
  	  }
  
! 	return ltype->clone ();
        }
        break;
  
--- 1972,1981 ----
  			     TyTy::TyWithLocation (&type.get_result_type ()));
  	if (res == nullptr || res->get_kind () == TyTy::TypeKind::ERROR)
  	  {
! 	    return unify_error_type_node ();
  	  }
  
! 	return ltype;
        }
        break;
  
*************** UnifyRules::expect_closure (TyTy::Closur
*** 1886,1894 ****
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return new TyTy::ErrorType (0);
      }
!   return new TyTy::ErrorType (0);
  }
  
  TyTy::BaseType *
--- 2003,2011 ----
      case TyTy::OPAQUE:
      case TyTy::CONST:
      case TyTy::ERROR:
!       return unify_error_type_node ();
      }
!   return unify_error_type_node ();
  }
  
  TyTy::BaseType *
*************** UnifyRules::expect_opaque (TyTy::OpaqueT
*** 1898,1904 ****
      {
        TyTy::OpaqueType *ro = rtype->as<TyTy::OpaqueType> ();
        if (!ltype->is_equal (*ro))
! 	return new TyTy::ErrorType (0);
  
        if (ltype->can_resolve () && ro->can_resolve ())
  	{
--- 2015,2021 ----
      {
        TyTy::OpaqueType *ro = rtype->as<TyTy::OpaqueType> ();
        if (!ltype->is_equal (*ro))
! 	return unify_error_type_node ();
  
        if (ltype->can_resolve () && ro->can_resolve ())
  	{
*************** UnifyRules::expect_opaque (TyTy::OpaqueT
*** 1908,1914 ****
  	  auto res = resolve_subtype (TyTy::TyWithLocation (lr),
  				      TyTy::TyWithLocation (rr));
  	  if (res->get_kind () == TyTy::TypeKind::ERROR)
! 	    return new TyTy::ErrorType (0);
  	}
        else if (ltype->can_resolve ())
  	{
--- 2025,2031 ----
  	  auto res = resolve_subtype (TyTy::TyWithLocation (lr),
  				      TyTy::TyWithLocation (rr));
  	  if (res->get_kind () == TyTy::TypeKind::ERROR)
! 	    return unify_error_type_node ();
  	}
        else if (ltype->can_resolve ())
  	{
*************** UnifyRules::expect_opaque (TyTy::OpaqueT
*** 1927,1933 ****
        auto res = resolve_subtype (TyTy::TyWithLocation (underly),
  				  TyTy::TyWithLocation (rtype));
        if (res->get_kind () == TyTy::TypeKind::ERROR)
! 	return new TyTy::ErrorType (0);
      }
    else
      {
--- 2044,2050 ----
        auto res = resolve_subtype (TyTy::TyWithLocation (underly),
  				  TyTy::TyWithLocation (rtype));
        if (res->get_kind () == TyTy::TypeKind::ERROR)
! 	return unify_error_type_node ();
      }
    else
      {
*************** UnifyRules::expect_opaque (TyTy::OpaqueT
*** 1938,2007 ****
  }
  
  TyTy::BaseType *
! UnifyRules::expect_const (TyTy::ConstType *ltype, TyTy::BaseType *rtype)
  {
    if (rtype->get_kind () != TyTy::TypeKind::CONST)
!     return new TyTy::ErrorType (0);
  
!   TyTy::ConstType &lhs = *ltype;
!   TyTy::ConstType &rhs = *static_cast<TyTy::ConstType *> (rtype);
  
!   auto res = resolve_subtype (TyTy::TyWithLocation (lhs.get_ty ()),
! 			      TyTy::TyWithLocation (rhs.get_ty ()));
!   if (res->get_kind () == TyTy::TypeKind::ERROR)
!     return new TyTy::ErrorType (0);
  
!   tree lv = lhs.get_value ();
!   tree rv = rhs.get_value ();
  
!   if (error_operand_p (lv) && error_operand_p (rv))
      {
!       // this is only allowed for some silly senarios like:
!       // gcc/testsuite/rust/compile/issue-const_generics_5.rs
!       if (lhs.get_const_kind () == rhs.get_const_kind ())
  	{
! 	  return new TyTy::ConstType (lhs.get_const_kind (), lhs.get_symbol (),
! 				      res, error_mark_node,
! 				      lhs.get_specified_bounds (),
! 				      lhs.get_locus (), lhs.get_ref (),
! 				      lhs.get_ty_ref (),
! 				      lhs.get_combined_refs ());
  	}
- 
-       return new TyTy::ErrorType (0);
      }
  
!   bool equal = operand_equal_p (lv, rv, 0);
!   if (equal)
      {
!       return new TyTy::ConstType (TyTy::ConstType::ConstKind::Value,
! 				  lhs.get_symbol (), res, lv,
! 				  lhs.get_specified_bounds (), lhs.get_locus (),
! 				  lhs.get_ref (), lhs.get_ty_ref (),
! 				  lhs.get_combined_refs ());
      }
  
!   if (lhs.get_const_kind () == TyTy::ConstType::Infer && !error_operand_p (rv))
      {
!       lhs.set_value (rv);
!       return new TyTy::ConstType (TyTy::ConstType::ConstKind::Value,
! 				  lhs.get_symbol (), res, rv,
! 				  lhs.get_specified_bounds (), lhs.get_locus (),
! 				  lhs.get_ref (), lhs.get_ty_ref (),
! 				  lhs.get_combined_refs ());
      }
!   else if (rhs.get_const_kind () == TyTy::ConstType::Infer
! 	   && !error_operand_p (lv))
      {
!       rhs.set_value (lv);
!       return new TyTy::ConstType (TyTy::ConstType::ConstKind::Value,
! 				  rhs.get_symbol (), res, lv,
! 				  rhs.get_specified_bounds (), rhs.get_locus (),
! 				  rhs.get_ref (), rhs.get_ty_ref (),
! 				  rhs.get_combined_refs ());
      }
  
!   return new TyTy::ErrorType (0);
  }
  
  } // namespace Resolver
--- 2055,2162 ----
  }
  
  TyTy::BaseType *
! UnifyRules::expect_const (TyTy::BaseConstType *ltype, TyTy::BaseType *rtype)
  {
    if (rtype->get_kind () != TyTy::TypeKind::CONST)
!     return unify_error_type_node ();
  
!   auto &lhs = *ltype;
!   auto &rhs = *rtype->as_const_type ();
  
!   // Handle error types early
!   if (lhs.const_kind () == TyTy::BaseConstType::ConstKind::Error
!       || rhs.const_kind () == TyTy::BaseConstType::ConstKind::Error)
!     {
!       auto lhs_base = ltype->as_base_type ();
!       return new TyTy::ConstErrorType (lhs.get_specified_type (),
! 				       lhs_base->get_ref (),
! 				       lhs_base->get_ty_ref (),
! 				       lhs_base->get_combined_refs ());
!     }
  
!   // Try to resolve Decl types (ConstParamType)
!   TyTy::BaseConstType *resolved_lhs = &lhs;
!   TyTy::BaseConstType *resolved_rhs = &rhs;
  
!   if (lhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl)
      {
!       auto *param = static_cast<TyTy::ConstParamType *> (&lhs);
!       if (param->can_resolve ())
  	{
! 	  auto *resolved = param->resolve ();
! 	  if (resolved->get_kind () == TyTy::TypeKind::CONST)
! 	    resolved_lhs = resolved->as_const_type ();
  	}
      }
  
!   if (rhs.const_kind () == TyTy::BaseConstType::ConstKind::Decl)
      {
!       auto *param = static_cast<TyTy::ConstParamType *> (&rhs);
!       if (param->can_resolve ())
! 	{
! 	  auto *resolved = param->resolve ();
! 	  if (resolved->get_kind () == TyTy::TypeKind::CONST)
! 	    resolved_rhs = resolved->as_const_type ();
! 	}
      }
  
!   auto res = resolve_subtype (
!     TyTy::TyWithLocation (resolved_lhs->get_specified_type ()),
!     TyTy::TyWithLocation (resolved_rhs->get_specified_type ()));
!   if (res->get_kind () == TyTy::TypeKind::ERROR)
!     return unify_error_type_node ();
! 
!   if (resolved_lhs->const_kind () == TyTy::BaseConstType::ConstKind::Value
!       && resolved_rhs->const_kind () == TyTy::BaseConstType::ConstKind::Value)
      {
!       auto vlhs = static_cast<TyTy::ConstValueType &> (*resolved_lhs);
!       auto vrhs = static_cast<TyTy::ConstValueType &> (*resolved_rhs);
!       tree lv = vlhs.get_value ();
!       tree rv = vrhs.get_value ();
! 
!       bool ok = operand_equal_p (lv, rv, 0);
!       if (!ok)
! 	return unify_error_type_node ();
!       else
! 	{
! 	  auto lhs_base = resolved_lhs->as_base_type ();
! 	  return new TyTy::ConstValueType (lv, res, lhs_base->get_ref (),
! 					   lhs_base->get_ty_ref (),
! 					   lhs_base->get_combined_refs ());
! 	}
      }
!   else if (resolved_lhs->const_kind () == TyTy::BaseConstType::ConstKind::Infer
! 	   && resolved_rhs->const_kind ()
! 		== TyTy::BaseConstType::ConstKind::Value)
!     return resolved_rhs->as_base_type ();
!   else if (resolved_rhs->const_kind () == TyTy::BaseConstType::ConstKind::Infer
! 	   && resolved_lhs->const_kind ()
! 		== TyTy::BaseConstType::ConstKind::Value)
!     return resolved_lhs->as_base_type ();
!   else if (resolved_lhs->const_kind () == TyTy::BaseConstType::ConstKind::Infer
! 	   && resolved_rhs->const_kind ()
! 		== TyTy::BaseConstType::ConstKind::Infer)
!     return resolved_lhs->as_base_type ();
!   else if (resolved_lhs->const_kind () == TyTy::BaseConstType::ConstKind::Decl
! 	   || resolved_rhs->const_kind ()
! 		== TyTy::BaseConstType::ConstKind::Decl)
      {
!       // If we still have unresolved Decl after trying to resolve, unify with it
!       // This allows const inference to work
!       if (resolved_lhs->const_kind () == TyTy::BaseConstType::ConstKind::Decl
! 	  && resolved_rhs->const_kind ()
! 	       != TyTy::BaseConstType::ConstKind::Decl)
! 	return resolved_rhs->as_base_type ();
!       else if (resolved_rhs->const_kind ()
! 		 == TyTy::BaseConstType::ConstKind::Decl
! 	       && resolved_lhs->const_kind ()
! 		    != TyTy::BaseConstType::ConstKind::Decl)
! 	return resolved_lhs->as_base_type ();
!       // Both are Decl - return lhs
!       return resolved_lhs->as_base_type ();
      }
  
!   return unify_error_type_node ();
  }
  
  } // namespace Resolver
diff -Nrcpad gcc-16-20251026/gcc/rust/typecheck/rust-unify.h gcc-16-20251102/gcc/rust/typecheck/rust-unify.h
*** gcc-16-20251026/gcc/rust/typecheck/rust-unify.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/typecheck/rust-unify.h	Sun Nov  2 22:32:23 2025
*************** class UnifyRules
*** 30,35 ****
--- 30,40 ----
  public:
    struct InferenceSite
    {
+     InferenceSite (HirId pref, HirId ptyref, TyTy::ParamType *param,
+ 		   TyTy::InferType *infer)
+       : pref (pref), ptyref (ptyref), param (param), infer (infer)
+     {}
+ 
      HirId pref;
      HirId ptyref;
      TyTy::ParamType *param;
*************** public:
*** 37,42 ****
--- 42,52 ----
    };
    struct CommitSite
    {
+     CommitSite (TyTy::BaseType *lhs, TyTy::BaseType *rhs,
+ 		TyTy::BaseType *resolved)
+       : lhs (lhs), rhs (rhs), resolved (resolved)
+     {}
+ 
      TyTy::BaseType *lhs;
      TyTy::BaseType *rhs;
      TyTy::BaseType *resolved;
*************** public:
*** 45,50 ****
--- 55,61 ----
    static TyTy::BaseType *Resolve (TyTy::TyWithLocation lhs,
  				  TyTy::TyWithLocation rhs, location_t locus,
  				  bool commit_flag, bool emit_error, bool infer,
+ 				  bool check_bounds,
  				  std::vector<CommitSite> &commits,
  				  std::vector<InferenceSite> &infers);
  
*************** protected:
*** 84,95 ****
  				  TyTy::BaseType *rtype);
    TyTy::BaseType *expect_opaque (TyTy::OpaqueType *ltype,
  				 TyTy::BaseType *rtype);
!   TyTy::BaseType *expect_const (TyTy::ConstType *ltype, TyTy::BaseType *rtype);
  
  private:
    UnifyRules (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  	      location_t locus, bool commit_flag, bool emit_error, bool infer,
! 	      std::vector<CommitSite> &commits,
  	      std::vector<InferenceSite> &infers);
  
    TyTy::BaseType *resolve_subtype (TyTy::TyWithLocation lhs,
--- 95,107 ----
  				  TyTy::BaseType *rtype);
    TyTy::BaseType *expect_opaque (TyTy::OpaqueType *ltype,
  				 TyTy::BaseType *rtype);
!   TyTy::BaseType *expect_const (TyTy::BaseConstType *ltype,
! 				TyTy::BaseType *rtype);
  
  private:
    UnifyRules (TyTy::TyWithLocation lhs, TyTy::TyWithLocation rhs,
  	      location_t locus, bool commit_flag, bool emit_error, bool infer,
! 	      bool check_bounds, std::vector<CommitSite> &commits,
  	      std::vector<InferenceSite> &infers);
  
    TyTy::BaseType *resolve_subtype (TyTy::TyWithLocation lhs,
*************** private:
*** 110,115 ****
--- 122,128 ----
    bool commit_flag;
    bool emit_error;
    bool infer_flag;
+   bool check_bounds_flag;
    std::vector<CommitSite> &commits;
    std::vector<InferenceSite> &infers;
  
diff -Nrcpad gcc-16-20251026/gcc/rust/util/bi-map.h gcc-16-20251102/gcc/rust/util/bi-map.h
*** gcc-16-20251026/gcc/rust/util/bi-map.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/bi-map.h	Sun Nov  2 22:32:23 2025
***************
*** 17,22 ****
--- 17,23 ----
  // <http://www.gnu.org/licenses/>.
  
  #include "rust-system.h"
+ #include "optional.h"
  
  #ifndef BIMAP_H
  #define BIMAP_H
diff -Nrcpad gcc-16-20251026/gcc/rust/util/fnv-hash.h gcc-16-20251102/gcc/rust/util/fnv-hash.h
*** gcc-16-20251026/gcc/rust/util/fnv-hash.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/fnv-hash.h	Sun Nov  2 22:32:23 2025
***************
*** 15,20 ****
--- 15,21 ----
  // You should have received a copy of the GNU General Public License
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
+ #include "rust-system.h"
  
  #ifndef RUST_FNV_HASH_H
  #define RUST_FNV_HASH_H
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-attribute-values.h gcc-16-20251102/gcc/rust/util/rust-attribute-values.h
*** gcc-16-20251026/gcc/rust/util/rust-attribute-values.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-attribute-values.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 36,41 ****
--- 36,42 ----
    static constexpr auto &DOC = "doc";
    static constexpr auto &MUST_USE = "must_use";
    static constexpr auto &LANG = "lang";
+   static constexpr auto &LINK_NAME = "link_name";
    static constexpr auto &LINK_SECTION = "link_section";
    static constexpr auto &NO_MANGLE = "no_mangle";
    static constexpr auto &REPR = "repr";
*************** public:
*** 48,53 ****
--- 49,56 ----
    static constexpr auto &PROC_MACRO_DERIVE = "proc_macro_derive";
    static constexpr auto &PROC_MACRO_ATTRIBUTE = "proc_macro_attribute";
  
+   static constexpr auto &DERIVE = "derive";
+ 
    static constexpr auto &TARGET_FEATURE = "target_feature";
    // From now on, these are reserved by the compiler and gated through
    // #![feature(rustc_attrs)]
*************** public:
*** 60,65 ****
--- 63,70 ----
    static constexpr auto &RUSTC_PROMOTABLE = "rustc_promotable";
    static constexpr auto &RUSTC_CONST_STABLE = "rustc_const_stable";
    static constexpr auto &RUSTC_CONST_UNSTABLE = "rustc_const_unstable";
+   static constexpr auto &RUSTC_ALLOW_CONST_FN_UNSTABLE
+     = "rustc_allow_const_fn_unstable";
  
    static constexpr auto &RUSTC_SPECIALIZATION_TRAIT
      = "rustc_specialization_trait";
*************** public:
*** 88,95 ****
  
    static constexpr auto &TEST = "test";
  
-   static constexpr auto &SIMD_TEST = "simd_test";
- 
    static constexpr auto &RUSTC_ARGS_REQUIRED_CONST
      = "rustc_args_required_const";
  };
--- 93,98 ----
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-attributes.cc gcc-16-20251102/gcc/rust/util/rust-attributes.cc
*** gcc-16-20251026/gcc/rust/util/rust-attributes.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-attributes.cc	Sun Nov  2 22:32:23 2025
*************** Attributes::is_known (const std::string
*** 38,43 ****
--- 38,68 ----
    return !lookup.is_error ();
  }
  
+ tl::optional<std::string>
+ Attributes::extract_string_literal (const AST::Attribute &attr)
+ {
+   if (!attr.has_attr_input ())
+     return tl::nullopt;
+ 
+   auto &attr_input = attr.get_attr_input ();
+ 
+   if (attr_input.get_attr_input_type ()
+       != AST::AttrInput::AttrInputType::LITERAL)
+     return tl::nullopt;
+ 
+   auto &literal_expr
+     = static_cast<AST::AttrInputLiteral &> (attr_input).get_literal ();
+ 
+   auto lit_type = literal_expr.get_lit_type ();
+ 
+   // TODO: bring escape sequence handling out of lexing?
+   if (lit_type != AST::Literal::LitType::STRING
+       && lit_type != AST::Literal::LitType::RAW_STRING)
+     return tl::nullopt;
+ 
+   return literal_expr.as_string ();
+ }
+ 
  using Attrs = Values::Attributes;
  
  // https://doc.rust-lang.org/stable/nightly-rustc/src/rustc_feature/builtin_attrs.rs.html#248
*************** static const BuiltinAttrDefinition __def
*** 53,58 ****
--- 78,84 ----
       {Attrs::DOC, HIR_LOWERING},
       {Attrs::MUST_USE, STATIC_ANALYSIS},
       {Attrs::LANG, HIR_LOWERING},
+      {Attrs::LINK_NAME, CODE_GENERATION},
       {Attrs::LINK_SECTION, CODE_GENERATION},
       {Attrs::NO_MANGLE, CODE_GENERATION},
       {Attrs::REPR, CODE_GENERATION},
*************** static const BuiltinAttrDefinition __def
*** 64,69 ****
--- 90,97 ----
       {Attrs::PROC_MACRO, EXPANSION},
       {Attrs::PROC_MACRO_DERIVE, EXPANSION},
       {Attrs::PROC_MACRO_ATTRIBUTE, EXPANSION},
+ 
+      {Attrs::DERIVE, EXPANSION},
       // FIXME: This is not implemented yet, see
       // https://github.com/Rust-GCC/gccrs/issues/1475
       {Attrs::TARGET_FEATURE, CODE_GENERATION},
*************** static const BuiltinAttrDefinition __def
*** 78,83 ****
--- 106,112 ----
       {Attrs::RUSTC_PROMOTABLE, CODE_GENERATION},
       {Attrs::RUSTC_CONST_STABLE, STATIC_ANALYSIS},
       {Attrs::RUSTC_CONST_UNSTABLE, STATIC_ANALYSIS},
+      {Attrs::RUSTC_ALLOW_CONST_FN_UNSTABLE, STATIC_ANALYSIS},
       {Attrs::PRELUDE_IMPORT, NAME_RESOLUTION},
       {Attrs::TRACK_CALLER, CODE_GENERATION},
       {Attrs::RUSTC_SPECIALIZATION_TRAIT, TYPE_CHECK},
*************** static const BuiltinAttrDefinition __def
*** 100,107 ****
       {Attrs::NON_EXHAUSTIVE, TYPE_CHECK},
       {Attrs::RUSTFMT, EXTERNAL},
  
!      {Attrs::TEST, CODE_GENERATION},
!      {Attrs::SIMD_TEST, CODE_GENERATION}};
  
  BuiltinAttributeMappings *
  BuiltinAttributeMappings::get ()
--- 129,135 ----
       {Attrs::NON_EXHAUSTIVE, TYPE_CHECK},
       {Attrs::RUSTFMT, EXTERNAL},
  
!      {Attrs::TEST, CODE_GENERATION}};
  
  BuiltinAttributeMappings *
  BuiltinAttributeMappings::get ()
*************** AttributeChecker::go (AST::Crate &crate)
*** 144,149 ****
--- 172,178 ----
  void
  AttributeChecker::visit (AST::Crate &crate)
  {
+   check_inner_attributes (crate.get_inner_attrs ());
    check_attributes (crate.get_inner_attrs ());
  
    for (auto &item : crate.items)
*************** check_doc_attribute (const AST::Attribut
*** 214,221 ****
      {
        rust_error_at (
  	attribute.get_locus (),
! 	// FIXME: Improve error message here. Rustc has a very good one
! 	"%<#[doc]%> cannot be an empty attribute");
        return;
      }
  
--- 243,250 ----
      {
        rust_error_at (
  	attribute.get_locus (),
! 	"valid forms for the attribute are "
! 	"%<#[doc(hidden|inline|...)]%> and %<#[doc = \" string \"]%>");
        return;
      }
  
*************** check_proc_macro_non_root (AST::AttrVec
*** 300,305 ****
--- 329,348 ----
  void
  AttributeChecker::check_attribute (const AST::Attribute &attribute)
  {
+   if (!attribute.empty_input ())
+     {
+       const auto &attr_input = attribute.get_attr_input ();
+       auto type = attr_input.get_attr_input_type ();
+       if (type == AST::AttrInput::AttrInputType::TOKEN_TREE)
+ 	{
+ 	  const auto &option = static_cast<const AST::DelimTokenTree &> (
+ 	    attribute.get_attr_input ());
+ 	  std::unique_ptr<AST::AttrInputMetaItemContainer> meta_item (
+ 	    option.parse_to_meta_item ());
+ 	  AST::DefaultASTVisitor::visit (meta_item);
+ 	}
+     }
+ 
    BuiltinAttrDefinition result;
  
    // This checker does not check non-builtin attributes
*************** AttributeChecker::check_attribute (const
*** 314,319 ****
--- 357,371 ----
  }
  
  void
+ AttributeChecker::check_inner_attributes (const AST::AttrVec &attributes)
+ {
+   for (auto &attr : attributes)
+     if (attr.is_derive ())
+       rust_error_at (attr.get_locus (),
+ 		     "derive attribute cannot be used at crate level");
+ }
+ 
+ void
  AttributeChecker::check_attributes (const AST::AttrVec &attributes)
  {
    for (auto &attr : attributes)
*************** AttributeChecker::visit (AST::DelimToken
*** 329,338 ****
  {}
  
  void
- AttributeChecker::visit (AST::AttrInputMetaItemContainer &)
- {}
- 
- void
  AttributeChecker::visit (AST::IdentifierExpr &)
  {}
  
--- 381,386 ----
*************** AttributeChecker::visit (AST::MetaItemLi
*** 395,402 ****
  {}
  
  void
! AttributeChecker::visit (AST::MetaItemPathExpr &)
! {}
  
  void
  AttributeChecker::visit (AST::BorrowExpr &)
--- 443,458 ----
  {}
  
  void
! AttributeChecker::visit (AST::MetaItemPathExpr &attribute)
! {
!   if (!attribute.get_expr ().is_literal ())
!     {
!       rust_error_at (attribute.get_expr ().get_locus (),
! 		     "malformed %<path%> attribute input");
!       rust_inform (attribute.get_expr ().get_locus (),
! 		   "must be of the form: %<#[path = \"file\"]%>");
!     }
! }
  
  void
  AttributeChecker::visit (AST::BorrowExpr &)
*************** AttributeChecker::visit (AST::TypeBoundW
*** 622,627 ****
--- 678,684 ----
  void
  AttributeChecker::visit (AST::Module &module)
  {
+   check_attributes (module.get_outer_attrs ());
    check_proc_macro_non_function (module.get_outer_attrs ());
    for (auto &item : module.get_items ())
      {
*************** AttributeChecker::visit (AST::StaticItem
*** 774,783 ****
  }
  
  void
- AttributeChecker::visit (AST::TraitItemConst &)
- {}
- 
- void
  AttributeChecker::visit (AST::TraitItemType &)
  {}
  
--- 831,836 ----
*************** void
*** 785,790 ****
--- 838,844 ----
  AttributeChecker::visit (AST::Trait &trait)
  {
    check_proc_macro_non_function (trait.get_outer_attrs ());
+   check_attributes (trait.get_outer_attrs ());
  }
  
  void
*************** AttributeChecker::visit (AST::MetaItemPa
*** 841,850 ****
  {}
  
  void
- AttributeChecker::visit (AST::MetaItemSeq &)
- {}
- 
- void
  AttributeChecker::visit (AST::MetaWord &)
  {}
  
--- 895,900 ----
*************** AttributeChecker::visit (AST::StructPatt
*** 920,930 ****
  // void AttributeChecker::visit(TupleStructItems& ){}
  
  void
! AttributeChecker::visit (AST::TupleStructItemsNoRange &)
  {}
  
  void
! AttributeChecker::visit (AST::TupleStructItemsRange &)
  {}
  
  void
--- 970,980 ----
  // void AttributeChecker::visit(TupleStructItems& ){}
  
  void
! AttributeChecker::visit (AST::TupleStructItemsNoRest &)
  {}
  
  void
! AttributeChecker::visit (AST::TupleStructItemsHasRest &)
  {}
  
  void
*************** AttributeChecker::visit (AST::TupleStruc
*** 934,944 ****
  // void AttributeChecker::visit(TuplePatternItems& ){}
  
  void
! AttributeChecker::visit (AST::TuplePatternItemsMultiple &)
  {}
  
  void
! AttributeChecker::visit (AST::TuplePatternItemsRanged &)
  {}
  
  void
--- 984,994 ----
  // void AttributeChecker::visit(TuplePatternItems& ){}
  
  void
! AttributeChecker::visit (AST::TuplePatternItemsNoRest &)
  {}
  
  void
! AttributeChecker::visit (AST::TuplePatternItemsHasRest &)
  {}
  
  void
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-attributes.h gcc-16-20251102/gcc/rust/util/rust-attributes.h
*** gcc-16-20251026/gcc/rust/util/rust-attributes.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-attributes.h	Sun Nov  2 22:32:23 2025
*************** class Attributes
*** 29,34 ****
--- 29,36 ----
  {
  public:
    static bool is_known (const std::string &attribute_path);
+   static tl::optional<std::string>
+   extract_string_literal (const AST::Attribute &attr);
  };
  
  enum CompilerPass
*************** private:
*** 104,116 ****
    void check_attribute (const AST::Attribute &attribute);
  
    /* Check the validity of all given attributes */
    void check_attributes (const AST::AttrVec &attributes);
  
    // rust-ast.h
    void visit (AST::Crate &crate) override;
    void visit (AST::Token &tok) override;
    void visit (AST::DelimTokenTree &delim_tok_tree) override;
-   void visit (AST::AttrInputMetaItemContainer &input) override;
    void visit (AST::IdentifierExpr &ident_expr) override;
    void visit (AST::Lifetime &lifetime) override;
    void visit (AST::LifetimeParam &lifetime_param) override;
--- 106,119 ----
    void check_attribute (const AST::Attribute &attribute);
  
    /* Check the validity of all given attributes */
+ 
+   void check_inner_attributes (const AST::AttrVec &attributes);
    void check_attributes (const AST::AttrVec &attributes);
  
    // rust-ast.h
    void visit (AST::Crate &crate) override;
    void visit (AST::Token &tok) override;
    void visit (AST::DelimTokenTree &delim_tok_tree) override;
    void visit (AST::IdentifierExpr &ident_expr) override;
    void visit (AST::Lifetime &lifetime) override;
    void visit (AST::LifetimeParam &lifetime_param) override;
*************** private:
*** 203,209 ****
    void visit (AST::Union &union_item) override;
    void visit (AST::ConstantItem &const_item) override;
    void visit (AST::StaticItem &static_item) override;
-   void visit (AST::TraitItemConst &item) override;
    void visit (AST::TraitItemType &item) override;
    void visit (AST::Trait &trait) override;
    void visit (AST::InherentImpl &impl) override;
--- 206,211 ----
*************** private:
*** 219,225 ****
    void visit (AST::MacroRulesDefinition &rules_def) override;
    void visit (AST::MacroInvocation &macro_invoc) override;
    void visit (AST::MetaItemPath &meta_item) override;
-   void visit (AST::MetaItemSeq &meta_item) override;
    void visit (AST::MetaWord &meta_item) override;
    void visit (AST::MetaNameValueStr &meta_item) override;
    void visit (AST::MetaListPaths &meta_item) override;
--- 221,226 ----
*************** private:
*** 242,253 ****
    void visit (AST::StructPatternFieldIdent &field) override;
    void visit (AST::StructPattern &pattern) override;
    // void visit(TupleStructItems& tuple_items) override;
!   void visit (AST::TupleStructItemsNoRange &tuple_items) override;
!   void visit (AST::TupleStructItemsRange &tuple_items) override;
    void visit (AST::TupleStructPattern &pattern) override;
    // void visit(TuplePatternItems& tuple_items) override;
!   void visit (AST::TuplePatternItemsMultiple &tuple_items) override;
!   void visit (AST::TuplePatternItemsRanged &tuple_items) override;
    void visit (AST::TuplePattern &pattern) override;
    void visit (AST::GroupedPattern &pattern) override;
    void visit (AST::SlicePattern &pattern) override;
--- 243,254 ----
    void visit (AST::StructPatternFieldIdent &field) override;
    void visit (AST::StructPattern &pattern) override;
    // void visit(TupleStructItems& tuple_items) override;
!   void visit (AST::TupleStructItemsNoRest &tuple_items) override;
!   void visit (AST::TupleStructItemsHasRest &tuple_items) override;
    void visit (AST::TupleStructPattern &pattern) override;
    // void visit(TuplePatternItems& tuple_items) override;
!   void visit (AST::TuplePatternItemsNoRest &tuple_items) override;
!   void visit (AST::TuplePatternItemsHasRest &tuple_items) override;
    void visit (AST::TuplePattern &pattern) override;
    void visit (AST::GroupedPattern &pattern) override;
    void visit (AST::SlicePattern &pattern) override;
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-canonical-path.h gcc-16-20251102/gcc/rust/util/rust-canonical-path.h
*** gcc-16-20251026/gcc/rust/util/rust-canonical-path.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-canonical-path.h	Sun Nov  2 22:32:23 2025
*************** public:
*** 114,119 ****
--- 114,121 ----
        return CanonicalPath (other.segs, crate_num);
  
      std::vector<std::pair<NodeId, std::string>> copy (segs);
+     copy.reserve (other.segs.size ());
+ 
      for (auto &s : other.segs)
        copy.push_back (s);
  
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-dump.h gcc-16-20251102/gcc/rust/util/rust-dump.h
*** gcc-16-20251026/gcc/rust/util/rust-dump.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-dump.h	Sun Nov  2 22:32:23 2025
***************
*** 16,21 ****
--- 16,23 ----
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
  
+ #include "rust-system.h"
+ 
  // Common definitions useful for textual dump of IRs (AST and HIR).
  
  #ifndef RUST_DUMP_H
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-ggc.cc gcc-16-20251102/gcc/rust/util/rust-ggc.cc
*** gcc-16-20251026/gcc/rust/util/rust-ggc.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-ggc.cc	Sun Nov  2 22:32:23 2025
***************
*** 17,22 ****
--- 17,23 ----
  // <http://www.gnu.org/licenses/>.
  
  #include "rust-ggc.h"
+ #include "rust-ast.h"
  #include "stringpool.h"
  
  namespace Rust {
*************** Ident::Ident (const std::string &str)
*** 29,34 ****
--- 30,37 ----
    : inner (get_identifier_with_length (str.c_str (), str.length ()))
  {}
  
+ Ident::Ident (const Rust::Identifier &ident) : Ident (ident.as_string ()) {}
+ 
  bool
  Ident::operator== (const std::string &other) const
  {
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-ggc.h gcc-16-20251102/gcc/rust/util/rust-ggc.h
*** gcc-16-20251026/gcc/rust/util/rust-ggc.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-ggc.h	Sun Nov  2 22:32:23 2025
***************
*** 24,29 ****
--- 24,32 ----
  
  namespace Rust {
  
+ // forward declare
+ class Identifier;
+ 
  namespace GGC {
  
  class Ident
*************** class Ident
*** 33,38 ****
--- 36,42 ----
  public:
    Ident (const char *str);
    Ident (const std::string &str);
+   Ident (const Rust::Identifier &ident);
  
    bool operator== (const Ident &other) const { return inner == other.inner; }
    bool operator== (const std::string &other) const;
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-inline-visitor.h gcc-16-20251102/gcc/rust/util/rust-inline-visitor.h
*** gcc-16-20251026/gcc/rust/util/rust-inline-visitor.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-inline-visitor.h	Sun Nov  2 22:32:23 2025
***************
*** 15,20 ****
--- 15,21 ----
  // You should have received a copy of the GNU General Public License
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
+ #include "rust-system.h"
  
  // An improved implementation of the inline visitor.
  // Original idea from https://members.accu.org/index.php/articles/2021
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-lang-item.h gcc-16-20251102/gcc/rust/util/rust-lang-item.h
*** gcc-16-20251026/gcc/rust/util/rust-lang-item.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-lang-item.h	Sun Nov  2 22:32:23 2025
***************
*** 21,26 ****
--- 21,29 ----
  #include "optional.h"
  #include "bi-map.h"
  
+ #ifndef RUST_LANG_ITEM_H
+ #define RUST_LANG_ITEM_H
+ 
  namespace Rust {
  
  class LangItem
*************** template <> struct hash<Rust::LangItem::
*** 185,187 ****
--- 188,192 ----
    }
  };
  } // namespace std
+ 
+ #endif // RUST_LANG_ITEM_H
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-token-converter.cc gcc-16-20251102/gcc/rust/util/rust-token-converter.cc
*** gcc-16-20251026/gcc/rust/util/rust-token-converter.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-token-converter.cc	Sun Nov  2 22:32:23 2025
*************** ProcMacro::TokenStream
*** 102,108 ****
  convert (const std::vector<const_TokenPtr> &tokens)
  {
    std::vector<ProcMacro::TokenStream> trees;
!   trees.push_back (ProcMacro::TokenStream::make_tokenstream ());
    for (auto &token : tokens)
      {
        auto loc = convert (token->get_locus ());
--- 102,110 ----
  convert (const std::vector<const_TokenPtr> &tokens)
  {
    std::vector<ProcMacro::TokenStream> trees;
!   trees.reserve (tokens.size ());
! 
!   trees.emplace_back (ProcMacro::TokenStream::make_tokenstream ());
    for (auto &token : tokens)
      {
        auto loc = convert (token->get_locus ());
diff -Nrcpad gcc-16-20251026/gcc/rust/util/rust-unwrap-segment.h gcc-16-20251102/gcc/rust/util/rust-unwrap-segment.h
*** gcc-16-20251026/gcc/rust/util/rust-unwrap-segment.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/rust/util/rust-unwrap-segment.h	Sun Nov  2 22:32:23 2025
***************
*** 16,21 ****
--- 16,25 ----
  // along with GCC; see the file COPYING3.  If not see
  // <http://www.gnu.org/licenses/>.
  
+ #include "rust-system.h"
+ #include "optional.h"
+ #include "rust-lang-item.h"
+ #include "rust-mapping-common.h"
  #include <ast/rust-ast-full-decls.h>
  
  namespace Rust {
*************** unwrap_segment_get_lang_item (const std:
*** 115,118 ****
--- 119,138 ----
    return unwrap_segment_get_lang_item (*ptr);
  }
  
+ /**
+  * Used to output a path in error messages
+  */
+ 
+ inline static std::string
+ unwrap_segment_error_string (const AST::TypePath &path)
+ {
+   return path.make_debug_string ();
+ }
+ 
+ inline static std::string
+ unwrap_segment_error_string (const AST::PathInExpression &path)
+ {
+   return path.as_simple_path ().as_string ();
+ }
+ 
  } // namespace Rust
diff -Nrcpad gcc-16-20251026/gcc/simplify-rtx.cc gcc-16-20251102/gcc/simplify-rtx.cc
*** gcc-16-20251026/gcc/simplify-rtx.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/simplify-rtx.cc	Sun Nov  2 22:32:24 2025
*************** simplify_context::simplify_binary_operat
*** 3673,3678 ****
--- 3673,3735 ----
  	  && GET_MODE_CLASS (mode) != MODE_CC)
  	return CONSTM1_RTX (mode);
  
+       /* IOR of two single bit bitfields extracted from the same object.
+ 	 Bitfields are represented as an AND based extraction */
+       if (GET_CODE (op0) == AND
+ 	  && GET_CODE (op1) == AND
+ 	  /* Verify both AND operands are logical right shifts. */
+ 	  && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
+ 	  && GET_CODE (XEXP (op1, 0)) == LSHIFTRT
+ 	  /* Verify both bitfields are extracted from the same object. */
+ 	  && XEXP (XEXP (op0, 0), 0) == XEXP (XEXP (op1, 0), 0)
+ 	  /* Verify both fields are a single bit (could be generalized). */
+ 	  && XEXP (op0, 1) == CONST1_RTX (mode)
+ 	  && XEXP (op1, 1) == CONST1_RTX (mode)
+ 	  /* Verify bit positions (for cases with variable bit position). */
+ 	  && CONST_INT_P (XEXP (op0, 1))
+ 	  && CONST_INT_P (XEXP (op1, 1)))
+ 	{
+ 	  unsigned HOST_WIDE_INT bitpos1 = INTVAL (XEXP (XEXP (op0, 0), 1));
+ 	  unsigned HOST_WIDE_INT bitpos2 = INTVAL (XEXP (XEXP (op1, 0), 1));
+ 	  unsigned HOST_WIDE_INT mask
+ 	    = (HOST_WIDE_INT_1U << bitpos1) | (HOST_WIDE_INT_1U << bitpos2);
+ 
+ 	  rtx m = GEN_INT (mask);
+ 	  rtx t = gen_rtx_AND (mode, XEXP (XEXP (op0, 0), 0), m);
+ 	  t = gen_rtx_NE (mode, t, CONST0_RTX (mode));
+ 	  return t;
+ 	}
+ 
+       /* IOR of multiple single bit bitfields extracted from the same object
+ 	 (building on previous case).
+ 	 First bitfield is represented as an AND based extraction, as done
+ 		above. Second represented as NE based extraction, from
+ 		output above. */
+       if (GET_CODE (op0) == AND
+ 	  && GET_CODE (op1) == NE
+ 	  /* Verify AND operand is logical right shift. */
+ 	  && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
+ 	  /* Verify NE operand is an AND (based on output above). */
+ 	  && GET_CODE (XEXP (op1, 0)) == AND
+ 	  /* Verify both bitfields are extracted from the same object. */
+ 	  && XEXP (XEXP (op0, 0), 0) == XEXP (XEXP (op1, 0), 0)
+ 	  /* Verify masking is with a single bit and that we have a NE 0
+ 	     comparison for the other operand.  */
+ 	  && XEXP (op0, 1) == CONST1_RTX (mode)
+ 	  && XEXP (op1, 1) == CONST0_RTX (mode)
+ 	  /* Verify bit position. */
+ 	  && CONST_INT_P (XEXP (op0, 1)))
+ 	{
+ 	  unsigned HOST_WIDE_INT bitpos1 = INTVAL (XEXP (XEXP (op0, 0), 1));
+ 	  unsigned HOST_WIDE_INT mask
+ 	    = (HOST_WIDE_INT_1U << bitpos1) | INTVAL (XEXP (XEXP (op1, 0), 1));
+ 
+ 	  rtx m = GEN_INT (mask);
+ 	  rtx t = gen_rtx_AND (mode, XEXP (XEXP (op0, 0), 0), m);
+ 	  t = gen_rtx_NE (mode, t, CONST0_RTX (mode));
+ 	  return t;
+ 	}
+ 
        /* Convert (ior (plus (A - 1)) (neg A)) to -1.  */
        if (match_plus_neg_pattern (op0, op1, mode))
  	return CONSTM1_RTX (mode);
diff -Nrcpad gcc-16-20251026/gcc/ssa-iterators.h gcc-16-20251102/gcc/ssa-iterators.h
*** gcc-16-20251026/gcc/ssa-iterators.h	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/ssa-iterators.h	Sun Nov  2 22:32:24 2025
*************** along with GCC; see the file COPYING3.
*** 36,60 ****
     base for a circular list, and initially this is the only node in
     the list.
  
!    Fast iteration allows each use to be examined, but does not allow
!    any modifications to the uses or stmts.
! 
!    Normal iteration allows insertion, deletion, and modification. the
!    iterator manages this by inserting a marker node into the list
!    immediately before the node currently being examined in the list.
!    this marker node is uniquely identified by having null stmt *and* a
!    null use pointer.
  
!    When iterating to the next use, the iteration routines check to see
!    if the node after the marker has changed. if it has, then the node
!    following the marker is now the next one to be visited. if not, the
!    marker node is moved past that node in the list (visualize it as
!    bumping the marker node through the list).  this continues until
!    the marker node is moved to the original anchor position. the
!    marker node is then removed from the list.
  
-    If iteration is halted early, the marker node must be removed from
-    the list before continuing.  */
  struct imm_use_iterator
  {
    /* This is the current use the iterator is processing.  */
--- 36,52 ----
     base for a circular list, and initially this is the only node in
     the list.
  
!    Fast iteration via FOR_EACH_IMM_USE_FAST allows each use to be
!    examined, but does not allow any modifications to the uses or stmts.
  
!    Safe iteration via FOR_EACH_IMM_USE_STMT and FOR_EACH_IMM_USE_ON_STMT
!    allows insertion, deletion, and modification of SSA operands within
!    the current stmt iterated.  The iterator manages this by re-sorting
!    the immediate uses to batch uses on a single stmt after each other
!    and inserts a marker node into the list immediately after the node
!    ending the current batch.  This marker node is uniquely identified by
!    having null stmt *and* a null use pointer.  */
  
  struct imm_use_iterator
  {
    /* This is the current use the iterator is processing.  */
diff -Nrcpad gcc-16-20251026/gcc/symtab.cc gcc-16-20251102/gcc/symtab.cc
*** gcc-16-20251026/gcc/symtab.cc	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/symtab.cc	Sun Nov  2 22:32:24 2025
*************** symtab_node::dump_referring (FILE *file)
*** 873,879 ****
    fprintf (file, "\n");
  }
  
! static const char * const symtab_type_names[] = {"symbol", "function", "variable"};
  
  /* Dump the visibility of the symbol.  */
  
--- 873,888 ----
    fprintf (file, "\n");
  }
  
! static const char * const toplevel_type_names[] =
! {
!  "base",
!  "asm",
!  "symbol",
!  "function",
!  "variable",
! };
! 
! static_assert (ARRAY_SIZE(toplevel_type_names)==TOPLEVEL_MAX);
  
  /* Dump the visibility of the symbol.  */
  
*************** symtab_node::get_visibility_string () co
*** 889,895 ****
  const char *
  symtab_node::get_symtab_type_string () const
  {
!   return symtab_type_names[type];
  }
  
  /* Dump base fields of symtab nodes to F.  Not to be used directly.  */
--- 898,904 ----
  const char *
  symtab_node::get_symtab_type_string () const
  {
!   return toplevel_type_names[type];
  }
  
  /* Dump base fields of symtab nodes to F.  Not to be used directly.  */
*************** symtab_node::dump_base (FILE *f)
*** 904,910 ****
    fprintf (f, "%s (%s)", dump_asm_name (), name ());
    if (dump_flags & TDF_ADDRESS)
      dump_addr (f, " @", (void *)this);
!   fprintf (f, "\n  Type: %s", symtab_type_names[type]);
  
    if (definition)
      fprintf (f, " definition");
--- 913,919 ----
    fprintf (f, "%s (%s)", dump_asm_name (), name ());
    if (dump_flags & TDF_ADDRESS)
      dump_addr (f, " @", (void *)this);
!   fprintf (f, "\n  Type: %s", toplevel_type_names[type]);
  
    if (definition)
      fprintf (f, " definition");
diff -Nrcpad gcc-16-20251026/gcc/testsuite/ChangeLog gcc-16-20251102/gcc/testsuite/ChangeLog
*** gcc-16-20251026/gcc/testsuite/ChangeLog	Sun Oct 26 22:32:33 2025
--- gcc-16-20251102/gcc/testsuite/ChangeLog	Sun Nov  2 22:32:24 2025
***************
*** 1,3 ****
--- 1,1380 ----
+ 2025-11-01  Shreya Munnangi  <smunnangi1@ventanamicro.com>
+ 
+ 	PR target/67731
+ 	* gcc.target/riscv/pr67731.c: New test.
+ 	* gcc.target/sh/pr67731.c: New test.
+ 
+ 2025-11-01  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR rtl-optimization/122321
+ 	* gcc.target/riscv/rvv/autovec/pr122321.c: New test.
+ 
+ 2025-11-01  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/78640
+ 	* gfortran.dg/pure_result.f90: New test.
+ 
+ 2025-11-01  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122381
+ 	* g++.dg/modules/convop-2_a.H: New test.
+ 	* g++.dg/modules/convop-2_b.C: New test.
+ 
+ 2025-11-01  Martin Uecker  <uecker@tugraz.at>
+ 
+ 	* gcc.dg/gnu-compoundlit-1.c: New test.
+ 	* gcc.dg/gnu-compoundlit-2.c: New test.
+ 	* gcc.dg/pr68090.c: Adapt.
+ 	* gcc.dg/vla-init-4.c: Adapt.
+ 	* gcc.dg/vla-init-5.c: Adapt.
+ 
+ 2025-11-01  Martin Uecker  <uecker@tugraz.at>
+ 
+ 	PR c/97986
+ 	* gcc.dg/pr97986-1.c: New test.
+ 	* gcc.dg/pr97986-2.c: New test.
+ 
+ 2025-11-01  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	* gcc.dg/fold-vecperm-1.c: Test at forwprop3.
+ 
+ 2025-10-31  Tamar Christina  <tamar.christina@arm.com>
+ 
+ 	PR target/121853
+ 	* gcc.target/aarch64/pr121853_1.c: New test.
+ 	* gcc.target/aarch64/pr121853_2.c: New test.
+ 
+ 2025-10-31  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122452
+ 	* gfortran.dg/pdt_65.f03: New test.
+ 
+ 2025-10-31  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/122502
+ 	* gcc.dg/torture/pr122502.c: New testcase.
+ 
+ 2025-10-31  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	* gcc.dg/tree-ssa/pr122478.c: Swap `1` and `"optimized"`.
+ 
+ 2025-10-31  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122497
+ 	* gcc.dg/torture/pr122497-1.c: New test.
+ 
+ 2025-10-31  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	* gcc.dg/vect/slp-widen-mult-half.c: Remove '-mlasx'.
+ 	* gcc.dg/vect/tree-vect.h: Check whether the runtime
+ 	environment supports LSX instructions.
+ 	* gcc.dg/vect/vect-widen-mult-const-s16.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-const-u16.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-half-u8.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-half.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-u16.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-u8-s16-s32.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-u8-u32.c: Dito.
+ 	* gcc.dg/vect/vect-widen-mult-u8.c: Dito.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/tuplepattern-restpattern-typecheck-err.rs: New file.
+ 
+ 2025-10-30  Ryo Yoshida  <low.ryoshida@gmail.com>
+ 
+ 	* rust/compile/match-tuplestructpattern-non-variant.rs: New test.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/issue-4231.rs: New file.
+ 
+ 2025-10-30  Lucas Ly Ba  <lucas.ly-ba@outlook.fr>
+ 
+ 	* rust/compile/issue-4212.rs: New test.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* rust/compile/issue-3556.rs: New test.
+ 
+ 2025-10-30  Ryo Yoshida  <low.ryoshida@gmail.com>
+ 
+ 	* rust/compile/tuple_index_on_non_tuple.rs: New test.
+ 
+ 2025-10-30  0xllx0  <github+elle@weathered-steel.dev>
+ 
+ 	* rust/compile/issue-4145.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/attr_malformed_doc.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/attr_malformed_path.rs: New test.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/match-tuplestructpattern-err.rs: New file.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/match-tuplestructpattern-rest.rs: New file.
+ 	* rust/execute/torture/match-tuplestructpattern-rest-1.rs: New file.
+ 	* rust/execute/torture/match-tuplestructpattern-rest-2.rs: New file.
+ 
+ 2025-10-30  0xllx0  <github+elle@weathered-steel.dev>
+ 
+ 	* rust/compile/issue-4148.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/core/core.exp: New test.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/issue-3929-1.rs: New file.
+ 	* rust/compile/issue-3929-2.rs: New file.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/execute/torture/link-name.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/macros/mbe/macro58.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-3538.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-3592.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-4165.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-4090-1.rs: New test.
+ 	* rust/compile/issue-4090-2.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-4168.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-2394.rs: Update test case
+ 	* rust/compile/issue-4146.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-4139.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/issue-4155.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/issue-3922.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/issue-3924.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-3969.rs: New test.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-3965-1.rs: New test.
+ 	* rust/compile/issue-3965-2.rs: New test.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/tuplepattern-rest-readonly.rs: New file.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/issue-3930.rs: New file.
+ 
+ 2025-10-30  Philip Herron  <herron.philip@googlemail.com>
+ 
+ 	* rust/compile/issue-1725-2.rs: remove bad error message
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/use_self_alone_in_list.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/use_self_alone.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/primitive-import.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/parse_float_dot.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/format_args_concat.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/global-path-array.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/impl_fnptr.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/parse_closure_bind.rs: New test.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* rust/compile/issue-3645.rs: New test.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/compile/slice_rest_pattern.rs: Removed -fsyntax-only.
+ 	* rust/execute/torture/match-slicepattern-array-2.rs: New file.
+ 	* rust/execute/torture/match-slicepattern-slice-2.rs: New file.
+ 
+ 2025-10-30  Yap Zhi Heng  <yapzhhg@gmail.com>
+ 
+ 	* rust/execute/torture/let-identifierpattern-subpattern.rs: New file.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* rust/compile/issue-3958.rs: New test.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* rust/compile/issue-3947.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/issue-3966.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/use_3.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/issue-3974.rs: New test.
+ 
+ 2025-10-30  Arthur Cohen  <arthur.cohen@embecosm.com>
+ 
+ 	* rust/compile/issue-3726.rs: New test.
+ 	* rust/compile/issue-3898.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/macros/mbe/macro-issue4054.rs: New test.
+ 
+ 2025-10-30  Ryutaro Okada  <1015ryu88@gmail.com>
+ 
+ 	* rust/compile/enum_discriminant3.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/cfg-test.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/compile/import_wildcards.rs: New test.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/macros/mbe/macro49.rs: Add missing lang items.
+ 
+ 2025-10-30  lishin  <lishin1008@gmail.com>
+ 
+ 	* rust/compile/issue-3928.rs: New test.
+ 
+ 2025-10-30  Pierre-Emmanuel Patry  <pierre-emmanuel.patry@embecosm.com>
+ 
+ 	* rust/execute/inline_asm_inout_ident.rs: Add arch filter on test.
+ 	* rust/execute/inline_asm_inout_var.rs: Likewise.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rust/compile/attr-macro.rs: New test.
+ 
+ 2025-10-30  David Faust  <david.faust@oracle.com>
+ 
+ 	PR debug/122248
+ 	* gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c: New.
+ 	* gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c: New.
+ 	* gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c: New.
+ 
+ 2025-10-30  David Faust  <david.faust@oracle.com>
+ 
+ 	* gcc.dg/debug/btf/btf-prune-4.c: New.
+ 
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gcc.dg/cpp/escape-3.i: Remove parentheses in dg-scan directive.
+ 
+ 2025-10-30  Qing Zhao  <qing.zhao@oracle.com>
+ 
+ 	* gcc.dg/pointer-counted-by.c: Update for void pointers.
+ 	* gcc.dg/pointer-counted-by-10.c: New test.
+ 	* gcc.dg/pointer-counted-by-4-void.c: New test.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR target/116075
+ 	* gcc.target/aarch64/sve/dup-insr-1.c: New test.
+ 	* gcc.target/aarch64/sve/dup-insr-2.c: New test.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122247
+ 	* g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C: New test.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/122247
+ 	* g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C: New test.
+ 
+ 2025-10-30  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	* gcc.dg/tree-ssa/ctz-char.c: Remove -fno-tree-ch.
+ 	* gcc.dg/tree-ssa/ctz-complement-char.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-complement-int.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-complement-long-long.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-complement-long.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-int.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-long-long.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-long.c: Ditto.
+ 	* gcc.dg/tree-ssa/ctz-ch.c: New test.
+ 	* gcc.dg/pr41488.c: Add -fno-tree-scev-cprop.
+ 
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/generic_inst7.ads: New test.
+ 	* gnat.dg/specs/generic_inst8.ads: New test.
+ 
+ 2025-10-30  Robin Dapp  <rdapp.gcc@gmail.com>
+ 
+ 	PR target/122445
+ 	* gcc.target/riscv/rvv/autovec/pr122445.c: New test.
+ 
+ 2025-10-30  Artemiy Volkov  <artemiy.volkov@arm.com>
+ 
+ 	PR tree-optimization/122478
+ 	* gcc.dg/tree-ssa/pr122478.c: New test.
+ 
+ 2025-10-30  Richard Biener  <rguenther@suse.de>
+ 
+ 	* gcc.dg/tree-ssa/pr92834.c: Scan phiopt1 instead of optimized.
+ 
+ 2025-10-30  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR rtl-optimization/121198
+ 	* gcc.target/avr/pr121198.c: New test.
+ 
+ 2025-10-30  Gaius Mulley  <gaiusmod2@gmail.com>
+ 
+ 	PR modula2/122485
+ 	* gm2.dg/spell/iso/fail/badimport.mod: New test.
+ 
+ 2025-10-30  Richard Biener  <rguenther@suse.de>
+ 	    Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gcc.dg/vect/slp-reduc-13.c: New testcase.
+ 
+ 2025-10-30  Uros Bizjak  <ubizjak@gmail.com>
+ 
+ 	PR target/116815
+ 	* gcc.dg/pr116815.c: New test.
+ 	* gcc.target/i386/pr116815.c: New test.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	* c-c++-common/ubsan/align-5.c: Xfail.
+ 	* gcc.dg/pr107389.c: Move to...
+ 	* gcc.dg/torture/pr107389.c: ...here. Skip for lto.
+ 	* gcc.dg/builtin-assume-aligned-1.c: Instead of
+ 	testing for deleting of assume-align, test for
+ 	the alignment/misalignment. Also disable the
+ 	vectorizer.
+ 
+ 2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Revert:
+ 	2025-10-30  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR middle-end/107389
+ 	PR tree-optimization/122086
+ 	* gcc.dg/pr107389.c: Move to...
+ 	* gcc.dg/torture/pr107389.c: ...here. Skip for lto.
+ 	Use dg-additional-options rather than dg-options.
+ 	* c-c++-common/ubsan/align-5.c: xfail.
+ 
+ 2025-10-30  liuhongt  <hongtao.liu@intel.com>
+ 
+ 	* gcc.target/i386/pr122457.c: New test.
+ 
+ 2025-10-30  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* gcc.target/loongarch/fnmam4-vec.c: New test.
+ 
+ 2025-10-30  Jinyang He  <hejinyang@loongson.cn>
+ 	    Peng Fan  <fanpeng@loongson.cn>
+ 
+ 	* gcc.target/loongarch/conditional-move-opt-1.c: Remove mul.
+ 	* gcc.target/loongarch/conditional-move-opt-2.c: Remove and.
+ 	* gcc.target/loongarch/conditional-move-opt-3.c: New test.
+ 
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/aggr32.adb: New test.
+ 	* gnat.dg/aggr32_pkg.ads: New helper.
+ 	* gnat.dg/aggr32_pkg-child.ads: Likewise.
+ 
+ 2025-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/generic_inst6.ads: New test.
+ 	* gnat.dg/specs/generic_inst6_pkg1-child.ads: New helper.
+ 	* gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads: Likewise.
+ 	* gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads: Likewise.
+ 	* gnat.dg/specs/generic_inst6_pkg1.ads: Likewise.
+ 	* gnat.dg/specs/generic_inst6_pkg2.ads: Likewise.
+ 	* gnat.dg/specs/generic_inst6_pkg3.ads: Likewise.
+ 
+ 2025-10-29  Andrew MacLeod  <amacleod@redhat.com>
+ 
+ 	PR tree-optimization/91191
+ 	* gcc.dg/pr91191.c: New.
+ 
+ 2025-10-29  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122165
+ 	* gfortran.dg/pdt_64.f03: New test.
+ 
+ 2025-10-29  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/70102
+ 	* gfortran.dg/vect/pr70102.f: New testcase.
+ 
+ 2025-10-29  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122433
+ 	PR fortran/122434
+ 	* gfortran.dg/pdt_62.f03: New test.
+ 	* gfortran.dg/pdt_63.f03: New test.
+ 
+ 2025-10-29  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	PR target/122097
+ 	* gcc.target/loongarch/pr122097.c: New test.
+ 
+ 2025-10-29  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	* gcc.target/loongarch/trap-default.c: New test.
+ 	* gcc.target/loongarch/trap-1.c: New test.
+ 
+ 2025-10-28  Yuao Ma  <c8ef@outlook.com>
+ 
+ 	PR fortran/122342
+ 	* gfortran.dg/coarray_atomic_5.f90: Update testcase.
+ 	* gfortran.dg/team_form_3.f90: Likewise.
+ 
+ 2025-10-28  Artemiy Volkov  <artemiy.volkov@arm.com>
+ 
+ 	* gcc.dg/tree-ssa/forwprop-42.c: New test.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/generic_inst5.ads: New test.
+ 	* gnat.dg/specs/generic_inst5_pkg1.ads: New helper.
+ 	* gnat.dg/specs/generic_inst5_pkg2.ads: Likewise.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/generic_inst4-child2.ads: New test.
+ 	* gnat.dg/specs/generic_inst4.ads: New helper.
+ 	* gnat.dg/specs/generic_inst4-child1.ads: Likewise.
+ 
+ 2025-10-28  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/generic_inst3.ads: Add dg-do directive.
+ 
+ 2025-10-27  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122422
+ 	* g++.dg/modules/merge-20.h: New test.
+ 	* g++.dg/modules/merge-20_a.H: New test.
+ 	* g++.dg/modules/merge-20_b.C: New test.
+ 
+ 2025-10-27  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122310
+ 	* g++.dg/modules/lambda-12.h: New test.
+ 	* g++.dg/modules/lambda-12_a.H: New test.
+ 	* g++.dg/modules/lambda-12_b.C: New test.
+ 
+ 2025-10-27  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/105749
+ 	PR tree-optimization/80635
+ 	* g++.dg/warn/pr80635-3.C: New test.
+ 	* g++.dg/warn/pr80635-4.C: New test.
+ 
+ 2025-10-27  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR c/122427
+ 	* g++.target/i386/cf_check-1.C: New test.
+ 	* g++.target/i386/cf_check-2.C: Likewise.
+ 	* g++.target/i386/cf_check-3.C: Likewise.
+ 	* g++.target/i386/cf_check-4.C: Likewise.
+ 	* gcc.target/i386/cf_check-7.c: Likewise.
+ 	* gcc.target/i386/cf_check-8.c: Likewise.
+ 	* gcc.target/i386/cf_check-9.c: Likewise.
+ 	* gcc.target/i386/cf_check-10.c: Likewise.
+ 	* gcc.target/i386/cf_check-11.c: Likewise.
+ 	* gcc.target/i386/no-callee-saved-12.c: Remove dg-error.
+ 	* gcc.target/i386/preserve-none-17.c: Likewise.
+ 
+ 2025-10-27  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/private3-child.ads: New test.
+ 	* gnat.dg/specs/private3.ads: New helper.
+ 
+ 2025-10-27  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/specs/generic_inst3.ads: New test.
+ 	* gnat.dg/specs/generic_inst3_pkg1.ads: New helper.
+ 	* gnat.dg/specs/generic_inst3_pkg1.adb: New helper.
+ 	* gnat.dg/specs/generic_inst3_pkg2.ads: Likewise.
+ 	* gnat.dg/specs/generic_inst3_pkg3.ads: Likewise.
+ 	* gnat.dg/specs/generic_inst3_pkg3-child.ads: Likewise.
+ 
+ 2025-10-27  Tamar Christina  <tamar.christina@arm.com>
+ 
+ 	PR tree-optimization/122408
+ 	* gfortran.target/aarch64/pr122408_1.f90: New test.
+ 	* gfortran.target/aarch64/pr122408_2.f90: New test.
+ 
+ 2025-10-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/122394
+ 	* g++.dg/opt/pr122394.C: New test.
+ 
+ 2025-10-27  Olivier Hainque  <hainque@adacore.com>
+ 
+ 	* g++.target/riscv/rvv/xtheadvector/pr116593.C: Skip if !hostedlib.
+ 
+ 2025-10-27  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/95541
+ 	* gfortran.dg/pdt_61.f03: New test.
+ 
+ 2025-10-27  Andrew MacLeod  <amacleod@redhat.com>
+ 
+ 	PR tree-optimization/111003
+ 	* gcc.dg/tree-ssa/pr111003.c: XFAIL.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/122325
+ 	* gcc.dg/complex-8.c: New testcase.
+ 	* gcc.dg/complex-9.c: Likewise.
+ 
+ 2025-10-27  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c:
+ 	New test.
+ 
+ 2025-10-27  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_single_register.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c:
+ 	New test.
+ 	* gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c: New test.
+ 	* gcc.target/riscv/rvv/vls-cc/vls-cc-common.h: New test.
+ 
+ 2025-10-27  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR target/64345
+ 	PR tree-optimization/80770
+ 	* gcc.target/riscv/pr120553-2.c: Update expected output.
+ 	* gcc.target/riscv/pr64345.c: New test.
+ 	* gcc.target/riscv/zbb-andn-orn-01.c: Skip when peephole2 isn't run.
+ 	* gcc.target/riscv/zbb-andn-orn-02.c: Likewise.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/122419
+ 	* gcc.dg/vect/pr122419.c: New testcase.
+ 
+ 2025-10-27  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/122435
+ 	* gcc.dg/tree-ssa/ssa-fre-111.c: New testcase.
+ 
+ 2025-10-27  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/122323
+ 	* gcc.target/i386/builtin-copysign-8b.c: Add -mtune=generic.
+ 
+ 2025-10-27  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* gcc.target/loongarch/widen-mul-rtx-cost-signed.c: New test.
+ 	* gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c: New test.
+ 
+ 2025-10-27  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* gcc.target/loongarch/compare-both-non-zero.c: New test.
+ 
+ 2025-10-27  Guo Jie  <guojie@loongson.cn>
+ 
+ 	* gcc.target/loongarch/sign_extend_ashift.c: New test.
+ 
+ 2025-10-27  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+ 
+ 	* gcc.target/xtensa/one_cmpl_abs.c: Remove.
+ 
+ 2025-10-27  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR middle-end/107389
+ 	PR tree-optimization/122086
+ 	* gcc.dg/pr107389.c: Move to...
+ 	* gcc.dg/torture/pr107389.c: ...here. Skip for lto.
+ 	Use dg-additional-options rather than dg-options.
+ 	* c-c++-common/ubsan/align-5.c: xfail.
+ 
+ 2025-10-26  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR target/122270
+ 	* gcc.target/riscv/rvv/base/pr122270-1.c: New test.
+ 
+ 2025-10-26  Kuan-Lin Chen  <rufus@andestech.com>
+ 
+ 	* gcc.target/riscv/rvv/autovec/pr111391-2.c: Add expected asm.
+ 
+ 2025-10-26  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/machine_attr3.ads, gnat.dg/machine_attr3.adb: New test.
+ 
+ 2025-10-26  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/122290
+ 	* gfortran.dg/pdt_60.f03: New test.
+ 
+ 2025-10-26  Alexandre Oliva  <oliva@adacore.com>
+ 
+ 	PR target/121599
+ 	* gcc.target/aarch64/sve2/pr121599.c: Tolerate alterate insn
+ 	selection.
+ 
  2025-10-25  Harald Anlauf  <anlauf@gmx.de>
  
  	PR fortran/114023
diff -Nrcpad gcc-16-20251026/gcc/testsuite/c-c++-common/ubsan/align-5.c gcc-16-20251102/gcc/testsuite/c-c++-common/ubsan/align-5.c
*** gcc-16-20251026/gcc/testsuite/c-c++-common/ubsan/align-5.c	Sun Oct 26 22:32:35 2025
--- gcc-16-20251102/gcc/testsuite/c-c++-common/ubsan/align-5.c	Sun Nov  2 22:32:30 2025
*************** foo (char *p)
*** 11,14 ****
    return *q;
  }
  
! /* { dg-final { scan-assembler "__ubsan_handle" } } */
--- 11,16 ----
    return *q;
  }
  
! /* xfail, see PR 122038 as __builtin_assume_aligned should be instrumented instead
!    of only the load. */
! /* { dg-final { scan-assembler "__ubsan_handle" { xfail *-*-* } } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/convop-2_a.H gcc-16-20251102/gcc/testsuite/g++.dg/modules/convop-2_a.H
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/convop-2_a.H	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/convop-2_a.H	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,10 ----
+ // PR c++/122381
+ // { dg-additional-options "-fmodule-header" }
+ // { dg-module-cmi {} }
+ 
+ template <typename T> struct color_ref {
+   operator int() const { return 0; }
+   int foo(color_ref x) {
+     return x.operator int();
+   }
+ };
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/convop-2_b.C gcc-16-20251102/gcc/testsuite/g++.dg/modules/convop-2_b.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/convop-2_b.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/convop-2_b.C	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,5 ----
+ // PR c++/122381
+ // { dg-additional-options "-fmodules" }
+ 
+ import "convop-2_a.H";
+ template struct color_ref<int>;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/inst-6_a.C gcc-16-20251102/gcc/testsuite/g++.dg/modules/inst-6_a.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/inst-6_a.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/inst-6_a.C	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,14 ----
+ // PR c++/122421
+ // { dg-additional-options "-fmodules" }
+ // { dg-module-cmi M }
+ 
+ export module M;
+ 
+ export template <typename T> struct Type {
+   static const int arr[3];
+ };
+ 
+ extern template const int Type<double>::arr[3];
+ template <typename T> const int Type<T>::arr[] = { 42, 43, 44 };
+ 
+ export Type<int> ti;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/inst-6_b.C gcc-16-20251102/gcc/testsuite/g++.dg/modules/inst-6_b.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/inst-6_b.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/inst-6_b.C	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,12 ----
+ // PR c++/122421
+ // { dg-additional-options "-fmodules" }
+ 
+ import M;
+ 
+ int main() {
+   const int& a = Type<int>::arr[0];
+   const int& b = Type<double>::arr[0];
+ }
+ 
+ // { dg-final { scan-assembler {_ZNW1M4TypeIiE3arrE:} } }
+ // { dg-final { scan-assembler-not {_ZNW1M4TypeIdE3arrE:} } }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/lambda-12.h gcc-16-20251102/gcc/testsuite/g++.dg/modules/lambda-12.h
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/lambda-12.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/lambda-12.h	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,27 ----
+ // PR c++/122310
+ struct Foo {
+   constexpr static inline auto do_nothing = [](auto && ...){};
+   using TNothing = decltype(do_nothing);
+ };
+ 
+ template <typename T>
+ struct X {
+   struct Inner {
+     union MoreInner {
+       static constexpr auto x = []{};
+ #if __cplusplus >= 202002L
+       static decltype([]{}) y;
+ #endif
+     };
+   };
+ 
+   using A = decltype(Inner::MoreInner::x);
+ #if __cplusplus >= 202002L
+   using B = decltype(Inner::MoreInner::y);
+ #endif
+ };
+ 
+ inline X<int>::A* a{};
+ #if __cplusplus >= 202002L
+ inline X<int>::B* b{};
+ #endif
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/lambda-12_a.H gcc-16-20251102/gcc/testsuite/g++.dg/modules/lambda-12_a.H
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/lambda-12_a.H	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/lambda-12_a.H	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,5 ----
+ // PR c++/122310
+ // { dg-additional-options "-fmodule-header" }
+ // { dg-module-cmi {} }
+ 
+ #include "lambda-12.h"
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/lambda-12_b.C gcc-16-20251102/gcc/testsuite/g++.dg/modules/lambda-12_b.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/lambda-12_b.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/lambda-12_b.C	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,5 ----
+ // PR c++/122310
+ // { dg-additional-options "-fmodules -fno-module-lazy" }
+ 
+ #include "lambda-12.h"
+ import "lambda-12_a.H";
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/merge-20.h gcc-16-20251102/gcc/testsuite/g++.dg/modules/merge-20.h
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/merge-20.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/merge-20.h	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,5 ----
+ // PR c++/122422
+ template <typename> struct Type {
+   constexpr static int arr[] = { 42, 43, 44 };
+ };
+ inline Type<int> tt;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/merge-20_a.H gcc-16-20251102/gcc/testsuite/g++.dg/modules/merge-20_a.H
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/merge-20_a.H	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/merge-20_a.H	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,5 ----
+ // PR c++/122422
+ // { dg-additional-options "-fmodule-header" }
+ // { dg-module-cmi {} }
+ 
+ #include "merge-20.h"
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/modules/merge-20_b.C gcc-16-20251102/gcc/testsuite/g++.dg/modules/merge-20_b.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/modules/merge-20_b.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/modules/merge-20_b.C	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,5 ----
+ // PR c++/122422
+ // { dg-additional-options "-fmodules -fno-module-lazy" }
+ 
+ #include "merge-20.h"
+ import "merge-20_a.H";
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/opt/pr122394.C gcc-16-20251102/gcc/testsuite/g++.dg/opt/pr122394.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/opt/pr122394.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/opt/pr122394.C	Sun Nov  2 22:32:51 2025
***************
*** 0 ****
--- 1,20 ----
+ // PR tree-optimization/122394
+ // { dg-do compile { target c++23 } }
+ // { dg-options "-O1 -g" }
+ 
+ #include <compare>
+ 
+ struct A {
+   friend auto operator<=> (A, A) = default;
+   double a;
+ };
+ void foo ();
+ A b, c;
+ 
+ void
+ bar ()
+ {
+   bool d = c >= b;
+   if (d)
+     foo ();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C gcc-16-20251102/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-1.C	Sun Nov  2 22:32:54 2025
***************
*** 0 ****
--- 1,33 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O1 -fdump-tree-forwprop1-details  -fdump-tree-esra-details -fexceptions" } */
+ 
+ /* PR tree-optimization/122247 */
+ 
+ struct s1
+ {
+   int t[1024];
+ };
+ 
+ struct s1 f(void);
+ 
+ void g(int a, int b, int );
+ void p(struct s1);
+ void h(struct s1 outer)
+ {
+   {
+     struct s1 inner = outer;
+     p(inner);
+   }
+   g(outer.t[0], outer.t[1], outer.t[2]);
+ }
+ /* Forwprop should be able to copy prop the copy of `inner = outer` to the call of p.
+    Also remove this copy. */
+ 
+ /* { dg-final { scan-tree-dump-times "after previous" 1 "forwprop1" } } */
+ /* { dg-final { scan-tree-dump-times "Removing dead store stmt inner = outer" 1 "forwprop1" } } */
+ 
+ /* The extra copy that was done by inlining is removed so SRA should not decide to cause
+    inner nor outer to be scalarized even for the 3 elements accessed afterwards.  */
+ /* { dg-final { scan-tree-dump-times "Disqualifying inner" 1 "esra" } } */
+ /* { dg-final { scan-tree-dump-times "Disqualifying outer" 1 "esra" } } */
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C gcc-16-20251102/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/tree-ssa/copy-prop-aggregate-sra-2.C	Sun Nov  2 22:32:54 2025
***************
*** 0 ****
--- 1,31 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fdump-tree-forwprop1-details  -fdump-tree-esra-details -fexceptions" } */
+ 
+ /* PR tree-optimization/122247 */
+ 
+ struct s1
+ {
+   int t[1024];
+ };
+ 
+ struct s1 f(void);
+ 
+ void g(int a, int b, int );
+ void p(struct s1);
+ void h(struct s1 outer)
+ {
+   struct s1 inner = outer;
+   p(inner);
+   g(outer.t[0], outer.t[1], outer.t[2]);
+ }
+ /* Forwprop should be able to copy prop the copy of `inner = outer` to the call of p.
+    Also remove this copy. */
+ 
+ /* { dg-final { scan-tree-dump-times "after previous" 1 "forwprop1" } } */
+ /* { dg-final { scan-tree-dump-times "Removing dead store stmt inner = outer" 1 "forwprop1" } } */
+ 
+ /* The extra copy that was done by inlining is removed so SRA should not decide to cause
+    inner nor outer to be scalarized even for the 3 elements accessed afterwards.  */
+ /* { dg-final { scan-tree-dump-times "Disqualifying inner" 1 "esra" } } */
+ /* { dg-final { scan-tree-dump-times "Disqualifying outer" 1 "esra" } } */
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/warn/pr80635-3.C gcc-16-20251102/gcc/testsuite/g++.dg/warn/pr80635-3.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/warn/pr80635-3.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/warn/pr80635-3.C	Sun Nov  2 22:32:56 2025
***************
*** 0 ****
--- 1,46 ----
+ // PR tree-optimization/80635
+ // { dg-do compile { target c++11 } }
+ // { dg-options "-O1 -Wmaybe-uninitialized" }
+ 
+ using size_t = decltype (sizeof (1));
+ inline void *operator new (size_t, void *p) { return p; }
+ template<typename T>
+ struct optional
+ {
+   optional () : m_dummy (), live (false) {}
+   void emplace () { new (&m_item) T (); live = true; }
+   ~optional () { if (live) m_item.~T (); }
+ 
+   union
+   {
+     struct {} m_dummy;
+     T m_item;
+   };
+   bool live;
+ };
+ 
+ extern int get ();
+ extern void set (int);
+ 
+ struct A
+ {
+   A () : m (get ()) {}
+   ~A () { set (m); }	// { dg-bogus "may be used uninitialized in this function" }
+ 
+   int m;
+ };
+ 
+ struct B
+ {
+   B ();
+   ~B ();
+ };
+ 
+ void func ()
+ {
+   optional<A> maybe_a;
+   optional<B> maybe_b;
+ 
+   maybe_a.emplace ();
+   maybe_b.emplace ();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.dg/warn/pr80635-4.C gcc-16-20251102/gcc/testsuite/g++.dg/warn/pr80635-4.C
*** gcc-16-20251026/gcc/testsuite/g++.dg/warn/pr80635-4.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.dg/warn/pr80635-4.C	Sun Nov  2 22:32:56 2025
***************
*** 0 ****
--- 1,31 ----
+ // PR tree-optimization/80635
+ // { dg-do compile { target c++17 } }
+ // { dg-options "-O1 -Wmaybe-uninitialized" }
+ 
+ #include <optional>
+ 
+ extern int get ();
+ extern void set (int);
+ 
+ struct A
+ {
+   A () : m (get ()) {}
+   ~A () { set (m); }	// { dg-bogus "may be used uninitialized in this function" }
+ 
+   int m;
+ };
+ 
+ struct B
+ {
+   B ();
+   ~B ();
+ };
+ 
+ void func ()
+ {
+   std::optional<A> maybe_a;
+   std::optional<B> maybe_b;
+ 
+   maybe_a.emplace ();
+   maybe_b.emplace ();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-1.C gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-1.C
*** gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-1.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-1.C	Sun Nov  2 22:32:57 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ 
+ extern void foo (void) __attribute__((nocf_check));
+ extern void foo (void);
+ 
+ void
+ foo (void)
+ {
+ }
+ 
+ extern void bar (void);
+ extern void bar (void) __attribute__((nocf_check)); /* { dg-error "ambiguating new declaration" } */
+ 
+ void
+ bar (void)
+ {
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-2.C gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-2.C
*** gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-2.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-2.C	Sun Nov  2 22:32:57 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ 
+ extern void bar (void);
+ extern void bar (void) __attribute__((nocf_check)); /* { dg-error "ambiguating new declaration" } */
+ extern void foo (void) __attribute__((nocf_check));
+ extern void foo (void);
+ 
+ void
+ func (void)
+ {
+   bar ();
+   foo ();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-3.C gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-3.C
*** gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-3.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-3.C	Sun Nov  2 22:32:57 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc').  */
+ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */
+ 
+ /*
+ **_Z3foov:
+ **.LFB[0-9]+:
+ **	.cfi_startproc
+ **	ret
+ **...
+ */
+ 
+ extern void foo (void) __attribute__((nocf_check));
+ 
+ void
+ foo (void)
+ {
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-4.C gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-4.C
*** gcc-16-20251026/gcc/testsuite/g++.target/i386/cf_check-4.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/g++.target/i386/cf_check-4.C	Sun Nov  2 22:32:57 2025
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-require-weak "" } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc').  */
+ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */
+ 
+ /*
+ **_Z3foov:
+ **.LFB[0-9]+:
+ **	.cfi_startproc
+ **	ret
+ **...
+ */
+ 
+ extern void foo (void) __attribute__((nocf_check));
+ 
+ __attribute__((weak))
+ void
+ foo (void)
+ {
+ }
+ 
+ /* { dg-final { scan-assembler ".weak\[ \t\]_?_Z3foov" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C gcc-16-20251102/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
*** gcc-16-20251026/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C	Sun Oct 26 22:32:38 2025
--- gcc-16-20251102/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C	Sun Nov  2 22:32:57 2025
***************
*** 1,5 ****
--- 1,6 ----
  /* Test that we do not have ice when compile */
  /* { dg-do compile } */
+ /* { dg-skip-if "requires hosted libstdc++ for vector" { ! hostedlib } } */
  /* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target { rv32 } } } */
  /* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target { rv64 } } } */
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c gcc-16-20251102/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c	Sun Oct 26 22:32:38 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/builtin-assume-aligned-1.c	Sun Nov  2 22:33:02 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O3 -fdump-tree-optimized" } */
  
  void
  test1 (double *out1, double *out2, double *out3, double *in1,
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O3 -fno-tree-vectorize -fdump-tree-optimized-alias" } */
  
  void
  test1 (double *out1, double *out2, double *out3, double *in1,
*************** test1 (double *out1, double *out2, doubl
*** 19,24 ****
--- 19,26 ----
      }
  }
  
+ /* { dg-final { scan-tree-dump-times " ALIGN = 16, MISALIGN = 0" 5 "optimized" } } */
+ 
  void
  test2 (double *out1, double *out2, double *out3, double *in1,
         double *in2, int len)
*************** test2 (double *out1, double *out2, doubl
*** 37,40 ****
      }
  }
  
! /* { dg-final { scan-tree-dump-not "__builtin_assume_aligned" "optimized" } } */
--- 39,46 ----
      }
  }
  
! 
! /* { dg-final { scan-tree-dump-times " ALIGN = 32" 5 "optimized" } } */
! /* { dg-final { scan-tree-dump-times " ALIGN = 32, MISALIGN = 16" 4 "optimized" } } */
! /* { dg-final { scan-tree-dump-times " ALIGN = 32, MISALIGN = 0" 1 "optimized" } } */
! 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/complex-8.c gcc-16-20251102/gcc/testsuite/gcc.dg/complex-8.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/complex-8.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/complex-8.c	Sun Nov  2 22:33:02 2025
***************
*** 0 ****
--- 1,13 ----
+ /* PR tree-optimization/122325.  */
+ 
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fdump-tree-cplxlower" } */
+ /* { dg-require-effective-target double64 } */
+ 
+ __complex double
+ foo (__complex double a, __complex double b)
+ {
+   return a / b;
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "__(?:gnu_)?divdc3" 1 "cplxlower1" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/complex-9.c gcc-16-20251102/gcc/testsuite/gcc.dg/complex-9.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/complex-9.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/complex-9.c	Sun Nov  2 22:33:02 2025
***************
*** 0 ****
--- 1,13 ----
+ /* PR tree-optimization/122325.  */
+ 
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -ffast-math -fdump-tree-cplxlower" } */
+ /* { dg-require-effective-target double64 } */
+ 
+ __complex double
+ foo (__complex double a, __complex double b)
+ {
+   return a / b;
+ }
+ 
+ /* { dg-final { scan-tree-dump-not "__(?:gnu_)?divdc3" "cplxlower1" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/cpp/escape-3.i gcc-16-20251102/gcc/testsuite/gcc.dg/cpp/escape-3.i
*** gcc-16-20251026/gcc/testsuite/gcc.dg/cpp/escape-3.i	Sun Oct 26 22:32:39 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/cpp/escape-3.i	Sun Nov  2 22:33:02 2025
*************** int foo (int a, int b)
*** 13,16 ****
  }
  
  /* Test for "/some\\directory" instead of "/some\\\\directory" */
! /* { dg-final { scan-assembler { "/some\\\\directory" } } } */
--- 13,16 ----
  }
  
  /* Test for "/some\\directory" instead of "/some\\\\directory" */
! /* { dg-final { scan-assembler "/some\\\\\\\\directory" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c gcc-16-20251102/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/debug/btf/btf-prune-4.c	Sun Nov  2 22:33:02 2025
***************
*** 0 ****
--- 1,61 ----
+ /* Test that -gprune-btf does not prune at typedefs.  */
+ 
+ /* { dg-do compile } */
+ /* { dg-options "-gbtf -gprune-btf -dA" } */
+ 
+ /* We must have the full definitions of td1 and td3.  Neither are pruned.
+    td2 will be skipped entirely, only because the only reference to
+    it is through struct inner, which is pruned because inner itself
+    is only used as a pointer member.
+ 
+    In general, we must never get an anonymous FWD; the only FWD in this
+    case will be for 'inner' */
+ 
+ /* Exactly 1 FWD for inner and no anonymous FWD.  */
+ /* { dg-final { scan-assembler-times "TYPE \[0-9\]+ BTF_KIND_FWD" 1 } } */
+ /* { dg-final { scan-assembler-not   "TYPE \[0-9\]+ BTF_KIND_FWD ''" } } */
+ /* { dg-final { scan-assembler       " BTF_KIND_FWD 'inner'" } } */
+ 
+ /* One anonymous struct for td1 and one anonymous union for td3.  */
+ /* { dg-final { scan-assembler-times "TYPE \[0-9\]+ BTF_KIND_STRUCT ''" 1 } } */
+ /* { dg-final { scan-assembler-times "TYPE \[0-9\]+ BTF_KIND_UNION ''" 1 } } */
+ 
+ /* The two remaining typedefs.  */
+ /* { dg-final { scan-assembler " BTF_KIND_TYPEDEF 'td1'" } } */
+ /* { dg-final { scan-assembler " BTF_KIND_TYPEDEF 'td3'" } } */
+ 
+ typedef struct {
+   int x;
+   char c;
+ } td1;
+ 
+ typedef struct {
+   long l;
+   char b[4];
+ } td2;
+ 
+ typedef union {
+   long l;
+   unsigned short s[2];
+ } td3;
+ 
+ struct inner {
+   char a;
+   td2 *ptd;
+   long z;
+ };
+ 
+ struct A {
+   td1 *pt;
+   struct inner *in;
+   unsigned long l[4];
+ };
+ 
+ struct A foo;
+ 
+ struct B {
+   int x;
+   td3 **ppptd3;
+ };
+ 
+ struct B bar;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c gcc-16-20251102/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-4.c	Sun Nov  2 22:33:02 2025
***************
*** 0 ****
--- 1,28 ----
+ /* Test DWARF generation for decl_tags on global decls appearing multiple
+    times with different decl_tags.  PR122248.  */
+ /* { dg-do compile } */
+ /* { dg-options "-gdwarf -dA" } */
+ 
+ #define __tag1 __attribute__((btf_decl_tag ("tag1")))
+ #define __tag2 __attribute__((btf_decl_tag ("tag2")))
+ #define __tag3 __attribute__((btf_decl_tag ("tag3")))
+ #define __tag4 __attribute__((btf_decl_tag ("tag4")))
+ 
+ int foo __tag1;
+ int foo __tag2;
+ 
+ /* Result: foo has __tag1 and __tag2.  */
+ 
+ int bar __tag3;
+ int bar;
+ 
+ /* Result: bar has __tag3.  */
+ 
+ int baz;
+ int baz __tag4;
+ 
+ /* Result: baz has __tag4.  */
+ 
+ /* { dg-final { scan-assembler-times "DIE \\(\[^\n\]*\\) DW_TAG_GNU_annotation" 4 } } */
+ /* { dg-final { scan-assembler-times " DW_AT_GNU_annotation" 4 } } */
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c gcc-16-20251102/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-5.c	Sun Nov  2 22:33:02 2025
***************
*** 0 ****
--- 1,35 ----
+ /* Test DWARF generation for decl_tags on global decls appearing multiple
+    times with different decl_tags.  PR122248.  */
+ /* { dg-do compile } */
+ /* { dg-options "-gdwarf -dA" } */
+ 
+ #define __tag1 __attribute__((btf_decl_tag ("tag1")))
+ #define __tag2 __attribute__((btf_decl_tag ("tag2")))
+ #define __tag3 __attribute__((btf_decl_tag ("tag3")))
+ 
+ struct S
+ {
+   int x;
+   char c;
+ };
+ 
+ extern struct S foo __tag1;
+ struct S foo __tag2;
+ 
+ /* Result: non-completing variable DIE for 'foo' has tag1, and the
+    completing DIE (with AT_specification) for 'foo' has tag2 -> tag1.  */
+ 
+ extern int a __tag3;
+ int a;
+ 
+ /* Result: non-completing variable DIE for a has tag3, and the
+    completing DIE (with AT_specification) for 'a' also refers to tag3.  */
+ 
+ /* { dg-final { scan-assembler-times "DIE \\(\[^\n\]*\\) DW_TAG_GNU_annotation" 3 } } */
+ 
+ /* 5 AT_GNU annotations:
+    - foo -> tag1
+    - foo -> tag2 -> tag1
+    - a -> tag3
+    - a -> tag3 */
+ /* { dg-final { scan-assembler-times " DW_AT_GNU_annotation" 5 } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c gcc-16-20251102/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-btf-decl-tag-6.c	Sun Nov  2 22:33:03 2025
***************
*** 0 ****
--- 1,24 ----
+ /* Test DWARF generation for decl_tags on global decls appearing multiple
+    times with different decl_tags.  PR122248.  */
+ /* { dg-do compile } */
+ /* { dg-options "-gdwarf -dA" } */
+ 
+ #define __tag1 __attribute__((btf_decl_tag ("tag1")))
+ #define __tag2 __attribute__((btf_decl_tag ("tag2")))
+ #define __tag3 __attribute__((btf_decl_tag ("tag3")))
+ 
+ __tag1
+ extern int
+ do_thing (int);
+ 
+ __tag2
+ __tag3
+ int
+ do_thing (int x)
+ {
+   return x * x;
+ }
+ 
+ /* Result: do_thing has all 3 tags.  */
+ /* { dg-final { scan-assembler-times "DIE \\(\[^\n\]*\\) DW_TAG_GNU_annotation" 3 } } */
+ /* { dg-final { scan-assembler-times " DW_AT_GNU_annotation" 3 } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/fold-vecperm-1.c gcc-16-20251102/gcc/testsuite/gcc.dg/fold-vecperm-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/fold-vecperm-1.c	Sun Oct 26 22:32:39 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/fold-vecperm-1.c	Sun Nov  2 22:33:03 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  typedef int v4si __attribute__((vector_size(16)));
  typedef short v8hi __attribute__((vector_size(16)));
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -fdump-tree-forwprop3" } */
  
  typedef int v4si __attribute__((vector_size(16)));
  typedef short v8hi __attribute__((vector_size(16)));
*************** int128 concat (int128 a, int128 b) {
*** 20,23 ****
    return res;
  }
  
! /* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 1 "optimized" } } */
--- 20,23 ----
    return res;
  }
  
! /* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 1 "forwprop3" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c gcc-16-20251102/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/gnu-compoundlit-1.c	Sun Nov  2 22:33:03 2025
***************
*** 0 ****
--- 1,26 ----
+ /* { dg-do compile } */
+ /* { dg-options "-std=gnu23" } */
+ 
+ int g(int n, int (*p)[n]);
+ int f(int n)
+ {
+ 	return g(n, &(int[n]){ });
+ }
+ 
+ void h(int n)
+ {
+ 	(int[n]){ 1 };		/* { dg-error "empty initializer" } */
+ }
+ 
+ void i(int n)
+ {
+ 	(static int[3]){ };
+ 	(static int[n]){ };	/* { dg-error "storage size" } */
+ 	(constexpr int[3]){ };
+ 	(constexpr int[n]){ };	/* { dg-error "storage size" } */
+ 	(register int[3]){ };	/* { dg-error "register" } */
+ 	(register int[n]){ };	/* { dg-error "register" } */
+ 	(_Thread_local int[3]){ };	/* { dg-error "_Thread_local" } */
+ 	(_Thread_local int[n]){ };	/* { dg-error "_Thread_local" } */
+ }
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c gcc-16-20251102/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/gnu-compoundlit-2.c	Sun Nov  2 22:33:03 2025
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do run } */
+ /* { dg-options "-std=gnu23 -Wall" } */
+ 
+ [[gnu::noinline,gnu::noipa]]
+ static bool f(int n)
+ {
+ 	struct foo { char a[n]; };
+ 	struct foo x = { };
+ 
+ 	return 0 == __builtin_memcmp(&x, &(struct foo){ }, sizeof x);
+ }
+ 
+ int main()
+ {
+ 	if (!f(7))
+ 		__builtin_abort();
+ 
+ 	return 0;
+ }
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pointer-counted-by-10.c gcc-16-20251102/gcc/testsuite/gcc.dg/pointer-counted-by-10.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pointer-counted-by-10.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pointer-counted-by-10.c	Sun Nov  2 22:33:04 2025
***************
*** 0 ****
--- 1,8 ----
+ /* Testing the correct usage of attribute counted_by for pointer to void.  */
+ /* { dg-do compile } */
+ /* { dg-options "-O0 -Wpointer-arith" } */
+ 
+ struct pointer_array {
+   int count;
+   void *array __attribute__ ((counted_by (count))); /* { dg-warning "attribute is used for a pointer to void" } */
+ }; 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c gcc-16-20251102/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pointer-counted-by-4-void.c	Sun Nov  2 22:33:04 2025
***************
*** 0 ****
--- 1,6 ----
+ /* Test the attribute counted_by for pointer field and its usage in
+  * __builtin_dynamic_object_size.  */ 
+ /* { dg-do run } */
+ /* { dg-options "-O2" } */
+ #define PTR_TYPE void 
+ #include "pointer-counted-by-4.c"
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pointer-counted-by.c gcc-16-20251102/gcc/testsuite/gcc.dg/pointer-counted-by.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pointer-counted-by.c	Sun Oct 26 22:32:39 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pointer-counted-by.c	Sun Nov  2 22:33:04 2025
*************** struct pointer_array_6 {
*** 49,57 ****
    int *array_6 __attribute__ ((counted_by (days)));
  }; 
  
  struct pointer_array_7 {
    int count;
!   void *array_7 __attribute__ ((counted_by (count))); /* { dg-error "attribute is not allowed for a pointer to void" } */
  }; 
  
  struct pointer_array_8 {
--- 49,58 ----
    int *array_6 __attribute__ ((counted_by (days)));
  }; 
  
+ /* counted_by is allowed for pointer to void when GNU extension is enabled.  */
  struct pointer_array_7 {
    int count;
!   void *array_7 __attribute__ ((counted_by (count)));
  }; 
  
  struct pointer_array_8 {
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr107389.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr107389.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr107389.c	Sun Oct 26 22:32:39 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr107389.c	Thu Jan  1 00:00:00 1970
***************
*** 1,13 ****
- /* { dg-do compile } */
- /* { dg-options "-fdump-tree-optimized-alias" } */
- 
- unsigned foo (void *p)
- {
-   unsigned i;
-   __builtin_memcpy (&i, __builtin_assume_aligned (p, 4), sizeof (unsigned));
-   return i;
- }
- 
- /* Even when not optimizing we should have alignment info on the temporary
-    feeding the memcpy.  */
- /* { dg-final { scan-tree-dump "ALIGN = 4" "optimized" } } */
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr116815.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr116815.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr116815.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr116815.c	Sun Nov  2 22:33:04 2025
***************
*** 0 ****
--- 1,57 ----
+ /* PR target/116815 */
+ /* { dg-do run } */
+ /* { dg-options "-O2" } */
+ 
+ [[gnu::always_inline]]
+ inline unsigned min (unsigned a, unsigned b)
+ {
+   return (a < b) ? a : b;
+ }
+ 
+ [[gnu::always_inline]]
+ inline unsigned max (unsigned a, unsigned b)
+ {
+   return (a > b) ? a : b;
+ }
+ 
+ [[gnu::noipa]] unsigned
+ umaxadd (unsigned a, unsigned b)
+ {
+   return max (a + b, a);
+ }
+ 
+ [[gnu::noipa]] unsigned
+ umaxsub (unsigned a, unsigned b)
+ {
+   return max (a - b, a);
+ }
+ 
+ [[gnu::noipa]] unsigned
+ uminadd (unsigned a, unsigned b)
+ {
+   return min (a + b, a);
+ }
+ 
+ [[gnu::noipa]] unsigned
+ uminsub (unsigned a, unsigned b)
+ {
+   return min (a - b, a);
+ }
+ 
+ int
+ main ()
+ {
+   /* Overflows to 0x30000000.  */
+   if (umaxadd (0x90000000, 0xa0000000) != 0x90000000)
+     __builtin_abort ();
+ 
+   if (uminadd (0x90000000, 0xa0000000) != 0x30000000)
+     __builtin_abort ();
+ 
+   /* Underflows to 0x60000000.  */
+   if (umaxsub (0x00000000, 0xa0000000) != 0x60000000)
+     __builtin_abort ();
+ 
+   if (uminsub (0x00000000, 0xa0000000) != 0x00000000)
+     __builtin_abort ();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr41488.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr41488.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr41488.c	Sun Oct 26 22:32:39 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr41488.c	Sun Nov  2 22:33:04 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -fdump-tree-ivcanon-scev" } */
  
  struct struct_t
  {
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -fno-tree-scev-cprop -fdump-tree-ivcanon-scev" } */
  
  struct struct_t
  {
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr68090.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr68090.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr68090.c	Sun Oct 26 22:32:39 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr68090.c	Sun Nov  2 22:33:04 2025
***************
*** 1,13 ****
  /* PR c/68090 */
  /* { dg-do compile } */
! /* { dg-options "" } */
  
  void
  fn (int i)
  {
    (int[(0, 1)]) { 0 }; /* { dg-error "compound literal has variable size" } */
    (int[i]) { 0 }; /* { dg-error "compound literal has variable size" } */
    (int[(0, i)]) { 0 }; /* { dg-error "compound literal has variable size" } */
    (int [][i]){ 0 }; /* { dg-error "compound literal has variable size" } */
    (int [][(1, 2)]){ 0 }; /* { dg-error "compound literal has variable size" } */
  }
--- 1,18 ----
  /* PR c/68090 */
  /* { dg-do compile } */
! /* { dg-options "--pedantic-error" } */
  
  void
  fn (int i)
  {
    (int[(0, 1)]) { 0 }; /* { dg-error "compound literal has variable size" } */
+   			/* { dg-error "variable-size" "" { target *-*-* } .-1 } */
    (int[i]) { 0 }; /* { dg-error "compound literal has variable size" } */
+   			/* { dg-error "variable-size" "" { target *-*-* } .-1 } */
    (int[(0, i)]) { 0 }; /* { dg-error "compound literal has variable size" } */
+   			/* { dg-error "variable-size" "" { target *-*-* } .-1 } */
    (int [][i]){ 0 }; /* { dg-error "compound literal has variable size" } */
+   			/* { dg-error "variable-size" "" { target *-*-* } .-1 } */
    (int [][(1, 2)]){ 0 }; /* { dg-error "compound literal has variable size" } */
+   			/* { dg-error "variable-size" "" { target *-*-* } .-1 } */
  }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr91191.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr91191.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr91191.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr91191.c	Sun Nov  2 22:33:04 2025
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fdump-tree-evrp" } */
+ 
+ unsigned char reg(_Bool b) {
+     union U {
+         unsigned char f0;
+         _Bool f1;
+     };
+     union U u;
+     u.f1 = b;
+     if (u.f0 > 1) {
+         // This cannot happen
+         // if b is only allowed
+         // to be 0 or 1:
+         return 42;
+     }
+     return 13;
+ }
+ 
+ /* { dg-final { scan-tree-dump "return 13"  "evrp" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr97986-1.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr97986-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr97986-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr97986-1.c	Sun Nov  2 22:33:04 2025
***************
*** 0 ****
--- 1,27 ----
+ /* { dg-do run } */
+ /* { dg-options "-std=gnu23" } */
+ 
+ #include <stdarg.h>
+ 
+ int f(int n, ...)
+ {
+ 	__label__ b, d;
+ 	va_list ap;
+ 	va_start(ap, n);
+ 	_Static_assert(5 == sizeof(va_arg(ap, char[5])));	/* { dg-warning "array type" } */
+ 	void g(void) { n++; goto b; }
+ 	int *a = va_arg((g(), ap), int[n]);	/* { dg-warning "array type" } */
+ b:
+ 	void h(void) { n++; goto d; }
+ 	typeof(va_arg(ap, int[(h(), n)])) c;	/* { dg-warning "array type" } */
+ d:
+ 	return n;
+ }
+ 
+ int main()
+ {
+ 	if (9 != f(7))
+ 		__builtin_abort();
+ 	return 0;
+ }
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/pr97986-2.c gcc-16-20251102/gcc/testsuite/gcc.dg/pr97986-2.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/pr97986-2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/pr97986-2.c	Sun Nov  2 22:33:04 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-std=c90" } */
+ 
+ #include <stdarg.h>
+ 
+ 
+ int f(int n, ...)
+ {
+ 	va_list ap;
+ 	va_start(ap, n);
+ 	_Static_assert(5 == sizeof(va_arg(ap, char[5])));
+ 	va_arg(ap, int[n]);			/* { dg-error "array type" } */
+ 	int * a = va_arg(ap, int[3]);		/* { dg-error "invalid use of non-lvalue array" } */
+ }
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/torture/pr107389.c gcc-16-20251102/gcc/testsuite/gcc.dg/torture/pr107389.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/torture/pr107389.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/torture/pr107389.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+ /* { dg-additional-options "-fdump-tree-optimized-alias" } */
+ 
+ unsigned foo (void *p)
+ {
+   unsigned i;
+   __builtin_memcpy (&i, __builtin_assume_aligned (p, 4), sizeof (unsigned));
+   return i;
+ }
+ 
+ /* Even when not optimizing we should have alignment info on the temporary
+    feeding the memcpy.  */
+ /* { dg-final { scan-tree-dump "ALIGN = 4" "optimized" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/torture/pr122497-1.c gcc-16-20251102/gcc/testsuite/gcc.dg/torture/pr122497-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/torture/pr122497-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/torture/pr122497-1.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* PR tree-optimization/122497 */
+ 
+ /* This was ICEing during SCCP
+    trying to simplify a reference back to the phi
+    which was removed.  */
+ 
+ char g_2[1][2];
+ int g_4, g_5;
+ void main() {
+   for (; g_4; g_4 -= 1)
+     g_5 = g_2[g_4 + 2][g_4];
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/torture/pr122502.c gcc-16-20251102/gcc/testsuite/gcc.dg/torture/pr122502.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/torture/pr122502.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/torture/pr122502.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ 
+ short int *ts;
+ 
+ void
+ c2 (unsigned long long int s4, int ns)
+ {
+   short int *b2 = (short int *)&ns;
+ 
+   while (ns != 0)
+     {
+       int xn;
+ 
+       for (xn = 0; xn < 3; ++xn)
+         for (*b2 = 0; *b2 < 2; ++*b2)
+           s4 += xn;
+       if (s4 != 0)
+         b2 = ts;
+       ++ns;
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-ch.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fdump-tree-optimized" } */
+ 
+ typedef unsigned long BITMAP_WORD;
+ 
+ bool
+ bmp_iter_set (BITMAP_WORD bits, unsigned *bit_no)
+ {
+   /* If our current word is nonzero, it contains the bit we want.  */
+   if (bits)
+     {
+       while (!(bits & 1))
+ 	{
+ 	  bits >>= 1;
+ 	  *bit_no += 1;
+ 	}
+       return true;
+     }
+ 
+   return false;
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "__builtin_ctz|\\.CTZ" 1 "optimized" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-char.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-char.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-int.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_INT__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_INT__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long-long.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctzll } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG_LONG__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctzll } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG_LONG__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-complement-long.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctzl } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctzl } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-int.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_INT__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctz } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_INT__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-long-long.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctzll } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG_LONG__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctzll } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG_LONG__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ctz-long.c	Sun Nov  2 22:33:05 2025
***************
*** 1,6 ****
  /* { dg-do run } */
  /* { dg-require-effective-target ctzl } */
! /* { dg-options "-O2 -fno-tree-ch -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG__)
  
--- 1,6 ----
  /* { dg-do run } */
  /* { dg-require-effective-target ctzl } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
  
  #define PREC (__CHAR_BIT__ * __SIZEOF_LONG__)
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,12 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fdump-tree-forwprop1" } */
+ 
+ typedef unsigned int vec2 __attribute__ ((vector_size (2 * sizeof (unsigned int))));
+ typedef unsigned int vec1 __attribute__ ((vector_size (sizeof (unsigned int))));
+ 
+ vec1 foo (vec2 x)
+ {
+ 	return (vec1) x[1];
+ }
+ 
+ /* { dg-final { scan-tree-dump-not "VIEW_CONVERT_EXPR" "forwprop1" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/pr111003.c	Sun Nov  2 22:33:05 2025
*************** static int *i() {
*** 31,34 ****
  }
  int main() { k(c, c); }
  
! /* { dg-final { scan-tree-dump-not "foo" "optimized" } } */
--- 31,34 ----
  }
  int main() { k(c, c); }
  
! /* { dg-final { scan-tree-dump-not "foo" "optimized" { xfail *-*-* } } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/pr122478.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fdump-tree-optimized" } */
+ /* { dg-additional-options "-fgimple" } */
+ 
+ unsigned char __GIMPLE (ssa)
+ foo (unsigned short mask__701)
+ {
+   _Bool _19;
+   unsigned char _180;
+ 
+ __BB(2):
+   _19 = __BIT_FIELD_REF <_Bool> (mask__701, 1, 12);
+   _180 = __VIEW_CONVERT<unsigned char>(_19);
+   return _180;
+ }
+ 
+ /* { dg-final { scan-tree-dump-times "VIEW_CONVERT_EXPR" 1 "optimized" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/pr92834.c	Sun Nov  2 22:33:05 2025
***************
*** 1,8 ****
  /* PR tree-optimization/92834 */
  /* { dg-do compile } */
! /* { dg-options "-O2 -fdump-tree-optimized" } */
! /* { dg-final { scan-tree-dump-times "MIN_EXPR <" 8 "optimized" } } */
! /* { dg-final { scan-tree-dump-times "MAX_EXPR <" 8 "optimized" } } */
  
  static inline unsigned
  umax1 (unsigned a, unsigned b)
--- 1,8 ----
  /* PR tree-optimization/92834 */
  /* { dg-do compile } */
! /* { dg-options "-O2 -fdump-tree-phiopt1" } */
! /* { dg-final { scan-tree-dump-times "MIN_EXPR <" 16 "phiopt1" } } */
! /* { dg-final { scan-tree-dump-times "MAX_EXPR <" 16 "phiopt1" } } */
  
  static inline unsigned
  umax1 (unsigned a, unsigned b)
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-111.c	Sun Nov  2 22:33:05 2025
***************
*** 0 ****
--- 1,11 ----
+ /* PR122435 */
+ /* { dg-do compile } */
+ /* { dg-options "-O -fdump-tree-fre1-details" } */
+ 
+ void foo (unsigned *p)
+ {
+   int i = *p;
+   *(int *)p = i;
+ }
+ 
+ /* { dg-final { scan-tree-dump "Deleted redundant store" "fre1" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/pr122419.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/pr122419.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/pr122419.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/pr122419.c	Sun Nov  2 22:33:06 2025
***************
*** 0 ****
--- 1,9 ----
+ /* { dg-do compile } */
+ 
+ int a;
+ long b;
+ void c()
+ {
+   for (; b; b--)
+     a = (char)a;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/slp-reduc-13.c	Sun Nov  2 22:33:06 2025
***************
*** 0 ****
--- 1,66 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target vect_int } */
+ /* { dg-additional-options "-fgimple" } */
+ 
+ int q[2];
+ 
+ void __GIMPLE (ssa,guessed_local(16535624),startwith("loop"))
+ foo (int * r)
+ {
+   int i;
+   int sum2;
+   int sum1;
+   int _1;
+   long unsigned int _2;
+   long unsigned int _3;
+   int * _4;
+   int _24;
+   __SIZETYPE__ _6;
+   __SIZETYPE__ _7;
+   int * _8;
+   int _9;
+   int _13;
+   unsigned int _30;
+   unsigned int _31;
+ 
+   __BB(2,guessed_local(16535624)):
+   goto __BB3(precise(134217728));
+ 
+   __BB(3,loop_header(1),guessed_local(1057206200)):
+   sum1_5 = __PHI (__BB5: sum1_18, __BB2: 0);
+   sum2_26 = __PHI (__BB5: sum2_19, __BB2: 0);
+   i_28 = __PHI (__BB5: i_20, __BB2: 0);
+   _31 = __PHI (__BB5: _30, __BB2: 64u);
+   _1 = i_28 * 2;
+   _2 = (long unsigned int) _1;
+   _3 = _2 * 4ul;
+   _4 = r_17(D) + _3;
+   _24 = __MEM <int> (_4);
+   /* Deliberately have swapped operands here */
+   sum1_18 = sum1_5 + _24;
+   _13 = _1 + 1;
+   _6 = (__SIZETYPE__) _13;
+   _7 = _6 * 4ul;
+   _8 = r_17(D) + _7;
+   _9 = __MEM <int> (_8);
+   /* versus here.  */
+   sum2_19 = _9 + sum2_26;
+   i_20 = i_28 + 1;
+   _30 = _31 - 1u;
+   if (_30 != 0u)
+     goto __BB5(guessed(132118446));
+   else
+     goto __BB4(guessed(2099282));
+ 
+   __BB(5,guessed_local(1040670576)):
+   goto __BB3(precise(134217728));
+ 
+   __BB(4,guessed_local(16535624)):
+   sum1_33 = __PHI (__BB3: sum1_18);
+   sum2_32 = __PHI (__BB3: sum2_19);
+   q[0] = sum1_33;
+   q[1] = sum2_32;
+   return;
+ }
+ 
+ /* { dg-final { scan-tree-dump "SLP discovery of size 2 reduction group succeeded" "vect" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c	Sun Nov  2 22:33:06 2025
***************
*** 1,7 ****
  /* Disabling epilogues until we find a better way to deal with scans.  */
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */
  
  #include "tree-vect.h"
  
--- 1,6 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/tree-vect.h gcc-16-20251102/gcc/testsuite/gcc.dg/vect/tree-vect.h
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/tree-vect.h	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/tree-vect.h	Sun Nov  2 22:33:06 2025
*************** check_vect (void)
*** 76,81 ****
--- 76,83 ----
    }
  #elif defined(__mips_msa)
    asm volatile ("or.v $w0,$w0,$w0");
+ #elif defined(__loongarch__)
+   asm volatile ("vor.v\t$vr0,$vr0,$vr0");
  #endif
    signal (SIGILL, SIG_DFL);
  }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c	Sun Nov  2 22:33:07 2025
***************
*** 2,8 ****
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
  /* { dg-additional-options "-fno-ipa-icf" } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include "tree-vect.h"
  
--- 2,7 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c	Sun Nov  2 22:33:07 2025
***************
*** 2,8 ****
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
  /* { dg-additional-options "-fno-ipa-icf" } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include "tree-vect.h"
  
--- 2,7 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c	Sun Nov  2 22:33:07 2025
***************
*** 2,8 ****
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
  /* { dg-additional-options "-fno-ipa-icf" } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include "tree-vect.h"
  
--- 2,7 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c	Sun Nov  2 22:33:07 2025
***************
*** 1,7 ****
  /* Disabling epilogues until we find a better way to deal with scans.  */
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include "tree-vect.h"
  
--- 1,6 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c	Sun Nov  2 22:33:07 2025
***************
*** 1,7 ****
  /* Disabling epilogues until we find a better way to deal with scans.  */
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include <stdarg.h>
  #include "tree-vect.h"
--- 1,6 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c	Sun Nov  2 22:33:07 2025
***************
*** 1,7 ****
  /* Disabling epilogues until we find a better way to deal with scans.  */
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include <stdarg.h>
  #include "tree-vect.h"
--- 1,6 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c	Sun Nov  2 22:33:07 2025
***************
*** 1,6 ****
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */
  
  #include <stdarg.h>
  #include "tree-vect.h"
--- 1,5 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c	Sun Nov  2 22:33:07 2025
***************
*** 1,6 ****
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_int } */
- /* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
  
  #include <stdarg.h>
  #include "tree-vect.h"
--- 1,5 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vla-init-4.c gcc-16-20251102/gcc/testsuite/gcc.dg/vla-init-4.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vla-init-4.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vla-init-4.c	Sun Nov  2 22:33:07 2025
***************
*** 4,7 ****
  /* { dg-options "" } */
  
  const int i = 1;
! void foo() { char *p = (char [i]){ "" }; } /* { dg-error "compound literal has variable size" } */
--- 4,7 ----
  /* { dg-options "" } */
  
  const int i = 1;
! void foo() { char *p = (char [i]){ "" }; } /* { dg-error "variable-sized object" } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.dg/vla-init-5.c gcc-16-20251102/gcc/testsuite/gcc.dg/vla-init-5.c
*** gcc-16-20251026/gcc/testsuite/gcc.dg/vla-init-5.c	Sun Oct 26 22:32:40 2025
--- gcc-16-20251102/gcc/testsuite/gcc.dg/vla-init-5.c	Sun Nov  2 22:33:07 2025
***************
*** 4,7 ****
  /* { dg-options "" } */
  
  const int i = 1;
! void foo() { void *p = (char [][i]){ "" }; } /* { dg-error "compound literal has variable size" } */
--- 4,7 ----
  /* { dg-options "" } */
  
  const int i = 1;
! void foo() { void *p = (char [][i]){ "" }; } /* { dg-error "variable-sized object" } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/pr121853_1.c gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/pr121853_1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/pr121853_1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/pr121853_1.c	Sun Nov  2 22:33:08 2025
***************
*** 0 ****
--- 1,64 ----
+ /* { dg-do run } */
+ /* { dg-additional-options "-O2 -std=c99" } */
+ 
+ #include <stdint.h>
+ #include <stdio.h>
+ #include <string.h>
+ 
+ __attribute__ ((noipa))
+ float convert(__bf16 value) {
+     return (float)value;
+ }
+ 
+ static inline uint32_t f32_bits(float f) {
+     uint32_t u; memcpy(&u, &f, sizeof u); return u;
+ }
+ static inline __bf16 bf16_from_bits(uint16_t u) {
+     __bf16 b;  memcpy(&b, &u, sizeof b); return b;
+ }
+ 
+ /* Fixed bf16 inputs (as raw 16-bit payloads) covering edge cases.  */
+ static const uint16_t inputs[] = {
+     0x0000, // +0
+     0x8000, // -0
+     0x7F80, // +inf
+     0xFF80, // -inf
+     0x7FC0, // qNaN (+)  (quiet bit set in bf16)
+     0xFFC0, // qNaN (-)
+     0x7F01, // sNaN (+)  (will be quieted by conversion)
+     0xFF01, // sNaN (-)
+     0x0001, // smallest +subnormal
+     0x007F, // largest  +subnormal
+     0x8001, // smallest -subnormal
+     0x807F, // largest  -subnormal
+     0x0080, // smallest +normal
+     0x3F80, // +1.0
+     0xBF80, // -1.0
+     0x3F00, // +0.5
+     0xBF00, // -0.5
+     0x3FC0, // +1.5
+     0x7F7F, // max finite +
+     0xFF7F, // max finite -
+ };
+ 
+ int main(void) {
+     const size_t N = sizeof(inputs)/sizeof(inputs[0]);
+     size_t fails = 0;
+ 
+     for (size_t i = 0; i < N; ++i) {
+         __bf16 in = bf16_from_bits(inputs[i]);
+         float out = convert(in);
+         uint32_t got = f32_bits(out);
+         uint32_t exp = inputs[i] << 16;
+ 
+         if (got != exp) {
+             printf("FAIL[%zu]: in_bf16=0x%04X  exp_f32=0x%08X  got_f32=0x%08X\n",
+                    i, inputs[i], exp, got);
+             ++fails;
+         }
+     }
+ 
+     if (fails != 0)
+       __builtin_abort ();
+ }
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/pr121853_2.c gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/pr121853_2.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/pr121853_2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/pr121853_2.c	Sun Nov  2 22:33:08 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-O1" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ float convert(__bf16 value) {
+     return (float)value;
+ }
+ 
+ /*
+ ** convert:
+ **	movi	v[0-9]+.4s, 0
+ **	ext	v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b, #14
+ **	ret
+ */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-1.c	Sun Nov  2 22:33:10 2025
***************
*** 0 ****
--- 1,26 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O -fdump-tree-optimized" } */
+ /* PR target/116075 */
+ 
+ #include <arm_sve.h>
+ 
+ svint8_t f(void)
+ {
+   svint8_t tt;
+   tt = svdup_s8 (0);
+   tt = svinsr (tt, 0);
+   return tt;
+ }
+ 
+ svint8_t f1(int8_t t)
+ {
+   svint8_t tt;
+   tt = svdup_s8 (t);
+   tt = svinsr (tt, t);
+   return tt;
+ }
+ 
+ /* The above 2 functions should have removed the VEC_SHL_INSERT. */
+ 
+ /* { dg-final { scan-tree-dump-not ".VEC_SHL_INSERT " "optimized" } } */
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/aarch64/sve/dup-insr-2.c	Sun Nov  2 22:33:10 2025
***************
*** 0 ****
--- 1,26 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O -fdump-tree-optimized" } */
+ /* PR target/116075 */
+ 
+ #include <arm_sve.h>
+ 
+ svint8_t f(int8_t t)
+ {
+   svint8_t tt;
+   tt = svdup_s8 (0);
+   tt = svinsr (tt, t);
+   return tt;
+ }
+ 
+ svint8_t f1(int8_t t)
+ {
+   svint8_t tt;
+   tt = svdup_s8 (t);
+   tt = svinsr (tt, 0);
+   return tt;
+ }
+ 
+ /* The above 2 functions should not have removed the VEC_SHL_INSERT. */
+ 
+ /* { dg-final { scan-tree-dump-times ".VEC_SHL_INSERT " 2 "optimized" } } */
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/avr/pr121198.c gcc-16-20251102/gcc/testsuite/gcc.target/avr/pr121198.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/avr/pr121198.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/avr/pr121198.c	Sun Nov  2 22:33:13 2025
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-do compile } */
+ /* { dg-options "-Os -mmcu=atmega8" } */
+ 
+ long
+ test (void)
+ {
+   long x;
+   __asm__ ("" : "={r22}" (x));
+   return x;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c gcc-16-20251102/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c	Sun Oct 26 22:32:41 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/avr/torture/pr84211-fuse-move-1.c	Sun Nov  2 22:33:13 2025
***************
*** 1,5 ****
  /* { dg-do run } */
! /* { dg-additional-options -std=gnu99 } */
  
  #define USE_VALUE 0
  
--- 1,6 ----
  /* { dg-do run } */
! /* Disable LTO since it has problems with flobal asm. */
! /* { dg-additional-options { -std=gnu99 -fno-lto } } */
  
  #define USE_VALUE 0
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c	Sun Oct 26 22:32:42 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/builtin-copysign-8b.c	Sun Nov  2 22:33:17 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mno-avx512f -mavx" } */
  /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc').  */
  /* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mno-avx512f -mavx -mtune=generic" } */
  /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc').  */
  /* { dg-final { check-function-bodies "**" "" "" { target { ! ia32 } } {^\t?\.} } } */
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-10.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-10.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-10.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-10.c	Sun Nov  2 22:33:17 2025
***************
*** 0 ****
--- 1,19 ----
+ /* PR c/122427 */
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ 
+ extern void foo (void) __attribute__((nocf_check));
+ extern void foo (void);
+ 
+ void
+ foo (void)
+ {
+ }
+ 
+ extern void bar (void);
+ extern void bar (void) __attribute__((nocf_check)); /* { dg-error "conflicting types" } */
+ 
+ void
+ bar (void)
+ {
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-11.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-11.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-11.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-11.c	Sun Nov  2 22:33:17 2025
***************
*** 0 ****
--- 1,24 ----
+ /* PR c/122427 */
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-require-weak "" } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc').  */
+ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */
+ 
+ /*
+ **foo:
+ **.LFB[0-9]+:
+ **	.cfi_startproc
+ **	ret
+ **...
+ */
+ 
+ extern void foo (void) __attribute__((nocf_check));
+ 
+ __attribute__((weak))
+ void
+ foo (void)
+ {
+ }
+ 
+ /* { dg-final { scan-assembler ".weak\[ \t\]_?foo" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-7.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-7.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-7.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-7.c	Sun Nov  2 22:33:17 2025
***************
*** 0 ****
--- 1,20 ----
+ /* PR c/122427 */
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ /* Keep labels and directives ('.cfi_startproc', '.cfi_endproc').  */
+ /* { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {^\t?\.} } } */
+ 
+ /*
+ **foo:
+ **.LFB[0-9]+:
+ **	.cfi_startproc
+ **	ret
+ **...
+ */
+ 
+ extern void foo (void) __attribute__((nocf_check));
+ 
+ void
+ foo (void)
+ {
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-8.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-8.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-8.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-8.c	Sun Nov  2 22:33:17 2025
***************
*** 0 ****
--- 1,11 ----
+ /* PR c/122427 */
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ 
+ extern void foo (void);
+ 
+ __attribute__((nocf_check))
+ void
+ foo (void) /* { dg-error "conflicting types" } */
+ {
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-9.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-9.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/cf_check-9.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/cf_check-9.c	Sun Nov  2 22:33:17 2025
***************
*** 0 ****
--- 1,15 ----
+ /* PR c/122427 */
+ /* { dg-do compile { target { "i?86-*-* x86_64-*-*" } } } */
+ /* { dg-options "-O2 -fcf-protection" } */
+ 
+ extern void bar (void);
+ extern void bar (void) __attribute__((nocf_check)); /* { dg-error "conflicting types" } */
+ extern void foo (void) __attribute__((nocf_check));
+ extern void foo (void);
+ 
+ void
+ func (void)
+ {
+   bar ();
+   foo ();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c	Sun Oct 26 22:32:42 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/no-callee-saved-12.c	Sun Nov  2 22:33:18 2025
***************
*** 1,10 ****
  /* { dg-do compile } */
  /* { dg-options "-O2" } */
  
! extern void foo (void) __attribute__ ((no_callee_saved_registers)); /* { dg-note "previous declaration" } */
  
  void
! foo (void) /* { dg-error "conflicting types" } */
  {
  }
- 
--- 1,9 ----
  /* { dg-do compile } */
  /* { dg-options "-O2" } */
  
! extern void foo (void) __attribute__ ((no_callee_saved_registers));
  
  void
! foo (void)
  {
  }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/pr116815.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/pr116815.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/pr116815.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/pr116815.c	Sun Nov  2 22:33:18 2025
***************
*** 0 ****
--- 1,31 ----
+ /* PR target/116815 */
+ /* { dg-do compile } */
+ /* { dg-options "-O2" } */
+ /* { dg-additional-options "-march=pentiumpro" { target ia32 } } */
+ 
+ static inline __attribute__ ((always_inline))
+ unsigned max (unsigned a, unsigned b) { return a > b ? a : b; }
+ 
+ static inline __attribute__ ((always_inline))
+ unsigned min (unsigned a, unsigned b) { return a < b ? a : b; }
+ 
+ #define OPERATION(op, type, N, exp1, exp2) \
+   unsigned u##op##type##N (unsigned a, unsigned b) { return op (exp1, exp2); }
+ 
+ OPERATION (max, add, 1, a, a + b)
+ OPERATION (max, add, 2, a, b + a)
+ OPERATION (max, add, 3, a + b, a)
+ OPERATION (max, add, 4, b + a, a)
+ 
+ OPERATION (min, add, 1, a, a + b)
+ OPERATION (min, add, 2, a, b + a)
+ OPERATION (min, add, 3, a + b, a)
+ OPERATION (min, add, 4, b + a, a)
+ 
+ OPERATION (max, sub, 1, a, a - b)
+ OPERATION (max, sub, 2, a - b, a)
+ 
+ OPERATION (min, sub, 1, a, a - b)
+ OPERATION (min, sub, 2, a - b, a)
+ 
+ /* { dg-final { scan-assembler-not "cmp" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/pr122457.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/pr122457.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/pr122457.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/pr122457.c	Sun Nov  2 22:33:19 2025
***************
*** 0 ****
--- 1,4 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -march=x86-64-v4 -mavxvnniint16" } */
+ 
+ #include "vnniint16-auto-vectorize-2.c"
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/pr122518.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/pr122518.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/pr122518.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/pr122518.c	Sun Nov  2 22:33:19 2025
***************
*** 0 ****
--- 1,15 ----
+ /* PR target/122518 */
+ /* { dg-do compile } */
+ /* { dg-options "-O2" } */
+ 
+ inline unsigned min (unsigned a, unsigned b)
+ {
+   return (a < b) ? a : b;
+ }
+ 
+ unsigned uminsub (unsigned a, unsigned b)
+ {
+   return min (a - b, a);
+ }
+ 
+ /* { dg-final { scan-assembler-not "cmp" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/i386/preserve-none-17.c gcc-16-20251102/gcc/testsuite/gcc.target/i386/preserve-none-17.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/i386/preserve-none-17.c	Sun Oct 26 22:32:42 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/i386/preserve-none-17.c	Sun Nov  2 22:33:20 2025
***************
*** 1,10 ****
  /* { dg-do compile } */
  /* { dg-options "-O2" } */
  
! extern void foo (void) __attribute__ ((preserve_none)); /* { dg-note "previous declaration" } */
  
  void
! foo (void) /* { dg-error "conflicting types" } */
  {
  }
- 
--- 1,9 ----
  /* { dg-do compile } */
  /* { dg-options "-O2" } */
  
! extern void foo (void) __attribute__ ((preserve_none));
  
  void
! foo (void)
  {
  }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/compare-both-non-zero.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-do compile { target { loongarch64*-*-* } } } */
+ /* { dg-options "-O3" } */
+ 
+ int
+ test (int a, int b)
+ {
+   return a && b;
+ }
+ 
+ /* { dg-final { scan-assembler "maskeqz" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c	Sun Oct 26 22:32:42 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c	Sun Nov  2 22:33:20 2025
*************** void
*** 27,33 ****
  test_lt ()
  {
    if (lm < ln)
!     lr *= (1 << 16);
    lr += lm;
  }
  
--- 27,33 ----
  test_lt ()
  {
    if (lm < ln)
!     lr += (1 << 16);
    lr += lm;
  }
  
*************** void
*** 35,41 ****
  test_le ()
  {
    if (lm <= ln)
!     lr = lm * ((long)1 << 32);
    else
      lr = lm;
    lr += lm;
--- 35,41 ----
  test_le ()
  {
    if (lm <= ln)
!     lr = lm + ((long)1 << 32);
    else
      lr = lm;
    lr += lm;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c	Sun Oct 26 22:32:42 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c	Sun Nov  2 22:33:20 2025
*************** void
*** 29,35 ****
  test_lez ()
  {
    if (lm <= 0)
!     lr &= (1 << 16);
    lr += lm;
  }
  
--- 29,35 ----
  test_lez ()
  {
    if (lm <= 0)
!     lr |= (1 << 16);
    lr += lm;
  }
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2" } */
+ /* { dg-final { scan-assembler "maskeqz" } } */
+ /* { dg-final { scan-assembler "masknez" } } */
+ 
+ extern long lm, ln, lr;
+ 
+ void
+ test_and ()
+ {
+   if (lm < 0)
+     lr &= (1 << 16);
+   lr += lm;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/fnmam4-vec.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-Ofast -mlasx -ftree-vectorize" } */
+ /* { dg-require-effective-target loongarch_asx } */
+ 
+ void
+ foo (float *u, float x, float *y, float z)
+ {
+   int i;
+   for (i = 0; i < 1024; i++)
+     *(u++) = (x - y[i] * z);
+ }
+ 
+ /* { dg-final { scan-assembler-not "\tvori.b"} } */
+ /* { dg-final { scan-assembler-not "\txvori.b"} } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/pr122097.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/pr122097.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/pr122097.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/pr122097.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,271 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O3 -mabi=lp64d -mlsx" } */
+ /* { dg-final { scan-assembler "vbitseti\.d\t\\\$vr\[0-9\]+,\\\$vr\[0-9\]+,63" } } */
+ 
+ typedef long unsigned int size_t;
+ typedef unsigned char simde__mmask8;
+ typedef long simde__m128i __attribute__ ((__aligned__ ((16))))
+ __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__));
+ typedef union
+ {
+ 
+   __attribute__ ((__aligned__ ((16)))) long i64
+       __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__));
+ } simde__m128i_private;
+ typedef double simde_float64;
+ typedef simde_float64 simde__m128d __attribute__ ((__aligned__ ((16))))
+ __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__));
+ typedef long int int_fast32_t;
+ typedef union
+ {
+ 
+   __attribute__ ((__aligned__ ((16)))) int_fast32_t i32f
+       __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__));
+   __attribute__ ((__aligned__ ((16)))) long i64
+       __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__));
+   __attribute__ ((__aligned__ ((16)))) simde_float64 f64
+       __attribute__ ((__vector_size__ (16))) __attribute__ ((__may_alias__));
+ } simde__m128d_private;
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde__m128d_from_private (simde__m128d_private v)
+ {
+   simde__m128d r;
+   __builtin_memcpy (&r, &v, sizeof (r));
+   return r;
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_set_pd (simde_float64 e1, simde_float64 e0)
+ {
+ 
+   simde__m128d_private r_;
+   r_.f64[0] = e0;
+   r_.f64[1] = e1;
+ 
+   return simde__m128d_from_private (r_);
+ }
+ __attribute__ ((__always_inline__)) inline static simde__m128i
+ simde_mm_castpd_si128 (simde__m128d a)
+ {
+   simde__m128i r;
+   __builtin_memcpy (&r, &a, sizeof (a));
+   return r;
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128i
+ simde__m128i_from_private (simde__m128i_private v)
+ {
+   simde__m128i r;
+   __builtin_memcpy (&r, &v, sizeof (r));
+   return r;
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128i_private
+ simde__m128i_to_private (simde__m128i v)
+ {
+   simde__m128i_private r;
+   __builtin_memcpy (&r, &v, sizeof (r));
+   return r;
+ }
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_castsi128_pd (simde__m128i a)
+ {
+   simde__m128d r;
+   __builtin_memcpy (&r, &a, sizeof (a));
+   return r;
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128i
+ simde_mm_mask_mov_epi64 (simde__m128i src, simde__mmask8 k, simde__m128i a)
+ {
+ 
+   simde__m128i_private src_ = simde__m128i_to_private (src),
+                        a_ = simde__m128i_to_private (a), r_;
+ 
+   for (size_t i = 0; i < (sizeof (r_.i64) / sizeof (r_.i64[0])); i++)
+     {
+       r_.i64[i] = ((k >> i) & 1) ? a_.i64[i] : src_.i64[i];
+     }
+ 
+   return simde__m128i_from_private (r_);
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_mask_mov_pd (simde__m128d src, simde__mmask8 k, simde__m128d a)
+ {
+   return simde_mm_castsi128_pd (simde_mm_mask_mov_epi64 (
+       simde_mm_castpd_si128 (src), k, simde_mm_castpd_si128 (a)));
+ }
+ 
+ static double
+ simde_test_f64_precision_to_slop (int precision)
+ {
+   return __builtin_expect (!!(precision == 0x7fffffff), 0)
+              ? 0.0
+              : __builtin_pow (10.0, -((double)(precision)));
+ }
+ __attribute__ ((__always_inline__)) inline static void
+ simde_mm_storeu_pd (simde_float64 *mem_addr, simde__m128d a)
+ {
+ 
+   __builtin_memcpy (mem_addr, &a, sizeof (a));
+ }
+ int simde_test_equal_f64 (simde_float64 a, simde_float64 b,
+                           simde_float64 slop);
+ void simde_test_debug_printf_ (const char *format, ...);
+ static int
+ simde_assert_equal_vf64_ (size_t vec_len, simde_float64 const a[(vec_len)],
+                           simde_float64 const b[(vec_len)], simde_float64 slop,
+                           const char *filename, int line, const char *astr,
+                           const char *bstr)
+ {
+   for (size_t i = 0; i < vec_len; i++)
+     {
+       if (__builtin_expect (!!(!simde_test_equal_f64 (a[i], b[i], slop)), 0))
+         {
+           simde_test_debug_printf_ (
+               "%s:%d: assertion failed: %s[%zu] ~= %s[%zu] (%f ~= %f)\n",
+               filename, line, astr, i, bstr, i, ((double)(a[i])),
+               ((double)(b[i])));
+           return 1;
+         }
+     }
+   return 0;
+ }
+ static int
+ simde_test_x86_assert_equal_f64x2_ (simde__m128d a, simde__m128d b,
+                                     simde_float64 slop, const char *filename,
+                                     int line, const char *astr,
+                                     const char *bstr)
+ {
+   simde_float64 a_[sizeof (a) / sizeof (simde_float64)],
+       b_[sizeof (a) / sizeof (simde_float64)];
+   simde_mm_storeu_pd (a_, a);
+   simde_mm_storeu_pd (b_, b);
+   return simde_assert_equal_vf64_ (sizeof (a_) / sizeof (a_[0]), a_, b_, slop,
+                                    filename, line, astr, bstr);
+ }
+ __attribute__ ((__always_inline__)) inline static simde__m128d_private
+ simde__m128d_to_private (simde__m128d v)
+ {
+   simde__m128d_private r;
+   __builtin_memcpy (&r, &v, sizeof (r));
+   return r;
+ }
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_min_pd (simde__m128d a, simde__m128d b)
+ {
+ 
+   simde__m128d_private r_, a_ = simde__m128d_to_private (a),
+                            b_ = simde__m128d_to_private (b);
+ 
+   for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++)
+     {
+       r_.f64[i] = (a_.f64[i] < b_.f64[i]) ? a_.f64[i] : b_.f64[i];
+     }
+ 
+   return simde__m128d_from_private (r_);
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_max_pd (simde__m128d a, simde__m128d b)
+ {
+ 
+   simde__m128d_private r_, a_ = simde__m128d_to_private (a),
+                            b_ = simde__m128d_to_private (b);
+ 
+   for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++)
+     {
+       r_.f64[i] = (a_.f64[i] > b_.f64[i]) ? a_.f64[i] : b_.f64[i];
+     }
+ 
+   return simde__m128d_from_private (r_);
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_x_mm_abs_pd (simde__m128d a)
+ {
+ 
+   simde__m128d_private r_, a_ = simde__m128d_to_private (a);
+   for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++)
+     {
+       r_.f64[i] = __builtin_fabs (a_.f64[i]);
+     }
+ 
+   return simde__m128d_from_private (r_);
+ }
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_cmple_pd (simde__m128d a, simde__m128d b)
+ {
+ 
+   simde__m128d_private r_, a_ = simde__m128d_to_private (a),
+                            b_ = simde__m128d_to_private (b);
+ 
+   r_.i64 = ((__typeof__ (r_.i64))((a_.f64 <= b_.f64)));
+   return simde__m128d_from_private (r_);
+ }
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_x_mm_select_pd (simde__m128d a, simde__m128d b, simde__m128d mask)
+ {
+   simde__m128d_private r_, a_ = simde__m128d_to_private (a),
+                            b_ = simde__m128d_to_private (b),
+                            mask_ = simde__m128d_to_private (mask);
+ 
+   r_.i64 = a_.i64 ^ ((a_.i64 ^ b_.i64) & mask_.i64);
+   return simde__m128d_from_private (r_);
+ }
+ simde__m128d simde_mm_cmpge_pd (simde__m128d a, simde__m128d b);
+ 
+ simde__m128d
+ simde_x_mm_copysign_pd (simde__m128d dest, simde__m128d src)
+ {
+   simde__m128d_private r_, dest_ = simde__m128d_to_private (dest),
+                            src_ = simde__m128d_to_private (src);
+   for (size_t i = 0; i < (sizeof (r_.f64) / sizeof (r_.f64[0])); i++)
+     {
+       r_.f64[i] = __builtin_copysign (dest_.f64[i], src_.f64[i]);
+     }
+ 
+   return simde__m128d_from_private (r_);
+ }
+ simde__m128d simde_mm_or_pd (simde__m128d a, simde__m128d b);
+ 
+ simde__m128d simde_mm_set1_pd (simde_float64 a);
+ 
+ __attribute__ ((__always_inline__)) inline static simde__m128d
+ simde_mm_range_pd (simde__m128d a, simde__m128d b, int imm8)
+ {
+   simde__m128d r;
+ 
+   r = simde_x_mm_select_pd (
+       b, a, simde_mm_cmple_pd (simde_x_mm_abs_pd (a), simde_x_mm_abs_pd (b)));
+ 
+   r = simde_x_mm_copysign_pd (r, a);
+ 
+   return r;
+ }
+ int
+ test_simde_mm_mask_range_pd (void)
+ {
+ 
+   simde__m128d src, a, b, e, r;
+ 
+   src = simde_mm_set_pd (-2.92, -85.39);
+   a = simde_mm_set_pd (-47.59, -122.31);
+   b = simde_mm_set_pd (877.42, 69.15);
+   e = simde_mm_set_pd (-47.59, -69.15);
+   r = simde_mm_mask_mov_pd (src, 143, simde_mm_range_pd (a, b, 2));
+   do
+     {
+       if (simde_test_x86_assert_equal_f64x2_ (
+               r, e, simde_test_f64_precision_to_slop (1),
+               "../test/x86/avx512/range.c", 1454, "r", "e"))
+         {
+           return 1;
+         }
+     }
+   while (0);
+ 
+   return 0;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/sign_extend_ashift.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile { target { loongarch64*-*-* } } } */
+ /* { dg-options "-O3" } */
+ /* { dg-final { scan-assembler "slli\\.w" } } */
+ /* { dg-final { scan-assembler-not "slli\\.d" } } */
+ /* { dg-final { scan-assembler-not "ext\\.w\\.b" } } */
+ 
+ unsigned int
+ test (unsigned int id)
+ {
+   return id << 24;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/trap-1.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/trap-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/trap-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/trap-1.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,9 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -w -fisolate-erroneous-paths-dereference -mbreak-code=1" } */
+ /* { dg-final { scan-assembler "break\\t1" } } */
+ 
+ int
+ bug (void)
+ {
+   return *(int *)0;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/trap-default.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/trap-default.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/trap-default.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/trap-default.c	Sun Nov  2 22:33:20 2025
***************
*** 0 ****
--- 1,9 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -w -fisolate-erroneous-paths-dereference" } */
+ /* { dg-final { scan-assembler "amswap\\.w\\t\\\$r0,\\\$r1,\\\$r0" } } */
+ 
+ int
+ bug (void)
+ {
+   return *(int *)0;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-signed.c	Sun Nov  2 22:33:21 2025
***************
*** 0 ****
--- 1,13 ----
+ /* Verify optimization for mulw.d.w,
+    which can help with the replacement of the high-latency div.w.  */
+ /* { dg-do compile { target { loongarch64*-*-* } } } */
+ /* { dg-options "-O3" } */
+ 
+ int
+ test (int a)
+ {
+   return a / 3;
+ }
+ 
+ /* { dg-final { scan-assembler {\tmulw.d.w\t} } } */
+ /* { dg-final { scan-assembler-not {\tdiv.w\t} } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/loongarch/widen-mul-rtx-cost-unsigned.c	Sun Nov  2 22:33:21 2025
***************
*** 0 ****
--- 1,11 ----
+ /* Verify optimization for mulh.wu, which can reduce insns.  */
+ /* { dg-do compile } */
+ /* { dg-options "-O3" } */
+ 
+ int
+ test (unsigned int a)
+ {
+   return a / 3;
+ }
+ 
+ /* { dg-final { scan-assembler {\tmulh.wu\t} } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/pr120553-2.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/pr120553-2.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/pr120553-2.c	Sun Oct 26 22:32:43 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/pr120553-2.c	Sun Nov  2 22:34:08 2025
*************** T1(63)
*** 83,90 ****
  #endif
  
  /* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */
! /* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 128 { target rv64 } } } */
  
  /* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */
! /* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 64 { target rv32 } } } */
  
--- 83,90 ----
  #endif
  
  /* { dg-final { scan-assembler-times "\\t(srai)" 128 { target rv64 } } } */
! /* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 196 { target rv64 } } } */
  
  /* { dg-final { scan-assembler-times "\\t(srai)" 64 { target rv32 } } } */
! /* { dg-final { scan-assembler-times "\\t(orn|ori|bset)" 66 { target rv32 } } } */
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/pr64345.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/pr64345.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/pr64345.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/pr64345.c	Sun Nov  2 22:34:08 2025
***************
*** 0 ****
--- 1,30 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -march=rv64gcbv_zicond -mabi=lp64d" { target rv64 } } */
+ /* { dg-options "-O2 -march=rv32gcbv_zicond -mabi=ilp32" { target rv32 } } */
+ 
+ 
+ 
+ unsigned int test0 (unsigned int x) { return ((x >> 4) ^ 1) & 1; }
+ 
+ unsigned int test1 (unsigned int x) { return ((x >> 4) & 1) ^ 1; }
+ 
+ unsigned int test2 (unsigned int x) { return ~(x >> 4) & 1; }
+ 
+ unsigned int test3 (unsigned int x) { return ((~x >> 4) & 1); }
+ 
+ unsigned int test4 (unsigned int x) { return (x >> 4) & 1; }
+ 
+ int test5 (int vi) { return vi - (((vi >> 6) & 0x01) << 1); }
+ 
+ int test6 (int vi) { return vi - (((vi >> 6) & 0x01) << 1) - 1; }
+ 
+ 
+ /* { dg-final { scan-assembler-times "\\tbexti" 5 } } */
+ /* { dg-final { scan-assembler-times "\\txori" 3 } } */
+ /* { dg-final { scan-assembler-times "\\tnot" 1 } } */
+ /* { dg-final { scan-assembler-times "\\tsrli" 2 } } */
+ /* { dg-final { scan-assembler-times "\\tandi" 2 } } */
+ /* { dg-final { scan-assembler-times "\\tsub" 2 } } */
+ /* { dg-final { scan-assembler-times "\\taddi" 1 } } */
+ 
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/pr67731.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/pr67731.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/pr67731.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/pr67731.c	Sun Nov  2 22:34:08 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -march=rv64gcbv -mabi=lp64d" { target { rv64 } } } */
+ /* { dg-options "-O2 -march=rv32gcbv -mabi=ilp32" { target { rv32 } } } */
+ 
+ typedef struct
+ {
+   _Bool a : 1;
+   _Bool b : 1;
+   _Bool c : 1;
+   _Bool d : 1;
+   unsigned int e : 4;
+ } S;
+ 
+ _Bool test_00 (S* s)
+ {
+   return s->b | s->c;
+ }
+ 
+ _Bool test_01 (S* s)
+ {
+   return s->b | s->c | s->d;
+ }
+ /* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 } } */
+ /* { dg-final { scan-assembler-not {\tor} } } */
+ /* { dg-final { scan-assembler-not {\tbexti} } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c	Sun Nov  2 22:34:09 2025
***************
*** 0 ****
--- 1,150 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv -mabi=lp64d -w -O0" { target rv64 } } */
+ /* { dg-options "-march=rv32gcv -mabi=ilp32 -w -O0" { target rv32 } } */
+ 
+ 
+ typedef int a;
+ typedef signed char b;
+ typedef char c;
+ typedef short d;
+ typedef unsigned short e;
+ typedef a f;
+ typedef unsigned g;
+ typedef long h;
+ h j, k, l, m, n, o;
+ int p, q, r, s;
+ short t;
+ volatile a u;
+ a v[];
+ char w, x;
+ a *y, *z;
+ a **aa;
+ __attribute__((always_inline)) b __attribute__((vector_size(16)))
+ ab(f __attribute__((vector_size(8 * sizeof(f)))), d ac,
+    d __attribute__((vector_size(2 * sizeof(d)))), d) {
+   return __builtin_shufflevector(
+       (b __attribute__((vector_size(16)))) __builtin_convertvector(
+           (d __attribute__((vector_size(16 *sizeof(d))))){
+               ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac},
+           c __attribute__((vector_size(16)))) |
+           __builtin_convertvector(
+               (d __attribute__((vector_size(16 *sizeof(d))))){
+                   ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac},
+               c __attribute__((vector_size(16)))),
+       __builtin_convertvector(
+           (d __attribute__((vector_size(16 *sizeof(d))))){
+               ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac},
+           b __attribute__((vector_size(16)))),
+       3, 21, 0, 2, 2, 7, 1, 8, 4, 0, 8, 0, 8, 9, 5, 6);
+ }
+ __attribute__((always_inline)) g
+ ad(d ae, h __attribute__((vector_size(32 * sizeof(h))))) {
+   g f = 6318;
+   return (8 ? ae / 786856318u : 0) & ae;
+ }
+ a(af)(a, int);
+ void(ag)(long);
+ char(ah)(char, char);
+ char(ai)(char);
+ short(aj)(short, short);
+ int ak(long, int *, int *, char, int);
+ void al(signed, a *, int *, long);
+ char am(int *, short, short);
+ void an(int *, long, int);
+ void ao(int, int *, a *);
+ a ap() {
+   int *aq, *ar, *as;
+   short at;
+   char au, av, aw = 2;
+   long ax, ay, az = j;
+   int ba, i;
+   g __attribute__((vector_size(16 * sizeof(g)))) bb = {80};
+   b __attribute__((vector_size(4))) bc = {6};
+   int bd[1];
+   char *be = &w;
+   int bf, bg = q;
+   a **bh[] = {
+       &y, &z, &z, &y, &y, &y, &y, &y, &z, &z, &y, &z, &y, &y, &y, &y, &z, &y,
+       &z, &y, &y, &y, &z, &z, &z, &y, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y,
+       &z, &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z, &z, &y, &y, 0,  &z, 0,
+       &z, 0,  &y, &z, &z, 0,  &z, 0,  &z, &z, &z, &y, &z, &z, &y, &z, &z, &y,
+       0,  &z, 0,  &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z, &z, &y, &y, 0,
+       &z, 0,  &z, 0,  &y, &z, &z, 0,  &z, 0,  &z, &z, &z, &y, &z, &z, &y, &z,
+       &z, &y, 0,  &z, 0,  &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z, &z, &y,
+       &y, 0,  &z, 0,  &z, 0,  &y, &z, &z, 0,  &z, 0,  &z, &z, &z, &y, &z, &z,
+       &y, &z, &z, &y, 0,  &z, 0,  &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z,
+       &z, &y, &y, 0,  &z, 0,  &z, 0,  &y, &z, &z, 0,  0,  &z, 0,  &z, &z, &z,
+       &y, &z, &z, &y, &z, &z, &y, 0,  &z, 0,  0,  &z, &z};
+   for (; i; i++)
+     bd[i] = p;
+   h __attribute__((vector_size(32 * sizeof(h))))
+   bi = {2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681,
+         2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681,
+         2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681},
+   bj = __builtin_convertvector(
+       (c __attribute__((vector_size(32)))){
+           aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw,
+           aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw},
+       h __attribute__((vector_size(32 * sizeof(h))))),
+   bk = __builtin_convertvector(
+       __builtin_shufflevector(bb, bb, 4, 8, 7, 9, 1, 10, 4, 7, 0, 4, 3, 5, 6, 7,
+                               6, 2, 2, 20, 6, 4, 7, 7, 9, 7, 4, 9, 8, 6, 1, 0,
+                               6, 9),
+       h __attribute__((vector_size(32 * sizeof(h)))));
+   bb = __builtin_convertvector(
+       ab(__builtin_shufflevector(
+              __builtin_shufflevector(
+                  __builtin_convertvector(
+                      __builtin_shufflevector(bb, bb, 1, 31, 8, 2, 3, 7, 4, 0, 7,
+                                              3, 4, 6, 7, 1, 9, 3, 8, 7, 1, 8, 5,
+                                              3, 9, 9, 0, 3, 2, 8, 5, 2, 5, 3),
+                      f __attribute__((vector_size(32 * sizeof(f))))),
+                  (f __attribute__((vector_size(32 * sizeof(f))))){
+                      800761418310502961587690471176286910032020044212442466872080013589354162852207417903424527024812447907811618435019152886919380169872910001752451018659493155196043018716516518746289614523948734758456011127254301274351182132760058399143431214610613191313926994549901191890929084305862034120561651877003645},
+                  32, 44),
+              (f __attribute__((vector_size(2 * sizeof(f))))){o}, 1, 0, 3, 0, 2,
+              1, 3, 3),
+          ad(__builtin_clzg((g)aw, (f)bb[9]),
+             (h __attribute__((vector_size(32 * sizeof(h))))){
+                 bi[0] ?: bk[0],    bi[1] ? 1 : bk[1],  bi[2] ? 2 : bk[2],
+                 bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4],  bi[5] ? 5 : bk[5],
+                 bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7],  bi[8] ? 8 : bk[8],
+                 bi[9] ? 9 : bk[9], bi[0] ? 10 : bk[0], bi[1] ? 1 : bk[1],
+                 bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3],  bi[4] ? 4 : bk[4],
+                 bi[5] ? 5 : bk[5], bi[6] ? 6 : bk[6],  bi[7] ? 7 : bk[7],
+                 bi[8] ? 8 : bk[8], bi[9] ? 9 : bk[9],  bi[0] ? 20 : bk[0],
+                 bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2],  bi[3] ? 3 : bk[3],
+                 bi[4] ? bj[4] : 4, bi[5] ?: 5,         bi[6] ?: 6,
+                 bi[7] ? 0 : 7,     bi[8] ?: 8,         bi[9] ? 0 : 9,
+                 bi[0] ? 0 : 30,    bi[1] ?: 1}),
+          (d __attribute__((vector_size(2 * sizeof(d)))))
+                  __builtin_shufflevector(
+                      __builtin_convertvector(
+                          __builtin_shufflevector(bb, bb, 2, 7, 21, 6),
+                          e __attribute__((vector_size(4 * sizeof(e))))),
+                      __builtin_convertvector(
+                          (c __attribute__((vector_size(4)))){aw, aw},
+                          e __attribute__((vector_size(4 * sizeof(e))))),
+                      5, 1) +
+              (__builtin_convertvector(
+                   __builtin_shufflevector(bb, bb, 4, 5),
+                   e __attribute__((vector_size(2 * sizeof(e))))) <=
+               __builtin_convertvector(
+                   (c __attribute__((vector_size(2)))){aw},
+                   e __attribute__((vector_size(2 * sizeof(e)))))),
+          n ? bb[5] << n : aw),
+       g __attribute__((vector_size(16 * sizeof(g)))));
+   ag(aw & t);
+   at = aj(aw, v[1]);
+   au = ah(at, aw);
+   ba = af((1 == ax != aw) <= aw <= au, aw);
+   ao(0, &bd[0], &r);
+   o = ay;
+   an(aq, aw, k);
+   av = am(ar, l, k);
+   *be = ai(*be);
+   al(x, as, &bd[0], aw);
+   bg = ak(u, &s, &bf, aw, aw);
+   as = *aa;
+   return m;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122445.c	Sun Nov  2 22:34:09 2025
***************
*** 0 ****
--- 1,26 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcbv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl --param=riscv-autovec-mode=V4QI -mtune=generic-ooo -fdump-rtl-avlprop-all" } */
+ 
+ typedef unsigned char uint8_t;
+ typedef short int16_t;
+ 
+ #define FDEC_STRIDE 32
+ 
+ static inline uint8_t x264_clip_uint8( int x )
+ {
+   return x;
+ }
+ 
+ void
+ x264_add4x4_idct (uint8_t *p_dst, int16_t d[16])
+ {
+   for( int y = 0; y < 4; y++ )
+     {
+       for( int x = 0; x < 4; x++ )
+         p_dst[x] = x264_clip_uint8( p_dst[x] + d[y*4+x] );
+       p_dst += FDEC_STRIDE;
+     }
+ }
+ 
+ /* { dg-final { scan-rtl-dump "Propagating AVL: \\(const_int 4" "avlprop" } } */
+ /* { dg-final { scan-rtl-dump-not "Propagating AVL: \\(const_int 1" "avlprop" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c	Sun Nov  2 22:34:13 2025
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-options "" } */
+ /* { dg-do compile } */
+ /* { dg-add-options riscv_v } */
+ /* PR target/122270 */
+ 
+ #include "riscv_vector.h"
+ 
+ void a(vfloat32m1_t b, vfloat32m1x4_t *c) {
+   *c = __riscv_vset_v_f32m1_f32m1x4(*c, 3, b);
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,39 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 8 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,39 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 8 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 128
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,39 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 8 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,39 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 8 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 256
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 32
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,39 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 8 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,39 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+ // Check vector argument 9 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+ // Check argument 10 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+ // Check argument 11 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+ // Check argument 12 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+ // Check argument 13 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+ // Check argument 14 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+ // Check argument 15 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+ // Check argument 16 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 8 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 512
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,29 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_128bit_vector.h"
+ // Function under test:
+ //	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_256bit_vector.h"
+ // Function under test:
+ //	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_32bit_vector.h"
+ // Function under test:
+ //	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_64bit_vector.h"
+ // Function under test:
+ //	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_all_mixed.h"
+ // Function under test:
+ //	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_call_mixed_function.h"
+ // Function under test:
+ //	int helper_mixed_function(int i, int32x4_t v, float f)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_different_vector_elements.h"
+ // Function under test:
+ //	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+ //	                                   int32x4_t int_vec, int64x2_t long_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_different_vectors_struct.h"
+ // Function under test:
+ //	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_different_width_vectors_struct.h"
+ // Function under test:
+ //	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_equivalent_struct.h"
+ // Function under test:
+ //	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_four_registers.h"
+ // Function under test:
+ //	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_fp_vs_int_vectors.h"
+ // Function under test:
+ //	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+ //	                             double64x2_t double_vec)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_large_vector_small_abi_vlen.h"
+ // Function under test:
+ //	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_args.h"
+ // Function under test:
+ //	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_float_vector.h"
+ // Function under test:
+ //	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_int_vector.h"
+ // Function under test:
+ //	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_struct.h"
+ // Function under test:
+ //	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_struct_advanced.h"
+ // Function under test:
+ //	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_mixed_vector_types_struct.h"
+ // Function under test:
+ //	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_multiple_unions.h"
+ // Function under test:
+ //	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_multiple_vectors.h"
+ // Function under test:
+ //	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_multiple_with_small_abi_vlen.h"
+ // Function under test:
+ //	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+ //	                                            int32x4_t v3, int32x4_t v4)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,29 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_register_exhaustion.h"
+ // Function under test:
+ //	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+ //	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+ //	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+ //	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+ //	     int32x4_t v17)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_register_exhaustion_mixed.h"
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+ // Check argument 6 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+ // Check argument 7 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+ // Check vector argument 8 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_register_pressure_scenarios.h"
+ // Function under test:
+ //	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+ //	                                      int32x4_t medium1, int32x4_t medium2,
+ //	                                      int32x8_t large1)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+ // Check vector argument 2 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+ // Check argument 3 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+ // Check argument 4 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */
+ // Check argument 5 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_same_vectors_struct.h"
+ // Function under test:
+ //	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_simple_union.h"
+ // Function under test:
+ //	union_vector_t test_simple_union(union_vector_t u)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+ // Check return value passed via integer registers using subreg
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_single_register.h"
+ // Function under test:
+ //	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_single_vector_struct.h"
+ // Function under test:
+ //	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_different_abi_vlen.h"
+ // Function under test:
+ //	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_eight_128bit_vectors.h"
+ // Function under test:
+ //	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_five_256bit_vectors.h"
+ // Function under test:
+ //	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_four_256bit_vectors.h"
+ // Function under test:
+ //	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_struct_nine_128bit_vectors.h"
+ // Function under test:
+ //	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_two_registers.h"
+ // Function under test:
+ //	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+ // Check vector argument 1 passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ // Check argument 2 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
+ // Check return value passed in vector register
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ #define ABI_VLEN 64
+ 
+ #include "../common/test_vector_array_struct.h"
+ // Function under test:
+ //	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+ // Check argument 1 register assignment
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+ // Check return value passed via pointer (result_ptr)
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ // Test: Two 128-bit vectors behavior under different ABI_VLEN
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x4_t VLS_CC(ABI_VLEN) test_128bit_vector(int32x4_t vec1, int32x4_t vec2) {
+     // Two 128-bit vectors:
+     // - ABI_VLEN=128: each uses 1 vector register (2 total)
+     // - ABI_VLEN=64:  each uses 2 vector registers (4 total)
+     // - ABI_VLEN=32:  each uses 4 vector registers (8 total)
+     int32x4_t result;
+     result = vec1 + vec2;
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ // Test: Two 256-bit vectors behavior under different ABI_VLEN
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x8_t VLS_CC(ABI_VLEN) test_256bit_vector(int32x8_t vec1, int32x8_t vec2) {
+     // Two 256-bit vectors:
+     // - ABI_VLEN=256: each uses 1 vector register (2 total)
+     // - ABI_VLEN=128: each uses 2 vector registers (4 total)
+     // - ABI_VLEN=64:  each uses 4 vector registers (8 total)
+     // - ABI_VLEN=32:  each uses 8 vector registers (16 total)
+     int32x8_t result;
+     result = vec1 + vec2;
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ // Test: Two 32-bit vectors (very small vectors)
+ 
+ #include "../vls-cc-common.h"
+ 
+ int16x2_t VLS_CC(ABI_VLEN) test_32bit_vector(int16x2_t vec1, int16x2_t vec2) {
+     // Two 32-bit vectors:
+     // - Each always uses 1 vector register regardless of ABI_VLEN
+     // - Uses even smaller portion when ABI_VLEN > 32
+     int16x2_t result;
+     result[0] = vec1[0] + vec2[0];
+     result[1] = vec1[1] + vec2[1];
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ // Test: Two 64-bit vectors (always fit in one register each)
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x2_t VLS_CC(ABI_VLEN) test_64bit_vector(int32x2_t vec1, int32x2_t vec2) {
+     // Two 64-bit vectors:
+     // - Each always uses 1 vector register regardless of ABI_VLEN
+     // - Only uses portion of the register when ABI_VLEN > 64
+     int32x2_t result;
+     result[0] = vec1[0] + vec2[0];
+     result[1] = vec1[1] + vec2[1];
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ // Test: All three types mixed (int, float, vector)
+ 
+ #include "../vls-cc-common.h"
+ 
+ double VLS_CC(ABI_VLEN) test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) {
+     // int i -> a0 (integer register)
+     // float f -> fa0 (FP register)  
+     // int32x4_t vec1 -> v8 (vector register)
+     // double d -> fa1 (FP register)
+     // float32x4_t vec2 -> v9 (vector register)
+     // int j -> a1 (integer register)
+     return i + f + vec1[0] + d + vec2[0] + j;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ // Test: Function pointers with mixed signatures
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef int (*mixed_func_ptr_t)(int, int32x4_t, float) VLS_CC(ABI_VLEN);
+ 
+ // Helper function to be called via function pointer
+ int VLS_CC(ABI_VLEN) helper_mixed_function(int i, int32x4_t v, float f) {
+     return i + v[0] + (int)f;
+ }
+ 
+ int VLS_CC(ABI_VLEN) test_call_mixed_function(mixed_func_ptr_t func, int i, int32x4_t v, float f) {
+     return func(i, v, f);
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,10 ----
+ // Test: Vector types with different element types in same call
+ 
+ #include "../vls-cc-common.h"
+ 
+ int VLS_CC(ABI_VLEN) test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, 
+                                   int32x4_t int_vec, int64x2_t long_vec) {
+     // All are 128-bit vectors but with different element types
+     // Should all use same vector register allocation rules
+     return byte_vec[0] + short_vec[0] + int_vec[0] + (int)long_vec[0];
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,9 ----
+ // Test: Struct with different sized vectors - uses hardware FP calling convention
+ 
+ #include "../vls-cc-common.h"
+ 
+ struct_different_vectors_t VLS_CC(ABI_VLEN) test_different_vectors_struct(struct_different_vectors_t s) {
+     // Contains int32x2_t (64 bits) and int32x4_t (128 bits) - different lengths
+     // Should use hardware floating-point calling convention, not vector registers
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,27 ----
+ // Test: Struct with two vectors of different widths but same total size
+ // int32x4_t (128 bits, 4 x 32-bit) and int16x8_t (128 bits, 8 x 16-bit) - both should be flattened
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x4_t wide_vec;   // 128-bit vector with 4 x 32-bit elements
+     int16x8_t narrow_vec; // 128-bit vector with 8 x 16-bit elements
+ } different_width_vectors_struct_t;
+ 
+ different_width_vectors_struct_t VLS_CC(ABI_VLEN) test_different_width_vectors_struct(different_width_vectors_struct_t s) {
+     // Should be flattened and passed as two separate vector arguments
+     // wide_vec should use first vector register, narrow_vec should use second vector register
+     different_width_vectors_struct_t result;
+     
+     // Process wide vector: add 100 to each 32-bit element
+     for (int i = 0; i < 4; i++) {
+         result.wide_vec[i] = s.wide_vec[i] + 100;
+     }
+     
+     // Process narrow vector: add 10 to each 16-bit element
+     for (int i = 0; i < 8; i++) {
+         result.narrow_vec[i] = s.narrow_vec[i] + 10;
+     }
+     
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ // Test: Compare struct vs union behavior
+ 
+ #include "../vls-cc-common.h"
+ 
+ // Struct equivalent to union (should use vector calling convention)
+ typedef struct {
+     int32x4_t vec;
+ } equivalent_struct_t;
+ 
+ equivalent_struct_t VLS_CC(ABI_VLEN) test_equivalent_struct(equivalent_struct_t s) {
+     // This struct should use vector calling convention (flattened)
+     // Compare behavior with the union version
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ // Test: Two vectors passed in eight registers (<= 4 * ABI_VLEN bits each)
+ // int32x16_t (512 bits) should use 4 registers each when ABI_VLEN = 128
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x16_t VLS_CC(ABI_VLEN) test_four_registers(int32x16_t vec1, int32x16_t vec2) {
+     // Add vectors element-wise
+     int32x16_t result;
+     result = vec1 + vec2;
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,10 ----
+ // Test: Floating-point vectors vs integer vectors
+ 
+ #include "../vls-cc-common.h"
+ 
+ float VLS_CC(ABI_VLEN) test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, 
+                             double64x2_t double_vec) {
+     // All vectors should use vector registers, regardless of element type
+     // Element type shouldn't affect register allocation for fixed-length vectors
+     return int_vec[0] + float_vec[0] + (float)double_vec[0];
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,13 ----
+ // Test: Two large vectors that might be passed by reference with small ABI_VLEN
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x16_t VLS_CC(ABI_VLEN) test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) {
+     // Two 512-bit vectors:
+     // - ABI_VLEN=128: each uses 4 registers (8 total, fits in available registers)
+     // - ABI_VLEN=64:  each needs 8 registers (16 total, exceeds available, passed by reference)
+     // - ABI_VLEN=32:  each needs 16 registers (32 total, far exceeds available, passed by reference)
+     int32x16_t result;
+     result = vec1 + vec2;
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,8 ----
+ // Test: Mixed scalar and vector arguments
+ 
+ #include "../vls-cc-common.h"
+ 
+ int VLS_CC(ABI_VLEN) test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) {
+     // scalars use integer/float registers, vectors use vector registers
+     return scalar1 + (int)scalar2 + vec1[0] + vec2[0];
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,10 ----
+ // Test: Mixed floating-point scalars and vectors
+ 
+ #include "../vls-cc-common.h"
+ 
+ float VLS_CC(ABI_VLEN) test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) {
+     // Float scalars should use FP registers (fa0, fa1, ...)
+     // Vectors should use vector registers (v8, v9, ...)
+     // Different register classes should not interfere
+     return f1 + (float)d1 + vec[0] + vec2[0];
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,10 ----
+ // Test: Mixed integer scalars and vectors
+ 
+ #include "../vls-cc-common.h"
+ 
+ int VLS_CC(ABI_VLEN) test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) {
+     // Scalars should use integer registers (a0, a1, a2, ...)
+     // Vectors should use vector registers (v8, v9, ...)  
+     // Should not interfere with each other's register allocation
+     return a + b + vec[0] + vec2[0];
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,8 ----
+ // Test: Struct with mixed vector and scalar - uses hardware FP calling convention
+ 
+ #include "../vls-cc-common.h"
+ 
+ struct_mixed_t VLS_CC(ABI_VLEN) test_mixed_struct(struct_mixed_t s) {
+     // Contains vector and scalar - should use hardware FP calling convention
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ // Test: Vector and scalar struct members (advanced mixed struct)
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int scalar;
+     int32x4_t vector;
+     float fp_scalar;
+ } mixed_struct_advanced_t;
+ 
+ mixed_struct_advanced_t VLS_CC(ABI_VLEN) test_mixed_struct_advanced(mixed_struct_advanced_t s) {
+     // Should use hardware FP calling convention due to mixed types
+     // Vector part will be treated according to standard struct rules
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,23 ----
+ // Test: Struct with two vectors of same width but different types
+ // int32x4_t (128 bits) and float32x4_t (128 bits) - both should be flattened
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x4_t int_vec;    // 128-bit integer vector
+     float32x4_t float_vec; // 128-bit float vector
+ } mixed_vector_types_struct_t;
+ 
+ mixed_vector_types_struct_t VLS_CC(ABI_VLEN) test_mixed_vector_types_struct(mixed_vector_types_struct_t s) {
+     // Should be flattened and passed as two separate vector arguments
+     // int_vec should use first vector register, float_vec should use second vector register
+     mixed_vector_types_struct_t result;
+     
+     // Combine the vectors: add 10 to int elements, multiply float elements by 2.0
+     for (int i = 0; i < 4; i++) {
+         result.int_vec[i] = s.int_vec[i] + 10;
+         result.float_vec[i] = s.float_vec[i] * 2.0f;
+     }
+     
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ // Test: Multiple union arguments
+ 
+ #include "../vls-cc-common.h"
+ 
+ union_vector_t VLS_CC(ABI_VLEN) test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) {
+     // All should use integer calling convention
+     // Should consume integer registers, not vector registers
+     union_vector_t result;
+     result.scalars[0] = u1.scalars[0] + u2.scalars[0] + u3.scalars[0];
+     result.scalars[1] = u1.scalars[1] + u2.scalars[1] + u3.scalars[1];
+     result.scalars[2] = u1.scalars[2] + u2.scalars[2] + u3.scalars[2];
+     result.scalars[3] = u1.scalars[3] + u2.scalars[3] + u3.scalars[3];
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,12 ----
+ // Test: Multiple vector arguments consuming available registers
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x4_t VLS_CC(ABI_VLEN) test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) {
+     // Each vector uses 1 register, total 3 registers
+     int32x4_t result = {v1[0] + v2[0] + v3[0], 
+                         v1[1] + v2[1] + v3[1],
+                         v1[2] + v2[2] + v3[2], 
+                         v1[3] + v2[3] + v3[3]};
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,12 ----
+ // Test: Multiple vectors that may exceed register count with small ABI_VLEN
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x4_t VLS_CC(ABI_VLEN) test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, 
+                                            int32x4_t v3, int32x4_t v4) {
+     // With ABI_VLEN=32, each 128-bit vector needs 4 registers
+     // 4 vectors  *  4 registers = 16 registers needed
+     // Will exceed available vector registers, some passed by reference
+     int32x4_t result = {v1[0] + v2[0], v1[1] + v3[1], v1[2] + v4[2], v1[3] + v2[3]};
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ // Test: Vector register exhaustion - should fall back to reference passing
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x4_t VLS_CC(ABI_VLEN) test_register_exhaustion(
+     int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+     int32x4_t v17) {
+     // First 16 vectors (v1-v16) should use vector registers v8-v23
+     // 17th vector (v17) should be passed by reference due to register exhaustion
+     int32x4_t result = {v1[0] + v17[0], v2[1] + v17[1], v3[2] + v17[2], v4[3] + v17[3]};
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,21 ----
+ // Test: Large number of mixed arguments to test register exhaustion
+ 
+ #include "../vls-cc-common.h"
+ 
+ int VLS_CC(ABI_VLEN) test_register_exhaustion_mixed(
+     // Integer arguments (use a0-a7)
+     int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9,
+     // FP arguments (use fa0-fa7) 
+     float f1, float f2, float f3, float f4, float f5, float f6, float f7, float f8, float f9,
+     // Vector arguments (use v8-v23, 16 registers available)
+     int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+     int32x4_t v17
+ ) {
+     // i9, f9 should be passed via stack due to integer/FP register exhaustion
+     // v1-v16 should use vector registers v8-v23
+     // v17 should be passed via stack/memory due to vector register exhaustion
+     return i1 + i9 + (int)f1 + (int)f9 + v1[0] + v17[0];
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,15 ----
+ // Test: Function demonstrating register pressure with different ABI_VLEN
+ 
+ #include "../vls-cc-common.h"
+ 
+ void VLS_CC(ABI_VLEN) test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+                                      int32x4_t medium1, int32x4_t medium2,
+                                      int32x8_t large1) {
+     // Different register consumption based on ABI_VLEN:
+     // ABI_VLEN=128: 2 * 1 + 2 * 1 + 1 * 2 = 6 registers
+     // ABI_VLEN=64:  2 * 1 + 2 * 2 + 1 * 4 = 10 registers (exceeds 8, some by reference)
+     // ABI_VLEN=32:  2 * 2 + 2 * 4 + 1 * 8 = 20 registers (many by reference)
+     
+     // Just use the parameters to avoid warnings
+     (void)small1; (void)small2; (void)medium1; (void)medium2; (void)large1;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,10 ----
+ // Test: Struct with two same-length vectors - should be passed as vector tuple
+ 
+ #include "../vls-cc-common.h"
+ 
+ struct_two_same_vectors_t VLS_CC(ABI_VLEN) test_same_vectors_struct(struct_two_same_vectors_t s) {
+     // Should be passed in vector registers like a vector tuple
+     // Both vectors are int32x4_t (128 bits each), total 256 bits
+     // Should use 2 vector registers when ABI_VLEN = 128
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,9 ----
+ // Test: Simple union with vector - should use integer calling convention
+ 
+ #include "../vls-cc-common.h"
+ 
+ union_vector_t VLS_CC(ABI_VLEN) test_simple_union(union_vector_t u) {
+     // Union with fixed-length vector should always use integer calling convention
+     // Should NOT use vector registers, even though it contains a vector
+     return u;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,11 ----
+ // Test: Two vectors passed in registers (<= ABI_VLEN bits each)
+ // int32x4_t (128 bits) should use 1 register per vector when ABI_VLEN >= 128
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x4_t VLS_CC(ABI_VLEN) test_single_register(int32x4_t vec1, int32x4_t vec2) {
+     // Add vectors element-wise
+     int32x4_t result;
+     result = vec1 + vec2;
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,8 ----
+ // Test: Struct with single vector - should be flattened
+ 
+ #include "../vls-cc-common.h"
+ 
+ struct_single_vector_t VLS_CC(ABI_VLEN) test_single_vector_struct(struct_single_vector_t s) {
+     // Should be flattened and passed as single vector argument
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,17 ----
+ // Test: Struct behavior under different ABI_VLEN
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x4_t vec1;
+     int32x4_t vec2;
+ } two_medium_vectors_t;
+ 
+ two_medium_vectors_t VLS_CC(ABI_VLEN) test_struct_different_abi_vlen(two_medium_vectors_t s) {
+     // Struct with 2 * 128-bit vectors (256 bits total):
+     // - ABI_VLEN=256: fits in single "vector tuple" concept, uses 2 registers
+     // - ABI_VLEN=128: each vector uses 1 register, total 2 registers  
+     // - ABI_VLEN=64:  each vector uses 2 registers, total 4 registers
+     // - ABI_VLEN=32:  each vector uses 4 registers, total 8 registers
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,38 ----
+ // Test: Struct with eight 128-bit vectors
+ // Each int32x4_t is 128 bits (4 x 32-bit elements)
+ // Total: 8 vectors * 128 bits = 1024 bits
+ // With ABI_VLEN=128: 8 vectors * 1 register each = 8 registers (fits in 16 available)
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x4_t vec1;  // 128-bit vector
+     int32x4_t vec2;  // 128-bit vector
+     int32x4_t vec3;  // 128-bit vector
+     int32x4_t vec4;  // 128-bit vector
+     int32x4_t vec5;  // 128-bit vector
+     int32x4_t vec6;  // 128-bit vector
+     int32x4_t vec7;  // 128-bit vector
+     int32x4_t vec8;  // 128-bit vector
+ } eight_128bit_vectors_struct_t;
+ 
+ eight_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) {
+     // Should be flattened and passed as separate vector arguments
+     // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec8 uses v15
+     // Total uses 8 out of 16 available vector argument registers
+     eight_128bit_vectors_struct_t result;
+     
+     // Process each 128-bit vector: multiply by (index + 1)
+     for (int i = 0; i < 4; i++) {
+         result.vec1[i] = s.vec1[i] * 1;
+         result.vec2[i] = s.vec2[i] * 2;
+         result.vec3[i] = s.vec3[i] * 3;
+         result.vec4[i] = s.vec4[i] * 4;
+         result.vec5[i] = s.vec5[i] * 5;
+         result.vec6[i] = s.vec6[i] * 6;
+         result.vec7[i] = s.vec7[i] * 7;
+         result.vec8[i] = s.vec8[i] * 8;
+     }
+     
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,33 ----
+ // Test: Struct with five 256-bit vectors
+ // Each int32x8_t is 256 bits (8 x 32-bit elements)
+ // Total: 5 vectors * 256 bits = 1280 bits
+ // With ABI_VLEN=128: 5 vectors * 2 registers each = 10 registers (fits in 16 available)
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x8_t vec1;  // 256-bit vector
+     int32x8_t vec2;  // 256-bit vector
+     int32x8_t vec3;  // 256-bit vector
+     int32x8_t vec4;  // 256-bit vector
+     int32x8_t vec5;  // 256-bit vector
+ } five_256bit_vectors_struct_t;
+ 
+ five_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) {
+     // Should be flattened and passed as separate vector arguments
+     // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, 
+     //                    vec4 uses v14+v15, vec5 uses v16+v17
+     // Total uses 10 out of 16 available vector argument registers
+     five_256bit_vectors_struct_t result;
+     
+     // Process each 256-bit vector: add different values to each vector
+     for (int i = 0; i < 8; i++) {
+         result.vec1[i] = s.vec1[i] + 1000;
+         result.vec2[i] = s.vec2[i] + 2000;
+         result.vec3[i] = s.vec3[i] + 3000;
+         result.vec4[i] = s.vec4[i] + 4000;
+         result.vec5[i] = s.vec5[i] + 5000;
+     }
+     
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,30 ----
+ // Test: Struct with four 256-bit vectors
+ // Each int32x8_t is 256 bits (8 x 32-bit elements)
+ // Total: 4 vectors * 256 bits = 1024 bits
+ // With ABI_VLEN=128: 4 vectors * 2 registers each = 8 registers (fits in 16 available)
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x8_t vec1;  // 256-bit vector
+     int32x8_t vec2;  // 256-bit vector
+     int32x8_t vec3;  // 256-bit vector
+     int32x8_t vec4;  // 256-bit vector
+ } four_256bit_vectors_struct_t;
+ 
+ four_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) {
+     // Should be flattened and passed as separate vector arguments
+     // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, vec4 uses v14+v15
+     // With ABI_VLEN=256: vec1 uses v8, vec2 uses v9, vec3 uses v10, vec4 uses v11
+     four_256bit_vectors_struct_t result;
+     
+     // Process each 256-bit vector: add 100 to first element, add 200 to second element, etc.
+     for (int i = 0; i < 8; i++) {
+         result.vec1[i] = s.vec1[i] + 100;
+         result.vec2[i] = s.vec2[i] + 200;
+         result.vec3[i] = s.vec3[i] + 300;
+         result.vec4[i] = s.vec4[i] + 400;
+     }
+     
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,40 ----
+ // Test: Struct with nine 128-bit vectors
+ // Each int32x4_t is 128 bits (4 x 32-bit elements)
+ // Total: 9 vectors * 128 bits = 1152 bits
+ // With ABI_VLEN=128: 9 vectors * 1 register each = 9 registers (fits in 16 available)
+ 
+ #include "../vls-cc-common.h"
+ 
+ typedef struct {
+     int32x4_t vec1;  // 128-bit vector
+     int32x4_t vec2;  // 128-bit vector
+     int32x4_t vec3;  // 128-bit vector
+     int32x4_t vec4;  // 128-bit vector
+     int32x4_t vec5;  // 128-bit vector
+     int32x4_t vec6;  // 128-bit vector
+     int32x4_t vec7;  // 128-bit vector
+     int32x4_t vec8;  // 128-bit vector
+     int32x4_t vec9;  // 128-bit vector
+ } nine_128bit_vectors_struct_t;
+ 
+ nine_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) {
+     // Should be flattened and passed as separate vector arguments
+     // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec9 uses v16
+     // Total uses 9 out of 16 available vector argument registers
+     nine_128bit_vectors_struct_t result;
+     
+     // Process each 128-bit vector: add vector index * 100 to each element
+     for (int i = 0; i < 4; i++) {
+         result.vec1[i] = s.vec1[i] + 100;
+         result.vec2[i] = s.vec2[i] + 200;
+         result.vec3[i] = s.vec3[i] + 300;
+         result.vec4[i] = s.vec4[i] + 400;
+         result.vec5[i] = s.vec5[i] + 500;
+         result.vec6[i] = s.vec6[i] + 600;
+         result.vec7[i] = s.vec7[i] + 700;
+         result.vec8[i] = s.vec8[i] + 800;
+         result.vec9[i] = s.vec9[i] + 900;
+     }
+     
+     return result;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,8 ----
+ // Test: Vector passed in two registers (<= 2 * ABI_VLEN bits)
+ // int32x8_t (256 bits) should use 2 registers when ABI_VLEN = 128
+ 
+ #include "../vls-cc-common.h"
+ 
+ int32x8_t VLS_CC(ABI_VLEN) test_two_registers(int32x8_t vec, int32x8_t vec2) {
+     return vec + vec2;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,9 ----
+ // Test: Struct with vector array - should be passed as vector tuple
+ 
+ #include "../vls-cc-common.h"
+ 
+ struct_vector_array_t VLS_CC(ABI_VLEN) test_vector_array_struct(struct_vector_array_t s) {
+     // Array of 2 int32x4_t vectors, should be passed as vector tuple
+     // Total size: 256 bits, should use 2 vector registers
+     return s;
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,63 ----
+ # Copyright (C) 2025 Free Software Foundation, Inc.
+ 
+ # This program is free software; you can redistribute it and/or modify
+ # it under the terms of the GNU General Public License as published by
+ # the Free Software Foundation; either version 3 of the License, or
+ # (at your option) any later version.
+ #
+ # This program is distributed in the hope that it will be useful,
+ # but WITHOUT ANY WARRANTY; without even the implied warranty of
+ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ # GNU General Public License for more details.
+ #
+ # You should have received a copy of the GNU General Public License
+ # along with GCC; see the file COPYING3.  If not see
+ # <http://www.gnu.org/licenses/>.
+ 
+ # GCC testsuite that uses the `dg.exp' driver.
+ 
+ # Exit immediately if this isn't a RISC-V target.
+ if ![istarget riscv*-*-*] then {
+   return
+ }
+ 
+ # Load support procs.
+ load_lib gcc-dg.exp
+ 
+ # If a testcase doesn't have special options, use these.
+ global DEFAULT_CFLAGS
+ if ![info exists DEFAULT_CFLAGS] then {
+     set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+ }
+ 
+ # Initialize `dg'.
+ dg-init
+ 
+ # Main loop.
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+ 	"" $DEFAULT_CFLAGS
+ 
+ # Test for specific XLEN and VLEN.
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-32/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-64/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-32/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-64/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-32/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-64/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-32/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-64/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-32/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-64/*.\[cS\]]] \
+         "" $DEFAULT_CFLAGS
+ 
+ # All done.
+ dg-finish
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Large vector with ABI_VLEN=128
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x8_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_large_vector(int32x8_t vec) {
+     // 256-bit vector with ABI_VLEN=128 -> uses 2 registers
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Medium vector with ABI_VLEN=128
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x4_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_medium_vector(int32x4_t vec) {
+     // 128-bit vector with ABI_VLEN=128 -> uses 1 register  
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Large vector with ABI_VLEN=256
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x8_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_large_vector(int32x8_t vec) {
+     // 256-bit vector with ABI_VLEN=256 -> uses 1 register
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Very large vector with ABI_VLEN=256
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x16_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_very_large_vector(int32x16_t vec) {
+     // 512-bit vector with ABI_VLEN=256 -> uses 2 registers
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ v8\)[[:space:]]+\(reg.*:V16SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Medium vector with ABI_VLEN=32
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x4_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_medium_vector(int32x4_t vec) {
+     // 128-bit vector with ABI_VLEN=32 -> uses 4 registers
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Small vector with ABI_VLEN=32
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x2_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_small_vector(int32x2_t vec) {
+     // 64-bit vector with ABI_VLEN=32 -> uses 2 registers
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Medium vector with ABI_VLEN=64
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x4_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_medium_vector(int32x4_t vec) {
+     // 128-bit vector with ABI_VLEN=64 -> uses 2 registers
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+ /* { dg-skip-if "" { *-*-* } { "-O0" } } */
+ 
+ // Test: Small vector with ABI_VLEN=64
+ 
+ #include "vls-cc-common.h"
+ 
+ int32x2_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_small_vector(int32x2_t vec) {
+     // 64-bit vector with ABI_VLEN=64 -> uses 1 register
+     return vec;
+ }
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+ /* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,125 ----
+ #ifndef VLS_CC_COMMON_H
+ #define VLS_CC_COMMON_H
+ 
+ #include <stdint-gcc.h>
+ 
+ // Check if ABI_VLEN is defined
+ #ifndef ABI_VLEN
+ #define ABI_VLEN 128  // Default fallback value
+ #endif
+ 
+ // VLS Calling Convention attribute macro
+ #define VLS_CC(ABI_VLEN) \
+   __attribute__((riscv_vls_cc(ABI_VLEN)))
+ 
+ // Fixed-length vector type definitions following <basetype><width>x<num>_t naming convention
+ // These use GCC/Clang __attribute__((vector_size(N))) extension
+ 
+ // 8-bit integer vectors
+ typedef int8_t int8x2_t __attribute__((vector_size(2)));
+ typedef int8_t int8x4_t __attribute__((vector_size(4)));
+ typedef int8_t int8x8_t __attribute__((vector_size(8)));
+ typedef int8_t int8x16_t __attribute__((vector_size(16)));
+ typedef int8_t int8x32_t __attribute__((vector_size(32)));
+ typedef int8_t int8x64_t __attribute__((vector_size(64)));
+ 
+ typedef uint8_t uint8x2_t __attribute__((vector_size(2)));
+ typedef uint8_t uint8x4_t __attribute__((vector_size(4)));
+ typedef uint8_t uint8x8_t __attribute__((vector_size(8)));
+ typedef uint8_t uint8x16_t __attribute__((vector_size(16)));
+ typedef uint8_t uint8x32_t __attribute__((vector_size(32)));
+ typedef uint8_t uint8x64_t __attribute__((vector_size(64)));
+ 
+ // 16-bit integer vectors
+ typedef int16_t int16x2_t __attribute__((vector_size(4)));
+ typedef int16_t int16x4_t __attribute__((vector_size(8)));
+ typedef int16_t int16x8_t __attribute__((vector_size(16)));
+ typedef int16_t int16x16_t __attribute__((vector_size(32)));
+ typedef int16_t int16x32_t __attribute__((vector_size(64)));
+ 
+ typedef uint16_t uint16x2_t __attribute__((vector_size(4)));
+ typedef uint16_t uint16x4_t __attribute__((vector_size(8)));
+ typedef uint16_t uint16x8_t __attribute__((vector_size(16)));
+ typedef uint16_t uint16x16_t __attribute__((vector_size(32)));
+ typedef uint16_t uint16x32_t __attribute__((vector_size(64)));
+ 
+ // 32-bit integer vectors
+ typedef int32_t int32x2_t __attribute__((vector_size(8)));
+ typedef int32_t int32x4_t __attribute__((vector_size(16)));
+ typedef int32_t int32x8_t __attribute__((vector_size(32)));
+ typedef int32_t int32x16_t __attribute__((vector_size(64)));
+ 
+ typedef uint32_t uint32x2_t __attribute__((vector_size(8)));
+ typedef uint32_t uint32x4_t __attribute__((vector_size(16)));
+ typedef uint32_t uint32x8_t __attribute__((vector_size(32)));
+ typedef uint32_t uint32x16_t __attribute__((vector_size(64)));
+ 
+ // 64-bit integer vectors
+ typedef int64_t int64x2_t __attribute__((vector_size(16)));
+ typedef int64_t int64x4_t __attribute__((vector_size(32)));
+ typedef int64_t int64x8_t __attribute__((vector_size(64)));
+ 
+ typedef uint64_t uint64x2_t __attribute__((vector_size(16)));
+ typedef uint64_t uint64x4_t __attribute__((vector_size(32)));
+ typedef uint64_t uint64x8_t __attribute__((vector_size(64)));
+ 
+ // Floating-point vectors (following the same pattern)
+ typedef float float32x2_t __attribute__((vector_size(8)));
+ typedef float float32x4_t __attribute__((vector_size(16)));
+ typedef float float32x8_t __attribute__((vector_size(32)));
+ typedef float float32x16_t __attribute__((vector_size(64)));
+ 
+ typedef double double64x2_t __attribute__((vector_size(16)));
+ typedef double double64x4_t __attribute__((vector_size(32)));
+ typedef double double64x8_t __attribute__((vector_size(64)));
+ 
+ // Test structures containing fixed-length vectors
+ typedef struct {
+     int32x4_t vec1;
+     int32x4_t vec2;
+ } struct_two_same_vectors_t;
+ 
+ typedef struct {
+     int32x4_t vec;
+ } struct_single_vector_t;
+ 
+ typedef struct {
+     int32x4_t vec_array[2];
+ } struct_vector_array_t;
+ 
+ typedef struct {
+     int32x2_t vec1;
+     int32x4_t vec2;  // Different sizes
+ } struct_different_vectors_t;
+ 
+ typedef struct {
+     int32x4_t vec;
+     int scalar;
+ } struct_mixed_t;
+ 
+ // Union containing fixed-length vectors (always uses integer calling convention)
+ typedef union {
+     int32x4_t vec;
+     int32_t scalars[4];
+ } union_vector_t;
+ 
+ // Function pointer types for testing
+ typedef int32x4_t (*func_return_vector_t)(int32x4_t);
+ typedef void (*func_pass_vector_t)(int32x4_t);
+ typedef struct_single_vector_t (*func_return_struct_t)(struct_single_vector_t);
+ 
+ // Test constants for initialization
+ #define INIT_INT32X4(a, b, c, d) (int32x4_t){a, b, c, d}
+ #define INIT_FLOAT32X4(a, b, c, d) (float32x4_t){a, b, c, d}
+ #define INIT_INT16X8(a, b, c, d, e, f, g, h) (int16x8_t){a, b, c, d, e, f, g, h}
+ 
+ #ifdef SUPPORT_NON_POWER_OF_2_VEC
+ #define INIT_INT32X3(a, b, c) (int32x3_t){a, b, c}
+ #define INIT_FLOAT32X3(a, b, c) (float32x3_t){a, b, c}
+ #endif
+ 
+ // Utility macros for vector operations testing
+ #define VEC_SIZE_BYTES(type) sizeof(type)
+ #define VEC_ELEMENT_COUNT(type, element_type) (sizeof(type) / sizeof(element_type))
+ 
+ #endif // VLS_CC_COMMON_H
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c	Sun Oct 26 22:32:44 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-01.c	Sun Nov  2 22:34:14 2025
***************
*** 1,6 ****
  /* { dg-do compile } */
  /* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
! /* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
  
  int foo1(int rs1)
  {
--- 1,6 ----
  /* { dg-do compile } */
  /* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
! /* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-O1" "-Oz" "-Os" } } */
  
  int foo1(int rs1)
  {
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c gcc-16-20251102/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c	Sun Oct 26 22:32:44 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-02.c	Sun Nov  2 22:34:14 2025
***************
*** 1,6 ****
  /* { dg-do compile } */
  /* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
! /* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
  
  int foo1(int rs1)
  {
--- 1,6 ----
  /* { dg-do compile } */
  /* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
! /* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-O1" "-Oz" "-Os" } } */
  
  int foo1(int rs1)
  {
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sh/pr67731.c gcc-16-20251102/gcc/testsuite/gcc.target/sh/pr67731.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sh/pr67731.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gcc.target/sh/pr67731.c	Sun Nov  2 22:34:14 2025
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -m4 -ml" } */
+ 
+ typedef struct
+ {
+   _Bool a : 1;
+   _Bool b : 1;
+   _Bool c : 1;
+   _Bool d : 1;
+   unsigned int e : 4;
+ } S;
+ 
+ _Bool test_00 (S* s)
+ {
+   return s->b | s->c;
+ }
+ 
+ _Bool test_01 (S* s)
+ {
+   return s->b | s->c | s->d;
+ }
+ 
+ /* { dg-final { scan-assembler-times {\ttst} 2 } } */
+ /* { dg-final { scan-assembler-times {\tnegc} 2 } } */
+ /* { dg-final { scan-assembler-not {\tor} } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sparc/cbcond-1.c gcc-16-20251102/gcc/testsuite/gcc.target/sparc/cbcond-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sparc/cbcond-1.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/sparc/cbcond-1.c	Sun Nov  2 22:34:14 2025
*************** void cbcondle (int a)
*** 34,38 ****
  
  /* { dg-final { scan-assembler "cwbe\t%"  { target ilp32 } } } */
  /* { dg-final { scan-assembler "cwbne\t%" { target ilp32 } } } */
! /* { dg-final { scan-assembler "cwbl\t%"  } } */
! /* { dg-final { scan-assembler "cwble\t%" } } */
--- 34,38 ----
  
  /* { dg-final { scan-assembler "cwbe\t%"  { target ilp32 } } } */
  /* { dg-final { scan-assembler "cwbne\t%" { target ilp32 } } } */
! /* { dg-final { scan-assembler "cwbl|cwbge\t%"  } } */
! /* { dg-final { scan-assembler "cwble|cwbg\t%" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sparc/cbcond-2.c gcc-16-20251102/gcc/testsuite/gcc.target/sparc/cbcond-2.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sparc/cbcond-2.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/sparc/cbcond-2.c	Sun Nov  2 22:34:14 2025
*************** void cbcondle (long a)
*** 35,39 ****
  
  /* { dg-final { scan-assembler "cxbe\t%"  } } */
  /* { dg-final { scan-assembler "cxbne\t%" } } */
! /* { dg-final { scan-assembler "cxbl\t%"  } } */
! /* { dg-final { scan-assembler "cxble\t%" } } */
--- 35,39 ----
  
  /* { dg-final { scan-assembler "cxbe\t%"  } } */
  /* { dg-final { scan-assembler "cxbne\t%" } } */
! /* { dg-final { scan-assembler "cxbl|cxbge\t%"  } } */
! /* { dg-final { scan-assembler "cxble|cxbg\t%" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sparc/overflow-3.c gcc-16-20251102/gcc/testsuite/gcc.target/sparc/overflow-3.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sparc/overflow-3.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/sparc/overflow-3.c	Sun Nov  2 22:34:14 2025
*************** bool my_neg_overflow (int32_t a, int32_t
*** 38,43 ****
  /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
  /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
  /* { dg-final { scan-assembler-times "addx\t%" 3 } } */
! /* { dg-final { scan-assembler-times "bvs" 3 } } */
  /* { dg-final { scan-assembler-not "cmp\t%" } } */
  /* { dg-final { scan-assembler-not "save\t%" } } */
--- 38,43 ----
  /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
  /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
  /* { dg-final { scan-assembler-times "addx\t%" 3 } } */
! /* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */
  /* { dg-final { scan-assembler-not "cmp\t%" } } */
  /* { dg-final { scan-assembler-not "save\t%" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sparc/overflow-4.c gcc-16-20251102/gcc/testsuite/gcc.target/sparc/overflow-4.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sparc/overflow-4.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/sparc/overflow-4.c	Sun Nov  2 22:34:14 2025
*************** bool my_neg_overflow (int64_t a, int64_t
*** 38,44 ****
  /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
  /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
  /* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
! /* { dg-final { scan-assembler-times "blu" 2 } } */
! /* { dg-final { scan-assembler-times "bvs" 3 } } */
  /* { dg-final { scan-assembler-not "cmp\t%" } } */
  /* { dg-final { scan-assembler-not "save\t%" } } */
--- 38,44 ----
  /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
  /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
  /* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
! /* { dg-final { scan-assembler-times "blu|bgeu" 2 } } */
! /* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */
  /* { dg-final { scan-assembler-not "cmp\t%" } } */
  /* { dg-final { scan-assembler-not "save\t%" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sparc/overflow-5.c gcc-16-20251102/gcc/testsuite/gcc.target/sparc/overflow-5.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sparc/overflow-5.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/sparc/overflow-5.c	Sun Nov  2 22:34:14 2025
*************** bool my_neg_overflow (int64_t a, int64_t
*** 38,43 ****
  /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
  /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
  /* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
! /* { dg-final { scan-assembler-times "bvs" 3 } } */
  /* { dg-final { scan-assembler-not "cmp\t%" } } */
  /* { dg-final { scan-assembler-not "save\t%" } } */
--- 38,43 ----
  /* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
  /* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
  /* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
! /* { dg-final { scan-assembler-times "bvs|bvc" 3 } } */
  /* { dg-final { scan-assembler-not "cmp\t%" } } */
  /* { dg-final { scan-assembler-not "save\t%" } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/sparc/small-struct-1.c gcc-16-20251102/gcc/testsuite/gcc.target/sparc/small-struct-1.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/sparc/small-struct-1.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/sparc/small-struct-1.c	Sun Nov  2 22:34:14 2025
*************** double get2x (struct vec2x v)
*** 42,46 ****
    return v.x + v.y;
  }
  
! /* { dg-final { scan-assembler-not "ldx" } } */
! /* { dg-final { scan-assembler-not "stx" } } */
--- 42,46 ----
    return v.x + v.y;
  }
  
! /* { dg-final { scan-assembler-not "ldx" { target *-*-solaris* } } } */
! /* { dg-final { scan-assembler-not "stx" { target *-*-solaris* } } } */
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c gcc-16-20251102/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c
*** gcc-16-20251026/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c	Sun Oct 26 22:32:45 2025
--- gcc-16-20251102/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c	Thu Jan  1 00:00:00 1970
***************
*** 1,9 ****
- /* { dg-do compile } */
- /* { dg-options "-O1" } */
- 
- int one_cmpl_abs(int a)
- {
-   return a < 0 ? ~a : a;
- }
- 
- /* { dg-final { scan-assembler-not "bgez" } } */
--- 0 ----
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/coarray_atomic_5.f90 gcc-16-20251102/gcc/testsuite/gfortran.dg/coarray_atomic_5.f90
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/coarray_atomic_5.f90	Sun Oct 26 22:32:46 2025
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/coarray_atomic_5.f90	Sun Nov  2 22:34:16 2025
*************** program atomic
*** 19,25 ****
    write(*,*) me
  end program
  
! ! { dg-final { scan-tree-dump-times "value.. = 0;" 1 "original" } }
! ! { dg-final { scan-tree-dump-times "_gfortran_caf_atomic_define \\(caf_token.., 0, 1, &value.., 0B, 1, 4\\);" 1 "original" } }
  ! { dg-final { scan-tree-dump-times "_gfortran_caf_atomic_op \\(1, caf_token.., 0, 1, &me, 0B, 0B, 1, 4\\);" 1 "original" } }
  ! { dg-final { scan-tree-dump-times "_gfortran_caf_atomic_ref \\(caf_token.., 0, 1, &me, 0B, 1, 4\\);" 1 "original" } }
--- 19,25 ----
    write(*,*) me
  end program
  
! ! { dg-final { scan-tree-dump-times "D\\.\[0-9\]+ = 0;" 1 "original" } }
! ! { dg-final { scan-tree-dump-times "_gfortran_caf_atomic_define \\(caf_token.., 0, 1, &D\\.\[0-9\]+, 0B, 1, 4\\);" 1 "original" } }
  ! { dg-final { scan-tree-dump-times "_gfortran_caf_atomic_op \\(1, caf_token.., 0, 1, &me, 0B, 0B, 1, 4\\);" 1 "original" } }
  ! { dg-final { scan-tree-dump-times "_gfortran_caf_atomic_ref \\(caf_token.., 0, 1, &me, 0B, 1, 4\\);" 1 "original" } }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_61.f03 gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_61.f03
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_61.f03	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_61.f03	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,35 ----
+ ! { dg-do run }
+ !
+ ! Test the fix for PR95541, in which parameterized array and string components
+ ! of PDT arrays caused an ICE in the ASSOCIATE selector expressions below.
+ !
+ ! Contributed by Gerhard Steinmetz  <gscfq@t-online.de>
+ !
+ program p
+    type t(n)
+       integer, len :: n
+       integer :: a(n)
+       character(len = n) :: chr
+    end type
+    type(t(3)) :: x(2)
+    integer :: tgt(2)
+    x(1)%a = [1, 2, 3]
+    x(1)%chr = "abc"
+    x(2)%a = [4, 5, 6]
+    x(2)%chr = "def"
+    associate (y => x(:)%a(3))
+       if (any (y /= [3,6]))          stop 1
+       y = -y
+    end associate
+    associate (y => x%a(3))
+       if (any (y /= [-3,-6]))        stop 2
+       y = -y * 10
+    end associate
+    if (any (x%a(3) /= [30,60]))      stop 3
+    if (any (x%a(2) /= [2,5]))        stop 4
+    associate (y => x%chr(2:2))
+       if (any (y /= ["b","e"]))      stop 5
+       y = ["x", "y"]
+    end associate
+    if (any (x%chr /= ["axc","dyf"])) stop 6
+ end
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_62.f03 gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_62.f03
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_62.f03	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_62.f03	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,78 ----
+ ! { dg-do run }
+ !
+ ! Test fix for PR122433
+ !
+ ! Contributed by Damian Rouson  <damian@archaeologic.codes>
+ !
+ module neuron_m
+   implicit none
+ 
+   type string_t
+     character(len=:), allocatable :: string_
+   end type
+ 
+   type neuron_t(k)
+     integer, kind :: k = kind(1.)
+     real(k) bias_
+     type(neuron_t(k)), allocatable :: next
+   end type
+ 
+ contains
+   recursive function from_json(neuron_lines, start) result(neuron)
+     type(string_t) neuron_lines(:)
+     integer start
+     type(neuron_t) neuron
+     character(len=:), allocatable :: line
+     line = neuron_lines(start+1)%string_
+     read(line(index(line, ":")+1:), fmt=*) neuron%bias_
+     line = adjustr(neuron_lines(start+3)%string_)
+ ! Used to give "Error: Syntax error in IF-clause" for next line.
+     if (line(len(line):) == ",") neuron%next = from_json(neuron_lines, start+4)
+   end function
+   recursive function from_json_8(neuron_lines, start) result(neuron)
+     type(string_t) neuron_lines(:)
+     integer start
+     type(neuron_t(kind(1d0))) neuron
+     character(len=:), allocatable :: line
+     line = neuron_lines(start+1)%string_
+     read(line(index(line, ":")+1:), fmt=*) neuron%bias_
+     line = adjustr(neuron_lines(start+3)%string_)
+     if (line(len(line):) == ",") neuron%next = from_json_8(neuron_lines, start+4)
+   end function
+ end module
+ 
+   use neuron_m
+   call foo
+   call bar
+ contains
+   subroutine foo
+     type(neuron_t) neuron
+     type(string_t) :: neuron_lines(8)
+     neuron_lines(2)%string_ = "real : 4.0 "
+     neuron_lines(4)%string_ = " ,"
+     neuron_lines(6)%string_ = "real : 8.0 "
+     neuron_lines(8)%string_ = " "
+     neuron = from_json(neuron_lines, 1)
+     if (int (neuron%bias_) /= 4) stop 1
+     if (allocated (neuron%next)) then
+       if (int (neuron%next%bias_) /= 8) stop 2
+     else
+       stop 3
+     endif
+   end subroutine
+   subroutine bar
+     type(neuron_t(kind(1d0))) neuron
+     type(string_t) :: neuron_lines(8)
+     neuron_lines(2)%string_ = "real : 4.0d0 "
+     neuron_lines(4)%string_ = " ,"
+     neuron_lines(6)%string_ = "real : 8.0d0 "
+     neuron_lines(8)%string_ = " "
+     neuron = from_json_8(neuron_lines, 1)
+     if (int (neuron%bias_) /= 4) stop 1
+     if (allocated (neuron%next)) then
+       if (int (neuron%next%bias_) /= 8) stop 2
+     else
+       stop 3
+     endif
+   end subroutine
+ end
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_63.f03 gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_63.f03
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_63.f03	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_63.f03	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,26 ----
+ ! { dg-do compile }
+ !
+ ! Test fix for PR122434
+ !
+ ! Contributed by Damian Rouson  <damian@archaeologic.codes>
+ !
+ module neuron_m
+   implicit none
+ 
+   type neuron_t
+     real, allocatable :: weight_
+   end type
+ 
+   interface
+     type(neuron_t) pure module function from_json() result(neuron)
+     end function
+   end interface
+ 
+ contains
+   module procedure from_json
+     associate(num_inputs => 1)
+ ! Gave "Error: Bad allocate-object at (1) for a PURE procedure" in next line.
+       allocate(neuron%weight_, source=0.)
+     end associate
+   end procedure
+ end module
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_64.f03 gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_64.f03
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_64.f03	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_64.f03	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,17 ----
+ ! { dg-do compile }
+ !
+ ! Test the fix for PR122165.
+ !
+ ! Contributed by Steve Kargl  <kargls@comcast.net>
+ !
+ program foo
+    implicit none
+    type dt(k,l)
+       integer(8), len :: k = 1
+       integer(8), KIND :: l = 1
+       character(k) :: arr
+    end type
+    type(dt(:)), allocatable  :: d1
+    if (d1%k%kind /= 8) stop 1 ! { dg-error "cannot be followed by the type inquiry ref" }
+    if (d1%l%kind /= 8) stop 2 ! { dg-error "cannot be followed by the type inquiry ref" }
+ end
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_65.f03 gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_65.f03
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/pdt_65.f03	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/pdt_65.f03	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,135 ----
+ ! { dg-do compile }
+ ! { dg-options "-fdump-tree-original" }
+ !
+ ! Test fix for PR122452
+ !
+ ! Contributed by Damian Rouson  <damian@archaeologic.codes>
+ !
+ module kind_parameters_m
+   integer, parameter :: default_real = kind(1e0)
+   integer, parameter :: double_precision = kind(1d0)
+ end module
+ 
+ module tensor_m
+   use kind_parameters_m, only : default_real, double_precision
+   implicit none
+ 
+   private
+   public :: tensor_t
+ 
+   type tensor_t(k)
+     integer, kind :: k = default_real 
+     real(k), allocatable, private :: values_(:)
+   contains
+     generic   :: values => default_real_values, double_precision_values
+     procedure, private, non_overridable ::  default_real_values, double_precision_values
+     generic :: num_components => default_real_num_components, double_precision_num_components
+     procedure, private ::        default_real_num_components, double_precision_num_components
+   end type
+ 
+   interface tensor_t
+ 
+     pure module function construct_default_real(values) result(tensor)
+       implicit none
+       real, intent(in) :: values(:)
+       type(tensor_t) tensor
+     end function
+ 
+     pure module function construct_double_precision(values) result(tensor)
+       implicit none
+       double precision, intent(in) :: values(:)
+       type(tensor_t(double_precision)) tensor
+     end function
+ 
+   end interface
+ 
+   interface
+ 
+     pure module function default_real_values(self) result(tensor_values)
+       implicit none
+       class(tensor_t), intent(in) :: self
+       real, allocatable :: tensor_values(:)
+     end function
+ 
+     pure module function double_precision_values(self) result(tensor_values)
+       implicit none
+       class(tensor_t(double_precision)), intent(in) :: self
+       double precision, allocatable :: tensor_values(:)
+     end function
+ 
+     pure module function default_real_num_components(self) result(n)
+       implicit none
+       class(tensor_t), intent(in) :: self
+       integer n
+     end function
+ 
+     pure module function double_precision_num_components(self) result(n)
+       implicit none
+       class(tensor_t(double_precision)), intent(in) :: self
+       integer n
+     end function
+ 
+   end interface
+ 
+ end module tensor_m
+ 
+ submodule(tensor_m) tensor_s
+ contains
+ 
+     pure module function construct_default_real(values) result(tensor)
+       implicit none
+       real, intent(in) :: values(:)
+       type(tensor_t) tensor
+       tensor = tensor_t ()(values)
+     end function
+ 
+     pure module function construct_double_precision(values) result(tensor)
+       implicit none
+       double precision, intent(in) :: values(:)
+       type(tensor_t(double_precision)) tensor
+       tensor = tensor_t (double_precision)(values)
+     end function
+ 
+     pure module function default_real_values(self) result(tensor_values)
+       implicit none
+       class(tensor_t), intent(in) :: self
+       real, allocatable :: tensor_values(:)
+       tensor_values = self%values_
+     end function
+ 
+     pure module function double_precision_values(self) result(tensor_values)
+       implicit none
+       class(tensor_t(double_precision)), intent(in) :: self
+       double precision, allocatable :: tensor_values(:)
+       tensor_values = self%values_
+     end function
+ 
+ 
+     pure module function default_real_num_components(self) result(n)
+       implicit none
+       class(tensor_t), intent(in) :: self
+       integer n
+       n = default_real
+     end function
+ 
+     pure module function double_precision_num_components(self) result(n)
+       implicit none
+       class(tensor_t(double_precision)), intent(in) :: self
+       integer n
+       n = double_precision
+     end function
+ 
+ end submodule tensor_s
+ 
+ 
+   use tensor_m
+   type(tensor_t(kind(0e0))) :: a
+   type(tensor_t(kind(0D0))) :: b
+   a = tensor_t ([1e0,2e0])
+   print *, a%num_components (), a%values ()
+   b = tensor_t ([3d0,4d0])
+   print *, b%num_components (), b%values ()
+ end
+ ! { dg-final { scan-tree-dump-times "construct_" 4 "original" } }
+ ! { dg-final { scan-tree-dump-times "_components" 4 "original" } }
+ ! { dg-final { scan-tree-dump-times "_values" 4 "original" } }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/pure_result.f90 gcc-16-20251102/gcc/testsuite/gfortran.dg/pure_result.f90
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/pure_result.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/pure_result.f90	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,49 ----
+ ! { dg-do compile }
+ ! PR fortran/78640 - constraints on pure function results
+ !
+ ! F2018:C1585, F2023:C1594:
+ ! "The function result of a pure function shall not be both polymorphic and
+ !  allocatable, or have a polymorphic allocatable ultimate component."
+ 
+ program pr78640
+   implicit none
+ 
+   type foo_t
+   end type
+ 
+   type bar_t
+      integer,  allocatable :: dummy
+      class(*), allocatable :: c
+   end type bar_t
+ 
+ contains
+ 
+   pure function f() result(foo) ! { dg-error "is polymorphic allocatable" }
+     class(foo_t), allocatable :: foo
+     foo = foo_t()
+   end function
+ 
+   pure function f2() ! { dg-error "is polymorphic allocatable" }
+     class(foo_t), allocatable :: f2
+     f2 = foo_t()
+   end function
+ 
+   pure function g() result(foo) ! { dg-error "is polymorphic allocatable" }
+     class(*), allocatable :: foo
+     foo = foo_t()
+   end function
+ 
+   pure function g2() ! { dg-error "is polymorphic allocatable" }
+     class(*), allocatable :: g2
+     g2 = foo_t()
+   end function
+ 
+   pure function h() result(bar) ! { dg-error "polymorphic allocatable component" }
+     type(bar_t) :: bar
+   end function
+ 
+   pure function h2() ! { dg-error "polymorphic allocatable component" }
+     type(bar_t) :: h2
+   end function
+ 
+ end
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/team_form_3.f90 gcc-16-20251102/gcc/testsuite/gfortran.dg/team_form_3.f90
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/team_form_3.f90	Sun Oct 26 22:32:47 2025
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/team_form_3.f90	Sun Nov  2 22:34:16 2025
*************** end
*** 29,34 ****
  ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, 0B, 0B, 0B, 0\\)" "original" } }
  ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, 0B, &istat, 0B, 0\\)" "original" } }
  ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, 0B, &istat, &err, 30\\)" "original" } }
! ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, &C\\.\[0-9\]+, 0B, 0B, 0\\)" "original" } }
! ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, &C\\.\[0-9\]+, &istat, 0B, 0\\)" "original" } }
! ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, &C\\.\[0-9\]+, &istat, &err, 30\\)" "original" } }
--- 29,34 ----
  ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, 0B, 0B, 0B, 0\\)" "original" } }
  ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, 0B, &istat, 0B, 0\\)" "original" } }
  ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, 0B, &istat, &err, 30\\)" "original" } }
! ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, &D\\.\[0-9\]+, 0B, 0B, 0\\)" "original" } }
! ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, &D\\.\[0-9\]+, &istat, 0B, 0\\)" "original" } }
! ! { dg-final { scan-tree-dump "_gfortran_caf_form_team \\(new_team, &team, &D\\.\[0-9\]+, &istat, &err, 30\\)" "original" } }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.dg/vect/pr70102.f gcc-16-20251102/gcc/testsuite/gfortran.dg/vect/pr70102.f
*** gcc-16-20251026/gcc/testsuite/gfortran.dg/vect/pr70102.f	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.dg/vect/pr70102.f	Sun Nov  2 22:34:16 2025
***************
*** 0 ****
--- 1,21 ----
+ ! { dg-do compile }
+ ! { dg-additional-options "-Ofast" }
+       subroutine test (x,y,z)
+       integer x,y,z
+       real*8 a(5,x,y,z),b(5,x,y,z)
+       real*8 c
+ 
+       c = 0.0d0
+       do k=1,z
+          do j=1,y
+            do i=1,x
+               do l=1,5
+                  c = c + a(l,i,j,k)*b(l,i,j,k)
+               enddo
+            enddo
+          enddo
+       enddo
+       write(30,*)'c ==',c
+       return
+       end
+ ! { dg-final { scan-tree-dump "vectorizing a reduction chain" "vect" { target vect_double } } }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90 gcc-16-20251102/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90
*** gcc-16-20251026/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.target/aarch64/pr122408_1.f90	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,61 ----
+ ! { dg-do compile }
+ ! { dg-additional-options "-O2 -march=armv8.3-a" }
+ 
+ subroutine c_add_ab(n, a, c, b)         ! C += A * B
+   use iso_fortran_env, only: real64
+   implicit none
+   !GCC$ ATTRIBUTES noinline :: c_add_ab
+   integer, intent(in) :: n
+   complex(real64), intent(in)    :: a
+   complex(real64), intent(inout) :: c(*)
+   complex(real64), intent(in)    :: b(*)
+   integer :: k
+   do k = 1, n
+     c(k) = c(k) + a * b(k)
+   end do
+ end subroutine c_add_ab
+ 
+ subroutine c_sub_ab(n, a, c, b)         ! C -= A * B
+   use iso_fortran_env, only: real64
+   implicit none
+   !GCC$ ATTRIBUTES noinline :: c_sub_ab
+   integer, intent(in) :: n
+   complex(real64), intent(in)    :: a
+   complex(real64), intent(inout) :: c(*)
+   complex(real64), intent(in)    :: b(*)
+   integer :: k
+   do k = 1, n
+     c(k) = c(k) - a * b(k)
+   end do
+ end subroutine c_sub_ab
+ 
+ subroutine c_add_a_conjb(n, a, c, b)    ! C += A * conj(B)
+   use iso_fortran_env, only: real64
+   implicit none
+   !GCC$ ATTRIBUTES noinline :: c_add_a_conjb
+   integer, intent(in) :: n
+   complex(real64), intent(in)    :: a
+   complex(real64), intent(inout) :: c(*)
+   complex(real64), intent(in)    :: b(*)
+   integer :: k
+   do k = 1, n
+     c(k) = c(k) + a * conjg(b(k))
+   end do
+ end subroutine c_add_a_conjb
+ 
+ subroutine c_sub_a_conjb(n, a, c, b)    ! C -= A * conj(B)
+   use iso_fortran_env, only: real64
+   implicit none
+   !GCC$ ATTRIBUTES noinline :: c_sub_a_conjb
+   integer, intent(in) :: n
+   complex(real64), intent(in)    :: a
+   complex(real64), intent(inout) :: c(*)
+   complex(real64), intent(in)    :: b(*)
+   integer :: k
+   do k = 1, n
+     c(k) = c(k) - a * conjg(b(k))
+   end do
+ end subroutine c_sub_a_conjb
+ 
+ ! { dg-final { scan-assembler-times {fcmla\s+v[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #0} 2 } }
+ ! { dg-final { scan-assembler-times {fcmla\s+v[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #270} 2 } }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90 gcc-16-20251102/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90
*** gcc-16-20251026/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gfortran.target/aarch64/pr122408_2.f90	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,140 ----
+ ! { dg-do run }
+ ! { dg-additional-options "-O2" }
+ ! { dg-additional-options "-O2 -march=armv8.3-a" { target arm_v8_3a_complex_neon_hw } }
+ 
+ module util
+   use iso_fortran_env, only: real64, int64
+   implicit none
+ contains
+   pure logical function bitwise_eq(x, y)
+     complex(real64), intent(in) :: x, y
+     integer(int64) :: xr, xi, yr, yi
+     xr = transfer(real(x,kind=real64), 0_int64)
+     xi = transfer(aimag(x),             0_int64)
+     yr = transfer(real(y,kind=real64),  0_int64)
+     yi = transfer(aimag(y),              0_int64)
+     bitwise_eq = (xr == yr) .and. (xi == yi)
+   end function bitwise_eq
+ 
+   subroutine check_equal(tag, got, ref, nfail)
+     character(*), intent(in) :: tag
+     complex(real64), intent(in) :: got(:), ref(:)
+     integer, intent(inout) :: nfail
+     integer :: i
+     do i = 1, size(got)
+       if (.not. bitwise_eq(got(i), ref(i))) then
+         nfail = nfail + 1
+         write(*,'(A,": mismatch at i=",I0, "  got=",2ES16.8,"  ref=",2ES16.8)') &
+              trim(tag), i, real(got(i)), aimag(got(i)), real(ref(i)), aimag(ref(i))
+       end if
+     end do
+   end subroutine check_equal
+ end module util
+ 
+ module fcmla_ops
+   use iso_fortran_env, only: real64
+   implicit none
+ contains
+   subroutine c_add_ab(n, a, c, b)         ! C += A * B
+     !GCC$ ATTRIBUTES noinline :: c_add_ab
+     integer, intent(in) :: n
+     complex(real64), intent(in)    :: a
+     complex(real64), intent(inout) :: c(*)
+     complex(real64), intent(in)    :: b(*)
+     integer :: k
+     do k = 1, n
+       c(k) = c(k) + a * b(k)
+     end do
+   end subroutine c_add_ab
+ 
+   subroutine c_sub_ab(n, a, c, b)         ! C -= A * B
+     !GCC$ ATTRIBUTES noinline :: c_sub_ab
+     integer, intent(in) :: n
+     complex(real64), intent(in)    :: a
+     complex(real64), intent(inout) :: c(*)
+     complex(real64), intent(in)    :: b(*)
+     integer :: k
+     do k = 1, n
+       c(k) = c(k) - a * b(k)
+     end do
+   end subroutine c_sub_ab
+ 
+   subroutine c_add_a_conjb(n, a, c, b)    ! C += A * conj(B)
+     !GCC$ ATTRIBUTES noinline :: c_add_a_conjb
+     integer, intent(in) :: n
+     complex(real64), intent(in)    :: a
+     complex(real64), intent(inout) :: c(*)
+     complex(real64), intent(in)    :: b(*)
+     integer :: k
+     do k = 1, n
+       c(k) = c(k) + a * conjg(b(k))
+     end do
+   end subroutine c_add_a_conjb
+ 
+   subroutine c_sub_a_conjb(n, a, c, b)    ! C -= A * conj(B)
+     !GCC$ ATTRIBUTES noinline :: c_sub_a_conjb
+     integer, intent(in) :: n
+     complex(real64), intent(in)    :: a
+     complex(real64), intent(inout) :: c(*)
+     complex(real64), intent(in)    :: b(*)
+     integer :: k
+     do k = 1, n
+       c(k) = c(k) - a * conjg(b(k))
+     end do
+   end subroutine c_sub_a_conjb
+ end module fcmla_ops
+ 
+ program fcmla_accum_pairs
+   use iso_fortran_env, only: real64
+   use util
+   use fcmla_ops
+   implicit none
+ 
+   integer, parameter :: n = 4
+   complex(real64) :: a, b(n), c0(n)
+   complex(real64) :: c_add_ab_got(n),      c_add_ab_ref(n)
+   complex(real64) :: c_sub_ab_got(n),      c_sub_ab_ref(n)
+   complex(real64) :: c_add_conjb_got(n),   c_add_conjb_ref(n)
+   complex(real64) :: c_sub_conjb_got(n),   c_sub_conjb_ref(n)
+   integer :: i, fails
+ 
+   ! Constants (include a signed-zero lane)
+   a    = cmplx( 2.0_real64, -3.0_real64, kind=real64)
+   b(1) = cmplx( 1.5_real64, -2.0_real64, kind=real64)
+   b(2) = cmplx(-4.0_real64,  5.0_real64, kind=real64)
+   b(3) = cmplx(-0.0_real64,  0.0_real64, kind=real64)
+   b(4) = cmplx( 0.25_real64, 3.0_real64, kind=real64)
+ 
+   c0(1) = cmplx( 1.0_real64, -2.0_real64, kind=real64)
+   c0(2) = cmplx( 3.0_real64, -4.0_real64, kind=real64)
+   c0(3) = cmplx(-5.0_real64,  6.0_real64, kind=real64)
+   c0(4) = cmplx( 0.0_real64,  0.0_real64, kind=real64)
+ 
+   ! Run each form
+   c_add_ab_got    = c0; call c_add_ab     (n, a, c_add_ab_got,    b)
+   c_sub_ab_got    = c0; call c_sub_ab     (n, a, c_sub_ab_got,    b)
+   c_add_conjb_got = c0; call c_add_a_conjb(n, a, c_add_conjb_got, b)
+   c_sub_conjb_got = c0; call c_sub_a_conjb(n, a, c_sub_conjb_got, b)
+ 
+   ! Scalar references
+   do i = 1, n
+     c_add_ab_ref(i)    = c0(i) + a * b(i)
+     c_sub_ab_ref(i)    = c0(i) - a * b(i)
+     c_add_conjb_ref(i) = c0(i) + a * conjg(b(i))
+     c_sub_conjb_ref(i) = c0(i) - a * conjg(b(i))
+   end do
+ 
+   ! Bitwise checks
+   fails = 0
+   call check_equal("C +=  A*B       ", c_add_ab_got,    c_add_ab_ref,    fails)
+   call check_equal("C -=  A*B       ", c_sub_ab_got,    c_sub_ab_ref,    fails)
+   call check_equal("C +=  A*conj(B) ", c_add_conjb_got, c_add_conjb_ref, fails)
+   call check_equal("C -=  A*conj(B) ", c_sub_conjb_got, c_sub_conjb_ref, fails)
+ 
+   if (fails == 0) then
+     stop 0
+   else
+     stop 1
+   end if
+ end program fcmla_accum_pairs
+ 
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod
*** gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport.mod	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,14 ----
+ 
+ (* { dg-do compile } *)
+ (* { dg-options "-g -c" } *)
+ 
+ MODULE badimport ;
+ 
+ IMPORT ASCII ;
+ FROM StrIO IMPORT WriteString ;
+ FROM ASCIi IMPORT nul ;
+  (* { dg-error "error: the file containing the definition module 'ASCIi' cannot be found, did you mean ASCII" "ASCIi" { target *-*-* } 9 } *)
+ 
+ BEGIN
+ 
+ END badimport.
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod
*** gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport2.mod	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,12 ----
+ 
+ (* { dg-do compile } *)
+ (* { dg-options "-g -c" } *)
+ 
+ MODULE badimport2 ;
+ 
+ FROM StrIO IMPORT Writestring ;
+  (* { dg-error "error: In program module 'badimport2': unknown symbol 'Writestring', did you mean WriteString?" "Writestring" { target *-*-* } 7 } *)
+ 
+ BEGIN
+ 
+ END badimport2.
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod
*** gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport3.mod	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,17 ----
+ 
+ (* { dg-do compile } *)
+ (* { dg-options "-g -c" } *)
+ 
+ MODULE badimport3 ;
+ 
+ CONST
+    Foo = 42 ;
+ 
+ MODULE inner ;
+ IMPORT foo ;
+  (* { dg-error "error: In inner module 'inner': unknown symbol 'foo', did you mean Foo?" "foo" { target *-*-* } 11 } *)
+ END inner ;
+ 
+ 
+ BEGIN
+ END badimport3.
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod
*** gcc-16-20251026/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gm2.dg/spell/iso/fail/badimport4.mod	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,17 ----
+ 
+ (* { dg-do compile } *)
+ (* { dg-options "-g -c" } *)
+ 
+ MODULE badimport4 ;
+ 
+ CONST
+    Foo = 42 ;
+ 
+ MODULE inner ;
+ IMPORT foo ;
+  (* { dg-error "error: In inner module 'inner': unknown symbol 'foo', did you mean Foo?" "foo" { target *-*-* } 11 } *)
+ END inner ;
+ 
+ 
+ BEGIN
+ END badimport4.
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/aggr32.adb gcc-16-20251102/gcc/testsuite/gnat.dg/aggr32.adb
*** gcc-16-20251026/gcc/testsuite/gnat.dg/aggr32.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/aggr32.adb	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,15 ----
+ -- { dg-do compile }
+ 
+ with Aggr32_Pkg.Child;
+ 
+ procedure Aggr32 (W, H : Positive) is
+ 
+   use Aggr32_Pkg;
+ 
+   package Test_1 is new Child (Frame => (Width => W, Height => H));
+ 
+   package Test_2 is new Child (Frame => Rec'(Width => W, Height => H));
+ 
+ begin
+   null;
+ end;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads gcc-16-20251102/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/aggr32_pkg-child.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,6 ----
+ generic
+ 
+   Frame : Rec;
+ 
+ package Aggr32_Pkg.Child is
+ end Aggr32_Pkg.Child;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/aggr32_pkg.ads gcc-16-20251102/gcc/testsuite/gnat.dg/aggr32_pkg.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/aggr32_pkg.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/aggr32_pkg.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,8 ----
+ package Aggr32_Pkg is
+ 
+   type Rec is record
+     Width  : Positive;
+     Height : Positive;
+   end record;
+ 
+ end Aggr32_Pkg;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,5 ----
+ -- { dg-do compile }
+ 
+ with Generic_Inst3_Pkg1;
+ 
+ package Generic_Inst3 is new Generic_Inst3_Pkg1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.adb	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,14 ----
+ with Generic_Inst3_Pkg2; use Generic_Inst3_Pkg2;
+ with Generic_Inst3_Pkg3, Generic_Inst3_Pkg3.Child;
+ 
+ package body Generic_Inst3_Pkg1 is
+ 
+   package Pkg3 is new Generic_Inst3_Pkg3 (T);
+ 
+   use Pkg3;
+ 
+   package Child is new Pkg3.Child;
+ 
+   procedure Proc is null;
+ 
+ end Generic_Inst3_Pkg1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg1.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,8 ----
+ -- { dg-excess-errors "no code generated" }
+ 
+ generic
+ package Generic_Inst3_Pkg1 is
+ 
+   procedure Proc;
+ 
+ end Generic_Inst3_Pkg1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg2.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,9 ----
+ package Generic_Inst3_Pkg2 is
+ 
+   type T is new Integer;
+ 
+   procedure S_One (N: in out T) is null;
+ 
+   procedure S_Two (N: in out T) is null;
+ 
+ end Generic_Inst3_Pkg2;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3-child.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,9 ----
+ generic
+ 
+   with procedure S_Two (N: in out Number) is <>;
+ 
+ package Generic_Inst3_Pkg3.Child is
+ 
+   procedure Two (N: in out Number) renames S_Two;
+ 
+ end Generic_Inst3_Pkg3.Child;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst3_pkg3.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,11 ----
+ generic
+ 
+   type Number is private;
+ 
+   with procedure S_One (N: in out Number) is <>;
+ 
+ package Generic_Inst3_Pkg3 is
+ 
+   procedure One (N: in out Number) renames S_One;
+ 
+ end Generic_Inst3_Pkg3;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst4-child1.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst4-child1.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst4-child1.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst4-child1.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,6 ----
+ generic
+ 
+   with procedure Proc is <>;
+ 
+ package Generic_Inst4.Child1 is
+ end Generic_Inst4.Child1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst4-child2.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst4-child2.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst4-child2.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst4-child2.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,5 ----
+ -- { dg-do compile }
+ 
+ with Generic_Inst4.Child1;
+ 
+ package Generic_Inst4.Child2 is new Generic_Inst4.Child1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst4.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst4.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst4.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst4.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,5 ----
+ package Generic_Inst4 is
+ 
+   procedure Proc is null;
+ 
+ end Generic_Inst4;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst5.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst5.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst5.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst5.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,14 ----
+ -- { dg-do compile }
+ 
+ with Ada.Containers.Ordered_Sets;
+ with Generic_Inst5_Pkg1;
+ with Generic_Inst5_Pkg2;
+ 
+ package Generic_Inst5 is
+ 
+    package Charsets is new Ada.Containers.Ordered_sets (Character);
+    package P1 is new Generic_Inst5_Pkg1 (Charsets);
+    package P1_N is new P1.Nested;
+    package P2 is new Generic_Inst5_Pkg2 (P1, P1_N);
+ 
+ end Generic_Inst5;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg1.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg1.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg1.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg1.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,9 ----
+ with Ada.Containers.Ordered_Sets;
+ 
+ generic
+    with package Sets is new Ada.Containers.Ordered_Sets (<>);
+ package Generic_Inst5_Pkg1 is
+    generic
+    package Nested is
+    end Nested;
+ end Generic_Inst5_Pkg1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg2.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg2.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg2.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst5_pkg2.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,7 ----
+ with Generic_Inst5_Pkg1;
+ 
+ generic
+    with package P1 is new Generic_Inst5_Pkg1 (<>);
+    with package P1_N is new P1.Nested;
+ package Generic_Inst5_Pkg2 is
+ end Generic_Inst5_Pkg2;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,6 ----
+ -- { dg-do compile }
+ 
+ with Generic_Inst6_Pkg1.Child.Grand2;
+ with Generic_Inst6_Pkg3;
+ 
+ package Generic_Inst6 is new Generic_Inst6_Pkg3.Grand2;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand1.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,3 ----
+ generic
+ package Generic_Inst6_Pkg1.Child.Grand1 is
+ end Generic_Inst6_Pkg1.Child.Grand1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child-grand2.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,6 ----
+ with Generic_Inst6_Pkg1.Child.Grand1;
+ 
+ generic
+ package Generic_Inst6_Pkg1.Child.Grand2 is
+    package My_Grand1 is new Generic_Inst6_Pkg1.Child.Grand1;
+ end Generic_Inst6_Pkg1.Child.Grand2;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1-child.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,3 ----
+ generic
+ package Generic_Inst6_Pkg1.Child is
+ end Generic_Inst6_Pkg1.Child;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg1.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,3 ----
+ generic
+ package Generic_Inst6_Pkg1 is
+ end Generic_Inst6_Pkg1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg2.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,3 ----
+ with Generic_Inst6_Pkg1;
+ 
+ package Generic_Inst6_Pkg2 is new Generic_Inst6_Pkg1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst6_pkg3.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,4 ----
+ with Generic_Inst6_Pkg1.Child;
+ with Generic_Inst6_Pkg2;
+ 
+ package Generic_Inst6_Pkg3 is new Generic_Inst6_Pkg2.Child;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst7.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst7.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst7.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst7.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,17 ----
+ -- { dg-do compile }
+ 
+ package Generic_Inst7 is
+ 
+    function F return Integer is (0);
+ 
+    generic
+      with function Foo return Integer;
+    package P is
+      type Color is (Foo);
+    end P;
+ 
+    package My_P is new P (F);
+ 
+    I : Integer := My_P.Foo; -- { dg-error "expected type|found type" }
+ 
+ end Generic_Inst7;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst8.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst8.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/generic_inst8.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/generic_inst8.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,18 ----
+ -- { dg-do compile }
+ 
+ package Generic_Inst8 is
+ 
+    function F return Integer is (0);
+ 
+    generic
+      with function Foo return Integer;
+    package P is
+      type Color1 is (Foo);
+      type Color2 is (Foo);
+    end P;
+ 
+    package My_P is new P (F);
+ 
+    I : Integer := My_P.Foo; -- { dg-error "no visible interpretation|use" }
+ 
+ end Generic_Inst8;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/private3-child.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/private3-child.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/private3-child.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/private3-child.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,11 ----
+ -- { dg-do compile }
+ 
+ generic
+ 
+   type Ext is new T with private;
+ 
+ package Private3.Child is
+ 
+   procedure P_Private (X : in out Ext) is null;
+ 
+ end Private3.Child;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/private3.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/private3.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/private3.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/private3.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,9 ----
+ package Private3 is
+ 
+   type T is tagged null record;
+ 
+ private
+ 
+   procedure P_Private (X : in out T) is null;
+ 
+ end Private3;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,23 ----
+ -- { dg-do compile }
+ 
+ with Unknown_Discr1_Pkg; use Unknown_Discr1_Pkg;
+ with Unknown_Discr1_Pkg.Child;
+ with Unknown_Discr1_Pkg.Inst;
+ 
+ package Unknown_Discr1 is
+ 
+   A : Tagged_Type (0); -- { dg-error "type has unknown discriminants" }
+ 
+   B : Child.Derived_1 (1); -- { dg-error "type has unknown discriminants" }
+ 
+   C : Child.Derived_2 (2); -- { dg-error "type has unknown discriminants" }
+ 
+   D : Child.Nested.Derived_3 (3); -- { dg-error "type has unknown discriminants" }
+ 
+   E : Inst.Derived_1 (1); -- { dg-error "type has unknown discriminants" }
+ 
+   F : Inst.Derived_2 (2); -- { dg-error "type has unknown discriminants" }
+ 
+   G : Inst.Nested.Derived_3 (3); -- { dg-error "type has unknown discriminants" }
+ 
+ end Unknown_Discr1;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-child.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,17 ----
+ package Unknown_Discr1_Pkg.Child is
+ 
+   type Derived_1 is new Tagged_Type with null record;
+ 
+   type Derived_2 is new Derived_1 with null record;
+ 
+   package Nested is
+ 
+     type Derived_3 is new Tagged_Type with private;
+ 
+   private
+ 
+     type Derived_3 is new Tagged_Type with null record;
+ 
+   end Nested;
+ 
+ end Unknown_Discr1_Pkg.Child;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-g.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,21 ----
+ generic
+ 
+   type Base (<>) is new Tagged_Type with private;
+ 
+ package Unknown_Discr1_Pkg.G is
+ 
+   type Derived_1 is new Base with null record;
+ 
+   type Derived_2 is new Derived_1 with null record;
+ 
+   package Nested is
+ 
+     type Derived_3 is new Tagged_Type with private;
+ 
+   private
+ 
+     type Derived_3 is new Tagged_Type with null record;
+ 
+   end Nested;
+ 
+ end Unknown_Discr1_Pkg.G;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg-inst.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,3 ----
+ with Unknown_Discr1_Pkg.G;
+ 
+ package Unknown_Discr1_Pkg.Inst is new Unknown_Discr1_Pkg.G (Tagged_Type);
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads
*** gcc-16-20251026/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/specs/unknown_discr1_pkg.ads	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,9 ----
+ package Unknown_Discr1_Pkg is
+ 
+   type Tagged_Type (<>) is tagged limited private;
+ 
+ private
+ 
+   type Tagged_Type (Kind : Integer) is tagged limited null record;
+ 
+ end Unknown_Discr1_Pkg;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/gnat.dg/use_type4.adb gcc-16-20251102/gcc/testsuite/gnat.dg/use_type4.adb
*** gcc-16-20251026/gcc/testsuite/gnat.dg/use_type4.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/gnat.dg/use_type4.adb	Sun Nov  2 22:34:17 2025
***************
*** 0 ****
--- 1,29 ----
+ -- { dg-do compile }
+ 
+ procedure Use_Type4 is
+ 
+   package P1 is
+     type T is new Integer;
+     function "and" (L, R : in Integer) return T;
+   end P1;
+ 
+   package body P1 is
+     function "and" (L, R : in Integer) return T is
+     begin
+       return T (L * R);
+     end "and";
+   end P1;
+ 
+   use type P1.T;
+ 
+   package Renaming renames P1;
+ 
+   package P2 is
+     use Renaming;
+   end P2;
+ 
+   G : P1.T := Integer'(1) and Integer'(2);
+ 
+ begin
+   null;
+ end;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/attr-macro.rs gcc-16-20251102/gcc/testsuite/rust/compile/attr-macro.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/attr-macro.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/attr-macro.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ macro_rules! foo {
+     () => { #[cfg(all())] 12 }
+ }
+ 
+ fn main() -> i32 {
+     foo!()
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/attr_malformed_doc.rs gcc-16-20251102/gcc/testsuite/rust/compile/attr_malformed_doc.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/attr_malformed_doc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/attr_malformed_doc.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,3 ----
+ // { dg-error "valid forms for the attribute are ...doc.hidden.inline....... and ...doc = . string ..." "" { target *-*-* } .+1 }
+ #[doc]
+ trait MyTrait {}
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/attr_malformed_path.rs gcc-16-20251102/gcc/testsuite/rust/compile/attr_malformed_path.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/attr_malformed_path.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/attr_malformed_path.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,3 ----
+ #[cfg_attr(target_arch = "x86_64", path = (target_arch = "x86",    path = "x86.rs"))]
+ mod imp {}
+ // { dg-error "malformed .path. attribute input" "" { target *-*-* } .-2 }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/cfg-test.rs gcc-16-20251102/gcc/testsuite/rust/compile/cfg-test.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/cfg-test.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/cfg-test.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,4 ----
+ #[test]
+ fn foo() {
+     some_function_which_doesnt_exist();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/enum_discriminant3.rs gcc-16-20251102/gcc/testsuite/rust/compile/enum_discriminant3.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/enum_discriminant3.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/enum_discriminant3.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,8 ----
+ const x: isize = 1;
+ // { dg-warning "unused name" "" { target *-*-* } .-1 }
+ 
+ fn main() {
+     enum Foo {
+         Bar = x,
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/format_args_concat.rs gcc-16-20251102/gcc/testsuite/rust/compile/format_args_concat.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/format_args_concat.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/format_args_concat.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,51 ----
+ #![feature(rustc_attrs)]
+ 
+ #[rustc_builtin_macro]
+ macro_rules! format_args {
+     () => {};
+ }
+ 
+ #[rustc_builtin_macro]
+ macro_rules! concat {
+     () => {};
+ }
+ 
+ #[lang = "sized"]
+ trait Sized {}
+ 
+ pub mod core {
+     pub mod fmt {
+         pub struct Formatter;
+         pub struct Result;
+ 
+         pub struct Arguments<'a>;
+ 
+         impl<'a> Arguments<'a> {
+             pub fn new_v1(_: &'a [&'static str], _: &'a [ArgumentV1<'a>]) -> Arguments<'a> {
+                 Arguments
+             }
+         }
+ 
+         pub struct ArgumentV1<'a>;
+ 
+         impl<'a> ArgumentV1<'a> {
+             pub fn new<'b, T>(_: &'b T, _: fn(&T, &mut Formatter) -> Result) -> ArgumentV1 {
+                 ArgumentV1
+             }
+         }
+ 
+         pub trait Display {
+             fn fmt(&self, _: &mut Formatter) -> Result;
+         }
+ 
+         impl Display for i32 {
+             fn fmt(&self, _: &mut Formatter) -> Result {
+                 Result
+             }
+         }
+     }
+ }
+ 
+ fn main() {
+     let _formatted = format_args!(concat!("hello ", "{}"), 15);
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/global-path-array.rs gcc-16-20251102/gcc/testsuite/rust/compile/global-path-array.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/global-path-array.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/global-path-array.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,5 ----
+ const X: i32 = 1;
+ 
+ pub fn foo() -> [i32; 1] {
+     [::X]
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/impl_fnptr.rs gcc-16-20251102/gcc/testsuite/rust/compile/impl_fnptr.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/impl_fnptr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/impl_fnptr.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,18 ----
+ #[lang = "sized"]
+ pub trait Sized {}
+ 
+ #[lang = "eq"]
+ pub trait PartialEq<Rhs: ?Sized = Self> {
+     fn eq(&self, other: &Rhs) -> bool;
+ 
+     fn ne(&self, other: &Rhs) -> bool {
+         !self.eq(other)
+     }
+ }
+ 
+ impl<Ret> PartialEq for extern "C" fn() -> Ret {
+     #[inline]
+     fn eq(&self, other: &Self) -> bool {
+         *self as usize == *other as usize
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/import_wildcards.rs gcc-16-20251102/gcc/testsuite/rust/compile/import_wildcards.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/import_wildcards.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/import_wildcards.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,8 ----
+ mod x {}
+ 
+ mod y {}
+ 
+ fn main() {
+     use x as _;
+     use y as _;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-1725-2.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-1725-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-1725-2.rs	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-1725-2.rs	Sun Nov  2 22:34:18 2025
*************** pub fn foo<T: core::ops::Add<Output = i3
*** 26,31 ****
  
  pub fn main() {
      foo(123f32);
!     // { dg-error "type mismatch, expected .i32. but got .f32." "" { target *-*-* } .-1 }
!     // { dg-error "bounds not satisfied for f32 .Add. is not satisfied" "" { target *-*-* } .-2 }
  }
--- 26,30 ----
  
  pub fn main() {
      foo(123f32);
!     // { dg-error "bounds not satisfied for f32 .Add. is not satisfied" "" { target *-*-* } .-1 }
  }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-2394.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-2394.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-2394.rs	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-2394.rs	Sun Nov  2 22:34:18 2025
***************
*** 1,5 ****
--- 1,6 ----
  const A: i32 = (1 / 0);
  // { dg-error "division by zero" "" { target *-*-* } .-1 }
+ // { dg-error "is not a constant expression" "" { target *-*-* } .-2 }
  
  fn main() {
      let a = 1 / 0;
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3538.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3538.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3538.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3538.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,9 ----
+ enum A {
+     Value(()),
+ }
+ 
+ fn main() {
+     let a = A::Value(());
+     a == A::Value;
+     // { dg-error "variant expected constructor call" "" { target *-*-* } .-1 }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3556.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3556.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3556.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3556.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,4 ----
+ fn main() {
+     let ref mut a @ (ref mut b,);
+     // { dg-error "expected T\\?, found tuple" "" { target *-*-* } .-1 }
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3592.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3592.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3592.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3592.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ pub trait X {
+     fn x() {
+         fn f(&mut self) {}
+         // { dg-error ".self. parameter is only allowed in associated functions" "" { target *-*-* } .-1 }
+         f();
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3645.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3645.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3645.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3645.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,6 ----
+ // { dg-warning "unused name 'y'" "" { target *-*-* } 5 }
+ // { dg-warning "unused name 'z'" "" { target *-*-* } 5 }
+ 
+ fn main() {
+     let (ref y,z) = (1i32, 2u32);
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3726.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3726.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3726.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3726.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,17 ----
+ pub enum TypeCtor {
+     Slice,
+     Array,
+ }
+ pub struct ApplicationTy(TypeCtor);
+ 
+ macro_rules! ty_app {
+     ($ctor:pat) => {
+         ApplicationTy($ctor)
+     };
+ }
+ 
+ pub fn foo(ty: ApplicationTy) {
+     match ty {
+         ty_app!(TypeCtor::Array) => {}
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3898.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3898.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3898.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3898.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,112 ----
+ // { dg-additional-options "-frust-compile-until=lowering" }
+ 
+ #[lang = "sized"]
+ trait Sized {}
+ 
+ enum Result<T, E> {
+     Ok(T),
+     Err(E),
+ }
+ 
+ use Result::{Err, Ok};
+ 
+ struct Utf8Error;
+ 
+ const CONT_MASK: u8 = 15;
+ const TAG_CONT_U8: u8 = 15;
+ 
+ #[inline(always)]
+ pub fn run_utf8_validation(v: &[u8]) -> Result<(), Utf8Error> {
+     let mut index = 0;
+     let len = 64;
+ 
+     let usize_bytes = 8;
+     let ascii_block_size = 2 * usize_bytes;
+     let blocks_end = if len >= ascii_block_size {
+         len - ascii_block_size + 1
+     } else {
+         0
+     };
+ 
+     while index < len {
+         let old_offset = index;
+         macro_rules! err {
+             ($error_len: expr) => {
+                 return Err(Utf8Error)
+             };
+         }
+ 
+         macro_rules! next {
+             () => {{
+                 index += 1;
+                 // we needed data, but there was none: error!
+                 if index >= len {
+                     err!(None)
+                 }
+                 v[index]
+             }};
+         }
+ 
+         let first = v[index];
+         if first >= 128 {
+             let w = 15;
+             // 2-byte encoding is for codepoints  \u{0080} to  \u{07ff}
+             //        first  C2 80        last DF BF
+             // 3-byte encoding is for codepoints  \u{0800} to  \u{ffff}
+             //        first  E0 A0 80     last EF BF BF
+             //   excluding surrogates codepoints  \u{d800} to  \u{dfff}
+             //               ED A0 80 to       ED BF BF
+             // 4-byte encoding is for codepoints \u{1000}0 to \u{10ff}ff
+             //        first  F0 90 80 80  last F4 8F BF BF
+             //
+             // Use the UTF-8 syntax from the RFC
+             //
+             // https://tools.ietf.org/html/rfc3629
+             // UTF8-1      = %x00-7F
+             // UTF8-2      = %xC2-DF UTF8-tail
+             // UTF8-3      = %xE0 %xA0-BF UTF8-tail / %xE1-EC 2( UTF8-tail ) /
+             //               %xED %x80-9F UTF8-tail / %xEE-EF 2( UTF8-tail )
+             // UTF8-4      = %xF0 %x90-BF 2( UTF8-tail ) / %xF1-F3 3( UTF8-tail ) /
+             //               %xF4 %x80-8F 2( UTF8-tail )
+             match w {
+                 2 => {
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(1))
+                     }
+                 }
+                 3 => {
+                     match (first, next!()) {
+                         (0xE0, 0xA0..=0xBF)
+                         | (0xE1..=0xEC, 0x80..=0xBF)
+                         | (0xED, 0x80..=0x9F)
+                         | (0xEE..=0xEF, 0x80..=0xBF) => {}
+                         _ => err!(Some(1)),
+                     }
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(2))
+                     }
+                 }
+                 4 => {
+                     match (first, next!()) {
+                         (0xF0, 0x90..=0xBF) | (0xF1..=0xF3, 0x80..=0xBF) | (0xF4, 0x80..=0x8F) => {}
+                         _ => err!(Some(1)),
+                     }
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(2))
+                     }
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(3))
+                     }
+                 }
+                 _ => err!(Some(1)),
+             }
+             index += 1;
+         } else {
+             index += 1;
+         }
+     }
+ 
+     Ok(())
+ }
+ 
+ fn main() {}
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3922.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3922.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3922.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3922.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,12 ----
+ struct S(
+     [u8; {
+         {
+             // { dg-error "mismatched types. expected .... but got ..integer.. .E0308." "" { target *-*-* } .-1 }
+             struct Z;
+             0
+         }
+         0
+     }],
+ );
+ 
+ fn main() {}
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3924.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3924.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3924.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3924.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,6 ----
+ pub fn main() {
+     const S: usize = 23 as i64;
+     // { dg-error {mismatched types, expected .usize. but got .i64.} "" { target *-*-* } .-1 }
+     [0; S];
+     ()
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3928.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3928.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3928.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3928.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,12 ----
+ // { dg-do compile }
+ // { dg-options "-fsyntax-only" }
+ 
+ #![feature(exclusive_range_pattern)]
+ 
+ fn Foo() {
+     let x = 1u32;
+ 
+     match x {
+         3..-1 => 4,
+     };
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3929-1.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3929-1.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3929-1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3929-1.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,9 ----
+ // { dg-options "-w" }
+ struct S();
+ 
+ fn main() {
+     let s = S{};
+     match s {
+         S{..} => {}
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3929-2.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3929-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3929-2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3929-2.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,12 ----
+ // { dg-options "-w" }
+ struct S {
+     x: i32,
+     y: i32,
+ }
+ 
+ fn main() {
+     let s = S{x: 1, y: 2};
+     match s {
+         S{x: 1, ..} => {}
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3930.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3930.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3930.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3930.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,4 ----
+ // { dg-additional-options "-w" }
+ fn main() {
+     let (a, .., b) = (2, 3);
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3947.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3947.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3947.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3947.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,10 ----
+ enum _Enum {
+     A(),
+ }
+ 
+ type _E = _Enum;
+ 
+ // { dg-warning "function is never used: '_a'" "" { target *-*-* } .+1 }
+ const fn _a() -> _Enum {
+     _E::A()
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3958.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3958.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3958.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3958.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,11 ----
+ // { dg-options "-fsyntax-only" }
+ trait A {
+     fn a(&self) -> <Self as A>::X;
+ }
+ 
+ impl A for u32 {}
+ 
+ fn main() {
+     let a: u32 = 0;
+     let b: u32 = a.a();
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3965-1.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3965-1.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3965-1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3965-1.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,4 ----
+ fn main() {
+     [(); { continue }];
+     // { dg-error ".continue. outside of a loop .E0268." "" { target *-*-* } .-1 }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3965-2.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3965-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3965-2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3965-2.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ fn main() {
+     loop { continue }
+ 
+     [(); {while true {break}; 0}];
+ 
+     [(); {while true {break}; 0}];
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3966.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3966.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3966.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3966.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,5 ----
+ struct S {
+     #[cfg_attr()]
+     field: u8,
+     // { dg-error "malformed .cfg_attr. attribute input" "" { target *-*-* } .-2 }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3969.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3969.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3969.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3969.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,30 ----
+ #[lang = "sized"]
+ pub trait Sized {
+     // Empty.
+ }
+ 
+ #[lang = "fn_once"]
+ pub trait FnOnce<Args> {
+     #[lang = "fn_once_output"]
+     type Output;
+ 
+     extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+ }
+ 
+ fn main() {
+     [(); {
+         while true {
+             // { dg-error ".constexpr. loop iteration count exceeds limit" "" { target *-*-* } .-1 }
+             break 9;
+             // { dg-error "can only .break. with a value inside a .loop. block .E0571." "" { target *-*-* } .-1 }
+         }
+         51
+     }];
+ 
+     while true {
+         break (|| {
+             // { dg-error "can only .break. with a value inside a .loop. block .E0571." "" { target *-*-* } .-1 }
+             let while_true = 9;
+         });
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-3974.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-3974.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-3974.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-3974.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,8 ----
+ impl<'a, F> RunUntil<'a, F> {
+     // { dg-error "could not resolve type path" "" { target *-*-* } .-1 }
+     fn project<'pin>() -> Projection<'pin, 'a, F> {
+         // { dg-error "could not resolve type path" "" { target *-*-* } .-1 }
+         Self!()
+         // { dg-error "could not resolve macro invocation" "" { target *-*-* } .-1 }
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4090-1.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4090-1.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4090-1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4090-1.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,68 ----
+ mod core {
+     mod marker {
+         #[lang = "sized"]
+         pub trait Sized {}
+ 
+         #[lang = "phantom_data"]
+         #[stable(feature = "rust1", since = "1.0.0")]
+         pub struct PhantomData<T: ?Sized>;
+ 
+         #[unstable(feature = "structural_match", issue = "31434")]
+         #[lang = "structural_teq"]
+         pub trait StructuralEq {
+             // Empty.
+         }
+ 
+         #[unstable(feature = "structural_match", issue = "31434")]
+         #[lang = "structural_peq"]
+         pub trait StructuralPartialEq {
+             // Empty.
+         }
+     }
+ 
+     pub mod cmp {
+         use super::marker::Sized;
+ 
+         #[lang = "eq"]
+         pub trait PartialEq<Rhs: ?Sized = Self> {
+             fn eq(&self, other: &Rhs) -> bool;
+ 
+             fn ne(&self, other: &Rhs) -> bool {
+                 !self.eq(other)
+             }
+         }
+ 
+         pub trait Eq: PartialEq<Self> {
+             fn assert_receiver_is_total_eq(&self) {}
+         }
+     }
+ 
+     pub mod ptr {
+ 
+         use super::cmp::{Eq, PartialEq};
+ 
+         macro_rules! fnptr_impls_safety_abi {
+             ($FnTy: ty, $($Arg: ident),*) => {
+                 #[stable(feature = "fnptr_impls", since = "1.4.0")]
+                 impl<Ret, $($Arg),*> PartialEq for $FnTy {
+                     #[inline]
+                     fn eq(&self, other: &Self) -> bool {
+                         *self as usize == *other as usize
+                     }
+                 }
+ 
+                 #[stable(feature = "fnptr_impls", since = "1.4.0")]
+                 impl<Ret, $($Arg),*> Eq for $FnTy {}
+ 
+             }
+         }
+ 
+         fnptr_impls_safety_abi! { extern "Rust" fn() -> Ret, }
+     }
+ }
+ 
+ #[derive(PartialEq, Eq)]
+ struct AllowedBelow {
+     // { dg-warning "struct is never constructed" "" { target *-*-* } .-1 }
+     f: fn(),
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4090-2.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4090-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4090-2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4090-2.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,71 ----
+ mod core {
+     mod marker {
+         #[lang = "sized"]
+         pub trait Sized {}
+ 
+         #[lang = "phantom_data"]
+         #[stable(feature = "rust1", since = "1.0.0")]
+         pub struct PhantomData<T: ?Sized>;
+ 
+         #[unstable(feature = "structural_match", issue = "31434")]
+         #[lang = "structural_teq"]
+         pub trait StructuralEq {
+             // Empty.
+         }
+ 
+         #[unstable(feature = "structural_match", issue = "31434")]
+         #[lang = "structural_peq"]
+         pub trait StructuralPartialEq {
+             // Empty.
+         }
+     }
+ 
+     pub mod cmp {
+         use super::marker::Sized;
+ 
+         #[lang = "eq"]
+         pub trait PartialEq<Rhs: ?Sized = Self> {
+             fn eq(&self, other: &Rhs) -> bool;
+ 
+             fn ne(&self, other: &Rhs) -> bool {
+                 !self.eq(other)
+             }
+         }
+ 
+         pub trait Eq: PartialEq<Self> {
+             fn assert_receiver_is_total_eq(&self) {}
+         }
+     }
+ 
+     pub mod ptr {
+ 
+         use super::cmp::{Eq, PartialEq};
+ 
+         macro_rules! fnptr_impls_safety_abi {
+             ($FnTy: ty, $($Arg: ident),*) => {
+                 #[stable(feature = "fnptr_impls", since = "1.4.0")]
+                 impl<Ret, $($Arg),*> PartialEq for $FnTy {
+                     #[inline]
+                     fn eq(&self, other: &Self) -> bool {
+                         *self as usize == *other as usize
+                     }
+                 }
+ 
+                 #[stable(feature = "fnptr_impls", since = "1.4.0")]
+                 impl<Ret, $($Arg),*> Eq for $FnTy {}
+ 
+             }
+         }
+ 
+         fnptr_impls_safety_abi! { extern "Rust" fn() -> Ret, }
+         fnptr_impls_safety_abi! { extern "C" fn() -> Ret, }
+         fnptr_impls_safety_abi! { unsafe extern "Rust" fn() -> Ret, }
+         fnptr_impls_safety_abi! { unsafe extern "C" fn() -> Ret, }
+     }
+ }
+ 
+ #[derive(PartialEq, Eq)]
+ struct AllowedBelow {
+     // { dg-warning "struct is never constructed" "" { target *-*-* } .-1 }
+     f: fn(),
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4139.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4139.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4139.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4139.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ // { dg-skip-if "" { *-*-* } { "-m32" } { "" } }
+ const X: i32 = const {
+     let a = 0x736f6d6570736575;
+     // { dg-error "integer overflows the respective type" "" { target *-*-* } .-1 }
+     let b = 14;
+     a + b
+ };
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4145.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4145.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4145.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4145.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,13 ----
+ // { dg-excess-errors "warnings" }
+ 
+ struct S {
+     field: [u8; {
+         #[path = "outer/inner.rs"]
+         // { dg-warning "error handling module file for .inner." "#4145" { xfail *-*-* } .+1 }
+         mod inner;
+         // OK
+         0
+     }],
+ }
+ 
+ fn main() {}
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4146.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4146.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4146.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4146.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,3 ----
+ const _NISIZE_DIV_P: &isize = &(1isize / 0);
+ // { dg-error "division by zero" "" { target *-*-* } .-1 }
+ // { dg-error "is not a constant expression" "" { target *-*-* } .-2 }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4148.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4148.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4148.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4148.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,26 ----
+ // { dg-excess-errors "warnings" }
+ 
+ // TODO: all `xfail` conditions should be changed to `target` once the ICE in #4148 is resolved
+ 
+ pub fn ret_parens(x: i32) -> i32 {
+     // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 }
+     ((x+1))
+ }
+ 
+ // { dg-warning "unnecessary parentheses around type" "#4148" { xfail *-*-* } .+1 }
+ // { dg-warning "unnecessary parentheses around pattern" "#4148" { xfail *-*-* } .+1 }
+ pub fn arg_ret_parens((x): (i32)) -> (i32) {
+     // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 }
+     ((x+1))
+ }
+ 
+ // { dg-warning "unnecessary parentheses around type" "#4148" { xfail *-*-* } .+1 }
+ pub fn ret_rpit_parens2(x: i32) -> (i32) {
+     // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 }
+     ((x+1))
+ }
+ 
+ pub fn ret_parens3(x: i32) -> i32 {
+     // { dg-warning "unnecessary parentheses around block return value" "#4148" { xfail *-*-* } .+1 }
+     ((x+1))
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4155.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4155.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4155.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4155.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ struct Bug {
+     inner: [(); match Vec::new {
+         f @  |n() => 1
+ // { dg-error "failed to parse pattern to bind" "" { target *-*-* } .-1 }
+ // { dg-error "unexpected token .|. in pattern" "" { target *-*-* } .-2 }
+     }],
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4165.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4165.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4165.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4165.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,12 ----
+ const N: usize = 2;
+ const ARR: [i32; N] = [42; X];
+ // { dg-error {cannot find value .X. in this scope \[E0425\]} "" { target *-*-* } .-1 }
+ // { dg-error {mismatched types, expected .\[i32; 2]. but got .<tyty::error>. \[E0308\]} "" { target *-*-* } .-2 }
+ // { dg-error {mismatched types, expected .usize. but got .bool. \[E0308\]} "" { target *-*-* } .-3 }
+ const X: bool = (N[0] == 99) && (ARR[0] == 0);
+ // { dg-error {the type .usize. cannot be indexed by .<integer>. \[E0277\]} "" { target *-*-* } .-1 }
+ // { dg-error {mismatched types, expected .<tyty::error>. but got .<integer>. \[E0308\]} "" { target *-*-* } .-2 }
+ 
+ fn main() {
+     let _ = X;
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4168.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4168.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4168.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4168.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ const fn add(x: usize, y: usize) -> i32 {
+     add + y
+     // { dg-error "cannot apply operator .+. to types fn .x usize,y usize,. -> i32 and usize" "" { target *-*-* } .-1 }
+ }
+ const ARR: [i32; add(1, 2)] = [5, 6, 1];
+ // { dg-error "mismatched types, expected .usize. but got .i32. .E0308." "" { target *-*-* } .-1 }
+ // { dg-error "mismatched types" "" { target *-*-* } .-2 }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4212.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4212.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4212.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4212.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,5 ----
+ #![derive(PartialOrd, PartialEq)]
+ // { dg-error "derive attribute cannot be used at crate level" "" { target *-*-* } .-1 }
+ pub fn check_ge(a: i32, b: i32) -> bool {
+     a >= b
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/issue-4231.rs gcc-16-20251102/gcc/testsuite/rust/compile/issue-4231.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/issue-4231.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/issue-4231.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,6 ----
+ #[repr = ""] // { dg-error "malformed .repr. attribute" }
+ struct ThreeInts {
+     first: i16,
+     second: i8,
+     third: i32
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs gcc-16-20251102/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/macros/mbe/macro-issue4054.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,14 ----
+ #[allow(path_statements)]
+ 
+ macro_rules! array_impl_default {
+     {$t:ident} => {
+         $t;
+         array_impl_default!{}
+     };
+     {} => {}
+ }
+ 
+ pub fn foo() {
+     let x = 12;
+     array_impl_default! {x}
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/macros/mbe/macro49.rs gcc-16-20251102/gcc/testsuite/rust/compile/macros/mbe/macro49.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/macros/mbe/macro49.rs	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/testsuite/rust/compile/macros/mbe/macro49.rs	Sun Nov  2 22:34:18 2025
***************
*** 1,3 ****
--- 1,14 ----
+ #[lang = "sized"]
+ pub trait Sized {}
+ 
+ #[lang = "fn_once"]
+ trait FnOnce<Args> {
+     #[lang = "fn_once_output"]
+     type Output;
+ 
+     extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+ }
+ 
  macro_rules! closure {
      () => {{
          14 + 15
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/macros/mbe/macro58.rs gcc-16-20251102/gcc/testsuite/rust/compile/macros/mbe/macro58.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/macros/mbe/macro58.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/macros/mbe/macro58.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,12 ----
+ pub fn print(a: *const u8) {}
+ #[macro_export]
+ macro_rules! pr_warn (
+     ($($arg:tt)*) => (
+         $($crate::print($arg))*
+     )
+ );
+ 
+ fn main() {
+     pr_warn!("test\0", "test\0");
+     // { dg-error "expecting .;. but .identifier. found" "" { target *-*-* } .-1 }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs gcc-16-20251102/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/match-tuplestructpattern-err.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,14 ----
+ fn main() {
+     struct A (i32, i32);
+     let a = A (0, 1);
+ 
+     match a {
+         A (1, 2, 3, 4) => {},
+         // { dg-error "this pattern has 4 fields but the corresponding tuple variant has 2 fields .E0023." "" { target *-*-* } .-1 }
+         A (1, 2, .., 3, 4) => {},
+         // { dg-error "this pattern has 4 fields but the corresponding tuple variant has 2 fields .E0023." "" { target *-*-* } .-1 }
+         A (.., 3, 4, 5) => {},
+         // { dg-error "this pattern has 3 fields but the corresponding tuple variant has 2 fields .E0023." "" { target *-*-* } .-1 }
+         _ => {}
+     }
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs gcc-16-20251102/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/match-tuplestructpattern-non-variant.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,20 ----
+ enum Empty {}
+ enum NonEmpty {
+     Foo(i32),
+ }
+ 
+ fn f(e: Empty) {
+     match e { 
+         Empty(0) => {} // { dg-error "expected tuple struct or tuple variant, found enum 'Empty'" }
+     }
+ 
+     match e {
+         Empty(Empty(..)) => {} // { dg-error "expected tuple struct or tuple variant, found enum 'Empty'" }
+     }
+ }
+ 
+ fn g(e: NonEmpty) {
+     match e {
+         NonEmpty(0) => {} // { dg-error "expected tuple struct or tuple variant, found enum 'NonEmpty'" }
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs gcc-16-20251102/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/match-tuplestructpattern-rest.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,9 ----
+ fn main() {
+     struct A (i32, i32);
+     let a = A (0, 1);
+ 
+     match a {
+         A (0, ..) => {},
+         _ => {}
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/parse_closure_bind.rs gcc-16-20251102/gcc/testsuite/rust/compile/parse_closure_bind.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/parse_closure_bind.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/parse_closure_bind.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,19 ----
+ // { dg-additional-options "-frust-compile-until=typecheck" }
+ // TODO: this should typecheck
+ 
+ #[lang = "sized"]
+ trait Sized {}
+ 
+ #[lang = "fn_once"]
+ pub trait FnOnce<Args> {
+     /// The returned type after the call operator is used.
+     #[lang = "fn_once_output"]
+     type Output;
+ 
+     /// Performs the call operation.
+     extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+ }
+ 
+ pub fn foo() {
+     (|_a @ _b| {}) (1)
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/parse_float_dot.rs gcc-16-20251102/gcc/testsuite/rust/compile/parse_float_dot.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/parse_float_dot.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/parse_float_dot.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,3 ----
+ // floating point literals can't start with a '.'
+ // TODO: improve the error message emitted here
+ const X: f32 = .5; // { dg-error ".*" }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/primitive-import.rs gcc-16-20251102/gcc/testsuite/rust/compile/primitive-import.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/primitive-import.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/primitive-import.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ mod primitive {
+     pub use i32;
+ }
+ 
+ pub fn foo() -> primitive::i32 {
+     1
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/slice_rest_pattern.rs gcc-16-20251102/gcc/testsuite/rust/compile/slice_rest_pattern.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/slice_rest_pattern.rs	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/testsuite/rust/compile/slice_rest_pattern.rs	Sun Nov  2 22:34:18 2025
***************
*** 1,5 ****
! // { dg-options "-fsyntax-only" }
! fn foo(a: &[u32]) {
      match a {
          [first, ..] => {}
          [.., last] => {}
--- 1,4 ----
! pub fn foo(a: &[u32]) {
      match a {
          [first, ..] => {}
          [.., last] => {}
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs gcc-16-20251102/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/tuple_index_on_non_tuple.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,15 ----
+ enum E {
+     V(usize),
+ }
+ 
+ struct S {
+     field: i32,
+ }
+ 
+ fn main() {
+     let e = E::V(0);
+     let _ = e.0; // { dg-error "expected tuple or tuple struct, found 'E'" }
+ 
+     let s = S { field: 0 };
+     let _ = s.0; // { dg-error "expected tuple or tuple struct, found 'S'" }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs gcc-16-20251102/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/tuplepattern-rest-readonly.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,5 ----
+ fn main() {
+     let (a, .., b) = (1, 1);
+     a = 2; // { dg-error "assignment of read-only variable .a." }
+     b = 2; // { dg-error "assignment of read-only variable .b." }
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs gcc-16-20251102/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/tuplepattern-restpattern-typecheck-err.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,8 ----
+ fn main() {
+     match (1, 2.2, "not 3") {
+         // { dg-error "expected a tuple with 3 elements, found one with 5 elements" "" { target *-*-* } .+1 }
+         (a, b, .., c, d, e) => {
+             let _ = b + c; // { dg-error "cannot apply operator .+. to types <float> and & str" }
+         }
+     }
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/use_3.rs gcc-16-20251102/gcc/testsuite/rust/compile/use_3.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/use_3.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/use_3.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,10 ----
+ mod intrinsic {
+     pub fn foo() {}
+ }
+ 
+ pub mod a {
+     pub fn b() {
+         use crate::intrinsic;
+         intrinsic::foo();
+     }
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/use_self_alone.rs gcc-16-20251102/gcc/testsuite/rust/compile/use_self_alone.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/use_self_alone.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/use_self_alone.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,2 ----
+ use self;
+ // { dg-error ".self. imports are only allowed within a { } list" "" { target *-*-* } .-1 }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/compile/use_self_alone_in_list.rs gcc-16-20251102/gcc/testsuite/rust/compile/use_self_alone_in_list.rs
*** gcc-16-20251026/gcc/testsuite/rust/compile/use_self_alone_in_list.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/compile/use_self_alone_in_list.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,7 ----
+ struct B;
+ 
+ use {B as B2, self};
+ // { dg-error ".self. import can only appear in an import list with a non-empty prefix" "" { target *-*-* } .-1 }
+ 
+ use {self};
+ // { dg-error ".self. import can only appear in an import list with a non-empty prefix" "" { target *-*-* } .-1 }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/core/core.exp gcc-16-20251102/gcc/testsuite/rust/core/core.exp
*** gcc-16-20251026/gcc/testsuite/rust/core/core.exp	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/core/core.exp	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,37 ----
+ # Copyright (C) 2025 Free Software Foundation, Inc.
+ 
+ # This program is free software; you can redistribute it and/or modify
+ # it under the terms of the GNU General Public License as published by
+ # the Free Software Foundation; either version 3 of the License, or
+ # (at your option) any later version.
+ # 
+ # This program is distributed in the hope that it will be useful,
+ # but WITHOUT ANY WARRANTY; without even the implied warranty of
+ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ # GNU General Public License for more details.
+ # 
+ # You should have received a copy of the GNU General Public License
+ # along with GCC; see the file COPYING3.  If not see
+ # <http://www.gnu.org/licenses/>.
+ 
+ # Compile test libcore, no torture testing.
+ #
+ # Skip torture testing for now, as it'd be slow
+ 
+ # Load support procs.
+ load_lib rust-dg.exp
+ 
+ # Initialize `dg'.
+ dg-init
+ 
+ # Main loop.
+ set saved-dg-do-what-default ${dg-do-what-default}
+ 
+ set dg-do-what-default "compile"
+ set individual_timeout 600
+ dg-additional-files [lsort [glob -nocomplain $srcdir/../../libgrust/rustc-lib/*]]
+ dg-runtest $srcdir/../../libgrust/rustc-lib/core/src/lib.rs "-frust-edition=2018 -frust-crate=core -frust-compile-until=astvalidation -w" ""
+ set dg-do-what-default ${saved-dg-do-what-default}
+ 
+ # All done.
+ dg-finish
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs gcc-16-20251102/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/testsuite/rust/execute/inline_asm_inout_ident.rs	Sun Nov  2 22:34:18 2025
***************
*** 1,3 ****
--- 1,4 ----
+ /* { dg-do run { target x86_64*-*-* } } */
  /* { dg-output "Value is: 5\r*\n" } */
  #![feature(rustc_attrs)]
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/inline_asm_inout_var.rs gcc-16-20251102/gcc/testsuite/rust/execute/inline_asm_inout_var.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/inline_asm_inout_var.rs	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/testsuite/rust/execute/inline_asm_inout_var.rs	Sun Nov  2 22:34:18 2025
***************
*** 1,3 ****
--- 1,4 ----
+ /* { dg-do run { target x86_64*-*-* } } */
  /* { dg-output "Value is: 5\r*\n" } */
  #![feature(rustc_attrs)]
  
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs gcc-16-20251102/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/execute/torture/let-identifierpattern-subpattern.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,11 ----
+ fn main() -> i32 {
+     let foo @ (bar, _, _) = (0, 2, 3);
+     let mut ret = 1;
+ 
+     match foo {
+         (0, 2, 3) => { ret = bar },
+         _ => {}
+     }
+ 
+     ret
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/torture/link-name.rs gcc-16-20251102/gcc/testsuite/rust/execute/torture/link-name.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/torture/link-name.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/execute/torture/link-name.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,16 ----
+ // { dg-additional-options "-fdump-rtl-final" }
+ // { dg-final { scan-rtl-dump "printf" "final" } }
+ // { dg-output "gcc\r*\n" }
+ 
+ extern "C" {
+     #[link_name = "printf"]
+     fn druckt(fmt: *const i8, ...);
+ }
+ 
+ fn main() -> i32 {
+     let a = "gcc\0";
+ 
+     unsafe { druckt("%s\n\0" as *const str as *const i8, a as *const str as *const i8); }
+ 
+     0
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-slicepattern-array-2.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,27 ----
+ // { dg-output "correct\r*" }
+ extern "C" {
+     fn puts(s: *const i8);
+ }
+ 
+ fn main() -> i32 {
+     let a = [0, 4, 5, 6, 1];
+     let mut ret = 1;
+ 
+     match a {
+         [1, .., b] => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         }
+         [0, .., 0] => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         },
+         [0, .., b] => {
+             ret -= b;
+             unsafe { puts("correct\0" as *const str as *const i8) }
+         },
+         _ => {}
+     }
+ 
+     ret
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-slicepattern-slice-2.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,28 ----
+ // { dg-output "correct\r*" }
+ extern "C" {
+     fn puts(s: *const i8);
+ }
+ 
+ fn main() -> i32 {
+     let arr = [0, 4, 5, 6, 1];
+     let a: &[i32] = &arr;
+     let mut ret = 1;
+ 
+     match a {
+         [1, .., b] => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         }
+         [0, .., 0] => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         },
+         [0, .., b] => {
+             ret -= b;
+             unsafe { puts("correct\0" as *const str as *const i8) }
+         },
+         _ => {}
+     }
+ 
+     ret
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-1.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,24 ----
+ // { dg-output "correct\r*" }
+ extern "C" {
+     fn puts(s: *const i8);
+ }
+ 
+ fn main() -> i32 {
+     struct A (i32, i32, i32);
+     let a = A (0, 1, 2);
+     let mut ret = 1;
+ 
+     match a {
+         A (1, ..) => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         }
+         A (0, b, ..) => { 
+             ret -= b;
+             unsafe { puts("correct\0" as *const str as *const i8) }
+         },
+         _ => {}
+     }
+ 
+     ret
+ }
diff -Nrcpad gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs
*** gcc-16-20251026/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/gcc/testsuite/rust/execute/torture/match-tuplestructpattern-rest-2.rs	Sun Nov  2 22:34:18 2025
***************
*** 0 ****
--- 1,28 ----
+ // { dg-output "correct\r*" }
+ extern "C" {
+     fn puts(s: *const i8);
+ }
+ 
+ fn main() -> i32 {
+     struct A (i32, i32, i32);
+     let a = A (0, 3, 1);
+     let mut ret = 1;
+ 
+     match a {
+         A (1, ..) => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         }
+         A (.., 3) => {
+             /* should not take this path */
+             unsafe { puts("wrong\0" as *const str as *const i8) }
+         }
+         A (.., b) => { 
+             ret -= b;
+             unsafe { puts("correct\0" as *const str as *const i8) }
+         },
+         _ => {}
+     }
+ 
+     ret
+ }
diff -Nrcpad gcc-16-20251026/gcc/tree-scalar-evolution.cc gcc-16-20251102/gcc/tree-scalar-evolution.cc
*** gcc-16-20251026/gcc/tree-scalar-evolution.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-scalar-evolution.cc	Sun Nov  2 22:34:18 2025
*************** final_value_replacement_loop (class loop
*** 3949,3959 ****
        auto loc = gimple_phi_arg_location (phi, exit->dest_idx);
        remove_phi_node (&psi, false);
  
-       /* Propagate constants immediately, but leave an unused initialization
- 	 around to avoid invalidating the SCEV cache.  */
-       if (CONSTANT_CLASS_P (def) && !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (rslt))
- 	replace_uses_by (rslt, def);
- 
        /* Create the replacement statements.  */
        gimple_seq stmts;
        def = force_gimple_operand (def, &stmts, false, NULL_TREE);
--- 3949,3954 ----
*************** final_value_replacement_loop (class loop
*** 3961,3966 ****
--- 3956,3966 ----
        gimple_set_location (ass, loc);
        gimple_seq_add_stmt (&stmts, ass);
  
+       /* Propagate constants immediately, but leave an unused initialization
+ 	 around to avoid invalidating the SCEV cache.  */
+       if (CONSTANT_CLASS_P (def) && !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (rslt))
+ 	replace_uses_by (rslt, def);
+ 
        /* If def's type has undefined overflow and there were folded
  	 casts, rewrite all stmts added for def into arithmetics
  	 with defined overflow behavior.  */
*************** final_value_replacement_loop (class loop
*** 3995,4005 ****
  	{
  	  gimple *use_stmt;
  	  imm_use_iterator imm_iter;
  	  FOR_EACH_IMM_USE_STMT (use_stmt, imm_iter, rslt)
  	    {
  	      gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt);
! 	      if (!stmt_can_throw_internal (cfun, use_stmt)
! 		  && fold_stmt (&gsi, follow_all_ssa_edges))
  		update_stmt (gsi_stmt (gsi));
  	    }
  	}
--- 3995,4011 ----
  	{
  	  gimple *use_stmt;
  	  imm_use_iterator imm_iter;
+ 	  auto_vec<gimple *, 4> to_fold;
  	  FOR_EACH_IMM_USE_STMT (use_stmt, imm_iter, rslt)
+ 	    if (!stmt_can_throw_internal (cfun, use_stmt))
+ 	      to_fold.safe_push (use_stmt);
+ 	  /* Delay folding until after the immediate use walk is completed
+ 	     as we have an active ranger and that might walk immediate
+ 	     uses of rslt again.  See PR122502.  */
+ 	  for (gimple *use_stmt : to_fold)
  	    {
  	      gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt);
! 	      if (fold_stmt (&gsi, follow_all_ssa_edges))
  		update_stmt (gsi_stmt (gsi));
  	    }
  	}
diff -Nrcpad gcc-16-20251026/gcc/tree-ssa-forwprop.cc gcc-16-20251102/gcc/tree-ssa-forwprop.cc
*** gcc-16-20251026/gcc/tree-ssa-forwprop.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-ssa-forwprop.cc	Sun Nov  2 22:34:18 2025
*************** do_simple_agr_dse (gassign *stmt, bool f
*** 1793,1798 ****
--- 1793,1799 ----
    /* Only handle clobbers of a full decl.  */
    if (!DECL_P (lhs))
      return;
+   clobber_kind kind = (clobber_kind)CLOBBER_KIND (gimple_assign_rhs1 (stmt));
    ao_ref_init (&read, lhs);
    tree vuse = gimple_vuse (stmt);
    unsigned limit = full_walk ? param_sccvn_max_alias_queries_per_access : 4;
*************** do_simple_agr_dse (gassign *stmt, bool f
*** 1814,1819 ****
--- 1815,1839 ----
  	  basic_block ubb = gimple_bb (use_stmt);
  	  if (stmt == use_stmt)
  	    continue;
+ 	  /* If the use is the same kind of clobber for lhs,
+ 	     then it can be safely skipped; this happens with eh
+ 	     and sometimes jump threading.  */
+ 	  if (gimple_clobber_p (use_stmt, kind)
+ 	      && lhs == gimple_assign_lhs (use_stmt))
+ 	    continue;
+ 	  /* If the use is a phi and it is single use then check if that single use
+ 	     is a clobber of the same kind and lhs is the same.  */
+ 	  if (gphi *use_phi = dyn_cast<gphi*>(use_stmt))
+ 	    {
+ 	      use_operand_p ou;
+ 	      gimple *ostmt;
+ 	      if (single_imm_use (gimple_phi_result (use_phi), &ou, &ostmt)
+ 		  && gimple_clobber_p (ostmt, kind)
+ 	          && lhs == gimple_assign_lhs (ostmt))
+ 		continue;
+ 	      /* A phi node will never be dominating the clobber.  */
+ 	      return;
+ 	    }
  	  /* The use needs to be dominating the clobber. */
  	  if ((ubb != bb && !dominated_by_p (CDI_DOMINATORS, bb, ubb))
  	      || ref_maybe_used_by_stmt_p (use_stmt, &read, false))
diff -Nrcpad gcc-16-20251026/gcc/tree-ssa-loop-niter.cc gcc-16-20251102/gcc/tree-ssa-loop-niter.cc
*** gcc-16-20251026/gcc/tree-ssa-loop-niter.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-ssa-loop-niter.cc	Sun Nov  2 22:34:18 2025
*************** is_rshift_by_1 (gassign *stmt)
*** 2321,2326 ****
--- 2321,2368 ----
    return false;
  }
  
+ /* Helper for number_of_iterations_cltz that uses ranger to determine
+    if SRC's range, shifted left (when LEFT_SHIFT is true) or right
+    by NUM_IGNORED_BITS, is guaranteed to be != 0 on LOOP's preheader
+    edge.
+    Return true if so or false otherwise.  */
+ 
+ static bool
+ shifted_range_nonzero_p (loop_p loop, tree src,
+ 			 bool left_shift, int num_ignored_bits)
+ {
+   int_range_max r (TREE_TYPE (src));
+   gcc_assert (num_ignored_bits >= 0);
+ 
+   if (get_range_query (cfun)->range_on_edge
+       (r, loop_preheader_edge (loop), src)
+       && !r.varying_p ()
+       && !r.undefined_p ())
+     {
+       if (num_ignored_bits)
+ 	{
+ 	  range_op_handler op (left_shift ? LSHIFT_EXPR : RSHIFT_EXPR);
+ 	  int_range_max shifted_range (TREE_TYPE (src));
+ 	  wide_int shift_count = wi::shwi (num_ignored_bits,
+ 					   TYPE_PRECISION (TREE_TYPE
+ 							   (src)));
+ 	  int_range_max shift_amount
+ 	    (TREE_TYPE (src), shift_count, shift_count);
+ 
+ 	  if (op.fold_range (shifted_range, TREE_TYPE (src), r,
+ 			     shift_amount))
+ 	    r = shifted_range;
+ 	}
+ 
+       /* If the range does not contain zero we are good.  */
+       if (!range_includes_zero_p (r))
+ 	return true;
+     }
+ 
+   return false;
+ }
+ 
+ 
  /* See comment below for number_of_iterations_bitcount.
     For c[lt]z, we have:
  
*************** number_of_iterations_cltz (loop_p loop,
*** 2438,2443 ****
--- 2480,2488 ----
    tree src = gimple_phi_arg_def (phi, loop_preheader_edge (loop)->dest_idx);
    int src_precision = TYPE_PRECISION (TREE_TYPE (src));
  
+   /* Save the original SSA name before preprocessing for ranger queries.  */
+   tree unshifted_src = src;
+ 
    /* Apply any needed preprocessing to src.  */
    int num_ignored_bits;
    if (left_shift)
*************** number_of_iterations_cltz (loop_p loop,
*** 2463,2472 ****
  
    expr = fold_convert (unsigned_type_node, expr);
  
!   tree assumptions = fold_build2 (NE_EXPR, boolean_type_node, src,
! 				  build_zero_cst (TREE_TYPE (src)));
  
!   niter->assumptions = simplify_using_initial_conditions (loop, assumptions);
    niter->may_be_zero = boolean_false_node;
    niter->niter = simplify_using_initial_conditions (loop, expr);
  
--- 2508,2559 ----
  
    expr = fold_convert (unsigned_type_node, expr);
  
!   /* If the copy-header (ch) pass peeled one iteration we're shifting
!      SRC by preprocessing it above.
  
!      A loop like
!       if (bits)
! 	{
! 	  while (!(bits & 1))
! 	    {
! 	      bits >>= 1;
! 	      cnt += 1;
! 	    }
! 	  return cnt;
! 	}
!      ch (roughly) transforms into:
!       if (bits)
! 	{
! 	  if (!(bits & 1)
! 	    {
! 	      do
! 		{
! 		  bits >>= 1;
! 		  cnt += 1;
! 		} while (!(bits & 1));
! 	    }
! 	   else
! 	     cnt = 1;
! 	  return cnt;
! 	}
! 
!      Then, our preprocessed SRC (that is used for c[tl]z computation)
!      will be bits >> 1, and the assumption is bits >> 1 != 0.  */
! 
!   tree assumptions;
!   if (shifted_range_nonzero_p (loop, unshifted_src,
! 			       left_shift, num_ignored_bits))
!     assumptions = boolean_true_node;
!   else
!     {
!       /* If ranger couldn't prove the assumption, try
! 	 simplify_using_initial_conditions.  */
!       assumptions = fold_build2 (NE_EXPR, boolean_type_node, src,
! 				 build_zero_cst (TREE_TYPE (src)));
!       assumptions = simplify_using_initial_conditions (loop, assumptions);
!     }
! 
!   niter->assumptions = assumptions;
    niter->may_be_zero = boolean_false_node;
    niter->niter = simplify_using_initial_conditions (loop, expr);
  
diff -Nrcpad gcc-16-20251026/gcc/tree-ssa-loop.cc gcc-16-20251102/gcc/tree-ssa-loop.cc
*** gcc-16-20251026/gcc/tree-ssa-loop.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-ssa-loop.cc	Sun Nov  2 22:34:18 2025
*************** along with GCC; see the file COPYING3.
*** 28,33 ****
--- 28,34 ----
  #include "tm_p.h"
  #include "fold-const.h"
  #include "gimple-iterator.h"
+ #include "gimple-range.h"
  #include "tree-ssa-loop-ivopts.h"
  #include "tree-ssa-loop-manip.h"
  #include "tree-ssa-loop-niter.h"
*************** pass_scev_cprop::execute (function *)
*** 404,414 ****
--- 405,419 ----
  {
    bool any = false;
  
+   enable_ranger (cfun);
+ 
    /* Perform final value replacement in loops, in case the replacement
       expressions are cheap.  */
    for (auto loop : loops_list (cfun, LI_FROM_INNERMOST))
      any |= final_value_replacement_loop (loop);
  
+   disable_ranger (cfun);
+ 
    return any ? TODO_cleanup_cfg | TODO_update_ssa_only_virtuals : 0;
  }
  
diff -Nrcpad gcc-16-20251026/gcc/tree-ssa-sccvn.cc gcc-16-20251102/gcc/tree-ssa-sccvn.cc
*** gcc-16-20251026/gcc/tree-ssa-sccvn.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-ssa-sccvn.cc	Sun Nov  2 22:34:18 2025
*************** eliminate_dom_walker::eliminate_stmt (ba
*** 7356,7368 ****
  	  else
  	    lookup_lhs = NULL_TREE;
  	}
!       tree val = NULL_TREE;
        if (lookup_lhs)
  	val = vn_reference_lookup (lookup_lhs, gimple_vuse (stmt),
  				   VN_WALKREWRITE, &vnresult, false,
  				   NULL, NULL_TREE, true);
        if (TREE_CODE (rhs) == SSA_NAME)
  	rhs = VN_INFO (rhs)->valnum;
        if (val
  	  && (operand_equal_p (val, rhs, 0)
  	      /* Due to the bitfield lookups above we can get bit
--- 7356,7369 ----
  	  else
  	    lookup_lhs = NULL_TREE;
  	}
!       tree val = NULL_TREE, tem;
        if (lookup_lhs)
  	val = vn_reference_lookup (lookup_lhs, gimple_vuse (stmt),
  				   VN_WALKREWRITE, &vnresult, false,
  				   NULL, NULL_TREE, true);
        if (TREE_CODE (rhs) == SSA_NAME)
  	rhs = VN_INFO (rhs)->valnum;
+       gassign *ass;
        if (val
  	  && (operand_equal_p (val, rhs, 0)
  	      /* Due to the bitfield lookups above we can get bit
*************** eliminate_dom_walker::eliminate_stmt (ba
*** 7370,7378 ****
  		 are redundant as well.  */
  	      || (TREE_CODE (val) == SSA_NAME
  		  && gimple_assign_single_p (SSA_NAME_DEF_STMT (val))
! 		  && (val = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (val)))
! 		  && TREE_CODE (val) == VIEW_CONVERT_EXPR
! 		  && TREE_OPERAND (val, 0) == rhs)))
  	{
  	  /* We can only remove the later store if the former aliases
  	     at least all accesses the later one does or if the store
--- 7371,7384 ----
  		 are redundant as well.  */
  	      || (TREE_CODE (val) == SSA_NAME
  		  && gimple_assign_single_p (SSA_NAME_DEF_STMT (val))
! 		  && (tem = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (val)))
! 		  && TREE_CODE (tem) == VIEW_CONVERT_EXPR
! 		  && TREE_OPERAND (tem, 0) == rhs)
! 	      || (TREE_CODE (rhs) == SSA_NAME
! 		  && (ass = dyn_cast <gassign *> (SSA_NAME_DEF_STMT (rhs)))
! 		  && gimple_assign_rhs1 (ass) == val
! 		  && CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (ass))
! 		  && tree_nop_conversion_p (TREE_TYPE (rhs), TREE_TYPE (val)))))
  	{
  	  /* We can only remove the later store if the former aliases
  	     at least all accesses the later one does or if the store
diff -Nrcpad gcc-16-20251026/gcc/tree-ssanames.cc gcc-16-20251102/gcc/tree-ssanames.cc
*** gcc-16-20251026/gcc/tree-ssanames.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-ssanames.cc	Sun Nov  2 22:34:18 2025
*************** get_known_nonzero_bits (const_tree name)
*** 611,625 ****
    return get_known_nonzero_bits_1 (name);
  }
  
! /* Return TRUE is OP, an SSA_NAME has a range of values [0..1], false
!    otherwise.
  
     This can be because it is a boolean type, any unsigned integral
     type with a single bit of precision, or has known range of [0..1]
     via range analysis.  */
  
  bool
! ssa_name_has_boolean_range (tree op)
  {
    gcc_assert (TREE_CODE (op) == SSA_NAME);
  
--- 611,625 ----
    return get_known_nonzero_bits_1 (name);
  }
  
! /* Return TRUE is OP, an SSA_NAME has a range of values [0..1] at the
!    STMT, false otherwise.
  
     This can be because it is a boolean type, any unsigned integral
     type with a single bit of precision, or has known range of [0..1]
     via range analysis.  */
  
  bool
! ssa_name_has_boolean_range (tree op, gimple *stmt)
  {
    gcc_assert (TREE_CODE (op) == SSA_NAME);
  
*************** ssa_name_has_boolean_range (tree op)
*** 636,642 ****
        && (TYPE_PRECISION (TREE_TYPE (op)) > 1))
      {
        int_range<2> r;
!       if (get_range_query (cfun)->range_of_expr (r, op)
  	  && r == range_true_and_false (TREE_TYPE (op)))
  	return true;
  
--- 636,642 ----
        && (TYPE_PRECISION (TREE_TYPE (op)) > 1))
      {
        int_range<2> r;
!       if (get_range_query (cfun)->range_of_expr (r, op, stmt)
  	  && r == range_true_and_false (TREE_TYPE (op)))
  	return true;
  
diff -Nrcpad gcc-16-20251026/gcc/tree-ssanames.h gcc-16-20251102/gcc/tree-ssanames.h
*** gcc-16-20251026/gcc/tree-ssanames.h	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-ssanames.h	Sun Nov  2 22:34:18 2025
*************** extern void set_nonzero_bits (tree, cons
*** 62,68 ****
  extern void set_bitmask (tree, const wide_int &value, const wide_int &mask);
  extern wide_int get_nonzero_bits (const_tree);
  extern wide_int get_known_nonzero_bits (const_tree);
! extern bool ssa_name_has_boolean_range (tree);
  extern void init_ssanames (struct function *, int);
  extern void fini_ssanames (struct function *);
  extern void ssanames_print_statistics (void);
--- 62,68 ----
  extern void set_bitmask (tree, const wide_int &value, const wide_int &mask);
  extern wide_int get_nonzero_bits (const_tree);
  extern wide_int get_known_nonzero_bits (const_tree);
! extern bool ssa_name_has_boolean_range (tree, gimple * = nullptr);
  extern void init_ssanames (struct function *, int);
  extern void fini_ssanames (struct function *);
  extern void ssanames_print_statistics (void);
diff -Nrcpad gcc-16-20251026/gcc/tree-vect-generic.cc gcc-16-20251102/gcc/tree-vect-generic.cc
*** gcc-16-20251026/gcc/tree-vect-generic.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-vect-generic.cc	Sun Nov  2 22:34:18 2025
*************** expand_vector_comparison (gimple_stmt_it
*** 460,466 ****
     of OP0 with shift counts in SHIFTCNTS array and return the temporary holding
     the result if successful, otherwise return NULL_TREE.  */
  static tree
! add_rshift (gimple_stmt_iterator *gsi, tree type, tree op0, int *shiftcnts)
  {
    optab op;
    unsigned int i, nunits = nunits_for_known_piecewise_op (type);
--- 460,467 ----
     of OP0 with shift counts in SHIFTCNTS array and return the temporary holding
     the result if successful, otherwise return NULL_TREE.  */
  static tree
! add_shift (gimple_stmt_iterator *gsi, tree type, tree op0, int *shiftcnts,
! 	   enum tree_code code)
  {
    optab op;
    unsigned int i, nunits = nunits_for_known_piecewise_op (type);
*************** add_rshift (gimple_stmt_iterator *gsi, t
*** 477,502 ****
  
    if (scalar_shift)
      {
!       op = optab_for_tree_code (RSHIFT_EXPR, type, optab_scalar);
        if (op != unknown_optab
  	  && can_implement_p (op, TYPE_MODE (type)))
! 	return gimplify_build2 (gsi, RSHIFT_EXPR, type, op0,
  				build_int_cst (NULL_TREE, shiftcnts[0]));
      }
  
!   op = optab_for_tree_code (RSHIFT_EXPR, type, optab_vector);
    if (op != unknown_optab
        && can_implement_p (op, TYPE_MODE (type)))
      {
        tree_vector_builder vec (type, nunits, 1);
        for (i = 0; i < nunits; i++)
  	vec.quick_push (build_int_cst (TREE_TYPE (type), shiftcnts[i]));
!       return gimplify_build2 (gsi, RSHIFT_EXPR, type, op0, vec.build ());
      }
  
    return NULL_TREE;
  }
  
  /* Try to expand integer vector division by constant using
     widening multiply, shifts and additions.  */
  static tree
--- 478,524 ----
  
    if (scalar_shift)
      {
!       op = optab_for_tree_code (code, type, optab_scalar);
        if (op != unknown_optab
  	  && can_implement_p (op, TYPE_MODE (type)))
! 	return gimplify_build2 (gsi, code, type, op0,
  				build_int_cst (NULL_TREE, shiftcnts[0]));
      }
  
!   op = optab_for_tree_code (code, type, optab_vector);
    if (op != unknown_optab
        && can_implement_p (op, TYPE_MODE (type)))
      {
        tree_vector_builder vec (type, nunits, 1);
        for (i = 0; i < nunits; i++)
  	vec.quick_push (build_int_cst (TREE_TYPE (type), shiftcnts[i]));
!       return gimplify_build2 (gsi, code, type, op0, vec.build ());
      }
  
    return NULL_TREE;
  }
+ /* Try to expand integer vector multiplication by constant of power 2 using
+    left shifts.  */
+ static tree
+ expand_vector_mult (gimple_stmt_iterator *gsi, tree type, tree op0,
+ 		    tree op1)
+ {
+   unsigned int nunits = nunits_for_known_piecewise_op (type);
+   int *shifts = XALLOCAVEC (int, nunits);
+ 
+   // if all element are same value and a power of 2, then we can use shifts
+   for (unsigned int i = 0; i < nunits; i++)
+     {
+       tree cst = VECTOR_CST_ELT (op1, i);
+       if ((TREE_CODE (cst) != INTEGER_CST || integer_zerop (cst))
+ 	  || !integer_pow2p (cst) || tree_int_cst_sgn (cst) != 1)
+ 	return NULL_TREE;
  
+       shifts[i] = tree_log2 (cst);
+     }
+   tree cur_op = add_shift (gsi, type, op0, shifts, LSHIFT_EXPR);
+   return cur_op;
+ }
  /* Try to expand integer vector division by constant using
     widening multiply, shifts and additions.  */
  static tree
*************** expand_vector_divmod (gimple_stmt_iterat
*** 705,718 ****
  	    {
  	      for (i = 0; i < nunits; i++)
  		shift_temps[i] = prec - 1;
! 	      cur_op = add_rshift (gsi, type, op0, shift_temps);
  	      if (cur_op != NULL_TREE)
  		{
  		  cur_op = gimplify_build1 (gsi, VIEW_CONVERT_EXPR,
  					    uns_type, cur_op);
  		  for (i = 0; i < nunits; i++)
  		    shift_temps[i] = prec - shifts[i];
! 		  cur_op = add_rshift (gsi, uns_type, cur_op, shift_temps);
  		  if (cur_op != NULL_TREE)
  		    addend = gimplify_build1 (gsi, VIEW_CONVERT_EXPR,
  					      type, cur_op);
--- 727,741 ----
  	    {
  	      for (i = 0; i < nunits; i++)
  		shift_temps[i] = prec - 1;
! 	      cur_op = add_shift (gsi, type, op0, shift_temps, RSHIFT_EXPR);
  	      if (cur_op != NULL_TREE)
  		{
  		  cur_op = gimplify_build1 (gsi, VIEW_CONVERT_EXPR,
  					    uns_type, cur_op);
  		  for (i = 0; i < nunits; i++)
  		    shift_temps[i] = prec - shifts[i];
! 		  cur_op = add_shift (gsi, uns_type, cur_op, shift_temps,
! 				      RSHIFT_EXPR);
  		  if (cur_op != NULL_TREE)
  		    addend = gimplify_build1 (gsi, VIEW_CONVERT_EXPR,
  					      type, cur_op);
*************** expand_vector_divmod (gimple_stmt_iterat
*** 748,754 ****
  	  if (sign_p == UNSIGNED)
  	    {
  	      /* q = op0 >> shift;  */
! 	      cur_op = add_rshift (gsi, type, op0, shifts);
  	      if (cur_op != NULL_TREE)
  		return cur_op;
  	    }
--- 771,777 ----
  	  if (sign_p == UNSIGNED)
  	    {
  	      /* q = op0 >> shift;  */
! 	      cur_op = add_shift (gsi, type, op0, shifts, RSHIFT_EXPR);
  	      if (cur_op != NULL_TREE)
  		return cur_op;
  	    }
*************** expand_vector_divmod (gimple_stmt_iterat
*** 761,767 ****
  		  && can_implement_p (op, TYPE_MODE (type)))
  		{
  		  cur_op = gimplify_build2 (gsi, PLUS_EXPR, type, op0, addend);
! 		  cur_op = add_rshift (gsi, type, cur_op, shifts);
  		  if (cur_op != NULL_TREE)
  		    return cur_op;
  		}
--- 784,790 ----
  		  && can_implement_p (op, TYPE_MODE (type)))
  		{
  		  cur_op = gimplify_build2 (gsi, PLUS_EXPR, type, op0, addend);
! 		  cur_op = add_shift (gsi, type, cur_op, shifts, RSHIFT_EXPR);
  		  if (cur_op != NULL_TREE)
  		    return cur_op;
  		}
*************** expand_vector_divmod (gimple_stmt_iterat
*** 823,829 ****
        /* t1 = oprnd0 >> pre_shift;
  	 t2 = t1 h* ml;
  	 q = t2 >> post_shift;  */
!       cur_op = add_rshift (gsi, type, cur_op, pre_shifts);
        if (cur_op == NULL_TREE)
  	return NULL_TREE;
        break;
--- 846,852 ----
        /* t1 = oprnd0 >> pre_shift;
  	 t2 = t1 h* ml;
  	 q = t2 >> post_shift;  */
!       cur_op = add_shift (gsi, type, cur_op, pre_shifts, RSHIFT_EXPR);
        if (cur_op == NULL_TREE)
  	return NULL_TREE;
        break;
*************** expand_vector_divmod (gimple_stmt_iterat
*** 860,866 ****
        /* t1 = oprnd0 >> pre_shift;
  	 t2 = t1 h* ml;
  	 q = t2 >> post_shift;  */
!       cur_op = add_rshift (gsi, type, cur_op, post_shifts);
        break;
      case 1:
        /* t1 = oprnd0 h* ml;
--- 883,889 ----
        /* t1 = oprnd0 >> pre_shift;
  	 t2 = t1 h* ml;
  	 q = t2 >> post_shift;  */
!       cur_op = add_shift (gsi, type, cur_op, post_shifts, RSHIFT_EXPR);
        break;
      case 1:
        /* t1 = oprnd0 h* ml;
*************** expand_vector_divmod (gimple_stmt_iterat
*** 873,885 ****
  	  || !can_implement_p (op, TYPE_MODE (type)))
  	return NULL_TREE;
        tem = gimplify_build2 (gsi, MINUS_EXPR, type, op0, cur_op);
!       tem = add_rshift (gsi, type, tem, shift_temps);
        op = optab_for_tree_code (PLUS_EXPR, type, optab_default);
        if (op == unknown_optab
  	  || !can_implement_p (op, TYPE_MODE (type)))
  	return NULL_TREE;
        tem = gimplify_build2 (gsi, PLUS_EXPR, type, cur_op, tem);
!       cur_op = add_rshift (gsi, type, tem, post_shifts);
        if (cur_op == NULL_TREE)
  	return NULL_TREE;
        break;
--- 896,908 ----
  	  || !can_implement_p (op, TYPE_MODE (type)))
  	return NULL_TREE;
        tem = gimplify_build2 (gsi, MINUS_EXPR, type, op0, cur_op);
!       tem = add_shift (gsi, type, tem, shift_temps, RSHIFT_EXPR);
        op = optab_for_tree_code (PLUS_EXPR, type, optab_default);
        if (op == unknown_optab
  	  || !can_implement_p (op, TYPE_MODE (type)))
  	return NULL_TREE;
        tem = gimplify_build2 (gsi, PLUS_EXPR, type, cur_op, tem);
!       cur_op = add_shift (gsi, type, tem, post_shifts, RSHIFT_EXPR);
        if (cur_op == NULL_TREE)
  	return NULL_TREE;
        break;
*************** expand_vector_divmod (gimple_stmt_iterat
*** 902,911 ****
  	    return NULL_TREE;
  	  cur_op = gimplify_build2 (gsi, PLUS_EXPR, type, cur_op, op0);
  	}
!       cur_op = add_rshift (gsi, type, cur_op, post_shifts);
        if (cur_op == NULL_TREE)
  	return NULL_TREE;
!       tem = add_rshift (gsi, type, op0, shift_temps);
        if (tem == NULL_TREE)
  	return NULL_TREE;
        op = optab_for_tree_code (MINUS_EXPR, type, optab_default);
--- 925,934 ----
  	    return NULL_TREE;
  	  cur_op = gimplify_build2 (gsi, PLUS_EXPR, type, cur_op, op0);
  	}
!       cur_op = add_shift (gsi, type, cur_op, post_shifts, RSHIFT_EXPR);
        if (cur_op == NULL_TREE)
  	return NULL_TREE;
!       tem = add_shift (gsi, type, op0, shift_temps, RSHIFT_EXPR);
        if (tem == NULL_TREE)
  	return NULL_TREE;
        op = optab_for_tree_code (MINUS_EXPR, type, optab_default);
*************** expand_vector_operation (gimple_stmt_ite
*** 1146,1152 ****
--- 1169,1191 ----
  	    return ret;
  	  break;
  	}
+       case MULT_EXPR:
+ 	{
+ 	  tree rhs1 = gimple_assign_rhs1 (assign);
+ 	  tree rhs2 = gimple_assign_rhs2 (assign);
+ 	  tree ret;
  
+ 	  if (!optimize
+ 	      || !VECTOR_INTEGER_TYPE_P (type)
+ 	      || TREE_CODE (rhs2) != VECTOR_CST
+ 	      || !VECTOR_MODE_P (TYPE_MODE (type)))
+ 	    break;
+ 
+ 	  ret = expand_vector_mult (gsi, type, rhs1, rhs2);
+ 	  if (ret != NULL_TREE)
+ 	    return ret;
+ 	  break;
+ 	}
        default:
  	break;
        }
diff -Nrcpad gcc-16-20251026/gcc/tree-vect-loop-manip.cc gcc-16-20251102/gcc/tree-vect-loop-manip.cc
*** gcc-16-20251026/gcc/tree-vect-loop-manip.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-vect-loop-manip.cc	Sun Nov  2 22:34:18 2025
*************** vect_update_ivs_after_vectorizer (loop_v
*** 2336,2342 ****
    gphi_iterator gsi, gsi1;
    class loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
    basic_block update_bb = update_e->dest;
!   basic_block exit_bb = LOOP_VINFO_IV_EXIT (loop_vinfo)->dest;
    gimple_stmt_iterator last_gsi = gsi_last_bb (exit_bb);
  
    for (gsi = gsi_start_phis (loop->header), gsi1 = gsi_start_phis (update_bb);
--- 2336,2342 ----
    gphi_iterator gsi, gsi1;
    class loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
    basic_block update_bb = update_e->dest;
!   basic_block exit_bb = update_e->src;
    gimple_stmt_iterator last_gsi = gsi_last_bb (exit_bb);
  
    for (gsi = gsi_start_phis (loop->header), gsi1 = gsi_start_phis (update_bb);
diff -Nrcpad gcc-16-20251026/gcc/tree-vect-slp-patterns.cc gcc-16-20251102/gcc/tree-vect-slp-patterns.cc
*** gcc-16-20251026/gcc/tree-vect-slp-patterns.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-vect-slp-patterns.cc	Sun Nov  2 22:34:18 2025
*************** compatible_complex_nodes_p (slp_compat_n
*** 852,866 ****
    return true;
  }
  
  static inline bool
  vect_validate_multiplication (slp_tree_to_load_perm_map_t *perm_cache,
  			      slp_compat_nodes_map_t *compat_cache,
! 			      vec<slp_tree> &left_op,
! 			      vec<slp_tree> &right_op,
! 			      bool subtract,
  			      enum _conj_status *_status)
  {
-   auto_vec<slp_tree> ops;
    enum _conj_status stats = CONJ_NONE;
  
    /* The complex operations can occur in two layouts and two permute sequences
--- 852,874 ----
    return true;
  }
  
+ 
+ /* Check to see if the oprands to two multiplies, 2 each in LEFT_OP and
+    RIGHT_OP match a complex multiplication  or complex multiply-and-accumulate
+    or complex multiply-and-subtract pattern.  Do this using the permute cache
+    PERM_CACHE and the combination compatibility list COMPAT_CACHE.  If
+    the operation is successful the macthing operands are returned in OPS and
+    _STATUS indicates if the operation matched includes a conjugate of one of the
+    operands.  If the operation succeeds True is returned, otherwise False and
+    the values in ops are meaningless.  */
  static inline bool
  vect_validate_multiplication (slp_tree_to_load_perm_map_t *perm_cache,
  			      slp_compat_nodes_map_t *compat_cache,
! 			      const vec<slp_tree> &left_op,
! 			      const vec<slp_tree> &right_op,
! 			      bool subtract, vec<slp_tree> &ops,
  			      enum _conj_status *_status)
  {
    enum _conj_status stats = CONJ_NONE;
  
    /* The complex operations can occur in two layouts and two permute sequences
*************** vect_validate_multiplication (slp_tree_t
*** 891,921 ****
    bool neg0 = vect_match_expression_p (right_op[0], NEGATE_EXPR);
    bool neg1 = vect_match_expression_p (right_op[1], NEGATE_EXPR);
  
    /* Determine which style we're looking at.  We only have different ones
       whenever a conjugate is involved.  */
    if (neg0 && neg1)
      ;
    else if (neg0)
      {
!       right_op[0] = SLP_TREE_CHILDREN (right_op[0])[0];
        stats = CONJ_FST;
        if (subtract)
  	perm = 0;
      }
    else if (neg1)
      {
!       right_op[1] = SLP_TREE_CHILDREN (right_op[1])[0];
        stats = CONJ_SND;
        perm = 1;
      }
  
    *_status = stats;
  
-   /* Flatten the inputs after we've remapped them.  */
-   ops.create (4);
-   ops.safe_splice (left_op);
-   ops.safe_splice (right_op);
- 
    /* Extract out the elements to check.  */
    slp_tree op0 = ops[styles[style][0]];
    slp_tree op1 = ops[styles[style][1]];
--- 899,929 ----
    bool neg0 = vect_match_expression_p (right_op[0], NEGATE_EXPR);
    bool neg1 = vect_match_expression_p (right_op[1], NEGATE_EXPR);
  
+   /* Create the combined inputs after remapping and flattening.  */
+   ops.create (4);
+   ops.safe_splice (left_op);
+   ops.safe_splice (right_op);
+ 
    /* Determine which style we're looking at.  We only have different ones
       whenever a conjugate is involved.  */
    if (neg0 && neg1)
      ;
    else if (neg0)
      {
!       ops[2] = SLP_TREE_CHILDREN (right_op[0])[0];
        stats = CONJ_FST;
        if (subtract)
  	perm = 0;
      }
    else if (neg1)
      {
!       ops[3] = SLP_TREE_CHILDREN (right_op[1])[0];
        stats = CONJ_SND;
        perm = 1;
      }
  
    *_status = stats;
  
    /* Extract out the elements to check.  */
    slp_tree op0 = ops[styles[style][0]];
    slp_tree op1 = ops[styles[style][1]];
*************** complex_mul_pattern::matches (complex_op
*** 1078,1092 ****
      return IFN_LAST;
  
    enum _conj_status status;
    if (!vect_validate_multiplication (perm_cache, compat_cache, left_op,
! 				     right_op, false, &status))
      {
        /* Try swapping the order and re-trying since multiplication is
  	 commutative.  */
        std::swap (left_op[0], left_op[1]);
        std::swap (right_op[0], right_op[1]);
        if (!vect_validate_multiplication (perm_cache, compat_cache, left_op,
! 					 right_op, false, &status))
  	return IFN_LAST;
      }
  
--- 1086,1101 ----
      return IFN_LAST;
  
    enum _conj_status status;
+   auto_vec<slp_tree> res_ops;
    if (!vect_validate_multiplication (perm_cache, compat_cache, left_op,
! 				     right_op, false, res_ops, &status))
      {
        /* Try swapping the order and re-trying since multiplication is
  	 commutative.  */
        std::swap (left_op[0], left_op[1]);
        std::swap (right_op[0], right_op[1]);
        if (!vect_validate_multiplication (perm_cache, compat_cache, left_op,
! 					 right_op, false, res_ops, &status))
  	return IFN_LAST;
      }
  
*************** complex_mul_pattern::matches (complex_op
*** 1114,1137 ****
    if (add0)
      ops->quick_push (add0);
  
!   complex_perm_kinds_t kind = linear_loads_p (perm_cache, left_op[0]);
    if (kind == PERM_EVENODD || kind == PERM_TOP)
      {
!       ops->quick_push (left_op[1]);
!       ops->quick_push (right_op[1]);
!       ops->quick_push (left_op[0]);
      }
    else if (kind == PERM_EVENEVEN && status != CONJ_SND)
      {
!       ops->quick_push (left_op[0]);
!       ops->quick_push (right_op[0]);
!       ops->quick_push (left_op[1]);
      }
    else
      {
!       ops->quick_push (left_op[0]);
!       ops->quick_push (right_op[1]);
!       ops->quick_push (left_op[1]);
      }
  
    return ifn;
--- 1123,1146 ----
    if (add0)
      ops->quick_push (add0);
  
!   complex_perm_kinds_t kind = linear_loads_p (perm_cache, res_ops[0]);
    if (kind == PERM_EVENODD || kind == PERM_TOP)
      {
!       ops->quick_push (res_ops[1]);
!       ops->quick_push (res_ops[3]);
!       ops->quick_push (res_ops[0]);
      }
    else if (kind == PERM_EVENEVEN && status != CONJ_SND)
      {
!       ops->quick_push (res_ops[0]);
!       ops->quick_push (res_ops[2]);
!       ops->quick_push (res_ops[1]);
      }
    else
      {
!       ops->quick_push (res_ops[0]);
!       ops->quick_push (res_ops[3]);
!       ops->quick_push (res_ops[1]);
      }
  
    return ifn;
*************** complex_fms_pattern::matches (complex_op
*** 1303,1317 ****
      return IFN_LAST;
  
    enum _conj_status status;
    if (!vect_validate_multiplication (perm_cache, compat_cache, right_op,
! 				     left_op, true, &status))
      {
        /* Try swapping the order and re-trying since multiplication is
  	 commutative.  */
        std::swap (left_op[0], left_op[1]);
        std::swap (right_op[0], right_op[1]);
        if (!vect_validate_multiplication (perm_cache, compat_cache, right_op,
! 					 left_op, true, &status))
  	return IFN_LAST;
      }
  
--- 1312,1328 ----
      return IFN_LAST;
  
    enum _conj_status status;
+   auto_vec<slp_tree> res_ops;
    if (!vect_validate_multiplication (perm_cache, compat_cache, right_op,
! 				     left_op, true, res_ops, &status))
      {
        /* Try swapping the order and re-trying since multiplication is
  	 commutative.  */
        std::swap (left_op[0], left_op[1]);
        std::swap (right_op[0], right_op[1]);
+       auto_vec<slp_tree> res_ops;
        if (!vect_validate_multiplication (perm_cache, compat_cache, right_op,
! 					 left_op, true, res_ops, &status))
  	return IFN_LAST;
      }
  
*************** complex_fms_pattern::matches (complex_op
*** 1326,1345 ****
    ops->truncate (0);
    ops->create (4);
  
!   complex_perm_kinds_t kind = linear_loads_p (perm_cache, right_op[0]);
    if (kind == PERM_EVENODD)
      {
        ops->quick_push (l0node[0]);
!       ops->quick_push (right_op[0]);
!       ops->quick_push (right_op[1]);
!       ops->quick_push (left_op[1]);
      }
    else
      {
        ops->quick_push (l0node[0]);
!       ops->quick_push (right_op[1]);
!       ops->quick_push (right_op[0]);
!       ops->quick_push (left_op[0]);
      }
  
    return ifn;
--- 1337,1356 ----
    ops->truncate (0);
    ops->create (4);
  
!   complex_perm_kinds_t kind = linear_loads_p (perm_cache, res_ops[2]);
    if (kind == PERM_EVENODD)
      {
        ops->quick_push (l0node[0]);
!       ops->quick_push (res_ops[2]);
!       ops->quick_push (res_ops[3]);
!       ops->quick_push (res_ops[1]);
      }
    else
      {
        ops->quick_push (l0node[0]);
!       ops->quick_push (res_ops[3]);
!       ops->quick_push (res_ops[2]);
!       ops->quick_push (res_ops[0]);
      }
  
    return ifn;
diff -Nrcpad gcc-16-20251026/gcc/tree-vect-slp.cc gcc-16-20251102/gcc/tree-vect-slp.cc
*** gcc-16-20251026/gcc/tree-vect-slp.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/tree-vect-slp.cc	Sun Nov  2 22:34:18 2025
*************** vect_get_operand_map (const gimple *stmt
*** 558,564 ****
        if (gimple_assign_rhs_code (assign) == COND_EXPR
  	  && COMPARISON_CLASS_P (gimple_assign_rhs1 (assign)))
  	gcc_unreachable ();
!       if (TREE_CODE_CLASS (gimple_assign_rhs_code (assign)) == tcc_comparison
  	  && swap)
  	return op1_op0_map;
        if (gather_scatter_p)
--- 558,565 ----
        if (gimple_assign_rhs_code (assign) == COND_EXPR
  	  && COMPARISON_CLASS_P (gimple_assign_rhs1 (assign)))
  	gcc_unreachable ();
!       if ((TREE_CODE_CLASS (gimple_assign_rhs_code (assign)) == tcc_comparison
! 	   || commutative_tree_code (gimple_assign_rhs_code (assign)))
  	  && swap)
  	return op1_op0_map;
        if (gather_scatter_p)
*************** vect_build_slp_tree_1 (vec_info *vinfo,
*** 1352,1358 ****
  		 uniform but only that of the first stmt matters.  */
  	      && !(first_reduc_idx != -1
  		   && STMT_VINFO_REDUC_IDX (stmt_info) != -1
! 		   && REDUC_GROUP_FIRST_ELEMENT (stmt_info)))
  	    {
  	      if (dump_enabled_p ())
  		{
--- 1353,1364 ----
  		 uniform but only that of the first stmt matters.  */
  	      && !(first_reduc_idx != -1
  		   && STMT_VINFO_REDUC_IDX (stmt_info) != -1
! 		   && REDUC_GROUP_FIRST_ELEMENT (stmt_info))
! 	      && !(first_reduc_idx != -1
! 		   && STMT_VINFO_REDUC_IDX (stmt_info) != -1
! 		   && rhs_code.is_tree_code ()
! 		   && commutative_tree_code (tree_code (rhs_code))
! 		   && first_reduc_idx == 1 - STMT_VINFO_REDUC_IDX (stmt_info)))
  	    {
  	      if (dump_enabled_p ())
  		{
*************** vect_build_slp_tree_1 (vec_info *vinfo,
*** 1617,1622 ****
--- 1623,1637 ----
  	      && (swap_tree_comparison ((tree_code)first_stmt_code)
  		  == (tree_code)rhs_code))
  	    swap[i] = 1;
+ 
+ 	  if (i != 0
+ 	      && first_reduc_idx != STMT_VINFO_REDUC_IDX (stmt_info)
+ 	      && first_reduc_idx != -1
+ 	      && STMT_VINFO_REDUC_IDX (stmt_info) != -1
+ 	      && rhs_code.is_tree_code ()
+ 	      && commutative_tree_code (tree_code (rhs_code))
+ 	      && first_reduc_idx == 1 - STMT_VINFO_REDUC_IDX (stmt_info))
+ 	    swap[i] = 1;
  	}
  
        matches[i] = true;
*************** vect_build_slp_store_interleaving (vec<s
*** 4045,4051 ****
  }
  
  /* Analyze an SLP instance starting from SCALAR_STMTS which are a group
!    of KIND.  Return true if successful.  */
  
  static bool
  vect_build_slp_instance (vec_info *vinfo,
--- 4060,4068 ----
  }
  
  /* Analyze an SLP instance starting from SCALAR_STMTS which are a group
!    of KIND.  Return true if successful.  SCALAR_STMTS is owned by this
!    function, REMAIN and ROOT_STMT_INFOS ownership is transfered back to
!    the caller upon failure.  */
  
  static bool
  vect_build_slp_instance (vec_info *vinfo,
*************** vect_build_slp_instance (vec_info *vinfo
*** 4059,4065 ****
  {
    /* If there's no budget left bail out early.  */
    if (*limit == 0)
!     return false;
  
    if (kind == slp_inst_kind_ctor)
      {
--- 4076,4085 ----
  {
    /* If there's no budget left bail out early.  */
    if (*limit == 0)
!     {
!       scalar_stmts.release ();
!       return false;
!     }
  
    if (kind == slp_inst_kind_ctor)
      {
*************** vect_build_slp_instance (vec_info *vinfo
*** 4159,4164 ****
--- 4179,4188 ----
  
  	  if (dump_enabled_p ())
  	    {
+ 	      if (kind == slp_inst_kind_reduc_group)
+ 		dump_printf_loc (MSG_NOTE, vect_location,
+ 				 "SLP discovery of size %d reduction group "
+ 				 "succeeded\n", group_size);
  	      dump_printf_loc (MSG_NOTE, vect_location,
  			       "Final SLP tree for instance %p:\n",
  			       (void *) new_instance);
*************** vect_analyze_slp_reduc_chain (loop_vec_i
*** 4217,4222 ****
--- 4241,4247 ----
        if (!gimple_extract_op (STMT_VINFO_STMT (vect_orig_stmt (stmt)), &op))
  	gcc_unreachable ();
        if (CONVERT_EXPR_CODE_P (op.code)
+ 	  && tree_nop_conversion_p (op.type, TREE_TYPE (op.ops[0]))
  	  && (first
  	      || is_a <gphi *> (STMT_VINFO_STMT (next_stmt))))
  	;
*************** vect_analyze_slp (vec_info *vinfo, unsig
*** 5563,5572 ****
  				       bb_vinfo->roots[i].remain,
  				       max_tree_size, &limit, bst_map, false))
  	    {
- 	      bb_vinfo->roots[i].stmts = vNULL;
  	      bb_vinfo->roots[i].roots = vNULL;
  	      bb_vinfo->roots[i].remain = vNULL;
  	    }
  	}
      }
  
--- 5588,5597 ----
  				       bb_vinfo->roots[i].remain,
  				       max_tree_size, &limit, bst_map, false))
  	    {
  	      bb_vinfo->roots[i].roots = vNULL;
  	      bb_vinfo->roots[i].remain = vNULL;
  	    }
+ 	  bb_vinfo->roots[i].stmts = vNULL;
  	}
      }
  
*************** private:
*** 6296,6301 ****
--- 6321,6327 ----
  
    /* Layout selection.  */
    bool is_compatible_layout (slp_tree, unsigned int);
+   bool is_compatible_layout (const slpg_partition_info &, unsigned int);
    int change_layout_cost (slp_tree, unsigned int, unsigned int);
    slpg_partition_layout_costs &partition_layout_costs (unsigned int,
  						       unsigned int);
*************** private:
*** 6303,6308 ****
--- 6329,6335 ----
  			       int, unsigned int);
    int internal_node_cost (slp_tree, int, unsigned int);
    void start_choosing_layouts ();
+   bool legitimize ();
  
    /* Cost propagation.  */
    slpg_layout_cost edge_layout_cost (graph_edge *, unsigned int,
*************** vect_optimize_slp_pass::is_compatible_la
*** 6709,6714 ****
--- 6736,6764 ----
    return true;
  }
  
+ /* Return true if layout LAYOUT_I is compatible with the number of SLP lanes
+    that NODE would operate on for each NODE in PARTITION.
+    This test is independent of NODE's actual operations.  */
+ 
+ bool
+ vect_optimize_slp_pass::is_compatible_layout (const slpg_partition_info
+ 						&partition,
+ 					      unsigned int layout_i)
+ {
+   for (unsigned int order_i = partition.node_begin;
+        order_i < partition.node_end; ++order_i)
+     {
+       unsigned int node_i = m_partitioned_nodes[order_i];
+       auto &vertex = m_vertices[node_i];
+ 
+       /* The layout is incompatible if it is individually incompatible
+ 	 with any node in the partition.  */
+       if (!is_compatible_layout (vertex.node, layout_i))
+ 	return false;
+     }
+   return true;
+ }
+ 
  /* Return the cost (in arbtirary units) of going from layout FROM_LAYOUT_I
     to layout TO_LAYOUT_I for a node like NODE.  Return -1 if either of the
     layouts is incompatible with NODE or if the change is not possible for
*************** vect_optimize_slp_pass::decide_masked_lo
*** 8028,8033 ****
--- 8078,8139 ----
      }
  }
  
+ /* Perform legitimizing attempts.  This is intended to improve the
+    situation when layout 0 is not valid which is a situation the cost
+    based propagation does not handle well.
+    Return true if further layout optimization is possible, false if
+    the layout configuration should be considered final.  */
+ 
+ bool
+ vect_optimize_slp_pass::legitimize ()
+ {
+   /* Perform a very simple legitimizing attempt by attempting to choose
+      a single layout for all partitions that will make all permutations
+      a noop.  That should also be the optimal layout choice in case
+      layout zero is legitimate.
+      ???  Disconnected components of the SLP graph could have distinct
+      single layouts.  */
+   int single_layout_i = -1;
+   unsigned deferred_up_to = -1U;
+   for (unsigned partition_i = 0; partition_i < m_partitions.length ();
+        ++partition_i)
+     {
+       auto &partition = m_partitions[partition_i];
+       if (single_layout_i == -1)
+ 	{
+ 	  single_layout_i = partition.layout;
+ 	  deferred_up_to = partition_i;
+ 	}
+       else if (partition.layout == single_layout_i || partition.layout == -1)
+ 	;
+       else
+ 	single_layout_i = 0;
+       if (single_layout_i == 0)
+ 	return true;
+ 
+       if (single_layout_i != -1
+ 	  && !is_compatible_layout (partition, single_layout_i))
+ 	return true;
+     }
+ 
+   if (single_layout_i <= 0)
+     return true;
+ 
+   for (unsigned partition_i = 0; partition_i < deferred_up_to; ++partition_i)
+     if (!is_compatible_layout (m_partitions[partition_i],
+ 			       single_layout_i))
+       return true;
+ 
+   for (unsigned partition_i = 0; partition_i < m_partitions.length ();
+        ++partition_i)
+     {
+       auto &partition = m_partitions[partition_i];
+       partition.layout = single_layout_i;
+     }
+ 
+   return false;
+ }
+ 
  /* Main entry point for the SLP graph optimization pass.  */
  
  void
*************** vect_optimize_slp_pass::run ()
*** 8038,8045 ****
    start_choosing_layouts ();
    if (m_perms.length () > 1)
      {
!       forward_pass ();
!       backward_pass ();
        if (dump_enabled_p ())
  	dump ();
        materialize ();
--- 8144,8154 ----
    start_choosing_layouts ();
    if (m_perms.length () > 1)
      {
!       if (legitimize ())
! 	{
! 	  forward_pass ();
! 	  backward_pass ();
! 	}
        if (dump_enabled_p ())
  	dump ();
        materialize ();
*************** vect_slp_analyze_operations (vec_info *v
*** 9030,9037 ****
  	  stmt_vec_info stmt_info;
  	  if (!SLP_INSTANCE_ROOT_STMTS (instance).is_empty ())
  	    stmt_info = SLP_INSTANCE_ROOT_STMTS (instance)[0];
! 	  else
  	    stmt_info = SLP_TREE_SCALAR_STMTS (node)[0];
  	  if (is_a <loop_vec_info> (vinfo))
  	    {
  	      if (dump_enabled_p ())
--- 9139,9149 ----
  	  stmt_vec_info stmt_info;
  	  if (!SLP_INSTANCE_ROOT_STMTS (instance).is_empty ())
  	    stmt_info = SLP_INSTANCE_ROOT_STMTS (instance)[0];
! 	  else if (!SLP_TREE_SCALAR_STMTS (node).is_empty ()
! 		   && SLP_TREE_SCALAR_STMTS (node)[0])
  	    stmt_info = SLP_TREE_SCALAR_STMTS (node)[0];
+ 	  else
+ 	    stmt_info = SLP_TREE_REPRESENTATIVE (node);
  	  if (is_a <loop_vec_info> (vinfo))
  	    {
  	      if (dump_enabled_p ())
diff -Nrcpad gcc-16-20251026/gcc/varpool.cc gcc-16-20251102/gcc/varpool.cc
*** gcc-16-20251026/gcc/varpool.cc	Sun Oct 26 22:33:04 2025
--- gcc-16-20251102/gcc/varpool.cc	Sun Nov  2 22:34:18 2025
*************** void
*** 172,182 ****
  varpool_node::remove (void)
  {
    symtab->call_varpool_removal_hooks (this);
!   if (lto_file_data)
!     {
!       lto_free_function_in_decl_state_for_node (this);
!       lto_file_data = NULL;
!     }
  
    /* When streaming we can have multiple nodes associated with decl.  */
    if (symtab->state == LTO_STREAMING)
--- 172,178 ----
  varpool_node::remove (void)
  {
    symtab->call_varpool_removal_hooks (this);
!   lto_free_function_in_decl_state_for_node (this);
  
    /* When streaming we can have multiple nodes associated with decl.  */
    if (symtab->state == LTO_STREAMING)
diff -Nrcpad gcc-16-20251026/libgcobol/ChangeLog gcc-16-20251102/libgcobol/ChangeLog
*** gcc-16-20251026/libgcobol/ChangeLog	Sun Oct 26 22:33:05 2025
--- gcc-16-20251102/libgcobol/ChangeLog	Sun Nov  2 22:34:19 2025
***************
*** 1,3 ****
--- 1,55 ----
+ 2025-10-28  Sam James  <sam@gentoo.org>
+ 
+ 	PR cobol/122451
+ 	* xmlparse.cc (context_t): Make 'ctxt' public.
+ 	(xml_push_parse): Fix xmlCtxtGetVersion argument.
+ 
+ 2025-10-27  Sam James  <sam@gentoo.org>
+ 
+ 	PR cobol/122451
+ 	* xmlparse.cc (xml_push_parse): Fix xmlCtxtGetVersion argument
+ 	typo to be 'context'.
+ 
+ 2025-10-27  James K. Lowden  <jklowden@cobolworx.com>
+ 
+ 	* xmlparse.cc (CTX): Macro for unused user-context parameter.
+ 	(attributeDecl): Mark unused parameters.
+ 	(cdataBlock): Same.
+ 	(characters): Same.
+ 	(comment): Same.
+ 	(elementDecl): Same.
+ 	(endDocument): Same.
+ 	(endElementNs): Same.
+ 	(endElement): Same.
+ 	(entityDecl): Same.
+ 	(error): Same.
+ 	(externalSubset): Same.
+ 	(fatalError): Same.
+ 	(getEntity): Eliminate via preprocessor until needed.
+ 	(getParameterEntity): Same.
+ 	(hasExternalSubset): Mark unused parameters.
+ 	(hasInternalSubset): Same.
+ 	(ignorableWhitespace): Same.
+ 	(internalSubset): Same.
+ 	(isStandalone): Eliminate via preprocessor until needed.
+ 	(notationDecl): Mark unused parameters.
+ 	(processingInstruction): Same.
+ 	(reference): Same.
+ 	(resolveEntity): Eliminate via preprocessor until needed.
+ 	(setDocumentLocator): Mark unused parameters.
+ 	(startDocument): Same.
+ 	(startElementNs): Same.
+ 	(startElement): Same.
+ 	(unparsedEntityDecl): Same.
+ 	(warning): Same.
+ 	(xmlchar_of): Utility cast function.
+ 	(xmlParserErrors_str): Message string for libxml2 errors.
+ 	(xmlerror_str): Macro to include textual form of libxml2 error.
+ 	(context_t): Push-parser context class.
+ 	(xml_push_parse): Use push-parser.
+ 	(__gg__xml_parse_done): Signify end-of-input to XML push-parser.
+ 	(__gg__xml_parse): Mark unused parameters.
+ 
  2025-10-25  Sam James  <sam@gentoo.org>
  
  	PR cobol/122398
diff -Nrcpad gcc-16-20251026/libgcobol/xmlparse.cc gcc-16-20251102/libgcobol/xmlparse.cc
*** gcc-16-20251026/libgcobol/xmlparse.cc	Sun Oct 26 22:33:05 2025
--- gcc-16-20251102/libgcobol/xmlparse.cc	Sun Nov  2 22:34:19 2025
***************
*** 46,51 ****
--- 46,53 ----
  #include <libxml/SAX2.h>
  #include <libxml/parser.h>
  
+ #include <syslog.h>
+ 
  #include "config.h"
  #include "libgcobol-fp.h"
  #include "ec.h"
*************** void sayso( const char func[], int line,
*** 76,193 ****
  #define SAYSO_DATAZ(S) sayso(__func__, __LINE__, -1, S)
  #define SAYSO_DATA(N, S) sayso(__func__, __LINE__, N, S)
  
  struct xml_ec_value_t {
    int ibm_code;
    const char msg[80];
! } xml_ec_values[] = {  
    // Table 73. XML PARSE exceptions that allow continuation
!   { 1, "invalid character between elements" }, 
!   { 2, "invalid start before element content" }, 
!   { 3, "duplicate attribute" }, 
!   { 4, "markup character '<' in an attribute value" }, 
!   { 5, "start/end tag mismatch" }, 
!   { 6, "invalid character in element" }, 
!   { 7, "invalid start in element content. " }, 
!   { 8, "CDATA closing character sequence ']]>' not opened" }, 
!   { 10, "comment the character sequence '--' without '>'" }, 
!   { 11, "invalid character in a processing instruction" }, 
!   { 12, "XML declaration was not start of  document" }, 
!   { 13, "invalid digit in a hexadecimal character reference" }, 
!   { 14, "invalid digit in a decimal character reference" }, 
!   { 15, "encoding declaration value name must start with [a-zA-Z] character" }, 
!   { 16, "character reference did not refer to a legal XML character" }, 
!   { 17, "invalid character in an entity reference name" }, 
!   { 70, "EBCDIC document, supported EBCDIC page, unsupported declaration" }, 
!   { 71, "EBCDIC document, unsupported EBCDIC page " }, 
!   { 72, "EBCDIC document, unsupported EBCDIC page, unsupported  declaration" }, 
!   { 73, "EBCDIC document, unsupported EBCDIC page and declaration " }, 
!   { 80, "ASCII document, supported ASCII page, unsupported declaration" }, 
!   { 81, "ASCII document, unsupported ASCII page " }, 
!   { 82, "ASCII document, unsupported ASCII page, unsupported  declaration" }, 
!   { 83, "ASCII document, unsupported ASCII page and declaration " }, 
!   { 84, "ASCII document, invalid UTF-8, external UTF-8, no declaration. " }, 
!   { 85, "ASCII document, invalid UTF-8, external UTF-8, invalid  declaration" }, 
!   { 86, "ASCII document, invalid UTF-8, external ASCII" }, 
!   { 87, "ASCII document, invalid UTF-8, external and document UTF-8" }, 
!   { 88, "ASCII document, invalid UTF-8, unsupported ASCII/UTF-8, UTF-8 declaration" }, 
!   { 89, "ASCII document, invalid UTF-8, external UTF-8, ASCII declaration" }, 
!   { 92, "alphanumeric document expected, document is UTF-16. " }, 
  
!   // XML PARSE exceptions that allow continuation (continued) 
    //// 100,001 - 165,535 EBCDIC document encoding does not match code page
    //// 200,001 - 265,535 ASCII document encoding does not match code page
  
!   // XML PARSE exceptions that do not allow continuation 
!   { 100, "end of document before start of XML declaration" }, 
!   { 101, "end of document before end of XML declaration" }, 
!   { 102, "end of document before root element" }, 
!   { 103, "end of document before version information in XML declaration" }, 
!   { 104, "end of document before version information value in XML declaration" }, 
!   { 106, "end of document before encoding declaration value in XML declaration" }, 
!   { 108, "end of document before standalone declaration value in XML declaration" }, 
!   { 109, "end of document before attribute name" }, 
!   { 110, "end of document before attribute value" }, 
!   { 111, "end of document before character/entity reference in attribute value" }, 
!   { 112, "end of document before empty element tag" }, 
!   { 113, "end of document before root element name" }, 
!   { 114, "end of document before element name" }, 
!   { 115, "end of document before character data in element content" }, 
!   { 116, "end of document before processing instruction in element content" }, 
!   { 117, "end of document before comment or CDATA section in element content" }, 
!   { 118, "end of document before comment in element content" }, 
!   { 119, "end of document before CDATA section in element content" }, 
!   { 120, "end of document before character/entity reference in element content" }, 
!   { 121, "end of document before after close of root element" }, 
!   { 122, "possible invalid start of a document type" }, 
!   { 123, "duplicate document type" }, 
!   { 124, "root element name must start with [A-Za-z_:]" }, 
!   { 125, "first attribute name must start with [A-Za-z_:]" }, 
!   { 126, "invalid character in or after element name" }, 
!   { 127, "attribute name not followed by '=' " }, 
!   { 128, "invalid attribute value delimiter" }, 
!   { 130, "attribute name must start with [A-Za-z_:]" }, 
!   { 131, "invalid character in or after attribute name" }, 
!   { 132, "empty element tag not terminated with '/>'" }, 
!   { 133, "element end tag name name must start with [A-Za-z_:]" }, 
!   { 134, "element end tag not terminated with '>'" }, 
!   { 135, "element name must start with [A-Za-z_:]" }, 
!   { 136, "invalid start of comment/CDATA in element" }, 
!   { 137, "invalid start of comment" }, 
!   { 138, "processing instruction target name must start with [A-Za-z_:]" }, 
!   { 139, "invalid character in/afterprocessing instruction target name" }, 
!   { 140, "processing instruction not terminated with '?>'" }, 
!   { 141, "invalid character following '&' in a character/entity reference" }, 
!   { 142, "missing version information in XML declaration" }, 
!   { 143, "missing '=' after 'version' in XML declaration " }, 
!   { 144, "missing XML version declaration " }, 
!   { 145, "invalid character in XML version information" }, 
!   { 146, "invalid character following XML version information value " }, 
!   { 147, "invalid attribute in XML declaration" }, 
!   { 148, "missing '=' after 'encoding' in XML declaration" }, 
!   { 149, "missing XML encoding declaration value" }, 
!   { 150, "invalid XML encoding declaration value" }, 
!   { 151, "invalid character afer XML declaration" }, 
!   { 152, "invalid attribute  XML declaration" }, 
!   { 153, "missing '=' after standalone  XML declaration" }, 
!   { 154, "missing standalone XML declaration value" }, 
!   { 155, "standalone declaration must be 'yes' or 'no'" }, 
!   { 156, "invalid standalone XML declaration value" }, 
!   { 157, "invalid character following XML standalone declaration value" }, 
!   { 158, "unterminated XML declaration " }, 
!   { 159, "start of document type declaration after end of root element" }, 
!   { 160, "start of element after end of root element" }, 
!   { 161, "invalid UTF-8 byte sequence" }, 
!   { 162, "UTF-8 character that has a Unicode code point above x'FFFF'" }, 
!   { 315, "UTF-16 document  little-endian unsupported" }, 
!   { 316, "UCS4 document unsupported" }, 
!   { 317, "unrecognized document encoding" }, 
!   { 318, "UTF-8 document unsupported " }, 
!   { 320, "mismatched national document data item to document encoding EBCDIC" }, 
!   { 321, "mismatched national document data item to document encoding ASCII" }, 
!   { 322, "mismatched native alphanumeric document data item to document encoding EBCDIC" }, 
!   { 323, "mismatched host alphanumeric document data item to document encoding ASCII" }, 
!   { 324, "mismatched national document data item to document encoding UTF-8" }, 
!   { 325, "mismatched host alphanumeric document datat to document encoding UTF-8" }, 
    { 500, "internal error" },
  }, *eoxml_ec_values = xml_ec_values + COUNT_OF(xml_ec_values);
  
--- 78,197 ----
  #define SAYSO_DATAZ(S) sayso(__func__, __LINE__, -1, S)
  #define SAYSO_DATA(N, S) sayso(__func__, __LINE__, N, S)
  
+ #define CTX ctx __attribute__ ((unused))
+ 
  struct xml_ec_value_t {
    int ibm_code;
    const char msg[80];
! } xml_ec_values[] = {
    // Table 73. XML PARSE exceptions that allow continuation
!   { 1, "invalid character between elements" },
!   { 2, "invalid start before element content" },
!   { 3, "duplicate attribute" },
!   { 4, "markup character '<' in an attribute value" },
!   { 5, "start/end tag mismatch" },
!   { 6, "invalid character in element" },
!   { 7, "invalid start in element content. " },
!   { 8, "CDATA closing character sequence ']]>' not opened" },
!   { 10, "comment the character sequence '--' without '>'" },
!   { 11, "invalid character in a processing instruction" },
!   { 12, "XML declaration was not start of  document" },
!   { 13, "invalid digit in a hexadecimal character reference" },
!   { 14, "invalid digit in a decimal character reference" },
!   { 15, "encoding declaration value name must start with [a-zA-Z] character" },
!   { 16, "character reference did not refer to a legal XML character" },
!   { 17, "invalid character in an entity reference name" },
!   { 70, "EBCDIC document, supported EBCDIC page, unsupported declaration" },
!   { 71, "EBCDIC document, unsupported EBCDIC page " },
!   { 72, "EBCDIC document, unsupported EBCDIC page, unsupported  declaration" },
!   { 73, "EBCDIC document, unsupported EBCDIC page and declaration " },
!   { 80, "ASCII document, supported ASCII page, unsupported declaration" },
!   { 81, "ASCII document, unsupported ASCII page " },
!   { 82, "ASCII document, unsupported ASCII page, unsupported  declaration" },
!   { 83, "ASCII document, unsupported ASCII page and declaration " },
!   { 84, "ASCII document, invalid UTF-8, external UTF-8, no declaration. " },
!   { 85, "ASCII document, invalid UTF-8, external UTF-8, invalid  declaration" },
!   { 86, "ASCII document, invalid UTF-8, external ASCII" },
!   { 87, "ASCII document, invalid UTF-8, external and document UTF-8" },
!   { 88, "ASCII document, invalid UTF-8, unsupported ASCII/UTF-8, UTF-8 declaration" },
!   { 89, "ASCII document, invalid UTF-8, external UTF-8, ASCII declaration" },
!   { 92, "alphanumeric document expected, document is UTF-16. " },
  
!   // XML PARSE exceptions that allow continuation (continued)
    //// 100,001 - 165,535 EBCDIC document encoding does not match code page
    //// 200,001 - 265,535 ASCII document encoding does not match code page
  
!   // XML PARSE exceptions that do not allow continuation
!   { 100, "end of document before start of XML declaration" },
!   { 101, "end of document before end of XML declaration" },
!   { 102, "end of document before root element" },
!   { 103, "end of document before version information in XML declaration" },
!   { 104, "end of document before version information value in XML declaration" },
!   { 106, "end of document before encoding declaration value in XML declaration" },
!   { 108, "end of document before standalone declaration value in XML declaration" },
!   { 109, "end of document before attribute name" },
!   { 110, "end of document before attribute value" },
!   { 111, "end of document before character/entity reference in attribute value" },
!   { 112, "end of document before empty element tag" },
!   { 113, "end of document before root element name" },
!   { 114, "end of document before element name" },
!   { 115, "end of document before character data in element content" },
!   { 116, "end of document before processing instruction in element content" },
!   { 117, "end of document before comment or CDATA section in element content" },
!   { 118, "end of document before comment in element content" },
!   { 119, "end of document before CDATA section in element content" },
!   { 120, "end of document before character/entity reference in element content" },
!   { 121, "end of document before after close of root element" },
!   { 122, "possible invalid start of a document type" },
!   { 123, "duplicate document type" },
!   { 124, "root element name must start with [A-Za-z_:]" },
!   { 125, "first attribute name must start with [A-Za-z_:]" },
!   { 126, "invalid character in or after element name" },
!   { 127, "attribute name not followed by '=' " },
!   { 128, "invalid attribute value delimiter" },
!   { 130, "attribute name must start with [A-Za-z_:]" },
!   { 131, "invalid character in or after attribute name" },
!   { 132, "empty element tag not terminated with '/>'" },
!   { 133, "element end tag name name must start with [A-Za-z_:]" },
!   { 134, "element end tag not terminated with '>'" },
!   { 135, "element name must start with [A-Za-z_:]" },
!   { 136, "invalid start of comment/CDATA in element" },
!   { 137, "invalid start of comment" },
!   { 138, "processing instruction target name must start with [A-Za-z_:]" },
!   { 139, "invalid character in/afterprocessing instruction target name" },
!   { 140, "processing instruction not terminated with '?>'" },
!   { 141, "invalid character following '&' in a character/entity reference" },
!   { 142, "missing version information in XML declaration" },
!   { 143, "missing '=' after 'version' in XML declaration " },
!   { 144, "missing XML version declaration " },
!   { 145, "invalid character in XML version information" },
!   { 146, "invalid character following XML version information value " },
!   { 147, "invalid attribute in XML declaration" },
!   { 148, "missing '=' after 'encoding' in XML declaration" },
!   { 149, "missing XML encoding declaration value" },
!   { 150, "invalid XML encoding declaration value" },
!   { 151, "invalid character afer XML declaration" },
!   { 152, "invalid attribute  XML declaration" },
!   { 153, "missing '=' after standalone  XML declaration" },
!   { 154, "missing standalone XML declaration value" },
!   { 155, "standalone declaration must be 'yes' or 'no'" },
!   { 156, "invalid standalone XML declaration value" },
!   { 157, "invalid character following XML standalone declaration value" },
!   { 158, "unterminated XML declaration " },
!   { 159, "start of document type declaration after end of root element" },
!   { 160, "start of element after end of root element" },
!   { 161, "invalid UTF-8 byte sequence" },
!   { 162, "UTF-8 character that has a Unicode code point above x'FFFF'" },
!   { 315, "UTF-16 document  little-endian unsupported" },
!   { 316, "UCS4 document unsupported" },
!   { 317, "unrecognized document encoding" },
!   { 318, "UTF-8 document unsupported " },
!   { 320, "mismatched national document data item to document encoding EBCDIC" },
!   { 321, "mismatched national document data item to document encoding ASCII" },
!   { 322, "mismatched native alphanumeric document data item to document encoding EBCDIC" },
!   { 323, "mismatched host alphanumeric document data item to document encoding ASCII" },
!   { 324, "mismatched national document data item to document encoding UTF-8" },
!   { 325, "mismatched host alphanumeric document datat to document encoding UTF-8" },
    { 500, "internal error" },
  }, *eoxml_ec_values = xml_ec_values + COUNT_OF(xml_ec_values);
  
*************** ATTRIBUTE-CHARACTER The single character
*** 240,256 ****
  ATTRIBUTE-CHARACTERS The value within quotation marks or apostrophes. This can be a substring of the attribute value if the value includes an entity reference.
  ATTRIBUTE-NAME The attribute name; the string to the left of the equal sign
  ATTRIBUTE-NATIONAL-CHARACTER Regardless of the type of the XML document specified by identifier-1 in the XML PARSE statement, XML-TEXT is empty with length zero and XML-NTEXT contains the single national character that corresponds with the numeric character reference.
!  
  CONTENT-CHARACTER The single character that corresponds with the predefined entity reference in the element content
!  
  CONTENT-NATIONAL-CHARACTER Regardless of the type of the XML document specified by identifier-1 in the XML PARSE statement, XML-TEXT is empty with length zero and XML-NTEXT contains the single national character that corresponds with the numeric character reference.1
  DOCUMENT-TYPE-DECLARATION The entire document type declaration, including the opening and closing character sequences "<!DOCTYPE" and ">"
  ENCODING-DECLARATION The value, between quotes or apostrophes, of the encoding declaration in the XML declaration
  END-OF-CDATA-SECTION The string "]]>"
  END-OF-DOCUMENT Empty with length zero
!  
  EXCEPTION The part of the document that was successfully scanned, up to and including the point at which the exception was detected.2 Special register XML-CODE contains the unique error code that identifies the exception.
!  
  PROCESSING-INSTRUCTION-TARGET The processing instruction target name, which occurs immediately after the processing instruction opening sequence, "<?"
  STANDALONE-DECLARATION The value, between quotation marks or apostrophes ("yes" or "no"), of the stand-alone declaration in the XML declaration
  START-OF-CDATA-SECTION The string "<![CDATA["
--- 244,260 ----
  ATTRIBUTE-CHARACTERS The value within quotation marks or apostrophes. This can be a substring of the attribute value if the value includes an entity reference.
  ATTRIBUTE-NAME The attribute name; the string to the left of the equal sign
  ATTRIBUTE-NATIONAL-CHARACTER Regardless of the type of the XML document specified by identifier-1 in the XML PARSE statement, XML-TEXT is empty with length zero and XML-NTEXT contains the single national character that corresponds with the numeric character reference.
! 
  CONTENT-CHARACTER The single character that corresponds with the predefined entity reference in the element content
! 
  CONTENT-NATIONAL-CHARACTER Regardless of the type of the XML document specified by identifier-1 in the XML PARSE statement, XML-TEXT is empty with length zero and XML-NTEXT contains the single national character that corresponds with the numeric character reference.1
  DOCUMENT-TYPE-DECLARATION The entire document type declaration, including the opening and closing character sequences "<!DOCTYPE" and ">"
  ENCODING-DECLARATION The value, between quotes or apostrophes, of the encoding declaration in the XML declaration
  END-OF-CDATA-SECTION The string "]]>"
  END-OF-DOCUMENT Empty with length zero
! 
  EXCEPTION The part of the document that was successfully scanned, up to and including the point at which the exception was detected.2 Special register XML-CODE contains the unique error code that identifies the exception.
! 
  PROCESSING-INSTRUCTION-TARGET The processing instruction target name, which occurs immediately after the processing instruction opening sequence, "<?"
  STANDALONE-DECLARATION The value, between quotation marks or apostrophes ("yes" or "no"), of the stand-alone declaration in the XML declaration
  START-OF-CDATA-SECTION The string "<![CDATA["
*************** xml_event( const char event_name[], size
*** 276,282 ****
    auto p = std::copy( event_name, event_name + strlen(event_name),
                        PTRCAST(char, __ggsr__xml_event.data) );
    std::fill(PTRCAST(unsigned char, p), pend, 0x20);
!   
    __ggsr__xml_text.data = reinterpret_cast<unsigned char*>(text);
    __ggsr__xml_text.capacity = __ggsr__xml_text.allocated = len;
    __ggsr__xml_code.data = 0;
--- 280,286 ----
    auto p = std::copy( event_name, event_name + strlen(event_name),
                        PTRCAST(char, __ggsr__xml_event.data) );
    std::fill(PTRCAST(unsigned char, p), pend, 0x20);
! 
    __ggsr__xml_text.data = reinterpret_cast<unsigned char*>(text);
    __ggsr__xml_text.capacity = __ggsr__xml_text.allocated = len;
    __ggsr__xml_code.data = 0;
*************** xml_event( const char event_name[], cons
*** 300,369 ****
    xml_event(event_name, strlen(text), text);
  }
  
! static void attributeDecl(void * ctx, 
!                           const xmlChar * elem, 
!                           const xmlChar * fullname, 
!                           int type, 
!                           int def, 
!                           const xmlChar * defaultValue, 
!                           xmlEnumerationPtr tree)
  {
    fprintf(stderr, "%s:%d: elem=%s, name=%s, default=%s\n",
            __func__, __LINE__, elem, fullname, defaultValue);
  }
  
! static void cdataBlock(void * ctx, 
!                        const xmlChar * data, 
                         int len)
! { 
    SAYSO_DATA(len, data);
    xml_event("CONTENT-CHARACTERS", len, data);
  }
  
! static void characters(void * ctx, 
!                        const xmlChar * data, 
                         int len)
  {
    SAYSO_DATA(len, data);
    xml_event("CONTENT-CHARACTERS", len, data);
  }
  
! static void comment(void * ctx, const xmlChar * value) {
    SAYSO_DATAZ(value);
    xml_event("COMMENT", value);
  }
  
! static void elementDecl(void * ctx, 
!                         const xmlChar * name, 
!                         int type, 
!                         xmlElementContentPtr content)
  { SAYSO_DATAZ(name); }
  
! static void endDocument(void * ctx)
  { SAYSO(); }
  
! static void endElementNs(void * ctx, 
!                          const xmlChar * localname, 
!                          const xmlChar * prefix, 
!                          const xmlChar * URI)
  {
    SAYSO_DATAZ(localname);
    xml_event("END-OF-ELEMENT", localname);
  }
  
! static void endElement(void * ctx, 
                         const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! static void entityDecl(void * ctx, 
!                        const xmlChar * name, 
!                        int type, 
!                        const xmlChar * publicId, 
!                        const xmlChar * systemId, 
!                        xmlChar * content)
! { SAYSO_DATAZ(name); }
  
! static void error(void * ctx, const char * msg, ...)
  {
    va_list ap;
    va_start (ap, msg);
--- 304,383 ----
    xml_event(event_name, strlen(text), text);
  }
  
! /*
!  * Many static handler functions are defined but not used while we learn what
!  * is needed.
!  */
! #pragma GCC diagnostic ignored "-Wunused-function"
! 
! static void attributeDecl(void * CTX,
!                           const xmlChar * elem,
!                           const xmlChar * fullname,
!                           int type __attribute__ ((unused)),
!                           int def  __attribute__ ((unused)),
!                           const xmlChar * defaultValue,
!                           xmlEnumerationPtr tree __attribute__ ((unused)) )
  {
    fprintf(stderr, "%s:%d: elem=%s, name=%s, default=%s\n",
            __func__, __LINE__, elem, fullname, defaultValue);
  }
  
! static void cdataBlock(void * CTX,
!                        const xmlChar * data,
                         int len)
! {
    SAYSO_DATA(len, data);
    xml_event("CONTENT-CHARACTERS", len, data);
  }
  
! static void characters(void * CTX,
!                        const xmlChar * data,
                         int len)
  {
    SAYSO_DATA(len, data);
    xml_event("CONTENT-CHARACTERS", len, data);
  }
  
! static void comment(void * CTX, const xmlChar * value) {
    SAYSO_DATAZ(value);
    xml_event("COMMENT", value);
  }
  
! static void elementDecl(void * CTX,
!                         const xmlChar * name,
!                         int type __attribute__ ((unused)),
!                         xmlElementContentPtr content __attribute__ ((unused)) )
  { SAYSO_DATAZ(name); }
  
! static void endDocument(void * CTX)
  { SAYSO(); }
  
! static void endElementNs(void * CTX,
!                          const xmlChar * localname,
!                          const xmlChar * prefix,
!                          const xmlChar * URI __attribute__ ((unused)) )
  {
+   SAYSO_DATAZ(prefix);
    SAYSO_DATAZ(localname);
    xml_event("END-OF-ELEMENT", localname);
  }
  
! static void endElement(void * CTX,
                         const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! static void entityDecl(void * CTX,
!                        const xmlChar * name,
!                        int type __attribute__ ((unused)),
!                        const xmlChar * publicId __attribute__ ((unused)),
!                        const xmlChar * systemId __attribute__ ((unused)),
!                        xmlChar * content )
! {
!   SAYSO_DATAZ(name);
!   SAYSO_DATAZ(content);
! }
  
! static void error(void * CTX, const char * msg, ...)
  {
    va_list ap;
    va_start (ap, msg);
*************** static void error(void * ctx, const char
*** 373,385 ****
    va_end (ap);
  }
  
! static void externalSubset(void * ctx, 
!                            const xmlChar * name, 
!                            const xmlChar * ExternalID, 
                             const xmlChar * SystemID)
! { SAYSO_DATAZ(name); }
  
! static void fatalError(void * ctx, const char * msg, ...)
  {
    va_list ap;
    va_start (ap, msg);
--- 387,403 ----
    va_end (ap);
  }
  
! static void externalSubset(void * CTX,
!                            const xmlChar * name,
!                            const xmlChar * ExternalID,
                             const xmlChar * SystemID)
! {
!   SAYSO_DATAZ(name);
!   SAYSO_DATAZ(ExternalID);
!   SAYSO_DATAZ(SystemID);
! }
  
! static void fatalError(void * CTX, const char * msg, ...)
  {
    va_list ap;
    va_start (ap, msg);
*************** static void fatalError(void * ctx, const
*** 389,431 ****
    va_end (ap);
  }
  
! static xmlEntityPtr getEntity(void * ctx, 
                                const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! static xmlEntityPtr getParameterEntity(void * ctx, 
                                         const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! static int hasExternalSubset(void * ctx)
! { SAYSO(); }
  
! static int hasInternalSubset(void * ctx)
! { SAYSO(); }
  
! static void ignorableWhitespace(void * ctx, 
!                                 const xmlChar * ch, 
                                  int len)
  { SAYSO_DATA(len, ch); }
  
! static void internalSubset(void * ctx, 
!                            const xmlChar * name, 
!                            const xmlChar * ExternalID, 
                             const xmlChar * SystemID)
! { SAYSO_DATAZ(name); }
  
! static int isStandalone (void * ctx)
  { SAYSO(); }
  
! 
! static void notationDecl(void * ctx, 
!                          const xmlChar * name, 
!                          const xmlChar * publicId, 
                           const xmlChar * systemId)
! { SAYSO_DATAZ(name); }
  
! static void processingInstruction(void * ctx, 
!                                   const xmlChar * target, 
                                    const xmlChar * data)
  {
    SAYSO_DATAZ(target);
--- 407,460 ----
    va_end (ap);
  }
  
! #if 0
! static xmlEntityPtr getEntity(void * CTX,
                                const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! static xmlEntityPtr getParameterEntity(void * CTX,
                                         const xmlChar * name)
  { SAYSO_DATAZ(name); }
+ #endif
  
! static int hasExternalSubset(void * CTX)
! { SAYSO(); return 0; }
  
! static int hasInternalSubset(void * CTX)
! { SAYSO(); return 0; }
  
! static void ignorableWhitespace(void * CTX,
!                                 const xmlChar * ch,
                                  int len)
  { SAYSO_DATA(len, ch); }
  
! static void internalSubset(void * CTX,
!                            const xmlChar * name,
!                            const xmlChar * ExternalID,
                             const xmlChar * SystemID)
! {
!   SAYSO_DATAZ(name);
!   SAYSO_DATAZ(ExternalID);
!   SAYSO_DATAZ(SystemID);
! }
  
! #if 0
! static int isStandalone (void * CTX)
  { SAYSO(); }
+ #endif
  
! static void notationDecl(void * CTX,
!                          const xmlChar * name,
!                          const xmlChar * publicId,
                           const xmlChar * systemId)
! {
!   SAYSO_DATAZ(name);
!   SAYSO_DATAZ(publicId);
!   SAYSO_DATAZ(systemId);
! }
  
! static void processingInstruction(void * CTX,
!                                   const xmlChar * target,
                                    const xmlChar * data)
  {
    SAYSO_DATAZ(target);
*************** static void processingInstruction(void *
*** 434,450 ****
    xml_event("PROCESSING-INSTRUCTION-DATA", data);
  }
  
! static void reference(void * ctx, 
                        const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! static xmlParserInputPtr resolveEntity( void * ctx, 
!                                         const xmlChar * publicId, 
                                          const xmlChar * systemId)
  { SAYSO(); }
  
! static void setDocumentLocator(void * ctx, 
!                                xmlSAXLocatorPtr loc)
  { SAYSO(); }
  
  /*
--- 463,481 ----
    xml_event("PROCESSING-INSTRUCTION-DATA", data);
  }
  
! static void reference(void * CTX,
                        const xmlChar * name)
  { SAYSO_DATAZ(name); }
  
! #if 0
! static xmlParserInputPtr resolveEntity( void * CTX,
!                                         const xmlChar * publicId,
                                          const xmlChar * systemId)
  { SAYSO(); }
+ #endif
  
! static void setDocumentLocator(void * CTX,
!                                xmlSAXLocatorPtr loc __attribute__ ((unused)) )
  { SAYSO(); }
  
  /*
*************** static void setDocumentLocator(void * ct
*** 452,487 ****
   * Use xmlCtxtGetVersion(), xmlCtxtGetDeclaredEncoding() and
   * xmlCtxtGetStandalone() to get data from the XML declaration.
   */
! static void startDocument(void * ctx)
! { SAYSO(); }
  
! static void startElementNs(void * ctx, 
!                            const xmlChar * localname, 
!                            const xmlChar * prefix, 
!                            const xmlChar * URI, 
!                            int nb_namespaces, 
!                            const xmlChar ** namespaces, 
!                            int nb_attributes, 
!                            int nb_defaulted, 
!                            const xmlChar ** attributes)
  {
    SAYSO_DATAZ(localname);
    xml_event("START-OF-ELEMENT", localname);
  }
  
! static void startElement(void * ctx, 
!                          const xmlChar * name, 
                           const xmlChar ** atts)
! { SAYSO_DATAZ(name); }
  
! static void unparsedEntityDecl(void * ctx, 
!                                const xmlChar * name, 
!                                const xmlChar * publicId, 
!                                const xmlChar * systemId, 
                                 const xmlChar * notationName)
! { SAYSO_DATAZ(name); }
  
! static void warning(void * ctx, const char * msg, ... )
  {
    va_list ap;
    va_start (ap, msg);
--- 483,530 ----
   * Use xmlCtxtGetVersion(), xmlCtxtGetDeclaredEncoding() and
   * xmlCtxtGetStandalone() to get data from the XML declaration.
   */
! static void startDocument(void * CTX)
! {
!   SAYSO();
! }
  
! static void startElementNs(void * CTX,
!                            const xmlChar * localname,
!                            const xmlChar * prefix,
!                            const xmlChar * URI,
!                            int nb_namespaces __attribute__ ((unused)),
!                            const xmlChar ** namespaces __attribute__ ((unused)),
!                            int nb_attributes __attribute__ ((unused)),
!                            int nb_defaulted __attribute__ ((unused)),
!                            const xmlChar ** attributes __attribute__ ((unused)))
  {
+   SAYSO_DATAZ(prefix);
+   SAYSO_DATAZ(URI);
    SAYSO_DATAZ(localname);
    xml_event("START-OF-ELEMENT", localname);
  }
  
! static void startElement(void * CTX,
!                          const xmlChar * name,
                           const xmlChar ** atts)
! {
!   SAYSO_DATAZ(name);
!   for( int i=0; atts[i]; i++ ) SAYSO_DATAZ(atts[i]);
! }
  
! static void unparsedEntityDecl(void * CTX,
!                                const xmlChar * name,
!                                const xmlChar * publicId,
!                                const xmlChar * systemId,
                                 const xmlChar * notationName)
! {
!   SAYSO_DATAZ(name);
!   SAYSO_DATAZ(publicId);
!   SAYSO_DATAZ(systemId);
!   SAYSO_DATAZ(notationName);
! }
  
! static void warning(void * CTX, const char * msg, ... )
  {
    va_list ap;
    va_start (ap, msg);
*************** static void warning(void * ctx, const ch
*** 494,508 ****
  /*
   * xmlSAXHandler is a structure of function pointers that the SAX parser calls
   * as it encounters XML elements in the input.  Each pointer is a callback
!  * function, locally defined in this file. These we term "handlers".  
!  * 
   * Each handler sets the XML registers per IBM, and then calls
   * cobol_callback(), which is a function pointer supplied by the COBOL program
!  * to be the processing procedure for XML PARSE.  
!  * 
   * There is no obvious way to abort parsing at the C level.  See:
   *     http://veillard.com/XML/messages/0540.html
!  * 
   * > The simplest to implement this would not be to add a new SAX
   * > callback but rather modify the xmlParserCtxtPtr passed to the
   * > callbacks. The best seems to be:
--- 537,551 ----
  /*
   * xmlSAXHandler is a structure of function pointers that the SAX parser calls
   * as it encounters XML elements in the input.  Each pointer is a callback
!  * function, locally defined in this file. These we term "handlers".
!  *
   * Each handler sets the XML registers per IBM, and then calls
   * cobol_callback(), which is a function pointer supplied by the COBOL program
!  * to be the processing procedure for XML PARSE.
!  *
   * There is no obvious way to abort parsing at the C level.  See:
   *     http://veillard.com/XML/messages/0540.html
!  *
   * > The simplest to implement this would not be to add a new SAX
   * > callback but rather modify the xmlParserCtxtPtr passed to the
   * > callbacks. The best seems to be:
*************** static void warning(void * ctx, const ch
*** 512,518 ****
   * > Doing both should led to a quick termination of parsing
   * > (but endElement(s)/endDocument will certainly be called anyway).
   *
!  * Another hack might be to set the input to all blanks in cobol_callback. 
   */
  
  static xmlSAXHandler handlers;
--- 555,561 ----
   * > Doing both should led to a quick termination of parsing
   * > (but endElement(s)/endDocument will certainly be called anyway).
   *
!  * Another hack might be to set the input to all blanks in cobol_callback.
   */
  
  static xmlSAXHandler handlers;
*************** initialize_handlers( callback_t *callbac
*** 548,554 ****
  
    //// Everything is available on the context, so this is useless in our case
    handlers.setDocumentLocator = setDocumentLocator;
! #endif  
  
    handlers.cdataBlock = cdataBlock;
    handlers.characters = characters;
--- 591,597 ----
  
    //// Everything is available on the context, so this is useless in our case
    handlers.setDocumentLocator = setDocumentLocator;
! #endif
  
    handlers.cdataBlock = cdataBlock;
    handlers.characters = characters;
*************** initialize_handlers( callback_t *callbac
*** 565,578 ****
    handlers.warning = warning;
  }
  
  extern "C"
! int 
  __gg__xml_parse(  const cblc_field_t *input_field,
                    size_t        input_offset,
                    size_t        len,
!                   cblc_field_t *encoding,
!                   cblc_field_t *validating,
!                   int           returns_national,
                    void (*callback)(void) )
  {
    initialize_handlers(callback);
--- 608,765 ----
    handlers.warning = warning;
  }
  
+ static xmlChar *
+ xmlchar_of( const char input[] ) {
+   return const_cast<xmlChar*>( reinterpret_cast<const xmlChar*>(input) );
+ }
+ 
+ static const char *
+ xmlParserErrors_str( xmlParserErrors erc, const char name[] ) {
+   const char *msg = "???";
+ 
+   switch( erc ) {
+   case XML_ERR_OK:
+     msg = "Success";
+     break;
+   case XML_ERR_INTERNAL_ERROR:
+     msg = "Internal assertion failure";
+     break;
+   case XML_ERR_NO_MEMORY:
+     msg = "Out of memory";
+     break;
+   case XML_ERR_UNSUPPORTED_ENCODING:
+     msg = "Unsupported character encoding";
+     break;
+ #if LIBXML_VERSION >= 21400
+   case XML_ERR_RESOURCE_LIMIT:
+     msg = "Internal resource limit like maximum amplification factor exceeded";
+     break;
+   case XML_ERR_ARGUMENT:
+     msg = "Invalid argument";
+     break;
+   case XML_ERR_SYSTEM:
+     msg = "Unexpected error from the OS or an external library";
+     break;
+ #endif
+   case XML_IO_ENOENT:
+     msg = "File not found";
+     break;
+   default:
+     msg = strdup(name);
+     if( ! msg ) msg = "unknown XML error";
+     break;
+   }
+   return msg;
+ }
+ 
+ #define xmlerror_str(E) xmlParserErrors_str( (E), #E )
+ 
+ /*
+  * The global context is NULL if XML PARSE is not in progress.
+  */
+ static class context_t {
+   const int priority;
+  public:
+   xmlParserCtxt * ctxt;
+   context_t() : ctxt(nullptr), priority(LOG_INFO) {
+     const int option = LOG_PERROR, facility = LOG_USER;
+ #if HAVE_DECL_PROGRAM_INVOCATION_SHORT_NAME
+     /* Declared in errno.h, when available.  */
+     static const char * const ident = program_invocation_short_name;
+ #elif defined (HAVE_GETPROGNAME)
+     /* Declared in stdlib.h.  */
+     static const char * const ident = getprogname();
+ #else
+     /* Avoid a NULL entry.  */
+     static const char * const ident = "unnamed_COBOL_program";
+ #endif
+     // TODO: Program to set option in library via command-line and/or environment.
+     //       Library listens to program, not to the environment.
+     openlog(ident, option, facility);
+ 
+     initialize_handlers(nullptr);
+   }
+ 
+   void
+   push( cblc_field_t *input_field, size_t input_offset, size_t len, bool done ) {
+     if( ! ctxt ) {
+       init();
+     }
+     assert(cobol_callback); // caller must set
+ 
+     if( input_offset < len ) {
+       int size = len - input_offset;
+       const char *chunk = PTRCAST(char, input_field->data + input_offset);
+       int terminate = done? 1 : 0;
+ 
+       auto erc = (xmlParserErrors )xmlParseChunk( ctxt, chunk, size, terminate );
+       if( erc != 0 ) {
+         auto msg = xmlerror_str(erc);
+         syslog(priority, "XML PARSE: XML error: %s", msg);
+       }
+ 
+       if( done ) this->done();
+ 
+     }
+   }
+ 
+   void done() {
+     if( ctxt ) {
+       xmlFreeParserCtxt( ctxt );
+       ctxt = nullptr;
+     }
+   }
+ 
+  protected:
+   void init() {
+     const char *external_entities = nullptr;
+     void * const user_data = nullptr;
+ 
+     ctxt = xmlCreatePushParserCtxt( &handlers, user_data,
+                                     nullptr, 0, external_entities);
+   }
+ } context;
+ 
+ static int
+ xml_push_parse( cblc_field_t *input_field,
+                   size_t        input_offset,
+                   size_t        len,
+                   cblc_field_t *encoding __attribute__ ((unused)),
+                   cblc_field_t *validating __attribute__ ((unused)),
+                   int           returns_national __attribute__ ((unused)),
+                   void (*callback)(void) )
+ {
+   ::cobol_callback = callback;
+ 
+   context.push( input_field, input_offset, len, false);
+ 
+ #if LIBXML_VERSION >= 21400
+   const xmlChar * version = xmlCtxtGetVersion( context.ctxt );
+ #else
+   const xmlChar * version = xmlchar_of("requires version 2.14");
+ #endif
+   assert(version);
+   assert(nullptr == "function not ready and not called");
+   return 0;
+ }
+ 
+ 
+ extern "C"  // Parser calls via parser_xml_parse_end, probabably.
+ int
+ __gg__xml_parse_done() {
+   context.done();
+   return 0;
+ }
+ 
+ 
  extern "C"
! int
  __gg__xml_parse(  const cblc_field_t *input_field,
                    size_t        input_offset,
                    size_t        len,
!                   cblc_field_t *encoding __attribute__ ((unused)),
!                   cblc_field_t *validating __attribute__ ((unused)),
!                   int           returns_national __attribute__ ((unused)),
                    void (*callback)(void) )
  {
    initialize_handlers(callback);
*************** __gg__xml_parse(  const cblc_field_t *in
*** 582,588 ****
    int erc = xmlSAXUserParseMemory(&handlers, nullptr, input, len);
  
    if( erc ) {
!     const xmlError* msg = xmlCtxtGetLastError(nullptr);
      fprintf(stderr, "XML PARSE: error: line %d: %s (%d: %d.%d.%d)\n",
              msg->line, msg->message, erc, msg->domain, msg->level, msg->code);
    }
--- 769,775 ----
    int erc = xmlSAXUserParseMemory(&handlers, nullptr, input, len);
  
    if( erc ) {
!     const xmlError *msg = xmlCtxtGetLastError(nullptr);
      fprintf(stderr, "XML PARSE: error: line %d: %s (%d: %d.%d.%d)\n",
              msg->line, msg->message, erc, msg->domain, msg->level, msg->code);
    }
diff -Nrcpad gcc-16-20251026/libgomp/ChangeLog gcc-16-20251102/libgomp/ChangeLog
*** gcc-16-20251026/libgomp/ChangeLog	Sun Oct 26 22:33:08 2025
--- gcc-16-20251102/libgomp/ChangeLog	Sun Nov  2 22:34:20 2025
***************
*** 1,3 ****
--- 1,7 ----
+ 2025-10-28  Thomas Schwinge  <tschwinge@baylibre.com>
+ 
+ 	* env.c (initialize_env): Simplify 'parse_stacksize' call.
+ 
  2025-10-23  Andrew Stubbs  <ams@baylibre.com>
  
  	* Makefile.am (libgomp_la_SOURCES): Add simple-allocator.c.
diff -Nrcpad gcc-16-20251026/libgomp/env.c gcc-16-20251102/libgomp/env.c
*** gcc-16-20251026/libgomp/env.c	Sun Oct 26 22:33:08 2025
--- gcc-16-20251102/libgomp/env.c	Sun Nov  2 22:34:20 2025
*************** initialize_env (void)
*** 2455,2461 ****
        const char *env = getenv ("GOMP_STACKSIZE");
        if (env != NULL
  	  && parse_stacksize ("GOMP_STACKSIZE", env,
! 			      (void *[3]) {&none->icvs.stacksize}))
  	gomp_set_icv_flag (&none->flags, GOMP_ICV_STACKSIZE);
      }
    if (none != NULL && gomp_get_icv_flag (none->flags, GOMP_ICV_STACKSIZE))
--- 2455,2461 ----
        const char *env = getenv ("GOMP_STACKSIZE");
        if (env != NULL
  	  && parse_stacksize ("GOMP_STACKSIZE", env,
! 			      (void *[]) {&none->icvs.stacksize}))
  	gomp_set_icv_flag (&none->flags, GOMP_ICV_STACKSIZE);
      }
    if (none != NULL && gomp_get_icv_flag (none->flags, GOMP_ICV_STACKSIZE))
diff -Nrcpad gcc-16-20251026/libgrust/ChangeLog gcc-16-20251102/libgrust/ChangeLog
*** gcc-16-20251026/libgrust/ChangeLog	Sun Oct 26 22:33:09 2025
--- gcc-16-20251102/libgrust/ChangeLog	Sun Nov  2 22:34:21 2025
***************
*** 1,3 ****
--- 1,261 ----
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* libformat_parser/src/lib.rs (struct FFIOpt): Likewise and
+ 	remove some now-redundant methods.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rustc-lib/stdarch/.cirrus.yml: New file.
+ 	* rustc-lib/stdarch/.github/workflows/main.yml: New file.
+ 	* rustc-lib/stdarch/.gitignore: New file.
+ 	* rustc-lib/stdarch/CONTRIBUTING.md: New file.
+ 	* rustc-lib/stdarch/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/LICENSE-APACHE: New file.
+ 	* rustc-lib/stdarch/LICENSE-MIT: New file.
+ 	* rustc-lib/stdarch/README.md: New file.
+ 	* rustc-lib/stdarch/ci/android-install-ndk.sh: New file.
+ 	* rustc-lib/stdarch/ci/android-install-sdk.sh: New file.
+ 	* rustc-lib/stdarch/ci/android-sysimage.sh: New file.
+ 	* rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile: New file.
+ 	* rustc-lib/stdarch/ci/dox.sh: New file.
+ 	* rustc-lib/stdarch/ci/gba.json: New file.
+ 	* rustc-lib/stdarch/ci/run-docker.sh: New file.
+ 	* rustc-lib/stdarch/ci/run.sh: New file.
+ 	* rustc-lib/stdarch/ci/runtest-android.rs: New file.
+ 	* rustc-lib/stdarch/ci/style.sh: New file.
+ 	* rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/assert-instr-macro/build.rs: New file.
+ 	* rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/LICENSE-MIT: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/README.md: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/avx512f.md: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/build.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/rustfmt.toml: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/v6.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/arm/v7.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/core_arch_docs.md: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/lib.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/macros.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/mips/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/mips/msa.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/mips/msa/macros.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/nvptx/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/powerpc/altivec.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/powerpc/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/powerpc/vsx.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/powerpc64/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/simd.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/simd_llvm.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/v64.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/wasm32/atomic.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/wasm32/memory.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/wasm32/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/wasm32/simd128.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/abm.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/adx.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/aes.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/avx.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/avx2.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/avx512f.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/bmi1.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/bmi2.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/bswap.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/bt.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/cpuid.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/eflags.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/f16c.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/fma.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/fxsr.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/macros.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/pclmulqdq.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/rdrand.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/rdtsc.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/rtm.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sha.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sse.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sse2.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sse3.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sse41.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sse42.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/sse4a.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/test.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86/xsave.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/adx.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/avx2.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse2.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs: New file.
+ 	* rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs: New file.
+ 	* rustc-lib/stdarch/crates/simd-test-macro/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/simd-test-macro/src/lib.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/LICENSE-APACHE: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/LICENSE-MIT: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/README.md: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/arm.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-x64-i7-6850k.auxv:
+ 	New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv:
+ 	New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/lib.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/src/mod.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs: New file.
+ 	* rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-gen/README.md: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-gen/neon.spec: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-gen/src/main.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-test/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-test/src/lib.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/.gitattributes: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/build.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs: New file.
+ 	* rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml: New file.
+ 	* rustc-lib/stdarch/examples/Cargo.toml: New file.
+ 	* rustc-lib/stdarch/examples/hex.rs: New file.
+ 	* rustc-lib/stdarch/examples/wasm.rs: New file.
+ 	* rustc-lib/stdarch/triagebot.toml: New file.
+ 	* rustc-lib/stdarch/vendor.yml: New file.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* rustc-lib/LICENSE-APACHE: New file.
+ 	* rustc-lib/LICENSE-MIT: New file.
+ 	* rustc-lib/version-info: New file.
+ 
+ 2025-10-30  Owen Avery  <powerboat9.gamer@gmail.com>
+ 
+ 	* libformat_parser/src/lib.rs (struct FFIVec): New.
+ 	(trait StringLeakExt): Remove.
+ 	(struct FFIOpt): New.
+ 	(trait IntoFFI): Adjust implementation for Option.
+ 	(struct RustHamster): Add lifetime and adjust conversion to and
+ 	from &str.
+ 	(enum Piece): Adjust definition to handle changes to
+ 	RustHamster.
+ 	(struct Argument): Likewise.
+ 	(struct FormatSpec): Use FFIOpt and RustHamster.
+ 	(enum Position): Use RustHamster.
+ 	(enum Count): Likewise.
+ 	(struct PieceSlice): Replace with...
+ 	(typedef PieceVec): ...this.
+ 	(struct RustString): Remove.
+ 	(struct FormatArgsHandle): Likewise.
+ 	(fn collect_pieces): Adjust signature, greatly simplifying
+ 	implementation.
+ 	(fn clone_pieces): Likewise.
+ 	(fn destroy_pieces): Remove.
+ 	(trait LayoutExt): New.
+ 	(fn rust_ffi_alloc): New.
+ 	(fn rust_ffi_dealloc): New.
+ 
  2025-10-05  Sam James  <sam@gentoo.org>
  
  	* Makefile.in: Regenerate.
diff -Nrcpad gcc-16-20251026/libgrust/libformat_parser/src/lib.rs gcc-16-20251102/libgrust/libformat_parser/src/lib.rs
*** gcc-16-20251026/libgrust/libformat_parser/src/lib.rs	Sun Oct 26 22:33:09 2025
--- gcc-16-20251102/libgrust/libformat_parser/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 1,56 ****
  //! FFI interface for `rustc_format_parser`
  
  // what's the plan? Have a function return something that can be constructed into a vector?
  // or an iterator?
  
- use std::ffi::CStr;
- 
  trait IntoFFI<T> {
      fn into_ffi(self) -> T;
  }
  
! impl<T> IntoFFI<*const T> for Option<T>
! where
!     T: Sized,
! {
!     fn into_ffi(self) -> *const T {
!         match self.as_ref() {
!             None => std::ptr::null(),
!             Some(r) => r as *const T,
          }
      }
- }
  
! // Extension trait to provide `String::leak` which did not exist in Rust 1.49
! pub trait StringLeakExt {
!     fn leak<'a>(self) -> &'a mut str;
! }
  
! impl StringLeakExt for String {
!     fn leak<'a>(self) -> &'a mut str {
!         Box::leak(self.into_boxed_str())
      }
- }
  
! // FIXME: Make an ffi module in a separate file
! // FIXME: Remember to leak the boxed type somehow
! // FIXME: How to encode the Option type? As a pointer? Option<T> -> Option<&T> -> *const T could work maybe?
! pub mod ffi {
!     use super::IntoFFI;
  
      // FIXME: We need to ensure we deal with memory properly - whether it's owned by the C++ side or the Rust side
      #[derive(Copy, Clone, PartialEq, Eq, Debug)]
      #[repr(C)]
!     pub struct RustHamster {
          ptr: *const u8,
          len: usize,
      }
  
!     impl<'a> From<&'a str> for RustHamster {
!         fn from(s: &'a str) -> RustHamster {
              RustHamster {
!                 ptr: s.as_ptr(),
!                 len: s.len(),
              }
          }
      }
--- 1,129 ----
  //! FFI interface for `rustc_format_parser`
  
+ use std::alloc::Layout;
+ 
  // what's the plan? Have a function return something that can be constructed into a vector?
  // or an iterator?
  
  trait IntoFFI<T> {
      fn into_ffi(self) -> T;
  }
  
! // FIXME: Make an ffi module in a separate file
! // FIXME: Remember to leak the boxed type somehow
! // FIXME: How to encode the Option type? As a pointer? Option<T> -> Option<&T> -> *const T could work maybe?
! pub mod ffi {
!     use super::IntoFFI;
!     use std::marker::PhantomData;
!     use std::mem::MaybeUninit;
! 
!     #[repr(C)]
!     pub struct FFIVec<T> {
!         data: *mut T,
!         len: usize,
!         cap: usize
!     }
! 
!     impl<T> IntoFFI<FFIVec<T>> for Vec<T> {
!         fn into_ffi(mut self) -> FFIVec<T> {
!             let ret = FFIVec {
!                 data: self.as_mut_ptr(),
!                 len: self.len(),
!                 cap: self.capacity()
!             };
!             self.leak();
!             ret
          }
      }
  
!     impl<T> Drop for FFIVec<T> {
!         fn drop(&mut self) {
!             unsafe {
!                 Vec::from_raw_parts(self.data, self.len, self.cap);
!             }
!         }
!     }
  
!     impl<T> FFIVec<T> {
!         fn with_vec_ref<R, F: for<'a> FnOnce(&'a Vec<T>) -> R>(
!             &self, f: F
!         ) -> R {
!             let v = unsafe {
!                 Vec::from_raw_parts(self.data, self.len, self.cap)
!             };
!             let ret = f(&v);
!             v.leak();
!             ret
!         }
! 
!         // currently unused
!         // may be nice to have later, though
!         #[allow(unused)]
!         fn with_vec_mut_ref<R, F: for<'a> FnOnce(&'a mut Vec<T>) -> R>(
!             &mut self, f: F
!         ) -> R {
!             let mut v = unsafe {
!                 Vec::from_raw_parts(self.data, self.len, self.cap)
!             };
!             let ret = f(&mut v);
!             self.data = v.as_mut_ptr();
!             self.len = v.len();
!             self.cap = v.capacity();
!             v.leak();
!             ret
!         }
      }
  
!     impl<T> Clone for FFIVec<T>
!     where
!         T: Clone
!     {
!         fn clone(&self) -> FFIVec<T> {
!             self.with_vec_ref(|v| v.clone().into_ffi())
!         }
!     }
! 
!     // https://github.com/rust-lang/rfcs/blob/master/text/2195-really-tagged-unions.md
!     #[repr(u8)]
!     #[derive(Copy, Clone, PartialEq, Eq)]
!     pub enum FFIOpt<T> {
!         Some(T),
!         None
!     }
! 
!     impl<T> IntoFFI<FFIOpt<T>> for Option<T> {
!         fn into_ffi(self) -> FFIOpt<T> {
!             match self {
!                 Some(v) => FFIOpt::Some(v),
!                 None => FFIOpt::None
!             }
!         }
!     }
  
      // FIXME: We need to ensure we deal with memory properly - whether it's owned by the C++ side or the Rust side
      #[derive(Copy, Clone, PartialEq, Eq, Debug)]
      #[repr(C)]
!     pub struct RustHamster<'a> {
          ptr: *const u8,
          len: usize,
+         phantom: PhantomData<&'a u8>
      }
  
!     impl<'a> IntoFFI<RustHamster<'a>> for &'a str {
!         fn into_ffi(self) -> RustHamster<'a> {
              RustHamster {
!                 ptr: self.as_ptr(),
!                 len: self.len(),
!                 phantom: PhantomData,
!             }
!         }
!     }
! 
!     impl<'a> RustHamster<'a> {
!         pub fn as_str(&self) -> &'a str {
!             unsafe {
!                 let slice: &'a [u8] = std::slice::from_raw_parts(self.ptr, self.len);
!                 std::str::from_utf8_unchecked(slice)
              }
          }
      }
*************** pub mod ffi {
*** 101,111 ****
  
      /// A piece is a portion of the format string which represents the next part
      /// to emit. These are emitted as a stream by the `Parser` class.
!     #[derive(Debug, Clone, PartialEq)]
      #[repr(C)]
      pub enum Piece<'a> {
          /// A literal string which should directly be emitted
!         String(RustHamster),
          /// This describes that formatting should process the next argument (as
          /// specified inside) for emission.
          // do we need a pointer here? we're doing big cloning anyway
--- 174,184 ----
  
      /// A piece is a portion of the format string which represents the next part
      /// to emit. These are emitted as a stream by the `Parser` class.
!     #[derive(Clone)]
      #[repr(C)]
      pub enum Piece<'a> {
          /// A literal string which should directly be emitted
!         String(RustHamster<'a>),
          /// This describes that formatting should process the next argument (as
          /// specified inside) for emission.
          // do we need a pointer here? we're doing big cloning anyway
*************** pub mod ffi {
*** 113,119 ****
      }
  
      /// Representation of an argument specification.
!     #[derive(Copy, Clone, Debug, PartialEq)]
      #[repr(C)]
      pub struct Argument<'a> {
          /// Where to find this argument
--- 186,192 ----
      }
  
      /// Representation of an argument specification.
!     #[derive(Clone)]
      #[repr(C)]
      pub struct Argument<'a> {
          /// Where to find this argument
*************** pub mod ffi {
*** 126,162 ****
      }
  
      /// Specification for the formatting of an argument in the format string.
!     #[derive(Copy, Clone, Debug, PartialEq)]
      #[repr(C)]
      pub struct FormatSpec<'a> {
          /// Optionally specified character to fill alignment with.
!         pub fill: Option<char>,
          /// Span of the optionally specified fill character.
!         pub fill_span: *const InnerSpan,
          /// Optionally specified alignment.
          pub align: Alignment,
          /// The `+` or `-` flag.
!         pub sign: *const Sign,
          /// The `#` flag.
          pub alternate: bool,
          /// The `0` flag.
          pub zero_pad: bool,
          /// The `x` or `X` flag. (Only for `Debug`.)
!         pub debug_hex: *const DebugHex,
          /// The integer precision to use.
          pub precision: Count<'a>,
          /// The span of the precision formatting flag (for diagnostics).
!         pub precision_span: *const InnerSpan,
          /// The string width requested for the resulting format.
          pub width: Count<'a>,
          /// The span of the width formatting flag (for diagnostics).
!         pub width_span: *const InnerSpan,
          /// The descriptor string representing the name of the format desired for
          /// this argument, this can be empty or any number of characters, although
          /// it is required to be one word.
!         pub ty: &'a str,
          /// The span of the descriptor string (for diagnostics).
!         pub ty_span: *const InnerSpan,
      }
  
      /// Enum describing where an argument for a format can be located.
--- 199,235 ----
      }
  
      /// Specification for the formatting of an argument in the format string.
!     #[derive(Clone)]
      #[repr(C)]
      pub struct FormatSpec<'a> {
          /// Optionally specified character to fill alignment with.
!         pub fill: FFIOpt<char>,
          /// Span of the optionally specified fill character.
!         pub fill_span: FFIOpt<InnerSpan>,
          /// Optionally specified alignment.
          pub align: Alignment,
          /// The `+` or `-` flag.
!         pub sign: FFIOpt<Sign>,
          /// The `#` flag.
          pub alternate: bool,
          /// The `0` flag.
          pub zero_pad: bool,
          /// The `x` or `X` flag. (Only for `Debug`.)
!         pub debug_hex: FFIOpt<DebugHex>,
          /// The integer precision to use.
          pub precision: Count<'a>,
          /// The span of the precision formatting flag (for diagnostics).
!         pub precision_span: FFIOpt<InnerSpan>,
          /// The string width requested for the resulting format.
          pub width: Count<'a>,
          /// The span of the width formatting flag (for diagnostics).
!         pub width_span: FFIOpt<InnerSpan>,
          /// The descriptor string representing the name of the format desired for
          /// this argument, this can be empty or any number of characters, although
          /// it is required to be one word.
!         pub ty: RustHamster<'a>,
          /// The span of the descriptor string (for diagnostics).
!         pub ty_span: FFIOpt<InnerSpan>,
      }
  
      /// Enum describing where an argument for a format can be located.
*************** pub mod ffi {
*** 168,174 ****
          /// The argument is located at a specific index given in the format,
          ArgumentIs(usize),
          /// The argument has a name.
!         ArgumentNamed(&'a str),
      }
  
      /// Enum of alignments which are supported.
--- 241,247 ----
          /// The argument is located at a specific index given in the format,
          ArgumentIs(usize),
          /// The argument has a name.
!         ArgumentNamed(RustHamster<'a>),
      }
  
      /// Enum of alignments which are supported.
*************** pub mod ffi {
*** 213,219 ****
          /// The count is specified explicitly.
          CountIs(usize),
          /// The count is specified by the argument with the given name.
!         CountIsName(&'a str, InnerSpan),
          /// The count is specified by the argument at the given index.
          CountIsParam(usize),
          /// The count is specified by a star (like in `{:.*}`) that refers to the argument at the given index.
--- 286,292 ----
          /// The count is specified explicitly.
          CountIs(usize),
          /// The count is specified by the argument with the given name.
!         CountIsName(RustHamster<'a>, InnerSpan),
          /// The count is specified by the argument at the given index.
          CountIsParam(usize),
          /// The count is specified by a star (like in `{:.*}`) that refers to the argument at the given index.
*************** pub mod ffi {
*** 225,231 ****
      impl<'a> From<generic_format_parser::Piece<'a>> for Piece<'a> {
          fn from(old: generic_format_parser::Piece<'a>) -> Self {
              match old {
!                 generic_format_parser::Piece::String(x) => Piece::String(x.into()),
                  generic_format_parser::Piece::NextArgument(x) => {
                      // FIXME: This is problematic - if we do this, then we probably run into the issue that the Box
                      // is freed at the end of the call to collect_pieces. if we just .leak() it, then we have
--- 298,304 ----
      impl<'a> From<generic_format_parser::Piece<'a>> for Piece<'a> {
          fn from(old: generic_format_parser::Piece<'a>) -> Self {
              match old {
!                 generic_format_parser::Piece::String(x) => Piece::String(x.into_ffi()),
                  generic_format_parser::Piece::NextArgument(x) => {
                      // FIXME: This is problematic - if we do this, then we probably run into the issue that the Box
                      // is freed at the end of the call to collect_pieces. if we just .leak() it, then we have
*************** pub mod ffi {
*** 259,265 ****
                  }
                  generic_format_parser::Position::ArgumentIs(x) => Position::ArgumentIs(x.into()),
                  generic_format_parser::Position::ArgumentNamed(x) => {
!                     Position::ArgumentNamed(x.into())
                  }
              }
          }
--- 332,338 ----
                  }
                  generic_format_parser::Position::ArgumentIs(x) => Position::ArgumentIs(x.into()),
                  generic_format_parser::Position::ArgumentNamed(x) => {
!                     Position::ArgumentNamed(x.into_ffi())
                  }
              }
          }
*************** pub mod ffi {
*** 277,283 ****
      impl<'a> From<generic_format_parser::FormatSpec<'a>> for FormatSpec<'a> {
          fn from(old: generic_format_parser::FormatSpec<'a>) -> Self {
              FormatSpec {
!                 fill: old.fill,
                  fill_span: old.fill_span.map(Into::into).into_ffi(),
                  align: old.align.into(),
                  sign: old.sign.map(Into::into).into_ffi(),
--- 350,356 ----
      impl<'a> From<generic_format_parser::FormatSpec<'a>> for FormatSpec<'a> {
          fn from(old: generic_format_parser::FormatSpec<'a>) -> Self {
              FormatSpec {
!                 fill: old.fill.into_ffi(),
                  fill_span: old.fill_span.map(Into::into).into_ffi(),
                  align: old.align.into(),
                  sign: old.sign.map(Into::into).into_ffi(),
*************** pub mod ffi {
*** 288,294 ****
                  precision_span: old.precision_span.map(Into::into).into_ffi(),
                  width: old.width.into(),
                  width_span: old.width_span.map(Into::into).into_ffi(),
!                 ty: old.ty,
                  ty_span: old.ty_span.map(Into::into).into_ffi(),
              }
          }
--- 361,367 ----
                  precision_span: old.precision_span.map(Into::into).into_ffi(),
                  width: old.width.into(),
                  width_span: old.width_span.map(Into::into).into_ffi(),
!                 ty: old.ty.into_ffi(),
                  ty_span: old.ty_span.map(Into::into).into_ffi(),
              }
          }
*************** pub mod ffi {
*** 307,313 ****
          fn from(old: generic_format_parser::Count<'a>) -> Self {
              match old {
                  generic_format_parser::Count::CountIs(x) => Count::CountIs(x),
!                 generic_format_parser::Count::CountIsName(x, y) => Count::CountIsName(x, y.into()),
                  generic_format_parser::Count::CountIsParam(x) => Count::CountIsParam(x),
                  generic_format_parser::Count::CountIsStar(x) => Count::CountIsStar(x),
                  generic_format_parser::Count::CountImplied => Count::CountImplied,
--- 380,386 ----
          fn from(old: generic_format_parser::Count<'a>) -> Self {
              match old {
                  generic_format_parser::Count::CountIs(x) => Count::CountIs(x),
!                 generic_format_parser::Count::CountIsName(x, y) => Count::CountIsName(x.into_ffi(), y.into()),
                  generic_format_parser::Count::CountIsParam(x) => Count::CountIsParam(x),
                  generic_format_parser::Count::CountIsStar(x) => Count::CountIsStar(x),
                  generic_format_parser::Count::CountImplied => Count::CountImplied,
*************** pub mod rust {
*** 357,456 ****
  }
  
  // TODO: Should we instead make an FFIVector struct?
! #[repr(C)]
! pub struct PieceSlice {
!     base_ptr: *mut ffi::Piece<'static /* FIXME: That's wrong */>,
!     len: usize,
!     cap: usize,
! }
! 
! #[repr(C)]
! // FIXME: we should probably use FFIString here
! pub struct RustString {
!     ptr: *const u8,
!     len: usize,
!     cap: usize,
! }
! 
! #[repr(C)]
! pub struct FormatArgsHandle(PieceSlice, RustString);
  
  #[no_mangle]
! pub extern "C" fn collect_pieces(
!     input: *const libc::c_char,
      append_newline: bool,
      parse_mode: crate::ffi::ParseMode,
! ) -> FormatArgsHandle {
!     // FIXME: Add comment
!     let str = unsafe { CStr::from_ptr(input) };
!     let str = str.to_str().unwrap().to_owned();
! 
!     // we are never going to free this string here (we leak it later on), so we can extend its lifetime
!     // to send it across an FFI boundary.
!     // FIXME: Is that correct?
!     let s = &str;
!     let s = unsafe { std::mem::transmute::<&'_ str, &'static str>(s) };
! 
      // FIXME: No unwrap
      let pieces: Vec<ffi::Piece<'_>> =
!         rust::collect_pieces(s, None, None, append_newline, parse_mode)
              .into_iter()
              .map(Into::into)
              .collect();
  
!     let piece_slice = PieceSlice {
!         len: pieces.len(),
!         cap: pieces.capacity(),
!         base_ptr: pieces.leak().as_mut_ptr(),
!     };
!     let rust_string = RustString {
!         len: str.len(),
!         cap: str.capacity(),
!         ptr: str.leak().as_ptr(),
!     };
! 
!     FormatArgsHandle(piece_slice, rust_string)
  }
  
  #[no_mangle]
! pub unsafe extern "C" fn destroy_pieces(FormatArgsHandle(piece_slice, s): FormatArgsHandle) {
!     let PieceSlice { base_ptr, len, cap } = piece_slice;
!     drop(Vec::from_raw_parts(base_ptr, len, cap));
! 
!     let RustString { ptr, len, cap } = s;
!     drop(String::from_raw_parts(ptr as *mut u8, len, cap));
  }
  
! #[no_mangle]
! pub extern "C" fn clone_pieces(
!     FormatArgsHandle(piece_slice, s): &FormatArgsHandle,
! ) -> FormatArgsHandle {
!     let PieceSlice { base_ptr, len, cap } = *piece_slice;
! 
!     let v = unsafe { Vec::from_raw_parts(base_ptr, len, cap) };
!     let cloned_v = v.clone();
! 
!     // FIXME: Add documentation
!     v.leak();
! 
!     let piece_slice = PieceSlice {
!         len: cloned_v.len(),
!         cap: cloned_v.capacity(),
!         base_ptr: cloned_v.leak().as_mut_ptr(),
!     };
! 
!     let RustString { ptr, len, cap } = *s;
!     let s = unsafe { String::from_raw_parts(ptr as *mut u8, len, cap) };
!     let cloned_s = s.clone();
  
!     // FIXME: Documentation
!     s.leak();
  
!     let rust_string = RustString {
!         len: cloned_s.len(),
!         cap: cloned_s.capacity(),
!         ptr: cloned_s.leak().as_ptr(),
!     };
  
!     FormatArgsHandle(piece_slice, rust_string)
  }
--- 430,495 ----
  }
  
  // TODO: Should we instead make an FFIVector struct?
! type PieceVec<'a> = ffi::FFIVec<ffi::Piece<'a>>;
  
  #[no_mangle]
! pub extern "C" fn collect_pieces<'a>(
!     input: ffi::RustHamster<'a>,
      append_newline: bool,
      parse_mode: crate::ffi::ParseMode,
! ) -> PieceVec<'a> {
      // FIXME: No unwrap
      let pieces: Vec<ffi::Piece<'_>> =
!         rust::collect_pieces(input.as_str(), None, None, append_newline, parse_mode)
              .into_iter()
              .map(Into::into)
              .collect();
  
!     pieces.into_ffi()
  }
  
  #[no_mangle]
! pub extern "C" fn clone_pieces<'a, 'b>(
!     piece_vec: &'a PieceVec<'b>
! ) -> PieceVec<'b> {
!     piece_vec.clone()
  }
  
! // we need Layout::repeat
! // function signature is a bit different, so call it repeat_x
! trait LayoutExt {
!     fn repeat_x(&self, n: usize) -> Layout;
! }
  
! impl LayoutExt for Layout {
!     fn repeat_x(&self, n: usize) -> Layout {
!         let elem = self.pad_to_align();
!         let total_size = elem.size().checked_mul(n).unwrap();
!         Layout::from_size_align(total_size, elem.align()).unwrap()
!     }
! }
  
! #[no_mangle]
! pub unsafe extern "C" fn rust_ffi_alloc(
!     count: usize, elem_size: usize, align: usize
! ) -> *mut u8 {
!     unsafe {
!         std::alloc::alloc(
!             Layout::from_size_align_unchecked(elem_size, align)
!                 .repeat_x(count)
!         )
!     }
! }
  
! #[no_mangle]
! pub unsafe extern "C" fn rust_ffi_dealloc(
!     data: *mut u8, count: usize, elem_size: usize, align: usize
! ) {
!     unsafe {
!         std::alloc::dealloc(
!             data,
!             Layout::from_size_align_unchecked(elem_size, align)
!                 .repeat_x(count)
!         )
!     }
  }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/LICENSE-APACHE gcc-16-20251102/libgrust/rustc-lib/LICENSE-APACHE
*** gcc-16-20251026/libgrust/rustc-lib/LICENSE-APACHE	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/LICENSE-APACHE	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,176 ----
+                               Apache License
+                         Version 2.0, January 2004
+                      http://www.apache.org/licenses/
+ 
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+ 
+ 1. Definitions.
+ 
+    "License" shall mean the terms and conditions for use, reproduction,
+    and distribution as defined by Sections 1 through 9 of this document.
+ 
+    "Licensor" shall mean the copyright owner or entity authorized by
+    the copyright owner that is granting the License.
+ 
+    "Legal Entity" shall mean the union of the acting entity and all
+    other entities that control, are controlled by, or are under common
+    control with that entity. For the purposes of this definition,
+    "control" means (i) the power, direct or indirect, to cause the
+    direction or management of such entity, whether by contract or
+    otherwise, or (ii) ownership of fifty percent (50%) or more of the
+    outstanding shares, or (iii) beneficial ownership of such entity.
+ 
+    "You" (or "Your") shall mean an individual or Legal Entity
+    exercising permissions granted by this License.
+ 
+    "Source" form shall mean the preferred form for making modifications,
+    including but not limited to software source code, documentation
+    source, and configuration files.
+ 
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+    transformation or translation of a Source form, including but
+    not limited to compiled object code, generated documentation,
+    and conversions to other media types.
+ 
+    "Work" shall mean the work of authorship, whether in Source or
+    Object form, made available under the License, as indicated by a
+    copyright notice that is included in or attached to the work
+    (an example is provided in the Appendix below).
+ 
+    "Derivative Works" shall mean any work, whether in Source or Object
+    form, that is based on (or derived from) the Work and for which the
+    editorial revisions, annotations, elaborations, or other modifications
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+    of this License, Derivative Works shall not include works that remain
+    separable from, or merely link (or bind by name) to the interfaces of,
+    the Work and Derivative Works thereof.
+ 
+    "Contribution" shall mean any work of authorship, including
+    the original version of the Work and any modifications or additions
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+    on behalf of whom a Contribution has been received by Licensor and
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+ 
+ 2. Grant of Copyright License. Subject to the terms and conditions of
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+    Contribution(s) alone or by combination of their Contribution(s)
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+    or a Contribution incorporated within the Work constitutes direct
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+ 
+ 4. Redistribution. You may reproduce and distribute copies of the
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+    meet the following conditions:
+ 
+    (a) You must give any other recipients of the Work or
+        Derivative Works a copy of this License; and
+ 
+    (b) You must cause any modified files to carry prominent notices
+        stating that You changed the files; and
+ 
+    (c) You must retain, in the Source form of any Derivative Works
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+ 
+    (d) If the Work includes a "NOTICE" text file as part of its
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+        as part of the Derivative Works; within the Source form or
+        documentation, if provided along with the Derivative Works; or,
+        within a display generated by the Derivative Works, if and
+        wherever such third-party notices normally appear. The contents
+        of the NOTICE file are for informational purposes only and
+        do not modify the License. You may add Your own attribution
+        notices within Derivative Works that You distribute, alongside
+        or as an addendum to the NOTICE text from the Work, provided
+        that such additional attribution notices cannot be construed
+        as modifying the License.
+ 
+    You may add Your own copyright statement to Your modifications and
+    may provide additional or different license terms and conditions
+    for use, reproduction, or distribution of Your modifications, or
+    for any such Derivative Works as a whole, provided Your use,
+    reproduction, and distribution of the Work otherwise complies with
+    the conditions stated in this License.
+ 
+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+    any Contribution intentionally submitted for inclusion in the Work
+    by You to the Licensor shall be under the terms and conditions of
+    this License, without any additional terms or conditions.
+    Notwithstanding the above, nothing herein shall supersede or modify
+    the terms of any separate license agreement you may have executed
+    with Licensor regarding such Contributions.
+ 
+ 6. Trademarks. This License does not grant permission to use the trade
+    names, trademarks, service marks, or product names of the Licensor,
+    except as required for reasonable and customary use in describing the
+    origin of the Work and reproducing the content of the NOTICE file.
+ 
+ 7. Disclaimer of Warranty. Unless required by applicable law or
+    agreed to in writing, Licensor provides the Work (and each
+    Contributor provides its Contributions) on an "AS IS" BASIS,
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+    PARTICULAR PURPOSE. You are solely responsible for determining the
+    appropriateness of using or redistributing the Work and assume any
+    risks associated with Your exercise of permissions under this License.
+ 
+ 8. Limitation of Liability. In no event and under no legal theory,
+    whether in tort (including negligence), contract, or otherwise,
+    unless required by applicable law (such as deliberate and grossly
+    negligent acts) or agreed to in writing, shall any Contributor be
+    liable to You for damages, including any direct, indirect, special,
+    incidental, or consequential damages of any character arising as a
+    result of this License or out of the use or inability to use the
+    Work (including but not limited to damages for loss of goodwill,
+    work stoppage, computer failure or malfunction, or any and all
+    other commercial damages or losses), even if such Contributor
+    has been advised of the possibility of such damages.
+ 
+ 9. Accepting Warranty or Additional Liability. While redistributing
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+    on Your own behalf and on Your sole responsibility, not on behalf
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+    defend, and hold each Contributor harmless for any liability
+    incurred by, or claims asserted against, such Contributor by reason
+    of your accepting any such warranty or additional liability.
+ 
+ END OF TERMS AND CONDITIONS
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/LICENSE-MIT gcc-16-20251102/libgrust/rustc-lib/LICENSE-MIT
*** gcc-16-20251026/libgrust/rustc-lib/LICENSE-MIT	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/LICENSE-MIT	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,23 ----
+ Permission is hereby granted, free of charge, to any
+ person obtaining a copy of this software and associated
+ documentation files (the "Software"), to deal in the
+ Software without restriction, including without
+ limitation the rights to use, copy, modify, merge,
+ publish, distribute, sublicense, and/or sell copies of
+ the Software, and to permit persons to whom the Software
+ is furnished to do so, subject to the following
+ conditions:
+ 
+ The above copyright notice and this permission notice
+ shall be included in all copies or substantial portions
+ of the Software.
+ 
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+ SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+ IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/core/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/core/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,27 ----
+ [package]
+ authors = ["The Rust Project Developers"]
+ name = "core"
+ version = "0.0.0"
+ autotests = false
+ autobenches = false
+ edition = "2018"
+ 
+ [lib]
+ test = false
+ bench = false
+ 
+ [[test]]
+ name = "coretests"
+ path = "tests/lib.rs"
+ 
+ [[bench]]
+ name = "corebenches"
+ path = "benches/lib.rs"
+ test = true
+ 
+ [dev-dependencies]
+ rand = "0.7"
+ 
+ [features]
+ # Make panics and failed asserts immediately abort without formatting any message
+ panic_immediate_abort = []
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/any.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/any.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/any.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/any.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,12 ----
+ use core::any::*;
+ use test::{black_box, Bencher};
+ 
+ #[bench]
+ fn bench_downcast_ref(b: &mut Bencher) {
+     b.iter(|| {
+         let mut x = 0;
+         let mut y = &mut x as &mut dyn Any;
+         black_box(&mut y);
+         black_box(y.downcast_ref::<isize>() == Some(&0));
+     });
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/ascii/is_ascii.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/ascii/is_ascii.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/ascii/is_ascii.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/ascii/is_ascii.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,82 ----
+ use super::{LONG, MEDIUM, SHORT};
+ use test::black_box;
+ use test::Bencher;
+ 
+ macro_rules! benches {
+     ($( fn $name: ident($arg: ident: &[u8]) $body: block )+) => {
+         benches!(mod short SHORT[..] $($name $arg $body)+);
+         benches!(mod medium MEDIUM[..] $($name $arg $body)+);
+         benches!(mod long LONG[..] $($name $arg $body)+);
+         // Ensure we benchmark cases where the functions are called with strings
+         // that are not perfectly aligned or have a length which is not a
+         // multiple of size_of::<usize>() (or both)
+         benches!(mod unaligned_head MEDIUM[1..] $($name $arg $body)+);
+         benches!(mod unaligned_tail MEDIUM[..(MEDIUM.len() - 1)] $($name $arg $body)+);
+         benches!(mod unaligned_both MEDIUM[1..(MEDIUM.len() - 1)] $($name $arg $body)+);
+     };
+ 
+     (mod $mod_name: ident $input: ident [$range: expr] $($name: ident $arg: ident $body: block)+) => {
+         mod $mod_name {
+             use super::*;
+             $(
+                 #[bench]
+                 fn $name(bencher: &mut Bencher) {
+                     bencher.bytes = $input[$range].len() as u64;
+                     let mut vec = $input.as_bytes().to_vec();
+                     bencher.iter(|| {
+                         let $arg: &[u8] = &black_box(&mut vec)[$range];
+                         black_box($body)
+                     })
+                 }
+             )+
+         }
+     };
+ }
+ 
+ benches! {
+     fn case00_libcore(bytes: &[u8]) {
+         bytes.is_ascii()
+     }
+ 
+     fn case01_iter_all(bytes: &[u8]) {
+         bytes.iter().all(|b| b.is_ascii())
+     }
+ 
+     fn case02_align_to(bytes: &[u8]) {
+         is_ascii_align_to(bytes)
+     }
+ 
+     fn case03_align_to_unrolled(bytes: &[u8]) {
+         is_ascii_align_to_unrolled(bytes)
+     }
+ }
+ 
+ // These are separate since it's easier to debug errors if they don't go through
+ // macro expansion first.
+ fn is_ascii_align_to(bytes: &[u8]) -> bool {
+     if bytes.len() < core::mem::size_of::<usize>() {
+         return bytes.iter().all(|b| b.is_ascii());
+     }
+     // SAFETY: transmuting a sequence of `u8` to `usize` is always fine
+     let (head, body, tail) = unsafe { bytes.align_to::<usize>() };
+     head.iter().all(|b| b.is_ascii())
+         && body.iter().all(|w| !contains_nonascii(*w))
+         && tail.iter().all(|b| b.is_ascii())
+ }
+ 
+ fn is_ascii_align_to_unrolled(bytes: &[u8]) -> bool {
+     if bytes.len() < core::mem::size_of::<usize>() {
+         return bytes.iter().all(|b| b.is_ascii());
+     }
+     // SAFETY: transmuting a sequence of `u8` to `[usize; 2]` is always fine
+     let (head, body, tail) = unsafe { bytes.align_to::<[usize; 2]>() };
+     head.iter().all(|b| b.is_ascii())
+         && body.iter().all(|w| !contains_nonascii(w[0] | w[1]))
+         && tail.iter().all(|b| b.is_ascii())
+ }
+ 
+ #[inline]
+ fn contains_nonascii(v: usize) -> bool {
+     const NONASCII_MASK: usize = 0x80808080_80808080u64 as usize;
+     (NONASCII_MASK & v) != 0
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/ascii.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/ascii.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/ascii.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/ascii.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,351 ----
+ mod is_ascii;
+ 
+ // Lower-case ASCII 'a' is the first byte that has its highest bit set
+ // after wrap-adding 0x1F:
+ //
+ //     b'a' + 0x1F == 0x80 == 0b1000_0000
+ //     b'z' + 0x1F == 0x98 == 0b1001_1000
+ //
+ // Lower-case ASCII 'z' is the last byte that has its highest bit unset
+ // after wrap-adding 0x05:
+ //
+ //     b'a' + 0x05 == 0x66 == 0b0110_0110
+ //     b'z' + 0x05 == 0x7F == 0b0111_1111
+ //
+ // … except for 0xFB to 0xFF, but those are in the range of bytes
+ // that have the highest bit unset again after adding 0x1F.
+ //
+ // So `(byte + 0x1f) & !(byte + 5)` has its highest bit set
+ // iff `byte` is a lower-case ASCII letter.
+ //
+ // Lower-case ASCII letters all have the 0x20 bit set.
+ // (Two positions right of 0x80, the highest bit.)
+ // Unsetting that bit produces the same letter, in upper-case.
+ //
+ // Therefore:
+ fn branchless_to_ascii_upper_case(byte: u8) -> u8 {
+     byte & !((byte.wrapping_add(0x1f) & !byte.wrapping_add(0x05) & 0x80) >> 2)
+ }
+ 
+ macro_rules! benches {
+     ($( fn $name: ident($arg: ident: &mut [u8]) $body: block )+ @iter $( $is_: ident, )+) => {
+         benches! {@
+             $( fn $name($arg: &mut [u8]) $body )+
+             $( fn $is_(bytes: &mut [u8]) { bytes.iter().all(u8::$is_) } )+
+         }
+     };
+ 
+     (@$( fn $name: ident($arg: ident: &mut [u8]) $body: block )+) => {
+         benches!(mod short SHORT $($name $arg $body)+);
+         benches!(mod medium MEDIUM $($name $arg $body)+);
+         benches!(mod long LONG $($name $arg $body)+);
+     };
+ 
+     (mod $mod_name: ident $input: ident $($name: ident $arg: ident $body: block)+) => {
+         mod $mod_name {
+             use super::*;
+ 
+             $(
+                 #[bench]
+                 fn $name(bencher: &mut Bencher) {
+                     bencher.bytes = $input.len() as u64;
+                     bencher.iter(|| {
+                         let mut vec = $input.as_bytes().to_vec();
+                         {
+                             let $arg = &mut vec[..];
+                             black_box($body);
+                         }
+                         vec
+                     })
+                 }
+             )+
+         }
+     }
+ }
+ 
+ use test::black_box;
+ use test::Bencher;
+ 
+ benches! {
+     fn case00_alloc_only(_bytes: &mut [u8]) {}
+ 
+     fn case01_black_box_read_each_byte(bytes: &mut [u8]) {
+         for byte in bytes {
+             black_box(*byte);
+         }
+     }
+ 
+     fn case02_lookup_table(bytes: &mut [u8]) {
+         for byte in bytes {
+             *byte = ASCII_UPPERCASE_MAP[*byte as usize]
+         }
+     }
+ 
+     fn case03_branch_and_subtract(bytes: &mut [u8]) {
+         for byte in bytes {
+             *byte = if b'a' <= *byte && *byte <= b'z' {
+                 *byte - b'a' + b'A'
+             } else {
+                 *byte
+             }
+         }
+     }
+ 
+     fn case04_branch_and_mask(bytes: &mut [u8]) {
+         for byte in bytes {
+             *byte = if b'a' <= *byte && *byte <= b'z' {
+                 *byte & !0x20
+             } else {
+                 *byte
+             }
+         }
+     }
+ 
+     fn case05_branchless(bytes: &mut [u8]) {
+         for byte in bytes {
+             *byte = branchless_to_ascii_upper_case(*byte)
+         }
+     }
+ 
+     fn case06_libcore(bytes: &mut [u8]) {
+         bytes.make_ascii_uppercase()
+     }
+ 
+     fn case07_fake_simd_u32(bytes: &mut [u8]) {
+         // SAFETY: transmuting a sequence of `u8` to `u32` is always fine
+         let (before, aligned, after) = unsafe {
+             bytes.align_to_mut::<u32>()
+         };
+         for byte in before {
+             *byte = branchless_to_ascii_upper_case(*byte)
+         }
+         for word in aligned {
+             // FIXME: this is incorrect for some byte values:
+             // addition within a byte can carry/overflow into the next byte.
+             // Test case: b"\xFFz  "
+             *word &= !(
+                 (
+                     word.wrapping_add(0x1f1f1f1f) &
+                     !word.wrapping_add(0x05050505) &
+                     0x80808080
+                 ) >> 2
+             )
+         }
+         for byte in after {
+             *byte = branchless_to_ascii_upper_case(*byte)
+         }
+     }
+ 
+     fn case08_fake_simd_u64(bytes: &mut [u8]) {
+         // SAFETY: transmuting a sequence of `u8` to `u64` is always fine
+         let (before, aligned, after) = unsafe {
+             bytes.align_to_mut::<u64>()
+         };
+         for byte in before {
+             *byte = branchless_to_ascii_upper_case(*byte)
+         }
+         for word in aligned {
+             // FIXME: like above, this is incorrect for some byte values.
+             *word &= !(
+                 (
+                     word.wrapping_add(0x1f1f1f1f_1f1f1f1f) &
+                     !word.wrapping_add(0x05050505_05050505) &
+                     0x80808080_80808080
+                 ) >> 2
+             )
+         }
+         for byte in after {
+             *byte = branchless_to_ascii_upper_case(*byte)
+         }
+     }
+ 
+     fn case09_mask_mult_bool_branchy_lookup_table(bytes: &mut [u8]) {
+         fn is_ascii_lowercase(b: u8) -> bool {
+             if b >= 0x80 { return false }
+             match ASCII_CHARACTER_CLASS[b as usize] {
+                 L | Lx => true,
+                 _ => false,
+             }
+         }
+         for byte in bytes {
+             *byte &= !(0x20 * (is_ascii_lowercase(*byte) as u8))
+         }
+     }
+ 
+     fn case10_mask_mult_bool_lookup_table(bytes: &mut [u8]) {
+         fn is_ascii_lowercase(b: u8) -> bool {
+             match ASCII_CHARACTER_CLASS[b as usize] {
+                 L | Lx => true,
+                 _ => false
+             }
+         }
+         for byte in bytes {
+             *byte &= !(0x20 * (is_ascii_lowercase(*byte) as u8))
+         }
+     }
+ 
+     fn case11_mask_mult_bool_match_range(bytes: &mut [u8]) {
+         fn is_ascii_lowercase(b: u8) -> bool {
+             match b {
+                 b'a'..=b'z' => true,
+                 _ => false
+             }
+         }
+         for byte in bytes {
+             *byte &= !(0x20 * (is_ascii_lowercase(*byte) as u8))
+         }
+     }
+ 
+     fn case12_mask_shifted_bool_match_range(bytes: &mut [u8]) {
+         fn is_ascii_lowercase(b: u8) -> bool {
+             match b {
+                 b'a'..=b'z' => true,
+                 _ => false
+             }
+         }
+         for byte in bytes {
+             *byte &= !((is_ascii_lowercase(*byte) as u8) << 5)
+         }
+     }
+ 
+     fn case13_subtract_shifted_bool_match_range(bytes: &mut [u8]) {
+         fn is_ascii_lowercase(b: u8) -> bool {
+             match b {
+                 b'a'..=b'z' => true,
+                 _ => false
+             }
+         }
+         for byte in bytes {
+             *byte -= (is_ascii_lowercase(*byte) as u8) << 5
+         }
+     }
+ 
+     fn case14_subtract_multiplied_bool_match_range(bytes: &mut [u8]) {
+         fn is_ascii_lowercase(b: u8) -> bool {
+             match b {
+                 b'a'..=b'z' => true,
+                 _ => false
+             }
+         }
+         for byte in bytes {
+             *byte -= (b'a' - b'A') * is_ascii_lowercase(*byte) as u8
+         }
+     }
+ 
+     @iter
+ 
+     is_ascii,
+     is_ascii_alphabetic,
+     is_ascii_uppercase,
+     is_ascii_lowercase,
+     is_ascii_alphanumeric,
+     is_ascii_digit,
+     is_ascii_hexdigit,
+     is_ascii_punctuation,
+     is_ascii_graphic,
+     is_ascii_whitespace,
+     is_ascii_control,
+ }
+ 
+ macro_rules! repeat {
+     ($s: expr) => {
+         concat!($s, $s, $s, $s, $s, $s, $s, $s, $s, $s)
+     };
+ }
+ 
+ const SHORT: &str = "Alice's";
+ const MEDIUM: &str = "Alice's Adventures in Wonderland";
+ const LONG: &str = repeat!(
+     r#"
+     La Guida di Bragia, a Ballad Opera for the Marionette Theatre (around 1850)
+     Alice's Adventures in Wonderland (1865)
+     Phantasmagoria and Other Poems (1869)
+     Through the Looking-Glass, and What Alice Found There
+         (includes "Jabberwocky" and "The Walrus and the Carpenter") (1871)
+     The Hunting of the Snark (1876)
+     Rhyme? And Reason? (1883) – shares some contents with the 1869 collection,
+         including the long poem "Phantasmagoria"
+     A Tangled Tale (1885)
+     Sylvie and Bruno (1889)
+     Sylvie and Bruno Concluded (1893)
+     Pillow Problems (1893)
+     What the Tortoise Said to Achilles (1895)
+     Three Sunsets and Other Poems (1898)
+     The Manlet (1903)[106]
+ "#
+ );
+ 
+ #[rustfmt::skip]
+ const ASCII_UPPERCASE_MAP: [u8; 256] = [
+     0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+     0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+     0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+     0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
+     b' ', b'!', b'"', b'#', b'$', b'%', b'&', b'\'',
+     b'(', b')', b'*', b'+', b',', b'-', b'.', b'/',
+     b'0', b'1', b'2', b'3', b'4', b'5', b'6', b'7',
+     b'8', b'9', b':', b';', b'<', b'=', b'>', b'?',
+     b'@', b'A', b'B', b'C', b'D', b'E', b'F', b'G',
+     b'H', b'I', b'J', b'K', b'L', b'M', b'N', b'O',
+     b'P', b'Q', b'R', b'S', b'T', b'U', b'V', b'W',
+     b'X', b'Y', b'Z', b'[', b'\\', b']', b'^', b'_',
+     b'`',
+ 
+           b'A', b'B', b'C', b'D', b'E', b'F', b'G',
+     b'H', b'I', b'J', b'K', b'L', b'M', b'N', b'O',
+     b'P', b'Q', b'R', b'S', b'T', b'U', b'V', b'W',
+     b'X', b'Y', b'Z',
+ 
+                       b'{', b'|', b'}', b'~', 0x7f,
+     0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+     0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
+     0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+     0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
+     0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+     0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
+     0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
+     0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
+     0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
+     0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
+     0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
+     0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
+     0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
+     0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
+     0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
+     0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
+ ];
+ 
+ enum AsciiCharacterClass {
+     C,  // control
+     Cw, // control whitespace
+     W,  // whitespace
+     D,  // digit
+     L,  // lowercase
+     Lx, // lowercase hex digit
+     U,  // uppercase
+     Ux, // uppercase hex digit
+     P,  // punctuation
+     N,  // Non-ASCII
+ }
+ use self::AsciiCharacterClass::*;
+ 
+ #[rustfmt::skip]
+ static ASCII_CHARACTER_CLASS: [AsciiCharacterClass; 256] = [
+ //  _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f
+     C, C, C, C, C, C, C, C, C, Cw,Cw,C, Cw,Cw,C, C, // 0_
+     C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, // 1_
+     W, P, P, P, P, P, P, P, P, P, P, P, P, P, P, P, // 2_
+     D, D, D, D, D, D, D, D, D, D, P, P, P, P, P, P, // 3_
+     P, Ux,Ux,Ux,Ux,Ux,Ux,U, U, U, U, U, U, U, U, U, // 4_
+     U, U, U, U, U, U, U, U, U, U, U, P, P, P, P, P, // 5_
+     P, Lx,Lx,Lx,Lx,Lx,Lx,L, L, L, L, L, L, L, L, L, // 6_
+     L, L, L, L, L, L, L, L, L, L, L, P, P, P, P, C, // 7_
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+     N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+ ];
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/char/methods.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/char/methods.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/char/methods.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/char/methods.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,37 ----
+ use test::Bencher;
+ 
+ const CHARS: [char; 9] = ['0', 'x', '2', '5', 'A', 'f', '7', '8', '9'];
+ const RADIX: [u32; 5] = [2, 8, 10, 16, 32];
+ 
+ #[bench]
+ fn bench_to_digit_radix_2(b: &mut Bencher) {
+     b.iter(|| CHARS.iter().cycle().take(10_000).map(|c| c.to_digit(2)).min())
+ }
+ 
+ #[bench]
+ fn bench_to_digit_radix_10(b: &mut Bencher) {
+     b.iter(|| CHARS.iter().cycle().take(10_000).map(|c| c.to_digit(10)).min())
+ }
+ 
+ #[bench]
+ fn bench_to_digit_radix_16(b: &mut Bencher) {
+     b.iter(|| CHARS.iter().cycle().take(10_000).map(|c| c.to_digit(16)).min())
+ }
+ 
+ #[bench]
+ fn bench_to_digit_radix_36(b: &mut Bencher) {
+     b.iter(|| CHARS.iter().cycle().take(10_000).map(|c| c.to_digit(36)).min())
+ }
+ 
+ #[bench]
+ fn bench_to_digit_radix_var(b: &mut Bencher) {
+     b.iter(|| {
+         CHARS
+             .iter()
+             .cycle()
+             .zip(RADIX.iter().cycle())
+             .take(10_000)
+             .map(|(c, radix)| c.to_digit(*radix))
+             .min()
+     })
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/char/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/char/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/char/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/char/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ mod methods;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/fmt.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/fmt.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/fmt.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/fmt.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,139 ----
+ use std::fmt::{self, Write as FmtWrite};
+ use std::io::{self, Write as IoWrite};
+ use test::Bencher;
+ 
+ #[bench]
+ fn write_vec_value(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = Vec::new();
+         for _ in 0..1000 {
+             mem.write_all("abc".as_bytes()).unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_vec_ref(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = Vec::new();
+         let wr = &mut mem as &mut dyn io::Write;
+         for _ in 0..1000 {
+             wr.write_all("abc".as_bytes()).unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_vec_macro1(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = Vec::new();
+         let wr = &mut mem as &mut dyn io::Write;
+         for _ in 0..1000 {
+             write!(wr, "abc").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_vec_macro2(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = Vec::new();
+         let wr = &mut mem as &mut dyn io::Write;
+         for _ in 0..1000 {
+             write!(wr, "{}", "abc").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_vec_macro_debug(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = Vec::new();
+         let wr = &mut mem as &mut dyn io::Write;
+         for _ in 0..1000 {
+             write!(wr, "{:?}", "☃").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_str_value(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = String::new();
+         for _ in 0..1000 {
+             mem.write_str("abc").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_str_ref(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = String::new();
+         let wr = &mut mem as &mut dyn fmt::Write;
+         for _ in 0..1000 {
+             wr.write_str("abc").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_str_macro1(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = String::new();
+         for _ in 0..1000 {
+             write!(mem, "abc").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_str_macro2(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = String::new();
+         let wr = &mut mem as &mut dyn fmt::Write;
+         for _ in 0..1000 {
+             write!(wr, "{}", "abc").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_str_macro_debug(bh: &mut Bencher) {
+     bh.iter(|| {
+         let mut mem = String::new();
+         let wr = &mut mem as &mut dyn fmt::Write;
+         for _ in 0..1000 {
+             write!(wr, "{:?}", "☃").unwrap();
+         }
+     });
+ }
+ 
+ #[bench]
+ fn write_u128_max(bh: &mut Bencher) {
+     bh.iter(|| {
+         std::hint::black_box(format!("{}", u128::MAX));
+     });
+ }
+ 
+ #[bench]
+ fn write_u128_min(bh: &mut Bencher) {
+     bh.iter(|| {
+         let s = format!("{}", 0u128);
+         std::hint::black_box(s);
+     });
+ }
+ 
+ #[bench]
+ fn write_u64_max(bh: &mut Bencher) {
+     bh.iter(|| {
+         std::hint::black_box(format!("{}", u64::MAX));
+     });
+ }
+ 
+ #[bench]
+ fn write_u64_min(bh: &mut Bencher) {
+     bh.iter(|| {
+         std::hint::black_box(format!("{}", 0u64));
+     });
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/hash/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/hash/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/hash/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/hash/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ mod sip;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/hash/sip.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/hash/sip.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/hash/sip.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/hash/sip.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,123 ----
+ #![allow(deprecated)]
+ 
+ use core::hash::*;
+ use test::{black_box, Bencher};
+ 
+ fn hash_bytes<H: Hasher>(mut s: H, x: &[u8]) -> u64 {
+     Hasher::write(&mut s, x);
+     s.finish()
+ }
+ 
+ fn hash_with<H: Hasher, T: Hash>(mut st: H, x: &T) -> u64 {
+     x.hash(&mut st);
+     st.finish()
+ }
+ 
+ fn hash<T: Hash>(x: &T) -> u64 {
+     hash_with(SipHasher::new(), x)
+ }
+ 
+ #[bench]
+ fn bench_str_under_8_bytes(b: &mut Bencher) {
+     let s = "foo";
+     b.iter(|| {
+         assert_eq!(hash(&s), 16262950014981195938);
+     })
+ }
+ 
+ #[bench]
+ fn bench_str_of_8_bytes(b: &mut Bencher) {
+     let s = "foobar78";
+     b.iter(|| {
+         assert_eq!(hash(&s), 4898293253460910787);
+     })
+ }
+ 
+ #[bench]
+ fn bench_str_over_8_bytes(b: &mut Bencher) {
+     let s = "foobarbaz0";
+     b.iter(|| {
+         assert_eq!(hash(&s), 10581415515220175264);
+     })
+ }
+ 
+ #[bench]
+ fn bench_long_str(b: &mut Bencher) {
+     let s = "Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor \
+              incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud \
+              exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute \
+              irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla \
+              pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui \
+              officia deserunt mollit anim id est laborum.";
+     b.iter(|| {
+         assert_eq!(hash(&s), 17717065544121360093);
+     })
+ }
+ 
+ #[bench]
+ fn bench_u32(b: &mut Bencher) {
+     let u = 162629500u32;
+     let u = black_box(u);
+     b.iter(|| hash(&u));
+     b.bytes = 8;
+ }
+ 
+ #[bench]
+ fn bench_u32_keyed(b: &mut Bencher) {
+     let u = 162629500u32;
+     let u = black_box(u);
+     let k1 = black_box(0x1);
+     let k2 = black_box(0x2);
+     b.iter(|| hash_with(SipHasher::new_with_keys(k1, k2), &u));
+     b.bytes = 8;
+ }
+ 
+ #[bench]
+ fn bench_u64(b: &mut Bencher) {
+     let u = 16262950014981195938u64;
+     let u = black_box(u);
+     b.iter(|| hash(&u));
+     b.bytes = 8;
+ }
+ 
+ #[bench]
+ fn bench_bytes_4(b: &mut Bencher) {
+     let data = black_box([b' '; 4]);
+     b.iter(|| hash_bytes(SipHasher::default(), &data));
+     b.bytes = 4;
+ }
+ 
+ #[bench]
+ fn bench_bytes_7(b: &mut Bencher) {
+     let data = black_box([b' '; 7]);
+     b.iter(|| hash_bytes(SipHasher::default(), &data));
+     b.bytes = 7;
+ }
+ 
+ #[bench]
+ fn bench_bytes_8(b: &mut Bencher) {
+     let data = black_box([b' '; 8]);
+     b.iter(|| hash_bytes(SipHasher::default(), &data));
+     b.bytes = 8;
+ }
+ 
+ #[bench]
+ fn bench_bytes_a_16(b: &mut Bencher) {
+     let data = black_box([b' '; 16]);
+     b.iter(|| hash_bytes(SipHasher::default(), &data));
+     b.bytes = 16;
+ }
+ 
+ #[bench]
+ fn bench_bytes_b_32(b: &mut Bencher) {
+     let data = black_box([b' '; 32]);
+     b.iter(|| hash_bytes(SipHasher::default(), &data));
+     b.bytes = 32;
+ }
+ 
+ #[bench]
+ fn bench_bytes_c_128(b: &mut Bencher) {
+     let data = black_box([b' '; 128]);
+     b.iter(|| hash_bytes(SipHasher::default(), &data));
+     b.bytes = 128;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/iter.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/iter.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/iter.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/iter.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,347 ----
+ use core::iter::*;
+ use test::{black_box, Bencher};
+ 
+ #[bench]
+ fn bench_rposition(b: &mut Bencher) {
+     let it: Vec<usize> = (0..300).collect();
+     b.iter(|| {
+         it.iter().rposition(|&x| x <= 150);
+     });
+ }
+ 
+ #[bench]
+ fn bench_skip_while(b: &mut Bencher) {
+     b.iter(|| {
+         let it = 0..100;
+         let mut sum = 0;
+         it.skip_while(|&x| {
+             sum += x;
+             sum < 4000
+         })
+         .all(|_| true);
+     });
+ }
+ 
+ #[bench]
+ fn bench_multiple_take(b: &mut Bencher) {
+     let mut it = (0..42).cycle();
+     b.iter(|| {
+         let n = it.next().unwrap();
+         for _ in 0..n {
+             it.clone().take(it.next().unwrap()).all(|_| true);
+         }
+     });
+ }
+ 
+ fn scatter(x: i32) -> i32 {
+     (x * 31) % 127
+ }
+ 
+ #[bench]
+ fn bench_max_by_key(b: &mut Bencher) {
+     b.iter(|| {
+         let it = 0..100;
+         it.map(black_box).max_by_key(|&x| scatter(x))
+     })
+ }
+ 
+ // http://www.reddit.com/r/rust/comments/31syce/using_iterators_to_find_the_index_of_the_min_or/
+ #[bench]
+ fn bench_max_by_key2(b: &mut Bencher) {
+     fn max_index_iter(array: &[i32]) -> usize {
+         array.iter().enumerate().max_by_key(|&(_, item)| item).unwrap().0
+     }
+ 
+     let mut data = vec![0; 1638];
+     data[514] = 9999;
+ 
+     b.iter(|| max_index_iter(&data));
+ }
+ 
+ #[bench]
+ fn bench_max(b: &mut Bencher) {
+     b.iter(|| {
+         let it = 0..100;
+         it.map(black_box).map(scatter).max()
+     })
+ }
+ 
+ pub fn copy_zip(xs: &[u8], ys: &mut [u8]) {
+     for (a, b) in ys.iter_mut().zip(xs) {
+         *a = *b;
+     }
+ }
+ 
+ pub fn add_zip(xs: &[f32], ys: &mut [f32]) {
+     for (a, b) in ys.iter_mut().zip(xs) {
+         *a += *b;
+     }
+ }
+ 
+ #[bench]
+ fn bench_zip_copy(b: &mut Bencher) {
+     let source = vec![0u8; 16 * 1024];
+     let mut dst = black_box(vec![0u8; 16 * 1024]);
+     b.iter(|| copy_zip(&source, &mut dst))
+ }
+ 
+ #[bench]
+ fn bench_zip_add(b: &mut Bencher) {
+     let source = vec![1.; 16 * 1024];
+     let mut dst = vec![0.; 16 * 1024];
+     b.iter(|| add_zip(&source, &mut dst));
+ }
+ 
+ /// `Iterator::for_each` implemented as a plain loop.
+ fn for_each_loop<I, F>(iter: I, mut f: F)
+ where
+     I: Iterator,
+     F: FnMut(I::Item),
+ {
+     for item in iter {
+         f(item);
+     }
+ }
+ 
+ /// `Iterator::for_each` implemented with `fold` for internal iteration.
+ /// (except when `by_ref()` effectively disables that optimization.)
+ fn for_each_fold<I, F>(iter: I, mut f: F)
+ where
+     I: Iterator,
+     F: FnMut(I::Item),
+ {
+     iter.fold((), move |(), item| f(item));
+ }
+ 
+ #[bench]
+ fn bench_for_each_chain_loop(b: &mut Bencher) {
+     b.iter(|| {
+         let mut acc = 0;
+         let iter = (0i64..1000000).chain(0..1000000).map(black_box);
+         for_each_loop(iter, |x| acc += x);
+         acc
+     });
+ }
+ 
+ #[bench]
+ fn bench_for_each_chain_fold(b: &mut Bencher) {
+     b.iter(|| {
+         let mut acc = 0;
+         let iter = (0i64..1000000).chain(0..1000000).map(black_box);
+         for_each_fold(iter, |x| acc += x);
+         acc
+     });
+ }
+ 
+ #[bench]
+ fn bench_for_each_chain_ref_fold(b: &mut Bencher) {
+     b.iter(|| {
+         let mut acc = 0;
+         let mut iter = (0i64..1000000).chain(0..1000000).map(black_box);
+         for_each_fold(iter.by_ref(), |x| acc += x);
+         acc
+     });
+ }
+ 
+ /// Helper to benchmark `sum` for iterators taken by value which
+ /// can optimize `fold`, and by reference which cannot.
+ macro_rules! bench_sums {
+     ($bench_sum:ident, $bench_ref_sum:ident, $iter:expr) => {
+         #[bench]
+         fn $bench_sum(b: &mut Bencher) {
+             b.iter(|| -> i64 { $iter.map(black_box).sum() });
+         }
+ 
+         #[bench]
+         fn $bench_ref_sum(b: &mut Bencher) {
+             b.iter(|| -> i64 { $iter.map(black_box).by_ref().sum() });
+         }
+     };
+ }
+ 
+ bench_sums! {
+     bench_flat_map_sum,
+     bench_flat_map_ref_sum,
+     (0i64..1000).flat_map(|x| x..x+1000)
+ }
+ 
+ bench_sums! {
+     bench_flat_map_chain_sum,
+     bench_flat_map_chain_ref_sum,
+     (0i64..1000000).flat_map(|x| once(x).chain(once(x)))
+ }
+ 
+ bench_sums! {
+     bench_enumerate_sum,
+     bench_enumerate_ref_sum,
+     (0i64..1000000).enumerate().map(|(i, x)| x * i as i64)
+ }
+ 
+ bench_sums! {
+     bench_enumerate_chain_sum,
+     bench_enumerate_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).enumerate().map(|(i, x)| x * i as i64)
+ }
+ 
+ bench_sums! {
+     bench_filter_sum,
+     bench_filter_ref_sum,
+     (0i64..1000000).filter(|x| x % 3 == 0)
+ }
+ 
+ bench_sums! {
+     bench_filter_chain_sum,
+     bench_filter_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).filter(|x| x % 3 == 0)
+ }
+ 
+ bench_sums! {
+     bench_filter_map_sum,
+     bench_filter_map_ref_sum,
+     (0i64..1000000).filter_map(|x| x.checked_mul(x))
+ }
+ 
+ bench_sums! {
+     bench_filter_map_chain_sum,
+     bench_filter_map_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).filter_map(|x| x.checked_mul(x))
+ }
+ 
+ bench_sums! {
+     bench_fuse_sum,
+     bench_fuse_ref_sum,
+     (0i64..1000000).fuse()
+ }
+ 
+ bench_sums! {
+     bench_fuse_chain_sum,
+     bench_fuse_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).fuse()
+ }
+ 
+ bench_sums! {
+     bench_inspect_sum,
+     bench_inspect_ref_sum,
+     (0i64..1000000).inspect(|_| {})
+ }
+ 
+ bench_sums! {
+     bench_inspect_chain_sum,
+     bench_inspect_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).inspect(|_| {})
+ }
+ 
+ bench_sums! {
+     bench_peekable_sum,
+     bench_peekable_ref_sum,
+     (0i64..1000000).peekable()
+ }
+ 
+ bench_sums! {
+     bench_peekable_chain_sum,
+     bench_peekable_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).peekable()
+ }
+ 
+ bench_sums! {
+     bench_skip_sum,
+     bench_skip_ref_sum,
+     (0i64..1000000).skip(1000)
+ }
+ 
+ bench_sums! {
+     bench_skip_chain_sum,
+     bench_skip_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).skip(1000)
+ }
+ 
+ bench_sums! {
+     bench_skip_while_sum,
+     bench_skip_while_ref_sum,
+     (0i64..1000000).skip_while(|&x| x < 1000)
+ }
+ 
+ bench_sums! {
+     bench_skip_while_chain_sum,
+     bench_skip_while_chain_ref_sum,
+     (0i64..1000000).chain(0..1000000).skip_while(|&x| x < 1000)
+ }
+ 
+ bench_sums! {
+     bench_take_while_chain_sum,
+     bench_take_while_chain_ref_sum,
+     (0i64..1000000).chain(1000000..).take_while(|&x| x < 1111111)
+ }
+ 
+ bench_sums! {
+     bench_cycle_take_sum,
+     bench_cycle_take_ref_sum,
+     (0i64..10000).cycle().take(1000000)
+ }
+ 
+ // Checks whether Skip<Zip<A,B>> is as fast as Zip<Skip<A>, Skip<B>>, from
+ // https://users.rust-lang.org/t/performance-difference-between-iterator-zip-and-skip-order/15743
+ #[bench]
+ fn bench_zip_then_skip(b: &mut Bencher) {
+     let v: Vec<_> = (0..100_000).collect();
+     let t: Vec<_> = (0..100_000).collect();
+ 
+     b.iter(|| {
+         let s = v
+             .iter()
+             .zip(t.iter())
+             .skip(10000)
+             .take_while(|t| *t.0 < 10100)
+             .map(|(a, b)| *a + *b)
+             .sum::<u64>();
+         assert_eq!(s, 2009900);
+     });
+ }
+ #[bench]
+ fn bench_skip_then_zip(b: &mut Bencher) {
+     let v: Vec<_> = (0..100_000).collect();
+     let t: Vec<_> = (0..100_000).collect();
+ 
+     b.iter(|| {
+         let s = v
+             .iter()
+             .skip(10000)
+             .zip(t.iter().skip(10000))
+             .take_while(|t| *t.0 < 10100)
+             .map(|(a, b)| *a + *b)
+             .sum::<u64>();
+         assert_eq!(s, 2009900);
+     });
+ }
+ 
+ #[bench]
+ fn bench_filter_count(b: &mut Bencher) {
+     b.iter(|| (0i64..1000000).map(black_box).filter(|x| x % 3 == 0).count())
+ }
+ 
+ #[bench]
+ fn bench_filter_ref_count(b: &mut Bencher) {
+     b.iter(|| (0i64..1000000).map(black_box).by_ref().filter(|x| x % 3 == 0).count())
+ }
+ 
+ #[bench]
+ fn bench_filter_chain_count(b: &mut Bencher) {
+     b.iter(|| (0i64..1000000).chain(0..1000000).map(black_box).filter(|x| x % 3 == 0).count())
+ }
+ 
+ #[bench]
+ fn bench_filter_chain_ref_count(b: &mut Bencher) {
+     b.iter(|| {
+         (0i64..1000000).chain(0..1000000).map(black_box).by_ref().filter(|x| x % 3 == 0).count()
+     })
+ }
+ 
+ #[bench]
+ fn bench_partial_cmp(b: &mut Bencher) {
+     b.iter(|| (0..100000).map(black_box).partial_cmp((0..100000).map(black_box)))
+ }
+ 
+ #[bench]
+ fn bench_lt(b: &mut Bencher) {
+     b.iter(|| (0..100000).map(black_box).lt((0..100000).map(black_box)))
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/lib.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,17 ----
+ // wasm32 does not support benches (no time).
+ #![cfg(not(target_arch = "wasm32"))]
+ #![feature(flt2dec)]
+ #![feature(test)]
+ 
+ extern crate test;
+ 
+ mod any;
+ mod ascii;
+ mod char;
+ mod fmt;
+ mod hash;
+ mod iter;
+ mod num;
+ mod ops;
+ mod pattern;
+ mod slice;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/num/dec2flt/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/num/dec2flt/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/num/dec2flt/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/num/dec2flt/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,57 ----
+ use test::Bencher;
+ 
+ #[bench]
+ fn bench_0(b: &mut Bencher) {
+     b.iter(|| "0.0".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_42(b: &mut Bencher) {
+     b.iter(|| "42".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_huge_int(b: &mut Bencher) {
+     // 2^128 - 1
+     b.iter(|| "170141183460469231731687303715884105727".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_short_decimal(b: &mut Bencher) {
+     b.iter(|| "1234.5678".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_pi_long(b: &mut Bencher) {
+     b.iter(|| "3.14159265358979323846264338327950288".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_pi_short(b: &mut Bencher) {
+     b.iter(|| "3.141592653589793".parse::<f64>())
+ }
+ 
+ #[bench]
+ fn bench_1e150(b: &mut Bencher) {
+     b.iter(|| "1e150".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_long_decimal_and_exp(b: &mut Bencher) {
+     b.iter(|| "727501488517303786137132964064381141071e-123".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_min_subnormal(b: &mut Bencher) {
+     b.iter(|| "5e-324".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_min_normal(b: &mut Bencher) {
+     b.iter(|| "2.2250738585072014e-308".parse::<f64>());
+ }
+ 
+ #[bench]
+ fn bench_max(b: &mut Bencher) {
+     b.iter(|| "1.7976931348623157e308".parse::<f64>());
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/num/flt2dec/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/num/flt2dec/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/num/flt2dec/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/num/flt2dec/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,37 ----
+ mod strategy {
+     mod dragon;
+     mod grisu;
+ }
+ 
+ use core::num::flt2dec::MAX_SIG_DIGITS;
+ use core::num::flt2dec::{decode, DecodableFloat, Decoded, FullDecoded};
+ use std::io::Write;
+ use std::vec::Vec;
+ use test::Bencher;
+ 
+ pub fn decode_finite<T: DecodableFloat>(v: T) -> Decoded {
+     match decode(v).1 {
+         FullDecoded::Finite(decoded) => decoded,
+         full_decoded => panic!("expected finite, got {:?} instead", full_decoded),
+     }
+ }
+ 
+ #[bench]
+ fn bench_small_shortest(b: &mut Bencher) {
+     let mut buf = Vec::with_capacity(20);
+ 
+     b.iter(|| {
+         buf.clear();
+         write!(&mut buf, "{}", 3.1415926f64).unwrap()
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_shortest(b: &mut Bencher) {
+     let mut buf = Vec::with_capacity(300);
+ 
+     b.iter(|| {
+         buf.clear();
+         write!(&mut buf, "{}", f64::MAX).unwrap()
+     });
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/dragon.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/dragon.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/dragon.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/dragon.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,76 ----
+ use super::super::*;
+ use core::num::flt2dec::strategy::dragon::*;
+ use std::mem::MaybeUninit;
+ use test::Bencher;
+ 
+ #[bench]
+ fn bench_small_shortest(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); MAX_SIG_DIGITS];
+     b.iter(|| {
+         format_shortest(&decoded, &mut buf);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_shortest(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); MAX_SIG_DIGITS];
+     b.iter(|| {
+         format_shortest(&decoded, &mut buf);
+     });
+ }
+ 
+ #[bench]
+ fn bench_small_exact_3(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); 3];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_exact_3(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); 3];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_small_exact_12(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); 12];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_exact_12(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); 12];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_small_exact_inf(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); 1024];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_exact_inf(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); 1024];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/grisu.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/grisu.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/grisu.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/num/flt2dec/strategy/grisu.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,83 ----
+ use super::super::*;
+ use core::num::flt2dec::strategy::grisu::*;
+ use std::mem::MaybeUninit;
+ use test::Bencher;
+ 
+ pub fn decode_finite<T: DecodableFloat>(v: T) -> Decoded {
+     match decode(v).1 {
+         FullDecoded::Finite(decoded) => decoded,
+         full_decoded => panic!("expected finite, got {:?} instead", full_decoded),
+     }
+ }
+ 
+ #[bench]
+ fn bench_small_shortest(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); MAX_SIG_DIGITS];
+     b.iter(|| {
+         format_shortest(&decoded, &mut buf);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_shortest(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); MAX_SIG_DIGITS];
+     b.iter(|| {
+         format_shortest(&decoded, &mut buf);
+     });
+ }
+ 
+ #[bench]
+ fn bench_small_exact_3(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); 3];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_exact_3(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); 3];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_small_exact_12(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); 12];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_exact_12(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); 12];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_small_exact_inf(b: &mut Bencher) {
+     let decoded = decode_finite(3.141592f64);
+     let mut buf = [MaybeUninit::new(0); 1024];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
+ 
+ #[bench]
+ fn bench_big_exact_inf(b: &mut Bencher) {
+     let decoded = decode_finite(f64::MAX);
+     let mut buf = [MaybeUninit::new(0); 1024];
+     b.iter(|| {
+         format_exact(&decoded, &mut buf, i16::MIN);
+     });
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/num/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/num/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/num/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/num/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,107 ----
+ mod dec2flt;
+ mod flt2dec;
+ 
+ use std::str::FromStr;
+ use test::Bencher;
+ 
+ const ASCII_NUMBERS: [&str; 19] = [
+     "0",
+     "1",
+     "2",
+     "43",
+     "765",
+     "76567",
+     "987245987",
+     "-4aa32",
+     "1786235",
+     "8723095",
+     "f##5s",
+     "83638730",
+     "-2345",
+     "562aa43",
+     "-1",
+     "-0",
+     "abc",
+     "xyz",
+     "c0ffee",
+ ];
+ 
+ macro_rules! from_str_bench {
+     ($mac:ident, $t:ty) => {
+         #[bench]
+         fn $mac(b: &mut Bencher) {
+             b.iter(|| {
+                 ASCII_NUMBERS
+                     .iter()
+                     .cycle()
+                     .take(5_000)
+                     .filter_map(|s| <$t>::from_str(s).ok())
+                     .max()
+             })
+         }
+     };
+ }
+ 
+ macro_rules! from_str_radix_bench {
+     ($mac:ident, $t:ty, $radix:expr) => {
+         #[bench]
+         fn $mac(b: &mut Bencher) {
+             b.iter(|| {
+                 ASCII_NUMBERS
+                     .iter()
+                     .cycle()
+                     .take(5_000)
+                     .filter_map(|s| <$t>::from_str_radix(s, $radix).ok())
+                     .max()
+             })
+         }
+     };
+ }
+ 
+ from_str_bench!(bench_u8_from_str, u8);
+ from_str_radix_bench!(bench_u8_from_str_radix_2, u8, 2);
+ from_str_radix_bench!(bench_u8_from_str_radix_10, u8, 10);
+ from_str_radix_bench!(bench_u8_from_str_radix_16, u8, 16);
+ from_str_radix_bench!(bench_u8_from_str_radix_36, u8, 36);
+ 
+ from_str_bench!(bench_u16_from_str, u16);
+ from_str_radix_bench!(bench_u16_from_str_radix_2, u16, 2);
+ from_str_radix_bench!(bench_u16_from_str_radix_10, u16, 10);
+ from_str_radix_bench!(bench_u16_from_str_radix_16, u16, 16);
+ from_str_radix_bench!(bench_u16_from_str_radix_36, u16, 36);
+ 
+ from_str_bench!(bench_u32_from_str, u32);
+ from_str_radix_bench!(bench_u32_from_str_radix_2, u32, 2);
+ from_str_radix_bench!(bench_u32_from_str_radix_10, u32, 10);
+ from_str_radix_bench!(bench_u32_from_str_radix_16, u32, 16);
+ from_str_radix_bench!(bench_u32_from_str_radix_36, u32, 36);
+ 
+ from_str_bench!(bench_u64_from_str, u64);
+ from_str_radix_bench!(bench_u64_from_str_radix_2, u64, 2);
+ from_str_radix_bench!(bench_u64_from_str_radix_10, u64, 10);
+ from_str_radix_bench!(bench_u64_from_str_radix_16, u64, 16);
+ from_str_radix_bench!(bench_u64_from_str_radix_36, u64, 36);
+ 
+ from_str_bench!(bench_i8_from_str, i8);
+ from_str_radix_bench!(bench_i8_from_str_radix_2, i8, 2);
+ from_str_radix_bench!(bench_i8_from_str_radix_10, i8, 10);
+ from_str_radix_bench!(bench_i8_from_str_radix_16, i8, 16);
+ from_str_radix_bench!(bench_i8_from_str_radix_36, i8, 36);
+ 
+ from_str_bench!(bench_i16_from_str, i16);
+ from_str_radix_bench!(bench_i16_from_str_radix_2, i16, 2);
+ from_str_radix_bench!(bench_i16_from_str_radix_10, i16, 10);
+ from_str_radix_bench!(bench_i16_from_str_radix_16, i16, 16);
+ from_str_radix_bench!(bench_i16_from_str_radix_36, i16, 36);
+ 
+ from_str_bench!(bench_i32_from_str, i32);
+ from_str_radix_bench!(bench_i32_from_str_radix_2, i32, 2);
+ from_str_radix_bench!(bench_i32_from_str_radix_10, i32, 10);
+ from_str_radix_bench!(bench_i32_from_str_radix_16, i32, 16);
+ from_str_radix_bench!(bench_i32_from_str_radix_36, i32, 36);
+ 
+ from_str_bench!(bench_i64_from_str, i64);
+ from_str_radix_bench!(bench_i64_from_str_radix_2, i64, 2);
+ from_str_radix_bench!(bench_i64_from_str_radix_10, i64, 10);
+ from_str_radix_bench!(bench_i64_from_str_radix_16, i64, 16);
+ from_str_radix_bench!(bench_i64_from_str_radix_36, i64, 36);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/ops.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/ops.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/ops.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/ops.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,19 ----
+ use core::ops::*;
+ use test::Bencher;
+ 
+ // Overhead of dtors
+ 
+ struct HasDtor {
+     _x: isize,
+ }
+ 
+ impl Drop for HasDtor {
+     fn drop(&mut self) {}
+ }
+ 
+ #[bench]
+ fn alloc_obj_with_dtor(b: &mut Bencher) {
+     b.iter(|| {
+         HasDtor { _x: 10 };
+     })
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/pattern.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/pattern.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/pattern.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/pattern.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,42 ----
+ use test::black_box;
+ use test::Bencher;
+ 
+ #[bench]
+ fn starts_with_char(b: &mut Bencher) {
+     let text = black_box("kdjsfhlakfhlsghlkvcnljknfqiunvcijqenwodind");
+     b.iter(|| {
+         for _ in 0..1024 {
+             black_box(text.starts_with('k'));
+         }
+     })
+ }
+ 
+ #[bench]
+ fn starts_with_str(b: &mut Bencher) {
+     let text = black_box("kdjsfhlakfhlsghlkvcnljknfqiunvcijqenwodind");
+     b.iter(|| {
+         for _ in 0..1024 {
+             black_box(text.starts_with("k"));
+         }
+     })
+ }
+ 
+ #[bench]
+ fn ends_with_char(b: &mut Bencher) {
+     let text = black_box("kdjsfhlakfhlsghlkvcnljknfqiunvcijqenwodind");
+     b.iter(|| {
+         for _ in 0..1024 {
+             black_box(text.ends_with('k'));
+         }
+     })
+ }
+ 
+ #[bench]
+ fn ends_with_str(b: &mut Bencher) {
+     let text = black_box("kdjsfhlakfhlsghlkvcnljknfqiunvcijqenwodind");
+     b.iter(|| {
+         for _ in 0..1024 {
+             black_box(text.ends_with("k"));
+         }
+     })
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/benches/slice.rs gcc-16-20251102/libgrust/rustc-lib/core/benches/slice.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/benches/slice.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/benches/slice.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,84 ----
+ use test::black_box;
+ use test::Bencher;
+ 
+ enum Cache {
+     L1,
+     L2,
+     L3,
+ }
+ 
+ fn binary_search<F>(b: &mut Bencher, cache: Cache, mapper: F)
+ where
+     F: Fn(usize) -> usize,
+ {
+     let size = match cache {
+         Cache::L1 => 1000,      // 8kb
+         Cache::L2 => 10_000,    // 80kb
+         Cache::L3 => 1_000_000, // 8Mb
+     };
+     let v = (0..size).map(&mapper).collect::<Vec<_>>();
+     let mut r = 0usize;
+     b.iter(move || {
+         // LCG constants from https://en.wikipedia.org/wiki/Numerical_Recipes.
+         r = r.wrapping_mul(1664525).wrapping_add(1013904223);
+         // Lookup the whole range to get 50% hits and 50% misses.
+         let i = mapper(r % size);
+         black_box(v.binary_search(&i).is_ok());
+     })
+ }
+ 
+ #[bench]
+ fn binary_search_l1(b: &mut Bencher) {
+     binary_search(b, Cache::L1, |i| i * 2);
+ }
+ 
+ #[bench]
+ fn binary_search_l2(b: &mut Bencher) {
+     binary_search(b, Cache::L2, |i| i * 2);
+ }
+ 
+ #[bench]
+ fn binary_search_l3(b: &mut Bencher) {
+     binary_search(b, Cache::L3, |i| i * 2);
+ }
+ 
+ #[bench]
+ fn binary_search_l1_with_dups(b: &mut Bencher) {
+     binary_search(b, Cache::L1, |i| i / 16 * 16);
+ }
+ 
+ #[bench]
+ fn binary_search_l2_with_dups(b: &mut Bencher) {
+     binary_search(b, Cache::L2, |i| i / 16 * 16);
+ }
+ 
+ #[bench]
+ fn binary_search_l3_with_dups(b: &mut Bencher) {
+     binary_search(b, Cache::L3, |i| i / 16 * 16);
+ }
+ 
+ macro_rules! rotate {
+     ($fn:ident, $n:expr, $mapper:expr) => {
+         #[bench]
+         fn $fn(b: &mut Bencher) {
+             let mut x = (0usize..$n).map(&$mapper).collect::<Vec<_>>();
+             b.iter(|| {
+                 for s in 0..x.len() {
+                     x[..].rotate_right(s);
+                 }
+                 black_box(x[0].clone())
+             })
+         }
+     };
+ }
+ 
+ #[derive(Clone)]
+ struct Rgb(u8, u8, u8);
+ 
+ rotate!(rotate_u8, 32, |i| i as u8);
+ rotate!(rotate_rgb, 32, |i| Rgb(i as u8, (i as u8).wrapping_add(7), (i as u8).wrapping_add(42)));
+ rotate!(rotate_usize, 32, |i| i);
+ rotate!(rotate_16_usize_4, 16, |i| [i; 4]);
+ rotate!(rotate_16_usize_5, 16, |i| [i; 5]);
+ rotate!(rotate_64_usize_4, 64, |i| [i; 4]);
+ rotate!(rotate_64_usize_5, 64, |i| [i; 5]);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/alloc/global.rs gcc-16-20251102/libgrust/rustc-lib/core/src/alloc/global.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/alloc/global.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/alloc/global.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,208 ----
+ use crate::alloc::Layout;
+ use crate::cmp;
+ use crate::ptr;
+ 
+ /// A memory allocator that can be registered as the standard library’s default
+ /// through the `#[global_allocator]` attribute.
+ ///
+ /// Some of the methods require that a memory block be *currently
+ /// allocated* via an allocator. This means that:
+ ///
+ /// * the starting address for that memory block was previously
+ ///   returned by a previous call to an allocation method
+ ///   such as `alloc`, and
+ ///
+ /// * the memory block has not been subsequently deallocated, where
+ ///   blocks are deallocated either by being passed to a deallocation
+ ///   method such as `dealloc` or by being
+ ///   passed to a reallocation method that returns a non-null pointer.
+ ///
+ ///
+ /// # Example
+ ///
+ /// ```no_run
+ /// use std::alloc::{GlobalAlloc, Layout, alloc};
+ /// use std::ptr::null_mut;
+ ///
+ /// struct MyAllocator;
+ ///
+ /// unsafe impl GlobalAlloc for MyAllocator {
+ ///     unsafe fn alloc(&self, _layout: Layout) -> *mut u8 { null_mut() }
+ ///     unsafe fn dealloc(&self, _ptr: *mut u8, _layout: Layout) {}
+ /// }
+ ///
+ /// #[global_allocator]
+ /// static A: MyAllocator = MyAllocator;
+ ///
+ /// fn main() {
+ ///     unsafe {
+ ///         assert!(alloc(Layout::new::<u32>()).is_null())
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// # Safety
+ ///
+ /// The `GlobalAlloc` trait is an `unsafe` trait for a number of reasons, and
+ /// implementors must ensure that they adhere to these contracts:
+ ///
+ /// * It's undefined behavior if global allocators unwind. This restriction may
+ ///   be lifted in the future, but currently a panic from any of these
+ ///   functions may lead to memory unsafety.
+ ///
+ /// * `Layout` queries and calculations in general must be correct. Callers of
+ ///   this trait are allowed to rely on the contracts defined on each method,
+ ///   and implementors must ensure such contracts remain true.
+ #[stable(feature = "global_alloc", since = "1.28.0")]
+ pub unsafe trait GlobalAlloc {
+     /// Allocate memory as described by the given `layout`.
+     ///
+     /// Returns a pointer to newly-allocated memory,
+     /// or null to indicate allocation failure.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe because undefined behavior can result
+     /// if the caller does not ensure that `layout` has non-zero size.
+     ///
+     /// (Extension subtraits might provide more specific bounds on
+     /// behavior, e.g., guarantee a sentinel address or a null pointer
+     /// in response to a zero-size allocation request.)
+     ///
+     /// The allocated block of memory may or may not be initialized.
+     ///
+     /// # Errors
+     ///
+     /// Returning a null pointer indicates that either memory is exhausted
+     /// or `layout` does not meet this allocator's size or alignment constraints.
+     ///
+     /// Implementations are encouraged to return null on memory
+     /// exhaustion rather than aborting, but this is not
+     /// a strict requirement. (Specifically: it is *legal* to
+     /// implement this trait atop an underlying native allocation
+     /// library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to an
+     /// allocation error are encouraged to call the [`handle_alloc_error`] function,
+     /// rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     #[stable(feature = "global_alloc", since = "1.28.0")]
+     unsafe fn alloc(&self, layout: Layout) -> *mut u8;
+ 
+     /// Deallocate the block of memory at the given `ptr` pointer with the given `layout`.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe because undefined behavior can result
+     /// if the caller does not ensure all of the following:
+     ///
+     /// * `ptr` must denote a block of memory currently allocated via
+     ///   this allocator,
+     ///
+     /// * `layout` must be the same layout that was used
+     ///   to allocate that block of memory,
+     #[stable(feature = "global_alloc", since = "1.28.0")]
+     unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout);
+ 
+     /// Behaves like `alloc`, but also ensures that the contents
+     /// are set to zero before being returned.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe for the same reasons that `alloc` is.
+     /// However the allocated block of memory is guaranteed to be initialized.
+     ///
+     /// # Errors
+     ///
+     /// Returning a null pointer indicates that either memory is exhausted
+     /// or `layout` does not meet allocator's size or alignment constraints,
+     /// just as in `alloc`.
+     ///
+     /// Clients wishing to abort computation in response to an
+     /// allocation error are encouraged to call the [`handle_alloc_error`] function,
+     /// rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     #[stable(feature = "global_alloc", since = "1.28.0")]
+     unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 {
+         let size = layout.size();
+         // SAFETY: the safety contract for `alloc` must be upheld by the caller.
+         let ptr = unsafe { self.alloc(layout) };
+         if !ptr.is_null() {
+             // SAFETY: as allocation succeeded, the region from `ptr`
+             // of size `size` is guaranteed to be valid for writes.
+             unsafe { ptr::write_bytes(ptr, 0, size) };
+         }
+         ptr
+     }
+ 
+     /// Shrink or grow a block of memory to the given `new_size`.
+     /// The block is described by the given `ptr` pointer and `layout`.
+     ///
+     /// If this returns a non-null pointer, then ownership of the memory block
+     /// referenced by `ptr` has been transferred to this allocator.
+     /// The memory may or may not have been deallocated,
+     /// and should be considered unusable (unless of course it was
+     /// transferred back to the caller again via the return value of
+     /// this method). The new memory block is allocated with `layout`, but
+     /// with the `size` updated to `new_size`.
+     ///
+     /// If this method returns null, then ownership of the memory
+     /// block has not been transferred to this allocator, and the
+     /// contents of the memory block are unaltered.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe because undefined behavior can result
+     /// if the caller does not ensure all of the following:
+     ///
+     /// * `ptr` must be currently allocated via this allocator,
+     ///
+     /// * `layout` must be the same layout that was used
+     ///   to allocate that block of memory,
+     ///
+     /// * `new_size` must be greater than zero.
+     ///
+     /// * `new_size`, when rounded up to the nearest multiple of `layout.align()`,
+     ///   must not overflow (i.e., the rounded value must be less than `usize::MAX`).
+     ///
+     /// (Extension subtraits might provide more specific bounds on
+     /// behavior, e.g., guarantee a sentinel address or a null pointer
+     /// in response to a zero-size allocation request.)
+     ///
+     /// # Errors
+     ///
+     /// Returns null if the new layout does not meet the size
+     /// and alignment constraints of the allocator, or if reallocation
+     /// otherwise fails.
+     ///
+     /// Implementations are encouraged to return null on memory
+     /// exhaustion rather than panicking or aborting, but this is not
+     /// a strict requirement. (Specifically: it is *legal* to
+     /// implement this trait atop an underlying native allocation
+     /// library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to a
+     /// reallocation error are encouraged to call the [`handle_alloc_error`] function,
+     /// rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     #[stable(feature = "global_alloc", since = "1.28.0")]
+     unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 {
+         // SAFETY: the caller must ensure that the `new_size` does not overflow.
+         // `layout.align()` comes from a `Layout` and is thus guaranteed to be valid.
+         let new_layout = unsafe { Layout::from_size_align_unchecked(new_size, layout.align()) };
+         // SAFETY: the caller must ensure that `new_layout` is greater than zero.
+         let new_ptr = unsafe { self.alloc(new_layout) };
+         if !new_ptr.is_null() {
+             // SAFETY: the previously allocated block cannot overlap the newly allocated block.
+             // The safety contract for `dealloc` must be upheld by the caller.
+             unsafe {
+                 ptr::copy_nonoverlapping(ptr, new_ptr, cmp::min(layout.size(), new_size));
+                 self.dealloc(ptr, layout);
+             }
+         }
+         new_ptr
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/alloc/layout.rs gcc-16-20251102/libgrust/rustc-lib/core/src/alloc/layout.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/alloc/layout.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/alloc/layout.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,410 ----
+ use crate::cmp;
+ use crate::fmt;
+ use crate::mem;
+ use crate::num::NonZeroUsize;
+ use crate::ptr::NonNull;
+ 
+ const fn size_align<T>() -> (usize, usize) {
+     (mem::size_of::<T>(), mem::align_of::<T>())
+ }
+ 
+ /// Layout of a block of memory.
+ ///
+ /// An instance of `Layout` describes a particular layout of memory.
+ /// You build a `Layout` up as an input to give to an allocator.
+ ///
+ /// All layouts have an associated size and a power-of-two alignment.
+ ///
+ /// (Note that layouts are *not* required to have non-zero size,
+ /// even though `GlobalAlloc` requires that all memory requests
+ /// be non-zero in size. A caller must either ensure that conditions
+ /// like this are met, use specific allocators with looser
+ /// requirements, or use the more lenient `AllocRef` interface.)
+ #[stable(feature = "alloc_layout", since = "1.28.0")]
+ #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+ #[lang = "alloc_layout"]
+ pub struct Layout {
+     // size of the requested block of memory, measured in bytes.
+     size_: usize,
+ 
+     // alignment of the requested block of memory, measured in bytes.
+     // we ensure that this is always a power-of-two, because API's
+     // like `posix_memalign` require it and it is a reasonable
+     // constraint to impose on Layout constructors.
+     //
+     // (However, we do not analogously require `align >= sizeof(void*)`,
+     //  even though that is *also* a requirement of `posix_memalign`.)
+     align_: NonZeroUsize,
+ }
+ 
+ impl Layout {
+     /// Constructs a `Layout` from a given `size` and `align`,
+     /// or returns `LayoutErr` if any of the following conditions
+     /// are not met:
+     ///
+     /// * `align` must not be zero,
+     ///
+     /// * `align` must be a power of two,
+     ///
+     /// * `size`, when rounded up to the nearest multiple of `align`,
+     ///    must not overflow (i.e., the rounded value must be less than
+     ///    or equal to `usize::MAX`).
+     #[stable(feature = "alloc_layout", since = "1.28.0")]
+     #[rustc_const_unstable(feature = "const_alloc_layout", issue = "67521")]
+     #[inline]
+     pub const fn from_size_align(size: usize, align: usize) -> Result<Self, LayoutErr> {
+         if !align.is_power_of_two() {
+             return Err(LayoutErr { private: () });
+         }
+ 
+         // (power-of-two implies align != 0.)
+ 
+         // Rounded up size is:
+         //   size_rounded_up = (size + align - 1) & !(align - 1);
+         //
+         // We know from above that align != 0. If adding (align - 1)
+         // does not overflow, then rounding up will be fine.
+         //
+         // Conversely, &-masking with !(align - 1) will subtract off
+         // only low-order-bits. Thus if overflow occurs with the sum,
+         // the &-mask cannot subtract enough to undo that overflow.
+         //
+         // Above implies that checking for summation overflow is both
+         // necessary and sufficient.
+         if size > usize::MAX - (align - 1) {
+             return Err(LayoutErr { private: () });
+         }
+ 
+         // SAFETY: the conditions for `from_size_align_unchecked` have been
+         // checked above.
+         unsafe { Ok(Layout::from_size_align_unchecked(size, align)) }
+     }
+ 
+     /// Creates a layout, bypassing all checks.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe as it does not verify the preconditions from
+     /// [`Layout::from_size_align`].
+     #[stable(feature = "alloc_layout", since = "1.28.0")]
+     #[rustc_const_stable(feature = "alloc_layout", since = "1.28.0")]
+     #[inline]
+     pub const unsafe fn from_size_align_unchecked(size: usize, align: usize) -> Self {
+         // SAFETY: the caller must ensure that `align` is greater than zero.
+         Layout { size_: size, align_: unsafe { NonZeroUsize::new_unchecked(align) } }
+     }
+ 
+     /// The minimum size in bytes for a memory block of this layout.
+     #[stable(feature = "alloc_layout", since = "1.28.0")]
+     #[rustc_const_unstable(feature = "const_alloc_layout", issue = "67521")]
+     #[inline]
+     pub const fn size(&self) -> usize {
+         self.size_
+     }
+ 
+     /// The minimum byte alignment for a memory block of this layout.
+     #[stable(feature = "alloc_layout", since = "1.28.0")]
+     #[rustc_const_unstable(feature = "const_alloc_layout", issue = "67521")]
+     #[inline]
+     pub const fn align(&self) -> usize {
+         self.align_.get()
+     }
+ 
+     /// Constructs a `Layout` suitable for holding a value of type `T`.
+     #[stable(feature = "alloc_layout", since = "1.28.0")]
+     #[rustc_const_stable(feature = "alloc_layout_const_new", since = "1.42.0")]
+     #[inline]
+     pub const fn new<T>() -> Self {
+         let (size, align) = size_align::<T>();
+         // SAFETY: the align is guaranteed by Rust to be a power of two and
+         // the size+align combo is guaranteed to fit in our address space. As a
+         // result use the unchecked constructor here to avoid inserting code
+         // that panics if it isn't optimized well enough.
+         unsafe { Layout::from_size_align_unchecked(size, align) }
+     }
+ 
+     /// Produces layout describing a record that could be used to
+     /// allocate backing structure for `T` (which could be a trait
+     /// or other unsized type like a slice).
+     #[stable(feature = "alloc_layout", since = "1.28.0")]
+     #[inline]
+     pub fn for_value<T: ?Sized>(t: &T) -> Self {
+         let (size, align) = (mem::size_of_val(t), mem::align_of_val(t));
+         debug_assert!(Layout::from_size_align(size, align).is_ok());
+         // SAFETY: see rationale in `new` for why this is using the unsafe variant
+         unsafe { Layout::from_size_align_unchecked(size, align) }
+     }
+ 
+     /// Produces layout describing a record that could be used to
+     /// allocate backing structure for `T` (which could be a trait
+     /// or other unsized type like a slice).
+     ///
+     /// # Safety
+     ///
+     /// This function is only safe to call if the following conditions hold:
+     ///
+     /// - If `T` is `Sized`, this function is always safe to call.
+     /// - If the unsized tail of `T` is:
+     ///     - a [slice], then the length of the slice tail must be an intialized
+     ///       integer, and the size of the *entire value*
+     ///       (dynamic tail length + statically sized prefix) must fit in `isize`.
+     ///     - a [trait object], then the vtable part of the pointer must point
+     ///       to a valid vtable for the type `T` acquired by an unsizing coersion,
+     ///       and the size of the *entire value*
+     ///       (dynamic tail length + statically sized prefix) must fit in `isize`.
+     ///     - an (unstable) [extern type], then this function is always safe to
+     ///       call, but may panic or otherwise return the wrong value, as the
+     ///       extern type's layout is not known. This is the same behavior as
+     ///       [`Layout::for_value`] on a reference to an extern type tail.
+     ///     - otherwise, it is conservatively not allowed to call this function.
+     ///
+     /// [slice]: ../../std/primitive.slice.html
+     /// [trait object]: ../../book/ch17-02-trait-objects.html
+     /// [extern type]: ../../unstable-book/language-features/extern-types.html
+     #[unstable(feature = "layout_for_ptr", issue = "69835")]
+     pub unsafe fn for_value_raw<T: ?Sized>(t: *const T) -> Self {
+         // SAFETY: we pass along the prerequisites of these functions to the caller
+         let (size, align) = unsafe { (mem::size_of_val_raw(t), mem::align_of_val_raw(t)) };
+         debug_assert!(Layout::from_size_align(size, align).is_ok());
+         // SAFETY: see rationale in `new` for why this is using the unsafe variant
+         unsafe { Layout::from_size_align_unchecked(size, align) }
+     }
+ 
+     /// Creates a `NonNull` that is dangling, but well-aligned for this Layout.
+     ///
+     /// Note that the pointer value may potentially represent a valid pointer,
+     /// which means this must not be used as a "not yet initialized"
+     /// sentinel value. Types that lazily allocate must track initialization by
+     /// some other means.
+     #[unstable(feature = "alloc_layout_extra", issue = "55724")]
+     #[rustc_const_unstable(feature = "alloc_layout_extra", issue = "55724")]
+     #[inline]
+     pub const fn dangling(&self) -> NonNull<u8> {
+         // SAFETY: align is guaranteed to be non-zero
+         unsafe { NonNull::new_unchecked(self.align() as *mut u8) }
+     }
+ 
+     /// Creates a layout describing the record that can hold a value
+     /// of the same layout as `self`, but that also is aligned to
+     /// alignment `align` (measured in bytes).
+     ///
+     /// If `self` already meets the prescribed alignment, then returns
+     /// `self`.
+     ///
+     /// Note that this method does not add any padding to the overall
+     /// size, regardless of whether the returned layout has a different
+     /// alignment. In other words, if `K` has size 16, `K.align_to(32)`
+     /// will *still* have size 16.
+     ///
+     /// Returns an error if the combination of `self.size()` and the given
+     /// `align` violates the conditions listed in [`Layout::from_size_align`].
+     #[stable(feature = "alloc_layout_manipulation", since = "1.44.0")]
+     #[inline]
+     pub fn align_to(&self, align: usize) -> Result<Self, LayoutErr> {
+         Layout::from_size_align(self.size(), cmp::max(self.align(), align))
+     }
+ 
+     /// Returns the amount of padding we must insert after `self`
+     /// to ensure that the following address will satisfy `align`
+     /// (measured in bytes).
+     ///
+     /// e.g., if `self.size()` is 9, then `self.padding_needed_for(4)`
+     /// returns 3, because that is the minimum number of bytes of
+     /// padding required to get a 4-aligned address (assuming that the
+     /// corresponding memory block starts at a 4-aligned address).
+     ///
+     /// The return value of this function has no meaning if `align` is
+     /// not a power-of-two.
+     ///
+     /// Note that the utility of the returned value requires `align`
+     /// to be less than or equal to the alignment of the starting
+     /// address for the whole allocated block of memory. One way to
+     /// satisfy this constraint is to ensure `align <= self.align()`.
+     #[unstable(feature = "alloc_layout_extra", issue = "55724")]
+     #[rustc_const_unstable(feature = "const_alloc_layout", issue = "67521")]
+     #[inline]
+     pub const fn padding_needed_for(&self, align: usize) -> usize {
+         let len = self.size();
+ 
+         // Rounded up value is:
+         //   len_rounded_up = (len + align - 1) & !(align - 1);
+         // and then we return the padding difference: `len_rounded_up - len`.
+         //
+         // We use modular arithmetic throughout:
+         //
+         // 1. align is guaranteed to be > 0, so align - 1 is always
+         //    valid.
+         //
+         // 2. `len + align - 1` can overflow by at most `align - 1`,
+         //    so the &-mask with `!(align - 1)` will ensure that in the
+         //    case of overflow, `len_rounded_up` will itself be 0.
+         //    Thus the returned padding, when added to `len`, yields 0,
+         //    which trivially satisfies the alignment `align`.
+         //
+         // (Of course, attempts to allocate blocks of memory whose
+         // size and padding overflow in the above manner should cause
+         // the allocator to yield an error anyway.)
+ 
+         let len_rounded_up = len.wrapping_add(align).wrapping_sub(1) & !align.wrapping_sub(1);
+         len_rounded_up.wrapping_sub(len)
+     }
+ 
+     /// Creates a layout by rounding the size of this layout up to a multiple
+     /// of the layout's alignment.
+     ///
+     /// This is equivalent to adding the result of `padding_needed_for`
+     /// to the layout's current size.
+     #[stable(feature = "alloc_layout_manipulation", since = "1.44.0")]
+     #[inline]
+     pub fn pad_to_align(&self) -> Layout {
+         let pad = self.padding_needed_for(self.align());
+         // This cannot overflow. Quoting from the invariant of Layout:
+         // > `size`, when rounded up to the nearest multiple of `align`,
+         // > must not overflow (i.e., the rounded value must be less than
+         // > `usize::MAX`)
+         let new_size = self.size() + pad;
+ 
+         Layout::from_size_align(new_size, self.align()).unwrap()
+     }
+ 
+     /// Creates a layout describing the record for `n` instances of
+     /// `self`, with a suitable amount of padding between each to
+     /// ensure that each instance is given its requested size and
+     /// alignment. On success, returns `(k, offs)` where `k` is the
+     /// layout of the array and `offs` is the distance between the start
+     /// of each element in the array.
+     ///
+     /// On arithmetic overflow, returns `LayoutErr`.
+     #[unstable(feature = "alloc_layout_extra", issue = "55724")]
+     #[inline]
+     pub fn repeat(&self, n: usize) -> Result<(Self, usize), LayoutErr> {
+         // This cannot overflow. Quoting from the invariant of Layout:
+         // > `size`, when rounded up to the nearest multiple of `align`,
+         // > must not overflow (i.e., the rounded value must be less than
+         // > `usize::MAX`)
+         let padded_size = self.size() + self.padding_needed_for(self.align());
+         let alloc_size = padded_size.checked_mul(n).ok_or(LayoutErr { private: () })?;
+ 
+         // SAFETY: self.align is already known to be valid and alloc_size has been
+         // padded already.
+         unsafe { Ok((Layout::from_size_align_unchecked(alloc_size, self.align()), padded_size)) }
+     }
+ 
+     /// Creates a layout describing the record for `self` followed by
+     /// `next`, including any necessary padding to ensure that `next`
+     /// will be properly aligned, but *no trailing padding*.
+     ///
+     /// In order to match C representation layout `repr(C)`, you should
+     /// call `pad_to_align` after extending the layout with all fields.
+     /// (There is no way to match the default Rust representation
+     /// layout `repr(Rust)`, as it is unspecified.)
+     ///
+     /// Note that the alignment of the resulting layout will be the maximum of
+     /// those of `self` and `next`, in order to ensure alignment of both parts.
+     ///
+     /// Returns `Ok((k, offset))`, where `k` is layout of the concatenated
+     /// record and `offset` is the relative location, in bytes, of the
+     /// start of the `next` embedded within the concatenated record
+     /// (assuming that the record itself starts at offset 0).
+     ///
+     /// On arithmetic overflow, returns `LayoutErr`.
+     ///
+     /// # Examples
+     ///
+     /// To calculate the layout of a `#[repr(C)]` structure and the offsets of
+     /// the fields from its fields' layouts:
+     ///
+     /// ```rust
+     /// # use std::alloc::{Layout, LayoutErr};
+     /// pub fn repr_c(fields: &[Layout]) -> Result<(Layout, Vec<usize>), LayoutErr> {
+     ///     let mut offsets = Vec::new();
+     ///     let mut layout = Layout::from_size_align(0, 1)?;
+     ///     for &field in fields {
+     ///         let (new_layout, offset) = layout.extend(field)?;
+     ///         layout = new_layout;
+     ///         offsets.push(offset);
+     ///     }
+     ///     // Remember to finalize with `pad_to_align`!
+     ///     Ok((layout.pad_to_align(), offsets))
+     /// }
+     /// # // test that it works
+     /// # #[repr(C)] struct S { a: u64, b: u32, c: u16, d: u32 }
+     /// # let s = Layout::new::<S>();
+     /// # let u16 = Layout::new::<u16>();
+     /// # let u32 = Layout::new::<u32>();
+     /// # let u64 = Layout::new::<u64>();
+     /// # assert_eq!(repr_c(&[u64, u32, u16, u32]), Ok((s, vec![0, 8, 12, 16])));
+     /// ```
+     #[stable(feature = "alloc_layout_manipulation", since = "1.44.0")]
+     #[inline]
+     pub fn extend(&self, next: Self) -> Result<(Self, usize), LayoutErr> {
+         let new_align = cmp::max(self.align(), next.align());
+         let pad = self.padding_needed_for(next.align());
+ 
+         let offset = self.size().checked_add(pad).ok_or(LayoutErr { private: () })?;
+         let new_size = offset.checked_add(next.size()).ok_or(LayoutErr { private: () })?;
+ 
+         let layout = Layout::from_size_align(new_size, new_align)?;
+         Ok((layout, offset))
+     }
+ 
+     /// Creates a layout describing the record for `n` instances of
+     /// `self`, with no padding between each instance.
+     ///
+     /// Note that, unlike `repeat`, `repeat_packed` does not guarantee
+     /// that the repeated instances of `self` will be properly
+     /// aligned, even if a given instance of `self` is properly
+     /// aligned. In other words, if the layout returned by
+     /// `repeat_packed` is used to allocate an array, it is not
+     /// guaranteed that all elements in the array will be properly
+     /// aligned.
+     ///
+     /// On arithmetic overflow, returns `LayoutErr`.
+     #[unstable(feature = "alloc_layout_extra", issue = "55724")]
+     #[inline]
+     pub fn repeat_packed(&self, n: usize) -> Result<Self, LayoutErr> {
+         let size = self.size().checked_mul(n).ok_or(LayoutErr { private: () })?;
+         Layout::from_size_align(size, self.align())
+     }
+ 
+     /// Creates a layout describing the record for `self` followed by
+     /// `next` with no additional padding between the two. Since no
+     /// padding is inserted, the alignment of `next` is irrelevant,
+     /// and is not incorporated *at all* into the resulting layout.
+     ///
+     /// On arithmetic overflow, returns `LayoutErr`.
+     #[unstable(feature = "alloc_layout_extra", issue = "55724")]
+     #[inline]
+     pub fn extend_packed(&self, next: Self) -> Result<Self, LayoutErr> {
+         let new_size = self.size().checked_add(next.size()).ok_or(LayoutErr { private: () })?;
+         Layout::from_size_align(new_size, self.align())
+     }
+ 
+     /// Creates a layout describing the record for a `[T; n]`.
+     ///
+     /// On arithmetic overflow, returns `LayoutErr`.
+     #[stable(feature = "alloc_layout_manipulation", since = "1.44.0")]
+     #[inline]
+     pub fn array<T>(n: usize) -> Result<Self, LayoutErr> {
+         let (layout, offset) = Layout::new::<T>().repeat(n)?;
+         debug_assert_eq!(offset, mem::size_of::<T>());
+         Ok(layout.pad_to_align())
+     }
+ }
+ 
+ /// The parameters given to `Layout::from_size_align`
+ /// or some other `Layout` constructor
+ /// do not satisfy its documented constraints.
+ #[stable(feature = "alloc_layout", since = "1.28.0")]
+ #[derive(Clone, PartialEq, Eq, Debug)]
+ pub struct LayoutErr {
+     private: (),
+ }
+ 
+ // (we need this for downstream impl of trait Error)
+ #[stable(feature = "alloc_layout", since = "1.28.0")]
+ impl fmt::Display for LayoutErr {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.write_str("invalid parameters to Layout::from_size_align")
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/alloc/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/alloc/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/alloc/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/alloc/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,392 ----
+ //! Memory allocation APIs
+ 
+ #![stable(feature = "alloc_module", since = "1.28.0")]
+ 
+ mod global;
+ mod layout;
+ 
+ #[stable(feature = "global_alloc", since = "1.28.0")]
+ pub use self::global::GlobalAlloc;
+ #[stable(feature = "alloc_layout", since = "1.28.0")]
+ pub use self::layout::{Layout, LayoutErr};
+ 
+ use crate::fmt;
+ use crate::ptr::{self, NonNull};
+ 
+ /// The `AllocError` error indicates an allocation failure
+ /// that may be due to resource exhaustion or to
+ /// something wrong when combining the given input arguments with this
+ /// allocator.
+ #[unstable(feature = "allocator_api", issue = "32838")]
+ #[derive(Copy, Clone, PartialEq, Eq, Debug)]
+ pub struct AllocError;
+ 
+ // (we need this for downstream impl of trait Error)
+ #[unstable(feature = "allocator_api", issue = "32838")]
+ impl fmt::Display for AllocError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.write_str("memory allocation failed")
+     }
+ }
+ 
+ /// An implementation of `AllocRef` can allocate, grow, shrink, and deallocate arbitrary blocks of
+ /// data described via [`Layout`][].
+ ///
+ /// `AllocRef` is designed to be implemented on ZSTs, references, or smart pointers because having
+ /// an allocator like `MyAlloc([u8; N])` cannot be moved, without updating the pointers to the
+ /// allocated memory.
+ ///
+ /// Unlike [`GlobalAlloc`][], zero-sized allocations are allowed in `AllocRef`. If an underlying
+ /// allocator does not support this (like jemalloc) or return a null pointer (such as
+ /// `libc::malloc`), this must be caught by the implementation.
+ ///
+ /// ### Currently allocated memory
+ ///
+ /// Some of the methods require that a memory block be *currently allocated* via an allocator. This
+ /// means that:
+ ///
+ /// * the starting address for that memory block was previously returned by [`alloc`], [`grow`], or
+ ///   [`shrink`], and
+ ///
+ /// * the memory block has not been subsequently deallocated, where blocks are either deallocated
+ ///   directly by being passed to [`dealloc`] or were changed by being passed to [`grow`] or
+ ///   [`shrink`] that returns `Ok`. If `grow` or `shrink` have returned `Err`, the passed pointer
+ ///   remains valid.
+ ///
+ /// [`alloc`]: AllocRef::alloc
+ /// [`grow`]: AllocRef::grow
+ /// [`shrink`]: AllocRef::shrink
+ /// [`dealloc`]: AllocRef::dealloc
+ ///
+ /// ### Memory fitting
+ ///
+ /// Some of the methods require that a layout *fit* a memory block. What it means for a layout to
+ /// "fit" a memory block means (or equivalently, for a memory block to "fit" a layout) is that the
+ /// following conditions must hold:
+ ///
+ /// * The block must be allocated with the same alignment as [`layout.align()`], and
+ ///
+ /// * The provided [`layout.size()`] must fall in the range `min ..= max`, where:
+ ///   - `min` is the size of the layout most recently used to allocate the block, and
+ ///   - `max` is the latest actual size returned from [`alloc`], [`grow`], or [`shrink`].
+ ///
+ /// [`layout.align()`]: Layout::align
+ /// [`layout.size()`]: Layout::size
+ ///
+ /// # Safety
+ ///
+ /// * Memory blocks returned from an allocator must point to valid memory and retain their validity
+ ///   until the instance and all of its clones are dropped,
+ ///
+ /// * cloning or moving the allocator must not invalidate memory blocks returned from this
+ ///   allocator. A cloned allocator must behave like the same allocator, and
+ ///
+ /// * any pointer to a memory block which is [*currently allocated*] may be passed to any other
+ ///   method of the allocator.
+ ///
+ /// [*currently allocated*]: #currently-allocated-memory
+ #[unstable(feature = "allocator_api", issue = "32838")]
+ pub unsafe trait AllocRef {
+     /// Attempts to allocate a block of memory.
+     ///
+     /// On success, returns a [`NonNull<[u8]>`][NonNull] meeting the size and alignment guarantees of `layout`.
+     ///
+     /// The returned block may have a larger size than specified by `layout.size()`, and may or may
+     /// not have its contents initialized.
+     ///
+     /// # Errors
+     ///
+     /// Returning `Err` indicates that either memory is exhausted or `layout` does not meet
+     /// allocator's size or alignment constraints.
+     ///
+     /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or
+     /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement
+     /// this trait atop an underlying native allocation library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to an allocation error are encouraged to
+     /// call the [`handle_alloc_error`] function, rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     fn alloc(&self, layout: Layout) -> Result<NonNull<[u8]>, AllocError>;
+ 
+     /// Behaves like `alloc`, but also ensures that the returned memory is zero-initialized.
+     ///
+     /// # Errors
+     ///
+     /// Returning `Err` indicates that either memory is exhausted or `layout` does not meet
+     /// allocator's size or alignment constraints.
+     ///
+     /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or
+     /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement
+     /// this trait atop an underlying native allocation library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to an allocation error are encouraged to
+     /// call the [`handle_alloc_error`] function, rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     fn alloc_zeroed(&self, layout: Layout) -> Result<NonNull<[u8]>, AllocError> {
+         let ptr = self.alloc(layout)?;
+         // SAFETY: `alloc` returns a valid memory block
+         unsafe { ptr.as_non_null_ptr().as_ptr().write_bytes(0, ptr.len()) }
+         Ok(ptr)
+     }
+ 
+     /// Deallocates the memory referenced by `ptr`.
+     ///
+     /// # Safety
+     ///
+     /// * `ptr` must denote a block of memory [*currently allocated*] via this allocator, and
+     /// * `layout` must [*fit*] that block of memory.
+     ///
+     /// [*currently allocated*]: #currently-allocated-memory
+     /// [*fit*]: #memory-fitting
+     unsafe fn dealloc(&self, ptr: NonNull<u8>, layout: Layout);
+ 
+     /// Attempts to extend the memory block.
+     ///
+     /// Returns a new [`NonNull<[u8]>`][NonNull] containing a pointer and the actual size of the allocated
+     /// memory. The pointer is suitable for holding data described by `new_layout`. To accomplish
+     /// this, the allocator may extend the allocation referenced by `ptr` to fit the new layout.
+     ///
+     /// If this returns `Ok`, then ownership of the memory block referenced by `ptr` has been
+     /// transferred to this allocator. The memory may or may not have been freed, and should be
+     /// considered unusable unless it was transferred back to the caller again via the return value
+     /// of this method.
+     ///
+     /// If this method returns `Err`, then ownership of the memory block has not been transferred to
+     /// this allocator, and the contents of the memory block are unaltered.
+     ///
+     /// # Safety
+     ///
+     /// * `ptr` must denote a block of memory [*currently allocated*] via this allocator.
+     /// * `old_layout` must [*fit*] that block of memory (The `new_layout` argument need not fit it.).
+     /// * `new_layout.size()` must be greater than or equal to `old_layout.size()`.
+     ///
+     /// [*currently allocated*]: #currently-allocated-memory
+     /// [*fit*]: #memory-fitting
+     ///
+     /// # Errors
+     ///
+     /// Returns `Err` if the new layout does not meet the allocator's size and alignment
+     /// constraints of the allocator, or if growing otherwise fails.
+     ///
+     /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or
+     /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement
+     /// this trait atop an underlying native allocation library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to an allocation error are encouraged to
+     /// call the [`handle_alloc_error`] function, rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     unsafe fn grow(
+         &self,
+         ptr: NonNull<u8>,
+         old_layout: Layout,
+         new_layout: Layout,
+     ) -> Result<NonNull<[u8]>, AllocError> {
+         debug_assert!(
+             new_layout.size() >= old_layout.size(),
+             "`new_layout.size()` must be greater than or equal to `old_layout.size()`"
+         );
+ 
+         let new_ptr = self.alloc(new_layout)?;
+ 
+         // SAFETY: because `new_layout.size()` must be greater than or equal to
+         // `old_layout.size()`, both the old and new memory allocation are valid for reads and
+         // writes for `old_layout.size()` bytes. Also, because the old allocation wasn't yet
+         // deallocated, it cannot overlap `new_ptr`. Thus, the call to `copy_nonoverlapping` is
+         // safe. The safety contract for `dealloc` must be upheld by the caller.
+         unsafe {
+             ptr::copy_nonoverlapping(ptr.as_ptr(), new_ptr.as_mut_ptr(), old_layout.size());
+             self.dealloc(ptr, old_layout);
+         }
+ 
+         Ok(new_ptr)
+     }
+ 
+     /// Behaves like `grow`, but also ensures that the new contents are set to zero before being
+     /// returned.
+     ///
+     /// The memory block will contain the following contents after a successful call to
+     /// `grow_zeroed`:
+     ///   * Bytes `0..old_layout.size()` are preserved from the original allocation.
+     ///   * Bytes `old_layout.size()..old_size` will either be preserved or zeroed, depending on
+     ///     the allocator implementation. `old_size` refers to the size of the memory block prior
+     ///     to the `grow_zeroed` call, which may be larger than the size that was originally
+     ///     requested when it was allocated.
+     ///   * Bytes `old_size..new_size` are zeroed. `new_size` refers to the size of the memory
+     ///     block returned by the `grow_zeroed` call.
+     ///
+     /// # Safety
+     ///
+     /// * `ptr` must denote a block of memory [*currently allocated*] via this allocator.
+     /// * `old_layout` must [*fit*] that block of memory (The `new_layout` argument need not fit it.).
+     /// * `new_layout.size()` must be greater than or equal to `old_layout.size()`.
+     ///
+     /// [*currently allocated*]: #currently-allocated-memory
+     /// [*fit*]: #memory-fitting
+     ///
+     /// # Errors
+     ///
+     /// Returns `Err` if the new layout does not meet the allocator's size and alignment
+     /// constraints of the allocator, or if growing otherwise fails.
+     ///
+     /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or
+     /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement
+     /// this trait atop an underlying native allocation library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to an allocation error are encouraged to
+     /// call the [`handle_alloc_error`] function, rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     unsafe fn grow_zeroed(
+         &self,
+         ptr: NonNull<u8>,
+         old_layout: Layout,
+         new_layout: Layout,
+     ) -> Result<NonNull<[u8]>, AllocError> {
+         debug_assert!(
+             new_layout.size() >= old_layout.size(),
+             "`new_layout.size()` must be greater than or equal to `old_layout.size()`"
+         );
+ 
+         let new_ptr = self.alloc_zeroed(new_layout)?;
+ 
+         // SAFETY: because `new_layout.size()` must be greater than or equal to
+         // `old_layout.size()`, both the old and new memory allocation are valid for reads and
+         // writes for `old_layout.size()` bytes. Also, because the old allocation wasn't yet
+         // deallocated, it cannot overlap `new_ptr`. Thus, the call to `copy_nonoverlapping` is
+         // safe. The safety contract for `dealloc` must be upheld by the caller.
+         unsafe {
+             ptr::copy_nonoverlapping(ptr.as_ptr(), new_ptr.as_mut_ptr(), old_layout.size());
+             self.dealloc(ptr, old_layout);
+         }
+ 
+         Ok(new_ptr)
+     }
+ 
+     /// Attempts to shrink the memory block.
+     ///
+     /// Returns a new [`NonNull<[u8]>`][NonNull] containing a pointer and the actual size of the allocated
+     /// memory. The pointer is suitable for holding data described by `new_layout`. To accomplish
+     /// this, the allocator may shrink the allocation referenced by `ptr` to fit the new layout.
+     ///
+     /// If this returns `Ok`, then ownership of the memory block referenced by `ptr` has been
+     /// transferred to this allocator. The memory may or may not have been freed, and should be
+     /// considered unusable unless it was transferred back to the caller again via the return value
+     /// of this method.
+     ///
+     /// If this method returns `Err`, then ownership of the memory block has not been transferred to
+     /// this allocator, and the contents of the memory block are unaltered.
+     ///
+     /// # Safety
+     ///
+     /// * `ptr` must denote a block of memory [*currently allocated*] via this allocator.
+     /// * `old_layout` must [*fit*] that block of memory (The `new_layout` argument need not fit it.).
+     /// * `new_layout.size()` must be smaller than or equal to `old_layout.size()`.
+     ///
+     /// [*currently allocated*]: #currently-allocated-memory
+     /// [*fit*]: #memory-fitting
+     ///
+     /// # Errors
+     ///
+     /// Returns `Err` if the new layout does not meet the allocator's size and alignment
+     /// constraints of the allocator, or if shrinking otherwise fails.
+     ///
+     /// Implementations are encouraged to return `Err` on memory exhaustion rather than panicking or
+     /// aborting, but this is not a strict requirement. (Specifically: it is *legal* to implement
+     /// this trait atop an underlying native allocation library that aborts on memory exhaustion.)
+     ///
+     /// Clients wishing to abort computation in response to an allocation error are encouraged to
+     /// call the [`handle_alloc_error`] function, rather than directly invoking `panic!` or similar.
+     ///
+     /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html
+     unsafe fn shrink(
+         &self,
+         ptr: NonNull<u8>,
+         old_layout: Layout,
+         new_layout: Layout,
+     ) -> Result<NonNull<[u8]>, AllocError> {
+         debug_assert!(
+             new_layout.size() <= old_layout.size(),
+             "`new_layout.size()` must be smaller than or equal to `old_layout.size()`"
+         );
+ 
+         let new_ptr = self.alloc(new_layout)?;
+ 
+         // SAFETY: because `new_layout.size()` must be lower than or equal to
+         // `old_layout.size()`, both the old and new memory allocation are valid for reads and
+         // writes for `new_layout.size()` bytes. Also, because the old allocation wasn't yet
+         // deallocated, it cannot overlap `new_ptr`. Thus, the call to `copy_nonoverlapping` is
+         // safe. The safety contract for `dealloc` must be upheld by the caller.
+         unsafe {
+             ptr::copy_nonoverlapping(ptr.as_ptr(), new_ptr.as_mut_ptr(), new_layout.size());
+             self.dealloc(ptr, old_layout);
+         }
+ 
+         Ok(new_ptr)
+     }
+ 
+     /// Creates a "by reference" adaptor for this instance of `AllocRef`.
+     ///
+     /// The returned adaptor also implements `AllocRef` and will simply borrow this.
+     #[inline(always)]
+     fn by_ref(&self) -> &Self {
+         self
+     }
+ }
+ 
+ #[unstable(feature = "allocator_api", issue = "32838")]
+ unsafe impl<A> AllocRef for &A
+ where
+     A: AllocRef + ?Sized,
+ {
+     #[inline]
+     fn alloc(&self, layout: Layout) -> Result<NonNull<[u8]>, AllocError> {
+         (**self).alloc(layout)
+     }
+ 
+     #[inline]
+     fn alloc_zeroed(&self, layout: Layout) -> Result<NonNull<[u8]>, AllocError> {
+         (**self).alloc_zeroed(layout)
+     }
+ 
+     #[inline]
+     unsafe fn dealloc(&self, ptr: NonNull<u8>, layout: Layout) {
+         // SAFETY: the safety contract must be upheld by the caller
+         unsafe { (**self).dealloc(ptr, layout) }
+     }
+ 
+     #[inline]
+     unsafe fn grow(
+         &self,
+         ptr: NonNull<u8>,
+         old_layout: Layout,
+         new_layout: Layout,
+     ) -> Result<NonNull<[u8]>, AllocError> {
+         // SAFETY: the safety contract must be upheld by the caller
+         unsafe { (**self).grow(ptr, old_layout, new_layout) }
+     }
+ 
+     #[inline]
+     unsafe fn grow_zeroed(
+         &self,
+         ptr: NonNull<u8>,
+         old_layout: Layout,
+         new_layout: Layout,
+     ) -> Result<NonNull<[u8]>, AllocError> {
+         // SAFETY: the safety contract must be upheld by the caller
+         unsafe { (**self).grow_zeroed(ptr, old_layout, new_layout) }
+     }
+ 
+     #[inline]
+     unsafe fn shrink(
+         &self,
+         ptr: NonNull<u8>,
+         old_layout: Layout,
+         new_layout: Layout,
+     ) -> Result<NonNull<[u8]>, AllocError> {
+         // SAFETY: the safety contract must be upheld by the caller
+         unsafe { (**self).shrink(ptr, old_layout, new_layout) }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/any.rs gcc-16-20251102/libgrust/rustc-lib/core/src/any.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/any.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/any.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,517 ----
+ //! This module implements the `Any` trait, which enables dynamic typing
+ //! of any `'static` type through runtime reflection.
+ //!
+ //! `Any` itself can be used to get a `TypeId`, and has more features when used
+ //! as a trait object. As `&dyn Any` (a borrowed trait object), it has the `is`
+ //! and `downcast_ref` methods, to test if the contained value is of a given type,
+ //! and to get a reference to the inner value as a type. As `&mut dyn Any`, there
+ //! is also the `downcast_mut` method, for getting a mutable reference to the
+ //! inner value. `Box<dyn Any>` adds the `downcast` method, which attempts to
+ //! convert to a `Box<T>`. See the [`Box`] documentation for the full details.
+ //!
+ //! Note that `&dyn Any` is limited to testing whether a value is of a specified
+ //! concrete type, and cannot be used to test whether a type implements a trait.
+ //!
+ //! [`Box`]: ../../std/boxed/struct.Box.html
+ //!
+ //! # Examples
+ //!
+ //! Consider a situation where we want to log out a value passed to a function.
+ //! We know the value we're working on implements Debug, but we don't know its
+ //! concrete type. We want to give special treatment to certain types: in this
+ //! case printing out the length of String values prior to their value.
+ //! We don't know the concrete type of our value at compile time, so we need to
+ //! use runtime reflection instead.
+ //!
+ //! ```rust
+ //! use std::fmt::Debug;
+ //! use std::any::Any;
+ //!
+ //! // Logger function for any type that implements Debug.
+ //! fn log<T: Any + Debug>(value: &T) {
+ //!     let value_any = value as &dyn Any;
+ //!
+ //!     // Try to convert our value to a `String`. If successful, we want to
+ //!     // output the String`'s length as well as its value. If not, it's a
+ //!     // different type: just print it out unadorned.
+ //!     match value_any.downcast_ref::<String>() {
+ //!         Some(as_string) => {
+ //!             println!("String ({}): {}", as_string.len(), as_string);
+ //!         }
+ //!         None => {
+ //!             println!("{:?}", value);
+ //!         }
+ //!     }
+ //! }
+ //!
+ //! // This function wants to log its parameter out prior to doing work with it.
+ //! fn do_work<T: Any + Debug>(value: &T) {
+ //!     log(value);
+ //!     // ...do some other work
+ //! }
+ //!
+ //! fn main() {
+ //!     let my_string = "Hello World".to_string();
+ //!     do_work(&my_string);
+ //!
+ //!     let my_i8: i8 = 100;
+ //!     do_work(&my_i8);
+ //! }
+ //! ```
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::fmt;
+ use crate::intrinsics;
+ 
+ ///////////////////////////////////////////////////////////////////////////////
+ // Any trait
+ ///////////////////////////////////////////////////////////////////////////////
+ 
+ /// A trait to emulate dynamic typing.
+ ///
+ /// Most types implement `Any`. However, any type which contains a non-`'static` reference does not.
+ /// See the [module-level documentation][mod] for more details.
+ ///
+ /// [mod]: crate::any
+ // This trait is not unsafe, though we rely on the specifics of it's sole impl's
+ // `type_id` function in unsafe code (e.g., `downcast`). Normally, that would be
+ // a problem, but because the only impl of `Any` is a blanket implementation, no
+ // other code can implement `Any`.
+ //
+ // We could plausibly make this trait unsafe -- it would not cause breakage,
+ // since we control all the implementations -- but we choose not to as that's
+ // both not really necessary and may confuse users about the distinction of
+ // unsafe traits and unsafe methods (i.e., `type_id` would still be safe to call,
+ // but we would likely want to indicate as such in documentation).
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Any: 'static {
+     /// Gets the `TypeId` of `self`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::{Any, TypeId};
+     ///
+     /// fn is_string(s: &dyn Any) -> bool {
+     ///     TypeId::of::<String>() == s.type_id()
+     /// }
+     ///
+     /// assert_eq!(is_string(&0), false);
+     /// assert_eq!(is_string(&"cookie monster".to_string()), true);
+     /// ```
+     #[stable(feature = "get_type_id", since = "1.34.0")]
+     fn type_id(&self) -> TypeId;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: 'static + ?Sized> Any for T {
+     fn type_id(&self) -> TypeId {
+         TypeId::of::<T>()
+     }
+ }
+ 
+ ///////////////////////////////////////////////////////////////////////////////
+ // Extension methods for Any trait objects.
+ ///////////////////////////////////////////////////////////////////////////////
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Debug for dyn Any {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("Any")
+     }
+ }
+ 
+ // Ensure that the result of e.g., joining a thread can be printed and
+ // hence used with `unwrap`. May eventually no longer be needed if
+ // dispatch works with upcasting.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Debug for dyn Any + Send {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("Any")
+     }
+ }
+ 
+ #[stable(feature = "any_send_sync_methods", since = "1.28.0")]
+ impl fmt::Debug for dyn Any + Send + Sync {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("Any")
+     }
+ }
+ 
+ impl dyn Any {
+     /// Returns `true` if the boxed type is the same as `T`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn is_string(s: &dyn Any) {
+     ///     if s.is::<String>() {
+     ///         println!("It's a string!");
+     ///     } else {
+     ///         println!("Not a string...");
+     ///     }
+     /// }
+     ///
+     /// is_string(&0);
+     /// is_string(&"cookie monster".to_string());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is<T: Any>(&self) -> bool {
+         // Get `TypeId` of the type this function is instantiated with.
+         let t = TypeId::of::<T>();
+ 
+         // Get `TypeId` of the type in the trait object (`self`).
+         let concrete = self.type_id();
+ 
+         // Compare both `TypeId`s on equality.
+         t == concrete
+     }
+ 
+     /// Returns some reference to the boxed value if it is of type `T`, or
+     /// `None` if it isn't.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn print_if_string(s: &dyn Any) {
+     ///     if let Some(string) = s.downcast_ref::<String>() {
+     ///         println!("It's a string({}): '{}'", string.len(), string);
+     ///     } else {
+     ///         println!("Not a string...");
+     ///     }
+     /// }
+     ///
+     /// print_if_string(&0);
+     /// print_if_string(&"cookie monster".to_string());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn downcast_ref<T: Any>(&self) -> Option<&T> {
+         if self.is::<T>() {
+             // SAFETY: just checked whether we are pointing to the correct type, and we can rely on
+             // that check for memory safety because we have implemented Any for all types; no other
+             // impls can exist as they would conflict with our impl.
+             unsafe { Some(&*(self as *const dyn Any as *const T)) }
+         } else {
+             None
+         }
+     }
+ 
+     /// Returns some mutable reference to the boxed value if it is of type `T`, or
+     /// `None` if it isn't.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn modify_if_u32(s: &mut dyn Any) {
+     ///     if let Some(num) = s.downcast_mut::<u32>() {
+     ///         *num = 42;
+     ///     }
+     /// }
+     ///
+     /// let mut x = 10u32;
+     /// let mut s = "starlord".to_string();
+     ///
+     /// modify_if_u32(&mut x);
+     /// modify_if_u32(&mut s);
+     ///
+     /// assert_eq!(x, 42);
+     /// assert_eq!(&s, "starlord");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn downcast_mut<T: Any>(&mut self) -> Option<&mut T> {
+         if self.is::<T>() {
+             // SAFETY: just checked whether we are pointing to the correct type, and we can rely on
+             // that check for memory safety because we have implemented Any for all types; no other
+             // impls can exist as they would conflict with our impl.
+             unsafe { Some(&mut *(self as *mut dyn Any as *mut T)) }
+         } else {
+             None
+         }
+     }
+ }
+ 
+ impl dyn Any + Send {
+     /// Forwards to the method defined on the type `Any`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn is_string(s: &(dyn Any + Send)) {
+     ///     if s.is::<String>() {
+     ///         println!("It's a string!");
+     ///     } else {
+     ///         println!("Not a string...");
+     ///     }
+     /// }
+     ///
+     /// is_string(&0);
+     /// is_string(&"cookie monster".to_string());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is<T: Any>(&self) -> bool {
+         Any::is::<T>(self)
+     }
+ 
+     /// Forwards to the method defined on the type `Any`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn print_if_string(s: &(dyn Any + Send)) {
+     ///     if let Some(string) = s.downcast_ref::<String>() {
+     ///         println!("It's a string({}): '{}'", string.len(), string);
+     ///     } else {
+     ///         println!("Not a string...");
+     ///     }
+     /// }
+     ///
+     /// print_if_string(&0);
+     /// print_if_string(&"cookie monster".to_string());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn downcast_ref<T: Any>(&self) -> Option<&T> {
+         Any::downcast_ref::<T>(self)
+     }
+ 
+     /// Forwards to the method defined on the type `Any`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn modify_if_u32(s: &mut (dyn Any + Send)) {
+     ///     if let Some(num) = s.downcast_mut::<u32>() {
+     ///         *num = 42;
+     ///     }
+     /// }
+     ///
+     /// let mut x = 10u32;
+     /// let mut s = "starlord".to_string();
+     ///
+     /// modify_if_u32(&mut x);
+     /// modify_if_u32(&mut s);
+     ///
+     /// assert_eq!(x, 42);
+     /// assert_eq!(&s, "starlord");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn downcast_mut<T: Any>(&mut self) -> Option<&mut T> {
+         Any::downcast_mut::<T>(self)
+     }
+ }
+ 
+ impl dyn Any + Send + Sync {
+     /// Forwards to the method defined on the type `Any`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn is_string(s: &(dyn Any + Send + Sync)) {
+     ///     if s.is::<String>() {
+     ///         println!("It's a string!");
+     ///     } else {
+     ///         println!("Not a string...");
+     ///     }
+     /// }
+     ///
+     /// is_string(&0);
+     /// is_string(&"cookie monster".to_string());
+     /// ```
+     #[stable(feature = "any_send_sync_methods", since = "1.28.0")]
+     #[inline]
+     pub fn is<T: Any>(&self) -> bool {
+         Any::is::<T>(self)
+     }
+ 
+     /// Forwards to the method defined on the type `Any`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn print_if_string(s: &(dyn Any + Send + Sync)) {
+     ///     if let Some(string) = s.downcast_ref::<String>() {
+     ///         println!("It's a string({}): '{}'", string.len(), string);
+     ///     } else {
+     ///         println!("Not a string...");
+     ///     }
+     /// }
+     ///
+     /// print_if_string(&0);
+     /// print_if_string(&"cookie monster".to_string());
+     /// ```
+     #[stable(feature = "any_send_sync_methods", since = "1.28.0")]
+     #[inline]
+     pub fn downcast_ref<T: Any>(&self) -> Option<&T> {
+         Any::downcast_ref::<T>(self)
+     }
+ 
+     /// Forwards to the method defined on the type `Any`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::Any;
+     ///
+     /// fn modify_if_u32(s: &mut (dyn Any + Send + Sync)) {
+     ///     if let Some(num) = s.downcast_mut::<u32>() {
+     ///         *num = 42;
+     ///     }
+     /// }
+     ///
+     /// let mut x = 10u32;
+     /// let mut s = "starlord".to_string();
+     ///
+     /// modify_if_u32(&mut x);
+     /// modify_if_u32(&mut s);
+     ///
+     /// assert_eq!(x, 42);
+     /// assert_eq!(&s, "starlord");
+     /// ```
+     #[stable(feature = "any_send_sync_methods", since = "1.28.0")]
+     #[inline]
+     pub fn downcast_mut<T: Any>(&mut self) -> Option<&mut T> {
+         Any::downcast_mut::<T>(self)
+     }
+ }
+ 
+ ///////////////////////////////////////////////////////////////////////////////
+ // TypeID and its methods
+ ///////////////////////////////////////////////////////////////////////////////
+ 
+ /// A `TypeId` represents a globally unique identifier for a type.
+ ///
+ /// Each `TypeId` is an opaque object which does not allow inspection of what's
+ /// inside but does allow basic operations such as cloning, comparison,
+ /// printing, and showing.
+ ///
+ /// A `TypeId` is currently only available for types which ascribe to `'static`,
+ /// but this limitation may be removed in the future.
+ ///
+ /// While `TypeId` implements `Hash`, `PartialOrd`, and `Ord`, it is worth
+ /// noting that the hashes and ordering will vary between Rust releases. Beware
+ /// of relying on them inside of your code!
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct TypeId {
+     t: u64,
+ }
+ 
+ impl TypeId {
+     /// Returns the `TypeId` of the type this generic function has been
+     /// instantiated with.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::any::{Any, TypeId};
+     ///
+     /// fn is_string<T: ?Sized + Any>(_s: &T) -> bool {
+     ///     TypeId::of::<String>() == TypeId::of::<T>()
+     /// }
+     ///
+     /// assert_eq!(is_string(&0), false);
+     /// assert_eq!(is_string(&"cookie monster".to_string()), true);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_type_id", issue = "77125")]
+     pub const fn of<T: ?Sized + 'static>() -> TypeId {
+         TypeId { t: intrinsics::type_id::<T>() }
+     }
+ }
+ 
+ /// Returns the name of a type as a string slice.
+ ///
+ /// # Note
+ ///
+ /// This is intended for diagnostic use. The exact contents and format of the
+ /// string returned are not specified, other than being a best-effort
+ /// description of the type. For example, amongst the strings
+ /// that `type_name::<Option<String>>()` might return are `"Option<String>"` and
+ /// `"std::option::Option<std::string::String>"`.
+ ///
+ /// The returned string must not be considered to be a unique identifier of a
+ /// type as multiple types may map to the same type name. Similarly, there is no
+ /// guarantee that all parts of a type will appear in the returned string: for
+ /// example, lifetime specifiers are currently not included. In addition, the
+ /// output may change between versions of the compiler.
+ ///
+ /// The current implementation uses the same infrastructure as compiler
+ /// diagnostics and debuginfo, but this is not guaranteed.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// assert_eq!(
+ ///     std::any::type_name::<Option<String>>(),
+ ///     "core::option::Option<alloc::string::String>",
+ /// );
+ /// ```
+ #[stable(feature = "type_name", since = "1.38.0")]
+ #[rustc_const_unstable(feature = "const_type_name", issue = "63084")]
+ pub const fn type_name<T: ?Sized>() -> &'static str {
+     intrinsics::type_name::<T>()
+ }
+ 
+ /// Returns the name of the type of the pointed-to value as a string slice.
+ /// This is the same as `type_name::<T>()`, but can be used where the type of a
+ /// variable is not easily available.
+ ///
+ /// # Note
+ ///
+ /// This is intended for diagnostic use. The exact contents and format of the
+ /// string are not specified, other than being a best-effort description of the
+ /// type. For example, `type_name_of_val::<Option<String>>(None)` could return
+ /// `"Option<String>"` or `"std::option::Option<std::string::String>"`, but not
+ /// `"foobar"`. In addition, the output may change between versions of the
+ /// compiler.
+ ///
+ /// This function does not resolve trait objects,
+ /// meaning that `type_name_of_val(&7u32 as &dyn Debug)`
+ /// may return `"dyn Debug"`, but not `"u32"`.
+ ///
+ /// The type name should not be considered a unique identifier of a type;
+ /// multiple types may share the same type name.
+ ///
+ /// The current implementation uses the same infrastructure as compiler
+ /// diagnostics and debuginfo, but this is not guaranteed.
+ ///
+ /// # Examples
+ ///
+ /// Prints the default integer and float types.
+ ///
+ /// ```rust
+ /// #![feature(type_name_of_val)]
+ /// use std::any::type_name_of_val;
+ ///
+ /// let x = 1;
+ /// println!("{}", type_name_of_val(&x));
+ /// let y = 1.0;
+ /// println!("{}", type_name_of_val(&y));
+ /// ```
+ #[unstable(feature = "type_name_of_val", issue = "66359")]
+ #[rustc_const_unstable(feature = "const_type_name", issue = "63084")]
+ pub const fn type_name_of_val<T: ?Sized>(_val: &T) -> &'static str {
+     type_name::<T>()
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/array/iter.rs gcc-16-20251102/libgrust/rustc-lib/core/src/array/iter.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/array/iter.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/array/iter.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,202 ----
+ //! Defines the `IntoIter` owned iterator for arrays.
+ 
+ use crate::{
+     fmt,
+     iter::{ExactSizeIterator, FusedIterator, TrustedLen},
+     mem::{self, MaybeUninit},
+     ops::Range,
+     ptr,
+ };
+ 
+ /// A by-value [array] iterator.
+ ///
+ /// [array]: ../../std/primitive.array.html
+ #[unstable(feature = "array_value_iter", issue = "65798")]
+ pub struct IntoIter<T, const N: usize> {
+     /// This is the array we are iterating over.
+     ///
+     /// Elements with index `i` where `alive.start <= i < alive.end` have not
+     /// been yielded yet and are valid array entries. Elements with indices `i
+     /// < alive.start` or `i >= alive.end` have been yielded already and must
+     /// not be accessed anymore! Those dead elements might even be in a
+     /// completely uninitialized state!
+     ///
+     /// So the invariants are:
+     /// - `data[alive]` is alive (i.e. contains valid elements)
+     /// - `data[..alive.start]` and `data[alive.end..]` are dead (i.e. the
+     ///   elements were already read and must not be touched anymore!)
+     data: [MaybeUninit<T>; N],
+ 
+     /// The elements in `data` that have not been yielded yet.
+     ///
+     /// Invariants:
+     /// - `alive.start <= alive.end`
+     /// - `alive.end <= N`
+     alive: Range<usize>,
+ }
+ 
+ impl<T, const N: usize> IntoIter<T, N> {
+     /// Creates a new iterator over the given `array`.
+     ///
+     /// *Note*: this method might never get stabilized and/or removed in the
+     /// future as there will likely be another, preferred way of obtaining this
+     /// iterator (either via `IntoIterator` for arrays or via another way).
+     #[unstable(feature = "array_value_iter", issue = "65798")]
+     pub fn new(array: [T; N]) -> Self {
+         // SAFETY: The transmute here is actually safe. The docs of `MaybeUninit`
+         // promise:
+         //
+         // > `MaybeUninit<T>` is guaranteed to have the same size and alignment
+         // > as `T`.
+         //
+         // The docs even show a transmute from an array of `MaybeUninit<T>` to
+         // an array of `T`.
+         //
+         // With that, this initialization satisfies the invariants.
+ 
+         // FIXME(LukasKalbertodt): actually use `mem::transmute` here, once it
+         // works with const generics:
+         //     `mem::transmute::<[T; N], [MaybeUninit<T>; N]>(array)`
+         //
+         // Until then, we can use `mem::transmute_copy` to create a bitwise copy
+         // as a different type, then forget `array` so that it is not dropped.
+         unsafe {
+             let iter = Self { data: mem::transmute_copy(&array), alive: 0..N };
+             mem::forget(array);
+             iter
+         }
+     }
+ 
+     /// Returns an immutable slice of all elements that have not been yielded
+     /// yet.
+     fn as_slice(&self) -> &[T] {
+         // SAFETY: We know that all elements within `alive` are properly initialized.
+         unsafe {
+             let slice = self.data.get_unchecked(self.alive.clone());
+             MaybeUninit::slice_assume_init_ref(slice)
+         }
+     }
+ 
+     /// Returns a mutable slice of all elements that have not been yielded yet.
+     fn as_mut_slice(&mut self) -> &mut [T] {
+         // SAFETY: We know that all elements within `alive` are properly initialized.
+         unsafe {
+             let slice = self.data.get_unchecked_mut(self.alive.clone());
+             MaybeUninit::slice_assume_init_mut(slice)
+         }
+     }
+ }
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T, const N: usize> Iterator for IntoIter<T, N> {
+     type Item = T;
+     fn next(&mut self) -> Option<Self::Item> {
+         // Get the next index from the front.
+         //
+         // Increasing `alive.start` by 1 maintains the invariant regarding
+         // `alive`. However, due to this change, for a short time, the alive
+         // zone is not `data[alive]` anymore, but `data[idx..alive.end]`.
+         self.alive.next().map(|idx| {
+             // Read the element from the array.
+             // SAFETY: `idx` is an index into the former "alive" region of the
+             // array. Reading this element means that `data[idx]` is regarded as
+             // dead now (i.e. do not touch). As `idx` was the start of the
+             // alive-zone, the alive zone is now `data[alive]` again, restoring
+             // all invariants.
+             unsafe { self.data.get_unchecked(idx).assume_init_read() }
+         })
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let len = self.len();
+         (len, Some(len))
+     }
+ 
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     fn last(mut self) -> Option<Self::Item> {
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T, const N: usize> DoubleEndedIterator for IntoIter<T, N> {
+     fn next_back(&mut self) -> Option<Self::Item> {
+         // Get the next index from the back.
+         //
+         // Decreasing `alive.end` by 1 maintains the invariant regarding
+         // `alive`. However, due to this change, for a short time, the alive
+         // zone is not `data[alive]` anymore, but `data[alive.start..=idx]`.
+         self.alive.next_back().map(|idx| {
+             // Read the element from the array.
+             // SAFETY: `idx` is an index into the former "alive" region of the
+             // array. Reading this element means that `data[idx]` is regarded as
+             // dead now (i.e. do not touch). As `idx` was the end of the
+             // alive-zone, the alive zone is now `data[alive]` again, restoring
+             // all invariants.
+             unsafe { self.data.get_unchecked(idx).assume_init_read() }
+         })
+     }
+ }
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T, const N: usize> Drop for IntoIter<T, N> {
+     fn drop(&mut self) {
+         // SAFETY: This is safe: `as_mut_slice` returns exactly the sub-slice
+         // of elements that have not been moved out yet and that remain
+         // to be dropped.
+         unsafe { ptr::drop_in_place(self.as_mut_slice()) }
+     }
+ }
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T, const N: usize> ExactSizeIterator for IntoIter<T, N> {
+     fn len(&self) -> usize {
+         // Will never underflow due to the invariant `alive.start <=
+         // alive.end`.
+         self.alive.end - self.alive.start
+     }
+     fn is_empty(&self) -> bool {
+         self.alive.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T, const N: usize> FusedIterator for IntoIter<T, N> {}
+ 
+ // The iterator indeed reports the correct length. The number of "alive"
+ // elements (that will still be yielded) is the length of the range `alive`.
+ // This range is decremented in length in either `next` or `next_back`. It is
+ // always decremented by 1 in those methods, but only if `Some(_)` is returned.
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ unsafe impl<T, const N: usize> TrustedLen for IntoIter<T, N> {}
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T: Clone, const N: usize> Clone for IntoIter<T, N> {
+     fn clone(&self) -> Self {
+         // Note, we don't really need to match the exact same alive range, so
+         // we can just clone into offset 0 regardless of where `self` is.
+         let mut new = Self { data: MaybeUninit::uninit_array(), alive: 0..0 };
+ 
+         // Clone all alive elements.
+         for (src, dst) in self.as_slice().iter().zip(&mut new.data) {
+             // Write a clone into the new array, then update its alive range.
+             // If cloning panics, we'll correctly drop the previous items.
+             dst.write(src.clone());
+             new.alive.end += 1;
+         }
+ 
+         new
+     }
+ }
+ 
+ #[stable(feature = "array_value_iter_impls", since = "1.40.0")]
+ impl<T: fmt::Debug, const N: usize> fmt::Debug for IntoIter<T, N> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         // Only print the elements that were not yielded yet: we cannot
+         // access the yielded elements anymore.
+         f.debug_tuple("IntoIter").field(&self.as_slice()).finish()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/array/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/array/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/array/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/array/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,453 ----
+ //! Implementations of things like `Eq` for fixed-length arrays
+ //! up to a certain length. Eventually, we should be able to generalize
+ //! to all lengths.
+ //!
+ //! *[See also the array primitive type](../../std/primitive.array.html).*
+ 
+ #![stable(feature = "core_array", since = "1.36.0")]
+ 
+ use crate::borrow::{Borrow, BorrowMut};
+ use crate::cmp::Ordering;
+ use crate::convert::{Infallible, TryFrom};
+ use crate::fmt;
+ use crate::hash::{self, Hash};
+ use crate::marker::Unsize;
+ use crate::slice::{Iter, IterMut};
+ 
+ mod iter;
+ 
+ #[unstable(feature = "array_value_iter", issue = "65798")]
+ pub use iter::IntoIter;
+ 
+ /// Converts a reference to `T` into a reference to an array of length 1 (without copying).
+ #[unstable(feature = "array_from_ref", issue = "77101")]
+ pub fn from_ref<T>(s: &T) -> &[T; 1] {
+     // SAFETY: Converting `&T` to `&[T; 1]` is sound.
+     unsafe { &*(s as *const T).cast::<[T; 1]>() }
+ }
+ 
+ /// Converts a mutable reference to `T` into a mutable reference to an array of length 1 (without copying).
+ #[unstable(feature = "array_from_ref", issue = "77101")]
+ pub fn from_mut<T>(s: &mut T) -> &mut [T; 1] {
+     // SAFETY: Converting `&mut T` to `&mut [T; 1]` is sound.
+     unsafe { &mut *(s as *mut T).cast::<[T; 1]>() }
+ }
+ 
+ /// Utility trait implemented only on arrays of fixed size
+ ///
+ /// This trait can be used to implement other traits on fixed-size arrays
+ /// without causing much metadata bloat.
+ ///
+ /// The trait is marked unsafe in order to restrict implementors to fixed-size
+ /// arrays. User of this trait can assume that implementors have the exact
+ /// layout in memory of a fixed size array (for example, for unsafe
+ /// initialization).
+ ///
+ /// Note that the traits [`AsRef`] and [`AsMut`] provide similar methods for types that
+ /// may not be fixed-size arrays. Implementors should prefer those traits
+ /// instead.
+ #[unstable(feature = "fixed_size_array", issue = "27778")]
+ pub unsafe trait FixedSizeArray<T> {
+     /// Converts the array to immutable slice
+     #[unstable(feature = "fixed_size_array", issue = "27778")]
+     fn as_slice(&self) -> &[T];
+     /// Converts the array to mutable slice
+     #[unstable(feature = "fixed_size_array", issue = "27778")]
+     fn as_mut_slice(&mut self) -> &mut [T];
+ }
+ 
+ #[unstable(feature = "fixed_size_array", issue = "27778")]
+ unsafe impl<T, A: Unsize<[T]>> FixedSizeArray<T> for A {
+     #[inline]
+     fn as_slice(&self) -> &[T] {
+         self
+     }
+     #[inline]
+     fn as_mut_slice(&mut self) -> &mut [T] {
+         self
+     }
+ }
+ 
+ /// The error type returned when a conversion from a slice to an array fails.
+ #[stable(feature = "try_from", since = "1.34.0")]
+ #[derive(Debug, Copy, Clone)]
+ pub struct TryFromSliceError(());
+ 
+ #[stable(feature = "core_array", since = "1.36.0")]
+ impl fmt::Display for TryFromSliceError {
+     #[inline]
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Display::fmt(self.__description(), f)
+     }
+ }
+ 
+ impl TryFromSliceError {
+     #[unstable(
+         feature = "array_error_internals",
+         reason = "available through Error trait and this method should not \
+                      be exposed publicly",
+         issue = "none"
+     )]
+     #[inline]
+     #[doc(hidden)]
+     pub fn __description(&self) -> &str {
+         "could not convert slice to array"
+     }
+ }
+ 
+ #[stable(feature = "try_from_slice_error", since = "1.36.0")]
+ impl From<Infallible> for TryFromSliceError {
+     fn from(x: Infallible) -> TryFromSliceError {
+         match x {}
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, const N: usize> AsRef<[T]> for [T; N] {
+     #[inline]
+     fn as_ref(&self) -> &[T] {
+         &self[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, const N: usize> AsMut<[T]> for [T; N] {
+     #[inline]
+     fn as_mut(&mut self) -> &mut [T] {
+         &mut self[..]
+     }
+ }
+ 
+ #[stable(feature = "array_borrow", since = "1.4.0")]
+ impl<T, const N: usize> Borrow<[T]> for [T; N] {
+     fn borrow(&self) -> &[T] {
+         self
+     }
+ }
+ 
+ #[stable(feature = "array_borrow", since = "1.4.0")]
+ impl<T, const N: usize> BorrowMut<[T]> for [T; N] {
+     fn borrow_mut(&mut self) -> &mut [T] {
+         self
+     }
+ }
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl<T, const N: usize> TryFrom<&[T]> for [T; N]
+ where
+     T: Copy,
+ {
+     type Error = TryFromSliceError;
+ 
+     fn try_from(slice: &[T]) -> Result<[T; N], TryFromSliceError> {
+         <&Self>::try_from(slice).map(|r| *r)
+     }
+ }
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl<'a, T, const N: usize> TryFrom<&'a [T]> for &'a [T; N] {
+     type Error = TryFromSliceError;
+ 
+     fn try_from(slice: &[T]) -> Result<&[T; N], TryFromSliceError> {
+         if slice.len() == N {
+             let ptr = slice.as_ptr() as *const [T; N];
+             // SAFETY: ok because we just checked that the length fits
+             unsafe { Ok(&*ptr) }
+         } else {
+             Err(TryFromSliceError(()))
+         }
+     }
+ }
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl<'a, T, const N: usize> TryFrom<&'a mut [T]> for &'a mut [T; N] {
+     type Error = TryFromSliceError;
+ 
+     fn try_from(slice: &mut [T]) -> Result<&mut [T; N], TryFromSliceError> {
+         if slice.len() == N {
+             let ptr = slice.as_mut_ptr() as *mut [T; N];
+             // SAFETY: ok because we just checked that the length fits
+             unsafe { Ok(&mut *ptr) }
+         } else {
+             Err(TryFromSliceError(()))
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Hash, const N: usize> Hash for [T; N] {
+     fn hash<H: hash::Hasher>(&self, state: &mut H) {
+         Hash::hash(&self[..], state)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: fmt::Debug, const N: usize> fmt::Debug for [T; N] {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Debug::fmt(&&self[..], f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T, const N: usize> IntoIterator for &'a [T; N] {
+     type Item = &'a T;
+     type IntoIter = Iter<'a, T>;
+ 
+     fn into_iter(self) -> Iter<'a, T> {
+         self.iter()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T, const N: usize> IntoIterator for &'a mut [T; N] {
+     type Item = &'a mut T;
+     type IntoIter = IterMut<'a, T>;
+ 
+     fn into_iter(self) -> IterMut<'a, T> {
+         self.iter_mut()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B, const N: usize> PartialEq<[B; N]> for [A; N]
+ where
+     A: PartialEq<B>,
+ {
+     #[inline]
+     fn eq(&self, other: &[B; N]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &[B; N]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B, const N: usize> PartialEq<[B]> for [A; N]
+ where
+     A: PartialEq<B>,
+ {
+     #[inline]
+     fn eq(&self, other: &[B]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &[B]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B, const N: usize> PartialEq<[A; N]> for [B]
+ where
+     B: PartialEq<A>,
+ {
+     #[inline]
+     fn eq(&self, other: &[A; N]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &[A; N]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'b, A, B, const N: usize> PartialEq<&'b [B]> for [A; N]
+ where
+     A: PartialEq<B>,
+ {
+     #[inline]
+     fn eq(&self, other: &&'b [B]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &&'b [B]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'b, A, B, const N: usize> PartialEq<[A; N]> for &'b [B]
+ where
+     B: PartialEq<A>,
+ {
+     #[inline]
+     fn eq(&self, other: &[A; N]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &[A; N]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'b, A, B, const N: usize> PartialEq<&'b mut [B]> for [A; N]
+ where
+     A: PartialEq<B>,
+ {
+     #[inline]
+     fn eq(&self, other: &&'b mut [B]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &&'b mut [B]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'b, A, B, const N: usize> PartialEq<[A; N]> for &'b mut [B]
+ where
+     B: PartialEq<A>,
+ {
+     #[inline]
+     fn eq(&self, other: &[A; N]) -> bool {
+         self[..] == other[..]
+     }
+     #[inline]
+     fn ne(&self, other: &[A; N]) -> bool {
+         self[..] != other[..]
+     }
+ }
+ 
+ // NOTE: some less important impls are omitted to reduce code bloat
+ // __impl_slice_eq2! { [A; $N], &'b [B; $N] }
+ // __impl_slice_eq2! { [A; $N], &'b mut [B; $N] }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Eq, const N: usize> Eq for [T; N] {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: PartialOrd, const N: usize> PartialOrd for [T; N] {
+     #[inline]
+     fn partial_cmp(&self, other: &[T; N]) -> Option<Ordering> {
+         PartialOrd::partial_cmp(&&self[..], &&other[..])
+     }
+     #[inline]
+     fn lt(&self, other: &[T; N]) -> bool {
+         PartialOrd::lt(&&self[..], &&other[..])
+     }
+     #[inline]
+     fn le(&self, other: &[T; N]) -> bool {
+         PartialOrd::le(&&self[..], &&other[..])
+     }
+     #[inline]
+     fn ge(&self, other: &[T; N]) -> bool {
+         PartialOrd::ge(&&self[..], &&other[..])
+     }
+     #[inline]
+     fn gt(&self, other: &[T; N]) -> bool {
+         PartialOrd::gt(&&self[..], &&other[..])
+     }
+ }
+ 
+ /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison).
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Ord, const N: usize> Ord for [T; N] {
+     #[inline]
+     fn cmp(&self, other: &[T; N]) -> Ordering {
+         Ord::cmp(&&self[..], &&other[..])
+     }
+ }
+ 
+ // The Default impls cannot be done with const generics because `[T; 0]` doesn't
+ // require Default to be implemented, and having different impl blocks for
+ // different numbers isn't supported yet.
+ 
+ macro_rules! array_impl_default {
+     {$n:expr, $t:ident $($ts:ident)*} => {
+         #[stable(since = "1.4.0", feature = "array_default")]
+         impl<T> Default for [T; $n] where T: Default {
+             fn default() -> [T; $n] {
+                 [$t::default(), $($ts::default()),*]
+             }
+         }
+         array_impl_default!{($n - 1), $($ts)*}
+     };
+     {$n:expr,} => {
+         #[stable(since = "1.4.0", feature = "array_default")]
+         impl<T> Default for [T; $n] {
+             fn default() -> [T; $n] { [] }
+         }
+     };
+ }
+ 
+ array_impl_default! {32, T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T}
+ 
+ #[lang = "array"]
+ impl<T, const N: usize> [T; N] {
+     /// Returns an array of the same size as `self`, with function `f` applied to each element
+     /// in order.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(array_map)]
+     /// let x = [1, 2, 3];
+     /// let y = x.map(|v| v + 1);
+     /// assert_eq!(y, [2, 3, 4]);
+     ///
+     /// let x = [1, 2, 3];
+     /// let mut temp = 0;
+     /// let y = x.map(|v| { temp += 1; v * temp });
+     /// assert_eq!(y, [1, 4, 9]);
+     ///
+     /// let x = ["Ferris", "Bueller's", "Day", "Off"];
+     /// let y = x.map(|v| v.len());
+     /// assert_eq!(y, [6, 9, 3, 3]);
+     /// ```
+     #[unstable(feature = "array_map", issue = "75243")]
+     pub fn map<F, U>(self, mut f: F) -> [U; N]
+     where
+         F: FnMut(T) -> U,
+     {
+         use crate::mem::MaybeUninit;
+         struct Guard<T, const N: usize> {
+             dst: *mut T,
+             initialized: usize,
+         }
+ 
+         impl<T, const N: usize> Drop for Guard<T, N> {
+             fn drop(&mut self) {
+                 debug_assert!(self.initialized <= N);
+ 
+                 let initialized_part =
+                     crate::ptr::slice_from_raw_parts_mut(self.dst, self.initialized);
+                 // SAFETY: this raw slice will contain only initialized objects
+                 // that's why, it is allowed to drop it.
+                 unsafe {
+                     crate::ptr::drop_in_place(initialized_part);
+                 }
+             }
+         }
+         let mut dst = MaybeUninit::uninit_array::<N>();
+         let mut guard: Guard<U, N> =
+             Guard { dst: MaybeUninit::slice_as_mut_ptr(&mut dst), initialized: 0 };
+         for (src, dst) in IntoIter::new(self).zip(&mut dst) {
+             dst.write(f(src));
+             guard.initialized += 1;
+         }
+         // FIXME: Convert to crate::mem::transmute once it works with generics.
+         // unsafe { crate::mem::transmute::<[MaybeUninit<U>; N], [U; N]>(dst) }
+         crate::mem::forget(guard);
+         // SAFETY: At this point we've properly initialized the whole array
+         // and we just need to cast it to the correct type.
+         unsafe { crate::mem::transmute_copy::<_, [U; N]>(&dst) }
+     }
+ 
+     /// Returns a slice containing the entire array. Equivalent to `&s[..]`.
+     #[unstable(feature = "array_methods", issue = "76118")]
+     pub fn as_slice(&self) -> &[T] {
+         self
+     }
+ 
+     /// Returns a mutable slice containing the entire array. Equivalent to
+     /// `&mut s[..]`.
+     #[unstable(feature = "array_methods", issue = "76118")]
+     pub fn as_mut_slice(&mut self) -> &mut [T] {
+         self
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ascii.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ascii.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ascii.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ascii.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,150 ----
+ //! Operations on ASCII strings and characters.
+ //!
+ //! Most string operations in Rust act on UTF-8 strings. However, at times it
+ //! makes more sense to only consider the ASCII character set for a specific
+ //! operation.
+ //!
+ //! The [`escape_default`] function provides an iterator over the bytes of an
+ //! escaped version of the character given.
+ 
+ #![stable(feature = "core_ascii", since = "1.26.0")]
+ 
+ use crate::fmt;
+ use crate::iter::FusedIterator;
+ use crate::ops::Range;
+ use crate::str::from_utf8_unchecked;
+ 
+ /// An iterator over the escaped version of a byte.
+ ///
+ /// This `struct` is created by the [`escape_default`] function. See its
+ /// documentation for more.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct EscapeDefault {
+     range: Range<usize>,
+     data: [u8; 4],
+ }
+ 
+ /// Returns an iterator that produces an escaped version of a `u8`.
+ ///
+ /// The default is chosen with a bias toward producing literals that are
+ /// legal in a variety of languages, including C++11 and similar C-family
+ /// languages. The exact rules are:
+ ///
+ /// * Tab is escaped as `\t`.
+ /// * Carriage return is escaped as `\r`.
+ /// * Line feed is escaped as `\n`.
+ /// * Single quote is escaped as `\'`.
+ /// * Double quote is escaped as `\"`.
+ /// * Backslash is escaped as `\\`.
+ /// * Any character in the 'printable ASCII' range `0x20` .. `0x7e`
+ ///   inclusive is not escaped.
+ /// * Any other chars are given hex escapes of the form '\xNN'.
+ /// * Unicode escapes are never generated by this function.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ascii;
+ ///
+ /// let escaped = ascii::escape_default(b'0').next().unwrap();
+ /// assert_eq!(b'0', escaped);
+ ///
+ /// let mut escaped = ascii::escape_default(b'\t');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b't', escaped.next().unwrap());
+ ///
+ /// let mut escaped = ascii::escape_default(b'\r');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b'r', escaped.next().unwrap());
+ ///
+ /// let mut escaped = ascii::escape_default(b'\n');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b'n', escaped.next().unwrap());
+ ///
+ /// let mut escaped = ascii::escape_default(b'\'');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b'\'', escaped.next().unwrap());
+ ///
+ /// let mut escaped = ascii::escape_default(b'"');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b'"', escaped.next().unwrap());
+ ///
+ /// let mut escaped = ascii::escape_default(b'\\');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ ///
+ /// let mut escaped = ascii::escape_default(b'\x9d');
+ ///
+ /// assert_eq!(b'\\', escaped.next().unwrap());
+ /// assert_eq!(b'x', escaped.next().unwrap());
+ /// assert_eq!(b'9', escaped.next().unwrap());
+ /// assert_eq!(b'd', escaped.next().unwrap());
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn escape_default(c: u8) -> EscapeDefault {
+     let (data, len) = match c {
+         b'\t' => ([b'\\', b't', 0, 0], 2),
+         b'\r' => ([b'\\', b'r', 0, 0], 2),
+         b'\n' => ([b'\\', b'n', 0, 0], 2),
+         b'\\' => ([b'\\', b'\\', 0, 0], 2),
+         b'\'' => ([b'\\', b'\'', 0, 0], 2),
+         b'"' => ([b'\\', b'"', 0, 0], 2),
+         b'\x20'..=b'\x7e' => ([c, 0, 0, 0], 1),
+         _ => ([b'\\', b'x', hexify(c >> 4), hexify(c & 0xf)], 4),
+     };
+ 
+     return EscapeDefault { range: 0..len, data };
+ 
+     fn hexify(b: u8) -> u8 {
+         match b {
+             0..=9 => b'0' + b,
+             _ => b'a' + b - 10,
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Iterator for EscapeDefault {
+     type Item = u8;
+     fn next(&mut self) -> Option<u8> {
+         self.range.next().map(|i| self.data[i])
+     }
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.range.size_hint()
+     }
+     fn last(mut self) -> Option<u8> {
+         self.next_back()
+     }
+ }
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl DoubleEndedIterator for EscapeDefault {
+     fn next_back(&mut self) -> Option<u8> {
+         self.range.next_back().map(|i| self.data[i])
+     }
+ }
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl ExactSizeIterator for EscapeDefault {}
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for EscapeDefault {}
+ 
+ #[stable(feature = "ascii_escape_display", since = "1.39.0")]
+ impl fmt::Display for EscapeDefault {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         // SAFETY: ok because `escape_default` created only valid utf-8 data
+         f.write_str(unsafe { from_utf8_unchecked(&self.data[self.range.clone()]) })
+     }
+ }
+ 
+ #[stable(feature = "std_debug", since = "1.16.0")]
+ impl fmt::Debug for EscapeDefault {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("EscapeDefault { .. }")
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/bool.rs gcc-16-20251102/libgrust/rustc-lib/core/src/bool.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/bool.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/bool.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,36 ----
+ //! impl bool {}
+ 
+ #[lang = "bool"]
+ impl bool {
+     /// Returns `Some(t)` if the `bool` is `true`, or `None` otherwise.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(bool_to_option)]
+     ///
+     /// assert_eq!(false.then_some(0), None);
+     /// assert_eq!(true.then_some(0), Some(0));
+     /// ```
+     #[unstable(feature = "bool_to_option", issue = "64260")]
+     #[inline]
+     pub fn then_some<T>(self, t: T) -> Option<T> {
+         if self { Some(t) } else { None }
+     }
+ 
+     /// Returns `Some(f())` if the `bool` is `true`, or `None` otherwise.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(bool_to_option)]
+     ///
+     /// assert_eq!(false.then(|| 0), None);
+     /// assert_eq!(true.then(|| 0), Some(0));
+     /// ```
+     #[unstable(feature = "bool_to_option", issue = "64260")]
+     #[inline]
+     pub fn then<T, F: FnOnce() -> T>(self, f: F) -> Option<T> {
+         if self { Some(f()) } else { None }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/borrow.rs gcc-16-20251102/libgrust/rustc-lib/core/src/borrow.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/borrow.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/borrow.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,242 ----
+ //! A module for working with borrowed data.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ /// A trait for borrowing data.
+ ///
+ /// In Rust, it is common to provide different representations of a type for
+ /// different use cases. For instance, storage location and management for a
+ /// value can be specifically chosen as appropriate for a particular use via
+ /// pointer types such as [`Box<T>`] or [`Rc<T>`]. Beyond these generic
+ /// wrappers that can be used with any type, some types provide optional
+ /// facets providing potentially costly functionality. An example for such a
+ /// type is [`String`] which adds the ability to extend a string to the basic
+ /// [`str`]. This requires keeping additional information unnecessary for a
+ /// simple, immutable string.
+ ///
+ /// These types provide access to the underlying data through references
+ /// to the type of that data. They are said to be ‘borrowed as’ that type.
+ /// For instance, a [`Box<T>`] can be borrowed as `T` while a [`String`]
+ /// can be borrowed as `str`.
+ ///
+ /// Types express that they can be borrowed as some type `T` by implementing
+ /// `Borrow<T>`, providing a reference to a `T` in the trait’s
+ /// [`borrow`] method. A type is free to borrow as several different types.
+ /// If it wishes to mutably borrow as the type – allowing the underlying data
+ /// to be modified, it can additionally implement [`BorrowMut<T>`].
+ ///
+ /// Further, when providing implementations for additional traits, it needs
+ /// to be considered whether they should behave identical to those of the
+ /// underlying type as a consequence of acting as a representation of that
+ /// underlying type. Generic code typically uses `Borrow<T>` when it relies
+ /// on the identical behavior of these additional trait implementations.
+ /// These traits will likely appear as additional trait bounds.
+ ///
+ /// In particular `Eq`, `Ord` and `Hash` must be equivalent for
+ /// borrowed and owned values: `x.borrow() == y.borrow()` should give the
+ /// same result as `x == y`.
+ ///
+ /// If generic code merely needs to work for all types that can
+ /// provide a reference to related type `T`, it is often better to use
+ /// [`AsRef<T>`] as more types can safely implement it.
+ ///
+ /// [`BorrowMut<T>`]: BorrowMut
+ /// [`Box<T>`]: ../../std/boxed/struct.Box.html
+ /// [`Mutex<T>`]: ../../std/sync/struct.Mutex.html
+ /// [`Rc<T>`]: ../../std/rc/struct.Rc.html
+ /// [`String`]: ../../std/string/struct.String.html
+ /// [`borrow`]: Borrow::borrow
+ ///
+ /// # Examples
+ ///
+ /// As a data collection, [`HashMap<K, V>`] owns both keys and values. If
+ /// the key’s actual data is wrapped in a managing type of some kind, it
+ /// should, however, still be possible to search for a value using a
+ /// reference to the key’s data. For instance, if the key is a string, then
+ /// it is likely stored with the hash map as a [`String`], while it should
+ /// be possible to search using a [`&str`][`str`]. Thus, `insert` needs to
+ /// operate on a `String` while `get` needs to be able to use a `&str`.
+ ///
+ /// Slightly simplified, the relevant parts of `HashMap<K, V>` look like
+ /// this:
+ ///
+ /// ```
+ /// use std::borrow::Borrow;
+ /// use std::hash::Hash;
+ ///
+ /// pub struct HashMap<K, V> {
+ ///     # marker: ::std::marker::PhantomData<(K, V)>,
+ ///     // fields omitted
+ /// }
+ ///
+ /// impl<K, V> HashMap<K, V> {
+ ///     pub fn insert(&self, key: K, value: V) -> Option<V>
+ ///     where K: Hash + Eq
+ ///     {
+ ///         # unimplemented!()
+ ///         // ...
+ ///     }
+ ///
+ ///     pub fn get<Q>(&self, k: &Q) -> Option<&V>
+ ///     where
+ ///         K: Borrow<Q>,
+ ///         Q: Hash + Eq + ?Sized
+ ///     {
+ ///         # unimplemented!()
+ ///         // ...
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// The entire hash map is generic over a key type `K`. Because these keys
+ /// are stored with the hash map, this type has to own the key’s data.
+ /// When inserting a key-value pair, the map is given such a `K` and needs
+ /// to find the correct hash bucket and check if the key is already present
+ /// based on that `K`. It therefore requires `K: Hash + Eq`.
+ ///
+ /// When searching for a value in the map, however, having to provide a
+ /// reference to a `K` as the key to search for would require to always
+ /// create such an owned value. For string keys, this would mean a `String`
+ /// value needs to be created just for the search for cases where only a
+ /// `str` is available.
+ ///
+ /// Instead, the `get` method is generic over the type of the underlying key
+ /// data, called `Q` in the method signature above. It states that `K`
+ /// borrows as a `Q` by requiring that `K: Borrow<Q>`. By additionally
+ /// requiring `Q: Hash + Eq`, it signals the requirement that `K` and `Q`
+ /// have implementations of the `Hash` and `Eq` traits that produce identical
+ /// results.
+ ///
+ /// The implementation of `get` relies in particular on identical
+ /// implementations of `Hash` by determining the key’s hash bucket by calling
+ /// `Hash::hash` on the `Q` value even though it inserted the key based on
+ /// the hash value calculated from the `K` value.
+ ///
+ /// As a consequence, the hash map breaks if a `K` wrapping a `Q` value
+ /// produces a different hash than `Q`. For instance, imagine you have a
+ /// type that wraps a string but compares ASCII letters ignoring their case:
+ ///
+ /// ```
+ /// pub struct CaseInsensitiveString(String);
+ ///
+ /// impl PartialEq for CaseInsensitiveString {
+ ///     fn eq(&self, other: &Self) -> bool {
+ ///         self.0.eq_ignore_ascii_case(&other.0)
+ ///     }
+ /// }
+ ///
+ /// impl Eq for CaseInsensitiveString { }
+ /// ```
+ ///
+ /// Because two equal values need to produce the same hash value, the
+ /// implementation of `Hash` needs to ignore ASCII case, too:
+ ///
+ /// ```
+ /// # use std::hash::{Hash, Hasher};
+ /// # pub struct CaseInsensitiveString(String);
+ /// impl Hash for CaseInsensitiveString {
+ ///     fn hash<H: Hasher>(&self, state: &mut H) {
+ ///         for c in self.0.as_bytes() {
+ ///             c.to_ascii_lowercase().hash(state)
+ ///         }
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// Can `CaseInsensitiveString` implement `Borrow<str>`? It certainly can
+ /// provide a reference to a string slice via its contained owned string.
+ /// But because its `Hash` implementation differs, it behaves differently
+ /// from `str` and therefore must not, in fact, implement `Borrow<str>`.
+ /// If it wants to allow others access to the underlying `str`, it can do
+ /// that via `AsRef<str>` which doesn’t carry any extra requirements.
+ ///
+ /// [`Hash`]: crate::hash::Hash
+ /// [`HashMap<K, V>`]: ../../std/collections/struct.HashMap.html
+ /// [`String`]: ../../std/string/struct.String.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Borrow<Borrowed: ?Sized> {
+     /// Immutably borrows from an owned value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::borrow::Borrow;
+     ///
+     /// fn check<T: Borrow<str>>(s: T) {
+     ///     assert_eq!("Hello", s.borrow());
+     /// }
+     ///
+     /// let s = "Hello".to_string();
+     ///
+     /// check(s);
+     ///
+     /// let s = "Hello";
+     ///
+     /// check(s);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn borrow(&self) -> &Borrowed;
+ }
+ 
+ /// A trait for mutably borrowing data.
+ ///
+ /// As a companion to [`Borrow<T>`] this trait allows a type to borrow as
+ /// an underlying type by providing a mutable reference. See [`Borrow<T>`]
+ /// for more information on borrowing as another type.
+ ///
+ /// [`Borrow<T>`]: Borrow
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait BorrowMut<Borrowed: ?Sized>: Borrow<Borrowed> {
+     /// Mutably borrows from an owned value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::borrow::BorrowMut;
+     ///
+     /// fn check<T: BorrowMut<[i32]>>(mut v: T) {
+     ///     assert_eq!(&mut [1, 2, 3], v.borrow_mut());
+     /// }
+     ///
+     /// let v = vec![1, 2, 3];
+     ///
+     /// check(v);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn borrow_mut(&mut self) -> &mut Borrowed;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Borrow<T> for T {
+     fn borrow(&self) -> &T {
+         self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> BorrowMut<T> for T {
+     fn borrow_mut(&mut self) -> &mut T {
+         self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Borrow<T> for &T {
+     fn borrow(&self) -> &T {
+         &**self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Borrow<T> for &mut T {
+     fn borrow(&self) -> &T {
+         &**self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> BorrowMut<T> for &mut T {
+     fn borrow_mut(&mut self) -> &mut T {
+         &mut **self
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/cell.rs gcc-16-20251102/libgrust/rustc-lib/core/src/cell.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/cell.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/cell.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1800 ----
+ //! Shareable mutable containers.
+ //!
+ //! Rust memory safety is based on this rule: Given an object `T`, it is only possible to
+ //! have one of the following:
+ //!
+ //! - Having several immutable references (`&T`) to the object (also known as **aliasing**).
+ //! - Having one mutable reference (`&mut T`) to the object (also known as **mutability**).
+ //!
+ //! This is enforced by the Rust compiler. However, there are situations where this rule is not
+ //! flexible enough. Sometimes it is required to have multiple references to an object and yet
+ //! mutate it.
+ //!
+ //! Shareable mutable containers exist to permit mutability in a controlled manner, even in the
+ //! presence of aliasing. Both `Cell<T>` and `RefCell<T>` allow doing this in a single-threaded
+ //! way. However, neither `Cell<T>` nor `RefCell<T>` are thread safe (they do not implement
+ //! `Sync`). If you need to do aliasing and mutation between multiple threads it is possible to
+ //! use [`Mutex`](../../std/sync/struct.Mutex.html),
+ //! [`RwLock`](../../std/sync/struct.RwLock.html) or
+ //! [`atomic`](../../core/sync/atomic/index.html) types.
+ //!
+ //! Values of the `Cell<T>` and `RefCell<T>` types may be mutated through shared references (i.e.
+ //! the common `&T` type), whereas most Rust types can only be mutated through unique (`&mut T`)
+ //! references. We say that `Cell<T>` and `RefCell<T>` provide 'interior mutability', in contrast
+ //! with typical Rust types that exhibit 'inherited mutability'.
+ //!
+ //! Cell types come in two flavors: `Cell<T>` and `RefCell<T>`. `Cell<T>` implements interior
+ //! mutability by moving values in and out of the `Cell<T>`. To use references instead of values,
+ //! one must use the `RefCell<T>` type, acquiring a write lock before mutating. `Cell<T>` provides
+ //! methods to retrieve and change the current interior value:
+ //!
+ //!  - For types that implement `Copy`, the `get` method retrieves the current interior value.
+ //!  - For types that implement `Default`, the `take` method replaces the current interior value
+ //!    with `Default::default()` and returns the replaced value.
+ //!  - For all types, the `replace` method replaces the current interior value and returns the
+ //!    replaced value and the `into_inner` method consumes the `Cell<T>` and returns the interior
+ //!    value. Additionally, the `set` method replaces the interior value, dropping the replaced
+ //!    value.
+ //!
+ //! `RefCell<T>` uses Rust's lifetimes to implement 'dynamic borrowing', a process whereby one can
+ //! claim temporary, exclusive, mutable access to the inner value. Borrows for `RefCell<T>`s are
+ //! tracked 'at runtime', unlike Rust's native reference types which are entirely tracked
+ //! statically, at compile time. Because `RefCell<T>` borrows are dynamic it is possible to attempt
+ //! to borrow a value that is already mutably borrowed; when this happens it results in thread
+ //! panic.
+ //!
+ //! # When to choose interior mutability
+ //!
+ //! The more common inherited mutability, where one must have unique access to mutate a value, is
+ //! one of the key language elements that enables Rust to reason strongly about pointer aliasing,
+ //! statically preventing crash bugs. Because of that, inherited mutability is preferred, and
+ //! interior mutability is something of a last resort. Since cell types enable mutation where it
+ //! would otherwise be disallowed though, there are occasions when interior mutability might be
+ //! appropriate, or even *must* be used, e.g.
+ //!
+ //! * Introducing mutability 'inside' of something immutable
+ //! * Implementation details of logically-immutable methods.
+ //! * Mutating implementations of `Clone`.
+ //!
+ //! ## Introducing mutability 'inside' of something immutable
+ //!
+ //! Many shared smart pointer types, including `Rc<T>` and `Arc<T>`, provide containers that can be
+ //! cloned and shared between multiple parties. Because the contained values may be
+ //! multiply-aliased, they can only be borrowed with `&`, not `&mut`. Without cells it would be
+ //! impossible to mutate data inside of these smart pointers at all.
+ //!
+ //! It's very common then to put a `RefCell<T>` inside shared pointer types to reintroduce
+ //! mutability:
+ //!
+ //! ```
+ //! use std::cell::{RefCell, RefMut};
+ //! use std::collections::HashMap;
+ //! use std::rc::Rc;
+ //!
+ //! fn main() {
+ //!     let shared_map: Rc<RefCell<_>> = Rc::new(RefCell::new(HashMap::new()));
+ //!     // Create a new block to limit the scope of the dynamic borrow
+ //!     {
+ //!         let mut map: RefMut<_> = shared_map.borrow_mut();
+ //!         map.insert("africa", 92388);
+ //!         map.insert("kyoto", 11837);
+ //!         map.insert("piccadilly", 11826);
+ //!         map.insert("marbles", 38);
+ //!     }
+ //!
+ //!     // Note that if we had not let the previous borrow of the cache fall out
+ //!     // of scope then the subsequent borrow would cause a dynamic thread panic.
+ //!     // This is the major hazard of using `RefCell`.
+ //!     let total: i32 = shared_map.borrow().values().sum();
+ //!     println!("{}", total);
+ //! }
+ //! ```
+ //!
+ //! Note that this example uses `Rc<T>` and not `Arc<T>`. `RefCell<T>`s are for single-threaded
+ //! scenarios. Consider using `RwLock<T>` or `Mutex<T>` if you need shared mutability in a
+ //! multi-threaded situation.
+ //!
+ //! ## Implementation details of logically-immutable methods
+ //!
+ //! Occasionally it may be desirable not to expose in an API that there is mutation happening
+ //! "under the hood". This may be because logically the operation is immutable, but e.g., caching
+ //! forces the implementation to perform mutation; or because you must employ mutation to implement
+ //! a trait method that was originally defined to take `&self`.
+ //!
+ //! ```
+ //! # #![allow(dead_code)]
+ //! use std::cell::RefCell;
+ //!
+ //! struct Graph {
+ //!     edges: Vec<(i32, i32)>,
+ //!     span_tree_cache: RefCell<Option<Vec<(i32, i32)>>>
+ //! }
+ //!
+ //! impl Graph {
+ //!     fn minimum_spanning_tree(&self) -> Vec<(i32, i32)> {
+ //!         self.span_tree_cache.borrow_mut()
+ //!             .get_or_insert_with(|| self.calc_span_tree())
+ //!             .clone()
+ //!     }
+ //!
+ //!     fn calc_span_tree(&self) -> Vec<(i32, i32)> {
+ //!         // Expensive computation goes here
+ //!         vec![]
+ //!     }
+ //! }
+ //! ```
+ //!
+ //! ## Mutating implementations of `Clone`
+ //!
+ //! This is simply a special - but common - case of the previous: hiding mutability for operations
+ //! that appear to be immutable. The `clone` method is expected to not change the source value, and
+ //! is declared to take `&self`, not `&mut self`. Therefore, any mutation that happens in the
+ //! `clone` method must use cell types. For example, `Rc<T>` maintains its reference counts within a
+ //! `Cell<T>`.
+ //!
+ //! ```
+ //! use std::cell::Cell;
+ //! use std::ptr::NonNull;
+ //! use std::process::abort;
+ //! use std::marker::PhantomData;
+ //!
+ //! struct Rc<T: ?Sized> {
+ //!     ptr: NonNull<RcBox<T>>,
+ //!     phantom: PhantomData<RcBox<T>>,
+ //! }
+ //!
+ //! struct RcBox<T: ?Sized> {
+ //!     strong: Cell<usize>,
+ //!     refcount: Cell<usize>,
+ //!     value: T,
+ //! }
+ //!
+ //! impl<T: ?Sized> Clone for Rc<T> {
+ //!     fn clone(&self) -> Rc<T> {
+ //!         self.inc_strong();
+ //!         Rc {
+ //!             ptr: self.ptr,
+ //!             phantom: PhantomData,
+ //!         }
+ //!     }
+ //! }
+ //!
+ //! trait RcBoxPtr<T: ?Sized> {
+ //!
+ //!     fn inner(&self) -> &RcBox<T>;
+ //!
+ //!     fn strong(&self) -> usize {
+ //!         self.inner().strong.get()
+ //!     }
+ //!
+ //!     fn inc_strong(&self) {
+ //!         self.inner()
+ //!             .strong
+ //!             .set(self.strong()
+ //!                      .checked_add(1)
+ //!                      .unwrap_or_else(|| abort() ));
+ //!     }
+ //! }
+ //!
+ //! impl<T: ?Sized> RcBoxPtr<T> for Rc<T> {
+ //!    fn inner(&self) -> &RcBox<T> {
+ //!        unsafe {
+ //!            self.ptr.as_ref()
+ //!        }
+ //!    }
+ //! }
+ //! ```
+ //!
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::cmp::Ordering;
+ use crate::fmt::{self, Debug, Display};
+ use crate::marker::Unsize;
+ use crate::mem;
+ use crate::ops::{CoerceUnsized, Deref, DerefMut};
+ use crate::ptr;
+ 
+ /// A mutable memory location.
+ ///
+ /// # Examples
+ ///
+ /// In this example, you can see that `Cell<T>` enables mutation inside an
+ /// immutable struct. In other words, it enables "interior mutability".
+ ///
+ /// ```
+ /// use std::cell::Cell;
+ ///
+ /// struct SomeStruct {
+ ///     regular_field: u8,
+ ///     special_field: Cell<u8>,
+ /// }
+ ///
+ /// let my_struct = SomeStruct {
+ ///     regular_field: 0,
+ ///     special_field: Cell::new(1),
+ /// };
+ ///
+ /// let new_value = 100;
+ ///
+ /// // ERROR: `my_struct` is immutable
+ /// // my_struct.regular_field = new_value;
+ ///
+ /// // WORKS: although `my_struct` is immutable, `special_field` is a `Cell`,
+ /// // which can always be mutated
+ /// my_struct.special_field.set(new_value);
+ /// assert_eq!(my_struct.special_field.get(), new_value);
+ /// ```
+ ///
+ /// See the [module-level documentation](self) for more.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[repr(transparent)]
+ pub struct Cell<T: ?Sized> {
+     value: UnsafeCell<T>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T: ?Sized> Send for Cell<T> where T: Send {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Sync for Cell<T> {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Copy> Clone for Cell<T> {
+     #[inline]
+     fn clone(&self) -> Cell<T> {
+         Cell::new(self.get())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Default> Default for Cell<T> {
+     /// Creates a `Cell<T>`, with the `Default` value for T.
+     #[inline]
+     fn default() -> Cell<T> {
+         Cell::new(Default::default())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: PartialEq + Copy> PartialEq for Cell<T> {
+     #[inline]
+     fn eq(&self, other: &Cell<T>) -> bool {
+         self.get() == other.get()
+     }
+ }
+ 
+ #[stable(feature = "cell_eq", since = "1.2.0")]
+ impl<T: Eq + Copy> Eq for Cell<T> {}
+ 
+ #[stable(feature = "cell_ord", since = "1.10.0")]
+ impl<T: PartialOrd + Copy> PartialOrd for Cell<T> {
+     #[inline]
+     fn partial_cmp(&self, other: &Cell<T>) -> Option<Ordering> {
+         self.get().partial_cmp(&other.get())
+     }
+ 
+     #[inline]
+     fn lt(&self, other: &Cell<T>) -> bool {
+         self.get() < other.get()
+     }
+ 
+     #[inline]
+     fn le(&self, other: &Cell<T>) -> bool {
+         self.get() <= other.get()
+     }
+ 
+     #[inline]
+     fn gt(&self, other: &Cell<T>) -> bool {
+         self.get() > other.get()
+     }
+ 
+     #[inline]
+     fn ge(&self, other: &Cell<T>) -> bool {
+         self.get() >= other.get()
+     }
+ }
+ 
+ #[stable(feature = "cell_ord", since = "1.10.0")]
+ impl<T: Ord + Copy> Ord for Cell<T> {
+     #[inline]
+     fn cmp(&self, other: &Cell<T>) -> Ordering {
+         self.get().cmp(&other.get())
+     }
+ }
+ 
+ #[stable(feature = "cell_from", since = "1.12.0")]
+ impl<T> From<T> for Cell<T> {
+     fn from(t: T) -> Cell<T> {
+         Cell::new(t)
+     }
+ }
+ 
+ impl<T> Cell<T> {
+     /// Creates a new `Cell` containing the given value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_cell_new", since = "1.32.0")]
+     #[inline]
+     pub const fn new(value: T) -> Cell<T> {
+         Cell { value: UnsafeCell::new(value) }
+     }
+ 
+     /// Sets the contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     ///
+     /// c.set(10);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn set(&self, val: T) {
+         let old = self.replace(val);
+         drop(old);
+     }
+ 
+     /// Swaps the values of two Cells.
+     /// Difference with `std::mem::swap` is that this function doesn't require `&mut` reference.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c1 = Cell::new(5i32);
+     /// let c2 = Cell::new(10i32);
+     /// c1.swap(&c2);
+     /// assert_eq!(10, c1.get());
+     /// assert_eq!(5, c2.get());
+     /// ```
+     #[inline]
+     #[stable(feature = "move_cell", since = "1.17.0")]
+     pub fn swap(&self, other: &Self) {
+         if ptr::eq(self, other) {
+             return;
+         }
+         // SAFETY: This can be risky if called from separate threads, but `Cell`
+         // is `!Sync` so this won't happen. This also won't invalidate any
+         // pointers since `Cell` makes sure nothing else will be pointing into
+         // either of these `Cell`s.
+         unsafe {
+             ptr::swap(self.value.get(), other.value.get());
+         }
+     }
+ 
+     /// Replaces the contained value, and returns it.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let cell = Cell::new(5);
+     /// assert_eq!(cell.get(), 5);
+     /// assert_eq!(cell.replace(10), 5);
+     /// assert_eq!(cell.get(), 10);
+     /// ```
+     #[stable(feature = "move_cell", since = "1.17.0")]
+     pub fn replace(&self, val: T) -> T {
+         // SAFETY: This can cause data races if called from a separate thread,
+         // but `Cell` is `!Sync` so this won't happen.
+         mem::replace(unsafe { &mut *self.value.get() }, val)
+     }
+ 
+     /// Unwraps the value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     /// let five = c.into_inner();
+     ///
+     /// assert_eq!(five, 5);
+     /// ```
+     #[stable(feature = "move_cell", since = "1.17.0")]
+     #[rustc_const_unstable(feature = "const_cell_into_inner", issue = "78729")]
+     pub const fn into_inner(self) -> T {
+         self.value.into_inner()
+     }
+ }
+ 
+ impl<T: Copy> Cell<T> {
+     /// Returns a copy of the contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     ///
+     /// let five = c.get();
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn get(&self) -> T {
+         // SAFETY: This can cause data races if called from a separate thread,
+         // but `Cell` is `!Sync` so this won't happen.
+         unsafe { *self.value.get() }
+     }
+ 
+     /// Updates the contained value using a function and returns the new value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(cell_update)]
+     ///
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     /// let new = c.update(|x| x + 1);
+     ///
+     /// assert_eq!(new, 6);
+     /// assert_eq!(c.get(), 6);
+     /// ```
+     #[inline]
+     #[unstable(feature = "cell_update", issue = "50186")]
+     pub fn update<F>(&self, f: F) -> T
+     where
+         F: FnOnce(T) -> T,
+     {
+         let old = self.get();
+         let new = f(old);
+         self.set(new);
+         new
+     }
+ }
+ 
+ impl<T: ?Sized> Cell<T> {
+     /// Returns a raw pointer to the underlying data in this cell.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     ///
+     /// let ptr = c.as_ptr();
+     /// ```
+     #[inline]
+     #[stable(feature = "cell_as_ptr", since = "1.12.0")]
+     #[rustc_const_stable(feature = "const_cell_as_ptr", since = "1.32.0")]
+     pub const fn as_ptr(&self) -> *mut T {
+         self.value.get()
+     }
+ 
+     /// Returns a mutable reference to the underlying data.
+     ///
+     /// This call borrows `Cell` mutably (at compile-time) which guarantees
+     /// that we possess the only reference.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let mut c = Cell::new(5);
+     /// *c.get_mut() += 1;
+     ///
+     /// assert_eq!(c.get(), 6);
+     /// ```
+     #[inline]
+     #[stable(feature = "cell_get_mut", since = "1.11.0")]
+     pub fn get_mut(&mut self) -> &mut T {
+         self.value.get_mut()
+     }
+ 
+     /// Returns a `&Cell<T>` from a `&mut T`
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let slice: &mut [i32] = &mut [1, 2, 3];
+     /// let cell_slice: &Cell<[i32]> = Cell::from_mut(slice);
+     /// let slice_cell: &[Cell<i32>] = cell_slice.as_slice_of_cells();
+     ///
+     /// assert_eq!(slice_cell.len(), 3);
+     /// ```
+     #[inline]
+     #[stable(feature = "as_cell", since = "1.37.0")]
+     pub fn from_mut(t: &mut T) -> &Cell<T> {
+         // SAFETY: `&mut` ensures unique access.
+         unsafe { &*(t as *mut T as *const Cell<T>) }
+     }
+ }
+ 
+ impl<T: Default> Cell<T> {
+     /// Takes the value of the cell, leaving `Default::default()` in its place.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let c = Cell::new(5);
+     /// let five = c.take();
+     ///
+     /// assert_eq!(five, 5);
+     /// assert_eq!(c.into_inner(), 0);
+     /// ```
+     #[stable(feature = "move_cell", since = "1.17.0")]
+     pub fn take(&self) -> T {
+         self.replace(Default::default())
+     }
+ }
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: CoerceUnsized<U>, U> CoerceUnsized<Cell<U>> for Cell<T> {}
+ 
+ impl<T> Cell<[T]> {
+     /// Returns a `&[Cell<T>]` from a `&Cell<[T]>`
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::Cell;
+     ///
+     /// let slice: &mut [i32] = &mut [1, 2, 3];
+     /// let cell_slice: &Cell<[i32]> = Cell::from_mut(slice);
+     /// let slice_cell: &[Cell<i32>] = cell_slice.as_slice_of_cells();
+     ///
+     /// assert_eq!(slice_cell.len(), 3);
+     /// ```
+     #[stable(feature = "as_cell", since = "1.37.0")]
+     pub fn as_slice_of_cells(&self) -> &[Cell<T>] {
+         // SAFETY: `Cell<T>` has the same memory layout as `T`.
+         unsafe { &*(self as *const Cell<[T]> as *const [Cell<T>]) }
+     }
+ }
+ 
+ /// A mutable memory location with dynamically checked borrow rules
+ ///
+ /// See the [module-level documentation](self) for more.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RefCell<T: ?Sized> {
+     borrow: Cell<BorrowFlag>,
+     value: UnsafeCell<T>,
+ }
+ 
+ /// An error returned by [`RefCell::try_borrow`].
+ #[stable(feature = "try_borrow", since = "1.13.0")]
+ pub struct BorrowError {
+     _private: (),
+ }
+ 
+ #[stable(feature = "try_borrow", since = "1.13.0")]
+ impl Debug for BorrowError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("BorrowError").finish()
+     }
+ }
+ 
+ #[stable(feature = "try_borrow", since = "1.13.0")]
+ impl Display for BorrowError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         Display::fmt("already mutably borrowed", f)
+     }
+ }
+ 
+ /// An error returned by [`RefCell::try_borrow_mut`].
+ #[stable(feature = "try_borrow", since = "1.13.0")]
+ pub struct BorrowMutError {
+     _private: (),
+ }
+ 
+ #[stable(feature = "try_borrow", since = "1.13.0")]
+ impl Debug for BorrowMutError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("BorrowMutError").finish()
+     }
+ }
+ 
+ #[stable(feature = "try_borrow", since = "1.13.0")]
+ impl Display for BorrowMutError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         Display::fmt("already borrowed", f)
+     }
+ }
+ 
+ // Positive values represent the number of `Ref` active. Negative values
+ // represent the number of `RefMut` active. Multiple `RefMut`s can only be
+ // active at a time if they refer to distinct, nonoverlapping components of a
+ // `RefCell` (e.g., different ranges of a slice).
+ //
+ // `Ref` and `RefMut` are both two words in size, and so there will likely never
+ // be enough `Ref`s or `RefMut`s in existence to overflow half of the `usize`
+ // range. Thus, a `BorrowFlag` will probably never overflow or underflow.
+ // However, this is not a guarantee, as a pathological program could repeatedly
+ // create and then mem::forget `Ref`s or `RefMut`s. Thus, all code must
+ // explicitly check for overflow and underflow in order to avoid unsafety, or at
+ // least behave correctly in the event that overflow or underflow happens (e.g.,
+ // see BorrowRef::new).
+ type BorrowFlag = isize;
+ const UNUSED: BorrowFlag = 0;
+ 
+ #[inline(always)]
+ fn is_writing(x: BorrowFlag) -> bool {
+     x < UNUSED
+ }
+ 
+ #[inline(always)]
+ fn is_reading(x: BorrowFlag) -> bool {
+     x > UNUSED
+ }
+ 
+ impl<T> RefCell<T> {
+     /// Creates a new `RefCell` containing `value`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_refcell_new", since = "1.32.0")]
+     #[inline]
+     pub const fn new(value: T) -> RefCell<T> {
+         RefCell { value: UnsafeCell::new(value), borrow: Cell::new(UNUSED) }
+     }
+ 
+     /// Consumes the `RefCell`, returning the wrapped value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// let five = c.into_inner();
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_cell_into_inner", issue = "78729")]
+     #[inline]
+     pub const fn into_inner(self) -> T {
+         // Since this function takes `self` (the `RefCell`) by value, the
+         // compiler statically verifies that it is not currently borrowed.
+         self.value.into_inner()
+     }
+ 
+     /// Replaces the wrapped value with a new one, returning the old value,
+     /// without deinitializing either one.
+     ///
+     /// This function corresponds to [`std::mem::replace`](../mem/fn.replace.html).
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is currently borrowed.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     /// let cell = RefCell::new(5);
+     /// let old_value = cell.replace(6);
+     /// assert_eq!(old_value, 5);
+     /// assert_eq!(cell, RefCell::new(6));
+     /// ```
+     #[inline]
+     #[stable(feature = "refcell_replace", since = "1.24.0")]
+     #[track_caller]
+     pub fn replace(&self, t: T) -> T {
+         mem::replace(&mut *self.borrow_mut(), t)
+     }
+ 
+     /// Replaces the wrapped value with a new one computed from `f`, returning
+     /// the old value, without deinitializing either one.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is currently borrowed.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     /// let cell = RefCell::new(5);
+     /// let old_value = cell.replace_with(|&mut old| old + 1);
+     /// assert_eq!(old_value, 5);
+     /// assert_eq!(cell, RefCell::new(6));
+     /// ```
+     #[inline]
+     #[stable(feature = "refcell_replace_swap", since = "1.35.0")]
+     #[track_caller]
+     pub fn replace_with<F: FnOnce(&mut T) -> T>(&self, f: F) -> T {
+         let mut_borrow = &mut *self.borrow_mut();
+         let replacement = f(mut_borrow);
+         mem::replace(mut_borrow, replacement)
+     }
+ 
+     /// Swaps the wrapped value of `self` with the wrapped value of `other`,
+     /// without deinitializing either one.
+     ///
+     /// This function corresponds to [`std::mem::swap`](../mem/fn.swap.html).
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     /// let c = RefCell::new(5);
+     /// let d = RefCell::new(6);
+     /// c.swap(&d);
+     /// assert_eq!(c, RefCell::new(6));
+     /// assert_eq!(d, RefCell::new(5));
+     /// ```
+     #[inline]
+     #[stable(feature = "refcell_swap", since = "1.24.0")]
+     pub fn swap(&self, other: &Self) {
+         mem::swap(&mut *self.borrow_mut(), &mut *other.borrow_mut())
+     }
+ }
+ 
+ impl<T: ?Sized> RefCell<T> {
+     /// Immutably borrows the wrapped value.
+     ///
+     /// The borrow lasts until the returned `Ref` exits scope. Multiple
+     /// immutable borrows can be taken out at the same time.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is currently mutably borrowed. For a non-panicking variant, use
+     /// [`try_borrow`](#method.try_borrow).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// let borrowed_five = c.borrow();
+     /// let borrowed_five2 = c.borrow();
+     /// ```
+     ///
+     /// An example of panic:
+     ///
+     /// ```should_panic
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// let m = c.borrow_mut();
+     /// let b = c.borrow(); // this causes a panic
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     #[track_caller]
+     pub fn borrow(&self) -> Ref<'_, T> {
+         self.try_borrow().expect("already mutably borrowed")
+     }
+ 
+     /// Immutably borrows the wrapped value, returning an error if the value is currently mutably
+     /// borrowed.
+     ///
+     /// The borrow lasts until the returned `Ref` exits scope. Multiple immutable borrows can be
+     /// taken out at the same time.
+     ///
+     /// This is the non-panicking variant of [`borrow`](#method.borrow).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// {
+     ///     let m = c.borrow_mut();
+     ///     assert!(c.try_borrow().is_err());
+     /// }
+     ///
+     /// {
+     ///     let m = c.borrow();
+     ///     assert!(c.try_borrow().is_ok());
+     /// }
+     /// ```
+     #[stable(feature = "try_borrow", since = "1.13.0")]
+     #[inline]
+     pub fn try_borrow(&self) -> Result<Ref<'_, T>, BorrowError> {
+         match BorrowRef::new(&self.borrow) {
+             // SAFETY: `BorrowRef` ensures that there is only immutable access
+             // to the value while borrowed.
+             Some(b) => Ok(Ref { value: unsafe { &*self.value.get() }, borrow: b }),
+             None => Err(BorrowError { _private: () }),
+         }
+     }
+ 
+     /// Mutably borrows the wrapped value.
+     ///
+     /// The borrow lasts until the returned `RefMut` or all `RefMut`s derived
+     /// from it exit scope. The value cannot be borrowed while this borrow is
+     /// active.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is currently borrowed. For a non-panicking variant, use
+     /// [`try_borrow_mut`](#method.try_borrow_mut).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new("hello".to_owned());
+     ///
+     /// *c.borrow_mut() = "bonjour".to_owned();
+     ///
+     /// assert_eq!(&*c.borrow(), "bonjour");
+     /// ```
+     ///
+     /// An example of panic:
+     ///
+     /// ```should_panic
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     /// let m = c.borrow();
+     ///
+     /// let b = c.borrow_mut(); // this causes a panic
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     #[track_caller]
+     pub fn borrow_mut(&self) -> RefMut<'_, T> {
+         self.try_borrow_mut().expect("already borrowed")
+     }
+ 
+     /// Mutably borrows the wrapped value, returning an error if the value is currently borrowed.
+     ///
+     /// The borrow lasts until the returned `RefMut` or all `RefMut`s derived
+     /// from it exit scope. The value cannot be borrowed while this borrow is
+     /// active.
+     ///
+     /// This is the non-panicking variant of [`borrow_mut`](#method.borrow_mut).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// {
+     ///     let m = c.borrow();
+     ///     assert!(c.try_borrow_mut().is_err());
+     /// }
+     ///
+     /// assert!(c.try_borrow_mut().is_ok());
+     /// ```
+     #[stable(feature = "try_borrow", since = "1.13.0")]
+     #[inline]
+     pub fn try_borrow_mut(&self) -> Result<RefMut<'_, T>, BorrowMutError> {
+         match BorrowRefMut::new(&self.borrow) {
+             // SAFETY: `BorrowRef` guarantees unique access.
+             Some(b) => Ok(RefMut { value: unsafe { &mut *self.value.get() }, borrow: b }),
+             None => Err(BorrowMutError { _private: () }),
+         }
+     }
+ 
+     /// Returns a raw pointer to the underlying data in this cell.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// let ptr = c.as_ptr();
+     /// ```
+     #[inline]
+     #[stable(feature = "cell_as_ptr", since = "1.12.0")]
+     pub fn as_ptr(&self) -> *mut T {
+         self.value.get()
+     }
+ 
+     /// Returns a mutable reference to the underlying data.
+     ///
+     /// This call borrows `RefCell` mutably (at compile-time) so there is no
+     /// need for dynamic checks.
+     ///
+     /// However be cautious: this method expects `self` to be mutable, which is
+     /// generally not the case when using a `RefCell`. Take a look at the
+     /// [`borrow_mut`] method instead if `self` isn't mutable.
+     ///
+     /// Also, please be aware that this method is only for special circumstances and is usually
+     /// not what you want. In case of doubt, use [`borrow_mut`] instead.
+     ///
+     /// [`borrow_mut`]: #method.borrow_mut
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let mut c = RefCell::new(5);
+     /// *c.get_mut() += 1;
+     ///
+     /// assert_eq!(c, RefCell::new(6));
+     /// ```
+     #[inline]
+     #[stable(feature = "cell_get_mut", since = "1.11.0")]
+     pub fn get_mut(&mut self) -> &mut T {
+         self.value.get_mut()
+     }
+ 
+     /// Undo the effect of leaked guards on the borrow state of the `RefCell`.
+     ///
+     /// This call is similar to [`get_mut`] but more specialized. It borrows `RefCell` mutably to
+     /// ensure no borrows exist and then resets the state tracking shared borrows. This is relevant
+     /// if some `Ref` or `RefMut` borrows have been leaked.
+     ///
+     /// [`get_mut`]: #method.get_mut
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(cell_leak)]
+     /// use std::cell::RefCell;
+     ///
+     /// let mut c = RefCell::new(0);
+     /// std::mem::forget(c.borrow_mut());
+     ///
+     /// assert!(c.try_borrow().is_err());
+     /// c.undo_leak();
+     /// assert!(c.try_borrow().is_ok());
+     /// ```
+     #[unstable(feature = "cell_leak", issue = "69099")]
+     pub fn undo_leak(&mut self) -> &mut T {
+         *self.borrow.get_mut() = UNUSED;
+         self.get_mut()
+     }
+ 
+     /// Immutably borrows the wrapped value, returning an error if the value is
+     /// currently mutably borrowed.
+     ///
+     /// # Safety
+     ///
+     /// Unlike `RefCell::borrow`, this method is unsafe because it does not
+     /// return a `Ref`, thus leaving the borrow flag untouched. Mutably
+     /// borrowing the `RefCell` while the reference returned by this method
+     /// is alive is undefined behaviour.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     ///
+     /// {
+     ///     let m = c.borrow_mut();
+     ///     assert!(unsafe { c.try_borrow_unguarded() }.is_err());
+     /// }
+     ///
+     /// {
+     ///     let m = c.borrow();
+     ///     assert!(unsafe { c.try_borrow_unguarded() }.is_ok());
+     /// }
+     /// ```
+     #[stable(feature = "borrow_state", since = "1.37.0")]
+     #[inline]
+     pub unsafe fn try_borrow_unguarded(&self) -> Result<&T, BorrowError> {
+         if !is_writing(self.borrow.get()) {
+             // SAFETY: We check that nobody is actively writing now, but it is
+             // the caller's responsibility to ensure that nobody writes until
+             // the returned reference is no longer in use.
+             // Also, `self.value.get()` refers to the value owned by `self`
+             // and is thus guaranteed to be valid for the lifetime of `self`.
+             Ok(unsafe { &*self.value.get() })
+         } else {
+             Err(BorrowError { _private: () })
+         }
+     }
+ }
+ 
+ impl<T: Default> RefCell<T> {
+     /// Takes the wrapped value, leaving `Default::default()` in its place.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is currently borrowed.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(refcell_take)]
+     /// use std::cell::RefCell;
+     ///
+     /// let c = RefCell::new(5);
+     /// let five = c.take();
+     ///
+     /// assert_eq!(five, 5);
+     /// assert_eq!(c.into_inner(), 0);
+     /// ```
+     #[unstable(feature = "refcell_take", issue = "71395")]
+     pub fn take(&self) -> T {
+         self.replace(Default::default())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T: ?Sized> Send for RefCell<T> where T: Send {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Sync for RefCell<T> {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Clone> Clone for RefCell<T> {
+     /// # Panics
+     ///
+     /// Panics if the value is currently mutably borrowed.
+     #[inline]
+     #[track_caller]
+     fn clone(&self) -> RefCell<T> {
+         RefCell::new(self.borrow().clone())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Default> Default for RefCell<T> {
+     /// Creates a `RefCell<T>`, with the `Default` value for T.
+     #[inline]
+     fn default() -> RefCell<T> {
+         RefCell::new(Default::default())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized + PartialEq> PartialEq for RefCell<T> {
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn eq(&self, other: &RefCell<T>) -> bool {
+         *self.borrow() == *other.borrow()
+     }
+ }
+ 
+ #[stable(feature = "cell_eq", since = "1.2.0")]
+ impl<T: ?Sized + Eq> Eq for RefCell<T> {}
+ 
+ #[stable(feature = "cell_ord", since = "1.10.0")]
+ impl<T: ?Sized + PartialOrd> PartialOrd for RefCell<T> {
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn partial_cmp(&self, other: &RefCell<T>) -> Option<Ordering> {
+         self.borrow().partial_cmp(&*other.borrow())
+     }
+ 
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn lt(&self, other: &RefCell<T>) -> bool {
+         *self.borrow() < *other.borrow()
+     }
+ 
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn le(&self, other: &RefCell<T>) -> bool {
+         *self.borrow() <= *other.borrow()
+     }
+ 
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn gt(&self, other: &RefCell<T>) -> bool {
+         *self.borrow() > *other.borrow()
+     }
+ 
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn ge(&self, other: &RefCell<T>) -> bool {
+         *self.borrow() >= *other.borrow()
+     }
+ }
+ 
+ #[stable(feature = "cell_ord", since = "1.10.0")]
+ impl<T: ?Sized + Ord> Ord for RefCell<T> {
+     /// # Panics
+     ///
+     /// Panics if the value in either `RefCell` is currently borrowed.
+     #[inline]
+     fn cmp(&self, other: &RefCell<T>) -> Ordering {
+         self.borrow().cmp(&*other.borrow())
+     }
+ }
+ 
+ #[stable(feature = "cell_from", since = "1.12.0")]
+ impl<T> From<T> for RefCell<T> {
+     fn from(t: T) -> RefCell<T> {
+         RefCell::new(t)
+     }
+ }
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: CoerceUnsized<U>, U> CoerceUnsized<RefCell<U>> for RefCell<T> {}
+ 
+ struct BorrowRef<'b> {
+     borrow: &'b Cell<BorrowFlag>,
+ }
+ 
+ impl<'b> BorrowRef<'b> {
+     #[inline]
+     fn new(borrow: &'b Cell<BorrowFlag>) -> Option<BorrowRef<'b>> {
+         let b = borrow.get().wrapping_add(1);
+         if !is_reading(b) {
+             // Incrementing borrow can result in a non-reading value (<= 0) in these cases:
+             // 1. It was < 0, i.e. there are writing borrows, so we can't allow a read borrow
+             //    due to Rust's reference aliasing rules
+             // 2. It was isize::MAX (the max amount of reading borrows) and it overflowed
+             //    into isize::MIN (the max amount of writing borrows) so we can't allow
+             //    an additional read borrow because isize can't represent so many read borrows
+             //    (this can only happen if you mem::forget more than a small constant amount of
+             //    `Ref`s, which is not good practice)
+             None
+         } else {
+             // Incrementing borrow can result in a reading value (> 0) in these cases:
+             // 1. It was = 0, i.e. it wasn't borrowed, and we are taking the first read borrow
+             // 2. It was > 0 and < isize::MAX, i.e. there were read borrows, and isize
+             //    is large enough to represent having one more read borrow
+             borrow.set(b);
+             Some(BorrowRef { borrow })
+         }
+     }
+ }
+ 
+ impl Drop for BorrowRef<'_> {
+     #[inline]
+     fn drop(&mut self) {
+         let borrow = self.borrow.get();
+         debug_assert!(is_reading(borrow));
+         self.borrow.set(borrow - 1);
+     }
+ }
+ 
+ impl Clone for BorrowRef<'_> {
+     #[inline]
+     fn clone(&self) -> Self {
+         // Since this Ref exists, we know the borrow flag
+         // is a reading borrow.
+         let borrow = self.borrow.get();
+         debug_assert!(is_reading(borrow));
+         // Prevent the borrow counter from overflowing into
+         // a writing borrow.
+         assert!(borrow != isize::MAX);
+         self.borrow.set(borrow + 1);
+         BorrowRef { borrow: self.borrow }
+     }
+ }
+ 
+ /// Wraps a borrowed reference to a value in a `RefCell` box.
+ /// A wrapper type for an immutably borrowed value from a `RefCell<T>`.
+ ///
+ /// See the [module-level documentation](self) for more.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Ref<'b, T: ?Sized + 'b> {
+     value: &'b T,
+     borrow: BorrowRef<'b>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Deref for Ref<'_, T> {
+     type Target = T;
+ 
+     #[inline]
+     fn deref(&self) -> &T {
+         self.value
+     }
+ }
+ 
+ impl<'b, T: ?Sized> Ref<'b, T> {
+     /// Copies a `Ref`.
+     ///
+     /// The `RefCell` is already immutably borrowed, so this cannot fail.
+     ///
+     /// This is an associated function that needs to be used as
+     /// `Ref::clone(...)`. A `Clone` implementation or a method would interfere
+     /// with the widespread use of `r.borrow().clone()` to clone the contents of
+     /// a `RefCell`.
+     #[stable(feature = "cell_extras", since = "1.15.0")]
+     #[inline]
+     pub fn clone(orig: &Ref<'b, T>) -> Ref<'b, T> {
+         Ref { value: orig.value, borrow: orig.borrow.clone() }
+     }
+ 
+     /// Makes a new `Ref` for a component of the borrowed data.
+     ///
+     /// The `RefCell` is already immutably borrowed, so this cannot fail.
+     ///
+     /// This is an associated function that needs to be used as `Ref::map(...)`.
+     /// A method would interfere with methods of the same name on the contents
+     /// of a `RefCell` used through `Deref`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::{RefCell, Ref};
+     ///
+     /// let c = RefCell::new((5, 'b'));
+     /// let b1: Ref<(u32, char)> = c.borrow();
+     /// let b2: Ref<u32> = Ref::map(b1, |t| &t.0);
+     /// assert_eq!(*b2, 5)
+     /// ```
+     #[stable(feature = "cell_map", since = "1.8.0")]
+     #[inline]
+     pub fn map<U: ?Sized, F>(orig: Ref<'b, T>, f: F) -> Ref<'b, U>
+     where
+         F: FnOnce(&T) -> &U,
+     {
+         Ref { value: f(orig.value), borrow: orig.borrow }
+     }
+ 
+     /// Splits a `Ref` into multiple `Ref`s for different components of the
+     /// borrowed data.
+     ///
+     /// The `RefCell` is already immutably borrowed, so this cannot fail.
+     ///
+     /// This is an associated function that needs to be used as
+     /// `Ref::map_split(...)`. A method would interfere with methods of the same
+     /// name on the contents of a `RefCell` used through `Deref`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::{Ref, RefCell};
+     ///
+     /// let cell = RefCell::new([1, 2, 3, 4]);
+     /// let borrow = cell.borrow();
+     /// let (begin, end) = Ref::map_split(borrow, |slice| slice.split_at(2));
+     /// assert_eq!(*begin, [1, 2]);
+     /// assert_eq!(*end, [3, 4]);
+     /// ```
+     #[stable(feature = "refcell_map_split", since = "1.35.0")]
+     #[inline]
+     pub fn map_split<U: ?Sized, V: ?Sized, F>(orig: Ref<'b, T>, f: F) -> (Ref<'b, U>, Ref<'b, V>)
+     where
+         F: FnOnce(&T) -> (&U, &V),
+     {
+         let (a, b) = f(orig.value);
+         let borrow = orig.borrow.clone();
+         (Ref { value: a, borrow }, Ref { value: b, borrow: orig.borrow })
+     }
+ 
+     /// Convert into a reference to the underlying data.
+     ///
+     /// The underlying `RefCell` can never be mutably borrowed from again and will always appear
+     /// already immutably borrowed. It is not a good idea to leak more than a constant number of
+     /// references. The `RefCell` can be immutably borrowed again if only a smaller number of leaks
+     /// have occurred in total.
+     ///
+     /// This is an associated function that needs to be used as
+     /// `Ref::leak(...)`. A method would interfere with methods of the
+     /// same name on the contents of a `RefCell` used through `Deref`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(cell_leak)]
+     /// use std::cell::{RefCell, Ref};
+     /// let cell = RefCell::new(0);
+     ///
+     /// let value = Ref::leak(cell.borrow());
+     /// assert_eq!(*value, 0);
+     ///
+     /// assert!(cell.try_borrow().is_ok());
+     /// assert!(cell.try_borrow_mut().is_err());
+     /// ```
+     #[unstable(feature = "cell_leak", issue = "69099")]
+     pub fn leak(orig: Ref<'b, T>) -> &'b T {
+         // By forgetting this Ref we ensure that the borrow counter in the RefCell can't go back to
+         // UNUSED within the lifetime `'b`. Resetting the reference tracking state would require a
+         // unique reference to the borrowed RefCell. No further mutable references can be created
+         // from the original cell.
+         mem::forget(orig.borrow);
+         orig.value
+     }
+ }
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'b, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<Ref<'b, U>> for Ref<'b, T> {}
+ 
+ #[stable(feature = "std_guard_impls", since = "1.20.0")]
+ impl<T: ?Sized + fmt::Display> fmt::Display for Ref<'_, T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.value.fmt(f)
+     }
+ }
+ 
+ impl<'b, T: ?Sized> RefMut<'b, T> {
+     /// Makes a new `RefMut` for a component of the borrowed data, e.g., an enum
+     /// variant.
+     ///
+     /// The `RefCell` is already mutably borrowed, so this cannot fail.
+     ///
+     /// This is an associated function that needs to be used as
+     /// `RefMut::map(...)`. A method would interfere with methods of the same
+     /// name on the contents of a `RefCell` used through `Deref`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::{RefCell, RefMut};
+     ///
+     /// let c = RefCell::new((5, 'b'));
+     /// {
+     ///     let b1: RefMut<(u32, char)> = c.borrow_mut();
+     ///     let mut b2: RefMut<u32> = RefMut::map(b1, |t| &mut t.0);
+     ///     assert_eq!(*b2, 5);
+     ///     *b2 = 42;
+     /// }
+     /// assert_eq!(*c.borrow(), (42, 'b'));
+     /// ```
+     #[stable(feature = "cell_map", since = "1.8.0")]
+     #[inline]
+     pub fn map<U: ?Sized, F>(orig: RefMut<'b, T>, f: F) -> RefMut<'b, U>
+     where
+         F: FnOnce(&mut T) -> &mut U,
+     {
+         // FIXME(nll-rfc#40): fix borrow-check
+         let RefMut { value, borrow } = orig;
+         RefMut { value: f(value), borrow }
+     }
+ 
+     /// Splits a `RefMut` into multiple `RefMut`s for different components of the
+     /// borrowed data.
+     ///
+     /// The underlying `RefCell` will remain mutably borrowed until both
+     /// returned `RefMut`s go out of scope.
+     ///
+     /// The `RefCell` is already mutably borrowed, so this cannot fail.
+     ///
+     /// This is an associated function that needs to be used as
+     /// `RefMut::map_split(...)`. A method would interfere with methods of the
+     /// same name on the contents of a `RefCell` used through `Deref`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::{RefCell, RefMut};
+     ///
+     /// let cell = RefCell::new([1, 2, 3, 4]);
+     /// let borrow = cell.borrow_mut();
+     /// let (mut begin, mut end) = RefMut::map_split(borrow, |slice| slice.split_at_mut(2));
+     /// assert_eq!(*begin, [1, 2]);
+     /// assert_eq!(*end, [3, 4]);
+     /// begin.copy_from_slice(&[4, 3]);
+     /// end.copy_from_slice(&[2, 1]);
+     /// ```
+     #[stable(feature = "refcell_map_split", since = "1.35.0")]
+     #[inline]
+     pub fn map_split<U: ?Sized, V: ?Sized, F>(
+         orig: RefMut<'b, T>,
+         f: F,
+     ) -> (RefMut<'b, U>, RefMut<'b, V>)
+     where
+         F: FnOnce(&mut T) -> (&mut U, &mut V),
+     {
+         let (a, b) = f(orig.value);
+         let borrow = orig.borrow.clone();
+         (RefMut { value: a, borrow }, RefMut { value: b, borrow: orig.borrow })
+     }
+ 
+     /// Convert into a mutable reference to the underlying data.
+     ///
+     /// The underlying `RefCell` can not be borrowed from again and will always appear already
+     /// mutably borrowed, making the returned reference the only to the interior.
+     ///
+     /// This is an associated function that needs to be used as
+     /// `RefMut::leak(...)`. A method would interfere with methods of the
+     /// same name on the contents of a `RefCell` used through `Deref`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(cell_leak)]
+     /// use std::cell::{RefCell, RefMut};
+     /// let cell = RefCell::new(0);
+     ///
+     /// let value = RefMut::leak(cell.borrow_mut());
+     /// assert_eq!(*value, 0);
+     /// *value = 1;
+     ///
+     /// assert!(cell.try_borrow_mut().is_err());
+     /// ```
+     #[unstable(feature = "cell_leak", issue = "69099")]
+     pub fn leak(orig: RefMut<'b, T>) -> &'b mut T {
+         // By forgetting this BorrowRefMut we ensure that the borrow counter in the RefCell can't
+         // go back to UNUSED within the lifetime `'b`. Resetting the reference tracking state would
+         // require a unique reference to the borrowed RefCell. No further references can be created
+         // from the original cell within that lifetime, making the current borrow the only
+         // reference for the remaining lifetime.
+         mem::forget(orig.borrow);
+         orig.value
+     }
+ }
+ 
+ struct BorrowRefMut<'b> {
+     borrow: &'b Cell<BorrowFlag>,
+ }
+ 
+ impl Drop for BorrowRefMut<'_> {
+     #[inline]
+     fn drop(&mut self) {
+         let borrow = self.borrow.get();
+         debug_assert!(is_writing(borrow));
+         self.borrow.set(borrow + 1);
+     }
+ }
+ 
+ impl<'b> BorrowRefMut<'b> {
+     #[inline]
+     fn new(borrow: &'b Cell<BorrowFlag>) -> Option<BorrowRefMut<'b>> {
+         // NOTE: Unlike BorrowRefMut::clone, new is called to create the initial
+         // mutable reference, and so there must currently be no existing
+         // references. Thus, while clone increments the mutable refcount, here
+         // we explicitly only allow going from UNUSED to UNUSED - 1.
+         match borrow.get() {
+             UNUSED => {
+                 borrow.set(UNUSED - 1);
+                 Some(BorrowRefMut { borrow })
+             }
+             _ => None,
+         }
+     }
+ 
+     // Clones a `BorrowRefMut`.
+     //
+     // This is only valid if each `BorrowRefMut` is used to track a mutable
+     // reference to a distinct, nonoverlapping range of the original object.
+     // This isn't in a Clone impl so that code doesn't call this implicitly.
+     #[inline]
+     fn clone(&self) -> BorrowRefMut<'b> {
+         let borrow = self.borrow.get();
+         debug_assert!(is_writing(borrow));
+         // Prevent the borrow counter from underflowing.
+         assert!(borrow != isize::MIN);
+         self.borrow.set(borrow - 1);
+         BorrowRefMut { borrow: self.borrow }
+     }
+ }
+ 
+ /// A wrapper type for a mutably borrowed value from a `RefCell<T>`.
+ ///
+ /// See the [module-level documentation](self) for more.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RefMut<'b, T: ?Sized + 'b> {
+     value: &'b mut T,
+     borrow: BorrowRefMut<'b>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Deref for RefMut<'_, T> {
+     type Target = T;
+ 
+     #[inline]
+     fn deref(&self) -> &T {
+         self.value
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> DerefMut for RefMut<'_, T> {
+     #[inline]
+     fn deref_mut(&mut self) -> &mut T {
+         self.value
+     }
+ }
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'b, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<RefMut<'b, U>> for RefMut<'b, T> {}
+ 
+ #[stable(feature = "std_guard_impls", since = "1.20.0")]
+ impl<T: ?Sized + fmt::Display> fmt::Display for RefMut<'_, T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.value.fmt(f)
+     }
+ }
+ 
+ /// The core primitive for interior mutability in Rust.
+ ///
+ /// `UnsafeCell<T>` is a type that wraps some `T` and indicates unsafe interior operations on the
+ /// wrapped type. Types with an `UnsafeCell<T>` field are considered to have an 'unsafe interior'.
+ /// The `UnsafeCell<T>` type is the only legal way to obtain aliasable data that is considered
+ /// mutable. In general, transmuting an `&T` type into an `&mut T` is considered undefined behavior.
+ ///
+ /// If you have a reference `&SomeStruct`, then normally in Rust all fields of `SomeStruct` are
+ /// immutable. The compiler makes optimizations based on the knowledge that `&T` is not mutably
+ /// aliased or mutated, and that `&mut T` is unique. `UnsafeCell<T>` is the only core language
+ /// feature to work around the restriction that `&T` may not be mutated. All other types that
+ /// allow internal mutability, such as `Cell<T>` and `RefCell<T>`, use `UnsafeCell` to wrap their
+ /// internal data. There is *no* legal way to obtain aliasing `&mut`, not even with `UnsafeCell<T>`.
+ ///
+ /// The `UnsafeCell` API itself is technically very simple: [`.get()`] gives you a raw pointer
+ /// `*mut T` to its contents. It is up to _you_ as the abstraction designer to use that raw pointer
+ /// correctly.
+ ///
+ /// [`.get()`]: `UnsafeCell::get`
+ ///
+ /// The precise Rust aliasing rules are somewhat in flux, but the main points are not contentious:
+ ///
+ /// - If you create a safe reference with lifetime `'a` (either a `&T` or `&mut T`
+ /// reference) that is accessible by safe code (for example, because you returned it),
+ /// then you must not access the data in any way that contradicts that reference for the
+ /// remainder of `'a`. For example, this means that if you take the `*mut T` from an
+ /// `UnsafeCell<T>` and cast it to an `&T`, then the data in `T` must remain immutable
+ /// (modulo any `UnsafeCell` data found within `T`, of course) until that reference's
+ /// lifetime expires. Similarly, if you create a `&mut T` reference that is released to
+ /// safe code, then you must not access the data within the `UnsafeCell` until that
+ /// reference expires.
+ ///
+ /// - At all times, you must avoid data races. If multiple threads have access to
+ /// the same `UnsafeCell`, then any writes must have a proper happens-before relation to all other
+ /// accesses (or use atomics).
+ ///
+ /// To assist with proper design, the following scenarios are explicitly declared legal
+ /// for single-threaded code:
+ ///
+ /// 1. A `&T` reference can be released to safe code and there it can co-exist with other `&T`
+ /// references, but not with a `&mut T`
+ ///
+ /// 2. A `&mut T` reference may be released to safe code provided neither other `&mut T` nor `&T`
+ /// co-exist with it. A `&mut T` must always be unique.
+ ///
+ /// Note that whilst mutating the contents of an `&UnsafeCell<T>` (even while other
+ /// `&UnsafeCell<T>` references alias the cell) is
+ /// ok (provided you enforce the above invariants some other way), it is still undefined behavior
+ /// to have multiple `&mut UnsafeCell<T>` aliases. That is, `UnsafeCell` is a wrapper
+ /// designed to have a special interaction with _shared_ accesses (_i.e._, through an
+ /// `&UnsafeCell<_>` reference); there is no magic whatsoever when dealing with _exclusive_
+ /// accesses (_e.g._, through an `&mut UnsafeCell<_>`): neither the cell nor the wrapped value
+ /// may be aliased for the duration of that `&mut` borrow.
+ /// This is showcased by the [`.get_mut()`] accessor, which is a non-`unsafe` getter that yields
+ /// a `&mut T`.
+ ///
+ /// [`.get_mut()`]: `UnsafeCell::get_mut`
+ ///
+ /// # Examples
+ ///
+ /// Here is an example showcasing how to soundly mutate the contents of an `UnsafeCell<_>` despite
+ /// there being multiple references aliasing the cell:
+ ///
+ /// ```
+ /// use std::cell::UnsafeCell;
+ ///
+ /// let x: UnsafeCell<i32> = 42.into();
+ /// // Get multiple / concurrent / shared references to the same `x`.
+ /// let (p1, p2): (&UnsafeCell<i32>, &UnsafeCell<i32>) = (&x, &x);
+ ///
+ /// unsafe {
+ ///     // SAFETY: within this scope there are no other references to `x`'s contents,
+ ///     // so ours is effectively unique.
+ ///     let p1_exclusive: &mut i32 = &mut *p1.get(); // -- borrow --+
+ ///     *p1_exclusive += 27; //                                     |
+ /// } // <---------- cannot go beyond this point -------------------+
+ ///
+ /// unsafe {
+ ///     // SAFETY: within this scope nobody expects to have exclusive access to `x`'s contents,
+ ///     // so we can have multiple shared accesses concurrently.
+ ///     let p2_shared: &i32 = &*p2.get();
+ ///     assert_eq!(*p2_shared, 42 + 27);
+ ///     let p1_shared: &i32 = &*p1.get();
+ ///     assert_eq!(*p1_shared, *p2_shared);
+ /// }
+ /// ```
+ ///
+ /// The following example showcases the fact that exclusive access to an `UnsafeCell<T>`
+ /// implies exclusive access to its `T`:
+ ///
+ /// ```rust
+ /// #![feature(unsafe_cell_get_mut)]
+ /// #![forbid(unsafe_code)] // with exclusive accesses,
+ ///                         // `UnsafeCell` is a transparent no-op wrapper,
+ ///                         // so no need for `unsafe` here.
+ /// use std::cell::UnsafeCell;
+ ///
+ /// let mut x: UnsafeCell<i32> = 42.into();
+ ///
+ /// // Get a compile-time-checked unique reference to `x`.
+ /// let p_unique: &mut UnsafeCell<i32> = &mut x;
+ /// // With an exclusive reference, we can mutate the contents for free.
+ /// *p_unique.get_mut() = 0;
+ /// // Or, equivalently:
+ /// x = UnsafeCell::new(0);
+ ///
+ /// // When we own the value, we can extract the contents for free.
+ /// let contents: i32 = x.into_inner();
+ /// assert_eq!(contents, 0);
+ /// ```
+ #[lang = "unsafe_cell"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[repr(transparent)]
+ #[repr(no_niche)] // rust-lang/rust#68303.
+ pub struct UnsafeCell<T: ?Sized> {
+     value: T,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Sync for UnsafeCell<T> {}
+ 
+ impl<T> UnsafeCell<T> {
+     /// Constructs a new instance of `UnsafeCell` which will wrap the specified
+     /// value.
+     ///
+     /// All access to the inner value through methods is `unsafe`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::UnsafeCell;
+     ///
+     /// let uc = UnsafeCell::new(5);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_unsafe_cell_new", since = "1.32.0")]
+     #[inline]
+     pub const fn new(value: T) -> UnsafeCell<T> {
+         UnsafeCell { value }
+     }
+ 
+     /// Unwraps the value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::UnsafeCell;
+     ///
+     /// let uc = UnsafeCell::new(5);
+     ///
+     /// let five = uc.into_inner();
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_cell_into_inner", issue = "78729")]
+     pub const fn into_inner(self) -> T {
+         self.value
+     }
+ }
+ 
+ impl<T: ?Sized> UnsafeCell<T> {
+     /// Gets a mutable pointer to the wrapped value.
+     ///
+     /// This can be cast to a pointer of any kind.
+     /// Ensure that the access is unique (no active references, mutable or not)
+     /// when casting to `&mut T`, and ensure that there are no mutations
+     /// or mutable aliases going on when casting to `&T`
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cell::UnsafeCell;
+     ///
+     /// let uc = UnsafeCell::new(5);
+     ///
+     /// let five = uc.get();
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_unsafecell_get", since = "1.32.0")]
+     pub const fn get(&self) -> *mut T {
+         // We can just cast the pointer from `UnsafeCell<T>` to `T` because of
+         // #[repr(transparent)]. This exploits libstd's special status, there is
+         // no guarantee for user code that this will work in future versions of the compiler!
+         self as *const UnsafeCell<T> as *const T as *mut T
+     }
+ 
+     /// Returns a mutable reference to the underlying data.
+     ///
+     /// This call borrows the `UnsafeCell` mutably (at compile-time) which
+     /// guarantees that we possess the only reference.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(unsafe_cell_get_mut)]
+     /// use std::cell::UnsafeCell;
+     ///
+     /// let mut c = UnsafeCell::new(5);
+     /// *c.get_mut() += 1;
+     ///
+     /// assert_eq!(*c.get_mut(), 6);
+     /// ```
+     #[inline]
+     #[unstable(feature = "unsafe_cell_get_mut", issue = "76943")]
+     pub fn get_mut(&mut self) -> &mut T {
+         &mut self.value
+     }
+ 
+     /// Gets a mutable pointer to the wrapped value.
+     /// The difference to [`get`] is that this function accepts a raw pointer,
+     /// which is useful to avoid the creation of temporary references.
+     ///
+     /// The result can be cast to a pointer of any kind.
+     /// Ensure that the access is unique (no active references, mutable or not)
+     /// when casting to `&mut T`, and ensure that there are no mutations
+     /// or mutable aliases going on when casting to `&T`.
+     ///
+     /// [`get`]: #method.get
+     ///
+     /// # Examples
+     ///
+     /// Gradual initialization of an `UnsafeCell` requires `raw_get`, as
+     /// calling `get` would require creating a reference to uninitialized data:
+     ///
+     /// ```
+     /// #![feature(unsafe_cell_raw_get)]
+     /// use std::cell::UnsafeCell;
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let m = MaybeUninit::<UnsafeCell<i32>>::uninit();
+     /// unsafe { UnsafeCell::raw_get(m.as_ptr()).write(5); }
+     /// let uc = unsafe { m.assume_init() };
+     ///
+     /// assert_eq!(uc.into_inner(), 5);
+     /// ```
+     #[inline]
+     #[unstable(feature = "unsafe_cell_raw_get", issue = "66358")]
+     pub const fn raw_get(this: *const Self) -> *mut T {
+         // We can just cast the pointer from `UnsafeCell<T>` to `T` because of
+         // #[repr(transparent)]. This exploits libstd's special status, there is
+         // no guarantee for user code that this will work in future versions of the compiler!
+         this as *const T as *mut T
+     }
+ }
+ 
+ #[stable(feature = "unsafe_cell_default", since = "1.10.0")]
+ impl<T: Default> Default for UnsafeCell<T> {
+     /// Creates an `UnsafeCell`, with the `Default` value for T.
+     fn default() -> UnsafeCell<T> {
+         UnsafeCell::new(Default::default())
+     }
+ }
+ 
+ #[stable(feature = "cell_from", since = "1.12.0")]
+ impl<T> From<T> for UnsafeCell<T> {
+     fn from(t: T) -> UnsafeCell<T> {
+         UnsafeCell::new(t)
+     }
+ }
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: CoerceUnsized<U>, U> CoerceUnsized<UnsafeCell<U>> for UnsafeCell<T> {}
+ 
+ #[allow(unused)]
+ fn assert_coerce_unsized(a: UnsafeCell<&i32>, b: Cell<&i32>, c: RefCell<&i32>) {
+     let _: UnsafeCell<&dyn Send> = a;
+     let _: Cell<&dyn Send> = b;
+     let _: RefCell<&dyn Send> = c;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/char/convert.rs gcc-16-20251102/libgrust/rustc-lib/core/src/char/convert.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/char/convert.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/char/convert.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,290 ----
+ //! Character conversions.
+ 
+ use crate::convert::TryFrom;
+ use crate::fmt;
+ use crate::mem::transmute;
+ use crate::str::FromStr;
+ 
+ use super::MAX;
+ 
+ /// Converts a `u32` to a `char`.
+ ///
+ /// Note that all [`char`]s are valid [`u32`]s, and can be cast to one with
+ /// `as`:
+ ///
+ /// ```
+ /// let c = '💯';
+ /// let i = c as u32;
+ ///
+ /// assert_eq!(128175, i);
+ /// ```
+ ///
+ /// However, the reverse is not true: not all valid [`u32`]s are valid
+ /// [`char`]s. `from_u32()` will return `None` if the input is not a valid value
+ /// for a [`char`].
+ ///
+ /// For an unsafe version of this function which ignores these checks, see
+ /// [`from_u32_unchecked`].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::char;
+ ///
+ /// let c = char::from_u32(0x2764);
+ ///
+ /// assert_eq!(Some('❤'), c);
+ /// ```
+ ///
+ /// Returning `None` when the input is not a valid [`char`]:
+ ///
+ /// ```
+ /// use std::char;
+ ///
+ /// let c = char::from_u32(0x110000);
+ ///
+ /// assert_eq!(None, c);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn from_u32(i: u32) -> Option<char> {
+     char::try_from(i).ok()
+ }
+ 
+ /// Converts a `u32` to a `char`, ignoring validity.
+ ///
+ /// Note that all [`char`]s are valid [`u32`]s, and can be cast to one with
+ /// `as`:
+ ///
+ /// ```
+ /// let c = '💯';
+ /// let i = c as u32;
+ ///
+ /// assert_eq!(128175, i);
+ /// ```
+ ///
+ /// However, the reverse is not true: not all valid [`u32`]s are valid
+ /// [`char`]s. `from_u32_unchecked()` will ignore this, and blindly cast to
+ /// [`char`], possibly creating an invalid one.
+ ///
+ /// # Safety
+ ///
+ /// This function is unsafe, as it may construct invalid `char` values.
+ ///
+ /// For a safe version of this function, see the [`from_u32`] function.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::char;
+ ///
+ /// let c = unsafe { char::from_u32_unchecked(0x2764) };
+ ///
+ /// assert_eq!('❤', c);
+ /// ```
+ #[inline]
+ #[stable(feature = "char_from_unchecked", since = "1.5.0")]
+ pub unsafe fn from_u32_unchecked(i: u32) -> char {
+     // SAFETY: the caller must guarantee that `i` is a valid char value.
+     if cfg!(debug_assertions) { char::from_u32(i).unwrap() } else { unsafe { transmute(i) } }
+ }
+ 
+ #[stable(feature = "char_convert", since = "1.13.0")]
+ impl From<char> for u32 {
+     /// Converts a [`char`] into a [`u32`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::mem;
+     ///
+     /// let c = 'c';
+     /// let u = u32::from(c);
+     /// assert!(4 == mem::size_of_val(&u))
+     /// ```
+     #[inline]
+     fn from(c: char) -> Self {
+         c as u32
+     }
+ }
+ 
+ /// Maps a byte in 0x00..=0xFF to a `char` whose code point has the same value, in U+0000..=U+00FF.
+ ///
+ /// Unicode is designed such that this effectively decodes bytes
+ /// with the character encoding that IANA calls ISO-8859-1.
+ /// This encoding is compatible with ASCII.
+ ///
+ /// Note that this is different from ISO/IEC 8859-1 a.k.a. ISO 8859-1 (with one less hyphen),
+ /// which leaves some "blanks", byte values that are not assigned to any character.
+ /// ISO-8859-1 (the IANA one) assigns them to the C0 and C1 control codes.
+ ///
+ /// Note that this is *also* different from Windows-1252 a.k.a. code page 1252,
+ /// which is a superset ISO/IEC 8859-1 that assigns some (not all!) blanks
+ /// to punctuation and various Latin characters.
+ ///
+ /// To confuse things further, [on the Web](https://encoding.spec.whatwg.org/)
+ /// `ascii`, `iso-8859-1`, and `windows-1252` are all aliases
+ /// for a superset of Windows-1252 that fills the remaining blanks with corresponding
+ /// C0 and C1 control codes.
+ #[stable(feature = "char_convert", since = "1.13.0")]
+ impl From<u8> for char {
+     /// Converts a [`u8`] into a [`char`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::mem;
+     ///
+     /// let u = 32 as u8;
+     /// let c = char::from(u);
+     /// assert!(4 == mem::size_of_val(&c))
+     /// ```
+     #[inline]
+     fn from(i: u8) -> Self {
+         i as char
+     }
+ }
+ 
+ /// An error which can be returned when parsing a char.
+ #[stable(feature = "char_from_str", since = "1.20.0")]
+ #[derive(Clone, Debug, PartialEq, Eq)]
+ pub struct ParseCharError {
+     kind: CharErrorKind,
+ }
+ 
+ impl ParseCharError {
+     #[unstable(
+         feature = "char_error_internals",
+         reason = "this method should not be available publicly",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     pub fn __description(&self) -> &str {
+         match self.kind {
+             CharErrorKind::EmptyString => "cannot parse char from empty string",
+             CharErrorKind::TooManyChars => "too many characters in string",
+         }
+     }
+ }
+ 
+ #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+ enum CharErrorKind {
+     EmptyString,
+     TooManyChars,
+ }
+ 
+ #[stable(feature = "char_from_str", since = "1.20.0")]
+ impl fmt::Display for ParseCharError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.__description().fmt(f)
+     }
+ }
+ 
+ #[stable(feature = "char_from_str", since = "1.20.0")]
+ impl FromStr for char {
+     type Err = ParseCharError;
+ 
+     #[inline]
+     fn from_str(s: &str) -> Result<Self, Self::Err> {
+         let mut chars = s.chars();
+         match (chars.next(), chars.next()) {
+             (None, _) => Err(ParseCharError { kind: CharErrorKind::EmptyString }),
+             (Some(c), None) => Ok(c),
+             _ => Err(ParseCharError { kind: CharErrorKind::TooManyChars }),
+         }
+     }
+ }
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl TryFrom<u32> for char {
+     type Error = CharTryFromError;
+ 
+     #[inline]
+     fn try_from(i: u32) -> Result<Self, Self::Error> {
+         if (i > MAX as u32) || (i >= 0xD800 && i <= 0xDFFF) {
+             Err(CharTryFromError(()))
+         } else {
+             // SAFETY: checked that it's a legal unicode value
+             Ok(unsafe { transmute(i) })
+         }
+     }
+ }
+ 
+ /// The error type returned when a conversion from u32 to char fails.
+ #[stable(feature = "try_from", since = "1.34.0")]
+ #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+ pub struct CharTryFromError(());
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl fmt::Display for CharTryFromError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         "converted integer out of range for `char`".fmt(f)
+     }
+ }
+ 
+ /// Converts a digit in the given radix to a `char`.
+ ///
+ /// A 'radix' here is sometimes also called a 'base'. A radix of two
+ /// indicates a binary number, a radix of ten, decimal, and a radix of
+ /// sixteen, hexadecimal, to give some common values. Arbitrary
+ /// radices are supported.
+ ///
+ /// `from_digit()` will return `None` if the input is not a digit in
+ /// the given radix.
+ ///
+ /// # Panics
+ ///
+ /// Panics if given a radix larger than 36.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::char;
+ ///
+ /// let c = char::from_digit(4, 10);
+ ///
+ /// assert_eq!(Some('4'), c);
+ ///
+ /// // Decimal 11 is a single digit in base 16
+ /// let c = char::from_digit(11, 16);
+ ///
+ /// assert_eq!(Some('b'), c);
+ /// ```
+ ///
+ /// Returning `None` when the input is not a digit:
+ ///
+ /// ```
+ /// use std::char;
+ ///
+ /// let c = char::from_digit(20, 10);
+ ///
+ /// assert_eq!(None, c);
+ /// ```
+ ///
+ /// Passing a large radix, causing a panic:
+ ///
+ /// ```should_panic
+ /// use std::char;
+ ///
+ /// // this panics
+ /// let c = char::from_digit(1, 37);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn from_digit(num: u32, radix: u32) -> Option<char> {
+     if radix > 36 {
+         panic!("from_digit: radix is too high (maximum 36)");
+     }
+     if num < radix {
+         let num = num as u8;
+         if num < 10 { Some((b'0' + num) as char) } else { Some((b'a' + num - 10) as char) }
+     } else {
+         None
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/char/decode.rs gcc-16-20251102/libgrust/rustc-lib/core/src/char/decode.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/char/decode.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/char/decode.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,135 ----
+ //! UTF-8 and UTF-16 decoding iterators
+ 
+ use crate::fmt;
+ 
+ use super::from_u32_unchecked;
+ 
+ /// An iterator that decodes UTF-16 encoded code points from an iterator of `u16`s.
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ #[derive(Clone, Debug)]
+ pub struct DecodeUtf16<I>
+ where
+     I: Iterator<Item = u16>,
+ {
+     iter: I,
+     buf: Option<u16>,
+ }
+ 
+ /// An error that can be returned when decoding UTF-16 code points.
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ #[derive(Debug, Clone, Eq, PartialEq)]
+ pub struct DecodeUtf16Error {
+     code: u16,
+ }
+ 
+ /// Creates an iterator over the UTF-16 encoded code points in `iter`,
+ /// returning unpaired surrogates as `Err`s.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::char::decode_utf16;
+ ///
+ /// // 𝄞mus<invalid>ic<invalid>
+ /// let v = [
+ ///     0xD834, 0xDD1E, 0x006d, 0x0075, 0x0073, 0xDD1E, 0x0069, 0x0063, 0xD834,
+ /// ];
+ ///
+ /// assert_eq!(
+ ///     decode_utf16(v.iter().cloned())
+ ///         .map(|r| r.map_err(|e| e.unpaired_surrogate()))
+ ///         .collect::<Vec<_>>(),
+ ///     vec![
+ ///         Ok('𝄞'),
+ ///         Ok('m'), Ok('u'), Ok('s'),
+ ///         Err(0xDD1E),
+ ///         Ok('i'), Ok('c'),
+ ///         Err(0xD834)
+ ///     ]
+ /// );
+ /// ```
+ ///
+ /// A lossy decoder can be obtained by replacing `Err` results with the replacement character:
+ ///
+ /// ```
+ /// use std::char::{decode_utf16, REPLACEMENT_CHARACTER};
+ ///
+ /// // 𝄞mus<invalid>ic<invalid>
+ /// let v = [
+ ///     0xD834, 0xDD1E, 0x006d, 0x0075, 0x0073, 0xDD1E, 0x0069, 0x0063, 0xD834,
+ /// ];
+ ///
+ /// assert_eq!(
+ ///     decode_utf16(v.iter().cloned())
+ ///        .map(|r| r.unwrap_or(REPLACEMENT_CHARACTER))
+ ///        .collect::<String>(),
+ ///     "𝄞mus�ic�"
+ /// );
+ /// ```
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ #[inline]
+ pub fn decode_utf16<I: IntoIterator<Item = u16>>(iter: I) -> DecodeUtf16<I::IntoIter> {
+     DecodeUtf16 { iter: iter.into_iter(), buf: None }
+ }
+ 
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ impl<I: Iterator<Item = u16>> Iterator for DecodeUtf16<I> {
+     type Item = Result<char, DecodeUtf16Error>;
+ 
+     fn next(&mut self) -> Option<Result<char, DecodeUtf16Error>> {
+         let u = match self.buf.take() {
+             Some(buf) => buf,
+             None => self.iter.next()?,
+         };
+ 
+         if u < 0xD800 || 0xDFFF < u {
+             // SAFETY: not a surrogate
+             Some(Ok(unsafe { from_u32_unchecked(u as u32) }))
+         } else if u >= 0xDC00 {
+             // a trailing surrogate
+             Some(Err(DecodeUtf16Error { code: u }))
+         } else {
+             let u2 = match self.iter.next() {
+                 Some(u2) => u2,
+                 // eof
+                 None => return Some(Err(DecodeUtf16Error { code: u })),
+             };
+             if u2 < 0xDC00 || u2 > 0xDFFF {
+                 // not a trailing surrogate so we're not a valid
+                 // surrogate pair, so rewind to redecode u2 next time.
+                 self.buf = Some(u2);
+                 return Some(Err(DecodeUtf16Error { code: u }));
+             }
+ 
+             // all ok, so lets decode it.
+             let c = (((u - 0xD800) as u32) << 10 | (u2 - 0xDC00) as u32) + 0x1_0000;
+             // SAFETY: we checked that it's a legal unicode value
+             Some(Ok(unsafe { from_u32_unchecked(c) }))
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (low, high) = self.iter.size_hint();
+         // we could be entirely valid surrogates (2 elements per
+         // char), or entirely non-surrogates (1 element per char)
+         (low / 2, high)
+     }
+ }
+ 
+ impl DecodeUtf16Error {
+     /// Returns the unpaired surrogate which caused this error.
+     #[stable(feature = "decode_utf16", since = "1.9.0")]
+     pub fn unpaired_surrogate(&self) -> u16 {
+         self.code
+     }
+ }
+ 
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ impl fmt::Display for DecodeUtf16Error {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(f, "unpaired surrogate found: {:x}", self.code)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/char/methods.rs gcc-16-20251102/libgrust/rustc-lib/core/src/char/methods.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/char/methods.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/char/methods.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1657 ----
+ //! impl char {}
+ 
+ use crate::slice;
+ use crate::str::from_utf8_unchecked_mut;
+ use crate::unicode::printable::is_printable;
+ use crate::unicode::{self, conversions};
+ 
+ use super::*;
+ 
+ #[lang = "char"]
+ impl char {
+     /// The highest valid code point a `char` can have.
+     ///
+     /// A `char` is a [Unicode Scalar Value], which means that it is a [Code
+     /// Point], but only ones within a certain range. `MAX` is the highest valid
+     /// code point that's a valid [Unicode Scalar Value].
+     ///
+     /// [Unicode Scalar Value]: http://www.unicode.org/glossary/#unicode_scalar_value
+     /// [Code Point]: http://www.unicode.org/glossary/#code_point
+     #[unstable(feature = "assoc_char_consts", reason = "recently added", issue = "71763")]
+     pub const MAX: char = '\u{10ffff}';
+ 
+     /// `U+FFFD REPLACEMENT CHARACTER` (�) is used in Unicode to represent a
+     /// decoding error.
+     ///
+     /// It can occur, for example, when giving ill-formed UTF-8 bytes to
+     /// [`String::from_utf8_lossy`](string/struct.String.html#method.from_utf8_lossy).
+     #[unstable(feature = "assoc_char_consts", reason = "recently added", issue = "71763")]
+     pub const REPLACEMENT_CHARACTER: char = '\u{FFFD}';
+ 
+     /// The version of [Unicode](http://www.unicode.org/) that the Unicode parts of
+     /// `char` and `str` methods are based on.
+     ///
+     /// New versions of Unicode are released regularly and subsequently all methods
+     /// in the standard library depending on Unicode are updated. Therefore the
+     /// behavior of some `char` and `str` methods and the value of this constant
+     /// changes over time. This is *not* considered to be a breaking change.
+     ///
+     /// The version numbering scheme is explained in
+     /// [Unicode 11.0 or later, Section 3.1 Versions of the Unicode Standard](https://www.unicode.org/versions/Unicode11.0.0/ch03.pdf#page=4).
+     #[unstable(feature = "assoc_char_consts", reason = "recently added", issue = "71763")]
+     pub const UNICODE_VERSION: (u8, u8, u8) = crate::unicode::UNICODE_VERSION;
+ 
+     /// Creates an iterator over the UTF-16 encoded code points in `iter`,
+     /// returning unpaired surrogates as `Err`s.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::char::decode_utf16;
+     ///
+     /// // 𝄞mus<invalid>ic<invalid>
+     /// let v = [
+     ///     0xD834, 0xDD1E, 0x006d, 0x0075, 0x0073, 0xDD1E, 0x0069, 0x0063, 0xD834,
+     /// ];
+     ///
+     /// assert_eq!(
+     ///     decode_utf16(v.iter().cloned())
+     ///         .map(|r| r.map_err(|e| e.unpaired_surrogate()))
+     ///         .collect::<Vec<_>>(),
+     ///     vec![
+     ///         Ok('𝄞'),
+     ///         Ok('m'), Ok('u'), Ok('s'),
+     ///         Err(0xDD1E),
+     ///         Ok('i'), Ok('c'),
+     ///         Err(0xD834)
+     ///     ]
+     /// );
+     /// ```
+     ///
+     /// A lossy decoder can be obtained by replacing `Err` results with the replacement character:
+     ///
+     /// ```
+     /// use std::char::{decode_utf16, REPLACEMENT_CHARACTER};
+     ///
+     /// // 𝄞mus<invalid>ic<invalid>
+     /// let v = [
+     ///     0xD834, 0xDD1E, 0x006d, 0x0075, 0x0073, 0xDD1E, 0x0069, 0x0063, 0xD834,
+     /// ];
+     ///
+     /// assert_eq!(
+     ///     decode_utf16(v.iter().cloned())
+     ///        .map(|r| r.unwrap_or(REPLACEMENT_CHARACTER))
+     ///        .collect::<String>(),
+     ///     "𝄞mus�ic�"
+     /// );
+     /// ```
+     #[unstable(feature = "assoc_char_funcs", reason = "recently added", issue = "71763")]
+     #[inline]
+     pub fn decode_utf16<I: IntoIterator<Item = u16>>(iter: I) -> DecodeUtf16<I::IntoIter> {
+         super::decode::decode_utf16(iter)
+     }
+ 
+     /// Converts a `u32` to a `char`.
+     ///
+     /// Note that all `char`s are valid [`u32`]s, and can be cast to one with
+     /// `as`:
+     ///
+     /// ```
+     /// let c = '💯';
+     /// let i = c as u32;
+     ///
+     /// assert_eq!(128175, i);
+     /// ```
+     ///
+     /// However, the reverse is not true: not all valid [`u32`]s are valid
+     /// `char`s. `from_u32()` will return `None` if the input is not a valid value
+     /// for a `char`.
+     ///
+     /// [`u32`]: primitive.u32.html
+     ///
+     /// For an unsafe version of this function which ignores these checks, see
+     /// [`from_u32_unchecked`].
+     ///
+     /// [`from_u32_unchecked`]: #method.from_u32_unchecked
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::char;
+     ///
+     /// let c = char::from_u32(0x2764);
+     ///
+     /// assert_eq!(Some('❤'), c);
+     /// ```
+     ///
+     /// Returning `None` when the input is not a valid `char`:
+     ///
+     /// ```
+     /// use std::char;
+     ///
+     /// let c = char::from_u32(0x110000);
+     ///
+     /// assert_eq!(None, c);
+     /// ```
+     #[unstable(feature = "assoc_char_funcs", reason = "recently added", issue = "71763")]
+     #[inline]
+     pub fn from_u32(i: u32) -> Option<char> {
+         super::convert::from_u32(i)
+     }
+ 
+     /// Converts a `u32` to a `char`, ignoring validity.
+     ///
+     /// Note that all `char`s are valid [`u32`]s, and can be cast to one with
+     /// `as`:
+     ///
+     /// ```
+     /// let c = '💯';
+     /// let i = c as u32;
+     ///
+     /// assert_eq!(128175, i);
+     /// ```
+     ///
+     /// However, the reverse is not true: not all valid [`u32`]s are valid
+     /// `char`s. `from_u32_unchecked()` will ignore this, and blindly cast to
+     /// `char`, possibly creating an invalid one.
+     ///
+     /// [`u32`]: primitive.u32.html
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe, as it may construct invalid `char` values.
+     ///
+     /// For a safe version of this function, see the [`from_u32`] function.
+     ///
+     /// [`from_u32`]: #method.from_u32
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::char;
+     ///
+     /// let c = unsafe { char::from_u32_unchecked(0x2764) };
+     ///
+     /// assert_eq!('❤', c);
+     /// ```
+     #[unstable(feature = "assoc_char_funcs", reason = "recently added", issue = "71763")]
+     #[inline]
+     pub unsafe fn from_u32_unchecked(i: u32) -> char {
+         // SAFETY: the safety contract must be upheld by the caller.
+         unsafe { super::convert::from_u32_unchecked(i) }
+     }
+ 
+     /// Converts a digit in the given radix to a `char`.
+     ///
+     /// A 'radix' here is sometimes also called a 'base'. A radix of two
+     /// indicates a binary number, a radix of ten, decimal, and a radix of
+     /// sixteen, hexadecimal, to give some common values. Arbitrary
+     /// radices are supported.
+     ///
+     /// `from_digit()` will return `None` if the input is not a digit in
+     /// the given radix.
+     ///
+     /// # Panics
+     ///
+     /// Panics if given a radix larger than 36.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::char;
+     ///
+     /// let c = char::from_digit(4, 10);
+     ///
+     /// assert_eq!(Some('4'), c);
+     ///
+     /// // Decimal 11 is a single digit in base 16
+     /// let c = char::from_digit(11, 16);
+     ///
+     /// assert_eq!(Some('b'), c);
+     /// ```
+     ///
+     /// Returning `None` when the input is not a digit:
+     ///
+     /// ```
+     /// use std::char;
+     ///
+     /// let c = char::from_digit(20, 10);
+     ///
+     /// assert_eq!(None, c);
+     /// ```
+     ///
+     /// Passing a large radix, causing a panic:
+     ///
+     /// ```should_panic
+     /// use std::char;
+     ///
+     /// // this panics
+     /// char::from_digit(1, 37);
+     /// ```
+     #[unstable(feature = "assoc_char_funcs", reason = "recently added", issue = "71763")]
+     #[inline]
+     pub fn from_digit(num: u32, radix: u32) -> Option<char> {
+         super::convert::from_digit(num, radix)
+     }
+ 
+     /// Checks if a `char` is a digit in the given radix.
+     ///
+     /// A 'radix' here is sometimes also called a 'base'. A radix of two
+     /// indicates a binary number, a radix of ten, decimal, and a radix of
+     /// sixteen, hexadecimal, to give some common values. Arbitrary
+     /// radices are supported.
+     ///
+     /// Compared to `is_numeric()`, this function only recognizes the characters
+     /// `0-9`, `a-z` and `A-Z`.
+     ///
+     /// 'Digit' is defined to be only the following characters:
+     ///
+     /// * `0-9`
+     /// * `a-z`
+     /// * `A-Z`
+     ///
+     /// For a more comprehensive understanding of 'digit', see [`is_numeric`][is_numeric].
+     ///
+     /// [is_numeric]: #method.is_numeric
+     ///
+     /// # Panics
+     ///
+     /// Panics if given a radix larger than 36.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!('1'.is_digit(10));
+     /// assert!('f'.is_digit(16));
+     /// assert!(!'f'.is_digit(10));
+     /// ```
+     ///
+     /// Passing a large radix, causing a panic:
+     ///
+     /// ```should_panic
+     /// // this panics
+     /// '1'.is_digit(37);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_digit(self, radix: u32) -> bool {
+         self.to_digit(radix).is_some()
+     }
+ 
+     /// Converts a `char` to a digit in the given radix.
+     ///
+     /// A 'radix' here is sometimes also called a 'base'. A radix of two
+     /// indicates a binary number, a radix of ten, decimal, and a radix of
+     /// sixteen, hexadecimal, to give some common values. Arbitrary
+     /// radices are supported.
+     ///
+     /// 'Digit' is defined to be only the following characters:
+     ///
+     /// * `0-9`
+     /// * `a-z`
+     /// * `A-Z`
+     ///
+     /// # Errors
+     ///
+     /// Returns `None` if the `char` does not refer to a digit in the given radix.
+     ///
+     /// # Panics
+     ///
+     /// Panics if given a radix larger than 36.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert_eq!('1'.to_digit(10), Some(1));
+     /// assert_eq!('f'.to_digit(16), Some(15));
+     /// ```
+     ///
+     /// Passing a non-digit results in failure:
+     ///
+     /// ```
+     /// assert_eq!('f'.to_digit(10), None);
+     /// assert_eq!('z'.to_digit(16), None);
+     /// ```
+     ///
+     /// Passing a large radix, causing a panic:
+     ///
+     /// ```should_panic
+     /// // this panics
+     /// '1'.to_digit(37);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn to_digit(self, radix: u32) -> Option<u32> {
+         assert!(radix <= 36, "to_digit: radix is too high (maximum 36)");
+ 
+         // the code is split up here to improve execution speed for cases where
+         // the `radix` is constant and 10 or smaller
+         let val = if radix <= 10 {
+             match self {
+                 '0'..='9' => self as u32 - '0' as u32,
+                 _ => return None,
+             }
+         } else {
+             match self {
+                 '0'..='9' => self as u32 - '0' as u32,
+                 'a'..='z' => self as u32 - 'a' as u32 + 10,
+                 'A'..='Z' => self as u32 - 'A' as u32 + 10,
+                 _ => return None,
+             }
+         };
+ 
+         if val < radix { Some(val) } else { None }
+     }
+ 
+     /// Returns an iterator that yields the hexadecimal Unicode escape of a
+     /// character as `char`s.
+     ///
+     /// This will escape characters with the Rust syntax of the form
+     /// `\u{NNNNNN}` where `NNNNNN` is a hexadecimal representation.
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in '❤'.escape_unicode() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", '❤'.escape_unicode());
+     /// ```
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("\\u{{2764}}");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!('❤'.escape_unicode().to_string(), "\\u{2764}");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn escape_unicode(self) -> EscapeUnicode {
+         let c = self as u32;
+ 
+         // or-ing 1 ensures that for c==0 the code computes that one
+         // digit should be printed and (which is the same) avoids the
+         // (31 - 32) underflow
+         let msb = 31 - (c | 1).leading_zeros();
+ 
+         // the index of the most significant hex digit
+         let ms_hex_digit = msb / 4;
+         EscapeUnicode {
+             c: self,
+             state: EscapeUnicodeState::Backslash,
+             hex_digit_idx: ms_hex_digit as usize,
+         }
+     }
+ 
+     /// An extended version of `escape_debug` that optionally permits escaping
+     /// Extended Grapheme codepoints. This allows us to format characters like
+     /// nonspacing marks better when they're at the start of a string.
+     #[inline]
+     pub(crate) fn escape_debug_ext(self, escape_grapheme_extended: bool) -> EscapeDebug {
+         let init_state = match self {
+             '\t' => EscapeDefaultState::Backslash('t'),
+             '\r' => EscapeDefaultState::Backslash('r'),
+             '\n' => EscapeDefaultState::Backslash('n'),
+             '\\' | '\'' | '"' => EscapeDefaultState::Backslash(self),
+             _ if escape_grapheme_extended && self.is_grapheme_extended() => {
+                 EscapeDefaultState::Unicode(self.escape_unicode())
+             }
+             _ if is_printable(self) => EscapeDefaultState::Char(self),
+             _ => EscapeDefaultState::Unicode(self.escape_unicode()),
+         };
+         EscapeDebug(EscapeDefault { state: init_state })
+     }
+ 
+     /// Returns an iterator that yields the literal escape code of a character
+     /// as `char`s.
+     ///
+     /// This will escape the characters similar to the `Debug` implementations
+     /// of `str` or `char`.
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in '\n'.escape_debug() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", '\n'.escape_debug());
+     /// ```
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("\\n");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!('\n'.escape_debug().to_string(), "\\n");
+     /// ```
+     #[stable(feature = "char_escape_debug", since = "1.20.0")]
+     #[inline]
+     pub fn escape_debug(self) -> EscapeDebug {
+         self.escape_debug_ext(true)
+     }
+ 
+     /// Returns an iterator that yields the literal escape code of a character
+     /// as `char`s.
+     ///
+     /// The default is chosen with a bias toward producing literals that are
+     /// legal in a variety of languages, including C++11 and similar C-family
+     /// languages. The exact rules are:
+     ///
+     /// * Tab is escaped as `\t`.
+     /// * Carriage return is escaped as `\r`.
+     /// * Line feed is escaped as `\n`.
+     /// * Single quote is escaped as `\'`.
+     /// * Double quote is escaped as `\"`.
+     /// * Backslash is escaped as `\\`.
+     /// * Any character in the 'printable ASCII' range `0x20` .. `0x7e`
+     ///   inclusive is not escaped.
+     /// * All other characters are given hexadecimal Unicode escapes; see
+     ///   [`escape_unicode`][escape_unicode].
+     ///
+     /// [escape_unicode]: #method.escape_unicode
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in '"'.escape_default() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", '"'.escape_default());
+     /// ```
+     ///
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("\\\"");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!('"'.escape_default().to_string(), "\\\"");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn escape_default(self) -> EscapeDefault {
+         let init_state = match self {
+             '\t' => EscapeDefaultState::Backslash('t'),
+             '\r' => EscapeDefaultState::Backslash('r'),
+             '\n' => EscapeDefaultState::Backslash('n'),
+             '\\' | '\'' | '"' => EscapeDefaultState::Backslash(self),
+             '\x20'..='\x7e' => EscapeDefaultState::Char(self),
+             _ => EscapeDefaultState::Unicode(self.escape_unicode()),
+         };
+         EscapeDefault { state: init_state }
+     }
+ 
+     /// Returns the number of bytes this `char` would need if encoded in UTF-8.
+     ///
+     /// That number of bytes is always between 1 and 4, inclusive.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let len = 'A'.len_utf8();
+     /// assert_eq!(len, 1);
+     ///
+     /// let len = 'ß'.len_utf8();
+     /// assert_eq!(len, 2);
+     ///
+     /// let len = 'ℝ'.len_utf8();
+     /// assert_eq!(len, 3);
+     ///
+     /// let len = '💣'.len_utf8();
+     /// assert_eq!(len, 4);
+     /// ```
+     ///
+     /// The `&str` type guarantees that its contents are UTF-8, and so we can compare the length it
+     /// would take if each code point was represented as a `char` vs in the `&str` itself:
+     ///
+     /// ```
+     /// // as chars
+     /// let eastern = '東';
+     /// let capital = '京';
+     ///
+     /// // both can be represented as three bytes
+     /// assert_eq!(3, eastern.len_utf8());
+     /// assert_eq!(3, capital.len_utf8());
+     ///
+     /// // as a &str, these two are encoded in UTF-8
+     /// let tokyo = "東京";
+     ///
+     /// let len = eastern.len_utf8() + capital.len_utf8();
+     ///
+     /// // we can see that they take six bytes total...
+     /// assert_eq!(6, tokyo.len());
+     ///
+     /// // ... just like the &str
+     /// assert_eq!(len, tokyo.len());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn len_utf8(self) -> usize {
+         len_utf8(self as u32)
+     }
+ 
+     /// Returns the number of 16-bit code units this `char` would need if
+     /// encoded in UTF-16.
+     ///
+     /// See the documentation for [`len_utf8`] for more explanation of this
+     /// concept. This function is a mirror, but for UTF-16 instead of UTF-8.
+     ///
+     /// [`len_utf8`]: #method.len_utf8
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let n = 'ß'.len_utf16();
+     /// assert_eq!(n, 1);
+     ///
+     /// let len = '💣'.len_utf16();
+     /// assert_eq!(len, 2);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn len_utf16(self) -> usize {
+         let ch = self as u32;
+         if (ch & 0xFFFF) == ch { 1 } else { 2 }
+     }
+ 
+     /// Encodes this character as UTF-8 into the provided byte buffer,
+     /// and then returns the subslice of the buffer that contains the encoded character.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the buffer is not large enough.
+     /// A buffer of length four is large enough to encode any `char`.
+     ///
+     /// # Examples
+     ///
+     /// In both of these examples, 'ß' takes two bytes to encode.
+     ///
+     /// ```
+     /// let mut b = [0; 2];
+     ///
+     /// let result = 'ß'.encode_utf8(&mut b);
+     ///
+     /// assert_eq!(result, "ß");
+     ///
+     /// assert_eq!(result.len(), 2);
+     /// ```
+     ///
+     /// A buffer that's too small:
+     ///
+     /// ```should_panic
+     /// let mut b = [0; 1];
+     ///
+     /// // this panics
+     /// 'ß'.encode_utf8(&mut b);
+     /// ```
+     #[stable(feature = "unicode_encode_char", since = "1.15.0")]
+     #[inline]
+     pub fn encode_utf8(self, dst: &mut [u8]) -> &mut str {
+         // SAFETY: `char` is not a surrogate, so this is valid UTF-8.
+         unsafe { from_utf8_unchecked_mut(encode_utf8_raw(self as u32, dst)) }
+     }
+ 
+     /// Encodes this character as UTF-16 into the provided `u16` buffer,
+     /// and then returns the subslice of the buffer that contains the encoded character.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the buffer is not large enough.
+     /// A buffer of length 2 is large enough to encode any `char`.
+     ///
+     /// # Examples
+     ///
+     /// In both of these examples, '𝕊' takes two `u16`s to encode.
+     ///
+     /// ```
+     /// let mut b = [0; 2];
+     ///
+     /// let result = '𝕊'.encode_utf16(&mut b);
+     ///
+     /// assert_eq!(result.len(), 2);
+     /// ```
+     ///
+     /// A buffer that's too small:
+     ///
+     /// ```should_panic
+     /// let mut b = [0; 1];
+     ///
+     /// // this panics
+     /// '𝕊'.encode_utf16(&mut b);
+     /// ```
+     #[stable(feature = "unicode_encode_char", since = "1.15.0")]
+     #[inline]
+     pub fn encode_utf16(self, dst: &mut [u16]) -> &mut [u16] {
+         encode_utf16_raw(self as u32, dst)
+     }
+ 
+     /// Returns `true` if this `char` has the `Alphabetic` property.
+     ///
+     /// `Alphabetic` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and
+     /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`].
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!('a'.is_alphabetic());
+     /// assert!('京'.is_alphabetic());
+     ///
+     /// let c = '💝';
+     /// // love is many things, but it is not alphabetic
+     /// assert!(!c.is_alphabetic());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_alphabetic(self) -> bool {
+         match self {
+             'a'..='z' | 'A'..='Z' => true,
+             c => c > '\x7f' && unicode::Alphabetic(c),
+         }
+     }
+ 
+     /// Returns `true` if this `char` has the `Lowercase` property.
+     ///
+     /// `Lowercase` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and
+     /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`].
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!('a'.is_lowercase());
+     /// assert!('δ'.is_lowercase());
+     /// assert!(!'A'.is_lowercase());
+     /// assert!(!'Δ'.is_lowercase());
+     ///
+     /// // The various Chinese scripts and punctuation do not have case, and so:
+     /// assert!(!'中'.is_lowercase());
+     /// assert!(!' '.is_lowercase());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_lowercase(self) -> bool {
+         match self {
+             'a'..='z' => true,
+             c => c > '\x7f' && unicode::Lowercase(c),
+         }
+     }
+ 
+     /// Returns `true` if this `char` has the `Uppercase` property.
+     ///
+     /// `Uppercase` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and
+     /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`].
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!(!'a'.is_uppercase());
+     /// assert!(!'δ'.is_uppercase());
+     /// assert!('A'.is_uppercase());
+     /// assert!('Δ'.is_uppercase());
+     ///
+     /// // The various Chinese scripts and punctuation do not have case, and so:
+     /// assert!(!'中'.is_uppercase());
+     /// assert!(!' '.is_uppercase());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_uppercase(self) -> bool {
+         match self {
+             'A'..='Z' => true,
+             c => c > '\x7f' && unicode::Uppercase(c),
+         }
+     }
+ 
+     /// Returns `true` if this `char` has the `White_Space` property.
+     ///
+     /// `White_Space` is specified in the [Unicode Character Database][ucd] [`PropList.txt`].
+     ///
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`PropList.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/PropList.txt
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!(' '.is_whitespace());
+     ///
+     /// // a non-breaking space
+     /// assert!('\u{A0}'.is_whitespace());
+     ///
+     /// assert!(!'越'.is_whitespace());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_whitespace(self) -> bool {
+         match self {
+             ' ' | '\x09'..='\x0d' => true,
+             c => c > '\x7f' && unicode::White_Space(c),
+         }
+     }
+ 
+     /// Returns `true` if this `char` satisfies either [`is_alphabetic()`] or [`is_numeric()`].
+     ///
+     /// [`is_alphabetic()`]: #method.is_alphabetic
+     /// [`is_numeric()`]: #method.is_numeric
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!('٣'.is_alphanumeric());
+     /// assert!('7'.is_alphanumeric());
+     /// assert!('৬'.is_alphanumeric());
+     /// assert!('¾'.is_alphanumeric());
+     /// assert!('①'.is_alphanumeric());
+     /// assert!('K'.is_alphanumeric());
+     /// assert!('و'.is_alphanumeric());
+     /// assert!('藏'.is_alphanumeric());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_alphanumeric(self) -> bool {
+         self.is_alphabetic() || self.is_numeric()
+     }
+ 
+     /// Returns `true` if this `char` has the general category for control codes.
+     ///
+     /// Control codes (code points with the general category of `Cc`) are described in Chapter 4
+     /// (Character Properties) of the [Unicode Standard] and specified in the [Unicode Character
+     /// Database][ucd] [`UnicodeData.txt`].
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // U+009C, STRING TERMINATOR
+     /// assert!(''.is_control());
+     /// assert!(!'q'.is_control());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_control(self) -> bool {
+         unicode::Cc(self)
+     }
+ 
+     /// Returns `true` if this `char` has the `Grapheme_Extend` property.
+     ///
+     /// `Grapheme_Extend` is described in [Unicode Standard Annex #29 (Unicode Text
+     /// Segmentation)][uax29] and specified in the [Unicode Character Database][ucd]
+     /// [`DerivedCoreProperties.txt`].
+     ///
+     /// [uax29]: https://www.unicode.org/reports/tr29/
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt
+     #[inline]
+     pub(crate) fn is_grapheme_extended(self) -> bool {
+         unicode::Grapheme_Extend(self)
+     }
+ 
+     /// Returns `true` if this `char` has one of the general categories for numbers.
+     ///
+     /// The general categories for numbers (`Nd` for decimal digits, `Nl` for letter-like numeric
+     /// characters, and `No` for other numeric characters) are specified in the [Unicode Character
+     /// Database][ucd] [`UnicodeData.txt`].
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert!('٣'.is_numeric());
+     /// assert!('7'.is_numeric());
+     /// assert!('৬'.is_numeric());
+     /// assert!('¾'.is_numeric());
+     /// assert!('①'.is_numeric());
+     /// assert!(!'K'.is_numeric());
+     /// assert!(!'و'.is_numeric());
+     /// assert!(!'藏'.is_numeric());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn is_numeric(self) -> bool {
+         match self {
+             '0'..='9' => true,
+             c => c > '\x7f' && unicode::N(c),
+         }
+     }
+ 
+     /// Returns an iterator that yields the lowercase mapping of this `char` as one or more
+     /// `char`s.
+     ///
+     /// If this `char` does not have a lowercase mapping, the iterator yields the same `char`.
+     ///
+     /// If this `char` has a one-to-one lowercase mapping given by the [Unicode Character
+     /// Database][ucd] [`UnicodeData.txt`], the iterator yields that `char`.
+     ///
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt
+     ///
+     /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields
+     /// the `char`(s) given by [`SpecialCasing.txt`].
+     ///
+     /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt
+     ///
+     /// This operation performs an unconditional mapping without tailoring. That is, the conversion
+     /// is independent of context and language.
+     ///
+     /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in
+     /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion.
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in 'İ'.to_lowercase() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", 'İ'.to_lowercase());
+     /// ```
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("i\u{307}");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!('C'.to_lowercase().to_string(), "c");
+     ///
+     /// // Sometimes the result is more than one character:
+     /// assert_eq!('İ'.to_lowercase().to_string(), "i\u{307}");
+     ///
+     /// // Characters that do not have both uppercase and lowercase
+     /// // convert into themselves.
+     /// assert_eq!('山'.to_lowercase().to_string(), "山");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn to_lowercase(self) -> ToLowercase {
+         ToLowercase(CaseMappingIter::new(conversions::to_lower(self)))
+     }
+ 
+     /// Returns an iterator that yields the uppercase mapping of this `char` as one or more
+     /// `char`s.
+     ///
+     /// If this `char` does not have a uppercase mapping, the iterator yields the same `char`.
+     ///
+     /// If this `char` has a one-to-one uppercase mapping given by the [Unicode Character
+     /// Database][ucd] [`UnicodeData.txt`], the iterator yields that `char`.
+     ///
+     /// [ucd]: https://www.unicode.org/reports/tr44/
+     /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt
+     ///
+     /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields
+     /// the `char`(s) given by [`SpecialCasing.txt`].
+     ///
+     /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt
+     ///
+     /// This operation performs an unconditional mapping without tailoring. That is, the conversion
+     /// is independent of context and language.
+     ///
+     /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in
+     /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion.
+     ///
+     /// [Unicode Standard]: https://www.unicode.org/versions/latest/
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in 'ß'.to_uppercase() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", 'ß'.to_uppercase());
+     /// ```
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("SS");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!('c'.to_uppercase().to_string(), "C");
+     ///
+     /// // Sometimes the result is more than one character:
+     /// assert_eq!('ß'.to_uppercase().to_string(), "SS");
+     ///
+     /// // Characters that do not have both uppercase and lowercase
+     /// // convert into themselves.
+     /// assert_eq!('山'.to_uppercase().to_string(), "山");
+     /// ```
+     ///
+     /// # Note on locale
+     ///
+     /// In Turkish, the equivalent of 'i' in Latin has five forms instead of two:
+     ///
+     /// * 'Dotless': I / ı, sometimes written ï
+     /// * 'Dotted': İ / i
+     ///
+     /// Note that the lowercase dotted 'i' is the same as the Latin. Therefore:
+     ///
+     /// ```
+     /// let upper_i = 'i'.to_uppercase().to_string();
+     /// ```
+     ///
+     /// The value of `upper_i` here relies on the language of the text: if we're
+     /// in `en-US`, it should be `"I"`, but if we're in `tr_TR`, it should
+     /// be `"İ"`. `to_uppercase()` does not take this into account, and so:
+     ///
+     /// ```
+     /// let upper_i = 'i'.to_uppercase().to_string();
+     ///
+     /// assert_eq!(upper_i, "I");
+     /// ```
+     ///
+     /// holds across languages.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn to_uppercase(self) -> ToUppercase {
+         ToUppercase(CaseMappingIter::new(conversions::to_upper(self)))
+     }
+ 
+     /// Checks if the value is within the ASCII range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let ascii = 'a';
+     /// let non_ascii = '❤';
+     ///
+     /// assert!(ascii.is_ascii());
+     /// assert!(!non_ascii.is_ascii());
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[rustc_const_stable(feature = "const_ascii_methods_on_intrinsics", since = "1.32.0")]
+     #[inline]
+     pub const fn is_ascii(&self) -> bool {
+         *self as u32 <= 0x7F
+     }
+ 
+     /// Makes a copy of the value in its ASCII upper case equivalent.
+     ///
+     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To uppercase the value in-place, use [`make_ascii_uppercase`].
+     ///
+     /// To uppercase ASCII characters in addition to non-ASCII characters, use
+     /// [`to_uppercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let ascii = 'a';
+     /// let non_ascii = '❤';
+     ///
+     /// assert_eq!('A', ascii.to_ascii_uppercase());
+     /// assert_eq!('❤', non_ascii.to_ascii_uppercase());
+     /// ```
+     ///
+     /// [`make_ascii_uppercase`]: #method.make_ascii_uppercase
+     /// [`to_uppercase`]: #method.to_uppercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn to_ascii_uppercase(&self) -> char {
+         if self.is_ascii() { (*self as u8).to_ascii_uppercase() as char } else { *self }
+     }
+ 
+     /// Makes a copy of the value in its ASCII lower case equivalent.
+     ///
+     /// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To lowercase the value in-place, use [`make_ascii_lowercase`].
+     ///
+     /// To lowercase ASCII characters in addition to non-ASCII characters, use
+     /// [`to_lowercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let ascii = 'A';
+     /// let non_ascii = '❤';
+     ///
+     /// assert_eq!('a', ascii.to_ascii_lowercase());
+     /// assert_eq!('❤', non_ascii.to_ascii_lowercase());
+     /// ```
+     ///
+     /// [`make_ascii_lowercase`]: #method.make_ascii_lowercase
+     /// [`to_lowercase`]: #method.to_lowercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn to_ascii_lowercase(&self) -> char {
+         if self.is_ascii() { (*self as u8).to_ascii_lowercase() as char } else { *self }
+     }
+ 
+     /// Checks that two values are an ASCII case-insensitive match.
+     ///
+     /// Equivalent to `to_ascii_lowercase(a) == to_ascii_lowercase(b)`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let upper_a = 'A';
+     /// let lower_a = 'a';
+     /// let lower_z = 'z';
+     ///
+     /// assert!(upper_a.eq_ignore_ascii_case(&lower_a));
+     /// assert!(upper_a.eq_ignore_ascii_case(&upper_a));
+     /// assert!(!upper_a.eq_ignore_ascii_case(&lower_z));
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn eq_ignore_ascii_case(&self, other: &char) -> bool {
+         self.to_ascii_lowercase() == other.to_ascii_lowercase()
+     }
+ 
+     /// Converts this type to its ASCII upper case equivalent in-place.
+     ///
+     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new uppercased value without modifying the existing one, use
+     /// [`to_ascii_uppercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut ascii = 'a';
+     ///
+     /// ascii.make_ascii_uppercase();
+     ///
+     /// assert_eq!('A', ascii);
+     /// ```
+     ///
+     /// [`to_ascii_uppercase`]: #method.to_ascii_uppercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_uppercase(&mut self) {
+         *self = self.to_ascii_uppercase();
+     }
+ 
+     /// Converts this type to its ASCII lower case equivalent in-place.
+     ///
+     /// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new lowercased value without modifying the existing one, use
+     /// [`to_ascii_lowercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut ascii = 'A';
+     ///
+     /// ascii.make_ascii_lowercase();
+     ///
+     /// assert_eq!('a', ascii);
+     /// ```
+     ///
+     /// [`to_ascii_lowercase`]: #method.to_ascii_lowercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_lowercase(&mut self) {
+         *self = self.to_ascii_lowercase();
+     }
+ 
+     /// Checks if the value is an ASCII alphabetic character:
+     ///
+     /// - U+0041 'A' ..= U+005A 'Z', or
+     /// - U+0061 'a' ..= U+007A 'z'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(uppercase_a.is_ascii_alphabetic());
+     /// assert!(uppercase_g.is_ascii_alphabetic());
+     /// assert!(a.is_ascii_alphabetic());
+     /// assert!(g.is_ascii_alphabetic());
+     /// assert!(!zero.is_ascii_alphabetic());
+     /// assert!(!percent.is_ascii_alphabetic());
+     /// assert!(!space.is_ascii_alphabetic());
+     /// assert!(!lf.is_ascii_alphabetic());
+     /// assert!(!esc.is_ascii_alphabetic());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_alphabetic(&self) -> bool {
+         matches!(*self, 'A'..='Z' | 'a'..='z')
+     }
+ 
+     /// Checks if the value is an ASCII uppercase character:
+     /// U+0041 'A' ..= U+005A 'Z'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(uppercase_a.is_ascii_uppercase());
+     /// assert!(uppercase_g.is_ascii_uppercase());
+     /// assert!(!a.is_ascii_uppercase());
+     /// assert!(!g.is_ascii_uppercase());
+     /// assert!(!zero.is_ascii_uppercase());
+     /// assert!(!percent.is_ascii_uppercase());
+     /// assert!(!space.is_ascii_uppercase());
+     /// assert!(!lf.is_ascii_uppercase());
+     /// assert!(!esc.is_ascii_uppercase());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_uppercase(&self) -> bool {
+         matches!(*self, 'A'..='Z')
+     }
+ 
+     /// Checks if the value is an ASCII lowercase character:
+     /// U+0061 'a' ..= U+007A 'z'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(!uppercase_a.is_ascii_lowercase());
+     /// assert!(!uppercase_g.is_ascii_lowercase());
+     /// assert!(a.is_ascii_lowercase());
+     /// assert!(g.is_ascii_lowercase());
+     /// assert!(!zero.is_ascii_lowercase());
+     /// assert!(!percent.is_ascii_lowercase());
+     /// assert!(!space.is_ascii_lowercase());
+     /// assert!(!lf.is_ascii_lowercase());
+     /// assert!(!esc.is_ascii_lowercase());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_lowercase(&self) -> bool {
+         matches!(*self, 'a'..='z')
+     }
+ 
+     /// Checks if the value is an ASCII alphanumeric character:
+     ///
+     /// - U+0041 'A' ..= U+005A 'Z', or
+     /// - U+0061 'a' ..= U+007A 'z', or
+     /// - U+0030 '0' ..= U+0039 '9'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(uppercase_a.is_ascii_alphanumeric());
+     /// assert!(uppercase_g.is_ascii_alphanumeric());
+     /// assert!(a.is_ascii_alphanumeric());
+     /// assert!(g.is_ascii_alphanumeric());
+     /// assert!(zero.is_ascii_alphanumeric());
+     /// assert!(!percent.is_ascii_alphanumeric());
+     /// assert!(!space.is_ascii_alphanumeric());
+     /// assert!(!lf.is_ascii_alphanumeric());
+     /// assert!(!esc.is_ascii_alphanumeric());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_alphanumeric(&self) -> bool {
+         matches!(*self, '0'..='9' | 'A'..='Z' | 'a'..='z')
+     }
+ 
+     /// Checks if the value is an ASCII decimal digit:
+     /// U+0030 '0' ..= U+0039 '9'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(!uppercase_a.is_ascii_digit());
+     /// assert!(!uppercase_g.is_ascii_digit());
+     /// assert!(!a.is_ascii_digit());
+     /// assert!(!g.is_ascii_digit());
+     /// assert!(zero.is_ascii_digit());
+     /// assert!(!percent.is_ascii_digit());
+     /// assert!(!space.is_ascii_digit());
+     /// assert!(!lf.is_ascii_digit());
+     /// assert!(!esc.is_ascii_digit());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_digit(&self) -> bool {
+         matches!(*self, '0'..='9')
+     }
+ 
+     /// Checks if the value is an ASCII hexadecimal digit:
+     ///
+     /// - U+0030 '0' ..= U+0039 '9', or
+     /// - U+0041 'A' ..= U+0046 'F', or
+     /// - U+0061 'a' ..= U+0066 'f'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(uppercase_a.is_ascii_hexdigit());
+     /// assert!(!uppercase_g.is_ascii_hexdigit());
+     /// assert!(a.is_ascii_hexdigit());
+     /// assert!(!g.is_ascii_hexdigit());
+     /// assert!(zero.is_ascii_hexdigit());
+     /// assert!(!percent.is_ascii_hexdigit());
+     /// assert!(!space.is_ascii_hexdigit());
+     /// assert!(!lf.is_ascii_hexdigit());
+     /// assert!(!esc.is_ascii_hexdigit());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_hexdigit(&self) -> bool {
+         matches!(*self, '0'..='9' | 'A'..='F' | 'a'..='f')
+     }
+ 
+     /// Checks if the value is an ASCII punctuation character:
+     ///
+     /// - U+0021 ..= U+002F `! " # $ % & ' ( ) * + , - . /`, or
+     /// - U+003A ..= U+0040 `: ; < = > ? @`, or
+     /// - U+005B ..= U+0060 ``[ \ ] ^ _ ` ``, or
+     /// - U+007B ..= U+007E `{ | } ~`
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(!uppercase_a.is_ascii_punctuation());
+     /// assert!(!uppercase_g.is_ascii_punctuation());
+     /// assert!(!a.is_ascii_punctuation());
+     /// assert!(!g.is_ascii_punctuation());
+     /// assert!(!zero.is_ascii_punctuation());
+     /// assert!(percent.is_ascii_punctuation());
+     /// assert!(!space.is_ascii_punctuation());
+     /// assert!(!lf.is_ascii_punctuation());
+     /// assert!(!esc.is_ascii_punctuation());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_punctuation(&self) -> bool {
+         matches!(*self, '!'..='/' | ':'..='@' | '['..='`' | '{'..='~')
+     }
+ 
+     /// Checks if the value is an ASCII graphic character:
+     /// U+0021 '!' ..= U+007E '~'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(uppercase_a.is_ascii_graphic());
+     /// assert!(uppercase_g.is_ascii_graphic());
+     /// assert!(a.is_ascii_graphic());
+     /// assert!(g.is_ascii_graphic());
+     /// assert!(zero.is_ascii_graphic());
+     /// assert!(percent.is_ascii_graphic());
+     /// assert!(!space.is_ascii_graphic());
+     /// assert!(!lf.is_ascii_graphic());
+     /// assert!(!esc.is_ascii_graphic());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_graphic(&self) -> bool {
+         matches!(*self, '!'..='~')
+     }
+ 
+     /// Checks if the value is an ASCII whitespace character:
+     /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED,
+     /// U+000C FORM FEED, or U+000D CARRIAGE RETURN.
+     ///
+     /// Rust uses the WhatWG Infra Standard's [definition of ASCII
+     /// whitespace][infra-aw]. There are several other definitions in
+     /// wide use. For instance, [the POSIX locale][pct] includes
+     /// U+000B VERTICAL TAB as well as all the above characters,
+     /// but—from the very same specification—[the default rule for
+     /// "field splitting" in the Bourne shell][bfs] considers *only*
+     /// SPACE, HORIZONTAL TAB, and LINE FEED as whitespace.
+     ///
+     /// If you are writing a program that will process an existing
+     /// file format, check what that format's definition of whitespace is
+     /// before using this function.
+     ///
+     /// [infra-aw]: https://infra.spec.whatwg.org/#ascii-whitespace
+     /// [pct]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap07.html#tag_07_03_01
+     /// [bfs]: http://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#tag_18_06_05
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(!uppercase_a.is_ascii_whitespace());
+     /// assert!(!uppercase_g.is_ascii_whitespace());
+     /// assert!(!a.is_ascii_whitespace());
+     /// assert!(!g.is_ascii_whitespace());
+     /// assert!(!zero.is_ascii_whitespace());
+     /// assert!(!percent.is_ascii_whitespace());
+     /// assert!(space.is_ascii_whitespace());
+     /// assert!(lf.is_ascii_whitespace());
+     /// assert!(!esc.is_ascii_whitespace());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_whitespace(&self) -> bool {
+         matches!(*self, '\t' | '\n' | '\x0C' | '\r' | ' ')
+     }
+ 
+     /// Checks if the value is an ASCII control character:
+     /// U+0000 NUL ..= U+001F UNIT SEPARATOR, or U+007F DELETE.
+     /// Note that most ASCII whitespace characters are control
+     /// characters, but SPACE is not.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 'A';
+     /// let uppercase_g = 'G';
+     /// let a = 'a';
+     /// let g = 'g';
+     /// let zero = '0';
+     /// let percent = '%';
+     /// let space = ' ';
+     /// let lf = '\n';
+     /// let esc: char = 0x1b_u8.into();
+     ///
+     /// assert!(!uppercase_a.is_ascii_control());
+     /// assert!(!uppercase_g.is_ascii_control());
+     /// assert!(!a.is_ascii_control());
+     /// assert!(!g.is_ascii_control());
+     /// assert!(!zero.is_ascii_control());
+     /// assert!(!percent.is_ascii_control());
+     /// assert!(!space.is_ascii_control());
+     /// assert!(lf.is_ascii_control());
+     /// assert!(esc.is_ascii_control());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_control(&self) -> bool {
+         matches!(*self, '\0'..='\x1F' | '\x7F')
+     }
+ }
+ 
+ #[inline]
+ fn len_utf8(code: u32) -> usize {
+     if code < MAX_ONE_B {
+         1
+     } else if code < MAX_TWO_B {
+         2
+     } else if code < MAX_THREE_B {
+         3
+     } else {
+         4
+     }
+ }
+ 
+ /// Encodes a raw u32 value as UTF-8 into the provided byte buffer,
+ /// and then returns the subslice of the buffer that contains the encoded character.
+ ///
+ /// Unlike `char::encode_utf8`, this method also handles codepoints in the surrogate range.
+ /// (Creating a `char` in the surrogate range is UB.)
+ /// The result is valid [generalized UTF-8] but not valid UTF-8.
+ ///
+ /// [generalized UTF-8]: https://simonsapin.github.io/wtf-8/#generalized-utf8
+ ///
+ /// # Panics
+ ///
+ /// Panics if the buffer is not large enough.
+ /// A buffer of length four is large enough to encode any `char`.
+ #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")]
+ #[doc(hidden)]
+ #[inline]
+ pub fn encode_utf8_raw(code: u32, dst: &mut [u8]) -> &mut [u8] {
+     let len = len_utf8(code);
+     match (len, &mut dst[..]) {
+         (1, [a, ..]) => {
+             *a = code as u8;
+         }
+         (2, [a, b, ..]) => {
+             *a = (code >> 6 & 0x1F) as u8 | TAG_TWO_B;
+             *b = (code & 0x3F) as u8 | TAG_CONT;
+         }
+         (3, [a, b, c, ..]) => {
+             *a = (code >> 12 & 0x0F) as u8 | TAG_THREE_B;
+             *b = (code >> 6 & 0x3F) as u8 | TAG_CONT;
+             *c = (code & 0x3F) as u8 | TAG_CONT;
+         }
+         (4, [a, b, c, d, ..]) => {
+             *a = (code >> 18 & 0x07) as u8 | TAG_FOUR_B;
+             *b = (code >> 12 & 0x3F) as u8 | TAG_CONT;
+             *c = (code >> 6 & 0x3F) as u8 | TAG_CONT;
+             *d = (code & 0x3F) as u8 | TAG_CONT;
+         }
+         _ => panic!(
+             "encode_utf8: need {} bytes to encode U+{:X}, but the buffer has {}",
+             len,
+             code,
+             dst.len(),
+         ),
+     };
+     &mut dst[..len]
+ }
+ 
+ /// Encodes a raw u32 value as UTF-16 into the provided `u16` buffer,
+ /// and then returns the subslice of the buffer that contains the encoded character.
+ ///
+ /// Unlike `char::encode_utf16`, this method also handles codepoints in the surrogate range.
+ /// (Creating a `char` in the surrogate range is UB.)
+ ///
+ /// # Panics
+ ///
+ /// Panics if the buffer is not large enough.
+ /// A buffer of length 2 is large enough to encode any `char`.
+ #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")]
+ #[doc(hidden)]
+ #[inline]
+ pub fn encode_utf16_raw(mut code: u32, dst: &mut [u16]) -> &mut [u16] {
+     // SAFETY: each arm checks whether there are enough bits to write into
+     unsafe {
+         if (code & 0xFFFF) == code && !dst.is_empty() {
+             // The BMP falls through
+             *dst.get_unchecked_mut(0) = code as u16;
+             slice::from_raw_parts_mut(dst.as_mut_ptr(), 1)
+         } else if dst.len() >= 2 {
+             // Supplementary planes break into surrogates.
+             code -= 0x1_0000;
+             *dst.get_unchecked_mut(0) = 0xD800 | ((code >> 10) as u16);
+             *dst.get_unchecked_mut(1) = 0xDC00 | ((code as u16) & 0x3FF);
+             slice::from_raw_parts_mut(dst.as_mut_ptr(), 2)
+         } else {
+             panic!(
+                 "encode_utf16: need {} units to encode U+{:X}, but the buffer has {}",
+                 from_u32_unchecked(code).len_utf16(),
+                 code,
+                 dst.len(),
+             )
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/char/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/char/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/char/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/char/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,511 ----
+ //! A character type.
+ //!
+ //! The `char` type represents a single character. More specifically, since
+ //! 'character' isn't a well-defined concept in Unicode, `char` is a '[Unicode
+ //! scalar value]', which is similar to, but not the same as, a '[Unicode code
+ //! point]'.
+ //!
+ //! [Unicode scalar value]: http://www.unicode.org/glossary/#unicode_scalar_value
+ //! [Unicode code point]: http://www.unicode.org/glossary/#code_point
+ //!
+ //! This module exists for technical reasons, the primary documentation for
+ //! `char` is directly on [the `char` primitive type](../../std/primitive.char.html)
+ //! itself.
+ //!
+ //! This module is the home of the iterator implementations for the iterators
+ //! implemented on `char`, as well as some useful constants and conversion
+ //! functions that convert various types to `char`.
+ 
+ #![allow(non_snake_case)]
+ #![stable(feature = "core_char", since = "1.2.0")]
+ 
+ mod convert;
+ mod decode;
+ mod methods;
+ 
+ // stable re-exports
+ #[stable(feature = "char_from_unchecked", since = "1.5.0")]
+ pub use self::convert::from_u32_unchecked;
+ #[stable(feature = "try_from", since = "1.34.0")]
+ pub use self::convert::CharTryFromError;
+ #[stable(feature = "char_from_str", since = "1.20.0")]
+ pub use self::convert::ParseCharError;
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::convert::{from_digit, from_u32};
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ pub use self::decode::{decode_utf16, DecodeUtf16, DecodeUtf16Error};
+ #[stable(feature = "unicode_version", since = "1.45.0")]
+ pub use crate::unicode::UNICODE_VERSION;
+ 
+ // perma-unstable re-exports
+ #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")]
+ pub use self::methods::encode_utf16_raw;
+ #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")]
+ pub use self::methods::encode_utf8_raw;
+ 
+ use crate::fmt::{self, Write};
+ use crate::iter::FusedIterator;
+ 
+ // UTF-8 ranges and tags for encoding characters
+ const TAG_CONT: u8 = 0b1000_0000;
+ const TAG_TWO_B: u8 = 0b1100_0000;
+ const TAG_THREE_B: u8 = 0b1110_0000;
+ const TAG_FOUR_B: u8 = 0b1111_0000;
+ const MAX_ONE_B: u32 = 0x80;
+ const MAX_TWO_B: u32 = 0x800;
+ const MAX_THREE_B: u32 = 0x10000;
+ 
+ /*
+     Lu  Uppercase_Letter        an uppercase letter
+     Ll  Lowercase_Letter        a lowercase letter
+     Lt  Titlecase_Letter        a digraphic character, with first part uppercase
+     Lm  Modifier_Letter         a modifier letter
+     Lo  Other_Letter            other letters, including syllables and ideographs
+     Mn  Nonspacing_Mark         a nonspacing combining mark (zero advance width)
+     Mc  Spacing_Mark            a spacing combining mark (positive advance width)
+     Me  Enclosing_Mark          an enclosing combining mark
+     Nd  Decimal_Number          a decimal digit
+     Nl  Letter_Number           a letterlike numeric character
+     No  Other_Number            a numeric character of other type
+     Pc  Connector_Punctuation   a connecting punctuation mark, like a tie
+     Pd  Dash_Punctuation        a dash or hyphen punctuation mark
+     Ps  Open_Punctuation        an opening punctuation mark (of a pair)
+     Pe  Close_Punctuation       a closing punctuation mark (of a pair)
+     Pi  Initial_Punctuation     an initial quotation mark
+     Pf  Final_Punctuation       a final quotation mark
+     Po  Other_Punctuation       a punctuation mark of other type
+     Sm  Math_Symbol             a symbol of primarily mathematical use
+     Sc  Currency_Symbol         a currency sign
+     Sk  Modifier_Symbol         a non-letterlike modifier symbol
+     So  Other_Symbol            a symbol of other type
+     Zs  Space_Separator         a space character (of various non-zero widths)
+     Zl  Line_Separator          U+2028 LINE SEPARATOR only
+     Zp  Paragraph_Separator     U+2029 PARAGRAPH SEPARATOR only
+     Cc  Control                 a C0 or C1 control code
+     Cf  Format                  a format control character
+     Cs  Surrogate               a surrogate code point
+     Co  Private_Use             a private-use character
+     Cn  Unassigned              a reserved unassigned code point or a noncharacter
+ */
+ 
+ /// The highest valid code point a `char` can have.
+ ///
+ /// A [`char`] is a [Unicode Scalar Value], which means that it is a [Code
+ /// Point], but only ones within a certain range. `MAX` is the highest valid
+ /// code point that's a valid [Unicode Scalar Value].
+ ///
+ /// [Unicode Scalar Value]: http://www.unicode.org/glossary/#unicode_scalar_value
+ /// [Code Point]: http://www.unicode.org/glossary/#code_point
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX: char = char::MAX;
+ 
+ /// `U+FFFD REPLACEMENT CHARACTER` (�) is used in Unicode to represent a
+ /// decoding error.
+ ///
+ /// It can occur, for example, when giving ill-formed UTF-8 bytes to
+ /// [`String::from_utf8_lossy`](../../std/string/struct.String.html#method.from_utf8_lossy).
+ #[stable(feature = "decode_utf16", since = "1.9.0")]
+ pub const REPLACEMENT_CHARACTER: char = char::REPLACEMENT_CHARACTER;
+ 
+ /// Returns an iterator that yields the hexadecimal Unicode escape of a
+ /// character, as `char`s.
+ ///
+ /// This `struct` is created by the [`escape_unicode`] method on [`char`]. See
+ /// its documentation for more.
+ ///
+ /// [`escape_unicode`]: char::escape_unicode
+ #[derive(Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct EscapeUnicode {
+     c: char,
+     state: EscapeUnicodeState,
+ 
+     // The index of the next hex digit to be printed (0 if none),
+     // i.e., the number of remaining hex digits to be printed;
+     // increasing from the least significant digit: 0x543210
+     hex_digit_idx: usize,
+ }
+ 
+ // The enum values are ordered so that their representation is the
+ // same as the remaining length (besides the hexadecimal digits). This
+ // likely makes `len()` a single load from memory) and inline-worth.
+ #[derive(Clone, Debug)]
+ enum EscapeUnicodeState {
+     Done,
+     RightBrace,
+     Value,
+     LeftBrace,
+     Type,
+     Backslash,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Iterator for EscapeUnicode {
+     type Item = char;
+ 
+     fn next(&mut self) -> Option<char> {
+         match self.state {
+             EscapeUnicodeState::Backslash => {
+                 self.state = EscapeUnicodeState::Type;
+                 Some('\\')
+             }
+             EscapeUnicodeState::Type => {
+                 self.state = EscapeUnicodeState::LeftBrace;
+                 Some('u')
+             }
+             EscapeUnicodeState::LeftBrace => {
+                 self.state = EscapeUnicodeState::Value;
+                 Some('{')
+             }
+             EscapeUnicodeState::Value => {
+                 let hex_digit = ((self.c as u32) >> (self.hex_digit_idx * 4)) & 0xf;
+                 let c = from_digit(hex_digit, 16).unwrap();
+                 if self.hex_digit_idx == 0 {
+                     self.state = EscapeUnicodeState::RightBrace;
+                 } else {
+                     self.hex_digit_idx -= 1;
+                 }
+                 Some(c)
+             }
+             EscapeUnicodeState::RightBrace => {
+                 self.state = EscapeUnicodeState::Done;
+                 Some('}')
+             }
+             EscapeUnicodeState::Done => None,
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = self.len();
+         (n, Some(n))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     fn last(self) -> Option<char> {
+         match self.state {
+             EscapeUnicodeState::Done => None,
+ 
+             EscapeUnicodeState::RightBrace
+             | EscapeUnicodeState::Value
+             | EscapeUnicodeState::LeftBrace
+             | EscapeUnicodeState::Type
+             | EscapeUnicodeState::Backslash => Some('}'),
+         }
+     }
+ }
+ 
+ #[stable(feature = "exact_size_escape", since = "1.11.0")]
+ impl ExactSizeIterator for EscapeUnicode {
+     #[inline]
+     fn len(&self) -> usize {
+         // The match is a single memory access with no branching
+         self.hex_digit_idx
+             + match self.state {
+                 EscapeUnicodeState::Done => 0,
+                 EscapeUnicodeState::RightBrace => 1,
+                 EscapeUnicodeState::Value => 2,
+                 EscapeUnicodeState::LeftBrace => 3,
+                 EscapeUnicodeState::Type => 4,
+                 EscapeUnicodeState::Backslash => 5,
+             }
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for EscapeUnicode {}
+ 
+ #[stable(feature = "char_struct_display", since = "1.16.0")]
+ impl fmt::Display for EscapeUnicode {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         for c in self.clone() {
+             f.write_char(c)?;
+         }
+         Ok(())
+     }
+ }
+ 
+ /// An iterator that yields the literal escape code of a `char`.
+ ///
+ /// This `struct` is created by the [`escape_default`] method on [`char`]. See
+ /// its documentation for more.
+ ///
+ /// [`escape_default`]: char::escape_default
+ #[derive(Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct EscapeDefault {
+     state: EscapeDefaultState,
+ }
+ 
+ #[derive(Clone, Debug)]
+ enum EscapeDefaultState {
+     Done,
+     Char(char),
+     Backslash(char),
+     Unicode(EscapeUnicode),
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Iterator for EscapeDefault {
+     type Item = char;
+ 
+     fn next(&mut self) -> Option<char> {
+         match self.state {
+             EscapeDefaultState::Backslash(c) => {
+                 self.state = EscapeDefaultState::Char(c);
+                 Some('\\')
+             }
+             EscapeDefaultState::Char(c) => {
+                 self.state = EscapeDefaultState::Done;
+                 Some(c)
+             }
+             EscapeDefaultState::Done => None,
+             EscapeDefaultState::Unicode(ref mut iter) => iter.next(),
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = self.len();
+         (n, Some(n))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     fn nth(&mut self, n: usize) -> Option<char> {
+         match self.state {
+             EscapeDefaultState::Backslash(c) if n == 0 => {
+                 self.state = EscapeDefaultState::Char(c);
+                 Some('\\')
+             }
+             EscapeDefaultState::Backslash(c) if n == 1 => {
+                 self.state = EscapeDefaultState::Done;
+                 Some(c)
+             }
+             EscapeDefaultState::Backslash(_) => {
+                 self.state = EscapeDefaultState::Done;
+                 None
+             }
+             EscapeDefaultState::Char(c) => {
+                 self.state = EscapeDefaultState::Done;
+ 
+                 if n == 0 { Some(c) } else { None }
+             }
+             EscapeDefaultState::Done => None,
+             EscapeDefaultState::Unicode(ref mut i) => i.nth(n),
+         }
+     }
+ 
+     fn last(self) -> Option<char> {
+         match self.state {
+             EscapeDefaultState::Unicode(iter) => iter.last(),
+             EscapeDefaultState::Done => None,
+             EscapeDefaultState::Backslash(c) | EscapeDefaultState::Char(c) => Some(c),
+         }
+     }
+ }
+ 
+ #[stable(feature = "exact_size_escape", since = "1.11.0")]
+ impl ExactSizeIterator for EscapeDefault {
+     fn len(&self) -> usize {
+         match self.state {
+             EscapeDefaultState::Done => 0,
+             EscapeDefaultState::Char(_) => 1,
+             EscapeDefaultState::Backslash(_) => 2,
+             EscapeDefaultState::Unicode(ref iter) => iter.len(),
+         }
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for EscapeDefault {}
+ 
+ #[stable(feature = "char_struct_display", since = "1.16.0")]
+ impl fmt::Display for EscapeDefault {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         for c in self.clone() {
+             f.write_char(c)?;
+         }
+         Ok(())
+     }
+ }
+ 
+ /// An iterator that yields the literal escape code of a `char`.
+ ///
+ /// This `struct` is created by the [`escape_debug`] method on [`char`]. See its
+ /// documentation for more.
+ ///
+ /// [`escape_debug`]: char::escape_debug
+ #[stable(feature = "char_escape_debug", since = "1.20.0")]
+ #[derive(Clone, Debug)]
+ pub struct EscapeDebug(EscapeDefault);
+ 
+ #[stable(feature = "char_escape_debug", since = "1.20.0")]
+ impl Iterator for EscapeDebug {
+     type Item = char;
+     fn next(&mut self) -> Option<char> {
+         self.0.next()
+     }
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.0.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "char_escape_debug", since = "1.20.0")]
+ impl ExactSizeIterator for EscapeDebug {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for EscapeDebug {}
+ 
+ #[stable(feature = "char_escape_debug", since = "1.20.0")]
+ impl fmt::Display for EscapeDebug {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Display::fmt(&self.0, f)
+     }
+ }
+ 
+ /// Returns an iterator that yields the lowercase equivalent of a `char`.
+ ///
+ /// This `struct` is created by the [`to_lowercase`] method on [`char`]. See
+ /// its documentation for more.
+ ///
+ /// [`to_lowercase`]: char::to_lowercase
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Debug, Clone)]
+ pub struct ToLowercase(CaseMappingIter);
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Iterator for ToLowercase {
+     type Item = char;
+     fn next(&mut self) -> Option<char> {
+         self.0.next()
+     }
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.0.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for ToLowercase {}
+ 
+ #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")]
+ impl ExactSizeIterator for ToLowercase {}
+ 
+ /// Returns an iterator that yields the uppercase equivalent of a `char`.
+ ///
+ /// This `struct` is created by the [`to_uppercase`] method on [`char`]. See
+ /// its documentation for more.
+ ///
+ /// [`to_uppercase`]: char::to_uppercase
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Debug, Clone)]
+ pub struct ToUppercase(CaseMappingIter);
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Iterator for ToUppercase {
+     type Item = char;
+     fn next(&mut self) -> Option<char> {
+         self.0.next()
+     }
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.0.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for ToUppercase {}
+ 
+ #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")]
+ impl ExactSizeIterator for ToUppercase {}
+ 
+ #[derive(Debug, Clone)]
+ enum CaseMappingIter {
+     Three(char, char, char),
+     Two(char, char),
+     One(char),
+     Zero,
+ }
+ 
+ impl CaseMappingIter {
+     fn new(chars: [char; 3]) -> CaseMappingIter {
+         if chars[2] == '\0' {
+             if chars[1] == '\0' {
+                 CaseMappingIter::One(chars[0]) // Including if chars[0] == '\0'
+             } else {
+                 CaseMappingIter::Two(chars[0], chars[1])
+             }
+         } else {
+             CaseMappingIter::Three(chars[0], chars[1], chars[2])
+         }
+     }
+ }
+ 
+ impl Iterator for CaseMappingIter {
+     type Item = char;
+     fn next(&mut self) -> Option<char> {
+         match *self {
+             CaseMappingIter::Three(a, b, c) => {
+                 *self = CaseMappingIter::Two(b, c);
+                 Some(a)
+             }
+             CaseMappingIter::Two(b, c) => {
+                 *self = CaseMappingIter::One(c);
+                 Some(b)
+             }
+             CaseMappingIter::One(c) => {
+                 *self = CaseMappingIter::Zero;
+                 Some(c)
+             }
+             CaseMappingIter::Zero => None,
+         }
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let size = match self {
+             CaseMappingIter::Three(..) => 3,
+             CaseMappingIter::Two(..) => 2,
+             CaseMappingIter::One(_) => 1,
+             CaseMappingIter::Zero => 0,
+         };
+         (size, Some(size))
+     }
+ }
+ 
+ impl fmt::Display for CaseMappingIter {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         match *self {
+             CaseMappingIter::Three(a, b, c) => {
+                 f.write_char(a)?;
+                 f.write_char(b)?;
+                 f.write_char(c)
+             }
+             CaseMappingIter::Two(b, c) => {
+                 f.write_char(b)?;
+                 f.write_char(c)
+             }
+             CaseMappingIter::One(c) => f.write_char(c),
+             CaseMappingIter::Zero => Ok(()),
+         }
+     }
+ }
+ 
+ #[stable(feature = "char_struct_display", since = "1.16.0")]
+ impl fmt::Display for ToLowercase {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Display::fmt(&self.0, f)
+     }
+ }
+ 
+ #[stable(feature = "char_struct_display", since = "1.16.0")]
+ impl fmt::Display for ToUppercase {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Display::fmt(&self.0, f)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/clone.rs gcc-16-20251102/libgrust/rustc-lib/core/src/clone.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/clone.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/clone.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,232 ----
+ //! The `Clone` trait for types that cannot be 'implicitly copied'.
+ //!
+ //! In Rust, some simple types are "implicitly copyable" and when you
+ //! assign them or pass them as arguments, the receiver will get a copy,
+ //! leaving the original value in place. These types do not require
+ //! allocation to copy and do not have finalizers (i.e., they do not
+ //! contain owned boxes or implement [`Drop`]), so the compiler considers
+ //! them cheap and safe to copy. For other types copies must be made
+ //! explicitly, by convention implementing the [`Clone`] trait and calling
+ //! the [`clone`] method.
+ //!
+ //! [`clone`]: Clone::clone
+ //!
+ //! Basic usage example:
+ //!
+ //! ```
+ //! let s = String::new(); // String type implements Clone
+ //! let copy = s.clone(); // so we can clone it
+ //! ```
+ //!
+ //! To easily implement the Clone trait, you can also use
+ //! `#[derive(Clone)]`. Example:
+ //!
+ //! ```
+ //! #[derive(Clone)] // we add the Clone trait to Morpheus struct
+ //! struct Morpheus {
+ //!    blue_pill: f32,
+ //!    red_pill: i64,
+ //! }
+ //!
+ //! fn main() {
+ //!    let f = Morpheus { blue_pill: 0.0, red_pill: 0 };
+ //!    let copy = f.clone(); // and now we can clone it!
+ //! }
+ //! ```
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ /// A common trait for the ability to explicitly duplicate an object.
+ ///
+ /// Differs from [`Copy`] in that [`Copy`] is implicit and extremely inexpensive, while
+ /// `Clone` is always explicit and may or may not be expensive. In order to enforce
+ /// these characteristics, Rust does not allow you to reimplement [`Copy`], but you
+ /// may reimplement `Clone` and run arbitrary code.
+ ///
+ /// Since `Clone` is more general than [`Copy`], you can automatically make anything
+ /// [`Copy`] be `Clone` as well.
+ ///
+ /// ## Derivable
+ ///
+ /// This trait can be used with `#[derive]` if all fields are `Clone`. The `derive`d
+ /// implementation of [`Clone`] calls [`clone`] on each field.
+ ///
+ /// [`clone`]: Clone::clone
+ ///
+ /// For a generic struct, `#[derive]` implements `Clone` conditionally by adding bound `Clone` on
+ /// generic parameters.
+ ///
+ /// ```
+ /// // `derive` implements Clone for Reading<T> when T is Clone.
+ /// #[derive(Clone)]
+ /// struct Reading<T> {
+ ///     frequency: T,
+ /// }
+ /// ```
+ ///
+ /// ## How can I implement `Clone`?
+ ///
+ /// Types that are [`Copy`] should have a trivial implementation of `Clone`. More formally:
+ /// if `T: Copy`, `x: T`, and `y: &T`, then `let x = y.clone();` is equivalent to `let x = *y;`.
+ /// Manual implementations should be careful to uphold this invariant; however, unsafe code
+ /// must not rely on it to ensure memory safety.
+ ///
+ /// An example is a generic struct holding a function pointer. In this case, the
+ /// implementation of `Clone` cannot be `derive`d, but can be implemented as:
+ ///
+ /// ```
+ /// struct Generate<T>(fn() -> T);
+ ///
+ /// impl<T> Copy for Generate<T> {}
+ ///
+ /// impl<T> Clone for Generate<T> {
+ ///     fn clone(&self) -> Self {
+ ///         *self
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// ## Additional implementors
+ ///
+ /// In addition to the [implementors listed below][impls],
+ /// the following types also implement `Clone`:
+ ///
+ /// * Function item types (i.e., the distinct types defined for each function)
+ /// * Function pointer types (e.g., `fn() -> i32`)
+ /// * Array types, for all sizes, if the item type also implements `Clone` (e.g., `[i32; 123456]`)
+ /// * Tuple types, if each component also implements `Clone` (e.g., `()`, `(i32, bool)`)
+ /// * Closure types, if they capture no value from the environment
+ ///   or if all such captured values implement `Clone` themselves.
+ ///   Note that variables captured by shared reference always implement `Clone`
+ ///   (even if the referent doesn't),
+ ///   while variables captured by mutable reference never implement `Clone`.
+ ///
+ /// [impls]: #implementors
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[lang = "clone"]
+ pub trait Clone: Sized {
+     /// Returns a copy of the value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let hello = "Hello"; // &str implements Clone
+     ///
+     /// assert_eq!("Hello", hello.clone());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[must_use = "cloning is often expensive and is not expected to have side effects"]
+     fn clone(&self) -> Self;
+ 
+     /// Performs copy-assignment from `source`.
+     ///
+     /// `a.clone_from(&b)` is equivalent to `a = b.clone()` in functionality,
+     /// but can be overridden to reuse the resources of `a` to avoid unnecessary
+     /// allocations.
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn clone_from(&mut self, source: &Self) {
+         *self = source.clone()
+     }
+ }
+ 
+ /// Derive macro generating an impl of the trait `Clone`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics, derive_clone_copy)]
+ pub macro Clone($item:item) {
+     /* compiler built-in */
+ }
+ 
+ // FIXME(aburka): these structs are used solely by #[derive] to
+ // assert that every component of a type implements Clone or Copy.
+ //
+ // These structs should never appear in user code.
+ #[doc(hidden)]
+ #[allow(missing_debug_implementations)]
+ #[unstable(
+     feature = "derive_clone_copy",
+     reason = "deriving hack, should not be public",
+     issue = "none"
+ )]
+ pub struct AssertParamIsClone<T: Clone + ?Sized> {
+     _field: crate::marker::PhantomData<T>,
+ }
+ #[doc(hidden)]
+ #[allow(missing_debug_implementations)]
+ #[unstable(
+     feature = "derive_clone_copy",
+     reason = "deriving hack, should not be public",
+     issue = "none"
+ )]
+ pub struct AssertParamIsCopy<T: Copy + ?Sized> {
+     _field: crate::marker::PhantomData<T>,
+ }
+ 
+ /// Implementations of `Clone` for primitive types.
+ ///
+ /// Implementations that cannot be described in Rust
+ /// are implemented in `traits::SelectionContext::copy_clone_conditions()`
+ /// in `rustc_trait_selection`.
+ mod impls {
+ 
+     use super::Clone;
+ 
+     macro_rules! impl_clone {
+         ($($t:ty)*) => {
+             $(
+                 #[stable(feature = "rust1", since = "1.0.0")]
+                 impl Clone for $t {
+                     #[inline]
+                     fn clone(&self) -> Self {
+                         *self
+                     }
+                 }
+             )*
+         }
+     }
+ 
+     impl_clone! {
+         usize u8 u16 u32 u64 u128
+         isize i8 i16 i32 i64 i128
+         f32 f64
+         bool char
+     }
+ 
+     #[unstable(feature = "never_type", issue = "35121")]
+     impl Clone for ! {
+         #[inline]
+         fn clone(&self) -> Self {
+             *self
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Clone for *const T {
+         #[inline]
+         fn clone(&self) -> Self {
+             *self
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Clone for *mut T {
+         #[inline]
+         fn clone(&self) -> Self {
+             *self
+         }
+     }
+ 
+     /// Shared references can be cloned, but mutable references *cannot*!
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Clone for &T {
+         #[inline]
+         fn clone(&self) -> Self {
+             *self
+         }
+     }
+ 
+     /// Shared references can be cloned, but mutable references *cannot*!
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> !Clone for &mut T {}
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/cmp.rs gcc-16-20251102/libgrust/rustc-lib/core/src/cmp.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/cmp.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/cmp.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1355 ----
+ //! Functionality for ordering and comparison.
+ //!
+ //! This module contains various tools for ordering and comparing values. In
+ //! summary:
+ //!
+ //! * [`Eq`] and [`PartialEq`] are traits that allow you to define total and
+ //!   partial equality between values, respectively. Implementing them overloads
+ //!   the `==` and `!=` operators.
+ //! * [`Ord`] and [`PartialOrd`] are traits that allow you to define total and
+ //!   partial orderings between values, respectively. Implementing them overloads
+ //!   the `<`, `<=`, `>`, and `>=` operators.
+ //! * [`Ordering`] is an enum returned by the main functions of [`Ord`] and
+ //!   [`PartialOrd`], and describes an ordering.
+ //! * [`Reverse`] is a struct that allows you to easily reverse an ordering.
+ //! * [`max`] and [`min`] are functions that build off of [`Ord`] and allow you
+ //!   to find the maximum or minimum of two values.
+ //!
+ //! For more details, see the respective documentation of each item in the list.
+ //!
+ //! [`max`]: Ord::max
+ //! [`min`]: Ord::min
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use self::Ordering::*;
+ 
+ /// Trait for equality comparisons which are [partial equivalence
+ /// relations](https://en.wikipedia.org/wiki/Partial_equivalence_relation).
+ ///
+ /// This trait allows for partial equality, for types that do not have a full
+ /// equivalence relation. For example, in floating point numbers `NaN != NaN`,
+ /// so floating point types implement `PartialEq` but not [`Eq`].
+ ///
+ /// Formally, the equality must be (for all `a`, `b` and `c`):
+ ///
+ /// - symmetric: `a == b` implies `b == a`; and
+ /// - transitive: `a == b` and `b == c` implies `a == c`.
+ ///
+ /// Note that these requirements mean that the trait itself must be implemented
+ /// symmetrically and transitively: if `T: PartialEq<U>` and `U: PartialEq<V>`
+ /// then `U: PartialEq<T>` and `T: PartialEq<V>`.
+ ///
+ /// ## Derivable
+ ///
+ /// This trait can be used with `#[derive]`. When `derive`d on structs, two
+ /// instances are equal if all fields are equal, and not equal if any fields
+ /// are not equal. When `derive`d on enums, each variant is equal to itself
+ /// and not equal to the other variants.
+ ///
+ /// ## How can I implement `PartialEq`?
+ ///
+ /// `PartialEq` only requires the [`eq`] method to be implemented; [`ne`] is defined
+ /// in terms of it by default. Any manual implementation of [`ne`] *must* respect
+ /// the rule that [`eq`] is a strict inverse of [`ne`]; that is, `!(a == b)` if and
+ /// only if `a != b`.
+ ///
+ /// Implementations of `PartialEq`, [`PartialOrd`], and [`Ord`] *must* agree with
+ /// each other. It's easy to accidentally make them disagree by deriving some
+ /// of the traits and manually implementing others.
+ ///
+ /// An example implementation for a domain in which two books are considered
+ /// the same book if their ISBN matches, even if the formats differ:
+ ///
+ /// ```
+ /// enum BookFormat {
+ ///     Paperback,
+ ///     Hardback,
+ ///     Ebook,
+ /// }
+ ///
+ /// struct Book {
+ ///     isbn: i32,
+ ///     format: BookFormat,
+ /// }
+ ///
+ /// impl PartialEq for Book {
+ ///     fn eq(&self, other: &Self) -> bool {
+ ///         self.isbn == other.isbn
+ ///     }
+ /// }
+ ///
+ /// let b1 = Book { isbn: 3, format: BookFormat::Paperback };
+ /// let b2 = Book { isbn: 3, format: BookFormat::Ebook };
+ /// let b3 = Book { isbn: 10, format: BookFormat::Paperback };
+ ///
+ /// assert!(b1 == b2);
+ /// assert!(b1 != b3);
+ /// ```
+ ///
+ /// ## How can I compare two different types?
+ ///
+ /// The type you can compare with is controlled by `PartialEq`'s type parameter.
+ /// For example, let's tweak our previous code a bit:
+ ///
+ /// ```
+ /// // The derive implements <BookFormat> == <BookFormat> comparisons
+ /// #[derive(PartialEq)]
+ /// enum BookFormat {
+ ///     Paperback,
+ ///     Hardback,
+ ///     Ebook,
+ /// }
+ ///
+ /// struct Book {
+ ///     isbn: i32,
+ ///     format: BookFormat,
+ /// }
+ ///
+ /// // Implement <Book> == <BookFormat> comparisons
+ /// impl PartialEq<BookFormat> for Book {
+ ///     fn eq(&self, other: &BookFormat) -> bool {
+ ///         self.format == *other
+ ///     }
+ /// }
+ ///
+ /// // Implement <BookFormat> == <Book> comparisons
+ /// impl PartialEq<Book> for BookFormat {
+ ///     fn eq(&self, other: &Book) -> bool {
+ ///         *self == other.format
+ ///     }
+ /// }
+ ///
+ /// let b1 = Book { isbn: 3, format: BookFormat::Paperback };
+ ///
+ /// assert!(b1 == BookFormat::Paperback);
+ /// assert!(BookFormat::Ebook != b1);
+ /// ```
+ ///
+ /// By changing `impl PartialEq for Book` to `impl PartialEq<BookFormat> for Book`,
+ /// we allow `BookFormat`s to be compared with `Book`s.
+ ///
+ /// A comparison like the one above, which ignores some fields of the struct,
+ /// can be dangerous. It can easily lead to an unintended violation of the
+ /// requirements for a partial equivalence relation. For example, if we kept
+ /// the above implementation of `PartialEq<Book>` for `BookFormat` and added an
+ /// implementation of `PartialEq<Book>` for `Book` (either via a `#[derive]` or
+ /// via the manual implementation from the first example) then the result would
+ /// violate transitivity:
+ ///
+ /// ```should_panic
+ /// #[derive(PartialEq)]
+ /// enum BookFormat {
+ ///     Paperback,
+ ///     Hardback,
+ ///     Ebook,
+ /// }
+ ///
+ /// #[derive(PartialEq)]
+ /// struct Book {
+ ///     isbn: i32,
+ ///     format: BookFormat,
+ /// }
+ ///
+ /// impl PartialEq<BookFormat> for Book {
+ ///     fn eq(&self, other: &BookFormat) -> bool {
+ ///         self.format == *other
+ ///     }
+ /// }
+ ///
+ /// impl PartialEq<Book> for BookFormat {
+ ///     fn eq(&self, other: &Book) -> bool {
+ ///         *self == other.format
+ ///     }
+ /// }
+ ///
+ /// fn main() {
+ ///     let b1 = Book { isbn: 1, format: BookFormat::Paperback };
+ ///     let b2 = Book { isbn: 2, format: BookFormat::Paperback };
+ ///
+ ///     assert!(b1 == BookFormat::Paperback);
+ ///     assert!(BookFormat::Paperback == b2);
+ ///
+ ///     // The following should hold by transitivity but doesn't.
+ ///     assert!(b1 == b2); // <-- PANICS
+ /// }
+ /// ```
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let x: u32 = 0;
+ /// let y: u32 = 1;
+ ///
+ /// assert_eq!(x == y, false);
+ /// assert_eq!(x.eq(&y), false);
+ /// ```
+ ///
+ /// [`eq`]: PartialEq::eq
+ /// [`ne`]: PartialEq::ne
+ #[lang = "eq"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(alias = "==")]
+ #[doc(alias = "!=")]
+ #[rustc_on_unimplemented(
+     message = "can't compare `{Self}` with `{Rhs}`",
+     label = "no implementation for `{Self} == {Rhs}`"
+ )]
+ pub trait PartialEq<Rhs: ?Sized = Self> {
+     /// This method tests for `self` and `other` values to be equal, and is used
+     /// by `==`.
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn eq(&self, other: &Rhs) -> bool;
+ 
+     /// This method tests for `!=`.
+     #[inline]
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn ne(&self, other: &Rhs) -> bool {
+         !self.eq(other)
+     }
+ }
+ 
+ /// Derive macro generating an impl of the trait `PartialEq`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics, structural_match)]
+ pub macro PartialEq($item:item) {
+     /* compiler built-in */
+ }
+ 
+ /// Trait for equality comparisons which are [equivalence relations](
+ /// https://en.wikipedia.org/wiki/Equivalence_relation).
+ ///
+ /// This means, that in addition to `a == b` and `a != b` being strict inverses, the equality must
+ /// be (for all `a`, `b` and `c`):
+ ///
+ /// - reflexive: `a == a`;
+ /// - symmetric: `a == b` implies `b == a`; and
+ /// - transitive: `a == b` and `b == c` implies `a == c`.
+ ///
+ /// This property cannot be checked by the compiler, and therefore `Eq` implies
+ /// [`PartialEq`], and has no extra methods.
+ ///
+ /// ## Derivable
+ ///
+ /// This trait can be used with `#[derive]`. When `derive`d, because `Eq` has
+ /// no extra methods, it is only informing the compiler that this is an
+ /// equivalence relation rather than a partial equivalence relation. Note that
+ /// the `derive` strategy requires all fields are `Eq`, which isn't
+ /// always desired.
+ ///
+ /// ## How can I implement `Eq`?
+ ///
+ /// If you cannot use the `derive` strategy, specify that your type implements
+ /// `Eq`, which has no methods:
+ ///
+ /// ```
+ /// enum BookFormat { Paperback, Hardback, Ebook }
+ /// struct Book {
+ ///     isbn: i32,
+ ///     format: BookFormat,
+ /// }
+ /// impl PartialEq for Book {
+ ///     fn eq(&self, other: &Self) -> bool {
+ ///         self.isbn == other.isbn
+ ///     }
+ /// }
+ /// impl Eq for Book {}
+ /// ```
+ #[doc(alias = "==")]
+ #[doc(alias = "!=")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Eq: PartialEq<Self> {
+     // this method is used solely by #[deriving] to assert
+     // that every component of a type implements #[deriving]
+     // itself, the current deriving infrastructure means doing this
+     // assertion without using a method on this trait is nearly
+     // impossible.
+     //
+     // This should never be implemented by hand.
+     #[doc(hidden)]
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn assert_receiver_is_total_eq(&self) {}
+ }
+ 
+ /// Derive macro generating an impl of the trait `Eq`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics, derive_eq, structural_match)]
+ pub macro Eq($item:item) {
+     /* compiler built-in */
+ }
+ 
+ // FIXME: this struct is used solely by #[derive] to
+ // assert that every component of a type implements Eq.
+ //
+ // This struct should never appear in user code.
+ #[doc(hidden)]
+ #[allow(missing_debug_implementations)]
+ #[unstable(feature = "derive_eq", reason = "deriving hack, should not be public", issue = "none")]
+ pub struct AssertParamIsEq<T: Eq + ?Sized> {
+     _field: crate::marker::PhantomData<T>,
+ }
+ 
+ /// An `Ordering` is the result of a comparison between two values.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::cmp::Ordering;
+ ///
+ /// let result = 1.cmp(&2);
+ /// assert_eq!(Ordering::Less, result);
+ ///
+ /// let result = 1.cmp(&1);
+ /// assert_eq!(Ordering::Equal, result);
+ ///
+ /// let result = 2.cmp(&1);
+ /// assert_eq!(Ordering::Greater, result);
+ /// ```
+ #[derive(Clone, Copy, PartialEq, Debug, Hash)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub enum Ordering {
+     /// An ordering where a compared value is less than another.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Less = -1,
+     /// An ordering where a compared value is equal to another.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Equal = 0,
+     /// An ordering where a compared value is greater than another.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Greater = 1,
+ }
+ 
+ impl Ordering {
+     /// Reverses the `Ordering`.
+     ///
+     /// * `Less` becomes `Greater`.
+     /// * `Greater` becomes `Less`.
+     /// * `Equal` becomes `Equal`.
+     ///
+     /// # Examples
+     ///
+     /// Basic behavior:
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// assert_eq!(Ordering::Less.reverse(), Ordering::Greater);
+     /// assert_eq!(Ordering::Equal.reverse(), Ordering::Equal);
+     /// assert_eq!(Ordering::Greater.reverse(), Ordering::Less);
+     /// ```
+     ///
+     /// This method can be used to reverse a comparison:
+     ///
+     /// ```
+     /// let data: &mut [_] = &mut [2, 10, 5, 8];
+     ///
+     /// // sort the array from largest to smallest.
+     /// data.sort_by(|a, b| a.cmp(b).reverse());
+     ///
+     /// let b: &mut [_] = &mut [10, 8, 5, 2];
+     /// assert!(data == b);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[rustc_const_stable(feature = "const_ordering", since = "1.48.0")]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn reverse(self) -> Ordering {
+         match self {
+             Less => Greater,
+             Equal => Equal,
+             Greater => Less,
+         }
+     }
+ 
+     /// Chains two orderings.
+     ///
+     /// Returns `self` when it's not `Equal`. Otherwise returns `other`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// let result = Ordering::Equal.then(Ordering::Less);
+     /// assert_eq!(result, Ordering::Less);
+     ///
+     /// let result = Ordering::Less.then(Ordering::Equal);
+     /// assert_eq!(result, Ordering::Less);
+     ///
+     /// let result = Ordering::Less.then(Ordering::Greater);
+     /// assert_eq!(result, Ordering::Less);
+     ///
+     /// let result = Ordering::Equal.then(Ordering::Equal);
+     /// assert_eq!(result, Ordering::Equal);
+     ///
+     /// let x: (i64, i64, i64) = (1, 2, 7);
+     /// let y: (i64, i64, i64) = (1, 5, 3);
+     /// let result = x.0.cmp(&y.0).then(x.1.cmp(&y.1)).then(x.2.cmp(&y.2));
+     ///
+     /// assert_eq!(result, Ordering::Less);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[rustc_const_stable(feature = "const_ordering", since = "1.48.0")]
+     #[stable(feature = "ordering_chaining", since = "1.17.0")]
+     pub const fn then(self, other: Ordering) -> Ordering {
+         match self {
+             Equal => other,
+             _ => self,
+         }
+     }
+ 
+     /// Chains the ordering with the given function.
+     ///
+     /// Returns `self` when it's not `Equal`. Otherwise calls `f` and returns
+     /// the result.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// let result = Ordering::Equal.then_with(|| Ordering::Less);
+     /// assert_eq!(result, Ordering::Less);
+     ///
+     /// let result = Ordering::Less.then_with(|| Ordering::Equal);
+     /// assert_eq!(result, Ordering::Less);
+     ///
+     /// let result = Ordering::Less.then_with(|| Ordering::Greater);
+     /// assert_eq!(result, Ordering::Less);
+     ///
+     /// let result = Ordering::Equal.then_with(|| Ordering::Equal);
+     /// assert_eq!(result, Ordering::Equal);
+     ///
+     /// let x: (i64, i64, i64) = (1, 2, 7);
+     /// let y: (i64, i64, i64)  = (1, 5, 3);
+     /// let result = x.0.cmp(&y.0).then_with(|| x.1.cmp(&y.1)).then_with(|| x.2.cmp(&y.2));
+     ///
+     /// assert_eq!(result, Ordering::Less);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[stable(feature = "ordering_chaining", since = "1.17.0")]
+     pub fn then_with<F: FnOnce() -> Ordering>(self, f: F) -> Ordering {
+         match self {
+             Equal => f(),
+             _ => self,
+         }
+     }
+ }
+ 
+ /// A helper struct for reverse ordering.
+ ///
+ /// This struct is a helper to be used with functions like [`Vec::sort_by_key`] and
+ /// can be used to reverse order a part of a key.
+ ///
+ /// [`Vec::sort_by_key`]: ../../std/vec/struct.Vec.html#method.sort_by_key
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::cmp::Reverse;
+ ///
+ /// let mut v = vec![1, 2, 3, 4, 5, 6];
+ /// v.sort_by_key(|&num| (num > 3, Reverse(num)));
+ /// assert_eq!(v, vec![3, 2, 1, 6, 5, 4]);
+ /// ```
+ #[derive(PartialEq, Eq, Debug, Copy, Clone, Default, Hash)]
+ #[stable(feature = "reverse_cmp_key", since = "1.19.0")]
+ pub struct Reverse<T>(#[stable(feature = "reverse_cmp_key", since = "1.19.0")] pub T);
+ 
+ #[stable(feature = "reverse_cmp_key", since = "1.19.0")]
+ impl<T: PartialOrd> PartialOrd for Reverse<T> {
+     #[inline]
+     fn partial_cmp(&self, other: &Reverse<T>) -> Option<Ordering> {
+         other.0.partial_cmp(&self.0)
+     }
+ 
+     #[inline]
+     fn lt(&self, other: &Self) -> bool {
+         other.0 < self.0
+     }
+     #[inline]
+     fn le(&self, other: &Self) -> bool {
+         other.0 <= self.0
+     }
+     #[inline]
+     fn gt(&self, other: &Self) -> bool {
+         other.0 > self.0
+     }
+     #[inline]
+     fn ge(&self, other: &Self) -> bool {
+         other.0 >= self.0
+     }
+ }
+ 
+ #[stable(feature = "reverse_cmp_key", since = "1.19.0")]
+ impl<T: Ord> Ord for Reverse<T> {
+     #[inline]
+     fn cmp(&self, other: &Reverse<T>) -> Ordering {
+         other.0.cmp(&self.0)
+     }
+ }
+ 
+ /// Trait for types that form a [total order](https://en.wikipedia.org/wiki/Total_order).
+ ///
+ /// An order is a total order if it is (for all `a`, `b` and `c`):
+ ///
+ /// - total and asymmetric: exactly one of `a < b`, `a == b` or `a > b` is true; and
+ /// - transitive, `a < b` and `b < c` implies `a < c`. The same must hold for both `==` and `>`.
+ ///
+ /// ## Derivable
+ ///
+ /// This trait can be used with `#[derive]`. When `derive`d on structs, it will produce a
+ /// [lexicographic](https://en.wikipedia.org/wiki/Lexicographic_order) ordering based on the top-to-bottom declaration order of the struct's members.
+ /// When `derive`d on enums, variants are ordered by their top-to-bottom discriminant order.
+ ///
+ /// ## Lexicographical comparison
+ ///
+ /// Lexicographical comparison is an operation with the following properties:
+ ///  - Two sequences are compared element by element.
+ ///  - The first mismatching element defines which sequence is lexicographically less or greater than the other.
+ ///  - If one sequence is a prefix of another, the shorter sequence is lexicographically less than the other.
+ ///  - If two sequence have equivalent elements and are of the same length, then the sequences are lexicographically equal.
+ ///  - An empty sequence is lexicographically less than any non-empty sequence.
+ ///  - Two empty sequences are lexicographically equal.
+ ///
+ /// ## How can I implement `Ord`?
+ ///
+ /// `Ord` requires that the type also be [`PartialOrd`] and [`Eq`] (which requires [`PartialEq`]).
+ ///
+ /// Then you must define an implementation for [`cmp`]. You may find it useful to use
+ /// [`cmp`] on your type's fields.
+ ///
+ /// Implementations of [`PartialEq`], [`PartialOrd`], and `Ord` *must*
+ /// agree with each other. That is, `a.cmp(b) == Ordering::Equal` if
+ /// and only if `a == b` and `Some(a.cmp(b)) == a.partial_cmp(b)` for
+ /// all `a` and `b`. It's easy to accidentally make them disagree by
+ /// deriving some of the traits and manually implementing others.
+ ///
+ /// Here's an example where you want to sort people by height only, disregarding `id`
+ /// and `name`:
+ ///
+ /// ```
+ /// use std::cmp::Ordering;
+ ///
+ /// #[derive(Eq)]
+ /// struct Person {
+ ///     id: u32,
+ ///     name: String,
+ ///     height: u32,
+ /// }
+ ///
+ /// impl Ord for Person {
+ ///     fn cmp(&self, other: &Self) -> Ordering {
+ ///         self.height.cmp(&other.height)
+ ///     }
+ /// }
+ ///
+ /// impl PartialOrd for Person {
+ ///     fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+ ///         Some(self.cmp(other))
+ ///     }
+ /// }
+ ///
+ /// impl PartialEq for Person {
+ ///     fn eq(&self, other: &Self) -> bool {
+ ///         self.height == other.height
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// [`cmp`]: Ord::cmp
+ #[doc(alias = "<")]
+ #[doc(alias = ">")]
+ #[doc(alias = "<=")]
+ #[doc(alias = ">=")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Ord: Eq + PartialOrd<Self> {
+     /// This method returns an [`Ordering`] between `self` and `other`.
+     ///
+     /// By convention, `self.cmp(&other)` returns the ordering matching the expression
+     /// `self <operator> other` if true.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// assert_eq!(5.cmp(&10), Ordering::Less);
+     /// assert_eq!(10.cmp(&5), Ordering::Greater);
+     /// assert_eq!(5.cmp(&5), Ordering::Equal);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn cmp(&self, other: &Self) -> Ordering;
+ 
+     /// Compares and returns the maximum of two values.
+     ///
+     /// Returns the second argument if the comparison determines them to be equal.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(2, 1.max(2));
+     /// assert_eq!(2, 2.max(2));
+     /// ```
+     #[stable(feature = "ord_max_min", since = "1.21.0")]
+     #[inline]
+     #[must_use]
+     fn max(self, other: Self) -> Self
+     where
+         Self: Sized,
+     {
+         max_by(self, other, Ord::cmp)
+     }
+ 
+     /// Compares and returns the minimum of two values.
+     ///
+     /// Returns the first argument if the comparison determines them to be equal.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(1, 1.min(2));
+     /// assert_eq!(2, 2.min(2));
+     /// ```
+     #[stable(feature = "ord_max_min", since = "1.21.0")]
+     #[inline]
+     #[must_use]
+     fn min(self, other: Self) -> Self
+     where
+         Self: Sized,
+     {
+         min_by(self, other, Ord::cmp)
+     }
+ 
+     /// Restrict a value to a certain interval.
+     ///
+     /// Returns `max` if `self` is greater than `max`, and `min` if `self` is
+     /// less than `min`. Otherwise this returns `self`.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `min > max`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(clamp)]
+     ///
+     /// assert!((-3).clamp(-2, 1) == -2);
+     /// assert!(0.clamp(-2, 1) == 0);
+     /// assert!(2.clamp(-2, 1) == 1);
+     /// ```
+     #[must_use]
+     #[unstable(feature = "clamp", issue = "44095")]
+     fn clamp(self, min: Self, max: Self) -> Self
+     where
+         Self: Sized,
+     {
+         assert!(min <= max);
+         if self < min {
+             min
+         } else if self > max {
+             max
+         } else {
+             self
+         }
+     }
+ }
+ 
+ /// Derive macro generating an impl of the trait `Ord`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics)]
+ pub macro Ord($item:item) {
+     /* compiler built-in */
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Eq for Ordering {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Ord for Ordering {
+     #[inline]
+     fn cmp(&self, other: &Ordering) -> Ordering {
+         (*self as i32).cmp(&(*other as i32))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl PartialOrd for Ordering {
+     #[inline]
+     fn partial_cmp(&self, other: &Ordering) -> Option<Ordering> {
+         (*self as i32).partial_cmp(&(*other as i32))
+     }
+ }
+ 
+ /// Trait for values that can be compared for a sort-order.
+ ///
+ /// The comparison must satisfy, for all `a`, `b` and `c`:
+ ///
+ /// - asymmetry: if `a < b` then `!(a > b)`, as well as `a > b` implying `!(a < b)`; and
+ /// - transitivity: `a < b` and `b < c` implies `a < c`. The same must hold for both `==` and `>`.
+ ///
+ /// Note that these requirements mean that the trait itself must be implemented symmetrically and
+ /// transitively: if `T: PartialOrd<U>` and `U: PartialOrd<V>` then `U: PartialOrd<T>` and `T:
+ /// PartialOrd<V>`.
+ ///
+ /// ## Derivable
+ ///
+ /// This trait can be used with `#[derive]`. When `derive`d on structs, it will produce a
+ /// lexicographic ordering based on the top-to-bottom declaration order of the struct's members.
+ /// When `derive`d on enums, variants are ordered by their top-to-bottom discriminant order.
+ ///
+ /// ## How can I implement `PartialOrd`?
+ ///
+ /// `PartialOrd` only requires implementation of the [`partial_cmp`] method, with the others
+ /// generated from default implementations.
+ ///
+ /// However it remains possible to implement the others separately for types which do not have a
+ /// total order. For example, for floating point numbers, `NaN < 0 == false` and `NaN >= 0 ==
+ /// false` (cf. IEEE 754-2008 section 5.11).
+ ///
+ /// `PartialOrd` requires your type to be [`PartialEq`].
+ ///
+ /// Implementations of [`PartialEq`], `PartialOrd`, and [`Ord`] *must* agree with each other. It's
+ /// easy to accidentally make them disagree by deriving some of the traits and manually
+ /// implementing others.
+ ///
+ /// If your type is [`Ord`], you can implement [`partial_cmp`] by using [`cmp`]:
+ ///
+ /// ```
+ /// use std::cmp::Ordering;
+ ///
+ /// #[derive(Eq)]
+ /// struct Person {
+ ///     id: u32,
+ ///     name: String,
+ ///     height: u32,
+ /// }
+ ///
+ /// impl PartialOrd for Person {
+ ///     fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+ ///         Some(self.cmp(other))
+ ///     }
+ /// }
+ ///
+ /// impl Ord for Person {
+ ///     fn cmp(&self, other: &Self) -> Ordering {
+ ///         self.height.cmp(&other.height)
+ ///     }
+ /// }
+ ///
+ /// impl PartialEq for Person {
+ ///     fn eq(&self, other: &Self) -> bool {
+ ///         self.height == other.height
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// You may also find it useful to use [`partial_cmp`] on your type's fields. Here
+ /// is an example of `Person` types who have a floating-point `height` field that
+ /// is the only field to be used for sorting:
+ ///
+ /// ```
+ /// use std::cmp::Ordering;
+ ///
+ /// struct Person {
+ ///     id: u32,
+ ///     name: String,
+ ///     height: f64,
+ /// }
+ ///
+ /// impl PartialOrd for Person {
+ ///     fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+ ///         self.height.partial_cmp(&other.height)
+ ///     }
+ /// }
+ ///
+ /// impl PartialEq for Person {
+ ///     fn eq(&self, other: &Self) -> bool {
+ ///         self.height == other.height
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let x : u32 = 0;
+ /// let y : u32 = 1;
+ ///
+ /// assert_eq!(x < y, true);
+ /// assert_eq!(x.lt(&y), true);
+ /// ```
+ ///
+ /// [`partial_cmp`]: PartialOrd::partial_cmp
+ /// [`cmp`]: Ord::cmp
+ #[lang = "partial_ord"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(alias = ">")]
+ #[doc(alias = "<")]
+ #[doc(alias = "<=")]
+ #[doc(alias = ">=")]
+ #[rustc_on_unimplemented(
+     message = "can't compare `{Self}` with `{Rhs}`",
+     label = "no implementation for `{Self} < {Rhs}` and `{Self} > {Rhs}`"
+ )]
+ pub trait PartialOrd<Rhs: ?Sized = Self>: PartialEq<Rhs> {
+     /// This method returns an ordering between `self` and `other` values if one exists.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// let result = 1.0.partial_cmp(&2.0);
+     /// assert_eq!(result, Some(Ordering::Less));
+     ///
+     /// let result = 1.0.partial_cmp(&1.0);
+     /// assert_eq!(result, Some(Ordering::Equal));
+     ///
+     /// let result = 2.0.partial_cmp(&1.0);
+     /// assert_eq!(result, Some(Ordering::Greater));
+     /// ```
+     ///
+     /// When comparison is impossible:
+     ///
+     /// ```
+     /// let result = f64::NAN.partial_cmp(&1.0);
+     /// assert_eq!(result, None);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn partial_cmp(&self, other: &Rhs) -> Option<Ordering>;
+ 
+     /// This method tests less than (for `self` and `other`) and is used by the `<` operator.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let result = 1.0 < 2.0;
+     /// assert_eq!(result, true);
+     ///
+     /// let result = 2.0 < 1.0;
+     /// assert_eq!(result, false);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn lt(&self, other: &Rhs) -> bool {
+         matches!(self.partial_cmp(other), Some(Less))
+     }
+ 
+     /// This method tests less than or equal to (for `self` and `other`) and is used by the `<=`
+     /// operator.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let result = 1.0 <= 2.0;
+     /// assert_eq!(result, true);
+     ///
+     /// let result = 2.0 <= 2.0;
+     /// assert_eq!(result, true);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn le(&self, other: &Rhs) -> bool {
+         matches!(self.partial_cmp(other), Some(Less | Equal))
+     }
+ 
+     /// This method tests greater than (for `self` and `other`) and is used by the `>` operator.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let result = 1.0 > 2.0;
+     /// assert_eq!(result, false);
+     ///
+     /// let result = 2.0 > 2.0;
+     /// assert_eq!(result, false);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn gt(&self, other: &Rhs) -> bool {
+         matches!(self.partial_cmp(other), Some(Greater))
+     }
+ 
+     /// This method tests greater than or equal to (for `self` and `other`) and is used by the `>=`
+     /// operator.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let result = 2.0 >= 1.0;
+     /// assert_eq!(result, true);
+     ///
+     /// let result = 2.0 >= 2.0;
+     /// assert_eq!(result, true);
+     /// ```
+     #[inline]
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn ge(&self, other: &Rhs) -> bool {
+         matches!(self.partial_cmp(other), Some(Greater | Equal))
+     }
+ }
+ 
+ /// Derive macro generating an impl of the trait `PartialOrd`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics)]
+ pub macro PartialOrd($item:item) {
+     /* compiler built-in */
+ }
+ 
+ /// Compares and returns the minimum of two values.
+ ///
+ /// Returns the first argument if the comparison determines them to be equal.
+ ///
+ /// Internally uses an alias to [`Ord::min`].
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::cmp;
+ ///
+ /// assert_eq!(1, cmp::min(1, 2));
+ /// assert_eq!(2, cmp::min(2, 2));
+ /// ```
+ #[inline]
+ #[must_use]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn min<T: Ord>(v1: T, v2: T) -> T {
+     v1.min(v2)
+ }
+ 
+ /// Returns the minimum of two values with respect to the specified comparison function.
+ ///
+ /// Returns the first argument if the comparison determines them to be equal.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(cmp_min_max_by)]
+ ///
+ /// use std::cmp;
+ ///
+ /// assert_eq!(cmp::min_by(-2, 1, |x: &i32, y: &i32| x.abs().cmp(&y.abs())), 1);
+ /// assert_eq!(cmp::min_by(-2, 2, |x: &i32, y: &i32| x.abs().cmp(&y.abs())), -2);
+ /// ```
+ #[inline]
+ #[must_use]
+ #[unstable(feature = "cmp_min_max_by", issue = "64460")]
+ pub fn min_by<T, F: FnOnce(&T, &T) -> Ordering>(v1: T, v2: T, compare: F) -> T {
+     match compare(&v1, &v2) {
+         Ordering::Less | Ordering::Equal => v1,
+         Ordering::Greater => v2,
+     }
+ }
+ 
+ /// Returns the element that gives the minimum value from the specified function.
+ ///
+ /// Returns the first argument if the comparison determines them to be equal.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(cmp_min_max_by)]
+ ///
+ /// use std::cmp;
+ ///
+ /// assert_eq!(cmp::min_by_key(-2, 1, |x: &i32| x.abs()), 1);
+ /// assert_eq!(cmp::min_by_key(-2, 2, |x: &i32| x.abs()), -2);
+ /// ```
+ #[inline]
+ #[must_use]
+ #[unstable(feature = "cmp_min_max_by", issue = "64460")]
+ pub fn min_by_key<T, F: FnMut(&T) -> K, K: Ord>(v1: T, v2: T, mut f: F) -> T {
+     min_by(v1, v2, |v1, v2| f(v1).cmp(&f(v2)))
+ }
+ 
+ /// Compares and returns the maximum of two values.
+ ///
+ /// Returns the second argument if the comparison determines them to be equal.
+ ///
+ /// Internally uses an alias to [`Ord::max`].
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::cmp;
+ ///
+ /// assert_eq!(2, cmp::max(1, 2));
+ /// assert_eq!(2, cmp::max(2, 2));
+ /// ```
+ #[inline]
+ #[must_use]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn max<T: Ord>(v1: T, v2: T) -> T {
+     v1.max(v2)
+ }
+ 
+ /// Returns the maximum of two values with respect to the specified comparison function.
+ ///
+ /// Returns the second argument if the comparison determines them to be equal.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(cmp_min_max_by)]
+ ///
+ /// use std::cmp;
+ ///
+ /// assert_eq!(cmp::max_by(-2, 1, |x: &i32, y: &i32| x.abs().cmp(&y.abs())), -2);
+ /// assert_eq!(cmp::max_by(-2, 2, |x: &i32, y: &i32| x.abs().cmp(&y.abs())), 2);
+ /// ```
+ #[inline]
+ #[must_use]
+ #[unstable(feature = "cmp_min_max_by", issue = "64460")]
+ pub fn max_by<T, F: FnOnce(&T, &T) -> Ordering>(v1: T, v2: T, compare: F) -> T {
+     match compare(&v1, &v2) {
+         Ordering::Less | Ordering::Equal => v2,
+         Ordering::Greater => v1,
+     }
+ }
+ 
+ /// Returns the element that gives the maximum value from the specified function.
+ ///
+ /// Returns the second argument if the comparison determines them to be equal.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(cmp_min_max_by)]
+ ///
+ /// use std::cmp;
+ ///
+ /// assert_eq!(cmp::max_by_key(-2, 1, |x: &i32| x.abs()), -2);
+ /// assert_eq!(cmp::max_by_key(-2, 2, |x: &i32| x.abs()), 2);
+ /// ```
+ #[inline]
+ #[must_use]
+ #[unstable(feature = "cmp_min_max_by", issue = "64460")]
+ pub fn max_by_key<T, F: FnMut(&T) -> K, K: Ord>(v1: T, v2: T, mut f: F) -> T {
+     max_by(v1, v2, |v1, v2| f(v1).cmp(&f(v2)))
+ }
+ 
+ // Implementation of PartialEq, Eq, PartialOrd and Ord for primitive types
+ mod impls {
+     use crate::cmp::Ordering::{self, Equal, Greater, Less};
+     use crate::hint::unreachable_unchecked;
+ 
+     macro_rules! partial_eq_impl {
+         ($($t:ty)*) => ($(
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl PartialEq for $t {
+                 #[inline]
+                 fn eq(&self, other: &$t) -> bool { (*self) == (*other) }
+                 #[inline]
+                 fn ne(&self, other: &$t) -> bool { (*self) != (*other) }
+             }
+         )*)
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl PartialEq for () {
+         #[inline]
+         fn eq(&self, _other: &()) -> bool {
+             true
+         }
+         #[inline]
+         fn ne(&self, _other: &()) -> bool {
+             false
+         }
+     }
+ 
+     partial_eq_impl! {
+         bool char usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64
+     }
+ 
+     macro_rules! eq_impl {
+         ($($t:ty)*) => ($(
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl Eq for $t {}
+         )*)
+     }
+ 
+     eq_impl! { () bool char usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+     macro_rules! partial_ord_impl {
+         ($($t:ty)*) => ($(
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl PartialOrd for $t {
+                 #[inline]
+                 fn partial_cmp(&self, other: &$t) -> Option<Ordering> {
+                     match (self <= other, self >= other) {
+                         (false, false) => None,
+                         (false, true) => Some(Greater),
+                         (true, false) => Some(Less),
+                         (true, true) => Some(Equal),
+                     }
+                 }
+                 #[inline]
+                 fn lt(&self, other: &$t) -> bool { (*self) < (*other) }
+                 #[inline]
+                 fn le(&self, other: &$t) -> bool { (*self) <= (*other) }
+                 #[inline]
+                 fn ge(&self, other: &$t) -> bool { (*self) >= (*other) }
+                 #[inline]
+                 fn gt(&self, other: &$t) -> bool { (*self) > (*other) }
+             }
+         )*)
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl PartialOrd for () {
+         #[inline]
+         fn partial_cmp(&self, _: &()) -> Option<Ordering> {
+             Some(Equal)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl PartialOrd for bool {
+         #[inline]
+         fn partial_cmp(&self, other: &bool) -> Option<Ordering> {
+             (*self as u8).partial_cmp(&(*other as u8))
+         }
+     }
+ 
+     partial_ord_impl! { f32 f64 }
+ 
+     macro_rules! ord_impl {
+         ($($t:ty)*) => ($(
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl PartialOrd for $t {
+                 #[inline]
+                 fn partial_cmp(&self, other: &$t) -> Option<Ordering> {
+                     Some(self.cmp(other))
+                 }
+                 #[inline]
+                 fn lt(&self, other: &$t) -> bool { (*self) < (*other) }
+                 #[inline]
+                 fn le(&self, other: &$t) -> bool { (*self) <= (*other) }
+                 #[inline]
+                 fn ge(&self, other: &$t) -> bool { (*self) >= (*other) }
+                 #[inline]
+                 fn gt(&self, other: &$t) -> bool { (*self) > (*other) }
+             }
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl Ord for $t {
+                 #[inline]
+                 fn cmp(&self, other: &$t) -> Ordering {
+                     // The order here is important to generate more optimal assembly.
+                     // See <https://github.com/rust-lang/rust/issues/63758> for more info.
+                     if *self < *other { Less }
+                     else if *self == *other { Equal }
+                     else { Greater }
+                 }
+             }
+         )*)
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl Ord for () {
+         #[inline]
+         fn cmp(&self, _other: &()) -> Ordering {
+             Equal
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl Ord for bool {
+         #[inline]
+         fn cmp(&self, other: &bool) -> Ordering {
+             // Casting to i8's and converting the difference to an Ordering generates
+             // more optimal assembly.
+             // See <https://github.com/rust-lang/rust/issues/66780> for more info.
+             match (*self as i8) - (*other as i8) {
+                 -1 => Less,
+                 0 => Equal,
+                 1 => Greater,
+                 // SAFETY: bool as i8 returns 0 or 1, so the difference can't be anything else
+                 _ => unsafe { unreachable_unchecked() },
+             }
+         }
+     }
+ 
+     ord_impl! { char usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+     #[unstable(feature = "never_type", issue = "35121")]
+     impl PartialEq for ! {
+         fn eq(&self, _: &!) -> bool {
+             *self
+         }
+     }
+ 
+     #[unstable(feature = "never_type", issue = "35121")]
+     impl Eq for ! {}
+ 
+     #[unstable(feature = "never_type", issue = "35121")]
+     impl PartialOrd for ! {
+         fn partial_cmp(&self, _: &!) -> Option<Ordering> {
+             *self
+         }
+     }
+ 
+     #[unstable(feature = "never_type", issue = "35121")]
+     impl Ord for ! {
+         fn cmp(&self, _: &!) -> Ordering {
+             *self
+         }
+     }
+ 
+     // & pointers
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized, B: ?Sized> PartialEq<&B> for &A
+     where
+         A: PartialEq<B>,
+     {
+         #[inline]
+         fn eq(&self, other: &&B) -> bool {
+             PartialEq::eq(*self, *other)
+         }
+         #[inline]
+         fn ne(&self, other: &&B) -> bool {
+             PartialEq::ne(*self, *other)
+         }
+     }
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized, B: ?Sized> PartialOrd<&B> for &A
+     where
+         A: PartialOrd<B>,
+     {
+         #[inline]
+         fn partial_cmp(&self, other: &&B) -> Option<Ordering> {
+             PartialOrd::partial_cmp(*self, *other)
+         }
+         #[inline]
+         fn lt(&self, other: &&B) -> bool {
+             PartialOrd::lt(*self, *other)
+         }
+         #[inline]
+         fn le(&self, other: &&B) -> bool {
+             PartialOrd::le(*self, *other)
+         }
+         #[inline]
+         fn gt(&self, other: &&B) -> bool {
+             PartialOrd::gt(*self, *other)
+         }
+         #[inline]
+         fn ge(&self, other: &&B) -> bool {
+             PartialOrd::ge(*self, *other)
+         }
+     }
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized> Ord for &A
+     where
+         A: Ord,
+     {
+         #[inline]
+         fn cmp(&self, other: &Self) -> Ordering {
+             Ord::cmp(*self, *other)
+         }
+     }
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized> Eq for &A where A: Eq {}
+ 
+     // &mut pointers
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized, B: ?Sized> PartialEq<&mut B> for &mut A
+     where
+         A: PartialEq<B>,
+     {
+         #[inline]
+         fn eq(&self, other: &&mut B) -> bool {
+             PartialEq::eq(*self, *other)
+         }
+         #[inline]
+         fn ne(&self, other: &&mut B) -> bool {
+             PartialEq::ne(*self, *other)
+         }
+     }
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized, B: ?Sized> PartialOrd<&mut B> for &mut A
+     where
+         A: PartialOrd<B>,
+     {
+         #[inline]
+         fn partial_cmp(&self, other: &&mut B) -> Option<Ordering> {
+             PartialOrd::partial_cmp(*self, *other)
+         }
+         #[inline]
+         fn lt(&self, other: &&mut B) -> bool {
+             PartialOrd::lt(*self, *other)
+         }
+         #[inline]
+         fn le(&self, other: &&mut B) -> bool {
+             PartialOrd::le(*self, *other)
+         }
+         #[inline]
+         fn gt(&self, other: &&mut B) -> bool {
+             PartialOrd::gt(*self, *other)
+         }
+         #[inline]
+         fn ge(&self, other: &&mut B) -> bool {
+             PartialOrd::ge(*self, *other)
+         }
+     }
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized> Ord for &mut A
+     where
+         A: Ord,
+     {
+         #[inline]
+         fn cmp(&self, other: &Self) -> Ordering {
+             Ord::cmp(*self, *other)
+         }
+     }
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized> Eq for &mut A where A: Eq {}
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized, B: ?Sized> PartialEq<&mut B> for &A
+     where
+         A: PartialEq<B>,
+     {
+         #[inline]
+         fn eq(&self, other: &&mut B) -> bool {
+             PartialEq::eq(*self, *other)
+         }
+         #[inline]
+         fn ne(&self, other: &&mut B) -> bool {
+             PartialEq::ne(*self, *other)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A: ?Sized, B: ?Sized> PartialEq<&B> for &mut A
+     where
+         A: PartialEq<B>,
+     {
+         #[inline]
+         fn eq(&self, other: &&B) -> bool {
+             PartialEq::eq(*self, *other)
+         }
+         #[inline]
+         fn ne(&self, other: &&B) -> bool {
+             PartialEq::ne(*self, *other)
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/convert/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/convert/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/convert/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/convert/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,738 ----
+ //! Traits for conversions between types.
+ //!
+ //! The traits in this module provide a way to convert from one type to another type.
+ //! Each trait serves a different purpose:
+ //!
+ //! - Implement the [`AsRef`] trait for cheap reference-to-reference conversions
+ //! - Implement the [`AsMut`] trait for cheap mutable-to-mutable conversions
+ //! - Implement the [`From`] trait for consuming value-to-value conversions
+ //! - Implement the [`Into`] trait for consuming value-to-value conversions to types
+ //!   outside the current crate
+ //! - The [`TryFrom`] and [`TryInto`] traits behave like [`From`] and [`Into`],
+ //!   but should be implemented when the conversion can fail.
+ //!
+ //! The traits in this module are often used as trait bounds for generic functions such that to
+ //! arguments of multiple types are supported. See the documentation of each trait for examples.
+ //!
+ //! As a library author, you should always prefer implementing [`From<T>`][`From`] or
+ //! [`TryFrom<T>`][`TryFrom`] rather than [`Into<U>`][`Into`] or [`TryInto<U>`][`TryInto`],
+ //! as [`From`] and [`TryFrom`] provide greater flexibility and offer
+ //! equivalent [`Into`] or [`TryInto`] implementations for free, thanks to a
+ //! blanket implementation in the standard library. When targeting a version prior to Rust 1.41, it
+ //! may be necessary to implement [`Into`] or [`TryInto`] directly when converting to a type
+ //! outside the current crate.
+ //!
+ //! # Generic Implementations
+ //!
+ //! - [`AsRef`] and [`AsMut`] auto-dereference if the inner type is a reference
+ //! - [`From`]`<U> for T` implies [`Into`]`<T> for U`
+ //! - [`TryFrom`]`<U> for T` implies [`TryInto`]`<T> for U`
+ //! - [`From`] and [`Into`] are reflexive, which means that all types can
+ //!   `into` themselves and `from` themselves
+ //!
+ //! See each trait for usage examples.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::fmt;
+ use crate::hash::{Hash, Hasher};
+ 
+ mod num;
+ 
+ #[unstable(feature = "convert_float_to_int", issue = "67057")]
+ pub use num::FloatToInt;
+ 
+ /// The identity function.
+ ///
+ /// Two things are important to note about this function:
+ ///
+ /// - It is not always equivalent to a closure like `|x| x`, since the
+ ///   closure may coerce `x` into a different type.
+ ///
+ /// - It moves the input `x` passed to the function.
+ ///
+ /// While it might seem strange to have a function that just returns back the
+ /// input, there are some interesting uses.
+ ///
+ /// # Examples
+ ///
+ /// Using `identity` to do nothing in a sequence of other, interesting,
+ /// functions:
+ ///
+ /// ```rust
+ /// use std::convert::identity;
+ ///
+ /// fn manipulation(x: u32) -> u32 {
+ ///     // Let's pretend that adding one is an interesting function.
+ ///     x + 1
+ /// }
+ ///
+ /// let _arr = &[identity, manipulation];
+ /// ```
+ ///
+ /// Using `identity` as a "do nothing" base case in a conditional:
+ ///
+ /// ```rust
+ /// use std::convert::identity;
+ ///
+ /// # let condition = true;
+ /// #
+ /// # fn manipulation(x: u32) -> u32 { x + 1 }
+ /// #
+ /// let do_stuff = if condition { manipulation } else { identity };
+ ///
+ /// // Do more interesting stuff...
+ ///
+ /// let _results = do_stuff(42);
+ /// ```
+ ///
+ /// Using `identity` to keep the `Some` variants of an iterator of `Option<T>`:
+ ///
+ /// ```rust
+ /// use std::convert::identity;
+ ///
+ /// let iter = vec![Some(1), None, Some(3)].into_iter();
+ /// let filtered = iter.filter_map(identity).collect::<Vec<_>>();
+ /// assert_eq!(vec![1, 3], filtered);
+ /// ```
+ #[stable(feature = "convert_id", since = "1.33.0")]
+ #[rustc_const_stable(feature = "const_identity", since = "1.33.0")]
+ #[inline]
+ pub const fn identity<T>(x: T) -> T {
+     x
+ }
+ 
+ /// Used to do a cheap reference-to-reference conversion.
+ ///
+ /// This trait is similar to [`AsMut`] which is used for converting between mutable references.
+ /// If you need to do a costly conversion it is better to implement [`From`] with type
+ /// `&T` or write a custom function.
+ ///
+ /// `AsRef` has the same signature as [`Borrow`], but [`Borrow`] is different in few aspects:
+ ///
+ /// - Unlike `AsRef`, [`Borrow`] has a blanket impl for any `T`, and can be used to accept either
+ ///   a reference or a value.
+ /// - [`Borrow`] also requires that [`Hash`], [`Eq`] and [`Ord`] for borrowed value are
+ ///   equivalent to those of the owned value. For this reason, if you want to
+ ///   borrow only a single field of a struct you can implement `AsRef`, but not [`Borrow`].
+ ///
+ /// **Note: This trait must not fail**. If the conversion can fail, use a
+ /// dedicated method which returns an [`Option<T>`] or a [`Result<T, E>`].
+ ///
+ /// # Generic Implementations
+ ///
+ /// - `AsRef` auto-dereferences if the inner type is a reference or a mutable
+ ///   reference (e.g.: `foo.as_ref()` will work the same if `foo` has type
+ ///   `&mut Foo` or `&&mut Foo`)
+ ///
+ /// # Examples
+ ///
+ /// By using trait bounds we can accept arguments of different types as long as they can be
+ /// converted to the specified type `T`.
+ ///
+ /// For example: By creating a generic function that takes an `AsRef<str>` we express that we
+ /// want to accept all references that can be converted to [`&str`] as an argument.
+ /// Since both [`String`] and [`&str`] implement `AsRef<str>` we can accept both as input argument.
+ ///
+ /// [`&str`]: primitive@str
+ /// [`Option<T>`]: Option
+ /// [`Result<T, E>`]: Result
+ /// [`Borrow`]: crate::borrow::Borrow
+ /// [`Eq`]: crate::cmp::Eq
+ /// [`Ord`]: crate::cmp::Ord
+ /// [`String`]: ../../std/string/struct.String.html
+ ///
+ /// ```
+ /// fn is_hello<T: AsRef<str>>(s: T) {
+ ///    assert_eq!("hello", s.as_ref());
+ /// }
+ ///
+ /// let s = "hello";
+ /// is_hello(s);
+ ///
+ /// let s = "hello".to_string();
+ /// is_hello(s);
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait AsRef<T: ?Sized> {
+     /// Performs the conversion.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn as_ref(&self) -> &T;
+ }
+ 
+ /// Used to do a cheap mutable-to-mutable reference conversion.
+ ///
+ /// This trait is similar to [`AsRef`] but used for converting between mutable
+ /// references. If you need to do a costly conversion it is better to
+ /// implement [`From`] with type `&mut T` or write a custom function.
+ ///
+ /// **Note: This trait must not fail**. If the conversion can fail, use a
+ /// dedicated method which returns an [`Option<T>`] or a [`Result<T, E>`].
+ ///
+ /// [`Option<T>`]: Option
+ /// [`Result<T, E>`]: Result
+ ///
+ /// # Generic Implementations
+ ///
+ /// - `AsMut` auto-dereferences if the inner type is a mutable reference
+ ///   (e.g.: `foo.as_mut()` will work the same if `foo` has type `&mut Foo`
+ ///   or `&mut &mut Foo`)
+ ///
+ /// # Examples
+ ///
+ /// Using `AsMut` as trait bound for a generic function we can accept all mutable references
+ /// that can be converted to type `&mut T`. Because [`Box<T>`] implements `AsMut<T>` we can
+ /// write a function `add_one` that takes all arguments that can be converted to `&mut u64`.
+ /// Because [`Box<T>`] implements `AsMut<T>`, `add_one` accepts arguments of type
+ /// `&mut Box<u64>` as well:
+ ///
+ /// ```
+ /// fn add_one<T: AsMut<u64>>(num: &mut T) {
+ ///     *num.as_mut() += 1;
+ /// }
+ ///
+ /// let mut boxed_num = Box::new(0);
+ /// add_one(&mut boxed_num);
+ /// assert_eq!(*boxed_num, 1);
+ /// ```
+ ///
+ /// [`Box<T>`]: ../../std/boxed/struct.Box.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait AsMut<T: ?Sized> {
+     /// Performs the conversion.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn as_mut(&mut self) -> &mut T;
+ }
+ 
+ /// A value-to-value conversion that consumes the input value. The
+ /// opposite of [`From`].
+ ///
+ /// One should avoid implementing [`Into`] and implement [`From`] instead.
+ /// Implementing [`From`] automatically provides one with an implementation of [`Into`]
+ /// thanks to the blanket implementation in the standard library.
+ ///
+ /// Prefer using [`Into`] over [`From`] when specifying trait bounds on a generic function
+ /// to ensure that types that only implement [`Into`] can be used as well.
+ ///
+ /// **Note: This trait must not fail**. If the conversion can fail, use [`TryInto`].
+ ///
+ /// # Generic Implementations
+ ///
+ /// - [`From`]`<T> for U` implies `Into<U> for T`
+ /// - [`Into`] is reflexive, which means that `Into<T> for T` is implemented
+ ///
+ /// # Implementing [`Into`] for conversions to external types in old versions of Rust
+ ///
+ /// Prior to Rust 1.41, if the destination type was not part of the current crate
+ /// then you couldn't implement [`From`] directly.
+ /// For example, take this code:
+ ///
+ /// ```
+ /// struct Wrapper<T>(Vec<T>);
+ /// impl<T> From<Wrapper<T>> for Vec<T> {
+ ///     fn from(w: Wrapper<T>) -> Vec<T> {
+ ///         w.0
+ ///     }
+ /// }
+ /// ```
+ /// This will fail to compile in older versions of the language because Rust's orphaning rules
+ /// used to be a little bit more strict. To bypass this, you could implement [`Into`] directly:
+ ///
+ /// ```
+ /// struct Wrapper<T>(Vec<T>);
+ /// impl<T> Into<Vec<T>> for Wrapper<T> {
+ ///     fn into(self) -> Vec<T> {
+ ///         self.0
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// It is important to understand that [`Into`] does not provide a [`From`] implementation
+ /// (as [`From`] does with [`Into`]). Therefore, you should always try to implement [`From`]
+ /// and then fall back to [`Into`] if [`From`] can't be implemented.
+ ///
+ /// # Examples
+ ///
+ /// [`String`] implements [`Into`]`<`[`Vec`]`<`[`u8`]`>>`:
+ ///
+ /// In order to express that we want a generic function to take all arguments that can be
+ /// converted to a specified type `T`, we can use a trait bound of [`Into`]`<T>`.
+ /// For example: The function `is_hello` takes all arguments that can be converted into a
+ /// [`Vec`]`<`[`u8`]`>`.
+ ///
+ /// ```
+ /// fn is_hello<T: Into<Vec<u8>>>(s: T) {
+ ///    let bytes = b"hello".to_vec();
+ ///    assert_eq!(bytes, s.into());
+ /// }
+ ///
+ /// let s = "hello".to_string();
+ /// is_hello(s);
+ /// ```
+ ///
+ /// [`Option<T>`]: Option
+ /// [`Result<T, E>`]: Result
+ /// [`String`]: ../../std/string/struct.String.html
+ /// [`Vec`]: ../../std/vec/struct.Vec.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Into<T>: Sized {
+     /// Performs the conversion.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn into(self) -> T;
+ }
+ 
+ /// Used to do value-to-value conversions while consuming the input value. It is the reciprocal of
+ /// [`Into`].
+ ///
+ /// One should always prefer implementing `From` over [`Into`]
+ /// because implementing `From` automatically provides one with an implementation of [`Into`]
+ /// thanks to the blanket implementation in the standard library.
+ ///
+ /// Only implement [`Into`] when targeting a version prior to Rust 1.41 and converting to a type
+ /// outside the current crate.
+ /// `From` was not able to do these types of conversions in earlier versions because of Rust's
+ /// orphaning rules.
+ /// See [`Into`] for more details.
+ ///
+ /// Prefer using [`Into`] over using `From` when specifying trait bounds on a generic function.
+ /// This way, types that directly implement [`Into`] can be used as arguments as well.
+ ///
+ /// The `From` is also very useful when performing error handling. When constructing a function
+ /// that is capable of failing, the return type will generally be of the form `Result<T, E>`.
+ /// The `From` trait simplifies error handling by allowing a function to return a single error type
+ /// that encapsulate multiple error types. See the "Examples" section and [the book][book] for more
+ /// details.
+ ///
+ /// **Note: This trait must not fail**. If the conversion can fail, use [`TryFrom`].
+ ///
+ /// # Generic Implementations
+ ///
+ /// - `From<T> for U` implies [`Into`]`<U> for T`
+ /// - `From` is reflexive, which means that `From<T> for T` is implemented
+ ///
+ /// # Examples
+ ///
+ /// [`String`] implements `From<&str>`:
+ ///
+ /// An explicit conversion from a `&str` to a String is done as follows:
+ ///
+ /// ```
+ /// let string = "hello".to_string();
+ /// let other_string = String::from("hello");
+ ///
+ /// assert_eq!(string, other_string);
+ /// ```
+ ///
+ /// While performing error handling it is often useful to implement `From` for your own error type.
+ /// By converting underlying error types to our own custom error type that encapsulates the
+ /// underlying error type, we can return a single error type without losing information on the
+ /// underlying cause. The '?' operator automatically converts the underlying error type to our
+ /// custom error type by calling `Into<CliError>::into` which is automatically provided when
+ /// implementing `From`. The compiler then infers which implementation of `Into` should be used.
+ ///
+ /// ```
+ /// use std::fs;
+ /// use std::io;
+ /// use std::num;
+ ///
+ /// enum CliError {
+ ///     IoError(io::Error),
+ ///     ParseError(num::ParseIntError),
+ /// }
+ ///
+ /// impl From<io::Error> for CliError {
+ ///     fn from(error: io::Error) -> Self {
+ ///         CliError::IoError(error)
+ ///     }
+ /// }
+ ///
+ /// impl From<num::ParseIntError> for CliError {
+ ///     fn from(error: num::ParseIntError) -> Self {
+ ///         CliError::ParseError(error)
+ ///     }
+ /// }
+ ///
+ /// fn open_and_parse_file(file_name: &str) -> Result<i32, CliError> {
+ ///     let mut contents = fs::read_to_string(&file_name)?;
+ ///     let num: i32 = contents.trim().parse()?;
+ ///     Ok(num)
+ /// }
+ /// ```
+ ///
+ /// [`Option<T>`]: Option
+ /// [`Result<T, E>`]: Result
+ /// [`String`]: ../../std/string/struct.String.html
+ /// [`from`]: From::from
+ /// [book]: ../../book/ch09-00-error-handling.html
+ #[rustc_diagnostic_item = "from_trait"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(on(
+     all(_Self = "&str", T = "std::string::String"),
+     note = "to coerce a `{T}` into a `{Self}`, use `&*` as a prefix",
+ ))]
+ pub trait From<T>: Sized {
+     /// Performs the conversion.
+     #[lang = "from"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn from(_: T) -> Self;
+ }
+ 
+ /// An attempted conversion that consumes `self`, which may or may not be
+ /// expensive.
+ ///
+ /// Library authors should usually not directly implement this trait,
+ /// but should prefer implementing the [`TryFrom`] trait, which offers
+ /// greater flexibility and provides an equivalent `TryInto`
+ /// implementation for free, thanks to a blanket implementation in the
+ /// standard library. For more information on this, see the
+ /// documentation for [`Into`].
+ ///
+ /// # Implementing `TryInto`
+ ///
+ /// This suffers the same restrictions and reasoning as implementing
+ /// [`Into`], see there for details.
+ #[stable(feature = "try_from", since = "1.34.0")]
+ pub trait TryInto<T>: Sized {
+     /// The type returned in the event of a conversion error.
+     #[stable(feature = "try_from", since = "1.34.0")]
+     type Error;
+ 
+     /// Performs the conversion.
+     #[stable(feature = "try_from", since = "1.34.0")]
+     fn try_into(self) -> Result<T, Self::Error>;
+ }
+ 
+ /// Simple and safe type conversions that may fail in a controlled
+ /// way under some circumstances. It is the reciprocal of [`TryInto`].
+ ///
+ /// This is useful when you are doing a type conversion that may
+ /// trivially succeed but may also need special handling.
+ /// For example, there is no way to convert an [`i64`] into an [`i32`]
+ /// using the [`From`] trait, because an [`i64`] may contain a value
+ /// that an [`i32`] cannot represent and so the conversion would lose data.
+ /// This might be handled by truncating the [`i64`] to an [`i32`] (essentially
+ /// giving the [`i64`]'s value modulo [`i32::MAX`]) or by simply returning
+ /// [`i32::MAX`], or by some other method.  The [`From`] trait is intended
+ /// for perfect conversions, so the `TryFrom` trait informs the
+ /// programmer when a type conversion could go bad and lets them
+ /// decide how to handle it.
+ ///
+ /// # Generic Implementations
+ ///
+ /// - `TryFrom<T> for U` implies [`TryInto`]`<U> for T`
+ /// - [`try_from`] is reflexive, which means that `TryFrom<T> for T`
+ /// is implemented and cannot fail -- the associated `Error` type for
+ /// calling `T::try_from()` on a value of type `T` is [`Infallible`].
+ /// When the [`!`] type is stabilized [`Infallible`] and [`!`] will be
+ /// equivalent.
+ ///
+ /// `TryFrom<T>` can be implemented as follows:
+ ///
+ /// ```
+ /// use std::convert::TryFrom;
+ ///
+ /// struct GreaterThanZero(i32);
+ ///
+ /// impl TryFrom<i32> for GreaterThanZero {
+ ///     type Error = &'static str;
+ ///
+ ///     fn try_from(value: i32) -> Result<Self, Self::Error> {
+ ///         if value <= 0 {
+ ///             Err("GreaterThanZero only accepts value superior than zero!")
+ ///         } else {
+ ///             Ok(GreaterThanZero(value))
+ ///         }
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// # Examples
+ ///
+ /// As described, [`i32`] implements `TryFrom<`[`i64`]`>`:
+ ///
+ /// ```
+ /// use std::convert::TryFrom;
+ ///
+ /// let big_number = 1_000_000_000_000i64;
+ /// // Silently truncates `big_number`, requires detecting
+ /// // and handling the truncation after the fact.
+ /// let smaller_number = big_number as i32;
+ /// assert_eq!(smaller_number, -727379968);
+ ///
+ /// // Returns an error because `big_number` is too big to
+ /// // fit in an `i32`.
+ /// let try_smaller_number = i32::try_from(big_number);
+ /// assert!(try_smaller_number.is_err());
+ ///
+ /// // Returns `Ok(3)`.
+ /// let try_successful_smaller_number = i32::try_from(3);
+ /// assert!(try_successful_smaller_number.is_ok());
+ /// ```
+ ///
+ /// [`i32::MAX`]: crate::i32::MAX
+ /// [`try_from`]: TryFrom::try_from
+ /// [`!`]: ../../std/primitive.never.html
+ #[stable(feature = "try_from", since = "1.34.0")]
+ pub trait TryFrom<T>: Sized {
+     /// The type returned in the event of a conversion error.
+     #[stable(feature = "try_from", since = "1.34.0")]
+     type Error;
+ 
+     /// Performs the conversion.
+     #[stable(feature = "try_from", since = "1.34.0")]
+     fn try_from(value: T) -> Result<Self, Self::Error>;
+ }
+ 
+ ////////////////////////////////////////////////////////////////////////////////
+ // GENERIC IMPLS
+ ////////////////////////////////////////////////////////////////////////////////
+ 
+ // As lifts over &
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized, U: ?Sized> AsRef<U> for &T
+ where
+     T: AsRef<U>,
+ {
+     fn as_ref(&self) -> &U {
+         <T as AsRef<U>>::as_ref(*self)
+     }
+ }
+ 
+ // As lifts over &mut
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized, U: ?Sized> AsRef<U> for &mut T
+ where
+     T: AsRef<U>,
+ {
+     fn as_ref(&self) -> &U {
+         <T as AsRef<U>>::as_ref(*self)
+     }
+ }
+ 
+ // FIXME (#45742): replace the above impls for &/&mut with the following more general one:
+ // // As lifts over Deref
+ // impl<D: ?Sized + Deref<Target: AsRef<U>>, U: ?Sized> AsRef<U> for D {
+ //     fn as_ref(&self) -> &U {
+ //         self.deref().as_ref()
+ //     }
+ // }
+ 
+ // AsMut lifts over &mut
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized, U: ?Sized> AsMut<U> for &mut T
+ where
+     T: AsMut<U>,
+ {
+     fn as_mut(&mut self) -> &mut U {
+         (*self).as_mut()
+     }
+ }
+ 
+ // FIXME (#45742): replace the above impl for &mut with the following more general one:
+ // // AsMut lifts over DerefMut
+ // impl<D: ?Sized + Deref<Target: AsMut<U>>, U: ?Sized> AsMut<U> for D {
+ //     fn as_mut(&mut self) -> &mut U {
+ //         self.deref_mut().as_mut()
+ //     }
+ // }
+ 
+ // From implies Into
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, U> Into<U> for T
+ where
+     U: From<T>,
+ {
+     fn into(self) -> U {
+         U::from(self)
+     }
+ }
+ 
+ // From (and thus Into) is reflexive
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> From<T> for T {
+     fn from(t: T) -> T {
+         t
+     }
+ }
+ 
+ /// **Stability note:** This impl does not yet exist, but we are
+ /// "reserving space" to add it in the future. See
+ /// [rust-lang/rust#64715][#64715] for details.
+ ///
+ /// [#64715]: https://github.com/rust-lang/rust/issues/64715
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ #[allow(unused_attributes)] // FIXME(#58633): do a principled fix instead.
+ #[rustc_reservation_impl = "permitting this impl would forbid us from adding \
+                             `impl<T> From<!> for T` later; see rust-lang/rust#64715 for details"]
+ impl<T> From<!> for T {
+     fn from(t: !) -> T {
+         t
+     }
+ }
+ 
+ // TryFrom implies TryInto
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl<T, U> TryInto<U> for T
+ where
+     U: TryFrom<T>,
+ {
+     type Error = U::Error;
+ 
+     fn try_into(self) -> Result<U, U::Error> {
+         U::try_from(self)
+     }
+ }
+ 
+ // Infallible conversions are semantically equivalent to fallible conversions
+ // with an uninhabited error type.
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl<T, U> TryFrom<U> for T
+ where
+     U: Into<T>,
+ {
+     type Error = Infallible;
+ 
+     fn try_from(value: U) -> Result<Self, Self::Error> {
+         Ok(U::into(value))
+     }
+ }
+ 
+ ////////////////////////////////////////////////////////////////////////////////
+ // CONCRETE IMPLS
+ ////////////////////////////////////////////////////////////////////////////////
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> AsRef<[T]> for [T] {
+     fn as_ref(&self) -> &[T] {
+         self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> AsMut<[T]> for [T] {
+     fn as_mut(&mut self) -> &mut [T] {
+         self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl AsRef<str> for str {
+     #[inline]
+     fn as_ref(&self) -> &str {
+         self
+     }
+ }
+ 
+ ////////////////////////////////////////////////////////////////////////////////
+ // THE NO-ERROR ERROR TYPE
+ ////////////////////////////////////////////////////////////////////////////////
+ 
+ /// The error type for errors that can never happen.
+ ///
+ /// Since this enum has no variant, a value of this type can never actually exist.
+ /// This can be useful for generic APIs that use [`Result`] and parameterize the error type,
+ /// to indicate that the result is always [`Ok`].
+ ///
+ /// For example, the [`TryFrom`] trait (conversion that returns a [`Result`])
+ /// has a blanket implementation for all types where a reverse [`Into`] implementation exists.
+ ///
+ /// ```ignore (illustrates std code, duplicating the impl in a doctest would be an error)
+ /// impl<T, U> TryFrom<U> for T where U: Into<T> {
+ ///     type Error = Infallible;
+ ///
+ ///     fn try_from(value: U) -> Result<Self, Infallible> {
+ ///         Ok(U::into(value))  // Never returns `Err`
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// # Future compatibility
+ ///
+ /// This enum has the same role as [the `!` “never” type][never],
+ /// which is unstable in this version of Rust.
+ /// When `!` is stabilized, we plan to make `Infallible` a type alias to it:
+ ///
+ /// ```ignore (illustrates future std change)
+ /// pub type Infallible = !;
+ /// ```
+ ///
+ /// … and eventually deprecate `Infallible`.
+ ///
+ /// However there is one case where `!` syntax can be used
+ /// before `!` is stabilized as a full-fledged type: in the position of a function’s return type.
+ /// Specifically, it is possible implementations for two different function pointer types:
+ ///
+ /// ```
+ /// trait MyTrait {}
+ /// impl MyTrait for fn() -> ! {}
+ /// impl MyTrait for fn() -> std::convert::Infallible {}
+ /// ```
+ ///
+ /// With `Infallible` being an enum, this code is valid.
+ /// However when `Infallible` becomes an alias for the never type,
+ /// the two `impl`s will start to overlap
+ /// and therefore will be disallowed by the language’s trait coherence rules.
+ ///
+ /// [never]: ../../std/primitive.never.html
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ #[derive(Copy)]
+ pub enum Infallible {}
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl Clone for Infallible {
+     fn clone(&self) -> Infallible {
+         match *self {}
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl fmt::Debug for Infallible {
+     fn fmt(&self, _: &mut fmt::Formatter<'_>) -> fmt::Result {
+         match *self {}
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl fmt::Display for Infallible {
+     fn fmt(&self, _: &mut fmt::Formatter<'_>) -> fmt::Result {
+         match *self {}
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl PartialEq for Infallible {
+     fn eq(&self, _: &Infallible) -> bool {
+         match *self {}
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl Eq for Infallible {}
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl PartialOrd for Infallible {
+     fn partial_cmp(&self, _other: &Self) -> Option<crate::cmp::Ordering> {
+         match *self {}
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl Ord for Infallible {
+     fn cmp(&self, _other: &Self) -> crate::cmp::Ordering {
+         match *self {}
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible", since = "1.34.0")]
+ impl From<!> for Infallible {
+     fn from(x: !) -> Self {
+         x
+     }
+ }
+ 
+ #[stable(feature = "convert_infallible_hash", since = "1.44.0")]
+ impl Hash for Infallible {
+     fn hash<H: Hasher>(&self, _: &mut H) {
+         match *self {}
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/convert/num.rs gcc-16-20251102/libgrust/rustc-lib/core/src/convert/num.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/convert/num.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/convert/num.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,533 ----
+ use super::{From, TryFrom};
+ use crate::num::TryFromIntError;
+ 
+ mod private {
+     /// This trait being unreachable from outside the crate
+     /// prevents other implementations of the `FloatToInt` trait,
+     /// which allows potentially adding more trait methods after the trait is `#[stable]`.
+     #[unstable(feature = "convert_float_to_int", issue = "67057")]
+     pub trait Sealed {}
+ }
+ 
+ /// Supporting trait for inherent methods of `f32` and `f64` such as `round_unchecked_to`.
+ /// Typically doesn’t need to be used directly.
+ #[unstable(feature = "convert_float_to_int", issue = "67057")]
+ pub trait FloatToInt<Int>: private::Sealed + Sized {
+     #[unstable(feature = "convert_float_to_int", issue = "67057")]
+     #[doc(hidden)]
+     unsafe fn to_int_unchecked(self) -> Int;
+ }
+ 
+ macro_rules! impl_float_to_int {
+     ( $Float: ident => $( $Int: ident )+ ) => {
+         #[unstable(feature = "convert_float_to_int", issue = "67057")]
+         impl private::Sealed for $Float {}
+         $(
+             #[unstable(feature = "convert_float_to_int", issue = "67057")]
+             impl FloatToInt<$Int> for $Float {
+                 #[doc(hidden)]
+                 #[inline]
+                 unsafe fn to_int_unchecked(self) -> $Int {
+                     // SAFETY: the safety contract must be upheld by the caller.
+                     unsafe { crate::intrinsics::float_to_int_unchecked(self) }
+                 }
+             }
+         )+
+     }
+ }
+ 
+ impl_float_to_int!(f32 => u8 u16 u32 u64 u128 usize i8 i16 i32 i64 i128 isize);
+ impl_float_to_int!(f64 => u8 u16 u32 u64 u128 usize i8 i16 i32 i64 i128 isize);
+ 
+ // Conversion traits for primitive integer and float types
+ // Conversions T -> T are covered by a blanket impl and therefore excluded
+ // Some conversions from and to usize/isize are not implemented due to portability concerns
+ macro_rules! impl_from {
+     ($Small: ty, $Large: ty, #[$attr:meta], $doc: expr) => {
+         #[$attr]
+         #[doc = $doc]
+         impl From<$Small> for $Large {
+             #[inline]
+             fn from(small: $Small) -> Self {
+                 small as Self
+             }
+         }
+     };
+     ($Small: ty, $Large: ty, #[$attr:meta]) => {
+         impl_from!($Small,
+                    $Large,
+                    #[$attr],
+                    concat!("Converts `",
+                            stringify!($Small),
+                            "` to `",
+                            stringify!($Large),
+                            "` losslessly."));
+     }
+ }
+ 
+ macro_rules! impl_from_bool {
+     ($target: ty, #[$attr:meta]) => {
+         impl_from!(bool, $target, #[$attr], concat!("Converts a `bool` to a `",
+             stringify!($target), "`. The resulting value is `0` for `false` and `1` for `true`
+ values.
+ 
+ # Examples
+ 
+ ```
+ assert_eq!(", stringify!($target), "::from(true), 1);
+ assert_eq!(", stringify!($target), "::from(false), 0);
+ ```"));
+     };
+ }
+ 
+ // Bool -> Any
+ impl_from_bool! { u8, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { u16, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { u32, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { u64, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { u128, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { usize, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { i8, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { i16, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { i32, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { i64, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { i128, #[stable(feature = "from_bool", since = "1.28.0")] }
+ impl_from_bool! { isize, #[stable(feature = "from_bool", since = "1.28.0")] }
+ 
+ // Unsigned -> Unsigned
+ impl_from! { u8, u16, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u8, u32, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u8, u64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u8, u128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { u8, usize, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u16, u32, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u16, u64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u16, u128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { u32, u64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u32, u128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { u64, u128, #[stable(feature = "i128", since = "1.26.0")] }
+ 
+ // Signed -> Signed
+ impl_from! { i8, i16, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i8, i32, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i8, i64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i8, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { i8, isize, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i16, i32, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i16, i64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i16, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { i32, i64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { i32, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { i64, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ 
+ // Unsigned -> Signed
+ impl_from! { u8, i16, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u8, i32, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u8, i64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u8, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { u16, i32, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u16, i64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u16, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { u32, i64, #[stable(feature = "lossless_int_conv", since = "1.5.0")] }
+ impl_from! { u32, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ impl_from! { u64, i128, #[stable(feature = "i128", since = "1.26.0")] }
+ 
+ // The C99 standard defines bounds on INTPTR_MIN, INTPTR_MAX, and UINTPTR_MAX
+ // which imply that pointer-sized integers must be at least 16 bits:
+ // https://port70.net/~nsz/c/c99/n1256.html#7.18.2.4
+ impl_from! { u16, usize, #[stable(feature = "lossless_iusize_conv", since = "1.26.0")] }
+ impl_from! { u8, isize, #[stable(feature = "lossless_iusize_conv", since = "1.26.0")] }
+ impl_from! { i16, isize, #[stable(feature = "lossless_iusize_conv", since = "1.26.0")] }
+ 
+ // RISC-V defines the possibility of a 128-bit address space (RV128).
+ 
+ // CHERI proposes 256-bit “capabilities”. Unclear if this would be relevant to usize/isize.
+ // https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/20171017a-cheri-poster.pdf
+ // http://www.csl.sri.com/users/neumann/2012resolve-cheri.pdf
+ 
+ // Note: integers can only be represented with full precision in a float if
+ // they fit in the significand, which is 24 bits in f32 and 53 bits in f64.
+ // Lossy float conversions are not implemented at this time.
+ 
+ // Signed -> Float
+ impl_from! { i8, f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { i8, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { i16, f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { i16, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { i32, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ 
+ // Unsigned -> Float
+ impl_from! { u8, f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { u8, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { u16, f32, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { u16, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ impl_from! { u32, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ 
+ // Float -> Float
+ impl_from! { f32, f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")] }
+ 
+ // no possible bounds violation
+ macro_rules! try_from_unbounded {
+     ($source:ty, $($target:ty),*) => {$(
+         #[stable(feature = "try_from", since = "1.34.0")]
+         impl TryFrom<$source> for $target {
+             type Error = TryFromIntError;
+ 
+             /// Try to create the target number type from a source
+             /// number type. This returns an error if the source value
+             /// is outside of the range of the target type.
+             #[inline]
+             fn try_from(value: $source) -> Result<Self, Self::Error> {
+                 Ok(value as Self)
+             }
+         }
+     )*}
+ }
+ 
+ // only negative bounds
+ macro_rules! try_from_lower_bounded {
+     ($source:ty, $($target:ty),*) => {$(
+         #[stable(feature = "try_from", since = "1.34.0")]
+         impl TryFrom<$source> for $target {
+             type Error = TryFromIntError;
+ 
+             /// Try to create the target number type from a source
+             /// number type. This returns an error if the source value
+             /// is outside of the range of the target type.
+             #[inline]
+             fn try_from(u: $source) -> Result<Self, Self::Error> {
+                 if u >= 0 {
+                     Ok(u as Self)
+                 } else {
+                     Err(TryFromIntError(()))
+                 }
+             }
+         }
+     )*}
+ }
+ 
+ // unsigned to signed (only positive bound)
+ macro_rules! try_from_upper_bounded {
+     ($source:ty, $($target:ty),*) => {$(
+         #[stable(feature = "try_from", since = "1.34.0")]
+         impl TryFrom<$source> for $target {
+             type Error = TryFromIntError;
+ 
+             /// Try to create the target number type from a source
+             /// number type. This returns an error if the source value
+             /// is outside of the range of the target type.
+             #[inline]
+             fn try_from(u: $source) -> Result<Self, Self::Error> {
+                 if u > (Self::MAX as $source) {
+                     Err(TryFromIntError(()))
+                 } else {
+                     Ok(u as Self)
+                 }
+             }
+         }
+     )*}
+ }
+ 
+ // all other cases
+ macro_rules! try_from_both_bounded {
+     ($source:ty, $($target:ty),*) => {$(
+         #[stable(feature = "try_from", since = "1.34.0")]
+         impl TryFrom<$source> for $target {
+             type Error = TryFromIntError;
+ 
+             /// Try to create the target number type from a source
+             /// number type. This returns an error if the source value
+             /// is outside of the range of the target type.
+             #[inline]
+             fn try_from(u: $source) -> Result<Self, Self::Error> {
+                 let min = Self::MIN as $source;
+                 let max = Self::MAX as $source;
+                 if u < min || u > max {
+                     Err(TryFromIntError(()))
+                 } else {
+                     Ok(u as Self)
+                 }
+             }
+         }
+     )*}
+ }
+ 
+ macro_rules! rev {
+     ($mac:ident, $source:ty, $($target:ty),*) => {$(
+         $mac!($target, $source);
+     )*}
+ }
+ 
+ // intra-sign conversions
+ try_from_upper_bounded!(u16, u8);
+ try_from_upper_bounded!(u32, u16, u8);
+ try_from_upper_bounded!(u64, u32, u16, u8);
+ try_from_upper_bounded!(u128, u64, u32, u16, u8);
+ 
+ try_from_both_bounded!(i16, i8);
+ try_from_both_bounded!(i32, i16, i8);
+ try_from_both_bounded!(i64, i32, i16, i8);
+ try_from_both_bounded!(i128, i64, i32, i16, i8);
+ 
+ // unsigned-to-signed
+ try_from_upper_bounded!(u8, i8);
+ try_from_upper_bounded!(u16, i8, i16);
+ try_from_upper_bounded!(u32, i8, i16, i32);
+ try_from_upper_bounded!(u64, i8, i16, i32, i64);
+ try_from_upper_bounded!(u128, i8, i16, i32, i64, i128);
+ 
+ // signed-to-unsigned
+ try_from_lower_bounded!(i8, u8, u16, u32, u64, u128);
+ try_from_lower_bounded!(i16, u16, u32, u64, u128);
+ try_from_lower_bounded!(i32, u32, u64, u128);
+ try_from_lower_bounded!(i64, u64, u128);
+ try_from_lower_bounded!(i128, u128);
+ try_from_both_bounded!(i16, u8);
+ try_from_both_bounded!(i32, u16, u8);
+ try_from_both_bounded!(i64, u32, u16, u8);
+ try_from_both_bounded!(i128, u64, u32, u16, u8);
+ 
+ // usize/isize
+ try_from_upper_bounded!(usize, isize);
+ try_from_lower_bounded!(isize, usize);
+ 
+ #[cfg(target_pointer_width = "16")]
+ mod ptr_try_from_impls {
+     use super::TryFromIntError;
+     use crate::convert::TryFrom;
+ 
+     try_from_upper_bounded!(usize, u8);
+     try_from_unbounded!(usize, u16, u32, u64, u128);
+     try_from_upper_bounded!(usize, i8, i16);
+     try_from_unbounded!(usize, i32, i64, i128);
+ 
+     try_from_both_bounded!(isize, u8);
+     try_from_lower_bounded!(isize, u16, u32, u64, u128);
+     try_from_both_bounded!(isize, i8);
+     try_from_unbounded!(isize, i16, i32, i64, i128);
+ 
+     rev!(try_from_upper_bounded, usize, u32, u64, u128);
+     rev!(try_from_lower_bounded, usize, i8, i16);
+     rev!(try_from_both_bounded, usize, i32, i64, i128);
+ 
+     rev!(try_from_upper_bounded, isize, u16, u32, u64, u128);
+     rev!(try_from_both_bounded, isize, i32, i64, i128);
+ }
+ 
+ #[cfg(target_pointer_width = "32")]
+ mod ptr_try_from_impls {
+     use super::TryFromIntError;
+     use crate::convert::TryFrom;
+ 
+     try_from_upper_bounded!(usize, u8, u16);
+     try_from_unbounded!(usize, u32, u64, u128);
+     try_from_upper_bounded!(usize, i8, i16, i32);
+     try_from_unbounded!(usize, i64, i128);
+ 
+     try_from_both_bounded!(isize, u8, u16);
+     try_from_lower_bounded!(isize, u32, u64, u128);
+     try_from_both_bounded!(isize, i8, i16);
+     try_from_unbounded!(isize, i32, i64, i128);
+ 
+     rev!(try_from_unbounded, usize, u32);
+     rev!(try_from_upper_bounded, usize, u64, u128);
+     rev!(try_from_lower_bounded, usize, i8, i16, i32);
+     rev!(try_from_both_bounded, usize, i64, i128);
+ 
+     rev!(try_from_unbounded, isize, u16);
+     rev!(try_from_upper_bounded, isize, u32, u64, u128);
+     rev!(try_from_unbounded, isize, i32);
+     rev!(try_from_both_bounded, isize, i64, i128);
+ }
+ 
+ #[cfg(target_pointer_width = "64")]
+ mod ptr_try_from_impls {
+     use super::TryFromIntError;
+     use crate::convert::TryFrom;
+ 
+     try_from_upper_bounded!(usize, u8, u16, u32);
+     try_from_unbounded!(usize, u64, u128);
+     try_from_upper_bounded!(usize, i8, i16, i32, i64);
+     try_from_unbounded!(usize, i128);
+ 
+     try_from_both_bounded!(isize, u8, u16, u32);
+     try_from_lower_bounded!(isize, u64, u128);
+     try_from_both_bounded!(isize, i8, i16, i32);
+     try_from_unbounded!(isize, i64, i128);
+ 
+     rev!(try_from_unbounded, usize, u32, u64);
+     rev!(try_from_upper_bounded, usize, u128);
+     rev!(try_from_lower_bounded, usize, i8, i16, i32, i64);
+     rev!(try_from_both_bounded, usize, i128);
+ 
+     rev!(try_from_unbounded, isize, u16, u32);
+     rev!(try_from_upper_bounded, isize, u64, u128);
+     rev!(try_from_unbounded, isize, i32, i64);
+     rev!(try_from_both_bounded, isize, i128);
+ }
+ 
+ // Conversion traits for non-zero integer types
+ use crate::num::NonZeroI128;
+ use crate::num::NonZeroI16;
+ use crate::num::NonZeroI32;
+ use crate::num::NonZeroI64;
+ use crate::num::NonZeroI8;
+ use crate::num::NonZeroIsize;
+ use crate::num::NonZeroU128;
+ use crate::num::NonZeroU16;
+ use crate::num::NonZeroU32;
+ use crate::num::NonZeroU64;
+ use crate::num::NonZeroU8;
+ use crate::num::NonZeroUsize;
+ 
+ macro_rules! nzint_impl_from {
+     ($Small: ty, $Large: ty, #[$attr:meta], $doc: expr) => {
+         #[$attr]
+         #[doc = $doc]
+         impl From<$Small> for $Large {
+             #[inline]
+             fn from(small: $Small) -> Self {
+                 // SAFETY: input type guarantees the value is non-zero
+                 unsafe {
+                     Self::new_unchecked(small.get().into())
+                 }
+             }
+         }
+     };
+     ($Small: ty, $Large: ty, #[$attr:meta]) => {
+         nzint_impl_from!($Small,
+                    $Large,
+                    #[$attr],
+                    concat!("Converts `",
+                            stringify!($Small),
+                            "` to `",
+                            stringify!($Large),
+                            "` losslessly."));
+     }
+ }
+ 
+ // Non-zero Unsigned -> Non-zero Unsigned
+ nzint_impl_from! { NonZeroU8, NonZeroU16, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroU32, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroU64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroU128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroUsize, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroU32, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroU64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroU128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroUsize, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU32, NonZeroU64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU32, NonZeroU128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU64, NonZeroU128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ 
+ // Non-zero Signed -> Non-zero Signed
+ nzint_impl_from! { NonZeroI8, NonZeroI16, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI8, NonZeroI32, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI8, NonZeroI64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI8, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI8, NonZeroIsize, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI16, NonZeroI32, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI16, NonZeroI64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI16, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI16, NonZeroIsize, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI32, NonZeroI64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI32, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroI64, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ 
+ // NonZero UnSigned -> Non-zero Signed
+ nzint_impl_from! { NonZeroU8, NonZeroI16, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroI32, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroI64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU8, NonZeroIsize, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroI32, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroI64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU16, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU32, NonZeroI64, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU32, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ nzint_impl_from! { NonZeroU64, NonZeroI128, #[stable(feature = "nz_int_conv", since = "1.41.0")] }
+ 
+ macro_rules! nzint_impl_try_from_int {
+     ($Int: ty, $NonZeroInt: ty, #[$attr:meta], $doc: expr) => {
+         #[$attr]
+         #[doc = $doc]
+         impl TryFrom<$Int> for $NonZeroInt {
+             type Error = TryFromIntError;
+ 
+             #[inline]
+             fn try_from(value: $Int) -> Result<Self, Self::Error> {
+                 Self::new(value).ok_or(TryFromIntError(()))
+             }
+         }
+     };
+     ($Int: ty, $NonZeroInt: ty, #[$attr:meta]) => {
+         nzint_impl_try_from_int!($Int,
+                                  $NonZeroInt,
+                                  #[$attr],
+                                  concat!("Attempts to convert `",
+                                          stringify!($Int),
+                                          "` to `",
+                                          stringify!($NonZeroInt),
+                                          "`."));
+     }
+ }
+ 
+ // Int -> Non-zero Int
+ nzint_impl_try_from_int! { u8, NonZeroU8, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { u16, NonZeroU16, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { u32, NonZeroU32, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { u64, NonZeroU64, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { u128, NonZeroU128, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { usize, NonZeroUsize, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { i8, NonZeroI8, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { i16, NonZeroI16, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { i32, NonZeroI32, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { i64, NonZeroI64, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { i128, NonZeroI128, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ nzint_impl_try_from_int! { isize, NonZeroIsize, #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] }
+ 
+ macro_rules! nzint_impl_try_from_nzint {
+     ($From:ty => $To:ty, $doc: expr) => {
+         #[stable(feature = "nzint_try_from_nzint_conv", since = "1.49.0")]
+         #[doc = $doc]
+         impl TryFrom<$From> for $To {
+             type Error = TryFromIntError;
+ 
+             #[inline]
+             fn try_from(value: $From) -> Result<Self, Self::Error> {
+                 TryFrom::try_from(value.get()).map(|v| {
+                     // SAFETY: $From is a NonZero type, so v is not zero.
+                     unsafe { Self::new_unchecked(v) }
+                 })
+             }
+         }
+     };
+     ($To:ty: $($From: ty),*) => {$(
+         nzint_impl_try_from_nzint!(
+             $From => $To,
+             concat!(
+                 "Attempts to convert `",
+                 stringify!($From),
+                 "` to `",
+                 stringify!($To),
+                 "`.",
+             )
+         );
+     )*};
+ }
+ 
+ // Non-zero int -> non-zero unsigned int
+ nzint_impl_try_from_nzint! { NonZeroU8: NonZeroI8, NonZeroU16, NonZeroI16, NonZeroU32, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroU16: NonZeroI8, NonZeroI16, NonZeroU32, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroU32: NonZeroI8, NonZeroI16, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroU64: NonZeroI8, NonZeroI16, NonZeroI32, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroU128: NonZeroI8, NonZeroI16, NonZeroI32, NonZeroI64, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroUsize: NonZeroI8, NonZeroI16, NonZeroU32, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroIsize }
+ 
+ // Non-zero int -> non-zero signed int
+ nzint_impl_try_from_nzint! { NonZeroI8: NonZeroU8, NonZeroU16, NonZeroI16, NonZeroU32, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroI16: NonZeroU16, NonZeroU32, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroI32: NonZeroU32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroI64: NonZeroU64, NonZeroU128, NonZeroI128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroI128: NonZeroU128, NonZeroUsize, NonZeroIsize }
+ nzint_impl_try_from_nzint! { NonZeroIsize: NonZeroU16, NonZeroU32, NonZeroI32, NonZeroU64, NonZeroI64, NonZeroU128, NonZeroI128, NonZeroUsize }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/default.rs gcc-16-20251102/libgrust/rustc-lib/core/src/default.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/default.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/default.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,200 ----
+ //! The `Default` trait for types which may have meaningful default values.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ /// A trait for giving a type a useful default value.
+ ///
+ /// Sometimes, you want to fall back to some kind of default value, and
+ /// don't particularly care what it is. This comes up often with `struct`s
+ /// that define a set of options:
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// struct SomeOptions {
+ ///     foo: i32,
+ ///     bar: f32,
+ /// }
+ /// ```
+ ///
+ /// How can we define some default values? You can use `Default`:
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// #[derive(Default)]
+ /// struct SomeOptions {
+ ///     foo: i32,
+ ///     bar: f32,
+ /// }
+ ///
+ /// fn main() {
+ ///     let options: SomeOptions = Default::default();
+ /// }
+ /// ```
+ ///
+ /// Now, you get all of the default values. Rust implements `Default` for various primitives types.
+ ///
+ /// If you want to override a particular option, but still retain the other defaults:
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// # #[derive(Default)]
+ /// # struct SomeOptions {
+ /// #     foo: i32,
+ /// #     bar: f32,
+ /// # }
+ /// fn main() {
+ ///     let options = SomeOptions { foo: 42, ..Default::default() };
+ /// }
+ /// ```
+ ///
+ /// ## Derivable
+ ///
+ /// This trait can be used with `#[derive]` if all of the type's fields implement
+ /// `Default`. When `derive`d, it will use the default value for each field's type.
+ ///
+ /// ## How can I implement `Default`?
+ ///
+ /// Provide an implementation for the `default()` method that returns the value of
+ /// your type that should be the default:
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// enum Kind {
+ ///     A,
+ ///     B,
+ ///     C,
+ /// }
+ ///
+ /// impl Default for Kind {
+ ///     fn default() -> Self { Kind::A }
+ /// }
+ /// ```
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// #[derive(Default)]
+ /// struct SomeOptions {
+ ///     foo: i32,
+ ///     bar: f32,
+ /// }
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Default: Sized {
+     /// Returns the "default value" for a type.
+     ///
+     /// Default values are often some kind of initial value, identity value, or anything else that
+     /// may make sense as a default.
+     ///
+     /// # Examples
+     ///
+     /// Using built-in default values:
+     ///
+     /// ```
+     /// let i: i8 = Default::default();
+     /// let (x, y): (Option<String>, f64) = Default::default();
+     /// let (a, b, (c, d)): (i32, u32, (bool, bool)) = Default::default();
+     /// ```
+     ///
+     /// Making your own:
+     ///
+     /// ```
+     /// # #[allow(dead_code)]
+     /// enum Kind {
+     ///     A,
+     ///     B,
+     ///     C,
+     /// }
+     ///
+     /// impl Default for Kind {
+     ///     fn default() -> Self { Kind::A }
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn default() -> Self;
+ }
+ 
+ /// Return the default value of a type according to the `Default` trait.
+ ///
+ /// The type to return is inferred from context; this is equivalent to
+ /// `Default::default()` but shorter to type.
+ ///
+ /// For example:
+ /// ```
+ /// #![feature(default_free_fn)]
+ ///
+ /// use std::default::default;
+ ///
+ /// #[derive(Default)]
+ /// struct AppConfig {
+ ///     foo: FooConfig,
+ ///     bar: BarConfig,
+ /// }
+ ///
+ /// #[derive(Default)]
+ /// struct FooConfig {
+ ///     foo: i32,
+ /// }
+ ///
+ /// #[derive(Default)]
+ /// struct BarConfig {
+ ///     bar: f32,
+ ///     baz: u8,
+ /// }
+ ///
+ /// fn main() {
+ ///     let options = AppConfig {
+ ///         foo: default(),
+ ///         bar: BarConfig {
+ ///             bar: 10.1,
+ ///             ..default()
+ ///         },
+ ///     };
+ /// }
+ /// ```
+ #[unstable(feature = "default_free_fn", issue = "73014")]
+ #[inline]
+ pub fn default<T: Default>() -> T {
+     Default::default()
+ }
+ 
+ /// Derive macro generating an impl of the trait `Default`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics)]
+ pub macro Default($item:item) {
+     /* compiler built-in */
+ }
+ 
+ macro_rules! default_impl {
+     ($t:ty, $v:expr, $doc:tt) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Default for $t {
+             #[inline]
+             #[doc = $doc]
+             fn default() -> $t { $v }
+         }
+     }
+ }
+ 
+ default_impl! { (), (), "Returns the default value of `()`" }
+ default_impl! { bool, false, "Returns the default value of `false`" }
+ default_impl! { char, '\x00', "Returns the default value of `\\x00`" }
+ 
+ default_impl! { usize, 0, "Returns the default value of `0`" }
+ default_impl! { u8, 0, "Returns the default value of `0`" }
+ default_impl! { u16, 0, "Returns the default value of `0`" }
+ default_impl! { u32, 0, "Returns the default value of `0`" }
+ default_impl! { u64, 0, "Returns the default value of `0`" }
+ default_impl! { u128, 0, "Returns the default value of `0`" }
+ 
+ default_impl! { isize, 0, "Returns the default value of `0`" }
+ default_impl! { i8, 0, "Returns the default value of `0`" }
+ default_impl! { i16, 0, "Returns the default value of `0`" }
+ default_impl! { i32, 0, "Returns the default value of `0`" }
+ default_impl! { i64, 0, "Returns the default value of `0`" }
+ default_impl! { i128, 0, "Returns the default value of `0`" }
+ 
+ default_impl! { f32, 0.0f32, "Returns the default value of `0.0`" }
+ default_impl! { f64, 0.0f64, "Returns the default value of `0.0`" }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ffi.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ffi.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ffi.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ffi.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,407 ----
+ #![stable(feature = "", since = "1.30.0")]
+ #![allow(non_camel_case_types)]
+ 
+ //! Utilities related to foreign function interface (FFI) bindings.
+ 
+ use crate::fmt;
+ use crate::marker::PhantomData;
+ use crate::ops::{Deref, DerefMut};
+ 
+ /// Equivalent to C's `void` type when used as a [pointer].
+ ///
+ /// In essence, `*const c_void` is equivalent to C's `const void*`
+ /// and `*mut c_void` is equivalent to C's `void*`. That said, this is
+ /// *not* the same as C's `void` return type, which is Rust's `()` type.
+ ///
+ /// To model pointers to opaque types in FFI, until `extern type` is
+ /// stabilized, it is recommended to use a newtype wrapper around an empty
+ /// byte array. See the [Nomicon] for details.
+ ///
+ /// One could use `std::os::raw::c_void` if they want to support old Rust
+ /// compiler down to 1.1.0. After Rust 1.30.0, it was re-exported by
+ /// this definition. For more information, please read [RFC 2521].
+ ///
+ /// [pointer]: ../../std/primitive.pointer.html
+ /// [Nomicon]: https://doc.rust-lang.org/nomicon/ffi.html#representing-opaque-structs
+ /// [RFC 2521]: https://github.com/rust-lang/rfcs/blob/master/text/2521-c_void-reunification.md
+ // N.B., for LLVM to recognize the void pointer type and by extension
+ //     functions like malloc(), we need to have it represented as i8* in
+ //     LLVM bitcode. The enum used here ensures this and prevents misuse
+ //     of the "raw" type by only having private variants. We need two
+ //     variants, because the compiler complains about the repr attribute
+ //     otherwise and we need at least one variant as otherwise the enum
+ //     would be uninhabited and at least dereferencing such pointers would
+ //     be UB.
+ #[repr(u8)]
+ #[stable(feature = "core_c_void", since = "1.30.0")]
+ pub enum c_void {
+     #[unstable(
+         feature = "c_void_variant",
+         reason = "temporary implementation detail",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     __variant1,
+     #[unstable(
+         feature = "c_void_variant",
+         reason = "temporary implementation detail",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     __variant2,
+ }
+ 
+ #[stable(feature = "std_debug", since = "1.16.0")]
+ impl fmt::Debug for c_void {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("c_void")
+     }
+ }
+ 
+ /// Basic implementation of a `va_list`.
+ // The name is WIP, using `VaListImpl` for now.
+ #[cfg(any(
+     all(not(target_arch = "aarch64"), not(target_arch = "powerpc"), not(target_arch = "x86_64")),
+     all(target_arch = "aarch64", any(target_os = "macos", target_os = "ios")),
+     target_arch = "wasm32",
+     target_arch = "asmjs",
+     windows
+ ))]
+ #[repr(transparent)]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ #[lang = "va_list"]
+ pub struct VaListImpl<'f> {
+     ptr: *mut c_void,
+ 
+     // Invariant over `'f`, so each `VaListImpl<'f>` object is tied to
+     // the region of the function it's defined in
+     _marker: PhantomData<&'f mut &'f c_void>,
+ }
+ 
+ #[cfg(any(
+     all(not(target_arch = "aarch64"), not(target_arch = "powerpc"), not(target_arch = "x86_64")),
+     all(target_arch = "aarch64", any(target_os = "macos", target_os = "ios")),
+     target_arch = "wasm32",
+     target_arch = "asmjs",
+     windows
+ ))]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'f> fmt::Debug for VaListImpl<'f> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(f, "va_list* {:p}", self.ptr)
+     }
+ }
+ 
+ /// AArch64 ABI implementation of a `va_list`. See the
+ /// [AArch64 Procedure Call Standard] for more details.
+ ///
+ /// [AArch64 Procedure Call Standard]:
+ /// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf
+ #[cfg(all(
+     target_arch = "aarch64",
+     not(any(target_os = "macos", target_os = "ios")),
+     not(windows)
+ ))]
+ #[repr(C)]
+ #[derive(Debug)]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ #[lang = "va_list"]
+ pub struct VaListImpl<'f> {
+     stack: *mut c_void,
+     gr_top: *mut c_void,
+     vr_top: *mut c_void,
+     gr_offs: i32,
+     vr_offs: i32,
+     _marker: PhantomData<&'f mut &'f c_void>,
+ }
+ 
+ /// PowerPC ABI implementation of a `va_list`.
+ #[cfg(all(target_arch = "powerpc", not(windows)))]
+ #[repr(C)]
+ #[derive(Debug)]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ #[lang = "va_list"]
+ pub struct VaListImpl<'f> {
+     gpr: u8,
+     fpr: u8,
+     reserved: u16,
+     overflow_arg_area: *mut c_void,
+     reg_save_area: *mut c_void,
+     _marker: PhantomData<&'f mut &'f c_void>,
+ }
+ 
+ /// x86_64 ABI implementation of a `va_list`.
+ #[cfg(all(target_arch = "x86_64", not(windows)))]
+ #[repr(C)]
+ #[derive(Debug)]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ #[lang = "va_list"]
+ pub struct VaListImpl<'f> {
+     gp_offset: i32,
+     fp_offset: i32,
+     overflow_arg_area: *mut c_void,
+     reg_save_area: *mut c_void,
+     _marker: PhantomData<&'f mut &'f c_void>,
+ }
+ 
+ /// A wrapper for a `va_list`
+ #[repr(transparent)]
+ #[derive(Debug)]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ pub struct VaList<'a, 'f: 'a> {
+     #[cfg(any(
+         all(
+             not(target_arch = "aarch64"),
+             not(target_arch = "powerpc"),
+             not(target_arch = "x86_64")
+         ),
+         all(target_arch = "aarch64", any(target_os = "macos", target_os = "ios")),
+         target_arch = "wasm32",
+         target_arch = "asmjs",
+         windows
+     ))]
+     inner: VaListImpl<'f>,
+ 
+     #[cfg(all(
+         any(target_arch = "aarch64", target_arch = "powerpc", target_arch = "x86_64"),
+         any(not(target_arch = "aarch64"), not(any(target_os = "macos", target_os = "ios"))),
+         not(target_arch = "wasm32"),
+         not(target_arch = "asmjs"),
+         not(windows)
+     ))]
+     inner: &'a mut VaListImpl<'f>,
+ 
+     _marker: PhantomData<&'a mut VaListImpl<'f>>,
+ }
+ 
+ #[cfg(any(
+     all(not(target_arch = "aarch64"), not(target_arch = "powerpc"), not(target_arch = "x86_64")),
+     all(target_arch = "aarch64", any(target_os = "macos", target_os = "ios")),
+     target_arch = "wasm32",
+     target_arch = "asmjs",
+     windows
+ ))]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'f> VaListImpl<'f> {
+     /// Convert a `VaListImpl` into a `VaList` that is binary-compatible with C's `va_list`.
+     #[inline]
+     pub fn as_va_list<'a>(&'a mut self) -> VaList<'a, 'f> {
+         VaList { inner: VaListImpl { ..*self }, _marker: PhantomData }
+     }
+ }
+ 
+ #[cfg(all(
+     any(target_arch = "aarch64", target_arch = "powerpc", target_arch = "x86_64"),
+     any(not(target_arch = "aarch64"), not(any(target_os = "macos", target_os = "ios"))),
+     not(target_arch = "wasm32"),
+     not(target_arch = "asmjs"),
+     not(windows)
+ ))]
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'f> VaListImpl<'f> {
+     /// Convert a `VaListImpl` into a `VaList` that is binary-compatible with C's `va_list`.
+     #[inline]
+     pub fn as_va_list<'a>(&'a mut self) -> VaList<'a, 'f> {
+         VaList { inner: self, _marker: PhantomData }
+     }
+ }
+ 
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'a, 'f: 'a> Deref for VaList<'a, 'f> {
+     type Target = VaListImpl<'f>;
+ 
+     #[inline]
+     fn deref(&self) -> &VaListImpl<'f> {
+         &self.inner
+     }
+ }
+ 
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'a, 'f: 'a> DerefMut for VaList<'a, 'f> {
+     #[inline]
+     fn deref_mut(&mut self) -> &mut VaListImpl<'f> {
+         &mut self.inner
+     }
+ }
+ 
+ // The VaArgSafe trait needs to be used in public interfaces, however, the trait
+ // itself must not be allowed to be used outside this module. Allowing users to
+ // implement the trait for a new type (thereby allowing the va_arg intrinsic to
+ // be used on a new type) is likely to cause undefined behavior.
+ //
+ // FIXME(dlrobertson): In order to use the VaArgSafe trait in a public interface
+ // but also ensure it cannot be used elsewhere, the trait needs to be public
+ // within a private module. Once RFC 2145 has been implemented look into
+ // improving this.
+ mod sealed_trait {
+     /// Trait which permits the allowed types to be used with [super::VaListImpl::arg].
+     #[unstable(
+         feature = "c_variadic",
+         reason = "the `c_variadic` feature has not been properly tested on \
+                   all supported platforms",
+         issue = "44930"
+     )]
+     pub trait VaArgSafe {}
+ }
+ 
+ macro_rules! impl_va_arg_safe {
+     ($($t:ty),+) => {
+         $(
+             #[unstable(feature = "c_variadic",
+                        reason = "the `c_variadic` feature has not been properly tested on \
+                                  all supported platforms",
+                        issue = "44930")]
+             impl sealed_trait::VaArgSafe for $t {}
+         )+
+     }
+ }
+ 
+ impl_va_arg_safe! {i8, i16, i32, i64, usize}
+ impl_va_arg_safe! {u8, u16, u32, u64, isize}
+ impl_va_arg_safe! {f64}
+ 
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<T> sealed_trait::VaArgSafe for *mut T {}
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<T> sealed_trait::VaArgSafe for *const T {}
+ 
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'f> VaListImpl<'f> {
+     /// Advance to the next arg.
+     #[inline]
+     pub unsafe fn arg<T: sealed_trait::VaArgSafe>(&mut self) -> T {
+         // SAFETY: the caller must uphold the safety contract for `va_arg`.
+         unsafe { va_arg(self) }
+     }
+ 
+     /// Copies the `va_list` at the current location.
+     pub unsafe fn with_copy<F, R>(&self, f: F) -> R
+     where
+         F: for<'copy> FnOnce(VaList<'copy, 'f>) -> R,
+     {
+         let mut ap = self.clone();
+         let ret = f(ap.as_va_list());
+         // SAFETY: the caller must uphold the safety contract for `va_end`.
+         unsafe {
+             va_end(&mut ap);
+         }
+         ret
+     }
+ }
+ 
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'f> Clone for VaListImpl<'f> {
+     #[inline]
+     fn clone(&self) -> Self {
+         let mut dest = crate::mem::MaybeUninit::uninit();
+         // SAFETY: we write to the `MaybeUninit`, thus it is initialized and `assume_init` is legal
+         unsafe {
+             va_copy(dest.as_mut_ptr(), self);
+             dest.assume_init()
+         }
+     }
+ }
+ 
+ #[unstable(
+     feature = "c_variadic",
+     reason = "the `c_variadic` feature has not been properly tested on \
+               all supported platforms",
+     issue = "44930"
+ )]
+ impl<'f> Drop for VaListImpl<'f> {
+     fn drop(&mut self) {
+         // FIXME: this should call `va_end`, but there's no clean way to
+         // guarantee that `drop` always gets inlined into its caller,
+         // so the `va_end` would get directly called from the same function as
+         // the corresponding `va_copy`. `man va_end` states that C requires this,
+         // and LLVM basically follows the C semantics, so we need to make sure
+         // that `va_end` is always called from the same function as `va_copy`.
+         // For more details, see https://github.com/rust-lang/rust/pull/59625
+         // and https://llvm.org/docs/LangRef.html#llvm-va-end-intrinsic.
+         //
+         // This works for now, since `va_end` is a no-op on all current LLVM targets.
+     }
+ }
+ 
+ extern "rust-intrinsic" {
+     /// Destroy the arglist `ap` after initialization with `va_start` or
+     /// `va_copy`.
+     fn va_end(ap: &mut VaListImpl<'_>);
+ 
+     /// Copies the current location of arglist `src` to the arglist `dst`.
+     fn va_copy<'f>(dest: *mut VaListImpl<'f>, src: &VaListImpl<'f>);
+ 
+     /// Loads an argument of type `T` from the `va_list` `ap` and increment the
+     /// argument `ap` points to.
+     fn va_arg<T: sealed_trait::VaArgSafe>(ap: &mut VaListImpl<'_>) -> T;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/builders.rs gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/builders.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/builders.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/builders.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,952 ----
+ #![allow(unused_imports)]
+ 
+ use crate::fmt::{self, Debug, Formatter};
+ 
+ struct PadAdapter<'buf, 'state> {
+     buf: &'buf mut (dyn fmt::Write + 'buf),
+     state: &'state mut PadAdapterState,
+ }
+ 
+ struct PadAdapterState {
+     on_newline: bool,
+ }
+ 
+ impl Default for PadAdapterState {
+     fn default() -> Self {
+         PadAdapterState { on_newline: true }
+     }
+ }
+ 
+ impl<'buf, 'state> PadAdapter<'buf, 'state> {
+     fn wrap<'slot, 'fmt: 'buf + 'slot>(
+         fmt: &'fmt mut fmt::Formatter<'_>,
+         slot: &'slot mut Option<Self>,
+         state: &'state mut PadAdapterState,
+     ) -> fmt::Formatter<'slot> {
+         fmt.wrap_buf(move |buf| {
+             *slot = Some(PadAdapter { buf, state });
+             slot.as_mut().unwrap()
+         })
+     }
+ }
+ 
+ impl fmt::Write for PadAdapter<'_, '_> {
+     fn write_str(&mut self, mut s: &str) -> fmt::Result {
+         while !s.is_empty() {
+             if self.state.on_newline {
+                 self.buf.write_str("    ")?;
+             }
+ 
+             let split = match s.find('\n') {
+                 Some(pos) => {
+                     self.state.on_newline = true;
+                     pos + 1
+                 }
+                 None => {
+                     self.state.on_newline = false;
+                     s.len()
+                 }
+             };
+             self.buf.write_str(&s[..split])?;
+             s = &s[split..];
+         }
+ 
+         Ok(())
+     }
+ }
+ 
+ /// A struct to help with [`fmt::Debug`](Debug) implementations.
+ ///
+ /// This is useful when you wish to output a formatted struct as a part of your
+ /// [`Debug::fmt`] implementation.
+ ///
+ /// This can be constructed by the [`Formatter::debug_struct`] method.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Foo {
+ ///     bar: i32,
+ ///     baz: String,
+ /// }
+ ///
+ /// impl fmt::Debug for Foo {
+ ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+ ///         fmt.debug_struct("Foo")
+ ///            .field("bar", &self.bar)
+ ///            .field("baz", &self.baz)
+ ///            .finish()
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(
+ ///     format!("{:?}", Foo { bar: 10, baz: "Hello World".to_string() }),
+ ///     "Foo { bar: 10, baz: \"Hello World\" }",
+ /// );
+ /// ```
+ #[must_use = "must eventually call `finish()` on Debug builders"]
+ #[allow(missing_debug_implementations)]
+ #[stable(feature = "debug_builders", since = "1.2.0")]
+ pub struct DebugStruct<'a, 'b: 'a> {
+     fmt: &'a mut fmt::Formatter<'b>,
+     result: fmt::Result,
+     has_fields: bool,
+ }
+ 
+ pub(super) fn debug_struct_new<'a, 'b>(
+     fmt: &'a mut fmt::Formatter<'b>,
+     name: &str,
+ ) -> DebugStruct<'a, 'b> {
+     let result = fmt.write_str(name);
+     DebugStruct { fmt, result, has_fields: false }
+ }
+ 
+ impl<'a, 'b: 'a> DebugStruct<'a, 'b> {
+     /// Adds a new field to the generated struct output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Bar {
+     ///     bar: i32,
+     ///     another: String,
+     /// }
+     ///
+     /// impl fmt::Debug for Bar {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_struct("Bar")
+     ///            .field("bar", &self.bar) // We add `bar` field.
+     ///            .field("another", &self.another) // We add `another` field.
+     ///            // We even add a field which doesn't exist (because why not?).
+     ///            .field("not_existing_field", &1)
+     ///            .finish() // We're good to go!
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Bar { bar: 10, another: "Hello World".to_string() }),
+     ///     "Bar { bar: 10, another: \"Hello World\", not_existing_field: 1 }",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn field(&mut self, name: &str, value: &dyn fmt::Debug) -> &mut Self {
+         self.result = self.result.and_then(|_| {
+             if self.is_pretty() {
+                 if !self.has_fields {
+                     self.fmt.write_str(" {\n")?;
+                 }
+                 let mut slot = None;
+                 let mut state = Default::default();
+                 let mut writer = PadAdapter::wrap(&mut self.fmt, &mut slot, &mut state);
+                 writer.write_str(name)?;
+                 writer.write_str(": ")?;
+                 value.fmt(&mut writer)?;
+                 writer.write_str(",\n")
+             } else {
+                 let prefix = if self.has_fields { ", " } else { " { " };
+                 self.fmt.write_str(prefix)?;
+                 self.fmt.write_str(name)?;
+                 self.fmt.write_str(": ")?;
+                 value.fmt(self.fmt)
+             }
+         });
+ 
+         self.has_fields = true;
+         self
+     }
+ 
+     /// Marks the struct as non-exhaustive, indicating to the reader that there are some other
+     /// fields that are not shown in the debug representation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// # #![feature(debug_non_exhaustive)]
+     /// use std::fmt;
+     ///
+     /// struct Bar {
+     ///     bar: i32,
+     ///     hidden: f32,
+     /// }
+     ///
+     /// impl fmt::Debug for Bar {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_struct("Bar")
+     ///            .field("bar", &self.bar)
+     ///            .finish_non_exhaustive() // Show that some other field(s) exist.
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Bar { bar: 10, hidden: 1.0 }),
+     ///     "Bar { bar: 10, .. }",
+     /// );
+     /// ```
+     #[unstable(feature = "debug_non_exhaustive", issue = "67364")]
+     pub fn finish_non_exhaustive(&mut self) -> fmt::Result {
+         self.result = self.result.and_then(|_| {
+             // Draw non-exhaustive dots (`..`), and open brace if necessary (no fields).
+             if self.is_pretty() {
+                 if !self.has_fields {
+                     self.fmt.write_str(" {\n")?;
+                 }
+                 let mut slot = None;
+                 let mut state = Default::default();
+                 let mut writer = PadAdapter::wrap(&mut self.fmt, &mut slot, &mut state);
+                 writer.write_str("..\n")?;
+             } else {
+                 if self.has_fields {
+                     self.fmt.write_str(", ..")?;
+                 } else {
+                     self.fmt.write_str(" { ..")?;
+                 }
+             }
+             if self.is_pretty() {
+                 self.fmt.write_str("}")?
+             } else {
+                 self.fmt.write_str(" }")?;
+             }
+             Ok(())
+         });
+         self.result
+     }
+ 
+     /// Finishes output and returns any error encountered.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Bar {
+     ///     bar: i32,
+     ///     baz: String,
+     /// }
+     ///
+     /// impl fmt::Debug for Bar {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_struct("Bar")
+     ///            .field("bar", &self.bar)
+     ///            .field("baz", &self.baz)
+     ///            .finish() // You need to call it to "finish" the
+     ///                      // struct formatting.
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Bar { bar: 10, baz: "Hello World".to_string() }),
+     ///     "Bar { bar: 10, baz: \"Hello World\" }",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn finish(&mut self) -> fmt::Result {
+         if self.has_fields {
+             self.result = self.result.and_then(|_| {
+                 if self.is_pretty() { self.fmt.write_str("}") } else { self.fmt.write_str(" }") }
+             });
+         }
+         self.result
+     }
+ 
+     fn is_pretty(&self) -> bool {
+         self.fmt.alternate()
+     }
+ }
+ 
+ /// A struct to help with [`fmt::Debug`](Debug) implementations.
+ ///
+ /// This is useful when you wish to output a formatted tuple as a part of your
+ /// [`Debug::fmt`] implementation.
+ ///
+ /// This can be constructed by the [`Formatter::debug_tuple`] method.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Foo(i32, String);
+ ///
+ /// impl fmt::Debug for Foo {
+ ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+ ///         fmt.debug_tuple("Foo")
+ ///            .field(&self.0)
+ ///            .field(&self.1)
+ ///            .finish()
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(
+ ///     format!("{:?}", Foo(10, "Hello World".to_string())),
+ ///     "Foo(10, \"Hello World\")",
+ /// );
+ /// ```
+ #[must_use = "must eventually call `finish()` on Debug builders"]
+ #[allow(missing_debug_implementations)]
+ #[stable(feature = "debug_builders", since = "1.2.0")]
+ pub struct DebugTuple<'a, 'b: 'a> {
+     fmt: &'a mut fmt::Formatter<'b>,
+     result: fmt::Result,
+     fields: usize,
+     empty_name: bool,
+ }
+ 
+ pub(super) fn debug_tuple_new<'a, 'b>(
+     fmt: &'a mut fmt::Formatter<'b>,
+     name: &str,
+ ) -> DebugTuple<'a, 'b> {
+     let result = fmt.write_str(name);
+     DebugTuple { fmt, result, fields: 0, empty_name: name.is_empty() }
+ }
+ 
+ impl<'a, 'b: 'a> DebugTuple<'a, 'b> {
+     /// Adds a new field to the generated tuple struct output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32, String);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_tuple("Foo")
+     ///            .field(&self.0) // We add the first field.
+     ///            .field(&self.1) // We add the second field.
+     ///            .finish() // We're good to go!
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(10, "Hello World".to_string())),
+     ///     "Foo(10, \"Hello World\")",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn field(&mut self, value: &dyn fmt::Debug) -> &mut Self {
+         self.result = self.result.and_then(|_| {
+             if self.is_pretty() {
+                 if self.fields == 0 {
+                     self.fmt.write_str("(\n")?;
+                 }
+                 let mut slot = None;
+                 let mut state = Default::default();
+                 let mut writer = PadAdapter::wrap(&mut self.fmt, &mut slot, &mut state);
+                 value.fmt(&mut writer)?;
+                 writer.write_str(",\n")
+             } else {
+                 let prefix = if self.fields == 0 { "(" } else { ", " };
+                 self.fmt.write_str(prefix)?;
+                 value.fmt(self.fmt)
+             }
+         });
+ 
+         self.fields += 1;
+         self
+     }
+ 
+     /// Finishes output and returns any error encountered.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32, String);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_tuple("Foo")
+     ///            .field(&self.0)
+     ///            .field(&self.1)
+     ///            .finish() // You need to call it to "finish" the
+     ///                      // tuple formatting.
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(10, "Hello World".to_string())),
+     ///     "Foo(10, \"Hello World\")",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn finish(&mut self) -> fmt::Result {
+         if self.fields > 0 {
+             self.result = self.result.and_then(|_| {
+                 if self.fields == 1 && self.empty_name && !self.is_pretty() {
+                     self.fmt.write_str(",")?;
+                 }
+                 self.fmt.write_str(")")
+             });
+         }
+         self.result
+     }
+ 
+     fn is_pretty(&self) -> bool {
+         self.fmt.alternate()
+     }
+ }
+ 
+ struct DebugInner<'a, 'b: 'a> {
+     fmt: &'a mut fmt::Formatter<'b>,
+     result: fmt::Result,
+     has_fields: bool,
+ }
+ 
+ impl<'a, 'b: 'a> DebugInner<'a, 'b> {
+     fn entry(&mut self, entry: &dyn fmt::Debug) {
+         self.result = self.result.and_then(|_| {
+             if self.is_pretty() {
+                 if !self.has_fields {
+                     self.fmt.write_str("\n")?;
+                 }
+                 let mut slot = None;
+                 let mut state = Default::default();
+                 let mut writer = PadAdapter::wrap(&mut self.fmt, &mut slot, &mut state);
+                 entry.fmt(&mut writer)?;
+                 writer.write_str(",\n")
+             } else {
+                 if self.has_fields {
+                     self.fmt.write_str(", ")?
+                 }
+                 entry.fmt(self.fmt)
+             }
+         });
+ 
+         self.has_fields = true;
+     }
+ 
+     fn is_pretty(&self) -> bool {
+         self.fmt.alternate()
+     }
+ }
+ 
+ /// A struct to help with [`fmt::Debug`](Debug) implementations.
+ ///
+ /// This is useful when you wish to output a formatted set of items as a part
+ /// of your [`Debug::fmt`] implementation.
+ ///
+ /// This can be constructed by the [`Formatter::debug_set`] method.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Foo(Vec<i32>);
+ ///
+ /// impl fmt::Debug for Foo {
+ ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+ ///         fmt.debug_set().entries(self.0.iter()).finish()
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(
+ ///     format!("{:?}", Foo(vec![10, 11])),
+ ///     "{10, 11}",
+ /// );
+ /// ```
+ #[must_use = "must eventually call `finish()` on Debug builders"]
+ #[allow(missing_debug_implementations)]
+ #[stable(feature = "debug_builders", since = "1.2.0")]
+ pub struct DebugSet<'a, 'b: 'a> {
+     inner: DebugInner<'a, 'b>,
+ }
+ 
+ pub(super) fn debug_set_new<'a, 'b>(fmt: &'a mut fmt::Formatter<'b>) -> DebugSet<'a, 'b> {
+     let result = fmt.write_str("{");
+     DebugSet { inner: DebugInner { fmt, result, has_fields: false } }
+ }
+ 
+ impl<'a, 'b: 'a> DebugSet<'a, 'b> {
+     /// Adds a new entry to the set output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>, Vec<u32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_set()
+     ///            .entry(&self.0) // Adds the first "entry".
+     ///            .entry(&self.1) // Adds the second "entry".
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![10, 11], vec![12, 13])),
+     ///     "{[10, 11], [12, 13]}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn entry(&mut self, entry: &dyn fmt::Debug) -> &mut Self {
+         self.inner.entry(entry);
+         self
+     }
+ 
+     /// Adds the contents of an iterator of entries to the set output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>, Vec<u32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_set()
+     ///            .entries(self.0.iter()) // Adds the first "entry".
+     ///            .entries(self.1.iter()) // Adds the second "entry".
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![10, 11], vec![12, 13])),
+     ///     "{10, 11, 12, 13}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn entries<D, I>(&mut self, entries: I) -> &mut Self
+     where
+         D: fmt::Debug,
+         I: IntoIterator<Item = D>,
+     {
+         for entry in entries {
+             self.entry(&entry);
+         }
+         self
+     }
+ 
+     /// Finishes output and returns any error encountered.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_set()
+     ///            .entries(self.0.iter())
+     ///            .finish() // Ends the struct formatting.
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![10, 11])),
+     ///     "{10, 11}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn finish(&mut self) -> fmt::Result {
+         self.inner.result.and_then(|_| self.inner.fmt.write_str("}"))
+     }
+ }
+ 
+ /// A struct to help with [`fmt::Debug`](Debug) implementations.
+ ///
+ /// This is useful when you wish to output a formatted list of items as a part
+ /// of your [`Debug::fmt`] implementation.
+ ///
+ /// This can be constructed by the [`Formatter::debug_list`] method.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Foo(Vec<i32>);
+ ///
+ /// impl fmt::Debug for Foo {
+ ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+ ///         fmt.debug_list().entries(self.0.iter()).finish()
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(
+ ///     format!("{:?}", Foo(vec![10, 11])),
+ ///     "[10, 11]",
+ /// );
+ /// ```
+ #[must_use = "must eventually call `finish()` on Debug builders"]
+ #[allow(missing_debug_implementations)]
+ #[stable(feature = "debug_builders", since = "1.2.0")]
+ pub struct DebugList<'a, 'b: 'a> {
+     inner: DebugInner<'a, 'b>,
+ }
+ 
+ pub(super) fn debug_list_new<'a, 'b>(fmt: &'a mut fmt::Formatter<'b>) -> DebugList<'a, 'b> {
+     let result = fmt.write_str("[");
+     DebugList { inner: DebugInner { fmt, result, has_fields: false } }
+ }
+ 
+ impl<'a, 'b: 'a> DebugList<'a, 'b> {
+     /// Adds a new entry to the list output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>, Vec<u32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_list()
+     ///            .entry(&self.0) // We add the first "entry".
+     ///            .entry(&self.1) // We add the second "entry".
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![10, 11], vec![12, 13])),
+     ///     "[[10, 11], [12, 13]]",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn entry(&mut self, entry: &dyn fmt::Debug) -> &mut Self {
+         self.inner.entry(entry);
+         self
+     }
+ 
+     /// Adds the contents of an iterator of entries to the list output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>, Vec<u32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_list()
+     ///            .entries(self.0.iter())
+     ///            .entries(self.1.iter())
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![10, 11], vec![12, 13])),
+     ///     "[10, 11, 12, 13]",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn entries<D, I>(&mut self, entries: I) -> &mut Self
+     where
+         D: fmt::Debug,
+         I: IntoIterator<Item = D>,
+     {
+         for entry in entries {
+             self.entry(&entry);
+         }
+         self
+     }
+ 
+     /// Finishes output and returns any error encountered.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_list()
+     ///            .entries(self.0.iter())
+     ///            .finish() // Ends the struct formatting.
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![10, 11])),
+     ///     "[10, 11]",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn finish(&mut self) -> fmt::Result {
+         self.inner.result.and_then(|_| self.inner.fmt.write_str("]"))
+     }
+ }
+ 
+ /// A struct to help with [`fmt::Debug`](Debug) implementations.
+ ///
+ /// This is useful when you wish to output a formatted map as a part of your
+ /// [`Debug::fmt`] implementation.
+ ///
+ /// This can be constructed by the [`Formatter::debug_map`] method.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Foo(Vec<(String, i32)>);
+ ///
+ /// impl fmt::Debug for Foo {
+ ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+ ///         fmt.debug_map().entries(self.0.iter().map(|&(ref k, ref v)| (k, v))).finish()
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(
+ ///     format!("{:?}", Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+ ///     "{\"A\": 10, \"B\": 11}",
+ /// );
+ /// ```
+ #[must_use = "must eventually call `finish()` on Debug builders"]
+ #[allow(missing_debug_implementations)]
+ #[stable(feature = "debug_builders", since = "1.2.0")]
+ pub struct DebugMap<'a, 'b: 'a> {
+     fmt: &'a mut fmt::Formatter<'b>,
+     result: fmt::Result,
+     has_fields: bool,
+     has_key: bool,
+     // The state of newlines is tracked between keys and values
+     state: PadAdapterState,
+ }
+ 
+ pub(super) fn debug_map_new<'a, 'b>(fmt: &'a mut fmt::Formatter<'b>) -> DebugMap<'a, 'b> {
+     let result = fmt.write_str("{");
+     DebugMap { fmt, result, has_fields: false, has_key: false, state: Default::default() }
+ }
+ 
+ impl<'a, 'b: 'a> DebugMap<'a, 'b> {
+     /// Adds a new entry to the map output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<(String, i32)>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_map()
+     ///            .entry(&"whole", &self.0) // We add the "whole" entry.
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+     ///     "{\"whole\": [(\"A\", 10), (\"B\", 11)]}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn entry(&mut self, key: &dyn fmt::Debug, value: &dyn fmt::Debug) -> &mut Self {
+         self.key(key).value(value)
+     }
+ 
+     /// Adds the key part of a new entry to the map output.
+     ///
+     /// This method, together with `value`, is an alternative to `entry` that
+     /// can be used when the complete entry isn't known upfront. Prefer the `entry`
+     /// method when it's possible to use.
+     ///
+     /// # Panics
+     ///
+     /// `key` must be called before `value` and each call to `key` must be followed
+     /// by a corresponding call to `value`. Otherwise this method will panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<(String, i32)>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_map()
+     ///            .key(&"whole").value(&self.0) // We add the "whole" entry.
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+     ///     "{\"whole\": [(\"A\", 10), (\"B\", 11)]}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_map_key_value", since = "1.42.0")]
+     pub fn key(&mut self, key: &dyn fmt::Debug) -> &mut Self {
+         self.result = self.result.and_then(|_| {
+             assert!(
+                 !self.has_key,
+                 "attempted to begin a new map entry \
+                                     without completing the previous one"
+             );
+ 
+             if self.is_pretty() {
+                 if !self.has_fields {
+                     self.fmt.write_str("\n")?;
+                 }
+                 let mut slot = None;
+                 self.state = Default::default();
+                 let mut writer = PadAdapter::wrap(&mut self.fmt, &mut slot, &mut self.state);
+                 key.fmt(&mut writer)?;
+                 writer.write_str(": ")?;
+             } else {
+                 if self.has_fields {
+                     self.fmt.write_str(", ")?
+                 }
+                 key.fmt(self.fmt)?;
+                 self.fmt.write_str(": ")?;
+             }
+ 
+             self.has_key = true;
+             Ok(())
+         });
+ 
+         self
+     }
+ 
+     /// Adds the value part of a new entry to the map output.
+     ///
+     /// This method, together with `key`, is an alternative to `entry` that
+     /// can be used when the complete entry isn't known upfront. Prefer the `entry`
+     /// method when it's possible to use.
+     ///
+     /// # Panics
+     ///
+     /// `key` must be called before `value` and each call to `key` must be followed
+     /// by a corresponding call to `value`. Otherwise this method will panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<(String, i32)>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_map()
+     ///            .key(&"whole").value(&self.0) // We add the "whole" entry.
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+     ///     "{\"whole\": [(\"A\", 10), (\"B\", 11)]}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_map_key_value", since = "1.42.0")]
+     pub fn value(&mut self, value: &dyn fmt::Debug) -> &mut Self {
+         self.result = self.result.and_then(|_| {
+             assert!(self.has_key, "attempted to format a map value before its key");
+ 
+             if self.is_pretty() {
+                 let mut slot = None;
+                 let mut writer = PadAdapter::wrap(&mut self.fmt, &mut slot, &mut self.state);
+                 value.fmt(&mut writer)?;
+                 writer.write_str(",\n")?;
+             } else {
+                 value.fmt(self.fmt)?;
+             }
+ 
+             self.has_key = false;
+             Ok(())
+         });
+ 
+         self.has_fields = true;
+         self
+     }
+ 
+     /// Adds the contents of an iterator of entries to the map output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<(String, i32)>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_map()
+     ///            // We map our vec so each entries' first field will become
+     ///            // the "key".
+     ///            .entries(self.0.iter().map(|&(ref k, ref v)| (k, v)))
+     ///            .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+     ///     "{\"A\": 10, \"B\": 11}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn entries<K, V, I>(&mut self, entries: I) -> &mut Self
+     where
+         K: fmt::Debug,
+         V: fmt::Debug,
+         I: IntoIterator<Item = (K, V)>,
+     {
+         for (k, v) in entries {
+             self.entry(&k, &v);
+         }
+         self
+     }
+ 
+     /// Finishes output and returns any error encountered.
+     ///
+     /// # Panics
+     ///
+     /// `key` must be called before `value` and each call to `key` must be followed
+     /// by a corresponding call to `value`. Otherwise this method will panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<(String, i32)>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         fmt.debug_map()
+     ///            .entries(self.0.iter().map(|&(ref k, ref v)| (k, v)))
+     ///            .finish() // Ends the struct formatting.
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}", Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+     ///     "{\"A\": 10, \"B\": 11}",
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn finish(&mut self) -> fmt::Result {
+         self.result.and_then(|_| {
+             assert!(!self.has_key, "attempted to finish a map with a partial entry");
+ 
+             self.fmt.write_str("}")
+         })
+     }
+ 
+     fn is_pretty(&self) -> bool {
+         self.fmt.alternate()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/float.rs gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/float.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/float.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/float.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,187 ----
+ use crate::fmt::{Debug, Display, Formatter, LowerExp, Result, UpperExp};
+ use crate::mem::MaybeUninit;
+ use crate::num::flt2dec;
+ 
+ // Don't inline this so callers don't use the stack space this function
+ // requires unless they have to.
+ #[inline(never)]
+ fn float_to_decimal_common_exact<T>(
+     fmt: &mut Formatter<'_>,
+     num: &T,
+     sign: flt2dec::Sign,
+     precision: usize,
+ ) -> Result
+ where
+     T: flt2dec::DecodableFloat,
+ {
+     let mut buf: [MaybeUninit<u8>; 1024] = MaybeUninit::uninit_array(); // enough for f32 and f64
+     let mut parts: [MaybeUninit<flt2dec::Part<'_>>; 4] = MaybeUninit::uninit_array();
+     let formatted = flt2dec::to_exact_fixed_str(
+         flt2dec::strategy::grisu::format_exact,
+         *num,
+         sign,
+         precision,
+         &mut buf,
+         &mut parts,
+     );
+     fmt.pad_formatted_parts(&formatted)
+ }
+ 
+ // Don't inline this so callers that call both this and the above won't wind
+ // up using the combined stack space of both functions in some cases.
+ #[inline(never)]
+ fn float_to_decimal_common_shortest<T>(
+     fmt: &mut Formatter<'_>,
+     num: &T,
+     sign: flt2dec::Sign,
+     precision: usize,
+ ) -> Result
+ where
+     T: flt2dec::DecodableFloat,
+ {
+     // enough for f32 and f64
+     let mut buf: [MaybeUninit<u8>; flt2dec::MAX_SIG_DIGITS] = MaybeUninit::uninit_array();
+     let mut parts: [MaybeUninit<flt2dec::Part<'_>>; 4] = MaybeUninit::uninit_array();
+     let formatted = flt2dec::to_shortest_str(
+         flt2dec::strategy::grisu::format_shortest,
+         *num,
+         sign,
+         precision,
+         &mut buf,
+         &mut parts,
+     );
+     fmt.pad_formatted_parts(&formatted)
+ }
+ 
+ // Common code of floating point Debug and Display.
+ fn float_to_decimal_common<T>(
+     fmt: &mut Formatter<'_>,
+     num: &T,
+     negative_zero: bool,
+     min_precision: usize,
+ ) -> Result
+ where
+     T: flt2dec::DecodableFloat,
+ {
+     let force_sign = fmt.sign_plus();
+     let sign = match (force_sign, negative_zero) {
+         (false, false) => flt2dec::Sign::Minus,
+         (false, true) => flt2dec::Sign::MinusRaw,
+         (true, false) => flt2dec::Sign::MinusPlus,
+         (true, true) => flt2dec::Sign::MinusPlusRaw,
+     };
+ 
+     if let Some(precision) = fmt.precision {
+         float_to_decimal_common_exact(fmt, num, sign, precision)
+     } else {
+         float_to_decimal_common_shortest(fmt, num, sign, min_precision)
+     }
+ }
+ 
+ // Don't inline this so callers don't use the stack space this function
+ // requires unless they have to.
+ #[inline(never)]
+ fn float_to_exponential_common_exact<T>(
+     fmt: &mut Formatter<'_>,
+     num: &T,
+     sign: flt2dec::Sign,
+     precision: usize,
+     upper: bool,
+ ) -> Result
+ where
+     T: flt2dec::DecodableFloat,
+ {
+     let mut buf: [MaybeUninit<u8>; 1024] = MaybeUninit::uninit_array(); // enough for f32 and f64
+     let mut parts: [MaybeUninit<flt2dec::Part<'_>>; 6] = MaybeUninit::uninit_array();
+     let formatted = flt2dec::to_exact_exp_str(
+         flt2dec::strategy::grisu::format_exact,
+         *num,
+         sign,
+         precision,
+         upper,
+         &mut buf,
+         &mut parts,
+     );
+     fmt.pad_formatted_parts(&formatted)
+ }
+ 
+ // Don't inline this so callers that call both this and the above won't wind
+ // up using the combined stack space of both functions in some cases.
+ #[inline(never)]
+ fn float_to_exponential_common_shortest<T>(
+     fmt: &mut Formatter<'_>,
+     num: &T,
+     sign: flt2dec::Sign,
+     upper: bool,
+ ) -> Result
+ where
+     T: flt2dec::DecodableFloat,
+ {
+     // enough for f32 and f64
+     let mut buf: [MaybeUninit<u8>; flt2dec::MAX_SIG_DIGITS] = MaybeUninit::uninit_array();
+     let mut parts: [MaybeUninit<flt2dec::Part<'_>>; 6] = MaybeUninit::uninit_array();
+     let formatted = flt2dec::to_shortest_exp_str(
+         flt2dec::strategy::grisu::format_shortest,
+         *num,
+         sign,
+         (0, 0),
+         upper,
+         &mut buf,
+         &mut parts,
+     );
+     fmt.pad_formatted_parts(&formatted)
+ }
+ 
+ // Common code of floating point LowerExp and UpperExp.
+ fn float_to_exponential_common<T>(fmt: &mut Formatter<'_>, num: &T, upper: bool) -> Result
+ where
+     T: flt2dec::DecodableFloat,
+ {
+     let force_sign = fmt.sign_plus();
+     let sign = match force_sign {
+         false => flt2dec::Sign::Minus,
+         true => flt2dec::Sign::MinusPlus,
+     };
+ 
+     if let Some(precision) = fmt.precision {
+         // 1 integral digit + `precision` fractional digits = `precision + 1` total digits
+         float_to_exponential_common_exact(fmt, num, sign, precision + 1, upper)
+     } else {
+         float_to_exponential_common_shortest(fmt, num, sign, upper)
+     }
+ }
+ 
+ macro_rules! floating {
+     ($ty:ident) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Debug for $ty {
+             fn fmt(&self, fmt: &mut Formatter<'_>) -> Result {
+                 float_to_decimal_common(fmt, self, true, 1)
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Display for $ty {
+             fn fmt(&self, fmt: &mut Formatter<'_>) -> Result {
+                 float_to_decimal_common(fmt, self, false, 0)
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl LowerExp for $ty {
+             fn fmt(&self, fmt: &mut Formatter<'_>) -> Result {
+                 float_to_exponential_common(fmt, self, false)
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl UpperExp for $ty {
+             fn fmt(&self, fmt: &mut Formatter<'_>) -> Result {
+                 float_to_exponential_common(fmt, self, true)
+             }
+         }
+     };
+ }
+ 
+ floating! { f32 }
+ floating! { f64 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2241 ----
+ //! Utilities for formatting and printing strings.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::cell::{Cell, Ref, RefCell, RefMut, UnsafeCell};
+ use crate::marker::PhantomData;
+ use crate::mem;
+ use crate::num::flt2dec;
+ use crate::ops::Deref;
+ use crate::result;
+ use crate::str;
+ 
+ mod builders;
+ mod float;
+ mod num;
+ 
+ #[stable(feature = "fmt_flags_align", since = "1.28.0")]
+ /// Possible alignments returned by `Formatter::align`
+ #[derive(Debug)]
+ pub enum Alignment {
+     #[stable(feature = "fmt_flags_align", since = "1.28.0")]
+     /// Indication that contents should be left-aligned.
+     Left,
+     #[stable(feature = "fmt_flags_align", since = "1.28.0")]
+     /// Indication that contents should be right-aligned.
+     Right,
+     #[stable(feature = "fmt_flags_align", since = "1.28.0")]
+     /// Indication that contents should be center-aligned.
+     Center,
+ }
+ 
+ #[stable(feature = "debug_builders", since = "1.2.0")]
+ pub use self::builders::{DebugList, DebugMap, DebugSet, DebugStruct, DebugTuple};
+ 
+ #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+ #[doc(hidden)]
+ pub mod rt {
+     pub mod v1;
+ }
+ 
+ /// The type returned by formatter methods.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// #[derive(Debug)]
+ /// struct Triangle {
+ ///     a: f32,
+ ///     b: f32,
+ ///     c: f32
+ /// }
+ ///
+ /// impl fmt::Display for Triangle {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         write!(f, "({}, {}, {})", self.a, self.b, self.c)
+ ///     }
+ /// }
+ ///
+ /// let pythagorean_triple = Triangle { a: 3.0, b: 4.0, c: 5.0 };
+ ///
+ /// assert_eq!(format!("{}", pythagorean_triple), "(3, 4, 5)");
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub type Result = result::Result<(), Error>;
+ 
+ /// The error type which is returned from formatting a message into a stream.
+ ///
+ /// This type does not support transmission of an error other than that an error
+ /// occurred. Any extra information must be arranged to be transmitted through
+ /// some other means.
+ ///
+ /// An important thing to remember is that the type `fmt::Error` should not be
+ /// confused with [`std::io::Error`] or [`std::error::Error`], which you may also
+ /// have in scope.
+ ///
+ /// [`std::io::Error`]: ../../std/io/struct.Error.html
+ /// [`std::error::Error`]: ../../std/error/trait.Error.html
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// use std::fmt::{self, write};
+ ///
+ /// let mut output = String::new();
+ /// if let Err(fmt::Error) = write(&mut output, format_args!("Hello {}!", "world")) {
+ ///     panic!("An error occurred");
+ /// }
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
+ pub struct Error;
+ 
+ /// A trait for writing or formatting into Unicode-accepting buffers or streams.
+ ///
+ /// This trait only accepts UTF-8–encoded data and is not [flushable]. If you only
+ /// want to accept Unicode and you don't need flushing, you should implement this trait;
+ /// otherwise you should implement [`std::io::Write`].
+ ///
+ /// [`std::io::Write`]: ../../std/io/trait.Write.html
+ /// [flushable]: ../../std/io/trait.Write.html#tymethod.flush
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Write {
+     /// Writes a string slice into this writer, returning whether the write
+     /// succeeded.
+     ///
+     /// This method can only succeed if the entire string slice was successfully
+     /// written, and this method will not return until all data has been
+     /// written or an error occurs.
+     ///
+     /// # Errors
+     ///
+     /// This function will return an instance of [`Error`] on error.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt::{Error, Write};
+     ///
+     /// fn writer<W: Write>(f: &mut W, s: &str) -> Result<(), Error> {
+     ///     f.write_str(s)
+     /// }
+     ///
+     /// let mut buf = String::new();
+     /// writer(&mut buf, "hola").unwrap();
+     /// assert_eq!(&buf, "hola");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn write_str(&mut self, s: &str) -> Result;
+ 
+     /// Writes a [`char`] into this writer, returning whether the write succeeded.
+     ///
+     /// A single [`char`] may be encoded as more than one byte.
+     /// This method can only succeed if the entire byte sequence was successfully
+     /// written, and this method will not return until all data has been
+     /// written or an error occurs.
+     ///
+     /// # Errors
+     ///
+     /// This function will return an instance of [`Error`] on error.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt::{Error, Write};
+     ///
+     /// fn writer<W: Write>(f: &mut W, c: char) -> Result<(), Error> {
+     ///     f.write_char(c)
+     /// }
+     ///
+     /// let mut buf = String::new();
+     /// writer(&mut buf, 'a').unwrap();
+     /// writer(&mut buf, 'b').unwrap();
+     /// assert_eq!(&buf, "ab");
+     /// ```
+     #[stable(feature = "fmt_write_char", since = "1.1.0")]
+     fn write_char(&mut self, c: char) -> Result {
+         self.write_str(c.encode_utf8(&mut [0; 4]))
+     }
+ 
+     /// Glue for usage of the [`write!`] macro with implementors of this trait.
+     ///
+     /// This method should generally not be invoked manually, but rather through
+     /// the [`write!`] macro itself.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt::{Error, Write};
+     ///
+     /// fn writer<W: Write>(f: &mut W, s: &str) -> Result<(), Error> {
+     ///     f.write_fmt(format_args!("{}", s))
+     /// }
+     ///
+     /// let mut buf = String::new();
+     /// writer(&mut buf, "world").unwrap();
+     /// assert_eq!(&buf, "world");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn write_fmt(mut self: &mut Self, args: Arguments<'_>) -> Result {
+         write(&mut self, args)
+     }
+ }
+ 
+ #[stable(feature = "fmt_write_blanket_impl", since = "1.4.0")]
+ impl<W: Write + ?Sized> Write for &mut W {
+     fn write_str(&mut self, s: &str) -> Result {
+         (**self).write_str(s)
+     }
+ 
+     fn write_char(&mut self, c: char) -> Result {
+         (**self).write_char(c)
+     }
+ 
+     fn write_fmt(&mut self, args: Arguments<'_>) -> Result {
+         (**self).write_fmt(args)
+     }
+ }
+ 
+ /// Configuration for formatting.
+ ///
+ /// A `Formatter` represents various options related to formatting. Users do not
+ /// construct `Formatter`s directly; a mutable reference to one is passed to
+ /// the `fmt` method of all formatting traits, like [`Debug`] and [`Display`].
+ ///
+ /// To interact with a `Formatter`, you'll call various methods to change the
+ /// various options related to formatting. For examples, please see the
+ /// documentation of the methods defined on `Formatter` below.
+ #[allow(missing_debug_implementations)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Formatter<'a> {
+     flags: u32,
+     fill: char,
+     align: rt::v1::Alignment,
+     width: Option<usize>,
+     precision: Option<usize>,
+ 
+     buf: &'a mut (dyn Write + 'a),
+ }
+ 
+ // NB. Argument is essentially an optimized partially applied formatting function,
+ // equivalent to `exists T.(&T, fn(&T, &mut Formatter<'_>) -> Result`.
+ 
+ extern "C" {
+     type Opaque;
+ }
+ 
+ /// This struct represents the generic "argument" which is taken by the Xprintf
+ /// family of functions. It contains a function to format the given value. At
+ /// compile time it is ensured that the function and the value have the correct
+ /// types, and then this struct is used to canonicalize arguments to one type.
+ #[derive(Copy, Clone)]
+ #[allow(missing_debug_implementations)]
+ #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+ #[doc(hidden)]
+ pub struct ArgumentV1<'a> {
+     value: &'a Opaque,
+     formatter: fn(&Opaque, &mut Formatter<'_>) -> Result,
+ }
+ 
+ // This guarantees a single stable value for the function pointer associated with
+ // indices/counts in the formatting infrastructure.
+ //
+ // Note that a function defined as such would not be correct as functions are
+ // always tagged unnamed_addr with the current lowering to LLVM IR, so their
+ // address is not considered important to LLVM and as such the as_usize cast
+ // could have been miscompiled. In practice, we never call as_usize on non-usize
+ // containing data (as a matter of static generation of the formatting
+ // arguments), so this is merely an additional check.
+ //
+ // We primarily want to ensure that the function pointer at `USIZE_MARKER` has
+ // an address corresponding *only* to functions that also take `&usize` as their
+ // first argument. The read_volatile here ensures that we can safely ready out a
+ // usize from the passed reference and that this address does not point at a
+ // non-usize taking function.
+ #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+ static USIZE_MARKER: fn(&usize, &mut Formatter<'_>) -> Result = |ptr, _| {
+     // SAFETY: ptr is a reference
+     let _v: usize = unsafe { crate::ptr::read_volatile(ptr) };
+     loop {}
+ };
+ 
+ impl<'a> ArgumentV1<'a> {
+     #[doc(hidden)]
+     #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+     pub fn new<'b, T>(x: &'b T, f: fn(&T, &mut Formatter<'_>) -> Result) -> ArgumentV1<'b> {
+         // SAFETY: `mem::transmute(x)` is safe because
+         //     1. `&'b T` keeps the lifetime it originated with `'b`
+         //              (so as to not have an unbounded lifetime)
+         //     2. `&'b T` and `&'b Opaque` have the same memory layout
+         //              (when `T` is `Sized`, as it is here)
+         // `mem::transmute(f)` is safe since `fn(&T, &mut Formatter<'_>) -> Result`
+         // and `fn(&Opaque, &mut Formatter<'_>) -> Result` have the same ABI
+         // (as long as `T` is `Sized`)
+         unsafe { ArgumentV1 { formatter: mem::transmute(f), value: mem::transmute(x) } }
+     }
+ 
+     #[doc(hidden)]
+     #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+     pub fn from_usize(x: &usize) -> ArgumentV1<'_> {
+         ArgumentV1::new(x, USIZE_MARKER)
+     }
+ 
+     fn as_usize(&self) -> Option<usize> {
+         if self.formatter as usize == USIZE_MARKER as usize {
+             // SAFETY: The `formatter` field is only set to USIZE_MARKER if
+             // the value is a usize, so this is safe
+             Some(unsafe { *(self.value as *const _ as *const usize) })
+         } else {
+             None
+         }
+     }
+ }
+ 
+ // flags available in the v1 format of format_args
+ #[derive(Copy, Clone)]
+ enum FlagV1 {
+     SignPlus,
+     SignMinus,
+     Alternate,
+     SignAwareZeroPad,
+     DebugLowerHex,
+     DebugUpperHex,
+ }
+ 
+ impl<'a> Arguments<'a> {
+     /// When using the format_args!() macro, this function is used to generate the
+     /// Arguments structure.
+     #[doc(hidden)]
+     #[inline]
+     #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+     pub fn new_v1(pieces: &'a [&'static str], args: &'a [ArgumentV1<'a>]) -> Arguments<'a> {
+         Arguments { pieces, fmt: None, args }
+     }
+ 
+     /// This function is used to specify nonstandard formatting parameters.
+     /// The `pieces` array must be at least as long as `fmt` to construct
+     /// a valid Arguments structure. Also, any `Count` within `fmt` that is
+     /// `CountIsParam` or `CountIsNextParam` has to point to an argument
+     /// created with `argumentusize`. However, failing to do so doesn't cause
+     /// unsafety, but will ignore invalid .
+     #[doc(hidden)]
+     #[inline]
+     #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+     pub fn new_v1_formatted(
+         pieces: &'a [&'static str],
+         args: &'a [ArgumentV1<'a>],
+         fmt: &'a [rt::v1::Argument],
+     ) -> Arguments<'a> {
+         Arguments { pieces, fmt: Some(fmt), args }
+     }
+ 
+     /// Estimates the length of the formatted text.
+     ///
+     /// This is intended to be used for setting initial `String` capacity
+     /// when using `format!`. Note: this is neither the lower nor upper bound.
+     #[doc(hidden)]
+     #[inline]
+     #[unstable(feature = "fmt_internals", reason = "internal to format_args!", issue = "none")]
+     pub fn estimated_capacity(&self) -> usize {
+         let pieces_length: usize = self.pieces.iter().map(|x| x.len()).sum();
+ 
+         if self.args.is_empty() {
+             pieces_length
+         } else if self.pieces[0] == "" && pieces_length < 16 {
+             // If the format string starts with an argument,
+             // don't preallocate anything, unless length
+             // of pieces is significant.
+             0
+         } else {
+             // There are some arguments, so any additional push
+             // will reallocate the string. To avoid that,
+             // we're "pre-doubling" the capacity here.
+             pieces_length.checked_mul(2).unwrap_or(0)
+         }
+     }
+ }
+ 
+ /// This structure represents a safely precompiled version of a format string
+ /// and its arguments. This cannot be generated at runtime because it cannot
+ /// safely be done, so no constructors are given and the fields are private
+ /// to prevent modification.
+ ///
+ /// The [`format_args!`] macro will safely create an instance of this structure.
+ /// The macro validates the format string at compile-time so usage of the
+ /// [`write()`] and [`format()`] functions can be safely performed.
+ ///
+ /// You can use the `Arguments<'a>` that [`format_args!`] returns in `Debug`
+ /// and `Display` contexts as seen below. The example also shows that `Debug`
+ /// and `Display` format to the same thing: the interpolated format string
+ /// in `format_args!`.
+ ///
+ /// ```rust
+ /// let debug = format!("{:?}", format_args!("{} foo {:?}", 1, 2));
+ /// let display = format!("{}", format_args!("{} foo {:?}", 1, 2));
+ /// assert_eq!("1 foo 2", display);
+ /// assert_eq!(display, debug);
+ /// ```
+ ///
+ /// [`format()`]: ../../std/fmt/fn.format.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Copy, Clone)]
+ pub struct Arguments<'a> {
+     // Format string pieces to print.
+     pieces: &'a [&'static str],
+ 
+     // Placeholder specs, or `None` if all specs are default (as in "{}{}").
+     fmt: Option<&'a [rt::v1::Argument]>,
+ 
+     // Dynamic arguments for interpolation, to be interleaved with string
+     // pieces. (Every argument is preceded by a string piece.)
+     args: &'a [ArgumentV1<'a>],
+ }
+ 
+ impl<'a> Arguments<'a> {
+     /// Get the formatted string, if it has no arguments to be formatted.
+     ///
+     /// This can be used to avoid allocations in the most trivial case.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(fmt_as_str)]
+     ///
+     /// use core::fmt::Arguments;
+     ///
+     /// fn write_str(_: &str) { /* ... */ }
+     ///
+     /// fn write_fmt(args: &Arguments) {
+     ///     if let Some(s) = args.as_str() {
+     ///         write_str(s)
+     ///     } else {
+     ///         write_str(&args.to_string());
+     ///     }
+     /// }
+     /// ```
+     ///
+     /// ```rust
+     /// #![feature(fmt_as_str)]
+     ///
+     /// assert_eq!(format_args!("hello").as_str(), Some("hello"));
+     /// assert_eq!(format_args!("").as_str(), Some(""));
+     /// assert_eq!(format_args!("{}", 1).as_str(), None);
+     /// ```
+     #[unstable(feature = "fmt_as_str", issue = "74442")]
+     #[inline]
+     pub fn as_str(&self) -> Option<&'static str> {
+         match (self.pieces, self.args) {
+             ([], []) => Some(""),
+             ([s], []) => Some(s),
+             _ => None,
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Debug for Arguments<'_> {
+     fn fmt(&self, fmt: &mut Formatter<'_>) -> Result {
+         Display::fmt(self, fmt)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Display for Arguments<'_> {
+     fn fmt(&self, fmt: &mut Formatter<'_>) -> Result {
+         write(fmt.buf, *self)
+     }
+ }
+ 
+ /// `?` formatting.
+ ///
+ /// `Debug` should format the output in a programmer-facing, debugging context.
+ ///
+ /// Generally speaking, you should just `derive` a `Debug` implementation.
+ ///
+ /// When used with the alternate format specifier `#?`, the output is pretty-printed.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// This trait can be used with `#[derive]` if all fields implement `Debug`. When
+ /// `derive`d for structs, it will use the name of the `struct`, then `{`, then a
+ /// comma-separated list of each field's name and `Debug` value, then `}`. For
+ /// `enum`s, it will use the name of the variant and, if applicable, `(`, then the
+ /// `Debug` values of the fields, then `)`.
+ ///
+ /// # Stability
+ ///
+ /// Derived `Debug` formats are not stable, and so may change with future Rust
+ /// versions. Additionally, `Debug` implementations of types provided by the
+ /// standard library (`libstd`, `libcore`, `liballoc`, etc.) are not stable, and
+ /// may also change with future Rust versions.
+ ///
+ /// # Examples
+ ///
+ /// Deriving an implementation:
+ ///
+ /// ```
+ /// #[derive(Debug)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// let origin = Point { x: 0, y: 0 };
+ ///
+ /// assert_eq!(format!("The origin is: {:?}", origin), "The origin is: Point { x: 0, y: 0 }");
+ /// ```
+ ///
+ /// Manually implementing:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// impl fmt::Debug for Point {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         f.debug_struct("Point")
+ ///          .field("x", &self.x)
+ ///          .field("y", &self.y)
+ ///          .finish()
+ ///     }
+ /// }
+ ///
+ /// let origin = Point { x: 0, y: 0 };
+ ///
+ /// assert_eq!(format!("The origin is: {:?}", origin), "The origin is: Point { x: 0, y: 0 }");
+ /// ```
+ ///
+ /// There are a number of helper methods on the [`Formatter`] struct to help you with manual
+ /// implementations, such as [`debug_struct`].
+ ///
+ /// `Debug` implementations using either `derive` or the debug builder API
+ /// on [`Formatter`] support pretty-printing using the alternate flag: `{:#?}`.
+ ///
+ /// [`debug_struct`]: Formatter::debug_struct
+ ///
+ /// Pretty-printing with `#?`:
+ ///
+ /// ```
+ /// #[derive(Debug)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// let origin = Point { x: 0, y: 0 };
+ ///
+ /// assert_eq!(format!("The origin is: {:#?}", origin),
+ /// "The origin is: Point {
+ ///     x: 0,
+ ///     y: 0,
+ /// }");
+ /// ```
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     on(
+         crate_local,
+         label = "`{Self}` cannot be formatted using `{{:?}}`",
+         note = "add `#[derive(Debug)]` or manually implement `{Debug}`"
+     ),
+     message = "`{Self}` doesn't implement `{Debug}`",
+     label = "`{Self}` cannot be formatted using `{{:?}}` because it doesn't implement `{Debug}`"
+ )]
+ #[doc(alias = "{:?}")]
+ #[rustc_diagnostic_item = "debug_trait"]
+ pub trait Debug {
+     /// Formats the value using the given formatter.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Position {
+     ///     longitude: f32,
+     ///     latitude: f32,
+     /// }
+     ///
+     /// impl fmt::Debug for Position {
+     ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         f.debug_tuple("")
+     ///          .field(&self.longitude)
+     ///          .field(&self.latitude)
+     ///          .finish()
+     ///     }
+     /// }
+     ///
+     /// let position = Position { longitude: 1.987, latitude: 2.983 };
+     /// assert_eq!(format!("{:?}", position), "(1.987, 2.983)");
+     ///
+     /// assert_eq!(format!("{:#?}", position), "(
+     ///     1.987,
+     ///     2.983,
+     /// )");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ // Separate module to reexport the macro `Debug` from prelude without the trait `Debug`.
+ pub(crate) mod macros {
+     /// Derive macro generating an impl of the trait `Debug`.
+     #[rustc_builtin_macro]
+     #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+     #[allow_internal_unstable(core_intrinsics)]
+     pub macro Debug($item:item) {
+         /* compiler built-in */
+     }
+ }
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[doc(inline)]
+ pub use macros::Debug;
+ 
+ /// Format trait for an empty format, `{}`.
+ ///
+ /// `Display` is similar to [`Debug`], but `Display` is for user-facing
+ /// output, and so cannot be derived.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Implementing `Display` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// impl fmt::Display for Point {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         write!(f, "({}, {})", self.x, self.y)
+ ///     }
+ /// }
+ ///
+ /// let origin = Point { x: 0, y: 0 };
+ ///
+ /// assert_eq!(format!("The origin is: {}", origin), "The origin is: (0, 0)");
+ /// ```
+ #[rustc_on_unimplemented(
+     on(
+         _Self = "std::path::Path",
+         label = "`{Self}` cannot be formatted with the default formatter; call `.display()` on it",
+         note = "call `.display()` or `.to_string_lossy()` to safely print paths, \
+                 as they may contain non-Unicode data"
+     ),
+     message = "`{Self}` doesn't implement `{Display}`",
+     label = "`{Self}` cannot be formatted with the default formatter",
+     note = "in format strings you may be able to use `{{:?}}` (or {{:#?}} for pretty-print) instead"
+ )]
+ #[doc(alias = "{}")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Display {
+     /// Formats the value using the given formatter.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Position {
+     ///     longitude: f32,
+     ///     latitude: f32,
+     /// }
+     ///
+     /// impl fmt::Display for Position {
+     ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+     ///         write!(f, "({}, {})", self.longitude, self.latitude)
+     ///     }
+     /// }
+     ///
+     /// assert_eq!("(1.987, 2.983)",
+     ///            format!("{}", Position { longitude: 1.987, latitude: 2.983, }));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `o` formatting.
+ ///
+ /// The `Octal` trait should format its output as a number in base-8.
+ ///
+ /// For primitive signed integers (`i8` to `i128`, and `isize`),
+ /// negative values are formatted as the two’s complement representation.
+ ///
+ /// The alternate flag, `#`, adds a `0o` in front of the output.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with `i32`:
+ ///
+ /// ```
+ /// let x = 42; // 42 is '52' in octal
+ ///
+ /// assert_eq!(format!("{:o}", x), "52");
+ /// assert_eq!(format!("{:#o}", x), "0o52");
+ ///
+ /// assert_eq!(format!("{:o}", -16), "37777777760");
+ /// ```
+ ///
+ /// Implementing `Octal` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::Octal for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         let val = self.0;
+ ///
+ ///         fmt::Octal::fmt(&val, f) // delegate to i32's implementation
+ ///     }
+ /// }
+ ///
+ /// let l = Length(9);
+ ///
+ /// assert_eq!(format!("l as octal is: {:o}", l), "l as octal is: 11");
+ ///
+ /// assert_eq!(format!("l as octal is: {:#06o}", l), "l as octal is: 0o0011");
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Octal {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `b` formatting.
+ ///
+ /// The `Binary` trait should format its output as a number in binary.
+ ///
+ /// For primitive signed integers ([`i8`] to [`i128`], and [`isize`]),
+ /// negative values are formatted as the two’s complement representation.
+ ///
+ /// The alternate flag, `#`, adds a `0b` in front of the output.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with [`i32`]:
+ ///
+ /// ```
+ /// let x = 42; // 42 is '101010' in binary
+ ///
+ /// assert_eq!(format!("{:b}", x), "101010");
+ /// assert_eq!(format!("{:#b}", x), "0b101010");
+ ///
+ /// assert_eq!(format!("{:b}", -16), "11111111111111111111111111110000");
+ /// ```
+ ///
+ /// Implementing `Binary` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::Binary for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         let val = self.0;
+ ///
+ ///         fmt::Binary::fmt(&val, f) // delegate to i32's implementation
+ ///     }
+ /// }
+ ///
+ /// let l = Length(107);
+ ///
+ /// assert_eq!(format!("l as binary is: {:b}", l), "l as binary is: 1101011");
+ ///
+ /// assert_eq!(
+ ///     format!("l as binary is: {:#032b}", l),
+ ///     "l as binary is: 0b000000000000000000000001101011"
+ /// );
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Binary {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `x` formatting.
+ ///
+ /// The `LowerHex` trait should format its output as a number in hexadecimal, with `a` through `f`
+ /// in lower case.
+ ///
+ /// For primitive signed integers (`i8` to `i128`, and `isize`),
+ /// negative values are formatted as the two’s complement representation.
+ ///
+ /// The alternate flag, `#`, adds a `0x` in front of the output.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with `i32`:
+ ///
+ /// ```
+ /// let x = 42; // 42 is '2a' in hex
+ ///
+ /// assert_eq!(format!("{:x}", x), "2a");
+ /// assert_eq!(format!("{:#x}", x), "0x2a");
+ ///
+ /// assert_eq!(format!("{:x}", -16), "fffffff0");
+ /// ```
+ ///
+ /// Implementing `LowerHex` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::LowerHex for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         let val = self.0;
+ ///
+ ///         fmt::LowerHex::fmt(&val, f) // delegate to i32's implementation
+ ///     }
+ /// }
+ ///
+ /// let l = Length(9);
+ ///
+ /// assert_eq!(format!("l as hex is: {:x}", l), "l as hex is: 9");
+ ///
+ /// assert_eq!(format!("l as hex is: {:#010x}", l), "l as hex is: 0x00000009");
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait LowerHex {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `X` formatting.
+ ///
+ /// The `UpperHex` trait should format its output as a number in hexadecimal, with `A` through `F`
+ /// in upper case.
+ ///
+ /// For primitive signed integers (`i8` to `i128`, and `isize`),
+ /// negative values are formatted as the two’s complement representation.
+ ///
+ /// The alternate flag, `#`, adds a `0x` in front of the output.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with `i32`:
+ ///
+ /// ```
+ /// let x = 42; // 42 is '2A' in hex
+ ///
+ /// assert_eq!(format!("{:X}", x), "2A");
+ /// assert_eq!(format!("{:#X}", x), "0x2A");
+ ///
+ /// assert_eq!(format!("{:X}", -16), "FFFFFFF0");
+ /// ```
+ ///
+ /// Implementing `UpperHex` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::UpperHex for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         let val = self.0;
+ ///
+ ///         fmt::UpperHex::fmt(&val, f) // delegate to i32's implementation
+ ///     }
+ /// }
+ ///
+ /// let l = Length(i32::MAX);
+ ///
+ /// assert_eq!(format!("l as hex is: {:X}", l), "l as hex is: 7FFFFFFF");
+ ///
+ /// assert_eq!(format!("l as hex is: {:#010X}", l), "l as hex is: 0x7FFFFFFF");
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait UpperHex {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `p` formatting.
+ ///
+ /// The `Pointer` trait should format its output as a memory location. This is commonly presented
+ /// as hexadecimal.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with `&i32`:
+ ///
+ /// ```
+ /// let x = &42;
+ ///
+ /// let address = format!("{:p}", x); // this produces something like '0x7f06092ac6d0'
+ /// ```
+ ///
+ /// Implementing `Pointer` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::Pointer for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         // use `as` to convert to a `*const T`, which implements Pointer, which we can use
+ ///
+ ///         let ptr = self as *const Self;
+ ///         fmt::Pointer::fmt(&ptr, f)
+ ///     }
+ /// }
+ ///
+ /// let l = Length(42);
+ ///
+ /// println!("l is in memory here: {:p}", l);
+ ///
+ /// let l_ptr = format!("{:018p}", l);
+ /// assert_eq!(l_ptr.len(), 18);
+ /// assert_eq!(&l_ptr[..2], "0x");
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_diagnostic_item = "pointer_trait"]
+ pub trait Pointer {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_diagnostic_item = "pointer_trait_fmt"]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `e` formatting.
+ ///
+ /// The `LowerExp` trait should format its output in scientific notation with a lower-case `e`.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with `f64`:
+ ///
+ /// ```
+ /// let x = 42.0; // 42.0 is '4.2e1' in scientific notation
+ ///
+ /// assert_eq!(format!("{:e}", x), "4.2e1");
+ /// ```
+ ///
+ /// Implementing `LowerExp` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::LowerExp for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         let val = f64::from(self.0);
+ ///         fmt::LowerExp::fmt(&val, f) // delegate to f64's implementation
+ ///     }
+ /// }
+ ///
+ /// let l = Length(100);
+ ///
+ /// assert_eq!(
+ ///     format!("l in scientific notation is: {:e}", l),
+ ///     "l in scientific notation is: 1e2"
+ /// );
+ ///
+ /// assert_eq!(
+ ///     format!("l in scientific notation is: {:05e}", l),
+ ///     "l in scientific notation is: 001e2"
+ /// );
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait LowerExp {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// `E` formatting.
+ ///
+ /// The `UpperExp` trait should format its output in scientific notation with an upper-case `E`.
+ ///
+ /// For more information on formatters, see [the module-level documentation][self].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage with `f64`:
+ ///
+ /// ```
+ /// let x = 42.0; // 42.0 is '4.2E1' in scientific notation
+ ///
+ /// assert_eq!(format!("{:E}", x), "4.2E1");
+ /// ```
+ ///
+ /// Implementing `UpperExp` on a type:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// struct Length(i32);
+ ///
+ /// impl fmt::UpperExp for Length {
+ ///     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ ///         let val = f64::from(self.0);
+ ///         fmt::UpperExp::fmt(&val, f) // delegate to f64's implementation
+ ///     }
+ /// }
+ ///
+ /// let l = Length(100);
+ ///
+ /// assert_eq!(
+ ///     format!("l in scientific notation is: {:E}", l),
+ ///     "l in scientific notation is: 1E2"
+ /// );
+ ///
+ /// assert_eq!(
+ ///     format!("l in scientific notation is: {:05E}", l),
+ ///     "l in scientific notation is: 001E2"
+ /// );
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait UpperExp {
+     /// Formats the value using the given formatter.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result;
+ }
+ 
+ /// The `write` function takes an output stream, and an `Arguments` struct
+ /// that can be precompiled with the `format_args!` macro.
+ ///
+ /// The arguments will be formatted according to the specified format string
+ /// into the output stream provided.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::fmt;
+ ///
+ /// let mut output = String::new();
+ /// fmt::write(&mut output, format_args!("Hello {}!", "world"))
+ ///     .expect("Error occurred while trying to write in String");
+ /// assert_eq!(output, "Hello world!");
+ /// ```
+ ///
+ /// Please note that using [`write!`] might be preferable. Example:
+ ///
+ /// ```
+ /// use std::fmt::Write;
+ ///
+ /// let mut output = String::new();
+ /// write!(&mut output, "Hello {}!", "world")
+ ///     .expect("Error occurred while trying to write in String");
+ /// assert_eq!(output, "Hello world!");
+ /// ```
+ ///
+ /// [`write!`]: crate::write!
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn write(output: &mut dyn Write, args: Arguments<'_>) -> Result {
+     let mut formatter = Formatter {
+         flags: 0,
+         width: None,
+         precision: None,
+         buf: output,
+         align: rt::v1::Alignment::Unknown,
+         fill: ' ',
+     };
+ 
+     let mut idx = 0;
+ 
+     match args.fmt {
+         None => {
+             // We can use default formatting parameters for all arguments.
+             for (arg, piece) in args.args.iter().zip(args.pieces.iter()) {
+                 formatter.buf.write_str(*piece)?;
+                 (arg.formatter)(arg.value, &mut formatter)?;
+                 idx += 1;
+             }
+         }
+         Some(fmt) => {
+             // Every spec has a corresponding argument that is preceded by
+             // a string piece.
+             for (arg, piece) in fmt.iter().zip(args.pieces.iter()) {
+                 formatter.buf.write_str(*piece)?;
+                 run(&mut formatter, arg, &args.args)?;
+                 idx += 1;
+             }
+         }
+     }
+ 
+     // There can be only one trailing string piece left.
+     if let Some(piece) = args.pieces.get(idx) {
+         formatter.buf.write_str(*piece)?;
+     }
+ 
+     Ok(())
+ }
+ 
+ fn run(fmt: &mut Formatter<'_>, arg: &rt::v1::Argument, args: &[ArgumentV1<'_>]) -> Result {
+     fmt.fill = arg.format.fill;
+     fmt.align = arg.format.align;
+     fmt.flags = arg.format.flags;
+     fmt.width = getcount(args, &arg.format.width);
+     fmt.precision = getcount(args, &arg.format.precision);
+ 
+     // Extract the correct argument
+     let value = args[arg.position];
+ 
+     // Then actually do some printing
+     (value.formatter)(value.value, fmt)
+ }
+ 
+ fn getcount(args: &[ArgumentV1<'_>], cnt: &rt::v1::Count) -> Option<usize> {
+     match *cnt {
+         rt::v1::Count::Is(n) => Some(n),
+         rt::v1::Count::Implied => None,
+         rt::v1::Count::Param(i) => args[i].as_usize(),
+     }
+ }
+ 
+ /// Padding after the end of something. Returned by `Formatter::padding`.
+ #[must_use = "don't forget to write the post padding"]
+ struct PostPadding {
+     fill: char,
+     padding: usize,
+ }
+ 
+ impl PostPadding {
+     fn new(fill: char, padding: usize) -> PostPadding {
+         PostPadding { fill, padding }
+     }
+ 
+     /// Write this post padding.
+     fn write(self, buf: &mut dyn Write) -> Result {
+         for _ in 0..self.padding {
+             buf.write_char(self.fill)?;
+         }
+         Ok(())
+     }
+ }
+ 
+ impl<'a> Formatter<'a> {
+     fn wrap_buf<'b, 'c, F>(&'b mut self, wrap: F) -> Formatter<'c>
+     where
+         'b: 'c,
+         F: FnOnce(&'b mut (dyn Write + 'b)) -> &'c mut (dyn Write + 'c),
+     {
+         Formatter {
+             // We want to change this
+             buf: wrap(self.buf),
+ 
+             // And preserve these
+             flags: self.flags,
+             fill: self.fill,
+             align: self.align,
+             width: self.width,
+             precision: self.precision,
+         }
+     }
+ 
+     // Helper methods used for padding and processing formatting arguments that
+     // all formatting traits can use.
+ 
+     /// Performs the correct padding for an integer which has already been
+     /// emitted into a str. The str should *not* contain the sign for the
+     /// integer, that will be added by this method.
+     ///
+     /// # Arguments
+     ///
+     /// * is_nonnegative - whether the original integer was either positive or zero.
+     /// * prefix - if the '#' character (Alternate) is provided, this
+     ///   is the prefix to put in front of the number.
+     /// * buf - the byte array that the number has been formatted into
+     ///
+     /// This function will correctly account for the flags provided as well as
+     /// the minimum width. It will not take precision into account.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo { nb: i32 };
+     ///
+     /// impl Foo {
+     ///     fn new(nb: i32) -> Foo {
+     ///         Foo {
+     ///             nb,
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         // We need to remove "-" from the number output.
+     ///         let tmp = self.nb.abs().to_string();
+     ///
+     ///         formatter.pad_integral(self.nb > 0, "Foo ", &tmp)
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{}", Foo::new(2)), "2");
+     /// assert_eq!(&format!("{}", Foo::new(-1)), "-1");
+     /// assert_eq!(&format!("{:#}", Foo::new(-1)), "-Foo 1");
+     /// assert_eq!(&format!("{:0>#8}", Foo::new(-1)), "00-Foo 1");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn pad_integral(&mut self, is_nonnegative: bool, prefix: &str, buf: &str) -> Result {
+         let mut width = buf.len();
+ 
+         let mut sign = None;
+         if !is_nonnegative {
+             sign = Some('-');
+             width += 1;
+         } else if self.sign_plus() {
+             sign = Some('+');
+             width += 1;
+         }
+ 
+         let prefix = if self.alternate() {
+             width += prefix.chars().count();
+             Some(prefix)
+         } else {
+             None
+         };
+ 
+         // Writes the sign if it exists, and then the prefix if it was requested
+         #[inline(never)]
+         fn write_prefix(f: &mut Formatter<'_>, sign: Option<char>, prefix: Option<&str>) -> Result {
+             if let Some(c) = sign {
+                 f.buf.write_char(c)?;
+             }
+             if let Some(prefix) = prefix { f.buf.write_str(prefix) } else { Ok(()) }
+         }
+ 
+         // The `width` field is more of a `min-width` parameter at this point.
+         match self.width {
+             // If there's no minimum length requirements then we can just
+             // write the bytes.
+             None => {
+                 write_prefix(self, sign, prefix)?;
+                 self.buf.write_str(buf)
+             }
+             // Check if we're over the minimum width, if so then we can also
+             // just write the bytes.
+             Some(min) if width >= min => {
+                 write_prefix(self, sign, prefix)?;
+                 self.buf.write_str(buf)
+             }
+             // The sign and prefix goes before the padding if the fill character
+             // is zero
+             Some(min) if self.sign_aware_zero_pad() => {
+                 let old_fill = crate::mem::replace(&mut self.fill, '0');
+                 let old_align = crate::mem::replace(&mut self.align, rt::v1::Alignment::Right);
+                 write_prefix(self, sign, prefix)?;
+                 let post_padding = self.padding(min - width, rt::v1::Alignment::Right)?;
+                 self.buf.write_str(buf)?;
+                 post_padding.write(self.buf)?;
+                 self.fill = old_fill;
+                 self.align = old_align;
+                 Ok(())
+             }
+             // Otherwise, the sign and prefix goes after the padding
+             Some(min) => {
+                 let post_padding = self.padding(min - width, rt::v1::Alignment::Right)?;
+                 write_prefix(self, sign, prefix)?;
+                 self.buf.write_str(buf)?;
+                 post_padding.write(self.buf)
+             }
+         }
+     }
+ 
+     /// This function takes a string slice and emits it to the internal buffer
+     /// after applying the relevant formatting flags specified. The flags
+     /// recognized for generic strings are:
+     ///
+     /// * width - the minimum width of what to emit
+     /// * fill/align - what to emit and where to emit it if the string
+     ///                provided needs to be padded
+     /// * precision - the maximum length to emit, the string is truncated if it
+     ///               is longer than this length
+     ///
+     /// Notably this function ignores the `flag` parameters.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo;
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         formatter.pad("Foo")
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:<4}", Foo), "Foo ");
+     /// assert_eq!(&format!("{:0>4}", Foo), "0Foo");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn pad(&mut self, s: &str) -> Result {
+         // Make sure there's a fast path up front
+         if self.width.is_none() && self.precision.is_none() {
+             return self.buf.write_str(s);
+         }
+         // The `precision` field can be interpreted as a `max-width` for the
+         // string being formatted.
+         let s = if let Some(max) = self.precision {
+             // If our string is longer that the precision, then we must have
+             // truncation. However other flags like `fill`, `width` and `align`
+             // must act as always.
+             if let Some((i, _)) = s.char_indices().nth(max) {
+                 // LLVM here can't prove that `..i` won't panic `&s[..i]`, but
+                 // we know that it can't panic. Use `get` + `unwrap_or` to avoid
+                 // `unsafe` and otherwise don't emit any panic-related code
+                 // here.
+                 s.get(..i).unwrap_or(&s)
+             } else {
+                 &s
+             }
+         } else {
+             &s
+         };
+         // The `width` field is more of a `min-width` parameter at this point.
+         match self.width {
+             // If we're under the maximum length, and there's no minimum length
+             // requirements, then we can just emit the string
+             None => self.buf.write_str(s),
+             // If we're under the maximum width, check if we're over the minimum
+             // width, if so it's as easy as just emitting the string.
+             Some(width) if s.chars().count() >= width => self.buf.write_str(s),
+             // If we're under both the maximum and the minimum width, then fill
+             // up the minimum width with the specified string + some alignment.
+             Some(width) => {
+                 let align = rt::v1::Alignment::Left;
+                 let post_padding = self.padding(width - s.chars().count(), align)?;
+                 self.buf.write_str(s)?;
+                 post_padding.write(self.buf)
+             }
+         }
+     }
+ 
+     /// Write the pre-padding and return the unwritten post-padding. Callers are
+     /// responsible for ensuring post-padding is written after the thing that is
+     /// being padded.
+     fn padding(
+         &mut self,
+         padding: usize,
+         default: rt::v1::Alignment,
+     ) -> result::Result<PostPadding, Error> {
+         let align = match self.align {
+             rt::v1::Alignment::Unknown => default,
+             _ => self.align,
+         };
+ 
+         let (pre_pad, post_pad) = match align {
+             rt::v1::Alignment::Left => (0, padding),
+             rt::v1::Alignment::Right | rt::v1::Alignment::Unknown => (padding, 0),
+             rt::v1::Alignment::Center => (padding / 2, (padding + 1) / 2),
+         };
+ 
+         for _ in 0..pre_pad {
+             self.buf.write_char(self.fill)?;
+         }
+ 
+         Ok(PostPadding::new(self.fill, post_pad))
+     }
+ 
+     /// Takes the formatted parts and applies the padding.
+     /// Assumes that the caller already has rendered the parts with required precision,
+     /// so that `self.precision` can be ignored.
+     fn pad_formatted_parts(&mut self, formatted: &flt2dec::Formatted<'_>) -> Result {
+         if let Some(mut width) = self.width {
+             // for the sign-aware zero padding, we render the sign first and
+             // behave as if we had no sign from the beginning.
+             let mut formatted = formatted.clone();
+             let old_fill = self.fill;
+             let old_align = self.align;
+             let mut align = old_align;
+             if self.sign_aware_zero_pad() {
+                 // a sign always goes first
+                 let sign = formatted.sign;
+                 self.buf.write_str(sign)?;
+ 
+                 // remove the sign from the formatted parts
+                 formatted.sign = "";
+                 width = width.saturating_sub(sign.len());
+                 align = rt::v1::Alignment::Right;
+                 self.fill = '0';
+                 self.align = rt::v1::Alignment::Right;
+             }
+ 
+             // remaining parts go through the ordinary padding process.
+             let len = formatted.len();
+             let ret = if width <= len {
+                 // no padding
+                 self.write_formatted_parts(&formatted)
+             } else {
+                 let post_padding = self.padding(width - len, align)?;
+                 self.write_formatted_parts(&formatted)?;
+                 post_padding.write(self.buf)
+             };
+             self.fill = old_fill;
+             self.align = old_align;
+             ret
+         } else {
+             // this is the common case and we take a shortcut
+             self.write_formatted_parts(formatted)
+         }
+     }
+ 
+     fn write_formatted_parts(&mut self, formatted: &flt2dec::Formatted<'_>) -> Result {
+         fn write_bytes(buf: &mut dyn Write, s: &[u8]) -> Result {
+             // SAFETY: This is used for `flt2dec::Part::Num` and `flt2dec::Part::Copy`.
+             // It's safe to use for `flt2dec::Part::Num` since every char `c` is between
+             // `b'0'` and `b'9'`, which means `s` is valid UTF-8.
+             // It's also probably safe in practice to use for `flt2dec::Part::Copy(buf)`
+             // since `buf` should be plain ASCII, but it's possible for someone to pass
+             // in a bad value for `buf` into `flt2dec::to_shortest_str` since it is a
+             // public function.
+             // FIXME: Determine whether this could result in UB.
+             buf.write_str(unsafe { str::from_utf8_unchecked(s) })
+         }
+ 
+         if !formatted.sign.is_empty() {
+             self.buf.write_str(formatted.sign)?;
+         }
+         for part in formatted.parts {
+             match *part {
+                 flt2dec::Part::Zero(mut nzeroes) => {
+                     const ZEROES: &str = // 64 zeroes
+                         "0000000000000000000000000000000000000000000000000000000000000000";
+                     while nzeroes > ZEROES.len() {
+                         self.buf.write_str(ZEROES)?;
+                         nzeroes -= ZEROES.len();
+                     }
+                     if nzeroes > 0 {
+                         self.buf.write_str(&ZEROES[..nzeroes])?;
+                     }
+                 }
+                 flt2dec::Part::Num(mut v) => {
+                     let mut s = [0; 5];
+                     let len = part.len();
+                     for c in s[..len].iter_mut().rev() {
+                         *c = b'0' + (v % 10) as u8;
+                         v /= 10;
+                     }
+                     write_bytes(self.buf, &s[..len])?;
+                 }
+                 flt2dec::Part::Copy(buf) => {
+                     write_bytes(self.buf, buf)?;
+                 }
+             }
+         }
+         Ok(())
+     }
+ 
+     /// Writes some data to the underlying buffer contained within this
+     /// formatter.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo;
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         formatter.write_str("Foo")
+     ///         // This is equivalent to:
+     ///         // write!(formatter, "Foo")
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{}", Foo), "Foo");
+     /// assert_eq!(&format!("{:0>8}", Foo), "Foo");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn write_str(&mut self, data: &str) -> Result {
+         self.buf.write_str(data)
+     }
+ 
+     /// Writes some formatted information into this instance.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         formatter.write_fmt(format_args!("Foo {}", self.0))
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{}", Foo(-1)), "Foo -1");
+     /// assert_eq!(&format!("{:0>8}", Foo(2)), "Foo 2");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn write_fmt(&mut self, fmt: Arguments<'_>) -> Result {
+         write(self.buf, fmt)
+     }
+ 
+     /// Flags for formatting
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.24.0",
+         reason = "use the `sign_plus`, `sign_minus`, `alternate`, \
+                   or `sign_aware_zero_pad` methods instead"
+     )]
+     pub fn flags(&self) -> u32 {
+         self.flags
+     }
+ 
+     /// Character used as 'fill' whenever there is alignment.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo;
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         let c = formatter.fill();
+     ///         if let Some(width) = formatter.width() {
+     ///             for _ in 0..width {
+     ///                 write!(formatter, "{}", c)?;
+     ///             }
+     ///             Ok(())
+     ///         } else {
+     ///             write!(formatter, "{}", c)
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// // We set alignment to the left with ">".
+     /// assert_eq!(&format!("{:G>3}", Foo), "GGG");
+     /// assert_eq!(&format!("{:t>6}", Foo), "tttttt");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn fill(&self) -> char {
+         self.fill
+     }
+ 
+     /// Flag indicating what form of alignment was requested.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// extern crate core;
+     ///
+     /// use std::fmt::{self, Alignment};
+     ///
+     /// struct Foo;
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         let s = if let Some(s) = formatter.align() {
+     ///             match s {
+     ///                 Alignment::Left    => "left",
+     ///                 Alignment::Right   => "right",
+     ///                 Alignment::Center  => "center",
+     ///             }
+     ///         } else {
+     ///             "into the void"
+     ///         };
+     ///         write!(formatter, "{}", s)
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:<}", Foo), "left");
+     /// assert_eq!(&format!("{:>}", Foo), "right");
+     /// assert_eq!(&format!("{:^}", Foo), "center");
+     /// assert_eq!(&format!("{}", Foo), "into the void");
+     /// ```
+     #[stable(feature = "fmt_flags_align", since = "1.28.0")]
+     pub fn align(&self) -> Option<Alignment> {
+         match self.align {
+             rt::v1::Alignment::Left => Some(Alignment::Left),
+             rt::v1::Alignment::Right => Some(Alignment::Right),
+             rt::v1::Alignment::Center => Some(Alignment::Center),
+             rt::v1::Alignment::Unknown => None,
+         }
+     }
+ 
+     /// Optionally specified integer width that the output should be.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         if let Some(width) = formatter.width() {
+     ///             // If we received a width, we use it
+     ///             write!(formatter, "{:width$}", &format!("Foo({})", self.0), width = width)
+     ///         } else {
+     ///             // Otherwise we do nothing special
+     ///             write!(formatter, "Foo({})", self.0)
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:10}", Foo(23)), "Foo(23)   ");
+     /// assert_eq!(&format!("{}", Foo(23)), "Foo(23)");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn width(&self) -> Option<usize> {
+         self.width
+     }
+ 
+     /// Optionally specified precision for numeric types. Alternatively, the
+     /// maximum width for string types.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(f32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         if let Some(precision) = formatter.precision() {
+     ///             // If we received a precision, we use it.
+     ///             write!(formatter, "Foo({1:.*})", precision, self.0)
+     ///         } else {
+     ///             // Otherwise we default to 2.
+     ///             write!(formatter, "Foo({:.2})", self.0)
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:.4}", Foo(23.2)), "Foo(23.2000)");
+     /// assert_eq!(&format!("{}", Foo(23.2)), "Foo(23.20)");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn precision(&self) -> Option<usize> {
+         self.precision
+     }
+ 
+     /// Determines if the `+` flag was specified.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         if formatter.sign_plus() {
+     ///             write!(formatter,
+     ///                    "Foo({}{})",
+     ///                    if self.0 < 0 { '-' } else { '+' },
+     ///                    self.0)
+     ///         } else {
+     ///             write!(formatter, "Foo({})", self.0)
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:+}", Foo(23)), "Foo(+23)");
+     /// assert_eq!(&format!("{}", Foo(23)), "Foo(23)");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn sign_plus(&self) -> bool {
+         self.flags & (1 << FlagV1::SignPlus as u32) != 0
+     }
+ 
+     /// Determines if the `-` flag was specified.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         if formatter.sign_minus() {
+     ///             // You want a minus sign? Have one!
+     ///             write!(formatter, "-Foo({})", self.0)
+     ///         } else {
+     ///             write!(formatter, "Foo({})", self.0)
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:-}", Foo(23)), "-Foo(23)");
+     /// assert_eq!(&format!("{}", Foo(23)), "Foo(23)");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn sign_minus(&self) -> bool {
+         self.flags & (1 << FlagV1::SignMinus as u32) != 0
+     }
+ 
+     /// Determines if the `#` flag was specified.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         if formatter.alternate() {
+     ///             write!(formatter, "Foo({})", self.0)
+     ///         } else {
+     ///             write!(formatter, "{}", self.0)
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:#}", Foo(23)), "Foo(23)");
+     /// assert_eq!(&format!("{}", Foo(23)), "23");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn alternate(&self) -> bool {
+         self.flags & (1 << FlagV1::Alternate as u32) != 0
+     }
+ 
+     /// Determines if the `0` flag was specified.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// struct Foo(i32);
+     ///
+     /// impl fmt::Display for Foo {
+     ///     fn fmt(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
+     ///         assert!(formatter.sign_aware_zero_pad());
+     ///         assert_eq!(formatter.width(), Some(4));
+     ///         // We ignore the formatter's options.
+     ///         write!(formatter, "{}", self.0)
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(&format!("{:04}", Foo(23)), "23");
+     /// ```
+     #[stable(feature = "fmt_flags", since = "1.5.0")]
+     pub fn sign_aware_zero_pad(&self) -> bool {
+         self.flags & (1 << FlagV1::SignAwareZeroPad as u32) != 0
+     }
+ 
+     // FIXME: Decide what public API we want for these two flags.
+     // https://github.com/rust-lang/rust/issues/48584
+     fn debug_lower_hex(&self) -> bool {
+         self.flags & (1 << FlagV1::DebugLowerHex as u32) != 0
+     }
+ 
+     fn debug_upper_hex(&self) -> bool {
+         self.flags & (1 << FlagV1::DebugUpperHex as u32) != 0
+     }
+ 
+     /// Creates a [`DebugStruct`] builder designed to assist with creation of
+     /// [`fmt::Debug`] implementations for structs.
+     ///
+     /// [`fmt::Debug`]: self::Debug
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::fmt;
+     /// use std::net::Ipv4Addr;
+     ///
+     /// struct Foo {
+     ///     bar: i32,
+     ///     baz: String,
+     ///     addr: Ipv4Addr,
+     /// }
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         fmt.debug_struct("Foo")
+     ///             .field("bar", &self.bar)
+     ///             .field("baz", &self.baz)
+     ///             .field("addr", &format_args!("{}", self.addr))
+     ///             .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     "Foo { bar: 10, baz: \"Hello World\", addr: 127.0.0.1 }",
+     ///     format!("{:?}", Foo {
+     ///         bar: 10,
+     ///         baz: "Hello World".to_string(),
+     ///         addr: Ipv4Addr::new(127, 0, 0, 1),
+     ///     })
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn debug_struct<'b>(&'b mut self, name: &str) -> DebugStruct<'b, 'a> {
+         builders::debug_struct_new(self, name)
+     }
+ 
+     /// Creates a `DebugTuple` builder designed to assist with creation of
+     /// `fmt::Debug` implementations for tuple structs.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::fmt;
+     /// use std::marker::PhantomData;
+     ///
+     /// struct Foo<T>(i32, String, PhantomData<T>);
+     ///
+     /// impl<T> fmt::Debug for Foo<T> {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         fmt.debug_tuple("Foo")
+     ///             .field(&self.0)
+     ///             .field(&self.1)
+     ///             .field(&format_args!("_"))
+     ///             .finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     "Foo(10, \"Hello\", _)",
+     ///     format!("{:?}", Foo(10, "Hello".to_string(), PhantomData::<u8>))
+     /// );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn debug_tuple<'b>(&'b mut self, name: &str) -> DebugTuple<'b, 'a> {
+         builders::debug_tuple_new(self, name)
+     }
+ 
+     /// Creates a `DebugList` builder designed to assist with creation of
+     /// `fmt::Debug` implementations for list-like structures.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         fmt.debug_list().entries(self.0.iter()).finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(format!("{:?}", Foo(vec![10, 11])), "[10, 11]");
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn debug_list<'b>(&'b mut self) -> DebugList<'b, 'a> {
+         builders::debug_list_new(self)
+     }
+ 
+     /// Creates a `DebugSet` builder designed to assist with creation of
+     /// `fmt::Debug` implementations for set-like structures.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<i32>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         fmt.debug_set().entries(self.0.iter()).finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(format!("{:?}", Foo(vec![10, 11])), "{10, 11}");
+     /// ```
+     ///
+     /// [`format_args!`]: crate::format_args
+     ///
+     /// In this more complex example, we use [`format_args!`] and `.debug_set()`
+     /// to build a list of match arms:
+     ///
+     /// ```rust
+     /// use std::fmt;
+     ///
+     /// struct Arm<'a, L: 'a, R: 'a>(&'a (L, R));
+     /// struct Table<'a, K: 'a, V: 'a>(&'a [(K, V)], V);
+     ///
+     /// impl<'a, L, R> fmt::Debug for Arm<'a, L, R>
+     /// where
+     ///     L: 'a + fmt::Debug, R: 'a + fmt::Debug
+     /// {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         L::fmt(&(self.0).0, fmt)?;
+     ///         fmt.write_str(" => ")?;
+     ///         R::fmt(&(self.0).1, fmt)
+     ///     }
+     /// }
+     ///
+     /// impl<'a, K, V> fmt::Debug for Table<'a, K, V>
+     /// where
+     ///     K: 'a + fmt::Debug, V: 'a + fmt::Debug
+     /// {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         fmt.debug_set()
+     ///         .entries(self.0.iter().map(Arm))
+     ///         .entry(&Arm(&(format_args!("_"), &self.1)))
+     ///         .finish()
+     ///     }
+     /// }
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn debug_set<'b>(&'b mut self) -> DebugSet<'b, 'a> {
+         builders::debug_set_new(self)
+     }
+ 
+     /// Creates a `DebugMap` builder designed to assist with creation of
+     /// `fmt::Debug` implementations for map-like structures.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::fmt;
+     ///
+     /// struct Foo(Vec<(String, i32)>);
+     ///
+     /// impl fmt::Debug for Foo {
+     ///     fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
+     ///         fmt.debug_map().entries(self.0.iter().map(|&(ref k, ref v)| (k, v))).finish()
+     ///     }
+     /// }
+     ///
+     /// assert_eq!(
+     ///     format!("{:?}",  Foo(vec![("A".to_string(), 10), ("B".to_string(), 11)])),
+     ///     r#"{"A": 10, "B": 11}"#
+     ///  );
+     /// ```
+     #[stable(feature = "debug_builders", since = "1.2.0")]
+     pub fn debug_map<'b>(&'b mut self) -> DebugMap<'b, 'a> {
+         builders::debug_map_new(self)
+     }
+ }
+ 
+ #[stable(since = "1.2.0", feature = "formatter_write")]
+ impl Write for Formatter<'_> {
+     fn write_str(&mut self, s: &str) -> Result {
+         self.buf.write_str(s)
+     }
+ 
+     fn write_char(&mut self, c: char) -> Result {
+         self.buf.write_char(c)
+     }
+ 
+     fn write_fmt(&mut self, args: Arguments<'_>) -> Result {
+         write(self.buf, args)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Display for Error {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Display::fmt("an error occurred when formatting an argument", f)
+     }
+ }
+ 
+ // Implementations of the core formatting traits
+ 
+ macro_rules! fmt_refs {
+     ($($tr:ident),*) => {
+         $(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized + $tr> $tr for &T {
+             fn fmt(&self, f: &mut Formatter<'_>) -> Result { $tr::fmt(&**self, f) }
+         }
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized + $tr> $tr for &mut T {
+             fn fmt(&self, f: &mut Formatter<'_>) -> Result { $tr::fmt(&**self, f) }
+         }
+         )*
+     }
+ }
+ 
+ fmt_refs! { Debug, Display, Octal, Binary, LowerHex, UpperHex, LowerExp, UpperExp }
+ 
+ #[unstable(feature = "never_type", issue = "35121")]
+ impl Debug for ! {
+     fn fmt(&self, _: &mut Formatter<'_>) -> Result {
+         *self
+     }
+ }
+ 
+ #[unstable(feature = "never_type", issue = "35121")]
+ impl Display for ! {
+     fn fmt(&self, _: &mut Formatter<'_>) -> Result {
+         *self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Debug for bool {
+     #[inline]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Display::fmt(self, f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Display for bool {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Display::fmt(if *self { "true" } else { "false" }, f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Debug for str {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.write_char('"')?;
+         let mut from = 0;
+         for (i, c) in self.char_indices() {
+             let esc = c.escape_debug();
+             // If char needs escaping, flush backlog so far and write, else skip
+             if esc.len() != 1 {
+                 f.write_str(&self[from..i])?;
+                 for c in esc {
+                     f.write_char(c)?;
+                 }
+                 from = i + c.len_utf8();
+             }
+         }
+         f.write_str(&self[from..])?;
+         f.write_char('"')
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Display for str {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.pad(self)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Debug for char {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.write_char('\'')?;
+         for c in self.escape_debug() {
+             f.write_char(c)?
+         }
+         f.write_char('\'')
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Display for char {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         if f.width.is_none() && f.precision.is_none() {
+             f.write_char(*self)
+         } else {
+             f.pad(self.encode_utf8(&mut [0; 4]))
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Pointer for *const T {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         let old_width = f.width;
+         let old_flags = f.flags;
+ 
+         // The alternate flag is already treated by LowerHex as being special-
+         // it denotes whether to prefix with 0x. We use it to work out whether
+         // or not to zero extend, and then unconditionally set it to get the
+         // prefix.
+         if f.alternate() {
+             f.flags |= 1 << (FlagV1::SignAwareZeroPad as u32);
+ 
+             if f.width.is_none() {
+                 f.width = Some((usize::BITS / 4) as usize + 2);
+             }
+         }
+         f.flags |= 1 << (FlagV1::Alternate as u32);
+ 
+         let ret = LowerHex::fmt(&(*self as *const () as usize), f);
+ 
+         f.width = old_width;
+         f.flags = old_flags;
+ 
+         ret
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Pointer for *mut T {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Pointer::fmt(&(*self as *const T), f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Pointer for &T {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Pointer::fmt(&(*self as *const T), f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Pointer for &mut T {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Pointer::fmt(&(&**self as *const T), f)
+     }
+ }
+ 
+ // Implementation of Display/Debug for various core types
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Debug for *const T {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Pointer::fmt(self, f)
+     }
+ }
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Debug for *mut T {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Pointer::fmt(self, f)
+     }
+ }
+ 
+ macro_rules! peel {
+     ($name:ident, $($other:ident,)*) => (tuple! { $($other,)* })
+ }
+ 
+ macro_rules! tuple {
+     () => ();
+     ( $($name:ident,)+ ) => (
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<$($name:Debug),+> Debug for ($($name,)+) where last_type!($($name,)+): ?Sized {
+             #[allow(non_snake_case, unused_assignments)]
+             fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+                 let mut builder = f.debug_tuple("");
+                 let ($(ref $name,)+) = *self;
+                 $(
+                     builder.field(&$name);
+                 )+
+ 
+                 builder.finish()
+             }
+         }
+         peel! { $($name,)+ }
+     )
+ }
+ 
+ macro_rules! last_type {
+     ($a:ident,) => { $a };
+     ($a:ident, $($rest_a:ident,)+) => { last_type!($($rest_a,)+) };
+ }
+ 
+ tuple! { T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Debug> Debug for [T] {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.debug_list().entries(self.iter()).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Debug for () {
+     #[inline]
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.pad("()")
+     }
+ }
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Debug for PhantomData<T> {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.pad("PhantomData")
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Copy + Debug> Debug for Cell<T> {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.debug_struct("Cell").field("value", &self.get()).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized + Debug> Debug for RefCell<T> {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         match self.try_borrow() {
+             Ok(borrow) => f.debug_struct("RefCell").field("value", &borrow).finish(),
+             Err(_) => {
+                 // The RefCell is mutably borrowed so we can't look at its value
+                 // here. Show a placeholder instead.
+                 struct BorrowedPlaceholder;
+ 
+                 impl Debug for BorrowedPlaceholder {
+                     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+                         f.write_str("<borrowed>")
+                     }
+                 }
+ 
+                 f.debug_struct("RefCell").field("value", &BorrowedPlaceholder).finish()
+             }
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized + Debug> Debug for Ref<'_, T> {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Debug::fmt(&**self, f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized + Debug> Debug for RefMut<'_, T> {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         Debug::fmt(&*(self.deref()), f)
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: ?Sized + Debug> Debug for UnsafeCell<T> {
+     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
+         f.pad("UnsafeCell")
+     }
+ }
+ 
+ // If you expected tests to be here, look instead at the core/tests/fmt.rs file,
+ // it's a lot easier than creating all of the rt::Piece structures here.
+ // There are also tests in the alloc crate, for those that need allocations.
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/num.rs gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/num.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/num.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/num.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,667 ----
+ //! Integer and floating-point number formatting
+ 
+ use crate::fmt;
+ use crate::mem::MaybeUninit;
+ use crate::num::flt2dec;
+ use crate::ops::{Div, Rem, Sub};
+ use crate::ptr;
+ use crate::slice;
+ use crate::str;
+ 
+ #[doc(hidden)]
+ trait DisplayInt:
+     PartialEq + PartialOrd + Div<Output = Self> + Rem<Output = Self> + Sub<Output = Self> + Copy
+ {
+     fn zero() -> Self;
+     fn from_u8(u: u8) -> Self;
+     fn to_u8(&self) -> u8;
+     fn to_u16(&self) -> u16;
+     fn to_u32(&self) -> u32;
+     fn to_u64(&self) -> u64;
+     fn to_u128(&self) -> u128;
+ }
+ 
+ macro_rules! impl_int {
+     ($($t:ident)*) => (
+       $(impl DisplayInt for $t {
+           fn zero() -> Self { 0 }
+           fn from_u8(u: u8) -> Self { u as Self }
+           fn to_u8(&self) -> u8 { *self as u8 }
+           fn to_u16(&self) -> u16 { *self as u16 }
+           fn to_u32(&self) -> u32 { *self as u32 }
+           fn to_u64(&self) -> u64 { *self as u64 }
+           fn to_u128(&self) -> u128 { *self as u128 }
+       })*
+     )
+ }
+ macro_rules! impl_uint {
+     ($($t:ident)*) => (
+       $(impl DisplayInt for $t {
+           fn zero() -> Self { 0 }
+           fn from_u8(u: u8) -> Self { u as Self }
+           fn to_u8(&self) -> u8 { *self as u8 }
+           fn to_u16(&self) -> u16 { *self as u16 }
+           fn to_u32(&self) -> u32 { *self as u32 }
+           fn to_u64(&self) -> u64 { *self as u64 }
+           fn to_u128(&self) -> u128 { *self as u128 }
+       })*
+     )
+ }
+ 
+ impl_int! { i8 i16 i32 i64 i128 isize }
+ impl_uint! { u8 u16 u32 u64 u128 usize }
+ 
+ /// A type that represents a specific radix
+ #[doc(hidden)]
+ trait GenericRadix: Sized {
+     /// The number of digits.
+     const BASE: u8;
+ 
+     /// A radix-specific prefix string.
+     const PREFIX: &'static str;
+ 
+     /// Converts an integer to corresponding radix digit.
+     fn digit(x: u8) -> u8;
+ 
+     /// Format an integer using the radix using a formatter.
+     fn fmt_int<T: DisplayInt>(&self, mut x: T, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         // The radix can be as low as 2, so we need a buffer of at least 128
+         // characters for a base 2 number.
+         let zero = T::zero();
+         let is_nonnegative = x >= zero;
+         let mut buf = [MaybeUninit::<u8>::uninit(); 128];
+         let mut curr = buf.len();
+         let base = T::from_u8(Self::BASE);
+         if is_nonnegative {
+             // Accumulate each digit of the number from the least significant
+             // to the most significant figure.
+             for byte in buf.iter_mut().rev() {
+                 let n = x % base; // Get the current place value.
+                 x = x / base; // Deaccumulate the number.
+                 byte.write(Self::digit(n.to_u8())); // Store the digit in the buffer.
+                 curr -= 1;
+                 if x == zero {
+                     // No more digits left to accumulate.
+                     break;
+                 };
+             }
+         } else {
+             // Do the same as above, but accounting for two's complement.
+             for byte in buf.iter_mut().rev() {
+                 let n = zero - (x % base); // Get the current place value.
+                 x = x / base; // Deaccumulate the number.
+                 byte.write(Self::digit(n.to_u8())); // Store the digit in the buffer.
+                 curr -= 1;
+                 if x == zero {
+                     // No more digits left to accumulate.
+                     break;
+                 };
+             }
+         }
+         let buf = &buf[curr..];
+         // SAFETY: The only chars in `buf` are created by `Self::digit` which are assumed to be
+         // valid UTF-8
+         let buf = unsafe {
+             str::from_utf8_unchecked(slice::from_raw_parts(
+                 MaybeUninit::slice_as_ptr(buf),
+                 buf.len(),
+             ))
+         };
+         f.pad_integral(is_nonnegative, Self::PREFIX, buf)
+     }
+ }
+ 
+ /// A binary (base 2) radix
+ #[derive(Clone, PartialEq)]
+ struct Binary;
+ 
+ /// An octal (base 8) radix
+ #[derive(Clone, PartialEq)]
+ struct Octal;
+ 
+ /// A hexadecimal (base 16) radix, formatted with lower-case characters
+ #[derive(Clone, PartialEq)]
+ struct LowerHex;
+ 
+ /// A hexadecimal (base 16) radix, formatted with upper-case characters
+ #[derive(Clone, PartialEq)]
+ struct UpperHex;
+ 
+ macro_rules! radix {
+     ($T:ident, $base:expr, $prefix:expr, $($x:pat => $conv:expr),+) => {
+         impl GenericRadix for $T {
+             const BASE: u8 = $base;
+             const PREFIX: &'static str = $prefix;
+             fn digit(x: u8) -> u8 {
+                 match x {
+                     $($x => $conv,)+
+                     x => panic!("number not in the range 0..={}: {}", Self::BASE - 1, x),
+                 }
+             }
+         }
+     }
+ }
+ 
+ radix! { Binary,    2, "0b", x @  0 ..=  1 => b'0' + x }
+ radix! { Octal,     8, "0o", x @  0 ..=  7 => b'0' + x }
+ radix! { LowerHex, 16, "0x", x @  0 ..=  9 => b'0' + x, x @ 10 ..= 15 => b'a' + (x - 10) }
+ radix! { UpperHex, 16, "0x", x @  0 ..=  9 => b'0' + x, x @ 10 ..= 15 => b'A' + (x - 10) }
+ 
+ macro_rules! int_base {
+     (fmt::$Trait:ident for $T:ident as $U:ident -> $Radix:ident) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl fmt::$Trait for $T {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 $Radix.fmt_int(*self as $U, f)
+             }
+         }
+     };
+ }
+ 
+ macro_rules! integer {
+     ($Int:ident, $Uint:ident) => {
+         int_base! { fmt::Binary   for $Int as $Uint  -> Binary }
+         int_base! { fmt::Octal    for $Int as $Uint  -> Octal }
+         int_base! { fmt::LowerHex for $Int as $Uint  -> LowerHex }
+         int_base! { fmt::UpperHex for $Int as $Uint  -> UpperHex }
+ 
+         int_base! { fmt::Binary   for $Uint as $Uint -> Binary }
+         int_base! { fmt::Octal    for $Uint as $Uint -> Octal }
+         int_base! { fmt::LowerHex for $Uint as $Uint -> LowerHex }
+         int_base! { fmt::UpperHex for $Uint as $Uint -> UpperHex }
+     };
+ }
+ integer! { isize, usize }
+ integer! { i8, u8 }
+ integer! { i16, u16 }
+ integer! { i32, u32 }
+ integer! { i64, u64 }
+ integer! { i128, u128 }
+ macro_rules! debug {
+     ($($T:ident)*) => {$(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl fmt::Debug for $T {
+             #[inline]
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 if f.debug_lower_hex() {
+                     fmt::LowerHex::fmt(self, f)
+                 } else if f.debug_upper_hex() {
+                     fmt::UpperHex::fmt(self, f)
+                 } else {
+                     fmt::Display::fmt(self, f)
+                 }
+             }
+         }
+     )*};
+ }
+ debug! {
+   i8 i16 i32 i64 i128 isize
+   u8 u16 u32 u64 u128 usize
+ }
+ 
+ // 2 digit decimal look up table
+ static DEC_DIGITS_LUT: &[u8; 200] = b"0001020304050607080910111213141516171819\
+       2021222324252627282930313233343536373839\
+       4041424344454647484950515253545556575859\
+       6061626364656667686970717273747576777879\
+       8081828384858687888990919293949596979899";
+ 
+ macro_rules! impl_Display {
+     ($($t:ident),* as $u:ident via $conv_fn:ident named $name:ident) => {
+         fn $name(mut n: $u, is_nonnegative: bool, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+             // 2^128 is about 3*10^38, so 39 gives an extra byte of space
+             let mut buf = [MaybeUninit::<u8>::uninit(); 39];
+             let mut curr = buf.len() as isize;
+             let buf_ptr = MaybeUninit::slice_as_mut_ptr(&mut buf);
+             let lut_ptr = DEC_DIGITS_LUT.as_ptr();
+ 
+             // SAFETY: Since `d1` and `d2` are always less than or equal to `198`, we
+             // can copy from `lut_ptr[d1..d1 + 1]` and `lut_ptr[d2..d2 + 1]`. To show
+             // that it's OK to copy into `buf_ptr`, notice that at the beginning
+             // `curr == buf.len() == 39 > log(n)` since `n < 2^128 < 10^39`, and at
+             // each step this is kept the same as `n` is divided. Since `n` is always
+             // non-negative, this means that `curr > 0` so `buf_ptr[curr..curr + 1]`
+             // is safe to access.
+             unsafe {
+                 // need at least 16 bits for the 4-characters-at-a-time to work.
+                 assert!(crate::mem::size_of::<$u>() >= 2);
+ 
+                 // eagerly decode 4 characters at a time
+                 while n >= 10000 {
+                     let rem = (n % 10000) as isize;
+                     n /= 10000;
+ 
+                     let d1 = (rem / 100) << 1;
+                     let d2 = (rem % 100) << 1;
+                     curr -= 4;
+ 
+                     // We are allowed to copy to `buf_ptr[curr..curr + 3]` here since
+                     // otherwise `curr < 0`. But then `n` was originally at least `10000^10`
+                     // which is `10^40 > 2^128 > n`.
+                     ptr::copy_nonoverlapping(lut_ptr.offset(d1), buf_ptr.offset(curr), 2);
+                     ptr::copy_nonoverlapping(lut_ptr.offset(d2), buf_ptr.offset(curr + 2), 2);
+                 }
+ 
+                 // if we reach here numbers are <= 9999, so at most 4 chars long
+                 let mut n = n as isize; // possibly reduce 64bit math
+ 
+                 // decode 2 more chars, if > 2 chars
+                 if n >= 100 {
+                     let d1 = (n % 100) << 1;
+                     n /= 100;
+                     curr -= 2;
+                     ptr::copy_nonoverlapping(lut_ptr.offset(d1), buf_ptr.offset(curr), 2);
+                 }
+ 
+                 // decode last 1 or 2 chars
+                 if n < 10 {
+                     curr -= 1;
+                     *buf_ptr.offset(curr) = (n as u8) + b'0';
+                 } else {
+                     let d1 = n << 1;
+                     curr -= 2;
+                     ptr::copy_nonoverlapping(lut_ptr.offset(d1), buf_ptr.offset(curr), 2);
+                 }
+             }
+ 
+             // SAFETY: `curr` > 0 (since we made `buf` large enough), and all the chars are valid
+             // UTF-8 since `DEC_DIGITS_LUT` is
+             let buf_slice = unsafe {
+                 str::from_utf8_unchecked(
+                     slice::from_raw_parts(buf_ptr.offset(curr), buf.len() - curr as usize))
+             };
+             f.pad_integral(is_nonnegative, "", buf_slice)
+         }
+ 
+         $(#[stable(feature = "rust1", since = "1.0.0")]
+         impl fmt::Display for $t {
+             #[allow(unused_comparisons)]
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 let is_nonnegative = *self >= 0;
+                 let n = if is_nonnegative {
+                     self.$conv_fn()
+                 } else {
+                     // convert the negative num to positive by summing 1 to it's 2 complement
+                     (!self.$conv_fn()).wrapping_add(1)
+                 };
+                 $name(n, is_nonnegative, f)
+             }
+         })*
+     };
+ }
+ 
+ macro_rules! impl_Exp {
+     ($($t:ident),* as $u:ident via $conv_fn:ident named $name:ident) => {
+         fn $name(
+             mut n: $u,
+             is_nonnegative: bool,
+             upper: bool,
+             f: &mut fmt::Formatter<'_>
+         ) -> fmt::Result {
+             let (mut n, mut exponent, trailing_zeros, added_precision) = {
+                 let mut exponent = 0;
+                 // count and remove trailing decimal zeroes
+                 while n % 10 == 0 && n >= 10 {
+                     n /= 10;
+                     exponent += 1;
+                 }
+                 let trailing_zeros = exponent;
+ 
+                 let (added_precision, subtracted_precision) = match f.precision() {
+                     Some(fmt_prec) => {
+                         // number of decimal digits minus 1
+                         let mut tmp = n;
+                         let mut prec = 0;
+                         while tmp >= 10 {
+                             tmp /= 10;
+                             prec += 1;
+                         }
+                         (fmt_prec.saturating_sub(prec), prec.saturating_sub(fmt_prec))
+                     }
+                     None => (0,0)
+                 };
+                 for _ in 1..subtracted_precision {
+                     n/=10;
+                     exponent += 1;
+                 }
+                 if subtracted_precision != 0 {
+                     let rem = n % 10;
+                     n /= 10;
+                     exponent += 1;
+                     // round up last digit
+                     if rem >= 5 {
+                         n += 1;
+                     }
+                 }
+                 (n, exponent, trailing_zeros, added_precision)
+             };
+ 
+             // 39 digits (worst case u128) + . = 40
+             // Since `curr` always decreases by the number of digits copied, this means
+             // that `curr >= 0`.
+             let mut buf = [MaybeUninit::<u8>::uninit(); 40];
+             let mut curr = buf.len() as isize; //index for buf
+             let buf_ptr = MaybeUninit::slice_as_mut_ptr(&mut buf);
+             let lut_ptr = DEC_DIGITS_LUT.as_ptr();
+ 
+             // decode 2 chars at a time
+             while n >= 100 {
+                 let d1 = ((n % 100) as isize) << 1;
+                 curr -= 2;
+                 // SAFETY: `d1 <= 198`, so we can copy from `lut_ptr[d1..d1 + 2]` since
+                 // `DEC_DIGITS_LUT` has a length of 200.
+                 unsafe {
+                     ptr::copy_nonoverlapping(lut_ptr.offset(d1), buf_ptr.offset(curr), 2);
+                 }
+                 n /= 100;
+                 exponent += 2;
+             }
+             // n is <= 99, so at most 2 chars long
+             let mut n = n as isize; // possibly reduce 64bit math
+             // decode second-to-last character
+             if n >= 10 {
+                 curr -= 1;
+                 // SAFETY: Safe since `40 > curr >= 0` (see comment)
+                 unsafe {
+                     *buf_ptr.offset(curr) = (n as u8 % 10_u8) + b'0';
+                 }
+                 n /= 10;
+                 exponent += 1;
+             }
+             // add decimal point iff >1 mantissa digit will be printed
+             if exponent != trailing_zeros || added_precision != 0 {
+                 curr -= 1;
+                 // SAFETY: Safe since `40 > curr >= 0`
+                 unsafe {
+                     *buf_ptr.offset(curr) = b'.';
+                 }
+             }
+ 
+             // SAFETY: Safe since `40 > curr >= 0`
+             let buf_slice = unsafe {
+                 // decode last character
+                 curr -= 1;
+                 *buf_ptr.offset(curr) = (n as u8) + b'0';
+ 
+                 let len = buf.len() - curr as usize;
+                 slice::from_raw_parts(buf_ptr.offset(curr), len)
+             };
+ 
+             // stores 'e' (or 'E') and the up to 2-digit exponent
+             let mut exp_buf = [MaybeUninit::<u8>::uninit(); 3];
+             let exp_ptr = MaybeUninit::slice_as_mut_ptr(&mut exp_buf);
+             // SAFETY: In either case, `exp_buf` is written within bounds and `exp_ptr[..len]`
+             // is contained within `exp_buf` since `len <= 3`.
+             let exp_slice = unsafe {
+                 *exp_ptr.offset(0) = if upper {b'E'} else {b'e'};
+                 let len = if exponent < 10 {
+                     *exp_ptr.offset(1) = (exponent as u8) + b'0';
+                     2
+                 } else {
+                     let off = exponent << 1;
+                     ptr::copy_nonoverlapping(lut_ptr.offset(off), exp_ptr.offset(1), 2);
+                     3
+                 };
+                 slice::from_raw_parts(exp_ptr, len)
+             };
+ 
+             let parts = &[
+                 flt2dec::Part::Copy(buf_slice),
+                 flt2dec::Part::Zero(added_precision),
+                 flt2dec::Part::Copy(exp_slice)
+             ];
+             let sign = if !is_nonnegative {
+                 "-"
+             } else if f.sign_plus() {
+                 "+"
+             } else {
+                 ""
+             };
+             let formatted = flt2dec::Formatted{sign, parts};
+             f.pad_formatted_parts(&formatted)
+         }
+ 
+         $(
+             #[stable(feature = "integer_exp_format", since = "1.42.0")]
+             impl fmt::LowerExp for $t {
+                 #[allow(unused_comparisons)]
+                 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                     let is_nonnegative = *self >= 0;
+                     let n = if is_nonnegative {
+                         self.$conv_fn()
+                     } else {
+                         // convert the negative num to positive by summing 1 to it's 2 complement
+                         (!self.$conv_fn()).wrapping_add(1)
+                     };
+                     $name(n, is_nonnegative, false, f)
+                 }
+             })*
+         $(
+             #[stable(feature = "integer_exp_format", since = "1.42.0")]
+             impl fmt::UpperExp for $t {
+                 #[allow(unused_comparisons)]
+                 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                     let is_nonnegative = *self >= 0;
+                     let n = if is_nonnegative {
+                         self.$conv_fn()
+                     } else {
+                         // convert the negative num to positive by summing 1 to it's 2 complement
+                         (!self.$conv_fn()).wrapping_add(1)
+                     };
+                     $name(n, is_nonnegative, true, f)
+                 }
+             })*
+     };
+ }
+ 
+ // Include wasm32 in here since it doesn't reflect the native pointer size, and
+ // often cares strongly about getting a smaller code size.
+ #[cfg(any(target_pointer_width = "64", target_arch = "wasm32"))]
+ mod imp {
+     use super::*;
+     impl_Display!(
+         i8, u8, i16, u16, i32, u32, i64, u64, usize, isize
+             as u64 via to_u64 named fmt_u64
+     );
+     impl_Exp!(
+         i8, u8, i16, u16, i32, u32, i64, u64, usize, isize
+             as u64 via to_u64 named exp_u64
+     );
+ }
+ 
+ #[cfg(not(any(target_pointer_width = "64", target_arch = "wasm32")))]
+ mod imp {
+     use super::*;
+     impl_Display!(i8, u8, i16, u16, i32, u32, isize, usize as u32 via to_u32 named fmt_u32);
+     impl_Display!(i64, u64 as u64 via to_u64 named fmt_u64);
+     impl_Exp!(i8, u8, i16, u16, i32, u32, isize, usize as u32 via to_u32 named exp_u32);
+     impl_Exp!(i64, u64 as u64 via to_u64 named exp_u64);
+ }
+ impl_Exp!(i128, u128 as u128 via to_u128 named exp_u128);
+ 
+ /// Helper function for writing a u64 into `buf` going from last to first, with `curr`.
+ fn parse_u64_into<const N: usize>(mut n: u64, buf: &mut [MaybeUninit<u8>; N], curr: &mut isize) {
+     let buf_ptr = MaybeUninit::slice_as_mut_ptr(buf);
+     let lut_ptr = DEC_DIGITS_LUT.as_ptr();
+     assert!(*curr > 19);
+ 
+     // SAFETY:
+     // Writes at most 19 characters into the buffer. Guaranteed that any ptr into LUT is at most
+     // 198, so will never OOB. There is a check above that there are at least 19 characters
+     // remaining.
+     unsafe {
+         if n >= 1e16 as u64 {
+             let to_parse = n % 1e16 as u64;
+             n /= 1e16 as u64;
+ 
+             // Some of these are nops but it looks more elegant this way.
+             let d1 = ((to_parse / 1e14 as u64) % 100) << 1;
+             let d2 = ((to_parse / 1e12 as u64) % 100) << 1;
+             let d3 = ((to_parse / 1e10 as u64) % 100) << 1;
+             let d4 = ((to_parse / 1e8 as u64) % 100) << 1;
+             let d5 = ((to_parse / 1e6 as u64) % 100) << 1;
+             let d6 = ((to_parse / 1e4 as u64) % 100) << 1;
+             let d7 = ((to_parse / 1e2 as u64) % 100) << 1;
+             let d8 = ((to_parse / 1e0 as u64) % 100) << 1;
+ 
+             *curr -= 16;
+ 
+             ptr::copy_nonoverlapping(lut_ptr.offset(d1 as isize), buf_ptr.offset(*curr + 0), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d2 as isize), buf_ptr.offset(*curr + 2), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d3 as isize), buf_ptr.offset(*curr + 4), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d4 as isize), buf_ptr.offset(*curr + 6), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d5 as isize), buf_ptr.offset(*curr + 8), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d6 as isize), buf_ptr.offset(*curr + 10), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d7 as isize), buf_ptr.offset(*curr + 12), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d8 as isize), buf_ptr.offset(*curr + 14), 2);
+         }
+         if n >= 1e8 as u64 {
+             let to_parse = n % 1e8 as u64;
+             n /= 1e8 as u64;
+ 
+             // Some of these are nops but it looks more elegant this way.
+             let d1 = ((to_parse / 1e6 as u64) % 100) << 1;
+             let d2 = ((to_parse / 1e4 as u64) % 100) << 1;
+             let d3 = ((to_parse / 1e2 as u64) % 100) << 1;
+             let d4 = ((to_parse / 1e0 as u64) % 100) << 1;
+             *curr -= 8;
+ 
+             ptr::copy_nonoverlapping(lut_ptr.offset(d1 as isize), buf_ptr.offset(*curr + 0), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d2 as isize), buf_ptr.offset(*curr + 2), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d3 as isize), buf_ptr.offset(*curr + 4), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d4 as isize), buf_ptr.offset(*curr + 6), 2);
+         }
+         // `n` < 1e8 < (1 << 32)
+         let mut n = n as u32;
+         if n >= 1e4 as u32 {
+             let to_parse = n % 1e4 as u32;
+             n /= 1e4 as u32;
+ 
+             let d1 = (to_parse / 100) << 1;
+             let d2 = (to_parse % 100) << 1;
+             *curr -= 4;
+ 
+             ptr::copy_nonoverlapping(lut_ptr.offset(d1 as isize), buf_ptr.offset(*curr + 0), 2);
+             ptr::copy_nonoverlapping(lut_ptr.offset(d2 as isize), buf_ptr.offset(*curr + 2), 2);
+         }
+ 
+         // `n` < 1e4 < (1 << 16)
+         let mut n = n as u16;
+         if n >= 100 {
+             let d1 = (n % 100) << 1;
+             n /= 100;
+             *curr -= 2;
+             ptr::copy_nonoverlapping(lut_ptr.offset(d1 as isize), buf_ptr.offset(*curr), 2);
+         }
+ 
+         // decode last 1 or 2 chars
+         if n < 10 {
+             *curr -= 1;
+             *buf_ptr.offset(*curr) = (n as u8) + b'0';
+         } else {
+             let d1 = n << 1;
+             *curr -= 2;
+             ptr::copy_nonoverlapping(lut_ptr.offset(d1 as isize), buf_ptr.offset(*curr), 2);
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Display for u128 {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt_u128(*self, true, f)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Display for i128 {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         let is_nonnegative = *self >= 0;
+         let n = if is_nonnegative {
+             self.to_u128()
+         } else {
+             // convert the negative num to positive by summing 1 to it's 2 complement
+             (!self.to_u128()).wrapping_add(1)
+         };
+         fmt_u128(n, is_nonnegative, f)
+     }
+ }
+ 
+ /// Specialized optimization for u128. Instead of taking two items at a time, it splits
+ /// into at most 2 u64s, and then chunks by 10e16, 10e8, 10e4, 10e2, and then 10e1.
+ /// It also has to handle 1 last item, as 10^40 > 2^128 > 10^39, whereas
+ /// 10^20 > 2^64 > 10^19.
+ fn fmt_u128(n: u128, is_nonnegative: bool, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+     // 2^128 is about 3*10^38, so 39 gives an extra byte of space
+     let mut buf = [MaybeUninit::<u8>::uninit(); 39];
+     let mut curr = buf.len() as isize;
+ 
+     let (n, rem) = udiv_1e19(n);
+     parse_u64_into(rem, &mut buf, &mut curr);
+ 
+     if n != 0 {
+         // 0 pad up to point
+         let target = (buf.len() - 19) as isize;
+         // SAFETY: Guaranteed that we wrote at most 19 bytes, and there must be space
+         // remaining since it has length 39
+         unsafe {
+             ptr::write_bytes(
+                 MaybeUninit::slice_as_mut_ptr(&mut buf).offset(target),
+                 b'0',
+                 (curr - target) as usize,
+             );
+         }
+         curr = target;
+ 
+         let (n, rem) = udiv_1e19(n);
+         parse_u64_into(rem, &mut buf, &mut curr);
+         // Should this following branch be annotated with unlikely?
+         if n != 0 {
+             let target = (buf.len() - 38) as isize;
+             // The raw `buf_ptr` pointer is only valid until `buf` is used the next time,
+             // buf `buf` is not used in this scope so we are good.
+             let buf_ptr = MaybeUninit::slice_as_mut_ptr(&mut buf);
+             // SAFETY: At this point we wrote at most 38 bytes, pad up to that point,
+             // There can only be at most 1 digit remaining.
+             unsafe {
+                 ptr::write_bytes(buf_ptr.offset(target), b'0', (curr - target) as usize);
+                 curr = target - 1;
+                 *buf_ptr.offset(curr) = (n as u8) + b'0';
+             }
+         }
+     }
+ 
+     // SAFETY: `curr` > 0 (since we made `buf` large enough), and all the chars are valid
+     // UTF-8 since `DEC_DIGITS_LUT` is
+     let buf_slice = unsafe {
+         str::from_utf8_unchecked(slice::from_raw_parts(
+             MaybeUninit::slice_as_mut_ptr(&mut buf).offset(curr),
+             buf.len() - curr as usize,
+         ))
+     };
+     f.pad_integral(is_nonnegative, "", buf_slice)
+ }
+ 
+ /// Partition of `n` into n > 1e19 and rem <= 1e19
+ fn udiv_1e19(n: u128) -> (u128, u64) {
+     const DIV: u64 = 1e19 as u64;
+     let high = (n >> 64) as u64;
+     if high == 0 {
+         let low = n as u64;
+         return ((low / DIV) as u128, low % DIV);
+     }
+     let sr = 65 - high.leading_zeros();
+     let mut q = n << (128 - sr);
+     let mut r = n >> sr;
+     let mut carry = 0;
+ 
+     for _ in 0..sr {
+         r = (r << 1) | (q >> 127);
+         q = (q << 1) | carry as u128;
+ 
+         let s = (DIV as u128).wrapping_sub(r).wrapping_sub(1) as i128 >> 127;
+         carry = (s & 1) as u64;
+         r -= (DIV as u128) & s as u128;
+     }
+     ((q << 1) | carry as u128, r as u64)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/rt/v1.rs gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/rt/v1.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/fmt/rt/v1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/fmt/rt/v1.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,45 ----
+ //! This is an internal module used by the ifmt! runtime. These structures are
+ //! emitted to static arrays to precompile format strings ahead of time.
+ //!
+ //! These definitions are similar to their `ct` equivalents, but differ in that
+ //! these can be statically allocated and are slightly optimized for the runtime
+ #![allow(missing_debug_implementations)]
+ 
+ #[derive(Copy, Clone)]
+ pub struct Argument {
+     pub position: usize,
+     pub format: FormatSpec,
+ }
+ 
+ #[derive(Copy, Clone)]
+ pub struct FormatSpec {
+     pub fill: char,
+     pub align: Alignment,
+     pub flags: u32,
+     pub precision: Count,
+     pub width: Count,
+ }
+ 
+ /// Possible alignments that can be requested as part of a formatting directive.
+ #[derive(Copy, Clone, PartialEq, Eq)]
+ pub enum Alignment {
+     /// Indication that contents should be left-aligned.
+     Left,
+     /// Indication that contents should be right-aligned.
+     Right,
+     /// Indication that contents should be center-aligned.
+     Center,
+     /// No alignment was requested.
+     Unknown,
+ }
+ 
+ /// Used by [width](https://doc.rust-lang.org/std/fmt/#width) and [precision](https://doc.rust-lang.org/std/fmt/#precision) specifiers.
+ #[derive(Copy, Clone)]
+ pub enum Count {
+     /// Specified with a literal number, stores the value
+     Is(usize),
+     /// Specified using `$` and `*` syntaxes, stores the index into `args`
+     Param(usize),
+     /// Not specified
+     Implied,
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/future/future.rs gcc-16-20251102/libgrust/rustc-lib/core/src/future/future.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/future/future.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/future/future.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,121 ----
+ #![stable(feature = "futures_api", since = "1.36.0")]
+ 
+ use crate::marker::Unpin;
+ use crate::ops;
+ use crate::pin::Pin;
+ use crate::task::{Context, Poll};
+ 
+ /// A future represents an asynchronous computation.
+ ///
+ /// A future is a value that may not have finished computing yet. This kind of
+ /// "asynchronous value" makes it possible for a thread to continue doing useful
+ /// work while it waits for the value to become available.
+ ///
+ /// # The `poll` method
+ ///
+ /// The core method of future, `poll`, *attempts* to resolve the future into a
+ /// final value. This method does not block if the value is not ready. Instead,
+ /// the current task is scheduled to be woken up when it's possible to make
+ /// further progress by `poll`ing again. The `context` passed to the `poll`
+ /// method can provide a [`Waker`], which is a handle for waking up the current
+ /// task.
+ ///
+ /// When using a future, you generally won't call `poll` directly, but instead
+ /// `.await` the value.
+ ///
+ /// [`Waker`]: crate::task::Waker
+ #[doc(spotlight)]
+ #[must_use = "futures do nothing unless you `.await` or poll them"]
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ #[lang = "future_trait"]
+ #[rustc_on_unimplemented(label = "`{Self}` is not a future", message = "`{Self}` is not a future")]
+ pub trait Future {
+     /// The type of value produced on completion.
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     type Output;
+ 
+     /// Attempt to resolve the future to a final value, registering
+     /// the current task for wakeup if the value is not yet available.
+     ///
+     /// # Return value
+     ///
+     /// This function returns:
+     ///
+     /// - [`Poll::Pending`] if the future is not ready yet
+     /// - [`Poll::Ready(val)`] with the result `val` of this future if it
+     ///   finished successfully.
+     ///
+     /// Once a future has finished, clients should not `poll` it again.
+     ///
+     /// When a future is not ready yet, `poll` returns `Poll::Pending` and
+     /// stores a clone of the [`Waker`] copied from the current [`Context`].
+     /// This [`Waker`] is then woken once the future can make progress.
+     /// For example, a future waiting for a socket to become
+     /// readable would call `.clone()` on the [`Waker`] and store it.
+     /// When a signal arrives elsewhere indicating that the socket is readable,
+     /// [`Waker::wake`] is called and the socket future's task is awoken.
+     /// Once a task has been woken up, it should attempt to `poll` the future
+     /// again, which may or may not produce a final value.
+     ///
+     /// Note that on multiple calls to `poll`, only the [`Waker`] from the
+     /// [`Context`] passed to the most recent call should be scheduled to
+     /// receive a wakeup.
+     ///
+     /// # Runtime characteristics
+     ///
+     /// Futures alone are *inert*; they must be *actively* `poll`ed to make
+     /// progress, meaning that each time the current task is woken up, it should
+     /// actively re-`poll` pending futures that it still has an interest in.
+     ///
+     /// The `poll` function is not called repeatedly in a tight loop -- instead,
+     /// it should only be called when the future indicates that it is ready to
+     /// make progress (by calling `wake()`). If you're familiar with the
+     /// `poll(2)` or `select(2)` syscalls on Unix it's worth noting that futures
+     /// typically do *not* suffer the same problems of "all wakeups must poll
+     /// all events"; they are more like `epoll(4)`.
+     ///
+     /// An implementation of `poll` should strive to return quickly, and should
+     /// not block. Returning quickly prevents unnecessarily clogging up
+     /// threads or event loops. If it is known ahead of time that a call to
+     /// `poll` may end up taking awhile, the work should be offloaded to a
+     /// thread pool (or something similar) to ensure that `poll` can return
+     /// quickly.
+     ///
+     /// # Panics
+     ///
+     /// Once a future has completed (returned `Ready` from `poll`), calling its
+     /// `poll` method again may panic, block forever, or cause other kinds of
+     /// problems; the `Future` trait places no requirements on the effects of
+     /// such a call. However, as the `poll` method is not marked `unsafe`,
+     /// Rust's usual rules apply: calls must never cause undefined behavior
+     /// (memory corruption, incorrect use of `unsafe` functions, or the like),
+     /// regardless of the future's state.
+     ///
+     /// [`Poll::Ready(val)`]: Poll::Ready
+     /// [`Waker`]: crate::task::Waker
+     /// [`Waker::wake`]: crate::task::Waker::wake
+     #[lang = "poll"]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output>;
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl<F: ?Sized + Future + Unpin> Future for &mut F {
+     type Output = F::Output;
+ 
+     fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+         F::poll(Pin::new(&mut **self), cx)
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl<P> Future for Pin<P>
+ where
+     P: Unpin + ops::DerefMut<Target: Future>,
+ {
+     type Output = <<P as ops::Deref>::Target as Future>::Output;
+ 
+     fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+         Pin::get_mut(self).as_mut().poll(cx)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/future/into_future.rs gcc-16-20251102/libgrust/rustc-lib/core/src/future/into_future.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/future/into_future.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/future/into_future.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,27 ----
+ use crate::future::Future;
+ 
+ /// Conversion into a `Future`.
+ #[unstable(feature = "into_future", issue = "67644")]
+ pub trait IntoFuture {
+     /// The output that the future will produce on completion.
+     #[unstable(feature = "into_future", issue = "67644")]
+     type Output;
+ 
+     /// Which kind of future are we turning this into?
+     #[unstable(feature = "into_future", issue = "67644")]
+     type Future: Future<Output = Self::Output>;
+ 
+     /// Creates a future from a value.
+     #[unstable(feature = "into_future", issue = "67644")]
+     fn into_future(self) -> Self::Future;
+ }
+ 
+ #[unstable(feature = "into_future", issue = "67644")]
+ impl<F: Future> IntoFuture for F {
+     type Output = F::Output;
+     type Future = F;
+ 
+     fn into_future(self) -> Self::Future {
+         self
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/future/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/future/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/future/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/future/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,98 ----
+ #![stable(feature = "futures_api", since = "1.36.0")]
+ 
+ //! Asynchronous values.
+ 
+ use crate::{
+     ops::{Generator, GeneratorState},
+     pin::Pin,
+     ptr::NonNull,
+     task::{Context, Poll},
+ };
+ 
+ mod future;
+ mod into_future;
+ mod pending;
+ mod poll_fn;
+ mod ready;
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub use self::future::Future;
+ 
+ #[unstable(feature = "into_future", issue = "67644")]
+ pub use into_future::IntoFuture;
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ pub use pending::{pending, Pending};
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ pub use ready::{ready, Ready};
+ 
+ #[unstable(feature = "future_poll_fn", issue = "72302")]
+ pub use poll_fn::{poll_fn, PollFn};
+ 
+ /// This type is needed because:
+ ///
+ /// a) Generators cannot implement `for<'a, 'b> Generator<&'a mut Context<'b>>`, so we need to pass
+ ///    a raw pointer (see <https://github.com/rust-lang/rust/issues/68923>).
+ /// b) Raw pointers and `NonNull` aren't `Send` or `Sync`, so that would make every single future
+ ///    non-Send/Sync as well, and we don't want that.
+ ///
+ /// It also simplifies the HIR lowering of `.await`.
+ #[doc(hidden)]
+ #[unstable(feature = "gen_future", issue = "50547")]
+ #[derive(Debug, Copy, Clone)]
+ pub struct ResumeTy(NonNull<Context<'static>>);
+ 
+ #[unstable(feature = "gen_future", issue = "50547")]
+ unsafe impl Send for ResumeTy {}
+ 
+ #[unstable(feature = "gen_future", issue = "50547")]
+ unsafe impl Sync for ResumeTy {}
+ 
+ /// Wrap a generator in a future.
+ ///
+ /// This function returns a `GenFuture` underneath, but hides it in `impl Trait` to give
+ /// better error messages (`impl Future` rather than `GenFuture<[closure.....]>`).
+ // This is `const` to avoid extra errors after we recover from `const async fn`
+ #[lang = "from_generator"]
+ #[doc(hidden)]
+ #[unstable(feature = "gen_future", issue = "50547")]
+ #[rustc_const_unstable(feature = "gen_future", issue = "50547")]
+ #[inline]
+ pub const fn from_generator<T>(gen: T) -> impl Future<Output = T::Return>
+ where
+     T: Generator<ResumeTy, Yield = ()>,
+ {
+     #[rustc_diagnostic_item = "gen_future"]
+     struct GenFuture<T: Generator<ResumeTy, Yield = ()>>(T);
+ 
+     // We rely on the fact that async/await futures are immovable in order to create
+     // self-referential borrows in the underlying generator.
+     impl<T: Generator<ResumeTy, Yield = ()>> !Unpin for GenFuture<T> {}
+ 
+     impl<T: Generator<ResumeTy, Yield = ()>> Future for GenFuture<T> {
+         type Output = T::Return;
+         fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+             // SAFETY: Safe because we're !Unpin + !Drop, and this is just a field projection.
+             let gen = unsafe { Pin::map_unchecked_mut(self, |s| &mut s.0) };
+ 
+             // Resume the generator, turning the `&mut Context` into a `NonNull` raw pointer. The
+             // `.await` lowering will safely cast that back to a `&mut Context`.
+             match gen.resume(ResumeTy(NonNull::from(cx).cast::<Context<'static>>())) {
+                 GeneratorState::Yielded(()) => Poll::Pending,
+                 GeneratorState::Complete(x) => Poll::Ready(x),
+             }
+         }
+     }
+ 
+     GenFuture(gen)
+ }
+ 
+ #[lang = "get_context"]
+ #[doc(hidden)]
+ #[unstable(feature = "gen_future", issue = "50547")]
+ #[inline]
+ pub unsafe fn get_context<'a, 'b>(cx: ResumeTy) -> &'a mut Context<'b> {
+     // SAFETY: the caller must guarantee that `cx.0` is a valid pointer
+     // that fulfills all the requirements for a mutable reference.
+     unsafe { &mut *cx.0.as_ptr().cast() }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/future/pending.rs gcc-16-20251102/libgrust/rustc-lib/core/src/future/pending.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/future/pending.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/future/pending.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,61 ----
+ use crate::fmt::{self, Debug};
+ use crate::future::Future;
+ use crate::marker;
+ use crate::pin::Pin;
+ use crate::task::{Context, Poll};
+ 
+ /// Creates a future which never resolves, representing a computation that never
+ /// finishes.
+ ///
+ /// This `struct` is created by [`pending()`]. See its
+ /// documentation for more.
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ #[must_use = "futures do nothing unless you `.await` or poll them"]
+ pub struct Pending<T> {
+     _data: marker::PhantomData<T>,
+ }
+ 
+ /// Creates a future which never resolves, representing a computation that never
+ /// finishes.
+ ///
+ /// # Examples
+ ///
+ /// ```no_run
+ /// use core::future;
+ ///
+ /// # async fn run() {
+ /// let future = future::pending();
+ /// let () = future.await;
+ /// unreachable!();
+ /// # }
+ /// ```
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ pub fn pending<T>() -> Pending<T> {
+     Pending { _data: marker::PhantomData }
+ }
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ impl<T> Future for Pending<T> {
+     type Output = T;
+ 
+     fn poll(self: Pin<&mut Self>, _: &mut Context<'_>) -> Poll<T> {
+         Poll::Pending
+     }
+ }
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ impl<T> Unpin for Pending<T> {}
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ impl<T> Debug for Pending<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Pending").finish()
+     }
+ }
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ impl<T> Clone for Pending<T> {
+     fn clone(&self) -> Self {
+         pending()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/future/poll_fn.rs gcc-16-20251102/libgrust/rustc-lib/core/src/future/poll_fn.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/future/poll_fn.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/future/poll_fn.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,64 ----
+ use crate::fmt;
+ use crate::future::Future;
+ use crate::pin::Pin;
+ use crate::task::{Context, Poll};
+ 
+ /// Creates a future that wraps a function returning `Poll`.
+ ///
+ /// Polling the future delegates to the wrapped function.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(future_poll_fn)]
+ /// # async fn run() {
+ /// use core::future::poll_fn;
+ /// use core::task::{Context, Poll};
+ ///
+ /// fn read_line(_cx: &mut Context<'_>) -> Poll<String> {
+ ///     Poll::Ready("Hello, World!".into())
+ /// }
+ ///
+ /// let read_future = poll_fn(read_line);
+ /// assert_eq!(read_future.await, "Hello, World!".to_owned());
+ /// # };
+ /// ```
+ #[unstable(feature = "future_poll_fn", issue = "72302")]
+ pub fn poll_fn<T, F>(f: F) -> PollFn<F>
+ where
+     F: FnMut(&mut Context<'_>) -> Poll<T>,
+ {
+     PollFn { f }
+ }
+ 
+ /// A Future that wraps a function returning `Poll`.
+ ///
+ /// This `struct` is created by [`poll_fn()`]. See its
+ /// documentation for more.
+ #[must_use = "futures do nothing unless you `.await` or poll them"]
+ #[unstable(feature = "future_poll_fn", issue = "72302")]
+ pub struct PollFn<F> {
+     f: F,
+ }
+ 
+ #[unstable(feature = "future_poll_fn", issue = "72302")]
+ impl<F> Unpin for PollFn<F> {}
+ 
+ #[unstable(feature = "future_poll_fn", issue = "72302")]
+ impl<F> fmt::Debug for PollFn<F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("PollFn").finish()
+     }
+ }
+ 
+ #[unstable(feature = "future_poll_fn", issue = "72302")]
+ impl<T, F> Future for PollFn<F>
+ where
+     F: FnMut(&mut Context<'_>) -> Poll<T>,
+ {
+     type Output = T;
+ 
+     fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<T> {
+         (&mut self.f)(cx)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/future/ready.rs gcc-16-20251102/libgrust/rustc-lib/core/src/future/ready.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/future/ready.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/future/ready.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,46 ----
+ use crate::future::Future;
+ use crate::pin::Pin;
+ use crate::task::{Context, Poll};
+ 
+ /// Creates a future that is immediately ready with a value.
+ ///
+ /// This `struct` is created by [`ready()`]. See its
+ /// documentation for more.
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ #[derive(Debug, Clone)]
+ #[must_use = "futures do nothing unless you `.await` or poll them"]
+ pub struct Ready<T>(Option<T>);
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ impl<T> Unpin for Ready<T> {}
+ 
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ impl<T> Future for Ready<T> {
+     type Output = T;
+ 
+     #[inline]
+     fn poll(mut self: Pin<&mut Self>, _cx: &mut Context<'_>) -> Poll<T> {
+         Poll::Ready(self.0.take().expect("Ready polled after completion"))
+     }
+ }
+ 
+ /// Creates a future that is immediately ready with a value.
+ ///
+ /// Futures created through this function are functionally similar to those
+ /// created through `async {}`. The main difference is that futures created
+ /// through this function are named and implement `Unpin`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use core::future;
+ ///
+ /// # async fn run() {
+ /// let a = future::ready(1);
+ /// assert_eq!(a.await, 1);
+ /// # }
+ /// ```
+ #[stable(feature = "future_readiness_fns", since = "1.48.0")]
+ pub fn ready<T>(t: T) -> Ready<T> {
+     Ready(Some(t))
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/hash/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/hash/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/hash/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/hash/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,712 ----
+ //! Generic hashing support.
+ //!
+ //! This module provides a generic way to compute the hash of a value. The
+ //! simplest way to make a type hashable is to use `#[derive(Hash)]`:
+ //!
+ //! # Examples
+ //!
+ //! ```rust
+ //! use std::collections::hash_map::DefaultHasher;
+ //! use std::hash::{Hash, Hasher};
+ //!
+ //! #[derive(Hash)]
+ //! struct Person {
+ //!     id: u32,
+ //!     name: String,
+ //!     phone: u64,
+ //! }
+ //!
+ //! let person1 = Person {
+ //!     id: 5,
+ //!     name: "Janet".to_string(),
+ //!     phone: 555_666_7777,
+ //! };
+ //! let person2 = Person {
+ //!     id: 5,
+ //!     name: "Bob".to_string(),
+ //!     phone: 555_666_7777,
+ //! };
+ //!
+ //! assert!(calculate_hash(&person1) != calculate_hash(&person2));
+ //!
+ //! fn calculate_hash<T: Hash>(t: &T) -> u64 {
+ //!     let mut s = DefaultHasher::new();
+ //!     t.hash(&mut s);
+ //!     s.finish()
+ //! }
+ //! ```
+ //!
+ //! If you need more control over how a value is hashed, you need to implement
+ //! the [`Hash`] trait:
+ //!
+ //! ```rust
+ //! use std::collections::hash_map::DefaultHasher;
+ //! use std::hash::{Hash, Hasher};
+ //!
+ //! struct Person {
+ //!     id: u32,
+ //!     # #[allow(dead_code)]
+ //!     name: String,
+ //!     phone: u64,
+ //! }
+ //!
+ //! impl Hash for Person {
+ //!     fn hash<H: Hasher>(&self, state: &mut H) {
+ //!         self.id.hash(state);
+ //!         self.phone.hash(state);
+ //!     }
+ //! }
+ //!
+ //! let person1 = Person {
+ //!     id: 5,
+ //!     name: "Janet".to_string(),
+ //!     phone: 555_666_7777,
+ //! };
+ //! let person2 = Person {
+ //!     id: 5,
+ //!     name: "Bob".to_string(),
+ //!     phone: 555_666_7777,
+ //! };
+ //!
+ //! assert_eq!(calculate_hash(&person1), calculate_hash(&person2));
+ //!
+ //! fn calculate_hash<T: Hash>(t: &T) -> u64 {
+ //!     let mut s = DefaultHasher::new();
+ //!     t.hash(&mut s);
+ //!     s.finish()
+ //! }
+ //! ```
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::fmt;
+ use crate::marker;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow(deprecated)]
+ pub use self::sip::SipHasher;
+ 
+ #[unstable(feature = "hashmap_internals", issue = "none")]
+ #[allow(deprecated)]
+ #[doc(hidden)]
+ pub use self::sip::SipHasher13;
+ 
+ mod sip;
+ 
+ /// A hashable type.
+ ///
+ /// Types implementing `Hash` are able to be [`hash`]ed with an instance of
+ /// [`Hasher`].
+ ///
+ /// ## Implementing `Hash`
+ ///
+ /// You can derive `Hash` with `#[derive(Hash)]` if all fields implement `Hash`.
+ /// The resulting hash will be the combination of the values from calling
+ /// [`hash`] on each field.
+ ///
+ /// ```
+ /// #[derive(Hash)]
+ /// struct Rustacean {
+ ///     name: String,
+ ///     country: String,
+ /// }
+ /// ```
+ ///
+ /// If you need more control over how a value is hashed, you can of course
+ /// implement the `Hash` trait yourself:
+ ///
+ /// ```
+ /// use std::hash::{Hash, Hasher};
+ ///
+ /// struct Person {
+ ///     id: u32,
+ ///     name: String,
+ ///     phone: u64,
+ /// }
+ ///
+ /// impl Hash for Person {
+ ///     fn hash<H: Hasher>(&self, state: &mut H) {
+ ///         self.id.hash(state);
+ ///         self.phone.hash(state);
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// ## `Hash` and `Eq`
+ ///
+ /// When implementing both `Hash` and [`Eq`], it is important that the following
+ /// property holds:
+ ///
+ /// ```text
+ /// k1 == k2 -> hash(k1) == hash(k2)
+ /// ```
+ ///
+ /// In other words, if two keys are equal, their hashes must also be equal.
+ /// [`HashMap`] and [`HashSet`] both rely on this behavior.
+ ///
+ /// Thankfully, you won't need to worry about upholding this property when
+ /// deriving both [`Eq`] and `Hash` with `#[derive(PartialEq, Eq, Hash)]`.
+ ///
+ /// [`HashMap`]: ../../std/collections/struct.HashMap.html
+ /// [`HashSet`]: ../../std/collections/struct.HashSet.html
+ /// [`hash`]: Hash::hash
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Hash {
+     /// Feeds this value into the given [`Hasher`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::collections::hash_map::DefaultHasher;
+     /// use std::hash::{Hash, Hasher};
+     ///
+     /// let mut hasher = DefaultHasher::new();
+     /// 7920.hash(&mut hasher);
+     /// println!("Hash is {:x}!", hasher.finish());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn hash<H: Hasher>(&self, state: &mut H);
+ 
+     /// Feeds a slice of this type into the given [`Hasher`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::collections::hash_map::DefaultHasher;
+     /// use std::hash::{Hash, Hasher};
+     ///
+     /// let mut hasher = DefaultHasher::new();
+     /// let numbers = [6, 28, 496, 8128];
+     /// Hash::hash_slice(&numbers, &mut hasher);
+     /// println!("Hash is {:x}!", hasher.finish());
+     /// ```
+     #[stable(feature = "hash_slice", since = "1.3.0")]
+     fn hash_slice<H: Hasher>(data: &[Self], state: &mut H)
+     where
+         Self: Sized,
+     {
+         for piece in data {
+             piece.hash(state);
+         }
+     }
+ }
+ 
+ // Separate module to reexport the macro `Hash` from prelude without the trait `Hash`.
+ pub(crate) mod macros {
+     /// Derive macro generating an impl of the trait `Hash`.
+     #[rustc_builtin_macro]
+     #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+     #[allow_internal_unstable(core_intrinsics)]
+     pub macro Hash($item:item) {
+         /* compiler built-in */
+     }
+ }
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[doc(inline)]
+ pub use macros::Hash;
+ 
+ /// A trait for hashing an arbitrary stream of bytes.
+ ///
+ /// Instances of `Hasher` usually represent state that is changed while hashing
+ /// data.
+ ///
+ /// `Hasher` provides a fairly basic interface for retrieving the generated hash
+ /// (with [`finish`]), and writing integers as well as slices of bytes into an
+ /// instance (with [`write`] and [`write_u8`] etc.). Most of the time, `Hasher`
+ /// instances are used in conjunction with the [`Hash`] trait.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::collections::hash_map::DefaultHasher;
+ /// use std::hash::Hasher;
+ ///
+ /// let mut hasher = DefaultHasher::new();
+ ///
+ /// hasher.write_u32(1989);
+ /// hasher.write_u8(11);
+ /// hasher.write_u8(9);
+ /// hasher.write(b"Huh?");
+ ///
+ /// println!("Hash is {:x}!", hasher.finish());
+ /// ```
+ ///
+ /// [`finish`]: Hasher::finish
+ /// [`write`]: Hasher::write
+ /// [`write_u8`]: Hasher::write_u8
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Hasher {
+     /// Returns the hash value for the values written so far.
+     ///
+     /// Despite its name, the method does not reset the hasher’s internal
+     /// state. Additional [`write`]s will continue from the current value.
+     /// If you need to start a fresh hash value, you will have to create
+     /// a new hasher.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::collections::hash_map::DefaultHasher;
+     /// use std::hash::Hasher;
+     ///
+     /// let mut hasher = DefaultHasher::new();
+     /// hasher.write(b"Cool!");
+     ///
+     /// println!("Hash is {:x}!", hasher.finish());
+     /// ```
+     ///
+     /// [`write`]: Hasher::write
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn finish(&self) -> u64;
+ 
+     /// Writes some data into this `Hasher`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::collections::hash_map::DefaultHasher;
+     /// use std::hash::Hasher;
+     ///
+     /// let mut hasher = DefaultHasher::new();
+     /// let data = [0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef];
+     ///
+     /// hasher.write(&data);
+     ///
+     /// println!("Hash is {:x}!", hasher.finish());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn write(&mut self, bytes: &[u8]);
+ 
+     /// Writes a single `u8` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_u8(&mut self, i: u8) {
+         self.write(&[i])
+     }
+     /// Writes a single `u16` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_u16(&mut self, i: u16) {
+         self.write(&i.to_ne_bytes())
+     }
+     /// Writes a single `u32` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_u32(&mut self, i: u32) {
+         self.write(&i.to_ne_bytes())
+     }
+     /// Writes a single `u64` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_u64(&mut self, i: u64) {
+         self.write(&i.to_ne_bytes())
+     }
+     /// Writes a single `u128` into this hasher.
+     #[inline]
+     #[stable(feature = "i128", since = "1.26.0")]
+     fn write_u128(&mut self, i: u128) {
+         self.write(&i.to_ne_bytes())
+     }
+     /// Writes a single `usize` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_usize(&mut self, i: usize) {
+         self.write(&i.to_ne_bytes())
+     }
+ 
+     /// Writes a single `i8` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_i8(&mut self, i: i8) {
+         self.write_u8(i as u8)
+     }
+     /// Writes a single `i16` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_i16(&mut self, i: i16) {
+         self.write_u16(i as u16)
+     }
+     /// Writes a single `i32` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_i32(&mut self, i: i32) {
+         self.write_u32(i as u32)
+     }
+     /// Writes a single `i64` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_i64(&mut self, i: i64) {
+         self.write_u64(i as u64)
+     }
+     /// Writes a single `i128` into this hasher.
+     #[inline]
+     #[stable(feature = "i128", since = "1.26.0")]
+     fn write_i128(&mut self, i: i128) {
+         self.write_u128(i as u128)
+     }
+     /// Writes a single `isize` into this hasher.
+     #[inline]
+     #[stable(feature = "hasher_write", since = "1.3.0")]
+     fn write_isize(&mut self, i: isize) {
+         self.write_usize(i as usize)
+     }
+ }
+ 
+ #[stable(feature = "indirect_hasher_impl", since = "1.22.0")]
+ impl<H: Hasher + ?Sized> Hasher for &mut H {
+     fn finish(&self) -> u64 {
+         (**self).finish()
+     }
+     fn write(&mut self, bytes: &[u8]) {
+         (**self).write(bytes)
+     }
+     fn write_u8(&mut self, i: u8) {
+         (**self).write_u8(i)
+     }
+     fn write_u16(&mut self, i: u16) {
+         (**self).write_u16(i)
+     }
+     fn write_u32(&mut self, i: u32) {
+         (**self).write_u32(i)
+     }
+     fn write_u64(&mut self, i: u64) {
+         (**self).write_u64(i)
+     }
+     fn write_u128(&mut self, i: u128) {
+         (**self).write_u128(i)
+     }
+     fn write_usize(&mut self, i: usize) {
+         (**self).write_usize(i)
+     }
+     fn write_i8(&mut self, i: i8) {
+         (**self).write_i8(i)
+     }
+     fn write_i16(&mut self, i: i16) {
+         (**self).write_i16(i)
+     }
+     fn write_i32(&mut self, i: i32) {
+         (**self).write_i32(i)
+     }
+     fn write_i64(&mut self, i: i64) {
+         (**self).write_i64(i)
+     }
+     fn write_i128(&mut self, i: i128) {
+         (**self).write_i128(i)
+     }
+     fn write_isize(&mut self, i: isize) {
+         (**self).write_isize(i)
+     }
+ }
+ 
+ /// A trait for creating instances of [`Hasher`].
+ ///
+ /// A `BuildHasher` is typically used (e.g., by [`HashMap`]) to create
+ /// [`Hasher`]s for each key such that they are hashed independently of one
+ /// another, since [`Hasher`]s contain state.
+ ///
+ /// For each instance of `BuildHasher`, the [`Hasher`]s created by
+ /// [`build_hasher`] should be identical. That is, if the same stream of bytes
+ /// is fed into each hasher, the same output will also be generated.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::collections::hash_map::RandomState;
+ /// use std::hash::{BuildHasher, Hasher};
+ ///
+ /// let s = RandomState::new();
+ /// let mut hasher_1 = s.build_hasher();
+ /// let mut hasher_2 = s.build_hasher();
+ ///
+ /// hasher_1.write_u32(8128);
+ /// hasher_2.write_u32(8128);
+ ///
+ /// assert_eq!(hasher_1.finish(), hasher_2.finish());
+ /// ```
+ ///
+ /// [`build_hasher`]: BuildHasher::build_hasher
+ /// [`HashMap`]: ../../std/collections/struct.HashMap.html
+ #[stable(since = "1.7.0", feature = "build_hasher")]
+ pub trait BuildHasher {
+     /// Type of the hasher that will be created.
+     #[stable(since = "1.7.0", feature = "build_hasher")]
+     type Hasher: Hasher;
+ 
+     /// Creates a new hasher.
+     ///
+     /// Each call to `build_hasher` on the same instance should produce identical
+     /// [`Hasher`]s.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::collections::hash_map::RandomState;
+     /// use std::hash::BuildHasher;
+     ///
+     /// let s = RandomState::new();
+     /// let new_s = s.build_hasher();
+     /// ```
+     #[stable(since = "1.7.0", feature = "build_hasher")]
+     fn build_hasher(&self) -> Self::Hasher;
+ }
+ 
+ /// Used to create a default [`BuildHasher`] instance for types that implement
+ /// [`Hasher`] and [`Default`].
+ ///
+ /// `BuildHasherDefault<H>` can be used when a type `H` implements [`Hasher`] and
+ /// [`Default`], and you need a corresponding [`BuildHasher`] instance, but none is
+ /// defined.
+ ///
+ /// Any `BuildHasherDefault` is [zero-sized]. It can be created with
+ /// [`default`][method.default]. When using `BuildHasherDefault` with [`HashMap`] or
+ /// [`HashSet`], this doesn't need to be done, since they implement appropriate
+ /// [`Default`] instances themselves.
+ ///
+ /// # Examples
+ ///
+ /// Using `BuildHasherDefault` to specify a custom [`BuildHasher`] for
+ /// [`HashMap`]:
+ ///
+ /// ```
+ /// use std::collections::HashMap;
+ /// use std::hash::{BuildHasherDefault, Hasher};
+ ///
+ /// #[derive(Default)]
+ /// struct MyHasher;
+ ///
+ /// impl Hasher for MyHasher {
+ ///     fn write(&mut self, bytes: &[u8]) {
+ ///         // Your hashing algorithm goes here!
+ ///        unimplemented!()
+ ///     }
+ ///
+ ///     fn finish(&self) -> u64 {
+ ///         // Your hashing algorithm goes here!
+ ///         unimplemented!()
+ ///     }
+ /// }
+ ///
+ /// type MyBuildHasher = BuildHasherDefault<MyHasher>;
+ ///
+ /// let hash_map = HashMap::<u32, u32, MyBuildHasher>::default();
+ /// ```
+ ///
+ /// [method.default]: BuildHasherDefault::default
+ /// [`HashMap`]: ../../std/collections/struct.HashMap.html
+ /// [`HashSet`]: ../../std/collections/struct.HashSet.html
+ /// [zero-sized]: https://doc.rust-lang.org/nomicon/exotic-sizes.html#zero-sized-types-zsts
+ #[stable(since = "1.7.0", feature = "build_hasher")]
+ pub struct BuildHasherDefault<H>(marker::PhantomData<H>);
+ 
+ #[stable(since = "1.9.0", feature = "core_impl_debug")]
+ impl<H> fmt::Debug for BuildHasherDefault<H> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("BuildHasherDefault")
+     }
+ }
+ 
+ #[stable(since = "1.7.0", feature = "build_hasher")]
+ impl<H: Default + Hasher> BuildHasher for BuildHasherDefault<H> {
+     type Hasher = H;
+ 
+     fn build_hasher(&self) -> H {
+         H::default()
+     }
+ }
+ 
+ #[stable(since = "1.7.0", feature = "build_hasher")]
+ impl<H> Clone for BuildHasherDefault<H> {
+     fn clone(&self) -> BuildHasherDefault<H> {
+         BuildHasherDefault(marker::PhantomData)
+     }
+ }
+ 
+ #[stable(since = "1.7.0", feature = "build_hasher")]
+ impl<H> Default for BuildHasherDefault<H> {
+     fn default() -> BuildHasherDefault<H> {
+         BuildHasherDefault(marker::PhantomData)
+     }
+ }
+ 
+ #[stable(since = "1.29.0", feature = "build_hasher_eq")]
+ impl<H> PartialEq for BuildHasherDefault<H> {
+     fn eq(&self, _other: &BuildHasherDefault<H>) -> bool {
+         true
+     }
+ }
+ 
+ #[stable(since = "1.29.0", feature = "build_hasher_eq")]
+ impl<H> Eq for BuildHasherDefault<H> {}
+ 
+ mod impls {
+     use crate::mem;
+     use crate::slice;
+ 
+     use super::*;
+ 
+     macro_rules! impl_write {
+         ($(($ty:ident, $meth:ident),)*) => {$(
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl Hash for $ty {
+                 fn hash<H: Hasher>(&self, state: &mut H) {
+                     state.$meth(*self)
+                 }
+ 
+                 fn hash_slice<H: Hasher>(data: &[$ty], state: &mut H) {
+                     let newlen = data.len() * mem::size_of::<$ty>();
+                     let ptr = data.as_ptr() as *const u8;
+                     // SAFETY: `ptr` is valid and aligned, as this macro is only used
+                     // for numeric primitives which have no padding. The new slice only
+                     // spans across `data` and is never mutated, and its total size is the
+                     // same as the original `data` so it can't be over `isize::MAX`.
+                     state.write(unsafe { slice::from_raw_parts(ptr, newlen) })
+                 }
+             }
+         )*}
+     }
+ 
+     impl_write! {
+         (u8, write_u8),
+         (u16, write_u16),
+         (u32, write_u32),
+         (u64, write_u64),
+         (usize, write_usize),
+         (i8, write_i8),
+         (i16, write_i16),
+         (i32, write_i32),
+         (i64, write_i64),
+         (isize, write_isize),
+         (u128, write_u128),
+         (i128, write_i128),
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl Hash for bool {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             state.write_u8(*self as u8)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl Hash for char {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             state.write_u32(*self as u32)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl Hash for str {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             state.write(self.as_bytes());
+             state.write_u8(0xff)
+         }
+     }
+ 
+     #[stable(feature = "never_hash", since = "1.29.0")]
+     impl Hash for ! {
+         fn hash<H: Hasher>(&self, _: &mut H) {
+             *self
+         }
+     }
+ 
+     macro_rules! impl_hash_tuple {
+         () => (
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl Hash for () {
+                 fn hash<H: Hasher>(&self, _state: &mut H) {}
+             }
+         );
+ 
+         ( $($name:ident)+) => (
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl<$($name: Hash),+> Hash for ($($name,)+) where last_type!($($name,)+): ?Sized {
+                 #[allow(non_snake_case)]
+                 fn hash<S: Hasher>(&self, state: &mut S) {
+                     let ($(ref $name,)+) = *self;
+                     $($name.hash(state);)+
+                 }
+             }
+         );
+     }
+ 
+     macro_rules! last_type {
+         ($a:ident,) => { $a };
+         ($a:ident, $($rest_a:ident,)+) => { last_type!($($rest_a,)+) };
+     }
+ 
+     impl_hash_tuple! {}
+     impl_hash_tuple! { A }
+     impl_hash_tuple! { A B }
+     impl_hash_tuple! { A B C }
+     impl_hash_tuple! { A B C D }
+     impl_hash_tuple! { A B C D E }
+     impl_hash_tuple! { A B C D E F }
+     impl_hash_tuple! { A B C D E F G }
+     impl_hash_tuple! { A B C D E F G H }
+     impl_hash_tuple! { A B C D E F G H I }
+     impl_hash_tuple! { A B C D E F G H I J }
+     impl_hash_tuple! { A B C D E F G H I J K }
+     impl_hash_tuple! { A B C D E F G H I J K L }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: Hash> Hash for [T] {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             self.len().hash(state);
+             Hash::hash_slice(self, state)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized + Hash> Hash for &T {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             (**self).hash(state);
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized + Hash> Hash for &mut T {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             (**self).hash(state);
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Hash for *const T {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             if mem::size_of::<Self>() == mem::size_of::<usize>() {
+                 // Thin pointer
+                 state.write_usize(*self as *const () as usize);
+             } else {
+                 // Fat pointer
+                 // SAFETY: we are accessing the memory occupied by `self`
+                 // which is guaranteed to be valid.
+                 // This assumes a fat pointer can be represented by a `(usize, usize)`,
+                 // which is safe to do in `std` because it is shipped and kept in sync
+                 // with the implementation of fat pointers in `rustc`.
+                 let (a, b) = unsafe { *(self as *const Self as *const (usize, usize)) };
+                 state.write_usize(a);
+                 state.write_usize(b);
+             }
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Hash for *mut T {
+         fn hash<H: Hasher>(&self, state: &mut H) {
+             if mem::size_of::<Self>() == mem::size_of::<usize>() {
+                 // Thin pointer
+                 state.write_usize(*self as *const () as usize);
+             } else {
+                 // Fat pointer
+                 // SAFETY: we are accessing the memory occupied by `self`
+                 // which is guaranteed to be valid.
+                 // This assumes a fat pointer can be represented by a `(usize, usize)`,
+                 // which is safe to do in `std` because it is shipped and kept in sync
+                 // with the implementation of fat pointers in `rustc`.
+                 let (a, b) = unsafe { *(self as *const Self as *const (usize, usize)) };
+                 state.write_usize(a);
+                 state.write_usize(b);
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/hash/sip.rs gcc-16-20251102/libgrust/rustc-lib/core/src/hash/sip.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/hash/sip.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/hash/sip.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,388 ----
+ //! An implementation of SipHash.
+ 
+ #![allow(deprecated)] // the types in this module are deprecated
+ 
+ use crate::cmp;
+ use crate::marker::PhantomData;
+ use crate::mem;
+ use crate::ptr;
+ 
+ /// An implementation of SipHash 1-3.
+ ///
+ /// This is currently the default hashing function used by standard library
+ /// (e.g., `collections::HashMap` uses it by default).
+ ///
+ /// See: <https://131002.net/siphash>
+ #[unstable(feature = "hashmap_internals", issue = "none")]
+ #[rustc_deprecated(
+     since = "1.13.0",
+     reason = "use `std::collections::hash_map::DefaultHasher` instead"
+ )]
+ #[derive(Debug, Clone, Default)]
+ #[doc(hidden)]
+ pub struct SipHasher13 {
+     hasher: Hasher<Sip13Rounds>,
+ }
+ 
+ /// An implementation of SipHash 2-4.
+ ///
+ /// See: <https://131002.net/siphash/>
+ #[unstable(feature = "hashmap_internals", issue = "none")]
+ #[rustc_deprecated(
+     since = "1.13.0",
+     reason = "use `std::collections::hash_map::DefaultHasher` instead"
+ )]
+ #[derive(Debug, Clone, Default)]
+ struct SipHasher24 {
+     hasher: Hasher<Sip24Rounds>,
+ }
+ 
+ /// An implementation of SipHash 2-4.
+ ///
+ /// See: <https://131002.net/siphash/>
+ ///
+ /// SipHash is a general-purpose hashing function: it runs at a good
+ /// speed (competitive with Spooky and City) and permits strong _keyed_
+ /// hashing. This lets you key your hash tables from a strong RNG, such as
+ /// [`rand::os::OsRng`](https://doc.rust-lang.org/rand/rand/os/struct.OsRng.html).
+ ///
+ /// Although the SipHash algorithm is considered to be generally strong,
+ /// it is not intended for cryptographic purposes. As such, all
+ /// cryptographic uses of this implementation are _strongly discouraged_.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_deprecated(
+     since = "1.13.0",
+     reason = "use `std::collections::hash_map::DefaultHasher` instead"
+ )]
+ #[derive(Debug, Clone, Default)]
+ pub struct SipHasher(SipHasher24);
+ 
+ #[derive(Debug)]
+ struct Hasher<S: Sip> {
+     k0: u64,
+     k1: u64,
+     length: usize, // how many bytes we've processed
+     state: State,  // hash State
+     tail: u64,     // unprocessed bytes le
+     ntail: usize,  // how many bytes in tail are valid
+     _marker: PhantomData<S>,
+ }
+ 
+ #[derive(Debug, Clone, Copy)]
+ #[repr(C)]
+ struct State {
+     // v0, v2 and v1, v3 show up in pairs in the algorithm,
+     // and simd implementations of SipHash will use vectors
+     // of v02 and v13. By placing them in this order in the struct,
+     // the compiler can pick up on just a few simd optimizations by itself.
+     v0: u64,
+     v2: u64,
+     v1: u64,
+     v3: u64,
+ }
+ 
+ macro_rules! compress {
+     ($state:expr) => {{ compress!($state.v0, $state.v1, $state.v2, $state.v3) }};
+     ($v0:expr, $v1:expr, $v2:expr, $v3:expr) => {{
+         $v0 = $v0.wrapping_add($v1);
+         $v1 = $v1.rotate_left(13);
+         $v1 ^= $v0;
+         $v0 = $v0.rotate_left(32);
+         $v2 = $v2.wrapping_add($v3);
+         $v3 = $v3.rotate_left(16);
+         $v3 ^= $v2;
+         $v0 = $v0.wrapping_add($v3);
+         $v3 = $v3.rotate_left(21);
+         $v3 ^= $v0;
+         $v2 = $v2.wrapping_add($v1);
+         $v1 = $v1.rotate_left(17);
+         $v1 ^= $v2;
+         $v2 = $v2.rotate_left(32);
+     }};
+ }
+ 
+ /// Loads an integer of the desired type from a byte stream, in LE order. Uses
+ /// `copy_nonoverlapping` to let the compiler generate the most efficient way
+ /// to load it from a possibly unaligned address.
+ ///
+ /// Unsafe because: unchecked indexing at i..i+size_of(int_ty)
+ macro_rules! load_int_le {
+     ($buf:expr, $i:expr, $int_ty:ident) => {{
+         debug_assert!($i + mem::size_of::<$int_ty>() <= $buf.len());
+         let mut data = 0 as $int_ty;
+         ptr::copy_nonoverlapping(
+             $buf.as_ptr().add($i),
+             &mut data as *mut _ as *mut u8,
+             mem::size_of::<$int_ty>(),
+         );
+         data.to_le()
+     }};
+ }
+ 
+ /// Loads a u64 using up to 7 bytes of a byte slice. It looks clumsy but the
+ /// `copy_nonoverlapping` calls that occur (via `load_int_le!`) all have fixed
+ /// sizes and avoid calling `memcpy`, which is good for speed.
+ ///
+ /// Unsafe because: unchecked indexing at start..start+len
+ #[inline]
+ unsafe fn u8to64_le(buf: &[u8], start: usize, len: usize) -> u64 {
+     debug_assert!(len < 8);
+     let mut i = 0; // current byte index (from LSB) in the output u64
+     let mut out = 0;
+     if i + 3 < len {
+         // SAFETY: `i` cannot be greater than `len`, and the caller must guarantee
+         // that the index start..start+len is in bounds.
+         out = unsafe { load_int_le!(buf, start + i, u32) } as u64;
+         i += 4;
+     }
+     if i + 1 < len {
+         // SAFETY: same as above.
+         out |= (unsafe { load_int_le!(buf, start + i, u16) } as u64) << (i * 8);
+         i += 2
+     }
+     if i < len {
+         // SAFETY: same as above.
+         out |= (unsafe { *buf.get_unchecked(start + i) } as u64) << (i * 8);
+         i += 1;
+     }
+     debug_assert_eq!(i, len);
+     out
+ }
+ 
+ impl SipHasher {
+     /// Creates a new `SipHasher` with the two initial keys set to 0.
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.13.0",
+         reason = "use `std::collections::hash_map::DefaultHasher` instead"
+     )]
+     pub fn new() -> SipHasher {
+         SipHasher::new_with_keys(0, 0)
+     }
+ 
+     /// Creates a `SipHasher` that is keyed off the provided keys.
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.13.0",
+         reason = "use `std::collections::hash_map::DefaultHasher` instead"
+     )]
+     pub fn new_with_keys(key0: u64, key1: u64) -> SipHasher {
+         SipHasher(SipHasher24 { hasher: Hasher::new_with_keys(key0, key1) })
+     }
+ }
+ 
+ impl SipHasher13 {
+     /// Creates a new `SipHasher13` with the two initial keys set to 0.
+     #[inline]
+     #[unstable(feature = "hashmap_internals", issue = "none")]
+     #[rustc_deprecated(
+         since = "1.13.0",
+         reason = "use `std::collections::hash_map::DefaultHasher` instead"
+     )]
+     pub fn new() -> SipHasher13 {
+         SipHasher13::new_with_keys(0, 0)
+     }
+ 
+     /// Creates a `SipHasher13` that is keyed off the provided keys.
+     #[inline]
+     #[unstable(feature = "hashmap_internals", issue = "none")]
+     #[rustc_deprecated(
+         since = "1.13.0",
+         reason = "use `std::collections::hash_map::DefaultHasher` instead"
+     )]
+     pub fn new_with_keys(key0: u64, key1: u64) -> SipHasher13 {
+         SipHasher13 { hasher: Hasher::new_with_keys(key0, key1) }
+     }
+ }
+ 
+ impl<S: Sip> Hasher<S> {
+     #[inline]
+     fn new_with_keys(key0: u64, key1: u64) -> Hasher<S> {
+         let mut state = Hasher {
+             k0: key0,
+             k1: key1,
+             length: 0,
+             state: State { v0: 0, v1: 0, v2: 0, v3: 0 },
+             tail: 0,
+             ntail: 0,
+             _marker: PhantomData,
+         };
+         state.reset();
+         state
+     }
+ 
+     #[inline]
+     fn reset(&mut self) {
+         self.length = 0;
+         self.state.v0 = self.k0 ^ 0x736f6d6570736575;
+         self.state.v1 = self.k1 ^ 0x646f72616e646f6d;
+         self.state.v2 = self.k0 ^ 0x6c7967656e657261;
+         self.state.v3 = self.k1 ^ 0x7465646279746573;
+         self.ntail = 0;
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl super::Hasher for SipHasher {
+     #[inline]
+     fn write(&mut self, msg: &[u8]) {
+         self.0.hasher.write(msg)
+     }
+ 
+     #[inline]
+     fn finish(&self) -> u64 {
+         self.0.hasher.finish()
+     }
+ }
+ 
+ #[unstable(feature = "hashmap_internals", issue = "none")]
+ impl super::Hasher for SipHasher13 {
+     #[inline]
+     fn write(&mut self, msg: &[u8]) {
+         self.hasher.write(msg)
+     }
+ 
+     #[inline]
+     fn finish(&self) -> u64 {
+         self.hasher.finish()
+     }
+ }
+ 
+ impl<S: Sip> super::Hasher for Hasher<S> {
+     // Note: no integer hashing methods (`write_u*`, `write_i*`) are defined
+     // for this type. We could add them, copy the `short_write` implementation
+     // in librustc_data_structures/sip128.rs, and add `write_u*`/`write_i*`
+     // methods to `SipHasher`, `SipHasher13`, and `DefaultHasher`. This would
+     // greatly speed up integer hashing by those hashers, at the cost of
+     // slightly slowing down compile speeds on some benchmarks. See #69152 for
+     // details.
+     #[inline]
+     fn write(&mut self, msg: &[u8]) {
+         let length = msg.len();
+         self.length += length;
+ 
+         let mut needed = 0;
+ 
+         if self.ntail != 0 {
+             needed = 8 - self.ntail;
+             // SAFETY: `cmp::min(length, needed)` is guaranteed to not be over `length`
+             self.tail |= unsafe { u8to64_le(msg, 0, cmp::min(length, needed)) } << (8 * self.ntail);
+             if length < needed {
+                 self.ntail += length;
+                 return;
+             } else {
+                 self.state.v3 ^= self.tail;
+                 S::c_rounds(&mut self.state);
+                 self.state.v0 ^= self.tail;
+                 self.ntail = 0;
+             }
+         }
+ 
+         // Buffered tail is now flushed, process new input.
+         let len = length - needed;
+         let left = len & 0x7; // len % 8
+ 
+         let mut i = needed;
+         while i < len - left {
+             // SAFETY: because `len - left` is the biggest multiple of 8 under
+             // `len`, and because `i` starts at `needed` where `len` is `length - needed`,
+             // `i + 8` is guaranteed to be less than or equal to `length`.
+             let mi = unsafe { load_int_le!(msg, i, u64) };
+ 
+             self.state.v3 ^= mi;
+             S::c_rounds(&mut self.state);
+             self.state.v0 ^= mi;
+ 
+             i += 8;
+         }
+ 
+         // SAFETY: `i` is now `needed + len.div_euclid(8) * 8`,
+         // so `i + left` = `needed + len` = `length`, which is by
+         // definition equal to `msg.len()`.
+         self.tail = unsafe { u8to64_le(msg, i, left) };
+         self.ntail = left;
+     }
+ 
+     #[inline]
+     fn finish(&self) -> u64 {
+         let mut state = self.state;
+ 
+         let b: u64 = ((self.length as u64 & 0xff) << 56) | self.tail;
+ 
+         state.v3 ^= b;
+         S::c_rounds(&mut state);
+         state.v0 ^= b;
+ 
+         state.v2 ^= 0xff;
+         S::d_rounds(&mut state);
+ 
+         state.v0 ^ state.v1 ^ state.v2 ^ state.v3
+     }
+ }
+ 
+ impl<S: Sip> Clone for Hasher<S> {
+     #[inline]
+     fn clone(&self) -> Hasher<S> {
+         Hasher {
+             k0: self.k0,
+             k1: self.k1,
+             length: self.length,
+             state: self.state,
+             tail: self.tail,
+             ntail: self.ntail,
+             _marker: self._marker,
+         }
+     }
+ }
+ 
+ impl<S: Sip> Default for Hasher<S> {
+     /// Creates a `Hasher<S>` with the two initial keys set to 0.
+     #[inline]
+     fn default() -> Hasher<S> {
+         Hasher::new_with_keys(0, 0)
+     }
+ }
+ 
+ #[doc(hidden)]
+ trait Sip {
+     fn c_rounds(_: &mut State);
+     fn d_rounds(_: &mut State);
+ }
+ 
+ #[derive(Debug, Clone, Default)]
+ struct Sip13Rounds;
+ 
+ impl Sip for Sip13Rounds {
+     #[inline]
+     fn c_rounds(state: &mut State) {
+         compress!(state);
+     }
+ 
+     #[inline]
+     fn d_rounds(state: &mut State) {
+         compress!(state);
+         compress!(state);
+         compress!(state);
+     }
+ }
+ 
+ #[derive(Debug, Clone, Default)]
+ struct Sip24Rounds;
+ 
+ impl Sip for Sip24Rounds {
+     #[inline]
+     fn c_rounds(state: &mut State) {
+         compress!(state);
+         compress!(state);
+     }
+ 
+     #[inline]
+     fn d_rounds(state: &mut State) {
+         compress!(state);
+         compress!(state);
+         compress!(state);
+         compress!(state);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/hint.rs gcc-16-20251102/libgrust/rustc-lib/core/src/hint.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/hint.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/hint.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,174 ----
+ #![stable(feature = "core_hint", since = "1.27.0")]
+ 
+ //! Hints to compiler that affects how code should be emitted or optimized.
+ //! Hints may be compile time or runtime.
+ 
+ use crate::intrinsics;
+ 
+ /// Informs the compiler that this point in the code is not reachable, enabling
+ /// further optimizations.
+ ///
+ /// # Safety
+ ///
+ /// Reaching this function is completely *undefined behavior* (UB). In
+ /// particular, the compiler assumes that all UB must never happen, and
+ /// therefore will eliminate all branches that reach to a call to
+ /// `unreachable_unchecked()`.
+ ///
+ /// Like all instances of UB, if this assumption turns out to be wrong, i.e., the
+ /// `unreachable_unchecked()` call is actually reachable among all possible
+ /// control flow, the compiler will apply the wrong optimization strategy, and
+ /// may sometimes even corrupt seemingly unrelated code, causing
+ /// difficult-to-debug problems.
+ ///
+ /// Use this function only when you can prove that the code will never call it.
+ /// Otherwise, consider using the [`unreachable!`] macro, which does not allow
+ /// optimizations but will panic when executed.
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// fn div_1(a: u32, b: u32) -> u32 {
+ ///     use std::hint::unreachable_unchecked;
+ ///
+ ///     // `b.saturating_add(1)` is always positive (not zero),
+ ///     // hence `checked_div` will never return `None`.
+ ///     // Therefore, the else branch is unreachable.
+ ///     a.checked_div(b.saturating_add(1))
+ ///         .unwrap_or_else(|| unsafe { unreachable_unchecked() })
+ /// }
+ ///
+ /// assert_eq!(div_1(7, 0), 7);
+ /// assert_eq!(div_1(9, 1), 4);
+ /// assert_eq!(div_1(11, u32::MAX), 0);
+ /// ```
+ #[inline]
+ #[stable(feature = "unreachable", since = "1.27.0")]
+ #[rustc_const_unstable(feature = "const_unreachable_unchecked", issue = "53188")]
+ pub const unsafe fn unreachable_unchecked() -> ! {
+     // SAFETY: the safety contract for `intrinsics::unreachable` must
+     // be upheld by the caller.
+     unsafe { intrinsics::unreachable() }
+ }
+ 
+ /// Emits a machine instruction to signal the processor that it is running in
+ /// a busy-wait spin-loop ("spin lock").
+ ///
+ /// Upon receiving the spin-loop signal the processor can optimize its behavior by,
+ /// for example, saving power or switching hyper-threads.
+ ///
+ /// This function is different from [`thread::yield_now`] which directly
+ /// yields to the system's scheduler, whereas `spin_loop` does not interact
+ /// with the operating system.
+ ///
+ /// A common use case for `spin_loop` is implementing bounded optimistic
+ /// spinning in a CAS loop in synchronization primitives. To avoid problems
+ /// like priority inversion, it is strongly recommended that the spin loop is
+ /// terminated after a finite amount of iterations and an appropriate blocking
+ /// syscall is made.
+ ///
+ /// **Note**: On platforms that do not support receiving spin-loop hints this
+ /// function does not do anything at all.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::sync::atomic::{AtomicBool, Ordering};
+ /// use std::sync::Arc;
+ /// use std::{hint, thread};
+ ///
+ /// // A shared atomic value that threads will use to coordinate
+ /// let live = Arc::new(AtomicBool::new(false));
+ ///
+ /// // In a background thread we'll eventually set the value
+ /// let bg_work = {
+ ///     let live = live.clone();
+ ///     thread::spawn(move || {
+ ///         // Do some work, then make the value live
+ ///         do_some_work();
+ ///         live.store(true, Ordering::Release);
+ ///     })
+ /// };
+ ///
+ /// // Back on our current thread, we wait for the value to be set
+ /// while live.load(Ordering::Acquire) {
+ ///     // The spin loop is a hint to the CPU that we're waiting, but probably
+ ///     // not for very long
+ ///     hint::spin_loop();
+ /// }
+ ///
+ /// // The value is now set
+ /// # fn do_some_work() {}
+ /// do_some_work();
+ /// bg_work.join()?;
+ /// # Ok::<(), Box<dyn core::any::Any + Send + 'static>>(())
+ /// ```
+ ///
+ /// [`thread::yield_now`]: ../../std/thread/fn.yield_now.html
+ #[inline]
+ #[stable(feature = "renamed_spin_loop", since = "1.49.0")]
+ pub fn spin_loop() {
+     #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"), target_feature = "sse2"))]
+     {
+         #[cfg(target_arch = "x86")]
+         {
+             // SAFETY: the `cfg` attr ensures that we only execute this on x86 targets.
+             unsafe { crate::arch::x86::_mm_pause() };
+         }
+ 
+         #[cfg(target_arch = "x86_64")]
+         {
+             // SAFETY: the `cfg` attr ensures that we only execute this on x86_64 targets.
+             unsafe { crate::arch::x86_64::_mm_pause() };
+         }
+     }
+ 
+     #[cfg(any(target_arch = "aarch64", all(target_arch = "arm", target_feature = "v6")))]
+     {
+         #[cfg(target_arch = "aarch64")]
+         {
+             // SAFETY: the `cfg` attr ensures that we only execute this on aarch64 targets.
+             unsafe { crate::arch::aarch64::__yield() };
+         }
+         #[cfg(target_arch = "arm")]
+         {
+             // SAFETY: the `cfg` attr ensures that we only execute this on arm targets
+             // with support for the v6 feature.
+             unsafe { crate::arch::arm::__yield() };
+         }
+     }
+ }
+ 
+ /// An identity function that *__hints__* to the compiler to be maximally pessimistic about what
+ /// `black_box` could do.
+ ///
+ /// Unlike [`std::convert::identity`], a Rust compiler is encouraged to assume that `black_box` can
+ /// use `dummy` in any possible valid way that Rust code is allowed to without introducing undefined
+ /// behavior in the calling code. This property makes `black_box` useful for writing code in which
+ /// certain optimizations are not desired, such as benchmarks.
+ ///
+ /// Note however, that `black_box` is only (and can only be) provided on a "best-effort" basis. The
+ /// extent to which it can block optimisations may vary depending upon the platform and code-gen
+ /// backend used. Programs cannot rely on `black_box` for *correctness* in any way.
+ ///
+ /// [`std::convert::identity`]: crate::convert::identity
+ #[cfg_attr(not(miri), inline)]
+ #[cfg_attr(miri, inline(never))]
+ #[unstable(feature = "test", issue = "50297")]
+ #[cfg_attr(miri, allow(unused_mut))]
+ pub fn black_box<T>(mut dummy: T) -> T {
+     // We need to "use" the argument in some way LLVM can't introspect, and on
+     // targets that support it we can typically leverage inline assembly to do
+     // this. LLVM's interpretation of inline assembly is that it's, well, a black
+     // box. This isn't the greatest implementation since it probably deoptimizes
+     // more than we want, but it's so far good enough.
+ 
+     #[cfg(not(miri))] // This is just a hint, so it is fine to skip in Miri.
+     // SAFETY: the inline assembly is a no-op.
+     unsafe {
+         // FIXME: Cannot use `asm!` because it doesn't support MIPS and other architectures.
+         llvm_asm!("" : : "r"(&mut dummy) : "memory" : "volatile");
+     }
+ 
+     dummy
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/internal_macros.rs gcc-16-20251102/libgrust/rustc-lib/core/src/internal_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/internal_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/internal_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,119 ----
+ // implements the unary operator "op &T"
+ // based on "op T" where T is expected to be `Copy`able
+ macro_rules! forward_ref_unop {
+     (impl $imp:ident, $method:ident for $t:ty) => {
+         forward_ref_unop!(impl $imp, $method for $t,
+                 #[stable(feature = "rust1", since = "1.0.0")]);
+     };
+     (impl $imp:ident, $method:ident for $t:ty, #[$attr:meta]) => {
+         #[$attr]
+         impl $imp for &$t {
+             type Output = <$t as $imp>::Output;
+ 
+             #[inline]
+             fn $method(self) -> <$t as $imp>::Output {
+                 $imp::$method(*self)
+             }
+         }
+     }
+ }
+ 
+ // implements binary operators "&T op U", "T op &U", "&T op &U"
+ // based on "T op U" where T and U are expected to be `Copy`able
+ macro_rules! forward_ref_binop {
+     (impl $imp:ident, $method:ident for $t:ty, $u:ty) => {
+         forward_ref_binop!(impl $imp, $method for $t, $u,
+                 #[stable(feature = "rust1", since = "1.0.0")]);
+     };
+     (impl $imp:ident, $method:ident for $t:ty, $u:ty, #[$attr:meta]) => {
+         #[$attr]
+         impl<'a> $imp<$u> for &'a $t {
+             type Output = <$t as $imp<$u>>::Output;
+ 
+             #[inline]
+             fn $method(self, other: $u) -> <$t as $imp<$u>>::Output {
+                 $imp::$method(*self, other)
+             }
+         }
+ 
+         #[$attr]
+         impl $imp<&$u> for $t {
+             type Output = <$t as $imp<$u>>::Output;
+ 
+             #[inline]
+             fn $method(self, other: &$u) -> <$t as $imp<$u>>::Output {
+                 $imp::$method(self, *other)
+             }
+         }
+ 
+         #[$attr]
+         impl $imp<&$u> for &$t {
+             type Output = <$t as $imp<$u>>::Output;
+ 
+             #[inline]
+             fn $method(self, other: &$u) -> <$t as $imp<$u>>::Output {
+                 $imp::$method(*self, *other)
+             }
+         }
+     }
+ }
+ 
+ // implements "T op= &U", based on "T op= U"
+ // where U is expected to be `Copy`able
+ macro_rules! forward_ref_op_assign {
+     (impl $imp:ident, $method:ident for $t:ty, $u:ty) => {
+         forward_ref_op_assign!(impl $imp, $method for $t, $u,
+                 #[stable(feature = "op_assign_builtins_by_ref", since = "1.22.0")]);
+     };
+     (impl $imp:ident, $method:ident for $t:ty, $u:ty, #[$attr:meta]) => {
+         #[$attr]
+         impl $imp<&$u> for $t {
+             #[inline]
+             fn $method(&mut self, other: &$u) {
+                 $imp::$method(self, *other);
+             }
+         }
+     }
+ }
+ 
+ /// Create a zero-size type similar to a closure type, but named.
+ #[unstable(feature = "std_internals", issue = "none")]
+ macro_rules! impl_fn_for_zst {
+     ($(
+         $( #[$attr: meta] )*
+         struct $Name: ident impl$( <$( $lifetime : lifetime ),+> )? Fn =
+             |$( $arg: ident: $ArgTy: ty ),*| -> $ReturnTy: ty
+             $body: block;
+     )+) => {
+         $(
+             $( #[$attr] )*
+             struct $Name;
+ 
+             impl $( <$( $lifetime ),+> )? Fn<($( $ArgTy, )*)> for $Name {
+                 #[inline]
+                 extern "rust-call" fn call(&self, ($( $arg, )*): ($( $ArgTy, )*)) -> $ReturnTy {
+                     $body
+                 }
+             }
+ 
+             impl $( <$( $lifetime ),+> )? FnMut<($( $ArgTy, )*)> for $Name {
+                 #[inline]
+                 extern "rust-call" fn call_mut(
+                     &mut self,
+                     ($( $arg, )*): ($( $ArgTy, )*)
+                 ) -> $ReturnTy {
+                     Fn::call(&*self, ($( $arg, )*))
+                 }
+             }
+ 
+             impl $( <$( $lifetime ),+> )? FnOnce<($( $ArgTy, )*)> for $Name {
+                 type Output = $ReturnTy;
+ 
+                 #[inline]
+                 extern "rust-call" fn call_once(self, ($( $arg, )*): ($( $ArgTy, )*)) -> $ReturnTy {
+                     Fn::call(&self, ($( $arg, )*))
+                 }
+             }
+         )+
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/intrinsics.rs gcc-16-20251102/libgrust/rustc-lib/core/src/intrinsics.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/intrinsics.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/intrinsics.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2023 ----
+ //! Compiler intrinsics.
+ //!
+ //! The corresponding definitions are in `compiler/rustc_codegen_llvm/src/intrinsic.rs`.
+ //! The corresponding const implementations are in `compiler/rustc_mir/src/interpret/intrinsics.rs`
+ //!
+ //! # Const intrinsics
+ //!
+ //! Note: any changes to the constness of intrinsics should be discussed with the language team.
+ //! This includes changes in the stability of the constness.
+ //!
+ //! In order to make an intrinsic usable at compile-time, one needs to copy the implementation
+ //! from <https://github.com/rust-lang/miri/blob/master/src/shims/intrinsics.rs> to
+ //! `compiler/rustc_mir/src/interpret/intrinsics.rs` and add a
+ //! `#[rustc_const_unstable(feature = "foo", issue = "01234")]` to the intrinsic.
+ //!
+ //! If an intrinsic is supposed to be used from a `const fn` with a `rustc_const_stable` attribute,
+ //! the intrinsic's attribute must be `rustc_const_stable`, too. Such a change should not be done
+ //! without T-lang consultation, because it bakes a feature into the language that cannot be
+ //! replicated in user code without compiler support.
+ //!
+ //! # Volatiles
+ //!
+ //! The volatile intrinsics provide operations intended to act on I/O
+ //! memory, which are guaranteed to not be reordered by the compiler
+ //! across other volatile intrinsics. See the LLVM documentation on
+ //! [[volatile]].
+ //!
+ //! [volatile]: http://llvm.org/docs/LangRef.html#volatile-memory-accesses
+ //!
+ //! # Atomics
+ //!
+ //! The atomic intrinsics provide common atomic operations on machine
+ //! words, with multiple possible memory orderings. They obey the same
+ //! semantics as C++11. See the LLVM documentation on [[atomics]].
+ //!
+ //! [atomics]: http://llvm.org/docs/Atomics.html
+ //!
+ //! A quick refresher on memory ordering:
+ //!
+ //! * Acquire - a barrier for acquiring a lock. Subsequent reads and writes
+ //!   take place after the barrier.
+ //! * Release - a barrier for releasing a lock. Preceding reads and writes
+ //!   take place before the barrier.
+ //! * Sequentially consistent - sequentially consistent operations are
+ //!   guaranteed to happen in order. This is the standard mode for working
+ //!   with atomic types and is equivalent to Java's `volatile`.
+ 
+ #![unstable(
+     feature = "core_intrinsics",
+     reason = "intrinsics are unlikely to ever be stabilized, instead \
+                       they should be used through stabilized interfaces \
+                       in the rest of the standard library",
+     issue = "none"
+ )]
+ #![allow(missing_docs)]
+ 
+ use crate::marker::DiscriminantKind;
+ use crate::mem;
+ 
+ // These imports are used for simplifying intra-doc links
+ #[allow(unused_imports)]
+ #[cfg(all(target_has_atomic = "8", target_has_atomic = "32", target_has_atomic = "ptr"))]
+ use crate::sync::atomic::{self, AtomicBool, AtomicI32, AtomicIsize, AtomicU32, Ordering};
+ 
+ #[stable(feature = "drop_in_place", since = "1.8.0")]
+ #[rustc_deprecated(
+     reason = "no longer an intrinsic - use `ptr::drop_in_place` directly",
+     since = "1.18.0"
+ )]
+ pub use crate::ptr::drop_in_place;
+ 
+ extern "rust-intrinsic" {
+     // N.B., these intrinsics take raw pointers because they mutate aliased
+     // memory, which is not valid for either `&` or `&mut`.
+ 
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::SeqCst`] as both the `success` and `failure` parameters.
+     /// For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::Acquire`] as both the `success` and `failure` parameters.
+     /// For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_acq<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::Release`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_rel<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::AcqRel`] as the `success` and [`Ordering::Acquire`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_acqrel<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::Relaxed`] as both the `success` and `failure` parameters.
+     /// For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_relaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::SeqCst`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_failrelaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::SeqCst`] as the `success` and [`Ordering::Acquire`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_failacq<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::Acquire`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_acq_failrelaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange` method by passing
+     /// [`Ordering::AcqRel`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange`].
+     pub fn atomic_cxchg_acqrel_failrelaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+ 
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::SeqCst`] as both the `success` and `failure` parameters.
+     /// For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::Acquire`] as both the `success` and `failure` parameters.
+     /// For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_acq<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::Release`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_rel<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::AcqRel`] as the `success` and [`Ordering::Acquire`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_acqrel<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::Relaxed`] as both the `success` and `failure` parameters.
+     /// For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_relaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::SeqCst`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_failrelaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::SeqCst`] as the `success` and [`Ordering::Acquire`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_failacq<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::Acquire`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_acq_failrelaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+     /// Stores a value if the current value is the same as the `old` value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `compare_exchange_weak` method by passing
+     /// [`Ordering::AcqRel`] as the `success` and [`Ordering::Relaxed`] as the
+     /// `failure` parameters. For example, [`AtomicBool::compare_exchange_weak`].
+     pub fn atomic_cxchgweak_acqrel_failrelaxed<T: Copy>(dst: *mut T, old: T, src: T) -> (T, bool);
+ 
+     /// Loads the current value of the pointer.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `load` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::load`].
+     pub fn atomic_load<T: Copy>(src: *const T) -> T;
+     /// Loads the current value of the pointer.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `load` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicBool::load`].
+     pub fn atomic_load_acq<T: Copy>(src: *const T) -> T;
+     /// Loads the current value of the pointer.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `load` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::load`].
+     pub fn atomic_load_relaxed<T: Copy>(src: *const T) -> T;
+     pub fn atomic_load_unordered<T: Copy>(src: *const T) -> T;
+ 
+     /// Stores the value at the specified memory location.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `store` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::store`].
+     pub fn atomic_store<T: Copy>(dst: *mut T, val: T);
+     /// Stores the value at the specified memory location.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `store` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicBool::store`].
+     pub fn atomic_store_rel<T: Copy>(dst: *mut T, val: T);
+     /// Stores the value at the specified memory location.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `store` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::store`].
+     pub fn atomic_store_relaxed<T: Copy>(dst: *mut T, val: T);
+     pub fn atomic_store_unordered<T: Copy>(dst: *mut T, val: T);
+ 
+     /// Stores the value at the specified memory location, returning the old value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `swap` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::swap`].
+     pub fn atomic_xchg<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Stores the value at the specified memory location, returning the old value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `swap` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicBool::swap`].
+     pub fn atomic_xchg_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Stores the value at the specified memory location, returning the old value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `swap` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicBool::swap`].
+     pub fn atomic_xchg_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Stores the value at the specified memory location, returning the old value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `swap` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicBool::swap`].
+     pub fn atomic_xchg_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Stores the value at the specified memory location, returning the old value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `swap` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::swap`].
+     pub fn atomic_xchg_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Adds to the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_add` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicIsize::fetch_add`].
+     pub fn atomic_xadd<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Adds to the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_add` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicIsize::fetch_add`].
+     pub fn atomic_xadd_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Adds to the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_add` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicIsize::fetch_add`].
+     pub fn atomic_xadd_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Adds to the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_add` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicIsize::fetch_add`].
+     pub fn atomic_xadd_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Adds to the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_add` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicIsize::fetch_add`].
+     pub fn atomic_xadd_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Subtract from the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_sub` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicIsize::fetch_sub`].
+     pub fn atomic_xsub<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Subtract from the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_sub` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicIsize::fetch_sub`].
+     pub fn atomic_xsub_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Subtract from the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_sub` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicIsize::fetch_sub`].
+     pub fn atomic_xsub_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Subtract from the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_sub` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicIsize::fetch_sub`].
+     pub fn atomic_xsub_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Subtract from the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_sub` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicIsize::fetch_sub`].
+     pub fn atomic_xsub_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Bitwise and with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_and` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::fetch_and`].
+     pub fn atomic_and<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise and with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_and` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicBool::fetch_and`].
+     pub fn atomic_and_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise and with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_and` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicBool::fetch_and`].
+     pub fn atomic_and_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise and with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_and` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicBool::fetch_and`].
+     pub fn atomic_and_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise and with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_and` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::fetch_and`].
+     pub fn atomic_and_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Bitwise nand with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`AtomicBool`] type via the `fetch_nand` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::fetch_nand`].
+     pub fn atomic_nand<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise nand with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`AtomicBool`] type via the `fetch_nand` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicBool::fetch_nand`].
+     pub fn atomic_nand_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise nand with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`AtomicBool`] type via the `fetch_nand` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicBool::fetch_nand`].
+     pub fn atomic_nand_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise nand with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`AtomicBool`] type via the `fetch_nand` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicBool::fetch_nand`].
+     pub fn atomic_nand_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise nand with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`AtomicBool`] type via the `fetch_nand` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::fetch_nand`].
+     pub fn atomic_nand_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Bitwise or with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_or` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::fetch_or`].
+     pub fn atomic_or<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise or with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_or` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicBool::fetch_or`].
+     pub fn atomic_or_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise or with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_or` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicBool::fetch_or`].
+     pub fn atomic_or_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise or with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_or` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicBool::fetch_or`].
+     pub fn atomic_or_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise or with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_or` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::fetch_or`].
+     pub fn atomic_or_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Bitwise xor with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_xor` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicBool::fetch_xor`].
+     pub fn atomic_xor<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise xor with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_xor` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicBool::fetch_xor`].
+     pub fn atomic_xor_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise xor with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_xor` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicBool::fetch_xor`].
+     pub fn atomic_xor_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise xor with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_xor` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicBool::fetch_xor`].
+     pub fn atomic_xor_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Bitwise xor with the current value, returning the previous value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] types via the `fetch_xor` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicBool::fetch_xor`].
+     pub fn atomic_xor_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Maximum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_max` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicI32::fetch_max`].
+     pub fn atomic_max<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_max` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicI32::fetch_max`].
+     pub fn atomic_max_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_max` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicI32::fetch_max`].
+     pub fn atomic_max_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_max` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicI32::fetch_max`].
+     pub fn atomic_max_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_max` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicI32::fetch_max`].
+     pub fn atomic_max_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Minimum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_min` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicI32::fetch_min`].
+     pub fn atomic_min<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_min` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicI32::fetch_min`].
+     pub fn atomic_min_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_min` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicI32::fetch_min`].
+     pub fn atomic_min_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_min` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicI32::fetch_min`].
+     pub fn atomic_min_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using a signed comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] signed integer types via the `fetch_min` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicI32::fetch_min`].
+     pub fn atomic_min_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Minimum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_min` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicU32::fetch_min`].
+     pub fn atomic_umin<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_min` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicU32::fetch_min`].
+     pub fn atomic_umin_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_min` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicU32::fetch_min`].
+     pub fn atomic_umin_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_min` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicU32::fetch_min`].
+     pub fn atomic_umin_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Minimum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_min` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicU32::fetch_min`].
+     pub fn atomic_umin_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// Maximum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_max` method by passing
+     /// [`Ordering::SeqCst`] as the `order`. For example, [`AtomicU32::fetch_max`].
+     pub fn atomic_umax<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_max` method by passing
+     /// [`Ordering::Acquire`] as the `order`. For example, [`AtomicU32::fetch_max`].
+     pub fn atomic_umax_acq<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_max` method by passing
+     /// [`Ordering::Release`] as the `order`. For example, [`AtomicU32::fetch_max`].
+     pub fn atomic_umax_rel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_max` method by passing
+     /// [`Ordering::AcqRel`] as the `order`. For example, [`AtomicU32::fetch_max`].
+     pub fn atomic_umax_acqrel<T: Copy>(dst: *mut T, src: T) -> T;
+     /// Maximum with the current value using an unsigned comparison.
+     ///
+     /// The stabilized version of this intrinsic is available on the
+     /// [`atomic`] unsigned integer types via the `fetch_max` method by passing
+     /// [`Ordering::Relaxed`] as the `order`. For example, [`AtomicU32::fetch_max`].
+     pub fn atomic_umax_relaxed<T: Copy>(dst: *mut T, src: T) -> T;
+ 
+     /// The `prefetch` intrinsic is a hint to the code generator to insert a prefetch instruction
+     /// if supported; otherwise, it is a no-op.
+     /// Prefetches have no effect on the behavior of the program but can change its performance
+     /// characteristics.
+     ///
+     /// The `locality` argument must be a constant integer and is a temporal locality specifier
+     /// ranging from (0) - no locality, to (3) - extremely local keep in cache.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn prefetch_read_data<T>(data: *const T, locality: i32);
+     /// The `prefetch` intrinsic is a hint to the code generator to insert a prefetch instruction
+     /// if supported; otherwise, it is a no-op.
+     /// Prefetches have no effect on the behavior of the program but can change its performance
+     /// characteristics.
+     ///
+     /// The `locality` argument must be a constant integer and is a temporal locality specifier
+     /// ranging from (0) - no locality, to (3) - extremely local keep in cache.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn prefetch_write_data<T>(data: *const T, locality: i32);
+     /// The `prefetch` intrinsic is a hint to the code generator to insert a prefetch instruction
+     /// if supported; otherwise, it is a no-op.
+     /// Prefetches have no effect on the behavior of the program but can change its performance
+     /// characteristics.
+     ///
+     /// The `locality` argument must be a constant integer and is a temporal locality specifier
+     /// ranging from (0) - no locality, to (3) - extremely local keep in cache.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn prefetch_read_instruction<T>(data: *const T, locality: i32);
+     /// The `prefetch` intrinsic is a hint to the code generator to insert a prefetch instruction
+     /// if supported; otherwise, it is a no-op.
+     /// Prefetches have no effect on the behavior of the program but can change its performance
+     /// characteristics.
+     ///
+     /// The `locality` argument must be a constant integer and is a temporal locality specifier
+     /// ranging from (0) - no locality, to (3) - extremely local keep in cache.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn prefetch_write_instruction<T>(data: *const T, locality: i32);
+ }
+ 
+ extern "rust-intrinsic" {
+     /// An atomic fence.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::fence`] by passing [`Ordering::SeqCst`]
+     /// as the `order`.
+     pub fn atomic_fence();
+     /// An atomic fence.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::fence`] by passing [`Ordering::Acquire`]
+     /// as the `order`.
+     pub fn atomic_fence_acq();
+     /// An atomic fence.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::fence`] by passing [`Ordering::Release`]
+     /// as the `order`.
+     pub fn atomic_fence_rel();
+     /// An atomic fence.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::fence`] by passing [`Ordering::AcqRel`]
+     /// as the `order`.
+     pub fn atomic_fence_acqrel();
+ 
+     /// A compiler-only memory barrier.
+     ///
+     /// Memory accesses will never be reordered across this barrier by the
+     /// compiler, but no instructions will be emitted for it. This is
+     /// appropriate for operations on the same thread that may be preempted,
+     /// such as when interacting with signal handlers.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::compiler_fence`] by passing [`Ordering::SeqCst`]
+     /// as the `order`.
+     pub fn atomic_singlethreadfence();
+     /// A compiler-only memory barrier.
+     ///
+     /// Memory accesses will never be reordered across this barrier by the
+     /// compiler, but no instructions will be emitted for it. This is
+     /// appropriate for operations on the same thread that may be preempted,
+     /// such as when interacting with signal handlers.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::compiler_fence`] by passing [`Ordering::Acquire`]
+     /// as the `order`.
+     pub fn atomic_singlethreadfence_acq();
+     /// A compiler-only memory barrier.
+     ///
+     /// Memory accesses will never be reordered across this barrier by the
+     /// compiler, but no instructions will be emitted for it. This is
+     /// appropriate for operations on the same thread that may be preempted,
+     /// such as when interacting with signal handlers.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::compiler_fence`] by passing [`Ordering::Release`]
+     /// as the `order`.
+     pub fn atomic_singlethreadfence_rel();
+     /// A compiler-only memory barrier.
+     ///
+     /// Memory accesses will never be reordered across this barrier by the
+     /// compiler, but no instructions will be emitted for it. This is
+     /// appropriate for operations on the same thread that may be preempted,
+     /// such as when interacting with signal handlers.
+     ///
+     /// The stabilized version of this intrinsic is available in
+     /// [`atomic::compiler_fence`] by passing [`Ordering::AcqRel`]
+     /// as the `order`.
+     pub fn atomic_singlethreadfence_acqrel();
+ 
+     /// Magic intrinsic that derives its meaning from attributes
+     /// attached to the function.
+     ///
+     /// For example, dataflow uses this to inject static assertions so
+     /// that `rustc_peek(potentially_uninitialized)` would actually
+     /// double-check that dataflow did indeed compute that it is
+     /// uninitialized at that point in the control flow.
+     ///
+     /// This intrinsic should not be used outside of the compiler.
+     pub fn rustc_peek<T>(_: T) -> T;
+ 
+     /// Aborts the execution of the process.
+     ///
+     /// A more user-friendly and stable version of this operation is
+     /// [`std::process::abort`](../../std/process/fn.abort.html).
+     pub fn abort() -> !;
+ 
+     /// Tells LLVM that this point in the code is not reachable, enabling
+     /// further optimizations.
+     ///
+     /// N.B., this is very different from the `unreachable!()` macro: Unlike the
+     /// macro, which panics when it is executed, it is *undefined behavior* to
+     /// reach code marked with this function.
+     ///
+     /// The stabilized version of this intrinsic is [`core::hint::unreachable_unchecked`](crate::hint::unreachable_unchecked).
+     #[rustc_const_unstable(feature = "const_unreachable_unchecked", issue = "53188")]
+     pub fn unreachable() -> !;
+ 
+     /// Informs the optimizer that a condition is always true.
+     /// If the condition is false, the behavior is undefined.
+     ///
+     /// No code is generated for this intrinsic, but the optimizer will try
+     /// to preserve it (and its condition) between passes, which may interfere
+     /// with optimization of surrounding code and reduce performance. It should
+     /// not be used if the invariant can be discovered by the optimizer on its
+     /// own, or if it does not enable any significant optimizations.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_assume", issue = "76972")]
+     pub fn assume(b: bool);
+ 
+     /// Hints to the compiler that branch condition is likely to be true.
+     /// Returns the value passed to it.
+     ///
+     /// Any use other than with `if` statements will probably not have an effect.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_likely", issue = "none")]
+     pub fn likely(b: bool) -> bool;
+ 
+     /// Hints to the compiler that branch condition is likely to be false.
+     /// Returns the value passed to it.
+     ///
+     /// Any use other than with `if` statements will probably not have an effect.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_likely", issue = "none")]
+     pub fn unlikely(b: bool) -> bool;
+ 
+     /// Executes a breakpoint trap, for inspection by a debugger.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn breakpoint();
+ 
+     /// The size of a type in bytes.
+     ///
+     /// More specifically, this is the offset in bytes between successive
+     /// items of the same type, including alignment padding.
+     ///
+     /// The stabilized version of this intrinsic is [`core::mem::size_of`](crate::mem::size_of).
+     #[rustc_const_stable(feature = "const_size_of", since = "1.40.0")]
+     pub fn size_of<T>() -> usize;
+ 
+     /// Moves a value to an uninitialized memory location.
+     ///
+     /// Drop glue is not run on the destination.
+     ///
+     /// The stabilized version of this intrinsic is [`core::ptr::write`](crate::ptr::write).
+     pub fn move_val_init<T>(dst: *mut T, src: T);
+ 
+     /// The minimum alignment of a type.
+     ///
+     /// The stabilized version of this intrinsic is [`core::mem::align_of`](crate::mem::align_of).
+     #[rustc_const_stable(feature = "const_min_align_of", since = "1.40.0")]
+     pub fn min_align_of<T>() -> usize;
+     /// The preferred alignment of a type.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_pref_align_of", issue = "none")]
+     pub fn pref_align_of<T>() -> usize;
+ 
+     /// The size of the referenced value in bytes.
+     ///
+     /// The stabilized version of this intrinsic is [`mem::size_of_val`].
+     #[rustc_const_unstable(feature = "const_size_of_val", issue = "46571")]
+     pub fn size_of_val<T: ?Sized>(_: *const T) -> usize;
+     /// The required alignment of the referenced value.
+     ///
+     /// The stabilized version of this intrinsic is [`core::mem::align_of_val`](crate::mem::align_of_val).
+     #[rustc_const_unstable(feature = "const_align_of_val", issue = "46571")]
+     pub fn min_align_of_val<T: ?Sized>(_: *const T) -> usize;
+ 
+     /// Gets a static string slice containing the name of a type.
+     ///
+     /// The stabilized version of this intrinsic is [`core::any::type_name`](crate::any::type_name).
+     #[rustc_const_unstable(feature = "const_type_name", issue = "63084")]
+     pub fn type_name<T: ?Sized>() -> &'static str;
+ 
+     /// Gets an identifier which is globally unique to the specified type. This
+     /// function will return the same value for a type regardless of whichever
+     /// crate it is invoked in.
+     ///
+     /// The stabilized version of this intrinsic is [`core::any::TypeId::of`](crate::any::TypeId::of).
+     #[rustc_const_unstable(feature = "const_type_id", issue = "77125")]
+     pub fn type_id<T: ?Sized + 'static>() -> u64;
+ 
+     /// A guard for unsafe functions that cannot ever be executed if `T` is uninhabited:
+     /// This will statically either panic, or do nothing.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn assert_inhabited<T>();
+ 
+     /// A guard for unsafe functions that cannot ever be executed if `T` does not permit
+     /// zero-initialization: This will statically either panic, or do nothing.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn assert_zero_valid<T>();
+ 
+     /// A guard for unsafe functions that cannot ever be executed if `T` has invalid
+     /// bit patterns: This will statically either panic, or do nothing.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn assert_uninit_valid<T>();
+ 
+     /// Gets a reference to a static `Location` indicating where it was called.
+     ///
+     /// Consider using [`core::panic::Location::caller`](crate::panic::Location::caller) instead.
+     #[rustc_const_unstable(feature = "const_caller_location", issue = "76156")]
+     pub fn caller_location() -> &'static crate::panic::Location<'static>;
+ 
+     /// Moves a value out of scope without running drop glue.
+     ///
+     /// This exists solely for [`mem::forget_unsized`]; normal `forget` uses
+     /// `ManuallyDrop` instead.
+     pub fn forget<T: ?Sized>(_: T);
+ 
+     /// Reinterprets the bits of a value of one type as another type.
+     ///
+     /// Both types must have the same size. Neither the original, nor the result,
+     /// may be an [invalid value](../../nomicon/what-unsafe-does.html).
+     ///
+     /// `transmute` is semantically equivalent to a bitwise move of one type
+     /// into another. It copies the bits from the source value into the
+     /// destination value, then forgets the original. It's equivalent to C's
+     /// `memcpy` under the hood, just like `transmute_copy`.
+     ///
+     /// `transmute` is **incredibly** unsafe. There are a vast number of ways to
+     /// cause [undefined behavior][ub] with this function. `transmute` should be
+     /// the absolute last resort.
+     ///
+     /// The [nomicon](../../nomicon/transmutes.html) has additional
+     /// documentation.
+     ///
+     /// [ub]: ../../reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// There are a few things that `transmute` is really useful for.
+     ///
+     /// Turning a pointer into a function pointer. This is *not* portable to
+     /// machines where function pointers and data pointers have different sizes.
+     ///
+     /// ```
+     /// fn foo() -> i32 {
+     ///     0
+     /// }
+     /// let pointer = foo as *const ();
+     /// let function = unsafe {
+     ///     std::mem::transmute::<*const (), fn() -> i32>(pointer)
+     /// };
+     /// assert_eq!(function(), 0);
+     /// ```
+     ///
+     /// Extending a lifetime, or shortening an invariant lifetime. This is
+     /// advanced, very unsafe Rust!
+     ///
+     /// ```
+     /// struct R<'a>(&'a i32);
+     /// unsafe fn extend_lifetime<'b>(r: R<'b>) -> R<'static> {
+     ///     std::mem::transmute::<R<'b>, R<'static>>(r)
+     /// }
+     ///
+     /// unsafe fn shorten_invariant_lifetime<'b, 'c>(r: &'b mut R<'static>)
+     ///                                              -> &'b mut R<'c> {
+     ///     std::mem::transmute::<&'b mut R<'static>, &'b mut R<'c>>(r)
+     /// }
+     /// ```
+     ///
+     /// # Alternatives
+     ///
+     /// Don't despair: many uses of `transmute` can be achieved through other means.
+     /// Below are common applications of `transmute` which can be replaced with safer
+     /// constructs.
+     ///
+     /// Turning raw bytes(`&[u8]`) to `u32`, `f64`, etc.:
+     ///
+     /// ```
+     /// let raw_bytes = [0x78, 0x56, 0x34, 0x12];
+     ///
+     /// let num = unsafe {
+     ///     std::mem::transmute::<[u8; 4], u32>(raw_bytes)
+     /// };
+     ///
+     /// // use `u32::from_ne_bytes` instead
+     /// let num = u32::from_ne_bytes(raw_bytes);
+     /// // or use `u32::from_le_bytes` or `u32::from_be_bytes` to specify the endianness
+     /// let num = u32::from_le_bytes(raw_bytes);
+     /// assert_eq!(num, 0x12345678);
+     /// let num = u32::from_be_bytes(raw_bytes);
+     /// assert_eq!(num, 0x78563412);
+     /// ```
+     ///
+     /// Turning a pointer into a `usize`:
+     ///
+     /// ```
+     /// let ptr = &0;
+     /// let ptr_num_transmute = unsafe {
+     ///     std::mem::transmute::<&i32, usize>(ptr)
+     /// };
+     ///
+     /// // Use an `as` cast instead
+     /// let ptr_num_cast = ptr as *const i32 as usize;
+     /// ```
+     ///
+     /// Turning a `*mut T` into an `&mut T`:
+     ///
+     /// ```
+     /// let ptr: *mut i32 = &mut 0;
+     /// let ref_transmuted = unsafe {
+     ///     std::mem::transmute::<*mut i32, &mut i32>(ptr)
+     /// };
+     ///
+     /// // Use a reborrow instead
+     /// let ref_casted = unsafe { &mut *ptr };
+     /// ```
+     ///
+     /// Turning an `&mut T` into an `&mut U`:
+     ///
+     /// ```
+     /// let ptr = &mut 0;
+     /// let val_transmuted = unsafe {
+     ///     std::mem::transmute::<&mut i32, &mut u32>(ptr)
+     /// };
+     ///
+     /// // Now, put together `as` and reborrowing - note the chaining of `as`
+     /// // `as` is not transitive
+     /// let val_casts = unsafe { &mut *(ptr as *mut i32 as *mut u32) };
+     /// ```
+     ///
+     /// Turning an `&str` into an `&[u8]`:
+     ///
+     /// ```
+     /// // this is not a good way to do this.
+     /// let slice = unsafe { std::mem::transmute::<&str, &[u8]>("Rust") };
+     /// assert_eq!(slice, &[82, 117, 115, 116]);
+     ///
+     /// // You could use `str::as_bytes`
+     /// let slice = "Rust".as_bytes();
+     /// assert_eq!(slice, &[82, 117, 115, 116]);
+     ///
+     /// // Or, just use a byte string, if you have control over the string
+     /// // literal
+     /// assert_eq!(b"Rust", &[82, 117, 115, 116]);
+     /// ```
+     ///
+     /// Turning a `Vec<&T>` into a `Vec<Option<&T>>`:
+     ///
+     /// ```
+     /// let store = [0, 1, 2, 3];
+     /// let v_orig = store.iter().collect::<Vec<&i32>>();
+     ///
+     /// // clone the vector as we will reuse them later
+     /// let v_clone = v_orig.clone();
+     ///
+     /// // Using transmute: this relies on the unspecified data layout of `Vec`, which is a
+     /// // bad idea and could cause Undefined Behavior.
+     /// // However, it is no-copy.
+     /// let v_transmuted = unsafe {
+     ///     std::mem::transmute::<Vec<&i32>, Vec<Option<&i32>>>(v_clone)
+     /// };
+     ///
+     /// let v_clone = v_orig.clone();
+     ///
+     /// // This is the suggested, safe way.
+     /// // It does copy the entire vector, though, into a new array.
+     /// let v_collected = v_clone.into_iter()
+     ///                          .map(Some)
+     ///                          .collect::<Vec<Option<&i32>>>();
+     ///
+     /// let v_clone = v_orig.clone();
+     ///
+     /// // The no-copy, unsafe way, still using transmute, but not relying on the data layout.
+     /// // Like the first approach, this reuses the `Vec` internals.
+     /// // Therefore, the new inner type must have the
+     /// // exact same size, *and the same alignment*, as the old type.
+     /// // The same caveats exist for this method as transmute, for
+     /// // the original inner type (`&i32`) to the converted inner type
+     /// // (`Option<&i32>`), so read the nomicon pages linked above and also
+     /// // consult the [`from_raw_parts`] documentation.
+     /// let v_from_raw = unsafe {
+     // FIXME Update this when vec_into_raw_parts is stabilized
+     ///     // Ensure the original vector is not dropped.
+     ///     let mut v_clone = std::mem::ManuallyDrop::new(v_clone);
+     ///     Vec::from_raw_parts(v_clone.as_mut_ptr() as *mut Option<&i32>,
+     ///                         v_clone.len(),
+     ///                         v_clone.capacity())
+     /// };
+     /// ```
+     ///
+     /// [`from_raw_parts`]: ../../std/vec/struct.Vec.html#method.from_raw_parts
+     ///
+     /// Implementing `split_at_mut`:
+     ///
+     /// ```
+     /// use std::{slice, mem};
+     ///
+     /// // There are multiple ways to do this, and there are multiple problems
+     /// // with the following (transmute) way.
+     /// fn split_at_mut_transmute<T>(slice: &mut [T], mid: usize)
+     ///                              -> (&mut [T], &mut [T]) {
+     ///     let len = slice.len();
+     ///     assert!(mid <= len);
+     ///     unsafe {
+     ///         let slice2 = mem::transmute::<&mut [T], &mut [T]>(slice);
+     ///         // first: transmute is not type safe; all it checks is that T and
+     ///         // U are of the same size. Second, right here, you have two
+     ///         // mutable references pointing to the same memory.
+     ///         (&mut slice[0..mid], &mut slice2[mid..len])
+     ///     }
+     /// }
+     ///
+     /// // This gets rid of the type safety problems; `&mut *` will *only* give
+     /// // you an `&mut T` from an `&mut T` or `*mut T`.
+     /// fn split_at_mut_casts<T>(slice: &mut [T], mid: usize)
+     ///                          -> (&mut [T], &mut [T]) {
+     ///     let len = slice.len();
+     ///     assert!(mid <= len);
+     ///     unsafe {
+     ///         let slice2 = &mut *(slice as *mut [T]);
+     ///         // however, you still have two mutable references pointing to
+     ///         // the same memory.
+     ///         (&mut slice[0..mid], &mut slice2[mid..len])
+     ///     }
+     /// }
+     ///
+     /// // This is how the standard library does it. This is the best method, if
+     /// // you need to do something like this
+     /// fn split_at_stdlib<T>(slice: &mut [T], mid: usize)
+     ///                       -> (&mut [T], &mut [T]) {
+     ///     let len = slice.len();
+     ///     assert!(mid <= len);
+     ///     unsafe {
+     ///         let ptr = slice.as_mut_ptr();
+     ///         // This now has three mutable references pointing at the same
+     ///         // memory. `slice`, the rvalue ret.0, and the rvalue ret.1.
+     ///         // `slice` is never used after `let ptr = ...`, and so one can
+     ///         // treat it as "dead", and therefore, you only have two real
+     ///         // mutable slices.
+     ///         (slice::from_raw_parts_mut(ptr, mid),
+     ///          slice::from_raw_parts_mut(ptr.add(mid), len - mid))
+     ///     }
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     // NOTE: While this makes the intrinsic const stable, we have some custom code in const fn
+     // checks that prevent its use within `const fn`.
+     #[rustc_const_stable(feature = "const_transmute", since = "1.46.0")]
+     #[rustc_diagnostic_item = "transmute"]
+     pub fn transmute<T, U>(e: T) -> U;
+ 
+     /// Returns `true` if the actual type given as `T` requires drop
+     /// glue; returns `false` if the actual type provided for `T`
+     /// implements `Copy`.
+     ///
+     /// If the actual type neither requires drop glue nor implements
+     /// `Copy`, then the return value of this function is unspecified.
+     ///
+     /// The stabilized version of this intrinsic is [`mem::needs_drop`](crate::mem::needs_drop).
+     #[rustc_const_stable(feature = "const_needs_drop", since = "1.40.0")]
+     pub fn needs_drop<T>() -> bool;
+ 
+     /// Calculates the offset from a pointer.
+     ///
+     /// This is implemented as an intrinsic to avoid converting to and from an
+     /// integer, since the conversion would throw away aliasing information.
+     ///
+     /// # Safety
+     ///
+     /// Both the starting and resulting pointer must be either in bounds or one
+     /// byte past the end of an allocated object. If either pointer is out of
+     /// bounds or arithmetic overflow occurs then any further use of the
+     /// returned value will result in undefined behavior.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::pointer::offset`](../../std/primitive.pointer.html#method.offset).
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     pub fn offset<T>(dst: *const T, offset: isize) -> *const T;
+ 
+     /// Calculates the offset from a pointer, potentially wrapping.
+     ///
+     /// This is implemented as an intrinsic to avoid converting to and from an
+     /// integer, since the conversion inhibits certain optimizations.
+     ///
+     /// # Safety
+     ///
+     /// Unlike the `offset` intrinsic, this intrinsic does not restrict the
+     /// resulting pointer to point into or one byte past the end of an allocated
+     /// object, and it wraps with two's complement arithmetic. The resulting
+     /// value is not necessarily valid to be used to actually access memory.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::pointer::wrapping_offset`](../../std/primitive.pointer.html#method.wrapping_offset).
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     pub fn arith_offset<T>(dst: *const T, offset: isize) -> *const T;
+ 
+     /// Equivalent to the appropriate `llvm.memcpy.p0i8.0i8.*` intrinsic, with
+     /// a size of `count` * `size_of::<T>()` and an alignment of
+     /// `min_align_of::<T>()`
+     ///
+     /// The volatile parameter is set to `true`, so it will not be optimized out
+     /// unless size is equal to zero.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn volatile_copy_nonoverlapping_memory<T>(dst: *mut T, src: *const T, count: usize);
+     /// Equivalent to the appropriate `llvm.memmove.p0i8.0i8.*` intrinsic, with
+     /// a size of `count` * `size_of::<T>()` and an alignment of
+     /// `min_align_of::<T>()`
+     ///
+     /// The volatile parameter is set to `true`, so it will not be optimized out
+     /// unless size is equal to zero.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn volatile_copy_memory<T>(dst: *mut T, src: *const T, count: usize);
+     /// Equivalent to the appropriate `llvm.memset.p0i8.*` intrinsic, with a
+     /// size of `count` * `size_of::<T>()` and an alignment of
+     /// `min_align_of::<T>()`.
+     ///
+     /// The volatile parameter is set to `true`, so it will not be optimized out
+     /// unless size is equal to zero.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn volatile_set_memory<T>(dst: *mut T, val: u8, count: usize);
+ 
+     /// Performs a volatile load from the `src` pointer.
+     ///
+     /// The stabilized version of this intrinsic is [`core::ptr::read_volatile`](crate::ptr::read_volatile).
+     pub fn volatile_load<T>(src: *const T) -> T;
+     /// Performs a volatile store to the `dst` pointer.
+     ///
+     /// The stabilized version of this intrinsic is [`core::ptr::write_volatile`](crate::ptr::write_volatile).
+     pub fn volatile_store<T>(dst: *mut T, val: T);
+ 
+     /// Performs a volatile load from the `src` pointer
+     /// The pointer is not required to be aligned.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn unaligned_volatile_load<T>(src: *const T) -> T;
+     /// Performs a volatile store to the `dst` pointer.
+     /// The pointer is not required to be aligned.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn unaligned_volatile_store<T>(dst: *mut T, val: T);
+ 
+     /// Returns the square root of an `f32`
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::sqrt`](../../std/primitive.f32.html#method.sqrt)
+     pub fn sqrtf32(x: f32) -> f32;
+     /// Returns the square root of an `f64`
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::sqrt`](../../std/primitive.f64.html#method.sqrt)
+     pub fn sqrtf64(x: f64) -> f64;
+ 
+     /// Raises an `f32` to an integer power.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::powi`](../../std/primitive.f32.html#method.powi)
+     pub fn powif32(a: f32, x: i32) -> f32;
+     /// Raises an `f64` to an integer power.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::powi`](../../std/primitive.f64.html#method.powi)
+     pub fn powif64(a: f64, x: i32) -> f64;
+ 
+     /// Returns the sine of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::sin`](../../std/primitive.f32.html#method.sin)
+     pub fn sinf32(x: f32) -> f32;
+     /// Returns the sine of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::sin`](../../std/primitive.f64.html#method.sin)
+     pub fn sinf64(x: f64) -> f64;
+ 
+     /// Returns the cosine of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::cos`](../../std/primitive.f32.html#method.cos)
+     pub fn cosf32(x: f32) -> f32;
+     /// Returns the cosine of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::cos`](../../std/primitive.f64.html#method.cos)
+     pub fn cosf64(x: f64) -> f64;
+ 
+     /// Raises an `f32` to an `f32` power.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::powf`](../../std/primitive.f32.html#method.powf)
+     pub fn powf32(a: f32, x: f32) -> f32;
+     /// Raises an `f64` to an `f64` power.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::powf`](../../std/primitive.f64.html#method.powf)
+     pub fn powf64(a: f64, x: f64) -> f64;
+ 
+     /// Returns the exponential of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::exp`](../../std/primitive.f32.html#method.exp)
+     pub fn expf32(x: f32) -> f32;
+     /// Returns the exponential of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::exp`](../../std/primitive.f64.html#method.exp)
+     pub fn expf64(x: f64) -> f64;
+ 
+     /// Returns 2 raised to the power of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::exp2`](../../std/primitive.f32.html#method.exp2)
+     pub fn exp2f32(x: f32) -> f32;
+     /// Returns 2 raised to the power of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::exp2`](../../std/primitive.f64.html#method.exp2)
+     pub fn exp2f64(x: f64) -> f64;
+ 
+     /// Returns the natural logarithm of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::ln`](../../std/primitive.f32.html#method.ln)
+     pub fn logf32(x: f32) -> f32;
+     /// Returns the natural logarithm of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::ln`](../../std/primitive.f64.html#method.ln)
+     pub fn logf64(x: f64) -> f64;
+ 
+     /// Returns the base 10 logarithm of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::log10`](../../std/primitive.f32.html#method.log10)
+     pub fn log10f32(x: f32) -> f32;
+     /// Returns the base 10 logarithm of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::log10`](../../std/primitive.f64.html#method.log10)
+     pub fn log10f64(x: f64) -> f64;
+ 
+     /// Returns the base 2 logarithm of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::log2`](../../std/primitive.f32.html#method.log2)
+     pub fn log2f32(x: f32) -> f32;
+     /// Returns the base 2 logarithm of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::log2`](../../std/primitive.f64.html#method.log2)
+     pub fn log2f64(x: f64) -> f64;
+ 
+     /// Returns `a * b + c` for `f32` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::mul_add`](../../std/primitive.f32.html#method.mul_add)
+     pub fn fmaf32(a: f32, b: f32, c: f32) -> f32;
+     /// Returns `a * b + c` for `f64` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::mul_add`](../../std/primitive.f64.html#method.mul_add)
+     pub fn fmaf64(a: f64, b: f64, c: f64) -> f64;
+ 
+     /// Returns the absolute value of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::abs`](../../std/primitive.f32.html#method.abs)
+     pub fn fabsf32(x: f32) -> f32;
+     /// Returns the absolute value of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::abs`](../../std/primitive.f64.html#method.abs)
+     pub fn fabsf64(x: f64) -> f64;
+ 
+     /// Returns the minimum of two `f32` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`f32::min`]
+     pub fn minnumf32(x: f32, y: f32) -> f32;
+     /// Returns the minimum of two `f64` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`f64::min`]
+     pub fn minnumf64(x: f64, y: f64) -> f64;
+     /// Returns the maximum of two `f32` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`f32::max`]
+     pub fn maxnumf32(x: f32, y: f32) -> f32;
+     /// Returns the maximum of two `f64` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`f64::max`]
+     pub fn maxnumf64(x: f64, y: f64) -> f64;
+ 
+     /// Copies the sign from `y` to `x` for `f32` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::copysign`](../../std/primitive.f32.html#method.copysign)
+     pub fn copysignf32(x: f32, y: f32) -> f32;
+     /// Copies the sign from `y` to `x` for `f64` values.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::copysign`](../../std/primitive.f64.html#method.copysign)
+     pub fn copysignf64(x: f64, y: f64) -> f64;
+ 
+     /// Returns the largest integer less than or equal to an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::floor`](../../std/primitive.f32.html#method.floor)
+     pub fn floorf32(x: f32) -> f32;
+     /// Returns the largest integer less than or equal to an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::floor`](../../std/primitive.f64.html#method.floor)
+     pub fn floorf64(x: f64) -> f64;
+ 
+     /// Returns the smallest integer greater than or equal to an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::ceil`](../../std/primitive.f32.html#method.ceil)
+     pub fn ceilf32(x: f32) -> f32;
+     /// Returns the smallest integer greater than or equal to an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::ceil`](../../std/primitive.f64.html#method.ceil)
+     pub fn ceilf64(x: f64) -> f64;
+ 
+     /// Returns the integer part of an `f32`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::trunc`](../../std/primitive.f32.html#method.trunc)
+     pub fn truncf32(x: f32) -> f32;
+     /// Returns the integer part of an `f64`.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::trunc`](../../std/primitive.f64.html#method.trunc)
+     pub fn truncf64(x: f64) -> f64;
+ 
+     /// Returns the nearest integer to an `f32`. May raise an inexact floating-point exception
+     /// if the argument is not an integer.
+     pub fn rintf32(x: f32) -> f32;
+     /// Returns the nearest integer to an `f64`. May raise an inexact floating-point exception
+     /// if the argument is not an integer.
+     pub fn rintf64(x: f64) -> f64;
+ 
+     /// Returns the nearest integer to an `f32`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn nearbyintf32(x: f32) -> f32;
+     /// Returns the nearest integer to an `f64`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn nearbyintf64(x: f64) -> f64;
+ 
+     /// Returns the nearest integer to an `f32`. Rounds half-way cases away from zero.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f32::round`](../../std/primitive.f32.html#method.round)
+     pub fn roundf32(x: f32) -> f32;
+     /// Returns the nearest integer to an `f64`. Rounds half-way cases away from zero.
+     ///
+     /// The stabilized version of this intrinsic is
+     /// [`std::f64::round`](../../std/primitive.f64.html#method.round)
+     pub fn roundf64(x: f64) -> f64;
+ 
+     /// Float addition that allows optimizations based on algebraic rules.
+     /// May assume inputs are finite.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn fadd_fast<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Float subtraction that allows optimizations based on algebraic rules.
+     /// May assume inputs are finite.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn fsub_fast<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Float multiplication that allows optimizations based on algebraic rules.
+     /// May assume inputs are finite.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn fmul_fast<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Float division that allows optimizations based on algebraic rules.
+     /// May assume inputs are finite.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn fdiv_fast<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Float remainder that allows optimizations based on algebraic rules.
+     /// May assume inputs are finite.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn frem_fast<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Convert with LLVM’s fptoui/fptosi, which may return undef for values out of range
+     /// (<https://github.com/rust-lang/rust/issues/10184>)
+     ///
+     /// Stabilized as [`f32::to_int_unchecked`] and [`f64::to_int_unchecked`].
+     pub fn float_to_int_unchecked<Float: Copy, Int: Copy>(value: Float) -> Int;
+ 
+     /// Returns the number of bits set in an integer type `T`
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `count_ones` method. For example,
+     /// [`u32::count_ones`]
+     #[rustc_const_stable(feature = "const_ctpop", since = "1.40.0")]
+     pub fn ctpop<T: Copy>(x: T) -> T;
+ 
+     /// Returns the number of leading unset bits (zeroes) in an integer type `T`.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `leading_zeros` method. For example,
+     /// [`u32::leading_zeros`]
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(core_intrinsics)]
+     ///
+     /// use std::intrinsics::ctlz;
+     ///
+     /// let x = 0b0001_1100_u8;
+     /// let num_leading = ctlz(x);
+     /// assert_eq!(num_leading, 3);
+     /// ```
+     ///
+     /// An `x` with value `0` will return the bit width of `T`.
+     ///
+     /// ```
+     /// #![feature(core_intrinsics)]
+     ///
+     /// use std::intrinsics::ctlz;
+     ///
+     /// let x = 0u16;
+     /// let num_leading = ctlz(x);
+     /// assert_eq!(num_leading, 16);
+     /// ```
+     #[rustc_const_stable(feature = "const_ctlz", since = "1.40.0")]
+     pub fn ctlz<T: Copy>(x: T) -> T;
+ 
+     /// Like `ctlz`, but extra-unsafe as it returns `undef` when
+     /// given an `x` with value `0`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(core_intrinsics)]
+     ///
+     /// use std::intrinsics::ctlz_nonzero;
+     ///
+     /// let x = 0b0001_1100_u8;
+     /// let num_leading = unsafe { ctlz_nonzero(x) };
+     /// assert_eq!(num_leading, 3);
+     /// ```
+     #[rustc_const_unstable(feature = "constctlz", issue = "none")]
+     pub fn ctlz_nonzero<T: Copy>(x: T) -> T;
+ 
+     /// Returns the number of trailing unset bits (zeroes) in an integer type `T`.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `trailing_zeros` method. For example,
+     /// [`u32::trailing_zeros`]
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(core_intrinsics)]
+     ///
+     /// use std::intrinsics::cttz;
+     ///
+     /// let x = 0b0011_1000_u8;
+     /// let num_trailing = cttz(x);
+     /// assert_eq!(num_trailing, 3);
+     /// ```
+     ///
+     /// An `x` with value `0` will return the bit width of `T`:
+     ///
+     /// ```
+     /// #![feature(core_intrinsics)]
+     ///
+     /// use std::intrinsics::cttz;
+     ///
+     /// let x = 0u16;
+     /// let num_trailing = cttz(x);
+     /// assert_eq!(num_trailing, 16);
+     /// ```
+     #[rustc_const_stable(feature = "const_cttz", since = "1.40.0")]
+     pub fn cttz<T: Copy>(x: T) -> T;
+ 
+     /// Like `cttz`, but extra-unsafe as it returns `undef` when
+     /// given an `x` with value `0`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(core_intrinsics)]
+     ///
+     /// use std::intrinsics::cttz_nonzero;
+     ///
+     /// let x = 0b0011_1000_u8;
+     /// let num_trailing = unsafe { cttz_nonzero(x) };
+     /// assert_eq!(num_trailing, 3);
+     /// ```
+     #[rustc_const_unstable(feature = "const_cttz", issue = "none")]
+     pub fn cttz_nonzero<T: Copy>(x: T) -> T;
+ 
+     /// Reverses the bytes in an integer type `T`.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `swap_bytes` method. For example,
+     /// [`u32::swap_bytes`]
+     #[rustc_const_stable(feature = "const_bswap", since = "1.40.0")]
+     pub fn bswap<T: Copy>(x: T) -> T;
+ 
+     /// Reverses the bits in an integer type `T`.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `reverse_bits` method. For example,
+     /// [`u32::reverse_bits`]
+     #[rustc_const_stable(feature = "const_bitreverse", since = "1.40.0")]
+     pub fn bitreverse<T: Copy>(x: T) -> T;
+ 
+     /// Performs checked integer addition.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `overflowing_add` method. For example,
+     /// [`u32::overflowing_add`]
+     #[rustc_const_stable(feature = "const_int_overflow", since = "1.40.0")]
+     pub fn add_with_overflow<T: Copy>(x: T, y: T) -> (T, bool);
+ 
+     /// Performs checked integer subtraction
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `overflowing_sub` method. For example,
+     /// [`u32::overflowing_sub`]
+     #[rustc_const_stable(feature = "const_int_overflow", since = "1.40.0")]
+     pub fn sub_with_overflow<T: Copy>(x: T, y: T) -> (T, bool);
+ 
+     /// Performs checked integer multiplication
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `overflowing_mul` method. For example,
+     /// [`u32::overflowing_mul`]
+     #[rustc_const_stable(feature = "const_int_overflow", since = "1.40.0")]
+     pub fn mul_with_overflow<T: Copy>(x: T, y: T) -> (T, bool);
+ 
+     /// Performs an exact division, resulting in undefined behavior where
+     /// `x % y != 0` or `y == 0` or `x == T::MIN && y == -1`
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     pub fn exact_div<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Performs an unchecked division, resulting in undefined behavior
+     /// where y = 0 or x = `T::MIN` and y = -1
+     ///
+     /// Safe wrappers for this intrinsic are available on the integer
+     /// primitives via the `checked_div` method. For example,
+     /// [`u32::checked_div`]
+     #[rustc_const_unstable(feature = "const_int_unchecked_arith", issue = "none")]
+     pub fn unchecked_div<T: Copy>(x: T, y: T) -> T;
+     /// Returns the remainder of an unchecked division, resulting in
+     /// undefined behavior where y = 0 or x = `T::MIN` and y = -1
+     ///
+     /// Safe wrappers for this intrinsic are available on the integer
+     /// primitives via the `checked_rem` method. For example,
+     /// [`u32::checked_rem`]
+     #[rustc_const_unstable(feature = "const_int_unchecked_arith", issue = "none")]
+     pub fn unchecked_rem<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Performs an unchecked left shift, resulting in undefined behavior when
+     /// y < 0 or y >= N, where N is the width of T in bits.
+     ///
+     /// Safe wrappers for this intrinsic are available on the integer
+     /// primitives via the `checked_shl` method. For example,
+     /// [`u32::checked_shl`]
+     #[rustc_const_stable(feature = "const_int_unchecked", since = "1.40.0")]
+     pub fn unchecked_shl<T: Copy>(x: T, y: T) -> T;
+     /// Performs an unchecked right shift, resulting in undefined behavior when
+     /// y < 0 or y >= N, where N is the width of T in bits.
+     ///
+     /// Safe wrappers for this intrinsic are available on the integer
+     /// primitives via the `checked_shr` method. For example,
+     /// [`u32::checked_shr`]
+     #[rustc_const_stable(feature = "const_int_unchecked", since = "1.40.0")]
+     pub fn unchecked_shr<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Returns the result of an unchecked addition, resulting in
+     /// undefined behavior when `x + y > T::MAX` or `x + y < T::MIN`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_int_unchecked_arith", issue = "none")]
+     pub fn unchecked_add<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Returns the result of an unchecked subtraction, resulting in
+     /// undefined behavior when `x - y > T::MAX` or `x - y < T::MIN`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_int_unchecked_arith", issue = "none")]
+     pub fn unchecked_sub<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Returns the result of an unchecked multiplication, resulting in
+     /// undefined behavior when `x * y > T::MAX` or `x * y < T::MIN`.
+     ///
+     /// This intrinsic does not have a stable counterpart.
+     #[rustc_const_unstable(feature = "const_int_unchecked_arith", issue = "none")]
+     pub fn unchecked_mul<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Performs rotate left.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `rotate_left` method. For example,
+     /// [`u32::rotate_left`]
+     #[rustc_const_stable(feature = "const_int_rotate", since = "1.40.0")]
+     pub fn rotate_left<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Performs rotate right.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `rotate_right` method. For example,
+     /// [`u32::rotate_right`]
+     #[rustc_const_stable(feature = "const_int_rotate", since = "1.40.0")]
+     pub fn rotate_right<T: Copy>(x: T, y: T) -> T;
+ 
+     /// Returns (a + b) mod 2<sup>N</sup>, where N is the width of T in bits.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `wrapping_add` method. For example,
+     /// [`u32::wrapping_add`]
+     #[rustc_const_stable(feature = "const_int_wrapping", since = "1.40.0")]
+     pub fn wrapping_add<T: Copy>(a: T, b: T) -> T;
+     /// Returns (a - b) mod 2<sup>N</sup>, where N is the width of T in bits.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `wrapping_sub` method. For example,
+     /// [`u32::wrapping_sub`]
+     #[rustc_const_stable(feature = "const_int_wrapping", since = "1.40.0")]
+     pub fn wrapping_sub<T: Copy>(a: T, b: T) -> T;
+     /// Returns (a * b) mod 2<sup>N</sup>, where N is the width of T in bits.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `wrapping_mul` method. For example,
+     /// [`u32::wrapping_mul`]
+     #[rustc_const_stable(feature = "const_int_wrapping", since = "1.40.0")]
+     pub fn wrapping_mul<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Computes `a + b`, while saturating at numeric bounds.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `saturating_add` method. For example,
+     /// [`u32::saturating_add`]
+     #[rustc_const_stable(feature = "const_int_saturating", since = "1.40.0")]
+     pub fn saturating_add<T: Copy>(a: T, b: T) -> T;
+     /// Computes `a - b`, while saturating at numeric bounds.
+     ///
+     /// The stabilized versions of this intrinsic are available on the integer
+     /// primitives via the `saturating_sub` method. For example,
+     /// [`u32::saturating_sub`]
+     #[rustc_const_stable(feature = "const_int_saturating", since = "1.40.0")]
+     pub fn saturating_sub<T: Copy>(a: T, b: T) -> T;
+ 
+     /// Returns the value of the discriminant for the variant in 'v',
+     /// cast to a `u64`; if `T` has no discriminant, returns 0.
+     ///
+     /// The stabilized version of this intrinsic is [`core::mem::discriminant`](crate::mem::discriminant).
+     #[rustc_const_unstable(feature = "const_discriminant", issue = "69821")]
+     pub fn discriminant_value<T>(v: &T) -> <T as DiscriminantKind>::Discriminant;
+ 
+     /// Returns the number of variants of the type `T` cast to a `usize`;
+     /// if `T` has no variants, returns 0. Uninhabited variants will be counted.
+     ///
+     /// The to-be-stabilized version of this intrinsic is [`mem::variant_count`].
+     #[rustc_const_unstable(feature = "variant_count", issue = "73662")]
+     pub fn variant_count<T>() -> usize;
+ 
+     /// Rust's "try catch" construct which invokes the function pointer `try_fn`
+     /// with the data pointer `data`.
+     ///
+     /// The third argument is a function called if a panic occurs. This function
+     /// takes the data pointer and a pointer to the target-specific exception
+     /// object that was caught. For more information see the compiler's
+     /// source as well as std's catch implementation.
+     pub fn r#try(try_fn: fn(*mut u8), data: *mut u8, catch_fn: fn(*mut u8, *mut u8)) -> i32;
+ 
+     /// Emits a `!nontemporal` store according to LLVM (see their docs).
+     /// Probably will never become stable.
+     pub fn nontemporal_store<T>(ptr: *mut T, val: T);
+ 
+     /// See documentation of `<*const T>::offset_from` for details.
+     #[rustc_const_unstable(feature = "const_ptr_offset_from", issue = "41079")]
+     pub fn ptr_offset_from<T>(ptr: *const T, base: *const T) -> isize;
+ 
+     /// See documentation of `<*const T>::guaranteed_eq` for details.
+     #[rustc_const_unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     pub fn ptr_guaranteed_eq<T>(ptr: *const T, other: *const T) -> bool;
+ 
+     /// See documentation of `<*const T>::guaranteed_ne` for details.
+     #[rustc_const_unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     pub fn ptr_guaranteed_ne<T>(ptr: *const T, other: *const T) -> bool;
+ }
+ 
+ // Some functions are defined here because they accidentally got made
+ // available in this module on stable. See <https://github.com/rust-lang/rust/issues/15702>.
+ // (`transmute` also falls into this category, but it cannot be wrapped due to the
+ // check that `T` and `U` have the same size.)
+ 
+ /// Checks whether `ptr` is properly aligned with respect to
+ /// `align_of::<T>()`.
+ pub(crate) fn is_aligned_and_not_null<T>(ptr: *const T) -> bool {
+     !ptr.is_null() && ptr as usize % mem::align_of::<T>() == 0
+ }
+ 
+ /// Checks whether the regions of memory starting at `src` and `dst` of size
+ /// `count * size_of::<T>()` do *not* overlap.
+ pub(crate) fn is_nonoverlapping<T>(src: *const T, dst: *const T, count: usize) -> bool {
+     let src_usize = src as usize;
+     let dst_usize = dst as usize;
+     let size = mem::size_of::<T>().checked_mul(count).unwrap();
+     let diff = if src_usize > dst_usize { src_usize - dst_usize } else { dst_usize - src_usize };
+     // If the absolute distance between the ptrs is at least as big as the size of the buffer,
+     // they do not overlap.
+     diff >= size
+ }
+ 
+ /// Copies `count * size_of::<T>()` bytes from `src` to `dst`. The source
+ /// and destination must *not* overlap.
+ ///
+ /// For regions of memory which might overlap, use [`copy`] instead.
+ ///
+ /// `copy_nonoverlapping` is semantically equivalent to C's [`memcpy`], but
+ /// with the argument order swapped.
+ ///
+ /// [`memcpy`]: https://en.cppreference.com/w/c/string/byte/memcpy
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `src` must be [valid] for reads of `count * size_of::<T>()` bytes.
+ ///
+ /// * `dst` must be [valid] for writes of `count * size_of::<T>()` bytes.
+ ///
+ /// * Both `src` and `dst` must be properly aligned.
+ ///
+ /// * The region of memory beginning at `src` with a size of `count *
+ ///   size_of::<T>()` bytes must *not* overlap with the region of memory
+ ///   beginning at `dst` with the same size.
+ ///
+ /// Like [`read`], `copy_nonoverlapping` creates a bitwise copy of `T`, regardless of
+ /// whether `T` is [`Copy`]. If `T` is not [`Copy`], using *both* the values
+ /// in the region beginning at `*src` and the region beginning at `*dst` can
+ /// [violate memory safety][read-ownership].
+ ///
+ /// Note that even if the effectively copied size (`count * size_of::<T>()`) is
+ /// `0`, the pointers must be non-NULL and properly aligned.
+ ///
+ /// [`read`]: crate::ptr::read
+ /// [read-ownership]: crate::ptr::read#ownership-of-the-returned-value
+ /// [valid]: crate::ptr#safety
+ ///
+ /// # Examples
+ ///
+ /// Manually implement [`Vec::append`]:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// /// Moves all the elements of `src` into `dst`, leaving `src` empty.
+ /// fn append<T>(dst: &mut Vec<T>, src: &mut Vec<T>) {
+ ///     let src_len = src.len();
+ ///     let dst_len = dst.len();
+ ///
+ ///     // Ensure that `dst` has enough capacity to hold all of `src`.
+ ///     dst.reserve(src_len);
+ ///
+ ///     unsafe {
+ ///         // The call to offset is always safe because `Vec` will never
+ ///         // allocate more than `isize::MAX` bytes.
+ ///         let dst_ptr = dst.as_mut_ptr().offset(dst_len as isize);
+ ///         let src_ptr = src.as_ptr();
+ ///
+ ///         // Truncate `src` without dropping its contents. We do this first,
+ ///         // to avoid problems in case something further down panics.
+ ///         src.set_len(0);
+ ///
+ ///         // The two regions cannot overlap because mutable references do
+ ///         // not alias, and two different vectors cannot own the same
+ ///         // memory.
+ ///         ptr::copy_nonoverlapping(src_ptr, dst_ptr, src_len);
+ ///
+ ///         // Notify `dst` that it now holds the contents of `src`.
+ ///         dst.set_len(dst_len + src_len);
+ ///     }
+ /// }
+ ///
+ /// let mut a = vec!['r'];
+ /// let mut b = vec!['u', 's', 't'];
+ ///
+ /// append(&mut a, &mut b);
+ ///
+ /// assert_eq!(a, &['r', 'u', 's', 't']);
+ /// assert!(b.is_empty());
+ /// ```
+ ///
+ /// [`Vec::append`]: ../../std/vec/struct.Vec.html#method.append
+ #[doc(alias = "memcpy")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[inline]
+ pub unsafe fn copy_nonoverlapping<T>(src: *const T, dst: *mut T, count: usize) {
+     extern "rust-intrinsic" {
+         fn copy_nonoverlapping<T>(src: *const T, dst: *mut T, count: usize);
+     }
+ 
+     if cfg!(debug_assertions)
+         && !(is_aligned_and_not_null(src)
+             && is_aligned_and_not_null(dst)
+             && is_nonoverlapping(src, dst, count))
+     {
+         // Not panicking to keep codegen impact smaller.
+         abort();
+     }
+ 
+     // SAFETY: the safety contract for `copy_nonoverlapping` must be
+     // upheld by the caller.
+     unsafe { copy_nonoverlapping(src, dst, count) }
+ }
+ 
+ /// Copies `count * size_of::<T>()` bytes from `src` to `dst`. The source
+ /// and destination may overlap.
+ ///
+ /// If the source and destination will *never* overlap,
+ /// [`copy_nonoverlapping`] can be used instead.
+ ///
+ /// `copy` is semantically equivalent to C's [`memmove`], but with the argument
+ /// order swapped. Copying takes place as if the bytes were copied from `src`
+ /// to a temporary array and then copied from the array to `dst`.
+ ///
+ /// [`memmove`]: https://en.cppreference.com/w/c/string/byte/memmove
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `src` must be [valid] for reads of `count * size_of::<T>()` bytes.
+ ///
+ /// * `dst` must be [valid] for writes of `count * size_of::<T>()` bytes.
+ ///
+ /// * Both `src` and `dst` must be properly aligned.
+ ///
+ /// Like [`read`], `copy` creates a bitwise copy of `T`, regardless of
+ /// whether `T` is [`Copy`]. If `T` is not [`Copy`], using both the values
+ /// in the region beginning at `*src` and the region beginning at `*dst` can
+ /// [violate memory safety][read-ownership].
+ ///
+ /// Note that even if the effectively copied size (`count * size_of::<T>()`) is
+ /// `0`, the pointers must be non-NULL and properly aligned.
+ ///
+ /// [`read`]: crate::ptr::read
+ /// [read-ownership]: crate::ptr::read#ownership-of-the-returned-value
+ /// [valid]: crate::ptr#safety
+ ///
+ /// # Examples
+ ///
+ /// Efficiently create a Rust vector from an unsafe buffer:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// /// # Safety
+ /// ///
+ /// /// * `ptr` must be correctly aligned for its type and non-zero.
+ /// /// * `ptr` must be valid for reads of `elts` contiguous elements of type `T`.
+ /// /// * Those elements must not be used after calling this function unless `T: Copy`.
+ /// # #[allow(dead_code)]
+ /// unsafe fn from_buf_raw<T>(ptr: *const T, elts: usize) -> Vec<T> {
+ ///     let mut dst = Vec::with_capacity(elts);
+ ///
+ ///     // SAFETY: Our precondition ensures the source is aligned and valid,
+ ///     // and `Vec::with_capacity` ensures that we have usable space to write them.
+ ///     ptr::copy(ptr, dst.as_mut_ptr(), elts);
+ ///
+ ///     // SAFETY: We created it with this much capacity earlier,
+ ///     // and the previous `copy` has initialized these elements.
+ ///     dst.set_len(elts);
+ ///     dst
+ /// }
+ /// ```
+ #[doc(alias = "memmove")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[inline]
+ pub unsafe fn copy<T>(src: *const T, dst: *mut T, count: usize) {
+     extern "rust-intrinsic" {
+         fn copy<T>(src: *const T, dst: *mut T, count: usize);
+     }
+ 
+     if cfg!(debug_assertions) && !(is_aligned_and_not_null(src) && is_aligned_and_not_null(dst)) {
+         // Not panicking to keep codegen impact smaller.
+         abort();
+     }
+ 
+     // SAFETY: the safety contract for `copy` must be upheld by the caller.
+     unsafe { copy(src, dst, count) }
+ }
+ 
+ /// Sets `count * size_of::<T>()` bytes of memory starting at `dst` to
+ /// `val`.
+ ///
+ /// `write_bytes` is similar to C's [`memset`], but sets `count *
+ /// size_of::<T>()` bytes to `val`.
+ ///
+ /// [`memset`]: https://en.cppreference.com/w/c/string/byte/memset
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `dst` must be [valid] for writes of `count * size_of::<T>()` bytes.
+ ///
+ /// * `dst` must be properly aligned.
+ ///
+ /// Additionally, the caller must ensure that writing `count *
+ /// size_of::<T>()` bytes to the given region of memory results in a valid
+ /// value of `T`. Using a region of memory typed as a `T` that contains an
+ /// invalid value of `T` is undefined behavior.
+ ///
+ /// Note that even if the effectively copied size (`count * size_of::<T>()`) is
+ /// `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// [valid]: crate::ptr#safety
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut vec = vec![0u32; 4];
+ /// unsafe {
+ ///     let vec_ptr = vec.as_mut_ptr();
+ ///     ptr::write_bytes(vec_ptr, 0xfe, 2);
+ /// }
+ /// assert_eq!(vec, [0xfefefefe, 0xfefefefe, 0, 0]);
+ /// ```
+ ///
+ /// Creating an invalid value:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut v = Box::new(0i32);
+ ///
+ /// unsafe {
+ ///     // Leaks the previously held value by overwriting the `Box<T>` with
+ ///     // a null pointer.
+ ///     ptr::write_bytes(&mut v as *mut Box<i32>, 0, 1);
+ /// }
+ ///
+ /// // At this point, using or dropping `v` results in undefined behavior.
+ /// // drop(v); // ERROR
+ ///
+ /// // Even leaking `v` "uses" it, and hence is undefined behavior.
+ /// // mem::forget(v); // ERROR
+ ///
+ /// // In fact, `v` is invalid according to basic type layout invariants, so *any*
+ /// // operation touching it is undefined behavior.
+ /// // let v2 = v; // ERROR
+ ///
+ /// unsafe {
+ ///     // Let us instead put in a valid value
+ ///     ptr::write(&mut v as *mut Box<i32>, Box::new(42i32));
+ /// }
+ ///
+ /// // Now the box is fine
+ /// assert_eq!(*v, 42);
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[inline]
+ pub unsafe fn write_bytes<T>(dst: *mut T, val: u8, count: usize) {
+     extern "rust-intrinsic" {
+         fn write_bytes<T>(dst: *mut T, val: u8, count: usize);
+     }
+ 
+     debug_assert!(is_aligned_and_not_null(dst), "attempt to write to unaligned or null pointer");
+ 
+     // SAFETY: the safety contract for `write_bytes` must be upheld by the caller.
+     unsafe { write_bytes(dst, val, count) }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/chain.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/chain.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/chain.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/chain.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,327 ----
+ use crate::iter::{DoubleEndedIterator, FusedIterator, Iterator, TrustedLen};
+ use crate::ops::Try;
+ use crate::usize;
+ 
+ /// An iterator that links two iterators together, in a chain.
+ ///
+ /// This `struct` is created by [`Iterator::chain`]. See its documentation
+ /// for more.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::iter::Chain;
+ /// use std::slice::Iter;
+ ///
+ /// let a1 = [1, 2, 3];
+ /// let a2 = [4, 5, 6];
+ /// let iter: Chain<Iter<_>, Iter<_>> = a1.iter().chain(a2.iter());
+ /// ```
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Chain<A, B> {
+     // These are "fused" with `Option` so we don't need separate state to track which part is
+     // already exhausted, and we may also get niche layout for `None`. We don't use the real `Fuse`
+     // adapter because its specialization for `FusedIterator` unconditionally descends into the
+     // iterator, and that could be expensive to keep revisiting stuff like nested chains. It also
+     // hurts compiler performance to add more iterator layers to `Chain`.
+     //
+     // Only the "first" iterator is actually set `None` when exhausted, depending on whether you
+     // iterate forward or backward. If you mix directions, then both sides may be `None`.
+     a: Option<A>,
+     b: Option<B>,
+ }
+ impl<A, B> Chain<A, B> {
+     pub(in super::super) fn new(a: A, b: B) -> Chain<A, B> {
+         Chain { a: Some(a), b: Some(b) }
+     }
+ }
+ 
+ /// Fuse the iterator if the expression is `None`.
+ macro_rules! fuse {
+     ($self:ident . $iter:ident . $($call:tt)+) => {
+         match $self.$iter {
+             Some(ref mut iter) => match iter.$($call)+ {
+                 None => {
+                     $self.$iter = None;
+                     None
+                 }
+                 item => item,
+             },
+             None => None,
+         }
+     };
+ }
+ 
+ /// Try an iterator method without fusing,
+ /// like an inline `.as_mut().and_then(...)`
+ macro_rules! maybe {
+     ($self:ident . $iter:ident . $($call:tt)+) => {
+         match $self.$iter {
+             Some(ref mut iter) => iter.$($call)+,
+             None => None,
+         }
+     };
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B> Iterator for Chain<A, B>
+ where
+     A: Iterator,
+     B: Iterator<Item = A::Item>,
+ {
+     type Item = A::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A::Item> {
+         match fuse!(self.a.next()) {
+             None => maybe!(self.b.next()),
+             item => item,
+         }
+     }
+ 
+     #[inline]
+     #[rustc_inherit_overflow_checks]
+     fn count(self) -> usize {
+         let a_count = match self.a {
+             Some(a) => a.count(),
+             None => 0,
+         };
+         let b_count = match self.b {
+             Some(b) => b.count(),
+             None => 0,
+         };
+         a_count + b_count
+     }
+ 
+     fn try_fold<Acc, F, R>(&mut self, mut acc: Acc, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         if let Some(ref mut a) = self.a {
+             acc = a.try_fold(acc, &mut f)?;
+             self.a = None;
+         }
+         if let Some(ref mut b) = self.b {
+             acc = b.try_fold(acc, f)?;
+             // we don't fuse the second iterator
+         }
+         try { acc }
+     }
+ 
+     fn fold<Acc, F>(self, mut acc: Acc, mut f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         if let Some(a) = self.a {
+             acc = a.fold(acc, &mut f);
+         }
+         if let Some(b) = self.b {
+             acc = b.fold(acc, f);
+         }
+         acc
+     }
+ 
+     #[inline]
+     fn advance_by(&mut self, n: usize) -> Result<(), usize> {
+         let mut rem = n;
+ 
+         if let Some(ref mut a) = self.a {
+             match a.advance_by(rem) {
+                 Ok(()) => return Ok(()),
+                 Err(k) => rem -= k,
+             }
+             self.a = None;
+         }
+ 
+         if let Some(ref mut b) = self.b {
+             match b.advance_by(rem) {
+                 Ok(()) => return Ok(()),
+                 Err(k) => rem -= k,
+             }
+             // we don't fuse the second iterator
+         }
+ 
+         if rem == 0 { Ok(()) } else { Err(n - rem) }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, mut n: usize) -> Option<Self::Item> {
+         if let Some(ref mut a) = self.a {
+             match a.advance_by(n) {
+                 Ok(()) => match a.next() {
+                     None => n = 0,
+                     x => return x,
+                 },
+                 Err(k) => n -= k,
+             }
+ 
+             self.a = None;
+         }
+ 
+         maybe!(self.b.nth(n))
+     }
+ 
+     #[inline]
+     fn find<P>(&mut self, mut predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         match fuse!(self.a.find(&mut predicate)) {
+             None => maybe!(self.b.find(predicate)),
+             item => item,
+         }
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<A::Item> {
+         // Must exhaust a before b.
+         let a_last = match self.a {
+             Some(a) => a.last(),
+             None => None,
+         };
+         let b_last = match self.b {
+             Some(b) => b.last(),
+             None => None,
+         };
+         b_last.or(a_last)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         match self {
+             Chain { a: Some(a), b: Some(b) } => {
+                 let (a_lower, a_upper) = a.size_hint();
+                 let (b_lower, b_upper) = b.size_hint();
+ 
+                 let lower = a_lower.saturating_add(b_lower);
+ 
+                 let upper = match (a_upper, b_upper) {
+                     (Some(x), Some(y)) => x.checked_add(y),
+                     _ => None,
+                 };
+ 
+                 (lower, upper)
+             }
+             Chain { a: Some(a), b: None } => a.size_hint(),
+             Chain { a: None, b: Some(b) } => b.size_hint(),
+             Chain { a: None, b: None } => (0, Some(0)),
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B> DoubleEndedIterator for Chain<A, B>
+ where
+     A: DoubleEndedIterator,
+     B: DoubleEndedIterator<Item = A::Item>,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<A::Item> {
+         match fuse!(self.b.next_back()) {
+             None => maybe!(self.a.next_back()),
+             item => item,
+         }
+     }
+ 
+     #[inline]
+     fn advance_back_by(&mut self, n: usize) -> Result<(), usize> {
+         let mut rem = n;
+ 
+         if let Some(ref mut b) = self.b {
+             match b.advance_back_by(rem) {
+                 Ok(()) => return Ok(()),
+                 Err(k) => rem -= k,
+             }
+             self.b = None;
+         }
+ 
+         if let Some(ref mut a) = self.a {
+             match a.advance_back_by(rem) {
+                 Ok(()) => return Ok(()),
+                 Err(k) => rem -= k,
+             }
+             // we don't fuse the second iterator
+         }
+ 
+         if rem == 0 { Ok(()) } else { Err(n - rem) }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, mut n: usize) -> Option<Self::Item> {
+         if let Some(ref mut b) = self.b {
+             match b.advance_back_by(n) {
+                 Ok(()) => match b.next_back() {
+                     None => n = 0,
+                     x => return x,
+                 },
+                 Err(k) => n -= k,
+             }
+ 
+             self.b = None;
+         }
+ 
+         maybe!(self.a.nth_back(n))
+     }
+ 
+     #[inline]
+     fn rfind<P>(&mut self, mut predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         match fuse!(self.b.rfind(&mut predicate)) {
+             None => maybe!(self.a.rfind(predicate)),
+             item => item,
+         }
+     }
+ 
+     fn try_rfold<Acc, F, R>(&mut self, mut acc: Acc, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         if let Some(ref mut b) = self.b {
+             acc = b.try_rfold(acc, &mut f)?;
+             self.b = None;
+         }
+         if let Some(ref mut a) = self.a {
+             acc = a.try_rfold(acc, f)?;
+             // we don't fuse the second iterator
+         }
+         try { acc }
+     }
+ 
+     fn rfold<Acc, F>(self, mut acc: Acc, mut f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         if let Some(b) = self.b {
+             acc = b.rfold(acc, &mut f);
+         }
+         if let Some(a) = self.a {
+             acc = a.rfold(acc, f);
+         }
+         acc
+     }
+ }
+ 
+ // Note: *both* must be fused to handle double-ended iterators.
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A, B> FusedIterator for Chain<A, B>
+ where
+     A: FusedIterator,
+     B: FusedIterator<Item = A::Item>,
+ {
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A, B> TrustedLen for Chain<A, B>
+ where
+     A: TrustedLen,
+     B: TrustedLen<Item = A::Item>,
+ {
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/flatten.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/flatten.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/flatten.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/flatten.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,421 ----
+ use crate::fmt;
+ use crate::ops::Try;
+ 
+ use super::super::{DoubleEndedIterator, Fuse, FusedIterator, Iterator};
+ use super::Map;
+ 
+ /// An iterator that maps each element to an iterator, and yields the elements
+ /// of the produced iterators.
+ ///
+ /// This `struct` is created by [`Iterator::flat_map`]. See its documentation
+ /// for more.
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct FlatMap<I, U: IntoIterator, F> {
+     inner: FlattenCompat<Map<I, F>, <U as IntoIterator>::IntoIter>,
+ }
+ impl<I: Iterator, U: IntoIterator, F: FnMut(I::Item) -> U> FlatMap<I, U, F> {
+     pub(in super::super) fn new(iter: I, f: F) -> FlatMap<I, U, F> {
+         FlatMap { inner: FlattenCompat::new(iter.map(f)) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Clone, U, F: Clone> Clone for FlatMap<I, U, F>
+ where
+     U: Clone + IntoIterator<IntoIter: Clone>,
+ {
+     fn clone(&self) -> Self {
+         FlatMap { inner: self.inner.clone() }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, U, F> fmt::Debug for FlatMap<I, U, F>
+ where
+     U: IntoIterator<IntoIter: fmt::Debug>,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("FlatMap").field("inner", &self.inner).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator, U: IntoIterator, F> Iterator for FlatMap<I, U, F>
+ where
+     F: FnMut(I::Item) -> U,
+ {
+     type Item = U::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<U::Item> {
+         self.inner.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.inner.try_fold(init, fold)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.inner.fold(init, fold)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: DoubleEndedIterator, U, F> DoubleEndedIterator for FlatMap<I, U, F>
+ where
+     F: FnMut(I::Item) -> U,
+     U: IntoIterator<IntoIter: DoubleEndedIterator>,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<U::Item> {
+         self.inner.next_back()
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.inner.try_rfold(init, fold)
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.inner.rfold(init, fold)
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I, U, F> FusedIterator for FlatMap<I, U, F>
+ where
+     I: FusedIterator,
+     U: IntoIterator,
+     F: FnMut(I::Item) -> U,
+ {
+ }
+ 
+ /// An iterator that flattens one level of nesting in an iterator of things
+ /// that can be turned into iterators.
+ ///
+ /// This `struct` is created by the [`flatten`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`flatten`]: Iterator::flatten
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ pub struct Flatten<I: Iterator<Item: IntoIterator>> {
+     inner: FlattenCompat<I, <I::Item as IntoIterator>::IntoIter>,
+ }
+ 
+ impl<I: Iterator<Item: IntoIterator>> Flatten<I> {
+     pub(in super::super) fn new(iter: I) -> Flatten<I> {
+         Flatten { inner: FlattenCompat::new(iter) }
+     }
+ }
+ 
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ impl<I, U> fmt::Debug for Flatten<I>
+ where
+     I: fmt::Debug + Iterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: fmt::Debug + Iterator,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Flatten").field("inner", &self.inner).finish()
+     }
+ }
+ 
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ impl<I, U> Clone for Flatten<I>
+ where
+     I: Clone + Iterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: Clone + Iterator,
+ {
+     fn clone(&self) -> Self {
+         Flatten { inner: self.inner.clone() }
+     }
+ }
+ 
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ impl<I, U> Iterator for Flatten<I>
+ where
+     I: Iterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: Iterator,
+ {
+     type Item = U::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<U::Item> {
+         self.inner.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.inner.try_fold(init, fold)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.inner.fold(init, fold)
+     }
+ }
+ 
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ impl<I, U> DoubleEndedIterator for Flatten<I>
+ where
+     I: DoubleEndedIterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: DoubleEndedIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<U::Item> {
+         self.inner.next_back()
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.inner.try_rfold(init, fold)
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.inner.rfold(init, fold)
+     }
+ }
+ 
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ impl<I, U> FusedIterator for Flatten<I>
+ where
+     I: FusedIterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: Iterator,
+ {
+ }
+ 
+ /// Real logic of both `Flatten` and `FlatMap` which simply delegate to
+ /// this type.
+ #[derive(Clone, Debug)]
+ struct FlattenCompat<I, U> {
+     iter: Fuse<I>,
+     frontiter: Option<U>,
+     backiter: Option<U>,
+ }
+ impl<I, U> FlattenCompat<I, U>
+ where
+     I: Iterator,
+ {
+     /// Adapts an iterator by flattening it, for use in `flatten()` and `flat_map()`.
+     fn new(iter: I) -> FlattenCompat<I, U> {
+         FlattenCompat { iter: iter.fuse(), frontiter: None, backiter: None }
+     }
+ }
+ 
+ impl<I, U> Iterator for FlattenCompat<I, U>
+ where
+     I: Iterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: Iterator,
+ {
+     type Item = U::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<U::Item> {
+         loop {
+             if let Some(ref mut inner) = self.frontiter {
+                 match inner.next() {
+                     None => self.frontiter = None,
+                     elt @ Some(_) => return elt,
+                 }
+             }
+             match self.iter.next() {
+                 None => return self.backiter.as_mut()?.next(),
+                 Some(inner) => self.frontiter = Some(inner.into_iter()),
+             }
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (flo, fhi) = self.frontiter.as_ref().map_or((0, Some(0)), U::size_hint);
+         let (blo, bhi) = self.backiter.as_ref().map_or((0, Some(0)), U::size_hint);
+         let lo = flo.saturating_add(blo);
+         match (self.iter.size_hint(), fhi, bhi) {
+             ((0, Some(0)), Some(a), Some(b)) => (lo, a.checked_add(b)),
+             _ => (lo, None),
+         }
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, mut init: Acc, mut fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         #[inline]
+         fn flatten<'a, T: IntoIterator, Acc, R: Try<Ok = Acc>>(
+             frontiter: &'a mut Option<T::IntoIter>,
+             fold: &'a mut impl FnMut(Acc, T::Item) -> R,
+         ) -> impl FnMut(Acc, T) -> R + 'a {
+             move |acc, x| {
+                 let mut mid = x.into_iter();
+                 let r = mid.try_fold(acc, &mut *fold);
+                 *frontiter = Some(mid);
+                 r
+             }
+         }
+ 
+         if let Some(ref mut front) = self.frontiter {
+             init = front.try_fold(init, &mut fold)?;
+         }
+         self.frontiter = None;
+ 
+         init = self.iter.try_fold(init, flatten(&mut self.frontiter, &mut fold))?;
+         self.frontiter = None;
+ 
+         if let Some(ref mut back) = self.backiter {
+             init = back.try_fold(init, &mut fold)?;
+         }
+         self.backiter = None;
+ 
+         try { init }
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, ref mut fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn flatten<U: Iterator, Acc>(
+             fold: &mut impl FnMut(Acc, U::Item) -> Acc,
+         ) -> impl FnMut(Acc, U) -> Acc + '_ {
+             move |acc, iter| iter.fold(acc, &mut *fold)
+         }
+ 
+         self.frontiter
+             .into_iter()
+             .chain(self.iter.map(IntoIterator::into_iter))
+             .chain(self.backiter)
+             .fold(init, flatten(fold))
+     }
+ }
+ 
+ impl<I, U> DoubleEndedIterator for FlattenCompat<I, U>
+ where
+     I: DoubleEndedIterator<Item: IntoIterator<IntoIter = U, Item = U::Item>>,
+     U: DoubleEndedIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<U::Item> {
+         loop {
+             if let Some(ref mut inner) = self.backiter {
+                 match inner.next_back() {
+                     None => self.backiter = None,
+                     elt @ Some(_) => return elt,
+                 }
+             }
+             match self.iter.next_back() {
+                 None => return self.frontiter.as_mut()?.next_back(),
+                 next => self.backiter = next.map(IntoIterator::into_iter),
+             }
+         }
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, mut init: Acc, mut fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         #[inline]
+         fn flatten<'a, T: IntoIterator, Acc, R: Try<Ok = Acc>>(
+             backiter: &'a mut Option<T::IntoIter>,
+             fold: &'a mut impl FnMut(Acc, T::Item) -> R,
+         ) -> impl FnMut(Acc, T) -> R + 'a
+         where
+             T::IntoIter: DoubleEndedIterator,
+         {
+             move |acc, x| {
+                 let mut mid = x.into_iter();
+                 let r = mid.try_rfold(acc, &mut *fold);
+                 *backiter = Some(mid);
+                 r
+             }
+         }
+ 
+         if let Some(ref mut back) = self.backiter {
+             init = back.try_rfold(init, &mut fold)?;
+         }
+         self.backiter = None;
+ 
+         init = self.iter.try_rfold(init, flatten(&mut self.backiter, &mut fold))?;
+         self.backiter = None;
+ 
+         if let Some(ref mut front) = self.frontiter {
+             init = front.try_rfold(init, &mut fold)?;
+         }
+         self.frontiter = None;
+ 
+         try { init }
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, ref mut fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn flatten<U: DoubleEndedIterator, Acc>(
+             fold: &mut impl FnMut(Acc, U::Item) -> Acc,
+         ) -> impl FnMut(Acc, U) -> Acc + '_ {
+             move |acc, iter| iter.rfold(acc, &mut *fold)
+         }
+ 
+         self.frontiter
+             .into_iter()
+             .chain(self.iter.map(IntoIterator::into_iter))
+             .chain(self.backiter)
+             .rfold(init, flatten(fold))
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/fuse.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/fuse.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/fuse.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/fuse.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,540 ----
+ use super::InPlaceIterable;
+ use crate::intrinsics;
+ use crate::iter::adapters::zip::try_get_unchecked;
+ use crate::iter::adapters::SourceIter;
+ use crate::iter::TrustedRandomAccess;
+ use crate::iter::{DoubleEndedIterator, ExactSizeIterator, FusedIterator, Iterator};
+ use crate::ops::Try;
+ 
+ /// An iterator that yields `None` forever after the underlying iterator
+ /// yields `None` once.
+ ///
+ /// This `struct` is created by [`Iterator::fuse`]. See its documentation
+ /// for more.
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Fuse<I> {
+     // NOTE: for `I: FusedIterator`, this is always assumed `Some`!
+     iter: Option<I>,
+ }
+ impl<I> Fuse<I> {
+     pub(in crate::iter) fn new(iter: I) -> Fuse<I> {
+         Fuse { iter: Some(iter) }
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I> FusedIterator for Fuse<I> where I: Iterator {}
+ 
+ /// Fuse the iterator if the expression is `None`.
+ macro_rules! fuse {
+     ($self:ident . iter . $($call:tt)+) => {
+         match $self.iter {
+             Some(ref mut iter) => match iter.$($call)+ {
+                 None => {
+                     $self.iter = None;
+                     None
+                 }
+                 item => item,
+             },
+             None => None,
+         }
+     };
+ }
+ 
+ // NOTE: for `I: FusedIterator`, we assume that the iterator is always `Some`.
+ // Implementing this as a directly-expanded macro helps codegen performance.
+ macro_rules! unchecked {
+     ($self:ident) => {
+         match $self {
+             Fuse { iter: Some(iter) } => iter,
+             // SAFETY: the specialized iterator never sets `None`
+             Fuse { iter: None } => unsafe { intrinsics::unreachable() },
+         }
+     };
+ }
+ 
+ // Any implementation here is made internal to avoid exposing default fns outside this trait
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> Iterator for Fuse<I>
+ where
+     I: Iterator,
+ {
+     type Item = <I as Iterator>::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<Self::Item> {
+         FuseImpl::next(self)
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<I::Item> {
+         FuseImpl::nth(self, n)
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         FuseImpl::last(self)
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         FuseImpl::count(self)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         FuseImpl::size_hint(self)
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, acc: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         FuseImpl::try_fold(self, acc, fold)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, acc: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         FuseImpl::fold(self, acc, fold)
+     }
+ 
+     #[inline]
+     fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         FuseImpl::find(self, predicate)
+     }
+ 
+     #[inline]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item
+     where
+         Self: TrustedRandomAccess,
+     {
+         match self.iter {
+             // SAFETY: the caller must uphold the contract for
+             // `Iterator::__iterator_get_unchecked`.
+             Some(ref mut iter) => unsafe { try_get_unchecked(iter, idx) },
+             // SAFETY: the caller asserts there is an item at `i`, so we're not exhausted.
+             None => unsafe { intrinsics::unreachable() },
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> DoubleEndedIterator for Fuse<I>
+ where
+     I: DoubleEndedIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<<I as Iterator>::Item> {
+         FuseImpl::next_back(self)
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<<I as Iterator>::Item> {
+         FuseImpl::nth_back(self, n)
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, acc: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         FuseImpl::try_rfold(self, acc, fold)
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, acc: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         FuseImpl::rfold(self, acc, fold)
+     }
+ 
+     #[inline]
+     fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         FuseImpl::rfind(self, predicate)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ExactSizeIterator for Fuse<I>
+ where
+     I: ExactSizeIterator,
+ {
+     fn len(&self) -> usize {
+         FuseImpl::len(self)
+     }
+ 
+     fn is_empty(&self) -> bool {
+         FuseImpl::is_empty(self)
+     }
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<I> TrustedRandomAccess for Fuse<I>
+ where
+     I: TrustedRandomAccess,
+ {
+     fn may_have_side_effect() -> bool {
+         I::may_have_side_effect()
+     }
+ }
+ 
+ // Fuse specialization trait
+ #[doc(hidden)]
+ trait FuseImpl<I> {
+     type Item;
+ 
+     // Functions specific to any normal Iterators
+     fn next(&mut self) -> Option<Self::Item>;
+     fn nth(&mut self, n: usize) -> Option<Self::Item>;
+     fn last(self) -> Option<Self::Item>;
+     fn count(self) -> usize;
+     fn size_hint(&self) -> (usize, Option<usize>);
+     fn try_fold<Acc, Fold, R>(&mut self, acc: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>;
+     fn fold<Acc, Fold>(self, acc: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc;
+     fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool;
+ 
+     // Functions specific to DoubleEndedIterators
+     fn next_back(&mut self) -> Option<Self::Item>
+     where
+         I: DoubleEndedIterator;
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item>
+     where
+         I: DoubleEndedIterator;
+     fn try_rfold<Acc, Fold, R>(&mut self, acc: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+         I: DoubleEndedIterator;
+     fn rfold<Acc, Fold>(self, acc: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+         I: DoubleEndedIterator;
+     fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+         I: DoubleEndedIterator;
+ 
+     // Functions specific to ExactSizeIterator
+     fn len(&self) -> usize
+     where
+         I: ExactSizeIterator;
+     fn is_empty(&self) -> bool
+     where
+         I: ExactSizeIterator;
+ }
+ 
+ // General Fuse impl
+ #[doc(hidden)]
+ impl<I> FuseImpl<I> for Fuse<I>
+ where
+     I: Iterator,
+ {
+     type Item = <I as Iterator>::Item;
+ 
+     #[inline]
+     default fn next(&mut self) -> Option<<I as Iterator>::Item> {
+         fuse!(self.iter.next())
+     }
+ 
+     #[inline]
+     default fn nth(&mut self, n: usize) -> Option<I::Item> {
+         fuse!(self.iter.nth(n))
+     }
+ 
+     #[inline]
+     default fn last(self) -> Option<I::Item> {
+         match self.iter {
+             Some(iter) => iter.last(),
+             None => None,
+         }
+     }
+ 
+     #[inline]
+     default fn count(self) -> usize {
+         match self.iter {
+             Some(iter) => iter.count(),
+             None => 0,
+         }
+     }
+ 
+     #[inline]
+     default fn size_hint(&self) -> (usize, Option<usize>) {
+         match self.iter {
+             Some(ref iter) => iter.size_hint(),
+             None => (0, Some(0)),
+         }
+     }
+ 
+     #[inline]
+     default fn try_fold<Acc, Fold, R>(&mut self, mut acc: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         if let Some(ref mut iter) = self.iter {
+             acc = iter.try_fold(acc, fold)?;
+             self.iter = None;
+         }
+         try { acc }
+     }
+ 
+     #[inline]
+     default fn fold<Acc, Fold>(self, mut acc: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         if let Some(iter) = self.iter {
+             acc = iter.fold(acc, fold);
+         }
+         acc
+     }
+ 
+     #[inline]
+     default fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         fuse!(self.iter.find(predicate))
+     }
+ 
+     #[inline]
+     default fn next_back(&mut self) -> Option<<I as Iterator>::Item>
+     where
+         I: DoubleEndedIterator,
+     {
+         fuse!(self.iter.next_back())
+     }
+ 
+     #[inline]
+     default fn nth_back(&mut self, n: usize) -> Option<<I as Iterator>::Item>
+     where
+         I: DoubleEndedIterator,
+     {
+         fuse!(self.iter.nth_back(n))
+     }
+ 
+     #[inline]
+     default fn try_rfold<Acc, Fold, R>(&mut self, mut acc: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+         I: DoubleEndedIterator,
+     {
+         if let Some(ref mut iter) = self.iter {
+             acc = iter.try_rfold(acc, fold)?;
+             self.iter = None;
+         }
+         try { acc }
+     }
+ 
+     #[inline]
+     default fn rfold<Acc, Fold>(self, mut acc: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+         I: DoubleEndedIterator,
+     {
+         if let Some(iter) = self.iter {
+             acc = iter.rfold(acc, fold);
+         }
+         acc
+     }
+ 
+     #[inline]
+     default fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+         I: DoubleEndedIterator,
+     {
+         fuse!(self.iter.rfind(predicate))
+     }
+ 
+     #[inline]
+     default fn len(&self) -> usize
+     where
+         I: ExactSizeIterator,
+     {
+         match self.iter {
+             Some(ref iter) => iter.len(),
+             None => 0,
+         }
+     }
+ 
+     #[inline]
+     default fn is_empty(&self) -> bool
+     where
+         I: ExactSizeIterator,
+     {
+         match self.iter {
+             Some(ref iter) => iter.is_empty(),
+             None => true,
+         }
+     }
+ }
+ 
+ #[doc(hidden)]
+ impl<I> FuseImpl<I> for Fuse<I>
+ where
+     I: FusedIterator,
+ {
+     #[inline]
+     fn next(&mut self) -> Option<<I as Iterator>::Item> {
+         unchecked!(self).next()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<I::Item> {
+         unchecked!(self).nth(n)
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<I::Item> {
+         unchecked!(self).last()
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         unchecked!(self).count()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         unchecked!(self).size_hint()
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         unchecked!(self).try_fold(init, fold)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         unchecked!(self).fold(init, fold)
+     }
+ 
+     #[inline]
+     fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         unchecked!(self).find(predicate)
+     }
+ 
+     #[inline]
+     fn next_back(&mut self) -> Option<<I as Iterator>::Item>
+     where
+         I: DoubleEndedIterator,
+     {
+         unchecked!(self).next_back()
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<<I as Iterator>::Item>
+     where
+         I: DoubleEndedIterator,
+     {
+         unchecked!(self).nth_back(n)
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+         I: DoubleEndedIterator,
+     {
+         unchecked!(self).try_rfold(init, fold)
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+         I: DoubleEndedIterator,
+     {
+         unchecked!(self).rfold(init, fold)
+     }
+ 
+     #[inline]
+     fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+         I: DoubleEndedIterator,
+     {
+         unchecked!(self).rfind(predicate)
+     }
+ 
+     #[inline]
+     fn len(&self) -> usize
+     where
+         I: ExactSizeIterator,
+     {
+         unchecked!(self).len()
+     }
+ 
+     #[inline]
+     fn is_empty(&self) -> bool
+     where
+         I: ExactSizeIterator,
+     {
+         unchecked!(self).is_empty()
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, I: FusedIterator> SourceIter for Fuse<I>
+ where
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         match self.iter {
+             // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+             Some(ref mut iter) => unsafe { SourceIter::as_inner(iter) },
+             // SAFETY: the specialized iterator never sets `None`
+             None => unsafe { intrinsics::unreachable() },
+         }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable> InPlaceIterable for Fuse<I> {}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2968 ----
+ use crate::cmp;
+ use crate::fmt;
+ use crate::intrinsics;
+ use crate::ops::{Add, AddAssign, ControlFlow, Try};
+ 
+ use super::from_fn;
+ use super::{
+     DoubleEndedIterator, ExactSizeIterator, FusedIterator, InPlaceIterable, Iterator, TrustedLen,
+ };
+ 
+ mod chain;
+ mod flatten;
+ mod fuse;
+ mod zip;
+ 
+ pub use self::chain::Chain;
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::flatten::{FlatMap, Flatten};
+ pub use self::fuse::Fuse;
+ use self::zip::try_get_unchecked;
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ pub use self::zip::TrustedRandomAccess;
+ pub use self::zip::Zip;
+ 
+ /// This trait provides transitive access to source-stage in an interator-adapter pipeline
+ /// under the conditions that
+ /// * the iterator source `S` itself implements `SourceIter<Source = S>`
+ /// * there is a delegating implementation of this trait for each adapter in the pipeline between
+ ///   the source and the pipeline consumer.
+ ///
+ /// When the source is an owning iterator struct (commonly called `IntoIter`) then
+ /// this can be useful for specializing [`FromIterator`] implementations or recovering the
+ /// remaining elements after an iterator has been partially exhausted.
+ ///
+ /// Note that implementations do not necessarily have to provide access to the inner-most
+ /// source of a pipeline. A stateful intermediate adapter might eagerly evaluate a part
+ /// of the pipeline and expose its internal storage as source.
+ ///
+ /// The trait is unsafe because implementers must uphold additional safety properties.
+ /// See [`as_inner`] for details.
+ ///
+ /// # Examples
+ ///
+ /// Retrieving a partially consumed source:
+ ///
+ /// ```
+ /// # #![feature(inplace_iteration)]
+ /// # use std::iter::SourceIter;
+ ///
+ /// let mut iter = vec![9, 9, 9].into_iter().map(|i| i * i);
+ /// let _ = iter.next();
+ /// let mut remainder = std::mem::replace(unsafe { iter.as_inner() }, Vec::new().into_iter());
+ /// println!("n = {} elements remaining", remainder.len());
+ /// ```
+ ///
+ /// [`FromIterator`]: crate::iter::FromIterator
+ /// [`as_inner`]: SourceIter::as_inner
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ pub unsafe trait SourceIter {
+     /// A source stage in an iterator pipeline.
+     type Source: Iterator;
+ 
+     /// Retrieve the source of an iterator pipeline.
+     ///
+     /// # Safety
+     ///
+     /// Implementations of must return the same mutable reference for their lifetime, unless
+     /// replaced by a caller.
+     /// Callers may only replace the reference when they stopped iteration and drop the
+     /// iterator pipeline after extracting the source.
+     ///
+     /// This means iterator adapters can rely on the source not changing during
+     /// iteration but they cannot rely on it in their Drop implementations.
+     ///
+     /// Implementing this method means adapters relinquish private-only access to their
+     /// source and can only rely on guarantees made based on method receiver types.
+     /// The lack of restricted access also requires that adapters must uphold the source's
+     /// public API even when they have access to its internals.
+     ///
+     /// Callers in turn must expect the source to be in any state that is consistent with
+     /// its public API since adapters sitting between it and the source have the same
+     /// access. In particular an adapter may have consumed more elements than strictly necessary.
+     ///
+     /// The overall goal of these requirements is to let the consumer of a pipeline use
+     /// * whatever remains in the source after iteration has stopped
+     /// * the memory that has become unused by advancing a consuming iterator
+     ///
+     /// [`next()`]: Iterator::next
+     unsafe fn as_inner(&mut self) -> &mut Self::Source;
+ }
+ 
+ /// A double-ended iterator with the direction inverted.
+ ///
+ /// This `struct` is created by the [`rev`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`rev`]: Iterator::rev
+ /// [`Iterator`]: trait.Iterator.html
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Rev<T> {
+     iter: T,
+ }
+ impl<T> Rev<T> {
+     pub(super) fn new(iter: T) -> Rev<T> {
+         Rev { iter }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> Iterator for Rev<I>
+ where
+     I: DoubleEndedIterator,
+ {
+     type Item = <I as Iterator>::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<<I as Iterator>::Item> {
+         self.iter.next_back()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     #[inline]
+     fn advance_by(&mut self, n: usize) -> Result<(), usize> {
+         self.iter.advance_back_by(n)
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<<I as Iterator>::Item> {
+         self.iter.nth_back(n)
+     }
+ 
+     fn try_fold<B, F, R>(&mut self, init: B, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         self.iter.try_rfold(init, f)
+     }
+ 
+     fn fold<Acc, F>(self, init: Acc, f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.rfold(init, f)
+     }
+ 
+     #[inline]
+     fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         self.iter.rfind(predicate)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> DoubleEndedIterator for Rev<I>
+ where
+     I: DoubleEndedIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<<I as Iterator>::Item> {
+         self.iter.next()
+     }
+ 
+     #[inline]
+     fn advance_back_by(&mut self, n: usize) -> Result<(), usize> {
+         self.iter.advance_by(n)
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<<I as Iterator>::Item> {
+         self.iter.nth(n)
+     }
+ 
+     fn try_rfold<B, F, R>(&mut self, init: B, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         self.iter.try_fold(init, f)
+     }
+ 
+     fn rfold<Acc, F>(self, init: Acc, f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.fold(init, f)
+     }
+ 
+     fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         self.iter.find(predicate)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ExactSizeIterator for Rev<I>
+ where
+     I: ExactSizeIterator + DoubleEndedIterator,
+ {
+     fn len(&self) -> usize {
+         self.iter.len()
+     }
+ 
+     fn is_empty(&self) -> bool {
+         self.iter.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I> FusedIterator for Rev<I> where I: FusedIterator + DoubleEndedIterator {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<I> TrustedLen for Rev<I> where I: TrustedLen + DoubleEndedIterator {}
+ 
+ /// An iterator that copies the elements of an underlying iterator.
+ ///
+ /// This `struct` is created by the [`copied`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`copied`]: Iterator::copied
+ /// [`Iterator`]: trait.Iterator.html
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[derive(Clone, Debug)]
+ pub struct Copied<I> {
+     it: I,
+ }
+ 
+ impl<I> Copied<I> {
+     pub(super) fn new(it: I) -> Copied<I> {
+         Copied { it }
+     }
+ }
+ 
+ fn copy_fold<T: Copy, Acc>(mut f: impl FnMut(Acc, T) -> Acc) -> impl FnMut(Acc, &T) -> Acc {
+     move |acc, &elt| f(acc, elt)
+ }
+ 
+ fn copy_try_fold<T: Copy, Acc, R>(mut f: impl FnMut(Acc, T) -> R) -> impl FnMut(Acc, &T) -> R {
+     move |acc, &elt| f(acc, elt)
+ }
+ 
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ impl<'a, I, T: 'a> Iterator for Copied<I>
+ where
+     I: Iterator<Item = &'a T>,
+     T: Copy,
+ {
+     type Item = T;
+ 
+     fn next(&mut self) -> Option<T> {
+         self.it.next().copied()
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.it.size_hint()
+     }
+ 
+     fn try_fold<B, F, R>(&mut self, init: B, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         self.it.try_fold(init, copy_try_fold(f))
+     }
+ 
+     fn fold<Acc, F>(self, init: Acc, f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.it.fold(init, copy_fold(f))
+     }
+ 
+     fn nth(&mut self, n: usize) -> Option<T> {
+         self.it.nth(n).copied()
+     }
+ 
+     fn last(self) -> Option<T> {
+         self.it.last().copied()
+     }
+ 
+     fn count(self) -> usize {
+         self.it.count()
+     }
+ 
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> T
+     where
+         Self: TrustedRandomAccess,
+     {
+         // SAFETY: the caller must uphold the contract for
+         // `Iterator::__iterator_get_unchecked`.
+         *unsafe { try_get_unchecked(&mut self.it, idx) }
+     }
+ }
+ 
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ impl<'a, I, T: 'a> DoubleEndedIterator for Copied<I>
+ where
+     I: DoubleEndedIterator<Item = &'a T>,
+     T: Copy,
+ {
+     fn next_back(&mut self) -> Option<T> {
+         self.it.next_back().copied()
+     }
+ 
+     fn try_rfold<B, F, R>(&mut self, init: B, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         self.it.try_rfold(init, copy_try_fold(f))
+     }
+ 
+     fn rfold<Acc, F>(self, init: Acc, f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.it.rfold(init, copy_fold(f))
+     }
+ }
+ 
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ impl<'a, I, T: 'a> ExactSizeIterator for Copied<I>
+ where
+     I: ExactSizeIterator<Item = &'a T>,
+     T: Copy,
+ {
+     fn len(&self) -> usize {
+         self.it.len()
+     }
+ 
+     fn is_empty(&self) -> bool {
+         self.it.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ impl<'a, I, T: 'a> FusedIterator for Copied<I>
+ where
+     I: FusedIterator<Item = &'a T>,
+     T: Copy,
+ {
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<I> TrustedRandomAccess for Copied<I>
+ where
+     I: TrustedRandomAccess,
+ {
+     #[inline]
+     fn may_have_side_effect() -> bool {
+         I::may_have_side_effect()
+     }
+ }
+ 
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ unsafe impl<'a, I, T: 'a> TrustedLen for Copied<I>
+ where
+     I: TrustedLen<Item = &'a T>,
+     T: Copy,
+ {
+ }
+ 
+ /// An iterator that clones the elements of an underlying iterator.
+ ///
+ /// This `struct` is created by the [`cloned`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`cloned`]: Iterator::cloned
+ /// [`Iterator`]: trait.Iterator.html
+ #[stable(feature = "iter_cloned", since = "1.1.0")]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[derive(Clone, Debug)]
+ pub struct Cloned<I> {
+     it: I,
+ }
+ impl<I> Cloned<I> {
+     pub(super) fn new(it: I) -> Cloned<I> {
+         Cloned { it }
+     }
+ }
+ 
+ fn clone_try_fold<T: Clone, Acc, R>(mut f: impl FnMut(Acc, T) -> R) -> impl FnMut(Acc, &T) -> R {
+     move |acc, elt| f(acc, elt.clone())
+ }
+ 
+ #[stable(feature = "iter_cloned", since = "1.1.0")]
+ impl<'a, I, T: 'a> Iterator for Cloned<I>
+ where
+     I: Iterator<Item = &'a T>,
+     T: Clone,
+ {
+     type Item = T;
+ 
+     fn next(&mut self) -> Option<T> {
+         self.it.next().cloned()
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.it.size_hint()
+     }
+ 
+     fn try_fold<B, F, R>(&mut self, init: B, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         self.it.try_fold(init, clone_try_fold(f))
+     }
+ 
+     fn fold<Acc, F>(self, init: Acc, f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.it.map(T::clone).fold(init, f)
+     }
+ 
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> T
+     where
+         Self: TrustedRandomAccess,
+     {
+         // SAFETY: the caller must uphold the contract for
+         // `Iterator::__iterator_get_unchecked`.
+         unsafe { try_get_unchecked(&mut self.it, idx).clone() }
+     }
+ }
+ 
+ #[stable(feature = "iter_cloned", since = "1.1.0")]
+ impl<'a, I, T: 'a> DoubleEndedIterator for Cloned<I>
+ where
+     I: DoubleEndedIterator<Item = &'a T>,
+     T: Clone,
+ {
+     fn next_back(&mut self) -> Option<T> {
+         self.it.next_back().cloned()
+     }
+ 
+     fn try_rfold<B, F, R>(&mut self, init: B, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         self.it.try_rfold(init, clone_try_fold(f))
+     }
+ 
+     fn rfold<Acc, F>(self, init: Acc, f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.it.map(T::clone).rfold(init, f)
+     }
+ }
+ 
+ #[stable(feature = "iter_cloned", since = "1.1.0")]
+ impl<'a, I, T: 'a> ExactSizeIterator for Cloned<I>
+ where
+     I: ExactSizeIterator<Item = &'a T>,
+     T: Clone,
+ {
+     fn len(&self) -> usize {
+         self.it.len()
+     }
+ 
+     fn is_empty(&self) -> bool {
+         self.it.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<'a, I, T: 'a> FusedIterator for Cloned<I>
+ where
+     I: FusedIterator<Item = &'a T>,
+     T: Clone,
+ {
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<I> TrustedRandomAccess for Cloned<I>
+ where
+     I: TrustedRandomAccess,
+ {
+     #[inline]
+     fn may_have_side_effect() -> bool {
+         true
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<'a, I, T: 'a> TrustedLen for Cloned<I>
+ where
+     I: TrustedLen<Item = &'a T>,
+     T: Clone,
+ {
+ }
+ 
+ /// An iterator that repeats endlessly.
+ ///
+ /// This `struct` is created by the [`cycle`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`cycle`]: Iterator::cycle
+ /// [`Iterator`]: trait.Iterator.html
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Cycle<I> {
+     orig: I,
+     iter: I,
+ }
+ impl<I: Clone> Cycle<I> {
+     pub(super) fn new(iter: I) -> Cycle<I> {
+         Cycle { orig: iter.clone(), iter }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> Iterator for Cycle<I>
+ where
+     I: Clone + Iterator,
+ {
+     type Item = <I as Iterator>::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<<I as Iterator>::Item> {
+         match self.iter.next() {
+             None => {
+                 self.iter = self.orig.clone();
+                 self.iter.next()
+             }
+             y => y,
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         // the cycle iterator is either empty or infinite
+         match self.orig.size_hint() {
+             sz @ (0, Some(0)) => sz,
+             (0, _) => (0, None),
+             _ => (usize::MAX, None),
+         }
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, F, R>(&mut self, mut acc: Acc, mut f: F) -> R
+     where
+         F: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         // fully iterate the current iterator. this is necessary because
+         // `self.iter` may be empty even when `self.orig` isn't
+         acc = self.iter.try_fold(acc, &mut f)?;
+         self.iter = self.orig.clone();
+ 
+         // complete a full cycle, keeping track of whether the cycled
+         // iterator is empty or not. we need to return early in case
+         // of an empty iterator to prevent an infinite loop
+         let mut is_empty = true;
+         acc = self.iter.try_fold(acc, |acc, x| {
+             is_empty = false;
+             f(acc, x)
+         })?;
+ 
+         if is_empty {
+             return try { acc };
+         }
+ 
+         loop {
+             self.iter = self.orig.clone();
+             acc = self.iter.try_fold(acc, &mut f)?;
+         }
+     }
+ 
+     // No `fold` override, because `fold` doesn't make much sense for `Cycle`,
+     // and we can't do anything better than the default.
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I> FusedIterator for Cycle<I> where I: Clone + Iterator {}
+ 
+ /// An iterator for stepping iterators by a custom amount.
+ ///
+ /// This `struct` is created by the [`step_by`] method on [`Iterator`]. See
+ /// its documentation for more.
+ ///
+ /// [`step_by`]: Iterator::step_by
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "iterator_step_by", since = "1.28.0")]
+ #[derive(Clone, Debug)]
+ pub struct StepBy<I> {
+     iter: I,
+     step: usize,
+     first_take: bool,
+ }
+ impl<I> StepBy<I> {
+     pub(super) fn new(iter: I, step: usize) -> StepBy<I> {
+         assert!(step != 0);
+         StepBy { iter, step: step - 1, first_take: true }
+     }
+ }
+ 
+ #[stable(feature = "iterator_step_by", since = "1.28.0")]
+ impl<I> Iterator for StepBy<I>
+ where
+     I: Iterator,
+ {
+     type Item = I::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<Self::Item> {
+         if self.first_take {
+             self.first_take = false;
+             self.iter.next()
+         } else {
+             self.iter.nth(self.step)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         #[inline]
+         fn first_size(step: usize) -> impl Fn(usize) -> usize {
+             move |n| if n == 0 { 0 } else { 1 + (n - 1) / (step + 1) }
+         }
+ 
+         #[inline]
+         fn other_size(step: usize) -> impl Fn(usize) -> usize {
+             move |n| n / (step + 1)
+         }
+ 
+         let (low, high) = self.iter.size_hint();
+ 
+         if self.first_take {
+             let f = first_size(self.step);
+             (f(low), high.map(f))
+         } else {
+             let f = other_size(self.step);
+             (f(low), high.map(f))
+         }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, mut n: usize) -> Option<Self::Item> {
+         if self.first_take {
+             self.first_take = false;
+             let first = self.iter.next();
+             if n == 0 {
+                 return first;
+             }
+             n -= 1;
+         }
+         // n and self.step are indices, we need to add 1 to get the amount of elements
+         // When calling `.nth`, we need to subtract 1 again to convert back to an index
+         // step + 1 can't overflow because `.step_by` sets `self.step` to `step - 1`
+         let mut step = self.step + 1;
+         // n + 1 could overflow
+         // thus, if n is usize::MAX, instead of adding one, we call .nth(step)
+         if n == usize::MAX {
+             self.iter.nth(step - 1);
+         } else {
+             n += 1;
+         }
+ 
+         // overflow handling
+         loop {
+             let mul = n.checked_mul(step);
+             {
+                 if intrinsics::likely(mul.is_some()) {
+                     return self.iter.nth(mul.unwrap() - 1);
+                 }
+             }
+             let div_n = usize::MAX / n;
+             let div_step = usize::MAX / step;
+             let nth_n = div_n * n;
+             let nth_step = div_step * step;
+             let nth = if nth_n > nth_step {
+                 step -= div_n;
+                 nth_n
+             } else {
+                 n -= div_step;
+                 nth_step
+             };
+             self.iter.nth(nth - 1);
+         }
+     }
+ 
+     fn try_fold<Acc, F, R>(&mut self, mut acc: Acc, mut f: F) -> R
+     where
+         F: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         #[inline]
+         fn nth<I: Iterator>(iter: &mut I, step: usize) -> impl FnMut() -> Option<I::Item> + '_ {
+             move || iter.nth(step)
+         }
+ 
+         if self.first_take {
+             self.first_take = false;
+             match self.iter.next() {
+                 None => return try { acc },
+                 Some(x) => acc = f(acc, x)?,
+             }
+         }
+         from_fn(nth(&mut self.iter, self.step)).try_fold(acc, f)
+     }
+ 
+     fn fold<Acc, F>(mut self, mut acc: Acc, mut f: F) -> Acc
+     where
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn nth<I: Iterator>(iter: &mut I, step: usize) -> impl FnMut() -> Option<I::Item> + '_ {
+             move || iter.nth(step)
+         }
+ 
+         if self.first_take {
+             self.first_take = false;
+             match self.iter.next() {
+                 None => return acc,
+                 Some(x) => acc = f(acc, x),
+             }
+         }
+         from_fn(nth(&mut self.iter, self.step)).fold(acc, f)
+     }
+ }
+ 
+ impl<I> StepBy<I>
+ where
+     I: ExactSizeIterator,
+ {
+     // The zero-based index starting from the end of the iterator of the
+     // last element. Used in the `DoubleEndedIterator` implementation.
+     fn next_back_index(&self) -> usize {
+         let rem = self.iter.len() % (self.step + 1);
+         if self.first_take {
+             if rem == 0 { self.step } else { rem - 1 }
+         } else {
+             rem
+         }
+     }
+ }
+ 
+ #[stable(feature = "double_ended_step_by_iterator", since = "1.38.0")]
+ impl<I> DoubleEndedIterator for StepBy<I>
+ where
+     I: DoubleEndedIterator + ExactSizeIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<Self::Item> {
+         self.iter.nth_back(self.next_back_index())
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         // `self.iter.nth_back(usize::MAX)` does the right thing here when `n`
+         // is out of bounds because the length of `self.iter` does not exceed
+         // `usize::MAX` (because `I: ExactSizeIterator`) and `nth_back` is
+         // zero-indexed
+         let n = n.saturating_mul(self.step + 1).saturating_add(self.next_back_index());
+         self.iter.nth_back(n)
+     }
+ 
+     fn try_rfold<Acc, F, R>(&mut self, init: Acc, mut f: F) -> R
+     where
+         F: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         #[inline]
+         fn nth_back<I: DoubleEndedIterator>(
+             iter: &mut I,
+             step: usize,
+         ) -> impl FnMut() -> Option<I::Item> + '_ {
+             move || iter.nth_back(step)
+         }
+ 
+         match self.next_back() {
+             None => try { init },
+             Some(x) => {
+                 let acc = f(init, x)?;
+                 from_fn(nth_back(&mut self.iter, self.step)).try_fold(acc, f)
+             }
+         }
+     }
+ 
+     #[inline]
+     fn rfold<Acc, F>(mut self, init: Acc, mut f: F) -> Acc
+     where
+         Self: Sized,
+         F: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn nth_back<I: DoubleEndedIterator>(
+             iter: &mut I,
+             step: usize,
+         ) -> impl FnMut() -> Option<I::Item> + '_ {
+             move || iter.nth_back(step)
+         }
+ 
+         match self.next_back() {
+             None => init,
+             Some(x) => {
+                 let acc = f(init, x);
+                 from_fn(nth_back(&mut self.iter, self.step)).fold(acc, f)
+             }
+         }
+     }
+ }
+ 
+ // StepBy can only make the iterator shorter, so the len will still fit.
+ #[stable(feature = "iterator_step_by", since = "1.28.0")]
+ impl<I> ExactSizeIterator for StepBy<I> where I: ExactSizeIterator {}
+ 
+ /// An iterator that maps the values of `iter` with `f`.
+ ///
+ /// This `struct` is created by the [`map`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`map`]: Iterator::map
+ /// [`Iterator`]: trait.Iterator.html
+ ///
+ /// # Notes about side effects
+ ///
+ /// The [`map`] iterator implements [`DoubleEndedIterator`], meaning that
+ /// you can also [`map`] backwards:
+ ///
+ /// ```rust
+ /// let v: Vec<i32> = vec![1, 2, 3].into_iter().map(|x| x + 1).rev().collect();
+ ///
+ /// assert_eq!(v, [4, 3, 2]);
+ /// ```
+ ///
+ /// [`DoubleEndedIterator`]: trait.DoubleEndedIterator.html
+ ///
+ /// But if your closure has state, iterating backwards may act in a way you do
+ /// not expect. Let's go through an example. First, in the forward direction:
+ ///
+ /// ```rust
+ /// let mut c = 0;
+ ///
+ /// for pair in vec!['a', 'b', 'c'].into_iter()
+ ///                                .map(|letter| { c += 1; (letter, c) }) {
+ ///     println!("{:?}", pair);
+ /// }
+ /// ```
+ ///
+ /// This will print "('a', 1), ('b', 2), ('c', 3)".
+ ///
+ /// Now consider this twist where we add a call to `rev`. This version will
+ /// print `('c', 1), ('b', 2), ('a', 3)`. Note that the letters are reversed,
+ /// but the values of the counter still go in order. This is because `map()` is
+ /// still being called lazily on each item, but we are popping items off the
+ /// back of the vector now, instead of shifting them from the front.
+ ///
+ /// ```rust
+ /// let mut c = 0;
+ ///
+ /// for pair in vec!['a', 'b', 'c'].into_iter()
+ ///                                .map(|letter| { c += 1; (letter, c) })
+ ///                                .rev() {
+ ///     println!("{:?}", pair);
+ /// }
+ /// ```
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct Map<I, F> {
+     iter: I,
+     f: F,
+ }
+ impl<I, F> Map<I, F> {
+     pub(super) fn new(iter: I, f: F) -> Map<I, F> {
+         Map { iter, f }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, F> fmt::Debug for Map<I, F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Map").field("iter", &self.iter).finish()
+     }
+ }
+ 
+ fn map_fold<T, B, Acc>(
+     mut f: impl FnMut(T) -> B,
+     mut g: impl FnMut(Acc, B) -> Acc,
+ ) -> impl FnMut(Acc, T) -> Acc {
+     move |acc, elt| g(acc, f(elt))
+ }
+ 
+ fn map_try_fold<'a, T, B, Acc, R>(
+     f: &'a mut impl FnMut(T) -> B,
+     mut g: impl FnMut(Acc, B) -> R + 'a,
+ ) -> impl FnMut(Acc, T) -> R + 'a {
+     move |acc, elt| g(acc, f(elt))
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<B, I: Iterator, F> Iterator for Map<I, F>
+ where
+     F: FnMut(I::Item) -> B,
+ {
+     type Item = B;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<B> {
+         self.iter.next().map(&mut self.f)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     fn try_fold<Acc, G, R>(&mut self, init: Acc, g: G) -> R
+     where
+         Self: Sized,
+         G: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_fold(init, map_try_fold(&mut self.f, g))
+     }
+ 
+     fn fold<Acc, G>(self, init: Acc, g: G) -> Acc
+     where
+         G: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.fold(init, map_fold(self.f, g))
+     }
+ 
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> B
+     where
+         Self: TrustedRandomAccess,
+     {
+         // SAFETY: the caller must uphold the contract for
+         // `Iterator::__iterator_get_unchecked`.
+         unsafe { (self.f)(try_get_unchecked(&mut self.iter, idx)) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<B, I: DoubleEndedIterator, F> DoubleEndedIterator for Map<I, F>
+ where
+     F: FnMut(I::Item) -> B,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<B> {
+         self.iter.next_back().map(&mut self.f)
+     }
+ 
+     fn try_rfold<Acc, G, R>(&mut self, init: Acc, g: G) -> R
+     where
+         Self: Sized,
+         G: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_rfold(init, map_try_fold(&mut self.f, g))
+     }
+ 
+     fn rfold<Acc, G>(self, init: Acc, g: G) -> Acc
+     where
+         G: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.rfold(init, map_fold(self.f, g))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<B, I: ExactSizeIterator, F> ExactSizeIterator for Map<I, F>
+ where
+     F: FnMut(I::Item) -> B,
+ {
+     fn len(&self) -> usize {
+         self.iter.len()
+     }
+ 
+     fn is_empty(&self) -> bool {
+         self.iter.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<B, I: FusedIterator, F> FusedIterator for Map<I, F> where F: FnMut(I::Item) -> B {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<B, I, F> TrustedLen for Map<I, F>
+ where
+     I: TrustedLen,
+     F: FnMut(I::Item) -> B,
+ {
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<I, F> TrustedRandomAccess for Map<I, F>
+ where
+     I: TrustedRandomAccess,
+ {
+     #[inline]
+     fn may_have_side_effect() -> bool {
+         true
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, B, I: Iterator, F> SourceIter for Map<I, F>
+ where
+     F: FnMut(I::Item) -> B,
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<B, I: InPlaceIterable, F> InPlaceIterable for Map<I, F> where F: FnMut(I::Item) -> B {}
+ 
+ /// An iterator that filters the elements of `iter` with `predicate`.
+ ///
+ /// This `struct` is created by the [`filter`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`filter`]: Iterator::filter
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct Filter<I, P> {
+     iter: I,
+     predicate: P,
+ }
+ impl<I, P> Filter<I, P> {
+     pub(super) fn new(iter: I, predicate: P) -> Filter<I, P> {
+         Filter { iter, predicate }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, P> fmt::Debug for Filter<I, P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Filter").field("iter", &self.iter).finish()
+     }
+ }
+ 
+ fn filter_fold<T, Acc>(
+     mut predicate: impl FnMut(&T) -> bool,
+     mut fold: impl FnMut(Acc, T) -> Acc,
+ ) -> impl FnMut(Acc, T) -> Acc {
+     move |acc, item| if predicate(&item) { fold(acc, item) } else { acc }
+ }
+ 
+ fn filter_try_fold<'a, T, Acc, R: Try<Ok = Acc>>(
+     predicate: &'a mut impl FnMut(&T) -> bool,
+     mut fold: impl FnMut(Acc, T) -> R + 'a,
+ ) -> impl FnMut(Acc, T) -> R + 'a {
+     move |acc, item| if predicate(&item) { fold(acc, item) } else { try { acc } }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator, P> Iterator for Filter<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+ {
+     type Item = I::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<I::Item> {
+         self.iter.find(&mut self.predicate)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (_, upper) = self.iter.size_hint();
+         (0, upper) // can't know a lower bound, due to the predicate
+     }
+ 
+     // this special case allows the compiler to make `.filter(_).count()`
+     // branchless. Barring perfect branch prediction (which is unattainable in
+     // the general case), this will be much faster in >90% of cases (containing
+     // virtually all real workloads) and only a tiny bit slower in the rest.
+     //
+     // Having this specialization thus allows us to write `.filter(p).count()`
+     // where we would otherwise write `.map(|x| p(x) as usize).sum()`, which is
+     // less readable and also less backwards-compatible to Rust before 1.10.
+     //
+     // Using the branchless version will also simplify the LLVM byte code, thus
+     // leaving more budget for LLVM optimizations.
+     #[inline]
+     fn count(self) -> usize {
+         #[inline]
+         fn to_usize<T>(mut predicate: impl FnMut(&T) -> bool) -> impl FnMut(T) -> usize {
+             move |x| predicate(&x) as usize
+         }
+ 
+         self.iter.map(to_usize(self.predicate)).sum()
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_fold(init, filter_try_fold(&mut self.predicate, fold))
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.fold(init, filter_fold(self.predicate, fold))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: DoubleEndedIterator, P> DoubleEndedIterator for Filter<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<I::Item> {
+         self.iter.rfind(&mut self.predicate)
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_rfold(init, filter_try_fold(&mut self.predicate, fold))
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.rfold(init, filter_fold(self.predicate, fold))
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I: FusedIterator, P> FusedIterator for Filter<I, P> where P: FnMut(&I::Item) -> bool {}
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, P, I: Iterator> SourceIter for Filter<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable, P> InPlaceIterable for Filter<I, P> where P: FnMut(&I::Item) -> bool {}
+ 
+ /// An iterator that uses `f` to both filter and map elements from `iter`.
+ ///
+ /// This `struct` is created by the [`filter_map`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`filter_map`]: Iterator::filter_map
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct FilterMap<I, F> {
+     iter: I,
+     f: F,
+ }
+ impl<I, F> FilterMap<I, F> {
+     pub(super) fn new(iter: I, f: F) -> FilterMap<I, F> {
+         FilterMap { iter, f }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, F> fmt::Debug for FilterMap<I, F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("FilterMap").field("iter", &self.iter).finish()
+     }
+ }
+ 
+ fn filter_map_fold<T, B, Acc>(
+     mut f: impl FnMut(T) -> Option<B>,
+     mut fold: impl FnMut(Acc, B) -> Acc,
+ ) -> impl FnMut(Acc, T) -> Acc {
+     move |acc, item| match f(item) {
+         Some(x) => fold(acc, x),
+         None => acc,
+     }
+ }
+ 
+ fn filter_map_try_fold<'a, T, B, Acc, R: Try<Ok = Acc>>(
+     f: &'a mut impl FnMut(T) -> Option<B>,
+     mut fold: impl FnMut(Acc, B) -> R + 'a,
+ ) -> impl FnMut(Acc, T) -> R + 'a {
+     move |acc, item| match f(item) {
+         Some(x) => fold(acc, x),
+         None => try { acc },
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<B, I: Iterator, F> Iterator for FilterMap<I, F>
+ where
+     F: FnMut(I::Item) -> Option<B>,
+ {
+     type Item = B;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<B> {
+         self.iter.find_map(&mut self.f)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (_, upper) = self.iter.size_hint();
+         (0, upper) // can't know a lower bound, due to the predicate
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_fold(init, filter_map_try_fold(&mut self.f, fold))
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.fold(init, filter_map_fold(self.f, fold))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<B, I: DoubleEndedIterator, F> DoubleEndedIterator for FilterMap<I, F>
+ where
+     F: FnMut(I::Item) -> Option<B>,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<B> {
+         #[inline]
+         fn find<T, B>(
+             f: &mut impl FnMut(T) -> Option<B>,
+         ) -> impl FnMut((), T) -> ControlFlow<B> + '_ {
+             move |(), x| match f(x) {
+                 Some(x) => ControlFlow::Break(x),
+                 None => ControlFlow::CONTINUE,
+             }
+         }
+ 
+         self.iter.try_rfold((), find(&mut self.f)).break_value()
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_rfold(init, filter_map_try_fold(&mut self.f, fold))
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.rfold(init, filter_map_fold(self.f, fold))
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<B, I: FusedIterator, F> FusedIterator for FilterMap<I, F> where F: FnMut(I::Item) -> Option<B> {}
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, B, I: Iterator, F> SourceIter for FilterMap<I, F>
+ where
+     F: FnMut(I::Item) -> Option<B>,
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<B, I: InPlaceIterable, F> InPlaceIterable for FilterMap<I, F> where
+     F: FnMut(I::Item) -> Option<B>
+ {
+ }
+ 
+ /// An iterator that yields the current count and the element during iteration.
+ ///
+ /// This `struct` is created by the [`enumerate`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`enumerate`]: Iterator::enumerate
+ /// [`Iterator`]: trait.Iterator.html
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Enumerate<I> {
+     iter: I,
+     count: usize,
+ }
+ impl<I> Enumerate<I> {
+     pub(super) fn new(iter: I) -> Enumerate<I> {
+         Enumerate { iter, count: 0 }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> Iterator for Enumerate<I>
+ where
+     I: Iterator,
+ {
+     type Item = (usize, <I as Iterator>::Item);
+ 
+     /// # Overflow Behavior
+     ///
+     /// The method does no guarding against overflows, so enumerating more than
+     /// `usize::MAX` elements either produces the wrong result or panics. If
+     /// debug assertions are enabled, a panic is guaranteed.
+     ///
+     /// # Panics
+     ///
+     /// Might panic if the index of the element overflows a `usize`.
+     #[inline]
+     fn next(&mut self) -> Option<(usize, <I as Iterator>::Item)> {
+         let a = self.iter.next()?;
+         let i = self.count;
+         // Possible undefined overflow.
+         AddAssign::add_assign(&mut self.count, 1);
+         Some((i, a))
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<(usize, I::Item)> {
+         let a = self.iter.nth(n)?;
+         // Possible undefined overflow.
+         let i = Add::add(self.count, n);
+         self.count = Add::add(i, 1);
+         Some((i, a))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.iter.count()
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         #[inline]
+         fn enumerate<'a, T, Acc, R>(
+             count: &'a mut usize,
+             mut fold: impl FnMut(Acc, (usize, T)) -> R + 'a,
+         ) -> impl FnMut(Acc, T) -> R + 'a {
+             move |acc, item| {
+                 let acc = fold(acc, (*count, item));
+                 // Possible undefined overflow.
+                 AddAssign::add_assign(count, 1);
+                 acc
+             }
+         }
+ 
+         self.iter.try_fold(init, enumerate(&mut self.count, fold))
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn enumerate<T, Acc>(
+             mut count: usize,
+             mut fold: impl FnMut(Acc, (usize, T)) -> Acc,
+         ) -> impl FnMut(Acc, T) -> Acc {
+             move |acc, item| {
+                 let acc = fold(acc, (count, item));
+                 // Possible undefined overflow.
+                 AddAssign::add_assign(&mut count, 1);
+                 acc
+             }
+         }
+ 
+         self.iter.fold(init, enumerate(self.count, fold))
+     }
+ 
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> <Self as Iterator>::Item
+     where
+         Self: TrustedRandomAccess,
+     {
+         // SAFETY: the caller must uphold the contract for
+         // `Iterator::__iterator_get_unchecked`.
+         let value = unsafe { try_get_unchecked(&mut self.iter, idx) };
+         (Add::add(self.count, idx), value)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> DoubleEndedIterator for Enumerate<I>
+ where
+     I: ExactSizeIterator + DoubleEndedIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<(usize, <I as Iterator>::Item)> {
+         let a = self.iter.next_back()?;
+         let len = self.iter.len();
+         // Can safely add, `ExactSizeIterator` promises that the number of
+         // elements fits into a `usize`.
+         Some((self.count + len, a))
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<(usize, <I as Iterator>::Item)> {
+         let a = self.iter.nth_back(n)?;
+         let len = self.iter.len();
+         // Can safely add, `ExactSizeIterator` promises that the number of
+         // elements fits into a `usize`.
+         Some((self.count + len, a))
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         // Can safely add and subtract the count, as `ExactSizeIterator` promises
+         // that the number of elements fits into a `usize`.
+         fn enumerate<T, Acc, R>(
+             mut count: usize,
+             mut fold: impl FnMut(Acc, (usize, T)) -> R,
+         ) -> impl FnMut(Acc, T) -> R {
+             move |acc, item| {
+                 count -= 1;
+                 fold(acc, (count, item))
+             }
+         }
+ 
+         let count = self.count + self.iter.len();
+         self.iter.try_rfold(init, enumerate(count, fold))
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         // Can safely add and subtract the count, as `ExactSizeIterator` promises
+         // that the number of elements fits into a `usize`.
+         fn enumerate<T, Acc>(
+             mut count: usize,
+             mut fold: impl FnMut(Acc, (usize, T)) -> Acc,
+         ) -> impl FnMut(Acc, T) -> Acc {
+             move |acc, item| {
+                 count -= 1;
+                 fold(acc, (count, item))
+             }
+         }
+ 
+         let count = self.count + self.iter.len();
+         self.iter.rfold(init, enumerate(count, fold))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ExactSizeIterator for Enumerate<I>
+ where
+     I: ExactSizeIterator,
+ {
+     fn len(&self) -> usize {
+         self.iter.len()
+     }
+ 
+     fn is_empty(&self) -> bool {
+         self.iter.is_empty()
+     }
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<I> TrustedRandomAccess for Enumerate<I>
+ where
+     I: TrustedRandomAccess,
+ {
+     fn may_have_side_effect() -> bool {
+         I::may_have_side_effect()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I> FusedIterator for Enumerate<I> where I: FusedIterator {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<I> TrustedLen for Enumerate<I> where I: TrustedLen {}
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, I: Iterator> SourceIter for Enumerate<I>
+ where
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable> InPlaceIterable for Enumerate<I> {}
+ 
+ /// An iterator with a `peek()` that returns an optional reference to the next
+ /// element.
+ ///
+ /// This `struct` is created by the [`peekable`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`peekable`]: Iterator::peekable
+ /// [`Iterator`]: trait.Iterator.html
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Peekable<I: Iterator> {
+     iter: I,
+     /// Remember a peeked value, even if it was None.
+     peeked: Option<Option<I::Item>>,
+ }
+ impl<I: Iterator> Peekable<I> {
+     pub(super) fn new(iter: I) -> Peekable<I> {
+         Peekable { iter, peeked: None }
+     }
+ }
+ 
+ // Peekable must remember if a None has been seen in the `.peek()` method.
+ // It ensures that `.peek(); .peek();` or `.peek(); .next();` only advances the
+ // underlying iterator at most once. This does not by itself make the iterator
+ // fused.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator> Iterator for Peekable<I> {
+     type Item = I::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<I::Item> {
+         match self.peeked.take() {
+             Some(v) => v,
+             None => self.iter.next(),
+         }
+     }
+ 
+     #[inline]
+     #[rustc_inherit_overflow_checks]
+     fn count(mut self) -> usize {
+         match self.peeked.take() {
+             Some(None) => 0,
+             Some(Some(_)) => 1 + self.iter.count(),
+             None => self.iter.count(),
+         }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<I::Item> {
+         match self.peeked.take() {
+             Some(None) => None,
+             Some(v @ Some(_)) if n == 0 => v,
+             Some(Some(_)) => self.iter.nth(n - 1),
+             None => self.iter.nth(n),
+         }
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<I::Item> {
+         let peek_opt = match self.peeked.take() {
+             Some(None) => return None,
+             Some(v) => v,
+             None => None,
+         };
+         self.iter.last().or(peek_opt)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let peek_len = match self.peeked {
+             Some(None) => return (0, Some(0)),
+             Some(Some(_)) => 1,
+             None => 0,
+         };
+         let (lo, hi) = self.iter.size_hint();
+         let lo = lo.saturating_add(peek_len);
+         let hi = match hi {
+             Some(x) => x.checked_add(peek_len),
+             None => None,
+         };
+         (lo, hi)
+     }
+ 
+     #[inline]
+     fn try_fold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         let acc = match self.peeked.take() {
+             Some(None) => return try { init },
+             Some(Some(v)) => f(init, v)?,
+             None => init,
+         };
+         self.iter.try_fold(acc, f)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, mut fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         let acc = match self.peeked {
+             Some(None) => return init,
+             Some(Some(v)) => fold(init, v),
+             None => init,
+         };
+         self.iter.fold(acc, fold)
+     }
+ }
+ 
+ #[stable(feature = "double_ended_peek_iterator", since = "1.38.0")]
+ impl<I> DoubleEndedIterator for Peekable<I>
+ where
+     I: DoubleEndedIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<Self::Item> {
+         match self.peeked.as_mut() {
+             Some(v @ Some(_)) => self.iter.next_back().or_else(|| v.take()),
+             Some(None) => None,
+             None => self.iter.next_back(),
+         }
+     }
+ 
+     #[inline]
+     fn try_rfold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         match self.peeked.take() {
+             Some(None) => try { init },
+             Some(Some(v)) => match self.iter.try_rfold(init, &mut f).into_result() {
+                 Ok(acc) => f(acc, v),
+                 Err(e) => {
+                     self.peeked = Some(Some(v));
+                     Try::from_error(e)
+                 }
+             },
+             None => self.iter.try_rfold(init, f),
+         }
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, mut fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         match self.peeked {
+             Some(None) => init,
+             Some(Some(v)) => {
+                 let acc = self.iter.rfold(init, &mut fold);
+                 fold(acc, v)
+             }
+             None => self.iter.rfold(init, fold),
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: ExactSizeIterator> ExactSizeIterator for Peekable<I> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I: FusedIterator> FusedIterator for Peekable<I> {}
+ 
+ impl<I: Iterator> Peekable<I> {
+     /// Returns a reference to the next() value without advancing the iterator.
+     ///
+     /// Like [`next`], if there is a value, it is wrapped in a `Some(T)`.
+     /// But if the iteration is over, `None` is returned.
+     ///
+     /// [`next`]: Iterator::next
+     ///
+     /// Because `peek()` returns a reference, and many iterators iterate over
+     /// references, there can be a possibly confusing situation where the
+     /// return value is a double reference. You can see this effect in the
+     /// examples below.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let xs = [1, 2, 3];
+     ///
+     /// let mut iter = xs.iter().peekable();
+     ///
+     /// // peek() lets us see into the future
+     /// assert_eq!(iter.peek(), Some(&&1));
+     /// assert_eq!(iter.next(), Some(&1));
+     ///
+     /// assert_eq!(iter.next(), Some(&2));
+     ///
+     /// // The iterator does not advance even if we `peek` multiple times
+     /// assert_eq!(iter.peek(), Some(&&3));
+     /// assert_eq!(iter.peek(), Some(&&3));
+     ///
+     /// assert_eq!(iter.next(), Some(&3));
+     ///
+     /// // After the iterator is finished, so is `peek()`
+     /// assert_eq!(iter.peek(), None);
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn peek(&mut self) -> Option<&I::Item> {
+         let iter = &mut self.iter;
+         self.peeked.get_or_insert_with(|| iter.next()).as_ref()
+     }
+ 
+     /// Consume and return the next value of this iterator if a condition is true.
+     ///
+     /// If `func` returns `true` for the next value of this iterator, consume and return it.
+     /// Otherwise, return `None`.
+     ///
+     /// # Examples
+     /// Consume a number if it's equal to 0.
+     /// ```
+     /// #![feature(peekable_next_if)]
+     /// let mut iter = (0..5).peekable();
+     /// // The first item of the iterator is 0; consume it.
+     /// assert_eq!(iter.next_if(|&x| x == 0), Some(0));
+     /// // The next item returned is now 1, so `consume` will return `false`.
+     /// assert_eq!(iter.next_if(|&x| x == 0), None);
+     /// // `next_if` saves the value of the next item if it was not equal to `expected`.
+     /// assert_eq!(iter.next(), Some(1));
+     /// ```
+     ///
+     /// Consume any number less than 10.
+     /// ```
+     /// #![feature(peekable_next_if)]
+     /// let mut iter = (1..20).peekable();
+     /// // Consume all numbers less than 10
+     /// while iter.next_if(|&x| x < 10).is_some() {}
+     /// // The next value returned will be 10
+     /// assert_eq!(iter.next(), Some(10));
+     /// ```
+     #[unstable(feature = "peekable_next_if", issue = "72480")]
+     pub fn next_if(&mut self, func: impl FnOnce(&I::Item) -> bool) -> Option<I::Item> {
+         match self.next() {
+             Some(matched) if func(&matched) => Some(matched),
+             other => {
+                 // Since we called `self.next()`, we consumed `self.peeked`.
+                 assert!(self.peeked.is_none());
+                 self.peeked = Some(other);
+                 None
+             }
+         }
+     }
+ 
+     /// Consume and return the next item if it is equal to `expected`.
+     ///
+     /// # Example
+     /// Consume a number if it's equal to 0.
+     /// ```
+     /// #![feature(peekable_next_if)]
+     /// let mut iter = (0..5).peekable();
+     /// // The first item of the iterator is 0; consume it.
+     /// assert_eq!(iter.next_if_eq(&0), Some(0));
+     /// // The next item returned is now 1, so `consume` will return `false`.
+     /// assert_eq!(iter.next_if_eq(&0), None);
+     /// // `next_if_eq` saves the value of the next item if it was not equal to `expected`.
+     /// assert_eq!(iter.next(), Some(1));
+     /// ```
+     #[unstable(feature = "peekable_next_if", issue = "72480")]
+     pub fn next_if_eq<T>(&mut self, expected: &T) -> Option<I::Item>
+     where
+         T: ?Sized,
+         I::Item: PartialEq<T>,
+     {
+         self.next_if(|next| next == expected)
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<I> TrustedLen for Peekable<I> where I: TrustedLen {}
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, I: Iterator> SourceIter for Peekable<I>
+ where
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable> InPlaceIterable for Peekable<I> {}
+ 
+ /// An iterator that rejects elements while `predicate` returns `true`.
+ ///
+ /// This `struct` is created by the [`skip_while`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`skip_while`]: Iterator::skip_while
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct SkipWhile<I, P> {
+     iter: I,
+     flag: bool,
+     predicate: P,
+ }
+ impl<I, P> SkipWhile<I, P> {
+     pub(super) fn new(iter: I, predicate: P) -> SkipWhile<I, P> {
+         SkipWhile { iter, flag: false, predicate }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, P> fmt::Debug for SkipWhile<I, P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SkipWhile").field("iter", &self.iter).field("flag", &self.flag).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator, P> Iterator for SkipWhile<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+ {
+     type Item = I::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<I::Item> {
+         fn check<'a, T>(
+             flag: &'a mut bool,
+             pred: &'a mut impl FnMut(&T) -> bool,
+         ) -> impl FnMut(&T) -> bool + 'a {
+             move |x| {
+                 if *flag || !pred(x) {
+                     *flag = true;
+                     true
+                 } else {
+                     false
+                 }
+             }
+         }
+ 
+         let flag = &mut self.flag;
+         let pred = &mut self.predicate;
+         self.iter.find(check(flag, pred))
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (_, upper) = self.iter.size_hint();
+         (0, upper) // can't know a lower bound, due to the predicate
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, mut init: Acc, mut fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         if !self.flag {
+             match self.next() {
+                 Some(v) => init = fold(init, v)?,
+                 None => return try { init },
+             }
+         }
+         self.iter.try_fold(init, fold)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(mut self, mut init: Acc, mut fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         if !self.flag {
+             match self.next() {
+                 Some(v) => init = fold(init, v),
+                 None => return init,
+             }
+         }
+         self.iter.fold(init, fold)
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I, P> FusedIterator for SkipWhile<I, P>
+ where
+     I: FusedIterator,
+     P: FnMut(&I::Item) -> bool,
+ {
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, P, I: Iterator> SourceIter for SkipWhile<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable, F> InPlaceIterable for SkipWhile<I, F> where
+     F: FnMut(&I::Item) -> bool
+ {
+ }
+ 
+ /// An iterator that only accepts elements while `predicate` returns `true`.
+ ///
+ /// This `struct` is created by the [`take_while`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`take_while`]: Iterator::take_while
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct TakeWhile<I, P> {
+     iter: I,
+     flag: bool,
+     predicate: P,
+ }
+ impl<I, P> TakeWhile<I, P> {
+     pub(super) fn new(iter: I, predicate: P) -> TakeWhile<I, P> {
+         TakeWhile { iter, flag: false, predicate }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, P> fmt::Debug for TakeWhile<I, P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("TakeWhile").field("iter", &self.iter).field("flag", &self.flag).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator, P> Iterator for TakeWhile<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+ {
+     type Item = I::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<I::Item> {
+         if self.flag {
+             None
+         } else {
+             let x = self.iter.next()?;
+             if (self.predicate)(&x) {
+                 Some(x)
+             } else {
+                 self.flag = true;
+                 None
+             }
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.flag {
+             (0, Some(0))
+         } else {
+             let (_, upper) = self.iter.size_hint();
+             (0, upper) // can't know a lower bound, due to the predicate
+         }
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         fn check<'a, T, Acc, R: Try<Ok = Acc>>(
+             flag: &'a mut bool,
+             p: &'a mut impl FnMut(&T) -> bool,
+             mut fold: impl FnMut(Acc, T) -> R + 'a,
+         ) -> impl FnMut(Acc, T) -> ControlFlow<R, Acc> + 'a {
+             move |acc, x| {
+                 if p(&x) {
+                     ControlFlow::from_try(fold(acc, x))
+                 } else {
+                     *flag = true;
+                     ControlFlow::Break(try { acc })
+                 }
+             }
+         }
+ 
+         if self.flag {
+             try { init }
+         } else {
+             let flag = &mut self.flag;
+             let p = &mut self.predicate;
+             self.iter.try_fold(init, check(flag, p, fold)).into_try()
+         }
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_fold(init, ok(fold)).unwrap()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I, P> FusedIterator for TakeWhile<I, P>
+ where
+     I: FusedIterator,
+     P: FnMut(&I::Item) -> bool,
+ {
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, P, I: Iterator> SourceIter for TakeWhile<I, P>
+ where
+     P: FnMut(&I::Item) -> bool,
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable, F> InPlaceIterable for TakeWhile<I, F> where
+     F: FnMut(&I::Item) -> bool
+ {
+ }
+ 
+ /// An iterator that only accepts elements while `predicate` returns `Some(_)`.
+ ///
+ /// This `struct` is created by the [`map_while`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`map_while`]: Iterator::map_while
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[unstable(feature = "iter_map_while", reason = "recently added", issue = "68537")]
+ #[derive(Clone)]
+ pub struct MapWhile<I, P> {
+     iter: I,
+     predicate: P,
+ }
+ 
+ impl<I, P> MapWhile<I, P> {
+     pub(super) fn new(iter: I, predicate: P) -> MapWhile<I, P> {
+         MapWhile { iter, predicate }
+     }
+ }
+ 
+ #[unstable(feature = "iter_map_while", reason = "recently added", issue = "68537")]
+ impl<I: fmt::Debug, P> fmt::Debug for MapWhile<I, P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("MapWhile").field("iter", &self.iter).finish()
+     }
+ }
+ 
+ #[unstable(feature = "iter_map_while", reason = "recently added", issue = "68537")]
+ impl<B, I: Iterator, P> Iterator for MapWhile<I, P>
+ where
+     P: FnMut(I::Item) -> Option<B>,
+ {
+     type Item = B;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<B> {
+         let x = self.iter.next()?;
+         (self.predicate)(x)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (_, upper) = self.iter.size_hint();
+         (0, upper) // can't know a lower bound, due to the predicate
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, mut fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         let Self { iter, predicate } = self;
+         iter.try_fold(init, |acc, x| match predicate(x) {
+             Some(item) => ControlFlow::from_try(fold(acc, item)),
+             None => ControlFlow::Break(try { acc }),
+         })
+         .into_try()
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_fold(init, ok(fold)).unwrap()
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, B, I: Iterator, P> SourceIter for MapWhile<I, P>
+ where
+     P: FnMut(I::Item) -> Option<B>,
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<B, I: InPlaceIterable, P> InPlaceIterable for MapWhile<I, P> where
+     P: FnMut(I::Item) -> Option<B>
+ {
+ }
+ 
+ /// An iterator that skips over `n` elements of `iter`.
+ ///
+ /// This `struct` is created by the [`skip`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`skip`]: Iterator::skip
+ /// [`Iterator`]: trait.Iterator.html
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Skip<I> {
+     iter: I,
+     n: usize,
+ }
+ impl<I> Skip<I> {
+     pub(super) fn new(iter: I, n: usize) -> Skip<I> {
+         Skip { iter, n }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> Iterator for Skip<I>
+ where
+     I: Iterator,
+ {
+     type Item = <I as Iterator>::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<I::Item> {
+         if self.n == 0 {
+             self.iter.next()
+         } else {
+             let old_n = self.n;
+             self.n = 0;
+             self.iter.nth(old_n)
+         }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<I::Item> {
+         // Can't just add n + self.n due to overflow.
+         if self.n > 0 {
+             let to_skip = self.n;
+             self.n = 0;
+             // nth(n) skips n+1
+             self.iter.nth(to_skip - 1)?;
+         }
+         self.iter.nth(n)
+     }
+ 
+     #[inline]
+     fn count(mut self) -> usize {
+         if self.n > 0 {
+             // nth(n) skips n+1
+             if self.iter.nth(self.n - 1).is_none() {
+                 return 0;
+             }
+         }
+         self.iter.count()
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<I::Item> {
+         if self.n > 0 {
+             // nth(n) skips n+1
+             self.iter.nth(self.n - 1)?;
+         }
+         self.iter.last()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (lower, upper) = self.iter.size_hint();
+ 
+         let lower = lower.saturating_sub(self.n);
+         let upper = match upper {
+             Some(x) => Some(x.saturating_sub(self.n)),
+             None => None,
+         };
+ 
+         (lower, upper)
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         let n = self.n;
+         self.n = 0;
+         if n > 0 {
+             // nth(n) skips n+1
+             if self.iter.nth(n - 1).is_none() {
+                 return try { init };
+             }
+         }
+         self.iter.try_fold(init, fold)
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         if self.n > 0 {
+             // nth(n) skips n+1
+             if self.iter.nth(self.n - 1).is_none() {
+                 return init;
+             }
+         }
+         self.iter.fold(init, fold)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ExactSizeIterator for Skip<I> where I: ExactSizeIterator {}
+ 
+ #[stable(feature = "double_ended_skip_iterator", since = "1.9.0")]
+ impl<I> DoubleEndedIterator for Skip<I>
+ where
+     I: DoubleEndedIterator + ExactSizeIterator,
+ {
+     fn next_back(&mut self) -> Option<Self::Item> {
+         if self.len() > 0 { self.iter.next_back() } else { None }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<I::Item> {
+         let len = self.len();
+         if n < len {
+             self.iter.nth_back(n)
+         } else {
+             if len > 0 {
+                 // consume the original iterator
+                 self.iter.nth_back(len - 1);
+             }
+             None
+         }
+     }
+ 
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         fn check<T, Acc, R: Try<Ok = Acc>>(
+             mut n: usize,
+             mut fold: impl FnMut(Acc, T) -> R,
+         ) -> impl FnMut(Acc, T) -> ControlFlow<R, Acc> {
+             move |acc, x| {
+                 n -= 1;
+                 let r = fold(acc, x);
+                 if n == 0 { ControlFlow::Break(r) } else { ControlFlow::from_try(r) }
+             }
+         }
+ 
+         let n = self.len();
+         if n == 0 { try { init } } else { self.iter.try_rfold(init, check(n, fold)).into_try() }
+     }
+ 
+     fn rfold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn ok<Acc, T>(mut f: impl FnMut(Acc, T) -> Acc) -> impl FnMut(Acc, T) -> Result<Acc, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_rfold(init, ok(fold)).unwrap()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I> FusedIterator for Skip<I> where I: FusedIterator {}
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, I: Iterator> SourceIter for Skip<I>
+ where
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable> InPlaceIterable for Skip<I> {}
+ 
+ /// An iterator that only iterates over the first `n` iterations of `iter`.
+ ///
+ /// This `struct` is created by the [`take`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`take`]: Iterator::take
+ /// [`Iterator`]: trait.Iterator.html
+ #[derive(Clone, Debug)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Take<I> {
+     pub(super) iter: I,
+     pub(super) n: usize,
+ }
+ impl<I> Take<I> {
+     pub(super) fn new(iter: I, n: usize) -> Take<I> {
+         Take { iter, n }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> Iterator for Take<I>
+ where
+     I: Iterator,
+ {
+     type Item = <I as Iterator>::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<<I as Iterator>::Item> {
+         if self.n != 0 {
+             self.n -= 1;
+             self.iter.next()
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<I::Item> {
+         if self.n > n {
+             self.n -= n + 1;
+             self.iter.nth(n)
+         } else {
+             if self.n > 0 {
+                 self.iter.nth(self.n - 1);
+                 self.n = 0;
+             }
+             None
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.n == 0 {
+             return (0, Some(0));
+         }
+ 
+         let (lower, upper) = self.iter.size_hint();
+ 
+         let lower = cmp::min(lower, self.n);
+ 
+         let upper = match upper {
+             Some(x) if x < self.n => Some(x),
+             _ => Some(self.n),
+         };
+ 
+         (lower, upper)
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         fn check<'a, T, Acc, R: Try<Ok = Acc>>(
+             n: &'a mut usize,
+             mut fold: impl FnMut(Acc, T) -> R + 'a,
+         ) -> impl FnMut(Acc, T) -> ControlFlow<R, Acc> + 'a {
+             move |acc, x| {
+                 *n -= 1;
+                 let r = fold(acc, x);
+                 if *n == 0 { ControlFlow::Break(r) } else { ControlFlow::from_try(r) }
+             }
+         }
+ 
+         if self.n == 0 {
+             try { init }
+         } else {
+             let n = &mut self.n;
+             self.iter.try_fold(init, check(n, fold)).into_try()
+         }
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_fold(init, ok(fold)).unwrap()
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, I: Iterator> SourceIter for Take<I>
+ where
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable> InPlaceIterable for Take<I> {}
+ 
+ #[stable(feature = "double_ended_take_iterator", since = "1.38.0")]
+ impl<I> DoubleEndedIterator for Take<I>
+ where
+     I: DoubleEndedIterator + ExactSizeIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<Self::Item> {
+         if self.n == 0 {
+             None
+         } else {
+             let n = self.n;
+             self.n -= 1;
+             self.iter.nth_back(self.iter.len().saturating_sub(n))
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.iter.len();
+         if self.n > n {
+             let m = len.saturating_sub(self.n) + n;
+             self.n -= n + 1;
+             self.iter.nth_back(m)
+         } else {
+             if len > 0 {
+                 self.iter.nth_back(len - 1);
+             }
+             None
+         }
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         if self.n == 0 {
+             try { init }
+         } else {
+             let len = self.iter.len();
+             if len > self.n && self.iter.nth_back(len - self.n - 1).is_none() {
+                 try { init }
+             } else {
+                 self.iter.try_rfold(init, fold)
+             }
+         }
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         if self.n == 0 {
+             init
+         } else {
+             let len = self.iter.len();
+             if len > self.n && self.iter.nth_back(len - self.n - 1).is_none() {
+                 init
+             } else {
+                 self.iter.rfold(init, fold)
+             }
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ExactSizeIterator for Take<I> where I: ExactSizeIterator {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I> FusedIterator for Take<I> where I: FusedIterator {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<I: TrustedLen> TrustedLen for Take<I> {}
+ 
+ /// An iterator to maintain state while iterating another iterator.
+ ///
+ /// This `struct` is created by the [`scan`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`scan`]: Iterator::scan
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct Scan<I, St, F> {
+     iter: I,
+     f: F,
+     state: St,
+ }
+ impl<I, St, F> Scan<I, St, F> {
+     pub(super) fn new(iter: I, state: St, f: F) -> Scan<I, St, F> {
+         Scan { iter, state, f }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, St: fmt::Debug, F> fmt::Debug for Scan<I, St, F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Scan").field("iter", &self.iter).field("state", &self.state).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<B, I, St, F> Iterator for Scan<I, St, F>
+ where
+     I: Iterator,
+     F: FnMut(&mut St, I::Item) -> Option<B>,
+ {
+     type Item = B;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<B> {
+         let a = self.iter.next()?;
+         (self.f)(&mut self.state, a)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (_, upper) = self.iter.size_hint();
+         (0, upper) // can't know a lower bound, due to the scan function
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         fn scan<'a, T, St, B, Acc, R: Try<Ok = Acc>>(
+             state: &'a mut St,
+             f: &'a mut impl FnMut(&mut St, T) -> Option<B>,
+             mut fold: impl FnMut(Acc, B) -> R + 'a,
+         ) -> impl FnMut(Acc, T) -> ControlFlow<R, Acc> + 'a {
+             move |acc, x| match f(state, x) {
+                 None => ControlFlow::Break(try { acc }),
+                 Some(x) => ControlFlow::from_try(fold(acc, x)),
+             }
+         }
+ 
+         let state = &mut self.state;
+         let f = &mut self.f;
+         self.iter.try_fold(init, scan(state, f, fold)).into_try()
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(mut self, init: Acc, fold: Fold) -> Acc
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_fold(init, ok(fold)).unwrap()
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<St, F, B, S: Iterator, I: Iterator> SourceIter for Scan<I, St, F>
+ where
+     I: SourceIter<Source = S>,
+     F: FnMut(&mut St, I::Item) -> Option<B>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<St, F, B, I: InPlaceIterable> InPlaceIterable for Scan<I, St, F> where
+     F: FnMut(&mut St, I::Item) -> Option<B>
+ {
+ }
+ 
+ /// An iterator that calls a function with a reference to each element before
+ /// yielding it.
+ ///
+ /// This `struct` is created by the [`inspect`] method on [`Iterator`]. See its
+ /// documentation for more.
+ ///
+ /// [`inspect`]: Iterator::inspect
+ /// [`Iterator`]: trait.Iterator.html
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone)]
+ pub struct Inspect<I, F> {
+     iter: I,
+     f: F,
+ }
+ impl<I, F> Inspect<I, F> {
+     pub(super) fn new(iter: I, f: F) -> Inspect<I, F> {
+         Inspect { iter, f }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<I: fmt::Debug, F> fmt::Debug for Inspect<I, F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Inspect").field("iter", &self.iter).finish()
+     }
+ }
+ 
+ impl<I: Iterator, F> Inspect<I, F>
+ where
+     F: FnMut(&I::Item),
+ {
+     #[inline]
+     fn do_inspect(&mut self, elt: Option<I::Item>) -> Option<I::Item> {
+         if let Some(ref a) = elt {
+             (self.f)(a);
+         }
+ 
+         elt
+     }
+ }
+ 
+ fn inspect_fold<T, Acc>(
+     mut f: impl FnMut(&T),
+     mut fold: impl FnMut(Acc, T) -> Acc,
+ ) -> impl FnMut(Acc, T) -> Acc {
+     move |acc, item| {
+         f(&item);
+         fold(acc, item)
+     }
+ }
+ 
+ fn inspect_try_fold<'a, T, Acc, R>(
+     f: &'a mut impl FnMut(&T),
+     mut fold: impl FnMut(Acc, T) -> R + 'a,
+ ) -> impl FnMut(Acc, T) -> R + 'a {
+     move |acc, item| {
+         f(&item);
+         fold(acc, item)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator, F> Iterator for Inspect<I, F>
+ where
+     F: FnMut(&I::Item),
+ {
+     type Item = I::Item;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<I::Item> {
+         let next = self.iter.next();
+         self.do_inspect(next)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     #[inline]
+     fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_fold(init, inspect_try_fold(&mut self.f, fold))
+     }
+ 
+     #[inline]
+     fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.fold(init, inspect_fold(self.f, fold))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: DoubleEndedIterator, F> DoubleEndedIterator for Inspect<I, F>
+ where
+     F: FnMut(&I::Item),
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<I::Item> {
+         let next = self.iter.next_back();
+         self.do_inspect(next)
+     }
+ 
+     #[inline]
+     fn try_rfold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R
+     where
+         Self: Sized,
+         Fold: FnMut(Acc, Self::Item) -> R,
+         R: Try<Ok = Acc>,
+     {
+         self.iter.try_rfold(init, inspect_try_fold(&mut self.f, fold))
+     }
+ 
+     #[inline]
+     fn rfold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+     where
+         Fold: FnMut(Acc, Self::Item) -> Acc,
+     {
+         self.iter.rfold(init, inspect_fold(self.f, fold))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: ExactSizeIterator, F> ExactSizeIterator for Inspect<I, F>
+ where
+     F: FnMut(&I::Item),
+ {
+     fn len(&self) -> usize {
+         self.iter.len()
+     }
+ 
+     fn is_empty(&self) -> bool {
+         self.iter.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I: FusedIterator, F> FusedIterator for Inspect<I, F> where F: FnMut(&I::Item) {}
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S: Iterator, I: Iterator, F> SourceIter for Inspect<I, F>
+ where
+     F: FnMut(&I::Item),
+     I: SourceIter<Source = S>,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.iter) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<I: InPlaceIterable, F> InPlaceIterable for Inspect<I, F> where F: FnMut(&I::Item) {}
+ 
+ /// An iterator adapter that produces output as long as the underlying
+ /// iterator produces `Result::Ok` values.
+ ///
+ /// If an error is encountered, the iterator stops and the error is
+ /// stored.
+ pub(crate) struct ResultShunt<'a, I, E> {
+     iter: I,
+     error: &'a mut Result<(), E>,
+ }
+ 
+ /// Process the given iterator as if it yielded a `T` instead of a
+ /// `Result<T, _>`. Any errors will stop the inner iterator and
+ /// the overall result will be an error.
+ pub(crate) fn process_results<I, T, E, F, U>(iter: I, mut f: F) -> Result<U, E>
+ where
+     I: Iterator<Item = Result<T, E>>,
+     for<'a> F: FnMut(ResultShunt<'a, I, E>) -> U,
+ {
+     let mut error = Ok(());
+     let shunt = ResultShunt { iter, error: &mut error };
+     let value = f(shunt);
+     error.map(|()| value)
+ }
+ 
+ impl<I, T, E> Iterator for ResultShunt<'_, I, E>
+ where
+     I: Iterator<Item = Result<T, E>>,
+ {
+     type Item = T;
+ 
+     fn next(&mut self) -> Option<Self::Item> {
+         self.find(|_| true)
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.error.is_err() {
+             (0, Some(0))
+         } else {
+             let (_, upper) = self.iter.size_hint();
+             (0, upper)
+         }
+     }
+ 
+     fn try_fold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         let error = &mut *self.error;
+         self.iter
+             .try_fold(init, |acc, x| match x {
+                 Ok(x) => ControlFlow::from_try(f(acc, x)),
+                 Err(e) => {
+                     *error = Err(e);
+                     ControlFlow::Break(try { acc })
+                 }
+             })
+             .into_try()
+     }
+ 
+     fn fold<B, F>(mut self, init: B, fold: F) -> B
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> B,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_fold(init, ok(fold)).unwrap()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/zip.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/zip.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/adapters/zip.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/adapters/zip.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,465 ----
+ use crate::cmp;
+ use crate::fmt::{self, Debug};
+ 
+ use super::super::{
+     DoubleEndedIterator, ExactSizeIterator, FusedIterator, InPlaceIterable, Iterator, SourceIter,
+     TrustedLen,
+ };
+ 
+ /// An iterator that iterates two other iterators simultaneously.
+ ///
+ /// This `struct` is created by [`Iterator::zip`]. See its documentation
+ /// for more.
+ #[derive(Clone)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Zip<A, B> {
+     a: A,
+     b: B,
+     // index and len are only used by the specialized version of zip
+     index: usize,
+     len: usize,
+ }
+ impl<A: Iterator, B: Iterator> Zip<A, B> {
+     pub(in super::super) fn new(a: A, b: B) -> Zip<A, B> {
+         ZipImpl::new(a, b)
+     }
+     fn super_nth(&mut self, mut n: usize) -> Option<(A::Item, B::Item)> {
+         while let Some(x) = Iterator::next(self) {
+             if n == 0 {
+                 return Some(x);
+             }
+             n -= 1;
+         }
+         None
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B> Iterator for Zip<A, B>
+ where
+     A: Iterator,
+     B: Iterator,
+ {
+     type Item = (A::Item, B::Item);
+ 
+     #[inline]
+     fn next(&mut self) -> Option<Self::Item> {
+         ZipImpl::next(self)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         ZipImpl::size_hint(self)
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         ZipImpl::nth(self, n)
+     }
+ 
+     #[inline]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item
+     where
+         Self: TrustedRandomAccess,
+     {
+         // SAFETY: `ZipImpl::__iterator_get_unchecked` has same safety
+         // requirements as `Iterator::__iterator_get_unchecked`.
+         unsafe { ZipImpl::get_unchecked(self, idx) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B> DoubleEndedIterator for Zip<A, B>
+ where
+     A: DoubleEndedIterator + ExactSizeIterator,
+     B: DoubleEndedIterator + ExactSizeIterator,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<(A::Item, B::Item)> {
+         ZipImpl::next_back(self)
+     }
+ }
+ 
+ // Zip specialization trait
+ #[doc(hidden)]
+ trait ZipImpl<A, B> {
+     type Item;
+     fn new(a: A, b: B) -> Self;
+     fn next(&mut self) -> Option<Self::Item>;
+     fn size_hint(&self) -> (usize, Option<usize>);
+     fn nth(&mut self, n: usize) -> Option<Self::Item>;
+     fn next_back(&mut self) -> Option<Self::Item>
+     where
+         A: DoubleEndedIterator + ExactSizeIterator,
+         B: DoubleEndedIterator + ExactSizeIterator;
+     // This has the same safety requirements as `Iterator::__iterator_get_unchecked`
+     unsafe fn get_unchecked(&mut self, idx: usize) -> <Self as Iterator>::Item
+     where
+         Self: Iterator + TrustedRandomAccess;
+ }
+ 
+ // General Zip impl
+ #[doc(hidden)]
+ impl<A, B> ZipImpl<A, B> for Zip<A, B>
+ where
+     A: Iterator,
+     B: Iterator,
+ {
+     type Item = (A::Item, B::Item);
+     default fn new(a: A, b: B) -> Self {
+         Zip {
+             a,
+             b,
+             index: 0, // unused
+             len: 0,   // unused
+         }
+     }
+ 
+     #[inline]
+     default fn next(&mut self) -> Option<(A::Item, B::Item)> {
+         let x = self.a.next()?;
+         let y = self.b.next()?;
+         Some((x, y))
+     }
+ 
+     #[inline]
+     default fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         self.super_nth(n)
+     }
+ 
+     #[inline]
+     default fn next_back(&mut self) -> Option<(A::Item, B::Item)>
+     where
+         A: DoubleEndedIterator + ExactSizeIterator,
+         B: DoubleEndedIterator + ExactSizeIterator,
+     {
+         let a_sz = self.a.len();
+         let b_sz = self.b.len();
+         if a_sz != b_sz {
+             // Adjust a, b to equal length
+             if a_sz > b_sz {
+                 for _ in 0..a_sz - b_sz {
+                     self.a.next_back();
+                 }
+             } else {
+                 for _ in 0..b_sz - a_sz {
+                     self.b.next_back();
+                 }
+             }
+         }
+         match (self.a.next_back(), self.b.next_back()) {
+             (Some(x), Some(y)) => Some((x, y)),
+             (None, None) => None,
+             _ => unreachable!(),
+         }
+     }
+ 
+     #[inline]
+     default fn size_hint(&self) -> (usize, Option<usize>) {
+         let (a_lower, a_upper) = self.a.size_hint();
+         let (b_lower, b_upper) = self.b.size_hint();
+ 
+         let lower = cmp::min(a_lower, b_lower);
+ 
+         let upper = match (a_upper, b_upper) {
+             (Some(x), Some(y)) => Some(cmp::min(x, y)),
+             (Some(x), None) => Some(x),
+             (None, Some(y)) => Some(y),
+             (None, None) => None,
+         };
+ 
+         (lower, upper)
+     }
+ 
+     default unsafe fn get_unchecked(&mut self, _idx: usize) -> <Self as Iterator>::Item
+     where
+         Self: TrustedRandomAccess,
+     {
+         unreachable!("Always specialized");
+     }
+ }
+ 
+ #[doc(hidden)]
+ impl<A, B> ZipImpl<A, B> for Zip<A, B>
+ where
+     A: TrustedRandomAccess + Iterator,
+     B: TrustedRandomAccess + Iterator,
+ {
+     fn new(a: A, b: B) -> Self {
+         let len = cmp::min(a.size(), b.size());
+         Zip { a, b, index: 0, len }
+     }
+ 
+     #[inline]
+     fn next(&mut self) -> Option<(A::Item, B::Item)> {
+         if self.index < self.len {
+             let i = self.index;
+             self.index += 1;
+             // SAFETY: `i` is smaller than `self.len`, thus smaller than `self.a.len()` and `self.b.len()`
+             unsafe {
+                 Some((self.a.__iterator_get_unchecked(i), self.b.__iterator_get_unchecked(i)))
+             }
+         } else if A::may_have_side_effect() && self.index < self.a.size() {
+             // match the base implementation's potential side effects
+             // SAFETY: we just checked that `self.index` < `self.a.len()`
+             unsafe {
+                 self.a.__iterator_get_unchecked(self.index);
+             }
+             self.index += 1;
+             None
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let len = self.len - self.index;
+         (len, Some(len))
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         let delta = cmp::min(n, self.len - self.index);
+         let end = self.index + delta;
+         while self.index < end {
+             let i = self.index;
+             self.index += 1;
+             if A::may_have_side_effect() {
+                 // SAFETY: the usage of `cmp::min` to calculate `delta`
+                 // ensures that `end` is smaller than or equal to `self.len`,
+                 // so `i` is also smaller than `self.len`.
+                 unsafe {
+                     self.a.__iterator_get_unchecked(i);
+                 }
+             }
+             if B::may_have_side_effect() {
+                 // SAFETY: same as above.
+                 unsafe {
+                     self.b.__iterator_get_unchecked(i);
+                 }
+             }
+         }
+ 
+         self.super_nth(n - delta)
+     }
+ 
+     #[inline]
+     fn next_back(&mut self) -> Option<(A::Item, B::Item)>
+     where
+         A: DoubleEndedIterator + ExactSizeIterator,
+         B: DoubleEndedIterator + ExactSizeIterator,
+     {
+         let a_side_effect = A::may_have_side_effect();
+         let b_side_effect = B::may_have_side_effect();
+         if a_side_effect || b_side_effect {
+             let sz_a = self.a.size();
+             let sz_b = self.b.size();
+             // Adjust a, b to equal length, make sure that only the first call
+             // of `next_back` does this, otherwise we will break the restriction
+             // on calls to `self.next_back()` after calling `get_unchecked()`.
+             if sz_a != sz_b {
+                 let sz_a = self.a.size();
+                 if a_side_effect && sz_a > self.len {
+                     for _ in 0..sz_a - cmp::max(self.len, self.index) {
+                         self.a.next_back();
+                     }
+                 }
+                 let sz_b = self.b.size();
+                 if b_side_effect && sz_b > self.len {
+                     for _ in 0..sz_b - self.len {
+                         self.b.next_back();
+                     }
+                 }
+             }
+         }
+         if self.index < self.len {
+             self.len -= 1;
+             let i = self.len;
+             // SAFETY: `i` is smaller than the previous value of `self.len`,
+             // which is also smaller than or equal to `self.a.len()` and `self.b.len()`
+             unsafe {
+                 Some((self.a.__iterator_get_unchecked(i), self.b.__iterator_get_unchecked(i)))
+             }
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(&mut self, idx: usize) -> <Self as Iterator>::Item {
+         // SAFETY: the caller must uphold the contract for
+         // `Iterator::__iterator_get_unchecked`.
+         unsafe { (self.a.__iterator_get_unchecked(idx), self.b.__iterator_get_unchecked(idx)) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B> ExactSizeIterator for Zip<A, B>
+ where
+     A: ExactSizeIterator,
+     B: ExactSizeIterator,
+ {
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<A, B> TrustedRandomAccess for Zip<A, B>
+ where
+     A: TrustedRandomAccess,
+     B: TrustedRandomAccess,
+ {
+     fn may_have_side_effect() -> bool {
+         A::may_have_side_effect() || B::may_have_side_effect()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A, B> FusedIterator for Zip<A, B>
+ where
+     A: FusedIterator,
+     B: FusedIterator,
+ {
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A, B> TrustedLen for Zip<A, B>
+ where
+     A: TrustedLen,
+     B: TrustedLen,
+ {
+ }
+ 
+ // Arbitrarily selects the left side of the zip iteration as extractable "source"
+ // it would require negative trait bounds to be able to try both
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ unsafe impl<S, A, B> SourceIter for Zip<A, B>
+ where
+     A: SourceIter<Source = S>,
+     B: Iterator,
+     S: Iterator,
+ {
+     type Source = S;
+ 
+     #[inline]
+     unsafe fn as_inner(&mut self) -> &mut S {
+         // SAFETY: unsafe function forwarding to unsafe function with the same requirements
+         unsafe { SourceIter::as_inner(&mut self.a) }
+     }
+ }
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ // Limited to Item: Copy since interaction between Zip's use of TrustedRandomAccess
+ // and Drop implementation of the source is unclear.
+ //
+ // An additional method returning the number of times the source has been logically advanced
+ // (without calling next()) would be needed to properly drop the remainder of the source.
+ unsafe impl<A: InPlaceIterable, B: Iterator> InPlaceIterable for Zip<A, B> where A::Item: Copy {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A: Debug, B: Debug> Debug for Zip<A, B> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         ZipFmt::fmt(self, f)
+     }
+ }
+ 
+ trait ZipFmt<A, B> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result;
+ }
+ 
+ impl<A: Debug, B: Debug> ZipFmt<A, B> for Zip<A, B> {
+     default fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Zip").field("a", &self.a).field("b", &self.b).finish()
+     }
+ }
+ 
+ impl<A: Debug + TrustedRandomAccess, B: Debug + TrustedRandomAccess> ZipFmt<A, B> for Zip<A, B> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         // It's *not safe* to call fmt on the contained iterators, since once
+         // we start iterating they're in strange, potentially unsafe, states.
+         f.debug_struct("Zip").finish()
+     }
+ }
+ 
+ /// An iterator whose items are random-accessible efficiently
+ ///
+ /// # Safety
+ ///
+ /// The iterator's `size_hint` must be exact and cheap to call.
+ ///
+ /// `size` may not be overridden.
+ ///
+ /// `<Self as Iterator>::__iterator_get_unchecked` must be safe to call
+ /// provided the following conditions are met.
+ ///
+ /// 1. `0 <= idx` and `idx < self.size()`.
+ /// 2. If `self: !Clone`, then `get_unchecked` is never called with the same
+ ///    index on `self` more than once.
+ /// 3. After `self.get_unchecked(idx)` has been called then `next_back` will
+ ///    only be called at most `self.size() - idx - 1` times.
+ /// 4. After `get_unchecked` is called, then only the following methods will be
+ ///    called on `self`:
+ ///     * `std::clone::Clone::clone`
+ ///     * `std::iter::Iterator::size_hint()`
+ ///     * `std::iter::Iterator::next_back()`
+ ///     * `std::iter::Iterator::__iterator_get_unchecked()`
+ ///     * `std::iter::TrustedRandomAccess::size()`
+ ///
+ /// Further, given that these conditions are met, it must guarantee that:
+ ///
+ /// * It does not change the value returned from `size_hint`
+ /// * It must be safe to call the methods listed above on `self` after calling
+ ///   `get_unchecked`, assuming that the required traits are implemented.
+ /// * It must also be safe to drop `self` after calling `get_unchecked`.
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ #[rustc_specialization_trait]
+ pub unsafe trait TrustedRandomAccess: Sized {
+     // Convenience method.
+     fn size(&self) -> usize
+     where
+         Self: Iterator,
+     {
+         self.size_hint().0
+     }
+     /// Returns `true` if getting an iterator element may have
+     /// side effects. Remember to take inner iterators into account.
+     fn may_have_side_effect() -> bool;
+ }
+ 
+ /// Like `Iterator::__iterator_get_unchecked`, but doesn't require the compiler to
+ /// know that `U: TrustedRandomAccess`.
+ ///
+ /// ## Safety
+ ///
+ /// Same requirements calling `get_unchecked` directly.
+ #[doc(hidden)]
+ pub(in crate::iter::adapters) unsafe fn try_get_unchecked<I>(it: &mut I, idx: usize) -> I::Item
+ where
+     I: Iterator,
+ {
+     // SAFETY: the caller must uphold the contract for
+     // `Iterator::__iterator_get_unchecked`.
+     unsafe { it.try_get_unchecked(idx) }
+ }
+ 
+ unsafe trait SpecTrustedRandomAccess: Iterator {
+     /// If `Self: TrustedRandomAccess`, it must be safe to call a
+     /// `Iterator::__iterator_get_unchecked(self, index)`.
+     unsafe fn try_get_unchecked(&mut self, index: usize) -> Self::Item;
+ }
+ 
+ unsafe impl<I: Iterator> SpecTrustedRandomAccess for I {
+     default unsafe fn try_get_unchecked(&mut self, _: usize) -> Self::Item {
+         panic!("Should only be called on TrustedRandomAccess iterators");
+     }
+ }
+ 
+ unsafe impl<I: Iterator + TrustedRandomAccess> SpecTrustedRandomAccess for I {
+     unsafe fn try_get_unchecked(&mut self, index: usize) -> Self::Item {
+         // SAFETY: the caller must uphold the contract for
+         // `Iterator::__iterator_get_unchecked`.
+         unsafe { self.__iterator_get_unchecked(index) }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,375 ----
+ //! Composable external iteration.
+ //!
+ //! If you've found yourself with a collection of some kind, and needed to
+ //! perform an operation on the elements of said collection, you'll quickly run
+ //! into 'iterators'. Iterators are heavily used in idiomatic Rust code, so
+ //! it's worth becoming familiar with them.
+ //!
+ //! Before explaining more, let's talk about how this module is structured:
+ //!
+ //! # Organization
+ //!
+ //! This module is largely organized by type:
+ //!
+ //! * [Traits] are the core portion: these traits define what kind of iterators
+ //!   exist and what you can do with them. The methods of these traits are worth
+ //!   putting some extra study time into.
+ //! * [Functions] provide some helpful ways to create some basic iterators.
+ //! * [Structs] are often the return types of the various methods on this
+ //!   module's traits. You'll usually want to look at the method that creates
+ //!   the `struct`, rather than the `struct` itself. For more detail about why,
+ //!   see '[Implementing Iterator](#implementing-iterator)'.
+ //!
+ //! [Traits]: #traits
+ //! [Functions]: #functions
+ //! [Structs]: #structs
+ //!
+ //! That's it! Let's dig into iterators.
+ //!
+ //! # Iterator
+ //!
+ //! The heart and soul of this module is the [`Iterator`] trait. The core of
+ //! [`Iterator`] looks like this:
+ //!
+ //! ```
+ //! trait Iterator {
+ //!     type Item;
+ //!     fn next(&mut self) -> Option<Self::Item>;
+ //! }
+ //! ```
+ //!
+ //! An iterator has a method, [`next`], which when called, returns an
+ //! [`Option`]`<Item>`. [`next`] will return [`Some(Item)`] as long as there
+ //! are elements, and once they've all been exhausted, will return `None` to
+ //! indicate that iteration is finished. Individual iterators may choose to
+ //! resume iteration, and so calling [`next`] again may or may not eventually
+ //! start returning [`Some(Item)`] again at some point (for example, see [`TryIter`]).
+ //!
+ //! [`Iterator`]'s full definition includes a number of other methods as well,
+ //! but they are default methods, built on top of [`next`], and so you get
+ //! them for free.
+ //!
+ //! Iterators are also composable, and it's common to chain them together to do
+ //! more complex forms of processing. See the [Adapters](#adapters) section
+ //! below for more details.
+ //!
+ //! [`Some(Item)`]: Some
+ //! [`next`]: Iterator::next
+ //! [`TryIter`]: ../../std/sync/mpsc/struct.TryIter.html
+ //!
+ //! # The three forms of iteration
+ //!
+ //! There are three common methods which can create iterators from a collection:
+ //!
+ //! * `iter()`, which iterates over `&T`.
+ //! * `iter_mut()`, which iterates over `&mut T`.
+ //! * `into_iter()`, which iterates over `T`.
+ //!
+ //! Various things in the standard library may implement one or more of the
+ //! three, where appropriate.
+ //!
+ //! # Implementing Iterator
+ //!
+ //! Creating an iterator of your own involves two steps: creating a `struct` to
+ //! hold the iterator's state, and then implementing [`Iterator`] for that `struct`.
+ //! This is why there are so many `struct`s in this module: there is one for
+ //! each iterator and iterator adapter.
+ //!
+ //! Let's make an iterator named `Counter` which counts from `1` to `5`:
+ //!
+ //! ```
+ //! // First, the struct:
+ //!
+ //! /// An iterator which counts from one to five
+ //! struct Counter {
+ //!     count: usize,
+ //! }
+ //!
+ //! // we want our count to start at one, so let's add a new() method to help.
+ //! // This isn't strictly necessary, but is convenient. Note that we start
+ //! // `count` at zero, we'll see why in `next()`'s implementation below.
+ //! impl Counter {
+ //!     fn new() -> Counter {
+ //!         Counter { count: 0 }
+ //!     }
+ //! }
+ //!
+ //! // Then, we implement `Iterator` for our `Counter`:
+ //!
+ //! impl Iterator for Counter {
+ //!     // we will be counting with usize
+ //!     type Item = usize;
+ //!
+ //!     // next() is the only required method
+ //!     fn next(&mut self) -> Option<Self::Item> {
+ //!         // Increment our count. This is why we started at zero.
+ //!         self.count += 1;
+ //!
+ //!         // Check to see if we've finished counting or not.
+ //!         if self.count < 6 {
+ //!             Some(self.count)
+ //!         } else {
+ //!             None
+ //!         }
+ //!     }
+ //! }
+ //!
+ //! // And now we can use it!
+ //!
+ //! let mut counter = Counter::new();
+ //!
+ //! assert_eq!(counter.next(), Some(1));
+ //! assert_eq!(counter.next(), Some(2));
+ //! assert_eq!(counter.next(), Some(3));
+ //! assert_eq!(counter.next(), Some(4));
+ //! assert_eq!(counter.next(), Some(5));
+ //! assert_eq!(counter.next(), None);
+ //! ```
+ //!
+ //! Calling [`next`] this way gets repetitive. Rust has a construct which can
+ //! call [`next`] on your iterator, until it reaches `None`. Let's go over that
+ //! next.
+ //!
+ //! Also note that `Iterator` provides a default implementation of methods such as `nth` and `fold`
+ //! which call `next` internally. However, it is also possible to write a custom implementation of
+ //! methods like `nth` and `fold` if an iterator can compute them more efficiently without calling
+ //! `next`.
+ //!
+ //! # `for` loops and `IntoIterator`
+ //!
+ //! Rust's `for` loop syntax is actually sugar for iterators. Here's a basic
+ //! example of `for`:
+ //!
+ //! ```
+ //! let values = vec![1, 2, 3, 4, 5];
+ //!
+ //! for x in values {
+ //!     println!("{}", x);
+ //! }
+ //! ```
+ //!
+ //! This will print the numbers one through five, each on their own line. But
+ //! you'll notice something here: we never called anything on our vector to
+ //! produce an iterator. What gives?
+ //!
+ //! There's a trait in the standard library for converting something into an
+ //! iterator: [`IntoIterator`]. This trait has one method, [`into_iter`],
+ //! which converts the thing implementing [`IntoIterator`] into an iterator.
+ //! Let's take a look at that `for` loop again, and what the compiler converts
+ //! it into:
+ //!
+ //! [`into_iter`]: IntoIterator::into_iter
+ //!
+ //! ```
+ //! let values = vec![1, 2, 3, 4, 5];
+ //!
+ //! for x in values {
+ //!     println!("{}", x);
+ //! }
+ //! ```
+ //!
+ //! Rust de-sugars this into:
+ //!
+ //! ```
+ //! let values = vec![1, 2, 3, 4, 5];
+ //! {
+ //!     let result = match IntoIterator::into_iter(values) {
+ //!         mut iter => loop {
+ //!             let next;
+ //!             match iter.next() {
+ //!                 Some(val) => next = val,
+ //!                 None => break,
+ //!             };
+ //!             let x = next;
+ //!             let () = { println!("{}", x); };
+ //!         },
+ //!     };
+ //!     result
+ //! }
+ //! ```
+ //!
+ //! First, we call `into_iter()` on the value. Then, we match on the iterator
+ //! that returns, calling [`next`] over and over until we see a `None`. At
+ //! that point, we `break` out of the loop, and we're done iterating.
+ //!
+ //! There's one more subtle bit here: the standard library contains an
+ //! interesting implementation of [`IntoIterator`]:
+ //!
+ //! ```ignore (only-for-syntax-highlight)
+ //! impl<I: Iterator> IntoIterator for I
+ //! ```
+ //!
+ //! In other words, all [`Iterator`]s implement [`IntoIterator`], by just
+ //! returning themselves. This means two things:
+ //!
+ //! 1. If you're writing an [`Iterator`], you can use it with a `for` loop.
+ //! 2. If you're creating a collection, implementing [`IntoIterator`] for it
+ //!    will allow your collection to be used with the `for` loop.
+ //!
+ //! # Adapters
+ //!
+ //! Functions which take an [`Iterator`] and return another [`Iterator`] are
+ //! often called 'iterator adapters', as they're a form of the 'adapter
+ //! pattern'.
+ //!
+ //! Common iterator adapters include [`map`], [`take`], and [`filter`].
+ //! For more, see their documentation.
+ //!
+ //! If an iterator adapter panics, the iterator will be in an unspecified (but
+ //! memory safe) state.  This state is also not guaranteed to stay the same
+ //! across versions of Rust, so you should avoid relying on the exact values
+ //! returned by an iterator which panicked.
+ //!
+ //! [`map`]: Iterator::map
+ //! [`take`]: Iterator::take
+ //! [`filter`]: Iterator::filter
+ //!
+ //! # Laziness
+ //!
+ //! Iterators (and iterator [adapters](#adapters)) are *lazy*. This means that
+ //! just creating an iterator doesn't _do_ a whole lot. Nothing really happens
+ //! until you call [`next`]. This is sometimes a source of confusion when
+ //! creating an iterator solely for its side effects. For example, the [`map`]
+ //! method calls a closure on each element it iterates over:
+ //!
+ //! ```
+ //! # #![allow(unused_must_use)]
+ //! let v = vec![1, 2, 3, 4, 5];
+ //! v.iter().map(|x| println!("{}", x));
+ //! ```
+ //!
+ //! This will not print any values, as we only created an iterator, rather than
+ //! using it. The compiler will warn us about this kind of behavior:
+ //!
+ //! ```text
+ //! warning: unused result that must be used: iterators are lazy and
+ //! do nothing unless consumed
+ //! ```
+ //!
+ //! The idiomatic way to write a [`map`] for its side effects is to use a
+ //! `for` loop or call the [`for_each`] method:
+ //!
+ //! ```
+ //! let v = vec![1, 2, 3, 4, 5];
+ //!
+ //! v.iter().for_each(|x| println!("{}", x));
+ //! // or
+ //! for x in &v {
+ //!     println!("{}", x);
+ //! }
+ //! ```
+ //!
+ //! [`map`]: Iterator::map
+ //! [`for_each`]: Iterator::for_each
+ //!
+ //! Another common way to evaluate an iterator is to use the [`collect`]
+ //! method to produce a new collection.
+ //!
+ //! [`collect`]: Iterator::collect
+ //!
+ //! # Infinity
+ //!
+ //! Iterators do not have to be finite. As an example, an open-ended range is
+ //! an infinite iterator:
+ //!
+ //! ```
+ //! let numbers = 0..;
+ //! ```
+ //!
+ //! It is common to use the [`take`] iterator adapter to turn an infinite
+ //! iterator into a finite one:
+ //!
+ //! ```
+ //! let numbers = 0..;
+ //! let five_numbers = numbers.take(5);
+ //!
+ //! for number in five_numbers {
+ //!     println!("{}", number);
+ //! }
+ //! ```
+ //!
+ //! This will print the numbers `0` through `4`, each on their own line.
+ //!
+ //! Bear in mind that methods on infinite iterators, even those for which a
+ //! result can be determined mathematically in finite time, may not terminate.
+ //! Specifically, methods such as [`min`], which in the general case require
+ //! traversing every element in the iterator, are likely not to return
+ //! successfully for any infinite iterators.
+ //!
+ //! ```no_run
+ //! let ones = std::iter::repeat(1);
+ //! let least = ones.min().unwrap(); // Oh no! An infinite loop!
+ //! // `ones.min()` causes an infinite loop, so we won't reach this point!
+ //! println!("The smallest number one is {}.", least);
+ //! ```
+ //!
+ //! [`take`]: Iterator::take
+ //! [`min`]: Iterator::min
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::traits::Iterator;
+ 
+ #[unstable(
+     feature = "step_trait",
+     reason = "likely to be replaced by finer-grained traits",
+     issue = "42168"
+ )]
+ pub use self::range::Step;
+ 
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ pub use self::sources::{empty, Empty};
+ #[stable(feature = "iter_from_fn", since = "1.34.0")]
+ pub use self::sources::{from_fn, FromFn};
+ #[stable(feature = "iter_once", since = "1.2.0")]
+ pub use self::sources::{once, Once};
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ pub use self::sources::{once_with, OnceWith};
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::sources::{repeat, Repeat};
+ #[stable(feature = "iterator_repeat_with", since = "1.28.0")]
+ pub use self::sources::{repeat_with, RepeatWith};
+ #[stable(feature = "iter_successors", since = "1.34.0")]
+ pub use self::sources::{successors, Successors};
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ pub use self::traits::FusedIterator;
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ pub use self::traits::TrustedLen;
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::traits::{DoubleEndedIterator, Extend, FromIterator, IntoIterator};
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::traits::{ExactSizeIterator, Product, Sum};
+ 
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ pub use self::traits::InPlaceIterable;
+ 
+ #[stable(feature = "iter_cloned", since = "1.1.0")]
+ pub use self::adapters::Cloned;
+ #[stable(feature = "iter_copied", since = "1.36.0")]
+ pub use self::adapters::Copied;
+ #[stable(feature = "iterator_flatten", since = "1.29.0")]
+ pub use self::adapters::Flatten;
+ 
+ #[unstable(feature = "iter_map_while", reason = "recently added", issue = "68537")]
+ pub use self::adapters::MapWhile;
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ pub use self::adapters::SourceIter;
+ #[stable(feature = "iterator_step_by", since = "1.28.0")]
+ pub use self::adapters::StepBy;
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ pub use self::adapters::TrustedRandomAccess;
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::adapters::{Chain, Cycle, Enumerate, Filter, FilterMap, Map, Rev, Zip};
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::adapters::{FlatMap, Peekable, Scan, Skip, SkipWhile, Take, TakeWhile};
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::adapters::{Fuse, Inspect};
+ 
+ pub(crate) use self::adapters::process_results;
+ 
+ mod adapters;
+ mod range;
+ mod sources;
+ mod traits;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/range.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/range.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/range.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/range.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,861 ----
+ use crate::char;
+ use crate::convert::TryFrom;
+ use crate::mem;
+ use crate::ops::{self, Add, Sub, Try};
+ 
+ use super::{FusedIterator, TrustedLen};
+ 
+ /// Objects that have a notion of *successor* and *predecessor* operations.
+ ///
+ /// The *successor* operation moves towards values that compare greater.
+ /// The *predecessor* operation moves towards values that compare lesser.
+ ///
+ /// # Safety
+ ///
+ /// This trait is `unsafe` because its implementation must be correct for
+ /// the safety of `unsafe trait TrustedLen` implementations, and the results
+ /// of using this trait can otherwise be trusted by `unsafe` code to be correct
+ /// and fulfill the listed obligations.
+ #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")]
+ pub unsafe trait Step: Clone + PartialOrd + Sized {
+     /// Returns the number of *successor* steps required to get from `start` to `end`.
+     ///
+     /// Returns `None` if the number of steps would overflow `usize`
+     /// (or is infinite, or if `end` would never be reached).
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`, `b`, and `n`:
+     ///
+     /// * `steps_between(&a, &b) == Some(n)` if and only if `Step::forward_checked(&a, n) == Some(b)`
+     /// * `steps_between(&a, &b) == Some(n)` if and only if `Step::backward_checked(&a, n) == Some(a)`
+     /// * `steps_between(&a, &b) == Some(n)` only if `a <= b`
+     ///   * Corollary: `steps_between(&a, &b) == Some(0)` if and only if `a == b`
+     ///   * Note that `a <= b` does _not_ imply `steps_between(&a, &b) != None`;
+     ///     this is the case when it would require more than `usize::MAX` steps to get to `b`
+     /// * `steps_between(&a, &b) == None` if `a > b`
+     fn steps_between(start: &Self, end: &Self) -> Option<usize>;
+ 
+     /// Returns the value that would be obtained by taking the *successor*
+     /// of `self` `count` times.
+     ///
+     /// If this would overflow the range of values supported by `Self`, returns `None`.
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`, `n`, and `m`:
+     ///
+     /// * `Step::forward_checked(a, n).and_then(|x| Step::forward_checked(x, m)) == Step::forward_checked(a, m).and_then(|x| Step::forward_checked(x, n))`
+     ///
+     /// For any `a`, `n`, and `m` where `n + m` does not overflow:
+     ///
+     /// * `Step::forward_checked(a, n).and_then(|x| Step::forward_checked(x, m)) == Step::forward_checked(a, n + m)`
+     ///
+     /// For any `a` and `n`:
+     ///
+     /// * `Step::forward_checked(a, n) == (0..n).try_fold(a, |x, _| Step::forward_checked(&x, 1))`
+     ///   * Corollary: `Step::forward_checked(&a, 0) == Some(a)`
+     #[unstable(feature = "step_trait_ext", reason = "recently added", issue = "42168")]
+     fn forward_checked(start: Self, count: usize) -> Option<Self>;
+ 
+     /// Returns the value that would be obtained by taking the *successor*
+     /// of `self` `count` times.
+     ///
+     /// If this would overflow the range of values supported by `Self`,
+     /// this function is allowed to panic, wrap, or saturate.
+     /// The suggested behavior is to panic when debug assertions are enabled,
+     /// and to wrap or saturate otherwise.
+     ///
+     /// Unsafe code should not rely on the correctness of behavior after overflow.
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`, `n`, and `m`, where no overflow occurs:
+     ///
+     /// * `Step::forward(Step::forward(a, n), m) == Step::forward(a, n + m)`
+     ///
+     /// For any `a` and `n`, where no overflow occurs:
+     ///
+     /// * `Step::forward_checked(a, n) == Some(Step::forward(a, n))`
+     /// * `Step::forward(a, n) == (0..n).fold(a, |x, _| Step::forward(x, 1))`
+     ///   * Corollary: `Step::forward(a, 0) == a`
+     /// * `Step::forward(a, n) >= a`
+     /// * `Step::backward(Step::forward(a, n), n) == a`
+     #[unstable(feature = "step_trait_ext", reason = "recently added", issue = "42168")]
+     fn forward(start: Self, count: usize) -> Self {
+         Step::forward_checked(start, count).expect("overflow in `Step::forward`")
+     }
+ 
+     /// Returns the value that would be obtained by taking the *successor*
+     /// of `self` `count` times.
+     ///
+     /// # Safety
+     ///
+     /// It is undefined behavior for this operation to overflow the
+     /// range of values supported by `Self`. If you cannot guarantee that this
+     /// will not overflow, use `forward` or `forward_checked` instead.
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`:
+     ///
+     /// * if there exists `b` such that `b > a`, it is safe to call `Step::forward_unchecked(a, 1)`
+     /// * if there exists `b`, `n` such that `steps_between(&a, &b) == Some(n)`,
+     ///   it is safe to call `Step::forward_unchecked(a, m)` for any `m <= n`.
+     ///
+     /// For any `a` and `n`, where no overflow occurs:
+     ///
+     /// * `Step::forward_unchecked(a, n)` is equivalent to `Step::forward(a, n)`
+     #[unstable(feature = "unchecked_math", reason = "niche optimization path", issue = "none")]
+     unsafe fn forward_unchecked(start: Self, count: usize) -> Self {
+         Step::forward(start, count)
+     }
+ 
+     /// Returns the value that would be obtained by taking the *successor*
+     /// of `self` `count` times.
+     ///
+     /// If this would overflow the range of values supported by `Self`, returns `None`.
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`, `n`, and `m`:
+     ///
+     /// * `Step::backward_checked(a, n).and_then(|x| Step::backward_checked(x, m)) == n.checked_add(m).and_then(|x| Step::backward_checked(a, x))`
+     /// * `Step::backward_checked(a, n).and_then(|x| Step::backward_checked(x, m)) == try { Step::backward_checked(a, n.checked_add(m)?) }`
+     ///
+     /// For any `a` and `n`:
+     ///
+     /// * `Step::backward_checked(a, n) == (0..n).try_fold(a, |x, _| Step::backward_checked(&x, 1))`
+     ///   * Corollary: `Step::backward_checked(&a, 0) == Some(a)`
+     #[unstable(feature = "step_trait_ext", reason = "recently added", issue = "42168")]
+     fn backward_checked(start: Self, count: usize) -> Option<Self>;
+ 
+     /// Returns the value that would be obtained by taking the *predecessor*
+     /// of `self` `count` times.
+     ///
+     /// If this would overflow the range of values supported by `Self`,
+     /// this function is allowed to panic, wrap, or saturate.
+     /// The suggested behavior is to panic when debug assertions are enabled,
+     /// and to wrap or saturate otherwise.
+     ///
+     /// Unsafe code should not rely on the correctness of behavior after overflow.
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`, `n`, and `m`, where no overflow occurs:
+     ///
+     /// * `Step::backward(Step::backward(a, n), m) == Step::backward(a, n + m)`
+     ///
+     /// For any `a` and `n`, where no overflow occurs:
+     ///
+     /// * `Step::backward_checked(a, n) == Some(Step::backward(a, n))`
+     /// * `Step::backward(a, n) == (0..n).fold(a, |x, _| Step::backward(x, 1))`
+     ///   * Corollary: `Step::backward(a, 0) == a`
+     /// * `Step::backward(a, n) <= a`
+     /// * `Step::forward(Step::backward(a, n), n) == a`
+     #[unstable(feature = "step_trait_ext", reason = "recently added", issue = "42168")]
+     fn backward(start: Self, count: usize) -> Self {
+         Step::backward_checked(start, count).expect("overflow in `Step::backward`")
+     }
+ 
+     /// Returns the value that would be obtained by taking the *predecessor*
+     /// of `self` `count` times.
+     ///
+     /// # Safety
+     ///
+     /// It is undefined behavior for this operation to overflow the
+     /// range of values supported by `Self`. If you cannot guarantee that this
+     /// will not overflow, use `backward` or `backward_checked` instead.
+     ///
+     /// # Invariants
+     ///
+     /// For any `a`:
+     ///
+     /// * if there exists `b` such that `b < a`, it is safe to call `Step::backward_unchecked(a, 1)`
+     /// * if there exists `b`, `n` such that `steps_between(&b, &a) == Some(n)`,
+     ///   it is safe to call `Step::backward_unchecked(a, m)` for any `m <= n`.
+     ///
+     /// For any `a` and `n`, where no overflow occurs:
+     ///
+     /// * `Step::backward_unchecked(a, n)` is equivalent to `Step::backward(a, n)`
+     #[unstable(feature = "unchecked_math", reason = "niche optimization path", issue = "none")]
+     unsafe fn backward_unchecked(start: Self, count: usize) -> Self {
+         Step::backward(start, count)
+     }
+ }
+ 
+ // These are still macro-generated because the integer literals resolve to different types.
+ macro_rules! step_identical_methods {
+     () => {
+         #[inline]
+         unsafe fn forward_unchecked(start: Self, n: usize) -> Self {
+             // SAFETY: the caller has to guarantee that `start + n` doesn't overflow.
+             unsafe { start.unchecked_add(n as Self) }
+         }
+ 
+         #[inline]
+         unsafe fn backward_unchecked(start: Self, n: usize) -> Self {
+             // SAFETY: the caller has to guarantee that `start - n` doesn't overflow.
+             unsafe { start.unchecked_sub(n as Self) }
+         }
+ 
+         #[inline]
+         fn forward(start: Self, n: usize) -> Self {
+             // In debug builds, trigger a panic on overflow.
+             // This should optimize completely out in release builds.
+             if Self::forward_checked(start, n).is_none() {
+                 let _ = Add::add(Self::MAX, 1);
+             }
+             // Do wrapping math to allow e.g. `Step::forward(-128i8, 255)`.
+             start.wrapping_add(n as Self)
+         }
+ 
+         #[inline]
+         fn backward(start: Self, n: usize) -> Self {
+             // In debug builds, trigger a panic on overflow.
+             // This should optimize completely out in release builds.
+             if Self::backward_checked(start, n).is_none() {
+                 let _ = Sub::sub(Self::MIN, 1);
+             }
+             // Do wrapping math to allow e.g. `Step::backward(127i8, 255)`.
+             start.wrapping_sub(n as Self)
+         }
+     };
+ }
+ 
+ macro_rules! step_integer_impls {
+     {
+         narrower than or same width as usize:
+             $( [ $u_narrower:ident $i_narrower:ident ] ),+;
+         wider than usize:
+             $( [ $u_wider:ident $i_wider:ident ] ),+;
+     } => {
+         $(
+             #[allow(unreachable_patterns)]
+             #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")]
+             unsafe impl Step for $u_narrower {
+                 step_identical_methods!();
+ 
+                 #[inline]
+                 fn steps_between(start: &Self, end: &Self) -> Option<usize> {
+                     if *start <= *end {
+                         // This relies on $u_narrower <= usize
+                         Some((*end - *start) as usize)
+                     } else {
+                         None
+                     }
+                 }
+ 
+                 #[inline]
+                 fn forward_checked(start: Self, n: usize) -> Option<Self> {
+                     match Self::try_from(n) {
+                         Ok(n) => start.checked_add(n),
+                         Err(_) => None, // if n is out of range, `unsigned_start + n` is too
+                     }
+                 }
+ 
+                 #[inline]
+                 fn backward_checked(start: Self, n: usize) -> Option<Self> {
+                     match Self::try_from(n) {
+                         Ok(n) => start.checked_sub(n),
+                         Err(_) => None, // if n is out of range, `unsigned_start - n` is too
+                     }
+                 }
+             }
+ 
+             #[allow(unreachable_patterns)]
+             #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")]
+             unsafe impl Step for $i_narrower {
+                 step_identical_methods!();
+ 
+                 #[inline]
+                 fn steps_between(start: &Self, end: &Self) -> Option<usize> {
+                     if *start <= *end {
+                         // This relies on $i_narrower <= usize
+                         //
+                         // Casting to isize extends the width but preserves the sign.
+                         // Use wrapping_sub in isize space and cast to usize to compute
+                         // the difference that may not fit inside the range of isize.
+                         Some((*end as isize).wrapping_sub(*start as isize) as usize)
+                     } else {
+                         None
+                     }
+                 }
+ 
+                 #[inline]
+                 fn forward_checked(start: Self, n: usize) -> Option<Self> {
+                     match $u_narrower::try_from(n) {
+                         Ok(n) => {
+                             // Wrapping handles cases like
+                             // `Step::forward(-120_i8, 200) == Some(80_i8)`,
+                             // even though 200 is out of range for i8.
+                             let wrapped = start.wrapping_add(n as Self);
+                             if wrapped >= start {
+                                 Some(wrapped)
+                             } else {
+                                 None // Addition overflowed
+                             }
+                         }
+                         // If n is out of range of e.g. u8,
+                         // then it is bigger than the entire range for i8 is wide
+                         // so `any_i8 + n` necessarily overflows i8.
+                         Err(_) => None,
+                     }
+                 }
+ 
+                 #[inline]
+                 fn backward_checked(start: Self, n: usize) -> Option<Self> {
+                     match $u_narrower::try_from(n) {
+                         Ok(n) => {
+                             // Wrapping handles cases like
+                             // `Step::forward(-120_i8, 200) == Some(80_i8)`,
+                             // even though 200 is out of range for i8.
+                             let wrapped = start.wrapping_sub(n as Self);
+                             if wrapped <= start {
+                                 Some(wrapped)
+                             } else {
+                                 None // Subtraction overflowed
+                             }
+                         }
+                         // If n is out of range of e.g. u8,
+                         // then it is bigger than the entire range for i8 is wide
+                         // so `any_i8 - n` necessarily overflows i8.
+                         Err(_) => None,
+                     }
+                 }
+             }
+         )+
+ 
+         $(
+             #[allow(unreachable_patterns)]
+             #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")]
+             unsafe impl Step for $u_wider {
+                 step_identical_methods!();
+ 
+                 #[inline]
+                 fn steps_between(start: &Self, end: &Self) -> Option<usize> {
+                     if *start <= *end {
+                         usize::try_from(*end - *start).ok()
+                     } else {
+                         None
+                     }
+                 }
+ 
+                 #[inline]
+                 fn forward_checked(start: Self, n: usize) -> Option<Self> {
+                     start.checked_add(n as Self)
+                 }
+ 
+                 #[inline]
+                 fn backward_checked(start: Self, n: usize) -> Option<Self> {
+                     start.checked_sub(n as Self)
+                 }
+             }
+ 
+             #[allow(unreachable_patterns)]
+             #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")]
+             unsafe impl Step for $i_wider {
+                 step_identical_methods!();
+ 
+                 #[inline]
+                 fn steps_between(start: &Self, end: &Self) -> Option<usize> {
+                     if *start <= *end {
+                         match end.checked_sub(*start) {
+                             Some(result) => usize::try_from(result).ok(),
+                             // If the difference is too big for e.g. i128,
+                             // it's also gonna be too big for usize with fewer bits.
+                             None => None,
+                         }
+                     } else {
+                         None
+                     }
+                 }
+ 
+                 #[inline]
+                 fn forward_checked(start: Self, n: usize) -> Option<Self> {
+                     start.checked_add(n as Self)
+                 }
+ 
+                 #[inline]
+                 fn backward_checked(start: Self, n: usize) -> Option<Self> {
+                     start.checked_sub(n as Self)
+                 }
+             }
+         )+
+     };
+ }
+ 
+ #[cfg(target_pointer_width = "64")]
+ step_integer_impls! {
+     narrower than or same width as usize: [u8 i8], [u16 i16], [u32 i32], [u64 i64], [usize isize];
+     wider than usize: [u128 i128];
+ }
+ 
+ #[cfg(target_pointer_width = "32")]
+ step_integer_impls! {
+     narrower than or same width as usize: [u8 i8], [u16 i16], [u32 i32], [usize isize];
+     wider than usize: [u64 i64], [u128 i128];
+ }
+ 
+ #[cfg(target_pointer_width = "16")]
+ step_integer_impls! {
+     narrower than or same width as usize: [u8 i8], [u16 i16], [usize isize];
+     wider than usize: [u32 i32], [u64 i64], [u128 i128];
+ }
+ 
+ #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")]
+ unsafe impl Step for char {
+     #[inline]
+     fn steps_between(&start: &char, &end: &char) -> Option<usize> {
+         let start = start as u32;
+         let end = end as u32;
+         if start <= end {
+             let count = end - start;
+             if start < 0xD800 && 0xE000 <= end {
+                 usize::try_from(count - 0x800).ok()
+             } else {
+                 usize::try_from(count).ok()
+             }
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn forward_checked(start: char, count: usize) -> Option<char> {
+         let start = start as u32;
+         let mut res = Step::forward_checked(start, count)?;
+         if start < 0xD800 && 0xD800 <= res {
+             res = Step::forward_checked(res, 0x800)?;
+         }
+         if res <= char::MAX as u32 {
+             // SAFETY: res is a valid unicode scalar
+             // (below 0x110000 and not in 0xD800..0xE000)
+             Some(unsafe { char::from_u32_unchecked(res) })
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn backward_checked(start: char, count: usize) -> Option<char> {
+         let start = start as u32;
+         let mut res = Step::backward_checked(start, count)?;
+         if start >= 0xE000 && 0xE000 > res {
+             res = Step::backward_checked(res, 0x800)?;
+         }
+         // SAFETY: res is a valid unicode scalar
+         // (below 0x110000 and not in 0xD800..0xE000)
+         Some(unsafe { char::from_u32_unchecked(res) })
+     }
+ 
+     #[inline]
+     unsafe fn forward_unchecked(start: char, count: usize) -> char {
+         let start = start as u32;
+         // SAFETY: the caller must guarantee that this doesn't overflow
+         // the range of values for a char.
+         let mut res = unsafe { Step::forward_unchecked(start, count) };
+         if start < 0xD800 && 0xD800 <= res {
+             // SAFETY: the caller must guarantee that this doesn't overflow
+             // the range of values for a char.
+             res = unsafe { Step::forward_unchecked(res, 0x800) };
+         }
+         // SAFETY: because of the previous contract, this is guaranteed
+         // by the caller to be a valid char.
+         unsafe { char::from_u32_unchecked(res) }
+     }
+ 
+     #[inline]
+     unsafe fn backward_unchecked(start: char, count: usize) -> char {
+         let start = start as u32;
+         // SAFETY: the caller must guarantee that this doesn't overflow
+         // the range of values for a char.
+         let mut res = unsafe { Step::backward_unchecked(start, count) };
+         if start >= 0xE000 && 0xE000 > res {
+             // SAFETY: the caller must guarantee that this doesn't overflow
+             // the range of values for a char.
+             res = unsafe { Step::backward_unchecked(res, 0x800) };
+         }
+         // SAFETY: because of the previous contract, this is guaranteed
+         // by the caller to be a valid char.
+         unsafe { char::from_u32_unchecked(res) }
+     }
+ }
+ 
+ macro_rules! range_exact_iter_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl ExactSizeIterator for ops::Range<$t> { }
+     )*)
+ }
+ 
+ macro_rules! range_incl_exact_iter_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "inclusive_range", since = "1.26.0")]
+         impl ExactSizeIterator for ops::RangeInclusive<$t> { }
+     )*)
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A: Step> Iterator for ops::Range<A> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         if self.start < self.end {
+             // SAFETY: just checked precondition
+             let n = unsafe { Step::forward_unchecked(self.start.clone(), 1) };
+             Some(mem::replace(&mut self.start, n))
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.start < self.end {
+             let hint = Step::steps_between(&self.start, &self.end);
+             (hint.unwrap_or(usize::MAX), hint)
+         } else {
+             (0, Some(0))
+         }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<A> {
+         if let Some(plus_n) = Step::forward_checked(self.start.clone(), n) {
+             if plus_n < self.end {
+                 // SAFETY: just checked precondition
+                 self.start = unsafe { Step::forward_unchecked(plus_n.clone(), 1) };
+                 return Some(plus_n);
+             }
+         }
+ 
+         self.start = self.end.clone();
+         None
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<A> {
+         self.next_back()
+     }
+ 
+     #[inline]
+     fn min(mut self) -> Option<A> {
+         self.next()
+     }
+ 
+     #[inline]
+     fn max(mut self) -> Option<A> {
+         self.next_back()
+     }
+ }
+ 
+ // These macros generate `ExactSizeIterator` impls for various range types.
+ //
+ // * `ExactSizeIterator::len` is required to always return an exact `usize`,
+ //   so no range can be longer than `usize::MAX`.
+ // * For integer types in `Range<_>` this is the case for types narrower than or as wide as `usize`.
+ //   For integer types in `RangeInclusive<_>`
+ //   this is the case for types *strictly narrower* than `usize`
+ //   since e.g. `(0..=u64::MAX).len()` would be `u64::MAX + 1`.
+ range_exact_iter_impl! {
+     usize u8 u16
+     isize i8 i16
+ 
+     // These are incorect per the reasoning above,
+     // but removing them would be a breaking change as they were stabilized in Rust 1.0.0.
+     // So e.g. `(0..66_000_u32).len()` for example will compile without error or warnings
+     // on 16-bit platforms, but continue to give a wrong result.
+     u32
+     i32
+ }
+ range_incl_exact_iter_impl! {
+     u8
+     i8
+ 
+     // These are incorect per the reasoning above,
+     // but removing them would be a breaking change as they were stabilized in Rust 1.26.0.
+     // So e.g. `(0..=u16::MAX).len()` for example will compile without error or warnings
+     // on 16-bit platforms, but continue to give a wrong result.
+     u16
+     i16
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A: Step> DoubleEndedIterator for ops::Range<A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<A> {
+         if self.start < self.end {
+             // SAFETY: just checked precondition
+             self.end = unsafe { Step::backward_unchecked(self.end.clone(), 1) };
+             Some(self.end.clone())
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<A> {
+         if let Some(minus_n) = Step::backward_checked(self.end.clone(), n) {
+             if minus_n > self.start {
+                 // SAFETY: just checked precondition
+                 self.end = unsafe { Step::backward_unchecked(minus_n, 1) };
+                 return Some(self.end.clone());
+             }
+         }
+ 
+         self.end = self.start.clone();
+         None
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A: Step> TrustedLen for ops::Range<A> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A: Step> FusedIterator for ops::Range<A> {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A: Step> Iterator for ops::RangeFrom<A> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         let n = Step::forward(self.start.clone(), 1);
+         Some(mem::replace(&mut self.start, n))
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (usize::MAX, None)
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<A> {
+         let plus_n = Step::forward(self.start.clone(), n);
+         self.start = Step::forward(plus_n.clone(), 1);
+         Some(plus_n)
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A: Step> FusedIterator for ops::RangeFrom<A> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A: Step> TrustedLen for ops::RangeFrom<A> {}
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ impl<A: Step> Iterator for ops::RangeInclusive<A> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         if self.is_empty() {
+             return None;
+         }
+         let is_iterating = self.start < self.end;
+         Some(if is_iterating {
+             // SAFETY: just checked precondition
+             let n = unsafe { Step::forward_unchecked(self.start.clone(), 1) };
+             mem::replace(&mut self.start, n)
+         } else {
+             self.exhausted = true;
+             self.start.clone()
+         })
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.is_empty() {
+             return (0, Some(0));
+         }
+ 
+         match Step::steps_between(&self.start, &self.end) {
+             Some(hint) => (hint.saturating_add(1), hint.checked_add(1)),
+             None => (usize::MAX, None),
+         }
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<A> {
+         if self.is_empty() {
+             return None;
+         }
+ 
+         if let Some(plus_n) = Step::forward_checked(self.start.clone(), n) {
+             use crate::cmp::Ordering::*;
+ 
+             match plus_n.partial_cmp(&self.end) {
+                 Some(Less) => {
+                     self.start = Step::forward(plus_n.clone(), 1);
+                     return Some(plus_n);
+                 }
+                 Some(Equal) => {
+                     self.start = plus_n.clone();
+                     self.exhausted = true;
+                     return Some(plus_n);
+                 }
+                 _ => {}
+             }
+         }
+ 
+         self.start = self.end.clone();
+         self.exhausted = true;
+         None
+     }
+ 
+     #[inline]
+     fn try_fold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         if self.is_empty() {
+             return try { init };
+         }
+ 
+         let mut accum = init;
+ 
+         while self.start < self.end {
+             // SAFETY: just checked precondition
+             let n = unsafe { Step::forward_unchecked(self.start.clone(), 1) };
+             let n = mem::replace(&mut self.start, n);
+             accum = f(accum, n)?;
+         }
+ 
+         self.exhausted = true;
+ 
+         if self.start == self.end {
+             accum = f(accum, self.start.clone())?;
+         }
+ 
+         try { accum }
+     }
+ 
+     #[inline]
+     fn fold<B, F>(mut self, init: B, f: F) -> B
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> B,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_fold(init, ok(f)).unwrap()
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<A> {
+         self.next_back()
+     }
+ 
+     #[inline]
+     fn min(mut self) -> Option<A> {
+         self.next()
+     }
+ 
+     #[inline]
+     fn max(mut self) -> Option<A> {
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ impl<A: Step> DoubleEndedIterator for ops::RangeInclusive<A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<A> {
+         if self.is_empty() {
+             return None;
+         }
+         let is_iterating = self.start < self.end;
+         Some(if is_iterating {
+             // SAFETY: just checked precondition
+             let n = unsafe { Step::backward_unchecked(self.end.clone(), 1) };
+             mem::replace(&mut self.end, n)
+         } else {
+             self.exhausted = true;
+             self.end.clone()
+         })
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<A> {
+         if self.is_empty() {
+             return None;
+         }
+ 
+         if let Some(minus_n) = Step::backward_checked(self.end.clone(), n) {
+             use crate::cmp::Ordering::*;
+ 
+             match minus_n.partial_cmp(&self.start) {
+                 Some(Greater) => {
+                     self.end = Step::backward(minus_n.clone(), 1);
+                     return Some(minus_n);
+                 }
+                 Some(Equal) => {
+                     self.end = minus_n.clone();
+                     self.exhausted = true;
+                     return Some(minus_n);
+                 }
+                 _ => {}
+             }
+         }
+ 
+         self.end = self.start.clone();
+         self.exhausted = true;
+         None
+     }
+ 
+     #[inline]
+     fn try_rfold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         if self.is_empty() {
+             return try { init };
+         }
+ 
+         let mut accum = init;
+ 
+         while self.start < self.end {
+             // SAFETY: just checked precondition
+             let n = unsafe { Step::backward_unchecked(self.end.clone(), 1) };
+             let n = mem::replace(&mut self.end, n);
+             accum = f(accum, n)?;
+         }
+ 
+         self.exhausted = true;
+ 
+         if self.start == self.end {
+             accum = f(accum, self.start.clone())?;
+         }
+ 
+         try { accum }
+     }
+ 
+     #[inline]
+     fn rfold<B, F>(mut self, init: B, f: F) -> B
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> B,
+     {
+         #[inline]
+         fn ok<B, T>(mut f: impl FnMut(B, T) -> B) -> impl FnMut(B, T) -> Result<B, !> {
+             move |acc, x| Ok(f(acc, x))
+         }
+ 
+         self.try_rfold(init, ok(f)).unwrap()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A: Step> TrustedLen for ops::RangeInclusive<A> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A: Step> FusedIterator for ops::RangeInclusive<A> {}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/sources.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/sources.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/sources.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/sources.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,625 ----
+ use crate::fmt;
+ use crate::marker;
+ 
+ use super::{FusedIterator, TrustedLen};
+ 
+ /// An iterator that repeats an element endlessly.
+ ///
+ /// This `struct` is created by the [`repeat()`] function. See its documentation for more.
+ #[derive(Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Repeat<A> {
+     element: A,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A: Clone> Iterator for Repeat<A> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         Some(self.element.clone())
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (usize::MAX, None)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A: Clone> DoubleEndedIterator for Repeat<A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<A> {
+         Some(self.element.clone())
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A: Clone> FusedIterator for Repeat<A> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A: Clone> TrustedLen for Repeat<A> {}
+ 
+ /// Creates a new iterator that endlessly repeats a single element.
+ ///
+ /// The `repeat()` function repeats a single value over and over again.
+ ///
+ /// Infinite iterators like `repeat()` are often used with adapters like
+ /// [`Iterator::take()`], in order to make them finite.
+ ///
+ /// If the element type of the iterator you need does not implement `Clone`,
+ /// or if you do not want to keep the repeated element in memory, you can
+ /// instead use the [`repeat_with()`] function.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::iter;
+ ///
+ /// // the number four 4ever:
+ /// let mut fours = iter::repeat(4);
+ ///
+ /// assert_eq!(Some(4), fours.next());
+ /// assert_eq!(Some(4), fours.next());
+ /// assert_eq!(Some(4), fours.next());
+ /// assert_eq!(Some(4), fours.next());
+ /// assert_eq!(Some(4), fours.next());
+ ///
+ /// // yup, still four
+ /// assert_eq!(Some(4), fours.next());
+ /// ```
+ ///
+ /// Going finite with [`Iterator::take()`]:
+ ///
+ /// ```
+ /// use std::iter;
+ ///
+ /// // that last example was too many fours. Let's only have four fours.
+ /// let mut four_fours = iter::repeat(4).take(4);
+ ///
+ /// assert_eq!(Some(4), four_fours.next());
+ /// assert_eq!(Some(4), four_fours.next());
+ /// assert_eq!(Some(4), four_fours.next());
+ /// assert_eq!(Some(4), four_fours.next());
+ ///
+ /// // ... and now we're done
+ /// assert_eq!(None, four_fours.next());
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn repeat<T: Clone>(elt: T) -> Repeat<T> {
+     Repeat { element: elt }
+ }
+ 
+ /// An iterator that repeats elements of type `A` endlessly by
+ /// applying the provided closure `F: FnMut() -> A`.
+ ///
+ /// This `struct` is created by the [`repeat_with()`] function.
+ /// See its documentation for more.
+ #[derive(Copy, Clone, Debug)]
+ #[stable(feature = "iterator_repeat_with", since = "1.28.0")]
+ pub struct RepeatWith<F> {
+     repeater: F,
+ }
+ 
+ #[stable(feature = "iterator_repeat_with", since = "1.28.0")]
+ impl<A, F: FnMut() -> A> Iterator for RepeatWith<F> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         Some((self.repeater)())
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (usize::MAX, None)
+     }
+ }
+ 
+ #[stable(feature = "iterator_repeat_with", since = "1.28.0")]
+ impl<A, F: FnMut() -> A> FusedIterator for RepeatWith<F> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A, F: FnMut() -> A> TrustedLen for RepeatWith<F> {}
+ 
+ /// Creates a new iterator that repeats elements of type `A` endlessly by
+ /// applying the provided closure, the repeater, `F: FnMut() -> A`.
+ ///
+ /// The `repeat_with()` function calls the repeater over and over again.
+ ///
+ /// Infinite iterators like `repeat_with()` are often used with adapters like
+ /// [`Iterator::take()`], in order to make them finite.
+ ///
+ /// If the element type of the iterator you need implements [`Clone`], and
+ /// it is OK to keep the source element in memory, you should instead use
+ /// the [`repeat()`] function.
+ ///
+ /// An iterator produced by `repeat_with()` is not a [`DoubleEndedIterator`].
+ /// If you need `repeat_with()` to return a [`DoubleEndedIterator`],
+ /// please open a GitHub issue explaining your use case.
+ ///
+ /// [`DoubleEndedIterator`]: crate::iter::DoubleEndedIterator
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::iter;
+ ///
+ /// // let's assume we have some value of a type that is not `Clone`
+ /// // or which don't want to have in memory just yet because it is expensive:
+ /// #[derive(PartialEq, Debug)]
+ /// struct Expensive;
+ ///
+ /// // a particular value forever:
+ /// let mut things = iter::repeat_with(|| Expensive);
+ ///
+ /// assert_eq!(Some(Expensive), things.next());
+ /// assert_eq!(Some(Expensive), things.next());
+ /// assert_eq!(Some(Expensive), things.next());
+ /// assert_eq!(Some(Expensive), things.next());
+ /// assert_eq!(Some(Expensive), things.next());
+ /// ```
+ ///
+ /// Using mutation and going finite:
+ ///
+ /// ```rust
+ /// use std::iter;
+ ///
+ /// // From the zeroth to the third power of two:
+ /// let mut curr = 1;
+ /// let mut pow2 = iter::repeat_with(|| { let tmp = curr; curr *= 2; tmp })
+ ///                     .take(4);
+ ///
+ /// assert_eq!(Some(1), pow2.next());
+ /// assert_eq!(Some(2), pow2.next());
+ /// assert_eq!(Some(4), pow2.next());
+ /// assert_eq!(Some(8), pow2.next());
+ ///
+ /// // ... and now we're done
+ /// assert_eq!(None, pow2.next());
+ /// ```
+ #[inline]
+ #[stable(feature = "iterator_repeat_with", since = "1.28.0")]
+ pub fn repeat_with<A, F: FnMut() -> A>(repeater: F) -> RepeatWith<F> {
+     RepeatWith { repeater }
+ }
+ 
+ /// An iterator that yields nothing.
+ ///
+ /// This `struct` is created by the [`empty()`] function. See its documentation for more.
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ pub struct Empty<T>(marker::PhantomData<T>);
+ 
+ #[stable(feature = "iter_empty_send_sync", since = "1.42.0")]
+ unsafe impl<T> Send for Empty<T> {}
+ #[stable(feature = "iter_empty_send_sync", since = "1.42.0")]
+ unsafe impl<T> Sync for Empty<T> {}
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T> fmt::Debug for Empty<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("Empty")
+     }
+ }
+ 
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ impl<T> Iterator for Empty<T> {
+     type Item = T;
+ 
+     fn next(&mut self) -> Option<T> {
+         None
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (0, Some(0))
+     }
+ }
+ 
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ impl<T> DoubleEndedIterator for Empty<T> {
+     fn next_back(&mut self) -> Option<T> {
+         None
+     }
+ }
+ 
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ impl<T> ExactSizeIterator for Empty<T> {
+     fn len(&self) -> usize {
+         0
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for Empty<T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for Empty<T> {}
+ 
+ // not #[derive] because that adds a Clone bound on T,
+ // which isn't necessary.
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ impl<T> Clone for Empty<T> {
+     fn clone(&self) -> Empty<T> {
+         Empty(marker::PhantomData)
+     }
+ }
+ 
+ // not #[derive] because that adds a Default bound on T,
+ // which isn't necessary.
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ impl<T> Default for Empty<T> {
+     fn default() -> Empty<T> {
+         Empty(marker::PhantomData)
+     }
+ }
+ 
+ /// Creates an iterator that yields nothing.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::iter;
+ ///
+ /// // this could have been an iterator over i32, but alas, it's just not.
+ /// let mut nope = iter::empty::<i32>();
+ ///
+ /// assert_eq!(None, nope.next());
+ /// ```
+ #[stable(feature = "iter_empty", since = "1.2.0")]
+ #[rustc_const_stable(feature = "const_iter_empty", since = "1.32.0")]
+ pub const fn empty<T>() -> Empty<T> {
+     Empty(marker::PhantomData)
+ }
+ 
+ /// An iterator that yields an element exactly once.
+ ///
+ /// This `struct` is created by the [`once()`] function. See its documentation for more.
+ #[derive(Clone, Debug)]
+ #[stable(feature = "iter_once", since = "1.2.0")]
+ pub struct Once<T> {
+     inner: crate::option::IntoIter<T>,
+ }
+ 
+ #[stable(feature = "iter_once", since = "1.2.0")]
+ impl<T> Iterator for Once<T> {
+     type Item = T;
+ 
+     fn next(&mut self) -> Option<T> {
+         self.inner.next()
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "iter_once", since = "1.2.0")]
+ impl<T> DoubleEndedIterator for Once<T> {
+     fn next_back(&mut self) -> Option<T> {
+         self.inner.next_back()
+     }
+ }
+ 
+ #[stable(feature = "iter_once", since = "1.2.0")]
+ impl<T> ExactSizeIterator for Once<T> {
+     fn len(&self) -> usize {
+         self.inner.len()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for Once<T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for Once<T> {}
+ 
+ /// Creates an iterator that yields an element exactly once.
+ ///
+ /// This is commonly used to adapt a single value into a [`chain()`] of other
+ /// kinds of iteration. Maybe you have an iterator that covers almost
+ /// everything, but you need an extra special case. Maybe you have a function
+ /// which works on iterators, but you only need to process one value.
+ ///
+ /// [`chain()`]: Iterator::chain
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::iter;
+ ///
+ /// // one is the loneliest number
+ /// let mut one = iter::once(1);
+ ///
+ /// assert_eq!(Some(1), one.next());
+ ///
+ /// // just one, that's all we get
+ /// assert_eq!(None, one.next());
+ /// ```
+ ///
+ /// Chaining together with another iterator. Let's say that we want to iterate
+ /// over each file of the `.foo` directory, but also a configuration file,
+ /// `.foorc`:
+ ///
+ /// ```no_run
+ /// use std::iter;
+ /// use std::fs;
+ /// use std::path::PathBuf;
+ ///
+ /// let dirs = fs::read_dir(".foo").unwrap();
+ ///
+ /// // we need to convert from an iterator of DirEntry-s to an iterator of
+ /// // PathBufs, so we use map
+ /// let dirs = dirs.map(|file| file.unwrap().path());
+ ///
+ /// // now, our iterator just for our config file
+ /// let config = iter::once(PathBuf::from(".foorc"));
+ ///
+ /// // chain the two iterators together into one big iterator
+ /// let files = dirs.chain(config);
+ ///
+ /// // this will give us all of the files in .foo as well as .foorc
+ /// for f in files {
+ ///     println!("{:?}", f);
+ /// }
+ /// ```
+ #[stable(feature = "iter_once", since = "1.2.0")]
+ pub fn once<T>(value: T) -> Once<T> {
+     Once { inner: Some(value).into_iter() }
+ }
+ 
+ /// An iterator that yields a single element of type `A` by
+ /// applying the provided closure `F: FnOnce() -> A`.
+ ///
+ /// This `struct` is created by the [`once_with()`] function.
+ /// See its documentation for more.
+ #[derive(Clone, Debug)]
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ pub struct OnceWith<F> {
+     gen: Option<F>,
+ }
+ 
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ impl<A, F: FnOnce() -> A> Iterator for OnceWith<F> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         let f = self.gen.take()?;
+         Some(f())
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.gen.iter().size_hint()
+     }
+ }
+ 
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ impl<A, F: FnOnce() -> A> DoubleEndedIterator for OnceWith<F> {
+     fn next_back(&mut self) -> Option<A> {
+         self.next()
+     }
+ }
+ 
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ impl<A, F: FnOnce() -> A> ExactSizeIterator for OnceWith<F> {
+     fn len(&self) -> usize {
+         self.gen.iter().len()
+     }
+ }
+ 
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ impl<A, F: FnOnce() -> A> FusedIterator for OnceWith<F> {}
+ 
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ unsafe impl<A, F: FnOnce() -> A> TrustedLen for OnceWith<F> {}
+ 
+ /// Creates an iterator that lazily generates a value exactly once by invoking
+ /// the provided closure.
+ ///
+ /// This is commonly used to adapt a single value generator into a [`chain()`] of
+ /// other kinds of iteration. Maybe you have an iterator that covers almost
+ /// everything, but you need an extra special case. Maybe you have a function
+ /// which works on iterators, but you only need to process one value.
+ ///
+ /// Unlike [`once()`], this function will lazily generate the value on request.
+ ///
+ /// [`chain()`]: Iterator::chain
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::iter;
+ ///
+ /// // one is the loneliest number
+ /// let mut one = iter::once_with(|| 1);
+ ///
+ /// assert_eq!(Some(1), one.next());
+ ///
+ /// // just one, that's all we get
+ /// assert_eq!(None, one.next());
+ /// ```
+ ///
+ /// Chaining together with another iterator. Let's say that we want to iterate
+ /// over each file of the `.foo` directory, but also a configuration file,
+ /// `.foorc`:
+ ///
+ /// ```no_run
+ /// use std::iter;
+ /// use std::fs;
+ /// use std::path::PathBuf;
+ ///
+ /// let dirs = fs::read_dir(".foo").unwrap();
+ ///
+ /// // we need to convert from an iterator of DirEntry-s to an iterator of
+ /// // PathBufs, so we use map
+ /// let dirs = dirs.map(|file| file.unwrap().path());
+ ///
+ /// // now, our iterator just for our config file
+ /// let config = iter::once_with(|| PathBuf::from(".foorc"));
+ ///
+ /// // chain the two iterators together into one big iterator
+ /// let files = dirs.chain(config);
+ ///
+ /// // this will give us all of the files in .foo as well as .foorc
+ /// for f in files {
+ ///     println!("{:?}", f);
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "iter_once_with", since = "1.43.0")]
+ pub fn once_with<A, F: FnOnce() -> A>(gen: F) -> OnceWith<F> {
+     OnceWith { gen: Some(gen) }
+ }
+ 
+ /// Creates a new iterator where each iteration calls the provided closure
+ /// `F: FnMut() -> Option<T>`.
+ ///
+ /// This allows creating a custom iterator with any behavior
+ /// without using the more verbose syntax of creating a dedicated type
+ /// and implementing the [`Iterator`] trait for it.
+ ///
+ /// Note that the `FromFn` iterator doesn’t make assumptions about the behavior of the closure,
+ /// and therefore conservatively does not implement [`FusedIterator`],
+ /// or override [`Iterator::size_hint()`] from its default `(0, None)`.
+ ///
+ /// The closure can use captures and its environment to track state across iterations. Depending on
+ /// how the iterator is used, this may require specifying the [`move`] keyword on the closure.
+ ///
+ /// [`move`]: ../../std/keyword.move.html
+ ///
+ /// # Examples
+ ///
+ /// Let’s re-implement the counter iterator from the [module-level documentation]:
+ ///
+ /// [module-level documentation]: super
+ ///
+ /// ```
+ /// let mut count = 0;
+ /// let counter = std::iter::from_fn(move || {
+ ///     // Increment our count. This is why we started at zero.
+ ///     count += 1;
+ ///
+ ///     // Check to see if we've finished counting or not.
+ ///     if count < 6 {
+ ///         Some(count)
+ ///     } else {
+ ///         None
+ ///     }
+ /// });
+ /// assert_eq!(counter.collect::<Vec<_>>(), &[1, 2, 3, 4, 5]);
+ /// ```
+ #[inline]
+ #[stable(feature = "iter_from_fn", since = "1.34.0")]
+ pub fn from_fn<T, F>(f: F) -> FromFn<F>
+ where
+     F: FnMut() -> Option<T>,
+ {
+     FromFn(f)
+ }
+ 
+ /// An iterator where each iteration calls the provided closure `F: FnMut() -> Option<T>`.
+ ///
+ /// This `struct` is created by the [`iter::from_fn()`] function.
+ /// See its documentation for more.
+ ///
+ /// [`iter::from_fn()`]: from_fn
+ #[derive(Clone)]
+ #[stable(feature = "iter_from_fn", since = "1.34.0")]
+ pub struct FromFn<F>(F);
+ 
+ #[stable(feature = "iter_from_fn", since = "1.34.0")]
+ impl<T, F> Iterator for FromFn<F>
+ where
+     F: FnMut() -> Option<T>,
+ {
+     type Item = T;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<Self::Item> {
+         (self.0)()
+     }
+ }
+ 
+ #[stable(feature = "iter_from_fn", since = "1.34.0")]
+ impl<F> fmt::Debug for FromFn<F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("FromFn").finish()
+     }
+ }
+ 
+ /// Creates a new iterator where each successive item is computed based on the preceding one.
+ ///
+ /// The iterator starts with the given first item (if any)
+ /// and calls the given `FnMut(&T) -> Option<T>` closure to compute each item’s successor.
+ ///
+ /// ```
+ /// use std::iter::successors;
+ ///
+ /// let powers_of_10 = successors(Some(1_u16), |n| n.checked_mul(10));
+ /// assert_eq!(powers_of_10.collect::<Vec<_>>(), &[1, 10, 100, 1_000, 10_000]);
+ /// ```
+ #[stable(feature = "iter_successors", since = "1.34.0")]
+ pub fn successors<T, F>(first: Option<T>, succ: F) -> Successors<T, F>
+ where
+     F: FnMut(&T) -> Option<T>,
+ {
+     // If this function returned `impl Iterator<Item=T>`
+     // it could be based on `unfold` and not need a dedicated type.
+     // However having a named `Successors<T, F>` type allows it to be `Clone` when `T` and `F` are.
+     Successors { next: first, succ }
+ }
+ 
+ /// An new iterator where each successive item is computed based on the preceding one.
+ ///
+ /// This `struct` is created by the [`iter::successors()`] function.
+ /// See its documentation for more.
+ ///
+ /// [`iter::successors()`]: successors
+ #[derive(Clone)]
+ #[stable(feature = "iter_successors", since = "1.34.0")]
+ pub struct Successors<T, F> {
+     next: Option<T>,
+     succ: F,
+ }
+ 
+ #[stable(feature = "iter_successors", since = "1.34.0")]
+ impl<T, F> Iterator for Successors<T, F>
+ where
+     F: FnMut(&T) -> Option<T>,
+ {
+     type Item = T;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<Self::Item> {
+         let item = self.next.take()?;
+         self.next = (self.succ)(&item);
+         Some(item)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.next.is_some() { (1, None) } else { (0, Some(0)) }
+     }
+ }
+ 
+ #[stable(feature = "iter_successors", since = "1.34.0")]
+ impl<T, F> FusedIterator for Successors<T, F> where F: FnMut(&T) -> Option<T> {}
+ 
+ #[stable(feature = "iter_successors", since = "1.34.0")]
+ impl<T: fmt::Debug, F> fmt::Debug for Successors<T, F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Successors").field("next", &self.next).finish()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/accum.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/accum.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/accum.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/accum.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,203 ----
+ use crate::iter;
+ use crate::num::Wrapping;
+ use crate::ops::{Add, Mul};
+ 
+ /// Trait to represent types that can be created by summing up an iterator.
+ ///
+ /// This trait is used to implement the [`sum()`] method on iterators. Types which
+ /// implement the trait can be generated by the [`sum()`] method. Like
+ /// [`FromIterator`] this trait should rarely be called directly and instead
+ /// interacted with through [`Iterator::sum()`].
+ ///
+ /// [`sum()`]: Sum::sum
+ /// [`FromIterator`]: iter::FromIterator
+ #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+ pub trait Sum<A = Self>: Sized {
+     /// Method which takes an iterator and generates `Self` from the elements by
+     /// "summing up" the items.
+     #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+     fn sum<I: Iterator<Item = A>>(iter: I) -> Self;
+ }
+ 
+ /// Trait to represent types that can be created by multiplying elements of an
+ /// iterator.
+ ///
+ /// This trait is used to implement the [`product()`] method on iterators. Types
+ /// which implement the trait can be generated by the [`product()`] method. Like
+ /// [`FromIterator`] this trait should rarely be called directly and instead
+ /// interacted with through [`Iterator::product()`].
+ ///
+ /// [`product()`]: Product::product
+ /// [`FromIterator`]: iter::FromIterator
+ #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+ pub trait Product<A = Self>: Sized {
+     /// Method which takes an iterator and generates `Self` from the elements by
+     /// multiplying the items.
+     #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+     fn product<I: Iterator<Item = A>>(iter: I) -> Self;
+ }
+ 
+ // N.B., explicitly use Add and Mul here to inherit overflow checks
+ macro_rules! integer_sum_product {
+     (@impls $zero:expr, $one:expr, #[$attr:meta], $($a:ty)*) => ($(
+         #[$attr]
+         impl Sum for $a {
+             fn sum<I: Iterator<Item=Self>>(iter: I) -> Self {
+                 iter.fold($zero, Add::add)
+             }
+         }
+ 
+         #[$attr]
+         impl Product for $a {
+             fn product<I: Iterator<Item=Self>>(iter: I) -> Self {
+                 iter.fold($one, Mul::mul)
+             }
+         }
+ 
+         #[$attr]
+         impl<'a> Sum<&'a $a> for $a {
+             fn sum<I: Iterator<Item=&'a Self>>(iter: I) -> Self {
+                 iter.fold($zero, Add::add)
+             }
+         }
+ 
+         #[$attr]
+         impl<'a> Product<&'a $a> for $a {
+             fn product<I: Iterator<Item=&'a Self>>(iter: I) -> Self {
+                 iter.fold($one, Mul::mul)
+             }
+         }
+     )*);
+     ($($a:ty)*) => (
+         integer_sum_product!(@impls 0, 1,
+                 #[stable(feature = "iter_arith_traits", since = "1.12.0")],
+                 $($a)*);
+         integer_sum_product!(@impls Wrapping(0), Wrapping(1),
+                 #[stable(feature = "wrapping_iter_arith", since = "1.14.0")],
+                 $(Wrapping<$a>)*);
+     );
+ }
+ 
+ macro_rules! float_sum_product {
+     ($($a:ident)*) => ($(
+         #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+         impl Sum for $a {
+             fn sum<I: Iterator<Item=Self>>(iter: I) -> Self {
+                 iter.fold(0.0, Add::add)
+             }
+         }
+ 
+         #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+         impl Product for $a {
+             fn product<I: Iterator<Item=Self>>(iter: I) -> Self {
+                 iter.fold(1.0, Mul::mul)
+             }
+         }
+ 
+         #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+         impl<'a> Sum<&'a $a> for $a {
+             fn sum<I: Iterator<Item=&'a Self>>(iter: I) -> Self {
+                 iter.fold(0.0, Add::add)
+             }
+         }
+ 
+         #[stable(feature = "iter_arith_traits", since = "1.12.0")]
+         impl<'a> Product<&'a $a> for $a {
+             fn product<I: Iterator<Item=&'a Self>>(iter: I) -> Self {
+                 iter.fold(1.0, Mul::mul)
+             }
+         }
+     )*)
+ }
+ 
+ integer_sum_product! { i8 i16 i32 i64 i128 isize u8 u16 u32 u64 u128 usize }
+ float_sum_product! { f32 f64 }
+ 
+ #[stable(feature = "iter_arith_traits_result", since = "1.16.0")]
+ impl<T, U, E> Sum<Result<U, E>> for Result<T, E>
+ where
+     T: Sum<U>,
+ {
+     /// Takes each element in the [`Iterator`]: if it is an [`Err`], no further
+     /// elements are taken, and the [`Err`] is returned. Should no [`Err`]
+     /// occur, the sum of all elements is returned.
+     ///
+     /// # Examples
+     ///
+     /// This sums up every integer in a vector, rejecting the sum if a negative
+     /// element is encountered:
+     ///
+     /// ```
+     /// let v = vec![1, 2];
+     /// let res: Result<i32, &'static str> = v.iter().map(|&x: &i32|
+     ///     if x < 0 { Err("Negative element found") }
+     ///     else { Ok(x) }
+     /// ).sum();
+     /// assert_eq!(res, Ok(3));
+     /// ```
+     fn sum<I>(iter: I) -> Result<T, E>
+     where
+         I: Iterator<Item = Result<U, E>>,
+     {
+         iter::process_results(iter, |i| i.sum())
+     }
+ }
+ 
+ #[stable(feature = "iter_arith_traits_result", since = "1.16.0")]
+ impl<T, U, E> Product<Result<U, E>> for Result<T, E>
+ where
+     T: Product<U>,
+ {
+     /// Takes each element in the [`Iterator`]: if it is an [`Err`], no further
+     /// elements are taken, and the [`Err`] is returned. Should no [`Err`]
+     /// occur, the product of all elements is returned.
+     fn product<I>(iter: I) -> Result<T, E>
+     where
+         I: Iterator<Item = Result<U, E>>,
+     {
+         iter::process_results(iter, |i| i.product())
+     }
+ }
+ 
+ #[stable(feature = "iter_arith_traits_option", since = "1.37.0")]
+ impl<T, U> Sum<Option<U>> for Option<T>
+ where
+     T: Sum<U>,
+ {
+     /// Takes each element in the [`Iterator`]: if it is a [`None`], no further
+     /// elements are taken, and the [`None`] is returned. Should no [`None`]
+     /// occur, the sum of all elements is returned.
+     ///
+     /// # Examples
+     ///
+     /// This sums up the position of the character 'a' in a vector of strings,
+     /// if a word did not have the character 'a' the operation returns `None`:
+     ///
+     /// ```
+     /// let words = vec!["have", "a", "great", "day"];
+     /// let total: Option<usize> = words.iter().map(|w| w.find('a')).sum();
+     /// assert_eq!(total, Some(5));
+     /// ```
+     fn sum<I>(iter: I) -> Option<T>
+     where
+         I: Iterator<Item = Option<U>>,
+     {
+         iter.map(|x| x.ok_or(())).sum::<Result<_, _>>().ok()
+     }
+ }
+ 
+ #[stable(feature = "iter_arith_traits_option", since = "1.37.0")]
+ impl<T, U> Product<Option<U>> for Option<T>
+ where
+     T: Product<U>,
+ {
+     /// Takes each element in the [`Iterator`]: if it is a [`None`], no further
+     /// elements are taken, and the [`None`] is returned. Should no [`None`]
+     /// occur, the product of all elements is returned.
+     fn product<I>(iter: I) -> Option<T>
+     where
+         I: Iterator<Item = Option<U>>,
+     {
+         iter.map(|x| x.ok_or(())).product::<Result<_, _>>().ok()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/collect.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/collect.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/collect.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/collect.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,359 ----
+ /// Conversion from an [`Iterator`].
+ ///
+ /// By implementing `FromIterator` for a type, you define how it will be
+ /// created from an iterator. This is common for types which describe a
+ /// collection of some kind.
+ ///
+ /// [`FromIterator::from_iter()`] is rarely called explicitly, and is instead
+ /// used through [`Iterator::collect()`] method. See [`Iterator::collect()`]'s
+ /// documentation for more examples.
+ ///
+ /// See also: [`IntoIterator`].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::iter::FromIterator;
+ ///
+ /// let five_fives = std::iter::repeat(5).take(5);
+ ///
+ /// let v = Vec::from_iter(five_fives);
+ ///
+ /// assert_eq!(v, vec![5, 5, 5, 5, 5]);
+ /// ```
+ ///
+ /// Using [`Iterator::collect()`] to implicitly use `FromIterator`:
+ ///
+ /// ```
+ /// let five_fives = std::iter::repeat(5).take(5);
+ ///
+ /// let v: Vec<i32> = five_fives.collect();
+ ///
+ /// assert_eq!(v, vec![5, 5, 5, 5, 5]);
+ /// ```
+ ///
+ /// Implementing `FromIterator` for your type:
+ ///
+ /// ```
+ /// use std::iter::FromIterator;
+ ///
+ /// // A sample collection, that's just a wrapper over Vec<T>
+ /// #[derive(Debug)]
+ /// struct MyCollection(Vec<i32>);
+ ///
+ /// // Let's give it some methods so we can create one and add things
+ /// // to it.
+ /// impl MyCollection {
+ ///     fn new() -> MyCollection {
+ ///         MyCollection(Vec::new())
+ ///     }
+ ///
+ ///     fn add(&mut self, elem: i32) {
+ ///         self.0.push(elem);
+ ///     }
+ /// }
+ ///
+ /// // and we'll implement FromIterator
+ /// impl FromIterator<i32> for MyCollection {
+ ///     fn from_iter<I: IntoIterator<Item=i32>>(iter: I) -> Self {
+ ///         let mut c = MyCollection::new();
+ ///
+ ///         for i in iter {
+ ///             c.add(i);
+ ///         }
+ ///
+ ///         c
+ ///     }
+ /// }
+ ///
+ /// // Now we can make a new iterator...
+ /// let iter = (0..5).into_iter();
+ ///
+ /// // ... and make a MyCollection out of it
+ /// let c = MyCollection::from_iter(iter);
+ ///
+ /// assert_eq!(c.0, vec![0, 1, 2, 3, 4]);
+ ///
+ /// // collect works too!
+ ///
+ /// let iter = (0..5).into_iter();
+ /// let c: MyCollection = iter.collect();
+ ///
+ /// assert_eq!(c.0, vec![0, 1, 2, 3, 4]);
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "a value of type `{Self}` cannot be built from an iterator \
+                over elements of type `{A}`",
+     label = "value of type `{Self}` cannot be built from `std::iter::Iterator<Item={A}>`"
+ )]
+ pub trait FromIterator<A>: Sized {
+     /// Creates a value from an iterator.
+     ///
+     /// See the [module-level documentation] for more.
+     ///
+     /// [module-level documentation]: crate::iter
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::iter::FromIterator;
+     ///
+     /// let five_fives = std::iter::repeat(5).take(5);
+     ///
+     /// let v = Vec::from_iter(five_fives);
+     ///
+     /// assert_eq!(v, vec![5, 5, 5, 5, 5]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn from_iter<T: IntoIterator<Item = A>>(iter: T) -> Self;
+ }
+ 
+ /// Conversion into an [`Iterator`].
+ ///
+ /// By implementing `IntoIterator` for a type, you define how it will be
+ /// converted to an iterator. This is common for types which describe a
+ /// collection of some kind.
+ ///
+ /// One benefit of implementing `IntoIterator` is that your type will [work
+ /// with Rust's `for` loop syntax](crate::iter#for-loops-and-intoiterator).
+ ///
+ /// See also: [`FromIterator`].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let v = vec![1, 2, 3];
+ /// let mut iter = v.into_iter();
+ ///
+ /// assert_eq!(Some(1), iter.next());
+ /// assert_eq!(Some(2), iter.next());
+ /// assert_eq!(Some(3), iter.next());
+ /// assert_eq!(None, iter.next());
+ /// ```
+ /// Implementing `IntoIterator` for your type:
+ ///
+ /// ```
+ /// // A sample collection, that's just a wrapper over Vec<T>
+ /// #[derive(Debug)]
+ /// struct MyCollection(Vec<i32>);
+ ///
+ /// // Let's give it some methods so we can create one and add things
+ /// // to it.
+ /// impl MyCollection {
+ ///     fn new() -> MyCollection {
+ ///         MyCollection(Vec::new())
+ ///     }
+ ///
+ ///     fn add(&mut self, elem: i32) {
+ ///         self.0.push(elem);
+ ///     }
+ /// }
+ ///
+ /// // and we'll implement IntoIterator
+ /// impl IntoIterator for MyCollection {
+ ///     type Item = i32;
+ ///     type IntoIter = std::vec::IntoIter<Self::Item>;
+ ///
+ ///     fn into_iter(self) -> Self::IntoIter {
+ ///         self.0.into_iter()
+ ///     }
+ /// }
+ ///
+ /// // Now we can make a new collection...
+ /// let mut c = MyCollection::new();
+ ///
+ /// // ... add some stuff to it ...
+ /// c.add(0);
+ /// c.add(1);
+ /// c.add(2);
+ ///
+ /// // ... and then turn it into an Iterator:
+ /// for (i, n) in c.into_iter().enumerate() {
+ ///     assert_eq!(i as i32, n);
+ /// }
+ /// ```
+ ///
+ /// It is common to use `IntoIterator` as a trait bound. This allows
+ /// the input collection type to change, so long as it is still an
+ /// iterator. Additional bounds can be specified by restricting on
+ /// `Item`:
+ ///
+ /// ```rust
+ /// fn collect_as_strings<T>(collection: T) -> Vec<String>
+ /// where
+ ///     T: IntoIterator,
+ ///     T::Item: std::fmt::Debug,
+ /// {
+ ///     collection
+ ///         .into_iter()
+ ///         .map(|item| format!("{:?}", item))
+ ///         .collect()
+ /// }
+ /// ```
+ #[rustc_diagnostic_item = "IntoIterator"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait IntoIterator {
+     /// The type of the elements being iterated over.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Item;
+ 
+     /// Which kind of iterator are we turning this into?
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type IntoIter: Iterator<Item = Self::Item>;
+ 
+     /// Creates an iterator from a value.
+     ///
+     /// See the [module-level documentation] for more.
+     ///
+     /// [module-level documentation]: crate::iter
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let v = vec![1, 2, 3];
+     /// let mut iter = v.into_iter();
+     ///
+     /// assert_eq!(Some(1), iter.next());
+     /// assert_eq!(Some(2), iter.next());
+     /// assert_eq!(Some(3), iter.next());
+     /// assert_eq!(None, iter.next());
+     /// ```
+     #[lang = "into_iter"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn into_iter(self) -> Self::IntoIter;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator> IntoIterator for I {
+     type Item = I::Item;
+     type IntoIter = I;
+ 
+     fn into_iter(self) -> I {
+         self
+     }
+ }
+ 
+ /// Extend a collection with the contents of an iterator.
+ ///
+ /// Iterators produce a series of values, and collections can also be thought
+ /// of as a series of values. The `Extend` trait bridges this gap, allowing you
+ /// to extend a collection by including the contents of that iterator. When
+ /// extending a collection with an already existing key, that entry is updated
+ /// or, in the case of collections that permit multiple entries with equal
+ /// keys, that entry is inserted.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// // You can extend a String with some chars:
+ /// let mut message = String::from("The first three letters are: ");
+ ///
+ /// message.extend(&['a', 'b', 'c']);
+ ///
+ /// assert_eq!("abc", &message[29..32]);
+ /// ```
+ ///
+ /// Implementing `Extend`:
+ ///
+ /// ```
+ /// // A sample collection, that's just a wrapper over Vec<T>
+ /// #[derive(Debug)]
+ /// struct MyCollection(Vec<i32>);
+ ///
+ /// // Let's give it some methods so we can create one and add things
+ /// // to it.
+ /// impl MyCollection {
+ ///     fn new() -> MyCollection {
+ ///         MyCollection(Vec::new())
+ ///     }
+ ///
+ ///     fn add(&mut self, elem: i32) {
+ ///         self.0.push(elem);
+ ///     }
+ /// }
+ ///
+ /// // since MyCollection has a list of i32s, we implement Extend for i32
+ /// impl Extend<i32> for MyCollection {
+ ///
+ ///     // This is a bit simpler with the concrete type signature: we can call
+ ///     // extend on anything which can be turned into an Iterator which gives
+ ///     // us i32s. Because we need i32s to put into MyCollection.
+ ///     fn extend<T: IntoIterator<Item=i32>>(&mut self, iter: T) {
+ ///
+ ///         // The implementation is very straightforward: loop through the
+ ///         // iterator, and add() each element to ourselves.
+ ///         for elem in iter {
+ ///             self.add(elem);
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// let mut c = MyCollection::new();
+ ///
+ /// c.add(5);
+ /// c.add(6);
+ /// c.add(7);
+ ///
+ /// // let's extend our collection with three more numbers
+ /// c.extend(vec![1, 2, 3]);
+ ///
+ /// // we've added these elements onto the end
+ /// assert_eq!("MyCollection([5, 6, 7, 1, 2, 3])", format!("{:?}", c));
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Extend<A> {
+     /// Extends a collection with the contents of an iterator.
+     ///
+     /// As this is the only required method for this trait, the [trait-level] docs
+     /// contain more details.
+     ///
+     /// [trait-level]: Extend
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // You can extend a String with some chars:
+     /// let mut message = String::from("abc");
+     ///
+     /// message.extend(['d', 'e', 'f'].iter());
+     ///
+     /// assert_eq!("abcdef", &message);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn extend<T: IntoIterator<Item = A>>(&mut self, iter: T);
+ 
+     /// Extends a collection with exactly one element.
+     #[unstable(feature = "extend_one", issue = "72631")]
+     fn extend_one(&mut self, item: A) {
+         self.extend(Some(item));
+     }
+ 
+     /// Reserves capacity in a collection for the given number of additional elements.
+     ///
+     /// The default implementation does nothing.
+     #[unstable(feature = "extend_one", issue = "72631")]
+     fn extend_reserve(&mut self, additional: usize) {
+         let _ = additional;
+     }
+ }
+ 
+ #[stable(feature = "extend_for_unit", since = "1.28.0")]
+ impl Extend<()> for () {
+     fn extend<T: IntoIterator<Item = ()>>(&mut self, iter: T) {
+         iter.into_iter().for_each(drop)
+     }
+     fn extend_one(&mut self, _item: ()) {}
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/double_ended.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/double_ended.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/double_ended.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/double_ended.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,363 ----
+ use crate::ops::{ControlFlow, Try};
+ 
+ /// An iterator able to yield elements from both ends.
+ ///
+ /// Something that implements `DoubleEndedIterator` has one extra capability
+ /// over something that implements [`Iterator`]: the ability to also take
+ /// `Item`s from the back, as well as the front.
+ ///
+ /// It is important to note that both back and forth work on the same range,
+ /// and do not cross: iteration is over when they meet in the middle.
+ ///
+ /// In a similar fashion to the [`Iterator`] protocol, once a
+ /// `DoubleEndedIterator` returns [`None`] from a [`next_back()`], calling it
+ /// again may or may not ever return [`Some`] again. [`next()`] and
+ /// [`next_back()`] are interchangeable for this purpose.
+ ///
+ /// [`next_back()`]: DoubleEndedIterator::next_back
+ /// [`next()`]: Iterator::next
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let numbers = vec![1, 2, 3, 4, 5, 6];
+ ///
+ /// let mut iter = numbers.iter();
+ ///
+ /// assert_eq!(Some(&1), iter.next());
+ /// assert_eq!(Some(&6), iter.next_back());
+ /// assert_eq!(Some(&5), iter.next_back());
+ /// assert_eq!(Some(&2), iter.next());
+ /// assert_eq!(Some(&3), iter.next());
+ /// assert_eq!(Some(&4), iter.next());
+ /// assert_eq!(None, iter.next());
+ /// assert_eq!(None, iter.next_back());
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait DoubleEndedIterator: Iterator {
+     /// Removes and returns an element from the end of the iterator.
+     ///
+     /// Returns `None` when there are no more elements.
+     ///
+     /// The [trait-level] docs contain more details.
+     ///
+     /// [trait-level]: DoubleEndedIterator
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let numbers = vec![1, 2, 3, 4, 5, 6];
+     ///
+     /// let mut iter = numbers.iter();
+     ///
+     /// assert_eq!(Some(&1), iter.next());
+     /// assert_eq!(Some(&6), iter.next_back());
+     /// assert_eq!(Some(&5), iter.next_back());
+     /// assert_eq!(Some(&2), iter.next());
+     /// assert_eq!(Some(&3), iter.next());
+     /// assert_eq!(Some(&4), iter.next());
+     /// assert_eq!(None, iter.next());
+     /// assert_eq!(None, iter.next_back());
+     /// ```
+     ///
+     /// # Remarks
+     ///
+     /// The elements yielded by `DoubleEndedIterator`'s methods may differ from
+     /// the ones yielded by [`Iterator`]'s methods:
+     ///
+     /// ```
+     /// let vec = vec![(1, 'a'), (1, 'b'), (1, 'c'), (2, 'a'), (2, 'b')];
+     /// let uniq_by_fst_comp = || {
+     ///     let mut seen = std::collections::HashSet::new();
+     ///     vec.iter().copied().filter(move |x| seen.insert(x.0))
+     /// };
+     ///
+     /// assert_eq!(uniq_by_fst_comp().last(), Some((2, 'a')));
+     /// assert_eq!(uniq_by_fst_comp().next_back(), Some((2, 'b')));
+     ///
+     /// assert_eq!(
+     ///     uniq_by_fst_comp().fold(vec![], |mut v, x| {v.push(x); v}),
+     ///     vec![(1, 'a'), (2, 'a')]
+     /// );
+     /// assert_eq!(
+     ///     uniq_by_fst_comp().rfold(vec![], |mut v, x| {v.push(x); v}),
+     ///     vec![(2, 'b'), (1, 'c')]
+     /// );
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn next_back(&mut self) -> Option<Self::Item>;
+ 
+     /// Advances the iterator from the back by `n` elements.
+     ///
+     /// `advance_back_by` is the reverse version of [`advance_by`]. This method will
+     /// eagerly skip `n` elements starting from the back by calling [`next_back`] up
+     /// to `n` times until [`None`] is encountered.
+     ///
+     /// `advance_back_by(n)` will return [`Ok(())`] if the iterator successfully advances by
+     /// `n` elements, or [`Err(k)`] if [`None`] is encountered, where `k` is the number of
+     /// elements the iterator is advanced by before running out of elements (i.e. the length
+     /// of the iterator). Note that `k` is always less than `n`.
+     ///
+     /// Calling `advance_back_by(0)` does not consume any elements and always returns [`Ok(())`].
+     ///
+     /// [`advance_by`]: Iterator::advance_by
+     /// [`next_back`]: DoubleEndedIterator::next_back
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(iter_advance_by)]
+     ///
+     /// let a = [3, 4, 5, 6];
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.advance_back_by(2), Ok(()));
+     /// assert_eq!(iter.next_back(), Some(&4));
+     /// assert_eq!(iter.advance_back_by(0), Ok(()));
+     /// assert_eq!(iter.advance_back_by(100), Err(1)); // only `&3` was skipped
+     /// ```
+     ///
+     /// [`Ok(())`]: Ok
+     /// [`Err(k)`]: Err
+     #[inline]
+     #[unstable(feature = "iter_advance_by", reason = "recently added", issue = "77404")]
+     fn advance_back_by(&mut self, n: usize) -> Result<(), usize> {
+         for i in 0..n {
+             self.next_back().ok_or(i)?;
+         }
+         Ok(())
+     }
+ 
+     /// Returns the `n`th element from the end of the iterator.
+     ///
+     /// This is essentially the reversed version of [`Iterator::nth()`].
+     /// Although like most indexing operations, the count starts from zero, so
+     /// `nth_back(0)` returns the first value from the end, `nth_back(1)` the
+     /// second, and so on.
+     ///
+     /// Note that all elements between the end and the returned element will be
+     /// consumed, including the returned element. This also means that calling
+     /// `nth_back(0)` multiple times on the same iterator will return different
+     /// elements.
+     ///
+     /// `nth_back()` will return [`None`] if `n` is greater than or equal to the
+     /// length of the iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.iter().nth_back(2), Some(&1));
+     /// ```
+     ///
+     /// Calling `nth_back()` multiple times doesn't rewind the iterator:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.nth_back(1), Some(&2));
+     /// assert_eq!(iter.nth_back(1), None);
+     /// ```
+     ///
+     /// Returning `None` if there are less than `n + 1` elements:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.iter().nth_back(10), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_nth_back", since = "1.37.0")]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         self.advance_back_by(n).ok()?;
+         self.next_back()
+     }
+ 
+     /// This is the reverse version of [`Iterator::try_fold()`]: it takes
+     /// elements starting from the back of the iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = ["1", "2", "3"];
+     /// let sum = a.iter()
+     ///     .map(|&s| s.parse::<i32>())
+     ///     .try_rfold(0, |acc, x| x.and_then(|y| Ok(acc + y)));
+     /// assert_eq!(sum, Ok(6));
+     /// ```
+     ///
+     /// Short-circuiting:
+     ///
+     /// ```
+     /// let a = ["1", "rust", "3"];
+     /// let mut it = a.iter();
+     /// let sum = it
+     ///     .by_ref()
+     ///     .map(|&s| s.parse::<i32>())
+     ///     .try_rfold(0, |acc, x| x.and_then(|y| Ok(acc + y)));
+     /// assert!(sum.is_err());
+     ///
+     /// // Because it short-circuited, the remaining elements are still
+     /// // available through the iterator.
+     /// assert_eq!(it.next_back(), Some(&"1"));
+     /// ```
+     #[inline]
+     #[stable(feature = "iterator_try_fold", since = "1.27.0")]
+     fn try_rfold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         let mut accum = init;
+         while let Some(x) = self.next_back() {
+             accum = f(accum, x)?;
+         }
+         try { accum }
+     }
+ 
+     /// An iterator method that reduces the iterator's elements to a single,
+     /// final value, starting from the back.
+     ///
+     /// This is the reverse version of [`Iterator::fold()`]: it takes elements
+     /// starting from the back of the iterator.
+     ///
+     /// `rfold()` takes two arguments: an initial value, and a closure with two
+     /// arguments: an 'accumulator', and an element. The closure returns the value that
+     /// the accumulator should have for the next iteration.
+     ///
+     /// The initial value is the value the accumulator will have on the first
+     /// call.
+     ///
+     /// After applying this closure to every element of the iterator, `rfold()`
+     /// returns the accumulator.
+     ///
+     /// This operation is sometimes called 'reduce' or 'inject'.
+     ///
+     /// Folding is useful whenever you have a collection of something, and want
+     /// to produce a single value from it.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// // the sum of all of the elements of a
+     /// let sum = a.iter()
+     ///            .rfold(0, |acc, &x| acc + x);
+     ///
+     /// assert_eq!(sum, 6);
+     /// ```
+     ///
+     /// This example builds a string, starting with an initial value
+     /// and continuing with each element from the back until the front:
+     ///
+     /// ```
+     /// let numbers = [1, 2, 3, 4, 5];
+     ///
+     /// let zero = "0".to_string();
+     ///
+     /// let result = numbers.iter().rfold(zero, |acc, &x| {
+     ///     format!("({} + {})", x, acc)
+     /// });
+     ///
+     /// assert_eq!(result, "(1 + (2 + (3 + (4 + (5 + 0)))))");
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_rfold", since = "1.27.0")]
+     fn rfold<B, F>(mut self, init: B, mut f: F) -> B
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> B,
+     {
+         let mut accum = init;
+         while let Some(x) = self.next_back() {
+             accum = f(accum, x);
+         }
+         accum
+     }
+ 
+     /// Searches for an element of an iterator from the back that satisfies a predicate.
+     ///
+     /// `rfind()` takes a closure that returns `true` or `false`. It applies
+     /// this closure to each element of the iterator, starting at the end, and if any
+     /// of them return `true`, then `rfind()` returns [`Some(element)`]. If they all return
+     /// `false`, it returns [`None`].
+     ///
+     /// `rfind()` is short-circuiting; in other words, it will stop processing
+     /// as soon as the closure returns `true`.
+     ///
+     /// Because `rfind()` takes a reference, and many iterators iterate over
+     /// references, this leads to a possibly confusing situation where the
+     /// argument is a double reference. You can see this effect in the
+     /// examples below, with `&&x`.
+     ///
+     /// [`Some(element)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// assert_eq!(a.iter().rfind(|&&x| x == 2), Some(&2));
+     ///
+     /// assert_eq!(a.iter().rfind(|&&x| x == 5), None);
+     /// ```
+     ///
+     /// Stopping at the first `true`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.rfind(|&&x| x == 2), Some(&2));
+     ///
+     /// // we can still use `iter`, as there are more elements.
+     /// assert_eq!(iter.next_back(), Some(&1));
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_rfind", since = "1.27.0")]
+     fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         Self: Sized,
+         P: FnMut(&Self::Item) -> bool,
+     {
+         #[inline]
+         fn check<T>(mut predicate: impl FnMut(&T) -> bool) -> impl FnMut((), T) -> ControlFlow<T> {
+             move |(), x| {
+                 if predicate(&x) { ControlFlow::Break(x) } else { ControlFlow::CONTINUE }
+             }
+         }
+ 
+         self.try_rfold((), check(predicate)).break_value()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, I: DoubleEndedIterator + ?Sized> DoubleEndedIterator for &'a mut I {
+     fn next_back(&mut self) -> Option<I::Item> {
+         (**self).next_back()
+     }
+     fn advance_back_by(&mut self, n: usize) -> Result<(), usize> {
+         (**self).advance_back_by(n)
+     }
+     fn nth_back(&mut self, n: usize) -> Option<I::Item> {
+         (**self).nth_back(n)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/exact_size.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/exact_size.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/exact_size.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/exact_size.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,141 ----
+ /// An iterator that knows its exact length.
+ ///
+ /// Many [`Iterator`]s don't know how many times they will iterate, but some do.
+ /// If an iterator knows how many times it can iterate, providing access to
+ /// that information can be useful. For example, if you want to iterate
+ /// backwards, a good start is to know where the end is.
+ ///
+ /// When implementing an `ExactSizeIterator`, you must also implement
+ /// [`Iterator`]. When doing so, the implementation of [`Iterator::size_hint`]
+ /// *must* return the exact size of the iterator.
+ ///
+ /// The [`len`] method has a default implementation, so you usually shouldn't
+ /// implement it. However, you may be able to provide a more performant
+ /// implementation than the default, so overriding it in this case makes sense.
+ ///
+ /// [`len`]: ExactSizeIterator::len
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// // a finite range knows exactly how many times it will iterate
+ /// let five = 0..5;
+ ///
+ /// assert_eq!(5, five.len());
+ /// ```
+ ///
+ /// In the [module-level docs], we implemented an [`Iterator`], `Counter`.
+ /// Let's implement `ExactSizeIterator` for it as well:
+ ///
+ /// [module-level docs]: crate::iter
+ ///
+ /// ```
+ /// # struct Counter {
+ /// #     count: usize,
+ /// # }
+ /// # impl Counter {
+ /// #     fn new() -> Counter {
+ /// #         Counter { count: 0 }
+ /// #     }
+ /// # }
+ /// # impl Iterator for Counter {
+ /// #     type Item = usize;
+ /// #     fn next(&mut self) -> Option<Self::Item> {
+ /// #         self.count += 1;
+ /// #         if self.count < 6 {
+ /// #             Some(self.count)
+ /// #         } else {
+ /// #             None
+ /// #         }
+ /// #     }
+ /// # }
+ /// impl ExactSizeIterator for Counter {
+ ///     // We can easily calculate the remaining number of iterations.
+ ///     fn len(&self) -> usize {
+ ///         5 - self.count
+ ///     }
+ /// }
+ ///
+ /// // And now we can use it!
+ ///
+ /// let counter = Counter::new();
+ ///
+ /// assert_eq!(5, counter.len());
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait ExactSizeIterator: Iterator {
+     /// Returns the exact length of the iterator.
+     ///
+     /// The implementation ensures that the iterator will return exactly `len()`
+     /// more times a [`Some(T)`] value, before returning [`None`].
+     /// This method has a default implementation, so you usually should not
+     /// implement it directly. However, if you can provide a more efficient
+     /// implementation, you can do so. See the [trait-level] docs for an
+     /// example.
+     ///
+     /// This function has the same safety guarantees as the
+     /// [`Iterator::size_hint`] function.
+     ///
+     /// [trait-level]: ExactSizeIterator
+     /// [`Some(T)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // a finite range knows exactly how many times it will iterate
+     /// let five = 0..5;
+     ///
+     /// assert_eq!(5, five.len());
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn len(&self) -> usize {
+         let (lower, upper) = self.size_hint();
+         // Note: This assertion is overly defensive, but it checks the invariant
+         // guaranteed by the trait. If this trait were rust-internal,
+         // we could use debug_assert!; assert_eq! will check all Rust user
+         // implementations too.
+         assert_eq!(upper, Some(lower));
+         lower
+     }
+ 
+     /// Returns `true` if the iterator is empty.
+     ///
+     /// This method has a default implementation using
+     /// [`ExactSizeIterator::len()`], so you don't need to implement it yourself.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(exact_size_is_empty)]
+     ///
+     /// let mut one_element = std::iter::once(0);
+     /// assert!(!one_element.is_empty());
+     ///
+     /// assert_eq!(one_element.next(), Some(0));
+     /// assert!(one_element.is_empty());
+     ///
+     /// assert_eq!(one_element.next(), None);
+     /// ```
+     #[inline]
+     #[unstable(feature = "exact_size_is_empty", issue = "35428")]
+     fn is_empty(&self) -> bool {
+         self.len() == 0
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: ExactSizeIterator + ?Sized> ExactSizeIterator for &mut I {
+     fn len(&self) -> usize {
+         (**self).len()
+     }
+     fn is_empty(&self) -> bool {
+         (**self).is_empty()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/iterator.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/iterator.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/iterator.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/iterator.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3303 ----
+ // ignore-tidy-filelength
+ // This file almost exclusively consists of the definition of `Iterator`. We
+ // can't split that into multiple files.
+ 
+ use crate::cmp::{self, Ordering};
+ use crate::ops::{Add, ControlFlow, Try};
+ 
+ use super::super::TrustedRandomAccess;
+ use super::super::{Chain, Cloned, Copied, Cycle, Enumerate, Filter, FilterMap, Fuse};
+ use super::super::{FlatMap, Flatten};
+ use super::super::{FromIterator, Product, Sum, Zip};
+ use super::super::{
+     Inspect, Map, MapWhile, Peekable, Rev, Scan, Skip, SkipWhile, StepBy, Take, TakeWhile,
+ };
+ 
+ fn _assert_is_object_safe(_: &dyn Iterator<Item = ()>) {}
+ 
+ /// An interface for dealing with iterators.
+ ///
+ /// This is the main iterator trait. For more about the concept of iterators
+ /// generally, please see the [module-level documentation]. In particular, you
+ /// may want to know how to [implement `Iterator`][impl].
+ ///
+ /// [module-level documentation]: crate::iter
+ /// [impl]: crate::iter#implementing-iterator
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     on(
+         _Self = "[std::ops::Range<Idx>; 1]",
+         label = "if you meant to iterate between two values, remove the square brackets",
+         note = "`[start..end]` is an array of one `Range`; you might have meant to have a `Range` \
+                 without the brackets: `start..end`"
+     ),
+     on(
+         _Self = "[std::ops::RangeFrom<Idx>; 1]",
+         label = "if you meant to iterate from a value onwards, remove the square brackets",
+         note = "`[start..]` is an array of one `RangeFrom`; you might have meant to have a \
+               `RangeFrom` without the brackets: `start..`, keeping in mind that iterating over an \
+               unbounded iterator will run forever unless you `break` or `return` from within the \
+               loop"
+     ),
+     on(
+         _Self = "[std::ops::RangeTo<Idx>; 1]",
+         label = "if you meant to iterate until a value, remove the square brackets and add a \
+                  starting value",
+         note = "`[..end]` is an array of one `RangeTo`; you might have meant to have a bounded \
+                 `Range` without the brackets: `0..end`"
+     ),
+     on(
+         _Self = "[std::ops::RangeInclusive<Idx>; 1]",
+         label = "if you meant to iterate between two values, remove the square brackets",
+         note = "`[start..=end]` is an array of one `RangeInclusive`; you might have meant to have a \
+               `RangeInclusive` without the brackets: `start..=end`"
+     ),
+     on(
+         _Self = "[std::ops::RangeToInclusive<Idx>; 1]",
+         label = "if you meant to iterate until a value (including it), remove the square brackets \
+                  and add a starting value",
+         note = "`[..=end]` is an array of one `RangeToInclusive`; you might have meant to have a \
+                 bounded `RangeInclusive` without the brackets: `0..=end`"
+     ),
+     on(
+         _Self = "std::ops::RangeTo<Idx>",
+         label = "if you meant to iterate until a value, add a starting value",
+         note = "`..end` is a `RangeTo`, which cannot be iterated on; you might have meant to have a \
+               bounded `Range`: `0..end`"
+     ),
+     on(
+         _Self = "std::ops::RangeToInclusive<Idx>",
+         label = "if you meant to iterate until a value (including it), add a starting value",
+         note = "`..=end` is a `RangeToInclusive`, which cannot be iterated on; you might have meant \
+               to have a bounded `RangeInclusive`: `0..=end`"
+     ),
+     on(
+         _Self = "&str",
+         label = "`{Self}` is not an iterator; try calling `.chars()` or `.bytes()`"
+     ),
+     on(
+         _Self = "std::string::String",
+         label = "`{Self}` is not an iterator; try calling `.chars()` or `.bytes()`"
+     ),
+     on(
+         _Self = "[]",
+         label = "borrow the array with `&` or call `.iter()` on it to iterate over it",
+         note = "arrays are not iterators, but slices like the following are: `&[1, 2, 3]`"
+     ),
+     on(
+         _Self = "{integral}",
+         note = "if you want to iterate between `start` until a value `end`, use the exclusive range \
+               syntax `start..end` or the inclusive range syntax `start..=end`"
+     ),
+     label = "`{Self}` is not an iterator",
+     message = "`{Self}` is not an iterator"
+ )]
+ #[doc(spotlight)]
+ #[must_use = "iterators are lazy and do nothing unless consumed"]
+ pub trait Iterator {
+     /// The type of the elements being iterated over.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Item;
+ 
+     /// Advances the iterator and returns the next value.
+     ///
+     /// Returns [`None`] when iteration is finished. Individual iterator
+     /// implementations may choose to resume iteration, and so calling `next()`
+     /// again may or may not eventually start returning [`Some(Item)`] again at some
+     /// point.
+     ///
+     /// [`Some(Item)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// // A call to next() returns the next value...
+     /// assert_eq!(Some(&1), iter.next());
+     /// assert_eq!(Some(&2), iter.next());
+     /// assert_eq!(Some(&3), iter.next());
+     ///
+     /// // ... and then None once it's over.
+     /// assert_eq!(None, iter.next());
+     ///
+     /// // More calls may or may not return `None`. Here, they always will.
+     /// assert_eq!(None, iter.next());
+     /// assert_eq!(None, iter.next());
+     /// ```
+     #[lang = "next"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn next(&mut self) -> Option<Self::Item>;
+ 
+     /// Returns the bounds on the remaining length of the iterator.
+     ///
+     /// Specifically, `size_hint()` returns a tuple where the first element
+     /// is the lower bound, and the second element is the upper bound.
+     ///
+     /// The second half of the tuple that is returned is an [`Option`]`<`[`usize`]`>`.
+     /// A [`None`] here means that either there is no known upper bound, or the
+     /// upper bound is larger than [`usize`].
+     ///
+     /// # Implementation notes
+     ///
+     /// It is not enforced that an iterator implementation yields the declared
+     /// number of elements. A buggy iterator may yield less than the lower bound
+     /// or more than the upper bound of elements.
+     ///
+     /// `size_hint()` is primarily intended to be used for optimizations such as
+     /// reserving space for the elements of the iterator, but must not be
+     /// trusted to e.g., omit bounds checks in unsafe code. An incorrect
+     /// implementation of `size_hint()` should not lead to memory safety
+     /// violations.
+     ///
+     /// That said, the implementation should provide a correct estimation,
+     /// because otherwise it would be a violation of the trait's protocol.
+     ///
+     /// The default implementation returns `(0, `[`None`]`)` which is correct for any
+     /// iterator.
+     ///
+     /// [`usize`]: type@usize
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// let iter = a.iter();
+     ///
+     /// assert_eq!((3, Some(3)), iter.size_hint());
+     /// ```
+     ///
+     /// A more complex example:
+     ///
+     /// ```
+     /// // The even numbers from zero to ten.
+     /// let iter = (0..10).filter(|x| x % 2 == 0);
+     ///
+     /// // We might iterate from zero to ten times. Knowing that it's five
+     /// // exactly wouldn't be possible without executing filter().
+     /// assert_eq!((0, Some(10)), iter.size_hint());
+     ///
+     /// // Let's add five more numbers with chain()
+     /// let iter = (0..10).filter(|x| x % 2 == 0).chain(15..20);
+     ///
+     /// // now both bounds are increased by five
+     /// assert_eq!((5, Some(15)), iter.size_hint());
+     /// ```
+     ///
+     /// Returning `None` for an upper bound:
+     ///
+     /// ```
+     /// // an infinite iterator has no upper bound
+     /// // and the maximum possible lower bound
+     /// let iter = 0..;
+     ///
+     /// assert_eq!((usize::MAX, None), iter.size_hint());
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (0, None)
+     }
+ 
+     /// Consumes the iterator, counting the number of iterations and returning it.
+     ///
+     /// This method will call [`next`] repeatedly until [`None`] is encountered,
+     /// returning the number of times it saw [`Some`]. Note that [`next`] has to be
+     /// called at least once even if the iterator does not have any elements.
+     ///
+     /// [`next`]: Iterator::next
+     ///
+     /// # Overflow Behavior
+     ///
+     /// The method does no guarding against overflows, so counting elements of
+     /// an iterator with more than [`usize::MAX`] elements either produces the
+     /// wrong result or panics. If debug assertions are enabled, a panic is
+     /// guaranteed.
+     ///
+     /// # Panics
+     ///
+     /// This function might panic if the iterator has more than [`usize::MAX`]
+     /// elements.
+     ///
+     /// [`usize::MAX`]: crate::usize::MAX
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.iter().count(), 3);
+     ///
+     /// let a = [1, 2, 3, 4, 5];
+     /// assert_eq!(a.iter().count(), 5);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn count(self) -> usize
+     where
+         Self: Sized,
+     {
+         #[inline]
+         fn add1<T>(count: usize, _: T) -> usize {
+             // Might overflow.
+             Add::add(count, 1)
+         }
+ 
+         self.fold(0, add1)
+     }
+ 
+     /// Consumes the iterator, returning the last element.
+     ///
+     /// This method will evaluate the iterator until it returns [`None`]. While
+     /// doing so, it keeps track of the current element. After [`None`] is
+     /// returned, `last()` will then return the last element it saw.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.iter().last(), Some(&3));
+     ///
+     /// let a = [1, 2, 3, 4, 5];
+     /// assert_eq!(a.iter().last(), Some(&5));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn last(self) -> Option<Self::Item>
+     where
+         Self: Sized,
+     {
+         #[inline]
+         fn some<T>(_: Option<T>, x: T) -> Option<T> {
+             Some(x)
+         }
+ 
+         self.fold(None, some)
+     }
+ 
+     /// Advances the iterator by `n` elements.
+     ///
+     /// This method will eagerly skip `n` elements by calling [`next`] up to `n`
+     /// times until [`None`] is encountered.
+     ///
+     /// `advance_by(n)` will return [`Ok(())`][Ok] if the iterator successfully advances by
+     /// `n` elements, or [`Err(k)`][Err] if [`None`] is encountered, where `k` is the number
+     /// of elements the iterator is advanced by before running out of elements (i.e. the
+     /// length of the iterator). Note that `k` is always less than `n`.
+     ///
+     /// Calling `advance_by(0)` does not consume any elements and always returns [`Ok(())`][Ok].
+     ///
+     /// [`next`]: Iterator::next
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(iter_advance_by)]
+     ///
+     /// let a = [1, 2, 3, 4];
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.advance_by(2), Ok(()));
+     /// assert_eq!(iter.next(), Some(&3));
+     /// assert_eq!(iter.advance_by(0), Ok(()));
+     /// assert_eq!(iter.advance_by(100), Err(1)); // only `&4` was skipped
+     /// ```
+     #[inline]
+     #[unstable(feature = "iter_advance_by", reason = "recently added", issue = "77404")]
+     fn advance_by(&mut self, n: usize) -> Result<(), usize> {
+         for i in 0..n {
+             self.next().ok_or(i)?;
+         }
+         Ok(())
+     }
+ 
+     /// Returns the `n`th element of the iterator.
+     ///
+     /// Like most indexing operations, the count starts from zero, so `nth(0)`
+     /// returns the first value, `nth(1)` the second, and so on.
+     ///
+     /// Note that all preceding elements, as well as the returned element, will be
+     /// consumed from the iterator. That means that the preceding elements will be
+     /// discarded, and also that calling `nth(0)` multiple times on the same iterator
+     /// will return different elements.
+     ///
+     /// `nth()` will return [`None`] if `n` is greater than or equal to the length of the
+     /// iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.iter().nth(1), Some(&2));
+     /// ```
+     ///
+     /// Calling `nth()` multiple times doesn't rewind the iterator:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.nth(1), Some(&2));
+     /// assert_eq!(iter.nth(1), None);
+     /// ```
+     ///
+     /// Returning `None` if there are less than `n + 1` elements:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.iter().nth(10), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         self.advance_by(n).ok()?;
+         self.next()
+     }
+ 
+     /// Creates an iterator starting at the same point, but stepping by
+     /// the given amount at each iteration.
+     ///
+     /// Note 1: The first element of the iterator will always be returned,
+     /// regardless of the step given.
+     ///
+     /// Note 2: The time at which ignored elements are pulled is not fixed.
+     /// `StepBy` behaves like the sequence `next(), nth(step-1), nth(step-1), …`,
+     /// but is also free to behave like the sequence
+     /// `advance_n_and_return_first(step), advance_n_and_return_first(step), …`
+     /// Which way is used may change for some iterators for performance reasons.
+     /// The second way will advance the iterator earlier and may consume more items.
+     ///
+     /// `advance_n_and_return_first` is the equivalent of:
+     /// ```
+     /// fn advance_n_and_return_first<I>(iter: &mut I, total_step: usize) -> Option<I::Item>
+     /// where
+     ///     I: Iterator,
+     /// {
+     ///     let next = iter.next();
+     ///     if total_step > 1 {
+     ///         iter.nth(total_step-2);
+     ///     }
+     ///     next
+     /// }
+     /// ```
+     ///
+     /// # Panics
+     ///
+     /// The method will panic if the given step is `0`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [0, 1, 2, 3, 4, 5];
+     /// let mut iter = a.iter().step_by(2);
+     ///
+     /// assert_eq!(iter.next(), Some(&0));
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), Some(&4));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "iterator_step_by", since = "1.28.0")]
+     fn step_by(self, step: usize) -> StepBy<Self>
+     where
+         Self: Sized,
+     {
+         StepBy::new(self, step)
+     }
+ 
+     /// Takes two iterators and creates a new iterator over both in sequence.
+     ///
+     /// `chain()` will return a new iterator which will first iterate over
+     /// values from the first iterator and then over values from the second
+     /// iterator.
+     ///
+     /// In other words, it links two iterators together, in a chain. 🔗
+     ///
+     /// [`once`] is commonly used to adapt a single value into a chain of
+     /// other kinds of iteration.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a1 = [1, 2, 3];
+     /// let a2 = [4, 5, 6];
+     ///
+     /// let mut iter = a1.iter().chain(a2.iter());
+     ///
+     /// assert_eq!(iter.next(), Some(&1));
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), Some(&3));
+     /// assert_eq!(iter.next(), Some(&4));
+     /// assert_eq!(iter.next(), Some(&5));
+     /// assert_eq!(iter.next(), Some(&6));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Since the argument to `chain()` uses [`IntoIterator`], we can pass
+     /// anything that can be converted into an [`Iterator`], not just an
+     /// [`Iterator`] itself. For example, slices (`&[T]`) implement
+     /// [`IntoIterator`], and so can be passed to `chain()` directly:
+     ///
+     /// ```
+     /// let s1 = &[1, 2, 3];
+     /// let s2 = &[4, 5, 6];
+     ///
+     /// let mut iter = s1.iter().chain(s2);
+     ///
+     /// assert_eq!(iter.next(), Some(&1));
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), Some(&3));
+     /// assert_eq!(iter.next(), Some(&4));
+     /// assert_eq!(iter.next(), Some(&5));
+     /// assert_eq!(iter.next(), Some(&6));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// If you work with Windows API, you may wish to convert [`OsStr`] to `Vec<u16>`:
+     ///
+     /// ```
+     /// #[cfg(windows)]
+     /// fn os_str_to_utf16(s: &std::ffi::OsStr) -> Vec<u16> {
+     ///     use std::os::windows::ffi::OsStrExt;
+     ///     s.encode_wide().chain(std::iter::once(0)).collect()
+     /// }
+     /// ```
+     ///
+     /// [`once`]: crate::iter::once
+     /// [`OsStr`]: ../../std/ffi/struct.OsStr.html
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn chain<U>(self, other: U) -> Chain<Self, U::IntoIter>
+     where
+         Self: Sized,
+         U: IntoIterator<Item = Self::Item>,
+     {
+         Chain::new(self, other.into_iter())
+     }
+ 
+     /// 'Zips up' two iterators into a single iterator of pairs.
+     ///
+     /// `zip()` returns a new iterator that will iterate over two other
+     /// iterators, returning a tuple where the first element comes from the
+     /// first iterator, and the second element comes from the second iterator.
+     ///
+     /// In other words, it zips two iterators together, into a single one.
+     ///
+     /// If either iterator returns [`None`], [`next`] from the zipped iterator
+     /// will return [`None`]. If the first iterator returns [`None`], `zip` will
+     /// short-circuit and `next` will not be called on the second iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a1 = [1, 2, 3];
+     /// let a2 = [4, 5, 6];
+     ///
+     /// let mut iter = a1.iter().zip(a2.iter());
+     ///
+     /// assert_eq!(iter.next(), Some((&1, &4)));
+     /// assert_eq!(iter.next(), Some((&2, &5)));
+     /// assert_eq!(iter.next(), Some((&3, &6)));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Since the argument to `zip()` uses [`IntoIterator`], we can pass
+     /// anything that can be converted into an [`Iterator`], not just an
+     /// [`Iterator`] itself. For example, slices (`&[T]`) implement
+     /// [`IntoIterator`], and so can be passed to `zip()` directly:
+     ///
+     /// ```
+     /// let s1 = &[1, 2, 3];
+     /// let s2 = &[4, 5, 6];
+     ///
+     /// let mut iter = s1.iter().zip(s2);
+     ///
+     /// assert_eq!(iter.next(), Some((&1, &4)));
+     /// assert_eq!(iter.next(), Some((&2, &5)));
+     /// assert_eq!(iter.next(), Some((&3, &6)));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// `zip()` is often used to zip an infinite iterator to a finite one.
+     /// This works because the finite iterator will eventually return [`None`],
+     /// ending the zipper. Zipping with `(0..)` can look a lot like [`enumerate`]:
+     ///
+     /// ```
+     /// let enumerate: Vec<_> = "foo".chars().enumerate().collect();
+     ///
+     /// let zipper: Vec<_> = (0..).zip("foo".chars()).collect();
+     ///
+     /// assert_eq!((0, 'f'), enumerate[0]);
+     /// assert_eq!((0, 'f'), zipper[0]);
+     ///
+     /// assert_eq!((1, 'o'), enumerate[1]);
+     /// assert_eq!((1, 'o'), zipper[1]);
+     ///
+     /// assert_eq!((2, 'o'), enumerate[2]);
+     /// assert_eq!((2, 'o'), zipper[2]);
+     /// ```
+     ///
+     /// [`enumerate`]: Iterator::enumerate
+     /// [`next`]: Iterator::next
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn zip<U>(self, other: U) -> Zip<Self, U::IntoIter>
+     where
+         Self: Sized,
+         U: IntoIterator,
+     {
+         Zip::new(self, other.into_iter())
+     }
+ 
+     /// Takes a closure and creates an iterator which calls that closure on each
+     /// element.
+     ///
+     /// `map()` transforms one iterator into another, by means of its argument:
+     /// something that implements [`FnMut`]. It produces a new iterator which
+     /// calls this closure on each element of the original iterator.
+     ///
+     /// If you are good at thinking in types, you can think of `map()` like this:
+     /// If you have an iterator that gives you elements of some type `A`, and
+     /// you want an iterator of some other type `B`, you can use `map()`,
+     /// passing a closure that takes an `A` and returns a `B`.
+     ///
+     /// `map()` is conceptually similar to a [`for`] loop. However, as `map()` is
+     /// lazy, it is best used when you're already working with other iterators.
+     /// If you're doing some sort of looping for a side effect, it's considered
+     /// more idiomatic to use [`for`] than `map()`.
+     ///
+     /// [`for`]: ../../book/ch03-05-control-flow.html#looping-through-a-collection-with-for
+     /// [`FnMut`]: crate::ops::FnMut
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter().map(|x| 2 * x);
+     ///
+     /// assert_eq!(iter.next(), Some(2));
+     /// assert_eq!(iter.next(), Some(4));
+     /// assert_eq!(iter.next(), Some(6));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// If you're doing some sort of side effect, prefer [`for`] to `map()`:
+     ///
+     /// ```
+     /// # #![allow(unused_must_use)]
+     /// // don't do this:
+     /// (0..5).map(|x| println!("{}", x));
+     ///
+     /// // it won't even execute, as it is lazy. Rust will warn you about this.
+     ///
+     /// // Instead, use for:
+     /// for x in 0..5 {
+     ///     println!("{}", x);
+     /// }
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn map<B, F>(self, f: F) -> Map<Self, F>
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> B,
+     {
+         Map::new(self, f)
+     }
+ 
+     /// Calls a closure on each element of an iterator.
+     ///
+     /// This is equivalent to using a [`for`] loop on the iterator, although
+     /// `break` and `continue` are not possible from a closure. It's generally
+     /// more idiomatic to use a `for` loop, but `for_each` may be more legible
+     /// when processing items at the end of longer iterator chains. In some
+     /// cases `for_each` may also be faster than a loop, because it will use
+     /// internal iteration on adaptors like `Chain`.
+     ///
+     /// [`for`]: ../../book/ch03-05-control-flow.html#looping-through-a-collection-with-for
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::sync::mpsc::channel;
+     ///
+     /// let (tx, rx) = channel();
+     /// (0..5).map(|x| x * 2 + 1)
+     ///       .for_each(move |x| tx.send(x).unwrap());
+     ///
+     /// let v: Vec<_> =  rx.iter().collect();
+     /// assert_eq!(v, vec![1, 3, 5, 7, 9]);
+     /// ```
+     ///
+     /// For such a small example, a `for` loop may be cleaner, but `for_each`
+     /// might be preferable to keep a functional style with longer iterators:
+     ///
+     /// ```
+     /// (0..5).flat_map(|x| x * 100 .. x * 110)
+     ///       .enumerate()
+     ///       .filter(|&(i, x)| (i + x) % 3 == 0)
+     ///       .for_each(|(i, x)| println!("{}:{}", i, x));
+     /// ```
+     #[inline]
+     #[stable(feature = "iterator_for_each", since = "1.21.0")]
+     fn for_each<F>(self, f: F)
+     where
+         Self: Sized,
+         F: FnMut(Self::Item),
+     {
+         #[inline]
+         fn call<T>(mut f: impl FnMut(T)) -> impl FnMut((), T) {
+             move |(), item| f(item)
+         }
+ 
+         self.fold((), call(f));
+     }
+ 
+     /// Creates an iterator which uses a closure to determine if an element
+     /// should be yielded.
+     ///
+     /// Given an element the closure must return `true` or `false`. The returned
+     /// iterator will yield only the elements for which the closure returns
+     /// true.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [0i32, 1, 2];
+     ///
+     /// let mut iter = a.iter().filter(|x| x.is_positive());
+     ///
+     /// assert_eq!(iter.next(), Some(&1));
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Because the closure passed to `filter()` takes a reference, and many
+     /// iterators iterate over references, this leads to a possibly confusing
+     /// situation, where the type of the closure is a double reference:
+     ///
+     /// ```
+     /// let a = [0, 1, 2];
+     ///
+     /// let mut iter = a.iter().filter(|x| **x > 1); // need two *s!
+     ///
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// It's common to instead use destructuring on the argument to strip away
+     /// one:
+     ///
+     /// ```
+     /// let a = [0, 1, 2];
+     ///
+     /// let mut iter = a.iter().filter(|&x| *x > 1); // both & and *
+     ///
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// or both:
+     ///
+     /// ```
+     /// let a = [0, 1, 2];
+     ///
+     /// let mut iter = a.iter().filter(|&&x| x > 1); // two &s
+     ///
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// of these layers.
+     ///
+     /// Note that `iter.filter(f).next()` is equivalent to `iter.find(f)`.
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn filter<P>(self, predicate: P) -> Filter<Self, P>
+     where
+         Self: Sized,
+         P: FnMut(&Self::Item) -> bool,
+     {
+         Filter::new(self, predicate)
+     }
+ 
+     /// Creates an iterator that both filters and maps.
+     ///
+     /// The returned iterator yields only the `value`s for which the supplied
+     /// closure returns `Some(value)`.
+     ///
+     /// `filter_map` can be used to make chains of [`filter`] and [`map`] more
+     /// concise. The example below shows how a `map().filter().map()` can be
+     /// shortened to a single call to `filter_map`.
+     ///
+     /// [`filter`]: Iterator::filter
+     /// [`map`]: Iterator::map
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = ["1", "two", "NaN", "four", "5"];
+     ///
+     /// let mut iter = a.iter().filter_map(|s| s.parse().ok());
+     ///
+     /// assert_eq!(iter.next(), Some(1));
+     /// assert_eq!(iter.next(), Some(5));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Here's the same example, but with [`filter`] and [`map`]:
+     ///
+     /// ```
+     /// let a = ["1", "two", "NaN", "four", "5"];
+     /// let mut iter = a.iter().map(|s| s.parse()).filter(|s| s.is_ok()).map(|s| s.unwrap());
+     /// assert_eq!(iter.next(), Some(1));
+     /// assert_eq!(iter.next(), Some(5));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// [`Option<T>`]: Option
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn filter_map<B, F>(self, f: F) -> FilterMap<Self, F>
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> Option<B>,
+     {
+         FilterMap::new(self, f)
+     }
+ 
+     /// Creates an iterator which gives the current iteration count as well as
+     /// the next value.
+     ///
+     /// The iterator returned yields pairs `(i, val)`, where `i` is the
+     /// current index of iteration and `val` is the value returned by the
+     /// iterator.
+     ///
+     /// `enumerate()` keeps its count as a [`usize`]. If you want to count by a
+     /// different sized integer, the [`zip`] function provides similar
+     /// functionality.
+     ///
+     /// # Overflow Behavior
+     ///
+     /// The method does no guarding against overflows, so enumerating more than
+     /// [`usize::MAX`] elements either produces the wrong result or panics. If
+     /// debug assertions are enabled, a panic is guaranteed.
+     ///
+     /// # Panics
+     ///
+     /// The returned iterator might panic if the to-be-returned index would
+     /// overflow a [`usize`].
+     ///
+     /// [`usize`]: type@usize
+     /// [`usize::MAX`]: crate::usize::MAX
+     /// [`zip`]: Iterator::zip
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = ['a', 'b', 'c'];
+     ///
+     /// let mut iter = a.iter().enumerate();
+     ///
+     /// assert_eq!(iter.next(), Some((0, &'a')));
+     /// assert_eq!(iter.next(), Some((1, &'b')));
+     /// assert_eq!(iter.next(), Some((2, &'c')));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn enumerate(self) -> Enumerate<Self>
+     where
+         Self: Sized,
+     {
+         Enumerate::new(self)
+     }
+ 
+     /// Creates an iterator which can use [`peek`] to look at the next element of
+     /// the iterator without consuming it.
+     ///
+     /// Adds a [`peek`] method to an iterator. See its documentation for
+     /// more information.
+     ///
+     /// Note that the underlying iterator is still advanced when [`peek`] is
+     /// called for the first time: In order to retrieve the next element,
+     /// [`next`] is called on the underlying iterator, hence any side effects (i.e.
+     /// anything other than fetching the next value) of the [`next`] method
+     /// will occur.
+     ///
+     /// [`peek`]: Peekable::peek
+     /// [`next`]: Iterator::next
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let xs = [1, 2, 3];
+     ///
+     /// let mut iter = xs.iter().peekable();
+     ///
+     /// // peek() lets us see into the future
+     /// assert_eq!(iter.peek(), Some(&&1));
+     /// assert_eq!(iter.next(), Some(&1));
+     ///
+     /// assert_eq!(iter.next(), Some(&2));
+     ///
+     /// // we can peek() multiple times, the iterator won't advance
+     /// assert_eq!(iter.peek(), Some(&&3));
+     /// assert_eq!(iter.peek(), Some(&&3));
+     ///
+     /// assert_eq!(iter.next(), Some(&3));
+     ///
+     /// // after the iterator is finished, so is peek()
+     /// assert_eq!(iter.peek(), None);
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn peekable(self) -> Peekable<Self>
+     where
+         Self: Sized,
+     {
+         Peekable::new(self)
+     }
+ 
+     /// Creates an iterator that [`skip`]s elements based on a predicate.
+     ///
+     /// [`skip`]: Iterator::skip
+     ///
+     /// `skip_while()` takes a closure as an argument. It will call this
+     /// closure on each element of the iterator, and ignore elements
+     /// until it returns `false`.
+     ///
+     /// After `false` is returned, `skip_while()`'s job is over, and the
+     /// rest of the elements are yielded.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [-1i32, 0, 1];
+     ///
+     /// let mut iter = a.iter().skip_while(|x| x.is_negative());
+     ///
+     /// assert_eq!(iter.next(), Some(&0));
+     /// assert_eq!(iter.next(), Some(&1));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Because the closure passed to `skip_while()` takes a reference, and many
+     /// iterators iterate over references, this leads to a possibly confusing
+     /// situation, where the type of the closure is a double reference:
+     ///
+     /// ```
+     /// let a = [-1, 0, 1];
+     ///
+     /// let mut iter = a.iter().skip_while(|x| **x < 0); // need two *s!
+     ///
+     /// assert_eq!(iter.next(), Some(&0));
+     /// assert_eq!(iter.next(), Some(&1));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Stopping after an initial `false`:
+     ///
+     /// ```
+     /// let a = [-1, 0, 1, -2];
+     ///
+     /// let mut iter = a.iter().skip_while(|x| **x < 0);
+     ///
+     /// assert_eq!(iter.next(), Some(&0));
+     /// assert_eq!(iter.next(), Some(&1));
+     ///
+     /// // while this would have been false, since we already got a false,
+     /// // skip_while() isn't used any more
+     /// assert_eq!(iter.next(), Some(&-2));
+     ///
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn skip_while<P>(self, predicate: P) -> SkipWhile<Self, P>
+     where
+         Self: Sized,
+         P: FnMut(&Self::Item) -> bool,
+     {
+         SkipWhile::new(self, predicate)
+     }
+ 
+     /// Creates an iterator that yields elements based on a predicate.
+     ///
+     /// `take_while()` takes a closure as an argument. It will call this
+     /// closure on each element of the iterator, and yield elements
+     /// while it returns `true`.
+     ///
+     /// After `false` is returned, `take_while()`'s job is over, and the
+     /// rest of the elements are ignored.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [-1i32, 0, 1];
+     ///
+     /// let mut iter = a.iter().take_while(|x| x.is_negative());
+     ///
+     /// assert_eq!(iter.next(), Some(&-1));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Because the closure passed to `take_while()` takes a reference, and many
+     /// iterators iterate over references, this leads to a possibly confusing
+     /// situation, where the type of the closure is a double reference:
+     ///
+     /// ```
+     /// let a = [-1, 0, 1];
+     ///
+     /// let mut iter = a.iter().take_while(|x| **x < 0); // need two *s!
+     ///
+     /// assert_eq!(iter.next(), Some(&-1));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Stopping after an initial `false`:
+     ///
+     /// ```
+     /// let a = [-1, 0, 1, -2];
+     ///
+     /// let mut iter = a.iter().take_while(|x| **x < 0);
+     ///
+     /// assert_eq!(iter.next(), Some(&-1));
+     ///
+     /// // We have more elements that are less than zero, but since we already
+     /// // got a false, take_while() isn't used any more
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Because `take_while()` needs to look at the value in order to see if it
+     /// should be included or not, consuming iterators will see that it is
+     /// removed:
+     ///
+     /// ```
+     /// let a = [1, 2, 3, 4];
+     /// let mut iter = a.iter();
+     ///
+     /// let result: Vec<i32> = iter.by_ref()
+     ///                            .take_while(|n| **n != 3)
+     ///                            .cloned()
+     ///                            .collect();
+     ///
+     /// assert_eq!(result, &[1, 2]);
+     ///
+     /// let result: Vec<i32> = iter.cloned().collect();
+     ///
+     /// assert_eq!(result, &[4]);
+     /// ```
+     ///
+     /// The `3` is no longer there, because it was consumed in order to see if
+     /// the iteration should stop, but wasn't placed back into the iterator.
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn take_while<P>(self, predicate: P) -> TakeWhile<Self, P>
+     where
+         Self: Sized,
+         P: FnMut(&Self::Item) -> bool,
+     {
+         TakeWhile::new(self, predicate)
+     }
+ 
+     /// Creates an iterator that both yields elements based on a predicate and maps.
+     ///
+     /// `map_while()` takes a closure as an argument. It will call this
+     /// closure on each element of the iterator, and yield elements
+     /// while it returns [`Some(_)`][`Some`].
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(iter_map_while)]
+     /// let a = [-1i32, 4, 0, 1];
+     ///
+     /// let mut iter = a.iter().map_while(|x| 16i32.checked_div(*x));
+     ///
+     /// assert_eq!(iter.next(), Some(-16));
+     /// assert_eq!(iter.next(), Some(4));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Here's the same example, but with [`take_while`] and [`map`]:
+     ///
+     /// [`take_while`]: Iterator::take_while
+     /// [`map`]: Iterator::map
+     ///
+     /// ```
+     /// let a = [-1i32, 4, 0, 1];
+     ///
+     /// let mut iter = a.iter()
+     ///                 .map(|x| 16i32.checked_div(*x))
+     ///                 .take_while(|x| x.is_some())
+     ///                 .map(|x| x.unwrap());
+     ///
+     /// assert_eq!(iter.next(), Some(-16));
+     /// assert_eq!(iter.next(), Some(4));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// Stopping after an initial [`None`]:
+     ///
+     /// ```
+     /// #![feature(iter_map_while)]
+     /// use std::convert::TryFrom;
+     ///
+     /// let a = [0, 1, 2, -3, 4, 5, -6];
+     ///
+     /// let iter = a.iter().map_while(|x| u32::try_from(*x).ok());
+     /// let vec = iter.collect::<Vec<_>>();
+     ///
+     /// // We have more elements which could fit in u32 (4, 5), but `map_while` returned `None` for `-3`
+     /// // (as the `predicate` returned `None`) and `collect` stops at the first `None` encountered.
+     /// assert_eq!(vec, vec![0, 1, 2]);
+     /// ```
+     ///
+     /// Because `map_while()` needs to look at the value in order to see if it
+     /// should be included or not, consuming iterators will see that it is
+     /// removed:
+     ///
+     /// ```
+     /// #![feature(iter_map_while)]
+     /// use std::convert::TryFrom;
+     ///
+     /// let a = [1, 2, -3, 4];
+     /// let mut iter = a.iter();
+     ///
+     /// let result: Vec<u32> = iter.by_ref()
+     ///                            .map_while(|n| u32::try_from(*n).ok())
+     ///                            .collect();
+     ///
+     /// assert_eq!(result, &[1, 2]);
+     ///
+     /// let result: Vec<i32> = iter.cloned().collect();
+     ///
+     /// assert_eq!(result, &[4]);
+     /// ```
+     ///
+     /// The `-3` is no longer there, because it was consumed in order to see if
+     /// the iteration should stop, but wasn't placed back into the iterator.
+     ///
+     /// Note that unlike [`take_while`] this iterator is **not** fused.
+     /// It is also not specified what this iterator returns after the first` None` is returned.
+     /// If you need fused iterator, use [`fuse`].
+     ///
+     /// [`fuse`]: Iterator::fuse
+     #[inline]
+     #[unstable(feature = "iter_map_while", reason = "recently added", issue = "68537")]
+     fn map_while<B, P>(self, predicate: P) -> MapWhile<Self, P>
+     where
+         Self: Sized,
+         P: FnMut(Self::Item) -> Option<B>,
+     {
+         MapWhile::new(self, predicate)
+     }
+ 
+     /// Creates an iterator that skips the first `n` elements.
+     ///
+     /// After they have been consumed, the rest of the elements are yielded.
+     /// Rather than overriding this method directly, instead override the `nth` method.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter().skip(2);
+     ///
+     /// assert_eq!(iter.next(), Some(&3));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn skip(self, n: usize) -> Skip<Self>
+     where
+         Self: Sized,
+     {
+         Skip::new(self, n)
+     }
+ 
+     /// Creates an iterator that yields its first `n` elements.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter().take(2);
+     ///
+     /// assert_eq!(iter.next(), Some(&1));
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// `take()` is often used with an infinite iterator, to make it finite:
+     ///
+     /// ```
+     /// let mut iter = (0..).take(3);
+     ///
+     /// assert_eq!(iter.next(), Some(0));
+     /// assert_eq!(iter.next(), Some(1));
+     /// assert_eq!(iter.next(), Some(2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// If less than `n` elements are available,
+     /// `take` will limit itself to the size of the underlying iterator:
+     ///
+     /// ```
+     /// let v = vec![1, 2];
+     /// let mut iter = v.into_iter().take(5);
+     /// assert_eq!(iter.next(), Some(1));
+     /// assert_eq!(iter.next(), Some(2));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn take(self, n: usize) -> Take<Self>
+     where
+         Self: Sized,
+     {
+         Take::new(self, n)
+     }
+ 
+     /// An iterator adaptor similar to [`fold`] that holds internal state and
+     /// produces a new iterator.
+     ///
+     /// [`fold`]: Iterator::fold
+     ///
+     /// `scan()` takes two arguments: an initial value which seeds the internal
+     /// state, and a closure with two arguments, the first being a mutable
+     /// reference to the internal state and the second an iterator element.
+     /// The closure can assign to the internal state to share state between
+     /// iterations.
+     ///
+     /// On iteration, the closure will be applied to each element of the
+     /// iterator and the return value from the closure, an [`Option`], is
+     /// yielded by the iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter().scan(1, |state, &x| {
+     ///     // each iteration, we'll multiply the state by the element
+     ///     *state = *state * x;
+     ///
+     ///     // then, we'll yield the negation of the state
+     ///     Some(-*state)
+     /// });
+     ///
+     /// assert_eq!(iter.next(), Some(-1));
+     /// assert_eq!(iter.next(), Some(-2));
+     /// assert_eq!(iter.next(), Some(-6));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn scan<St, B, F>(self, initial_state: St, f: F) -> Scan<Self, St, F>
+     where
+         Self: Sized,
+         F: FnMut(&mut St, Self::Item) -> Option<B>,
+     {
+         Scan::new(self, initial_state, f)
+     }
+ 
+     /// Creates an iterator that works like map, but flattens nested structure.
+     ///
+     /// The [`map`] adapter is very useful, but only when the closure
+     /// argument produces values. If it produces an iterator instead, there's
+     /// an extra layer of indirection. `flat_map()` will remove this extra layer
+     /// on its own.
+     ///
+     /// You can think of `flat_map(f)` as the semantic equivalent
+     /// of [`map`]ping, and then [`flatten`]ing as in `map(f).flatten()`.
+     ///
+     /// Another way of thinking about `flat_map()`: [`map`]'s closure returns
+     /// one item for each element, and `flat_map()`'s closure returns an
+     /// iterator for each element.
+     ///
+     /// [`map`]: Iterator::map
+     /// [`flatten`]: Iterator::flatten
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let words = ["alpha", "beta", "gamma"];
+     ///
+     /// // chars() returns an iterator
+     /// let merged: String = words.iter()
+     ///                           .flat_map(|s| s.chars())
+     ///                           .collect();
+     /// assert_eq!(merged, "alphabetagamma");
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn flat_map<U, F>(self, f: F) -> FlatMap<Self, U, F>
+     where
+         Self: Sized,
+         U: IntoIterator,
+         F: FnMut(Self::Item) -> U,
+     {
+         FlatMap::new(self, f)
+     }
+ 
+     /// Creates an iterator that flattens nested structure.
+     ///
+     /// This is useful when you have an iterator of iterators or an iterator of
+     /// things that can be turned into iterators and you want to remove one
+     /// level of indirection.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let data = vec![vec![1, 2, 3, 4], vec![5, 6]];
+     /// let flattened = data.into_iter().flatten().collect::<Vec<u8>>();
+     /// assert_eq!(flattened, &[1, 2, 3, 4, 5, 6]);
+     /// ```
+     ///
+     /// Mapping and then flattening:
+     ///
+     /// ```
+     /// let words = ["alpha", "beta", "gamma"];
+     ///
+     /// // chars() returns an iterator
+     /// let merged: String = words.iter()
+     ///                           .map(|s| s.chars())
+     ///                           .flatten()
+     ///                           .collect();
+     /// assert_eq!(merged, "alphabetagamma");
+     /// ```
+     ///
+     /// You can also rewrite this in terms of [`flat_map()`], which is preferable
+     /// in this case since it conveys intent more clearly:
+     ///
+     /// ```
+     /// let words = ["alpha", "beta", "gamma"];
+     ///
+     /// // chars() returns an iterator
+     /// let merged: String = words.iter()
+     ///                           .flat_map(|s| s.chars())
+     ///                           .collect();
+     /// assert_eq!(merged, "alphabetagamma");
+     /// ```
+     ///
+     /// Flattening once only removes one level of nesting:
+     ///
+     /// ```
+     /// let d3 = [[[1, 2], [3, 4]], [[5, 6], [7, 8]]];
+     ///
+     /// let d2 = d3.iter().flatten().collect::<Vec<_>>();
+     /// assert_eq!(d2, [&[1, 2], &[3, 4], &[5, 6], &[7, 8]]);
+     ///
+     /// let d1 = d3.iter().flatten().flatten().collect::<Vec<_>>();
+     /// assert_eq!(d1, [&1, &2, &3, &4, &5, &6, &7, &8]);
+     /// ```
+     ///
+     /// Here we see that `flatten()` does not perform a "deep" flatten.
+     /// Instead, only one level of nesting is removed. That is, if you
+     /// `flatten()` a three-dimensional array the result will be
+     /// two-dimensional and not one-dimensional. To get a one-dimensional
+     /// structure, you have to `flatten()` again.
+     ///
+     /// [`flat_map()`]: Iterator::flat_map
+     #[inline]
+     #[stable(feature = "iterator_flatten", since = "1.29.0")]
+     fn flatten(self) -> Flatten<Self>
+     where
+         Self: Sized,
+         Self::Item: IntoIterator,
+     {
+         Flatten::new(self)
+     }
+ 
+     /// Creates an iterator which ends after the first [`None`].
+     ///
+     /// After an iterator returns [`None`], future calls may or may not yield
+     /// [`Some(T)`] again. `fuse()` adapts an iterator, ensuring that after a
+     /// [`None`] is given, it will always return [`None`] forever.
+     ///
+     /// [`Some(T)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // an iterator which alternates between Some and None
+     /// struct Alternate {
+     ///     state: i32,
+     /// }
+     ///
+     /// impl Iterator for Alternate {
+     ///     type Item = i32;
+     ///
+     ///     fn next(&mut self) -> Option<i32> {
+     ///         let val = self.state;
+     ///         self.state = self.state + 1;
+     ///
+     ///         // if it's even, Some(i32), else None
+     ///         if val % 2 == 0 {
+     ///             Some(val)
+     ///         } else {
+     ///             None
+     ///         }
+     ///     }
+     /// }
+     ///
+     /// let mut iter = Alternate { state: 0 };
+     ///
+     /// // we can see our iterator going back and forth
+     /// assert_eq!(iter.next(), Some(0));
+     /// assert_eq!(iter.next(), None);
+     /// assert_eq!(iter.next(), Some(2));
+     /// assert_eq!(iter.next(), None);
+     ///
+     /// // however, once we fuse it...
+     /// let mut iter = iter.fuse();
+     ///
+     /// assert_eq!(iter.next(), Some(4));
+     /// assert_eq!(iter.next(), None);
+     ///
+     /// // it will always return `None` after the first time.
+     /// assert_eq!(iter.next(), None);
+     /// assert_eq!(iter.next(), None);
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fuse(self) -> Fuse<Self>
+     where
+         Self: Sized,
+     {
+         Fuse::new(self)
+     }
+ 
+     /// Does something with each element of an iterator, passing the value on.
+     ///
+     /// When using iterators, you'll often chain several of them together.
+     /// While working on such code, you might want to check out what's
+     /// happening at various parts in the pipeline. To do that, insert
+     /// a call to `inspect()`.
+     ///
+     /// It's more common for `inspect()` to be used as a debugging tool than to
+     /// exist in your final code, but applications may find it useful in certain
+     /// situations when errors need to be logged before being discarded.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 4, 2, 3];
+     ///
+     /// // this iterator sequence is complex.
+     /// let sum = a.iter()
+     ///     .cloned()
+     ///     .filter(|x| x % 2 == 0)
+     ///     .fold(0, |sum, i| sum + i);
+     ///
+     /// println!("{}", sum);
+     ///
+     /// // let's add some inspect() calls to investigate what's happening
+     /// let sum = a.iter()
+     ///     .cloned()
+     ///     .inspect(|x| println!("about to filter: {}", x))
+     ///     .filter(|x| x % 2 == 0)
+     ///     .inspect(|x| println!("made it through filter: {}", x))
+     ///     .fold(0, |sum, i| sum + i);
+     ///
+     /// println!("{}", sum);
+     /// ```
+     ///
+     /// This will print:
+     ///
+     /// ```text
+     /// 6
+     /// about to filter: 1
+     /// about to filter: 4
+     /// made it through filter: 4
+     /// about to filter: 2
+     /// made it through filter: 2
+     /// about to filter: 3
+     /// 6
+     /// ```
+     ///
+     /// Logging errors before discarding them:
+     ///
+     /// ```
+     /// let lines = ["1", "2", "a"];
+     ///
+     /// let sum: i32 = lines
+     ///     .iter()
+     ///     .map(|line| line.parse::<i32>())
+     ///     .inspect(|num| {
+     ///         if let Err(ref e) = *num {
+     ///             println!("Parsing error: {}", e);
+     ///         }
+     ///     })
+     ///     .filter_map(Result::ok)
+     ///     .sum();
+     ///
+     /// println!("Sum: {}", sum);
+     /// ```
+     ///
+     /// This will print:
+     ///
+     /// ```text
+     /// Parsing error: invalid digit found in string
+     /// Sum: 3
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn inspect<F>(self, f: F) -> Inspect<Self, F>
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item),
+     {
+         Inspect::new(self, f)
+     }
+ 
+     /// Borrows an iterator, rather than consuming it.
+     ///
+     /// This is useful to allow applying iterator adaptors while still
+     /// retaining ownership of the original iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let iter = a.iter();
+     ///
+     /// let sum: i32 = iter.take(5).fold(0, |acc, i| acc + i);
+     ///
+     /// assert_eq!(sum, 6);
+     ///
+     /// // if we try to use iter again, it won't work. The following line
+     /// // gives "error: use of moved value: `iter`
+     /// // assert_eq!(iter.next(), None);
+     ///
+     /// // let's try that again
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// // instead, we add in a .by_ref()
+     /// let sum: i32 = iter.by_ref().take(2).fold(0, |acc, i| acc + i);
+     ///
+     /// assert_eq!(sum, 3);
+     ///
+     /// // now this is just fine:
+     /// assert_eq!(iter.next(), Some(&3));
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn by_ref(&mut self) -> &mut Self
+     where
+         Self: Sized,
+     {
+         self
+     }
+ 
+     /// Transforms an iterator into a collection.
+     ///
+     /// `collect()` can take anything iterable, and turn it into a relevant
+     /// collection. This is one of the more powerful methods in the standard
+     /// library, used in a variety of contexts.
+     ///
+     /// The most basic pattern in which `collect()` is used is to turn one
+     /// collection into another. You take a collection, call [`iter`] on it,
+     /// do a bunch of transformations, and then `collect()` at the end.
+     ///
+     /// `collect()` can also create instances of types that are not typical
+     /// collections. For example, a [`String`] can be built from [`char`]s,
+     /// and an iterator of [`Result<T, E>`][`Result`] items can be collected
+     /// into `Result<Collection<T>, E>`. See the examples below for more.
+     ///
+     /// Because `collect()` is so general, it can cause problems with type
+     /// inference. As such, `collect()` is one of the few times you'll see
+     /// the syntax affectionately known as the 'turbofish': `::<>`. This
+     /// helps the inference algorithm understand specifically which collection
+     /// you're trying to collect into.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let doubled: Vec<i32> = a.iter()
+     ///                          .map(|&x| x * 2)
+     ///                          .collect();
+     ///
+     /// assert_eq!(vec![2, 4, 6], doubled);
+     /// ```
+     ///
+     /// Note that we needed the `: Vec<i32>` on the left-hand side. This is because
+     /// we could collect into, for example, a [`VecDeque<T>`] instead:
+     ///
+     /// [`VecDeque<T>`]: ../../std/collections/struct.VecDeque.html
+     ///
+     /// ```
+     /// use std::collections::VecDeque;
+     ///
+     /// let a = [1, 2, 3];
+     ///
+     /// let doubled: VecDeque<i32> = a.iter().map(|&x| x * 2).collect();
+     ///
+     /// assert_eq!(2, doubled[0]);
+     /// assert_eq!(4, doubled[1]);
+     /// assert_eq!(6, doubled[2]);
+     /// ```
+     ///
+     /// Using the 'turbofish' instead of annotating `doubled`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let doubled = a.iter().map(|x| x * 2).collect::<Vec<i32>>();
+     ///
+     /// assert_eq!(vec![2, 4, 6], doubled);
+     /// ```
+     ///
+     /// Because `collect()` only cares about what you're collecting into, you can
+     /// still use a partial type hint, `_`, with the turbofish:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let doubled = a.iter().map(|x| x * 2).collect::<Vec<_>>();
+     ///
+     /// assert_eq!(vec![2, 4, 6], doubled);
+     /// ```
+     ///
+     /// Using `collect()` to make a [`String`]:
+     ///
+     /// ```
+     /// let chars = ['g', 'd', 'k', 'k', 'n'];
+     ///
+     /// let hello: String = chars.iter()
+     ///     .map(|&x| x as u8)
+     ///     .map(|x| (x + 1) as char)
+     ///     .collect();
+     ///
+     /// assert_eq!("hello", hello);
+     /// ```
+     ///
+     /// If you have a list of [`Result<T, E>`][`Result`]s, you can use `collect()` to
+     /// see if any of them failed:
+     ///
+     /// ```
+     /// let results = [Ok(1), Err("nope"), Ok(3), Err("bad")];
+     ///
+     /// let result: Result<Vec<_>, &str> = results.iter().cloned().collect();
+     ///
+     /// // gives us the first error
+     /// assert_eq!(Err("nope"), result);
+     ///
+     /// let results = [Ok(1), Ok(3)];
+     ///
+     /// let result: Result<Vec<_>, &str> = results.iter().cloned().collect();
+     ///
+     /// // gives us the list of answers
+     /// assert_eq!(Ok(vec![1, 3]), result);
+     /// ```
+     ///
+     /// [`iter`]: Iterator::next
+     /// [`String`]: ../../std/string/struct.String.html
+     /// [`char`]: type@char
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[must_use = "if you really need to exhaust the iterator, consider `.for_each(drop)` instead"]
+     fn collect<B: FromIterator<Self::Item>>(self) -> B
+     where
+         Self: Sized,
+     {
+         FromIterator::from_iter(self)
+     }
+ 
+     /// Consumes an iterator, creating two collections from it.
+     ///
+     /// The predicate passed to `partition()` can return `true`, or `false`.
+     /// `partition()` returns a pair, all of the elements for which it returned
+     /// `true`, and all of the elements for which it returned `false`.
+     ///
+     /// See also [`is_partitioned()`] and [`partition_in_place()`].
+     ///
+     /// [`is_partitioned()`]: Iterator::is_partitioned
+     /// [`partition_in_place()`]: Iterator::partition_in_place
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let (even, odd): (Vec<i32>, Vec<i32>) = a
+     ///     .iter()
+     ///     .partition(|&n| n % 2 == 0);
+     ///
+     /// assert_eq!(even, vec![2]);
+     /// assert_eq!(odd, vec![1, 3]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn partition<B, F>(self, f: F) -> (B, B)
+     where
+         Self: Sized,
+         B: Default + Extend<Self::Item>,
+         F: FnMut(&Self::Item) -> bool,
+     {
+         #[inline]
+         fn extend<'a, T, B: Extend<T>>(
+             mut f: impl FnMut(&T) -> bool + 'a,
+             left: &'a mut B,
+             right: &'a mut B,
+         ) -> impl FnMut((), T) + 'a {
+             move |(), x| {
+                 if f(&x) {
+                     left.extend_one(x);
+                 } else {
+                     right.extend_one(x);
+                 }
+             }
+         }
+ 
+         let mut left: B = Default::default();
+         let mut right: B = Default::default();
+ 
+         self.fold((), extend(f, &mut left, &mut right));
+ 
+         (left, right)
+     }
+ 
+     /// Reorders the elements of this iterator *in-place* according to the given predicate,
+     /// such that all those that return `true` precede all those that return `false`.
+     /// Returns the number of `true` elements found.
+     ///
+     /// The relative order of partitioned items is not maintained.
+     ///
+     /// See also [`is_partitioned()`] and [`partition()`].
+     ///
+     /// [`is_partitioned()`]: Iterator::is_partitioned
+     /// [`partition()`]: Iterator::partition
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(iter_partition_in_place)]
+     ///
+     /// let mut a = [1, 2, 3, 4, 5, 6, 7];
+     ///
+     /// // Partition in-place between evens and odds
+     /// let i = a.iter_mut().partition_in_place(|&n| n % 2 == 0);
+     ///
+     /// assert_eq!(i, 3);
+     /// assert!(a[..i].iter().all(|&n| n % 2 == 0)); // evens
+     /// assert!(a[i..].iter().all(|&n| n % 2 == 1)); // odds
+     /// ```
+     #[unstable(feature = "iter_partition_in_place", reason = "new API", issue = "62543")]
+     fn partition_in_place<'a, T: 'a, P>(mut self, ref mut predicate: P) -> usize
+     where
+         Self: Sized + DoubleEndedIterator<Item = &'a mut T>,
+         P: FnMut(&T) -> bool,
+     {
+         // FIXME: should we worry about the count overflowing? The only way to have more than
+         // `usize::MAX` mutable references is with ZSTs, which aren't useful to partition...
+ 
+         // These closure "factory" functions exist to avoid genericity in `Self`.
+ 
+         #[inline]
+         fn is_false<'a, T>(
+             predicate: &'a mut impl FnMut(&T) -> bool,
+             true_count: &'a mut usize,
+         ) -> impl FnMut(&&mut T) -> bool + 'a {
+             move |x| {
+                 let p = predicate(&**x);
+                 *true_count += p as usize;
+                 !p
+             }
+         }
+ 
+         #[inline]
+         fn is_true<T>(predicate: &mut impl FnMut(&T) -> bool) -> impl FnMut(&&mut T) -> bool + '_ {
+             move |x| predicate(&**x)
+         }
+ 
+         // Repeatedly find the first `false` and swap it with the last `true`.
+         let mut true_count = 0;
+         while let Some(head) = self.find(is_false(predicate, &mut true_count)) {
+             if let Some(tail) = self.rfind(is_true(predicate)) {
+                 crate::mem::swap(head, tail);
+                 true_count += 1;
+             } else {
+                 break;
+             }
+         }
+         true_count
+     }
+ 
+     /// Checks if the elements of this iterator are partitioned according to the given predicate,
+     /// such that all those that return `true` precede all those that return `false`.
+     ///
+     /// See also [`partition()`] and [`partition_in_place()`].
+     ///
+     /// [`partition()`]: Iterator::partition
+     /// [`partition_in_place()`]: Iterator::partition_in_place
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(iter_is_partitioned)]
+     ///
+     /// assert!("Iterator".chars().is_partitioned(char::is_uppercase));
+     /// assert!(!"IntoIterator".chars().is_partitioned(char::is_uppercase));
+     /// ```
+     #[unstable(feature = "iter_is_partitioned", reason = "new API", issue = "62544")]
+     fn is_partitioned<P>(mut self, mut predicate: P) -> bool
+     where
+         Self: Sized,
+         P: FnMut(Self::Item) -> bool,
+     {
+         // Either all items test `true`, or the first clause stops at `false`
+         // and we check that there are no more `true` items after that.
+         self.all(&mut predicate) || !self.any(predicate)
+     }
+ 
+     /// An iterator method that applies a function as long as it returns
+     /// successfully, producing a single, final value.
+     ///
+     /// `try_fold()` takes two arguments: an initial value, and a closure with
+     /// two arguments: an 'accumulator', and an element. The closure either
+     /// returns successfully, with the value that the accumulator should have
+     /// for the next iteration, or it returns failure, with an error value that
+     /// is propagated back to the caller immediately (short-circuiting).
+     ///
+     /// The initial value is the value the accumulator will have on the first
+     /// call. If applying the closure succeeded against every element of the
+     /// iterator, `try_fold()` returns the final accumulator as success.
+     ///
+     /// Folding is useful whenever you have a collection of something, and want
+     /// to produce a single value from it.
+     ///
+     /// # Note to Implementors
+     ///
+     /// Several of the other (forward) methods have default implementations in
+     /// terms of this one, so try to implement this explicitly if it can
+     /// do something better than the default `for` loop implementation.
+     ///
+     /// In particular, try to have this call `try_fold()` on the internal parts
+     /// from which this iterator is composed. If multiple calls are needed,
+     /// the `?` operator may be convenient for chaining the accumulator value
+     /// along, but beware any invariants that need to be upheld before those
+     /// early returns. This is a `&mut self` method, so iteration needs to be
+     /// resumable after hitting an error here.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// // the checked sum of all of the elements of the array
+     /// let sum = a.iter().try_fold(0i8, |acc, &x| acc.checked_add(x));
+     ///
+     /// assert_eq!(sum, Some(6));
+     /// ```
+     ///
+     /// Short-circuiting:
+     ///
+     /// ```
+     /// let a = [10, 20, 30, 100, 40, 50];
+     /// let mut it = a.iter();
+     ///
+     /// // This sum overflows when adding the 100 element
+     /// let sum = it.try_fold(0i8, |acc, &x| acc.checked_add(x));
+     /// assert_eq!(sum, None);
+     ///
+     /// // Because it short-circuited, the remaining elements are still
+     /// // available through the iterator.
+     /// assert_eq!(it.len(), 2);
+     /// assert_eq!(it.next(), Some(&40));
+     /// ```
+     #[inline]
+     #[stable(feature = "iterator_try_fold", since = "1.27.0")]
+     fn try_fold<B, F, R>(&mut self, init: B, mut f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> R,
+         R: Try<Ok = B>,
+     {
+         let mut accum = init;
+         while let Some(x) = self.next() {
+             accum = f(accum, x)?;
+         }
+         try { accum }
+     }
+ 
+     /// An iterator method that applies a fallible function to each item in the
+     /// iterator, stopping at the first error and returning that error.
+     ///
+     /// This can also be thought of as the fallible form of [`for_each()`]
+     /// or as the stateless version of [`try_fold()`].
+     ///
+     /// [`for_each()`]: Iterator::for_each
+     /// [`try_fold()`]: Iterator::try_fold
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fs::rename;
+     /// use std::io::{stdout, Write};
+     /// use std::path::Path;
+     ///
+     /// let data = ["no_tea.txt", "stale_bread.json", "torrential_rain.png"];
+     ///
+     /// let res = data.iter().try_for_each(|x| writeln!(stdout(), "{}", x));
+     /// assert!(res.is_ok());
+     ///
+     /// let mut it = data.iter().cloned();
+     /// let res = it.try_for_each(|x| rename(x, Path::new(x).with_extension("old")));
+     /// assert!(res.is_err());
+     /// // It short-circuited, so the remaining items are still in the iterator:
+     /// assert_eq!(it.next(), Some("stale_bread.json"));
+     /// ```
+     #[inline]
+     #[stable(feature = "iterator_try_fold", since = "1.27.0")]
+     fn try_for_each<F, R>(&mut self, f: F) -> R
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> R,
+         R: Try<Ok = ()>,
+     {
+         #[inline]
+         fn call<T, R>(mut f: impl FnMut(T) -> R) -> impl FnMut((), T) -> R {
+             move |(), x| f(x)
+         }
+ 
+         self.try_fold((), call(f))
+     }
+ 
+     /// An iterator method that applies a function, producing a single, final value.
+     ///
+     /// `fold()` takes two arguments: an initial value, and a closure with two
+     /// arguments: an 'accumulator', and an element. The closure returns the value that
+     /// the accumulator should have for the next iteration.
+     ///
+     /// The initial value is the value the accumulator will have on the first
+     /// call.
+     ///
+     /// After applying this closure to every element of the iterator, `fold()`
+     /// returns the accumulator.
+     ///
+     /// This operation is sometimes called 'reduce' or 'inject'.
+     ///
+     /// Folding is useful whenever you have a collection of something, and want
+     /// to produce a single value from it.
+     ///
+     /// Note: `fold()`, and similar methods that traverse the entire iterator,
+     /// may not terminate for infinite iterators, even on traits for which a
+     /// result is determinable in finite time.
+     ///
+     /// # Note to Implementors
+     ///
+     /// Several of the other (forward) methods have default implementations in
+     /// terms of this one, so try to implement this explicitly if it can
+     /// do something better than the default `for` loop implementation.
+     ///
+     /// In particular, try to have this call `fold()` on the internal parts
+     /// from which this iterator is composed.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// // the sum of all of the elements of the array
+     /// let sum = a.iter().fold(0, |acc, x| acc + x);
+     ///
+     /// assert_eq!(sum, 6);
+     /// ```
+     ///
+     /// Let's walk through each step of the iteration here:
+     ///
+     /// | element | acc | x | result |
+     /// |---------|-----|---|--------|
+     /// |         | 0   |   |        |
+     /// | 1       | 0   | 1 | 1      |
+     /// | 2       | 1   | 2 | 3      |
+     /// | 3       | 3   | 3 | 6      |
+     ///
+     /// And so, our final result, `6`.
+     ///
+     /// It's common for people who haven't used iterators a lot to
+     /// use a `for` loop with a list of things to build up a result. Those
+     /// can be turned into `fold()`s:
+     ///
+     /// [`for`]: ../../book/ch03-05-control-flow.html#looping-through-a-collection-with-for
+     ///
+     /// ```
+     /// let numbers = [1, 2, 3, 4, 5];
+     ///
+     /// let mut result = 0;
+     ///
+     /// // for loop:
+     /// for i in &numbers {
+     ///     result = result + i;
+     /// }
+     ///
+     /// // fold:
+     /// let result2 = numbers.iter().fold(0, |acc, &x| acc + x);
+     ///
+     /// // they're the same
+     /// assert_eq!(result, result2);
+     /// ```
+     #[doc(alias = "reduce")]
+     #[doc(alias = "inject")]
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn fold<B, F>(mut self, init: B, mut f: F) -> B
+     where
+         Self: Sized,
+         F: FnMut(B, Self::Item) -> B,
+     {
+         let mut accum = init;
+         while let Some(x) = self.next() {
+             accum = f(accum, x);
+         }
+         accum
+     }
+ 
+     /// The same as [`fold()`], but uses the first element in the
+     /// iterator as the initial value, folding every subsequent element into it.
+     /// If the iterator is empty, return [`None`]; otherwise, return the result
+     /// of the fold.
+     ///
+     /// [`fold()`]: Iterator::fold
+     ///
+     /// # Example
+     ///
+     /// Find the maximum value:
+     ///
+     /// ```
+     /// #![feature(iterator_fold_self)]
+     ///
+     /// fn find_max<I>(iter: I) -> Option<I::Item>
+     ///     where I: Iterator,
+     ///           I::Item: Ord,
+     /// {
+     ///     iter.fold_first(|a, b| {
+     ///         if a >= b { a } else { b }
+     ///     })
+     /// }
+     /// let a = [10, 20, 5, -23, 0];
+     /// let b: [u32; 0] = [];
+     ///
+     /// assert_eq!(find_max(a.iter()), Some(&20));
+     /// assert_eq!(find_max(b.iter()), None);
+     /// ```
+     #[inline]
+     #[unstable(feature = "iterator_fold_self", issue = "68125")]
+     fn fold_first<F>(mut self, f: F) -> Option<Self::Item>
+     where
+         Self: Sized,
+         F: FnMut(Self::Item, Self::Item) -> Self::Item,
+     {
+         let first = self.next()?;
+         Some(self.fold(first, f))
+     }
+ 
+     /// Tests if every element of the iterator matches a predicate.
+     ///
+     /// `all()` takes a closure that returns `true` or `false`. It applies
+     /// this closure to each element of the iterator, and if they all return
+     /// `true`, then so does `all()`. If any of them return `false`, it
+     /// returns `false`.
+     ///
+     /// `all()` is short-circuiting; in other words, it will stop processing
+     /// as soon as it finds a `false`, given that no matter what else happens,
+     /// the result will also be `false`.
+     ///
+     /// An empty iterator returns `true`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// assert!(a.iter().all(|&x| x > 0));
+     ///
+     /// assert!(!a.iter().all(|&x| x > 2));
+     /// ```
+     ///
+     /// Stopping at the first `false`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert!(!iter.all(|&x| x != 2));
+     ///
+     /// // we can still use `iter`, as there are more elements.
+     /// assert_eq!(iter.next(), Some(&3));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn all<F>(&mut self, f: F) -> bool
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> bool,
+     {
+         #[inline]
+         fn check<T>(mut f: impl FnMut(T) -> bool) -> impl FnMut((), T) -> ControlFlow<()> {
+             move |(), x| {
+                 if f(x) { ControlFlow::CONTINUE } else { ControlFlow::BREAK }
+             }
+         }
+         self.try_fold((), check(f)) == ControlFlow::CONTINUE
+     }
+ 
+     /// Tests if any element of the iterator matches a predicate.
+     ///
+     /// `any()` takes a closure that returns `true` or `false`. It applies
+     /// this closure to each element of the iterator, and if any of them return
+     /// `true`, then so does `any()`. If they all return `false`, it
+     /// returns `false`.
+     ///
+     /// `any()` is short-circuiting; in other words, it will stop processing
+     /// as soon as it finds a `true`, given that no matter what else happens,
+     /// the result will also be `true`.
+     ///
+     /// An empty iterator returns `false`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// assert!(a.iter().any(|&x| x > 0));
+     ///
+     /// assert!(!a.iter().any(|&x| x > 5));
+     /// ```
+     ///
+     /// Stopping at the first `true`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert!(iter.any(|&x| x != 2));
+     ///
+     /// // we can still use `iter`, as there are more elements.
+     /// assert_eq!(iter.next(), Some(&2));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn any<F>(&mut self, f: F) -> bool
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> bool,
+     {
+         #[inline]
+         fn check<T>(mut f: impl FnMut(T) -> bool) -> impl FnMut((), T) -> ControlFlow<()> {
+             move |(), x| {
+                 if f(x) { ControlFlow::BREAK } else { ControlFlow::CONTINUE }
+             }
+         }
+ 
+         self.try_fold((), check(f)) == ControlFlow::BREAK
+     }
+ 
+     /// Searches for an element of an iterator that satisfies a predicate.
+     ///
+     /// `find()` takes a closure that returns `true` or `false`. It applies
+     /// this closure to each element of the iterator, and if any of them return
+     /// `true`, then `find()` returns [`Some(element)`]. If they all return
+     /// `false`, it returns [`None`].
+     ///
+     /// `find()` is short-circuiting; in other words, it will stop processing
+     /// as soon as the closure returns `true`.
+     ///
+     /// Because `find()` takes a reference, and many iterators iterate over
+     /// references, this leads to a possibly confusing situation where the
+     /// argument is a double reference. You can see this effect in the
+     /// examples below, with `&&x`.
+     ///
+     /// [`Some(element)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// assert_eq!(a.iter().find(|&&x| x == 2), Some(&2));
+     ///
+     /// assert_eq!(a.iter().find(|&&x| x == 5), None);
+     /// ```
+     ///
+     /// Stopping at the first `true`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.find(|&&x| x == 2), Some(&2));
+     ///
+     /// // we can still use `iter`, as there are more elements.
+     /// assert_eq!(iter.next(), Some(&3));
+     /// ```
+     ///
+     /// Note that `iter.find(f)` is equivalent to `iter.filter(f).next()`.
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         Self: Sized,
+         P: FnMut(&Self::Item) -> bool,
+     {
+         #[inline]
+         fn check<T>(mut predicate: impl FnMut(&T) -> bool) -> impl FnMut((), T) -> ControlFlow<T> {
+             move |(), x| {
+                 if predicate(&x) { ControlFlow::Break(x) } else { ControlFlow::CONTINUE }
+             }
+         }
+ 
+         self.try_fold((), check(predicate)).break_value()
+     }
+ 
+     /// Applies function to the elements of iterator and returns
+     /// the first non-none result.
+     ///
+     /// `iter.find_map(f)` is equivalent to `iter.filter_map(f).next()`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = ["lol", "NaN", "2", "5"];
+     ///
+     /// let first_number = a.iter().find_map(|s| s.parse().ok());
+     ///
+     /// assert_eq!(first_number, Some(2));
+     /// ```
+     #[inline]
+     #[stable(feature = "iterator_find_map", since = "1.30.0")]
+     fn find_map<B, F>(&mut self, f: F) -> Option<B>
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> Option<B>,
+     {
+         #[inline]
+         fn check<T, B>(mut f: impl FnMut(T) -> Option<B>) -> impl FnMut((), T) -> ControlFlow<B> {
+             move |(), x| match f(x) {
+                 Some(x) => ControlFlow::Break(x),
+                 None => ControlFlow::CONTINUE,
+             }
+         }
+ 
+         self.try_fold((), check(f)).break_value()
+     }
+ 
+     /// Applies function to the elements of iterator and returns
+     /// the first true result or the first error.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(try_find)]
+     ///
+     /// let a = ["1", "2", "lol", "NaN", "5"];
+     ///
+     /// let is_my_num = |s: &str, search: i32| -> Result<bool, std::num::ParseIntError> {
+     ///     Ok(s.parse::<i32>()?  == search)
+     /// };
+     ///
+     /// let result = a.iter().try_find(|&&s| is_my_num(s, 2));
+     /// assert_eq!(result, Ok(Some(&"2")));
+     ///
+     /// let result = a.iter().try_find(|&&s| is_my_num(s, 5));
+     /// assert!(result.is_err());
+     /// ```
+     #[inline]
+     #[unstable(feature = "try_find", reason = "new API", issue = "63178")]
+     fn try_find<F, R>(&mut self, f: F) -> Result<Option<Self::Item>, R::Error>
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item) -> R,
+         R: Try<Ok = bool>,
+     {
+         #[inline]
+         fn check<F, T, R>(mut f: F) -> impl FnMut((), T) -> ControlFlow<Result<T, R::Error>>
+         where
+             F: FnMut(&T) -> R,
+             R: Try<Ok = bool>,
+         {
+             move |(), x| match f(&x).into_result() {
+                 Ok(false) => ControlFlow::CONTINUE,
+                 Ok(true) => ControlFlow::Break(Ok(x)),
+                 Err(x) => ControlFlow::Break(Err(x)),
+             }
+         }
+ 
+         self.try_fold((), check(f)).break_value().transpose()
+     }
+ 
+     /// Searches for an element in an iterator, returning its index.
+     ///
+     /// `position()` takes a closure that returns `true` or `false`. It applies
+     /// this closure to each element of the iterator, and if one of them
+     /// returns `true`, then `position()` returns [`Some(index)`]. If all of
+     /// them return `false`, it returns [`None`].
+     ///
+     /// `position()` is short-circuiting; in other words, it will stop
+     /// processing as soon as it finds a `true`.
+     ///
+     /// # Overflow Behavior
+     ///
+     /// The method does no guarding against overflows, so if there are more
+     /// than [`usize::MAX`] non-matching elements, it either produces the wrong
+     /// result or panics. If debug assertions are enabled, a panic is
+     /// guaranteed.
+     ///
+     /// # Panics
+     ///
+     /// This function might panic if the iterator has more than `usize::MAX`
+     /// non-matching elements.
+     ///
+     /// [`Some(index)`]: Some
+     /// [`usize::MAX`]: crate::usize::MAX
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// assert_eq!(a.iter().position(|&x| x == 2), Some(1));
+     ///
+     /// assert_eq!(a.iter().position(|&x| x == 5), None);
+     /// ```
+     ///
+     /// Stopping at the first `true`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3, 4];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.position(|&x| x >= 2), Some(1));
+     ///
+     /// // we can still use `iter`, as there are more elements.
+     /// assert_eq!(iter.next(), Some(&3));
+     ///
+     /// // The returned index depends on iterator state
+     /// assert_eq!(iter.position(|&x| x == 4), Some(0));
+     ///
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn position<P>(&mut self, predicate: P) -> Option<usize>
+     where
+         Self: Sized,
+         P: FnMut(Self::Item) -> bool,
+     {
+         #[inline]
+         fn check<T>(
+             mut predicate: impl FnMut(T) -> bool,
+         ) -> impl FnMut(usize, T) -> ControlFlow<usize, usize> {
+             // The addition might panic on overflow
+             move |i, x| {
+                 if predicate(x) {
+                     ControlFlow::Break(i)
+                 } else {
+                     ControlFlow::Continue(Add::add(i, 1))
+                 }
+             }
+         }
+ 
+         self.try_fold(0, check(predicate)).break_value()
+     }
+ 
+     /// Searches for an element in an iterator from the right, returning its
+     /// index.
+     ///
+     /// `rposition()` takes a closure that returns `true` or `false`. It applies
+     /// this closure to each element of the iterator, starting from the end,
+     /// and if one of them returns `true`, then `rposition()` returns
+     /// [`Some(index)`]. If all of them return `false`, it returns [`None`].
+     ///
+     /// `rposition()` is short-circuiting; in other words, it will stop
+     /// processing as soon as it finds a `true`.
+     ///
+     /// [`Some(index)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// assert_eq!(a.iter().rposition(|&x| x == 3), Some(2));
+     ///
+     /// assert_eq!(a.iter().rposition(|&x| x == 5), None);
+     /// ```
+     ///
+     /// Stopping at the first `true`:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter();
+     ///
+     /// assert_eq!(iter.rposition(|&x| x == 2), Some(1));
+     ///
+     /// // we can still use `iter`, as there are more elements.
+     /// assert_eq!(iter.next(), Some(&1));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn rposition<P>(&mut self, predicate: P) -> Option<usize>
+     where
+         P: FnMut(Self::Item) -> bool,
+         Self: Sized + ExactSizeIterator + DoubleEndedIterator,
+     {
+         // No need for an overflow check here, because `ExactSizeIterator`
+         // implies that the number of elements fits into a `usize`.
+         #[inline]
+         fn check<T>(
+             mut predicate: impl FnMut(T) -> bool,
+         ) -> impl FnMut(usize, T) -> ControlFlow<usize, usize> {
+             move |i, x| {
+                 let i = i - 1;
+                 if predicate(x) { ControlFlow::Break(i) } else { ControlFlow::Continue(i) }
+             }
+         }
+ 
+         let n = self.len();
+         self.try_rfold(n, check(predicate)).break_value()
+     }
+ 
+     /// Returns the maximum element of an iterator.
+     ///
+     /// If several elements are equally maximum, the last element is
+     /// returned. If the iterator is empty, [`None`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// let b: Vec<u32> = Vec::new();
+     ///
+     /// assert_eq!(a.iter().max(), Some(&3));
+     /// assert_eq!(b.iter().max(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn max(self) -> Option<Self::Item>
+     where
+         Self: Sized,
+         Self::Item: Ord,
+     {
+         self.max_by(Ord::cmp)
+     }
+ 
+     /// Returns the minimum element of an iterator.
+     ///
+     /// If several elements are equally minimum, the first element is
+     /// returned. If the iterator is empty, [`None`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// let b: Vec<u32> = Vec::new();
+     ///
+     /// assert_eq!(a.iter().min(), Some(&1));
+     /// assert_eq!(b.iter().min(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn min(self) -> Option<Self::Item>
+     where
+         Self: Sized,
+         Self::Item: Ord,
+     {
+         self.min_by(Ord::cmp)
+     }
+ 
+     /// Returns the element that gives the maximum value from the
+     /// specified function.
+     ///
+     /// If several elements are equally maximum, the last element is
+     /// returned. If the iterator is empty, [`None`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [-3_i32, 0, 1, 5, -10];
+     /// assert_eq!(*a.iter().max_by_key(|x| x.abs()).unwrap(), -10);
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_cmp_by_key", since = "1.6.0")]
+     fn max_by_key<B: Ord, F>(self, f: F) -> Option<Self::Item>
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item) -> B,
+     {
+         #[inline]
+         fn key<T, B>(mut f: impl FnMut(&T) -> B) -> impl FnMut(T) -> (B, T) {
+             move |x| (f(&x), x)
+         }
+ 
+         #[inline]
+         fn compare<T, B: Ord>((x_p, _): &(B, T), (y_p, _): &(B, T)) -> Ordering {
+             x_p.cmp(y_p)
+         }
+ 
+         let (_, x) = self.map(key(f)).max_by(compare)?;
+         Some(x)
+     }
+ 
+     /// Returns the element that gives the maximum value with respect to the
+     /// specified comparison function.
+     ///
+     /// If several elements are equally maximum, the last element is
+     /// returned. If the iterator is empty, [`None`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [-3_i32, 0, 1, 5, -10];
+     /// assert_eq!(*a.iter().max_by(|x, y| x.cmp(y)).unwrap(), 5);
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_max_by", since = "1.15.0")]
+     fn max_by<F>(self, compare: F) -> Option<Self::Item>
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item, &Self::Item) -> Ordering,
+     {
+         #[inline]
+         fn fold<T>(mut compare: impl FnMut(&T, &T) -> Ordering) -> impl FnMut(T, T) -> T {
+             move |x, y| cmp::max_by(x, y, &mut compare)
+         }
+ 
+         self.fold_first(fold(compare))
+     }
+ 
+     /// Returns the element that gives the minimum value from the
+     /// specified function.
+     ///
+     /// If several elements are equally minimum, the first element is
+     /// returned. If the iterator is empty, [`None`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [-3_i32, 0, 1, 5, -10];
+     /// assert_eq!(*a.iter().min_by_key(|x| x.abs()).unwrap(), 0);
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_cmp_by_key", since = "1.6.0")]
+     fn min_by_key<B: Ord, F>(self, f: F) -> Option<Self::Item>
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item) -> B,
+     {
+         #[inline]
+         fn key<T, B>(mut f: impl FnMut(&T) -> B) -> impl FnMut(T) -> (B, T) {
+             move |x| (f(&x), x)
+         }
+ 
+         #[inline]
+         fn compare<T, B: Ord>((x_p, _): &(B, T), (y_p, _): &(B, T)) -> Ordering {
+             x_p.cmp(y_p)
+         }
+ 
+         let (_, x) = self.map(key(f)).min_by(compare)?;
+         Some(x)
+     }
+ 
+     /// Returns the element that gives the minimum value with respect to the
+     /// specified comparison function.
+     ///
+     /// If several elements are equally minimum, the first element is
+     /// returned. If the iterator is empty, [`None`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [-3_i32, 0, 1, 5, -10];
+     /// assert_eq!(*a.iter().min_by(|x, y| x.cmp(y)).unwrap(), -10);
+     /// ```
+     #[inline]
+     #[stable(feature = "iter_min_by", since = "1.15.0")]
+     fn min_by<F>(self, compare: F) -> Option<Self::Item>
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item, &Self::Item) -> Ordering,
+     {
+         #[inline]
+         fn fold<T>(mut compare: impl FnMut(&T, &T) -> Ordering) -> impl FnMut(T, T) -> T {
+             move |x, y| cmp::min_by(x, y, &mut compare)
+         }
+ 
+         self.fold_first(fold(compare))
+     }
+ 
+     /// Reverses an iterator's direction.
+     ///
+     /// Usually, iterators iterate from left to right. After using `rev()`,
+     /// an iterator will instead iterate from right to left.
+     ///
+     /// This is only possible if the iterator has an end, so `rev()` only
+     /// works on [`DoubleEndedIterator`]s.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut iter = a.iter().rev();
+     ///
+     /// assert_eq!(iter.next(), Some(&3));
+     /// assert_eq!(iter.next(), Some(&2));
+     /// assert_eq!(iter.next(), Some(&1));
+     ///
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn rev(self) -> Rev<Self>
+     where
+         Self: Sized + DoubleEndedIterator,
+     {
+         Rev::new(self)
+     }
+ 
+     /// Converts an iterator of pairs into a pair of containers.
+     ///
+     /// `unzip()` consumes an entire iterator of pairs, producing two
+     /// collections: one from the left elements of the pairs, and one
+     /// from the right elements.
+     ///
+     /// This function is, in some sense, the opposite of [`zip`].
+     ///
+     /// [`zip`]: Iterator::zip
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [(1, 2), (3, 4)];
+     ///
+     /// let (left, right): (Vec<_>, Vec<_>) = a.iter().cloned().unzip();
+     ///
+     /// assert_eq!(left, [1, 3]);
+     /// assert_eq!(right, [2, 4]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn unzip<A, B, FromA, FromB>(self) -> (FromA, FromB)
+     where
+         FromA: Default + Extend<A>,
+         FromB: Default + Extend<B>,
+         Self: Sized + Iterator<Item = (A, B)>,
+     {
+         fn extend<'a, A, B>(
+             ts: &'a mut impl Extend<A>,
+             us: &'a mut impl Extend<B>,
+         ) -> impl FnMut((), (A, B)) + 'a {
+             move |(), (t, u)| {
+                 ts.extend_one(t);
+                 us.extend_one(u);
+             }
+         }
+ 
+         let mut ts: FromA = Default::default();
+         let mut us: FromB = Default::default();
+ 
+         let (lower_bound, _) = self.size_hint();
+         if lower_bound > 0 {
+             ts.extend_reserve(lower_bound);
+             us.extend_reserve(lower_bound);
+         }
+ 
+         self.fold((), extend(&mut ts, &mut us));
+ 
+         (ts, us)
+     }
+ 
+     /// Creates an iterator which copies all of its elements.
+     ///
+     /// This is useful when you have an iterator over `&T`, but you need an
+     /// iterator over `T`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let v_copied: Vec<_> = a.iter().copied().collect();
+     ///
+     /// // copied is the same as .map(|&x| x)
+     /// let v_map: Vec<_> = a.iter().map(|&x| x).collect();
+     ///
+     /// assert_eq!(v_copied, vec![1, 2, 3]);
+     /// assert_eq!(v_map, vec![1, 2, 3]);
+     /// ```
+     #[stable(feature = "iter_copied", since = "1.36.0")]
+     fn copied<'a, T: 'a>(self) -> Copied<Self>
+     where
+         Self: Sized + Iterator<Item = &'a T>,
+         T: Copy,
+     {
+         Copied::new(self)
+     }
+ 
+     /// Creates an iterator which [`clone`]s all of its elements.
+     ///
+     /// This is useful when you have an iterator over `&T`, but you need an
+     /// iterator over `T`.
+     ///
+     /// [`clone`]: Clone::clone
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let v_cloned: Vec<_> = a.iter().cloned().collect();
+     ///
+     /// // cloned is the same as .map(|&x| x), for integers
+     /// let v_map: Vec<_> = a.iter().map(|&x| x).collect();
+     ///
+     /// assert_eq!(v_cloned, vec![1, 2, 3]);
+     /// assert_eq!(v_map, vec![1, 2, 3]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn cloned<'a, T: 'a>(self) -> Cloned<Self>
+     where
+         Self: Sized + Iterator<Item = &'a T>,
+         T: Clone,
+     {
+         Cloned::new(self)
+     }
+ 
+     /// Repeats an iterator endlessly.
+     ///
+     /// Instead of stopping at [`None`], the iterator will instead start again,
+     /// from the beginning. After iterating again, it will start at the
+     /// beginning again. And again. And again. Forever.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     ///
+     /// let mut it = a.iter().cycle();
+     ///
+     /// assert_eq!(it.next(), Some(&1));
+     /// assert_eq!(it.next(), Some(&2));
+     /// assert_eq!(it.next(), Some(&3));
+     /// assert_eq!(it.next(), Some(&1));
+     /// assert_eq!(it.next(), Some(&2));
+     /// assert_eq!(it.next(), Some(&3));
+     /// assert_eq!(it.next(), Some(&1));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     fn cycle(self) -> Cycle<Self>
+     where
+         Self: Sized + Clone,
+     {
+         Cycle::new(self)
+     }
+ 
+     /// Sums the elements of an iterator.
+     ///
+     /// Takes each element, adds them together, and returns the result.
+     ///
+     /// An empty iterator returns the zero value of the type.
+     ///
+     /// # Panics
+     ///
+     /// When calling `sum()` and a primitive integer type is being returned, this
+     /// method will panic if the computation overflows and debug assertions are
+     /// enabled.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// let sum: i32 = a.iter().sum();
+     ///
+     /// assert_eq!(sum, 6);
+     /// ```
+     #[stable(feature = "iter_arith", since = "1.11.0")]
+     fn sum<S>(self) -> S
+     where
+         Self: Sized,
+         S: Sum<Self::Item>,
+     {
+         Sum::sum(self)
+     }
+ 
+     /// Iterates over the entire iterator, multiplying all the elements
+     ///
+     /// An empty iterator returns the one value of the type.
+     ///
+     /// # Panics
+     ///
+     /// When calling `product()` and a primitive integer type is being returned,
+     /// method will panic if the computation overflows and debug assertions are
+     /// enabled.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// fn factorial(n: u32) -> u32 {
+     ///     (1..=n).product()
+     /// }
+     /// assert_eq!(factorial(0), 1);
+     /// assert_eq!(factorial(1), 1);
+     /// assert_eq!(factorial(5), 120);
+     /// ```
+     #[stable(feature = "iter_arith", since = "1.11.0")]
+     fn product<P>(self) -> P
+     where
+         Self: Sized,
+         P: Product<Self::Item>,
+     {
+         Product::product(self)
+     }
+ 
+     /// [Lexicographically](Ord#lexicographical-comparison) compares the elements of this [`Iterator`] with those
+     /// of another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// assert_eq!([1].iter().cmp([1].iter()), Ordering::Equal);
+     /// assert_eq!([1].iter().cmp([1, 2].iter()), Ordering::Less);
+     /// assert_eq!([1, 2].iter().cmp([1].iter()), Ordering::Greater);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn cmp<I>(self, other: I) -> Ordering
+     where
+         I: IntoIterator<Item = Self::Item>,
+         Self::Item: Ord,
+         Self: Sized,
+     {
+         self.cmp_by(other, |x, y| x.cmp(&y))
+     }
+ 
+     /// [Lexicographically](Ord#lexicographical-comparison) compares the elements of this [`Iterator`] with those
+     /// of another with respect to the specified comparison function.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(iter_order_by)]
+     ///
+     /// use std::cmp::Ordering;
+     ///
+     /// let xs = [1, 2, 3, 4];
+     /// let ys = [1, 4, 9, 16];
+     ///
+     /// assert_eq!(xs.iter().cmp_by(&ys, |&x, &y| x.cmp(&y)), Ordering::Less);
+     /// assert_eq!(xs.iter().cmp_by(&ys, |&x, &y| (x * x).cmp(&y)), Ordering::Equal);
+     /// assert_eq!(xs.iter().cmp_by(&ys, |&x, &y| (2 * x).cmp(&y)), Ordering::Greater);
+     /// ```
+     #[unstable(feature = "iter_order_by", issue = "64295")]
+     fn cmp_by<I, F>(mut self, other: I, mut cmp: F) -> Ordering
+     where
+         Self: Sized,
+         I: IntoIterator,
+         F: FnMut(Self::Item, I::Item) -> Ordering,
+     {
+         let mut other = other.into_iter();
+ 
+         loop {
+             let x = match self.next() {
+                 None => {
+                     if other.next().is_none() {
+                         return Ordering::Equal;
+                     } else {
+                         return Ordering::Less;
+                     }
+                 }
+                 Some(val) => val,
+             };
+ 
+             let y = match other.next() {
+                 None => return Ordering::Greater,
+                 Some(val) => val,
+             };
+ 
+             match cmp(x, y) {
+                 Ordering::Equal => (),
+                 non_eq => return non_eq,
+             }
+         }
+     }
+ 
+     /// [Lexicographically](Ord#lexicographical-comparison) compares the elements of this [`Iterator`] with those
+     /// of another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::cmp::Ordering;
+     ///
+     /// assert_eq!([1.].iter().partial_cmp([1.].iter()), Some(Ordering::Equal));
+     /// assert_eq!([1.].iter().partial_cmp([1., 2.].iter()), Some(Ordering::Less));
+     /// assert_eq!([1., 2.].iter().partial_cmp([1.].iter()), Some(Ordering::Greater));
+     ///
+     /// assert_eq!([f64::NAN].iter().partial_cmp([1.].iter()), None);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn partial_cmp<I>(self, other: I) -> Option<Ordering>
+     where
+         I: IntoIterator,
+         Self::Item: PartialOrd<I::Item>,
+         Self: Sized,
+     {
+         self.partial_cmp_by(other, |x, y| x.partial_cmp(&y))
+     }
+ 
+     /// [Lexicographically](Ord#lexicographical-comparison) compares the elements of this [`Iterator`] with those
+     /// of another with respect to the specified comparison function.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(iter_order_by)]
+     ///
+     /// use std::cmp::Ordering;
+     ///
+     /// let xs = [1.0, 2.0, 3.0, 4.0];
+     /// let ys = [1.0, 4.0, 9.0, 16.0];
+     ///
+     /// assert_eq!(
+     ///     xs.iter().partial_cmp_by(&ys, |&x, &y| x.partial_cmp(&y)),
+     ///     Some(Ordering::Less)
+     /// );
+     /// assert_eq!(
+     ///     xs.iter().partial_cmp_by(&ys, |&x, &y| (x * x).partial_cmp(&y)),
+     ///     Some(Ordering::Equal)
+     /// );
+     /// assert_eq!(
+     ///     xs.iter().partial_cmp_by(&ys, |&x, &y| (2.0 * x).partial_cmp(&y)),
+     ///     Some(Ordering::Greater)
+     /// );
+     /// ```
+     #[unstable(feature = "iter_order_by", issue = "64295")]
+     fn partial_cmp_by<I, F>(mut self, other: I, mut partial_cmp: F) -> Option<Ordering>
+     where
+         Self: Sized,
+         I: IntoIterator,
+         F: FnMut(Self::Item, I::Item) -> Option<Ordering>,
+     {
+         let mut other = other.into_iter();
+ 
+         loop {
+             let x = match self.next() {
+                 None => {
+                     if other.next().is_none() {
+                         return Some(Ordering::Equal);
+                     } else {
+                         return Some(Ordering::Less);
+                     }
+                 }
+                 Some(val) => val,
+             };
+ 
+             let y = match other.next() {
+                 None => return Some(Ordering::Greater),
+                 Some(val) => val,
+             };
+ 
+             match partial_cmp(x, y) {
+                 Some(Ordering::Equal) => (),
+                 non_eq => return non_eq,
+             }
+         }
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are equal to those of
+     /// another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!([1].iter().eq([1].iter()), true);
+     /// assert_eq!([1].iter().eq([1, 2].iter()), false);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn eq<I>(self, other: I) -> bool
+     where
+         I: IntoIterator,
+         Self::Item: PartialEq<I::Item>,
+         Self: Sized,
+     {
+         self.eq_by(other, |x, y| x == y)
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are equal to those of
+     /// another with respect to the specified equality function.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(iter_order_by)]
+     ///
+     /// let xs = [1, 2, 3, 4];
+     /// let ys = [1, 4, 9, 16];
+     ///
+     /// assert!(xs.iter().eq_by(&ys, |&x, &y| x * x == y));
+     /// ```
+     #[unstable(feature = "iter_order_by", issue = "64295")]
+     fn eq_by<I, F>(mut self, other: I, mut eq: F) -> bool
+     where
+         Self: Sized,
+         I: IntoIterator,
+         F: FnMut(Self::Item, I::Item) -> bool,
+     {
+         let mut other = other.into_iter();
+ 
+         loop {
+             let x = match self.next() {
+                 None => return other.next().is_none(),
+                 Some(val) => val,
+             };
+ 
+             let y = match other.next() {
+                 None => return false,
+                 Some(val) => val,
+             };
+ 
+             if !eq(x, y) {
+                 return false;
+             }
+         }
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are unequal to those of
+     /// another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!([1].iter().ne([1].iter()), false);
+     /// assert_eq!([1].iter().ne([1, 2].iter()), true);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn ne<I>(self, other: I) -> bool
+     where
+         I: IntoIterator,
+         Self::Item: PartialEq<I::Item>,
+         Self: Sized,
+     {
+         !self.eq(other)
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are [lexicographically](Ord#lexicographical-comparison)
+     /// less than those of another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!([1].iter().lt([1].iter()), false);
+     /// assert_eq!([1].iter().lt([1, 2].iter()), true);
+     /// assert_eq!([1, 2].iter().lt([1].iter()), false);
+     /// assert_eq!([1, 2].iter().lt([1, 2].iter()), false);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn lt<I>(self, other: I) -> bool
+     where
+         I: IntoIterator,
+         Self::Item: PartialOrd<I::Item>,
+         Self: Sized,
+     {
+         self.partial_cmp(other) == Some(Ordering::Less)
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are [lexicographically](Ord#lexicographical-comparison)
+     /// less or equal to those of another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!([1].iter().le([1].iter()), true);
+     /// assert_eq!([1].iter().le([1, 2].iter()), true);
+     /// assert_eq!([1, 2].iter().le([1].iter()), false);
+     /// assert_eq!([1, 2].iter().le([1, 2].iter()), true);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn le<I>(self, other: I) -> bool
+     where
+         I: IntoIterator,
+         Self::Item: PartialOrd<I::Item>,
+         Self: Sized,
+     {
+         matches!(self.partial_cmp(other), Some(Ordering::Less | Ordering::Equal))
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are [lexicographically](Ord#lexicographical-comparison)
+     /// greater than those of another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!([1].iter().gt([1].iter()), false);
+     /// assert_eq!([1].iter().gt([1, 2].iter()), false);
+     /// assert_eq!([1, 2].iter().gt([1].iter()), true);
+     /// assert_eq!([1, 2].iter().gt([1, 2].iter()), false);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn gt<I>(self, other: I) -> bool
+     where
+         I: IntoIterator,
+         Self::Item: PartialOrd<I::Item>,
+         Self: Sized,
+     {
+         self.partial_cmp(other) == Some(Ordering::Greater)
+     }
+ 
+     /// Determines if the elements of this [`Iterator`] are [lexicographically](Ord#lexicographical-comparison)
+     /// greater than or equal to those of another.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!([1].iter().ge([1].iter()), true);
+     /// assert_eq!([1].iter().ge([1, 2].iter()), false);
+     /// assert_eq!([1, 2].iter().ge([1].iter()), true);
+     /// assert_eq!([1, 2].iter().ge([1, 2].iter()), true);
+     /// ```
+     #[stable(feature = "iter_order", since = "1.5.0")]
+     fn ge<I>(self, other: I) -> bool
+     where
+         I: IntoIterator,
+         Self::Item: PartialOrd<I::Item>,
+         Self: Sized,
+     {
+         matches!(self.partial_cmp(other), Some(Ordering::Greater | Ordering::Equal))
+     }
+ 
+     /// Checks if the elements of this iterator are sorted.
+     ///
+     /// That is, for each element `a` and its following element `b`, `a <= b` must hold. If the
+     /// iterator yields exactly zero or one element, `true` is returned.
+     ///
+     /// Note that if `Self::Item` is only `PartialOrd`, but not `Ord`, the above definition
+     /// implies that this function returns `false` if any two consecutive items are not
+     /// comparable.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(is_sorted)]
+     ///
+     /// assert!([1, 2, 2, 9].iter().is_sorted());
+     /// assert!(![1, 3, 2, 4].iter().is_sorted());
+     /// assert!([0].iter().is_sorted());
+     /// assert!(std::iter::empty::<i32>().is_sorted());
+     /// assert!(![0.0, 1.0, f32::NAN].iter().is_sorted());
+     /// ```
+     #[inline]
+     #[unstable(feature = "is_sorted", reason = "new API", issue = "53485")]
+     fn is_sorted(self) -> bool
+     where
+         Self: Sized,
+         Self::Item: PartialOrd,
+     {
+         self.is_sorted_by(PartialOrd::partial_cmp)
+     }
+ 
+     /// Checks if the elements of this iterator are sorted using the given comparator function.
+     ///
+     /// Instead of using `PartialOrd::partial_cmp`, this function uses the given `compare`
+     /// function to determine the ordering of two elements. Apart from that, it's equivalent to
+     /// [`is_sorted`]; see its documentation for more information.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(is_sorted)]
+     ///
+     /// assert!([1, 2, 2, 9].iter().is_sorted_by(|a, b| a.partial_cmp(b)));
+     /// assert!(![1, 3, 2, 4].iter().is_sorted_by(|a, b| a.partial_cmp(b)));
+     /// assert!([0].iter().is_sorted_by(|a, b| a.partial_cmp(b)));
+     /// assert!(std::iter::empty::<i32>().is_sorted_by(|a, b| a.partial_cmp(b)));
+     /// assert!(![0.0, 1.0, f32::NAN].iter().is_sorted_by(|a, b| a.partial_cmp(b)));
+     /// ```
+     ///
+     /// [`is_sorted`]: Iterator::is_sorted
+     #[unstable(feature = "is_sorted", reason = "new API", issue = "53485")]
+     fn is_sorted_by<F>(mut self, mut compare: F) -> bool
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item, &Self::Item) -> Option<Ordering>,
+     {
+         let mut last = match self.next() {
+             Some(e) => e,
+             None => return true,
+         };
+ 
+         while let Some(curr) = self.next() {
+             if let Some(Ordering::Greater) | None = compare(&last, &curr) {
+                 return false;
+             }
+             last = curr;
+         }
+ 
+         true
+     }
+ 
+     /// Checks if the elements of this iterator are sorted using the given key extraction
+     /// function.
+     ///
+     /// Instead of comparing the iterator's elements directly, this function compares the keys of
+     /// the elements, as determined by `f`. Apart from that, it's equivalent to [`is_sorted`]; see
+     /// its documentation for more information.
+     ///
+     /// [`is_sorted`]: Iterator::is_sorted
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(is_sorted)]
+     ///
+     /// assert!(["c", "bb", "aaa"].iter().is_sorted_by_key(|s| s.len()));
+     /// assert!(![-2i32, -1, 0, 3].iter().is_sorted_by_key(|n| n.abs()));
+     /// ```
+     #[inline]
+     #[unstable(feature = "is_sorted", reason = "new API", issue = "53485")]
+     fn is_sorted_by_key<F, K>(self, f: F) -> bool
+     where
+         Self: Sized,
+         F: FnMut(Self::Item) -> K,
+         K: PartialOrd,
+     {
+         self.map(f).is_sorted()
+     }
+ 
+     /// See [TrustedRandomAccess]
+     // The unusual name is to avoid name collisions in method resolution
+     // see #76479.
+     #[inline]
+     #[doc(hidden)]
+     #[unstable(feature = "trusted_random_access", issue = "none")]
+     unsafe fn __iterator_get_unchecked(&mut self, _idx: usize) -> Self::Item
+     where
+         Self: TrustedRandomAccess,
+     {
+         unreachable!("Always specialized");
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I: Iterator + ?Sized> Iterator for &mut I {
+     type Item = I::Item;
+     fn next(&mut self) -> Option<I::Item> {
+         (**self).next()
+     }
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (**self).size_hint()
+     }
+     fn advance_by(&mut self, n: usize) -> Result<(), usize> {
+         (**self).advance_by(n)
+     }
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         (**self).nth(n)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/marker.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/marker.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/marker.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/marker.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,56 ----
+ /// An iterator that always continues to yield `None` when exhausted.
+ ///
+ /// Calling next on a fused iterator that has returned `None` once is guaranteed
+ /// to return [`None`] again. This trait should be implemented by all iterators
+ /// that behave this way because it allows optimizing [`Iterator::fuse()`].
+ ///
+ /// Note: In general, you should not use `FusedIterator` in generic bounds if
+ /// you need a fused iterator. Instead, you should just call [`Iterator::fuse()`]
+ /// on the iterator. If the iterator is already fused, the additional [`Fuse`]
+ /// wrapper will be a no-op with no performance penalty.
+ ///
+ /// [`Fuse`]: crate::iter::Fuse
+ #[stable(feature = "fused", since = "1.26.0")]
+ #[rustc_unsafe_specialization_marker]
+ pub trait FusedIterator: Iterator {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<I: FusedIterator + ?Sized> FusedIterator for &mut I {}
+ 
+ /// An iterator that reports an accurate length using size_hint.
+ ///
+ /// The iterator reports a size hint where it is either exact
+ /// (lower bound is equal to upper bound), or the upper bound is [`None`].
+ /// The upper bound must only be [`None`] if the actual iterator length is
+ /// larger than [`usize::MAX`]. In that case, the lower bound must be
+ /// [`usize::MAX`], resulting in a [`Iterator::size_hint()`] of
+ /// `(usize::MAX, None)`.
+ ///
+ /// The iterator must produce exactly the number of elements it reported
+ /// or diverge before reaching the end.
+ ///
+ /// # Safety
+ ///
+ /// This trait must only be implemented when the contract is upheld. Consumers
+ /// of this trait must inspect [`Iterator::size_hint()`]’s upper bound.
+ ///
+ /// [`usize::MAX`]: crate::usize::MAX
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ #[rustc_unsafe_specialization_marker]
+ pub unsafe trait TrustedLen: Iterator {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<I: TrustedLen + ?Sized> TrustedLen for &mut I {}
+ 
+ /// An iterator that when yielding an item will have taken at least one element
+ /// from its underlying [`SourceIter`].
+ ///
+ /// Calling [`next()`] guarantees that at least one value of the iterator's underlying source
+ /// has been moved out and the result of the iterator chain could be inserted in its place,
+ /// assuming structural constraints of the source allow such an insertion.
+ /// In other words this trait indicates that an iterator pipeline can be collected in place.
+ ///
+ /// [`SourceIter`]: crate::iter::SourceIter
+ /// [`next()`]: Iterator::next
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ pub unsafe trait InPlaceIterable: Iterator {}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/iter/traits/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/iter/traits/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,17 ----
+ mod accum;
+ mod collect;
+ mod double_ended;
+ mod exact_size;
+ mod iterator;
+ mod marker;
+ 
+ pub use self::accum::{Product, Sum};
+ pub use self::collect::{Extend, FromIterator, IntoIterator};
+ pub use self::double_ended::DoubleEndedIterator;
+ pub use self::exact_size::ExactSizeIterator;
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::iterator::Iterator;
+ #[unstable(issue = "none", feature = "inplace_iteration")]
+ pub use self::marker::InPlaceIterable;
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::marker::{FusedIterator, TrustedLen};
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/lazy.rs gcc-16-20251102/libgrust/rustc-lib/core/src/lazy.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/lazy.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/lazy.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,379 ----
+ //! Lazy values and one-time initialization of static data.
+ 
+ use crate::cell::{Cell, UnsafeCell};
+ use crate::fmt;
+ use crate::mem;
+ use crate::ops::Deref;
+ 
+ /// A cell which can be written to only once.
+ ///
+ /// Unlike `RefCell`, a `OnceCell` only provides shared `&T` references to its value.
+ /// Unlike `Cell`, a `OnceCell` doesn't require copying or replacing the value to access it.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(once_cell)]
+ ///
+ /// use std::lazy::OnceCell;
+ ///
+ /// let cell = OnceCell::new();
+ /// assert!(cell.get().is_none());
+ ///
+ /// let value: &String = cell.get_or_init(|| {
+ ///     "Hello, World!".to_string()
+ /// });
+ /// assert_eq!(value, "Hello, World!");
+ /// assert!(cell.get().is_some());
+ /// ```
+ #[unstable(feature = "once_cell", issue = "74465")]
+ pub struct OnceCell<T> {
+     // Invariant: written to at most once.
+     inner: UnsafeCell<Option<T>>,
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T> Default for OnceCell<T> {
+     fn default() -> Self {
+         Self::new()
+     }
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T: fmt::Debug> fmt::Debug for OnceCell<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         match self.get() {
+             Some(v) => f.debug_tuple("OnceCell").field(v).finish(),
+             None => f.write_str("OnceCell(Uninit)"),
+         }
+     }
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T: Clone> Clone for OnceCell<T> {
+     fn clone(&self) -> OnceCell<T> {
+         let res = OnceCell::new();
+         if let Some(value) = self.get() {
+             match res.set(value.clone()) {
+                 Ok(()) => (),
+                 Err(_) => unreachable!(),
+             }
+         }
+         res
+     }
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T: PartialEq> PartialEq for OnceCell<T> {
+     fn eq(&self, other: &Self) -> bool {
+         self.get() == other.get()
+     }
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T: Eq> Eq for OnceCell<T> {}
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T> From<T> for OnceCell<T> {
+     fn from(value: T) -> Self {
+         OnceCell { inner: UnsafeCell::new(Some(value)) }
+     }
+ }
+ 
+ impl<T> OnceCell<T> {
+     /// Creates a new empty cell.
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub const fn new() -> OnceCell<T> {
+         OnceCell { inner: UnsafeCell::new(None) }
+     }
+ 
+     /// Gets the reference to the underlying value.
+     ///
+     /// Returns `None` if the cell is empty.
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn get(&self) -> Option<&T> {
+         // SAFETY: Safe due to `inner`'s invariant
+         unsafe { &*self.inner.get() }.as_ref()
+     }
+ 
+     /// Gets the mutable reference to the underlying value.
+     ///
+     /// Returns `None` if the cell is empty.
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn get_mut(&mut self) -> Option<&mut T> {
+         // SAFETY: Safe because we have unique access
+         unsafe { &mut *self.inner.get() }.as_mut()
+     }
+ 
+     /// Sets the contents of the cell to `value`.
+     ///
+     /// # Errors
+     ///
+     /// This method returns `Ok(())` if the cell was empty and `Err(value)` if
+     /// it was full.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// use std::lazy::OnceCell;
+     ///
+     /// let cell = OnceCell::new();
+     /// assert!(cell.get().is_none());
+     ///
+     /// assert_eq!(cell.set(92), Ok(()));
+     /// assert_eq!(cell.set(62), Err(62));
+     ///
+     /// assert!(cell.get().is_some());
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn set(&self, value: T) -> Result<(), T> {
+         // SAFETY: Safe because we cannot have overlapping mutable borrows
+         let slot = unsafe { &*self.inner.get() };
+         if slot.is_some() {
+             return Err(value);
+         }
+ 
+         // SAFETY: This is the only place where we set the slot, no races
+         // due to reentrancy/concurrency are possible, and we've
+         // checked that slot is currently `None`, so this write
+         // maintains the `inner`'s invariant.
+         let slot = unsafe { &mut *self.inner.get() };
+         *slot = Some(value);
+         Ok(())
+     }
+ 
+     /// Gets the contents of the cell, initializing it with `f`
+     /// if the cell was empty.
+     ///
+     /// # Panics
+     ///
+     /// If `f` panics, the panic is propagated to the caller, and the cell
+     /// remains uninitialized.
+     ///
+     /// It is an error to reentrantly initialize the cell from `f`. Doing
+     /// so results in a panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// use std::lazy::OnceCell;
+     ///
+     /// let cell = OnceCell::new();
+     /// let value = cell.get_or_init(|| 92);
+     /// assert_eq!(value, &92);
+     /// let value = cell.get_or_init(|| unreachable!());
+     /// assert_eq!(value, &92);
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn get_or_init<F>(&self, f: F) -> &T
+     where
+         F: FnOnce() -> T,
+     {
+         match self.get_or_try_init(|| Ok::<T, !>(f())) {
+             Ok(val) => val,
+         }
+     }
+ 
+     /// Gets the contents of the cell, initializing it with `f` if
+     /// the cell was empty. If the cell was empty and `f` failed, an
+     /// error is returned.
+     ///
+     /// # Panics
+     ///
+     /// If `f` panics, the panic is propagated to the caller, and the cell
+     /// remains uninitialized.
+     ///
+     /// It is an error to reentrantly initialize the cell from `f`. Doing
+     /// so results in a panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// use std::lazy::OnceCell;
+     ///
+     /// let cell = OnceCell::new();
+     /// assert_eq!(cell.get_or_try_init(|| Err(())), Err(()));
+     /// assert!(cell.get().is_none());
+     /// let value = cell.get_or_try_init(|| -> Result<i32, ()> {
+     ///     Ok(92)
+     /// });
+     /// assert_eq!(value, Ok(&92));
+     /// assert_eq!(cell.get(), Some(&92))
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn get_or_try_init<F, E>(&self, f: F) -> Result<&T, E>
+     where
+         F: FnOnce() -> Result<T, E>,
+     {
+         if let Some(val) = self.get() {
+             return Ok(val);
+         }
+         let val = f()?;
+         // Note that *some* forms of reentrant initialization might lead to
+         // UB (see `reentrant_init` test). I believe that just removing this
+         // `assert`, while keeping `set/get` would be sound, but it seems
+         // better to panic, rather than to silently use an old value.
+         assert!(self.set(val).is_ok(), "reentrant init");
+         Ok(self.get().unwrap())
+     }
+ 
+     /// Consumes the cell, returning the wrapped value.
+     ///
+     /// Returns `None` if the cell was empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// use std::lazy::OnceCell;
+     ///
+     /// let cell: OnceCell<String> = OnceCell::new();
+     /// assert_eq!(cell.into_inner(), None);
+     ///
+     /// let cell = OnceCell::new();
+     /// cell.set("hello".to_string()).unwrap();
+     /// assert_eq!(cell.into_inner(), Some("hello".to_string()));
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn into_inner(self) -> Option<T> {
+         // Because `into_inner` takes `self` by value, the compiler statically verifies
+         // that it is not currently borrowed. So it is safe to move out `Option<T>`.
+         self.inner.into_inner()
+     }
+ 
+     /// Takes the value out of this `OnceCell`, moving it back to an uninitialized state.
+     ///
+     /// Has no effect and returns `None` if the `OnceCell` hasn't been initialized.
+     ///
+     /// Safety is guaranteed by requiring a mutable reference.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// use std::lazy::OnceCell;
+     ///
+     /// let mut cell: OnceCell<String> = OnceCell::new();
+     /// assert_eq!(cell.take(), None);
+     ///
+     /// let mut cell = OnceCell::new();
+     /// cell.set("hello".to_string()).unwrap();
+     /// assert_eq!(cell.take(), Some("hello".to_string()));
+     /// assert_eq!(cell.get(), None);
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn take(&mut self) -> Option<T> {
+         mem::take(self).into_inner()
+     }
+ }
+ 
+ /// A value which is initialized on the first access.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(once_cell)]
+ ///
+ /// use std::lazy::Lazy;
+ ///
+ /// let lazy: Lazy<i32> = Lazy::new(|| {
+ ///     println!("initializing");
+ ///     92
+ /// });
+ /// println!("ready");
+ /// println!("{}", *lazy);
+ /// println!("{}", *lazy);
+ ///
+ /// // Prints:
+ /// //   ready
+ /// //   initializing
+ /// //   92
+ /// //   92
+ /// ```
+ #[unstable(feature = "once_cell", issue = "74465")]
+ pub struct Lazy<T, F = fn() -> T> {
+     cell: OnceCell<T>,
+     init: Cell<Option<F>>,
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T: fmt::Debug, F> fmt::Debug for Lazy<T, F> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Lazy").field("cell", &self.cell).field("init", &"..").finish()
+     }
+ }
+ 
+ impl<T, F> Lazy<T, F> {
+     /// Creates a new lazy value with the given initializing function.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// # fn main() {
+     /// use std::lazy::Lazy;
+     ///
+     /// let hello = "Hello, World!".to_string();
+     ///
+     /// let lazy = Lazy::new(|| hello.to_uppercase());
+     ///
+     /// assert_eq!(&*lazy, "HELLO, WORLD!");
+     /// # }
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub const fn new(init: F) -> Lazy<T, F> {
+         Lazy { cell: OnceCell::new(), init: Cell::new(Some(init)) }
+     }
+ }
+ 
+ impl<T, F: FnOnce() -> T> Lazy<T, F> {
+     /// Forces the evaluation of this lazy value and returns a reference to
+     /// the result.
+     ///
+     /// This is equivalent to the `Deref` impl, but is explicit.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(once_cell)]
+     ///
+     /// use std::lazy::Lazy;
+     ///
+     /// let lazy = Lazy::new(|| 92);
+     ///
+     /// assert_eq!(Lazy::force(&lazy), &92);
+     /// assert_eq!(&*lazy, &92);
+     /// ```
+     #[unstable(feature = "once_cell", issue = "74465")]
+     pub fn force(this: &Lazy<T, F>) -> &T {
+         this.cell.get_or_init(|| match this.init.take() {
+             Some(f) => f(),
+             None => panic!("`Lazy` instance has previously been poisoned"),
+         })
+     }
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T, F: FnOnce() -> T> Deref for Lazy<T, F> {
+     type Target = T;
+     fn deref(&self) -> &T {
+         Lazy::force(self)
+     }
+ }
+ 
+ #[unstable(feature = "once_cell", issue = "74465")]
+ impl<T: Default> Default for Lazy<T> {
+     /// Creates a new lazy value using `Default` as the initializing function.
+     fn default() -> Lazy<T> {
+         Lazy::new(T::default)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/core/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,300 ----
+ //! # The Rust Core Library
+ //!
+ //! The Rust Core Library is the dependency-free[^free] foundation of [The
+ //! Rust Standard Library](../std/index.html). It is the portable glue
+ //! between the language and its libraries, defining the intrinsic and
+ //! primitive building blocks of all Rust code. It links to no
+ //! upstream libraries, no system libraries, and no libc.
+ //!
+ //! [^free]: Strictly speaking, there are some symbols which are needed but
+ //!          they aren't always necessary.
+ //!
+ //! The core library is *minimal*: it isn't even aware of heap allocation,
+ //! nor does it provide concurrency or I/O. These things require
+ //! platform integration, and this library is platform-agnostic.
+ //!
+ //! # How to use the core library
+ //!
+ //! Please note that all of these details are currently not considered stable.
+ //!
+ // FIXME: Fill me in with more detail when the interface settles
+ //! This library is built on the assumption of a few existing symbols:
+ //!
+ //! * `memcpy`, `memcmp`, `memset` - These are core memory routines which are
+ //!   often generated by LLVM. Additionally, this library can make explicit
+ //!   calls to these functions. Their signatures are the same as found in C.
+ //!   These functions are often provided by the system libc, but can also be
+ //!   provided by the [compiler-builtins crate](https://crates.io/crates/compiler_builtins).
+ //!
+ //! * `rust_begin_panic` - This function takes four arguments, a
+ //!   `fmt::Arguments`, a `&'static str`, and two `u32`'s. These four arguments
+ //!   dictate the panic message, the file at which panic was invoked, and the
+ //!   line and column inside the file. It is up to consumers of this core
+ //!   library to define this panic function; it is only required to never
+ //!   return. This requires a `lang` attribute named `panic_impl`.
+ //!
+ //! * `rust_eh_personality` - is used by the failure mechanisms of the
+ //!    compiler. This is often mapped to GCC's personality function, but crates
+ //!    which do not trigger a panic can be assured that this function is never
+ //!    called. The `lang` attribute is called `eh_personality`.
+ 
+ // Since libcore defines many fundamental lang items, all tests live in a
+ // separate crate, libcoretest, to avoid bizarre issues.
+ //
+ // Here we explicitly #[cfg]-out this whole crate when testing. If we don't do
+ // this, both the generated test artifact and the linked libtest (which
+ // transitively includes libcore) will both define the same set of lang items,
+ // and this will cause the E0152 "found duplicate lang item" error. See
+ // discussion in #50466 for details.
+ //
+ // This cfg won't affect doc tests.
+ #![cfg(not(test))]
+ #![stable(feature = "core", since = "1.6.0")]
+ #![doc(
+     html_root_url = "https://doc.rust-lang.org/nightly/",
+     html_playground_url = "https://play.rust-lang.org/",
+     issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/",
+     test(no_crate_inject, attr(deny(warnings))),
+     test(attr(allow(dead_code, deprecated, unused_variables, unused_mut)))
+ )]
+ #![no_core]
+ #![warn(deprecated_in_future)]
+ #![warn(missing_docs)]
+ #![warn(missing_debug_implementations)]
+ #![allow(explicit_outlives_requirements)]
+ #![allow(incomplete_features)]
+ #![cfg_attr(not(bootstrap), feature(rustc_allow_const_fn_unstable))]
+ #![feature(allow_internal_unstable)]
+ #![feature(arbitrary_self_types)]
+ #![feature(asm)]
+ #![feature(cfg_target_has_atomic)]
+ #![feature(const_alloc_layout)]
+ #![feature(const_discriminant)]
+ #![feature(const_cell_into_inner)]
+ #![feature(const_checked_int_methods)]
+ #![feature(const_euclidean_int_methods)]
+ #![feature(const_float_classify)]
+ #![feature(const_float_bits_conv)]
+ #![feature(const_overflowing_int_methods)]
+ #![feature(const_int_unchecked_arith)]
+ #![feature(const_mut_refs)]
+ #![feature(const_int_pow)]
+ #![feature(constctlz)]
+ #![feature(const_panic)]
+ #![feature(const_pin)]
+ #![feature(const_fn)]
+ #![feature(const_fn_union)]
+ #![cfg_attr(not(bootstrap), feature(const_impl_trait))]
+ #![feature(const_fn_floating_point_arithmetic)]
+ #![feature(const_fn_fn_ptr_basics)]
+ #![feature(const_generics)]
+ #![feature(const_option)]
+ #![feature(const_precise_live_drops)]
+ #![feature(const_ptr_offset)]
+ #![feature(const_ptr_offset_from)]
+ #![feature(const_raw_ptr_comparison)]
+ #![feature(const_slice_from_raw_parts)]
+ #![feature(const_slice_ptr_len)]
+ #![feature(const_size_of_val)]
+ #![feature(const_align_of_val)]
+ #![feature(const_type_id)]
+ #![feature(const_type_name)]
+ #![feature(const_likely)]
+ #![feature(const_unreachable_unchecked)]
+ #![feature(custom_inner_attributes)]
+ #![feature(decl_macro)]
+ #![feature(doc_cfg)]
+ #![feature(doc_spotlight)]
+ #![feature(duration_consts_2)]
+ #![feature(duration_saturating_ops)]
+ #![feature(extern_types)]
+ #![feature(fundamental)]
+ #![feature(intrinsics)]
+ #![feature(lang_items)]
+ #![feature(link_llvm_intrinsics)]
+ #![feature(llvm_asm)]
+ #![feature(negative_impls)]
+ #![feature(never_type)]
+ #![feature(nll)]
+ #![feature(exhaustive_patterns)]
+ #![feature(no_core)]
+ #![feature(optin_builtin_traits)]
+ #![feature(or_patterns)]
+ #![feature(prelude_import)]
+ #![feature(repr_simd, platform_intrinsics)]
+ #![feature(rustc_attrs)]
+ #![feature(simd_ffi)]
+ #![feature(min_specialization)]
+ #![feature(staged_api)]
+ #![feature(std_internals)]
+ #![feature(stmt_expr_attributes)]
+ #![feature(str_split_as_str)]
+ #![feature(str_split_inclusive_as_str)]
+ #![feature(transparent_unions)]
+ #![feature(try_blocks)]
+ #![feature(unboxed_closures)]
+ #![cfg_attr(not(bootstrap), feature(unsized_fn_params))]
+ #![cfg_attr(bootstrap, feature(unsized_locals))]
+ #![cfg_attr(bootstrap, feature(untagged_unions))]
+ #![feature(unwind_attributes)]
+ #![feature(variant_count)]
+ #![feature(tbm_target_feature)]
+ #![feature(sse4a_target_feature)]
+ #![feature(arm_target_feature)]
+ #![feature(powerpc_target_feature)]
+ #![feature(mips_target_feature)]
+ #![feature(aarch64_target_feature)]
+ #![feature(wasm_target_feature)]
+ #![feature(avx512_target_feature)]
+ #![feature(cmpxchg16b_target_feature)]
+ #![feature(rtm_target_feature)]
+ #![feature(f16c_target_feature)]
+ #![feature(hexagon_target_feature)]
+ #![feature(const_fn_transmute)]
+ #![feature(abi_unadjusted)]
+ #![feature(adx_target_feature)]
+ #![feature(external_doc)]
+ #![feature(associated_type_bounds)]
+ #![feature(const_caller_location)]
+ #![feature(slice_ptr_get)]
+ #![feature(no_niche)] // rust-lang/rust#68303
+ #![feature(unsafe_block_in_unsafe_fn)]
+ #![feature(int_error_matching)]
+ #![deny(unsafe_op_in_unsafe_fn)]
+ 
+ #[prelude_import]
+ #[allow(unused)]
+ use prelude::v1::*;
+ 
+ #[cfg(not(test))] // See #65860
+ #[macro_use]
+ mod macros;
+ 
+ #[macro_use]
+ mod internal_macros;
+ 
+ #[path = "num/shells/int_macros.rs"]
+ #[macro_use]
+ mod int_macros;
+ 
+ #[path = "num/shells/i128.rs"]
+ pub mod i128;
+ #[path = "num/shells/i16.rs"]
+ pub mod i16;
+ #[path = "num/shells/i32.rs"]
+ pub mod i32;
+ #[path = "num/shells/i64.rs"]
+ pub mod i64;
+ #[path = "num/shells/i8.rs"]
+ pub mod i8;
+ #[path = "num/shells/isize.rs"]
+ pub mod isize;
+ 
+ #[path = "num/shells/u128.rs"]
+ pub mod u128;
+ #[path = "num/shells/u16.rs"]
+ pub mod u16;
+ #[path = "num/shells/u32.rs"]
+ pub mod u32;
+ #[path = "num/shells/u64.rs"]
+ pub mod u64;
+ #[path = "num/shells/u8.rs"]
+ pub mod u8;
+ #[path = "num/shells/usize.rs"]
+ pub mod usize;
+ 
+ #[path = "num/f32.rs"]
+ pub mod f32;
+ #[path = "num/f64.rs"]
+ pub mod f64;
+ 
+ #[macro_use]
+ pub mod num;
+ 
+ /* The libcore prelude, not as all-encompassing as the libstd prelude */
+ 
+ pub mod prelude;
+ 
+ /* Core modules for ownership management */
+ 
+ pub mod hint;
+ pub mod intrinsics;
+ pub mod mem;
+ pub mod ptr;
+ 
+ /* Core language traits */
+ 
+ pub mod borrow;
+ pub mod clone;
+ pub mod cmp;
+ pub mod convert;
+ pub mod default;
+ pub mod marker;
+ pub mod ops;
+ 
+ /* Core types and methods on primitives */
+ 
+ pub mod any;
+ pub mod array;
+ pub mod ascii;
+ pub mod cell;
+ pub mod char;
+ pub mod ffi;
+ pub mod iter;
+ #[unstable(feature = "once_cell", issue = "74465")]
+ pub mod lazy;
+ pub mod option;
+ pub mod panic;
+ pub mod panicking;
+ pub mod pin;
+ pub mod raw;
+ pub mod result;
+ pub mod sync;
+ 
+ pub mod fmt;
+ pub mod hash;
+ pub mod slice;
+ pub mod str;
+ pub mod time;
+ 
+ pub mod unicode;
+ 
+ /* Async */
+ pub mod future;
+ pub mod task;
+ 
+ /* Heap memory allocator trait */
+ #[allow(missing_docs)]
+ pub mod alloc;
+ 
+ // note: does not need to be public
+ mod bool;
+ mod tuple;
+ mod unit;
+ 
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub mod primitive;
+ 
+ // Pull in the `core_arch` crate directly into libcore. The contents of
+ // `core_arch` are in a different repository: rust-lang/stdarch.
+ //
+ // `core_arch` depends on libcore, but the contents of this module are
+ // set up in such a way that directly pulling it here works such that the
+ // crate uses the this crate as its libcore.
+ #[path = "../../stdarch/crates/core_arch/src/mod.rs"]
+ #[allow(
+     missing_docs,
+     missing_debug_implementations,
+     dead_code,
+     unused_imports,
+     unsafe_op_in_unsafe_fn
+ )]
+ #[cfg_attr(not(bootstrap), allow(non_autolinks))]
+ // FIXME: This annotation should be moved into rust-lang/stdarch after clashing_extern_declarations is
+ // merged. It currently cannot because bootstrap fails as the lint hasn't been defined yet.
+ #[allow(clashing_extern_declarations)]
+ #[unstable(feature = "stdsimd", issue = "48556")]
+ mod core_arch;
+ 
+ #[stable(feature = "simd_arch", since = "1.27.0")]
+ pub use core_arch::arch;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/macros/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/macros/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/macros/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/macros/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1376 ----
+ #[doc(include = "panic.md")]
+ #[macro_export]
+ #[allow_internal_unstable(core_panic, const_caller_location)]
+ #[stable(feature = "core", since = "1.6.0")]
+ macro_rules! panic {
+     () => (
+         $crate::panic!("explicit panic")
+     );
+     ($msg:literal $(,)?) => (
+         $crate::panicking::panic($msg)
+     );
+     ($msg:expr $(,)?) => (
+         $crate::panicking::panic_str($msg)
+     );
+     ($fmt:expr, $($arg:tt)+) => (
+         $crate::panicking::panic_fmt($crate::format_args!($fmt, $($arg)+))
+     );
+ }
+ 
+ /// Asserts that two expressions are equal to each other (using [`PartialEq`]).
+ ///
+ /// On panic, this macro will print the values of the expressions with their
+ /// debug representations.
+ ///
+ /// Like [`assert!`], this macro has a second form, where a custom
+ /// panic message can be provided.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let a = 3;
+ /// let b = 1 + 2;
+ /// assert_eq!(a, b);
+ ///
+ /// assert_eq!(a, b, "we are testing addition with {} and {}", a, b);
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ macro_rules! assert_eq {
+     ($left:expr, $right:expr $(,)?) => ({
+         match (&$left, &$right) {
+             (left_val, right_val) => {
+                 if !(*left_val == *right_val) {
+                     // The reborrows below are intentional. Without them, the stack slot for the
+                     // borrow is initialized even before the values are compared, leading to a
+                     // noticeable slow down.
+                     panic!(r#"assertion failed: `(left == right)`
+   left: `{:?}`,
+  right: `{:?}`"#, &*left_val, &*right_val)
+                 }
+             }
+         }
+     });
+     ($left:expr, $right:expr, $($arg:tt)+) => ({
+         match (&($left), &($right)) {
+             (left_val, right_val) => {
+                 if !(*left_val == *right_val) {
+                     // The reborrows below are intentional. Without them, the stack slot for the
+                     // borrow is initialized even before the values are compared, leading to a
+                     // noticeable slow down.
+                     panic!(r#"assertion failed: `(left == right)`
+   left: `{:?}`,
+  right: `{:?}`: {}"#, &*left_val, &*right_val,
+                            $crate::format_args!($($arg)+))
+                 }
+             }
+         }
+     });
+ }
+ 
+ /// Asserts that two expressions are not equal to each other (using [`PartialEq`]).
+ ///
+ /// On panic, this macro will print the values of the expressions with their
+ /// debug representations.
+ ///
+ /// Like [`assert!`], this macro has a second form, where a custom
+ /// panic message can be provided.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let a = 3;
+ /// let b = 2;
+ /// assert_ne!(a, b);
+ ///
+ /// assert_ne!(a, b, "we are testing that the values are not equal");
+ /// ```
+ #[macro_export]
+ #[stable(feature = "assert_ne", since = "1.13.0")]
+ macro_rules! assert_ne {
+     ($left:expr, $right:expr $(,)?) => ({
+         match (&$left, &$right) {
+             (left_val, right_val) => {
+                 if *left_val == *right_val {
+                     // The reborrows below are intentional. Without them, the stack slot for the
+                     // borrow is initialized even before the values are compared, leading to a
+                     // noticeable slow down.
+                     panic!(r#"assertion failed: `(left != right)`
+   left: `{:?}`,
+  right: `{:?}`"#, &*left_val, &*right_val)
+                 }
+             }
+         }
+     });
+     ($left:expr, $right:expr, $($arg:tt)+) => ({
+         match (&($left), &($right)) {
+             (left_val, right_val) => {
+                 if *left_val == *right_val {
+                     // The reborrows below are intentional. Without them, the stack slot for the
+                     // borrow is initialized even before the values are compared, leading to a
+                     // noticeable slow down.
+                     panic!(r#"assertion failed: `(left != right)`
+   left: `{:?}`,
+  right: `{:?}`: {}"#, &*left_val, &*right_val,
+                            $crate::format_args!($($arg)+))
+                 }
+             }
+         }
+     });
+ }
+ 
+ /// Asserts that a boolean expression is `true` at runtime.
+ ///
+ /// This will invoke the [`panic!`] macro if the provided expression cannot be
+ /// evaluated to `true` at runtime.
+ ///
+ /// Like [`assert!`], this macro also has a second version, where a custom panic
+ /// message can be provided.
+ ///
+ /// # Uses
+ ///
+ /// Unlike [`assert!`], `debug_assert!` statements are only enabled in non
+ /// optimized builds by default. An optimized build will not execute
+ /// `debug_assert!` statements unless `-C debug-assertions` is passed to the
+ /// compiler. This makes `debug_assert!` useful for checks that are too
+ /// expensive to be present in a release build but may be helpful during
+ /// development. The result of expanding `debug_assert!` is always type checked.
+ ///
+ /// An unchecked assertion allows a program in an inconsistent state to keep
+ /// running, which might have unexpected consequences but does not introduce
+ /// unsafety as long as this only happens in safe code. The performance cost
+ /// of assertions, however, is not measurable in general. Replacing [`assert!`]
+ /// with `debug_assert!` is thus only encouraged after thorough profiling, and
+ /// more importantly, only in safe code!
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// // the panic message for these assertions is the stringified value of the
+ /// // expression given.
+ /// debug_assert!(true);
+ ///
+ /// fn some_expensive_computation() -> bool { true } // a very simple function
+ /// debug_assert!(some_expensive_computation());
+ ///
+ /// // assert with a custom message
+ /// let x = true;
+ /// debug_assert!(x, "x wasn't true!");
+ ///
+ /// let a = 3; let b = 27;
+ /// debug_assert!(a + b == 30, "a = {}, b = {}", a, b);
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ macro_rules! debug_assert {
+     ($($arg:tt)*) => (if $crate::cfg!(debug_assertions) { $crate::assert!($($arg)*); })
+ }
+ 
+ /// Asserts that two expressions are equal to each other.
+ ///
+ /// On panic, this macro will print the values of the expressions with their
+ /// debug representations.
+ ///
+ /// Unlike [`assert_eq!`], `debug_assert_eq!` statements are only enabled in non
+ /// optimized builds by default. An optimized build will not execute
+ /// `debug_assert_eq!` statements unless `-C debug-assertions` is passed to the
+ /// compiler. This makes `debug_assert_eq!` useful for checks that are too
+ /// expensive to be present in a release build but may be helpful during
+ /// development. The result of expanding `debug_assert_eq!` is always type checked.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let a = 3;
+ /// let b = 1 + 2;
+ /// debug_assert_eq!(a, b);
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ macro_rules! debug_assert_eq {
+     ($($arg:tt)*) => (if $crate::cfg!(debug_assertions) { $crate::assert_eq!($($arg)*); })
+ }
+ 
+ /// Asserts that two expressions are not equal to each other.
+ ///
+ /// On panic, this macro will print the values of the expressions with their
+ /// debug representations.
+ ///
+ /// Unlike [`assert_ne!`], `debug_assert_ne!` statements are only enabled in non
+ /// optimized builds by default. An optimized build will not execute
+ /// `debug_assert_ne!` statements unless `-C debug-assertions` is passed to the
+ /// compiler. This makes `debug_assert_ne!` useful for checks that are too
+ /// expensive to be present in a release build but may be helpful during
+ /// development. The result of expanding `debug_assert_ne!` is always type checked.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let a = 3;
+ /// let b = 2;
+ /// debug_assert_ne!(a, b);
+ /// ```
+ #[macro_export]
+ #[stable(feature = "assert_ne", since = "1.13.0")]
+ macro_rules! debug_assert_ne {
+     ($($arg:tt)*) => (if $crate::cfg!(debug_assertions) { $crate::assert_ne!($($arg)*); })
+ }
+ 
+ /// Returns whether the given expression matches any of the given patterns.
+ ///
+ /// Like in a `match` expression, the pattern can be optionally followed by `if`
+ /// and a guard expression that has access to names bound by the pattern.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let foo = 'f';
+ /// assert!(matches!(foo, 'A'..='Z' | 'a'..='z'));
+ ///
+ /// let bar = Some(4);
+ /// assert!(matches!(bar, Some(x) if x > 2));
+ /// ```
+ #[macro_export]
+ #[stable(feature = "matches_macro", since = "1.42.0")]
+ macro_rules! matches {
+     ($expression:expr, $( $pattern:pat )|+ $( if $guard: expr )? $(,)?) => {
+         match $expression {
+             $( $pattern )|+ $( if $guard )? => true,
+             _ => false
+         }
+     }
+ }
+ 
+ /// Unwraps a result or propagates its error.
+ ///
+ /// The `?` operator was added to replace `try!` and should be used instead.
+ /// Furthermore, `try` is a reserved word in Rust 2018, so if you must use
+ /// it, you will need to use the [raw-identifier syntax][ris]: `r#try`.
+ ///
+ /// [ris]: https://doc.rust-lang.org/nightly/rust-by-example/compatibility/raw_identifiers.html
+ ///
+ /// `try!` matches the given [`Result`]. In case of the `Ok` variant, the
+ /// expression has the value of the wrapped value.
+ ///
+ /// In case of the `Err` variant, it retrieves the inner error. `try!` then
+ /// performs conversion using `From`. This provides automatic conversion
+ /// between specialized errors and more general ones. The resulting
+ /// error is then immediately returned.
+ ///
+ /// Because of the early return, `try!` can only be used in functions that
+ /// return [`Result`].
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::io;
+ /// use std::fs::File;
+ /// use std::io::prelude::*;
+ ///
+ /// enum MyError {
+ ///     FileWriteError
+ /// }
+ ///
+ /// impl From<io::Error> for MyError {
+ ///     fn from(e: io::Error) -> MyError {
+ ///         MyError::FileWriteError
+ ///     }
+ /// }
+ ///
+ /// // The preferred method of quick returning Errors
+ /// fn write_to_file_question() -> Result<(), MyError> {
+ ///     let mut file = File::create("my_best_friends.txt")?;
+ ///     file.write_all(b"This is a list of my best friends.")?;
+ ///     Ok(())
+ /// }
+ ///
+ /// // The previous method of quick returning Errors
+ /// fn write_to_file_using_try() -> Result<(), MyError> {
+ ///     let mut file = r#try!(File::create("my_best_friends.txt"));
+ ///     r#try!(file.write_all(b"This is a list of my best friends."));
+ ///     Ok(())
+ /// }
+ ///
+ /// // This is equivalent to:
+ /// fn write_to_file_using_match() -> Result<(), MyError> {
+ ///     let mut file = r#try!(File::create("my_best_friends.txt"));
+ ///     match file.write_all(b"This is a list of my best friends.") {
+ ///         Ok(v) => v,
+ ///         Err(e) => return Err(From::from(e)),
+ ///     }
+ ///     Ok(())
+ /// }
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_deprecated(since = "1.39.0", reason = "use the `?` operator instead")]
+ #[doc(alias = "?")]
+ macro_rules! r#try {
+     ($expr:expr $(,)?) => {
+         match $expr {
+             $crate::result::Result::Ok(val) => val,
+             $crate::result::Result::Err(err) => {
+                 return $crate::result::Result::Err($crate::convert::From::from(err));
+             }
+         }
+     };
+ }
+ 
+ /// Writes formatted data into a buffer.
+ ///
+ /// This macro accepts a 'writer', a format string, and a list of arguments. Arguments will be
+ /// formatted according to the specified format string and the result will be passed to the writer.
+ /// The writer may be any value with a `write_fmt` method; generally this comes from an
+ /// implementation of either the [`fmt::Write`] or the [`io::Write`] trait. The macro
+ /// returns whatever the `write_fmt` method returns; commonly a [`fmt::Result`], or an
+ /// [`io::Result`].
+ ///
+ /// See [`std::fmt`] for more information on the format string syntax.
+ ///
+ /// [`std::fmt`]: ../std/fmt/index.html
+ /// [`fmt::Write`]: crate::fmt::Write
+ /// [`io::Write`]: ../std/io/trait.Write.html
+ /// [`fmt::Result`]: crate::fmt::Result
+ /// [`io::Result`]: ../std/io/type.Result.html
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::io::Write;
+ ///
+ /// fn main() -> std::io::Result<()> {
+ ///     let mut w = Vec::new();
+ ///     write!(&mut w, "test")?;
+ ///     write!(&mut w, "formatted {}", "arguments")?;
+ ///
+ ///     assert_eq!(w, b"testformatted arguments");
+ ///     Ok(())
+ /// }
+ /// ```
+ ///
+ /// A module can import both `std::fmt::Write` and `std::io::Write` and call `write!` on objects
+ /// implementing either, as objects do not typically implement both. However, the module must
+ /// import the traits qualified so their names do not conflict:
+ ///
+ /// ```
+ /// use std::fmt::Write as FmtWrite;
+ /// use std::io::Write as IoWrite;
+ ///
+ /// fn main() -> Result<(), Box<dyn std::error::Error>> {
+ ///     let mut s = String::new();
+ ///     let mut v = Vec::new();
+ ///
+ ///     write!(&mut s, "{} {}", "abc", 123)?; // uses fmt::Write::write_fmt
+ ///     write!(&mut v, "s = {:?}", s)?; // uses io::Write::write_fmt
+ ///     assert_eq!(v, b"s = \"abc 123\"");
+ ///     Ok(())
+ /// }
+ /// ```
+ ///
+ /// Note: This macro can be used in `no_std` setups as well.
+ /// In a `no_std` setup you are responsible for the implementation details of the components.
+ ///
+ /// ```no_run
+ /// # extern crate core;
+ /// use core::fmt::Write;
+ ///
+ /// struct Example;
+ ///
+ /// impl Write for Example {
+ ///     fn write_str(&mut self, _s: &str) -> core::fmt::Result {
+ ///          unimplemented!();
+ ///     }
+ /// }
+ ///
+ /// let mut m = Example{};
+ /// write!(&mut m, "Hello World").expect("Not written");
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ macro_rules! write {
+     ($dst:expr, $($arg:tt)*) => ($dst.write_fmt($crate::format_args!($($arg)*)))
+ }
+ 
+ /// Write formatted data into a buffer, with a newline appended.
+ ///
+ /// On all platforms, the newline is the LINE FEED character (`\n`/`U+000A`) alone
+ /// (no additional CARRIAGE RETURN (`\r`/`U+000D`).
+ ///
+ /// For more information, see [`write!`]. For information on the format string syntax, see
+ /// [`std::fmt`].
+ ///
+ /// [`std::fmt`]: crate::fmt
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::io::{Write, Result};
+ ///
+ /// fn main() -> Result<()> {
+ ///     let mut w = Vec::new();
+ ///     writeln!(&mut w)?;
+ ///     writeln!(&mut w, "test")?;
+ ///     writeln!(&mut w, "formatted {}", "arguments")?;
+ ///
+ ///     assert_eq!(&w[..], "\ntest\nformatted arguments\n".as_bytes());
+ ///     Ok(())
+ /// }
+ /// ```
+ ///
+ /// A module can import both `std::fmt::Write` and `std::io::Write` and call `write!` on objects
+ /// implementing either, as objects do not typically implement both. However, the module must
+ /// import the traits qualified so their names do not conflict:
+ ///
+ /// ```
+ /// use std::fmt::Write as FmtWrite;
+ /// use std::io::Write as IoWrite;
+ ///
+ /// fn main() -> Result<(), Box<dyn std::error::Error>> {
+ ///     let mut s = String::new();
+ ///     let mut v = Vec::new();
+ ///
+ ///     writeln!(&mut s, "{} {}", "abc", 123)?; // uses fmt::Write::write_fmt
+ ///     writeln!(&mut v, "s = {:?}", s)?; // uses io::Write::write_fmt
+ ///     assert_eq!(v, b"s = \"abc 123\\n\"\n");
+ ///     Ok(())
+ /// }
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow_internal_unstable(format_args_nl)]
+ macro_rules! writeln {
+     ($dst:expr $(,)?) => (
+         $crate::write!($dst, "\n")
+     );
+     ($dst:expr, $($arg:tt)*) => (
+         $dst.write_fmt($crate::format_args_nl!($($arg)*))
+     );
+ }
+ 
+ /// Indicates unreachable code.
+ ///
+ /// This is useful any time that the compiler can't determine that some code is unreachable. For
+ /// example:
+ ///
+ /// * Match arms with guard conditions.
+ /// * Loops that dynamically terminate.
+ /// * Iterators that dynamically terminate.
+ ///
+ /// If the determination that the code is unreachable proves incorrect, the
+ /// program immediately terminates with a [`panic!`].
+ ///
+ /// The unsafe counterpart of this macro is the [`unreachable_unchecked`] function, which
+ /// will cause undefined behavior if the code is reached.
+ ///
+ /// [`unreachable_unchecked`]: crate::hint::unreachable_unchecked
+ ///
+ /// # Panics
+ ///
+ /// This will always [`panic!`]
+ ///
+ /// # Examples
+ ///
+ /// Match arms:
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// fn foo(x: Option<i32>) {
+ ///     match x {
+ ///         Some(n) if n >= 0 => println!("Some(Non-negative)"),
+ ///         Some(n) if n <  0 => println!("Some(Negative)"),
+ ///         Some(_)           => unreachable!(), // compile error if commented out
+ ///         None              => println!("None")
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// Iterators:
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// fn divide_by_three(x: u32) -> u32 { // one of the poorest implementations of x/3
+ ///     for i in 0.. {
+ ///         if 3*i < i { panic!("u32 overflow"); }
+ ///         if x < 3*i { return i-1; }
+ ///     }
+ ///     unreachable!();
+ /// }
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ macro_rules! unreachable {
+     () => ({
+         panic!("internal error: entered unreachable code")
+     });
+     ($msg:expr $(,)?) => ({
+         $crate::unreachable!("{}", $msg)
+     });
+     ($fmt:expr, $($arg:tt)*) => ({
+         panic!($crate::concat!("internal error: entered unreachable code: ", $fmt), $($arg)*)
+     });
+ }
+ 
+ /// Indicates unimplemented code by panicking with a message of "not implemented".
+ ///
+ /// This allows your code to type-check, which is useful if you are prototyping or
+ /// implementing a trait that requires multiple methods which you don't plan of using all of.
+ ///
+ /// The difference between `unimplemented!` and [`todo!`](macro.todo.html) is that while `todo!`
+ /// conveys an intent of implementing the functionality later and the message is "not yet
+ /// implemented", `unimplemented!` makes no such claims. Its message is "not implemented".
+ /// Also some IDEs will mark `todo!`s.
+ ///
+ /// # Panics
+ ///
+ /// This will always [panic!](macro.panic.html) because `unimplemented!` is just a
+ /// shorthand for `panic!` with a fixed, specific message.
+ ///
+ /// Like `panic!`, this macro has a second form for displaying custom values.
+ ///
+ /// # Examples
+ ///
+ /// Say we have a trait `Foo`:
+ ///
+ /// ```
+ /// trait Foo {
+ ///     fn bar(&self) -> u8;
+ ///     fn baz(&self);
+ ///     fn qux(&self) -> Result<u64, ()>;
+ /// }
+ /// ```
+ ///
+ /// We want to implement `Foo` for 'MyStruct', but for some reason it only makes sense
+ /// to implement the `bar()` function. `baz()` and `qux()` will still need to be defined
+ /// in our implementation of `Foo`, but we can use `unimplemented!` in their definitions
+ /// to allow our code to compile.
+ ///
+ /// We still want to have our program stop running if the unimplemented methods are
+ /// reached.
+ ///
+ /// ```
+ /// # trait Foo {
+ /// #     fn bar(&self) -> u8;
+ /// #     fn baz(&self);
+ /// #     fn qux(&self) -> Result<u64, ()>;
+ /// # }
+ /// struct MyStruct;
+ ///
+ /// impl Foo for MyStruct {
+ ///     fn bar(&self) -> u8 {
+ ///         1 + 1
+ ///     }
+ ///
+ ///     fn baz(&self) {
+ ///         // It makes no sense to `baz` a `MyStruct`, so we have no logic here
+ ///         // at all.
+ ///         // This will display "thread 'main' panicked at 'not implemented'".
+ ///         unimplemented!();
+ ///     }
+ ///
+ ///     fn qux(&self) -> Result<u64, ()> {
+ ///         // We have some logic here,
+ ///         // We can add a message to unimplemented! to display our omission.
+ ///         // This will display:
+ ///         // "thread 'main' panicked at 'not implemented: MyStruct isn't quxable'".
+ ///         unimplemented!("MyStruct isn't quxable");
+ ///     }
+ /// }
+ ///
+ /// fn main() {
+ ///     let s = MyStruct;
+ ///     s.bar();
+ /// }
+ /// ```
+ #[macro_export]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ macro_rules! unimplemented {
+     () => (panic!("not implemented"));
+     ($($arg:tt)+) => (panic!("not implemented: {}", $crate::format_args!($($arg)+)));
+ }
+ 
+ /// Indicates unfinished code.
+ ///
+ /// This can be useful if you are prototyping and are just looking to have your
+ /// code typecheck.
+ ///
+ /// The difference between [`unimplemented!`] and `todo!` is that while `todo!` conveys
+ /// an intent of implementing the functionality later and the message is "not yet
+ /// implemented", `unimplemented!` makes no such claims. Its message is "not implemented".
+ /// Also some IDEs will mark `todo!`s.
+ ///
+ /// # Panics
+ ///
+ /// This will always [panic!](macro.panic.html)
+ ///
+ /// # Examples
+ ///
+ /// Here's an example of some in-progress code. We have a trait `Foo`:
+ ///
+ /// ```
+ /// trait Foo {
+ ///     fn bar(&self);
+ ///     fn baz(&self);
+ /// }
+ /// ```
+ ///
+ /// We want to implement `Foo` on one of our types, but we also want to work on
+ /// just `bar()` first. In order for our code to compile, we need to implement
+ /// `baz()`, so we can use `todo!`:
+ ///
+ /// ```
+ /// # trait Foo {
+ /// #     fn bar(&self);
+ /// #     fn baz(&self);
+ /// # }
+ /// struct MyStruct;
+ ///
+ /// impl Foo for MyStruct {
+ ///     fn bar(&self) {
+ ///         // implementation goes here
+ ///     }
+ ///
+ ///     fn baz(&self) {
+ ///         // let's not worry about implementing baz() for now
+ ///         todo!();
+ ///     }
+ /// }
+ ///
+ /// fn main() {
+ ///     let s = MyStruct;
+ ///     s.bar();
+ ///
+ ///     // we aren't even using baz(), so this is fine.
+ /// }
+ /// ```
+ #[macro_export]
+ #[stable(feature = "todo_macro", since = "1.40.0")]
+ macro_rules! todo {
+     () => (panic!("not yet implemented"));
+     ($($arg:tt)+) => (panic!("not yet implemented: {}", $crate::format_args!($($arg)+)));
+ }
+ 
+ /// Definitions of built-in macros.
+ ///
+ /// Most of the macro properties (stability, visibility, etc.) are taken from the source code here,
+ /// with exception of expansion functions transforming macro inputs into outputs,
+ /// those functions are provided by the compiler.
+ pub(crate) mod builtin {
+ 
+     /// Causes compilation to fail with the given error message when encountered.
+     ///
+     /// This macro should be used when a crate uses a conditional compilation strategy to provide
+     /// better error messages for erroneous conditions. It's the compiler-level form of [`panic!`],
+     /// but emits an error during *compilation* rather than at *runtime*.
+     ///
+     /// # Examples
+     ///
+     /// Two such examples are macros and `#[cfg]` environments.
+     ///
+     /// Emit better compiler error if a macro is passed invalid values. Without the final branch,
+     /// the compiler would still emit an error, but the error's message would not mention the two
+     /// valid values.
+     ///
+     /// ```compile_fail
+     /// macro_rules! give_me_foo_or_bar {
+     ///     (foo) => {};
+     ///     (bar) => {};
+     ///     ($x:ident) => {
+     ///         compile_error!("This macro only accepts `foo` or `bar`");
+     ///     }
+     /// }
+     ///
+     /// give_me_foo_or_bar!(neither);
+     /// // ^ will fail at compile time with message "This macro only accepts `foo` or `bar`"
+     /// ```
+     ///
+     /// Emit compiler error if one of a number of features isn't available.
+     ///
+     /// ```compile_fail
+     /// #[cfg(not(any(feature = "foo", feature = "bar")))]
+     /// compile_error!("Either feature \"foo\" or \"bar\" must be enabled for this crate.");
+     /// ```
+     #[stable(feature = "compile_error_macro", since = "1.20.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! compile_error {
+         ($msg:expr $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Constructs parameters for the other string-formatting macros.
+     ///
+     /// This macro functions by taking a formatting string literal containing
+     /// `{}` for each additional argument passed. `format_args!` prepares the
+     /// additional parameters to ensure the output can be interpreted as a string
+     /// and canonicalizes the arguments into a single type. Any value that implements
+     /// the [`Display`] trait can be passed to `format_args!`, as can any
+     /// [`Debug`] implementation be passed to a `{:?}` within the formatting string.
+     ///
+     /// This macro produces a value of type [`fmt::Arguments`]. This value can be
+     /// passed to the macros within [`std::fmt`] for performing useful redirection.
+     /// All other formatting macros ([`format!`], [`write!`], [`println!`], etc) are
+     /// proxied through this one. `format_args!`, unlike its derived macros, avoids
+     /// heap allocations.
+     ///
+     /// You can use the [`fmt::Arguments`] value that `format_args!` returns
+     /// in `Debug` and `Display` contexts as seen below. The example also shows
+     /// that `Debug` and `Display` format to the same thing: the interpolated
+     /// format string in `format_args!`.
+     ///
+     /// ```rust
+     /// let debug = format!("{:?}", format_args!("{} foo {:?}", 1, 2));
+     /// let display = format!("{}", format_args!("{} foo {:?}", 1, 2));
+     /// assert_eq!("1 foo 2", display);
+     /// assert_eq!(display, debug);
+     /// ```
+     ///
+     /// For more information, see the documentation in [`std::fmt`].
+     ///
+     /// [`Display`]: crate::fmt::Display
+     /// [`Debug`]: crate::fmt::Debug
+     /// [`fmt::Arguments`]: crate::fmt::Arguments
+     /// [`std::fmt`]: crate::fmt
+     /// [`format!`]: ../std/macro.format.html
+     /// [`println!`]: ../std/macro.println.html
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::fmt;
+     ///
+     /// let s = fmt::format(format_args!("hello {}", "world"));
+     /// assert_eq!(s, format!("hello {}", "world"));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[allow_internal_unstable(fmt_internals)]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! format_args {
+         ($fmt:expr) => {{ /* compiler built-in */ }};
+         ($fmt:expr, $($args:tt)*) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Same as `format_args`, but adds a newline in the end.
+     #[unstable(
+         feature = "format_args_nl",
+         issue = "none",
+         reason = "`format_args_nl` is only for internal \
+                   language use and is subject to change"
+     )]
+     #[allow_internal_unstable(fmt_internals)]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! format_args_nl {
+         ($fmt:expr) => {{ /* compiler built-in */ }};
+         ($fmt:expr, $($args:tt)*) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Inspects an environment variable at compile time.
+     ///
+     /// This macro will expand to the value of the named environment variable at
+     /// compile time, yielding an expression of type `&'static str`.
+     ///
+     /// If the environment variable is not defined, then a compilation error
+     /// will be emitted. To not emit a compile error, use the [`option_env!`]
+     /// macro instead.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let path: &'static str = env!("PATH");
+     /// println!("the $PATH variable at the time of compiling was: {}", path);
+     /// ```
+     ///
+     /// You can customize the error message by passing a string as the second
+     /// parameter:
+     ///
+     /// ```compile_fail
+     /// let doc: &'static str = env!("documentation", "what's that?!");
+     /// ```
+     ///
+     /// If the `documentation` environment variable is not defined, you'll get
+     /// the following error:
+     ///
+     /// ```text
+     /// error: what's that?!
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! env {
+         ($name:expr $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Optionally inspects an environment variable at compile time.
+     ///
+     /// If the named environment variable is present at compile time, this will
+     /// expand into an expression of type `Option<&'static str>` whose value is
+     /// `Some` of the value of the environment variable. If the environment
+     /// variable is not present, then this will expand to `None`. See
+     /// [`Option<T>`][Option] for more information on this type.
+     ///
+     /// A compile time error is never emitted when using this macro regardless
+     /// of whether the environment variable is present or not.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let key: Option<&'static str> = option_env!("SECRET_KEY");
+     /// println!("the secret key might be: {:?}", key);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! option_env {
+         ($name:expr $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Concatenates identifiers into one identifier.
+     ///
+     /// This macro takes any number of comma-separated identifiers, and
+     /// concatenates them all into one, yielding an expression which is a new
+     /// identifier. Note that hygiene makes it such that this macro cannot
+     /// capture local variables. Also, as a general rule, macros are only
+     /// allowed in item, statement or expression position. That means while
+     /// you may use this macro for referring to existing variables, functions or
+     /// modules etc, you cannot define a new one with it.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(concat_idents)]
+     ///
+     /// # fn main() {
+     /// fn foobar() -> u32 { 23 }
+     ///
+     /// let f = concat_idents!(foo, bar);
+     /// println!("{}", f());
+     ///
+     /// // fn concat_idents!(new, fun, name) { } // not usable in this way!
+     /// # }
+     /// ```
+     #[unstable(
+         feature = "concat_idents",
+         issue = "29599",
+         reason = "`concat_idents` is not stable enough for use and is subject to change"
+     )]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! concat_idents {
+         ($($e:ident),+ $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Concatenates literals into a static string slice.
+     ///
+     /// This macro takes any number of comma-separated literals, yielding an
+     /// expression of type `&'static str` which represents all of the literals
+     /// concatenated left-to-right.
+     ///
+     /// Integer and floating point literals are stringified in order to be
+     /// concatenated.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let s = concat!("test", 10, 'b', true);
+     /// assert_eq!(s, "test10btrue");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! concat {
+         ($($e:expr),* $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Expands to the line number on which it was invoked.
+     ///
+     /// With [`column!`] and [`file!`], these macros provide debugging information for
+     /// developers about the location within the source.
+     ///
+     /// The expanded expression has type `u32` and is 1-based, so the first line
+     /// in each file evaluates to 1, the second to 2, etc. This is consistent
+     /// with error messages by common compilers or popular editors.
+     /// The returned line is *not necessarily* the line of the `line!` invocation itself,
+     /// but rather the first macro invocation leading up to the invocation
+     /// of the `line!` macro.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let current_line = line!();
+     /// println!("defined on line: {}", current_line);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! line {
+         () => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Expands to the column number at which it was invoked.
+     ///
+     /// With [`line!`] and [`file!`], these macros provide debugging information for
+     /// developers about the location within the source.
+     ///
+     /// The expanded expression has type `u32` and is 1-based, so the first column
+     /// in each line evaluates to 1, the second to 2, etc. This is consistent
+     /// with error messages by common compilers or popular editors.
+     /// The returned column is *not necessarily* the line of the `column!` invocation itself,
+     /// but rather the first macro invocation leading up to the invocation
+     /// of the `column!` macro.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let current_col = column!();
+     /// println!("defined on column: {}", current_col);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! column {
+         () => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Expands to the file name in which it was invoked.
+     ///
+     /// With [`line!`] and [`column!`], these macros provide debugging information for
+     /// developers about the location within the source.
+     ///
+     /// The expanded expression has type `&'static str`, and the returned file
+     /// is not the invocation of the `file!` macro itself, but rather the
+     /// first macro invocation leading up to the invocation of the `file!`
+     /// macro.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let this_file = file!();
+     /// println!("defined in file: {}", this_file);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! file {
+         () => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Stringifies its arguments.
+     ///
+     /// This macro will yield an expression of type `&'static str` which is the
+     /// stringification of all the tokens passed to the macro. No restrictions
+     /// are placed on the syntax of the macro invocation itself.
+     ///
+     /// Note that the expanded results of the input tokens may change in the
+     /// future. You should be careful if you rely on the output.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let one_plus_one = stringify!(1 + 1);
+     /// assert_eq!(one_plus_one, "1 + 1");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! stringify {
+         ($($t:tt)*) => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Includes a UTF-8 encoded file as a string.
+     ///
+     /// The file is located relative to the current file (similarly to how
+     /// modules are found). The provided path is interpreted in a platform-specific
+     /// way at compile time. So, for instance, an invocation with a Windows path
+     /// containing backslashes `\` would not compile correctly on Unix.
+     ///
+     /// This macro will yield an expression of type `&'static str` which is the
+     /// contents of the file.
+     ///
+     /// # Examples
+     ///
+     /// Assume there are two files in the same directory with the following
+     /// contents:
+     ///
+     /// File 'spanish.in':
+     ///
+     /// ```text
+     /// adiós
+     /// ```
+     ///
+     /// File 'main.rs':
+     ///
+     /// ```ignore (cannot-doctest-external-file-dependency)
+     /// fn main() {
+     ///     let my_str = include_str!("spanish.in");
+     ///     assert_eq!(my_str, "adiós\n");
+     ///     print!("{}", my_str);
+     /// }
+     /// ```
+     ///
+     /// Compiling 'main.rs' and running the resulting binary will print "adiós".
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! include_str {
+         ($file:expr $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Includes a file as a reference to a byte array.
+     ///
+     /// The file is located relative to the current file (similarly to how
+     /// modules are found). The provided path is interpreted in a platform-specific
+     /// way at compile time. So, for instance, an invocation with a Windows path
+     /// containing backslashes `\` would not compile correctly on Unix.
+     ///
+     /// This macro will yield an expression of type `&'static [u8; N]` which is
+     /// the contents of the file.
+     ///
+     /// # Examples
+     ///
+     /// Assume there are two files in the same directory with the following
+     /// contents:
+     ///
+     /// File 'spanish.in':
+     ///
+     /// ```text
+     /// adiós
+     /// ```
+     ///
+     /// File 'main.rs':
+     ///
+     /// ```ignore (cannot-doctest-external-file-dependency)
+     /// fn main() {
+     ///     let bytes = include_bytes!("spanish.in");
+     ///     assert_eq!(bytes, b"adi\xc3\xb3s\n");
+     ///     print!("{}", String::from_utf8_lossy(bytes));
+     /// }
+     /// ```
+     ///
+     /// Compiling 'main.rs' and running the resulting binary will print "adiós".
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! include_bytes {
+         ($file:expr $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Expands to a string that represents the current module path.
+     ///
+     /// The current module path can be thought of as the hierarchy of modules
+     /// leading back up to the crate root. The first component of the path
+     /// returned is the name of the crate currently being compiled.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// mod test {
+     ///     pub fn foo() {
+     ///         assert!(module_path!().ends_with("test"));
+     ///     }
+     /// }
+     ///
+     /// test::foo();
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! module_path {
+         () => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Evaluates boolean combinations of configuration flags at compile-time.
+     ///
+     /// In addition to the `#[cfg]` attribute, this macro is provided to allow
+     /// boolean expression evaluation of configuration flags. This frequently
+     /// leads to less duplicated code.
+     ///
+     /// The syntax given to this macro is the same syntax as the [`cfg`]
+     /// attribute.
+     ///
+     /// `cfg!`, unlike `#[cfg]`, does not remove any code and only evaluates to true or false. For
+     /// example, all blocks in an if/else expression need to be valid when `cfg!` is used for
+     /// the condition, regardless of what `cfg!` is evaluating.
+     ///
+     /// [`cfg`]: ../reference/conditional-compilation.html#the-cfg-attribute
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let my_directory = if cfg!(windows) {
+     ///     "windows-specific-directory"
+     /// } else {
+     ///     "unix-directory"
+     /// };
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! cfg {
+         ($($cfg:tt)*) => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Parses a file as an expression or an item according to the context.
+     ///
+     /// The file is located relative to the current file (similarly to how
+     /// modules are found). The provided path is interpreted in a platform-specific
+     /// way at compile time. So, for instance, an invocation with a Windows path
+     /// containing backslashes `\` would not compile correctly on Unix.
+     ///
+     /// Using this macro is often a bad idea, because if the file is
+     /// parsed as an expression, it is going to be placed in the
+     /// surrounding code unhygienically. This could result in variables
+     /// or functions being different from what the file expected if
+     /// there are variables or functions that have the same name in
+     /// the current file.
+     ///
+     /// # Examples
+     ///
+     /// Assume there are two files in the same directory with the following
+     /// contents:
+     ///
+     /// File 'monkeys.in':
+     ///
+     /// ```ignore (only-for-syntax-highlight)
+     /// ['🙈', '🙊', '🙉']
+     ///     .iter()
+     ///     .cycle()
+     ///     .take(6)
+     ///     .collect::<String>()
+     /// ```
+     ///
+     /// File 'main.rs':
+     ///
+     /// ```ignore (cannot-doctest-external-file-dependency)
+     /// fn main() {
+     ///     let my_string = include!("monkeys.in");
+     ///     assert_eq!("🙈🙊🙉🙈🙊🙉", my_string);
+     ///     println!("{}", my_string);
+     /// }
+     /// ```
+     ///
+     /// Compiling 'main.rs' and running the resulting binary will print
+     /// "🙈🙊🙉🙈🙊🙉".
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! include {
+         ($file:expr $(,)?) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Asserts that a boolean expression is `true` at runtime.
+     ///
+     /// This will invoke the [`panic!`] macro if the provided expression cannot be
+     /// evaluated to `true` at runtime.
+     ///
+     /// # Uses
+     ///
+     /// Assertions are always checked in both debug and release builds, and cannot
+     /// be disabled. See [`debug_assert!`] for assertions that are not enabled in
+     /// release builds by default.
+     ///
+     /// Unsafe code may rely on `assert!` to enforce run-time invariants that, if
+     /// violated could lead to unsafety.
+     ///
+     /// Other use-cases of `assert!` include testing and enforcing run-time
+     /// invariants in safe code (whose violation cannot result in unsafety).
+     ///
+     /// # Custom Messages
+     ///
+     /// This macro has a second form, where a custom panic message can
+     /// be provided with or without arguments for formatting. See [`std::fmt`]
+     /// for syntax for this form.
+     ///
+     /// [`std::fmt`]: crate::fmt
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// // the panic message for these assertions is the stringified value of the
+     /// // expression given.
+     /// assert!(true);
+     ///
+     /// fn some_computation() -> bool { true } // a very simple function
+     ///
+     /// assert!(some_computation());
+     ///
+     /// // assert with a custom message
+     /// let x = true;
+     /// assert!(x, "x wasn't true!");
+     ///
+     /// let a = 3; let b = 27;
+     /// assert!(a + b == 30, "a = {}, b = {}", a, b);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! assert {
+         ($cond:expr $(,)?) => {{ /* compiler built-in */ }};
+         ($cond:expr, $($arg:tt)+) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Inline assembly.
+     ///
+     /// Read the [unstable book] for the usage.
+     ///
+     /// [unstable book]: ../unstable-book/library-features/asm.html
+     #[unstable(
+         feature = "asm",
+         issue = "72016",
+         reason = "inline assembly is not stable enough for use and is subject to change"
+     )]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! asm {
+         ("assembly template",
+             $(operands,)*
+             $(options($(option),*))?
+         ) => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// LLVM-style inline assembly.
+     ///
+     /// Read the [unstable book] for the usage.
+     ///
+     /// [unstable book]: ../unstable-book/library-features/llvm-asm.html
+     #[unstable(
+         feature = "llvm_asm",
+         issue = "70173",
+         reason = "prefer using the new asm! syntax instead"
+     )]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! llvm_asm {
+         ("assembly template"
+                         : $("output"(operand),)*
+                         : $("input"(operand),)*
+                         : $("clobbers",)*
+                         : $("options",)*) => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Module-level inline assembly.
+     #[unstable(
+         feature = "global_asm",
+         issue = "35119",
+         reason = "`global_asm!` is not stable enough for use and is subject to change"
+     )]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! global_asm {
+         ("assembly") => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Prints passed tokens into the standard output.
+     #[unstable(
+         feature = "log_syntax",
+         issue = "29598",
+         reason = "`log_syntax!` is not stable enough for use and is subject to change"
+     )]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! log_syntax {
+         ($($arg:tt)*) => {
+             /* compiler built-in */
+         };
+     }
+ 
+     /// Enables or disables tracing functionality used for debugging other macros.
+     #[unstable(
+         feature = "trace_macros",
+         issue = "29598",
+         reason = "`trace_macros` is not stable enough for use and is subject to change"
+     )]
+     #[rustc_builtin_macro]
+     #[macro_export]
+     macro_rules! trace_macros {
+         (true) => {{ /* compiler built-in */ }};
+         (false) => {{ /* compiler built-in */ }};
+     }
+ 
+     /// Attribute macro applied to a function to turn it into a unit test.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[allow_internal_unstable(test, rustc_attrs)]
+     #[rustc_builtin_macro]
+     pub macro test($item:item) {
+         /* compiler built-in */
+     }
+ 
+     /// Attribute macro applied to a function to turn it into a benchmark test.
+     #[unstable(
+         feature = "test",
+         issue = "50297",
+         soft,
+         reason = "`bench` is a part of custom test frameworks which are unstable"
+     )]
+     #[allow_internal_unstable(test, rustc_attrs)]
+     #[rustc_builtin_macro]
+     pub macro bench($item:item) {
+         /* compiler built-in */
+     }
+ 
+     /// An implementation detail of the `#[test]` and `#[bench]` macros.
+     #[unstable(
+         feature = "custom_test_frameworks",
+         issue = "50297",
+         reason = "custom test frameworks are an unstable feature"
+     )]
+     #[allow_internal_unstable(test, rustc_attrs)]
+     #[rustc_builtin_macro]
+     pub macro test_case($item:item) {
+         /* compiler built-in */
+     }
+ 
+     /// Attribute macro applied to a static to register it as a global allocator.
+     ///
+     /// See also [`std::alloc::GlobalAlloc`](../std/alloc/trait.GlobalAlloc.html).
+     #[stable(feature = "global_allocator", since = "1.28.0")]
+     #[allow_internal_unstable(rustc_attrs)]
+     #[rustc_builtin_macro]
+     pub macro global_allocator($item:item) {
+         /* compiler built-in */
+     }
+ 
+     /// Keeps the item it's applied to if the passed path is accessible, and removes it otherwise.
+     #[unstable(
+         feature = "cfg_accessible",
+         issue = "64797",
+         reason = "`cfg_accessible` is not fully implemented"
+     )]
+     #[rustc_builtin_macro]
+     pub macro cfg_accessible($item:item) {
+         /* compiler built-in */
+     }
+ 
+     /// Unstable implementation detail of the `rustc` compiler, do not use.
+     #[rustc_builtin_macro]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[allow_internal_unstable(core_intrinsics, libstd_sys_internals)]
+     pub macro RustcDecodable($item:item) {
+         /* compiler built-in */
+     }
+ 
+     /// Unstable implementation detail of the `rustc` compiler, do not use.
+     #[rustc_builtin_macro]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[allow_internal_unstable(core_intrinsics)]
+     pub macro RustcEncodable($item:item) {
+         /* compiler built-in */
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/macros/panic.md gcc-16-20251102/libgrust/rustc-lib/core/src/macros/panic.md
*** gcc-16-20251026/libgrust/rustc-lib/core/src/macros/panic.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/macros/panic.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,47 ----
+ Panics the current thread.
+ 
+ This allows a program to terminate immediately and provide feedback
+ to the caller of the program. `panic!` should be used when a program reaches
+ an unrecoverable state.
+ 
+ This macro is the perfect way to assert conditions in example code and in
+ tests. `panic!` is closely tied with the `unwrap` method of both
+ [`Option`][ounwrap] and [`Result`][runwrap] enums. Both implementations call
+ `panic!` when they are set to [`None`] or [`Err`] variants.
+ 
+ This macro is used to inject panic into a Rust thread, causing the thread to
+ panic entirely. Each thread's panic can be reaped as the [`Box`]`<`[`Any`]`>` type,
+ and the single-argument form of the `panic!` macro will be the value which
+ is transmitted.
+ 
+ [`Result`] enum is often a better solution for recovering from errors than
+ using the `panic!` macro. This macro should be used to avoid proceeding using
+ incorrect values, such as from external sources. Detailed information about
+ error handling is found in the [book].
+ 
+ The multi-argument form of this macro panics with a string and has the
+ [`format!`] syntax for building a string.
+ 
+ See also the macro [`compile_error!`], for raising errors during compilation.
+ 
+ [ounwrap]: Option::unwrap
+ [runwrap]: Result::unwrap
+ [`Box`]: ../std/boxed/struct.Box.html
+ [`Any`]: crate::any::Any
+ [`format!`]: ../std/macro.format.html
+ [book]: ../book/ch09-00-error-handling.html
+ 
+ # Current implementation
+ 
+ If the main thread panics it will terminate all your threads and end your
+ program with code `101`.
+ 
+ # Examples
+ 
+ ```should_panic
+ # #![allow(unreachable_code)]
+ panic!();
+ panic!("this is a terrible mistake!");
+ panic!(4); // panic with the value of 4 to be collected elsewhere
+ panic!("this is a {} {message}", "fancy", message = "message");
+ ```
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/marker.rs gcc-16-20251102/libgrust/rustc-lib/core/src/marker.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/marker.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/marker.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,830 ----
+ //! Primitive traits and types representing basic properties of types.
+ //!
+ //! Rust types can be classified in various useful ways according to
+ //! their intrinsic properties. These classifications are represented
+ //! as traits.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::cell::UnsafeCell;
+ use crate::cmp;
+ use crate::fmt::Debug;
+ use crate::hash::Hash;
+ use crate::hash::Hasher;
+ 
+ /// Types that can be transferred across thread boundaries.
+ ///
+ /// This trait is automatically implemented when the compiler determines it's
+ /// appropriate.
+ ///
+ /// An example of a non-`Send` type is the reference-counting pointer
+ /// [`rc::Rc`][`Rc`]. If two threads attempt to clone [`Rc`]s that point to the same
+ /// reference-counted value, they might try to update the reference count at the
+ /// same time, which is [undefined behavior][ub] because [`Rc`] doesn't use atomic
+ /// operations. Its cousin [`sync::Arc`][arc] does use atomic operations (incurring
+ /// some overhead) and thus is `Send`.
+ ///
+ /// See [the Nomicon](../../nomicon/send-and-sync.html) for more details.
+ ///
+ /// [`Rc`]: ../../std/rc/struct.Rc.html
+ /// [arc]: ../../std/sync/struct.Arc.html
+ /// [ub]: ../../reference/behavior-considered-undefined.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[cfg_attr(not(test), rustc_diagnostic_item = "send_trait")]
+ #[rustc_on_unimplemented(
+     message = "`{Self}` cannot be sent between threads safely",
+     label = "`{Self}` cannot be sent between threads safely"
+ )]
+ pub unsafe auto trait Send {
+     // empty.
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Send for *const T {}
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Send for *mut T {}
+ 
+ /// Types with a constant size known at compile time.
+ ///
+ /// All type parameters have an implicit bound of `Sized`. The special syntax
+ /// `?Sized` can be used to remove this bound if it's not appropriate.
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// struct Foo<T>(T);
+ /// struct Bar<T: ?Sized>(T);
+ ///
+ /// // struct FooUse(Foo<[i32]>); // error: Sized is not implemented for [i32]
+ /// struct BarUse(Bar<[i32]>); // OK
+ /// ```
+ ///
+ /// The one exception is the implicit `Self` type of a trait. A trait does not
+ /// have an implicit `Sized` bound as this is incompatible with [trait object]s
+ /// where, by definition, the trait needs to work with all possible implementors,
+ /// and thus could be any size.
+ ///
+ /// Although Rust will let you bind `Sized` to a trait, you won't
+ /// be able to use it to form a trait object later:
+ ///
+ /// ```
+ /// # #![allow(unused_variables)]
+ /// trait Foo { }
+ /// trait Bar: Sized { }
+ ///
+ /// struct Impl;
+ /// impl Foo for Impl { }
+ /// impl Bar for Impl { }
+ ///
+ /// let x: &dyn Foo = &Impl;    // OK
+ /// // let y: &dyn Bar = &Impl; // error: the trait `Bar` cannot
+ ///                             // be made into an object
+ /// ```
+ ///
+ /// [trait object]: ../../book/ch17-02-trait-objects.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[lang = "sized"]
+ #[rustc_on_unimplemented(
+     message = "the size for values of type `{Self}` cannot be known at compilation time",
+     label = "doesn't have a size known at compile-time"
+ )]
+ #[fundamental] // for Default, for example, which requires that `[T]: !Default` be evaluatable
+ #[rustc_specialization_trait]
+ pub trait Sized {
+     // Empty.
+ }
+ 
+ /// Types that can be "unsized" to a dynamically-sized type.
+ ///
+ /// For example, the sized array type `[i8; 2]` implements `Unsize<[i8]>` and
+ /// `Unsize<dyn fmt::Debug>`.
+ ///
+ /// All implementations of `Unsize` are provided automatically by the compiler.
+ ///
+ /// `Unsize` is implemented for:
+ ///
+ /// - `[T; N]` is `Unsize<[T]>`
+ /// - `T` is `Unsize<dyn Trait>` when `T: Trait`
+ /// - `Foo<..., T, ...>` is `Unsize<Foo<..., U, ...>>` if:
+ ///   - `T: Unsize<U>`
+ ///   - Foo is a struct
+ ///   - Only the last field of `Foo` has a type involving `T`
+ ///   - `T` is not part of the type of any other fields
+ ///   - `Bar<T>: Unsize<Bar<U>>`, if the last field of `Foo` has type `Bar<T>`
+ ///
+ /// `Unsize` is used along with [`ops::CoerceUnsized`] to allow
+ /// "user-defined" containers such as [`Rc`] to contain dynamically-sized
+ /// types. See the [DST coercion RFC][RFC982] and [the nomicon entry on coercion][nomicon-coerce]
+ /// for more details.
+ ///
+ /// [`ops::CoerceUnsized`]: crate::ops::CoerceUnsized
+ /// [`Rc`]: ../../std/rc/struct.Rc.html
+ /// [RFC982]: https://github.com/rust-lang/rfcs/blob/master/text/0982-dst-coercion.md
+ /// [nomicon-coerce]: ../../nomicon/coercions.html
+ #[unstable(feature = "unsize", issue = "27732")]
+ #[lang = "unsize"]
+ pub trait Unsize<T: ?Sized> {
+     // Empty.
+ }
+ 
+ /// Required trait for constants used in pattern matches.
+ ///
+ /// Any type that derives `PartialEq` automatically implements this trait,
+ /// *regardless* of whether its type-parameters implement `Eq`.
+ ///
+ /// If a `const` item contains some type that does not implement this trait,
+ /// then that type either (1.) does not implement `PartialEq` (which means the
+ /// constant will not provide that comparison method, which code generation
+ /// assumes is available), or (2.) it implements *its own* version of
+ /// `PartialEq` (which we assume does not conform to a structural-equality
+ /// comparison).
+ ///
+ /// In either of the two scenarios above, we reject usage of such a constant in
+ /// a pattern match.
+ ///
+ /// See also the [structural match RFC][RFC1445], and [issue 63438] which
+ /// motivated migrating from attribute-based design to this trait.
+ ///
+ /// [RFC1445]: https://github.com/rust-lang/rfcs/blob/master/text/1445-restrict-constants-in-patterns.md
+ /// [issue 63438]: https://github.com/rust-lang/rust/issues/63438
+ #[unstable(feature = "structural_match", issue = "31434")]
+ #[rustc_on_unimplemented(message = "the type `{Self}` does not `#[derive(PartialEq)]`")]
+ #[lang = "structural_peq"]
+ pub trait StructuralPartialEq {
+     // Empty.
+ }
+ 
+ /// Required trait for constants used in pattern matches.
+ ///
+ /// Any type that derives `Eq` automatically implements this trait, *regardless*
+ /// of whether its type-parameters implement `Eq`.
+ ///
+ /// This is a hack to workaround a limitation in our type-system.
+ ///
+ /// Background:
+ ///
+ /// We want to require that types of consts used in pattern matches
+ /// have the attribute `#[derive(PartialEq, Eq)]`.
+ ///
+ /// In a more ideal world, we could check that requirement by just checking that
+ /// the given type implements both (1.) the `StructuralPartialEq` trait *and*
+ /// (2.) the `Eq` trait. However, you can have ADTs that *do* `derive(PartialEq, Eq)`,
+ /// and be a case that we want the compiler to accept, and yet the constant's
+ /// type fails to implement `Eq`.
+ ///
+ /// Namely, a case like this:
+ ///
+ /// ```rust
+ /// #[derive(PartialEq, Eq)]
+ /// struct Wrap<X>(X);
+ /// fn higher_order(_: &()) { }
+ /// const CFN: Wrap<fn(&())> = Wrap(higher_order);
+ /// fn main() {
+ ///     match CFN {
+ ///         CFN => {}
+ ///         _ => {}
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// (The problem in the above code is that `Wrap<fn(&())>` does not implement
+ /// `PartialEq`, nor `Eq`, because `for<'a> fn(&'a _)` does not implement those
+ /// traits.)
+ ///
+ /// Therefore, we cannot rely on naive check for `StructuralPartialEq` and
+ /// mere `Eq`.
+ ///
+ /// As a hack to work around this, we use two separate traits injected by each
+ /// of the two derives (`#[derive(PartialEq)]` and `#[derive(Eq)]`) and check
+ /// that both of them are present as part of structural-match checking.
+ #[unstable(feature = "structural_match", issue = "31434")]
+ #[rustc_on_unimplemented(message = "the type `{Self}` does not `#[derive(Eq)]`")]
+ #[lang = "structural_teq"]
+ pub trait StructuralEq {
+     // Empty.
+ }
+ 
+ /// Types whose values can be duplicated simply by copying bits.
+ ///
+ /// By default, variable bindings have 'move semantics.' In other
+ /// words:
+ ///
+ /// ```
+ /// #[derive(Debug)]
+ /// struct Foo;
+ ///
+ /// let x = Foo;
+ ///
+ /// let y = x;
+ ///
+ /// // `x` has moved into `y`, and so cannot be used
+ ///
+ /// // println!("{:?}", x); // error: use of moved value
+ /// ```
+ ///
+ /// However, if a type implements `Copy`, it instead has 'copy semantics':
+ ///
+ /// ```
+ /// // We can derive a `Copy` implementation. `Clone` is also required, as it's
+ /// // a supertrait of `Copy`.
+ /// #[derive(Debug, Copy, Clone)]
+ /// struct Foo;
+ ///
+ /// let x = Foo;
+ ///
+ /// let y = x;
+ ///
+ /// // `y` is a copy of `x`
+ ///
+ /// println!("{:?}", x); // A-OK!
+ /// ```
+ ///
+ /// It's important to note that in these two examples, the only difference is whether you
+ /// are allowed to access `x` after the assignment. Under the hood, both a copy and a move
+ /// can result in bits being copied in memory, although this is sometimes optimized away.
+ ///
+ /// ## How can I implement `Copy`?
+ ///
+ /// There are two ways to implement `Copy` on your type. The simplest is to use `derive`:
+ ///
+ /// ```
+ /// #[derive(Copy, Clone)]
+ /// struct MyStruct;
+ /// ```
+ ///
+ /// You can also implement `Copy` and `Clone` manually:
+ ///
+ /// ```
+ /// struct MyStruct;
+ ///
+ /// impl Copy for MyStruct { }
+ ///
+ /// impl Clone for MyStruct {
+ ///     fn clone(&self) -> MyStruct {
+ ///         *self
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// There is a small difference between the two: the `derive` strategy will also place a `Copy`
+ /// bound on type parameters, which isn't always desired.
+ ///
+ /// ## What's the difference between `Copy` and `Clone`?
+ ///
+ /// Copies happen implicitly, for example as part of an assignment `y = x`. The behavior of
+ /// `Copy` is not overloadable; it is always a simple bit-wise copy.
+ ///
+ /// Cloning is an explicit action, `x.clone()`. The implementation of [`Clone`] can
+ /// provide any type-specific behavior necessary to duplicate values safely. For example,
+ /// the implementation of [`Clone`] for [`String`] needs to copy the pointed-to string
+ /// buffer in the heap. A simple bitwise copy of [`String`] values would merely copy the
+ /// pointer, leading to a double free down the line. For this reason, [`String`] is [`Clone`]
+ /// but not `Copy`.
+ ///
+ /// [`Clone`] is a supertrait of `Copy`, so everything which is `Copy` must also implement
+ /// [`Clone`]. If a type is `Copy` then its [`Clone`] implementation only needs to return `*self`
+ /// (see the example above).
+ ///
+ /// ## When can my type be `Copy`?
+ ///
+ /// A type can implement `Copy` if all of its components implement `Copy`. For example, this
+ /// struct can be `Copy`:
+ ///
+ /// ```
+ /// # #[allow(dead_code)]
+ /// #[derive(Copy, Clone)]
+ /// struct Point {
+ ///    x: i32,
+ ///    y: i32,
+ /// }
+ /// ```
+ ///
+ /// A struct can be `Copy`, and [`i32`] is `Copy`, therefore `Point` is eligible to be `Copy`.
+ /// By contrast, consider
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// # struct Point;
+ /// struct PointList {
+ ///     points: Vec<Point>,
+ /// }
+ /// ```
+ ///
+ /// The struct `PointList` cannot implement `Copy`, because [`Vec<T>`] is not `Copy`. If we
+ /// attempt to derive a `Copy` implementation, we'll get an error:
+ ///
+ /// ```text
+ /// the trait `Copy` may not be implemented for this type; field `points` does not implement `Copy`
+ /// ```
+ ///
+ /// Shared references (`&T`) are also `Copy`, so a type can be `Copy`, even when it holds
+ /// shared references of types `T` that are *not* `Copy`. Consider the following struct,
+ /// which can implement `Copy`, because it only holds a *shared reference* to our non-`Copy`
+ /// type `PointList` from above:
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// # struct PointList;
+ /// #[derive(Copy, Clone)]
+ /// struct PointListWrapper<'a> {
+ ///     point_list_ref: &'a PointList,
+ /// }
+ /// ```
+ ///
+ /// ## When *can't* my type be `Copy`?
+ ///
+ /// Some types can't be copied safely. For example, copying `&mut T` would create an aliased
+ /// mutable reference. Copying [`String`] would duplicate responsibility for managing the
+ /// [`String`]'s buffer, leading to a double free.
+ ///
+ /// Generalizing the latter case, any type implementing [`Drop`] can't be `Copy`, because it's
+ /// managing some resource besides its own [`size_of::<T>`] bytes.
+ ///
+ /// If you try to implement `Copy` on a struct or enum containing non-`Copy` data, you will get
+ /// the error [E0204].
+ ///
+ /// [E0204]: ../../error-index.html#E0204
+ ///
+ /// ## When *should* my type be `Copy`?
+ ///
+ /// Generally speaking, if your type _can_ implement `Copy`, it should. Keep in mind, though,
+ /// that implementing `Copy` is part of the public API of your type. If the type might become
+ /// non-`Copy` in the future, it could be prudent to omit the `Copy` implementation now, to
+ /// avoid a breaking API change.
+ ///
+ /// ## Additional implementors
+ ///
+ /// In addition to the [implementors listed below][impls],
+ /// the following types also implement `Copy`:
+ ///
+ /// * Function item types (i.e., the distinct types defined for each function)
+ /// * Function pointer types (e.g., `fn() -> i32`)
+ /// * Array types, for all sizes, if the item type also implements `Copy` (e.g., `[i32; 123456]`)
+ /// * Tuple types, if each component also implements `Copy` (e.g., `()`, `(i32, bool)`)
+ /// * Closure types, if they capture no value from the environment
+ ///   or if all such captured values implement `Copy` themselves.
+ ///   Note that variables captured by shared reference always implement `Copy`
+ ///   (even if the referent doesn't),
+ ///   while variables captured by mutable reference never implement `Copy`.
+ ///
+ /// [`Vec<T>`]: ../../std/vec/struct.Vec.html
+ /// [`String`]: ../../std/string/struct.String.html
+ /// [`size_of::<T>`]: crate::mem::size_of
+ /// [impls]: #implementors
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[lang = "copy"]
+ // FIXME(matthewjasper) This allows copying a type that doesn't implement
+ // `Copy` because of unsatisfied lifetime bounds (copying `A<'_>` when only
+ // `A<'static>: Copy` and `A<'_>: Clone`).
+ // We have this attribute here for now only because there are quite a few
+ // existing specializations on `Copy` that already exist in the standard
+ // library, and there's no way to safely have this behavior right now.
+ #[rustc_unsafe_specialization_marker]
+ pub trait Copy: Clone {
+     // Empty.
+ }
+ 
+ /// Derive macro generating an impl of the trait `Copy`.
+ #[rustc_builtin_macro]
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow_internal_unstable(core_intrinsics, derive_clone_copy)]
+ pub macro Copy($item:item) {
+     /* compiler built-in */
+ }
+ 
+ /// Types for which it is safe to share references between threads.
+ ///
+ /// This trait is automatically implemented when the compiler determines
+ /// it's appropriate.
+ ///
+ /// The precise definition is: a type `T` is [`Sync`] if and only if `&T` is
+ /// [`Send`]. In other words, if there is no possibility of
+ /// [undefined behavior][ub] (including data races) when passing
+ /// `&T` references between threads.
+ ///
+ /// As one would expect, primitive types like [`u8`] and [`f64`]
+ /// are all [`Sync`], and so are simple aggregate types containing them,
+ /// like tuples, structs and enums. More examples of basic [`Sync`]
+ /// types include "immutable" types like `&T`, and those with simple
+ /// inherited mutability, such as [`Box<T>`][box], [`Vec<T>`][vec] and
+ /// most other collection types. (Generic parameters need to be [`Sync`]
+ /// for their container to be [`Sync`].)
+ ///
+ /// A somewhat surprising consequence of the definition is that `&mut T`
+ /// is `Sync` (if `T` is `Sync`) even though it seems like that might
+ /// provide unsynchronized mutation. The trick is that a mutable
+ /// reference behind a shared reference (that is, `& &mut T`)
+ /// becomes read-only, as if it were a `& &T`. Hence there is no risk
+ /// of a data race.
+ ///
+ /// Types that are not `Sync` are those that have "interior
+ /// mutability" in a non-thread-safe form, such as [`Cell`][cell]
+ /// and [`RefCell`][refcell]. These types allow for mutation of
+ /// their contents even through an immutable, shared reference. For
+ /// example the `set` method on [`Cell<T>`][cell] takes `&self`, so it requires
+ /// only a shared reference [`&Cell<T>`][cell]. The method performs no
+ /// synchronization, thus [`Cell`][cell] cannot be `Sync`.
+ ///
+ /// Another example of a non-`Sync` type is the reference-counting
+ /// pointer [`Rc`][rc]. Given any reference [`&Rc<T>`][rc], you can clone
+ /// a new [`Rc<T>`][rc], modifying the reference counts in a non-atomic way.
+ ///
+ /// For cases when one does need thread-safe interior mutability,
+ /// Rust provides [atomic data types], as well as explicit locking via
+ /// [`sync::Mutex`][mutex] and [`sync::RwLock`][rwlock]. These types
+ /// ensure that any mutation cannot cause data races, hence the types
+ /// are `Sync`. Likewise, [`sync::Arc`][arc] provides a thread-safe
+ /// analogue of [`Rc`][rc].
+ ///
+ /// Any types with interior mutability must also use the
+ /// [`cell::UnsafeCell`][unsafecell] wrapper around the value(s) which
+ /// can be mutated through a shared reference. Failing to doing this is
+ /// [undefined behavior][ub]. For example, [`transmute`][transmute]-ing
+ /// from `&T` to `&mut T` is invalid.
+ ///
+ /// See [the Nomicon][nomicon-send-and-sync] for more details about `Sync`.
+ ///
+ /// [box]: ../../std/boxed/struct.Box.html
+ /// [vec]: ../../std/vec/struct.Vec.html
+ /// [cell]: crate::cell::Cell
+ /// [refcell]: crate::cell::RefCell
+ /// [rc]: ../../std/rc/struct.Rc.html
+ /// [arc]: ../../std/sync/struct.Arc.html
+ /// [atomic data types]: crate::sync::atomic
+ /// [mutex]: ../../std/sync/struct.Mutex.html
+ /// [rwlock]: ../../std/sync/struct.RwLock.html
+ /// [unsafecell]: crate::cell::UnsafeCell
+ /// [ub]: ../../reference/behavior-considered-undefined.html
+ /// [transmute]: crate::mem::transmute
+ /// [nomicon-send-and-sync]: ../../nomicon/send-and-sync.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[cfg_attr(not(test), rustc_diagnostic_item = "sync_trait")]
+ #[lang = "sync"]
+ #[rustc_on_unimplemented(
+     message = "`{Self}` cannot be shared between threads safely",
+     label = "`{Self}` cannot be shared between threads safely"
+ )]
+ pub unsafe auto trait Sync {
+     // FIXME(estebank): once support to add notes in `rustc_on_unimplemented`
+     // lands in beta, and it has been extended to check whether a closure is
+     // anywhere in the requirement chain, extend it as such (#48534):
+     // ```
+     // on(
+     //     closure,
+     //     note="`{Self}` cannot be shared safely, consider marking the closure `move`"
+     // ),
+     // ```
+ 
+     // Empty
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Sync for *const T {}
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !Sync for *mut T {}
+ 
+ macro_rules! impls {
+     ($t: ident) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> Hash for $t<T> {
+             #[inline]
+             fn hash<H: Hasher>(&self, _: &mut H) {}
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> cmp::PartialEq for $t<T> {
+             fn eq(&self, _other: &$t<T>) -> bool {
+                 true
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> cmp::Eq for $t<T> {}
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> cmp::PartialOrd for $t<T> {
+             fn partial_cmp(&self, _other: &$t<T>) -> Option<cmp::Ordering> {
+                 Option::Some(cmp::Ordering::Equal)
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> cmp::Ord for $t<T> {
+             fn cmp(&self, _other: &$t<T>) -> cmp::Ordering {
+                 cmp::Ordering::Equal
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> Copy for $t<T> {}
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> Clone for $t<T> {
+             fn clone(&self) -> Self {
+                 Self
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T: ?Sized> Default for $t<T> {
+             fn default() -> Self {
+                 Self
+             }
+         }
+ 
+         #[unstable(feature = "structural_match", issue = "31434")]
+         impl<T: ?Sized> StructuralPartialEq for $t<T> {}
+ 
+         #[unstable(feature = "structural_match", issue = "31434")]
+         impl<T: ?Sized> StructuralEq for $t<T> {}
+     };
+ }
+ 
+ /// Zero-sized type used to mark things that "act like" they own a `T`.
+ ///
+ /// Adding a `PhantomData<T>` field to your type tells the compiler that your
+ /// type acts as though it stores a value of type `T`, even though it doesn't
+ /// really. This information is used when computing certain safety properties.
+ ///
+ /// For a more in-depth explanation of how to use `PhantomData<T>`, please see
+ /// [the Nomicon](../../nomicon/phantom-data.html).
+ ///
+ /// # A ghastly note 👻👻👻
+ ///
+ /// Though they both have scary names, `PhantomData` and 'phantom types' are
+ /// related, but not identical. A phantom type parameter is simply a type
+ /// parameter which is never used. In Rust, this often causes the compiler to
+ /// complain, and the solution is to add a "dummy" use by way of `PhantomData`.
+ ///
+ /// # Examples
+ ///
+ /// ## Unused lifetime parameters
+ ///
+ /// Perhaps the most common use case for `PhantomData` is a struct that has an
+ /// unused lifetime parameter, typically as part of some unsafe code. For
+ /// example, here is a struct `Slice` that has two pointers of type `*const T`,
+ /// presumably pointing into an array somewhere:
+ ///
+ /// ```compile_fail,E0392
+ /// struct Slice<'a, T> {
+ ///     start: *const T,
+ ///     end: *const T,
+ /// }
+ /// ```
+ ///
+ /// The intention is that the underlying data is only valid for the
+ /// lifetime `'a`, so `Slice` should not outlive `'a`. However, this
+ /// intent is not expressed in the code, since there are no uses of
+ /// the lifetime `'a` and hence it is not clear what data it applies
+ /// to. We can correct this by telling the compiler to act *as if* the
+ /// `Slice` struct contained a reference `&'a T`:
+ ///
+ /// ```
+ /// use std::marker::PhantomData;
+ ///
+ /// # #[allow(dead_code)]
+ /// struct Slice<'a, T: 'a> {
+ ///     start: *const T,
+ ///     end: *const T,
+ ///     phantom: PhantomData<&'a T>,
+ /// }
+ /// ```
+ ///
+ /// This also in turn requires the annotation `T: 'a`, indicating
+ /// that any references in `T` are valid over the lifetime `'a`.
+ ///
+ /// When initializing a `Slice` you simply provide the value
+ /// `PhantomData` for the field `phantom`:
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// # use std::marker::PhantomData;
+ /// # struct Slice<'a, T: 'a> {
+ /// #     start: *const T,
+ /// #     end: *const T,
+ /// #     phantom: PhantomData<&'a T>,
+ /// # }
+ /// fn borrow_vec<T>(vec: &Vec<T>) -> Slice<'_, T> {
+ ///     let ptr = vec.as_ptr();
+ ///     Slice {
+ ///         start: ptr,
+ ///         end: unsafe { ptr.add(vec.len()) },
+ ///         phantom: PhantomData,
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// ## Unused type parameters
+ ///
+ /// It sometimes happens that you have unused type parameters which
+ /// indicate what type of data a struct is "tied" to, even though that
+ /// data is not actually found in the struct itself. Here is an
+ /// example where this arises with [FFI]. The foreign interface uses
+ /// handles of type `*mut ()` to refer to Rust values of different
+ /// types. We track the Rust type using a phantom type parameter on
+ /// the struct `ExternalResource` which wraps a handle.
+ ///
+ /// [FFI]: ../../book/ch19-01-unsafe-rust.html#using-extern-functions-to-call-external-code
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// # trait ResType { }
+ /// # struct ParamType;
+ /// # mod foreign_lib {
+ /// #     pub fn new(_: usize) -> *mut () { 42 as *mut () }
+ /// #     pub fn do_stuff(_: *mut (), _: usize) {}
+ /// # }
+ /// # fn convert_params(_: ParamType) -> usize { 42 }
+ /// use std::marker::PhantomData;
+ /// use std::mem;
+ ///
+ /// struct ExternalResource<R> {
+ ///    resource_handle: *mut (),
+ ///    resource_type: PhantomData<R>,
+ /// }
+ ///
+ /// impl<R: ResType> ExternalResource<R> {
+ ///     fn new() -> Self {
+ ///         let size_of_res = mem::size_of::<R>();
+ ///         Self {
+ ///             resource_handle: foreign_lib::new(size_of_res),
+ ///             resource_type: PhantomData,
+ ///         }
+ ///     }
+ ///
+ ///     fn do_stuff(&self, param: ParamType) {
+ ///         let foreign_params = convert_params(param);
+ ///         foreign_lib::do_stuff(self.resource_handle, foreign_params);
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// ## Ownership and the drop check
+ ///
+ /// Adding a field of type `PhantomData<T>` indicates that your
+ /// type owns data of type `T`. This in turn implies that when your
+ /// type is dropped, it may drop one or more instances of the type
+ /// `T`. This has bearing on the Rust compiler's [drop check]
+ /// analysis.
+ ///
+ /// If your struct does not in fact *own* the data of type `T`, it is
+ /// better to use a reference type, like `PhantomData<&'a T>`
+ /// (ideally) or `PhantomData<*const T>` (if no lifetime applies), so
+ /// as not to indicate ownership.
+ ///
+ /// [drop check]: ../../nomicon/dropck.html
+ #[lang = "phantom_data"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct PhantomData<T: ?Sized>;
+ 
+ impls! { PhantomData }
+ 
+ mod impls {
+     #[stable(feature = "rust1", since = "1.0.0")]
+     unsafe impl<T: Sync + ?Sized> Send for &T {}
+     #[stable(feature = "rust1", since = "1.0.0")]
+     unsafe impl<T: Send + ?Sized> Send for &mut T {}
+ }
+ 
+ /// Compiler-internal trait used to indicate the type of enum discriminants.
+ ///
+ /// This trait is automatically implemented for every type and does not add any
+ /// guarantees to [`mem::Discriminant`]. It is **undefined behavior** to transmute
+ /// between `DiscriminantKind::Discriminant` and `mem::Discriminant`.
+ ///
+ /// [`mem::Discriminant`]: crate::mem::Discriminant
+ #[unstable(
+     feature = "discriminant_kind",
+     issue = "none",
+     reason = "this trait is unlikely to ever be stabilized, use `mem::discriminant` instead"
+ )]
+ #[lang = "discriminant_kind"]
+ pub trait DiscriminantKind {
+     /// The type of the discriminant, which must satisfy the trait
+     /// bounds required by `mem::Discriminant`.
+     #[lang = "discriminant_type"]
+     type Discriminant: Clone + Copy + Debug + Eq + PartialEq + Hash + Send + Sync + Unpin;
+ }
+ 
+ /// Compiler-internal trait used to determine whether a type contains
+ /// any `UnsafeCell` internally, but not through an indirection.
+ /// This affects, for example, whether a `static` of that type is
+ /// placed in read-only static memory or writable static memory.
+ #[lang = "freeze"]
+ pub(crate) unsafe auto trait Freeze {}
+ 
+ impl<T: ?Sized> !Freeze for UnsafeCell<T> {}
+ unsafe impl<T: ?Sized> Freeze for PhantomData<T> {}
+ unsafe impl<T: ?Sized> Freeze for *const T {}
+ unsafe impl<T: ?Sized> Freeze for *mut T {}
+ unsafe impl<T: ?Sized> Freeze for &T {}
+ unsafe impl<T: ?Sized> Freeze for &mut T {}
+ 
+ /// Types that can be safely moved after being pinned.
+ ///
+ /// Rust itself has no notion of immovable types, and considers moves (e.g.,
+ /// through assignment or [`mem::replace`]) to always be safe.
+ ///
+ /// The [`Pin`][Pin] type is used instead to prevent moves through the type
+ /// system. Pointers `P<T>` wrapped in the [`Pin<P<T>>`][Pin] wrapper can't be
+ /// moved out of. See the [`pin` module] documentation for more information on
+ /// pinning.
+ ///
+ /// Implementing the `Unpin` trait for `T` lifts the restrictions of pinning off
+ /// the type, which then allows moving `T` out of [`Pin<P<T>>`][Pin] with
+ /// functions such as [`mem::replace`].
+ ///
+ /// `Unpin` has no consequence at all for non-pinned data. In particular,
+ /// [`mem::replace`] happily moves `!Unpin` data (it works for any `&mut T`, not
+ /// just when `T: Unpin`). However, you cannot use [`mem::replace`] on data
+ /// wrapped inside a [`Pin<P<T>>`][Pin] because you cannot get the `&mut T` you
+ /// need for that, and *that* is what makes this system work.
+ ///
+ /// So this, for example, can only be done on types implementing `Unpin`:
+ ///
+ /// ```rust
+ /// # #![allow(unused_must_use)]
+ /// use std::mem;
+ /// use std::pin::Pin;
+ ///
+ /// let mut string = "this".to_string();
+ /// let mut pinned_string = Pin::new(&mut string);
+ ///
+ /// // We need a mutable reference to call `mem::replace`.
+ /// // We can obtain such a reference by (implicitly) invoking `Pin::deref_mut`,
+ /// // but that is only possible because `String` implements `Unpin`.
+ /// mem::replace(&mut *pinned_string, "other".to_string());
+ /// ```
+ ///
+ /// This trait is automatically implemented for almost every type.
+ ///
+ /// [`mem::replace`]: crate::mem::replace
+ /// [Pin]: crate::pin::Pin
+ /// [`pin` module]: crate::pin
+ #[stable(feature = "pin", since = "1.33.0")]
+ #[rustc_on_unimplemented(
+     on(_Self = "std::future::Future", note = "consider using `Box::pin`",),
+     message = "`{Self}` cannot be unpinned"
+ )]
+ #[lang = "unpin"]
+ pub auto trait Unpin {}
+ 
+ /// A marker type which does not implement `Unpin`.
+ ///
+ /// If a type contains a `PhantomPinned`, it will not implement `Unpin` by default.
+ #[stable(feature = "pin", since = "1.33.0")]
+ #[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
+ pub struct PhantomPinned;
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl !Unpin for PhantomPinned {}
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<'a, T: ?Sized + 'a> Unpin for &'a T {}
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<'a, T: ?Sized + 'a> Unpin for &'a mut T {}
+ 
+ #[stable(feature = "pin_raw", since = "1.38.0")]
+ impl<T: ?Sized> Unpin for *const T {}
+ 
+ #[stable(feature = "pin_raw", since = "1.38.0")]
+ impl<T: ?Sized> Unpin for *mut T {}
+ 
+ /// Implementations of `Copy` for primitive types.
+ ///
+ /// Implementations that cannot be described in Rust
+ /// are implemented in `traits::SelectionContext::copy_clone_conditions()`
+ /// in `rustc_trait_selection`.
+ mod copy_impls {
+ 
+     use super::Copy;
+ 
+     macro_rules! impl_copy {
+         ($($t:ty)*) => {
+             $(
+                 #[stable(feature = "rust1", since = "1.0.0")]
+                 impl Copy for $t {}
+             )*
+         }
+     }
+ 
+     impl_copy! {
+         usize u8 u16 u32 u64 u128
+         isize i8 i16 i32 i64 i128
+         f32 f64
+         bool char
+     }
+ 
+     #[unstable(feature = "never_type", issue = "35121")]
+     impl Copy for ! {}
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Copy for *const T {}
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Copy for *mut T {}
+ 
+     /// Shared references can be copied, but mutable references *cannot*!
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<T: ?Sized> Copy for &T {}
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/mem/manually_drop.rs gcc-16-20251102/libgrust/rustc-lib/core/src/mem/manually_drop.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/mem/manually_drop.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/mem/manually_drop.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,162 ----
+ use crate::ops::{Deref, DerefMut};
+ use crate::ptr;
+ 
+ /// A wrapper to inhibit compiler from automatically calling `T`’s destructor.
+ /// This wrapper is 0-cost.
+ ///
+ /// `ManuallyDrop<T>` is subject to the same layout optimizations as `T`.
+ /// As a consequence, it has *no effect* on the assumptions that the compiler makes
+ /// about its contents. For example, initializing a `ManuallyDrop<&mut T>`
+ /// with [`mem::zeroed`] is undefined behavior.
+ /// If you need to handle uninitialized data, use [`MaybeUninit<T>`] instead.
+ ///
+ /// Note that accessing the value inside a `ManuallyDrop<T>` is safe.
+ /// This means that a `ManuallyDrop<T>` whose content has been dropped must not
+ /// be exposed through a public safe API.
+ /// Correspondingly, `ManuallyDrop::drop` is unsafe.
+ ///
+ /// # `ManuallyDrop` and drop order.
+ ///
+ /// Rust has a well-defined [drop order] of values. To make sure that fields or
+ /// locals are dropped in a specific order, reorder the declarations such that
+ /// the implicit drop order is the correct one.
+ ///
+ /// It is possible to use `ManuallyDrop` to control the drop order, but this
+ /// requires unsafe code and is hard to do correctly in the presence of
+ /// unwinding.
+ ///
+ /// For example, if you want to make sure that a specific field is dropped after
+ /// the others, make it the last field of a struct:
+ ///
+ /// ```
+ /// struct Context;
+ ///
+ /// struct Widget {
+ ///     children: Vec<Widget>,
+ ///     // `context` will be dropped after `children`.
+ ///     // Rust guarantees that fields are dropped in the order of declaration.
+ ///     context: Context,
+ /// }
+ /// ```
+ ///
+ /// [drop order]: https://doc.rust-lang.org/reference/destructors.html
+ /// [`mem::zeroed`]: crate::mem::zeroed
+ /// [`MaybeUninit<T>`]: crate::mem::MaybeUninit
+ #[stable(feature = "manually_drop", since = "1.20.0")]
+ #[lang = "manually_drop"]
+ #[derive(Copy, Clone, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
+ #[repr(transparent)]
+ pub struct ManuallyDrop<T: ?Sized> {
+     value: T,
+ }
+ 
+ impl<T> ManuallyDrop<T> {
+     /// Wrap a value to be manually dropped.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::mem::ManuallyDrop;
+     /// let mut x = ManuallyDrop::new(String::from("Hello World!"));
+     /// x.truncate(5); // You can still safely operate on the value
+     /// assert_eq!(*x, "Hello");
+     /// // But `Drop` will not be run here
+     /// ```
+     #[must_use = "if you don't need the wrapper, you can use `mem::forget` instead"]
+     #[stable(feature = "manually_drop", since = "1.20.0")]
+     #[rustc_const_stable(feature = "const_manually_drop", since = "1.36.0")]
+     #[inline(always)]
+     pub const fn new(value: T) -> ManuallyDrop<T> {
+         ManuallyDrop { value }
+     }
+ 
+     /// Extracts the value from the `ManuallyDrop` container.
+     ///
+     /// This allows the value to be dropped again.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// use std::mem::ManuallyDrop;
+     /// let x = ManuallyDrop::new(Box::new(()));
+     /// let _: Box<()> = ManuallyDrop::into_inner(x); // This drops the `Box`.
+     /// ```
+     #[stable(feature = "manually_drop", since = "1.20.0")]
+     #[rustc_const_stable(feature = "const_manually_drop", since = "1.36.0")]
+     #[inline(always)]
+     pub const fn into_inner(slot: ManuallyDrop<T>) -> T {
+         slot.value
+     }
+ 
+     /// Takes the value from the `ManuallyDrop<T>` container out.
+     ///
+     /// This method is primarily intended for moving out values in drop.
+     /// Instead of using [`ManuallyDrop::drop`] to manually drop the value,
+     /// you can use this method to take the value and use it however desired.
+     ///
+     /// Whenever possible, it is preferable to use [`into_inner`][`ManuallyDrop::into_inner`]
+     /// instead, which prevents duplicating the content of the `ManuallyDrop<T>`.
+     ///
+     /// # Safety
+     ///
+     /// This function semantically moves out the contained value without preventing further usage,
+     /// leaving the state of this container unchanged.
+     /// It is your responsibility to ensure that this `ManuallyDrop` is not used again.
+     ///
+     #[must_use = "if you don't need the value, you can use `ManuallyDrop::drop` instead"]
+     #[stable(feature = "manually_drop_take", since = "1.42.0")]
+     #[inline]
+     pub unsafe fn take(slot: &mut ManuallyDrop<T>) -> T {
+         // SAFETY: we are reading from a reference, which is guaranteed
+         // to be valid for reads.
+         unsafe { ptr::read(&slot.value) }
+     }
+ }
+ 
+ impl<T: ?Sized> ManuallyDrop<T> {
+     /// Manually drops the contained value. This is exactly equivalent to calling
+     /// [`ptr::drop_in_place`] with a pointer to the contained value. As such, unless
+     /// the contained value is a packed struct, the destructor will be called in-place
+     /// without moving the value, and thus can be used to safely drop [pinned] data.
+     ///
+     /// If you have ownership of the value, you can use [`ManuallyDrop::into_inner`] instead.
+     ///
+     /// # Safety
+     ///
+     /// This function runs the destructor of the contained value. Other than changes made by
+     /// the destructor itself, the memory is left unchanged, and so as far as the compiler is
+     /// concerned still holds a bit-pattern which is valid for the type `T`.
+     ///
+     /// However, this "zombie" value should not be exposed to safe code, and this function
+     /// should not be called more than once. To use a value after it's been dropped, or drop
+     /// a value multiple times, can cause Undefined Behavior (depending on what `drop` does).
+     /// This is normally prevented by the type system, but users of `ManuallyDrop` must
+     /// uphold those guarantees without assistance from the compiler.
+     ///
+     /// [pinned]: crate::pin
+     #[stable(feature = "manually_drop", since = "1.20.0")]
+     #[inline]
+     pub unsafe fn drop(slot: &mut ManuallyDrop<T>) {
+         // SAFETY: we are dropping the value pointed to by a mutable reference
+         // which is guaranteed to be valid for writes.
+         // It is up to the caller to make sure that `slot` isn't dropped again.
+         unsafe { ptr::drop_in_place(&mut slot.value) }
+     }
+ }
+ 
+ #[stable(feature = "manually_drop", since = "1.20.0")]
+ impl<T: ?Sized> Deref for ManuallyDrop<T> {
+     type Target = T;
+     #[inline(always)]
+     fn deref(&self) -> &T {
+         &self.value
+     }
+ }
+ 
+ #[stable(feature = "manually_drop", since = "1.20.0")]
+ impl<T: ?Sized> DerefMut for ManuallyDrop<T> {
+     #[inline(always)]
+     fn deref_mut(&mut self) -> &mut T {
+         &mut self.value
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/mem/maybe_uninit.rs gcc-16-20251102/libgrust/rustc-lib/core/src/mem/maybe_uninit.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/mem/maybe_uninit.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/mem/maybe_uninit.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,854 ----
+ use crate::any::type_name;
+ use crate::fmt;
+ use crate::intrinsics;
+ use crate::mem::ManuallyDrop;
+ use crate::ptr;
+ 
+ /// A wrapper type to construct uninitialized instances of `T`.
+ ///
+ /// # Initialization invariant
+ ///
+ /// The compiler, in general, assumes that a variable is properly initialized
+ /// according to the requirements of the variable's type. For example, a variable of
+ /// reference type must be aligned and non-NULL. This is an invariant that must
+ /// *always* be upheld, even in unsafe code. As a consequence, zero-initializing a
+ /// variable of reference type causes instantaneous [undefined behavior][ub],
+ /// no matter whether that reference ever gets used to access memory:
+ ///
+ /// ```rust,no_run
+ /// # #![allow(invalid_value)]
+ /// use std::mem::{self, MaybeUninit};
+ ///
+ /// let x: &i32 = unsafe { mem::zeroed() }; // undefined behavior! ⚠️
+ /// // The equivalent code with `MaybeUninit<&i32>`:
+ /// let x: &i32 = unsafe { MaybeUninit::zeroed().assume_init() }; // undefined behavior! ⚠️
+ /// ```
+ ///
+ /// This is exploited by the compiler for various optimizations, such as eliding
+ /// run-time checks and optimizing `enum` layout.
+ ///
+ /// Similarly, entirely uninitialized memory may have any content, while a `bool` must
+ /// always be `true` or `false`. Hence, creating an uninitialized `bool` is undefined behavior:
+ ///
+ /// ```rust,no_run
+ /// # #![allow(invalid_value)]
+ /// use std::mem::{self, MaybeUninit};
+ ///
+ /// let b: bool = unsafe { mem::uninitialized() }; // undefined behavior! ⚠️
+ /// // The equivalent code with `MaybeUninit<bool>`:
+ /// let b: bool = unsafe { MaybeUninit::uninit().assume_init() }; // undefined behavior! ⚠️
+ /// ```
+ ///
+ /// Moreover, uninitialized memory is special in that the compiler knows that
+ /// it does not have a fixed value. This makes it undefined behavior to have
+ /// uninitialized data in a variable even if that variable has an integer type,
+ /// which otherwise can hold any *fixed* bit pattern:
+ ///
+ /// ```rust,no_run
+ /// # #![allow(invalid_value)]
+ /// use std::mem::{self, MaybeUninit};
+ ///
+ /// let x: i32 = unsafe { mem::uninitialized() }; // undefined behavior! ⚠️
+ /// // The equivalent code with `MaybeUninit<i32>`:
+ /// let x: i32 = unsafe { MaybeUninit::uninit().assume_init() }; // undefined behavior! ⚠️
+ /// ```
+ /// (Notice that the rules around uninitialized integers are not finalized yet, but
+ /// until they are, it is advisable to avoid them.)
+ ///
+ /// On top of that, remember that most types have additional invariants beyond merely
+ /// being considered initialized at the type level. For example, a `1`-initialized [`Vec<T>`]
+ /// is considered initialized (under the current implementation; this does not constitute
+ /// a stable guarantee) because the only requirement the compiler knows about it
+ /// is that the data pointer must be non-null. Creating such a `Vec<T>` does not cause
+ /// *immediate* undefined behavior, but will cause undefined behavior with most
+ /// safe operations (including dropping it).
+ ///
+ /// [`Vec<T>`]: ../../std/vec/struct.Vec.html
+ ///
+ /// # Examples
+ ///
+ /// `MaybeUninit<T>` serves to enable unsafe code to deal with uninitialized data.
+ /// It is a signal to the compiler indicating that the data here might *not*
+ /// be initialized:
+ ///
+ /// ```rust
+ /// use std::mem::MaybeUninit;
+ ///
+ /// // Create an explicitly uninitialized reference. The compiler knows that data inside
+ /// // a `MaybeUninit<T>` may be invalid, and hence this is not UB:
+ /// let mut x = MaybeUninit::<&i32>::uninit();
+ /// // Set it to a valid value.
+ /// unsafe { x.as_mut_ptr().write(&0); }
+ /// // Extract the initialized data -- this is only allowed *after* properly
+ /// // initializing `x`!
+ /// let x = unsafe { x.assume_init() };
+ /// ```
+ ///
+ /// The compiler then knows to not make any incorrect assumptions or optimizations on this code.
+ ///
+ /// You can think of `MaybeUninit<T>` as being a bit like `Option<T>` but without
+ /// any of the run-time tracking and without any of the safety checks.
+ ///
+ /// ## out-pointers
+ ///
+ /// You can use `MaybeUninit<T>` to implement "out-pointers": instead of returning data
+ /// from a function, pass it a pointer to some (uninitialized) memory to put the
+ /// result into. This can be useful when it is important for the caller to control
+ /// how the memory the result is stored in gets allocated, and you want to avoid
+ /// unnecessary moves.
+ ///
+ /// ```
+ /// use std::mem::MaybeUninit;
+ ///
+ /// unsafe fn make_vec(out: *mut Vec<i32>) {
+ ///     // `write` does not drop the old contents, which is important.
+ ///     out.write(vec![1, 2, 3]);
+ /// }
+ ///
+ /// let mut v = MaybeUninit::uninit();
+ /// unsafe { make_vec(v.as_mut_ptr()); }
+ /// // Now we know `v` is initialized! This also makes sure the vector gets
+ /// // properly dropped.
+ /// let v = unsafe { v.assume_init() };
+ /// assert_eq!(&v, &[1, 2, 3]);
+ /// ```
+ ///
+ /// ## Initializing an array element-by-element
+ ///
+ /// `MaybeUninit<T>` can be used to initialize a large array element-by-element:
+ ///
+ /// ```
+ /// use std::mem::{self, MaybeUninit};
+ ///
+ /// let data = {
+ ///     // Create an uninitialized array of `MaybeUninit`. The `assume_init` is
+ ///     // safe because the type we are claiming to have initialized here is a
+ ///     // bunch of `MaybeUninit`s, which do not require initialization.
+ ///     let mut data: [MaybeUninit<Vec<u32>>; 1000] = unsafe {
+ ///         MaybeUninit::uninit().assume_init()
+ ///     };
+ ///
+ ///     // Dropping a `MaybeUninit` does nothing. Thus using raw pointer
+ ///     // assignment instead of `ptr::write` does not cause the old
+ ///     // uninitialized value to be dropped. Also if there is a panic during
+ ///     // this loop, we have a memory leak, but there is no memory safety
+ ///     // issue.
+ ///     for elem in &mut data[..] {
+ ///         *elem = MaybeUninit::new(vec![42]);
+ ///     }
+ ///
+ ///     // Everything is initialized. Transmute the array to the
+ ///     // initialized type.
+ ///     unsafe { mem::transmute::<_, [Vec<u32>; 1000]>(data) }
+ /// };
+ ///
+ /// assert_eq!(&data[0], &[42]);
+ /// ```
+ ///
+ /// You can also work with partially initialized arrays, which could
+ /// be found in low-level datastructures.
+ ///
+ /// ```
+ /// use std::mem::MaybeUninit;
+ /// use std::ptr;
+ ///
+ /// // Create an uninitialized array of `MaybeUninit`. The `assume_init` is
+ /// // safe because the type we are claiming to have initialized here is a
+ /// // bunch of `MaybeUninit`s, which do not require initialization.
+ /// let mut data: [MaybeUninit<String>; 1000] = unsafe { MaybeUninit::uninit().assume_init() };
+ /// // Count the number of elements we have assigned.
+ /// let mut data_len: usize = 0;
+ ///
+ /// for elem in &mut data[0..500] {
+ ///     *elem = MaybeUninit::new(String::from("hello"));
+ ///     data_len += 1;
+ /// }
+ ///
+ /// // For each item in the array, drop if we allocated it.
+ /// for elem in &mut data[0..data_len] {
+ ///     unsafe { ptr::drop_in_place(elem.as_mut_ptr()); }
+ /// }
+ /// ```
+ ///
+ /// ## Initializing a struct field-by-field
+ ///
+ /// There is currently no supported way to create a raw pointer or reference
+ /// to a field of a struct inside `MaybeUninit<Struct>`. That means it is not possible
+ /// to create a struct by calling `MaybeUninit::uninit::<Struct>()` and then writing
+ /// to its fields.
+ ///
+ /// [ub]: ../../reference/behavior-considered-undefined.html
+ ///
+ /// # Layout
+ ///
+ /// `MaybeUninit<T>` is guaranteed to have the same size, alignment, and ABI as `T`:
+ ///
+ /// ```rust
+ /// use std::mem::{MaybeUninit, size_of, align_of};
+ /// assert_eq!(size_of::<MaybeUninit<u64>>(), size_of::<u64>());
+ /// assert_eq!(align_of::<MaybeUninit<u64>>(), align_of::<u64>());
+ /// ```
+ ///
+ /// However remember that a type *containing* a `MaybeUninit<T>` is not necessarily the same
+ /// layout; Rust does not in general guarantee that the fields of a `Foo<T>` have the same order as
+ /// a `Foo<U>` even if `T` and `U` have the same size and alignment. Furthermore because any bit
+ /// value is valid for a `MaybeUninit<T>` the compiler can't apply non-zero/niche-filling
+ /// optimizations, potentially resulting in a larger size:
+ ///
+ /// ```rust
+ /// # use std::mem::{MaybeUninit, size_of};
+ /// assert_eq!(size_of::<Option<bool>>(), 1);
+ /// assert_eq!(size_of::<Option<MaybeUninit<bool>>>(), 2);
+ /// ```
+ ///
+ /// If `T` is FFI-safe, then so is `MaybeUninit<T>`.
+ ///
+ /// While `MaybeUninit` is `#[repr(transparent)]` (indicating it guarantees the same size,
+ /// alignment, and ABI as `T`), this does *not* change any of the previous caveats. `Option<T>` and
+ /// `Option<MaybeUninit<T>>` may still have different sizes, and types containing a field of type
+ /// `T` may be laid out (and sized) differently than if that field were `MaybeUninit<T>`.
+ /// `MaybeUninit` is a union type, and `#[repr(transparent)]` on unions is unstable (see [the
+ /// tracking issue](https://github.com/rust-lang/rust/issues/60405)). Over time, the exact
+ /// guarantees of `#[repr(transparent)]` on unions may evolve, and `MaybeUninit` may or may not
+ /// remain `#[repr(transparent)]`. That said, `MaybeUninit<T>` will *always* guarantee that it has
+ /// the same size, alignment, and ABI as `T`; it's just that the way `MaybeUninit` implements that
+ /// guarantee may evolve.
+ #[stable(feature = "maybe_uninit", since = "1.36.0")]
+ // Lang item so we can wrap other types in it. This is useful for generators.
+ #[lang = "maybe_uninit"]
+ #[derive(Copy)]
+ #[repr(transparent)]
+ pub union MaybeUninit<T> {
+     uninit: (),
+     value: ManuallyDrop<T>,
+ }
+ 
+ #[stable(feature = "maybe_uninit", since = "1.36.0")]
+ impl<T: Copy> Clone for MaybeUninit<T> {
+     #[inline(always)]
+     fn clone(&self) -> Self {
+         // Not calling `T::clone()`, we cannot know if we are initialized enough for that.
+         *self
+     }
+ }
+ 
+ #[stable(feature = "maybe_uninit_debug", since = "1.41.0")]
+ impl<T> fmt::Debug for MaybeUninit<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad(type_name::<Self>())
+     }
+ }
+ 
+ impl<T> MaybeUninit<T> {
+     /// Creates a new `MaybeUninit<T>` initialized with the given value.
+     /// It is safe to call [`assume_init`] on the return value of this function.
+     ///
+     /// Note that dropping a `MaybeUninit<T>` will never call `T`'s drop code.
+     /// It is your responsibility to make sure `T` gets dropped if it got initialized.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let v: MaybeUninit<Vec<u8>> = MaybeUninit::new(vec![42]);
+     /// ```
+     ///
+     /// [`assume_init`]: MaybeUninit::assume_init
+     #[stable(feature = "maybe_uninit", since = "1.36.0")]
+     #[rustc_const_stable(feature = "const_maybe_uninit", since = "1.36.0")]
+     #[inline(always)]
+     pub const fn new(val: T) -> MaybeUninit<T> {
+         MaybeUninit { value: ManuallyDrop::new(val) }
+     }
+ 
+     /// Creates a new `MaybeUninit<T>` in an uninitialized state.
+     ///
+     /// Note that dropping a `MaybeUninit<T>` will never call `T`'s drop code.
+     /// It is your responsibility to make sure `T` gets dropped if it got initialized.
+     ///
+     /// See the [type-level documentation][MaybeUninit] for some examples.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let v: MaybeUninit<String> = MaybeUninit::uninit();
+     /// ```
+     #[stable(feature = "maybe_uninit", since = "1.36.0")]
+     #[rustc_const_stable(feature = "const_maybe_uninit", since = "1.36.0")]
+     #[inline(always)]
+     #[rustc_diagnostic_item = "maybe_uninit_uninit"]
+     pub const fn uninit() -> MaybeUninit<T> {
+         MaybeUninit { uninit: () }
+     }
+ 
+     /// Create a new array of `MaybeUninit<T>` items, in an uninitialized state.
+     ///
+     /// Note: in a future Rust version this method may become unnecessary
+     /// when array literal syntax allows
+     /// [repeating const expressions](https://github.com/rust-lang/rust/issues/49147).
+     /// The example below could then use `let mut buf = [MaybeUninit::<u8>::uninit(); 32];`.
+     ///
+     /// # Examples
+     ///
+     /// ```no_run
+     /// #![feature(maybe_uninit_uninit_array, maybe_uninit_extra, maybe_uninit_slice)]
+     ///
+     /// use std::mem::MaybeUninit;
+     ///
+     /// extern "C" {
+     ///     fn read_into_buffer(ptr: *mut u8, max_len: usize) -> usize;
+     /// }
+     ///
+     /// /// Returns a (possibly smaller) slice of data that was actually read
+     /// fn read(buf: &mut [MaybeUninit<u8>]) -> &[u8] {
+     ///     unsafe {
+     ///         let len = read_into_buffer(buf.as_mut_ptr() as *mut u8, buf.len());
+     ///         MaybeUninit::slice_assume_init_ref(&buf[..len])
+     ///     }
+     /// }
+     ///
+     /// let mut buf: [MaybeUninit<u8>; 32] = MaybeUninit::uninit_array();
+     /// let data = read(&mut buf);
+     /// ```
+     #[unstable(feature = "maybe_uninit_uninit_array", issue = "none")]
+     #[inline(always)]
+     pub fn uninit_array<const LEN: usize>() -> [Self; LEN] {
+         // SAFETY: An uninitialized `[MaybeUninit<_>; LEN]` is valid.
+         unsafe { MaybeUninit::<[MaybeUninit<T>; LEN]>::uninit().assume_init() }
+     }
+ 
+     /// Creates a new `MaybeUninit<T>` in an uninitialized state, with the memory being
+     /// filled with `0` bytes. It depends on `T` whether that already makes for
+     /// proper initialization. For example, `MaybeUninit<usize>::zeroed()` is initialized,
+     /// but `MaybeUninit<&'static i32>::zeroed()` is not because references must not
+     /// be null.
+     ///
+     /// Note that dropping a `MaybeUninit<T>` will never call `T`'s drop code.
+     /// It is your responsibility to make sure `T` gets dropped if it got initialized.
+     ///
+     /// # Example
+     ///
+     /// Correct usage of this function: initializing a struct with zero, where all
+     /// fields of the struct can hold the bit-pattern 0 as a valid value.
+     ///
+     /// ```rust
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let x = MaybeUninit::<(u8, bool)>::zeroed();
+     /// let x = unsafe { x.assume_init() };
+     /// assert_eq!(x, (0, false));
+     /// ```
+     ///
+     /// *Incorrect* usage of this function: calling `x.zeroed().assume_init()`
+     /// when `0` is not a valid bit-pattern for the type:
+     ///
+     /// ```rust,no_run
+     /// use std::mem::MaybeUninit;
+     ///
+     /// enum NotZero { One = 1, Two = 2 };
+     ///
+     /// let x = MaybeUninit::<(u8, NotZero)>::zeroed();
+     /// let x = unsafe { x.assume_init() };
+     /// // Inside a pair, we create a `NotZero` that does not have a valid discriminant.
+     /// // This is undefined behavior. ⚠️
+     /// ```
+     #[stable(feature = "maybe_uninit", since = "1.36.0")]
+     #[inline]
+     #[rustc_diagnostic_item = "maybe_uninit_zeroed"]
+     pub fn zeroed() -> MaybeUninit<T> {
+         let mut u = MaybeUninit::<T>::uninit();
+         // SAFETY: `u.as_mut_ptr()` points to allocated memory.
+         unsafe {
+             u.as_mut_ptr().write_bytes(0u8, 1);
+         }
+         u
+     }
+ 
+     /// Sets the value of the `MaybeUninit<T>`. This overwrites any previous value
+     /// without dropping it, so be careful not to use this twice unless you want to
+     /// skip running the destructor. For your convenience, this also returns a mutable
+     /// reference to the (now safely initialized) contents of `self`.
+     #[unstable(feature = "maybe_uninit_extra", issue = "63567")]
+     #[inline(always)]
+     pub fn write(&mut self, val: T) -> &mut T {
+         *self = MaybeUninit::new(val);
+         // SAFETY: We just initialized this value.
+         unsafe { self.assume_init_mut() }
+     }
+ 
+     /// Gets a pointer to the contained value. Reading from this pointer or turning it
+     /// into a reference is undefined behavior unless the `MaybeUninit<T>` is initialized.
+     /// Writing to memory that this pointer (non-transitively) points to is undefined behavior
+     /// (except inside an `UnsafeCell<T>`).
+     ///
+     /// # Examples
+     ///
+     /// Correct usage of this method:
+     ///
+     /// ```rust
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<Vec<u32>>::uninit();
+     /// unsafe { x.as_mut_ptr().write(vec![0,1,2]); }
+     /// // Create a reference into the `MaybeUninit<T>`. This is okay because we initialized it.
+     /// let x_vec = unsafe { &*x.as_ptr() };
+     /// assert_eq!(x_vec.len(), 3);
+     /// ```
+     ///
+     /// *Incorrect* usage of this method:
+     ///
+     /// ```rust,no_run
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let x = MaybeUninit::<Vec<u32>>::uninit();
+     /// let x_vec = unsafe { &*x.as_ptr() };
+     /// // We have created a reference to an uninitialized vector! This is undefined behavior. ⚠️
+     /// ```
+     ///
+     /// (Notice that the rules around references to uninitialized data are not finalized yet, but
+     /// until they are, it is advisable to avoid them.)
+     #[stable(feature = "maybe_uninit", since = "1.36.0")]
+     #[rustc_const_unstable(feature = "const_maybe_uninit_as_ptr", issue = "75251")]
+     #[inline(always)]
+     pub const fn as_ptr(&self) -> *const T {
+         // `MaybeUninit` and `ManuallyDrop` are both `repr(transparent)` so we can cast the pointer.
+         self as *const _ as *const T
+     }
+ 
+     /// Gets a mutable pointer to the contained value. Reading from this pointer or turning it
+     /// into a reference is undefined behavior unless the `MaybeUninit<T>` is initialized.
+     ///
+     /// # Examples
+     ///
+     /// Correct usage of this method:
+     ///
+     /// ```rust
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<Vec<u32>>::uninit();
+     /// unsafe { x.as_mut_ptr().write(vec![0,1,2]); }
+     /// // Create a reference into the `MaybeUninit<Vec<u32>>`.
+     /// // This is okay because we initialized it.
+     /// let x_vec = unsafe { &mut *x.as_mut_ptr() };
+     /// x_vec.push(3);
+     /// assert_eq!(x_vec.len(), 4);
+     /// ```
+     ///
+     /// *Incorrect* usage of this method:
+     ///
+     /// ```rust,no_run
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<Vec<u32>>::uninit();
+     /// let x_vec = unsafe { &mut *x.as_mut_ptr() };
+     /// // We have created a reference to an uninitialized vector! This is undefined behavior. ⚠️
+     /// ```
+     ///
+     /// (Notice that the rules around references to uninitialized data are not finalized yet, but
+     /// until they are, it is advisable to avoid them.)
+     #[stable(feature = "maybe_uninit", since = "1.36.0")]
+     #[rustc_const_unstable(feature = "const_maybe_uninit_as_ptr", issue = "75251")]
+     #[inline(always)]
+     pub const fn as_mut_ptr(&mut self) -> *mut T {
+         // `MaybeUninit` and `ManuallyDrop` are both `repr(transparent)` so we can cast the pointer.
+         self as *mut _ as *mut T
+     }
+ 
+     /// Extracts the value from the `MaybeUninit<T>` container. This is a great way
+     /// to ensure that the data will get dropped, because the resulting `T` is
+     /// subject to the usual drop handling.
+     ///
+     /// # Safety
+     ///
+     /// It is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized
+     /// state. Calling this when the content is not yet fully initialized causes immediate undefined
+     /// behavior. The [type-level documentation][inv] contains more information about
+     /// this initialization invariant.
+     ///
+     /// [inv]: #initialization-invariant
+     ///
+     /// On top of that, remember that most types have additional invariants beyond merely
+     /// being considered initialized at the type level. For example, a `1`-initialized [`Vec<T>`]
+     /// is considered initialized (under the current implementation; this does not constitute
+     /// a stable guarantee) because the only requirement the compiler knows about it
+     /// is that the data pointer must be non-null. Creating such a `Vec<T>` does not cause
+     /// *immediate* undefined behavior, but will cause undefined behavior with most
+     /// safe operations (including dropping it).
+     ///
+     /// [`Vec<T>`]: ../../std/vec/struct.Vec.html
+     ///
+     /// # Examples
+     ///
+     /// Correct usage of this method:
+     ///
+     /// ```rust
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<bool>::uninit();
+     /// unsafe { x.as_mut_ptr().write(true); }
+     /// let x_init = unsafe { x.assume_init() };
+     /// assert_eq!(x_init, true);
+     /// ```
+     ///
+     /// *Incorrect* usage of this method:
+     ///
+     /// ```rust,no_run
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let x = MaybeUninit::<Vec<u32>>::uninit();
+     /// let x_init = unsafe { x.assume_init() };
+     /// // `x` had not been initialized yet, so this last line caused undefined behavior. ⚠️
+     /// ```
+     #[stable(feature = "maybe_uninit", since = "1.36.0")]
+     #[inline(always)]
+     #[rustc_diagnostic_item = "assume_init"]
+     pub unsafe fn assume_init(self) -> T {
+         // SAFETY: the caller must guarantee that `self` is initialized.
+         // This also means that `self` must be a `value` variant.
+         unsafe {
+             intrinsics::assert_inhabited::<T>();
+             ManuallyDrop::into_inner(self.value)
+         }
+     }
+ 
+     /// Reads the value from the `MaybeUninit<T>` container. The resulting `T` is subject
+     /// to the usual drop handling.
+     ///
+     /// Whenever possible, it is preferable to use [`assume_init`] instead, which
+     /// prevents duplicating the content of the `MaybeUninit<T>`.
+     ///
+     /// # Safety
+     ///
+     /// It is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized
+     /// state. Calling this when the content is not yet fully initialized causes undefined
+     /// behavior. The [type-level documentation][inv] contains more information about
+     /// this initialization invariant.
+     ///
+     /// Moreover, this leaves a copy of the same data behind in the `MaybeUninit<T>`. When using
+     /// multiple copies of the data (by calling `assume_init_read` multiple times, or first
+     /// calling `assume_init_read` and then [`assume_init`]), it is your responsibility
+     /// to ensure that that data may indeed be duplicated.
+     ///
+     /// [inv]: #initialization-invariant
+     /// [`assume_init`]: MaybeUninit::assume_init
+     ///
+     /// # Examples
+     ///
+     /// Correct usage of this method:
+     ///
+     /// ```rust
+     /// #![feature(maybe_uninit_extra)]
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<u32>::uninit();
+     /// x.write(13);
+     /// let x1 = unsafe { x.assume_init_read() };
+     /// // `u32` is `Copy`, so we may read multiple times.
+     /// let x2 = unsafe { x.assume_init_read() };
+     /// assert_eq!(x1, x2);
+     ///
+     /// let mut x = MaybeUninit::<Option<Vec<u32>>>::uninit();
+     /// x.write(None);
+     /// let x1 = unsafe { x.assume_init_read() };
+     /// // Duplicating a `None` value is okay, so we may read multiple times.
+     /// let x2 = unsafe { x.assume_init_read() };
+     /// assert_eq!(x1, x2);
+     /// ```
+     ///
+     /// *Incorrect* usage of this method:
+     ///
+     /// ```rust,no_run
+     /// #![feature(maybe_uninit_extra)]
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<Option<Vec<u32>>>::uninit();
+     /// x.write(Some(vec![0,1,2]));
+     /// let x1 = unsafe { x.assume_init_read() };
+     /// let x2 = unsafe { x.assume_init_read() };
+     /// // We now created two copies of the same vector, leading to a double-free ⚠️ when
+     /// // they both get dropped!
+     /// ```
+     #[unstable(feature = "maybe_uninit_extra", issue = "63567")]
+     #[inline(always)]
+     pub unsafe fn assume_init_read(&self) -> T {
+         // SAFETY: the caller must guarantee that `self` is initialized.
+         // Reading from `self.as_ptr()` is safe since `self` should be initialized.
+         unsafe {
+             intrinsics::assert_inhabited::<T>();
+             self.as_ptr().read()
+         }
+     }
+ 
+     /// Drops the contained value in place.
+     ///
+     /// If you have ownership of the `MaybeUninit`, you can use [`assume_init`] instead.
+     ///
+     /// # Safety
+     ///
+     /// It is up to the caller to guarantee that the `MaybeUninit<T>` really is
+     /// in an initialized state. Calling this when the content is not yet fully
+     /// initialized causes undefined behavior.
+     ///
+     /// On top of that, all additional invariants of the type `T` must be
+     /// satisfied, as the `Drop` implementation of `T` (or its members) may
+     /// rely on this. For example, a `1`-initialized [`Vec<T>`] is considered
+     /// initialized (under the current implementation; this does not constitute
+     /// a stable guarantee) because the only requirement the compiler knows
+     /// about it is that the data pointer must be non-null. Dropping such a
+     /// `Vec<T>` however will cause undefined behaviour.
+     ///
+     /// [`assume_init`]: MaybeUninit::assume_init
+     /// [`Vec<T>`]: ../../std/vec/struct.Vec.html
+     #[unstable(feature = "maybe_uninit_extra", issue = "63567")]
+     pub unsafe fn assume_init_drop(&mut self) {
+         // SAFETY: the caller must guarantee that `self` is initialized and
+         // satisfies all invariants of `T`.
+         // Dropping the value in place is safe if that is the case.
+         unsafe { ptr::drop_in_place(self.as_mut_ptr()) }
+     }
+ 
+     /// Gets a shared reference to the contained value.
+     ///
+     /// This can be useful when we want to access a `MaybeUninit` that has been
+     /// initialized but don't have ownership of the `MaybeUninit` (preventing the use
+     /// of `.assume_init()`).
+     ///
+     /// # Safety
+     ///
+     /// Calling this when the content is not yet fully initialized causes undefined
+     /// behavior: it is up to the caller to guarantee that the `MaybeUninit<T>` really
+     /// is in an initialized state.
+     ///
+     /// # Examples
+     ///
+     /// ### Correct usage of this method:
+     ///
+     /// ```rust
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut x = MaybeUninit::<Vec<u32>>::uninit();
+     /// // Initialize `x`:
+     /// unsafe { x.as_mut_ptr().write(vec![1, 2, 3]); }
+     /// // Now that our `MaybeUninit<_>` is known to be initialized, it is okay to
+     /// // create a shared reference to it:
+     /// let x: &Vec<u32> = unsafe {
+     ///     // SAFETY: `x` has been initialized.
+     ///     x.assume_init_ref()
+     /// };
+     /// assert_eq!(x, &vec![1, 2, 3]);
+     /// ```
+     ///
+     /// ### *Incorrect* usages of this method:
+     ///
+     /// ```rust,no_run
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let x = MaybeUninit::<Vec<u32>>::uninit();
+     /// let x_vec: &Vec<u32> = unsafe { x.assume_init_ref() };
+     /// // We have created a reference to an uninitialized vector! This is undefined behavior. ⚠️
+     /// ```
+     ///
+     /// ```rust,no_run
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::{cell::Cell, mem::MaybeUninit};
+     ///
+     /// let b = MaybeUninit::<Cell<bool>>::uninit();
+     /// // Initialize the `MaybeUninit` using `Cell::set`:
+     /// unsafe {
+     ///     b.assume_init_ref().set(true);
+     ///    // ^^^^^^^^^^^^^^^
+     ///    // Reference to an uninitialized `Cell<bool>`: UB!
+     /// }
+     /// ```
+     #[unstable(feature = "maybe_uninit_ref", issue = "63568")]
+     #[inline(always)]
+     pub unsafe fn assume_init_ref(&self) -> &T {
+         // SAFETY: the caller must guarantee that `self` is initialized.
+         // This also means that `self` must be a `value` variant.
+         unsafe {
+             intrinsics::assert_inhabited::<T>();
+             &*self.value
+         }
+     }
+ 
+     /// Gets a mutable (unique) reference to the contained value.
+     ///
+     /// This can be useful when we want to access a `MaybeUninit` that has been
+     /// initialized but don't have ownership of the `MaybeUninit` (preventing the use
+     /// of `.assume_init()`).
+     ///
+     /// # Safety
+     ///
+     /// Calling this when the content is not yet fully initialized causes undefined
+     /// behavior: it is up to the caller to guarantee that the `MaybeUninit<T>` really
+     /// is in an initialized state. For instance, `.assume_init_mut()` cannot be used to
+     /// initialize a `MaybeUninit`.
+     ///
+     /// # Examples
+     ///
+     /// ### Correct usage of this method:
+     ///
+     /// ```rust
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::mem::MaybeUninit;
+     ///
+     /// # unsafe extern "C" fn initialize_buffer(buf: *mut [u8; 2048]) { *buf = [0; 2048] }
+     /// # #[cfg(FALSE)]
+     /// extern "C" {
+     ///     /// Initializes *all* the bytes of the input buffer.
+     ///     fn initialize_buffer(buf: *mut [u8; 2048]);
+     /// }
+     ///
+     /// let mut buf = MaybeUninit::<[u8; 2048]>::uninit();
+     ///
+     /// // Initialize `buf`:
+     /// unsafe { initialize_buffer(buf.as_mut_ptr()); }
+     /// // Now we know that `buf` has been initialized, so we could `.assume_init()` it.
+     /// // However, using `.assume_init()` may trigger a `memcpy` of the 2048 bytes.
+     /// // To assert our buffer has been initialized without copying it, we upgrade
+     /// // the `&mut MaybeUninit<[u8; 2048]>` to a `&mut [u8; 2048]`:
+     /// let buf: &mut [u8; 2048] = unsafe {
+     ///     // SAFETY: `buf` has been initialized.
+     ///     buf.assume_init_mut()
+     /// };
+     ///
+     /// // Now we can use `buf` as a normal slice:
+     /// buf.sort_unstable();
+     /// assert!(
+     ///     buf.windows(2).all(|pair| pair[0] <= pair[1]),
+     ///     "buffer is sorted",
+     /// );
+     /// ```
+     ///
+     /// ### *Incorrect* usages of this method:
+     ///
+     /// You cannot use `.assume_init_mut()` to initialize a value:
+     ///
+     /// ```rust,no_run
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::mem::MaybeUninit;
+     ///
+     /// let mut b = MaybeUninit::<bool>::uninit();
+     /// unsafe {
+     ///     *b.assume_init_mut() = true;
+     ///     // We have created a (mutable) reference to an uninitialized `bool`!
+     ///     // This is undefined behavior. ⚠️
+     /// }
+     /// ```
+     ///
+     /// For instance, you cannot [`Read`] into an uninitialized buffer:
+     ///
+     /// [`Read`]: https://doc.rust-lang.org/std/io/trait.Read.html
+     ///
+     /// ```rust,no_run
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::{io, mem::MaybeUninit};
+     ///
+     /// fn read_chunk (reader: &'_ mut dyn io::Read) -> io::Result<[u8; 64]>
+     /// {
+     ///     let mut buffer = MaybeUninit::<[u8; 64]>::uninit();
+     ///     reader.read_exact(unsafe { buffer.assume_init_mut() })?;
+     ///                             // ^^^^^^^^^^^^^^^^^^^^^^^^
+     ///                             // (mutable) reference to uninitialized memory!
+     ///                             // This is undefined behavior.
+     ///     Ok(unsafe { buffer.assume_init() })
+     /// }
+     /// ```
+     ///
+     /// Nor can you use direct field access to do field-by-field gradual initialization:
+     ///
+     /// ```rust,no_run
+     /// #![feature(maybe_uninit_ref)]
+     /// use std::{mem::MaybeUninit, ptr};
+     ///
+     /// struct Foo {
+     ///     a: u32,
+     ///     b: u8,
+     /// }
+     ///
+     /// let foo: Foo = unsafe {
+     ///     let mut foo = MaybeUninit::<Foo>::uninit();
+     ///     ptr::write(&mut foo.assume_init_mut().a as *mut u32, 1337);
+     ///                  // ^^^^^^^^^^^^^^^^^^^^^
+     ///                  // (mutable) reference to uninitialized memory!
+     ///                  // This is undefined behavior.
+     ///     ptr::write(&mut foo.assume_init_mut().b as *mut u8, 42);
+     ///                  // ^^^^^^^^^^^^^^^^^^^^^
+     ///                  // (mutable) reference to uninitialized memory!
+     ///                  // This is undefined behavior.
+     ///     foo.assume_init()
+     /// };
+     /// ```
+     // FIXME(#76092): We currently rely on the above being incorrect, i.e., we have references
+     // to uninitialized data (e.g., in `libcore/fmt/float.rs`).  We should make
+     // a final decision about the rules before stabilization.
+     #[unstable(feature = "maybe_uninit_ref", issue = "63568")]
+     #[inline(always)]
+     pub unsafe fn assume_init_mut(&mut self) -> &mut T {
+         // SAFETY: the caller must guarantee that `self` is initialized.
+         // This also means that `self` must be a `value` variant.
+         unsafe {
+             intrinsics::assert_inhabited::<T>();
+             &mut *self.value
+         }
+     }
+ 
+     /// Assuming all the elements are initialized, get a slice to them.
+     ///
+     /// # Safety
+     ///
+     /// It is up to the caller to guarantee that the `MaybeUninit<T>` elements
+     /// really are in an initialized state.
+     /// Calling this when the content is not yet fully initialized causes undefined behavior.
+     ///
+     /// See [`assume_init_ref`] for more details and examples.
+     ///
+     /// [`assume_init_ref`]: MaybeUninit::assume_init_ref
+     #[unstable(feature = "maybe_uninit_slice", issue = "63569")]
+     #[inline(always)]
+     pub unsafe fn slice_assume_init_ref(slice: &[Self]) -> &[T] {
+         // SAFETY: casting slice to a `*const [T]` is safe since the caller guarantees that
+         // `slice` is initialized, and`MaybeUninit` is guaranteed to have the same layout as `T`.
+         // The pointer obtained is valid since it refers to memory owned by `slice` which is a
+         // reference and thus guaranteed to be valid for reads.
+         unsafe { &*(slice as *const [Self] as *const [T]) }
+     }
+ 
+     /// Assuming all the elements are initialized, get a mutable slice to them.
+     ///
+     /// # Safety
+     ///
+     /// It is up to the caller to guarantee that the `MaybeUninit<T>` elements
+     /// really are in an initialized state.
+     /// Calling this when the content is not yet fully initialized causes undefined behavior.
+     ///
+     /// See [`assume_init_mut`] for more details and examples.
+     ///
+     /// [`assume_init_mut`]: MaybeUninit::assume_init_mut
+     #[unstable(feature = "maybe_uninit_slice", issue = "63569")]
+     #[inline(always)]
+     pub unsafe fn slice_assume_init_mut(slice: &mut [Self]) -> &mut [T] {
+         // SAFETY: similar to safety notes for `slice_get_ref`, but we have a
+         // mutable reference which is also guaranteed to be valid for writes.
+         unsafe { &mut *(slice as *mut [Self] as *mut [T]) }
+     }
+ 
+     /// Gets a pointer to the first element of the array.
+     #[unstable(feature = "maybe_uninit_slice", issue = "63569")]
+     #[inline(always)]
+     pub fn slice_as_ptr(this: &[MaybeUninit<T>]) -> *const T {
+         this.as_ptr() as *const T
+     }
+ 
+     /// Gets a mutable pointer to the first element of the array.
+     #[unstable(feature = "maybe_uninit_slice", issue = "63569")]
+     #[inline(always)]
+     pub fn slice_as_mut_ptr(this: &mut [MaybeUninit<T>]) -> *mut T {
+         this.as_mut_ptr() as *mut T
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/mem/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/mem/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/mem/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/mem/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1040 ----
+ //! Basic functions for dealing with memory.
+ //!
+ //! This module contains functions for querying the size and alignment of
+ //! types, initializing and manipulating memory.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::clone;
+ use crate::cmp;
+ use crate::fmt;
+ use crate::hash;
+ use crate::intrinsics;
+ use crate::marker::{Copy, DiscriminantKind, Sized};
+ use crate::ptr;
+ 
+ mod manually_drop;
+ #[stable(feature = "manually_drop", since = "1.20.0")]
+ pub use manually_drop::ManuallyDrop;
+ 
+ mod maybe_uninit;
+ #[stable(feature = "maybe_uninit", since = "1.36.0")]
+ pub use maybe_uninit::MaybeUninit;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(inline)]
+ pub use crate::intrinsics::transmute;
+ 
+ /// Takes ownership and "forgets" about the value **without running its destructor**.
+ ///
+ /// Any resources the value manages, such as heap memory or a file handle, will linger
+ /// forever in an unreachable state. However, it does not guarantee that pointers
+ /// to this memory will remain valid.
+ ///
+ /// * If you want to leak memory, see [`Box::leak`].
+ /// * If you want to obtain a raw pointer to the memory, see [`Box::into_raw`].
+ /// * If you want to dispose of a value properly, running its destructor, see
+ /// [`mem::drop`].
+ ///
+ /// # Safety
+ ///
+ /// `forget` is not marked as `unsafe`, because Rust's safety guarantees
+ /// do not include a guarantee that destructors will always run. For example,
+ /// a program can create a reference cycle using [`Rc`][rc], or call
+ /// [`process::exit`][exit] to exit without running destructors. Thus, allowing
+ /// `mem::forget` from safe code does not fundamentally change Rust's safety
+ /// guarantees.
+ ///
+ /// That said, leaking resources such as memory or I/O objects is usually undesirable.
+ /// The need comes up in some specialized use cases for FFI or unsafe code, but even
+ /// then, [`ManuallyDrop`] is typically preferred.
+ ///
+ /// Because forgetting a value is allowed, any `unsafe` code you write must
+ /// allow for this possibility. You cannot return a value and expect that the
+ /// caller will necessarily run the value's destructor.
+ ///
+ /// [rc]: ../../std/rc/struct.Rc.html
+ /// [exit]: ../../std/process/fn.exit.html
+ ///
+ /// # Examples
+ ///
+ /// The canonical safe use of `mem::forget` is to circumvent a value's destructor
+ /// implemented by the `Drop` trait. For example, this will leak a `File`, i.e. reclaim
+ /// the space taken by the variable but never close the underlying system resource:
+ ///
+ /// ```no_run
+ /// use std::mem;
+ /// use std::fs::File;
+ ///
+ /// let file = File::open("foo.txt").unwrap();
+ /// mem::forget(file);
+ /// ```
+ ///
+ /// This is useful when the ownership of the underlying resource was previously
+ /// transferred to code outside of Rust, for example by transmitting the raw
+ /// file descriptor to C code.
+ ///
+ /// # Relationship with `ManuallyDrop`
+ ///
+ /// While `mem::forget` can also be used to transfer *memory* ownership, doing so is error-prone.
+ /// [`ManuallyDrop`] should be used instead. Consider, for example, this code:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// let mut v = vec![65, 122];
+ /// // Build a `String` using the contents of `v`
+ /// let s = unsafe { String::from_raw_parts(v.as_mut_ptr(), v.len(), v.capacity()) };
+ /// // leak `v` because its memory is now managed by `s`
+ /// mem::forget(v);  // ERROR - v is invalid and must not be passed to a function
+ /// assert_eq!(s, "Az");
+ /// // `s` is implicitly dropped and its memory deallocated.
+ /// ```
+ ///
+ /// There are two issues with the above example:
+ ///
+ /// * If more code were added between the construction of `String` and the invocation of
+ ///   `mem::forget()`, a panic within it would cause a double free because the same memory
+ ///   is handled by both `v` and `s`.
+ /// * After calling `v.as_mut_ptr()` and transmitting the ownership of the data to `s`,
+ ///   the `v` value is invalid. Even when a value is just moved to `mem::forget` (which won't
+ ///   inspect it), some types have strict requirements on their values that
+ ///   make them invalid when dangling or no longer owned. Using invalid values in any
+ ///   way, including passing them to or returning them from functions, constitutes
+ ///   undefined behavior and may break the assumptions made by the compiler.
+ ///
+ /// Switching to `ManuallyDrop` avoids both issues:
+ ///
+ /// ```
+ /// use std::mem::ManuallyDrop;
+ ///
+ /// let v = vec![65, 122];
+ /// // Before we disassemble `v` into its raw parts, make sure it
+ /// // does not get dropped!
+ /// let mut v = ManuallyDrop::new(v);
+ /// // Now disassemble `v`. These operations cannot panic, so there cannot be a leak.
+ /// let (ptr, len, cap) = (v.as_mut_ptr(), v.len(), v.capacity());
+ /// // Finally, build a `String`.
+ /// let s = unsafe { String::from_raw_parts(ptr, len, cap) };
+ /// assert_eq!(s, "Az");
+ /// // `s` is implicitly dropped and its memory deallocated.
+ /// ```
+ ///
+ /// `ManuallyDrop` robustly prevents double-free because we disable `v`'s destructor
+ /// before doing anything else. `mem::forget()` doesn't allow this because it consumes its
+ /// argument, forcing us to call it only after extracting anything we need from `v`. Even
+ /// if a panic were introduced between construction of `ManuallyDrop` and building the
+ /// string (which cannot happen in the code as shown), it would result in a leak and not a
+ /// double free. In other words, `ManuallyDrop` errs on the side of leaking instead of
+ /// erring on the side of (double-)dropping.
+ ///
+ /// Also, `ManuallyDrop` prevents us from having to "touch" `v` after transferring the
+ /// ownership to `s` — the final step of interacting with `v` to dispose of it without
+ /// running its destructor is entirely avoided.
+ ///
+ /// [`Box`]: ../../std/boxed/struct.Box.html
+ /// [`Box::leak`]: ../../std/boxed/struct.Box.html#method.leak
+ /// [`Box::into_raw`]: ../../std/boxed/struct.Box.html#method.into_raw
+ /// [`mem::drop`]: drop
+ /// [ub]: ../../reference/behavior-considered-undefined.html
+ #[inline]
+ #[rustc_const_stable(feature = "const_forget", since = "1.46.0")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const fn forget<T>(t: T) {
+     let _ = ManuallyDrop::new(t);
+ }
+ 
+ /// Like [`forget`], but also accepts unsized values.
+ ///
+ /// This function is just a shim intended to be removed when the `unsized_locals` feature gets
+ /// stabilized.
+ #[inline]
+ #[unstable(feature = "forget_unsized", issue = "none")]
+ pub fn forget_unsized<T: ?Sized>(t: T) {
+     // SAFETY: the forget intrinsic could be safe, but there's no point in making it safe since
+     // we'll be implementing this function soon via `ManuallyDrop`
+     unsafe { intrinsics::forget(t) }
+ }
+ 
+ /// Returns the size of a type in bytes.
+ ///
+ /// More specifically, this is the offset in bytes between successive elements
+ /// in an array with that item type including alignment padding. Thus, for any
+ /// type `T` and length `n`, `[T; n]` has a size of `n * size_of::<T>()`.
+ ///
+ /// In general, the size of a type is not stable across compilations, but
+ /// specific types such as primitives are.
+ ///
+ /// The following table gives the size for primitives.
+ ///
+ /// Type | size_of::\<Type>()
+ /// ---- | ---------------
+ /// () | 0
+ /// bool | 1
+ /// u8 | 1
+ /// u16 | 2
+ /// u32 | 4
+ /// u64 | 8
+ /// u128 | 16
+ /// i8 | 1
+ /// i16 | 2
+ /// i32 | 4
+ /// i64 | 8
+ /// i128 | 16
+ /// f32 | 4
+ /// f64 | 8
+ /// char | 4
+ ///
+ /// Furthermore, `usize` and `isize` have the same size.
+ ///
+ /// The types `*const T`, `&T`, `Box<T>`, `Option<&T>`, and `Option<Box<T>>` all have
+ /// the same size. If `T` is Sized, all of those types have the same size as `usize`.
+ ///
+ /// The mutability of a pointer does not change its size. As such, `&T` and `&mut T`
+ /// have the same size. Likewise for `*const T` and `*mut T`.
+ ///
+ /// # Size of `#[repr(C)]` items
+ ///
+ /// The `C` representation for items has a defined layout. With this layout,
+ /// the size of items is also stable as long as all fields have a stable size.
+ ///
+ /// ## Size of Structs
+ ///
+ /// For `structs`, the size is determined by the following algorithm.
+ ///
+ /// For each field in the struct ordered by declaration order:
+ ///
+ /// 1. Add the size of the field.
+ /// 2. Round up the current size to the nearest multiple of the next field's [alignment].
+ ///
+ /// Finally, round the size of the struct to the nearest multiple of its [alignment].
+ /// The alignment of the struct is usually the largest alignment of all its
+ /// fields; this can be changed with the use of `repr(align(N))`.
+ ///
+ /// Unlike `C`, zero sized structs are not rounded up to one byte in size.
+ ///
+ /// ## Size of Enums
+ ///
+ /// Enums that carry no data other than the discriminant have the same size as C enums
+ /// on the platform they are compiled for.
+ ///
+ /// ## Size of Unions
+ ///
+ /// The size of a union is the size of its largest field.
+ ///
+ /// Unlike `C`, zero sized unions are not rounded up to one byte in size.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// // Some primitives
+ /// assert_eq!(4, mem::size_of::<i32>());
+ /// assert_eq!(8, mem::size_of::<f64>());
+ /// assert_eq!(0, mem::size_of::<()>());
+ ///
+ /// // Some arrays
+ /// assert_eq!(8, mem::size_of::<[i32; 2]>());
+ /// assert_eq!(12, mem::size_of::<[i32; 3]>());
+ /// assert_eq!(0, mem::size_of::<[i32; 0]>());
+ ///
+ ///
+ /// // Pointer size equality
+ /// assert_eq!(mem::size_of::<&i32>(), mem::size_of::<*const i32>());
+ /// assert_eq!(mem::size_of::<&i32>(), mem::size_of::<Box<i32>>());
+ /// assert_eq!(mem::size_of::<&i32>(), mem::size_of::<Option<&i32>>());
+ /// assert_eq!(mem::size_of::<Box<i32>>(), mem::size_of::<Option<Box<i32>>>());
+ /// ```
+ ///
+ /// Using `#[repr(C)]`.
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// #[repr(C)]
+ /// struct FieldStruct {
+ ///     first: u8,
+ ///     second: u16,
+ ///     third: u8
+ /// }
+ ///
+ /// // The size of the first field is 1, so add 1 to the size. Size is 1.
+ /// // The alignment of the second field is 2, so add 1 to the size for padding. Size is 2.
+ /// // The size of the second field is 2, so add 2 to the size. Size is 4.
+ /// // The alignment of the third field is 1, so add 0 to the size for padding. Size is 4.
+ /// // The size of the third field is 1, so add 1 to the size. Size is 5.
+ /// // Finally, the alignment of the struct is 2 (because the largest alignment amongst its
+ /// // fields is 2), so add 1 to the size for padding. Size is 6.
+ /// assert_eq!(6, mem::size_of::<FieldStruct>());
+ ///
+ /// #[repr(C)]
+ /// struct TupleStruct(u8, u16, u8);
+ ///
+ /// // Tuple structs follow the same rules.
+ /// assert_eq!(6, mem::size_of::<TupleStruct>());
+ ///
+ /// // Note that reordering the fields can lower the size. We can remove both padding bytes
+ /// // by putting `third` before `second`.
+ /// #[repr(C)]
+ /// struct FieldStructOptimized {
+ ///     first: u8,
+ ///     third: u8,
+ ///     second: u16
+ /// }
+ ///
+ /// assert_eq!(4, mem::size_of::<FieldStructOptimized>());
+ ///
+ /// // Union size is the size of the largest field.
+ /// #[repr(C)]
+ /// union ExampleUnion {
+ ///     smaller: u8,
+ ///     larger: u16
+ /// }
+ ///
+ /// assert_eq!(2, mem::size_of::<ExampleUnion>());
+ /// ```
+ ///
+ /// [alignment]: align_of
+ #[inline(always)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_promotable]
+ #[rustc_const_stable(feature = "const_size_of", since = "1.32.0")]
+ pub const fn size_of<T>() -> usize {
+     intrinsics::size_of::<T>()
+ }
+ 
+ /// Returns the size of the pointed-to value in bytes.
+ ///
+ /// This is usually the same as `size_of::<T>()`. However, when `T` *has* no
+ /// statically-known size, e.g., a slice [`[T]`][slice] or a [trait object],
+ /// then `size_of_val` can be used to get the dynamically-known size.
+ ///
+ /// [slice]: ../../std/primitive.slice.html
+ /// [trait object]: ../../book/ch17-02-trait-objects.html
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, mem::size_of_val(&5i32));
+ ///
+ /// let x: [u8; 13] = [0; 13];
+ /// let y: &[u8] = &x;
+ /// assert_eq!(13, mem::size_of_val(y));
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_const_unstable(feature = "const_size_of_val", issue = "46571")]
+ pub const fn size_of_val<T: ?Sized>(val: &T) -> usize {
+     intrinsics::size_of_val(val)
+ }
+ 
+ /// Returns the size of the pointed-to value in bytes.
+ ///
+ /// This is usually the same as `size_of::<T>()`. However, when `T` *has* no
+ /// statically-known size, e.g., a slice [`[T]`][slice] or a [trait object],
+ /// then `size_of_val_raw` can be used to get the dynamically-known size.
+ ///
+ /// # Safety
+ ///
+ /// This function is only safe to call if the following conditions hold:
+ ///
+ /// - If `T` is `Sized`, this function is always safe to call.
+ /// - If the unsized tail of `T` is:
+ ///     - a [slice], then the length of the slice tail must be an initialized
+ ///       integer, and the size of the *entire value*
+ ///       (dynamic tail length + statically sized prefix) must fit in `isize`.
+ ///     - a [trait object], then the vtable part of the pointer must point
+ ///       to a valid vtable acquired by an unsizing coercion, and the size
+ ///       of the *entire value* (dynamic tail length + statically sized prefix)
+ ///       must fit in `isize`.
+ ///     - an (unstable) [extern type], then this function is always safe to
+ ///       call, but may panic or otherwise return the wrong value, as the
+ ///       extern type's layout is not known. This is the same behavior as
+ ///       [`size_of_val`] on a reference to a type with an extern type tail.
+ ///     - otherwise, it is conservatively not allowed to call this function.
+ ///
+ /// [slice]: ../../std/primitive.slice.html
+ /// [trait object]: ../../book/ch17-02-trait-objects.html
+ /// [extern type]: ../../unstable-book/language-features/extern-types.html
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(layout_for_ptr)]
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, mem::size_of_val(&5i32));
+ ///
+ /// let x: [u8; 13] = [0; 13];
+ /// let y: &[u8] = &x;
+ /// assert_eq!(13, unsafe { mem::size_of_val_raw(y) });
+ /// ```
+ #[inline]
+ #[unstable(feature = "layout_for_ptr", issue = "69835")]
+ pub unsafe fn size_of_val_raw<T: ?Sized>(val: *const T) -> usize {
+     intrinsics::size_of_val(val)
+ }
+ 
+ /// Returns the [ABI]-required minimum alignment of a type.
+ ///
+ /// Every reference to a value of the type `T` must be a multiple of this number.
+ ///
+ /// This is the alignment used for struct fields. It may be smaller than the preferred alignment.
+ ///
+ /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// # #![allow(deprecated)]
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, mem::min_align_of::<i32>());
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_deprecated(reason = "use `align_of` instead", since = "1.2.0")]
+ pub fn min_align_of<T>() -> usize {
+     intrinsics::min_align_of::<T>()
+ }
+ 
+ /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to.
+ ///
+ /// Every reference to a value of the type `T` must be a multiple of this number.
+ ///
+ /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// # #![allow(deprecated)]
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, mem::min_align_of_val(&5i32));
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_deprecated(reason = "use `align_of_val` instead", since = "1.2.0")]
+ pub fn min_align_of_val<T: ?Sized>(val: &T) -> usize {
+     intrinsics::min_align_of_val(val)
+ }
+ 
+ /// Returns the [ABI]-required minimum alignment of a type.
+ ///
+ /// Every reference to a value of the type `T` must be a multiple of this number.
+ ///
+ /// This is the alignment used for struct fields. It may be smaller than the preferred alignment.
+ ///
+ /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, mem::align_of::<i32>());
+ /// ```
+ #[inline(always)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_promotable]
+ #[rustc_const_stable(feature = "const_align_of", since = "1.32.0")]
+ pub const fn align_of<T>() -> usize {
+     intrinsics::min_align_of::<T>()
+ }
+ 
+ /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to.
+ ///
+ /// Every reference to a value of the type `T` must be a multiple of this number.
+ ///
+ /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, mem::align_of_val(&5i32));
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_const_unstable(feature = "const_align_of_val", issue = "46571")]
+ #[allow(deprecated)]
+ pub const fn align_of_val<T: ?Sized>(val: &T) -> usize {
+     intrinsics::min_align_of_val(val)
+ }
+ 
+ /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to.
+ ///
+ /// Every reference to a value of the type `T` must be a multiple of this number.
+ ///
+ /// [ABI]: https://en.wikipedia.org/wiki/Application_binary_interface
+ ///
+ /// # Safety
+ ///
+ /// This function is only safe to call if the following conditions hold:
+ ///
+ /// - If `T` is `Sized`, this function is always safe to call.
+ /// - If the unsized tail of `T` is:
+ ///     - a [slice], then the length of the slice tail must be an initialized
+ ///       integer, and the size of the *entire value*
+ ///       (dynamic tail length + statically sized prefix) must fit in `isize`.
+ ///     - a [trait object], then the vtable part of the pointer must point
+ ///       to a valid vtable acquired by an unsizing coercion, and the size
+ ///       of the *entire value* (dynamic tail length + statically sized prefix)
+ ///       must fit in `isize`.
+ ///     - an (unstable) [extern type], then this function is always safe to
+ ///       call, but may panic or otherwise return the wrong value, as the
+ ///       extern type's layout is not known. This is the same behavior as
+ ///       [`align_of_val`] on a reference to a type with an extern type tail.
+ ///     - otherwise, it is conservatively not allowed to call this function.
+ ///
+ /// [slice]: ../../std/primitive.slice.html
+ /// [trait object]: ../../book/ch17-02-trait-objects.html
+ /// [extern type]: ../../unstable-book/language-features/extern-types.html
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(layout_for_ptr)]
+ /// use std::mem;
+ ///
+ /// assert_eq!(4, unsafe { mem::align_of_val_raw(&5i32) });
+ /// ```
+ #[inline]
+ #[unstable(feature = "layout_for_ptr", issue = "69835")]
+ pub unsafe fn align_of_val_raw<T: ?Sized>(val: *const T) -> usize {
+     intrinsics::min_align_of_val(val)
+ }
+ 
+ /// Returns `true` if dropping values of type `T` matters.
+ ///
+ /// This is purely an optimization hint, and may be implemented conservatively:
+ /// it may return `true` for types that don't actually need to be dropped.
+ /// As such always returning `true` would be a valid implementation of
+ /// this function. However if this function actually returns `false`, then you
+ /// can be certain dropping `T` has no side effect.
+ ///
+ /// Low level implementations of things like collections, which need to manually
+ /// drop their data, should use this function to avoid unnecessarily
+ /// trying to drop all their contents when they are destroyed. This might not
+ /// make a difference in release builds (where a loop that has no side-effects
+ /// is easily detected and eliminated), but is often a big win for debug builds.
+ ///
+ /// Note that [`drop_in_place`] already performs this check, so if your workload
+ /// can be reduced to some small number of [`drop_in_place`] calls, using this is
+ /// unnecessary. In particular note that you can [`drop_in_place`] a slice, and that
+ /// will do a single needs_drop check for all the values.
+ ///
+ /// Types like Vec therefore just `drop_in_place(&mut self[..])` without using
+ /// `needs_drop` explicitly. Types like [`HashMap`], on the other hand, have to drop
+ /// values one at a time and should use this API.
+ ///
+ /// [`drop_in_place`]: crate::ptr::drop_in_place
+ /// [`HashMap`]: ../../std/collections/struct.HashMap.html
+ ///
+ /// # Examples
+ ///
+ /// Here's an example of how a collection might make use of `needs_drop`:
+ ///
+ /// ```
+ /// use std::{mem, ptr};
+ ///
+ /// pub struct MyCollection<T> {
+ /// #   data: [T; 1],
+ ///     /* ... */
+ /// }
+ /// # impl<T> MyCollection<T> {
+ /// #   fn iter_mut(&mut self) -> &mut [T] { &mut self.data }
+ /// #   fn free_buffer(&mut self) {}
+ /// # }
+ ///
+ /// impl<T> Drop for MyCollection<T> {
+ ///     fn drop(&mut self) {
+ ///         unsafe {
+ ///             // drop the data
+ ///             if mem::needs_drop::<T>() {
+ ///                 for x in self.iter_mut() {
+ ///                     ptr::drop_in_place(x);
+ ///                 }
+ ///             }
+ ///             self.free_buffer();
+ ///         }
+ ///     }
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "needs_drop", since = "1.21.0")]
+ #[rustc_const_stable(feature = "const_needs_drop", since = "1.36.0")]
+ #[rustc_diagnostic_item = "needs_drop"]
+ pub const fn needs_drop<T>() -> bool {
+     intrinsics::needs_drop::<T>()
+ }
+ 
+ /// Returns the value of type `T` represented by the all-zero byte-pattern.
+ ///
+ /// This means that, for example, the padding byte in `(u8, u16)` is not
+ /// necessarily zeroed.
+ ///
+ /// There is no guarantee that an all-zero byte-pattern represents a valid value
+ /// of some type `T`. For example, the all-zero byte-pattern is not a valid value
+ /// for reference types (`&T`, `&mut T`) and functions pointers. Using `zeroed`
+ /// on such types causes immediate [undefined behavior][ub] because [the Rust
+ /// compiler assumes][inv] that there always is a valid value in a variable it
+ /// considers initialized.
+ ///
+ /// This has the same effect as [`MaybeUninit::zeroed().assume_init()`][zeroed].
+ /// It is useful for FFI sometimes, but should generally be avoided.
+ ///
+ /// [zeroed]: MaybeUninit::zeroed
+ /// [ub]: ../../reference/behavior-considered-undefined.html
+ /// [inv]: MaybeUninit#initialization-invariant
+ ///
+ /// # Examples
+ ///
+ /// Correct usage of this function: initializing an integer with zero.
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// let x: i32 = unsafe { mem::zeroed() };
+ /// assert_eq!(0, x);
+ /// ```
+ ///
+ /// *Incorrect* usage of this function: initializing a reference with zero.
+ ///
+ /// ```rust,no_run
+ /// # #![allow(invalid_value)]
+ /// use std::mem;
+ ///
+ /// let _x: &i32 = unsafe { mem::zeroed() }; // Undefined behavior!
+ /// let _y: fn() = unsafe { mem::zeroed() }; // And again!
+ /// ```
+ #[inline(always)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow(deprecated_in_future)]
+ #[allow(deprecated)]
+ #[rustc_diagnostic_item = "mem_zeroed"]
+ pub unsafe fn zeroed<T>() -> T {
+     // SAFETY: the caller must guarantee that an all-zero value is valid for `T`.
+     unsafe {
+         intrinsics::assert_zero_valid::<T>();
+         MaybeUninit::zeroed().assume_init()
+     }
+ }
+ 
+ /// Bypasses Rust's normal memory-initialization checks by pretending to
+ /// produce a value of type `T`, while doing nothing at all.
+ ///
+ /// **This function is deprecated.** Use [`MaybeUninit<T>`] instead.
+ ///
+ /// The reason for deprecation is that the function basically cannot be used
+ /// correctly: it has the same effect as [`MaybeUninit::uninit().assume_init()`][uninit].
+ /// As the [`assume_init` documentation][assume_init] explains,
+ /// [the Rust compiler assumes][inv] that values are properly initialized.
+ /// As a consequence, calling e.g. `mem::uninitialized::<bool>()` causes immediate
+ /// undefined behavior for returning a `bool` that is not definitely either `true`
+ /// or `false`. Worse, truly uninitialized memory like what gets returned here
+ /// is special in that the compiler knows that it does not have a fixed value.
+ /// This makes it undefined behavior to have uninitialized data in a variable even
+ /// if that variable has an integer type.
+ /// (Notice that the rules around uninitialized integers are not finalized yet, but
+ /// until they are, it is advisable to avoid them.)
+ ///
+ /// [`MaybeUninit<T>`]: MaybeUninit
+ /// [uninit]: MaybeUninit::uninit
+ /// [assume_init]: MaybeUninit::assume_init
+ /// [inv]: MaybeUninit#initialization-invariant
+ #[inline(always)]
+ #[rustc_deprecated(since = "1.39.0", reason = "use `mem::MaybeUninit` instead")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow(deprecated_in_future)]
+ #[allow(deprecated)]
+ #[rustc_diagnostic_item = "mem_uninitialized"]
+ pub unsafe fn uninitialized<T>() -> T {
+     // SAFETY: the caller must guarantee that an unitialized value is valid for `T`.
+     unsafe {
+         intrinsics::assert_uninit_valid::<T>();
+         MaybeUninit::uninit().assume_init()
+     }
+ }
+ 
+ /// Swaps the values at two mutable locations, without deinitializing either one.
+ ///
+ /// * If you want to swap with a default or dummy value, see [`take`].
+ /// * If you want to swap with a passed value, returning the old value, see [`replace`].
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// let mut x = 5;
+ /// let mut y = 42;
+ ///
+ /// mem::swap(&mut x, &mut y);
+ ///
+ /// assert_eq!(42, x);
+ /// assert_eq!(5, y);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn swap<T>(x: &mut T, y: &mut T) {
+     // SAFETY: the raw pointers have been created from safe mutable references satisfying all the
+     // constraints on `ptr::swap_nonoverlapping_one`
+     unsafe {
+         ptr::swap_nonoverlapping_one(x, y);
+     }
+ }
+ 
+ /// Replaces `dest` with the default value of `T`, returning the previous `dest` value.
+ ///
+ /// * If you want to replace the values of two variables, see [`swap`].
+ /// * If you want to replace with a passed value instead of the default value, see [`replace`].
+ ///
+ /// # Examples
+ ///
+ /// A simple example:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// let mut v: Vec<i32> = vec![1, 2];
+ ///
+ /// let old_v = mem::take(&mut v);
+ /// assert_eq!(vec![1, 2], old_v);
+ /// assert!(v.is_empty());
+ /// ```
+ ///
+ /// `take` allows taking ownership of a struct field by replacing it with an "empty" value.
+ /// Without `take` you can run into issues like these:
+ ///
+ /// ```compile_fail,E0507
+ /// struct Buffer<T> { buf: Vec<T> }
+ ///
+ /// impl<T> Buffer<T> {
+ ///     fn get_and_reset(&mut self) -> Vec<T> {
+ ///         // error: cannot move out of dereference of `&mut`-pointer
+ ///         let buf = self.buf;
+ ///         self.buf = Vec::new();
+ ///         buf
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// Note that `T` does not necessarily implement [`Clone`], so it can't even clone and reset
+ /// `self.buf`. But `take` can be used to disassociate the original value of `self.buf` from
+ /// `self`, allowing it to be returned:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// # struct Buffer<T> { buf: Vec<T> }
+ /// impl<T> Buffer<T> {
+ ///     fn get_and_reset(&mut self) -> Vec<T> {
+ ///         mem::take(&mut self.buf)
+ ///     }
+ /// }
+ ///
+ /// let mut buffer = Buffer { buf: vec![0, 1] };
+ /// assert_eq!(buffer.buf.len(), 2);
+ ///
+ /// assert_eq!(buffer.get_and_reset(), vec![0, 1]);
+ /// assert_eq!(buffer.buf.len(), 0);
+ /// ```
+ #[inline]
+ #[stable(feature = "mem_take", since = "1.40.0")]
+ pub fn take<T: Default>(dest: &mut T) -> T {
+     replace(dest, T::default())
+ }
+ 
+ /// Moves `src` into the referenced `dest`, returning the previous `dest` value.
+ ///
+ /// Neither value is dropped.
+ ///
+ /// * If you want to replace the values of two variables, see [`swap`].
+ /// * If you want to replace with a default value, see [`take`].
+ ///
+ /// # Examples
+ ///
+ /// A simple example:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// let mut v: Vec<i32> = vec![1, 2];
+ ///
+ /// let old_v = mem::replace(&mut v, vec![3, 4, 5]);
+ /// assert_eq!(vec![1, 2], old_v);
+ /// assert_eq!(vec![3, 4, 5], v);
+ /// ```
+ ///
+ /// `replace` allows consumption of a struct field by replacing it with another value.
+ /// Without `replace` you can run into issues like these:
+ ///
+ /// ```compile_fail,E0507
+ /// struct Buffer<T> { buf: Vec<T> }
+ ///
+ /// impl<T> Buffer<T> {
+ ///     fn replace_index(&mut self, i: usize, v: T) -> T {
+ ///         // error: cannot move out of dereference of `&mut`-pointer
+ ///         let t = self.buf[i];
+ ///         self.buf[i] = v;
+ ///         t
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// Note that `T` does not necessarily implement [`Clone`], so we can't even clone `self.buf[i]` to
+ /// avoid the move. But `replace` can be used to disassociate the original value at that index from
+ /// `self`, allowing it to be returned:
+ ///
+ /// ```
+ /// # #![allow(dead_code)]
+ /// use std::mem;
+ ///
+ /// # struct Buffer<T> { buf: Vec<T> }
+ /// impl<T> Buffer<T> {
+ ///     fn replace_index(&mut self, i: usize, v: T) -> T {
+ ///         mem::replace(&mut self.buf[i], v)
+ ///     }
+ /// }
+ ///
+ /// let mut buffer = Buffer { buf: vec![0, 1] };
+ /// assert_eq!(buffer.buf[0], 0);
+ ///
+ /// assert_eq!(buffer.replace_index(0, 2), 0);
+ /// assert_eq!(buffer.buf[0], 2);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[must_use = "if you don't need the old value, you can just assign the new value directly"]
+ pub fn replace<T>(dest: &mut T, mut src: T) -> T {
+     swap(dest, &mut src);
+     src
+ }
+ 
+ /// Disposes of a value.
+ ///
+ /// This does so by calling the argument's implementation of [`Drop`][drop].
+ ///
+ /// This effectively does nothing for types which implement `Copy`, e.g.
+ /// integers. Such values are copied and _then_ moved into the function, so the
+ /// value persists after this function call.
+ ///
+ /// This function is not magic; it is literally defined as
+ ///
+ /// ```
+ /// pub fn drop<T>(_x: T) { }
+ /// ```
+ ///
+ /// Because `_x` is moved into the function, it is automatically dropped before
+ /// the function returns.
+ ///
+ /// [drop]: Drop
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let v = vec![1, 2, 3];
+ ///
+ /// drop(v); // explicitly drop the vector
+ /// ```
+ ///
+ /// Since [`RefCell`] enforces the borrow rules at runtime, `drop` can
+ /// release a [`RefCell`] borrow:
+ ///
+ /// ```
+ /// use std::cell::RefCell;
+ ///
+ /// let x = RefCell::new(1);
+ ///
+ /// let mut mutable_borrow = x.borrow_mut();
+ /// *mutable_borrow = 1;
+ ///
+ /// drop(mutable_borrow); // relinquish the mutable borrow on this slot
+ ///
+ /// let borrow = x.borrow();
+ /// println!("{}", *borrow);
+ /// ```
+ ///
+ /// Integers and other types implementing [`Copy`] are unaffected by `drop`.
+ ///
+ /// ```
+ /// #[derive(Copy, Clone)]
+ /// struct Foo(u8);
+ ///
+ /// let x = 1;
+ /// let y = Foo(2);
+ /// drop(x); // a copy of `x` is moved and dropped
+ /// drop(y); // a copy of `y` is moved and dropped
+ ///
+ /// println!("x: {}, y: {}", x, y.0); // still available
+ /// ```
+ ///
+ /// [`RefCell`]: crate::cell::RefCell
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn drop<T>(_x: T) {}
+ 
+ /// Interprets `src` as having type `&U`, and then reads `src` without moving
+ /// the contained value.
+ ///
+ /// This function will unsafely assume the pointer `src` is valid for [`size_of::<U>`][size_of]
+ /// bytes by transmuting `&T` to `&U` and then reading the `&U` (except that this is done in a way
+ /// that is correct even when `&U` makes stricter alignment requirements than `&T`). It will also
+ /// unsafely create a copy of the contained value instead of moving out of `src`.
+ ///
+ /// It is not a compile-time error if `T` and `U` have different sizes, but it
+ /// is highly encouraged to only invoke this function where `T` and `U` have the
+ /// same size. This function triggers [undefined behavior][ub] if `U` is larger than
+ /// `T`.
+ ///
+ /// [ub]: ../../reference/behavior-considered-undefined.html
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// #[repr(packed)]
+ /// struct Foo {
+ ///     bar: u8,
+ /// }
+ ///
+ /// let foo_array = [10u8];
+ ///
+ /// unsafe {
+ ///     // Copy the data from 'foo_array' and treat it as a 'Foo'
+ ///     let mut foo_struct: Foo = mem::transmute_copy(&foo_array);
+ ///     assert_eq!(foo_struct.bar, 10);
+ ///
+ ///     // Modify the copied data
+ ///     foo_struct.bar = 20;
+ ///     assert_eq!(foo_struct.bar, 20);
+ /// }
+ ///
+ /// // The contents of 'foo_array' should not have changed
+ /// assert_eq!(foo_array, [10]);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn transmute_copy<T, U>(src: &T) -> U {
+     // If U has a higher alignment requirement, src may not be suitably aligned.
+     if align_of::<U>() > align_of::<T>() {
+         // SAFETY: `src` is a reference which is guaranteed to be valid for reads.
+         // The caller must guarantee that the actual transmutation is safe.
+         unsafe { ptr::read_unaligned(src as *const T as *const U) }
+     } else {
+         // SAFETY: `src` is a reference which is guaranteed to be valid for reads.
+         // We just checked that `src as *const U` was properly aligned.
+         // The caller must guarantee that the actual transmutation is safe.
+         unsafe { ptr::read(src as *const T as *const U) }
+     }
+ }
+ 
+ /// Opaque type representing the discriminant of an enum.
+ ///
+ /// See the [`discriminant`] function in this module for more information.
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ pub struct Discriminant<T>(<T as DiscriminantKind>::Discriminant);
+ 
+ // N.B. These trait implementations cannot be derived because we don't want any bounds on T.
+ 
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ impl<T> Copy for Discriminant<T> {}
+ 
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ impl<T> clone::Clone for Discriminant<T> {
+     fn clone(&self) -> Self {
+         *self
+     }
+ }
+ 
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ impl<T> cmp::PartialEq for Discriminant<T> {
+     fn eq(&self, rhs: &Self) -> bool {
+         self.0 == rhs.0
+     }
+ }
+ 
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ impl<T> cmp::Eq for Discriminant<T> {}
+ 
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ impl<T> hash::Hash for Discriminant<T> {
+     fn hash<H: hash::Hasher>(&self, state: &mut H) {
+         self.0.hash(state);
+     }
+ }
+ 
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ impl<T> fmt::Debug for Discriminant<T> {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt.debug_tuple("Discriminant").field(&self.0).finish()
+     }
+ }
+ 
+ /// Returns a value uniquely identifying the enum variant in `v`.
+ ///
+ /// If `T` is not an enum, calling this function will not result in undefined behavior, but the
+ /// return value is unspecified.
+ ///
+ /// # Stability
+ ///
+ /// The discriminant of an enum variant may change if the enum definition changes. A discriminant
+ /// of some variant will not change between compilations with the same compiler.
+ ///
+ /// # Examples
+ ///
+ /// This can be used to compare enums that carry data, while disregarding
+ /// the actual data:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// enum Foo { A(&'static str), B(i32), C(i32) }
+ ///
+ /// assert_eq!(mem::discriminant(&Foo::A("bar")), mem::discriminant(&Foo::A("baz")));
+ /// assert_eq!(mem::discriminant(&Foo::B(1)), mem::discriminant(&Foo::B(2)));
+ /// assert_ne!(mem::discriminant(&Foo::B(3)), mem::discriminant(&Foo::C(3)));
+ /// ```
+ #[stable(feature = "discriminant_value", since = "1.21.0")]
+ #[rustc_const_unstable(feature = "const_discriminant", issue = "69821")]
+ pub const fn discriminant<T>(v: &T) -> Discriminant<T> {
+     Discriminant(intrinsics::discriminant_value(v))
+ }
+ 
+ /// Returns the number of variants in the enum type `T`.
+ ///
+ /// If `T` is not an enum, calling this function will not result in undefined behavior, but the
+ /// return value is unspecified. Equally, if `T` is an enum with more variants than `usize::MAX`
+ /// the return value is unspecified. Uninhabited variants will be counted.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// # #![feature(never_type)]
+ /// # #![feature(variant_count)]
+ ///
+ /// use std::mem;
+ ///
+ /// enum Void {}
+ /// enum Foo { A(&'static str), B(i32), C(i32) }
+ ///
+ /// assert_eq!(mem::variant_count::<Void>(), 0);
+ /// assert_eq!(mem::variant_count::<Foo>(), 3);
+ ///
+ /// assert_eq!(mem::variant_count::<Option<!>>(), 2);
+ /// assert_eq!(mem::variant_count::<Result<!, !>>(), 2);
+ /// ```
+ #[inline(always)]
+ #[unstable(feature = "variant_count", issue = "73662")]
+ #[rustc_const_unstable(feature = "variant_count", issue = "73662")]
+ pub const fn variant_count<T>() -> usize {
+     intrinsics::variant_count::<T>()
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/bignum.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/bignum.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/bignum.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/bignum.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,473 ----
+ //! Custom arbitrary-precision number (bignum) implementation.
+ //!
+ //! This is designed to avoid the heap allocation at expense of stack memory.
+ //! The most used bignum type, `Big32x40`, is limited by 32 × 40 = 1,280 bits
+ //! and will take at most 160 bytes of stack memory. This is more than enough
+ //! for round-tripping all possible finite `f64` values.
+ //!
+ //! In principle it is possible to have multiple bignum types for different
+ //! inputs, but we don't do so to avoid the code bloat. Each bignum is still
+ //! tracked for the actual usages, so it normally doesn't matter.
+ 
+ // This module is only for dec2flt and flt2dec, and only public because of coretests.
+ // It is not intended to ever be stabilized.
+ #![doc(hidden)]
+ #![unstable(
+     feature = "core_private_bignum",
+     reason = "internal routines only exposed for testing",
+     issue = "none"
+ )]
+ #![macro_use]
+ 
+ use crate::intrinsics;
+ 
+ /// Arithmetic operations required by bignums.
+ pub trait FullOps: Sized {
+     /// Returns `(carry', v')` such that `carry' * 2^W + v' = self + other + carry`,
+     /// where `W` is the number of bits in `Self`.
+     fn full_add(self, other: Self, carry: bool) -> (bool /* carry */, Self);
+ 
+     /// Returns `(carry', v')` such that `carry' * 2^W + v' = self * other + carry`,
+     /// where `W` is the number of bits in `Self`.
+     fn full_mul(self, other: Self, carry: Self) -> (Self /* carry */, Self);
+ 
+     /// Returns `(carry', v')` such that `carry' * 2^W + v' = self * other + other2 + carry`,
+     /// where `W` is the number of bits in `Self`.
+     fn full_mul_add(self, other: Self, other2: Self, carry: Self) -> (Self /* carry */, Self);
+ 
+     /// Returns `(quo, rem)` such that `borrow * 2^W + self = quo * other + rem`
+     /// and `0 <= rem < other`, where `W` is the number of bits in `Self`.
+     fn full_div_rem(self, other: Self, borrow: Self)
+     -> (Self /* quotient */, Self /* remainder */);
+ }
+ 
+ macro_rules! impl_full_ops {
+     ($($ty:ty: add($addfn:path), mul/div($bigty:ident);)*) => (
+         $(
+             impl FullOps for $ty {
+                 fn full_add(self, other: $ty, carry: bool) -> (bool, $ty) {
+                     // This cannot overflow; the output is between `0` and `2 * 2^nbits - 1`.
+                     // FIXME: will LLVM optimize this into ADC or similar?
+                     let (v, carry1) = intrinsics::add_with_overflow(self, other);
+                     let (v, carry2) = intrinsics::add_with_overflow(v, if carry {1} else {0});
+                     (carry1 || carry2, v)
+                 }
+ 
+                 fn full_mul(self, other: $ty, carry: $ty) -> ($ty, $ty) {
+                     // This cannot overflow;
+                     // the output is between `0` and `2^nbits * (2^nbits - 1)`.
+                     // FIXME: will LLVM optimize this into ADC or similar?
+                     let v = (self as $bigty) * (other as $bigty) + (carry as $bigty);
+                     ((v >> <$ty>::BITS) as $ty, v as $ty)
+                 }
+ 
+                 fn full_mul_add(self, other: $ty, other2: $ty, carry: $ty) -> ($ty, $ty) {
+                     // This cannot overflow;
+                     // the output is between `0` and `2^nbits * (2^nbits - 1)`.
+                     let v = (self as $bigty) * (other as $bigty) + (other2 as $bigty) +
+                             (carry as $bigty);
+                     ((v >> <$ty>::BITS) as $ty, v as $ty)
+                 }
+ 
+                 fn full_div_rem(self, other: $ty, borrow: $ty) -> ($ty, $ty) {
+                     debug_assert!(borrow < other);
+                     // This cannot overflow; the output is between `0` and `other * (2^nbits - 1)`.
+                     let lhs = ((borrow as $bigty) << <$ty>::BITS) | (self as $bigty);
+                     let rhs = other as $bigty;
+                     ((lhs / rhs) as $ty, (lhs % rhs) as $ty)
+                 }
+             }
+         )*
+     )
+ }
+ 
+ impl_full_ops! {
+     u8:  add(intrinsics::u8_add_with_overflow),  mul/div(u16);
+     u16: add(intrinsics::u16_add_with_overflow), mul/div(u32);
+     u32: add(intrinsics::u32_add_with_overflow), mul/div(u64);
+     // See RFC #521 for enabling this.
+     // u64: add(intrinsics::u64_add_with_overflow), mul/div(u128);
+ }
+ 
+ /// Table of powers of 5 representable in digits. Specifically, the largest {u8, u16, u32} value
+ /// that's a power of five, plus the corresponding exponent. Used in `mul_pow5`.
+ const SMALL_POW5: [(u64, usize); 3] = [(125, 3), (15625, 6), (1_220_703_125, 13)];
+ 
+ macro_rules! define_bignum {
+     ($name:ident: type=$ty:ty, n=$n:expr) => {
+         /// Stack-allocated arbitrary-precision (up to certain limit) integer.
+         ///
+         /// This is backed by a fixed-size array of given type ("digit").
+         /// While the array is not very large (normally some hundred bytes),
+         /// copying it recklessly may result in the performance hit.
+         /// Thus this is intentionally not `Copy`.
+         ///
+         /// All operations available to bignums panic in the case of overflows.
+         /// The caller is responsible to use large enough bignum types.
+         pub struct $name {
+             /// One plus the offset to the maximum "digit" in use.
+             /// This does not decrease, so be aware of the computation order.
+             /// `base[size..]` should be zero.
+             size: usize,
+             /// Digits. `[a, b, c, ...]` represents `a + b*2^W + c*2^(2W) + ...`
+             /// where `W` is the number of bits in the digit type.
+             base: [$ty; $n],
+         }
+ 
+         impl $name {
+             /// Makes a bignum from one digit.
+             pub fn from_small(v: $ty) -> $name {
+                 let mut base = [0; $n];
+                 base[0] = v;
+                 $name { size: 1, base: base }
+             }
+ 
+             /// Makes a bignum from `u64` value.
+             pub fn from_u64(mut v: u64) -> $name {
+                 let mut base = [0; $n];
+                 let mut sz = 0;
+                 while v > 0 {
+                     base[sz] = v as $ty;
+                     v >>= <$ty>::BITS;
+                     sz += 1;
+                 }
+                 $name { size: sz, base: base }
+             }
+ 
+             /// Returns the internal digits as a slice `[a, b, c, ...]` such that the numeric
+             /// value is `a + b * 2^W + c * 2^(2W) + ...` where `W` is the number of bits in
+             /// the digit type.
+             pub fn digits(&self) -> &[$ty] {
+                 &self.base[..self.size]
+             }
+ 
+             /// Returns the `i`-th bit where bit 0 is the least significant one.
+             /// In other words, the bit with weight `2^i`.
+             pub fn get_bit(&self, i: usize) -> u8 {
+                 let digitbits = <$ty>::BITS as usize;
+                 let d = i / digitbits;
+                 let b = i % digitbits;
+                 ((self.base[d] >> b) & 1) as u8
+             }
+ 
+             /// Returns `true` if the bignum is zero.
+             pub fn is_zero(&self) -> bool {
+                 self.digits().iter().all(|&v| v == 0)
+             }
+ 
+             /// Returns the number of bits necessary to represent this value. Note that zero
+             /// is considered to need 0 bits.
+             pub fn bit_length(&self) -> usize {
+                 // Skip over the most significant digits which are zero.
+                 let digits = self.digits();
+                 let zeros = digits.iter().rev().take_while(|&&x| x == 0).count();
+                 let end = digits.len() - zeros;
+                 let nonzero = &digits[..end];
+ 
+                 if nonzero.is_empty() {
+                     // There are no non-zero digits, i.e., the number is zero.
+                     return 0;
+                 }
+                 // This could be optimized with leading_zeros() and bit shifts, but that's
+                 // probably not worth the hassle.
+                 let digitbits = <$ty>::BITS as usize;
+                 let mut i = nonzero.len() * digitbits - 1;
+                 while self.get_bit(i) == 0 {
+                     i -= 1;
+                 }
+                 i + 1
+             }
+ 
+             /// Adds `other` to itself and returns its own mutable reference.
+             pub fn add<'a>(&'a mut self, other: &$name) -> &'a mut $name {
+                 use crate::cmp;
+                 use crate::num::bignum::FullOps;
+ 
+                 let mut sz = cmp::max(self.size, other.size);
+                 let mut carry = false;
+                 for (a, b) in self.base[..sz].iter_mut().zip(&other.base[..sz]) {
+                     let (c, v) = (*a).full_add(*b, carry);
+                     *a = v;
+                     carry = c;
+                 }
+                 if carry {
+                     self.base[sz] = 1;
+                     sz += 1;
+                 }
+                 self.size = sz;
+                 self
+             }
+ 
+             pub fn add_small(&mut self, other: $ty) -> &mut $name {
+                 use crate::num::bignum::FullOps;
+ 
+                 let (mut carry, v) = self.base[0].full_add(other, false);
+                 self.base[0] = v;
+                 let mut i = 1;
+                 while carry {
+                     let (c, v) = self.base[i].full_add(0, carry);
+                     self.base[i] = v;
+                     carry = c;
+                     i += 1;
+                 }
+                 if i > self.size {
+                     self.size = i;
+                 }
+                 self
+             }
+ 
+             /// Subtracts `other` from itself and returns its own mutable reference.
+             pub fn sub<'a>(&'a mut self, other: &$name) -> &'a mut $name {
+                 use crate::cmp;
+                 use crate::num::bignum::FullOps;
+ 
+                 let sz = cmp::max(self.size, other.size);
+                 let mut noborrow = true;
+                 for (a, b) in self.base[..sz].iter_mut().zip(&other.base[..sz]) {
+                     let (c, v) = (*a).full_add(!*b, noborrow);
+                     *a = v;
+                     noborrow = c;
+                 }
+                 assert!(noborrow);
+                 self.size = sz;
+                 self
+             }
+ 
+             /// Multiplies itself by a digit-sized `other` and returns its own
+             /// mutable reference.
+             pub fn mul_small(&mut self, other: $ty) -> &mut $name {
+                 use crate::num::bignum::FullOps;
+ 
+                 let mut sz = self.size;
+                 let mut carry = 0;
+                 for a in &mut self.base[..sz] {
+                     let (c, v) = (*a).full_mul(other, carry);
+                     *a = v;
+                     carry = c;
+                 }
+                 if carry > 0 {
+                     self.base[sz] = carry;
+                     sz += 1;
+                 }
+                 self.size = sz;
+                 self
+             }
+ 
+             /// Multiplies itself by `2^bits` and returns its own mutable reference.
+             pub fn mul_pow2(&mut self, bits: usize) -> &mut $name {
+                 let digitbits = <$ty>::BITS as usize;
+                 let digits = bits / digitbits;
+                 let bits = bits % digitbits;
+ 
+                 assert!(digits < $n);
+                 debug_assert!(self.base[$n - digits..].iter().all(|&v| v == 0));
+                 debug_assert!(bits == 0 || (self.base[$n - digits - 1] >> (digitbits - bits)) == 0);
+ 
+                 // shift by `digits * digitbits` bits
+                 for i in (0..self.size).rev() {
+                     self.base[i + digits] = self.base[i];
+                 }
+                 for i in 0..digits {
+                     self.base[i] = 0;
+                 }
+ 
+                 // shift by `bits` bits
+                 let mut sz = self.size + digits;
+                 if bits > 0 {
+                     let last = sz;
+                     let overflow = self.base[last - 1] >> (digitbits - bits);
+                     if overflow > 0 {
+                         self.base[last] = overflow;
+                         sz += 1;
+                     }
+                     for i in (digits + 1..last).rev() {
+                         self.base[i] =
+                             (self.base[i] << bits) | (self.base[i - 1] >> (digitbits - bits));
+                     }
+                     self.base[digits] <<= bits;
+                     // self.base[..digits] is zero, no need to shift
+                 }
+ 
+                 self.size = sz;
+                 self
+             }
+ 
+             /// Multiplies itself by `5^e` and returns its own mutable reference.
+             pub fn mul_pow5(&mut self, mut e: usize) -> &mut $name {
+                 use crate::mem;
+                 use crate::num::bignum::SMALL_POW5;
+ 
+                 // There are exactly n trailing zeros on 2^n, and the only relevant digit sizes
+                 // are consecutive powers of two, so this is well suited index for the table.
+                 let table_index = mem::size_of::<$ty>().trailing_zeros() as usize;
+                 let (small_power, small_e) = SMALL_POW5[table_index];
+                 let small_power = small_power as $ty;
+ 
+                 // Multiply with the largest single-digit power as long as possible ...
+                 while e >= small_e {
+                     self.mul_small(small_power);
+                     e -= small_e;
+                 }
+ 
+                 // ... then finish off the remainder.
+                 let mut rest_power = 1;
+                 for _ in 0..e {
+                     rest_power *= 5;
+                 }
+                 self.mul_small(rest_power);
+ 
+                 self
+             }
+ 
+             /// Multiplies itself by a number described by `other[0] + other[1] * 2^W +
+             /// other[2] * 2^(2W) + ...` (where `W` is the number of bits in the digit type)
+             /// and returns its own mutable reference.
+             pub fn mul_digits<'a>(&'a mut self, other: &[$ty]) -> &'a mut $name {
+                 // the internal routine. works best when aa.len() <= bb.len().
+                 fn mul_inner(ret: &mut [$ty; $n], aa: &[$ty], bb: &[$ty]) -> usize {
+                     use crate::num::bignum::FullOps;
+ 
+                     let mut retsz = 0;
+                     for (i, &a) in aa.iter().enumerate() {
+                         if a == 0 {
+                             continue;
+                         }
+                         let mut sz = bb.len();
+                         let mut carry = 0;
+                         for (j, &b) in bb.iter().enumerate() {
+                             let (c, v) = a.full_mul_add(b, ret[i + j], carry);
+                             ret[i + j] = v;
+                             carry = c;
+                         }
+                         if carry > 0 {
+                             ret[i + sz] = carry;
+                             sz += 1;
+                         }
+                         if retsz < i + sz {
+                             retsz = i + sz;
+                         }
+                     }
+                     retsz
+                 }
+ 
+                 let mut ret = [0; $n];
+                 let retsz = if self.size < other.len() {
+                     mul_inner(&mut ret, &self.digits(), other)
+                 } else {
+                     mul_inner(&mut ret, other, &self.digits())
+                 };
+                 self.base = ret;
+                 self.size = retsz;
+                 self
+             }
+ 
+             /// Divides itself by a digit-sized `other` and returns its own
+             /// mutable reference *and* the remainder.
+             pub fn div_rem_small(&mut self, other: $ty) -> (&mut $name, $ty) {
+                 use crate::num::bignum::FullOps;
+ 
+                 assert!(other > 0);
+ 
+                 let sz = self.size;
+                 let mut borrow = 0;
+                 for a in self.base[..sz].iter_mut().rev() {
+                     let (q, r) = (*a).full_div_rem(other, borrow);
+                     *a = q;
+                     borrow = r;
+                 }
+                 (self, borrow)
+             }
+ 
+             /// Divide self by another bignum, overwriting `q` with the quotient and `r` with the
+             /// remainder.
+             pub fn div_rem(&self, d: &$name, q: &mut $name, r: &mut $name) {
+                 // Stupid slow base-2 long division taken from
+                 // https://en.wikipedia.org/wiki/Division_algorithm
+                 // FIXME use a greater base ($ty) for the long division.
+                 assert!(!d.is_zero());
+                 let digitbits = <$ty>::BITS as usize;
+                 for digit in &mut q.base[..] {
+                     *digit = 0;
+                 }
+                 for digit in &mut r.base[..] {
+                     *digit = 0;
+                 }
+                 r.size = d.size;
+                 q.size = 1;
+                 let mut q_is_zero = true;
+                 let end = self.bit_length();
+                 for i in (0..end).rev() {
+                     r.mul_pow2(1);
+                     r.base[0] |= self.get_bit(i) as $ty;
+                     if &*r >= d {
+                         r.sub(d);
+                         // Set bit `i` of q to 1.
+                         let digit_idx = i / digitbits;
+                         let bit_idx = i % digitbits;
+                         if q_is_zero {
+                             q.size = digit_idx + 1;
+                             q_is_zero = false;
+                         }
+                         q.base[digit_idx] |= 1 << bit_idx;
+                     }
+                 }
+                 debug_assert!(q.base[q.size..].iter().all(|&d| d == 0));
+                 debug_assert!(r.base[r.size..].iter().all(|&d| d == 0));
+             }
+         }
+ 
+         impl crate::cmp::PartialEq for $name {
+             fn eq(&self, other: &$name) -> bool {
+                 self.base[..] == other.base[..]
+             }
+         }
+ 
+         impl crate::cmp::Eq for $name {}
+ 
+         impl crate::cmp::PartialOrd for $name {
+             fn partial_cmp(&self, other: &$name) -> crate::option::Option<crate::cmp::Ordering> {
+                 crate::option::Option::Some(self.cmp(other))
+             }
+         }
+ 
+         impl crate::cmp::Ord for $name {
+             fn cmp(&self, other: &$name) -> crate::cmp::Ordering {
+                 use crate::cmp::max;
+                 let sz = max(self.size, other.size);
+                 let lhs = self.base[..sz].iter().cloned().rev();
+                 let rhs = other.base[..sz].iter().cloned().rev();
+                 lhs.cmp(rhs)
+             }
+         }
+ 
+         impl crate::clone::Clone for $name {
+             fn clone(&self) -> Self {
+                 Self { size: self.size, base: self.base }
+             }
+         }
+ 
+         impl crate::fmt::Debug for $name {
+             fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result {
+                 let sz = if self.size < 1 { 1 } else { self.size };
+                 let digitlen = <$ty>::BITS as usize / 4;
+ 
+                 write!(f, "{:#x}", self.base[sz - 1])?;
+                 for &v in self.base[..sz - 1].iter().rev() {
+                     write!(f, "_{:01$x}", v, digitlen)?;
+                 }
+                 crate::result::Result::Ok(())
+             }
+         }
+     };
+ }
+ 
+ /// The digit type for `Big32x40`.
+ pub type Digit32 = u32;
+ 
+ define_bignum!(Big32x40: type=Digit32, n=40);
+ 
+ // this one is used for testing only.
+ #[doc(hidden)]
+ pub mod tests {
+     define_bignum!(Big8x3: type=u8, n=3);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/algorithm.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/algorithm.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/algorithm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/algorithm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,431 ----
+ //! The various algorithms from the paper.
+ 
+ use crate::cmp::min;
+ use crate::cmp::Ordering::{Equal, Greater, Less};
+ use crate::num::dec2flt::num::{self, Big};
+ use crate::num::dec2flt::rawfp::{self, fp_to_float, next_float, prev_float, RawFloat, Unpacked};
+ use crate::num::dec2flt::table;
+ use crate::num::diy_float::Fp;
+ 
+ /// Number of significand bits in Fp
+ const P: u32 = 64;
+ 
+ // We simply store the best approximation for *all* exponents, so the variable "h" and the
+ // associated conditions can be omitted. This trades performance for a couple kilobytes of space.
+ 
+ fn power_of_ten(e: i16) -> Fp {
+     assert!(e >= table::MIN_E);
+     let i = e - table::MIN_E;
+     let sig = table::POWERS.0[i as usize];
+     let exp = table::POWERS.1[i as usize];
+     Fp { f: sig, e: exp }
+ }
+ 
+ // In most architectures, floating point operations have an explicit bit size, therefore the
+ // precision of the computation is determined on a per-operation basis.
+ #[cfg(any(not(target_arch = "x86"), target_feature = "sse2"))]
+ mod fpu_precision {
+     pub fn set_precision<T>() {}
+ }
+ 
+ // On x86, the x87 FPU is used for float operations if the SSE/SSE2 extensions are not available.
+ // The x87 FPU operates with 80 bits of precision by default, which means that operations will
+ // round to 80 bits causing double rounding to happen when values are eventually represented as
+ // 32/64 bit float values. To overcome this, the FPU control word can be set so that the
+ // computations are performed in the desired precision.
+ #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))]
+ mod fpu_precision {
+     use crate::mem::size_of;
+ 
+     /// A structure used to preserve the original value of the FPU control word, so that it can be
+     /// restored when the structure is dropped.
+     ///
+     /// The x87 FPU is a 16-bits register whose fields are as follows:
+     ///
+     /// | 12-15 | 10-11 | 8-9 | 6-7 |  5 |  4 |  3 |  2 |  1 |  0 |
+     /// |------:|------:|----:|----:|---:|---:|---:|---:|---:|---:|
+     /// |       | RC    | PC  |     | PM | UM | OM | ZM | DM | IM |
+     ///
+     /// The documentation for all of the fields is available in the IA-32 Architectures Software
+     /// Developer's Manual (Volume 1).
+     ///
+     /// The only field which is relevant for the following code is PC, Precision Control. This
+     /// field determines the precision of the operations performed by the  FPU. It can be set to:
+     ///  - 0b00, single precision i.e., 32-bits
+     ///  - 0b10, double precision i.e., 64-bits
+     ///  - 0b11, double extended precision i.e., 80-bits (default state)
+     /// The 0b01 value is reserved and should not be used.
+     pub struct FPUControlWord(u16);
+ 
+     fn set_cw(cw: u16) {
+         // SAFETY: the `fldcw` instruction has been audited to be able to work correctly with
+         // any `u16`
+         unsafe {
+             asm!(
+                 "fldcw ({})",
+                 in(reg) &cw,
+                 // FIXME: We are using ATT syntax to support LLVM 8 and LLVM 9.
+                 options(att_syntax, nostack),
+             )
+         }
+     }
+ 
+     /// Sets the precision field of the FPU to `T` and returns a `FPUControlWord`.
+     pub fn set_precision<T>() -> FPUControlWord {
+         let mut cw = 0_u16;
+ 
+         // Compute the value for the Precision Control field that is appropriate for `T`.
+         let cw_precision = match size_of::<T>() {
+             4 => 0x0000, // 32 bits
+             8 => 0x0200, // 64 bits
+             _ => 0x0300, // default, 80 bits
+         };
+ 
+         // Get the original value of the control word to restore it later, when the
+         // `FPUControlWord` structure is dropped
+         // SAFETY: the `fnstcw` instruction has been audited to be able to work correctly with
+         // any `u16`
+         unsafe {
+             asm!(
+                 "fnstcw ({})",
+                 in(reg) &mut cw,
+                 // FIXME: We are using ATT syntax to support LLVM 8 and LLVM 9.
+                 options(att_syntax, nostack),
+             )
+         }
+ 
+         // Set the control word to the desired precision. This is achieved by masking away the old
+         // precision (bits 8 and 9, 0x300) and replacing it with the precision flag computed above.
+         set_cw((cw & 0xFCFF) | cw_precision);
+ 
+         FPUControlWord(cw)
+     }
+ 
+     impl Drop for FPUControlWord {
+         fn drop(&mut self) {
+             set_cw(self.0)
+         }
+     }
+ }
+ 
+ /// The fast path of Bellerophon using machine-sized integers and floats.
+ ///
+ /// This is extracted into a separate function so that it can be attempted before constructing
+ /// a bignum.
+ pub fn fast_path<T: RawFloat>(integral: &[u8], fractional: &[u8], e: i64) -> Option<T> {
+     let num_digits = integral.len() + fractional.len();
+     // log_10(f64::MAX_SIG) ~ 15.95. We compare the exact value to MAX_SIG near the end,
+     // this is just a quick, cheap rejection (and also frees the rest of the code from
+     // worrying about underflow).
+     if num_digits > 16 {
+         return None;
+     }
+     if e.abs() >= T::CEIL_LOG5_OF_MAX_SIG as i64 {
+         return None;
+     }
+     let f = num::from_str_unchecked(integral.iter().chain(fractional.iter()));
+     if f > T::MAX_SIG {
+         return None;
+     }
+ 
+     // The fast path crucially depends on arithmetic being rounded to the correct number of bits
+     // without any intermediate rounding. On x86 (without SSE or SSE2) this requires the precision
+     // of the x87 FPU stack to be changed so that it directly rounds to 64/32 bit.
+     // The `set_precision` function takes care of setting the precision on architectures which
+     // require setting it by changing the global state (like the control word of the x87 FPU).
+     let _cw = fpu_precision::set_precision::<T>();
+ 
+     // The case e < 0 cannot be folded into the other branch. Negative powers result in
+     // a repeating fractional part in binary, which are rounded, which causes real
+     // (and occasionally quite significant!) errors in the final result.
+     if e >= 0 {
+         Some(T::from_int(f) * T::short_fast_pow10(e as usize))
+     } else {
+         Some(T::from_int(f) / T::short_fast_pow10(e.abs() as usize))
+     }
+ }
+ 
+ /// Algorithm Bellerophon is trivial code justified by non-trivial numeric analysis.
+ ///
+ /// It rounds ``f`` to a float with 64 bit significand and multiplies it by the best approximation
+ /// of `10^e` (in the same floating point format). This is often enough to get the correct result.
+ /// However, when the result is close to halfway between two adjacent (ordinary) floats, the
+ /// compound rounding error from multiplying two approximation means the result may be off by a
+ /// few bits. When this happens, the iterative Algorithm R fixes things up.
+ ///
+ /// The hand-wavy "close to halfway" is made precise by the numeric analysis in the paper.
+ /// In the words of Clinger:
+ ///
+ /// > Slop, expressed in units of the least significant bit, is an inclusive bound for the error
+ /// > accumulated during the floating point calculation of the approximation to f * 10^e. (Slop is
+ /// > not a bound for the true error, but bounds the difference between the approximation z and
+ /// > the best possible approximation that uses p bits of significand.)
+ pub fn bellerophon<T: RawFloat>(f: &Big, e: i16) -> T {
+     let slop = if f <= &Big::from_u64(T::MAX_SIG) {
+         // The cases abs(e) < log5(2^N) are in fast_path()
+         if e >= 0 { 0 } else { 3 }
+     } else {
+         if e >= 0 { 1 } else { 4 }
+     };
+     let z = rawfp::big_to_fp(f).mul(&power_of_ten(e)).normalize();
+     let exp_p_n = 1 << (P - T::SIG_BITS as u32);
+     let lowbits: i64 = (z.f % exp_p_n) as i64;
+     // Is the slop large enough to make a difference when
+     // rounding to n bits?
+     if (lowbits - exp_p_n as i64 / 2).abs() <= slop {
+         algorithm_r(f, e, fp_to_float(z))
+     } else {
+         fp_to_float(z)
+     }
+ }
+ 
+ /// An iterative algorithm that improves a floating point approximation of `f * 10^e`.
+ ///
+ /// Each iteration gets one unit in the last place closer, which of course takes terribly long to
+ /// converge if `z0` is even mildly off. Luckily, when used as fallback for Bellerophon, the
+ /// starting approximation is off by at most one ULP.
+ fn algorithm_r<T: RawFloat>(f: &Big, e: i16, z0: T) -> T {
+     let mut z = z0;
+     loop {
+         let raw = z.unpack();
+         let (m, k) = (raw.sig, raw.k);
+         let mut x = f.clone();
+         let mut y = Big::from_u64(m);
+ 
+         // Find positive integers `x`, `y` such that `x / y` is exactly `(f * 10^e) / (m * 2^k)`.
+         // This not only avoids dealing with the signs of `e` and `k`, we also eliminate the
+         // power of two common to `10^e` and `2^k` to make the numbers smaller.
+         make_ratio(&mut x, &mut y, e, k);
+ 
+         let m_digits = [(m & 0xFF_FF_FF_FF) as u32, (m >> 32) as u32];
+         // This is written a bit awkwardly because our bignums don't support
+         // negative numbers, so we use the absolute value + sign information.
+         // The multiplication with m_digits can't overflow. If `x` or `y` are large enough that
+         // we need to worry about overflow, then they are also large enough that `make_ratio` has
+         // reduced the fraction by a factor of 2^64 or more.
+         let (d2, d_negative) = if x >= y {
+             // Don't need x any more, save a clone().
+             x.sub(&y).mul_pow2(1).mul_digits(&m_digits);
+             (x, false)
+         } else {
+             // Still need y - make a copy.
+             let mut y = y.clone();
+             y.sub(&x).mul_pow2(1).mul_digits(&m_digits);
+             (y, true)
+         };
+ 
+         if d2 < y {
+             let mut d2_double = d2;
+             d2_double.mul_pow2(1);
+             if m == T::MIN_SIG && d_negative && d2_double > y {
+                 z = prev_float(z);
+             } else {
+                 return z;
+             }
+         } else if d2 == y {
+             if m % 2 == 0 {
+                 if m == T::MIN_SIG && d_negative {
+                     z = prev_float(z);
+                 } else {
+                     return z;
+                 }
+             } else if d_negative {
+                 z = prev_float(z);
+             } else {
+                 z = next_float(z);
+             }
+         } else if d_negative {
+             z = prev_float(z);
+         } else {
+             z = next_float(z);
+         }
+     }
+ }
+ 
+ /// Given `x = f` and `y = m` where `f` represent input decimal digits as usual and `m` is the
+ /// significand of a floating point approximation, make the ratio `x / y` equal to
+ /// `(f * 10^e) / (m * 2^k)`, possibly reduced by a power of two both have in common.
+ fn make_ratio(x: &mut Big, y: &mut Big, e: i16, k: i16) {
+     let (e_abs, k_abs) = (e.abs() as usize, k.abs() as usize);
+     if e >= 0 {
+         if k >= 0 {
+             // x = f * 10^e, y = m * 2^k, except that we reduce the fraction by some power of two.
+             let common = min(e_abs, k_abs);
+             x.mul_pow5(e_abs).mul_pow2(e_abs - common);
+             y.mul_pow2(k_abs - common);
+         } else {
+             // x = f * 10^e * 2^abs(k), y = m
+             // This can't overflow because it requires positive `e` and negative `k`, which can
+             // only happen for values extremely close to 1, which means that `e` and `k` will be
+             // comparatively tiny.
+             x.mul_pow5(e_abs).mul_pow2(e_abs + k_abs);
+         }
+     } else {
+         if k >= 0 {
+             // x = f, y = m * 10^abs(e) * 2^k
+             // This can't overflow either, see above.
+             y.mul_pow5(e_abs).mul_pow2(k_abs + e_abs);
+         } else {
+             // x = f * 2^abs(k), y = m * 10^abs(e), again reducing by a common power of two.
+             let common = min(e_abs, k_abs);
+             x.mul_pow2(k_abs - common);
+             y.mul_pow5(e_abs).mul_pow2(e_abs - common);
+         }
+     }
+ }
+ 
+ /// Conceptually, Algorithm M is the simplest way to convert a decimal to a float.
+ ///
+ /// We form a ratio that is equal to `f * 10^e`, then throwing in powers of two until it gives
+ /// a valid float significand. The binary exponent `k` is the number of times we multiplied
+ /// numerator or denominator by two, i.e., at all times `f * 10^e` equals `(u / v) * 2^k`.
+ /// When we have found out significand, we only need to round by inspecting the remainder of the
+ /// division, which is done in helper functions further below.
+ ///
+ /// This algorithm is super slow, even with the optimization described in `quick_start()`.
+ /// However, it's the simplest of the algorithms to adapt for overflow, underflow, and subnormal
+ /// results. This implementation takes over when Bellerophon and Algorithm R are overwhelmed.
+ /// Detecting underflow and overflow is easy: The ratio still isn't an in-range significand,
+ /// yet the minimum/maximum exponent has been reached. In the case of overflow, we simply return
+ /// infinity.
+ ///
+ /// Handling underflow and subnormals is trickier. One big problem is that, with the minimum
+ /// exponent, the ratio might still be too large for a significand. See underflow() for details.
+ pub fn algorithm_m<T: RawFloat>(f: &Big, e: i16) -> T {
+     let mut u;
+     let mut v;
+     let e_abs = e.abs() as usize;
+     let mut k = 0;
+     if e < 0 {
+         u = f.clone();
+         v = Big::from_small(1);
+         v.mul_pow5(e_abs).mul_pow2(e_abs);
+     } else {
+         // FIXME possible optimization: generalize big_to_fp so that we can do the equivalent of
+         // fp_to_float(big_to_fp(u)) here, only without the double rounding.
+         u = f.clone();
+         u.mul_pow5(e_abs).mul_pow2(e_abs);
+         v = Big::from_small(1);
+     }
+     quick_start::<T>(&mut u, &mut v, &mut k);
+     let mut rem = Big::from_small(0);
+     let mut x = Big::from_small(0);
+     let min_sig = Big::from_u64(T::MIN_SIG);
+     let max_sig = Big::from_u64(T::MAX_SIG);
+     loop {
+         u.div_rem(&v, &mut x, &mut rem);
+         if k == T::MIN_EXP_INT {
+             // We have to stop at the minimum exponent, if we wait until `k < T::MIN_EXP_INT`,
+             // then we'd be off by a factor of two. Unfortunately this means we have to special-
+             // case normal numbers with the minimum exponent.
+             // FIXME find a more elegant formulation, but run the `tiny-pow10` test to make sure
+             // that it's actually correct!
+             if x >= min_sig && x <= max_sig {
+                 break;
+             }
+             return underflow(x, v, rem);
+         }
+         if k > T::MAX_EXP_INT {
+             return T::INFINITY;
+         }
+         if x < min_sig {
+             u.mul_pow2(1);
+             k -= 1;
+         } else if x > max_sig {
+             v.mul_pow2(1);
+             k += 1;
+         } else {
+             break;
+         }
+     }
+     let q = num::to_u64(&x);
+     let z = rawfp::encode_normal(Unpacked::new(q, k));
+     round_by_remainder(v, rem, q, z)
+ }
+ 
+ /// Skips over most Algorithm M iterations by checking the bit length.
+ fn quick_start<T: RawFloat>(u: &mut Big, v: &mut Big, k: &mut i16) {
+     // The bit length is an estimate of the base two logarithm, and log(u / v) = log(u) - log(v).
+     // The estimate is off by at most 1, but always an under-estimate, so the error on log(u)
+     // and log(v) are of the same sign and cancel out (if both are large). Therefore the error
+     // for log(u / v) is at most one as well.
+     // The target ratio is one where u/v is in an in-range significand. Thus our termination
+     // condition is log2(u / v) being the significand bits, plus/minus one.
+     // FIXME Looking at the second bit could improve the estimate and avoid some more divisions.
+     let target_ratio = T::SIG_BITS as i16;
+     let log2_u = u.bit_length() as i16;
+     let log2_v = v.bit_length() as i16;
+     let mut u_shift: i16 = 0;
+     let mut v_shift: i16 = 0;
+     assert!(*k == 0);
+     loop {
+         if *k == T::MIN_EXP_INT {
+             // Underflow or subnormal. Leave it to the main function.
+             break;
+         }
+         if *k == T::MAX_EXP_INT {
+             // Overflow. Leave it to the main function.
+             break;
+         }
+         let log2_ratio = (log2_u + u_shift) - (log2_v + v_shift);
+         if log2_ratio < target_ratio - 1 {
+             u_shift += 1;
+             *k -= 1;
+         } else if log2_ratio > target_ratio + 1 {
+             v_shift += 1;
+             *k += 1;
+         } else {
+             break;
+         }
+     }
+     u.mul_pow2(u_shift as usize);
+     v.mul_pow2(v_shift as usize);
+ }
+ 
+ fn underflow<T: RawFloat>(x: Big, v: Big, rem: Big) -> T {
+     if x < Big::from_u64(T::MIN_SIG) {
+         let q = num::to_u64(&x);
+         let z = rawfp::encode_subnormal(q);
+         return round_by_remainder(v, rem, q, z);
+     }
+     // Ratio isn't an in-range significand with the minimum exponent, so we need to round off
+     // excess bits and adjust the exponent accordingly. The real value now looks like this:
+     //
+     //        x        lsb
+     // /--------------\/
+     // 1010101010101010.10101010101010 * 2^k
+     // \-----/\-------/ \------------/
+     //    q     trunc.    (represented by rem)
+     //
+     // Therefore, when the rounded-off bits are != 0.5 ULP, they decide the rounding
+     // on their own. When they are equal and the remainder is non-zero, the value still
+     // needs to be rounded up. Only when the rounded off bits are 1/2 and the remainder
+     // is zero, we have a half-to-even situation.
+     let bits = x.bit_length();
+     let lsb = bits - T::SIG_BITS as usize;
+     let q = num::get_bits(&x, lsb, bits);
+     let k = T::MIN_EXP_INT + lsb as i16;
+     let z = rawfp::encode_normal(Unpacked::new(q, k));
+     let q_even = q % 2 == 0;
+     match num::compare_with_half_ulp(&x, lsb) {
+         Greater => next_float(z),
+         Less => z,
+         Equal if rem.is_zero() && q_even => z,
+         Equal => next_float(z),
+     }
+ }
+ 
+ /// Ordinary round-to-even, obfuscated by having to round based on the remainder of a division.
+ fn round_by_remainder<T: RawFloat>(v: Big, r: Big, q: u64, z: T) -> T {
+     let mut v_minus_r = v;
+     v_minus_r.sub(&r);
+     if r < v_minus_r {
+         z
+     } else if r > v_minus_r {
+         next_float(z)
+     } else if q % 2 == 0 {
+         z
+     } else {
+         next_float(z)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,356 ----
+ //! Converting decimal strings into IEEE 754 binary floating point numbers.
+ //!
+ //! # Problem statement
+ //!
+ //! We are given a decimal string such as `12.34e56`. This string consists of integral (`12`),
+ //! fractional (`45`), and exponent (`56`) parts. All parts are optional and interpreted as zero
+ //! when missing.
+ //!
+ //! We seek the IEEE 754 floating point number that is closest to the exact value of the decimal
+ //! string. It is well-known that many decimal strings do not have terminating representations in
+ //! base two, so we round to 0.5 units in the last place (in other words, as well as possible).
+ //! Ties, decimal values exactly half-way between two consecutive floats, are resolved with the
+ //! half-to-even strategy, also known as banker's rounding.
+ //!
+ //! Needless to say, this is quite hard, both in terms of implementation complexity and in terms
+ //! of CPU cycles taken.
+ //!
+ //! # Implementation
+ //!
+ //! First, we ignore signs. Or rather, we remove it at the very beginning of the conversion
+ //! process and re-apply it at the very end. This is correct in all edge cases since IEEE
+ //! floats are symmetric around zero, negating one simply flips the first bit.
+ //!
+ //! Then we remove the decimal point by adjusting the exponent: Conceptually, `12.34e56` turns
+ //! into `1234e54`, which we describe with a positive integer `f = 1234` and an integer `e = 54`.
+ //! The `(f, e)` representation is used by almost all code past the parsing stage.
+ //!
+ //! We then try a long chain of progressively more general and expensive special cases using
+ //! machine-sized integers and small, fixed-sized floating point numbers (first `f32`/`f64`, then
+ //! a type with 64 bit significand, `Fp`). When all these fail, we bite the bullet and resort to a
+ //! simple but very slow algorithm that involved computing `f * 10^e` fully and doing an iterative
+ //! search for the best approximation.
+ //!
+ //! Primarily, this module and its children implement the algorithms described in:
+ //! "How to Read Floating Point Numbers Accurately" by William D. Clinger,
+ //! available online: <http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.45.4152>
+ //!
+ //! In addition, there are numerous helper functions that are used in the paper but not available
+ //! in Rust (or at least in core). Our version is additionally complicated by the need to handle
+ //! overflow and underflow and the desire to handle subnormal numbers. Bellerophon and
+ //! Algorithm R have trouble with overflow, subnormals, and underflow. We conservatively switch to
+ //! Algorithm M (with the modifications described in section 8 of the paper) well before the
+ //! inputs get into the critical region.
+ //!
+ //! Another aspect that needs attention is the ``RawFloat`` trait by which almost all functions
+ //! are parametrized. One might think that it's enough to parse to `f64` and cast the result to
+ //! `f32`. Unfortunately this is not the world we live in, and this has nothing to do with using
+ //! base two or half-to-even rounding.
+ //!
+ //! Consider for example two types `d2` and `d4` representing a decimal type with two decimal
+ //! digits and four decimal digits each and take "0.01499" as input. Let's use half-up rounding.
+ //! Going directly to two decimal digits gives `0.01`, but if we round to four digits first,
+ //! we get `0.0150`, which is then rounded up to `0.02`. The same principle applies to other
+ //! operations as well, if you want 0.5 ULP accuracy you need to do *everything* in full precision
+ //! and round *exactly once, at the end*, by considering all truncated bits at once.
+ //!
+ //! FIXME: Although some code duplication is necessary, perhaps parts of the code could be shuffled
+ //! around such that less code is duplicated. Large parts of the algorithms are independent of the
+ //! float type to output, or only needs access to a few constants, which could be passed in as
+ //! parameters.
+ //!
+ //! # Other
+ //!
+ //! The conversion should *never* panic. There are assertions and explicit panics in the code,
+ //! but they should never be triggered and only serve as internal sanity checks. Any panics should
+ //! be considered a bug.
+ //!
+ //! There are unit tests but they are woefully inadequate at ensuring correctness, they only cover
+ //! a small percentage of possible errors. Far more extensive tests are located in the directory
+ //! `src/etc/test-float-parse` as a Python script.
+ //!
+ //! A note on integer overflow: Many parts of this file perform arithmetic with the decimal
+ //! exponent `e`. Primarily, we shift the decimal point around: Before the first decimal digit,
+ //! after the last decimal digit, and so on. This could overflow if done carelessly. We rely on
+ //! the parsing submodule to only hand out sufficiently small exponents, where "sufficient" means
+ //! "such that the exponent +/- the number of decimal digits fits into a 64 bit integer".
+ //! Larger exponents are accepted, but we don't do arithmetic with them, they are immediately
+ //! turned into {positive,negative} {zero,infinity}.
+ 
+ #![doc(hidden)]
+ #![unstable(
+     feature = "dec2flt",
+     reason = "internal routines only exposed for testing",
+     issue = "none"
+ )]
+ 
+ use crate::fmt;
+ use crate::str::FromStr;
+ 
+ use self::num::digits_to_big;
+ use self::parse::{parse_decimal, Decimal, ParseResult, Sign};
+ use self::rawfp::RawFloat;
+ 
+ mod algorithm;
+ mod num;
+ mod table;
+ // These two have their own tests.
+ pub mod parse;
+ pub mod rawfp;
+ 
+ macro_rules! from_str_float_impl {
+     ($t:ty) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl FromStr for $t {
+             type Err = ParseFloatError;
+ 
+             /// Converts a string in base 10 to a float.
+             /// Accepts an optional decimal exponent.
+             ///
+             /// This function accepts strings such as
+             ///
+             /// * '3.14'
+             /// * '-3.14'
+             /// * '2.5E10', or equivalently, '2.5e10'
+             /// * '2.5E-10'
+             /// * '5.'
+             /// * '.5', or, equivalently, '0.5'
+             /// * 'inf', '-inf', 'NaN'
+             ///
+             /// Leading and trailing whitespace represent an error.
+             ///
+             /// # Grammar
+             ///
+             /// All strings that adhere to the following [EBNF] grammar
+             /// will result in an [`Ok`] being returned:
+             ///
+             /// ```txt
+             /// Float  ::= Sign? ( 'inf' | 'NaN' | Number )
+             /// Number ::= ( Digit+ |
+             ///              Digit+ '.' Digit* |
+             ///              Digit* '.' Digit+ ) Exp?
+             /// Exp    ::= [eE] Sign? Digit+
+             /// Sign   ::= [+-]
+             /// Digit  ::= [0-9]
+             /// ```
+             ///
+             /// [EBNF]: https://www.w3.org/TR/REC-xml/#sec-notation
+             ///
+             /// # Known bugs
+             ///
+             /// In some situations, some strings that should create a valid float
+             /// instead return an error. See [issue #31407] for details.
+             ///
+             /// [issue #31407]: https://github.com/rust-lang/rust/issues/31407
+             ///
+             /// # Arguments
+             ///
+             /// * src - A string
+             ///
+             /// # Return value
+             ///
+             /// `Err(ParseFloatError)` if the string did not represent a valid
+             /// number. Otherwise, `Ok(n)` where `n` is the floating-point
+             /// number represented by `src`.
+             #[inline]
+             fn from_str(src: &str) -> Result<Self, ParseFloatError> {
+                 dec2flt(src)
+             }
+         }
+     };
+ }
+ from_str_float_impl!(f32);
+ from_str_float_impl!(f64);
+ 
+ /// An error which can be returned when parsing a float.
+ ///
+ /// This error is used as the error type for the [`FromStr`] implementation
+ /// for [`f32`] and [`f64`].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// use std::str::FromStr;
+ ///
+ /// if let Err(e) = f64::from_str("a.12") {
+ ///     println!("Failed conversion to f64: {}", e);
+ /// }
+ /// ```
+ #[derive(Debug, Clone, PartialEq, Eq)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct ParseFloatError {
+     kind: FloatErrorKind,
+ }
+ 
+ #[derive(Debug, Clone, PartialEq, Eq)]
+ enum FloatErrorKind {
+     Empty,
+     Invalid,
+ }
+ 
+ impl ParseFloatError {
+     #[unstable(
+         feature = "int_error_internals",
+         reason = "available through Error trait and this method should \
+                   not be exposed publicly",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     pub fn __description(&self) -> &str {
+         match self.kind {
+             FloatErrorKind::Empty => "cannot parse float from empty string",
+             FloatErrorKind::Invalid => "invalid float literal",
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Display for ParseFloatError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.__description().fmt(f)
+     }
+ }
+ 
+ fn pfe_empty() -> ParseFloatError {
+     ParseFloatError { kind: FloatErrorKind::Empty }
+ }
+ 
+ fn pfe_invalid() -> ParseFloatError {
+     ParseFloatError { kind: FloatErrorKind::Invalid }
+ }
+ 
+ /// Splits a decimal string into sign and the rest, without inspecting or validating the rest.
+ fn extract_sign(s: &str) -> (Sign, &str) {
+     match s.as_bytes()[0] {
+         b'+' => (Sign::Positive, &s[1..]),
+         b'-' => (Sign::Negative, &s[1..]),
+         // If the string is invalid, we never use the sign, so we don't need to validate here.
+         _ => (Sign::Positive, s),
+     }
+ }
+ 
+ /// Converts a decimal string into a floating point number.
+ fn dec2flt<T: RawFloat>(s: &str) -> Result<T, ParseFloatError> {
+     if s.is_empty() {
+         return Err(pfe_empty());
+     }
+     let (sign, s) = extract_sign(s);
+     let flt = match parse_decimal(s) {
+         ParseResult::Valid(decimal) => convert(decimal)?,
+         ParseResult::ShortcutToInf => T::INFINITY,
+         ParseResult::ShortcutToZero => T::ZERO,
+         ParseResult::Invalid => match s {
+             "inf" => T::INFINITY,
+             "NaN" => T::NAN,
+             _ => {
+                 return Err(pfe_invalid());
+             }
+         },
+     };
+ 
+     match sign {
+         Sign::Positive => Ok(flt),
+         Sign::Negative => Ok(-flt),
+     }
+ }
+ 
+ /// The main workhorse for the decimal-to-float conversion: Orchestrate all the preprocessing
+ /// and figure out which algorithm should do the actual conversion.
+ fn convert<T: RawFloat>(mut decimal: Decimal<'_>) -> Result<T, ParseFloatError> {
+     simplify(&mut decimal);
+     if let Some(x) = trivial_cases(&decimal) {
+         return Ok(x);
+     }
+     // Remove/shift out the decimal point.
+     let e = decimal.exp - decimal.fractional.len() as i64;
+     if let Some(x) = algorithm::fast_path(decimal.integral, decimal.fractional, e) {
+         return Ok(x);
+     }
+     // Big32x40 is limited to 1280 bits, which translates to about 385 decimal digits.
+     // If we exceed this, we'll crash, so we error out before getting too close (within 10^10).
+     let upper_bound = bound_intermediate_digits(&decimal, e);
+     if upper_bound > 375 {
+         return Err(pfe_invalid());
+     }
+     let f = digits_to_big(decimal.integral, decimal.fractional);
+ 
+     // Now the exponent certainly fits in 16 bit, which is used throughout the main algorithms.
+     let e = e as i16;
+     // FIXME These bounds are rather conservative. A more careful analysis of the failure modes
+     // of Bellerophon could allow using it in more cases for a massive speed up.
+     let exponent_in_range = table::MIN_E <= e && e <= table::MAX_E;
+     let value_in_range = upper_bound <= T::MAX_NORMAL_DIGITS as u64;
+     if exponent_in_range && value_in_range {
+         Ok(algorithm::bellerophon(&f, e))
+     } else {
+         Ok(algorithm::algorithm_m(&f, e))
+     }
+ }
+ 
+ // As written, this optimizes badly (see #27130, though it refers to an old version of the code).
+ // `inline(always)` is a workaround for that. There are only two call sites overall and it doesn't
+ // make code size worse.
+ 
+ /// Strip zeros where possible, even when this requires changing the exponent
+ #[inline(always)]
+ fn simplify(decimal: &mut Decimal<'_>) {
+     let is_zero = &|&&d: &&u8| -> bool { d == b'0' };
+     // Trimming these zeros does not change anything but may enable the fast path (< 15 digits).
+     let leading_zeros = decimal.integral.iter().take_while(is_zero).count();
+     decimal.integral = &decimal.integral[leading_zeros..];
+     let trailing_zeros = decimal.fractional.iter().rev().take_while(is_zero).count();
+     let end = decimal.fractional.len() - trailing_zeros;
+     decimal.fractional = &decimal.fractional[..end];
+     // Simplify numbers of the form 0.0...x and x...0.0, adjusting the exponent accordingly.
+     // This may not always be a win (possibly pushes some numbers out of the fast path), but it
+     // simplifies other parts significantly (notably, approximating the magnitude of the value).
+     if decimal.integral.is_empty() {
+         let leading_zeros = decimal.fractional.iter().take_while(is_zero).count();
+         decimal.fractional = &decimal.fractional[leading_zeros..];
+         decimal.exp -= leading_zeros as i64;
+     } else if decimal.fractional.is_empty() {
+         let trailing_zeros = decimal.integral.iter().rev().take_while(is_zero).count();
+         let end = decimal.integral.len() - trailing_zeros;
+         decimal.integral = &decimal.integral[..end];
+         decimal.exp += trailing_zeros as i64;
+     }
+ }
+ 
+ /// Returns a quick-an-dirty upper bound on the size (log10) of the largest value that Algorithm R
+ /// and Algorithm M will compute while working on the given decimal.
+ fn bound_intermediate_digits(decimal: &Decimal<'_>, e: i64) -> u64 {
+     // We don't need to worry too much about overflow here thanks to trivial_cases() and the
+     // parser, which filter out the most extreme inputs for us.
+     let f_len: u64 = decimal.integral.len() as u64 + decimal.fractional.len() as u64;
+     if e >= 0 {
+         // In the case e >= 0, both algorithms compute about `f * 10^e`. Algorithm R proceeds to
+         // do some complicated calculations with this but we can ignore that for the upper bound
+         // because it also reduces the fraction beforehand, so we have plenty of buffer there.
+         f_len + (e as u64)
+     } else {
+         // If e < 0, Algorithm R does roughly the same thing, but Algorithm M differs:
+         // It tries to find a positive number k such that `f << k / 10^e` is an in-range
+         // significand. This will result in about `2^53 * f * 10^e` < `10^17 * f * 10^e`.
+         // One input that triggers this is 0.33...33 (375 x 3).
+         f_len + (e.abs() as u64) + 17
+     }
+ }
+ 
+ /// Detects obvious overflows and underflows without even looking at the decimal digits.
+ fn trivial_cases<T: RawFloat>(decimal: &Decimal<'_>) -> Option<T> {
+     // There were zeros but they were stripped by simplify()
+     if decimal.integral.is_empty() && decimal.fractional.is_empty() {
+         return Some(T::ZERO);
+     }
+     // This is a crude approximation of ceil(log10(the real value)). We don't need to worry too
+     // much about overflow here because the input length is tiny (at least compared to 2^64) and
+     // the parser already handles exponents whose absolute value is greater than 10^18
+     // (which is still 10^19 short of 2^64).
+     let max_place = decimal.exp + decimal.integral.len() as i64;
+     if max_place > T::INF_CUTOFF {
+         return Some(T::INFINITY);
+     } else if max_place < T::ZERO_CUTOFF {
+         return Some(T::ZERO);
+     }
+     None
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/num.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/num.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/num.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/num.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,81 ----
+ //! Utility functions for bignums that don't make too much sense to turn into methods.
+ 
+ // FIXME This module's name is a bit unfortunate, since other modules also import `core::num`.
+ 
+ use crate::cmp::Ordering::{self, Equal, Greater, Less};
+ 
+ pub use crate::num::bignum::Big32x40 as Big;
+ 
+ /// Test whether truncating all bits less significant than `ones_place` introduces
+ /// a relative error less, equal, or greater than 0.5 ULP.
+ pub fn compare_with_half_ulp(f: &Big, ones_place: usize) -> Ordering {
+     if ones_place == 0 {
+         return Less;
+     }
+     let half_bit = ones_place - 1;
+     if f.get_bit(half_bit) == 0 {
+         // < 0.5 ULP
+         return Less;
+     }
+     // If all remaining bits are zero, it's = 0.5 ULP, otherwise > 0.5
+     // If there are no more bits (half_bit == 0), the below also correctly returns Equal.
+     for i in 0..half_bit {
+         if f.get_bit(i) == 1 {
+             return Greater;
+         }
+     }
+     Equal
+ }
+ 
+ /// Converts an ASCII string containing only decimal digits to a `u64`.
+ ///
+ /// Does not perform checks for overflow or invalid characters, so if the caller is not careful,
+ /// the result is bogus and can panic (though it won't be `unsafe`). Additionally, empty strings
+ /// are treated as zero. This function exists because
+ ///
+ /// 1. using `FromStr` on `&[u8]` requires `from_utf8_unchecked`, which is bad, and
+ /// 2. piecing together the results of `integral.parse()` and `fractional.parse()` is
+ ///    more complicated than this entire function.
+ pub fn from_str_unchecked<'a, T>(bytes: T) -> u64
+ where
+     T: IntoIterator<Item = &'a u8>,
+ {
+     let mut result = 0;
+     for &c in bytes {
+         result = result * 10 + (c - b'0') as u64;
+     }
+     result
+ }
+ 
+ /// Converts a string of ASCII digits into a bignum.
+ ///
+ /// Like `from_str_unchecked`, this function relies on the parser to weed out non-digits.
+ pub fn digits_to_big(integral: &[u8], fractional: &[u8]) -> Big {
+     let mut f = Big::from_small(0);
+     for &c in integral.iter().chain(fractional) {
+         let n = (c - b'0') as u32;
+         f.mul_small(10);
+         f.add_small(n);
+     }
+     f
+ }
+ 
+ /// Unwraps a bignum into a 64 bit integer. Panics if the number is too large.
+ pub fn to_u64(x: &Big) -> u64 {
+     assert!(x.bit_length() < 64);
+     let d = x.digits();
+     if d.len() < 2 { d[0] as u64 } else { (d[1] as u64) << 32 | d[0] as u64 }
+ }
+ 
+ /// Extracts a range of bits.
+ 
+ /// Index 0 is the least significant bit and the range is half-open as usual.
+ /// Panics if asked to extract more bits than fit into the return type.
+ pub fn get_bits(x: &Big, start: usize, end: usize) -> u64 {
+     assert!(end - start <= 64);
+     let mut result: u64 = 0;
+     for i in (start..end).rev() {
+         result = result << 1 | x.get_bit(i) as u64;
+     }
+     result
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/parse.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/parse.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/parse.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/parse.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,124 ----
+ //! Validating and decomposing a decimal string of the form:
+ //!
+ //! `(digits | digits? '.'? digits?) (('e' | 'E') ('+' | '-')? digits)?`
+ //!
+ //! In other words, standard floating-point syntax, with two exceptions: No sign, and no
+ //! handling of "inf" and "NaN". These are handled by the driver function (super::dec2flt).
+ //!
+ //! Although recognizing valid inputs is relatively easy, this module also has to reject the
+ //! countless invalid variations, never panic, and perform numerous checks that the other
+ //! modules rely on to not panic (or overflow) in turn.
+ //! To make matters worse, all that happens in a single pass over the input.
+ //! So, be careful when modifying anything, and double-check with the other modules.
+ use self::ParseResult::{Invalid, ShortcutToInf, ShortcutToZero, Valid};
+ use super::num;
+ 
+ #[derive(Debug)]
+ pub enum Sign {
+     Positive,
+     Negative,
+ }
+ 
+ #[derive(Debug, PartialEq, Eq)]
+ /// The interesting parts of a decimal string.
+ pub struct Decimal<'a> {
+     pub integral: &'a [u8],
+     pub fractional: &'a [u8],
+     /// The decimal exponent, guaranteed to have fewer than 18 decimal digits.
+     pub exp: i64,
+ }
+ 
+ impl<'a> Decimal<'a> {
+     pub fn new(integral: &'a [u8], fractional: &'a [u8], exp: i64) -> Decimal<'a> {
+         Decimal { integral, fractional, exp }
+     }
+ }
+ 
+ #[derive(Debug, PartialEq, Eq)]
+ pub enum ParseResult<'a> {
+     Valid(Decimal<'a>),
+     ShortcutToInf,
+     ShortcutToZero,
+     Invalid,
+ }
+ 
+ /// Checks if the input string is a valid floating point number and if so, locate the integral
+ /// part, the fractional part, and the exponent in it. Does not handle signs.
+ pub fn parse_decimal(s: &str) -> ParseResult<'_> {
+     if s.is_empty() {
+         return Invalid;
+     }
+ 
+     let s = s.as_bytes();
+     let (integral, s) = eat_digits(s);
+ 
+     match s.first() {
+         None => Valid(Decimal::new(integral, b"", 0)),
+         Some(&b'e' | &b'E') => {
+             if integral.is_empty() {
+                 return Invalid; // No digits before 'e'
+             }
+ 
+             parse_exp(integral, b"", &s[1..])
+         }
+         Some(&b'.') => {
+             let (fractional, s) = eat_digits(&s[1..]);
+             if integral.is_empty() && fractional.is_empty() {
+                 // We require at least a single digit before or after the point.
+                 return Invalid;
+             }
+ 
+             match s.first() {
+                 None => Valid(Decimal::new(integral, fractional, 0)),
+                 Some(&b'e' | &b'E') => parse_exp(integral, fractional, &s[1..]),
+                 _ => Invalid, // Trailing junk after fractional part
+             }
+         }
+         _ => Invalid, // Trailing junk after first digit string
+     }
+ }
+ 
+ /// Carves off decimal digits up to the first non-digit character.
+ fn eat_digits(s: &[u8]) -> (&[u8], &[u8]) {
+     let mut i = 0;
+     while i < s.len() && b'0' <= s[i] && s[i] <= b'9' {
+         i += 1;
+     }
+     (&s[..i], &s[i..])
+ }
+ 
+ /// Exponent extraction and error checking.
+ fn parse_exp<'a>(integral: &'a [u8], fractional: &'a [u8], rest: &'a [u8]) -> ParseResult<'a> {
+     let (sign, rest) = match rest.first() {
+         Some(&b'-') => (Sign::Negative, &rest[1..]),
+         Some(&b'+') => (Sign::Positive, &rest[1..]),
+         _ => (Sign::Positive, rest),
+     };
+     let (mut number, trailing) = eat_digits(rest);
+     if !trailing.is_empty() {
+         return Invalid; // Trailing junk after exponent
+     }
+     if number.is_empty() {
+         return Invalid; // Empty exponent
+     }
+     // At this point, we certainly have a valid string of digits. It may be too long to put into
+     // an `i64`, but if it's that huge, the input is certainly zero or infinity. Since each zero
+     // in the decimal digits only adjusts the exponent by +/- 1, at exp = 10^18 the input would
+     // have to be 17 exabyte (!) of zeros to get even remotely close to being finite.
+     // This is not exactly a use case we need to cater to.
+     while number.first() == Some(&b'0') {
+         number = &number[1..];
+     }
+     if number.len() >= 18 {
+         return match sign {
+             Sign::Positive => ShortcutToInf,
+             Sign::Negative => ShortcutToZero,
+         };
+     }
+     let abs_exp = num::from_str_unchecked(number);
+     let e = match sign {
+         Sign::Positive => abs_exp as i64,
+         Sign::Negative => -(abs_exp as i64),
+     };
+     Valid(Decimal::new(integral, fractional, e))
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/rawfp.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/rawfp.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/rawfp.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/rawfp.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,363 ----
+ //! Bit fiddling on positive IEEE 754 floats. Negative numbers aren't and needn't be handled.
+ //! Normal floating point numbers have a canonical representation as (frac, exp) such that the
+ //! value is 2<sup>exp</sup> * (1 + sum(frac[N-i] / 2<sup>i</sup>)) where N is the number of bits.
+ //! Subnormals are slightly different and weird, but the same principle applies.
+ //!
+ //! Here, however, we represent them as (sig, k) with f positive, such that the value is f *
+ //! 2<sup>e</sup>. Besides making the "hidden bit" explicit, this changes the exponent by the
+ //! so-called mantissa shift.
+ //!
+ //! Put another way, normally floats are written as (1) but here they are written as (2):
+ //!
+ //! 1. `1.101100...11 * 2^m`
+ //! 2. `1101100...11 * 2^n`
+ //!
+ //! We call (1) the **fractional representation** and (2) the **integral representation**.
+ //!
+ //! Many functions in this module only handle normal numbers. The dec2flt routines conservatively
+ //! take the universally-correct slow path (Algorithm M) for very small and very large numbers.
+ //! That algorithm needs only next_float() which does handle subnormals and zeros.
+ use crate::cmp::Ordering::{Equal, Greater, Less};
+ use crate::convert::{TryFrom, TryInto};
+ use crate::fmt::{Debug, LowerExp};
+ use crate::num::dec2flt::num::{self, Big};
+ use crate::num::dec2flt::table;
+ use crate::num::diy_float::Fp;
+ use crate::num::FpCategory;
+ use crate::num::FpCategory::{Infinite, Nan, Normal, Subnormal, Zero};
+ use crate::ops::{Add, Div, Mul, Neg};
+ 
+ #[derive(Copy, Clone, Debug)]
+ pub struct Unpacked {
+     pub sig: u64,
+     pub k: i16,
+ }
+ 
+ impl Unpacked {
+     pub fn new(sig: u64, k: i16) -> Self {
+         Unpacked { sig, k }
+     }
+ }
+ 
+ /// A helper trait to avoid duplicating basically all the conversion code for `f32` and `f64`.
+ ///
+ /// See the parent module's doc comment for why this is necessary.
+ ///
+ /// Should **never ever** be implemented for other types or be used outside the dec2flt module.
+ pub trait RawFloat:
+     Copy + Debug + LowerExp + Mul<Output = Self> + Div<Output = Self> + Neg<Output = Self>
+ {
+     const INFINITY: Self;
+     const NAN: Self;
+     const ZERO: Self;
+ 
+     /// Type used by `to_bits` and `from_bits`.
+     type Bits: Add<Output = Self::Bits> + From<u8> + TryFrom<u64>;
+ 
+     /// Performs a raw transmutation to an integer.
+     fn to_bits(self) -> Self::Bits;
+ 
+     /// Performs a raw transmutation from an integer.
+     fn from_bits(v: Self::Bits) -> Self;
+ 
+     /// Returns the category that this number falls into.
+     fn classify(self) -> FpCategory;
+ 
+     /// Returns the mantissa, exponent and sign as integers.
+     fn integer_decode(self) -> (u64, i16, i8);
+ 
+     /// Decodes the float.
+     fn unpack(self) -> Unpacked;
+ 
+     /// Casts from a small integer that can be represented exactly. Panic if the integer can't be
+     /// represented, the other code in this module makes sure to never let that happen.
+     fn from_int(x: u64) -> Self;
+ 
+     /// Gets the value 10<sup>e</sup> from a pre-computed table.
+     /// Panics for `e >= CEIL_LOG5_OF_MAX_SIG`.
+     fn short_fast_pow10(e: usize) -> Self;
+ 
+     /// What the name says. It's easier to hard code than juggling intrinsics and
+     /// hoping LLVM constant folds it.
+     const CEIL_LOG5_OF_MAX_SIG: i16;
+ 
+     // A conservative bound on the decimal digits of inputs that can't produce overflow or zero or
+     /// subnormals. Probably the decimal exponent of the maximum normal value, hence the name.
+     const MAX_NORMAL_DIGITS: usize;
+ 
+     /// When the most significant decimal digit has a place value greater than this, the number
+     /// is certainly rounded to infinity.
+     const INF_CUTOFF: i64;
+ 
+     /// When the most significant decimal digit has a place value less than this, the number
+     /// is certainly rounded to zero.
+     const ZERO_CUTOFF: i64;
+ 
+     /// The number of bits in the exponent.
+     const EXP_BITS: u8;
+ 
+     /// The number of bits in the significand, *including* the hidden bit.
+     const SIG_BITS: u8;
+ 
+     /// The number of bits in the significand, *excluding* the hidden bit.
+     const EXPLICIT_SIG_BITS: u8;
+ 
+     /// The maximum legal exponent in fractional representation.
+     const MAX_EXP: i16;
+ 
+     /// The minimum legal exponent in fractional representation, excluding subnormals.
+     const MIN_EXP: i16;
+ 
+     /// `MAX_EXP` for integral representation, i.e., with the shift applied.
+     const MAX_EXP_INT: i16;
+ 
+     /// `MAX_EXP` encoded (i.e., with offset bias)
+     const MAX_ENCODED_EXP: i16;
+ 
+     /// `MIN_EXP` for integral representation, i.e., with the shift applied.
+     const MIN_EXP_INT: i16;
+ 
+     /// The maximum normalized significand in integral representation.
+     const MAX_SIG: u64;
+ 
+     /// The minimal normalized significand in integral representation.
+     const MIN_SIG: u64;
+ }
+ 
+ // Mostly a workaround for #34344.
+ macro_rules! other_constants {
+     ($type: ident) => {
+         const EXPLICIT_SIG_BITS: u8 = Self::SIG_BITS - 1;
+         const MAX_EXP: i16 = (1 << (Self::EXP_BITS - 1)) - 1;
+         const MIN_EXP: i16 = -<Self as RawFloat>::MAX_EXP + 1;
+         const MAX_EXP_INT: i16 = <Self as RawFloat>::MAX_EXP - (Self::SIG_BITS as i16 - 1);
+         const MAX_ENCODED_EXP: i16 = (1 << Self::EXP_BITS) - 1;
+         const MIN_EXP_INT: i16 = <Self as RawFloat>::MIN_EXP - (Self::SIG_BITS as i16 - 1);
+         const MAX_SIG: u64 = (1 << Self::SIG_BITS) - 1;
+         const MIN_SIG: u64 = 1 << (Self::SIG_BITS - 1);
+ 
+         const INFINITY: Self = $type::INFINITY;
+         const NAN: Self = $type::NAN;
+         const ZERO: Self = 0.0;
+     };
+ }
+ 
+ impl RawFloat for f32 {
+     type Bits = u32;
+ 
+     const SIG_BITS: u8 = 24;
+     const EXP_BITS: u8 = 8;
+     const CEIL_LOG5_OF_MAX_SIG: i16 = 11;
+     const MAX_NORMAL_DIGITS: usize = 35;
+     const INF_CUTOFF: i64 = 40;
+     const ZERO_CUTOFF: i64 = -48;
+     other_constants!(f32);
+ 
+     /// Returns the mantissa, exponent and sign as integers.
+     fn integer_decode(self) -> (u64, i16, i8) {
+         let bits = self.to_bits();
+         let sign: i8 = if bits >> 31 == 0 { 1 } else { -1 };
+         let mut exponent: i16 = ((bits >> 23) & 0xff) as i16;
+         let mantissa =
+             if exponent == 0 { (bits & 0x7fffff) << 1 } else { (bits & 0x7fffff) | 0x800000 };
+         // Exponent bias + mantissa shift
+         exponent -= 127 + 23;
+         (mantissa as u64, exponent, sign)
+     }
+ 
+     fn unpack(self) -> Unpacked {
+         let (sig, exp, _sig) = self.integer_decode();
+         Unpacked::new(sig, exp)
+     }
+ 
+     fn from_int(x: u64) -> f32 {
+         // rkruppe is uncertain whether `as` rounds correctly on all platforms.
+         debug_assert!(x as f32 == fp_to_float(Fp { f: x, e: 0 }));
+         x as f32
+     }
+ 
+     fn short_fast_pow10(e: usize) -> Self {
+         table::F32_SHORT_POWERS[e]
+     }
+ 
+     fn classify(self) -> FpCategory {
+         self.classify()
+     }
+     fn to_bits(self) -> Self::Bits {
+         self.to_bits()
+     }
+     fn from_bits(v: Self::Bits) -> Self {
+         Self::from_bits(v)
+     }
+ }
+ 
+ impl RawFloat for f64 {
+     type Bits = u64;
+ 
+     const SIG_BITS: u8 = 53;
+     const EXP_BITS: u8 = 11;
+     const CEIL_LOG5_OF_MAX_SIG: i16 = 23;
+     const MAX_NORMAL_DIGITS: usize = 305;
+     const INF_CUTOFF: i64 = 310;
+     const ZERO_CUTOFF: i64 = -326;
+     other_constants!(f64);
+ 
+     /// Returns the mantissa, exponent and sign as integers.
+     fn integer_decode(self) -> (u64, i16, i8) {
+         let bits = self.to_bits();
+         let sign: i8 = if bits >> 63 == 0 { 1 } else { -1 };
+         let mut exponent: i16 = ((bits >> 52) & 0x7ff) as i16;
+         let mantissa = if exponent == 0 {
+             (bits & 0xfffffffffffff) << 1
+         } else {
+             (bits & 0xfffffffffffff) | 0x10000000000000
+         };
+         // Exponent bias + mantissa shift
+         exponent -= 1023 + 52;
+         (mantissa, exponent, sign)
+     }
+ 
+     fn unpack(self) -> Unpacked {
+         let (sig, exp, _sig) = self.integer_decode();
+         Unpacked::new(sig, exp)
+     }
+ 
+     fn from_int(x: u64) -> f64 {
+         // rkruppe is uncertain whether `as` rounds correctly on all platforms.
+         debug_assert!(x as f64 == fp_to_float(Fp { f: x, e: 0 }));
+         x as f64
+     }
+ 
+     fn short_fast_pow10(e: usize) -> Self {
+         table::F64_SHORT_POWERS[e]
+     }
+ 
+     fn classify(self) -> FpCategory {
+         self.classify()
+     }
+     fn to_bits(self) -> Self::Bits {
+         self.to_bits()
+     }
+     fn from_bits(v: Self::Bits) -> Self {
+         Self::from_bits(v)
+     }
+ }
+ 
+ /// Converts an `Fp` to the closest machine float type.
+ /// Does not handle subnormal results.
+ pub fn fp_to_float<T: RawFloat>(x: Fp) -> T {
+     let x = x.normalize();
+     // x.f is 64 bit, so x.e has a mantissa shift of 63
+     let e = x.e + 63;
+     if e > T::MAX_EXP {
+         panic!("fp_to_float: exponent {} too large", e)
+     } else if e > T::MIN_EXP {
+         encode_normal(round_normal::<T>(x))
+     } else {
+         panic!("fp_to_float: exponent {} too small", e)
+     }
+ }
+ 
+ /// Round the 64-bit significand to T::SIG_BITS bits with half-to-even.
+ /// Does not handle exponent overflow.
+ pub fn round_normal<T: RawFloat>(x: Fp) -> Unpacked {
+     let excess = 64 - T::SIG_BITS as i16;
+     let half: u64 = 1 << (excess - 1);
+     let (q, rem) = (x.f >> excess, x.f & ((1 << excess) - 1));
+     assert_eq!(q << excess | rem, x.f);
+     // Adjust mantissa shift
+     let k = x.e + excess;
+     if rem < half {
+         Unpacked::new(q, k)
+     } else if rem == half && (q % 2) == 0 {
+         Unpacked::new(q, k)
+     } else if q == T::MAX_SIG {
+         Unpacked::new(T::MIN_SIG, k + 1)
+     } else {
+         Unpacked::new(q + 1, k)
+     }
+ }
+ 
+ /// Inverse of `RawFloat::unpack()` for normalized numbers.
+ /// Panics if the significand or exponent are not valid for normalized numbers.
+ pub fn encode_normal<T: RawFloat>(x: Unpacked) -> T {
+     debug_assert!(
+         T::MIN_SIG <= x.sig && x.sig <= T::MAX_SIG,
+         "encode_normal: significand not normalized"
+     );
+     // Remove the hidden bit
+     let sig_enc = x.sig & !(1 << T::EXPLICIT_SIG_BITS);
+     // Adjust the exponent for exponent bias and mantissa shift
+     let k_enc = x.k + T::MAX_EXP + T::EXPLICIT_SIG_BITS as i16;
+     debug_assert!(k_enc != 0 && k_enc < T::MAX_ENCODED_EXP, "encode_normal: exponent out of range");
+     // Leave sign bit at 0 ("+"), our numbers are all positive
+     let bits = (k_enc as u64) << T::EXPLICIT_SIG_BITS | sig_enc;
+     T::from_bits(bits.try_into().unwrap_or_else(|_| unreachable!()))
+ }
+ 
+ /// Construct a subnormal. A mantissa of 0 is allowed and constructs zero.
+ pub fn encode_subnormal<T: RawFloat>(significand: u64) -> T {
+     assert!(significand < T::MIN_SIG, "encode_subnormal: not actually subnormal");
+     // Encoded exponent is 0, the sign bit is 0, so we just have to reinterpret the bits.
+     T::from_bits(significand.try_into().unwrap_or_else(|_| unreachable!()))
+ }
+ 
+ /// Approximate a bignum with an Fp. Rounds within 0.5 ULP with half-to-even.
+ pub fn big_to_fp(f: &Big) -> Fp {
+     let end = f.bit_length();
+     assert!(end != 0, "big_to_fp: unexpectedly, input is zero");
+     let start = end.saturating_sub(64);
+     let leading = num::get_bits(f, start, end);
+     // We cut off all bits prior to the index `start`, i.e., we effectively right-shift by
+     // an amount of `start`, so this is also the exponent we need.
+     let e = start as i16;
+     let rounded_down = Fp { f: leading, e }.normalize();
+     // Round (half-to-even) depending on the truncated bits.
+     match num::compare_with_half_ulp(f, start) {
+         Less => rounded_down,
+         Equal if leading % 2 == 0 => rounded_down,
+         Equal | Greater => match leading.checked_add(1) {
+             Some(f) => Fp { f, e }.normalize(),
+             None => Fp { f: 1 << 63, e: e + 1 },
+         },
+     }
+ }
+ 
+ /// Finds the largest floating point number strictly smaller than the argument.
+ /// Does not handle subnormals, zero, or exponent underflow.
+ pub fn prev_float<T: RawFloat>(x: T) -> T {
+     match x.classify() {
+         Infinite => panic!("prev_float: argument is infinite"),
+         Nan => panic!("prev_float: argument is NaN"),
+         Subnormal => panic!("prev_float: argument is subnormal"),
+         Zero => panic!("prev_float: argument is zero"),
+         Normal => {
+             let Unpacked { sig, k } = x.unpack();
+             if sig == T::MIN_SIG {
+                 encode_normal(Unpacked::new(T::MAX_SIG, k - 1))
+             } else {
+                 encode_normal(Unpacked::new(sig - 1, k))
+             }
+         }
+     }
+ }
+ 
+ // Find the smallest floating point number strictly larger than the argument.
+ // This operation is saturating, i.e., next_float(inf) == inf.
+ // Unlike most code in this module, this function does handle zero, subnormals, and infinities.
+ // However, like all other code here, it does not deal with NaN and negative numbers.
+ pub fn next_float<T: RawFloat>(x: T) -> T {
+     match x.classify() {
+         Nan => panic!("next_float: argument is NaN"),
+         Infinite => T::INFINITY,
+         // This seems too good to be true, but it works.
+         // 0.0 is encoded as the all-zero word. Subnormals are 0x000m...m where m is the mantissa.
+         // In particular, the smallest subnormal is 0x0...01 and the largest is 0x000F...F.
+         // The smallest normal number is 0x0010...0, so this corner case works as well.
+         // If the increment overflows the mantissa, the carry bit increments the exponent as we
+         // want, and the mantissa bits become zero. Because of the hidden bit convention, this
+         // too is exactly what we want!
+         // Finally, f64::MAX + 1 = 7eff...f + 1 = 7ff0...0 = f64::INFINITY.
+         Zero | Subnormal | Normal => T::from_bits(x.to_bits() + T::Bits::from(1u8)),
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/table.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/table.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/dec2flt/table.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/dec2flt/table.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1277 ----
+ //! Tables of approximations of powers of ten.
+ //! DO NOT MODIFY: Generated by `src/etc/dec2flt_table.py`
+ 
+ pub const MIN_E: i16 = -305;
+ pub const MAX_E: i16 = 305;
+ 
+ #[rustfmt::skip]
+ pub const POWERS: ([u64; 611], [i16; 611]) = (
+     [
+         0xe0b62e2929aba83c,
+         0x8c71dcd9ba0b4926,
+         0xaf8e5410288e1b6f,
+         0xdb71e91432b1a24b,
+         0x892731ac9faf056f,
+         0xab70fe17c79ac6ca,
+         0xd64d3d9db981787d,
+         0x85f0468293f0eb4e,
+         0xa76c582338ed2622,
+         0xd1476e2c07286faa,
+         0x82cca4db847945ca,
+         0xa37fce126597973d,
+         0xcc5fc196fefd7d0c,
+         0xff77b1fcbebcdc4f,
+         0x9faacf3df73609b1,
+         0xc795830d75038c1e,
+         0xf97ae3d0d2446f25,
+         0x9becce62836ac577,
+         0xc2e801fb244576d5,
+         0xf3a20279ed56d48a,
+         0x9845418c345644d7,
+         0xbe5691ef416bd60c,
+         0xedec366b11c6cb8f,
+         0x94b3a202eb1c3f39,
+         0xb9e08a83a5e34f08,
+         0xe858ad248f5c22ca,
+         0x91376c36d99995be,
+         0xb58547448ffffb2e,
+         0xe2e69915b3fff9f9,
+         0x8dd01fad907ffc3c,
+         0xb1442798f49ffb4b,
+         0xdd95317f31c7fa1d,
+         0x8a7d3eef7f1cfc52,
+         0xad1c8eab5ee43b67,
+         0xd863b256369d4a41,
+         0x873e4f75e2224e68,
+         0xa90de3535aaae202,
+         0xd3515c2831559a83,
+         0x8412d9991ed58092,
+         0xa5178fff668ae0b6,
+         0xce5d73ff402d98e4,
+         0x80fa687f881c7f8e,
+         0xa139029f6a239f72,
+         0xc987434744ac874f,
+         0xfbe9141915d7a922,
+         0x9d71ac8fada6c9b5,
+         0xc4ce17b399107c23,
+         0xf6019da07f549b2b,
+         0x99c102844f94e0fb,
+         0xc0314325637a193a,
+         0xf03d93eebc589f88,
+         0x96267c7535b763b5,
+         0xbbb01b9283253ca3,
+         0xea9c227723ee8bcb,
+         0x92a1958a7675175f,
+         0xb749faed14125d37,
+         0xe51c79a85916f485,
+         0x8f31cc0937ae58d3,
+         0xb2fe3f0b8599ef08,
+         0xdfbdcece67006ac9,
+         0x8bd6a141006042be,
+         0xaecc49914078536d,
+         0xda7f5bf590966849,
+         0x888f99797a5e012d,
+         0xaab37fd7d8f58179,
+         0xd5605fcdcf32e1d7,
+         0x855c3be0a17fcd26,
+         0xa6b34ad8c9dfc070,
+         0xd0601d8efc57b08c,
+         0x823c12795db6ce57,
+         0xa2cb1717b52481ed,
+         0xcb7ddcdda26da269,
+         0xfe5d54150b090b03,
+         0x9efa548d26e5a6e2,
+         0xc6b8e9b0709f109a,
+         0xf867241c8cc6d4c1,
+         0x9b407691d7fc44f8,
+         0xc21094364dfb5637,
+         0xf294b943e17a2bc4,
+         0x979cf3ca6cec5b5b,
+         0xbd8430bd08277231,
+         0xece53cec4a314ebe,
+         0x940f4613ae5ed137,
+         0xb913179899f68584,
+         0xe757dd7ec07426e5,
+         0x9096ea6f3848984f,
+         0xb4bca50b065abe63,
+         0xe1ebce4dc7f16dfc,
+         0x8d3360f09cf6e4bd,
+         0xb080392cc4349ded,
+         0xdca04777f541c568,
+         0x89e42caaf9491b61,
+         0xac5d37d5b79b6239,
+         0xd77485cb25823ac7,
+         0x86a8d39ef77164bd,
+         0xa8530886b54dbdec,
+         0xd267caa862a12d67,
+         0x8380dea93da4bc60,
+         0xa46116538d0deb78,
+         0xcd795be870516656,
+         0x806bd9714632dff6,
+         0xa086cfcd97bf97f4,
+         0xc8a883c0fdaf7df0,
+         0xfad2a4b13d1b5d6c,
+         0x9cc3a6eec6311a64,
+         0xc3f490aa77bd60fd,
+         0xf4f1b4d515acb93c,
+         0x991711052d8bf3c5,
+         0xbf5cd54678eef0b7,
+         0xef340a98172aace5,
+         0x9580869f0e7aac0f,
+         0xbae0a846d2195713,
+         0xe998d258869facd7,
+         0x91ff83775423cc06,
+         0xb67f6455292cbf08,
+         0xe41f3d6a7377eeca,
+         0x8e938662882af53e,
+         0xb23867fb2a35b28e,
+         0xdec681f9f4c31f31,
+         0x8b3c113c38f9f37f,
+         0xae0b158b4738705f,
+         0xd98ddaee19068c76,
+         0x87f8a8d4cfa417ca,
+         0xa9f6d30a038d1dbc,
+         0xd47487cc8470652b,
+         0x84c8d4dfd2c63f3b,
+         0xa5fb0a17c777cf0a,
+         0xcf79cc9db955c2cc,
+         0x81ac1fe293d599c0,
+         0xa21727db38cb0030,
+         0xca9cf1d206fdc03c,
+         0xfd442e4688bd304b,
+         0x9e4a9cec15763e2f,
+         0xc5dd44271ad3cdba,
+         0xf7549530e188c129,
+         0x9a94dd3e8cf578ba,
+         0xc13a148e3032d6e8,
+         0xf18899b1bc3f8ca2,
+         0x96f5600f15a7b7e5,
+         0xbcb2b812db11a5de,
+         0xebdf661791d60f56,
+         0x936b9fcebb25c996,
+         0xb84687c269ef3bfb,
+         0xe65829b3046b0afa,
+         0x8ff71a0fe2c2e6dc,
+         0xb3f4e093db73a093,
+         0xe0f218b8d25088b8,
+         0x8c974f7383725573,
+         0xafbd2350644eead0,
+         0xdbac6c247d62a584,
+         0x894bc396ce5da772,
+         0xab9eb47c81f5114f,
+         0xd686619ba27255a3,
+         0x8613fd0145877586,
+         0xa798fc4196e952e7,
+         0xd17f3b51fca3a7a1,
+         0x82ef85133de648c5,
+         0xa3ab66580d5fdaf6,
+         0xcc963fee10b7d1b3,
+         0xffbbcfe994e5c620,
+         0x9fd561f1fd0f9bd4,
+         0xc7caba6e7c5382c9,
+         0xf9bd690a1b68637b,
+         0x9c1661a651213e2d,
+         0xc31bfa0fe5698db8,
+         0xf3e2f893dec3f126,
+         0x986ddb5c6b3a76b8,
+         0xbe89523386091466,
+         0xee2ba6c0678b597f,
+         0x94db483840b717f0,
+         0xba121a4650e4ddec,
+         0xe896a0d7e51e1566,
+         0x915e2486ef32cd60,
+         0xb5b5ada8aaff80b8,
+         0xe3231912d5bf60e6,
+         0x8df5efabc5979c90,
+         0xb1736b96b6fd83b4,
+         0xddd0467c64bce4a1,
+         0x8aa22c0dbef60ee4,
+         0xad4ab7112eb3929e,
+         0xd89d64d57a607745,
+         0x87625f056c7c4a8b,
+         0xa93af6c6c79b5d2e,
+         0xd389b47879823479,
+         0x843610cb4bf160cc,
+         0xa54394fe1eedb8ff,
+         0xce947a3da6a9273e,
+         0x811ccc668829b887,
+         0xa163ff802a3426a9,
+         0xc9bcff6034c13053,
+         0xfc2c3f3841f17c68,
+         0x9d9ba7832936edc1,
+         0xc5029163f384a931,
+         0xf64335bcf065d37d,
+         0x99ea0196163fa42e,
+         0xc06481fb9bcf8d3a,
+         0xf07da27a82c37088,
+         0x964e858c91ba2655,
+         0xbbe226efb628afeb,
+         0xeadab0aba3b2dbe5,
+         0x92c8ae6b464fc96f,
+         0xb77ada0617e3bbcb,
+         0xe55990879ddcaabe,
+         0x8f57fa54c2a9eab7,
+         0xb32df8e9f3546564,
+         0xdff9772470297ebd,
+         0x8bfbea76c619ef36,
+         0xaefae51477a06b04,
+         0xdab99e59958885c5,
+         0x88b402f7fd75539b,
+         0xaae103b5fcd2a882,
+         0xd59944a37c0752a2,
+         0x857fcae62d8493a5,
+         0xa6dfbd9fb8e5b88f,
+         0xd097ad07a71f26b2,
+         0x825ecc24c8737830,
+         0xa2f67f2dfa90563b,
+         0xcbb41ef979346bca,
+         0xfea126b7d78186bd,
+         0x9f24b832e6b0f436,
+         0xc6ede63fa05d3144,
+         0xf8a95fcf88747d94,
+         0x9b69dbe1b548ce7d,
+         0xc24452da229b021c,
+         0xf2d56790ab41c2a3,
+         0x97c560ba6b0919a6,
+         0xbdb6b8e905cb600f,
+         0xed246723473e3813,
+         0x9436c0760c86e30c,
+         0xb94470938fa89bcf,
+         0xe7958cb87392c2c3,
+         0x90bd77f3483bb9ba,
+         0xb4ecd5f01a4aa828,
+         0xe2280b6c20dd5232,
+         0x8d590723948a535f,
+         0xb0af48ec79ace837,
+         0xdcdb1b2798182245,
+         0x8a08f0f8bf0f156b,
+         0xac8b2d36eed2dac6,
+         0xd7adf884aa879177,
+         0x86ccbb52ea94baeb,
+         0xa87fea27a539e9a5,
+         0xd29fe4b18e88640f,
+         0x83a3eeeef9153e89,
+         0xa48ceaaab75a8e2b,
+         0xcdb02555653131b6,
+         0x808e17555f3ebf12,
+         0xa0b19d2ab70e6ed6,
+         0xc8de047564d20a8c,
+         0xfb158592be068d2f,
+         0x9ced737bb6c4183d,
+         0xc428d05aa4751e4d,
+         0xf53304714d9265e0,
+         0x993fe2c6d07b7fac,
+         0xbf8fdb78849a5f97,
+         0xef73d256a5c0f77d,
+         0x95a8637627989aae,
+         0xbb127c53b17ec159,
+         0xe9d71b689dde71b0,
+         0x9226712162ab070e,
+         0xb6b00d69bb55c8d1,
+         0xe45c10c42a2b3b06,
+         0x8eb98a7a9a5b04e3,
+         0xb267ed1940f1c61c,
+         0xdf01e85f912e37a3,
+         0x8b61313bbabce2c6,
+         0xae397d8aa96c1b78,
+         0xd9c7dced53c72256,
+         0x881cea14545c7575,
+         0xaa242499697392d3,
+         0xd4ad2dbfc3d07788,
+         0x84ec3c97da624ab5,
+         0xa6274bbdd0fadd62,
+         0xcfb11ead453994ba,
+         0x81ceb32c4b43fcf5,
+         0xa2425ff75e14fc32,
+         0xcad2f7f5359a3b3e,
+         0xfd87b5f28300ca0e,
+         0x9e74d1b791e07e48,
+         0xc612062576589ddb,
+         0xf79687aed3eec551,
+         0x9abe14cd44753b53,
+         0xc16d9a0095928a27,
+         0xf1c90080baf72cb1,
+         0x971da05074da7bef,
+         0xbce5086492111aeb,
+         0xec1e4a7db69561a5,
+         0x9392ee8e921d5d07,
+         0xb877aa3236a4b449,
+         0xe69594bec44de15b,
+         0x901d7cf73ab0acd9,
+         0xb424dc35095cd80f,
+         0xe12e13424bb40e13,
+         0x8cbccc096f5088cc,
+         0xafebff0bcb24aaff,
+         0xdbe6fecebdedd5bf,
+         0x89705f4136b4a597,
+         0xabcc77118461cefd,
+         0xd6bf94d5e57a42bc,
+         0x8637bd05af6c69b6,
+         0xa7c5ac471b478423,
+         0xd1b71758e219652c,
+         0x83126e978d4fdf3b,
+         0xa3d70a3d70a3d70a,
+         0xcccccccccccccccd,
+         0x8000000000000000,
+         0xa000000000000000,
+         0xc800000000000000,
+         0xfa00000000000000,
+         0x9c40000000000000,
+         0xc350000000000000,
+         0xf424000000000000,
+         0x9896800000000000,
+         0xbebc200000000000,
+         0xee6b280000000000,
+         0x9502f90000000000,
+         0xba43b74000000000,
+         0xe8d4a51000000000,
+         0x9184e72a00000000,
+         0xb5e620f480000000,
+         0xe35fa931a0000000,
+         0x8e1bc9bf04000000,
+         0xb1a2bc2ec5000000,
+         0xde0b6b3a76400000,
+         0x8ac7230489e80000,
+         0xad78ebc5ac620000,
+         0xd8d726b7177a8000,
+         0x878678326eac9000,
+         0xa968163f0a57b400,
+         0xd3c21bcecceda100,
+         0x84595161401484a0,
+         0xa56fa5b99019a5c8,
+         0xcecb8f27f4200f3a,
+         0x813f3978f8940984,
+         0xa18f07d736b90be5,
+         0xc9f2c9cd04674edf,
+         0xfc6f7c4045812296,
+         0x9dc5ada82b70b59e,
+         0xc5371912364ce305,
+         0xf684df56c3e01bc7,
+         0x9a130b963a6c115c,
+         0xc097ce7bc90715b3,
+         0xf0bdc21abb48db20,
+         0x96769950b50d88f4,
+         0xbc143fa4e250eb31,
+         0xeb194f8e1ae525fd,
+         0x92efd1b8d0cf37be,
+         0xb7abc627050305ae,
+         0xe596b7b0c643c719,
+         0x8f7e32ce7bea5c70,
+         0xb35dbf821ae4f38c,
+         0xe0352f62a19e306f,
+         0x8c213d9da502de45,
+         0xaf298d050e4395d7,
+         0xdaf3f04651d47b4c,
+         0x88d8762bf324cd10,
+         0xab0e93b6efee0054,
+         0xd5d238a4abe98068,
+         0x85a36366eb71f041,
+         0xa70c3c40a64e6c52,
+         0xd0cf4b50cfe20766,
+         0x82818f1281ed44a0,
+         0xa321f2d7226895c8,
+         0xcbea6f8ceb02bb3a,
+         0xfee50b7025c36a08,
+         0x9f4f2726179a2245,
+         0xc722f0ef9d80aad6,
+         0xf8ebad2b84e0d58c,
+         0x9b934c3b330c8577,
+         0xc2781f49ffcfa6d5,
+         0xf316271c7fc3908b,
+         0x97edd871cfda3a57,
+         0xbde94e8e43d0c8ec,
+         0xed63a231d4c4fb27,
+         0x945e455f24fb1cf9,
+         0xb975d6b6ee39e437,
+         0xe7d34c64a9c85d44,
+         0x90e40fbeea1d3a4b,
+         0xb51d13aea4a488dd,
+         0xe264589a4dcdab15,
+         0x8d7eb76070a08aed,
+         0xb0de65388cc8ada8,
+         0xdd15fe86affad912,
+         0x8a2dbf142dfcc7ab,
+         0xacb92ed9397bf996,
+         0xd7e77a8f87daf7fc,
+         0x86f0ac99b4e8dafd,
+         0xa8acd7c0222311bd,
+         0xd2d80db02aabd62c,
+         0x83c7088e1aab65db,
+         0xa4b8cab1a1563f52,
+         0xcde6fd5e09abcf27,
+         0x80b05e5ac60b6178,
+         0xa0dc75f1778e39d6,
+         0xc913936dd571c84c,
+         0xfb5878494ace3a5f,
+         0x9d174b2dcec0e47b,
+         0xc45d1df942711d9a,
+         0xf5746577930d6501,
+         0x9968bf6abbe85f20,
+         0xbfc2ef456ae276e9,
+         0xefb3ab16c59b14a3,
+         0x95d04aee3b80ece6,
+         0xbb445da9ca61281f,
+         0xea1575143cf97227,
+         0x924d692ca61be758,
+         0xb6e0c377cfa2e12e,
+         0xe498f455c38b997a,
+         0x8edf98b59a373fec,
+         0xb2977ee300c50fe7,
+         0xdf3d5e9bc0f653e1,
+         0x8b865b215899f46d,
+         0xae67f1e9aec07188,
+         0xda01ee641a708dea,
+         0x884134fe908658b2,
+         0xaa51823e34a7eedf,
+         0xd4e5e2cdc1d1ea96,
+         0x850fadc09923329e,
+         0xa6539930bf6bff46,
+         0xcfe87f7cef46ff17,
+         0x81f14fae158c5f6e,
+         0xa26da3999aef774a,
+         0xcb090c8001ab551c,
+         0xfdcb4fa002162a63,
+         0x9e9f11c4014dda7e,
+         0xc646d63501a1511e,
+         0xf7d88bc24209a565,
+         0x9ae757596946075f,
+         0xc1a12d2fc3978937,
+         0xf209787bb47d6b85,
+         0x9745eb4d50ce6333,
+         0xbd176620a501fc00,
+         0xec5d3fa8ce427b00,
+         0x93ba47c980e98ce0,
+         0xb8a8d9bbe123f018,
+         0xe6d3102ad96cec1e,
+         0x9043ea1ac7e41393,
+         0xb454e4a179dd1877,
+         0xe16a1dc9d8545e95,
+         0x8ce2529e2734bb1d,
+         0xb01ae745b101e9e4,
+         0xdc21a1171d42645d,
+         0x899504ae72497eba,
+         0xabfa45da0edbde69,
+         0xd6f8d7509292d603,
+         0x865b86925b9bc5c2,
+         0xa7f26836f282b733,
+         0xd1ef0244af2364ff,
+         0x8335616aed761f1f,
+         0xa402b9c5a8d3a6e7,
+         0xcd036837130890a1,
+         0x802221226be55a65,
+         0xa02aa96b06deb0fe,
+         0xc83553c5c8965d3d,
+         0xfa42a8b73abbf48d,
+         0x9c69a97284b578d8,
+         0xc38413cf25e2d70e,
+         0xf46518c2ef5b8cd1,
+         0x98bf2f79d5993803,
+         0xbeeefb584aff8604,
+         0xeeaaba2e5dbf6785,
+         0x952ab45cfa97a0b3,
+         0xba756174393d88e0,
+         0xe912b9d1478ceb17,
+         0x91abb422ccb812ef,
+         0xb616a12b7fe617aa,
+         0xe39c49765fdf9d95,
+         0x8e41ade9fbebc27d,
+         0xb1d219647ae6b31c,
+         0xde469fbd99a05fe3,
+         0x8aec23d680043bee,
+         0xada72ccc20054aea,
+         0xd910f7ff28069da4,
+         0x87aa9aff79042287,
+         0xa99541bf57452b28,
+         0xd3fa922f2d1675f2,
+         0x847c9b5d7c2e09b7,
+         0xa59bc234db398c25,
+         0xcf02b2c21207ef2f,
+         0x8161afb94b44f57d,
+         0xa1ba1ba79e1632dc,
+         0xca28a291859bbf93,
+         0xfcb2cb35e702af78,
+         0x9defbf01b061adab,
+         0xc56baec21c7a1916,
+         0xf6c69a72a3989f5c,
+         0x9a3c2087a63f6399,
+         0xc0cb28a98fcf3c80,
+         0xf0fdf2d3f3c30b9f,
+         0x969eb7c47859e744,
+         0xbc4665b596706115,
+         0xeb57ff22fc0c795a,
+         0x9316ff75dd87cbd8,
+         0xb7dcbf5354e9bece,
+         0xe5d3ef282a242e82,
+         0x8fa475791a569d11,
+         0xb38d92d760ec4455,
+         0xe070f78d3927556b,
+         0x8c469ab843b89563,
+         0xaf58416654a6babb,
+         0xdb2e51bfe9d0696a,
+         0x88fcf317f22241e2,
+         0xab3c2fddeeaad25b,
+         0xd60b3bd56a5586f2,
+         0x85c7056562757457,
+         0xa738c6bebb12d16d,
+         0xd106f86e69d785c8,
+         0x82a45b450226b39d,
+         0xa34d721642b06084,
+         0xcc20ce9bd35c78a5,
+         0xff290242c83396ce,
+         0x9f79a169bd203e41,
+         0xc75809c42c684dd1,
+         0xf92e0c3537826146,
+         0x9bbcc7a142b17ccc,
+         0xc2abf989935ddbfe,
+         0xf356f7ebf83552fe,
+         0x98165af37b2153df,
+         0xbe1bf1b059e9a8d6,
+         0xeda2ee1c7064130c,
+         0x9485d4d1c63e8be8,
+         0xb9a74a0637ce2ee1,
+         0xe8111c87c5c1ba9a,
+         0x910ab1d4db9914a0,
+         0xb54d5e4a127f59c8,
+         0xe2a0b5dc971f303a,
+         0x8da471a9de737e24,
+         0xb10d8e1456105dad,
+         0xdd50f1996b947519,
+         0x8a5296ffe33cc930,
+         0xace73cbfdc0bfb7b,
+         0xd8210befd30efa5a,
+         0x8714a775e3e95c78,
+         0xa8d9d1535ce3b396,
+         0xd31045a8341ca07c,
+         0x83ea2b892091e44e,
+         0xa4e4b66b68b65d61,
+         0xce1de40642e3f4b9,
+         0x80d2ae83e9ce78f4,
+         0xa1075a24e4421731,
+         0xc94930ae1d529cfd,
+         0xfb9b7cd9a4a7443c,
+         0x9d412e0806e88aa6,
+         0xc491798a08a2ad4f,
+         0xf5b5d7ec8acb58a3,
+         0x9991a6f3d6bf1766,
+         0xbff610b0cc6edd3f,
+         0xeff394dcff8a948f,
+         0x95f83d0a1fb69cd9,
+         0xbb764c4ca7a44410,
+         0xea53df5fd18d5514,
+         0x92746b9be2f8552c,
+         0xb7118682dbb66a77,
+         0xe4d5e82392a40515,
+         0x8f05b1163ba6832d,
+         0xb2c71d5bca9023f8,
+         0xdf78e4b2bd342cf7,
+         0x8bab8eefb6409c1a,
+         0xae9672aba3d0c321,
+         0xda3c0f568cc4f3e9,
+         0x8865899617fb1871,
+         0xaa7eebfb9df9de8e,
+         0xd51ea6fa85785631,
+         0x8533285c936b35df,
+         0xa67ff273b8460357,
+         0xd01fef10a657842c,
+         0x8213f56a67f6b29c,
+         0xa298f2c501f45f43,
+         0xcb3f2f7642717713,
+         0xfe0efb53d30dd4d8,
+         0x9ec95d1463e8a507,
+         0xc67bb4597ce2ce49,
+         0xf81aa16fdc1b81db,
+         0x9b10a4e5e9913129,
+         0xc1d4ce1f63f57d73,
+         0xf24a01a73cf2dcd0,
+         0x976e41088617ca02,
+         0xbd49d14aa79dbc82,
+         0xec9c459d51852ba3,
+         0x93e1ab8252f33b46,
+         0xb8da1662e7b00a17,
+         0xe7109bfba19c0c9d,
+         0x906a617d450187e2,
+         0xb484f9dc9641e9db,
+         0xe1a63853bbd26451,
+         0x8d07e33455637eb3,
+         0xb049dc016abc5e60,
+         0xdc5c5301c56b75f7,
+         0x89b9b3e11b6329bb,
+         0xac2820d9623bf429,
+         0xd732290fbacaf134,
+         0x867f59a9d4bed6c0,
+         0xa81f301449ee8c70,
+         0xd226fc195c6a2f8c,
+         0x83585d8fd9c25db8,
+         0xa42e74f3d032f526,
+         0xcd3a1230c43fb26f,
+         0x80444b5e7aa7cf85,
+         0xa0555e361951c367,
+         0xc86ab5c39fa63441,
+         0xfa856334878fc151,
+         0x9c935e00d4b9d8d2,
+         0xc3b8358109e84f07,
+         0xf4a642e14c6262c9,
+         0x98e7e9cccfbd7dbe,
+         0xbf21e44003acdd2d,
+         0xeeea5d5004981478,
+         0x95527a5202df0ccb,
+         0xbaa718e68396cffe,
+         0xe950df20247c83fd,
+         0x91d28b7416cdd27e,
+     ],
+     [
+         -1077,
+         -1073,
+         -1070,
+         -1067,
+         -1063,
+         -1060,
+         -1057,
+         -1053,
+         -1050,
+         -1047,
+         -1043,
+         -1040,
+         -1037,
+         -1034,
+         -1030,
+         -1027,
+         -1024,
+         -1020,
+         -1017,
+         -1014,
+         -1010,
+         -1007,
+         -1004,
+         -1000,
+         -997,
+         -994,
+         -990,
+         -987,
+         -984,
+         -980,
+         -977,
+         -974,
+         -970,
+         -967,
+         -964,
+         -960,
+         -957,
+         -954,
+         -950,
+         -947,
+         -944,
+         -940,
+         -937,
+         -934,
+         -931,
+         -927,
+         -924,
+         -921,
+         -917,
+         -914,
+         -911,
+         -907,
+         -904,
+         -901,
+         -897,
+         -894,
+         -891,
+         -887,
+         -884,
+         -881,
+         -877,
+         -874,
+         -871,
+         -867,
+         -864,
+         -861,
+         -857,
+         -854,
+         -851,
+         -847,
+         -844,
+         -841,
+         -838,
+         -834,
+         -831,
+         -828,
+         -824,
+         -821,
+         -818,
+         -814,
+         -811,
+         -808,
+         -804,
+         -801,
+         -798,
+         -794,
+         -791,
+         -788,
+         -784,
+         -781,
+         -778,
+         -774,
+         -771,
+         -768,
+         -764,
+         -761,
+         -758,
+         -754,
+         -751,
+         -748,
+         -744,
+         -741,
+         -738,
+         -735,
+         -731,
+         -728,
+         -725,
+         -721,
+         -718,
+         -715,
+         -711,
+         -708,
+         -705,
+         -701,
+         -698,
+         -695,
+         -691,
+         -688,
+         -685,
+         -681,
+         -678,
+         -675,
+         -671,
+         -668,
+         -665,
+         -661,
+         -658,
+         -655,
+         -651,
+         -648,
+         -645,
+         -642,
+         -638,
+         -635,
+         -632,
+         -628,
+         -625,
+         -622,
+         -618,
+         -615,
+         -612,
+         -608,
+         -605,
+         -602,
+         -598,
+         -595,
+         -592,
+         -588,
+         -585,
+         -582,
+         -578,
+         -575,
+         -572,
+         -568,
+         -565,
+         -562,
+         -558,
+         -555,
+         -552,
+         -549,
+         -545,
+         -542,
+         -539,
+         -535,
+         -532,
+         -529,
+         -525,
+         -522,
+         -519,
+         -515,
+         -512,
+         -509,
+         -505,
+         -502,
+         -499,
+         -495,
+         -492,
+         -489,
+         -485,
+         -482,
+         -479,
+         -475,
+         -472,
+         -469,
+         -465,
+         -462,
+         -459,
+         -455,
+         -452,
+         -449,
+         -446,
+         -442,
+         -439,
+         -436,
+         -432,
+         -429,
+         -426,
+         -422,
+         -419,
+         -416,
+         -412,
+         -409,
+         -406,
+         -402,
+         -399,
+         -396,
+         -392,
+         -389,
+         -386,
+         -382,
+         -379,
+         -376,
+         -372,
+         -369,
+         -366,
+         -362,
+         -359,
+         -356,
+         -353,
+         -349,
+         -346,
+         -343,
+         -339,
+         -336,
+         -333,
+         -329,
+         -326,
+         -323,
+         -319,
+         -316,
+         -313,
+         -309,
+         -306,
+         -303,
+         -299,
+         -296,
+         -293,
+         -289,
+         -286,
+         -283,
+         -279,
+         -276,
+         -273,
+         -269,
+         -266,
+         -263,
+         -259,
+         -256,
+         -253,
+         -250,
+         -246,
+         -243,
+         -240,
+         -236,
+         -233,
+         -230,
+         -226,
+         -223,
+         -220,
+         -216,
+         -213,
+         -210,
+         -206,
+         -203,
+         -200,
+         -196,
+         -193,
+         -190,
+         -186,
+         -183,
+         -180,
+         -176,
+         -173,
+         -170,
+         -166,
+         -163,
+         -160,
+         -157,
+         -153,
+         -150,
+         -147,
+         -143,
+         -140,
+         -137,
+         -133,
+         -130,
+         -127,
+         -123,
+         -120,
+         -117,
+         -113,
+         -110,
+         -107,
+         -103,
+         -100,
+         -97,
+         -93,
+         -90,
+         -87,
+         -83,
+         -80,
+         -77,
+         -73,
+         -70,
+         -67,
+         -63,
+         -60,
+         -57,
+         -54,
+         -50,
+         -47,
+         -44,
+         -40,
+         -37,
+         -34,
+         -30,
+         -27,
+         -24,
+         -20,
+         -17,
+         -14,
+         -10,
+         -7,
+         -4,
+         0,
+         3,
+         6,
+         10,
+         13,
+         16,
+         20,
+         23,
+         26,
+         30,
+         33,
+         36,
+         39,
+         43,
+         46,
+         49,
+         53,
+         56,
+         59,
+         63,
+         66,
+         69,
+         73,
+         76,
+         79,
+         83,
+         86,
+         89,
+         93,
+         96,
+         99,
+         103,
+         106,
+         109,
+         113,
+         116,
+         119,
+         123,
+         126,
+         129,
+         132,
+         136,
+         139,
+         142,
+         146,
+         149,
+         152,
+         156,
+         159,
+         162,
+         166,
+         169,
+         172,
+         176,
+         179,
+         182,
+         186,
+         189,
+         192,
+         196,
+         199,
+         202,
+         206,
+         209,
+         212,
+         216,
+         219,
+         222,
+         226,
+         229,
+         232,
+         235,
+         239,
+         242,
+         245,
+         249,
+         252,
+         255,
+         259,
+         262,
+         265,
+         269,
+         272,
+         275,
+         279,
+         282,
+         285,
+         289,
+         292,
+         295,
+         299,
+         302,
+         305,
+         309,
+         312,
+         315,
+         319,
+         322,
+         325,
+         328,
+         332,
+         335,
+         338,
+         342,
+         345,
+         348,
+         352,
+         355,
+         358,
+         362,
+         365,
+         368,
+         372,
+         375,
+         378,
+         382,
+         385,
+         388,
+         392,
+         395,
+         398,
+         402,
+         405,
+         408,
+         412,
+         415,
+         418,
+         422,
+         425,
+         428,
+         431,
+         435,
+         438,
+         441,
+         445,
+         448,
+         451,
+         455,
+         458,
+         461,
+         465,
+         468,
+         471,
+         475,
+         478,
+         481,
+         485,
+         488,
+         491,
+         495,
+         498,
+         501,
+         505,
+         508,
+         511,
+         515,
+         518,
+         521,
+         524,
+         528,
+         531,
+         534,
+         538,
+         541,
+         544,
+         548,
+         551,
+         554,
+         558,
+         561,
+         564,
+         568,
+         571,
+         574,
+         578,
+         581,
+         584,
+         588,
+         591,
+         594,
+         598,
+         601,
+         604,
+         608,
+         611,
+         614,
+         617,
+         621,
+         624,
+         627,
+         631,
+         634,
+         637,
+         641,
+         644,
+         647,
+         651,
+         654,
+         657,
+         661,
+         664,
+         667,
+         671,
+         674,
+         677,
+         681,
+         684,
+         687,
+         691,
+         694,
+         697,
+         701,
+         704,
+         707,
+         711,
+         714,
+         717,
+         720,
+         724,
+         727,
+         730,
+         734,
+         737,
+         740,
+         744,
+         747,
+         750,
+         754,
+         757,
+         760,
+         764,
+         767,
+         770,
+         774,
+         777,
+         780,
+         784,
+         787,
+         790,
+         794,
+         797,
+         800,
+         804,
+         807,
+         810,
+         813,
+         817,
+         820,
+         823,
+         827,
+         830,
+         833,
+         837,
+         840,
+         843,
+         847,
+         850,
+         853,
+         857,
+         860,
+         863,
+         867,
+         870,
+         873,
+         877,
+         880,
+         883,
+         887,
+         890,
+         893,
+         897,
+         900,
+         903,
+         907,
+         910,
+         913,
+         916,
+         920,
+         923,
+         926,
+         930,
+         933,
+         936,
+         940,
+         943,
+         946,
+         950,
+     ],
+ );
+ 
+ #[rustfmt::skip]
+ pub const F32_SHORT_POWERS: [f32; 11] = [
+     1e0,
+     1e1,
+     1e2,
+     1e3,
+     1e4,
+     1e5,
+     1e6,
+     1e7,
+     1e8,
+     1e9,
+     1e10,
+ ];
+ 
+ #[rustfmt::skip]
+ pub const F64_SHORT_POWERS: [f64; 23] = [
+     1e0,
+     1e1,
+     1e2,
+     1e3,
+     1e4,
+     1e5,
+     1e6,
+     1e7,
+     1e8,
+     1e9,
+     1e10,
+     1e11,
+     1e12,
+     1e13,
+     1e14,
+     1e15,
+     1e16,
+     1e17,
+     1e18,
+     1e19,
+     1e20,
+     1e21,
+     1e22,
+ ];
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/diy_float.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/diy_float.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/diy_float.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/diy_float.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,81 ----
+ //! Extended precision "soft float", for internal use only.
+ 
+ // This module is only for dec2flt and flt2dec, and only public because of coretests.
+ // It is not intended to ever be stabilized.
+ #![doc(hidden)]
+ #![unstable(
+     feature = "core_private_diy_float",
+     reason = "internal routines only exposed for testing",
+     issue = "none"
+ )]
+ 
+ /// A custom 64-bit floating point type, representing `f * 2^e`.
+ #[derive(Copy, Clone, Debug)]
+ #[doc(hidden)]
+ pub struct Fp {
+     /// The integer mantissa.
+     pub f: u64,
+     /// The exponent in base 2.
+     pub e: i16,
+ }
+ 
+ impl Fp {
+     /// Returns a correctly rounded product of itself and `other`.
+     pub fn mul(&self, other: &Fp) -> Fp {
+         const MASK: u64 = 0xffffffff;
+         let a = self.f >> 32;
+         let b = self.f & MASK;
+         let c = other.f >> 32;
+         let d = other.f & MASK;
+         let ac = a * c;
+         let bc = b * c;
+         let ad = a * d;
+         let bd = b * d;
+         let tmp = (bd >> 32) + (ad & MASK) + (bc & MASK) + (1 << 31) /* round */;
+         let f = ac + (ad >> 32) + (bc >> 32) + (tmp >> 32);
+         let e = self.e + other.e + 64;
+         Fp { f, e }
+     }
+ 
+     /// Normalizes itself so that the resulting mantissa is at least `2^63`.
+     pub fn normalize(&self) -> Fp {
+         let mut f = self.f;
+         let mut e = self.e;
+         if f >> (64 - 32) == 0 {
+             f <<= 32;
+             e -= 32;
+         }
+         if f >> (64 - 16) == 0 {
+             f <<= 16;
+             e -= 16;
+         }
+         if f >> (64 - 8) == 0 {
+             f <<= 8;
+             e -= 8;
+         }
+         if f >> (64 - 4) == 0 {
+             f <<= 4;
+             e -= 4;
+         }
+         if f >> (64 - 2) == 0 {
+             f <<= 2;
+             e -= 2;
+         }
+         if f >> (64 - 1) == 0 {
+             f <<= 1;
+             e -= 1;
+         }
+         debug_assert!(f >= (1 >> 63));
+         Fp { f, e }
+     }
+ 
+     /// Normalizes itself to have the shared exponent.
+     /// It can only decrease the exponent (and thus increase the mantissa).
+     pub fn normalize_to(&self, e: i16) -> Fp {
+         let edelta = self.e - e;
+         assert!(edelta >= 0);
+         let edelta = edelta as usize;
+         assert_eq!(self.f << edelta >> edelta, self.f);
+         Fp { f: self.f << edelta, e }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/error.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/error.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/error.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/error.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,154 ----
+ //! Error types for conversion to integral types.
+ 
+ use crate::convert::Infallible;
+ use crate::fmt;
+ 
+ /// The error type returned when a checked integral type conversion fails.
+ #[stable(feature = "try_from", since = "1.34.0")]
+ #[derive(Debug, Copy, Clone, PartialEq, Eq)]
+ pub struct TryFromIntError(pub(crate) ());
+ 
+ impl TryFromIntError {
+     #[unstable(
+         feature = "int_error_internals",
+         reason = "available through Error trait and this method should \
+                   not be exposed publicly",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     pub fn __description(&self) -> &str {
+         "out of range integral type conversion attempted"
+     }
+ }
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl fmt::Display for TryFromIntError {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.__description().fmt(fmt)
+     }
+ }
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ impl From<Infallible> for TryFromIntError {
+     fn from(x: Infallible) -> TryFromIntError {
+         match x {}
+     }
+ }
+ 
+ #[unstable(feature = "never_type", issue = "35121")]
+ impl From<!> for TryFromIntError {
+     fn from(never: !) -> TryFromIntError {
+         // Match rather than coerce to make sure that code like
+         // `From<Infallible> for TryFromIntError` above will keep working
+         // when `Infallible` becomes an alias to `!`.
+         match never {}
+     }
+ }
+ 
+ /// An error which can be returned when parsing an integer.
+ ///
+ /// This error is used as the error type for the `from_str_radix()` functions
+ /// on the primitive integer types, such as [`i8::from_str_radix`].
+ ///
+ /// # Potential causes
+ ///
+ /// Among other causes, `ParseIntError` can be thrown because of leading or trailing whitespace
+ /// in the string e.g., when it is obtained from the standard input.
+ /// Using the [`str.trim()`] method ensures that no whitespace remains before parsing.
+ ///
+ /// [`str.trim()`]: ../../std/primitive.str.html#method.trim
+ /// [`i8::from_str_radix`]: ../../std/primitive.i8.html#method.from_str_radix
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// if let Err(e) = i32::from_str_radix("a12", 10) {
+ ///     println!("Failed conversion to i32: {}", e);
+ /// }
+ /// ```
+ #[derive(Debug, Clone, PartialEq, Eq)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct ParseIntError {
+     pub(super) kind: IntErrorKind,
+ }
+ 
+ /// Enum to store the various types of errors that can cause parsing an integer to fail.
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(int_error_matching)]
+ ///
+ /// # fn main() {
+ /// if let Err(e) = i32::from_str_radix("a12", 10) {
+ ///     println!("Failed conversion to i32: {:?}", e.kind());
+ /// }
+ /// # }
+ /// ```
+ #[unstable(
+     feature = "int_error_matching",
+     reason = "it can be useful to match errors when making error messages \
+               for integer parsing",
+     issue = "22639"
+ )]
+ #[derive(Debug, Clone, PartialEq, Eq)]
+ #[non_exhaustive]
+ pub enum IntErrorKind {
+     /// Value being parsed is empty.
+     ///
+     /// Among other causes, this variant will be constructed when parsing an empty string.
+     Empty,
+     /// Contains an invalid digit in its context.
+     ///
+     /// Among other causes, this variant will be constructed when parsing a string that
+     /// contains a non-ASCII char.
+     ///
+     /// This variant is also constructed when a `+` or `-` is misplaced within a string
+     /// either on its own or in the middle of a number.
+     InvalidDigit,
+     /// Integer is too large to store in target integer type.
+     PosOverflow,
+     /// Integer is too small to store in target integer type.
+     NegOverflow,
+     /// Value was Zero
+     ///
+     /// This variant will be emitted when the parsing string has a value of zero, which
+     /// would be illegal for non-zero types.
+     Zero,
+ }
+ 
+ impl ParseIntError {
+     /// Outputs the detailed cause of parsing an integer failing.
+     #[unstable(
+         feature = "int_error_matching",
+         reason = "it can be useful to match errors when making error messages \
+               for integer parsing",
+         issue = "22639"
+     )]
+     pub fn kind(&self) -> &IntErrorKind {
+         &self.kind
+     }
+     #[unstable(
+         feature = "int_error_internals",
+         reason = "available through Error trait and this method should \
+                   not be exposed publicly",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     pub fn __description(&self) -> &str {
+         match self.kind {
+             IntErrorKind::Empty => "cannot parse integer from empty string",
+             IntErrorKind::InvalidDigit => "invalid digit found in string",
+             IntErrorKind::PosOverflow => "number too large to fit in target type",
+             IntErrorKind::NegOverflow => "number too small to fit in target type",
+             IntErrorKind::Zero => "number would be zero for non-zero type",
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Display for ParseIntError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.__description().fmt(f)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/f32.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/f32.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/f32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/f32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,938 ----
+ //! This module provides constants which are specific to the implementation
+ //! of the `f32` floating point data type.
+ //!
+ //! *[See also the `f32` primitive type](../../std/primitive.f32.html).*
+ //!
+ //! Mathematically significant numbers are provided in the `consts` sub-module.
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::convert::FloatToInt;
+ #[cfg(not(test))]
+ use crate::intrinsics;
+ use crate::mem;
+ use crate::num::FpCategory;
+ 
+ /// The radix or base of the internal representation of `f32`.
+ /// Use [`f32::RADIX`](../../std/primitive.f32.html#associatedconstant.RADIX) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let r = std::f32::RADIX;
+ ///
+ /// // intended way
+ /// let r = f32::RADIX;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const RADIX: u32 = f32::RADIX;
+ 
+ /// Number of significant digits in base 2.
+ /// Use [`f32::MANTISSA_DIGITS`](../../std/primitive.f32.html#associatedconstant.MANTISSA_DIGITS) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let d = std::f32::MANTISSA_DIGITS;
+ ///
+ /// // intended way
+ /// let d = f32::MANTISSA_DIGITS;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MANTISSA_DIGITS: u32 = f32::MANTISSA_DIGITS;
+ 
+ /// Approximate number of significant digits in base 10.
+ /// Use [`f32::DIGITS`](../../std/primitive.f32.html#associatedconstant.DIGITS) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let d = std::f32::DIGITS;
+ ///
+ /// // intended way
+ /// let d = f32::DIGITS;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const DIGITS: u32 = f32::DIGITS;
+ 
+ /// [Machine epsilon] value for `f32`.
+ /// Use [`f32::EPSILON`](../../std/primitive.f32.html#associatedconstant.EPSILON) instead.
+ ///
+ /// This is the difference between `1.0` and the next larger representable number.
+ ///
+ /// [Machine epsilon]: https://en.wikipedia.org/wiki/Machine_epsilon
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let e = std::f32::EPSILON;
+ ///
+ /// // intended way
+ /// let e = f32::EPSILON;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const EPSILON: f32 = f32::EPSILON;
+ 
+ /// Smallest finite `f32` value.
+ /// Use [`f32::MIN`](../../std/primitive.f32.html#associatedconstant.MIN) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f32::MIN;
+ ///
+ /// // intended way
+ /// let min = f32::MIN;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN: f32 = f32::MIN;
+ 
+ /// Smallest positive normal `f32` value.
+ /// Use [`f32::MIN_POSITIVE`](../../std/primitive.f32.html#associatedconstant.MIN_POSITIVE) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f32::MIN_POSITIVE;
+ ///
+ /// // intended way
+ /// let min = f32::MIN_POSITIVE;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN_POSITIVE: f32 = f32::MIN_POSITIVE;
+ 
+ /// Largest finite `f32` value.
+ /// Use [`f32::MAX`](../../std/primitive.f32.html#associatedconstant.MAX) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let max = std::f32::MAX;
+ ///
+ /// // intended way
+ /// let max = f32::MAX;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX: f32 = f32::MAX;
+ 
+ /// One greater than the minimum possible normal power of 2 exponent.
+ /// Use [`f32::MIN_EXP`](../../std/primitive.f32.html#associatedconstant.MIN_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f32::MIN_EXP;
+ ///
+ /// // intended way
+ /// let min = f32::MIN_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN_EXP: i32 = f32::MIN_EXP;
+ 
+ /// Maximum possible power of 2 exponent.
+ /// Use [`f32::MAX_EXP`](../../std/primitive.f32.html#associatedconstant.MAX_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let max = std::f32::MAX_EXP;
+ ///
+ /// // intended way
+ /// let max = f32::MAX_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX_EXP: i32 = f32::MAX_EXP;
+ 
+ /// Minimum possible normal power of 10 exponent.
+ /// Use [`f32::MIN_10_EXP`](../../std/primitive.f32.html#associatedconstant.MIN_10_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f32::MIN_10_EXP;
+ ///
+ /// // intended way
+ /// let min = f32::MIN_10_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN_10_EXP: i32 = f32::MIN_10_EXP;
+ 
+ /// Maximum possible power of 10 exponent.
+ /// Use [`f32::MAX_10_EXP`](../../std/primitive.f32.html#associatedconstant.MAX_10_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let max = std::f32::MAX_10_EXP;
+ ///
+ /// // intended way
+ /// let max = f32::MAX_10_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX_10_EXP: i32 = f32::MAX_10_EXP;
+ 
+ /// Not a Number (NaN).
+ /// Use [`f32::NAN`](../../std/primitive.f32.html#associatedconstant.NAN) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let nan = std::f32::NAN;
+ ///
+ /// // intended way
+ /// let nan = f32::NAN;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const NAN: f32 = f32::NAN;
+ 
+ /// Infinity (∞).
+ /// Use [`f32::INFINITY`](../../std/primitive.f32.html#associatedconstant.INFINITY) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let inf = std::f32::INFINITY;
+ ///
+ /// // intended way
+ /// let inf = f32::INFINITY;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const INFINITY: f32 = f32::INFINITY;
+ 
+ /// Negative infinity (−∞).
+ /// Use [`f32::NEG_INFINITY`](../../std/primitive.f32.html#associatedconstant.NEG_INFINITY) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let ninf = std::f32::NEG_INFINITY;
+ ///
+ /// // intended way
+ /// let ninf = f32::NEG_INFINITY;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const NEG_INFINITY: f32 = f32::NEG_INFINITY;
+ 
+ /// Basic mathematical constants.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub mod consts {
+     // FIXME: replace with mathematical constants from cmath.
+ 
+     /// Archimedes' constant (π)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const PI: f32 = 3.14159265358979323846264338327950288_f32;
+ 
+     /// The full circle constant (τ)
+     ///
+     /// Equal to 2π.
+     #[stable(feature = "tau_constant", since = "1.47.0")]
+     pub const TAU: f32 = 6.28318530717958647692528676655900577_f32;
+ 
+     /// π/2
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_2: f32 = 1.57079632679489661923132169163975144_f32;
+ 
+     /// π/3
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_3: f32 = 1.04719755119659774615421446109316763_f32;
+ 
+     /// π/4
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_4: f32 = 0.785398163397448309615660845819875721_f32;
+ 
+     /// π/6
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_6: f32 = 0.52359877559829887307710723054658381_f32;
+ 
+     /// π/8
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_8: f32 = 0.39269908169872415480783042290993786_f32;
+ 
+     /// 1/π
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_1_PI: f32 = 0.318309886183790671537767526745028724_f32;
+ 
+     /// 2/π
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_2_PI: f32 = 0.636619772367581343075535053490057448_f32;
+ 
+     /// 2/sqrt(π)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_2_SQRT_PI: f32 = 1.12837916709551257389615890312154517_f32;
+ 
+     /// sqrt(2)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const SQRT_2: f32 = 1.41421356237309504880168872420969808_f32;
+ 
+     /// 1/sqrt(2)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_1_SQRT_2: f32 = 0.707106781186547524400844362104849039_f32;
+ 
+     /// Euler's number (e)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const E: f32 = 2.71828182845904523536028747135266250_f32;
+ 
+     /// log<sub>2</sub>(e)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LOG2_E: f32 = 1.44269504088896340735992468100189214_f32;
+ 
+     /// log<sub>2</sub>(10)
+     #[stable(feature = "extra_log_consts", since = "1.43.0")]
+     pub const LOG2_10: f32 = 3.32192809488736234787031942948939018_f32;
+ 
+     /// log<sub>10</sub>(e)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LOG10_E: f32 = 0.434294481903251827651128918916605082_f32;
+ 
+     /// log<sub>10</sub>(2)
+     #[stable(feature = "extra_log_consts", since = "1.43.0")]
+     pub const LOG10_2: f32 = 0.301029995663981195213738894724493027_f32;
+ 
+     /// ln(2)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LN_2: f32 = 0.693147180559945309417232121458176568_f32;
+ 
+     /// ln(10)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LN_10: f32 = 2.30258509299404568401799145468436421_f32;
+ }
+ 
+ #[lang = "f32"]
+ #[cfg(not(test))]
+ impl f32 {
+     /// The radix or base of the internal representation of `f32`.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const RADIX: u32 = 2;
+ 
+     /// Number of significant digits in base 2.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MANTISSA_DIGITS: u32 = 24;
+ 
+     /// Approximate number of significant digits in base 10.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const DIGITS: u32 = 6;
+ 
+     /// [Machine epsilon] value for `f32`.
+     ///
+     /// This is the difference between `1.0` and the next larger representable number.
+     ///
+     /// [Machine epsilon]: https://en.wikipedia.org/wiki/Machine_epsilon
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const EPSILON: f32 = 1.19209290e-07_f32;
+ 
+     /// Smallest finite `f32` value.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN: f32 = -3.40282347e+38_f32;
+     /// Smallest positive normal `f32` value.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN_POSITIVE: f32 = 1.17549435e-38_f32;
+     /// Largest finite `f32` value.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MAX: f32 = 3.40282347e+38_f32;
+ 
+     /// One greater than the minimum possible normal power of 2 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN_EXP: i32 = -125;
+     /// Maximum possible power of 2 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MAX_EXP: i32 = 128;
+ 
+     /// Minimum possible normal power of 10 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN_10_EXP: i32 = -37;
+     /// Maximum possible power of 10 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MAX_10_EXP: i32 = 38;
+ 
+     /// Not a Number (NaN).
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const NAN: f32 = 0.0_f32 / 0.0_f32;
+     /// Infinity (∞).
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const INFINITY: f32 = 1.0_f32 / 0.0_f32;
+     /// Negative infinity (−∞).
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const NEG_INFINITY: f32 = -1.0_f32 / 0.0_f32;
+ 
+     /// Returns `true` if this value is `NaN`.
+     ///
+     /// ```
+     /// let nan = f32::NAN;
+     /// let f = 7.0_f32;
+     ///
+     /// assert!(nan.is_nan());
+     /// assert!(!f.is_nan());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_nan(self) -> bool {
+         self != self
+     }
+ 
+     // FIXME(#50145): `abs` is publicly unavailable in libcore due to
+     // concerns about portability, so this implementation is for
+     // private use internally.
+     #[inline]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     const fn abs_private(self) -> f32 {
+         f32::from_bits(self.to_bits() & 0x7fff_ffff)
+     }
+ 
+     /// Returns `true` if this value is positive infinity or negative infinity, and
+     /// `false` otherwise.
+     ///
+     /// ```
+     /// let f = 7.0f32;
+     /// let inf = f32::INFINITY;
+     /// let neg_inf = f32::NEG_INFINITY;
+     /// let nan = f32::NAN;
+     ///
+     /// assert!(!f.is_infinite());
+     /// assert!(!nan.is_infinite());
+     ///
+     /// assert!(inf.is_infinite());
+     /// assert!(neg_inf.is_infinite());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_infinite(self) -> bool {
+         self.abs_private() == Self::INFINITY
+     }
+ 
+     /// Returns `true` if this number is neither infinite nor `NaN`.
+     ///
+     /// ```
+     /// let f = 7.0f32;
+     /// let inf = f32::INFINITY;
+     /// let neg_inf = f32::NEG_INFINITY;
+     /// let nan = f32::NAN;
+     ///
+     /// assert!(f.is_finite());
+     ///
+     /// assert!(!nan.is_finite());
+     /// assert!(!inf.is_finite());
+     /// assert!(!neg_inf.is_finite());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_finite(self) -> bool {
+         // There's no need to handle NaN separately: if self is NaN,
+         // the comparison is not true, exactly as desired.
+         self.abs_private() < Self::INFINITY
+     }
+ 
+     /// Returns `true` if the number is neither zero, infinite,
+     /// [subnormal], or `NaN`.
+     ///
+     /// ```
+     /// let min = f32::MIN_POSITIVE; // 1.17549435e-38f32
+     /// let max = f32::MAX;
+     /// let lower_than_min = 1.0e-40_f32;
+     /// let zero = 0.0_f32;
+     ///
+     /// assert!(min.is_normal());
+     /// assert!(max.is_normal());
+     ///
+     /// assert!(!zero.is_normal());
+     /// assert!(!f32::NAN.is_normal());
+     /// assert!(!f32::INFINITY.is_normal());
+     /// // Values between `0` and `min` are Subnormal.
+     /// assert!(!lower_than_min.is_normal());
+     /// ```
+     /// [subnormal]: https://en.wikipedia.org/wiki/Denormal_number
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_normal(self) -> bool {
+         matches!(self.classify(), FpCategory::Normal)
+     }
+ 
+     /// Returns the floating point category of the number. If only one property
+     /// is going to be tested, it is generally faster to use the specific
+     /// predicate instead.
+     ///
+     /// ```
+     /// use std::num::FpCategory;
+     ///
+     /// let num = 12.4_f32;
+     /// let inf = f32::INFINITY;
+     ///
+     /// assert_eq!(num.classify(), FpCategory::Normal);
+     /// assert_eq!(inf.classify(), FpCategory::Infinite);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     pub const fn classify(self) -> FpCategory {
+         const EXP_MASK: u32 = 0x7f800000;
+         const MAN_MASK: u32 = 0x007fffff;
+ 
+         let bits = self.to_bits();
+         match (bits & MAN_MASK, bits & EXP_MASK) {
+             (0, 0) => FpCategory::Zero,
+             (_, 0) => FpCategory::Subnormal,
+             (0, EXP_MASK) => FpCategory::Infinite,
+             (_, EXP_MASK) => FpCategory::Nan,
+             _ => FpCategory::Normal,
+         }
+     }
+ 
+     /// Returns `true` if `self` has a positive sign, including `+0.0`, `NaN`s with
+     /// positive sign bit and positive infinity.
+     ///
+     /// ```
+     /// let f = 7.0_f32;
+     /// let g = -7.0_f32;
+     ///
+     /// assert!(f.is_sign_positive());
+     /// assert!(!g.is_sign_positive());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_sign_positive(self) -> bool {
+         !self.is_sign_negative()
+     }
+ 
+     /// Returns `true` if `self` has a negative sign, including `-0.0`, `NaN`s with
+     /// negative sign bit and negative infinity.
+     ///
+     /// ```
+     /// let f = 7.0f32;
+     /// let g = -7.0f32;
+     ///
+     /// assert!(!f.is_sign_negative());
+     /// assert!(g.is_sign_negative());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_sign_negative(self) -> bool {
+         // IEEE754 says: isSignMinus(x) is true if and only if x has negative sign. isSignMinus
+         // applies to zeros and NaNs as well.
+         self.to_bits() & 0x8000_0000 != 0
+     }
+ 
+     /// Takes the reciprocal (inverse) of a number, `1/x`.
+     ///
+     /// ```
+     /// let x = 2.0_f32;
+     /// let abs_difference = (x.recip() - (1.0 / x)).abs();
+     ///
+     /// assert!(abs_difference <= f32::EPSILON);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn recip(self) -> f32 {
+         1.0 / self
+     }
+ 
+     /// Converts radians to degrees.
+     ///
+     /// ```
+     /// let angle = std::f32::consts::PI;
+     ///
+     /// let abs_difference = (angle.to_degrees() - 180.0).abs();
+     ///
+     /// assert!(abs_difference <= f32::EPSILON);
+     /// ```
+     #[stable(feature = "f32_deg_rad_conversions", since = "1.7.0")]
+     #[inline]
+     pub fn to_degrees(self) -> f32 {
+         // Use a constant for better precision.
+         const PIS_IN_180: f32 = 57.2957795130823208767981548141051703_f32;
+         self * PIS_IN_180
+     }
+ 
+     /// Converts degrees to radians.
+     ///
+     /// ```
+     /// let angle = 180.0f32;
+     ///
+     /// let abs_difference = (angle.to_radians() - std::f32::consts::PI).abs();
+     ///
+     /// assert!(abs_difference <= f32::EPSILON);
+     /// ```
+     #[stable(feature = "f32_deg_rad_conversions", since = "1.7.0")]
+     #[inline]
+     pub fn to_radians(self) -> f32 {
+         let value: f32 = consts::PI;
+         self * (value / 180.0f32)
+     }
+ 
+     /// Returns the maximum of the two numbers.
+     ///
+     /// ```
+     /// let x = 1.0f32;
+     /// let y = 2.0f32;
+     ///
+     /// assert_eq!(x.max(y), y);
+     /// ```
+     ///
+     /// If one of the arguments is NaN, then the other argument is returned.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn max(self, other: f32) -> f32 {
+         intrinsics::maxnumf32(self, other)
+     }
+ 
+     /// Returns the minimum of the two numbers.
+     ///
+     /// ```
+     /// let x = 1.0f32;
+     /// let y = 2.0f32;
+     ///
+     /// assert_eq!(x.min(y), x);
+     /// ```
+     ///
+     /// If one of the arguments is NaN, then the other argument is returned.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn min(self, other: f32) -> f32 {
+         intrinsics::minnumf32(self, other)
+     }
+ 
+     /// Rounds toward zero and converts to any primitive integer type,
+     /// assuming that the value is finite and fits in that type.
+     ///
+     /// ```
+     /// let value = 4.6_f32;
+     /// let rounded = unsafe { value.to_int_unchecked::<u16>() };
+     /// assert_eq!(rounded, 4);
+     ///
+     /// let value = -128.9_f32;
+     /// let rounded = unsafe { value.to_int_unchecked::<i8>() };
+     /// assert_eq!(rounded, i8::MIN);
+     /// ```
+     ///
+     /// # Safety
+     ///
+     /// The value must:
+     ///
+     /// * Not be `NaN`
+     /// * Not be infinite
+     /// * Be representable in the return type `Int`, after truncating off its fractional part
+     #[stable(feature = "float_approx_unchecked_to", since = "1.44.0")]
+     #[inline]
+     pub unsafe fn to_int_unchecked<Int>(self) -> Int
+     where
+         Self: FloatToInt<Int>,
+     {
+         // SAFETY: the caller must uphold the safety contract for
+         // `FloatToInt::to_int_unchecked`.
+         unsafe { FloatToInt::<Int>::to_int_unchecked(self) }
+     }
+ 
+     /// Raw transmutation to `u32`.
+     ///
+     /// This is currently identical to `transmute::<f32, u32>(self)` on all platforms.
+     ///
+     /// See `from_bits` for some discussion of the portability of this operation
+     /// (there are almost no issues).
+     ///
+     /// Note that this function is distinct from `as` casting, which attempts to
+     /// preserve the *numeric* value, and not the bitwise value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_ne!((1f32).to_bits(), 1f32 as u32); // to_bits() is not casting!
+     /// assert_eq!((12.5f32).to_bits(), 0x41480000);
+     ///
+     /// ```
+     #[stable(feature = "float_bits_conv", since = "1.20.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_bits(self) -> u32 {
+         // SAFETY: `u32` is a plain old datatype so we can always transmute to it
+         unsafe { mem::transmute(self) }
+     }
+ 
+     /// Raw transmutation from `u32`.
+     ///
+     /// This is currently identical to `transmute::<u32, f32>(v)` on all platforms.
+     /// It turns out this is incredibly portable, for two reasons:
+     ///
+     /// * Floats and Ints have the same endianness on all supported platforms.
+     /// * IEEE-754 very precisely specifies the bit layout of floats.
+     ///
+     /// However there is one caveat: prior to the 2008 version of IEEE-754, how
+     /// to interpret the NaN signaling bit wasn't actually specified. Most platforms
+     /// (notably x86 and ARM) picked the interpretation that was ultimately
+     /// standardized in 2008, but some didn't (notably MIPS). As a result, all
+     /// signaling NaNs on MIPS are quiet NaNs on x86, and vice-versa.
+     ///
+     /// Rather than trying to preserve signaling-ness cross-platform, this
+     /// implementation favors preserving the exact bits. This means that
+     /// any payloads encoded in NaNs will be preserved even if the result of
+     /// this method is sent over the network from an x86 machine to a MIPS one.
+     ///
+     /// If the results of this method are only manipulated by the same
+     /// architecture that produced them, then there is no portability concern.
+     ///
+     /// If the input isn't NaN, then there is no portability concern.
+     ///
+     /// If you don't care about signalingness (very likely), then there is no
+     /// portability concern.
+     ///
+     /// Note that this function is distinct from `as` casting, which attempts to
+     /// preserve the *numeric* value, and not the bitwise value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = f32::from_bits(0x41480000);
+     /// assert_eq!(v, 12.5);
+     /// ```
+     #[stable(feature = "float_bits_conv", since = "1.20.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_bits(v: u32) -> Self {
+         // SAFETY: `u32` is a plain old datatype so we can always transmute from it
+         // It turns out the safety issues with sNaN were overblown! Hooray!
+         unsafe { mem::transmute(v) }
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// big-endian (network) byte order.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let bytes = 12.5f32.to_be_bytes();
+     /// assert_eq!(bytes, [0x41, 0x48, 0x00, 0x00]);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_be_bytes(self) -> [u8; 4] {
+         self.to_bits().to_be_bytes()
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// little-endian byte order.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let bytes = 12.5f32.to_le_bytes();
+     /// assert_eq!(bytes, [0x00, 0x00, 0x48, 0x41]);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_le_bytes(self) -> [u8; 4] {
+         self.to_bits().to_le_bytes()
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// native byte order.
+     ///
+     /// As the target platform's native endianness is used, portable code
+     /// should use [`to_be_bytes`] or [`to_le_bytes`], as appropriate, instead.
+     ///
+     /// [`to_be_bytes`]: #method.to_be_bytes
+     /// [`to_le_bytes`]: #method.to_le_bytes
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let bytes = 12.5f32.to_ne_bytes();
+     /// assert_eq!(
+     ///     bytes,
+     ///     if cfg!(target_endian = "big") {
+     ///         [0x41, 0x48, 0x00, 0x00]
+     ///     } else {
+     ///         [0x00, 0x00, 0x48, 0x41]
+     ///     }
+     /// );
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_ne_bytes(self) -> [u8; 4] {
+         self.to_bits().to_ne_bytes()
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// native byte order.
+     ///
+     /// [`to_ne_bytes`] should be preferred over this whenever possible.
+     ///
+     /// [`to_ne_bytes`]: #method.to_ne_bytes
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(num_as_ne_bytes)]
+     /// let num = 12.5f32;
+     /// let bytes = num.as_ne_bytes();
+     /// assert_eq!(
+     ///     bytes,
+     ///     if cfg!(target_endian = "big") {
+     ///         &[0x41, 0x48, 0x00, 0x00]
+     ///     } else {
+     ///         &[0x00, 0x00, 0x48, 0x41]
+     ///     }
+     /// );
+     /// ```
+     #[unstable(feature = "num_as_ne_bytes", issue = "76976")]
+     #[inline]
+     pub fn as_ne_bytes(&self) -> &[u8; 4] {
+         // SAFETY: `f32` is a plain old datatype so we can always transmute to it
+         unsafe { &*(self as *const Self as *const _) }
+     }
+ 
+     /// Create a floating point value from its representation as a byte array in big endian.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let value = f32::from_be_bytes([0x41, 0x48, 0x00, 0x00]);
+     /// assert_eq!(value, 12.5);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_be_bytes(bytes: [u8; 4]) -> Self {
+         Self::from_bits(u32::from_be_bytes(bytes))
+     }
+ 
+     /// Create a floating point value from its representation as a byte array in little endian.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let value = f32::from_le_bytes([0x00, 0x00, 0x48, 0x41]);
+     /// assert_eq!(value, 12.5);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_le_bytes(bytes: [u8; 4]) -> Self {
+         Self::from_bits(u32::from_le_bytes(bytes))
+     }
+ 
+     /// Create a floating point value from its representation as a byte array in native endian.
+     ///
+     /// As the target platform's native endianness is used, portable code
+     /// likely wants to use [`from_be_bytes`] or [`from_le_bytes`], as
+     /// appropriate instead.
+     ///
+     /// [`from_be_bytes`]: #method.from_be_bytes
+     /// [`from_le_bytes`]: #method.from_le_bytes
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let value = f32::from_ne_bytes(if cfg!(target_endian = "big") {
+     ///     [0x41, 0x48, 0x00, 0x00]
+     /// } else {
+     ///     [0x00, 0x00, 0x48, 0x41]
+     /// });
+     /// assert_eq!(value, 12.5);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_ne_bytes(bytes: [u8; 4]) -> Self {
+         Self::from_bits(u32::from_ne_bytes(bytes))
+     }
+ 
+     /// Returns an ordering between self and other values.
+     /// Unlike the standard partial comparison between floating point numbers,
+     /// this comparison always produces an ordering in accordance to
+     /// the totalOrder predicate as defined in IEEE 754 (2008 revision)
+     /// floating point standard. The values are ordered in following order:
+     /// - Negative quiet NaN
+     /// - Negative signaling NaN
+     /// - Negative infinity
+     /// - Negative numbers
+     /// - Negative subnormal numbers
+     /// - Negative zero
+     /// - Positive zero
+     /// - Positive subnormal numbers
+     /// - Positive numbers
+     /// - Positive infinity
+     /// - Positive signaling NaN
+     /// - Positive quiet NaN
+     ///
+     /// Note that this function does not always agree with the [`PartialOrd`]
+     /// and [`PartialEq`] implementations of `f32`. In particular, they regard
+     /// negative and positive zero as equal, while `total_cmp` doesn't.
+     ///
+     /// # Example
+     /// ```
+     /// #![feature(total_cmp)]
+     /// struct GoodBoy {
+     ///     name: String,
+     ///     weight: f32,
+     /// }
+     ///
+     /// let mut bois = vec![
+     ///     GoodBoy { name: "Pucci".to_owned(), weight: 0.1 },
+     ///     GoodBoy { name: "Woofer".to_owned(), weight: 99.0 },
+     ///     GoodBoy { name: "Yapper".to_owned(), weight: 10.0 },
+     ///     GoodBoy { name: "Chonk".to_owned(), weight: f32::INFINITY },
+     ///     GoodBoy { name: "Abs. Unit".to_owned(), weight: f32::NAN },
+     ///     GoodBoy { name: "Floaty".to_owned(), weight: -5.0 },
+     /// ];
+     ///
+     /// bois.sort_by(|a, b| a.weight.total_cmp(&b.weight));
+     /// # assert!(bois.into_iter().map(|b| b.weight)
+     /// #     .zip([-5.0, 0.1, 10.0, 99.0, f32::INFINITY, f32::NAN].iter())
+     /// #     .all(|(a, b)| a.to_bits() == b.to_bits()))
+     /// ```
+     #[unstable(feature = "total_cmp", issue = "72599")]
+     #[inline]
+     pub fn total_cmp(&self, other: &Self) -> crate::cmp::Ordering {
+         let mut left = self.to_bits() as i32;
+         let mut right = other.to_bits() as i32;
+ 
+         // In case of negatives, flip all the bits except the sign
+         // to achieve a similar layout as two's complement integers
+         //
+         // Why does this work? IEEE 754 floats consist of three fields:
+         // Sign bit, exponent and mantissa. The set of exponent and mantissa
+         // fields as a whole have the property that their bitwise order is
+         // equal to the numeric magnitude where the magnitude is defined.
+         // The magnitude is not normally defined on NaN values, but
+         // IEEE 754 totalOrder defines the NaN values also to follow the
+         // bitwise order. This leads to order explained in the doc comment.
+         // However, the representation of magnitude is the same for negative
+         // and positive numbers – only the sign bit is different.
+         // To easily compare the floats as signed integers, we need to
+         // flip the exponent and mantissa bits in case of negative numbers.
+         // We effectively convert the numbers to "two's complement" form.
+         //
+         // To do the flipping, we construct a mask and XOR against it.
+         // We branchlessly calculate an "all-ones except for the sign bit"
+         // mask from negative-signed values: right shifting sign-extends
+         // the integer, so we "fill" the mask with sign bits, and then
+         // convert to unsigned to push one more zero bit.
+         // On positive values, the mask is all zeros, so it's a no-op.
+         left ^= (((left >> 31) as u32) >> 1) as i32;
+         right ^= (((right >> 31) as u32) >> 1) as i32;
+ 
+         left.cmp(&right)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/f64.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/f64.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/f64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/f64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,952 ----
+ //! This module provides constants which are specific to the implementation
+ //! of the `f64` floating point data type.
+ //!
+ //! *[See also the `f64` primitive type](../../std/primitive.f64.html).*
+ //!
+ //! Mathematically significant numbers are provided in the `consts` sub-module.
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::convert::FloatToInt;
+ #[cfg(not(test))]
+ use crate::intrinsics;
+ use crate::mem;
+ use crate::num::FpCategory;
+ 
+ /// The radix or base of the internal representation of `f64`.
+ /// Use [`f64::RADIX`](../../std/primitive.f64.html#associatedconstant.RADIX) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let r = std::f64::RADIX;
+ ///
+ /// // intended way
+ /// let r = f64::RADIX;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const RADIX: u32 = f64::RADIX;
+ 
+ /// Number of significant digits in base 2.
+ /// Use [`f64::MANTISSA_DIGITS`](../../std/primitive.f64.html#associatedconstant.MANTISSA_DIGITS) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let d = std::f64::MANTISSA_DIGITS;
+ ///
+ /// // intended way
+ /// let d = f64::MANTISSA_DIGITS;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MANTISSA_DIGITS: u32 = f64::MANTISSA_DIGITS;
+ 
+ /// Approximate number of significant digits in base 10.
+ /// Use [`f64::DIGITS`](../../std/primitive.f64.html#associatedconstant.DIGITS) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let d = std::f64::DIGITS;
+ ///
+ /// // intended way
+ /// let d = f64::DIGITS;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const DIGITS: u32 = f64::DIGITS;
+ 
+ /// [Machine epsilon] value for `f64`.
+ /// Use [`f64::EPSILON`](../../std/primitive.f64.html#associatedconstant.EPSILON) instead.
+ ///
+ /// This is the difference between `1.0` and the next larger representable number.
+ ///
+ /// [Machine epsilon]: https://en.wikipedia.org/wiki/Machine_epsilon
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let e = std::f64::EPSILON;
+ ///
+ /// // intended way
+ /// let e = f64::EPSILON;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const EPSILON: f64 = f64::EPSILON;
+ 
+ /// Smallest finite `f64` value.
+ /// Use [`f64::MIN`](../../std/primitive.f64.html#associatedconstant.MIN) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f64::MIN;
+ ///
+ /// // intended way
+ /// let min = f64::MIN;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN: f64 = f64::MIN;
+ 
+ /// Smallest positive normal `f64` value.
+ /// Use [`f64::MIN_POSITIVE`](../../std/primitive.f64.html#associatedconstant.MIN_POSITIVE) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f64::MIN_POSITIVE;
+ ///
+ /// // intended way
+ /// let min = f64::MIN_POSITIVE;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN_POSITIVE: f64 = f64::MIN_POSITIVE;
+ 
+ /// Largest finite `f64` value.
+ /// Use [`f64::MAX`](../../std/primitive.f64.html#associatedconstant.MAX) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let max = std::f64::MAX;
+ ///
+ /// // intended way
+ /// let max = f64::MAX;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX: f64 = f64::MAX;
+ 
+ /// One greater than the minimum possible normal power of 2 exponent.
+ /// Use [`f64::MIN_EXP`](../../std/primitive.f64.html#associatedconstant.MIN_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f64::MIN_EXP;
+ ///
+ /// // intended way
+ /// let min = f64::MIN_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN_EXP: i32 = f64::MIN_EXP;
+ 
+ /// Maximum possible power of 2 exponent.
+ /// Use [`f64::MAX_EXP`](../../std/primitive.f64.html#associatedconstant.MAX_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let max = std::f64::MAX_EXP;
+ ///
+ /// // intended way
+ /// let max = f64::MAX_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX_EXP: i32 = f64::MAX_EXP;
+ 
+ /// Minimum possible normal power of 10 exponent.
+ /// Use [`f64::MIN_10_EXP`](../../std/primitive.f64.html#associatedconstant.MIN_10_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let min = std::f64::MIN_10_EXP;
+ ///
+ /// // intended way
+ /// let min = f64::MIN_10_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MIN_10_EXP: i32 = f64::MIN_10_EXP;
+ 
+ /// Maximum possible power of 10 exponent.
+ /// Use [`f64::MAX_10_EXP`](../../std/primitive.f64.html#associatedconstant.MAX_10_EXP) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let max = std::f64::MAX_10_EXP;
+ ///
+ /// // intended way
+ /// let max = f64::MAX_10_EXP;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const MAX_10_EXP: i32 = f64::MAX_10_EXP;
+ 
+ /// Not a Number (NaN).
+ /// Use [`f64::NAN`](../../std/primitive.f64.html#associatedconstant.NAN) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let nan = std::f64::NAN;
+ ///
+ /// // intended way
+ /// let nan = f64::NAN;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const NAN: f64 = f64::NAN;
+ 
+ /// Infinity (∞).
+ /// Use [`f64::INFINITY`](../../std/primitive.f64.html#associatedconstant.INFINITY) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let inf = std::f64::INFINITY;
+ ///
+ /// // intended way
+ /// let inf = f64::INFINITY;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const INFINITY: f64 = f64::INFINITY;
+ 
+ /// Negative infinity (−∞).
+ /// Use [`f64::NEG_INFINITY`](../../std/primitive.f64.html#associatedconstant.NEG_INFINITY) instead.
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// // deprecated way
+ /// let ninf = std::f64::NEG_INFINITY;
+ ///
+ /// // intended way
+ /// let ninf = f64::NEG_INFINITY;
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub const NEG_INFINITY: f64 = f64::NEG_INFINITY;
+ 
+ /// Basic mathematical constants.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub mod consts {
+     // FIXME: replace with mathematical constants from cmath.
+ 
+     /// Archimedes' constant (π)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const PI: f64 = 3.14159265358979323846264338327950288_f64;
+ 
+     /// The full circle constant (τ)
+     ///
+     /// Equal to 2π.
+     #[stable(feature = "tau_constant", since = "1.47.0")]
+     pub const TAU: f64 = 6.28318530717958647692528676655900577_f64;
+ 
+     /// π/2
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_2: f64 = 1.57079632679489661923132169163975144_f64;
+ 
+     /// π/3
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_3: f64 = 1.04719755119659774615421446109316763_f64;
+ 
+     /// π/4
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_4: f64 = 0.785398163397448309615660845819875721_f64;
+ 
+     /// π/6
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_6: f64 = 0.52359877559829887307710723054658381_f64;
+ 
+     /// π/8
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_PI_8: f64 = 0.39269908169872415480783042290993786_f64;
+ 
+     /// 1/π
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_1_PI: f64 = 0.318309886183790671537767526745028724_f64;
+ 
+     /// 2/π
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_2_PI: f64 = 0.636619772367581343075535053490057448_f64;
+ 
+     /// 2/sqrt(π)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_2_SQRT_PI: f64 = 1.12837916709551257389615890312154517_f64;
+ 
+     /// sqrt(2)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const SQRT_2: f64 = 1.41421356237309504880168872420969808_f64;
+ 
+     /// 1/sqrt(2)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const FRAC_1_SQRT_2: f64 = 0.707106781186547524400844362104849039_f64;
+ 
+     /// Euler's number (e)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const E: f64 = 2.71828182845904523536028747135266250_f64;
+ 
+     /// log<sub>2</sub>(10)
+     #[stable(feature = "extra_log_consts", since = "1.43.0")]
+     pub const LOG2_10: f64 = 3.32192809488736234787031942948939018_f64;
+ 
+     /// log<sub>2</sub>(e)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LOG2_E: f64 = 1.44269504088896340735992468100189214_f64;
+ 
+     /// log<sub>10</sub>(2)
+     #[stable(feature = "extra_log_consts", since = "1.43.0")]
+     pub const LOG10_2: f64 = 0.301029995663981195213738894724493027_f64;
+ 
+     /// log<sub>10</sub>(e)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LOG10_E: f64 = 0.434294481903251827651128918916605082_f64;
+ 
+     /// ln(2)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LN_2: f64 = 0.693147180559945309417232121458176568_f64;
+ 
+     /// ln(10)
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const LN_10: f64 = 2.30258509299404568401799145468436421_f64;
+ }
+ 
+ #[lang = "f64"]
+ #[cfg(not(test))]
+ impl f64 {
+     /// The radix or base of the internal representation of `f64`.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const RADIX: u32 = 2;
+ 
+     /// Number of significant digits in base 2.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MANTISSA_DIGITS: u32 = 53;
+     /// Approximate number of significant digits in base 10.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const DIGITS: u32 = 15;
+ 
+     /// [Machine epsilon] value for `f64`.
+     ///
+     /// This is the difference between `1.0` and the next larger representable number.
+     ///
+     /// [Machine epsilon]: https://en.wikipedia.org/wiki/Machine_epsilon
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const EPSILON: f64 = 2.2204460492503131e-16_f64;
+ 
+     /// Smallest finite `f64` value.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN: f64 = -1.7976931348623157e+308_f64;
+     /// Smallest positive normal `f64` value.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN_POSITIVE: f64 = 2.2250738585072014e-308_f64;
+     /// Largest finite `f64` value.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MAX: f64 = 1.7976931348623157e+308_f64;
+ 
+     /// One greater than the minimum possible normal power of 2 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN_EXP: i32 = -1021;
+     /// Maximum possible power of 2 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MAX_EXP: i32 = 1024;
+ 
+     /// Minimum possible normal power of 10 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MIN_10_EXP: i32 = -307;
+     /// Maximum possible power of 10 exponent.
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const MAX_10_EXP: i32 = 308;
+ 
+     /// Not a Number (NaN).
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const NAN: f64 = 0.0_f64 / 0.0_f64;
+     /// Infinity (∞).
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const INFINITY: f64 = 1.0_f64 / 0.0_f64;
+     /// Negative infinity (−∞).
+     #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+     pub const NEG_INFINITY: f64 = -1.0_f64 / 0.0_f64;
+ 
+     /// Returns `true` if this value is `NaN`.
+     ///
+     /// ```
+     /// let nan = f64::NAN;
+     /// let f = 7.0_f64;
+     ///
+     /// assert!(nan.is_nan());
+     /// assert!(!f.is_nan());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_nan(self) -> bool {
+         self != self
+     }
+ 
+     // FIXME(#50145): `abs` is publicly unavailable in libcore due to
+     // concerns about portability, so this implementation is for
+     // private use internally.
+     #[inline]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     const fn abs_private(self) -> f64 {
+         f64::from_bits(self.to_bits() & 0x7fff_ffff_ffff_ffff)
+     }
+ 
+     /// Returns `true` if this value is positive infinity or negative infinity, and
+     /// `false` otherwise.
+     ///
+     /// ```
+     /// let f = 7.0f64;
+     /// let inf = f64::INFINITY;
+     /// let neg_inf = f64::NEG_INFINITY;
+     /// let nan = f64::NAN;
+     ///
+     /// assert!(!f.is_infinite());
+     /// assert!(!nan.is_infinite());
+     ///
+     /// assert!(inf.is_infinite());
+     /// assert!(neg_inf.is_infinite());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_infinite(self) -> bool {
+         self.abs_private() == Self::INFINITY
+     }
+ 
+     /// Returns `true` if this number is neither infinite nor `NaN`.
+     ///
+     /// ```
+     /// let f = 7.0f64;
+     /// let inf: f64 = f64::INFINITY;
+     /// let neg_inf: f64 = f64::NEG_INFINITY;
+     /// let nan: f64 = f64::NAN;
+     ///
+     /// assert!(f.is_finite());
+     ///
+     /// assert!(!nan.is_finite());
+     /// assert!(!inf.is_finite());
+     /// assert!(!neg_inf.is_finite());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_finite(self) -> bool {
+         // There's no need to handle NaN separately: if self is NaN,
+         // the comparison is not true, exactly as desired.
+         self.abs_private() < Self::INFINITY
+     }
+ 
+     /// Returns `true` if the number is neither zero, infinite,
+     /// [subnormal], or `NaN`.
+     ///
+     /// ```
+     /// let min = f64::MIN_POSITIVE; // 2.2250738585072014e-308f64
+     /// let max = f64::MAX;
+     /// let lower_than_min = 1.0e-308_f64;
+     /// let zero = 0.0f64;
+     ///
+     /// assert!(min.is_normal());
+     /// assert!(max.is_normal());
+     ///
+     /// assert!(!zero.is_normal());
+     /// assert!(!f64::NAN.is_normal());
+     /// assert!(!f64::INFINITY.is_normal());
+     /// // Values between `0` and `min` are Subnormal.
+     /// assert!(!lower_than_min.is_normal());
+     /// ```
+     /// [subnormal]: https://en.wikipedia.org/wiki/Denormal_number
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_normal(self) -> bool {
+         matches!(self.classify(), FpCategory::Normal)
+     }
+ 
+     /// Returns the floating point category of the number. If only one property
+     /// is going to be tested, it is generally faster to use the specific
+     /// predicate instead.
+     ///
+     /// ```
+     /// use std::num::FpCategory;
+     ///
+     /// let num = 12.4_f64;
+     /// let inf = f64::INFINITY;
+     ///
+     /// assert_eq!(num.classify(), FpCategory::Normal);
+     /// assert_eq!(inf.classify(), FpCategory::Infinite);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     pub const fn classify(self) -> FpCategory {
+         const EXP_MASK: u64 = 0x7ff0000000000000;
+         const MAN_MASK: u64 = 0x000fffffffffffff;
+ 
+         let bits = self.to_bits();
+         match (bits & MAN_MASK, bits & EXP_MASK) {
+             (0, 0) => FpCategory::Zero,
+             (_, 0) => FpCategory::Subnormal,
+             (0, EXP_MASK) => FpCategory::Infinite,
+             (_, EXP_MASK) => FpCategory::Nan,
+             _ => FpCategory::Normal,
+         }
+     }
+ 
+     /// Returns `true` if `self` has a positive sign, including `+0.0`, `NaN`s with
+     /// positive sign bit and positive infinity.
+     ///
+     /// ```
+     /// let f = 7.0_f64;
+     /// let g = -7.0_f64;
+     ///
+     /// assert!(f.is_sign_positive());
+     /// assert!(!g.is_sign_positive());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_sign_positive(self) -> bool {
+         !self.is_sign_negative()
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(since = "1.0.0", reason = "renamed to is_sign_positive")]
+     #[inline]
+     #[doc(hidden)]
+     pub fn is_positive(self) -> bool {
+         self.is_sign_positive()
+     }
+ 
+     /// Returns `true` if `self` has a negative sign, including `-0.0`, `NaN`s with
+     /// negative sign bit and negative infinity.
+     ///
+     /// ```
+     /// let f = 7.0_f64;
+     /// let g = -7.0_f64;
+     ///
+     /// assert!(!f.is_sign_negative());
+     /// assert!(g.is_sign_negative());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_float_classify", issue = "72505")]
+     #[inline]
+     pub const fn is_sign_negative(self) -> bool {
+         self.to_bits() & 0x8000_0000_0000_0000 != 0
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(since = "1.0.0", reason = "renamed to is_sign_negative")]
+     #[inline]
+     #[doc(hidden)]
+     pub fn is_negative(self) -> bool {
+         self.is_sign_negative()
+     }
+ 
+     /// Takes the reciprocal (inverse) of a number, `1/x`.
+     ///
+     /// ```
+     /// let x = 2.0_f64;
+     /// let abs_difference = (x.recip() - (1.0 / x)).abs();
+     ///
+     /// assert!(abs_difference < 1e-10);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn recip(self) -> f64 {
+         1.0 / self
+     }
+ 
+     /// Converts radians to degrees.
+     ///
+     /// ```
+     /// let angle = std::f64::consts::PI;
+     ///
+     /// let abs_difference = (angle.to_degrees() - 180.0).abs();
+     ///
+     /// assert!(abs_difference < 1e-10);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn to_degrees(self) -> f64 {
+         // The division here is correctly rounded with respect to the true
+         // value of 180/π. (This differs from f32, where a constant must be
+         // used to ensure a correctly rounded result.)
+         self * (180.0f64 / consts::PI)
+     }
+ 
+     /// Converts degrees to radians.
+     ///
+     /// ```
+     /// let angle = 180.0_f64;
+     ///
+     /// let abs_difference = (angle.to_radians() - std::f64::consts::PI).abs();
+     ///
+     /// assert!(abs_difference < 1e-10);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn to_radians(self) -> f64 {
+         let value: f64 = consts::PI;
+         self * (value / 180.0)
+     }
+ 
+     /// Returns the maximum of the two numbers.
+     ///
+     /// ```
+     /// let x = 1.0_f64;
+     /// let y = 2.0_f64;
+     ///
+     /// assert_eq!(x.max(y), y);
+     /// ```
+     ///
+     /// If one of the arguments is NaN, then the other argument is returned.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn max(self, other: f64) -> f64 {
+         intrinsics::maxnumf64(self, other)
+     }
+ 
+     /// Returns the minimum of the two numbers.
+     ///
+     /// ```
+     /// let x = 1.0_f64;
+     /// let y = 2.0_f64;
+     ///
+     /// assert_eq!(x.min(y), x);
+     /// ```
+     ///
+     /// If one of the arguments is NaN, then the other argument is returned.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn min(self, other: f64) -> f64 {
+         intrinsics::minnumf64(self, other)
+     }
+ 
+     /// Rounds toward zero and converts to any primitive integer type,
+     /// assuming that the value is finite and fits in that type.
+     ///
+     /// ```
+     /// let value = 4.6_f64;
+     /// let rounded = unsafe { value.to_int_unchecked::<u16>() };
+     /// assert_eq!(rounded, 4);
+     ///
+     /// let value = -128.9_f64;
+     /// let rounded = unsafe { value.to_int_unchecked::<i8>() };
+     /// assert_eq!(rounded, i8::MIN);
+     /// ```
+     ///
+     /// # Safety
+     ///
+     /// The value must:
+     ///
+     /// * Not be `NaN`
+     /// * Not be infinite
+     /// * Be representable in the return type `Int`, after truncating off its fractional part
+     #[stable(feature = "float_approx_unchecked_to", since = "1.44.0")]
+     #[inline]
+     pub unsafe fn to_int_unchecked<Int>(self) -> Int
+     where
+         Self: FloatToInt<Int>,
+     {
+         // SAFETY: the caller must uphold the safety contract for
+         // `FloatToInt::to_int_unchecked`.
+         unsafe { FloatToInt::<Int>::to_int_unchecked(self) }
+     }
+ 
+     /// Raw transmutation to `u64`.
+     ///
+     /// This is currently identical to `transmute::<f64, u64>(self)` on all platforms.
+     ///
+     /// See `from_bits` for some discussion of the portability of this operation
+     /// (there are almost no issues).
+     ///
+     /// Note that this function is distinct from `as` casting, which attempts to
+     /// preserve the *numeric* value, and not the bitwise value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!((1f64).to_bits() != 1f64 as u64); // to_bits() is not casting!
+     /// assert_eq!((12.5f64).to_bits(), 0x4029000000000000);
+     ///
+     /// ```
+     #[stable(feature = "float_bits_conv", since = "1.20.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_bits(self) -> u64 {
+         // SAFETY: `u64` is a plain old datatype so we can always transmute to it
+         unsafe { mem::transmute(self) }
+     }
+ 
+     /// Raw transmutation from `u64`.
+     ///
+     /// This is currently identical to `transmute::<u64, f64>(v)` on all platforms.
+     /// It turns out this is incredibly portable, for two reasons:
+     ///
+     /// * Floats and Ints have the same endianness on all supported platforms.
+     /// * IEEE-754 very precisely specifies the bit layout of floats.
+     ///
+     /// However there is one caveat: prior to the 2008 version of IEEE-754, how
+     /// to interpret the NaN signaling bit wasn't actually specified. Most platforms
+     /// (notably x86 and ARM) picked the interpretation that was ultimately
+     /// standardized in 2008, but some didn't (notably MIPS). As a result, all
+     /// signaling NaNs on MIPS are quiet NaNs on x86, and vice-versa.
+     ///
+     /// Rather than trying to preserve signaling-ness cross-platform, this
+     /// implementation favors preserving the exact bits. This means that
+     /// any payloads encoded in NaNs will be preserved even if the result of
+     /// this method is sent over the network from an x86 machine to a MIPS one.
+     ///
+     /// If the results of this method are only manipulated by the same
+     /// architecture that produced them, then there is no portability concern.
+     ///
+     /// If the input isn't NaN, then there is no portability concern.
+     ///
+     /// If you don't care about signaling-ness (very likely), then there is no
+     /// portability concern.
+     ///
+     /// Note that this function is distinct from `as` casting, which attempts to
+     /// preserve the *numeric* value, and not the bitwise value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = f64::from_bits(0x4029000000000000);
+     /// assert_eq!(v, 12.5);
+     /// ```
+     #[stable(feature = "float_bits_conv", since = "1.20.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_bits(v: u64) -> Self {
+         // SAFETY: `u64` is a plain old datatype so we can always transmute from it
+         // It turns out the safety issues with sNaN were overblown! Hooray!
+         unsafe { mem::transmute(v) }
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// big-endian (network) byte order.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let bytes = 12.5f64.to_be_bytes();
+     /// assert_eq!(bytes, [0x40, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_be_bytes(self) -> [u8; 8] {
+         self.to_bits().to_be_bytes()
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// little-endian byte order.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let bytes = 12.5f64.to_le_bytes();
+     /// assert_eq!(bytes, [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x40]);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_le_bytes(self) -> [u8; 8] {
+         self.to_bits().to_le_bytes()
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// native byte order.
+     ///
+     /// As the target platform's native endianness is used, portable code
+     /// should use [`to_be_bytes`] or [`to_le_bytes`], as appropriate, instead.
+     ///
+     /// [`to_be_bytes`]: #method.to_be_bytes
+     /// [`to_le_bytes`]: #method.to_le_bytes
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let bytes = 12.5f64.to_ne_bytes();
+     /// assert_eq!(
+     ///     bytes,
+     ///     if cfg!(target_endian = "big") {
+     ///         [0x40, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]
+     ///     } else {
+     ///         [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x40]
+     ///     }
+     /// );
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn to_ne_bytes(self) -> [u8; 8] {
+         self.to_bits().to_ne_bytes()
+     }
+ 
+     /// Return the memory representation of this floating point number as a byte array in
+     /// native byte order.
+     ///
+     /// [`to_ne_bytes`] should be preferred over this whenever possible.
+     ///
+     /// [`to_ne_bytes`]: #method.to_ne_bytes
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(num_as_ne_bytes)]
+     /// let num = 12.5f64;
+     /// let bytes = num.as_ne_bytes();
+     /// assert_eq!(
+     ///     bytes,
+     ///     if cfg!(target_endian = "big") {
+     ///         &[0x40, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]
+     ///     } else {
+     ///         &[0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x40]
+     ///     }
+     /// );
+     /// ```
+     #[unstable(feature = "num_as_ne_bytes", issue = "76976")]
+     #[inline]
+     pub fn as_ne_bytes(&self) -> &[u8; 8] {
+         // SAFETY: `f64` is a plain old datatype so we can always transmute to it
+         unsafe { &*(self as *const Self as *const _) }
+     }
+ 
+     /// Create a floating point value from its representation as a byte array in big endian.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let value = f64::from_be_bytes([0x40, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]);
+     /// assert_eq!(value, 12.5);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_be_bytes(bytes: [u8; 8]) -> Self {
+         Self::from_bits(u64::from_be_bytes(bytes))
+     }
+ 
+     /// Create a floating point value from its representation as a byte array in little endian.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let value = f64::from_le_bytes([0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x40]);
+     /// assert_eq!(value, 12.5);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_le_bytes(bytes: [u8; 8]) -> Self {
+         Self::from_bits(u64::from_le_bytes(bytes))
+     }
+ 
+     /// Create a floating point value from its representation as a byte array in native endian.
+     ///
+     /// As the target platform's native endianness is used, portable code
+     /// likely wants to use [`from_be_bytes`] or [`from_le_bytes`], as
+     /// appropriate instead.
+     ///
+     /// [`from_be_bytes`]: #method.from_be_bytes
+     /// [`from_le_bytes`]: #method.from_le_bytes
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let value = f64::from_ne_bytes(if cfg!(target_endian = "big") {
+     ///     [0x40, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]
+     /// } else {
+     ///     [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x40]
+     /// });
+     /// assert_eq!(value, 12.5);
+     /// ```
+     #[stable(feature = "float_to_from_bytes", since = "1.40.0")]
+     #[rustc_const_unstable(feature = "const_float_bits_conv", issue = "72447")]
+     #[inline]
+     pub const fn from_ne_bytes(bytes: [u8; 8]) -> Self {
+         Self::from_bits(u64::from_ne_bytes(bytes))
+     }
+ 
+     /// Returns an ordering between self and other values.
+     /// Unlike the standard partial comparison between floating point numbers,
+     /// this comparison always produces an ordering in accordance to
+     /// the totalOrder predicate as defined in IEEE 754 (2008 revision)
+     /// floating point standard. The values are ordered in following order:
+     /// - Negative quiet NaN
+     /// - Negative signaling NaN
+     /// - Negative infinity
+     /// - Negative numbers
+     /// - Negative subnormal numbers
+     /// - Negative zero
+     /// - Positive zero
+     /// - Positive subnormal numbers
+     /// - Positive numbers
+     /// - Positive infinity
+     /// - Positive signaling NaN
+     /// - Positive quiet NaN
+     ///
+     /// Note that this function does not always agree with the [`PartialOrd`]
+     /// and [`PartialEq`] implementations of `f64`. In particular, they regard
+     /// negative and positive zero as equal, while `total_cmp` doesn't.
+     ///
+     /// # Example
+     /// ```
+     /// #![feature(total_cmp)]
+     /// struct GoodBoy {
+     ///     name: String,
+     ///     weight: f64,
+     /// }
+     ///
+     /// let mut bois = vec![
+     ///     GoodBoy { name: "Pucci".to_owned(), weight: 0.1 },
+     ///     GoodBoy { name: "Woofer".to_owned(), weight: 99.0 },
+     ///     GoodBoy { name: "Yapper".to_owned(), weight: 10.0 },
+     ///     GoodBoy { name: "Chonk".to_owned(), weight: f64::INFINITY },
+     ///     GoodBoy { name: "Abs. Unit".to_owned(), weight: f64::NAN },
+     ///     GoodBoy { name: "Floaty".to_owned(), weight: -5.0 },
+     /// ];
+     ///
+     /// bois.sort_by(|a, b| a.weight.total_cmp(&b.weight));
+     /// # assert!(bois.into_iter().map(|b| b.weight)
+     /// #     .zip([-5.0, 0.1, 10.0, 99.0, f64::INFINITY, f64::NAN].iter())
+     /// #     .all(|(a, b)| a.to_bits() == b.to_bits()))
+     /// ```
+     #[unstable(feature = "total_cmp", issue = "72599")]
+     #[inline]
+     pub fn total_cmp(&self, other: &Self) -> crate::cmp::Ordering {
+         let mut left = self.to_bits() as i64;
+         let mut right = other.to_bits() as i64;
+ 
+         // In case of negatives, flip all the bits except the sign
+         // to achieve a similar layout as two's complement integers
+         //
+         // Why does this work? IEEE 754 floats consist of three fields:
+         // Sign bit, exponent and mantissa. The set of exponent and mantissa
+         // fields as a whole have the property that their bitwise order is
+         // equal to the numeric magnitude where the magnitude is defined.
+         // The magnitude is not normally defined on NaN values, but
+         // IEEE 754 totalOrder defines the NaN values also to follow the
+         // bitwise order. This leads to order explained in the doc comment.
+         // However, the representation of magnitude is the same for negative
+         // and positive numbers – only the sign bit is different.
+         // To easily compare the floats as signed integers, we need to
+         // flip the exponent and mantissa bits in case of negative numbers.
+         // We effectively convert the numbers to "two's complement" form.
+         //
+         // To do the flipping, we construct a mask and XOR against it.
+         // We branchlessly calculate an "all-ones except for the sign bit"
+         // mask from negative-signed values: right shifting sign-extends
+         // the integer, so we "fill" the mask with sign bits, and then
+         // convert to unsigned to push one more zero bit.
+         // On positive values, the mask is all zeros, so it's a no-op.
+         left ^= (((left >> 63) as u64) >> 1) as i64;
+         right ^= (((right >> 63) as u64) >> 1) as i64;
+ 
+         left.cmp(&right)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/decoder.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/decoder.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/decoder.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/decoder.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,100 ----
+ //! Decodes a floating-point value into individual parts and error ranges.
+ 
+ use crate::num::dec2flt::rawfp::RawFloat;
+ use crate::num::FpCategory;
+ 
+ /// Decoded unsigned finite value, such that:
+ ///
+ /// - The original value equals to `mant * 2^exp`.
+ ///
+ /// - Any number from `(mant - minus) * 2^exp` to `(mant + plus) * 2^exp` will
+ ///   round to the original value. The range is inclusive only when
+ ///   `inclusive` is `true`.
+ #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+ pub struct Decoded {
+     /// The scaled mantissa.
+     pub mant: u64,
+     /// The lower error range.
+     pub minus: u64,
+     /// The upper error range.
+     pub plus: u64,
+     /// The shared exponent in base 2.
+     pub exp: i16,
+     /// True when the error range is inclusive.
+     ///
+     /// In IEEE 754, this is true when the original mantissa was even.
+     pub inclusive: bool,
+ }
+ 
+ /// Decoded unsigned value.
+ #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+ pub enum FullDecoded {
+     /// Not-a-number.
+     Nan,
+     /// Infinities, either positive or negative.
+     Infinite,
+     /// Zero, either positive or negative.
+     Zero,
+     /// Finite numbers with further decoded fields.
+     Finite(Decoded),
+ }
+ 
+ /// A floating point type which can be `decode`d.
+ pub trait DecodableFloat: RawFloat + Copy {
+     /// The minimum positive normalized value.
+     fn min_pos_norm_value() -> Self;
+ }
+ 
+ impl DecodableFloat for f32 {
+     fn min_pos_norm_value() -> Self {
+         f32::MIN_POSITIVE
+     }
+ }
+ 
+ impl DecodableFloat for f64 {
+     fn min_pos_norm_value() -> Self {
+         f64::MIN_POSITIVE
+     }
+ }
+ 
+ /// Returns a sign (true when negative) and `FullDecoded` value
+ /// from given floating point number.
+ pub fn decode<T: DecodableFloat>(v: T) -> (/*negative?*/ bool, FullDecoded) {
+     let (mant, exp, sign) = v.integer_decode();
+     let even = (mant & 1) == 0;
+     let decoded = match v.classify() {
+         FpCategory::Nan => FullDecoded::Nan,
+         FpCategory::Infinite => FullDecoded::Infinite,
+         FpCategory::Zero => FullDecoded::Zero,
+         FpCategory::Subnormal => {
+             // neighbors: (mant - 2, exp) -- (mant, exp) -- (mant + 2, exp)
+             // Float::integer_decode always preserves the exponent,
+             // so the mantissa is scaled for subnormals.
+             FullDecoded::Finite(Decoded { mant, minus: 1, plus: 1, exp, inclusive: even })
+         }
+         FpCategory::Normal => {
+             let minnorm = <T as DecodableFloat>::min_pos_norm_value().integer_decode();
+             if mant == minnorm.0 {
+                 // neighbors: (maxmant, exp - 1) -- (minnormmant, exp) -- (minnormmant + 1, exp)
+                 // where maxmant = minnormmant * 2 - 1
+                 FullDecoded::Finite(Decoded {
+                     mant: mant << 2,
+                     minus: 1,
+                     plus: 2,
+                     exp: exp - 2,
+                     inclusive: even,
+                 })
+             } else {
+                 // neighbors: (mant - 1, exp) -- (mant, exp) -- (mant + 1, exp)
+                 FullDecoded::Finite(Decoded {
+                     mant: mant << 1,
+                     minus: 1,
+                     plus: 1,
+                     exp: exp - 1,
+                     inclusive: even,
+                 })
+             }
+         }
+     };
+     (sign < 0, decoded)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/estimator.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/estimator.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/estimator.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/estimator.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,14 ----
+ //! The exponent estimator.
+ 
+ /// Finds `k_0` such that `10^(k_0-1) < mant * 2^exp <= 10^(k_0+1)`.
+ ///
+ /// This is used to approximate `k = ceil(log_10 (mant * 2^exp))`;
+ /// the true `k` is either `k_0` or `k_0+1`.
+ #[doc(hidden)]
+ pub fn estimate_scaling_factor(mant: u64, exp: i16) -> i16 {
+     // 2^(nbits-1) < mant <= 2^nbits if mant > 0
+     let nbits = 64 - (mant - 1).leading_zeros() as i64;
+     // 1292913986 = floor(2^32 * log_10 2)
+     // therefore this always underestimates (or is exact), but not much.
+     (((nbits + exp as i64) * 1292913986) >> 32) as i16
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,793 ----
+ /*!
+ 
+ Floating-point number to decimal conversion routines.
+ 
+ # Problem statement
+ 
+ We are given the floating-point number `v = f * 2^e` with an integer `f`,
+ and its bounds `minus` and `plus` such that any number between `v - minus` and
+ `v + plus` will be rounded to `v`. For the simplicity we assume that
+ this range is exclusive. Then we would like to get the unique decimal
+ representation `V = 0.d[0..n-1] * 10^k` such that:
+ 
+ - `d[0]` is non-zero.
+ 
+ - It's correctly rounded when parsed back: `v - minus < V < v + plus`.
+   Furthermore it is shortest such one, i.e., there is no representation
+   with less than `n` digits that is correctly rounded.
+ 
+ - It's closest to the original value: `abs(V - v) <= 10^(k-n) / 2`. Note that
+   there might be two representations satisfying this uniqueness requirement,
+   in which case some tie-breaking mechanism is used.
+ 
+ We will call this mode of operation as to the *shortest* mode. This mode is used
+ when there is no additional constraint, and can be thought as a "natural" mode
+ as it matches the ordinary intuition (it at least prints `0.1f32` as "0.1").
+ 
+ We have two more modes of operation closely related to each other. In these modes
+ we are given either the number of significant digits `n` or the last-digit
+ limitation `limit` (which determines the actual `n`), and we would like to get
+ the representation `V = 0.d[0..n-1] * 10^k` such that:
+ 
+ - `d[0]` is non-zero, unless `n` was zero in which case only `k` is returned.
+ 
+ - It's closest to the original value: `abs(V - v) <= 10^(k-n) / 2`. Again,
+   there might be some tie-breaking mechanism.
+ 
+ When `limit` is given but not `n`, we set `n` such that `k - n = limit`
+ so that the last digit `d[n-1]` is scaled by `10^(k-n) = 10^limit`.
+ If such `n` is negative, we clip it to zero so that we will only get `k`.
+ We are also limited by the supplied buffer. This limitation is used to print
+ the number up to given number of fractional digits without knowing
+ the correct `k` beforehand.
+ 
+ We will call the mode of operation requiring `n` as to the *exact* mode,
+ and one requiring `limit` as to the *fixed* mode. The exact mode is a subset of
+ the fixed mode: the sufficiently large last-digit limitation will eventually fill
+ the supplied buffer and let the algorithm to return.
+ 
+ # Implementation overview
+ 
+ It is easy to get the floating point printing correct but slow (Russ Cox has
+ [demonstrated](http://research.swtch.com/ftoa) how it's easy), or incorrect but
+ fast (naïve division and modulo). But it is surprisingly hard to print
+ floating point numbers correctly *and* efficiently.
+ 
+ There are two classes of algorithms widely known to be correct.
+ 
+ - The "Dragon" family of algorithm is first described by Guy L. Steele Jr. and
+   Jon L. White. They rely on the fixed-size big integer for their correctness.
+   A slight improvement was found later, which is posthumously described by
+   Robert G. Burger and R. Kent Dybvig. David Gay's `dtoa.c` routine is
+   a popular implementation of this strategy.
+ 
+ - The "Grisu" family of algorithm is first described by Florian Loitsch.
+   They use very cheap integer-only procedure to determine the close-to-correct
+   representation which is at least guaranteed to be shortest. The variant,
+   Grisu3, actively detects if the resulting representation is incorrect.
+ 
+ We implement both algorithms with necessary tweaks to suit our requirements.
+ In particular, published literatures are short of the actual implementation
+ difficulties like how to avoid arithmetic overflows. Each implementation,
+ available in `strategy::dragon` and `strategy::grisu` respectively,
+ extensively describes all necessary justifications and many proofs for them.
+ (It is still difficult to follow though. You have been warned.)
+ 
+ Both implementations expose two public functions:
+ 
+ - `format_shortest(decoded, buf)`, which always needs at least
+   `MAX_SIG_DIGITS` digits of buffer. Implements the shortest mode.
+ 
+ - `format_exact(decoded, buf, limit)`, which accepts as small as
+   one digit of buffer. Implements exact and fixed modes.
+ 
+ They try to fill the `u8` buffer with digits and returns the number of digits
+ written and the exponent `k`. They are total for all finite `f32` and `f64`
+ inputs (Grisu internally falls back to Dragon if necessary).
+ 
+ The rendered digits are formatted into the actual string form with
+ four functions:
+ 
+ - `to_shortest_str` prints the shortest representation, which can be padded by
+   zeroes to make *at least* given number of fractional digits.
+ 
+ - `to_shortest_exp_str` prints the shortest representation, which can be
+   padded by zeroes when its exponent is in the specified ranges,
+   or can be printed in the exponential form such as `1.23e45`.
+ 
+ - `to_exact_exp_str` prints the exact representation with given number of
+   digits in the exponential form.
+ 
+ - `to_exact_fixed_str` prints the fixed representation with *exactly*
+   given number of fractional digits.
+ 
+ They all return a slice of preallocated `Part` array, which corresponds to
+ the individual part of strings: a fixed string, a part of rendered digits,
+ a number of zeroes or a small (`u16`) number. The caller is expected to
+ provide a large enough buffer and `Part` array, and to assemble the final
+ string from resulting `Part`s itself.
+ 
+ All algorithms and formatting functions are accompanied by extensive tests
+ in `coretests::num::flt2dec` module. It also shows how to use individual
+ functions.
+ 
+ */
+ 
+ // while this is extensively documented, this is in principle private which is
+ // only made public for testing. do not expose us.
+ #![doc(hidden)]
+ #![unstable(
+     feature = "flt2dec",
+     reason = "internal routines only exposed for testing",
+     issue = "none"
+ )]
+ 
+ pub use self::decoder::{decode, DecodableFloat, Decoded, FullDecoded};
+ 
+ use crate::mem::MaybeUninit;
+ 
+ pub mod decoder;
+ pub mod estimator;
+ 
+ /// Digit-generation algorithms.
+ pub mod strategy {
+     pub mod dragon;
+     pub mod grisu;
+ }
+ 
+ /// The minimum size of buffer necessary for the shortest mode.
+ ///
+ /// It is a bit non-trivial to derive, but this is one plus the maximal number of
+ /// significant decimal digits from formatting algorithms with the shortest result.
+ /// The exact formula is `ceil(# bits in mantissa * log_10 2 + 1)`.
+ pub const MAX_SIG_DIGITS: usize = 17;
+ 
+ /// When `d` contains decimal digits, increase the last digit and propagate carry.
+ /// Returns a next digit when it causes the length to change.
+ #[doc(hidden)]
+ pub fn round_up(d: &mut [u8]) -> Option<u8> {
+     match d.iter().rposition(|&c| c != b'9') {
+         Some(i) => {
+             // d[i+1..n] is all nines
+             d[i] += 1;
+             for j in i + 1..d.len() {
+                 d[j] = b'0';
+             }
+             None
+         }
+         None if d.len() > 0 => {
+             // 999..999 rounds to 1000..000 with an increased exponent
+             d[0] = b'1';
+             for j in 1..d.len() {
+                 d[j] = b'0';
+             }
+             Some(b'0')
+         }
+         None => {
+             // an empty buffer rounds up (a bit strange but reasonable)
+             Some(b'1')
+         }
+     }
+ }
+ 
+ /// Formatted parts.
+ #[derive(Copy, Clone, PartialEq, Eq, Debug)]
+ pub enum Part<'a> {
+     /// Given number of zero digits.
+     Zero(usize),
+     /// A literal number up to 5 digits.
+     Num(u16),
+     /// A verbatim copy of given bytes.
+     Copy(&'a [u8]),
+ }
+ 
+ impl<'a> Part<'a> {
+     /// Returns the exact byte length of given part.
+     pub fn len(&self) -> usize {
+         match *self {
+             Part::Zero(nzeroes) => nzeroes,
+             Part::Num(v) => {
+                 if v < 1_000 {
+                     if v < 10 {
+                         1
+                     } else if v < 100 {
+                         2
+                     } else {
+                         3
+                     }
+                 } else {
+                     if v < 10_000 { 4 } else { 5 }
+                 }
+             }
+             Part::Copy(buf) => buf.len(),
+         }
+     }
+ 
+     /// Writes a part into the supplied buffer.
+     /// Returns the number of written bytes, or `None` if the buffer is not enough.
+     /// (It may still leave partially written bytes in the buffer; do not rely on that.)
+     pub fn write(&self, out: &mut [u8]) -> Option<usize> {
+         let len = self.len();
+         if out.len() >= len {
+             match *self {
+                 Part::Zero(nzeroes) => {
+                     for c in &mut out[..nzeroes] {
+                         *c = b'0';
+                     }
+                 }
+                 Part::Num(mut v) => {
+                     for c in out[..len].iter_mut().rev() {
+                         *c = b'0' + (v % 10) as u8;
+                         v /= 10;
+                     }
+                 }
+                 Part::Copy(buf) => {
+                     out[..buf.len()].copy_from_slice(buf);
+                 }
+             }
+             Some(len)
+         } else {
+             None
+         }
+     }
+ }
+ 
+ /// Formatted result containing one or more parts.
+ /// This can be written to the byte buffer or converted to the allocated string.
+ #[allow(missing_debug_implementations)]
+ #[derive(Clone)]
+ pub struct Formatted<'a> {
+     /// A byte slice representing a sign, either `""`, `"-"` or `"+"`.
+     pub sign: &'static str,
+     /// Formatted parts to be rendered after a sign and optional zero padding.
+     pub parts: &'a [Part<'a>],
+ }
+ 
+ impl<'a> Formatted<'a> {
+     /// Returns the exact byte length of combined formatted result.
+     pub fn len(&self) -> usize {
+         let mut len = self.sign.len();
+         for part in self.parts {
+             len += part.len();
+         }
+         len
+     }
+ 
+     /// Writes all formatted parts into the supplied buffer.
+     /// Returns the number of written bytes, or `None` if the buffer is not enough.
+     /// (It may still leave partially written bytes in the buffer; do not rely on that.)
+     pub fn write(&self, out: &mut [u8]) -> Option<usize> {
+         if out.len() < self.sign.len() {
+             return None;
+         }
+         out[..self.sign.len()].copy_from_slice(self.sign.as_bytes());
+ 
+         let mut written = self.sign.len();
+         for part in self.parts {
+             let len = part.write(&mut out[written..])?;
+             written += len;
+         }
+         Some(written)
+     }
+ }
+ 
+ /// Formats given decimal digits `0.<...buf...> * 10^exp` into the decimal form
+ /// with at least given number of fractional digits. The result is stored to
+ /// the supplied parts array and a slice of written parts is returned.
+ ///
+ /// `frac_digits` can be less than the number of actual fractional digits in `buf`;
+ /// it will be ignored and full digits will be printed. It is only used to print
+ /// additional zeroes after rendered digits. Thus `frac_digits` of 0 means that
+ /// it will only print given digits and nothing else.
+ fn digits_to_dec_str<'a>(
+     buf: &'a [u8],
+     exp: i16,
+     frac_digits: usize,
+     parts: &'a mut [MaybeUninit<Part<'a>>],
+ ) -> &'a [Part<'a>] {
+     assert!(!buf.is_empty());
+     assert!(buf[0] > b'0');
+     assert!(parts.len() >= 4);
+ 
+     // if there is the restriction on the last digit position, `buf` is assumed to be
+     // left-padded with the virtual zeroes. the number of virtual zeroes, `nzeroes`,
+     // equals to `max(0, exp + frac_digits - buf.len())`, so that the position of
+     // the last digit `exp - buf.len() - nzeroes` is no more than `-frac_digits`:
+     //
+     //                       |<-virtual->|
+     //       |<---- buf ---->|  zeroes   |     exp
+     //    0. 1 2 3 4 5 6 7 8 9 _ _ _ _ _ _ x 10
+     //    |                  |           |
+     // 10^exp    10^(exp-buf.len())   10^(exp-buf.len()-nzeroes)
+     //
+     // `nzeroes` is individually calculated for each case in order to avoid overflow.
+ 
+     if exp <= 0 {
+         // the decimal point is before rendered digits: [0.][000...000][1234][____]
+         let minus_exp = -(exp as i32) as usize;
+         parts[0] = MaybeUninit::new(Part::Copy(b"0."));
+         parts[1] = MaybeUninit::new(Part::Zero(minus_exp));
+         parts[2] = MaybeUninit::new(Part::Copy(buf));
+         if frac_digits > buf.len() && frac_digits - buf.len() > minus_exp {
+             parts[3] = MaybeUninit::new(Part::Zero((frac_digits - buf.len()) - minus_exp));
+             // SAFETY: we just initialized the elements `..4`.
+             unsafe { MaybeUninit::slice_assume_init_ref(&parts[..4]) }
+         } else {
+             // SAFETY: we just initialized the elements `..3`.
+             unsafe { MaybeUninit::slice_assume_init_ref(&parts[..3]) }
+         }
+     } else {
+         let exp = exp as usize;
+         if exp < buf.len() {
+             // the decimal point is inside rendered digits: [12][.][34][____]
+             parts[0] = MaybeUninit::new(Part::Copy(&buf[..exp]));
+             parts[1] = MaybeUninit::new(Part::Copy(b"."));
+             parts[2] = MaybeUninit::new(Part::Copy(&buf[exp..]));
+             if frac_digits > buf.len() - exp {
+                 parts[3] = MaybeUninit::new(Part::Zero(frac_digits - (buf.len() - exp)));
+                 // SAFETY: we just initialized the elements `..4`.
+                 unsafe { MaybeUninit::slice_assume_init_ref(&parts[..4]) }
+             } else {
+                 // SAFETY: we just initialized the elements `..3`.
+                 unsafe { MaybeUninit::slice_assume_init_ref(&parts[..3]) }
+             }
+         } else {
+             // the decimal point is after rendered digits: [1234][____0000] or [1234][__][.][__].
+             parts[0] = MaybeUninit::new(Part::Copy(buf));
+             parts[1] = MaybeUninit::new(Part::Zero(exp - buf.len()));
+             if frac_digits > 0 {
+                 parts[2] = MaybeUninit::new(Part::Copy(b"."));
+                 parts[3] = MaybeUninit::new(Part::Zero(frac_digits));
+                 // SAFETY: we just initialized the elements `..4`.
+                 unsafe { MaybeUninit::slice_assume_init_ref(&parts[..4]) }
+             } else {
+                 // SAFETY: we just initialized the elements `..2`.
+                 unsafe { MaybeUninit::slice_assume_init_ref(&parts[..2]) }
+             }
+         }
+     }
+ }
+ 
+ /// Formats the given decimal digits `0.<...buf...> * 10^exp` into the exponential
+ /// form with at least the given number of significant digits. When `upper` is `true`,
+ /// the exponent will be prefixed by `E`; otherwise that's `e`. The result is
+ /// stored to the supplied parts array and a slice of written parts is returned.
+ ///
+ /// `min_digits` can be less than the number of actual significant digits in `buf`;
+ /// it will be ignored and full digits will be printed. It is only used to print
+ /// additional zeroes after rendered digits. Thus, `min_digits == 0` means that
+ /// it will only print the given digits and nothing else.
+ fn digits_to_exp_str<'a>(
+     buf: &'a [u8],
+     exp: i16,
+     min_ndigits: usize,
+     upper: bool,
+     parts: &'a mut [MaybeUninit<Part<'a>>],
+ ) -> &'a [Part<'a>] {
+     assert!(!buf.is_empty());
+     assert!(buf[0] > b'0');
+     assert!(parts.len() >= 6);
+ 
+     let mut n = 0;
+ 
+     parts[n] = MaybeUninit::new(Part::Copy(&buf[..1]));
+     n += 1;
+ 
+     if buf.len() > 1 || min_ndigits > 1 {
+         parts[n] = MaybeUninit::new(Part::Copy(b"."));
+         parts[n + 1] = MaybeUninit::new(Part::Copy(&buf[1..]));
+         n += 2;
+         if min_ndigits > buf.len() {
+             parts[n] = MaybeUninit::new(Part::Zero(min_ndigits - buf.len()));
+             n += 1;
+         }
+     }
+ 
+     // 0.1234 x 10^exp = 1.234 x 10^(exp-1)
+     let exp = exp as i32 - 1; // avoid underflow when exp is i16::MIN
+     if exp < 0 {
+         parts[n] = MaybeUninit::new(Part::Copy(if upper { b"E-" } else { b"e-" }));
+         parts[n + 1] = MaybeUninit::new(Part::Num(-exp as u16));
+     } else {
+         parts[n] = MaybeUninit::new(Part::Copy(if upper { b"E" } else { b"e" }));
+         parts[n + 1] = MaybeUninit::new(Part::Num(exp as u16));
+     }
+     // SAFETY: we just initialized the elements `..n + 2`.
+     unsafe { MaybeUninit::slice_assume_init_ref(&parts[..n + 2]) }
+ }
+ 
+ /// Sign formatting options.
+ #[derive(Copy, Clone, PartialEq, Eq, Debug)]
+ pub enum Sign {
+     /// Prints `-` only for the negative non-zero values.
+     Minus, // -inf -1  0  0  1  inf nan
+     /// Prints `-` only for any negative values (including the negative zero).
+     MinusRaw, // -inf -1 -0  0  1  inf nan
+     /// Prints `-` for the negative non-zero values, or `+` otherwise.
+     MinusPlus, // -inf -1 +0 +0 +1 +inf nan
+     /// Prints `-` for any negative values (including the negative zero), or `+` otherwise.
+     MinusPlusRaw, // -inf -1 -0 +0 +1 +inf nan
+ }
+ 
+ /// Returns the static byte string corresponding to the sign to be formatted.
+ /// It can be either `""`, `"+"` or `"-"`.
+ fn determine_sign(sign: Sign, decoded: &FullDecoded, negative: bool) -> &'static str {
+     match (*decoded, sign) {
+         (FullDecoded::Nan, _) => "",
+         (FullDecoded::Zero, Sign::Minus) => "",
+         (FullDecoded::Zero, Sign::MinusRaw) => {
+             if negative {
+                 "-"
+             } else {
+                 ""
+             }
+         }
+         (FullDecoded::Zero, Sign::MinusPlus) => "+",
+         (FullDecoded::Zero, Sign::MinusPlusRaw) => {
+             if negative {
+                 "-"
+             } else {
+                 "+"
+             }
+         }
+         (_, Sign::Minus | Sign::MinusRaw) => {
+             if negative {
+                 "-"
+             } else {
+                 ""
+             }
+         }
+         (_, Sign::MinusPlus | Sign::MinusPlusRaw) => {
+             if negative {
+                 "-"
+             } else {
+                 "+"
+             }
+         }
+     }
+ }
+ 
+ /// Formats the given floating point number into the decimal form with at least
+ /// given number of fractional digits. The result is stored to the supplied parts
+ /// array while utilizing given byte buffer as a scratch. `upper` is currently
+ /// unused but left for the future decision to change the case of non-finite values,
+ /// i.e., `inf` and `nan`. The first part to be rendered is always a `Part::Sign`
+ /// (which can be an empty string if no sign is rendered).
+ ///
+ /// `format_shortest` should be the underlying digit-generation function.
+ /// It should return the part of the buffer that it initialized.
+ /// You probably would want `strategy::grisu::format_shortest` for this.
+ ///
+ /// `frac_digits` can be less than the number of actual fractional digits in `v`;
+ /// it will be ignored and full digits will be printed. It is only used to print
+ /// additional zeroes after rendered digits. Thus `frac_digits` of 0 means that
+ /// it will only print given digits and nothing else.
+ ///
+ /// The byte buffer should be at least `MAX_SIG_DIGITS` bytes long.
+ /// There should be at least 4 parts available, due to the worst case like
+ /// `[+][0.][0000][2][0000]` with `frac_digits = 10`.
+ pub fn to_shortest_str<'a, T, F>(
+     mut format_shortest: F,
+     v: T,
+     sign: Sign,
+     frac_digits: usize,
+     buf: &'a mut [MaybeUninit<u8>],
+     parts: &'a mut [MaybeUninit<Part<'a>>],
+ ) -> Formatted<'a>
+ where
+     T: DecodableFloat,
+     F: FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     assert!(parts.len() >= 4);
+     assert!(buf.len() >= MAX_SIG_DIGITS);
+ 
+     let (negative, full_decoded) = decode(v);
+     let sign = determine_sign(sign, &full_decoded, negative);
+     match full_decoded {
+         FullDecoded::Nan => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"NaN"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Infinite => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"inf"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Zero => {
+             if frac_digits > 0 {
+                 // [0.][0000]
+                 parts[0] = MaybeUninit::new(Part::Copy(b"0."));
+                 parts[1] = MaybeUninit::new(Part::Zero(frac_digits));
+                 Formatted {
+                     sign,
+                     // SAFETY: we just initialized the elements `..2`.
+                     parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..2]) },
+                 }
+             } else {
+                 parts[0] = MaybeUninit::new(Part::Copy(b"0"));
+                 Formatted {
+                     sign,
+                     // SAFETY: we just initialized the elements `..1`.
+                     parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) },
+                 }
+             }
+         }
+         FullDecoded::Finite(ref decoded) => {
+             let (buf, exp) = format_shortest(decoded, buf);
+             Formatted { sign, parts: digits_to_dec_str(buf, exp, frac_digits, parts) }
+         }
+     }
+ }
+ 
+ /// Formats the given floating point number into the decimal form or
+ /// the exponential form, depending on the resulting exponent. The result is
+ /// stored to the supplied parts array while utilizing given byte buffer
+ /// as a scratch. `upper` is used to determine the case of non-finite values
+ /// (`inf` and `nan`) or the case of the exponent prefix (`e` or `E`).
+ /// The first part to be rendered is always a `Part::Sign` (which can be
+ /// an empty string if no sign is rendered).
+ ///
+ /// `format_shortest` should be the underlying digit-generation function.
+ /// It should return the part of the buffer that it initialized.
+ /// You probably would want `strategy::grisu::format_shortest` for this.
+ ///
+ /// The `dec_bounds` is a tuple `(lo, hi)` such that the number is formatted
+ /// as decimal only when `10^lo <= V < 10^hi`. Note that this is the *apparent* `V`
+ /// instead of the actual `v`! Thus any printed exponent in the exponential form
+ /// cannot be in this range, avoiding any confusion.
+ ///
+ /// The byte buffer should be at least `MAX_SIG_DIGITS` bytes long.
+ /// There should be at least 6 parts available, due to the worst case like
+ /// `[+][1][.][2345][e][-][6]`.
+ pub fn to_shortest_exp_str<'a, T, F>(
+     mut format_shortest: F,
+     v: T,
+     sign: Sign,
+     dec_bounds: (i16, i16),
+     upper: bool,
+     buf: &'a mut [MaybeUninit<u8>],
+     parts: &'a mut [MaybeUninit<Part<'a>>],
+ ) -> Formatted<'a>
+ where
+     T: DecodableFloat,
+     F: FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     assert!(parts.len() >= 6);
+     assert!(buf.len() >= MAX_SIG_DIGITS);
+     assert!(dec_bounds.0 <= dec_bounds.1);
+ 
+     let (negative, full_decoded) = decode(v);
+     let sign = determine_sign(sign, &full_decoded, negative);
+     match full_decoded {
+         FullDecoded::Nan => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"NaN"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Infinite => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"inf"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Zero => {
+             parts[0] = if dec_bounds.0 <= 0 && 0 < dec_bounds.1 {
+                 MaybeUninit::new(Part::Copy(b"0"))
+             } else {
+                 MaybeUninit::new(Part::Copy(if upper { b"0E0" } else { b"0e0" }))
+             };
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Finite(ref decoded) => {
+             let (buf, exp) = format_shortest(decoded, buf);
+             let vis_exp = exp as i32 - 1;
+             let parts = if dec_bounds.0 as i32 <= vis_exp && vis_exp < dec_bounds.1 as i32 {
+                 digits_to_dec_str(buf, exp, 0, parts)
+             } else {
+                 digits_to_exp_str(buf, exp, 0, upper, parts)
+             };
+             Formatted { sign, parts }
+         }
+     }
+ }
+ 
+ /// Returns a rather crude approximation (upper bound) for the maximum buffer size
+ /// calculated from the given decoded exponent.
+ ///
+ /// The exact limit is:
+ ///
+ /// - when `exp < 0`, the maximum length is `ceil(log_10 (5^-exp * (2^64 - 1)))`.
+ /// - when `exp >= 0`, the maximum length is `ceil(log_10 (2^exp * (2^64 - 1)))`.
+ ///
+ /// `ceil(log_10 (x^exp * (2^64 - 1)))` is less than `ceil(log_10 (2^64 - 1)) +
+ /// ceil(exp * log_10 x)`, which is in turn less than `20 + (1 + exp * log_10 x)`.
+ /// We use the facts that `log_10 2 < 5/16` and `log_10 5 < 12/16`, which is
+ /// enough for our purposes.
+ ///
+ /// Why do we need this? `format_exact` functions will fill the entire buffer
+ /// unless limited by the last digit restriction, but it is possible that
+ /// the number of digits requested is ridiculously large (say, 30,000 digits).
+ /// The vast majority of buffer will be filled with zeroes, so we don't want to
+ /// allocate all the buffer beforehand. Consequently, for any given arguments,
+ /// 826 bytes of buffer should be sufficient for `f64`. Compare this with
+ /// the actual number for the worst case: 770 bytes (when `exp = -1074`).
+ fn estimate_max_buf_len(exp: i16) -> usize {
+     21 + ((if exp < 0 { -12 } else { 5 } * exp as i32) as usize >> 4)
+ }
+ 
+ /// Formats given floating point number into the exponential form with
+ /// exactly given number of significant digits. The result is stored to
+ /// the supplied parts array while utilizing given byte buffer as a scratch.
+ /// `upper` is used to determine the case of the exponent prefix (`e` or `E`).
+ /// The first part to be rendered is always a `Part::Sign` (which can be
+ /// an empty string if no sign is rendered).
+ ///
+ /// `format_exact` should be the underlying digit-generation function.
+ /// It should return the part of the buffer that it initialized.
+ /// You probably would want `strategy::grisu::format_exact` for this.
+ ///
+ /// The byte buffer should be at least `ndigits` bytes long unless `ndigits` is
+ /// so large that only the fixed number of digits will be ever written.
+ /// (The tipping point for `f64` is about 800, so 1000 bytes should be enough.)
+ /// There should be at least 6 parts available, due to the worst case like
+ /// `[+][1][.][2345][e][-][6]`.
+ pub fn to_exact_exp_str<'a, T, F>(
+     mut format_exact: F,
+     v: T,
+     sign: Sign,
+     ndigits: usize,
+     upper: bool,
+     buf: &'a mut [MaybeUninit<u8>],
+     parts: &'a mut [MaybeUninit<Part<'a>>],
+ ) -> Formatted<'a>
+ where
+     T: DecodableFloat,
+     F: FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     assert!(parts.len() >= 6);
+     assert!(ndigits > 0);
+ 
+     let (negative, full_decoded) = decode(v);
+     let sign = determine_sign(sign, &full_decoded, negative);
+     match full_decoded {
+         FullDecoded::Nan => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"NaN"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Infinite => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"inf"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Zero => {
+             if ndigits > 1 {
+                 // [0.][0000][e0]
+                 parts[0] = MaybeUninit::new(Part::Copy(b"0."));
+                 parts[1] = MaybeUninit::new(Part::Zero(ndigits - 1));
+                 parts[2] = MaybeUninit::new(Part::Copy(if upper { b"E0" } else { b"e0" }));
+                 Formatted {
+                     sign,
+                     // SAFETY: we just initialized the elements `..3`.
+                     parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..3]) },
+                 }
+             } else {
+                 parts[0] = MaybeUninit::new(Part::Copy(if upper { b"0E0" } else { b"0e0" }));
+                 Formatted {
+                     sign,
+                     // SAFETY: we just initialized the elements `..1`.
+                     parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) },
+                 }
+             }
+         }
+         FullDecoded::Finite(ref decoded) => {
+             let maxlen = estimate_max_buf_len(decoded.exp);
+             assert!(buf.len() >= ndigits || buf.len() >= maxlen);
+ 
+             let trunc = if ndigits < maxlen { ndigits } else { maxlen };
+             let (buf, exp) = format_exact(decoded, &mut buf[..trunc], i16::MIN);
+             Formatted { sign, parts: digits_to_exp_str(buf, exp, ndigits, upper, parts) }
+         }
+     }
+ }
+ 
+ /// Formats given floating point number into the decimal form with exactly
+ /// given number of fractional digits. The result is stored to the supplied parts
+ /// array while utilizing given byte buffer as a scratch. `upper` is currently
+ /// unused but left for the future decision to change the case of non-finite values,
+ /// i.e., `inf` and `nan`. The first part to be rendered is always a `Part::Sign`
+ /// (which can be an empty string if no sign is rendered).
+ ///
+ /// `format_exact` should be the underlying digit-generation function.
+ /// It should return the part of the buffer that it initialized.
+ /// You probably would want `strategy::grisu::format_exact` for this.
+ ///
+ /// The byte buffer should be enough for the output unless `frac_digits` is
+ /// so large that only the fixed number of digits will be ever written.
+ /// (The tipping point for `f64` is about 800, and 1000 bytes should be enough.)
+ /// There should be at least 4 parts available, due to the worst case like
+ /// `[+][0.][0000][2][0000]` with `frac_digits = 10`.
+ pub fn to_exact_fixed_str<'a, T, F>(
+     mut format_exact: F,
+     v: T,
+     sign: Sign,
+     frac_digits: usize,
+     buf: &'a mut [MaybeUninit<u8>],
+     parts: &'a mut [MaybeUninit<Part<'a>>],
+ ) -> Formatted<'a>
+ where
+     T: DecodableFloat,
+     F: FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     assert!(parts.len() >= 4);
+ 
+     let (negative, full_decoded) = decode(v);
+     let sign = determine_sign(sign, &full_decoded, negative);
+     match full_decoded {
+         FullDecoded::Nan => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"NaN"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Infinite => {
+             parts[0] = MaybeUninit::new(Part::Copy(b"inf"));
+             // SAFETY: we just initialized the elements `..1`.
+             Formatted { sign, parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) } }
+         }
+         FullDecoded::Zero => {
+             if frac_digits > 0 {
+                 // [0.][0000]
+                 parts[0] = MaybeUninit::new(Part::Copy(b"0."));
+                 parts[1] = MaybeUninit::new(Part::Zero(frac_digits));
+                 Formatted {
+                     sign,
+                     // SAFETY: we just initialized the elements `..2`.
+                     parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..2]) },
+                 }
+             } else {
+                 parts[0] = MaybeUninit::new(Part::Copy(b"0"));
+                 Formatted {
+                     sign,
+                     // SAFETY: we just initialized the elements `..1`.
+                     parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) },
+                 }
+             }
+         }
+         FullDecoded::Finite(ref decoded) => {
+             let maxlen = estimate_max_buf_len(decoded.exp);
+             assert!(buf.len() >= maxlen);
+ 
+             // it *is* possible that `frac_digits` is ridiculously large.
+             // `format_exact` will end rendering digits much earlier in this case,
+             // because we are strictly limited by `maxlen`.
+             let limit = if frac_digits < 0x8000 { -(frac_digits as i16) } else { i16::MIN };
+             let (buf, exp) = format_exact(decoded, &mut buf[..maxlen], limit);
+             if exp <= limit {
+                 // the restriction couldn't been met, so this should render like zero no matter
+                 // `exp` was. this does not include the case that the restriction has been met
+                 // only after the final rounding-up; it's a regular case with `exp = limit + 1`.
+                 debug_assert_eq!(buf.len(), 0);
+                 if frac_digits > 0 {
+                     // [0.][0000]
+                     parts[0] = MaybeUninit::new(Part::Copy(b"0."));
+                     parts[1] = MaybeUninit::new(Part::Zero(frac_digits));
+                     Formatted {
+                         sign,
+                         // SAFETY: we just initialized the elements `..2`.
+                         parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..2]) },
+                     }
+                 } else {
+                     parts[0] = MaybeUninit::new(Part::Copy(b"0"));
+                     Formatted {
+                         sign,
+                         // SAFETY: we just initialized the elements `..1`.
+                         parts: unsafe { MaybeUninit::slice_assume_init_ref(&parts[..1]) },
+                     }
+                 }
+             } else {
+                 Formatted { sign, parts: digits_to_dec_str(buf, exp, frac_digits, parts) }
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/strategy/dragon.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/strategy/dragon.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/strategy/dragon.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/strategy/dragon.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,388 ----
+ //! Almost direct (but slightly optimized) Rust translation of Figure 3 of "Printing
+ //! Floating-Point Numbers Quickly and Accurately"[^1].
+ //!
+ //! [^1]: Burger, R. G. and Dybvig, R. K. 1996. Printing floating-point numbers
+ //!   quickly and accurately. SIGPLAN Not. 31, 5 (May. 1996), 108-116.
+ 
+ use crate::cmp::Ordering;
+ use crate::mem::MaybeUninit;
+ 
+ use crate::num::bignum::Big32x40 as Big;
+ use crate::num::bignum::Digit32 as Digit;
+ use crate::num::flt2dec::estimator::estimate_scaling_factor;
+ use crate::num::flt2dec::{round_up, Decoded, MAX_SIG_DIGITS};
+ 
+ static POW10: [Digit; 10] =
+     [1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000];
+ static TWOPOW10: [Digit; 10] =
+     [2, 20, 200, 2000, 20000, 200000, 2000000, 20000000, 200000000, 2000000000];
+ 
+ // precalculated arrays of `Digit`s for 10^(2^n)
+ static POW10TO16: [Digit; 2] = [0x6fc10000, 0x2386f2];
+ static POW10TO32: [Digit; 4] = [0, 0x85acef81, 0x2d6d415b, 0x4ee];
+ static POW10TO64: [Digit; 7] = [0, 0, 0xbf6a1f01, 0x6e38ed64, 0xdaa797ed, 0xe93ff9f4, 0x184f03];
+ static POW10TO128: [Digit; 14] = [
+     0, 0, 0, 0, 0x2e953e01, 0x3df9909, 0xf1538fd, 0x2374e42f, 0xd3cff5ec, 0xc404dc08, 0xbccdb0da,
+     0xa6337f19, 0xe91f2603, 0x24e,
+ ];
+ static POW10TO256: [Digit; 27] = [
+     0, 0, 0, 0, 0, 0, 0, 0, 0x982e7c01, 0xbed3875b, 0xd8d99f72, 0x12152f87, 0x6bde50c6, 0xcf4a6e70,
+     0xd595d80f, 0x26b2716e, 0xadc666b0, 0x1d153624, 0x3c42d35a, 0x63ff540e, 0xcc5573c0, 0x65f9ef17,
+     0x55bc28f2, 0x80dcc7f7, 0xf46eeddc, 0x5fdcefce, 0x553f7,
+ ];
+ 
+ #[doc(hidden)]
+ pub fn mul_pow10(x: &mut Big, n: usize) -> &mut Big {
+     debug_assert!(n < 512);
+     if n & 7 != 0 {
+         x.mul_small(POW10[n & 7]);
+     }
+     if n & 8 != 0 {
+         x.mul_small(POW10[8]);
+     }
+     if n & 16 != 0 {
+         x.mul_digits(&POW10TO16);
+     }
+     if n & 32 != 0 {
+         x.mul_digits(&POW10TO32);
+     }
+     if n & 64 != 0 {
+         x.mul_digits(&POW10TO64);
+     }
+     if n & 128 != 0 {
+         x.mul_digits(&POW10TO128);
+     }
+     if n & 256 != 0 {
+         x.mul_digits(&POW10TO256);
+     }
+     x
+ }
+ 
+ fn div_2pow10(x: &mut Big, mut n: usize) -> &mut Big {
+     let largest = POW10.len() - 1;
+     while n > largest {
+         x.div_rem_small(POW10[largest]);
+         n -= largest;
+     }
+     x.div_rem_small(TWOPOW10[n]);
+     x
+ }
+ 
+ // only usable when `x < 16 * scale`; `scaleN` should be `scale.mul_small(N)`
+ fn div_rem_upto_16<'a>(
+     x: &'a mut Big,
+     scale: &Big,
+     scale2: &Big,
+     scale4: &Big,
+     scale8: &Big,
+ ) -> (u8, &'a mut Big) {
+     let mut d = 0;
+     if *x >= *scale8 {
+         x.sub(scale8);
+         d += 8;
+     }
+     if *x >= *scale4 {
+         x.sub(scale4);
+         d += 4;
+     }
+     if *x >= *scale2 {
+         x.sub(scale2);
+         d += 2;
+     }
+     if *x >= *scale {
+         x.sub(scale);
+         d += 1;
+     }
+     debug_assert!(*x < *scale);
+     (d, x)
+ }
+ 
+ /// The shortest mode implementation for Dragon.
+ pub fn format_shortest<'a>(
+     d: &Decoded,
+     buf: &'a mut [MaybeUninit<u8>],
+ ) -> (/*digits*/ &'a [u8], /*exp*/ i16) {
+     // the number `v` to format is known to be:
+     // - equal to `mant * 2^exp`;
+     // - preceded by `(mant - 2 * minus) * 2^exp` in the original type; and
+     // - followed by `(mant + 2 * plus) * 2^exp` in the original type.
+     //
+     // obviously, `minus` and `plus` cannot be zero. (for infinities, we use out-of-range values.)
+     // also we assume that at least one digit is generated, i.e., `mant` cannot be zero too.
+     //
+     // this also means that any number between `low = (mant - minus) * 2^exp` and
+     // `high = (mant + plus) * 2^exp` will map to this exact floating point number,
+     // with bounds included when the original mantissa was even (i.e., `!mant_was_odd`).
+ 
+     assert!(d.mant > 0);
+     assert!(d.minus > 0);
+     assert!(d.plus > 0);
+     assert!(d.mant.checked_add(d.plus).is_some());
+     assert!(d.mant.checked_sub(d.minus).is_some());
+     assert!(buf.len() >= MAX_SIG_DIGITS);
+ 
+     // `a.cmp(&b) < rounding` is `if d.inclusive {a <= b} else {a < b}`
+     let rounding = if d.inclusive { Ordering::Greater } else { Ordering::Equal };
+ 
+     // estimate `k_0` from original inputs satisfying `10^(k_0-1) < high <= 10^(k_0+1)`.
+     // the tight bound `k` satisfying `10^(k-1) < high <= 10^k` is calculated later.
+     let mut k = estimate_scaling_factor(d.mant + d.plus, d.exp);
+ 
+     // convert `{mant, plus, minus} * 2^exp` into the fractional form so that:
+     // - `v = mant / scale`
+     // - `low = (mant - minus) / scale`
+     // - `high = (mant + plus) / scale`
+     let mut mant = Big::from_u64(d.mant);
+     let mut minus = Big::from_u64(d.minus);
+     let mut plus = Big::from_u64(d.plus);
+     let mut scale = Big::from_small(1);
+     if d.exp < 0 {
+         scale.mul_pow2(-d.exp as usize);
+     } else {
+         mant.mul_pow2(d.exp as usize);
+         minus.mul_pow2(d.exp as usize);
+         plus.mul_pow2(d.exp as usize);
+     }
+ 
+     // divide `mant` by `10^k`. now `scale / 10 < mant + plus <= scale * 10`.
+     if k >= 0 {
+         mul_pow10(&mut scale, k as usize);
+     } else {
+         mul_pow10(&mut mant, -k as usize);
+         mul_pow10(&mut minus, -k as usize);
+         mul_pow10(&mut plus, -k as usize);
+     }
+ 
+     // fixup when `mant + plus > scale` (or `>=`).
+     // we are not actually modifying `scale`, since we can skip the initial multiplication instead.
+     // now `scale < mant + plus <= scale * 10` and we are ready to generate digits.
+     //
+     // note that `d[0]` *can* be zero, when `scale - plus < mant < scale`.
+     // in this case rounding-up condition (`up` below) will be triggered immediately.
+     if scale.cmp(mant.clone().add(&plus)) < rounding {
+         // equivalent to scaling `scale` by 10
+         k += 1;
+     } else {
+         mant.mul_small(10);
+         minus.mul_small(10);
+         plus.mul_small(10);
+     }
+ 
+     // cache `(2, 4, 8) * scale` for digit generation.
+     let mut scale2 = scale.clone();
+     scale2.mul_pow2(1);
+     let mut scale4 = scale.clone();
+     scale4.mul_pow2(2);
+     let mut scale8 = scale.clone();
+     scale8.mul_pow2(3);
+ 
+     let mut down;
+     let mut up;
+     let mut i = 0;
+     loop {
+         // invariants, where `d[0..n-1]` are digits generated so far:
+         // - `v = mant / scale * 10^(k-n-1) + d[0..n-1] * 10^(k-n)`
+         // - `v - low = minus / scale * 10^(k-n-1)`
+         // - `high - v = plus / scale * 10^(k-n-1)`
+         // - `(mant + plus) / scale <= 10` (thus `mant / scale < 10`)
+         // where `d[i..j]` is a shorthand for `d[i] * 10^(j-i) + ... + d[j-1] * 10 + d[j]`.
+ 
+         // generate one digit: `d[n] = floor(mant / scale) < 10`.
+         let (d, _) = div_rem_upto_16(&mut mant, &scale, &scale2, &scale4, &scale8);
+         debug_assert!(d < 10);
+         buf[i] = MaybeUninit::new(b'0' + d);
+         i += 1;
+ 
+         // this is a simplified description of the modified Dragon algorithm.
+         // many intermediate derivations and completeness arguments are omitted for convenience.
+         //
+         // start with modified invariants, as we've updated `n`:
+         // - `v = mant / scale * 10^(k-n) + d[0..n-1] * 10^(k-n)`
+         // - `v - low = minus / scale * 10^(k-n)`
+         // - `high - v = plus / scale * 10^(k-n)`
+         //
+         // assume that `d[0..n-1]` is the shortest representation between `low` and `high`,
+         // i.e., `d[0..n-1]` satisfies both of the following but `d[0..n-2]` doesn't:
+         // - `low < d[0..n-1] * 10^(k-n) < high` (bijectivity: digits round to `v`); and
+         // - `abs(v / 10^(k-n) - d[0..n-1]) <= 1/2` (the last digit is correct).
+         //
+         // the second condition simplifies to `2 * mant <= scale`.
+         // solving invariants in terms of `mant`, `low` and `high` yields
+         // a simpler version of the first condition: `-plus < mant < minus`.
+         // since `-plus < 0 <= mant`, we have the correct shortest representation
+         // when `mant < minus` and `2 * mant <= scale`.
+         // (the former becomes `mant <= minus` when the original mantissa is even.)
+         //
+         // when the second doesn't hold (`2 * mant > scale`), we need to increase the last digit.
+         // this is enough for restoring that condition: we already know that
+         // the digit generation guarantees `0 <= v / 10^(k-n) - d[0..n-1] < 1`.
+         // in this case, the first condition becomes `-plus < mant - scale < minus`.
+         // since `mant < scale` after the generation, we have `scale < mant + plus`.
+         // (again, this becomes `scale <= mant + plus` when the original mantissa is even.)
+         //
+         // in short:
+         // - stop and round `down` (keep digits as is) when `mant < minus` (or `<=`).
+         // - stop and round `up` (increase the last digit) when `scale < mant + plus` (or `<=`).
+         // - keep generating otherwise.
+         down = mant.cmp(&minus) < rounding;
+         up = scale.cmp(mant.clone().add(&plus)) < rounding;
+         if down || up {
+             break;
+         } // we have the shortest representation, proceed to the rounding
+ 
+         // restore the invariants.
+         // this makes the algorithm always terminating: `minus` and `plus` always increases,
+         // but `mant` is clipped modulo `scale` and `scale` is fixed.
+         mant.mul_small(10);
+         minus.mul_small(10);
+         plus.mul_small(10);
+     }
+ 
+     // rounding up happens when
+     // i) only the rounding-up condition was triggered, or
+     // ii) both conditions were triggered and tie breaking prefers rounding up.
+     if up && (!down || *mant.mul_pow2(1) >= scale) {
+         // if rounding up changes the length, the exponent should also change.
+         // it seems that this condition is very hard to satisfy (possibly impossible),
+         // but we are just being safe and consistent here.
+         // SAFETY: we initialized that memory above.
+         if let Some(c) = round_up(unsafe { MaybeUninit::slice_assume_init_mut(&mut buf[..i]) }) {
+             buf[i] = MaybeUninit::new(c);
+             i += 1;
+             k += 1;
+         }
+     }
+ 
+     // SAFETY: we initialized that memory above.
+     (unsafe { MaybeUninit::slice_assume_init_ref(&buf[..i]) }, k)
+ }
+ 
+ /// The exact and fixed mode implementation for Dragon.
+ pub fn format_exact<'a>(
+     d: &Decoded,
+     buf: &'a mut [MaybeUninit<u8>],
+     limit: i16,
+ ) -> (/*digits*/ &'a [u8], /*exp*/ i16) {
+     assert!(d.mant > 0);
+     assert!(d.minus > 0);
+     assert!(d.plus > 0);
+     assert!(d.mant.checked_add(d.plus).is_some());
+     assert!(d.mant.checked_sub(d.minus).is_some());
+ 
+     // estimate `k_0` from original inputs satisfying `10^(k_0-1) < v <= 10^(k_0+1)`.
+     let mut k = estimate_scaling_factor(d.mant, d.exp);
+ 
+     // `v = mant / scale`.
+     let mut mant = Big::from_u64(d.mant);
+     let mut scale = Big::from_small(1);
+     if d.exp < 0 {
+         scale.mul_pow2(-d.exp as usize);
+     } else {
+         mant.mul_pow2(d.exp as usize);
+     }
+ 
+     // divide `mant` by `10^k`. now `scale / 10 < mant <= scale * 10`.
+     if k >= 0 {
+         mul_pow10(&mut scale, k as usize);
+     } else {
+         mul_pow10(&mut mant, -k as usize);
+     }
+ 
+     // fixup when `mant + plus >= scale`, where `plus / scale = 10^-buf.len() / 2`.
+     // in order to keep the fixed-size bignum, we actually use `mant + floor(plus) >= scale`.
+     // we are not actually modifying `scale`, since we can skip the initial multiplication instead.
+     // again with the shortest algorithm, `d[0]` can be zero but will be eventually rounded up.
+     if *div_2pow10(&mut scale.clone(), buf.len()).add(&mant) >= scale {
+         // equivalent to scaling `scale` by 10
+         k += 1;
+     } else {
+         mant.mul_small(10);
+     }
+ 
+     // if we are working with the last-digit limitation, we need to shorten the buffer
+     // before the actual rendering in order to avoid double rounding.
+     // note that we have to enlarge the buffer again when rounding up happens!
+     let mut len = if k < limit {
+         // oops, we cannot even produce *one* digit.
+         // this is possible when, say, we've got something like 9.5 and it's being rounded to 10.
+         // we return an empty buffer, with an exception of the later rounding-up case
+         // which occurs when `k == limit` and has to produce exactly one digit.
+         0
+     } else if ((k as i32 - limit as i32) as usize) < buf.len() {
+         (k - limit) as usize
+     } else {
+         buf.len()
+     };
+ 
+     if len > 0 {
+         // cache `(2, 4, 8) * scale` for digit generation.
+         // (this can be expensive, so do not calculate them when the buffer is empty.)
+         let mut scale2 = scale.clone();
+         scale2.mul_pow2(1);
+         let mut scale4 = scale.clone();
+         scale4.mul_pow2(2);
+         let mut scale8 = scale.clone();
+         scale8.mul_pow2(3);
+ 
+         for i in 0..len {
+             if mant.is_zero() {
+                 // following digits are all zeroes, we stop here
+                 // do *not* try to perform rounding! rather, fill remaining digits.
+                 for c in &mut buf[i..len] {
+                     *c = MaybeUninit::new(b'0');
+                 }
+                 // SAFETY: we initialized that memory above.
+                 return (unsafe { MaybeUninit::slice_assume_init_ref(&buf[..len]) }, k);
+             }
+ 
+             let mut d = 0;
+             if mant >= scale8 {
+                 mant.sub(&scale8);
+                 d += 8;
+             }
+             if mant >= scale4 {
+                 mant.sub(&scale4);
+                 d += 4;
+             }
+             if mant >= scale2 {
+                 mant.sub(&scale2);
+                 d += 2;
+             }
+             if mant >= scale {
+                 mant.sub(&scale);
+                 d += 1;
+             }
+             debug_assert!(mant < scale);
+             debug_assert!(d < 10);
+             buf[i] = MaybeUninit::new(b'0' + d);
+             mant.mul_small(10);
+         }
+     }
+ 
+     // rounding up if we stop in the middle of digits
+     // if the following digits are exactly 5000..., check the prior digit and try to
+     // round to even (i.e., avoid rounding up when the prior digit is even).
+     let order = mant.cmp(scale.mul_small(5));
+     if order == Ordering::Greater
+         || (order == Ordering::Equal
+             // SAFETY: `buf[len-1]` is initialized.
+             && (len == 0 || unsafe { buf[len - 1].assume_init() } & 1 == 1))
+     {
+         // if rounding up changes the length, the exponent should also change.
+         // but we've been requested a fixed number of digits, so do not alter the buffer...
+         // SAFETY: we initialized that memory above.
+         if let Some(c) = round_up(unsafe { MaybeUninit::slice_assume_init_mut(&mut buf[..len]) }) {
+             // ...unless we've been requested the fixed precision instead.
+             // we also need to check that, if the original buffer was empty,
+             // the additional digit can only be added when `k == limit` (edge case).
+             k += 1;
+             if k > limit && len < buf.len() {
+                 buf[len] = MaybeUninit::new(c);
+                 len += 1;
+             }
+         }
+     }
+ 
+     // SAFETY: we initialized that memory above.
+     (unsafe { MaybeUninit::slice_assume_init_ref(&buf[..len]) }, k)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/strategy/grisu.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/strategy/grisu.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/flt2dec/strategy/grisu.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/flt2dec/strategy/grisu.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,764 ----
+ //! Rust adaptation of the Grisu3 algorithm described in "Printing Floating-Point Numbers Quickly
+ //! and Accurately with Integers"[^1]. It uses about 1KB of precomputed table, and in turn, it's
+ //! very quick for most inputs.
+ //!
+ //! [^1]: Florian Loitsch. 2010. Printing floating-point numbers quickly and
+ //!   accurately with integers. SIGPLAN Not. 45, 6 (June 2010), 233-243.
+ 
+ use crate::mem::MaybeUninit;
+ use crate::num::diy_float::Fp;
+ use crate::num::flt2dec::{round_up, Decoded, MAX_SIG_DIGITS};
+ 
+ // see the comments in `format_shortest_opt` for the rationale.
+ #[doc(hidden)]
+ pub const ALPHA: i16 = -60;
+ #[doc(hidden)]
+ pub const GAMMA: i16 = -32;
+ 
+ /*
+ # the following Python code generates this table:
+ for i in xrange(-308, 333, 8):
+     if i >= 0: f = 10**i; e = 0
+     else: f = 2**(80-4*i) // 10**-i; e = 4 * i - 80
+     l = f.bit_length()
+     f = ((f << 64 >> (l-1)) + 1) >> 1; e += l - 64
+     print '    (%#018x, %5d, %4d),' % (f, e, i)
+ */
+ 
+ #[doc(hidden)]
+ pub static CACHED_POW10: [(u64, i16, i16); 81] = [
+     // (f, e, k)
+     (0xe61acf033d1a45df, -1087, -308),
+     (0xab70fe17c79ac6ca, -1060, -300),
+     (0xff77b1fcbebcdc4f, -1034, -292),
+     (0xbe5691ef416bd60c, -1007, -284),
+     (0x8dd01fad907ffc3c, -980, -276),
+     (0xd3515c2831559a83, -954, -268),
+     (0x9d71ac8fada6c9b5, -927, -260),
+     (0xea9c227723ee8bcb, -901, -252),
+     (0xaecc49914078536d, -874, -244),
+     (0x823c12795db6ce57, -847, -236),
+     (0xc21094364dfb5637, -821, -228),
+     (0x9096ea6f3848984f, -794, -220),
+     (0xd77485cb25823ac7, -768, -212),
+     (0xa086cfcd97bf97f4, -741, -204),
+     (0xef340a98172aace5, -715, -196),
+     (0xb23867fb2a35b28e, -688, -188),
+     (0x84c8d4dfd2c63f3b, -661, -180),
+     (0xc5dd44271ad3cdba, -635, -172),
+     (0x936b9fcebb25c996, -608, -164),
+     (0xdbac6c247d62a584, -582, -156),
+     (0xa3ab66580d5fdaf6, -555, -148),
+     (0xf3e2f893dec3f126, -529, -140),
+     (0xb5b5ada8aaff80b8, -502, -132),
+     (0x87625f056c7c4a8b, -475, -124),
+     (0xc9bcff6034c13053, -449, -116),
+     (0x964e858c91ba2655, -422, -108),
+     (0xdff9772470297ebd, -396, -100),
+     (0xa6dfbd9fb8e5b88f, -369, -92),
+     (0xf8a95fcf88747d94, -343, -84),
+     (0xb94470938fa89bcf, -316, -76),
+     (0x8a08f0f8bf0f156b, -289, -68),
+     (0xcdb02555653131b6, -263, -60),
+     (0x993fe2c6d07b7fac, -236, -52),
+     (0xe45c10c42a2b3b06, -210, -44),
+     (0xaa242499697392d3, -183, -36),
+     (0xfd87b5f28300ca0e, -157, -28),
+     (0xbce5086492111aeb, -130, -20),
+     (0x8cbccc096f5088cc, -103, -12),
+     (0xd1b71758e219652c, -77, -4),
+     (0x9c40000000000000, -50, 4),
+     (0xe8d4a51000000000, -24, 12),
+     (0xad78ebc5ac620000, 3, 20),
+     (0x813f3978f8940984, 30, 28),
+     (0xc097ce7bc90715b3, 56, 36),
+     (0x8f7e32ce7bea5c70, 83, 44),
+     (0xd5d238a4abe98068, 109, 52),
+     (0x9f4f2726179a2245, 136, 60),
+     (0xed63a231d4c4fb27, 162, 68),
+     (0xb0de65388cc8ada8, 189, 76),
+     (0x83c7088e1aab65db, 216, 84),
+     (0xc45d1df942711d9a, 242, 92),
+     (0x924d692ca61be758, 269, 100),
+     (0xda01ee641a708dea, 295, 108),
+     (0xa26da3999aef774a, 322, 116),
+     (0xf209787bb47d6b85, 348, 124),
+     (0xb454e4a179dd1877, 375, 132),
+     (0x865b86925b9bc5c2, 402, 140),
+     (0xc83553c5c8965d3d, 428, 148),
+     (0x952ab45cfa97a0b3, 455, 156),
+     (0xde469fbd99a05fe3, 481, 164),
+     (0xa59bc234db398c25, 508, 172),
+     (0xf6c69a72a3989f5c, 534, 180),
+     (0xb7dcbf5354e9bece, 561, 188),
+     (0x88fcf317f22241e2, 588, 196),
+     (0xcc20ce9bd35c78a5, 614, 204),
+     (0x98165af37b2153df, 641, 212),
+     (0xe2a0b5dc971f303a, 667, 220),
+     (0xa8d9d1535ce3b396, 694, 228),
+     (0xfb9b7cd9a4a7443c, 720, 236),
+     (0xbb764c4ca7a44410, 747, 244),
+     (0x8bab8eefb6409c1a, 774, 252),
+     (0xd01fef10a657842c, 800, 260),
+     (0x9b10a4e5e9913129, 827, 268),
+     (0xe7109bfba19c0c9d, 853, 276),
+     (0xac2820d9623bf429, 880, 284),
+     (0x80444b5e7aa7cf85, 907, 292),
+     (0xbf21e44003acdd2d, 933, 300),
+     (0x8e679c2f5e44ff8f, 960, 308),
+     (0xd433179d9c8cb841, 986, 316),
+     (0x9e19db92b4e31ba9, 1013, 324),
+     (0xeb96bf6ebadf77d9, 1039, 332),
+ ];
+ 
+ #[doc(hidden)]
+ pub const CACHED_POW10_FIRST_E: i16 = -1087;
+ #[doc(hidden)]
+ pub const CACHED_POW10_LAST_E: i16 = 1039;
+ 
+ #[doc(hidden)]
+ pub fn cached_power(alpha: i16, gamma: i16) -> (i16, Fp) {
+     let offset = CACHED_POW10_FIRST_E as i32;
+     let range = (CACHED_POW10.len() as i32) - 1;
+     let domain = (CACHED_POW10_LAST_E - CACHED_POW10_FIRST_E) as i32;
+     let idx = ((gamma as i32) - offset) * range / domain;
+     let (f, e, k) = CACHED_POW10[idx as usize];
+     debug_assert!(alpha <= e && e <= gamma);
+     (k, Fp { f, e })
+ }
+ 
+ /// Given `x > 0`, returns `(k, 10^k)` such that `10^k <= x < 10^(k+1)`.
+ #[doc(hidden)]
+ pub fn max_pow10_no_more_than(x: u32) -> (u8, u32) {
+     debug_assert!(x > 0);
+ 
+     const X9: u32 = 10_0000_0000;
+     const X8: u32 = 1_0000_0000;
+     const X7: u32 = 1000_0000;
+     const X6: u32 = 100_0000;
+     const X5: u32 = 10_0000;
+     const X4: u32 = 1_0000;
+     const X3: u32 = 1000;
+     const X2: u32 = 100;
+     const X1: u32 = 10;
+ 
+     if x < X4 {
+         if x < X2 {
+             if x < X1 { (0, 1) } else { (1, X1) }
+         } else {
+             if x < X3 { (2, X2) } else { (3, X3) }
+         }
+     } else {
+         if x < X6 {
+             if x < X5 { (4, X4) } else { (5, X5) }
+         } else if x < X8 {
+             if x < X7 { (6, X6) } else { (7, X7) }
+         } else {
+             if x < X9 { (8, X8) } else { (9, X9) }
+         }
+     }
+ }
+ 
+ /// The shortest mode implementation for Grisu.
+ ///
+ /// It returns `None` when it would return an inexact representation otherwise.
+ pub fn format_shortest_opt<'a>(
+     d: &Decoded,
+     buf: &'a mut [MaybeUninit<u8>],
+ ) -> Option<(/*digits*/ &'a [u8], /*exp*/ i16)> {
+     assert!(d.mant > 0);
+     assert!(d.minus > 0);
+     assert!(d.plus > 0);
+     assert!(d.mant.checked_add(d.plus).is_some());
+     assert!(d.mant.checked_sub(d.minus).is_some());
+     assert!(buf.len() >= MAX_SIG_DIGITS);
+     assert!(d.mant + d.plus < (1 << 61)); // we need at least three bits of additional precision
+ 
+     // start with the normalized values with the shared exponent
+     let plus = Fp { f: d.mant + d.plus, e: d.exp }.normalize();
+     let minus = Fp { f: d.mant - d.minus, e: d.exp }.normalize_to(plus.e);
+     let v = Fp { f: d.mant, e: d.exp }.normalize_to(plus.e);
+ 
+     // find any `cached = 10^minusk` such that `ALPHA <= minusk + plus.e + 64 <= GAMMA`.
+     // since `plus` is normalized, this means `2^(62 + ALPHA) <= plus * cached < 2^(64 + GAMMA)`;
+     // given our choices of `ALPHA` and `GAMMA`, this puts `plus * cached` into `[4, 2^32)`.
+     //
+     // it is obviously desirable to maximize `GAMMA - ALPHA`,
+     // so that we don't need many cached powers of 10, but there are some considerations:
+     //
+     // 1. we want to keep `floor(plus * cached)` within `u32` since it needs a costly division.
+     //    (this is not really avoidable, remainder is required for accuracy estimation.)
+     // 2. the remainder of `floor(plus * cached)` repeatedly gets multiplied by 10,
+     //    and it should not overflow.
+     //
+     // the first gives `64 + GAMMA <= 32`, while the second gives `10 * 2^-ALPHA <= 2^64`;
+     // -60 and -32 is the maximal range with this constraint, and V8 also uses them.
+     let (minusk, cached) = cached_power(ALPHA - plus.e - 64, GAMMA - plus.e - 64);
+ 
+     // scale fps. this gives the maximal error of 1 ulp (proved from Theorem 5.1).
+     let plus = plus.mul(&cached);
+     let minus = minus.mul(&cached);
+     let v = v.mul(&cached);
+     debug_assert_eq!(plus.e, minus.e);
+     debug_assert_eq!(plus.e, v.e);
+ 
+     //         +- actual range of minus
+     //   | <---|---------------------- unsafe region --------------------------> |
+     //   |     |                                                                 |
+     //   |  |<--->|  | <--------------- safe region ---------------> |           |
+     //   |  |     |  |                                               |           |
+     //   |1 ulp|1 ulp|                 |1 ulp|1 ulp|                 |1 ulp|1 ulp|
+     //   |<--->|<--->|                 |<--->|<--->|                 |<--->|<--->|
+     //   |-----|-----|-------...-------|-----|-----|-------...-------|-----|-----|
+     //   |   minus   |                 |     v     |                 |   plus    |
+     // minus1     minus0           v - 1 ulp   v + 1 ulp           plus0       plus1
+     //
+     // above `minus`, `v` and `plus` are *quantized* approximations (error < 1 ulp).
+     // as we don't know the error is positive or negative, we use two approximations spaced equally
+     // and have the maximal error of 2 ulps.
+     //
+     // the "unsafe region" is a liberal interval which we initially generate.
+     // the "safe region" is a conservative interval which we only accept.
+     // we start with the correct repr within the unsafe region, and try to find the closest repr
+     // to `v` which is also within the safe region. if we can't, we give up.
+     let plus1 = plus.f + 1;
+     //  let plus0 = plus.f - 1; // only for explanation
+     //  let minus0 = minus.f + 1; // only for explanation
+     let minus1 = minus.f - 1;
+     let e = -plus.e as usize; // shared exponent
+ 
+     // divide `plus1` into integral and fractional parts.
+     // integral parts are guaranteed to fit in u32, since cached power guarantees `plus < 2^32`
+     // and normalized `plus.f` is always less than `2^64 - 2^4` due to the precision requirement.
+     let plus1int = (plus1 >> e) as u32;
+     let plus1frac = plus1 & ((1 << e) - 1);
+ 
+     // calculate the largest `10^max_kappa` no more than `plus1` (thus `plus1 < 10^(max_kappa+1)`).
+     // this is an upper bound of `kappa` below.
+     let (max_kappa, max_ten_kappa) = max_pow10_no_more_than(plus1int);
+ 
+     let mut i = 0;
+     let exp = max_kappa as i16 - minusk + 1;
+ 
+     // Theorem 6.2: if `k` is the greatest integer s.t. `0 <= y mod 10^k <= y - x`,
+     //              then `V = floor(y / 10^k) * 10^k` is in `[x, y]` and one of the shortest
+     //              representations (with the minimal number of significant digits) in that range.
+     //
+     // find the digit length `kappa` between `(minus1, plus1)` as per Theorem 6.2.
+     // Theorem 6.2 can be adopted to exclude `x` by requiring `y mod 10^k < y - x` instead.
+     // (e.g., `x` = 32000, `y` = 32777; `kappa` = 2 since `y mod 10^3 = 777 < y - x = 777`.)
+     // the algorithm relies on the later verification phase to exclude `y`.
+     let delta1 = plus1 - minus1;
+     //  let delta1int = (delta1 >> e) as usize; // only for explanation
+     let delta1frac = delta1 & ((1 << e) - 1);
+ 
+     // render integral parts, while checking for the accuracy at each step.
+     let mut kappa = max_kappa as i16;
+     let mut ten_kappa = max_ten_kappa; // 10^kappa
+     let mut remainder = plus1int; // digits yet to be rendered
+     loop {
+         // we always have at least one digit to render, as `plus1 >= 10^kappa`
+         // invariants:
+         // - `delta1int <= remainder < 10^(kappa+1)`
+         // - `plus1int = d[0..n-1] * 10^(kappa+1) + remainder`
+         //   (it follows that `remainder = plus1int % 10^(kappa+1)`)
+ 
+         // divide `remainder` by `10^kappa`. both are scaled by `2^-e`.
+         let q = remainder / ten_kappa;
+         let r = remainder % ten_kappa;
+         debug_assert!(q < 10);
+         buf[i] = MaybeUninit::new(b'0' + q as u8);
+         i += 1;
+ 
+         let plus1rem = ((r as u64) << e) + plus1frac; // == (plus1 % 10^kappa) * 2^e
+         if plus1rem < delta1 {
+             // `plus1 % 10^kappa < delta1 = plus1 - minus1`; we've found the correct `kappa`.
+             let ten_kappa = (ten_kappa as u64) << e; // scale 10^kappa back to the shared exponent
+             return round_and_weed(
+                 // SAFETY: we initialized that memory above.
+                 unsafe { MaybeUninit::slice_assume_init_mut(&mut buf[..i]) },
+                 exp,
+                 plus1rem,
+                 delta1,
+                 plus1 - v.f,
+                 ten_kappa,
+                 1,
+             );
+         }
+ 
+         // break the loop when we have rendered all integral digits.
+         // the exact number of digits is `max_kappa + 1` as `plus1 < 10^(max_kappa+1)`.
+         if i > max_kappa as usize {
+             debug_assert_eq!(ten_kappa, 1);
+             debug_assert_eq!(kappa, 0);
+             break;
+         }
+ 
+         // restore invariants
+         kappa -= 1;
+         ten_kappa /= 10;
+         remainder = r;
+     }
+ 
+     // render fractional parts, while checking for the accuracy at each step.
+     // this time we rely on repeated multiplications, as division will lose the precision.
+     let mut remainder = plus1frac;
+     let mut threshold = delta1frac;
+     let mut ulp = 1;
+     loop {
+         // the next digit should be significant as we've tested that before breaking out
+         // invariants, where `m = max_kappa + 1` (# of digits in the integral part):
+         // - `remainder < 2^e`
+         // - `plus1frac * 10^(n-m) = d[m..n-1] * 2^e + remainder`
+ 
+         remainder *= 10; // won't overflow, `2^e * 10 < 2^64`
+         threshold *= 10;
+         ulp *= 10;
+ 
+         // divide `remainder` by `10^kappa`.
+         // both are scaled by `2^e / 10^kappa`, so the latter is implicit here.
+         let q = remainder >> e;
+         let r = remainder & ((1 << e) - 1);
+         debug_assert!(q < 10);
+         buf[i] = MaybeUninit::new(b'0' + q as u8);
+         i += 1;
+ 
+         if r < threshold {
+             let ten_kappa = 1 << e; // implicit divisor
+             return round_and_weed(
+                 // SAFETY: we initialized that memory above.
+                 unsafe { MaybeUninit::slice_assume_init_mut(&mut buf[..i]) },
+                 exp,
+                 r,
+                 threshold,
+                 (plus1 - v.f) * ulp,
+                 ten_kappa,
+                 ulp,
+             );
+         }
+ 
+         // restore invariants
+         kappa -= 1;
+         remainder = r;
+     }
+ 
+     // we've generated all significant digits of `plus1`, but not sure if it's the optimal one.
+     // for example, if `minus1` is 3.14153... and `plus1` is 3.14158..., there are 5 different
+     // shortest representation from 3.14154 to 3.14158 but we only have the greatest one.
+     // we have to successively decrease the last digit and check if this is the optimal repr.
+     // there are at most 9 candidates (..1 to ..9), so this is fairly quick. ("rounding" phase)
+     //
+     // the function checks if this "optimal" repr is actually within the ulp ranges,
+     // and also, it is possible that the "second-to-optimal" repr can actually be optimal
+     // due to the rounding error. in either cases this returns `None`. ("weeding" phase)
+     //
+     // all arguments here are scaled by the common (but implicit) value `k`, so that:
+     // - `remainder = (plus1 % 10^kappa) * k`
+     // - `threshold = (plus1 - minus1) * k` (and also, `remainder < threshold`)
+     // - `plus1v = (plus1 - v) * k` (and also, `threshold > plus1v` from prior invariants)
+     // - `ten_kappa = 10^kappa * k`
+     // - `ulp = 2^-e * k`
+     fn round_and_weed(
+         buf: &mut [u8],
+         exp: i16,
+         remainder: u64,
+         threshold: u64,
+         plus1v: u64,
+         ten_kappa: u64,
+         ulp: u64,
+     ) -> Option<(&[u8], i16)> {
+         assert!(!buf.is_empty());
+ 
+         // produce two approximations to `v` (actually `plus1 - v`) within 1.5 ulps.
+         // the resulting representation should be the closest representation to both.
+         //
+         // here `plus1 - v` is used since calculations are done with respect to `plus1`
+         // in order to avoid overflow/underflow (hence the seemingly swapped names).
+         let plus1v_down = plus1v + ulp; // plus1 - (v - 1 ulp)
+         let plus1v_up = plus1v - ulp; // plus1 - (v + 1 ulp)
+ 
+         // decrease the last digit and stop at the closest representation to `v + 1 ulp`.
+         let mut plus1w = remainder; // plus1w(n) = plus1 - w(n)
+         {
+             let last = buf.last_mut().unwrap();
+ 
+             // we work with the approximated digits `w(n)`, which is initially equal to `plus1 -
+             // plus1 % 10^kappa`. after running the loop body `n` times, `w(n) = plus1 -
+             // plus1 % 10^kappa - n * 10^kappa`. we set `plus1w(n) = plus1 - w(n) =
+             // plus1 % 10^kappa + n * 10^kappa` (thus `remainder = plus1w(0)`) to simplify checks.
+             // note that `plus1w(n)` is always increasing.
+             //
+             // we have three conditions to terminate. any of them will make the loop unable to
+             // proceed, but we then have at least one valid representation known to be closest to
+             // `v + 1 ulp` anyway. we will denote them as TC1 through TC3 for brevity.
+             //
+             // TC1: `w(n) <= v + 1 ulp`, i.e., this is the last repr that can be the closest one.
+             // this is equivalent to `plus1 - w(n) = plus1w(n) >= plus1 - (v + 1 ulp) = plus1v_up`.
+             // combined with TC2 (which checks if `w(n+1)` is valid), this prevents the possible
+             // overflow on the calculation of `plus1w(n)`.
+             //
+             // TC2: `w(n+1) < minus1`, i.e., the next repr definitely does not round to `v`.
+             // this is equivalent to `plus1 - w(n) + 10^kappa = plus1w(n) + 10^kappa >
+             // plus1 - minus1 = threshold`. the left hand side can overflow, but we know
+             // `threshold > plus1v`, so if TC1 is false, `threshold - plus1w(n) >
+             // threshold - (plus1v - 1 ulp) > 1 ulp` and we can safely test if
+             // `threshold - plus1w(n) < 10^kappa` instead.
+             //
+             // TC3: `abs(w(n) - (v + 1 ulp)) <= abs(w(n+1) - (v + 1 ulp))`, i.e., the next repr is
+             // no closer to `v + 1 ulp` than the current repr. given `z(n) = plus1v_up - plus1w(n)`,
+             // this becomes `abs(z(n)) <= abs(z(n+1))`. again assuming that TC1 is false, we have
+             // `z(n) > 0`. we have two cases to consider:
+             //
+             // - when `z(n+1) >= 0`: TC3 becomes `z(n) <= z(n+1)`. as `plus1w(n)` is increasing,
+             //   `z(n)` should be decreasing and this is clearly false.
+             // - when `z(n+1) < 0`:
+             //   - TC3a: the precondition is `plus1v_up < plus1w(n) + 10^kappa`. assuming TC2 is
+             //     false, `threshold >= plus1w(n) + 10^kappa` so it cannot overflow.
+             //   - TC3b: TC3 becomes `z(n) <= -z(n+1)`, i.e., `plus1v_up - plus1w(n) >=
+             //     plus1w(n+1) - plus1v_up = plus1w(n) + 10^kappa - plus1v_up`. the negated TC1
+             //     gives `plus1v_up > plus1w(n)`, so it cannot overflow or underflow when
+             //     combined with TC3a.
+             //
+             // consequently, we should stop when `TC1 || TC2 || (TC3a && TC3b)`. the following is
+             // equal to its inverse, `!TC1 && !TC2 && (!TC3a || !TC3b)`.
+             while plus1w < plus1v_up
+                 && threshold - plus1w >= ten_kappa
+                 && (plus1w + ten_kappa < plus1v_up
+                     || plus1v_up - plus1w >= plus1w + ten_kappa - plus1v_up)
+             {
+                 *last -= 1;
+                 debug_assert!(*last > b'0'); // the shortest repr cannot end with `0`
+                 plus1w += ten_kappa;
+             }
+         }
+ 
+         // check if this representation is also the closest representation to `v - 1 ulp`.
+         //
+         // this is simply same to the terminating conditions for `v + 1 ulp`, with all `plus1v_up`
+         // replaced by `plus1v_down` instead. overflow analysis equally holds.
+         if plus1w < plus1v_down
+             && threshold - plus1w >= ten_kappa
+             && (plus1w + ten_kappa < plus1v_down
+                 || plus1v_down - plus1w >= plus1w + ten_kappa - plus1v_down)
+         {
+             return None;
+         }
+ 
+         // now we have the closest representation to `v` between `plus1` and `minus1`.
+         // this is too liberal, though, so we reject any `w(n)` not between `plus0` and `minus0`,
+         // i.e., `plus1 - plus1w(n) <= minus0` or `plus1 - plus1w(n) >= plus0`. we utilize the facts
+         // that `threshold = plus1 - minus1` and `plus1 - plus0 = minus0 - minus1 = 2 ulp`.
+         if 2 * ulp <= plus1w && plus1w <= threshold - 4 * ulp { Some((buf, exp)) } else { None }
+     }
+ }
+ 
+ /// The shortest mode implementation for Grisu with Dragon fallback.
+ ///
+ /// This should be used for most cases.
+ pub fn format_shortest<'a>(
+     d: &Decoded,
+     buf: &'a mut [MaybeUninit<u8>],
+ ) -> (/*digits*/ &'a [u8], /*exp*/ i16) {
+     use crate::num::flt2dec::strategy::dragon::format_shortest as fallback;
+     // SAFETY: The borrow checker is not smart enough to let us use `buf`
+     // in the second branch, so we launder the lifetime here. But we only re-use
+     // `buf` if `format_shortest_opt` returned `None` so this is okay.
+     match format_shortest_opt(d, unsafe { &mut *(buf as *mut _) }) {
+         Some(ret) => ret,
+         None => fallback(d, buf),
+     }
+ }
+ 
+ /// The exact and fixed mode implementation for Grisu.
+ ///
+ /// It returns `None` when it would return an inexact representation otherwise.
+ pub fn format_exact_opt<'a>(
+     d: &Decoded,
+     buf: &'a mut [MaybeUninit<u8>],
+     limit: i16,
+ ) -> Option<(/*digits*/ &'a [u8], /*exp*/ i16)> {
+     assert!(d.mant > 0);
+     assert!(d.mant < (1 << 61)); // we need at least three bits of additional precision
+     assert!(!buf.is_empty());
+ 
+     // normalize and scale `v`.
+     let v = Fp { f: d.mant, e: d.exp }.normalize();
+     let (minusk, cached) = cached_power(ALPHA - v.e - 64, GAMMA - v.e - 64);
+     let v = v.mul(&cached);
+ 
+     // divide `v` into integral and fractional parts.
+     let e = -v.e as usize;
+     let vint = (v.f >> e) as u32;
+     let vfrac = v.f & ((1 << e) - 1);
+ 
+     // both old `v` and new `v` (scaled by `10^-k`) has an error of < 1 ulp (Theorem 5.1).
+     // as we don't know the error is positive or negative, we use two approximations
+     // spaced equally and have the maximal error of 2 ulps (same to the shortest case).
+     //
+     // the goal is to find the exactly rounded series of digits that are common to
+     // both `v - 1 ulp` and `v + 1 ulp`, so that we are maximally confident.
+     // if this is not possible, we don't know which one is the correct output for `v`,
+     // so we give up and fall back.
+     //
+     // `err` is defined as `1 ulp * 2^e` here (same to the ulp in `vfrac`),
+     // and we will scale it whenever `v` gets scaled.
+     let mut err = 1;
+ 
+     // calculate the largest `10^max_kappa` no more than `v` (thus `v < 10^(max_kappa+1)`).
+     // this is an upper bound of `kappa` below.
+     let (max_kappa, max_ten_kappa) = max_pow10_no_more_than(vint);
+ 
+     let mut i = 0;
+     let exp = max_kappa as i16 - minusk + 1;
+ 
+     // if we are working with the last-digit limitation, we need to shorten the buffer
+     // before the actual rendering in order to avoid double rounding.
+     // note that we have to enlarge the buffer again when rounding up happens!
+     let len = if exp <= limit {
+         // oops, we cannot even produce *one* digit.
+         // this is possible when, say, we've got something like 9.5 and it's being rounded to 10.
+         //
+         // in principle we can immediately call `possibly_round` with an empty buffer,
+         // but scaling `max_ten_kappa << e` by 10 can result in overflow.
+         // thus we are being sloppy here and widen the error range by a factor of 10.
+         // this will increase the false negative rate, but only very, *very* slightly;
+         // it can only matter noticeably when the mantissa is bigger than 60 bits.
+         //
+         // SAFETY: `len=0`, so the obligation of having initialized this memory is trivial.
+         return unsafe {
+             possibly_round(buf, 0, exp, limit, v.f / 10, (max_ten_kappa as u64) << e, err << e)
+         };
+     } else if ((exp as i32 - limit as i32) as usize) < buf.len() {
+         (exp - limit) as usize
+     } else {
+         buf.len()
+     };
+     debug_assert!(len > 0);
+ 
+     // render integral parts.
+     // the error is entirely fractional, so we don't need to check it in this part.
+     let mut kappa = max_kappa as i16;
+     let mut ten_kappa = max_ten_kappa; // 10^kappa
+     let mut remainder = vint; // digits yet to be rendered
+     loop {
+         // we always have at least one digit to render
+         // invariants:
+         // - `remainder < 10^(kappa+1)`
+         // - `vint = d[0..n-1] * 10^(kappa+1) + remainder`
+         //   (it follows that `remainder = vint % 10^(kappa+1)`)
+ 
+         // divide `remainder` by `10^kappa`. both are scaled by `2^-e`.
+         let q = remainder / ten_kappa;
+         let r = remainder % ten_kappa;
+         debug_assert!(q < 10);
+         buf[i] = MaybeUninit::new(b'0' + q as u8);
+         i += 1;
+ 
+         // is the buffer full? run the rounding pass with the remainder.
+         if i == len {
+             let vrem = ((r as u64) << e) + vfrac; // == (v % 10^kappa) * 2^e
+             // SAFETY: we have initialized `len` many bytes.
+             return unsafe {
+                 possibly_round(buf, len, exp, limit, vrem, (ten_kappa as u64) << e, err << e)
+             };
+         }
+ 
+         // break the loop when we have rendered all integral digits.
+         // the exact number of digits is `max_kappa + 1` as `plus1 < 10^(max_kappa+1)`.
+         if i > max_kappa as usize {
+             debug_assert_eq!(ten_kappa, 1);
+             debug_assert_eq!(kappa, 0);
+             break;
+         }
+ 
+         // restore invariants
+         kappa -= 1;
+         ten_kappa /= 10;
+         remainder = r;
+     }
+ 
+     // render fractional parts.
+     //
+     // in principle we can continue to the last available digit and check for the accuracy.
+     // unfortunately we are working with the finite-sized integers, so we need some criterion
+     // to detect the overflow. V8 uses `remainder > err`, which becomes false when
+     // the first `i` significant digits of `v - 1 ulp` and `v` differ. however this rejects
+     // too many otherwise valid input.
+     //
+     // since the later phase has a correct overflow detection, we instead use tighter criterion:
+     // we continue til `err` exceeds `10^kappa / 2`, so that the range between `v - 1 ulp` and
+     // `v + 1 ulp` definitely contains two or more rounded representations. this is same to
+     // the first two comparisons from `possibly_round`, for the reference.
+     let mut remainder = vfrac;
+     let maxerr = 1 << (e - 1);
+     while err < maxerr {
+         // invariants, where `m = max_kappa + 1` (# of digits in the integral part):
+         // - `remainder < 2^e`
+         // - `vfrac * 10^(n-m) = d[m..n-1] * 2^e + remainder`
+         // - `err = 10^(n-m)`
+ 
+         remainder *= 10; // won't overflow, `2^e * 10 < 2^64`
+         err *= 10; // won't overflow, `err * 10 < 2^e * 5 < 2^64`
+ 
+         // divide `remainder` by `10^kappa`.
+         // both are scaled by `2^e / 10^kappa`, so the latter is implicit here.
+         let q = remainder >> e;
+         let r = remainder & ((1 << e) - 1);
+         debug_assert!(q < 10);
+         buf[i] = MaybeUninit::new(b'0' + q as u8);
+         i += 1;
+ 
+         // is the buffer full? run the rounding pass with the remainder.
+         if i == len {
+             // SAFETY: we have initialized `len` many bytes.
+             return unsafe { possibly_round(buf, len, exp, limit, r, 1 << e, err) };
+         }
+ 
+         // restore invariants
+         remainder = r;
+     }
+ 
+     // further calculation is useless (`possibly_round` definitely fails), so we give up.
+     return None;
+ 
+     // we've generated all requested digits of `v`, which should be also same to corresponding
+     // digits of `v - 1 ulp`. now we check if there is a unique representation shared by
+     // both `v - 1 ulp` and `v + 1 ulp`; this can be either same to generated digits, or
+     // to the rounded-up version of those digits. if the range contains multiple representations
+     // of the same length, we cannot be sure and should return `None` instead.
+     //
+     // all arguments here are scaled by the common (but implicit) value `k`, so that:
+     // - `remainder = (v % 10^kappa) * k`
+     // - `ten_kappa = 10^kappa * k`
+     // - `ulp = 2^-e * k`
+     //
+     // SAFETY: the first `len` bytes of `buf` must be initialized.
+     unsafe fn possibly_round(
+         buf: &mut [MaybeUninit<u8>],
+         mut len: usize,
+         mut exp: i16,
+         limit: i16,
+         remainder: u64,
+         ten_kappa: u64,
+         ulp: u64,
+     ) -> Option<(&[u8], i16)> {
+         debug_assert!(remainder < ten_kappa);
+ 
+         //           10^kappa
+         //    :   :   :<->:   :
+         //    :   :   :   :   :
+         //    :|1 ulp|1 ulp|  :
+         //    :|<--->|<--->|  :
+         // ----|-----|-----|----
+         //     |     v     |
+         // v - 1 ulp   v + 1 ulp
+         //
+         // (for the reference, the dotted line indicates the exact value for
+         // possible representations in given number of digits.)
+         //
+         // error is too large that there are at least three possible representations
+         // between `v - 1 ulp` and `v + 1 ulp`. we cannot determine which one is correct.
+         if ulp >= ten_kappa {
+             return None;
+         }
+ 
+         //    10^kappa
+         //   :<------->:
+         //   :         :
+         //   : |1 ulp|1 ulp|
+         //   : |<--->|<--->|
+         // ----|-----|-----|----
+         //     |     v     |
+         // v - 1 ulp   v + 1 ulp
+         //
+         // in fact, 1/2 ulp is enough to introduce two possible representations.
+         // (remember that we need a unique representation for both `v - 1 ulp` and `v + 1 ulp`.)
+         // this won't overflow, as `ulp < ten_kappa` from the first check.
+         if ten_kappa - ulp <= ulp {
+             return None;
+         }
+ 
+         //     remainder
+         //       :<->|                           :
+         //       :   |                           :
+         //       :<--------- 10^kappa ---------->:
+         //     | :   |                           :
+         //     |1 ulp|1 ulp|                     :
+         //     |<--->|<--->|                     :
+         // ----|-----|-----|------------------------
+         //     |     v     |
+         // v - 1 ulp   v + 1 ulp
+         //
+         // if `v + 1 ulp` is closer to the rounded-down representation (which is already in `buf`),
+         // then we can safely return. note that `v - 1 ulp` *can* be less than the current
+         // representation, but as `1 ulp < 10^kappa / 2`, this condition is enough:
+         // the distance between `v - 1 ulp` and the current representation
+         // cannot exceed `10^kappa / 2`.
+         //
+         // the condition equals to `remainder + ulp < 10^kappa / 2`.
+         // since this can easily overflow, first check if `remainder < 10^kappa / 2`.
+         // we've already verified that `ulp < 10^kappa / 2`, so as long as
+         // `10^kappa` did not overflow after all, the second check is fine.
+         if ten_kappa - remainder > remainder && ten_kappa - 2 * remainder >= 2 * ulp {
+             // SAFETY: our caller initialized that memory.
+             return Some((unsafe { MaybeUninit::slice_assume_init_ref(&buf[..len]) }, exp));
+         }
+ 
+         //   :<------- remainder ------>|   :
+         //   :                          |   :
+         //   :<--------- 10^kappa --------->:
+         //   :                    |     |   : |
+         //   :                    |1 ulp|1 ulp|
+         //   :                    |<--->|<--->|
+         // -----------------------|-----|-----|-----
+         //                        |     v     |
+         //                    v - 1 ulp   v + 1 ulp
+         //
+         // on the other hands, if `v - 1 ulp` is closer to the rounded-up representation,
+         // we should round up and return. for the same reason we don't need to check `v + 1 ulp`.
+         //
+         // the condition equals to `remainder - ulp >= 10^kappa / 2`.
+         // again we first check if `remainder > ulp` (note that this is not `remainder >= ulp`,
+         // as `10^kappa` is never zero). also note that `remainder - ulp <= 10^kappa`,
+         // so the second check does not overflow.
+         if remainder > ulp && ten_kappa - (remainder - ulp) <= remainder - ulp {
+             if let Some(c) =
+                 // SAFETY: our caller must have initialized that memory.
+                 round_up(unsafe { MaybeUninit::slice_assume_init_mut(&mut buf[..len]) })
+             {
+                 // only add an additional digit when we've been requested the fixed precision.
+                 // we also need to check that, if the original buffer was empty,
+                 // the additional digit can only be added when `exp == limit` (edge case).
+                 exp += 1;
+                 if exp > limit && len < buf.len() {
+                     buf[len] = MaybeUninit::new(c);
+                     len += 1;
+                 }
+             }
+             // SAFETY: we and our caller initialized that memory.
+             return Some((unsafe { MaybeUninit::slice_assume_init_ref(&buf[..len]) }, exp));
+         }
+ 
+         // otherwise we are doomed (i.e., some values between `v - 1 ulp` and `v + 1 ulp` are
+         // rounding down and others are rounding up) and give up.
+         None
+     }
+ }
+ 
+ /// The exact and fixed mode implementation for Grisu with Dragon fallback.
+ ///
+ /// This should be used for most cases.
+ pub fn format_exact<'a>(
+     d: &Decoded,
+     buf: &'a mut [MaybeUninit<u8>],
+     limit: i16,
+ ) -> (/*digits*/ &'a [u8], /*exp*/ i16) {
+     use crate::num::flt2dec::strategy::dragon::format_exact as fallback;
+     // SAFETY: The borrow checker is not smart enough to let us use `buf`
+     // in the second branch, so we launder the lifetime here. But we only re-use
+     // `buf` if `format_exact_opt` returned `None` so this is okay.
+     match format_exact_opt(d, unsafe { &mut *(buf as *mut _) }, limit) {
+         Some(ret) => ret,
+         None => fallback(d, buf, limit),
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/int_macros.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/int_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/int_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/int_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2240 ----
+ macro_rules! int_impl {
+     ($SelfT:ty, $ActualT:ident, $UnsignedT:ty, $BITS:expr, $Min:expr, $Max:expr, $Feature:expr,
+      $EndFeature:expr, $rot:expr, $rot_op:expr, $rot_result:expr, $swap_op:expr, $swapped:expr,
+      $reversed:expr, $le_bytes:expr, $be_bytes:expr,
+      $to_xe_bytes_doc:expr, $from_xe_bytes_doc:expr) => {
+         doc_comment! {
+             concat!("The smallest value that can be represented by this integer type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::MIN, ", stringify!($Min), ");",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+             pub const MIN: Self = !0 ^ ((!0 as $UnsignedT) >> 1) as Self;
+         }
+ 
+         doc_comment! {
+             concat!("The largest value that can be represented by this integer type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::MAX, ", stringify!($Max), ");",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+             pub const MAX: Self = !Self::MIN;
+         }
+ 
+         doc_comment! {
+             concat!("The size of this integer type in bits.
+ 
+ # Examples
+ 
+ ```
+ ", $Feature, "#![feature(int_bits_const)]
+ assert_eq!(", stringify!($SelfT), "::BITS, ", stringify!($BITS), ");",
+ $EndFeature, "
+ ```"),
+             #[unstable(feature = "int_bits_const", issue = "76904")]
+             pub const BITS: u32 = $BITS;
+         }
+ 
+         doc_comment! {
+             concat!("Converts a string slice in a given base to an integer.
+ 
+ The string is expected to be an optional `+` or `-` sign followed by digits.
+ Leading and trailing whitespace represent an error. Digits are a subset of these characters,
+ depending on `radix`:
+ 
+  * `0-9`
+  * `a-z`
+  * `A-Z`
+ 
+ # Panics
+ 
+ This function panics if `radix` is not in the range from 2 to 36.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::from_str_radix(\"A\", 16), Ok(10));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             pub fn from_str_radix(src: &str, radix: u32) -> Result<Self, ParseIntError> {
+                 from_str_radix(src, radix)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of ones in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0b100_0000", stringify!($SelfT), ";
+ 
+ assert_eq!(n.count_ones(), 1);",
+ $EndFeature, "
+ ```
+ "),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn count_ones(self) -> u32 { (self as $UnsignedT).count_ones() }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::MAX.count_zeros(), 1);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn count_zeros(self) -> u32 {
+                 (!self).count_ones()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of leading zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = -1", stringify!($SelfT), ";
+ 
+ assert_eq!(n.leading_zeros(), 0);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn leading_zeros(self) -> u32 {
+                 (self as $UnsignedT).leading_zeros()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of trailing zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = -4", stringify!($SelfT), ";
+ 
+ assert_eq!(n.trailing_zeros(), 2);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn trailing_zeros(self) -> u32 {
+                 (self as $UnsignedT).trailing_zeros()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of leading ones in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = -1", stringify!($SelfT), ";
+ 
+ assert_eq!(n.leading_ones(), ", stringify!($BITS), ");",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[rustc_const_stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[inline]
+             pub const fn leading_ones(self) -> u32 {
+                 (self as $UnsignedT).leading_ones()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of trailing ones in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 3", stringify!($SelfT), ";
+ 
+ assert_eq!(n.trailing_ones(), 2);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[rustc_const_stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[inline]
+             pub const fn trailing_ones(self) -> u32 {
+                 (self as $UnsignedT).trailing_ones()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts the bits to the left by a specified amount, `n`,
+ wrapping the truncated bits to the end of the resulting integer.
+ 
+ Please note this isn't the same operation as the `<<` shifting operator!
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $rot_op, stringify!($SelfT), ";
+ let m = ", $rot_result, ";
+ 
+ assert_eq!(n.rotate_left(", $rot, "), m);
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn rotate_left(self, n: u32) -> Self {
+                 (self as $UnsignedT).rotate_left(n) as Self
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts the bits to the right by a specified amount, `n`,
+ wrapping the truncated bits to the beginning of the resulting
+ integer.
+ 
+ Please note this isn't the same operation as the `>>` shifting operator!
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $rot_result, stringify!($SelfT), ";
+ let m = ", $rot_op, ";
+ 
+ assert_eq!(n.rotate_right(", $rot, "), m);
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn rotate_right(self, n: u32) -> Self {
+                 (self as $UnsignedT).rotate_right(n) as Self
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Reverses the byte order of the integer.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $swap_op, stringify!($SelfT), ";
+ 
+ let m = n.swap_bytes();
+ 
+ assert_eq!(m, ", $swapped, ");
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn swap_bytes(self) -> Self {
+                 (self as $UnsignedT).swap_bytes() as Self
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Reverses the order of bits in the integer. The least significant bit becomes the most significant bit,
+                 second least-significant bit becomes second most-significant bit, etc.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $swap_op, stringify!($SelfT), ";
+ let m = n.reverse_bits();
+ 
+ assert_eq!(m, ", $reversed, ");
+ assert_eq!(0, 0", stringify!($SelfT), ".reverse_bits());
+ ```"),
+             #[stable(feature = "reverse_bits", since = "1.37.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             #[must_use]
+             pub const fn reverse_bits(self) -> Self {
+                 (self as $UnsignedT).reverse_bits() as Self
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts an integer from big endian to the target's endianness.
+ 
+ On big endian this is a no-op. On little endian the bytes are swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"big\") {
+     assert_eq!(", stringify!($SelfT), "::from_be(n), n)
+ } else {
+     assert_eq!(", stringify!($SelfT), "::from_be(n), n.swap_bytes())
+ }",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_conversions", since = "1.32.0")]
+             #[inline]
+             pub const fn from_be(x: Self) -> Self {
+                 #[cfg(target_endian = "big")]
+                 {
+                     x
+                 }
+                 #[cfg(not(target_endian = "big"))]
+                 {
+                     x.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts an integer from little endian to the target's endianness.
+ 
+ On little endian this is a no-op. On big endian the bytes are swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"little\") {
+     assert_eq!(", stringify!($SelfT), "::from_le(n), n)
+ } else {
+     assert_eq!(", stringify!($SelfT), "::from_le(n), n.swap_bytes())
+ }",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_conversions", since = "1.32.0")]
+             #[inline]
+             pub const fn from_le(x: Self) -> Self {
+                 #[cfg(target_endian = "little")]
+                 {
+                     x
+                 }
+                 #[cfg(not(target_endian = "little"))]
+                 {
+                     x.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts `self` to big endian from the target's endianness.
+ 
+ On big endian this is a no-op. On little endian the bytes are swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"big\") {
+     assert_eq!(n.to_be(), n)
+ } else {
+     assert_eq!(n.to_be(), n.swap_bytes())
+ }",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_conversions", since = "1.32.0")]
+             #[inline]
+             pub const fn to_be(self) -> Self { // or not to be?
+                 #[cfg(target_endian = "big")]
+                 {
+                     self
+                 }
+                 #[cfg(not(target_endian = "big"))]
+                 {
+                     self.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts `self` to little endian from the target's endianness.
+ 
+ On little endian this is a no-op. On big endian the bytes are swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"little\") {
+     assert_eq!(n.to_le(), n)
+ } else {
+     assert_eq!(n.to_le(), n.swap_bytes())
+ }",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_conversions", since = "1.32.0")]
+             #[inline]
+             pub const fn to_le(self) -> Self {
+                 #[cfg(target_endian = "little")]
+                 {
+                     self
+                 }
+                 #[cfg(not(target_endian = "little"))]
+                 {
+                     self.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer addition. Computes `self + rhs`, returning `None`
+ if overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!((", stringify!($SelfT),
+ "::MAX - 2).checked_add(1), Some(", stringify!($SelfT), "::MAX - 1));
+ assert_eq!((", stringify!($SelfT), "::MAX - 2).checked_add(3), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_add(self, rhs: Self) -> Option<Self> {
+                 let (a, b) = self.overflowing_add(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Unchecked integer addition. Computes `self + rhs`, assuming overflow
+ cannot occur. This results in undefined behavior when `self + rhs > ", stringify!($SelfT),
+ "::MAX` or `self + rhs < ", stringify!($SelfT), "::MIN`."),
+             #[unstable(
+                 feature = "unchecked_math",
+                 reason = "niche optimization path",
+                 issue = "none",
+             )]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub unsafe fn unchecked_add(self, rhs: Self) -> Self {
+                 // SAFETY: the caller must uphold the safety contract for
+                 // `unchecked_add`.
+                 unsafe { intrinsics::unchecked_add(self, rhs) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer subtraction. Computes `self - rhs`, returning `None` if
+ overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!((", stringify!($SelfT),
+ "::MIN + 2).checked_sub(1), Some(", stringify!($SelfT), "::MIN + 1));
+ assert_eq!((", stringify!($SelfT), "::MIN + 2).checked_sub(3), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_sub(self, rhs: Self) -> Option<Self> {
+                 let (a, b) = self.overflowing_sub(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Unchecked integer subtraction. Computes `self - rhs`, assuming overflow
+ cannot occur. This results in undefined behavior when `self - rhs > ", stringify!($SelfT),
+ "::MAX` or `self - rhs < ", stringify!($SelfT), "::MIN`."),
+             #[unstable(
+                 feature = "unchecked_math",
+                 reason = "niche optimization path",
+                 issue = "none",
+             )]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub unsafe fn unchecked_sub(self, rhs: Self) -> Self {
+                 // SAFETY: the caller must uphold the safety contract for
+                 // `unchecked_sub`.
+                 unsafe { intrinsics::unchecked_sub(self, rhs) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer multiplication. Computes `self * rhs`, returning `None` if
+ overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT),
+ "::MAX.checked_mul(1), Some(", stringify!($SelfT), "::MAX));
+ assert_eq!(", stringify!($SelfT), "::MAX.checked_mul(2), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_mul(self, rhs: Self) -> Option<Self> {
+                 let (a, b) = self.overflowing_mul(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Unchecked integer multiplication. Computes `self * rhs`, assuming overflow
+ cannot occur. This results in undefined behavior when `self * rhs > ", stringify!($SelfT),
+ "::MAX` or `self * rhs < ", stringify!($SelfT), "::MIN`."),
+             #[unstable(
+                 feature = "unchecked_math",
+                 reason = "niche optimization path",
+                 issue = "none",
+             )]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub unsafe fn unchecked_mul(self, rhs: Self) -> Self {
+                 // SAFETY: the caller must uphold the safety contract for
+                 // `unchecked_mul`.
+                 unsafe { intrinsics::unchecked_mul(self, rhs) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer division. Computes `self / rhs`, returning `None` if `rhs == 0`
+ or the division results in overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!((", stringify!($SelfT),
+ "::MIN + 1).checked_div(-1), Some(", stringify!($Max), "));
+ assert_eq!(", stringify!($SelfT), "::MIN.checked_div(-1), None);
+ assert_eq!((1", stringify!($SelfT), ").checked_div(0), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_unstable(feature = "const_checked_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_div(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0 || (self == Self::MIN && rhs == -1)) {
+                     None
+                 } else {
+                     // SAFETY: div by zero and by INT_MIN have been checked above
+                     Some(unsafe { intrinsics::unchecked_div(self, rhs) })
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked Euclidean division. Computes `self.div_euclid(rhs)`,
+ returning `None` if `rhs == 0` or the division results in overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!((", stringify!($SelfT),
+ "::MIN + 1).checked_div_euclid(-1), Some(", stringify!($Max), "));
+ assert_eq!(", stringify!($SelfT), "::MIN.checked_div_euclid(-1), None);
+ assert_eq!((1", stringify!($SelfT), ").checked_div_euclid(0), None);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_div_euclid(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0 || (self == Self::MIN && rhs == -1)) {
+                     None
+                 } else {
+                     Some(self.div_euclid(rhs))
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer remainder. Computes `self % rhs`, returning `None` if
+ `rhs == 0` or the division results in overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".checked_rem(2), Some(1));
+ assert_eq!(5", stringify!($SelfT), ".checked_rem(0), None);
+ assert_eq!(", stringify!($SelfT), "::MIN.checked_rem(-1), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_unstable(feature = "const_checked_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_rem(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0 || (self == Self::MIN && rhs == -1)) {
+                     None
+                 } else {
+                     // SAFETY: div by zero and by INT_MIN have been checked above
+                     Some(unsafe { intrinsics::unchecked_rem(self, rhs) })
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked Euclidean remainder. Computes `self.rem_euclid(rhs)`, returning `None`
+ if `rhs == 0` or the division results in overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(5", stringify!($SelfT), ".checked_rem_euclid(2), Some(1));
+ assert_eq!(5", stringify!($SelfT), ".checked_rem_euclid(0), None);
+ assert_eq!(", stringify!($SelfT), "::MIN.checked_rem_euclid(-1), None);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_rem_euclid(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0 || (self == Self::MIN && rhs == -1)) {
+                     None
+                 } else {
+                     Some(self.rem_euclid(rhs))
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked negation. Computes `-self`, returning `None` if `self == MIN`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".checked_neg(), Some(-5));
+ assert_eq!(", stringify!($SelfT), "::MIN.checked_neg(), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn checked_neg(self) -> Option<Self> {
+                 let (a, b) = self.overflowing_neg();
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked shift left. Computes `self << rhs`, returning `None` if `rhs` is larger
+ than or equal to the number of bits in `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0x1", stringify!($SelfT), ".checked_shl(4), Some(0x10));
+ assert_eq!(0x1", stringify!($SelfT), ".checked_shl(129), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_shl(self, rhs: u32) -> Option<Self> {
+                 let (a, b) = self.overflowing_shl(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked shift right. Computes `self >> rhs`, returning `None` if `rhs` is
+ larger than or equal to the number of bits in `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0x10", stringify!($SelfT), ".checked_shr(4), Some(0x1));
+ assert_eq!(0x10", stringify!($SelfT), ".checked_shr(128), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_shr(self, rhs: u32) -> Option<Self> {
+                 let (a, b) = self.overflowing_shr(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked absolute value. Computes `self.abs()`, returning `None` if
+ `self == MIN`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!((-5", stringify!($SelfT), ").checked_abs(), Some(5));
+ assert_eq!(", stringify!($SelfT), "::MIN.checked_abs(), None);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_abs", since = "1.13.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn checked_abs(self) -> Option<Self> {
+                 if self.is_negative() {
+                     self.checked_neg()
+                 } else {
+                     Some(self)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked exponentiation. Computes `self.pow(exp)`, returning `None` if
+ overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(8", stringify!($SelfT), ".checked_pow(2), Some(64));
+ assert_eq!(", stringify!($SelfT), "::MAX.checked_pow(2), None);",
+ $EndFeature, "
+ ```"),
+ 
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_pow(self, mut exp: u32) -> Option<Self> {
+                 if exp == 0 {
+                     return Some(1);
+                 }
+                 let mut base = self;
+                 let mut acc: Self = 1;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         acc = try_opt!(acc.checked_mul(base));
+                     }
+                     exp /= 2;
+                     base = try_opt!(base.checked_mul(base));
+                 }
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+                 Some(try_opt!(acc.checked_mul(base)))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer addition. Computes `self + rhs`, saturating at the numeric
+ bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".saturating_add(1), 101);
+ assert_eq!(", stringify!($SelfT), "::MAX.saturating_add(100), ", stringify!($SelfT),
+ "::MAX);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_add(-1), ", stringify!($SelfT),
+ "::MIN);",
+ $EndFeature, "
+ ```"),
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn saturating_add(self, rhs: Self) -> Self {
+                 intrinsics::saturating_add(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer subtraction. Computes `self - rhs`, saturating at the
+ numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".saturating_sub(127), -27);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_sub(100), ", stringify!($SelfT),
+ "::MIN);
+ assert_eq!(", stringify!($SelfT), "::MAX.saturating_sub(-1), ", stringify!($SelfT),
+ "::MAX);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn saturating_sub(self, rhs: Self) -> Self {
+                 intrinsics::saturating_sub(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer negation. Computes `-self`, returning `MAX` if `self == MIN`
+ instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".saturating_neg(), -100);
+ assert_eq!((-100", stringify!($SelfT), ").saturating_neg(), 100);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_neg(), ", stringify!($SelfT),
+ "::MAX);
+ assert_eq!(", stringify!($SelfT), "::MAX.saturating_neg(), ", stringify!($SelfT),
+ "::MIN + 1);",
+ $EndFeature, "
+ ```"),
+ 
+             #[stable(feature = "saturating_neg", since = "1.45.0")]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn saturating_neg(self) -> Self {
+                 intrinsics::saturating_sub(0, self)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating absolute value. Computes `self.abs()`, returning `MAX` if `self ==
+ MIN` instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".saturating_abs(), 100);
+ assert_eq!((-100", stringify!($SelfT), ").saturating_abs(), 100);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_abs(), ", stringify!($SelfT),
+ "::MAX);
+ assert_eq!((", stringify!($SelfT), "::MIN + 1).saturating_abs(), ", stringify!($SelfT),
+ "::MAX);",
+ $EndFeature, "
+ ```"),
+ 
+             #[stable(feature = "saturating_neg", since = "1.45.0")]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn saturating_abs(self) -> Self {
+                 if self.is_negative() {
+                     self.saturating_neg()
+                 } else {
+                     self
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer multiplication. Computes `self * rhs`, saturating at the
+ numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(10", stringify!($SelfT), ".saturating_mul(12), 120);
+ assert_eq!(", stringify!($SelfT), "::MAX.saturating_mul(10), ", stringify!($SelfT), "::MAX);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_mul(10), ", stringify!($SelfT), "::MIN);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn saturating_mul(self, rhs: Self) -> Self {
+                 match self.checked_mul(rhs) {
+                     Some(x) => x,
+                     None => if (self < 0) == (rhs < 0) {
+                         Self::MAX
+                     } else {
+                         Self::MIN
+                     }
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer exponentiation. Computes `self.pow(exp)`,
+ saturating at the numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!((-4", stringify!($SelfT), ").saturating_pow(3), -64);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_pow(2), ", stringify!($SelfT), "::MAX);
+ assert_eq!(", stringify!($SelfT), "::MIN.saturating_pow(3), ", stringify!($SelfT), "::MIN);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn saturating_pow(self, exp: u32) -> Self {
+                 match self.checked_pow(exp) {
+                     Some(x) => x,
+                     None if self < 0 && exp % 2 == 1 => Self::MIN,
+                     None => Self::MAX,
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) addition. Computes `self + rhs`, wrapping around at the
+ boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_add(27), 127);
+ assert_eq!(", stringify!($SelfT), "::MAX.wrapping_add(2), ", stringify!($SelfT),
+ "::MIN + 1);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_add(self, rhs: Self) -> Self {
+                 intrinsics::wrapping_add(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) subtraction. Computes `self - rhs`, wrapping around at the
+ boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0", stringify!($SelfT), ".wrapping_sub(127), -127);
+ assert_eq!((-2", stringify!($SelfT), ").wrapping_sub(", stringify!($SelfT), "::MAX), ",
+ stringify!($SelfT), "::MAX);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_sub(self, rhs: Self) -> Self {
+                 intrinsics::wrapping_sub(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) multiplication. Computes `self * rhs`, wrapping around at
+ the boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(10", stringify!($SelfT), ".wrapping_mul(12), 120);
+ assert_eq!(11i8.wrapping_mul(12), -124);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_mul(self, rhs: Self) -> Self {
+                 intrinsics::wrapping_mul(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) division. Computes `self / rhs`, wrapping around at the
+ boundary of the type.
+ 
+ The only case where such wrapping can occur is when one divides `MIN / -1` on a signed type (where
+ `MIN` is the negative minimal value for the type); this is equivalent to `-MIN`, a positive value
+ that is too large to represent in the type. In such a case, this function returns `MIN` itself.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_div(10), 10);
+ assert_eq!((-128i8).wrapping_div(-1), -128);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_unstable(feature = "const_wrapping_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_div(self, rhs: Self) -> Self {
+                 self.overflowing_div(rhs).0
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping Euclidean division. Computes `self.div_euclid(rhs)`,
+ wrapping around at the boundary of the type.
+ 
+ Wrapping will only occur in `MIN / -1` on a signed type (where `MIN` is the negative minimal value
+ for the type). This is equivalent to `-MIN`, a positive value that is too large to represent in the
+ type. In this case, this method returns `MIN` itself.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(100", stringify!($SelfT), ".wrapping_div_euclid(10), 10);
+ assert_eq!((-128i8).wrapping_div_euclid(-1), -128);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_div_euclid(self, rhs: Self) -> Self {
+                 self.overflowing_div_euclid(rhs).0
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) remainder. Computes `self % rhs`, wrapping around at the
+ boundary of the type.
+ 
+ Such wrap-around never actually occurs mathematically; implementation artifacts make `x % y`
+ invalid for `MIN / -1` on a signed type (where `MIN` is the negative minimal value). In such a case,
+ this function returns `0`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_rem(10), 0);
+ assert_eq!((-128i8).wrapping_rem(-1), 0);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_unstable(feature = "const_wrapping_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_rem(self, rhs: Self) -> Self {
+                 self.overflowing_rem(rhs).0
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping Euclidean remainder. Computes `self.rem_euclid(rhs)`, wrapping around
+ at the boundary of the type.
+ 
+ Wrapping will only occur in `MIN % -1` on a signed type (where `MIN` is the negative minimal value
+ for the type). In this case, this method returns 0.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(100", stringify!($SelfT), ".wrapping_rem_euclid(10), 0);
+ assert_eq!((-128i8).wrapping_rem_euclid(-1), 0);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_rem_euclid(self, rhs: Self) -> Self {
+                 self.overflowing_rem_euclid(rhs).0
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) negation. Computes `-self`, wrapping around at the boundary
+ of the type.
+ 
+ The only case where such wrapping can occur is when one negates `MIN` on a signed type (where `MIN`
+ is the negative minimal value for the type); this is a positive value that is too large to represent
+ in the type. In such a case, this function returns `MIN` itself.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_neg(), -100);
+ assert_eq!(", stringify!($SelfT), "::MIN.wrapping_neg(), ", stringify!($SelfT),
+ "::MIN);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn wrapping_neg(self) -> Self {
+                 self.overflowing_neg().0
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Panic-free bitwise shift-left; yields `self << mask(rhs)`, where `mask` removes
+ any high-order bits of `rhs` that would cause the shift to exceed the bitwidth of the type.
+ 
+ Note that this is *not* the same as a rotate-left; the RHS of a wrapping shift-left is restricted to
+ the range of the type, rather than the bits shifted out of the LHS being returned to the other end.
+ The primitive integer types all implement a `[`rotate_left`](#method.rotate_left) function,
+ which may be what you want instead.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!((-1", stringify!($SelfT), ").wrapping_shl(7), -128);
+ assert_eq!((-1", stringify!($SelfT), ").wrapping_shl(128), -1);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_shl(self, rhs: u32) -> Self {
+                 // SAFETY: the masking by the bitsize of the type ensures that we do not shift
+                 // out of bounds
+                 unsafe {
+                     intrinsics::unchecked_shl(self, (rhs & ($BITS - 1)) as $SelfT)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Panic-free bitwise shift-right; yields `self >> mask(rhs)`, where `mask`
+ removes any high-order bits of `rhs` that would cause the shift to exceed the bitwidth of the type.
+ 
+ Note that this is *not* the same as a rotate-right; the RHS of a wrapping shift-right is restricted
+ to the range of the type, rather than the bits shifted out of the LHS being returned to the other
+ end. The primitive integer types all implement a [`rotate_right`](#method.rotate_right) function,
+ which may be what you want instead.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!((-128", stringify!($SelfT), ").wrapping_shr(7), -1);
+ assert_eq!((-128i16).wrapping_shr(64), -128);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_shr(self, rhs: u32) -> Self {
+                 // SAFETY: the masking by the bitsize of the type ensures that we do not shift
+                 // out of bounds
+                 unsafe {
+                     intrinsics::unchecked_shr(self, (rhs & ($BITS - 1)) as $SelfT)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) absolute value. Computes `self.abs()`, wrapping around at
+ the boundary of the type.
+ 
+ The only case where such wrapping can occur is when one takes the absolute value of the negative
+ minimal value for the type; this is a positive value that is too large to represent in the type. In
+ such a case, this function returns `MIN` itself.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_abs(), 100);
+ assert_eq!((-100", stringify!($SelfT), ").wrapping_abs(), 100);
+ assert_eq!(", stringify!($SelfT), "::MIN.wrapping_abs(), ", stringify!($SelfT),
+ "::MIN);
+ assert_eq!((-128i8).wrapping_abs() as u8, 128);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_abs", since = "1.13.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[allow(unused_attributes)]
+             #[inline]
+             pub const fn wrapping_abs(self) -> Self {
+                  if self.is_negative() {
+                      self.wrapping_neg()
+                  } else {
+                      self
+                  }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Computes the absolute value of `self` without any wrapping
+ or panicking.
+ 
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "#![feature(unsigned_abs)]
+ assert_eq!(100", stringify!($SelfT), ".unsigned_abs(), 100", stringify!($UnsignedT), ");
+ assert_eq!((-100", stringify!($SelfT), ").unsigned_abs(), 100", stringify!($UnsignedT), ");
+ assert_eq!((-128i8).unsigned_abs(), 128u8);",
+ $EndFeature, "
+ ```"),
+             #[unstable(feature = "unsigned_abs", issue = "74913")]
+             #[inline]
+             pub const fn unsigned_abs(self) -> $UnsignedT {
+                  self.wrapping_abs() as $UnsignedT
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) exponentiation. Computes `self.pow(exp)`,
+ wrapping around at the boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(3", stringify!($SelfT), ".wrapping_pow(4), 81);
+ assert_eq!(3i8.wrapping_pow(5), -13);
+ assert_eq!(3i8.wrapping_pow(6), -39);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_pow(self, mut exp: u32) -> Self {
+                 if exp == 0 {
+                     return 1;
+                 }
+                 let mut base = self;
+                 let mut acc: Self = 1;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         acc = acc.wrapping_mul(base);
+                     }
+                     exp /= 2;
+                     base = base.wrapping_mul(base);
+                 }
+ 
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+                 acc.wrapping_mul(base)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates `self` + `rhs`
+ 
+ Returns a tuple of the addition along with a boolean indicating whether an arithmetic overflow would
+ occur. If an overflow would have occurred then the wrapped value is returned.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".overflowing_add(2), (7, false));
+ assert_eq!(", stringify!($SelfT), "::MAX.overflowing_add(1), (", stringify!($SelfT),
+ "::MIN, true));", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_add(self, rhs: Self) -> (Self, bool) {
+                 let (a, b) = intrinsics::add_with_overflow(self as $ActualT, rhs as $ActualT);
+                 (a as Self, b)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates `self` - `rhs`
+ 
+ Returns a tuple of the subtraction along with a boolean indicating whether an arithmetic overflow
+ would occur. If an overflow would have occurred then the wrapped value is returned.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".overflowing_sub(2), (3, false));
+ assert_eq!(", stringify!($SelfT), "::MIN.overflowing_sub(1), (", stringify!($SelfT),
+ "::MAX, true));", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_sub(self, rhs: Self) -> (Self, bool) {
+                 let (a, b) = intrinsics::sub_with_overflow(self as $ActualT, rhs as $ActualT);
+                 (a as Self, b)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the multiplication of `self` and `rhs`.
+ 
+ Returns a tuple of the multiplication along with a boolean indicating whether an arithmetic overflow
+ would occur. If an overflow would have occurred then the wrapped value is returned.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(5", stringify!($SelfT), ".overflowing_mul(2), (10, false));
+ assert_eq!(1_000_000_000i32.overflowing_mul(10), (1410065408, true));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_mul(self, rhs: Self) -> (Self, bool) {
+                 let (a, b) = intrinsics::mul_with_overflow(self as $ActualT, rhs as $ActualT);
+                 (a as Self, b)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the divisor when `self` is divided by `rhs`.
+ 
+ Returns a tuple of the divisor along with a boolean indicating whether an arithmetic overflow would
+ occur. If an overflow would occur then self is returned.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".overflowing_div(2), (2, false));
+ assert_eq!(", stringify!($SelfT), "::MIN.overflowing_div(-1), (", stringify!($SelfT),
+ "::MIN, true));",
+ $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_unstable(feature = "const_overflowing_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_div(self, rhs: Self) -> (Self, bool) {
+                 if unlikely!(self == Self::MIN && rhs == -1) {
+                     (self, true)
+                 } else {
+                     (self / rhs, false)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the quotient of Euclidean division `self.div_euclid(rhs)`.
+ 
+ Returns a tuple of the divisor along with a boolean indicating whether an arithmetic overflow would
+ occur. If an overflow would occur then `self` is returned.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(5", stringify!($SelfT), ".overflowing_div_euclid(2), (2, false));
+ assert_eq!(", stringify!($SelfT), "::MIN.overflowing_div_euclid(-1), (", stringify!($SelfT),
+ "::MIN, true));
+ ```"),
+             #[inline]
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_div_euclid(self, rhs: Self) -> (Self, bool) {
+                 if unlikely!(self == Self::MIN && rhs == -1) {
+                     (self, true)
+                 } else {
+                     (self.div_euclid(rhs), false)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the remainder when `self` is divided by `rhs`.
+ 
+ Returns a tuple of the remainder after dividing along with a boolean indicating whether an
+ arithmetic overflow would occur. If an overflow would occur then 0 is returned.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".overflowing_rem(2), (1, false));
+ assert_eq!(", stringify!($SelfT), "::MIN.overflowing_rem(-1), (0, true));",
+ $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_unstable(feature = "const_overflowing_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_rem(self, rhs: Self) -> (Self, bool) {
+                 if unlikely!(self == Self::MIN && rhs == -1) {
+                     (0, true)
+                 } else {
+                     (self % rhs, false)
+                 }
+             }
+         }
+ 
+ 
+         doc_comment! {
+             concat!("Overflowing Euclidean remainder. Calculates `self.rem_euclid(rhs)`.
+ 
+ Returns a tuple of the remainder after dividing along with a boolean indicating whether an
+ arithmetic overflow would occur. If an overflow would occur then 0 is returned.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(5", stringify!($SelfT), ".overflowing_rem_euclid(2), (1, false));
+ assert_eq!(", stringify!($SelfT), "::MIN.overflowing_rem_euclid(-1), (0, true));
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_rem_euclid(self, rhs: Self) -> (Self, bool) {
+                 if unlikely!(self == Self::MIN && rhs == -1) {
+                     (0, true)
+                 } else {
+                     (self.rem_euclid(rhs), false)
+                 }
+             }
+         }
+ 
+ 
+         doc_comment! {
+             concat!("Negates self, overflowing if this is equal to the minimum value.
+ 
+ Returns a tuple of the negated version of self along with a boolean indicating whether an overflow
+ happened. If `self` is the minimum value (e.g., `i32::MIN` for values of type `i32`), then the
+ minimum value will be returned again and `true` will be returned for an overflow happening.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(2", stringify!($SelfT), ".overflowing_neg(), (-2, false));
+ assert_eq!(", stringify!($SelfT), "::MIN.overflowing_neg(), (", stringify!($SelfT),
+ "::MIN, true));", $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[allow(unused_attributes)]
+             pub const fn overflowing_neg(self) -> (Self, bool) {
+                 if unlikely!(self == Self::MIN) {
+                     (Self::MIN, true)
+                 } else {
+                     (-self, false)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts self left by `rhs` bits.
+ 
+ Returns a tuple of the shifted version of self along with a boolean indicating whether the shift
+ value was larger than or equal to the number of bits. If the shift value is too large, then value is
+ masked (N-1) where N is the number of bits, and this value is then used to perform the shift.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0x1", stringify!($SelfT),".overflowing_shl(4), (0x10, false));
+ assert_eq!(0x1i32.overflowing_shl(36), (0x10, true));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_shl(self, rhs: u32) -> (Self, bool) {
+                 (self.wrapping_shl(rhs), (rhs > ($BITS - 1)))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts self right by `rhs` bits.
+ 
+ Returns a tuple of the shifted version of self along with a boolean indicating whether the shift
+ value was larger than or equal to the number of bits. If the shift value is too large, then value is
+ masked (N-1) where N is the number of bits, and this value is then used to perform the shift.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0x10", stringify!($SelfT), ".overflowing_shr(4), (0x1, false));
+ assert_eq!(0x10i32.overflowing_shr(36), (0x1, true));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_shr(self, rhs: u32) -> (Self, bool) {
+                 (self.wrapping_shr(rhs), (rhs > ($BITS - 1)))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Computes the absolute value of `self`.
+ 
+ Returns a tuple of the absolute version of self along with a boolean indicating whether an overflow
+ happened. If self is the minimum value (e.g., ", stringify!($SelfT), "::MIN for values of type
+  ", stringify!($SelfT), "), then the minimum value will be returned again and true will be returned
+ for an overflow happening.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(10", stringify!($SelfT), ".overflowing_abs(), (10, false));
+ assert_eq!((-10", stringify!($SelfT), ").overflowing_abs(), (10, false));
+ assert_eq!((", stringify!($SelfT), "::MIN).overflowing_abs(), (", stringify!($SelfT),
+ "::MIN, true));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_abs", since = "1.13.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn overflowing_abs(self) -> (Self, bool) {
+                 (self.wrapping_abs(), self == Self::MIN)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Raises self to the power of `exp`, using exponentiation by squaring.
+ 
+ Returns a tuple of the exponentiation along with a bool indicating
+ whether an overflow happened.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(3", stringify!($SelfT), ".overflowing_pow(4), (81, false));
+ assert_eq!(3i8.overflowing_pow(5), (-13, true));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_pow(self, mut exp: u32) -> (Self, bool) {
+                 if exp == 0 {
+                     return (1,false);
+                 }
+                 let mut base = self;
+                 let mut acc: Self = 1;
+                 let mut overflown = false;
+                 // Scratch space for storing results of overflowing_mul.
+                 let mut r;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         r = acc.overflowing_mul(base);
+                         acc = r.0;
+                         overflown |= r.1;
+                     }
+                     exp /= 2;
+                     r = base.overflowing_mul(base);
+                     base = r.0;
+                     overflown |= r.1;
+                 }
+ 
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+                 r = acc.overflowing_mul(base);
+                 r.1 |= overflown;
+                 r
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Raises self to the power of `exp`, using exponentiation by squaring.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let x: ", stringify!($SelfT), " = 2; // or any other integer type
+ 
+ assert_eq!(x.pow(5), 32);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn pow(self, mut exp: u32) -> Self {
+                 if exp == 0 {
+                     return 1;
+                 }
+                 let mut base = self;
+                 let mut acc = 1;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         acc = acc * base;
+                     }
+                     exp /= 2;
+                     base = base * base;
+                 }
+ 
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+                 acc * base
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the quotient of Euclidean division of `self` by `rhs`.
+ 
+ This computes the integer `n` such that `self = n * rhs + self.rem_euclid(rhs)`,
+ with `0 <= self.rem_euclid(rhs) < rhs`.
+ 
+ In other words, the result is `self / rhs` rounded to the integer `n`
+ such that `self >= n * rhs`.
+ If `self > 0`, this is equal to round towards zero (the default in Rust);
+ if `self < 0`, this is equal to round towards +/- infinity.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0 or the division results in overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let a: ", stringify!($SelfT), " = 7; // or any other integer type
+ let b = 4;
+ 
+ assert_eq!(a.div_euclid(b), 1); // 7 >= 4 * 1
+ assert_eq!(a.div_euclid(-b), -1); // 7 >= -4 * -1
+ assert_eq!((-a).div_euclid(b), -2); // -7 >= 4 * -2
+ assert_eq!((-a).div_euclid(-b), 2); // -7 >= -4 * 2
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn div_euclid(self, rhs: Self) -> Self {
+                 let q = self / rhs;
+                 if self % rhs < 0 {
+                     return if rhs > 0 { q - 1 } else { q + 1 }
+                 }
+                 q
+             }
+         }
+ 
+ 
+         doc_comment! {
+             concat!("Calculates the least nonnegative remainder of `self (mod rhs)`.
+ 
+ This is done as if by the Euclidean division algorithm -- given
+ `r = self.rem_euclid(rhs)`, `self = rhs * self.div_euclid(rhs) + r`, and
+ `0 <= r < abs(rhs)`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0 or the division results in overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let a: ", stringify!($SelfT), " = 7; // or any other integer type
+ let b = 4;
+ 
+ assert_eq!(a.rem_euclid(b), 3);
+ assert_eq!((-a).rem_euclid(b), 1);
+ assert_eq!(a.rem_euclid(-b), 3);
+ assert_eq!((-a).rem_euclid(-b), 1);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn rem_euclid(self, rhs: Self) -> Self {
+                 let r = self % rhs;
+                 if r < 0 {
+                     if rhs < 0 {
+                         r - rhs
+                     } else {
+                         r + rhs
+                     }
+                 } else {
+                     r
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Computes the absolute value of `self`.
+ 
+ # Overflow behavior
+ 
+ The absolute value of `", stringify!($SelfT), "::MIN` cannot be represented as an
+ `", stringify!($SelfT), "`, and attempting to calculate it will cause an overflow. This means that
+ code in debug mode will trigger a panic on this case and optimized code will return `",
+ stringify!($SelfT), "::MIN` without a panic.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(10", stringify!($SelfT), ".abs(), 10);
+ assert_eq!((-10", stringify!($SelfT), ").abs(), 10);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[allow(unused_attributes)]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn abs(self) -> Self {
+                 // Note that the #[inline] above means that the overflow
+                 // semantics of the subtraction depend on the crate we're being
+                 // inlined into.
+                 if self.is_negative() {
+                     -self
+                 } else {
+                     self
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns a number representing sign of `self`.
+ 
+  - `0` if the number is zero
+  - `1` if the number is positive
+  - `-1` if the number is negative
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(10", stringify!($SelfT), ".signum(), 1);
+ assert_eq!(0", stringify!($SelfT), ".signum(), 0);
+ assert_eq!((-10", stringify!($SelfT), ").signum(), -1);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_sign", since = "1.47.0")]
+             #[inline]
+             pub const fn signum(self) -> Self {
+                 match self {
+                     n if n > 0 =>  1,
+                     0          =>  0,
+                     _          => -1,
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns `true` if `self` is positive and `false` if the number is zero or
+ negative.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert!(10", stringify!($SelfT), ".is_positive());
+ assert!(!(-10", stringify!($SelfT), ").is_positive());",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn is_positive(self) -> bool { self > 0 }
+         }
+ 
+         doc_comment! {
+             concat!("Returns `true` if `self` is negative and `false` if the number is zero or
+ positive.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert!((-10", stringify!($SelfT), ").is_negative());
+ assert!(!10", stringify!($SelfT), ".is_negative());",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_int_methods", since = "1.32.0")]
+             #[inline]
+             pub const fn is_negative(self) -> bool { self < 0 }
+         }
+ 
+         doc_comment! {
+             concat!("Return the memory representation of this integer as a byte array in
+ big-endian (network) byte order.
+ ",
+ $to_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let bytes = ", $swap_op, stringify!($SelfT), ".to_be_bytes();
+ assert_eq!(bytes, ", $be_bytes, ");
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn to_be_bytes(self) -> [u8; mem::size_of::<Self>()] {
+                 self.to_be().to_ne_bytes()
+             }
+         }
+ 
+ doc_comment! {
+             concat!("Return the memory representation of this integer as a byte array in
+ little-endian byte order.
+ ",
+ $to_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let bytes = ", $swap_op, stringify!($SelfT), ".to_le_bytes();
+ assert_eq!(bytes, ", $le_bytes, ");
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn to_le_bytes(self) -> [u8; mem::size_of::<Self>()] {
+                 self.to_le().to_ne_bytes()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("
+ Return the memory representation of this integer as a byte array in
+ native byte order.
+ 
+ As the target platform's native endianness is used, portable code
+ should use [`to_be_bytes`] or [`to_le_bytes`], as appropriate,
+ instead.
+ ",
+ $to_xe_bytes_doc,
+ "
+ [`to_be_bytes`]: #method.to_be_bytes
+ [`to_le_bytes`]: #method.to_le_bytes
+ 
+ # Examples
+ 
+ ```
+ let bytes = ", $swap_op, stringify!($SelfT), ".to_ne_bytes();
+ assert_eq!(
+     bytes,
+     if cfg!(target_endian = \"big\") {
+         ", $be_bytes, "
+     } else {
+         ", $le_bytes, "
+     }
+ );
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             // SAFETY: const sound because integers are plain old datatypes so we can always
+             // transmute them to arrays of bytes
+             #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_transmute))]
+             #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_transmute))]
+             #[inline]
+             pub const fn to_ne_bytes(self) -> [u8; mem::size_of::<Self>()] {
+                 // SAFETY: integers are plain old datatypes so we can always transmute them to
+                 // arrays of bytes
+                 unsafe { mem::transmute(self) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("
+ Return the memory representation of this integer as a byte array in
+ native byte order.
+ 
+ [`to_ne_bytes`] should be preferred over this whenever possible.
+ 
+ [`to_ne_bytes`]: #method.to_ne_bytes
+ ",
+ 
+ "
+ # Examples
+ 
+ ```
+ #![feature(num_as_ne_bytes)]
+ let num = ", $swap_op, stringify!($SelfT), ";
+ let bytes = num.as_ne_bytes();
+ assert_eq!(
+     bytes,
+     if cfg!(target_endian = \"big\") {
+         &", $be_bytes, "
+     } else {
+         &", $le_bytes, "
+     }
+ );
+ ```"),
+             #[unstable(feature = "num_as_ne_bytes", issue = "76976")]
+             #[inline]
+             pub fn as_ne_bytes(&self) -> &[u8; mem::size_of::<Self>()] {
+                 // SAFETY: integers are plain old datatypes so we can always transmute them to
+                 // arrays of bytes
+                 unsafe { &*(self as *const Self as *const _) }
+             }
+         }
+ 
+ doc_comment! {
+             concat!("Create an integer value from its representation as a byte array in
+ big endian.
+ ",
+ $from_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let value = ", stringify!($SelfT), "::from_be_bytes(", $be_bytes, ");
+ assert_eq!(value, ", $swap_op, ");
+ ```
+ 
+ When starting from a slice rather than an array, fallible conversion APIs can be used:
+ 
+ ```
+ use std::convert::TryInto;
+ 
+ fn read_be_", stringify!($SelfT), "(input: &mut &[u8]) -> ", stringify!($SelfT), " {
+     let (int_bytes, rest) = input.split_at(std::mem::size_of::<", stringify!($SelfT), ">());
+     *input = rest;
+     ", stringify!($SelfT), "::from_be_bytes(int_bytes.try_into().unwrap())
+ }
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn from_be_bytes(bytes: [u8; mem::size_of::<Self>()]) -> Self {
+                 Self::from_be(Self::from_ne_bytes(bytes))
+             }
+         }
+ 
+ doc_comment! {
+             concat!("
+ Create an integer value from its representation as a byte array in
+ little endian.
+ ",
+ $from_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let value = ", stringify!($SelfT), "::from_le_bytes(", $le_bytes, ");
+ assert_eq!(value, ", $swap_op, ");
+ ```
+ 
+ When starting from a slice rather than an array, fallible conversion APIs can be used:
+ 
+ ```
+ use std::convert::TryInto;
+ 
+ fn read_le_", stringify!($SelfT), "(input: &mut &[u8]) -> ", stringify!($SelfT), " {
+     let (int_bytes, rest) = input.split_at(std::mem::size_of::<", stringify!($SelfT), ">());
+     *input = rest;
+     ", stringify!($SelfT), "::from_le_bytes(int_bytes.try_into().unwrap())
+ }
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn from_le_bytes(bytes: [u8; mem::size_of::<Self>()]) -> Self {
+                 Self::from_le(Self::from_ne_bytes(bytes))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Create an integer value from its memory representation as a byte
+ array in native endianness.
+ 
+ As the target platform's native endianness is used, portable code
+ likely wants to use [`from_be_bytes`] or [`from_le_bytes`], as
+ appropriate instead.
+ 
+ [`from_be_bytes`]: #method.from_be_bytes
+ [`from_le_bytes`]: #method.from_le_bytes
+ ",
+ $from_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let value = ", stringify!($SelfT), "::from_ne_bytes(if cfg!(target_endian = \"big\") {
+     ", $be_bytes, "
+ } else {
+     ", $le_bytes, "
+ });
+ assert_eq!(value, ", $swap_op, ");
+ ```
+ 
+ When starting from a slice rather than an array, fallible conversion APIs can be used:
+ 
+ ```
+ use std::convert::TryInto;
+ 
+ fn read_ne_", stringify!($SelfT), "(input: &mut &[u8]) -> ", stringify!($SelfT), " {
+     let (int_bytes, rest) = input.split_at(std::mem::size_of::<", stringify!($SelfT), ">());
+     *input = rest;
+     ", stringify!($SelfT), "::from_ne_bytes(int_bytes.try_into().unwrap())
+ }
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             // SAFETY: const sound because integers are plain old datatypes so we can always
+             // transmute to them
+             #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_transmute))]
+             #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_transmute))]
+             #[inline]
+             pub const fn from_ne_bytes(bytes: [u8; mem::size_of::<Self>()]) -> Self {
+                 // SAFETY: integers are plain old datatypes so we can always transmute to them
+                 unsafe { mem::transmute(bytes) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("**This method is soft-deprecated.**
+ 
+ Although using it won’t cause a compilation warning,
+ new code should use [`", stringify!($SelfT), "::MIN", "`](#associatedconstant.MIN) instead.
+ 
+ Returns the smallest value that can be represented by this integer type."),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[inline(always)]
+             #[rustc_promotable]
+             #[rustc_const_stable(feature = "const_min_value", since = "1.32.0")]
+             pub const fn min_value() -> Self {
+                 Self::MIN
+             }
+         }
+ 
+         doc_comment! {
+             concat!("**This method is soft-deprecated.**
+ 
+ Although using it won’t cause a compilation warning,
+ new code should use [`", stringify!($SelfT), "::MAX", "`](#associatedconstant.MAX) instead.
+ 
+ Returns the largest value that can be represented by this integer type."),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[inline(always)]
+             #[rustc_promotable]
+             #[rustc_const_stable(feature = "const_max_value", since = "1.32.0")]
+             pub const fn max_value() -> Self {
+                 Self::MAX
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,881 ----
+ //! Numeric traits and functions for the built-in numeric types.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::intrinsics;
+ use crate::mem;
+ use crate::str::FromStr;
+ 
+ // Used because the `?` operator is not allowed in a const context.
+ macro_rules! try_opt {
+     ($e:expr) => {
+         match $e {
+             Some(x) => x,
+             None => return None,
+         }
+     };
+ }
+ 
+ #[allow_internal_unstable(const_likely)]
+ macro_rules! unlikely {
+     ($e: expr) => {
+         intrinsics::unlikely($e)
+     };
+ }
+ 
+ macro_rules! doc_comment {
+     ($x:expr, $($tt:tt)*) => {
+         #[doc = $x]
+         $($tt)*
+     };
+ }
+ 
+ // All these modules are technically private and only exposed for coretests:
+ pub mod bignum;
+ pub mod dec2flt;
+ pub mod diy_float;
+ pub mod flt2dec;
+ 
+ #[macro_use]
+ mod int_macros; // import int_impl!
+ #[macro_use]
+ mod uint_macros; // import uint_impl!
+ 
+ mod error;
+ mod nonzero;
+ mod wrapping;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use wrapping::Wrapping;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use dec2flt::ParseFloatError;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use error::ParseIntError;
+ 
+ #[stable(feature = "nonzero", since = "1.28.0")]
+ pub use nonzero::{NonZeroU128, NonZeroU16, NonZeroU32, NonZeroU64, NonZeroU8, NonZeroUsize};
+ 
+ #[stable(feature = "signed_nonzero", since = "1.34.0")]
+ pub use nonzero::{NonZeroI128, NonZeroI16, NonZeroI32, NonZeroI64, NonZeroI8, NonZeroIsize};
+ 
+ #[stable(feature = "try_from", since = "1.34.0")]
+ pub use error::TryFromIntError;
+ 
+ #[unstable(
+     feature = "int_error_matching",
+     reason = "it can be useful to match errors when making error messages \
+               for integer parsing",
+     issue = "22639"
+ )]
+ pub use error::IntErrorKind;
+ 
+ macro_rules! usize_isize_to_xe_bytes_doc {
+     () => {
+         "
+ 
+ **Note**: This function returns an array of length 2, 4 or 8 bytes
+ depending on the target pointer size.
+ 
+ "
+     };
+ }
+ 
+ macro_rules! usize_isize_from_xe_bytes_doc {
+     () => {
+         "
+ 
+ **Note**: This function takes an array of length 2, 4 or 8 bytes
+ depending on the target pointer size.
+ 
+ "
+     };
+ }
+ 
+ #[lang = "i8"]
+ impl i8 {
+     int_impl! { i8, i8, u8, 8, -128, 127, "", "", 2, "-0x7e", "0xa", "0x12", "0x12", "0x48",
+     "[0x12]", "[0x12]", "", "" }
+ }
+ 
+ #[lang = "i16"]
+ impl i16 {
+     int_impl! { i16, i16, u16, 16, -32768, 32767, "", "", 4, "-0x5ffd", "0x3a", "0x1234", "0x3412",
+     "0x2c48", "[0x34, 0x12]", "[0x12, 0x34]", "", "" }
+ }
+ 
+ #[lang = "i32"]
+ impl i32 {
+     int_impl! { i32, i32, u32, 32, -2147483648, 2147483647, "", "", 8, "0x10000b3", "0xb301",
+     "0x12345678", "0x78563412", "0x1e6a2c48", "[0x78, 0x56, 0x34, 0x12]",
+     "[0x12, 0x34, 0x56, 0x78]", "", "" }
+ }
+ 
+ #[lang = "i64"]
+ impl i64 {
+     int_impl! { i64, i64, u64, 64, -9223372036854775808, 9223372036854775807, "", "", 12,
+     "0xaa00000000006e1", "0x6e10aa", "0x1234567890123456", "0x5634129078563412",
+     "0x6a2c48091e6a2c48", "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]",
+     "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]", "", "" }
+ }
+ 
+ #[lang = "i128"]
+ impl i128 {
+     int_impl! { i128, i128, u128, 128, -170141183460469231731687303715884105728,
+     170141183460469231731687303715884105727, "", "", 16,
+     "0x13f40000000000000000000000004f76", "0x4f7613f4", "0x12345678901234567890123456789012",
+     "0x12907856341290785634129078563412", "0x48091e6a2c48091e6a2c48091e6a2c48",
+     "[0x12, 0x90, 0x78, 0x56, 0x34, 0x12, 0x90, 0x78, \
+       0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]",
+     "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56, \
+       0x78, 0x90, 0x12, 0x34, 0x56, 0x78, 0x90, 0x12]", "", "" }
+ }
+ 
+ #[cfg(target_pointer_width = "16")]
+ #[lang = "isize"]
+ impl isize {
+     int_impl! { isize, i16, usize, 16, -32768, 32767, "", "", 4, "-0x5ffd", "0x3a", "0x1234",
+     "0x3412", "0x2c48", "[0x34, 0x12]", "[0x12, 0x34]",
+     usize_isize_to_xe_bytes_doc!(), usize_isize_from_xe_bytes_doc!() }
+ }
+ 
+ #[cfg(target_pointer_width = "32")]
+ #[lang = "isize"]
+ impl isize {
+     int_impl! { isize, i32, usize, 32, -2147483648, 2147483647, "", "", 8, "0x10000b3", "0xb301",
+     "0x12345678", "0x78563412", "0x1e6a2c48", "[0x78, 0x56, 0x34, 0x12]",
+     "[0x12, 0x34, 0x56, 0x78]",
+     usize_isize_to_xe_bytes_doc!(), usize_isize_from_xe_bytes_doc!() }
+ }
+ 
+ #[cfg(target_pointer_width = "64")]
+ #[lang = "isize"]
+ impl isize {
+     int_impl! { isize, i64, usize, 64, -9223372036854775808, 9223372036854775807, "", "",
+     12, "0xaa00000000006e1", "0x6e10aa",  "0x1234567890123456", "0x5634129078563412",
+      "0x6a2c48091e6a2c48", "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]",
+      "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]",
+      usize_isize_to_xe_bytes_doc!(), usize_isize_from_xe_bytes_doc!() }
+ }
+ 
+ #[lang = "u8"]
+ impl u8 {
+     uint_impl! { u8, u8, 8, 255, "", "", 2, "0x82", "0xa", "0x12", "0x12", "0x48", "[0x12]",
+     "[0x12]", "", "" }
+ 
+     /// Checks if the value is within the ASCII range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let ascii = 97u8;
+     /// let non_ascii = 150u8;
+     ///
+     /// assert!(ascii.is_ascii());
+     /// assert!(!non_ascii.is_ascii());
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[rustc_const_stable(feature = "const_ascii_methods_on_intrinsics", since = "1.43.0")]
+     #[inline]
+     pub const fn is_ascii(&self) -> bool {
+         *self & 128 == 0
+     }
+ 
+     /// Makes a copy of the value in its ASCII upper case equivalent.
+     ///
+     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To uppercase the value in-place, use [`make_ascii_uppercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let lowercase_a = 97u8;
+     ///
+     /// assert_eq!(65, lowercase_a.to_ascii_uppercase());
+     /// ```
+     ///
+     /// [`make_ascii_uppercase`]: #method.make_ascii_uppercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn to_ascii_uppercase(&self) -> u8 {
+         // Unset the fifth bit if this is a lowercase letter
+         *self & !((self.is_ascii_lowercase() as u8) << 5)
+     }
+ 
+     /// Makes a copy of the value in its ASCII lower case equivalent.
+     ///
+     /// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To lowercase the value in-place, use [`make_ascii_lowercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = 65u8;
+     ///
+     /// assert_eq!(97, uppercase_a.to_ascii_lowercase());
+     /// ```
+     ///
+     /// [`make_ascii_lowercase`]: #method.make_ascii_lowercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn to_ascii_lowercase(&self) -> u8 {
+         // Set the fifth bit if this is an uppercase letter
+         *self | ((self.is_ascii_uppercase() as u8) << 5)
+     }
+ 
+     /// Checks that two values are an ASCII case-insensitive match.
+     ///
+     /// This is equivalent to `to_ascii_lowercase(a) == to_ascii_lowercase(b)`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let lowercase_a = 97u8;
+     /// let uppercase_a = 65u8;
+     ///
+     /// assert!(lowercase_a.eq_ignore_ascii_case(&uppercase_a));
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn eq_ignore_ascii_case(&self, other: &u8) -> bool {
+         self.to_ascii_lowercase() == other.to_ascii_lowercase()
+     }
+ 
+     /// Converts this value to its ASCII upper case equivalent in-place.
+     ///
+     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new uppercased value without modifying the existing one, use
+     /// [`to_ascii_uppercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut byte = b'a';
+     ///
+     /// byte.make_ascii_uppercase();
+     ///
+     /// assert_eq!(b'A', byte);
+     /// ```
+     ///
+     /// [`to_ascii_uppercase`]: #method.to_ascii_uppercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_uppercase(&mut self) {
+         *self = self.to_ascii_uppercase();
+     }
+ 
+     /// Converts this value to its ASCII lower case equivalent in-place.
+     ///
+     /// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new lowercased value without modifying the existing one, use
+     /// [`to_ascii_lowercase`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut byte = b'A';
+     ///
+     /// byte.make_ascii_lowercase();
+     ///
+     /// assert_eq!(b'a', byte);
+     /// ```
+     ///
+     /// [`to_ascii_lowercase`]: #method.to_ascii_lowercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_lowercase(&mut self) {
+         *self = self.to_ascii_lowercase();
+     }
+ 
+     /// Checks if the value is an ASCII alphabetic character:
+     ///
+     /// - U+0041 'A' ..= U+005A 'Z', or
+     /// - U+0061 'a' ..= U+007A 'z'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(uppercase_a.is_ascii_alphabetic());
+     /// assert!(uppercase_g.is_ascii_alphabetic());
+     /// assert!(a.is_ascii_alphabetic());
+     /// assert!(g.is_ascii_alphabetic());
+     /// assert!(!zero.is_ascii_alphabetic());
+     /// assert!(!percent.is_ascii_alphabetic());
+     /// assert!(!space.is_ascii_alphabetic());
+     /// assert!(!lf.is_ascii_alphabetic());
+     /// assert!(!esc.is_ascii_alphabetic());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_alphabetic(&self) -> bool {
+         matches!(*self, b'A'..=b'Z' | b'a'..=b'z')
+     }
+ 
+     /// Checks if the value is an ASCII uppercase character:
+     /// U+0041 'A' ..= U+005A 'Z'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(uppercase_a.is_ascii_uppercase());
+     /// assert!(uppercase_g.is_ascii_uppercase());
+     /// assert!(!a.is_ascii_uppercase());
+     /// assert!(!g.is_ascii_uppercase());
+     /// assert!(!zero.is_ascii_uppercase());
+     /// assert!(!percent.is_ascii_uppercase());
+     /// assert!(!space.is_ascii_uppercase());
+     /// assert!(!lf.is_ascii_uppercase());
+     /// assert!(!esc.is_ascii_uppercase());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_uppercase(&self) -> bool {
+         matches!(*self, b'A'..=b'Z')
+     }
+ 
+     /// Checks if the value is an ASCII lowercase character:
+     /// U+0061 'a' ..= U+007A 'z'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(!uppercase_a.is_ascii_lowercase());
+     /// assert!(!uppercase_g.is_ascii_lowercase());
+     /// assert!(a.is_ascii_lowercase());
+     /// assert!(g.is_ascii_lowercase());
+     /// assert!(!zero.is_ascii_lowercase());
+     /// assert!(!percent.is_ascii_lowercase());
+     /// assert!(!space.is_ascii_lowercase());
+     /// assert!(!lf.is_ascii_lowercase());
+     /// assert!(!esc.is_ascii_lowercase());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_lowercase(&self) -> bool {
+         matches!(*self, b'a'..=b'z')
+     }
+ 
+     /// Checks if the value is an ASCII alphanumeric character:
+     ///
+     /// - U+0041 'A' ..= U+005A 'Z', or
+     /// - U+0061 'a' ..= U+007A 'z', or
+     /// - U+0030 '0' ..= U+0039 '9'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(uppercase_a.is_ascii_alphanumeric());
+     /// assert!(uppercase_g.is_ascii_alphanumeric());
+     /// assert!(a.is_ascii_alphanumeric());
+     /// assert!(g.is_ascii_alphanumeric());
+     /// assert!(zero.is_ascii_alphanumeric());
+     /// assert!(!percent.is_ascii_alphanumeric());
+     /// assert!(!space.is_ascii_alphanumeric());
+     /// assert!(!lf.is_ascii_alphanumeric());
+     /// assert!(!esc.is_ascii_alphanumeric());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_alphanumeric(&self) -> bool {
+         matches!(*self, b'0'..=b'9' | b'A'..=b'Z' | b'a'..=b'z')
+     }
+ 
+     /// Checks if the value is an ASCII decimal digit:
+     /// U+0030 '0' ..= U+0039 '9'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(!uppercase_a.is_ascii_digit());
+     /// assert!(!uppercase_g.is_ascii_digit());
+     /// assert!(!a.is_ascii_digit());
+     /// assert!(!g.is_ascii_digit());
+     /// assert!(zero.is_ascii_digit());
+     /// assert!(!percent.is_ascii_digit());
+     /// assert!(!space.is_ascii_digit());
+     /// assert!(!lf.is_ascii_digit());
+     /// assert!(!esc.is_ascii_digit());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_digit(&self) -> bool {
+         matches!(*self, b'0'..=b'9')
+     }
+ 
+     /// Checks if the value is an ASCII hexadecimal digit:
+     ///
+     /// - U+0030 '0' ..= U+0039 '9', or
+     /// - U+0041 'A' ..= U+0046 'F', or
+     /// - U+0061 'a' ..= U+0066 'f'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(uppercase_a.is_ascii_hexdigit());
+     /// assert!(!uppercase_g.is_ascii_hexdigit());
+     /// assert!(a.is_ascii_hexdigit());
+     /// assert!(!g.is_ascii_hexdigit());
+     /// assert!(zero.is_ascii_hexdigit());
+     /// assert!(!percent.is_ascii_hexdigit());
+     /// assert!(!space.is_ascii_hexdigit());
+     /// assert!(!lf.is_ascii_hexdigit());
+     /// assert!(!esc.is_ascii_hexdigit());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_hexdigit(&self) -> bool {
+         matches!(*self, b'0'..=b'9' | b'A'..=b'F' | b'a'..=b'f')
+     }
+ 
+     /// Checks if the value is an ASCII punctuation character:
+     ///
+     /// - U+0021 ..= U+002F `! " # $ % & ' ( ) * + , - . /`, or
+     /// - U+003A ..= U+0040 `: ; < = > ? @`, or
+     /// - U+005B ..= U+0060 ``[ \ ] ^ _ ` ``, or
+     /// - U+007B ..= U+007E `{ | } ~`
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(!uppercase_a.is_ascii_punctuation());
+     /// assert!(!uppercase_g.is_ascii_punctuation());
+     /// assert!(!a.is_ascii_punctuation());
+     /// assert!(!g.is_ascii_punctuation());
+     /// assert!(!zero.is_ascii_punctuation());
+     /// assert!(percent.is_ascii_punctuation());
+     /// assert!(!space.is_ascii_punctuation());
+     /// assert!(!lf.is_ascii_punctuation());
+     /// assert!(!esc.is_ascii_punctuation());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_punctuation(&self) -> bool {
+         matches!(*self, b'!'..=b'/' | b':'..=b'@' | b'['..=b'`' | b'{'..=b'~')
+     }
+ 
+     /// Checks if the value is an ASCII graphic character:
+     /// U+0021 '!' ..= U+007E '~'.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(uppercase_a.is_ascii_graphic());
+     /// assert!(uppercase_g.is_ascii_graphic());
+     /// assert!(a.is_ascii_graphic());
+     /// assert!(g.is_ascii_graphic());
+     /// assert!(zero.is_ascii_graphic());
+     /// assert!(percent.is_ascii_graphic());
+     /// assert!(!space.is_ascii_graphic());
+     /// assert!(!lf.is_ascii_graphic());
+     /// assert!(!esc.is_ascii_graphic());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_graphic(&self) -> bool {
+         matches!(*self, b'!'..=b'~')
+     }
+ 
+     /// Checks if the value is an ASCII whitespace character:
+     /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED,
+     /// U+000C FORM FEED, or U+000D CARRIAGE RETURN.
+     ///
+     /// Rust uses the WhatWG Infra Standard's [definition of ASCII
+     /// whitespace][infra-aw]. There are several other definitions in
+     /// wide use. For instance, [the POSIX locale][pct] includes
+     /// U+000B VERTICAL TAB as well as all the above characters,
+     /// but—from the very same specification—[the default rule for
+     /// "field splitting" in the Bourne shell][bfs] considers *only*
+     /// SPACE, HORIZONTAL TAB, and LINE FEED as whitespace.
+     ///
+     /// If you are writing a program that will process an existing
+     /// file format, check what that format's definition of whitespace is
+     /// before using this function.
+     ///
+     /// [infra-aw]: https://infra.spec.whatwg.org/#ascii-whitespace
+     /// [pct]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap07.html#tag_07_03_01
+     /// [bfs]: http://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#tag_18_06_05
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(!uppercase_a.is_ascii_whitespace());
+     /// assert!(!uppercase_g.is_ascii_whitespace());
+     /// assert!(!a.is_ascii_whitespace());
+     /// assert!(!g.is_ascii_whitespace());
+     /// assert!(!zero.is_ascii_whitespace());
+     /// assert!(!percent.is_ascii_whitespace());
+     /// assert!(space.is_ascii_whitespace());
+     /// assert!(lf.is_ascii_whitespace());
+     /// assert!(!esc.is_ascii_whitespace());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_whitespace(&self) -> bool {
+         matches!(*self, b'\t' | b'\n' | b'\x0C' | b'\r' | b' ')
+     }
+ 
+     /// Checks if the value is an ASCII control character:
+     /// U+0000 NUL ..= U+001F UNIT SEPARATOR, or U+007F DELETE.
+     /// Note that most ASCII whitespace characters are control
+     /// characters, but SPACE is not.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let uppercase_a = b'A';
+     /// let uppercase_g = b'G';
+     /// let a = b'a';
+     /// let g = b'g';
+     /// let zero = b'0';
+     /// let percent = b'%';
+     /// let space = b' ';
+     /// let lf = b'\n';
+     /// let esc = 0x1b_u8;
+     ///
+     /// assert!(!uppercase_a.is_ascii_control());
+     /// assert!(!uppercase_g.is_ascii_control());
+     /// assert!(!a.is_ascii_control());
+     /// assert!(!g.is_ascii_control());
+     /// assert!(!zero.is_ascii_control());
+     /// assert!(!percent.is_ascii_control());
+     /// assert!(!space.is_ascii_control());
+     /// assert!(lf.is_ascii_control());
+     /// assert!(esc.is_ascii_control());
+     /// ```
+     #[stable(feature = "ascii_ctype_on_intrinsics", since = "1.24.0")]
+     #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")]
+     #[inline]
+     pub const fn is_ascii_control(&self) -> bool {
+         matches!(*self, b'\0'..=b'\x1F' | b'\x7F')
+     }
+ }
+ 
+ #[lang = "u16"]
+ impl u16 {
+     uint_impl! { u16, u16, 16, 65535, "", "", 4, "0xa003", "0x3a", "0x1234", "0x3412", "0x2c48",
+     "[0x34, 0x12]", "[0x12, 0x34]", "", "" }
+ }
+ 
+ #[lang = "u32"]
+ impl u32 {
+     uint_impl! { u32, u32, 32, 4294967295, "", "", 8, "0x10000b3", "0xb301", "0x12345678",
+     "0x78563412", "0x1e6a2c48", "[0x78, 0x56, 0x34, 0x12]", "[0x12, 0x34, 0x56, 0x78]", "", "" }
+ }
+ 
+ #[lang = "u64"]
+ impl u64 {
+     uint_impl! { u64, u64, 64, 18446744073709551615, "", "", 12, "0xaa00000000006e1", "0x6e10aa",
+     "0x1234567890123456", "0x5634129078563412", "0x6a2c48091e6a2c48",
+     "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]",
+     "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]",
+     "", ""}
+ }
+ 
+ #[lang = "u128"]
+ impl u128 {
+     uint_impl! { u128, u128, 128, 340282366920938463463374607431768211455, "", "", 16,
+     "0x13f40000000000000000000000004f76", "0x4f7613f4", "0x12345678901234567890123456789012",
+     "0x12907856341290785634129078563412", "0x48091e6a2c48091e6a2c48091e6a2c48",
+     "[0x12, 0x90, 0x78, 0x56, 0x34, 0x12, 0x90, 0x78, \
+       0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]",
+     "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56, \
+       0x78, 0x90, 0x12, 0x34, 0x56, 0x78, 0x90, 0x12]",
+      "", ""}
+ }
+ 
+ #[cfg(target_pointer_width = "16")]
+ #[lang = "usize"]
+ impl usize {
+     uint_impl! { usize, u16, 16, 65535, "", "", 4, "0xa003", "0x3a", "0x1234", "0x3412", "0x2c48",
+     "[0x34, 0x12]", "[0x12, 0x34]",
+     usize_isize_to_xe_bytes_doc!(), usize_isize_from_xe_bytes_doc!() }
+ }
+ #[cfg(target_pointer_width = "32")]
+ #[lang = "usize"]
+ impl usize {
+     uint_impl! { usize, u32, 32, 4294967295, "", "", 8, "0x10000b3", "0xb301", "0x12345678",
+     "0x78563412", "0x1e6a2c48", "[0x78, 0x56, 0x34, 0x12]", "[0x12, 0x34, 0x56, 0x78]",
+     usize_isize_to_xe_bytes_doc!(), usize_isize_from_xe_bytes_doc!() }
+ }
+ 
+ #[cfg(target_pointer_width = "64")]
+ #[lang = "usize"]
+ impl usize {
+     uint_impl! { usize, u64, 64, 18446744073709551615, "", "", 12, "0xaa00000000006e1", "0x6e10aa",
+     "0x1234567890123456", "0x5634129078563412", "0x6a2c48091e6a2c48",
+     "[0x56, 0x34, 0x12, 0x90, 0x78, 0x56, 0x34, 0x12]",
+      "[0x12, 0x34, 0x56, 0x78, 0x90, 0x12, 0x34, 0x56]",
+     usize_isize_to_xe_bytes_doc!(), usize_isize_from_xe_bytes_doc!() }
+ }
+ 
+ /// A classification of floating point numbers.
+ ///
+ /// This `enum` is used as the return type for [`f32::classify`] and [`f64::classify`]. See
+ /// their documentation for more.
+ ///
+ /// [`f32::classify`]: ../../std/primitive.f32.html#method.classify
+ /// [`f64::classify`]: ../../std/primitive.f64.html#method.classify
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::num::FpCategory;
+ ///
+ /// let num = 12.4_f32;
+ /// let inf = f32::INFINITY;
+ /// let zero = 0f32;
+ /// let sub: f32 = 1.1754942e-38;
+ /// let nan = f32::NAN;
+ ///
+ /// assert_eq!(num.classify(), FpCategory::Normal);
+ /// assert_eq!(inf.classify(), FpCategory::Infinite);
+ /// assert_eq!(zero.classify(), FpCategory::Zero);
+ /// assert_eq!(nan.classify(), FpCategory::Nan);
+ /// assert_eq!(sub.classify(), FpCategory::Subnormal);
+ /// ```
+ #[derive(Copy, Clone, PartialEq, Eq, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub enum FpCategory {
+     /// "Not a Number", often obtained by dividing by zero.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Nan,
+ 
+     /// Positive or negative infinity.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Infinite,
+ 
+     /// Positive or negative zero.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Zero,
+ 
+     /// De-normalized floating point representation (less precise than `Normal`).
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Subnormal,
+ 
+     /// A regular floating point number.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Normal,
+ }
+ 
+ #[doc(hidden)]
+ trait FromStrRadixHelper: PartialOrd + Copy {
+     fn min_value() -> Self;
+     fn max_value() -> Self;
+     fn from_u32(u: u32) -> Self;
+     fn checked_mul(&self, other: u32) -> Option<Self>;
+     fn checked_sub(&self, other: u32) -> Option<Self>;
+     fn checked_add(&self, other: u32) -> Option<Self>;
+ }
+ 
+ macro_rules! from_str_radix_int_impl {
+     ($($t:ty)*) => {$(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl FromStr for $t {
+             type Err = ParseIntError;
+             fn from_str(src: &str) -> Result<Self, ParseIntError> {
+                 from_str_radix(src, 10)
+             }
+         }
+     )*}
+ }
+ from_str_radix_int_impl! { isize i8 i16 i32 i64 i128 usize u8 u16 u32 u64 u128 }
+ 
+ macro_rules! doit {
+     ($($t:ty)*) => ($(impl FromStrRadixHelper for $t {
+         #[inline]
+         fn min_value() -> Self { Self::MIN }
+         #[inline]
+         fn max_value() -> Self { Self::MAX }
+         #[inline]
+         fn from_u32(u: u32) -> Self { u as Self }
+         #[inline]
+         fn checked_mul(&self, other: u32) -> Option<Self> {
+             Self::checked_mul(*self, other as Self)
+         }
+         #[inline]
+         fn checked_sub(&self, other: u32) -> Option<Self> {
+             Self::checked_sub(*self, other as Self)
+         }
+         #[inline]
+         fn checked_add(&self, other: u32) -> Option<Self> {
+             Self::checked_add(*self, other as Self)
+         }
+     })*)
+ }
+ doit! { i8 i16 i32 i64 i128 isize u8 u16 u32 u64 u128 usize }
+ 
+ fn from_str_radix<T: FromStrRadixHelper>(src: &str, radix: u32) -> Result<T, ParseIntError> {
+     use self::IntErrorKind::*;
+     use self::ParseIntError as PIE;
+ 
+     assert!(
+         radix >= 2 && radix <= 36,
+         "from_str_radix_int: must lie in the range `[2, 36]` - found {}",
+         radix
+     );
+ 
+     if src.is_empty() {
+         return Err(PIE { kind: Empty });
+     }
+ 
+     let is_signed_ty = T::from_u32(0) > T::min_value();
+ 
+     // all valid digits are ascii, so we will just iterate over the utf8 bytes
+     // and cast them to chars. .to_digit() will safely return None for anything
+     // other than a valid ascii digit for the given radix, including the first-byte
+     // of multi-byte sequences
+     let src = src.as_bytes();
+ 
+     let (is_positive, digits) = match src[0] {
+         b'+' | b'-' if src[1..].is_empty() => {
+             return Err(PIE { kind: InvalidDigit });
+         }
+         b'+' => (true, &src[1..]),
+         b'-' if is_signed_ty => (false, &src[1..]),
+         _ => (true, src),
+     };
+ 
+     let mut result = T::from_u32(0);
+     if is_positive {
+         // The number is positive
+         for &c in digits {
+             let x = match (c as char).to_digit(radix) {
+                 Some(x) => x,
+                 None => return Err(PIE { kind: InvalidDigit }),
+             };
+             result = match result.checked_mul(radix) {
+                 Some(result) => result,
+                 None => return Err(PIE { kind: PosOverflow }),
+             };
+             result = match result.checked_add(x) {
+                 Some(result) => result,
+                 None => return Err(PIE { kind: PosOverflow }),
+             };
+         }
+     } else {
+         // The number is negative
+         for &c in digits {
+             let x = match (c as char).to_digit(radix) {
+                 Some(x) => x,
+                 None => return Err(PIE { kind: InvalidDigit }),
+             };
+             result = match result.checked_mul(radix) {
+                 Some(result) => result,
+                 None => return Err(PIE { kind: NegOverflow }),
+             };
+             result = match result.checked_sub(x) {
+                 Some(result) => result,
+                 None => return Err(PIE { kind: NegOverflow }),
+             };
+         }
+     }
+     Ok(result)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/nonzero.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/nonzero.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/nonzero.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/nonzero.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,191 ----
+ //! Definitions of integer that is known not to equal zero.
+ 
+ use crate::fmt;
+ use crate::ops::{BitOr, BitOrAssign};
+ use crate::str::FromStr;
+ 
+ use super::from_str_radix;
+ use super::{IntErrorKind, ParseIntError};
+ 
+ macro_rules! doc_comment {
+     ($x:expr, $($tt:tt)*) => {
+         #[doc = $x]
+         $($tt)*
+     };
+ }
+ 
+ macro_rules! impl_nonzero_fmt {
+     ( #[$stability: meta] ( $( $Trait: ident ),+ ) for $Ty: ident ) => {
+         $(
+             #[$stability]
+             impl fmt::$Trait for $Ty {
+                 #[inline]
+                 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                     self.get().fmt(f)
+                 }
+             }
+         )+
+     }
+ }
+ 
+ macro_rules! nonzero_integers {
+     ( $( #[$stability: meta] $Ty: ident($Int: ty); )+ ) => {
+         $(
+             doc_comment! {
+                 concat!("An integer that is known not to equal zero.
+ 
+ This enables some memory layout optimization.
+ For example, `Option<", stringify!($Ty), ">` is the same size as `", stringify!($Int), "`:
+ 
+ ```rust
+ use std::mem::size_of;
+ assert_eq!(size_of::<Option<core::num::", stringify!($Ty), ">>(), size_of::<", stringify!($Int),
+ ">());
+ ```"),
+                 #[$stability]
+                 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
+                 #[repr(transparent)]
+                 #[rustc_layout_scalar_valid_range_start(1)]
+                 #[rustc_nonnull_optimization_guaranteed]
+                 pub struct $Ty($Int);
+             }
+ 
+             impl $Ty {
+                 /// Creates a non-zero without checking the value.
+                 ///
+                 /// # Safety
+                 ///
+                 /// The value must not be zero.
+                 #[$stability]
+                 #[rustc_const_stable(feature = "nonzero", since = "1.34.0")]
+                 #[inline]
+                 pub const unsafe fn new_unchecked(n: $Int) -> Self {
+                     // SAFETY: this is guaranteed to be safe by the caller.
+                     unsafe { Self(n) }
+                 }
+ 
+                 /// Creates a non-zero if the given value is not zero.
+                 #[$stability]
+                 #[rustc_const_stable(feature = "const_nonzero_int_methods", since = "1.47.0")]
+                 #[inline]
+                 pub const fn new(n: $Int) -> Option<Self> {
+                     if n != 0 {
+                         // SAFETY: we just checked that there's no `0`
+                         Some(unsafe { Self(n) })
+                     } else {
+                         None
+                     }
+                 }
+ 
+                 /// Returns the value as a primitive type.
+                 #[$stability]
+                 #[inline]
+                 #[rustc_const_stable(feature = "nonzero", since = "1.34.0")]
+                 pub const fn get(self) -> $Int {
+                     self.0
+                 }
+ 
+             }
+ 
+             #[stable(feature = "from_nonzero", since = "1.31.0")]
+             impl From<$Ty> for $Int {
+                 doc_comment! {
+                     concat!(
+ "Converts a `", stringify!($Ty), "` into an `", stringify!($Int), "`"),
+                     #[inline]
+                     fn from(nonzero: $Ty) -> Self {
+                         nonzero.0
+                     }
+                 }
+             }
+ 
+             #[stable(feature = "nonzero_bitor", since = "1.45.0")]
+             impl BitOr for $Ty {
+                 type Output = Self;
+                 #[inline]
+                 fn bitor(self, rhs: Self) -> Self::Output {
+                     // SAFETY: since `self` and `rhs` are both nonzero, the
+                     // result of the bitwise-or will be nonzero.
+                     unsafe { $Ty::new_unchecked(self.get() | rhs.get()) }
+                 }
+             }
+ 
+             #[stable(feature = "nonzero_bitor", since = "1.45.0")]
+             impl BitOr<$Int> for $Ty {
+                 type Output = Self;
+                 #[inline]
+                 fn bitor(self, rhs: $Int) -> Self::Output {
+                     // SAFETY: since `self` is nonzero, the result of the
+                     // bitwise-or will be nonzero regardless of the value of
+                     // `rhs`.
+                     unsafe { $Ty::new_unchecked(self.get() | rhs) }
+                 }
+             }
+ 
+             #[stable(feature = "nonzero_bitor", since = "1.45.0")]
+             impl BitOr<$Ty> for $Int {
+                 type Output = $Ty;
+                 #[inline]
+                 fn bitor(self, rhs: $Ty) -> Self::Output {
+                     // SAFETY: since `rhs` is nonzero, the result of the
+                     // bitwise-or will be nonzero regardless of the value of
+                     // `self`.
+                     unsafe { $Ty::new_unchecked(self | rhs.get()) }
+                 }
+             }
+ 
+             #[stable(feature = "nonzero_bitor", since = "1.45.0")]
+             impl BitOrAssign for $Ty {
+                 #[inline]
+                 fn bitor_assign(&mut self, rhs: Self) {
+                     *self = *self | rhs;
+                 }
+             }
+ 
+             #[stable(feature = "nonzero_bitor", since = "1.45.0")]
+             impl BitOrAssign<$Int> for $Ty {
+                 #[inline]
+                 fn bitor_assign(&mut self, rhs: $Int) {
+                     *self = *self | rhs;
+                 }
+             }
+ 
+             impl_nonzero_fmt! {
+                 #[$stability] (Debug, Display, Binary, Octal, LowerHex, UpperHex) for $Ty
+             }
+         )+
+     }
+ }
+ 
+ nonzero_integers! {
+     #[stable(feature = "nonzero", since = "1.28.0")] NonZeroU8(u8);
+     #[stable(feature = "nonzero", since = "1.28.0")] NonZeroU16(u16);
+     #[stable(feature = "nonzero", since = "1.28.0")] NonZeroU32(u32);
+     #[stable(feature = "nonzero", since = "1.28.0")] NonZeroU64(u64);
+     #[stable(feature = "nonzero", since = "1.28.0")] NonZeroU128(u128);
+     #[stable(feature = "nonzero", since = "1.28.0")] NonZeroUsize(usize);
+     #[stable(feature = "signed_nonzero", since = "1.34.0")] NonZeroI8(i8);
+     #[stable(feature = "signed_nonzero", since = "1.34.0")] NonZeroI16(i16);
+     #[stable(feature = "signed_nonzero", since = "1.34.0")] NonZeroI32(i32);
+     #[stable(feature = "signed_nonzero", since = "1.34.0")] NonZeroI64(i64);
+     #[stable(feature = "signed_nonzero", since = "1.34.0")] NonZeroI128(i128);
+     #[stable(feature = "signed_nonzero", since = "1.34.0")] NonZeroIsize(isize);
+ }
+ 
+ macro_rules! from_str_radix_nzint_impl {
+     ($($t:ty)*) => {$(
+         #[stable(feature = "nonzero_parse", since = "1.35.0")]
+         impl FromStr for $t {
+             type Err = ParseIntError;
+             fn from_str(src: &str) -> Result<Self, Self::Err> {
+                 Self::new(from_str_radix(src, 10)?)
+                     .ok_or(ParseIntError {
+                         kind: IntErrorKind::Zero
+                     })
+             }
+         }
+     )*}
+ }
+ 
+ from_str_radix_nzint_impl! { NonZeroU8 NonZeroU16 NonZeroU32 NonZeroU64 NonZeroU128 NonZeroUsize
+ NonZeroI8 NonZeroI16 NonZeroI32 NonZeroI64 NonZeroI128 NonZeroIsize }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i128.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i128.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i128.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i128.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 128-bit signed integer type.
+ //!
+ //! *[See also the `i128` primitive type](../../std/primitive.i128.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "i128", since = "1.26.0")]
+ 
+ int_module! { i128, #[stable(feature = "i128", since="1.26.0")] }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i16.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i16.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i16.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i16.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 16-bit signed integer type.
+ //!
+ //! *[See also the `i16` primitive type](../../std/primitive.i16.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { i16 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i32.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i32.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 32-bit signed integer type.
+ //!
+ //! *[See also the `i32` primitive type](../../std/primitive.i32.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { i32 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i64.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i64.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 64-bit signed integer type.
+ //!
+ //! *[See also the `i64` primitive type](../../std/primitive.i64.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { i64 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i8.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i8.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/i8.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/i8.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 8-bit signed integer type.
+ //!
+ //! *[See also the `i8` primitive type](../../std/primitive.i8.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { i8 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/int_macros.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/int_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/int_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/int_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,49 ----
+ #![doc(hidden)]
+ 
+ macro_rules! doc_comment {
+     ($x:expr, $($tt:tt)*) => {
+         #[doc = $x]
+         $($tt)*
+     };
+ }
+ 
+ macro_rules! int_module {
+     ($T:ident) => (int_module!($T, #[stable(feature = "rust1", since = "1.0.0")]););
+     ($T:ident, #[$attr:meta]) => (
+         doc_comment! {
+             concat!("The smallest value that can be represented by this integer type.
+ Use [`", stringify!($T), "::MIN", "`](../../std/primitive.", stringify!($T), ".html#associatedconstant.MIN) instead.
+ 
+ # Examples
+ 
+ ```rust
+ // deprecated way
+ let min = std::", stringify!($T), "::MIN;
+ 
+ // intended way
+ let min = ", stringify!($T), "::MIN;
+ ```
+ "),
+             #[$attr]
+             pub const MIN: $T = $T::MIN;
+         }
+ 
+         doc_comment! {
+             concat!("The largest value that can be represented by this integer type.
+ Use [`", stringify!($T), "::MAX", "`](../../std/primitive.", stringify!($T), ".html#associatedconstant.MAX) instead.
+ 
+ # Examples
+ 
+ ```rust
+ // deprecated way
+ let max = std::", stringify!($T), "::MAX;
+ 
+ // intended way
+ let max = ", stringify!($T), "::MAX;
+ ```
+ "),
+             #[$attr]
+             pub const MAX: $T = $T::MAX;
+         }
+     )
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/isize.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/isize.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/isize.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/isize.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The pointer-sized signed integer type.
+ //!
+ //! *[See also the `isize` primitive type](../../std/primitive.isize.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { isize }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u128.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u128.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u128.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u128.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,9 ----
+ //! The 128-bit unsigned integer type.
+ //!
+ //! *[See also the `u128` primitive type](../../std/primitive.u128.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "i128", since = "1.26.0")]
+ int_module! { u128, #[stable(feature = "i128", since="1.26.0")] }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u16.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u16.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u16.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u16.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 16-bit unsigned integer type.
+ //!
+ //! *[See also the `u16` primitive type](../../std/primitive.u16.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { u16 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u32.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u32.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 32-bit unsigned integer type.
+ //!
+ //! *[See also the `u32` primitive type](../../std/primitive.u32.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { u32 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u64.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u64.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 64-bit unsigned integer type.
+ //!
+ //! *[See also the `u64` primitive type](../../std/primitive.u64.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { u64 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u8.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u8.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/u8.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/u8.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The 8-bit unsigned integer type.
+ //!
+ //! *[See also the `u8` primitive type](../../std/primitive.u8.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { u8 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/usize.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/usize.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/shells/usize.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/shells/usize.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ //! The pointer-sized unsigned integer type.
+ //!
+ //! *[See also the `usize` primitive type](../../std/primitive.usize.html).*
+ //!
+ //! Although using these constants won’t cause compilation warnings,
+ //! new code should use the associated constants directly on the primitive type.
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ int_module! { usize }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/uint_macros.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/uint_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/uint_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/uint_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1994 ----
+ macro_rules! uint_impl {
+     ($SelfT:ty, $ActualT:ty, $BITS:expr, $MaxV:expr, $Feature:expr, $EndFeature:expr,
+         $rot:expr, $rot_op:expr, $rot_result:expr, $swap_op:expr, $swapped:expr,
+         $reversed:expr, $le_bytes:expr, $be_bytes:expr,
+         $to_xe_bytes_doc:expr, $from_xe_bytes_doc:expr) => {
+         doc_comment! {
+             concat!("The smallest value that can be represented by this integer type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::MIN, 0);", $EndFeature, "
+ ```"),
+             #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+             pub const MIN: Self = 0;
+         }
+ 
+         doc_comment! {
+             concat!("The largest value that can be represented by this integer type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::MAX, ", stringify!($MaxV), ");",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "assoc_int_consts", since = "1.43.0")]
+             pub const MAX: Self = !0;
+         }
+ 
+         doc_comment! {
+             concat!("The size of this integer type in bits.
+ 
+ # Examples
+ 
+ ```
+ ", $Feature, "#![feature(int_bits_const)]
+ assert_eq!(", stringify!($SelfT), "::BITS, ", stringify!($BITS), ");",
+ $EndFeature, "
+ ```"),
+             #[unstable(feature = "int_bits_const", issue = "76904")]
+             pub const BITS: u32 = $BITS;
+         }
+ 
+         doc_comment! {
+             concat!("Converts a string slice in a given base to an integer.
+ 
+ The string is expected to be an optional `+` sign
+ followed by digits.
+ Leading and trailing whitespace represent an error.
+ Digits are a subset of these characters, depending on `radix`:
+ 
+ * `0-9`
+ * `a-z`
+ * `A-Z`
+ 
+ # Panics
+ 
+ This function panics if `radix` is not in the range from 2 to 36.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::from_str_radix(\"A\", 16), Ok(10));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             pub fn from_str_radix(src: &str, radix: u32) -> Result<Self, ParseIntError> {
+                 from_str_radix(src, radix)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of ones in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0b01001100", stringify!($SelfT), ";
+ 
+ assert_eq!(n.count_ones(), 3);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn count_ones(self) -> u32 {
+                 intrinsics::ctpop(self as $ActualT) as u32
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(", stringify!($SelfT), "::MAX.count_zeros(), 0);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn count_zeros(self) -> u32 {
+                 (!self).count_ones()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of leading zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = ", stringify!($SelfT), "::MAX >> 2;
+ 
+ assert_eq!(n.leading_zeros(), 2);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn leading_zeros(self) -> u32 {
+                 intrinsics::ctlz(self as $ActualT) as u32
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of trailing zeros in the binary representation
+ of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0b0101000", stringify!($SelfT), ";
+ 
+ assert_eq!(n.trailing_zeros(), 3);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn trailing_zeros(self) -> u32 {
+                 intrinsics::cttz(self) as u32
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of leading ones in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = !(", stringify!($SelfT), "::MAX >> 2);
+ 
+ assert_eq!(n.leading_ones(), 2);", $EndFeature, "
+ ```"),
+             #[stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[rustc_const_stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[inline]
+             pub const fn leading_ones(self) -> u32 {
+                 (!self).leading_zeros()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the number of trailing ones in the binary representation
+ of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0b1010111", stringify!($SelfT), ";
+ 
+ assert_eq!(n.trailing_ones(), 3);", $EndFeature, "
+ ```"),
+             #[stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[rustc_const_stable(feature = "leading_trailing_ones", since = "1.46.0")]
+             #[inline]
+             pub const fn trailing_ones(self) -> u32 {
+                 (!self).trailing_zeros()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts the bits to the left by a specified amount, `n`,
+ wrapping the truncated bits to the end of the resulting integer.
+ 
+ Please note this isn't the same operation as the `<<` shifting operator!
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $rot_op, stringify!($SelfT), ";
+ let m = ", $rot_result, ";
+ 
+ assert_eq!(n.rotate_left(", $rot, "), m);
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn rotate_left(self, n: u32) -> Self {
+                 intrinsics::rotate_left(self, n as $SelfT)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts the bits to the right by a specified amount, `n`,
+ wrapping the truncated bits to the beginning of the resulting
+ integer.
+ 
+ Please note this isn't the same operation as the `>>` shifting operator!
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $rot_result, stringify!($SelfT), ";
+ let m = ", $rot_op, ";
+ 
+ assert_eq!(n.rotate_right(", $rot, "), m);
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn rotate_right(self, n: u32) -> Self {
+                 intrinsics::rotate_right(self, n as $SelfT)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("
+ Reverses the byte order of the integer.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $swap_op, stringify!($SelfT), ";
+ let m = n.swap_bytes();
+ 
+ assert_eq!(m, ", $swapped, ");
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn swap_bytes(self) -> Self {
+                 intrinsics::bswap(self as $ActualT) as Self
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Reverses the order of bits in the integer. The least significant bit becomes the most significant bit,
+                 second least-significant bit becomes second most-significant bit, etc.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ let n = ", $swap_op, stringify!($SelfT), ";
+ let m = n.reverse_bits();
+ 
+ assert_eq!(m, ", $reversed, ");
+ assert_eq!(0, 0", stringify!($SelfT), ".reverse_bits());
+ ```"),
+             #[stable(feature = "reverse_bits", since = "1.37.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             #[must_use]
+             pub const fn reverse_bits(self) -> Self {
+                 intrinsics::bitreverse(self as $ActualT) as Self
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts an integer from big endian to the target's endianness.
+ 
+ On big endian this is a no-op. On little endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"big\") {
+     assert_eq!(", stringify!($SelfT), "::from_be(n), n)
+ } else {
+     assert_eq!(", stringify!($SelfT), "::from_be(n), n.swap_bytes())
+ }", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn from_be(x: Self) -> Self {
+                 #[cfg(target_endian = "big")]
+                 {
+                     x
+                 }
+                 #[cfg(not(target_endian = "big"))]
+                 {
+                     x.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts an integer from little endian to the target's endianness.
+ 
+ On little endian this is a no-op. On big endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"little\") {
+     assert_eq!(", stringify!($SelfT), "::from_le(n), n)
+ } else {
+     assert_eq!(", stringify!($SelfT), "::from_le(n), n.swap_bytes())
+ }", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn from_le(x: Self) -> Self {
+                 #[cfg(target_endian = "little")]
+                 {
+                     x
+                 }
+                 #[cfg(not(target_endian = "little"))]
+                 {
+                     x.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts `self` to big endian from the target's endianness.
+ 
+ On big endian this is a no-op. On little endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"big\") {
+     assert_eq!(n.to_be(), n)
+ } else {
+     assert_eq!(n.to_be(), n.swap_bytes())
+ }", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn to_be(self) -> Self { // or not to be?
+                 #[cfg(target_endian = "big")]
+                 {
+                     self
+                 }
+                 #[cfg(not(target_endian = "big"))]
+                 {
+                     self.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Converts `self` to little endian from the target's endianness.
+ 
+ On little endian this is a no-op. On big endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "let n = 0x1A", stringify!($SelfT), ";
+ 
+ if cfg!(target_endian = \"little\") {
+     assert_eq!(n.to_le(), n)
+ } else {
+     assert_eq!(n.to_le(), n.swap_bytes())
+ }", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_math", since = "1.32.0")]
+             #[inline]
+             pub const fn to_le(self) -> Self {
+                 #[cfg(target_endian = "little")]
+                 {
+                     self
+                 }
+                 #[cfg(not(target_endian = "little"))]
+                 {
+                     self.swap_bytes()
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer addition. Computes `self + rhs`, returning `None`
+ if overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!((", stringify!($SelfT), "::MAX - 2).checked_add(1), ",
+ "Some(", stringify!($SelfT), "::MAX - 1));
+ assert_eq!((", stringify!($SelfT), "::MAX - 2).checked_add(3), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_add(self, rhs: Self) -> Option<Self> {
+                 let (a, b) = self.overflowing_add(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Unchecked integer addition. Computes `self + rhs`, assuming overflow
+ cannot occur. This results in undefined behavior when `self + rhs > ", stringify!($SelfT),
+ "::MAX` or `self + rhs < ", stringify!($SelfT), "::MIN`."),
+             #[unstable(
+                 feature = "unchecked_math",
+                 reason = "niche optimization path",
+                 issue = "none",
+             )]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub unsafe fn unchecked_add(self, rhs: Self) -> Self {
+                 // SAFETY: the caller must uphold the safety contract for
+                 // `unchecked_add`.
+                 unsafe { intrinsics::unchecked_add(self, rhs) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer subtraction. Computes `self - rhs`, returning
+ `None` if overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(1", stringify!($SelfT), ".checked_sub(1), Some(0));
+ assert_eq!(0", stringify!($SelfT), ".checked_sub(1), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_sub(self, rhs: Self) -> Option<Self> {
+                 let (a, b) = self.overflowing_sub(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Unchecked integer subtraction. Computes `self - rhs`, assuming overflow
+ cannot occur. This results in undefined behavior when `self - rhs > ", stringify!($SelfT),
+ "::MAX` or `self - rhs < ", stringify!($SelfT), "::MIN`."),
+             #[unstable(
+                 feature = "unchecked_math",
+                 reason = "niche optimization path",
+                 issue = "none",
+             )]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub unsafe fn unchecked_sub(self, rhs: Self) -> Self {
+                 // SAFETY: the caller must uphold the safety contract for
+                 // `unchecked_sub`.
+                 unsafe { intrinsics::unchecked_sub(self, rhs) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer multiplication. Computes `self * rhs`, returning
+ `None` if overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(5", stringify!($SelfT), ".checked_mul(1), Some(5));
+ assert_eq!(", stringify!($SelfT), "::MAX.checked_mul(2), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_mul(self, rhs: Self) -> Option<Self> {
+                 let (a, b) = self.overflowing_mul(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Unchecked integer multiplication. Computes `self * rhs`, assuming overflow
+ cannot occur. This results in undefined behavior when `self * rhs > ", stringify!($SelfT),
+ "::MAX` or `self * rhs < ", stringify!($SelfT), "::MIN`."),
+             #[unstable(
+                 feature = "unchecked_math",
+                 reason = "niche optimization path",
+                 issue = "none",
+             )]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub unsafe fn unchecked_mul(self, rhs: Self) -> Self {
+                 // SAFETY: the caller must uphold the safety contract for
+                 // `unchecked_mul`.
+                 unsafe { intrinsics::unchecked_mul(self, rhs) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked integer division. Computes `self / rhs`, returning `None`
+ if `rhs == 0`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(128", stringify!($SelfT), ".checked_div(2), Some(64));
+ assert_eq!(1", stringify!($SelfT), ".checked_div(0), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_unstable(feature = "const_checked_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_div(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0) {
+                     None
+                 } else {
+                     // SAFETY: div by zero has been checked above and unsigned types have no other
+                     // failure modes for division
+                     Some(unsafe { intrinsics::unchecked_div(self, rhs) })
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked Euclidean division. Computes `self.div_euclid(rhs)`, returning `None`
+ if `rhs == 0`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(128", stringify!($SelfT), ".checked_div_euclid(2), Some(64));
+ assert_eq!(1", stringify!($SelfT), ".checked_div_euclid(0), None);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_div_euclid(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0) {
+                     None
+                 } else {
+                     Some(self.div_euclid(rhs))
+                 }
+             }
+         }
+ 
+ 
+         doc_comment! {
+             concat!("Checked integer remainder. Computes `self % rhs`, returning `None`
+ if `rhs == 0`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(5", stringify!($SelfT), ".checked_rem(2), Some(1));
+ assert_eq!(5", stringify!($SelfT), ".checked_rem(0), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_unstable(feature = "const_checked_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_rem(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0) {
+                     None
+                 } else {
+                     // SAFETY: div by zero has been checked above and unsigned types have no other
+                     // failure modes for division
+                     Some(unsafe { intrinsics::unchecked_rem(self, rhs) })
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked Euclidean modulo. Computes `self.rem_euclid(rhs)`, returning `None`
+ if `rhs == 0`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(5", stringify!($SelfT), ".checked_rem_euclid(2), Some(1));
+ assert_eq!(5", stringify!($SelfT), ".checked_rem_euclid(0), None);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_rem_euclid(self, rhs: Self) -> Option<Self> {
+                 if unlikely!(rhs == 0) {
+                     None
+                 } else {
+                     Some(self.rem_euclid(rhs))
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked negation. Computes `-self`, returning `None` unless `self ==
+ 0`.
+ 
+ Note that negating any positive integer will overflow.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0", stringify!($SelfT), ".checked_neg(), Some(0));
+ assert_eq!(1", stringify!($SelfT), ".checked_neg(), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn checked_neg(self) -> Option<Self> {
+                 let (a, b) = self.overflowing_neg();
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked shift left. Computes `self << rhs`, returning `None`
+ if `rhs` is larger than or equal to the number of bits in `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0x1", stringify!($SelfT), ".checked_shl(4), Some(0x10));
+ assert_eq!(0x10", stringify!($SelfT), ".checked_shl(129), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_shl(self, rhs: u32) -> Option<Self> {
+                 let (a, b) = self.overflowing_shl(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked shift right. Computes `self >> rhs`, returning `None`
+ if `rhs` is larger than or equal to the number of bits in `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(0x10", stringify!($SelfT), ".checked_shr(4), Some(0x1));
+ assert_eq!(0x10", stringify!($SelfT), ".checked_shr(129), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_checked_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_shr(self, rhs: u32) -> Option<Self> {
+                 let (a, b) = self.overflowing_shr(rhs);
+                 if unlikely!(b) {None} else {Some(a)}
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Checked exponentiation. Computes `self.pow(exp)`, returning `None` if
+ overflow occurred.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(2", stringify!($SelfT), ".checked_pow(5), Some(32));
+ assert_eq!(", stringify!($SelfT), "::MAX.checked_pow(2), None);", $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn checked_pow(self, mut exp: u32) -> Option<Self> {
+                 if exp == 0 {
+                     return Some(1);
+                 }
+                 let mut base = self;
+                 let mut acc: Self = 1;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         acc = try_opt!(acc.checked_mul(base));
+                     }
+                     exp /= 2;
+                     base = try_opt!(base.checked_mul(base));
+                 }
+ 
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+ 
+                 Some(try_opt!(acc.checked_mul(base)))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer addition. Computes `self + rhs`, saturating at
+ the numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".saturating_add(1), 101);
+ assert_eq!(", stringify!($SelfT), "::MAX.saturating_add(127), ", stringify!($SelfT), "::MAX);",
+ $EndFeature, "
+ ```"),
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn saturating_add(self, rhs: Self) -> Self {
+                 intrinsics::saturating_add(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer subtraction. Computes `self - rhs`, saturating
+ at the numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".saturating_sub(27), 73);
+ assert_eq!(13", stringify!($SelfT), ".saturating_sub(127), 0);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[inline]
+             pub const fn saturating_sub(self, rhs: Self) -> Self {
+                 intrinsics::saturating_sub(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer multiplication. Computes `self * rhs`,
+ saturating at the numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(2", stringify!($SelfT), ".saturating_mul(10), 20);
+ assert_eq!((", stringify!($SelfT), "::MAX).saturating_mul(10), ", stringify!($SelfT),
+ "::MAX);", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_saturating_int_methods", since = "1.47.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn saturating_mul(self, rhs: Self) -> Self {
+                 match self.checked_mul(rhs) {
+                     Some(x) => x,
+                     None => Self::MAX,
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Saturating integer exponentiation. Computes `self.pow(exp)`,
+ saturating at the numeric bounds instead of overflowing.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(4", stringify!($SelfT), ".saturating_pow(3), 64);
+ assert_eq!(", stringify!($SelfT), "::MAX.saturating_pow(2), ", stringify!($SelfT), "::MAX);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn saturating_pow(self, exp: u32) -> Self {
+                 match self.checked_pow(exp) {
+                     Some(x) => x,
+                     None => Self::MAX,
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) addition. Computes `self + rhs`,
+ wrapping around at the boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(200", stringify!($SelfT), ".wrapping_add(55), 255);
+ assert_eq!(200", stringify!($SelfT), ".wrapping_add(", stringify!($SelfT), "::MAX), 199);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_add(self, rhs: Self) -> Self {
+                 intrinsics::wrapping_add(self, rhs)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) subtraction. Computes `self - rhs`,
+ wrapping around at the boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_sub(100), 0);
+ assert_eq!(100", stringify!($SelfT), ".wrapping_sub(", stringify!($SelfT), "::MAX), 101);",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_sub(self, rhs: Self) -> Self {
+                 intrinsics::wrapping_sub(self, rhs)
+             }
+         }
+ 
+         /// Wrapping (modular) multiplication. Computes `self *
+         /// rhs`, wrapping around at the boundary of the type.
+         ///
+         /// # Examples
+         ///
+         /// Basic usage:
+         ///
+         /// Please note that this example is shared between integer types.
+         /// Which explains why `u8` is used here.
+         ///
+         /// ```
+         /// assert_eq!(10u8.wrapping_mul(12), 120);
+         /// assert_eq!(25u8.wrapping_mul(12), 44);
+         /// ```
+         #[stable(feature = "rust1", since = "1.0.0")]
+         #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+         #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+         #[inline]
+         pub const fn wrapping_mul(self, rhs: Self) -> Self {
+             intrinsics::wrapping_mul(self, rhs)
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) division. Computes `self / rhs`.
+ Wrapped division on unsigned types is just normal division.
+ There's no way wrapping could ever happen.
+ This function exists, so that all operations
+ are accounted for in the wrapping operations.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_div(10), 10);", $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_unstable(feature = "const_wrapping_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_div(self, rhs: Self) -> Self {
+                 self / rhs
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping Euclidean division. Computes `self.div_euclid(rhs)`.
+ Wrapped division on unsigned types is just normal division.
+ There's no way wrapping could ever happen.
+ This function exists, so that all operations
+ are accounted for in the wrapping operations.
+ Since, for the positive integers, all common
+ definitions of division are equal, this
+ is exactly equal to `self.wrapping_div(rhs)`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(100", stringify!($SelfT), ".wrapping_div_euclid(10), 10);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_div_euclid(self, rhs: Self) -> Self {
+                 self / rhs
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) remainder. Computes `self % rhs`.
+ Wrapped remainder calculation on unsigned types is
+ just the regular remainder calculation.
+ There's no way wrapping could ever happen.
+ This function exists, so that all operations
+ are accounted for in the wrapping operations.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(100", stringify!($SelfT), ".wrapping_rem(10), 0);", $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_unstable(feature = "const_wrapping_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_rem(self, rhs: Self) -> Self {
+                 self % rhs
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping Euclidean modulo. Computes `self.rem_euclid(rhs)`.
+ Wrapped modulo calculation on unsigned types is
+ just the regular remainder calculation.
+ There's no way wrapping could ever happen.
+ This function exists, so that all operations
+ are accounted for in the wrapping operations.
+ Since, for the positive integers, all common
+ definitions of division are equal, this
+ is exactly equal to `self.wrapping_rem(rhs)`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(100", stringify!($SelfT), ".wrapping_rem_euclid(10), 0);
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_rem_euclid(self, rhs: Self) -> Self {
+                 self % rhs
+             }
+         }
+ 
+         /// Wrapping (modular) negation. Computes `-self`,
+         /// wrapping around at the boundary of the type.
+         ///
+         /// Since unsigned types do not have negative equivalents
+         /// all applications of this function will wrap (except for `-0`).
+         /// For values smaller than the corresponding signed type's maximum
+         /// the result is the same as casting the corresponding signed value.
+         /// Any larger values are equivalent to `MAX + 1 - (val - MAX - 1)` where
+         /// `MAX` is the corresponding signed type's maximum.
+         ///
+         /// # Examples
+         ///
+         /// Basic usage:
+         ///
+         /// Please note that this example is shared between integer types.
+         /// Which explains why `i8` is used here.
+         ///
+         /// ```
+         /// assert_eq!(100i8.wrapping_neg(), -100);
+         /// assert_eq!((-128i8).wrapping_neg(), -128);
+         /// ```
+         #[stable(feature = "num_wrapping", since = "1.2.0")]
+         #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+         #[inline]
+         pub const fn wrapping_neg(self) -> Self {
+             self.overflowing_neg().0
+         }
+ 
+         doc_comment! {
+             concat!("Panic-free bitwise shift-left; yields `self << mask(rhs)`,
+ where `mask` removes any high-order bits of `rhs` that
+ would cause the shift to exceed the bitwidth of the type.
+ 
+ Note that this is *not* the same as a rotate-left; the
+ RHS of a wrapping shift-left is restricted to the range
+ of the type, rather than the bits shifted out of the LHS
+ being returned to the other end. The primitive integer
+ types all implement a [`rotate_left`](#method.rotate_left) function,
+ which may be what you want instead.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(1", stringify!($SelfT), ".wrapping_shl(7), 128);
+ assert_eq!(1", stringify!($SelfT), ".wrapping_shl(128), 1);", $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_shl(self, rhs: u32) -> Self {
+                 // SAFETY: the masking by the bitsize of the type ensures that we do not shift
+                 // out of bounds
+                 unsafe {
+                     intrinsics::unchecked_shl(self, (rhs & ($BITS - 1)) as $SelfT)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Panic-free bitwise shift-right; yields `self >> mask(rhs)`,
+ where `mask` removes any high-order bits of `rhs` that
+ would cause the shift to exceed the bitwidth of the type.
+ 
+ Note that this is *not* the same as a rotate-right; the
+ RHS of a wrapping shift-right is restricted to the range
+ of the type, rather than the bits shifted out of the LHS
+ being returned to the other end. The primitive integer
+ types all implement a [`rotate_right`](#method.rotate_right) function,
+ which may be what you want instead.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(128", stringify!($SelfT), ".wrapping_shr(7), 1);
+ assert_eq!(128", stringify!($SelfT), ".wrapping_shr(128), 128);", $EndFeature, "
+ ```"),
+             #[stable(feature = "num_wrapping", since = "1.2.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_shr(self, rhs: u32) -> Self {
+                 // SAFETY: the masking by the bitsize of the type ensures that we do not shift
+                 // out of bounds
+                 unsafe {
+                     intrinsics::unchecked_shr(self, (rhs & ($BITS - 1)) as $SelfT)
+                 }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Wrapping (modular) exponentiation. Computes `self.pow(exp)`,
+ wrapping around at the boundary of the type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(3", stringify!($SelfT), ".wrapping_pow(5), 243);
+ assert_eq!(3u8.wrapping_pow(6), 217);", $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn wrapping_pow(self, mut exp: u32) -> Self {
+                 if exp == 0 {
+                     return 1;
+                 }
+                 let mut base = self;
+                 let mut acc: Self = 1;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         acc = acc.wrapping_mul(base);
+                     }
+                     exp /= 2;
+                     base = base.wrapping_mul(base);
+                 }
+ 
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+                 acc.wrapping_mul(base)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates `self` + `rhs`
+ 
+ Returns a tuple of the addition along with a boolean indicating
+ whether an arithmetic overflow would occur. If an overflow would
+ have occurred then the wrapped value is returned.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".overflowing_add(2), (7, false));
+ assert_eq!(", stringify!($SelfT), "::MAX.overflowing_add(1), (0, true));", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_add(self, rhs: Self) -> (Self, bool) {
+                 let (a, b) = intrinsics::add_with_overflow(self as $ActualT, rhs as $ActualT);
+                 (a as Self, b)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates `self` - `rhs`
+ 
+ Returns a tuple of the subtraction along with a boolean indicating
+ whether an arithmetic overflow would occur. If an overflow would
+ have occurred then the wrapped value is returned.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "
+ assert_eq!(5", stringify!($SelfT), ".overflowing_sub(2), (3, false));
+ assert_eq!(0", stringify!($SelfT), ".overflowing_sub(1), (", stringify!($SelfT), "::MAX, true));",
+ $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_sub(self, rhs: Self) -> (Self, bool) {
+                 let (a, b) = intrinsics::sub_with_overflow(self as $ActualT, rhs as $ActualT);
+                 (a as Self, b)
+             }
+         }
+ 
+         /// Calculates the multiplication of `self` and `rhs`.
+         ///
+         /// Returns a tuple of the multiplication along with a boolean
+         /// indicating whether an arithmetic overflow would occur. If an
+         /// overflow would have occurred then the wrapped value is returned.
+         ///
+         /// # Examples
+         ///
+         /// Basic usage:
+         ///
+         /// Please note that this example is shared between integer types.
+         /// Which explains why `u32` is used here.
+         ///
+         /// ```
+         /// assert_eq!(5u32.overflowing_mul(2), (10, false));
+         /// assert_eq!(1_000_000_000u32.overflowing_mul(10), (1410065408, true));
+         /// ```
+         #[stable(feature = "wrapping", since = "1.7.0")]
+         #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+         #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+         #[inline]
+         pub const fn overflowing_mul(self, rhs: Self) -> (Self, bool) {
+             let (a, b) = intrinsics::mul_with_overflow(self as $ActualT, rhs as $ActualT);
+             (a as Self, b)
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the divisor when `self` is divided by `rhs`.
+ 
+ Returns a tuple of the divisor along with a boolean indicating
+ whether an arithmetic overflow would occur. Note that for unsigned
+ integers overflow never occurs, so the second value is always
+ `false`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "assert_eq!(5", stringify!($SelfT), ".overflowing_div(2), (2, false));", $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_unstable(feature = "const_overflowing_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_div(self, rhs: Self) -> (Self, bool) {
+                 (self / rhs, false)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the quotient of Euclidean division `self.div_euclid(rhs)`.
+ 
+ Returns a tuple of the divisor along with a boolean indicating
+ whether an arithmetic overflow would occur. Note that for unsigned
+ integers overflow never occurs, so the second value is always
+ `false`.
+ Since, for the positive integers, all common
+ definitions of division are equal, this
+ is exactly equal to `self.overflowing_div(rhs)`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ assert_eq!(5", stringify!($SelfT), ".overflowing_div_euclid(2), (2, false));
+ ```"),
+             #[inline]
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_div_euclid(self, rhs: Self) -> (Self, bool) {
+                 (self / rhs, false)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the remainder when `self` is divided by `rhs`.
+ 
+ Returns a tuple of the remainder after dividing along with a boolean
+ indicating whether an arithmetic overflow would occur. Note that for
+ unsigned integers overflow never occurs, so the second value is
+ always `false`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "assert_eq!(5", stringify!($SelfT), ".overflowing_rem(2), (1, false));", $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_unstable(feature = "const_overflowing_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_rem(self, rhs: Self) -> (Self, bool) {
+                 (self % rhs, false)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Calculates the remainder `self.rem_euclid(rhs)` as if by Euclidean division.
+ 
+ Returns a tuple of the modulo after dividing along with a boolean
+ indicating whether an arithmetic overflow would occur. Note that for
+ unsigned integers overflow never occurs, so the second value is
+ always `false`.
+ Since, for the positive integers, all common
+ definitions of division are equal, this operation
+ is exactly equal to `self.overflowing_rem(rhs)`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ assert_eq!(5", stringify!($SelfT), ".overflowing_rem_euclid(2), (1, false));
+ ```"),
+             #[inline]
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             pub const fn overflowing_rem_euclid(self, rhs: Self) -> (Self, bool) {
+                 (self % rhs, false)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Negates self in an overflowing fashion.
+ 
+ Returns `!self + 1` using wrapping operations to return the value
+ that represents the negation of this unsigned value. Note that for
+ positive unsigned values overflow always occurs, but negating 0 does
+ not overflow.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "assert_eq!(0", stringify!($SelfT), ".overflowing_neg(), (0, false));
+ assert_eq!(2", stringify!($SelfT), ".overflowing_neg(), (-2i32 as ", stringify!($SelfT),
+ ", true));", $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             pub const fn overflowing_neg(self) -> (Self, bool) {
+                 ((!self).wrapping_add(1), self != 0)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts self left by `rhs` bits.
+ 
+ Returns a tuple of the shifted version of self along with a boolean
+ indicating whether the shift value was larger than or equal to the
+ number of bits. If the shift value is too large, then value is
+ masked (N-1) where N is the number of bits, and this value is then
+ used to perform the shift.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "assert_eq!(0x1", stringify!($SelfT), ".overflowing_shl(4), (0x10, false));
+ assert_eq!(0x1", stringify!($SelfT), ".overflowing_shl(132), (0x10, true));", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_shl(self, rhs: u32) -> (Self, bool) {
+                 (self.wrapping_shl(rhs), (rhs > ($BITS - 1)))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Shifts self right by `rhs` bits.
+ 
+ Returns a tuple of the shifted version of self along with a boolean
+ indicating whether the shift value was larger than or equal to the
+ number of bits. If the shift value is too large, then value is
+ masked (N-1) where N is the number of bits, and this value is then
+ used to perform the shift.
+ 
+ # Examples
+ 
+ Basic usage
+ 
+ ```
+ ", $Feature, "assert_eq!(0x10", stringify!($SelfT), ".overflowing_shr(4), (0x1, false));
+ assert_eq!(0x10", stringify!($SelfT), ".overflowing_shr(132), (0x1, true));", $EndFeature, "
+ ```"),
+             #[stable(feature = "wrapping", since = "1.7.0")]
+             #[rustc_const_stable(feature = "const_wrapping_math", since = "1.32.0")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_shr(self, rhs: u32) -> (Self, bool) {
+                 (self.wrapping_shr(rhs), (rhs > ($BITS - 1)))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Raises self to the power of `exp`, using exponentiation by squaring.
+ 
+ Returns a tuple of the exponentiation along with a bool indicating
+ whether an overflow happened.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(3", stringify!($SelfT), ".overflowing_pow(5), (243, false));
+ assert_eq!(3u8.overflowing_pow(6), (217, true));", $EndFeature, "
+ ```"),
+             #[stable(feature = "no_panic_pow", since = "1.34.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             pub const fn overflowing_pow(self, mut exp: u32) -> (Self, bool) {
+                 if exp == 0{
+                     return (1,false);
+                 }
+                 let mut base = self;
+                 let mut acc: Self = 1;
+                 let mut overflown = false;
+                 // Scratch space for storing results of overflowing_mul.
+                 let mut r;
+ 
+                 while exp > 1 {
+                     if (exp & 1) == 1 {
+                         r = acc.overflowing_mul(base);
+                         acc = r.0;
+                         overflown |= r.1;
+                     }
+                     exp /= 2;
+                     r = base.overflowing_mul(base);
+                     base = r.0;
+                     overflown |= r.1;
+                 }
+ 
+                 // since exp!=0, finally the exp must be 1.
+                 // Deal with the final bit of the exponent separately, since
+                 // squaring the base afterwards is not necessary and may cause a
+                 // needless overflow.
+                 r = acc.overflowing_mul(base);
+                 r.1 |= overflown;
+ 
+                 r
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Raises self to the power of `exp`, using exponentiation by squaring.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(2", stringify!($SelfT), ".pow(5), 32);", $EndFeature, "
+ ```"),
+         #[stable(feature = "rust1", since = "1.0.0")]
+         #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+         #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+         #[inline]
+         #[rustc_inherit_overflow_checks]
+         pub const fn pow(self, mut exp: u32) -> Self {
+             if exp == 0 {
+                 return 1;
+             }
+             let mut base = self;
+             let mut acc = 1;
+ 
+             while exp > 1 {
+                 if (exp & 1) == 1 {
+                     acc = acc * base;
+                 }
+                 exp /= 2;
+                 base = base * base;
+             }
+ 
+             // since exp!=0, finally the exp must be 1.
+             // Deal with the final bit of the exponent separately, since
+             // squaring the base afterwards is not necessary and may cause a
+             // needless overflow.
+             acc * base
+         }
+     }
+ 
+         doc_comment! {
+             concat!("Performs Euclidean division.
+ 
+ Since, for the positive integers, all common
+ definitions of division are equal, this
+ is exactly equal to `self / rhs`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(7", stringify!($SelfT), ".div_euclid(4), 1); // or any other integer type
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn div_euclid(self, rhs: Self) -> Self {
+                 self / rhs
+             }
+         }
+ 
+ 
+         doc_comment! {
+             concat!("Calculates the least remainder of `self (mod rhs)`.
+ 
+ Since, for the positive integers, all common
+ definitions of division are equal, this
+ is exactly equal to `self % rhs`.
+ 
+ # Panics
+ 
+ This function will panic if `rhs` is 0.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ assert_eq!(7", stringify!($SelfT), ".rem_euclid(4), 3); // or any other integer type
+ ```"),
+             #[stable(feature = "euclidean_division", since = "1.38.0")]
+             #[rustc_const_unstable(feature = "const_euclidean_int_methods", issue = "53718")]
+             #[must_use = "this returns the result of the operation, \
+                           without modifying the original"]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn rem_euclid(self, rhs: Self) -> Self {
+                 self % rhs
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns `true` if and only if `self == 2^k` for some `k`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert!(16", stringify!($SelfT), ".is_power_of_two());
+ assert!(!10", stringify!($SelfT), ".is_power_of_two());", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_stable(feature = "const_is_power_of_two", since = "1.32.0")]
+             #[inline]
+             pub const fn is_power_of_two(self) -> bool {
+                 self.count_ones() == 1
+             }
+         }
+ 
+         // Returns one less than next power of two.
+         // (For 8u8 next power of two is 8u8 and for 6u8 it is 8u8)
+         //
+         // 8u8.one_less_than_next_power_of_two() == 7
+         // 6u8.one_less_than_next_power_of_two() == 7
+         //
+         // This method cannot overflow, as in the `next_power_of_two`
+         // overflow cases it instead ends up returning the maximum value
+         // of the type, and can return 0 for 0.
+         #[inline]
+         #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+         const fn one_less_than_next_power_of_two(self) -> Self {
+             if self <= 1 { return 0; }
+ 
+             let p = self - 1;
+             // SAFETY: Because `p > 0`, it cannot consist entirely of leading zeros.
+             // That means the shift is always in-bounds, and some processors
+             // (such as intel pre-haswell) have more efficient ctlz
+             // intrinsics when the argument is non-zero.
+             let z = unsafe { intrinsics::ctlz_nonzero(p) };
+             <$SelfT>::MAX >> z
+         }
+ 
+         doc_comment! {
+             concat!("Returns the smallest power of two greater than or equal to `self`.
+ 
+ When return value overflows (i.e., `self > (1 << (N-1))` for type
+ `uN`), it panics in debug mode and return value is wrapped to 0 in
+ release mode (the only situation in which method can return 0).
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(2", stringify!($SelfT), ".next_power_of_two(), 2);
+ assert_eq!(3", stringify!($SelfT), ".next_power_of_two(), 4);", $EndFeature, "
+ ```"),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             pub const fn next_power_of_two(self) -> Self {
+                 self.one_less_than_next_power_of_two() + 1
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the smallest power of two greater than or equal to `n`. If
+ the next power of two is greater than the type's maximum value,
+ `None` is returned, otherwise the power of two is wrapped in `Some`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ ", $Feature, "assert_eq!(2", stringify!($SelfT),
+ ".checked_next_power_of_two(), Some(2));
+ assert_eq!(3", stringify!($SelfT), ".checked_next_power_of_two(), Some(4));
+ assert_eq!(", stringify!($SelfT), "::MAX.checked_next_power_of_two(), None);",
+ $EndFeature, "
+ ```"),
+             #[inline]
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             pub const fn checked_next_power_of_two(self) -> Option<Self> {
+                 self.one_less_than_next_power_of_two().checked_add(1)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Returns the smallest power of two greater than or equal to `n`. If
+ the next power of two is greater than the type's maximum value,
+ the return value is wrapped to `0`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_next_power_of_two)]
+ ", $Feature, "
+ assert_eq!(2", stringify!($SelfT), ".wrapping_next_power_of_two(), 2);
+ assert_eq!(3", stringify!($SelfT), ".wrapping_next_power_of_two(), 4);
+ assert_eq!(", stringify!($SelfT), "::MAX.wrapping_next_power_of_two(), 0);",
+ $EndFeature, "
+ ```"),
+             #[unstable(feature = "wrapping_next_power_of_two", issue = "32463",
+                        reason = "needs decision on wrapping behaviour")]
+             #[rustc_const_unstable(feature = "const_int_pow", issue = "53718")]
+             pub const fn wrapping_next_power_of_two(self) -> Self {
+                 self.one_less_than_next_power_of_two().wrapping_add(1)
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Return the memory representation of this integer as a byte array in
+ big-endian (network) byte order.
+ ",
+ $to_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let bytes = ", $swap_op, stringify!($SelfT), ".to_be_bytes();
+ assert_eq!(bytes, ", $be_bytes, ");
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn to_be_bytes(self) -> [u8; mem::size_of::<Self>()] {
+                 self.to_be().to_ne_bytes()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Return the memory representation of this integer as a byte array in
+ little-endian byte order.
+ ",
+ $to_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let bytes = ", $swap_op, stringify!($SelfT), ".to_le_bytes();
+ assert_eq!(bytes, ", $le_bytes, ");
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn to_le_bytes(self) -> [u8; mem::size_of::<Self>()] {
+                 self.to_le().to_ne_bytes()
+             }
+         }
+ 
+         doc_comment! {
+             concat!("
+ Return the memory representation of this integer as a byte array in
+ native byte order.
+ 
+ As the target platform's native endianness is used, portable code
+ should use [`to_be_bytes`] or [`to_le_bytes`], as appropriate,
+ instead.
+ ",
+ $to_xe_bytes_doc,
+ "
+ [`to_be_bytes`]: #method.to_be_bytes
+ [`to_le_bytes`]: #method.to_le_bytes
+ 
+ # Examples
+ 
+ ```
+ let bytes = ", $swap_op, stringify!($SelfT), ".to_ne_bytes();
+ assert_eq!(
+     bytes,
+     if cfg!(target_endian = \"big\") {
+         ", $be_bytes, "
+     } else {
+         ", $le_bytes, "
+     }
+ );
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             // SAFETY: const sound because integers are plain old datatypes so we can always
+             // transmute them to arrays of bytes
+             #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_transmute))]
+             #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_transmute))]
+             #[inline]
+             pub const fn to_ne_bytes(self) -> [u8; mem::size_of::<Self>()] {
+                 // SAFETY: integers are plain old datatypes so we can always transmute them to
+                 // arrays of bytes
+                 unsafe { mem::transmute(self) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("
+ Return the memory representation of this integer as a byte array in
+ native byte order.
+ 
+ [`to_ne_bytes`] should be preferred over this whenever possible.
+ 
+ [`to_ne_bytes`]: #method.to_ne_bytes
+ ",
+ 
+ "
+ # Examples
+ 
+ ```
+ #![feature(num_as_ne_bytes)]
+ let num = ", $swap_op, stringify!($SelfT), ";
+ let bytes = num.as_ne_bytes();
+ assert_eq!(
+     bytes,
+     if cfg!(target_endian = \"big\") {
+         &", $be_bytes, "
+     } else {
+         &", $le_bytes, "
+     }
+ );
+ ```"),
+             #[unstable(feature = "num_as_ne_bytes", issue = "76976")]
+             #[inline]
+             pub fn as_ne_bytes(&self) -> &[u8; mem::size_of::<Self>()] {
+                 // SAFETY: integers are plain old datatypes so we can always transmute them to
+                 // arrays of bytes
+                 unsafe { &*(self as *const Self as *const _) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Create a native endian integer value from its representation
+ as a byte array in big endian.
+ ",
+ $from_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let value = ", stringify!($SelfT), "::from_be_bytes(", $be_bytes, ");
+ assert_eq!(value, ", $swap_op, ");
+ ```
+ 
+ When starting from a slice rather than an array, fallible conversion APIs can be used:
+ 
+ ```
+ use std::convert::TryInto;
+ 
+ fn read_be_", stringify!($SelfT), "(input: &mut &[u8]) -> ", stringify!($SelfT), " {
+     let (int_bytes, rest) = input.split_at(std::mem::size_of::<", stringify!($SelfT), ">());
+     *input = rest;
+     ", stringify!($SelfT), "::from_be_bytes(int_bytes.try_into().unwrap())
+ }
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn from_be_bytes(bytes: [u8; mem::size_of::<Self>()]) -> Self {
+                 Self::from_be(Self::from_ne_bytes(bytes))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("
+ Create a native endian integer value from its representation
+ as a byte array in little endian.
+ ",
+ $from_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let value = ", stringify!($SelfT), "::from_le_bytes(", $le_bytes, ");
+ assert_eq!(value, ", $swap_op, ");
+ ```
+ 
+ When starting from a slice rather than an array, fallible conversion APIs can be used:
+ 
+ ```
+ use std::convert::TryInto;
+ 
+ fn read_le_", stringify!($SelfT), "(input: &mut &[u8]) -> ", stringify!($SelfT), " {
+     let (int_bytes, rest) = input.split_at(std::mem::size_of::<", stringify!($SelfT), ">());
+     *input = rest;
+     ", stringify!($SelfT), "::from_le_bytes(int_bytes.try_into().unwrap())
+ }
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             #[inline]
+             pub const fn from_le_bytes(bytes: [u8; mem::size_of::<Self>()]) -> Self {
+                 Self::from_le(Self::from_ne_bytes(bytes))
+             }
+         }
+ 
+         doc_comment! {
+             concat!("Create a native endian integer value from its memory representation
+ as a byte array in native endianness.
+ 
+ As the target platform's native endianness is used, portable code
+ likely wants to use [`from_be_bytes`] or [`from_le_bytes`], as
+ appropriate instead.
+ 
+ [`from_be_bytes`]: #method.from_be_bytes
+ [`from_le_bytes`]: #method.from_le_bytes
+ ",
+ $from_xe_bytes_doc,
+ "
+ # Examples
+ 
+ ```
+ let value = ", stringify!($SelfT), "::from_ne_bytes(if cfg!(target_endian = \"big\") {
+     ", $be_bytes, "
+ } else {
+     ", $le_bytes, "
+ });
+ assert_eq!(value, ", $swap_op, ");
+ ```
+ 
+ When starting from a slice rather than an array, fallible conversion APIs can be used:
+ 
+ ```
+ use std::convert::TryInto;
+ 
+ fn read_ne_", stringify!($SelfT), "(input: &mut &[u8]) -> ", stringify!($SelfT), " {
+     let (int_bytes, rest) = input.split_at(std::mem::size_of::<", stringify!($SelfT), ">());
+     *input = rest;
+     ", stringify!($SelfT), "::from_ne_bytes(int_bytes.try_into().unwrap())
+ }
+ ```"),
+             #[stable(feature = "int_to_from_bytes", since = "1.32.0")]
+             #[rustc_const_stable(feature = "const_int_conversion", since = "1.44.0")]
+             // SAFETY: const sound because integers are plain old datatypes so we can always
+             // transmute to them
+             #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_transmute))]
+             #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_transmute))]
+             #[inline]
+             pub const fn from_ne_bytes(bytes: [u8; mem::size_of::<Self>()]) -> Self {
+                 // SAFETY: integers are plain old datatypes so we can always transmute to them
+                 unsafe { mem::transmute(bytes) }
+             }
+         }
+ 
+         doc_comment! {
+             concat!("**This method is soft-deprecated.**
+ 
+ Although using it won’t cause compilation warning,
+ new code should use [`", stringify!($SelfT), "::MIN", "`](#associatedconstant.MIN) instead.
+ 
+ Returns the smallest value that can be represented by this integer type."),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_promotable]
+             #[inline(always)]
+             #[rustc_const_stable(feature = "const_max_value", since = "1.32.0")]
+             pub const fn min_value() -> Self { Self::MIN }
+         }
+ 
+         doc_comment! {
+             concat!("**This method is soft-deprecated.**
+ 
+ Although using it won’t cause compilation warning,
+ new code should use [`", stringify!($SelfT), "::MAX", "`](#associatedconstant.MAX) instead.
+ 
+ Returns the largest value that can be represented by this integer type."),
+             #[stable(feature = "rust1", since = "1.0.0")]
+             #[rustc_promotable]
+             #[inline(always)]
+             #[rustc_const_stable(feature = "const_max_value", since = "1.32.0")]
+             pub const fn max_value() -> Self { Self::MAX }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/num/wrapping.rs gcc-16-20251102/libgrust/rustc-lib/core/src/num/wrapping.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/num/wrapping.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/num/wrapping.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,999 ----
+ //! Definitions of `Wrapping<T>`.
+ 
+ use crate::fmt;
+ use crate::ops::{Add, AddAssign, BitAnd, BitAndAssign, BitOr, BitOrAssign};
+ use crate::ops::{BitXor, BitXorAssign, Div, DivAssign};
+ use crate::ops::{Mul, MulAssign, Neg, Not, Rem, RemAssign};
+ use crate::ops::{Shl, ShlAssign, Shr, ShrAssign, Sub, SubAssign};
+ 
+ /// Provides intentionally-wrapped arithmetic on `T`.
+ ///
+ /// Operations like `+` on `u32` values are intended to never overflow,
+ /// and in some debug configurations overflow is detected and results
+ /// in a panic. While most arithmetic falls into this category, some
+ /// code explicitly expects and relies upon modular arithmetic (e.g.,
+ /// hashing).
+ ///
+ /// Wrapping arithmetic can be achieved either through methods like
+ /// `wrapping_add`, or through the `Wrapping<T>` type, which says that
+ /// all standard arithmetic operations on the underlying value are
+ /// intended to have wrapping semantics.
+ ///
+ /// The underlying value can be retrieved through the `.0` index of the
+ /// `Wrapping` tuple.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::num::Wrapping;
+ ///
+ /// let zero = Wrapping(0u32);
+ /// let one = Wrapping(1u32);
+ ///
+ /// assert_eq!(u32::MAX, (zero - one).0);
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(PartialEq, Eq, PartialOrd, Ord, Clone, Copy, Default, Hash)]
+ #[repr(transparent)]
+ pub struct Wrapping<T>(#[stable(feature = "rust1", since = "1.0.0")] pub T);
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: fmt::Debug> fmt::Debug for Wrapping<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.0.fmt(f)
+     }
+ }
+ 
+ #[stable(feature = "wrapping_display", since = "1.10.0")]
+ impl<T: fmt::Display> fmt::Display for Wrapping<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.0.fmt(f)
+     }
+ }
+ 
+ #[stable(feature = "wrapping_fmt", since = "1.11.0")]
+ impl<T: fmt::Binary> fmt::Binary for Wrapping<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.0.fmt(f)
+     }
+ }
+ 
+ #[stable(feature = "wrapping_fmt", since = "1.11.0")]
+ impl<T: fmt::Octal> fmt::Octal for Wrapping<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.0.fmt(f)
+     }
+ }
+ 
+ #[stable(feature = "wrapping_fmt", since = "1.11.0")]
+ impl<T: fmt::LowerHex> fmt::LowerHex for Wrapping<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.0.fmt(f)
+     }
+ }
+ 
+ #[stable(feature = "wrapping_fmt", since = "1.11.0")]
+ impl<T: fmt::UpperHex> fmt::UpperHex for Wrapping<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.0.fmt(f)
+     }
+ }
+ 
+ #[allow(unused_macros)]
+ macro_rules! sh_impl_signed {
+     ($t:ident, $f:ident) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Shl<$f> for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn shl(self, other: $f) -> Wrapping<$t> {
+                 if other < 0 {
+                     Wrapping(self.0.wrapping_shr((-other & self::shift_max::$t as $f) as u32))
+                 } else {
+                     Wrapping(self.0.wrapping_shl((other & self::shift_max::$t as $f) as u32))
+                 }
+             }
+         }
+         forward_ref_binop! { impl Shl, shl for Wrapping<$t>, $f,
+         #[stable(feature = "wrapping_ref_ops", since = "1.39.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl ShlAssign<$f> for Wrapping<$t> {
+             #[inline]
+             fn shl_assign(&mut self, other: $f) {
+                 *self = *self << other;
+             }
+         }
+         forward_ref_op_assign! { impl ShlAssign, shl_assign for Wrapping<$t>, $f }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Shr<$f> for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn shr(self, other: $f) -> Wrapping<$t> {
+                 if other < 0 {
+                     Wrapping(self.0.wrapping_shl((-other & self::shift_max::$t as $f) as u32))
+                 } else {
+                     Wrapping(self.0.wrapping_shr((other & self::shift_max::$t as $f) as u32))
+                 }
+             }
+         }
+         forward_ref_binop! { impl Shr, shr for Wrapping<$t>, $f,
+         #[stable(feature = "wrapping_ref_ops", since = "1.39.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl ShrAssign<$f> for Wrapping<$t> {
+             #[inline]
+             fn shr_assign(&mut self, other: $f) {
+                 *self = *self >> other;
+             }
+         }
+         forward_ref_op_assign! { impl ShrAssign, shr_assign for Wrapping<$t>, $f }
+     };
+ }
+ 
+ macro_rules! sh_impl_unsigned {
+     ($t:ident, $f:ident) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Shl<$f> for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn shl(self, other: $f) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_shl((other & self::shift_max::$t as $f) as u32))
+             }
+         }
+         forward_ref_binop! { impl Shl, shl for Wrapping<$t>, $f,
+         #[stable(feature = "wrapping_ref_ops", since = "1.39.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl ShlAssign<$f> for Wrapping<$t> {
+             #[inline]
+             fn shl_assign(&mut self, other: $f) {
+                 *self = *self << other;
+             }
+         }
+         forward_ref_op_assign! { impl ShlAssign, shl_assign for Wrapping<$t>, $f }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Shr<$f> for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn shr(self, other: $f) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_shr((other & self::shift_max::$t as $f) as u32))
+             }
+         }
+         forward_ref_binop! { impl Shr, shr for Wrapping<$t>, $f,
+         #[stable(feature = "wrapping_ref_ops", since = "1.39.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl ShrAssign<$f> for Wrapping<$t> {
+             #[inline]
+             fn shr_assign(&mut self, other: $f) {
+                 *self = *self >> other;
+             }
+         }
+         forward_ref_op_assign! { impl ShrAssign, shr_assign for Wrapping<$t>, $f }
+     };
+ }
+ 
+ // FIXME (#23545): uncomment the remaining impls
+ macro_rules! sh_impl_all {
+     ($($t:ident)*) => ($(
+         //sh_impl_unsigned! { $t, u8 }
+         //sh_impl_unsigned! { $t, u16 }
+         //sh_impl_unsigned! { $t, u32 }
+         //sh_impl_unsigned! { $t, u64 }
+         //sh_impl_unsigned! { $t, u128 }
+         sh_impl_unsigned! { $t, usize }
+ 
+         //sh_impl_signed! { $t, i8 }
+         //sh_impl_signed! { $t, i16 }
+         //sh_impl_signed! { $t, i32 }
+         //sh_impl_signed! { $t, i64 }
+         //sh_impl_signed! { $t, i128 }
+         //sh_impl_signed! { $t, isize }
+     )*)
+ }
+ 
+ sh_impl_all! { u8 u16 u32 u64 u128 usize i8 i16 i32 i64 i128 isize }
+ 
+ // FIXME(30524): impl Op<T> for Wrapping<T>, impl OpAssign<T> for Wrapping<T>
+ macro_rules! wrapping_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Add for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn add(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_add(other.0))
+             }
+         }
+         forward_ref_binop! { impl Add, add for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl AddAssign for Wrapping<$t> {
+             #[inline]
+             fn add_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self + other;
+             }
+         }
+         forward_ref_op_assign! { impl AddAssign, add_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Sub for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn sub(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_sub(other.0))
+             }
+         }
+         forward_ref_binop! { impl Sub, sub for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl SubAssign for Wrapping<$t> {
+             #[inline]
+             fn sub_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self - other;
+             }
+         }
+         forward_ref_op_assign! { impl SubAssign, sub_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Mul for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn mul(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_mul(other.0))
+             }
+         }
+         forward_ref_binop! { impl Mul, mul for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl MulAssign for Wrapping<$t> {
+             #[inline]
+             fn mul_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self * other;
+             }
+         }
+         forward_ref_op_assign! { impl MulAssign, mul_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "wrapping_div", since = "1.3.0")]
+         impl Div for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn div(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_div(other.0))
+             }
+         }
+         forward_ref_binop! { impl Div, div for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl DivAssign for Wrapping<$t> {
+             #[inline]
+             fn div_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self / other;
+             }
+         }
+         forward_ref_op_assign! { impl DivAssign, div_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "wrapping_impls", since = "1.7.0")]
+         impl Rem for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn rem(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0.wrapping_rem(other.0))
+             }
+         }
+         forward_ref_binop! { impl Rem, rem for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl RemAssign for Wrapping<$t> {
+             #[inline]
+             fn rem_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self % other;
+             }
+         }
+         forward_ref_op_assign! { impl RemAssign, rem_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Not for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn not(self) -> Wrapping<$t> {
+                 Wrapping(!self.0)
+             }
+         }
+         forward_ref_unop! { impl Not, not for Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl BitXor for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn bitxor(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0 ^ other.0)
+             }
+         }
+         forward_ref_binop! { impl BitXor, bitxor for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl BitXorAssign for Wrapping<$t> {
+             #[inline]
+             fn bitxor_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self ^ other;
+             }
+         }
+         forward_ref_op_assign! { impl BitXorAssign, bitxor_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl BitOr for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn bitor(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0 | other.0)
+             }
+         }
+         forward_ref_binop! { impl BitOr, bitor for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl BitOrAssign for Wrapping<$t> {
+             #[inline]
+             fn bitor_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self | other;
+             }
+         }
+         forward_ref_op_assign! { impl BitOrAssign, bitor_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl BitAnd for Wrapping<$t> {
+             type Output = Wrapping<$t>;
+ 
+             #[inline]
+             fn bitand(self, other: Wrapping<$t>) -> Wrapping<$t> {
+                 Wrapping(self.0 & other.0)
+             }
+         }
+         forward_ref_binop! { impl BitAnd, bitand for Wrapping<$t>, Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl BitAndAssign for Wrapping<$t> {
+             #[inline]
+             fn bitand_assign(&mut self, other: Wrapping<$t>) {
+                 *self = *self & other;
+             }
+         }
+         forward_ref_op_assign! { impl BitAndAssign, bitand_assign for Wrapping<$t>, Wrapping<$t> }
+ 
+         #[stable(feature = "wrapping_neg", since = "1.10.0")]
+         impl Neg for Wrapping<$t> {
+             type Output = Self;
+             #[inline]
+             fn neg(self) -> Self {
+                 Wrapping(0) - self
+             }
+         }
+         forward_ref_unop! { impl Neg, neg for Wrapping<$t>,
+                 #[stable(feature = "wrapping_ref", since = "1.14.0")] }
+ 
+     )*)
+ }
+ 
+ wrapping_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ macro_rules! wrapping_int_impl {
+     ($($t:ty)*) => ($(
+         impl Wrapping<$t> {
+             doc_comment! {
+                 concat!("Returns the smallest value that can be represented by this integer type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(<Wrapping<", stringify!($t), ">>::MIN, Wrapping(", stringify!($t), "::MIN));
+ ```"),
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const MIN: Self = Self(<$t>::MIN);
+             }
+ 
+             doc_comment! {
+                 concat!("Returns the largest value that can be represented by this integer type.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(<Wrapping<", stringify!($t), ">>::MAX, Wrapping(", stringify!($t), "::MAX));
+ ```"),
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const MAX: Self = Self(<$t>::MAX);
+             }
+ 
+             doc_comment! {
+                 concat!("Returns the number of ones in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(0b01001100", stringify!($t), ");
+ 
+ assert_eq!(n.count_ones(), 3);
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn count_ones(self) -> u32 {
+                     self.0.count_ones()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns the number of zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(Wrapping(!0", stringify!($t), ").count_zeros(), 0);
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn count_zeros(self) -> u32 {
+                     self.0.count_zeros()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns the number of trailing zeros in the binary representation
+ of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(0b0101000", stringify!($t), ");
+ 
+ assert_eq!(n.trailing_zeros(), 3);
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn trailing_zeros(self) -> u32 {
+                     self.0.trailing_zeros()
+                 }
+             }
+ 
+             /// Shifts the bits to the left by a specified amount, `n`,
+             /// wrapping the truncated bits to the end of the resulting
+             /// integer.
+             ///
+             /// Please note this isn't the same operation as the `<<` shifting
+             /// operator!
+             ///
+             /// # Examples
+             ///
+             /// Basic usage:
+             ///
+             /// ```
+             /// #![feature(wrapping_int_impl)]
+             /// use std::num::Wrapping;
+             ///
+             /// let n: Wrapping<i64> = Wrapping(0x0123456789ABCDEF);
+             /// let m: Wrapping<i64> = Wrapping(-0x76543210FEDCBA99);
+             ///
+             /// assert_eq!(n.rotate_left(32), m);
+             /// ```
+             #[inline]
+             #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+             pub const fn rotate_left(self, n: u32) -> Self {
+                 Wrapping(self.0.rotate_left(n))
+             }
+ 
+             /// Shifts the bits to the right by a specified amount, `n`,
+             /// wrapping the truncated bits to the beginning of the resulting
+             /// integer.
+             ///
+             /// Please note this isn't the same operation as the `>>` shifting
+             /// operator!
+             ///
+             /// # Examples
+             ///
+             /// Basic usage:
+             ///
+             /// ```
+             /// #![feature(wrapping_int_impl)]
+             /// use std::num::Wrapping;
+             ///
+             /// let n: Wrapping<i64> = Wrapping(0x0123456789ABCDEF);
+             /// let m: Wrapping<i64> = Wrapping(-0xFEDCBA987654322);
+             ///
+             /// assert_eq!(n.rotate_right(4), m);
+             /// ```
+             #[inline]
+             #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+             pub const fn rotate_right(self, n: u32) -> Self {
+                 Wrapping(self.0.rotate_right(n))
+             }
+ 
+             /// Reverses the byte order of the integer.
+             ///
+             /// # Examples
+             ///
+             /// Basic usage:
+             ///
+             /// ```
+             /// #![feature(wrapping_int_impl)]
+             /// use std::num::Wrapping;
+             ///
+             /// let n: Wrapping<i16> = Wrapping(0b0000000_01010101);
+             /// assert_eq!(n, Wrapping(85));
+             ///
+             /// let m = n.swap_bytes();
+             ///
+             /// assert_eq!(m, Wrapping(0b01010101_00000000));
+             /// assert_eq!(m, Wrapping(21760));
+             /// ```
+             #[inline]
+             #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+             pub const fn swap_bytes(self) -> Self {
+                 Wrapping(self.0.swap_bytes())
+             }
+ 
+             /// Reverses the bit pattern of the integer.
+             ///
+             /// # Examples
+             ///
+             /// Please note that this example is shared between integer types.
+             /// Which explains why `i16` is used here.
+             ///
+             /// Basic usage:
+             ///
+             /// ```
+             /// use std::num::Wrapping;
+             ///
+             /// let n = Wrapping(0b0000000_01010101i16);
+             /// assert_eq!(n, Wrapping(85));
+             ///
+             /// let m = n.reverse_bits();
+             ///
+             /// assert_eq!(m.0 as u16, 0b10101010_00000000);
+             /// assert_eq!(m, Wrapping(-22016));
+             /// ```
+             #[stable(feature = "reverse_bits", since = "1.37.0")]
+             #[rustc_const_stable(feature = "const_reverse_bits", since = "1.37.0")]
+             #[inline]
+             #[must_use]
+             pub const fn reverse_bits(self) -> Self {
+                 Wrapping(self.0.reverse_bits())
+             }
+ 
+             doc_comment! {
+                 concat!("Converts an integer from big endian to the target's endianness.
+ 
+ On big endian this is a no-op. On little endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(0x1A", stringify!($t), ");
+ 
+ if cfg!(target_endian = \"big\") {
+     assert_eq!(<Wrapping<", stringify!($t), ">>::from_be(n), n)
+ } else {
+     assert_eq!(<Wrapping<", stringify!($t), ">>::from_be(n), n.swap_bytes())
+ }
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn from_be(x: Self) -> Self {
+                     Wrapping(<$t>::from_be(x.0))
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Converts an integer from little endian to the target's endianness.
+ 
+ On little endian this is a no-op. On big endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(0x1A", stringify!($t), ");
+ 
+ if cfg!(target_endian = \"little\") {
+     assert_eq!(<Wrapping<", stringify!($t), ">>::from_le(n), n)
+ } else {
+     assert_eq!(<Wrapping<", stringify!($t), ">>::from_le(n), n.swap_bytes())
+ }
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn from_le(x: Self) -> Self {
+                     Wrapping(<$t>::from_le(x.0))
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Converts `self` to big endian from the target's endianness.
+ 
+ On big endian this is a no-op. On little endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(0x1A", stringify!($t), ");
+ 
+ if cfg!(target_endian = \"big\") {
+     assert_eq!(n.to_be(), n)
+ } else {
+     assert_eq!(n.to_be(), n.swap_bytes())
+ }
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn to_be(self) -> Self {
+                     Wrapping(self.0.to_be())
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Converts `self` to little endian from the target's endianness.
+ 
+ On little endian this is a no-op. On big endian the bytes are
+ swapped.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(0x1A", stringify!($t), ");
+ 
+ if cfg!(target_endian = \"little\") {
+     assert_eq!(n.to_le(), n)
+ } else {
+     assert_eq!(n.to_le(), n.swap_bytes())
+ }
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn to_le(self) -> Self {
+                     Wrapping(self.0.to_le())
+                 }
+             }
+ 
+         doc_comment! {
+             concat!("Raises self to the power of `exp`, using exponentiation by squaring.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(Wrapping(3", stringify!($t), ").pow(4), Wrapping(81));
+ ```
+ 
+ Results that are too large are wrapped:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(Wrapping(3i8).pow(5), Wrapping(-13));
+ assert_eq!(Wrapping(3i8).pow(6), Wrapping(-39));
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub fn pow(self, exp: u32) -> Self {
+                     Wrapping(self.0.wrapping_pow(exp))
+                 }
+             }
+         }
+     )*)
+ }
+ 
+ wrapping_int_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ macro_rules! wrapping_int_impl_signed {
+     ($($t:ty)*) => ($(
+         impl Wrapping<$t> {
+             doc_comment! {
+                 concat!("Returns the number of leading zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(", stringify!($t), "::MAX) >> 2;
+ 
+ assert_eq!(n.leading_zeros(), 3);
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn leading_zeros(self) -> u32 {
+                     self.0.leading_zeros()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Computes the absolute value of `self`, wrapping around at
+ the boundary of the type.
+ 
+ The only case where such wrapping can occur is when one takes the absolute value of the negative
+ minimal value for the type this is a positive value that is too large to represent in the type. In
+ such a case, this function returns `MIN` itself.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(Wrapping(100", stringify!($t), ").abs(), Wrapping(100));
+ assert_eq!(Wrapping(-100", stringify!($t), ").abs(), Wrapping(100));
+ assert_eq!(Wrapping(", stringify!($t), "::MIN).abs(), Wrapping(", stringify!($t), "::MIN));
+ assert_eq!(Wrapping(-128i8).abs().0 as u8, 128u8);
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub fn abs(self) -> Wrapping<$t> {
+                     Wrapping(self.0.wrapping_abs())
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns a number representing sign of `self`.
+ 
+  - `0` if the number is zero
+  - `1` if the number is positive
+  - `-1` if the number is negative
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(Wrapping(10", stringify!($t), ").signum(), Wrapping(1));
+ assert_eq!(Wrapping(0", stringify!($t), ").signum(), Wrapping(0));
+ assert_eq!(Wrapping(-10", stringify!($t), ").signum(), Wrapping(-1));
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub fn signum(self) -> Wrapping<$t> {
+                     Wrapping(self.0.signum())
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns `true` if `self` is positive and `false` if the number is zero or
+ negative.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert!(Wrapping(10", stringify!($t), ").is_positive());
+ assert!(!Wrapping(-10", stringify!($t), ").is_positive());
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn is_positive(self) -> bool {
+                     self.0.is_positive()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns `true` if `self` is negative and `false` if the number is zero or
+ positive.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert!(Wrapping(-10", stringify!($t), ").is_negative());
+ assert!(!Wrapping(10", stringify!($t), ").is_negative());
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn is_negative(self) -> bool {
+                     self.0.is_negative()
+                 }
+             }
+         }
+     )*)
+ }
+ 
+ wrapping_int_impl_signed! { isize i8 i16 i32 i64 i128 }
+ 
+ macro_rules! wrapping_int_impl_unsigned {
+     ($($t:ty)*) => ($(
+         impl Wrapping<$t> {
+             doc_comment! {
+                 concat!("Returns the number of leading zeros in the binary representation of `self`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ let n = Wrapping(", stringify!($t), "::MAX) >> 2;
+ 
+ assert_eq!(n.leading_zeros(), 2);
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub const fn leading_zeros(self) -> u32 {
+                     self.0.leading_zeros()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns `true` if and only if `self == 2^k` for some `k`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_int_impl)]
+ use std::num::Wrapping;
+ 
+ assert!(Wrapping(16", stringify!($t), ").is_power_of_two());
+ assert!(!Wrapping(10", stringify!($t), ").is_power_of_two());
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_int_impl", issue = "32463")]
+                 pub fn is_power_of_two(self) -> bool {
+                     self.0.is_power_of_two()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns the smallest power of two greater than or equal to `self`.
+ 
+ When return value overflows (i.e., `self > (1 << (N-1))` for type
+ `uN`), overflows to `2^N = 0`.
+ 
+ # Examples
+ 
+ Basic usage:
+ 
+ ```
+ #![feature(wrapping_next_power_of_two)]
+ use std::num::Wrapping;
+ 
+ assert_eq!(Wrapping(2", stringify!($t), ").next_power_of_two(), Wrapping(2));
+ assert_eq!(Wrapping(3", stringify!($t), ").next_power_of_two(), Wrapping(4));
+ assert_eq!(Wrapping(200_u8).next_power_of_two(), Wrapping(0));
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "wrapping_next_power_of_two", issue = "32463",
+                            reason = "needs decision on wrapping behaviour")]
+                 pub fn next_power_of_two(self) -> Self {
+                     Wrapping(self.0.wrapping_next_power_of_two())
+                 }
+             }
+         }
+     )*)
+ }
+ 
+ wrapping_int_impl_unsigned! { usize u8 u16 u32 u64 u128 }
+ 
+ mod shift_max {
+     #![allow(non_upper_case_globals)]
+ 
+     #[cfg(target_pointer_width = "16")]
+     mod platform {
+         pub const usize: u32 = super::u16;
+         pub const isize: u32 = super::i16;
+     }
+ 
+     #[cfg(target_pointer_width = "32")]
+     mod platform {
+         pub const usize: u32 = super::u32;
+         pub const isize: u32 = super::i32;
+     }
+ 
+     #[cfg(target_pointer_width = "64")]
+     mod platform {
+         pub const usize: u32 = super::u64;
+         pub const isize: u32 = super::i64;
+     }
+ 
+     pub const i8: u32 = (1 << 3) - 1;
+     pub const i16: u32 = (1 << 4) - 1;
+     pub const i32: u32 = (1 << 5) - 1;
+     pub const i64: u32 = (1 << 6) - 1;
+     pub const i128: u32 = (1 << 7) - 1;
+     pub use self::platform::isize;
+ 
+     pub const u8: u32 = i8;
+     pub const u16: u32 = i16;
+     pub const u32: u32 = i32;
+     pub const u64: u32 = i64;
+     pub const u128: u32 = i128;
+     pub use self::platform::usize;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/arith.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/arith.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/arith.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/arith.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,977 ----
+ /// The addition operator `+`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory. For
+ /// example, [`std::time::SystemTime`] implements `Add<Duration>`, which permits
+ /// operations of the form `SystemTime = SystemTime + Duration`.
+ ///
+ /// [`std::time::SystemTime`]: ../../std/time/struct.SystemTime.html
+ ///
+ /// # Examples
+ ///
+ /// ## `Add`able points
+ ///
+ /// ```
+ /// use std::ops::Add;
+ ///
+ /// #[derive(Debug, Copy, Clone, PartialEq)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// impl Add for Point {
+ ///     type Output = Self;
+ ///
+ ///     fn add(self, other: Self) -> Self {
+ ///         Self {
+ ///             x: self.x + other.x,
+ ///             y: self.y + other.y,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Point { x: 1, y: 0 } + Point { x: 2, y: 3 },
+ ///            Point { x: 3, y: 3 });
+ /// ```
+ ///
+ /// ## Implementing `Add` with generics
+ ///
+ /// Here is an example of the same `Point` struct implementing the `Add` trait
+ /// using generics.
+ ///
+ /// ```
+ /// use std::ops::Add;
+ ///
+ /// #[derive(Debug, Copy, Clone, PartialEq)]
+ /// struct Point<T> {
+ ///     x: T,
+ ///     y: T,
+ /// }
+ ///
+ /// // Notice that the implementation uses the associated type `Output`.
+ /// impl<T: Add<Output = T>> Add for Point<T> {
+ ///     type Output = Self;
+ ///
+ ///     fn add(self, other: Self) -> Self::Output {
+ ///         Self {
+ ///             x: self.x + other.x,
+ ///             y: self.y + other.y,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Point { x: 1, y: 0 } + Point { x: 2, y: 3 },
+ ///            Point { x: 3, y: 3 });
+ /// ```
+ #[lang = "add"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     on(all(_Self = "{integer}", Rhs = "{float}"), message = "cannot add a float to an integer",),
+     on(all(_Self = "{float}", Rhs = "{integer}"), message = "cannot add an integer to a float",),
+     message = "cannot add `{Rhs}` to `{Self}`",
+     label = "no implementation for `{Self} + {Rhs}`"
+ )]
+ #[doc(alias = "+")]
+ pub trait Add<Rhs = Self> {
+     /// The resulting type after applying the `+` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `+` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// assert_eq!(12 + 1, 13);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn add(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! add_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Add for $t {
+             type Output = $t;
+ 
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn add(self, other: $t) -> $t { self + other }
+         }
+ 
+         forward_ref_binop! { impl Add, add for $t, $t }
+     )*)
+ }
+ 
+ add_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The subtraction operator `-`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory. For
+ /// example, [`std::time::SystemTime`] implements `Sub<Duration>`, which permits
+ /// operations of the form `SystemTime = SystemTime - Duration`.
+ ///
+ /// [`std::time::SystemTime`]: ../../std/time/struct.SystemTime.html
+ ///
+ /// # Examples
+ ///
+ /// ## `Sub`tractable points
+ ///
+ /// ```
+ /// use std::ops::Sub;
+ ///
+ /// #[derive(Debug, Copy, Clone, PartialEq)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// impl Sub for Point {
+ ///     type Output = Self;
+ ///
+ ///     fn sub(self, other: Self) -> Self::Output {
+ ///         Self {
+ ///             x: self.x - other.x,
+ ///             y: self.y - other.y,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Point { x: 3, y: 3 } - Point { x: 2, y: 3 },
+ ///            Point { x: 1, y: 0 });
+ /// ```
+ ///
+ /// ## Implementing `Sub` with generics
+ ///
+ /// Here is an example of the same `Point` struct implementing the `Sub` trait
+ /// using generics.
+ ///
+ /// ```
+ /// use std::ops::Sub;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Point<T> {
+ ///     x: T,
+ ///     y: T,
+ /// }
+ ///
+ /// // Notice that the implementation uses the associated type `Output`.
+ /// impl<T: Sub<Output = T>> Sub for Point<T> {
+ ///     type Output = Self;
+ ///
+ ///     fn sub(self, other: Self) -> Self::Output {
+ ///         Point {
+ ///             x: self.x - other.x,
+ ///             y: self.y - other.y,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Point { x: 2, y: 3 } - Point { x: 1, y: 0 },
+ ///            Point { x: 1, y: 3 });
+ /// ```
+ #[lang = "sub"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot subtract `{Rhs}` from `{Self}`",
+     label = "no implementation for `{Self} - {Rhs}`"
+ )]
+ #[doc(alias = "-")]
+ pub trait Sub<Rhs = Self> {
+     /// The resulting type after applying the `-` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `-` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// assert_eq!(12 - 1, 11);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn sub(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! sub_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Sub for $t {
+             type Output = $t;
+ 
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn sub(self, other: $t) -> $t { self - other }
+         }
+ 
+         forward_ref_binop! { impl Sub, sub for $t, $t }
+     )*)
+ }
+ 
+ sub_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The multiplication operator `*`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory.
+ ///
+ /// # Examples
+ ///
+ /// ## `Mul`tipliable rational numbers
+ ///
+ /// ```
+ /// use std::ops::Mul;
+ ///
+ /// // By the fundamental theorem of arithmetic, rational numbers in lowest
+ /// // terms are unique. So, by keeping `Rational`s in reduced form, we can
+ /// // derive `Eq` and `PartialEq`.
+ /// #[derive(Debug, Eq, PartialEq)]
+ /// struct Rational {
+ ///     numerator: usize,
+ ///     denominator: usize,
+ /// }
+ ///
+ /// impl Rational {
+ ///     fn new(numerator: usize, denominator: usize) -> Self {
+ ///         if denominator == 0 {
+ ///             panic!("Zero is an invalid denominator!");
+ ///         }
+ ///
+ ///         // Reduce to lowest terms by dividing by the greatest common
+ ///         // divisor.
+ ///         let gcd = gcd(numerator, denominator);
+ ///         Self {
+ ///             numerator: numerator / gcd,
+ ///             denominator: denominator / gcd,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// impl Mul for Rational {
+ ///     // The multiplication of rational numbers is a closed operation.
+ ///     type Output = Self;
+ ///
+ ///     fn mul(self, rhs: Self) -> Self {
+ ///         let numerator = self.numerator * rhs.numerator;
+ ///         let denominator = self.denominator * rhs.denominator;
+ ///         Self::new(numerator, denominator)
+ ///     }
+ /// }
+ ///
+ /// // Euclid's two-thousand-year-old algorithm for finding the greatest common
+ /// // divisor.
+ /// fn gcd(x: usize, y: usize) -> usize {
+ ///     let mut x = x;
+ ///     let mut y = y;
+ ///     while y != 0 {
+ ///         let t = y;
+ ///         y = x % y;
+ ///         x = t;
+ ///     }
+ ///     x
+ /// }
+ ///
+ /// assert_eq!(Rational::new(1, 2), Rational::new(2, 4));
+ /// assert_eq!(Rational::new(2, 3) * Rational::new(3, 4),
+ ///            Rational::new(1, 2));
+ /// ```
+ ///
+ /// ## Multiplying vectors by scalars as in linear algebra
+ ///
+ /// ```
+ /// use std::ops::Mul;
+ ///
+ /// struct Scalar { value: usize }
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Vector { value: Vec<usize> }
+ ///
+ /// impl Mul<Scalar> for Vector {
+ ///     type Output = Self;
+ ///
+ ///     fn mul(self, rhs: Scalar) -> Self::Output {
+ ///         Self { value: self.value.iter().map(|v| v * rhs.value).collect() }
+ ///     }
+ /// }
+ ///
+ /// let vector = Vector { value: vec![2, 4, 6] };
+ /// let scalar = Scalar { value: 3 };
+ /// assert_eq!(vector * scalar, Vector { value: vec![6, 12, 18] });
+ /// ```
+ #[lang = "mul"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot multiply `{Self}` by `{Rhs}`",
+     label = "no implementation for `{Self} * {Rhs}`"
+ )]
+ #[doc(alias = "*")]
+ pub trait Mul<Rhs = Self> {
+     /// The resulting type after applying the `*` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `*` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// assert_eq!(12 * 2, 24);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn mul(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! mul_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Mul for $t {
+             type Output = $t;
+ 
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn mul(self, other: $t) -> $t { self * other }
+         }
+ 
+         forward_ref_binop! { impl Mul, mul for $t, $t }
+     )*)
+ }
+ 
+ mul_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The division operator `/`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory.
+ ///
+ /// # Examples
+ ///
+ /// ## `Div`idable rational numbers
+ ///
+ /// ```
+ /// use std::ops::Div;
+ ///
+ /// // By the fundamental theorem of arithmetic, rational numbers in lowest
+ /// // terms are unique. So, by keeping `Rational`s in reduced form, we can
+ /// // derive `Eq` and `PartialEq`.
+ /// #[derive(Debug, Eq, PartialEq)]
+ /// struct Rational {
+ ///     numerator: usize,
+ ///     denominator: usize,
+ /// }
+ ///
+ /// impl Rational {
+ ///     fn new(numerator: usize, denominator: usize) -> Self {
+ ///         if denominator == 0 {
+ ///             panic!("Zero is an invalid denominator!");
+ ///         }
+ ///
+ ///         // Reduce to lowest terms by dividing by the greatest common
+ ///         // divisor.
+ ///         let gcd = gcd(numerator, denominator);
+ ///         Self {
+ ///             numerator: numerator / gcd,
+ ///             denominator: denominator / gcd,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// impl Div for Rational {
+ ///     // The division of rational numbers is a closed operation.
+ ///     type Output = Self;
+ ///
+ ///     fn div(self, rhs: Self) -> Self::Output {
+ ///         if rhs.numerator == 0 {
+ ///             panic!("Cannot divide by zero-valued `Rational`!");
+ ///         }
+ ///
+ ///         let numerator = self.numerator * rhs.denominator;
+ ///         let denominator = self.denominator * rhs.numerator;
+ ///         Self::new(numerator, denominator)
+ ///     }
+ /// }
+ ///
+ /// // Euclid's two-thousand-year-old algorithm for finding the greatest common
+ /// // divisor.
+ /// fn gcd(x: usize, y: usize) -> usize {
+ ///     let mut x = x;
+ ///     let mut y = y;
+ ///     while y != 0 {
+ ///         let t = y;
+ ///         y = x % y;
+ ///         x = t;
+ ///     }
+ ///     x
+ /// }
+ ///
+ /// assert_eq!(Rational::new(1, 2), Rational::new(2, 4));
+ /// assert_eq!(Rational::new(1, 2) / Rational::new(3, 4),
+ ///            Rational::new(2, 3));
+ /// ```
+ ///
+ /// ## Dividing vectors by scalars as in linear algebra
+ ///
+ /// ```
+ /// use std::ops::Div;
+ ///
+ /// struct Scalar { value: f32 }
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Vector { value: Vec<f32> }
+ ///
+ /// impl Div<Scalar> for Vector {
+ ///     type Output = Self;
+ ///
+ ///     fn div(self, rhs: Scalar) -> Self::Output {
+ ///         Self { value: self.value.iter().map(|v| v / rhs.value).collect() }
+ ///     }
+ /// }
+ ///
+ /// let scalar = Scalar { value: 2f32 };
+ /// let vector = Vector { value: vec![2f32, 4f32, 6f32] };
+ /// assert_eq!(vector / scalar, Vector { value: vec![1f32, 2f32, 3f32] });
+ /// ```
+ #[lang = "div"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot divide `{Self}` by `{Rhs}`",
+     label = "no implementation for `{Self} / {Rhs}`"
+ )]
+ #[doc(alias = "/")]
+ pub trait Div<Rhs = Self> {
+     /// The resulting type after applying the `/` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `/` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// assert_eq!(12 / 2, 6);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn div(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! div_impl_integer {
+     ($($t:ty)*) => ($(
+         /// This operation rounds towards zero, truncating any
+         /// fractional part of the exact result.
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Div for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn div(self, other: $t) -> $t { self / other }
+         }
+ 
+         forward_ref_binop! { impl Div, div for $t, $t }
+     )*)
+ }
+ 
+ div_impl_integer! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ macro_rules! div_impl_float {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Div for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn div(self, other: $t) -> $t { self / other }
+         }
+ 
+         forward_ref_binop! { impl Div, div for $t, $t }
+     )*)
+ }
+ 
+ div_impl_float! { f32 f64 }
+ 
+ /// The remainder operator `%`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory.
+ ///
+ /// # Examples
+ ///
+ /// This example implements `Rem` on a `SplitSlice` object. After `Rem` is
+ /// implemented, one can use the `%` operator to find out what the remaining
+ /// elements of the slice would be after splitting it into equal slices of a
+ /// given length.
+ ///
+ /// ```
+ /// use std::ops::Rem;
+ ///
+ /// #[derive(PartialEq, Debug)]
+ /// struct SplitSlice<'a, T: 'a> {
+ ///     slice: &'a [T],
+ /// }
+ ///
+ /// impl<'a, T> Rem<usize> for SplitSlice<'a, T> {
+ ///     type Output = Self;
+ ///
+ ///     fn rem(self, modulus: usize) -> Self::Output {
+ ///         let len = self.slice.len();
+ ///         let rem = len % modulus;
+ ///         let start = len - rem;
+ ///         Self {slice: &self.slice[start..]}
+ ///     }
+ /// }
+ ///
+ /// // If we were to divide &[0, 1, 2, 3, 4, 5, 6, 7] into slices of size 3,
+ /// // the remainder would be &[6, 7].
+ /// assert_eq!(SplitSlice { slice: &[0, 1, 2, 3, 4, 5, 6, 7] } % 3,
+ ///            SplitSlice { slice: &[6, 7] });
+ /// ```
+ #[lang = "rem"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot mod `{Self}` by `{Rhs}`",
+     label = "no implementation for `{Self} % {Rhs}`"
+ )]
+ #[doc(alias = "%")]
+ pub trait Rem<Rhs = Self> {
+     /// The resulting type after applying the `%` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `%` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// assert_eq!(12 % 10, 2);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn rem(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! rem_impl_integer {
+     ($($t:ty)*) => ($(
+         /// This operation satisfies `n % d == n - (n / d) * d`. The
+         /// result has the same sign as the left operand.
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Rem for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn rem(self, other: $t) -> $t { self % other }
+         }
+ 
+         forward_ref_binop! { impl Rem, rem for $t, $t }
+     )*)
+ }
+ 
+ rem_impl_integer! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ macro_rules! rem_impl_float {
+     ($($t:ty)*) => ($(
+ 
+         /// The remainder from the division of two floats.
+         ///
+         /// The remainder has the same sign as the dividend and is computed as:
+         /// `x - (x / y).trunc() * y`.
+         ///
+         /// # Examples
+         /// ```
+         /// let x: f32 = 50.50;
+         /// let y: f32 = 8.125;
+         /// let remainder = x - (x / y).trunc() * y;
+         ///
+         /// // The answer to both operations is 1.75
+         /// assert_eq!(x % y, remainder);
+         /// ```
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Rem for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn rem(self, other: $t) -> $t { self % other }
+         }
+ 
+         forward_ref_binop! { impl Rem, rem for $t, $t }
+     )*)
+ }
+ 
+ rem_impl_float! { f32 f64 }
+ 
+ /// The unary negation operator `-`.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `Neg` for `Sign`, which allows the use of `-` to
+ /// negate its value.
+ ///
+ /// ```
+ /// use std::ops::Neg;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// enum Sign {
+ ///     Negative,
+ ///     Zero,
+ ///     Positive,
+ /// }
+ ///
+ /// impl Neg for Sign {
+ ///     type Output = Self;
+ ///
+ ///     fn neg(self) -> Self::Output {
+ ///         match self {
+ ///             Sign::Negative => Sign::Positive,
+ ///             Sign::Zero => Sign::Zero,
+ ///             Sign::Positive => Sign::Negative,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// // A negative positive is a negative.
+ /// assert_eq!(-Sign::Positive, Sign::Negative);
+ /// // A double negative is a positive.
+ /// assert_eq!(-Sign::Negative, Sign::Positive);
+ /// // Zero is its own negation.
+ /// assert_eq!(-Sign::Zero, Sign::Zero);
+ /// ```
+ #[lang = "neg"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(alias = "-")]
+ pub trait Neg {
+     /// The resulting type after applying the `-` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the unary `-` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// let x: i32 = 12;
+     /// assert_eq!(-x, -12);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn neg(self) -> Self::Output;
+ }
+ 
+ macro_rules! neg_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Neg for $t {
+             type Output = $t;
+ 
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn neg(self) -> $t { -self }
+         }
+ 
+         forward_ref_unop! { impl Neg, neg for $t }
+     )*)
+ }
+ 
+ neg_impl! { isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The addition assignment operator `+=`.
+ ///
+ /// # Examples
+ ///
+ /// This example creates a `Point` struct that implements the `AddAssign`
+ /// trait, and then demonstrates add-assigning to a mutable `Point`.
+ ///
+ /// ```
+ /// use std::ops::AddAssign;
+ ///
+ /// #[derive(Debug, Copy, Clone, PartialEq)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// impl AddAssign for Point {
+ ///     fn add_assign(&mut self, other: Self) {
+ ///         *self = Self {
+ ///             x: self.x + other.x,
+ ///             y: self.y + other.y,
+ ///         };
+ ///     }
+ /// }
+ ///
+ /// let mut point = Point { x: 1, y: 0 };
+ /// point += Point { x: 2, y: 3 };
+ /// assert_eq!(point, Point { x: 3, y: 3 });
+ /// ```
+ #[lang = "add_assign"]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot add-assign `{Rhs}` to `{Self}`",
+     label = "no implementation for `{Self} += {Rhs}`"
+ )]
+ #[doc(alias = "+")]
+ #[doc(alias = "+=")]
+ pub trait AddAssign<Rhs = Self> {
+     /// Performs the `+=` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// let mut x: u32 = 12;
+     /// x += 1;
+     /// assert_eq!(x, 13);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn add_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! add_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl AddAssign for $t {
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn add_assign(&mut self, other: $t) { *self += other }
+         }
+ 
+         forward_ref_op_assign! { impl AddAssign, add_assign for $t, $t }
+     )+)
+ }
+ 
+ add_assign_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The subtraction assignment operator `-=`.
+ ///
+ /// # Examples
+ ///
+ /// This example creates a `Point` struct that implements the `SubAssign`
+ /// trait, and then demonstrates sub-assigning to a mutable `Point`.
+ ///
+ /// ```
+ /// use std::ops::SubAssign;
+ ///
+ /// #[derive(Debug, Copy, Clone, PartialEq)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32,
+ /// }
+ ///
+ /// impl SubAssign for Point {
+ ///     fn sub_assign(&mut self, other: Self) {
+ ///         *self = Self {
+ ///             x: self.x - other.x,
+ ///             y: self.y - other.y,
+ ///         };
+ ///     }
+ /// }
+ ///
+ /// let mut point = Point { x: 3, y: 3 };
+ /// point -= Point { x: 2, y: 3 };
+ /// assert_eq!(point, Point {x: 1, y: 0});
+ /// ```
+ #[lang = "sub_assign"]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot subtract-assign `{Rhs}` from `{Self}`",
+     label = "no implementation for `{Self} -= {Rhs}`"
+ )]
+ #[doc(alias = "-")]
+ #[doc(alias = "-=")]
+ pub trait SubAssign<Rhs = Self> {
+     /// Performs the `-=` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// let mut x: u32 = 12;
+     /// x -= 1;
+     /// assert_eq!(x, 11);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn sub_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! sub_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl SubAssign for $t {
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn sub_assign(&mut self, other: $t) { *self -= other }
+         }
+ 
+         forward_ref_op_assign! { impl SubAssign, sub_assign for $t, $t }
+     )+)
+ }
+ 
+ sub_assign_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The multiplication assignment operator `*=`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ops::MulAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Frequency { hertz: f64 }
+ ///
+ /// impl MulAssign<f64> for Frequency {
+ ///     fn mul_assign(&mut self, rhs: f64) {
+ ///         self.hertz *= rhs;
+ ///     }
+ /// }
+ ///
+ /// let mut frequency = Frequency { hertz: 50.0 };
+ /// frequency *= 4.0;
+ /// assert_eq!(Frequency { hertz: 200.0 }, frequency);
+ /// ```
+ #[lang = "mul_assign"]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot multiply-assign `{Self}` by `{Rhs}`",
+     label = "no implementation for `{Self} *= {Rhs}`"
+ )]
+ #[doc(alias = "*")]
+ #[doc(alias = "*=")]
+ pub trait MulAssign<Rhs = Self> {
+     /// Performs the `*=` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// let mut x: u32 = 12;
+     /// x *= 2;
+     /// assert_eq!(x, 24);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn mul_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! mul_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl MulAssign for $t {
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn mul_assign(&mut self, other: $t) { *self *= other }
+         }
+ 
+         forward_ref_op_assign! { impl MulAssign, mul_assign for $t, $t }
+     )+)
+ }
+ 
+ mul_assign_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The division assignment operator `/=`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ops::DivAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Frequency { hertz: f64 }
+ ///
+ /// impl DivAssign<f64> for Frequency {
+ ///     fn div_assign(&mut self, rhs: f64) {
+ ///         self.hertz /= rhs;
+ ///     }
+ /// }
+ ///
+ /// let mut frequency = Frequency { hertz: 200.0 };
+ /// frequency /= 4.0;
+ /// assert_eq!(Frequency { hertz: 50.0 }, frequency);
+ /// ```
+ #[lang = "div_assign"]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot divide-assign `{Self}` by `{Rhs}`",
+     label = "no implementation for `{Self} /= {Rhs}`"
+ )]
+ #[doc(alias = "/")]
+ #[doc(alias = "/=")]
+ pub trait DivAssign<Rhs = Self> {
+     /// Performs the `/=` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// let mut x: u32 = 12;
+     /// x /= 2;
+     /// assert_eq!(x, 6);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn div_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! div_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl DivAssign for $t {
+             #[inline]
+             fn div_assign(&mut self, other: $t) { *self /= other }
+         }
+ 
+         forward_ref_op_assign! { impl DivAssign, div_assign for $t, $t }
+     )+)
+ }
+ 
+ div_assign_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
+ 
+ /// The remainder assignment operator `%=`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ops::RemAssign;
+ ///
+ /// struct CookieJar { cookies: u32 }
+ ///
+ /// impl RemAssign<u32> for CookieJar {
+ ///     fn rem_assign(&mut self, piles: u32) {
+ ///         self.cookies %= piles;
+ ///     }
+ /// }
+ ///
+ /// let mut jar = CookieJar { cookies: 31 };
+ /// let piles = 4;
+ ///
+ /// println!("Splitting up {} cookies into {} even piles!", jar.cookies, piles);
+ ///
+ /// jar %= piles;
+ ///
+ /// println!("{} cookies remain in the cookie jar!", jar.cookies);
+ /// ```
+ #[lang = "rem_assign"]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "cannot mod-assign `{Self}` by `{Rhs}``",
+     label = "no implementation for `{Self} %= {Rhs}`"
+ )]
+ #[doc(alias = "%")]
+ #[doc(alias = "%=")]
+ pub trait RemAssign<Rhs = Self> {
+     /// Performs the `%=` operation.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// let mut x: u32 = 12;
+     /// x %= 10;
+     /// assert_eq!(x, 2);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn rem_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! rem_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl RemAssign for $t {
+             #[inline]
+             fn rem_assign(&mut self, other: $t) { *self %= other }
+         }
+ 
+         forward_ref_op_assign! { impl RemAssign, rem_assign for $t, $t }
+     )+)
+ }
+ 
+ rem_assign_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/bit.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/bit.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/bit.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/bit.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1021 ----
+ /// The unary logical negation operator `!`.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `Not` for `Answer`, which enables the use of `!` to
+ /// invert its value.
+ ///
+ /// ```
+ /// use std::ops::Not;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// enum Answer {
+ ///     Yes,
+ ///     No,
+ /// }
+ ///
+ /// impl Not for Answer {
+ ///     type Output = Self;
+ ///
+ ///     fn not(self) -> Self::Output {
+ ///         match self {
+ ///             Answer::Yes => Answer::No,
+ ///             Answer::No => Answer::Yes
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(!Answer::Yes, Answer::No);
+ /// assert_eq!(!Answer::No, Answer::Yes);
+ /// ```
+ #[lang = "not"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Not {
+     /// The resulting type after applying the `!` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the unary `!` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(!true, false);
+     /// assert_eq!(!false, true);
+     /// assert_eq!(!1u8, 254);
+     /// assert_eq!(!0u8, 255);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn not(self) -> Self::Output;
+ }
+ 
+ macro_rules! not_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Not for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn not(self) -> $t { !self }
+         }
+ 
+         forward_ref_unop! { impl Not, not for $t }
+     )*)
+ }
+ 
+ not_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The bitwise AND operator `&`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `BitAnd` for a wrapper around `bool`.
+ ///
+ /// ```
+ /// use std::ops::BitAnd;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Scalar(bool);
+ ///
+ /// impl BitAnd for Scalar {
+ ///     type Output = Self;
+ ///
+ ///     // rhs is the "right-hand side" of the expression `a & b`
+ ///     fn bitand(self, rhs: Self) -> Self::Output {
+ ///         Self(self.0 & rhs.0)
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Scalar(true) & Scalar(true), Scalar(true));
+ /// assert_eq!(Scalar(true) & Scalar(false), Scalar(false));
+ /// assert_eq!(Scalar(false) & Scalar(true), Scalar(false));
+ /// assert_eq!(Scalar(false) & Scalar(false), Scalar(false));
+ /// ```
+ ///
+ /// An implementation of `BitAnd` for a wrapper around `Vec<bool>`.
+ ///
+ /// ```
+ /// use std::ops::BitAnd;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct BooleanVector(Vec<bool>);
+ ///
+ /// impl BitAnd for BooleanVector {
+ ///     type Output = Self;
+ ///
+ ///     fn bitand(self, Self(rhs): Self) -> Self::Output {
+ ///         let Self(lhs) = self;
+ ///         assert_eq!(lhs.len(), rhs.len());
+ ///         Self(
+ ///             lhs.iter()
+ ///                 .zip(rhs.iter())
+ ///                 .map(|(x, y)| *x & *y)
+ ///                 .collect()
+ ///         )
+ ///     }
+ /// }
+ ///
+ /// let bv1 = BooleanVector(vec![true, true, false, false]);
+ /// let bv2 = BooleanVector(vec![true, false, true, false]);
+ /// let expected = BooleanVector(vec![true, false, false, false]);
+ /// assert_eq!(bv1 & bv2, expected);
+ /// ```
+ #[lang = "bitand"]
+ #[doc(alias = "&")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} & {Rhs}`",
+     label = "no implementation for `{Self} & {Rhs}`"
+ )]
+ pub trait BitAnd<Rhs = Self> {
+     /// The resulting type after applying the `&` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `&` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(true & false, false);
+     /// assert_eq!(true & true, true);
+     /// assert_eq!(5u8 & 1u8, 1);
+     /// assert_eq!(5u8 & 2u8, 0);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn bitand(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! bitand_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl BitAnd for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn bitand(self, rhs: $t) -> $t { self & rhs }
+         }
+ 
+         forward_ref_binop! { impl BitAnd, bitand for $t, $t }
+     )*)
+ }
+ 
+ bitand_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The bitwise OR operator `|`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `BitOr` for a wrapper around `bool`.
+ ///
+ /// ```
+ /// use std::ops::BitOr;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Scalar(bool);
+ ///
+ /// impl BitOr for Scalar {
+ ///     type Output = Self;
+ ///
+ ///     // rhs is the "right-hand side" of the expression `a | b`
+ ///     fn bitor(self, rhs: Self) -> Self::Output {
+ ///         Self(self.0 | rhs.0)
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Scalar(true) | Scalar(true), Scalar(true));
+ /// assert_eq!(Scalar(true) | Scalar(false), Scalar(true));
+ /// assert_eq!(Scalar(false) | Scalar(true), Scalar(true));
+ /// assert_eq!(Scalar(false) | Scalar(false), Scalar(false));
+ /// ```
+ ///
+ /// An implementation of `BitOr` for a wrapper around `Vec<bool>`.
+ ///
+ /// ```
+ /// use std::ops::BitOr;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct BooleanVector(Vec<bool>);
+ ///
+ /// impl BitOr for BooleanVector {
+ ///     type Output = Self;
+ ///
+ ///     fn bitor(self, Self(rhs): Self) -> Self::Output {
+ ///         let Self(lhs) = self;
+ ///         assert_eq!(lhs.len(), rhs.len());
+ ///         Self(
+ ///             lhs.iter()
+ ///                 .zip(rhs.iter())
+ ///                 .map(|(x, y)| *x | *y)
+ ///                 .collect()
+ ///         )
+ ///     }
+ /// }
+ ///
+ /// let bv1 = BooleanVector(vec![true, true, false, false]);
+ /// let bv2 = BooleanVector(vec![true, false, true, false]);
+ /// let expected = BooleanVector(vec![true, true, true, false]);
+ /// assert_eq!(bv1 | bv2, expected);
+ /// ```
+ #[lang = "bitor"]
+ #[doc(alias = "|")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} | {Rhs}`",
+     label = "no implementation for `{Self} | {Rhs}`"
+ )]
+ pub trait BitOr<Rhs = Self> {
+     /// The resulting type after applying the `|` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `|` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(true | false, true);
+     /// assert_eq!(false | false, false);
+     /// assert_eq!(5u8 | 1u8, 5);
+     /// assert_eq!(5u8 | 2u8, 7);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn bitor(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! bitor_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl BitOr for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn bitor(self, rhs: $t) -> $t { self | rhs }
+         }
+ 
+         forward_ref_binop! { impl BitOr, bitor for $t, $t }
+     )*)
+ }
+ 
+ bitor_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The bitwise XOR operator `^`.
+ ///
+ /// Note that `Rhs` is `Self` by default, but this is not mandatory.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `BitXor` that lifts `^` to a wrapper around `bool`.
+ ///
+ /// ```
+ /// use std::ops::BitXor;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Scalar(bool);
+ ///
+ /// impl BitXor for Scalar {
+ ///     type Output = Self;
+ ///
+ ///     // rhs is the "right-hand side" of the expression `a ^ b`
+ ///     fn bitxor(self, rhs: Self) -> Self::Output {
+ ///         Self(self.0 ^ rhs.0)
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Scalar(true) ^ Scalar(true), Scalar(false));
+ /// assert_eq!(Scalar(true) ^ Scalar(false), Scalar(true));
+ /// assert_eq!(Scalar(false) ^ Scalar(true), Scalar(true));
+ /// assert_eq!(Scalar(false) ^ Scalar(false), Scalar(false));
+ /// ```
+ ///
+ /// An implementation of `BitXor` trait for a wrapper around `Vec<bool>`.
+ ///
+ /// ```
+ /// use std::ops::BitXor;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct BooleanVector(Vec<bool>);
+ ///
+ /// impl BitXor for BooleanVector {
+ ///     type Output = Self;
+ ///
+ ///     fn bitxor(self, Self(rhs): Self) -> Self::Output {
+ ///         let Self(lhs) = self;
+ ///         assert_eq!(lhs.len(), rhs.len());
+ ///         Self(
+ ///             lhs.iter()
+ ///                 .zip(rhs.iter())
+ ///                 .map(|(x, y)| *x ^ *y)
+ ///                 .collect()
+ ///         )
+ ///     }
+ /// }
+ ///
+ /// let bv1 = BooleanVector(vec![true, true, false, false]);
+ /// let bv2 = BooleanVector(vec![true, false, true, false]);
+ /// let expected = BooleanVector(vec![false, true, true, false]);
+ /// assert_eq!(bv1 ^ bv2, expected);
+ /// ```
+ #[lang = "bitxor"]
+ #[doc(alias = "^")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} ^ {Rhs}`",
+     label = "no implementation for `{Self} ^ {Rhs}`"
+ )]
+ pub trait BitXor<Rhs = Self> {
+     /// The resulting type after applying the `^` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `^` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(true ^ false, true);
+     /// assert_eq!(true ^ true, false);
+     /// assert_eq!(5u8 ^ 1u8, 4);
+     /// assert_eq!(5u8 ^ 2u8, 7);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn bitxor(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! bitxor_impl {
+     ($($t:ty)*) => ($(
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl BitXor for $t {
+             type Output = $t;
+ 
+             #[inline]
+             fn bitxor(self, other: $t) -> $t { self ^ other }
+         }
+ 
+         forward_ref_binop! { impl BitXor, bitxor for $t, $t }
+     )*)
+ }
+ 
+ bitxor_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The left shift operator `<<`. Note that because this trait is implemented
+ /// for all integer types with multiple right-hand-side types, Rust's type
+ /// checker has special handling for `_ << _`, setting the result type for
+ /// integer operations to the type of the left-hand-side operand. This means
+ /// that though `a << b` and `a.shl(b)` are one and the same from an evaluation
+ /// standpoint, they are different when it comes to type inference.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `Shl` that lifts the `<<` operation on integers to a
+ /// wrapper around `usize`.
+ ///
+ /// ```
+ /// use std::ops::Shl;
+ ///
+ /// #[derive(PartialEq, Debug)]
+ /// struct Scalar(usize);
+ ///
+ /// impl Shl<Scalar> for Scalar {
+ ///     type Output = Self;
+ ///
+ ///     fn shl(self, Self(rhs): Self) -> Self::Output {
+ ///         let Self(lhs) = self;
+ ///         Self(lhs << rhs)
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Scalar(4) << Scalar(2), Scalar(16));
+ /// ```
+ ///
+ /// An implementation of `Shl` that spins a vector leftward by a given amount.
+ ///
+ /// ```
+ /// use std::ops::Shl;
+ ///
+ /// #[derive(PartialEq, Debug)]
+ /// struct SpinVector<T: Clone> {
+ ///     vec: Vec<T>,
+ /// }
+ ///
+ /// impl<T: Clone> Shl<usize> for SpinVector<T> {
+ ///     type Output = Self;
+ ///
+ ///     fn shl(self, rhs: usize) -> Self::Output {
+ ///         // Rotate the vector by `rhs` places.
+ ///         let (a, b) = self.vec.split_at(rhs);
+ ///         let mut spun_vector = vec![];
+ ///         spun_vector.extend_from_slice(b);
+ ///         spun_vector.extend_from_slice(a);
+ ///         Self { vec: spun_vector }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(SpinVector { vec: vec![0, 1, 2, 3, 4] } << 2,
+ ///            SpinVector { vec: vec![2, 3, 4, 0, 1] });
+ /// ```
+ #[lang = "shl"]
+ #[doc(alias = "<<")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} << {Rhs}`",
+     label = "no implementation for `{Self} << {Rhs}`"
+ )]
+ pub trait Shl<Rhs = Self> {
+     /// The resulting type after applying the `<<` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `<<` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(5u8 << 1, 10);
+     /// assert_eq!(1u8 << 1, 2);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn shl(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! shl_impl {
+     ($t:ty, $f:ty) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Shl<$f> for $t {
+             type Output = $t;
+ 
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn shl(self, other: $f) -> $t {
+                 self << other
+             }
+         }
+ 
+         forward_ref_binop! { impl Shl, shl for $t, $f }
+     };
+ }
+ 
+ macro_rules! shl_impl_all {
+     ($($t:ty)*) => ($(
+         shl_impl! { $t, u8 }
+         shl_impl! { $t, u16 }
+         shl_impl! { $t, u32 }
+         shl_impl! { $t, u64 }
+         shl_impl! { $t, u128 }
+         shl_impl! { $t, usize }
+ 
+         shl_impl! { $t, i8 }
+         shl_impl! { $t, i16 }
+         shl_impl! { $t, i32 }
+         shl_impl! { $t, i64 }
+         shl_impl! { $t, i128 }
+         shl_impl! { $t, isize }
+     )*)
+ }
+ 
+ shl_impl_all! { u8 u16 u32 u64 u128 usize i8 i16 i32 i64 isize i128 }
+ 
+ /// The right shift operator `>>`. Note that because this trait is implemented
+ /// for all integer types with multiple right-hand-side types, Rust's type
+ /// checker has special handling for `_ >> _`, setting the result type for
+ /// integer operations to the type of the left-hand-side operand. This means
+ /// that though `a >> b` and `a.shr(b)` are one and the same from an evaluation
+ /// standpoint, they are different when it comes to type inference.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `Shr` that lifts the `>>` operation on integers to a
+ /// wrapper around `usize`.
+ ///
+ /// ```
+ /// use std::ops::Shr;
+ ///
+ /// #[derive(PartialEq, Debug)]
+ /// struct Scalar(usize);
+ ///
+ /// impl Shr<Scalar> for Scalar {
+ ///     type Output = Self;
+ ///
+ ///     fn shr(self, Self(rhs): Self) -> Self::Output {
+ ///         let Self(lhs) = self;
+ ///         Self(lhs >> rhs)
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(Scalar(16) >> Scalar(2), Scalar(4));
+ /// ```
+ ///
+ /// An implementation of `Shr` that spins a vector rightward by a given amount.
+ ///
+ /// ```
+ /// use std::ops::Shr;
+ ///
+ /// #[derive(PartialEq, Debug)]
+ /// struct SpinVector<T: Clone> {
+ ///     vec: Vec<T>,
+ /// }
+ ///
+ /// impl<T: Clone> Shr<usize> for SpinVector<T> {
+ ///     type Output = Self;
+ ///
+ ///     fn shr(self, rhs: usize) -> Self::Output {
+ ///         // Rotate the vector by `rhs` places.
+ ///         let (a, b) = self.vec.split_at(self.vec.len() - rhs);
+ ///         let mut spun_vector = vec![];
+ ///         spun_vector.extend_from_slice(b);
+ ///         spun_vector.extend_from_slice(a);
+ ///         Self { vec: spun_vector }
+ ///     }
+ /// }
+ ///
+ /// assert_eq!(SpinVector { vec: vec![0, 1, 2, 3, 4] } >> 2,
+ ///            SpinVector { vec: vec![3, 4, 0, 1, 2] });
+ /// ```
+ #[lang = "shr"]
+ #[doc(alias = ">>")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} >> {Rhs}`",
+     label = "no implementation for `{Self} >> {Rhs}`"
+ )]
+ pub trait Shr<Rhs = Self> {
+     /// The resulting type after applying the `>>` operator.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output;
+ 
+     /// Performs the `>>` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(5u8 >> 1, 2);
+     /// assert_eq!(2u8 >> 1, 1);
+     /// ```
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn shr(self, rhs: Rhs) -> Self::Output;
+ }
+ 
+ macro_rules! shr_impl {
+     ($t:ty, $f:ty) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl Shr<$f> for $t {
+             type Output = $t;
+ 
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn shr(self, other: $f) -> $t {
+                 self >> other
+             }
+         }
+ 
+         forward_ref_binop! { impl Shr, shr for $t, $f }
+     };
+ }
+ 
+ macro_rules! shr_impl_all {
+     ($($t:ty)*) => ($(
+         shr_impl! { $t, u8 }
+         shr_impl! { $t, u16 }
+         shr_impl! { $t, u32 }
+         shr_impl! { $t, u64 }
+         shr_impl! { $t, u128 }
+         shr_impl! { $t, usize }
+ 
+         shr_impl! { $t, i8 }
+         shr_impl! { $t, i16 }
+         shr_impl! { $t, i32 }
+         shr_impl! { $t, i64 }
+         shr_impl! { $t, i128 }
+         shr_impl! { $t, isize }
+     )*)
+ }
+ 
+ shr_impl_all! { u8 u16 u32 u64 u128 usize i8 i16 i32 i64 i128 isize }
+ 
+ /// The bitwise AND assignment operator `&=`.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `BitAndAssign` that lifts the `&=` operator to a
+ /// wrapper around `bool`.
+ ///
+ /// ```
+ /// use std::ops::BitAndAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Scalar(bool);
+ ///
+ /// impl BitAndAssign for Scalar {
+ ///     // rhs is the "right-hand side" of the expression `a &= b`
+ ///     fn bitand_assign(&mut self, rhs: Self) {
+ ///         *self = Self(self.0 & rhs.0)
+ ///     }
+ /// }
+ ///
+ /// let mut scalar = Scalar(true);
+ /// scalar &= Scalar(true);
+ /// assert_eq!(scalar, Scalar(true));
+ ///
+ /// let mut scalar = Scalar(true);
+ /// scalar &= Scalar(false);
+ /// assert_eq!(scalar, Scalar(false));
+ ///
+ /// let mut scalar = Scalar(false);
+ /// scalar &= Scalar(true);
+ /// assert_eq!(scalar, Scalar(false));
+ ///
+ /// let mut scalar = Scalar(false);
+ /// scalar &= Scalar(false);
+ /// assert_eq!(scalar, Scalar(false));
+ /// ```
+ ///
+ /// Here, the `BitAndAssign` trait is implemented for a wrapper around
+ /// `Vec<bool>`.
+ ///
+ /// ```
+ /// use std::ops::BitAndAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct BooleanVector(Vec<bool>);
+ ///
+ /// impl BitAndAssign for BooleanVector {
+ ///     // `rhs` is the "right-hand side" of the expression `a &= b`.
+ ///     fn bitand_assign(&mut self, rhs: Self) {
+ ///         assert_eq!(self.0.len(), rhs.0.len());
+ ///         *self = Self(
+ ///             self.0
+ ///                 .iter()
+ ///                 .zip(rhs.0.iter())
+ ///                 .map(|(x, y)| *x & *y)
+ ///                 .collect()
+ ///         );
+ ///     }
+ /// }
+ ///
+ /// let mut bv = BooleanVector(vec![true, true, false, false]);
+ /// bv &= BooleanVector(vec![true, false, true, false]);
+ /// let expected = BooleanVector(vec![true, false, false, false]);
+ /// assert_eq!(bv, expected);
+ /// ```
+ #[lang = "bitand_assign"]
+ #[doc(alias = "&=")]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} &= {Rhs}`",
+     label = "no implementation for `{Self} &= {Rhs}`"
+ )]
+ pub trait BitAndAssign<Rhs = Self> {
+     /// Performs the `&=` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = true;
+     /// x &= false;
+     /// assert_eq!(x, false);
+     ///
+     /// let mut x = true;
+     /// x &= true;
+     /// assert_eq!(x, true);
+     ///
+     /// let mut x: u8 = 5;
+     /// x &= 1;
+     /// assert_eq!(x, 1);
+     ///
+     /// let mut x: u8 = 5;
+     /// x &= 2;
+     /// assert_eq!(x, 0);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn bitand_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! bitand_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl BitAndAssign for $t {
+             #[inline]
+             fn bitand_assign(&mut self, other: $t) { *self &= other }
+         }
+ 
+         forward_ref_op_assign! { impl BitAndAssign, bitand_assign for $t, $t }
+     )+)
+ }
+ 
+ bitand_assign_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The bitwise OR assignment operator `|=`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ops::BitOrAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct PersonalPreferences {
+ ///     likes_cats: bool,
+ ///     likes_dogs: bool,
+ /// }
+ ///
+ /// impl BitOrAssign for PersonalPreferences {
+ ///     fn bitor_assign(&mut self, rhs: Self) {
+ ///         self.likes_cats |= rhs.likes_cats;
+ ///         self.likes_dogs |= rhs.likes_dogs;
+ ///     }
+ /// }
+ ///
+ /// let mut prefs = PersonalPreferences { likes_cats: true, likes_dogs: false };
+ /// prefs |= PersonalPreferences { likes_cats: false, likes_dogs: true };
+ /// assert_eq!(prefs, PersonalPreferences { likes_cats: true, likes_dogs: true });
+ /// ```
+ #[lang = "bitor_assign"]
+ #[doc(alias = "|=")]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} |= {Rhs}`",
+     label = "no implementation for `{Self} |= {Rhs}`"
+ )]
+ pub trait BitOrAssign<Rhs = Self> {
+     /// Performs the `|=` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = true;
+     /// x |= false;
+     /// assert_eq!(x, true);
+     ///
+     /// let mut x = false;
+     /// x |= false;
+     /// assert_eq!(x, false);
+     ///
+     /// let mut x: u8 = 5;
+     /// x |= 1;
+     /// assert_eq!(x, 5);
+     ///
+     /// let mut x: u8 = 5;
+     /// x |= 2;
+     /// assert_eq!(x, 7);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn bitor_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! bitor_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl BitOrAssign for $t {
+             #[inline]
+             fn bitor_assign(&mut self, other: $t) { *self |= other }
+         }
+ 
+         forward_ref_op_assign! { impl BitOrAssign, bitor_assign for $t, $t }
+     )+)
+ }
+ 
+ bitor_assign_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The bitwise XOR assignment operator `^=`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ops::BitXorAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Personality {
+ ///     has_soul: bool,
+ ///     likes_knitting: bool,
+ /// }
+ ///
+ /// impl BitXorAssign for Personality {
+ ///     fn bitxor_assign(&mut self, rhs: Self) {
+ ///         self.has_soul ^= rhs.has_soul;
+ ///         self.likes_knitting ^= rhs.likes_knitting;
+ ///     }
+ /// }
+ ///
+ /// let mut personality = Personality { has_soul: false, likes_knitting: true };
+ /// personality ^= Personality { has_soul: true, likes_knitting: true };
+ /// assert_eq!(personality, Personality { has_soul: true, likes_knitting: false});
+ /// ```
+ #[lang = "bitxor_assign"]
+ #[doc(alias = "^=")]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} ^= {Rhs}`",
+     label = "no implementation for `{Self} ^= {Rhs}`"
+ )]
+ pub trait BitXorAssign<Rhs = Self> {
+     /// Performs the `^=` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = true;
+     /// x ^= false;
+     /// assert_eq!(x, true);
+     ///
+     /// let mut x = true;
+     /// x ^= true;
+     /// assert_eq!(x, false);
+     ///
+     /// let mut x: u8 = 5;
+     /// x ^= 1;
+     /// assert_eq!(x, 4);
+     ///
+     /// let mut x: u8 = 5;
+     /// x ^= 2;
+     /// assert_eq!(x, 7);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn bitxor_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! bitxor_assign_impl {
+     ($($t:ty)+) => ($(
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl BitXorAssign for $t {
+             #[inline]
+             fn bitxor_assign(&mut self, other: $t) { *self ^= other }
+         }
+ 
+         forward_ref_op_assign! { impl BitXorAssign, bitxor_assign for $t, $t }
+     )+)
+ }
+ 
+ bitxor_assign_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 }
+ 
+ /// The left shift assignment operator `<<=`.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `ShlAssign` for a wrapper around `usize`.
+ ///
+ /// ```
+ /// use std::ops::ShlAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Scalar(usize);
+ ///
+ /// impl ShlAssign<usize> for Scalar {
+ ///     fn shl_assign(&mut self, rhs: usize) {
+ ///         self.0 <<= rhs;
+ ///     }
+ /// }
+ ///
+ /// let mut scalar = Scalar(4);
+ /// scalar <<= 2;
+ /// assert_eq!(scalar, Scalar(16));
+ /// ```
+ #[lang = "shl_assign"]
+ #[doc(alias = "<<=")]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} <<= {Rhs}`",
+     label = "no implementation for `{Self} <<= {Rhs}`"
+ )]
+ pub trait ShlAssign<Rhs = Self> {
+     /// Performs the `<<=` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x: u8 = 5;
+     /// x <<= 1;
+     /// assert_eq!(x, 10);
+     ///
+     /// let mut x: u8 = 1;
+     /// x <<= 1;
+     /// assert_eq!(x, 2);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn shl_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! shl_assign_impl {
+     ($t:ty, $f:ty) => {
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl ShlAssign<$f> for $t {
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn shl_assign(&mut self, other: $f) {
+                 *self <<= other
+             }
+         }
+ 
+         forward_ref_op_assign! { impl ShlAssign, shl_assign for $t, $f }
+     };
+ }
+ 
+ macro_rules! shl_assign_impl_all {
+     ($($t:ty)*) => ($(
+         shl_assign_impl! { $t, u8 }
+         shl_assign_impl! { $t, u16 }
+         shl_assign_impl! { $t, u32 }
+         shl_assign_impl! { $t, u64 }
+         shl_assign_impl! { $t, u128 }
+         shl_assign_impl! { $t, usize }
+ 
+         shl_assign_impl! { $t, i8 }
+         shl_assign_impl! { $t, i16 }
+         shl_assign_impl! { $t, i32 }
+         shl_assign_impl! { $t, i64 }
+         shl_assign_impl! { $t, i128 }
+         shl_assign_impl! { $t, isize }
+     )*)
+ }
+ 
+ shl_assign_impl_all! { u8 u16 u32 u64 u128 usize i8 i16 i32 i64 i128 isize }
+ 
+ /// The right shift assignment operator `>>=`.
+ ///
+ /// # Examples
+ ///
+ /// An implementation of `ShrAssign` for a wrapper around `usize`.
+ ///
+ /// ```
+ /// use std::ops::ShrAssign;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Scalar(usize);
+ ///
+ /// impl ShrAssign<usize> for Scalar {
+ ///     fn shr_assign(&mut self, rhs: usize) {
+ ///         self.0 >>= rhs;
+ ///     }
+ /// }
+ ///
+ /// let mut scalar = Scalar(16);
+ /// scalar >>= 2;
+ /// assert_eq!(scalar, Scalar(4));
+ /// ```
+ #[lang = "shr_assign"]
+ #[doc(alias = ">>=")]
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ #[rustc_on_unimplemented(
+     message = "no implementation for `{Self} >>= {Rhs}`",
+     label = "no implementation for `{Self} >>= {Rhs}`"
+ )]
+ pub trait ShrAssign<Rhs = Self> {
+     /// Performs the `>>=` operation.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x: u8 = 5;
+     /// x >>= 1;
+     /// assert_eq!(x, 2);
+     ///
+     /// let mut x: u8 = 2;
+     /// x >>= 1;
+     /// assert_eq!(x, 1);
+     /// ```
+     #[stable(feature = "op_assign_traits", since = "1.8.0")]
+     fn shr_assign(&mut self, rhs: Rhs);
+ }
+ 
+ macro_rules! shr_assign_impl {
+     ($t:ty, $f:ty) => {
+         #[stable(feature = "op_assign_traits", since = "1.8.0")]
+         impl ShrAssign<$f> for $t {
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn shr_assign(&mut self, other: $f) {
+                 *self >>= other
+             }
+         }
+ 
+         forward_ref_op_assign! { impl ShrAssign, shr_assign for $t, $f }
+     };
+ }
+ 
+ macro_rules! shr_assign_impl_all {
+     ($($t:ty)*) => ($(
+         shr_assign_impl! { $t, u8 }
+         shr_assign_impl! { $t, u16 }
+         shr_assign_impl! { $t, u32 }
+         shr_assign_impl! { $t, u64 }
+         shr_assign_impl! { $t, u128 }
+         shr_assign_impl! { $t, usize }
+ 
+         shr_assign_impl! { $t, i8 }
+         shr_assign_impl! { $t, i16 }
+         shr_assign_impl! { $t, i32 }
+         shr_assign_impl! { $t, i64 }
+         shr_assign_impl! { $t, i128 }
+         shr_assign_impl! { $t, isize }
+     )*)
+ }
+ 
+ shr_assign_impl_all! { u8 u16 u32 u64 u128 usize i8 i16 i32 i64 i128 isize }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/control_flow.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/control_flow.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/control_flow.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/control_flow.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,124 ----
+ use crate::ops::Try;
+ 
+ /// Used to make try_fold closures more like normal loops
+ #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+ #[derive(Debug, Clone, Copy, PartialEq)]
+ pub enum ControlFlow<B, C = ()> {
+     /// Continue in the loop, using the given value for the next iteration
+     Continue(C),
+     /// Exit the loop, yielding the given value
+     Break(B),
+ }
+ 
+ #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+ impl<B, C> Try for ControlFlow<B, C> {
+     type Ok = C;
+     type Error = B;
+     #[inline]
+     fn into_result(self) -> Result<Self::Ok, Self::Error> {
+         match self {
+             ControlFlow::Continue(y) => Ok(y),
+             ControlFlow::Break(x) => Err(x),
+         }
+     }
+     #[inline]
+     fn from_error(v: Self::Error) -> Self {
+         ControlFlow::Break(v)
+     }
+     #[inline]
+     fn from_ok(v: Self::Ok) -> Self {
+         ControlFlow::Continue(v)
+     }
+ }
+ 
+ impl<B, C> ControlFlow<B, C> {
+     /// Returns `true` if this is a `Break` variant.
+     #[inline]
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     pub fn is_break(&self) -> bool {
+         matches!(*self, ControlFlow::Break(_))
+     }
+ 
+     /// Returns `true` if this is a `Continue` variant.
+     #[inline]
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     pub fn is_continue(&self) -> bool {
+         matches!(*self, ControlFlow::Continue(_))
+     }
+ 
+     /// Converts the `ControlFlow` into an `Option` which is `Some` if the
+     /// `ControlFlow` was `Break` and `None` otherwise.
+     #[inline]
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     pub fn break_value(self) -> Option<B> {
+         match self {
+             ControlFlow::Continue(..) => None,
+             ControlFlow::Break(x) => Some(x),
+         }
+     }
+ }
+ 
+ impl<R: Try> ControlFlow<R, R::Ok> {
+     /// Create a `ControlFlow` from any type implementing `Try`.
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     #[inline]
+     pub fn from_try(r: R) -> Self {
+         match Try::into_result(r) {
+             Ok(v) => ControlFlow::Continue(v),
+             Err(v) => ControlFlow::Break(Try::from_error(v)),
+         }
+     }
+ 
+     /// Convert a `ControlFlow` into any type implementing `Try`;
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     #[inline]
+     pub fn into_try(self) -> R {
+         match self {
+             ControlFlow::Continue(v) => Try::from_ok(v),
+             ControlFlow::Break(v) => v,
+         }
+     }
+ }
+ 
+ impl<B> ControlFlow<B, ()> {
+     /// It's frequently the case that there's no value needed with `Continue`,
+     /// so this provides a way to avoid typing `(())`, if you prefer it.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(control_flow_enum)]
+     /// use std::ops::ControlFlow;
+     ///
+     /// let mut partial_sum = 0;
+     /// let last_used = (1..10).chain(20..25).try_for_each(|x| {
+     ///     partial_sum += x;
+     ///     if partial_sum > 100 { ControlFlow::Break(x) }
+     ///     else { ControlFlow::CONTINUE }
+     /// });
+     /// assert_eq!(last_used.break_value(), Some(22));
+     /// ```
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     pub const CONTINUE: Self = ControlFlow::Continue(());
+ }
+ 
+ impl<C> ControlFlow<(), C> {
+     /// APIs like `try_for_each` don't need values with `Break`,
+     /// so this provides a way to avoid typing `(())`, if you prefer it.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(control_flow_enum)]
+     /// use std::ops::ControlFlow;
+     ///
+     /// let mut partial_sum = 0;
+     /// (1..10).chain(20..25).try_for_each(|x| {
+     ///     if partial_sum > 100 { ControlFlow::BREAK }
+     ///     else { partial_sum += x; ControlFlow::CONTINUE }
+     /// });
+     /// assert_eq!(partial_sum, 108);
+     /// ```
+     #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+     pub const BREAK: Self = ControlFlow::Break(());
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/deref.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/deref.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/deref.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/deref.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,194 ----
+ /// Used for immutable dereferencing operations, like `*v`.
+ ///
+ /// In addition to being used for explicit dereferencing operations with the
+ /// (unary) `*` operator in immutable contexts, `Deref` is also used implicitly
+ /// by the compiler in many circumstances. This mechanism is called
+ /// ['`Deref` coercion'][more]. In mutable contexts, [`DerefMut`] is used.
+ ///
+ /// Implementing `Deref` for smart pointers makes accessing the data behind them
+ /// convenient, which is why they implement `Deref`. On the other hand, the
+ /// rules regarding `Deref` and [`DerefMut`] were designed specifically to
+ /// accommodate smart pointers. Because of this, **`Deref` should only be
+ /// implemented for smart pointers** to avoid confusion.
+ ///
+ /// For similar reasons, **this trait should never fail**. Failure during
+ /// dereferencing can be extremely confusing when `Deref` is invoked implicitly.
+ ///
+ /// # More on `Deref` coercion
+ ///
+ /// If `T` implements `Deref<Target = U>`, and `x` is a value of type `T`, then:
+ ///
+ /// * In immutable contexts, `*x` (where `T` is neither a reference nor a raw pointer)
+ ///   is equivalent to `*Deref::deref(&x)`.
+ /// * Values of type `&T` are coerced to values of type `&U`
+ /// * `T` implicitly implements all the (immutable) methods of the type `U`.
+ ///
+ /// For more details, visit [the chapter in *The Rust Programming Language*][book]
+ /// as well as the reference sections on [the dereference operator][ref-deref-op],
+ /// [method resolution] and [type coercions].
+ ///
+ /// [book]: ../../book/ch15-02-deref.html
+ /// [more]: #more-on-deref-coercion
+ /// [ref-deref-op]: ../../reference/expressions/operator-expr.html#the-dereference-operator
+ /// [method resolution]: ../../reference/expressions/method-call-expr.html
+ /// [type coercions]: ../../reference/type-coercions.html
+ ///
+ /// # Examples
+ ///
+ /// A struct with a single field which is accessible by dereferencing the
+ /// struct.
+ ///
+ /// ```
+ /// use std::ops::Deref;
+ ///
+ /// struct DerefExample<T> {
+ ///     value: T
+ /// }
+ ///
+ /// impl<T> Deref for DerefExample<T> {
+ ///     type Target = T;
+ ///
+ ///     fn deref(&self) -> &Self::Target {
+ ///         &self.value
+ ///     }
+ /// }
+ ///
+ /// let x = DerefExample { value: 'a' };
+ /// assert_eq!('a', *x);
+ /// ```
+ #[lang = "deref"]
+ #[doc(alias = "*")]
+ #[doc(alias = "&*")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Deref {
+     /// The resulting type after dereferencing.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_diagnostic_item = "deref_target"]
+     type Target: ?Sized;
+ 
+     /// Dereferences the value.
+     #[must_use]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_diagnostic_item = "deref_method"]
+     fn deref(&self) -> &Self::Target;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Deref for &T {
+     type Target = T;
+ 
+     fn deref(&self) -> &T {
+         *self
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> !DerefMut for &T {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Deref for &mut T {
+     type Target = T;
+ 
+     fn deref(&self) -> &T {
+         *self
+     }
+ }
+ 
+ /// Used for mutable dereferencing operations, like in `*v = 1;`.
+ ///
+ /// In addition to being used for explicit dereferencing operations with the
+ /// (unary) `*` operator in mutable contexts, `DerefMut` is also used implicitly
+ /// by the compiler in many circumstances. This mechanism is called
+ /// ['`Deref` coercion'][more]. In immutable contexts, [`Deref`] is used.
+ ///
+ /// Implementing `DerefMut` for smart pointers makes mutating the data behind
+ /// them convenient, which is why they implement `DerefMut`. On the other hand,
+ /// the rules regarding [`Deref`] and `DerefMut` were designed specifically to
+ /// accommodate smart pointers. Because of this, **`DerefMut` should only be
+ /// implemented for smart pointers** to avoid confusion.
+ ///
+ /// For similar reasons, **this trait should never fail**. Failure during
+ /// dereferencing can be extremely confusing when `DerefMut` is invoked
+ /// implicitly.
+ ///
+ /// # More on `Deref` coercion
+ ///
+ /// If `T` implements `DerefMut<Target = U>`, and `x` is a value of type `T`,
+ /// then:
+ ///
+ /// * In mutable contexts, `*x` (where `T` is neither a reference nor a raw pointer)
+ ///   is equivalent to `*DerefMut::deref_mut(&mut x)`.
+ /// * Values of type `&mut T` are coerced to values of type `&mut U`
+ /// * `T` implicitly implements all the (mutable) methods of the type `U`.
+ ///
+ /// For more details, visit [the chapter in *The Rust Programming Language*][book]
+ /// as well as the reference sections on [the dereference operator][ref-deref-op],
+ /// [method resolution] and [type coercions].
+ ///
+ /// [book]: ../../book/ch15-02-deref.html
+ /// [more]: #more-on-deref-coercion
+ /// [ref-deref-op]: ../../reference/expressions/operator-expr.html#the-dereference-operator
+ /// [method resolution]: ../../reference/expressions/method-call-expr.html
+ /// [type coercions]: ../../reference/type-coercions.html
+ ///
+ /// # Examples
+ ///
+ /// A struct with a single field which is modifiable by dereferencing the
+ /// struct.
+ ///
+ /// ```
+ /// use std::ops::{Deref, DerefMut};
+ ///
+ /// struct DerefMutExample<T> {
+ ///     value: T
+ /// }
+ ///
+ /// impl<T> Deref for DerefMutExample<T> {
+ ///     type Target = T;
+ ///
+ ///     fn deref(&self) -> &Self::Target {
+ ///         &self.value
+ ///     }
+ /// }
+ ///
+ /// impl<T> DerefMut for DerefMutExample<T> {
+ ///     fn deref_mut(&mut self) -> &mut Self::Target {
+ ///         &mut self.value
+ ///     }
+ /// }
+ ///
+ /// let mut x = DerefMutExample { value: 'a' };
+ /// *x = 'b';
+ /// assert_eq!('b', *x);
+ /// ```
+ #[lang = "deref_mut"]
+ #[doc(alias = "*")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait DerefMut: Deref {
+     /// Mutably dereferences the value.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn deref_mut(&mut self) -> &mut Self::Target;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> DerefMut for &mut T {
+     fn deref_mut(&mut self) -> &mut T {
+         *self
+     }
+ }
+ 
+ /// Indicates that a struct can be used as a method receiver, without the
+ /// `arbitrary_self_types` feature. This is implemented by stdlib pointer types like `Box<T>`,
+ /// `Rc<T>`, `&T`, and `Pin<P>`.
+ #[lang = "receiver"]
+ #[unstable(feature = "receiver_trait", issue = "none")]
+ #[doc(hidden)]
+ pub trait Receiver {
+     // Empty.
+ }
+ 
+ #[unstable(feature = "receiver_trait", issue = "none")]
+ impl<T: ?Sized> Receiver for &T {}
+ 
+ #[unstable(feature = "receiver_trait", issue = "none")]
+ impl<T: ?Sized> Receiver for &mut T {}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/drop.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/drop.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/drop.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/drop.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,165 ----
+ /// Custom code within the destructor.
+ ///
+ /// When a value is no longer needed, Rust will run a "destructor" on that value.
+ /// The most common way that a value is no longer needed is when it goes out of
+ /// scope. Destructors may still run in other circumstances, but we're going to
+ /// focus on scope for the examples here. To learn about some of those other cases,
+ /// please see [the reference] section on destructors.
+ ///
+ /// [the reference]: https://doc.rust-lang.org/reference/destructors.html
+ ///
+ /// This destructor consists of two components:
+ /// - A call to `Drop::drop` for that value, if this special `Drop` trait is implemented for its type.
+ /// - The automatically generated "drop glue" which recursively calls the destructors
+ ///     of the all fields of this value.
+ ///
+ /// As Rust automatically calls the destructors of all contained fields,
+ /// you don't have to implement `Drop` in most cases. But there are some cases where
+ /// it is useful, for example for types which directly manage a resource.
+ /// That resource may be memory, it may be a file descriptor, it may be a network socket.
+ /// Once a value of that type is no longer going to be used, it should "clean up" its
+ /// resource by freeing the memory or closing the file or socket. This is
+ /// the job of a destructor, and therefore the job of `Drop::drop`.
+ ///
+ /// ## Examples
+ ///
+ /// To see destructors in action, let's take a look at the following program:
+ ///
+ /// ```rust
+ /// struct HasDrop;
+ ///
+ /// impl Drop for HasDrop {
+ ///     fn drop(&mut self) {
+ ///         println!("Dropping HasDrop!");
+ ///     }
+ /// }
+ ///
+ /// struct HasTwoDrops {
+ ///     one: HasDrop,
+ ///     two: HasDrop,
+ /// }
+ ///
+ /// impl Drop for HasTwoDrops {
+ ///     fn drop(&mut self) {
+ ///         println!("Dropping HasTwoDrops!");
+ ///     }
+ /// }
+ ///
+ /// fn main() {
+ ///     let _x = HasTwoDrops { one: HasDrop, two: HasDrop };
+ ///     println!("Running!");
+ /// }
+ /// ```
+ ///
+ /// Rust will first call `Drop::drop` for `_x` and then for both `_x.one` and `_x.two`,
+ /// meaning that running this will print
+ ///
+ /// ```text
+ /// Running!
+ /// Dropping HasTwoDrops!
+ /// Dropping HasDrop!
+ /// Dropping HasDrop!
+ /// ```
+ ///
+ /// Even if we remove the implementation of `Drop` for `HasTwoDrop`, the destructors of its fields are still called.
+ /// This would result in
+ ///
+ /// ```test
+ /// Running!
+ /// Dropping HasDrop!
+ /// Dropping HasDrop!
+ /// ```
+ ///
+ /// ## You cannot call `Drop::drop` yourself
+ ///
+ /// Because `Drop::drop` is used to clean up a value, it may be dangerous to use this value after
+ /// the method has been called. As `Drop::drop` does not take ownership of its input,
+ /// Rust prevents misuse by not allowing you to call `Drop::drop` directly.
+ ///
+ /// In other words, if you tried to explicitly call `Drop::drop` in the above example, you'd get a compiler error.
+ ///
+ /// If you'd like explicitly call the destructor of a value, [`mem::drop`] can be used instead.
+ ///
+ /// [`mem::drop`]: drop
+ ///
+ /// ## Drop order
+ ///
+ /// Which of our two `HasDrop` drops first, though? For structs, it's the same
+ /// order that they're declared: first `one`, then `two`. If you'd like to try
+ /// this yourself, you can modify `HasDrop` above to contain some data, like an
+ /// integer, and then use it in the `println!` inside of `Drop`. This behavior is
+ /// guaranteed by the language.
+ ///
+ /// Unlike for structs, local variables are dropped in reverse order:
+ ///
+ /// ```rust
+ /// struct Foo;
+ ///
+ /// impl Drop for Foo {
+ ///     fn drop(&mut self) {
+ ///         println!("Dropping Foo!")
+ ///     }
+ /// }
+ ///
+ /// struct Bar;
+ ///
+ /// impl Drop for Bar {
+ ///     fn drop(&mut self) {
+ ///         println!("Dropping Bar!")
+ ///     }
+ /// }
+ ///
+ /// fn main() {
+ ///     let _foo = Foo;
+ ///     let _bar = Bar;
+ /// }
+ /// ```
+ ///
+ /// This will print
+ ///
+ /// ```text
+ /// Dropping Bar!
+ /// Dropping Foo!
+ /// ```
+ ///
+ /// Please see [the reference] for the full rules.
+ ///
+ /// [the reference]: https://doc.rust-lang.org/reference/destructors.html
+ ///
+ /// ## `Copy` and `Drop` are exclusive
+ ///
+ /// You cannot implement both [`Copy`] and `Drop` on the same type. Types that
+ /// are `Copy` get implicitly duplicated by the compiler, making it very
+ /// hard to predict when, and how often destructors will be executed. As such,
+ /// these types cannot have destructors.
+ #[lang = "drop"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait Drop {
+     /// Executes the destructor for this type.
+     ///
+     /// This method is called implicitly when the value goes out of scope,
+     /// and cannot be called explicitly (this is compiler error [E0040]).
+     /// However, the [`mem::drop`] function in the prelude can be
+     /// used to call the argument's `Drop` implementation.
+     ///
+     /// When this method has been called, `self` has not yet been deallocated.
+     /// That only happens after the method is over.
+     /// If this wasn't the case, `self` would be a dangling reference.
+     ///
+     /// # Panics
+     ///
+     /// Given that a [`panic!`] will call `drop` as it unwinds, any [`panic!`]
+     /// in a `drop` implementation will likely abort.
+     ///
+     /// Note that even if this panics, the value is considered to be dropped;
+     /// you must not cause `drop` to be called again. This is normally automatically
+     /// handled by the compiler, but when using unsafe code, can sometimes occur
+     /// unintentionally, particularly when using [`ptr::drop_in_place`].
+     ///
+     /// [E0040]: ../../error-index.html#E0040
+     /// [`panic!`]: crate::panic!
+     /// [`mem::drop`]: drop
+     /// [`ptr::drop_in_place`]: crate::ptr::drop_in_place
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn drop(&mut self);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/function.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/function.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/function.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/function.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,283 ----
+ /// The version of the call operator that takes an immutable receiver.
+ ///
+ /// Instances of `Fn` can be called repeatedly without mutating state.
+ ///
+ /// *This trait (`Fn`) is not to be confused with [function pointers]
+ /// (`fn`).*
+ ///
+ /// `Fn` is implemented automatically by closures which only take immutable
+ /// references to captured variables or don't capture anything at all, as well
+ /// as (safe) [function pointers] (with some caveats, see their documentation
+ /// for more details). Additionally, for any type `F` that implements `Fn`, `&F`
+ /// implements `Fn`, too.
+ ///
+ /// Since both [`FnMut`] and [`FnOnce`] are supertraits of `Fn`, any
+ /// instance of `Fn` can be used as a parameter where a [`FnMut`] or [`FnOnce`]
+ /// is expected.
+ ///
+ /// Use `Fn` as a bound when you want to accept a parameter of function-like
+ /// type and need to call it repeatedly and without mutating state (e.g., when
+ /// calling it concurrently). If you do not need such strict requirements, use
+ /// [`FnMut`] or [`FnOnce`] as bounds.
+ ///
+ /// See the [chapter on closures in *The Rust Programming Language*][book] for
+ /// some more information on this topic.
+ ///
+ /// Also of note is the special syntax for `Fn` traits (e.g.
+ /// `Fn(usize, bool) -> usize`). Those interested in the technical details of
+ /// this can refer to [the relevant section in the *Rustonomicon*][nomicon].
+ ///
+ /// [book]: ../../book/ch13-01-closures.html
+ /// [function pointers]: ../../std/primitive.fn.html
+ /// [nomicon]: ../../nomicon/hrtb.html
+ ///
+ /// # Examples
+ ///
+ /// ## Calling a closure
+ ///
+ /// ```
+ /// let square = |x| x * x;
+ /// assert_eq!(square(5), 25);
+ /// ```
+ ///
+ /// ## Using a `Fn` parameter
+ ///
+ /// ```
+ /// fn call_with_one<F>(func: F) -> usize
+ ///     where F: Fn(usize) -> usize {
+ ///     func(1)
+ /// }
+ ///
+ /// let double = |x| x * 2;
+ /// assert_eq!(call_with_one(double), 2);
+ /// ```
+ #[lang = "fn"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_paren_sugar]
+ #[rustc_on_unimplemented(
+     on(
+         Args = "()",
+         note = "wrap the `{Self}` in a closure with no arguments: `|| {{ /* code */ }}`"
+     ),
+     message = "expected a `{Fn}<{Args}>` closure, found `{Self}`",
+     label = "expected an `Fn<{Args}>` closure, found `{Self}`"
+ )]
+ #[fundamental] // so that regex can rely that `&str: !FnMut`
+ #[must_use = "closures are lazy and do nothing unless called"]
+ pub trait Fn<Args>: FnMut<Args> {
+     /// Performs the call operation.
+     #[unstable(feature = "fn_traits", issue = "29625")]
+     extern "rust-call" fn call(&self, args: Args) -> Self::Output;
+ }
+ 
+ /// The version of the call operator that takes a mutable receiver.
+ ///
+ /// Instances of `FnMut` can be called repeatedly and may mutate state.
+ ///
+ /// `FnMut` is implemented automatically by closures which take mutable
+ /// references to captured variables, as well as all types that implement
+ /// [`Fn`], e.g., (safe) [function pointers] (since `FnMut` is a supertrait of
+ /// [`Fn`]). Additionally, for any type `F` that implements `FnMut`, `&mut F`
+ /// implements `FnMut`, too.
+ ///
+ /// Since [`FnOnce`] is a supertrait of `FnMut`, any instance of `FnMut` can be
+ /// used where a [`FnOnce`] is expected, and since [`Fn`] is a subtrait of
+ /// `FnMut`, any instance of [`Fn`] can be used where `FnMut` is expected.
+ ///
+ /// Use `FnMut` as a bound when you want to accept a parameter of function-like
+ /// type and need to call it repeatedly, while allowing it to mutate state.
+ /// If you don't want the parameter to mutate state, use [`Fn`] as a
+ /// bound; if you don't need to call it repeatedly, use [`FnOnce`].
+ ///
+ /// See the [chapter on closures in *The Rust Programming Language*][book] for
+ /// some more information on this topic.
+ ///
+ /// Also of note is the special syntax for `Fn` traits (e.g.
+ /// `Fn(usize, bool) -> usize`). Those interested in the technical details of
+ /// this can refer to [the relevant section in the *Rustonomicon*][nomicon].
+ ///
+ /// [book]: ../../book/ch13-01-closures.html
+ /// [function pointers]: ../../std/primitive.fn.html
+ /// [nomicon]: ../../nomicon/hrtb.html
+ ///
+ /// # Examples
+ ///
+ /// ## Calling a mutably capturing closure
+ ///
+ /// ```
+ /// let mut x = 5;
+ /// {
+ ///     let mut square_x = || x *= x;
+ ///     square_x();
+ /// }
+ /// assert_eq!(x, 25);
+ /// ```
+ ///
+ /// ## Using a `FnMut` parameter
+ ///
+ /// ```
+ /// fn do_twice<F>(mut func: F)
+ ///     where F: FnMut()
+ /// {
+ ///     func();
+ ///     func();
+ /// }
+ ///
+ /// let mut x: usize = 1;
+ /// {
+ ///     let add_two_to_x = || x += 2;
+ ///     do_twice(add_two_to_x);
+ /// }
+ ///
+ /// assert_eq!(x, 5);
+ /// ```
+ #[lang = "fn_mut"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_paren_sugar]
+ #[rustc_on_unimplemented(
+     on(
+         Args = "()",
+         note = "wrap the `{Self}` in a closure with no arguments: `|| {{ /* code */ }}`"
+     ),
+     message = "expected a `{FnMut}<{Args}>` closure, found `{Self}`",
+     label = "expected an `FnMut<{Args}>` closure, found `{Self}`"
+ )]
+ #[fundamental] // so that regex can rely that `&str: !FnMut`
+ #[must_use = "closures are lazy and do nothing unless called"]
+ pub trait FnMut<Args>: FnOnce<Args> {
+     /// Performs the call operation.
+     #[unstable(feature = "fn_traits", issue = "29625")]
+     extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output;
+ }
+ 
+ /// The version of the call operator that takes a by-value receiver.
+ ///
+ /// Instances of `FnOnce` can be called, but might not be callable multiple
+ /// times. Because of this, if the only thing known about a type is that it
+ /// implements `FnOnce`, it can only be called once.
+ ///
+ /// `FnOnce` is implemented automatically by closures that might consume captured
+ /// variables, as well as all types that implement [`FnMut`], e.g., (safe)
+ /// [function pointers] (since `FnOnce` is a supertrait of [`FnMut`]).
+ ///
+ /// Since both [`Fn`] and [`FnMut`] are subtraits of `FnOnce`, any instance of
+ /// [`Fn`] or [`FnMut`] can be used where a `FnOnce` is expected.
+ ///
+ /// Use `FnOnce` as a bound when you want to accept a parameter of function-like
+ /// type and only need to call it once. If you need to call the parameter
+ /// repeatedly, use [`FnMut`] as a bound; if you also need it to not mutate
+ /// state, use [`Fn`].
+ ///
+ /// See the [chapter on closures in *The Rust Programming Language*][book] for
+ /// some more information on this topic.
+ ///
+ /// Also of note is the special syntax for `Fn` traits (e.g.
+ /// `Fn(usize, bool) -> usize`). Those interested in the technical details of
+ /// this can refer to [the relevant section in the *Rustonomicon*][nomicon].
+ ///
+ /// [book]: ../../book/ch13-01-closures.html
+ /// [function pointers]: ../../std/primitive.fn.html
+ /// [nomicon]: ../../nomicon/hrtb.html
+ ///
+ /// # Examples
+ ///
+ /// ## Using a `FnOnce` parameter
+ ///
+ /// ```
+ /// fn consume_with_relish<F>(func: F)
+ ///     where F: FnOnce() -> String
+ /// {
+ ///     // `func` consumes its captured variables, so it cannot be run more
+ ///     // than once.
+ ///     println!("Consumed: {}", func());
+ ///
+ ///     println!("Delicious!");
+ ///
+ ///     // Attempting to invoke `func()` again will throw a `use of moved
+ ///     // value` error for `func`.
+ /// }
+ ///
+ /// let x = String::from("x");
+ /// let consume_and_return_x = move || x;
+ /// consume_with_relish(consume_and_return_x);
+ ///
+ /// // `consume_and_return_x` can no longer be invoked at this point
+ /// ```
+ #[lang = "fn_once"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_paren_sugar]
+ #[rustc_on_unimplemented(
+     on(
+         Args = "()",
+         note = "wrap the `{Self}` in a closure with no arguments: `|| {{ /* code */ }}`"
+     ),
+     message = "expected a `{FnOnce}<{Args}>` closure, found `{Self}`",
+     label = "expected an `FnOnce<{Args}>` closure, found `{Self}`"
+ )]
+ #[fundamental] // so that regex can rely that `&str: !FnMut`
+ #[must_use = "closures are lazy and do nothing unless called"]
+ pub trait FnOnce<Args> {
+     /// The returned type after the call operator is used.
+     #[lang = "fn_once_output"]
+     #[stable(feature = "fn_once_output", since = "1.12.0")]
+     type Output;
+ 
+     /// Performs the call operation.
+     #[unstable(feature = "fn_traits", issue = "29625")]
+     extern "rust-call" fn call_once(self, args: Args) -> Self::Output;
+ }
+ 
+ mod impls {
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A, F: ?Sized> Fn<A> for &F
+     where
+         F: Fn<A>,
+     {
+         extern "rust-call" fn call(&self, args: A) -> F::Output {
+             (**self).call(args)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A, F: ?Sized> FnMut<A> for &F
+     where
+         F: Fn<A>,
+     {
+         extern "rust-call" fn call_mut(&mut self, args: A) -> F::Output {
+             (**self).call(args)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A, F: ?Sized> FnOnce<A> for &F
+     where
+         F: Fn<A>,
+     {
+         type Output = F::Output;
+ 
+         extern "rust-call" fn call_once(self, args: A) -> F::Output {
+             (*self).call(args)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A, F: ?Sized> FnMut<A> for &mut F
+     where
+         F: FnMut<A>,
+     {
+         extern "rust-call" fn call_mut(&mut self, args: A) -> F::Output {
+             (*self).call_mut(args)
+         }
+     }
+ 
+     #[stable(feature = "rust1", since = "1.0.0")]
+     impl<A, F: ?Sized> FnOnce<A> for &mut F
+     where
+         F: FnMut<A>,
+     {
+         type Output = F::Output;
+         extern "rust-call" fn call_once(self, args: A) -> F::Output {
+             (*self).call_mut(args)
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/generator.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/generator.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/generator.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/generator.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,134 ----
+ use crate::marker::Unpin;
+ use crate::pin::Pin;
+ 
+ /// The result of a generator resumption.
+ ///
+ /// This enum is returned from the `Generator::resume` method and indicates the
+ /// possible return values of a generator. Currently this corresponds to either
+ /// a suspension point (`Yielded`) or a termination point (`Complete`).
+ #[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord, Debug, Hash)]
+ #[lang = "generator_state"]
+ #[unstable(feature = "generator_trait", issue = "43122")]
+ pub enum GeneratorState<Y, R> {
+     /// The generator suspended with a value.
+     ///
+     /// This state indicates that a generator has been suspended, and typically
+     /// corresponds to a `yield` statement. The value provided in this variant
+     /// corresponds to the expression passed to `yield` and allows generators to
+     /// provide a value each time they yield.
+     Yielded(Y),
+ 
+     /// The generator completed with a return value.
+     ///
+     /// This state indicates that a generator has finished execution with the
+     /// provided value. Once a generator has returned `Complete` it is
+     /// considered a programmer error to call `resume` again.
+     Complete(R),
+ }
+ 
+ /// The trait implemented by builtin generator types.
+ ///
+ /// Generators, also commonly referred to as coroutines, are currently an
+ /// experimental language feature in Rust. Added in [RFC 2033] generators are
+ /// currently intended to primarily provide a building block for async/await
+ /// syntax but will likely extend to also providing an ergonomic definition for
+ /// iterators and other primitives.
+ ///
+ /// The syntax and semantics for generators is unstable and will require a
+ /// further RFC for stabilization. At this time, though, the syntax is
+ /// closure-like:
+ ///
+ /// ```rust
+ /// #![feature(generators, generator_trait)]
+ ///
+ /// use std::ops::{Generator, GeneratorState};
+ /// use std::pin::Pin;
+ ///
+ /// fn main() {
+ ///     let mut generator = || {
+ ///         yield 1;
+ ///         return "foo"
+ ///     };
+ ///
+ ///     match Pin::new(&mut generator).resume(()) {
+ ///         GeneratorState::Yielded(1) => {}
+ ///         _ => panic!("unexpected return from resume"),
+ ///     }
+ ///     match Pin::new(&mut generator).resume(()) {
+ ///         GeneratorState::Complete("foo") => {}
+ ///         _ => panic!("unexpected return from resume"),
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// More documentation of generators can be found in the unstable book.
+ ///
+ /// [RFC 2033]: https://github.com/rust-lang/rfcs/pull/2033
+ #[lang = "generator"]
+ #[unstable(feature = "generator_trait", issue = "43122")]
+ #[fundamental]
+ pub trait Generator<R = ()> {
+     /// The type of value this generator yields.
+     ///
+     /// This associated type corresponds to the `yield` expression and the
+     /// values which are allowed to be returned each time a generator yields.
+     /// For example an iterator-as-a-generator would likely have this type as
+     /// `T`, the type being iterated over.
+     type Yield;
+ 
+     /// The type of value this generator returns.
+     ///
+     /// This corresponds to the type returned from a generator either with a
+     /// `return` statement or implicitly as the last expression of a generator
+     /// literal. For example futures would use this as `Result<T, E>` as it
+     /// represents a completed future.
+     type Return;
+ 
+     /// Resumes the execution of this generator.
+     ///
+     /// This function will resume execution of the generator or start execution
+     /// if it hasn't already. This call will return back into the generator's
+     /// last suspension point, resuming execution from the latest `yield`. The
+     /// generator will continue executing until it either yields or returns, at
+     /// which point this function will return.
+     ///
+     /// # Return value
+     ///
+     /// The `GeneratorState` enum returned from this function indicates what
+     /// state the generator is in upon returning. If the `Yielded` variant is
+     /// returned then the generator has reached a suspension point and a value
+     /// has been yielded out. Generators in this state are available for
+     /// resumption at a later point.
+     ///
+     /// If `Complete` is returned then the generator has completely finished
+     /// with the value provided. It is invalid for the generator to be resumed
+     /// again.
+     ///
+     /// # Panics
+     ///
+     /// This function may panic if it is called after the `Complete` variant has
+     /// been returned previously. While generator literals in the language are
+     /// guaranteed to panic on resuming after `Complete`, this is not guaranteed
+     /// for all implementations of the `Generator` trait.
+     fn resume(self: Pin<&mut Self>, arg: R) -> GeneratorState<Self::Yield, Self::Return>;
+ }
+ 
+ #[unstable(feature = "generator_trait", issue = "43122")]
+ impl<G: ?Sized + Generator<R>, R> Generator<R> for Pin<&mut G> {
+     type Yield = G::Yield;
+     type Return = G::Return;
+ 
+     fn resume(mut self: Pin<&mut Self>, arg: R) -> GeneratorState<Self::Yield, Self::Return> {
+         G::resume((*self).as_mut(), arg)
+     }
+ }
+ 
+ #[unstable(feature = "generator_trait", issue = "43122")]
+ impl<G: ?Sized + Generator<R> + Unpin, R> Generator<R> for &mut G {
+     type Yield = G::Yield;
+     type Return = G::Return;
+ 
+     fn resume(mut self: Pin<&mut Self>, arg: R) -> GeneratorState<Self::Yield, Self::Return> {
+         G::resume(Pin::new(&mut *self), arg)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/index.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/index.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/index.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/index.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,167 ----
+ /// Used for indexing operations (`container[index]`) in immutable contexts.
+ ///
+ /// `container[index]` is actually syntactic sugar for `*container.index(index)`,
+ /// but only when used as an immutable value. If a mutable value is requested,
+ /// [`IndexMut`] is used instead. This allows nice things such as
+ /// `let value = v[index]` if the type of `value` implements [`Copy`].
+ ///
+ /// # Examples
+ ///
+ /// The following example implements `Index` on a read-only `NucleotideCount`
+ /// container, enabling individual counts to be retrieved with index syntax.
+ ///
+ /// ```
+ /// use std::ops::Index;
+ ///
+ /// enum Nucleotide {
+ ///     A,
+ ///     C,
+ ///     G,
+ ///     T,
+ /// }
+ ///
+ /// struct NucleotideCount {
+ ///     a: usize,
+ ///     c: usize,
+ ///     g: usize,
+ ///     t: usize,
+ /// }
+ ///
+ /// impl Index<Nucleotide> for NucleotideCount {
+ ///     type Output = usize;
+ ///
+ ///     fn index(&self, nucleotide: Nucleotide) -> &Self::Output {
+ ///         match nucleotide {
+ ///             Nucleotide::A => &self.a,
+ ///             Nucleotide::C => &self.c,
+ ///             Nucleotide::G => &self.g,
+ ///             Nucleotide::T => &self.t,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// let nucleotide_count = NucleotideCount {a: 14, c: 9, g: 10, t: 12};
+ /// assert_eq!(nucleotide_count[Nucleotide::A], 14);
+ /// assert_eq!(nucleotide_count[Nucleotide::C], 9);
+ /// assert_eq!(nucleotide_count[Nucleotide::G], 10);
+ /// assert_eq!(nucleotide_count[Nucleotide::T], 12);
+ /// ```
+ #[lang = "index"]
+ #[rustc_on_unimplemented(
+     message = "the type `{Self}` cannot be indexed by `{Idx}`",
+     label = "`{Self}` cannot be indexed by `{Idx}`"
+ )]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(alias = "]")]
+ #[doc(alias = "[")]
+ #[doc(alias = "[]")]
+ pub trait Index<Idx: ?Sized> {
+     /// The returned type after indexing.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Output: ?Sized;
+ 
+     /// Performs the indexing (`container[index]`) operation.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[track_caller]
+     fn index(&self, index: Idx) -> &Self::Output;
+ }
+ 
+ /// Used for indexing operations (`container[index]`) in mutable contexts.
+ ///
+ /// `container[index]` is actually syntactic sugar for
+ /// `*container.index_mut(index)`, but only when used as a mutable value. If
+ /// an immutable value is requested, the [`Index`] trait is used instead. This
+ /// allows nice things such as `v[index] = value`.
+ ///
+ /// # Examples
+ ///
+ /// A very simple implementation of a `Balance` struct that has two sides, where
+ /// each can be indexed mutably and immutably.
+ ///
+ /// ```
+ /// use std::ops::{Index,IndexMut};
+ ///
+ /// #[derive(Debug)]
+ /// enum Side {
+ ///     Left,
+ ///     Right,
+ /// }
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// enum Weight {
+ ///     Kilogram(f32),
+ ///     Pound(f32),
+ /// }
+ ///
+ /// struct Balance {
+ ///     pub left: Weight,
+ ///     pub right: Weight,
+ /// }
+ ///
+ /// impl Index<Side> for Balance {
+ ///     type Output = Weight;
+ ///
+ ///     fn index(&self, index: Side) -> &Self::Output {
+ ///         println!("Accessing {:?}-side of balance immutably", index);
+ ///         match index {
+ ///             Side::Left => &self.left,
+ ///             Side::Right => &self.right,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// impl IndexMut<Side> for Balance {
+ ///     fn index_mut(&mut self, index: Side) -> &mut Self::Output {
+ ///         println!("Accessing {:?}-side of balance mutably", index);
+ ///         match index {
+ ///             Side::Left => &mut self.left,
+ ///             Side::Right => &mut self.right,
+ ///         }
+ ///     }
+ /// }
+ ///
+ /// let mut balance = Balance {
+ ///     right: Weight::Kilogram(2.5),
+ ///     left: Weight::Pound(1.5),
+ /// };
+ ///
+ /// // In this case, `balance[Side::Right]` is sugar for
+ /// // `*balance.index(Side::Right)`, since we are only *reading*
+ /// // `balance[Side::Right]`, not writing it.
+ /// assert_eq!(balance[Side::Right], Weight::Kilogram(2.5));
+ ///
+ /// // However, in this case `balance[Side::Left]` is sugar for
+ /// // `*balance.index_mut(Side::Left)`, since we are writing
+ /// // `balance[Side::Left]`.
+ /// balance[Side::Left] = Weight::Kilogram(3.0);
+ /// ```
+ #[lang = "index_mut"]
+ #[rustc_on_unimplemented(
+     on(
+         _Self = "&str",
+         note = "you can use `.chars().nth()` or `.bytes().nth()`
+ see chapter in The Book <https://doc.rust-lang.org/book/ch08-02-strings.html#indexing-into-strings>"
+     ),
+     on(
+         _Self = "str",
+         note = "you can use `.chars().nth()` or `.bytes().nth()`
+ see chapter in The Book <https://doc.rust-lang.org/book/ch08-02-strings.html#indexing-into-strings>"
+     ),
+     on(
+         _Self = "std::string::String",
+         note = "you can use `.chars().nth()` or `.bytes().nth()`
+ see chapter in The Book <https://doc.rust-lang.org/book/ch08-02-strings.html#indexing-into-strings>"
+     ),
+     message = "the type `{Self}` cannot be mutably indexed by `{Idx}`",
+     label = "`{Self}` cannot be mutably indexed by `{Idx}`"
+ )]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(alias = "[")]
+ #[doc(alias = "]")]
+ #[doc(alias = "[]")]
+ pub trait IndexMut<Idx: ?Sized>: Index<Idx> {
+     /// Performs the mutable indexing (`container[index]`) operation.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[track_caller]
+     fn index_mut(&mut self, index: Idx) -> &mut Self::Output;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,197 ----
+ //! Overloadable operators.
+ //!
+ //! Implementing these traits allows you to overload certain operators.
+ //!
+ //! Some of these traits are imported by the prelude, so they are available in
+ //! every Rust program. Only operators backed by traits can be overloaded. For
+ //! example, the addition operator (`+`) can be overloaded through the [`Add`]
+ //! trait, but since the assignment operator (`=`) has no backing trait, there
+ //! is no way of overloading its semantics. Additionally, this module does not
+ //! provide any mechanism to create new operators. If traitless overloading or
+ //! custom operators are required, you should look toward macros or compiler
+ //! plugins to extend Rust's syntax.
+ //!
+ //! Implementations of operator traits should be unsurprising in their
+ //! respective contexts, keeping in mind their usual meanings and
+ //! [operator precedence]. For example, when implementing [`Mul`], the operation
+ //! should have some resemblance to multiplication (and share expected
+ //! properties like associativity).
+ //!
+ //! Note that the `&&` and `||` operators short-circuit, i.e., they only
+ //! evaluate their second operand if it contributes to the result. Since this
+ //! behavior is not enforceable by traits, `&&` and `||` are not supported as
+ //! overloadable operators.
+ //!
+ //! Many of the operators take their operands by value. In non-generic
+ //! contexts involving built-in types, this is usually not a problem.
+ //! However, using these operators in generic code, requires some
+ //! attention if values have to be reused as opposed to letting the operators
+ //! consume them. One option is to occasionally use [`clone`].
+ //! Another option is to rely on the types involved providing additional
+ //! operator implementations for references. For example, for a user-defined
+ //! type `T` which is supposed to support addition, it is probably a good
+ //! idea to have both `T` and `&T` implement the traits [`Add<T>`][`Add`] and
+ //! [`Add<&T>`][`Add`] so that generic code can be written without unnecessary
+ //! cloning.
+ //!
+ //! # Examples
+ //!
+ //! This example creates a `Point` struct that implements [`Add`] and [`Sub`],
+ //! and then demonstrates adding and subtracting two `Point`s.
+ //!
+ //! ```rust
+ //! use std::ops::{Add, Sub};
+ //!
+ //! #[derive(Debug, Copy, Clone, PartialEq)]
+ //! struct Point {
+ //!     x: i32,
+ //!     y: i32,
+ //! }
+ //!
+ //! impl Add for Point {
+ //!     type Output = Self;
+ //!
+ //!     fn add(self, other: Self) -> Self {
+ //!         Self {x: self.x + other.x, y: self.y + other.y}
+ //!     }
+ //! }
+ //!
+ //! impl Sub for Point {
+ //!     type Output = Self;
+ //!
+ //!     fn sub(self, other: Self) -> Self {
+ //!         Self {x: self.x - other.x, y: self.y - other.y}
+ //!     }
+ //! }
+ //!
+ //! assert_eq!(Point {x: 3, y: 3}, Point {x: 1, y: 0} + Point {x: 2, y: 3});
+ //! assert_eq!(Point {x: -1, y: -3}, Point {x: 1, y: 0} - Point {x: 2, y: 3});
+ //! ```
+ //!
+ //! See the documentation for each trait for an example implementation.
+ //!
+ //! The [`Fn`], [`FnMut`], and [`FnOnce`] traits are implemented by types that can be
+ //! invoked like functions. Note that [`Fn`] takes `&self`, [`FnMut`] takes `&mut
+ //! self` and [`FnOnce`] takes `self`. These correspond to the three kinds of
+ //! methods that can be invoked on an instance: call-by-reference,
+ //! call-by-mutable-reference, and call-by-value. The most common use of these
+ //! traits is to act as bounds to higher-level functions that take functions or
+ //! closures as arguments.
+ //!
+ //! Taking a [`Fn`] as a parameter:
+ //!
+ //! ```rust
+ //! fn call_with_one<F>(func: F) -> usize
+ //!     where F: Fn(usize) -> usize
+ //! {
+ //!     func(1)
+ //! }
+ //!
+ //! let double = |x| x * 2;
+ //! assert_eq!(call_with_one(double), 2);
+ //! ```
+ //!
+ //! Taking a [`FnMut`] as a parameter:
+ //!
+ //! ```rust
+ //! fn do_twice<F>(mut func: F)
+ //!     where F: FnMut()
+ //! {
+ //!     func();
+ //!     func();
+ //! }
+ //!
+ //! let mut x: usize = 1;
+ //! {
+ //!     let add_two_to_x = || x += 2;
+ //!     do_twice(add_two_to_x);
+ //! }
+ //!
+ //! assert_eq!(x, 5);
+ //! ```
+ //!
+ //! Taking a [`FnOnce`] as a parameter:
+ //!
+ //! ```rust
+ //! fn consume_with_relish<F>(func: F)
+ //!     where F: FnOnce() -> String
+ //! {
+ //!     // `func` consumes its captured variables, so it cannot be run more
+ //!     // than once
+ //!     println!("Consumed: {}", func());
+ //!
+ //!     println!("Delicious!");
+ //!
+ //!     // Attempting to invoke `func()` again will throw a `use of moved
+ //!     // value` error for `func`
+ //! }
+ //!
+ //! let x = String::from("x");
+ //! let consume_and_return_x = move || x;
+ //! consume_with_relish(consume_and_return_x);
+ //!
+ //! // `consume_and_return_x` can no longer be invoked at this point
+ //! ```
+ //!
+ //! [`clone`]: Clone::clone
+ //! [operator precedence]: ../../reference/expressions.html#expression-precedence
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ mod arith;
+ mod bit;
+ mod control_flow;
+ mod deref;
+ mod drop;
+ mod function;
+ mod generator;
+ mod index;
+ mod range;
+ mod r#try;
+ mod unsize;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::arith::{Add, Div, Mul, Neg, Rem, Sub};
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ pub use self::arith::{AddAssign, DivAssign, MulAssign, RemAssign, SubAssign};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::bit::{BitAnd, BitOr, BitXor, Not, Shl, Shr};
+ #[stable(feature = "op_assign_traits", since = "1.8.0")]
+ pub use self::bit::{BitAndAssign, BitOrAssign, BitXorAssign, ShlAssign, ShrAssign};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::deref::{Deref, DerefMut};
+ 
+ #[unstable(feature = "receiver_trait", issue = "none")]
+ pub use self::deref::Receiver;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::drop::Drop;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::function::{Fn, FnMut, FnOnce};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::index::{Index, IndexMut};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use self::range::{Range, RangeFrom, RangeFull, RangeTo};
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ pub use self::range::{Bound, RangeBounds, RangeInclusive, RangeToInclusive};
+ 
+ #[unstable(feature = "try_trait", issue = "42327")]
+ pub use self::r#try::Try;
+ 
+ #[unstable(feature = "generator_trait", issue = "43122")]
+ pub use self::generator::{Generator, GeneratorState};
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ pub use self::unsize::CoerceUnsized;
+ 
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ pub use self::unsize::DispatchFromDyn;
+ 
+ #[unstable(feature = "control_flow_enum", reason = "new API", issue = "75744")]
+ pub use self::control_flow::ControlFlow;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/range.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/range.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/range.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/range.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1006 ----
+ use crate::fmt;
+ use crate::hash::Hash;
+ use crate::slice::index::{
+     slice_end_index_len_fail, slice_end_index_overflow_fail, slice_index_order_fail,
+     slice_start_index_overflow_fail,
+ };
+ 
+ /// An unbounded range (`..`).
+ ///
+ /// `RangeFull` is primarily used as a [slicing index], its shorthand is `..`.
+ /// It cannot serve as an [`Iterator`] because it doesn't have a starting point.
+ ///
+ /// # Examples
+ ///
+ /// The `..` syntax is a `RangeFull`:
+ ///
+ /// ```
+ /// assert_eq!((..), std::ops::RangeFull);
+ /// ```
+ ///
+ /// It does not have an [`IntoIterator`] implementation, so you can't use it in
+ /// a `for` loop directly. This won't compile:
+ ///
+ /// ```compile_fail,E0277
+ /// for i in .. {
+ ///     // ...
+ /// }
+ /// ```
+ ///
+ /// Used as a [slicing index], `RangeFull` produces the full array as a slice.
+ ///
+ /// ```
+ /// let arr = [0, 1, 2, 3, 4];
+ /// assert_eq!(arr[ ..  ], [0, 1, 2, 3, 4]); // This is the `RangeFull`
+ /// assert_eq!(arr[ .. 3], [0, 1, 2      ]);
+ /// assert_eq!(arr[ ..=3], [0, 1, 2, 3   ]);
+ /// assert_eq!(arr[1..  ], [   1, 2, 3, 4]);
+ /// assert_eq!(arr[1.. 3], [   1, 2      ]);
+ /// assert_eq!(arr[1..=3], [   1, 2, 3   ]);
+ /// ```
+ ///
+ /// [slicing index]: crate::slice::SliceIndex
+ #[lang = "RangeFull"]
+ #[doc(alias = "..")]
+ #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RangeFull;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Debug for RangeFull {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(fmt, "..")
+     }
+ }
+ 
+ /// A (half-open) range bounded inclusively below and exclusively above
+ /// (`start..end`).
+ ///
+ /// The range `start..end` contains all values with `start <= x < end`.
+ /// It is empty if `start >= end`.
+ ///
+ /// # Examples
+ ///
+ /// The `start..end` syntax is a `Range`:
+ ///
+ /// ```
+ /// assert_eq!((3..5), std::ops::Range { start: 3, end: 5 });
+ /// assert_eq!(3 + 4 + 5, (3..6).sum());
+ /// ```
+ ///
+ /// ```
+ /// let arr = [0, 1, 2, 3, 4];
+ /// assert_eq!(arr[ ..  ], [0, 1, 2, 3, 4]);
+ /// assert_eq!(arr[ .. 3], [0, 1, 2      ]);
+ /// assert_eq!(arr[ ..=3], [0, 1, 2, 3   ]);
+ /// assert_eq!(arr[1..  ], [   1, 2, 3, 4]);
+ /// assert_eq!(arr[1.. 3], [   1, 2      ]); // This is a `Range`
+ /// assert_eq!(arr[1..=3], [   1, 2, 3   ]);
+ /// ```
+ #[lang = "Range"]
+ #[doc(alias = "..")]
+ #[derive(Clone, Default, PartialEq, Eq, Hash)] // not Copy -- see #27186
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Range<Idx> {
+     /// The lower bound of the range (inclusive).
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub start: Idx,
+     /// The upper bound of the range (exclusive).
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub end: Idx,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<Idx: fmt::Debug> fmt::Debug for Range<Idx> {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.start.fmt(fmt)?;
+         write!(fmt, "..")?;
+         self.end.fmt(fmt)?;
+         Ok(())
+     }
+ }
+ 
+ impl<Idx: PartialOrd<Idx>> Range<Idx> {
+     /// Returns `true` if `item` is contained in the range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!(!(3..5).contains(&2));
+     /// assert!( (3..5).contains(&3));
+     /// assert!( (3..5).contains(&4));
+     /// assert!(!(3..5).contains(&5));
+     ///
+     /// assert!(!(3..3).contains(&3));
+     /// assert!(!(3..2).contains(&3));
+     ///
+     /// assert!( (0.0..1.0).contains(&0.5));
+     /// assert!(!(0.0..1.0).contains(&f32::NAN));
+     /// assert!(!(0.0..f32::NAN).contains(&0.5));
+     /// assert!(!(f32::NAN..1.0).contains(&0.5));
+     /// ```
+     #[stable(feature = "range_contains", since = "1.35.0")]
+     pub fn contains<U>(&self, item: &U) -> bool
+     where
+         Idx: PartialOrd<U>,
+         U: ?Sized + PartialOrd<Idx>,
+     {
+         <Self as RangeBounds<Idx>>::contains(self, item)
+     }
+ 
+     /// Returns `true` if the range contains no items.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!(!(3..5).is_empty());
+     /// assert!( (3..3).is_empty());
+     /// assert!( (3..2).is_empty());
+     /// ```
+     ///
+     /// The range is empty if either side is incomparable:
+     ///
+     /// ```
+     /// assert!(!(3.0..5.0).is_empty());
+     /// assert!( (3.0..f32::NAN).is_empty());
+     /// assert!( (f32::NAN..5.0).is_empty());
+     /// ```
+     #[stable(feature = "range_is_empty", since = "1.47.0")]
+     pub fn is_empty(&self) -> bool {
+         !(self.start < self.end)
+     }
+ }
+ 
+ /// A range only bounded inclusively below (`start..`).
+ ///
+ /// The `RangeFrom` `start..` contains all values with `x >= start`.
+ ///
+ /// *Note*: Overflow in the [`Iterator`] implementation (when the contained
+ /// data type reaches its numerical limit) is allowed to panic, wrap, or
+ /// saturate. This behavior is defined by the implementation of the [`Step`]
+ /// trait. For primitive integers, this follows the normal rules, and respects
+ /// the overflow checks profile (panic in debug, wrap in release). Note also
+ /// that overflow happens earlier than you might assume: the overflow happens
+ /// in the call to `next` that yields the maximum value, as the range must be
+ /// set to a state to yield the next value.
+ ///
+ /// [`Step`]: crate::iter::Step
+ ///
+ /// # Examples
+ ///
+ /// The `start..` syntax is a `RangeFrom`:
+ ///
+ /// ```
+ /// assert_eq!((2..), std::ops::RangeFrom { start: 2 });
+ /// assert_eq!(2 + 3 + 4, (2..).take(3).sum());
+ /// ```
+ ///
+ /// ```
+ /// let arr = [0, 1, 2, 3, 4];
+ /// assert_eq!(arr[ ..  ], [0, 1, 2, 3, 4]);
+ /// assert_eq!(arr[ .. 3], [0, 1, 2      ]);
+ /// assert_eq!(arr[ ..=3], [0, 1, 2, 3   ]);
+ /// assert_eq!(arr[1..  ], [   1, 2, 3, 4]); // This is a `RangeFrom`
+ /// assert_eq!(arr[1.. 3], [   1, 2      ]);
+ /// assert_eq!(arr[1..=3], [   1, 2, 3   ]);
+ /// ```
+ #[lang = "RangeFrom"]
+ #[doc(alias = "..")]
+ #[derive(Clone, PartialEq, Eq, Hash)] // not Copy -- see #27186
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RangeFrom<Idx> {
+     /// The lower bound of the range (inclusive).
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub start: Idx,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<Idx: fmt::Debug> fmt::Debug for RangeFrom<Idx> {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.start.fmt(fmt)?;
+         write!(fmt, "..")?;
+         Ok(())
+     }
+ }
+ 
+ impl<Idx: PartialOrd<Idx>> RangeFrom<Idx> {
+     /// Returns `true` if `item` is contained in the range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!(!(3..).contains(&2));
+     /// assert!( (3..).contains(&3));
+     /// assert!( (3..).contains(&1_000_000_000));
+     ///
+     /// assert!( (0.0..).contains(&0.5));
+     /// assert!(!(0.0..).contains(&f32::NAN));
+     /// assert!(!(f32::NAN..).contains(&0.5));
+     /// ```
+     #[stable(feature = "range_contains", since = "1.35.0")]
+     pub fn contains<U>(&self, item: &U) -> bool
+     where
+         Idx: PartialOrd<U>,
+         U: ?Sized + PartialOrd<Idx>,
+     {
+         <Self as RangeBounds<Idx>>::contains(self, item)
+     }
+ }
+ 
+ /// A range only bounded exclusively above (`..end`).
+ ///
+ /// The `RangeTo` `..end` contains all values with `x < end`.
+ /// It cannot serve as an [`Iterator`] because it doesn't have a starting point.
+ ///
+ /// # Examples
+ ///
+ /// The `..end` syntax is a `RangeTo`:
+ ///
+ /// ```
+ /// assert_eq!((..5), std::ops::RangeTo { end: 5 });
+ /// ```
+ ///
+ /// It does not have an [`IntoIterator`] implementation, so you can't use it in
+ /// a `for` loop directly. This won't compile:
+ ///
+ /// ```compile_fail,E0277
+ /// // error[E0277]: the trait bound `std::ops::RangeTo<{integer}>:
+ /// // std::iter::Iterator` is not satisfied
+ /// for i in ..5 {
+ ///     // ...
+ /// }
+ /// ```
+ ///
+ /// When used as a [slicing index], `RangeTo` produces a slice of all array
+ /// elements before the index indicated by `end`.
+ ///
+ /// ```
+ /// let arr = [0, 1, 2, 3, 4];
+ /// assert_eq!(arr[ ..  ], [0, 1, 2, 3, 4]);
+ /// assert_eq!(arr[ .. 3], [0, 1, 2      ]); // This is a `RangeTo`
+ /// assert_eq!(arr[ ..=3], [0, 1, 2, 3   ]);
+ /// assert_eq!(arr[1..  ], [   1, 2, 3, 4]);
+ /// assert_eq!(arr[1.. 3], [   1, 2      ]);
+ /// assert_eq!(arr[1..=3], [   1, 2, 3   ]);
+ /// ```
+ ///
+ /// [slicing index]: crate::slice::SliceIndex
+ #[lang = "RangeTo"]
+ #[doc(alias = "..")]
+ #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RangeTo<Idx> {
+     /// The upper bound of the range (exclusive).
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub end: Idx,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<Idx: fmt::Debug> fmt::Debug for RangeTo<Idx> {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(fmt, "..")?;
+         self.end.fmt(fmt)?;
+         Ok(())
+     }
+ }
+ 
+ impl<Idx: PartialOrd<Idx>> RangeTo<Idx> {
+     /// Returns `true` if `item` is contained in the range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!( (..5).contains(&-1_000_000_000));
+     /// assert!( (..5).contains(&4));
+     /// assert!(!(..5).contains(&5));
+     ///
+     /// assert!( (..1.0).contains(&0.5));
+     /// assert!(!(..1.0).contains(&f32::NAN));
+     /// assert!(!(..f32::NAN).contains(&0.5));
+     /// ```
+     #[stable(feature = "range_contains", since = "1.35.0")]
+     pub fn contains<U>(&self, item: &U) -> bool
+     where
+         Idx: PartialOrd<U>,
+         U: ?Sized + PartialOrd<Idx>,
+     {
+         <Self as RangeBounds<Idx>>::contains(self, item)
+     }
+ }
+ 
+ /// A range bounded inclusively below and above (`start..=end`).
+ ///
+ /// The `RangeInclusive` `start..=end` contains all values with `x >= start`
+ /// and `x <= end`. It is empty unless `start <= end`.
+ ///
+ /// This iterator is [fused], but the specific values of `start` and `end` after
+ /// iteration has finished are **unspecified** other than that [`.is_empty()`]
+ /// will return `true` once no more values will be produced.
+ ///
+ /// [fused]: crate::iter::FusedIterator
+ /// [`.is_empty()`]: RangeInclusive::is_empty
+ ///
+ /// # Examples
+ ///
+ /// The `start..=end` syntax is a `RangeInclusive`:
+ ///
+ /// ```
+ /// assert_eq!((3..=5), std::ops::RangeInclusive::new(3, 5));
+ /// assert_eq!(3 + 4 + 5, (3..=5).sum());
+ /// ```
+ ///
+ /// ```
+ /// let arr = [0, 1, 2, 3, 4];
+ /// assert_eq!(arr[ ..  ], [0, 1, 2, 3, 4]);
+ /// assert_eq!(arr[ .. 3], [0, 1, 2      ]);
+ /// assert_eq!(arr[ ..=3], [0, 1, 2, 3   ]);
+ /// assert_eq!(arr[1..  ], [   1, 2, 3, 4]);
+ /// assert_eq!(arr[1.. 3], [   1, 2      ]);
+ /// assert_eq!(arr[1..=3], [   1, 2, 3   ]); // This is a `RangeInclusive`
+ /// ```
+ #[lang = "RangeInclusive"]
+ #[doc(alias = "..=")]
+ #[derive(Clone, PartialEq, Eq, Hash)] // not Copy -- see #27186
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ pub struct RangeInclusive<Idx> {
+     // Note that the fields here are not public to allow changing the
+     // representation in the future; in particular, while we could plausibly
+     // expose start/end, modifying them without changing (future/current)
+     // private fields may lead to incorrect behavior, so we don't want to
+     // support that mode.
+     pub(crate) start: Idx,
+     pub(crate) end: Idx,
+ 
+     // This field is:
+     //  - `false` upon construction
+     //  - `false` when iteration has yielded an element and the iterator is not exhausted
+     //  - `true` when iteration has been used to exhaust the iterator
+     //
+     // This is required to support PartialEq and Hash without a PartialOrd bound or specialization.
+     pub(crate) exhausted: bool,
+ }
+ 
+ impl<Idx> RangeInclusive<Idx> {
+     /// Creates a new inclusive range. Equivalent to writing `start..=end`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::ops::RangeInclusive;
+     ///
+     /// assert_eq!(3..=5, RangeInclusive::new(3, 5));
+     /// ```
+     #[lang = "range_inclusive_new"]
+     #[stable(feature = "inclusive_range_methods", since = "1.27.0")]
+     #[inline]
+     #[rustc_promotable]
+     #[rustc_const_stable(feature = "const_range_new", since = "1.32.0")]
+     pub const fn new(start: Idx, end: Idx) -> Self {
+         Self { start, end, exhausted: false }
+     }
+ 
+     /// Returns the lower bound of the range (inclusive).
+     ///
+     /// When using an inclusive range for iteration, the values of `start()` and
+     /// [`end()`] are unspecified after the iteration ended. To determine
+     /// whether the inclusive range is empty, use the [`is_empty()`] method
+     /// instead of comparing `start() > end()`.
+     ///
+     /// Note: the value returned by this method is unspecified after the range
+     /// has been iterated to exhaustion.
+     ///
+     /// [`end()`]: RangeInclusive::end
+     /// [`is_empty()`]: RangeInclusive::is_empty
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!((3..=5).start(), &3);
+     /// ```
+     #[stable(feature = "inclusive_range_methods", since = "1.27.0")]
+     #[rustc_const_stable(feature = "const_inclusive_range_methods", since = "1.32.0")]
+     #[inline]
+     pub const fn start(&self) -> &Idx {
+         &self.start
+     }
+ 
+     /// Returns the upper bound of the range (inclusive).
+     ///
+     /// When using an inclusive range for iteration, the values of [`start()`]
+     /// and `end()` are unspecified after the iteration ended. To determine
+     /// whether the inclusive range is empty, use the [`is_empty()`] method
+     /// instead of comparing `start() > end()`.
+     ///
+     /// Note: the value returned by this method is unspecified after the range
+     /// has been iterated to exhaustion.
+     ///
+     /// [`start()`]: RangeInclusive::start
+     /// [`is_empty()`]: RangeInclusive::is_empty
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!((3..=5).end(), &5);
+     /// ```
+     #[stable(feature = "inclusive_range_methods", since = "1.27.0")]
+     #[rustc_const_stable(feature = "const_inclusive_range_methods", since = "1.32.0")]
+     #[inline]
+     pub const fn end(&self) -> &Idx {
+         &self.end
+     }
+ 
+     /// Destructures the `RangeInclusive` into (lower bound, upper (inclusive) bound).
+     ///
+     /// Note: the value returned by this method is unspecified after the range
+     /// has been iterated to exhaustion.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!((3..=5).into_inner(), (3, 5));
+     /// ```
+     #[stable(feature = "inclusive_range_methods", since = "1.27.0")]
+     #[inline]
+     pub fn into_inner(self) -> (Idx, Idx) {
+         (self.start, self.end)
+     }
+ }
+ 
+ impl RangeInclusive<usize> {
+     /// Converts to an exclusive `Range` for `SliceIndex` implementations.
+     /// The caller is responsible for dealing with `end == usize::MAX`.
+     #[inline]
+     pub(crate) fn into_slice_range(self) -> Range<usize> {
+         // If we're not exhausted, we want to simply slice `start..end + 1`.
+         // If we are exhausted, then slicing with `end + 1..end + 1` gives us an
+         // empty range that is still subject to bounds-checks for that endpoint.
+         let exclusive_end = self.end + 1;
+         let start = if self.exhausted { exclusive_end } else { self.start };
+         start..exclusive_end
+     }
+ }
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ impl<Idx: fmt::Debug> fmt::Debug for RangeInclusive<Idx> {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         self.start.fmt(fmt)?;
+         write!(fmt, "..=")?;
+         self.end.fmt(fmt)?;
+         if self.exhausted {
+             write!(fmt, " (exhausted)")?;
+         }
+         Ok(())
+     }
+ }
+ 
+ impl<Idx: PartialOrd<Idx>> RangeInclusive<Idx> {
+     /// Returns `true` if `item` is contained in the range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!(!(3..=5).contains(&2));
+     /// assert!( (3..=5).contains(&3));
+     /// assert!( (3..=5).contains(&4));
+     /// assert!( (3..=5).contains(&5));
+     /// assert!(!(3..=5).contains(&6));
+     ///
+     /// assert!( (3..=3).contains(&3));
+     /// assert!(!(3..=2).contains(&3));
+     ///
+     /// assert!( (0.0..=1.0).contains(&1.0));
+     /// assert!(!(0.0..=1.0).contains(&f32::NAN));
+     /// assert!(!(0.0..=f32::NAN).contains(&0.0));
+     /// assert!(!(f32::NAN..=1.0).contains(&1.0));
+     /// ```
+     ///
+     /// This method always returns `false` after iteration has finished:
+     ///
+     /// ```
+     /// let mut r = 3..=5;
+     /// assert!(r.contains(&3) && r.contains(&5));
+     /// for _ in r.by_ref() {}
+     /// // Precise field values are unspecified here
+     /// assert!(!r.contains(&3) && !r.contains(&5));
+     /// ```
+     #[stable(feature = "range_contains", since = "1.35.0")]
+     pub fn contains<U>(&self, item: &U) -> bool
+     where
+         Idx: PartialOrd<U>,
+         U: ?Sized + PartialOrd<Idx>,
+     {
+         <Self as RangeBounds<Idx>>::contains(self, item)
+     }
+ 
+     /// Returns `true` if the range contains no items.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!(!(3..=5).is_empty());
+     /// assert!(!(3..=3).is_empty());
+     /// assert!( (3..=2).is_empty());
+     /// ```
+     ///
+     /// The range is empty if either side is incomparable:
+     ///
+     /// ```
+     /// assert!(!(3.0..=5.0).is_empty());
+     /// assert!( (3.0..=f32::NAN).is_empty());
+     /// assert!( (f32::NAN..=5.0).is_empty());
+     /// ```
+     ///
+     /// This method returns `true` after iteration has finished:
+     ///
+     /// ```
+     /// let mut r = 3..=5;
+     /// for _ in r.by_ref() {}
+     /// // Precise field values are unspecified here
+     /// assert!(r.is_empty());
+     /// ```
+     #[stable(feature = "range_is_empty", since = "1.47.0")]
+     #[inline]
+     pub fn is_empty(&self) -> bool {
+         self.exhausted || !(self.start <= self.end)
+     }
+ }
+ 
+ /// A range only bounded inclusively above (`..=end`).
+ ///
+ /// The `RangeToInclusive` `..=end` contains all values with `x <= end`.
+ /// It cannot serve as an [`Iterator`] because it doesn't have a starting point.
+ ///
+ /// # Examples
+ ///
+ /// The `..=end` syntax is a `RangeToInclusive`:
+ ///
+ /// ```
+ /// assert_eq!((..=5), std::ops::RangeToInclusive{ end: 5 });
+ /// ```
+ ///
+ /// It does not have an [`IntoIterator`] implementation, so you can't use it in a
+ /// `for` loop directly. This won't compile:
+ ///
+ /// ```compile_fail,E0277
+ /// // error[E0277]: the trait bound `std::ops::RangeToInclusive<{integer}>:
+ /// // std::iter::Iterator` is not satisfied
+ /// for i in ..=5 {
+ ///     // ...
+ /// }
+ /// ```
+ ///
+ /// When used as a [slicing index], `RangeToInclusive` produces a slice of all
+ /// array elements up to and including the index indicated by `end`.
+ ///
+ /// ```
+ /// let arr = [0, 1, 2, 3, 4];
+ /// assert_eq!(arr[ ..  ], [0, 1, 2, 3, 4]);
+ /// assert_eq!(arr[ .. 3], [0, 1, 2      ]);
+ /// assert_eq!(arr[ ..=3], [0, 1, 2, 3   ]); // This is a `RangeToInclusive`
+ /// assert_eq!(arr[1..  ], [   1, 2, 3, 4]);
+ /// assert_eq!(arr[1.. 3], [   1, 2      ]);
+ /// assert_eq!(arr[1..=3], [   1, 2, 3   ]);
+ /// ```
+ ///
+ /// [slicing index]: crate::slice::SliceIndex
+ #[lang = "RangeToInclusive"]
+ #[doc(alias = "..=")]
+ #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ pub struct RangeToInclusive<Idx> {
+     /// The upper bound of the range (inclusive)
+     #[stable(feature = "inclusive_range", since = "1.26.0")]
+     pub end: Idx,
+ }
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ impl<Idx: fmt::Debug> fmt::Debug for RangeToInclusive<Idx> {
+     fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(fmt, "..=")?;
+         self.end.fmt(fmt)?;
+         Ok(())
+     }
+ }
+ 
+ impl<Idx: PartialOrd<Idx>> RangeToInclusive<Idx> {
+     /// Returns `true` if `item` is contained in the range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!( (..=5).contains(&-1_000_000_000));
+     /// assert!( (..=5).contains(&5));
+     /// assert!(!(..=5).contains(&6));
+     ///
+     /// assert!( (..=1.0).contains(&1.0));
+     /// assert!(!(..=1.0).contains(&f32::NAN));
+     /// assert!(!(..=f32::NAN).contains(&0.5));
+     /// ```
+     #[stable(feature = "range_contains", since = "1.35.0")]
+     pub fn contains<U>(&self, item: &U) -> bool
+     where
+         Idx: PartialOrd<U>,
+         U: ?Sized + PartialOrd<Idx>,
+     {
+         <Self as RangeBounds<Idx>>::contains(self, item)
+     }
+ }
+ 
+ // RangeToInclusive<Idx> cannot impl From<RangeTo<Idx>>
+ // because underflow would be possible with (..0).into()
+ 
+ /// An endpoint of a range of keys.
+ ///
+ /// # Examples
+ ///
+ /// `Bound`s are range endpoints:
+ ///
+ /// ```
+ /// use std::ops::Bound::*;
+ /// use std::ops::RangeBounds;
+ ///
+ /// assert_eq!((..100).start_bound(), Unbounded);
+ /// assert_eq!((1..12).start_bound(), Included(&1));
+ /// assert_eq!((1..12).end_bound(), Excluded(&12));
+ /// ```
+ ///
+ /// Using a tuple of `Bound`s as an argument to [`BTreeMap::range`].
+ /// Note that in most cases, it's better to use range syntax (`1..5`) instead.
+ ///
+ /// ```
+ /// use std::collections::BTreeMap;
+ /// use std::ops::Bound::{Excluded, Included, Unbounded};
+ ///
+ /// let mut map = BTreeMap::new();
+ /// map.insert(3, "a");
+ /// map.insert(5, "b");
+ /// map.insert(8, "c");
+ ///
+ /// for (key, value) in map.range((Excluded(3), Included(8))) {
+ ///     println!("{}: {}", key, value);
+ /// }
+ ///
+ /// assert_eq!(Some((&3, &"a")), map.range((Unbounded, Included(5))).next());
+ /// ```
+ ///
+ /// [`BTreeMap::range`]: ../../std/collections/btree_map/struct.BTreeMap.html#method.range
+ #[stable(feature = "collections_bound", since = "1.17.0")]
+ #[derive(Clone, Copy, Debug, Hash, PartialEq, Eq)]
+ pub enum Bound<T> {
+     /// An inclusive bound.
+     #[stable(feature = "collections_bound", since = "1.17.0")]
+     Included(#[stable(feature = "collections_bound", since = "1.17.0")] T),
+     /// An exclusive bound.
+     #[stable(feature = "collections_bound", since = "1.17.0")]
+     Excluded(#[stable(feature = "collections_bound", since = "1.17.0")] T),
+     /// An infinite endpoint. Indicates that there is no bound in this direction.
+     #[stable(feature = "collections_bound", since = "1.17.0")]
+     Unbounded,
+ }
+ 
+ impl<T: Clone> Bound<&T> {
+     /// Map a `Bound<&T>` to a `Bound<T>` by cloning the contents of the bound.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(bound_cloned)]
+     /// use std::ops::Bound::*;
+     /// use std::ops::RangeBounds;
+     ///
+     /// assert_eq!((1..12).start_bound(), Included(&1));
+     /// assert_eq!((1..12).start_bound().cloned(), Included(1));
+     /// ```
+     #[unstable(feature = "bound_cloned", issue = "61356")]
+     pub fn cloned(self) -> Bound<T> {
+         match self {
+             Bound::Unbounded => Bound::Unbounded,
+             Bound::Included(x) => Bound::Included(x.clone()),
+             Bound::Excluded(x) => Bound::Excluded(x.clone()),
+         }
+     }
+ }
+ 
+ /// `RangeBounds` is implemented by Rust's built-in range types, produced
+ /// by range syntax like `..`, `a..`, `..b`, `..=c`, `d..e`, or `f..=g`.
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ pub trait RangeBounds<T: ?Sized> {
+     /// Start index bound.
+     ///
+     /// Returns the start value as a `Bound`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// # fn main() {
+     /// use std::ops::Bound::*;
+     /// use std::ops::RangeBounds;
+     ///
+     /// assert_eq!((..10).start_bound(), Unbounded);
+     /// assert_eq!((3..10).start_bound(), Included(&3));
+     /// # }
+     /// ```
+     #[stable(feature = "collections_range", since = "1.28.0")]
+     fn start_bound(&self) -> Bound<&T>;
+ 
+     /// End index bound.
+     ///
+     /// Returns the end value as a `Bound`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// # fn main() {
+     /// use std::ops::Bound::*;
+     /// use std::ops::RangeBounds;
+     ///
+     /// assert_eq!((3..).end_bound(), Unbounded);
+     /// assert_eq!((3..10).end_bound(), Excluded(&10));
+     /// # }
+     /// ```
+     #[stable(feature = "collections_range", since = "1.28.0")]
+     fn end_bound(&self) -> Bound<&T>;
+ 
+     /// Performs bounds-checking of this range.
+     ///
+     /// The returned [`Range`] is safe to pass to [`slice::get_unchecked`] and
+     /// [`slice::get_unchecked_mut`] for slices of the given length.
+     ///
+     /// [`slice::get_unchecked`]: ../../std/primitive.slice.html#method.get_unchecked
+     /// [`slice::get_unchecked_mut`]: ../../std/primitive.slice.html#method.get_unchecked_mut
+     ///
+     /// # Panics
+     ///
+     /// Panics if the range would be out of bounds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(range_bounds_assert_len)]
+     ///
+     /// use std::ops::RangeBounds;
+     ///
+     /// let v = [10, 40, 30];
+     /// assert_eq!(1..2, (1..2).assert_len(v.len()));
+     /// assert_eq!(0..2, (..2).assert_len(v.len()));
+     /// assert_eq!(1..3, (1..).assert_len(v.len()));
+     /// ```
+     ///
+     /// Panics when [`Index::index`] would panic:
+     ///
+     /// ```should_panic
+     /// #![feature(range_bounds_assert_len)]
+     ///
+     /// use std::ops::RangeBounds;
+     ///
+     /// (2..1).assert_len(3);
+     /// ```
+     ///
+     /// ```should_panic
+     /// #![feature(range_bounds_assert_len)]
+     ///
+     /// use std::ops::RangeBounds;
+     ///
+     /// (1..4).assert_len(3);
+     /// ```
+     ///
+     /// ```should_panic
+     /// #![feature(range_bounds_assert_len)]
+     ///
+     /// use std::ops::RangeBounds;
+     ///
+     /// (1..=usize::MAX).assert_len(3);
+     /// ```
+     ///
+     /// [`Index::index`]: crate::ops::Index::index
+     #[track_caller]
+     #[unstable(feature = "range_bounds_assert_len", issue = "76393")]
+     fn assert_len(self, len: usize) -> Range<usize>
+     where
+         Self: RangeBounds<usize>,
+     {
+         let start: Bound<&usize> = self.start_bound();
+         let start = match start {
+             Bound::Included(&start) => start,
+             Bound::Excluded(start) => {
+                 start.checked_add(1).unwrap_or_else(|| slice_start_index_overflow_fail())
+             }
+             Bound::Unbounded => 0,
+         };
+ 
+         let end: Bound<&usize> = self.end_bound();
+         let end = match end {
+             Bound::Included(end) => {
+                 end.checked_add(1).unwrap_or_else(|| slice_end_index_overflow_fail())
+             }
+             Bound::Excluded(&end) => end,
+             Bound::Unbounded => len,
+         };
+ 
+         if start > end {
+             slice_index_order_fail(start, end);
+         }
+         if end > len {
+             slice_end_index_len_fail(end, len);
+         }
+ 
+         Range { start, end }
+     }
+ 
+     /// Returns `true` if `item` is contained in the range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!( (3..5).contains(&4));
+     /// assert!(!(3..5).contains(&2));
+     ///
+     /// assert!( (0.0..1.0).contains(&0.5));
+     /// assert!(!(0.0..1.0).contains(&f32::NAN));
+     /// assert!(!(0.0..f32::NAN).contains(&0.5));
+     /// assert!(!(f32::NAN..1.0).contains(&0.5));
+     #[stable(feature = "range_contains", since = "1.35.0")]
+     fn contains<U>(&self, item: &U) -> bool
+     where
+         T: PartialOrd<U>,
+         U: ?Sized + PartialOrd<T>,
+     {
+         (match self.start_bound() {
+             Included(ref start) => *start <= item,
+             Excluded(ref start) => *start < item,
+             Unbounded => true,
+         }) && (match self.end_bound() {
+             Included(ref end) => item <= *end,
+             Excluded(ref end) => item < *end,
+             Unbounded => true,
+         })
+     }
+ }
+ 
+ use self::Bound::{Excluded, Included, Unbounded};
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T: ?Sized> RangeBounds<T> for RangeFull {
+     fn start_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeFrom<T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Included(&self.start)
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeTo<T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Excluded(&self.end)
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for Range<T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Included(&self.start)
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Excluded(&self.end)
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeInclusive<T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Included(&self.start)
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         if self.exhausted {
+             // When the iterator is exhausted, we usually have start == end,
+             // but we want the range to appear empty, containing nothing.
+             Excluded(&self.end)
+         } else {
+             Included(&self.end)
+         }
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeToInclusive<T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Included(&self.end)
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for (Bound<T>, Bound<T>) {
+     fn start_bound(&self) -> Bound<&T> {
+         match *self {
+             (Included(ref start), _) => Included(start),
+             (Excluded(ref start), _) => Excluded(start),
+             (Unbounded, _) => Unbounded,
+         }
+     }
+ 
+     fn end_bound(&self) -> Bound<&T> {
+         match *self {
+             (_, Included(ref end)) => Included(end),
+             (_, Excluded(ref end)) => Excluded(end),
+             (_, Unbounded) => Unbounded,
+         }
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<'a, T: ?Sized + 'a> RangeBounds<T> for (Bound<&'a T>, Bound<&'a T>) {
+     fn start_bound(&self) -> Bound<&T> {
+         self.0
+     }
+ 
+     fn end_bound(&self) -> Bound<&T> {
+         self.1
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeFrom<&T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Included(self.start)
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeTo<&T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Excluded(self.end)
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for Range<&T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Included(self.start)
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Excluded(self.end)
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeInclusive<&T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Included(self.start)
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Included(self.end)
+     }
+ }
+ 
+ #[stable(feature = "collections_range", since = "1.28.0")]
+ impl<T> RangeBounds<T> for RangeToInclusive<&T> {
+     fn start_bound(&self) -> Bound<&T> {
+         Unbounded
+     }
+     fn end_bound(&self) -> Bound<&T> {
+         Included(self.end)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/try.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/try.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/try.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/try.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,61 ----
+ /// A trait for customizing the behavior of the `?` operator.
+ ///
+ /// A type implementing `Try` is one that has a canonical way to view it
+ /// in terms of a success/failure dichotomy. This trait allows both
+ /// extracting those success or failure values from an existing instance and
+ /// creating a new instance from a success or failure value.
+ #[unstable(feature = "try_trait", issue = "42327")]
+ #[rustc_on_unimplemented(
+     on(
+         all(
+             any(from_method = "from_error", from_method = "from_ok"),
+             from_desugaring = "QuestionMark"
+         ),
+         message = "the `?` operator can only be used in {ItemContext} \
+                     that returns `Result` or `Option` \
+                     (or another type that implements `{Try}`)",
+         label = "cannot use the `?` operator in {ItemContext} that returns `{Self}`",
+         enclosing_scope = "this function should return `Result` or `Option` to accept `?`"
+     ),
+     on(
+         all(from_method = "into_result", from_desugaring = "QuestionMark"),
+         message = "the `?` operator can only be applied to values \
+                     that implement `{Try}`",
+         label = "the `?` operator cannot be applied to type `{Self}`"
+     )
+ )]
+ #[doc(alias = "?")]
+ #[lang = "try"]
+ pub trait Try {
+     /// The type of this value when viewed as successful.
+     #[unstable(feature = "try_trait", issue = "42327")]
+     type Ok;
+     /// The type of this value when viewed as failed.
+     #[unstable(feature = "try_trait", issue = "42327")]
+     type Error;
+ 
+     /// Applies the "?" operator. A return of `Ok(t)` means that the
+     /// execution should continue normally, and the result of `?` is the
+     /// value `t`. A return of `Err(e)` means that execution should branch
+     /// to the innermost enclosing `catch`, or return from the function.
+     ///
+     /// If an `Err(e)` result is returned, the value `e` will be "wrapped"
+     /// in the return type of the enclosing scope (which must itself implement
+     /// `Try`). Specifically, the value `X::from_error(From::from(e))`
+     /// is returned, where `X` is the return type of the enclosing function.
+     #[lang = "into_result"]
+     #[unstable(feature = "try_trait", issue = "42327")]
+     fn into_result(self) -> Result<Self::Ok, Self::Error>;
+ 
+     /// Wrap an error value to construct the composite result. For example,
+     /// `Result::Err(x)` and `Result::from_error(x)` are equivalent.
+     #[lang = "from_error"]
+     #[unstable(feature = "try_trait", issue = "42327")]
+     fn from_error(v: Self::Error) -> Self;
+ 
+     /// Wrap an OK value to construct the composite result. For example,
+     /// `Result::Ok(x)` and `Result::from_ok(x)` are equivalent.
+     #[lang = "from_ok"]
+     #[unstable(feature = "try_trait", issue = "42327")]
+     fn from_ok(v: Self::Ok) -> Self;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ops/unsize.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ops/unsize.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ops/unsize.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ops/unsize.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,101 ----
+ use crate::marker::Unsize;
+ 
+ /// Trait that indicates that this is a pointer or a wrapper for one,
+ /// where unsizing can be performed on the pointee.
+ ///
+ /// See the [DST coercion RFC][dst-coerce] and [the nomicon entry on coercion][nomicon-coerce]
+ /// for more details.
+ ///
+ /// For builtin pointer types, pointers to `T` will coerce to pointers to `U` if `T: Unsize<U>`
+ /// by converting from a thin pointer to a fat pointer.
+ ///
+ /// For custom types, the coercion here works by coercing `Foo<T>` to `Foo<U>`
+ /// provided an impl of `CoerceUnsized<Foo<U>> for Foo<T>` exists.
+ /// Such an impl can only be written if `Foo<T>` has only a single non-phantomdata
+ /// field involving `T`. If the type of that field is `Bar<T>`, an implementation
+ /// of `CoerceUnsized<Bar<U>> for Bar<T>` must exist. The coercion will work by
+ /// coercing the `Bar<T>` field into `Bar<U>` and filling in the rest of the fields
+ /// from `Foo<T>` to create a `Foo<U>`. This will effectively drill down to a pointer
+ /// field and coerce that.
+ ///
+ /// Generally, for smart pointers you will implement
+ /// `CoerceUnsized<Ptr<U>> for Ptr<T> where T: Unsize<U>, U: ?Sized`, with an
+ /// optional `?Sized` bound on `T` itself. For wrapper types that directly embed `T`
+ /// like `Cell<T>` and `RefCell<T>`, you
+ /// can directly implement `CoerceUnsized<Wrap<U>> for Wrap<T> where T: CoerceUnsized<U>`.
+ /// This will let coercions of types like `Cell<Box<T>>` work.
+ ///
+ /// [`Unsize`][unsize] is used to mark types which can be coerced to DSTs if behind
+ /// pointers. It is implemented automatically by the compiler.
+ ///
+ /// [dst-coerce]: https://github.com/rust-lang/rfcs/blob/master/text/0982-dst-coercion.md
+ /// [unsize]: crate::marker::Unsize
+ /// [nomicon-coerce]: ../../nomicon/coercions.html
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ #[lang = "coerce_unsized"]
+ pub trait CoerceUnsized<T: ?Sized> {
+     // Empty.
+ }
+ 
+ // &mut T -> &mut U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'a, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<&'a mut U> for &'a mut T {}
+ // &mut T -> &U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'a, 'b: 'a, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<&'a U> for &'b mut T {}
+ // &mut T -> *mut U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'a, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<*mut U> for &'a mut T {}
+ // &mut T -> *const U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'a, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<*const U> for &'a mut T {}
+ 
+ // &T -> &U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'a, 'b: 'a, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<&'a U> for &'b T {}
+ // &T -> *const U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<'a, T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<*const U> for &'a T {}
+ 
+ // *mut T -> *mut U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<*mut U> for *mut T {}
+ // *mut T -> *const U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<*const U> for *mut T {}
+ 
+ // *const T -> *const U
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: ?Sized + Unsize<U>, U: ?Sized> CoerceUnsized<*const U> for *const T {}
+ 
+ /// This is used for object safety, to check that a method's receiver type can be dispatched on.
+ ///
+ /// An example implementation of the trait:
+ ///
+ /// ```
+ /// # #![feature(dispatch_from_dyn, unsize)]
+ /// # use std::{ops::DispatchFromDyn, marker::Unsize};
+ /// # struct Rc<T: ?Sized>(std::rc::Rc<T>);
+ /// impl<T: ?Sized, U: ?Sized> DispatchFromDyn<Rc<U>> for Rc<T>
+ /// where
+ ///     T: Unsize<U>,
+ /// {}
+ /// ```
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ #[lang = "dispatch_from_dyn"]
+ pub trait DispatchFromDyn<T> {
+     // Empty.
+ }
+ 
+ // &T -> &U
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ impl<'a, T: ?Sized + Unsize<U>, U: ?Sized> DispatchFromDyn<&'a U> for &'a T {}
+ // &mut T -> &mut U
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ impl<'a, T: ?Sized + Unsize<U>, U: ?Sized> DispatchFromDyn<&'a mut U> for &'a mut T {}
+ // *const T -> *const U
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ impl<T: ?Sized + Unsize<U>, U: ?Sized> DispatchFromDyn<*const U> for *const T {}
+ // *mut T -> *mut U
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ impl<T: ?Sized + Unsize<U>, U: ?Sized> DispatchFromDyn<*mut U> for *mut T {}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/option.rs gcc-16-20251102/libgrust/rustc-lib/core/src/option.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/option.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/option.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1720 ----
+ //! Optional values.
+ //!
+ //! Type [`Option`] represents an optional value: every [`Option`]
+ //! is either [`Some`] and contains a value, or [`None`], and
+ //! does not. [`Option`] types are very common in Rust code, as
+ //! they have a number of uses:
+ //!
+ //! * Initial values
+ //! * Return values for functions that are not defined
+ //!   over their entire input range (partial functions)
+ //! * Return value for otherwise reporting simple errors, where [`None`] is
+ //!   returned on error
+ //! * Optional struct fields
+ //! * Struct fields that can be loaned or "taken"
+ //! * Optional function arguments
+ //! * Nullable pointers
+ //! * Swapping things out of difficult situations
+ //!
+ //! [`Option`]s are commonly paired with pattern matching to query the presence
+ //! of a value and take action, always accounting for the [`None`] case.
+ //!
+ //! ```
+ //! fn divide(numerator: f64, denominator: f64) -> Option<f64> {
+ //!     if denominator == 0.0 {
+ //!         None
+ //!     } else {
+ //!         Some(numerator / denominator)
+ //!     }
+ //! }
+ //!
+ //! // The return value of the function is an option
+ //! let result = divide(2.0, 3.0);
+ //!
+ //! // Pattern match to retrieve the value
+ //! match result {
+ //!     // The division was valid
+ //!     Some(x) => println!("Result: {}", x),
+ //!     // The division was invalid
+ //!     None    => println!("Cannot divide by 0"),
+ //! }
+ //! ```
+ //!
+ //
+ // FIXME: Show how `Option` is used in practice, with lots of methods
+ //
+ //! # Options and pointers ("nullable" pointers)
+ //!
+ //! Rust's pointer types must always point to a valid location; there are
+ //! no "null" references. Instead, Rust has *optional* pointers, like
+ //! the optional owned box, [`Option`]`<`[`Box<T>`]`>`.
+ //!
+ //! The following example uses [`Option`] to create an optional box of
+ //! [`i32`]. Notice that in order to use the inner [`i32`] value first, the
+ //! `check_optional` function needs to use pattern matching to
+ //! determine whether the box has a value (i.e., it is [`Some(...)`][`Some`]) or
+ //! not ([`None`]).
+ //!
+ //! ```
+ //! let optional = None;
+ //! check_optional(optional);
+ //!
+ //! let optional = Some(Box::new(9000));
+ //! check_optional(optional);
+ //!
+ //! fn check_optional(optional: Option<Box<i32>>) {
+ //!     match optional {
+ //!         Some(p) => println!("has value {}", p),
+ //!         None => println!("has no value"),
+ //!     }
+ //! }
+ //! ```
+ //!
+ //! # Representation
+ //!
+ //! Rust guarantees to optimize the following types `T` such that
+ //! [`Option<T>`] has the same size as `T`:
+ //!
+ //! * [`Box<U>`]
+ //! * `&U`
+ //! * `&mut U`
+ //! * `fn`, `extern "C" fn`
+ //! * [`num::NonZero*`]
+ //! * [`ptr::NonNull<U>`]
+ //! * `#[repr(transparent)]` struct around one of the types in this list.
+ //!
+ //! It is further guaranteed that, for the cases above, one can
+ //! [`mem::transmute`] from all valid values of `T` to `Option<T>` and
+ //! from `Some::<T>(_)` to `T` (but transmuting `None::<T>` to `T`
+ //! is undefined behaviour).
+ //!
+ //! # Examples
+ //!
+ //! Basic pattern matching on [`Option`]:
+ //!
+ //! ```
+ //! let msg = Some("howdy");
+ //!
+ //! // Take a reference to the contained string
+ //! if let Some(m) = &msg {
+ //!     println!("{}", *m);
+ //! }
+ //!
+ //! // Remove the contained string, destroying the Option
+ //! let unwrapped_msg = msg.unwrap_or("default message");
+ //! ```
+ //!
+ //! Initialize a result to [`None`] before a loop:
+ //!
+ //! ```
+ //! enum Kingdom { Plant(u32, &'static str), Animal(u32, &'static str) }
+ //!
+ //! // A list of data to search through.
+ //! let all_the_big_things = [
+ //!     Kingdom::Plant(250, "redwood"),
+ //!     Kingdom::Plant(230, "noble fir"),
+ //!     Kingdom::Plant(229, "sugar pine"),
+ //!     Kingdom::Animal(25, "blue whale"),
+ //!     Kingdom::Animal(19, "fin whale"),
+ //!     Kingdom::Animal(15, "north pacific right whale"),
+ //! ];
+ //!
+ //! // We're going to search for the name of the biggest animal,
+ //! // but to start with we've just got `None`.
+ //! let mut name_of_biggest_animal = None;
+ //! let mut size_of_biggest_animal = 0;
+ //! for big_thing in &all_the_big_things {
+ //!     match *big_thing {
+ //!         Kingdom::Animal(size, name) if size > size_of_biggest_animal => {
+ //!             // Now we've found the name of some big animal
+ //!             size_of_biggest_animal = size;
+ //!             name_of_biggest_animal = Some(name);
+ //!         }
+ //!         Kingdom::Animal(..) | Kingdom::Plant(..) => ()
+ //!     }
+ //! }
+ //!
+ //! match name_of_biggest_animal {
+ //!     Some(name) => println!("the biggest animal is {}", name),
+ //!     None => println!("there are no animals :("),
+ //! }
+ //! ```
+ //!
+ //! [`Box<T>`]: ../../std/boxed/struct.Box.html
+ //! [`Box<U>`]: ../../std/boxed/struct.Box.html
+ //! [`num::NonZero*`]: crate::num
+ //! [`ptr::NonNull<U>`]: crate::ptr::NonNull
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::iter::{FromIterator, FusedIterator, TrustedLen};
+ use crate::pin::Pin;
+ use crate::{
+     convert, fmt, hint, mem,
+     ops::{self, Deref, DerefMut},
+ };
+ 
+ /// The `Option` type. See [the module level documentation](self) for more.
+ #[derive(Copy, PartialEq, PartialOrd, Eq, Ord, Debug, Hash)]
+ #[rustc_diagnostic_item = "option_type"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub enum Option<T> {
+     /// No value
+     #[lang = "None"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     None,
+     /// Some value `T`
+     #[lang = "Some"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Some(#[stable(feature = "rust1", since = "1.0.0")] T),
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Type implementation
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ impl<T> Option<T> {
+     /////////////////////////////////////////////////////////////////////////
+     // Querying the contained values
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns `true` if the option is a [`Some`] value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x: Option<u32> = Some(2);
+     /// assert_eq!(x.is_some(), true);
+     ///
+     /// let x: Option<u32> = None;
+     /// assert_eq!(x.is_some(), false);
+     /// ```
+     #[must_use = "if you intended to assert that this has a value, consider `.unwrap()` instead"]
+     #[inline]
+     #[rustc_const_stable(feature = "const_option", since = "1.48.0")]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn is_some(&self) -> bool {
+         matches!(*self, Some(_))
+     }
+ 
+     /// Returns `true` if the option is a [`None`] value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x: Option<u32> = Some(2);
+     /// assert_eq!(x.is_none(), false);
+     ///
+     /// let x: Option<u32> = None;
+     /// assert_eq!(x.is_none(), true);
+     /// ```
+     #[must_use = "if you intended to assert that this doesn't have a value, consider \
+                   `.and_then(|| panic!(\"`Option` had a value when expected `None`\"))` instead"]
+     #[inline]
+     #[rustc_const_stable(feature = "const_option", since = "1.48.0")]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn is_none(&self) -> bool {
+         !self.is_some()
+     }
+ 
+     /// Returns `true` if the option is a [`Some`] value containing the given value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(option_result_contains)]
+     ///
+     /// let x: Option<u32> = Some(2);
+     /// assert_eq!(x.contains(&2), true);
+     ///
+     /// let x: Option<u32> = Some(3);
+     /// assert_eq!(x.contains(&2), false);
+     ///
+     /// let x: Option<u32> = None;
+     /// assert_eq!(x.contains(&2), false);
+     /// ```
+     #[must_use]
+     #[inline]
+     #[unstable(feature = "option_result_contains", issue = "62358")]
+     pub fn contains<U>(&self, x: &U) -> bool
+     where
+         U: PartialEq<T>,
+     {
+         match self {
+             Some(y) => x == y,
+             None => false,
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Adapter for working with references
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Converts from `&Option<T>` to `Option<&T>`.
+     ///
+     /// # Examples
+     ///
+     /// Converts an `Option<`[`String`]`>` into an `Option<`[`usize`]`>`, preserving the original.
+     /// The [`map`] method takes the `self` argument by value, consuming the original,
+     /// so this technique uses `as_ref` to first take an `Option` to a reference
+     /// to the value inside the original.
+     ///
+     /// [`map`]: Option::map
+     /// [`String`]: ../../std/string/struct.String.html
+     ///
+     /// ```
+     /// let text: Option<String> = Some("Hello, world!".to_string());
+     /// // First, cast `Option<String>` to `Option<&String>` with `as_ref`,
+     /// // then consume *that* with `map`, leaving `text` on the stack.
+     /// let text_length: Option<usize> = text.as_ref().map(|s| s.len());
+     /// println!("still can print text: {:?}", text);
+     /// ```
+     #[inline]
+     #[rustc_const_stable(feature = "const_option", since = "1.48.0")]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn as_ref(&self) -> Option<&T> {
+         match *self {
+             Some(ref x) => Some(x),
+             None => None,
+         }
+     }
+ 
+     /// Converts from `&mut Option<T>` to `Option<&mut T>`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = Some(2);
+     /// match x.as_mut() {
+     ///     Some(v) => *v = 42,
+     ///     None => {},
+     /// }
+     /// assert_eq!(x, Some(42));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn as_mut(&mut self) -> Option<&mut T> {
+         match *self {
+             Some(ref mut x) => Some(x),
+             None => None,
+         }
+     }
+ 
+     /// Converts from [`Pin`]`<&Option<T>>` to `Option<`[`Pin`]`<&T>>`.
+     #[inline]
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub fn as_pin_ref(self: Pin<&Self>) -> Option<Pin<&T>> {
+         // SAFETY: `x` is guaranteed to be pinned because it comes from `self`
+         // which is pinned.
+         unsafe { Pin::get_ref(self).as_ref().map(|x| Pin::new_unchecked(x)) }
+     }
+ 
+     /// Converts from [`Pin`]`<&mut Option<T>>` to `Option<`[`Pin`]`<&mut T>>`.
+     #[inline]
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub fn as_pin_mut(self: Pin<&mut Self>) -> Option<Pin<&mut T>> {
+         // SAFETY: `get_unchecked_mut` is never used to move the `Option` inside `self`.
+         // `x` is guaranteed to be pinned because it comes from `self` which is pinned.
+         unsafe { Pin::get_unchecked_mut(self).as_mut().map(|x| Pin::new_unchecked(x)) }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Getting to contained values
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns the contained [`Some`] value, consuming the `self` value.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is a [`None`] with a custom panic message provided by
+     /// `msg`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some("value");
+     /// assert_eq!(x.expect("fruits are healthy"), "value");
+     /// ```
+     ///
+     /// ```{.should_panic}
+     /// let x: Option<&str> = None;
+     /// x.expect("fruits are healthy"); // panics with `fruits are healthy`
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn expect(self, msg: &str) -> T {
+         match self {
+             Some(val) => val,
+             None => expect_failed(msg),
+         }
+     }
+ 
+     /// Returns the contained [`Some`] value, consuming the `self` value.
+     ///
+     /// Because this function may panic, its use is generally discouraged.
+     /// Instead, prefer to use pattern matching and handle the [`None`]
+     /// case explicitly, or call [`unwrap_or`], [`unwrap_or_else`], or
+     /// [`unwrap_or_default`].
+     ///
+     /// [`unwrap_or`]: Option::unwrap_or
+     /// [`unwrap_or_else`]: Option::unwrap_or_else
+     /// [`unwrap_or_default`]: Option::unwrap_or_default
+     ///
+     /// # Panics
+     ///
+     /// Panics if the self value equals [`None`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some("air");
+     /// assert_eq!(x.unwrap(), "air");
+     /// ```
+     ///
+     /// ```{.should_panic}
+     /// let x: Option<&str> = None;
+     /// assert_eq!(x.unwrap(), "air"); // fails
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_option", issue = "67441")]
+     pub const fn unwrap(self) -> T {
+         match self {
+             Some(val) => val,
+             None => panic!("called `Option::unwrap()` on a `None` value"),
+         }
+     }
+ 
+     /// Returns the contained [`Some`] value or a provided default.
+     ///
+     /// Arguments passed to `unwrap_or` are eagerly evaluated; if you are passing
+     /// the result of a function call, it is recommended to use [`unwrap_or_else`],
+     /// which is lazily evaluated.
+     ///
+     /// [`unwrap_or_else`]: Option::unwrap_or_else
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!(Some("car").unwrap_or("bike"), "car");
+     /// assert_eq!(None.unwrap_or("bike"), "bike");
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap_or(self, default: T) -> T {
+         match self {
+             Some(x) => x,
+             None => default,
+         }
+     }
+ 
+     /// Returns the contained [`Some`] value or computes it from a closure.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let k = 10;
+     /// assert_eq!(Some(4).unwrap_or_else(|| 2 * k), 4);
+     /// assert_eq!(None.unwrap_or_else(|| 2 * k), 20);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap_or_else<F: FnOnce() -> T>(self, f: F) -> T {
+         match self {
+             Some(x) => x,
+             None => f(),
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Transforming contained values
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Maps an `Option<T>` to `Option<U>` by applying a function to a contained value.
+     ///
+     /// # Examples
+     ///
+     /// Converts an `Option<`[`String`]`>` into an `Option<`[`usize`]`>`, consuming the original:
+     ///
+     /// [`String`]: ../../std/string/struct.String.html
+     /// ```
+     /// let maybe_some_string = Some(String::from("Hello, World!"));
+     /// // `Option::map` takes self *by value*, consuming `maybe_some_string`
+     /// let maybe_some_len = maybe_some_string.map(|s| s.len());
+     ///
+     /// assert_eq!(maybe_some_len, Some(13));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn map<U, F: FnOnce(T) -> U>(self, f: F) -> Option<U> {
+         match self {
+             Some(x) => Some(f(x)),
+             None => None,
+         }
+     }
+ 
+     /// Applies a function to the contained value (if any),
+     /// or returns the provided default (if not).
+     ///
+     /// Arguments passed to `map_or` are eagerly evaluated; if you are passing
+     /// the result of a function call, it is recommended to use [`map_or_else`],
+     /// which is lazily evaluated.
+     ///
+     /// [`map_or_else`]: Option::map_or_else
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some("foo");
+     /// assert_eq!(x.map_or(42, |v| v.len()), 3);
+     ///
+     /// let x: Option<&str> = None;
+     /// assert_eq!(x.map_or(42, |v| v.len()), 42);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn map_or<U, F: FnOnce(T) -> U>(self, default: U, f: F) -> U {
+         match self {
+             Some(t) => f(t),
+             None => default,
+         }
+     }
+ 
+     /// Applies a function to the contained value (if any),
+     /// or computes a default (if not).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let k = 21;
+     ///
+     /// let x = Some("foo");
+     /// assert_eq!(x.map_or_else(|| 2 * k, |v| v.len()), 3);
+     ///
+     /// let x: Option<&str> = None;
+     /// assert_eq!(x.map_or_else(|| 2 * k, |v| v.len()), 42);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn map_or_else<U, D: FnOnce() -> U, F: FnOnce(T) -> U>(self, default: D, f: F) -> U {
+         match self {
+             Some(t) => f(t),
+             None => default(),
+         }
+     }
+ 
+     /// Transforms the `Option<T>` into a [`Result<T, E>`], mapping [`Some(v)`] to
+     /// [`Ok(v)`] and [`None`] to [`Err(err)`].
+     ///
+     /// Arguments passed to `ok_or` are eagerly evaluated; if you are passing the
+     /// result of a function call, it is recommended to use [`ok_or_else`], which is
+     /// lazily evaluated.
+     ///
+     /// [`Result<T, E>`]: Result
+     /// [`Ok(v)`]: Ok
+     /// [`Err(err)`]: Err
+     /// [`Some(v)`]: Some
+     /// [`ok_or_else`]: Option::ok_or_else
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some("foo");
+     /// assert_eq!(x.ok_or(0), Ok("foo"));
+     ///
+     /// let x: Option<&str> = None;
+     /// assert_eq!(x.ok_or(0), Err(0));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn ok_or<E>(self, err: E) -> Result<T, E> {
+         match self {
+             Some(v) => Ok(v),
+             None => Err(err),
+         }
+     }
+ 
+     /// Transforms the `Option<T>` into a [`Result<T, E>`], mapping [`Some(v)`] to
+     /// [`Ok(v)`] and [`None`] to [`Err(err())`].
+     ///
+     /// [`Result<T, E>`]: Result
+     /// [`Ok(v)`]: Ok
+     /// [`Err(err())`]: Err
+     /// [`Some(v)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some("foo");
+     /// assert_eq!(x.ok_or_else(|| 0), Ok("foo"));
+     ///
+     /// let x: Option<&str> = None;
+     /// assert_eq!(x.ok_or_else(|| 0), Err(0));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn ok_or_else<E, F: FnOnce() -> E>(self, err: F) -> Result<T, E> {
+         match self {
+             Some(v) => Ok(v),
+             None => Err(err()),
+         }
+     }
+ 
+     /// Inserts `value` into the option then returns a mutable reference to it.
+     ///
+     /// If the option already contains a value, the old value is dropped.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// #![feature(option_insert)]
+     ///
+     /// let mut opt = None;
+     /// let val = opt.insert(1);
+     /// assert_eq!(*val, 1);
+     /// assert_eq!(opt.unwrap(), 1);
+     /// let val = opt.insert(2);
+     /// assert_eq!(*val, 2);
+     /// *val = 3;
+     /// assert_eq!(opt.unwrap(), 3);
+     /// ```
+     #[inline]
+     #[unstable(feature = "option_insert", reason = "newly added", issue = "78271")]
+     pub fn insert(&mut self, value: T) -> &mut T {
+         *self = Some(value);
+ 
+         match self {
+             Some(v) => v,
+             // SAFETY: the code above just filled the option
+             None => unsafe { hint::unreachable_unchecked() },
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Iterator constructors
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns an iterator over the possibly contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some(4);
+     /// assert_eq!(x.iter().next(), Some(&4));
+     ///
+     /// let x: Option<u32> = None;
+     /// assert_eq!(x.iter().next(), None);
+     /// ```
+     #[inline]
+     #[rustc_const_unstable(feature = "const_option", issue = "67441")]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn iter(&self) -> Iter<'_, T> {
+         Iter { inner: Item { opt: self.as_ref() } }
+     }
+ 
+     /// Returns a mutable iterator over the possibly contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = Some(4);
+     /// match x.iter_mut().next() {
+     ///     Some(v) => *v = 42,
+     ///     None => {},
+     /// }
+     /// assert_eq!(x, Some(42));
+     ///
+     /// let mut x: Option<u32> = None;
+     /// assert_eq!(x.iter_mut().next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn iter_mut(&mut self) -> IterMut<'_, T> {
+         IterMut { inner: Item { opt: self.as_mut() } }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Boolean operations on the values, eager and lazy
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns [`None`] if the option is [`None`], otherwise returns `optb`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some(2);
+     /// let y: Option<&str> = None;
+     /// assert_eq!(x.and(y), None);
+     ///
+     /// let x: Option<u32> = None;
+     /// let y = Some("foo");
+     /// assert_eq!(x.and(y), None);
+     ///
+     /// let x = Some(2);
+     /// let y = Some("foo");
+     /// assert_eq!(x.and(y), Some("foo"));
+     ///
+     /// let x: Option<u32> = None;
+     /// let y: Option<&str> = None;
+     /// assert_eq!(x.and(y), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn and<U>(self, optb: Option<U>) -> Option<U> {
+         match self {
+             Some(_) => optb,
+             None => None,
+         }
+     }
+ 
+     /// Returns [`None`] if the option is [`None`], otherwise calls `f` with the
+     /// wrapped value and returns the result.
+     ///
+     /// Some languages call this operation flatmap.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// fn sq(x: u32) -> Option<u32> { Some(x * x) }
+     /// fn nope(_: u32) -> Option<u32> { None }
+     ///
+     /// assert_eq!(Some(2).and_then(sq).and_then(sq), Some(16));
+     /// assert_eq!(Some(2).and_then(sq).and_then(nope), None);
+     /// assert_eq!(Some(2).and_then(nope).and_then(sq), None);
+     /// assert_eq!(None.and_then(sq).and_then(sq), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn and_then<U, F: FnOnce(T) -> Option<U>>(self, f: F) -> Option<U> {
+         match self {
+             Some(x) => f(x),
+             None => None,
+         }
+     }
+ 
+     /// Returns [`None`] if the option is [`None`], otherwise calls `predicate`
+     /// with the wrapped value and returns:
+     ///
+     /// - [`Some(t)`] if `predicate` returns `true` (where `t` is the wrapped
+     ///   value), and
+     /// - [`None`] if `predicate` returns `false`.
+     ///
+     /// This function works similar to [`Iterator::filter()`]. You can imagine
+     /// the `Option<T>` being an iterator over one or zero elements. `filter()`
+     /// lets you decide which elements to keep.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// fn is_even(n: &i32) -> bool {
+     ///     n % 2 == 0
+     /// }
+     ///
+     /// assert_eq!(None.filter(is_even), None);
+     /// assert_eq!(Some(3).filter(is_even), None);
+     /// assert_eq!(Some(4).filter(is_even), Some(4));
+     /// ```
+     ///
+     /// [`Some(t)`]: Some
+     #[inline]
+     #[stable(feature = "option_filter", since = "1.27.0")]
+     pub fn filter<P: FnOnce(&T) -> bool>(self, predicate: P) -> Self {
+         if let Some(x) = self {
+             if predicate(&x) {
+                 return Some(x);
+             }
+         }
+         None
+     }
+ 
+     /// Returns the option if it contains a value, otherwise returns `optb`.
+     ///
+     /// Arguments passed to `or` are eagerly evaluated; if you are passing the
+     /// result of a function call, it is recommended to use [`or_else`], which is
+     /// lazily evaluated.
+     ///
+     /// [`or_else`]: Option::or_else
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some(2);
+     /// let y = None;
+     /// assert_eq!(x.or(y), Some(2));
+     ///
+     /// let x = None;
+     /// let y = Some(100);
+     /// assert_eq!(x.or(y), Some(100));
+     ///
+     /// let x = Some(2);
+     /// let y = Some(100);
+     /// assert_eq!(x.or(y), Some(2));
+     ///
+     /// let x: Option<u32> = None;
+     /// let y = None;
+     /// assert_eq!(x.or(y), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn or(self, optb: Option<T>) -> Option<T> {
+         match self {
+             Some(_) => self,
+             None => optb,
+         }
+     }
+ 
+     /// Returns the option if it contains a value, otherwise calls `f` and
+     /// returns the result.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// fn nobody() -> Option<&'static str> { None }
+     /// fn vikings() -> Option<&'static str> { Some("vikings") }
+     ///
+     /// assert_eq!(Some("barbarians").or_else(vikings), Some("barbarians"));
+     /// assert_eq!(None.or_else(vikings), Some("vikings"));
+     /// assert_eq!(None.or_else(nobody), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn or_else<F: FnOnce() -> Option<T>>(self, f: F) -> Option<T> {
+         match self {
+             Some(_) => self,
+             None => f(),
+         }
+     }
+ 
+     /// Returns [`Some`] if exactly one of `self`, `optb` is [`Some`], otherwise returns [`None`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some(2);
+     /// let y: Option<u32> = None;
+     /// assert_eq!(x.xor(y), Some(2));
+     ///
+     /// let x: Option<u32> = None;
+     /// let y = Some(2);
+     /// assert_eq!(x.xor(y), Some(2));
+     ///
+     /// let x = Some(2);
+     /// let y = Some(2);
+     /// assert_eq!(x.xor(y), None);
+     ///
+     /// let x: Option<u32> = None;
+     /// let y: Option<u32> = None;
+     /// assert_eq!(x.xor(y), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "option_xor", since = "1.37.0")]
+     pub fn xor(self, optb: Option<T>) -> Option<T> {
+         match (self, optb) {
+             (Some(a), None) => Some(a),
+             (None, Some(b)) => Some(b),
+             _ => None,
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Entry-like operations to insert if None and return a reference
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Inserts `value` into the option if it is [`None`], then
+     /// returns a mutable reference to the contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = None;
+     ///
+     /// {
+     ///     let y: &mut u32 = x.get_or_insert(5);
+     ///     assert_eq!(y, &5);
+     ///
+     ///     *y = 7;
+     /// }
+     ///
+     /// assert_eq!(x, Some(7));
+     /// ```
+     #[inline]
+     #[stable(feature = "option_entry", since = "1.20.0")]
+     pub fn get_or_insert(&mut self, value: T) -> &mut T {
+         self.get_or_insert_with(|| value)
+     }
+ 
+     /// Inserts a value computed from `f` into the option if it is [`None`],
+     /// then returns a mutable reference to the contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = None;
+     ///
+     /// {
+     ///     let y: &mut u32 = x.get_or_insert_with(|| 5);
+     ///     assert_eq!(y, &5);
+     ///
+     ///     *y = 7;
+     /// }
+     ///
+     /// assert_eq!(x, Some(7));
+     /// ```
+     #[inline]
+     #[stable(feature = "option_entry", since = "1.20.0")]
+     pub fn get_or_insert_with<F: FnOnce() -> T>(&mut self, f: F) -> &mut T {
+         if let None = *self {
+             *self = Some(f());
+         }
+ 
+         match self {
+             Some(v) => v,
+             // SAFETY: a `None` variant for `self` would have been replaced by a `Some`
+             // variant in the code above.
+             None => unsafe { hint::unreachable_unchecked() },
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Misc
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Takes the value out of the option, leaving a [`None`] in its place.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = Some(2);
+     /// let y = x.take();
+     /// assert_eq!(x, None);
+     /// assert_eq!(y, Some(2));
+     ///
+     /// let mut x: Option<u32> = None;
+     /// let y = x.take();
+     /// assert_eq!(x, None);
+     /// assert_eq!(y, None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn take(&mut self) -> Option<T> {
+         mem::take(self)
+     }
+ 
+     /// Replaces the actual value in the option by the value given in parameter,
+     /// returning the old value if present,
+     /// leaving a [`Some`] in its place without deinitializing either one.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = Some(2);
+     /// let old = x.replace(5);
+     /// assert_eq!(x, Some(5));
+     /// assert_eq!(old, Some(2));
+     ///
+     /// let mut x = None;
+     /// let old = x.replace(3);
+     /// assert_eq!(x, Some(3));
+     /// assert_eq!(old, None);
+     /// ```
+     #[inline]
+     #[stable(feature = "option_replace", since = "1.31.0")]
+     pub fn replace(&mut self, value: T) -> Option<T> {
+         mem::replace(self, Some(value))
+     }
+ 
+     /// Zips `self` with another `Option`.
+     ///
+     /// If `self` is `Some(s)` and `other` is `Some(o)`, this method returns `Some((s, o))`.
+     /// Otherwise, `None` is returned.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some(1);
+     /// let y = Some("hi");
+     /// let z = None::<u8>;
+     ///
+     /// assert_eq!(x.zip(y), Some((1, "hi")));
+     /// assert_eq!(x.zip(z), None);
+     /// ```
+     #[stable(feature = "option_zip_option", since = "1.46.0")]
+     pub fn zip<U>(self, other: Option<U>) -> Option<(T, U)> {
+         match (self, other) {
+             (Some(a), Some(b)) => Some((a, b)),
+             _ => None,
+         }
+     }
+ 
+     /// Zips `self` and another `Option` with function `f`.
+     ///
+     /// If `self` is `Some(s)` and `other` is `Some(o)`, this method returns `Some(f(s, o))`.
+     /// Otherwise, `None` is returned.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(option_zip)]
+     ///
+     /// #[derive(Debug, PartialEq)]
+     /// struct Point {
+     ///     x: f64,
+     ///     y: f64,
+     /// }
+     ///
+     /// impl Point {
+     ///     fn new(x: f64, y: f64) -> Self {
+     ///         Self { x, y }
+     ///     }
+     /// }
+     ///
+     /// let x = Some(17.5);
+     /// let y = Some(42.7);
+     ///
+     /// assert_eq!(x.zip_with(y, Point::new), Some(Point { x: 17.5, y: 42.7 }));
+     /// assert_eq!(x.zip_with(None, Point::new), None);
+     /// ```
+     #[unstable(feature = "option_zip", issue = "70086")]
+     pub fn zip_with<U, F, R>(self, other: Option<U>, f: F) -> Option<R>
+     where
+         F: FnOnce(T, U) -> R,
+     {
+         Some(f(self?, other?))
+     }
+ }
+ 
+ impl<T: Copy> Option<&T> {
+     /// Maps an `Option<&T>` to an `Option<T>` by copying the contents of the
+     /// option.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = 12;
+     /// let opt_x = Some(&x);
+     /// assert_eq!(opt_x, Some(&12));
+     /// let copied = opt_x.copied();
+     /// assert_eq!(copied, Some(12));
+     /// ```
+     #[stable(feature = "copied", since = "1.35.0")]
+     pub fn copied(self) -> Option<T> {
+         self.map(|&t| t)
+     }
+ }
+ 
+ impl<T: Copy> Option<&mut T> {
+     /// Maps an `Option<&mut T>` to an `Option<T>` by copying the contents of the
+     /// option.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = 12;
+     /// let opt_x = Some(&mut x);
+     /// assert_eq!(opt_x, Some(&mut 12));
+     /// let copied = opt_x.copied();
+     /// assert_eq!(copied, Some(12));
+     /// ```
+     #[stable(feature = "copied", since = "1.35.0")]
+     pub fn copied(self) -> Option<T> {
+         self.map(|&mut t| t)
+     }
+ }
+ 
+ impl<T: Clone> Option<&T> {
+     /// Maps an `Option<&T>` to an `Option<T>` by cloning the contents of the
+     /// option.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = 12;
+     /// let opt_x = Some(&x);
+     /// assert_eq!(opt_x, Some(&12));
+     /// let cloned = opt_x.cloned();
+     /// assert_eq!(cloned, Some(12));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn cloned(self) -> Option<T> {
+         self.map(|t| t.clone())
+     }
+ }
+ 
+ impl<T: Clone> Option<&mut T> {
+     /// Maps an `Option<&mut T>` to an `Option<T>` by cloning the contents of the
+     /// option.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x = 12;
+     /// let opt_x = Some(&mut x);
+     /// assert_eq!(opt_x, Some(&mut 12));
+     /// let cloned = opt_x.cloned();
+     /// assert_eq!(cloned, Some(12));
+     /// ```
+     #[stable(since = "1.26.0", feature = "option_ref_mut_cloned")]
+     pub fn cloned(self) -> Option<T> {
+         self.map(|t| t.clone())
+     }
+ }
+ 
+ impl<T: fmt::Debug> Option<T> {
+     /// Consumes `self` while expecting [`None`] and returning nothing.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is a [`Some`], with a panic message including the
+     /// passed message, and the content of the [`Some`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(option_expect_none)]
+     ///
+     /// use std::collections::HashMap;
+     /// let mut squares = HashMap::new();
+     /// for i in -10..=10 {
+     ///     // This will not panic, since all keys are unique.
+     ///     squares.insert(i, i * i).expect_none("duplicate key");
+     /// }
+     /// ```
+     ///
+     /// ```{.should_panic}
+     /// #![feature(option_expect_none)]
+     ///
+     /// use std::collections::HashMap;
+     /// let mut sqrts = HashMap::new();
+     /// for i in -10..=10 {
+     ///     // This will panic, since both negative and positive `i` will
+     ///     // insert the same `i * i` key, returning the old `Some(i)`.
+     ///     sqrts.insert(i * i, i).expect_none("duplicate key");
+     /// }
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[unstable(feature = "option_expect_none", reason = "newly added", issue = "62633")]
+     pub fn expect_none(self, msg: &str) {
+         if let Some(val) = self {
+             expect_none_failed(msg, &val);
+         }
+     }
+ 
+     /// Consumes `self` while expecting [`None`] and returning nothing.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is a [`Some`], with a custom panic message provided
+     /// by the [`Some`]'s value.
+     ///
+     /// [`Some(v)`]: Some
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(option_unwrap_none)]
+     ///
+     /// use std::collections::HashMap;
+     /// let mut squares = HashMap::new();
+     /// for i in -10..=10 {
+     ///     // This will not panic, since all keys are unique.
+     ///     squares.insert(i, i * i).unwrap_none();
+     /// }
+     /// ```
+     ///
+     /// ```{.should_panic}
+     /// #![feature(option_unwrap_none)]
+     ///
+     /// use std::collections::HashMap;
+     /// let mut sqrts = HashMap::new();
+     /// for i in -10..=10 {
+     ///     // This will panic, since both negative and positive `i` will
+     ///     // insert the same `i * i` key, returning the old `Some(i)`.
+     ///     sqrts.insert(i * i, i).unwrap_none();
+     /// }
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[unstable(feature = "option_unwrap_none", reason = "newly added", issue = "62633")]
+     pub fn unwrap_none(self) {
+         if let Some(val) = self {
+             expect_none_failed("called `Option::unwrap_none()` on a `Some` value", &val);
+         }
+     }
+ }
+ 
+ impl<T: Default> Option<T> {
+     /// Returns the contained [`Some`] value or a default
+     ///
+     /// Consumes the `self` argument then, if [`Some`], returns the contained
+     /// value, otherwise if [`None`], returns the [default value] for that
+     /// type.
+     ///
+     /// # Examples
+     ///
+     /// Converts a string to an integer, turning poorly-formed strings
+     /// into 0 (the default value for integers). [`parse`] converts
+     /// a string to any other type that implements [`FromStr`], returning
+     /// [`None`] on error.
+     ///
+     /// ```
+     /// let good_year_from_input = "1909";
+     /// let bad_year_from_input = "190blarg";
+     /// let good_year = good_year_from_input.parse().ok().unwrap_or_default();
+     /// let bad_year = bad_year_from_input.parse().ok().unwrap_or_default();
+     ///
+     /// assert_eq!(1909, good_year);
+     /// assert_eq!(0, bad_year);
+     /// ```
+     ///
+     /// [default value]: Default::default
+     /// [`parse`]: str::parse
+     /// [`FromStr`]: crate::str::FromStr
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap_or_default(self) -> T {
+         match self {
+             Some(x) => x,
+             None => Default::default(),
+         }
+     }
+ }
+ 
+ impl<T: Deref> Option<T> {
+     /// Converts from `Option<T>` (or `&Option<T>`) to `Option<&T::Target>`.
+     ///
+     /// Leaves the original Option in-place, creating a new one with a reference
+     /// to the original one, additionally coercing the contents via [`Deref`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x: Option<String> = Some("hey".to_owned());
+     /// assert_eq!(x.as_deref(), Some("hey"));
+     ///
+     /// let x: Option<String> = None;
+     /// assert_eq!(x.as_deref(), None);
+     /// ```
+     #[stable(feature = "option_deref", since = "1.40.0")]
+     pub fn as_deref(&self) -> Option<&T::Target> {
+         self.as_ref().map(|t| t.deref())
+     }
+ }
+ 
+ impl<T: DerefMut> Option<T> {
+     /// Converts from `Option<T>` (or `&mut Option<T>`) to `Option<&mut T::Target>`.
+     ///
+     /// Leaves the original `Option` in-place, creating a new one containing a mutable reference to
+     /// the inner type's `Deref::Target` type.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut x: Option<String> = Some("hey".to_owned());
+     /// assert_eq!(x.as_deref_mut().map(|x| {
+     ///     x.make_ascii_uppercase();
+     ///     x
+     /// }), Some("HEY".to_owned().as_mut_str()));
+     /// ```
+     #[stable(feature = "option_deref", since = "1.40.0")]
+     pub fn as_deref_mut(&mut self) -> Option<&mut T::Target> {
+         self.as_mut().map(|t| t.deref_mut())
+     }
+ }
+ 
+ impl<T, E> Option<Result<T, E>> {
+     /// Transposes an `Option` of a [`Result`] into a [`Result`] of an `Option`.
+     ///
+     /// [`None`] will be mapped to [`Ok`]`(`[`None`]`)`.
+     /// [`Some`]`(`[`Ok`]`(_))` and [`Some`]`(`[`Err`]`(_))` will be mapped to
+     /// [`Ok`]`(`[`Some`]`(_))` and [`Err`]`(_)`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[derive(Debug, Eq, PartialEq)]
+     /// struct SomeErr;
+     ///
+     /// let x: Result<Option<i32>, SomeErr> = Ok(Some(5));
+     /// let y: Option<Result<i32, SomeErr>> = Some(Ok(5));
+     /// assert_eq!(x, y.transpose());
+     /// ```
+     #[inline]
+     #[stable(feature = "transpose_result", since = "1.33.0")]
+     pub fn transpose(self) -> Result<Option<T>, E> {
+         match self {
+             Some(Ok(x)) => Ok(Some(x)),
+             Some(Err(e)) => Err(e),
+             None => Ok(None),
+         }
+     }
+ }
+ 
+ // This is a separate function to reduce the code size of .expect() itself.
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ fn expect_failed(msg: &str) -> ! {
+     panic!("{}", msg)
+ }
+ 
+ // This is a separate function to reduce the code size of .expect_none() itself.
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ fn expect_none_failed(msg: &str, value: &dyn fmt::Debug) -> ! {
+     panic!("{}: {:?}", msg, value)
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Trait implementations
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Clone> Clone for Option<T> {
+     #[inline]
+     fn clone(&self) -> Self {
+         match self {
+             Some(x) => Some(x.clone()),
+             None => None,
+         }
+     }
+ 
+     #[inline]
+     fn clone_from(&mut self, source: &Self) {
+         match (self, source) {
+             (Some(to), Some(from)) => to.clone_from(from),
+             (to, from) => *to = from.clone(),
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Default for Option<T> {
+     /// Returns [`None`][Option::None].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let opt: Option<u32> = Option::default();
+     /// assert!(opt.is_none());
+     /// ```
+     #[inline]
+     fn default() -> Option<T> {
+         None
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> IntoIterator for Option<T> {
+     type Item = T;
+     type IntoIter = IntoIter<T>;
+ 
+     /// Returns a consuming iterator over the possibly contained value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = Some("string");
+     /// let v: Vec<&str> = x.into_iter().collect();
+     /// assert_eq!(v, ["string"]);
+     ///
+     /// let x = None;
+     /// let v: Vec<&str> = x.into_iter().collect();
+     /// assert!(v.is_empty());
+     /// ```
+     #[inline]
+     fn into_iter(self) -> IntoIter<T> {
+         IntoIter { inner: Item { opt: self } }
+     }
+ }
+ 
+ #[stable(since = "1.4.0", feature = "option_iter")]
+ impl<'a, T> IntoIterator for &'a Option<T> {
+     type Item = &'a T;
+     type IntoIter = Iter<'a, T>;
+ 
+     fn into_iter(self) -> Iter<'a, T> {
+         self.iter()
+     }
+ }
+ 
+ #[stable(since = "1.4.0", feature = "option_iter")]
+ impl<'a, T> IntoIterator for &'a mut Option<T> {
+     type Item = &'a mut T;
+     type IntoIter = IterMut<'a, T>;
+ 
+     fn into_iter(self) -> IterMut<'a, T> {
+         self.iter_mut()
+     }
+ }
+ 
+ #[stable(since = "1.12.0", feature = "option_from")]
+ impl<T> From<T> for Option<T> {
+     /// Copies `val` into a new `Some`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let o: Option<u8> = Option::from(67);
+     ///
+     /// assert_eq!(Some(67), o);
+     /// ```
+     fn from(val: T) -> Option<T> {
+         Some(val)
+     }
+ }
+ 
+ #[stable(feature = "option_ref_from_ref_option", since = "1.30.0")]
+ impl<'a, T> From<&'a Option<T>> for Option<&'a T> {
+     /// Converts from `&Option<T>` to `Option<&T>`.
+     ///
+     /// # Examples
+     ///
+     /// Converts an `Option<`[`String`]`>` into an `Option<`[`usize`]`>`, preserving the original.
+     /// The [`map`] method takes the `self` argument by value, consuming the original,
+     /// so this technique uses `as_ref` to first take an `Option` to a reference
+     /// to the value inside the original.
+     ///
+     /// [`map`]: Option::map
+     /// [`String`]: ../../std/string/struct.String.html
+     ///
+     /// ```
+     /// let s: Option<String> = Some(String::from("Hello, Rustaceans!"));
+     /// let o: Option<usize> = Option::from(&s).map(|ss: &String| ss.len());
+     ///
+     /// println!("Can still print s: {:?}", s);
+     ///
+     /// assert_eq!(o, Some(18));
+     /// ```
+     fn from(o: &'a Option<T>) -> Option<&'a T> {
+         o.as_ref()
+     }
+ }
+ 
+ #[stable(feature = "option_ref_from_ref_option", since = "1.30.0")]
+ impl<'a, T> From<&'a mut Option<T>> for Option<&'a mut T> {
+     /// Converts from `&mut Option<T>` to `Option<&mut T>`
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut s = Some(String::from("Hello"));
+     /// let o: Option<&mut String> = Option::from(&mut s);
+     ///
+     /// match o {
+     ///     Some(t) => *t = String::from("Hello, Rustaceans!"),
+     ///     None => (),
+     /// }
+     ///
+     /// assert_eq!(s, Some(String::from("Hello, Rustaceans!")));
+     /// ```
+     fn from(o: &'a mut Option<T>) -> Option<&'a mut T> {
+         o.as_mut()
+     }
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // The Option Iterators
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[derive(Clone, Debug)]
+ struct Item<A> {
+     opt: Option<A>,
+ }
+ 
+ impl<A> Iterator for Item<A> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         self.opt.take()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         match self.opt {
+             Some(_) => (1, Some(1)),
+             None => (0, Some(0)),
+         }
+     }
+ }
+ 
+ impl<A> DoubleEndedIterator for Item<A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<A> {
+         self.opt.take()
+     }
+ }
+ 
+ impl<A> ExactSizeIterator for Item<A> {}
+ impl<A> FusedIterator for Item<A> {}
+ unsafe impl<A> TrustedLen for Item<A> {}
+ 
+ /// An iterator over a reference to the [`Some`] variant of an [`Option`].
+ ///
+ /// The iterator yields one value if the [`Option`] is a [`Some`], otherwise none.
+ ///
+ /// This `struct` is created by the [`Option::iter`] function.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Debug)]
+ pub struct Iter<'a, A: 'a> {
+     inner: Item<&'a A>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, A> Iterator for Iter<'a, A> {
+     type Item = &'a A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a A> {
+         self.inner.next()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, A> DoubleEndedIterator for Iter<'a, A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a A> {
+         self.inner.next_back()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A> ExactSizeIterator for Iter<'_, A> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A> FusedIterator for Iter<'_, A> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A> TrustedLen for Iter<'_, A> {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A> Clone for Iter<'_, A> {
+     #[inline]
+     fn clone(&self) -> Self {
+         Iter { inner: self.inner.clone() }
+     }
+ }
+ 
+ /// An iterator over a mutable reference to the [`Some`] variant of an [`Option`].
+ ///
+ /// The iterator yields one value if the [`Option`] is a [`Some`], otherwise none.
+ ///
+ /// This `struct` is created by the [`Option::iter_mut`] function.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Debug)]
+ pub struct IterMut<'a, A: 'a> {
+     inner: Item<&'a mut A>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, A> Iterator for IterMut<'a, A> {
+     type Item = &'a mut A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut A> {
+         self.inner.next()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, A> DoubleEndedIterator for IterMut<'a, A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut A> {
+         self.inner.next_back()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A> ExactSizeIterator for IterMut<'_, A> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A> FusedIterator for IterMut<'_, A> {}
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A> TrustedLen for IterMut<'_, A> {}
+ 
+ /// An iterator over the value in [`Some`] variant of an [`Option`].
+ ///
+ /// The iterator yields one value if the [`Option`] is a [`Some`], otherwise none.
+ ///
+ /// This `struct` is created by the [`Option::into_iter`] function.
+ #[derive(Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct IntoIter<A> {
+     inner: Item<A>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A> Iterator for IntoIter<A> {
+     type Item = A;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<A> {
+         self.inner.next()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A> DoubleEndedIterator for IntoIter<A> {
+     #[inline]
+     fn next_back(&mut self) -> Option<A> {
+         self.inner.next_back()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A> ExactSizeIterator for IntoIter<A> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<A> FusedIterator for IntoIter<A> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A> TrustedLen for IntoIter<A> {}
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // FromIterator
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, V: FromIterator<A>> FromIterator<Option<A>> for Option<V> {
+     /// Takes each element in the [`Iterator`]: if it is [`None`][Option::None],
+     /// no further elements are taken, and the [`None`][Option::None] is
+     /// returned. Should no [`None`][Option::None] occur, a container with the
+     /// values of each [`Option`] is returned.
+     ///
+     /// # Examples
+     ///
+     /// Here is an example which increments every integer in a vector.
+     /// We use the checked variant of `add` that returns `None` when the
+     /// calculation would result in an overflow.
+     ///
+     /// ```
+     /// let items = vec![0_u16, 1, 2];
+     ///
+     /// let res: Option<Vec<u16>> = items
+     ///     .iter()
+     ///     .map(|x| x.checked_add(1))
+     ///     .collect();
+     ///
+     /// assert_eq!(res, Some(vec![1, 2, 3]));
+     /// ```
+     ///
+     /// As you can see, this will return the expected, valid items.
+     ///
+     /// Here is another example that tries to subtract one from another list
+     /// of integers, this time checking for underflow:
+     ///
+     /// ```
+     /// let items = vec![2_u16, 1, 0];
+     ///
+     /// let res: Option<Vec<u16>> = items
+     ///     .iter()
+     ///     .map(|x| x.checked_sub(1))
+     ///     .collect();
+     ///
+     /// assert_eq!(res, None);
+     /// ```
+     ///
+     /// Since the last element is zero, it would underflow. Thus, the resulting
+     /// value is `None`.
+     ///
+     /// Here is a variation on the previous example, showing that no
+     /// further elements are taken from `iter` after the first `None`.
+     ///
+     /// ```
+     /// let items = vec![3_u16, 2, 1, 10];
+     ///
+     /// let mut shared = 0;
+     ///
+     /// let res: Option<Vec<u16>> = items
+     ///     .iter()
+     ///     .map(|x| { shared += x; x.checked_sub(2) })
+     ///     .collect();
+     ///
+     /// assert_eq!(res, None);
+     /// assert_eq!(shared, 6);
+     /// ```
+     ///
+     /// Since the third element caused an underflow, no further elements were taken,
+     /// so the final value of `shared` is 6 (= `3 + 2 + 1`), not 16.
+     #[inline]
+     fn from_iter<I: IntoIterator<Item = Option<A>>>(iter: I) -> Option<V> {
+         // FIXME(#11084): This could be replaced with Iterator::scan when this
+         // performance bug is closed.
+ 
+         iter.into_iter().map(|x| x.ok_or(())).collect::<Result<_, _>>().ok()
+     }
+ }
+ 
+ /// The error type that results from applying the try operator (`?`) to a `None` value. If you wish
+ /// to allow `x?` (where `x` is an `Option<T>`) to be converted into your error type, you can
+ /// implement `impl From<NoneError>` for `YourErrorType`. In that case, `x?` within a function that
+ /// returns `Result<_, YourErrorType>` will translate a `None` value into an `Err` result.
+ #[rustc_diagnostic_item = "none_error"]
+ #[unstable(feature = "try_trait", issue = "42327")]
+ #[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord, Debug, Hash)]
+ pub struct NoneError;
+ 
+ #[unstable(feature = "try_trait", issue = "42327")]
+ impl<T> ops::Try for Option<T> {
+     type Ok = T;
+     type Error = NoneError;
+ 
+     #[inline]
+     fn into_result(self) -> Result<T, NoneError> {
+         self.ok_or(NoneError)
+     }
+ 
+     #[inline]
+     fn from_ok(v: T) -> Self {
+         Some(v)
+     }
+ 
+     #[inline]
+     fn from_error(_: NoneError) -> Self {
+         None
+     }
+ }
+ 
+ impl<T> Option<Option<T>> {
+     /// Converts from `Option<Option<T>>` to `Option<T>`
+     ///
+     /// # Examples
+     /// Basic usage:
+     /// ```
+     /// let x: Option<Option<u32>> = Some(Some(6));
+     /// assert_eq!(Some(6), x.flatten());
+     ///
+     /// let x: Option<Option<u32>> = Some(None);
+     /// assert_eq!(None, x.flatten());
+     ///
+     /// let x: Option<Option<u32>> = None;
+     /// assert_eq!(None, x.flatten());
+     /// ```
+     /// Flattening once only removes one level of nesting:
+     /// ```
+     /// let x: Option<Option<Option<u32>>> = Some(Some(Some(6)));
+     /// assert_eq!(Some(Some(6)), x.flatten());
+     /// assert_eq!(Some(6), x.flatten().flatten());
+     /// ```
+     #[inline]
+     #[stable(feature = "option_flattening", since = "1.40.0")]
+     pub fn flatten(self) -> Option<T> {
+         self.and_then(convert::identity)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/panic.rs gcc-16-20251102/libgrust/rustc-lib/core/src/panic.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/panic.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/panic.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,354 ----
+ //! Panic support in the standard library.
+ 
+ #![stable(feature = "core_panic_info", since = "1.41.0")]
+ 
+ use crate::any::Any;
+ use crate::fmt;
+ 
+ /// A struct providing information about a panic.
+ ///
+ /// `PanicInfo` structure is passed to a panic hook set by the [`set_hook`]
+ /// function.
+ ///
+ /// [`set_hook`]: ../../std/panic/fn.set_hook.html
+ ///
+ /// # Examples
+ ///
+ /// ```should_panic
+ /// use std::panic;
+ ///
+ /// panic::set_hook(Box::new(|panic_info| {
+ ///     if let Some(s) = panic_info.payload().downcast_ref::<&str>() {
+ ///         println!("panic occurred: {:?}", s);
+ ///     } else {
+ ///         println!("panic occurred");
+ ///     }
+ /// }));
+ ///
+ /// panic!("Normal panic");
+ /// ```
+ #[lang = "panic_info"]
+ #[stable(feature = "panic_hooks", since = "1.10.0")]
+ #[derive(Debug)]
+ pub struct PanicInfo<'a> {
+     payload: &'a (dyn Any + Send),
+     message: Option<&'a fmt::Arguments<'a>>,
+     location: &'a Location<'a>,
+ }
+ 
+ impl<'a> PanicInfo<'a> {
+     #[unstable(
+         feature = "panic_internals",
+         reason = "internal details of the implementation of the `panic!` and related macros",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     #[inline]
+     pub fn internal_constructor(
+         message: Option<&'a fmt::Arguments<'a>>,
+         location: &'a Location<'a>,
+     ) -> Self {
+         struct NoPayload;
+         PanicInfo { location, message, payload: &NoPayload }
+     }
+ 
+     #[unstable(
+         feature = "panic_internals",
+         reason = "internal details of the implementation of the `panic!` and related macros",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     #[inline]
+     pub fn set_payload(&mut self, info: &'a (dyn Any + Send)) {
+         self.payload = info;
+     }
+ 
+     /// Returns the payload associated with the panic.
+     ///
+     /// This will commonly, but not always, be a `&'static str` or [`String`].
+     ///
+     /// [`String`]: ../../std/string/struct.String.html
+     ///
+     /// # Examples
+     ///
+     /// ```should_panic
+     /// use std::panic;
+     ///
+     /// panic::set_hook(Box::new(|panic_info| {
+     ///     if let Some(s) = panic_info.payload().downcast_ref::<&str>() {
+     ///         println!("panic occurred: {:?}", s);
+     ///     } else {
+     ///         println!("panic occurred");
+     ///     }
+     /// }));
+     ///
+     /// panic!("Normal panic");
+     /// ```
+     #[stable(feature = "panic_hooks", since = "1.10.0")]
+     pub fn payload(&self) -> &(dyn Any + Send) {
+         self.payload
+     }
+ 
+     /// If the `panic!` macro from the `core` crate (not from `std`)
+     /// was used with a formatting string and some additional arguments,
+     /// returns that message ready to be used for example with [`fmt::write`]
+     #[unstable(feature = "panic_info_message", issue = "66745")]
+     pub fn message(&self) -> Option<&fmt::Arguments<'_>> {
+         self.message
+     }
+ 
+     /// Returns information about the location from which the panic originated,
+     /// if available.
+     ///
+     /// This method will currently always return [`Some`], but this may change
+     /// in future versions.
+     ///
+     /// # Examples
+     ///
+     /// ```should_panic
+     /// use std::panic;
+     ///
+     /// panic::set_hook(Box::new(|panic_info| {
+     ///     if let Some(location) = panic_info.location() {
+     ///         println!("panic occurred in file '{}' at line {}",
+     ///             location.file(),
+     ///             location.line(),
+     ///         );
+     ///     } else {
+     ///         println!("panic occurred but can't get location information...");
+     ///     }
+     /// }));
+     ///
+     /// panic!("Normal panic");
+     /// ```
+     #[stable(feature = "panic_hooks", since = "1.10.0")]
+     pub fn location(&self) -> Option<&Location<'_>> {
+         // NOTE: If this is changed to sometimes return None,
+         // deal with that case in std::panicking::default_hook and std::panicking::begin_panic_fmt.
+         Some(&self.location)
+     }
+ }
+ 
+ #[stable(feature = "panic_hook_display", since = "1.26.0")]
+ impl fmt::Display for PanicInfo<'_> {
+     fn fmt(&self, formatter: &mut fmt::Formatter<'_>) -> fmt::Result {
+         formatter.write_str("panicked at ")?;
+         if let Some(message) = self.message {
+             write!(formatter, "'{}', ", message)?
+         } else if let Some(payload) = self.payload.downcast_ref::<&'static str>() {
+             write!(formatter, "'{}', ", payload)?
+         }
+         // NOTE: we cannot use downcast_ref::<String>() here
+         // since String is not available in libcore!
+         // The payload is a String when `std::panic!` is called with multiple arguments,
+         // but in that case the message is also available.
+ 
+         self.location.fmt(formatter)
+     }
+ }
+ 
+ /// A struct containing information about the location of a panic.
+ ///
+ /// This structure is created by [`PanicInfo::location()`].
+ ///
+ /// # Examples
+ ///
+ /// ```should_panic
+ /// use std::panic;
+ ///
+ /// panic::set_hook(Box::new(|panic_info| {
+ ///     if let Some(location) = panic_info.location() {
+ ///         println!("panic occurred in file '{}' at line {}", location.file(), location.line());
+ ///     } else {
+ ///         println!("panic occurred but can't get location information...");
+ ///     }
+ /// }));
+ ///
+ /// panic!("Normal panic");
+ /// ```
+ ///
+ /// # Comparisons
+ ///
+ /// Comparisons for equality and ordering are made in file, line, then column priority.
+ /// Files are compared as strings, not `Path`, which could be unexpected.
+ /// See [`Location::file`]'s documentation for more discussion.
+ #[lang = "panic_location"]
+ #[derive(Copy, Clone, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
+ #[stable(feature = "panic_hooks", since = "1.10.0")]
+ pub struct Location<'a> {
+     file: &'a str,
+     line: u32,
+     col: u32,
+ }
+ 
+ impl<'a> Location<'a> {
+     /// Returns the source location of the caller of this function. If that function's caller is
+     /// annotated then its call location will be returned, and so on up the stack to the first call
+     /// within a non-tracked function body.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use core::panic::Location;
+     ///
+     /// /// Returns the [`Location`] at which it is called.
+     /// #[track_caller]
+     /// fn get_caller_location() -> &'static Location<'static> {
+     ///     Location::caller()
+     /// }
+     ///
+     /// /// Returns a [`Location`] from within this function's definition.
+     /// fn get_just_one_location() -> &'static Location<'static> {
+     ///     get_caller_location()
+     /// }
+     ///
+     /// let fixed_location = get_just_one_location();
+     /// assert_eq!(fixed_location.file(), file!());
+     /// assert_eq!(fixed_location.line(), 14);
+     /// assert_eq!(fixed_location.column(), 5);
+     ///
+     /// // running the same untracked function in a different location gives us the same result
+     /// let second_fixed_location = get_just_one_location();
+     /// assert_eq!(fixed_location.file(), second_fixed_location.file());
+     /// assert_eq!(fixed_location.line(), second_fixed_location.line());
+     /// assert_eq!(fixed_location.column(), second_fixed_location.column());
+     ///
+     /// let this_location = get_caller_location();
+     /// assert_eq!(this_location.file(), file!());
+     /// assert_eq!(this_location.line(), 28);
+     /// assert_eq!(this_location.column(), 21);
+     ///
+     /// // running the tracked function in a different location produces a different value
+     /// let another_location = get_caller_location();
+     /// assert_eq!(this_location.file(), another_location.file());
+     /// assert_ne!(this_location.line(), another_location.line());
+     /// assert_ne!(this_location.column(), another_location.column());
+     /// ```
+     #[stable(feature = "track_caller", since = "1.46.0")]
+     #[rustc_const_unstable(feature = "const_caller_location", issue = "76156")]
+     #[track_caller]
+     pub const fn caller() -> &'static Location<'static> {
+         crate::intrinsics::caller_location()
+     }
+ }
+ 
+ impl<'a> Location<'a> {
+     #![unstable(
+         feature = "panic_internals",
+         reason = "internal details of the implementation of the `panic!` and related macros",
+         issue = "none"
+     )]
+     #[doc(hidden)]
+     pub const fn internal_constructor(file: &'a str, line: u32, col: u32) -> Self {
+         Location { file, line, col }
+     }
+ 
+     /// Returns the name of the source file from which the panic originated.
+     ///
+     /// # `&str`, not `&Path`
+     ///
+     /// The returned name refers to a source path on the compiling system, but it isn't valid to
+     /// represent this directly as a `&Path`. The compiled code may run on a different system with
+     /// a different `Path` implementation than the system providing the contents and this library
+     /// does not currently have a different "host path" type.
+     ///
+     /// The most surprising behavior occurs when "the same" file is reachable via multiple paths in
+     /// the module system (usually using the `#[path = "..."]` attribute or similar), which can
+     /// cause what appears to be identical code to return differing values from this function.
+     ///
+     /// # Cross-compilation
+     ///
+     /// This value is not suitable for passing to `Path::new` or similar constructors when the host
+     /// platform and target platform differ.
+     ///
+     /// # Examples
+     ///
+     /// ```should_panic
+     /// use std::panic;
+     ///
+     /// panic::set_hook(Box::new(|panic_info| {
+     ///     if let Some(location) = panic_info.location() {
+     ///         println!("panic occurred in file '{}'", location.file());
+     ///     } else {
+     ///         println!("panic occurred but can't get location information...");
+     ///     }
+     /// }));
+     ///
+     /// panic!("Normal panic");
+     /// ```
+     #[stable(feature = "panic_hooks", since = "1.10.0")]
+     pub fn file(&self) -> &str {
+         self.file
+     }
+ 
+     /// Returns the line number from which the panic originated.
+     ///
+     /// # Examples
+     ///
+     /// ```should_panic
+     /// use std::panic;
+     ///
+     /// panic::set_hook(Box::new(|panic_info| {
+     ///     if let Some(location) = panic_info.location() {
+     ///         println!("panic occurred at line {}", location.line());
+     ///     } else {
+     ///         println!("panic occurred but can't get location information...");
+     ///     }
+     /// }));
+     ///
+     /// panic!("Normal panic");
+     /// ```
+     #[stable(feature = "panic_hooks", since = "1.10.0")]
+     pub fn line(&self) -> u32 {
+         self.line
+     }
+ 
+     /// Returns the column from which the panic originated.
+     ///
+     /// # Examples
+     ///
+     /// ```should_panic
+     /// use std::panic;
+     ///
+     /// panic::set_hook(Box::new(|panic_info| {
+     ///     if let Some(location) = panic_info.location() {
+     ///         println!("panic occurred at column {}", location.column());
+     ///     } else {
+     ///         println!("panic occurred but can't get location information...");
+     ///     }
+     /// }));
+     ///
+     /// panic!("Normal panic");
+     /// ```
+     #[stable(feature = "panic_col", since = "1.25.0")]
+     pub fn column(&self) -> u32 {
+         self.col
+     }
+ }
+ 
+ #[stable(feature = "panic_hook_display", since = "1.26.0")]
+ impl fmt::Display for Location<'_> {
+     fn fmt(&self, formatter: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(formatter, "{}:{}:{}", self.file, self.line, self.col)
+     }
+ }
+ 
+ /// An internal trait used by libstd to pass data from libstd to `panic_unwind`
+ /// and other panic runtimes. Not intended to be stabilized any time soon, do
+ /// not use.
+ #[unstable(feature = "std_internals", issue = "none")]
+ #[doc(hidden)]
+ pub unsafe trait BoxMeUp {
+     /// Take full ownership of the contents.
+     /// The return type is actually `Box<dyn Any + Send>`, but we cannot use `Box` in libcore.
+     ///
+     /// After this method got called, only some dummy default value is left in `self`.
+     /// Calling this method twice, or calling `get` after calling this method, is an error.
+     ///
+     /// The argument is borrowed because the panic runtime (`__rust_start_panic`) only
+     /// gets a borrowed `dyn BoxMeUp`.
+     fn take_box(&mut self) -> *mut (dyn Any + Send);
+ 
+     /// Just borrow the contents.
+     fn get(&mut self) -> &(dyn Any + Send);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/panicking.rs gcc-16-20251102/libgrust/rustc-lib/core/src/panicking.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/panicking.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/panicking.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,93 ----
+ //! Panic support for libcore
+ //!
+ //! The core library cannot define panicking, but it does *declare* panicking. This
+ //! means that the functions inside of libcore are allowed to panic, but to be
+ //! useful an upstream crate must define panicking for libcore to use. The current
+ //! interface for panicking is:
+ //!
+ //! ```
+ //! fn panic_impl(pi: &core::panic::PanicInfo<'_>) -> !
+ //! # { loop {} }
+ //! ```
+ //!
+ //! This definition allows for panicking with any general message, but it does not
+ //! allow for failing with a `Box<Any>` value. (`PanicInfo` just contains a `&(dyn Any + Send)`,
+ //! for which we fill in a dummy value in `PanicInfo::internal_constructor`.)
+ //! The reason for this is that libcore is not allowed to allocate.
+ //!
+ //! This module contains a few other panicking functions, but these are just the
+ //! necessary lang items for the compiler. All panics are funneled through this
+ //! one function. The actual symbol is declared through the `#[panic_handler]` attribute.
+ 
+ #![allow(dead_code, missing_docs)]
+ #![unstable(
+     feature = "core_panic",
+     reason = "internal details of the implementation of the `panic!` and related macros",
+     issue = "none"
+ )]
+ 
+ use crate::fmt;
+ use crate::panic::{Location, PanicInfo};
+ 
+ /// The underlying implementation of libcore's `panic!` macro when no formatting is used.
+ #[cold]
+ // never inline unless panic_immediate_abort to avoid code
+ // bloat at the call sites as much as possible
+ #[cfg_attr(not(feature = "panic_immediate_abort"), inline(never))]
+ #[track_caller]
+ #[lang = "panic"] // needed by codegen for panic on overflow and other `Assert` MIR terminators
+ pub fn panic(expr: &'static str) -> ! {
+     if cfg!(feature = "panic_immediate_abort") {
+         super::intrinsics::abort()
+     }
+ 
+     // Use Arguments::new_v1 instead of format_args!("{}", expr) to potentially
+     // reduce size overhead. The format_args! macro uses str's Display trait to
+     // write expr, which calls Formatter::pad, which must accommodate string
+     // truncation and padding (even though none is used here). Using
+     // Arguments::new_v1 may allow the compiler to omit Formatter::pad from the
+     // output binary, saving up to a few kilobytes.
+     panic_fmt(fmt::Arguments::new_v1(&[expr], &[]));
+ }
+ 
+ #[inline]
+ #[track_caller]
+ #[cfg_attr(not(bootstrap), lang = "panic_str")] // needed for const-evaluated panics
+ pub fn panic_str(expr: &str) -> ! {
+     panic_fmt(format_args!("{}", expr));
+ }
+ 
+ #[cold]
+ #[cfg_attr(not(feature = "panic_immediate_abort"), inline(never))]
+ #[track_caller]
+ #[lang = "panic_bounds_check"] // needed by codegen for panic on OOB array/slice access
+ fn panic_bounds_check(index: usize, len: usize) -> ! {
+     if cfg!(feature = "panic_immediate_abort") {
+         super::intrinsics::abort()
+     }
+ 
+     panic!("index out of bounds: the len is {} but the index is {}", len, index)
+ }
+ 
+ /// The underlying implementation of libcore's `panic!` macro when formatting is used.
+ #[cold]
+ #[cfg_attr(not(feature = "panic_immediate_abort"), inline(never))]
+ #[cfg_attr(feature = "panic_immediate_abort", inline)]
+ #[track_caller]
+ pub fn panic_fmt(fmt: fmt::Arguments<'_>) -> ! {
+     if cfg!(feature = "panic_immediate_abort") {
+         super::intrinsics::abort()
+     }
+ 
+     // NOTE This function never crosses the FFI boundary; it's a Rust-to-Rust call
+     // that gets resolved to the `#[panic_handler]` function.
+     extern "Rust" {
+         #[lang = "panic_impl"]
+         fn panic_impl(pi: &PanicInfo<'_>) -> !;
+     }
+ 
+     let pi = PanicInfo::internal_constructor(Some(&fmt), Location::caller());
+ 
+     // SAFETY: `panic_impl` is defined in safe Rust code and thus is safe to call.
+     unsafe { panic_impl(&pi) }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/pin.rs gcc-16-20251102/libgrust/rustc-lib/core/src/pin.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/pin.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/pin.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,860 ----
+ //! Types that pin data to its location in memory.
+ //!
+ //! It is sometimes useful to have objects that are guaranteed not to move,
+ //! in the sense that their placement in memory does not change, and can thus be relied upon.
+ //! A prime example of such a scenario would be building self-referential structs,
+ //! as moving an object with pointers to itself will invalidate them, which could cause undefined
+ //! behavior.
+ //!
+ //! At a high level, a [`Pin<P>`] ensures that the pointee of any pointer type
+ //! `P` has a stable location in memory, meaning it cannot be moved elsewhere
+ //! and its memory cannot be deallocated until it gets dropped. We say that the
+ //! pointee is "pinned". Things get more subtle when discussing types that
+ //! combine pinned with non-pinned data; [see below](#projections-and-structural-pinning)
+ //! for more details.
+ //!
+ //! By default, all types in Rust are movable. Rust allows passing all types by-value,
+ //! and common smart-pointer types such as [`Box<T>`] and `&mut T` allow replacing and
+ //! moving the values they contain: you can move out of a [`Box<T>`], or you can use [`mem::swap`].
+ //! [`Pin<P>`] wraps a pointer type `P`, so [`Pin`]`<`[`Box`]`<T>>` functions much like a regular
+ //! [`Box<T>`]: when a [`Pin`]`<`[`Box`]`<T>>` gets dropped, so do its contents, and the memory gets
+ //! deallocated. Similarly, [`Pin`]`<&mut T>` is a lot like `&mut T`. However, [`Pin<P>`] does
+ //! not let clients actually obtain a [`Box<T>`] or `&mut T` to pinned data, which implies that you
+ //! cannot use operations such as [`mem::swap`]:
+ //!
+ //! ```
+ //! use std::pin::Pin;
+ //! fn swap_pins<T>(x: Pin<&mut T>, y: Pin<&mut T>) {
+ //!     // `mem::swap` needs `&mut T`, but we cannot get it.
+ //!     // We are stuck, we cannot swap the contents of these references.
+ //!     // We could use `Pin::get_unchecked_mut`, but that is unsafe for a reason:
+ //!     // we are not allowed to use it for moving things out of the `Pin`.
+ //! }
+ //! ```
+ //!
+ //! It is worth reiterating that [`Pin<P>`] does *not* change the fact that a Rust compiler
+ //! considers all types movable. [`mem::swap`] remains callable for any `T`. Instead, [`Pin<P>`]
+ //! prevents certain *values* (pointed to by pointers wrapped in [`Pin<P>`]) from being
+ //! moved by making it impossible to call methods that require `&mut T` on them
+ //! (like [`mem::swap`]).
+ //!
+ //! [`Pin<P>`] can be used to wrap any pointer type `P`, and as such it interacts with
+ //! [`Deref`] and [`DerefMut`]. A [`Pin<P>`] where `P: Deref` should be considered
+ //! as a "`P`-style pointer" to a pinned `P::Target` -- so, a [`Pin`]`<`[`Box`]`<T>>` is
+ //! an owned pointer to a pinned `T`, and a [`Pin`]`<`[`Rc`]`<T>>` is a reference-counted
+ //! pointer to a pinned `T`.
+ //! For correctness, [`Pin<P>`] relies on the implementations of [`Deref`] and
+ //! [`DerefMut`] not to move out of their `self` parameter, and only ever to
+ //! return a pointer to pinned data when they are called on a pinned pointer.
+ //!
+ //! # `Unpin`
+ //!
+ //! Many types are always freely movable, even when pinned, because they do not
+ //! rely on having a stable address. This includes all the basic types (like
+ //! [`bool`], [`i32`], and references) as well as types consisting solely of these
+ //! types. Types that do not care about pinning implement the [`Unpin`]
+ //! auto-trait, which cancels the effect of [`Pin<P>`]. For `T: Unpin`,
+ //! [`Pin`]`<`[`Box`]`<T>>` and [`Box<T>`] function identically, as do [`Pin`]`<&mut T>` and
+ //! `&mut T`.
+ //!
+ //! Note that pinning and [`Unpin`] only affect the pointed-to type `P::Target`, not the pointer
+ //! type `P` itself that got wrapped in [`Pin<P>`]. For example, whether or not [`Box<T>`] is
+ //! [`Unpin`] has no effect on the behavior of [`Pin`]`<`[`Box`]`<T>>` (here, `T` is the
+ //! pointed-to type).
+ //!
+ //! # Example: self-referential struct
+ //!
+ //! Before we go into more details to explain the guarantees and choices
+ //! associated with `Pin<T>`, we discuss some examples for how it might be used.
+ //! Feel free to [skip to where the theoretical discussion continues](#drop-guarantee).
+ //!
+ //! ```rust
+ //! use std::pin::Pin;
+ //! use std::marker::PhantomPinned;
+ //! use std::ptr::NonNull;
+ //!
+ //! // This is a self-referential struct because the slice field points to the data field.
+ //! // We cannot inform the compiler about that with a normal reference,
+ //! // as this pattern cannot be described with the usual borrowing rules.
+ //! // Instead we use a raw pointer, though one which is known not to be null,
+ //! // as we know it's pointing at the string.
+ //! struct Unmovable {
+ //!     data: String,
+ //!     slice: NonNull<String>,
+ //!     _pin: PhantomPinned,
+ //! }
+ //!
+ //! impl Unmovable {
+ //!     // To ensure the data doesn't move when the function returns,
+ //!     // we place it in the heap where it will stay for the lifetime of the object,
+ //!     // and the only way to access it would be through a pointer to it.
+ //!     fn new(data: String) -> Pin<Box<Self>> {
+ //!         let res = Unmovable {
+ //!             data,
+ //!             // we only create the pointer once the data is in place
+ //!             // otherwise it will have already moved before we even started
+ //!             slice: NonNull::dangling(),
+ //!             _pin: PhantomPinned,
+ //!         };
+ //!         let mut boxed = Box::pin(res);
+ //!
+ //!         let slice = NonNull::from(&boxed.data);
+ //!         // we know this is safe because modifying a field doesn't move the whole struct
+ //!         unsafe {
+ //!             let mut_ref: Pin<&mut Self> = Pin::as_mut(&mut boxed);
+ //!             Pin::get_unchecked_mut(mut_ref).slice = slice;
+ //!         }
+ //!         boxed
+ //!     }
+ //! }
+ //!
+ //! let unmoved = Unmovable::new("hello".to_string());
+ //! // The pointer should point to the correct location,
+ //! // so long as the struct hasn't moved.
+ //! // Meanwhile, we are free to move the pointer around.
+ //! # #[allow(unused_mut)]
+ //! let mut still_unmoved = unmoved;
+ //! assert_eq!(still_unmoved.slice, NonNull::from(&still_unmoved.data));
+ //!
+ //! // Since our type doesn't implement Unpin, this will fail to compile:
+ //! // let mut new_unmoved = Unmovable::new("world".to_string());
+ //! // std::mem::swap(&mut *still_unmoved, &mut *new_unmoved);
+ //! ```
+ //!
+ //! # Example: intrusive doubly-linked list
+ //!
+ //! In an intrusive doubly-linked list, the collection does not actually allocate
+ //! the memory for the elements itself. Allocation is controlled by the clients,
+ //! and elements can live on a stack frame that lives shorter than the collection does.
+ //!
+ //! To make this work, every element has pointers to its predecessor and successor in
+ //! the list. Elements can only be added when they are pinned, because moving the elements
+ //! around would invalidate the pointers. Moreover, the [`Drop`] implementation of a linked
+ //! list element will patch the pointers of its predecessor and successor to remove itself
+ //! from the list.
+ //!
+ //! Crucially, we have to be able to rely on [`drop`] being called. If an element
+ //! could be deallocated or otherwise invalidated without calling [`drop`], the pointers into it
+ //! from its neighboring elements would become invalid, which would break the data structure.
+ //!
+ //! Therefore, pinning also comes with a [`drop`]-related guarantee.
+ //!
+ //! # `Drop` guarantee
+ //!
+ //! The purpose of pinning is to be able to rely on the placement of some data in memory.
+ //! To make this work, not just moving the data is restricted; deallocating, repurposing, or
+ //! otherwise invalidating the memory used to store the data is restricted, too.
+ //! Concretely, for pinned data you have to maintain the invariant
+ //! that *its memory will not get invalidated or repurposed from the moment it gets pinned until
+ //! when [`drop`] is called*.  Only once [`drop`] returns or panics, the memory may be reused.
+ //!
+ //! Memory can be "invalidated" by deallocation, but also by
+ //! replacing a [`Some(v)`] by [`None`], or calling [`Vec::set_len`] to "kill" some elements
+ //! off of a vector. It can be repurposed by using [`ptr::write`] to overwrite it without
+ //! calling the destructor first. None of this is allowed for pinned data without calling [`drop`].
+ //!
+ //! This is exactly the kind of guarantee that the intrusive linked list from the previous
+ //! section needs to function correctly.
+ //!
+ //! Notice that this guarantee does *not* mean that memory does not leak! It is still
+ //! completely okay not ever to call [`drop`] on a pinned element (e.g., you can still
+ //! call [`mem::forget`] on a [`Pin`]`<`[`Box`]`<T>>`). In the example of the doubly-linked
+ //! list, that element would just stay in the list. However you may not free or reuse the storage
+ //! *without calling [`drop`]*.
+ //!
+ //! # `Drop` implementation
+ //!
+ //! If your type uses pinning (such as the two examples above), you have to be careful
+ //! when implementing [`Drop`]. The [`drop`] function takes `&mut self`, but this
+ //! is called *even if your type was previously pinned*! It is as if the
+ //! compiler automatically called [`Pin::get_unchecked_mut`].
+ //!
+ //! This can never cause a problem in safe code because implementing a type that
+ //! relies on pinning requires unsafe code, but be aware that deciding to make
+ //! use of pinning in your type (for example by implementing some operation on
+ //! [`Pin`]`<&Self>` or [`Pin`]`<&mut Self>`) has consequences for your [`Drop`]
+ //! implementation as well: if an element of your type could have been pinned,
+ //! you must treat [`Drop`] as implicitly taking [`Pin`]`<&mut Self>`.
+ //!
+ //! For example, you could implement `Drop` as follows:
+ //!
+ //! ```rust,no_run
+ //! # use std::pin::Pin;
+ //! # struct Type { }
+ //! impl Drop for Type {
+ //!     fn drop(&mut self) {
+ //!         // `new_unchecked` is okay because we know this value is never used
+ //!         // again after being dropped.
+ //!         inner_drop(unsafe { Pin::new_unchecked(self)});
+ //!         fn inner_drop(this: Pin<&mut Type>) {
+ //!             // Actual drop code goes here.
+ //!         }
+ //!     }
+ //! }
+ //! ```
+ //!
+ //! The function `inner_drop` has the type that [`drop`] *should* have, so this makes sure that
+ //! you do not accidentally use `self`/`this` in a way that is in conflict with pinning.
+ //!
+ //! Moreover, if your type is `#[repr(packed)]`, the compiler will automatically
+ //! move fields around to be able to drop them. It might even do
+ //! that for fields that happen to be sufficiently aligned. As a consequence, you cannot use
+ //! pinning with a `#[repr(packed)]` type.
+ //!
+ //! # Projections and Structural Pinning
+ //!
+ //! When working with pinned structs, the question arises how one can access the
+ //! fields of that struct in a method that takes just [`Pin`]`<&mut Struct>`.
+ //! The usual approach is to write helper methods (so called *projections*)
+ //! that turn [`Pin`]`<&mut Struct>` into a reference to the field, but what
+ //! type should that reference have? Is it [`Pin`]`<&mut Field>` or `&mut Field`?
+ //! The same question arises with the fields of an `enum`, and also when considering
+ //! container/wrapper types such as [`Vec<T>`], [`Box<T>`], or [`RefCell<T>`].
+ //! (This question applies to both mutable and shared references, we just
+ //! use the more common case of mutable references here for illustration.)
+ //!
+ //! It turns out that it is actually up to the author of the data structure
+ //! to decide whether the pinned projection for a particular field turns
+ //! [`Pin`]`<&mut Struct>` into [`Pin`]`<&mut Field>` or `&mut Field`. There are some
+ //! constraints though, and the most important constraint is *consistency*:
+ //! every field can be *either* projected to a pinned reference, *or* have
+ //! pinning removed as part of the projection. If both are done for the same field,
+ //! that will likely be unsound!
+ //!
+ //! As the author of a data structure you get to decide for each field whether pinning
+ //! "propagates" to this field or not. Pinning that propagates is also called "structural",
+ //! because it follows the structure of the type.
+ //! In the following subsections, we describe the considerations that have to be made
+ //! for either choice.
+ //!
+ //! ## Pinning *is not* structural for `field`
+ //!
+ //! It may seem counter-intuitive that the field of a pinned struct might not be pinned,
+ //! but that is actually the easiest choice: if a [`Pin`]`<&mut Field>` is never created,
+ //! nothing can go wrong! So, if you decide that some field does not have structural pinning,
+ //! all you have to ensure is that you never create a pinned reference to that field.
+ //!
+ //! Fields without structural pinning may have a projection method that turns
+ //! [`Pin`]`<&mut Struct>` into `&mut Field`:
+ //!
+ //! ```rust,no_run
+ //! # use std::pin::Pin;
+ //! # type Field = i32;
+ //! # struct Struct { field: Field }
+ //! impl Struct {
+ //!     fn pin_get_field(self: Pin<&mut Self>) -> &mut Field {
+ //!         // This is okay because `field` is never considered pinned.
+ //!         unsafe { &mut self.get_unchecked_mut().field }
+ //!     }
+ //! }
+ //! ```
+ //!
+ //! You may also `impl Unpin for Struct` *even if* the type of `field`
+ //! is not [`Unpin`]. What that type thinks about pinning is not relevant
+ //! when no [`Pin`]`<&mut Field>` is ever created.
+ //!
+ //! ## Pinning *is* structural for `field`
+ //!
+ //! The other option is to decide that pinning is "structural" for `field`,
+ //! meaning that if the struct is pinned then so is the field.
+ //!
+ //! This allows writing a projection that creates a [`Pin`]`<&mut Field>`, thus
+ //! witnessing that the field is pinned:
+ //!
+ //! ```rust,no_run
+ //! # use std::pin::Pin;
+ //! # type Field = i32;
+ //! # struct Struct { field: Field }
+ //! impl Struct {
+ //!     fn pin_get_field(self: Pin<&mut Self>) -> Pin<&mut Field> {
+ //!         // This is okay because `field` is pinned when `self` is.
+ //!         unsafe { self.map_unchecked_mut(|s| &mut s.field) }
+ //!     }
+ //! }
+ //! ```
+ //!
+ //! However, structural pinning comes with a few extra requirements:
+ //!
+ //! 1.  The struct must only be [`Unpin`] if all the structural fields are
+ //!     [`Unpin`]. This is the default, but [`Unpin`] is a safe trait, so as the author of
+ //!     the struct it is your responsibility *not* to add something like
+ //!     `impl<T> Unpin for Struct<T>`. (Notice that adding a projection operation
+ //!     requires unsafe code, so the fact that [`Unpin`] is a safe trait does not break
+ //!     the principle that you only have to worry about any of this if you use `unsafe`.)
+ //! 2.  The destructor of the struct must not move structural fields out of its argument. This
+ //!     is the exact point that was raised in the [previous section][drop-impl]: `drop` takes
+ //!     `&mut self`, but the struct (and hence its fields) might have been pinned before.
+ //!     You have to guarantee that you do not move a field inside your [`Drop`] implementation.
+ //!     In particular, as explained previously, this means that your struct must *not*
+ //!     be `#[repr(packed)]`.
+ //!     See that section for how to write [`drop`] in a way that the compiler can help you
+ //!     not accidentally break pinning.
+ //! 3.  You must make sure that you uphold the [`Drop` guarantee][drop-guarantee]:
+ //!     once your struct is pinned, the memory that contains the
+ //!     content is not overwritten or deallocated without calling the content's destructors.
+ //!     This can be tricky, as witnessed by [`VecDeque<T>`]: the destructor of [`VecDeque<T>`]
+ //!     can fail to call [`drop`] on all elements if one of the destructors panics. This violates
+ //!     the [`Drop`] guarantee, because it can lead to elements being deallocated without
+ //!     their destructor being called. ([`VecDeque<T>`] has no pinning projections, so this
+ //!     does not cause unsoundness.)
+ //! 4.  You must not offer any other operations that could lead to data being moved out of
+ //!     the structural fields when your type is pinned. For example, if the struct contains an
+ //!     [`Option<T>`] and there is a `take`-like operation with type
+ //!     `fn(Pin<&mut Struct<T>>) -> Option<T>`,
+ //!     that operation can be used to move a `T` out of a pinned `Struct<T>` -- which means
+ //!     pinning cannot be structural for the field holding this data.
+ //!
+ //!     For a more complex example of moving data out of a pinned type, imagine if [`RefCell<T>`]
+ //!     had a method `fn get_pin_mut(self: Pin<&mut Self>) -> Pin<&mut T>`.
+ //!     Then we could do the following:
+ //!     ```compile_fail
+ //!     fn exploit_ref_cell<T>(rc: Pin<&mut RefCell<T>>) {
+ //!         { let p = rc.as_mut().get_pin_mut(); } // Here we get pinned access to the `T`.
+ //!         let rc_shr: &RefCell<T> = rc.into_ref().get_ref();
+ //!         let b = rc_shr.borrow_mut();
+ //!         let content = &mut *b; // And here we have `&mut T` to the same data.
+ //!     }
+ //!     ```
+ //!     This is catastrophic, it means we can first pin the content of the [`RefCell<T>`]
+ //!     (using `RefCell::get_pin_mut`) and then move that content using the mutable
+ //!     reference we got later.
+ //!
+ //! ## Examples
+ //!
+ //! For a type like [`Vec<T>`], both possibilities (structural pinning or not) make sense.
+ //! A [`Vec<T>`] with structural pinning could have `get_pin`/`get_pin_mut` methods to get
+ //! pinned references to elements. However, it could *not* allow calling
+ //! [`pop`][Vec::pop] on a pinned [`Vec<T>`] because that would move the (structurally pinned)
+ //! contents! Nor could it allow [`push`][Vec::push], which might reallocate and thus also move the
+ //! contents.
+ //!
+ //! A [`Vec<T>`] without structural pinning could `impl<T> Unpin for Vec<T>`, because the contents
+ //! are never pinned and the [`Vec<T>`] itself is fine with being moved as well.
+ //! At that point pinning just has no effect on the vector at all.
+ //!
+ //! In the standard library, pointer types generally do not have structural pinning,
+ //! and thus they do not offer pinning projections. This is why `Box<T>: Unpin` holds for all `T`.
+ //! It makes sense to do this for pointer types, because moving the `Box<T>`
+ //! does not actually move the `T`: the [`Box<T>`] can be freely movable (aka `Unpin`) even if
+ //! the `T` is not. In fact, even [`Pin`]`<`[`Box`]`<T>>` and [`Pin`]`<&mut T>` are always
+ //! [`Unpin`] themselves, for the same reason: their contents (the `T`) are pinned, but the
+ //! pointers themselves can be moved without moving the pinned data. For both [`Box<T>`] and
+ //! [`Pin`]`<`[`Box`]`<T>>`, whether the content is pinned is entirely independent of whether the
+ //! pointer is pinned, meaning pinning is *not* structural.
+ //!
+ //! When implementing a [`Future`] combinator, you will usually need structural pinning
+ //! for the nested futures, as you need to get pinned references to them to call [`poll`].
+ //! But if your combinator contains any other data that does not need to be pinned,
+ //! you can make those fields not structural and hence freely access them with a
+ //! mutable reference even when you just have [`Pin`]`<&mut Self>` (such as in your own
+ //! [`poll`] implementation).
+ //!
+ //! [`Pin<P>`]: Pin
+ //! [`Deref`]: crate::ops::Deref
+ //! [`DerefMut`]: crate::ops::DerefMut
+ //! [`mem::swap`]: crate::mem::swap
+ //! [`mem::forget`]: crate::mem::forget
+ //! [`Box<T>`]: ../../std/boxed/struct.Box.html
+ //! [`Vec<T>`]: ../../std/vec/struct.Vec.html
+ //! [`Vec::set_len`]: ../../std/vec/struct.Vec.html#method.set_len
+ //! [`Box`]: ../../std/boxed/struct.Box.html
+ //! [Vec::pop]: ../../std/vec/struct.Vec.html#method.pop
+ //! [Vec::push]: ../../std/vec/struct.Vec.html#method.push
+ //! [`Rc`]: ../../std/rc/struct.Rc.html
+ //! [`RefCell<T>`]: crate::cell::RefCell
+ //! [`drop`]: Drop::drop
+ //! [`VecDeque<T>`]: ../../std/collections/struct.VecDeque.html
+ //! [`Option<T>`]: Option
+ //! [`Some(v)`]: Some
+ //! [`ptr::write`]: crate::ptr::write
+ //! [`Future`]: crate::future::Future
+ //! [drop-impl]: #drop-implementation
+ //! [drop-guarantee]: #drop-guarantee
+ //! [`poll`]: crate::future::Future::poll
+ 
+ #![stable(feature = "pin", since = "1.33.0")]
+ 
+ use crate::cmp::{self, PartialEq, PartialOrd};
+ use crate::fmt;
+ use crate::hash::{Hash, Hasher};
+ use crate::marker::{Sized, Unpin};
+ use crate::ops::{CoerceUnsized, Deref, DerefMut, DispatchFromDyn, Receiver};
+ 
+ /// A pinned pointer.
+ ///
+ /// This is a wrapper around a kind of pointer which makes that pointer "pin" its
+ /// value in place, preventing the value referenced by that pointer from being moved
+ /// unless it implements [`Unpin`].
+ ///
+ /// *See the [`pin` module] documentation for an explanation of pinning.*
+ ///
+ /// [`pin` module]: self
+ //
+ // Note: the `Clone` derive below causes unsoundness as it's possible to implement
+ // `Clone` for mutable references.
+ // See <https://internals.rust-lang.org/t/unsoundness-in-pin/11311> for more details.
+ #[stable(feature = "pin", since = "1.33.0")]
+ #[lang = "pin"]
+ #[fundamental]
+ #[repr(transparent)]
+ #[derive(Copy, Clone)]
+ pub struct Pin<P> {
+     pointer: P,
+ }
+ 
+ // The following implementations aren't derived in order to avoid soundness
+ // issues. `&self.pointer` should not be accessible to untrusted trait
+ // implementations.
+ //
+ // See <https://internals.rust-lang.org/t/unsoundness-in-pin/11311/73> for more details.
+ 
+ #[stable(feature = "pin_trait_impls", since = "1.41.0")]
+ impl<P: Deref, Q: Deref> PartialEq<Pin<Q>> for Pin<P>
+ where
+     P::Target: PartialEq<Q::Target>,
+ {
+     fn eq(&self, other: &Pin<Q>) -> bool {
+         P::Target::eq(self, other)
+     }
+ 
+     fn ne(&self, other: &Pin<Q>) -> bool {
+         P::Target::ne(self, other)
+     }
+ }
+ 
+ #[stable(feature = "pin_trait_impls", since = "1.41.0")]
+ impl<P: Deref<Target: Eq>> Eq for Pin<P> {}
+ 
+ #[stable(feature = "pin_trait_impls", since = "1.41.0")]
+ impl<P: Deref, Q: Deref> PartialOrd<Pin<Q>> for Pin<P>
+ where
+     P::Target: PartialOrd<Q::Target>,
+ {
+     fn partial_cmp(&self, other: &Pin<Q>) -> Option<cmp::Ordering> {
+         P::Target::partial_cmp(self, other)
+     }
+ 
+     fn lt(&self, other: &Pin<Q>) -> bool {
+         P::Target::lt(self, other)
+     }
+ 
+     fn le(&self, other: &Pin<Q>) -> bool {
+         P::Target::le(self, other)
+     }
+ 
+     fn gt(&self, other: &Pin<Q>) -> bool {
+         P::Target::gt(self, other)
+     }
+ 
+     fn ge(&self, other: &Pin<Q>) -> bool {
+         P::Target::ge(self, other)
+     }
+ }
+ 
+ #[stable(feature = "pin_trait_impls", since = "1.41.0")]
+ impl<P: Deref<Target: Ord>> Ord for Pin<P> {
+     fn cmp(&self, other: &Self) -> cmp::Ordering {
+         P::Target::cmp(self, other)
+     }
+ }
+ 
+ #[stable(feature = "pin_trait_impls", since = "1.41.0")]
+ impl<P: Deref<Target: Hash>> Hash for Pin<P> {
+     fn hash<H: Hasher>(&self, state: &mut H) {
+         P::Target::hash(self, state);
+     }
+ }
+ 
+ impl<P: Deref<Target: Unpin>> Pin<P> {
+     /// Construct a new `Pin<P>` around a pointer to some data of a type that
+     /// implements [`Unpin`].
+     ///
+     /// Unlike `Pin::new_unchecked`, this method is safe because the pointer
+     /// `P` dereferences to an [`Unpin`] type, which cancels the pinning guarantees.
+     #[inline(always)]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub const fn new(pointer: P) -> Pin<P> {
+         // SAFETY: the value pointed to is `Unpin`, and so has no requirements
+         // around pinning.
+         unsafe { Pin::new_unchecked(pointer) }
+     }
+ 
+     /// Unwraps this `Pin<P>` returning the underlying pointer.
+     ///
+     /// This requires that the data inside this `Pin` is [`Unpin`] so that we
+     /// can ignore the pinning invariants when unwrapping it.
+     #[inline(always)]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     #[stable(feature = "pin_into_inner", since = "1.39.0")]
+     pub const fn into_inner(pin: Pin<P>) -> P {
+         pin.pointer
+     }
+ }
+ 
+ impl<P: Deref> Pin<P> {
+     /// Construct a new `Pin<P>` around a reference to some data of a type that
+     /// may or may not implement `Unpin`.
+     ///
+     /// If `pointer` dereferences to an `Unpin` type, `Pin::new` should be used
+     /// instead.
+     ///
+     /// # Safety
+     ///
+     /// This constructor is unsafe because we cannot guarantee that the data
+     /// pointed to by `pointer` is pinned, meaning that the data will not be moved or
+     /// its storage invalidated until it gets dropped. If the constructed `Pin<P>` does
+     /// not guarantee that the data `P` points to is pinned, that is a violation of
+     /// the API contract and may lead to undefined behavior in later (safe) operations.
+     ///
+     /// By using this method, you are making a promise about the `P::Deref` and
+     /// `P::DerefMut` implementations, if they exist. Most importantly, they
+     /// must not move out of their `self` arguments: `Pin::as_mut` and `Pin::as_ref`
+     /// will call `DerefMut::deref_mut` and `Deref::deref` *on the pinned pointer*
+     /// and expect these methods to uphold the pinning invariants.
+     /// Moreover, by calling this method you promise that the reference `P`
+     /// dereferences to will not be moved out of again; in particular, it
+     /// must not be possible to obtain a `&mut P::Target` and then
+     /// move out of that reference (using, for example [`mem::swap`]).
+     ///
+     /// For example, calling `Pin::new_unchecked` on an `&'a mut T` is unsafe because
+     /// while you are able to pin it for the given lifetime `'a`, you have no control
+     /// over whether it is kept pinned once `'a` ends:
+     /// ```
+     /// use std::mem;
+     /// use std::pin::Pin;
+     ///
+     /// fn move_pinned_ref<T>(mut a: T, mut b: T) {
+     ///     unsafe {
+     ///         let p: Pin<&mut T> = Pin::new_unchecked(&mut a);
+     ///         // This should mean the pointee `a` can never move again.
+     ///     }
+     ///     mem::swap(&mut a, &mut b);
+     ///     // The address of `a` changed to `b`'s stack slot, so `a` got moved even
+     ///     // though we have previously pinned it! We have violated the pinning API contract.
+     /// }
+     /// ```
+     /// A value, once pinned, must remain pinned forever (unless its type implements `Unpin`).
+     ///
+     /// Similarly, calling `Pin::new_unchecked` on an `Rc<T>` is unsafe because there could be
+     /// aliases to the same data that are not subject to the pinning restrictions:
+     /// ```
+     /// use std::rc::Rc;
+     /// use std::pin::Pin;
+     ///
+     /// fn move_pinned_rc<T>(mut x: Rc<T>) {
+     ///     let pinned = unsafe { Pin::new_unchecked(Rc::clone(&x)) };
+     ///     {
+     ///         let p: Pin<&T> = pinned.as_ref();
+     ///         // This should mean the pointee can never move again.
+     ///     }
+     ///     drop(pinned);
+     ///     let content = Rc::get_mut(&mut x).unwrap();
+     ///     // Now, if `x` was the only reference, we have a mutable reference to
+     ///     // data that we pinned above, which we could use to move it as we have
+     ///     // seen in the previous example. We have violated the pinning API contract.
+     ///  }
+     ///  ```
+     ///
+     /// [`mem::swap`]: crate::mem::swap
+     #[lang = "new_unchecked"]
+     #[inline(always)]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub const unsafe fn new_unchecked(pointer: P) -> Pin<P> {
+         Pin { pointer }
+     }
+ 
+     /// Gets a pinned shared reference from this pinned pointer.
+     ///
+     /// This is a generic method to go from `&Pin<Pointer<T>>` to `Pin<&T>`.
+     /// It is safe because, as part of the contract of `Pin::new_unchecked`,
+     /// the pointee cannot move after `Pin<Pointer<T>>` got created.
+     /// "Malicious" implementations of `Pointer::Deref` are likewise
+     /// ruled out by the contract of `Pin::new_unchecked`.
+     #[stable(feature = "pin", since = "1.33.0")]
+     #[inline(always)]
+     pub fn as_ref(&self) -> Pin<&P::Target> {
+         // SAFETY: see documentation on this function
+         unsafe { Pin::new_unchecked(&*self.pointer) }
+     }
+ 
+     /// Unwraps this `Pin<P>` returning the underlying pointer.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe. You must guarantee that you will continue to
+     /// treat the pointer `P` as pinned after you call this function, so that
+     /// the invariants on the `Pin` type can be upheld. If the code using the
+     /// resulting `P` does not continue to maintain the pinning invariants that
+     /// is a violation of the API contract and may lead to undefined behavior in
+     /// later (safe) operations.
+     ///
+     /// If the underlying data is [`Unpin`], [`Pin::into_inner`] should be used
+     /// instead.
+     #[inline(always)]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     #[stable(feature = "pin_into_inner", since = "1.39.0")]
+     pub const unsafe fn into_inner_unchecked(pin: Pin<P>) -> P {
+         pin.pointer
+     }
+ }
+ 
+ impl<P: DerefMut> Pin<P> {
+     /// Gets a pinned mutable reference from this pinned pointer.
+     ///
+     /// This is a generic method to go from `&mut Pin<Pointer<T>>` to `Pin<&mut T>`.
+     /// It is safe because, as part of the contract of `Pin::new_unchecked`,
+     /// the pointee cannot move after `Pin<Pointer<T>>` got created.
+     /// "Malicious" implementations of `Pointer::DerefMut` are likewise
+     /// ruled out by the contract of `Pin::new_unchecked`.
+     ///
+     /// This method is useful when doing multiple calls to functions that consume the pinned type.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// use std::pin::Pin;
+     ///
+     /// # struct Type {}
+     /// impl Type {
+     ///     fn method(self: Pin<&mut Self>) {
+     ///         // do something
+     ///     }
+     ///
+     ///     fn call_method_twice(mut self: Pin<&mut Self>) {
+     ///         // `method` consumes `self`, so reborrow the `Pin<&mut Self>` via `as_mut`.
+     ///         self.as_mut().method();
+     ///         self.as_mut().method();
+     ///     }
+     /// }
+     /// ```
+     #[stable(feature = "pin", since = "1.33.0")]
+     #[inline(always)]
+     pub fn as_mut(&mut self) -> Pin<&mut P::Target> {
+         // SAFETY: see documentation on this function
+         unsafe { Pin::new_unchecked(&mut *self.pointer) }
+     }
+ 
+     /// Assigns a new value to the memory behind the pinned reference.
+     ///
+     /// This overwrites pinned data, but that is okay: its destructor gets
+     /// run before being overwritten, so no pinning guarantee is violated.
+     #[stable(feature = "pin", since = "1.33.0")]
+     #[inline(always)]
+     pub fn set(&mut self, value: P::Target)
+     where
+         P::Target: Sized,
+     {
+         *(self.pointer) = value;
+     }
+ }
+ 
+ impl<'a, T: ?Sized> Pin<&'a T> {
+     /// Constructs a new pin by mapping the interior value.
+     ///
+     /// For example, if you  wanted to get a `Pin` of a field of something,
+     /// you could use this to get access to that field in one line of code.
+     /// However, there are several gotchas with these "pinning projections";
+     /// see the [`pin` module] documentation for further details on that topic.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe. You must guarantee that the data you return
+     /// will not move so long as the argument value does not move (for example,
+     /// because it is one of the fields of that value), and also that you do
+     /// not move out of the argument you receive to the interior function.
+     ///
+     /// [`pin` module]: self#projections-and-structural-pinning
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub unsafe fn map_unchecked<U, F>(self, func: F) -> Pin<&'a U>
+     where
+         U: ?Sized,
+         F: FnOnce(&T) -> &U,
+     {
+         let pointer = &*self.pointer;
+         let new_pointer = func(pointer);
+ 
+         // SAFETY: the safety contract for `new_unchecked` must be
+         // upheld by the caller.
+         unsafe { Pin::new_unchecked(new_pointer) }
+     }
+ 
+     /// Gets a shared reference out of a pin.
+     ///
+     /// This is safe because it is not possible to move out of a shared reference.
+     /// It may seem like there is an issue here with interior mutability: in fact,
+     /// it *is* possible to move a `T` out of a `&RefCell<T>`. However, this is
+     /// not a problem as long as there does not also exist a `Pin<&T>` pointing
+     /// to the same data, and `RefCell<T>` does not let you create a pinned reference
+     /// to its contents. See the discussion on ["pinning projections"] for further
+     /// details.
+     ///
+     /// Note: `Pin` also implements `Deref` to the target, which can be used
+     /// to access the inner value. However, `Deref` only provides a reference
+     /// that lives for as long as the borrow of the `Pin`, not the lifetime of
+     /// the `Pin` itself. This method allows turning the `Pin` into a reference
+     /// with the same lifetime as the original `Pin`.
+     ///
+     /// ["pinning projections"]: self#projections-and-structural-pinning
+     #[inline(always)]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub const fn get_ref(self) -> &'a T {
+         self.pointer
+     }
+ }
+ 
+ impl<'a, T: ?Sized> Pin<&'a mut T> {
+     /// Converts this `Pin<&mut T>` into a `Pin<&T>` with the same lifetime.
+     #[inline(always)]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub const fn into_ref(self) -> Pin<&'a T> {
+         Pin { pointer: self.pointer }
+     }
+ 
+     /// Gets a mutable reference to the data inside of this `Pin`.
+     ///
+     /// This requires that the data inside this `Pin` is `Unpin`.
+     ///
+     /// Note: `Pin` also implements `DerefMut` to the data, which can be used
+     /// to access the inner value. However, `DerefMut` only provides a reference
+     /// that lives for as long as the borrow of the `Pin`, not the lifetime of
+     /// the `Pin` itself. This method allows turning the `Pin` into a reference
+     /// with the same lifetime as the original `Pin`.
+     #[inline(always)]
+     #[stable(feature = "pin", since = "1.33.0")]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     pub const fn get_mut(self) -> &'a mut T
+     where
+         T: Unpin,
+     {
+         self.pointer
+     }
+ 
+     /// Gets a mutable reference to the data inside of this `Pin`.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe. You must guarantee that you will never move
+     /// the data out of the mutable reference you receive when you call this
+     /// function, so that the invariants on the `Pin` type can be upheld.
+     ///
+     /// If the underlying data is `Unpin`, `Pin::get_mut` should be used
+     /// instead.
+     #[inline(always)]
+     #[stable(feature = "pin", since = "1.33.0")]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     pub const unsafe fn get_unchecked_mut(self) -> &'a mut T {
+         self.pointer
+     }
+ 
+     /// Construct a new pin by mapping the interior value.
+     ///
+     /// For example, if you  wanted to get a `Pin` of a field of something,
+     /// you could use this to get access to that field in one line of code.
+     /// However, there are several gotchas with these "pinning projections";
+     /// see the [`pin` module] documentation for further details on that topic.
+     ///
+     /// # Safety
+     ///
+     /// This function is unsafe. You must guarantee that the data you return
+     /// will not move so long as the argument value does not move (for example,
+     /// because it is one of the fields of that value), and also that you do
+     /// not move out of the argument you receive to the interior function.
+     ///
+     /// [`pin` module]: self#projections-and-structural-pinning
+     #[stable(feature = "pin", since = "1.33.0")]
+     pub unsafe fn map_unchecked_mut<U, F>(self, func: F) -> Pin<&'a mut U>
+     where
+         U: ?Sized,
+         F: FnOnce(&mut T) -> &mut U,
+     {
+         // SAFETY: the caller is responsible for not moving the
+         // value out of this reference.
+         let pointer = unsafe { Pin::get_unchecked_mut(self) };
+         let new_pointer = func(pointer);
+         // SAFETY: as the value of `this` is guaranteed to not have
+         // been moved out, this call to `new_unchecked` is safe.
+         unsafe { Pin::new_unchecked(new_pointer) }
+     }
+ }
+ 
+ impl<T: ?Sized> Pin<&'static T> {
+     /// Get a pinned reference from a static reference.
+     ///
+     /// This is safe, because `T` is borrowed for the `'static` lifetime, which
+     /// never ends.
+     #[unstable(feature = "pin_static_ref", issue = "78186")]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     pub const fn static_ref(r: &'static T) -> Pin<&'static T> {
+         // SAFETY: The 'static borrow guarantees the data will not be
+         // moved/invalidated until it gets dropped (which is never).
+         unsafe { Pin::new_unchecked(r) }
+     }
+ }
+ 
+ impl<T: ?Sized> Pin<&'static mut T> {
+     /// Get a pinned mutable reference from a static mutable reference.
+     ///
+     /// This is safe, because `T` is borrowed for the `'static` lifetime, which
+     /// never ends.
+     #[unstable(feature = "pin_static_ref", issue = "78186")]
+     #[rustc_const_unstable(feature = "const_pin", issue = "76654")]
+     pub const fn static_mut(r: &'static mut T) -> Pin<&'static mut T> {
+         // SAFETY: The 'static borrow guarantees the data will not be
+         // moved/invalidated until it gets dropped (which is never).
+         unsafe { Pin::new_unchecked(r) }
+     }
+ }
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P: Deref> Deref for Pin<P> {
+     type Target = P::Target;
+     fn deref(&self) -> &P::Target {
+         Pin::get_ref(Pin::as_ref(self))
+     }
+ }
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P: DerefMut<Target: Unpin>> DerefMut for Pin<P> {
+     fn deref_mut(&mut self) -> &mut P::Target {
+         Pin::get_mut(Pin::as_mut(self))
+     }
+ }
+ 
+ #[unstable(feature = "receiver_trait", issue = "none")]
+ impl<P: Receiver> Receiver for Pin<P> {}
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P: fmt::Debug> fmt::Debug for Pin<P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Debug::fmt(&self.pointer, f)
+     }
+ }
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P: fmt::Display> fmt::Display for Pin<P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Display::fmt(&self.pointer, f)
+     }
+ }
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P: fmt::Pointer> fmt::Pointer for Pin<P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Pointer::fmt(&self.pointer, f)
+     }
+ }
+ 
+ // Note: this means that any impl of `CoerceUnsized` that allows coercing from
+ // a type that impls `Deref<Target=impl !Unpin>` to a type that impls
+ // `Deref<Target=Unpin>` is unsound. Any such impl would probably be unsound
+ // for other reasons, though, so we just need to take care not to allow such
+ // impls to land in std.
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P, U> CoerceUnsized<Pin<U>> for Pin<P> where P: CoerceUnsized<U> {}
+ 
+ #[stable(feature = "pin", since = "1.33.0")]
+ impl<P, U> DispatchFromDyn<Pin<U>> for Pin<P> where P: DispatchFromDyn<U> {}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/prelude/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/prelude/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/prelude/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/prelude/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,5 ----
+ //! The libcore prelude
+ 
+ #![stable(feature = "core_prelude", since = "1.4.0")]
+ 
+ pub mod v1;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/prelude/v1.rs gcc-16-20251102/libgrust/rustc-lib/core/src/prelude/v1.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/prelude/v1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/prelude/v1.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,78 ----
+ //! The core prelude
+ //!
+ //! This module is intended for users of libcore which do not link to libstd as
+ //! well. This module is imported by default when `#![no_std]` is used in the
+ //! same manner as the standard library's prelude.
+ 
+ #![stable(feature = "core_prelude", since = "1.4.0")]
+ 
+ // Re-exported core operators
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::marker::{Copy, Send, Sized, Sync, Unpin};
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::ops::{Drop, Fn, FnMut, FnOnce};
+ 
+ // Re-exported functions
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::mem::drop;
+ 
+ // Re-exported types and traits
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::clone::Clone;
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::cmp::{Eq, Ord, PartialEq, PartialOrd};
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::convert::{AsMut, AsRef, From, Into};
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::default::Default;
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::iter::{DoubleEndedIterator, ExactSizeIterator};
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::iter::{Extend, IntoIterator, Iterator};
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::option::Option::{self, None, Some};
+ #[stable(feature = "core_prelude", since = "1.4.0")]
+ #[doc(no_inline)]
+ pub use crate::result::Result::{self, Err, Ok};
+ 
+ // Re-exported built-in macros
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[doc(no_inline)]
+ pub use crate::fmt::macros::Debug;
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[doc(no_inline)]
+ pub use crate::hash::macros::Hash;
+ 
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow(deprecated)]
+ #[doc(no_inline)]
+ pub use crate::{
+     asm, assert, cfg, column, compile_error, concat, concat_idents, env, file, format_args,
+     format_args_nl, global_asm, include, include_bytes, include_str, line, llvm_asm, log_syntax,
+     module_path, option_env, stringify, trace_macros,
+ };
+ 
+ #[stable(feature = "builtin_macro_prelude", since = "1.38.0")]
+ #[allow(deprecated)]
+ #[doc(no_inline)]
+ pub use crate::macros::builtin::{
+     bench, global_allocator, test, test_case, RustcDecodable, RustcEncodable,
+ };
+ 
+ #[unstable(
+     feature = "cfg_accessible",
+     issue = "64797",
+     reason = "`cfg_accessible` is not fully implemented"
+ )]
+ #[doc(no_inline)]
+ pub use crate::macros::builtin::cfg_accessible;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/primitive.rs gcc-16-20251102/libgrust/rustc-lib/core/src/primitive.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/primitive.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/primitive.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,67 ----
+ //! This module reexports the primitive types to allow usage that is not
+ //! possibly shadowed by other declared types.
+ //!
+ //! This is normally only useful in macro generated code.
+ //!
+ //! An example of this is when generating a new struct and an impl for it:
+ //!
+ //! ```rust,compile_fail
+ //! pub struct bool;
+ //!
+ //! impl QueryId for bool {
+ //!     const SOME_PROPERTY: bool = true;
+ //! }
+ //!
+ //! # trait QueryId { const SOME_PROPERTY: core::primitive::bool; }
+ //! ```
+ //!
+ //! Note that the `SOME_PROPERTY` associated constant would not compile, as its
+ //! type `bool` refers to the struct, rather than to the primitive bool type.
+ //!
+ //! A correct implementation could look like:
+ //!
+ //! ```rust
+ //! # #[allow(non_camel_case_types)]
+ //! pub struct bool;
+ //!
+ //! impl QueryId for bool {
+ //!     const SOME_PROPERTY: core::primitive::bool = true;
+ //! }
+ //!
+ //! # trait QueryId { const SOME_PROPERTY: core::primitive::bool; }
+ //! ```
+ 
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use bool;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use char;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use f32;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use f64;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use i128;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use i16;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use i32;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use i64;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use i8;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use isize;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use str;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use u128;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use u16;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use u32;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use u64;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use u8;
+ #[stable(feature = "core_primitive", since = "1.43.0")]
+ pub use usize;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/const_ptr.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/const_ptr.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/const_ptr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/const_ptr.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1043 ----
+ use super::*;
+ use crate::cmp::Ordering::{self, Equal, Greater, Less};
+ use crate::intrinsics;
+ use crate::mem;
+ use crate::slice::{self, SliceIndex};
+ 
+ #[lang = "const_ptr"]
+ impl<T: ?Sized> *const T {
+     /// Returns `true` if the pointer is null.
+     ///
+     /// Note that unsized types have many possible null pointers, as only the
+     /// raw data pointer is considered, not their length, vtable, etc.
+     /// Therefore, two pointers that are null may still not compare equal to
+     /// each other.
+     ///
+     /// ## Behavior during const evaluation
+     ///
+     /// When this function is used during const evaluation, it may return `false` for pointers
+     /// that turn out to be null at runtime. Specifically, when a pointer to some memory
+     /// is offset beyond its bounds in such a way that the resulting pointer is null,
+     /// the function will still return `false`. There is no way for CTFE to know
+     /// the absolute position of that memory, so we cannot tell if the pointer is
+     /// null or not.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s: &str = "Follow the rabbit";
+     /// let ptr: *const u8 = s.as_ptr();
+     /// assert!(!ptr.is_null());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_ptr_is_null", issue = "74939")]
+     #[inline]
+     pub const fn is_null(self) -> bool {
+         // Compare via a cast to a thin pointer, so fat pointers are only
+         // considering their "data" part for null-ness.
+         (self as *const u8).guaranteed_eq(null())
+     }
+ 
+     /// Casts to a pointer of another type.
+     #[stable(feature = "ptr_cast", since = "1.38.0")]
+     #[rustc_const_stable(feature = "const_ptr_cast", since = "1.38.0")]
+     #[inline]
+     pub const fn cast<U>(self) -> *const U {
+         self as _
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a shared reference to
+     /// the value wrapped in `Some`. If the value may be uninitialized, [`as_uninit_ref`]
+     /// must be used instead.
+     ///
+     /// [`as_uninit_ref`]: #method.as_uninit_ref
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * The pointer must point to an initialized instance of `T`.
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     /// (The part about being initialized is not yet fully decided, but until
+     /// it is, the only safe approach is to ensure that they are indeed initialized.)
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let ptr: *const u8 = &10u8 as *const u8;
+     ///
+     /// unsafe {
+     ///     if let Some(val_back) = ptr.as_ref() {
+     ///         println!("We got back the value: {}!", val_back);
+     ///     }
+     /// }
+     /// ```
+     ///
+     /// # Null-unchecked version
+     ///
+     /// If you are sure the pointer can never be null and are looking for some kind of
+     /// `as_ref_unchecked` that returns the `&T` instead of `Option<&T>`, know that you can
+     /// dereference the pointer directly.
+     ///
+     /// ```
+     /// let ptr: *const u8 = &10u8 as *const u8;
+     ///
+     /// unsafe {
+     ///     let val_back = &*ptr;
+     ///     println!("We got back the value: {}!", val_back);
+     /// }
+     /// ```
+     #[stable(feature = "ptr_as_ref", since = "1.9.0")]
+     #[inline]
+     pub unsafe fn as_ref<'a>(self) -> Option<&'a T> {
+         // SAFETY: the caller must guarantee that `self` is valid
+         // for a reference if it isn't null.
+         if self.is_null() { None } else { unsafe { Some(&*self) } }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a shared reference to
+     /// the value wrapped in `Some`. In contrast to [`as_ref`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// [`as_ref`]: #method.as_ref
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(ptr_as_uninit)]
+     ///
+     /// let ptr: *const u8 = &10u8 as *const u8;
+     ///
+     /// unsafe {
+     ///     if let Some(val_back) = ptr.as_uninit_ref() {
+     ///         println!("We got back the value: {}!", val_back.assume_init());
+     ///     }
+     /// }
+     /// ```
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_ref<'a>(self) -> Option<&'a MaybeUninit<T>>
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         if self.is_null() { None } else { Some(unsafe { &*(self as *const MaybeUninit<T>) }) }
+     }
+ 
+     /// Calculates the offset from a pointer.
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and resulting pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * The computed offset, **in bytes**, cannot overflow an `isize`.
+     ///
+     /// * The offset being in bounds cannot rely on "wrapping around" the address
+     ///   space. That is, the infinite-precision sum, **in bytes** must fit in a usize.
+     ///
+     /// The compiler and standard library generally tries to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `vec.as_ptr().add(vec.len())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// Consider using [`wrapping_offset`] instead if these constraints are
+     /// difficult to satisfy. The only advantage of this method is that it
+     /// enables more aggressive compiler optimizations.
+     ///
+     /// [`wrapping_offset`]: #method.wrapping_offset
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s: &str = "123";
+     /// let ptr: *const u8 = s.as_ptr();
+     ///
+     /// unsafe {
+     ///     println!("{}", *ptr.offset(1) as char);
+     ///     println!("{}", *ptr.offset(2) as char);
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const unsafe fn offset(self, count: isize) -> *const T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset`.
+         unsafe { intrinsics::offset(self, count) }
+     }
+ 
+     /// Calculates the offset from a pointer using wrapping arithmetic.
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// The resulting pointer does not need to be in bounds, but it is
+     /// potentially hazardous to dereference (which requires `unsafe`).
+     ///
+     /// In particular, the resulting pointer remains attached to the same allocated
+     /// object that `self` points to. It may *not* be used to access a
+     /// different allocated object. Note that in Rust,
+     /// every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// In other words, `x.wrapping_offset((y as usize).wrapping_sub(x as usize) / size_of::<T>())`
+     /// is *not* the same as `y`, and dereferencing it is undefined behavior
+     /// unless `x` and `y` point into the same allocated object.
+     ///
+     /// Compared to [`offset`], this method basically delays the requirement of staying
+     /// within the same allocated object: [`offset`] is immediate Undefined Behavior when
+     /// crossing object boundaries; `wrapping_offset` produces a pointer but still leads
+     /// to Undefined Behavior if that pointer is dereferenced. [`offset`] can be optimized
+     /// better and is thus preferable in performance-sensitive code.
+     ///
+     /// If you need to cross object boundaries, cast the pointer to an integer and
+     /// do the arithmetic there.
+     ///
+     /// [`offset`]: #method.offset
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // Iterate using a raw pointer in increments of two elements
+     /// let data = [1u8, 2, 3, 4, 5];
+     /// let mut ptr: *const u8 = data.as_ptr();
+     /// let step = 2;
+     /// let end_rounded_up = ptr.wrapping_offset(6);
+     ///
+     /// // This loop prints "1, 3, 5, "
+     /// while ptr != end_rounded_up {
+     ///     unsafe {
+     ///         print!("{}, ", *ptr);
+     ///     }
+     ///     ptr = ptr.wrapping_offset(step);
+     /// }
+     /// ```
+     #[stable(feature = "ptr_wrapping_offset", since = "1.16.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn wrapping_offset(self, count: isize) -> *const T
+     where
+         T: Sized,
+     {
+         // SAFETY: the `arith_offset` intrinsic has no prerequisites to be called.
+         unsafe { intrinsics::arith_offset(self, count) }
+     }
+ 
+     /// Calculates the distance between two pointers. The returned value is in
+     /// units of T: the distance in bytes is divided by `mem::size_of::<T>()`.
+     ///
+     /// This function is the inverse of [`offset`].
+     ///
+     /// [`offset`]: #method.offset
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and other pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * Both pointers must be *derived from* a pointer to the same object.
+     ///   (See below for an example.)
+     ///
+     /// * The distance between the pointers, **in bytes**, cannot overflow an `isize`.
+     ///
+     /// * The distance between the pointers, in bytes, must be an exact multiple
+     ///   of the size of `T`.
+     ///
+     /// * The distance being in bounds cannot rely on "wrapping around" the address space.
+     ///
+     /// The compiler and standard library generally try to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `ptr_into_vec.offset_from(vec.as_ptr())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// # Panics
+     ///
+     /// This function panics if `T` is a Zero-Sized Type ("ZST").
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let a = [0; 5];
+     /// let ptr1: *const i32 = &a[1];
+     /// let ptr2: *const i32 = &a[3];
+     /// unsafe {
+     ///     assert_eq!(ptr2.offset_from(ptr1), 2);
+     ///     assert_eq!(ptr1.offset_from(ptr2), -2);
+     ///     assert_eq!(ptr1.offset(2), ptr2);
+     ///     assert_eq!(ptr2.offset(-2), ptr1);
+     /// }
+     /// ```
+     ///
+     /// *Incorrect* usage:
+     ///
+     /// ```rust,no_run
+     /// let ptr1 = Box::into_raw(Box::new(0u8)) as *const u8;
+     /// let ptr2 = Box::into_raw(Box::new(1u8)) as *const u8;
+     /// let diff = (ptr2 as isize).wrapping_sub(ptr1 as isize);
+     /// // Make ptr2_other an "alias" of ptr2, but derived from ptr1.
+     /// let ptr2_other = (ptr1 as *const u8).wrapping_offset(diff);
+     /// assert_eq!(ptr2 as usize, ptr2_other as usize);
+     /// // Since ptr2_other and ptr2 are derived from pointers to different objects,
+     /// // computing their offset is undefined behavior, even though
+     /// // they point to the same address!
+     /// unsafe {
+     ///     let zero = ptr2_other.offset_from(ptr2); // Undefined Behavior
+     /// }
+     /// ```
+     #[stable(feature = "ptr_offset_from", since = "1.47.0")]
+     #[rustc_const_unstable(feature = "const_ptr_offset_from", issue = "41079")]
+     #[inline]
+     pub const unsafe fn offset_from(self, origin: *const T) -> isize
+     where
+         T: Sized,
+     {
+         let pointee_size = mem::size_of::<T>();
+         assert!(0 < pointee_size && pointee_size <= isize::MAX as usize);
+         // SAFETY: the caller must uphold the safety contract for `ptr_offset_from`.
+         unsafe { intrinsics::ptr_offset_from(self, origin) }
+     }
+ 
+     /// Returns whether two pointers are guaranteed to be equal.
+     ///
+     /// At runtime this function behaves like `self == other`.
+     /// However, in some contexts (e.g., compile-time evaluation),
+     /// it is not always possible to determine equality of two pointers, so this function may
+     /// spuriously return `false` for pointers that later actually turn out to be equal.
+     /// But when it returns `true`, the pointers are guaranteed to be equal.
+     ///
+     /// This function is the mirror of [`guaranteed_ne`], but not its inverse. There are pointer
+     /// comparisons for which both functions return `false`.
+     ///
+     /// [`guaranteed_ne`]: #method.guaranteed_ne
+     ///
+     /// The return value may change depending on the compiler version and unsafe code may not
+     /// rely on the result of this function for soundness. It is suggested to only use this function
+     /// for performance optimizations where spurious `false` return values by this function do not
+     /// affect the outcome, but just the performance.
+     /// The consequences of using this method to make runtime and compile-time code behave
+     /// differently have not been explored. This method should not be used to introduce such
+     /// differences, and it should also not be stabilized before we have a better understanding
+     /// of this issue.
+     #[unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[rustc_const_unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[inline]
+     pub const fn guaranteed_eq(self, other: *const T) -> bool
+     where
+         T: Sized,
+     {
+         intrinsics::ptr_guaranteed_eq(self, other)
+     }
+ 
+     /// Returns whether two pointers are guaranteed to be unequal.
+     ///
+     /// At runtime this function behaves like `self != other`.
+     /// However, in some contexts (e.g., compile-time evaluation),
+     /// it is not always possible to determine the inequality of two pointers, so this function may
+     /// spuriously return `false` for pointers that later actually turn out to be unequal.
+     /// But when it returns `true`, the pointers are guaranteed to be unequal.
+     ///
+     /// This function is the mirror of [`guaranteed_eq`], but not its inverse. There are pointer
+     /// comparisons for which both functions return `false`.
+     ///
+     /// [`guaranteed_eq`]: #method.guaranteed_eq
+     ///
+     /// The return value may change depending on the compiler version and unsafe code may not
+     /// rely on the result of this function for soundness. It is suggested to only use this function
+     /// for performance optimizations where spurious `false` return values by this function do not
+     /// affect the outcome, but just the performance.
+     /// The consequences of using this method to make runtime and compile-time code behave
+     /// differently have not been explored. This method should not be used to introduce such
+     /// differences, and it should also not be stabilized before we have a better understanding
+     /// of this issue.
+     #[unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[rustc_const_unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[inline]
+     pub const fn guaranteed_ne(self, other: *const T) -> bool
+     where
+         T: Sized,
+     {
+         intrinsics::ptr_guaranteed_ne(self, other)
+     }
+ 
+     /// Calculates the offset from a pointer (convenience for `.offset(count as isize)`).
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and resulting pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * The computed offset, **in bytes**, cannot overflow an `isize`.
+     ///
+     /// * The offset being in bounds cannot rely on "wrapping around" the address
+     ///   space. That is, the infinite-precision sum must fit in a `usize`.
+     ///
+     /// The compiler and standard library generally tries to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `vec.as_ptr().add(vec.len())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// Consider using [`wrapping_add`] instead if these constraints are
+     /// difficult to satisfy. The only advantage of this method is that it
+     /// enables more aggressive compiler optimizations.
+     ///
+     /// [`wrapping_add`]: #method.wrapping_add
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s: &str = "123";
+     /// let ptr: *const u8 = s.as_ptr();
+     ///
+     /// unsafe {
+     ///     println!("{}", *ptr.add(1) as char);
+     ///     println!("{}", *ptr.add(2) as char);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const unsafe fn add(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset`.
+         unsafe { self.offset(count as isize) }
+     }
+ 
+     /// Calculates the offset from a pointer (convenience for
+     /// `.offset((count as isize).wrapping_neg())`).
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and resulting pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * The computed offset cannot exceed `isize::MAX` **bytes**.
+     ///
+     /// * The offset being in bounds cannot rely on "wrapping around" the address
+     ///   space. That is, the infinite-precision sum must fit in a usize.
+     ///
+     /// The compiler and standard library generally tries to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `vec.as_ptr().add(vec.len()).sub(vec.len())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// Consider using [`wrapping_sub`] instead if these constraints are
+     /// difficult to satisfy. The only advantage of this method is that it
+     /// enables more aggressive compiler optimizations.
+     ///
+     /// [`wrapping_sub`]: #method.wrapping_sub
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s: &str = "123";
+     ///
+     /// unsafe {
+     ///     let end: *const u8 = s.as_ptr().add(3);
+     ///     println!("{}", *end.sub(1) as char);
+     ///     println!("{}", *end.sub(2) as char);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const unsafe fn sub(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset`.
+         unsafe { self.offset((count as isize).wrapping_neg()) }
+     }
+ 
+     /// Calculates the offset from a pointer using wrapping arithmetic.
+     /// (convenience for `.wrapping_offset(count as isize)`)
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// The resulting pointer does not need to be in bounds, but it is
+     /// potentially hazardous to dereference (which requires `unsafe`).
+     ///
+     /// In particular, the resulting pointer remains attached to the same allocated
+     /// object that `self` points to. It may *not* be used to access a
+     /// different allocated object. Note that in Rust,
+     /// every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// Compared to [`add`], this method basically delays the requirement of staying
+     /// within the same allocated object: [`add`] is immediate Undefined Behavior when
+     /// crossing object boundaries; `wrapping_add` produces a pointer but still leads
+     /// to Undefined Behavior if that pointer is dereferenced. [`add`] can be optimized
+     /// better and is thus preferable in performance-sensitive code.
+     ///
+     /// If you need to cross object boundaries, cast the pointer to an integer and
+     /// do the arithmetic there.
+     ///
+     /// [`add`]: #method.add
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // Iterate using a raw pointer in increments of two elements
+     /// let data = [1u8, 2, 3, 4, 5];
+     /// let mut ptr: *const u8 = data.as_ptr();
+     /// let step = 2;
+     /// let end_rounded_up = ptr.wrapping_add(6);
+     ///
+     /// // This loop prints "1, 3, 5, "
+     /// while ptr != end_rounded_up {
+     ///     unsafe {
+     ///         print!("{}, ", *ptr);
+     ///     }
+     ///     ptr = ptr.wrapping_add(step);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn wrapping_add(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         self.wrapping_offset(count as isize)
+     }
+ 
+     /// Calculates the offset from a pointer using wrapping arithmetic.
+     /// (convenience for `.wrapping_offset((count as isize).wrapping_sub())`)
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// The resulting pointer does not need to be in bounds, but it is
+     /// potentially hazardous to dereference (which requires `unsafe`).
+     ///
+     /// In particular, the resulting pointer remains attached to the same allocated
+     /// object that `self` points to. It may *not* be used to access a
+     /// different allocated object. Note that in Rust,
+     /// every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// Compared to [`sub`], this method basically delays the requirement of staying
+     /// within the same allocated object: [`sub`] is immediate Undefined Behavior when
+     /// crossing object boundaries; `wrapping_sub` produces a pointer but still leads
+     /// to Undefined Behavior if that pointer is dereferenced. [`sub`] can be optimized
+     /// better and is thus preferable in performance-sensitive code.
+     ///
+     /// If you need to cross object boundaries, cast the pointer to an integer and
+     /// do the arithmetic there.
+     ///
+     /// [`sub`]: #method.sub
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // Iterate using a raw pointer in increments of two elements (backwards)
+     /// let data = [1u8, 2, 3, 4, 5];
+     /// let mut ptr: *const u8 = data.as_ptr();
+     /// let start_rounded_down = ptr.wrapping_sub(2);
+     /// ptr = ptr.wrapping_add(4);
+     /// let step = 2;
+     /// // This loop prints "5, 3, 1, "
+     /// while ptr != start_rounded_down {
+     ///     unsafe {
+     ///         print!("{}, ", *ptr);
+     ///     }
+     ///     ptr = ptr.wrapping_sub(step);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn wrapping_sub(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         self.wrapping_offset((count as isize).wrapping_neg())
+     }
+ 
+     /// Sets the pointer value to `ptr`.
+     ///
+     /// In case `self` is a (fat) pointer to an unsized type, this operation
+     /// will only affect the pointer part, whereas for (thin) pointers to
+     /// sized types, this has the same effect as a simple assignment.
+     ///
+     /// The resulting pointer will have provenance of `val`, i.e., for a fat
+     /// pointer, this operation is semantically the same as creating a new
+     /// fat pointer with the data pointer value of `val` but the metadata of
+     /// `self`.
+     ///
+     /// # Examples
+     ///
+     /// This function is primarily useful for allowing byte-wise pointer
+     /// arithmetic on potentially fat pointers:
+     ///
+     /// ```
+     /// #![feature(set_ptr_value)]
+     /// # use core::fmt::Debug;
+     /// let arr: [i32; 3] = [1, 2, 3];
+     /// let mut ptr = &arr[0] as *const dyn Debug;
+     /// let thin = ptr as *const u8;
+     /// unsafe {
+     ///     ptr = ptr.set_ptr_value(thin.add(8));
+     ///     # assert_eq!(*(ptr as *const i32), 3);
+     ///     println!("{:?}", &*ptr); // will print "3"
+     /// }
+     /// ```
+     #[unstable(feature = "set_ptr_value", issue = "75091")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[inline]
+     pub fn set_ptr_value(mut self, val: *const u8) -> Self {
+         let thin = &mut self as *mut *const T as *mut *const u8;
+         // SAFETY: In case of a thin pointer, this operations is identical
+         // to a simple assignment. In case of a fat pointer, with the current
+         // fat pointer layout implementation, the first field of such a
+         // pointer is always the data pointer, which is likewise assigned.
+         unsafe { *thin = val };
+         self
+     }
+ 
+     /// Reads the value from `self` without moving it. This leaves the
+     /// memory in `self` unchanged.
+     ///
+     /// See [`ptr::read`] for safety concerns and examples.
+     ///
+     /// [`ptr::read`]: ./ptr/fn.read.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn read(self) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `read`.
+         unsafe { read(self) }
+     }
+ 
+     /// Performs a volatile read of the value from `self` without moving it. This
+     /// leaves the memory in `self` unchanged.
+     ///
+     /// Volatile operations are intended to act on I/O memory, and are guaranteed
+     /// to not be elided or reordered by the compiler across other volatile
+     /// operations.
+     ///
+     /// See [`ptr::read_volatile`] for safety concerns and examples.
+     ///
+     /// [`ptr::read_volatile`]: ./ptr/fn.read_volatile.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn read_volatile(self) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `read_volatile`.
+         unsafe { read_volatile(self) }
+     }
+ 
+     /// Reads the value from `self` without moving it. This leaves the
+     /// memory in `self` unchanged.
+     ///
+     /// Unlike `read`, the pointer may be unaligned.
+     ///
+     /// See [`ptr::read_unaligned`] for safety concerns and examples.
+     ///
+     /// [`ptr::read_unaligned`]: ./ptr/fn.read_unaligned.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn read_unaligned(self) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `read_unaligned`.
+         unsafe { read_unaligned(self) }
+     }
+ 
+     /// Copies `count * size_of<T>` bytes from `self` to `dest`. The source
+     /// and destination may overlap.
+     ///
+     /// NOTE: this has the *same* argument order as [`ptr::copy`].
+     ///
+     /// See [`ptr::copy`] for safety concerns and examples.
+     ///
+     /// [`ptr::copy`]: ./ptr/fn.copy.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn copy_to(self, dest: *mut T, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `copy`.
+         unsafe { copy(self, dest, count) }
+     }
+ 
+     /// Copies `count * size_of<T>` bytes from `self` to `dest`. The source
+     /// and destination may *not* overlap.
+     ///
+     /// NOTE: this has the *same* argument order as [`ptr::copy_nonoverlapping`].
+     ///
+     /// See [`ptr::copy_nonoverlapping`] for safety concerns and examples.
+     ///
+     /// [`ptr::copy_nonoverlapping`]: ./ptr/fn.copy_nonoverlapping.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn copy_to_nonoverlapping(self, dest: *mut T, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `copy_nonoverlapping`.
+         unsafe { copy_nonoverlapping(self, dest, count) }
+     }
+ 
+     /// Computes the offset that needs to be applied to the pointer in order to make it aligned to
+     /// `align`.
+     ///
+     /// If it is not possible to align the pointer, the implementation returns
+     /// `usize::MAX`. It is permissible for the implementation to *always*
+     /// return `usize::MAX`. Only your algorithm's performance can depend
+     /// on getting a usable offset here, not its correctness.
+     ///
+     /// The offset is expressed in number of `T` elements, and not bytes. The value returned can be
+     /// used with the `wrapping_add` method.
+     ///
+     /// There are no guarantees whatsoever that offsetting the pointer will not overflow or go
+     /// beyond the allocation that the pointer points into. It is up to the caller to ensure that
+     /// the returned offset is correct in all terms other than alignment.
+     ///
+     /// # Panics
+     ///
+     /// The function panics if `align` is not a power-of-two.
+     ///
+     /// # Examples
+     ///
+     /// Accessing adjacent `u8` as `u16`
+     ///
+     /// ```
+     /// # fn foo(n: usize) {
+     /// # use std::mem::align_of;
+     /// # unsafe {
+     /// let x = [5u8, 6u8, 7u8, 8u8, 9u8];
+     /// let ptr = x.as_ptr().add(n) as *const u8;
+     /// let offset = ptr.align_offset(align_of::<u16>());
+     /// if offset < x.len() - n - 1 {
+     ///     let u16_ptr = ptr.add(offset) as *const u16;
+     ///     assert_ne!(*u16_ptr, 500);
+     /// } else {
+     ///     // while the pointer can be aligned via `offset`, it would point
+     ///     // outside the allocation
+     /// }
+     /// # } }
+     /// ```
+     #[stable(feature = "align_offset", since = "1.36.0")]
+     pub fn align_offset(self, align: usize) -> usize
+     where
+         T: Sized,
+     {
+         if !align.is_power_of_two() {
+             panic!("align_offset: align is not a power-of-two");
+         }
+         // SAFETY: `align` has been checked to be a power of 2 above
+         unsafe { align_offset(self, align) }
+     }
+ }
+ 
+ #[lang = "const_slice_ptr"]
+ impl<T> *const [T] {
+     /// Returns the length of a raw slice.
+     ///
+     /// The returned value is the number of **elements**, not the number of bytes.
+     ///
+     /// This function is safe, even when the raw slice cannot be cast to a slice
+     /// reference because the pointer is null or unaligned.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_len)]
+     ///
+     /// use std::ptr;
+     ///
+     /// let slice: *const [i8] = ptr::slice_from_raw_parts(ptr::null(), 3);
+     /// assert_eq!(slice.len(), 3);
+     /// ```
+     #[inline]
+     #[unstable(feature = "slice_ptr_len", issue = "71146")]
+     #[rustc_const_unstable(feature = "const_slice_ptr_len", issue = "71146")]
+     pub const fn len(self) -> usize {
+         // SAFETY: this is safe because `*const [T]` and `FatPtr<T>` have the same layout.
+         // Only `std` can make this guarantee.
+         unsafe { Repr { rust: self }.raw }.len
+     }
+ 
+     /// Returns a raw pointer to the slice's buffer.
+     ///
+     /// This is equivalent to casting `self` to `*const T`, but more type-safe.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_get)]
+     /// use std::ptr;
+     ///
+     /// let slice: *const [i8] = ptr::slice_from_raw_parts(ptr::null(), 3);
+     /// assert_eq!(slice.as_ptr(), 0 as *const i8);
+     /// ```
+     #[inline]
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[rustc_const_unstable(feature = "slice_ptr_get", issue = "74265")]
+     pub const fn as_ptr(self) -> *const T {
+         self as *const T
+     }
+ 
+     /// Returns a raw pointer to an element or subslice, without doing bounds
+     /// checking.
+     ///
+     /// Calling this method with an out-of-bounds index or when `self` is not dereferencable
+     /// is *[undefined behavior]* even if the resulting pointer is not used.
+     ///
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_ptr_get)]
+     ///
+     /// let x = &[1, 2, 4] as *const [i32];
+     ///
+     /// unsafe {
+     ///     assert_eq!(x.get_unchecked(1), x.as_ptr().add(1));
+     /// }
+     /// ```
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[inline]
+     pub unsafe fn get_unchecked<I>(self, index: I) -> *const I::Output
+     where
+         I: SliceIndex<[T]>,
+     {
+         // SAFETY: the caller ensures that `self` is dereferencable and `index` in-bounds.
+         unsafe { index.get_unchecked(self) }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a shared slice to
+     /// the value wrapped in `Some`. In contrast to [`as_ref`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// [`as_ref`]: #method.as_ref
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be [valid] for reads for `ptr.len() * mem::size_of::<T>()` many bytes,
+     ///   and it must be properly aligned. This means in particular:
+     ///
+     ///     * The entire memory range of this slice must be contained within a single allocated object!
+     ///       Slices can never span across multiple allocated objects.
+     ///
+     ///     * The pointer must be aligned even for zero-length slices. One
+     ///       reason for this is that enum layout optimizations may rely on references
+     ///       (including slices of any length) being aligned and non-null to distinguish
+     ///       them from other data. You can obtain a pointer that is usable as `data`
+     ///       for zero-length slices using [`NonNull::dangling()`].
+     ///
+     /// * The total size `ptr.len() * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+     ///   See the safety documentation of [`pointer::offset`].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// See also [`slice::from_raw_parts`][].
+     ///
+     /// [valid]: crate::ptr#safety
+     /// [`NonNull::dangling()`]: NonNull::dangling
+     /// [`pointer::offset`]: ../std/primitive.pointer.html#method.offset
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_slice<'a>(self) -> Option<&'a [MaybeUninit<T>]> {
+         if self.is_null() {
+             None
+         } else {
+             // SAFETY: the caller must uphold the safety contract for `as_uninit_slice`.
+             Some(unsafe { slice::from_raw_parts(self as *const MaybeUninit<T>, self.len()) })
+         }
+     }
+ }
+ 
+ // Equality for pointers
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> PartialEq for *const T {
+     #[inline]
+     fn eq(&self, other: &*const T) -> bool {
+         *self == *other
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Eq for *const T {}
+ 
+ // Comparison for pointers
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Ord for *const T {
+     #[inline]
+     fn cmp(&self, other: &*const T) -> Ordering {
+         if self < other {
+             Less
+         } else if self == other {
+             Equal
+         } else {
+             Greater
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> PartialOrd for *const T {
+     #[inline]
+     fn partial_cmp(&self, other: &*const T) -> Option<Ordering> {
+         Some(self.cmp(other))
+     }
+ 
+     #[inline]
+     fn lt(&self, other: &*const T) -> bool {
+         *self < *other
+     }
+ 
+     #[inline]
+     fn le(&self, other: &*const T) -> bool {
+         *self <= *other
+     }
+ 
+     #[inline]
+     fn gt(&self, other: &*const T) -> bool {
+         *self > *other
+     }
+ 
+     #[inline]
+     fn ge(&self, other: &*const T) -> bool {
+         *self >= *other
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1547 ----
+ //! Manually manage memory through raw pointers.
+ //!
+ //! *[See also the pointer primitive types](../../std/primitive.pointer.html).*
+ //!
+ //! # Safety
+ //!
+ //! Many functions in this module take raw pointers as arguments and read from
+ //! or write to them. For this to be safe, these pointers must be *valid*.
+ //! Whether a pointer is valid depends on the operation it is used for
+ //! (read or write), and the extent of the memory that is accessed (i.e.,
+ //! how many bytes are read/written). Most functions use `*mut T` and `*const T`
+ //! to access only a single value, in which case the documentation omits the size
+ //! and implicitly assumes it to be `size_of::<T>()` bytes.
+ //!
+ //! The precise rules for validity are not determined yet. The guarantees that are
+ //! provided at this point are very minimal:
+ //!
+ //! * A [null] pointer is *never* valid, not even for accesses of [size zero][zst].
+ //! * All pointers (except for the null pointer) are valid for all operations of
+ //!   [size zero][zst].
+ //! * For a pointer to be valid, it is necessary, but not always sufficient, that the pointer
+ //!   be *dereferenceable*: the memory range of the given size starting at the pointer must all be
+ //!   within the bounds of a single allocated object. Note that in Rust,
+ //!   every (stack-allocated) variable is considered a separate allocated object.
+ //! * All accesses performed by functions in this module are *non-atomic* in the sense
+ //!   of [atomic operations] used to synchronize between threads. This means it is
+ //!   undefined behavior to perform two concurrent accesses to the same location from different
+ //!   threads unless both accesses only read from memory. Notice that this explicitly
+ //!   includes [`read_volatile`] and [`write_volatile`]: Volatile accesses cannot
+ //!   be used for inter-thread synchronization.
+ //! * The result of casting a reference to a pointer is valid for as long as the
+ //!   underlying object is live and no reference (just raw pointers) is used to
+ //!   access the same memory.
+ //!
+ //! These axioms, along with careful use of [`offset`] for pointer arithmetic,
+ //! are enough to correctly implement many useful things in unsafe code. Stronger guarantees
+ //! will be provided eventually, as the [aliasing] rules are being determined. For more
+ //! information, see the [book] as well as the section in the reference devoted
+ //! to [undefined behavior][ub].
+ //!
+ //! ## Alignment
+ //!
+ //! Valid raw pointers as defined above are not necessarily properly aligned (where
+ //! "proper" alignment is defined by the pointee type, i.e., `*const T` must be
+ //! aligned to `mem::align_of::<T>()`). However, most functions require their
+ //! arguments to be properly aligned, and will explicitly state
+ //! this requirement in their documentation. Notable exceptions to this are
+ //! [`read_unaligned`] and [`write_unaligned`].
+ //!
+ //! When a function requires proper alignment, it does so even if the access
+ //! has size 0, i.e., even if memory is not actually touched. Consider using
+ //! [`NonNull::dangling`] in such cases.
+ //!
+ //! [aliasing]: ../../nomicon/aliasing.html
+ //! [book]: ../../book/ch19-01-unsafe-rust.html#dereferencing-a-raw-pointer
+ //! [ub]: ../../reference/behavior-considered-undefined.html
+ //! [zst]: ../../nomicon/exotic-sizes.html#zero-sized-types-zsts
+ //! [atomic operations]: crate::sync::atomic
+ //! [`offset`]: ../../std/primitive.pointer.html#method.offset
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::cmp::Ordering;
+ use crate::fmt;
+ use crate::hash;
+ use crate::intrinsics::{self, abort, is_aligned_and_not_null, is_nonoverlapping};
+ use crate::mem::{self, MaybeUninit};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(inline)]
+ pub use crate::intrinsics::copy_nonoverlapping;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(inline)]
+ pub use crate::intrinsics::copy;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[doc(inline)]
+ pub use crate::intrinsics::write_bytes;
+ 
+ mod non_null;
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ pub use non_null::NonNull;
+ 
+ mod unique;
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ pub use unique::Unique;
+ 
+ mod const_ptr;
+ mod mut_ptr;
+ 
+ /// Executes the destructor (if any) of the pointed-to value.
+ ///
+ /// This is semantically equivalent to calling [`ptr::read`] and discarding
+ /// the result, but has the following advantages:
+ ///
+ /// * It is *required* to use `drop_in_place` to drop unsized types like
+ ///   trait objects, because they can't be read out onto the stack and
+ ///   dropped normally.
+ ///
+ /// * It is friendlier to the optimizer to do this over [`ptr::read`] when
+ ///   dropping manually allocated memory (e.g., in the implementations of
+ ///   `Box`/`Rc`/`Vec`), as the compiler doesn't need to prove that it's
+ ///   sound to elide the copy.
+ ///
+ /// * It can be used to drop [pinned] data when `T` is not `repr(packed)`
+ ///   (pinned data must not be moved before it is dropped).
+ ///
+ /// Unaligned values cannot be dropped in place, they must be copied to an aligned
+ /// location first using [`ptr::read_unaligned`]. For packed structs, this move is
+ /// done automatically by the compiler. This means the fields of packed structs
+ /// are not dropped in-place.
+ ///
+ /// [`ptr::read`]: self::read
+ /// [`ptr::read_unaligned`]: self::read_unaligned
+ /// [pinned]: crate::pin
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `to_drop` must be [valid] for both reads and writes.
+ ///
+ /// * `to_drop` must be properly aligned.
+ ///
+ /// * The value `to_drop` points to must be valid for dropping, which may mean it must uphold
+ ///   additional invariants - this is type-dependent.
+ ///
+ /// Additionally, if `T` is not [`Copy`], using the pointed-to value after
+ /// calling `drop_in_place` can cause undefined behavior. Note that `*to_drop =
+ /// foo` counts as a use because it will cause the value to be dropped
+ /// again. [`write()`] can be used to overwrite data without causing it to be
+ /// dropped.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// # Examples
+ ///
+ /// Manually remove the last item from a vector:
+ ///
+ /// ```
+ /// use std::ptr;
+ /// use std::rc::Rc;
+ ///
+ /// let last = Rc::new(1);
+ /// let weak = Rc::downgrade(&last);
+ ///
+ /// let mut v = vec![Rc::new(0), last];
+ ///
+ /// unsafe {
+ ///     // Get a raw pointer to the last element in `v`.
+ ///     let ptr = &mut v[1] as *mut _;
+ ///     // Shorten `v` to prevent the last item from being dropped. We do that first,
+ ///     // to prevent issues if the `drop_in_place` below panics.
+ ///     v.set_len(1);
+ ///     // Without a call `drop_in_place`, the last item would never be dropped,
+ ///     // and the memory it manages would be leaked.
+ ///     ptr::drop_in_place(ptr);
+ /// }
+ ///
+ /// assert_eq!(v, &[0.into()]);
+ ///
+ /// // Ensure that the last item was dropped.
+ /// assert!(weak.upgrade().is_none());
+ /// ```
+ ///
+ /// Notice that the compiler performs this copy automatically when dropping packed structs,
+ /// i.e., you do not usually have to worry about such issues unless you call `drop_in_place`
+ /// manually.
+ #[stable(feature = "drop_in_place", since = "1.8.0")]
+ #[lang = "drop_in_place"]
+ #[allow(unconditional_recursion)]
+ pub unsafe fn drop_in_place<T: ?Sized>(to_drop: *mut T) {
+     // Code here does not matter - this is replaced by the
+     // real drop glue by the compiler.
+ 
+     // SAFETY: see comment above
+     unsafe { drop_in_place(to_drop) }
+ }
+ 
+ /// Creates a null raw pointer.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let p: *const i32 = ptr::null();
+ /// assert!(p.is_null());
+ /// ```
+ #[inline(always)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_promotable]
+ #[rustc_const_stable(feature = "const_ptr_null", since = "1.32.0")]
+ pub const fn null<T>() -> *const T {
+     0 as *const T
+ }
+ 
+ /// Creates a null mutable raw pointer.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let p: *mut i32 = ptr::null_mut();
+ /// assert!(p.is_null());
+ /// ```
+ #[inline(always)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_promotable]
+ #[rustc_const_stable(feature = "const_ptr_null", since = "1.32.0")]
+ pub const fn null_mut<T>() -> *mut T {
+     0 as *mut T
+ }
+ 
+ #[repr(C)]
+ pub(crate) union Repr<T> {
+     pub(crate) rust: *const [T],
+     rust_mut: *mut [T],
+     pub(crate) raw: FatPtr<T>,
+ }
+ 
+ #[repr(C)]
+ pub(crate) struct FatPtr<T> {
+     data: *const T,
+     pub(crate) len: usize,
+ }
+ 
+ // Manual impl needed to avoid `T: Clone` bound.
+ impl<T> Clone for FatPtr<T> {
+     fn clone(&self) -> Self {
+         *self
+     }
+ }
+ 
+ // Manual impl needed to avoid `T: Copy` bound.
+ impl<T> Copy for FatPtr<T> {}
+ 
+ /// Forms a raw slice from a pointer and a length.
+ ///
+ /// The `len` argument is the number of **elements**, not the number of bytes.
+ ///
+ /// This function is safe, but actually using the return value is unsafe.
+ /// See the documentation of [`slice::from_raw_parts`] for slice safety requirements.
+ ///
+ /// [`slice::from_raw_parts`]: crate::slice::from_raw_parts
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// use std::ptr;
+ ///
+ /// // create a slice pointer when starting out with a pointer to the first element
+ /// let x = [5, 6, 7];
+ /// let raw_pointer = x.as_ptr();
+ /// let slice = ptr::slice_from_raw_parts(raw_pointer, 3);
+ /// assert_eq!(unsafe { &*slice }[2], 7);
+ /// ```
+ #[inline]
+ #[stable(feature = "slice_from_raw_parts", since = "1.42.0")]
+ #[rustc_const_unstable(feature = "const_slice_from_raw_parts", issue = "67456")]
+ pub const fn slice_from_raw_parts<T>(data: *const T, len: usize) -> *const [T] {
+     // SAFETY: Accessing the value from the `Repr` union is safe since *const [T]
+     // and FatPtr have the same memory layouts. Only std can make this
+     // guarantee.
+     unsafe { Repr { raw: FatPtr { data, len } }.rust }
+ }
+ 
+ /// Performs the same functionality as [`slice_from_raw_parts`], except that a
+ /// raw mutable slice is returned, as opposed to a raw immutable slice.
+ ///
+ /// See the documentation of [`slice_from_raw_parts`] for more details.
+ ///
+ /// This function is safe, but actually using the return value is unsafe.
+ /// See the documentation of [`slice::from_raw_parts_mut`] for slice safety requirements.
+ ///
+ /// [`slice::from_raw_parts_mut`]: crate::slice::from_raw_parts_mut
+ ///
+ /// # Examples
+ ///
+ /// ```rust
+ /// use std::ptr;
+ ///
+ /// let x = &mut [5, 6, 7];
+ /// let raw_pointer = x.as_mut_ptr();
+ /// let slice = ptr::slice_from_raw_parts_mut(raw_pointer, 3);
+ ///
+ /// unsafe {
+ ///     (*slice)[2] = 99; // assign a value at an index in the slice
+ /// };
+ ///
+ /// assert_eq!(unsafe { &*slice }[2], 99);
+ /// ```
+ #[inline]
+ #[stable(feature = "slice_from_raw_parts", since = "1.42.0")]
+ #[rustc_const_unstable(feature = "const_slice_from_raw_parts", issue = "67456")]
+ pub const fn slice_from_raw_parts_mut<T>(data: *mut T, len: usize) -> *mut [T] {
+     // SAFETY: Accessing the value from the `Repr` union is safe since *mut [T]
+     // and FatPtr have the same memory layouts
+     unsafe { Repr { raw: FatPtr { data, len } }.rust_mut }
+ }
+ 
+ /// Swaps the values at two mutable locations of the same type, without
+ /// deinitializing either.
+ ///
+ /// But for the following two exceptions, this function is semantically
+ /// equivalent to [`mem::swap`]:
+ ///
+ /// * It operates on raw pointers instead of references. When references are
+ ///   available, [`mem::swap`] should be preferred.
+ ///
+ /// * The two pointed-to values may overlap. If the values do overlap, then the
+ ///   overlapping region of memory from `x` will be used. This is demonstrated
+ ///   in the second example below.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * Both `x` and `y` must be [valid] for both reads and writes.
+ ///
+ /// * Both `x` and `y` must be properly aligned.
+ ///
+ /// Note that even if `T` has size `0`, the pointers must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// # Examples
+ ///
+ /// Swapping two non-overlapping regions:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut array = [0, 1, 2, 3];
+ ///
+ /// let x = array[0..].as_mut_ptr() as *mut [u32; 2]; // this is `array[0..2]`
+ /// let y = array[2..].as_mut_ptr() as *mut [u32; 2]; // this is `array[2..4]`
+ ///
+ /// unsafe {
+ ///     ptr::swap(x, y);
+ ///     assert_eq!([2, 3, 0, 1], array);
+ /// }
+ /// ```
+ ///
+ /// Swapping two overlapping regions:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut array = [0, 1, 2, 3];
+ ///
+ /// let x = array[0..].as_mut_ptr() as *mut [u32; 3]; // this is `array[0..3]`
+ /// let y = array[1..].as_mut_ptr() as *mut [u32; 3]; // this is `array[1..4]`
+ ///
+ /// unsafe {
+ ///     ptr::swap(x, y);
+ ///     // The indices `1..3` of the slice overlap between `x` and `y`.
+ ///     // Reasonable results would be for to them be `[2, 3]`, so that indices `0..3` are
+ ///     // `[1, 2, 3]` (matching `y` before the `swap`); or for them to be `[0, 1]`
+ ///     // so that indices `1..4` are `[0, 1, 2]` (matching `x` before the `swap`).
+ ///     // This implementation is defined to make the latter choice.
+ ///     assert_eq!([1, 0, 1, 2], array);
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn swap<T>(x: *mut T, y: *mut T) {
+     // Give ourselves some scratch space to work with.
+     // We do not have to worry about drops: `MaybeUninit` does nothing when dropped.
+     let mut tmp = MaybeUninit::<T>::uninit();
+ 
+     // Perform the swap
+     // SAFETY: the caller must guarantee that `x` and `y` are
+     // valid for writes and properly aligned. `tmp` cannot be
+     // overlapping either `x` or `y` because `tmp` was just allocated
+     // on the stack as a separate allocated object.
+     unsafe {
+         copy_nonoverlapping(x, tmp.as_mut_ptr(), 1);
+         copy(y, x, 1); // `x` and `y` may overlap
+         copy_nonoverlapping(tmp.as_ptr(), y, 1);
+     }
+ }
+ 
+ /// Swaps `count * size_of::<T>()` bytes between the two regions of memory
+ /// beginning at `x` and `y`. The two regions must *not* overlap.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * Both `x` and `y` must be [valid] for both reads and writes of `count *
+ ///   size_of::<T>()` bytes.
+ ///
+ /// * Both `x` and `y` must be properly aligned.
+ ///
+ /// * The region of memory beginning at `x` with a size of `count *
+ ///   size_of::<T>()` bytes must *not* overlap with the region of memory
+ ///   beginning at `y` with the same size.
+ ///
+ /// Note that even if the effectively copied size (`count * size_of::<T>()`) is `0`,
+ /// the pointers must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut x = [1, 2, 3, 4];
+ /// let mut y = [7, 8, 9];
+ ///
+ /// unsafe {
+ ///     ptr::swap_nonoverlapping(x.as_mut_ptr(), y.as_mut_ptr(), 2);
+ /// }
+ ///
+ /// assert_eq!(x, [7, 8, 3, 4]);
+ /// assert_eq!(y, [1, 2, 9]);
+ /// ```
+ #[inline]
+ #[stable(feature = "swap_nonoverlapping", since = "1.27.0")]
+ pub unsafe fn swap_nonoverlapping<T>(x: *mut T, y: *mut T, count: usize) {
+     if cfg!(debug_assertions)
+         && !(is_aligned_and_not_null(x)
+             && is_aligned_and_not_null(y)
+             && is_nonoverlapping(x, y, count))
+     {
+         // Not panicking to keep codegen impact smaller.
+         abort();
+     }
+ 
+     let x = x as *mut u8;
+     let y = y as *mut u8;
+     let len = mem::size_of::<T>() * count;
+     // SAFETY: the caller must guarantee that `x` and `y` are
+     // valid for writes and properly aligned.
+     unsafe { swap_nonoverlapping_bytes(x, y, len) }
+ }
+ 
+ #[inline]
+ pub(crate) unsafe fn swap_nonoverlapping_one<T>(x: *mut T, y: *mut T) {
+     // For types smaller than the block optimization below,
+     // just swap directly to avoid pessimizing codegen.
+     if mem::size_of::<T>() < 32 {
+         // SAFETY: the caller must guarantee that `x` and `y` are valid
+         // for writes, properly aligned, and non-overlapping.
+         unsafe {
+             let z = read(x);
+             copy_nonoverlapping(y, x, 1);
+             write(y, z);
+         }
+     } else {
+         // SAFETY: the caller must uphold the safety contract for `swap_nonoverlapping`.
+         unsafe { swap_nonoverlapping(x, y, 1) };
+     }
+ }
+ 
+ #[inline]
+ unsafe fn swap_nonoverlapping_bytes(x: *mut u8, y: *mut u8, len: usize) {
+     // The approach here is to utilize simd to swap x & y efficiently. Testing reveals
+     // that swapping either 32 bytes or 64 bytes at a time is most efficient for Intel
+     // Haswell E processors. LLVM is more able to optimize if we give a struct a
+     // #[repr(simd)], even if we don't actually use this struct directly.
+     //
+     // FIXME repr(simd) broken on emscripten and redox
+     #[cfg_attr(not(any(target_os = "emscripten", target_os = "redox")), repr(simd))]
+     struct Block(u64, u64, u64, u64);
+     struct UnalignedBlock(u64, u64, u64, u64);
+ 
+     let block_size = mem::size_of::<Block>();
+ 
+     // Loop through x & y, copying them `Block` at a time
+     // The optimizer should unroll the loop fully for most types
+     // N.B. We can't use a for loop as the `range` impl calls `mem::swap` recursively
+     let mut i = 0;
+     while i + block_size <= len {
+         // Create some uninitialized memory as scratch space
+         // Declaring `t` here avoids aligning the stack when this loop is unused
+         let mut t = mem::MaybeUninit::<Block>::uninit();
+         let t = t.as_mut_ptr() as *mut u8;
+ 
+         // SAFETY: As `i < len`, and as the caller must guarantee that `x` and `y` are valid
+         // for `len` bytes, `x + i` and `y + i` must be valid adresses, which fulfills the
+         // safety contract for `add`.
+         //
+         // Also, the caller must guarantee that `x` and `y` are valid for writes, properly aligned,
+         // and non-overlapping, which fulfills the safety contract for `copy_nonoverlapping`.
+         unsafe {
+             let x = x.add(i);
+             let y = y.add(i);
+ 
+             // Swap a block of bytes of x & y, using t as a temporary buffer
+             // This should be optimized into efficient SIMD operations where available
+             copy_nonoverlapping(x, t, block_size);
+             copy_nonoverlapping(y, x, block_size);
+             copy_nonoverlapping(t, y, block_size);
+         }
+         i += block_size;
+     }
+ 
+     if i < len {
+         // Swap any remaining bytes
+         let mut t = mem::MaybeUninit::<UnalignedBlock>::uninit();
+         let rem = len - i;
+ 
+         let t = t.as_mut_ptr() as *mut u8;
+ 
+         // SAFETY: see previous safety comment.
+         unsafe {
+             let x = x.add(i);
+             let y = y.add(i);
+ 
+             copy_nonoverlapping(x, t, rem);
+             copy_nonoverlapping(y, x, rem);
+             copy_nonoverlapping(t, y, rem);
+         }
+     }
+ }
+ 
+ /// Moves `src` into the pointed `dst`, returning the previous `dst` value.
+ ///
+ /// Neither value is dropped.
+ ///
+ /// This function is semantically equivalent to [`mem::replace`] except that it
+ /// operates on raw pointers instead of references. When references are
+ /// available, [`mem::replace`] should be preferred.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `dst` must be [valid] for both reads and writes.
+ ///
+ /// * `dst` must be properly aligned.
+ ///
+ /// * `dst` must point to a properly initialized value of type `T`.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut rust = vec!['b', 'u', 's', 't'];
+ ///
+ /// // `mem::replace` would have the same effect without requiring the unsafe
+ /// // block.
+ /// let b = unsafe {
+ ///     ptr::replace(&mut rust[0], 'r')
+ /// };
+ ///
+ /// assert_eq!(b, 'b');
+ /// assert_eq!(rust, &['r', 'u', 's', 't']);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn replace<T>(dst: *mut T, mut src: T) -> T {
+     // SAFETY: the caller must guarantee that `dst` is valid to be
+     // cast to a mutable reference (valid for writes, aligned, initialized),
+     // and cannot overlap `src` since `dst` must point to a distinct
+     // allocated object.
+     unsafe {
+         mem::swap(&mut *dst, &mut src); // cannot overlap
+     }
+     src
+ }
+ 
+ /// Reads the value from `src` without moving it. This leaves the
+ /// memory in `src` unchanged.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `src` must be [valid] for reads.
+ ///
+ /// * `src` must be properly aligned. Use [`read_unaligned`] if this is not the
+ ///   case.
+ ///
+ /// * `src` must point to a properly initialized value of type `T`.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let x = 12;
+ /// let y = &x as *const i32;
+ ///
+ /// unsafe {
+ ///     assert_eq!(std::ptr::read(y), 12);
+ /// }
+ /// ```
+ ///
+ /// Manually implement [`mem::swap`]:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// fn swap<T>(a: &mut T, b: &mut T) {
+ ///     unsafe {
+ ///         // Create a bitwise copy of the value at `a` in `tmp`.
+ ///         let tmp = ptr::read(a);
+ ///
+ ///         // Exiting at this point (either by explicitly returning or by
+ ///         // calling a function which panics) would cause the value in `tmp` to
+ ///         // be dropped while the same value is still referenced by `a`. This
+ ///         // could trigger undefined behavior if `T` is not `Copy`.
+ ///
+ ///         // Create a bitwise copy of the value at `b` in `a`.
+ ///         // This is safe because mutable references cannot alias.
+ ///         ptr::copy_nonoverlapping(b, a, 1);
+ ///
+ ///         // As above, exiting here could trigger undefined behavior because
+ ///         // the same value is referenced by `a` and `b`.
+ ///
+ ///         // Move `tmp` into `b`.
+ ///         ptr::write(b, tmp);
+ ///
+ ///         // `tmp` has been moved (`write` takes ownership of its second argument),
+ ///         // so nothing is dropped implicitly here.
+ ///     }
+ /// }
+ ///
+ /// let mut foo = "foo".to_owned();
+ /// let mut bar = "bar".to_owned();
+ ///
+ /// swap(&mut foo, &mut bar);
+ ///
+ /// assert_eq!(foo, "bar");
+ /// assert_eq!(bar, "foo");
+ /// ```
+ ///
+ /// ## Ownership of the Returned Value
+ ///
+ /// `read` creates a bitwise copy of `T`, regardless of whether `T` is [`Copy`].
+ /// If `T` is not [`Copy`], using both the returned value and the value at
+ /// `*src` can violate memory safety. Note that assigning to `*src` counts as a
+ /// use because it will attempt to drop the value at `*src`.
+ ///
+ /// [`write()`] can be used to overwrite data without causing it to be dropped.
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let mut s = String::from("foo");
+ /// unsafe {
+ ///     // `s2` now points to the same underlying memory as `s`.
+ ///     let mut s2: String = ptr::read(&s);
+ ///
+ ///     assert_eq!(s2, "foo");
+ ///
+ ///     // Assigning to `s2` causes its original value to be dropped. Beyond
+ ///     // this point, `s` must no longer be used, as the underlying memory has
+ ///     // been freed.
+ ///     s2 = String::default();
+ ///     assert_eq!(s2, "");
+ ///
+ ///     // Assigning to `s` would cause the old value to be dropped again,
+ ///     // resulting in undefined behavior.
+ ///     // s = String::from("bar"); // ERROR
+ ///
+ ///     // `ptr::write` can be used to overwrite a value without dropping it.
+ ///     ptr::write(&mut s, String::from("bar"));
+ /// }
+ ///
+ /// assert_eq!(s, "bar");
+ /// ```
+ ///
+ /// [valid]: self#safety
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn read<T>(src: *const T) -> T {
+     // `copy_nonoverlapping` takes care of debug_assert.
+     let mut tmp = MaybeUninit::<T>::uninit();
+     // SAFETY: the caller must guarantee that `src` is valid for reads.
+     // `src` cannot overlap `tmp` because `tmp` was just allocated on
+     // the stack as a separate allocated object.
+     //
+     // Also, since we just wrote a valid value into `tmp`, it is guaranteed
+     // to be properly initialized.
+     unsafe {
+         copy_nonoverlapping(src, tmp.as_mut_ptr(), 1);
+         tmp.assume_init()
+     }
+ }
+ 
+ /// Reads the value from `src` without moving it. This leaves the
+ /// memory in `src` unchanged.
+ ///
+ /// Unlike [`read`], `read_unaligned` works with unaligned pointers.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `src` must be [valid] for reads.
+ ///
+ /// * `src` must point to a properly initialized value of type `T`.
+ ///
+ /// Like [`read`], `read_unaligned` creates a bitwise copy of `T`, regardless of
+ /// whether `T` is [`Copy`]. If `T` is not [`Copy`], using both the returned
+ /// value and the value at `*src` can [violate memory safety][read-ownership].
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL.
+ ///
+ /// [read-ownership]: read#ownership-of-the-returned-value
+ /// [valid]: self#safety
+ ///
+ /// ## On `packed` structs
+ ///
+ /// It is currently impossible to create raw pointers to unaligned fields
+ /// of a packed struct.
+ ///
+ /// Attempting to create a raw pointer to an `unaligned` struct field with
+ /// an expression such as `&packed.unaligned as *const FieldType` creates an
+ /// intermediate unaligned reference before converting that to a raw pointer.
+ /// That this reference is temporary and immediately cast is inconsequential
+ /// as the compiler always expects references to be properly aligned.
+ /// As a result, using `&packed.unaligned as *const FieldType` causes immediate
+ /// *undefined behavior* in your program.
+ ///
+ /// An example of what not to do and how this relates to `read_unaligned` is:
+ ///
+ /// ```no_run
+ /// #[repr(packed, C)]
+ /// struct Packed {
+ ///     _padding: u8,
+ ///     unaligned: u32,
+ /// }
+ ///
+ /// let packed = Packed {
+ ///     _padding: 0x00,
+ ///     unaligned: 0x01020304,
+ /// };
+ ///
+ /// let v = unsafe {
+ ///     // Here we attempt to take the address of a 32-bit integer which is not aligned.
+ ///     let unaligned =
+ ///         // A temporary unaligned reference is created here which results in
+ ///         // undefined behavior regardless of whether the reference is used or not.
+ ///         &packed.unaligned
+ ///         // Casting to a raw pointer doesn't help; the mistake already happened.
+ ///         as *const u32;
+ ///
+ ///     let v = std::ptr::read_unaligned(unaligned);
+ ///
+ ///     v
+ /// };
+ /// ```
+ ///
+ /// Accessing unaligned fields directly with e.g. `packed.unaligned` is safe however.
+ // FIXME: Update docs based on outcome of RFC #2582 and friends.
+ ///
+ /// # Examples
+ ///
+ /// Read an usize value from a byte buffer:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// fn read_usize(x: &[u8]) -> usize {
+ ///     assert!(x.len() >= mem::size_of::<usize>());
+ ///
+ ///     let ptr = x.as_ptr() as *const usize;
+ ///
+ ///     unsafe { ptr.read_unaligned() }
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "ptr_unaligned", since = "1.17.0")]
+ pub unsafe fn read_unaligned<T>(src: *const T) -> T {
+     // `copy_nonoverlapping` takes care of debug_assert.
+     let mut tmp = MaybeUninit::<T>::uninit();
+     // SAFETY: the caller must guarantee that `src` is valid for reads.
+     // `src` cannot overlap `tmp` because `tmp` was just allocated on
+     // the stack as a separate allocated object.
+     //
+     // Also, since we just wrote a valid value into `tmp`, it is guaranteed
+     // to be properly initialized.
+     unsafe {
+         copy_nonoverlapping(src as *const u8, tmp.as_mut_ptr() as *mut u8, mem::size_of::<T>());
+         tmp.assume_init()
+     }
+ }
+ 
+ /// Overwrites a memory location with the given value without reading or
+ /// dropping the old value.
+ ///
+ /// `write` does not drop the contents of `dst`. This is safe, but it could leak
+ /// allocations or resources, so care should be taken not to overwrite an object
+ /// that should be dropped.
+ ///
+ /// Additionally, it does not drop `src`. Semantically, `src` is moved into the
+ /// location pointed to by `dst`.
+ ///
+ /// This is appropriate for initializing uninitialized memory, or overwriting
+ /// memory that has previously been [`read`] from.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `dst` must be [valid] for writes.
+ ///
+ /// * `dst` must be properly aligned. Use [`write_unaligned`] if this is not the
+ ///   case.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let mut x = 0;
+ /// let y = &mut x as *mut i32;
+ /// let z = 12;
+ ///
+ /// unsafe {
+ ///     std::ptr::write(y, z);
+ ///     assert_eq!(std::ptr::read(y), 12);
+ /// }
+ /// ```
+ ///
+ /// Manually implement [`mem::swap`]:
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// fn swap<T>(a: &mut T, b: &mut T) {
+ ///     unsafe {
+ ///         // Create a bitwise copy of the value at `a` in `tmp`.
+ ///         let tmp = ptr::read(a);
+ ///
+ ///         // Exiting at this point (either by explicitly returning or by
+ ///         // calling a function which panics) would cause the value in `tmp` to
+ ///         // be dropped while the same value is still referenced by `a`. This
+ ///         // could trigger undefined behavior if `T` is not `Copy`.
+ ///
+ ///         // Create a bitwise copy of the value at `b` in `a`.
+ ///         // This is safe because mutable references cannot alias.
+ ///         ptr::copy_nonoverlapping(b, a, 1);
+ ///
+ ///         // As above, exiting here could trigger undefined behavior because
+ ///         // the same value is referenced by `a` and `b`.
+ ///
+ ///         // Move `tmp` into `b`.
+ ///         ptr::write(b, tmp);
+ ///
+ ///         // `tmp` has been moved (`write` takes ownership of its second argument),
+ ///         // so nothing is dropped implicitly here.
+ ///     }
+ /// }
+ ///
+ /// let mut foo = "foo".to_owned();
+ /// let mut bar = "bar".to_owned();
+ ///
+ /// swap(&mut foo, &mut bar);
+ ///
+ /// assert_eq!(foo, "bar");
+ /// assert_eq!(bar, "foo");
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn write<T>(dst: *mut T, src: T) {
+     if cfg!(debug_assertions) && !is_aligned_and_not_null(dst) {
+         // Not panicking to keep codegen impact smaller.
+         abort();
+     }
+     // SAFETY: the caller must uphold the safety contract for `move_val_init`.
+     unsafe { intrinsics::move_val_init(&mut *dst, src) }
+ }
+ 
+ /// Overwrites a memory location with the given value without reading or
+ /// dropping the old value.
+ ///
+ /// Unlike [`write()`], the pointer may be unaligned.
+ ///
+ /// `write_unaligned` does not drop the contents of `dst`. This is safe, but it
+ /// could leak allocations or resources, so care should be taken not to overwrite
+ /// an object that should be dropped.
+ ///
+ /// Additionally, it does not drop `src`. Semantically, `src` is moved into the
+ /// location pointed to by `dst`.
+ ///
+ /// This is appropriate for initializing uninitialized memory, or overwriting
+ /// memory that has previously been read with [`read_unaligned`].
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `dst` must be [valid] for writes.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// ## On `packed` structs
+ ///
+ /// It is currently impossible to create raw pointers to unaligned fields
+ /// of a packed struct.
+ ///
+ /// Attempting to create a raw pointer to an `unaligned` struct field with
+ /// an expression such as `&packed.unaligned as *const FieldType` creates an
+ /// intermediate unaligned reference before converting that to a raw pointer.
+ /// That this reference is temporary and immediately cast is inconsequential
+ /// as the compiler always expects references to be properly aligned.
+ /// As a result, using `&packed.unaligned as *const FieldType` causes immediate
+ /// *undefined behavior* in your program.
+ ///
+ /// An example of what not to do and how this relates to `write_unaligned` is:
+ ///
+ /// ```no_run
+ /// #[repr(packed, C)]
+ /// struct Packed {
+ ///     _padding: u8,
+ ///     unaligned: u32,
+ /// }
+ ///
+ /// let v = 0x01020304;
+ /// let mut packed: Packed = unsafe { std::mem::zeroed() };
+ ///
+ /// let v = unsafe {
+ ///     // Here we attempt to take the address of a 32-bit integer which is not aligned.
+ ///     let unaligned =
+ ///         // A temporary unaligned reference is created here which results in
+ ///         // undefined behavior regardless of whether the reference is used or not.
+ ///         &mut packed.unaligned
+ ///         // Casting to a raw pointer doesn't help; the mistake already happened.
+ ///         as *mut u32;
+ ///
+ ///     std::ptr::write_unaligned(unaligned, v);
+ ///
+ ///     v
+ /// };
+ /// ```
+ ///
+ /// Accessing unaligned fields directly with e.g. `packed.unaligned` is safe however.
+ // FIXME: Update docs based on outcome of RFC #2582 and friends.
+ ///
+ /// # Examples
+ ///
+ /// Write an usize value to a byte buffer:
+ ///
+ /// ```
+ /// use std::mem;
+ ///
+ /// fn write_usize(x: &mut [u8], val: usize) {
+ ///     assert!(x.len() >= mem::size_of::<usize>());
+ ///
+ ///     let ptr = x.as_mut_ptr() as *mut usize;
+ ///
+ ///     unsafe { ptr.write_unaligned(val) }
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "ptr_unaligned", since = "1.17.0")]
+ pub unsafe fn write_unaligned<T>(dst: *mut T, src: T) {
+     // SAFETY: the caller must guarantee that `dst` is valid for writes.
+     // `dst` cannot overlap `src` because the caller has mutable access
+     // to `dst` while `src` is owned by this function.
+     unsafe {
+         // `copy_nonoverlapping` takes care of debug_assert.
+         copy_nonoverlapping(&src as *const T as *const u8, dst as *mut u8, mem::size_of::<T>());
+     }
+     mem::forget(src);
+ }
+ 
+ /// Performs a volatile read of the value from `src` without moving it. This
+ /// leaves the memory in `src` unchanged.
+ ///
+ /// Volatile operations are intended to act on I/O memory, and are guaranteed
+ /// to not be elided or reordered by the compiler across other volatile
+ /// operations.
+ ///
+ /// # Notes
+ ///
+ /// Rust does not currently have a rigorously and formally defined memory model,
+ /// so the precise semantics of what "volatile" means here is subject to change
+ /// over time. That being said, the semantics will almost always end up pretty
+ /// similar to [C11's definition of volatile][c11].
+ ///
+ /// The compiler shouldn't change the relative order or number of volatile
+ /// memory operations. However, volatile memory operations on zero-sized types
+ /// (e.g., if a zero-sized type is passed to `read_volatile`) are noops
+ /// and may be ignored.
+ ///
+ /// [c11]: http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1570.pdf
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `src` must be [valid] for reads.
+ ///
+ /// * `src` must be properly aligned.
+ ///
+ /// * `src` must point to a properly initialized value of type `T`.
+ ///
+ /// Like [`read`], `read_volatile` creates a bitwise copy of `T`, regardless of
+ /// whether `T` is [`Copy`]. If `T` is not [`Copy`], using both the returned
+ /// value and the value at `*src` can [violate memory safety][read-ownership].
+ /// However, storing non-[`Copy`] types in volatile memory is almost certainly
+ /// incorrect.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ /// [read-ownership]: read#ownership-of-the-returned-value
+ ///
+ /// Just like in C, whether an operation is volatile has no bearing whatsoever
+ /// on questions involving concurrent access from multiple threads. Volatile
+ /// accesses behave exactly like non-atomic accesses in that regard. In particular,
+ /// a race between a `read_volatile` and any write operation to the same location
+ /// is undefined behavior.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let x = 12;
+ /// let y = &x as *const i32;
+ ///
+ /// unsafe {
+ ///     assert_eq!(std::ptr::read_volatile(y), 12);
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "volatile", since = "1.9.0")]
+ pub unsafe fn read_volatile<T>(src: *const T) -> T {
+     if cfg!(debug_assertions) && !is_aligned_and_not_null(src) {
+         // Not panicking to keep codegen impact smaller.
+         abort();
+     }
+     // SAFETY: the caller must uphold the safety contract for `volatile_load`.
+     unsafe { intrinsics::volatile_load(src) }
+ }
+ 
+ /// Performs a volatile write of a memory location with the given value without
+ /// reading or dropping the old value.
+ ///
+ /// Volatile operations are intended to act on I/O memory, and are guaranteed
+ /// to not be elided or reordered by the compiler across other volatile
+ /// operations.
+ ///
+ /// `write_volatile` does not drop the contents of `dst`. This is safe, but it
+ /// could leak allocations or resources, so care should be taken not to overwrite
+ /// an object that should be dropped.
+ ///
+ /// Additionally, it does not drop `src`. Semantically, `src` is moved into the
+ /// location pointed to by `dst`.
+ ///
+ /// # Notes
+ ///
+ /// Rust does not currently have a rigorously and formally defined memory model,
+ /// so the precise semantics of what "volatile" means here is subject to change
+ /// over time. That being said, the semantics will almost always end up pretty
+ /// similar to [C11's definition of volatile][c11].
+ ///
+ /// The compiler shouldn't change the relative order or number of volatile
+ /// memory operations. However, volatile memory operations on zero-sized types
+ /// (e.g., if a zero-sized type is passed to `write_volatile`) are noops
+ /// and may be ignored.
+ ///
+ /// [c11]: http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1570.pdf
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `dst` must be [valid] for writes.
+ ///
+ /// * `dst` must be properly aligned.
+ ///
+ /// Note that even if `T` has size `0`, the pointer must be non-NULL and properly aligned.
+ ///
+ /// [valid]: self#safety
+ ///
+ /// Just like in C, whether an operation is volatile has no bearing whatsoever
+ /// on questions involving concurrent access from multiple threads. Volatile
+ /// accesses behave exactly like non-atomic accesses in that regard. In particular,
+ /// a race between a `write_volatile` and any other operation (reading or writing)
+ /// on the same location is undefined behavior.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// let mut x = 0;
+ /// let y = &mut x as *mut i32;
+ /// let z = 12;
+ ///
+ /// unsafe {
+ ///     std::ptr::write_volatile(y, z);
+ ///     assert_eq!(std::ptr::read_volatile(y), 12);
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "volatile", since = "1.9.0")]
+ pub unsafe fn write_volatile<T>(dst: *mut T, src: T) {
+     if cfg!(debug_assertions) && !is_aligned_and_not_null(dst) {
+         // Not panicking to keep codegen impact smaller.
+         abort();
+     }
+     // SAFETY: the caller must uphold the safety contract for `volatile_store`.
+     unsafe {
+         intrinsics::volatile_store(dst, src);
+     }
+ }
+ 
+ /// Align pointer `p`.
+ ///
+ /// Calculate offset (in terms of elements of `stride` stride) that has to be applied
+ /// to pointer `p` so that pointer `p` would get aligned to `a`.
+ ///
+ /// Note: This implementation has been carefully tailored to not panic. It is UB for this to panic.
+ /// The only real change that can be made here is change of `INV_TABLE_MOD_16` and associated
+ /// constants.
+ ///
+ /// If we ever decide to make it possible to call the intrinsic with `a` that is not a
+ /// power-of-two, it will probably be more prudent to just change to a naive implementation rather
+ /// than trying to adapt this to accommodate that change.
+ ///
+ /// Any questions go to @nagisa.
+ #[lang = "align_offset"]
+ pub(crate) unsafe fn align_offset<T: Sized>(p: *const T, a: usize) -> usize {
+     // FIXME(#75598): Direct use of these intrinsics improves codegen significantly at opt-level <=
+     // 1, where the method versions of these operations are not inlined.
+     use intrinsics::{
+         unchecked_shl, unchecked_shr, unchecked_sub, wrapping_add, wrapping_mul, wrapping_sub,
+     };
+ 
+     /// Calculate multiplicative modular inverse of `x` modulo `m`.
+     ///
+     /// This implementation is tailored for `align_offset` and has following preconditions:
+     ///
+     /// * `m` is a power-of-two;
+     /// * `x < m`; (if `x ≥ m`, pass in `x % m` instead)
+     ///
+     /// Implementation of this function shall not panic. Ever.
+     #[inline]
+     unsafe fn mod_inv(x: usize, m: usize) -> usize {
+         /// Multiplicative modular inverse table modulo 2⁴ = 16.
+         ///
+         /// Note, that this table does not contain values where inverse does not exist (i.e., for
+         /// `0⁻¹ mod 16`, `2⁻¹ mod 16`, etc.)
+         const INV_TABLE_MOD_16: [u8; 8] = [1, 11, 13, 7, 9, 3, 5, 15];
+         /// Modulo for which the `INV_TABLE_MOD_16` is intended.
+         const INV_TABLE_MOD: usize = 16;
+         /// INV_TABLE_MOD²
+         const INV_TABLE_MOD_SQUARED: usize = INV_TABLE_MOD * INV_TABLE_MOD;
+ 
+         let table_inverse = INV_TABLE_MOD_16[(x & (INV_TABLE_MOD - 1)) >> 1] as usize;
+         // SAFETY: `m` is required to be a power-of-two, hence non-zero.
+         let m_minus_one = unsafe { unchecked_sub(m, 1) };
+         if m <= INV_TABLE_MOD {
+             table_inverse & m_minus_one
+         } else {
+             // We iterate "up" using the following formula:
+             //
+             // $$ xy ≡ 1 (mod 2ⁿ) → xy (2 - xy) ≡ 1 (mod 2²ⁿ) $$
+             //
+             // until 2²ⁿ ≥ m. Then we can reduce to our desired `m` by taking the result `mod m`.
+             let mut inverse = table_inverse;
+             let mut going_mod = INV_TABLE_MOD_SQUARED;
+             loop {
+                 // y = y * (2 - xy) mod n
+                 //
+                 // Note, that we use wrapping operations here intentionally – the original formula
+                 // uses e.g., subtraction `mod n`. It is entirely fine to do them `mod
+                 // usize::MAX` instead, because we take the result `mod n` at the end
+                 // anyway.
+                 inverse = wrapping_mul(inverse, wrapping_sub(2usize, wrapping_mul(x, inverse)));
+                 if going_mod >= m {
+                     return inverse & m_minus_one;
+                 }
+                 going_mod = wrapping_mul(going_mod, going_mod);
+             }
+         }
+     }
+ 
+     let stride = mem::size_of::<T>();
+     // SAFETY: `a` is a power-of-two, therefore non-zero.
+     let a_minus_one = unsafe { unchecked_sub(a, 1) };
+     if stride == 1 {
+         // `stride == 1` case can be computed more simply through `-p (mod a)`, but doing so
+         // inhibits LLVM's ability to select instructions like `lea`. Instead we compute
+         //
+         //    round_up_to_next_alignment(p, a) - p
+         //
+         // which distributes operations around the load-bearing, but pessimizing `and` sufficiently
+         // for LLVM to be able to utilize the various optimizations it knows about.
+         return wrapping_sub(
+             wrapping_add(p as usize, a_minus_one) & wrapping_sub(0, a),
+             p as usize,
+         );
+     }
+ 
+     let pmoda = p as usize & a_minus_one;
+     if pmoda == 0 {
+         // Already aligned. Yay!
+         return 0;
+     } else if stride == 0 {
+         // If the pointer is not aligned, and the element is zero-sized, then no amount of
+         // elements will ever align the pointer.
+         return usize::MAX;
+     }
+ 
+     let smoda = stride & a_minus_one;
+     // SAFETY: a is power-of-two hence non-zero. stride == 0 case is handled above.
+     let gcdpow = unsafe { intrinsics::cttz_nonzero(stride).min(intrinsics::cttz_nonzero(a)) };
+     // SAFETY: gcdpow has an upper-bound that’s at most the number of bits in an usize.
+     let gcd = unsafe { unchecked_shl(1usize, gcdpow) };
+ 
+     // SAFETY: gcd is always greater or equal to 1.
+     if p as usize & unsafe { unchecked_sub(gcd, 1) } == 0 {
+         // This branch solves for the following linear congruence equation:
+         //
+         // ` p + so = 0 mod a `
+         //
+         // `p` here is the pointer value, `s` - stride of `T`, `o` offset in `T`s, and `a` - the
+         // requested alignment.
+         //
+         // With `g = gcd(a, s)`, and the above condition asserting that `p` is also divisible by
+         // `g`, we can denote `a' = a/g`, `s' = s/g`, `p' = p/g`, then this becomes equivalent to:
+         //
+         // ` p' + s'o = 0 mod a' `
+         // ` o = (a' - (p' mod a')) * (s'^-1 mod a') `
+         //
+         // The first term is "the relative alignment of `p` to `a`" (divided by the `g`), the second
+         // term is "how does incrementing `p` by `s` bytes change the relative alignment of `p`" (again
+         // divided by `g`).
+         // Division by `g` is necessary to make the inverse well formed if `a` and `s` are not
+         // co-prime.
+         //
+         // Furthermore, the result produced by this solution is not "minimal", so it is necessary
+         // to take the result `o mod lcm(s, a)`. We can replace `lcm(s, a)` with just a `a'`.
+ 
+         // SAFETY: `gcdpow` has an upper-bound not greater than the number of trailing 0-bits in
+         // `a`.
+         let a2 = unsafe { unchecked_shr(a, gcdpow) };
+         // SAFETY: `a2` is non-zero. Shifting `a` by `gcdpow` cannot shift out any of the set bits
+         // in `a` (of which it has exactly one).
+         let a2minus1 = unsafe { unchecked_sub(a2, 1) };
+         // SAFETY: `gcdpow` has an upper-bound not greater than the number of trailing 0-bits in
+         // `a`.
+         let s2 = unsafe { unchecked_shr(smoda, gcdpow) };
+         // SAFETY: `gcdpow` has an upper-bound not greater than the number of trailing 0-bits in
+         // `a`. Furthermore, the subtraction cannot overflow, because `a2 = a >> gcdpow` will
+         // always be strictly greater than `(p % a) >> gcdpow`.
+         let minusp2 = unsafe { unchecked_sub(a2, unchecked_shr(pmoda, gcdpow)) };
+         // SAFETY: `a2` is a power-of-two, as proven above. `s2` is strictly less than `a2`
+         // because `(s % a) >> gcdpow` is strictly less than `a >> gcdpow`.
+         return wrapping_mul(minusp2, unsafe { mod_inv(s2, a2) }) & a2minus1;
+     }
+ 
+     // Cannot be aligned at all.
+     usize::MAX
+ }
+ 
+ /// Compares raw pointers for equality.
+ ///
+ /// This is the same as using the `==` operator, but less generic:
+ /// the arguments have to be `*const T` raw pointers,
+ /// not anything that implements `PartialEq`.
+ ///
+ /// This can be used to compare `&T` references (which coerce to `*const T` implicitly)
+ /// by their address rather than comparing the values they point to
+ /// (which is what the `PartialEq for &T` implementation does).
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::ptr;
+ ///
+ /// let five = 5;
+ /// let other_five = 5;
+ /// let five_ref = &five;
+ /// let same_five_ref = &five;
+ /// let other_five_ref = &other_five;
+ ///
+ /// assert!(five_ref == same_five_ref);
+ /// assert!(ptr::eq(five_ref, same_five_ref));
+ ///
+ /// assert!(five_ref == other_five_ref);
+ /// assert!(!ptr::eq(five_ref, other_five_ref));
+ /// ```
+ ///
+ /// Slices are also compared by their length (fat pointers):
+ ///
+ /// ```
+ /// let a = [1, 2, 3];
+ /// assert!(std::ptr::eq(&a[..3], &a[..3]));
+ /// assert!(!std::ptr::eq(&a[..2], &a[..3]));
+ /// assert!(!std::ptr::eq(&a[0..2], &a[1..3]));
+ /// ```
+ ///
+ /// Traits are also compared by their implementation:
+ ///
+ /// ```
+ /// #[repr(transparent)]
+ /// struct Wrapper { member: i32 }
+ ///
+ /// trait Trait {}
+ /// impl Trait for Wrapper {}
+ /// impl Trait for i32 {}
+ ///
+ /// let wrapper = Wrapper { member: 10 };
+ ///
+ /// // Pointers have equal addresses.
+ /// assert!(std::ptr::eq(
+ ///     &wrapper as *const Wrapper as *const u8,
+ ///     &wrapper.member as *const i32 as *const u8
+ /// ));
+ ///
+ /// // Objects have equal addresses, but `Trait` has different implementations.
+ /// assert!(!std::ptr::eq(
+ ///     &wrapper as &dyn Trait,
+ ///     &wrapper.member as &dyn Trait,
+ /// ));
+ /// assert!(!std::ptr::eq(
+ ///     &wrapper as &dyn Trait as *const dyn Trait,
+ ///     &wrapper.member as &dyn Trait as *const dyn Trait,
+ /// ));
+ ///
+ /// // Converting the reference to a `*const u8` compares by address.
+ /// assert!(std::ptr::eq(
+ ///     &wrapper as &dyn Trait as *const dyn Trait as *const u8,
+ ///     &wrapper.member as &dyn Trait as *const dyn Trait as *const u8,
+ /// ));
+ /// ```
+ #[stable(feature = "ptr_eq", since = "1.17.0")]
+ #[inline]
+ pub fn eq<T: ?Sized>(a: *const T, b: *const T) -> bool {
+     a == b
+ }
+ 
+ /// Hash a raw pointer.
+ ///
+ /// This can be used to hash a `&T` reference (which coerces to `*const T` implicitly)
+ /// by its address rather than the value it points to
+ /// (which is what the `Hash for &T` implementation does).
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::collections::hash_map::DefaultHasher;
+ /// use std::hash::{Hash, Hasher};
+ /// use std::ptr;
+ ///
+ /// let five = 5;
+ /// let five_ref = &five;
+ ///
+ /// let mut hasher = DefaultHasher::new();
+ /// ptr::hash(five_ref, &mut hasher);
+ /// let actual = hasher.finish();
+ ///
+ /// let mut hasher = DefaultHasher::new();
+ /// (five_ref as *const i32).hash(&mut hasher);
+ /// let expected = hasher.finish();
+ ///
+ /// assert_eq!(actual, expected);
+ /// ```
+ #[stable(feature = "ptr_hash", since = "1.35.0")]
+ pub fn hash<T: ?Sized, S: hash::Hasher>(hashee: *const T, into: &mut S) {
+     use crate::hash::Hash;
+     hashee.hash(into);
+ }
+ 
+ // Impls for function pointers
+ macro_rules! fnptr_impls_safety_abi {
+     ($FnTy: ty, $($Arg: ident),*) => {
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> PartialEq for $FnTy {
+             #[inline]
+             fn eq(&self, other: &Self) -> bool {
+                 *self as usize == *other as usize
+             }
+         }
+ 
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> Eq for $FnTy {}
+ 
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> PartialOrd for $FnTy {
+             #[inline]
+             fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+                 (*self as usize).partial_cmp(&(*other as usize))
+             }
+         }
+ 
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> Ord for $FnTy {
+             #[inline]
+             fn cmp(&self, other: &Self) -> Ordering {
+                 (*self as usize).cmp(&(*other as usize))
+             }
+         }
+ 
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> hash::Hash for $FnTy {
+             fn hash<HH: hash::Hasher>(&self, state: &mut HH) {
+                 state.write_usize(*self as usize)
+             }
+         }
+ 
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> fmt::Pointer for $FnTy {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 // HACK: The intermediate cast as usize is required for AVR
+                 // so that the address space of the source function pointer
+                 // is preserved in the final function pointer.
+                 //
+                 // https://github.com/avr-rust/rust/issues/143
+                 fmt::Pointer::fmt(&(*self as usize as *const ()), f)
+             }
+         }
+ 
+         #[stable(feature = "fnptr_impls", since = "1.4.0")]
+         impl<Ret, $($Arg),*> fmt::Debug for $FnTy {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 // HACK: The intermediate cast as usize is required for AVR
+                 // so that the address space of the source function pointer
+                 // is preserved in the final function pointer.
+                 //
+                 // https://github.com/avr-rust/rust/issues/143
+                 fmt::Pointer::fmt(&(*self as usize as *const ()), f)
+             }
+         }
+     }
+ }
+ 
+ macro_rules! fnptr_impls_args {
+     ($($Arg: ident),+) => {
+         fnptr_impls_safety_abi! { extern "Rust" fn($($Arg),+) -> Ret, $($Arg),+ }
+         fnptr_impls_safety_abi! { extern "C" fn($($Arg),+) -> Ret, $($Arg),+ }
+         fnptr_impls_safety_abi! { extern "C" fn($($Arg),+ , ...) -> Ret, $($Arg),+ }
+         fnptr_impls_safety_abi! { unsafe extern "Rust" fn($($Arg),+) -> Ret, $($Arg),+ }
+         fnptr_impls_safety_abi! { unsafe extern "C" fn($($Arg),+) -> Ret, $($Arg),+ }
+         fnptr_impls_safety_abi! { unsafe extern "C" fn($($Arg),+ , ...) -> Ret, $($Arg),+ }
+     };
+     () => {
+         // No variadic functions with 0 parameters
+         fnptr_impls_safety_abi! { extern "Rust" fn() -> Ret, }
+         fnptr_impls_safety_abi! { extern "C" fn() -> Ret, }
+         fnptr_impls_safety_abi! { unsafe extern "Rust" fn() -> Ret, }
+         fnptr_impls_safety_abi! { unsafe extern "C" fn() -> Ret, }
+     };
+ }
+ 
+ fnptr_impls_args! {}
+ fnptr_impls_args! { A }
+ fnptr_impls_args! { A, B }
+ fnptr_impls_args! { A, B, C }
+ fnptr_impls_args! { A, B, C, D }
+ fnptr_impls_args! { A, B, C, D, E }
+ fnptr_impls_args! { A, B, C, D, E, F }
+ fnptr_impls_args! { A, B, C, D, E, F, G }
+ fnptr_impls_args! { A, B, C, D, E, F, G, H }
+ fnptr_impls_args! { A, B, C, D, E, F, G, H, I }
+ fnptr_impls_args! { A, B, C, D, E, F, G, H, I, J }
+ fnptr_impls_args! { A, B, C, D, E, F, G, H, I, J, K }
+ fnptr_impls_args! { A, B, C, D, E, F, G, H, I, J, K, L }
+ 
+ /// Create a `const` raw pointer to a place, without creating an intermediate reference.
+ ///
+ /// Creating a reference with `&`/`&mut` is only allowed if the pointer is properly aligned
+ /// and points to initialized data. For cases where those requirements do not hold,
+ /// raw pointers should be used instead. However, `&expr as *const _` creates a reference
+ /// before casting it to a raw pointer, and that reference is subject to the same rules
+ /// as all other references. This macro can create a raw pointer *without* creating
+ /// a reference first.
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(raw_ref_macros)]
+ /// use std::ptr;
+ ///
+ /// #[repr(packed)]
+ /// struct Packed {
+ ///     f1: u8,
+ ///     f2: u16,
+ /// }
+ ///
+ /// let packed = Packed { f1: 1, f2: 2 };
+ /// // `&packed.f2` would create an unaligned reference, and thus be Undefined Behavior!
+ /// let raw_f2 = ptr::raw_const!(packed.f2);
+ /// assert_eq!(unsafe { raw_f2.read_unaligned() }, 2);
+ /// ```
+ #[unstable(feature = "raw_ref_macros", issue = "73394")]
+ #[rustc_macro_transparency = "semitransparent"]
+ #[allow_internal_unstable(raw_ref_op)]
+ pub macro raw_const($e:expr) {
+     &raw const $e
+ }
+ 
+ /// Create a `mut` raw pointer to a place, without creating an intermediate reference.
+ ///
+ /// Creating a reference with `&`/`&mut` is only allowed if the pointer is properly aligned
+ /// and points to initialized data. For cases where those requirements do not hold,
+ /// raw pointers should be used instead. However, `&mut expr as *mut _` creates a reference
+ /// before casting it to a raw pointer, and that reference is subject to the same rules
+ /// as all other references. This macro can create a raw pointer *without* creating
+ /// a reference first.
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(raw_ref_macros)]
+ /// use std::ptr;
+ ///
+ /// #[repr(packed)]
+ /// struct Packed {
+ ///     f1: u8,
+ ///     f2: u16,
+ /// }
+ ///
+ /// let mut packed = Packed { f1: 1, f2: 2 };
+ /// // `&mut packed.f2` would create an unaligned reference, and thus be Undefined Behavior!
+ /// let raw_f2 = ptr::raw_mut!(packed.f2);
+ /// unsafe { raw_f2.write_unaligned(42); }
+ /// assert_eq!({packed.f2}, 42); // `{...}` forces copying the field instead of creating a reference.
+ /// ```
+ #[unstable(feature = "raw_ref_macros", issue = "73394")]
+ #[rustc_macro_transparency = "semitransparent"]
+ #[allow_internal_unstable(raw_ref_op)]
+ pub macro raw_mut($e:expr) {
+     &raw mut $e
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/mut_ptr.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/mut_ptr.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/mut_ptr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/mut_ptr.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1354 ----
+ use super::*;
+ use crate::cmp::Ordering::{self, Equal, Greater, Less};
+ use crate::intrinsics;
+ use crate::slice::{self, SliceIndex};
+ 
+ #[lang = "mut_ptr"]
+ impl<T: ?Sized> *mut T {
+     /// Returns `true` if the pointer is null.
+     ///
+     /// Note that unsized types have many possible null pointers, as only the
+     /// raw data pointer is considered, not their length, vtable, etc.
+     /// Therefore, two pointers that are null may still not compare equal to
+     /// each other.
+     ///
+     /// ## Behavior during const evaluation
+     ///
+     /// When this function is used during const evaluation, it may return `false` for pointers
+     /// that turn out to be null at runtime. Specifically, when a pointer to some memory
+     /// is offset beyond its bounds in such a way that the resulting pointer is null,
+     /// the function will still return `false`. There is no way for CTFE to know
+     /// the absolute position of that memory, so we cannot tell if the pointer is
+     /// null or not.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut s = [1, 2, 3];
+     /// let ptr: *mut u32 = s.as_mut_ptr();
+     /// assert!(!ptr.is_null());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_ptr_is_null", issue = "74939")]
+     #[inline]
+     pub const fn is_null(self) -> bool {
+         // Compare via a cast to a thin pointer, so fat pointers are only
+         // considering their "data" part for null-ness.
+         (self as *mut u8).guaranteed_eq(null_mut())
+     }
+ 
+     /// Casts to a pointer of another type.
+     #[stable(feature = "ptr_cast", since = "1.38.0")]
+     #[rustc_const_stable(feature = "const_ptr_cast", since = "1.38.0")]
+     #[inline]
+     pub const fn cast<U>(self) -> *mut U {
+         self as _
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a shared reference to
+     /// the value wrapped in `Some`. If the value may be uninitialized, [`as_uninit_ref`]
+     /// must be used instead.
+     ///
+     /// For the mutable counterpart see [`as_mut`].
+     ///
+     /// [`as_uninit_ref`]: #method.as_uninit_ref-1
+     /// [`as_mut`]: #method.as_mut
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * The pointer must point to an initialized instance of `T`.
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     /// (The part about being initialized is not yet fully decided, but until
+     /// it is, the only safe approach is to ensure that they are indeed initialized.)
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let ptr: *mut u8 = &mut 10u8 as *mut u8;
+     ///
+     /// unsafe {
+     ///     if let Some(val_back) = ptr.as_ref() {
+     ///         println!("We got back the value: {}!", val_back);
+     ///     }
+     /// }
+     /// ```
+     ///
+     /// # Null-unchecked version
+     ///
+     /// If you are sure the pointer can never be null and are looking for some kind of
+     /// `as_ref_unchecked` that returns the `&T` instead of `Option<&T>`, know that you can
+     /// dereference the pointer directly.
+     ///
+     /// ```
+     /// let ptr: *mut u8 = &mut 10u8 as *mut u8;
+     ///
+     /// unsafe {
+     ///     let val_back = &*ptr;
+     ///     println!("We got back the value: {}!", val_back);
+     /// }
+     /// ```
+     #[stable(feature = "ptr_as_ref", since = "1.9.0")]
+     #[inline]
+     pub unsafe fn as_ref<'a>(self) -> Option<&'a T> {
+         // SAFETY: the caller must guarantee that `self` is valid for a
+         // reference if it isn't null.
+         if self.is_null() { None } else { unsafe { Some(&*self) } }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a shared reference to
+     /// the value wrapped in `Some`. In contrast to [`as_ref`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// For the mutable counterpart see [`as_uninit_mut`].
+     ///
+     /// [`as_ref`]: #method.as_ref-1
+     /// [`as_uninit_mut`]: #method.as_uninit_mut
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// #![feature(ptr_as_uninit)]
+     ///
+     /// let ptr: *mut u8 = &mut 10u8 as *mut u8;
+     ///
+     /// unsafe {
+     ///     if let Some(val_back) = ptr.as_uninit_ref() {
+     ///         println!("We got back the value: {}!", val_back.assume_init());
+     ///     }
+     /// }
+     /// ```
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_ref<'a>(self) -> Option<&'a MaybeUninit<T>>
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         if self.is_null() { None } else { Some(unsafe { &*(self as *const MaybeUninit<T>) }) }
+     }
+ 
+     /// Calculates the offset from a pointer.
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and resulting pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * The computed offset, **in bytes**, cannot overflow an `isize`.
+     ///
+     /// * The offset being in bounds cannot rely on "wrapping around" the address
+     ///   space. That is, the infinite-precision sum, **in bytes** must fit in a usize.
+     ///
+     /// The compiler and standard library generally tries to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `vec.as_ptr().add(vec.len())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// Consider using [`wrapping_offset`] instead if these constraints are
+     /// difficult to satisfy. The only advantage of this method is that it
+     /// enables more aggressive compiler optimizations.
+     ///
+     /// [`wrapping_offset`]: #method.wrapping_offset
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut s = [1, 2, 3];
+     /// let ptr: *mut u32 = s.as_mut_ptr();
+     ///
+     /// unsafe {
+     ///     println!("{}", *ptr.offset(1));
+     ///     println!("{}", *ptr.offset(2));
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const unsafe fn offset(self, count: isize) -> *mut T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset`.
+         // The obtained pointer is valid for writes since the caller must
+         // guarantee that it points to the same allocated object as `self`.
+         unsafe { intrinsics::offset(self, count) as *mut T }
+     }
+ 
+     /// Calculates the offset from a pointer using wrapping arithmetic.
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// The resulting pointer does not need to be in bounds, but it is
+     /// potentially hazardous to dereference (which requires `unsafe`).
+     ///
+     /// In particular, the resulting pointer remains attached to the same allocated
+     /// object that `self` points to. It may *not* be used to access a
+     /// different allocated object. Note that in Rust,
+     /// every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// In other words, `x.wrapping_offset((y as usize).wrapping_sub(x as usize) / size_of::<T>())`
+     /// is *not* the same as `y`, and dereferencing it is undefined behavior
+     /// unless `x` and `y` point into the same allocated object.
+     ///
+     /// Compared to [`offset`], this method basically delays the requirement of staying
+     /// within the same allocated object: [`offset`] is immediate Undefined Behavior when
+     /// crossing object boundaries; `wrapping_offset` produces a pointer but still leads
+     /// to Undefined Behavior if that pointer is dereferenced. [`offset`] can be optimized
+     /// better and is thus preferable in performance-sensitive code.
+     ///
+     /// If you need to cross object boundaries, cast the pointer to an integer and
+     /// do the arithmetic there.
+     ///
+     /// [`offset`]: #method.offset
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // Iterate using a raw pointer in increments of two elements
+     /// let mut data = [1u8, 2, 3, 4, 5];
+     /// let mut ptr: *mut u8 = data.as_mut_ptr();
+     /// let step = 2;
+     /// let end_rounded_up = ptr.wrapping_offset(6);
+     ///
+     /// while ptr != end_rounded_up {
+     ///     unsafe {
+     ///         *ptr = 0;
+     ///     }
+     ///     ptr = ptr.wrapping_offset(step);
+     /// }
+     /// assert_eq!(&data, &[0, 2, 0, 4, 0]);
+     /// ```
+     #[stable(feature = "ptr_wrapping_offset", since = "1.16.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn wrapping_offset(self, count: isize) -> *mut T
+     where
+         T: Sized,
+     {
+         // SAFETY: the `arith_offset` intrinsic has no prerequisites to be called.
+         unsafe { intrinsics::arith_offset(self, count) as *mut T }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a unique reference to
+     /// the value wrapped in `Some`. If the value may be uninitialized, [`as_uninit_mut`]
+     /// must be used instead.
+     ///
+     /// For the shared counterpart see [`as_ref`].
+     ///
+     /// [`as_uninit_mut`]: #method.as_uninit_mut
+     /// [`as_ref`]: #method.as_ref-1
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * The pointer must point to an initialized instance of `T`.
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get accessed (read or written) through any other pointer.
+     ///
+     /// This applies even if the result of this method is unused!
+     /// (The part about being initialized is not yet fully decided, but until
+     /// it is, the only safe approach is to ensure that they are indeed initialized.)
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut s = [1, 2, 3];
+     /// let ptr: *mut u32 = s.as_mut_ptr();
+     /// let first_value = unsafe { ptr.as_mut().unwrap() };
+     /// *first_value = 4;
+     /// # assert_eq!(s, [4, 2, 3]);
+     /// println!("{:?}", s); // It'll print: "[4, 2, 3]".
+     /// ```
+     ///
+     /// # Null-unchecked version
+     ///
+     /// If you are sure the pointer can never be null and are looking for some kind of
+     /// `as_mut_unchecked` that returns the `&mut T` instead of `Option<&mut T>`, know that
+     /// you can dereference the pointer directly.
+     ///
+     /// ```
+     /// let mut s = [1, 2, 3];
+     /// let ptr: *mut u32 = s.as_mut_ptr();
+     /// let first_value = unsafe { &mut *ptr };
+     /// *first_value = 4;
+     /// # assert_eq!(s, [4, 2, 3]);
+     /// println!("{:?}", s); // It'll print: "[4, 2, 3]".
+     /// ```
+     #[stable(feature = "ptr_as_ref", since = "1.9.0")]
+     #[inline]
+     pub unsafe fn as_mut<'a>(self) -> Option<&'a mut T> {
+         // SAFETY: the caller must guarantee that `self` is be valid for
+         // a mutable reference if it isn't null.
+         if self.is_null() { None } else { unsafe { Some(&mut *self) } }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a unique reference to
+     /// the value wrapped in `Some`. In contrast to [`as_mut`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// For the shared counterpart see [`as_uninit_ref`].
+     ///
+     /// [`as_mut`]: #method.as_mut
+     /// [`as_uninit_ref`]: #method.as_uninit_ref-1
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get accessed (read or written) through any other pointer.
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_mut<'a>(self) -> Option<&'a mut MaybeUninit<T>>
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         if self.is_null() { None } else { Some(unsafe { &mut *(self as *mut MaybeUninit<T>) }) }
+     }
+ 
+     /// Returns whether two pointers are guaranteed to be equal.
+     ///
+     /// At runtime this function behaves like `self == other`.
+     /// However, in some contexts (e.g., compile-time evaluation),
+     /// it is not always possible to determine equality of two pointers, so this function may
+     /// spuriously return `false` for pointers that later actually turn out to be equal.
+     /// But when it returns `true`, the pointers are guaranteed to be equal.
+     ///
+     /// This function is the mirror of [`guaranteed_ne`], but not its inverse. There are pointer
+     /// comparisons for which both functions return `false`.
+     ///
+     /// [`guaranteed_ne`]: #method.guaranteed_ne
+     ///
+     /// The return value may change depending on the compiler version and unsafe code may not
+     /// rely on the result of this function for soundness. It is suggested to only use this function
+     /// for performance optimizations where spurious `false` return values by this function do not
+     /// affect the outcome, but just the performance.
+     /// The consequences of using this method to make runtime and compile-time code behave
+     /// differently have not been explored. This method should not be used to introduce such
+     /// differences, and it should also not be stabilized before we have a better understanding
+     /// of this issue.
+     #[unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[rustc_const_unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[inline]
+     pub const fn guaranteed_eq(self, other: *mut T) -> bool
+     where
+         T: Sized,
+     {
+         intrinsics::ptr_guaranteed_eq(self as *const _, other as *const _)
+     }
+ 
+     /// Returns whether two pointers are guaranteed to be unequal.
+     ///
+     /// At runtime this function behaves like `self != other`.
+     /// However, in some contexts (e.g., compile-time evaluation),
+     /// it is not always possible to determine the inequality of two pointers, so this function may
+     /// spuriously return `false` for pointers that later actually turn out to be unequal.
+     /// But when it returns `true`, the pointers are guaranteed to be unequal.
+     ///
+     /// This function is the mirror of [`guaranteed_eq`], but not its inverse. There are pointer
+     /// comparisons for which both functions return `false`.
+     ///
+     /// [`guaranteed_eq`]: #method.guaranteed_eq
+     ///
+     /// The return value may change depending on the compiler version and unsafe code may not
+     /// rely on the result of this function for soundness. It is suggested to only use this function
+     /// for performance optimizations where spurious `false` return values by this function do not
+     /// affect the outcome, but just the performance.
+     /// The consequences of using this method to make runtime and compile-time code behave
+     /// differently have not been explored. This method should not be used to introduce such
+     /// differences, and it should also not be stabilized before we have a better understanding
+     /// of this issue.
+     #[unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[rustc_const_unstable(feature = "const_raw_ptr_comparison", issue = "53020")]
+     #[inline]
+     pub const unsafe fn guaranteed_ne(self, other: *mut T) -> bool
+     where
+         T: Sized,
+     {
+         intrinsics::ptr_guaranteed_ne(self as *const _, other as *const _)
+     }
+ 
+     /// Calculates the distance between two pointers. The returned value is in
+     /// units of T: the distance in bytes is divided by `mem::size_of::<T>()`.
+     ///
+     /// This function is the inverse of [`offset`].
+     ///
+     /// [`offset`]: #method.offset-1
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and other pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * Both pointers must be *derived from* a pointer to the same object.
+     ///   (See below for an example.)
+     ///
+     /// * The distance between the pointers, **in bytes**, cannot overflow an `isize`.
+     ///
+     /// * The distance between the pointers, in bytes, must be an exact multiple
+     ///   of the size of `T`.
+     ///
+     /// * The distance being in bounds cannot rely on "wrapping around" the address space.
+     ///
+     /// The compiler and standard library generally try to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `ptr_into_vec.offset_from(vec.as_ptr())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// # Panics
+     ///
+     /// This function panics if `T` is a Zero-Sized Type ("ZST").
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut a = [0; 5];
+     /// let ptr1: *mut i32 = &mut a[1];
+     /// let ptr2: *mut i32 = &mut a[3];
+     /// unsafe {
+     ///     assert_eq!(ptr2.offset_from(ptr1), 2);
+     ///     assert_eq!(ptr1.offset_from(ptr2), -2);
+     ///     assert_eq!(ptr1.offset(2), ptr2);
+     ///     assert_eq!(ptr2.offset(-2), ptr1);
+     /// }
+     /// ```
+     ///
+     /// *Incorrect* usage:
+     ///
+     /// ```rust,no_run
+     /// let ptr1 = Box::into_raw(Box::new(0u8));
+     /// let ptr2 = Box::into_raw(Box::new(1u8));
+     /// let diff = (ptr2 as isize).wrapping_sub(ptr1 as isize);
+     /// // Make ptr2_other an "alias" of ptr2, but derived from ptr1.
+     /// let ptr2_other = (ptr1 as *mut u8).wrapping_offset(diff);
+     /// assert_eq!(ptr2 as usize, ptr2_other as usize);
+     /// // Since ptr2_other and ptr2 are derived from pointers to different objects,
+     /// // computing their offset is undefined behavior, even though
+     /// // they point to the same address!
+     /// unsafe {
+     ///     let zero = ptr2_other.offset_from(ptr2); // Undefined Behavior
+     /// }
+     /// ```
+     #[stable(feature = "ptr_offset_from", since = "1.47.0")]
+     #[rustc_const_unstable(feature = "const_ptr_offset_from", issue = "41079")]
+     #[inline]
+     pub const unsafe fn offset_from(self, origin: *const T) -> isize
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset_from`.
+         unsafe { (self as *const T).offset_from(origin) }
+     }
+ 
+     /// Calculates the offset from a pointer (convenience for `.offset(count as isize)`).
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and resulting pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * The computed offset, **in bytes**, cannot overflow an `isize`.
+     ///
+     /// * The offset being in bounds cannot rely on "wrapping around" the address
+     ///   space. That is, the infinite-precision sum must fit in a `usize`.
+     ///
+     /// The compiler and standard library generally tries to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `vec.as_ptr().add(vec.len())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// Consider using [`wrapping_add`] instead if these constraints are
+     /// difficult to satisfy. The only advantage of this method is that it
+     /// enables more aggressive compiler optimizations.
+     ///
+     /// [`wrapping_add`]: #method.wrapping_add
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s: &str = "123";
+     /// let ptr: *const u8 = s.as_ptr();
+     ///
+     /// unsafe {
+     ///     println!("{}", *ptr.add(1) as char);
+     ///     println!("{}", *ptr.add(2) as char);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const unsafe fn add(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset`.
+         unsafe { self.offset(count as isize) }
+     }
+ 
+     /// Calculates the offset from a pointer (convenience for
+     /// `.offset((count as isize).wrapping_neg())`).
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// If any of the following conditions are violated, the result is Undefined
+     /// Behavior:
+     ///
+     /// * Both the starting and resulting pointer must be either in bounds or one
+     ///   byte past the end of the same allocated object. Note that in Rust,
+     ///   every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// * The computed offset cannot exceed `isize::MAX` **bytes**.
+     ///
+     /// * The offset being in bounds cannot rely on "wrapping around" the address
+     ///   space. That is, the infinite-precision sum must fit in a usize.
+     ///
+     /// The compiler and standard library generally tries to ensure allocations
+     /// never reach a size where an offset is a concern. For instance, `Vec`
+     /// and `Box` ensure they never allocate more than `isize::MAX` bytes, so
+     /// `vec.as_ptr().add(vec.len()).sub(vec.len())` is always safe.
+     ///
+     /// Most platforms fundamentally can't even construct such an allocation.
+     /// For instance, no known 64-bit platform can ever serve a request
+     /// for 2<sup>63</sup> bytes due to page-table limitations or splitting the address space.
+     /// However, some 32-bit and 16-bit platforms may successfully serve a request for
+     /// more than `isize::MAX` bytes with things like Physical Address
+     /// Extension. As such, memory acquired directly from allocators or memory
+     /// mapped files *may* be too large to handle with this function.
+     ///
+     /// Consider using [`wrapping_sub`] instead if these constraints are
+     /// difficult to satisfy. The only advantage of this method is that it
+     /// enables more aggressive compiler optimizations.
+     ///
+     /// [`wrapping_sub`]: #method.wrapping_sub
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s: &str = "123";
+     ///
+     /// unsafe {
+     ///     let end: *const u8 = s.as_ptr().add(3);
+     ///     println!("{}", *end.sub(1) as char);
+     ///     println!("{}", *end.sub(2) as char);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const unsafe fn sub(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `offset`.
+         unsafe { self.offset((count as isize).wrapping_neg()) }
+     }
+ 
+     /// Calculates the offset from a pointer using wrapping arithmetic.
+     /// (convenience for `.wrapping_offset(count as isize)`)
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// The resulting pointer does not need to be in bounds, but it is
+     /// potentially hazardous to dereference (which requires `unsafe`).
+     ///
+     /// In particular, the resulting pointer remains attached to the same allocated
+     /// object that `self` points to. It may *not* be used to access a
+     /// different allocated object. Note that in Rust,
+     /// every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// Compared to [`add`], this method basically delays the requirement of staying
+     /// within the same allocated object: [`add`] is immediate Undefined Behavior when
+     /// crossing object boundaries; `wrapping_add` produces a pointer but still leads
+     /// to Undefined Behavior if that pointer is dereferenced. [`add`] can be optimized
+     /// better and is thus preferable in performance-sensitive code.
+     ///
+     /// If you need to cross object boundaries, cast the pointer to an integer and
+     /// do the arithmetic there.
+     ///
+     /// [`add`]: #method.add
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // Iterate using a raw pointer in increments of two elements
+     /// let data = [1u8, 2, 3, 4, 5];
+     /// let mut ptr: *const u8 = data.as_ptr();
+     /// let step = 2;
+     /// let end_rounded_up = ptr.wrapping_add(6);
+     ///
+     /// // This loop prints "1, 3, 5, "
+     /// while ptr != end_rounded_up {
+     ///     unsafe {
+     ///         print!("{}, ", *ptr);
+     ///     }
+     ///     ptr = ptr.wrapping_add(step);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn wrapping_add(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         self.wrapping_offset(count as isize)
+     }
+ 
+     /// Calculates the offset from a pointer using wrapping arithmetic.
+     /// (convenience for `.wrapping_offset((count as isize).wrapping_sub())`)
+     ///
+     /// `count` is in units of T; e.g., a `count` of 3 represents a pointer
+     /// offset of `3 * size_of::<T>()` bytes.
+     ///
+     /// # Safety
+     ///
+     /// The resulting pointer does not need to be in bounds, but it is
+     /// potentially hazardous to dereference (which requires `unsafe`).
+     ///
+     /// In particular, the resulting pointer remains attached to the same allocated
+     /// object that `self` points to. It may *not* be used to access a
+     /// different allocated object. Note that in Rust,
+     /// every (stack-allocated) variable is considered a separate allocated object.
+     ///
+     /// Compared to [`sub`], this method basically delays the requirement of staying
+     /// within the same allocated object: [`sub`] is immediate Undefined Behavior when
+     /// crossing object boundaries; `wrapping_sub` produces a pointer but still leads
+     /// to Undefined Behavior if that pointer is dereferenced. [`sub`] can be optimized
+     /// better and is thus preferable in performance-sensitive code.
+     ///
+     /// If you need to cross object boundaries, cast the pointer to an integer and
+     /// do the arithmetic there.
+     ///
+     /// [`sub`]: #method.sub
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // Iterate using a raw pointer in increments of two elements (backwards)
+     /// let data = [1u8, 2, 3, 4, 5];
+     /// let mut ptr: *const u8 = data.as_ptr();
+     /// let start_rounded_down = ptr.wrapping_sub(2);
+     /// ptr = ptr.wrapping_add(4);
+     /// let step = 2;
+     /// // This loop prints "5, 3, 1, "
+     /// while ptr != start_rounded_down {
+     ///     unsafe {
+     ///         print!("{}, ", *ptr);
+     ///     }
+     ///     ptr = ptr.wrapping_sub(step);
+     /// }
+     /// ```
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn wrapping_sub(self, count: usize) -> Self
+     where
+         T: Sized,
+     {
+         self.wrapping_offset((count as isize).wrapping_neg())
+     }
+ 
+     /// Sets the pointer value to `ptr`.
+     ///
+     /// In case `self` is a (fat) pointer to an unsized type, this operation
+     /// will only affect the pointer part, whereas for (thin) pointers to
+     /// sized types, this has the same effect as a simple assignment.
+     ///
+     /// The resulting pointer will have provenance of `val`, i.e., for a fat
+     /// pointer, this operation is semantically the same as creating a new
+     /// fat pointer with the data pointer value of `val` but the metadata of
+     /// `self`.
+     ///
+     /// # Examples
+     ///
+     /// This function is primarily useful for allowing byte-wise pointer
+     /// arithmetic on potentially fat pointers:
+     ///
+     /// ```
+     /// #![feature(set_ptr_value)]
+     /// # use core::fmt::Debug;
+     /// let mut arr: [i32; 3] = [1, 2, 3];
+     /// let mut ptr = &mut arr[0] as *mut dyn Debug;
+     /// let thin = ptr as *mut u8;
+     /// unsafe {
+     ///     ptr = ptr.set_ptr_value(thin.add(8));
+     ///     # assert_eq!(*(ptr as *mut i32), 3);
+     ///     println!("{:?}", &*ptr); // will print "3"
+     /// }
+     /// ```
+     #[unstable(feature = "set_ptr_value", issue = "75091")]
+     #[must_use = "returns a new pointer rather than modifying its argument"]
+     #[inline]
+     pub fn set_ptr_value(mut self, val: *mut u8) -> Self {
+         let thin = &mut self as *mut *mut T as *mut *mut u8;
+         // SAFETY: In case of a thin pointer, this operations is identical
+         // to a simple assignment. In case of a fat pointer, with the current
+         // fat pointer layout implementation, the first field of such a
+         // pointer is always the data pointer, which is likewise assigned.
+         unsafe { *thin = val };
+         self
+     }
+ 
+     /// Reads the value from `self` without moving it. This leaves the
+     /// memory in `self` unchanged.
+     ///
+     /// See [`ptr::read`] for safety concerns and examples.
+     ///
+     /// [`ptr::read`]: ./ptr/fn.read.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn read(self) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for ``.
+         unsafe { read(self) }
+     }
+ 
+     /// Performs a volatile read of the value from `self` without moving it. This
+     /// leaves the memory in `self` unchanged.
+     ///
+     /// Volatile operations are intended to act on I/O memory, and are guaranteed
+     /// to not be elided or reordered by the compiler across other volatile
+     /// operations.
+     ///
+     /// See [`ptr::read_volatile`] for safety concerns and examples.
+     ///
+     /// [`ptr::read_volatile`]: ./ptr/fn.read_volatile.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn read_volatile(self) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `read_volatile`.
+         unsafe { read_volatile(self) }
+     }
+ 
+     /// Reads the value from `self` without moving it. This leaves the
+     /// memory in `self` unchanged.
+     ///
+     /// Unlike `read`, the pointer may be unaligned.
+     ///
+     /// See [`ptr::read_unaligned`] for safety concerns and examples.
+     ///
+     /// [`ptr::read_unaligned`]: ./ptr/fn.read_unaligned.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn read_unaligned(self) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `read_unaligned`.
+         unsafe { read_unaligned(self) }
+     }
+ 
+     /// Copies `count * size_of<T>` bytes from `self` to `dest`. The source
+     /// and destination may overlap.
+     ///
+     /// NOTE: this has the *same* argument order as [`ptr::copy`].
+     ///
+     /// See [`ptr::copy`] for safety concerns and examples.
+     ///
+     /// [`ptr::copy`]: ./ptr/fn.copy.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn copy_to(self, dest: *mut T, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `copy`.
+         unsafe { copy(self, dest, count) }
+     }
+ 
+     /// Copies `count * size_of<T>` bytes from `self` to `dest`. The source
+     /// and destination may *not* overlap.
+     ///
+     /// NOTE: this has the *same* argument order as [`ptr::copy_nonoverlapping`].
+     ///
+     /// See [`ptr::copy_nonoverlapping`] for safety concerns and examples.
+     ///
+     /// [`ptr::copy_nonoverlapping`]: ./ptr/fn.copy_nonoverlapping.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn copy_to_nonoverlapping(self, dest: *mut T, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `copy_nonoverlapping`.
+         unsafe { copy_nonoverlapping(self, dest, count) }
+     }
+ 
+     /// Copies `count * size_of<T>` bytes from `src` to `self`. The source
+     /// and destination may overlap.
+     ///
+     /// NOTE: this has the *opposite* argument order of [`ptr::copy`].
+     ///
+     /// See [`ptr::copy`] for safety concerns and examples.
+     ///
+     /// [`ptr::copy`]: ./ptr/fn.copy.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn copy_from(self, src: *const T, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `copy`.
+         unsafe { copy(src, self, count) }
+     }
+ 
+     /// Copies `count * size_of<T>` bytes from `src` to `self`. The source
+     /// and destination may *not* overlap.
+     ///
+     /// NOTE: this has the *opposite* argument order of [`ptr::copy_nonoverlapping`].
+     ///
+     /// See [`ptr::copy_nonoverlapping`] for safety concerns and examples.
+     ///
+     /// [`ptr::copy_nonoverlapping`]: ./ptr/fn.copy_nonoverlapping.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn copy_from_nonoverlapping(self, src: *const T, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `copy_nonoverlapping`.
+         unsafe { copy_nonoverlapping(src, self, count) }
+     }
+ 
+     /// Executes the destructor (if any) of the pointed-to value.
+     ///
+     /// See [`ptr::drop_in_place`] for safety concerns and examples.
+     ///
+     /// [`ptr::drop_in_place`]: ./ptr/fn.drop_in_place.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn drop_in_place(self) {
+         // SAFETY: the caller must uphold the safety contract for `drop_in_place`.
+         unsafe { drop_in_place(self) }
+     }
+ 
+     /// Overwrites a memory location with the given value without reading or
+     /// dropping the old value.
+     ///
+     /// See [`ptr::write`] for safety concerns and examples.
+     ///
+     /// [`ptr::write`]: ./ptr/fn.write.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn write(self, val: T)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `write`.
+         unsafe { write(self, val) }
+     }
+ 
+     /// Invokes memset on the specified pointer, setting `count * size_of::<T>()`
+     /// bytes of memory starting at `self` to `val`.
+     ///
+     /// See [`ptr::write_bytes`] for safety concerns and examples.
+     ///
+     /// [`ptr::write_bytes`]: ./ptr/fn.write_bytes.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn write_bytes(self, val: u8, count: usize)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `write_bytes`.
+         unsafe { write_bytes(self, val, count) }
+     }
+ 
+     /// Performs a volatile write of a memory location with the given value without
+     /// reading or dropping the old value.
+     ///
+     /// Volatile operations are intended to act on I/O memory, and are guaranteed
+     /// to not be elided or reordered by the compiler across other volatile
+     /// operations.
+     ///
+     /// See [`ptr::write_volatile`] for safety concerns and examples.
+     ///
+     /// [`ptr::write_volatile`]: ./ptr/fn.write_volatile.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn write_volatile(self, val: T)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `write_volatile`.
+         unsafe { write_volatile(self, val) }
+     }
+ 
+     /// Overwrites a memory location with the given value without reading or
+     /// dropping the old value.
+     ///
+     /// Unlike `write`, the pointer may be unaligned.
+     ///
+     /// See [`ptr::write_unaligned`] for safety concerns and examples.
+     ///
+     /// [`ptr::write_unaligned`]: ./ptr/fn.write_unaligned.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn write_unaligned(self, val: T)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `write_unaligned`.
+         unsafe { write_unaligned(self, val) }
+     }
+ 
+     /// Replaces the value at `self` with `src`, returning the old
+     /// value, without dropping either.
+     ///
+     /// See [`ptr::replace`] for safety concerns and examples.
+     ///
+     /// [`ptr::replace`]: ./ptr/fn.replace.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn replace(self, src: T) -> T
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `replace`.
+         unsafe { replace(self, src) }
+     }
+ 
+     /// Swaps the values at two mutable locations of the same type, without
+     /// deinitializing either. They may overlap, unlike `mem::swap` which is
+     /// otherwise equivalent.
+     ///
+     /// See [`ptr::swap`] for safety concerns and examples.
+     ///
+     /// [`ptr::swap`]: ./ptr/fn.swap.html
+     #[stable(feature = "pointer_methods", since = "1.26.0")]
+     #[inline]
+     pub unsafe fn swap(self, with: *mut T)
+     where
+         T: Sized,
+     {
+         // SAFETY: the caller must uphold the safety contract for `swap`.
+         unsafe { swap(self, with) }
+     }
+ 
+     /// Computes the offset that needs to be applied to the pointer in order to make it aligned to
+     /// `align`.
+     ///
+     /// If it is not possible to align the pointer, the implementation returns
+     /// `usize::MAX`. It is permissible for the implementation to *always*
+     /// return `usize::MAX`. Only your algorithm's performance can depend
+     /// on getting a usable offset here, not its correctness.
+     ///
+     /// The offset is expressed in number of `T` elements, and not bytes. The value returned can be
+     /// used with the `wrapping_add` method.
+     ///
+     /// There are no guarantees whatsoever that offsetting the pointer will not overflow or go
+     /// beyond the allocation that the pointer points into. It is up to the caller to ensure that
+     /// the returned offset is correct in all terms other than alignment.
+     ///
+     /// # Panics
+     ///
+     /// The function panics if `align` is not a power-of-two.
+     ///
+     /// # Examples
+     ///
+     /// Accessing adjacent `u8` as `u16`
+     ///
+     /// ```
+     /// # fn foo(n: usize) {
+     /// # use std::mem::align_of;
+     /// # unsafe {
+     /// let x = [5u8, 6u8, 7u8, 8u8, 9u8];
+     /// let ptr = x.as_ptr().add(n) as *const u8;
+     /// let offset = ptr.align_offset(align_of::<u16>());
+     /// if offset < x.len() - n - 1 {
+     ///     let u16_ptr = ptr.add(offset) as *const u16;
+     ///     assert_ne!(*u16_ptr, 500);
+     /// } else {
+     ///     // while the pointer can be aligned via `offset`, it would point
+     ///     // outside the allocation
+     /// }
+     /// # } }
+     /// ```
+     #[stable(feature = "align_offset", since = "1.36.0")]
+     pub fn align_offset(self, align: usize) -> usize
+     where
+         T: Sized,
+     {
+         if !align.is_power_of_two() {
+             panic!("align_offset: align is not a power-of-two");
+         }
+         // SAFETY: `align` has been checked to be a power of 2 above
+         unsafe { align_offset(self, align) }
+     }
+ }
+ 
+ #[lang = "mut_slice_ptr"]
+ impl<T> *mut [T] {
+     /// Returns the length of a raw slice.
+     ///
+     /// The returned value is the number of **elements**, not the number of bytes.
+     ///
+     /// This function is safe, even when the raw slice cannot be cast to a slice
+     /// reference because the pointer is null or unaligned.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_len)]
+     /// use std::ptr;
+     ///
+     /// let slice: *mut [i8] = ptr::slice_from_raw_parts_mut(ptr::null_mut(), 3);
+     /// assert_eq!(slice.len(), 3);
+     /// ```
+     #[inline]
+     #[unstable(feature = "slice_ptr_len", issue = "71146")]
+     #[rustc_const_unstable(feature = "const_slice_ptr_len", issue = "71146")]
+     pub const fn len(self) -> usize {
+         // SAFETY: this is safe because `*const [T]` and `FatPtr<T>` have the same layout.
+         // Only `std` can make this guarantee.
+         unsafe { Repr { rust_mut: self }.raw }.len
+     }
+ 
+     /// Returns a raw pointer to the slice's buffer.
+     ///
+     /// This is equivalent to casting `self` to `*mut T`, but more type-safe.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_get)]
+     /// use std::ptr;
+     ///
+     /// let slice: *mut [i8] = ptr::slice_from_raw_parts_mut(ptr::null_mut(), 3);
+     /// assert_eq!(slice.as_mut_ptr(), 0 as *mut i8);
+     /// ```
+     #[inline]
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[rustc_const_unstable(feature = "slice_ptr_get", issue = "74265")]
+     pub const fn as_mut_ptr(self) -> *mut T {
+         self as *mut T
+     }
+ 
+     /// Returns a raw pointer to an element or subslice, without doing bounds
+     /// checking.
+     ///
+     /// Calling this method with an out-of-bounds index or when `self` is not dereferencable
+     /// is *[undefined behavior]* even if the resulting pointer is not used.
+     ///
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_ptr_get)]
+     ///
+     /// let x = &mut [1, 2, 4] as *mut [i32];
+     ///
+     /// unsafe {
+     ///     assert_eq!(x.get_unchecked_mut(1), x.as_mut_ptr().add(1));
+     /// }
+     /// ```
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[inline]
+     pub unsafe fn get_unchecked_mut<I>(self, index: I) -> *mut I::Output
+     where
+         I: SliceIndex<[T]>,
+     {
+         // SAFETY: the caller ensures that `self` is dereferencable and `index` in-bounds.
+         unsafe { index.get_unchecked_mut(self) }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a shared slice to
+     /// the value wrapped in `Some`. In contrast to [`as_ref`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// For the mutable counterpart see [`as_uninit_slice_mut`].
+     ///
+     /// [`as_ref`]: #method.as_ref-1
+     /// [`as_uninit_slice_mut`]: #method.as_uninit_slice_mut
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be [valid] for reads for `ptr.len() * mem::size_of::<T>()` many bytes,
+     ///   and it must be properly aligned. This means in particular:
+     ///
+     ///     * The entire memory range of this slice must be contained within a single allocated object!
+     ///       Slices can never span across multiple allocated objects.
+     ///
+     ///     * The pointer must be aligned even for zero-length slices. One
+     ///       reason for this is that enum layout optimizations may rely on references
+     ///       (including slices of any length) being aligned and non-null to distinguish
+     ///       them from other data. You can obtain a pointer that is usable as `data`
+     ///       for zero-length slices using [`NonNull::dangling()`].
+     ///
+     /// * The total size `ptr.len() * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+     ///   See the safety documentation of [`pointer::offset`].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// See also [`slice::from_raw_parts`][].
+     ///
+     /// [valid]: crate::ptr#safety
+     /// [`NonNull::dangling()`]: NonNull::dangling
+     /// [`pointer::offset`]: ../std/primitive.pointer.html#method.offset
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_slice<'a>(self) -> Option<&'a [MaybeUninit<T>]> {
+         if self.is_null() {
+             None
+         } else {
+             // SAFETY: the caller must uphold the safety contract for `as_uninit_slice`.
+             Some(unsafe { slice::from_raw_parts(self as *const MaybeUninit<T>, self.len()) })
+         }
+     }
+ 
+     /// Returns `None` if the pointer is null, or else returns a unique slice to
+     /// the value wrapped in `Some`. In contrast to [`as_mut`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// For the shared counterpart see [`as_uninit_slice`].
+     ///
+     /// [`as_mut`]: #method.as_mut
+     /// [`as_uninit_slice`]: #method.as_uninit_slice-1
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that *either* the pointer is NULL *or*
+     /// all of the following is true:
+     ///
+     /// * The pointer must be [valid] for reads and writes for `ptr.len() * mem::size_of::<T>()`
+     ///   many bytes, and it must be properly aligned. This means in particular:
+     ///
+     ///     * The entire memory range of this slice must be contained within a single allocated object!
+     ///       Slices can never span across multiple allocated objects.
+     ///
+     ///     * The pointer must be aligned even for zero-length slices. One
+     ///       reason for this is that enum layout optimizations may rely on references
+     ///       (including slices of any length) being aligned and non-null to distinguish
+     ///       them from other data. You can obtain a pointer that is usable as `data`
+     ///       for zero-length slices using [`NonNull::dangling()`].
+     ///
+     /// * The total size `ptr.len() * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+     ///   See the safety documentation of [`pointer::offset`].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get accessed (read or written) through any other pointer.
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// See also [`slice::from_raw_parts_mut`][].
+     ///
+     /// [valid]: crate::ptr#safety
+     /// [`NonNull::dangling()`]: NonNull::dangling
+     /// [`pointer::offset`]: ../std/primitive.pointer.html#method.offset
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_slice_mut<'a>(self) -> Option<&'a mut [MaybeUninit<T>]> {
+         if self.is_null() {
+             None
+         } else {
+             // SAFETY: the caller must uphold the safety contract for `as_uninit_slice_mut`.
+             Some(unsafe { slice::from_raw_parts_mut(self as *mut MaybeUninit<T>, self.len()) })
+         }
+     }
+ }
+ 
+ // Equality for pointers
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> PartialEq for *mut T {
+     #[inline]
+     fn eq(&self, other: &*mut T) -> bool {
+         *self == *other
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Eq for *mut T {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> Ord for *mut T {
+     #[inline]
+     fn cmp(&self, other: &*mut T) -> Ordering {
+         if self < other {
+             Less
+         } else if self == other {
+             Equal
+         } else {
+             Greater
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: ?Sized> PartialOrd for *mut T {
+     #[inline]
+     fn partial_cmp(&self, other: &*mut T) -> Option<Ordering> {
+         Some(self.cmp(other))
+     }
+ 
+     #[inline]
+     fn lt(&self, other: &*mut T) -> bool {
+         *self < *other
+     }
+ 
+     #[inline]
+     fn le(&self, other: &*mut T) -> bool {
+         *self <= *other
+     }
+ 
+     #[inline]
+     fn gt(&self, other: &*mut T) -> bool {
+         *self > *other
+     }
+ 
+     #[inline]
+     fn ge(&self, other: &*mut T) -> bool {
+         *self >= *other
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/non_null.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/non_null.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/non_null.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/non_null.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,586 ----
+ use crate::cmp::Ordering;
+ use crate::convert::From;
+ use crate::fmt;
+ use crate::hash;
+ use crate::marker::Unsize;
+ use crate::mem::{self, MaybeUninit};
+ use crate::ops::{CoerceUnsized, DispatchFromDyn};
+ use crate::ptr::Unique;
+ use crate::slice::{self, SliceIndex};
+ 
+ /// `*mut T` but non-zero and covariant.
+ ///
+ /// This is often the correct thing to use when building data structures using
+ /// raw pointers, but is ultimately more dangerous to use because of its additional
+ /// properties. If you're not sure if you should use `NonNull<T>`, just use `*mut T`!
+ ///
+ /// Unlike `*mut T`, the pointer must always be non-null, even if the pointer
+ /// is never dereferenced. This is so that enums may use this forbidden value
+ /// as a discriminant -- `Option<NonNull<T>>` has the same size as `*mut T`.
+ /// However the pointer may still dangle if it isn't dereferenced.
+ ///
+ /// Unlike `*mut T`, `NonNull<T>` is covariant over `T`. If this is incorrect
+ /// for your use case, you should include some [`PhantomData`] in your type to
+ /// provide invariance, such as `PhantomData<Cell<T>>` or `PhantomData<&'a mut T>`.
+ /// Usually this won't be necessary; covariance is correct for most safe abstractions,
+ /// such as `Box`, `Rc`, `Arc`, `Vec`, and `LinkedList`. This is the case because they
+ /// provide a public API that follows the normal shared XOR mutable rules of Rust.
+ ///
+ /// Notice that `NonNull<T>` has a `From` instance for `&T`. However, this does
+ /// not change the fact that mutating through a (pointer derived from a) shared
+ /// reference is undefined behavior unless the mutation happens inside an
+ /// [`UnsafeCell<T>`]. The same goes for creating a mutable reference from a shared
+ /// reference. When using this `From` instance without an `UnsafeCell<T>`,
+ /// it is your responsibility to ensure that `as_mut` is never called, and `as_ptr`
+ /// is never used for mutation.
+ ///
+ /// [`PhantomData`]: crate::marker::PhantomData
+ /// [`UnsafeCell<T>`]: crate::cell::UnsafeCell
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ #[repr(transparent)]
+ #[rustc_layout_scalar_valid_range_start(1)]
+ #[rustc_nonnull_optimization_guaranteed]
+ pub struct NonNull<T: ?Sized> {
+     pointer: *const T,
+ }
+ 
+ /// `NonNull` pointers are not `Send` because the data they reference may be aliased.
+ // N.B., this impl is unnecessary, but should provide better error messages.
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> !Send for NonNull<T> {}
+ 
+ /// `NonNull` pointers are not `Sync` because the data they reference may be aliased.
+ // N.B., this impl is unnecessary, but should provide better error messages.
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> !Sync for NonNull<T> {}
+ 
+ impl<T: Sized> NonNull<T> {
+     /// Creates a new `NonNull` that is dangling, but well-aligned.
+     ///
+     /// This is useful for initializing types which lazily allocate, like
+     /// `Vec::new` does.
+     ///
+     /// Note that the pointer value may potentially represent a valid pointer to
+     /// a `T`, which means this must not be used as a "not yet initialized"
+     /// sentinel value. Types that lazily allocate must track initialization by
+     /// some other means.
+     #[stable(feature = "nonnull", since = "1.25.0")]
+     #[rustc_const_stable(feature = "const_nonnull_dangling", since = "1.32.0")]
+     #[inline]
+     pub const fn dangling() -> Self {
+         // SAFETY: mem::align_of() returns a non-zero usize which is then casted
+         // to a *mut T. Therefore, `ptr` is not null and the conditions for
+         // calling new_unchecked() are respected.
+         unsafe {
+             let ptr = mem::align_of::<T>() as *mut T;
+             NonNull::new_unchecked(ptr)
+         }
+     }
+ 
+     /// Returns a shared references to the value. In contrast to [`as_ref`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// For the mutable counterpart see [`as_uninit_mut`].
+     ///
+     /// [`as_ref`]: NonNull::as_ref
+     /// [`as_uninit_mut`]: NonNull::as_uninit_mut
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_ref(&self) -> &MaybeUninit<T> {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         unsafe { &*self.cast().as_ptr() }
+     }
+ 
+     /// Returns a unique references to the value. In contrast to [`as_mut`], this does not require
+     /// that the value has to be initialized.
+     ///
+     /// For the shared counterpart see [`as_uninit_ref`].
+     ///
+     /// [`as_mut`]: NonNull::as_mut
+     /// [`as_uninit_ref`]: NonNull::as_uninit_ref
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get accessed (read or written) through any other pointer.
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_mut(&mut self) -> &mut MaybeUninit<T> {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         unsafe { &mut *self.cast().as_ptr() }
+     }
+ }
+ 
+ impl<T: ?Sized> NonNull<T> {
+     /// Creates a new `NonNull`.
+     ///
+     /// # Safety
+     ///
+     /// `ptr` must be non-null.
+     #[stable(feature = "nonnull", since = "1.25.0")]
+     #[rustc_const_stable(feature = "const_nonnull_new_unchecked", since = "1.32.0")]
+     #[inline]
+     pub const unsafe fn new_unchecked(ptr: *mut T) -> Self {
+         // SAFETY: the caller must guarantee that `ptr` is non-null.
+         unsafe { NonNull { pointer: ptr as _ } }
+     }
+ 
+     /// Creates a new `NonNull` if `ptr` is non-null.
+     #[stable(feature = "nonnull", since = "1.25.0")]
+     #[inline]
+     pub fn new(ptr: *mut T) -> Option<Self> {
+         if !ptr.is_null() {
+             // SAFETY: The pointer is already checked and is not null
+             Some(unsafe { Self::new_unchecked(ptr) })
+         } else {
+             None
+         }
+     }
+ 
+     /// Acquires the underlying `*mut` pointer.
+     #[stable(feature = "nonnull", since = "1.25.0")]
+     #[rustc_const_stable(feature = "const_nonnull_as_ptr", since = "1.32.0")]
+     #[inline]
+     pub const fn as_ptr(self) -> *mut T {
+         self.pointer as *mut T
+     }
+ 
+     /// Returns a shared reference to the value. If the value may be uninitialized, [`as_uninit_ref`]
+     /// must be used instead.
+     ///
+     /// For the mutable counterpart see [`as_mut`].
+     ///
+     /// [`as_uninit_ref`]: NonNull::as_uninit_ref
+     /// [`as_mut`]: NonNull::as_mut
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * The pointer must point to an initialized instance of `T`.
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     /// (The part about being initialized is not yet fully decided, but until
+     /// it is, the only safe approach is to ensure that they are indeed initialized.)
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     #[stable(feature = "nonnull", since = "1.25.0")]
+     #[inline]
+     pub unsafe fn as_ref(&self) -> &T {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         unsafe { &*self.as_ptr() }
+     }
+ 
+     /// Returns a unique reference to the value. If the value may be uninitialized, [`as_uninit_mut`]
+     /// must be used instead.
+     ///
+     /// For the shared counterpart see [`as_ref`].
+     ///
+     /// [`as_uninit_mut`]: NonNull::as_uninit_mut
+     /// [`as_ref`]: NonNull::as_ref
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that all of the following is true:
+     ///
+     /// * The pointer must be properly aligned.
+     ///
+     /// * It must be "dereferencable" in the sense defined in [the module documentation].
+     ///
+     /// * The pointer must point to an initialized instance of `T`.
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get accessed (read or written) through any other pointer.
+     ///
+     /// This applies even if the result of this method is unused!
+     /// (The part about being initialized is not yet fully decided, but until
+     /// it is, the only safe approach is to ensure that they are indeed initialized.)
+     ///
+     /// [the module documentation]: crate::ptr#safety
+     #[stable(feature = "nonnull", since = "1.25.0")]
+     #[inline]
+     pub unsafe fn as_mut(&mut self) -> &mut T {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a mutable reference.
+         unsafe { &mut *self.as_ptr() }
+     }
+ 
+     /// Casts to a pointer of another type.
+     #[stable(feature = "nonnull_cast", since = "1.27.0")]
+     #[rustc_const_stable(feature = "const_nonnull_cast", since = "1.32.0")]
+     #[inline]
+     pub const fn cast<U>(self) -> NonNull<U> {
+         // SAFETY: `self` is a `NonNull` pointer which is necessarily non-null
+         unsafe { NonNull::new_unchecked(self.as_ptr() as *mut U) }
+     }
+ }
+ 
+ impl<T> NonNull<[T]> {
+     /// Creates a non-null raw slice from a thin pointer and a length.
+     ///
+     /// The `len` argument is the number of **elements**, not the number of bytes.
+     ///
+     /// This function is safe, but dereferencing the return value is unsafe.
+     /// See the documentation of [`slice::from_raw_parts`] for slice safety requirements.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(nonnull_slice_from_raw_parts)]
+     ///
+     /// use std::ptr::NonNull;
+     ///
+     /// // create a slice pointer when starting out with a pointer to the first element
+     /// let mut x = [5, 6, 7];
+     /// let nonnull_pointer = NonNull::new(x.as_mut_ptr()).unwrap();
+     /// let slice = NonNull::slice_from_raw_parts(nonnull_pointer, 3);
+     /// assert_eq!(unsafe { slice.as_ref()[2] }, 7);
+     /// ```
+     ///
+     /// (Note that this example artificially demonstrates a use of this method,
+     /// but `let slice = NonNull::from(&x[..]);` would be a better way to write code like this.)
+     #[unstable(feature = "nonnull_slice_from_raw_parts", issue = "71941")]
+     #[rustc_const_unstable(feature = "const_nonnull_slice_from_raw_parts", issue = "71941")]
+     #[inline]
+     pub const fn slice_from_raw_parts(data: NonNull<T>, len: usize) -> Self {
+         // SAFETY: `data` is a `NonNull` pointer which is necessarily non-null
+         unsafe { Self::new_unchecked(super::slice_from_raw_parts_mut(data.as_ptr(), len)) }
+     }
+ 
+     /// Returns the length of a non-null raw slice.
+     ///
+     /// The returned value is the number of **elements**, not the number of bytes.
+     ///
+     /// This function is safe, even when the non-null raw slice cannot be dereferenced to a slice
+     /// because the pointer does not have a valid address.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_len, nonnull_slice_from_raw_parts)]
+     /// use std::ptr::NonNull;
+     ///
+     /// let slice: NonNull<[i8]> = NonNull::slice_from_raw_parts(NonNull::dangling(), 3);
+     /// assert_eq!(slice.len(), 3);
+     /// ```
+     #[unstable(feature = "slice_ptr_len", issue = "71146")]
+     #[rustc_const_unstable(feature = "const_slice_ptr_len", issue = "71146")]
+     #[inline]
+     pub const fn len(self) -> usize {
+         self.as_ptr().len()
+     }
+ 
+     /// Returns a non-null pointer to the slice's buffer.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_get, nonnull_slice_from_raw_parts)]
+     /// use std::ptr::NonNull;
+     ///
+     /// let slice: NonNull<[i8]> = NonNull::slice_from_raw_parts(NonNull::dangling(), 3);
+     /// assert_eq!(slice.as_non_null_ptr(), NonNull::new(1 as *mut i8).unwrap());
+     /// ```
+     #[inline]
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[rustc_const_unstable(feature = "slice_ptr_get", issue = "74265")]
+     pub const fn as_non_null_ptr(self) -> NonNull<T> {
+         // SAFETY: We know `self` is non-null.
+         unsafe { NonNull::new_unchecked(self.as_ptr().as_mut_ptr()) }
+     }
+ 
+     /// Returns a raw pointer to the slice's buffer.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(slice_ptr_get, nonnull_slice_from_raw_parts)]
+     /// use std::ptr::NonNull;
+     ///
+     /// let slice: NonNull<[i8]> = NonNull::slice_from_raw_parts(NonNull::dangling(), 3);
+     /// assert_eq!(slice.as_mut_ptr(), 1 as *mut i8);
+     /// ```
+     #[inline]
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[rustc_const_unstable(feature = "slice_ptr_get", issue = "74265")]
+     pub const fn as_mut_ptr(self) -> *mut T {
+         self.as_non_null_ptr().as_ptr()
+     }
+ 
+     /// Returns a shared reference to a slice of possibly uninitialized values. In contrast to
+     /// [`as_ref`], this does not require that the value has to be initialized.
+     ///
+     /// For the mutable counterpart see [`as_uninit_slice_mut`].
+     ///
+     /// [`as_ref`]: NonNull::as_ref
+     /// [`as_uninit_slice_mut`]: NonNull::as_uninit_slice_mut
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that all of the following is true:
+     ///
+     /// * The pointer must be [valid] for reads for `ptr.len() * mem::size_of::<T>()` many bytes,
+     ///   and it must be properly aligned. This means in particular:
+     ///
+     ///     * The entire memory range of this slice must be contained within a single allocated object!
+     ///       Slices can never span across multiple allocated objects.
+     ///
+     ///     * The pointer must be aligned even for zero-length slices. One
+     ///       reason for this is that enum layout optimizations may rely on references
+     ///       (including slices of any length) being aligned and non-null to distinguish
+     ///       them from other data. You can obtain a pointer that is usable as `data`
+     ///       for zero-length slices using [`NonNull::dangling()`].
+     ///
+     /// * The total size `ptr.len() * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+     ///   See the safety documentation of [`pointer::offset`].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get mutated (except inside `UnsafeCell`).
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// See also [`slice::from_raw_parts`].
+     ///
+     /// [valid]: crate::ptr#safety
+     /// [`pointer::offset`]: ../../std/primitive.pointer.html#method.offset
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_slice(&self) -> &[MaybeUninit<T>] {
+         // SAFETY: the caller must uphold the safety contract for `as_uninit_slice`.
+         unsafe { slice::from_raw_parts(self.cast().as_ptr(), self.len()) }
+     }
+ 
+     /// Returns a unique reference to a slice of possibly uninitialized values. In contrast to
+     /// [`as_mut`], this does not require that the value has to be initialized.
+     ///
+     /// For the shared counterpart see [`as_uninit_slice`].
+     ///
+     /// [`as_mut`]: NonNull::as_mut
+     /// [`as_uninit_slice`]: NonNull::as_uninit_slice
+     ///
+     /// # Safety
+     ///
+     /// When calling this method, you have to ensure that all of the following is true:
+     ///
+     /// * The pointer must be [valid] for reads and writes for `ptr.len() * mem::size_of::<T>()`
+     ///   many bytes, and it must be properly aligned. This means in particular:
+     ///
+     ///     * The entire memory range of this slice must be contained within a single allocated object!
+     ///       Slices can never span across multiple allocated objects.
+     ///
+     ///     * The pointer must be aligned even for zero-length slices. One
+     ///       reason for this is that enum layout optimizations may rely on references
+     ///       (including slices of any length) being aligned and non-null to distinguish
+     ///       them from other data. You can obtain a pointer that is usable as `data`
+     ///       for zero-length slices using [`NonNull::dangling()`].
+     ///
+     /// * The total size `ptr.len() * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+     ///   See the safety documentation of [`pointer::offset`].
+     ///
+     /// * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is
+     ///   arbitrarily chosen and does not necessarily reflect the actual lifetime of the data.
+     ///   In particular, for the duration of this lifetime, the memory the pointer points to must
+     ///   not get accessed (read or written) through any other pointer.
+     ///
+     /// This applies even if the result of this method is unused!
+     ///
+     /// See also [`slice::from_raw_parts_mut`].
+     ///
+     /// [valid]: crate::ptr#safety
+     /// [`pointer::offset`]: ../../std/primitive.pointer.html#method.offset
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(allocator_api, ptr_as_uninit)]
+     ///
+     /// use std::alloc::{AllocRef, Layout, Global};
+     /// use std::mem::MaybeUninit;
+     /// use std::ptr::NonNull;
+     ///
+     /// let memory: NonNull<[u8]> = Global.alloc(Layout::new::<[u8; 32]>())?;
+     /// // This is safe as `memory` is valid for reads and writes for `memory.len()` many bytes.
+     /// // Note that calling `memory.as_mut()` is not allowed here as the content may be uninitialized.
+     /// # #[allow(unused_variables)]
+     /// let slice: &mut [MaybeUninit<u8>] = unsafe { memory.as_uninit_slice_mut() };
+     /// # Ok::<_, std::alloc::AllocError>(())
+     /// ```
+     #[inline]
+     #[unstable(feature = "ptr_as_uninit", issue = "75402")]
+     pub unsafe fn as_uninit_slice_mut(&self) -> &mut [MaybeUninit<T>] {
+         // SAFETY: the caller must uphold the safety contract for `as_uninit_slice_mut`.
+         unsafe { slice::from_raw_parts_mut(self.cast().as_ptr(), self.len()) }
+     }
+ 
+     /// Returns a raw pointer to an element or subslice, without doing bounds
+     /// checking.
+     ///
+     /// Calling this method with an out-of-bounds index or when `self` is not dereferencable
+     /// is *[undefined behavior]* even if the resulting pointer is not used.
+     ///
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_ptr_get, nonnull_slice_from_raw_parts)]
+     /// use std::ptr::NonNull;
+     ///
+     /// let x = &mut [1, 2, 4];
+     /// let x = NonNull::slice_from_raw_parts(NonNull::new(x.as_mut_ptr()).unwrap(), x.len());
+     ///
+     /// unsafe {
+     ///     assert_eq!(x.get_unchecked_mut(1).as_ptr(), x.as_non_null_ptr().as_ptr().add(1));
+     /// }
+     /// ```
+     #[unstable(feature = "slice_ptr_get", issue = "74265")]
+     #[inline]
+     pub unsafe fn get_unchecked_mut<I>(self, index: I) -> NonNull<I::Output>
+     where
+         I: SliceIndex<[T]>,
+     {
+         // SAFETY: the caller ensures that `self` is dereferencable and `index` in-bounds.
+         // As a consequence, the resulting pointer cannot be NULL.
+         unsafe { NonNull::new_unchecked(self.as_ptr().get_unchecked_mut(index)) }
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> Clone for NonNull<T> {
+     #[inline]
+     fn clone(&self) -> Self {
+         *self
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> Copy for NonNull<T> {}
+ 
+ #[unstable(feature = "coerce_unsized", issue = "27732")]
+ impl<T: ?Sized, U: ?Sized> CoerceUnsized<NonNull<U>> for NonNull<T> where T: Unsize<U> {}
+ 
+ #[unstable(feature = "dispatch_from_dyn", issue = "none")]
+ impl<T: ?Sized, U: ?Sized> DispatchFromDyn<NonNull<U>> for NonNull<T> where T: Unsize<U> {}
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> fmt::Debug for NonNull<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Pointer::fmt(&self.as_ptr(), f)
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> fmt::Pointer for NonNull<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Pointer::fmt(&self.as_ptr(), f)
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> Eq for NonNull<T> {}
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> PartialEq for NonNull<T> {
+     #[inline]
+     fn eq(&self, other: &Self) -> bool {
+         self.as_ptr() == other.as_ptr()
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> Ord for NonNull<T> {
+     #[inline]
+     fn cmp(&self, other: &Self) -> Ordering {
+         self.as_ptr().cmp(&other.as_ptr())
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> PartialOrd for NonNull<T> {
+     #[inline]
+     fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+         self.as_ptr().partial_cmp(&other.as_ptr())
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> hash::Hash for NonNull<T> {
+     #[inline]
+     fn hash<H: hash::Hasher>(&self, state: &mut H) {
+         self.as_ptr().hash(state)
+     }
+ }
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> From<Unique<T>> for NonNull<T> {
+     #[inline]
+     fn from(unique: Unique<T>) -> Self {
+         // SAFETY: A Unique pointer cannot be null, so the conditions for
+         // new_unchecked() are respected.
+         unsafe { NonNull::new_unchecked(unique.as_ptr()) }
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> From<&mut T> for NonNull<T> {
+     #[inline]
+     fn from(reference: &mut T) -> Self {
+         // SAFETY: A mutable reference cannot be null.
+         unsafe { NonNull { pointer: reference as *mut T } }
+     }
+ }
+ 
+ #[stable(feature = "nonnull", since = "1.25.0")]
+ impl<T: ?Sized> From<&T> for NonNull<T> {
+     #[inline]
+     fn from(reference: &T) -> Self {
+         // SAFETY: A reference cannot be null, so the conditions for
+         // new_unchecked() are respected.
+         unsafe { NonNull { pointer: reference as *const T } }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/unique.rs gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/unique.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/ptr/unique.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/ptr/unique.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,181 ----
+ use crate::convert::From;
+ use crate::fmt;
+ use crate::marker::{PhantomData, Unsize};
+ use crate::mem;
+ use crate::ops::{CoerceUnsized, DispatchFromDyn};
+ 
+ /// A wrapper around a raw non-null `*mut T` that indicates that the possessor
+ /// of this wrapper owns the referent. Useful for building abstractions like
+ /// `Box<T>`, `Vec<T>`, `String`, and `HashMap<K, V>`.
+ ///
+ /// Unlike `*mut T`, `Unique<T>` behaves "as if" it were an instance of `T`.
+ /// It implements `Send`/`Sync` if `T` is `Send`/`Sync`. It also implies
+ /// the kind of strong aliasing guarantees an instance of `T` can expect:
+ /// the referent of the pointer should not be modified without a unique path to
+ /// its owning Unique.
+ ///
+ /// If you're uncertain of whether it's correct to use `Unique` for your purposes,
+ /// consider using `NonNull`, which has weaker semantics.
+ ///
+ /// Unlike `*mut T`, the pointer must always be non-null, even if the pointer
+ /// is never dereferenced. This is so that enums may use this forbidden value
+ /// as a discriminant -- `Option<Unique<T>>` has the same size as `Unique<T>`.
+ /// However the pointer may still dangle if it isn't dereferenced.
+ ///
+ /// Unlike `*mut T`, `Unique<T>` is covariant over `T`. This should always be correct
+ /// for any type which upholds Unique's aliasing requirements.
+ #[unstable(
+     feature = "ptr_internals",
+     issue = "none",
+     reason = "use `NonNull` instead and consider `PhantomData<T>` \
+               (if you also use `#[may_dangle]`), `Send`, and/or `Sync`"
+ )]
+ #[doc(hidden)]
+ #[repr(transparent)]
+ #[rustc_layout_scalar_valid_range_start(1)]
+ pub struct Unique<T: ?Sized> {
+     pointer: *const T,
+     // NOTE: this marker has no consequences for variance, but is necessary
+     // for dropck to understand that we logically own a `T`.
+     //
+     // For details, see:
+     // https://github.com/rust-lang/rfcs/blob/master/text/0769-sound-generic-drop.md#phantom-data
+     _marker: PhantomData<T>,
+ }
+ 
+ /// `Unique` pointers are `Send` if `T` is `Send` because the data they
+ /// reference is unaliased. Note that this aliasing invariant is
+ /// unenforced by the type system; the abstraction using the
+ /// `Unique` must enforce it.
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ unsafe impl<T: Send + ?Sized> Send for Unique<T> {}
+ 
+ /// `Unique` pointers are `Sync` if `T` is `Sync` because the data they
+ /// reference is unaliased. Note that this aliasing invariant is
+ /// unenforced by the type system; the abstraction using the
+ /// `Unique` must enforce it.
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ unsafe impl<T: Sync + ?Sized> Sync for Unique<T> {}
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: Sized> Unique<T> {
+     /// Creates a new `Unique` that is dangling, but well-aligned.
+     ///
+     /// This is useful for initializing types which lazily allocate, like
+     /// `Vec::new` does.
+     ///
+     /// Note that the pointer value may potentially represent a valid pointer to
+     /// a `T`, which means this must not be used as a "not yet initialized"
+     /// sentinel value. Types that lazily allocate must track initialization by
+     /// some other means.
+     #[inline]
+     pub const fn dangling() -> Self {
+         // SAFETY: mem::align_of() returns a valid, non-null pointer. The
+         // conditions to call new_unchecked() are thus respected.
+         unsafe { Unique::new_unchecked(mem::align_of::<T>() as *mut T) }
+     }
+ }
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> Unique<T> {
+     /// Creates a new `Unique`.
+     ///
+     /// # Safety
+     ///
+     /// `ptr` must be non-null.
+     #[inline]
+     pub const unsafe fn new_unchecked(ptr: *mut T) -> Self {
+         // SAFETY: the caller must guarantee that `ptr` is non-null.
+         unsafe { Unique { pointer: ptr as _, _marker: PhantomData } }
+     }
+ 
+     /// Creates a new `Unique` if `ptr` is non-null.
+     #[inline]
+     pub fn new(ptr: *mut T) -> Option<Self> {
+         if !ptr.is_null() {
+             // SAFETY: The pointer has already been checked and is not null.
+             Some(unsafe { Unique { pointer: ptr as _, _marker: PhantomData } })
+         } else {
+             None
+         }
+     }
+ 
+     /// Acquires the underlying `*mut` pointer.
+     #[inline]
+     pub const fn as_ptr(self) -> *mut T {
+         self.pointer as *mut T
+     }
+ 
+     /// Dereferences the content.
+     ///
+     /// The resulting lifetime is bound to self so this behaves "as if"
+     /// it were actually an instance of T that is getting borrowed. If a longer
+     /// (unbound) lifetime is needed, use `&*my_ptr.as_ptr()`.
+     #[inline]
+     pub unsafe fn as_ref(&self) -> &T {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a reference.
+         unsafe { &*self.as_ptr() }
+     }
+ 
+     /// Mutably dereferences the content.
+     ///
+     /// The resulting lifetime is bound to self so this behaves "as if"
+     /// it were actually an instance of T that is getting borrowed. If a longer
+     /// (unbound) lifetime is needed, use `&mut *my_ptr.as_ptr()`.
+     #[inline]
+     pub unsafe fn as_mut(&mut self) -> &mut T {
+         // SAFETY: the caller must guarantee that `self` meets all the
+         // requirements for a mutable reference.
+         unsafe { &mut *self.as_ptr() }
+     }
+ 
+     /// Casts to a pointer of another type.
+     #[inline]
+     pub const fn cast<U>(self) -> Unique<U> {
+         // SAFETY: Unique::new_unchecked() creates a new unique and needs
+         // the given pointer to not be null.
+         // Since we are passing self as a pointer, it cannot be null.
+         unsafe { Unique::new_unchecked(self.as_ptr() as *mut U) }
+     }
+ }
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> Clone for Unique<T> {
+     #[inline]
+     fn clone(&self) -> Self {
+         *self
+     }
+ }
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> Copy for Unique<T> {}
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized, U: ?Sized> CoerceUnsized<Unique<U>> for Unique<T> where T: Unsize<U> {}
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized, U: ?Sized> DispatchFromDyn<Unique<U>> for Unique<T> where T: Unsize<U> {}
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> fmt::Debug for Unique<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Pointer::fmt(&self.as_ptr(), f)
+     }
+ }
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> fmt::Pointer for Unique<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Pointer::fmt(&self.as_ptr(), f)
+     }
+ }
+ 
+ #[unstable(feature = "ptr_internals", issue = "none")]
+ impl<T: ?Sized> From<&mut T> for Unique<T> {
+     #[inline]
+     fn from(reference: &mut T) -> Self {
+         // SAFETY: A mutable reference cannot be null
+         unsafe { Unique { pointer: reference as *mut T, _marker: PhantomData } }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/raw.rs gcc-16-20251102/libgrust/rustc-lib/core/src/raw.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/raw.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/raw.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,86 ----
+ #![allow(missing_docs)]
+ #![unstable(feature = "raw", issue = "27751")]
+ 
+ //! Contains struct definitions for the layout of compiler built-in types.
+ //!
+ //! They can be used as targets of transmutes in unsafe code for manipulating
+ //! the raw representations directly.
+ //!
+ //! Their definition should always match the ABI defined in
+ //! `rustc_middle::ty::layout`.
+ 
+ /// The representation of a trait object like `&dyn SomeTrait`.
+ ///
+ /// This struct has the same layout as types like `&dyn SomeTrait` and
+ /// `Box<dyn AnotherTrait>`.
+ ///
+ /// `TraitObject` is guaranteed to match layouts, but it is not the
+ /// type of trait objects (e.g., the fields are not directly accessible
+ /// on a `&dyn SomeTrait`) nor does it control that layout (changing the
+ /// definition will not change the layout of a `&dyn SomeTrait`). It is
+ /// only designed to be used by unsafe code that needs to manipulate
+ /// the low-level details.
+ ///
+ /// There is no way to refer to all trait objects generically, so the only
+ /// way to create values of this type is with functions like
+ /// [`std::mem::transmute`][transmute]. Similarly, the only way to create a true
+ /// trait object from a `TraitObject` value is with `transmute`.
+ ///
+ /// [transmute]: crate::intrinsics::transmute
+ ///
+ /// Synthesizing a trait object with mismatched types—one where the
+ /// vtable does not correspond to the type of the value to which the
+ /// data pointer points—is highly likely to lead to undefined
+ /// behavior.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(raw)]
+ ///
+ /// use std::{mem, raw};
+ ///
+ /// // an example trait
+ /// trait Foo {
+ ///     fn bar(&self) -> i32;
+ /// }
+ ///
+ /// impl Foo for i32 {
+ ///     fn bar(&self) -> i32 {
+ ///          *self + 1
+ ///     }
+ /// }
+ ///
+ /// let value: i32 = 123;
+ ///
+ /// // let the compiler make a trait object
+ /// let object: &dyn Foo = &value;
+ ///
+ /// // look at the raw representation
+ /// let raw_object: raw::TraitObject = unsafe { mem::transmute(object) };
+ ///
+ /// // the data pointer is the address of `value`
+ /// assert_eq!(raw_object.data as *const i32, &value as *const _);
+ ///
+ /// let other_value: i32 = 456;
+ ///
+ /// // construct a new object, pointing to a different `i32`, being
+ /// // careful to use the `i32` vtable from `object`
+ /// let synthesized: &dyn Foo = unsafe {
+ ///      mem::transmute(raw::TraitObject {
+ ///          data: &other_value as *const _ as *mut (),
+ ///          vtable: raw_object.vtable,
+ ///      })
+ /// };
+ ///
+ /// // it should work just as if we had constructed a trait object out of
+ /// // `other_value` directly
+ /// assert_eq!(synthesized.bar(), 457);
+ /// ```
+ #[repr(C)]
+ #[derive(Copy, Clone)]
+ #[allow(missing_debug_implementations)]
+ pub struct TraitObject {
+     pub data: *mut (),
+     pub vtable: *mut (),
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/result.rs gcc-16-20251102/libgrust/rustc-lib/core/src/result.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/result.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/result.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1513 ----
+ //! Error handling with the `Result` type.
+ //!
+ //! [`Result<T, E>`][`Result`] is the type used for returning and propagating
+ //! errors. It is an enum with the variants, [`Ok(T)`], representing
+ //! success and containing a value, and [`Err(E)`], representing error
+ //! and containing an error value.
+ //!
+ //! ```
+ //! # #[allow(dead_code)]
+ //! enum Result<T, E> {
+ //!    Ok(T),
+ //!    Err(E),
+ //! }
+ //! ```
+ //!
+ //! Functions return [`Result`] whenever errors are expected and
+ //! recoverable. In the `std` crate, [`Result`] is most prominently used
+ //! for [I/O](../../std/io/index.html).
+ //!
+ //! A simple function returning [`Result`] might be
+ //! defined and used like so:
+ //!
+ //! ```
+ //! #[derive(Debug)]
+ //! enum Version { Version1, Version2 }
+ //!
+ //! fn parse_version(header: &[u8]) -> Result<Version, &'static str> {
+ //!     match header.get(0) {
+ //!         None => Err("invalid header length"),
+ //!         Some(&1) => Ok(Version::Version1),
+ //!         Some(&2) => Ok(Version::Version2),
+ //!         Some(_) => Err("invalid version"),
+ //!     }
+ //! }
+ //!
+ //! let version = parse_version(&[1, 2, 3, 4]);
+ //! match version {
+ //!     Ok(v) => println!("working with version: {:?}", v),
+ //!     Err(e) => println!("error parsing header: {:?}", e),
+ //! }
+ //! ```
+ //!
+ //! Pattern matching on [`Result`]s is clear and straightforward for
+ //! simple cases, but [`Result`] comes with some convenience methods
+ //! that make working with it more succinct.
+ //!
+ //! ```
+ //! let good_result: Result<i32, i32> = Ok(10);
+ //! let bad_result: Result<i32, i32> = Err(10);
+ //!
+ //! // The `is_ok` and `is_err` methods do what they say.
+ //! assert!(good_result.is_ok() && !good_result.is_err());
+ //! assert!(bad_result.is_err() && !bad_result.is_ok());
+ //!
+ //! // `map` consumes the `Result` and produces another.
+ //! let good_result: Result<i32, i32> = good_result.map(|i| i + 1);
+ //! let bad_result: Result<i32, i32> = bad_result.map(|i| i - 1);
+ //!
+ //! // Use `and_then` to continue the computation.
+ //! let good_result: Result<bool, i32> = good_result.and_then(|i| Ok(i == 11));
+ //!
+ //! // Use `or_else` to handle the error.
+ //! let bad_result: Result<i32, i32> = bad_result.or_else(|i| Ok(i + 20));
+ //!
+ //! // Consume the result and return the contents with `unwrap`.
+ //! let final_awesome_result = good_result.unwrap();
+ //! ```
+ //!
+ //! # Results must be used
+ //!
+ //! A common problem with using return values to indicate errors is
+ //! that it is easy to ignore the return value, thus failing to handle
+ //! the error. [`Result`] is annotated with the `#[must_use]` attribute,
+ //! which will cause the compiler to issue a warning when a Result
+ //! value is ignored. This makes [`Result`] especially useful with
+ //! functions that may encounter errors but don't otherwise return a
+ //! useful value.
+ //!
+ //! Consider the [`write_all`] method defined for I/O types
+ //! by the [`Write`] trait:
+ //!
+ //! ```
+ //! use std::io;
+ //!
+ //! trait Write {
+ //!     fn write_all(&mut self, bytes: &[u8]) -> Result<(), io::Error>;
+ //! }
+ //! ```
+ //!
+ //! *Note: The actual definition of [`Write`] uses [`io::Result`], which
+ //! is just a synonym for [`Result`]`<T, `[`io::Error`]`>`.*
+ //!
+ //! This method doesn't produce a value, but the write may
+ //! fail. It's crucial to handle the error case, and *not* write
+ //! something like this:
+ //!
+ //! ```no_run
+ //! # #![allow(unused_must_use)] // \o/
+ //! use std::fs::File;
+ //! use std::io::prelude::*;
+ //!
+ //! let mut file = File::create("valuable_data.txt").unwrap();
+ //! // If `write_all` errors, then we'll never know, because the return
+ //! // value is ignored.
+ //! file.write_all(b"important message");
+ //! ```
+ //!
+ //! If you *do* write that in Rust, the compiler will give you a
+ //! warning (by default, controlled by the `unused_must_use` lint).
+ //!
+ //! You might instead, if you don't want to handle the error, simply
+ //! assert success with [`expect`]. This will panic if the
+ //! write fails, providing a marginally useful message indicating why:
+ //!
+ //! ```{.no_run}
+ //! use std::fs::File;
+ //! use std::io::prelude::*;
+ //!
+ //! let mut file = File::create("valuable_data.txt").unwrap();
+ //! file.write_all(b"important message").expect("failed to write message");
+ //! ```
+ //!
+ //! You might also simply assert success:
+ //!
+ //! ```{.no_run}
+ //! # use std::fs::File;
+ //! # use std::io::prelude::*;
+ //! # let mut file = File::create("valuable_data.txt").unwrap();
+ //! assert!(file.write_all(b"important message").is_ok());
+ //! ```
+ //!
+ //! Or propagate the error up the call stack with [`?`]:
+ //!
+ //! ```
+ //! # use std::fs::File;
+ //! # use std::io::prelude::*;
+ //! # use std::io;
+ //! # #[allow(dead_code)]
+ //! fn write_message() -> io::Result<()> {
+ //!     let mut file = File::create("valuable_data.txt")?;
+ //!     file.write_all(b"important message")?;
+ //!     Ok(())
+ //! }
+ //! ```
+ //!
+ //! # The question mark operator, `?`
+ //!
+ //! When writing code that calls many functions that return the
+ //! [`Result`] type, the error handling can be tedious. The question mark
+ //! operator, [`?`], hides some of the boilerplate of propagating errors
+ //! up the call stack.
+ //!
+ //! It replaces this:
+ //!
+ //! ```
+ //! # #![allow(dead_code)]
+ //! use std::fs::File;
+ //! use std::io::prelude::*;
+ //! use std::io;
+ //!
+ //! struct Info {
+ //!     name: String,
+ //!     age: i32,
+ //!     rating: i32,
+ //! }
+ //!
+ //! fn write_info(info: &Info) -> io::Result<()> {
+ //!     // Early return on error
+ //!     let mut file = match File::create("my_best_friends.txt") {
+ //!            Err(e) => return Err(e),
+ //!            Ok(f) => f,
+ //!     };
+ //!     if let Err(e) = file.write_all(format!("name: {}\n", info.name).as_bytes()) {
+ //!         return Err(e)
+ //!     }
+ //!     if let Err(e) = file.write_all(format!("age: {}\n", info.age).as_bytes()) {
+ //!         return Err(e)
+ //!     }
+ //!     if let Err(e) = file.write_all(format!("rating: {}\n", info.rating).as_bytes()) {
+ //!         return Err(e)
+ //!     }
+ //!     Ok(())
+ //! }
+ //! ```
+ //!
+ //! With this:
+ //!
+ //! ```
+ //! # #![allow(dead_code)]
+ //! use std::fs::File;
+ //! use std::io::prelude::*;
+ //! use std::io;
+ //!
+ //! struct Info {
+ //!     name: String,
+ //!     age: i32,
+ //!     rating: i32,
+ //! }
+ //!
+ //! fn write_info(info: &Info) -> io::Result<()> {
+ //!     let mut file = File::create("my_best_friends.txt")?;
+ //!     // Early return on error
+ //!     file.write_all(format!("name: {}\n", info.name).as_bytes())?;
+ //!     file.write_all(format!("age: {}\n", info.age).as_bytes())?;
+ //!     file.write_all(format!("rating: {}\n", info.rating).as_bytes())?;
+ //!     Ok(())
+ //! }
+ //! ```
+ //!
+ //! *It's much nicer!*
+ //!
+ //! Ending the expression with [`?`] will result in the unwrapped
+ //! success ([`Ok`]) value, unless the result is [`Err`], in which case
+ //! [`Err`] is returned early from the enclosing function.
+ //!
+ //! [`?`] can only be used in functions that return [`Result`] because of the
+ //! early return of [`Err`] that it provides.
+ //!
+ //! [`expect`]: Result::expect
+ //! [`Write`]: ../../std/io/trait.Write.html
+ //! [`write_all`]: ../../std/io/trait.Write.html#method.write_all
+ //! [`io::Result`]: ../../std/io/type.Result.html
+ //! [`?`]: crate::ops::Try
+ //! [`Ok(T)`]: Ok
+ //! [`Err(E)`]: Err
+ //! [`io::Error`]: ../../std/io/struct.Error.html
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::iter::{self, FromIterator, FusedIterator, TrustedLen};
+ use crate::ops::{self, Deref, DerefMut};
+ use crate::{convert, fmt};
+ 
+ /// `Result` is a type that represents either success ([`Ok`]) or failure ([`Err`]).
+ ///
+ /// See the [module documentation](self) for details.
+ #[derive(Copy, PartialEq, PartialOrd, Eq, Ord, Debug, Hash)]
+ #[must_use = "this `Result` may be an `Err` variant, which should be handled"]
+ #[rustc_diagnostic_item = "result_type"]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub enum Result<T, E> {
+     /// Contains the success value
+     #[lang = "Ok"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Ok(#[stable(feature = "rust1", since = "1.0.0")] T),
+ 
+     /// Contains the error value
+     #[lang = "Err"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Err(#[stable(feature = "rust1", since = "1.0.0")] E),
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Type implementation
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ impl<T, E> Result<T, E> {
+     /////////////////////////////////////////////////////////////////////////
+     // Querying the contained values
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns `true` if the result is [`Ok`].
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<i32, &str> = Ok(-3);
+     /// assert_eq!(x.is_ok(), true);
+     ///
+     /// let x: Result<i32, &str> = Err("Some error message");
+     /// assert_eq!(x.is_ok(), false);
+     /// ```
+     #[must_use = "if you intended to assert that this is ok, consider `.unwrap()` instead"]
+     #[rustc_const_stable(feature = "const_result", since = "1.48.0")]
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn is_ok(&self) -> bool {
+         matches!(*self, Ok(_))
+     }
+ 
+     /// Returns `true` if the result is [`Err`].
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<i32, &str> = Ok(-3);
+     /// assert_eq!(x.is_err(), false);
+     ///
+     /// let x: Result<i32, &str> = Err("Some error message");
+     /// assert_eq!(x.is_err(), true);
+     /// ```
+     #[must_use = "if you intended to assert that this is err, consider `.unwrap_err()` instead"]
+     #[rustc_const_stable(feature = "const_result", since = "1.48.0")]
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn is_err(&self) -> bool {
+         !self.is_ok()
+     }
+ 
+     /// Returns `true` if the result is an [`Ok`] value containing the given value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(option_result_contains)]
+     ///
+     /// let x: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.contains(&2), true);
+     ///
+     /// let x: Result<u32, &str> = Ok(3);
+     /// assert_eq!(x.contains(&2), false);
+     ///
+     /// let x: Result<u32, &str> = Err("Some error message");
+     /// assert_eq!(x.contains(&2), false);
+     /// ```
+     #[must_use]
+     #[inline]
+     #[unstable(feature = "option_result_contains", issue = "62358")]
+     pub fn contains<U>(&self, x: &U) -> bool
+     where
+         U: PartialEq<T>,
+     {
+         match self {
+             Ok(y) => x == y,
+             Err(_) => false,
+         }
+     }
+ 
+     /// Returns `true` if the result is an [`Err`] value containing the given value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(result_contains_err)]
+     ///
+     /// let x: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.contains_err(&"Some error message"), false);
+     ///
+     /// let x: Result<u32, &str> = Err("Some error message");
+     /// assert_eq!(x.contains_err(&"Some error message"), true);
+     ///
+     /// let x: Result<u32, &str> = Err("Some other error message");
+     /// assert_eq!(x.contains_err(&"Some error message"), false);
+     /// ```
+     #[must_use]
+     #[inline]
+     #[unstable(feature = "result_contains_err", issue = "62358")]
+     pub fn contains_err<F>(&self, f: &F) -> bool
+     where
+         F: PartialEq<E>,
+     {
+         match self {
+             Ok(_) => false,
+             Err(e) => f == e,
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Adapter for each variant
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Converts from `Result<T, E>` to [`Option<T>`].
+     ///
+     /// Converts `self` into an [`Option<T>`], consuming `self`,
+     /// and discarding the error, if any.
+     ///
+     /// [`Option<T>`]: Option
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.ok(), Some(2));
+     ///
+     /// let x: Result<u32, &str> = Err("Nothing here");
+     /// assert_eq!(x.ok(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn ok(self) -> Option<T> {
+         match self {
+             Ok(x) => Some(x),
+             Err(_) => None,
+         }
+     }
+ 
+     /// Converts from `Result<T, E>` to [`Option<E>`].
+     ///
+     /// Converts `self` into an [`Option<E>`], consuming `self`,
+     /// and discarding the success value, if any.
+     ///
+     /// [`Option<E>`]: Option
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.err(), None);
+     ///
+     /// let x: Result<u32, &str> = Err("Nothing here");
+     /// assert_eq!(x.err(), Some("Nothing here"));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn err(self) -> Option<E> {
+         match self {
+             Ok(_) => None,
+             Err(x) => Some(x),
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Adapter for working with references
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Converts from `&Result<T, E>` to `Result<&T, &E>`.
+     ///
+     /// Produces a new `Result`, containing a reference
+     /// into the original, leaving the original in place.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.as_ref(), Ok(&2));
+     ///
+     /// let x: Result<u32, &str> = Err("Error");
+     /// assert_eq!(x.as_ref(), Err(&"Error"));
+     /// ```
+     #[inline]
+     #[rustc_const_stable(feature = "const_result", since = "1.48.0")]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub const fn as_ref(&self) -> Result<&T, &E> {
+         match *self {
+             Ok(ref x) => Ok(x),
+             Err(ref x) => Err(x),
+         }
+     }
+ 
+     /// Converts from `&mut Result<T, E>` to `Result<&mut T, &mut E>`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// fn mutate(r: &mut Result<i32, i32>) {
+     ///     match r.as_mut() {
+     ///         Ok(v) => *v = 42,
+     ///         Err(e) => *e = 0,
+     ///     }
+     /// }
+     ///
+     /// let mut x: Result<i32, i32> = Ok(2);
+     /// mutate(&mut x);
+     /// assert_eq!(x.unwrap(), 42);
+     ///
+     /// let mut x: Result<i32, i32> = Err(13);
+     /// mutate(&mut x);
+     /// assert_eq!(x.unwrap_err(), 0);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn as_mut(&mut self) -> Result<&mut T, &mut E> {
+         match *self {
+             Ok(ref mut x) => Ok(x),
+             Err(ref mut x) => Err(x),
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Transforming contained values
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Maps a `Result<T, E>` to `Result<U, E>` by applying a function to a
+     /// contained [`Ok`] value, leaving an [`Err`] value untouched.
+     ///
+     /// This function can be used to compose the results of two functions.
+     ///
+     /// # Examples
+     ///
+     /// Print the numbers on each line of a string multiplied by two.
+     ///
+     /// ```
+     /// let line = "1\n2\n3\n4\n";
+     ///
+     /// for num in line.lines() {
+     ///     match num.parse::<i32>().map(|i| i * 2) {
+     ///         Ok(n) => println!("{}", n),
+     ///         Err(..) => {}
+     ///     }
+     /// }
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn map<U, F: FnOnce(T) -> U>(self, op: F) -> Result<U, E> {
+         match self {
+             Ok(t) => Ok(op(t)),
+             Err(e) => Err(e),
+         }
+     }
+ 
+     /// Applies a function to the contained value (if [`Ok`]),
+     /// or returns the provided default (if [`Err`]).
+     ///
+     /// Arguments passed to `map_or` are eagerly evaluated; if you are passing
+     /// the result of a function call, it is recommended to use [`map_or_else`],
+     /// which is lazily evaluated.
+     ///
+     /// [`map_or_else`]: Result::map_or_else
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x: Result<_, &str> = Ok("foo");
+     /// assert_eq!(x.map_or(42, |v| v.len()), 3);
+     ///
+     /// let x: Result<&str, _> = Err("bar");
+     /// assert_eq!(x.map_or(42, |v| v.len()), 42);
+     /// ```
+     #[inline]
+     #[stable(feature = "result_map_or", since = "1.41.0")]
+     pub fn map_or<U, F: FnOnce(T) -> U>(self, default: U, f: F) -> U {
+         match self {
+             Ok(t) => f(t),
+             Err(_) => default,
+         }
+     }
+ 
+     /// Maps a `Result<T, E>` to `U` by applying a function to a
+     /// contained [`Ok`] value, or a fallback function to a
+     /// contained [`Err`] value.
+     ///
+     /// This function can be used to unpack a successful result
+     /// while handling an error.
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let k = 21;
+     ///
+     /// let x : Result<_, &str> = Ok("foo");
+     /// assert_eq!(x.map_or_else(|e| k * 2, |v| v.len()), 3);
+     ///
+     /// let x : Result<&str, _> = Err("bar");
+     /// assert_eq!(x.map_or_else(|e| k * 2, |v| v.len()), 42);
+     /// ```
+     #[inline]
+     #[stable(feature = "result_map_or_else", since = "1.41.0")]
+     pub fn map_or_else<U, D: FnOnce(E) -> U, F: FnOnce(T) -> U>(self, default: D, f: F) -> U {
+         match self {
+             Ok(t) => f(t),
+             Err(e) => default(e),
+         }
+     }
+ 
+     /// Maps a `Result<T, E>` to `Result<T, F>` by applying a function to a
+     /// contained [`Err`] value, leaving an [`Ok`] value untouched.
+     ///
+     /// This function can be used to pass through a successful result while handling
+     /// an error.
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// fn stringify(x: u32) -> String { format!("error code: {}", x) }
+     ///
+     /// let x: Result<u32, u32> = Ok(2);
+     /// assert_eq!(x.map_err(stringify), Ok(2));
+     ///
+     /// let x: Result<u32, u32> = Err(13);
+     /// assert_eq!(x.map_err(stringify), Err("error code: 13".to_string()));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn map_err<F, O: FnOnce(E) -> F>(self, op: O) -> Result<T, F> {
+         match self {
+             Ok(t) => Ok(t),
+             Err(e) => Err(op(e)),
+         }
+     }
+ 
+     /////////////////////////////////////////////////////////////////////////
+     // Iterator constructors
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns an iterator over the possibly contained value.
+     ///
+     /// The iterator yields one value if the result is [`Result::Ok`], otherwise none.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(7);
+     /// assert_eq!(x.iter().next(), Some(&7));
+     ///
+     /// let x: Result<u32, &str> = Err("nothing!");
+     /// assert_eq!(x.iter().next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn iter(&self) -> Iter<'_, T> {
+         Iter { inner: self.as_ref().ok() }
+     }
+ 
+     /// Returns a mutable iterator over the possibly contained value.
+     ///
+     /// The iterator yields one value if the result is [`Result::Ok`], otherwise none.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut x: Result<u32, &str> = Ok(7);
+     /// match x.iter_mut().next() {
+     ///     Some(v) => *v = 40,
+     ///     None => {},
+     /// }
+     /// assert_eq!(x, Ok(40));
+     ///
+     /// let mut x: Result<u32, &str> = Err("nothing!");
+     /// assert_eq!(x.iter_mut().next(), None);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn iter_mut(&mut self) -> IterMut<'_, T> {
+         IterMut { inner: self.as_mut().ok() }
+     }
+ 
+     ////////////////////////////////////////////////////////////////////////
+     // Boolean operations on the values, eager and lazy
+     /////////////////////////////////////////////////////////////////////////
+ 
+     /// Returns `res` if the result is [`Ok`], otherwise returns the [`Err`] value of `self`.
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(2);
+     /// let y: Result<&str, &str> = Err("late error");
+     /// assert_eq!(x.and(y), Err("late error"));
+     ///
+     /// let x: Result<u32, &str> = Err("early error");
+     /// let y: Result<&str, &str> = Ok("foo");
+     /// assert_eq!(x.and(y), Err("early error"));
+     ///
+     /// let x: Result<u32, &str> = Err("not a 2");
+     /// let y: Result<&str, &str> = Err("late error");
+     /// assert_eq!(x.and(y), Err("not a 2"));
+     ///
+     /// let x: Result<u32, &str> = Ok(2);
+     /// let y: Result<&str, &str> = Ok("different result type");
+     /// assert_eq!(x.and(y), Ok("different result type"));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn and<U>(self, res: Result<U, E>) -> Result<U, E> {
+         match self {
+             Ok(_) => res,
+             Err(e) => Err(e),
+         }
+     }
+ 
+     /// Calls `op` if the result is [`Ok`], otherwise returns the [`Err`] value of `self`.
+     ///
+     ///
+     /// This function can be used for control flow based on `Result` values.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// fn sq(x: u32) -> Result<u32, u32> { Ok(x * x) }
+     /// fn err(x: u32) -> Result<u32, u32> { Err(x) }
+     ///
+     /// assert_eq!(Ok(2).and_then(sq).and_then(sq), Ok(16));
+     /// assert_eq!(Ok(2).and_then(sq).and_then(err), Err(4));
+     /// assert_eq!(Ok(2).and_then(err).and_then(sq), Err(2));
+     /// assert_eq!(Err(3).and_then(sq).and_then(sq), Err(3));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn and_then<U, F: FnOnce(T) -> Result<U, E>>(self, op: F) -> Result<U, E> {
+         match self {
+             Ok(t) => op(t),
+             Err(e) => Err(e),
+         }
+     }
+ 
+     /// Returns `res` if the result is [`Err`], otherwise returns the [`Ok`] value of `self`.
+     ///
+     /// Arguments passed to `or` are eagerly evaluated; if you are passing the
+     /// result of a function call, it is recommended to use [`or_else`], which is
+     /// lazily evaluated.
+     ///
+     /// [`or_else`]: Result::or_else
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(2);
+     /// let y: Result<u32, &str> = Err("late error");
+     /// assert_eq!(x.or(y), Ok(2));
+     ///
+     /// let x: Result<u32, &str> = Err("early error");
+     /// let y: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.or(y), Ok(2));
+     ///
+     /// let x: Result<u32, &str> = Err("not a 2");
+     /// let y: Result<u32, &str> = Err("late error");
+     /// assert_eq!(x.or(y), Err("late error"));
+     ///
+     /// let x: Result<u32, &str> = Ok(2);
+     /// let y: Result<u32, &str> = Ok(100);
+     /// assert_eq!(x.or(y), Ok(2));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn or<F>(self, res: Result<T, F>) -> Result<T, F> {
+         match self {
+             Ok(v) => Ok(v),
+             Err(_) => res,
+         }
+     }
+ 
+     /// Calls `op` if the result is [`Err`], otherwise returns the [`Ok`] value of `self`.
+     ///
+     /// This function can be used for control flow based on result values.
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// fn sq(x: u32) -> Result<u32, u32> { Ok(x * x) }
+     /// fn err(x: u32) -> Result<u32, u32> { Err(x) }
+     ///
+     /// assert_eq!(Ok(2).or_else(sq).or_else(sq), Ok(2));
+     /// assert_eq!(Ok(2).or_else(err).or_else(sq), Ok(2));
+     /// assert_eq!(Err(3).or_else(sq).or_else(err), Ok(9));
+     /// assert_eq!(Err(3).or_else(err).or_else(err), Err(3));
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn or_else<F, O: FnOnce(E) -> Result<T, F>>(self, op: O) -> Result<T, F> {
+         match self {
+             Ok(t) => Ok(t),
+             Err(e) => op(e),
+         }
+     }
+ 
+     /// Returns the contained [`Ok`] value or a provided default.
+     ///
+     /// Arguments passed to `unwrap_or` are eagerly evaluated; if you are passing
+     /// the result of a function call, it is recommended to use [`unwrap_or_else`],
+     /// which is lazily evaluated.
+     ///
+     /// [`unwrap_or_else`]: Result::unwrap_or_else
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let default = 2;
+     /// let x: Result<u32, &str> = Ok(9);
+     /// assert_eq!(x.unwrap_or(default), 9);
+     ///
+     /// let x: Result<u32, &str> = Err("error");
+     /// assert_eq!(x.unwrap_or(default), default);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap_or(self, default: T) -> T {
+         match self {
+             Ok(t) => t,
+             Err(_) => default,
+         }
+     }
+ 
+     /// Returns the contained [`Ok`] value or computes it from a closure.
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// fn count(x: &str) -> usize { x.len() }
+     ///
+     /// assert_eq!(Ok(2).unwrap_or_else(count), 2);
+     /// assert_eq!(Err("foo").unwrap_or_else(count), 3);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap_or_else<F: FnOnce(E) -> T>(self, op: F) -> T {
+         match self {
+             Ok(t) => t,
+             Err(e) => op(e),
+         }
+     }
+ }
+ 
+ impl<T: Copy, E> Result<&T, E> {
+     /// Maps a `Result<&T, E>` to a `Result<T, E>` by copying the contents of the
+     /// `Ok` part.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(result_copied)]
+     /// let val = 12;
+     /// let x: Result<&i32, i32> = Ok(&val);
+     /// assert_eq!(x, Ok(&12));
+     /// let copied = x.copied();
+     /// assert_eq!(copied, Ok(12));
+     /// ```
+     #[unstable(feature = "result_copied", reason = "newly added", issue = "63168")]
+     pub fn copied(self) -> Result<T, E> {
+         self.map(|&t| t)
+     }
+ }
+ 
+ impl<T: Copy, E> Result<&mut T, E> {
+     /// Maps a `Result<&mut T, E>` to a `Result<T, E>` by copying the contents of the
+     /// `Ok` part.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(result_copied)]
+     /// let mut val = 12;
+     /// let x: Result<&mut i32, i32> = Ok(&mut val);
+     /// assert_eq!(x, Ok(&mut 12));
+     /// let copied = x.copied();
+     /// assert_eq!(copied, Ok(12));
+     /// ```
+     #[unstable(feature = "result_copied", reason = "newly added", issue = "63168")]
+     pub fn copied(self) -> Result<T, E> {
+         self.map(|&mut t| t)
+     }
+ }
+ 
+ impl<T: Clone, E> Result<&T, E> {
+     /// Maps a `Result<&T, E>` to a `Result<T, E>` by cloning the contents of the
+     /// `Ok` part.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(result_cloned)]
+     /// let val = 12;
+     /// let x: Result<&i32, i32> = Ok(&val);
+     /// assert_eq!(x, Ok(&12));
+     /// let cloned = x.cloned();
+     /// assert_eq!(cloned, Ok(12));
+     /// ```
+     #[unstable(feature = "result_cloned", reason = "newly added", issue = "63168")]
+     pub fn cloned(self) -> Result<T, E> {
+         self.map(|t| t.clone())
+     }
+ }
+ 
+ impl<T: Clone, E> Result<&mut T, E> {
+     /// Maps a `Result<&mut T, E>` to a `Result<T, E>` by cloning the contents of the
+     /// `Ok` part.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(result_cloned)]
+     /// let mut val = 12;
+     /// let x: Result<&mut i32, i32> = Ok(&mut val);
+     /// assert_eq!(x, Ok(&mut 12));
+     /// let cloned = x.cloned();
+     /// assert_eq!(cloned, Ok(12));
+     /// ```
+     #[unstable(feature = "result_cloned", reason = "newly added", issue = "63168")]
+     pub fn cloned(self) -> Result<T, E> {
+         self.map(|t| t.clone())
+     }
+ }
+ 
+ impl<T, E: fmt::Debug> Result<T, E> {
+     /// Returns the contained [`Ok`] value, consuming the `self` value.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is an [`Err`], with a panic message including the
+     /// passed message, and the content of the [`Err`].
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```{.should_panic}
+     /// let x: Result<u32, &str> = Err("emergency failure");
+     /// x.expect("Testing expect"); // panics with `Testing expect: emergency failure`
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[stable(feature = "result_expect", since = "1.4.0")]
+     pub fn expect(self, msg: &str) -> T {
+         match self {
+             Ok(t) => t,
+             Err(e) => unwrap_failed(msg, &e),
+         }
+     }
+ 
+     /// Returns the contained [`Ok`] value, consuming the `self` value.
+     ///
+     /// Because this function may panic, its use is generally discouraged.
+     /// Instead, prefer to use pattern matching and handle the [`Err`]
+     /// case explicitly, or call [`unwrap_or`], [`unwrap_or_else`], or
+     /// [`unwrap_or_default`].
+     ///
+     /// [`unwrap_or`]: Result::unwrap_or
+     /// [`unwrap_or_else`]: Result::unwrap_or_else
+     /// [`unwrap_or_default`]: Result::unwrap_or_default
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is an [`Err`], with a panic message provided by the
+     /// [`Err`]'s value.
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(2);
+     /// assert_eq!(x.unwrap(), 2);
+     /// ```
+     ///
+     /// ```{.should_panic}
+     /// let x: Result<u32, &str> = Err("emergency failure");
+     /// x.unwrap(); // panics with `emergency failure`
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap(self) -> T {
+         match self {
+             Ok(t) => t,
+             Err(e) => unwrap_failed("called `Result::unwrap()` on an `Err` value", &e),
+         }
+     }
+ }
+ 
+ impl<T: fmt::Debug, E> Result<T, E> {
+     /// Returns the contained [`Err`] value, consuming the `self` value.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is an [`Ok`], with a panic message including the
+     /// passed message, and the content of the [`Ok`].
+     ///
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```{.should_panic}
+     /// let x: Result<u32, &str> = Ok(10);
+     /// x.expect_err("Testing expect_err"); // panics with `Testing expect_err: 10`
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[stable(feature = "result_expect_err", since = "1.17.0")]
+     pub fn expect_err(self, msg: &str) -> E {
+         match self {
+             Ok(t) => unwrap_failed(msg, &t),
+             Err(e) => e,
+         }
+     }
+ 
+     /// Returns the contained [`Err`] value, consuming the `self` value.
+     ///
+     /// # Panics
+     ///
+     /// Panics if the value is an [`Ok`], with a custom panic message provided
+     /// by the [`Ok`]'s value.
+     ///
+     ///
+     ///
+     /// # Examples
+     ///
+     /// ```{.should_panic}
+     /// let x: Result<u32, &str> = Ok(2);
+     /// x.unwrap_err(); // panics with `2`
+     /// ```
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Err("emergency failure");
+     /// assert_eq!(x.unwrap_err(), "emergency failure");
+     /// ```
+     #[inline]
+     #[track_caller]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn unwrap_err(self) -> E {
+         match self {
+             Ok(t) => unwrap_failed("called `Result::unwrap_err()` on an `Ok` value", &t),
+             Err(e) => e,
+         }
+     }
+ }
+ 
+ impl<T: Default, E> Result<T, E> {
+     /// Returns the contained [`Ok`] value or a default
+     ///
+     /// Consumes the `self` argument then, if [`Ok`], returns the contained
+     /// value, otherwise if [`Err`], returns the default value for that
+     /// type.
+     ///
+     /// # Examples
+     ///
+     /// Converts a string to an integer, turning poorly-formed strings
+     /// into 0 (the default value for integers). [`parse`] converts
+     /// a string to any other type that implements [`FromStr`], returning an
+     /// [`Err`] on error.
+     ///
+     /// ```
+     /// let good_year_from_input = "1909";
+     /// let bad_year_from_input = "190blarg";
+     /// let good_year = good_year_from_input.parse().unwrap_or_default();
+     /// let bad_year = bad_year_from_input.parse().unwrap_or_default();
+     ///
+     /// assert_eq!(1909, good_year);
+     /// assert_eq!(0, bad_year);
+     /// ```
+     ///
+     /// [`parse`]: str::parse
+     /// [`FromStr`]: crate::str::FromStr
+     #[inline]
+     #[stable(feature = "result_unwrap_or_default", since = "1.16.0")]
+     pub fn unwrap_or_default(self) -> T {
+         match self {
+             Ok(x) => x,
+             Err(_) => Default::default(),
+         }
+     }
+ }
+ 
+ #[unstable(feature = "unwrap_infallible", reason = "newly added", issue = "61695")]
+ impl<T, E: Into<!>> Result<T, E> {
+     /// Returns the contained [`Ok`] value, but never panics.
+     ///
+     /// Unlike [`unwrap`], this method is known to never panic on the
+     /// result types it is implemented for. Therefore, it can be used
+     /// instead of `unwrap` as a maintainability safeguard that will fail
+     /// to compile if the error type of the `Result` is later changed
+     /// to an error that can actually occur.
+     ///
+     /// [`unwrap`]: Result::unwrap
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// # #![feature(never_type)]
+     /// # #![feature(unwrap_infallible)]
+     ///
+     /// fn only_good_news() -> Result<String, !> {
+     ///     Ok("this is fine".into())
+     /// }
+     ///
+     /// let s: String = only_good_news().into_ok();
+     /// println!("{}", s);
+     /// ```
+     #[inline]
+     pub fn into_ok(self) -> T {
+         match self {
+             Ok(x) => x,
+             Err(e) => e.into(),
+         }
+     }
+ }
+ 
+ impl<T: Deref, E> Result<T, E> {
+     /// Converts from `Result<T, E>` (or `&Result<T, E>`) to `Result<&<T as Deref>::Target, &E>`.
+     ///
+     /// Coerces the [`Ok`] variant of the original [`Result`] via [`Deref`](crate::ops::Deref)
+     /// and returns the new [`Result`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x: Result<String, u32> = Ok("hello".to_string());
+     /// let y: Result<&str, &u32> = Ok("hello");
+     /// assert_eq!(x.as_deref(), y);
+     ///
+     /// let x: Result<String, u32> = Err(42);
+     /// let y: Result<&str, &u32> = Err(&42);
+     /// assert_eq!(x.as_deref(), y);
+     /// ```
+     #[stable(feature = "inner_deref", since = "1.47.0")]
+     pub fn as_deref(&self) -> Result<&T::Target, &E> {
+         self.as_ref().map(|t| t.deref())
+     }
+ }
+ 
+ impl<T: DerefMut, E> Result<T, E> {
+     /// Converts from `Result<T, E>` (or `&mut Result<T, E>`) to `Result<&mut <T as DerefMut>::Target, &mut E>`.
+     ///
+     /// Coerces the [`Ok`] variant of the original [`Result`] via [`DerefMut`](crate::ops::DerefMut)
+     /// and returns the new [`Result`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut s = "HELLO".to_string();
+     /// let mut x: Result<String, u32> = Ok("hello".to_string());
+     /// let y: Result<&mut str, &mut u32> = Ok(&mut s);
+     /// assert_eq!(x.as_deref_mut().map(|x| { x.make_ascii_uppercase(); x }), y);
+     ///
+     /// let mut i = 42;
+     /// let mut x: Result<String, u32> = Err(42);
+     /// let y: Result<&mut str, &mut u32> = Err(&mut i);
+     /// assert_eq!(x.as_deref_mut().map(|x| { x.make_ascii_uppercase(); x }), y);
+     /// ```
+     #[stable(feature = "inner_deref", since = "1.47.0")]
+     pub fn as_deref_mut(&mut self) -> Result<&mut T::Target, &mut E> {
+         self.as_mut().map(|t| t.deref_mut())
+     }
+ }
+ 
+ impl<T, E> Result<Option<T>, E> {
+     /// Transposes a `Result` of an `Option` into an `Option` of a `Result`.
+     ///
+     /// `Ok(None)` will be mapped to `None`.
+     /// `Ok(Some(_))` and `Err(_)` will be mapped to `Some(Ok(_))` and `Some(Err(_))`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[derive(Debug, Eq, PartialEq)]
+     /// struct SomeErr;
+     ///
+     /// let x: Result<Option<i32>, SomeErr> = Ok(Some(5));
+     /// let y: Option<Result<i32, SomeErr>> = Some(Ok(5));
+     /// assert_eq!(x.transpose(), y);
+     /// ```
+     #[inline]
+     #[stable(feature = "transpose_result", since = "1.33.0")]
+     pub fn transpose(self) -> Option<Result<T, E>> {
+         match self {
+             Ok(Some(x)) => Some(Ok(x)),
+             Ok(None) => None,
+             Err(e) => Some(Err(e)),
+         }
+     }
+ }
+ 
+ impl<T, E> Result<Result<T, E>, E> {
+     /// Converts from `Result<Result<T, E>, E>` to `Result<T, E>`
+     ///
+     /// # Examples
+     /// Basic usage:
+     /// ```
+     /// #![feature(result_flattening)]
+     /// let x: Result<Result<&'static str, u32>, u32> = Ok(Ok("hello"));
+     /// assert_eq!(Ok("hello"), x.flatten());
+     ///
+     /// let x: Result<Result<&'static str, u32>, u32> = Ok(Err(6));
+     /// assert_eq!(Err(6), x.flatten());
+     ///
+     /// let x: Result<Result<&'static str, u32>, u32> = Err(6);
+     /// assert_eq!(Err(6), x.flatten());
+     /// ```
+     ///
+     /// Flattening once only removes one level of nesting:
+     ///
+     /// ```
+     /// #![feature(result_flattening)]
+     /// let x: Result<Result<Result<&'static str, u32>, u32>, u32> = Ok(Ok(Ok("hello")));
+     /// assert_eq!(Ok(Ok("hello")), x.flatten());
+     /// assert_eq!(Ok("hello"), x.flatten().flatten());
+     /// ```
+     #[inline]
+     #[unstable(feature = "result_flattening", issue = "70142")]
+     pub fn flatten(self) -> Result<T, E> {
+         self.and_then(convert::identity)
+     }
+ }
+ 
+ // This is a separate function to reduce the code size of the methods
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ fn unwrap_failed(msg: &str, error: &dyn fmt::Debug) -> ! {
+     panic!("{}: {:?}", msg, error)
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Trait implementations
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Clone, E: Clone> Clone for Result<T, E> {
+     #[inline]
+     fn clone(&self) -> Self {
+         match self {
+             Ok(x) => Ok(x.clone()),
+             Err(x) => Err(x.clone()),
+         }
+     }
+ 
+     #[inline]
+     fn clone_from(&mut self, source: &Self) {
+         match (self, source) {
+             (Ok(to), Ok(from)) => to.clone_from(from),
+             (Err(to), Err(from)) => to.clone_from(from),
+             (to, from) => *to = from.clone(),
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, E> IntoIterator for Result<T, E> {
+     type Item = T;
+     type IntoIter = IntoIter<T>;
+ 
+     /// Returns a consuming iterator over the possibly contained value.
+     ///
+     /// The iterator yields one value if the result is [`Result::Ok`], otherwise none.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let x: Result<u32, &str> = Ok(5);
+     /// let v: Vec<u32> = x.into_iter().collect();
+     /// assert_eq!(v, [5]);
+     ///
+     /// let x: Result<u32, &str> = Err("nothing!");
+     /// let v: Vec<u32> = x.into_iter().collect();
+     /// assert_eq!(v, []);
+     /// ```
+     #[inline]
+     fn into_iter(self) -> IntoIter<T> {
+         IntoIter { inner: self.ok() }
+     }
+ }
+ 
+ #[stable(since = "1.4.0", feature = "result_iter")]
+ impl<'a, T, E> IntoIterator for &'a Result<T, E> {
+     type Item = &'a T;
+     type IntoIter = Iter<'a, T>;
+ 
+     fn into_iter(self) -> Iter<'a, T> {
+         self.iter()
+     }
+ }
+ 
+ #[stable(since = "1.4.0", feature = "result_iter")]
+ impl<'a, T, E> IntoIterator for &'a mut Result<T, E> {
+     type Item = &'a mut T;
+     type IntoIter = IterMut<'a, T>;
+ 
+     fn into_iter(self) -> IterMut<'a, T> {
+         self.iter_mut()
+     }
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // The Result Iterators
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ /// An iterator over a reference to the [`Ok`] variant of a [`Result`].
+ ///
+ /// The iterator yields one value if the result is [`Ok`], otherwise none.
+ ///
+ /// Created by [`Result::iter`].
+ #[derive(Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Iter<'a, T: 'a> {
+     inner: Option<&'a T>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> Iterator for Iter<'a, T> {
+     type Item = &'a T;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a T> {
+         self.inner.take()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = if self.inner.is_some() { 1 } else { 0 };
+         (n, Some(n))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> DoubleEndedIterator for Iter<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a T> {
+         self.inner.take()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> ExactSizeIterator for Iter<'_, T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for Iter<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A> TrustedLen for Iter<'_, A> {}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Clone for Iter<'_, T> {
+     #[inline]
+     fn clone(&self) -> Self {
+         Iter { inner: self.inner }
+     }
+ }
+ 
+ /// An iterator over a mutable reference to the [`Ok`] variant of a [`Result`].
+ ///
+ /// Created by [`Result::iter_mut`].
+ #[derive(Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct IterMut<'a, T: 'a> {
+     inner: Option<&'a mut T>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> Iterator for IterMut<'a, T> {
+     type Item = &'a mut T;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut T> {
+         self.inner.take()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = if self.inner.is_some() { 1 } else { 0 };
+         (n, Some(n))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> DoubleEndedIterator for IterMut<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut T> {
+         self.inner.take()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> ExactSizeIterator for IterMut<'_, T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for IterMut<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A> TrustedLen for IterMut<'_, A> {}
+ 
+ /// An iterator over the value in a [`Ok`] variant of a [`Result`].
+ ///
+ /// The iterator yields one value if the result is [`Ok`], otherwise none.
+ ///
+ /// This struct is created by the [`into_iter`] method on
+ /// [`Result`] (provided by the [`IntoIterator`] trait).
+ ///
+ /// [`into_iter`]: IntoIterator::into_iter
+ #[derive(Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct IntoIter<T> {
+     inner: Option<T>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Iterator for IntoIter<T> {
+     type Item = T;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<T> {
+         self.inner.take()
+     }
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = if self.inner.is_some() { 1 } else { 0 };
+         (n, Some(n))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> DoubleEndedIterator for IntoIter<T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<T> {
+         self.inner.take()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> ExactSizeIterator for IntoIter<T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for IntoIter<T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<A> TrustedLen for IntoIter<A> {}
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // FromIterator
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, E, V: FromIterator<A>> FromIterator<Result<A, E>> for Result<V, E> {
+     /// Takes each element in the `Iterator`: if it is an `Err`, no further
+     /// elements are taken, and the `Err` is returned. Should no `Err` occur, a
+     /// container with the values of each `Result` is returned.
+     ///
+     /// Here is an example which increments every integer in a vector,
+     /// checking for overflow:
+     ///
+     /// ```
+     /// let v = vec![1, 2];
+     /// let res: Result<Vec<u32>, &'static str> = v.iter().map(|x: &u32|
+     ///     x.checked_add(1).ok_or("Overflow!")
+     /// ).collect();
+     /// assert_eq!(res, Ok(vec![2, 3]));
+     /// ```
+     ///
+     /// Here is another example that tries to subtract one from another list
+     /// of integers, this time checking for underflow:
+     ///
+     /// ```
+     /// let v = vec![1, 2, 0];
+     /// let res: Result<Vec<u32>, &'static str> = v.iter().map(|x: &u32|
+     ///     x.checked_sub(1).ok_or("Underflow!")
+     /// ).collect();
+     /// assert_eq!(res, Err("Underflow!"));
+     /// ```
+     ///
+     /// Here is a variation on the previous example, showing that no
+     /// further elements are taken from `iter` after the first `Err`.
+     ///
+     /// ```
+     /// let v = vec![3, 2, 1, 10];
+     /// let mut shared = 0;
+     /// let res: Result<Vec<u32>, &'static str> = v.iter().map(|x: &u32| {
+     ///     shared += x;
+     ///     x.checked_sub(2).ok_or("Underflow!")
+     /// }).collect();
+     /// assert_eq!(res, Err("Underflow!"));
+     /// assert_eq!(shared, 6);
+     /// ```
+     ///
+     /// Since the third element caused an underflow, no further elements were taken,
+     /// so the final value of `shared` is 6 (= `3 + 2 + 1`), not 16.
+     #[inline]
+     fn from_iter<I: IntoIterator<Item = Result<A, E>>>(iter: I) -> Result<V, E> {
+         // FIXME(#11084): This could be replaced with Iterator::scan when this
+         // performance bug is closed.
+ 
+         iter::process_results(iter.into_iter(), |i| i.collect())
+     }
+ }
+ 
+ #[unstable(feature = "try_trait", issue = "42327")]
+ impl<T, E> ops::Try for Result<T, E> {
+     type Ok = T;
+     type Error = E;
+ 
+     #[inline]
+     fn into_result(self) -> Self {
+         self
+     }
+ 
+     #[inline]
+     fn from_ok(v: T) -> Self {
+         Ok(v)
+     }
+ 
+     #[inline]
+     fn from_error(v: E) -> Self {
+         Err(v)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/ascii.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/ascii.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/ascii.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/ascii.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,156 ----
+ //! Operations on ASCII `[u8]`.
+ 
+ use crate::mem;
+ 
+ #[lang = "slice_u8"]
+ #[cfg(not(test))]
+ impl [u8] {
+     /// Checks if all bytes in this slice are within the ASCII range.
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn is_ascii(&self) -> bool {
+         is_ascii(self)
+     }
+ 
+     /// Checks that two slices are an ASCII case-insensitive match.
+     ///
+     /// Same as `to_ascii_lowercase(a) == to_ascii_lowercase(b)`,
+     /// but without allocating and copying temporaries.
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn eq_ignore_ascii_case(&self, other: &[u8]) -> bool {
+         self.len() == other.len() && self.iter().zip(other).all(|(a, b)| a.eq_ignore_ascii_case(b))
+     }
+ 
+     /// Converts this slice to its ASCII upper case equivalent in-place.
+     ///
+     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new uppercased value without modifying the existing one, use
+     /// [`to_ascii_uppercase`].
+     ///
+     /// [`to_ascii_uppercase`]: #method.to_ascii_uppercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_uppercase(&mut self) {
+         for byte in self {
+             byte.make_ascii_uppercase();
+         }
+     }
+ 
+     /// Converts this slice to its ASCII lower case equivalent in-place.
+     ///
+     /// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new lowercased value without modifying the existing one, use
+     /// [`to_ascii_lowercase`].
+     ///
+     /// [`to_ascii_lowercase`]: #method.to_ascii_lowercase
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_lowercase(&mut self) {
+         for byte in self {
+             byte.make_ascii_lowercase();
+         }
+     }
+ }
+ 
+ /// Returns `true` if any byte in the word `v` is nonascii (>= 128). Snarfed
+ /// from `../str/mod.rs`, which does something similar for utf8 validation.
+ #[inline]
+ fn contains_nonascii(v: usize) -> bool {
+     const NONASCII_MASK: usize = 0x80808080_80808080u64 as usize;
+     (NONASCII_MASK & v) != 0
+ }
+ 
+ /// Optimized ASCII test that will use usize-at-a-time operations instead of
+ /// byte-at-a-time operations (when possible).
+ ///
+ /// The algorithm we use here is pretty simple. If `s` is too short, we just
+ /// check each byte and be done with it. Otherwise:
+ ///
+ /// - Read the first word with an unaligned load.
+ /// - Align the pointer, read subsequent words until end with aligned loads.
+ /// - Read the last `usize` from `s` with an unaligned load.
+ ///
+ /// If any of these loads produces something for which `contains_nonascii`
+ /// (above) returns true, then we know the answer is false.
+ #[inline]
+ fn is_ascii(s: &[u8]) -> bool {
+     const USIZE_SIZE: usize = mem::size_of::<usize>();
+ 
+     let len = s.len();
+     let align_offset = s.as_ptr().align_offset(USIZE_SIZE);
+ 
+     // If we wouldn't gain anything from the word-at-a-time implementation, fall
+     // back to a scalar loop.
+     //
+     // We also do this for architectures where `size_of::<usize>()` isn't
+     // sufficient alignment for `usize`, because it's a weird edge case.
+     if len < USIZE_SIZE || len < align_offset || USIZE_SIZE < mem::align_of::<usize>() {
+         return s.iter().all(|b| b.is_ascii());
+     }
+ 
+     // We always read the first word unaligned, which means `align_offset` is
+     // 0, we'd read the same value again for the aligned read.
+     let offset_to_aligned = if align_offset == 0 { USIZE_SIZE } else { align_offset };
+ 
+     let start = s.as_ptr();
+     // SAFETY: We verify `len < USIZE_SIZE` above.
+     let first_word = unsafe { (start as *const usize).read_unaligned() };
+ 
+     if contains_nonascii(first_word) {
+         return false;
+     }
+     // We checked this above, somewhat implicitly. Note that `offset_to_aligned`
+     // is either `align_offset` or `USIZE_SIZE`, both of are explicitly checked
+     // above.
+     debug_assert!(offset_to_aligned <= len);
+ 
+     // SAFETY: word_ptr is the (properly aligned) usize ptr we use to read the
+     // middle chunk of the slice.
+     let mut word_ptr = unsafe { start.add(offset_to_aligned) as *const usize };
+ 
+     // `byte_pos` is the byte index of `word_ptr`, used for loop end checks.
+     let mut byte_pos = offset_to_aligned;
+ 
+     // Paranoia check about alignment, since we're about to do a bunch of
+     // unaligned loads. In practice this should be impossible barring a bug in
+     // `align_offset` though.
+     debug_assert_eq!((word_ptr as usize) % mem::align_of::<usize>(), 0);
+ 
+     // Read subsequent words until the last aligned word, excluding the last
+     // aligned word by itself to be done in tail check later, to ensure that
+     // tail is always one `usize` at most to extra branch `byte_pos == len`.
+     while byte_pos < len - USIZE_SIZE {
+         debug_assert!(
+             // Sanity check that the read is in bounds
+             (word_ptr as usize + USIZE_SIZE) <= (start.wrapping_add(len) as usize) &&
+             // And that our assumptions about `byte_pos` hold.
+             (word_ptr as usize) - (start as usize) == byte_pos
+         );
+ 
+         // SAFETY: We know `word_ptr` is properly aligned (because of
+         // `align_offset`), and we know that we have enough bytes between `word_ptr` and the end
+         let word = unsafe { word_ptr.read() };
+         if contains_nonascii(word) {
+             return false;
+         }
+ 
+         byte_pos += USIZE_SIZE;
+         // SAFETY: We know that `byte_pos <= len - USIZE_SIZE`, which means that
+         // after this `add`, `word_ptr` will be at most one-past-the-end.
+         word_ptr = unsafe { word_ptr.add(1) };
+     }
+ 
+     // Sanity check to ensure there really is only one `usize` left. This should
+     // be guaranteed by our loop condition.
+     debug_assert!(byte_pos <= len && len - byte_pos <= USIZE_SIZE);
+ 
+     // SAFETY: This relies on `len >= USIZE_SIZE`, which we check at the start.
+     let last_word = unsafe { (start.add(len - USIZE_SIZE) as *const usize).read_unaligned() };
+ 
+     !contains_nonascii(last_word)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/cmp.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/cmp.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/cmp.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/cmp.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,288 ----
+ //! Comparison traits for `[T]`.
+ 
+ use crate::cmp;
+ use crate::cmp::Ordering::{self, Greater, Less};
+ use crate::mem;
+ 
+ use super::from_raw_parts;
+ use super::memchr;
+ 
+ extern "C" {
+     /// Calls implementation provided memcmp.
+     ///
+     /// Interprets the data as u8.
+     ///
+     /// Returns 0 for equal, < 0 for less than and > 0 for greater
+     /// than.
+     // FIXME(#32610): Return type should be c_int
+     fn memcmp(s1: *const u8, s2: *const u8, n: usize) -> i32;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<A, B> PartialEq<[B]> for [A]
+ where
+     A: PartialEq<B>,
+ {
+     fn eq(&self, other: &[B]) -> bool {
+         SlicePartialEq::equal(self, other)
+     }
+ 
+     fn ne(&self, other: &[B]) -> bool {
+         SlicePartialEq::not_equal(self, other)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Eq> Eq for [T] {}
+ 
+ /// Implements comparison of vectors [lexicographically](Ord#lexicographical-comparison).
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: Ord> Ord for [T] {
+     fn cmp(&self, other: &[T]) -> Ordering {
+         SliceOrd::compare(self, other)
+     }
+ }
+ 
+ /// Implements comparison of vectors [lexicographically](Ord#lexicographical-comparison).
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T: PartialOrd> PartialOrd for [T] {
+     fn partial_cmp(&self, other: &[T]) -> Option<Ordering> {
+         SlicePartialOrd::partial_compare(self, other)
+     }
+ }
+ 
+ #[doc(hidden)]
+ // intermediate trait for specialization of slice's PartialEq
+ trait SlicePartialEq<B> {
+     fn equal(&self, other: &[B]) -> bool;
+ 
+     fn not_equal(&self, other: &[B]) -> bool {
+         !self.equal(other)
+     }
+ }
+ 
+ // Generic slice equality
+ impl<A, B> SlicePartialEq<B> for [A]
+ where
+     A: PartialEq<B>,
+ {
+     default fn equal(&self, other: &[B]) -> bool {
+         if self.len() != other.len() {
+             return false;
+         }
+ 
+         self.iter().zip(other.iter()).all(|(x, y)| x == y)
+     }
+ }
+ 
+ // Use an equal-pointer optimization when types are `Eq`
+ // We can't make `A` and `B` the same type because `min_specialization` won't
+ // allow it.
+ impl<A, B> SlicePartialEq<B> for [A]
+ where
+     A: MarkerEq<B>,
+ {
+     default fn equal(&self, other: &[B]) -> bool {
+         if self.len() != other.len() {
+             return false;
+         }
+ 
+         // While performance would suffer if `guaranteed_eq` just returned `false`
+         // for all arguments, correctness and return value of this function are not affected.
+         if self.as_ptr().guaranteed_eq(other.as_ptr() as *const A) {
+             return true;
+         }
+ 
+         self.iter().zip(other.iter()).all(|(x, y)| x == y)
+     }
+ }
+ 
+ // Use memcmp for bytewise equality when the types allow
+ impl<A, B> SlicePartialEq<B> for [A]
+ where
+     A: BytewiseEquality<B>,
+ {
+     fn equal(&self, other: &[B]) -> bool {
+         if self.len() != other.len() {
+             return false;
+         }
+ 
+         // While performance would suffer if `guaranteed_eq` just returned `false`
+         // for all arguments, correctness and return value of this function are not affected.
+         if self.as_ptr().guaranteed_eq(other.as_ptr() as *const A) {
+             return true;
+         }
+         // SAFETY: `self` and `other` are references and are thus guaranteed to be valid.
+         // The two slices have been checked to have the same size above.
+         unsafe {
+             let size = mem::size_of_val(self);
+             memcmp(self.as_ptr() as *const u8, other.as_ptr() as *const u8, size) == 0
+         }
+     }
+ }
+ 
+ #[doc(hidden)]
+ // intermediate trait for specialization of slice's PartialOrd
+ trait SlicePartialOrd: Sized {
+     fn partial_compare(left: &[Self], right: &[Self]) -> Option<Ordering>;
+ }
+ 
+ impl<A: PartialOrd> SlicePartialOrd for A {
+     default fn partial_compare(left: &[A], right: &[A]) -> Option<Ordering> {
+         let l = cmp::min(left.len(), right.len());
+ 
+         // Slice to the loop iteration range to enable bound check
+         // elimination in the compiler
+         let lhs = &left[..l];
+         let rhs = &right[..l];
+ 
+         for i in 0..l {
+             match lhs[i].partial_cmp(&rhs[i]) {
+                 Some(Ordering::Equal) => (),
+                 non_eq => return non_eq,
+             }
+         }
+ 
+         left.len().partial_cmp(&right.len())
+     }
+ }
+ 
+ // This is the impl that we would like to have. Unfortunately it's not sound.
+ // See `partial_ord_slice.rs`.
+ /*
+ impl<A> SlicePartialOrd for A
+ where
+     A: Ord,
+ {
+     default fn partial_compare(left: &[A], right: &[A]) -> Option<Ordering> {
+         Some(SliceOrd::compare(left, right))
+     }
+ }
+ */
+ 
+ impl<A: AlwaysApplicableOrd> SlicePartialOrd for A {
+     fn partial_compare(left: &[A], right: &[A]) -> Option<Ordering> {
+         Some(SliceOrd::compare(left, right))
+     }
+ }
+ 
+ #[rustc_specialization_trait]
+ trait AlwaysApplicableOrd: SliceOrd + Ord {}
+ 
+ macro_rules! always_applicable_ord {
+     ($([$($p:tt)*] $t:ty,)*) => {
+         $(impl<$($p)*> AlwaysApplicableOrd for $t {})*
+     }
+ }
+ 
+ always_applicable_ord! {
+     [] u8, [] u16, [] u32, [] u64, [] u128, [] usize,
+     [] i8, [] i16, [] i32, [] i64, [] i128, [] isize,
+     [] bool, [] char,
+     [T: ?Sized] *const T, [T: ?Sized] *mut T,
+     [T: AlwaysApplicableOrd] &T,
+     [T: AlwaysApplicableOrd] &mut T,
+     [T: AlwaysApplicableOrd] Option<T>,
+ }
+ 
+ #[doc(hidden)]
+ // intermediate trait for specialization of slice's Ord
+ trait SliceOrd: Sized {
+     fn compare(left: &[Self], right: &[Self]) -> Ordering;
+ }
+ 
+ impl<A: Ord> SliceOrd for A {
+     default fn compare(left: &[Self], right: &[Self]) -> Ordering {
+         let l = cmp::min(left.len(), right.len());
+ 
+         // Slice to the loop iteration range to enable bound check
+         // elimination in the compiler
+         let lhs = &left[..l];
+         let rhs = &right[..l];
+ 
+         for i in 0..l {
+             match lhs[i].cmp(&rhs[i]) {
+                 Ordering::Equal => (),
+                 non_eq => return non_eq,
+             }
+         }
+ 
+         left.len().cmp(&right.len())
+     }
+ }
+ 
+ // memcmp compares a sequence of unsigned bytes lexicographically.
+ // this matches the order we want for [u8], but no others (not even [i8]).
+ impl SliceOrd for u8 {
+     #[inline]
+     fn compare(left: &[Self], right: &[Self]) -> Ordering {
+         let order =
+             // SAFETY: `left` and `right` are references and are thus guaranteed to be valid.
+             // We use the minimum of both lengths which guarantees that both regions are
+             // valid for reads in that interval.
+             unsafe { memcmp(left.as_ptr(), right.as_ptr(), cmp::min(left.len(), right.len())) };
+         if order == 0 {
+             left.len().cmp(&right.len())
+         } else if order < 0 {
+             Less
+         } else {
+             Greater
+         }
+     }
+ }
+ 
+ // Hack to allow specializing on `Eq` even though `Eq` has a method.
+ #[rustc_unsafe_specialization_marker]
+ trait MarkerEq<T>: PartialEq<T> {}
+ 
+ impl<T: Eq> MarkerEq<T> for T {}
+ 
+ #[doc(hidden)]
+ /// Trait implemented for types that can be compared for equality using
+ /// their bytewise representation
+ #[rustc_specialization_trait]
+ trait BytewiseEquality<T>: MarkerEq<T> + Copy {}
+ 
+ macro_rules! impl_marker_for {
+     ($traitname:ident, $($ty:ty)*) => {
+         $(
+             impl $traitname<$ty> for $ty { }
+         )*
+     }
+ }
+ 
+ impl_marker_for!(BytewiseEquality,
+                  u8 i8 u16 i16 u32 i32 u64 i64 u128 i128 usize isize char bool);
+ 
+ pub(super) trait SliceContains: Sized {
+     fn slice_contains(&self, x: &[Self]) -> bool;
+ }
+ 
+ impl<T> SliceContains for T
+ where
+     T: PartialEq,
+ {
+     default fn slice_contains(&self, x: &[Self]) -> bool {
+         x.iter().any(|y| *y == *self)
+     }
+ }
+ 
+ impl SliceContains for u8 {
+     #[inline]
+     fn slice_contains(&self, x: &[Self]) -> bool {
+         memchr::memchr(*self, x).is_some()
+     }
+ }
+ 
+ impl SliceContains for i8 {
+     #[inline]
+     fn slice_contains(&self, x: &[Self]) -> bool {
+         let byte = *self as u8;
+         // SAFETY: `i8` and `u8` have the same memory layout, thus casting `x.as_ptr()`
+         // as `*const u8` is safe. The `x.as_ptr()` comes from a reference and is thus guaranteed
+         // to be valid for reads for the length of the slice `x.len()`, which cannot be larger
+         // than `isize::MAX`. The returned slice is never mutated.
+         let bytes: &[u8] = unsafe { from_raw_parts(x.as_ptr() as *const u8, x.len()) };
+         memchr::memchr(byte, bytes).is_some()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/index.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/index.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/index.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/index.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,451 ----
+ //! Indexing implementations for `[T]`.
+ 
+ use crate::ops;
+ use crate::ptr;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, I> ops::Index<I> for [T]
+ where
+     I: SliceIndex<[T]>,
+ {
+     type Output = I::Output;
+ 
+     #[inline]
+     fn index(&self, index: I) -> &I::Output {
+         index.index(self)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, I> ops::IndexMut<I> for [T]
+ where
+     I: SliceIndex<[T]>,
+ {
+     #[inline]
+     fn index_mut(&mut self, index: I) -> &mut I::Output {
+         index.index_mut(self)
+     }
+ }
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ fn slice_start_index_len_fail(index: usize, len: usize) -> ! {
+     panic!("range start index {} out of range for slice of length {}", index, len);
+ }
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ pub(crate) fn slice_end_index_len_fail(index: usize, len: usize) -> ! {
+     panic!("range end index {} out of range for slice of length {}", index, len);
+ }
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ pub(crate) fn slice_index_order_fail(index: usize, end: usize) -> ! {
+     panic!("slice index starts at {} but ends at {}", index, end);
+ }
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ pub(crate) fn slice_start_index_overflow_fail() -> ! {
+     panic!("attempted to index slice from after maximum usize");
+ }
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ pub(crate) fn slice_end_index_overflow_fail() -> ! {
+     panic!("attempted to index slice up to maximum usize");
+ }
+ 
+ mod private_slice_index {
+     use super::ops;
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     pub trait Sealed {}
+ 
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for usize {}
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for ops::Range<usize> {}
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for ops::RangeTo<usize> {}
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for ops::RangeFrom<usize> {}
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for ops::RangeFull {}
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for ops::RangeInclusive<usize> {}
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     impl Sealed for ops::RangeToInclusive<usize> {}
+ }
+ 
+ /// A helper trait used for indexing operations.
+ ///
+ /// Implementations of this trait have to promise that if the argument
+ /// to `get_(mut_)unchecked` is a safe reference, then so is the result.
+ #[stable(feature = "slice_get_slice", since = "1.28.0")]
+ #[rustc_on_unimplemented(
+     on(T = "str", label = "string indices are ranges of `usize`",),
+     on(
+         all(any(T = "str", T = "&str", T = "std::string::String"), _Self = "{integer}"),
+         note = "you can use `.chars().nth()` or `.bytes().nth()`\n\
+                 for more information, see chapter 8 in The Book: \
+                 <https://doc.rust-lang.org/book/ch08-02-strings.html#indexing-into-strings>"
+     ),
+     message = "the type `{T}` cannot be indexed by `{Self}`",
+     label = "slice indices are of type `usize` or ranges of `usize`"
+ )]
+ pub unsafe trait SliceIndex<T: ?Sized>: private_slice_index::Sealed {
+     /// The output type returned by methods.
+     #[stable(feature = "slice_get_slice", since = "1.28.0")]
+     type Output: ?Sized;
+ 
+     /// Returns a shared reference to the output at this location, if in
+     /// bounds.
+     #[unstable(feature = "slice_index_methods", issue = "none")]
+     fn get(self, slice: &T) -> Option<&Self::Output>;
+ 
+     /// Returns a mutable reference to the output at this location, if in
+     /// bounds.
+     #[unstable(feature = "slice_index_methods", issue = "none")]
+     fn get_mut(self, slice: &mut T) -> Option<&mut Self::Output>;
+ 
+     /// Returns a shared reference to the output at this location, without
+     /// performing any bounds checking.
+     /// Calling this method with an out-of-bounds index or a dangling `slice` pointer
+     /// is *[undefined behavior]* even if the resulting reference is not used.
+     ///
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     #[unstable(feature = "slice_index_methods", issue = "none")]
+     unsafe fn get_unchecked(self, slice: *const T) -> *const Self::Output;
+ 
+     /// Returns a mutable reference to the output at this location, without
+     /// performing any bounds checking.
+     /// Calling this method with an out-of-bounds index or a dangling `slice` pointer
+     /// is *[undefined behavior]* even if the resulting reference is not used.
+     ///
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     #[unstable(feature = "slice_index_methods", issue = "none")]
+     unsafe fn get_unchecked_mut(self, slice: *mut T) -> *mut Self::Output;
+ 
+     /// Returns a shared reference to the output at this location, panicking
+     /// if out of bounds.
+     #[unstable(feature = "slice_index_methods", issue = "none")]
+     #[track_caller]
+     fn index(self, slice: &T) -> &Self::Output;
+ 
+     /// Returns a mutable reference to the output at this location, panicking
+     /// if out of bounds.
+     #[unstable(feature = "slice_index_methods", issue = "none")]
+     #[track_caller]
+     fn index_mut(self, slice: &mut T) -> &mut Self::Output;
+ }
+ 
+ #[stable(feature = "slice_get_slice_impls", since = "1.15.0")]
+ unsafe impl<T> SliceIndex<[T]> for usize {
+     type Output = T;
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&T> {
+         // SAFETY: `self` is checked to be in bounds.
+         if self < slice.len() { unsafe { Some(&*self.get_unchecked(slice)) } } else { None }
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut T> {
+         // SAFETY: `self` is checked to be in bounds.
+         if self < slice.len() { unsafe { Some(&mut *self.get_unchecked_mut(slice)) } } else { None }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const T {
+         // SAFETY: the caller guarantees that `slice` is not dangling, so it
+         // cannot be longer than `isize::MAX`. They also guarantee that
+         // `self` is in bounds of `slice` so `self` cannot overflow an `isize`,
+         // so the call to `add` is safe.
+         unsafe { slice.as_ptr().add(self) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut T {
+         // SAFETY: see comments for `get_unchecked` above.
+         unsafe { slice.as_mut_ptr().add(self) }
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &T {
+         // N.B., use intrinsic indexing
+         &(*slice)[self]
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut T {
+         // N.B., use intrinsic indexing
+         &mut (*slice)[self]
+     }
+ }
+ 
+ #[stable(feature = "slice_get_slice_impls", since = "1.15.0")]
+ unsafe impl<T> SliceIndex<[T]> for ops::Range<usize> {
+     type Output = [T];
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&[T]> {
+         if self.start > self.end || self.end > slice.len() {
+             None
+         } else {
+             // SAFETY: `self` is checked to be valid and in bounds above.
+             unsafe { Some(&*self.get_unchecked(slice)) }
+         }
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> {
+         if self.start > self.end || self.end > slice.len() {
+             None
+         } else {
+             // SAFETY: `self` is checked to be valid and in bounds above.
+             unsafe { Some(&mut *self.get_unchecked_mut(slice)) }
+         }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const [T] {
+         // SAFETY: the caller guarantees that `slice` is not dangling, so it
+         // cannot be longer than `isize::MAX`. They also guarantee that
+         // `self` is in bounds of `slice` so `self` cannot overflow an `isize`,
+         // so the call to `add` is safe.
+         unsafe { ptr::slice_from_raw_parts(slice.as_ptr().add(self.start), self.end - self.start) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut [T] {
+         // SAFETY: see comments for `get_unchecked` above.
+         unsafe {
+             ptr::slice_from_raw_parts_mut(slice.as_mut_ptr().add(self.start), self.end - self.start)
+         }
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &[T] {
+         if self.start > self.end {
+             slice_index_order_fail(self.start, self.end);
+         } else if self.end > slice.len() {
+             slice_end_index_len_fail(self.end, slice.len());
+         }
+         // SAFETY: `self` is checked to be valid and in bounds above.
+         unsafe { &*self.get_unchecked(slice) }
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut [T] {
+         if self.start > self.end {
+             slice_index_order_fail(self.start, self.end);
+         } else if self.end > slice.len() {
+             slice_end_index_len_fail(self.end, slice.len());
+         }
+         // SAFETY: `self` is checked to be valid and in bounds above.
+         unsafe { &mut *self.get_unchecked_mut(slice) }
+     }
+ }
+ 
+ #[stable(feature = "slice_get_slice_impls", since = "1.15.0")]
+ unsafe impl<T> SliceIndex<[T]> for ops::RangeTo<usize> {
+     type Output = [T];
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&[T]> {
+         (0..self.end).get(slice)
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> {
+         (0..self.end).get_mut(slice)
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked`.
+         unsafe { (0..self.end).get_unchecked(slice) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked_mut`.
+         unsafe { (0..self.end).get_unchecked_mut(slice) }
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &[T] {
+         (0..self.end).index(slice)
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut [T] {
+         (0..self.end).index_mut(slice)
+     }
+ }
+ 
+ #[stable(feature = "slice_get_slice_impls", since = "1.15.0")]
+ unsafe impl<T> SliceIndex<[T]> for ops::RangeFrom<usize> {
+     type Output = [T];
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&[T]> {
+         (self.start..slice.len()).get(slice)
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> {
+         (self.start..slice.len()).get_mut(slice)
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked`.
+         unsafe { (self.start..slice.len()).get_unchecked(slice) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked_mut`.
+         unsafe { (self.start..slice.len()).get_unchecked_mut(slice) }
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &[T] {
+         if self.start > slice.len() {
+             slice_start_index_len_fail(self.start, slice.len());
+         }
+         // SAFETY: `self` is checked to be valid and in bounds above.
+         unsafe { &*self.get_unchecked(slice) }
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut [T] {
+         if self.start > slice.len() {
+             slice_start_index_len_fail(self.start, slice.len());
+         }
+         // SAFETY: `self` is checked to be valid and in bounds above.
+         unsafe { &mut *self.get_unchecked_mut(slice) }
+     }
+ }
+ 
+ #[stable(feature = "slice_get_slice_impls", since = "1.15.0")]
+ unsafe impl<T> SliceIndex<[T]> for ops::RangeFull {
+     type Output = [T];
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&[T]> {
+         Some(slice)
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> {
+         Some(slice)
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const [T] {
+         slice
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut [T] {
+         slice
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &[T] {
+         slice
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut [T] {
+         slice
+     }
+ }
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ unsafe impl<T> SliceIndex<[T]> for ops::RangeInclusive<usize> {
+     type Output = [T];
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&[T]> {
+         if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) }
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> {
+         if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked`.
+         unsafe { self.into_slice_range().get_unchecked(slice) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked_mut`.
+         unsafe { self.into_slice_range().get_unchecked_mut(slice) }
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &[T] {
+         if *self.end() == usize::MAX {
+             slice_end_index_overflow_fail();
+         }
+         self.into_slice_range().index(slice)
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut [T] {
+         if *self.end() == usize::MAX {
+             slice_end_index_overflow_fail();
+         }
+         self.into_slice_range().index_mut(slice)
+     }
+ }
+ 
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ unsafe impl<T> SliceIndex<[T]> for ops::RangeToInclusive<usize> {
+     type Output = [T];
+ 
+     #[inline]
+     fn get(self, slice: &[T]) -> Option<&[T]> {
+         (0..=self.end).get(slice)
+     }
+ 
+     #[inline]
+     fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> {
+         (0..=self.end).get_mut(slice)
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const [T]) -> *const [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked`.
+         unsafe { (0..=self.end).get_unchecked(slice) }
+     }
+ 
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut [T]) -> *mut [T] {
+         // SAFETY: the caller has to uphold the safety contract for `get_unchecked_mut`.
+         unsafe { (0..=self.end).get_unchecked_mut(slice) }
+     }
+ 
+     #[inline]
+     fn index(self, slice: &[T]) -> &[T] {
+         (0..=self.end).index(slice)
+     }
+ 
+     #[inline]
+     fn index_mut(self, slice: &mut [T]) -> &mut [T] {
+         (0..=self.end).index_mut(slice)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/iter/macros.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/iter/macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/iter/macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/iter/macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,407 ----
+ //! Macros used by iterators of slice.
+ 
+ // Inlining is_empty and len makes a huge performance difference
+ macro_rules! is_empty {
+     // The way we encode the length of a ZST iterator, this works both for ZST
+     // and non-ZST.
+     ($self: ident) => {
+         $self.ptr.as_ptr() as *const T == $self.end
+     };
+ }
+ 
+ // To get rid of some bounds checks (see `position`), we compute the length in a somewhat
+ // unexpected way. (Tested by `codegen/slice-position-bounds-check`.)
+ macro_rules! len {
+     ($self: ident) => {{
+         #![allow(unused_unsafe)] // we're sometimes used within an unsafe block
+ 
+         let start = $self.ptr;
+         let size = size_from_ptr(start.as_ptr());
+         if size == 0 {
+             // This _cannot_ use `unchecked_sub` because we depend on wrapping
+             // to represent the length of long ZST slice iterators.
+             ($self.end as usize).wrapping_sub(start.as_ptr() as usize)
+         } else {
+             // We know that `start <= end`, so can do better than `offset_from`,
+             // which needs to deal in signed.  By setting appropriate flags here
+             // we can tell LLVM this, which helps it remove bounds checks.
+             // SAFETY: By the type invariant, `start <= end`
+             let diff = unsafe { unchecked_sub($self.end as usize, start.as_ptr() as usize) };
+             // By also telling LLVM that the pointers are apart by an exact
+             // multiple of the type size, it can optimize `len() == 0` down to
+             // `start == end` instead of `(end - start) < size`.
+             // SAFETY: By the type invariant, the pointers are aligned so the
+             //         distance between them must be a multiple of pointee size
+             unsafe { exact_div(diff, size) }
+         }
+     }};
+ }
+ 
+ // The shared definition of the `Iter` and `IterMut` iterators
+ macro_rules! iterator {
+     (
+         struct $name:ident -> $ptr:ty,
+         $elem:ty,
+         $raw_mut:tt,
+         {$( $mut_:tt )?},
+         {$($extra:tt)*}
+     ) => {
+         // Returns the first element and moves the start of the iterator forwards by 1.
+         // Greatly improves performance compared to an inlined function. The iterator
+         // must not be empty.
+         macro_rules! next_unchecked {
+             ($self: ident) => {& $( $mut_ )? *$self.post_inc_start(1)}
+         }
+ 
+         // Returns the last element and moves the end of the iterator backwards by 1.
+         // Greatly improves performance compared to an inlined function. The iterator
+         // must not be empty.
+         macro_rules! next_back_unchecked {
+             ($self: ident) => {& $( $mut_ )? *$self.pre_dec_end(1)}
+         }
+ 
+         // Shrinks the iterator when T is a ZST, by moving the end of the iterator
+         // backwards by `n`. `n` must not exceed `self.len()`.
+         macro_rules! zst_shrink {
+             ($self: ident, $n: ident) => {
+                 $self.end = ($self.end as * $raw_mut u8).wrapping_offset(-$n) as * $raw_mut T;
+             }
+         }
+ 
+         impl<'a, T> $name<'a, T> {
+             // Helper function for creating a slice from the iterator.
+             #[inline(always)]
+             fn make_slice(&self) -> &'a [T] {
+                 // SAFETY: the iterator was created from a slice with pointer
+                 // `self.ptr` and length `len!(self)`. This guarantees that all
+                 // the prerequisites for `from_raw_parts` are fulfilled.
+                 unsafe { from_raw_parts(self.ptr.as_ptr(), len!(self)) }
+             }
+ 
+             // Helper function for moving the start of the iterator forwards by `offset` elements,
+             // returning the old start.
+             // Unsafe because the offset must not exceed `self.len()`.
+             #[inline(always)]
+             unsafe fn post_inc_start(&mut self, offset: isize) -> * $raw_mut T {
+                 if mem::size_of::<T>() == 0 {
+                     zst_shrink!(self, offset);
+                     self.ptr.as_ptr()
+                 } else {
+                     let old = self.ptr.as_ptr();
+                     // SAFETY: the caller guarantees that `offset` doesn't exceed `self.len()`,
+                     // so this new pointer is inside `self` and thus guaranteed to be non-null.
+                     self.ptr = unsafe { NonNull::new_unchecked(self.ptr.as_ptr().offset(offset)) };
+                     old
+                 }
+             }
+ 
+             // Helper function for moving the end of the iterator backwards by `offset` elements,
+             // returning the new end.
+             // Unsafe because the offset must not exceed `self.len()`.
+             #[inline(always)]
+             unsafe fn pre_dec_end(&mut self, offset: isize) -> * $raw_mut T {
+                 if mem::size_of::<T>() == 0 {
+                     zst_shrink!(self, offset);
+                     self.ptr.as_ptr()
+                 } else {
+                     // SAFETY: the caller guarantees that `offset` doesn't exceed `self.len()`,
+                     // which is guaranteed to not overflow an `isize`. Also, the resulting pointer
+                     // is in bounds of `slice`, which fulfills the other requirements for `offset`.
+                     self.end = unsafe { self.end.offset(-offset) };
+                     self.end
+                 }
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<T> ExactSizeIterator for $name<'_, T> {
+             #[inline(always)]
+             fn len(&self) -> usize {
+                 len!(self)
+             }
+ 
+             #[inline(always)]
+             fn is_empty(&self) -> bool {
+                 is_empty!(self)
+             }
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<'a, T> Iterator for $name<'a, T> {
+             type Item = $elem;
+ 
+             #[inline]
+             fn next(&mut self) -> Option<$elem> {
+                 // could be implemented with slices, but this avoids bounds checks
+ 
+                 // SAFETY: `assume` calls are safe since a slice's start pointer
+                 // must be non-null, and slices over non-ZSTs must also have a
+                 // non-null end pointer. The call to `next_unchecked!` is safe
+                 // since we check if the iterator is empty first.
+                 unsafe {
+                     assume(!self.ptr.as_ptr().is_null());
+                     if mem::size_of::<T>() != 0 {
+                         assume(!self.end.is_null());
+                     }
+                     if is_empty!(self) {
+                         None
+                     } else {
+                         Some(next_unchecked!(self))
+                     }
+                 }
+             }
+ 
+             #[inline]
+             fn size_hint(&self) -> (usize, Option<usize>) {
+                 let exact = len!(self);
+                 (exact, Some(exact))
+             }
+ 
+             #[inline]
+             fn count(self) -> usize {
+                 len!(self)
+             }
+ 
+             #[inline]
+             fn nth(&mut self, n: usize) -> Option<$elem> {
+                 if n >= len!(self) {
+                     // This iterator is now empty.
+                     if mem::size_of::<T>() == 0 {
+                         // We have to do it this way as `ptr` may never be 0, but `end`
+                         // could be (due to wrapping).
+                         self.end = self.ptr.as_ptr();
+                     } else {
+                         // SAFETY: end can't be 0 if T isn't ZST because ptr isn't 0 and end >= ptr
+                         unsafe {
+                             self.ptr = NonNull::new_unchecked(self.end as *mut T);
+                         }
+                     }
+                     return None;
+                 }
+                 // SAFETY: We are in bounds. `post_inc_start` does the right thing even for ZSTs.
+                 unsafe {
+                     self.post_inc_start(n as isize);
+                     Some(next_unchecked!(self))
+                 }
+             }
+ 
+             #[inline]
+             fn last(mut self) -> Option<$elem> {
+                 self.next_back()
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile.
+             #[inline]
+             fn for_each<F>(mut self, mut f: F)
+             where
+                 Self: Sized,
+                 F: FnMut(Self::Item),
+             {
+                 while let Some(x) = self.next() {
+                     f(x);
+                 }
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile.
+             #[inline]
+             fn all<F>(&mut self, mut f: F) -> bool
+             where
+                 Self: Sized,
+                 F: FnMut(Self::Item) -> bool,
+             {
+                 while let Some(x) = self.next() {
+                     if !f(x) {
+                         return false;
+                     }
+                 }
+                 true
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile.
+             #[inline]
+             fn any<F>(&mut self, mut f: F) -> bool
+             where
+                 Self: Sized,
+                 F: FnMut(Self::Item) -> bool,
+             {
+                 while let Some(x) = self.next() {
+                     if f(x) {
+                         return true;
+                     }
+                 }
+                 false
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile.
+             #[inline]
+             fn find<P>(&mut self, mut predicate: P) -> Option<Self::Item>
+             where
+                 Self: Sized,
+                 P: FnMut(&Self::Item) -> bool,
+             {
+                 while let Some(x) = self.next() {
+                     if predicate(&x) {
+                         return Some(x);
+                     }
+                 }
+                 None
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile.
+             #[inline]
+             fn find_map<B, F>(&mut self, mut f: F) -> Option<B>
+             where
+                 Self: Sized,
+                 F: FnMut(Self::Item) -> Option<B>,
+             {
+                 while let Some(x) = self.next() {
+                     if let Some(y) = f(x) {
+                         return Some(y);
+                     }
+                 }
+                 None
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile. Also, the `assume` avoids a bounds check.
+             #[inline]
+             #[rustc_inherit_overflow_checks]
+             fn position<P>(&mut self, mut predicate: P) -> Option<usize> where
+                 Self: Sized,
+                 P: FnMut(Self::Item) -> bool,
+             {
+                 let n = len!(self);
+                 let mut i = 0;
+                 while let Some(x) = self.next() {
+                     if predicate(x) {
+                         // SAFETY: we are guaranteed to be in bounds by the loop invariant:
+                         // when `i >= n`, `self.next()` returns `None` and the loop breaks.
+                         unsafe { assume(i < n) };
+                         return Some(i);
+                     }
+                     i += 1;
+                 }
+                 None
+             }
+ 
+             // We override the default implementation, which uses `try_fold`,
+             // because this simple implementation generates less LLVM IR and is
+             // faster to compile. Also, the `assume` avoids a bounds check.
+             #[inline]
+             fn rposition<P>(&mut self, mut predicate: P) -> Option<usize> where
+                 P: FnMut(Self::Item) -> bool,
+                 Self: Sized + ExactSizeIterator + DoubleEndedIterator
+             {
+                 let n = len!(self);
+                 let mut i = n;
+                 while let Some(x) = self.next_back() {
+                     i -= 1;
+                     if predicate(x) {
+                         // SAFETY: `i` must be lower than `n` since it starts at `n`
+                         // and is only decreasing.
+                         unsafe { assume(i < n) };
+                         return Some(i);
+                     }
+                 }
+                 None
+             }
+ 
+             #[doc(hidden)]
+             unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+                 // SAFETY: the caller must guarantee that `i` is in bounds of
+                 // the underlying slice, so `i` cannot overflow an `isize`, and
+                 // the returned references is guaranteed to refer to an element
+                 // of the slice and thus guaranteed to be valid.
+                 //
+                 // Also note that the caller also guarantees that we're never
+                 // called with the same index again, and that no other methods
+                 // that will access this subslice are called, so it is valid
+                 // for the returned reference to be mutable in the case of
+                 // `IterMut`
+                 unsafe { & $( $mut_ )? * self.ptr.as_ptr().add(idx) }
+             }
+ 
+             $($extra)*
+         }
+ 
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<'a, T> DoubleEndedIterator for $name<'a, T> {
+             #[inline]
+             fn next_back(&mut self) -> Option<$elem> {
+                 // could be implemented with slices, but this avoids bounds checks
+ 
+                 // SAFETY: `assume` calls are safe since a slice's start pointer must be non-null,
+                 // and slices over non-ZSTs must also have a non-null end pointer.
+                 // The call to `next_back_unchecked!` is safe since we check if the iterator is
+                 // empty first.
+                 unsafe {
+                     assume(!self.ptr.as_ptr().is_null());
+                     if mem::size_of::<T>() != 0 {
+                         assume(!self.end.is_null());
+                     }
+                     if is_empty!(self) {
+                         None
+                     } else {
+                         Some(next_back_unchecked!(self))
+                     }
+                 }
+             }
+ 
+             #[inline]
+             fn nth_back(&mut self, n: usize) -> Option<$elem> {
+                 if n >= len!(self) {
+                     // This iterator is now empty.
+                     self.end = self.ptr.as_ptr();
+                     return None;
+                 }
+                 // SAFETY: We are in bounds. `pre_dec_end` does the right thing even for ZSTs.
+                 unsafe {
+                     self.pre_dec_end(n as isize);
+                     Some(next_back_unchecked!(self))
+                 }
+             }
+         }
+ 
+         #[stable(feature = "fused", since = "1.26.0")]
+         impl<T> FusedIterator for $name<'_, T> {}
+ 
+         #[unstable(feature = "trusted_len", issue = "37572")]
+         unsafe impl<T> TrustedLen for $name<'_, T> {}
+     }
+ }
+ 
+ macro_rules! forward_iterator {
+     ($name:ident: $elem:ident, $iter_of:ty) => {
+         #[stable(feature = "rust1", since = "1.0.0")]
+         impl<'a, $elem, P> Iterator for $name<'a, $elem, P>
+         where
+             P: FnMut(&T) -> bool,
+         {
+             type Item = $iter_of;
+ 
+             #[inline]
+             fn next(&mut self) -> Option<$iter_of> {
+                 self.inner.next()
+             }
+ 
+             #[inline]
+             fn size_hint(&self) -> (usize, Option<usize>) {
+                 self.inner.size_hint()
+             }
+         }
+ 
+         #[stable(feature = "fused", since = "1.26.0")]
+         impl<'a, $elem, P> FusedIterator for $name<'a, $elem, P> where P: FnMut(&T) -> bool {}
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/iter.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/iter.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/iter.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/iter.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2969 ----
+ //! Definitions of a bunch of iterators for `[T]`.
+ 
+ #[macro_use] // import iterator! and forward_iterator!
+ mod macros;
+ 
+ use crate::cmp;
+ use crate::cmp::Ordering;
+ use crate::fmt;
+ use crate::intrinsics::{assume, exact_div, unchecked_sub};
+ use crate::iter::{FusedIterator, TrustedLen, TrustedRandomAccess};
+ use crate::marker::{PhantomData, Send, Sized, Sync};
+ use crate::mem;
+ use crate::num::NonZeroUsize;
+ use crate::ptr::NonNull;
+ 
+ use super::{from_raw_parts, from_raw_parts_mut};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> IntoIterator for &'a [T] {
+     type Item = &'a T;
+     type IntoIter = Iter<'a, T>;
+ 
+     fn into_iter(self) -> Iter<'a, T> {
+         self.iter()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> IntoIterator for &'a mut [T] {
+     type Item = &'a mut T;
+     type IntoIter = IterMut<'a, T>;
+ 
+     fn into_iter(self) -> IterMut<'a, T> {
+         self.iter_mut()
+     }
+ }
+ 
+ // Macro helper functions
+ #[inline(always)]
+ fn size_from_ptr<T>(_: *const T) -> usize {
+     mem::size_of::<T>()
+ }
+ 
+ /// Immutable slice iterator
+ ///
+ /// This struct is created by the [`iter`] method on [slices].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// // First, we declare a type which has `iter` method to get the `Iter` struct (&[usize here]):
+ /// let slice = &[1, 2, 3];
+ ///
+ /// // Then, we iterate over it:
+ /// for element in slice.iter() {
+ ///     println!("{}", element);
+ /// }
+ /// ```
+ ///
+ /// [`iter`]: ../../std/primitive.slice.html#method.iter
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Iter<'a, T: 'a> {
+     ptr: NonNull<T>,
+     end: *const T, // If T is a ZST, this is actually ptr+len.  This encoding is picked so that
+     // ptr == end is a quick test for the Iterator being empty, that works
+     // for both ZST and non-ZST.
+     _marker: PhantomData<&'a T>,
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug> fmt::Debug for Iter<'_, T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_tuple("Iter").field(&self.as_slice()).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T: Sync> Sync for Iter<'_, T> {}
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T: Sync> Send for Iter<'_, T> {}
+ 
+ impl<'a, T> Iter<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T]) -> Self {
+         let ptr = slice.as_ptr();
+         // SAFETY: Similar to `IterMut::new`.
+         unsafe {
+             assume(!ptr.is_null());
+ 
+             let end = if mem::size_of::<T>() == 0 {
+                 (ptr as *const u8).wrapping_add(slice.len()) as *const T
+             } else {
+                 ptr.add(slice.len())
+             };
+ 
+             Self { ptr: NonNull::new_unchecked(ptr as *mut T), end, _marker: PhantomData }
+         }
+     }
+ 
+     /// Views the underlying data as a subslice of the original data.
+     ///
+     /// This has the same lifetime as the original slice, and so the
+     /// iterator can continue to be used while this exists.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // First, we declare a type which has the `iter` method to get the `Iter`
+     /// // struct (&[usize here]):
+     /// let slice = &[1, 2, 3];
+     ///
+     /// // Then, we get the iterator:
+     /// let mut iter = slice.iter();
+     /// // So if we print what `as_slice` method returns here, we have "[1, 2, 3]":
+     /// println!("{:?}", iter.as_slice());
+     ///
+     /// // Next, we move to the second element of the slice:
+     /// iter.next();
+     /// // Now `as_slice` returns "[2, 3]":
+     /// println!("{:?}", iter.as_slice());
+     /// ```
+     #[stable(feature = "iter_to_slice", since = "1.4.0")]
+     pub fn as_slice(&self) -> &'a [T] {
+         self.make_slice()
+     }
+ }
+ 
+ iterator! {struct Iter -> *const T, &'a T, const, {/* no mut */}, {
+     fn is_sorted_by<F>(self, mut compare: F) -> bool
+     where
+         Self: Sized,
+         F: FnMut(&Self::Item, &Self::Item) -> Option<Ordering>,
+     {
+         self.as_slice().windows(2).all(|w| {
+             compare(&&w[0], &&w[1]).map(|o| o != Ordering::Greater).unwrap_or(false)
+         })
+     }
+ }}
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Clone for Iter<'_, T> {
+     fn clone(&self) -> Self {
+         Iter { ptr: self.ptr, end: self.end, _marker: self._marker }
+     }
+ }
+ 
+ #[stable(feature = "slice_iter_as_ref", since = "1.13.0")]
+ impl<T> AsRef<[T]> for Iter<'_, T> {
+     fn as_ref(&self) -> &[T] {
+         self.as_slice()
+     }
+ }
+ 
+ /// Mutable slice iterator.
+ ///
+ /// This struct is created by the [`iter_mut`] method on [slices].
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// // First, we declare a type which has `iter_mut` method to get the `IterMut`
+ /// // struct (&[usize here]):
+ /// let mut slice = &mut [1, 2, 3];
+ ///
+ /// // Then, we iterate over it and increment each element value:
+ /// for element in slice.iter_mut() {
+ ///     *element += 1;
+ /// }
+ ///
+ /// // We now have "[2, 3, 4]":
+ /// println!("{:?}", slice);
+ /// ```
+ ///
+ /// [`iter_mut`]: ../../std/primitive.slice.html#method.iter_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct IterMut<'a, T: 'a> {
+     ptr: NonNull<T>,
+     end: *mut T, // If T is a ZST, this is actually ptr+len.  This encoding is picked so that
+     // ptr == end is a quick test for the Iterator being empty, that works
+     // for both ZST and non-ZST.
+     _marker: PhantomData<&'a mut T>,
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug> fmt::Debug for IterMut<'_, T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_tuple("IterMut").field(&self.make_slice()).finish()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T: Sync> Sync for IterMut<'_, T> {}
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T: Send> Send for IterMut<'_, T> {}
+ 
+ impl<'a, T> IterMut<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T]) -> Self {
+         let ptr = slice.as_mut_ptr();
+         // SAFETY: There are several things here:
+         //
+         // `ptr` has been obtained by `slice.as_ptr()` where `slice` is a valid
+         // reference thus it is non-NUL and safe to use and pass to
+         // `NonNull::new_unchecked` .
+         //
+         // Adding `slice.len()` to the starting pointer gives a pointer
+         // at the end of `slice`. `end` will never be dereferenced, only checked
+         // for direct pointer equality with `ptr` to check if the iterator is
+         // done.
+         //
+         // In the case of a ZST, the end pointer is just the start pointer plus
+         // the length, to also allows for the fast `ptr == end` check.
+         //
+         // See the `next_unchecked!` and `is_empty!` macros as well as the
+         // `post_inc_start` method for more informations.
+         unsafe {
+             assume(!ptr.is_null());
+ 
+             let end = if mem::size_of::<T>() == 0 {
+                 (ptr as *mut u8).wrapping_add(slice.len()) as *mut T
+             } else {
+                 ptr.add(slice.len())
+             };
+ 
+             Self { ptr: NonNull::new_unchecked(ptr), end, _marker: PhantomData }
+         }
+     }
+ 
+     /// Views the underlying data as a subslice of the original data.
+     ///
+     /// To avoid creating `&mut` references that alias, this is forced
+     /// to consume the iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// // First, we declare a type which has `iter_mut` method to get the `IterMut`
+     /// // struct (&[usize here]):
+     /// let mut slice = &mut [1, 2, 3];
+     ///
+     /// {
+     ///     // Then, we get the iterator:
+     ///     let mut iter = slice.iter_mut();
+     ///     // We move to next element:
+     ///     iter.next();
+     ///     // So if we print what `into_slice` method returns here, we have "[2, 3]":
+     ///     println!("{:?}", iter.into_slice());
+     /// }
+     ///
+     /// // Now let's modify a value of the slice:
+     /// {
+     ///     // First we get back the iterator:
+     ///     let mut iter = slice.iter_mut();
+     ///     // We change the value of the first element of the slice returned by the `next` method:
+     ///     *iter.next().unwrap() += 1;
+     /// }
+     /// // Now slice is "[2, 2, 3]":
+     /// println!("{:?}", slice);
+     /// ```
+     #[stable(feature = "iter_to_slice", since = "1.4.0")]
+     pub fn into_slice(self) -> &'a mut [T] {
+         // SAFETY: the iterator was created from a mutable slice with pointer
+         // `self.ptr` and length `len!(self)`. This guarantees that all the prerequisites
+         // for `from_raw_parts_mut` are fulfilled.
+         unsafe { from_raw_parts_mut(self.ptr.as_ptr(), len!(self)) }
+     }
+ 
+     /// Views the underlying data as a subslice of the original data.
+     ///
+     /// To avoid creating `&mut [T]` references that alias, the returned slice
+     /// borrows its lifetime from the iterator the method is applied on.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// # #![feature(slice_iter_mut_as_slice)]
+     /// let mut slice: &mut [usize] = &mut [1, 2, 3];
+     ///
+     /// // First, we get the iterator:
+     /// let mut iter = slice.iter_mut();
+     /// // So if we check what the `as_slice` method returns here, we have "[1, 2, 3]":
+     /// assert_eq!(iter.as_slice(), &[1, 2, 3]);
+     ///
+     /// // Next, we move to the second element of the slice:
+     /// iter.next();
+     /// // Now `as_slice` returns "[2, 3]":
+     /// assert_eq!(iter.as_slice(), &[2, 3]);
+     /// ```
+     #[unstable(feature = "slice_iter_mut_as_slice", reason = "recently added", issue = "58957")]
+     pub fn as_slice(&self) -> &[T] {
+         self.make_slice()
+     }
+ }
+ 
+ iterator! {struct IterMut -> *mut T, &'a mut T, mut, {mut}, {}}
+ 
+ /// An internal abstraction over the splitting iterators, so that
+ /// splitn, splitn_mut etc can be implemented once.
+ #[doc(hidden)]
+ pub(super) trait SplitIter: DoubleEndedIterator {
+     /// Marks the underlying iterator as complete, extracting the remaining
+     /// portion of the slice.
+     fn finish(&mut self) -> Option<Self::Item>;
+ }
+ 
+ /// An iterator over subslices separated by elements that match a predicate
+ /// function.
+ ///
+ /// This struct is created by the [`split`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = [10, 40, 33, 20];
+ /// let mut iter = slice.split(|num| num % 3 == 0);
+ /// ```
+ ///
+ /// [`split`]: ../../std/primitive.slice.html#method.split
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Split<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     v: &'a [T],
+     pred: P,
+     finished: bool,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> Split<'a, T, P> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], pred: P) -> Self {
+         Self { v: slice, pred, finished: false }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for Split<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Split").field("v", &self.v).field("finished", &self.finished).finish()
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T, P> Clone for Split<'_, T, P>
+ where
+     P: Clone + FnMut(&T) -> bool,
+ {
+     fn clone(&self) -> Self {
+         Split { v: self.v, pred: self.pred.clone(), finished: self.finished }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T, P> Iterator for Split<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         match self.v.iter().position(|x| (self.pred)(x)) {
+             None => self.finish(),
+             Some(idx) => {
+                 let ret = Some(&self.v[..idx]);
+                 self.v = &self.v[idx + 1..];
+                 ret
+             }
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.finished { (0, Some(0)) } else { (1, Some(self.v.len() + 1)) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T, P> DoubleEndedIterator for Split<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         match self.v.iter().rposition(|x| (self.pred)(x)) {
+             None => self.finish(),
+             Some(idx) => {
+                 let ret = Some(&self.v[idx + 1..]);
+                 self.v = &self.v[..idx];
+                 ret
+             }
+         }
+     }
+ }
+ 
+ impl<'a, T, P> SplitIter for Split<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn finish(&mut self) -> Option<&'a [T]> {
+         if self.finished {
+             None
+         } else {
+             self.finished = true;
+             Some(self.v)
+         }
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T, P> FusedIterator for Split<'_, T, P> where P: FnMut(&T) -> bool {}
+ 
+ /// An iterator over subslices separated by elements that match a predicate
+ /// function. Unlike `Split`, it contains the matched part as a terminator
+ /// of the subslice.
+ ///
+ /// This struct is created by the [`split_inclusive`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(split_inclusive)]
+ ///
+ /// let slice = [10, 40, 33, 20];
+ /// let mut iter = slice.split_inclusive(|num| num % 3 == 0);
+ /// ```
+ ///
+ /// [`split_inclusive`]: ../../std/primitive.slice.html#method.split_inclusive
+ /// [slices]: ../../std/primitive.slice.html
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ pub struct SplitInclusive<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     v: &'a [T],
+     pred: P,
+     finished: bool,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> SplitInclusive<'a, T, P> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], pred: P) -> Self {
+         Self { v: slice, pred, finished: false }
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<T: fmt::Debug, P> fmt::Debug for SplitInclusive<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitInclusive")
+             .field("v", &self.v)
+             .field("finished", &self.finished)
+             .finish()
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<T, P> Clone for SplitInclusive<'_, T, P>
+ where
+     P: Clone + FnMut(&T) -> bool,
+ {
+     fn clone(&self) -> Self {
+         SplitInclusive { v: self.v, pred: self.pred.clone(), finished: self.finished }
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, T, P> Iterator for SplitInclusive<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         let idx =
+             self.v.iter().position(|x| (self.pred)(x)).map(|idx| idx + 1).unwrap_or(self.v.len());
+         if idx == self.v.len() {
+             self.finished = true;
+         }
+         let ret = Some(&self.v[..idx]);
+         self.v = &self.v[idx..];
+         ret
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.finished { (0, Some(0)) } else { (1, Some(self.v.len() + 1)) }
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, T, P> DoubleEndedIterator for SplitInclusive<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         // The last index of self.v is already checked and found to match
+         // by the last iteration, so we start searching a new match
+         // one index to the left.
+         let remainder = if self.v.is_empty() { &[] } else { &self.v[..(self.v.len() - 1)] };
+         let idx = remainder.iter().rposition(|x| (self.pred)(x)).map(|idx| idx + 1).unwrap_or(0);
+         if idx == 0 {
+             self.finished = true;
+         }
+         let ret = Some(&self.v[idx..]);
+         self.v = &self.v[..idx];
+         ret
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<T, P> FusedIterator for SplitInclusive<'_, T, P> where P: FnMut(&T) -> bool {}
+ 
+ /// An iterator over the mutable subslices of the vector which are separated
+ /// by elements that match `pred`.
+ ///
+ /// This struct is created by the [`split_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut v = [10, 40, 30, 20, 60, 50];
+ /// let iter = v.split_mut(|num| *num % 3 == 0);
+ /// ```
+ ///
+ /// [`split_mut`]: ../../std/primitive.slice.html#method.split_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct SplitMut<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     v: &'a mut [T],
+     pred: P,
+     finished: bool,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> SplitMut<'a, T, P> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], pred: P) -> Self {
+         Self { v: slice, pred, finished: false }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for SplitMut<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitMut").field("v", &self.v).field("finished", &self.finished).finish()
+     }
+ }
+ 
+ impl<'a, T, P> SplitIter for SplitMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn finish(&mut self) -> Option<&'a mut [T]> {
+         if self.finished {
+             None
+         } else {
+             self.finished = true;
+             Some(mem::replace(&mut self.v, &mut []))
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T, P> Iterator for SplitMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         let idx_opt = {
+             // work around borrowck limitations
+             let pred = &mut self.pred;
+             self.v.iter().position(|x| (*pred)(x))
+         };
+         match idx_opt {
+             None => self.finish(),
+             Some(idx) => {
+                 let tmp = mem::replace(&mut self.v, &mut []);
+                 let (head, tail) = tmp.split_at_mut(idx);
+                 self.v = &mut tail[1..];
+                 Some(head)
+             }
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.finished {
+             (0, Some(0))
+         } else {
+             // if the predicate doesn't match anything, we yield one slice
+             // if it matches every element, we yield len+1 empty slices.
+             (1, Some(self.v.len() + 1))
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T, P> DoubleEndedIterator for SplitMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         let idx_opt = {
+             // work around borrowck limitations
+             let pred = &mut self.pred;
+             self.v.iter().rposition(|x| (*pred)(x))
+         };
+         match idx_opt {
+             None => self.finish(),
+             Some(idx) => {
+                 let tmp = mem::replace(&mut self.v, &mut []);
+                 let (head, tail) = tmp.split_at_mut(idx);
+                 self.v = head;
+                 Some(&mut tail[1..])
+             }
+         }
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T, P> FusedIterator for SplitMut<'_, T, P> where P: FnMut(&T) -> bool {}
+ 
+ /// An iterator over the mutable subslices of the vector which are separated
+ /// by elements that match `pred`. Unlike `SplitMut`, it contains the matched
+ /// parts in the ends of the subslices.
+ ///
+ /// This struct is created by the [`split_inclusive_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(split_inclusive)]
+ ///
+ /// let mut v = [10, 40, 30, 20, 60, 50];
+ /// let iter = v.split_inclusive_mut(|num| *num % 3 == 0);
+ /// ```
+ ///
+ /// [`split_inclusive_mut`]: ../../std/primitive.slice.html#method.split_inclusive_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ pub struct SplitInclusiveMut<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     v: &'a mut [T],
+     pred: P,
+     finished: bool,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> SplitInclusiveMut<'a, T, P> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], pred: P) -> Self {
+         Self { v: slice, pred, finished: false }
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<T: fmt::Debug, P> fmt::Debug for SplitInclusiveMut<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitInclusiveMut")
+             .field("v", &self.v)
+             .field("finished", &self.finished)
+             .finish()
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, T, P> Iterator for SplitInclusiveMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         let idx_opt = {
+             // work around borrowck limitations
+             let pred = &mut self.pred;
+             self.v.iter().position(|x| (*pred)(x))
+         };
+         let idx = idx_opt.map(|idx| idx + 1).unwrap_or(self.v.len());
+         if idx == self.v.len() {
+             self.finished = true;
+         }
+         let tmp = mem::replace(&mut self.v, &mut []);
+         let (head, tail) = tmp.split_at_mut(idx);
+         self.v = tail;
+         Some(head)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.finished {
+             (0, Some(0))
+         } else {
+             // if the predicate doesn't match anything, we yield one slice
+             // if it matches every element, we yield len+1 empty slices.
+             (1, Some(self.v.len() + 1))
+         }
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, T, P> DoubleEndedIterator for SplitInclusiveMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         if self.finished {
+             return None;
+         }
+ 
+         let idx_opt = if self.v.is_empty() {
+             None
+         } else {
+             // work around borrowck limitations
+             let pred = &mut self.pred;
+ 
+             // The last index of self.v is already checked and found to match
+             // by the last iteration, so we start searching a new match
+             // one index to the left.
+             let remainder = &self.v[..(self.v.len() - 1)];
+             remainder.iter().rposition(|x| (*pred)(x))
+         };
+         let idx = idx_opt.map(|idx| idx + 1).unwrap_or(0);
+         if idx == 0 {
+             self.finished = true;
+         }
+         let tmp = mem::replace(&mut self.v, &mut []);
+         let (head, tail) = tmp.split_at_mut(idx);
+         self.v = head;
+         Some(tail)
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<T, P> FusedIterator for SplitInclusiveMut<'_, T, P> where P: FnMut(&T) -> bool {}
+ 
+ /// An iterator over subslices separated by elements that match a predicate
+ /// function, starting from the end of the slice.
+ ///
+ /// This struct is created by the [`rsplit`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = [11, 22, 33, 0, 44, 55];
+ /// let iter = slice.rsplit(|num| *num == 0);
+ /// ```
+ ///
+ /// [`rsplit`]: ../../std/primitive.slice.html#method.rsplit
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ #[derive(Clone)] // Is this correct, or does it incorrectly require `T: Clone`?
+ pub struct RSplit<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     inner: Split<'a, T, P>,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> RSplit<'a, T, P> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], pred: P) -> Self {
+         Self { inner: Split::new(slice, pred) }
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for RSplit<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("RSplit")
+             .field("v", &self.inner.v)
+             .field("finished", &self.inner.finished)
+             .finish()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<'a, T, P> Iterator for RSplit<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         self.inner.next_back()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<'a, T, P> DoubleEndedIterator for RSplit<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         self.inner.next()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<'a, T, P> SplitIter for RSplit<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn finish(&mut self) -> Option<&'a [T]> {
+         self.inner.finish()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<T, P> FusedIterator for RSplit<'_, T, P> where P: FnMut(&T) -> bool {}
+ 
+ /// An iterator over the subslices of the vector which are separated
+ /// by elements that match `pred`, starting from the end of the slice.
+ ///
+ /// This struct is created by the [`rsplit_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = [11, 22, 33, 0, 44, 55];
+ /// let iter = slice.rsplit_mut(|num| *num == 0);
+ /// ```
+ ///
+ /// [`rsplit_mut`]: ../../std/primitive.slice.html#method.rsplit_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ pub struct RSplitMut<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     inner: SplitMut<'a, T, P>,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> RSplitMut<'a, T, P> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], pred: P) -> Self {
+         Self { inner: SplitMut::new(slice, pred) }
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for RSplitMut<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("RSplitMut")
+             .field("v", &self.inner.v)
+             .field("finished", &self.inner.finished)
+             .finish()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<'a, T, P> SplitIter for RSplitMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn finish(&mut self) -> Option<&'a mut [T]> {
+         self.inner.finish()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<'a, T, P> Iterator for RSplitMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         self.inner.next_back()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<'a, T, P> DoubleEndedIterator for RSplitMut<'a, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         self.inner.next()
+     }
+ }
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ impl<T, P> FusedIterator for RSplitMut<'_, T, P> where P: FnMut(&T) -> bool {}
+ 
+ /// An private iterator over subslices separated by elements that
+ /// match a predicate function, splitting at most a fixed number of
+ /// times.
+ #[derive(Debug)]
+ struct GenericSplitN<I> {
+     iter: I,
+     count: usize,
+ }
+ 
+ impl<T, I: SplitIter<Item = T>> Iterator for GenericSplitN<I> {
+     type Item = T;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<T> {
+         match self.count {
+             0 => None,
+             1 => {
+                 self.count -= 1;
+                 self.iter.finish()
+             }
+             _ => {
+                 self.count -= 1;
+                 self.iter.next()
+             }
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (lower, upper_opt) = self.iter.size_hint();
+         (lower, upper_opt.map(|upper| cmp::min(self.count, upper)))
+     }
+ }
+ 
+ /// An iterator over subslices separated by elements that match a predicate
+ /// function, limited to a given number of splits.
+ ///
+ /// This struct is created by the [`splitn`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = [10, 40, 30, 20, 60, 50];
+ /// let iter = slice.splitn(2, |num| *num % 3 == 0);
+ /// ```
+ ///
+ /// [`splitn`]: ../../std/primitive.slice.html#method.splitn
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct SplitN<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     inner: GenericSplitN<Split<'a, T, P>>,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> SplitN<'a, T, P> {
+     #[inline]
+     pub(super) fn new(s: Split<'a, T, P>, n: usize) -> Self {
+         Self { inner: GenericSplitN { iter: s, count: n } }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for SplitN<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitN").field("inner", &self.inner).finish()
+     }
+ }
+ 
+ /// An iterator over subslices separated by elements that match a
+ /// predicate function, limited to a given number of splits, starting
+ /// from the end of the slice.
+ ///
+ /// This struct is created by the [`rsplitn`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = [10, 40, 30, 20, 60, 50];
+ /// let iter = slice.rsplitn(2, |num| *num % 3 == 0);
+ /// ```
+ ///
+ /// [`rsplitn`]: ../../std/primitive.slice.html#method.rsplitn
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RSplitN<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     inner: GenericSplitN<RSplit<'a, T, P>>,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> RSplitN<'a, T, P> {
+     #[inline]
+     pub(super) fn new(s: RSplit<'a, T, P>, n: usize) -> Self {
+         Self { inner: GenericSplitN { iter: s, count: n } }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for RSplitN<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("RSplitN").field("inner", &self.inner).finish()
+     }
+ }
+ 
+ /// An iterator over subslices separated by elements that match a predicate
+ /// function, limited to a given number of splits.
+ ///
+ /// This struct is created by the [`splitn_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = [10, 40, 30, 20, 60, 50];
+ /// let iter = slice.splitn_mut(2, |num| *num % 3 == 0);
+ /// ```
+ ///
+ /// [`splitn_mut`]: ../../std/primitive.slice.html#method.splitn_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct SplitNMut<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     inner: GenericSplitN<SplitMut<'a, T, P>>,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> SplitNMut<'a, T, P> {
+     #[inline]
+     pub(super) fn new(s: SplitMut<'a, T, P>, n: usize) -> Self {
+         Self { inner: GenericSplitN { iter: s, count: n } }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for SplitNMut<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitNMut").field("inner", &self.inner).finish()
+     }
+ }
+ 
+ /// An iterator over subslices separated by elements that match a
+ /// predicate function, limited to a given number of splits, starting
+ /// from the end of the slice.
+ ///
+ /// This struct is created by the [`rsplitn_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = [10, 40, 30, 20, 60, 50];
+ /// let iter = slice.rsplitn_mut(2, |num| *num % 3 == 0);
+ /// ```
+ ///
+ /// [`rsplitn_mut`]: ../../std/primitive.slice.html#method.rsplitn_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct RSplitNMut<'a, T: 'a, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     inner: GenericSplitN<RSplitMut<'a, T, P>>,
+ }
+ 
+ impl<'a, T: 'a, P: FnMut(&T) -> bool> RSplitNMut<'a, T, P> {
+     #[inline]
+     pub(super) fn new(s: RSplitMut<'a, T, P>, n: usize) -> Self {
+         Self { inner: GenericSplitN { iter: s, count: n } }
+     }
+ }
+ 
+ #[stable(feature = "core_impl_debug", since = "1.9.0")]
+ impl<T: fmt::Debug, P> fmt::Debug for RSplitNMut<'_, T, P>
+ where
+     P: FnMut(&T) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("RSplitNMut").field("inner", &self.inner).finish()
+     }
+ }
+ 
+ forward_iterator! { SplitN: T, &'a [T] }
+ forward_iterator! { RSplitN: T, &'a [T] }
+ forward_iterator! { SplitNMut: T, &'a mut [T] }
+ forward_iterator! { RSplitNMut: T, &'a mut [T] }
+ 
+ /// An iterator over overlapping subslices of length `size`.
+ ///
+ /// This struct is created by the [`windows`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = ['r', 'u', 's', 't'];
+ /// let iter = slice.windows(2);
+ /// ```
+ ///
+ /// [`windows`]: ../../std/primitive.slice.html#method.windows
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Windows<'a, T: 'a> {
+     v: &'a [T],
+     size: NonZeroUsize,
+ }
+ 
+ impl<'a, T: 'a> Windows<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], size: NonZeroUsize) -> Self {
+         Self { v: slice, size }
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Clone for Windows<'_, T> {
+     fn clone(&self) -> Self {
+         Windows { v: self.v, size: self.size }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> Iterator for Windows<'a, T> {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.size.get() > self.v.len() {
+             None
+         } else {
+             let ret = Some(&self.v[..self.size.get()]);
+             self.v = &self.v[1..];
+             ret
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.size.get() > self.v.len() {
+             (0, Some(0))
+         } else {
+             let size = self.v.len() - self.size.get() + 1;
+             (size, Some(size))
+         }
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         let (end, overflow) = self.size.get().overflowing_add(n);
+         if end > self.v.len() || overflow {
+             self.v = &[];
+             None
+         } else {
+             let nth = &self.v[n..end];
+             self.v = &self.v[n + 1..];
+             Some(nth)
+         }
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         if self.size.get() > self.v.len() {
+             None
+         } else {
+             let start = self.v.len() - self.size.get();
+             Some(&self.v[start..])
+         }
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         // SAFETY: since the caller guarantees that `i` is in bounds,
+         // which means that `i` cannot overflow an `isize`, and the
+         // slice created by `from_raw_parts` is a subslice of `self.v`
+         // thus is guaranteed to be valid for the lifetime `'a` of `self.v`.
+         unsafe { from_raw_parts(self.v.as_ptr().add(idx), self.size.get()) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> DoubleEndedIterator for Windows<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.size.get() > self.v.len() {
+             None
+         } else {
+             let ret = Some(&self.v[self.v.len() - self.size.get()..]);
+             self.v = &self.v[..self.v.len() - 1];
+             ret
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let (end, overflow) = self.v.len().overflowing_sub(n);
+         if end < self.size.get() || overflow {
+             self.v = &[];
+             None
+         } else {
+             let ret = &self.v[end - self.size.get()..end];
+             self.v = &self.v[..end - 1];
+             Some(ret)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> ExactSizeIterator for Windows<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for Windows<'_, T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for Windows<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for Windows<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a
+ /// time), starting at the beginning of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last slice
+ /// of the iteration will be the remainder.
+ ///
+ /// This struct is created by the [`chunks`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.chunks(2);
+ /// ```
+ ///
+ /// [`chunks`]: ../../std/primitive.slice.html#method.chunks
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Chunks<'a, T: 'a> {
+     v: &'a [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T: 'a> Chunks<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], size: usize) -> Self {
+         Self { v: slice, chunk_size: size }
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Clone for Chunks<'_, T> {
+     fn clone(&self) -> Self {
+         Chunks { v: self.v, chunk_size: self.chunk_size }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> Iterator for Chunks<'a, T> {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let chunksz = cmp::min(self.v.len(), self.chunk_size);
+             let (fst, snd) = self.v.split_at(chunksz);
+             self.v = snd;
+             Some(fst)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.v.is_empty() {
+             (0, Some(0))
+         } else {
+             let n = self.v.len() / self.chunk_size;
+             let rem = self.v.len() % self.chunk_size;
+             let n = if rem > 0 { n + 1 } else { n };
+             (n, Some(n))
+         }
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         let (start, overflow) = n.overflowing_mul(self.chunk_size);
+         if start >= self.v.len() || overflow {
+             self.v = &[];
+             None
+         } else {
+             let end = match start.checked_add(self.chunk_size) {
+                 Some(sum) => cmp::min(self.v.len(), sum),
+                 None => self.v.len(),
+             };
+             let nth = &self.v[start..end];
+             self.v = &self.v[end..];
+             Some(nth)
+         }
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let start = (self.v.len() - 1) / self.chunk_size * self.chunk_size;
+             Some(&self.v[start..])
+         }
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let start = idx * self.chunk_size;
+         let end = match start.checked_add(self.chunk_size) {
+             None => self.v.len(),
+             Some(end) => cmp::min(end, self.v.len()),
+         };
+         // SAFETY: the caller guarantees that `i` is in bounds,
+         // which means that `start` must be in bounds of the
+         // underlying `self.v` slice, and we made sure that `end`
+         // is also in bounds of `self.v`. Thus, `start` cannot overflow
+         // an `isize`, and the slice constructed by `from_raw_parts`
+         // is a subslice of `self.v` which is guaranteed to be valid
+         // for the lifetime `'a` of `self.v`.
+         unsafe { from_raw_parts(self.v.as_ptr().add(start), end - start) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> DoubleEndedIterator for Chunks<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let remainder = self.v.len() % self.chunk_size;
+             let chunksz = if remainder != 0 { remainder } else { self.chunk_size };
+             let (fst, snd) = self.v.split_at(self.v.len() - chunksz);
+             self.v = fst;
+             Some(snd)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &[];
+             None
+         } else {
+             let start = (len - 1 - n) * self.chunk_size;
+             let end = match start.checked_add(self.chunk_size) {
+                 Some(res) => cmp::min(res, self.v.len()),
+                 None => self.v.len(),
+             };
+             let nth_back = &self.v[start..end];
+             self.v = &self.v[..start];
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> ExactSizeIterator for Chunks<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for Chunks<'_, T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for Chunks<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for Chunks<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) mutable chunks (`chunk_size`
+ /// elements at a time), starting at the beginning of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last slice
+ /// of the iteration will be the remainder.
+ ///
+ /// This struct is created by the [`chunks_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.chunks_mut(2);
+ /// ```
+ ///
+ /// [`chunks_mut`]: ../../std/primitive.slice.html#method.chunks_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct ChunksMut<'a, T: 'a> {
+     v: &'a mut [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T: 'a> ChunksMut<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], size: usize) -> Self {
+         Self { v: slice, chunk_size: size }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> Iterator for ChunksMut<'a, T> {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let sz = cmp::min(self.v.len(), self.chunk_size);
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (head, tail) = tmp.split_at_mut(sz);
+             self.v = tail;
+             Some(head)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.v.is_empty() {
+             (0, Some(0))
+         } else {
+             let n = self.v.len() / self.chunk_size;
+             let rem = self.v.len() % self.chunk_size;
+             let n = if rem > 0 { n + 1 } else { n };
+             (n, Some(n))
+         }
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<&'a mut [T]> {
+         let (start, overflow) = n.overflowing_mul(self.chunk_size);
+         if start >= self.v.len() || overflow {
+             self.v = &mut [];
+             None
+         } else {
+             let end = match start.checked_add(self.chunk_size) {
+                 Some(sum) => cmp::min(self.v.len(), sum),
+                 None => self.v.len(),
+             };
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (head, tail) = tmp.split_at_mut(end);
+             let (_, nth) = head.split_at_mut(start);
+             self.v = tail;
+             Some(nth)
+         }
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let start = (self.v.len() - 1) / self.chunk_size * self.chunk_size;
+             Some(&mut self.v[start..])
+         }
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let start = idx * self.chunk_size;
+         let end = match start.checked_add(self.chunk_size) {
+             None => self.v.len(),
+             Some(end) => cmp::min(end, self.v.len()),
+         };
+         // SAFETY: see comments for `Chunks::__iterator_get_unchecked`.
+         //
+         // Also note that the caller also guarantees that we're never called
+         // with the same index again, and that no other methods that will
+         // access this subslice are called, so it is valid for the returned
+         // slice to be mutable.
+         unsafe { from_raw_parts_mut(self.v.as_mut_ptr().add(start), end - start) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a, T> DoubleEndedIterator for ChunksMut<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let remainder = self.v.len() % self.chunk_size;
+             let sz = if remainder != 0 { remainder } else { self.chunk_size };
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let tmp_len = tmp.len();
+             let (head, tail) = tmp.split_at_mut(tmp_len - sz);
+             self.v = head;
+             Some(tail)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &mut [];
+             None
+         } else {
+             let start = (len - 1 - n) * self.chunk_size;
+             let end = match start.checked_add(self.chunk_size) {
+                 Some(res) => cmp::min(res, self.v.len()),
+                 None => self.v.len(),
+             };
+             let (temp, _tail) = mem::replace(&mut self.v, &mut []).split_at_mut(end);
+             let (head, nth_back) = temp.split_at_mut(start);
+             self.v = head;
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> ExactSizeIterator for ChunksMut<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for ChunksMut<'_, T> {}
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl<T> FusedIterator for ChunksMut<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for ChunksMut<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a
+ /// time), starting at the beginning of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last
+ /// up to `chunk_size-1` elements will be omitted but can be retrieved from
+ /// the [`remainder`] function from the iterator.
+ ///
+ /// This struct is created by the [`chunks_exact`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.chunks_exact(2);
+ /// ```
+ ///
+ /// [`chunks_exact`]: ../../std/primitive.slice.html#method.chunks_exact
+ /// [`remainder`]: ChunksExact::remainder
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ pub struct ChunksExact<'a, T: 'a> {
+     v: &'a [T],
+     rem: &'a [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T> ChunksExact<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], chunk_size: usize) -> Self {
+         let rem = slice.len() % chunk_size;
+         let fst_len = slice.len() - rem;
+         // SAFETY: 0 <= fst_len <= slice.len() by construction above
+         let (fst, snd) = unsafe { slice.split_at_unchecked(fst_len) };
+         Self { v: fst, rem: snd, chunk_size }
+     }
+ 
+     /// Returns the remainder of the original slice that is not going to be
+     /// returned by the iterator. The returned slice has at most `chunk_size-1`
+     /// elements.
+     #[stable(feature = "chunks_exact", since = "1.31.0")]
+     pub fn remainder(&self) -> &'a [T] {
+         self.rem
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<T> Clone for ChunksExact<'_, T> {
+     fn clone(&self) -> Self {
+         ChunksExact { v: self.v, rem: self.rem, chunk_size: self.chunk_size }
+     }
+ }
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<'a, T> Iterator for ChunksExact<'a, T> {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let (fst, snd) = self.v.split_at(self.chunk_size);
+             self.v = snd;
+             Some(fst)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = self.v.len() / self.chunk_size;
+         (n, Some(n))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         let (start, overflow) = n.overflowing_mul(self.chunk_size);
+         if start >= self.v.len() || overflow {
+             self.v = &[];
+             None
+         } else {
+             let (_, snd) = self.v.split_at(start);
+             self.v = snd;
+             self.next()
+         }
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<Self::Item> {
+         self.next_back()
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let start = idx * self.chunk_size;
+         // SAFETY: mostly identical to `Chunks::__iterator_get_unchecked`.
+         unsafe { from_raw_parts(self.v.as_ptr().add(start), self.chunk_size) }
+     }
+ }
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<'a, T> DoubleEndedIterator for ChunksExact<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let (fst, snd) = self.v.split_at(self.v.len() - self.chunk_size);
+             self.v = fst;
+             Some(snd)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &[];
+             None
+         } else {
+             let start = (len - 1 - n) * self.chunk_size;
+             let end = start + self.chunk_size;
+             let nth_back = &self.v[start..end];
+             self.v = &self.v[..start];
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<T> ExactSizeIterator for ChunksExact<'_, T> {
+     fn is_empty(&self) -> bool {
+         self.v.is_empty()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for ChunksExact<'_, T> {}
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<T> FusedIterator for ChunksExact<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for ChunksExact<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) mutable chunks (`chunk_size`
+ /// elements at a time), starting at the beginning of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last up to
+ /// `chunk_size-1` elements will be omitted but can be retrieved from the
+ /// [`into_remainder`] function from the iterator.
+ ///
+ /// This struct is created by the [`chunks_exact_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.chunks_exact_mut(2);
+ /// ```
+ ///
+ /// [`chunks_exact_mut`]: ../../std/primitive.slice.html#method.chunks_exact_mut
+ /// [`into_remainder`]: ChunksExactMut::into_remainder
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ pub struct ChunksExactMut<'a, T: 'a> {
+     v: &'a mut [T],
+     rem: &'a mut [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T> ChunksExactMut<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], chunk_size: usize) -> Self {
+         let rem = slice.len() % chunk_size;
+         let fst_len = slice.len() - rem;
+         // SAFETY: 0 <= fst_len <= slice.len() by construction above
+         let (fst, snd) = unsafe { slice.split_at_mut_unchecked(fst_len) };
+         Self { v: fst, rem: snd, chunk_size }
+     }
+ 
+     /// Returns the remainder of the original slice that is not going to be
+     /// returned by the iterator. The returned slice has at most `chunk_size-1`
+     /// elements.
+     #[stable(feature = "chunks_exact", since = "1.31.0")]
+     pub fn into_remainder(self) -> &'a mut [T] {
+         self.rem
+     }
+ }
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<'a, T> Iterator for ChunksExactMut<'a, T> {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (head, tail) = tmp.split_at_mut(self.chunk_size);
+             self.v = tail;
+             Some(head)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = self.v.len() / self.chunk_size;
+         (n, Some(n))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<&'a mut [T]> {
+         let (start, overflow) = n.overflowing_mul(self.chunk_size);
+         if start >= self.v.len() || overflow {
+             self.v = &mut [];
+             None
+         } else {
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (_, snd) = tmp.split_at_mut(start);
+             self.v = snd;
+             self.next()
+         }
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<Self::Item> {
+         self.next_back()
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let start = idx * self.chunk_size;
+         // SAFETY: see comments for `ChunksMut::__iterator_get_unchecked`.
+         unsafe { from_raw_parts_mut(self.v.as_mut_ptr().add(start), self.chunk_size) }
+     }
+ }
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<'a, T> DoubleEndedIterator for ChunksExactMut<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let tmp_len = tmp.len();
+             let (head, tail) = tmp.split_at_mut(tmp_len - self.chunk_size);
+             self.v = head;
+             Some(tail)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &mut [];
+             None
+         } else {
+             let start = (len - 1 - n) * self.chunk_size;
+             let end = start + self.chunk_size;
+             let (temp, _tail) = mem::replace(&mut self.v, &mut []).split_at_mut(end);
+             let (head, nth_back) = temp.split_at_mut(start);
+             self.v = head;
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<T> ExactSizeIterator for ChunksExactMut<'_, T> {
+     fn is_empty(&self) -> bool {
+         self.v.is_empty()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for ChunksExactMut<'_, T> {}
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ impl<T> FusedIterator for ChunksExactMut<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for ChunksExactMut<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// A windowed iterator over a slice in overlapping chunks (`N` elements at a
+ /// time), starting at the beginning of the slice
+ ///
+ /// This struct is created by the [`array_windows`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(array_windows)]
+ ///
+ /// let slice = [0, 1, 2, 3];
+ /// let iter = slice.array_windows::<2>();
+ /// ```
+ ///
+ /// [`array_windows`]: ../../std/primitive.slice.html#method.array_windows
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug, Clone, Copy)]
+ #[unstable(feature = "array_windows", issue = "75027")]
+ pub struct ArrayWindows<'a, T: 'a, const N: usize> {
+     slice_head: *const T,
+     num: usize,
+     marker: PhantomData<&'a [T; N]>,
+ }
+ 
+ impl<'a, T: 'a, const N: usize> ArrayWindows<'a, T, N> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T]) -> Self {
+         let num_windows = slice.len().saturating_sub(N - 1);
+         Self { slice_head: slice.as_ptr(), num: num_windows, marker: PhantomData }
+     }
+ }
+ 
+ #[unstable(feature = "array_windows", issue = "75027")]
+ impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> {
+     type Item = &'a [T; N];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<Self::Item> {
+         if self.num == 0 {
+             return None;
+         }
+         // SAFETY:
+         // This is safe because it's indexing into a slice guaranteed to be length > N.
+         let ret = unsafe { &*self.slice_head.cast::<[T; N]>() };
+         // SAFETY: Guaranteed that there are at least 1 item remaining otherwise
+         // earlier branch would've been hit
+         self.slice_head = unsafe { self.slice_head.add(1) };
+ 
+         self.num -= 1;
+         Some(ret)
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         (self.num, Some(self.num))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.num
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         if self.num <= n {
+             self.num = 0;
+             return None;
+         }
+         // SAFETY:
+         // This is safe because it's indexing into a slice guaranteed to be length > N.
+         let ret = unsafe { &*self.slice_head.add(n).cast::<[T; N]>() };
+         // SAFETY: Guaranteed that there are at least n items remaining
+         self.slice_head = unsafe { self.slice_head.add(n + 1) };
+ 
+         self.num -= n + 1;
+         Some(ret)
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<Self::Item> {
+         self.nth(self.num.checked_sub(1)?)
+     }
+ }
+ 
+ #[unstable(feature = "array_windows", issue = "75027")]
+ impl<'a, T, const N: usize> DoubleEndedIterator for ArrayWindows<'a, T, N> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T; N]> {
+         if self.num == 0 {
+             return None;
+         }
+         // SAFETY: Guaranteed that there are n items remaining, n-1 for 0-indexing.
+         let ret = unsafe { &*self.slice_head.add(self.num - 1).cast::<[T; N]>() };
+         self.num -= 1;
+         Some(ret)
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<&'a [T; N]> {
+         if self.num <= n {
+             self.num = 0;
+             return None;
+         }
+         // SAFETY: Guaranteed that there are n items remaining, n-1 for 0-indexing.
+         let ret = unsafe { &*self.slice_head.add(self.num - (n + 1)).cast::<[T; N]>() };
+         self.num -= n + 1;
+         Some(ret)
+     }
+ }
+ 
+ #[unstable(feature = "array_windows", issue = "75027")]
+ impl<T, const N: usize> ExactSizeIterator for ArrayWindows<'_, T, N> {
+     fn is_empty(&self) -> bool {
+         self.num == 0
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) chunks (`N` elements at a
+ /// time), starting at the beginning of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last
+ /// up to `N-1` elements will be omitted but can be retrieved from
+ /// the [`remainder`] function from the iterator.
+ ///
+ /// This struct is created by the [`array_chunks`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(array_chunks)]
+ ///
+ /// let slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.array_chunks::<2>();
+ /// ```
+ ///
+ /// [`array_chunks`]: ../../std/primitive.slice.html#method.array_chunks
+ /// [`remainder`]: ArrayChunks::remainder
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ pub struct ArrayChunks<'a, T: 'a, const N: usize> {
+     iter: Iter<'a, [T; N]>,
+     rem: &'a [T],
+ }
+ 
+ impl<'a, T, const N: usize> ArrayChunks<'a, T, N> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T]) -> Self {
+         let (array_slice, rem) = slice.as_chunks();
+         Self { iter: array_slice.iter(), rem }
+     }
+ 
+     /// Returns the remainder of the original slice that is not going to be
+     /// returned by the iterator. The returned slice has at most `N-1`
+     /// elements.
+     #[unstable(feature = "array_chunks", issue = "74985")]
+     pub fn remainder(&self) -> &'a [T] {
+         self.rem
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<T, const N: usize> Clone for ArrayChunks<'_, T, N> {
+     fn clone(&self) -> Self {
+         ArrayChunks { iter: self.iter.clone(), rem: self.rem }
+     }
+ }
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<'a, T, const N: usize> Iterator for ArrayChunks<'a, T, N> {
+     type Item = &'a [T; N];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T; N]> {
+         self.iter.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.iter.count()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         self.iter.nth(n)
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         self.iter.last()
+     }
+ 
+     unsafe fn __iterator_get_unchecked(&mut self, i: usize) -> &'a [T; N] {
+         // SAFETY: The safety guarantees of `__iterator_get_unchecked` are
+         // transferred to the caller.
+         unsafe { self.iter.__iterator_get_unchecked(i) }
+     }
+ }
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<'a, T, const N: usize> DoubleEndedIterator for ArrayChunks<'a, T, N> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T; N]> {
+         self.iter.next_back()
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         self.iter.nth_back(n)
+     }
+ }
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<T, const N: usize> ExactSizeIterator for ArrayChunks<'_, T, N> {
+     fn is_empty(&self) -> bool {
+         self.iter.is_empty()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T, const N: usize> TrustedLen for ArrayChunks<'_, T, N> {}
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<T, const N: usize> FusedIterator for ArrayChunks<'_, T, N> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ unsafe impl<'a, T, const N: usize> TrustedRandomAccess for ArrayChunks<'a, T, N> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) mutable chunks (`N` elements
+ /// at a time), starting at the beginning of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last
+ /// up to `N-1` elements will be omitted but can be retrieved from
+ /// the [`into_remainder`] function from the iterator.
+ ///
+ /// This struct is created by the [`array_chunks_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// #![feature(array_chunks)]
+ ///
+ /// let mut slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.array_chunks_mut::<2>();
+ /// ```
+ ///
+ /// [`array_chunks_mut`]: ../../std/primitive.slice.html#method.array_chunks_mut
+ /// [`into_remainder`]: ../../std/slice/struct.ArrayChunksMut.html#method.into_remainder
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ pub struct ArrayChunksMut<'a, T: 'a, const N: usize> {
+     iter: IterMut<'a, [T; N]>,
+     rem: &'a mut [T],
+ }
+ 
+ impl<'a, T, const N: usize> ArrayChunksMut<'a, T, N> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T]) -> Self {
+         let (array_slice, rem) = slice.as_chunks_mut();
+         Self { iter: array_slice.iter_mut(), rem }
+     }
+ 
+     /// Returns the remainder of the original slice that is not going to be
+     /// returned by the iterator. The returned slice has at most `N-1`
+     /// elements.
+     #[unstable(feature = "array_chunks", issue = "74985")]
+     pub fn into_remainder(self) -> &'a mut [T] {
+         self.rem
+     }
+ }
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<'a, T, const N: usize> Iterator for ArrayChunksMut<'a, T, N> {
+     type Item = &'a mut [T; N];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T; N]> {
+         self.iter.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.iter.count()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         self.iter.nth(n)
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         self.iter.last()
+     }
+ 
+     unsafe fn __iterator_get_unchecked(&mut self, i: usize) -> &'a mut [T; N] {
+         // SAFETY: The safety guarantees of `__iterator_get_unchecked` are transferred to
+         // the caller.
+         unsafe { self.iter.__iterator_get_unchecked(i) }
+     }
+ }
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<'a, T, const N: usize> DoubleEndedIterator for ArrayChunksMut<'a, T, N> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T; N]> {
+         self.iter.next_back()
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         self.iter.nth_back(n)
+     }
+ }
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<T, const N: usize> ExactSizeIterator for ArrayChunksMut<'_, T, N> {
+     fn is_empty(&self) -> bool {
+         self.iter.is_empty()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T, const N: usize> TrustedLen for ArrayChunksMut<'_, T, N> {}
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ impl<T, const N: usize> FusedIterator for ArrayChunksMut<'_, T, N> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ unsafe impl<'a, T, const N: usize> TrustedRandomAccess for ArrayChunksMut<'a, T, N> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a
+ /// time), starting at the end of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last slice
+ /// of the iteration will be the remainder.
+ ///
+ /// This struct is created by the [`rchunks`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.rchunks(2);
+ /// ```
+ ///
+ /// [`rchunks`]: ../../std/primitive.slice.html#method.rchunks
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ pub struct RChunks<'a, T: 'a> {
+     v: &'a [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T: 'a> RChunks<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], size: usize) -> Self {
+         Self { v: slice, chunk_size: size }
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> Clone for RChunks<'_, T> {
+     fn clone(&self) -> Self {
+         RChunks { v: self.v, chunk_size: self.chunk_size }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> Iterator for RChunks<'a, T> {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let chunksz = cmp::min(self.v.len(), self.chunk_size);
+             let (fst, snd) = self.v.split_at(self.v.len() - chunksz);
+             self.v = fst;
+             Some(snd)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.v.is_empty() {
+             (0, Some(0))
+         } else {
+             let n = self.v.len() / self.chunk_size;
+             let rem = self.v.len() % self.chunk_size;
+             let n = if rem > 0 { n + 1 } else { n };
+             (n, Some(n))
+         }
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         let (end, overflow) = n.overflowing_mul(self.chunk_size);
+         if end >= self.v.len() || overflow {
+             self.v = &[];
+             None
+         } else {
+             // Can't underflow because of the check above
+             let end = self.v.len() - end;
+             let start = match end.checked_sub(self.chunk_size) {
+                 Some(sum) => sum,
+                 None => 0,
+             };
+             let nth = &self.v[start..end];
+             self.v = &self.v[0..start];
+             Some(nth)
+         }
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let rem = self.v.len() % self.chunk_size;
+             let end = if rem == 0 { self.chunk_size } else { rem };
+             Some(&self.v[0..end])
+         }
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let end = self.v.len() - idx * self.chunk_size;
+         let start = match end.checked_sub(self.chunk_size) {
+             None => 0,
+             Some(start) => start,
+         };
+         // SAFETY: mostly identical to `Chunks::__iterator_get_unchecked`.
+         unsafe { from_raw_parts(self.v.as_ptr().add(start), end - start) }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> DoubleEndedIterator for RChunks<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let remainder = self.v.len() % self.chunk_size;
+             let chunksz = if remainder != 0 { remainder } else { self.chunk_size };
+             let (fst, snd) = self.v.split_at(chunksz);
+             self.v = snd;
+             Some(fst)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &[];
+             None
+         } else {
+             // can't underflow because `n < len`
+             let offset_from_end = (len - 1 - n) * self.chunk_size;
+             let end = self.v.len() - offset_from_end;
+             let start = end.saturating_sub(self.chunk_size);
+             let nth_back = &self.v[start..end];
+             self.v = &self.v[end..];
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> ExactSizeIterator for RChunks<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for RChunks<'_, T> {}
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> FusedIterator for RChunks<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for RChunks<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) mutable chunks (`chunk_size`
+ /// elements at a time), starting at the end of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last slice
+ /// of the iteration will be the remainder.
+ ///
+ /// This struct is created by the [`rchunks_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.rchunks_mut(2);
+ /// ```
+ ///
+ /// [`rchunks_mut`]: ../../std/primitive.slice.html#method.rchunks_mut
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ pub struct RChunksMut<'a, T: 'a> {
+     v: &'a mut [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T: 'a> RChunksMut<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], size: usize) -> Self {
+         Self { v: slice, chunk_size: size }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> Iterator for RChunksMut<'a, T> {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let sz = cmp::min(self.v.len(), self.chunk_size);
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let tmp_len = tmp.len();
+             let (head, tail) = tmp.split_at_mut(tmp_len - sz);
+             self.v = head;
+             Some(tail)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.v.is_empty() {
+             (0, Some(0))
+         } else {
+             let n = self.v.len() / self.chunk_size;
+             let rem = self.v.len() % self.chunk_size;
+             let n = if rem > 0 { n + 1 } else { n };
+             (n, Some(n))
+         }
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<&'a mut [T]> {
+         let (end, overflow) = n.overflowing_mul(self.chunk_size);
+         if end >= self.v.len() || overflow {
+             self.v = &mut [];
+             None
+         } else {
+             // Can't underflow because of the check above
+             let end = self.v.len() - end;
+             let start = match end.checked_sub(self.chunk_size) {
+                 Some(sum) => sum,
+                 None => 0,
+             };
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (head, tail) = tmp.split_at_mut(start);
+             let (nth, _) = tail.split_at_mut(end - start);
+             self.v = head;
+             Some(nth)
+         }
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let rem = self.v.len() % self.chunk_size;
+             let end = if rem == 0 { self.chunk_size } else { rem };
+             Some(&mut self.v[0..end])
+         }
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let end = self.v.len() - idx * self.chunk_size;
+         let start = match end.checked_sub(self.chunk_size) {
+             None => 0,
+             Some(start) => start,
+         };
+         // SAFETY: see comments for `RChunks::__iterator_get_unchecked` and
+         // `ChunksMut::__iterator_get_unchecked`
+         unsafe { from_raw_parts_mut(self.v.as_mut_ptr().add(start), end - start) }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> DoubleEndedIterator for RChunksMut<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         if self.v.is_empty() {
+             None
+         } else {
+             let remainder = self.v.len() % self.chunk_size;
+             let sz = if remainder != 0 { remainder } else { self.chunk_size };
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (head, tail) = tmp.split_at_mut(sz);
+             self.v = tail;
+             Some(head)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &mut [];
+             None
+         } else {
+             // can't underflow because `n < len`
+             let offset_from_end = (len - 1 - n) * self.chunk_size;
+             let end = self.v.len() - offset_from_end;
+             let start = end.saturating_sub(self.chunk_size);
+             let (tmp, tail) = mem::replace(&mut self.v, &mut []).split_at_mut(end);
+             let (_, nth_back) = tmp.split_at_mut(start);
+             self.v = tail;
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> ExactSizeIterator for RChunksMut<'_, T> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for RChunksMut<'_, T> {}
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> FusedIterator for RChunksMut<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for RChunksMut<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a
+ /// time), starting at the end of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last
+ /// up to `chunk_size-1` elements will be omitted but can be retrieved from
+ /// the [`remainder`] function from the iterator.
+ ///
+ /// This struct is created by the [`rchunks_exact`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.rchunks_exact(2);
+ /// ```
+ ///
+ /// [`rchunks_exact`]: ../../std/primitive.slice.html#method.rchunks_exact
+ /// [`remainder`]: ChunksExact::remainder
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ pub struct RChunksExact<'a, T: 'a> {
+     v: &'a [T],
+     rem: &'a [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T> RChunksExact<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a [T], chunk_size: usize) -> Self {
+         let rem = slice.len() % chunk_size;
+         // SAFETY: 0 <= rem <= slice.len() by construction above
+         let (fst, snd) = unsafe { slice.split_at_unchecked(rem) };
+         Self { v: snd, rem: fst, chunk_size }
+     }
+ 
+     /// Returns the remainder of the original slice that is not going to be
+     /// returned by the iterator. The returned slice has at most `chunk_size-1`
+     /// elements.
+     #[stable(feature = "rchunks", since = "1.31.0")]
+     pub fn remainder(&self) -> &'a [T] {
+         self.rem
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> Clone for RChunksExact<'a, T> {
+     fn clone(&self) -> RChunksExact<'a, T> {
+         RChunksExact { v: self.v, rem: self.rem, chunk_size: self.chunk_size }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> Iterator for RChunksExact<'a, T> {
+     type Item = &'a [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let (fst, snd) = self.v.split_at(self.v.len() - self.chunk_size);
+             self.v = fst;
+             Some(snd)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = self.v.len() / self.chunk_size;
+         (n, Some(n))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         let (end, overflow) = n.overflowing_mul(self.chunk_size);
+         if end >= self.v.len() || overflow {
+             self.v = &[];
+             None
+         } else {
+             let (fst, _) = self.v.split_at(self.v.len() - end);
+             self.v = fst;
+             self.next()
+         }
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<Self::Item> {
+         self.next_back()
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let end = self.v.len() - idx * self.chunk_size;
+         let start = end - self.chunk_size;
+         // SAFETY:
+         // SAFETY: mostmy identical to `Chunks::__iterator_get_unchecked`.
+         unsafe { from_raw_parts(self.v.as_ptr().add(start), self.chunk_size) }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> DoubleEndedIterator for RChunksExact<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let (fst, snd) = self.v.split_at(self.chunk_size);
+             self.v = snd;
+             Some(fst)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &[];
+             None
+         } else {
+             // now that we know that `n` corresponds to a chunk,
+             // none of these operations can underflow/overflow
+             let offset = (len - n) * self.chunk_size;
+             let start = self.v.len() - offset;
+             let end = start + self.chunk_size;
+             let nth_back = &self.v[start..end];
+             self.v = &self.v[end..];
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> ExactSizeIterator for RChunksExact<'a, T> {
+     fn is_empty(&self) -> bool {
+         self.v.is_empty()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for RChunksExact<'_, T> {}
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> FusedIterator for RChunksExact<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for RChunksExact<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// An iterator over a slice in (non-overlapping) mutable chunks (`chunk_size`
+ /// elements at a time), starting at the end of the slice.
+ ///
+ /// When the slice len is not evenly divided by the chunk size, the last up to
+ /// `chunk_size-1` elements will be omitted but can be retrieved from the
+ /// [`into_remainder`] function from the iterator.
+ ///
+ /// This struct is created by the [`rchunks_exact_mut`] method on [slices].
+ ///
+ /// # Example
+ ///
+ /// ```
+ /// let mut slice = ['l', 'o', 'r', 'e', 'm'];
+ /// let iter = slice.rchunks_exact_mut(2);
+ /// ```
+ ///
+ /// [`rchunks_exact_mut`]: ../../std/primitive.slice.html#method.rchunks_exact_mut
+ /// [`into_remainder`]: ChunksExactMut::into_remainder
+ /// [slices]: ../../std/primitive.slice.html
+ #[derive(Debug)]
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ pub struct RChunksExactMut<'a, T: 'a> {
+     v: &'a mut [T],
+     rem: &'a mut [T],
+     chunk_size: usize,
+ }
+ 
+ impl<'a, T> RChunksExactMut<'a, T> {
+     #[inline]
+     pub(super) fn new(slice: &'a mut [T], chunk_size: usize) -> Self {
+         let rem = slice.len() % chunk_size;
+         // SAFETY: 0 <= rem <= slice.len() by construction above
+         let (fst, snd) = unsafe { slice.split_at_mut_unchecked(rem) };
+         Self { v: snd, rem: fst, chunk_size }
+     }
+ 
+     /// Returns the remainder of the original slice that is not going to be
+     /// returned by the iterator. The returned slice has at most `chunk_size-1`
+     /// elements.
+     #[stable(feature = "rchunks", since = "1.31.0")]
+     pub fn into_remainder(self) -> &'a mut [T] {
+         self.rem
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> Iterator for RChunksExactMut<'a, T> {
+     type Item = &'a mut [T];
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a mut [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let tmp_len = tmp.len();
+             let (head, tail) = tmp.split_at_mut(tmp_len - self.chunk_size);
+             self.v = head;
+             Some(tail)
+         }
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let n = self.v.len() / self.chunk_size;
+         (n, Some(n))
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.len()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<&'a mut [T]> {
+         let (end, overflow) = n.overflowing_mul(self.chunk_size);
+         if end >= self.v.len() || overflow {
+             self.v = &mut [];
+             None
+         } else {
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let tmp_len = tmp.len();
+             let (fst, _) = tmp.split_at_mut(tmp_len - end);
+             self.v = fst;
+             self.next()
+         }
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<Self::Item> {
+         self.next_back()
+     }
+ 
+     #[doc(hidden)]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item {
+         let end = self.v.len() - idx * self.chunk_size;
+         let start = end - self.chunk_size;
+         // SAFETY: see comments for `RChunksMut::__iterator_get_unchecked`.
+         unsafe { from_raw_parts_mut(self.v.as_mut_ptr().add(start), self.chunk_size) }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<'a, T> DoubleEndedIterator for RChunksExactMut<'a, T> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a mut [T]> {
+         if self.v.len() < self.chunk_size {
+             None
+         } else {
+             let tmp = mem::replace(&mut self.v, &mut []);
+             let (head, tail) = tmp.split_at_mut(self.chunk_size);
+             self.v = tail;
+             Some(head)
+         }
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         let len = self.len();
+         if n >= len {
+             self.v = &mut [];
+             None
+         } else {
+             // now that we know that `n` corresponds to a chunk,
+             // none of these operations can underflow/overflow
+             let offset = (len - n) * self.chunk_size;
+             let start = self.v.len() - offset;
+             let end = start + self.chunk_size;
+             let (tmp, tail) = mem::replace(&mut self.v, &mut []).split_at_mut(end);
+             let (_, nth_back) = tmp.split_at_mut(start);
+             self.v = tail;
+             Some(nth_back)
+         }
+     }
+ }
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> ExactSizeIterator for RChunksExactMut<'_, T> {
+     fn is_empty(&self) -> bool {
+         self.v.is_empty()
+     }
+ }
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl<T> TrustedLen for RChunksExactMut<'_, T> {}
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ impl<T> FusedIterator for RChunksExactMut<'_, T> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for RChunksExactMut<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for Iter<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl<'a, T> TrustedRandomAccess for IterMut<'a, T> {
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/memchr.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/memchr.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/memchr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/memchr.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,140 ----
+ // Original implementation taken from rust-memchr.
+ // Copyright 2015 Andrew Gallant, bluss and Nicolas Koch
+ 
+ // ignore-tidy-undocumented-unsafe
+ 
+ use crate::cmp;
+ use crate::mem;
+ 
+ const LO_U64: u64 = 0x0101010101010101;
+ const HI_U64: u64 = 0x8080808080808080;
+ 
+ // Use truncation.
+ const LO_USIZE: usize = LO_U64 as usize;
+ const HI_USIZE: usize = HI_U64 as usize;
+ const USIZE_BYTES: usize = mem::size_of::<usize>();
+ 
+ /// Returns `true` if `x` contains any zero byte.
+ ///
+ /// From *Matters Computational*, J. Arndt:
+ ///
+ /// "The idea is to subtract one from each of the bytes and then look for
+ /// bytes where the borrow propagated all the way to the most significant
+ /// bit."
+ #[inline]
+ fn contains_zero_byte(x: usize) -> bool {
+     x.wrapping_sub(LO_USIZE) & !x & HI_USIZE != 0
+ }
+ 
+ #[cfg(target_pointer_width = "16")]
+ #[inline]
+ fn repeat_byte(b: u8) -> usize {
+     (b as usize) << 8 | b as usize
+ }
+ 
+ #[cfg(not(target_pointer_width = "16"))]
+ #[inline]
+ fn repeat_byte(b: u8) -> usize {
+     (b as usize) * (usize::MAX / 255)
+ }
+ 
+ /// Returns the first index matching the byte `x` in `text`.
+ #[inline]
+ pub fn memchr(x: u8, text: &[u8]) -> Option<usize> {
+     // Fast path for small slices
+     if text.len() < 2 * USIZE_BYTES {
+         return text.iter().position(|elt| *elt == x);
+     }
+ 
+     memchr_general_case(x, text)
+ }
+ 
+ fn memchr_general_case(x: u8, text: &[u8]) -> Option<usize> {
+     // Scan for a single byte value by reading two `usize` words at a time.
+     //
+     // Split `text` in three parts
+     // - unaligned initial part, before the first word aligned address in text
+     // - body, scan by 2 words at a time
+     // - the last remaining part, < 2 word size
+ 
+     // search up to an aligned boundary
+     let len = text.len();
+     let ptr = text.as_ptr();
+     let mut offset = ptr.align_offset(USIZE_BYTES);
+ 
+     if offset > 0 {
+         offset = cmp::min(offset, len);
+         if let Some(index) = text[..offset].iter().position(|elt| *elt == x) {
+             return Some(index);
+         }
+     }
+ 
+     // search the body of the text
+     let repeated_x = repeat_byte(x);
+     while offset <= len - 2 * USIZE_BYTES {
+         unsafe {
+             let u = *(ptr.add(offset) as *const usize);
+             let v = *(ptr.add(offset + USIZE_BYTES) as *const usize);
+ 
+             // break if there is a matching byte
+             let zu = contains_zero_byte(u ^ repeated_x);
+             let zv = contains_zero_byte(v ^ repeated_x);
+             if zu || zv {
+                 break;
+             }
+         }
+         offset += USIZE_BYTES * 2;
+     }
+ 
+     // Find the byte after the point the body loop stopped.
+     text[offset..].iter().position(|elt| *elt == x).map(|i| offset + i)
+ }
+ 
+ /// Returns the last index matching the byte `x` in `text`.
+ pub fn memrchr(x: u8, text: &[u8]) -> Option<usize> {
+     // Scan for a single byte value by reading two `usize` words at a time.
+     //
+     // Split `text` in three parts:
+     // - unaligned tail, after the last word aligned address in text,
+     // - body, scanned by 2 words at a time,
+     // - the first remaining bytes, < 2 word size.
+     let len = text.len();
+     let ptr = text.as_ptr();
+     type Chunk = usize;
+ 
+     let (min_aligned_offset, max_aligned_offset) = {
+         // We call this just to obtain the length of the prefix and suffix.
+         // In the middle we always process two chunks at once.
+         let (prefix, _, suffix) = unsafe { text.align_to::<(Chunk, Chunk)>() };
+         (prefix.len(), len - suffix.len())
+     };
+ 
+     let mut offset = max_aligned_offset;
+     if let Some(index) = text[offset..].iter().rposition(|elt| *elt == x) {
+         return Some(offset + index);
+     }
+ 
+     // Search the body of the text, make sure we don't cross min_aligned_offset.
+     // offset is always aligned, so just testing `>` is sufficient and avoids possible
+     // overflow.
+     let repeated_x = repeat_byte(x);
+     let chunk_bytes = mem::size_of::<Chunk>();
+ 
+     while offset > min_aligned_offset {
+         unsafe {
+             let u = *(ptr.offset(offset as isize - 2 * chunk_bytes as isize) as *const Chunk);
+             let v = *(ptr.offset(offset as isize - chunk_bytes as isize) as *const Chunk);
+ 
+             // Break if there is a matching byte.
+             let zu = contains_zero_byte(u ^ repeated_x);
+             let zv = contains_zero_byte(v ^ repeated_x);
+             if zu || zv {
+                 break;
+             }
+         }
+         offset -= 2 * chunk_bytes;
+     }
+ 
+     // Find the byte before the point the body loop stopped.
+     text[..offset].iter().rposition(|elt| *elt == x)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3188 ----
+ // ignore-tidy-filelength
+ 
+ //! Slice management and manipulation.
+ //!
+ //! For more details see [`std::slice`].
+ //!
+ //! [`std::slice`]: ../../std/slice/index.html
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ use crate::cmp::Ordering::{self, Equal, Greater, Less};
+ use crate::marker::Copy;
+ use crate::mem;
+ use crate::num::NonZeroUsize;
+ use crate::ops::{FnMut, Range, RangeBounds};
+ use crate::option::Option;
+ use crate::option::Option::{None, Some};
+ use crate::ptr;
+ use crate::result::Result;
+ use crate::result::Result::{Err, Ok};
+ 
+ #[unstable(
+     feature = "slice_internals",
+     issue = "none",
+     reason = "exposed from core to be reused in std; use the memchr crate"
+ )]
+ /// Pure rust memchr implementation, taken from rust-memchr
+ pub mod memchr;
+ 
+ mod ascii;
+ mod cmp;
+ pub(crate) mod index;
+ mod iter;
+ mod raw;
+ mod rotate;
+ mod sort;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use iter::{Chunks, ChunksMut, Windows};
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use iter::{Iter, IterMut};
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use iter::{RSplitN, RSplitNMut, Split, SplitMut, SplitN, SplitNMut};
+ 
+ #[stable(feature = "slice_rsplit", since = "1.27.0")]
+ pub use iter::{RSplit, RSplitMut};
+ 
+ #[stable(feature = "chunks_exact", since = "1.31.0")]
+ pub use iter::{ChunksExact, ChunksExactMut};
+ 
+ #[stable(feature = "rchunks", since = "1.31.0")]
+ pub use iter::{RChunks, RChunksExact, RChunksExactMut, RChunksMut};
+ 
+ #[unstable(feature = "array_chunks", issue = "74985")]
+ pub use iter::{ArrayChunks, ArrayChunksMut};
+ 
+ #[unstable(feature = "array_windows", issue = "75027")]
+ pub use iter::ArrayWindows;
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ pub use iter::{SplitInclusive, SplitInclusiveMut};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use raw::{from_raw_parts, from_raw_parts_mut};
+ 
+ #[stable(feature = "from_ref", since = "1.28.0")]
+ pub use raw::{from_mut, from_ref};
+ 
+ // This function is public only because there is no other way to unit test heapsort.
+ #[unstable(feature = "sort_internals", reason = "internal to sort module", issue = "none")]
+ pub use sort::heapsort;
+ 
+ #[stable(feature = "slice_get_slice", since = "1.28.0")]
+ pub use index::SliceIndex;
+ 
+ #[lang = "slice"]
+ #[cfg(not(test))]
+ impl<T> [T] {
+     /// Returns the number of elements in the slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert_eq!(a.len(), 3);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_slice_len", since = "1.32.0")]
+     #[inline]
+     // SAFETY: const sound because we transmute out the length field as a usize (which it must be)
+     #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_union))]
+     #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_union))]
+     pub const fn len(&self) -> usize {
+         // SAFETY: this is safe because `&[T]` and `FatPtr<T>` have the same layout.
+         // Only `std` can make this guarantee.
+         unsafe { crate::ptr::Repr { rust: self }.raw.len }
+     }
+ 
+     /// Returns `true` if the slice has a length of 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// assert!(!a.is_empty());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_slice_is_empty", since = "1.32.0")]
+     #[inline]
+     pub const fn is_empty(&self) -> bool {
+         self.len() == 0
+     }
+ 
+     /// Returns the first element of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [10, 40, 30];
+     /// assert_eq!(Some(&10), v.first());
+     ///
+     /// let w: &[i32] = &[];
+     /// assert_eq!(None, w.first());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn first(&self) -> Option<&T> {
+         if let [first, ..] = self { Some(first) } else { None }
+     }
+ 
+     /// Returns a mutable pointer to the first element of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [0, 1, 2];
+     ///
+     /// if let Some(first) = x.first_mut() {
+     ///     *first = 5;
+     /// }
+     /// assert_eq!(x, &[5, 1, 2]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn first_mut(&mut self) -> Option<&mut T> {
+         if let [first, ..] = self { Some(first) } else { None }
+     }
+ 
+     /// Returns the first and all the rest of the elements of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &[0, 1, 2];
+     ///
+     /// if let Some((first, elements)) = x.split_first() {
+     ///     assert_eq!(first, &0);
+     ///     assert_eq!(elements, &[1, 2]);
+     /// }
+     /// ```
+     #[stable(feature = "slice_splits", since = "1.5.0")]
+     #[inline]
+     pub fn split_first(&self) -> Option<(&T, &[T])> {
+         if let [first, tail @ ..] = self { Some((first, tail)) } else { None }
+     }
+ 
+     /// Returns the first and all the rest of the elements of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [0, 1, 2];
+     ///
+     /// if let Some((first, elements)) = x.split_first_mut() {
+     ///     *first = 3;
+     ///     elements[0] = 4;
+     ///     elements[1] = 5;
+     /// }
+     /// assert_eq!(x, &[3, 4, 5]);
+     /// ```
+     #[stable(feature = "slice_splits", since = "1.5.0")]
+     #[inline]
+     pub fn split_first_mut(&mut self) -> Option<(&mut T, &mut [T])> {
+         if let [first, tail @ ..] = self { Some((first, tail)) } else { None }
+     }
+ 
+     /// Returns the last and all the rest of the elements of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &[0, 1, 2];
+     ///
+     /// if let Some((last, elements)) = x.split_last() {
+     ///     assert_eq!(last, &2);
+     ///     assert_eq!(elements, &[0, 1]);
+     /// }
+     /// ```
+     #[stable(feature = "slice_splits", since = "1.5.0")]
+     #[inline]
+     pub fn split_last(&self) -> Option<(&T, &[T])> {
+         if let [init @ .., last] = self { Some((last, init)) } else { None }
+     }
+ 
+     /// Returns the last and all the rest of the elements of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [0, 1, 2];
+     ///
+     /// if let Some((last, elements)) = x.split_last_mut() {
+     ///     *last = 3;
+     ///     elements[0] = 4;
+     ///     elements[1] = 5;
+     /// }
+     /// assert_eq!(x, &[4, 5, 3]);
+     /// ```
+     #[stable(feature = "slice_splits", since = "1.5.0")]
+     #[inline]
+     pub fn split_last_mut(&mut self) -> Option<(&mut T, &mut [T])> {
+         if let [init @ .., last] = self { Some((last, init)) } else { None }
+     }
+ 
+     /// Returns the last element of the slice, or `None` if it is empty.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [10, 40, 30];
+     /// assert_eq!(Some(&30), v.last());
+     ///
+     /// let w: &[i32] = &[];
+     /// assert_eq!(None, w.last());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn last(&self) -> Option<&T> {
+         if let [.., last] = self { Some(last) } else { None }
+     }
+ 
+     /// Returns a mutable pointer to the last item in the slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [0, 1, 2];
+     ///
+     /// if let Some(last) = x.last_mut() {
+     ///     *last = 10;
+     /// }
+     /// assert_eq!(x, &[0, 1, 10]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn last_mut(&mut self) -> Option<&mut T> {
+         if let [.., last] = self { Some(last) } else { None }
+     }
+ 
+     /// Returns a reference to an element or subslice depending on the type of
+     /// index.
+     ///
+     /// - If given a position, returns a reference to the element at that
+     ///   position or `None` if out of bounds.
+     /// - If given a range, returns the subslice corresponding to that range,
+     ///   or `None` if out of bounds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [10, 40, 30];
+     /// assert_eq!(Some(&40), v.get(1));
+     /// assert_eq!(Some(&[10, 40][..]), v.get(0..2));
+     /// assert_eq!(None, v.get(3));
+     /// assert_eq!(None, v.get(0..4));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn get<I>(&self, index: I) -> Option<&I::Output>
+     where
+         I: SliceIndex<Self>,
+     {
+         index.get(self)
+     }
+ 
+     /// Returns a mutable reference to an element or subslice depending on the
+     /// type of index (see [`get`]) or `None` if the index is out of bounds.
+     ///
+     /// [`get`]: #method.get
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [0, 1, 2];
+     ///
+     /// if let Some(elem) = x.get_mut(1) {
+     ///     *elem = 42;
+     /// }
+     /// assert_eq!(x, &[0, 42, 2]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn get_mut<I>(&mut self, index: I) -> Option<&mut I::Output>
+     where
+         I: SliceIndex<Self>,
+     {
+         index.get_mut(self)
+     }
+ 
+     /// Returns a reference to an element or subslice, without doing bounds
+     /// checking.
+     ///
+     /// For a safe alternative see [`get`].
+     ///
+     /// # Safety
+     ///
+     /// Calling this method with an out-of-bounds index is *[undefined behavior]*
+     /// even if the resulting reference is not used.
+     ///
+     /// [`get`]: #method.get
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &[1, 2, 4];
+     ///
+     /// unsafe {
+     ///     assert_eq!(x.get_unchecked(1), &2);
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub unsafe fn get_unchecked<I>(&self, index: I) -> &I::Output
+     where
+         I: SliceIndex<Self>,
+     {
+         // SAFETY: the caller must uphold most of the safety requirements for `get_unchecked`;
+         // the slice is dereferencable because `self` is a safe reference.
+         // The returned pointer is safe because impls of `SliceIndex` have to guarantee that it is.
+         unsafe { &*index.get_unchecked(self) }
+     }
+ 
+     /// Returns a mutable reference to an element or subslice, without doing
+     /// bounds checking.
+     ///
+     /// For a safe alternative see [`get_mut`].
+     ///
+     /// # Safety
+     ///
+     /// Calling this method with an out-of-bounds index is *[undefined behavior]*
+     /// even if the resulting reference is not used.
+     ///
+     /// [`get_mut`]: #method.get_mut
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [1, 2, 4];
+     ///
+     /// unsafe {
+     ///     let elem = x.get_unchecked_mut(1);
+     ///     *elem = 13;
+     /// }
+     /// assert_eq!(x, &[1, 13, 4]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub unsafe fn get_unchecked_mut<I>(&mut self, index: I) -> &mut I::Output
+     where
+         I: SliceIndex<Self>,
+     {
+         // SAFETY: the caller must uphold the safety requirements for `get_unchecked_mut`;
+         // the slice is dereferencable because `self` is a safe reference.
+         // The returned pointer is safe because impls of `SliceIndex` have to guarantee that it is.
+         unsafe { &mut *index.get_unchecked_mut(self) }
+     }
+ 
+     /// Returns a raw pointer to the slice's buffer.
+     ///
+     /// The caller must ensure that the slice outlives the pointer this
+     /// function returns, or else it will end up pointing to garbage.
+     ///
+     /// The caller must also ensure that the memory the pointer (non-transitively) points to
+     /// is never written to (except inside an `UnsafeCell`) using this pointer or any pointer
+     /// derived from it. If you need to mutate the contents of the slice, use [`as_mut_ptr`].
+     ///
+     /// Modifying the container referenced by this slice may cause its buffer
+     /// to be reallocated, which would also make any pointers to it invalid.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &[1, 2, 4];
+     /// let x_ptr = x.as_ptr();
+     ///
+     /// unsafe {
+     ///     for i in 0..x.len() {
+     ///         assert_eq!(x.get_unchecked(i), &*x_ptr.add(i));
+     ///     }
+     /// }
+     /// ```
+     ///
+     /// [`as_mut_ptr`]: #method.as_mut_ptr
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_slice_as_ptr", since = "1.32.0")]
+     #[inline]
+     pub const fn as_ptr(&self) -> *const T {
+         self as *const [T] as *const T
+     }
+ 
+     /// Returns an unsafe mutable pointer to the slice's buffer.
+     ///
+     /// The caller must ensure that the slice outlives the pointer this
+     /// function returns, or else it will end up pointing to garbage.
+     ///
+     /// Modifying the container referenced by this slice may cause its buffer
+     /// to be reallocated, which would also make any pointers to it invalid.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [1, 2, 4];
+     /// let x_ptr = x.as_mut_ptr();
+     ///
+     /// unsafe {
+     ///     for i in 0..x.len() {
+     ///         *x_ptr.add(i) += 2;
+     ///     }
+     /// }
+     /// assert_eq!(x, &[3, 4, 6]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn as_mut_ptr(&mut self) -> *mut T {
+         self as *mut [T] as *mut T
+     }
+ 
+     /// Returns the two raw pointers spanning the slice.
+     ///
+     /// The returned range is half-open, which means that the end pointer
+     /// points *one past* the last element of the slice. This way, an empty
+     /// slice is represented by two equal pointers, and the difference between
+     /// the two pointers represents the size of the slice.
+     ///
+     /// See [`as_ptr`] for warnings on using these pointers. The end pointer
+     /// requires extra caution, as it does not point to a valid element in the
+     /// slice.
+     ///
+     /// This function is useful for interacting with foreign interfaces which
+     /// use two pointers to refer to a range of elements in memory, as is
+     /// common in C++.
+     ///
+     /// It can also be useful to check if a pointer to an element refers to an
+     /// element of this slice:
+     ///
+     /// ```
+     /// let a = [1, 2, 3];
+     /// let x = &a[1] as *const _;
+     /// let y = &5 as *const _;
+     ///
+     /// assert!(a.as_ptr_range().contains(&x));
+     /// assert!(!a.as_ptr_range().contains(&y));
+     /// ```
+     ///
+     /// [`as_ptr`]: #method.as_ptr
+     #[stable(feature = "slice_ptr_range", since = "1.48.0")]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn as_ptr_range(&self) -> Range<*const T> {
+         let start = self.as_ptr();
+         // SAFETY: The `add` here is safe, because:
+         //
+         //   - Both pointers are part of the same object, as pointing directly
+         //     past the object also counts.
+         //
+         //   - The size of the slice is never larger than isize::MAX bytes, as
+         //     noted here:
+         //       - https://github.com/rust-lang/unsafe-code-guidelines/issues/102#issuecomment-473340447
+         //       - https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+         //       - https://doc.rust-lang.org/core/slice/fn.from_raw_parts.html#safety
+         //     (This doesn't seem normative yet, but the very same assumption is
+         //     made in many places, including the Index implementation of slices.)
+         //
+         //   - There is no wrapping around involved, as slices do not wrap past
+         //     the end of the address space.
+         //
+         // See the documentation of pointer::add.
+         let end = unsafe { start.add(self.len()) };
+         start..end
+     }
+ 
+     /// Returns the two unsafe mutable pointers spanning the slice.
+     ///
+     /// The returned range is half-open, which means that the end pointer
+     /// points *one past* the last element of the slice. This way, an empty
+     /// slice is represented by two equal pointers, and the difference between
+     /// the two pointers represents the size of the slice.
+     ///
+     /// See [`as_mut_ptr`] for warnings on using these pointers. The end
+     /// pointer requires extra caution, as it does not point to a valid element
+     /// in the slice.
+     ///
+     /// This function is useful for interacting with foreign interfaces which
+     /// use two pointers to refer to a range of elements in memory, as is
+     /// common in C++.
+     ///
+     /// [`as_mut_ptr`]: #method.as_mut_ptr
+     #[stable(feature = "slice_ptr_range", since = "1.48.0")]
+     #[rustc_const_unstable(feature = "const_ptr_offset", issue = "71499")]
+     #[inline]
+     pub const fn as_mut_ptr_range(&mut self) -> Range<*mut T> {
+         let start = self.as_mut_ptr();
+         // SAFETY: See as_ptr_range() above for why `add` here is safe.
+         let end = unsafe { start.add(self.len()) };
+         start..end
+     }
+ 
+     /// Swaps two elements in the slice.
+     ///
+     /// # Arguments
+     ///
+     /// * a - The index of the first element
+     /// * b - The index of the second element
+     ///
+     /// # Panics
+     ///
+     /// Panics if `a` or `b` are out of bounds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = ["a", "b", "c", "d"];
+     /// v.swap(1, 3);
+     /// assert!(v == ["a", "d", "c", "b"]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn swap(&mut self, a: usize, b: usize) {
+         // Can't take two mutable loans from one vector, so instead just cast
+         // them to their raw pointers to do the swap.
+         let pa: *mut T = &mut self[a];
+         let pb: *mut T = &mut self[b];
+         // SAFETY: `pa` and `pb` have been created from safe mutable references and refer
+         // to elements in the slice and therefore are guaranteed to be valid and aligned.
+         // Note that accessing the elements behind `a` and `b` is checked and will
+         // panic when out of bounds.
+         unsafe {
+             ptr::swap(pa, pb);
+         }
+     }
+ 
+     /// Reverses the order of elements in the slice, in place.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [1, 2, 3];
+     /// v.reverse();
+     /// assert!(v == [3, 2, 1]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn reverse(&mut self) {
+         let mut i: usize = 0;
+         let ln = self.len();
+ 
+         // For very small types, all the individual reads in the normal
+         // path perform poorly.  We can do better, given efficient unaligned
+         // load/store, by loading a larger chunk and reversing a register.
+ 
+         // Ideally LLVM would do this for us, as it knows better than we do
+         // whether unaligned reads are efficient (since that changes between
+         // different ARM versions, for example) and what the best chunk size
+         // would be.  Unfortunately, as of LLVM 4.0 (2017-05) it only unrolls
+         // the loop, so we need to do this ourselves.  (Hypothesis: reverse
+         // is troublesome because the sides can be aligned differently --
+         // will be, when the length is odd -- so there's no way of emitting
+         // pre- and postludes to use fully-aligned SIMD in the middle.)
+ 
+         let fast_unaligned = cfg!(any(target_arch = "x86", target_arch = "x86_64"));
+ 
+         if fast_unaligned && mem::size_of::<T>() == 1 {
+             // Use the llvm.bswap intrinsic to reverse u8s in a usize
+             let chunk = mem::size_of::<usize>();
+             while i + chunk - 1 < ln / 2 {
+                 // SAFETY: There are several things to check here:
+                 //
+                 // - Note that `chunk` is either 4 or 8 due to the cfg check
+                 //   above. So `chunk - 1` is positive.
+                 // - Indexing with index `i` is fine as the loop check guarantees
+                 //   `i + chunk - 1 < ln / 2`
+                 //   <=> `i < ln / 2 - (chunk - 1) < ln / 2 < ln`.
+                 // - Indexing with index `ln - i - chunk = ln - (i + chunk)` is fine:
+                 //   - `i + chunk > 0` is trivially true.
+                 //   - The loop check guarantees:
+                 //     `i + chunk - 1 < ln / 2`
+                 //     <=> `i + chunk ≤ ln / 2 ≤ ln`, thus subtraction does not underflow.
+                 // - The `read_unaligned` and `write_unaligned` calls are fine:
+                 //   - `pa` points to index `i` where `i < ln / 2 - (chunk - 1)`
+                 //     (see above) and `pb` points to index `ln - i - chunk`, so
+                 //     both are at least `chunk`
+                 //     many bytes away from the end of `self`.
+                 //   - Any initialized memory is valid `usize`.
+                 unsafe {
+                     let pa: *mut T = self.get_unchecked_mut(i);
+                     let pb: *mut T = self.get_unchecked_mut(ln - i - chunk);
+                     let va = ptr::read_unaligned(pa as *mut usize);
+                     let vb = ptr::read_unaligned(pb as *mut usize);
+                     ptr::write_unaligned(pa as *mut usize, vb.swap_bytes());
+                     ptr::write_unaligned(pb as *mut usize, va.swap_bytes());
+                 }
+                 i += chunk;
+             }
+         }
+ 
+         if fast_unaligned && mem::size_of::<T>() == 2 {
+             // Use rotate-by-16 to reverse u16s in a u32
+             let chunk = mem::size_of::<u32>() / 2;
+             while i + chunk - 1 < ln / 2 {
+                 // SAFETY: An unaligned u32 can be read from `i` if `i + 1 < ln`
+                 // (and obviously `i < ln`), because each element is 2 bytes and
+                 // we're reading 4.
+                 //
+                 // `i + chunk - 1 < ln / 2` # while condition
+                 // `i + 2 - 1 < ln / 2`
+                 // `i + 1 < ln / 2`
+                 //
+                 // Since it's less than the length divided by 2, then it must be
+                 // in bounds.
+                 //
+                 // This also means that the condition `0 < i + chunk <= ln` is
+                 // always respected, ensuring the `pb` pointer can be used
+                 // safely.
+                 unsafe {
+                     let pa: *mut T = self.get_unchecked_mut(i);
+                     let pb: *mut T = self.get_unchecked_mut(ln - i - chunk);
+                     let va = ptr::read_unaligned(pa as *mut u32);
+                     let vb = ptr::read_unaligned(pb as *mut u32);
+                     ptr::write_unaligned(pa as *mut u32, vb.rotate_left(16));
+                     ptr::write_unaligned(pb as *mut u32, va.rotate_left(16));
+                 }
+                 i += chunk;
+             }
+         }
+ 
+         while i < ln / 2 {
+             // SAFETY: `i` is inferior to half the length of the slice so
+             // accessing `i` and `ln - i - 1` is safe (`i` starts at 0 and
+             // will not go further than `ln / 2 - 1`).
+             // The resulting pointers `pa` and `pb` are therefore valid and
+             // aligned, and can be read from and written to.
+             unsafe {
+                 // Unsafe swap to avoid the bounds check in safe swap.
+                 let pa: *mut T = self.get_unchecked_mut(i);
+                 let pb: *mut T = self.get_unchecked_mut(ln - i - 1);
+                 ptr::swap(pa, pb);
+             }
+             i += 1;
+         }
+     }
+ 
+     /// Returns an iterator over the slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &[1, 2, 4];
+     /// let mut iterator = x.iter();
+     ///
+     /// assert_eq!(iterator.next(), Some(&1));
+     /// assert_eq!(iterator.next(), Some(&2));
+     /// assert_eq!(iterator.next(), Some(&4));
+     /// assert_eq!(iterator.next(), None);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn iter(&self) -> Iter<'_, T> {
+         Iter::new(self)
+     }
+ 
+     /// Returns an iterator that allows modifying each value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let x = &mut [1, 2, 4];
+     /// for elem in x.iter_mut() {
+     ///     *elem += 2;
+     /// }
+     /// assert_eq!(x, &[3, 4, 6]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn iter_mut(&mut self) -> IterMut<'_, T> {
+         IterMut::new(self)
+     }
+ 
+     /// Returns an iterator over all contiguous windows of length
+     /// `size`. The windows overlap. If the slice is shorter than
+     /// `size`, the iterator returns no values.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = ['r', 'u', 's', 't'];
+     /// let mut iter = slice.windows(2);
+     /// assert_eq!(iter.next().unwrap(), &['r', 'u']);
+     /// assert_eq!(iter.next().unwrap(), &['u', 's']);
+     /// assert_eq!(iter.next().unwrap(), &['s', 't']);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// If the slice is shorter than `size`:
+     ///
+     /// ```
+     /// let slice = ['f', 'o', 'o'];
+     /// let mut iter = slice.windows(4);
+     /// assert!(iter.next().is_none());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn windows(&self, size: usize) -> Windows<'_, T> {
+         let size = NonZeroUsize::new(size).expect("size is zero");
+         Windows::new(self, size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the
+     /// beginning of the slice.
+     ///
+     /// The chunks are slices and do not overlap. If `chunk_size` does not divide the length of the
+     /// slice, then the last chunk will not have length `chunk_size`.
+     ///
+     /// See [`chunks_exact`] for a variant of this iterator that returns chunks of always exactly
+     /// `chunk_size` elements, and [`rchunks`] for the same iterator but starting at the end of the
+     /// slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = ['l', 'o', 'r', 'e', 'm'];
+     /// let mut iter = slice.chunks(2);
+     /// assert_eq!(iter.next().unwrap(), &['l', 'o']);
+     /// assert_eq!(iter.next().unwrap(), &['r', 'e']);
+     /// assert_eq!(iter.next().unwrap(), &['m']);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// [`chunks_exact`]: #method.chunks_exact
+     /// [`rchunks`]: #method.rchunks
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn chunks(&self, chunk_size: usize) -> Chunks<'_, T> {
+         assert_ne!(chunk_size, 0);
+         Chunks::new(self, chunk_size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the
+     /// beginning of the slice.
+     ///
+     /// The chunks are mutable slices, and do not overlap. If `chunk_size` does not divide the
+     /// length of the slice, then the last chunk will not have length `chunk_size`.
+     ///
+     /// See [`chunks_exact_mut`] for a variant of this iterator that returns chunks of always
+     /// exactly `chunk_size` elements, and [`rchunks_mut`] for the same iterator but starting at
+     /// the end of the slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = &mut [0, 0, 0, 0, 0];
+     /// let mut count = 1;
+     ///
+     /// for chunk in v.chunks_mut(2) {
+     ///     for elem in chunk.iter_mut() {
+     ///         *elem += count;
+     ///     }
+     ///     count += 1;
+     /// }
+     /// assert_eq!(v, &[1, 1, 2, 2, 3]);
+     /// ```
+     ///
+     /// [`chunks_exact_mut`]: #method.chunks_exact_mut
+     /// [`rchunks_mut`]: #method.rchunks_mut
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn chunks_mut(&mut self, chunk_size: usize) -> ChunksMut<'_, T> {
+         assert_ne!(chunk_size, 0);
+         ChunksMut::new(self, chunk_size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the
+     /// beginning of the slice.
+     ///
+     /// The chunks are slices and do not overlap. If `chunk_size` does not divide the length of the
+     /// slice, then the last up to `chunk_size-1` elements will be omitted and can be retrieved
+     /// from the `remainder` function of the iterator.
+     ///
+     /// Due to each chunk having exactly `chunk_size` elements, the compiler can often optimize the
+     /// resulting code better than in the case of [`chunks`].
+     ///
+     /// See [`chunks`] for a variant of this iterator that also returns the remainder as a smaller
+     /// chunk, and [`rchunks_exact`] for the same iterator but starting at the end of the slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = ['l', 'o', 'r', 'e', 'm'];
+     /// let mut iter = slice.chunks_exact(2);
+     /// assert_eq!(iter.next().unwrap(), &['l', 'o']);
+     /// assert_eq!(iter.next().unwrap(), &['r', 'e']);
+     /// assert!(iter.next().is_none());
+     /// assert_eq!(iter.remainder(), &['m']);
+     /// ```
+     ///
+     /// [`chunks`]: #method.chunks
+     /// [`rchunks_exact`]: #method.rchunks_exact
+     #[stable(feature = "chunks_exact", since = "1.31.0")]
+     #[inline]
+     pub fn chunks_exact(&self, chunk_size: usize) -> ChunksExact<'_, T> {
+         assert_ne!(chunk_size, 0);
+         ChunksExact::new(self, chunk_size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the
+     /// beginning of the slice.
+     ///
+     /// The chunks are mutable slices, and do not overlap. If `chunk_size` does not divide the
+     /// length of the slice, then the last up to `chunk_size-1` elements will be omitted and can be
+     /// retrieved from the `into_remainder` function of the iterator.
+     ///
+     /// Due to each chunk having exactly `chunk_size` elements, the compiler can often optimize the
+     /// resulting code better than in the case of [`chunks_mut`].
+     ///
+     /// See [`chunks_mut`] for a variant of this iterator that also returns the remainder as a
+     /// smaller chunk, and [`rchunks_exact_mut`] for the same iterator but starting at the end of
+     /// the slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = &mut [0, 0, 0, 0, 0];
+     /// let mut count = 1;
+     ///
+     /// for chunk in v.chunks_exact_mut(2) {
+     ///     for elem in chunk.iter_mut() {
+     ///         *elem += count;
+     ///     }
+     ///     count += 1;
+     /// }
+     /// assert_eq!(v, &[1, 1, 2, 2, 0]);
+     /// ```
+     ///
+     /// [`chunks_mut`]: #method.chunks_mut
+     /// [`rchunks_exact_mut`]: #method.rchunks_exact_mut
+     #[stable(feature = "chunks_exact", since = "1.31.0")]
+     #[inline]
+     pub fn chunks_exact_mut(&mut self, chunk_size: usize) -> ChunksExactMut<'_, T> {
+         assert_ne!(chunk_size, 0);
+         ChunksExactMut::new(self, chunk_size)
+     }
+ 
+     /// Splits the slice into a slice of `N`-element arrays,
+     /// starting at the beginning of the slice,
+     /// and a remainder slice with length strictly less than `N`.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `N` is 0. This check will most probably get changed to a compile time
+     /// error before this method gets stabilized.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_as_chunks)]
+     /// let slice = ['l', 'o', 'r', 'e', 'm'];
+     /// let (chunks, remainder) = slice.as_chunks();
+     /// assert_eq!(chunks, &[['l', 'o'], ['r', 'e']]);
+     /// assert_eq!(remainder, &['m']);
+     /// ```
+     #[unstable(feature = "slice_as_chunks", issue = "74985")]
+     #[inline]
+     pub fn as_chunks<const N: usize>(&self) -> (&[[T; N]], &[T]) {
+         assert_ne!(N, 0);
+         let len = self.len() / N;
+         let (multiple_of_n, remainder) = self.split_at(len * N);
+         // SAFETY: We cast a slice of `len * N` elements into
+         // a slice of `len` many `N` elements chunks.
+         let array_slice: &[[T; N]] = unsafe { from_raw_parts(multiple_of_n.as_ptr().cast(), len) };
+         (array_slice, remainder)
+     }
+ 
+     /// Returns an iterator over `N` elements of the slice at a time, starting at the
+     /// beginning of the slice.
+     ///
+     /// The chunks are array references and do not overlap. If `N` does not divide the
+     /// length of the slice, then the last up to `N-1` elements will be omitted and can be
+     /// retrieved from the `remainder` function of the iterator.
+     ///
+     /// This method is the const generic equivalent of [`chunks_exact`].
+     ///
+     /// # Panics
+     ///
+     /// Panics if `N` is 0. This check will most probably get changed to a compile time
+     /// error before this method gets stabilized.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(array_chunks)]
+     /// let slice = ['l', 'o', 'r', 'e', 'm'];
+     /// let mut iter = slice.array_chunks();
+     /// assert_eq!(iter.next().unwrap(), &['l', 'o']);
+     /// assert_eq!(iter.next().unwrap(), &['r', 'e']);
+     /// assert!(iter.next().is_none());
+     /// assert_eq!(iter.remainder(), &['m']);
+     /// ```
+     ///
+     /// [`chunks_exact`]: #method.chunks_exact
+     #[unstable(feature = "array_chunks", issue = "74985")]
+     #[inline]
+     pub fn array_chunks<const N: usize>(&self) -> ArrayChunks<'_, T, N> {
+         assert_ne!(N, 0);
+         ArrayChunks::new(self)
+     }
+ 
+     /// Splits the slice into a slice of `N`-element arrays,
+     /// starting at the beginning of the slice,
+     /// and a remainder slice with length strictly less than `N`.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `N` is 0. This check will most probably get changed to a compile time
+     /// error before this method gets stabilized.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_as_chunks)]
+     /// let v = &mut [0, 0, 0, 0, 0];
+     /// let mut count = 1;
+     ///
+     /// let (chunks, remainder) = v.as_chunks_mut();
+     /// remainder[0] = 9;
+     /// for chunk in chunks {
+     ///     *chunk = [count; 2];
+     ///     count += 1;
+     /// }
+     /// assert_eq!(v, &[1, 1, 2, 2, 9]);
+     /// ```
+     #[unstable(feature = "slice_as_chunks", issue = "74985")]
+     #[inline]
+     pub fn as_chunks_mut<const N: usize>(&mut self) -> (&mut [[T; N]], &mut [T]) {
+         assert_ne!(N, 0);
+         let len = self.len() / N;
+         let (multiple_of_n, remainder) = self.split_at_mut(len * N);
+         let array_slice: &mut [[T; N]] =
+             // SAFETY: We cast a slice of `len * N` elements into
+             // a slice of `len` many `N` elements chunks.
+             unsafe { from_raw_parts_mut(multiple_of_n.as_mut_ptr().cast(), len) };
+         (array_slice, remainder)
+     }
+ 
+     /// Returns an iterator over `N` elements of the slice at a time, starting at the
+     /// beginning of the slice.
+     ///
+     /// The chunks are mutable array references and do not overlap. If `N` does not divide
+     /// the length of the slice, then the last up to `N-1` elements will be omitted and
+     /// can be retrieved from the `into_remainder` function of the iterator.
+     ///
+     /// This method is the const generic equivalent of [`chunks_exact_mut`].
+     ///
+     /// # Panics
+     ///
+     /// Panics if `N` is 0. This check will most probably get changed to a compile time
+     /// error before this method gets stabilized.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(array_chunks)]
+     /// let v = &mut [0, 0, 0, 0, 0];
+     /// let mut count = 1;
+     ///
+     /// for chunk in v.array_chunks_mut() {
+     ///     *chunk = [count; 2];
+     ///     count += 1;
+     /// }
+     /// assert_eq!(v, &[1, 1, 2, 2, 0]);
+     /// ```
+     ///
+     /// [`chunks_exact_mut`]: #method.chunks_exact_mut
+     #[unstable(feature = "array_chunks", issue = "74985")]
+     #[inline]
+     pub fn array_chunks_mut<const N: usize>(&mut self) -> ArrayChunksMut<'_, T, N> {
+         assert_ne!(N, 0);
+         ArrayChunksMut::new(self)
+     }
+ 
+     /// Returns an iterator over overlapping windows of `N` elements of  a slice,
+     /// starting at the beginning of the slice.
+     ///
+     /// This is the const generic equivalent of [`windows`].
+     ///
+     /// If `N` is greater than the size of the slice, it will return no windows.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `N` is 0. This check will most probably get changed to a compile time
+     /// error before this method gets stabilized.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(array_windows)]
+     /// let slice = [0, 1, 2, 3];
+     /// let mut iter = slice.array_windows();
+     /// assert_eq!(iter.next().unwrap(), &[0, 1]);
+     /// assert_eq!(iter.next().unwrap(), &[1, 2]);
+     /// assert_eq!(iter.next().unwrap(), &[2, 3]);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// [`windows`]: #method.windows
+     #[unstable(feature = "array_windows", issue = "75027")]
+     #[inline]
+     pub fn array_windows<const N: usize>(&self) -> ArrayWindows<'_, T, N> {
+         assert_ne!(N, 0);
+         ArrayWindows::new(self)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the end
+     /// of the slice.
+     ///
+     /// The chunks are slices and do not overlap. If `chunk_size` does not divide the length of the
+     /// slice, then the last chunk will not have length `chunk_size`.
+     ///
+     /// See [`rchunks_exact`] for a variant of this iterator that returns chunks of always exactly
+     /// `chunk_size` elements, and [`chunks`] for the same iterator but starting at the beginning
+     /// of the slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = ['l', 'o', 'r', 'e', 'm'];
+     /// let mut iter = slice.rchunks(2);
+     /// assert_eq!(iter.next().unwrap(), &['e', 'm']);
+     /// assert_eq!(iter.next().unwrap(), &['o', 'r']);
+     /// assert_eq!(iter.next().unwrap(), &['l']);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// [`rchunks_exact`]: #method.rchunks_exact
+     /// [`chunks`]: #method.chunks
+     #[stable(feature = "rchunks", since = "1.31.0")]
+     #[inline]
+     pub fn rchunks(&self, chunk_size: usize) -> RChunks<'_, T> {
+         assert!(chunk_size != 0);
+         RChunks::new(self, chunk_size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the end
+     /// of the slice.
+     ///
+     /// The chunks are mutable slices, and do not overlap. If `chunk_size` does not divide the
+     /// length of the slice, then the last chunk will not have length `chunk_size`.
+     ///
+     /// See [`rchunks_exact_mut`] for a variant of this iterator that returns chunks of always
+     /// exactly `chunk_size` elements, and [`chunks_mut`] for the same iterator but starting at the
+     /// beginning of the slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = &mut [0, 0, 0, 0, 0];
+     /// let mut count = 1;
+     ///
+     /// for chunk in v.rchunks_mut(2) {
+     ///     for elem in chunk.iter_mut() {
+     ///         *elem += count;
+     ///     }
+     ///     count += 1;
+     /// }
+     /// assert_eq!(v, &[3, 2, 2, 1, 1]);
+     /// ```
+     ///
+     /// [`rchunks_exact_mut`]: #method.rchunks_exact_mut
+     /// [`chunks_mut`]: #method.chunks_mut
+     #[stable(feature = "rchunks", since = "1.31.0")]
+     #[inline]
+     pub fn rchunks_mut(&mut self, chunk_size: usize) -> RChunksMut<'_, T> {
+         assert!(chunk_size != 0);
+         RChunksMut::new(self, chunk_size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the
+     /// end of the slice.
+     ///
+     /// The chunks are slices and do not overlap. If `chunk_size` does not divide the length of the
+     /// slice, then the last up to `chunk_size-1` elements will be omitted and can be retrieved
+     /// from the `remainder` function of the iterator.
+     ///
+     /// Due to each chunk having exactly `chunk_size` elements, the compiler can often optimize the
+     /// resulting code better than in the case of [`chunks`].
+     ///
+     /// See [`rchunks`] for a variant of this iterator that also returns the remainder as a smaller
+     /// chunk, and [`chunks_exact`] for the same iterator but starting at the beginning of the
+     /// slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = ['l', 'o', 'r', 'e', 'm'];
+     /// let mut iter = slice.rchunks_exact(2);
+     /// assert_eq!(iter.next().unwrap(), &['e', 'm']);
+     /// assert_eq!(iter.next().unwrap(), &['o', 'r']);
+     /// assert!(iter.next().is_none());
+     /// assert_eq!(iter.remainder(), &['l']);
+     /// ```
+     ///
+     /// [`chunks`]: #method.chunks
+     /// [`rchunks`]: #method.rchunks
+     /// [`chunks_exact`]: #method.chunks_exact
+     #[stable(feature = "rchunks", since = "1.31.0")]
+     #[inline]
+     pub fn rchunks_exact(&self, chunk_size: usize) -> RChunksExact<'_, T> {
+         assert!(chunk_size != 0);
+         RChunksExact::new(self, chunk_size)
+     }
+ 
+     /// Returns an iterator over `chunk_size` elements of the slice at a time, starting at the end
+     /// of the slice.
+     ///
+     /// The chunks are mutable slices, and do not overlap. If `chunk_size` does not divide the
+     /// length of the slice, then the last up to `chunk_size-1` elements will be omitted and can be
+     /// retrieved from the `into_remainder` function of the iterator.
+     ///
+     /// Due to each chunk having exactly `chunk_size` elements, the compiler can often optimize the
+     /// resulting code better than in the case of [`chunks_mut`].
+     ///
+     /// See [`rchunks_mut`] for a variant of this iterator that also returns the remainder as a
+     /// smaller chunk, and [`chunks_exact_mut`] for the same iterator but starting at the beginning
+     /// of the slice.
+     ///
+     /// # Panics
+     ///
+     /// Panics if `chunk_size` is 0.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = &mut [0, 0, 0, 0, 0];
+     /// let mut count = 1;
+     ///
+     /// for chunk in v.rchunks_exact_mut(2) {
+     ///     for elem in chunk.iter_mut() {
+     ///         *elem += count;
+     ///     }
+     ///     count += 1;
+     /// }
+     /// assert_eq!(v, &[0, 2, 2, 1, 1]);
+     /// ```
+     ///
+     /// [`chunks_mut`]: #method.chunks_mut
+     /// [`rchunks_mut`]: #method.rchunks_mut
+     /// [`chunks_exact_mut`]: #method.chunks_exact_mut
+     #[stable(feature = "rchunks", since = "1.31.0")]
+     #[inline]
+     pub fn rchunks_exact_mut(&mut self, chunk_size: usize) -> RChunksExactMut<'_, T> {
+         assert!(chunk_size != 0);
+         RChunksExactMut::new(self, chunk_size)
+     }
+ 
+     /// Divides one slice into two at an index.
+     ///
+     /// The first will contain all indices from `[0, mid)` (excluding
+     /// the index `mid` itself) and the second will contain all
+     /// indices from `[mid, len)` (excluding the index `len` itself).
+     ///
+     /// # Panics
+     ///
+     /// Panics if `mid > len`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [1, 2, 3, 4, 5, 6];
+     ///
+     /// {
+     ///    let (left, right) = v.split_at(0);
+     ///    assert_eq!(left, []);
+     ///    assert_eq!(right, [1, 2, 3, 4, 5, 6]);
+     /// }
+     ///
+     /// {
+     ///     let (left, right) = v.split_at(2);
+     ///     assert_eq!(left, [1, 2]);
+     ///     assert_eq!(right, [3, 4, 5, 6]);
+     /// }
+     ///
+     /// {
+     ///     let (left, right) = v.split_at(6);
+     ///     assert_eq!(left, [1, 2, 3, 4, 5, 6]);
+     ///     assert_eq!(right, []);
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn split_at(&self, mid: usize) -> (&[T], &[T]) {
+         assert!(mid <= self.len());
+         // SAFETY: `[ptr; mid]` and `[mid; len]` are inside `self`, which
+         // fulfills the requirements of `from_raw_parts_mut`.
+         unsafe { self.split_at_unchecked(mid) }
+     }
+ 
+     /// Divides one mutable slice into two at an index.
+     ///
+     /// The first will contain all indices from `[0, mid)` (excluding
+     /// the index `mid` itself) and the second will contain all
+     /// indices from `[mid, len)` (excluding the index `len` itself).
+     ///
+     /// # Panics
+     ///
+     /// Panics if `mid > len`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [1, 0, 3, 0, 5, 6];
+     /// // scoped to restrict the lifetime of the borrows
+     /// {
+     ///     let (left, right) = v.split_at_mut(2);
+     ///     assert_eq!(left, [1, 0]);
+     ///     assert_eq!(right, [3, 0, 5, 6]);
+     ///     left[1] = 2;
+     ///     right[1] = 4;
+     /// }
+     /// assert_eq!(v, [1, 2, 3, 4, 5, 6]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn split_at_mut(&mut self, mid: usize) -> (&mut [T], &mut [T]) {
+         assert!(mid <= self.len());
+         // SAFETY: `[ptr; mid]` and `[mid; len]` are inside `self`, which
+         // fulfills the requirements of `from_raw_parts_mut`.
+         unsafe { self.split_at_mut_unchecked(mid) }
+     }
+ 
+     /// Divides one slice into two at an index, without doing bounds checking.
+     ///
+     /// The first will contain all indices from `[0, mid)` (excluding
+     /// the index `mid` itself) and the second will contain all
+     /// indices from `[mid, len)` (excluding the index `len` itself).
+     ///
+     /// For a safe alternative see [`split_at`].
+     ///
+     /// # Safety
+     ///
+     /// Calling this method with an out-of-bounds index is *[undefined behavior]*
+     /// even if the resulting reference is not used. The caller has to ensure that
+     /// `0 <= mid <= self.len()`.
+     ///
+     /// [`split_at`]: #method.split_at
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```compile_fail
+     /// #![feature(slice_split_at_unchecked)]
+     ///
+     /// let v = [1, 2, 3, 4, 5, 6];
+     ///
+     /// unsafe {
+     ///    let (left, right) = v.split_at_unchecked(0);
+     ///    assert_eq!(left, []);
+     ///    assert_eq!(right, [1, 2, 3, 4, 5, 6]);
+     /// }
+     ///
+     /// unsafe {
+     ///     let (left, right) = v.split_at_unchecked(2);
+     ///     assert_eq!(left, [1, 2]);
+     ///     assert_eq!(right, [3, 4, 5, 6]);
+     /// }
+     ///
+     /// unsafe {
+     ///     let (left, right) = v.split_at_unchecked(6);
+     ///     assert_eq!(left, [1, 2, 3, 4, 5, 6]);
+     ///     assert_eq!(right, []);
+     /// }
+     /// ```
+     #[unstable(feature = "slice_split_at_unchecked", reason = "new API", issue = "76014")]
+     #[inline]
+     unsafe fn split_at_unchecked(&self, mid: usize) -> (&[T], &[T]) {
+         // SAFETY: Caller has to check that `0 <= mid <= self.len()`
+         unsafe { (self.get_unchecked(..mid), self.get_unchecked(mid..)) }
+     }
+ 
+     /// Divides one mutable slice into two at an index, without doing bounds checking.
+     ///
+     /// The first will contain all indices from `[0, mid)` (excluding
+     /// the index `mid` itself) and the second will contain all
+     /// indices from `[mid, len)` (excluding the index `len` itself).
+     ///
+     /// For a safe alternative see [`split_at_mut`].
+     ///
+     /// # Safety
+     ///
+     /// Calling this method with an out-of-bounds index is *[undefined behavior]*
+     /// even if the resulting reference is not used. The caller has to ensure that
+     /// `0 <= mid <= self.len()`.
+     ///
+     /// [`split_at_mut`]: #method.split_at_mut
+     /// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+     ///
+     /// # Examples
+     ///
+     /// ```compile_fail
+     /// #![feature(slice_split_at_unchecked)]
+     ///
+     /// let mut v = [1, 0, 3, 0, 5, 6];
+     /// // scoped to restrict the lifetime of the borrows
+     /// unsafe {
+     ///     let (left, right) = v.split_at_mut_unchecked(2);
+     ///     assert_eq!(left, [1, 0]);
+     ///     assert_eq!(right, [3, 0, 5, 6]);
+     ///     left[1] = 2;
+     ///     right[1] = 4;
+     /// }
+     /// assert_eq!(v, [1, 2, 3, 4, 5, 6]);
+     /// ```
+     #[unstable(feature = "slice_split_at_unchecked", reason = "new API", issue = "76014")]
+     #[inline]
+     unsafe fn split_at_mut_unchecked(&mut self, mid: usize) -> (&mut [T], &mut [T]) {
+         let len = self.len();
+         let ptr = self.as_mut_ptr();
+ 
+         // SAFETY: Caller has to check that `0 <= mid <= self.len()`.
+         //
+         // `[ptr; mid]` and `[mid; len]` are not overlapping, so returning a mutable reference
+         // is fine.
+         unsafe { (from_raw_parts_mut(ptr, mid), from_raw_parts_mut(ptr.add(mid), len - mid)) }
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred`. The matched element is not contained in the subslices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = [10, 40, 33, 20];
+     /// let mut iter = slice.split(|num| num % 3 == 0);
+     ///
+     /// assert_eq!(iter.next().unwrap(), &[10, 40]);
+     /// assert_eq!(iter.next().unwrap(), &[20]);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// If the first element is matched, an empty slice will be the first item
+     /// returned by the iterator. Similarly, if the last element in the slice
+     /// is matched, an empty slice will be the last item returned by the
+     /// iterator:
+     ///
+     /// ```
+     /// let slice = [10, 40, 33];
+     /// let mut iter = slice.split(|num| num % 3 == 0);
+     ///
+     /// assert_eq!(iter.next().unwrap(), &[10, 40]);
+     /// assert_eq!(iter.next().unwrap(), &[]);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// If two matched elements are directly adjacent, an empty slice will be
+     /// present between them:
+     ///
+     /// ```
+     /// let slice = [10, 6, 33, 20];
+     /// let mut iter = slice.split(|num| num % 3 == 0);
+     ///
+     /// assert_eq!(iter.next().unwrap(), &[10]);
+     /// assert_eq!(iter.next().unwrap(), &[]);
+     /// assert_eq!(iter.next().unwrap(), &[20]);
+     /// assert!(iter.next().is_none());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn split<F>(&self, pred: F) -> Split<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         Split::new(self, pred)
+     }
+ 
+     /// Returns an iterator over mutable subslices separated by elements that
+     /// match `pred`. The matched element is not contained in the subslices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [10, 40, 30, 20, 60, 50];
+     ///
+     /// for group in v.split_mut(|num| *num % 3 == 0) {
+     ///     group[0] = 1;
+     /// }
+     /// assert_eq!(v, [1, 40, 30, 1, 60, 1]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn split_mut<F>(&mut self, pred: F) -> SplitMut<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         SplitMut::new(self, pred)
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred`. The matched element is contained in the end of the previous
+     /// subslice as a terminator.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(split_inclusive)]
+     /// let slice = [10, 40, 33, 20];
+     /// let mut iter = slice.split_inclusive(|num| num % 3 == 0);
+     ///
+     /// assert_eq!(iter.next().unwrap(), &[10, 40, 33]);
+     /// assert_eq!(iter.next().unwrap(), &[20]);
+     /// assert!(iter.next().is_none());
+     /// ```
+     ///
+     /// If the last element of the slice is matched,
+     /// that element will be considered the terminator of the preceding slice.
+     /// That slice will be the last item returned by the iterator.
+     ///
+     /// ```
+     /// #![feature(split_inclusive)]
+     /// let slice = [3, 10, 40, 33];
+     /// let mut iter = slice.split_inclusive(|num| num % 3 == 0);
+     ///
+     /// assert_eq!(iter.next().unwrap(), &[3]);
+     /// assert_eq!(iter.next().unwrap(), &[10, 40, 33]);
+     /// assert!(iter.next().is_none());
+     /// ```
+     #[unstable(feature = "split_inclusive", issue = "72360")]
+     #[inline]
+     pub fn split_inclusive<F>(&self, pred: F) -> SplitInclusive<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         SplitInclusive::new(self, pred)
+     }
+ 
+     /// Returns an iterator over mutable subslices separated by elements that
+     /// match `pred`. The matched element is contained in the previous
+     /// subslice as a terminator.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(split_inclusive)]
+     /// let mut v = [10, 40, 30, 20, 60, 50];
+     ///
+     /// for group in v.split_inclusive_mut(|num| *num % 3 == 0) {
+     ///     let terminator_idx = group.len()-1;
+     ///     group[terminator_idx] = 1;
+     /// }
+     /// assert_eq!(v, [10, 40, 1, 20, 1, 1]);
+     /// ```
+     #[unstable(feature = "split_inclusive", issue = "72360")]
+     #[inline]
+     pub fn split_inclusive_mut<F>(&mut self, pred: F) -> SplitInclusiveMut<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         SplitInclusiveMut::new(self, pred)
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred`, starting at the end of the slice and working backwards.
+     /// The matched element is not contained in the subslices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let slice = [11, 22, 33, 0, 44, 55];
+     /// let mut iter = slice.rsplit(|num| *num == 0);
+     ///
+     /// assert_eq!(iter.next().unwrap(), &[44, 55]);
+     /// assert_eq!(iter.next().unwrap(), &[11, 22, 33]);
+     /// assert_eq!(iter.next(), None);
+     /// ```
+     ///
+     /// As with `split()`, if the first or last element is matched, an empty
+     /// slice will be the first (or last) item returned by the iterator.
+     ///
+     /// ```
+     /// let v = &[0, 1, 1, 2, 3, 5, 8];
+     /// let mut it = v.rsplit(|n| *n % 2 == 0);
+     /// assert_eq!(it.next().unwrap(), &[]);
+     /// assert_eq!(it.next().unwrap(), &[3, 5]);
+     /// assert_eq!(it.next().unwrap(), &[1, 1]);
+     /// assert_eq!(it.next().unwrap(), &[]);
+     /// assert_eq!(it.next(), None);
+     /// ```
+     #[stable(feature = "slice_rsplit", since = "1.27.0")]
+     #[inline]
+     pub fn rsplit<F>(&self, pred: F) -> RSplit<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         RSplit::new(self, pred)
+     }
+ 
+     /// Returns an iterator over mutable subslices separated by elements that
+     /// match `pred`, starting at the end of the slice and working
+     /// backwards. The matched element is not contained in the subslices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [100, 400, 300, 200, 600, 500];
+     ///
+     /// let mut count = 0;
+     /// for group in v.rsplit_mut(|num| *num % 3 == 0) {
+     ///     count += 1;
+     ///     group[0] = count;
+     /// }
+     /// assert_eq!(v, [3, 400, 300, 2, 600, 1]);
+     /// ```
+     ///
+     #[stable(feature = "slice_rsplit", since = "1.27.0")]
+     #[inline]
+     pub fn rsplit_mut<F>(&mut self, pred: F) -> RSplitMut<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         RSplitMut::new(self, pred)
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred`, limited to returning at most `n` items. The matched element is
+     /// not contained in the subslices.
+     ///
+     /// The last element returned, if any, will contain the remainder of the
+     /// slice.
+     ///
+     /// # Examples
+     ///
+     /// Print the slice split once by numbers divisible by 3 (i.e., `[10, 40]`,
+     /// `[20, 60, 50]`):
+     ///
+     /// ```
+     /// let v = [10, 40, 30, 20, 60, 50];
+     ///
+     /// for group in v.splitn(2, |num| *num % 3 == 0) {
+     ///     println!("{:?}", group);
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn splitn<F>(&self, n: usize, pred: F) -> SplitN<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         SplitN::new(self.split(pred), n)
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred`, limited to returning at most `n` items. The matched element is
+     /// not contained in the subslices.
+     ///
+     /// The last element returned, if any, will contain the remainder of the
+     /// slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [10, 40, 30, 20, 60, 50];
+     ///
+     /// for group in v.splitn_mut(2, |num| *num % 3 == 0) {
+     ///     group[0] = 1;
+     /// }
+     /// assert_eq!(v, [1, 40, 30, 1, 60, 50]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn splitn_mut<F>(&mut self, n: usize, pred: F) -> SplitNMut<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         SplitNMut::new(self.split_mut(pred), n)
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred` limited to returning at most `n` items. This starts at the end of
+     /// the slice and works backwards. The matched element is not contained in
+     /// the subslices.
+     ///
+     /// The last element returned, if any, will contain the remainder of the
+     /// slice.
+     ///
+     /// # Examples
+     ///
+     /// Print the slice split once, starting from the end, by numbers divisible
+     /// by 3 (i.e., `[50]`, `[10, 40, 30, 20]`):
+     ///
+     /// ```
+     /// let v = [10, 40, 30, 20, 60, 50];
+     ///
+     /// for group in v.rsplitn(2, |num| *num % 3 == 0) {
+     ///     println!("{:?}", group);
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn rsplitn<F>(&self, n: usize, pred: F) -> RSplitN<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         RSplitN::new(self.rsplit(pred), n)
+     }
+ 
+     /// Returns an iterator over subslices separated by elements that match
+     /// `pred` limited to returning at most `n` items. This starts at the end of
+     /// the slice and works backwards. The matched element is not contained in
+     /// the subslices.
+     ///
+     /// The last element returned, if any, will contain the remainder of the
+     /// slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut s = [10, 40, 30, 20, 60, 50];
+     ///
+     /// for group in s.rsplitn_mut(2, |num| *num % 3 == 0) {
+     ///     group[0] = 1;
+     /// }
+     /// assert_eq!(s, [1, 40, 30, 20, 60, 1]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn rsplitn_mut<F>(&mut self, n: usize, pred: F) -> RSplitNMut<'_, T, F>
+     where
+         F: FnMut(&T) -> bool,
+     {
+         RSplitNMut::new(self.rsplit_mut(pred), n)
+     }
+ 
+     /// Returns `true` if the slice contains an element with the given value.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [10, 40, 30];
+     /// assert!(v.contains(&30));
+     /// assert!(!v.contains(&50));
+     /// ```
+     ///
+     /// If you do not have an `&T`, but just an `&U` such that `T: Borrow<U>`
+     /// (e.g. `String: Borrow<str>`), you can use `iter().any`:
+     ///
+     /// ```
+     /// let v = [String::from("hello"), String::from("world")]; // slice of `String`
+     /// assert!(v.iter().any(|e| e == "hello")); // search with `&str`
+     /// assert!(!v.iter().any(|e| e == "hi"));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn contains(&self, x: &T) -> bool
+     where
+         T: PartialEq,
+     {
+         cmp::SliceContains::slice_contains(x, self)
+     }
+ 
+     /// Returns `true` if `needle` is a prefix of the slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [10, 40, 30];
+     /// assert!(v.starts_with(&[10]));
+     /// assert!(v.starts_with(&[10, 40]));
+     /// assert!(!v.starts_with(&[50]));
+     /// assert!(!v.starts_with(&[10, 50]));
+     /// ```
+     ///
+     /// Always returns `true` if `needle` is an empty slice:
+     ///
+     /// ```
+     /// let v = &[10, 40, 30];
+     /// assert!(v.starts_with(&[]));
+     /// let v: &[u8] = &[];
+     /// assert!(v.starts_with(&[]));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn starts_with(&self, needle: &[T]) -> bool
+     where
+         T: PartialEq,
+     {
+         let n = needle.len();
+         self.len() >= n && needle == &self[..n]
+     }
+ 
+     /// Returns `true` if `needle` is a suffix of the slice.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = [10, 40, 30];
+     /// assert!(v.ends_with(&[30]));
+     /// assert!(v.ends_with(&[40, 30]));
+     /// assert!(!v.ends_with(&[50]));
+     /// assert!(!v.ends_with(&[50, 30]));
+     /// ```
+     ///
+     /// Always returns `true` if `needle` is an empty slice:
+     ///
+     /// ```
+     /// let v = &[10, 40, 30];
+     /// assert!(v.ends_with(&[]));
+     /// let v: &[u8] = &[];
+     /// assert!(v.ends_with(&[]));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn ends_with(&self, needle: &[T]) -> bool
+     where
+         T: PartialEq,
+     {
+         let (m, n) = (self.len(), needle.len());
+         m >= n && needle == &self[m - n..]
+     }
+ 
+     /// Returns a subslice with the prefix removed.
+     ///
+     /// If the slice starts with `prefix`, returns the subslice after the prefix, wrapped in `Some`.
+     /// If `prefix` is empty, simply returns the original slice.
+     ///
+     /// If the slice does not start with `prefix`, returns `None`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_strip)]
+     /// let v = &[10, 40, 30];
+     /// assert_eq!(v.strip_prefix(&[10]), Some(&[40, 30][..]));
+     /// assert_eq!(v.strip_prefix(&[10, 40]), Some(&[30][..]));
+     /// assert_eq!(v.strip_prefix(&[50]), None);
+     /// assert_eq!(v.strip_prefix(&[10, 50]), None);
+     /// ```
+     #[must_use = "returns the subslice without modifying the original"]
+     #[unstable(feature = "slice_strip", issue = "73413")]
+     pub fn strip_prefix(&self, prefix: &[T]) -> Option<&[T]>
+     where
+         T: PartialEq,
+     {
+         let n = prefix.len();
+         if n <= self.len() {
+             let (head, tail) = self.split_at(n);
+             if head == prefix {
+                 return Some(tail);
+             }
+         }
+         None
+     }
+ 
+     /// Returns a subslice with the suffix removed.
+     ///
+     /// If the slice ends with `suffix`, returns the subslice before the suffix, wrapped in `Some`.
+     /// If `suffix` is empty, simply returns the original slice.
+     ///
+     /// If the slice does not end with `suffix`, returns `None`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_strip)]
+     /// let v = &[10, 40, 30];
+     /// assert_eq!(v.strip_suffix(&[30]), Some(&[10, 40][..]));
+     /// assert_eq!(v.strip_suffix(&[40, 30]), Some(&[10][..]));
+     /// assert_eq!(v.strip_suffix(&[50]), None);
+     /// assert_eq!(v.strip_suffix(&[50, 30]), None);
+     /// ```
+     #[must_use = "returns the subslice without modifying the original"]
+     #[unstable(feature = "slice_strip", issue = "73413")]
+     pub fn strip_suffix(&self, suffix: &[T]) -> Option<&[T]>
+     where
+         T: PartialEq,
+     {
+         let (len, n) = (self.len(), suffix.len());
+         if n <= len {
+             let (head, tail) = self.split_at(len - n);
+             if tail == suffix {
+                 return Some(head);
+             }
+         }
+         None
+     }
+ 
+     /// Binary searches this sorted slice for a given element.
+     ///
+     /// If the value is found then [`Result::Ok`] is returned, containing the
+     /// index of the matching element. If there are multiple matches, then any
+     /// one of the matches could be returned. If the value is not found then
+     /// [`Result::Err`] is returned, containing the index where a matching
+     /// element could be inserted while maintaining sorted order.
+     ///
+     /// # Examples
+     ///
+     /// Looks up a series of four elements. The first is found, with a
+     /// uniquely determined position; the second and third are not
+     /// found; the fourth could match any position in `[1, 4]`.
+     ///
+     /// ```
+     /// let s = [0, 1, 1, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55];
+     ///
+     /// assert_eq!(s.binary_search(&13),  Ok(9));
+     /// assert_eq!(s.binary_search(&4),   Err(7));
+     /// assert_eq!(s.binary_search(&100), Err(13));
+     /// let r = s.binary_search(&1);
+     /// assert!(match r { Ok(1..=4) => true, _ => false, });
+     /// ```
+     ///
+     /// If you want to insert an item to a sorted vector, while maintaining
+     /// sort order:
+     ///
+     /// ```
+     /// let mut s = vec![0, 1, 1, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55];
+     /// let num = 42;
+     /// let idx = s.binary_search(&num).unwrap_or_else(|x| x);
+     /// s.insert(idx, num);
+     /// assert_eq!(s, [0, 1, 1, 1, 1, 2, 3, 5, 8, 13, 21, 34, 42, 55]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn binary_search(&self, x: &T) -> Result<usize, usize>
+     where
+         T: Ord,
+     {
+         self.binary_search_by(|p| p.cmp(x))
+     }
+ 
+     /// Binary searches this sorted slice with a comparator function.
+     ///
+     /// The comparator function should implement an order consistent
+     /// with the sort order of the underlying slice, returning an
+     /// order code that indicates whether its argument is `Less`,
+     /// `Equal` or `Greater` the desired target.
+     ///
+     /// If the value is found then [`Result::Ok`] is returned, containing the
+     /// index of the matching element. If there are multiple matches, then any
+     /// one of the matches could be returned. If the value is not found then
+     /// [`Result::Err`] is returned, containing the index where a matching
+     /// element could be inserted while maintaining sorted order.
+     ///
+     /// # Examples
+     ///
+     /// Looks up a series of four elements. The first is found, with a
+     /// uniquely determined position; the second and third are not
+     /// found; the fourth could match any position in `[1, 4]`.
+     ///
+     /// ```
+     /// let s = [0, 1, 1, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55];
+     ///
+     /// let seek = 13;
+     /// assert_eq!(s.binary_search_by(|probe| probe.cmp(&seek)), Ok(9));
+     /// let seek = 4;
+     /// assert_eq!(s.binary_search_by(|probe| probe.cmp(&seek)), Err(7));
+     /// let seek = 100;
+     /// assert_eq!(s.binary_search_by(|probe| probe.cmp(&seek)), Err(13));
+     /// let seek = 1;
+     /// let r = s.binary_search_by(|probe| probe.cmp(&seek));
+     /// assert!(match r { Ok(1..=4) => true, _ => false, });
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn binary_search_by<'a, F>(&'a self, mut f: F) -> Result<usize, usize>
+     where
+         F: FnMut(&'a T) -> Ordering,
+     {
+         let s = self;
+         let mut size = s.len();
+         if size == 0 {
+             return Err(0);
+         }
+         let mut base = 0usize;
+         while size > 1 {
+             let half = size / 2;
+             let mid = base + half;
+             // SAFETY: the call is made safe by the following inconstants:
+             // - `mid >= 0`: by definition
+             // - `mid < size`: `mid = size / 2 + size / 4 + size / 8 ...`
+             let cmp = f(unsafe { s.get_unchecked(mid) });
+             base = if cmp == Greater { base } else { mid };
+             size -= half;
+         }
+         // SAFETY: base is always in [0, size) because base <= mid.
+         let cmp = f(unsafe { s.get_unchecked(base) });
+         if cmp == Equal { Ok(base) } else { Err(base + (cmp == Less) as usize) }
+     }
+ 
+     /// Binary searches this sorted slice with a key extraction function.
+     ///
+     /// Assumes that the slice is sorted by the key, for instance with
+     /// [`sort_by_key`] using the same key extraction function.
+     ///
+     /// If the value is found then [`Result::Ok`] is returned, containing the
+     /// index of the matching element. If there are multiple matches, then any
+     /// one of the matches could be returned. If the value is not found then
+     /// [`Result::Err`] is returned, containing the index where a matching
+     /// element could be inserted while maintaining sorted order.
+     ///
+     /// [`sort_by_key`]: #method.sort_by_key
+     ///
+     /// # Examples
+     ///
+     /// Looks up a series of four elements in a slice of pairs sorted by
+     /// their second elements. The first is found, with a uniquely
+     /// determined position; the second and third are not found; the
+     /// fourth could match any position in `[1, 4]`.
+     ///
+     /// ```
+     /// let s = [(0, 0), (2, 1), (4, 1), (5, 1), (3, 1),
+     ///          (1, 2), (2, 3), (4, 5), (5, 8), (3, 13),
+     ///          (1, 21), (2, 34), (4, 55)];
+     ///
+     /// assert_eq!(s.binary_search_by_key(&13, |&(a,b)| b),  Ok(9));
+     /// assert_eq!(s.binary_search_by_key(&4, |&(a,b)| b),   Err(7));
+     /// assert_eq!(s.binary_search_by_key(&100, |&(a,b)| b), Err(13));
+     /// let r = s.binary_search_by_key(&1, |&(a,b)| b);
+     /// assert!(match r { Ok(1..=4) => true, _ => false, });
+     /// ```
+     #[stable(feature = "slice_binary_search_by_key", since = "1.10.0")]
+     #[inline]
+     pub fn binary_search_by_key<'a, B, F>(&'a self, b: &B, mut f: F) -> Result<usize, usize>
+     where
+         F: FnMut(&'a T) -> B,
+         B: Ord,
+     {
+         self.binary_search_by(|k| f(k).cmp(b))
+     }
+ 
+     /// Sorts the slice, but may not preserve the order of equal elements.
+     ///
+     /// This sort is unstable (i.e., may reorder equal elements), in-place
+     /// (i.e., does not allocate), and *O*(*n* \* log(*n*)) worst-case.
+     ///
+     /// # Current implementation
+     ///
+     /// The current algorithm is based on [pattern-defeating quicksort][pdqsort] by Orson Peters,
+     /// which combines the fast average case of randomized quicksort with the fast worst case of
+     /// heapsort, while achieving linear time on slices with certain patterns. It uses some
+     /// randomization to avoid degenerate cases, but with a fixed seed to always provide
+     /// deterministic behavior.
+     ///
+     /// It is typically faster than stable sorting, except in a few special cases, e.g., when the
+     /// slice consists of several concatenated sorted sequences.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [-5, 4, 1, -3, 2];
+     ///
+     /// v.sort_unstable();
+     /// assert!(v == [-5, -3, 1, 2, 4]);
+     /// ```
+     ///
+     /// [pdqsort]: https://github.com/orlp/pdqsort
+     #[stable(feature = "sort_unstable", since = "1.20.0")]
+     #[inline]
+     pub fn sort_unstable(&mut self)
+     where
+         T: Ord,
+     {
+         sort::quicksort(self, |a, b| a.lt(b));
+     }
+ 
+     /// Sorts the slice with a comparator function, but may not preserve the order of equal
+     /// elements.
+     ///
+     /// This sort is unstable (i.e., may reorder equal elements), in-place
+     /// (i.e., does not allocate), and *O*(*n* \* log(*n*)) worst-case.
+     ///
+     /// The comparator function must define a total ordering for the elements in the slice. If
+     /// the ordering is not total, the order of the elements is unspecified. An order is a
+     /// total order if it is (for all `a`, `b` and `c`):
+     ///
+     /// * total and antisymmetric: exactly one of `a < b`, `a == b` or `a > b` is true, and
+     /// * transitive, `a < b` and `b < c` implies `a < c`. The same must hold for both `==` and `>`.
+     ///
+     /// For example, while [`f64`] doesn't implement [`Ord`] because `NaN != NaN`, we can use
+     /// `partial_cmp` as our sort function when we know the slice doesn't contain a `NaN`.
+     ///
+     /// ```
+     /// let mut floats = [5f64, 4.0, 1.0, 3.0, 2.0];
+     /// floats.sort_unstable_by(|a, b| a.partial_cmp(b).unwrap());
+     /// assert_eq!(floats, [1.0, 2.0, 3.0, 4.0, 5.0]);
+     /// ```
+     ///
+     /// # Current implementation
+     ///
+     /// The current algorithm is based on [pattern-defeating quicksort][pdqsort] by Orson Peters,
+     /// which combines the fast average case of randomized quicksort with the fast worst case of
+     /// heapsort, while achieving linear time on slices with certain patterns. It uses some
+     /// randomization to avoid degenerate cases, but with a fixed seed to always provide
+     /// deterministic behavior.
+     ///
+     /// It is typically faster than stable sorting, except in a few special cases, e.g., when the
+     /// slice consists of several concatenated sorted sequences.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [5, 4, 1, 3, 2];
+     /// v.sort_unstable_by(|a, b| a.cmp(b));
+     /// assert!(v == [1, 2, 3, 4, 5]);
+     ///
+     /// // reverse sorting
+     /// v.sort_unstable_by(|a, b| b.cmp(a));
+     /// assert!(v == [5, 4, 3, 2, 1]);
+     /// ```
+     ///
+     /// [pdqsort]: https://github.com/orlp/pdqsort
+     #[stable(feature = "sort_unstable", since = "1.20.0")]
+     #[inline]
+     pub fn sort_unstable_by<F>(&mut self, mut compare: F)
+     where
+         F: FnMut(&T, &T) -> Ordering,
+     {
+         sort::quicksort(self, |a, b| compare(a, b) == Ordering::Less);
+     }
+ 
+     /// Sorts the slice with a key extraction function, but may not preserve the order of equal
+     /// elements.
+     ///
+     /// This sort is unstable (i.e., may reorder equal elements), in-place
+     /// (i.e., does not allocate), and *O*(m \* *n* \* log(*n*)) worst-case, where the key function is
+     /// *O*(*m*).
+     ///
+     /// # Current implementation
+     ///
+     /// The current algorithm is based on [pattern-defeating quicksort][pdqsort] by Orson Peters,
+     /// which combines the fast average case of randomized quicksort with the fast worst case of
+     /// heapsort, while achieving linear time on slices with certain patterns. It uses some
+     /// randomization to avoid degenerate cases, but with a fixed seed to always provide
+     /// deterministic behavior.
+     ///
+     /// Due to its key calling strategy, [`sort_unstable_by_key`](#method.sort_unstable_by_key)
+     /// is likely to be slower than [`sort_by_cached_key`](#method.sort_by_cached_key) in
+     /// cases where the key function is expensive.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [-5i32, 4, 1, -3, 2];
+     ///
+     /// v.sort_unstable_by_key(|k| k.abs());
+     /// assert!(v == [1, 2, -3, 4, -5]);
+     /// ```
+     ///
+     /// [pdqsort]: https://github.com/orlp/pdqsort
+     #[stable(feature = "sort_unstable", since = "1.20.0")]
+     #[inline]
+     pub fn sort_unstable_by_key<K, F>(&mut self, mut f: F)
+     where
+         F: FnMut(&T) -> K,
+         K: Ord,
+     {
+         sort::quicksort(self, |a, b| f(a).lt(&f(b)));
+     }
+ 
+     /// Reorder the slice such that the element at `index` is at its final sorted position.
+     #[unstable(feature = "slice_partition_at_index", issue = "55300")]
+     #[rustc_deprecated(since = "1.49.0", reason = "use the select_nth_unstable() instead")]
+     #[inline]
+     pub fn partition_at_index(&mut self, index: usize) -> (&mut [T], &mut T, &mut [T])
+     where
+         T: Ord,
+     {
+         self.select_nth_unstable(index)
+     }
+ 
+     /// Reorder the slice with a comparator function such that the element at `index` is at its
+     /// final sorted position.
+     #[unstable(feature = "slice_partition_at_index", issue = "55300")]
+     #[rustc_deprecated(since = "1.49.0", reason = "use select_nth_unstable_by() instead")]
+     #[inline]
+     pub fn partition_at_index_by<F>(
+         &mut self,
+         index: usize,
+         compare: F,
+     ) -> (&mut [T], &mut T, &mut [T])
+     where
+         F: FnMut(&T, &T) -> Ordering,
+     {
+         self.select_nth_unstable_by(index, compare)
+     }
+ 
+     /// Reorder the slice with a key extraction function such that the element at `index` is at its
+     /// final sorted position.
+     #[unstable(feature = "slice_partition_at_index", issue = "55300")]
+     #[rustc_deprecated(since = "1.49.0", reason = "use the select_nth_unstable_by_key() instead")]
+     #[inline]
+     pub fn partition_at_index_by_key<K, F>(
+         &mut self,
+         index: usize,
+         f: F,
+     ) -> (&mut [T], &mut T, &mut [T])
+     where
+         F: FnMut(&T) -> K,
+         K: Ord,
+     {
+         self.select_nth_unstable_by_key(index, f)
+     }
+ 
+     /// Reorder the slice such that the element at `index` is at its final sorted position.
+     ///
+     /// This reordering has the additional property that any value at position `i < index` will be
+     /// less than or equal to any value at a position `j > index`. Additionally, this reordering is
+     /// unstable (i.e. any number of equal elements may end up at position `index`), in-place
+     /// (i.e. does not allocate), and *O*(*n*) worst-case. This function is also/ known as "kth
+     /// element" in other libraries. It returns a triplet of the following values: all elements less
+     /// than the one at the given index, the value at the given index, and all elements greater than
+     /// the one at the given index.
+     ///
+     /// # Current implementation
+     ///
+     /// The current algorithm is based on the quickselect portion of the same quicksort algorithm
+     /// used for [`sort_unstable`].
+     ///
+     /// [`sort_unstable`]: #method.sort_unstable
+     ///
+     /// # Panics
+     ///
+     /// Panics when `index >= len()`, meaning it always panics on empty slices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [-5i32, 4, 1, -3, 2];
+     ///
+     /// // Find the median
+     /// v.select_nth_unstable(2);
+     ///
+     /// // We are only guaranteed the slice will be one of the following, based on the way we sort
+     /// // about the specified index.
+     /// assert!(v == [-3, -5, 1, 2, 4] ||
+     ///         v == [-5, -3, 1, 2, 4] ||
+     ///         v == [-3, -5, 1, 4, 2] ||
+     ///         v == [-5, -3, 1, 4, 2]);
+     /// ```
+     #[stable(feature = "slice_select_nth_unstable", since = "1.49.0")]
+     #[inline]
+     pub fn select_nth_unstable(&mut self, index: usize) -> (&mut [T], &mut T, &mut [T])
+     where
+         T: Ord,
+     {
+         let mut f = |a: &T, b: &T| a.lt(b);
+         sort::partition_at_index(self, index, &mut f)
+     }
+ 
+     /// Reorder the slice with a comparator function such that the element at `index` is at its
+     /// final sorted position.
+     ///
+     /// This reordering has the additional property that any value at position `i < index` will be
+     /// less than or equal to any value at a position `j > index` using the comparator function.
+     /// Additionally, this reordering is unstable (i.e. any number of equal elements may end up at
+     /// position `index`), in-place (i.e. does not allocate), and *O*(*n*) worst-case. This function
+     /// is also known as "kth element" in other libraries. It returns a triplet of the following
+     /// values: all elements less than the one at the given index, the value at the given index,
+     /// and all elements greater than the one at the given index, using the provided comparator
+     /// function.
+     ///
+     /// # Current implementation
+     ///
+     /// The current algorithm is based on the quickselect portion of the same quicksort algorithm
+     /// used for [`sort_unstable`].
+     ///
+     /// [`sort_unstable`]: #method.sort_unstable
+     ///
+     /// # Panics
+     ///
+     /// Panics when `index >= len()`, meaning it always panics on empty slices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [-5i32, 4, 1, -3, 2];
+     ///
+     /// // Find the median as if the slice were sorted in descending order.
+     /// v.select_nth_unstable_by(2, |a, b| b.cmp(a));
+     ///
+     /// // We are only guaranteed the slice will be one of the following, based on the way we sort
+     /// // about the specified index.
+     /// assert!(v == [2, 4, 1, -5, -3] ||
+     ///         v == [2, 4, 1, -3, -5] ||
+     ///         v == [4, 2, 1, -5, -3] ||
+     ///         v == [4, 2, 1, -3, -5]);
+     /// ```
+     #[stable(feature = "slice_select_nth_unstable", since = "1.49.0")]
+     #[inline]
+     pub fn select_nth_unstable_by<F>(
+         &mut self,
+         index: usize,
+         mut compare: F,
+     ) -> (&mut [T], &mut T, &mut [T])
+     where
+         F: FnMut(&T, &T) -> Ordering,
+     {
+         let mut f = |a: &T, b: &T| compare(a, b) == Less;
+         sort::partition_at_index(self, index, &mut f)
+     }
+ 
+     /// Reorder the slice with a key extraction function such that the element at `index` is at its
+     /// final sorted position.
+     ///
+     /// This reordering has the additional property that any value at position `i < index` will be
+     /// less than or equal to any value at a position `j > index` using the key extraction function.
+     /// Additionally, this reordering is unstable (i.e. any number of equal elements may end up at
+     /// position `index`), in-place (i.e. does not allocate), and *O*(*n*) worst-case. This function
+     /// is also known as "kth element" in other libraries. It returns a triplet of the following
+     /// values: all elements less than the one at the given index, the value at the given index, and
+     /// all elements greater than the one at the given index, using the provided key extraction
+     /// function.
+     ///
+     /// # Current implementation
+     ///
+     /// The current algorithm is based on the quickselect portion of the same quicksort algorithm
+     /// used for [`sort_unstable`].
+     ///
+     /// [`sort_unstable`]: #method.sort_unstable
+     ///
+     /// # Panics
+     ///
+     /// Panics when `index >= len()`, meaning it always panics on empty slices.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = [-5i32, 4, 1, -3, 2];
+     ///
+     /// // Return the median as if the array were sorted according to absolute value.
+     /// v.select_nth_unstable_by_key(2, |a| a.abs());
+     ///
+     /// // We are only guaranteed the slice will be one of the following, based on the way we sort
+     /// // about the specified index.
+     /// assert!(v == [1, 2, -3, 4, -5] ||
+     ///         v == [1, 2, -3, -5, 4] ||
+     ///         v == [2, 1, -3, 4, -5] ||
+     ///         v == [2, 1, -3, -5, 4]);
+     /// ```
+     #[stable(feature = "slice_select_nth_unstable", since = "1.49.0")]
+     #[inline]
+     pub fn select_nth_unstable_by_key<K, F>(
+         &mut self,
+         index: usize,
+         mut f: F,
+     ) -> (&mut [T], &mut T, &mut [T])
+     where
+         F: FnMut(&T) -> K,
+         K: Ord,
+     {
+         let mut g = |a: &T, b: &T| f(a).lt(&f(b));
+         sort::partition_at_index(self, index, &mut g)
+     }
+ 
+     /// Moves all consecutive repeated elements to the end of the slice according to the
+     /// [`PartialEq`] trait implementation.
+     ///
+     /// Returns two slices. The first contains no consecutive repeated elements.
+     /// The second contains all the duplicates in no specified order.
+     ///
+     /// If the slice is sorted, the first returned slice contains no duplicates.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_partition_dedup)]
+     ///
+     /// let mut slice = [1, 2, 2, 3, 3, 2, 1, 1];
+     ///
+     /// let (dedup, duplicates) = slice.partition_dedup();
+     ///
+     /// assert_eq!(dedup, [1, 2, 3, 2, 1]);
+     /// assert_eq!(duplicates, [2, 3, 1]);
+     /// ```
+     #[unstable(feature = "slice_partition_dedup", issue = "54279")]
+     #[inline]
+     pub fn partition_dedup(&mut self) -> (&mut [T], &mut [T])
+     where
+         T: PartialEq,
+     {
+         self.partition_dedup_by(|a, b| a == b)
+     }
+ 
+     /// Moves all but the first of consecutive elements to the end of the slice satisfying
+     /// a given equality relation.
+     ///
+     /// Returns two slices. The first contains no consecutive repeated elements.
+     /// The second contains all the duplicates in no specified order.
+     ///
+     /// The `same_bucket` function is passed references to two elements from the slice and
+     /// must determine if the elements compare equal. The elements are passed in opposite order
+     /// from their order in the slice, so if `same_bucket(a, b)` returns `true`, `a` is moved
+     /// at the end of the slice.
+     ///
+     /// If the slice is sorted, the first returned slice contains no duplicates.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_partition_dedup)]
+     ///
+     /// let mut slice = ["foo", "Foo", "BAZ", "Bar", "bar", "baz", "BAZ"];
+     ///
+     /// let (dedup, duplicates) = slice.partition_dedup_by(|a, b| a.eq_ignore_ascii_case(b));
+     ///
+     /// assert_eq!(dedup, ["foo", "BAZ", "Bar", "baz"]);
+     /// assert_eq!(duplicates, ["bar", "Foo", "BAZ"]);
+     /// ```
+     #[unstable(feature = "slice_partition_dedup", issue = "54279")]
+     #[inline]
+     pub fn partition_dedup_by<F>(&mut self, mut same_bucket: F) -> (&mut [T], &mut [T])
+     where
+         F: FnMut(&mut T, &mut T) -> bool,
+     {
+         // Although we have a mutable reference to `self`, we cannot make
+         // *arbitrary* changes. The `same_bucket` calls could panic, so we
+         // must ensure that the slice is in a valid state at all times.
+         //
+         // The way that we handle this is by using swaps; we iterate
+         // over all the elements, swapping as we go so that at the end
+         // the elements we wish to keep are in the front, and those we
+         // wish to reject are at the back. We can then split the slice.
+         // This operation is still `O(n)`.
+         //
+         // Example: We start in this state, where `r` represents "next
+         // read" and `w` represents "next_write`.
+         //
+         //           r
+         //     +---+---+---+---+---+---+
+         //     | 0 | 1 | 1 | 2 | 3 | 3 |
+         //     +---+---+---+---+---+---+
+         //           w
+         //
+         // Comparing self[r] against self[w-1], this is not a duplicate, so
+         // we swap self[r] and self[w] (no effect as r==w) and then increment both
+         // r and w, leaving us with:
+         //
+         //               r
+         //     +---+---+---+---+---+---+
+         //     | 0 | 1 | 1 | 2 | 3 | 3 |
+         //     +---+---+---+---+---+---+
+         //               w
+         //
+         // Comparing self[r] against self[w-1], this value is a duplicate,
+         // so we increment `r` but leave everything else unchanged:
+         //
+         //                   r
+         //     +---+---+---+---+---+---+
+         //     | 0 | 1 | 1 | 2 | 3 | 3 |
+         //     +---+---+---+---+---+---+
+         //               w
+         //
+         // Comparing self[r] against self[w-1], this is not a duplicate,
+         // so swap self[r] and self[w] and advance r and w:
+         //
+         //                       r
+         //     +---+---+---+---+---+---+
+         //     | 0 | 1 | 2 | 1 | 3 | 3 |
+         //     +---+---+---+---+---+---+
+         //                   w
+         //
+         // Not a duplicate, repeat:
+         //
+         //                           r
+         //     +---+---+---+---+---+---+
+         //     | 0 | 1 | 2 | 3 | 1 | 3 |
+         //     +---+---+---+---+---+---+
+         //                       w
+         //
+         // Duplicate, advance r. End of slice. Split at w.
+ 
+         let len = self.len();
+         if len <= 1 {
+             return (self, &mut []);
+         }
+ 
+         let ptr = self.as_mut_ptr();
+         let mut next_read: usize = 1;
+         let mut next_write: usize = 1;
+ 
+         // SAFETY: the `while` condition guarantees `next_read` and `next_write`
+         // are less than `len`, thus are inside `self`. `prev_ptr_write` points to
+         // one element before `ptr_write`, but `next_write` starts at 1, so
+         // `prev_ptr_write` is never less than 0 and is inside the slice.
+         // This fulfils the requirements for dereferencing `ptr_read`, `prev_ptr_write`
+         // and `ptr_write`, and for using `ptr.add(next_read)`, `ptr.add(next_write - 1)`
+         // and `prev_ptr_write.offset(1)`.
+         //
+         // `next_write` is also incremented at most once per loop at most meaning
+         // no element is skipped when it may need to be swapped.
+         //
+         // `ptr_read` and `prev_ptr_write` never point to the same element. This
+         // is required for `&mut *ptr_read`, `&mut *prev_ptr_write` to be safe.
+         // The explanation is simply that `next_read >= next_write` is always true,
+         // thus `next_read > next_write - 1` is too.
+         unsafe {
+             // Avoid bounds checks by using raw pointers.
+             while next_read < len {
+                 let ptr_read = ptr.add(next_read);
+                 let prev_ptr_write = ptr.add(next_write - 1);
+                 if !same_bucket(&mut *ptr_read, &mut *prev_ptr_write) {
+                     if next_read != next_write {
+                         let ptr_write = prev_ptr_write.offset(1);
+                         mem::swap(&mut *ptr_read, &mut *ptr_write);
+                     }
+                     next_write += 1;
+                 }
+                 next_read += 1;
+             }
+         }
+ 
+         self.split_at_mut(next_write)
+     }
+ 
+     /// Moves all but the first of consecutive elements to the end of the slice that resolve
+     /// to the same key.
+     ///
+     /// Returns two slices. The first contains no consecutive repeated elements.
+     /// The second contains all the duplicates in no specified order.
+     ///
+     /// If the slice is sorted, the first returned slice contains no duplicates.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_partition_dedup)]
+     ///
+     /// let mut slice = [10, 20, 21, 30, 30, 20, 11, 13];
+     ///
+     /// let (dedup, duplicates) = slice.partition_dedup_by_key(|i| *i / 10);
+     ///
+     /// assert_eq!(dedup, [10, 20, 30, 20, 11]);
+     /// assert_eq!(duplicates, [21, 30, 13]);
+     /// ```
+     #[unstable(feature = "slice_partition_dedup", issue = "54279")]
+     #[inline]
+     pub fn partition_dedup_by_key<K, F>(&mut self, mut key: F) -> (&mut [T], &mut [T])
+     where
+         F: FnMut(&mut T) -> K,
+         K: PartialEq,
+     {
+         self.partition_dedup_by(|a, b| key(a) == key(b))
+     }
+ 
+     /// Rotates the slice in-place such that the first `mid` elements of the
+     /// slice move to the end while the last `self.len() - mid` elements move to
+     /// the front. After calling `rotate_left`, the element previously at index
+     /// `mid` will become the first element in the slice.
+     ///
+     /// # Panics
+     ///
+     /// This function will panic if `mid` is greater than the length of the
+     /// slice. Note that `mid == self.len()` does _not_ panic and is a no-op
+     /// rotation.
+     ///
+     /// # Complexity
+     ///
+     /// Takes linear (in `self.len()`) time.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut a = ['a', 'b', 'c', 'd', 'e', 'f'];
+     /// a.rotate_left(2);
+     /// assert_eq!(a, ['c', 'd', 'e', 'f', 'a', 'b']);
+     /// ```
+     ///
+     /// Rotating a subslice:
+     ///
+     /// ```
+     /// let mut a = ['a', 'b', 'c', 'd', 'e', 'f'];
+     /// a[1..5].rotate_left(1);
+     /// assert_eq!(a, ['a', 'c', 'd', 'e', 'b', 'f']);
+     /// ```
+     #[stable(feature = "slice_rotate", since = "1.26.0")]
+     pub fn rotate_left(&mut self, mid: usize) {
+         assert!(mid <= self.len());
+         let k = self.len() - mid;
+         let p = self.as_mut_ptr();
+ 
+         // SAFETY: The range `[p.add(mid) - mid, p.add(mid) + k)` is trivially
+         // valid for reading and writing, as required by `ptr_rotate`.
+         unsafe {
+             rotate::ptr_rotate(mid, p.add(mid), k);
+         }
+     }
+ 
+     /// Rotates the slice in-place such that the first `self.len() - k`
+     /// elements of the slice move to the end while the last `k` elements move
+     /// to the front. After calling `rotate_right`, the element previously at
+     /// index `self.len() - k` will become the first element in the slice.
+     ///
+     /// # Panics
+     ///
+     /// This function will panic if `k` is greater than the length of the
+     /// slice. Note that `k == self.len()` does _not_ panic and is a no-op
+     /// rotation.
+     ///
+     /// # Complexity
+     ///
+     /// Takes linear (in `self.len()`) time.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut a = ['a', 'b', 'c', 'd', 'e', 'f'];
+     /// a.rotate_right(2);
+     /// assert_eq!(a, ['e', 'f', 'a', 'b', 'c', 'd']);
+     /// ```
+     ///
+     /// Rotate a subslice:
+     ///
+     /// ```
+     /// let mut a = ['a', 'b', 'c', 'd', 'e', 'f'];
+     /// a[1..5].rotate_right(1);
+     /// assert_eq!(a, ['a', 'e', 'b', 'c', 'd', 'f']);
+     /// ```
+     #[stable(feature = "slice_rotate", since = "1.26.0")]
+     pub fn rotate_right(&mut self, k: usize) {
+         assert!(k <= self.len());
+         let mid = self.len() - k;
+         let p = self.as_mut_ptr();
+ 
+         // SAFETY: The range `[p.add(mid) - mid, p.add(mid) + k)` is trivially
+         // valid for reading and writing, as required by `ptr_rotate`.
+         unsafe {
+             rotate::ptr_rotate(mid, p.add(mid), k);
+         }
+     }
+ 
+     /// Fills `self` with elements by cloning `value`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(slice_fill)]
+     ///
+     /// let mut buf = vec![0; 10];
+     /// buf.fill(1);
+     /// assert_eq!(buf, vec![1; 10]);
+     /// ```
+     #[unstable(feature = "slice_fill", issue = "70758")]
+     pub fn fill(&mut self, value: T)
+     where
+         T: Clone,
+     {
+         if let Some((last, elems)) = self.split_last_mut() {
+             for el in elems {
+                 el.clone_from(&value);
+             }
+ 
+             *last = value
+         }
+     }
+ 
+     /// Copies the elements from `src` into `self`.
+     ///
+     /// The length of `src` must be the same as `self`.
+     ///
+     /// If `T` implements `Copy`, it can be more performant to use
+     /// [`copy_from_slice`].
+     ///
+     /// # Panics
+     ///
+     /// This function will panic if the two slices have different lengths.
+     ///
+     /// # Examples
+     ///
+     /// Cloning two elements from a slice into another:
+     ///
+     /// ```
+     /// let src = [1, 2, 3, 4];
+     /// let mut dst = [0, 0];
+     ///
+     /// // Because the slices have to be the same length,
+     /// // we slice the source slice from four elements
+     /// // to two. It will panic if we don't do this.
+     /// dst.clone_from_slice(&src[2..]);
+     ///
+     /// assert_eq!(src, [1, 2, 3, 4]);
+     /// assert_eq!(dst, [3, 4]);
+     /// ```
+     ///
+     /// Rust enforces that there can only be one mutable reference with no
+     /// immutable references to a particular piece of data in a particular
+     /// scope. Because of this, attempting to use `clone_from_slice` on a
+     /// single slice will result in a compile failure:
+     ///
+     /// ```compile_fail
+     /// let mut slice = [1, 2, 3, 4, 5];
+     ///
+     /// slice[..2].clone_from_slice(&slice[3..]); // compile fail!
+     /// ```
+     ///
+     /// To work around this, we can use [`split_at_mut`] to create two distinct
+     /// sub-slices from a slice:
+     ///
+     /// ```
+     /// let mut slice = [1, 2, 3, 4, 5];
+     ///
+     /// {
+     ///     let (left, right) = slice.split_at_mut(2);
+     ///     left.clone_from_slice(&right[1..]);
+     /// }
+     ///
+     /// assert_eq!(slice, [4, 5, 3, 4, 5]);
+     /// ```
+     ///
+     /// [`copy_from_slice`]: #method.copy_from_slice
+     /// [`split_at_mut`]: #method.split_at_mut
+     #[stable(feature = "clone_from_slice", since = "1.7.0")]
+     pub fn clone_from_slice(&mut self, src: &[T])
+     where
+         T: Clone,
+     {
+         assert!(self.len() == src.len(), "destination and source slices have different lengths");
+         // NOTE: We need to explicitly slice them to the same length
+         // for bounds checking to be elided, and the optimizer will
+         // generate memcpy for simple cases (for example T = u8).
+         let len = self.len();
+         let src = &src[..len];
+         for i in 0..len {
+             self[i].clone_from(&src[i]);
+         }
+     }
+ 
+     /// Copies all elements from `src` into `self`, using a memcpy.
+     ///
+     /// The length of `src` must be the same as `self`.
+     ///
+     /// If `T` does not implement `Copy`, use [`clone_from_slice`].
+     ///
+     /// # Panics
+     ///
+     /// This function will panic if the two slices have different lengths.
+     ///
+     /// # Examples
+     ///
+     /// Copying two elements from a slice into another:
+     ///
+     /// ```
+     /// let src = [1, 2, 3, 4];
+     /// let mut dst = [0, 0];
+     ///
+     /// // Because the slices have to be the same length,
+     /// // we slice the source slice from four elements
+     /// // to two. It will panic if we don't do this.
+     /// dst.copy_from_slice(&src[2..]);
+     ///
+     /// assert_eq!(src, [1, 2, 3, 4]);
+     /// assert_eq!(dst, [3, 4]);
+     /// ```
+     ///
+     /// Rust enforces that there can only be one mutable reference with no
+     /// immutable references to a particular piece of data in a particular
+     /// scope. Because of this, attempting to use `copy_from_slice` on a
+     /// single slice will result in a compile failure:
+     ///
+     /// ```compile_fail
+     /// let mut slice = [1, 2, 3, 4, 5];
+     ///
+     /// slice[..2].copy_from_slice(&slice[3..]); // compile fail!
+     /// ```
+     ///
+     /// To work around this, we can use [`split_at_mut`] to create two distinct
+     /// sub-slices from a slice:
+     ///
+     /// ```
+     /// let mut slice = [1, 2, 3, 4, 5];
+     ///
+     /// {
+     ///     let (left, right) = slice.split_at_mut(2);
+     ///     left.copy_from_slice(&right[1..]);
+     /// }
+     ///
+     /// assert_eq!(slice, [4, 5, 3, 4, 5]);
+     /// ```
+     ///
+     /// [`clone_from_slice`]: #method.clone_from_slice
+     /// [`split_at_mut`]: #method.split_at_mut
+     #[stable(feature = "copy_from_slice", since = "1.9.0")]
+     pub fn copy_from_slice(&mut self, src: &[T])
+     where
+         T: Copy,
+     {
+         // The panic code path was put into a cold function to not bloat the
+         // call site.
+         #[inline(never)]
+         #[cold]
+         #[track_caller]
+         fn len_mismatch_fail(dst_len: usize, src_len: usize) -> ! {
+             panic!(
+                 "source slice length ({}) does not match destination slice length ({})",
+                 src_len, dst_len,
+             );
+         }
+ 
+         if self.len() != src.len() {
+             len_mismatch_fail(self.len(), src.len());
+         }
+ 
+         // SAFETY: `self` is valid for `self.len()` elements by definition, and `src` was
+         // checked to have the same length. The slices cannot overlap because
+         // mutable references are exclusive.
+         unsafe {
+             ptr::copy_nonoverlapping(src.as_ptr(), self.as_mut_ptr(), self.len());
+         }
+     }
+ 
+     /// Copies elements from one part of the slice to another part of itself,
+     /// using a memmove.
+     ///
+     /// `src` is the range within `self` to copy from. `dest` is the starting
+     /// index of the range within `self` to copy to, which will have the same
+     /// length as `src`. The two ranges may overlap. The ends of the two ranges
+     /// must be less than or equal to `self.len()`.
+     ///
+     /// # Panics
+     ///
+     /// This function will panic if either range exceeds the end of the slice,
+     /// or if the end of `src` is before the start.
+     ///
+     /// # Examples
+     ///
+     /// Copying four bytes within a slice:
+     ///
+     /// ```
+     /// let mut bytes = *b"Hello, World!";
+     ///
+     /// bytes.copy_within(1..5, 8);
+     ///
+     /// assert_eq!(&bytes, b"Hello, Wello!");
+     /// ```
+     #[stable(feature = "copy_within", since = "1.37.0")]
+     #[track_caller]
+     pub fn copy_within<R: RangeBounds<usize>>(&mut self, src: R, dest: usize)
+     where
+         T: Copy,
+     {
+         let Range { start: src_start, end: src_end } = src.assert_len(self.len());
+         let count = src_end - src_start;
+         assert!(dest <= self.len() - count, "dest is out of bounds");
+         // SAFETY: the conditions for `ptr::copy` have all been checked above,
+         // as have those for `ptr::add`.
+         unsafe {
+             ptr::copy(self.as_ptr().add(src_start), self.as_mut_ptr().add(dest), count);
+         }
+     }
+ 
+     /// Swaps all elements in `self` with those in `other`.
+     ///
+     /// The length of `other` must be the same as `self`.
+     ///
+     /// # Panics
+     ///
+     /// This function will panic if the two slices have different lengths.
+     ///
+     /// # Example
+     ///
+     /// Swapping two elements across slices:
+     ///
+     /// ```
+     /// let mut slice1 = [0, 0];
+     /// let mut slice2 = [1, 2, 3, 4];
+     ///
+     /// slice1.swap_with_slice(&mut slice2[2..]);
+     ///
+     /// assert_eq!(slice1, [3, 4]);
+     /// assert_eq!(slice2, [1, 2, 0, 0]);
+     /// ```
+     ///
+     /// Rust enforces that there can only be one mutable reference to a
+     /// particular piece of data in a particular scope. Because of this,
+     /// attempting to use `swap_with_slice` on a single slice will result in
+     /// a compile failure:
+     ///
+     /// ```compile_fail
+     /// let mut slice = [1, 2, 3, 4, 5];
+     /// slice[..2].swap_with_slice(&mut slice[3..]); // compile fail!
+     /// ```
+     ///
+     /// To work around this, we can use [`split_at_mut`] to create two distinct
+     /// mutable sub-slices from a slice:
+     ///
+     /// ```
+     /// let mut slice = [1, 2, 3, 4, 5];
+     ///
+     /// {
+     ///     let (left, right) = slice.split_at_mut(2);
+     ///     left.swap_with_slice(&mut right[1..]);
+     /// }
+     ///
+     /// assert_eq!(slice, [4, 5, 3, 1, 2]);
+     /// ```
+     ///
+     /// [`split_at_mut`]: #method.split_at_mut
+     #[stable(feature = "swap_with_slice", since = "1.27.0")]
+     pub fn swap_with_slice(&mut self, other: &mut [T]) {
+         assert!(self.len() == other.len(), "destination and source slices have different lengths");
+         // SAFETY: `self` is valid for `self.len()` elements by definition, and `src` was
+         // checked to have the same length. The slices cannot overlap because
+         // mutable references are exclusive.
+         unsafe {
+             ptr::swap_nonoverlapping(self.as_mut_ptr(), other.as_mut_ptr(), self.len());
+         }
+     }
+ 
+     /// Function to calculate lengths of the middle and trailing slice for `align_to{,_mut}`.
+     fn align_to_offsets<U>(&self) -> (usize, usize) {
+         // What we gonna do about `rest` is figure out what multiple of `U`s we can put in a
+         // lowest number of `T`s. And how many `T`s we need for each such "multiple".
+         //
+         // Consider for example T=u8 U=u16. Then we can put 1 U in 2 Ts. Simple. Now, consider
+         // for example a case where size_of::<T> = 16, size_of::<U> = 24. We can put 2 Us in
+         // place of every 3 Ts in the `rest` slice. A bit more complicated.
+         //
+         // Formula to calculate this is:
+         //
+         // Us = lcm(size_of::<T>, size_of::<U>) / size_of::<U>
+         // Ts = lcm(size_of::<T>, size_of::<U>) / size_of::<T>
+         //
+         // Expanded and simplified:
+         //
+         // Us = size_of::<T> / gcd(size_of::<T>, size_of::<U>)
+         // Ts = size_of::<U> / gcd(size_of::<T>, size_of::<U>)
+         //
+         // Luckily since all this is constant-evaluated... performance here matters not!
+         #[inline]
+         fn gcd(a: usize, b: usize) -> usize {
+             use crate::intrinsics;
+             // iterative stein’s algorithm
+             // We should still make this `const fn` (and revert to recursive algorithm if we do)
+             // because relying on llvm to consteval all this is… well, it makes me uncomfortable.
+ 
+             // SAFETY: `a` and `b` are checked to be non-zero values.
+             let (ctz_a, mut ctz_b) = unsafe {
+                 if a == 0 {
+                     return b;
+                 }
+                 if b == 0 {
+                     return a;
+                 }
+                 (intrinsics::cttz_nonzero(a), intrinsics::cttz_nonzero(b))
+             };
+             let k = ctz_a.min(ctz_b);
+             let mut a = a >> ctz_a;
+             let mut b = b;
+             loop {
+                 // remove all factors of 2 from b
+                 b >>= ctz_b;
+                 if a > b {
+                     mem::swap(&mut a, &mut b);
+                 }
+                 b = b - a;
+                 // SAFETY: `b` is checked to be non-zero.
+                 unsafe {
+                     if b == 0 {
+                         break;
+                     }
+                     ctz_b = intrinsics::cttz_nonzero(b);
+                 }
+             }
+             a << k
+         }
+         let gcd: usize = gcd(mem::size_of::<T>(), mem::size_of::<U>());
+         let ts: usize = mem::size_of::<U>() / gcd;
+         let us: usize = mem::size_of::<T>() / gcd;
+ 
+         // Armed with this knowledge, we can find how many `U`s we can fit!
+         let us_len = self.len() / ts * us;
+         // And how many `T`s will be in the trailing slice!
+         let ts_len = self.len() % ts;
+         (us_len, ts_len)
+     }
+ 
+     /// Transmute the slice to a slice of another type, ensuring alignment of the types is
+     /// maintained.
+     ///
+     /// This method splits the slice into three distinct slices: prefix, correctly aligned middle
+     /// slice of a new type, and the suffix slice. The method may make the middle slice the greatest
+     /// length possible for a given type and input slice, but only your algorithm's performance
+     /// should depend on that, not its correctness. It is permissible for all of the input data to
+     /// be returned as the prefix or suffix slice.
+     ///
+     /// This method has no purpose when either input element `T` or output element `U` are
+     /// zero-sized and will return the original slice without splitting anything.
+     ///
+     /// # Safety
+     ///
+     /// This method is essentially a `transmute` with respect to the elements in the returned
+     /// middle slice, so all the usual caveats pertaining to `transmute::<T, U>` also apply here.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// unsafe {
+     ///     let bytes: [u8; 7] = [1, 2, 3, 4, 5, 6, 7];
+     ///     let (prefix, shorts, suffix) = bytes.align_to::<u16>();
+     ///     // less_efficient_algorithm_for_bytes(prefix);
+     ///     // more_efficient_algorithm_for_aligned_shorts(shorts);
+     ///     // less_efficient_algorithm_for_bytes(suffix);
+     /// }
+     /// ```
+     #[stable(feature = "slice_align_to", since = "1.30.0")]
+     pub unsafe fn align_to<U>(&self) -> (&[T], &[U], &[T]) {
+         // Note that most of this function will be constant-evaluated,
+         if mem::size_of::<U>() == 0 || mem::size_of::<T>() == 0 {
+             // handle ZSTs specially, which is – don't handle them at all.
+             return (self, &[], &[]);
+         }
+ 
+         // First, find at what point do we split between the first and 2nd slice. Easy with
+         // ptr.align_offset.
+         let ptr = self.as_ptr();
+         // SAFETY: See the `align_to_mut` method for the detailed safety comment.
+         let offset = unsafe { crate::ptr::align_offset(ptr, mem::align_of::<U>()) };
+         if offset > self.len() {
+             (self, &[], &[])
+         } else {
+             let (left, rest) = self.split_at(offset);
+             let (us_len, ts_len) = rest.align_to_offsets::<U>();
+             // SAFETY: now `rest` is definitely aligned, so `from_raw_parts` below is okay,
+             // since the caller guarantees that we can transmute `T` to `U` safely.
+             unsafe {
+                 (
+                     left,
+                     from_raw_parts(rest.as_ptr() as *const U, us_len),
+                     from_raw_parts(rest.as_ptr().add(rest.len() - ts_len), ts_len),
+                 )
+             }
+         }
+     }
+ 
+     /// Transmute the slice to a slice of another type, ensuring alignment of the types is
+     /// maintained.
+     ///
+     /// This method splits the slice into three distinct slices: prefix, correctly aligned middle
+     /// slice of a new type, and the suffix slice. The method may make the middle slice the greatest
+     /// length possible for a given type and input slice, but only your algorithm's performance
+     /// should depend on that, not its correctness. It is permissible for all of the input data to
+     /// be returned as the prefix or suffix slice.
+     ///
+     /// This method has no purpose when either input element `T` or output element `U` are
+     /// zero-sized and will return the original slice without splitting anything.
+     ///
+     /// # Safety
+     ///
+     /// This method is essentially a `transmute` with respect to the elements in the returned
+     /// middle slice, so all the usual caveats pertaining to `transmute::<T, U>` also apply here.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// unsafe {
+     ///     let mut bytes: [u8; 7] = [1, 2, 3, 4, 5, 6, 7];
+     ///     let (prefix, shorts, suffix) = bytes.align_to_mut::<u16>();
+     ///     // less_efficient_algorithm_for_bytes(prefix);
+     ///     // more_efficient_algorithm_for_aligned_shorts(shorts);
+     ///     // less_efficient_algorithm_for_bytes(suffix);
+     /// }
+     /// ```
+     #[stable(feature = "slice_align_to", since = "1.30.0")]
+     pub unsafe fn align_to_mut<U>(&mut self) -> (&mut [T], &mut [U], &mut [T]) {
+         // Note that most of this function will be constant-evaluated,
+         if mem::size_of::<U>() == 0 || mem::size_of::<T>() == 0 {
+             // handle ZSTs specially, which is – don't handle them at all.
+             return (self, &mut [], &mut []);
+         }
+ 
+         // First, find at what point do we split between the first and 2nd slice. Easy with
+         // ptr.align_offset.
+         let ptr = self.as_ptr();
+         // SAFETY: Here we are ensuring we will use aligned pointers for U for the
+         // rest of the method. This is done by passing a pointer to &[T] with an
+         // alignment targeted for U.
+         // `crate::ptr::align_offset` is called with a correctly aligned and
+         // valid pointer `ptr` (it comes from a reference to `self`) and with
+         // a size that is a power of two (since it comes from the alignement for U),
+         // satisfying its safety constraints.
+         let offset = unsafe { crate::ptr::align_offset(ptr, mem::align_of::<U>()) };
+         if offset > self.len() {
+             (self, &mut [], &mut [])
+         } else {
+             let (left, rest) = self.split_at_mut(offset);
+             let (us_len, ts_len) = rest.align_to_offsets::<U>();
+             let rest_len = rest.len();
+             let mut_ptr = rest.as_mut_ptr();
+             // We can't use `rest` again after this, that would invalidate its alias `mut_ptr`!
+             // SAFETY: see comments for `align_to`.
+             unsafe {
+                 (
+                     left,
+                     from_raw_parts_mut(mut_ptr as *mut U, us_len),
+                     from_raw_parts_mut(mut_ptr.add(rest_len - ts_len), ts_len),
+                 )
+             }
+         }
+     }
+ 
+     /// Checks if the elements of this slice are sorted.
+     ///
+     /// That is, for each element `a` and its following element `b`, `a <= b` must hold. If the
+     /// slice yields exactly zero or one element, `true` is returned.
+     ///
+     /// Note that if `Self::Item` is only `PartialOrd`, but not `Ord`, the above definition
+     /// implies that this function returns `false` if any two consecutive items are not
+     /// comparable.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(is_sorted)]
+     /// let empty: [i32; 0] = [];
+     ///
+     /// assert!([1, 2, 2, 9].is_sorted());
+     /// assert!(![1, 3, 2, 4].is_sorted());
+     /// assert!([0].is_sorted());
+     /// assert!(empty.is_sorted());
+     /// assert!(![0.0, 1.0, f32::NAN].is_sorted());
+     /// ```
+     #[inline]
+     #[unstable(feature = "is_sorted", reason = "new API", issue = "53485")]
+     pub fn is_sorted(&self) -> bool
+     where
+         T: PartialOrd,
+     {
+         self.is_sorted_by(|a, b| a.partial_cmp(b))
+     }
+ 
+     /// Checks if the elements of this slice are sorted using the given comparator function.
+     ///
+     /// Instead of using `PartialOrd::partial_cmp`, this function uses the given `compare`
+     /// function to determine the ordering of two elements. Apart from that, it's equivalent to
+     /// [`is_sorted`]; see its documentation for more information.
+     ///
+     /// [`is_sorted`]: #method.is_sorted
+     #[unstable(feature = "is_sorted", reason = "new API", issue = "53485")]
+     pub fn is_sorted_by<F>(&self, mut compare: F) -> bool
+     where
+         F: FnMut(&T, &T) -> Option<Ordering>,
+     {
+         self.iter().is_sorted_by(|a, b| compare(*a, *b))
+     }
+ 
+     /// Checks if the elements of this slice are sorted using the given key extraction function.
+     ///
+     /// Instead of comparing the slice's elements directly, this function compares the keys of the
+     /// elements, as determined by `f`. Apart from that, it's equivalent to [`is_sorted`]; see its
+     /// documentation for more information.
+     ///
+     /// [`is_sorted`]: #method.is_sorted
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(is_sorted)]
+     ///
+     /// assert!(["c", "bb", "aaa"].is_sorted_by_key(|s| s.len()));
+     /// assert!(![-2i32, -1, 0, 3].is_sorted_by_key(|n| n.abs()));
+     /// ```
+     #[inline]
+     #[unstable(feature = "is_sorted", reason = "new API", issue = "53485")]
+     pub fn is_sorted_by_key<F, K>(&self, f: F) -> bool
+     where
+         F: FnMut(&T) -> K,
+         K: PartialOrd,
+     {
+         self.iter().is_sorted_by_key(f)
+     }
+ 
+     /// Returns the index of the partition point according to the given predicate
+     /// (the index of the first element of the second partition).
+     ///
+     /// The slice is assumed to be partitioned according to the given predicate.
+     /// This means that all elements for which the predicate returns true are at the start of the slice
+     /// and all elements for which the predicate returns false are at the end.
+     /// For example, [7, 15, 3, 5, 4, 12, 6] is a partitioned under the predicate x % 2 != 0
+     /// (all odd numbers are at the start, all even at the end).
+     ///
+     /// If this slice is not partitioned, the returned result is unspecified and meaningless,
+     /// as this method performs a kind of binary search.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(partition_point)]
+     ///
+     /// let v = [1, 2, 3, 3, 5, 6, 7];
+     /// let i = v.partition_point(|&x| x < 5);
+     ///
+     /// assert_eq!(i, 4);
+     /// assert!(v[..i].iter().all(|&x| x < 5));
+     /// assert!(v[i..].iter().all(|&x| !(x < 5)));
+     /// ```
+     #[unstable(feature = "partition_point", reason = "new API", issue = "73831")]
+     pub fn partition_point<P>(&self, mut pred: P) -> usize
+     where
+         P: FnMut(&T) -> bool,
+     {
+         let mut left = 0;
+         let mut right = self.len();
+ 
+         while left != right {
+             let mid = left + (right - left) / 2;
+             // SAFETY: When `left < right`, `left <= mid < right`.
+             // Therefore `left` always increases and `right` always decreases,
+             // and either of them is selected. In both cases `left <= right` is
+             // satisfied. Therefore if `left < right` in a step, `left <= right`
+             // is satisfied in the next step. Therefore as long as `left != right`,
+             // `0 <= left < right <= len` is satisfied and if this case
+             // `0 <= mid < len` is satisfied too.
+             let value = unsafe { self.get_unchecked(mid) };
+             if pred(value) {
+                 left = mid + 1;
+             } else {
+                 right = mid;
+             }
+         }
+ 
+         left
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Default for &[T] {
+     /// Creates an empty slice.
+     fn default() -> Self {
+         &[]
+     }
+ }
+ 
+ #[stable(feature = "mut_slice_default", since = "1.5.0")]
+ impl<T> Default for &mut [T] {
+     /// Creates a mutable empty slice.
+     fn default() -> Self {
+         &mut []
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/raw.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/raw.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/raw.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/raw.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,151 ----
+ //! Free functions to create `&[T]` and `&mut [T]`.
+ 
+ use crate::array;
+ use crate::intrinsics::is_aligned_and_not_null;
+ use crate::mem;
+ use crate::ptr;
+ 
+ /// Forms a slice from a pointer and a length.
+ ///
+ /// The `len` argument is the number of **elements**, not the number of bytes.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `data` must be [valid] for reads for `len * mem::size_of::<T>()` many bytes,
+ ///   and it must be properly aligned. This means in particular:
+ ///
+ ///     * The entire memory range of this slice must be contained within a single allocated object!
+ ///       Slices can never span across multiple allocated objects. See [below](#incorrect-usage)
+ ///       for an example incorrectly not taking this into account.
+ ///     * `data` must be non-null and aligned even for zero-length slices. One
+ ///       reason for this is that enum layout optimizations may rely on references
+ ///       (including slices of any length) being aligned and non-null to distinguish
+ ///       them from other data. You can obtain a pointer that is usable as `data`
+ ///       for zero-length slices using [`NonNull::dangling()`].
+ ///
+ /// * `data` must point to `len` consecutive properly initialized values of type `T`.
+ ///
+ /// * The memory referenced by the returned slice must not be mutated for the duration
+ ///   of lifetime `'a`, except inside an `UnsafeCell`.
+ ///
+ /// * The total size `len * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+ ///   See the safety documentation of [`pointer::offset`].
+ ///
+ /// # Caveat
+ ///
+ /// The lifetime for the returned slice is inferred from its usage. To
+ /// prevent accidental misuse, it's suggested to tie the lifetime to whichever
+ /// source lifetime is safe in the context, such as by providing a helper
+ /// function taking the lifetime of a host value for the slice, or by explicit
+ /// annotation.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::slice;
+ ///
+ /// // manifest a slice for a single element
+ /// let x = 42;
+ /// let ptr = &x as *const _;
+ /// let slice = unsafe { slice::from_raw_parts(ptr, 1) };
+ /// assert_eq!(slice[0], 42);
+ /// ```
+ ///
+ /// ### Incorrect usage
+ ///
+ /// The following `join_slices` function is **unsound** ⚠️
+ ///
+ /// ```rust,no_run
+ /// use std::slice;
+ ///
+ /// fn join_slices<'a, T>(fst: &'a [T], snd: &'a [T]) -> &'a [T] {
+ ///     let fst_end = fst.as_ptr().wrapping_add(fst.len());
+ ///     let snd_start = snd.as_ptr();
+ ///     assert_eq!(fst_end, snd_start, "Slices must be contiguous!");
+ ///     unsafe {
+ ///         // The assertion above ensures `fst` and `snd` are contiguous, but they might
+ ///         // still be contained within _different allocated objects_, in which case
+ ///         // creating this slice is undefined behavior.
+ ///         slice::from_raw_parts(fst.as_ptr(), fst.len() + snd.len())
+ ///     }
+ /// }
+ ///
+ /// fn main() {
+ ///     // `a` and `b` are different allocated objects...
+ ///     let a = 42;
+ ///     let b = 27;
+ ///     // ... which may nevertheless be laid out contiguously in memory: | a | b |
+ ///     let _ = join_slices(slice::from_ref(&a), slice::from_ref(&b)); // UB
+ /// }
+ /// ```
+ ///
+ /// [valid]: ptr#safety
+ /// [`NonNull::dangling()`]: ptr::NonNull::dangling
+ /// [`pointer::offset`]: ../../std/primitive.pointer.html#method.offset
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn from_raw_parts<'a, T>(data: *const T, len: usize) -> &'a [T] {
+     debug_assert!(is_aligned_and_not_null(data), "attempt to create unaligned or null slice");
+     debug_assert!(
+         mem::size_of::<T>().saturating_mul(len) <= isize::MAX as usize,
+         "attempt to create slice covering at least half the address space"
+     );
+     // SAFETY: the caller must uphold the safety contract for `from_raw_parts`.
+     unsafe { &*ptr::slice_from_raw_parts(data, len) }
+ }
+ 
+ /// Performs the same functionality as [`from_raw_parts`], except that a
+ /// mutable slice is returned.
+ ///
+ /// # Safety
+ ///
+ /// Behavior is undefined if any of the following conditions are violated:
+ ///
+ /// * `data` must be [valid] for boths reads and writes for `len * mem::size_of::<T>()` many bytes,
+ ///   and it must be properly aligned. This means in particular:
+ ///
+ ///     * The entire memory range of this slice must be contained within a single allocated object!
+ ///       Slices can never span across multiple allocated objects.
+ ///     * `data` must be non-null and aligned even for zero-length slices. One
+ ///       reason for this is that enum layout optimizations may rely on references
+ ///       (including slices of any length) being aligned and non-null to distinguish
+ ///       them from other data. You can obtain a pointer that is usable as `data`
+ ///       for zero-length slices using [`NonNull::dangling()`].
+ ///
+ /// * `data` must point to `len` consecutive properly initialized values of type `T`.
+ ///
+ /// * The memory referenced by the returned slice must not be accessed through any other pointer
+ ///   (not derived from the return value) for the duration of lifetime `'a`.
+ ///   Both read and write accesses are forbidden.
+ ///
+ /// * The total size `len * mem::size_of::<T>()` of the slice must be no larger than `isize::MAX`.
+ ///   See the safety documentation of [`pointer::offset`].
+ ///
+ /// [valid]: ptr#safety
+ /// [`NonNull::dangling()`]: ptr::NonNull::dangling
+ /// [`pointer::offset`]: ../../std/primitive.pointer.html#method.offset
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub unsafe fn from_raw_parts_mut<'a, T>(data: *mut T, len: usize) -> &'a mut [T] {
+     debug_assert!(is_aligned_and_not_null(data), "attempt to create unaligned or null slice");
+     debug_assert!(
+         mem::size_of::<T>().saturating_mul(len) <= isize::MAX as usize,
+         "attempt to create slice covering at least half the address space"
+     );
+     // SAFETY: the caller must uphold the safety contract for `from_raw_parts_mut`.
+     unsafe { &mut *ptr::slice_from_raw_parts_mut(data, len) }
+ }
+ 
+ /// Converts a reference to T into a slice of length 1 (without copying).
+ #[stable(feature = "from_ref", since = "1.28.0")]
+ pub fn from_ref<T>(s: &T) -> &[T] {
+     array::from_ref(s)
+ }
+ 
+ /// Converts a reference to T into a slice of length 1 (without copying).
+ #[stable(feature = "from_ref", since = "1.28.0")]
+ pub fn from_mut<T>(s: &mut T) -> &mut [T] {
+     array::from_mut(s)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/rotate.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/rotate.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/rotate.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/rotate.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,182 ----
+ // ignore-tidy-undocumented-unsafe
+ 
+ use crate::cmp;
+ use crate::mem::{self, MaybeUninit};
+ use crate::ptr;
+ 
+ /// Rotates the range `[mid-left, mid+right)` such that the element at `mid` becomes the first
+ /// element. Equivalently, rotates the range `left` elements to the left or `right` elements to the
+ /// right.
+ ///
+ /// # Safety
+ ///
+ /// The specified range must be valid for reading and writing.
+ ///
+ /// # Algorithm
+ ///
+ /// Algorithm 1 is used for small values of `left + right` or for large `T`. The elements are moved
+ /// into their final positions one at a time starting at `mid - left` and advancing by `right` steps
+ /// modulo `left + right`, such that only one temporary is needed. Eventually, we arrive back at
+ /// `mid - left`. However, if `gcd(left + right, right)` is not 1, the above steps skipped over
+ /// elements. For example:
+ /// ```text
+ /// left = 10, right = 6
+ /// the `^` indicates an element in its final place
+ /// 6 7 8 9 10 11 12 13 14 15 . 0 1 2 3 4 5
+ /// after using one step of the above algorithm (The X will be overwritten at the end of the round,
+ /// and 12 is stored in a temporary):
+ /// X 7 8 9 10 11 6 13 14 15 . 0 1 2 3 4 5
+ ///               ^
+ /// after using another step (now 2 is in the temporary):
+ /// X 7 8 9 10 11 6 13 14 15 . 0 1 12 3 4 5
+ ///               ^                 ^
+ /// after the third step (the steps wrap around, and 8 is in the temporary):
+ /// X 7 2 9 10 11 6 13 14 15 . 0 1 12 3 4 5
+ ///     ^         ^                 ^
+ /// after 7 more steps, the round ends with the temporary 0 getting put in the X:
+ /// 0 7 2 9 4 11 6 13 8 15 . 10 1 12 3 14 5
+ /// ^   ^   ^    ^    ^       ^    ^    ^
+ /// ```
+ /// Fortunately, the number of skipped over elements between finalized elements is always equal, so
+ /// we can just offset our starting position and do more rounds (the total number of rounds is the
+ /// `gcd(left + right, right)` value). The end result is that all elements are finalized once and
+ /// only once.
+ ///
+ /// Algorithm 2 is used if `left + right` is large but `min(left, right)` is small enough to
+ /// fit onto a stack buffer. The `min(left, right)` elements are copied onto the buffer, `memmove`
+ /// is applied to the others, and the ones on the buffer are moved back into the hole on the
+ /// opposite side of where they originated.
+ ///
+ /// Algorithms that can be vectorized outperform the above once `left + right` becomes large enough.
+ /// Algorithm 1 can be vectorized by chunking and performing many rounds at once, but there are too
+ /// few rounds on average until `left + right` is enormous, and the worst case of a single
+ /// round is always there. Instead, algorithm 3 utilizes repeated swapping of
+ /// `min(left, right)` elements until a smaller rotate problem is left.
+ ///
+ /// ```text
+ /// left = 11, right = 4
+ /// [4 5 6 7 8 9 10 11 12 13 14 . 0 1 2 3]
+ ///                  ^  ^  ^  ^   ^ ^ ^ ^ swapping the right most elements with elements to the left
+ /// [4 5 6 7 8 9 10 . 0 1 2 3] 11 12 13 14
+ ///        ^ ^ ^  ^   ^ ^ ^ ^ swapping these
+ /// [4 5 6 . 0 1 2 3] 7 8 9 10 11 12 13 14
+ /// we cannot swap any more, but a smaller rotation problem is left to solve
+ /// ```
+ /// when `left < right` the swapping happens from the left instead.
+ pub unsafe fn ptr_rotate<T>(mut left: usize, mut mid: *mut T, mut right: usize) {
+     type BufType = [usize; 32];
+     if mem::size_of::<T>() == 0 {
+         return;
+     }
+     loop {
+         // N.B. the below algorithms can fail if these cases are not checked
+         if (right == 0) || (left == 0) {
+             return;
+         }
+         if (left + right < 24) || (mem::size_of::<T>() > mem::size_of::<[usize; 4]>()) {
+             // Algorithm 1
+             // Microbenchmarks indicate that the average performance for random shifts is better all
+             // the way until about `left + right == 32`, but the worst case performance breaks even
+             // around 16. 24 was chosen as middle ground. If the size of `T` is larger than 4
+             // `usize`s, this algorithm also outperforms other algorithms.
+             let x = unsafe { mid.sub(left) };
+             // beginning of first round
+             let mut tmp: T = unsafe { x.read() };
+             let mut i = right;
+             // `gcd` can be found before hand by calculating `gcd(left + right, right)`,
+             // but it is faster to do one loop which calculates the gcd as a side effect, then
+             // doing the rest of the chunk
+             let mut gcd = right;
+             // benchmarks reveal that it is faster to swap temporaries all the way through instead
+             // of reading one temporary once, copying backwards, and then writing that temporary at
+             // the very end. This is possibly due to the fact that swapping or replacing temporaries
+             // uses only one memory address in the loop instead of needing to manage two.
+             loop {
+                 tmp = unsafe { x.add(i).replace(tmp) };
+                 // instead of incrementing `i` and then checking if it is outside the bounds, we
+                 // check if `i` will go outside the bounds on the next increment. This prevents
+                 // any wrapping of pointers or `usize`.
+                 if i >= left {
+                     i -= left;
+                     if i == 0 {
+                         // end of first round
+                         unsafe { x.write(tmp) };
+                         break;
+                     }
+                     // this conditional must be here if `left + right >= 15`
+                     if i < gcd {
+                         gcd = i;
+                     }
+                 } else {
+                     i += right;
+                 }
+             }
+             // finish the chunk with more rounds
+             for start in 1..gcd {
+                 tmp = unsafe { x.add(start).read() };
+                 i = start + right;
+                 loop {
+                     tmp = unsafe { x.add(i).replace(tmp) };
+                     if i >= left {
+                         i -= left;
+                         if i == start {
+                             unsafe { x.add(start).write(tmp) };
+                             break;
+                         }
+                     } else {
+                         i += right;
+                     }
+                 }
+             }
+             return;
+         // `T` is not a zero-sized type, so it's okay to divide by its size.
+         } else if cmp::min(left, right) <= mem::size_of::<BufType>() / mem::size_of::<T>() {
+             // Algorithm 2
+             // The `[T; 0]` here is to ensure this is appropriately aligned for T
+             let mut rawarray = MaybeUninit::<(BufType, [T; 0])>::uninit();
+             let buf = rawarray.as_mut_ptr() as *mut T;
+             let dim = unsafe { mid.sub(left).add(right) };
+             if left <= right {
+                 unsafe {
+                     ptr::copy_nonoverlapping(mid.sub(left), buf, left);
+                     ptr::copy(mid, mid.sub(left), right);
+                     ptr::copy_nonoverlapping(buf, dim, left);
+                 }
+             } else {
+                 unsafe {
+                     ptr::copy_nonoverlapping(mid, buf, right);
+                     ptr::copy(mid.sub(left), dim, left);
+                     ptr::copy_nonoverlapping(buf, mid.sub(left), right);
+                 }
+             }
+             return;
+         } else if left >= right {
+             // Algorithm 3
+             // There is an alternate way of swapping that involves finding where the last swap
+             // of this algorithm would be, and swapping using that last chunk instead of swapping
+             // adjacent chunks like this algorithm is doing, but this way is still faster.
+             loop {
+                 unsafe {
+                     ptr::swap_nonoverlapping(mid.sub(right), mid, right);
+                     mid = mid.sub(right);
+                 }
+                 left -= right;
+                 if left < right {
+                     break;
+                 }
+             }
+         } else {
+             // Algorithm 3, `left < right`
+             loop {
+                 unsafe {
+                     ptr::swap_nonoverlapping(mid.sub(left), mid, left);
+                     mid = mid.add(left);
+                 }
+                 right -= left;
+                 if right < left {
+                     break;
+                 }
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/slice/sort.rs gcc-16-20251102/libgrust/rustc-lib/core/src/slice/sort.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/slice/sort.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/slice/sort.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,874 ----
+ //! Slice sorting
+ //!
+ //! This module contains a sorting algorithm based on Orson Peters' pattern-defeating quicksort,
+ //! published at: <https://github.com/orlp/pdqsort>
+ //!
+ //! Unstable sorting is compatible with libcore because it doesn't allocate memory, unlike our
+ //! stable sorting implementation.
+ 
+ // ignore-tidy-undocumented-unsafe
+ 
+ use crate::cmp;
+ use crate::mem::{self, MaybeUninit};
+ use crate::ptr;
+ 
+ /// When dropped, copies from `src` into `dest`.
+ struct CopyOnDrop<T> {
+     src: *mut T,
+     dest: *mut T,
+ }
+ 
+ impl<T> Drop for CopyOnDrop<T> {
+     fn drop(&mut self) {
+         // SAFETY:  This is a helper class.
+         //          Please refer to its usage for correctness.
+         //          Namely, one must be sure that `src` and `dst` does not overlap as required by `ptr::copy_nonoverlapping`.
+         unsafe {
+             ptr::copy_nonoverlapping(self.src, self.dest, 1);
+         }
+     }
+ }
+ 
+ /// Shifts the first element to the right until it encounters a greater or equal element.
+ fn shift_head<T, F>(v: &mut [T], is_less: &mut F)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     let len = v.len();
+     // SAFETY: The unsafe operations below involves indexing without a bound check (`get_unchecked` and `get_unchecked_mut`)
+     // and copying memory (`ptr::copy_nonoverlapping`).
+     //
+     // a. Indexing:
+     //  1. We checked the size of the array to >=2.
+     //  2. All the indexing that we will do is always between {0 <= index < len} at most.
+     //
+     // b. Memory copying
+     //  1. We are obtaining pointers to references which are guaranteed to be valid.
+     //  2. They cannot overlap because we obtain pointers to difference indices of the slice.
+     //     Namely, `i` and `i-1`.
+     //  3. If the slice is properly aligned, the elements are properly aligned.
+     //     It is the caller's responsibility to make sure the slice is properly aligned.
+     //
+     // See comments below for further detail.
+     unsafe {
+         // If the first two elements are out-of-order...
+         if len >= 2 && is_less(v.get_unchecked(1), v.get_unchecked(0)) {
+             // Read the first element into a stack-allocated variable. If a following comparison
+             // operation panics, `hole` will get dropped and automatically write the element back
+             // into the slice.
+             let mut tmp = mem::ManuallyDrop::new(ptr::read(v.get_unchecked(0)));
+             let mut hole = CopyOnDrop { src: &mut *tmp, dest: v.get_unchecked_mut(1) };
+             ptr::copy_nonoverlapping(v.get_unchecked(1), v.get_unchecked_mut(0), 1);
+ 
+             for i in 2..len {
+                 if !is_less(v.get_unchecked(i), &*tmp) {
+                     break;
+                 }
+ 
+                 // Move `i`-th element one place to the left, thus shifting the hole to the right.
+                 ptr::copy_nonoverlapping(v.get_unchecked(i), v.get_unchecked_mut(i - 1), 1);
+                 hole.dest = v.get_unchecked_mut(i);
+             }
+             // `hole` gets dropped and thus copies `tmp` into the remaining hole in `v`.
+         }
+     }
+ }
+ 
+ /// Shifts the last element to the left until it encounters a smaller or equal element.
+ fn shift_tail<T, F>(v: &mut [T], is_less: &mut F)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     let len = v.len();
+     // SAFETY: The unsafe operations below involves indexing without a bound check (`get_unchecked` and `get_unchecked_mut`)
+     // and copying memory (`ptr::copy_nonoverlapping`).
+     //
+     // a. Indexing:
+     //  1. We checked the size of the array to >= 2.
+     //  2. All the indexing that we will do is always between `0 <= index < len-1` at most.
+     //
+     // b. Memory copying
+     //  1. We are obtaining pointers to references which are guaranteed to be valid.
+     //  2. They cannot overlap because we obtain pointers to difference indices of the slice.
+     //     Namely, `i` and `i+1`.
+     //  3. If the slice is properly aligned, the elements are properly aligned.
+     //     It is the caller's responsibility to make sure the slice is properly aligned.
+     //
+     // See comments below for further detail.
+     unsafe {
+         // If the last two elements are out-of-order...
+         if len >= 2 && is_less(v.get_unchecked(len - 1), v.get_unchecked(len - 2)) {
+             // Read the last element into a stack-allocated variable. If a following comparison
+             // operation panics, `hole` will get dropped and automatically write the element back
+             // into the slice.
+             let mut tmp = mem::ManuallyDrop::new(ptr::read(v.get_unchecked(len - 1)));
+             let mut hole = CopyOnDrop { src: &mut *tmp, dest: v.get_unchecked_mut(len - 2) };
+             ptr::copy_nonoverlapping(v.get_unchecked(len - 2), v.get_unchecked_mut(len - 1), 1);
+ 
+             for i in (0..len - 2).rev() {
+                 if !is_less(&*tmp, v.get_unchecked(i)) {
+                     break;
+                 }
+ 
+                 // Move `i`-th element one place to the right, thus shifting the hole to the left.
+                 ptr::copy_nonoverlapping(v.get_unchecked(i), v.get_unchecked_mut(i + 1), 1);
+                 hole.dest = v.get_unchecked_mut(i);
+             }
+             // `hole` gets dropped and thus copies `tmp` into the remaining hole in `v`.
+         }
+     }
+ }
+ 
+ /// Partially sorts a slice by shifting several out-of-order elements around.
+ ///
+ /// Returns `true` if the slice is sorted at the end. This function is *O*(*n*) worst-case.
+ #[cold]
+ fn partial_insertion_sort<T, F>(v: &mut [T], is_less: &mut F) -> bool
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // Maximum number of adjacent out-of-order pairs that will get shifted.
+     const MAX_STEPS: usize = 5;
+     // If the slice is shorter than this, don't shift any elements.
+     const SHORTEST_SHIFTING: usize = 50;
+ 
+     let len = v.len();
+     let mut i = 1;
+ 
+     for _ in 0..MAX_STEPS {
+         // SAFETY: We already explicitly did the bound checking with `i < len`.
+         // All our subsequent indexing is only in the range `0 <= index < len`
+         unsafe {
+             // Find the next pair of adjacent out-of-order elements.
+             while i < len && !is_less(v.get_unchecked(i), v.get_unchecked(i - 1)) {
+                 i += 1;
+             }
+         }
+ 
+         // Are we done?
+         if i == len {
+             return true;
+         }
+ 
+         // Don't shift elements on short arrays, that has a performance cost.
+         if len < SHORTEST_SHIFTING {
+             return false;
+         }
+ 
+         // Swap the found pair of elements. This puts them in correct order.
+         v.swap(i - 1, i);
+ 
+         // Shift the smaller element to the left.
+         shift_tail(&mut v[..i], is_less);
+         // Shift the greater element to the right.
+         shift_head(&mut v[i..], is_less);
+     }
+ 
+     // Didn't manage to sort the slice in the limited number of steps.
+     false
+ }
+ 
+ /// Sorts a slice using insertion sort, which is *O*(*n*^2) worst-case.
+ fn insertion_sort<T, F>(v: &mut [T], is_less: &mut F)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     for i in 1..v.len() {
+         shift_tail(&mut v[..i + 1], is_less);
+     }
+ }
+ 
+ /// Sorts `v` using heapsort, which guarantees *O*(*n* \* log(*n*)) worst-case.
+ #[cold]
+ #[unstable(feature = "sort_internals", reason = "internal to sort module", issue = "none")]
+ pub fn heapsort<T, F>(v: &mut [T], mut is_less: F)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // This binary heap respects the invariant `parent >= child`.
+     let mut sift_down = |v: &mut [T], mut node| {
+         loop {
+             // Children of `node`:
+             let left = 2 * node + 1;
+             let right = 2 * node + 2;
+ 
+             // Choose the greater child.
+             let greater =
+                 if right < v.len() && is_less(&v[left], &v[right]) { right } else { left };
+ 
+             // Stop if the invariant holds at `node`.
+             if greater >= v.len() || !is_less(&v[node], &v[greater]) {
+                 break;
+             }
+ 
+             // Swap `node` with the greater child, move one step down, and continue sifting.
+             v.swap(node, greater);
+             node = greater;
+         }
+     };
+ 
+     // Build the heap in linear time.
+     for i in (0..v.len() / 2).rev() {
+         sift_down(v, i);
+     }
+ 
+     // Pop maximal elements from the heap.
+     for i in (1..v.len()).rev() {
+         v.swap(0, i);
+         sift_down(&mut v[..i], 0);
+     }
+ }
+ 
+ /// Partitions `v` into elements smaller than `pivot`, followed by elements greater than or equal
+ /// to `pivot`.
+ ///
+ /// Returns the number of elements smaller than `pivot`.
+ ///
+ /// Partitioning is performed block-by-block in order to minimize the cost of branching operations.
+ /// This idea is presented in the [BlockQuicksort][pdf] paper.
+ ///
+ /// [pdf]: http://drops.dagstuhl.de/opus/volltexte/2016/6389/pdf/LIPIcs-ESA-2016-38.pdf
+ fn partition_in_blocks<T, F>(v: &mut [T], pivot: &T, is_less: &mut F) -> usize
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // Number of elements in a typical block.
+     const BLOCK: usize = 128;
+ 
+     // The partitioning algorithm repeats the following steps until completion:
+     //
+     // 1. Trace a block from the left side to identify elements greater than or equal to the pivot.
+     // 2. Trace a block from the right side to identify elements smaller than the pivot.
+     // 3. Exchange the identified elements between the left and right side.
+     //
+     // We keep the following variables for a block of elements:
+     //
+     // 1. `block` - Number of elements in the block.
+     // 2. `start` - Start pointer into the `offsets` array.
+     // 3. `end` - End pointer into the `offsets` array.
+     // 4. `offsets - Indices of out-of-order elements within the block.
+ 
+     // The current block on the left side (from `l` to `l.add(block_l)`).
+     let mut l = v.as_mut_ptr();
+     let mut block_l = BLOCK;
+     let mut start_l = ptr::null_mut();
+     let mut end_l = ptr::null_mut();
+     let mut offsets_l = [MaybeUninit::<u8>::uninit(); BLOCK];
+ 
+     // The current block on the right side (from `r.sub(block_r)` to `r`).
+     // SAFETY: The documentation for .add() specifically mention that `vec.as_ptr().add(vec.len())` is always safe`
+     let mut r = unsafe { l.add(v.len()) };
+     let mut block_r = BLOCK;
+     let mut start_r = ptr::null_mut();
+     let mut end_r = ptr::null_mut();
+     let mut offsets_r = [MaybeUninit::<u8>::uninit(); BLOCK];
+ 
+     // FIXME: When we get VLAs, try creating one array of length `min(v.len(), 2 * BLOCK)` rather
+     // than two fixed-size arrays of length `BLOCK`. VLAs might be more cache-efficient.
+ 
+     // Returns the number of elements between pointers `l` (inclusive) and `r` (exclusive).
+     fn width<T>(l: *mut T, r: *mut T) -> usize {
+         assert!(mem::size_of::<T>() > 0);
+         (r as usize - l as usize) / mem::size_of::<T>()
+     }
+ 
+     loop {
+         // We are done with partitioning block-by-block when `l` and `r` get very close. Then we do
+         // some patch-up work in order to partition the remaining elements in between.
+         let is_done = width(l, r) <= 2 * BLOCK;
+ 
+         if is_done {
+             // Number of remaining elements (still not compared to the pivot).
+             let mut rem = width(l, r);
+             if start_l < end_l || start_r < end_r {
+                 rem -= BLOCK;
+             }
+ 
+             // Adjust block sizes so that the left and right block don't overlap, but get perfectly
+             // aligned to cover the whole remaining gap.
+             if start_l < end_l {
+                 block_r = rem;
+             } else if start_r < end_r {
+                 block_l = rem;
+             } else {
+                 block_l = rem / 2;
+                 block_r = rem - block_l;
+             }
+             debug_assert!(block_l <= BLOCK && block_r <= BLOCK);
+             debug_assert!(width(l, r) == block_l + block_r);
+         }
+ 
+         if start_l == end_l {
+             // Trace `block_l` elements from the left side.
+             start_l = MaybeUninit::slice_as_mut_ptr(&mut offsets_l);
+             end_l = MaybeUninit::slice_as_mut_ptr(&mut offsets_l);
+             let mut elem = l;
+ 
+             for i in 0..block_l {
+                 // SAFETY: The unsafety operations below involve the usage of the `offset`.
+                 //         According to the conditions required by the function, we satisfy them because:
+                 //         1. `offsets_l` is stack-allocated, and thus considered separate allocated object.
+                 //         2. The function `is_less` returns a `bool`.
+                 //            Casting a `bool` will never overflow `isize`.
+                 //         3. We have guaranteed that `block_l` will be `<= BLOCK`.
+                 //            Plus, `end_l` was initially set to the begin pointer of `offsets_` which was declared on the stack.
+                 //            Thus, we know that even in the worst case (all invocations of `is_less` returns false) we will only be at most 1 byte pass the end.
+                 //        Another unsafety operation here is dereferencing `elem`.
+                 //        However, `elem` was initially the begin pointer to the slice which is always valid.
+                 unsafe {
+                     // Branchless comparison.
+                     *end_l = i as u8;
+                     end_l = end_l.offset(!is_less(&*elem, pivot) as isize);
+                     elem = elem.offset(1);
+                 }
+             }
+         }
+ 
+         if start_r == end_r {
+             // Trace `block_r` elements from the right side.
+             start_r = MaybeUninit::slice_as_mut_ptr(&mut offsets_r);
+             end_r = MaybeUninit::slice_as_mut_ptr(&mut offsets_r);
+             let mut elem = r;
+ 
+             for i in 0..block_r {
+                 // SAFETY: The unsafety operations below involve the usage of the `offset`.
+                 //         According to the conditions required by the function, we satisfy them because:
+                 //         1. `offsets_r` is stack-allocated, and thus considered separate allocated object.
+                 //         2. The function `is_less` returns a `bool`.
+                 //            Casting a `bool` will never overflow `isize`.
+                 //         3. We have guaranteed that `block_r` will be `<= BLOCK`.
+                 //            Plus, `end_r` was initially set to the begin pointer of `offsets_` which was declared on the stack.
+                 //            Thus, we know that even in the worst case (all invocations of `is_less` returns true) we will only be at most 1 byte pass the end.
+                 //        Another unsafety operation here is dereferencing `elem`.
+                 //        However, `elem` was initially `1 * sizeof(T)` past the end and we decrement it by `1 * sizeof(T)` before accessing it.
+                 //        Plus, `block_r` was asserted to be less than `BLOCK` and `elem` will therefore at most be pointing to the beginning of the slice.
+                 unsafe {
+                     // Branchless comparison.
+                     elem = elem.offset(-1);
+                     *end_r = i as u8;
+                     end_r = end_r.offset(is_less(&*elem, pivot) as isize);
+                 }
+             }
+         }
+ 
+         // Number of out-of-order elements to swap between the left and right side.
+         let count = cmp::min(width(start_l, end_l), width(start_r, end_r));
+ 
+         if count > 0 {
+             macro_rules! left {
+                 () => {
+                     l.offset(*start_l as isize)
+                 };
+             }
+             macro_rules! right {
+                 () => {
+                     r.offset(-(*start_r as isize) - 1)
+                 };
+             }
+ 
+             // Instead of swapping one pair at the time, it is more efficient to perform a cyclic
+             // permutation. This is not strictly equivalent to swapping, but produces a similar
+             // result using fewer memory operations.
+             unsafe {
+                 let tmp = ptr::read(left!());
+                 ptr::copy_nonoverlapping(right!(), left!(), 1);
+ 
+                 for _ in 1..count {
+                     start_l = start_l.offset(1);
+                     ptr::copy_nonoverlapping(left!(), right!(), 1);
+                     start_r = start_r.offset(1);
+                     ptr::copy_nonoverlapping(right!(), left!(), 1);
+                 }
+ 
+                 ptr::copy_nonoverlapping(&tmp, right!(), 1);
+                 mem::forget(tmp);
+                 start_l = start_l.offset(1);
+                 start_r = start_r.offset(1);
+             }
+         }
+ 
+         if start_l == end_l {
+             // All out-of-order elements in the left block were moved. Move to the next block.
+             l = unsafe { l.offset(block_l as isize) };
+         }
+ 
+         if start_r == end_r {
+             // All out-of-order elements in the right block were moved. Move to the previous block.
+             r = unsafe { r.offset(-(block_r as isize)) };
+         }
+ 
+         if is_done {
+             break;
+         }
+     }
+ 
+     // All that remains now is at most one block (either the left or the right) with out-of-order
+     // elements that need to be moved. Such remaining elements can be simply shifted to the end
+     // within their block.
+ 
+     if start_l < end_l {
+         // The left block remains.
+         // Move its remaining out-of-order elements to the far right.
+         debug_assert_eq!(width(l, r), block_l);
+         while start_l < end_l {
+             unsafe {
+                 end_l = end_l.offset(-1);
+                 ptr::swap(l.offset(*end_l as isize), r.offset(-1));
+                 r = r.offset(-1);
+             }
+         }
+         width(v.as_mut_ptr(), r)
+     } else if start_r < end_r {
+         // The right block remains.
+         // Move its remaining out-of-order elements to the far left.
+         debug_assert_eq!(width(l, r), block_r);
+         while start_r < end_r {
+             unsafe {
+                 end_r = end_r.offset(-1);
+                 ptr::swap(l, r.offset(-(*end_r as isize) - 1));
+                 l = l.offset(1);
+             }
+         }
+         width(v.as_mut_ptr(), l)
+     } else {
+         // Nothing else to do, we're done.
+         width(v.as_mut_ptr(), l)
+     }
+ }
+ 
+ /// Partitions `v` into elements smaller than `v[pivot]`, followed by elements greater than or
+ /// equal to `v[pivot]`.
+ ///
+ /// Returns a tuple of:
+ ///
+ /// 1. Number of elements smaller than `v[pivot]`.
+ /// 2. True if `v` was already partitioned.
+ fn partition<T, F>(v: &mut [T], pivot: usize, is_less: &mut F) -> (usize, bool)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     let (mid, was_partitioned) = {
+         // Place the pivot at the beginning of slice.
+         v.swap(0, pivot);
+         let (pivot, v) = v.split_at_mut(1);
+         let pivot = &mut pivot[0];
+ 
+         // Read the pivot into a stack-allocated variable for efficiency. If a following comparison
+         // operation panics, the pivot will be automatically written back into the slice.
+         let mut tmp = mem::ManuallyDrop::new(unsafe { ptr::read(pivot) });
+         let _pivot_guard = CopyOnDrop { src: &mut *tmp, dest: pivot };
+         let pivot = &*tmp;
+ 
+         // Find the first pair of out-of-order elements.
+         let mut l = 0;
+         let mut r = v.len();
+ 
+         // SAFETY: The unsafety below involves indexing an array.
+         // For the first one: We already do the bounds checking here with `l < r`.
+         // For the second one: We initially have `l == 0` and `r == v.len()` and we checked that `l < r` at every indexing operation.
+         //                     From here we know that `r` must be at least `r == l` which was shown to be valid from the first one.
+         unsafe {
+             // Find the first element greater than or equal to the pivot.
+             while l < r && is_less(v.get_unchecked(l), pivot) {
+                 l += 1;
+             }
+ 
+             // Find the last element smaller that the pivot.
+             while l < r && !is_less(v.get_unchecked(r - 1), pivot) {
+                 r -= 1;
+             }
+         }
+ 
+         (l + partition_in_blocks(&mut v[l..r], pivot, is_less), l >= r)
+ 
+         // `_pivot_guard` goes out of scope and writes the pivot (which is a stack-allocated
+         // variable) back into the slice where it originally was. This step is critical in ensuring
+         // safety!
+     };
+ 
+     // Place the pivot between the two partitions.
+     v.swap(0, mid);
+ 
+     (mid, was_partitioned)
+ }
+ 
+ /// Partitions `v` into elements equal to `v[pivot]` followed by elements greater than `v[pivot]`.
+ ///
+ /// Returns the number of elements equal to the pivot. It is assumed that `v` does not contain
+ /// elements smaller than the pivot.
+ fn partition_equal<T, F>(v: &mut [T], pivot: usize, is_less: &mut F) -> usize
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // Place the pivot at the beginning of slice.
+     v.swap(0, pivot);
+     let (pivot, v) = v.split_at_mut(1);
+     let pivot = &mut pivot[0];
+ 
+     // Read the pivot into a stack-allocated variable for efficiency. If a following comparison
+     // operation panics, the pivot will be automatically written back into the slice.
+     // SAFETY: The pointer here is valid because it is obtained from a reference to a slice.
+     let mut tmp = mem::ManuallyDrop::new(unsafe { ptr::read(pivot) });
+     let _pivot_guard = CopyOnDrop { src: &mut *tmp, dest: pivot };
+     let pivot = &*tmp;
+ 
+     // Now partition the slice.
+     let mut l = 0;
+     let mut r = v.len();
+     loop {
+         // SAFETY: The unsafety below involves indexing an array.
+         // For the first one: We already do the bounds checking here with `l < r`.
+         // For the second one: We initially have `l == 0` and `r == v.len()` and we checked that `l < r` at every indexing operation.
+         //                     From here we know that `r` must be at least `r == l` which was shown to be valid from the first one.
+         unsafe {
+             // Find the first element greater than the pivot.
+             while l < r && !is_less(pivot, v.get_unchecked(l)) {
+                 l += 1;
+             }
+ 
+             // Find the last element equal to the pivot.
+             while l < r && is_less(pivot, v.get_unchecked(r - 1)) {
+                 r -= 1;
+             }
+ 
+             // Are we done?
+             if l >= r {
+                 break;
+             }
+ 
+             // Swap the found pair of out-of-order elements.
+             r -= 1;
+             ptr::swap(v.get_unchecked_mut(l), v.get_unchecked_mut(r));
+             l += 1;
+         }
+     }
+ 
+     // We found `l` elements equal to the pivot. Add 1 to account for the pivot itself.
+     l + 1
+ 
+     // `_pivot_guard` goes out of scope and writes the pivot (which is a stack-allocated variable)
+     // back into the slice where it originally was. This step is critical in ensuring safety!
+ }
+ 
+ /// Scatters some elements around in an attempt to break patterns that might cause imbalanced
+ /// partitions in quicksort.
+ #[cold]
+ fn break_patterns<T>(v: &mut [T]) {
+     let len = v.len();
+     if len >= 8 {
+         // Pseudorandom number generator from the "Xorshift RNGs" paper by George Marsaglia.
+         let mut random = len as u32;
+         let mut gen_u32 = || {
+             random ^= random << 13;
+             random ^= random >> 17;
+             random ^= random << 5;
+             random
+         };
+         let mut gen_usize = || {
+             if usize::BITS <= 32 {
+                 gen_u32() as usize
+             } else {
+                 (((gen_u32() as u64) << 32) | (gen_u32() as u64)) as usize
+             }
+         };
+ 
+         // Take random numbers modulo this number.
+         // The number fits into `usize` because `len` is not greater than `isize::MAX`.
+         let modulus = len.next_power_of_two();
+ 
+         // Some pivot candidates will be in the nearby of this index. Let's randomize them.
+         let pos = len / 4 * 2;
+ 
+         for i in 0..3 {
+             // Generate a random number modulo `len`. However, in order to avoid costly operations
+             // we first take it modulo a power of two, and then decrease by `len` until it fits
+             // into the range `[0, len - 1]`.
+             let mut other = gen_usize() & (modulus - 1);
+ 
+             // `other` is guaranteed to be less than `2 * len`.
+             if other >= len {
+                 other -= len;
+             }
+ 
+             v.swap(pos - 1 + i, other);
+         }
+     }
+ }
+ 
+ /// Chooses a pivot in `v` and returns the index and `true` if the slice is likely already sorted.
+ ///
+ /// Elements in `v` might be reordered in the process.
+ fn choose_pivot<T, F>(v: &mut [T], is_less: &mut F) -> (usize, bool)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // Minimum length to choose the median-of-medians method.
+     // Shorter slices use the simple median-of-three method.
+     const SHORTEST_MEDIAN_OF_MEDIANS: usize = 50;
+     // Maximum number of swaps that can be performed in this function.
+     const MAX_SWAPS: usize = 4 * 3;
+ 
+     let len = v.len();
+ 
+     // Three indices near which we are going to choose a pivot.
+     let mut a = len / 4 * 1;
+     let mut b = len / 4 * 2;
+     let mut c = len / 4 * 3;
+ 
+     // Counts the total number of swaps we are about to perform while sorting indices.
+     let mut swaps = 0;
+ 
+     if len >= 8 {
+         // Swaps indices so that `v[a] <= v[b]`.
+         let mut sort2 = |a: &mut usize, b: &mut usize| unsafe {
+             if is_less(v.get_unchecked(*b), v.get_unchecked(*a)) {
+                 ptr::swap(a, b);
+                 swaps += 1;
+             }
+         };
+ 
+         // Swaps indices so that `v[a] <= v[b] <= v[c]`.
+         let mut sort3 = |a: &mut usize, b: &mut usize, c: &mut usize| {
+             sort2(a, b);
+             sort2(b, c);
+             sort2(a, b);
+         };
+ 
+         if len >= SHORTEST_MEDIAN_OF_MEDIANS {
+             // Finds the median of `v[a - 1], v[a], v[a + 1]` and stores the index into `a`.
+             let mut sort_adjacent = |a: &mut usize| {
+                 let tmp = *a;
+                 sort3(&mut (tmp - 1), a, &mut (tmp + 1));
+             };
+ 
+             // Find medians in the neighborhoods of `a`, `b`, and `c`.
+             sort_adjacent(&mut a);
+             sort_adjacent(&mut b);
+             sort_adjacent(&mut c);
+         }
+ 
+         // Find the median among `a`, `b`, and `c`.
+         sort3(&mut a, &mut b, &mut c);
+     }
+ 
+     if swaps < MAX_SWAPS {
+         (b, swaps == 0)
+     } else {
+         // The maximum number of swaps was performed. Chances are the slice is descending or mostly
+         // descending, so reversing will probably help sort it faster.
+         v.reverse();
+         (len - 1 - b, true)
+     }
+ }
+ 
+ /// Sorts `v` recursively.
+ ///
+ /// If the slice had a predecessor in the original array, it is specified as `pred`.
+ ///
+ /// `limit` is the number of allowed imbalanced partitions before switching to `heapsort`. If zero,
+ /// this function will immediately switch to heapsort.
+ fn recurse<'a, T, F>(mut v: &'a mut [T], is_less: &mut F, mut pred: Option<&'a T>, mut limit: u32)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // Slices of up to this length get sorted using insertion sort.
+     const MAX_INSERTION: usize = 20;
+ 
+     // True if the last partitioning was reasonably balanced.
+     let mut was_balanced = true;
+     // True if the last partitioning didn't shuffle elements (the slice was already partitioned).
+     let mut was_partitioned = true;
+ 
+     loop {
+         let len = v.len();
+ 
+         // Very short slices get sorted using insertion sort.
+         if len <= MAX_INSERTION {
+             insertion_sort(v, is_less);
+             return;
+         }
+ 
+         // If too many bad pivot choices were made, simply fall back to heapsort in order to
+         // guarantee `O(n * log(n))` worst-case.
+         if limit == 0 {
+             heapsort(v, is_less);
+             return;
+         }
+ 
+         // If the last partitioning was imbalanced, try breaking patterns in the slice by shuffling
+         // some elements around. Hopefully we'll choose a better pivot this time.
+         if !was_balanced {
+             break_patterns(v);
+             limit -= 1;
+         }
+ 
+         // Choose a pivot and try guessing whether the slice is already sorted.
+         let (pivot, likely_sorted) = choose_pivot(v, is_less);
+ 
+         // If the last partitioning was decently balanced and didn't shuffle elements, and if pivot
+         // selection predicts the slice is likely already sorted...
+         if was_balanced && was_partitioned && likely_sorted {
+             // Try identifying several out-of-order elements and shifting them to correct
+             // positions. If the slice ends up being completely sorted, we're done.
+             if partial_insertion_sort(v, is_less) {
+                 return;
+             }
+         }
+ 
+         // If the chosen pivot is equal to the predecessor, then it's the smallest element in the
+         // slice. Partition the slice into elements equal to and elements greater than the pivot.
+         // This case is usually hit when the slice contains many duplicate elements.
+         if let Some(p) = pred {
+             if !is_less(p, &v[pivot]) {
+                 let mid = partition_equal(v, pivot, is_less);
+ 
+                 // Continue sorting elements greater than the pivot.
+                 v = &mut { v }[mid..];
+                 continue;
+             }
+         }
+ 
+         // Partition the slice.
+         let (mid, was_p) = partition(v, pivot, is_less);
+         was_balanced = cmp::min(mid, len - mid) >= len / 8;
+         was_partitioned = was_p;
+ 
+         // Split the slice into `left`, `pivot`, and `right`.
+         let (left, right) = { v }.split_at_mut(mid);
+         let (pivot, right) = right.split_at_mut(1);
+         let pivot = &pivot[0];
+ 
+         // Recurse into the shorter side only in order to minimize the total number of recursive
+         // calls and consume less stack space. Then just continue with the longer side (this is
+         // akin to tail recursion).
+         if left.len() < right.len() {
+             recurse(left, is_less, pred, limit);
+             v = right;
+             pred = Some(pivot);
+         } else {
+             recurse(right, is_less, Some(pivot), limit);
+             v = left;
+         }
+     }
+ }
+ 
+ /// Sorts `v` using pattern-defeating quicksort, which is *O*(*n* \* log(*n*)) worst-case.
+ pub fn quicksort<T, F>(v: &mut [T], mut is_less: F)
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     // Sorting has no meaningful behavior on zero-sized types.
+     if mem::size_of::<T>() == 0 {
+         return;
+     }
+ 
+     // Limit the number of imbalanced partitions to `floor(log2(len)) + 1`.
+     let limit = usize::BITS - v.len().leading_zeros();
+ 
+     recurse(v, &mut is_less, None, limit);
+ }
+ 
+ fn partition_at_index_loop<'a, T, F>(
+     mut v: &'a mut [T],
+     mut index: usize,
+     is_less: &mut F,
+     mut pred: Option<&'a T>,
+ ) where
+     F: FnMut(&T, &T) -> bool,
+ {
+     loop {
+         // For slices of up to this length it's probably faster to simply sort them.
+         const MAX_INSERTION: usize = 10;
+         if v.len() <= MAX_INSERTION {
+             insertion_sort(v, is_less);
+             return;
+         }
+ 
+         // Choose a pivot
+         let (pivot, _) = choose_pivot(v, is_less);
+ 
+         // If the chosen pivot is equal to the predecessor, then it's the smallest element in the
+         // slice. Partition the slice into elements equal to and elements greater than the pivot.
+         // This case is usually hit when the slice contains many duplicate elements.
+         if let Some(p) = pred {
+             if !is_less(p, &v[pivot]) {
+                 let mid = partition_equal(v, pivot, is_less);
+ 
+                 // If we've passed our index, then we're good.
+                 if mid > index {
+                     return;
+                 }
+ 
+                 // Otherwise, continue sorting elements greater than the pivot.
+                 v = &mut v[mid..];
+                 index = index - mid;
+                 pred = None;
+                 continue;
+             }
+         }
+ 
+         let (mid, _) = partition(v, pivot, is_less);
+ 
+         // Split the slice into `left`, `pivot`, and `right`.
+         let (left, right) = { v }.split_at_mut(mid);
+         let (pivot, right) = right.split_at_mut(1);
+         let pivot = &pivot[0];
+ 
+         if mid < index {
+             v = right;
+             index = index - mid - 1;
+             pred = Some(pivot);
+         } else if mid > index {
+             v = left;
+         } else {
+             // If mid == index, then we're done, since partition() guaranteed that all elements
+             // after mid are greater than or equal to mid.
+             return;
+         }
+     }
+ }
+ 
+ pub fn partition_at_index<T, F>(
+     v: &mut [T],
+     index: usize,
+     mut is_less: F,
+ ) -> (&mut [T], &mut T, &mut [T])
+ where
+     F: FnMut(&T, &T) -> bool,
+ {
+     use cmp::Ordering::Greater;
+     use cmp::Ordering::Less;
+ 
+     if index >= v.len() {
+         panic!("partition_at_index index {} greater than length of slice {}", index, v.len());
+     }
+ 
+     if mem::size_of::<T>() == 0 {
+         // Sorting has no meaningful behavior on zero-sized types. Do nothing.
+     } else if index == v.len() - 1 {
+         // Find max element and place it in the last position of the array. We're free to use
+         // `unwrap()` here because we know v must not be empty.
+         let (max_index, _) = v
+             .iter()
+             .enumerate()
+             .max_by(|&(_, x), &(_, y)| if is_less(x, y) { Less } else { Greater })
+             .unwrap();
+         v.swap(max_index, index);
+     } else if index == 0 {
+         // Find min element and place it in the first position of the array. We're free to use
+         // `unwrap()` here because we know v must not be empty.
+         let (min_index, _) = v
+             .iter()
+             .enumerate()
+             .min_by(|&(_, x), &(_, y)| if is_less(x, y) { Less } else { Greater })
+             .unwrap();
+         v.swap(min_index, index);
+     } else {
+         partition_at_index_loop(v, index, &mut is_less, None);
+     }
+ 
+     let (left, right) = v.split_at_mut(index);
+     let (pivot, right) = right.split_at_mut(1);
+     let pivot = &mut pivot[0];
+     (left, pivot, right)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/converts.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/converts.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/converts.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/converts.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,193 ----
+ //! Ways to create a `str` from bytes slice.
+ 
+ use crate::mem;
+ 
+ use super::validations::run_utf8_validation;
+ use super::Utf8Error;
+ 
+ /// Converts a slice of bytes to a string slice.
+ ///
+ /// A string slice ([`&str`]) is made of bytes ([`u8`]), and a byte slice
+ /// ([`&[u8]`][byteslice]) is made of bytes, so this function converts between
+ /// the two. Not all byte slices are valid string slices, however: [`&str`] requires
+ /// that it is valid UTF-8. `from_utf8()` checks to ensure that the bytes are valid
+ /// UTF-8, and then does the conversion.
+ ///
+ /// [`&str`]: str
+ /// [byteslice]: ../../std/primitive.slice.html
+ ///
+ /// If you are sure that the byte slice is valid UTF-8, and you don't want to
+ /// incur the overhead of the validity check, there is an unsafe version of
+ /// this function, [`from_utf8_unchecked`], which has the same
+ /// behavior but skips the check.
+ ///
+ /// If you need a `String` instead of a `&str`, consider
+ /// [`String::from_utf8`][string].
+ ///
+ /// [string]: ../../std/string/struct.String.html#method.from_utf8
+ ///
+ /// Because you can stack-allocate a `[u8; N]`, and you can take a
+ /// [`&[u8]`][byteslice] of it, this function is one way to have a
+ /// stack-allocated string. There is an example of this in the
+ /// examples section below.
+ ///
+ /// [byteslice]: ../../std/primitive.slice.html
+ ///
+ /// # Errors
+ ///
+ /// Returns `Err` if the slice is not UTF-8 with a description as to why the
+ /// provided slice is not UTF-8.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// // some bytes, in a vector
+ /// let sparkle_heart = vec![240, 159, 146, 150];
+ ///
+ /// // We know these bytes are valid, so just use `unwrap()`.
+ /// let sparkle_heart = str::from_utf8(&sparkle_heart).unwrap();
+ ///
+ /// assert_eq!("💖", sparkle_heart);
+ /// ```
+ ///
+ /// Incorrect bytes:
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// // some invalid bytes, in a vector
+ /// let sparkle_heart = vec![0, 159, 146, 150];
+ ///
+ /// assert!(str::from_utf8(&sparkle_heart).is_err());
+ /// ```
+ ///
+ /// See the docs for [`Utf8Error`] for more details on the kinds of
+ /// errors that can be returned.
+ ///
+ /// A "stack allocated string":
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// // some bytes, in a stack-allocated array
+ /// let sparkle_heart = [240, 159, 146, 150];
+ ///
+ /// // We know these bytes are valid, so just use `unwrap()`.
+ /// let sparkle_heart = str::from_utf8(&sparkle_heart).unwrap();
+ ///
+ /// assert_eq!("💖", sparkle_heart);
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn from_utf8(v: &[u8]) -> Result<&str, Utf8Error> {
+     run_utf8_validation(v)?;
+     // SAFETY: Just ran validation.
+     Ok(unsafe { from_utf8_unchecked(v) })
+ }
+ 
+ /// Converts a mutable slice of bytes to a mutable string slice.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// // "Hello, Rust!" as a mutable vector
+ /// let mut hellorust = vec![72, 101, 108, 108, 111, 44, 32, 82, 117, 115, 116, 33];
+ ///
+ /// // As we know these bytes are valid, we can use `unwrap()`
+ /// let outstr = str::from_utf8_mut(&mut hellorust).unwrap();
+ ///
+ /// assert_eq!("Hello, Rust!", outstr);
+ /// ```
+ ///
+ /// Incorrect bytes:
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// // Some invalid bytes in a mutable vector
+ /// let mut invalid = vec![128, 223];
+ ///
+ /// assert!(str::from_utf8_mut(&mut invalid).is_err());
+ /// ```
+ /// See the docs for [`Utf8Error`] for more details on the kinds of
+ /// errors that can be returned.
+ #[stable(feature = "str_mut_extras", since = "1.20.0")]
+ pub fn from_utf8_mut(v: &mut [u8]) -> Result<&mut str, Utf8Error> {
+     run_utf8_validation(v)?;
+     // SAFETY: Just ran validation.
+     Ok(unsafe { from_utf8_unchecked_mut(v) })
+ }
+ 
+ /// Converts a slice of bytes to a string slice without checking
+ /// that the string contains valid UTF-8.
+ ///
+ /// See the safe version, [`from_utf8`], for more information.
+ ///
+ /// # Safety
+ ///
+ /// This function is unsafe because it does not check that the bytes passed to
+ /// it are valid UTF-8. If this constraint is violated, undefined behavior
+ /// results, as the rest of Rust assumes that [`&str`]s are valid UTF-8.
+ ///
+ /// [`&str`]: str
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// // some bytes, in a vector
+ /// let sparkle_heart = vec![240, 159, 146, 150];
+ ///
+ /// let sparkle_heart = unsafe {
+ ///     str::from_utf8_unchecked(&sparkle_heart)
+ /// };
+ ///
+ /// assert_eq!("💖", sparkle_heart);
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_const_unstable(feature = "const_str_from_utf8_unchecked", issue = "75196")]
+ #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_transmute))]
+ #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_transmute))]
+ pub const unsafe fn from_utf8_unchecked(v: &[u8]) -> &str {
+     // SAFETY: the caller must guarantee that the bytes `v` are valid UTF-8.
+     // Also relies on `&str` and `&[u8]` having the same layout.
+     unsafe { mem::transmute(v) }
+ }
+ 
+ /// Converts a slice of bytes to a string slice without checking
+ /// that the string contains valid UTF-8; mutable version.
+ ///
+ /// See the immutable version, [`from_utf8_unchecked()`] for more information.
+ ///
+ /// # Examples
+ ///
+ /// Basic usage:
+ ///
+ /// ```
+ /// use std::str;
+ ///
+ /// let mut heart = vec![240, 159, 146, 150];
+ /// let heart = unsafe { str::from_utf8_unchecked_mut(&mut heart) };
+ ///
+ /// assert_eq!("💖", heart);
+ /// ```
+ #[inline]
+ #[stable(feature = "str_mut_extras", since = "1.20.0")]
+ pub unsafe fn from_utf8_unchecked_mut(v: &mut [u8]) -> &mut str {
+     // SAFETY: the caller must guarantee that the bytes `v`
+     // are valid UTF-8, thus the cast to `*mut str` is safe.
+     // Also, the pointer dereference is safe because that pointer
+     // comes from a reference which is guaranteed to be valid for writes.
+     unsafe { &mut *(v as *mut [u8] as *mut str) }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/error.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/error.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/error.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/error.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,131 ----
+ //! Defines utf8 error type.
+ 
+ use crate::fmt;
+ 
+ /// Errors which can occur when attempting to interpret a sequence of [`u8`]
+ /// as a string.
+ ///
+ /// As such, the `from_utf8` family of functions and methods for both [`String`]s
+ /// and [`&str`]s make use of this error, for example.
+ ///
+ /// [`String`]: ../../std/string/struct.String.html#method.from_utf8
+ /// [`&str`]: super::from_utf8
+ ///
+ /// # Examples
+ ///
+ /// This error type’s methods can be used to create functionality
+ /// similar to `String::from_utf8_lossy` without allocating heap memory:
+ ///
+ /// ```
+ /// fn from_utf8_lossy<F>(mut input: &[u8], mut push: F) where F: FnMut(&str) {
+ ///     loop {
+ ///         match std::str::from_utf8(input) {
+ ///             Ok(valid) => {
+ ///                 push(valid);
+ ///                 break
+ ///             }
+ ///             Err(error) => {
+ ///                 let (valid, after_valid) = input.split_at(error.valid_up_to());
+ ///                 unsafe {
+ ///                     push(std::str::from_utf8_unchecked(valid))
+ ///                 }
+ ///                 push("\u{FFFD}");
+ ///
+ ///                 if let Some(invalid_sequence_length) = error.error_len() {
+ ///                     input = &after_valid[invalid_sequence_length..]
+ ///                 } else {
+ ///                     break
+ ///                 }
+ ///             }
+ ///         }
+ ///     }
+ /// }
+ /// ```
+ #[derive(Copy, Eq, PartialEq, Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Utf8Error {
+     pub(super) valid_up_to: usize,
+     pub(super) error_len: Option<u8>,
+ }
+ 
+ impl Utf8Error {
+     /// Returns the index in the given string up to which valid UTF-8 was
+     /// verified.
+     ///
+     /// It is the maximum index such that `from_utf8(&input[..index])`
+     /// would return `Ok(_)`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::str;
+     ///
+     /// // some invalid bytes, in a vector
+     /// let sparkle_heart = vec![0, 159, 146, 150];
+     ///
+     /// // std::str::from_utf8 returns a Utf8Error
+     /// let error = str::from_utf8(&sparkle_heart).unwrap_err();
+     ///
+     /// // the second byte is invalid here
+     /// assert_eq!(1, error.valid_up_to());
+     /// ```
+     #[stable(feature = "utf8_error", since = "1.5.0")]
+     #[inline]
+     pub fn valid_up_to(&self) -> usize {
+         self.valid_up_to
+     }
+ 
+     /// Provides more information about the failure:
+     ///
+     /// * `None`: the end of the input was reached unexpectedly.
+     ///   `self.valid_up_to()` is 1 to 3 bytes from the end of the input.
+     ///   If a byte stream (such as a file or a network socket) is being decoded incrementally,
+     ///   this could be a valid `char` whose UTF-8 byte sequence is spanning multiple chunks.
+     ///
+     /// * `Some(len)`: an unexpected byte was encountered.
+     ///   The length provided is that of the invalid byte sequence
+     ///   that starts at the index given by `valid_up_to()`.
+     ///   Decoding should resume after that sequence
+     ///   (after inserting a [`U+FFFD REPLACEMENT CHARACTER`][U+FFFD]) in case of
+     ///   lossy decoding.
+     ///
+     /// [U+FFFD]: ../../std/char/constant.REPLACEMENT_CHARACTER.html
+     #[stable(feature = "utf8_error_error_len", since = "1.20.0")]
+     #[inline]
+     pub fn error_len(&self) -> Option<usize> {
+         self.error_len.map(|len| len as usize)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Display for Utf8Error {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         if let Some(error_len) = self.error_len {
+             write!(
+                 f,
+                 "invalid utf-8 sequence of {} bytes from index {}",
+                 error_len, self.valid_up_to
+             )
+         } else {
+             write!(f, "incomplete utf-8 byte sequence from index {}", self.valid_up_to)
+         }
+     }
+ }
+ 
+ /// An error returned when parsing a `bool` using [`from_str`] fails
+ ///
+ /// [`from_str`]: super::FromStr::from_str
+ #[derive(Debug, Clone, PartialEq, Eq)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct ParseBoolError {
+     pub(super) _priv: (),
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl fmt::Display for ParseBoolError {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         "provided string was not `true` or `false`".fmt(f)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/iter.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/iter.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/iter.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/iter.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1420 ----
+ //! Iterators for `str` methods.
+ 
+ use crate::char;
+ use crate::fmt::{self, Write};
+ use crate::iter::TrustedRandomAccess;
+ use crate::iter::{Chain, FlatMap, Flatten};
+ use crate::iter::{Copied, Filter, FusedIterator, Map, TrustedLen};
+ use crate::ops::Try;
+ use crate::option;
+ use crate::slice::{self, Split as SliceSplit};
+ 
+ use super::from_utf8_unchecked;
+ use super::pattern::Pattern;
+ use super::pattern::{DoubleEndedSearcher, ReverseSearcher, Searcher};
+ use super::validations::{next_code_point, next_code_point_reverse, utf8_is_cont_byte};
+ use super::LinesAnyMap;
+ use super::{BytesIsNotEmpty, UnsafeBytesToStr};
+ use super::{CharEscapeDebugContinue, CharEscapeDefault, CharEscapeUnicode};
+ use super::{IsAsciiWhitespace, IsNotEmpty, IsWhitespace};
+ 
+ /// An iterator over the [`char`]s of a string slice.
+ ///
+ ///
+ /// This struct is created by the [`chars`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`char`]: prim@char
+ /// [`chars`]: str::chars
+ #[derive(Clone)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct Chars<'a> {
+     pub(super) iter: slice::Iter<'a, u8>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a> Iterator for Chars<'a> {
+     type Item = char;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<char> {
+         next_code_point(&mut self.iter).map(|ch| {
+             // SAFETY: `str` invariant says `ch` is a valid Unicode Scalar Value.
+             unsafe { char::from_u32_unchecked(ch) }
+         })
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         // length in `char` is equal to the number of non-continuation bytes
+         let bytes_len = self.iter.len();
+         let mut cont_bytes = 0;
+         for &byte in self.iter {
+             cont_bytes += utf8_is_cont_byte(byte) as usize;
+         }
+         bytes_len - cont_bytes
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let len = self.iter.len();
+         // `(len + 3)` can't overflow, because we know that the `slice::Iter`
+         // belongs to a slice in memory which has a maximum length of
+         // `isize::MAX` (that's well below `usize::MAX`).
+         ((len + 3) / 4, Some(len))
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<char> {
+         // No need to go through the entire string.
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "chars_debug_impl", since = "1.38.0")]
+ impl fmt::Debug for Chars<'_> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         write!(f, "Chars(")?;
+         f.debug_list().entries(self.clone()).finish()?;
+         write!(f, ")")?;
+         Ok(())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a> DoubleEndedIterator for Chars<'a> {
+     #[inline]
+     fn next_back(&mut self) -> Option<char> {
+         next_code_point_reverse(&mut self.iter).map(|ch| {
+             // SAFETY: `str` invariant says `ch` is a valid Unicode Scalar Value.
+             unsafe { char::from_u32_unchecked(ch) }
+         })
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for Chars<'_> {}
+ 
+ impl<'a> Chars<'a> {
+     /// Views the underlying data as a subslice of the original data.
+     ///
+     /// This has the same lifetime as the original slice, and so the
+     /// iterator can continue to be used while this exists.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut chars = "abc".chars();
+     ///
+     /// assert_eq!(chars.as_str(), "abc");
+     /// chars.next();
+     /// assert_eq!(chars.as_str(), "bc");
+     /// chars.next();
+     /// chars.next();
+     /// assert_eq!(chars.as_str(), "");
+     /// ```
+     #[stable(feature = "iter_to_slice", since = "1.4.0")]
+     #[inline]
+     pub fn as_str(&self) -> &'a str {
+         // SAFETY: `Chars` is only made from a str, which guarantees the iter is valid UTF-8.
+         unsafe { from_utf8_unchecked(self.iter.as_slice()) }
+     }
+ }
+ 
+ /// An iterator over the [`char`]s of a string slice, and their positions.
+ ///
+ /// This struct is created by the [`char_indices`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`char`]: prim@char
+ /// [`char_indices`]: str::char_indices
+ #[derive(Clone, Debug)]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub struct CharIndices<'a> {
+     pub(super) front_offset: usize,
+     pub(super) iter: Chars<'a>,
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a> Iterator for CharIndices<'a> {
+     type Item = (usize, char);
+ 
+     #[inline]
+     fn next(&mut self) -> Option<(usize, char)> {
+         let pre_len = self.iter.iter.len();
+         match self.iter.next() {
+             None => None,
+             Some(ch) => {
+                 let index = self.front_offset;
+                 let len = self.iter.iter.len();
+                 self.front_offset += pre_len - len;
+                 Some((index, ch))
+             }
+         }
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.iter.count()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.iter.size_hint()
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<(usize, char)> {
+         // No need to go through the entire string.
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a> DoubleEndedIterator for CharIndices<'a> {
+     #[inline]
+     fn next_back(&mut self) -> Option<(usize, char)> {
+         self.iter.next_back().map(|ch| {
+             let index = self.front_offset + self.iter.iter.len();
+             (index, ch)
+         })
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for CharIndices<'_> {}
+ 
+ impl<'a> CharIndices<'a> {
+     /// Views the underlying data as a subslice of the original data.
+     ///
+     /// This has the same lifetime as the original slice, and so the
+     /// iterator can continue to be used while this exists.
+     #[stable(feature = "iter_to_slice", since = "1.4.0")]
+     #[inline]
+     pub fn as_str(&self) -> &'a str {
+         self.iter.as_str()
+     }
+ }
+ 
+ /// An iterator over the bytes of a string slice.
+ ///
+ /// This struct is created by the [`bytes`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`bytes`]: str::bytes
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone, Debug)]
+ pub struct Bytes<'a>(pub(super) Copied<slice::Iter<'a, u8>>);
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Iterator for Bytes<'_> {
+     type Item = u8;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<u8> {
+         self.0.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.0.size_hint()
+     }
+ 
+     #[inline]
+     fn count(self) -> usize {
+         self.0.count()
+     }
+ 
+     #[inline]
+     fn last(self) -> Option<Self::Item> {
+         self.0.last()
+     }
+ 
+     #[inline]
+     fn nth(&mut self, n: usize) -> Option<Self::Item> {
+         self.0.nth(n)
+     }
+ 
+     #[inline]
+     fn all<F>(&mut self, f: F) -> bool
+     where
+         F: FnMut(Self::Item) -> bool,
+     {
+         self.0.all(f)
+     }
+ 
+     #[inline]
+     fn any<F>(&mut self, f: F) -> bool
+     where
+         F: FnMut(Self::Item) -> bool,
+     {
+         self.0.any(f)
+     }
+ 
+     #[inline]
+     fn find<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         self.0.find(predicate)
+     }
+ 
+     #[inline]
+     fn position<P>(&mut self, predicate: P) -> Option<usize>
+     where
+         P: FnMut(Self::Item) -> bool,
+     {
+         self.0.position(predicate)
+     }
+ 
+     #[inline]
+     fn rposition<P>(&mut self, predicate: P) -> Option<usize>
+     where
+         P: FnMut(Self::Item) -> bool,
+     {
+         self.0.rposition(predicate)
+     }
+ 
+     #[inline]
+     unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> u8 {
+         // SAFETY: the caller must uphold the safety contract
+         // for `Iterator::__iterator_get_unchecked`.
+         unsafe { self.0.__iterator_get_unchecked(idx) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl DoubleEndedIterator for Bytes<'_> {
+     #[inline]
+     fn next_back(&mut self) -> Option<u8> {
+         self.0.next_back()
+     }
+ 
+     #[inline]
+     fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+         self.0.nth_back(n)
+     }
+ 
+     #[inline]
+     fn rfind<P>(&mut self, predicate: P) -> Option<Self::Item>
+     where
+         P: FnMut(&Self::Item) -> bool,
+     {
+         self.0.rfind(predicate)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl ExactSizeIterator for Bytes<'_> {
+     #[inline]
+     fn len(&self) -> usize {
+         self.0.len()
+     }
+ 
+     #[inline]
+     fn is_empty(&self) -> bool {
+         self.0.is_empty()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for Bytes<'_> {}
+ 
+ #[unstable(feature = "trusted_len", issue = "37572")]
+ unsafe impl TrustedLen for Bytes<'_> {}
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "trusted_random_access", issue = "none")]
+ unsafe impl TrustedRandomAccess for Bytes<'_> {
+     #[inline]
+     fn may_have_side_effect() -> bool {
+         false
+     }
+ }
+ 
+ /// This macro generates a Clone impl for string pattern API
+ /// wrapper types of the form X<'a, P>
+ macro_rules! derive_pattern_clone {
+     (clone $t:ident with |$s:ident| $e:expr) => {
+         impl<'a, P> Clone for $t<'a, P>
+         where
+             P: Pattern<'a, Searcher: Clone>,
+         {
+             fn clone(&self) -> Self {
+                 let $s = self;
+                 $e
+             }
+         }
+     };
+ }
+ 
+ /// This macro generates two public iterator structs
+ /// wrapping a private internal one that makes use of the `Pattern` API.
+ ///
+ /// For all patterns `P: Pattern<'a>` the following items will be
+ /// generated (generics omitted):
+ ///
+ /// struct $forward_iterator($internal_iterator);
+ /// struct $reverse_iterator($internal_iterator);
+ ///
+ /// impl Iterator for $forward_iterator
+ /// { /* internal ends up calling Searcher::next_match() */ }
+ ///
+ /// impl DoubleEndedIterator for $forward_iterator
+ ///       where P::Searcher: DoubleEndedSearcher
+ /// { /* internal ends up calling Searcher::next_match_back() */ }
+ ///
+ /// impl Iterator for $reverse_iterator
+ ///       where P::Searcher: ReverseSearcher
+ /// { /* internal ends up calling Searcher::next_match_back() */ }
+ ///
+ /// impl DoubleEndedIterator for $reverse_iterator
+ ///       where P::Searcher: DoubleEndedSearcher
+ /// { /* internal ends up calling Searcher::next_match() */ }
+ ///
+ /// The internal one is defined outside the macro, and has almost the same
+ /// semantic as a DoubleEndedIterator by delegating to `pattern::Searcher` and
+ /// `pattern::ReverseSearcher` for both forward and reverse iteration.
+ ///
+ /// "Almost", because a `Searcher` and a `ReverseSearcher` for a given
+ /// `Pattern` might not return the same elements, so actually implementing
+ /// `DoubleEndedIterator` for it would be incorrect.
+ /// (See the docs in `str::pattern` for more details)
+ ///
+ /// However, the internal struct still represents a single ended iterator from
+ /// either end, and depending on pattern is also a valid double ended iterator,
+ /// so the two wrapper structs implement `Iterator`
+ /// and `DoubleEndedIterator` depending on the concrete pattern type, leading
+ /// to the complex impls seen above.
+ macro_rules! generate_pattern_iterators {
+     {
+         // Forward iterator
+         forward:
+             $(#[$forward_iterator_attribute:meta])*
+             struct $forward_iterator:ident;
+ 
+         // Reverse iterator
+         reverse:
+             $(#[$reverse_iterator_attribute:meta])*
+             struct $reverse_iterator:ident;
+ 
+         // Stability of all generated items
+         stability:
+             $(#[$common_stability_attribute:meta])*
+ 
+         // Internal almost-iterator that is being delegated to
+         internal:
+             $internal_iterator:ident yielding ($iterty:ty);
+ 
+         // Kind of delegation - either single ended or double ended
+         delegate $($t:tt)*
+     } => {
+         $(#[$forward_iterator_attribute])*
+         $(#[$common_stability_attribute])*
+         pub struct $forward_iterator<'a, P: Pattern<'a>>(pub(super) $internal_iterator<'a, P>);
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P> fmt::Debug for $forward_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: fmt::Debug>,
+         {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 f.debug_tuple(stringify!($forward_iterator))
+                     .field(&self.0)
+                     .finish()
+             }
+         }
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P: Pattern<'a>> Iterator for $forward_iterator<'a, P> {
+             type Item = $iterty;
+ 
+             #[inline]
+             fn next(&mut self) -> Option<$iterty> {
+                 self.0.next()
+             }
+         }
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P> Clone for $forward_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: Clone>,
+         {
+             fn clone(&self) -> Self {
+                 $forward_iterator(self.0.clone())
+             }
+         }
+ 
+         $(#[$reverse_iterator_attribute])*
+         $(#[$common_stability_attribute])*
+         pub struct $reverse_iterator<'a, P: Pattern<'a>>(pub(super) $internal_iterator<'a, P>);
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P> fmt::Debug for $reverse_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: fmt::Debug>,
+         {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 f.debug_tuple(stringify!($reverse_iterator))
+                     .field(&self.0)
+                     .finish()
+             }
+         }
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P> Iterator for $reverse_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+         {
+             type Item = $iterty;
+ 
+             #[inline]
+             fn next(&mut self) -> Option<$iterty> {
+                 self.0.next_back()
+             }
+         }
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P> Clone for $reverse_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: Clone>,
+         {
+             fn clone(&self) -> Self {
+                 $reverse_iterator(self.0.clone())
+             }
+         }
+ 
+         #[stable(feature = "fused", since = "1.26.0")]
+         impl<'a, P: Pattern<'a>> FusedIterator for $forward_iterator<'a, P> {}
+ 
+         #[stable(feature = "fused", since = "1.26.0")]
+         impl<'a, P> FusedIterator for $reverse_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+         {}
+ 
+         generate_pattern_iterators!($($t)* with $(#[$common_stability_attribute])*,
+                                                 $forward_iterator,
+                                                 $reverse_iterator, $iterty);
+     };
+     {
+         double ended; with $(#[$common_stability_attribute:meta])*,
+                            $forward_iterator:ident,
+                            $reverse_iterator:ident, $iterty:ty
+     } => {
+         $(#[$common_stability_attribute])*
+         impl<'a, P> DoubleEndedIterator for $forward_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: DoubleEndedSearcher<'a>>,
+         {
+             #[inline]
+             fn next_back(&mut self) -> Option<$iterty> {
+                 self.0.next_back()
+             }
+         }
+ 
+         $(#[$common_stability_attribute])*
+         impl<'a, P> DoubleEndedIterator for $reverse_iterator<'a, P>
+         where
+             P: Pattern<'a, Searcher: DoubleEndedSearcher<'a>>,
+         {
+             #[inline]
+             fn next_back(&mut self) -> Option<$iterty> {
+                 self.0.next()
+             }
+         }
+     };
+     {
+         single ended; with $(#[$common_stability_attribute:meta])*,
+                            $forward_iterator:ident,
+                            $reverse_iterator:ident, $iterty:ty
+     } => {}
+ }
+ 
+ derive_pattern_clone! {
+     clone SplitInternal
+     with |s| SplitInternal { matcher: s.matcher.clone(), ..*s }
+ }
+ 
+ pub(super) struct SplitInternal<'a, P: Pattern<'a>> {
+     pub(super) start: usize,
+     pub(super) end: usize,
+     pub(super) matcher: P::Searcher,
+     pub(super) allow_trailing_empty: bool,
+     pub(super) finished: bool,
+ }
+ 
+ impl<'a, P> fmt::Debug for SplitInternal<'a, P>
+ where
+     P: Pattern<'a, Searcher: fmt::Debug>,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitInternal")
+             .field("start", &self.start)
+             .field("end", &self.end)
+             .field("matcher", &self.matcher)
+             .field("allow_trailing_empty", &self.allow_trailing_empty)
+             .field("finished", &self.finished)
+             .finish()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> SplitInternal<'a, P> {
+     #[inline]
+     fn get_end(&mut self) -> Option<&'a str> {
+         if !self.finished && (self.allow_trailing_empty || self.end - self.start > 0) {
+             self.finished = true;
+             // SAFETY: `self.start` and `self.end` always lie on unicode boundaries.
+             unsafe {
+                 let string = self.matcher.haystack().get_unchecked(self.start..self.end);
+                 Some(string)
+             }
+         } else {
+             None
+         }
+     }
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         if self.finished {
+             return None;
+         }
+ 
+         let haystack = self.matcher.haystack();
+         match self.matcher.next_match() {
+             // SAFETY: `Searcher` guarantees that `a` and `b` lie on unicode boundaries.
+             Some((a, b)) => unsafe {
+                 let elt = haystack.get_unchecked(self.start..a);
+                 self.start = b;
+                 Some(elt)
+             },
+             None => self.get_end(),
+         }
+     }
+ 
+     #[inline]
+     fn next_inclusive(&mut self) -> Option<&'a str> {
+         if self.finished {
+             return None;
+         }
+ 
+         let haystack = self.matcher.haystack();
+         match self.matcher.next_match() {
+             // SAFETY: `Searcher` guarantees that `b` lies on unicode boundary,
+             // and self.start is either the start of the original string,
+             // or `b` was assigned to it, so it also lies on unicode boundary.
+             Some((_, b)) => unsafe {
+                 let elt = haystack.get_unchecked(self.start..b);
+                 self.start = b;
+                 Some(elt)
+             },
+             None => self.get_end(),
+         }
+     }
+ 
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str>
+     where
+         P::Searcher: ReverseSearcher<'a>,
+     {
+         if self.finished {
+             return None;
+         }
+ 
+         if !self.allow_trailing_empty {
+             self.allow_trailing_empty = true;
+             match self.next_back() {
+                 Some(elt) if !elt.is_empty() => return Some(elt),
+                 _ => {
+                     if self.finished {
+                         return None;
+                     }
+                 }
+             }
+         }
+ 
+         let haystack = self.matcher.haystack();
+         match self.matcher.next_match_back() {
+             // SAFETY: `Searcher` guarantees that `a` and `b` lie on unicode boundaries.
+             Some((a, b)) => unsafe {
+                 let elt = haystack.get_unchecked(b..self.end);
+                 self.end = a;
+                 Some(elt)
+             },
+             // SAFETY: `self.start` and `self.end` always lie on unicode boundaries.
+             None => unsafe {
+                 self.finished = true;
+                 Some(haystack.get_unchecked(self.start..self.end))
+             },
+         }
+     }
+ 
+     #[inline]
+     fn next_back_inclusive(&mut self) -> Option<&'a str>
+     where
+         P::Searcher: ReverseSearcher<'a>,
+     {
+         if self.finished {
+             return None;
+         }
+ 
+         if !self.allow_trailing_empty {
+             self.allow_trailing_empty = true;
+             match self.next_back_inclusive() {
+                 Some(elt) if !elt.is_empty() => return Some(elt),
+                 _ => {
+                     if self.finished {
+                         return None;
+                     }
+                 }
+             }
+         }
+ 
+         let haystack = self.matcher.haystack();
+         match self.matcher.next_match_back() {
+             // SAFETY: `Searcher` guarantees that `b` lies on unicode boundary,
+             // and self.end is either the end of the original string,
+             // or `b` was assigned to it, so it also lies on unicode boundary.
+             Some((_, b)) => unsafe {
+                 let elt = haystack.get_unchecked(b..self.end);
+                 self.end = b;
+                 Some(elt)
+             },
+             // SAFETY: self.start is either the start of the original string,
+             // or start of a substring that represents the part of the string that hasn't
+             // iterated yet. Either way, it is guaranteed to lie on unicode boundary.
+             // self.end is either the end of the original string,
+             // or `b` was assigned to it, so it also lies on unicode boundary.
+             None => unsafe {
+                 self.finished = true;
+                 Some(haystack.get_unchecked(self.start..self.end))
+             },
+         }
+     }
+ 
+     #[inline]
+     fn as_str(&self) -> &'a str {
+         // `Self::get_end` doesn't change `self.start`
+         if self.finished {
+             return "";
+         }
+ 
+         // SAFETY: `self.start` and `self.end` always lie on unicode boundaries.
+         unsafe { self.matcher.haystack().get_unchecked(self.start..self.end) }
+     }
+ }
+ 
+ generate_pattern_iterators! {
+     forward:
+         /// Created with the method [`split`].
+         ///
+         /// [`split`]: str::split
+         struct Split;
+     reverse:
+         /// Created with the method [`rsplit`].
+         ///
+         /// [`rsplit`]: str::rsplit
+         struct RSplit;
+     stability:
+         #[stable(feature = "rust1", since = "1.0.0")]
+     internal:
+         SplitInternal yielding (&'a str);
+     delegate double ended;
+ }
+ 
+ impl<'a, P: Pattern<'a>> Split<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_as_str)]
+     /// let mut split = "Mary had a little lamb".split(' ');
+     /// assert_eq!(split.as_str(), "Mary had a little lamb");
+     /// split.next();
+     /// assert_eq!(split.as_str(), "had a little lamb");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> RSplit<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_as_str)]
+     /// let mut split = "Mary had a little lamb".rsplit(' ');
+     /// assert_eq!(split.as_str(), "Mary had a little lamb");
+     /// split.next();
+     /// assert_eq!(split.as_str(), "Mary had a little");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ generate_pattern_iterators! {
+     forward:
+         /// Created with the method [`split_terminator`].
+         ///
+         /// [`split_terminator`]: str::split_terminator
+         struct SplitTerminator;
+     reverse:
+         /// Created with the method [`rsplit_terminator`].
+         ///
+         /// [`rsplit_terminator`]: str::rsplit_terminator
+         struct RSplitTerminator;
+     stability:
+         #[stable(feature = "rust1", since = "1.0.0")]
+     internal:
+         SplitInternal yielding (&'a str);
+     delegate double ended;
+ }
+ 
+ impl<'a, P: Pattern<'a>> SplitTerminator<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_as_str)]
+     /// let mut split = "A..B..".split_terminator('.');
+     /// assert_eq!(split.as_str(), "A..B..");
+     /// split.next();
+     /// assert_eq!(split.as_str(), ".B..");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> RSplitTerminator<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_as_str)]
+     /// let mut split = "A..B..".rsplit_terminator('.');
+     /// assert_eq!(split.as_str(), "A..B..");
+     /// split.next();
+     /// assert_eq!(split.as_str(), "A..B");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ derive_pattern_clone! {
+     clone SplitNInternal
+     with |s| SplitNInternal { iter: s.iter.clone(), ..*s }
+ }
+ 
+ pub(super) struct SplitNInternal<'a, P: Pattern<'a>> {
+     pub(super) iter: SplitInternal<'a, P>,
+     /// The number of splits remaining
+     pub(super) count: usize,
+ }
+ 
+ impl<'a, P> fmt::Debug for SplitNInternal<'a, P>
+ where
+     P: Pattern<'a, Searcher: fmt::Debug>,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitNInternal")
+             .field("iter", &self.iter)
+             .field("count", &self.count)
+             .finish()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> SplitNInternal<'a, P> {
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         match self.count {
+             0 => None,
+             1 => {
+                 self.count = 0;
+                 self.iter.get_end()
+             }
+             _ => {
+                 self.count -= 1;
+                 self.iter.next()
+             }
+         }
+     }
+ 
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str>
+     where
+         P::Searcher: ReverseSearcher<'a>,
+     {
+         match self.count {
+             0 => None,
+             1 => {
+                 self.count = 0;
+                 self.iter.get_end()
+             }
+             _ => {
+                 self.count -= 1;
+                 self.iter.next_back()
+             }
+         }
+     }
+ 
+     #[inline]
+     fn as_str(&self) -> &'a str {
+         self.iter.as_str()
+     }
+ }
+ 
+ generate_pattern_iterators! {
+     forward:
+         /// Created with the method [`splitn`].
+         ///
+         /// [`splitn`]: str::splitn
+         struct SplitN;
+     reverse:
+         /// Created with the method [`rsplitn`].
+         ///
+         /// [`rsplitn`]: str::rsplitn
+         struct RSplitN;
+     stability:
+         #[stable(feature = "rust1", since = "1.0.0")]
+     internal:
+         SplitNInternal yielding (&'a str);
+     delegate single ended;
+ }
+ 
+ impl<'a, P: Pattern<'a>> SplitN<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_as_str)]
+     /// let mut split = "Mary had a little lamb".splitn(3, ' ');
+     /// assert_eq!(split.as_str(), "Mary had a little lamb");
+     /// split.next();
+     /// assert_eq!(split.as_str(), "had a little lamb");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> RSplitN<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_as_str)]
+     /// let mut split = "Mary had a little lamb".rsplitn(3, ' ');
+     /// assert_eq!(split.as_str(), "Mary had a little lamb");
+     /// split.next();
+     /// assert_eq!(split.as_str(), "Mary had a little");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ derive_pattern_clone! {
+     clone MatchIndicesInternal
+     with |s| MatchIndicesInternal(s.0.clone())
+ }
+ 
+ pub(super) struct MatchIndicesInternal<'a, P: Pattern<'a>>(pub(super) P::Searcher);
+ 
+ impl<'a, P> fmt::Debug for MatchIndicesInternal<'a, P>
+ where
+     P: Pattern<'a, Searcher: fmt::Debug>,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_tuple("MatchIndicesInternal").field(&self.0).finish()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> MatchIndicesInternal<'a, P> {
+     #[inline]
+     fn next(&mut self) -> Option<(usize, &'a str)> {
+         self.0
+             .next_match()
+             // SAFETY: `Searcher` guarantees that `start` and `end` lie on unicode boundaries.
+             .map(|(start, end)| unsafe { (start, self.0.haystack().get_unchecked(start..end)) })
+     }
+ 
+     #[inline]
+     fn next_back(&mut self) -> Option<(usize, &'a str)>
+     where
+         P::Searcher: ReverseSearcher<'a>,
+     {
+         self.0
+             .next_match_back()
+             // SAFETY: `Searcher` guarantees that `start` and `end` lie on unicode boundaries.
+             .map(|(start, end)| unsafe { (start, self.0.haystack().get_unchecked(start..end)) })
+     }
+ }
+ 
+ generate_pattern_iterators! {
+     forward:
+         /// Created with the method [`match_indices`].
+         ///
+         /// [`match_indices`]: str::match_indices
+         struct MatchIndices;
+     reverse:
+         /// Created with the method [`rmatch_indices`].
+         ///
+         /// [`rmatch_indices`]: str::rmatch_indices
+         struct RMatchIndices;
+     stability:
+         #[stable(feature = "str_match_indices", since = "1.5.0")]
+     internal:
+         MatchIndicesInternal yielding ((usize, &'a str));
+     delegate double ended;
+ }
+ 
+ derive_pattern_clone! {
+     clone MatchesInternal
+     with |s| MatchesInternal(s.0.clone())
+ }
+ 
+ pub(super) struct MatchesInternal<'a, P: Pattern<'a>>(pub(super) P::Searcher);
+ 
+ impl<'a, P> fmt::Debug for MatchesInternal<'a, P>
+ where
+     P: Pattern<'a, Searcher: fmt::Debug>,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_tuple("MatchesInternal").field(&self.0).finish()
+     }
+ }
+ 
+ impl<'a, P: Pattern<'a>> MatchesInternal<'a, P> {
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         // SAFETY: `Searcher` guarantees that `start` and `end` lie on unicode boundaries.
+         self.0.next_match().map(|(a, b)| unsafe {
+             // Indices are known to be on utf8 boundaries
+             self.0.haystack().get_unchecked(a..b)
+         })
+     }
+ 
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str>
+     where
+         P::Searcher: ReverseSearcher<'a>,
+     {
+         // SAFETY: `Searcher` guarantees that `start` and `end` lie on unicode boundaries.
+         self.0.next_match_back().map(|(a, b)| unsafe {
+             // Indices are known to be on utf8 boundaries
+             self.0.haystack().get_unchecked(a..b)
+         })
+     }
+ }
+ 
+ generate_pattern_iterators! {
+     forward:
+         /// Created with the method [`matches`].
+         ///
+         /// [`matches`]: str::matches
+         struct Matches;
+     reverse:
+         /// Created with the method [`rmatches`].
+         ///
+         /// [`rmatches`]: str::rmatches
+         struct RMatches;
+     stability:
+         #[stable(feature = "str_matches", since = "1.2.0")]
+     internal:
+         MatchesInternal yielding (&'a str);
+     delegate double ended;
+ }
+ 
+ /// An iterator over the lines of a string, as string slices.
+ ///
+ /// This struct is created with the [`lines`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`lines`]: str::lines
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Clone, Debug)]
+ pub struct Lines<'a>(pub(super) Map<SplitTerminator<'a, char>, LinesAnyMap>);
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a> Iterator for Lines<'a> {
+     type Item = &'a str;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         self.0.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.0.size_hint()
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<&'a str> {
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<'a> DoubleEndedIterator for Lines<'a> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str> {
+         self.0.next_back()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for Lines<'_> {}
+ 
+ /// Created with the method [`lines_any`].
+ ///
+ /// [`lines_any`]: str::lines_any
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_deprecated(since = "1.4.0", reason = "use lines()/Lines instead now")]
+ #[derive(Clone, Debug)]
+ #[allow(deprecated)]
+ pub struct LinesAny<'a>(pub(super) Lines<'a>);
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow(deprecated)]
+ impl<'a> Iterator for LinesAny<'a> {
+     type Item = &'a str;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         self.0.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.0.size_hint()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow(deprecated)]
+ impl<'a> DoubleEndedIterator for LinesAny<'a> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str> {
+         self.0.next_back()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ #[allow(deprecated)]
+ impl FusedIterator for LinesAny<'_> {}
+ 
+ /// An iterator over the non-whitespace substrings of a string,
+ /// separated by any amount of whitespace.
+ ///
+ /// This struct is created by the [`split_whitespace`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`split_whitespace`]: str::split_whitespace
+ #[stable(feature = "split_whitespace", since = "1.1.0")]
+ #[derive(Clone, Debug)]
+ pub struct SplitWhitespace<'a> {
+     pub(super) inner: Filter<Split<'a, IsWhitespace>, IsNotEmpty>,
+ }
+ 
+ /// An iterator over the non-ASCII-whitespace substrings of a string,
+ /// separated by any amount of ASCII whitespace.
+ ///
+ /// This struct is created by the [`split_ascii_whitespace`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`split_ascii_whitespace`]: str::split_ascii_whitespace
+ #[stable(feature = "split_ascii_whitespace", since = "1.34.0")]
+ #[derive(Clone, Debug)]
+ pub struct SplitAsciiWhitespace<'a> {
+     pub(super) inner:
+         Map<Filter<SliceSplit<'a, u8, IsAsciiWhitespace>, BytesIsNotEmpty>, UnsafeBytesToStr>,
+ }
+ 
+ /// An iterator over the substrings of a string,
+ /// terminated by a substring matching to a predicate function
+ /// Unlike `Split`, it contains the matched part as a terminator
+ /// of the subslice.
+ ///
+ /// This struct is created by the [`split_inclusive`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`split_inclusive`]: str::split_inclusive
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ pub struct SplitInclusive<'a, P: Pattern<'a>>(pub(super) SplitInternal<'a, P>);
+ 
+ #[stable(feature = "split_whitespace", since = "1.1.0")]
+ impl<'a> Iterator for SplitWhitespace<'a> {
+     type Item = &'a str;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         self.inner.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<&'a str> {
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "split_whitespace", since = "1.1.0")]
+ impl<'a> DoubleEndedIterator for SplitWhitespace<'a> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str> {
+         self.inner.next_back()
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for SplitWhitespace<'_> {}
+ 
+ #[stable(feature = "split_ascii_whitespace", since = "1.34.0")]
+ impl<'a> Iterator for SplitAsciiWhitespace<'a> {
+     type Item = &'a str;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         self.inner.next()
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         self.inner.size_hint()
+     }
+ 
+     #[inline]
+     fn last(mut self) -> Option<&'a str> {
+         self.next_back()
+     }
+ }
+ 
+ #[stable(feature = "split_ascii_whitespace", since = "1.34.0")]
+ impl<'a> DoubleEndedIterator for SplitAsciiWhitespace<'a> {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str> {
+         self.inner.next_back()
+     }
+ }
+ 
+ #[stable(feature = "split_ascii_whitespace", since = "1.34.0")]
+ impl FusedIterator for SplitAsciiWhitespace<'_> {}
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, P: Pattern<'a>> Iterator for SplitInclusive<'a, P> {
+     type Item = &'a str;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<&'a str> {
+         self.0.next_inclusive()
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, P: Pattern<'a, Searcher: fmt::Debug>> fmt::Debug for SplitInclusive<'a, P> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("SplitInclusive").field("0", &self.0).finish()
+     }
+ }
+ 
+ // FIXME(#26925) Remove in favor of `#[derive(Clone)]`
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, P: Pattern<'a, Searcher: Clone>> Clone for SplitInclusive<'a, P> {
+     fn clone(&self) -> Self {
+         SplitInclusive(self.0.clone())
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, P: Pattern<'a, Searcher: ReverseSearcher<'a>>> DoubleEndedIterator
+     for SplitInclusive<'a, P>
+ {
+     #[inline]
+     fn next_back(&mut self) -> Option<&'a str> {
+         self.0.next_back_inclusive()
+     }
+ }
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ impl<'a, P: Pattern<'a>> FusedIterator for SplitInclusive<'a, P> {}
+ 
+ impl<'a, P: Pattern<'a>> SplitInclusive<'a, P> {
+     /// Returns remainder of the splitted string
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_inclusive_as_str)]
+     /// #![feature(split_inclusive)]
+     /// let mut split = "Mary had a little lamb".split_inclusive(' ');
+     /// assert_eq!(split.as_str(), "Mary had a little lamb");
+     /// split.next();
+     /// assert_eq!(split.as_str(), "had a little lamb");
+     /// split.by_ref().for_each(drop);
+     /// assert_eq!(split.as_str(), "");
+     /// ```
+     #[inline]
+     #[unstable(feature = "str_split_inclusive_as_str", issue = "77998")]
+     pub fn as_str(&self) -> &'a str {
+         self.0.as_str()
+     }
+ }
+ 
+ /// An iterator of [`u16`] over the string encoded as UTF-16.
+ ///
+ /// This struct is created by the [`encode_utf16`] method on [`str`].
+ /// See its documentation for more.
+ ///
+ /// [`encode_utf16`]: str::encode_utf16
+ #[derive(Clone)]
+ #[stable(feature = "encode_utf16", since = "1.8.0")]
+ pub struct EncodeUtf16<'a> {
+     pub(super) chars: Chars<'a>,
+     pub(super) extra: u16,
+ }
+ 
+ #[stable(feature = "collection_debug", since = "1.17.0")]
+ impl fmt::Debug for EncodeUtf16<'_> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.pad("EncodeUtf16 { .. }")
+     }
+ }
+ 
+ #[stable(feature = "encode_utf16", since = "1.8.0")]
+ impl<'a> Iterator for EncodeUtf16<'a> {
+     type Item = u16;
+ 
+     #[inline]
+     fn next(&mut self) -> Option<u16> {
+         if self.extra != 0 {
+             let tmp = self.extra;
+             self.extra = 0;
+             return Some(tmp);
+         }
+ 
+         let mut buf = [0; 2];
+         self.chars.next().map(|ch| {
+             let n = ch.encode_utf16(&mut buf).len();
+             if n == 2 {
+                 self.extra = buf[1];
+             }
+             buf[0]
+         })
+     }
+ 
+     #[inline]
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         let (low, high) = self.chars.size_hint();
+         // every char gets either one u16 or two u16,
+         // so this iterator is between 1 or 2 times as
+         // long as the underlying iterator.
+         (low, high.and_then(|n| n.checked_mul(2)))
+     }
+ }
+ 
+ #[stable(feature = "fused", since = "1.26.0")]
+ impl FusedIterator for EncodeUtf16<'_> {}
+ 
+ /// The return type of [`str::escape_debug`].
+ #[stable(feature = "str_escape", since = "1.34.0")]
+ #[derive(Clone, Debug)]
+ pub struct EscapeDebug<'a> {
+     pub(super) inner: Chain<
+         Flatten<option::IntoIter<char::EscapeDebug>>,
+         FlatMap<Chars<'a>, char::EscapeDebug, CharEscapeDebugContinue>,
+     >,
+ }
+ 
+ /// The return type of [`str::escape_default`].
+ #[stable(feature = "str_escape", since = "1.34.0")]
+ #[derive(Clone, Debug)]
+ pub struct EscapeDefault<'a> {
+     pub(super) inner: FlatMap<Chars<'a>, char::EscapeDefault, CharEscapeDefault>,
+ }
+ 
+ /// The return type of [`str::escape_unicode`].
+ #[stable(feature = "str_escape", since = "1.34.0")]
+ #[derive(Clone, Debug)]
+ pub struct EscapeUnicode<'a> {
+     pub(super) inner: FlatMap<Chars<'a>, char::EscapeUnicode, CharEscapeUnicode>,
+ }
+ 
+ macro_rules! escape_types_impls {
+     ($( $Name: ident ),+) => {$(
+         #[stable(feature = "str_escape", since = "1.34.0")]
+         impl<'a> fmt::Display for $Name<'a> {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 self.clone().try_for_each(|c| f.write_char(c))
+             }
+         }
+ 
+         #[stable(feature = "str_escape", since = "1.34.0")]
+         impl<'a> Iterator for $Name<'a> {
+             type Item = char;
+ 
+             #[inline]
+             fn next(&mut self) -> Option<char> { self.inner.next() }
+ 
+             #[inline]
+             fn size_hint(&self) -> (usize, Option<usize>) { self.inner.size_hint() }
+ 
+             #[inline]
+             fn try_fold<Acc, Fold, R>(&mut self, init: Acc, fold: Fold) -> R where
+                 Self: Sized, Fold: FnMut(Acc, Self::Item) -> R, R: Try<Ok=Acc>
+             {
+                 self.inner.try_fold(init, fold)
+             }
+ 
+             #[inline]
+             fn fold<Acc, Fold>(self, init: Acc, fold: Fold) -> Acc
+                 where Fold: FnMut(Acc, Self::Item) -> Acc,
+             {
+                 self.inner.fold(init, fold)
+             }
+         }
+ 
+         #[stable(feature = "str_escape", since = "1.34.0")]
+         impl<'a> FusedIterator for $Name<'a> {}
+     )+}
+ }
+ 
+ escape_types_impls!(EscapeDebug, EscapeDefault, EscapeUnicode);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/lossy.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/lossy.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/lossy.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/lossy.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,203 ----
+ use crate::char;
+ use crate::fmt::{self, Write};
+ use crate::mem;
+ 
+ use super::from_utf8_unchecked;
+ use super::validations::utf8_char_width;
+ 
+ /// Lossy UTF-8 string.
+ #[unstable(feature = "str_internals", issue = "none")]
+ pub struct Utf8Lossy {
+     bytes: [u8],
+ }
+ 
+ impl Utf8Lossy {
+     pub fn from_str(s: &str) -> &Utf8Lossy {
+         Utf8Lossy::from_bytes(s.as_bytes())
+     }
+ 
+     pub fn from_bytes(bytes: &[u8]) -> &Utf8Lossy {
+         // SAFETY: Both use the same memory layout, and UTF-8 correctness isn't required.
+         unsafe { mem::transmute(bytes) }
+     }
+ 
+     pub fn chunks(&self) -> Utf8LossyChunksIter<'_> {
+         Utf8LossyChunksIter { source: &self.bytes }
+     }
+ }
+ 
+ /// Iterator over lossy UTF-8 string
+ #[unstable(feature = "str_internals", issue = "none")]
+ #[allow(missing_debug_implementations)]
+ pub struct Utf8LossyChunksIter<'a> {
+     source: &'a [u8],
+ }
+ 
+ #[unstable(feature = "str_internals", issue = "none")]
+ #[derive(PartialEq, Eq, Debug)]
+ pub struct Utf8LossyChunk<'a> {
+     /// Sequence of valid chars.
+     /// Can be empty between broken UTF-8 chars.
+     pub valid: &'a str,
+     /// Single broken char, empty if none.
+     /// Empty iff iterator item is last.
+     pub broken: &'a [u8],
+ }
+ 
+ impl<'a> Iterator for Utf8LossyChunksIter<'a> {
+     type Item = Utf8LossyChunk<'a>;
+ 
+     fn next(&mut self) -> Option<Utf8LossyChunk<'a>> {
+         if self.source.is_empty() {
+             return None;
+         }
+ 
+         const TAG_CONT_U8: u8 = 128;
+         fn safe_get(xs: &[u8], i: usize) -> u8 {
+             *xs.get(i).unwrap_or(&0)
+         }
+ 
+         let mut i = 0;
+         while i < self.source.len() {
+             let i_ = i;
+ 
+             // SAFETY: `i` starts at `0`, is less than `self.source.len()`, and
+             // only increases, so `0 <= i < self.source.len()`.
+             let byte = unsafe { *self.source.get_unchecked(i) };
+             i += 1;
+ 
+             if byte < 128 {
+             } else {
+                 let w = utf8_char_width(byte);
+ 
+                 macro_rules! error {
+                     () => {{
+                         // SAFETY: We have checked up to `i` that source is valid UTF-8.
+                         unsafe {
+                             let r = Utf8LossyChunk {
+                                 valid: from_utf8_unchecked(&self.source[0..i_]),
+                                 broken: &self.source[i_..i],
+                             };
+                             self.source = &self.source[i..];
+                             return Some(r);
+                         }
+                     }};
+                 }
+ 
+                 match w {
+                     2 => {
+                         if safe_get(self.source, i) & 192 != TAG_CONT_U8 {
+                             error!();
+                         }
+                         i += 1;
+                     }
+                     3 => {
+                         match (byte, safe_get(self.source, i)) {
+                             (0xE0, 0xA0..=0xBF) => (),
+                             (0xE1..=0xEC, 0x80..=0xBF) => (),
+                             (0xED, 0x80..=0x9F) => (),
+                             (0xEE..=0xEF, 0x80..=0xBF) => (),
+                             _ => {
+                                 error!();
+                             }
+                         }
+                         i += 1;
+                         if safe_get(self.source, i) & 192 != TAG_CONT_U8 {
+                             error!();
+                         }
+                         i += 1;
+                     }
+                     4 => {
+                         match (byte, safe_get(self.source, i)) {
+                             (0xF0, 0x90..=0xBF) => (),
+                             (0xF1..=0xF3, 0x80..=0xBF) => (),
+                             (0xF4, 0x80..=0x8F) => (),
+                             _ => {
+                                 error!();
+                             }
+                         }
+                         i += 1;
+                         if safe_get(self.source, i) & 192 != TAG_CONT_U8 {
+                             error!();
+                         }
+                         i += 1;
+                         if safe_get(self.source, i) & 192 != TAG_CONT_U8 {
+                             error!();
+                         }
+                         i += 1;
+                     }
+                     _ => {
+                         error!();
+                     }
+                 }
+             }
+         }
+ 
+         let r = Utf8LossyChunk {
+             // SAFETY: We have checked that the entire source is valid UTF-8.
+             valid: unsafe { from_utf8_unchecked(self.source) },
+             broken: &[],
+         };
+         self.source = &[];
+         Some(r)
+     }
+ }
+ 
+ impl fmt::Display for Utf8Lossy {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         // If we're the empty string then our iterator won't actually yield
+         // anything, so perform the formatting manually
+         if self.bytes.is_empty() {
+             return "".fmt(f);
+         }
+ 
+         for Utf8LossyChunk { valid, broken } in self.chunks() {
+             // If we successfully decoded the whole chunk as a valid string then
+             // we can return a direct formatting of the string which will also
+             // respect various formatting flags if possible.
+             if valid.len() == self.bytes.len() {
+                 assert!(broken.is_empty());
+                 return valid.fmt(f);
+             }
+ 
+             f.write_str(valid)?;
+             if !broken.is_empty() {
+                 f.write_char(char::REPLACEMENT_CHARACTER)?;
+             }
+         }
+         Ok(())
+     }
+ }
+ 
+ impl fmt::Debug for Utf8Lossy {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.write_char('"')?;
+ 
+         for Utf8LossyChunk { valid, broken } in self.chunks() {
+             // Valid part.
+             // Here we partially parse UTF-8 again which is suboptimal.
+             {
+                 let mut from = 0;
+                 for (i, c) in valid.char_indices() {
+                     let esc = c.escape_debug();
+                     // If char needs escaping, flush backlog so far and write, else skip
+                     if esc.len() != 1 {
+                         f.write_str(&valid[from..i])?;
+                         for c in esc {
+                             f.write_char(c)?;
+                         }
+                         from = i + c.len_utf8();
+                     }
+                 }
+                 f.write_str(&valid[from..])?;
+             }
+ 
+             // Broken parts of string as hex escape.
+             for &b in broken {
+                 write!(f, "\\x{:02x}", b)?;
+             }
+         }
+ 
+         f.write_char('"')
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2499 ----
+ //! String manipulation.
+ //!
+ //! For more details, see the [`std::str`] module.
+ //!
+ //! [`std::str`]: ../../std/str/index.html
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ mod converts;
+ mod error;
+ mod iter;
+ mod traits;
+ mod validations;
+ 
+ use self::pattern::Pattern;
+ use self::pattern::{DoubleEndedSearcher, ReverseSearcher, Searcher};
+ 
+ use crate::char;
+ use crate::mem;
+ use crate::slice::{self, SliceIndex};
+ 
+ pub mod pattern;
+ 
+ #[unstable(feature = "str_internals", issue = "none")]
+ #[allow(missing_docs)]
+ pub mod lossy;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use converts::{from_utf8, from_utf8_unchecked};
+ 
+ #[stable(feature = "str_mut_extras", since = "1.20.0")]
+ pub use converts::{from_utf8_mut, from_utf8_unchecked_mut};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use error::{ParseBoolError, Utf8Error};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use traits::FromStr;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use iter::{Bytes, CharIndices, Chars, Lines, SplitWhitespace};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[allow(deprecated)]
+ pub use iter::LinesAny;
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use iter::{RSplit, RSplitTerminator, Split, SplitTerminator};
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub use iter::{RSplitN, SplitN};
+ 
+ #[stable(feature = "str_matches", since = "1.2.0")]
+ pub use iter::{Matches, RMatches};
+ 
+ #[stable(feature = "str_match_indices", since = "1.5.0")]
+ pub use iter::{MatchIndices, RMatchIndices};
+ 
+ #[stable(feature = "encode_utf16", since = "1.8.0")]
+ pub use iter::EncodeUtf16;
+ 
+ #[stable(feature = "str_escape", since = "1.34.0")]
+ pub use iter::{EscapeDebug, EscapeDefault, EscapeUnicode};
+ 
+ #[stable(feature = "split_ascii_whitespace", since = "1.34.0")]
+ pub use iter::SplitAsciiWhitespace;
+ 
+ #[unstable(feature = "split_inclusive", issue = "72360")]
+ use iter::SplitInclusive;
+ 
+ #[unstable(feature = "str_internals", issue = "none")]
+ pub use validations::next_code_point;
+ 
+ use iter::MatchIndicesInternal;
+ use iter::SplitInternal;
+ use iter::{MatchesInternal, SplitNInternal};
+ 
+ use validations::truncate_to_char_boundary;
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ fn slice_error_fail(s: &str, begin: usize, end: usize) -> ! {
+     const MAX_DISPLAY_LENGTH: usize = 256;
+     let (truncated, s_trunc) = truncate_to_char_boundary(s, MAX_DISPLAY_LENGTH);
+     let ellipsis = if truncated { "[...]" } else { "" };
+ 
+     // 1. out of bounds
+     if begin > s.len() || end > s.len() {
+         let oob_index = if begin > s.len() { begin } else { end };
+         panic!("byte index {} is out of bounds of `{}`{}", oob_index, s_trunc, ellipsis);
+     }
+ 
+     // 2. begin <= end
+     assert!(
+         begin <= end,
+         "begin <= end ({} <= {}) when slicing `{}`{}",
+         begin,
+         end,
+         s_trunc,
+         ellipsis
+     );
+ 
+     // 3. character boundary
+     let index = if !s.is_char_boundary(begin) { begin } else { end };
+     // find the character
+     let mut char_start = index;
+     while !s.is_char_boundary(char_start) {
+         char_start -= 1;
+     }
+     // `char_start` must be less than len and a char boundary
+     let ch = s[char_start..].chars().next().unwrap();
+     let char_range = char_start..char_start + ch.len_utf8();
+     panic!(
+         "byte index {} is not a char boundary; it is inside {:?} (bytes {:?}) of `{}`{}",
+         index, ch, char_range, s_trunc, ellipsis
+     );
+ }
+ 
+ #[lang = "str"]
+ #[cfg(not(test))]
+ impl str {
+     /// Returns the length of `self`.
+     ///
+     /// This length is in bytes, not [`char`]s or graphemes. In other words,
+     /// it may not be what a human considers the length of the string.
+     ///
+     /// [`char`]: prim@char
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let len = "foo".len();
+     /// assert_eq!(3, len);
+     ///
+     /// assert_eq!("ƒoo".len(), 4); // fancy f!
+     /// assert_eq!("ƒoo".chars().count(), 3);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_str_len", since = "1.32.0")]
+     #[inline]
+     pub const fn len(&self) -> usize {
+         self.as_bytes().len()
+     }
+ 
+     /// Returns `true` if `self` has a length of zero bytes.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = "";
+     /// assert!(s.is_empty());
+     ///
+     /// let s = "not empty";
+     /// assert!(!s.is_empty());
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_str_is_empty", since = "1.32.0")]
+     pub const fn is_empty(&self) -> bool {
+         self.len() == 0
+     }
+ 
+     /// Checks that `index`-th byte is the first byte in a UTF-8 code point
+     /// sequence or the end of the string.
+     ///
+     /// The start and end of the string (when `index == self.len()`) are
+     /// considered to be boundaries.
+     ///
+     /// Returns `false` if `index` is greater than `self.len()`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard";
+     /// assert!(s.is_char_boundary(0));
+     /// // start of `老`
+     /// assert!(s.is_char_boundary(6));
+     /// assert!(s.is_char_boundary(s.len()));
+     ///
+     /// // second byte of `ö`
+     /// assert!(!s.is_char_boundary(2));
+     ///
+     /// // third byte of `老`
+     /// assert!(!s.is_char_boundary(8));
+     /// ```
+     #[stable(feature = "is_char_boundary", since = "1.9.0")]
+     #[inline]
+     pub fn is_char_boundary(&self, index: usize) -> bool {
+         // 0 and len are always ok.
+         // Test for 0 explicitly so that it can optimize out the check
+         // easily and skip reading string data for that case.
+         if index == 0 || index == self.len() {
+             return true;
+         }
+         match self.as_bytes().get(index) {
+             None => false,
+             // This is bit magic equivalent to: b < 128 || b >= 192
+             Some(&b) => (b as i8) >= -0x40,
+         }
+     }
+ 
+     /// Converts a string slice to a byte slice. To convert the byte slice back
+     /// into a string slice, use the [`from_utf8`] function.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let bytes = "bors".as_bytes();
+     /// assert_eq!(b"bors", bytes);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "str_as_bytes", since = "1.32.0")]
+     #[inline(always)]
+     #[allow(unused_attributes)]
+     #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_transmute))]
+     #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_transmute))]
+     pub const fn as_bytes(&self) -> &[u8] {
+         // SAFETY: const sound because we transmute two types with the same layout
+         unsafe { mem::transmute(self) }
+     }
+ 
+     /// Converts a mutable string slice to a mutable byte slice.
+     ///
+     /// # Safety
+     ///
+     /// The caller must ensure that the content of the slice is valid UTF-8
+     /// before the borrow ends and the underlying `str` is used.
+     ///
+     /// Use of a `str` whose contents are not valid UTF-8 is undefined behavior.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut s = String::from("Hello");
+     /// let bytes = unsafe { s.as_bytes_mut() };
+     ///
+     /// assert_eq!(b"Hello", bytes);
+     /// ```
+     ///
+     /// Mutability:
+     ///
+     /// ```
+     /// let mut s = String::from("🗻∈🌏");
+     ///
+     /// unsafe {
+     ///     let bytes = s.as_bytes_mut();
+     ///
+     ///     bytes[0] = 0xF0;
+     ///     bytes[1] = 0x9F;
+     ///     bytes[2] = 0x8D;
+     ///     bytes[3] = 0x94;
+     /// }
+     ///
+     /// assert_eq!("🍔∈🌏", s);
+     /// ```
+     #[stable(feature = "str_mut_extras", since = "1.20.0")]
+     #[inline(always)]
+     pub unsafe fn as_bytes_mut(&mut self) -> &mut [u8] {
+         // SAFETY: the cast from `&str` to `&[u8]` is safe since `str`
+         // has the same layout as `&[u8]` (only libstd can make this guarantee).
+         // The pointer dereference is safe since it comes from a mutable reference which
+         // is guaranteed to be valid for writes.
+         unsafe { &mut *(self as *mut str as *mut [u8]) }
+     }
+ 
+     /// Converts a string slice to a raw pointer.
+     ///
+     /// As string slices are a slice of bytes, the raw pointer points to a
+     /// [`u8`]. This pointer will be pointing to the first byte of the string
+     /// slice.
+     ///
+     /// The caller must ensure that the returned pointer is never written to.
+     /// If you need to mutate the contents of the string slice, use [`as_mut_ptr`].
+     ///
+     /// [`as_mut_ptr`]: str::as_mut_ptr
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = "Hello";
+     /// let ptr = s.as_ptr();
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "rustc_str_as_ptr", since = "1.32.0")]
+     #[inline]
+     pub const fn as_ptr(&self) -> *const u8 {
+         self as *const str as *const u8
+     }
+ 
+     /// Converts a mutable string slice to a raw pointer.
+     ///
+     /// As string slices are a slice of bytes, the raw pointer points to a
+     /// [`u8`]. This pointer will be pointing to the first byte of the string
+     /// slice.
+     ///
+     /// It is your responsibility to make sure that the string slice only gets
+     /// modified in a way that it remains valid UTF-8.
+     #[stable(feature = "str_as_mut_ptr", since = "1.36.0")]
+     #[inline]
+     pub fn as_mut_ptr(&mut self) -> *mut u8 {
+         self as *mut str as *mut u8
+     }
+ 
+     /// Returns a subslice of `str`.
+     ///
+     /// This is the non-panicking alternative to indexing the `str`. Returns
+     /// [`None`] whenever equivalent indexing operation would panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = String::from("🗻∈🌏");
+     ///
+     /// assert_eq!(Some("🗻"), v.get(0..4));
+     ///
+     /// // indices not on UTF-8 sequence boundaries
+     /// assert!(v.get(1..).is_none());
+     /// assert!(v.get(..8).is_none());
+     ///
+     /// // out of bounds
+     /// assert!(v.get(..42).is_none());
+     /// ```
+     #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+     #[inline]
+     pub fn get<I: SliceIndex<str>>(&self, i: I) -> Option<&I::Output> {
+         i.get(self)
+     }
+ 
+     /// Returns a mutable subslice of `str`.
+     ///
+     /// This is the non-panicking alternative to indexing the `str`. Returns
+     /// [`None`] whenever equivalent indexing operation would panic.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = String::from("hello");
+     /// // correct length
+     /// assert!(v.get_mut(0..5).is_some());
+     /// // out of bounds
+     /// assert!(v.get_mut(..42).is_none());
+     /// assert_eq!(Some("he"), v.get_mut(0..2).map(|v| &*v));
+     ///
+     /// assert_eq!("hello", v);
+     /// {
+     ///     let s = v.get_mut(0..2);
+     ///     let s = s.map(|s| {
+     ///         s.make_ascii_uppercase();
+     ///         &*s
+     ///     });
+     ///     assert_eq!(Some("HE"), s);
+     /// }
+     /// assert_eq!("HEllo", v);
+     /// ```
+     #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+     #[inline]
+     pub fn get_mut<I: SliceIndex<str>>(&mut self, i: I) -> Option<&mut I::Output> {
+         i.get_mut(self)
+     }
+ 
+     /// Returns an unchecked subslice of `str`.
+     ///
+     /// This is the unchecked alternative to indexing the `str`.
+     ///
+     /// # Safety
+     ///
+     /// Callers of this function are responsible that these preconditions are
+     /// satisfied:
+     ///
+     /// * The starting index must not exceed the ending index;
+     /// * Indexes must be within bounds of the original slice;
+     /// * Indexes must lie on UTF-8 sequence boundaries.
+     ///
+     /// Failing that, the returned string slice may reference invalid memory or
+     /// violate the invariants communicated by the `str` type.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v = "🗻∈🌏";
+     /// unsafe {
+     ///     assert_eq!("🗻", v.get_unchecked(0..4));
+     ///     assert_eq!("∈", v.get_unchecked(4..7));
+     ///     assert_eq!("🌏", v.get_unchecked(7..11));
+     /// }
+     /// ```
+     #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+     #[inline]
+     pub unsafe fn get_unchecked<I: SliceIndex<str>>(&self, i: I) -> &I::Output {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked`;
+         // the slice is dereferencable because `self` is a safe reference.
+         // The returned pointer is safe because impls of `SliceIndex` have to guarantee that it is.
+         unsafe { &*i.get_unchecked(self) }
+     }
+ 
+     /// Returns a mutable, unchecked subslice of `str`.
+     ///
+     /// This is the unchecked alternative to indexing the `str`.
+     ///
+     /// # Safety
+     ///
+     /// Callers of this function are responsible that these preconditions are
+     /// satisfied:
+     ///
+     /// * The starting index must not exceed the ending index;
+     /// * Indexes must be within bounds of the original slice;
+     /// * Indexes must lie on UTF-8 sequence boundaries.
+     ///
+     /// Failing that, the returned string slice may reference invalid memory or
+     /// violate the invariants communicated by the `str` type.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut v = String::from("🗻∈🌏");
+     /// unsafe {
+     ///     assert_eq!("🗻", v.get_unchecked_mut(0..4));
+     ///     assert_eq!("∈", v.get_unchecked_mut(4..7));
+     ///     assert_eq!("🌏", v.get_unchecked_mut(7..11));
+     /// }
+     /// ```
+     #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+     #[inline]
+     pub unsafe fn get_unchecked_mut<I: SliceIndex<str>>(&mut self, i: I) -> &mut I::Output {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`;
+         // the slice is dereferencable because `self` is a safe reference.
+         // The returned pointer is safe because impls of `SliceIndex` have to guarantee that it is.
+         unsafe { &mut *i.get_unchecked_mut(self) }
+     }
+ 
+     /// Creates a string slice from another string slice, bypassing safety
+     /// checks.
+     ///
+     /// This is generally not recommended, use with caution! For a safe
+     /// alternative see [`str`] and [`Index`].
+     ///
+     /// [`Index`]: crate::ops::Index
+     ///
+     /// This new slice goes from `begin` to `end`, including `begin` but
+     /// excluding `end`.
+     ///
+     /// To get a mutable string slice instead, see the
+     /// [`slice_mut_unchecked`] method.
+     ///
+     /// [`slice_mut_unchecked`]: str::slice_mut_unchecked
+     ///
+     /// # Safety
+     ///
+     /// Callers of this function are responsible that three preconditions are
+     /// satisfied:
+     ///
+     /// * `begin` must not exceed `end`.
+     /// * `begin` and `end` must be byte positions within the string slice.
+     /// * `begin` and `end` must lie on UTF-8 sequence boundaries.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard";
+     ///
+     /// unsafe {
+     ///     assert_eq!("Löwe 老虎 Léopard", s.slice_unchecked(0, 21));
+     /// }
+     ///
+     /// let s = "Hello, world!";
+     ///
+     /// unsafe {
+     ///     assert_eq!("world", s.slice_unchecked(7, 12));
+     /// }
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(since = "1.29.0", reason = "use `get_unchecked(begin..end)` instead")]
+     #[inline]
+     pub unsafe fn slice_unchecked(&self, begin: usize, end: usize) -> &str {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked`;
+         // the slice is dereferencable because `self` is a safe reference.
+         // The returned pointer is safe because impls of `SliceIndex` have to guarantee that it is.
+         unsafe { &*(begin..end).get_unchecked(self) }
+     }
+ 
+     /// Creates a string slice from another string slice, bypassing safety
+     /// checks.
+     /// This is generally not recommended, use with caution! For a safe
+     /// alternative see [`str`] and [`IndexMut`].
+     ///
+     /// [`IndexMut`]: crate::ops::IndexMut
+     ///
+     /// This new slice goes from `begin` to `end`, including `begin` but
+     /// excluding `end`.
+     ///
+     /// To get an immutable string slice instead, see the
+     /// [`slice_unchecked`] method.
+     ///
+     /// [`slice_unchecked`]: str::slice_unchecked
+     ///
+     /// # Safety
+     ///
+     /// Callers of this function are responsible that three preconditions are
+     /// satisfied:
+     ///
+     /// * `begin` must not exceed `end`.
+     /// * `begin` and `end` must be byte positions within the string slice.
+     /// * `begin` and `end` must lie on UTF-8 sequence boundaries.
+     #[stable(feature = "str_slice_mut", since = "1.5.0")]
+     #[rustc_deprecated(since = "1.29.0", reason = "use `get_unchecked_mut(begin..end)` instead")]
+     #[inline]
+     pub unsafe fn slice_mut_unchecked(&mut self, begin: usize, end: usize) -> &mut str {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`;
+         // the slice is dereferencable because `self` is a safe reference.
+         // The returned pointer is safe because impls of `SliceIndex` have to guarantee that it is.
+         unsafe { &mut *(begin..end).get_unchecked_mut(self) }
+     }
+ 
+     /// Divide one string slice into two at an index.
+     ///
+     /// The argument, `mid`, should be a byte offset from the start of the
+     /// string. It must also be on the boundary of a UTF-8 code point.
+     ///
+     /// The two slices returned go from the start of the string slice to `mid`,
+     /// and from `mid` to the end of the string slice.
+     ///
+     /// To get mutable string slices instead, see the [`split_at_mut`]
+     /// method.
+     ///
+     /// [`split_at_mut`]: str::split_at_mut
+     ///
+     /// # Panics
+     ///
+     /// Panics if `mid` is not on a UTF-8 code point boundary, or if it is
+     /// past the end of the last code point of the string slice.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = "Per Martin-Löf";
+     ///
+     /// let (first, last) = s.split_at(3);
+     ///
+     /// assert_eq!("Per", first);
+     /// assert_eq!(" Martin-Löf", last);
+     /// ```
+     #[inline]
+     #[stable(feature = "str_split_at", since = "1.4.0")]
+     pub fn split_at(&self, mid: usize) -> (&str, &str) {
+         // is_char_boundary checks that the index is in [0, .len()]
+         if self.is_char_boundary(mid) {
+             // SAFETY: just checked that `mid` is on a char boundary.
+             unsafe { (self.get_unchecked(0..mid), self.get_unchecked(mid..self.len())) }
+         } else {
+             slice_error_fail(self, 0, mid)
+         }
+     }
+ 
+     /// Divide one mutable string slice into two at an index.
+     ///
+     /// The argument, `mid`, should be a byte offset from the start of the
+     /// string. It must also be on the boundary of a UTF-8 code point.
+     ///
+     /// The two slices returned go from the start of the string slice to `mid`,
+     /// and from `mid` to the end of the string slice.
+     ///
+     /// To get immutable string slices instead, see the [`split_at`] method.
+     ///
+     /// [`split_at`]: str::split_at
+     ///
+     /// # Panics
+     ///
+     /// Panics if `mid` is not on a UTF-8 code point boundary, or if it is
+     /// past the end of the last code point of the string slice.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut s = "Per Martin-Löf".to_string();
+     /// {
+     ///     let (first, last) = s.split_at_mut(3);
+     ///     first.make_ascii_uppercase();
+     ///     assert_eq!("PER", first);
+     ///     assert_eq!(" Martin-Löf", last);
+     /// }
+     /// assert_eq!("PER Martin-Löf", s);
+     /// ```
+     #[inline]
+     #[stable(feature = "str_split_at", since = "1.4.0")]
+     pub fn split_at_mut(&mut self, mid: usize) -> (&mut str, &mut str) {
+         // is_char_boundary checks that the index is in [0, .len()]
+         if self.is_char_boundary(mid) {
+             let len = self.len();
+             let ptr = self.as_mut_ptr();
+             // SAFETY: just checked that `mid` is on a char boundary.
+             unsafe {
+                 (
+                     from_utf8_unchecked_mut(slice::from_raw_parts_mut(ptr, mid)),
+                     from_utf8_unchecked_mut(slice::from_raw_parts_mut(ptr.add(mid), len - mid)),
+                 )
+             }
+         } else {
+             slice_error_fail(self, 0, mid)
+         }
+     }
+ 
+     /// Returns an iterator over the [`char`]s of a string slice.
+     ///
+     /// As a string slice consists of valid UTF-8, we can iterate through a
+     /// string slice by [`char`]. This method returns such an iterator.
+     ///
+     /// It's important to remember that [`char`] represents a Unicode Scalar
+     /// Value, and may not match your idea of what a 'character' is. Iteration
+     /// over grapheme clusters may be what you actually want. This functionality
+     /// is not provided by Rust's standard library, check crates.io instead.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let word = "goodbye";
+     ///
+     /// let count = word.chars().count();
+     /// assert_eq!(7, count);
+     ///
+     /// let mut chars = word.chars();
+     ///
+     /// assert_eq!(Some('g'), chars.next());
+     /// assert_eq!(Some('o'), chars.next());
+     /// assert_eq!(Some('o'), chars.next());
+     /// assert_eq!(Some('d'), chars.next());
+     /// assert_eq!(Some('b'), chars.next());
+     /// assert_eq!(Some('y'), chars.next());
+     /// assert_eq!(Some('e'), chars.next());
+     ///
+     /// assert_eq!(None, chars.next());
+     /// ```
+     ///
+     /// Remember, [`char`]s may not match your intuition about characters:
+     ///
+     /// [`char`]: prim@char
+     ///
+     /// ```
+     /// let y = "y̆";
+     ///
+     /// let mut chars = y.chars();
+     ///
+     /// assert_eq!(Some('y'), chars.next()); // not 'y̆'
+     /// assert_eq!(Some('\u{0306}'), chars.next());
+     ///
+     /// assert_eq!(None, chars.next());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn chars(&self) -> Chars<'_> {
+         Chars { iter: self.as_bytes().iter() }
+     }
+ 
+     /// Returns an iterator over the [`char`]s of a string slice, and their
+     /// positions.
+     ///
+     /// As a string slice consists of valid UTF-8, we can iterate through a
+     /// string slice by [`char`]. This method returns an iterator of both
+     /// these [`char`]s, as well as their byte positions.
+     ///
+     /// The iterator yields tuples. The position is first, the [`char`] is
+     /// second.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let word = "goodbye";
+     ///
+     /// let count = word.char_indices().count();
+     /// assert_eq!(7, count);
+     ///
+     /// let mut char_indices = word.char_indices();
+     ///
+     /// assert_eq!(Some((0, 'g')), char_indices.next());
+     /// assert_eq!(Some((1, 'o')), char_indices.next());
+     /// assert_eq!(Some((2, 'o')), char_indices.next());
+     /// assert_eq!(Some((3, 'd')), char_indices.next());
+     /// assert_eq!(Some((4, 'b')), char_indices.next());
+     /// assert_eq!(Some((5, 'y')), char_indices.next());
+     /// assert_eq!(Some((6, 'e')), char_indices.next());
+     ///
+     /// assert_eq!(None, char_indices.next());
+     /// ```
+     ///
+     /// Remember, [`char`]s may not match your intuition about characters:
+     ///
+     /// [`char`]: prim@char
+     ///
+     /// ```
+     /// let yes = "y̆es";
+     ///
+     /// let mut char_indices = yes.char_indices();
+     ///
+     /// assert_eq!(Some((0, 'y')), char_indices.next()); // not (0, 'y̆')
+     /// assert_eq!(Some((1, '\u{0306}')), char_indices.next());
+     ///
+     /// // note the 3 here - the last character took up two bytes
+     /// assert_eq!(Some((3, 'e')), char_indices.next());
+     /// assert_eq!(Some((4, 's')), char_indices.next());
+     ///
+     /// assert_eq!(None, char_indices.next());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn char_indices(&self) -> CharIndices<'_> {
+         CharIndices { front_offset: 0, iter: self.chars() }
+     }
+ 
+     /// An iterator over the bytes of a string slice.
+     ///
+     /// As a string slice consists of a sequence of bytes, we can iterate
+     /// through a string slice by byte. This method returns such an iterator.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut bytes = "bors".bytes();
+     ///
+     /// assert_eq!(Some(b'b'), bytes.next());
+     /// assert_eq!(Some(b'o'), bytes.next());
+     /// assert_eq!(Some(b'r'), bytes.next());
+     /// assert_eq!(Some(b's'), bytes.next());
+     ///
+     /// assert_eq!(None, bytes.next());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn bytes(&self) -> Bytes<'_> {
+         Bytes(self.as_bytes().iter().copied())
+     }
+ 
+     /// Splits a string slice by whitespace.
+     ///
+     /// The iterator returned will return string slices that are sub-slices of
+     /// the original string slice, separated by any amount of whitespace.
+     ///
+     /// 'Whitespace' is defined according to the terms of the Unicode Derived
+     /// Core Property `White_Space`. If you only want to split on ASCII whitespace
+     /// instead, use [`split_ascii_whitespace`].
+     ///
+     /// [`split_ascii_whitespace`]: str::split_ascii_whitespace
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut iter = "A few words".split_whitespace();
+     ///
+     /// assert_eq!(Some("A"), iter.next());
+     /// assert_eq!(Some("few"), iter.next());
+     /// assert_eq!(Some("words"), iter.next());
+     ///
+     /// assert_eq!(None, iter.next());
+     /// ```
+     ///
+     /// All kinds of whitespace are considered:
+     ///
+     /// ```
+     /// let mut iter = " Mary   had\ta\u{2009}little  \n\t lamb".split_whitespace();
+     /// assert_eq!(Some("Mary"), iter.next());
+     /// assert_eq!(Some("had"), iter.next());
+     /// assert_eq!(Some("a"), iter.next());
+     /// assert_eq!(Some("little"), iter.next());
+     /// assert_eq!(Some("lamb"), iter.next());
+     ///
+     /// assert_eq!(None, iter.next());
+     /// ```
+     #[stable(feature = "split_whitespace", since = "1.1.0")]
+     #[inline]
+     pub fn split_whitespace(&self) -> SplitWhitespace<'_> {
+         SplitWhitespace { inner: self.split(IsWhitespace).filter(IsNotEmpty) }
+     }
+ 
+     /// Splits a string slice by ASCII whitespace.
+     ///
+     /// The iterator returned will return string slices that are sub-slices of
+     /// the original string slice, separated by any amount of ASCII whitespace.
+     ///
+     /// To split by Unicode `Whitespace` instead, use [`split_whitespace`].
+     ///
+     /// [`split_whitespace`]: str::split_whitespace
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let mut iter = "A few words".split_ascii_whitespace();
+     ///
+     /// assert_eq!(Some("A"), iter.next());
+     /// assert_eq!(Some("few"), iter.next());
+     /// assert_eq!(Some("words"), iter.next());
+     ///
+     /// assert_eq!(None, iter.next());
+     /// ```
+     ///
+     /// All kinds of ASCII whitespace are considered:
+     ///
+     /// ```
+     /// let mut iter = " Mary   had\ta little  \n\t lamb".split_ascii_whitespace();
+     /// assert_eq!(Some("Mary"), iter.next());
+     /// assert_eq!(Some("had"), iter.next());
+     /// assert_eq!(Some("a"), iter.next());
+     /// assert_eq!(Some("little"), iter.next());
+     /// assert_eq!(Some("lamb"), iter.next());
+     ///
+     /// assert_eq!(None, iter.next());
+     /// ```
+     #[stable(feature = "split_ascii_whitespace", since = "1.34.0")]
+     #[inline]
+     pub fn split_ascii_whitespace(&self) -> SplitAsciiWhitespace<'_> {
+         let inner =
+             self.as_bytes().split(IsAsciiWhitespace).filter(BytesIsNotEmpty).map(UnsafeBytesToStr);
+         SplitAsciiWhitespace { inner }
+     }
+ 
+     /// An iterator over the lines of a string, as string slices.
+     ///
+     /// Lines are ended with either a newline (`\n`) or a carriage return with
+     /// a line feed (`\r\n`).
+     ///
+     /// The final line ending is optional. A string that ends with a final line
+     /// ending will return the same lines as an otherwise identical string
+     /// without a final line ending.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let text = "foo\r\nbar\n\nbaz\n";
+     /// let mut lines = text.lines();
+     ///
+     /// assert_eq!(Some("foo"), lines.next());
+     /// assert_eq!(Some("bar"), lines.next());
+     /// assert_eq!(Some(""), lines.next());
+     /// assert_eq!(Some("baz"), lines.next());
+     ///
+     /// assert_eq!(None, lines.next());
+     /// ```
+     ///
+     /// The final line ending isn't required:
+     ///
+     /// ```
+     /// let text = "foo\nbar\n\r\nbaz";
+     /// let mut lines = text.lines();
+     ///
+     /// assert_eq!(Some("foo"), lines.next());
+     /// assert_eq!(Some("bar"), lines.next());
+     /// assert_eq!(Some(""), lines.next());
+     /// assert_eq!(Some("baz"), lines.next());
+     ///
+     /// assert_eq!(None, lines.next());
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn lines(&self) -> Lines<'_> {
+         Lines(self.split_terminator('\n').map(LinesAnyMap))
+     }
+ 
+     /// An iterator over the lines of a string.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(since = "1.4.0", reason = "use lines() instead now")]
+     #[inline]
+     #[allow(deprecated)]
+     pub fn lines_any(&self) -> LinesAny<'_> {
+         LinesAny(self.lines())
+     }
+ 
+     /// Returns an iterator of `u16` over the string encoded as UTF-16.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let text = "Zażółć gęślą jaźń";
+     ///
+     /// let utf8_len = text.len();
+     /// let utf16_len = text.encode_utf16().count();
+     ///
+     /// assert!(utf16_len <= utf8_len);
+     /// ```
+     #[stable(feature = "encode_utf16", since = "1.8.0")]
+     pub fn encode_utf16(&self) -> EncodeUtf16<'_> {
+         EncodeUtf16 { chars: self.chars(), extra: 0 }
+     }
+ 
+     /// Returns `true` if the given pattern matches a sub-slice of
+     /// this string slice.
+     ///
+     /// Returns `false` if it does not.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let bananas = "bananas";
+     ///
+     /// assert!(bananas.contains("nana"));
+     /// assert!(!bananas.contains("apples"));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn contains<'a, P: Pattern<'a>>(&'a self, pat: P) -> bool {
+         pat.is_contained_in(self)
+     }
+ 
+     /// Returns `true` if the given pattern matches a prefix of this
+     /// string slice.
+     ///
+     /// Returns `false` if it does not.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let bananas = "bananas";
+     ///
+     /// assert!(bananas.starts_with("bana"));
+     /// assert!(!bananas.starts_with("nana"));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn starts_with<'a, P: Pattern<'a>>(&'a self, pat: P) -> bool {
+         pat.is_prefix_of(self)
+     }
+ 
+     /// Returns `true` if the given pattern matches a suffix of this
+     /// string slice.
+     ///
+     /// Returns `false` if it does not.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let bananas = "bananas";
+     ///
+     /// assert!(bananas.ends_with("anas"));
+     /// assert!(!bananas.ends_with("nana"));
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn ends_with<'a, P>(&'a self, pat: P) -> bool
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         pat.is_suffix_of(self)
+     }
+ 
+     /// Returns the byte index of the first character of this string slice that
+     /// matches the pattern.
+     ///
+     /// Returns [`None`] if the pattern doesn't match.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard Gepardi";
+     ///
+     /// assert_eq!(s.find('L'), Some(0));
+     /// assert_eq!(s.find('é'), Some(14));
+     /// assert_eq!(s.find("pard"), Some(17));
+     /// ```
+     ///
+     /// More complex patterns using point-free style and closures:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard";
+     ///
+     /// assert_eq!(s.find(char::is_whitespace), Some(5));
+     /// assert_eq!(s.find(char::is_lowercase), Some(1));
+     /// assert_eq!(s.find(|c: char| c.is_whitespace() || c.is_lowercase()), Some(1));
+     /// assert_eq!(s.find(|c: char| (c < 'o') && (c > 'a')), Some(4));
+     /// ```
+     ///
+     /// Not finding the pattern:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard";
+     /// let x: &[_] = &['1', '2'];
+     ///
+     /// assert_eq!(s.find(x), None);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn find<'a, P: Pattern<'a>>(&'a self, pat: P) -> Option<usize> {
+         pat.into_searcher(self).next_match().map(|(i, _)| i)
+     }
+ 
+     /// Returns the byte index for the first character of the rightmost match of the pattern in
+     /// this string slice.
+     ///
+     /// Returns [`None`] if the pattern doesn't match.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard Gepardi";
+     ///
+     /// assert_eq!(s.rfind('L'), Some(13));
+     /// assert_eq!(s.rfind('é'), Some(14));
+     /// assert_eq!(s.rfind("pard"), Some(24));
+     /// ```
+     ///
+     /// More complex patterns with closures:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard";
+     ///
+     /// assert_eq!(s.rfind(char::is_whitespace), Some(12));
+     /// assert_eq!(s.rfind(char::is_lowercase), Some(20));
+     /// ```
+     ///
+     /// Not finding the pattern:
+     ///
+     /// ```
+     /// let s = "Löwe 老虎 Léopard";
+     /// let x: &[_] = &['1', '2'];
+     ///
+     /// assert_eq!(s.rfind(x), None);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn rfind<'a, P>(&'a self, pat: P) -> Option<usize>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         pat.into_searcher(self).next_match_back().map(|(i, _)| i)
+     }
+ 
+     /// An iterator over substrings of this string slice, separated by
+     /// characters matched by a pattern.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator will be a [`DoubleEndedIterator`] if the pattern
+     /// allows a reverse search and forward/reverse search yields the same
+     /// elements. This is true for, e.g., [`char`], but not for `&str`.
+     ///
+     /// If the pattern allows a reverse search but its results might differ
+     /// from a forward search, the [`rsplit`] method can be used.
+     ///
+     /// [`rsplit`]: str::rsplit
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "Mary had a little lamb".split(' ').collect();
+     /// assert_eq!(v, ["Mary", "had", "a", "little", "lamb"]);
+     ///
+     /// let v: Vec<&str> = "".split('X').collect();
+     /// assert_eq!(v, [""]);
+     ///
+     /// let v: Vec<&str> = "lionXXtigerXleopard".split('X').collect();
+     /// assert_eq!(v, ["lion", "", "tiger", "leopard"]);
+     ///
+     /// let v: Vec<&str> = "lion::tiger::leopard".split("::").collect();
+     /// assert_eq!(v, ["lion", "tiger", "leopard"]);
+     ///
+     /// let v: Vec<&str> = "abc1def2ghi".split(char::is_numeric).collect();
+     /// assert_eq!(v, ["abc", "def", "ghi"]);
+     ///
+     /// let v: Vec<&str> = "lionXtigerXleopard".split(char::is_uppercase).collect();
+     /// assert_eq!(v, ["lion", "tiger", "leopard"]);
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "abc1defXghi".split(|c| c == '1' || c == 'X').collect();
+     /// assert_eq!(v, ["abc", "def", "ghi"]);
+     /// ```
+     ///
+     /// If a string contains multiple contiguous separators, you will end up
+     /// with empty strings in the output:
+     ///
+     /// ```
+     /// let x = "||||a||b|c".to_string();
+     /// let d: Vec<_> = x.split('|').collect();
+     ///
+     /// assert_eq!(d, &["", "", "", "", "a", "", "b", "c"]);
+     /// ```
+     ///
+     /// Contiguous separators are separated by the empty string.
+     ///
+     /// ```
+     /// let x = "(///)".to_string();
+     /// let d: Vec<_> = x.split('/').collect();
+     ///
+     /// assert_eq!(d, &["(", "", "", ")"]);
+     /// ```
+     ///
+     /// Separators at the start or end of a string are neighbored
+     /// by empty strings.
+     ///
+     /// ```
+     /// let d: Vec<_> = "010".split("0").collect();
+     /// assert_eq!(d, &["", "1", ""]);
+     /// ```
+     ///
+     /// When the empty string is used as a separator, it separates
+     /// every character in the string, along with the beginning
+     /// and end of the string.
+     ///
+     /// ```
+     /// let f: Vec<_> = "rust".split("").collect();
+     /// assert_eq!(f, &["", "r", "u", "s", "t", ""]);
+     /// ```
+     ///
+     /// Contiguous separators can lead to possibly surprising behavior
+     /// when whitespace is used as the separator. This code is correct:
+     ///
+     /// ```
+     /// let x = "    a  b c".to_string();
+     /// let d: Vec<_> = x.split(' ').collect();
+     ///
+     /// assert_eq!(d, &["", "", "", "", "a", "", "b", "c"]);
+     /// ```
+     ///
+     /// It does _not_ give you:
+     ///
+     /// ```,ignore
+     /// assert_eq!(d, &["a", "b", "c"]);
+     /// ```
+     ///
+     /// Use [`split_whitespace`] for this behavior.
+     ///
+     /// [`split_whitespace`]: str::split_whitespace
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn split<'a, P: Pattern<'a>>(&'a self, pat: P) -> Split<'a, P> {
+         Split(SplitInternal {
+             start: 0,
+             end: self.len(),
+             matcher: pat.into_searcher(self),
+             allow_trailing_empty: true,
+             finished: false,
+         })
+     }
+ 
+     /// An iterator over substrings of this string slice, separated by
+     /// characters matched by a pattern. Differs from the iterator produced by
+     /// `split` in that `split_inclusive` leaves the matched part as the
+     /// terminator of the substring.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(split_inclusive)]
+     /// let v: Vec<&str> = "Mary had a little lamb\nlittle lamb\nlittle lamb."
+     ///     .split_inclusive('\n').collect();
+     /// assert_eq!(v, ["Mary had a little lamb\n", "little lamb\n", "little lamb."]);
+     /// ```
+     ///
+     /// If the last element of the string is matched,
+     /// that element will be considered the terminator of the preceding substring.
+     /// That substring will be the last item returned by the iterator.
+     ///
+     /// ```
+     /// #![feature(split_inclusive)]
+     /// let v: Vec<&str> = "Mary had a little lamb\nlittle lamb\nlittle lamb.\n"
+     ///     .split_inclusive('\n').collect();
+     /// assert_eq!(v, ["Mary had a little lamb\n", "little lamb\n", "little lamb.\n"]);
+     /// ```
+     #[unstable(feature = "split_inclusive", issue = "72360")]
+     #[inline]
+     pub fn split_inclusive<'a, P: Pattern<'a>>(&'a self, pat: P) -> SplitInclusive<'a, P> {
+         SplitInclusive(SplitInternal {
+             start: 0,
+             end: self.len(),
+             matcher: pat.into_searcher(self),
+             allow_trailing_empty: false,
+             finished: false,
+         })
+     }
+ 
+     /// An iterator over substrings of the given string slice, separated by
+     /// characters matched by a pattern and yielded in reverse order.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator requires that the pattern supports a reverse
+     /// search, and it will be a [`DoubleEndedIterator`] if a forward/reverse
+     /// search yields the same elements.
+     ///
+     /// For iterating from the front, the [`split`] method can be used.
+     ///
+     /// [`split`]: str::split
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "Mary had a little lamb".rsplit(' ').collect();
+     /// assert_eq!(v, ["lamb", "little", "a", "had", "Mary"]);
+     ///
+     /// let v: Vec<&str> = "".rsplit('X').collect();
+     /// assert_eq!(v, [""]);
+     ///
+     /// let v: Vec<&str> = "lionXXtigerXleopard".rsplit('X').collect();
+     /// assert_eq!(v, ["leopard", "tiger", "", "lion"]);
+     ///
+     /// let v: Vec<&str> = "lion::tiger::leopard".rsplit("::").collect();
+     /// assert_eq!(v, ["leopard", "tiger", "lion"]);
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "abc1defXghi".rsplit(|c| c == '1' || c == 'X').collect();
+     /// assert_eq!(v, ["ghi", "def", "abc"]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn rsplit<'a, P>(&'a self, pat: P) -> RSplit<'a, P>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         RSplit(self.split(pat).0)
+     }
+ 
+     /// An iterator over substrings of the given string slice, separated by
+     /// characters matched by a pattern.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// Equivalent to [`split`], except that the trailing substring
+     /// is skipped if empty.
+     ///
+     /// [`split`]: str::split
+     ///
+     /// This method can be used for string data that is _terminated_,
+     /// rather than _separated_ by a pattern.
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator will be a [`DoubleEndedIterator`] if the pattern
+     /// allows a reverse search and forward/reverse search yields the same
+     /// elements. This is true for, e.g., [`char`], but not for `&str`.
+     ///
+     /// If the pattern allows a reverse search but its results might differ
+     /// from a forward search, the [`rsplit_terminator`] method can be used.
+     ///
+     /// [`rsplit_terminator`]: str::rsplit_terminator
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "A.B.".split_terminator('.').collect();
+     /// assert_eq!(v, ["A", "B"]);
+     ///
+     /// let v: Vec<&str> = "A..B..".split_terminator(".").collect();
+     /// assert_eq!(v, ["A", "", "B", ""]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn split_terminator<'a, P: Pattern<'a>>(&'a self, pat: P) -> SplitTerminator<'a, P> {
+         SplitTerminator(SplitInternal { allow_trailing_empty: false, ..self.split(pat).0 })
+     }
+ 
+     /// An iterator over substrings of `self`, separated by characters
+     /// matched by a pattern and yielded in reverse order.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// Equivalent to [`split`], except that the trailing substring is
+     /// skipped if empty.
+     ///
+     /// [`split`]: str::split
+     ///
+     /// This method can be used for string data that is _terminated_,
+     /// rather than _separated_ by a pattern.
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator requires that the pattern supports a
+     /// reverse search, and it will be double ended if a forward/reverse
+     /// search yields the same elements.
+     ///
+     /// For iterating from the front, the [`split_terminator`] method can be
+     /// used.
+     ///
+     /// [`split_terminator`]: str::split_terminator
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let v: Vec<&str> = "A.B.".rsplit_terminator('.').collect();
+     /// assert_eq!(v, ["B", "A"]);
+     ///
+     /// let v: Vec<&str> = "A..B..".rsplit_terminator(".").collect();
+     /// assert_eq!(v, ["", "B", "", "A"]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn rsplit_terminator<'a, P>(&'a self, pat: P) -> RSplitTerminator<'a, P>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         RSplitTerminator(self.split_terminator(pat).0)
+     }
+ 
+     /// An iterator over substrings of the given string slice, separated by a
+     /// pattern, restricted to returning at most `n` items.
+     ///
+     /// If `n` substrings are returned, the last substring (the `n`th substring)
+     /// will contain the remainder of the string.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator will not be double ended, because it is
+     /// not efficient to support.
+     ///
+     /// If the pattern allows a reverse search, the [`rsplitn`] method can be
+     /// used.
+     ///
+     /// [`rsplitn`]: str::rsplitn
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "Mary had a little lambda".splitn(3, ' ').collect();
+     /// assert_eq!(v, ["Mary", "had", "a little lambda"]);
+     ///
+     /// let v: Vec<&str> = "lionXXtigerXleopard".splitn(3, "X").collect();
+     /// assert_eq!(v, ["lion", "", "tigerXleopard"]);
+     ///
+     /// let v: Vec<&str> = "abcXdef".splitn(1, 'X').collect();
+     /// assert_eq!(v, ["abcXdef"]);
+     ///
+     /// let v: Vec<&str> = "".splitn(1, 'X').collect();
+     /// assert_eq!(v, [""]);
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "abc1defXghi".splitn(2, |c| c == '1' || c == 'X').collect();
+     /// assert_eq!(v, ["abc", "defXghi"]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn splitn<'a, P: Pattern<'a>>(&'a self, n: usize, pat: P) -> SplitN<'a, P> {
+         SplitN(SplitNInternal { iter: self.split(pat).0, count: n })
+     }
+ 
+     /// An iterator over substrings of this string slice, separated by a
+     /// pattern, starting from the end of the string, restricted to returning
+     /// at most `n` items.
+     ///
+     /// If `n` substrings are returned, the last substring (the `n`th substring)
+     /// will contain the remainder of the string.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator will not be double ended, because it is not
+     /// efficient to support.
+     ///
+     /// For splitting from the front, the [`splitn`] method can be used.
+     ///
+     /// [`splitn`]: str::splitn
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "Mary had a little lamb".rsplitn(3, ' ').collect();
+     /// assert_eq!(v, ["lamb", "little", "Mary had a"]);
+     ///
+     /// let v: Vec<&str> = "lionXXtigerXleopard".rsplitn(3, 'X').collect();
+     /// assert_eq!(v, ["leopard", "tiger", "lionX"]);
+     ///
+     /// let v: Vec<&str> = "lion::tiger::leopard".rsplitn(2, "::").collect();
+     /// assert_eq!(v, ["leopard", "lion::tiger"]);
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "abc1defXghi".rsplitn(2, |c| c == '1' || c == 'X').collect();
+     /// assert_eq!(v, ["ghi", "abc1def"]);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[inline]
+     pub fn rsplitn<'a, P>(&'a self, n: usize, pat: P) -> RSplitN<'a, P>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         RSplitN(self.splitn(n, pat).0)
+     }
+ 
+     /// Splits the string on the first occurrence of the specified delimiter and
+     /// returns prefix before delimiter and suffix after delimiter.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_once)]
+     ///
+     /// assert_eq!("cfg".split_once('='), None);
+     /// assert_eq!("cfg=foo".split_once('='), Some(("cfg", "foo")));
+     /// assert_eq!("cfg=foo=bar".split_once('='), Some(("cfg", "foo=bar")));
+     /// ```
+     #[unstable(feature = "str_split_once", reason = "newly added", issue = "74773")]
+     #[inline]
+     pub fn split_once<'a, P: Pattern<'a>>(&'a self, delimiter: P) -> Option<(&'a str, &'a str)> {
+         let (start, end) = delimiter.into_searcher(self).next_match()?;
+         Some((&self[..start], &self[end..]))
+     }
+ 
+     /// Splits the string on the last occurrence of the specified delimiter and
+     /// returns prefix before delimiter and suffix after delimiter.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(str_split_once)]
+     ///
+     /// assert_eq!("cfg".rsplit_once('='), None);
+     /// assert_eq!("cfg=foo".rsplit_once('='), Some(("cfg", "foo")));
+     /// assert_eq!("cfg=foo=bar".rsplit_once('='), Some(("cfg=foo", "bar")));
+     /// ```
+     #[unstable(feature = "str_split_once", reason = "newly added", issue = "74773")]
+     #[inline]
+     pub fn rsplit_once<'a, P>(&'a self, delimiter: P) -> Option<(&'a str, &'a str)>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         let (start, end) = delimiter.into_searcher(self).next_match_back()?;
+         Some((&self[..start], &self[end..]))
+     }
+ 
+     /// An iterator over the disjoint matches of a pattern within the given string
+     /// slice.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator will be a [`DoubleEndedIterator`] if the pattern
+     /// allows a reverse search and forward/reverse search yields the same
+     /// elements. This is true for, e.g., [`char`], but not for `&str`.
+     ///
+     /// If the pattern allows a reverse search but its results might differ
+     /// from a forward search, the [`rmatches`] method can be used.
+     ///
+     /// [`rmatches`]: str::matches
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "abcXXXabcYYYabc".matches("abc").collect();
+     /// assert_eq!(v, ["abc", "abc", "abc"]);
+     ///
+     /// let v: Vec<&str> = "1abc2abc3".matches(char::is_numeric).collect();
+     /// assert_eq!(v, ["1", "2", "3"]);
+     /// ```
+     #[stable(feature = "str_matches", since = "1.2.0")]
+     #[inline]
+     pub fn matches<'a, P: Pattern<'a>>(&'a self, pat: P) -> Matches<'a, P> {
+         Matches(MatchesInternal(pat.into_searcher(self)))
+     }
+ 
+     /// An iterator over the disjoint matches of a pattern within this string slice,
+     /// yielded in reverse order.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator requires that the pattern supports a reverse
+     /// search, and it will be a [`DoubleEndedIterator`] if a forward/reverse
+     /// search yields the same elements.
+     ///
+     /// For iterating from the front, the [`matches`] method can be used.
+     ///
+     /// [`matches`]: str::matches
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let v: Vec<&str> = "abcXXXabcYYYabc".rmatches("abc").collect();
+     /// assert_eq!(v, ["abc", "abc", "abc"]);
+     ///
+     /// let v: Vec<&str> = "1abc2abc3".rmatches(char::is_numeric).collect();
+     /// assert_eq!(v, ["3", "2", "1"]);
+     /// ```
+     #[stable(feature = "str_matches", since = "1.2.0")]
+     #[inline]
+     pub fn rmatches<'a, P>(&'a self, pat: P) -> RMatches<'a, P>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         RMatches(self.matches(pat).0)
+     }
+ 
+     /// An iterator over the disjoint matches of a pattern within this string
+     /// slice as well as the index that the match starts at.
+     ///
+     /// For matches of `pat` within `self` that overlap, only the indices
+     /// corresponding to the first match are returned.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator will be a [`DoubleEndedIterator`] if the pattern
+     /// allows a reverse search and forward/reverse search yields the same
+     /// elements. This is true for, e.g., [`char`], but not for `&str`.
+     ///
+     /// If the pattern allows a reverse search but its results might differ
+     /// from a forward search, the [`rmatch_indices`] method can be used.
+     ///
+     /// [`rmatch_indices`]: str::match_indices
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let v: Vec<_> = "abcXXXabcYYYabc".match_indices("abc").collect();
+     /// assert_eq!(v, [(0, "abc"), (6, "abc"), (12, "abc")]);
+     ///
+     /// let v: Vec<_> = "1abcabc2".match_indices("abc").collect();
+     /// assert_eq!(v, [(1, "abc"), (4, "abc")]);
+     ///
+     /// let v: Vec<_> = "ababa".match_indices("aba").collect();
+     /// assert_eq!(v, [(0, "aba")]); // only the first `aba`
+     /// ```
+     #[stable(feature = "str_match_indices", since = "1.5.0")]
+     #[inline]
+     pub fn match_indices<'a, P: Pattern<'a>>(&'a self, pat: P) -> MatchIndices<'a, P> {
+         MatchIndices(MatchIndicesInternal(pat.into_searcher(self)))
+     }
+ 
+     /// An iterator over the disjoint matches of a pattern within `self`,
+     /// yielded in reverse order along with the index of the match.
+     ///
+     /// For matches of `pat` within `self` that overlap, only the indices
+     /// corresponding to the last match are returned.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Iterator behavior
+     ///
+     /// The returned iterator requires that the pattern supports a reverse
+     /// search, and it will be a [`DoubleEndedIterator`] if a forward/reverse
+     /// search yields the same elements.
+     ///
+     /// For iterating from the front, the [`match_indices`] method can be used.
+     ///
+     /// [`match_indices`]: str::match_indices
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let v: Vec<_> = "abcXXXabcYYYabc".rmatch_indices("abc").collect();
+     /// assert_eq!(v, [(12, "abc"), (6, "abc"), (0, "abc")]);
+     ///
+     /// let v: Vec<_> = "1abcabc2".rmatch_indices("abc").collect();
+     /// assert_eq!(v, [(4, "abc"), (1, "abc")]);
+     ///
+     /// let v: Vec<_> = "ababa".rmatch_indices("aba").collect();
+     /// assert_eq!(v, [(2, "aba")]); // only the last `aba`
+     /// ```
+     #[stable(feature = "str_match_indices", since = "1.5.0")]
+     #[inline]
+     pub fn rmatch_indices<'a, P>(&'a self, pat: P) -> RMatchIndices<'a, P>
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         RMatchIndices(self.match_indices(pat).0)
+     }
+ 
+     /// Returns a string slice with leading and trailing whitespace removed.
+     ///
+     /// 'Whitespace' is defined according to the terms of the Unicode Derived
+     /// Core Property `White_Space`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = " Hello\tworld\t";
+     ///
+     /// assert_eq!("Hello\tworld", s.trim());
+     /// ```
+     #[inline]
+     #[must_use = "this returns the trimmed string as a slice, \
+                   without modifying the original"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn trim(&self) -> &str {
+         self.trim_matches(|c: char| c.is_whitespace())
+     }
+ 
+     /// Returns a string slice with leading whitespace removed.
+     ///
+     /// 'Whitespace' is defined according to the terms of the Unicode Derived
+     /// Core Property `White_Space`.
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. `start` in this context means the first
+     /// position of that byte string; for a left-to-right language like English or
+     /// Russian, this will be left side, and for right-to-left languages like
+     /// Arabic or Hebrew, this will be the right side.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = " Hello\tworld\t";
+     /// assert_eq!("Hello\tworld\t", s.trim_start());
+     /// ```
+     ///
+     /// Directionality:
+     ///
+     /// ```
+     /// let s = "  English  ";
+     /// assert!(Some('E') == s.trim_start().chars().next());
+     ///
+     /// let s = "  עברית  ";
+     /// assert!(Some('ע') == s.trim_start().chars().next());
+     /// ```
+     #[inline]
+     #[must_use = "this returns the trimmed string as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "trim_direction", since = "1.30.0")]
+     pub fn trim_start(&self) -> &str {
+         self.trim_start_matches(|c: char| c.is_whitespace())
+     }
+ 
+     /// Returns a string slice with trailing whitespace removed.
+     ///
+     /// 'Whitespace' is defined according to the terms of the Unicode Derived
+     /// Core Property `White_Space`.
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. `end` in this context means the last
+     /// position of that byte string; for a left-to-right language like English or
+     /// Russian, this will be right side, and for right-to-left languages like
+     /// Arabic or Hebrew, this will be the left side.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = " Hello\tworld\t";
+     /// assert_eq!(" Hello\tworld", s.trim_end());
+     /// ```
+     ///
+     /// Directionality:
+     ///
+     /// ```
+     /// let s = "  English  ";
+     /// assert!(Some('h') == s.trim_end().chars().rev().next());
+     ///
+     /// let s = "  עברית  ";
+     /// assert!(Some('ת') == s.trim_end().chars().rev().next());
+     /// ```
+     #[inline]
+     #[must_use = "this returns the trimmed string as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "trim_direction", since = "1.30.0")]
+     pub fn trim_end(&self) -> &str {
+         self.trim_end_matches(|c: char| c.is_whitespace())
+     }
+ 
+     /// Returns a string slice with leading whitespace removed.
+     ///
+     /// 'Whitespace' is defined according to the terms of the Unicode Derived
+     /// Core Property `White_Space`.
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. 'Left' in this context means the first
+     /// position of that byte string; for a language like Arabic or Hebrew
+     /// which are 'right to left' rather than 'left to right', this will be
+     /// the _right_ side, not the left.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = " Hello\tworld\t";
+     ///
+     /// assert_eq!("Hello\tworld\t", s.trim_left());
+     /// ```
+     ///
+     /// Directionality:
+     ///
+     /// ```
+     /// let s = "  English";
+     /// assert!(Some('E') == s.trim_left().chars().next());
+     ///
+     /// let s = "  עברית";
+     /// assert!(Some('ע') == s.trim_left().chars().next());
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.33.0",
+         reason = "superseded by `trim_start`",
+         suggestion = "trim_start"
+     )]
+     pub fn trim_left(&self) -> &str {
+         self.trim_start()
+     }
+ 
+     /// Returns a string slice with trailing whitespace removed.
+     ///
+     /// 'Whitespace' is defined according to the terms of the Unicode Derived
+     /// Core Property `White_Space`.
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. 'Right' in this context means the last
+     /// position of that byte string; for a language like Arabic or Hebrew
+     /// which are 'right to left' rather than 'left to right', this will be
+     /// the _left_ side, not the right.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// let s = " Hello\tworld\t";
+     ///
+     /// assert_eq!(" Hello\tworld", s.trim_right());
+     /// ```
+     ///
+     /// Directionality:
+     ///
+     /// ```
+     /// let s = "English  ";
+     /// assert!(Some('h') == s.trim_right().chars().rev().next());
+     ///
+     /// let s = "עברית  ";
+     /// assert!(Some('ת') == s.trim_right().chars().rev().next());
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.33.0",
+         reason = "superseded by `trim_end`",
+         suggestion = "trim_end"
+     )]
+     pub fn trim_right(&self) -> &str {
+         self.trim_end()
+     }
+ 
+     /// Returns a string slice with all prefixes and suffixes that match a
+     /// pattern repeatedly removed.
+     ///
+     /// The [pattern] can be a [`char`], a slice of [`char`]s, or a function
+     /// or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// assert_eq!("11foo1bar11".trim_matches('1'), "foo1bar");
+     /// assert_eq!("123foo1bar123".trim_matches(char::is_numeric), "foo1bar");
+     ///
+     /// let x: &[_] = &['1', '2'];
+     /// assert_eq!("12foo1bar12".trim_matches(x), "foo1bar");
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// assert_eq!("1foo1barXX".trim_matches(|c| c == '1' || c == 'X'), "foo1bar");
+     /// ```
+     #[must_use = "this returns the trimmed string as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn trim_matches<'a, P>(&'a self, pat: P) -> &'a str
+     where
+         P: Pattern<'a, Searcher: DoubleEndedSearcher<'a>>,
+     {
+         let mut i = 0;
+         let mut j = 0;
+         let mut matcher = pat.into_searcher(self);
+         if let Some((a, b)) = matcher.next_reject() {
+             i = a;
+             j = b; // Remember earliest known match, correct it below if
+             // last match is different
+         }
+         if let Some((_, b)) = matcher.next_reject_back() {
+             j = b;
+         }
+         // SAFETY: `Searcher` is known to return valid indices.
+         unsafe { self.get_unchecked(i..j) }
+     }
+ 
+     /// Returns a string slice with all prefixes that match a pattern
+     /// repeatedly removed.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. `start` in this context means the first
+     /// position of that byte string; for a left-to-right language like English or
+     /// Russian, this will be left side, and for right-to-left languages like
+     /// Arabic or Hebrew, this will be the right side.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert_eq!("11foo1bar11".trim_start_matches('1'), "foo1bar11");
+     /// assert_eq!("123foo1bar123".trim_start_matches(char::is_numeric), "foo1bar123");
+     ///
+     /// let x: &[_] = &['1', '2'];
+     /// assert_eq!("12foo1bar12".trim_start_matches(x), "foo1bar12");
+     /// ```
+     #[must_use = "this returns the trimmed string as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "trim_direction", since = "1.30.0")]
+     pub fn trim_start_matches<'a, P: Pattern<'a>>(&'a self, pat: P) -> &'a str {
+         let mut i = self.len();
+         let mut matcher = pat.into_searcher(self);
+         if let Some((a, _)) = matcher.next_reject() {
+             i = a;
+         }
+         // SAFETY: `Searcher` is known to return valid indices.
+         unsafe { self.get_unchecked(i..self.len()) }
+     }
+ 
+     /// Returns a string slice with the prefix removed.
+     ///
+     /// If the string starts with the pattern `prefix`, returns substring after the prefix, wrapped
+     /// in `Some`.  Unlike `trim_start_matches`, this method removes the prefix exactly once.
+     ///
+     /// If the string does not start with `prefix`, returns `None`.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!("foo:bar".strip_prefix("foo:"), Some("bar"));
+     /// assert_eq!("foo:bar".strip_prefix("bar"), None);
+     /// assert_eq!("foofoo".strip_prefix("foo"), Some("foo"));
+     /// ```
+     #[must_use = "this returns the remaining substring as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "str_strip", since = "1.45.0")]
+     pub fn strip_prefix<'a, P: Pattern<'a>>(&'a self, prefix: P) -> Option<&'a str> {
+         prefix.strip_prefix_of(self)
+     }
+ 
+     /// Returns a string slice with the suffix removed.
+     ///
+     /// If the string ends with the pattern `suffix`, returns the substring before the suffix,
+     /// wrapped in `Some`.  Unlike `trim_end_matches`, this method removes the suffix exactly once.
+     ///
+     /// If the string does not end with `suffix`, returns `None`.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert_eq!("bar:foo".strip_suffix(":foo"), Some("bar"));
+     /// assert_eq!("bar:foo".strip_suffix("bar"), None);
+     /// assert_eq!("foofoo".strip_suffix("foo"), Some("foo"));
+     /// ```
+     #[must_use = "this returns the remaining substring as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "str_strip", since = "1.45.0")]
+     pub fn strip_suffix<'a, P>(&'a self, suffix: P) -> Option<&'a str>
+     where
+         P: Pattern<'a>,
+         <P as Pattern<'a>>::Searcher: ReverseSearcher<'a>,
+     {
+         suffix.strip_suffix_of(self)
+     }
+ 
+     /// Returns a string slice with all suffixes that match a pattern
+     /// repeatedly removed.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. `end` in this context means the last
+     /// position of that byte string; for a left-to-right language like English or
+     /// Russian, this will be right side, and for right-to-left languages like
+     /// Arabic or Hebrew, this will be the left side.
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// assert_eq!("11foo1bar11".trim_end_matches('1'), "11foo1bar");
+     /// assert_eq!("123foo1bar123".trim_end_matches(char::is_numeric), "123foo1bar");
+     ///
+     /// let x: &[_] = &['1', '2'];
+     /// assert_eq!("12foo1bar12".trim_end_matches(x), "12foo1bar");
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// assert_eq!("1fooX".trim_end_matches(|c| c == '1' || c == 'X'), "1foo");
+     /// ```
+     #[must_use = "this returns the trimmed string as a new slice, \
+                   without modifying the original"]
+     #[stable(feature = "trim_direction", since = "1.30.0")]
+     pub fn trim_end_matches<'a, P>(&'a self, pat: P) -> &'a str
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         let mut j = 0;
+         let mut matcher = pat.into_searcher(self);
+         if let Some((_, b)) = matcher.next_reject_back() {
+             j = b;
+         }
+         // SAFETY: `Searcher` is known to return valid indices.
+         unsafe { self.get_unchecked(0..j) }
+     }
+ 
+     /// Returns a string slice with all prefixes that match a pattern
+     /// repeatedly removed.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. 'Left' in this context means the first
+     /// position of that byte string; for a language like Arabic or Hebrew
+     /// which are 'right to left' rather than 'left to right', this will be
+     /// the _right_ side, not the left.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// assert_eq!("11foo1bar11".trim_left_matches('1'), "foo1bar11");
+     /// assert_eq!("123foo1bar123".trim_left_matches(char::is_numeric), "foo1bar123");
+     ///
+     /// let x: &[_] = &['1', '2'];
+     /// assert_eq!("12foo1bar12".trim_left_matches(x), "foo1bar12");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.33.0",
+         reason = "superseded by `trim_start_matches`",
+         suggestion = "trim_start_matches"
+     )]
+     pub fn trim_left_matches<'a, P: Pattern<'a>>(&'a self, pat: P) -> &'a str {
+         self.trim_start_matches(pat)
+     }
+ 
+     /// Returns a string slice with all suffixes that match a pattern
+     /// repeatedly removed.
+     ///
+     /// The [pattern] can be a `&str`, [`char`], a slice of [`char`]s, or a
+     /// function or closure that determines if a character matches.
+     ///
+     /// [`char`]: prim@char
+     /// [pattern]: self::pattern
+     ///
+     /// # Text directionality
+     ///
+     /// A string is a sequence of bytes. 'Right' in this context means the last
+     /// position of that byte string; for a language like Arabic or Hebrew
+     /// which are 'right to left' rather than 'left to right', this will be
+     /// the _left_ side, not the right.
+     ///
+     /// # Examples
+     ///
+     /// Simple patterns:
+     ///
+     /// ```
+     /// assert_eq!("11foo1bar11".trim_right_matches('1'), "11foo1bar");
+     /// assert_eq!("123foo1bar123".trim_right_matches(char::is_numeric), "123foo1bar");
+     ///
+     /// let x: &[_] = &['1', '2'];
+     /// assert_eq!("12foo1bar12".trim_right_matches(x), "12foo1bar");
+     /// ```
+     ///
+     /// A more complex pattern, using a closure:
+     ///
+     /// ```
+     /// assert_eq!("1fooX".trim_right_matches(|c| c == '1' || c == 'X'), "1foo");
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_deprecated(
+         since = "1.33.0",
+         reason = "superseded by `trim_end_matches`",
+         suggestion = "trim_end_matches"
+     )]
+     pub fn trim_right_matches<'a, P>(&'a self, pat: P) -> &'a str
+     where
+         P: Pattern<'a, Searcher: ReverseSearcher<'a>>,
+     {
+         self.trim_end_matches(pat)
+     }
+ 
+     /// Parses this string slice into another type.
+     ///
+     /// Because `parse` is so general, it can cause problems with type
+     /// inference. As such, `parse` is one of the few times you'll see
+     /// the syntax affectionately known as the 'turbofish': `::<>`. This
+     /// helps the inference algorithm understand specifically which type
+     /// you're trying to parse into.
+     ///
+     /// `parse` can parse any type that implements the [`FromStr`] trait.
+ 
+     ///
+     /// # Errors
+     ///
+     /// Will return [`Err`] if it's not possible to parse this string slice into
+     /// the desired type.
+     ///
+     /// [`Err`]: FromStr::Err
+     ///
+     /// # Examples
+     ///
+     /// Basic usage
+     ///
+     /// ```
+     /// let four: u32 = "4".parse().unwrap();
+     ///
+     /// assert_eq!(4, four);
+     /// ```
+     ///
+     /// Using the 'turbofish' instead of annotating `four`:
+     ///
+     /// ```
+     /// let four = "4".parse::<u32>();
+     ///
+     /// assert_eq!(Ok(4), four);
+     /// ```
+     ///
+     /// Failing to parse:
+     ///
+     /// ```
+     /// let nope = "j".parse::<u32>();
+     ///
+     /// assert!(nope.is_err());
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn parse<F: FromStr>(&self) -> Result<F, F::Err> {
+         FromStr::from_str(self)
+     }
+ 
+     /// Checks if all characters in this string are within the ASCII range.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let ascii = "hello!\n";
+     /// let non_ascii = "Grüße, Jürgen ❤";
+     ///
+     /// assert!(ascii.is_ascii());
+     /// assert!(!non_ascii.is_ascii());
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn is_ascii(&self) -> bool {
+         // We can treat each byte as character here: all multibyte characters
+         // start with a byte that is not in the ascii range, so we will stop
+         // there already.
+         self.as_bytes().is_ascii()
+     }
+ 
+     /// Checks that two strings are an ASCII case-insensitive match.
+     ///
+     /// Same as `to_ascii_lowercase(a) == to_ascii_lowercase(b)`,
+     /// but without allocating and copying temporaries.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// assert!("Ferris".eq_ignore_ascii_case("FERRIS"));
+     /// assert!("Ferrös".eq_ignore_ascii_case("FERRöS"));
+     /// assert!(!"Ferrös".eq_ignore_ascii_case("FERRÖS"));
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn eq_ignore_ascii_case(&self, other: &str) -> bool {
+         self.as_bytes().eq_ignore_ascii_case(other.as_bytes())
+     }
+ 
+     /// Converts this string to its ASCII upper case equivalent in-place.
+     ///
+     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new uppercased value without modifying the existing one, use
+     /// [`to_ascii_uppercase`].
+     ///
+     /// [`to_ascii_uppercase`]: #method.to_ascii_uppercase
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut s = String::from("Grüße, Jürgen ❤");
+     ///
+     /// s.make_ascii_uppercase();
+     ///
+     /// assert_eq!("GRüßE, JüRGEN ❤", s);
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_uppercase(&mut self) {
+         // SAFETY: safe because we transmute two types with the same layout.
+         let me = unsafe { self.as_bytes_mut() };
+         me.make_ascii_uppercase()
+     }
+ 
+     /// Converts this string to its ASCII lower case equivalent in-place.
+     ///
+     /// ASCII letters 'A' to 'Z' are mapped to 'a' to 'z',
+     /// but non-ASCII letters are unchanged.
+     ///
+     /// To return a new lowercased value without modifying the existing one, use
+     /// [`to_ascii_lowercase`].
+     ///
+     /// [`to_ascii_lowercase`]: #method.to_ascii_lowercase
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// let mut s = String::from("GRÜßE, JÜRGEN ❤");
+     ///
+     /// s.make_ascii_lowercase();
+     ///
+     /// assert_eq!("grÜße, jÜrgen ❤", s);
+     /// ```
+     #[stable(feature = "ascii_methods_on_intrinsics", since = "1.23.0")]
+     #[inline]
+     pub fn make_ascii_lowercase(&mut self) {
+         // SAFETY: safe because we transmute two types with the same layout.
+         let me = unsafe { self.as_bytes_mut() };
+         me.make_ascii_lowercase()
+     }
+ 
+     /// Return an iterator that escapes each char in `self` with [`char::escape_debug`].
+     ///
+     /// Note: only extended grapheme codepoints that begin the string will be
+     /// escaped.
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in "❤\n!".escape_debug() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", "❤\n!".escape_debug());
+     /// ```
+     ///
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("❤\\n!");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!("❤\n!".escape_debug().to_string(), "❤\\n!");
+     /// ```
+     #[stable(feature = "str_escape", since = "1.34.0")]
+     pub fn escape_debug(&self) -> EscapeDebug<'_> {
+         let mut chars = self.chars();
+         EscapeDebug {
+             inner: chars
+                 .next()
+                 .map(|first| first.escape_debug_ext(true))
+                 .into_iter()
+                 .flatten()
+                 .chain(chars.flat_map(CharEscapeDebugContinue)),
+         }
+     }
+ 
+     /// Return an iterator that escapes each char in `self` with [`char::escape_default`].
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in "❤\n!".escape_default() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", "❤\n!".escape_default());
+     /// ```
+     ///
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("\\u{{2764}}\\n!");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!("❤\n!".escape_default().to_string(), "\\u{2764}\\n!");
+     /// ```
+     #[stable(feature = "str_escape", since = "1.34.0")]
+     pub fn escape_default(&self) -> EscapeDefault<'_> {
+         EscapeDefault { inner: self.chars().flat_map(CharEscapeDefault) }
+     }
+ 
+     /// Return an iterator that escapes each char in `self` with [`char::escape_unicode`].
+     ///
+     /// # Examples
+     ///
+     /// As an iterator:
+     ///
+     /// ```
+     /// for c in "❤\n!".escape_unicode() {
+     ///     print!("{}", c);
+     /// }
+     /// println!();
+     /// ```
+     ///
+     /// Using `println!` directly:
+     ///
+     /// ```
+     /// println!("{}", "❤\n!".escape_unicode());
+     /// ```
+     ///
+     ///
+     /// Both are equivalent to:
+     ///
+     /// ```
+     /// println!("\\u{{2764}}\\u{{a}}\\u{{21}}");
+     /// ```
+     ///
+     /// Using `to_string`:
+     ///
+     /// ```
+     /// assert_eq!("❤\n!".escape_unicode().to_string(), "\\u{2764}\\u{a}\\u{21}");
+     /// ```
+     #[stable(feature = "str_escape", since = "1.34.0")]
+     pub fn escape_unicode(&self) -> EscapeUnicode<'_> {
+         EscapeUnicode { inner: self.chars().flat_map(CharEscapeUnicode) }
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl AsRef<[u8]> for str {
+     #[inline]
+     fn as_ref(&self) -> &[u8] {
+         self.as_bytes()
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Default for &str {
+     /// Creates an empty str
+     #[inline]
+     fn default() -> Self {
+         ""
+     }
+ }
+ 
+ #[stable(feature = "default_mut_str", since = "1.28.0")]
+ impl Default for &mut str {
+     /// Creates an empty mutable str
+     #[inline]
+     fn default() -> Self {
+         // SAFETY: The empty string is valid UTF-8.
+         unsafe { from_utf8_unchecked_mut(&mut []) }
+     }
+ }
+ 
+ impl_fn_for_zst! {
+     /// A nameable, cloneable fn type
+     #[derive(Clone)]
+     struct LinesAnyMap impl<'a> Fn = |line: &'a str| -> &'a str {
+         let l = line.len();
+         if l > 0 && line.as_bytes()[l - 1] == b'\r' { &line[0 .. l - 1] }
+         else { line }
+     };
+ 
+     #[derive(Clone)]
+     struct CharEscapeDebugContinue impl Fn = |c: char| -> char::EscapeDebug {
+         c.escape_debug_ext(false)
+     };
+ 
+     #[derive(Clone)]
+     struct CharEscapeUnicode impl Fn = |c: char| -> char::EscapeUnicode {
+         c.escape_unicode()
+     };
+     #[derive(Clone)]
+     struct CharEscapeDefault impl Fn = |c: char| -> char::EscapeDefault {
+         c.escape_default()
+     };
+ 
+     #[derive(Clone)]
+     struct IsWhitespace impl Fn = |c: char| -> bool {
+         c.is_whitespace()
+     };
+ 
+     #[derive(Clone)]
+     struct IsAsciiWhitespace impl Fn = |byte: &u8| -> bool {
+         byte.is_ascii_whitespace()
+     };
+ 
+     #[derive(Clone)]
+     struct IsNotEmpty impl<'a, 'b> Fn = |s: &'a &'b str| -> bool {
+         !s.is_empty()
+     };
+ 
+     #[derive(Clone)]
+     struct BytesIsNotEmpty impl<'a, 'b> Fn = |s: &'a &'b [u8]| -> bool {
+         !s.is_empty()
+     };
+ 
+     #[derive(Clone)]
+     struct UnsafeBytesToStr impl<'a> Fn = |bytes: &'a [u8]| -> &'a str {
+         // SAFETY: not safe
+         unsafe { from_utf8_unchecked(bytes) }
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/pattern.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/pattern.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/pattern.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/pattern.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1598 ----
+ //! The string Pattern API.
+ //!
+ //! The Pattern API provides a generic mechanism for using different pattern
+ //! types when searching through a string.
+ //!
+ //! For more details, see the traits [`Pattern`], [`Searcher`],
+ //! [`ReverseSearcher`], and [`DoubleEndedSearcher`].
+ //!
+ //! Although this API is unstable, it is exposed via stable APIs on the
+ //! [`str`] type.
+ //!
+ //! # Examples
+ //!
+ //! [`Pattern`] is [implemented][pattern-impls] in the stable API for
+ //! [`&str`][`str`], [`char`], slices of [`char`], and functions and closures
+ //! implementing `FnMut(char) -> bool`.
+ //!
+ //! ```
+ //! let s = "Can you find a needle in a haystack?";
+ //!
+ //! // &str pattern
+ //! assert_eq!(s.find("you"), Some(4));
+ //! // char pattern
+ //! assert_eq!(s.find('n'), Some(2));
+ //! // slice of chars pattern
+ //! assert_eq!(s.find(&['a', 'e', 'i', 'o', 'u'][..]), Some(1));
+ //! // closure pattern
+ //! assert_eq!(s.find(|c: char| c.is_ascii_punctuation()), Some(35));
+ //! ```
+ //!
+ //! [pattern-impls]: Pattern#implementors
+ 
+ #![unstable(
+     feature = "pattern",
+     reason = "API not fully fleshed out and ready to be stabilized",
+     issue = "27721"
+ )]
+ 
+ use crate::cmp;
+ use crate::fmt;
+ use crate::slice::memchr;
+ 
+ // Pattern
+ 
+ /// A string pattern.
+ ///
+ /// A `Pattern<'a>` expresses that the implementing type
+ /// can be used as a string pattern for searching in a [`&'a str`][str].
+ ///
+ /// For example, both `'a'` and `"aa"` are patterns that
+ /// would match at index `1` in the string `"baaaab"`.
+ ///
+ /// The trait itself acts as a builder for an associated
+ /// [`Searcher`] type, which does the actual work of finding
+ /// occurrences of the pattern in a string.
+ ///
+ /// Depending on the type of the pattern, the behaviour of methods like
+ /// [`str::find`] and [`str::contains`] can change. The table below describes
+ /// some of those behaviours.
+ ///
+ /// | Pattern type             | Match condition                           |
+ /// |--------------------------|-------------------------------------------|
+ /// | `&str`                   | is substring                              |
+ /// | `char`                   | is contained in string                    |
+ /// | `&[char]`                | any char in slice is contained in string  |
+ /// | `F: FnMut(char) -> bool` | `F` returns `true` for a char in string   |
+ /// | `&&str`                  | is substring                              |
+ /// | `&String`                | is substring                              |
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// // &str
+ /// assert_eq!("abaaa".find("ba"), Some(1));
+ /// assert_eq!("abaaa".find("bac"), None);
+ ///
+ /// // char
+ /// assert_eq!("abaaa".find('a'), Some(0));
+ /// assert_eq!("abaaa".find('b'), Some(1));
+ /// assert_eq!("abaaa".find('c'), None);
+ ///
+ /// // &[char]
+ /// assert_eq!("ab".find(&['b', 'a'][..]), Some(0));
+ /// assert_eq!("abaaa".find(&['a', 'z'][..]), Some(0));
+ /// assert_eq!("abaaa".find(&['c', 'd'][..]), None);
+ ///
+ /// // FnMut(char) -> bool
+ /// assert_eq!("abcdef_z".find(|ch| ch > 'd' && ch < 'y'), Some(4));
+ /// assert_eq!("abcddd_z".find(|ch| ch > 'd' && ch < 'y'), None);
+ /// ```
+ pub trait Pattern<'a>: Sized {
+     /// Associated searcher for this pattern
+     type Searcher: Searcher<'a>;
+ 
+     /// Constructs the associated searcher from
+     /// `self` and the `haystack` to search in.
+     fn into_searcher(self, haystack: &'a str) -> Self::Searcher;
+ 
+     /// Checks whether the pattern matches anywhere in the haystack
+     #[inline]
+     fn is_contained_in(self, haystack: &'a str) -> bool {
+         self.into_searcher(haystack).next_match().is_some()
+     }
+ 
+     /// Checks whether the pattern matches at the front of the haystack
+     #[inline]
+     fn is_prefix_of(self, haystack: &'a str) -> bool {
+         matches!(self.into_searcher(haystack).next(), SearchStep::Match(0, _))
+     }
+ 
+     /// Checks whether the pattern matches at the back of the haystack
+     #[inline]
+     fn is_suffix_of(self, haystack: &'a str) -> bool
+     where
+         Self::Searcher: ReverseSearcher<'a>,
+     {
+         matches!(self.into_searcher(haystack).next_back(), SearchStep::Match(_, j) if haystack.len() == j)
+     }
+ 
+     /// Removes the pattern from the front of haystack, if it matches.
+     #[inline]
+     fn strip_prefix_of(self, haystack: &'a str) -> Option<&'a str> {
+         if let SearchStep::Match(start, len) = self.into_searcher(haystack).next() {
+             debug_assert_eq!(
+                 start, 0,
+                 "The first search step from Searcher \
+                  must include the first character"
+             );
+             // SAFETY: `Searcher` is known to return valid indices.
+             unsafe { Some(haystack.get_unchecked(len..)) }
+         } else {
+             None
+         }
+     }
+ 
+     /// Removes the pattern from the back of haystack, if it matches.
+     #[inline]
+     fn strip_suffix_of(self, haystack: &'a str) -> Option<&'a str>
+     where
+         Self::Searcher: ReverseSearcher<'a>,
+     {
+         if let SearchStep::Match(start, end) = self.into_searcher(haystack).next_back() {
+             debug_assert_eq!(
+                 end,
+                 haystack.len(),
+                 "The first search step from ReverseSearcher \
+                  must include the last character"
+             );
+             // SAFETY: `Searcher` is known to return valid indices.
+             unsafe { Some(haystack.get_unchecked(..start)) }
+         } else {
+             None
+         }
+     }
+ }
+ 
+ // Searcher
+ 
+ /// Result of calling [`Searcher::next()`] or [`ReverseSearcher::next_back()`].
+ #[derive(Copy, Clone, Eq, PartialEq, Debug)]
+ pub enum SearchStep {
+     /// Expresses that a match of the pattern has been found at
+     /// `haystack[a..b]`.
+     Match(usize, usize),
+     /// Expresses that `haystack[a..b]` has been rejected as a possible match
+     /// of the pattern.
+     ///
+     /// Note that there might be more than one `Reject` between two `Match`es,
+     /// there is no requirement for them to be combined into one.
+     Reject(usize, usize),
+     /// Expresses that every byte of the haystack has been visited, ending
+     /// the iteration.
+     Done,
+ }
+ 
+ /// A searcher for a string pattern.
+ ///
+ /// This trait provides methods for searching for non-overlapping
+ /// matches of a pattern starting from the front (left) of a string.
+ ///
+ /// It will be implemented by associated `Searcher`
+ /// types of the [`Pattern`] trait.
+ ///
+ /// The trait is marked unsafe because the indices returned by the
+ /// [`next()`][Searcher::next] methods are required to lie on valid utf8
+ /// boundaries in the haystack. This enables consumers of this trait to
+ /// slice the haystack without additional runtime checks.
+ pub unsafe trait Searcher<'a> {
+     /// Getter for the underlying string to be searched in
+     ///
+     /// Will always return the same [`&str`][str].
+     fn haystack(&self) -> &'a str;
+ 
+     /// Performs the next search step starting from the front.
+     ///
+     /// - Returns [`Match(a, b)`][SearchStep::Match] if `haystack[a..b]` matches
+     ///   the pattern.
+     /// - Returns [`Reject(a, b)`][SearchStep::Reject] if `haystack[a..b]` can
+     ///   not match the pattern, even partially.
+     /// - Returns [`Done`][SearchStep::Done] if every byte of the haystack has
+     ///   been visited.
+     ///
+     /// The stream of [`Match`][SearchStep::Match] and
+     /// [`Reject`][SearchStep::Reject] values up to a [`Done`][SearchStep::Done]
+     /// will contain index ranges that are adjacent, non-overlapping,
+     /// covering the whole haystack, and laying on utf8 boundaries.
+     ///
+     /// A [`Match`][SearchStep::Match] result needs to contain the whole matched
+     /// pattern, however [`Reject`][SearchStep::Reject] results may be split up
+     /// into arbitrary many adjacent fragments. Both ranges may have zero length.
+     ///
+     /// As an example, the pattern `"aaa"` and the haystack `"cbaaaaab"`
+     /// might produce the stream
+     /// `[Reject(0, 1), Reject(1, 2), Match(2, 5), Reject(5, 8)]`
+     fn next(&mut self) -> SearchStep;
+ 
+     /// Finds the next [`Match`][SearchStep::Match] result. See [`next()`][Searcher::next].
+     ///
+     /// Unlike [`next()`][Searcher::next], there is no guarantee that the returned ranges
+     /// of this and [`next_reject`][Searcher::next_reject] will overlap. This will return
+     /// `(start_match, end_match)`, where start_match is the index of where
+     /// the match begins, and end_match is the index after the end of the match.
+     #[inline]
+     fn next_match(&mut self) -> Option<(usize, usize)> {
+         loop {
+             match self.next() {
+                 SearchStep::Match(a, b) => return Some((a, b)),
+                 SearchStep::Done => return None,
+                 _ => continue,
+             }
+         }
+     }
+ 
+     /// Finds the next [`Reject`][SearchStep::Reject] result. See [`next()`][Searcher::next]
+     /// and [`next_match()`][Searcher::next_match].
+     ///
+     /// Unlike [`next()`][Searcher::next], there is no guarantee that the returned ranges
+     /// of this and [`next_match`][Searcher::next_match] will overlap.
+     #[inline]
+     fn next_reject(&mut self) -> Option<(usize, usize)> {
+         loop {
+             match self.next() {
+                 SearchStep::Reject(a, b) => return Some((a, b)),
+                 SearchStep::Done => return None,
+                 _ => continue,
+             }
+         }
+     }
+ }
+ 
+ /// A reverse searcher for a string pattern.
+ ///
+ /// This trait provides methods for searching for non-overlapping
+ /// matches of a pattern starting from the back (right) of a string.
+ ///
+ /// It will be implemented by associated [`Searcher`]
+ /// types of the [`Pattern`] trait if the pattern supports searching
+ /// for it from the back.
+ ///
+ /// The index ranges returned by this trait are not required
+ /// to exactly match those of the forward search in reverse.
+ ///
+ /// For the reason why this trait is marked unsafe, see them
+ /// parent trait [`Searcher`].
+ pub unsafe trait ReverseSearcher<'a>: Searcher<'a> {
+     /// Performs the next search step starting from the back.
+     ///
+     /// - Returns [`Match(a, b)`][SearchStep::Match] if `haystack[a..b]`
+     ///   matches the pattern.
+     /// - Returns [`Reject(a, b)`][SearchStep::Reject] if `haystack[a..b]`
+     ///   can not match the pattern, even partially.
+     /// - Returns [`Done`][SearchStep::Done] if every byte of the haystack
+     ///   has been visited
+     ///
+     /// The stream of [`Match`][SearchStep::Match] and
+     /// [`Reject`][SearchStep::Reject] values up to a [`Done`][SearchStep::Done]
+     /// will contain index ranges that are adjacent, non-overlapping,
+     /// covering the whole haystack, and laying on utf8 boundaries.
+     ///
+     /// A [`Match`][SearchStep::Match] result needs to contain the whole matched
+     /// pattern, however [`Reject`][SearchStep::Reject] results may be split up
+     /// into arbitrary many adjacent fragments. Both ranges may have zero length.
+     ///
+     /// As an example, the pattern `"aaa"` and the haystack `"cbaaaaab"`
+     /// might produce the stream
+     /// `[Reject(7, 8), Match(4, 7), Reject(1, 4), Reject(0, 1)]`.
+     fn next_back(&mut self) -> SearchStep;
+ 
+     /// Finds the next [`Match`][SearchStep::Match] result.
+     /// See [`next_back()`][ReverseSearcher::next_back].
+     #[inline]
+     fn next_match_back(&mut self) -> Option<(usize, usize)> {
+         loop {
+             match self.next_back() {
+                 SearchStep::Match(a, b) => return Some((a, b)),
+                 SearchStep::Done => return None,
+                 _ => continue,
+             }
+         }
+     }
+ 
+     /// Finds the next [`Reject`][SearchStep::Reject] result.
+     /// See [`next_back()`][ReverseSearcher::next_back].
+     #[inline]
+     fn next_reject_back(&mut self) -> Option<(usize, usize)> {
+         loop {
+             match self.next_back() {
+                 SearchStep::Reject(a, b) => return Some((a, b)),
+                 SearchStep::Done => return None,
+                 _ => continue,
+             }
+         }
+     }
+ }
+ 
+ /// A marker trait to express that a [`ReverseSearcher`]
+ /// can be used for a [`DoubleEndedIterator`] implementation.
+ ///
+ /// For this, the impl of [`Searcher`] and [`ReverseSearcher`] need
+ /// to follow these conditions:
+ ///
+ /// - All results of `next()` need to be identical
+ ///   to the results of `next_back()` in reverse order.
+ /// - `next()` and `next_back()` need to behave as
+ ///   the two ends of a range of values, that is they
+ ///   can not "walk past each other".
+ ///
+ /// # Examples
+ ///
+ /// `char::Searcher` is a `DoubleEndedSearcher` because searching for a
+ /// [`char`] only requires looking at one at a time, which behaves the same
+ /// from both ends.
+ ///
+ /// `(&str)::Searcher` is not a `DoubleEndedSearcher` because
+ /// the pattern `"aa"` in the haystack `"aaa"` matches as either
+ /// `"[aa]a"` or `"a[aa]"`, depending from which side it is searched.
+ pub trait DoubleEndedSearcher<'a>: ReverseSearcher<'a> {}
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Impl for char
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ /// Associated type for `<char as Pattern<'a>>::Searcher`.
+ #[derive(Clone, Debug)]
+ pub struct CharSearcher<'a> {
+     haystack: &'a str,
+     // safety invariant: `finger`/`finger_back` must be a valid utf8 byte index of `haystack`
+     // This invariant can be broken *within* next_match and next_match_back, however
+     // they must exit with fingers on valid code point boundaries.
+     /// `finger` is the current byte index of the forward search.
+     /// Imagine that it exists before the byte at its index, i.e.
+     /// `haystack[finger]` is the first byte of the slice we must inspect during
+     /// forward searching
+     finger: usize,
+     /// `finger_back` is the current byte index of the reverse search.
+     /// Imagine that it exists after the byte at its index, i.e.
+     /// haystack[finger_back - 1] is the last byte of the slice we must inspect during
+     /// forward searching (and thus the first byte to be inspected when calling next_back()).
+     finger_back: usize,
+     /// The character being searched for
+     needle: char,
+ 
+     // safety invariant: `utf8_size` must be less than 5
+     /// The number of bytes `needle` takes up when encoded in utf8.
+     utf8_size: usize,
+     /// A utf8 encoded copy of the `needle`
+     utf8_encoded: [u8; 4],
+ }
+ 
+ unsafe impl<'a> Searcher<'a> for CharSearcher<'a> {
+     #[inline]
+     fn haystack(&self) -> &'a str {
+         self.haystack
+     }
+     #[inline]
+     fn next(&mut self) -> SearchStep {
+         let old_finger = self.finger;
+         // SAFETY: 1-4 guarantee safety of `get_unchecked`
+         // 1. `self.finger` and `self.finger_back` are kept on unicode boundaries
+         //    (this is invariant)
+         // 2. `self.finger >= 0` since it starts at 0 and only increases
+         // 3. `self.finger < self.finger_back` because otherwise the char `iter`
+         //    would return `SearchStep::Done`
+         // 4. `self.finger` comes before the end of the haystack because `self.finger_back`
+         //    starts at the end and only decreases
+         let slice = unsafe { self.haystack.get_unchecked(old_finger..self.finger_back) };
+         let mut iter = slice.chars();
+         let old_len = iter.iter.len();
+         if let Some(ch) = iter.next() {
+             // add byte offset of current character
+             // without re-encoding as utf-8
+             self.finger += old_len - iter.iter.len();
+             if ch == self.needle {
+                 SearchStep::Match(old_finger, self.finger)
+             } else {
+                 SearchStep::Reject(old_finger, self.finger)
+             }
+         } else {
+             SearchStep::Done
+         }
+     }
+     #[inline]
+     fn next_match(&mut self) -> Option<(usize, usize)> {
+         loop {
+             // get the haystack after the last character found
+             let bytes = self.haystack.as_bytes().get(self.finger..self.finger_back)?;
+             // the last byte of the utf8 encoded needle
+             // SAFETY: we have an invariant that `utf8_size < 5`
+             let last_byte = unsafe { *self.utf8_encoded.get_unchecked(self.utf8_size - 1) };
+             if let Some(index) = memchr::memchr(last_byte, bytes) {
+                 // The new finger is the index of the byte we found,
+                 // plus one, since we memchr'd for the last byte of the character.
+                 //
+                 // Note that this doesn't always give us a finger on a UTF8 boundary.
+                 // If we *didn't* find our character
+                 // we may have indexed to the non-last byte of a 3-byte or 4-byte character.
+                 // We can't just skip to the next valid starting byte because a character like
+                 // ꁁ (U+A041 YI SYLLABLE PA), utf-8 `EA 81 81` will have us always find
+                 // the second byte when searching for the third.
+                 //
+                 // However, this is totally okay. While we have the invariant that
+                 // self.finger is on a UTF8 boundary, this invariant is not relied upon
+                 // within this method (it is relied upon in CharSearcher::next()).
+                 //
+                 // We only exit this method when we reach the end of the string, or if we
+                 // find something. When we find something the `finger` will be set
+                 // to a UTF8 boundary.
+                 self.finger += index + 1;
+                 if self.finger >= self.utf8_size {
+                     let found_char = self.finger - self.utf8_size;
+                     if let Some(slice) = self.haystack.as_bytes().get(found_char..self.finger) {
+                         if slice == &self.utf8_encoded[0..self.utf8_size] {
+                             return Some((found_char, self.finger));
+                         }
+                     }
+                 }
+             } else {
+                 // found nothing, exit
+                 self.finger = self.finger_back;
+                 return None;
+             }
+         }
+     }
+ 
+     // let next_reject use the default implementation from the Searcher trait
+ }
+ 
+ unsafe impl<'a> ReverseSearcher<'a> for CharSearcher<'a> {
+     #[inline]
+     fn next_back(&mut self) -> SearchStep {
+         let old_finger = self.finger_back;
+         // SAFETY: see the comment for next() above
+         let slice = unsafe { self.haystack.get_unchecked(self.finger..old_finger) };
+         let mut iter = slice.chars();
+         let old_len = iter.iter.len();
+         if let Some(ch) = iter.next_back() {
+             // subtract byte offset of current character
+             // without re-encoding as utf-8
+             self.finger_back -= old_len - iter.iter.len();
+             if ch == self.needle {
+                 SearchStep::Match(self.finger_back, old_finger)
+             } else {
+                 SearchStep::Reject(self.finger_back, old_finger)
+             }
+         } else {
+             SearchStep::Done
+         }
+     }
+     #[inline]
+     fn next_match_back(&mut self) -> Option<(usize, usize)> {
+         let haystack = self.haystack.as_bytes();
+         loop {
+             // get the haystack up to but not including the last character searched
+             let bytes = haystack.get(self.finger..self.finger_back)?;
+             // the last byte of the utf8 encoded needle
+             // SAFETY: we have an invariant that `utf8_size < 5`
+             let last_byte = unsafe { *self.utf8_encoded.get_unchecked(self.utf8_size - 1) };
+             if let Some(index) = memchr::memrchr(last_byte, bytes) {
+                 // we searched a slice that was offset by self.finger,
+                 // add self.finger to recoup the original index
+                 let index = self.finger + index;
+                 // memrchr will return the index of the byte we wish to
+                 // find. In case of an ASCII character, this is indeed
+                 // were we wish our new finger to be ("after" the found
+                 // char in the paradigm of reverse iteration). For
+                 // multibyte chars we need to skip down by the number of more
+                 // bytes they have than ASCII
+                 let shift = self.utf8_size - 1;
+                 if index >= shift {
+                     let found_char = index - shift;
+                     if let Some(slice) = haystack.get(found_char..(found_char + self.utf8_size)) {
+                         if slice == &self.utf8_encoded[0..self.utf8_size] {
+                             // move finger to before the character found (i.e., at its start index)
+                             self.finger_back = found_char;
+                             return Some((self.finger_back, self.finger_back + self.utf8_size));
+                         }
+                     }
+                 }
+                 // We can't use finger_back = index - size + 1 here. If we found the last char
+                 // of a different-sized character (or the middle byte of a different character)
+                 // we need to bump the finger_back down to `index`. This similarly makes
+                 // `finger_back` have the potential to no longer be on a boundary,
+                 // but this is OK since we only exit this function on a boundary
+                 // or when the haystack has been searched completely.
+                 //
+                 // Unlike next_match this does not
+                 // have the problem of repeated bytes in utf-8 because
+                 // we're searching for the last byte, and we can only have
+                 // found the last byte when searching in reverse.
+                 self.finger_back = index;
+             } else {
+                 self.finger_back = self.finger;
+                 // found nothing, exit
+                 return None;
+             }
+         }
+     }
+ 
+     // let next_reject_back use the default implementation from the Searcher trait
+ }
+ 
+ impl<'a> DoubleEndedSearcher<'a> for CharSearcher<'a> {}
+ 
+ /// Searches for chars that are equal to a given [`char`].
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// assert_eq!("Hello world".find('o'), Some(4));
+ /// ```
+ impl<'a> Pattern<'a> for char {
+     type Searcher = CharSearcher<'a>;
+ 
+     #[inline]
+     fn into_searcher(self, haystack: &'a str) -> Self::Searcher {
+         let mut utf8_encoded = [0; 4];
+         let utf8_size = self.encode_utf8(&mut utf8_encoded).len();
+         CharSearcher {
+             haystack,
+             finger: 0,
+             finger_back: haystack.len(),
+             needle: self,
+             utf8_size,
+             utf8_encoded,
+         }
+     }
+ 
+     #[inline]
+     fn is_contained_in(self, haystack: &'a str) -> bool {
+         if (self as u32) < 128 {
+             haystack.as_bytes().contains(&(self as u8))
+         } else {
+             let mut buffer = [0u8; 4];
+             self.encode_utf8(&mut buffer).is_contained_in(haystack)
+         }
+     }
+ 
+     #[inline]
+     fn is_prefix_of(self, haystack: &'a str) -> bool {
+         self.encode_utf8(&mut [0u8; 4]).is_prefix_of(haystack)
+     }
+ 
+     #[inline]
+     fn strip_prefix_of(self, haystack: &'a str) -> Option<&'a str> {
+         self.encode_utf8(&mut [0u8; 4]).strip_prefix_of(haystack)
+     }
+ 
+     #[inline]
+     fn is_suffix_of(self, haystack: &'a str) -> bool
+     where
+         Self::Searcher: ReverseSearcher<'a>,
+     {
+         self.encode_utf8(&mut [0u8; 4]).is_suffix_of(haystack)
+     }
+ 
+     #[inline]
+     fn strip_suffix_of(self, haystack: &'a str) -> Option<&'a str>
+     where
+         Self::Searcher: ReverseSearcher<'a>,
+     {
+         self.encode_utf8(&mut [0u8; 4]).strip_suffix_of(haystack)
+     }
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Impl for a MultiCharEq wrapper
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[doc(hidden)]
+ trait MultiCharEq {
+     fn matches(&mut self, c: char) -> bool;
+ }
+ 
+ impl<F> MultiCharEq for F
+ where
+     F: FnMut(char) -> bool,
+ {
+     #[inline]
+     fn matches(&mut self, c: char) -> bool {
+         (*self)(c)
+     }
+ }
+ 
+ impl MultiCharEq for &[char] {
+     #[inline]
+     fn matches(&mut self, c: char) -> bool {
+         self.iter().any(|&m| m == c)
+     }
+ }
+ 
+ struct MultiCharEqPattern<C: MultiCharEq>(C);
+ 
+ #[derive(Clone, Debug)]
+ struct MultiCharEqSearcher<'a, C: MultiCharEq> {
+     char_eq: C,
+     haystack: &'a str,
+     char_indices: super::CharIndices<'a>,
+ }
+ 
+ impl<'a, C: MultiCharEq> Pattern<'a> for MultiCharEqPattern<C> {
+     type Searcher = MultiCharEqSearcher<'a, C>;
+ 
+     #[inline]
+     fn into_searcher(self, haystack: &'a str) -> MultiCharEqSearcher<'a, C> {
+         MultiCharEqSearcher { haystack, char_eq: self.0, char_indices: haystack.char_indices() }
+     }
+ }
+ 
+ unsafe impl<'a, C: MultiCharEq> Searcher<'a> for MultiCharEqSearcher<'a, C> {
+     #[inline]
+     fn haystack(&self) -> &'a str {
+         self.haystack
+     }
+ 
+     #[inline]
+     fn next(&mut self) -> SearchStep {
+         let s = &mut self.char_indices;
+         // Compare lengths of the internal byte slice iterator
+         // to find length of current char
+         let pre_len = s.iter.iter.len();
+         if let Some((i, c)) = s.next() {
+             let len = s.iter.iter.len();
+             let char_len = pre_len - len;
+             if self.char_eq.matches(c) {
+                 return SearchStep::Match(i, i + char_len);
+             } else {
+                 return SearchStep::Reject(i, i + char_len);
+             }
+         }
+         SearchStep::Done
+     }
+ }
+ 
+ unsafe impl<'a, C: MultiCharEq> ReverseSearcher<'a> for MultiCharEqSearcher<'a, C> {
+     #[inline]
+     fn next_back(&mut self) -> SearchStep {
+         let s = &mut self.char_indices;
+         // Compare lengths of the internal byte slice iterator
+         // to find length of current char
+         let pre_len = s.iter.iter.len();
+         if let Some((i, c)) = s.next_back() {
+             let len = s.iter.iter.len();
+             let char_len = pre_len - len;
+             if self.char_eq.matches(c) {
+                 return SearchStep::Match(i, i + char_len);
+             } else {
+                 return SearchStep::Reject(i, i + char_len);
+             }
+         }
+         SearchStep::Done
+     }
+ }
+ 
+ impl<'a, C: MultiCharEq> DoubleEndedSearcher<'a> for MultiCharEqSearcher<'a, C> {}
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ macro_rules! pattern_methods {
+     ($t:ty, $pmap:expr, $smap:expr) => {
+         type Searcher = $t;
+ 
+         #[inline]
+         fn into_searcher(self, haystack: &'a str) -> $t {
+             ($smap)(($pmap)(self).into_searcher(haystack))
+         }
+ 
+         #[inline]
+         fn is_contained_in(self, haystack: &'a str) -> bool {
+             ($pmap)(self).is_contained_in(haystack)
+         }
+ 
+         #[inline]
+         fn is_prefix_of(self, haystack: &'a str) -> bool {
+             ($pmap)(self).is_prefix_of(haystack)
+         }
+ 
+         #[inline]
+         fn strip_prefix_of(self, haystack: &'a str) -> Option<&'a str> {
+             ($pmap)(self).strip_prefix_of(haystack)
+         }
+ 
+         #[inline]
+         fn is_suffix_of(self, haystack: &'a str) -> bool
+         where
+             $t: ReverseSearcher<'a>,
+         {
+             ($pmap)(self).is_suffix_of(haystack)
+         }
+ 
+         #[inline]
+         fn strip_suffix_of(self, haystack: &'a str) -> Option<&'a str>
+         where
+             $t: ReverseSearcher<'a>,
+         {
+             ($pmap)(self).strip_suffix_of(haystack)
+         }
+     };
+ }
+ 
+ macro_rules! searcher_methods {
+     (forward) => {
+         #[inline]
+         fn haystack(&self) -> &'a str {
+             self.0.haystack()
+         }
+         #[inline]
+         fn next(&mut self) -> SearchStep {
+             self.0.next()
+         }
+         #[inline]
+         fn next_match(&mut self) -> Option<(usize, usize)> {
+             self.0.next_match()
+         }
+         #[inline]
+         fn next_reject(&mut self) -> Option<(usize, usize)> {
+             self.0.next_reject()
+         }
+     };
+     (reverse) => {
+         #[inline]
+         fn next_back(&mut self) -> SearchStep {
+             self.0.next_back()
+         }
+         #[inline]
+         fn next_match_back(&mut self) -> Option<(usize, usize)> {
+             self.0.next_match_back()
+         }
+         #[inline]
+         fn next_reject_back(&mut self) -> Option<(usize, usize)> {
+             self.0.next_reject_back()
+         }
+     };
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Impl for &[char]
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ // Todo: Change / Remove due to ambiguity in meaning.
+ 
+ /// Associated type for `<&[char] as Pattern<'a>>::Searcher`.
+ #[derive(Clone, Debug)]
+ pub struct CharSliceSearcher<'a, 'b>(<MultiCharEqPattern<&'b [char]> as Pattern<'a>>::Searcher);
+ 
+ unsafe impl<'a, 'b> Searcher<'a> for CharSliceSearcher<'a, 'b> {
+     searcher_methods!(forward);
+ }
+ 
+ unsafe impl<'a, 'b> ReverseSearcher<'a> for CharSliceSearcher<'a, 'b> {
+     searcher_methods!(reverse);
+ }
+ 
+ impl<'a, 'b> DoubleEndedSearcher<'a> for CharSliceSearcher<'a, 'b> {}
+ 
+ /// Searches for chars that are equal to any of the [`char`]s in the slice.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// assert_eq!("Hello world".find(&['l', 'l'] as &[_]), Some(2));
+ /// assert_eq!("Hello world".find(&['l', 'l'][..]), Some(2));
+ /// ```
+ impl<'a, 'b> Pattern<'a> for &'b [char] {
+     pattern_methods!(CharSliceSearcher<'a, 'b>, MultiCharEqPattern, CharSliceSearcher);
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Impl for F: FnMut(char) -> bool
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ /// Associated type for `<F as Pattern<'a>>::Searcher`.
+ #[derive(Clone)]
+ pub struct CharPredicateSearcher<'a, F>(<MultiCharEqPattern<F> as Pattern<'a>>::Searcher)
+ where
+     F: FnMut(char) -> bool;
+ 
+ impl<F> fmt::Debug for CharPredicateSearcher<'_, F>
+ where
+     F: FnMut(char) -> bool,
+ {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("CharPredicateSearcher")
+             .field("haystack", &self.0.haystack)
+             .field("char_indices", &self.0.char_indices)
+             .finish()
+     }
+ }
+ unsafe impl<'a, F> Searcher<'a> for CharPredicateSearcher<'a, F>
+ where
+     F: FnMut(char) -> bool,
+ {
+     searcher_methods!(forward);
+ }
+ 
+ unsafe impl<'a, F> ReverseSearcher<'a> for CharPredicateSearcher<'a, F>
+ where
+     F: FnMut(char) -> bool,
+ {
+     searcher_methods!(reverse);
+ }
+ 
+ impl<'a, F> DoubleEndedSearcher<'a> for CharPredicateSearcher<'a, F> where F: FnMut(char) -> bool {}
+ 
+ /// Searches for [`char`]s that match the given predicate.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// assert_eq!("Hello world".find(char::is_uppercase), Some(0));
+ /// assert_eq!("Hello world".find(|c| "aeiou".contains(c)), Some(1));
+ /// ```
+ impl<'a, F> Pattern<'a> for F
+ where
+     F: FnMut(char) -> bool,
+ {
+     pattern_methods!(CharPredicateSearcher<'a, F>, MultiCharEqPattern, CharPredicateSearcher);
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Impl for &&str
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ /// Delegates to the `&str` impl.
+ impl<'a, 'b, 'c> Pattern<'a> for &'c &'b str {
+     pattern_methods!(StrSearcher<'a, 'b>, |&s| s, |s| s);
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Impl for &str
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ /// Non-allocating substring search.
+ ///
+ /// Will handle the pattern `""` as returning empty matches at each character
+ /// boundary.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// assert_eq!("Hello world".find("world"), Some(6));
+ /// ```
+ impl<'a, 'b> Pattern<'a> for &'b str {
+     type Searcher = StrSearcher<'a, 'b>;
+ 
+     #[inline]
+     fn into_searcher(self, haystack: &'a str) -> StrSearcher<'a, 'b> {
+         StrSearcher::new(haystack, self)
+     }
+ 
+     /// Checks whether the pattern matches at the front of the haystack.
+     #[inline]
+     fn is_prefix_of(self, haystack: &'a str) -> bool {
+         haystack.as_bytes().starts_with(self.as_bytes())
+     }
+ 
+     /// Removes the pattern from the front of haystack, if it matches.
+     #[inline]
+     fn strip_prefix_of(self, haystack: &'a str) -> Option<&'a str> {
+         if self.is_prefix_of(haystack) {
+             // SAFETY: prefix was just verified to exist.
+             unsafe { Some(haystack.get_unchecked(self.as_bytes().len()..)) }
+         } else {
+             None
+         }
+     }
+ 
+     /// Checks whether the pattern matches at the back of the haystack.
+     #[inline]
+     fn is_suffix_of(self, haystack: &'a str) -> bool {
+         haystack.as_bytes().ends_with(self.as_bytes())
+     }
+ 
+     /// Removes the pattern from the back of haystack, if it matches.
+     #[inline]
+     fn strip_suffix_of(self, haystack: &'a str) -> Option<&'a str> {
+         if self.is_suffix_of(haystack) {
+             let i = haystack.len() - self.as_bytes().len();
+             // SAFETY: suffix was just verified to exist.
+             unsafe { Some(haystack.get_unchecked(..i)) }
+         } else {
+             None
+         }
+     }
+ }
+ 
+ /////////////////////////////////////////////////////////////////////////////
+ // Two Way substring searcher
+ /////////////////////////////////////////////////////////////////////////////
+ 
+ #[derive(Clone, Debug)]
+ /// Associated type for `<&str as Pattern<'a>>::Searcher`.
+ pub struct StrSearcher<'a, 'b> {
+     haystack: &'a str,
+     needle: &'b str,
+ 
+     searcher: StrSearcherImpl,
+ }
+ 
+ #[derive(Clone, Debug)]
+ enum StrSearcherImpl {
+     Empty(EmptyNeedle),
+     TwoWay(TwoWaySearcher),
+ }
+ 
+ #[derive(Clone, Debug)]
+ struct EmptyNeedle {
+     position: usize,
+     end: usize,
+     is_match_fw: bool,
+     is_match_bw: bool,
+ }
+ 
+ impl<'a, 'b> StrSearcher<'a, 'b> {
+     fn new(haystack: &'a str, needle: &'b str) -> StrSearcher<'a, 'b> {
+         if needle.is_empty() {
+             StrSearcher {
+                 haystack,
+                 needle,
+                 searcher: StrSearcherImpl::Empty(EmptyNeedle {
+                     position: 0,
+                     end: haystack.len(),
+                     is_match_fw: true,
+                     is_match_bw: true,
+                 }),
+             }
+         } else {
+             StrSearcher {
+                 haystack,
+                 needle,
+                 searcher: StrSearcherImpl::TwoWay(TwoWaySearcher::new(
+                     needle.as_bytes(),
+                     haystack.len(),
+                 )),
+             }
+         }
+     }
+ }
+ 
+ unsafe impl<'a, 'b> Searcher<'a> for StrSearcher<'a, 'b> {
+     #[inline]
+     fn haystack(&self) -> &'a str {
+         self.haystack
+     }
+ 
+     #[inline]
+     fn next(&mut self) -> SearchStep {
+         match self.searcher {
+             StrSearcherImpl::Empty(ref mut searcher) => {
+                 // empty needle rejects every char and matches every empty string between them
+                 let is_match = searcher.is_match_fw;
+                 searcher.is_match_fw = !searcher.is_match_fw;
+                 let pos = searcher.position;
+                 match self.haystack[pos..].chars().next() {
+                     _ if is_match => SearchStep::Match(pos, pos),
+                     None => SearchStep::Done,
+                     Some(ch) => {
+                         searcher.position += ch.len_utf8();
+                         SearchStep::Reject(pos, searcher.position)
+                     }
+                 }
+             }
+             StrSearcherImpl::TwoWay(ref mut searcher) => {
+                 // TwoWaySearcher produces valid *Match* indices that split at char boundaries
+                 // as long as it does correct matching and that haystack and needle are
+                 // valid UTF-8
+                 // *Rejects* from the algorithm can fall on any indices, but we will walk them
+                 // manually to the next character boundary, so that they are utf-8 safe.
+                 if searcher.position == self.haystack.len() {
+                     return SearchStep::Done;
+                 }
+                 let is_long = searcher.memory == usize::MAX;
+                 match searcher.next::<RejectAndMatch>(
+                     self.haystack.as_bytes(),
+                     self.needle.as_bytes(),
+                     is_long,
+                 ) {
+                     SearchStep::Reject(a, mut b) => {
+                         // skip to next char boundary
+                         while !self.haystack.is_char_boundary(b) {
+                             b += 1;
+                         }
+                         searcher.position = cmp::max(b, searcher.position);
+                         SearchStep::Reject(a, b)
+                     }
+                     otherwise => otherwise,
+                 }
+             }
+         }
+     }
+ 
+     #[inline]
+     fn next_match(&mut self) -> Option<(usize, usize)> {
+         match self.searcher {
+             StrSearcherImpl::Empty(..) => loop {
+                 match self.next() {
+                     SearchStep::Match(a, b) => return Some((a, b)),
+                     SearchStep::Done => return None,
+                     SearchStep::Reject(..) => {}
+                 }
+             },
+             StrSearcherImpl::TwoWay(ref mut searcher) => {
+                 let is_long = searcher.memory == usize::MAX;
+                 // write out `true` and `false` cases to encourage the compiler
+                 // to specialize the two cases separately.
+                 if is_long {
+                     searcher.next::<MatchOnly>(
+                         self.haystack.as_bytes(),
+                         self.needle.as_bytes(),
+                         true,
+                     )
+                 } else {
+                     searcher.next::<MatchOnly>(
+                         self.haystack.as_bytes(),
+                         self.needle.as_bytes(),
+                         false,
+                     )
+                 }
+             }
+         }
+     }
+ }
+ 
+ unsafe impl<'a, 'b> ReverseSearcher<'a> for StrSearcher<'a, 'b> {
+     #[inline]
+     fn next_back(&mut self) -> SearchStep {
+         match self.searcher {
+             StrSearcherImpl::Empty(ref mut searcher) => {
+                 let is_match = searcher.is_match_bw;
+                 searcher.is_match_bw = !searcher.is_match_bw;
+                 let end = searcher.end;
+                 match self.haystack[..end].chars().next_back() {
+                     _ if is_match => SearchStep::Match(end, end),
+                     None => SearchStep::Done,
+                     Some(ch) => {
+                         searcher.end -= ch.len_utf8();
+                         SearchStep::Reject(searcher.end, end)
+                     }
+                 }
+             }
+             StrSearcherImpl::TwoWay(ref mut searcher) => {
+                 if searcher.end == 0 {
+                     return SearchStep::Done;
+                 }
+                 let is_long = searcher.memory == usize::MAX;
+                 match searcher.next_back::<RejectAndMatch>(
+                     self.haystack.as_bytes(),
+                     self.needle.as_bytes(),
+                     is_long,
+                 ) {
+                     SearchStep::Reject(mut a, b) => {
+                         // skip to next char boundary
+                         while !self.haystack.is_char_boundary(a) {
+                             a -= 1;
+                         }
+                         searcher.end = cmp::min(a, searcher.end);
+                         SearchStep::Reject(a, b)
+                     }
+                     otherwise => otherwise,
+                 }
+             }
+         }
+     }
+ 
+     #[inline]
+     fn next_match_back(&mut self) -> Option<(usize, usize)> {
+         match self.searcher {
+             StrSearcherImpl::Empty(..) => loop {
+                 match self.next_back() {
+                     SearchStep::Match(a, b) => return Some((a, b)),
+                     SearchStep::Done => return None,
+                     SearchStep::Reject(..) => {}
+                 }
+             },
+             StrSearcherImpl::TwoWay(ref mut searcher) => {
+                 let is_long = searcher.memory == usize::MAX;
+                 // write out `true` and `false`, like `next_match`
+                 if is_long {
+                     searcher.next_back::<MatchOnly>(
+                         self.haystack.as_bytes(),
+                         self.needle.as_bytes(),
+                         true,
+                     )
+                 } else {
+                     searcher.next_back::<MatchOnly>(
+                         self.haystack.as_bytes(),
+                         self.needle.as_bytes(),
+                         false,
+                     )
+                 }
+             }
+         }
+     }
+ }
+ 
+ /// The internal state of the two-way substring search algorithm.
+ #[derive(Clone, Debug)]
+ struct TwoWaySearcher {
+     // constants
+     /// critical factorization index
+     crit_pos: usize,
+     /// critical factorization index for reversed needle
+     crit_pos_back: usize,
+     period: usize,
+     /// `byteset` is an extension (not part of the two way algorithm);
+     /// it's a 64-bit "fingerprint" where each set bit `j` corresponds
+     /// to a (byte & 63) == j present in the needle.
+     byteset: u64,
+ 
+     // variables
+     position: usize,
+     end: usize,
+     /// index into needle before which we have already matched
+     memory: usize,
+     /// index into needle after which we have already matched
+     memory_back: usize,
+ }
+ 
+ /*
+     This is the Two-Way search algorithm, which was introduced in the paper:
+     Crochemore, M., Perrin, D., 1991, Two-way string-matching, Journal of the ACM 38(3):651-675.
+ 
+     Here's some background information.
+ 
+     A *word* is a string of symbols. The *length* of a word should be a familiar
+     notion, and here we denote it for any word x by |x|.
+     (We also allow for the possibility of the *empty word*, a word of length zero).
+ 
+     If x is any non-empty word, then an integer p with 0 < p <= |x| is said to be a
+     *period* for x iff for all i with 0 <= i <= |x| - p - 1, we have x[i] == x[i+p].
+     For example, both 1 and 2 are periods for the string "aa". As another example,
+     the only period of the string "abcd" is 4.
+ 
+     We denote by period(x) the *smallest* period of x (provided that x is non-empty).
+     This is always well-defined since every non-empty word x has at least one period,
+     |x|. We sometimes call this *the period* of x.
+ 
+     If u, v and x are words such that x = uv, where uv is the concatenation of u and
+     v, then we say that (u, v) is a *factorization* of x.
+ 
+     Let (u, v) be a factorization for a word x. Then if w is a non-empty word such
+     that both of the following hold
+ 
+       - either w is a suffix of u or u is a suffix of w
+       - either w is a prefix of v or v is a prefix of w
+ 
+     then w is said to be a *repetition* for the factorization (u, v).
+ 
+     Just to unpack this, there are four possibilities here. Let w = "abc". Then we
+     might have:
+ 
+       - w is a suffix of u and w is a prefix of v. ex: ("lolabc", "abcde")
+       - w is a suffix of u and v is a prefix of w. ex: ("lolabc", "ab")
+       - u is a suffix of w and w is a prefix of v. ex: ("bc", "abchi")
+       - u is a suffix of w and v is a prefix of w. ex: ("bc", "a")
+ 
+     Note that the word vu is a repetition for any factorization (u,v) of x = uv,
+     so every factorization has at least one repetition.
+ 
+     If x is a string and (u, v) is a factorization for x, then a *local period* for
+     (u, v) is an integer r such that there is some word w such that |w| = r and w is
+     a repetition for (u, v).
+ 
+     We denote by local_period(u, v) the smallest local period of (u, v). We sometimes
+     call this *the local period* of (u, v). Provided that x = uv is non-empty, this
+     is well-defined (because each non-empty word has at least one factorization, as
+     noted above).
+ 
+     It can be proven that the following is an equivalent definition of a local period
+     for a factorization (u, v): any positive integer r such that x[i] == x[i+r] for
+     all i such that |u| - r <= i <= |u| - 1 and such that both x[i] and x[i+r] are
+     defined. (i.e., i > 0 and i + r < |x|).
+ 
+     Using the above reformulation, it is easy to prove that
+ 
+         1 <= local_period(u, v) <= period(uv)
+ 
+     A factorization (u, v) of x such that local_period(u,v) = period(x) is called a
+     *critical factorization*.
+ 
+     The algorithm hinges on the following theorem, which is stated without proof:
+ 
+     **Critical Factorization Theorem** Any word x has at least one critical
+     factorization (u, v) such that |u| < period(x).
+ 
+     The purpose of maximal_suffix is to find such a critical factorization.
+ 
+     If the period is short, compute another factorization x = u' v' to use
+     for reverse search, chosen instead so that |v'| < period(x).
+ 
+ */
+ impl TwoWaySearcher {
+     fn new(needle: &[u8], end: usize) -> TwoWaySearcher {
+         let (crit_pos_false, period_false) = TwoWaySearcher::maximal_suffix(needle, false);
+         let (crit_pos_true, period_true) = TwoWaySearcher::maximal_suffix(needle, true);
+ 
+         let (crit_pos, period) = if crit_pos_false > crit_pos_true {
+             (crit_pos_false, period_false)
+         } else {
+             (crit_pos_true, period_true)
+         };
+ 
+         // A particularly readable explanation of what's going on here can be found
+         // in Crochemore and Rytter's book "Text Algorithms", ch 13. Specifically
+         // see the code for "Algorithm CP" on p. 323.
+         //
+         // What's going on is we have some critical factorization (u, v) of the
+         // needle, and we want to determine whether u is a suffix of
+         // &v[..period]. If it is, we use "Algorithm CP1". Otherwise we use
+         // "Algorithm CP2", which is optimized for when the period of the needle
+         // is large.
+         if needle[..crit_pos] == needle[period..period + crit_pos] {
+             // short period case -- the period is exact
+             // compute a separate critical factorization for the reversed needle
+             // x = u' v' where |v'| < period(x).
+             //
+             // This is sped up by the period being known already.
+             // Note that a case like x = "acba" may be factored exactly forwards
+             // (crit_pos = 1, period = 3) while being factored with approximate
+             // period in reverse (crit_pos = 2, period = 2). We use the given
+             // reverse factorization but keep the exact period.
+             let crit_pos_back = needle.len()
+                 - cmp::max(
+                     TwoWaySearcher::reverse_maximal_suffix(needle, period, false),
+                     TwoWaySearcher::reverse_maximal_suffix(needle, period, true),
+                 );
+ 
+             TwoWaySearcher {
+                 crit_pos,
+                 crit_pos_back,
+                 period,
+                 byteset: Self::byteset_create(&needle[..period]),
+ 
+                 position: 0,
+                 end,
+                 memory: 0,
+                 memory_back: needle.len(),
+             }
+         } else {
+             // long period case -- we have an approximation to the actual period,
+             // and don't use memorization.
+             //
+             // Approximate the period by lower bound max(|u|, |v|) + 1.
+             // The critical factorization is efficient to use for both forward and
+             // reverse search.
+ 
+             TwoWaySearcher {
+                 crit_pos,
+                 crit_pos_back: crit_pos,
+                 period: cmp::max(crit_pos, needle.len() - crit_pos) + 1,
+                 byteset: Self::byteset_create(needle),
+ 
+                 position: 0,
+                 end,
+                 memory: usize::MAX, // Dummy value to signify that the period is long
+                 memory_back: usize::MAX,
+             }
+         }
+     }
+ 
+     #[inline]
+     fn byteset_create(bytes: &[u8]) -> u64 {
+         bytes.iter().fold(0, |a, &b| (1 << (b & 0x3f)) | a)
+     }
+ 
+     #[inline]
+     fn byteset_contains(&self, byte: u8) -> bool {
+         (self.byteset >> ((byte & 0x3f) as usize)) & 1 != 0
+     }
+ 
+     // One of the main ideas of Two-Way is that we factorize the needle into
+     // two halves, (u, v), and begin trying to find v in the haystack by scanning
+     // left to right. If v matches, we try to match u by scanning right to left.
+     // How far we can jump when we encounter a mismatch is all based on the fact
+     // that (u, v) is a critical factorization for the needle.
+     #[inline]
+     fn next<S>(&mut self, haystack: &[u8], needle: &[u8], long_period: bool) -> S::Output
+     where
+         S: TwoWayStrategy,
+     {
+         // `next()` uses `self.position` as its cursor
+         let old_pos = self.position;
+         let needle_last = needle.len() - 1;
+         'search: loop {
+             // Check that we have room to search in
+             // position + needle_last can not overflow if we assume slices
+             // are bounded by isize's range.
+             let tail_byte = match haystack.get(self.position + needle_last) {
+                 Some(&b) => b,
+                 None => {
+                     self.position = haystack.len();
+                     return S::rejecting(old_pos, self.position);
+                 }
+             };
+ 
+             if S::use_early_reject() && old_pos != self.position {
+                 return S::rejecting(old_pos, self.position);
+             }
+ 
+             // Quickly skip by large portions unrelated to our substring
+             if !self.byteset_contains(tail_byte) {
+                 self.position += needle.len();
+                 if !long_period {
+                     self.memory = 0;
+                 }
+                 continue 'search;
+             }
+ 
+             // See if the right part of the needle matches
+             let start =
+                 if long_period { self.crit_pos } else { cmp::max(self.crit_pos, self.memory) };
+             for i in start..needle.len() {
+                 if needle[i] != haystack[self.position + i] {
+                     self.position += i - self.crit_pos + 1;
+                     if !long_period {
+                         self.memory = 0;
+                     }
+                     continue 'search;
+                 }
+             }
+ 
+             // See if the left part of the needle matches
+             let start = if long_period { 0 } else { self.memory };
+             for i in (start..self.crit_pos).rev() {
+                 if needle[i] != haystack[self.position + i] {
+                     self.position += self.period;
+                     if !long_period {
+                         self.memory = needle.len() - self.period;
+                     }
+                     continue 'search;
+                 }
+             }
+ 
+             // We have found a match!
+             let match_pos = self.position;
+ 
+             // Note: add self.period instead of needle.len() to have overlapping matches
+             self.position += needle.len();
+             if !long_period {
+                 self.memory = 0; // set to needle.len() - self.period for overlapping matches
+             }
+ 
+             return S::matching(match_pos, match_pos + needle.len());
+         }
+     }
+ 
+     // Follows the ideas in `next()`.
+     //
+     // The definitions are symmetrical, with period(x) = period(reverse(x))
+     // and local_period(u, v) = local_period(reverse(v), reverse(u)), so if (u, v)
+     // is a critical factorization, so is (reverse(v), reverse(u)).
+     //
+     // For the reverse case we have computed a critical factorization x = u' v'
+     // (field `crit_pos_back`). We need |u| < period(x) for the forward case and
+     // thus |v'| < period(x) for the reverse.
+     //
+     // To search in reverse through the haystack, we search forward through
+     // a reversed haystack with a reversed needle, matching first u' and then v'.
+     #[inline]
+     fn next_back<S>(&mut self, haystack: &[u8], needle: &[u8], long_period: bool) -> S::Output
+     where
+         S: TwoWayStrategy,
+     {
+         // `next_back()` uses `self.end` as its cursor -- so that `next()` and `next_back()`
+         // are independent.
+         let old_end = self.end;
+         'search: loop {
+             // Check that we have room to search in
+             // end - needle.len() will wrap around when there is no more room,
+             // but due to slice length limits it can never wrap all the way back
+             // into the length of haystack.
+             let front_byte = match haystack.get(self.end.wrapping_sub(needle.len())) {
+                 Some(&b) => b,
+                 None => {
+                     self.end = 0;
+                     return S::rejecting(0, old_end);
+                 }
+             };
+ 
+             if S::use_early_reject() && old_end != self.end {
+                 return S::rejecting(self.end, old_end);
+             }
+ 
+             // Quickly skip by large portions unrelated to our substring
+             if !self.byteset_contains(front_byte) {
+                 self.end -= needle.len();
+                 if !long_period {
+                     self.memory_back = needle.len();
+                 }
+                 continue 'search;
+             }
+ 
+             // See if the left part of the needle matches
+             let crit = if long_period {
+                 self.crit_pos_back
+             } else {
+                 cmp::min(self.crit_pos_back, self.memory_back)
+             };
+             for i in (0..crit).rev() {
+                 if needle[i] != haystack[self.end - needle.len() + i] {
+                     self.end -= self.crit_pos_back - i;
+                     if !long_period {
+                         self.memory_back = needle.len();
+                     }
+                     continue 'search;
+                 }
+             }
+ 
+             // See if the right part of the needle matches
+             let needle_end = if long_period { needle.len() } else { self.memory_back };
+             for i in self.crit_pos_back..needle_end {
+                 if needle[i] != haystack[self.end - needle.len() + i] {
+                     self.end -= self.period;
+                     if !long_period {
+                         self.memory_back = self.period;
+                     }
+                     continue 'search;
+                 }
+             }
+ 
+             // We have found a match!
+             let match_pos = self.end - needle.len();
+             // Note: sub self.period instead of needle.len() to have overlapping matches
+             self.end -= needle.len();
+             if !long_period {
+                 self.memory_back = needle.len();
+             }
+ 
+             return S::matching(match_pos, match_pos + needle.len());
+         }
+     }
+ 
+     // Compute the maximal suffix of `arr`.
+     //
+     // The maximal suffix is a possible critical factorization (u, v) of `arr`.
+     //
+     // Returns (`i`, `p`) where `i` is the starting index of v and `p` is the
+     // period of v.
+     //
+     // `order_greater` determines if lexical order is `<` or `>`. Both
+     // orders must be computed -- the ordering with the largest `i` gives
+     // a critical factorization.
+     //
+     // For long period cases, the resulting period is not exact (it is too short).
+     #[inline]
+     fn maximal_suffix(arr: &[u8], order_greater: bool) -> (usize, usize) {
+         let mut left = 0; // Corresponds to i in the paper
+         let mut right = 1; // Corresponds to j in the paper
+         let mut offset = 0; // Corresponds to k in the paper, but starting at 0
+         // to match 0-based indexing.
+         let mut period = 1; // Corresponds to p in the paper
+ 
+         while let Some(&a) = arr.get(right + offset) {
+             // `left` will be inbounds when `right` is.
+             let b = arr[left + offset];
+             if (a < b && !order_greater) || (a > b && order_greater) {
+                 // Suffix is smaller, period is entire prefix so far.
+                 right += offset + 1;
+                 offset = 0;
+                 period = right - left;
+             } else if a == b {
+                 // Advance through repetition of the current period.
+                 if offset + 1 == period {
+                     right += offset + 1;
+                     offset = 0;
+                 } else {
+                     offset += 1;
+                 }
+             } else {
+                 // Suffix is larger, start over from current location.
+                 left = right;
+                 right += 1;
+                 offset = 0;
+                 period = 1;
+             }
+         }
+         (left, period)
+     }
+ 
+     // Compute the maximal suffix of the reverse of `arr`.
+     //
+     // The maximal suffix is a possible critical factorization (u', v') of `arr`.
+     //
+     // Returns `i` where `i` is the starting index of v', from the back;
+     // returns immediately when a period of `known_period` is reached.
+     //
+     // `order_greater` determines if lexical order is `<` or `>`. Both
+     // orders must be computed -- the ordering with the largest `i` gives
+     // a critical factorization.
+     //
+     // For long period cases, the resulting period is not exact (it is too short).
+     fn reverse_maximal_suffix(arr: &[u8], known_period: usize, order_greater: bool) -> usize {
+         let mut left = 0; // Corresponds to i in the paper
+         let mut right = 1; // Corresponds to j in the paper
+         let mut offset = 0; // Corresponds to k in the paper, but starting at 0
+         // to match 0-based indexing.
+         let mut period = 1; // Corresponds to p in the paper
+         let n = arr.len();
+ 
+         while right + offset < n {
+             let a = arr[n - (1 + right + offset)];
+             let b = arr[n - (1 + left + offset)];
+             if (a < b && !order_greater) || (a > b && order_greater) {
+                 // Suffix is smaller, period is entire prefix so far.
+                 right += offset + 1;
+                 offset = 0;
+                 period = right - left;
+             } else if a == b {
+                 // Advance through repetition of the current period.
+                 if offset + 1 == period {
+                     right += offset + 1;
+                     offset = 0;
+                 } else {
+                     offset += 1;
+                 }
+             } else {
+                 // Suffix is larger, start over from current location.
+                 left = right;
+                 right += 1;
+                 offset = 0;
+                 period = 1;
+             }
+             if period == known_period {
+                 break;
+             }
+         }
+         debug_assert!(period <= known_period);
+         left
+     }
+ }
+ 
+ // TwoWayStrategy allows the algorithm to either skip non-matches as quickly
+ // as possible, or to work in a mode where it emits Rejects relatively quickly.
+ trait TwoWayStrategy {
+     type Output;
+     fn use_early_reject() -> bool;
+     fn rejecting(a: usize, b: usize) -> Self::Output;
+     fn matching(a: usize, b: usize) -> Self::Output;
+ }
+ 
+ /// Skip to match intervals as quickly as possible
+ enum MatchOnly {}
+ 
+ impl TwoWayStrategy for MatchOnly {
+     type Output = Option<(usize, usize)>;
+ 
+     #[inline]
+     fn use_early_reject() -> bool {
+         false
+     }
+     #[inline]
+     fn rejecting(_a: usize, _b: usize) -> Self::Output {
+         None
+     }
+     #[inline]
+     fn matching(a: usize, b: usize) -> Self::Output {
+         Some((a, b))
+     }
+ }
+ 
+ /// Emit Rejects regularly
+ enum RejectAndMatch {}
+ 
+ impl TwoWayStrategy for RejectAndMatch {
+     type Output = SearchStep;
+ 
+     #[inline]
+     fn use_early_reject() -> bool {
+         true
+     }
+     #[inline]
+     fn rejecting(a: usize, b: usize) -> Self::Output {
+         SearchStep::Reject(a, b)
+     }
+     #[inline]
+     fn matching(a: usize, b: usize) -> Self::Output {
+         SearchStep::Match(a, b)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/traits.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/traits.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/traits.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/traits.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,593 ----
+ //! Trait implementations for `str`.
+ 
+ use crate::cmp::Ordering;
+ use crate::ops;
+ use crate::ptr;
+ use crate::slice::SliceIndex;
+ 
+ use super::ParseBoolError;
+ 
+ /// Implements ordering of strings.
+ ///
+ /// Strings are ordered  [lexicographically](Ord#lexicographical-comparison) by their byte values. This orders Unicode code
+ /// points based on their positions in the code charts. This is not necessarily the same as
+ /// "alphabetical" order, which varies by language and locale. Sorting strings according to
+ /// culturally-accepted standards requires locale-specific data that is outside the scope of
+ /// the `str` type.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Ord for str {
+     #[inline]
+     fn cmp(&self, other: &str) -> Ordering {
+         self.as_bytes().cmp(other.as_bytes())
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl PartialEq for str {
+     #[inline]
+     fn eq(&self, other: &str) -> bool {
+         self.as_bytes() == other.as_bytes()
+     }
+     #[inline]
+     fn ne(&self, other: &str) -> bool {
+         !(*self).eq(other)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Eq for str {}
+ 
+ /// Implements comparison operations on strings.
+ ///
+ /// Strings are compared [lexicographically](Ord#lexicographical-comparison) by their byte values. This compares Unicode code
+ /// points based on their positions in the code charts. This is not necessarily the same as
+ /// "alphabetical" order, which varies by language and locale. Comparing strings according to
+ /// culturally-accepted standards requires locale-specific data that is outside the scope of
+ /// the `str` type.
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl PartialOrd for str {
+     #[inline]
+     fn partial_cmp(&self, other: &str) -> Option<Ordering> {
+         Some(self.cmp(other))
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ops::Index<I> for str
+ where
+     I: SliceIndex<str>,
+ {
+     type Output = I::Output;
+ 
+     #[inline]
+     fn index(&self, index: I) -> &I::Output {
+         index.index(self)
+     }
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<I> ops::IndexMut<I> for str
+ where
+     I: SliceIndex<str>,
+ {
+     #[inline]
+     fn index_mut(&mut self, index: I) -> &mut I::Output {
+         index.index_mut(self)
+     }
+ }
+ 
+ #[inline(never)]
+ #[cold]
+ #[track_caller]
+ fn str_index_overflow_fail() -> ! {
+     panic!("attempted to index str up to maximum usize");
+ }
+ 
+ /// Implements substring slicing with syntax `&self[..]` or `&mut self[..]`.
+ ///
+ /// Returns a slice of the whole string, i.e., returns `&self` or `&mut
+ /// self`. Equivalent to `&self[0 .. len]` or `&mut self[0 .. len]`. Unlike
+ /// other indexing operations, this can never panic.
+ ///
+ /// This operation is *O*(1).
+ ///
+ /// Prior to 1.20.0, these indexing operations were still supported by
+ /// direct implementation of `Index` and `IndexMut`.
+ ///
+ /// Equivalent to `&self[0 .. len]` or `&mut self[0 .. len]`.
+ #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+ unsafe impl SliceIndex<str> for ops::RangeFull {
+     type Output = str;
+     #[inline]
+     fn get(self, slice: &str) -> Option<&Self::Output> {
+         Some(slice)
+     }
+     #[inline]
+     fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> {
+         Some(slice)
+     }
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output {
+         slice
+     }
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output {
+         slice
+     }
+     #[inline]
+     fn index(self, slice: &str) -> &Self::Output {
+         slice
+     }
+     #[inline]
+     fn index_mut(self, slice: &mut str) -> &mut Self::Output {
+         slice
+     }
+ }
+ 
+ /// Implements substring slicing with syntax `&self[begin .. end]` or `&mut
+ /// self[begin .. end]`.
+ ///
+ /// Returns a slice of the given string from the byte range
+ /// [`begin`, `end`).
+ ///
+ /// This operation is *O*(1).
+ ///
+ /// Prior to 1.20.0, these indexing operations were still supported by
+ /// direct implementation of `Index` and `IndexMut`.
+ ///
+ /// # Panics
+ ///
+ /// Panics if `begin` or `end` does not point to the starting byte offset of
+ /// a character (as defined by `is_char_boundary`), if `begin > end`, or if
+ /// `end > len`.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// let s = "Löwe 老虎 Léopard";
+ /// assert_eq!(&s[0 .. 1], "L");
+ ///
+ /// assert_eq!(&s[1 .. 9], "öwe 老");
+ ///
+ /// // these will panic:
+ /// // byte 2 lies within `ö`:
+ /// // &s[2 ..3];
+ ///
+ /// // byte 8 lies within `老`
+ /// // &s[1 .. 8];
+ ///
+ /// // byte 100 is outside the string
+ /// // &s[3 .. 100];
+ /// ```
+ #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+ unsafe impl SliceIndex<str> for ops::Range<usize> {
+     type Output = str;
+     #[inline]
+     fn get(self, slice: &str) -> Option<&Self::Output> {
+         if self.start <= self.end
+             && slice.is_char_boundary(self.start)
+             && slice.is_char_boundary(self.end)
+         {
+             // SAFETY: just checked that `start` and `end` are on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             // We also checked char boundaries, so this is valid UTF-8.
+             Some(unsafe { &*self.get_unchecked(slice) })
+         } else {
+             None
+         }
+     }
+     #[inline]
+     fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> {
+         if self.start <= self.end
+             && slice.is_char_boundary(self.start)
+             && slice.is_char_boundary(self.end)
+         {
+             // SAFETY: just checked that `start` and `end` are on a char boundary.
+             // We know the pointer is unique because we got it from `slice`.
+             Some(unsafe { &mut *self.get_unchecked_mut(slice) })
+         } else {
+             None
+         }
+     }
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output {
+         let slice = slice as *const [u8];
+         // SAFETY: the caller guarantees that `self` is in bounds of `slice`
+         // which satisfies all the conditions for `add`.
+         let ptr = unsafe { slice.as_ptr().add(self.start) };
+         let len = self.end - self.start;
+         ptr::slice_from_raw_parts(ptr, len) as *const str
+     }
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output {
+         let slice = slice as *mut [u8];
+         // SAFETY: see comments for `get_unchecked`.
+         let ptr = unsafe { slice.as_mut_ptr().add(self.start) };
+         let len = self.end - self.start;
+         ptr::slice_from_raw_parts_mut(ptr, len) as *mut str
+     }
+     #[inline]
+     fn index(self, slice: &str) -> &Self::Output {
+         let (start, end) = (self.start, self.end);
+         match self.get(slice) {
+             Some(s) => s,
+             None => super::slice_error_fail(slice, start, end),
+         }
+     }
+     #[inline]
+     fn index_mut(self, slice: &mut str) -> &mut Self::Output {
+         // is_char_boundary checks that the index is in [0, .len()]
+         // cannot reuse `get` as above, because of NLL trouble
+         if self.start <= self.end
+             && slice.is_char_boundary(self.start)
+             && slice.is_char_boundary(self.end)
+         {
+             // SAFETY: just checked that `start` and `end` are on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             unsafe { &mut *self.get_unchecked_mut(slice) }
+         } else {
+             super::slice_error_fail(slice, self.start, self.end)
+         }
+     }
+ }
+ 
+ /// Implements substring slicing with syntax `&self[.. end]` or `&mut
+ /// self[.. end]`.
+ ///
+ /// Returns a slice of the given string from the byte range [`0`, `end`).
+ /// Equivalent to `&self[0 .. end]` or `&mut self[0 .. end]`.
+ ///
+ /// This operation is *O*(1).
+ ///
+ /// Prior to 1.20.0, these indexing operations were still supported by
+ /// direct implementation of `Index` and `IndexMut`.
+ ///
+ /// # Panics
+ ///
+ /// Panics if `end` does not point to the starting byte offset of a
+ /// character (as defined by `is_char_boundary`), or if `end > len`.
+ #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+ unsafe impl SliceIndex<str> for ops::RangeTo<usize> {
+     type Output = str;
+     #[inline]
+     fn get(self, slice: &str) -> Option<&Self::Output> {
+         if slice.is_char_boundary(self.end) {
+             // SAFETY: just checked that `end` is on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             Some(unsafe { &*self.get_unchecked(slice) })
+         } else {
+             None
+         }
+     }
+     #[inline]
+     fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> {
+         if slice.is_char_boundary(self.end) {
+             // SAFETY: just checked that `end` is on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             Some(unsafe { &mut *self.get_unchecked_mut(slice) })
+         } else {
+             None
+         }
+     }
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output {
+         let slice = slice as *const [u8];
+         let ptr = slice.as_ptr();
+         ptr::slice_from_raw_parts(ptr, self.end) as *const str
+     }
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output {
+         let slice = slice as *mut [u8];
+         let ptr = slice.as_mut_ptr();
+         ptr::slice_from_raw_parts_mut(ptr, self.end) as *mut str
+     }
+     #[inline]
+     fn index(self, slice: &str) -> &Self::Output {
+         let end = self.end;
+         match self.get(slice) {
+             Some(s) => s,
+             None => super::slice_error_fail(slice, 0, end),
+         }
+     }
+     #[inline]
+     fn index_mut(self, slice: &mut str) -> &mut Self::Output {
+         if slice.is_char_boundary(self.end) {
+             // SAFETY: just checked that `end` is on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             unsafe { &mut *self.get_unchecked_mut(slice) }
+         } else {
+             super::slice_error_fail(slice, 0, self.end)
+         }
+     }
+ }
+ 
+ /// Implements substring slicing with syntax `&self[begin ..]` or `&mut
+ /// self[begin ..]`.
+ ///
+ /// Returns a slice of the given string from the byte range [`begin`,
+ /// `len`). Equivalent to `&self[begin .. len]` or `&mut self[begin ..
+ /// len]`.
+ ///
+ /// This operation is *O*(1).
+ ///
+ /// Prior to 1.20.0, these indexing operations were still supported by
+ /// direct implementation of `Index` and `IndexMut`.
+ ///
+ /// # Panics
+ ///
+ /// Panics if `begin` does not point to the starting byte offset of
+ /// a character (as defined by `is_char_boundary`), or if `begin > len`.
+ #[stable(feature = "str_checked_slicing", since = "1.20.0")]
+ unsafe impl SliceIndex<str> for ops::RangeFrom<usize> {
+     type Output = str;
+     #[inline]
+     fn get(self, slice: &str) -> Option<&Self::Output> {
+         if slice.is_char_boundary(self.start) {
+             // SAFETY: just checked that `start` is on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             Some(unsafe { &*self.get_unchecked(slice) })
+         } else {
+             None
+         }
+     }
+     #[inline]
+     fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> {
+         if slice.is_char_boundary(self.start) {
+             // SAFETY: just checked that `start` is on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             Some(unsafe { &mut *self.get_unchecked_mut(slice) })
+         } else {
+             None
+         }
+     }
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output {
+         let slice = slice as *const [u8];
+         // SAFETY: the caller guarantees that `self` is in bounds of `slice`
+         // which satisfies all the conditions for `add`.
+         let ptr = unsafe { slice.as_ptr().add(self.start) };
+         let len = slice.len() - self.start;
+         ptr::slice_from_raw_parts(ptr, len) as *const str
+     }
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output {
+         let slice = slice as *mut [u8];
+         // SAFETY: identical to `get_unchecked`.
+         let ptr = unsafe { slice.as_mut_ptr().add(self.start) };
+         let len = slice.len() - self.start;
+         ptr::slice_from_raw_parts_mut(ptr, len) as *mut str
+     }
+     #[inline]
+     fn index(self, slice: &str) -> &Self::Output {
+         let (start, end) = (self.start, slice.len());
+         match self.get(slice) {
+             Some(s) => s,
+             None => super::slice_error_fail(slice, start, end),
+         }
+     }
+     #[inline]
+     fn index_mut(self, slice: &mut str) -> &mut Self::Output {
+         if slice.is_char_boundary(self.start) {
+             // SAFETY: just checked that `start` is on a char boundary,
+             // and we are passing in a safe reference, so the return value will also be one.
+             unsafe { &mut *self.get_unchecked_mut(slice) }
+         } else {
+             super::slice_error_fail(slice, self.start, slice.len())
+         }
+     }
+ }
+ 
+ /// Implements substring slicing with syntax `&self[begin ..= end]` or `&mut
+ /// self[begin ..= end]`.
+ ///
+ /// Returns a slice of the given string from the byte range
+ /// [`begin`, `end`]. Equivalent to `&self [begin .. end + 1]` or `&mut
+ /// self[begin .. end + 1]`, except if `end` has the maximum value for
+ /// `usize`.
+ ///
+ /// This operation is *O*(1).
+ ///
+ /// # Panics
+ ///
+ /// Panics if `begin` does not point to the starting byte offset of
+ /// a character (as defined by `is_char_boundary`), if `end` does not point
+ /// to the ending byte offset of a character (`end + 1` is either a starting
+ /// byte offset or equal to `len`), if `begin > end`, or if `end >= len`.
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ unsafe impl SliceIndex<str> for ops::RangeInclusive<usize> {
+     type Output = str;
+     #[inline]
+     fn get(self, slice: &str) -> Option<&Self::Output> {
+         if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) }
+     }
+     #[inline]
+     fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> {
+         if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) }
+     }
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked`.
+         unsafe { self.into_slice_range().get_unchecked(slice) }
+     }
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`.
+         unsafe { self.into_slice_range().get_unchecked_mut(slice) }
+     }
+     #[inline]
+     fn index(self, slice: &str) -> &Self::Output {
+         if *self.end() == usize::MAX {
+             str_index_overflow_fail();
+         }
+         self.into_slice_range().index(slice)
+     }
+     #[inline]
+     fn index_mut(self, slice: &mut str) -> &mut Self::Output {
+         if *self.end() == usize::MAX {
+             str_index_overflow_fail();
+         }
+         self.into_slice_range().index_mut(slice)
+     }
+ }
+ 
+ /// Implements substring slicing with syntax `&self[..= end]` or `&mut
+ /// self[..= end]`.
+ ///
+ /// Returns a slice of the given string from the byte range [0, `end`].
+ /// Equivalent to `&self [0 .. end + 1]`, except if `end` has the maximum
+ /// value for `usize`.
+ ///
+ /// This operation is *O*(1).
+ ///
+ /// # Panics
+ ///
+ /// Panics if `end` does not point to the ending byte offset of a character
+ /// (`end + 1` is either a starting byte offset as defined by
+ /// `is_char_boundary`, or equal to `len`), or if `end >= len`.
+ #[stable(feature = "inclusive_range", since = "1.26.0")]
+ unsafe impl SliceIndex<str> for ops::RangeToInclusive<usize> {
+     type Output = str;
+     #[inline]
+     fn get(self, slice: &str) -> Option<&Self::Output> {
+         if self.end == usize::MAX { None } else { (..self.end + 1).get(slice) }
+     }
+     #[inline]
+     fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> {
+         if self.end == usize::MAX { None } else { (..self.end + 1).get_mut(slice) }
+     }
+     #[inline]
+     unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked`.
+         unsafe { (..self.end + 1).get_unchecked(slice) }
+     }
+     #[inline]
+     unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output {
+         // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`.
+         unsafe { (..self.end + 1).get_unchecked_mut(slice) }
+     }
+     #[inline]
+     fn index(self, slice: &str) -> &Self::Output {
+         if self.end == usize::MAX {
+             str_index_overflow_fail();
+         }
+         (..self.end + 1).index(slice)
+     }
+     #[inline]
+     fn index_mut(self, slice: &mut str) -> &mut Self::Output {
+         if self.end == usize::MAX {
+             str_index_overflow_fail();
+         }
+         (..self.end + 1).index_mut(slice)
+     }
+ }
+ 
+ /// Parse a value from a string
+ ///
+ /// `FromStr`'s [`from_str`] method is often used implicitly, through
+ /// [`str`]'s [`parse`] method. See [`parse`]'s documentation for examples.
+ ///
+ /// [`from_str`]: FromStr::from_str
+ /// [`parse`]: str::parse
+ ///
+ /// `FromStr` does not have a lifetime parameter, and so you can only parse types
+ /// that do not contain a lifetime parameter themselves. In other words, you can
+ /// parse an `i32` with `FromStr`, but not a `&i32`. You can parse a struct that
+ /// contains an `i32`, but not one that contains an `&i32`.
+ ///
+ /// # Examples
+ ///
+ /// Basic implementation of `FromStr` on an example `Point` type:
+ ///
+ /// ```
+ /// use std::str::FromStr;
+ /// use std::num::ParseIntError;
+ ///
+ /// #[derive(Debug, PartialEq)]
+ /// struct Point {
+ ///     x: i32,
+ ///     y: i32
+ /// }
+ ///
+ /// impl FromStr for Point {
+ ///     type Err = ParseIntError;
+ ///
+ ///     fn from_str(s: &str) -> Result<Self, Self::Err> {
+ ///         let coords: Vec<&str> = s.trim_matches(|p| p == '(' || p == ')' )
+ ///                                  .split(',')
+ ///                                  .collect();
+ ///
+ ///         let x_fromstr = coords[0].parse::<i32>()?;
+ ///         let y_fromstr = coords[1].parse::<i32>()?;
+ ///
+ ///         Ok(Point { x: x_fromstr, y: y_fromstr })
+ ///     }
+ /// }
+ ///
+ /// let p = Point::from_str("(1,2)");
+ /// assert_eq!(p.unwrap(), Point{ x: 1, y: 2} )
+ /// ```
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub trait FromStr: Sized {
+     /// The associated error which can be returned from parsing.
+     #[stable(feature = "rust1", since = "1.0.0")]
+     type Err;
+ 
+     /// Parses a string `s` to return a value of this type.
+     ///
+     /// If parsing succeeds, return the value inside [`Ok`], otherwise
+     /// when the string is ill-formatted return an error specific to the
+     /// inside [`Err`]. The error type is specific to implementation of the trait.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage with [`i32`][ithirtytwo], a type that implements `FromStr`:
+     ///
+     /// [ithirtytwo]: ../../std/primitive.i32.html
+     ///
+     /// ```
+     /// use std::str::FromStr;
+     ///
+     /// let s = "5";
+     /// let x = i32::from_str(s).unwrap();
+     ///
+     /// assert_eq!(5, x);
+     /// ```
+     #[stable(feature = "rust1", since = "1.0.0")]
+     fn from_str(s: &str) -> Result<Self, Self::Err>;
+ }
+ 
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl FromStr for bool {
+     type Err = ParseBoolError;
+ 
+     /// Parse a `bool` from a string.
+     ///
+     /// Yields a `Result<bool, ParseBoolError>`, because `s` may or may not
+     /// actually be parseable.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::str::FromStr;
+     ///
+     /// assert_eq!(FromStr::from_str("true"), Ok(true));
+     /// assert_eq!(FromStr::from_str("false"), Ok(false));
+     /// assert!(<bool as FromStr>::from_str("not even a boolean").is_err());
+     /// ```
+     ///
+     /// Note, in many cases, the `.parse()` method on `str` is more proper.
+     ///
+     /// ```
+     /// assert_eq!("true".parse(), Ok(true));
+     /// assert_eq!("false".parse(), Ok(false));
+     /// assert!("not even a boolean".parse::<bool>().is_err());
+     /// ```
+     #[inline]
+     fn from_str(s: &str) -> Result<bool, ParseBoolError> {
+         match s {
+             "true" => Ok(true),
+             "false" => Ok(false),
+             _ => Err(ParseBoolError { _priv: () }),
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/str/validations.rs gcc-16-20251102/libgrust/rustc-lib/core/src/str/validations.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/str/validations.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/str/validations.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,275 ----
+ //! Operations related to UTF-8 validation.
+ 
+ use crate::mem;
+ 
+ use super::Utf8Error;
+ 
+ /// Returns the initial codepoint accumulator for the first byte.
+ /// The first byte is special, only want bottom 5 bits for width 2, 4 bits
+ /// for width 3, and 3 bits for width 4.
+ #[inline]
+ fn utf8_first_byte(byte: u8, width: u32) -> u32 {
+     (byte & (0x7F >> width)) as u32
+ }
+ 
+ /// Returns the value of `ch` updated with continuation byte `byte`.
+ #[inline]
+ fn utf8_acc_cont_byte(ch: u32, byte: u8) -> u32 {
+     (ch << 6) | (byte & CONT_MASK) as u32
+ }
+ 
+ /// Checks whether the byte is a UTF-8 continuation byte (i.e., starts with the
+ /// bits `10`).
+ #[inline]
+ pub(super) fn utf8_is_cont_byte(byte: u8) -> bool {
+     (byte & !CONT_MASK) == TAG_CONT_U8
+ }
+ 
+ #[inline]
+ fn unwrap_or_0(opt: Option<&u8>) -> u8 {
+     match opt {
+         Some(&byte) => byte,
+         None => 0,
+     }
+ }
+ 
+ /// Reads the next code point out of a byte iterator (assuming a
+ /// UTF-8-like encoding).
+ #[unstable(feature = "str_internals", issue = "none")]
+ #[inline]
+ pub fn next_code_point<'a, I: Iterator<Item = &'a u8>>(bytes: &mut I) -> Option<u32> {
+     // Decode UTF-8
+     let x = *bytes.next()?;
+     if x < 128 {
+         return Some(x as u32);
+     }
+ 
+     // Multibyte case follows
+     // Decode from a byte combination out of: [[[x y] z] w]
+     // NOTE: Performance is sensitive to the exact formulation here
+     let init = utf8_first_byte(x, 2);
+     let y = unwrap_or_0(bytes.next());
+     let mut ch = utf8_acc_cont_byte(init, y);
+     if x >= 0xE0 {
+         // [[x y z] w] case
+         // 5th bit in 0xE0 .. 0xEF is always clear, so `init` is still valid
+         let z = unwrap_or_0(bytes.next());
+         let y_z = utf8_acc_cont_byte((y & CONT_MASK) as u32, z);
+         ch = init << 12 | y_z;
+         if x >= 0xF0 {
+             // [x y z w] case
+             // use only the lower 3 bits of `init`
+             let w = unwrap_or_0(bytes.next());
+             ch = (init & 7) << 18 | utf8_acc_cont_byte(y_z, w);
+         }
+     }
+ 
+     Some(ch)
+ }
+ 
+ /// Reads the last code point out of a byte iterator (assuming a
+ /// UTF-8-like encoding).
+ #[inline]
+ pub(super) fn next_code_point_reverse<'a, I>(bytes: &mut I) -> Option<u32>
+ where
+     I: DoubleEndedIterator<Item = &'a u8>,
+ {
+     // Decode UTF-8
+     let w = match *bytes.next_back()? {
+         next_byte if next_byte < 128 => return Some(next_byte as u32),
+         back_byte => back_byte,
+     };
+ 
+     // Multibyte case follows
+     // Decode from a byte combination out of: [x [y [z w]]]
+     let mut ch;
+     let z = unwrap_or_0(bytes.next_back());
+     ch = utf8_first_byte(z, 2);
+     if utf8_is_cont_byte(z) {
+         let y = unwrap_or_0(bytes.next_back());
+         ch = utf8_first_byte(y, 3);
+         if utf8_is_cont_byte(y) {
+             let x = unwrap_or_0(bytes.next_back());
+             ch = utf8_first_byte(x, 4);
+             ch = utf8_acc_cont_byte(ch, y);
+         }
+         ch = utf8_acc_cont_byte(ch, z);
+     }
+     ch = utf8_acc_cont_byte(ch, w);
+ 
+     Some(ch)
+ }
+ 
+ // use truncation to fit u64 into usize
+ const NONASCII_MASK: usize = 0x80808080_80808080u64 as usize;
+ 
+ /// Returns `true` if any byte in the word `x` is nonascii (>= 128).
+ #[inline]
+ fn contains_nonascii(x: usize) -> bool {
+     (x & NONASCII_MASK) != 0
+ }
+ 
+ /// Walks through `v` checking that it's a valid UTF-8 sequence,
+ /// returning `Ok(())` in that case, or, if it is invalid, `Err(err)`.
+ #[inline(always)]
+ pub(super) fn run_utf8_validation(v: &[u8]) -> Result<(), Utf8Error> {
+     let mut index = 0;
+     let len = v.len();
+ 
+     let usize_bytes = mem::size_of::<usize>();
+     let ascii_block_size = 2 * usize_bytes;
+     let blocks_end = if len >= ascii_block_size { len - ascii_block_size + 1 } else { 0 };
+     let align = v.as_ptr().align_offset(usize_bytes);
+ 
+     while index < len {
+         let old_offset = index;
+         macro_rules! err {
+             ($error_len: expr) => {
+                 return Err(Utf8Error { valid_up_to: old_offset, error_len: $error_len });
+             };
+         }
+ 
+         macro_rules! next {
+             () => {{
+                 index += 1;
+                 // we needed data, but there was none: error!
+                 if index >= len {
+                     err!(None)
+                 }
+                 v[index]
+             }};
+         }
+ 
+         let first = v[index];
+         if first >= 128 {
+             let w = UTF8_CHAR_WIDTH[first as usize];
+             // 2-byte encoding is for codepoints  \u{0080} to  \u{07ff}
+             //        first  C2 80        last DF BF
+             // 3-byte encoding is for codepoints  \u{0800} to  \u{ffff}
+             //        first  E0 A0 80     last EF BF BF
+             //   excluding surrogates codepoints  \u{d800} to  \u{dfff}
+             //               ED A0 80 to       ED BF BF
+             // 4-byte encoding is for codepoints \u{1000}0 to \u{10ff}ff
+             //        first  F0 90 80 80  last F4 8F BF BF
+             //
+             // Use the UTF-8 syntax from the RFC
+             //
+             // https://tools.ietf.org/html/rfc3629
+             // UTF8-1      = %x00-7F
+             // UTF8-2      = %xC2-DF UTF8-tail
+             // UTF8-3      = %xE0 %xA0-BF UTF8-tail / %xE1-EC 2( UTF8-tail ) /
+             //               %xED %x80-9F UTF8-tail / %xEE-EF 2( UTF8-tail )
+             // UTF8-4      = %xF0 %x90-BF 2( UTF8-tail ) / %xF1-F3 3( UTF8-tail ) /
+             //               %xF4 %x80-8F 2( UTF8-tail )
+             match w {
+                 2 => {
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(1))
+                     }
+                 }
+                 3 => {
+                     match (first, next!()) {
+                         (0xE0, 0xA0..=0xBF)
+                         | (0xE1..=0xEC, 0x80..=0xBF)
+                         | (0xED, 0x80..=0x9F)
+                         | (0xEE..=0xEF, 0x80..=0xBF) => {}
+                         _ => err!(Some(1)),
+                     }
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(2))
+                     }
+                 }
+                 4 => {
+                     match (first, next!()) {
+                         (0xF0, 0x90..=0xBF) | (0xF1..=0xF3, 0x80..=0xBF) | (0xF4, 0x80..=0x8F) => {}
+                         _ => err!(Some(1)),
+                     }
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(2))
+                     }
+                     if next!() & !CONT_MASK != TAG_CONT_U8 {
+                         err!(Some(3))
+                     }
+                 }
+                 _ => err!(Some(1)),
+             }
+             index += 1;
+         } else {
+             // Ascii case, try to skip forward quickly.
+             // When the pointer is aligned, read 2 words of data per iteration
+             // until we find a word containing a non-ascii byte.
+             if align != usize::MAX && align.wrapping_sub(index) % usize_bytes == 0 {
+                 let ptr = v.as_ptr();
+                 while index < blocks_end {
+                     // SAFETY: since `align - index` and `ascii_block_size` are
+                     // multiples of `usize_bytes`, `block = ptr.add(index)` is
+                     // always aligned with a `usize` so it's safe to dereference
+                     // both `block` and `block.offset(1)`.
+                     unsafe {
+                         let block = ptr.add(index) as *const usize;
+                         // break if there is a nonascii byte
+                         let zu = contains_nonascii(*block);
+                         let zv = contains_nonascii(*block.offset(1));
+                         if zu | zv {
+                             break;
+                         }
+                     }
+                     index += ascii_block_size;
+                 }
+                 // step from the point where the wordwise loop stopped
+                 while index < len && v[index] < 128 {
+                     index += 1;
+                 }
+             } else {
+                 index += 1;
+             }
+         }
+     }
+ 
+     Ok(())
+ }
+ 
+ // https://tools.ietf.org/html/rfc3629
+ static UTF8_CHAR_WIDTH: [u8; 256] = [
+     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+     1, // 0x1F
+     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+     1, // 0x3F
+     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+     1, // 0x5F
+     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+     1, // 0x7F
+     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+     0, // 0x9F
+     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+     0, // 0xBF
+     0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+     2, // 0xDF
+     3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 0xEF
+     4, 4, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0xFF
+ ];
+ 
+ /// Given a first byte, determines how many bytes are in this UTF-8 character.
+ #[unstable(feature = "str_internals", issue = "none")]
+ #[inline]
+ pub fn utf8_char_width(b: u8) -> usize {
+     UTF8_CHAR_WIDTH[b as usize] as usize
+ }
+ 
+ /// Mask of the value bits of a continuation byte.
+ const CONT_MASK: u8 = 0b0011_1111;
+ /// Value of the tag bits (tag mask is !CONT_MASK) of a continuation byte.
+ const TAG_CONT_U8: u8 = 0b1000_0000;
+ 
+ // truncate `&str` to length at most equal to `max`
+ // return `true` if it were truncated, and the new str.
+ pub(super) fn truncate_to_char_boundary(s: &str, mut max: usize) -> (bool, &str) {
+     if max >= s.len() {
+         (false, s)
+     } else {
+         while !s.is_char_boundary(max) {
+             max -= 1;
+         }
+         (true, &s[..max])
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/sync/atomic.rs gcc-16-20251102/libgrust/rustc-lib/core/src/sync/atomic.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/sync/atomic.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/sync/atomic.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2780 ----
+ //! Atomic types
+ //!
+ //! Atomic types provide primitive shared-memory communication between
+ //! threads, and are the building blocks of other concurrent
+ //! types.
+ //!
+ //! This module defines atomic versions of a select number of primitive
+ //! types, including [`AtomicBool`], [`AtomicIsize`], [`AtomicUsize`],
+ //! [`AtomicI8`], [`AtomicU16`], etc.
+ //! Atomic types present operations that, when used correctly, synchronize
+ //! updates between threads.
+ //!
+ //! Each method takes an [`Ordering`] which represents the strength of
+ //! the memory barrier for that operation. These orderings are the
+ //! same as the [C++20 atomic orderings][1]. For more information see the [nomicon][2].
+ //!
+ //! [1]: https://en.cppreference.com/w/cpp/atomic/memory_order
+ //! [2]: ../../../nomicon/atomics.html
+ //!
+ //! Atomic variables are safe to share between threads (they implement [`Sync`])
+ //! but they do not themselves provide the mechanism for sharing and follow the
+ //! [threading model](../../../std/thread/index.html#the-threading-model) of Rust.
+ //! The most common way to share an atomic variable is to put it into an [`Arc`][arc] (an
+ //! atomically-reference-counted shared pointer).
+ //!
+ //! [arc]: ../../../std/sync/struct.Arc.html
+ //!
+ //! Atomic types may be stored in static variables, initialized using
+ //! the constant initializers like [`AtomicBool::new`]. Atomic statics
+ //! are often used for lazy global initialization.
+ //!
+ //! # Portability
+ //!
+ //! All atomic types in this module are guaranteed to be [lock-free] if they're
+ //! available. This means they don't internally acquire a global mutex. Atomic
+ //! types and operations are not guaranteed to be wait-free. This means that
+ //! operations like `fetch_or` may be implemented with a compare-and-swap loop.
+ //!
+ //! Atomic operations may be implemented at the instruction layer with
+ //! larger-size atomics. For example some platforms use 4-byte atomic
+ //! instructions to implement `AtomicI8`. Note that this emulation should not
+ //! have an impact on correctness of code, it's just something to be aware of.
+ //!
+ //! The atomic types in this module may not be available on all platforms. The
+ //! atomic types here are all widely available, however, and can generally be
+ //! relied upon existing. Some notable exceptions are:
+ //!
+ //! * PowerPC and MIPS platforms with 32-bit pointers do not have `AtomicU64` or
+ //!   `AtomicI64` types.
+ //! * ARM platforms like `armv5te` that aren't for Linux do not have any atomics
+ //!   at all.
+ //! * ARM targets with `thumbv6m` do not have atomic operations at all.
+ //!
+ //! Note that future platforms may be added that also do not have support for
+ //! some atomic operations. Maximally portable code will want to be careful
+ //! about which atomic types are used. `AtomicUsize` and `AtomicIsize` are
+ //! generally the most portable, but even then they're not available everywhere.
+ //! For reference, the `std` library requires pointer-sized atomics, although
+ //! `core` does not.
+ //!
+ //! Currently you'll need to use `#[cfg(target_arch)]` primarily to
+ //! conditionally compile in code with atomics. There is an unstable
+ //! `#[cfg(target_has_atomic)]` as well which may be stabilized in the future.
+ //!
+ //! [lock-free]: https://en.wikipedia.org/wiki/Non-blocking_algorithm
+ //!
+ //! # Examples
+ //!
+ //! A simple spinlock:
+ //!
+ //! ```
+ //! use std::sync::Arc;
+ //! use std::sync::atomic::{AtomicUsize, Ordering};
+ //! use std::thread;
+ //!
+ //! fn main() {
+ //!     let spinlock = Arc::new(AtomicUsize::new(1));
+ //!
+ //!     let spinlock_clone = Arc::clone(&spinlock);
+ //!     let thread = thread::spawn(move|| {
+ //!         spinlock_clone.store(0, Ordering::SeqCst);
+ //!     });
+ //!
+ //!     // Wait for the other thread to release the lock
+ //!     while spinlock.load(Ordering::SeqCst) != 0 {}
+ //!
+ //!     if let Err(panic) = thread.join() {
+ //!         println!("Thread had an error: {:?}", panic);
+ //!     }
+ //! }
+ //! ```
+ //!
+ //! Keep a global count of live threads:
+ //!
+ //! ```
+ //! use std::sync::atomic::{AtomicUsize, Ordering};
+ //!
+ //! static GLOBAL_THREAD_COUNT: AtomicUsize = AtomicUsize::new(0);
+ //!
+ //! let old_thread_count = GLOBAL_THREAD_COUNT.fetch_add(1, Ordering::SeqCst);
+ //! println!("live threads: {}", old_thread_count + 1);
+ //! ```
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ #![cfg_attr(not(target_has_atomic_load_store = "8"), allow(dead_code))]
+ #![cfg_attr(not(target_has_atomic_load_store = "8"), allow(unused_imports))]
+ 
+ use self::Ordering::*;
+ 
+ use crate::cell::UnsafeCell;
+ use crate::fmt;
+ use crate::intrinsics;
+ 
+ use crate::hint::spin_loop;
+ 
+ /// Signals the processor that it is inside a busy-wait spin-loop ("spin lock").
+ ///
+ /// This function is expected to be deprecated in favor of
+ /// [`hint::spin_loop`].
+ ///
+ /// **Note**: On platforms that do not support receiving spin-loop hints this function does not
+ /// do anything at all.
+ ///
+ /// [`hint::spin_loop`]: crate::hint::spin_loop
+ #[inline]
+ #[stable(feature = "spin_loop_hint", since = "1.24.0")]
+ pub fn spin_loop_hint() {
+     spin_loop()
+ }
+ 
+ /// A boolean type which can be safely shared between threads.
+ ///
+ /// This type has the same in-memory representation as a [`bool`].
+ ///
+ /// **Note**: This type is only available on platforms that support atomic
+ /// loads and stores of `u8`.
+ #[cfg(target_has_atomic_load_store = "8")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[repr(C, align(1))]
+ pub struct AtomicBool {
+     v: UnsafeCell<u8>,
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "8")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl Default for AtomicBool {
+     /// Creates an `AtomicBool` initialized to `false`.
+     #[inline]
+     fn default() -> Self {
+         Self::new(false)
+     }
+ }
+ 
+ // Send is implicitly implemented for AtomicBool.
+ #[cfg(target_has_atomic_load_store = "8")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl Sync for AtomicBool {}
+ 
+ /// A raw pointer type which can be safely shared between threads.
+ ///
+ /// This type has the same in-memory representation as a `*mut T`.
+ ///
+ /// **Note**: This type is only available on platforms that support atomic
+ /// loads and stores of pointers. Its size depends on the target pointer's size.
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[cfg_attr(target_pointer_width = "16", repr(C, align(2)))]
+ #[cfg_attr(target_pointer_width = "32", repr(C, align(4)))]
+ #[cfg_attr(target_pointer_width = "64", repr(C, align(8)))]
+ pub struct AtomicPtr<T> {
+     p: UnsafeCell<*mut T>,
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ impl<T> Default for AtomicPtr<T> {
+     /// Creates a null `AtomicPtr<T>`.
+     fn default() -> AtomicPtr<T> {
+         AtomicPtr::new(crate::ptr::null_mut())
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T> Send for AtomicPtr<T> {}
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ unsafe impl<T> Sync for AtomicPtr<T> {}
+ 
+ /// Atomic memory orderings
+ ///
+ /// Memory orderings specify the way atomic operations synchronize memory.
+ /// In its weakest [`Ordering::Relaxed`], only the memory directly touched by the
+ /// operation is synchronized. On the other hand, a store-load pair of [`Ordering::SeqCst`]
+ /// operations synchronize other memory while additionally preserving a total order of such
+ /// operations across all threads.
+ ///
+ /// Rust's memory orderings are [the same as those of
+ /// C++20](https://en.cppreference.com/w/cpp/atomic/memory_order).
+ ///
+ /// For more information see the [nomicon].
+ ///
+ /// [nomicon]: ../../../nomicon/atomics.html
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)]
+ #[non_exhaustive]
+ pub enum Ordering {
+     /// No ordering constraints, only atomic operations.
+     ///
+     /// Corresponds to [`memory_order_relaxed`] in C++20.
+     ///
+     /// [`memory_order_relaxed`]: https://en.cppreference.com/w/cpp/atomic/memory_order#Relaxed_ordering
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Relaxed,
+     /// When coupled with a store, all previous operations become ordered
+     /// before any load of this value with [`Acquire`] (or stronger) ordering.
+     /// In particular, all previous writes become visible to all threads
+     /// that perform an [`Acquire`] (or stronger) load of this value.
+     ///
+     /// Notice that using this ordering for an operation that combines loads
+     /// and stores leads to a [`Relaxed`] load operation!
+     ///
+     /// This ordering is only applicable for operations that can perform a store.
+     ///
+     /// Corresponds to [`memory_order_release`] in C++20.
+     ///
+     /// [`memory_order_release`]: https://en.cppreference.com/w/cpp/atomic/memory_order#Release-Acquire_ordering
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Release,
+     /// When coupled with a load, if the loaded value was written by a store operation with
+     /// [`Release`] (or stronger) ordering, then all subsequent operations
+     /// become ordered after that store. In particular, all subsequent loads will see data
+     /// written before the store.
+     ///
+     /// Notice that using this ordering for an operation that combines loads
+     /// and stores leads to a [`Relaxed`] store operation!
+     ///
+     /// This ordering is only applicable for operations that can perform a load.
+     ///
+     /// Corresponds to [`memory_order_acquire`] in C++20.
+     ///
+     /// [`memory_order_acquire`]: https://en.cppreference.com/w/cpp/atomic/memory_order#Release-Acquire_ordering
+     #[stable(feature = "rust1", since = "1.0.0")]
+     Acquire,
+     /// Has the effects of both [`Acquire`] and [`Release`] together:
+     /// For loads it uses [`Acquire`] ordering. For stores it uses the [`Release`] ordering.
+     ///
+     /// Notice that in the case of `compare_and_swap`, it is possible that the operation ends up
+     /// not performing any store and hence it has just [`Acquire`] ordering. However,
+     /// `AcqRel` will never perform [`Relaxed`] accesses.
+     ///
+     /// This ordering is only applicable for operations that combine both loads and stores.
+     ///
+     /// Corresponds to [`memory_order_acq_rel`] in C++20.
+     ///
+     /// [`memory_order_acq_rel`]: https://en.cppreference.com/w/cpp/atomic/memory_order#Release-Acquire_ordering
+     #[stable(feature = "rust1", since = "1.0.0")]
+     AcqRel,
+     /// Like [`Acquire`]/[`Release`]/[`AcqRel`] (for load, store, and load-with-store
+     /// operations, respectively) with the additional guarantee that all threads see all
+     /// sequentially consistent operations in the same order.
+     ///
+     /// Corresponds to [`memory_order_seq_cst`] in C++20.
+     ///
+     /// [`memory_order_seq_cst`]: https://en.cppreference.com/w/cpp/atomic/memory_order#Sequentially-consistent_ordering
+     #[stable(feature = "rust1", since = "1.0.0")]
+     SeqCst,
+ }
+ 
+ /// An [`AtomicBool`] initialized to `false`.
+ #[cfg(target_has_atomic_load_store = "8")]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ #[rustc_deprecated(
+     since = "1.34.0",
+     reason = "the `new` function is now preferred",
+     suggestion = "AtomicBool::new(false)"
+ )]
+ pub const ATOMIC_BOOL_INIT: AtomicBool = AtomicBool::new(false);
+ 
+ #[cfg(target_has_atomic_load_store = "8")]
+ impl AtomicBool {
+     /// Creates a new `AtomicBool`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::AtomicBool;
+     ///
+     /// let atomic_true  = AtomicBool::new(true);
+     /// let atomic_false = AtomicBool::new(false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_atomic_new", since = "1.32.0")]
+     pub const fn new(v: bool) -> AtomicBool {
+         AtomicBool { v: UnsafeCell::new(v as u8) }
+     }
+ 
+     /// Returns a mutable reference to the underlying [`bool`].
+     ///
+     /// This is safe because the mutable reference guarantees that no other threads are
+     /// concurrently accessing the atomic data.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let mut some_bool = AtomicBool::new(true);
+     /// assert_eq!(*some_bool.get_mut(), true);
+     /// *some_bool.get_mut() = false;
+     /// assert_eq!(some_bool.load(Ordering::SeqCst), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "atomic_access", since = "1.15.0")]
+     pub fn get_mut(&mut self) -> &mut bool {
+         // SAFETY: the mutable reference guarantees unique ownership.
+         unsafe { &mut *(self.v.get() as *mut bool) }
+     }
+ 
+     /// Get atomic access to a `&mut bool`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(atomic_from_mut)]
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let mut some_bool = true;
+     /// let a = AtomicBool::from_mut(&mut some_bool);
+     /// a.store(false, Ordering::Relaxed);
+     /// assert_eq!(some_bool, false);
+     /// ```
+     #[inline]
+     #[cfg(target_has_atomic_equal_alignment = "8")]
+     #[unstable(feature = "atomic_from_mut", issue = "76314")]
+     pub fn from_mut(v: &mut bool) -> &Self {
+         // SAFETY: the mutable reference guarantees unique ownership, and
+         // alignment of both `bool` and `Self` is 1.
+         unsafe { &*(v as *mut bool as *mut Self) }
+     }
+ 
+     /// Consumes the atomic and returns the contained value.
+     ///
+     /// This is safe because passing `self` by value guarantees that no other threads are
+     /// concurrently accessing the atomic data.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::AtomicBool;
+     ///
+     /// let some_bool = AtomicBool::new(true);
+     /// assert_eq!(some_bool.into_inner(), true);
+     /// ```
+     #[inline]
+     #[stable(feature = "atomic_access", since = "1.15.0")]
+     #[rustc_const_unstable(feature = "const_cell_into_inner", issue = "78729")]
+     pub const fn into_inner(self) -> bool {
+         self.v.into_inner() != 0
+     }
+ 
+     /// Loads a value from the bool.
+     ///
+     /// `load` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. Possible values are [`SeqCst`], [`Acquire`] and [`Relaxed`].
+     ///
+     /// # Panics
+     ///
+     /// Panics if `order` is [`Release`] or [`AcqRel`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let some_bool = AtomicBool::new(true);
+     ///
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), true);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn load(&self, order: Ordering) -> bool {
+         // SAFETY: any data races are prevented by atomic intrinsics and the raw
+         // pointer passed in is valid because we got it from a reference.
+         unsafe { atomic_load(self.v.get(), order) != 0 }
+     }
+ 
+     /// Stores a value into the bool.
+     ///
+     /// `store` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. Possible values are [`SeqCst`], [`Release`] and [`Relaxed`].
+     ///
+     /// # Panics
+     ///
+     /// Panics if `order` is [`Acquire`] or [`AcqRel`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let some_bool = AtomicBool::new(true);
+     ///
+     /// some_bool.store(false, Ordering::Relaxed);
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn store(&self, val: bool, order: Ordering) {
+         // SAFETY: any data races are prevented by atomic intrinsics and the raw
+         // pointer passed in is valid because we got it from a reference.
+         unsafe {
+             atomic_store(self.v.get(), val as u8, order);
+         }
+     }
+ 
+     /// Stores a value into the bool, returning the previous value.
+     ///
+     /// `swap` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. All ordering modes are possible. Note that using
+     /// [`Acquire`] makes the store part of this operation [`Relaxed`], and
+     /// using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let some_bool = AtomicBool::new(true);
+     ///
+     /// assert_eq!(some_bool.swap(false, Ordering::Relaxed), true);
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn swap(&self, val: bool, order: Ordering) -> bool {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe { atomic_swap(self.v.get(), val as u8, order) != 0 }
+     }
+ 
+     /// Stores a value into the [`bool`] if the current value is the same as the `current` value.
+     ///
+     /// The return value is always the previous value. If it is equal to `current`, then the value
+     /// was updated.
+     ///
+     /// `compare_and_swap` also takes an [`Ordering`] argument which describes the memory
+     /// ordering of this operation. Notice that even when using [`AcqRel`], the operation
+     /// might fail and hence just perform an `Acquire` load, but not have `Release` semantics.
+     /// Using [`Acquire`] makes the store part of this operation [`Relaxed`] if it
+     /// happens, and using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let some_bool = AtomicBool::new(true);
+     ///
+     /// assert_eq!(some_bool.compare_and_swap(true, false, Ordering::Relaxed), true);
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), false);
+     ///
+     /// assert_eq!(some_bool.compare_and_swap(true, true, Ordering::Relaxed), false);
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn compare_and_swap(&self, current: bool, new: bool, order: Ordering) -> bool {
+         match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) {
+             Ok(x) => x,
+             Err(x) => x,
+         }
+     }
+ 
+     /// Stores a value into the [`bool`] if the current value is the same as the `current` value.
+     ///
+     /// The return value is a result indicating whether the new value was written and containing
+     /// the previous value. On success this value is guaranteed to be equal to `current`.
+     ///
+     /// `compare_exchange` takes two [`Ordering`] arguments to describe the memory
+     /// ordering of this operation. The first describes the required ordering if the
+     /// operation succeeds while the second describes the required ordering when the
+     /// operation fails. Using [`Acquire`] as success ordering makes the store part
+     /// of this operation [`Relaxed`], and using [`Release`] makes the successful load
+     /// [`Relaxed`]. The failure ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+     /// and must be equivalent to or weaker than the success ordering.
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let some_bool = AtomicBool::new(true);
+     ///
+     /// assert_eq!(some_bool.compare_exchange(true,
+     ///                                       false,
+     ///                                       Ordering::Acquire,
+     ///                                       Ordering::Relaxed),
+     ///            Ok(true));
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), false);
+     ///
+     /// assert_eq!(some_bool.compare_exchange(true, true,
+     ///                                       Ordering::SeqCst,
+     ///                                       Ordering::Acquire),
+     ///            Err(false));
+     /// assert_eq!(some_bool.load(Ordering::Relaxed), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn compare_exchange(
+         &self,
+         current: bool,
+         new: bool,
+         success: Ordering,
+         failure: Ordering,
+     ) -> Result<bool, bool> {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         match unsafe {
+             atomic_compare_exchange(self.v.get(), current as u8, new as u8, success, failure)
+         } {
+             Ok(x) => Ok(x != 0),
+             Err(x) => Err(x != 0),
+         }
+     }
+ 
+     /// Stores a value into the [`bool`] if the current value is the same as the `current` value.
+     ///
+     /// Unlike [`AtomicBool::compare_exchange`], this function is allowed to spuriously fail even when the
+     /// comparison succeeds, which can result in more efficient code on some platforms. The
+     /// return value is a result indicating whether the new value was written and containing the
+     /// previous value.
+     ///
+     /// `compare_exchange_weak` takes two [`Ordering`] arguments to describe the memory
+     /// ordering of this operation. The first describes the required ordering if the
+     /// operation succeeds while the second describes the required ordering when the
+     /// operation fails. Using [`Acquire`] as success ordering makes the store part
+     /// of this operation [`Relaxed`], and using [`Release`] makes the successful load
+     /// [`Relaxed`]. The failure ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+     /// and must be equivalent to or weaker than the success ordering.
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let val = AtomicBool::new(false);
+     ///
+     /// let new = true;
+     /// let mut old = val.load(Ordering::Relaxed);
+     /// loop {
+     ///     match val.compare_exchange_weak(old, new, Ordering::SeqCst, Ordering::Relaxed) {
+     ///         Ok(_) => break,
+     ///         Err(x) => old = x,
+     ///     }
+     /// }
+     /// ```
+     #[inline]
+     #[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn compare_exchange_weak(
+         &self,
+         current: bool,
+         new: bool,
+         success: Ordering,
+         failure: Ordering,
+     ) -> Result<bool, bool> {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         match unsafe {
+             atomic_compare_exchange_weak(self.v.get(), current as u8, new as u8, success, failure)
+         } {
+             Ok(x) => Ok(x != 0),
+             Err(x) => Err(x != 0),
+         }
+     }
+ 
+     /// Logical "and" with a boolean value.
+     ///
+     /// Performs a logical "and" operation on the current value and the argument `val`, and sets
+     /// the new value to the result.
+     ///
+     /// Returns the previous value.
+     ///
+     /// `fetch_and` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. All ordering modes are possible. Note that using
+     /// [`Acquire`] makes the store part of this operation [`Relaxed`], and
+     /// using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_and(false, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), false);
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_and(true, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), true);
+     ///
+     /// let foo = AtomicBool::new(false);
+     /// assert_eq!(foo.fetch_and(false, Ordering::SeqCst), false);
+     /// assert_eq!(foo.load(Ordering::SeqCst), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn fetch_and(&self, val: bool, order: Ordering) -> bool {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe { atomic_and(self.v.get(), val as u8, order) != 0 }
+     }
+ 
+     /// Logical "nand" with a boolean value.
+     ///
+     /// Performs a logical "nand" operation on the current value and the argument `val`, and sets
+     /// the new value to the result.
+     ///
+     /// Returns the previous value.
+     ///
+     /// `fetch_nand` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. All ordering modes are possible. Note that using
+     /// [`Acquire`] makes the store part of this operation [`Relaxed`], and
+     /// using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_nand(false, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), true);
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_nand(true, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst) as usize, 0);
+     /// assert_eq!(foo.load(Ordering::SeqCst), false);
+     ///
+     /// let foo = AtomicBool::new(false);
+     /// assert_eq!(foo.fetch_nand(false, Ordering::SeqCst), false);
+     /// assert_eq!(foo.load(Ordering::SeqCst), true);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn fetch_nand(&self, val: bool, order: Ordering) -> bool {
+         // We can't use atomic_nand here because it can result in a bool with
+         // an invalid value. This happens because the atomic operation is done
+         // with an 8-bit integer internally, which would set the upper 7 bits.
+         // So we just use fetch_xor or swap instead.
+         if val {
+             // !(x & true) == !x
+             // We must invert the bool.
+             self.fetch_xor(true, order)
+         } else {
+             // !(x & false) == true
+             // We must set the bool to true.
+             self.swap(true, order)
+         }
+     }
+ 
+     /// Logical "or" with a boolean value.
+     ///
+     /// Performs a logical "or" operation on the current value and the argument `val`, and sets the
+     /// new value to the result.
+     ///
+     /// Returns the previous value.
+     ///
+     /// `fetch_or` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. All ordering modes are possible. Note that using
+     /// [`Acquire`] makes the store part of this operation [`Relaxed`], and
+     /// using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_or(false, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), true);
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_or(true, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), true);
+     ///
+     /// let foo = AtomicBool::new(false);
+     /// assert_eq!(foo.fetch_or(false, Ordering::SeqCst), false);
+     /// assert_eq!(foo.load(Ordering::SeqCst), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn fetch_or(&self, val: bool, order: Ordering) -> bool {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe { atomic_or(self.v.get(), val as u8, order) != 0 }
+     }
+ 
+     /// Logical "xor" with a boolean value.
+     ///
+     /// Performs a logical "xor" operation on the current value and the argument `val`, and sets
+     /// the new value to the result.
+     ///
+     /// Returns the previous value.
+     ///
+     /// `fetch_xor` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. All ordering modes are possible. Note that using
+     /// [`Acquire`] makes the store part of this operation [`Relaxed`], and
+     /// using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_xor(false, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), true);
+     ///
+     /// let foo = AtomicBool::new(true);
+     /// assert_eq!(foo.fetch_xor(true, Ordering::SeqCst), true);
+     /// assert_eq!(foo.load(Ordering::SeqCst), false);
+     ///
+     /// let foo = AtomicBool::new(false);
+     /// assert_eq!(foo.fetch_xor(false, Ordering::SeqCst), false);
+     /// assert_eq!(foo.load(Ordering::SeqCst), false);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn fetch_xor(&self, val: bool, order: Ordering) -> bool {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe { atomic_xor(self.v.get(), val as u8, order) != 0 }
+     }
+ 
+     /// Returns a mutable pointer to the underlying [`bool`].
+     ///
+     /// Doing non-atomic reads and writes on the resulting integer can be a data race.
+     /// This method is mostly useful for FFI, where the function signature may use
+     /// `*mut bool` instead of `&AtomicBool`.
+     ///
+     /// Returning an `*mut` pointer from a shared reference to this atomic is safe because the
+     /// atomic types work with interior mutability. All modifications of an atomic change the value
+     /// through a shared reference, and can do so safely as long as they use atomic operations. Any
+     /// use of the returned raw pointer requires an `unsafe` block and still has to uphold the same
+     /// restriction: operations on it must be atomic.
+     ///
+     /// # Examples
+     ///
+     /// ```ignore (extern-declaration)
+     /// # fn main() {
+     /// use std::sync::atomic::AtomicBool;
+     /// extern {
+     ///     fn my_atomic_op(arg: *mut bool);
+     /// }
+     ///
+     /// let mut atomic = AtomicBool::new(true);
+     /// unsafe {
+     ///     my_atomic_op(atomic.as_mut_ptr());
+     /// }
+     /// # }
+     /// ```
+     #[inline]
+     #[unstable(feature = "atomic_mut_ptr", reason = "recently added", issue = "66893")]
+     pub fn as_mut_ptr(&self) -> *mut bool {
+         self.v.get() as *mut bool
+     }
+ 
+     /// Fetches the value, and applies a function to it that returns an optional
+     /// new value. Returns a `Result` of `Ok(previous_value)` if the function
+     /// returned `Some(_)`, else `Err(previous_value)`.
+     ///
+     /// Note: This may call the function multiple times if the value has been
+     /// changed from other threads in the meantime, as long as the function
+     /// returns `Some(_)`, but the function will have been applied only once to
+     /// the stored value.
+     ///
+     /// `fetch_update` takes two [`Ordering`] arguments to describe the memory
+     /// ordering of this operation. The first describes the required ordering for
+     /// when the operation finally succeeds while the second describes the
+     /// required ordering for loads. These correspond to the success and failure
+     /// orderings of [`AtomicBool::compare_exchange`] respectively.
+     ///
+     /// Using [`Acquire`] as success ordering makes the store part of this
+     /// operation [`Relaxed`], and using [`Release`] makes the final successful
+     /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`],
+     /// [`Acquire`] or [`Relaxed`] and must be equivalent to or weaker than the
+     /// success ordering.
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on `u8`.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(atomic_fetch_update)]
+     /// use std::sync::atomic::{AtomicBool, Ordering};
+     ///
+     /// let x = AtomicBool::new(false);
+     /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(false));
+     /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(false));
+     /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(true));
+     /// assert_eq!(x.load(Ordering::SeqCst), false);
+     /// ```
+     #[inline]
+     #[unstable(feature = "atomic_fetch_update", reason = "recently added", issue = "78639")]
+     #[cfg(target_has_atomic = "8")]
+     pub fn fetch_update<F>(
+         &self,
+         set_order: Ordering,
+         fetch_order: Ordering,
+         mut f: F,
+     ) -> Result<bool, bool>
+     where
+         F: FnMut(bool) -> Option<bool>,
+     {
+         let mut prev = self.load(fetch_order);
+         while let Some(next) = f(prev) {
+             match self.compare_exchange_weak(prev, next, set_order, fetch_order) {
+                 x @ Ok(_) => return x,
+                 Err(next_prev) => prev = next_prev,
+             }
+         }
+         Err(prev)
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ impl<T> AtomicPtr<T> {
+     /// Creates a new `AtomicPtr`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::AtomicPtr;
+     ///
+     /// let ptr = &mut 5;
+     /// let atomic_ptr  = AtomicPtr::new(ptr);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[rustc_const_stable(feature = "const_atomic_new", since = "1.32.0")]
+     pub const fn new(p: *mut T) -> AtomicPtr<T> {
+         AtomicPtr { p: UnsafeCell::new(p) }
+     }
+ 
+     /// Returns a mutable reference to the underlying pointer.
+     ///
+     /// This is safe because the mutable reference guarantees that no other threads are
+     /// concurrently accessing the atomic data.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let mut atomic_ptr = AtomicPtr::new(&mut 10);
+     /// *atomic_ptr.get_mut() = &mut 5;
+     /// assert_eq!(unsafe { *atomic_ptr.load(Ordering::SeqCst) }, 5);
+     /// ```
+     #[inline]
+     #[stable(feature = "atomic_access", since = "1.15.0")]
+     pub fn get_mut(&mut self) -> &mut *mut T {
+         self.p.get_mut()
+     }
+ 
+     /// Get atomic access to a pointer.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(atomic_from_mut)]
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let mut some_ptr = &mut 123 as *mut i32;
+     /// let a = AtomicPtr::from_mut(&mut some_ptr);
+     /// a.store(&mut 456, Ordering::Relaxed);
+     /// assert_eq!(unsafe { *some_ptr }, 456);
+     /// ```
+     #[inline]
+     #[cfg(target_has_atomic_equal_alignment = "ptr")]
+     #[unstable(feature = "atomic_from_mut", issue = "76314")]
+     pub fn from_mut(v: &mut *mut T) -> &Self {
+         use crate::mem::align_of;
+         let [] = [(); align_of::<AtomicPtr<()>>() - align_of::<*mut ()>()];
+         // SAFETY:
+         //  - the mutable reference guarantees unique ownership.
+         //  - the alignment of `*mut T` and `Self` is the same on all platforms
+         //    supported by rust, as verified above.
+         unsafe { &*(v as *mut *mut T as *mut Self) }
+     }
+ 
+     /// Consumes the atomic and returns the contained value.
+     ///
+     /// This is safe because passing `self` by value guarantees that no other threads are
+     /// concurrently accessing the atomic data.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::AtomicPtr;
+     ///
+     /// let atomic_ptr = AtomicPtr::new(&mut 5);
+     /// assert_eq!(unsafe { *atomic_ptr.into_inner() }, 5);
+     /// ```
+     #[inline]
+     #[stable(feature = "atomic_access", since = "1.15.0")]
+     #[rustc_const_unstable(feature = "const_cell_into_inner", issue = "78729")]
+     pub const fn into_inner(self) -> *mut T {
+         self.p.into_inner()
+     }
+ 
+     /// Loads a value from the pointer.
+     ///
+     /// `load` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. Possible values are [`SeqCst`], [`Acquire`] and [`Relaxed`].
+     ///
+     /// # Panics
+     ///
+     /// Panics if `order` is [`Release`] or [`AcqRel`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let ptr = &mut 5;
+     /// let some_ptr  = AtomicPtr::new(ptr);
+     ///
+     /// let value = some_ptr.load(Ordering::Relaxed);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn load(&self, order: Ordering) -> *mut T {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe { atomic_load(self.p.get() as *mut usize, order) as *mut T }
+     }
+ 
+     /// Stores a value into the pointer.
+     ///
+     /// `store` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. Possible values are [`SeqCst`], [`Release`] and [`Relaxed`].
+     ///
+     /// # Panics
+     ///
+     /// Panics if `order` is [`Acquire`] or [`AcqRel`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let ptr = &mut 5;
+     /// let some_ptr  = AtomicPtr::new(ptr);
+     ///
+     /// let other_ptr = &mut 10;
+     ///
+     /// some_ptr.store(other_ptr, Ordering::Relaxed);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     pub fn store(&self, ptr: *mut T, order: Ordering) {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe {
+             atomic_store(self.p.get() as *mut usize, ptr as usize, order);
+         }
+     }
+ 
+     /// Stores a value into the pointer, returning the previous value.
+     ///
+     /// `swap` takes an [`Ordering`] argument which describes the memory ordering
+     /// of this operation. All ordering modes are possible. Note that using
+     /// [`Acquire`] makes the store part of this operation [`Relaxed`], and
+     /// using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on pointers.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let ptr = &mut 5;
+     /// let some_ptr  = AtomicPtr::new(ptr);
+     ///
+     /// let other_ptr = &mut 10;
+     ///
+     /// let value = some_ptr.swap(other_ptr, Ordering::Relaxed);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "ptr")]
+     pub fn swap(&self, ptr: *mut T, order: Ordering) -> *mut T {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe { atomic_swap(self.p.get() as *mut usize, ptr as usize, order) as *mut T }
+     }
+ 
+     /// Stores a value into the pointer if the current value is the same as the `current` value.
+     ///
+     /// The return value is always the previous value. If it is equal to `current`, then the value
+     /// was updated.
+     ///
+     /// `compare_and_swap` also takes an [`Ordering`] argument which describes the memory
+     /// ordering of this operation. Notice that even when using [`AcqRel`], the operation
+     /// might fail and hence just perform an `Acquire` load, but not have `Release` semantics.
+     /// Using [`Acquire`] makes the store part of this operation [`Relaxed`] if it
+     /// happens, and using [`Release`] makes the load part [`Relaxed`].
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on pointers.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let ptr = &mut 5;
+     /// let some_ptr  = AtomicPtr::new(ptr);
+     ///
+     /// let other_ptr   = &mut 10;
+     ///
+     /// let value = some_ptr.compare_and_swap(ptr, other_ptr, Ordering::Relaxed);
+     /// ```
+     #[inline]
+     #[stable(feature = "rust1", since = "1.0.0")]
+     #[cfg(target_has_atomic = "ptr")]
+     pub fn compare_and_swap(&self, current: *mut T, new: *mut T, order: Ordering) -> *mut T {
+         match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) {
+             Ok(x) => x,
+             Err(x) => x,
+         }
+     }
+ 
+     /// Stores a value into the pointer if the current value is the same as the `current` value.
+     ///
+     /// The return value is a result indicating whether the new value was written and containing
+     /// the previous value. On success this value is guaranteed to be equal to `current`.
+     ///
+     /// `compare_exchange` takes two [`Ordering`] arguments to describe the memory
+     /// ordering of this operation. The first describes the required ordering if the
+     /// operation succeeds while the second describes the required ordering when the
+     /// operation fails. Using [`Acquire`] as success ordering makes the store part
+     /// of this operation [`Relaxed`], and using [`Release`] makes the successful load
+     /// [`Relaxed`]. The failure ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+     /// and must be equivalent to or weaker than the success ordering.
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on pointers.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let ptr = &mut 5;
+     /// let some_ptr  = AtomicPtr::new(ptr);
+     ///
+     /// let other_ptr   = &mut 10;
+     ///
+     /// let value = some_ptr.compare_exchange(ptr, other_ptr,
+     ///                                       Ordering::SeqCst, Ordering::Relaxed);
+     /// ```
+     #[inline]
+     #[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
+     #[cfg(target_has_atomic = "ptr")]
+     pub fn compare_exchange(
+         &self,
+         current: *mut T,
+         new: *mut T,
+         success: Ordering,
+         failure: Ordering,
+     ) -> Result<*mut T, *mut T> {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe {
+             let res = atomic_compare_exchange(
+                 self.p.get() as *mut usize,
+                 current as usize,
+                 new as usize,
+                 success,
+                 failure,
+             );
+             match res {
+                 Ok(x) => Ok(x as *mut T),
+                 Err(x) => Err(x as *mut T),
+             }
+         }
+     }
+ 
+     /// Stores a value into the pointer if the current value is the same as the `current` value.
+     ///
+     /// Unlike [`AtomicPtr::compare_exchange`], this function is allowed to spuriously fail even when the
+     /// comparison succeeds, which can result in more efficient code on some platforms. The
+     /// return value is a result indicating whether the new value was written and containing the
+     /// previous value.
+     ///
+     /// `compare_exchange_weak` takes two [`Ordering`] arguments to describe the memory
+     /// ordering of this operation. The first describes the required ordering if the
+     /// operation succeeds while the second describes the required ordering when the
+     /// operation fails. Using [`Acquire`] as success ordering makes the store part
+     /// of this operation [`Relaxed`], and using [`Release`] makes the successful load
+     /// [`Relaxed`]. The failure ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+     /// and must be equivalent to or weaker than the success ordering.
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on pointers.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let some_ptr = AtomicPtr::new(&mut 5);
+     ///
+     /// let new = &mut 10;
+     /// let mut old = some_ptr.load(Ordering::Relaxed);
+     /// loop {
+     ///     match some_ptr.compare_exchange_weak(old, new, Ordering::SeqCst, Ordering::Relaxed) {
+     ///         Ok(_) => break,
+     ///         Err(x) => old = x,
+     ///     }
+     /// }
+     /// ```
+     #[inline]
+     #[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
+     #[cfg(target_has_atomic = "ptr")]
+     pub fn compare_exchange_weak(
+         &self,
+         current: *mut T,
+         new: *mut T,
+         success: Ordering,
+         failure: Ordering,
+     ) -> Result<*mut T, *mut T> {
+         // SAFETY: data races are prevented by atomic intrinsics.
+         unsafe {
+             let res = atomic_compare_exchange_weak(
+                 self.p.get() as *mut usize,
+                 current as usize,
+                 new as usize,
+                 success,
+                 failure,
+             );
+             match res {
+                 Ok(x) => Ok(x as *mut T),
+                 Err(x) => Err(x as *mut T),
+             }
+         }
+     }
+ 
+     /// Fetches the value, and applies a function to it that returns an optional
+     /// new value. Returns a `Result` of `Ok(previous_value)` if the function
+     /// returned `Some(_)`, else `Err(previous_value)`.
+     ///
+     /// Note: This may call the function multiple times if the value has been
+     /// changed from other threads in the meantime, as long as the function
+     /// returns `Some(_)`, but the function will have been applied only once to
+     /// the stored value.
+     ///
+     /// `fetch_update` takes two [`Ordering`] arguments to describe the memory
+     /// ordering of this operation. The first describes the required ordering for
+     /// when the operation finally succeeds while the second describes the
+     /// required ordering for loads. These correspond to the success and failure
+     /// orderings of [`AtomicPtr::compare_exchange`] respectively.
+     ///
+     /// Using [`Acquire`] as success ordering makes the store part of this
+     /// operation [`Relaxed`], and using [`Release`] makes the final successful
+     /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`],
+     /// [`Acquire`] or [`Relaxed`] and must be equivalent to or weaker than the
+     /// success ordering.
+     ///
+     /// **Note:** This method is only available on platforms that support atomic
+     /// operations on pointers.
+     ///
+     /// # Examples
+     ///
+     /// ```rust
+     /// #![feature(atomic_fetch_update)]
+     /// use std::sync::atomic::{AtomicPtr, Ordering};
+     ///
+     /// let ptr: *mut _ = &mut 5;
+     /// let some_ptr = AtomicPtr::new(ptr);
+     ///
+     /// let new: *mut _ = &mut 10;
+     /// assert_eq!(some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(ptr));
+     /// let result = some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| {
+     ///     if x == ptr {
+     ///         Some(new)
+     ///     } else {
+     ///         None
+     ///     }
+     /// });
+     /// assert_eq!(result, Ok(ptr));
+     /// assert_eq!(some_ptr.load(Ordering::SeqCst), new);
+     /// ```
+     #[inline]
+     #[unstable(feature = "atomic_fetch_update", reason = "recently added", issue = "78639")]
+     #[cfg(target_has_atomic = "ptr")]
+     pub fn fetch_update<F>(
+         &self,
+         set_order: Ordering,
+         fetch_order: Ordering,
+         mut f: F,
+     ) -> Result<*mut T, *mut T>
+     where
+         F: FnMut(*mut T) -> Option<*mut T>,
+     {
+         let mut prev = self.load(fetch_order);
+         while let Some(next) = f(prev) {
+             match self.compare_exchange_weak(prev, next, set_order, fetch_order) {
+                 x @ Ok(_) => return x,
+                 Err(next_prev) => prev = next_prev,
+             }
+         }
+         Err(prev)
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "8")]
+ #[stable(feature = "atomic_bool_from", since = "1.24.0")]
+ impl From<bool> for AtomicBool {
+     /// Converts a `bool` into an `AtomicBool`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::sync::atomic::AtomicBool;
+     /// let atomic_bool = AtomicBool::from(true);
+     /// assert_eq!(format!("{:?}", atomic_bool), "true")
+     /// ```
+     #[inline]
+     fn from(b: bool) -> Self {
+         Self::new(b)
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "atomic_from", since = "1.23.0")]
+ impl<T> From<*mut T> for AtomicPtr<T> {
+     #[inline]
+     fn from(p: *mut T) -> Self {
+         Self::new(p)
+     }
+ }
+ 
+ #[allow(unused_macros)] // This macro ends up being unused on some architectures.
+ macro_rules! if_not_8_bit {
+     (u8, $($tt:tt)*) => { "" };
+     (i8, $($tt:tt)*) => { "" };
+     ($_:ident, $($tt:tt)*) => { $($tt)* };
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "8")]
+ macro_rules! atomic_int {
+     ($cfg_cas:meta,
+      $cfg_align:meta,
+      $stable:meta,
+      $stable_cxchg:meta,
+      $stable_debug:meta,
+      $stable_access:meta,
+      $stable_from:meta,
+      $stable_nand:meta,
+      $const_stable:meta,
+      $stable_init_const:meta,
+      $s_int_type:literal, $int_ref:expr,
+      $extra_feature:expr,
+      $min_fn:ident, $max_fn:ident,
+      $align:expr,
+      $atomic_new:expr,
+      $int_type:ident $atomic_type:ident $atomic_init:ident) => {
+         /// An integer type which can be safely shared between threads.
+         ///
+         /// This type has the same in-memory representation as the underlying
+         /// integer type, [`
+         #[doc = $s_int_type]
+         /// `](
+         #[doc = $int_ref]
+         /// ). For more about the differences between atomic types and
+         /// non-atomic types as well as information about the portability of
+         /// this type, please see the [module-level documentation].
+         ///
+         /// **Note:** This type is only available on platforms that support
+         /// atomic loads and stores of [`
+         #[doc = $s_int_type]
+         /// `](
+         #[doc = $int_ref]
+         /// ).
+         ///
+         /// [module-level documentation]: crate::sync::atomic
+         #[$stable]
+         #[repr(C, align($align))]
+         pub struct $atomic_type {
+             v: UnsafeCell<$int_type>,
+         }
+ 
+         /// An atomic integer initialized to `0`.
+         #[$stable_init_const]
+         #[rustc_deprecated(
+             since = "1.34.0",
+             reason = "the `new` function is now preferred",
+             suggestion = $atomic_new,
+         )]
+         pub const $atomic_init: $atomic_type = $atomic_type::new(0);
+ 
+         #[$stable]
+         impl Default for $atomic_type {
+             #[inline]
+             fn default() -> Self {
+                 Self::new(Default::default())
+             }
+         }
+ 
+         #[$stable_from]
+         impl From<$int_type> for $atomic_type {
+             doc_comment! {
+                 concat!(
+ "Converts an `", stringify!($int_type), "` into an `", stringify!($atomic_type), "`."),
+                 #[inline]
+                 fn from(v: $int_type) -> Self { Self::new(v) }
+             }
+         }
+ 
+         #[$stable_debug]
+         impl fmt::Debug for $atomic_type {
+             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt::Debug::fmt(&self.load(Ordering::SeqCst), f)
+             }
+         }
+ 
+         // Send is implicitly implemented.
+         #[$stable]
+         unsafe impl Sync for $atomic_type {}
+ 
+         impl $atomic_type {
+             doc_comment! {
+                 concat!("Creates a new atomic integer.
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::", stringify!($atomic_type), ";
+ 
+ let atomic_forty_two = ", stringify!($atomic_type), "::new(42);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$const_stable]
+                 pub const fn new(v: $int_type) -> Self {
+                     Self {v: UnsafeCell::new(v)}
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns a mutable reference to the underlying integer.
+ 
+ This is safe because the mutable reference guarantees that no other threads are
+ concurrently accessing the atomic data.
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let mut some_var = ", stringify!($atomic_type), "::new(10);
+ assert_eq!(*some_var.get_mut(), 10);
+ *some_var.get_mut() = 5;
+ assert_eq!(some_var.load(Ordering::SeqCst), 5);
+ ```"),
+                 #[inline]
+                 #[$stable_access]
+                 pub fn get_mut(&mut self) -> &mut $int_type {
+                     self.v.get_mut()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Get atomic access to a `&mut ", stringify!($int_type), "`.
+ 
+ ",
+ if_not_8_bit! {
+     $int_type,
+     concat!(
+         "**Note:** This function is only available on targets where `",
+         stringify!($int_type), "` has an alignment of ", $align, " bytes."
+     )
+ },
+ "
+ 
+ # Examples
+ 
+ ```
+ #![feature(atomic_from_mut)]
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let mut some_int = 123;
+ let a = ", stringify!($atomic_type), "::from_mut(&mut some_int);
+ a.store(100, Ordering::Relaxed);
+ assert_eq!(some_int, 100);
+ ```
+                 "),
+                 #[inline]
+                 #[$cfg_align]
+                 #[unstable(feature = "atomic_from_mut", issue = "76314")]
+                 pub fn from_mut(v: &mut $int_type) -> &Self {
+                     use crate::mem::align_of;
+                     let [] = [(); align_of::<Self>() - align_of::<$int_type>()];
+                     // SAFETY:
+                     //  - the mutable reference guarantees unique ownership.
+                     //  - the alignment of `$int_type` and `Self` is the
+                     //    same, as promised by $cfg_align and verified above.
+                     unsafe { &*(v as *mut $int_type as *mut Self) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Consumes the atomic and returns the contained value.
+ 
+ This is safe because passing `self` by value guarantees that no other threads are
+ concurrently accessing the atomic data.
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::", stringify!($atomic_type), ";
+ 
+ let some_var = ", stringify!($atomic_type), "::new(5);
+ assert_eq!(some_var.into_inner(), 5);
+ ```"),
+                 #[inline]
+                 #[$stable_access]
+                 #[rustc_const_unstable(feature = "const_cell_into_inner", issue = "78729")]
+                 pub const fn into_inner(self) -> $int_type {
+                     self.v.into_inner()
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Loads a value from the atomic integer.
+ 
+ `load` takes an [`Ordering`] argument which describes the memory ordering of this operation.
+ Possible values are [`SeqCst`], [`Acquire`] and [`Relaxed`].
+ 
+ # Panics
+ 
+ Panics if `order` is [`Release`] or [`AcqRel`].
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let some_var = ", stringify!($atomic_type), "::new(5);
+ 
+ assert_eq!(some_var.load(Ordering::Relaxed), 5);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 pub fn load(&self, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_load(self.v.get(), order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Stores a value into the atomic integer.
+ 
+ `store` takes an [`Ordering`] argument which describes the memory ordering of this operation.
+  Possible values are [`SeqCst`], [`Release`] and [`Relaxed`].
+ 
+ # Panics
+ 
+ Panics if `order` is [`Acquire`] or [`AcqRel`].
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let some_var = ", stringify!($atomic_type), "::new(5);
+ 
+ some_var.store(10, Ordering::Relaxed);
+ assert_eq!(some_var.load(Ordering::Relaxed), 10);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 pub fn store(&self, val: $int_type, order: Ordering) {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_store(self.v.get(), val, order); }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Stores a value into the atomic integer, returning the previous value.
+ 
+ `swap` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let some_var = ", stringify!($atomic_type), "::new(5);
+ 
+ assert_eq!(some_var.swap(10, Ordering::Relaxed), 5);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn swap(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_swap(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Stores a value into the atomic integer if the current value is the same as
+ the `current` value.
+ 
+ The return value is always the previous value. If it is equal to `current`, then the
+ value was updated.
+ 
+ `compare_and_swap` also takes an [`Ordering`] argument which describes the memory
+ ordering of this operation. Notice that even when using [`AcqRel`], the operation
+ might fail and hence just perform an `Acquire` load, but not have `Release` semantics.
+ Using [`Acquire`] makes the store part of this operation [`Relaxed`] if it
+ happens, and using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let some_var = ", stringify!($atomic_type), "::new(5);
+ 
+ assert_eq!(some_var.compare_and_swap(5, 10, Ordering::Relaxed), 5);
+ assert_eq!(some_var.load(Ordering::Relaxed), 10);
+ 
+ assert_eq!(some_var.compare_and_swap(6, 12, Ordering::Relaxed), 10);
+ assert_eq!(some_var.load(Ordering::Relaxed), 10);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn compare_and_swap(&self,
+                                         current: $int_type,
+                                         new: $int_type,
+                                         order: Ordering) -> $int_type {
+                     match self.compare_exchange(current,
+                                                 new,
+                                                 order,
+                                                 strongest_failure_ordering(order)) {
+                         Ok(x) => x,
+                         Err(x) => x,
+                     }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Stores a value into the atomic integer if the current value is the same as
+ the `current` value.
+ 
+ The return value is a result indicating whether the new value was written and
+ containing the previous value. On success this value is guaranteed to be equal to
+ `current`.
+ 
+ `compare_exchange` takes two [`Ordering`] arguments to describe the memory
+ ordering of this operation. The first describes the required ordering if the
+ operation succeeds while the second describes the required ordering when the
+ operation fails. Using [`Acquire`] as success ordering makes the store part
+ of this operation [`Relaxed`], and using [`Release`] makes the successful load
+ [`Relaxed`]. The failure ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+ and must be equivalent to or weaker than the success ordering.
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let some_var = ", stringify!($atomic_type), "::new(5);
+ 
+ assert_eq!(some_var.compare_exchange(5, 10,
+                                      Ordering::Acquire,
+                                      Ordering::Relaxed),
+            Ok(5));
+ assert_eq!(some_var.load(Ordering::Relaxed), 10);
+ 
+ assert_eq!(some_var.compare_exchange(6, 12,
+                                      Ordering::SeqCst,
+                                      Ordering::Acquire),
+            Err(10));
+ assert_eq!(some_var.load(Ordering::Relaxed), 10);
+ ```"),
+                 #[inline]
+                 #[$stable_cxchg]
+                 #[$cfg_cas]
+                 pub fn compare_exchange(&self,
+                                         current: $int_type,
+                                         new: $int_type,
+                                         success: Ordering,
+                                         failure: Ordering) -> Result<$int_type, $int_type> {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_compare_exchange(self.v.get(), current, new, success, failure) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Stores a value into the atomic integer if the current value is the same as
+ the `current` value.
+ 
+ Unlike [`", stringify!($atomic_type), "::compare_exchange`], this function is allowed to spuriously fail even
+ when the comparison succeeds, which can result in more efficient code on some
+ platforms. The return value is a result indicating whether the new value was
+ written and containing the previous value.
+ 
+ `compare_exchange_weak` takes two [`Ordering`] arguments to describe the memory
+ ordering of this operation. The first describes the required ordering if the
+ operation succeeds while the second describes the required ordering when the
+ operation fails. Using [`Acquire`] as success ordering makes the store part
+ of this operation [`Relaxed`], and using [`Release`] makes the successful load
+ [`Relaxed`]. The failure ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+ and must be equivalent to or weaker than the success ordering.
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let val = ", stringify!($atomic_type), "::new(4);
+ 
+ let mut old = val.load(Ordering::Relaxed);
+ loop {
+     let new = old * 2;
+     match val.compare_exchange_weak(old, new, Ordering::SeqCst, Ordering::Relaxed) {
+         Ok(_) => break,
+         Err(x) => old = x,
+     }
+ }
+ ```"),
+                 #[inline]
+                 #[$stable_cxchg]
+                 #[$cfg_cas]
+                 pub fn compare_exchange_weak(&self,
+                                              current: $int_type,
+                                              new: $int_type,
+                                              success: Ordering,
+                                              failure: Ordering) -> Result<$int_type, $int_type> {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe {
+                         atomic_compare_exchange_weak(self.v.get(), current, new, success, failure)
+                     }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Adds to the current value, returning the previous value.
+ 
+ This operation wraps around on overflow.
+ 
+ `fetch_add` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(0);
+ assert_eq!(foo.fetch_add(10, Ordering::SeqCst), 0);
+ assert_eq!(foo.load(Ordering::SeqCst), 10);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn fetch_add(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_add(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Subtracts from the current value, returning the previous value.
+ 
+ This operation wraps around on overflow.
+ 
+ `fetch_sub` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(20);
+ assert_eq!(foo.fetch_sub(10, Ordering::SeqCst), 20);
+ assert_eq!(foo.load(Ordering::SeqCst), 10);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn fetch_sub(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_sub(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Bitwise \"and\" with the current value.
+ 
+ Performs a bitwise \"and\" operation on the current value and the argument `val`, and
+ sets the new value to the result.
+ 
+ Returns the previous value.
+ 
+ `fetch_and` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(0b101101);
+ assert_eq!(foo.fetch_and(0b110011, Ordering::SeqCst), 0b101101);
+ assert_eq!(foo.load(Ordering::SeqCst), 0b100001);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn fetch_and(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_and(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Bitwise \"nand\" with the current value.
+ 
+ Performs a bitwise \"nand\" operation on the current value and the argument `val`, and
+ sets the new value to the result.
+ 
+ Returns the previous value.
+ 
+ `fetch_nand` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "
+ use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(0x13);
+ assert_eq!(foo.fetch_nand(0x31, Ordering::SeqCst), 0x13);
+ assert_eq!(foo.load(Ordering::SeqCst), !(0x13 & 0x31));
+ ```"),
+                 #[inline]
+                 #[$stable_nand]
+                 #[$cfg_cas]
+                 pub fn fetch_nand(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_nand(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Bitwise \"or\" with the current value.
+ 
+ Performs a bitwise \"or\" operation on the current value and the argument `val`, and
+ sets the new value to the result.
+ 
+ Returns the previous value.
+ 
+ `fetch_or` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(0b101101);
+ assert_eq!(foo.fetch_or(0b110011, Ordering::SeqCst), 0b101101);
+ assert_eq!(foo.load(Ordering::SeqCst), 0b111111);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn fetch_or(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_or(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Bitwise \"xor\" with the current value.
+ 
+ Performs a bitwise \"xor\" operation on the current value and the argument `val`, and
+ sets the new value to the result.
+ 
+ Returns the previous value.
+ 
+ `fetch_xor` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(0b101101);
+ assert_eq!(foo.fetch_xor(0b110011, Ordering::SeqCst), 0b101101);
+ assert_eq!(foo.load(Ordering::SeqCst), 0b011110);
+ ```"),
+                 #[inline]
+                 #[$stable]
+                 #[$cfg_cas]
+                 pub fn fetch_xor(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { atomic_xor(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Fetches the value, and applies a function to it that returns an optional
+ new value. Returns a `Result` of `Ok(previous_value)` if the function returned `Some(_)`, else
+ `Err(previous_value)`.
+ 
+ Note: This may call the function multiple times if the value has been changed from other threads in
+ the meantime, as long as the function returns `Some(_)`, but the function will have been applied
+ only once to the stored value.
+ 
+ `fetch_update` takes two [`Ordering`] arguments to describe the memory ordering of this operation.
+ The first describes the required ordering for when the operation finally succeeds while the second
+ describes the required ordering for loads. These correspond to the success and failure orderings of
+ [`", stringify!($atomic_type), "::compare_exchange`] respectively.
+ 
+ Using [`Acquire`] as success ordering makes the store part
+ of this operation [`Relaxed`], and using [`Release`] makes the final successful load
+ [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]
+ and must be equivalent to or weaker than the success ordering.
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```rust
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let x = ", stringify!($atomic_type), "::new(7);
+ assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(7));
+ assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(7));
+ assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(8));
+ assert_eq!(x.load(Ordering::SeqCst), 9);
+ ```"),
+                 #[inline]
+                 #[stable(feature = "no_more_cas", since = "1.45.0")]
+                 #[$cfg_cas]
+                 pub fn fetch_update<F>(&self,
+                                        set_order: Ordering,
+                                        fetch_order: Ordering,
+                                        mut f: F) -> Result<$int_type, $int_type>
+                 where F: FnMut($int_type) -> Option<$int_type> {
+                     let mut prev = self.load(fetch_order);
+                     while let Some(next) = f(prev) {
+                         match self.compare_exchange_weak(prev, next, set_order, fetch_order) {
+                             x @ Ok(_) => return x,
+                             Err(next_prev) => prev = next_prev
+                         }
+                     }
+                     Err(prev)
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Maximum with the current value.
+ 
+ Finds the maximum of the current value and the argument `val`, and
+ sets the new value to the result.
+ 
+ Returns the previous value.
+ 
+ `fetch_max` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(23);
+ assert_eq!(foo.fetch_max(42, Ordering::SeqCst), 23);
+ assert_eq!(foo.load(Ordering::SeqCst), 42);
+ ```
+ 
+ If you want to obtain the maximum value in one step, you can use the following:
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(23);
+ let bar = 42;
+ let max_foo = foo.fetch_max(bar, Ordering::SeqCst).max(bar);
+ assert!(max_foo == 42);
+ ```"),
+                 #[inline]
+                 #[stable(feature = "atomic_min_max", since = "1.45.0")]
+                 #[$cfg_cas]
+                 pub fn fetch_max(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { $max_fn(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Minimum with the current value.
+ 
+ Finds the minimum of the current value and the argument `val`, and
+ sets the new value to the result.
+ 
+ Returns the previous value.
+ 
+ `fetch_min` takes an [`Ordering`] argument which describes the memory ordering
+ of this operation. All ordering modes are possible. Note that using
+ [`Acquire`] makes the store part of this operation [`Relaxed`], and
+ using [`Release`] makes the load part [`Relaxed`].
+ 
+ **Note**: This method is only available on platforms that support atomic
+ operations on [`", $s_int_type, "`](", $int_ref, ").
+ 
+ # Examples
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(23);
+ assert_eq!(foo.fetch_min(42, Ordering::Relaxed), 23);
+ assert_eq!(foo.load(Ordering::Relaxed), 23);
+ assert_eq!(foo.fetch_min(22, Ordering::Relaxed), 23);
+ assert_eq!(foo.load(Ordering::Relaxed), 22);
+ ```
+ 
+ If you want to obtain the minimum value in one step, you can use the following:
+ 
+ ```
+ ", $extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};
+ 
+ let foo = ", stringify!($atomic_type), "::new(23);
+ let bar = 12;
+ let min_foo = foo.fetch_min(bar, Ordering::SeqCst).min(bar);
+ assert_eq!(min_foo, 12);
+ ```"),
+                 #[inline]
+                 #[stable(feature = "atomic_min_max", since = "1.45.0")]
+                 #[$cfg_cas]
+                 pub fn fetch_min(&self, val: $int_type, order: Ordering) -> $int_type {
+                     // SAFETY: data races are prevented by atomic intrinsics.
+                     unsafe { $min_fn(self.v.get(), val, order) }
+                 }
+             }
+ 
+             doc_comment! {
+                 concat!("Returns a mutable pointer to the underlying integer.
+ 
+ Doing non-atomic reads and writes on the resulting integer can be a data race.
+ This method is mostly useful for FFI, where the function signature may use
+ `*mut ", stringify!($int_type), "` instead of `&", stringify!($atomic_type), "`.
+ 
+ Returning an `*mut` pointer from a shared reference to this atomic is safe because the
+ atomic types work with interior mutability. All modifications of an atomic change the value
+ through a shared reference, and can do so safely as long as they use atomic operations. Any
+ use of the returned raw pointer requires an `unsafe` block and still has to uphold the same
+ restriction: operations on it must be atomic.
+ 
+ # Examples
+ 
+ ```ignore (extern-declaration)
+ # fn main() {
+ ", $extra_feature, "use std::sync::atomic::", stringify!($atomic_type), ";
+ 
+ extern {
+     fn my_atomic_op(arg: *mut ", stringify!($int_type), ");
+ }
+ 
+ let mut atomic = ", stringify!($atomic_type), "::new(1);
+ ",
+ // SAFETY: Safe as long as `my_atomic_op` is atomic.
+ "unsafe {
+     my_atomic_op(atomic.as_mut_ptr());
+ }
+ # }
+ ```"),
+                 #[inline]
+                 #[unstable(feature = "atomic_mut_ptr",
+                        reason = "recently added",
+                        issue = "66893")]
+                 pub fn as_mut_ptr(&self) -> *mut $int_type {
+                     self.v.get()
+                 }
+             }
+         }
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "8")]
+ atomic_int! {
+     cfg(target_has_atomic = "8"),
+     cfg(target_has_atomic_equal_alignment = "8"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "i8", "../../../std/primitive.i8.html",
+     "",
+     atomic_min, atomic_max,
+     1,
+     "AtomicI8::new(0)",
+     i8 AtomicI8 ATOMIC_I8_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "8")]
+ atomic_int! {
+     cfg(target_has_atomic = "8"),
+     cfg(target_has_atomic_equal_alignment = "8"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "u8", "../../../std/primitive.u8.html",
+     "",
+     atomic_umin, atomic_umax,
+     1,
+     "AtomicU8::new(0)",
+     u8 AtomicU8 ATOMIC_U8_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "16")]
+ atomic_int! {
+     cfg(target_has_atomic = "16"),
+     cfg(target_has_atomic_equal_alignment = "16"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "i16", "../../../std/primitive.i16.html",
+     "",
+     atomic_min, atomic_max,
+     2,
+     "AtomicI16::new(0)",
+     i16 AtomicI16 ATOMIC_I16_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "16")]
+ atomic_int! {
+     cfg(target_has_atomic = "16"),
+     cfg(target_has_atomic_equal_alignment = "16"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "u16", "../../../std/primitive.u16.html",
+     "",
+     atomic_umin, atomic_umax,
+     2,
+     "AtomicU16::new(0)",
+     u16 AtomicU16 ATOMIC_U16_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "32")]
+ atomic_int! {
+     cfg(target_has_atomic = "32"),
+     cfg(target_has_atomic_equal_alignment = "32"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "i32", "../../../std/primitive.i32.html",
+     "",
+     atomic_min, atomic_max,
+     4,
+     "AtomicI32::new(0)",
+     i32 AtomicI32 ATOMIC_I32_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "32")]
+ atomic_int! {
+     cfg(target_has_atomic = "32"),
+     cfg(target_has_atomic_equal_alignment = "32"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "u32", "../../../std/primitive.u32.html",
+     "",
+     atomic_umin, atomic_umax,
+     4,
+     "AtomicU32::new(0)",
+     u32 AtomicU32 ATOMIC_U32_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "64")]
+ atomic_int! {
+     cfg(target_has_atomic = "64"),
+     cfg(target_has_atomic_equal_alignment = "64"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "i64", "../../../std/primitive.i64.html",
+     "",
+     atomic_min, atomic_max,
+     8,
+     "AtomicI64::new(0)",
+     i64 AtomicI64 ATOMIC_I64_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "64")]
+ atomic_int! {
+     cfg(target_has_atomic = "64"),
+     cfg(target_has_atomic_equal_alignment = "64"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     stable(feature = "integer_atomics_stable", since = "1.34.0"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "u64", "../../../std/primitive.u64.html",
+     "",
+     atomic_umin, atomic_umax,
+     8,
+     "AtomicU64::new(0)",
+     u64 AtomicU64 ATOMIC_U64_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "128")]
+ atomic_int! {
+     cfg(target_has_atomic = "128"),
+     cfg(target_has_atomic_equal_alignment = "128"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "i128", "../../../std/primitive.i128.html",
+     "#![feature(integer_atomics)]\n\n",
+     atomic_min, atomic_max,
+     16,
+     "AtomicI128::new(0)",
+     i128 AtomicI128 ATOMIC_I128_INIT
+ }
+ #[cfg(target_has_atomic_load_store = "128")]
+ atomic_int! {
+     cfg(target_has_atomic = "128"),
+     cfg(target_has_atomic_equal_alignment = "128"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+     unstable(feature = "integer_atomics", issue = "32976"),
+     "u128", "../../../std/primitive.u128.html",
+     "#![feature(integer_atomics)]\n\n",
+     atomic_umin, atomic_umax,
+     16,
+     "AtomicU128::new(0)",
+     u128 AtomicU128 ATOMIC_U128_INIT
+ }
+ 
+ macro_rules! atomic_int_ptr_sized {
+     ( $($target_pointer_width:literal $align:literal)* ) => { $(
+         #[cfg(target_has_atomic_load_store = "ptr")]
+         #[cfg(target_pointer_width = $target_pointer_width)]
+         atomic_int! {
+             cfg(target_has_atomic = "ptr"),
+             cfg(target_has_atomic_equal_alignment = "ptr"),
+             stable(feature = "rust1", since = "1.0.0"),
+             stable(feature = "extended_compare_and_swap", since = "1.10.0"),
+             stable(feature = "atomic_debug", since = "1.3.0"),
+             stable(feature = "atomic_access", since = "1.15.0"),
+             stable(feature = "atomic_from", since = "1.23.0"),
+             stable(feature = "atomic_nand", since = "1.27.0"),
+             rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+             stable(feature = "rust1", since = "1.0.0"),
+             "isize", "../../../std/primitive.isize.html",
+             "",
+             atomic_min, atomic_max,
+             $align,
+             "AtomicIsize::new(0)",
+             isize AtomicIsize ATOMIC_ISIZE_INIT
+         }
+         #[cfg(target_has_atomic_load_store = "ptr")]
+         #[cfg(target_pointer_width = $target_pointer_width)]
+         atomic_int! {
+             cfg(target_has_atomic = "ptr"),
+             cfg(target_has_atomic_equal_alignment = "ptr"),
+             stable(feature = "rust1", since = "1.0.0"),
+             stable(feature = "extended_compare_and_swap", since = "1.10.0"),
+             stable(feature = "atomic_debug", since = "1.3.0"),
+             stable(feature = "atomic_access", since = "1.15.0"),
+             stable(feature = "atomic_from", since = "1.23.0"),
+             stable(feature = "atomic_nand", since = "1.27.0"),
+             rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"),
+             stable(feature = "rust1", since = "1.0.0"),
+             "usize", "../../../std/primitive.usize.html",
+             "",
+             atomic_umin, atomic_umax,
+             $align,
+             "AtomicUsize::new(0)",
+             usize AtomicUsize ATOMIC_USIZE_INIT
+         }
+     )* };
+ }
+ 
+ atomic_int_ptr_sized! {
+     "16" 2
+     "32" 4
+     "64" 8
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ fn strongest_failure_ordering(order: Ordering) -> Ordering {
+     match order {
+         Release => Relaxed,
+         Relaxed => Relaxed,
+         SeqCst => SeqCst,
+         Acquire => Acquire,
+         AcqRel => Acquire,
+     }
+ }
+ 
+ #[inline]
+ unsafe fn atomic_store<T: Copy>(dst: *mut T, val: T, order: Ordering) {
+     // SAFETY: the caller must uphold the safety contract for `atomic_store`.
+     unsafe {
+         match order {
+             Release => intrinsics::atomic_store_rel(dst, val),
+             Relaxed => intrinsics::atomic_store_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_store(dst, val),
+             Acquire => panic!("there is no such thing as an acquire store"),
+             AcqRel => panic!("there is no such thing as an acquire/release store"),
+         }
+     }
+ }
+ 
+ #[inline]
+ unsafe fn atomic_load<T: Copy>(dst: *const T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_load`.
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_load_acq(dst),
+             Relaxed => intrinsics::atomic_load_relaxed(dst),
+             SeqCst => intrinsics::atomic_load(dst),
+             Release => panic!("there is no such thing as a release load"),
+             AcqRel => panic!("there is no such thing as an acquire/release load"),
+         }
+     }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_swap<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_swap`.
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_xchg_acq(dst, val),
+             Release => intrinsics::atomic_xchg_rel(dst, val),
+             AcqRel => intrinsics::atomic_xchg_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_xchg_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_xchg(dst, val),
+         }
+     }
+ }
+ 
+ /// Returns the previous value (like __sync_fetch_and_add).
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_add<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_add`.
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_xadd_acq(dst, val),
+             Release => intrinsics::atomic_xadd_rel(dst, val),
+             AcqRel => intrinsics::atomic_xadd_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_xadd_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_xadd(dst, val),
+         }
+     }
+ }
+ 
+ /// Returns the previous value (like __sync_fetch_and_sub).
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_sub<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_sub`.
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_xsub_acq(dst, val),
+             Release => intrinsics::atomic_xsub_rel(dst, val),
+             AcqRel => intrinsics::atomic_xsub_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_xsub_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_xsub(dst, val),
+         }
+     }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_compare_exchange<T: Copy>(
+     dst: *mut T,
+     old: T,
+     new: T,
+     success: Ordering,
+     failure: Ordering,
+ ) -> Result<T, T> {
+     // SAFETY: the caller must uphold the safety contract for `atomic_compare_exchange`.
+     let (val, ok) = unsafe {
+         match (success, failure) {
+             (Acquire, Acquire) => intrinsics::atomic_cxchg_acq(dst, old, new),
+             (Release, Relaxed) => intrinsics::atomic_cxchg_rel(dst, old, new),
+             (AcqRel, Acquire) => intrinsics::atomic_cxchg_acqrel(dst, old, new),
+             (Relaxed, Relaxed) => intrinsics::atomic_cxchg_relaxed(dst, old, new),
+             (SeqCst, SeqCst) => intrinsics::atomic_cxchg(dst, old, new),
+             (Acquire, Relaxed) => intrinsics::atomic_cxchg_acq_failrelaxed(dst, old, new),
+             (AcqRel, Relaxed) => intrinsics::atomic_cxchg_acqrel_failrelaxed(dst, old, new),
+             (SeqCst, Relaxed) => intrinsics::atomic_cxchg_failrelaxed(dst, old, new),
+             (SeqCst, Acquire) => intrinsics::atomic_cxchg_failacq(dst, old, new),
+             (_, AcqRel) => panic!("there is no such thing as an acquire/release failure ordering"),
+             (_, Release) => panic!("there is no such thing as a release failure ordering"),
+             _ => panic!("a failure ordering can't be stronger than a success ordering"),
+         }
+     };
+     if ok { Ok(val) } else { Err(val) }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_compare_exchange_weak<T: Copy>(
+     dst: *mut T,
+     old: T,
+     new: T,
+     success: Ordering,
+     failure: Ordering,
+ ) -> Result<T, T> {
+     // SAFETY: the caller must uphold the safety contract for `atomic_compare_exchange_weak`.
+     let (val, ok) = unsafe {
+         match (success, failure) {
+             (Acquire, Acquire) => intrinsics::atomic_cxchgweak_acq(dst, old, new),
+             (Release, Relaxed) => intrinsics::atomic_cxchgweak_rel(dst, old, new),
+             (AcqRel, Acquire) => intrinsics::atomic_cxchgweak_acqrel(dst, old, new),
+             (Relaxed, Relaxed) => intrinsics::atomic_cxchgweak_relaxed(dst, old, new),
+             (SeqCst, SeqCst) => intrinsics::atomic_cxchgweak(dst, old, new),
+             (Acquire, Relaxed) => intrinsics::atomic_cxchgweak_acq_failrelaxed(dst, old, new),
+             (AcqRel, Relaxed) => intrinsics::atomic_cxchgweak_acqrel_failrelaxed(dst, old, new),
+             (SeqCst, Relaxed) => intrinsics::atomic_cxchgweak_failrelaxed(dst, old, new),
+             (SeqCst, Acquire) => intrinsics::atomic_cxchgweak_failacq(dst, old, new),
+             (_, AcqRel) => panic!("there is no such thing as an acquire/release failure ordering"),
+             (_, Release) => panic!("there is no such thing as a release failure ordering"),
+             _ => panic!("a failure ordering can't be stronger than a success ordering"),
+         }
+     };
+     if ok { Ok(val) } else { Err(val) }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_and<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_and`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_and_acq(dst, val),
+             Release => intrinsics::atomic_and_rel(dst, val),
+             AcqRel => intrinsics::atomic_and_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_and_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_and(dst, val),
+         }
+     }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_nand<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_nand`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_nand_acq(dst, val),
+             Release => intrinsics::atomic_nand_rel(dst, val),
+             AcqRel => intrinsics::atomic_nand_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_nand_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_nand(dst, val),
+         }
+     }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_or<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_or`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_or_acq(dst, val),
+             Release => intrinsics::atomic_or_rel(dst, val),
+             AcqRel => intrinsics::atomic_or_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_or_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_or(dst, val),
+         }
+     }
+ }
+ 
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_xor<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_xor`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_xor_acq(dst, val),
+             Release => intrinsics::atomic_xor_rel(dst, val),
+             AcqRel => intrinsics::atomic_xor_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_xor_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_xor(dst, val),
+         }
+     }
+ }
+ 
+ /// returns the max value (signed comparison)
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_max<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_max`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_max_acq(dst, val),
+             Release => intrinsics::atomic_max_rel(dst, val),
+             AcqRel => intrinsics::atomic_max_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_max_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_max(dst, val),
+         }
+     }
+ }
+ 
+ /// returns the min value (signed comparison)
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_min<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_min`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_min_acq(dst, val),
+             Release => intrinsics::atomic_min_rel(dst, val),
+             AcqRel => intrinsics::atomic_min_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_min_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_min(dst, val),
+         }
+     }
+ }
+ 
+ /// returns the max value (unsigned comparison)
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_umax<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_umax`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_umax_acq(dst, val),
+             Release => intrinsics::atomic_umax_rel(dst, val),
+             AcqRel => intrinsics::atomic_umax_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_umax_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_umax(dst, val),
+         }
+     }
+ }
+ 
+ /// returns the min value (unsigned comparison)
+ #[inline]
+ #[cfg(target_has_atomic = "8")]
+ unsafe fn atomic_umin<T: Copy>(dst: *mut T, val: T, order: Ordering) -> T {
+     // SAFETY: the caller must uphold the safety contract for `atomic_umin`
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_umin_acq(dst, val),
+             Release => intrinsics::atomic_umin_rel(dst, val),
+             AcqRel => intrinsics::atomic_umin_acqrel(dst, val),
+             Relaxed => intrinsics::atomic_umin_relaxed(dst, val),
+             SeqCst => intrinsics::atomic_umin(dst, val),
+         }
+     }
+ }
+ 
+ /// An atomic fence.
+ ///
+ /// Depending on the specified order, a fence prevents the compiler and CPU from
+ /// reordering certain types of memory operations around it.
+ /// That creates synchronizes-with relationships between it and atomic operations
+ /// or fences in other threads.
+ ///
+ /// A fence 'A' which has (at least) [`Release`] ordering semantics, synchronizes
+ /// with a fence 'B' with (at least) [`Acquire`] semantics, if and only if there
+ /// exist operations X and Y, both operating on some atomic object 'M' such
+ /// that A is sequenced before X, Y is synchronized before B and Y observes
+ /// the change to M. This provides a happens-before dependence between A and B.
+ ///
+ /// ```text
+ ///     Thread 1                                          Thread 2
+ ///
+ /// fence(Release);      A --------------
+ /// x.store(3, Relaxed); X ---------    |
+ ///                                |    |
+ ///                                |    |
+ ///                                -------------> Y  if x.load(Relaxed) == 3 {
+ ///                                     |-------> B      fence(Acquire);
+ ///                                                      ...
+ ///                                                  }
+ /// ```
+ ///
+ /// Atomic operations with [`Release`] or [`Acquire`] semantics can also synchronize
+ /// with a fence.
+ ///
+ /// A fence which has [`SeqCst`] ordering, in addition to having both [`Acquire`]
+ /// and [`Release`] semantics, participates in the global program order of the
+ /// other [`SeqCst`] operations and/or fences.
+ ///
+ /// Accepts [`Acquire`], [`Release`], [`AcqRel`] and [`SeqCst`] orderings.
+ ///
+ /// # Panics
+ ///
+ /// Panics if `order` is [`Relaxed`].
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::sync::atomic::AtomicBool;
+ /// use std::sync::atomic::fence;
+ /// use std::sync::atomic::Ordering;
+ ///
+ /// // A mutual exclusion primitive based on spinlock.
+ /// pub struct Mutex {
+ ///     flag: AtomicBool,
+ /// }
+ ///
+ /// impl Mutex {
+ ///     pub fn new() -> Mutex {
+ ///         Mutex {
+ ///             flag: AtomicBool::new(false),
+ ///         }
+ ///     }
+ ///
+ ///     pub fn lock(&self) {
+ ///         // Wait until the old value is `false`.
+ ///         while self.flag.compare_and_swap(false, true, Ordering::Relaxed) != false {}
+ ///         // This fence synchronizes-with store in `unlock`.
+ ///         fence(Ordering::Acquire);
+ ///     }
+ ///
+ ///     pub fn unlock(&self) {
+ ///         self.flag.store(false, Ordering::Release);
+ ///     }
+ /// }
+ /// ```
+ #[inline]
+ #[stable(feature = "rust1", since = "1.0.0")]
+ pub fn fence(order: Ordering) {
+     // SAFETY: using an atomic fence is safe.
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_fence_acq(),
+             Release => intrinsics::atomic_fence_rel(),
+             AcqRel => intrinsics::atomic_fence_acqrel(),
+             SeqCst => intrinsics::atomic_fence(),
+             Relaxed => panic!("there is no such thing as a relaxed fence"),
+         }
+     }
+ }
+ 
+ /// A compiler memory fence.
+ ///
+ /// `compiler_fence` does not emit any machine code, but restricts the kinds
+ /// of memory re-ordering the compiler is allowed to do. Specifically, depending on
+ /// the given [`Ordering`] semantics, the compiler may be disallowed from moving reads
+ /// or writes from before or after the call to the other side of the call to
+ /// `compiler_fence`. Note that it does **not** prevent the *hardware*
+ /// from doing such re-ordering. This is not a problem in a single-threaded,
+ /// execution context, but when other threads may modify memory at the same
+ /// time, stronger synchronization primitives such as [`fence`] are required.
+ ///
+ /// The re-ordering prevented by the different ordering semantics are:
+ ///
+ ///  - with [`SeqCst`], no re-ordering of reads and writes across this point is allowed.
+ ///  - with [`Release`], preceding reads and writes cannot be moved past subsequent writes.
+ ///  - with [`Acquire`], subsequent reads and writes cannot be moved ahead of preceding reads.
+ ///  - with [`AcqRel`], both of the above rules are enforced.
+ ///
+ /// `compiler_fence` is generally only useful for preventing a thread from
+ /// racing *with itself*. That is, if a given thread is executing one piece
+ /// of code, and is then interrupted, and starts executing code elsewhere
+ /// (while still in the same thread, and conceptually still on the same
+ /// core). In traditional programs, this can only occur when a signal
+ /// handler is registered. In more low-level code, such situations can also
+ /// arise when handling interrupts, when implementing green threads with
+ /// pre-emption, etc. Curious readers are encouraged to read the Linux kernel's
+ /// discussion of [memory barriers].
+ ///
+ /// # Panics
+ ///
+ /// Panics if `order` is [`Relaxed`].
+ ///
+ /// # Examples
+ ///
+ /// Without `compiler_fence`, the `assert_eq!` in following code
+ /// is *not* guaranteed to succeed, despite everything happening in a single thread.
+ /// To see why, remember that the compiler is free to swap the stores to
+ /// `IMPORTANT_VARIABLE` and `IS_READ` since they are both
+ /// `Ordering::Relaxed`. If it does, and the signal handler is invoked right
+ /// after `IS_READY` is updated, then the signal handler will see
+ /// `IS_READY=1`, but `IMPORTANT_VARIABLE=0`.
+ /// Using a `compiler_fence` remedies this situation.
+ ///
+ /// ```
+ /// use std::sync::atomic::{AtomicBool, AtomicUsize};
+ /// use std::sync::atomic::Ordering;
+ /// use std::sync::atomic::compiler_fence;
+ ///
+ /// static IMPORTANT_VARIABLE: AtomicUsize = AtomicUsize::new(0);
+ /// static IS_READY: AtomicBool = AtomicBool::new(false);
+ ///
+ /// fn main() {
+ ///     IMPORTANT_VARIABLE.store(42, Ordering::Relaxed);
+ ///     // prevent earlier writes from being moved beyond this point
+ ///     compiler_fence(Ordering::Release);
+ ///     IS_READY.store(true, Ordering::Relaxed);
+ /// }
+ ///
+ /// fn signal_handler() {
+ ///     if IS_READY.load(Ordering::Relaxed) {
+ ///         assert_eq!(IMPORTANT_VARIABLE.load(Ordering::Relaxed), 42);
+ ///     }
+ /// }
+ /// ```
+ ///
+ /// [memory barriers]: https://www.kernel.org/doc/Documentation/memory-barriers.txt
+ #[inline]
+ #[stable(feature = "compiler_fences", since = "1.21.0")]
+ pub fn compiler_fence(order: Ordering) {
+     // SAFETY: using an atomic fence is safe.
+     unsafe {
+         match order {
+             Acquire => intrinsics::atomic_singlethreadfence_acq(),
+             Release => intrinsics::atomic_singlethreadfence_rel(),
+             AcqRel => intrinsics::atomic_singlethreadfence_acqrel(),
+             SeqCst => intrinsics::atomic_singlethreadfence(),
+             Relaxed => panic!("there is no such thing as a relaxed compiler fence"),
+         }
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "8")]
+ #[stable(feature = "atomic_debug", since = "1.3.0")]
+ impl fmt::Debug for AtomicBool {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Debug::fmt(&self.load(Ordering::SeqCst), f)
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "atomic_debug", since = "1.3.0")]
+ impl<T> fmt::Debug for AtomicPtr<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Debug::fmt(&self.load(Ordering::SeqCst), f)
+     }
+ }
+ 
+ #[cfg(target_has_atomic_load_store = "ptr")]
+ #[stable(feature = "atomic_pointer", since = "1.24.0")]
+ impl<T> fmt::Pointer for AtomicPtr<T> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         fmt::Pointer::fmt(&self.load(Ordering::SeqCst), f)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/sync/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/sync/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/sync/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/sync/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,5 ----
+ //! Synchronization primitives
+ 
+ #![stable(feature = "rust1", since = "1.0.0")]
+ 
+ pub mod atomic;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/task/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/task/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/task/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/task/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,15 ----
+ #![stable(feature = "futures_api", since = "1.36.0")]
+ 
+ //! Types and Traits for working with asynchronous tasks.
+ 
+ mod poll;
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub use self::poll::Poll;
+ 
+ mod wake;
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub use self::wake::{Context, RawWaker, RawWakerVTable, Waker};
+ 
+ mod ready;
+ #[unstable(feature = "ready_macro", issue = "70922")]
+ pub use ready::ready;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/task/poll.rs gcc-16-20251102/libgrust/rustc-lib/core/src/task/poll.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/task/poll.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/task/poll.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,179 ----
+ #![stable(feature = "futures_api", since = "1.36.0")]
+ 
+ use crate::ops::Try;
+ use crate::result::Result;
+ 
+ /// Indicates whether a value is available or if the current task has been
+ /// scheduled to receive a wakeup instead.
+ #[must_use = "this `Poll` may be a `Pending` variant, which should be handled"]
+ #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd, Hash)]
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub enum Poll<T> {
+     /// Represents that a value is immediately ready.
+     #[lang = "Ready"]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     Ready(#[stable(feature = "futures_api", since = "1.36.0")] T),
+ 
+     /// Represents that a value is not ready yet.
+     ///
+     /// When a function returns `Pending`, the function *must* also
+     /// ensure that the current task is scheduled to be awoken when
+     /// progress can be made.
+     #[lang = "Pending"]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     Pending,
+ }
+ 
+ impl<T> Poll<T> {
+     /// Changes the ready value of this `Poll` with the closure provided.
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub fn map<U, F>(self, f: F) -> Poll<U>
+     where
+         F: FnOnce(T) -> U,
+     {
+         match self {
+             Poll::Ready(t) => Poll::Ready(f(t)),
+             Poll::Pending => Poll::Pending,
+         }
+     }
+ 
+     /// Returns `true` if this is `Poll::Ready`
+     #[inline]
+     #[rustc_const_stable(feature = "const_poll", since = "1.49.0")]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub const fn is_ready(&self) -> bool {
+         matches!(*self, Poll::Ready(_))
+     }
+ 
+     /// Returns `true` if this is `Poll::Pending`
+     #[inline]
+     #[rustc_const_stable(feature = "const_poll", since = "1.49.0")]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub const fn is_pending(&self) -> bool {
+         !self.is_ready()
+     }
+ }
+ 
+ impl<T, E> Poll<Result<T, E>> {
+     /// Changes the success value of this `Poll` with the closure provided.
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub fn map_ok<U, F>(self, f: F) -> Poll<Result<U, E>>
+     where
+         F: FnOnce(T) -> U,
+     {
+         match self {
+             Poll::Ready(Ok(t)) => Poll::Ready(Ok(f(t))),
+             Poll::Ready(Err(e)) => Poll::Ready(Err(e)),
+             Poll::Pending => Poll::Pending,
+         }
+     }
+ 
+     /// Changes the error value of this `Poll` with the closure provided.
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub fn map_err<U, F>(self, f: F) -> Poll<Result<T, U>>
+     where
+         F: FnOnce(E) -> U,
+     {
+         match self {
+             Poll::Ready(Ok(t)) => Poll::Ready(Ok(t)),
+             Poll::Ready(Err(e)) => Poll::Ready(Err(f(e))),
+             Poll::Pending => Poll::Pending,
+         }
+     }
+ }
+ 
+ impl<T, E> Poll<Option<Result<T, E>>> {
+     /// Changes the success value of this `Poll` with the closure provided.
+     #[unstable(feature = "poll_map", issue = "63514")]
+     pub fn map_ok<U, F>(self, f: F) -> Poll<Option<Result<U, E>>>
+     where
+         F: FnOnce(T) -> U,
+     {
+         match self {
+             Poll::Ready(Some(Ok(t))) => Poll::Ready(Some(Ok(f(t)))),
+             Poll::Ready(Some(Err(e))) => Poll::Ready(Some(Err(e))),
+             Poll::Ready(None) => Poll::Ready(None),
+             Poll::Pending => Poll::Pending,
+         }
+     }
+ 
+     /// Changes the error value of this `Poll` with the closure provided.
+     #[unstable(feature = "poll_map", issue = "63514")]
+     pub fn map_err<U, F>(self, f: F) -> Poll<Option<Result<T, U>>>
+     where
+         F: FnOnce(E) -> U,
+     {
+         match self {
+             Poll::Ready(Some(Ok(t))) => Poll::Ready(Some(Ok(t))),
+             Poll::Ready(Some(Err(e))) => Poll::Ready(Some(Err(f(e)))),
+             Poll::Ready(None) => Poll::Ready(None),
+             Poll::Pending => Poll::Pending,
+         }
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl<T> From<T> for Poll<T> {
+     /// Convert to a `Ready` variant.
+     ///
+     /// # Example
+     ///
+     /// ```
+     /// # use core::task::Poll;
+     /// assert_eq!(Poll::from(true), Poll::Ready(true));
+     /// ```
+     fn from(t: T) -> Poll<T> {
+         Poll::Ready(t)
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl<T, E> Try for Poll<Result<T, E>> {
+     type Ok = Poll<T>;
+     type Error = E;
+ 
+     #[inline]
+     fn into_result(self) -> Result<Self::Ok, Self::Error> {
+         match self {
+             Poll::Ready(Ok(x)) => Ok(Poll::Ready(x)),
+             Poll::Ready(Err(e)) => Err(e),
+             Poll::Pending => Ok(Poll::Pending),
+         }
+     }
+ 
+     #[inline]
+     fn from_error(e: Self::Error) -> Self {
+         Poll::Ready(Err(e))
+     }
+ 
+     #[inline]
+     fn from_ok(x: Self::Ok) -> Self {
+         x.map(Ok)
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl<T, E> Try for Poll<Option<Result<T, E>>> {
+     type Ok = Poll<Option<T>>;
+     type Error = E;
+ 
+     #[inline]
+     fn into_result(self) -> Result<Self::Ok, Self::Error> {
+         match self {
+             Poll::Ready(Some(Ok(x))) => Ok(Poll::Ready(Some(x))),
+             Poll::Ready(Some(Err(e))) => Err(e),
+             Poll::Ready(None) => Ok(Poll::Ready(None)),
+             Poll::Pending => Ok(Poll::Pending),
+         }
+     }
+ 
+     #[inline]
+     fn from_error(e: Self::Error) -> Self {
+         Poll::Ready(Some(Err(e)))
+     }
+ 
+     #[inline]
+     fn from_ok(x: Self::Ok) -> Self {
+         x.map(|x| x.map(Ok))
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/task/ready.rs gcc-16-20251102/libgrust/rustc-lib/core/src/task/ready.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/task/ready.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/task/ready.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,58 ----
+ /// Extracts the successful type of a `Poll<T>`.
+ ///
+ /// This macro bakes in propagation of `Pending` signals by returning early.
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #![feature(ready_macro)]
+ ///
+ /// use core::task::{ready, Context, Poll};
+ /// use core::future::{self, Future};
+ /// use core::pin::Pin;
+ ///
+ /// pub fn do_poll(cx: &mut Context<'_>) -> Poll<()> {
+ ///     let mut fut = future::ready(42);
+ ///     let fut = Pin::new(&mut fut);
+ ///
+ ///     let num = ready!(fut.poll(cx));
+ ///     # drop(num);
+ ///     // ... use num
+ ///
+ ///     Poll::Ready(())
+ /// }
+ /// ```
+ ///
+ /// The `ready!` call expands to:
+ ///
+ /// ```
+ /// # #![feature(ready_macro)]
+ /// #
+ /// # use core::task::{Context, Poll};
+ /// # use core::future::{self, Future};
+ /// # use core::pin::Pin;
+ /// #
+ /// # pub fn do_poll(cx: &mut Context<'_>) -> Poll<()> {
+ ///     # let mut fut = future::ready(42);
+ ///     # let fut = Pin::new(&mut fut);
+ ///     #
+ /// let num = match fut.poll(cx) {
+ ///     Poll::Ready(t) => t,
+ ///     Poll::Pending => return Poll::Pending,
+ /// };
+ ///     # drop(num);
+ ///     # // ... use num
+ ///     #
+ ///     # Poll::Ready(())
+ /// # }
+ /// ```
+ #[unstable(feature = "ready_macro", issue = "70922")]
+ #[rustc_macro_transparency = "semitransparent"]
+ pub macro ready($e:expr) {
+     match $e {
+         $crate::task::Poll::Ready(t) => t,
+         $crate::task::Poll::Pending => {
+             return $crate::task::Poll::Pending;
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/task/wake.rs gcc-16-20251102/libgrust/rustc-lib/core/src/task/wake.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/task/wake.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/task/wake.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,294 ----
+ #![stable(feature = "futures_api", since = "1.36.0")]
+ 
+ use crate::fmt;
+ use crate::marker::{PhantomData, Unpin};
+ 
+ /// A `RawWaker` allows the implementor of a task executor to create a [`Waker`]
+ /// which provides customized wakeup behavior.
+ ///
+ /// [vtable]: https://en.wikipedia.org/wiki/Virtual_method_table
+ ///
+ /// It consists of a data pointer and a [virtual function pointer table (vtable)][vtable]
+ /// that customizes the behavior of the `RawWaker`.
+ #[derive(PartialEq, Debug)]
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub struct RawWaker {
+     /// A data pointer, which can be used to store arbitrary data as required
+     /// by the executor. This could be e.g. a type-erased pointer to an `Arc`
+     /// that is associated with the task.
+     /// The value of this field gets passed to all functions that are part of
+     /// the vtable as the first parameter.
+     data: *const (),
+     /// Virtual function pointer table that customizes the behavior of this waker.
+     vtable: &'static RawWakerVTable,
+ }
+ 
+ impl RawWaker {
+     /// Creates a new `RawWaker` from the provided `data` pointer and `vtable`.
+     ///
+     /// The `data` pointer can be used to store arbitrary data as required
+     /// by the executor. This could be e.g. a type-erased pointer to an `Arc`
+     /// that is associated with the task.
+     /// The value of this pointer will get passed to all functions that are part
+     /// of the `vtable` as the first parameter.
+     ///
+     /// The `vtable` customizes the behavior of a `Waker` which gets created
+     /// from a `RawWaker`. For each operation on the `Waker`, the associated
+     /// function in the `vtable` of the underlying `RawWaker` will be called.
+     #[inline]
+     #[rustc_promotable]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     #[rustc_const_stable(feature = "futures_api", since = "1.36.0")]
+     pub const fn new(data: *const (), vtable: &'static RawWakerVTable) -> RawWaker {
+         RawWaker { data, vtable }
+     }
+ }
+ 
+ /// A virtual function pointer table (vtable) that specifies the behavior
+ /// of a [`RawWaker`].
+ ///
+ /// The pointer passed to all functions inside the vtable is the `data` pointer
+ /// from the enclosing [`RawWaker`] object.
+ ///
+ /// The functions inside this struct are only intended to be called on the `data`
+ /// pointer of a properly constructed [`RawWaker`] object from inside the
+ /// [`RawWaker`] implementation. Calling one of the contained functions using
+ /// any other `data` pointer will cause undefined behavior.
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ #[derive(PartialEq, Copy, Clone, Debug)]
+ pub struct RawWakerVTable {
+     /// This function will be called when the [`RawWaker`] gets cloned, e.g. when
+     /// the [`Waker`] in which the [`RawWaker`] is stored gets cloned.
+     ///
+     /// The implementation of this function must retain all resources that are
+     /// required for this additional instance of a [`RawWaker`] and associated
+     /// task. Calling `wake` on the resulting [`RawWaker`] should result in a wakeup
+     /// of the same task that would have been awoken by the original [`RawWaker`].
+     clone: unsafe fn(*const ()) -> RawWaker,
+ 
+     /// This function will be called when `wake` is called on the [`Waker`].
+     /// It must wake up the task associated with this [`RawWaker`].
+     ///
+     /// The implementation of this function must make sure to release any
+     /// resources that are associated with this instance of a [`RawWaker`] and
+     /// associated task.
+     wake: unsafe fn(*const ()),
+ 
+     /// This function will be called when `wake_by_ref` is called on the [`Waker`].
+     /// It must wake up the task associated with this [`RawWaker`].
+     ///
+     /// This function is similar to `wake`, but must not consume the provided data
+     /// pointer.
+     wake_by_ref: unsafe fn(*const ()),
+ 
+     /// This function gets called when a [`RawWaker`] gets dropped.
+     ///
+     /// The implementation of this function must make sure to release any
+     /// resources that are associated with this instance of a [`RawWaker`] and
+     /// associated task.
+     drop: unsafe fn(*const ()),
+ }
+ 
+ impl RawWakerVTable {
+     /// Creates a new `RawWakerVTable` from the provided `clone`, `wake`,
+     /// `wake_by_ref`, and `drop` functions.
+     ///
+     /// # `clone`
+     ///
+     /// This function will be called when the [`RawWaker`] gets cloned, e.g. when
+     /// the [`Waker`] in which the [`RawWaker`] is stored gets cloned.
+     ///
+     /// The implementation of this function must retain all resources that are
+     /// required for this additional instance of a [`RawWaker`] and associated
+     /// task. Calling `wake` on the resulting [`RawWaker`] should result in a wakeup
+     /// of the same task that would have been awoken by the original [`RawWaker`].
+     ///
+     /// # `wake`
+     ///
+     /// This function will be called when `wake` is called on the [`Waker`].
+     /// It must wake up the task associated with this [`RawWaker`].
+     ///
+     /// The implementation of this function must make sure to release any
+     /// resources that are associated with this instance of a [`RawWaker`] and
+     /// associated task.
+     ///
+     /// # `wake_by_ref`
+     ///
+     /// This function will be called when `wake_by_ref` is called on the [`Waker`].
+     /// It must wake up the task associated with this [`RawWaker`].
+     ///
+     /// This function is similar to `wake`, but must not consume the provided data
+     /// pointer.
+     ///
+     /// # `drop`
+     ///
+     /// This function gets called when a [`RawWaker`] gets dropped.
+     ///
+     /// The implementation of this function must make sure to release any
+     /// resources that are associated with this instance of a [`RawWaker`] and
+     /// associated task.
+     #[rustc_promotable]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     #[rustc_const_stable(feature = "futures_api", since = "1.36.0")]
+     #[cfg_attr(not(bootstrap), rustc_allow_const_fn_unstable(const_fn_fn_ptr_basics))]
+     #[cfg_attr(bootstrap, allow_internal_unstable(const_fn_fn_ptr_basics))]
+     pub const fn new(
+         clone: unsafe fn(*const ()) -> RawWaker,
+         wake: unsafe fn(*const ()),
+         wake_by_ref: unsafe fn(*const ()),
+         drop: unsafe fn(*const ()),
+     ) -> Self {
+         Self { clone, wake, wake_by_ref, drop }
+     }
+ }
+ 
+ /// The `Context` of an asynchronous task.
+ ///
+ /// Currently, `Context` only serves to provide access to a `&Waker`
+ /// which can be used to wake the current task.
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub struct Context<'a> {
+     waker: &'a Waker,
+     // Ensure we future-proof against variance changes by forcing
+     // the lifetime to be invariant (argument-position lifetimes
+     // are contravariant while return-position lifetimes are
+     // covariant).
+     _marker: PhantomData<fn(&'a ()) -> &'a ()>,
+ }
+ 
+ impl<'a> Context<'a> {
+     /// Create a new `Context` from a `&Waker`.
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     #[inline]
+     pub fn from_waker(waker: &'a Waker) -> Self {
+         Context { waker, _marker: PhantomData }
+     }
+ 
+     /// Returns a reference to the `Waker` for the current task.
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     #[inline]
+     pub fn waker(&self) -> &'a Waker {
+         &self.waker
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl fmt::Debug for Context<'_> {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         f.debug_struct("Context").field("waker", &self.waker).finish()
+     }
+ }
+ 
+ /// A `Waker` is a handle for waking up a task by notifying its executor that it
+ /// is ready to be run.
+ ///
+ /// This handle encapsulates a [`RawWaker`] instance, which defines the
+ /// executor-specific wakeup behavior.
+ ///
+ /// Implements [`Clone`], [`Send`], and [`Sync`].
+ #[repr(transparent)]
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ pub struct Waker {
+     waker: RawWaker,
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl Unpin for Waker {}
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ unsafe impl Send for Waker {}
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ unsafe impl Sync for Waker {}
+ 
+ impl Waker {
+     /// Wake up the task associated with this `Waker`.
+     #[inline]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub fn wake(self) {
+         // The actual wakeup call is delegated through a virtual function call
+         // to the implementation which is defined by the executor.
+         let wake = self.waker.vtable.wake;
+         let data = self.waker.data;
+ 
+         // Don't call `drop` -- the waker will be consumed by `wake`.
+         crate::mem::forget(self);
+ 
+         // SAFETY: This is safe because `Waker::from_raw` is the only way
+         // to initialize `wake` and `data` requiring the user to acknowledge
+         // that the contract of `RawWaker` is upheld.
+         unsafe { (wake)(data) };
+     }
+ 
+     /// Wake up the task associated with this `Waker` without consuming the `Waker`.
+     ///
+     /// This is similar to `wake`, but may be slightly less efficient in the case
+     /// where an owned `Waker` is available. This method should be preferred to
+     /// calling `waker.clone().wake()`.
+     #[inline]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub fn wake_by_ref(&self) {
+         // The actual wakeup call is delegated through a virtual function call
+         // to the implementation which is defined by the executor.
+ 
+         // SAFETY: see `wake`
+         unsafe { (self.waker.vtable.wake_by_ref)(self.waker.data) }
+     }
+ 
+     /// Returns `true` if this `Waker` and another `Waker` have awoken the same task.
+     ///
+     /// This function works on a best-effort basis, and may return false even
+     /// when the `Waker`s would awaken the same task. However, if this function
+     /// returns `true`, it is guaranteed that the `Waker`s will awaken the same task.
+     ///
+     /// This function is primarily used for optimization purposes.
+     #[inline]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub fn will_wake(&self, other: &Waker) -> bool {
+         self.waker == other.waker
+     }
+ 
+     /// Creates a new `Waker` from [`RawWaker`].
+     ///
+     /// The behavior of the returned `Waker` is undefined if the contract defined
+     /// in [`RawWaker`]'s and [`RawWakerVTable`]'s documentation is not upheld.
+     /// Therefore this method is unsafe.
+     #[inline]
+     #[stable(feature = "futures_api", since = "1.36.0")]
+     pub unsafe fn from_raw(waker: RawWaker) -> Waker {
+         Waker { waker }
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl Clone for Waker {
+     #[inline]
+     fn clone(&self) -> Self {
+         Waker {
+             // SAFETY: This is safe because `Waker::from_raw` is the only way
+             // to initialize `clone` and `data` requiring the user to acknowledge
+             // that the contract of [`RawWaker`] is upheld.
+             waker: unsafe { (self.waker.vtable.clone)(self.waker.data) },
+         }
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl Drop for Waker {
+     #[inline]
+     fn drop(&mut self) {
+         // SAFETY: This is safe because `Waker::from_raw` is the only way
+         // to initialize `drop` and `data` requiring the user to acknowledge
+         // that the contract of `RawWaker` is upheld.
+         unsafe { (self.waker.vtable.drop)(self.waker.data) }
+     }
+ }
+ 
+ #[stable(feature = "futures_api", since = "1.36.0")]
+ impl fmt::Debug for Waker {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         let vtable_ptr = self.waker.vtable as *const RawWakerVTable;
+         f.debug_struct("Waker")
+             .field("data", &self.waker.data)
+             .field("vtable", &vtable_ptr)
+             .finish()
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/time.rs gcc-16-20251102/libgrust/rustc-lib/core/src/time.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/time.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/time.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1083 ----
+ #![stable(feature = "duration_core", since = "1.25.0")]
+ 
+ //! Temporal quantification.
+ //!
+ //! Example:
+ //!
+ //! ```
+ //! use std::time::Duration;
+ //!
+ //! let five_seconds = Duration::new(5, 0);
+ //! // both declarations are equivalent
+ //! assert_eq!(Duration::new(5, 0), Duration::from_secs(5));
+ //! ```
+ 
+ use crate::fmt;
+ use crate::iter::Sum;
+ use crate::ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Sub, SubAssign};
+ 
+ const NANOS_PER_SEC: u32 = 1_000_000_000;
+ const NANOS_PER_MILLI: u32 = 1_000_000;
+ const NANOS_PER_MICRO: u32 = 1_000;
+ const MILLIS_PER_SEC: u64 = 1_000;
+ const MICROS_PER_SEC: u64 = 1_000_000;
+ 
+ /// A `Duration` type to represent a span of time, typically used for system
+ /// timeouts.
+ ///
+ /// Each `Duration` is composed of a whole number of seconds and a fractional part
+ /// represented in nanoseconds. If the underlying system does not support
+ /// nanosecond-level precision, APIs binding a system timeout will typically round up
+ /// the number of nanoseconds.
+ ///
+ /// [`Duration`]s implement many common traits, including [`Add`], [`Sub`], and other
+ /// [`ops`] traits. It implements [`Default`] by returning a zero-length `Duration`.
+ ///
+ /// [`ops`]: crate::ops
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// use std::time::Duration;
+ ///
+ /// let five_seconds = Duration::new(5, 0);
+ /// let five_seconds_and_five_nanos = five_seconds + Duration::new(0, 5);
+ ///
+ /// assert_eq!(five_seconds_and_five_nanos.as_secs(), 5);
+ /// assert_eq!(five_seconds_and_five_nanos.subsec_nanos(), 5);
+ ///
+ /// let ten_millis = Duration::from_millis(10);
+ /// ```
+ #[stable(feature = "duration", since = "1.3.0")]
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
+ pub struct Duration {
+     secs: u64,
+     nanos: u32, // Always 0 <= nanos < NANOS_PER_SEC
+ }
+ 
+ impl Duration {
+     /// The duration of one second.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::SECOND, Duration::from_secs(1));
+     /// ```
+     #[unstable(feature = "duration_constants", issue = "57391")]
+     pub const SECOND: Duration = Duration::from_secs(1);
+ 
+     /// The duration of one millisecond.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::MILLISECOND, Duration::from_millis(1));
+     /// ```
+     #[unstable(feature = "duration_constants", issue = "57391")]
+     pub const MILLISECOND: Duration = Duration::from_millis(1);
+ 
+     /// The duration of one microsecond.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::MICROSECOND, Duration::from_micros(1));
+     /// ```
+     #[unstable(feature = "duration_constants", issue = "57391")]
+     pub const MICROSECOND: Duration = Duration::from_micros(1);
+ 
+     /// The duration of one nanosecond.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::NANOSECOND, Duration::from_nanos(1));
+     /// ```
+     #[unstable(feature = "duration_constants", issue = "57391")]
+     pub const NANOSECOND: Duration = Duration::from_nanos(1);
+ 
+     /// A duration of zero time.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_zero)]
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::ZERO;
+     /// assert!(duration.is_zero());
+     /// assert_eq!(duration.as_nanos(), 0);
+     /// ```
+     #[unstable(feature = "duration_zero", issue = "73544")]
+     pub const ZERO: Duration = Duration::from_nanos(0);
+ 
+     /// The maximum duration.
+     ///
+     /// It is roughly equal to a duration of 584,942,417,355 years.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::MAX, Duration::new(u64::MAX, 1_000_000_000 - 1));
+     /// ```
+     #[unstable(feature = "duration_constants", issue = "57391")]
+     pub const MAX: Duration = Duration::new(u64::MAX, NANOS_PER_SEC - 1);
+ 
+     /// Creates a new `Duration` from the specified number of whole seconds and
+     /// additional nanoseconds.
+     ///
+     /// If the number of nanoseconds is greater than 1 billion (the number of
+     /// nanoseconds in a second), then it will carry over into the seconds provided.
+     ///
+     /// # Panics
+     ///
+     /// This constructor will panic if the carry from the nanoseconds overflows
+     /// the seconds counter.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let five_seconds = Duration::new(5, 0);
+     /// ```
+     #[stable(feature = "duration", since = "1.3.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn new(secs: u64, nanos: u32) -> Duration {
+         let secs = match secs.checked_add((nanos / NANOS_PER_SEC) as u64) {
+             Some(secs) => secs,
+             None => panic!("overflow in Duration::new"),
+         };
+         let nanos = nanos % NANOS_PER_SEC;
+         Duration { secs, nanos }
+     }
+ 
+     /// Creates a new `Duration` from the specified number of whole seconds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_secs(5);
+     ///
+     /// assert_eq!(5, duration.as_secs());
+     /// assert_eq!(0, duration.subsec_nanos());
+     /// ```
+     #[stable(feature = "duration", since = "1.3.0")]
+     #[inline]
+     #[rustc_const_stable(feature = "duration_consts", since = "1.32.0")]
+     pub const fn from_secs(secs: u64) -> Duration {
+         Duration { secs, nanos: 0 }
+     }
+ 
+     /// Creates a new `Duration` from the specified number of milliseconds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_millis(2569);
+     ///
+     /// assert_eq!(2, duration.as_secs());
+     /// assert_eq!(569_000_000, duration.subsec_nanos());
+     /// ```
+     #[stable(feature = "duration", since = "1.3.0")]
+     #[inline]
+     #[rustc_const_stable(feature = "duration_consts", since = "1.32.0")]
+     pub const fn from_millis(millis: u64) -> Duration {
+         Duration {
+             secs: millis / MILLIS_PER_SEC,
+             nanos: ((millis % MILLIS_PER_SEC) as u32) * NANOS_PER_MILLI,
+         }
+     }
+ 
+     /// Creates a new `Duration` from the specified number of microseconds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_micros(1_000_002);
+     ///
+     /// assert_eq!(1, duration.as_secs());
+     /// assert_eq!(2000, duration.subsec_nanos());
+     /// ```
+     #[stable(feature = "duration_from_micros", since = "1.27.0")]
+     #[inline]
+     #[rustc_const_stable(feature = "duration_consts", since = "1.32.0")]
+     pub const fn from_micros(micros: u64) -> Duration {
+         Duration {
+             secs: micros / MICROS_PER_SEC,
+             nanos: ((micros % MICROS_PER_SEC) as u32) * NANOS_PER_MICRO,
+         }
+     }
+ 
+     /// Creates a new `Duration` from the specified number of nanoseconds.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_nanos(1_000_000_123);
+     ///
+     /// assert_eq!(1, duration.as_secs());
+     /// assert_eq!(123, duration.subsec_nanos());
+     /// ```
+     #[stable(feature = "duration_extras", since = "1.27.0")]
+     #[inline]
+     #[rustc_const_stable(feature = "duration_consts", since = "1.32.0")]
+     pub const fn from_nanos(nanos: u64) -> Duration {
+         Duration {
+             secs: nanos / (NANOS_PER_SEC as u64),
+             nanos: (nanos % (NANOS_PER_SEC as u64)) as u32,
+         }
+     }
+ 
+     /// Returns true if this `Duration` spans no time.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_zero)]
+     /// use std::time::Duration;
+     ///
+     /// assert!(Duration::ZERO.is_zero());
+     /// assert!(Duration::new(0, 0).is_zero());
+     /// assert!(Duration::from_nanos(0).is_zero());
+     /// assert!(Duration::from_secs(0).is_zero());
+     ///
+     /// assert!(!Duration::new(1, 1).is_zero());
+     /// assert!(!Duration::from_nanos(1).is_zero());
+     /// assert!(!Duration::from_secs(1).is_zero());
+     /// ```
+     #[unstable(feature = "duration_zero", issue = "73544")]
+     #[inline]
+     pub const fn is_zero(&self) -> bool {
+         self.secs == 0 && self.nanos == 0
+     }
+ 
+     /// Returns the number of _whole_ seconds contained by this `Duration`.
+     ///
+     /// The returned value does not include the fractional (nanosecond) part of the
+     /// duration, which can be obtained using [`subsec_nanos`].
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::new(5, 730023852);
+     /// assert_eq!(duration.as_secs(), 5);
+     /// ```
+     ///
+     /// To determine the total number of seconds represented by the `Duration`,
+     /// use `as_secs` in combination with [`subsec_nanos`]:
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::new(5, 730023852);
+     ///
+     /// assert_eq!(5.730023852,
+     ///            duration.as_secs() as f64
+     ///            + duration.subsec_nanos() as f64 * 1e-9);
+     /// ```
+     ///
+     /// [`subsec_nanos`]: Duration::subsec_nanos
+     #[stable(feature = "duration", since = "1.3.0")]
+     #[rustc_const_stable(feature = "duration", since = "1.32.0")]
+     #[inline]
+     pub const fn as_secs(&self) -> u64 {
+         self.secs
+     }
+ 
+     /// Returns the fractional part of this `Duration`, in whole milliseconds.
+     ///
+     /// This method does **not** return the length of the duration when
+     /// represented by milliseconds. The returned number always represents a
+     /// fractional portion of a second (i.e., it is less than one thousand).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_millis(5432);
+     /// assert_eq!(duration.as_secs(), 5);
+     /// assert_eq!(duration.subsec_millis(), 432);
+     /// ```
+     #[stable(feature = "duration_extras", since = "1.27.0")]
+     #[rustc_const_stable(feature = "duration_extras", since = "1.32.0")]
+     #[inline]
+     pub const fn subsec_millis(&self) -> u32 {
+         self.nanos / NANOS_PER_MILLI
+     }
+ 
+     /// Returns the fractional part of this `Duration`, in whole microseconds.
+     ///
+     /// This method does **not** return the length of the duration when
+     /// represented by microseconds. The returned number always represents a
+     /// fractional portion of a second (i.e., it is less than one million).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_micros(1_234_567);
+     /// assert_eq!(duration.as_secs(), 1);
+     /// assert_eq!(duration.subsec_micros(), 234_567);
+     /// ```
+     #[stable(feature = "duration_extras", since = "1.27.0")]
+     #[rustc_const_stable(feature = "duration_extras", since = "1.32.0")]
+     #[inline]
+     pub const fn subsec_micros(&self) -> u32 {
+         self.nanos / NANOS_PER_MICRO
+     }
+ 
+     /// Returns the fractional part of this `Duration`, in nanoseconds.
+     ///
+     /// This method does **not** return the length of the duration when
+     /// represented by nanoseconds. The returned number always represents a
+     /// fractional portion of a second (i.e., it is less than one billion).
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::from_millis(5010);
+     /// assert_eq!(duration.as_secs(), 5);
+     /// assert_eq!(duration.subsec_nanos(), 10_000_000);
+     /// ```
+     #[stable(feature = "duration", since = "1.3.0")]
+     #[rustc_const_stable(feature = "duration", since = "1.32.0")]
+     #[inline]
+     pub const fn subsec_nanos(&self) -> u32 {
+         self.nanos
+     }
+ 
+     /// Returns the total number of whole milliseconds contained by this `Duration`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::new(5, 730023852);
+     /// assert_eq!(duration.as_millis(), 5730);
+     /// ```
+     #[stable(feature = "duration_as_u128", since = "1.33.0")]
+     #[rustc_const_stable(feature = "duration_as_u128", since = "1.33.0")]
+     #[inline]
+     pub const fn as_millis(&self) -> u128 {
+         self.secs as u128 * MILLIS_PER_SEC as u128 + (self.nanos / NANOS_PER_MILLI) as u128
+     }
+ 
+     /// Returns the total number of whole microseconds contained by this `Duration`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::new(5, 730023852);
+     /// assert_eq!(duration.as_micros(), 5730023);
+     /// ```
+     #[stable(feature = "duration_as_u128", since = "1.33.0")]
+     #[rustc_const_stable(feature = "duration_as_u128", since = "1.33.0")]
+     #[inline]
+     pub const fn as_micros(&self) -> u128 {
+         self.secs as u128 * MICROS_PER_SEC as u128 + (self.nanos / NANOS_PER_MICRO) as u128
+     }
+ 
+     /// Returns the total number of nanoseconds contained by this `Duration`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let duration = Duration::new(5, 730023852);
+     /// assert_eq!(duration.as_nanos(), 5730023852);
+     /// ```
+     #[stable(feature = "duration_as_u128", since = "1.33.0")]
+     #[rustc_const_stable(feature = "duration_as_u128", since = "1.33.0")]
+     #[inline]
+     pub const fn as_nanos(&self) -> u128 {
+         self.secs as u128 * NANOS_PER_SEC as u128 + self.nanos as u128
+     }
+ 
+     /// Checked `Duration` addition. Computes `self + other`, returning [`None`]
+     /// if overflow occurred.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(0, 0).checked_add(Duration::new(0, 1)), Some(Duration::new(0, 1)));
+     /// assert_eq!(Duration::new(1, 0).checked_add(Duration::new(u64::MAX, 0)), None);
+     /// ```
+     #[stable(feature = "duration_checked_ops", since = "1.16.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn checked_add(self, rhs: Duration) -> Option<Duration> {
+         if let Some(mut secs) = self.secs.checked_add(rhs.secs) {
+             let mut nanos = self.nanos + rhs.nanos;
+             if nanos >= NANOS_PER_SEC {
+                 nanos -= NANOS_PER_SEC;
+                 if let Some(new_secs) = secs.checked_add(1) {
+                     secs = new_secs;
+                 } else {
+                     return None;
+                 }
+             }
+             debug_assert!(nanos < NANOS_PER_SEC);
+             Some(Duration { secs, nanos })
+         } else {
+             None
+         }
+     }
+ 
+     /// Saturating `Duration` addition. Computes `self + other`, returning [`Duration::MAX`]
+     /// if overflow occurred.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_saturating_ops)]
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(0, 0).saturating_add(Duration::new(0, 1)), Duration::new(0, 1));
+     /// assert_eq!(Duration::new(1, 0).saturating_add(Duration::new(u64::MAX, 0)), Duration::MAX);
+     /// ```
+     #[unstable(feature = "duration_saturating_ops", issue = "76416")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn saturating_add(self, rhs: Duration) -> Duration {
+         match self.checked_add(rhs) {
+             Some(res) => res,
+             None => Duration::MAX,
+         }
+     }
+ 
+     /// Checked `Duration` subtraction. Computes `self - other`, returning [`None`]
+     /// if the result would be negative or if overflow occurred.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(0, 1).checked_sub(Duration::new(0, 0)), Some(Duration::new(0, 1)));
+     /// assert_eq!(Duration::new(0, 0).checked_sub(Duration::new(0, 1)), None);
+     /// ```
+     #[stable(feature = "duration_checked_ops", since = "1.16.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn checked_sub(self, rhs: Duration) -> Option<Duration> {
+         if let Some(mut secs) = self.secs.checked_sub(rhs.secs) {
+             let nanos = if self.nanos >= rhs.nanos {
+                 self.nanos - rhs.nanos
+             } else {
+                 if let Some(sub_secs) = secs.checked_sub(1) {
+                     secs = sub_secs;
+                     self.nanos + NANOS_PER_SEC - rhs.nanos
+                 } else {
+                     return None;
+                 }
+             };
+             debug_assert!(nanos < NANOS_PER_SEC);
+             Some(Duration { secs, nanos })
+         } else {
+             None
+         }
+     }
+ 
+     /// Saturating `Duration` subtraction. Computes `self - other`, returning [`Duration::ZERO`]
+     /// if the result would be negative or if overflow occurred.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_saturating_ops)]
+     /// #![feature(duration_zero)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(0, 1).saturating_sub(Duration::new(0, 0)), Duration::new(0, 1));
+     /// assert_eq!(Duration::new(0, 0).saturating_sub(Duration::new(0, 1)), Duration::ZERO);
+     /// ```
+     #[unstable(feature = "duration_saturating_ops", issue = "76416")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn saturating_sub(self, rhs: Duration) -> Duration {
+         match self.checked_sub(rhs) {
+             Some(res) => res,
+             None => Duration::ZERO,
+         }
+     }
+ 
+     /// Checked `Duration` multiplication. Computes `self * other`, returning
+     /// [`None`] if overflow occurred.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(0, 500_000_001).checked_mul(2), Some(Duration::new(1, 2)));
+     /// assert_eq!(Duration::new(u64::MAX - 1, 0).checked_mul(2), None);
+     /// ```
+     #[stable(feature = "duration_checked_ops", since = "1.16.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn checked_mul(self, rhs: u32) -> Option<Duration> {
+         // Multiply nanoseconds as u64, because it cannot overflow that way.
+         let total_nanos = self.nanos as u64 * rhs as u64;
+         let extra_secs = total_nanos / (NANOS_PER_SEC as u64);
+         let nanos = (total_nanos % (NANOS_PER_SEC as u64)) as u32;
+         if let Some(s) = self.secs.checked_mul(rhs as u64) {
+             if let Some(secs) = s.checked_add(extra_secs) {
+                 debug_assert!(nanos < NANOS_PER_SEC);
+                 return Some(Duration { secs, nanos });
+             }
+         }
+         None
+     }
+ 
+     /// Saturating `Duration` multiplication. Computes `self * other`, returning
+     /// [`Duration::MAX`] if overflow occurred.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #![feature(duration_saturating_ops)]
+     /// #![feature(duration_constants)]
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(0, 500_000_001).saturating_mul(2), Duration::new(1, 2));
+     /// assert_eq!(Duration::new(u64::MAX - 1, 0).saturating_mul(2), Duration::MAX);
+     /// ```
+     #[unstable(feature = "duration_saturating_ops", issue = "76416")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn saturating_mul(self, rhs: u32) -> Duration {
+         match self.checked_mul(rhs) {
+             Some(res) => res,
+             None => Duration::MAX,
+         }
+     }
+ 
+     /// Checked `Duration` division. Computes `self / other`, returning [`None`]
+     /// if `other == 0`.
+     ///
+     /// # Examples
+     ///
+     /// Basic usage:
+     ///
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// assert_eq!(Duration::new(2, 0).checked_div(2), Some(Duration::new(1, 0)));
+     /// assert_eq!(Duration::new(1, 0).checked_div(2), Some(Duration::new(0, 500_000_000)));
+     /// assert_eq!(Duration::new(2, 0).checked_div(0), None);
+     /// ```
+     #[stable(feature = "duration_checked_ops", since = "1.16.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn checked_div(self, rhs: u32) -> Option<Duration> {
+         if rhs != 0 {
+             let secs = self.secs / (rhs as u64);
+             let carry = self.secs - secs * (rhs as u64);
+             let extra_nanos = carry * (NANOS_PER_SEC as u64) / (rhs as u64);
+             let nanos = self.nanos / rhs + (extra_nanos as u32);
+             debug_assert!(nanos < NANOS_PER_SEC);
+             Some(Duration { secs, nanos })
+         } else {
+             None
+         }
+     }
+ 
+     /// Returns the number of seconds contained by this `Duration` as `f64`.
+     ///
+     /// The returned value does include the fractional (nanosecond) part of the duration.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::new(2, 700_000_000);
+     /// assert_eq!(dur.as_secs_f64(), 2.7);
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn as_secs_f64(&self) -> f64 {
+         (self.secs as f64) + (self.nanos as f64) / (NANOS_PER_SEC as f64)
+     }
+ 
+     /// Returns the number of seconds contained by this `Duration` as `f32`.
+     ///
+     /// The returned value does include the fractional (nanosecond) part of the duration.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::new(2, 700_000_000);
+     /// assert_eq!(dur.as_secs_f32(), 2.7);
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn as_secs_f32(&self) -> f32 {
+         (self.secs as f32) + (self.nanos as f32) / (NANOS_PER_SEC as f32)
+     }
+ 
+     /// Creates a new `Duration` from the specified number of seconds represented
+     /// as `f64`.
+     ///
+     /// # Panics
+     /// This constructor will panic if `secs` is not finite, negative or overflows `Duration`.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::from_secs_f64(2.7);
+     /// assert_eq!(dur, Duration::new(2, 700_000_000));
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn from_secs_f64(secs: f64) -> Duration {
+         const MAX_NANOS_F64: f64 = ((u64::MAX as u128 + 1) * (NANOS_PER_SEC as u128)) as f64;
+         let nanos = secs * (NANOS_PER_SEC as f64);
+         if !nanos.is_finite() {
+             panic!("got non-finite value when converting float to duration");
+         }
+         if nanos >= MAX_NANOS_F64 {
+             panic!("overflow when converting float to duration");
+         }
+         if nanos < 0.0 {
+             panic!("underflow when converting float to duration");
+         }
+         let nanos = nanos as u128;
+         Duration {
+             secs: (nanos / (NANOS_PER_SEC as u128)) as u64,
+             nanos: (nanos % (NANOS_PER_SEC as u128)) as u32,
+         }
+     }
+ 
+     /// Creates a new `Duration` from the specified number of seconds represented
+     /// as `f32`.
+     ///
+     /// # Panics
+     /// This constructor will panic if `secs` is not finite, negative or overflows `Duration`.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::from_secs_f32(2.7);
+     /// assert_eq!(dur, Duration::new(2, 700_000_000));
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn from_secs_f32(secs: f32) -> Duration {
+         const MAX_NANOS_F32: f32 = ((u64::MAX as u128 + 1) * (NANOS_PER_SEC as u128)) as f32;
+         let nanos = secs * (NANOS_PER_SEC as f32);
+         if !nanos.is_finite() {
+             panic!("got non-finite value when converting float to duration");
+         }
+         if nanos >= MAX_NANOS_F32 {
+             panic!("overflow when converting float to duration");
+         }
+         if nanos < 0.0 {
+             panic!("underflow when converting float to duration");
+         }
+         let nanos = nanos as u128;
+         Duration {
+             secs: (nanos / (NANOS_PER_SEC as u128)) as u64,
+             nanos: (nanos % (NANOS_PER_SEC as u128)) as u32,
+         }
+     }
+ 
+     /// Multiplies `Duration` by `f64`.
+     ///
+     /// # Panics
+     /// This method will panic if result is not finite, negative or overflows `Duration`.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::new(2, 700_000_000);
+     /// assert_eq!(dur.mul_f64(3.14), Duration::new(8, 478_000_000));
+     /// assert_eq!(dur.mul_f64(3.14e5), Duration::new(847_800, 0));
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn mul_f64(self, rhs: f64) -> Duration {
+         Duration::from_secs_f64(rhs * self.as_secs_f64())
+     }
+ 
+     /// Multiplies `Duration` by `f32`.
+     ///
+     /// # Panics
+     /// This method will panic if result is not finite, negative or overflows `Duration`.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::new(2, 700_000_000);
+     /// // note that due to rounding errors result is slightly different
+     /// // from 8.478 and 847800.0
+     /// assert_eq!(dur.mul_f32(3.14), Duration::new(8, 478_000_640));
+     /// assert_eq!(dur.mul_f32(3.14e5), Duration::new(847799, 969_120_256));
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn mul_f32(self, rhs: f32) -> Duration {
+         Duration::from_secs_f32(rhs * self.as_secs_f32())
+     }
+ 
+     /// Divide `Duration` by `f64`.
+     ///
+     /// # Panics
+     /// This method will panic if result is not finite, negative or overflows `Duration`.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::new(2, 700_000_000);
+     /// assert_eq!(dur.div_f64(3.14), Duration::new(0, 859_872_611));
+     /// // note that truncation is used, not rounding
+     /// assert_eq!(dur.div_f64(3.14e5), Duration::new(0, 8_598));
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn div_f64(self, rhs: f64) -> Duration {
+         Duration::from_secs_f64(self.as_secs_f64() / rhs)
+     }
+ 
+     /// Divide `Duration` by `f32`.
+     ///
+     /// # Panics
+     /// This method will panic if result is not finite, negative or overflows `Duration`.
+     ///
+     /// # Examples
+     /// ```
+     /// use std::time::Duration;
+     ///
+     /// let dur = Duration::new(2, 700_000_000);
+     /// // note that due to rounding errors result is slightly
+     /// // different from 0.859_872_611
+     /// assert_eq!(dur.div_f32(3.14), Duration::new(0, 859_872_576));
+     /// // note that truncation is used, not rounding
+     /// assert_eq!(dur.div_f32(3.14e5), Duration::new(0, 8_598));
+     /// ```
+     #[stable(feature = "duration_float", since = "1.38.0")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn div_f32(self, rhs: f32) -> Duration {
+         Duration::from_secs_f32(self.as_secs_f32() / rhs)
+     }
+ 
+     /// Divide `Duration` by `Duration` and return `f64`.
+     ///
+     /// # Examples
+     /// ```
+     /// #![feature(div_duration)]
+     /// use std::time::Duration;
+     ///
+     /// let dur1 = Duration::new(2, 700_000_000);
+     /// let dur2 = Duration::new(5, 400_000_000);
+     /// assert_eq!(dur1.div_duration_f64(dur2), 0.5);
+     /// ```
+     #[unstable(feature = "div_duration", issue = "63139")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn div_duration_f64(self, rhs: Duration) -> f64 {
+         self.as_secs_f64() / rhs.as_secs_f64()
+     }
+ 
+     /// Divide `Duration` by `Duration` and return `f32`.
+     ///
+     /// # Examples
+     /// ```
+     /// #![feature(div_duration)]
+     /// use std::time::Duration;
+     ///
+     /// let dur1 = Duration::new(2, 700_000_000);
+     /// let dur2 = Duration::new(5, 400_000_000);
+     /// assert_eq!(dur1.div_duration_f32(dur2), 0.5);
+     /// ```
+     #[unstable(feature = "div_duration", issue = "63139")]
+     #[inline]
+     #[rustc_const_unstable(feature = "duration_consts_2", issue = "72440")]
+     pub const fn div_duration_f32(self, rhs: Duration) -> f32 {
+         self.as_secs_f32() / rhs.as_secs_f32()
+     }
+ }
+ 
+ #[stable(feature = "duration", since = "1.3.0")]
+ impl Add for Duration {
+     type Output = Duration;
+ 
+     fn add(self, rhs: Duration) -> Duration {
+         self.checked_add(rhs).expect("overflow when adding durations")
+     }
+ }
+ 
+ #[stable(feature = "time_augmented_assignment", since = "1.9.0")]
+ impl AddAssign for Duration {
+     fn add_assign(&mut self, rhs: Duration) {
+         *self = *self + rhs;
+     }
+ }
+ 
+ #[stable(feature = "duration", since = "1.3.0")]
+ impl Sub for Duration {
+     type Output = Duration;
+ 
+     fn sub(self, rhs: Duration) -> Duration {
+         self.checked_sub(rhs).expect("overflow when subtracting durations")
+     }
+ }
+ 
+ #[stable(feature = "time_augmented_assignment", since = "1.9.0")]
+ impl SubAssign for Duration {
+     fn sub_assign(&mut self, rhs: Duration) {
+         *self = *self - rhs;
+     }
+ }
+ 
+ #[stable(feature = "duration", since = "1.3.0")]
+ impl Mul<u32> for Duration {
+     type Output = Duration;
+ 
+     fn mul(self, rhs: u32) -> Duration {
+         self.checked_mul(rhs).expect("overflow when multiplying duration by scalar")
+     }
+ }
+ 
+ #[stable(feature = "symmetric_u32_duration_mul", since = "1.31.0")]
+ impl Mul<Duration> for u32 {
+     type Output = Duration;
+ 
+     fn mul(self, rhs: Duration) -> Duration {
+         rhs * self
+     }
+ }
+ 
+ #[stable(feature = "time_augmented_assignment", since = "1.9.0")]
+ impl MulAssign<u32> for Duration {
+     fn mul_assign(&mut self, rhs: u32) {
+         *self = *self * rhs;
+     }
+ }
+ 
+ #[stable(feature = "duration", since = "1.3.0")]
+ impl Div<u32> for Duration {
+     type Output = Duration;
+ 
+     fn div(self, rhs: u32) -> Duration {
+         self.checked_div(rhs).expect("divide by zero error when dividing duration by scalar")
+     }
+ }
+ 
+ #[stable(feature = "time_augmented_assignment", since = "1.9.0")]
+ impl DivAssign<u32> for Duration {
+     fn div_assign(&mut self, rhs: u32) {
+         *self = *self / rhs;
+     }
+ }
+ 
+ macro_rules! sum_durations {
+     ($iter:expr) => {{
+         let mut total_secs: u64 = 0;
+         let mut total_nanos: u64 = 0;
+ 
+         for entry in $iter {
+             total_secs =
+                 total_secs.checked_add(entry.secs).expect("overflow in iter::sum over durations");
+             total_nanos = match total_nanos.checked_add(entry.nanos as u64) {
+                 Some(n) => n,
+                 None => {
+                     total_secs = total_secs
+                         .checked_add(total_nanos / NANOS_PER_SEC as u64)
+                         .expect("overflow in iter::sum over durations");
+                     (total_nanos % NANOS_PER_SEC as u64) + entry.nanos as u64
+                 }
+             };
+         }
+         total_secs = total_secs
+             .checked_add(total_nanos / NANOS_PER_SEC as u64)
+             .expect("overflow in iter::sum over durations");
+         total_nanos = total_nanos % NANOS_PER_SEC as u64;
+         Duration { secs: total_secs, nanos: total_nanos as u32 }
+     }};
+ }
+ 
+ #[stable(feature = "duration_sum", since = "1.16.0")]
+ impl Sum for Duration {
+     fn sum<I: Iterator<Item = Duration>>(iter: I) -> Duration {
+         sum_durations!(iter)
+     }
+ }
+ 
+ #[stable(feature = "duration_sum", since = "1.16.0")]
+ impl<'a> Sum<&'a Duration> for Duration {
+     fn sum<I: Iterator<Item = &'a Duration>>(iter: I) -> Duration {
+         sum_durations!(iter)
+     }
+ }
+ 
+ #[stable(feature = "duration_debug_impl", since = "1.27.0")]
+ impl fmt::Debug for Duration {
+     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+         /// Formats a floating point number in decimal notation.
+         ///
+         /// The number is given as the `integer_part` and a fractional part.
+         /// The value of the fractional part is `fractional_part / divisor`. So
+         /// `integer_part` = 3, `fractional_part` = 12 and `divisor` = 100
+         /// represents the number `3.012`. Trailing zeros are omitted.
+         ///
+         /// `divisor` must not be above 100_000_000. It also should be a power
+         /// of 10, everything else doesn't make sense. `fractional_part` has
+         /// to be less than `10 * divisor`!
+         fn fmt_decimal(
+             f: &mut fmt::Formatter<'_>,
+             mut integer_part: u64,
+             mut fractional_part: u32,
+             mut divisor: u32,
+         ) -> fmt::Result {
+             // Encode the fractional part into a temporary buffer. The buffer
+             // only need to hold 9 elements, because `fractional_part` has to
+             // be smaller than 10^9. The buffer is prefilled with '0' digits
+             // to simplify the code below.
+             let mut buf = [b'0'; 9];
+ 
+             // The next digit is written at this position
+             let mut pos = 0;
+ 
+             // We keep writing digits into the buffer while there are non-zero
+             // digits left and we haven't written enough digits yet.
+             while fractional_part > 0 && pos < f.precision().unwrap_or(9) {
+                 // Write new digit into the buffer
+                 buf[pos] = b'0' + (fractional_part / divisor) as u8;
+ 
+                 fractional_part %= divisor;
+                 divisor /= 10;
+                 pos += 1;
+             }
+ 
+             // If a precision < 9 was specified, there may be some non-zero
+             // digits left that weren't written into the buffer. In that case we
+             // need to perform rounding to match the semantics of printing
+             // normal floating point numbers. However, we only need to do work
+             // when rounding up. This happens if the first digit of the
+             // remaining ones is >= 5.
+             if fractional_part > 0 && fractional_part >= divisor * 5 {
+                 // Round up the number contained in the buffer. We go through
+                 // the buffer backwards and keep track of the carry.
+                 let mut rev_pos = pos;
+                 let mut carry = true;
+                 while carry && rev_pos > 0 {
+                     rev_pos -= 1;
+ 
+                     // If the digit in the buffer is not '9', we just need to
+                     // increment it and can stop then (since we don't have a
+                     // carry anymore). Otherwise, we set it to '0' (overflow)
+                     // and continue.
+                     if buf[rev_pos] < b'9' {
+                         buf[rev_pos] += 1;
+                         carry = false;
+                     } else {
+                         buf[rev_pos] = b'0';
+                     }
+                 }
+ 
+                 // If we still have the carry bit set, that means that we set
+                 // the whole buffer to '0's and need to increment the integer
+                 // part.
+                 if carry {
+                     integer_part += 1;
+                 }
+             }
+ 
+             // Determine the end of the buffer: if precision is set, we just
+             // use as many digits from the buffer (capped to 9). If it isn't
+             // set, we only use all digits up to the last non-zero one.
+             let end = f.precision().map(|p| crate::cmp::min(p, 9)).unwrap_or(pos);
+ 
+             // If we haven't emitted a single fractional digit and the precision
+             // wasn't set to a non-zero value, we don't print the decimal point.
+             if end == 0 {
+                 write!(f, "{}", integer_part)
+             } else {
+                 // SAFETY: We are only writing ASCII digits into the buffer and it was
+                 // initialized with '0's, so it contains valid UTF8.
+                 let s = unsafe { crate::str::from_utf8_unchecked(&buf[..end]) };
+ 
+                 // If the user request a precision > 9, we pad '0's at the end.
+                 let w = f.precision().unwrap_or(pos);
+                 write!(f, "{}.{:0<width$}", integer_part, s, width = w)
+             }
+         }
+ 
+         // Print leading '+' sign if requested
+         if f.sign_plus() {
+             write!(f, "+")?;
+         }
+ 
+         if self.secs > 0 {
+             fmt_decimal(f, self.secs, self.nanos, 100_000_000)?;
+             f.write_str("s")
+         } else if self.nanos >= 1_000_000 {
+             fmt_decimal(f, self.nanos as u64 / 1_000_000, self.nanos % 1_000_000, 100_000)?;
+             f.write_str("ms")
+         } else if self.nanos >= 1_000 {
+             fmt_decimal(f, self.nanos as u64 / 1_000, self.nanos % 1_000, 100)?;
+             f.write_str("µs")
+         } else {
+             fmt_decimal(f, self.nanos as u64, 0, 1)?;
+             f.write_str("ns")
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/tuple.rs gcc-16-20251102/libgrust/rustc-lib/core/src/tuple.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/tuple.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/tuple.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,213 ----
+ // See src/libstd/primitive_docs.rs for documentation.
+ 
+ use crate::cmp::Ordering::*;
+ use crate::cmp::*;
+ 
+ // macro for implementing n-ary tuple functions and operations
+ macro_rules! tuple_impls {
+     ($(
+         $Tuple:ident {
+             $(($idx:tt) -> $T:ident)+
+         }
+     )+) => {
+         $(
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl<$($T:PartialEq),+> PartialEq for ($($T,)+) where last_type!($($T,)+): ?Sized {
+                 #[inline]
+                 fn eq(&self, other: &($($T,)+)) -> bool {
+                     $(self.$idx == other.$idx)&&+
+                 }
+                 #[inline]
+                 fn ne(&self, other: &($($T,)+)) -> bool {
+                     $(self.$idx != other.$idx)||+
+                 }
+             }
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl<$($T:Eq),+> Eq for ($($T,)+) where last_type!($($T,)+): ?Sized {}
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl<$($T:PartialOrd + PartialEq),+> PartialOrd for ($($T,)+)
+                     where last_type!($($T,)+): ?Sized {
+                 #[inline]
+                 fn partial_cmp(&self, other: &($($T,)+)) -> Option<Ordering> {
+                     lexical_partial_cmp!($(self.$idx, other.$idx),+)
+                 }
+                 #[inline]
+                 fn lt(&self, other: &($($T,)+)) -> bool {
+                     lexical_ord!(lt, $(self.$idx, other.$idx),+)
+                 }
+                 #[inline]
+                 fn le(&self, other: &($($T,)+)) -> bool {
+                     lexical_ord!(le, $(self.$idx, other.$idx),+)
+                 }
+                 #[inline]
+                 fn ge(&self, other: &($($T,)+)) -> bool {
+                     lexical_ord!(ge, $(self.$idx, other.$idx),+)
+                 }
+                 #[inline]
+                 fn gt(&self, other: &($($T,)+)) -> bool {
+                     lexical_ord!(gt, $(self.$idx, other.$idx),+)
+                 }
+             }
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl<$($T:Ord),+> Ord for ($($T,)+) where last_type!($($T,)+): ?Sized {
+                 #[inline]
+                 fn cmp(&self, other: &($($T,)+)) -> Ordering {
+                     lexical_cmp!($(self.$idx, other.$idx),+)
+                 }
+             }
+ 
+             #[stable(feature = "rust1", since = "1.0.0")]
+             impl<$($T:Default),+> Default for ($($T,)+) {
+                 #[inline]
+                 fn default() -> ($($T,)+) {
+                     ($({ let x: $T = Default::default(); x},)+)
+                 }
+             }
+         )+
+     }
+ }
+ 
+ // Constructs an expression that performs a lexical ordering using method $rel.
+ // The values are interleaved, so the macro invocation for
+ // `(a1, a2, a3) < (b1, b2, b3)` would be `lexical_ord!(lt, a1, b1, a2, b2,
+ // a3, b3)` (and similarly for `lexical_cmp`)
+ macro_rules! lexical_ord {
+     ($rel: ident, $a:expr, $b:expr, $($rest_a:expr, $rest_b:expr),+) => {
+         if $a != $b { lexical_ord!($rel, $a, $b) }
+         else { lexical_ord!($rel, $($rest_a, $rest_b),+) }
+     };
+     ($rel: ident, $a:expr, $b:expr) => { ($a) . $rel (& $b) };
+ }
+ 
+ macro_rules! lexical_partial_cmp {
+     ($a:expr, $b:expr, $($rest_a:expr, $rest_b:expr),+) => {
+         match ($a).partial_cmp(&$b) {
+             Some(Equal) => lexical_partial_cmp!($($rest_a, $rest_b),+),
+             ordering   => ordering
+         }
+     };
+     ($a:expr, $b:expr) => { ($a).partial_cmp(&$b) };
+ }
+ 
+ macro_rules! lexical_cmp {
+     ($a:expr, $b:expr, $($rest_a:expr, $rest_b:expr),+) => {
+         match ($a).cmp(&$b) {
+             Equal => lexical_cmp!($($rest_a, $rest_b),+),
+             ordering   => ordering
+         }
+     };
+     ($a:expr, $b:expr) => { ($a).cmp(&$b) };
+ }
+ 
+ macro_rules! last_type {
+     ($a:ident,) => { $a };
+     ($a:ident, $($rest_a:ident,)+) => { last_type!($($rest_a,)+) };
+ }
+ 
+ tuple_impls! {
+     Tuple1 {
+         (0) -> A
+     }
+     Tuple2 {
+         (0) -> A
+         (1) -> B
+     }
+     Tuple3 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+     }
+     Tuple4 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+     }
+     Tuple5 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+     }
+     Tuple6 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+     }
+     Tuple7 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+         (6) -> G
+     }
+     Tuple8 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+         (6) -> G
+         (7) -> H
+     }
+     Tuple9 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+         (6) -> G
+         (7) -> H
+         (8) -> I
+     }
+     Tuple10 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+         (6) -> G
+         (7) -> H
+         (8) -> I
+         (9) -> J
+     }
+     Tuple11 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+         (6) -> G
+         (7) -> H
+         (8) -> I
+         (9) -> J
+         (10) -> K
+     }
+     Tuple12 {
+         (0) -> A
+         (1) -> B
+         (2) -> C
+         (3) -> D
+         (4) -> E
+         (5) -> F
+         (6) -> G
+         (7) -> H
+         (8) -> I
+         (9) -> J
+         (10) -> K
+         (11) -> L
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,34 ----
+ #![unstable(feature = "unicode_internals", issue = "none")]
+ #![allow(missing_docs)]
+ 
+ pub(crate) mod printable;
+ mod unicode_data;
+ 
+ /// The version of [Unicode](http://www.unicode.org/) that the Unicode parts of
+ /// `char` and `str` methods are based on.
+ ///
+ /// New versions of Unicode are released regularly and subsequently all methods
+ /// in the standard library depending on Unicode are updated. Therefore the
+ /// behavior of some `char` and `str` methods and the value of this constant
+ /// changes over time. This is *not* considered to be a breaking change.
+ ///
+ /// The version numbering scheme is explained in
+ /// [Unicode 11.0 or later, Section 3.1 Versions of the Unicode Standard](https://www.unicode.org/versions/Unicode11.0.0/ch03.pdf#page=4).
+ #[stable(feature = "unicode_version", since = "1.45.0")]
+ pub const UNICODE_VERSION: (u8, u8, u8) = unicode_data::UNICODE_VERSION;
+ 
+ // For use in liballoc, not re-exported in libstd.
+ pub mod derived_property {
+     pub use super::{Case_Ignorable, Cased};
+ }
+ 
+ pub use unicode_data::alphabetic::lookup as Alphabetic;
+ pub use unicode_data::case_ignorable::lookup as Case_Ignorable;
+ pub use unicode_data::cased::lookup as Cased;
+ pub use unicode_data::cc::lookup as Cc;
+ pub use unicode_data::conversions;
+ pub use unicode_data::grapheme_extend::lookup as Grapheme_Extend;
+ pub use unicode_data::lowercase::lookup as Lowercase;
+ pub use unicode_data::n::lookup as N;
+ pub use unicode_data::uppercase::lookup as Uppercase;
+ pub use unicode_data::white_space::lookup as White_Space;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/printable.py gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/printable.py
*** gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/printable.py	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/printable.py	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,236 ----
+ #!/usr/bin/env python
+ 
+ # This script uses the following Unicode tables:
+ # - UnicodeData.txt
+ 
+ 
+ from collections import namedtuple
+ import csv
+ import os
+ import subprocess
+ 
+ NUM_CODEPOINTS=0x110000
+ 
+ def to_ranges(iter):
+     current = None
+     for i in iter:
+         if current is None or i != current[1] or i in (0x10000, 0x20000):
+             if current is not None:
+                 yield tuple(current)
+             current = [i, i + 1]
+         else:
+             current[1] += 1
+     if current is not None:
+         yield tuple(current)
+ 
+ def get_escaped(codepoints):
+     for c in codepoints:
+         if (c.class_ or "Cn") in "Cc Cf Cs Co Cn Zl Zp Zs".split() and c.value != ord(' '):
+             yield c.value
+ 
+ def get_file(f):
+     try:
+         return open(os.path.basename(f))
+     except FileNotFoundError:
+         subprocess.run(["curl", "-O", f], check=True)
+         return open(os.path.basename(f))
+ 
+ Codepoint = namedtuple('Codepoint', 'value class_')
+ 
+ def get_codepoints(f):
+     r = csv.reader(f, delimiter=";")
+     prev_codepoint = 0
+     class_first = None
+     for row in r:
+         codepoint = int(row[0], 16)
+         name = row[1]
+         class_ = row[2]
+ 
+         if class_first is not None:
+             if not name.endswith("Last>"):
+                 raise ValueError("Missing Last after First")
+ 
+         for c in range(prev_codepoint + 1, codepoint):
+             yield Codepoint(c, class_first)
+ 
+         class_first = None
+         if name.endswith("First>"):
+             class_first = class_
+ 
+         yield Codepoint(codepoint, class_)
+         prev_codepoint = codepoint
+ 
+     if class_first is not None:
+         raise ValueError("Missing Last after First")
+ 
+     for c in range(prev_codepoint + 1, NUM_CODEPOINTS):
+         yield Codepoint(c, None)
+ 
+ def compress_singletons(singletons):
+     uppers = [] # (upper, # items in lowers)
+     lowers = []
+ 
+     for i in singletons:
+         upper = i >> 8
+         lower = i & 0xff
+         if len(uppers) == 0 or uppers[-1][0] != upper:
+             uppers.append((upper, 1))
+         else:
+             upper, count = uppers[-1]
+             uppers[-1] = upper, count + 1
+         lowers.append(lower)
+ 
+     return uppers, lowers
+ 
+ def compress_normal(normal):
+     # lengths 0x00..0x7f are encoded as 00, 01, ..., 7e, 7f
+     # lengths 0x80..0x7fff are encoded as 80 80, 80 81, ..., ff fe, ff ff
+     compressed = [] # [truelen, (truelenaux), falselen, (falselenaux)]
+ 
+     prev_start = 0
+     for start, count in normal:
+         truelen = start - prev_start
+         falselen = count
+         prev_start = start + count
+ 
+         assert truelen < 0x8000 and falselen < 0x8000
+         entry = []
+         if truelen > 0x7f:
+             entry.append(0x80 | (truelen >> 8))
+             entry.append(truelen & 0xff)
+         else:
+             entry.append(truelen & 0x7f)
+         if falselen > 0x7f:
+             entry.append(0x80 | (falselen >> 8))
+             entry.append(falselen & 0xff)
+         else:
+             entry.append(falselen & 0x7f)
+ 
+         compressed.append(entry)
+ 
+     return compressed
+ 
+ def print_singletons(uppers, lowers, uppersname, lowersname):
+     print("#[rustfmt::skip]")
+     print("const {}: &[(u8, u8)] = &[".format(uppersname))
+     for u, c in uppers:
+         print("    ({:#04x}, {}),".format(u, c))
+     print("];")
+     print("#[rustfmt::skip]")
+     print("const {}: &[u8] = &[".format(lowersname))
+     for i in range(0, len(lowers), 8):
+         print("    {}".format(" ".join("{:#04x},".format(l) for l in lowers[i:i+8])))
+     print("];")
+ 
+ def print_normal(normal, normalname):
+     print("#[rustfmt::skip]")
+     print("const {}: &[u8] = &[".format(normalname))
+     for v in normal:
+         print("    {}".format(" ".join("{:#04x},".format(i) for i in v)))
+     print("];")
+ 
+ def main():
+     file = get_file("http://www.unicode.org/Public/UNIDATA/UnicodeData.txt")
+ 
+     codepoints = get_codepoints(file)
+ 
+     CUTOFF=0x10000
+     singletons0 = []
+     singletons1 = []
+     normal0 = []
+     normal1 = []
+     extra = []
+ 
+     for a, b in to_ranges(get_escaped(codepoints)):
+         if a > 2 * CUTOFF:
+             extra.append((a, b - a))
+         elif a == b - 1:
+             if a & CUTOFF:
+                 singletons1.append(a & ~CUTOFF)
+             else:
+                 singletons0.append(a)
+         elif a == b - 2:
+             if a & CUTOFF:
+                 singletons1.append(a & ~CUTOFF)
+                 singletons1.append((a + 1) & ~CUTOFF)
+             else:
+                 singletons0.append(a)
+                 singletons0.append(a + 1)
+         else:
+             if a >= 2 * CUTOFF:
+                 extra.append((a, b - a))
+             elif a & CUTOFF:
+                 normal1.append((a & ~CUTOFF, b - a))
+             else:
+                 normal0.append((a, b - a))
+ 
+     singletons0u, singletons0l = compress_singletons(singletons0)
+     singletons1u, singletons1l = compress_singletons(singletons1)
+     normal0 = compress_normal(normal0)
+     normal1 = compress_normal(normal1)
+ 
+     print("""\
+ // NOTE: The following code was generated by "src/libcore/unicode/printable.py",
+ //       do not edit directly!
+ 
+ fn check(x: u16, singletonuppers: &[(u8, u8)], singletonlowers: &[u8], normal: &[u8]) -> bool {
+     let xupper = (x >> 8) as u8;
+     let mut lowerstart = 0;
+     for &(upper, lowercount) in singletonuppers {
+         let lowerend = lowerstart + lowercount as usize;
+         if xupper == upper {
+             for &lower in &singletonlowers[lowerstart..lowerend] {
+                 if lower == x as u8 {
+                     return false;
+                 }
+             }
+         } else if xupper < upper {
+             break;
+         }
+         lowerstart = lowerend;
+     }
+ 
+     let mut x = x as i32;
+     let mut normal = normal.iter().cloned();
+     let mut current = true;
+     while let Some(v) = normal.next() {
+         let len = if v & 0x80 != 0 {
+             ((v & 0x7f) as i32) << 8 | normal.next().unwrap() as i32
+         } else {
+             v as i32
+         };
+         x -= len;
+         if x < 0 {
+             break;
+         }
+         current = !current;
+     }
+     current
+ }
+ 
+ pub(crate) fn is_printable(x: char) -> bool {
+     let x = x as u32;
+     let lower = x as u16;
+     if x < 0x10000 {
+         check(lower, SINGLETONS0U, SINGLETONS0L, NORMAL0)
+     } else if x < 0x20000 {
+         check(lower, SINGLETONS1U, SINGLETONS1L, NORMAL1)
+     } else {\
+ """)
+     for a, b in extra:
+         print("        if 0x{:x} <= x && x < 0x{:x} {{".format(a, a + b))
+         print("            return false;")
+         print("        }")
+     print("""\
+         true
+     }
+ }\
+ """)
+     print()
+     print_singletons(singletons0u, singletons0l, 'SINGLETONS0U', 'SINGLETONS0L')
+     print_singletons(singletons1u, singletons1l, 'SINGLETONS1U', 'SINGLETONS1L')
+     print_normal(normal0, 'NORMAL0')
+     print_normal(normal1, 'NORMAL1')
+ 
+ if __name__ == '__main__':
+     main()
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/printable.rs gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/printable.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/printable.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/printable.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,555 ----
+ // NOTE: The following code was generated by "src/libcore/unicode/printable.py",
+ //       do not edit directly!
+ 
+ fn check(x: u16, singletonuppers: &[(u8, u8)], singletonlowers: &[u8], normal: &[u8]) -> bool {
+     let xupper = (x >> 8) as u8;
+     let mut lowerstart = 0;
+     for &(upper, lowercount) in singletonuppers {
+         let lowerend = lowerstart + lowercount as usize;
+         if xupper == upper {
+             for &lower in &singletonlowers[lowerstart..lowerend] {
+                 if lower == x as u8 {
+                     return false;
+                 }
+             }
+         } else if xupper < upper {
+             break;
+         }
+         lowerstart = lowerend;
+     }
+ 
+     let mut x = x as i32;
+     let mut normal = normal.iter().cloned();
+     let mut current = true;
+     while let Some(v) = normal.next() {
+         let len = if v & 0x80 != 0 {
+             ((v & 0x7f) as i32) << 8 | normal.next().unwrap() as i32
+         } else {
+             v as i32
+         };
+         x -= len;
+         if x < 0 {
+             break;
+         }
+         current = !current;
+     }
+     current
+ }
+ 
+ pub(crate) fn is_printable(x: char) -> bool {
+     let x = x as u32;
+     let lower = x as u16;
+     if x < 0x10000 {
+         check(lower, SINGLETONS0U, SINGLETONS0L, NORMAL0)
+     } else if x < 0x20000 {
+         check(lower, SINGLETONS1U, SINGLETONS1L, NORMAL1)
+     } else {
+         if 0x2a6de <= x && x < 0x2a700 {
+             return false;
+         }
+         if 0x2b735 <= x && x < 0x2b740 {
+             return false;
+         }
+         if 0x2b81e <= x && x < 0x2b820 {
+             return false;
+         }
+         if 0x2cea2 <= x && x < 0x2ceb0 {
+             return false;
+         }
+         if 0x2ebe1 <= x && x < 0x2f800 {
+             return false;
+         }
+         if 0x2fa1e <= x && x < 0x30000 {
+             return false;
+         }
+         if 0x3134b <= x && x < 0xe0100 {
+             return false;
+         }
+         if 0xe01f0 <= x && x < 0x110000 {
+             return false;
+         }
+         true
+     }
+ }
+ 
+ #[rustfmt::skip]
+ const SINGLETONS0U: &[(u8, u8)] = &[
+     (0x00, 1),
+     (0x03, 5),
+     (0x05, 6),
+     (0x06, 3),
+     (0x07, 6),
+     (0x08, 8),
+     (0x09, 17),
+     (0x0a, 28),
+     (0x0b, 25),
+     (0x0c, 20),
+     (0x0d, 16),
+     (0x0e, 13),
+     (0x0f, 4),
+     (0x10, 3),
+     (0x12, 18),
+     (0x13, 9),
+     (0x16, 1),
+     (0x17, 5),
+     (0x18, 2),
+     (0x19, 3),
+     (0x1a, 7),
+     (0x1c, 2),
+     (0x1d, 1),
+     (0x1f, 22),
+     (0x20, 3),
+     (0x2b, 3),
+     (0x2c, 2),
+     (0x2d, 11),
+     (0x2e, 1),
+     (0x30, 3),
+     (0x31, 2),
+     (0x32, 1),
+     (0xa7, 2),
+     (0xa9, 2),
+     (0xaa, 4),
+     (0xab, 8),
+     (0xfa, 2),
+     (0xfb, 5),
+     (0xfd, 4),
+     (0xfe, 3),
+     (0xff, 9),
+ ];
+ #[rustfmt::skip]
+ const SINGLETONS0L: &[u8] = &[
+     0xad, 0x78, 0x79, 0x8b, 0x8d, 0xa2, 0x30, 0x57,
+     0x58, 0x8b, 0x8c, 0x90, 0x1c, 0x1d, 0xdd, 0x0e,
+     0x0f, 0x4b, 0x4c, 0xfb, 0xfc, 0x2e, 0x2f, 0x3f,
+     0x5c, 0x5d, 0x5f, 0xb5, 0xe2, 0x84, 0x8d, 0x8e,
+     0x91, 0x92, 0xa9, 0xb1, 0xba, 0xbb, 0xc5, 0xc6,
+     0xc9, 0xca, 0xde, 0xe4, 0xe5, 0xff, 0x00, 0x04,
+     0x11, 0x12, 0x29, 0x31, 0x34, 0x37, 0x3a, 0x3b,
+     0x3d, 0x49, 0x4a, 0x5d, 0x84, 0x8e, 0x92, 0xa9,
+     0xb1, 0xb4, 0xba, 0xbb, 0xc6, 0xca, 0xce, 0xcf,
+     0xe4, 0xe5, 0x00, 0x04, 0x0d, 0x0e, 0x11, 0x12,
+     0x29, 0x31, 0x34, 0x3a, 0x3b, 0x45, 0x46, 0x49,
+     0x4a, 0x5e, 0x64, 0x65, 0x84, 0x91, 0x9b, 0x9d,
+     0xc9, 0xce, 0xcf, 0x0d, 0x11, 0x29, 0x45, 0x49,
+     0x57, 0x64, 0x65, 0x8d, 0x91, 0xa9, 0xb4, 0xba,
+     0xbb, 0xc5, 0xc9, 0xdf, 0xe4, 0xe5, 0xf0, 0x0d,
+     0x11, 0x45, 0x49, 0x64, 0x65, 0x80, 0x84, 0xb2,
+     0xbc, 0xbe, 0xbf, 0xd5, 0xd7, 0xf0, 0xf1, 0x83,
+     0x85, 0x8b, 0xa4, 0xa6, 0xbe, 0xbf, 0xc5, 0xc7,
+     0xce, 0xcf, 0xda, 0xdb, 0x48, 0x98, 0xbd, 0xcd,
+     0xc6, 0xce, 0xcf, 0x49, 0x4e, 0x4f, 0x57, 0x59,
+     0x5e, 0x5f, 0x89, 0x8e, 0x8f, 0xb1, 0xb6, 0xb7,
+     0xbf, 0xc1, 0xc6, 0xc7, 0xd7, 0x11, 0x16, 0x17,
+     0x5b, 0x5c, 0xf6, 0xf7, 0xfe, 0xff, 0x80, 0x0d,
+     0x6d, 0x71, 0xde, 0xdf, 0x0e, 0x0f, 0x1f, 0x6e,
+     0x6f, 0x1c, 0x1d, 0x5f, 0x7d, 0x7e, 0xae, 0xaf,
+     0xbb, 0xbc, 0xfa, 0x16, 0x17, 0x1e, 0x1f, 0x46,
+     0x47, 0x4e, 0x4f, 0x58, 0x5a, 0x5c, 0x5e, 0x7e,
+     0x7f, 0xb5, 0xc5, 0xd4, 0xd5, 0xdc, 0xf0, 0xf1,
+     0xf5, 0x72, 0x73, 0x8f, 0x74, 0x75, 0x96, 0x2f,
+     0x5f, 0x26, 0x2e, 0x2f, 0xa7, 0xaf, 0xb7, 0xbf,
+     0xc7, 0xcf, 0xd7, 0xdf, 0x9a, 0x40, 0x97, 0x98,
+     0x30, 0x8f, 0x1f, 0xc0, 0xc1, 0xce, 0xff, 0x4e,
+     0x4f, 0x5a, 0x5b, 0x07, 0x08, 0x0f, 0x10, 0x27,
+     0x2f, 0xee, 0xef, 0x6e, 0x6f, 0x37, 0x3d, 0x3f,
+     0x42, 0x45, 0x90, 0x91, 0xfe, 0xff, 0x53, 0x67,
+     0x75, 0xc8, 0xc9, 0xd0, 0xd1, 0xd8, 0xd9, 0xe7,
+     0xfe, 0xff,
+ ];
+ #[rustfmt::skip]
+ const SINGLETONS1U: &[(u8, u8)] = &[
+     (0x00, 6),
+     (0x01, 1),
+     (0x03, 1),
+     (0x04, 2),
+     (0x08, 8),
+     (0x09, 2),
+     (0x0a, 5),
+     (0x0b, 2),
+     (0x0e, 4),
+     (0x10, 1),
+     (0x11, 2),
+     (0x12, 5),
+     (0x13, 17),
+     (0x14, 1),
+     (0x15, 2),
+     (0x17, 2),
+     (0x19, 13),
+     (0x1c, 5),
+     (0x1d, 8),
+     (0x24, 1),
+     (0x6a, 3),
+     (0x6b, 2),
+     (0xbc, 2),
+     (0xd1, 2),
+     (0xd4, 12),
+     (0xd5, 9),
+     (0xd6, 2),
+     (0xd7, 2),
+     (0xda, 1),
+     (0xe0, 5),
+     (0xe1, 2),
+     (0xe8, 2),
+     (0xee, 32),
+     (0xf0, 4),
+     (0xf8, 2),
+     (0xf9, 2),
+     (0xfa, 2),
+     (0xfb, 1),
+ ];
+ #[rustfmt::skip]
+ const SINGLETONS1L: &[u8] = &[
+     0x0c, 0x27, 0x3b, 0x3e, 0x4e, 0x4f, 0x8f, 0x9e,
+     0x9e, 0x9f, 0x06, 0x07, 0x09, 0x36, 0x3d, 0x3e,
+     0x56, 0xf3, 0xd0, 0xd1, 0x04, 0x14, 0x18, 0x36,
+     0x37, 0x56, 0x57, 0x7f, 0xaa, 0xae, 0xaf, 0xbd,
+     0x35, 0xe0, 0x12, 0x87, 0x89, 0x8e, 0x9e, 0x04,
+     0x0d, 0x0e, 0x11, 0x12, 0x29, 0x31, 0x34, 0x3a,
+     0x45, 0x46, 0x49, 0x4a, 0x4e, 0x4f, 0x64, 0x65,
+     0x5c, 0xb6, 0xb7, 0x1b, 0x1c, 0x07, 0x08, 0x0a,
+     0x0b, 0x14, 0x17, 0x36, 0x39, 0x3a, 0xa8, 0xa9,
+     0xd8, 0xd9, 0x09, 0x37, 0x90, 0x91, 0xa8, 0x07,
+     0x0a, 0x3b, 0x3e, 0x66, 0x69, 0x8f, 0x92, 0x6f,
+     0x5f, 0xee, 0xef, 0x5a, 0x62, 0x9a, 0x9b, 0x27,
+     0x28, 0x55, 0x9d, 0xa0, 0xa1, 0xa3, 0xa4, 0xa7,
+     0xa8, 0xad, 0xba, 0xbc, 0xc4, 0x06, 0x0b, 0x0c,
+     0x15, 0x1d, 0x3a, 0x3f, 0x45, 0x51, 0xa6, 0xa7,
+     0xcc, 0xcd, 0xa0, 0x07, 0x19, 0x1a, 0x22, 0x25,
+     0x3e, 0x3f, 0xc5, 0xc6, 0x04, 0x20, 0x23, 0x25,
+     0x26, 0x28, 0x33, 0x38, 0x3a, 0x48, 0x4a, 0x4c,
+     0x50, 0x53, 0x55, 0x56, 0x58, 0x5a, 0x5c, 0x5e,
+     0x60, 0x63, 0x65, 0x66, 0x6b, 0x73, 0x78, 0x7d,
+     0x7f, 0x8a, 0xa4, 0xaa, 0xaf, 0xb0, 0xc0, 0xd0,
+     0xae, 0xaf, 0x79, 0xcc, 0x6e, 0x6f, 0x93,
+ ];
+ #[rustfmt::skip]
+ const NORMAL0: &[u8] = &[
+     0x00, 0x20,
+     0x5f, 0x22,
+     0x82, 0xdf, 0x04,
+     0x82, 0x44, 0x08,
+     0x1b, 0x04,
+     0x06, 0x11,
+     0x81, 0xac, 0x0e,
+     0x80, 0xab, 0x35,
+     0x28, 0x0b,
+     0x80, 0xe0, 0x03,
+     0x19, 0x08,
+     0x01, 0x04,
+     0x2f, 0x04,
+     0x34, 0x04,
+     0x07, 0x03,
+     0x01, 0x07,
+     0x06, 0x07,
+     0x11, 0x0a,
+     0x50, 0x0f,
+     0x12, 0x07,
+     0x55, 0x07,
+     0x03, 0x04,
+     0x1c, 0x0a,
+     0x09, 0x03,
+     0x08, 0x03,
+     0x07, 0x03,
+     0x02, 0x03,
+     0x03, 0x03,
+     0x0c, 0x04,
+     0x05, 0x03,
+     0x0b, 0x06,
+     0x01, 0x0e,
+     0x15, 0x05,
+     0x3a, 0x03,
+     0x11, 0x07,
+     0x06, 0x05,
+     0x10, 0x07,
+     0x57, 0x07,
+     0x02, 0x07,
+     0x15, 0x0d,
+     0x50, 0x04,
+     0x43, 0x03,
+     0x2d, 0x03,
+     0x01, 0x04,
+     0x11, 0x06,
+     0x0f, 0x0c,
+     0x3a, 0x04,
+     0x1d, 0x25,
+     0x5f, 0x20,
+     0x6d, 0x04,
+     0x6a, 0x25,
+     0x80, 0xc8, 0x05,
+     0x82, 0xb0, 0x03,
+     0x1a, 0x06,
+     0x82, 0xfd, 0x03,
+     0x59, 0x07,
+     0x15, 0x0b,
+     0x17, 0x09,
+     0x14, 0x0c,
+     0x14, 0x0c,
+     0x6a, 0x06,
+     0x0a, 0x06,
+     0x1a, 0x06,
+     0x59, 0x07,
+     0x2b, 0x05,
+     0x46, 0x0a,
+     0x2c, 0x04,
+     0x0c, 0x04,
+     0x01, 0x03,
+     0x31, 0x0b,
+     0x2c, 0x04,
+     0x1a, 0x06,
+     0x0b, 0x03,
+     0x80, 0xac, 0x06,
+     0x0a, 0x06,
+     0x21, 0x3f,
+     0x4c, 0x04,
+     0x2d, 0x03,
+     0x74, 0x08,
+     0x3c, 0x03,
+     0x0f, 0x03,
+     0x3c, 0x07,
+     0x38, 0x08,
+     0x2b, 0x05,
+     0x82, 0xff, 0x11,
+     0x18, 0x08,
+     0x2f, 0x11,
+     0x2d, 0x03,
+     0x20, 0x10,
+     0x21, 0x0f,
+     0x80, 0x8c, 0x04,
+     0x82, 0x97, 0x19,
+     0x0b, 0x15,
+     0x88, 0x94, 0x05,
+     0x2f, 0x05,
+     0x3b, 0x07,
+     0x02, 0x0e,
+     0x18, 0x09,
+     0x80, 0xb3, 0x2d,
+     0x74, 0x0c,
+     0x80, 0xd6, 0x1a,
+     0x0c, 0x05,
+     0x80, 0xff, 0x05,
+     0x80, 0xdf, 0x0c,
+     0xee, 0x0d, 0x03,
+     0x84, 0x8d, 0x03,
+     0x37, 0x09,
+     0x81, 0x5c, 0x14,
+     0x80, 0xb8, 0x08,
+     0x80, 0xcb, 0x2a,
+     0x38, 0x03,
+     0x0a, 0x06,
+     0x38, 0x08,
+     0x46, 0x08,
+     0x0c, 0x06,
+     0x74, 0x0b,
+     0x1e, 0x03,
+     0x5a, 0x04,
+     0x59, 0x09,
+     0x80, 0x83, 0x18,
+     0x1c, 0x0a,
+     0x16, 0x09,
+     0x4c, 0x04,
+     0x80, 0x8a, 0x06,
+     0xab, 0xa4, 0x0c,
+     0x17, 0x04,
+     0x31, 0xa1, 0x04,
+     0x81, 0xda, 0x26,
+     0x07, 0x0c,
+     0x05, 0x05,
+     0x80, 0xa5, 0x11,
+     0x81, 0x6d, 0x10,
+     0x78, 0x28,
+     0x2a, 0x06,
+     0x4c, 0x04,
+     0x80, 0x8d, 0x04,
+     0x80, 0xbe, 0x03,
+     0x1b, 0x03,
+     0x0f, 0x0d,
+ ];
+ #[rustfmt::skip]
+ const NORMAL1: &[u8] = &[
+     0x5e, 0x22,
+     0x7b, 0x05,
+     0x03, 0x04,
+     0x2d, 0x03,
+     0x66, 0x03,
+     0x01, 0x2f,
+     0x2e, 0x80, 0x82,
+     0x1d, 0x03,
+     0x31, 0x0f,
+     0x1c, 0x04,
+     0x24, 0x09,
+     0x1e, 0x05,
+     0x2b, 0x05,
+     0x44, 0x04,
+     0x0e, 0x2a,
+     0x80, 0xaa, 0x06,
+     0x24, 0x04,
+     0x24, 0x04,
+     0x28, 0x08,
+     0x34, 0x0b,
+     0x01, 0x80, 0x90,
+     0x81, 0x37, 0x09,
+     0x16, 0x0a,
+     0x08, 0x80, 0x98,
+     0x39, 0x03,
+     0x63, 0x08,
+     0x09, 0x30,
+     0x16, 0x05,
+     0x21, 0x03,
+     0x1b, 0x05,
+     0x01, 0x40,
+     0x38, 0x04,
+     0x4b, 0x05,
+     0x2f, 0x04,
+     0x0a, 0x07,
+     0x09, 0x07,
+     0x40, 0x20,
+     0x27, 0x04,
+     0x0c, 0x09,
+     0x36, 0x03,
+     0x3a, 0x05,
+     0x1a, 0x07,
+     0x04, 0x0c,
+     0x07, 0x50,
+     0x49, 0x37,
+     0x33, 0x0d,
+     0x33, 0x07,
+     0x2e, 0x08,
+     0x0a, 0x81, 0x26,
+     0x52, 0x4e,
+     0x28, 0x08,
+     0x2a, 0x56,
+     0x1c, 0x14,
+     0x17, 0x09,
+     0x4e, 0x04,
+     0x1e, 0x0f,
+     0x43, 0x0e,
+     0x19, 0x07,
+     0x0a, 0x06,
+     0x48, 0x08,
+     0x27, 0x09,
+     0x75, 0x0b,
+     0x3f, 0x41,
+     0x2a, 0x06,
+     0x3b, 0x05,
+     0x0a, 0x06,
+     0x51, 0x06,
+     0x01, 0x05,
+     0x10, 0x03,
+     0x05, 0x80, 0x8b,
+     0x62, 0x1e,
+     0x48, 0x08,
+     0x0a, 0x80, 0xa6,
+     0x5e, 0x22,
+     0x45, 0x0b,
+     0x0a, 0x06,
+     0x0d, 0x13,
+     0x39, 0x07,
+     0x0a, 0x36,
+     0x2c, 0x04,
+     0x10, 0x80, 0xc0,
+     0x3c, 0x64,
+     0x53, 0x0c,
+     0x48, 0x09,
+     0x0a, 0x46,
+     0x45, 0x1b,
+     0x48, 0x08,
+     0x53, 0x1d,
+     0x39, 0x81, 0x07,
+     0x46, 0x0a,
+     0x1d, 0x03,
+     0x47, 0x49,
+     0x37, 0x03,
+     0x0e, 0x08,
+     0x0a, 0x06,
+     0x39, 0x07,
+     0x0a, 0x81, 0x36,
+     0x19, 0x80, 0xb7,
+     0x01, 0x0f,
+     0x32, 0x0d,
+     0x83, 0x9b, 0x66,
+     0x75, 0x0b,
+     0x80, 0xc4, 0x8a, 0xbc,
+     0x84, 0x2f, 0x8f, 0xd1,
+     0x82, 0x47, 0xa1, 0xb9,
+     0x82, 0x39, 0x07,
+     0x2a, 0x04,
+     0x02, 0x60,
+     0x26, 0x0a,
+     0x46, 0x0a,
+     0x28, 0x05,
+     0x13, 0x82, 0xb0,
+     0x5b, 0x65,
+     0x4b, 0x04,
+     0x39, 0x07,
+     0x11, 0x40,
+     0x05, 0x0b,
+     0x02, 0x0e,
+     0x97, 0xf8, 0x08,
+     0x84, 0xd6, 0x2a,
+     0x09, 0xa2, 0xf7,
+     0x81, 0x1f, 0x31,
+     0x03, 0x11,
+     0x04, 0x08,
+     0x81, 0x8c, 0x89, 0x04,
+     0x6b, 0x05,
+     0x0d, 0x03,
+     0x09, 0x07,
+     0x10, 0x93, 0x60,
+     0x80, 0xf6, 0x0a,
+     0x73, 0x08,
+     0x6e, 0x17,
+     0x46, 0x80, 0x9a,
+     0x14, 0x0c,
+     0x57, 0x09,
+     0x19, 0x80, 0x87,
+     0x81, 0x47, 0x03,
+     0x85, 0x42, 0x0f,
+     0x15, 0x85, 0x50,
+     0x2b, 0x80, 0xd5,
+     0x2d, 0x03,
+     0x1a, 0x04,
+     0x02, 0x81, 0x70,
+     0x3a, 0x05,
+     0x01, 0x85, 0x00,
+     0x80, 0xd7, 0x29,
+     0x4c, 0x04,
+     0x0a, 0x04,
+     0x02, 0x83, 0x11,
+     0x44, 0x4c,
+     0x3d, 0x80, 0xc2,
+     0x3c, 0x06,
+     0x01, 0x04,
+     0x55, 0x05,
+     0x1b, 0x34,
+     0x02, 0x81, 0x0e,
+     0x2c, 0x04,
+     0x64, 0x0c,
+     0x56, 0x0a,
+     0x80, 0xae, 0x38,
+     0x1d, 0x0d,
+     0x2c, 0x04,
+     0x09, 0x07,
+     0x02, 0x0e,
+     0x06, 0x80, 0x9a,
+     0x83, 0xd8, 0x08,
+     0x0d, 0x03,
+     0x0d, 0x03,
+     0x74, 0x0c,
+     0x59, 0x07,
+     0x0c, 0x14,
+     0x0c, 0x04,
+     0x38, 0x08,
+     0x0a, 0x06,
+     0x28, 0x08,
+     0x22, 0x4e,
+     0x81, 0x54, 0x0c,
+     0x15, 0x03,
+     0x03, 0x05,
+     0x07, 0x09,
+     0x19, 0x07,
+     0x07, 0x09,
+     0x03, 0x0d,
+     0x07, 0x29,
+     0x80, 0xcb, 0x25,
+     0x0a, 0x84, 0x06,
+ ];
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/unicode_data.rs gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/unicode_data.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/unicode/unicode_data.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/unicode/unicode_data.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2278 ----
+ ///! This file is generated by src/tools/unicode-table-generator; do not edit manually!
+ 
+ #[inline(always)]
+ fn bitset_search<
+     const N: usize,
+     const CHUNK_SIZE: usize,
+     const N1: usize,
+     const CANONICAL: usize,
+     const CANONICALIZED: usize,
+ >(
+     needle: u32,
+     chunk_idx_map: &[u8; N],
+     bitset_chunk_idx: &[[u8; CHUNK_SIZE]; N1],
+     bitset_canonical: &[u64; CANONICAL],
+     bitset_canonicalized: &[(u8, u8); CANONICALIZED],
+ ) -> bool {
+     let bucket_idx = (needle / 64) as usize;
+     let chunk_map_idx = bucket_idx / CHUNK_SIZE;
+     let chunk_piece = bucket_idx % CHUNK_SIZE;
+     let chunk_idx = if let Some(&v) = chunk_idx_map.get(chunk_map_idx) {
+         v
+     } else {
+         return false;
+     };
+     let idx = bitset_chunk_idx[chunk_idx as usize][chunk_piece] as usize;
+     let word = if let Some(word) = bitset_canonical.get(idx) {
+         *word
+     } else {
+         let (real_idx, mapping) = bitset_canonicalized[idx - bitset_canonical.len()];
+         let mut word = bitset_canonical[real_idx as usize];
+         let should_invert = mapping & (1 << 6) != 0;
+         if should_invert {
+             word = !word;
+         }
+         // Lower 6 bits
+         let quantity = mapping & ((1 << 6) - 1);
+         if mapping & (1 << 7) != 0 {
+             // shift
+             word >>= quantity as u64;
+         } else {
+             word = word.rotate_left(quantity as u32);
+         }
+         word
+     };
+     (word & (1 << (needle % 64) as u64)) != 0
+ }
+ 
+ fn decode_prefix_sum(short_offset_run_header: u32) -> u32 {
+     short_offset_run_header & ((1 << 21) - 1)
+ }
+ 
+ fn decode_length(short_offset_run_header: u32) -> usize {
+     (short_offset_run_header >> 21) as usize
+ }
+ 
+ #[inline(always)]
+ fn skip_search<const SOR: usize, const OFFSETS: usize>(
+     needle: u32,
+     short_offset_runs: &[u32; SOR],
+     offsets: &[u8; OFFSETS],
+ ) -> bool {
+     // Note that this *cannot* be past the end of the array, as the last
+     // element is greater than std::char::MAX (the largest possible needle).
+     //
+     // So, we cannot have found it (i.e. Ok(idx) + 1 != length) and the correct
+     // location cannot be past it, so Err(idx) != length either.
+     //
+     // This means that we can avoid bounds checking for the accesses below, too.
+     let last_idx =
+         match short_offset_runs.binary_search_by_key(&(needle << 11), |header| header << 11) {
+             Ok(idx) => idx + 1,
+             Err(idx) => idx,
+         };
+ 
+     let mut offset_idx = decode_length(short_offset_runs[last_idx]);
+     let length = if let Some(next) = short_offset_runs.get(last_idx + 1) {
+         decode_length(*next) - offset_idx
+     } else {
+         offsets.len() - offset_idx
+     };
+     let prev =
+         last_idx.checked_sub(1).map(|prev| decode_prefix_sum(short_offset_runs[prev])).unwrap_or(0);
+ 
+     let total = needle - prev;
+     let mut prefix_sum = 0;
+     for _ in 0..(length - 1) {
+         let offset = offsets[offset_idx];
+         prefix_sum += offset as u32;
+         if prefix_sum > total {
+             break;
+         }
+         offset_idx += 1;
+     }
+     offset_idx % 2 == 1
+ }
+ 
+ pub const UNICODE_VERSION: (u8, u8, u8) = (13, 0, 0);
+ 
+ #[rustfmt::skip]
+ pub mod alphabetic {
+     static SHORT_OFFSET_RUNS: [u32; 52] = [
+         706, 33559113, 868226669, 947920662, 1157637302, 1306536960, 1310732293, 1398813696,
+         1449151936, 1451270141, 1455465613, 1459660301, 1468061604, 1648425216, 1658911342,
+         1661009214, 1707147904, 1793132343, 1853951616, 1994464256, 2330009312, 2418090906,
+         2428579840, 2439066671, 2441167872, 2443265607, 2445371392, 2447469113, 2449567296,
+         2476836856, 2508295382, 2512498688, 2518790431, 2520888060, 2533473280, 2535576576,
+         2556548774, 2634145792, 2682380992, 2715936768, 2720132608, 2736910640, 2875326464,
+         2887952094, 2890053429, 2894253730, 2902649825, 2906847232, 2908944926, 2911043584,
+         2913145675, 2916356939,
+     ];
+     static OFFSETS: [u8; 1391] = [
+         65, 26, 6, 26, 47, 1, 10, 1, 4, 1, 5, 23, 1, 31, 1, 0, 4, 12, 14, 5, 7, 1, 1, 1, 86, 1, 42,
+         5, 1, 2, 2, 4, 1, 1, 6, 1, 1, 3, 1, 1, 1, 20, 1, 83, 1, 139, 8, 166, 1, 38, 2, 1, 6, 41, 39,
+         14, 1, 1, 1, 2, 1, 2, 1, 1, 8, 27, 4, 4, 29, 11, 5, 56, 1, 7, 14, 102, 1, 8, 4, 8, 4, 3, 10,
+         3, 2, 1, 16, 48, 13, 101, 24, 33, 9, 2, 4, 1, 5, 24, 2, 19, 19, 25, 7, 11, 53, 21, 1, 18,
+         12, 12, 3, 7, 6, 76, 1, 16, 1, 3, 4, 15, 13, 19, 1, 8, 2, 2, 2, 22, 1, 7, 1, 1, 3, 4, 3, 8,
+         2, 2, 2, 2, 1, 1, 8, 1, 4, 2, 1, 5, 12, 2, 10, 1, 4, 3, 1, 6, 4, 2, 2, 22, 1, 7, 1, 2, 1, 2,
+         1, 2, 4, 5, 4, 2, 2, 2, 4, 1, 7, 4, 1, 1, 17, 6, 11, 3, 1, 9, 1, 3, 1, 22, 1, 7, 1, 2, 1, 5,
+         3, 9, 1, 3, 1, 2, 3, 1, 15, 4, 21, 4, 4, 3, 1, 8, 2, 2, 2, 22, 1, 7, 1, 2, 1, 5, 3, 8, 2, 2,
+         2, 2, 9, 2, 4, 2, 1, 5, 13, 1, 16, 2, 1, 6, 3, 3, 1, 4, 3, 2, 1, 1, 1, 2, 3, 2, 3, 3, 3, 12,
+         4, 5, 3, 3, 1, 3, 3, 1, 6, 1, 40, 4, 1, 8, 1, 3, 1, 23, 1, 16, 3, 8, 1, 3, 1, 3, 8, 2, 1, 3,
+         5, 4, 28, 4, 1, 8, 1, 3, 1, 23, 1, 10, 1, 5, 3, 8, 1, 3, 1, 3, 8, 2, 7, 1, 1, 4, 13, 2, 13,
+         13, 1, 3, 1, 41, 2, 8, 1, 3, 1, 3, 1, 1, 5, 4, 7, 5, 22, 6, 1, 3, 1, 18, 3, 24, 1, 9, 1, 1,
+         2, 7, 8, 6, 1, 1, 1, 8, 18, 2, 13, 58, 5, 7, 6, 1, 51, 2, 1, 1, 1, 5, 1, 24, 1, 1, 1, 19, 1,
+         3, 2, 5, 1, 1, 6, 1, 14, 4, 32, 1, 63, 8, 1, 36, 4, 17, 6, 16, 1, 36, 67, 55, 1, 1, 2, 5,
+         16, 64, 10, 4, 2, 38, 1, 1, 5, 1, 2, 43, 1, 0, 1, 4, 2, 7, 1, 1, 1, 4, 2, 41, 1, 4, 2, 33,
+         1, 4, 2, 7, 1, 1, 1, 4, 2, 15, 1, 57, 1, 4, 2, 67, 37, 16, 16, 86, 2, 6, 3, 0, 2, 17, 1, 26,
+         5, 75, 3, 11, 7, 13, 1, 6, 12, 20, 12, 20, 12, 13, 1, 3, 1, 2, 12, 52, 2, 19, 14, 1, 4, 1,
+         67, 89, 7, 43, 5, 70, 10, 31, 1, 12, 4, 9, 23, 30, 2, 5, 11, 44, 4, 26, 54, 28, 4, 63, 2,
+         20, 50, 1, 23, 2, 63, 52, 1, 15, 1, 7, 52, 42, 2, 4, 10, 44, 1, 11, 14, 55, 22, 3, 10, 36,
+         2, 9, 7, 43, 2, 3, 41, 4, 1, 6, 1, 2, 3, 1, 5, 192, 39, 14, 11, 0, 2, 6, 2, 38, 2, 6, 2, 8,
+         1, 1, 1, 1, 1, 1, 1, 31, 2, 53, 1, 7, 1, 1, 3, 3, 1, 7, 3, 4, 2, 6, 4, 13, 5, 3, 1, 7, 116,
+         1, 13, 1, 16, 13, 101, 1, 4, 1, 2, 10, 1, 1, 3, 5, 6, 1, 1, 1, 1, 1, 1, 4, 1, 11, 2, 4, 5,
+         5, 4, 1, 17, 41, 0, 52, 0, 47, 1, 47, 1, 133, 6, 4, 3, 2, 12, 38, 1, 1, 5, 1, 2, 56, 7, 1,
+         16, 23, 9, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 7, 1, 32, 47, 1, 0, 3, 25, 9, 7, 5, 2,
+         5, 4, 86, 6, 3, 1, 90, 1, 4, 5, 43, 1, 94, 17, 32, 48, 16, 0, 0, 64, 0, 3, 0, 67, 46, 2, 0,
+         3, 16, 10, 2, 20, 47, 5, 8, 3, 113, 39, 9, 2, 103, 2, 53, 2, 9, 42, 17, 1, 33, 24, 52, 12,
+         68, 1, 1, 44, 6, 3, 1, 1, 3, 10, 33, 5, 35, 13, 29, 3, 51, 1, 12, 15, 1, 16, 16, 10, 5, 1,
+         55, 9, 14, 18, 23, 3, 69, 1, 1, 1, 1, 24, 3, 2, 16, 2, 4, 11, 6, 2, 6, 2, 6, 9, 7, 1, 7, 1,
+         43, 1, 14, 6, 123, 21, 0, 12, 23, 4, 49, 0, 0, 2, 106, 38, 7, 12, 5, 5, 12, 1, 13, 1, 5, 1,
+         1, 1, 2, 1, 2, 1, 108, 33, 0, 18, 64, 2, 54, 40, 12, 116, 5, 1, 135, 36, 26, 6, 26, 11, 89,
+         3, 6, 2, 6, 2, 6, 2, 3, 35, 12, 1, 26, 1, 19, 1, 2, 1, 15, 2, 14, 34, 123, 69, 53, 0, 29, 3,
+         49, 47, 32, 13, 30, 5, 43, 5, 30, 2, 36, 4, 8, 1, 5, 42, 158, 18, 36, 4, 36, 4, 40, 8, 52,
+         156, 0, 9, 22, 10, 8, 152, 6, 2, 1, 1, 44, 1, 2, 3, 1, 2, 23, 10, 23, 9, 31, 65, 19, 1, 2,
+         10, 22, 10, 26, 70, 56, 6, 2, 64, 4, 1, 2, 5, 8, 1, 3, 1, 29, 42, 29, 3, 29, 35, 8, 1, 28,
+         27, 54, 10, 22, 10, 19, 13, 18, 110, 73, 55, 51, 13, 51, 13, 40, 0, 42, 1, 2, 3, 2, 78, 29,
+         10, 1, 8, 22, 106, 21, 27, 23, 9, 70, 60, 55, 23, 25, 23, 51, 17, 4, 8, 35, 3, 1, 9, 64, 1,
+         4, 9, 2, 10, 1, 1, 1, 35, 18, 1, 34, 2, 1, 6, 1, 65, 7, 1, 1, 1, 4, 1, 15, 1, 10, 7, 57, 23,
+         4, 1, 8, 2, 2, 2, 22, 1, 7, 1, 2, 1, 5, 3, 8, 2, 2, 2, 2, 3, 1, 6, 1, 5, 7, 156, 66, 1, 3,
+         1, 4, 20, 3, 30, 66, 2, 2, 1, 1, 184, 54, 2, 7, 25, 6, 34, 63, 1, 1, 3, 1, 59, 54, 2, 1, 71,
+         27, 2, 14, 213, 57, 103, 64, 31, 8, 2, 1, 2, 8, 1, 2, 1, 30, 1, 2, 2, 2, 2, 4, 93, 8, 2, 46,
+         2, 6, 1, 1, 1, 2, 27, 51, 2, 10, 17, 72, 5, 1, 34, 57, 0, 9, 1, 45, 1, 7, 1, 1, 49, 30, 2,
+         22, 1, 14, 73, 7, 1, 2, 1, 44, 3, 1, 1, 2, 1, 3, 1, 1, 2, 2, 24, 6, 1, 2, 1, 37, 1, 2, 1, 4,
+         1, 1, 0, 23, 185, 1, 79, 0, 102, 111, 17, 196, 0, 0, 0, 0, 0, 0, 7, 31, 113, 30, 18, 48, 16,
+         4, 31, 21, 5, 19, 0, 64, 128, 75, 4, 57, 7, 17, 64, 2, 1, 1, 12, 2, 14, 0, 8, 0, 42, 9, 0,
+         0, 49, 3, 17, 4, 8, 0, 0, 107, 5, 13, 3, 9, 7, 10, 4, 1, 0, 85, 1, 71, 1, 2, 2, 1, 2, 2, 2,
+         4, 1, 12, 1, 1, 1, 7, 1, 65, 1, 4, 2, 8, 1, 7, 1, 28, 1, 4, 1, 5, 1, 1, 3, 7, 1, 0, 2, 25,
+         1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 8, 0, 7, 1, 17, 2, 7, 1,
+         2, 1, 5, 213, 45, 10, 7, 16, 1, 0, 44, 0, 197, 59, 68, 3, 1, 3, 1, 0, 4, 1, 27, 1, 2, 1, 1,
+         2, 1, 1, 10, 1, 4, 1, 1, 1, 1, 6, 1, 4, 1, 1, 1, 1, 1, 1, 3, 1, 2, 1, 1, 2, 1, 1, 1, 1, 1,
+         1, 1, 1, 1, 1, 2, 1, 1, 2, 4, 1, 7, 1, 4, 1, 4, 1, 1, 1, 10, 1, 17, 5, 3, 1, 5, 1, 17, 0,
+         26, 6, 26, 6, 26, 0, 0, 34, 0, 11, 222, 2, 0, 14, 0, 0, 0, 0, 0, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod case_ignorable {
+     static SHORT_OFFSET_RUNS: [u32; 32] = [
+         688, 44045149, 555751186, 559947709, 794831996, 866136069, 891330581, 916497656, 920692236,
+         924908318, 1122041344, 1130430973, 1193347585, 1205931300, 1231097515, 1235294255,
+         1445009723, 1453399088, 1512120051, 1575040048, 1579248368, 1583443791, 1596046493,
+         1612829031, 1621219840, 1642192896, 1667359024, 1688330988, 1692526800, 1696723963,
+         1705902081, 1711210992,
+     ];
+     static OFFSETS: [u8; 821] = [
+         39, 1, 6, 1, 11, 1, 35, 1, 1, 1, 71, 1, 4, 1, 1, 1, 4, 1, 2, 2, 0, 192, 4, 2, 4, 1, 9, 2,
+         1, 1, 251, 7, 207, 1, 5, 1, 49, 45, 1, 1, 1, 2, 1, 2, 1, 1, 44, 1, 11, 6, 10, 11, 1, 1, 35,
+         1, 10, 21, 16, 1, 101, 8, 1, 10, 1, 4, 33, 1, 1, 1, 30, 27, 91, 11, 58, 11, 4, 1, 2, 1, 24,
+         24, 43, 3, 119, 48, 55, 1, 1, 1, 4, 8, 4, 1, 3, 7, 10, 2, 13, 1, 15, 1, 58, 1, 4, 4, 8, 1,
+         20, 2, 26, 1, 2, 2, 57, 1, 4, 2, 4, 2, 2, 3, 3, 1, 30, 2, 3, 1, 11, 2, 57, 1, 4, 5, 1, 2, 4,
+         1, 20, 2, 22, 6, 1, 1, 58, 1, 2, 1, 1, 4, 8, 1, 7, 2, 11, 2, 30, 1, 61, 1, 12, 1, 50, 1, 3,
+         1, 57, 3, 5, 3, 1, 4, 7, 2, 11, 2, 29, 1, 58, 1, 2, 1, 6, 1, 5, 2, 20, 2, 28, 2, 57, 2, 4,
+         4, 8, 1, 20, 2, 29, 1, 72, 1, 7, 3, 1, 1, 90, 1, 2, 7, 11, 9, 98, 1, 2, 9, 9, 1, 1, 6, 74,
+         2, 27, 1, 1, 1, 1, 1, 55, 14, 1, 5, 1, 2, 5, 11, 1, 36, 9, 1, 102, 4, 1, 6, 1, 2, 2, 2, 25,
+         2, 4, 3, 16, 4, 13, 1, 2, 2, 6, 1, 15, 1, 94, 1, 0, 3, 0, 3, 29, 3, 29, 2, 30, 2, 64, 2, 1,
+         7, 8, 1, 2, 11, 3, 1, 5, 1, 45, 4, 52, 1, 65, 2, 34, 1, 118, 3, 4, 2, 9, 1, 6, 3, 219, 2, 2,
+         1, 58, 1, 1, 7, 1, 1, 1, 1, 2, 8, 6, 10, 2, 1, 39, 1, 8, 17, 63, 4, 48, 1, 1, 5, 1, 1, 5, 1,
+         40, 9, 12, 2, 32, 4, 2, 2, 1, 3, 56, 1, 1, 2, 3, 1, 1, 3, 58, 8, 2, 2, 64, 6, 82, 3, 1, 13,
+         1, 7, 4, 1, 6, 1, 3, 2, 50, 63, 13, 1, 34, 95, 1, 5, 0, 1, 1, 3, 11, 3, 13, 3, 13, 3, 13, 2,
+         12, 5, 8, 2, 10, 1, 2, 1, 2, 5, 49, 5, 1, 10, 1, 1, 13, 1, 16, 13, 51, 33, 0, 2, 113, 3,
+         125, 1, 15, 1, 96, 32, 47, 1, 0, 1, 36, 4, 3, 5, 5, 1, 93, 6, 93, 3, 0, 1, 0, 6, 0, 1, 98,
+         4, 1, 10, 1, 1, 28, 4, 80, 2, 14, 34, 78, 1, 23, 3, 109, 2, 8, 1, 3, 1, 4, 1, 25, 2, 5, 1,
+         151, 2, 26, 18, 13, 1, 38, 8, 25, 11, 46, 3, 48, 1, 2, 4, 2, 2, 17, 1, 21, 2, 66, 6, 2, 2,
+         2, 2, 12, 1, 8, 1, 35, 1, 11, 1, 51, 1, 1, 3, 2, 2, 5, 2, 1, 1, 27, 1, 14, 2, 5, 2, 1, 1,
+         100, 5, 9, 3, 121, 1, 2, 1, 4, 1, 0, 1, 147, 16, 0, 16, 3, 1, 12, 16, 34, 1, 2, 1, 169, 1,
+         7, 1, 6, 1, 11, 1, 35, 1, 1, 1, 47, 1, 45, 2, 67, 1, 21, 3, 0, 1, 226, 1, 149, 5, 0, 3, 1,
+         2, 5, 4, 40, 3, 4, 1, 165, 2, 0, 4, 0, 2, 153, 11, 176, 1, 54, 15, 56, 3, 49, 4, 2, 2, 2, 1,
+         15, 1, 50, 3, 36, 5, 1, 8, 62, 1, 12, 2, 52, 9, 10, 4, 2, 1, 95, 3, 2, 1, 1, 2, 6, 1, 160,
+         1, 3, 8, 21, 2, 57, 2, 3, 1, 37, 7, 3, 5, 195, 8, 2, 3, 1, 1, 23, 1, 84, 6, 1, 1, 4, 2, 1,
+         2, 238, 4, 6, 2, 1, 2, 27, 2, 85, 8, 2, 1, 1, 2, 106, 1, 1, 1, 2, 6, 1, 1, 101, 3, 2, 4, 1,
+         5, 0, 9, 1, 2, 0, 2, 1, 1, 4, 1, 144, 4, 2, 2, 4, 1, 32, 10, 40, 6, 2, 4, 8, 1, 9, 6, 2, 3,
+         46, 13, 1, 2, 0, 7, 1, 6, 1, 1, 82, 22, 2, 7, 1, 2, 1, 2, 122, 6, 3, 1, 1, 2, 1, 7, 1, 1,
+         72, 2, 3, 1, 1, 1, 0, 2, 0, 9, 0, 5, 59, 7, 9, 4, 0, 1, 63, 17, 64, 2, 1, 2, 0, 2, 1, 4, 0,
+         3, 9, 16, 2, 7, 30, 4, 148, 3, 0, 55, 4, 50, 8, 1, 14, 1, 22, 5, 1, 15, 0, 7, 1, 17, 2, 7,
+         1, 2, 1, 5, 0, 14, 0, 4, 0, 7, 109, 8, 0, 5, 0, 1, 30, 96, 128, 240, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod cased {
+     static SHORT_OFFSET_RUNS: [u32; 19] = [
+         4256, 115348384, 136322176, 144711446, 163587254, 320875520, 325101120, 358656816,
+         392231680, 404815649, 413205504, 421596288, 434182304, 442592832, 446813184, 451008166,
+         528607488, 576844080, 582152586,
+     ];
+     static OFFSETS: [u8; 283] = [
+         65, 26, 6, 26, 47, 1, 10, 1, 4, 1, 5, 23, 1, 31, 1, 195, 1, 4, 4, 208, 1, 36, 7, 2, 30, 5,
+         96, 1, 42, 4, 2, 2, 2, 4, 1, 1, 6, 1, 1, 3, 1, 1, 1, 20, 1, 83, 1, 139, 8, 166, 1, 38, 9,
+         41, 0, 38, 1, 1, 5, 1, 2, 43, 2, 3, 0, 86, 2, 6, 0, 9, 7, 43, 2, 3, 64, 192, 64, 0, 2, 6, 2,
+         38, 2, 6, 2, 8, 1, 1, 1, 1, 1, 1, 1, 31, 2, 53, 1, 7, 1, 1, 3, 3, 1, 7, 3, 4, 2, 6, 4, 13,
+         5, 3, 1, 7, 116, 1, 13, 1, 16, 13, 101, 1, 4, 1, 2, 10, 1, 1, 3, 5, 6, 1, 1, 1, 1, 1, 1, 4,
+         1, 6, 4, 1, 2, 4, 5, 5, 4, 1, 17, 32, 3, 2, 0, 52, 0, 47, 1, 47, 1, 133, 6, 4, 3, 2, 12, 38,
+         1, 1, 5, 1, 0, 46, 18, 30, 132, 102, 3, 4, 1, 48, 2, 9, 42, 2, 1, 3, 0, 43, 1, 13, 7, 80, 0,
+         7, 12, 5, 0, 26, 6, 26, 0, 80, 96, 36, 4, 36, 0, 51, 13, 51, 0, 64, 0, 64, 0, 85, 1, 71, 1,
+         2, 2, 1, 2, 2, 2, 4, 1, 12, 1, 1, 1, 7, 1, 65, 1, 4, 2, 8, 1, 7, 1, 28, 1, 4, 1, 5, 1, 1, 3,
+         7, 1, 0, 2, 25, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 8, 0, 68,
+         0, 26, 6, 26, 6, 26, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod cc {
+     static SHORT_OFFSET_RUNS: [u32; 1] = [
+         1114272,
+     ];
+     static OFFSETS: [u8; 5] = [
+         0, 32, 95, 33, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod grapheme_extend {
+     static SHORT_OFFSET_RUNS: [u32; 31] = [
+         768, 2098307, 6292881, 10490717, 513808146, 518004748, 723528943, 731918378, 744531567,
+         752920578, 769719070, 899743232, 903937950, 912327165, 916523521, 929107236, 954273451,
+         958470191, 1180769328, 1252073203, 1315007216, 1319202639, 1327611037, 1340199269,
+         1344395776, 1373757440, 1398923568, 1419895532, 1424091344, 1429078048, 1438581232,
+     ];
+     static OFFSETS: [u8; 689] = [
+         0, 112, 0, 7, 0, 45, 1, 1, 1, 2, 1, 2, 1, 1, 72, 11, 48, 21, 16, 1, 101, 7, 2, 6, 2, 2, 1,
+         4, 35, 1, 30, 27, 91, 11, 58, 9, 9, 1, 24, 4, 1, 9, 1, 3, 1, 5, 43, 3, 119, 15, 1, 32, 55,
+         1, 1, 1, 4, 8, 4, 1, 3, 7, 10, 2, 29, 1, 58, 1, 1, 1, 2, 4, 8, 1, 9, 1, 10, 2, 26, 1, 2, 2,
+         57, 1, 4, 2, 4, 2, 2, 3, 3, 1, 30, 2, 3, 1, 11, 2, 57, 1, 4, 5, 1, 2, 4, 1, 20, 2, 22, 6, 1,
+         1, 58, 1, 1, 2, 1, 4, 8, 1, 7, 3, 10, 2, 30, 1, 59, 1, 1, 1, 12, 1, 9, 1, 40, 1, 3, 1, 57,
+         3, 5, 3, 1, 4, 7, 2, 11, 2, 29, 1, 58, 1, 2, 1, 2, 1, 3, 1, 5, 2, 7, 2, 11, 2, 28, 2, 57, 2,
+         1, 1, 2, 4, 8, 1, 9, 1, 10, 2, 29, 1, 72, 1, 4, 1, 2, 3, 1, 1, 8, 1, 81, 1, 2, 7, 12, 8, 98,
+         1, 2, 9, 11, 6, 74, 2, 27, 1, 1, 1, 1, 1, 55, 14, 1, 5, 1, 2, 5, 11, 1, 36, 9, 1, 102, 4, 1,
+         6, 1, 2, 2, 2, 25, 2, 4, 3, 16, 4, 13, 1, 2, 2, 6, 1, 15, 1, 0, 3, 0, 3, 29, 3, 29, 2, 30,
+         2, 64, 2, 1, 7, 8, 1, 2, 11, 9, 1, 45, 3, 119, 2, 34, 1, 118, 3, 4, 2, 9, 1, 6, 3, 219, 2,
+         2, 1, 58, 1, 1, 7, 1, 1, 1, 1, 2, 8, 6, 10, 2, 1, 48, 17, 63, 4, 48, 7, 1, 1, 5, 1, 40, 9,
+         12, 2, 32, 4, 2, 2, 1, 3, 56, 1, 1, 2, 3, 1, 1, 3, 58, 8, 2, 2, 152, 3, 1, 13, 1, 7, 4, 1,
+         6, 1, 3, 2, 198, 58, 1, 5, 0, 1, 195, 33, 0, 3, 141, 1, 96, 32, 0, 6, 105, 2, 0, 4, 1, 10,
+         32, 2, 80, 2, 0, 1, 3, 1, 4, 1, 25, 2, 5, 1, 151, 2, 26, 18, 13, 1, 38, 8, 25, 11, 46, 3,
+         48, 1, 2, 4, 2, 2, 39, 1, 67, 6, 2, 2, 2, 2, 12, 1, 8, 1, 47, 1, 51, 1, 1, 3, 2, 2, 5, 2, 1,
+         1, 42, 2, 8, 1, 238, 1, 2, 1, 4, 1, 0, 1, 0, 16, 16, 16, 0, 2, 0, 1, 226, 1, 149, 5, 0, 3,
+         1, 2, 5, 4, 40, 3, 4, 1, 165, 2, 0, 4, 0, 2, 153, 11, 176, 1, 54, 15, 56, 3, 49, 4, 2, 2,
+         69, 3, 36, 5, 1, 8, 62, 1, 12, 2, 52, 9, 10, 4, 2, 1, 95, 3, 2, 1, 1, 2, 6, 1, 160, 1, 3, 8,
+         21, 2, 57, 2, 1, 1, 1, 1, 22, 1, 14, 7, 3, 5, 195, 8, 2, 3, 1, 1, 23, 1, 81, 1, 2, 6, 1, 1,
+         2, 1, 1, 2, 1, 2, 235, 1, 2, 4, 6, 2, 1, 2, 27, 2, 85, 8, 2, 1, 1, 2, 106, 1, 1, 1, 2, 6, 1,
+         1, 101, 3, 2, 4, 1, 5, 0, 9, 1, 2, 245, 1, 10, 2, 1, 1, 4, 1, 144, 4, 2, 2, 4, 1, 32, 10,
+         40, 6, 2, 4, 8, 1, 9, 6, 2, 3, 46, 13, 1, 2, 0, 7, 1, 6, 1, 1, 82, 22, 2, 7, 1, 2, 1, 2,
+         122, 6, 3, 1, 1, 2, 1, 7, 1, 1, 72, 2, 3, 1, 1, 1, 0, 2, 0, 5, 59, 7, 0, 1, 63, 4, 81, 1, 0,
+         2, 0, 1, 1, 3, 4, 5, 8, 8, 2, 7, 30, 4, 148, 3, 0, 55, 4, 50, 8, 1, 14, 1, 22, 5, 1, 15, 0,
+         7, 1, 17, 2, 7, 1, 2, 1, 5, 0, 7, 0, 4, 0, 7, 109, 7, 0, 96, 128, 240, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod lowercase {
+     static BITSET_CHUNKS_MAP: [u8; 123] = [
+         13, 16, 0, 0, 8, 0, 0, 11, 12, 9, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 3, 1, 0, 14, 0, 7, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0,
+         0, 0, 6,
+     ];
+     static BITSET_INDEX_CHUNKS: [[u8; 16]; 18] = [
+         [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 56, 0, 0],
+         [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 14, 52, 0],
+         [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 0, 0, 0],
+         [0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0],
+         [0, 0, 0, 0, 0, 0, 0, 0, 0, 62, 39, 0, 47, 43, 45, 30],
+         [0, 0, 0, 0, 10, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 0, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26],
+         [0, 0, 0, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 0, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 54, 0, 52, 52, 52, 0, 21, 21, 64, 21, 33, 24, 23, 34],
+         [0, 5, 71, 0, 28, 15, 69, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 61, 31, 17, 22, 48, 49, 44, 42, 8, 32, 38, 0, 27, 13, 29],
+         [11, 55, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [16, 25, 21, 35, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [16, 46, 2, 20, 63, 9, 54, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [60, 37, 51, 12, 70, 58, 18, 1, 6, 59, 68, 19, 65, 66, 3, 41],
+     ];
+     static BITSET_CANONICAL: [u64; 52] = [
+         0b0000000000000000000000000000000000000000000000000000000000000000,
+         0b1111111111111111110000000000000000000000000011111111111111111111,
+         0b1010101010101010101010101010101010101010101010101010100000000010,
+         0b1111111111111111111111000000000000000000000000001111110111111111,
+         0b0000111111111111111111111111111111111111000000000000000000000000,
+         0b1000000000000010000000000000000000000000000000000000000000000000,
+         0b0000111111111111111111111111110000000000000000000000000011111111,
+         0b0000000000000111111111111111111111111111111111111111111111111111,
+         0b1111111111111111111111111111111111111111111111111010101010000101,
+         0b1111111111111111111111111111111100000000000000000000000000000000,
+         0b1111111111111111111111111111110000000000000000000000000000000000,
+         0b1111111111111111111111110000000000000000000000000000000000000000,
+         0b1111111111111111111111000000000000000000000000001111111111101111,
+         0b1111111111111111111100000000000000000000000000010000000000000000,
+         0b1111111111111111000000011111111111110111111111111111111111111111,
+         0b1111111111111111000000000000000000000000000000000100001111000000,
+         0b1111111111111111000000000000000000000000000000000000000000000000,
+         0b1111111101111111111111111111111110000000000000000000000000000000,
+         0b1111110000000000000000000000000011111111111111111111111111000000,
+         0b1111000000000000000000000000001111110111111111111111111111111100,
+         0b1010101010101010101010101010101010101010101010101101010101010100,
+         0b1010101010101010101010101010101010101010101010101010101010101010,
+         0b0101010110101010101010101010101010101010101010101010101010101010,
+         0b0100000011011111000000001111111100000000111111110000000011111111,
+         0b0011111111111111000000001111111100000000111111110000000000111111,
+         0b0011111111011010000101010110001001111111111111111111111111111111,
+         0b0011111100000000000000000000000000000000000000000000000000000000,
+         0b0011110010001010000000000000000000000000000000000000000000100000,
+         0b0011001000010000100000000000000000000000000010001100010000000000,
+         0b0001100100101111101010101010101010101010111000110111111111111111,
+         0b0000011101000000000000000000000000000000000000000000010100001000,
+         0b0000010000100000000001000000000000000000000000000000000000000000,
+         0b0000000111111111111111111111111111111111111011111111111111111111,
+         0b0000000011111111000000001111111100000000001111110000000011111111,
+         0b0000000011011100000000001111111100000000110011110000000011011100,
+         0b0000000000001000010100000001101010101010101010101010101010101010,
+         0b0000000000000000001000001011111111111111111111111111111111111111,
+         0b0000000000000000000000001111111111111111110111111100000000000000,
+         0b0000000000000000000000000001111100000000000000000000000000000011,
+         0b0000000000000000000000000000000000111010101010101010101010101010,
+         0b0000000000000000000000000000000000000000111110000000000001111111,
+         0b0000000000000000000000000000000000000000000000000000101111110111,
+         0b1001001111111010101010101010101010101010101010101010101010101010,
+         0b1001010111111111101010101010101010101010101010101010101010101010,
+         0b1010101000101001101010101010101010110101010101010101001001000000,
+         0b1010101010100000100000101010101010101010101110100101000010101010,
+         0b1010101010101010101010101010101011111111111111111111111111111111,
+         0b1010101010101011101010101010100000000000000000000000000000000000,
+         0b1101010010101010101010101010101010101010101010101010101101010101,
+         0b1110011001010001001011010010101001001110001001000011000100101001,
+         0b1110011111111111111111111111111111111111111111110000000000000000,
+         0b1110101111000000000000000000000000001111111111111111111111111100,
+     ];
+     static BITSET_MAPPING: [(u8, u8); 20] = [
+         (0, 64), (1, 188), (1, 183), (1, 176), (1, 109), (1, 124), (1, 126), (1, 66), (1, 70),
+         (1, 77), (2, 146), (2, 144), (2, 83), (3, 12), (3, 6), (4, 156), (4, 78), (5, 187),
+         (6, 132), (7, 93),
+     ];
+ 
+     pub fn lookup(c: char) -> bool {
+         super::bitset_search(
+             c as u32,
+             &BITSET_CHUNKS_MAP,
+             &BITSET_INDEX_CHUNKS,
+             &BITSET_CANONICAL,
+             &BITSET_MAPPING,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod n {
+     static SHORT_OFFSET_RUNS: [u32; 38] = [
+         1632, 18876774, 31461440, 102765417, 111154926, 115349830, 132128880, 165684320, 186656630,
+         195046653, 199241735, 203436434, 216049184, 241215536, 249605104, 274792208, 278987015,
+         283181793, 295766104, 320933114, 383848032, 392238160, 434181712, 442570976, 455154768,
+         463544256, 476128256, 480340576, 484535936, 497144544, 501340110, 509731136, 513925872,
+         518121671, 522316913, 530706688, 551681008, 556989434,
+     ];
+     static OFFSETS: [u8; 267] = [
+         48, 10, 120, 2, 5, 1, 2, 3, 0, 10, 134, 10, 198, 10, 0, 10, 118, 10, 4, 6, 108, 10, 118,
+         10, 118, 10, 2, 6, 110, 13, 115, 10, 8, 7, 103, 10, 104, 7, 7, 19, 109, 10, 96, 10, 118, 10,
+         70, 20, 0, 10, 70, 10, 0, 20, 0, 3, 239, 10, 6, 10, 22, 10, 0, 10, 128, 11, 165, 10, 6, 10,
+         182, 10, 86, 10, 134, 10, 6, 10, 0, 1, 3, 6, 6, 10, 198, 51, 2, 5, 0, 60, 78, 22, 0, 30, 0,
+         1, 0, 1, 25, 9, 14, 3, 0, 4, 138, 10, 30, 8, 1, 15, 32, 10, 39, 15, 0, 10, 188, 10, 0, 6,
+         154, 10, 38, 10, 198, 10, 22, 10, 86, 10, 0, 10, 0, 10, 0, 45, 12, 57, 17, 2, 0, 27, 36, 4,
+         29, 1, 8, 1, 134, 5, 202, 10, 0, 8, 25, 7, 39, 9, 75, 5, 22, 6, 160, 2, 2, 16, 2, 46, 64, 9,
+         52, 2, 30, 3, 75, 5, 104, 8, 24, 8, 41, 7, 0, 6, 48, 10, 0, 31, 158, 10, 42, 4, 112, 7, 134,
+         30, 128, 10, 60, 10, 144, 10, 7, 20, 251, 10, 0, 10, 118, 10, 0, 10, 102, 10, 102, 12, 0,
+         19, 93, 10, 0, 29, 227, 10, 70, 10, 0, 21, 0, 111, 0, 10, 230, 10, 1, 7, 0, 23, 0, 20, 108,
+         25, 0, 50, 0, 10, 0, 10, 0, 9, 128, 10, 0, 59, 1, 3, 1, 4, 76, 45, 1, 15, 0, 13, 0, 10, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod uppercase {
+     static BITSET_CHUNKS_MAP: [u8; 125] = [
+         12, 15, 5, 5, 0, 5, 5, 2, 4, 11, 5, 14, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+         5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 8, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+         5, 5, 5, 6, 5, 13, 5, 10, 5, 5, 1, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+         5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 16, 5, 5,
+         5, 5, 9, 5, 3,
+     ];
+     static BITSET_INDEX_CHUNKS: [[u8; 16]; 17] = [
+         [41, 41, 5, 33, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 5, 0],
+         [41, 41, 5, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 41, 38, 41, 41, 41, 41, 41, 17, 17, 61, 17, 40, 29, 24, 23],
+         [41, 41, 41, 41, 9, 8, 42, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 41, 41, 41, 35, 28, 65, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 56, 41, 41, 41],
+         [41, 41, 41, 41, 41, 41, 41, 41, 41, 46, 41, 41, 41, 41, 41, 41],
+         [41, 41, 41, 41, 41, 41, 41, 41, 41, 60, 59, 41, 20, 14, 16, 4],
+         [41, 41, 41, 41, 47, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 41, 51, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 41, 52, 43, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [41, 53, 41, 31, 34, 21, 22, 15, 13, 32, 41, 41, 41, 11, 30, 37],
+         [48, 41, 9, 44, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [49, 36, 17, 27, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [50, 19, 2, 18, 10, 45, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41],
+         [57, 1, 26, 54, 12, 7, 25, 55, 39, 58, 6, 3, 64, 63, 62, 66],
+     ];
+     static BITSET_CANONICAL: [u64; 41] = [
+         0b0000000000111111111111111111111111111111111111111111111111111111,
+         0b1111111111111111111111110000000000000000000000000011111111111111,
+         0b0101010101010101010101010101010101010101010101010101010000000001,
+         0b0000011111111111111111111111110000000000000000000000000000000001,
+         0b0000000000100000000000000000000000000000000000000000001011110100,
+         0b1111111111111111111111111111111100000000000000000000000000000000,
+         0b1111111111111111111111110000000000000000000000000000001111111111,
+         0b1111111111111111111100000000000000000000000000011111110001011111,
+         0b1111111111111111000000111111111111111111111111110000001111111111,
+         0b1111111111111111000000000000000000000000000000000000000000000000,
+         0b1111111111111110010101010101010101010101010101010101010101010101,
+         0b1000000001000101000000000000000000000000000000000000000000000000,
+         0b0111101100000000000000000000000000011111110111111110011110110000,
+         0b0110110000000101010101010101010101010101010101010101010101010101,
+         0b0110101000000000010101010101010101010101010101010101010101010101,
+         0b0101010111010010010101010101010101001010101010101010010010010000,
+         0b0101010101011111011111010101010101010101010001010010100001010101,
+         0b0101010101010101010101010101010101010101010101010101010101010101,
+         0b0101010101010101010101010101010101010101010101010010101010101011,
+         0b0101010101010101010101010101010100000000000000000000000000000000,
+         0b0101010101010100010101010101010000000000000000000000000000000000,
+         0b0010101101010101010101010101010101010101010101010101010010101010,
+         0b0001000110101110110100101101010110110001110110111100111011010110,
+         0b0000111100000000000111110000000000001111000000000000111100000000,
+         0b0000111100000000000000000000000000000000000000000000000000000000,
+         0b0000001111111111111111111111111100000000000000000000000000111111,
+         0b0000000000111111110111100110010011010000000000000000000000000011,
+         0b0000000000000100001010000000010101010101010101010101010101010101,
+         0b0000000000000000111111111111111100000000000000000000000000100000,
+         0b0000000000000000111111110000000010101010000000000011111100000000,
+         0b0000000000000000000011111111101111111111111111101101011101000000,
+         0b0000000000000000000000000000000001111111011111111111111111111111,
+         0b0000000000000000000000000000000000000000000000000101010101111010,
+         0b0000000000000000000000000000000000000000000000000010000010111111,
+         0b1010101001010101010101010101010101010101010101010101010101010101,
+         0b1100000000001111001111010101000000111110001001110011100010000100,
+         0b1100000000100101111010101001110100000000000000000000000000000000,
+         0b1110011010010000010101010101010101010101000111001000000000000000,
+         0b1110011111111111111111111111111111111111111111110000000000000000,
+         0b1111000000000000000000000000001111111111111111111111111100000000,
+         0b1111111100000000111111110000000000111111000000001111111100000000,
+     ];
+     static BITSET_MAPPING: [(u8, u8); 26] = [
+         (0, 182), (0, 74), (0, 166), (0, 162), (0, 159), (0, 150), (0, 148), (0, 142), (0, 135),
+         (0, 134), (0, 131), (0, 64), (1, 115), (1, 66), (1, 70), (1, 83), (1, 12), (1, 8), (2, 164),
+         (2, 146), (2, 20), (3, 146), (3, 140), (3, 134), (4, 178), (4, 171),
+     ];
+ 
+     pub fn lookup(c: char) -> bool {
+         super::bitset_search(
+             c as u32,
+             &BITSET_CHUNKS_MAP,
+             &BITSET_INDEX_CHUNKS,
+             &BITSET_CANONICAL,
+             &BITSET_MAPPING,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod white_space {
+     static SHORT_OFFSET_RUNS: [u32; 4] = [
+         5760, 18882560, 23080960, 40972289,
+     ];
+     static OFFSETS: [u8; 21] = [
+         9, 5, 18, 1, 100, 1, 26, 1, 0, 1, 0, 11, 29, 2, 5, 1, 47, 1, 0, 1, 0,
+     ];
+     pub fn lookup(c: char) -> bool {
+         super::skip_search(
+             c as u32,
+             &SHORT_OFFSET_RUNS,
+             &OFFSETS,
+         )
+     }
+ }
+ 
+ #[rustfmt::skip]
+ pub mod conversions {
+     pub fn to_lower(c: char) -> [char; 3] {
+         match bsearch_case_table(c, LOWERCASE_TABLE) {
+             None => [c, '\0', '\0'],
+             Some(index) => LOWERCASE_TABLE[index].1,
+         }
+     }
+ 
+     pub fn to_upper(c: char) -> [char; 3] {
+         match bsearch_case_table(c, UPPERCASE_TABLE) {
+             None => [c, '\0', '\0'],
+             Some(index) => UPPERCASE_TABLE[index].1,
+         }
+     }
+ 
+     fn bsearch_case_table(c: char, table: &[(char, [char; 3])]) -> Option<usize> {
+         table.binary_search_by(|&(key, _)| key.cmp(&c)).ok()
+     }
+     static LOWERCASE_TABLE: &[(char, [char; 3])] = &[
+         ('A', ['a', '\u{0}', '\u{0}']), ('B', ['b', '\u{0}', '\u{0}']),
+         ('C', ['c', '\u{0}', '\u{0}']), ('D', ['d', '\u{0}', '\u{0}']),
+         ('E', ['e', '\u{0}', '\u{0}']), ('F', ['f', '\u{0}', '\u{0}']),
+         ('G', ['g', '\u{0}', '\u{0}']), ('H', ['h', '\u{0}', '\u{0}']),
+         ('I', ['i', '\u{0}', '\u{0}']), ('J', ['j', '\u{0}', '\u{0}']),
+         ('K', ['k', '\u{0}', '\u{0}']), ('L', ['l', '\u{0}', '\u{0}']),
+         ('M', ['m', '\u{0}', '\u{0}']), ('N', ['n', '\u{0}', '\u{0}']),
+         ('O', ['o', '\u{0}', '\u{0}']), ('P', ['p', '\u{0}', '\u{0}']),
+         ('Q', ['q', '\u{0}', '\u{0}']), ('R', ['r', '\u{0}', '\u{0}']),
+         ('S', ['s', '\u{0}', '\u{0}']), ('T', ['t', '\u{0}', '\u{0}']),
+         ('U', ['u', '\u{0}', '\u{0}']), ('V', ['v', '\u{0}', '\u{0}']),
+         ('W', ['w', '\u{0}', '\u{0}']), ('X', ['x', '\u{0}', '\u{0}']),
+         ('Y', ['y', '\u{0}', '\u{0}']), ('Z', ['z', '\u{0}', '\u{0}']),
+         ('\u{c0}', ['\u{e0}', '\u{0}', '\u{0}']), ('\u{c1}', ['\u{e1}', '\u{0}', '\u{0}']),
+         ('\u{c2}', ['\u{e2}', '\u{0}', '\u{0}']), ('\u{c3}', ['\u{e3}', '\u{0}', '\u{0}']),
+         ('\u{c4}', ['\u{e4}', '\u{0}', '\u{0}']), ('\u{c5}', ['\u{e5}', '\u{0}', '\u{0}']),
+         ('\u{c6}', ['\u{e6}', '\u{0}', '\u{0}']), ('\u{c7}', ['\u{e7}', '\u{0}', '\u{0}']),
+         ('\u{c8}', ['\u{e8}', '\u{0}', '\u{0}']), ('\u{c9}', ['\u{e9}', '\u{0}', '\u{0}']),
+         ('\u{ca}', ['\u{ea}', '\u{0}', '\u{0}']), ('\u{cb}', ['\u{eb}', '\u{0}', '\u{0}']),
+         ('\u{cc}', ['\u{ec}', '\u{0}', '\u{0}']), ('\u{cd}', ['\u{ed}', '\u{0}', '\u{0}']),
+         ('\u{ce}', ['\u{ee}', '\u{0}', '\u{0}']), ('\u{cf}', ['\u{ef}', '\u{0}', '\u{0}']),
+         ('\u{d0}', ['\u{f0}', '\u{0}', '\u{0}']), ('\u{d1}', ['\u{f1}', '\u{0}', '\u{0}']),
+         ('\u{d2}', ['\u{f2}', '\u{0}', '\u{0}']), ('\u{d3}', ['\u{f3}', '\u{0}', '\u{0}']),
+         ('\u{d4}', ['\u{f4}', '\u{0}', '\u{0}']), ('\u{d5}', ['\u{f5}', '\u{0}', '\u{0}']),
+         ('\u{d6}', ['\u{f6}', '\u{0}', '\u{0}']), ('\u{d8}', ['\u{f8}', '\u{0}', '\u{0}']),
+         ('\u{d9}', ['\u{f9}', '\u{0}', '\u{0}']), ('\u{da}', ['\u{fa}', '\u{0}', '\u{0}']),
+         ('\u{db}', ['\u{fb}', '\u{0}', '\u{0}']), ('\u{dc}', ['\u{fc}', '\u{0}', '\u{0}']),
+         ('\u{dd}', ['\u{fd}', '\u{0}', '\u{0}']), ('\u{de}', ['\u{fe}', '\u{0}', '\u{0}']),
+         ('\u{100}', ['\u{101}', '\u{0}', '\u{0}']), ('\u{102}', ['\u{103}', '\u{0}', '\u{0}']),
+         ('\u{104}', ['\u{105}', '\u{0}', '\u{0}']), ('\u{106}', ['\u{107}', '\u{0}', '\u{0}']),
+         ('\u{108}', ['\u{109}', '\u{0}', '\u{0}']), ('\u{10a}', ['\u{10b}', '\u{0}', '\u{0}']),
+         ('\u{10c}', ['\u{10d}', '\u{0}', '\u{0}']), ('\u{10e}', ['\u{10f}', '\u{0}', '\u{0}']),
+         ('\u{110}', ['\u{111}', '\u{0}', '\u{0}']), ('\u{112}', ['\u{113}', '\u{0}', '\u{0}']),
+         ('\u{114}', ['\u{115}', '\u{0}', '\u{0}']), ('\u{116}', ['\u{117}', '\u{0}', '\u{0}']),
+         ('\u{118}', ['\u{119}', '\u{0}', '\u{0}']), ('\u{11a}', ['\u{11b}', '\u{0}', '\u{0}']),
+         ('\u{11c}', ['\u{11d}', '\u{0}', '\u{0}']), ('\u{11e}', ['\u{11f}', '\u{0}', '\u{0}']),
+         ('\u{120}', ['\u{121}', '\u{0}', '\u{0}']), ('\u{122}', ['\u{123}', '\u{0}', '\u{0}']),
+         ('\u{124}', ['\u{125}', '\u{0}', '\u{0}']), ('\u{126}', ['\u{127}', '\u{0}', '\u{0}']),
+         ('\u{128}', ['\u{129}', '\u{0}', '\u{0}']), ('\u{12a}', ['\u{12b}', '\u{0}', '\u{0}']),
+         ('\u{12c}', ['\u{12d}', '\u{0}', '\u{0}']), ('\u{12e}', ['\u{12f}', '\u{0}', '\u{0}']),
+         ('\u{130}', ['i', '\u{307}', '\u{0}']), ('\u{132}', ['\u{133}', '\u{0}', '\u{0}']),
+         ('\u{134}', ['\u{135}', '\u{0}', '\u{0}']), ('\u{136}', ['\u{137}', '\u{0}', '\u{0}']),
+         ('\u{139}', ['\u{13a}', '\u{0}', '\u{0}']), ('\u{13b}', ['\u{13c}', '\u{0}', '\u{0}']),
+         ('\u{13d}', ['\u{13e}', '\u{0}', '\u{0}']), ('\u{13f}', ['\u{140}', '\u{0}', '\u{0}']),
+         ('\u{141}', ['\u{142}', '\u{0}', '\u{0}']), ('\u{143}', ['\u{144}', '\u{0}', '\u{0}']),
+         ('\u{145}', ['\u{146}', '\u{0}', '\u{0}']), ('\u{147}', ['\u{148}', '\u{0}', '\u{0}']),
+         ('\u{14a}', ['\u{14b}', '\u{0}', '\u{0}']), ('\u{14c}', ['\u{14d}', '\u{0}', '\u{0}']),
+         ('\u{14e}', ['\u{14f}', '\u{0}', '\u{0}']), ('\u{150}', ['\u{151}', '\u{0}', '\u{0}']),
+         ('\u{152}', ['\u{153}', '\u{0}', '\u{0}']), ('\u{154}', ['\u{155}', '\u{0}', '\u{0}']),
+         ('\u{156}', ['\u{157}', '\u{0}', '\u{0}']), ('\u{158}', ['\u{159}', '\u{0}', '\u{0}']),
+         ('\u{15a}', ['\u{15b}', '\u{0}', '\u{0}']), ('\u{15c}', ['\u{15d}', '\u{0}', '\u{0}']),
+         ('\u{15e}', ['\u{15f}', '\u{0}', '\u{0}']), ('\u{160}', ['\u{161}', '\u{0}', '\u{0}']),
+         ('\u{162}', ['\u{163}', '\u{0}', '\u{0}']), ('\u{164}', ['\u{165}', '\u{0}', '\u{0}']),
+         ('\u{166}', ['\u{167}', '\u{0}', '\u{0}']), ('\u{168}', ['\u{169}', '\u{0}', '\u{0}']),
+         ('\u{16a}', ['\u{16b}', '\u{0}', '\u{0}']), ('\u{16c}', ['\u{16d}', '\u{0}', '\u{0}']),
+         ('\u{16e}', ['\u{16f}', '\u{0}', '\u{0}']), ('\u{170}', ['\u{171}', '\u{0}', '\u{0}']),
+         ('\u{172}', ['\u{173}', '\u{0}', '\u{0}']), ('\u{174}', ['\u{175}', '\u{0}', '\u{0}']),
+         ('\u{176}', ['\u{177}', '\u{0}', '\u{0}']), ('\u{178}', ['\u{ff}', '\u{0}', '\u{0}']),
+         ('\u{179}', ['\u{17a}', '\u{0}', '\u{0}']), ('\u{17b}', ['\u{17c}', '\u{0}', '\u{0}']),
+         ('\u{17d}', ['\u{17e}', '\u{0}', '\u{0}']), ('\u{181}', ['\u{253}', '\u{0}', '\u{0}']),
+         ('\u{182}', ['\u{183}', '\u{0}', '\u{0}']), ('\u{184}', ['\u{185}', '\u{0}', '\u{0}']),
+         ('\u{186}', ['\u{254}', '\u{0}', '\u{0}']), ('\u{187}', ['\u{188}', '\u{0}', '\u{0}']),
+         ('\u{189}', ['\u{256}', '\u{0}', '\u{0}']), ('\u{18a}', ['\u{257}', '\u{0}', '\u{0}']),
+         ('\u{18b}', ['\u{18c}', '\u{0}', '\u{0}']), ('\u{18e}', ['\u{1dd}', '\u{0}', '\u{0}']),
+         ('\u{18f}', ['\u{259}', '\u{0}', '\u{0}']), ('\u{190}', ['\u{25b}', '\u{0}', '\u{0}']),
+         ('\u{191}', ['\u{192}', '\u{0}', '\u{0}']), ('\u{193}', ['\u{260}', '\u{0}', '\u{0}']),
+         ('\u{194}', ['\u{263}', '\u{0}', '\u{0}']), ('\u{196}', ['\u{269}', '\u{0}', '\u{0}']),
+         ('\u{197}', ['\u{268}', '\u{0}', '\u{0}']), ('\u{198}', ['\u{199}', '\u{0}', '\u{0}']),
+         ('\u{19c}', ['\u{26f}', '\u{0}', '\u{0}']), ('\u{19d}', ['\u{272}', '\u{0}', '\u{0}']),
+         ('\u{19f}', ['\u{275}', '\u{0}', '\u{0}']), ('\u{1a0}', ['\u{1a1}', '\u{0}', '\u{0}']),
+         ('\u{1a2}', ['\u{1a3}', '\u{0}', '\u{0}']), ('\u{1a4}', ['\u{1a5}', '\u{0}', '\u{0}']),
+         ('\u{1a6}', ['\u{280}', '\u{0}', '\u{0}']), ('\u{1a7}', ['\u{1a8}', '\u{0}', '\u{0}']),
+         ('\u{1a9}', ['\u{283}', '\u{0}', '\u{0}']), ('\u{1ac}', ['\u{1ad}', '\u{0}', '\u{0}']),
+         ('\u{1ae}', ['\u{288}', '\u{0}', '\u{0}']), ('\u{1af}', ['\u{1b0}', '\u{0}', '\u{0}']),
+         ('\u{1b1}', ['\u{28a}', '\u{0}', '\u{0}']), ('\u{1b2}', ['\u{28b}', '\u{0}', '\u{0}']),
+         ('\u{1b3}', ['\u{1b4}', '\u{0}', '\u{0}']), ('\u{1b5}', ['\u{1b6}', '\u{0}', '\u{0}']),
+         ('\u{1b7}', ['\u{292}', '\u{0}', '\u{0}']), ('\u{1b8}', ['\u{1b9}', '\u{0}', '\u{0}']),
+         ('\u{1bc}', ['\u{1bd}', '\u{0}', '\u{0}']), ('\u{1c4}', ['\u{1c6}', '\u{0}', '\u{0}']),
+         ('\u{1c5}', ['\u{1c6}', '\u{0}', '\u{0}']), ('\u{1c7}', ['\u{1c9}', '\u{0}', '\u{0}']),
+         ('\u{1c8}', ['\u{1c9}', '\u{0}', '\u{0}']), ('\u{1ca}', ['\u{1cc}', '\u{0}', '\u{0}']),
+         ('\u{1cb}', ['\u{1cc}', '\u{0}', '\u{0}']), ('\u{1cd}', ['\u{1ce}', '\u{0}', '\u{0}']),
+         ('\u{1cf}', ['\u{1d0}', '\u{0}', '\u{0}']), ('\u{1d1}', ['\u{1d2}', '\u{0}', '\u{0}']),
+         ('\u{1d3}', ['\u{1d4}', '\u{0}', '\u{0}']), ('\u{1d5}', ['\u{1d6}', '\u{0}', '\u{0}']),
+         ('\u{1d7}', ['\u{1d8}', '\u{0}', '\u{0}']), ('\u{1d9}', ['\u{1da}', '\u{0}', '\u{0}']),
+         ('\u{1db}', ['\u{1dc}', '\u{0}', '\u{0}']), ('\u{1de}', ['\u{1df}', '\u{0}', '\u{0}']),
+         ('\u{1e0}', ['\u{1e1}', '\u{0}', '\u{0}']), ('\u{1e2}', ['\u{1e3}', '\u{0}', '\u{0}']),
+         ('\u{1e4}', ['\u{1e5}', '\u{0}', '\u{0}']), ('\u{1e6}', ['\u{1e7}', '\u{0}', '\u{0}']),
+         ('\u{1e8}', ['\u{1e9}', '\u{0}', '\u{0}']), ('\u{1ea}', ['\u{1eb}', '\u{0}', '\u{0}']),
+         ('\u{1ec}', ['\u{1ed}', '\u{0}', '\u{0}']), ('\u{1ee}', ['\u{1ef}', '\u{0}', '\u{0}']),
+         ('\u{1f1}', ['\u{1f3}', '\u{0}', '\u{0}']), ('\u{1f2}', ['\u{1f3}', '\u{0}', '\u{0}']),
+         ('\u{1f4}', ['\u{1f5}', '\u{0}', '\u{0}']), ('\u{1f6}', ['\u{195}', '\u{0}', '\u{0}']),
+         ('\u{1f7}', ['\u{1bf}', '\u{0}', '\u{0}']), ('\u{1f8}', ['\u{1f9}', '\u{0}', '\u{0}']),
+         ('\u{1fa}', ['\u{1fb}', '\u{0}', '\u{0}']), ('\u{1fc}', ['\u{1fd}', '\u{0}', '\u{0}']),
+         ('\u{1fe}', ['\u{1ff}', '\u{0}', '\u{0}']), ('\u{200}', ['\u{201}', '\u{0}', '\u{0}']),
+         ('\u{202}', ['\u{203}', '\u{0}', '\u{0}']), ('\u{204}', ['\u{205}', '\u{0}', '\u{0}']),
+         ('\u{206}', ['\u{207}', '\u{0}', '\u{0}']), ('\u{208}', ['\u{209}', '\u{0}', '\u{0}']),
+         ('\u{20a}', ['\u{20b}', '\u{0}', '\u{0}']), ('\u{20c}', ['\u{20d}', '\u{0}', '\u{0}']),
+         ('\u{20e}', ['\u{20f}', '\u{0}', '\u{0}']), ('\u{210}', ['\u{211}', '\u{0}', '\u{0}']),
+         ('\u{212}', ['\u{213}', '\u{0}', '\u{0}']), ('\u{214}', ['\u{215}', '\u{0}', '\u{0}']),
+         ('\u{216}', ['\u{217}', '\u{0}', '\u{0}']), ('\u{218}', ['\u{219}', '\u{0}', '\u{0}']),
+         ('\u{21a}', ['\u{21b}', '\u{0}', '\u{0}']), ('\u{21c}', ['\u{21d}', '\u{0}', '\u{0}']),
+         ('\u{21e}', ['\u{21f}', '\u{0}', '\u{0}']), ('\u{220}', ['\u{19e}', '\u{0}', '\u{0}']),
+         ('\u{222}', ['\u{223}', '\u{0}', '\u{0}']), ('\u{224}', ['\u{225}', '\u{0}', '\u{0}']),
+         ('\u{226}', ['\u{227}', '\u{0}', '\u{0}']), ('\u{228}', ['\u{229}', '\u{0}', '\u{0}']),
+         ('\u{22a}', ['\u{22b}', '\u{0}', '\u{0}']), ('\u{22c}', ['\u{22d}', '\u{0}', '\u{0}']),
+         ('\u{22e}', ['\u{22f}', '\u{0}', '\u{0}']), ('\u{230}', ['\u{231}', '\u{0}', '\u{0}']),
+         ('\u{232}', ['\u{233}', '\u{0}', '\u{0}']), ('\u{23a}', ['\u{2c65}', '\u{0}', '\u{0}']),
+         ('\u{23b}', ['\u{23c}', '\u{0}', '\u{0}']), ('\u{23d}', ['\u{19a}', '\u{0}', '\u{0}']),
+         ('\u{23e}', ['\u{2c66}', '\u{0}', '\u{0}']), ('\u{241}', ['\u{242}', '\u{0}', '\u{0}']),
+         ('\u{243}', ['\u{180}', '\u{0}', '\u{0}']), ('\u{244}', ['\u{289}', '\u{0}', '\u{0}']),
+         ('\u{245}', ['\u{28c}', '\u{0}', '\u{0}']), ('\u{246}', ['\u{247}', '\u{0}', '\u{0}']),
+         ('\u{248}', ['\u{249}', '\u{0}', '\u{0}']), ('\u{24a}', ['\u{24b}', '\u{0}', '\u{0}']),
+         ('\u{24c}', ['\u{24d}', '\u{0}', '\u{0}']), ('\u{24e}', ['\u{24f}', '\u{0}', '\u{0}']),
+         ('\u{370}', ['\u{371}', '\u{0}', '\u{0}']), ('\u{372}', ['\u{373}', '\u{0}', '\u{0}']),
+         ('\u{376}', ['\u{377}', '\u{0}', '\u{0}']), ('\u{37f}', ['\u{3f3}', '\u{0}', '\u{0}']),
+         ('\u{386}', ['\u{3ac}', '\u{0}', '\u{0}']), ('\u{388}', ['\u{3ad}', '\u{0}', '\u{0}']),
+         ('\u{389}', ['\u{3ae}', '\u{0}', '\u{0}']), ('\u{38a}', ['\u{3af}', '\u{0}', '\u{0}']),
+         ('\u{38c}', ['\u{3cc}', '\u{0}', '\u{0}']), ('\u{38e}', ['\u{3cd}', '\u{0}', '\u{0}']),
+         ('\u{38f}', ['\u{3ce}', '\u{0}', '\u{0}']), ('\u{391}', ['\u{3b1}', '\u{0}', '\u{0}']),
+         ('\u{392}', ['\u{3b2}', '\u{0}', '\u{0}']), ('\u{393}', ['\u{3b3}', '\u{0}', '\u{0}']),
+         ('\u{394}', ['\u{3b4}', '\u{0}', '\u{0}']), ('\u{395}', ['\u{3b5}', '\u{0}', '\u{0}']),
+         ('\u{396}', ['\u{3b6}', '\u{0}', '\u{0}']), ('\u{397}', ['\u{3b7}', '\u{0}', '\u{0}']),
+         ('\u{398}', ['\u{3b8}', '\u{0}', '\u{0}']), ('\u{399}', ['\u{3b9}', '\u{0}', '\u{0}']),
+         ('\u{39a}', ['\u{3ba}', '\u{0}', '\u{0}']), ('\u{39b}', ['\u{3bb}', '\u{0}', '\u{0}']),
+         ('\u{39c}', ['\u{3bc}', '\u{0}', '\u{0}']), ('\u{39d}', ['\u{3bd}', '\u{0}', '\u{0}']),
+         ('\u{39e}', ['\u{3be}', '\u{0}', '\u{0}']), ('\u{39f}', ['\u{3bf}', '\u{0}', '\u{0}']),
+         ('\u{3a0}', ['\u{3c0}', '\u{0}', '\u{0}']), ('\u{3a1}', ['\u{3c1}', '\u{0}', '\u{0}']),
+         ('\u{3a3}', ['\u{3c3}', '\u{0}', '\u{0}']), ('\u{3a4}', ['\u{3c4}', '\u{0}', '\u{0}']),
+         ('\u{3a5}', ['\u{3c5}', '\u{0}', '\u{0}']), ('\u{3a6}', ['\u{3c6}', '\u{0}', '\u{0}']),
+         ('\u{3a7}', ['\u{3c7}', '\u{0}', '\u{0}']), ('\u{3a8}', ['\u{3c8}', '\u{0}', '\u{0}']),
+         ('\u{3a9}', ['\u{3c9}', '\u{0}', '\u{0}']), ('\u{3aa}', ['\u{3ca}', '\u{0}', '\u{0}']),
+         ('\u{3ab}', ['\u{3cb}', '\u{0}', '\u{0}']), ('\u{3cf}', ['\u{3d7}', '\u{0}', '\u{0}']),
+         ('\u{3d8}', ['\u{3d9}', '\u{0}', '\u{0}']), ('\u{3da}', ['\u{3db}', '\u{0}', '\u{0}']),
+         ('\u{3dc}', ['\u{3dd}', '\u{0}', '\u{0}']), ('\u{3de}', ['\u{3df}', '\u{0}', '\u{0}']),
+         ('\u{3e0}', ['\u{3e1}', '\u{0}', '\u{0}']), ('\u{3e2}', ['\u{3e3}', '\u{0}', '\u{0}']),
+         ('\u{3e4}', ['\u{3e5}', '\u{0}', '\u{0}']), ('\u{3e6}', ['\u{3e7}', '\u{0}', '\u{0}']),
+         ('\u{3e8}', ['\u{3e9}', '\u{0}', '\u{0}']), ('\u{3ea}', ['\u{3eb}', '\u{0}', '\u{0}']),
+         ('\u{3ec}', ['\u{3ed}', '\u{0}', '\u{0}']), ('\u{3ee}', ['\u{3ef}', '\u{0}', '\u{0}']),
+         ('\u{3f4}', ['\u{3b8}', '\u{0}', '\u{0}']), ('\u{3f7}', ['\u{3f8}', '\u{0}', '\u{0}']),
+         ('\u{3f9}', ['\u{3f2}', '\u{0}', '\u{0}']), ('\u{3fa}', ['\u{3fb}', '\u{0}', '\u{0}']),
+         ('\u{3fd}', ['\u{37b}', '\u{0}', '\u{0}']), ('\u{3fe}', ['\u{37c}', '\u{0}', '\u{0}']),
+         ('\u{3ff}', ['\u{37d}', '\u{0}', '\u{0}']), ('\u{400}', ['\u{450}', '\u{0}', '\u{0}']),
+         ('\u{401}', ['\u{451}', '\u{0}', '\u{0}']), ('\u{402}', ['\u{452}', '\u{0}', '\u{0}']),
+         ('\u{403}', ['\u{453}', '\u{0}', '\u{0}']), ('\u{404}', ['\u{454}', '\u{0}', '\u{0}']),
+         ('\u{405}', ['\u{455}', '\u{0}', '\u{0}']), ('\u{406}', ['\u{456}', '\u{0}', '\u{0}']),
+         ('\u{407}', ['\u{457}', '\u{0}', '\u{0}']), ('\u{408}', ['\u{458}', '\u{0}', '\u{0}']),
+         ('\u{409}', ['\u{459}', '\u{0}', '\u{0}']), ('\u{40a}', ['\u{45a}', '\u{0}', '\u{0}']),
+         ('\u{40b}', ['\u{45b}', '\u{0}', '\u{0}']), ('\u{40c}', ['\u{45c}', '\u{0}', '\u{0}']),
+         ('\u{40d}', ['\u{45d}', '\u{0}', '\u{0}']), ('\u{40e}', ['\u{45e}', '\u{0}', '\u{0}']),
+         ('\u{40f}', ['\u{45f}', '\u{0}', '\u{0}']), ('\u{410}', ['\u{430}', '\u{0}', '\u{0}']),
+         ('\u{411}', ['\u{431}', '\u{0}', '\u{0}']), ('\u{412}', ['\u{432}', '\u{0}', '\u{0}']),
+         ('\u{413}', ['\u{433}', '\u{0}', '\u{0}']), ('\u{414}', ['\u{434}', '\u{0}', '\u{0}']),
+         ('\u{415}', ['\u{435}', '\u{0}', '\u{0}']), ('\u{416}', ['\u{436}', '\u{0}', '\u{0}']),
+         ('\u{417}', ['\u{437}', '\u{0}', '\u{0}']), ('\u{418}', ['\u{438}', '\u{0}', '\u{0}']),
+         ('\u{419}', ['\u{439}', '\u{0}', '\u{0}']), ('\u{41a}', ['\u{43a}', '\u{0}', '\u{0}']),
+         ('\u{41b}', ['\u{43b}', '\u{0}', '\u{0}']), ('\u{41c}', ['\u{43c}', '\u{0}', '\u{0}']),
+         ('\u{41d}', ['\u{43d}', '\u{0}', '\u{0}']), ('\u{41e}', ['\u{43e}', '\u{0}', '\u{0}']),
+         ('\u{41f}', ['\u{43f}', '\u{0}', '\u{0}']), ('\u{420}', ['\u{440}', '\u{0}', '\u{0}']),
+         ('\u{421}', ['\u{441}', '\u{0}', '\u{0}']), ('\u{422}', ['\u{442}', '\u{0}', '\u{0}']),
+         ('\u{423}', ['\u{443}', '\u{0}', '\u{0}']), ('\u{424}', ['\u{444}', '\u{0}', '\u{0}']),
+         ('\u{425}', ['\u{445}', '\u{0}', '\u{0}']), ('\u{426}', ['\u{446}', '\u{0}', '\u{0}']),
+         ('\u{427}', ['\u{447}', '\u{0}', '\u{0}']), ('\u{428}', ['\u{448}', '\u{0}', '\u{0}']),
+         ('\u{429}', ['\u{449}', '\u{0}', '\u{0}']), ('\u{42a}', ['\u{44a}', '\u{0}', '\u{0}']),
+         ('\u{42b}', ['\u{44b}', '\u{0}', '\u{0}']), ('\u{42c}', ['\u{44c}', '\u{0}', '\u{0}']),
+         ('\u{42d}', ['\u{44d}', '\u{0}', '\u{0}']), ('\u{42e}', ['\u{44e}', '\u{0}', '\u{0}']),
+         ('\u{42f}', ['\u{44f}', '\u{0}', '\u{0}']), ('\u{460}', ['\u{461}', '\u{0}', '\u{0}']),
+         ('\u{462}', ['\u{463}', '\u{0}', '\u{0}']), ('\u{464}', ['\u{465}', '\u{0}', '\u{0}']),
+         ('\u{466}', ['\u{467}', '\u{0}', '\u{0}']), ('\u{468}', ['\u{469}', '\u{0}', '\u{0}']),
+         ('\u{46a}', ['\u{46b}', '\u{0}', '\u{0}']), ('\u{46c}', ['\u{46d}', '\u{0}', '\u{0}']),
+         ('\u{46e}', ['\u{46f}', '\u{0}', '\u{0}']), ('\u{470}', ['\u{471}', '\u{0}', '\u{0}']),
+         ('\u{472}', ['\u{473}', '\u{0}', '\u{0}']), ('\u{474}', ['\u{475}', '\u{0}', '\u{0}']),
+         ('\u{476}', ['\u{477}', '\u{0}', '\u{0}']), ('\u{478}', ['\u{479}', '\u{0}', '\u{0}']),
+         ('\u{47a}', ['\u{47b}', '\u{0}', '\u{0}']), ('\u{47c}', ['\u{47d}', '\u{0}', '\u{0}']),
+         ('\u{47e}', ['\u{47f}', '\u{0}', '\u{0}']), ('\u{480}', ['\u{481}', '\u{0}', '\u{0}']),
+         ('\u{48a}', ['\u{48b}', '\u{0}', '\u{0}']), ('\u{48c}', ['\u{48d}', '\u{0}', '\u{0}']),
+         ('\u{48e}', ['\u{48f}', '\u{0}', '\u{0}']), ('\u{490}', ['\u{491}', '\u{0}', '\u{0}']),
+         ('\u{492}', ['\u{493}', '\u{0}', '\u{0}']), ('\u{494}', ['\u{495}', '\u{0}', '\u{0}']),
+         ('\u{496}', ['\u{497}', '\u{0}', '\u{0}']), ('\u{498}', ['\u{499}', '\u{0}', '\u{0}']),
+         ('\u{49a}', ['\u{49b}', '\u{0}', '\u{0}']), ('\u{49c}', ['\u{49d}', '\u{0}', '\u{0}']),
+         ('\u{49e}', ['\u{49f}', '\u{0}', '\u{0}']), ('\u{4a0}', ['\u{4a1}', '\u{0}', '\u{0}']),
+         ('\u{4a2}', ['\u{4a3}', '\u{0}', '\u{0}']), ('\u{4a4}', ['\u{4a5}', '\u{0}', '\u{0}']),
+         ('\u{4a6}', ['\u{4a7}', '\u{0}', '\u{0}']), ('\u{4a8}', ['\u{4a9}', '\u{0}', '\u{0}']),
+         ('\u{4aa}', ['\u{4ab}', '\u{0}', '\u{0}']), ('\u{4ac}', ['\u{4ad}', '\u{0}', '\u{0}']),
+         ('\u{4ae}', ['\u{4af}', '\u{0}', '\u{0}']), ('\u{4b0}', ['\u{4b1}', '\u{0}', '\u{0}']),
+         ('\u{4b2}', ['\u{4b3}', '\u{0}', '\u{0}']), ('\u{4b4}', ['\u{4b5}', '\u{0}', '\u{0}']),
+         ('\u{4b6}', ['\u{4b7}', '\u{0}', '\u{0}']), ('\u{4b8}', ['\u{4b9}', '\u{0}', '\u{0}']),
+         ('\u{4ba}', ['\u{4bb}', '\u{0}', '\u{0}']), ('\u{4bc}', ['\u{4bd}', '\u{0}', '\u{0}']),
+         ('\u{4be}', ['\u{4bf}', '\u{0}', '\u{0}']), ('\u{4c0}', ['\u{4cf}', '\u{0}', '\u{0}']),
+         ('\u{4c1}', ['\u{4c2}', '\u{0}', '\u{0}']), ('\u{4c3}', ['\u{4c4}', '\u{0}', '\u{0}']),
+         ('\u{4c5}', ['\u{4c6}', '\u{0}', '\u{0}']), ('\u{4c7}', ['\u{4c8}', '\u{0}', '\u{0}']),
+         ('\u{4c9}', ['\u{4ca}', '\u{0}', '\u{0}']), ('\u{4cb}', ['\u{4cc}', '\u{0}', '\u{0}']),
+         ('\u{4cd}', ['\u{4ce}', '\u{0}', '\u{0}']), ('\u{4d0}', ['\u{4d1}', '\u{0}', '\u{0}']),
+         ('\u{4d2}', ['\u{4d3}', '\u{0}', '\u{0}']), ('\u{4d4}', ['\u{4d5}', '\u{0}', '\u{0}']),
+         ('\u{4d6}', ['\u{4d7}', '\u{0}', '\u{0}']), ('\u{4d8}', ['\u{4d9}', '\u{0}', '\u{0}']),
+         ('\u{4da}', ['\u{4db}', '\u{0}', '\u{0}']), ('\u{4dc}', ['\u{4dd}', '\u{0}', '\u{0}']),
+         ('\u{4de}', ['\u{4df}', '\u{0}', '\u{0}']), ('\u{4e0}', ['\u{4e1}', '\u{0}', '\u{0}']),
+         ('\u{4e2}', ['\u{4e3}', '\u{0}', '\u{0}']), ('\u{4e4}', ['\u{4e5}', '\u{0}', '\u{0}']),
+         ('\u{4e6}', ['\u{4e7}', '\u{0}', '\u{0}']), ('\u{4e8}', ['\u{4e9}', '\u{0}', '\u{0}']),
+         ('\u{4ea}', ['\u{4eb}', '\u{0}', '\u{0}']), ('\u{4ec}', ['\u{4ed}', '\u{0}', '\u{0}']),
+         ('\u{4ee}', ['\u{4ef}', '\u{0}', '\u{0}']), ('\u{4f0}', ['\u{4f1}', '\u{0}', '\u{0}']),
+         ('\u{4f2}', ['\u{4f3}', '\u{0}', '\u{0}']), ('\u{4f4}', ['\u{4f5}', '\u{0}', '\u{0}']),
+         ('\u{4f6}', ['\u{4f7}', '\u{0}', '\u{0}']), ('\u{4f8}', ['\u{4f9}', '\u{0}', '\u{0}']),
+         ('\u{4fa}', ['\u{4fb}', '\u{0}', '\u{0}']), ('\u{4fc}', ['\u{4fd}', '\u{0}', '\u{0}']),
+         ('\u{4fe}', ['\u{4ff}', '\u{0}', '\u{0}']), ('\u{500}', ['\u{501}', '\u{0}', '\u{0}']),
+         ('\u{502}', ['\u{503}', '\u{0}', '\u{0}']), ('\u{504}', ['\u{505}', '\u{0}', '\u{0}']),
+         ('\u{506}', ['\u{507}', '\u{0}', '\u{0}']), ('\u{508}', ['\u{509}', '\u{0}', '\u{0}']),
+         ('\u{50a}', ['\u{50b}', '\u{0}', '\u{0}']), ('\u{50c}', ['\u{50d}', '\u{0}', '\u{0}']),
+         ('\u{50e}', ['\u{50f}', '\u{0}', '\u{0}']), ('\u{510}', ['\u{511}', '\u{0}', '\u{0}']),
+         ('\u{512}', ['\u{513}', '\u{0}', '\u{0}']), ('\u{514}', ['\u{515}', '\u{0}', '\u{0}']),
+         ('\u{516}', ['\u{517}', '\u{0}', '\u{0}']), ('\u{518}', ['\u{519}', '\u{0}', '\u{0}']),
+         ('\u{51a}', ['\u{51b}', '\u{0}', '\u{0}']), ('\u{51c}', ['\u{51d}', '\u{0}', '\u{0}']),
+         ('\u{51e}', ['\u{51f}', '\u{0}', '\u{0}']), ('\u{520}', ['\u{521}', '\u{0}', '\u{0}']),
+         ('\u{522}', ['\u{523}', '\u{0}', '\u{0}']), ('\u{524}', ['\u{525}', '\u{0}', '\u{0}']),
+         ('\u{526}', ['\u{527}', '\u{0}', '\u{0}']), ('\u{528}', ['\u{529}', '\u{0}', '\u{0}']),
+         ('\u{52a}', ['\u{52b}', '\u{0}', '\u{0}']), ('\u{52c}', ['\u{52d}', '\u{0}', '\u{0}']),
+         ('\u{52e}', ['\u{52f}', '\u{0}', '\u{0}']), ('\u{531}', ['\u{561}', '\u{0}', '\u{0}']),
+         ('\u{532}', ['\u{562}', '\u{0}', '\u{0}']), ('\u{533}', ['\u{563}', '\u{0}', '\u{0}']),
+         ('\u{534}', ['\u{564}', '\u{0}', '\u{0}']), ('\u{535}', ['\u{565}', '\u{0}', '\u{0}']),
+         ('\u{536}', ['\u{566}', '\u{0}', '\u{0}']), ('\u{537}', ['\u{567}', '\u{0}', '\u{0}']),
+         ('\u{538}', ['\u{568}', '\u{0}', '\u{0}']), ('\u{539}', ['\u{569}', '\u{0}', '\u{0}']),
+         ('\u{53a}', ['\u{56a}', '\u{0}', '\u{0}']), ('\u{53b}', ['\u{56b}', '\u{0}', '\u{0}']),
+         ('\u{53c}', ['\u{56c}', '\u{0}', '\u{0}']), ('\u{53d}', ['\u{56d}', '\u{0}', '\u{0}']),
+         ('\u{53e}', ['\u{56e}', '\u{0}', '\u{0}']), ('\u{53f}', ['\u{56f}', '\u{0}', '\u{0}']),
+         ('\u{540}', ['\u{570}', '\u{0}', '\u{0}']), ('\u{541}', ['\u{571}', '\u{0}', '\u{0}']),
+         ('\u{542}', ['\u{572}', '\u{0}', '\u{0}']), ('\u{543}', ['\u{573}', '\u{0}', '\u{0}']),
+         ('\u{544}', ['\u{574}', '\u{0}', '\u{0}']), ('\u{545}', ['\u{575}', '\u{0}', '\u{0}']),
+         ('\u{546}', ['\u{576}', '\u{0}', '\u{0}']), ('\u{547}', ['\u{577}', '\u{0}', '\u{0}']),
+         ('\u{548}', ['\u{578}', '\u{0}', '\u{0}']), ('\u{549}', ['\u{579}', '\u{0}', '\u{0}']),
+         ('\u{54a}', ['\u{57a}', '\u{0}', '\u{0}']), ('\u{54b}', ['\u{57b}', '\u{0}', '\u{0}']),
+         ('\u{54c}', ['\u{57c}', '\u{0}', '\u{0}']), ('\u{54d}', ['\u{57d}', '\u{0}', '\u{0}']),
+         ('\u{54e}', ['\u{57e}', '\u{0}', '\u{0}']), ('\u{54f}', ['\u{57f}', '\u{0}', '\u{0}']),
+         ('\u{550}', ['\u{580}', '\u{0}', '\u{0}']), ('\u{551}', ['\u{581}', '\u{0}', '\u{0}']),
+         ('\u{552}', ['\u{582}', '\u{0}', '\u{0}']), ('\u{553}', ['\u{583}', '\u{0}', '\u{0}']),
+         ('\u{554}', ['\u{584}', '\u{0}', '\u{0}']), ('\u{555}', ['\u{585}', '\u{0}', '\u{0}']),
+         ('\u{556}', ['\u{586}', '\u{0}', '\u{0}']), ('\u{10a0}', ['\u{2d00}', '\u{0}', '\u{0}']),
+         ('\u{10a1}', ['\u{2d01}', '\u{0}', '\u{0}']), ('\u{10a2}', ['\u{2d02}', '\u{0}', '\u{0}']),
+         ('\u{10a3}', ['\u{2d03}', '\u{0}', '\u{0}']), ('\u{10a4}', ['\u{2d04}', '\u{0}', '\u{0}']),
+         ('\u{10a5}', ['\u{2d05}', '\u{0}', '\u{0}']), ('\u{10a6}', ['\u{2d06}', '\u{0}', '\u{0}']),
+         ('\u{10a7}', ['\u{2d07}', '\u{0}', '\u{0}']), ('\u{10a8}', ['\u{2d08}', '\u{0}', '\u{0}']),
+         ('\u{10a9}', ['\u{2d09}', '\u{0}', '\u{0}']), ('\u{10aa}', ['\u{2d0a}', '\u{0}', '\u{0}']),
+         ('\u{10ab}', ['\u{2d0b}', '\u{0}', '\u{0}']), ('\u{10ac}', ['\u{2d0c}', '\u{0}', '\u{0}']),
+         ('\u{10ad}', ['\u{2d0d}', '\u{0}', '\u{0}']), ('\u{10ae}', ['\u{2d0e}', '\u{0}', '\u{0}']),
+         ('\u{10af}', ['\u{2d0f}', '\u{0}', '\u{0}']), ('\u{10b0}', ['\u{2d10}', '\u{0}', '\u{0}']),
+         ('\u{10b1}', ['\u{2d11}', '\u{0}', '\u{0}']), ('\u{10b2}', ['\u{2d12}', '\u{0}', '\u{0}']),
+         ('\u{10b3}', ['\u{2d13}', '\u{0}', '\u{0}']), ('\u{10b4}', ['\u{2d14}', '\u{0}', '\u{0}']),
+         ('\u{10b5}', ['\u{2d15}', '\u{0}', '\u{0}']), ('\u{10b6}', ['\u{2d16}', '\u{0}', '\u{0}']),
+         ('\u{10b7}', ['\u{2d17}', '\u{0}', '\u{0}']), ('\u{10b8}', ['\u{2d18}', '\u{0}', '\u{0}']),
+         ('\u{10b9}', ['\u{2d19}', '\u{0}', '\u{0}']), ('\u{10ba}', ['\u{2d1a}', '\u{0}', '\u{0}']),
+         ('\u{10bb}', ['\u{2d1b}', '\u{0}', '\u{0}']), ('\u{10bc}', ['\u{2d1c}', '\u{0}', '\u{0}']),
+         ('\u{10bd}', ['\u{2d1d}', '\u{0}', '\u{0}']), ('\u{10be}', ['\u{2d1e}', '\u{0}', '\u{0}']),
+         ('\u{10bf}', ['\u{2d1f}', '\u{0}', '\u{0}']), ('\u{10c0}', ['\u{2d20}', '\u{0}', '\u{0}']),
+         ('\u{10c1}', ['\u{2d21}', '\u{0}', '\u{0}']), ('\u{10c2}', ['\u{2d22}', '\u{0}', '\u{0}']),
+         ('\u{10c3}', ['\u{2d23}', '\u{0}', '\u{0}']), ('\u{10c4}', ['\u{2d24}', '\u{0}', '\u{0}']),
+         ('\u{10c5}', ['\u{2d25}', '\u{0}', '\u{0}']), ('\u{10c7}', ['\u{2d27}', '\u{0}', '\u{0}']),
+         ('\u{10cd}', ['\u{2d2d}', '\u{0}', '\u{0}']), ('\u{13a0}', ['\u{ab70}', '\u{0}', '\u{0}']),
+         ('\u{13a1}', ['\u{ab71}', '\u{0}', '\u{0}']), ('\u{13a2}', ['\u{ab72}', '\u{0}', '\u{0}']),
+         ('\u{13a3}', ['\u{ab73}', '\u{0}', '\u{0}']), ('\u{13a4}', ['\u{ab74}', '\u{0}', '\u{0}']),
+         ('\u{13a5}', ['\u{ab75}', '\u{0}', '\u{0}']), ('\u{13a6}', ['\u{ab76}', '\u{0}', '\u{0}']),
+         ('\u{13a7}', ['\u{ab77}', '\u{0}', '\u{0}']), ('\u{13a8}', ['\u{ab78}', '\u{0}', '\u{0}']),
+         ('\u{13a9}', ['\u{ab79}', '\u{0}', '\u{0}']), ('\u{13aa}', ['\u{ab7a}', '\u{0}', '\u{0}']),
+         ('\u{13ab}', ['\u{ab7b}', '\u{0}', '\u{0}']), ('\u{13ac}', ['\u{ab7c}', '\u{0}', '\u{0}']),
+         ('\u{13ad}', ['\u{ab7d}', '\u{0}', '\u{0}']), ('\u{13ae}', ['\u{ab7e}', '\u{0}', '\u{0}']),
+         ('\u{13af}', ['\u{ab7f}', '\u{0}', '\u{0}']), ('\u{13b0}', ['\u{ab80}', '\u{0}', '\u{0}']),
+         ('\u{13b1}', ['\u{ab81}', '\u{0}', '\u{0}']), ('\u{13b2}', ['\u{ab82}', '\u{0}', '\u{0}']),
+         ('\u{13b3}', ['\u{ab83}', '\u{0}', '\u{0}']), ('\u{13b4}', ['\u{ab84}', '\u{0}', '\u{0}']),
+         ('\u{13b5}', ['\u{ab85}', '\u{0}', '\u{0}']), ('\u{13b6}', ['\u{ab86}', '\u{0}', '\u{0}']),
+         ('\u{13b7}', ['\u{ab87}', '\u{0}', '\u{0}']), ('\u{13b8}', ['\u{ab88}', '\u{0}', '\u{0}']),
+         ('\u{13b9}', ['\u{ab89}', '\u{0}', '\u{0}']), ('\u{13ba}', ['\u{ab8a}', '\u{0}', '\u{0}']),
+         ('\u{13bb}', ['\u{ab8b}', '\u{0}', '\u{0}']), ('\u{13bc}', ['\u{ab8c}', '\u{0}', '\u{0}']),
+         ('\u{13bd}', ['\u{ab8d}', '\u{0}', '\u{0}']), ('\u{13be}', ['\u{ab8e}', '\u{0}', '\u{0}']),
+         ('\u{13bf}', ['\u{ab8f}', '\u{0}', '\u{0}']), ('\u{13c0}', ['\u{ab90}', '\u{0}', '\u{0}']),
+         ('\u{13c1}', ['\u{ab91}', '\u{0}', '\u{0}']), ('\u{13c2}', ['\u{ab92}', '\u{0}', '\u{0}']),
+         ('\u{13c3}', ['\u{ab93}', '\u{0}', '\u{0}']), ('\u{13c4}', ['\u{ab94}', '\u{0}', '\u{0}']),
+         ('\u{13c5}', ['\u{ab95}', '\u{0}', '\u{0}']), ('\u{13c6}', ['\u{ab96}', '\u{0}', '\u{0}']),
+         ('\u{13c7}', ['\u{ab97}', '\u{0}', '\u{0}']), ('\u{13c8}', ['\u{ab98}', '\u{0}', '\u{0}']),
+         ('\u{13c9}', ['\u{ab99}', '\u{0}', '\u{0}']), ('\u{13ca}', ['\u{ab9a}', '\u{0}', '\u{0}']),
+         ('\u{13cb}', ['\u{ab9b}', '\u{0}', '\u{0}']), ('\u{13cc}', ['\u{ab9c}', '\u{0}', '\u{0}']),
+         ('\u{13cd}', ['\u{ab9d}', '\u{0}', '\u{0}']), ('\u{13ce}', ['\u{ab9e}', '\u{0}', '\u{0}']),
+         ('\u{13cf}', ['\u{ab9f}', '\u{0}', '\u{0}']), ('\u{13d0}', ['\u{aba0}', '\u{0}', '\u{0}']),
+         ('\u{13d1}', ['\u{aba1}', '\u{0}', '\u{0}']), ('\u{13d2}', ['\u{aba2}', '\u{0}', '\u{0}']),
+         ('\u{13d3}', ['\u{aba3}', '\u{0}', '\u{0}']), ('\u{13d4}', ['\u{aba4}', '\u{0}', '\u{0}']),
+         ('\u{13d5}', ['\u{aba5}', '\u{0}', '\u{0}']), ('\u{13d6}', ['\u{aba6}', '\u{0}', '\u{0}']),
+         ('\u{13d7}', ['\u{aba7}', '\u{0}', '\u{0}']), ('\u{13d8}', ['\u{aba8}', '\u{0}', '\u{0}']),
+         ('\u{13d9}', ['\u{aba9}', '\u{0}', '\u{0}']), ('\u{13da}', ['\u{abaa}', '\u{0}', '\u{0}']),
+         ('\u{13db}', ['\u{abab}', '\u{0}', '\u{0}']), ('\u{13dc}', ['\u{abac}', '\u{0}', '\u{0}']),
+         ('\u{13dd}', ['\u{abad}', '\u{0}', '\u{0}']), ('\u{13de}', ['\u{abae}', '\u{0}', '\u{0}']),
+         ('\u{13df}', ['\u{abaf}', '\u{0}', '\u{0}']), ('\u{13e0}', ['\u{abb0}', '\u{0}', '\u{0}']),
+         ('\u{13e1}', ['\u{abb1}', '\u{0}', '\u{0}']), ('\u{13e2}', ['\u{abb2}', '\u{0}', '\u{0}']),
+         ('\u{13e3}', ['\u{abb3}', '\u{0}', '\u{0}']), ('\u{13e4}', ['\u{abb4}', '\u{0}', '\u{0}']),
+         ('\u{13e5}', ['\u{abb5}', '\u{0}', '\u{0}']), ('\u{13e6}', ['\u{abb6}', '\u{0}', '\u{0}']),
+         ('\u{13e7}', ['\u{abb7}', '\u{0}', '\u{0}']), ('\u{13e8}', ['\u{abb8}', '\u{0}', '\u{0}']),
+         ('\u{13e9}', ['\u{abb9}', '\u{0}', '\u{0}']), ('\u{13ea}', ['\u{abba}', '\u{0}', '\u{0}']),
+         ('\u{13eb}', ['\u{abbb}', '\u{0}', '\u{0}']), ('\u{13ec}', ['\u{abbc}', '\u{0}', '\u{0}']),
+         ('\u{13ed}', ['\u{abbd}', '\u{0}', '\u{0}']), ('\u{13ee}', ['\u{abbe}', '\u{0}', '\u{0}']),
+         ('\u{13ef}', ['\u{abbf}', '\u{0}', '\u{0}']), ('\u{13f0}', ['\u{13f8}', '\u{0}', '\u{0}']),
+         ('\u{13f1}', ['\u{13f9}', '\u{0}', '\u{0}']), ('\u{13f2}', ['\u{13fa}', '\u{0}', '\u{0}']),
+         ('\u{13f3}', ['\u{13fb}', '\u{0}', '\u{0}']), ('\u{13f4}', ['\u{13fc}', '\u{0}', '\u{0}']),
+         ('\u{13f5}', ['\u{13fd}', '\u{0}', '\u{0}']), ('\u{1c90}', ['\u{10d0}', '\u{0}', '\u{0}']),
+         ('\u{1c91}', ['\u{10d1}', '\u{0}', '\u{0}']), ('\u{1c92}', ['\u{10d2}', '\u{0}', '\u{0}']),
+         ('\u{1c93}', ['\u{10d3}', '\u{0}', '\u{0}']), ('\u{1c94}', ['\u{10d4}', '\u{0}', '\u{0}']),
+         ('\u{1c95}', ['\u{10d5}', '\u{0}', '\u{0}']), ('\u{1c96}', ['\u{10d6}', '\u{0}', '\u{0}']),
+         ('\u{1c97}', ['\u{10d7}', '\u{0}', '\u{0}']), ('\u{1c98}', ['\u{10d8}', '\u{0}', '\u{0}']),
+         ('\u{1c99}', ['\u{10d9}', '\u{0}', '\u{0}']), ('\u{1c9a}', ['\u{10da}', '\u{0}', '\u{0}']),
+         ('\u{1c9b}', ['\u{10db}', '\u{0}', '\u{0}']), ('\u{1c9c}', ['\u{10dc}', '\u{0}', '\u{0}']),
+         ('\u{1c9d}', ['\u{10dd}', '\u{0}', '\u{0}']), ('\u{1c9e}', ['\u{10de}', '\u{0}', '\u{0}']),
+         ('\u{1c9f}', ['\u{10df}', '\u{0}', '\u{0}']), ('\u{1ca0}', ['\u{10e0}', '\u{0}', '\u{0}']),
+         ('\u{1ca1}', ['\u{10e1}', '\u{0}', '\u{0}']), ('\u{1ca2}', ['\u{10e2}', '\u{0}', '\u{0}']),
+         ('\u{1ca3}', ['\u{10e3}', '\u{0}', '\u{0}']), ('\u{1ca4}', ['\u{10e4}', '\u{0}', '\u{0}']),
+         ('\u{1ca5}', ['\u{10e5}', '\u{0}', '\u{0}']), ('\u{1ca6}', ['\u{10e6}', '\u{0}', '\u{0}']),
+         ('\u{1ca7}', ['\u{10e7}', '\u{0}', '\u{0}']), ('\u{1ca8}', ['\u{10e8}', '\u{0}', '\u{0}']),
+         ('\u{1ca9}', ['\u{10e9}', '\u{0}', '\u{0}']), ('\u{1caa}', ['\u{10ea}', '\u{0}', '\u{0}']),
+         ('\u{1cab}', ['\u{10eb}', '\u{0}', '\u{0}']), ('\u{1cac}', ['\u{10ec}', '\u{0}', '\u{0}']),
+         ('\u{1cad}', ['\u{10ed}', '\u{0}', '\u{0}']), ('\u{1cae}', ['\u{10ee}', '\u{0}', '\u{0}']),
+         ('\u{1caf}', ['\u{10ef}', '\u{0}', '\u{0}']), ('\u{1cb0}', ['\u{10f0}', '\u{0}', '\u{0}']),
+         ('\u{1cb1}', ['\u{10f1}', '\u{0}', '\u{0}']), ('\u{1cb2}', ['\u{10f2}', '\u{0}', '\u{0}']),
+         ('\u{1cb3}', ['\u{10f3}', '\u{0}', '\u{0}']), ('\u{1cb4}', ['\u{10f4}', '\u{0}', '\u{0}']),
+         ('\u{1cb5}', ['\u{10f5}', '\u{0}', '\u{0}']), ('\u{1cb6}', ['\u{10f6}', '\u{0}', '\u{0}']),
+         ('\u{1cb7}', ['\u{10f7}', '\u{0}', '\u{0}']), ('\u{1cb8}', ['\u{10f8}', '\u{0}', '\u{0}']),
+         ('\u{1cb9}', ['\u{10f9}', '\u{0}', '\u{0}']), ('\u{1cba}', ['\u{10fa}', '\u{0}', '\u{0}']),
+         ('\u{1cbd}', ['\u{10fd}', '\u{0}', '\u{0}']), ('\u{1cbe}', ['\u{10fe}', '\u{0}', '\u{0}']),
+         ('\u{1cbf}', ['\u{10ff}', '\u{0}', '\u{0}']), ('\u{1e00}', ['\u{1e01}', '\u{0}', '\u{0}']),
+         ('\u{1e02}', ['\u{1e03}', '\u{0}', '\u{0}']), ('\u{1e04}', ['\u{1e05}', '\u{0}', '\u{0}']),
+         ('\u{1e06}', ['\u{1e07}', '\u{0}', '\u{0}']), ('\u{1e08}', ['\u{1e09}', '\u{0}', '\u{0}']),
+         ('\u{1e0a}', ['\u{1e0b}', '\u{0}', '\u{0}']), ('\u{1e0c}', ['\u{1e0d}', '\u{0}', '\u{0}']),
+         ('\u{1e0e}', ['\u{1e0f}', '\u{0}', '\u{0}']), ('\u{1e10}', ['\u{1e11}', '\u{0}', '\u{0}']),
+         ('\u{1e12}', ['\u{1e13}', '\u{0}', '\u{0}']), ('\u{1e14}', ['\u{1e15}', '\u{0}', '\u{0}']),
+         ('\u{1e16}', ['\u{1e17}', '\u{0}', '\u{0}']), ('\u{1e18}', ['\u{1e19}', '\u{0}', '\u{0}']),
+         ('\u{1e1a}', ['\u{1e1b}', '\u{0}', '\u{0}']), ('\u{1e1c}', ['\u{1e1d}', '\u{0}', '\u{0}']),
+         ('\u{1e1e}', ['\u{1e1f}', '\u{0}', '\u{0}']), ('\u{1e20}', ['\u{1e21}', '\u{0}', '\u{0}']),
+         ('\u{1e22}', ['\u{1e23}', '\u{0}', '\u{0}']), ('\u{1e24}', ['\u{1e25}', '\u{0}', '\u{0}']),
+         ('\u{1e26}', ['\u{1e27}', '\u{0}', '\u{0}']), ('\u{1e28}', ['\u{1e29}', '\u{0}', '\u{0}']),
+         ('\u{1e2a}', ['\u{1e2b}', '\u{0}', '\u{0}']), ('\u{1e2c}', ['\u{1e2d}', '\u{0}', '\u{0}']),
+         ('\u{1e2e}', ['\u{1e2f}', '\u{0}', '\u{0}']), ('\u{1e30}', ['\u{1e31}', '\u{0}', '\u{0}']),
+         ('\u{1e32}', ['\u{1e33}', '\u{0}', '\u{0}']), ('\u{1e34}', ['\u{1e35}', '\u{0}', '\u{0}']),
+         ('\u{1e36}', ['\u{1e37}', '\u{0}', '\u{0}']), ('\u{1e38}', ['\u{1e39}', '\u{0}', '\u{0}']),
+         ('\u{1e3a}', ['\u{1e3b}', '\u{0}', '\u{0}']), ('\u{1e3c}', ['\u{1e3d}', '\u{0}', '\u{0}']),
+         ('\u{1e3e}', ['\u{1e3f}', '\u{0}', '\u{0}']), ('\u{1e40}', ['\u{1e41}', '\u{0}', '\u{0}']),
+         ('\u{1e42}', ['\u{1e43}', '\u{0}', '\u{0}']), ('\u{1e44}', ['\u{1e45}', '\u{0}', '\u{0}']),
+         ('\u{1e46}', ['\u{1e47}', '\u{0}', '\u{0}']), ('\u{1e48}', ['\u{1e49}', '\u{0}', '\u{0}']),
+         ('\u{1e4a}', ['\u{1e4b}', '\u{0}', '\u{0}']), ('\u{1e4c}', ['\u{1e4d}', '\u{0}', '\u{0}']),
+         ('\u{1e4e}', ['\u{1e4f}', '\u{0}', '\u{0}']), ('\u{1e50}', ['\u{1e51}', '\u{0}', '\u{0}']),
+         ('\u{1e52}', ['\u{1e53}', '\u{0}', '\u{0}']), ('\u{1e54}', ['\u{1e55}', '\u{0}', '\u{0}']),
+         ('\u{1e56}', ['\u{1e57}', '\u{0}', '\u{0}']), ('\u{1e58}', ['\u{1e59}', '\u{0}', '\u{0}']),
+         ('\u{1e5a}', ['\u{1e5b}', '\u{0}', '\u{0}']), ('\u{1e5c}', ['\u{1e5d}', '\u{0}', '\u{0}']),
+         ('\u{1e5e}', ['\u{1e5f}', '\u{0}', '\u{0}']), ('\u{1e60}', ['\u{1e61}', '\u{0}', '\u{0}']),
+         ('\u{1e62}', ['\u{1e63}', '\u{0}', '\u{0}']), ('\u{1e64}', ['\u{1e65}', '\u{0}', '\u{0}']),
+         ('\u{1e66}', ['\u{1e67}', '\u{0}', '\u{0}']), ('\u{1e68}', ['\u{1e69}', '\u{0}', '\u{0}']),
+         ('\u{1e6a}', ['\u{1e6b}', '\u{0}', '\u{0}']), ('\u{1e6c}', ['\u{1e6d}', '\u{0}', '\u{0}']),
+         ('\u{1e6e}', ['\u{1e6f}', '\u{0}', '\u{0}']), ('\u{1e70}', ['\u{1e71}', '\u{0}', '\u{0}']),
+         ('\u{1e72}', ['\u{1e73}', '\u{0}', '\u{0}']), ('\u{1e74}', ['\u{1e75}', '\u{0}', '\u{0}']),
+         ('\u{1e76}', ['\u{1e77}', '\u{0}', '\u{0}']), ('\u{1e78}', ['\u{1e79}', '\u{0}', '\u{0}']),
+         ('\u{1e7a}', ['\u{1e7b}', '\u{0}', '\u{0}']), ('\u{1e7c}', ['\u{1e7d}', '\u{0}', '\u{0}']),
+         ('\u{1e7e}', ['\u{1e7f}', '\u{0}', '\u{0}']), ('\u{1e80}', ['\u{1e81}', '\u{0}', '\u{0}']),
+         ('\u{1e82}', ['\u{1e83}', '\u{0}', '\u{0}']), ('\u{1e84}', ['\u{1e85}', '\u{0}', '\u{0}']),
+         ('\u{1e86}', ['\u{1e87}', '\u{0}', '\u{0}']), ('\u{1e88}', ['\u{1e89}', '\u{0}', '\u{0}']),
+         ('\u{1e8a}', ['\u{1e8b}', '\u{0}', '\u{0}']), ('\u{1e8c}', ['\u{1e8d}', '\u{0}', '\u{0}']),
+         ('\u{1e8e}', ['\u{1e8f}', '\u{0}', '\u{0}']), ('\u{1e90}', ['\u{1e91}', '\u{0}', '\u{0}']),
+         ('\u{1e92}', ['\u{1e93}', '\u{0}', '\u{0}']), ('\u{1e94}', ['\u{1e95}', '\u{0}', '\u{0}']),
+         ('\u{1e9e}', ['\u{df}', '\u{0}', '\u{0}']), ('\u{1ea0}', ['\u{1ea1}', '\u{0}', '\u{0}']),
+         ('\u{1ea2}', ['\u{1ea3}', '\u{0}', '\u{0}']), ('\u{1ea4}', ['\u{1ea5}', '\u{0}', '\u{0}']),
+         ('\u{1ea6}', ['\u{1ea7}', '\u{0}', '\u{0}']), ('\u{1ea8}', ['\u{1ea9}', '\u{0}', '\u{0}']),
+         ('\u{1eaa}', ['\u{1eab}', '\u{0}', '\u{0}']), ('\u{1eac}', ['\u{1ead}', '\u{0}', '\u{0}']),
+         ('\u{1eae}', ['\u{1eaf}', '\u{0}', '\u{0}']), ('\u{1eb0}', ['\u{1eb1}', '\u{0}', '\u{0}']),
+         ('\u{1eb2}', ['\u{1eb3}', '\u{0}', '\u{0}']), ('\u{1eb4}', ['\u{1eb5}', '\u{0}', '\u{0}']),
+         ('\u{1eb6}', ['\u{1eb7}', '\u{0}', '\u{0}']), ('\u{1eb8}', ['\u{1eb9}', '\u{0}', '\u{0}']),
+         ('\u{1eba}', ['\u{1ebb}', '\u{0}', '\u{0}']), ('\u{1ebc}', ['\u{1ebd}', '\u{0}', '\u{0}']),
+         ('\u{1ebe}', ['\u{1ebf}', '\u{0}', '\u{0}']), ('\u{1ec0}', ['\u{1ec1}', '\u{0}', '\u{0}']),
+         ('\u{1ec2}', ['\u{1ec3}', '\u{0}', '\u{0}']), ('\u{1ec4}', ['\u{1ec5}', '\u{0}', '\u{0}']),
+         ('\u{1ec6}', ['\u{1ec7}', '\u{0}', '\u{0}']), ('\u{1ec8}', ['\u{1ec9}', '\u{0}', '\u{0}']),
+         ('\u{1eca}', ['\u{1ecb}', '\u{0}', '\u{0}']), ('\u{1ecc}', ['\u{1ecd}', '\u{0}', '\u{0}']),
+         ('\u{1ece}', ['\u{1ecf}', '\u{0}', '\u{0}']), ('\u{1ed0}', ['\u{1ed1}', '\u{0}', '\u{0}']),
+         ('\u{1ed2}', ['\u{1ed3}', '\u{0}', '\u{0}']), ('\u{1ed4}', ['\u{1ed5}', '\u{0}', '\u{0}']),
+         ('\u{1ed6}', ['\u{1ed7}', '\u{0}', '\u{0}']), ('\u{1ed8}', ['\u{1ed9}', '\u{0}', '\u{0}']),
+         ('\u{1eda}', ['\u{1edb}', '\u{0}', '\u{0}']), ('\u{1edc}', ['\u{1edd}', '\u{0}', '\u{0}']),
+         ('\u{1ede}', ['\u{1edf}', '\u{0}', '\u{0}']), ('\u{1ee0}', ['\u{1ee1}', '\u{0}', '\u{0}']),
+         ('\u{1ee2}', ['\u{1ee3}', '\u{0}', '\u{0}']), ('\u{1ee4}', ['\u{1ee5}', '\u{0}', '\u{0}']),
+         ('\u{1ee6}', ['\u{1ee7}', '\u{0}', '\u{0}']), ('\u{1ee8}', ['\u{1ee9}', '\u{0}', '\u{0}']),
+         ('\u{1eea}', ['\u{1eeb}', '\u{0}', '\u{0}']), ('\u{1eec}', ['\u{1eed}', '\u{0}', '\u{0}']),
+         ('\u{1eee}', ['\u{1eef}', '\u{0}', '\u{0}']), ('\u{1ef0}', ['\u{1ef1}', '\u{0}', '\u{0}']),
+         ('\u{1ef2}', ['\u{1ef3}', '\u{0}', '\u{0}']), ('\u{1ef4}', ['\u{1ef5}', '\u{0}', '\u{0}']),
+         ('\u{1ef6}', ['\u{1ef7}', '\u{0}', '\u{0}']), ('\u{1ef8}', ['\u{1ef9}', '\u{0}', '\u{0}']),
+         ('\u{1efa}', ['\u{1efb}', '\u{0}', '\u{0}']), ('\u{1efc}', ['\u{1efd}', '\u{0}', '\u{0}']),
+         ('\u{1efe}', ['\u{1eff}', '\u{0}', '\u{0}']), ('\u{1f08}', ['\u{1f00}', '\u{0}', '\u{0}']),
+         ('\u{1f09}', ['\u{1f01}', '\u{0}', '\u{0}']), ('\u{1f0a}', ['\u{1f02}', '\u{0}', '\u{0}']),
+         ('\u{1f0b}', ['\u{1f03}', '\u{0}', '\u{0}']), ('\u{1f0c}', ['\u{1f04}', '\u{0}', '\u{0}']),
+         ('\u{1f0d}', ['\u{1f05}', '\u{0}', '\u{0}']), ('\u{1f0e}', ['\u{1f06}', '\u{0}', '\u{0}']),
+         ('\u{1f0f}', ['\u{1f07}', '\u{0}', '\u{0}']), ('\u{1f18}', ['\u{1f10}', '\u{0}', '\u{0}']),
+         ('\u{1f19}', ['\u{1f11}', '\u{0}', '\u{0}']), ('\u{1f1a}', ['\u{1f12}', '\u{0}', '\u{0}']),
+         ('\u{1f1b}', ['\u{1f13}', '\u{0}', '\u{0}']), ('\u{1f1c}', ['\u{1f14}', '\u{0}', '\u{0}']),
+         ('\u{1f1d}', ['\u{1f15}', '\u{0}', '\u{0}']), ('\u{1f28}', ['\u{1f20}', '\u{0}', '\u{0}']),
+         ('\u{1f29}', ['\u{1f21}', '\u{0}', '\u{0}']), ('\u{1f2a}', ['\u{1f22}', '\u{0}', '\u{0}']),
+         ('\u{1f2b}', ['\u{1f23}', '\u{0}', '\u{0}']), ('\u{1f2c}', ['\u{1f24}', '\u{0}', '\u{0}']),
+         ('\u{1f2d}', ['\u{1f25}', '\u{0}', '\u{0}']), ('\u{1f2e}', ['\u{1f26}', '\u{0}', '\u{0}']),
+         ('\u{1f2f}', ['\u{1f27}', '\u{0}', '\u{0}']), ('\u{1f38}', ['\u{1f30}', '\u{0}', '\u{0}']),
+         ('\u{1f39}', ['\u{1f31}', '\u{0}', '\u{0}']), ('\u{1f3a}', ['\u{1f32}', '\u{0}', '\u{0}']),
+         ('\u{1f3b}', ['\u{1f33}', '\u{0}', '\u{0}']), ('\u{1f3c}', ['\u{1f34}', '\u{0}', '\u{0}']),
+         ('\u{1f3d}', ['\u{1f35}', '\u{0}', '\u{0}']), ('\u{1f3e}', ['\u{1f36}', '\u{0}', '\u{0}']),
+         ('\u{1f3f}', ['\u{1f37}', '\u{0}', '\u{0}']), ('\u{1f48}', ['\u{1f40}', '\u{0}', '\u{0}']),
+         ('\u{1f49}', ['\u{1f41}', '\u{0}', '\u{0}']), ('\u{1f4a}', ['\u{1f42}', '\u{0}', '\u{0}']),
+         ('\u{1f4b}', ['\u{1f43}', '\u{0}', '\u{0}']), ('\u{1f4c}', ['\u{1f44}', '\u{0}', '\u{0}']),
+         ('\u{1f4d}', ['\u{1f45}', '\u{0}', '\u{0}']), ('\u{1f59}', ['\u{1f51}', '\u{0}', '\u{0}']),
+         ('\u{1f5b}', ['\u{1f53}', '\u{0}', '\u{0}']), ('\u{1f5d}', ['\u{1f55}', '\u{0}', '\u{0}']),
+         ('\u{1f5f}', ['\u{1f57}', '\u{0}', '\u{0}']), ('\u{1f68}', ['\u{1f60}', '\u{0}', '\u{0}']),
+         ('\u{1f69}', ['\u{1f61}', '\u{0}', '\u{0}']), ('\u{1f6a}', ['\u{1f62}', '\u{0}', '\u{0}']),
+         ('\u{1f6b}', ['\u{1f63}', '\u{0}', '\u{0}']), ('\u{1f6c}', ['\u{1f64}', '\u{0}', '\u{0}']),
+         ('\u{1f6d}', ['\u{1f65}', '\u{0}', '\u{0}']), ('\u{1f6e}', ['\u{1f66}', '\u{0}', '\u{0}']),
+         ('\u{1f6f}', ['\u{1f67}', '\u{0}', '\u{0}']), ('\u{1f88}', ['\u{1f80}', '\u{0}', '\u{0}']),
+         ('\u{1f89}', ['\u{1f81}', '\u{0}', '\u{0}']), ('\u{1f8a}', ['\u{1f82}', '\u{0}', '\u{0}']),
+         ('\u{1f8b}', ['\u{1f83}', '\u{0}', '\u{0}']), ('\u{1f8c}', ['\u{1f84}', '\u{0}', '\u{0}']),
+         ('\u{1f8d}', ['\u{1f85}', '\u{0}', '\u{0}']), ('\u{1f8e}', ['\u{1f86}', '\u{0}', '\u{0}']),
+         ('\u{1f8f}', ['\u{1f87}', '\u{0}', '\u{0}']), ('\u{1f98}', ['\u{1f90}', '\u{0}', '\u{0}']),
+         ('\u{1f99}', ['\u{1f91}', '\u{0}', '\u{0}']), ('\u{1f9a}', ['\u{1f92}', '\u{0}', '\u{0}']),
+         ('\u{1f9b}', ['\u{1f93}', '\u{0}', '\u{0}']), ('\u{1f9c}', ['\u{1f94}', '\u{0}', '\u{0}']),
+         ('\u{1f9d}', ['\u{1f95}', '\u{0}', '\u{0}']), ('\u{1f9e}', ['\u{1f96}', '\u{0}', '\u{0}']),
+         ('\u{1f9f}', ['\u{1f97}', '\u{0}', '\u{0}']), ('\u{1fa8}', ['\u{1fa0}', '\u{0}', '\u{0}']),
+         ('\u{1fa9}', ['\u{1fa1}', '\u{0}', '\u{0}']), ('\u{1faa}', ['\u{1fa2}', '\u{0}', '\u{0}']),
+         ('\u{1fab}', ['\u{1fa3}', '\u{0}', '\u{0}']), ('\u{1fac}', ['\u{1fa4}', '\u{0}', '\u{0}']),
+         ('\u{1fad}', ['\u{1fa5}', '\u{0}', '\u{0}']), ('\u{1fae}', ['\u{1fa6}', '\u{0}', '\u{0}']),
+         ('\u{1faf}', ['\u{1fa7}', '\u{0}', '\u{0}']), ('\u{1fb8}', ['\u{1fb0}', '\u{0}', '\u{0}']),
+         ('\u{1fb9}', ['\u{1fb1}', '\u{0}', '\u{0}']), ('\u{1fba}', ['\u{1f70}', '\u{0}', '\u{0}']),
+         ('\u{1fbb}', ['\u{1f71}', '\u{0}', '\u{0}']), ('\u{1fbc}', ['\u{1fb3}', '\u{0}', '\u{0}']),
+         ('\u{1fc8}', ['\u{1f72}', '\u{0}', '\u{0}']), ('\u{1fc9}', ['\u{1f73}', '\u{0}', '\u{0}']),
+         ('\u{1fca}', ['\u{1f74}', '\u{0}', '\u{0}']), ('\u{1fcb}', ['\u{1f75}', '\u{0}', '\u{0}']),
+         ('\u{1fcc}', ['\u{1fc3}', '\u{0}', '\u{0}']), ('\u{1fd8}', ['\u{1fd0}', '\u{0}', '\u{0}']),
+         ('\u{1fd9}', ['\u{1fd1}', '\u{0}', '\u{0}']), ('\u{1fda}', ['\u{1f76}', '\u{0}', '\u{0}']),
+         ('\u{1fdb}', ['\u{1f77}', '\u{0}', '\u{0}']), ('\u{1fe8}', ['\u{1fe0}', '\u{0}', '\u{0}']),
+         ('\u{1fe9}', ['\u{1fe1}', '\u{0}', '\u{0}']), ('\u{1fea}', ['\u{1f7a}', '\u{0}', '\u{0}']),
+         ('\u{1feb}', ['\u{1f7b}', '\u{0}', '\u{0}']), ('\u{1fec}', ['\u{1fe5}', '\u{0}', '\u{0}']),
+         ('\u{1ff8}', ['\u{1f78}', '\u{0}', '\u{0}']), ('\u{1ff9}', ['\u{1f79}', '\u{0}', '\u{0}']),
+         ('\u{1ffa}', ['\u{1f7c}', '\u{0}', '\u{0}']), ('\u{1ffb}', ['\u{1f7d}', '\u{0}', '\u{0}']),
+         ('\u{1ffc}', ['\u{1ff3}', '\u{0}', '\u{0}']), ('\u{2126}', ['\u{3c9}', '\u{0}', '\u{0}']),
+         ('\u{212a}', ['k', '\u{0}', '\u{0}']), ('\u{212b}', ['\u{e5}', '\u{0}', '\u{0}']),
+         ('\u{2132}', ['\u{214e}', '\u{0}', '\u{0}']), ('\u{2160}', ['\u{2170}', '\u{0}', '\u{0}']),
+         ('\u{2161}', ['\u{2171}', '\u{0}', '\u{0}']), ('\u{2162}', ['\u{2172}', '\u{0}', '\u{0}']),
+         ('\u{2163}', ['\u{2173}', '\u{0}', '\u{0}']), ('\u{2164}', ['\u{2174}', '\u{0}', '\u{0}']),
+         ('\u{2165}', ['\u{2175}', '\u{0}', '\u{0}']), ('\u{2166}', ['\u{2176}', '\u{0}', '\u{0}']),
+         ('\u{2167}', ['\u{2177}', '\u{0}', '\u{0}']), ('\u{2168}', ['\u{2178}', '\u{0}', '\u{0}']),
+         ('\u{2169}', ['\u{2179}', '\u{0}', '\u{0}']), ('\u{216a}', ['\u{217a}', '\u{0}', '\u{0}']),
+         ('\u{216b}', ['\u{217b}', '\u{0}', '\u{0}']), ('\u{216c}', ['\u{217c}', '\u{0}', '\u{0}']),
+         ('\u{216d}', ['\u{217d}', '\u{0}', '\u{0}']), ('\u{216e}', ['\u{217e}', '\u{0}', '\u{0}']),
+         ('\u{216f}', ['\u{217f}', '\u{0}', '\u{0}']), ('\u{2183}', ['\u{2184}', '\u{0}', '\u{0}']),
+         ('\u{24b6}', ['\u{24d0}', '\u{0}', '\u{0}']), ('\u{24b7}', ['\u{24d1}', '\u{0}', '\u{0}']),
+         ('\u{24b8}', ['\u{24d2}', '\u{0}', '\u{0}']), ('\u{24b9}', ['\u{24d3}', '\u{0}', '\u{0}']),
+         ('\u{24ba}', ['\u{24d4}', '\u{0}', '\u{0}']), ('\u{24bb}', ['\u{24d5}', '\u{0}', '\u{0}']),
+         ('\u{24bc}', ['\u{24d6}', '\u{0}', '\u{0}']), ('\u{24bd}', ['\u{24d7}', '\u{0}', '\u{0}']),
+         ('\u{24be}', ['\u{24d8}', '\u{0}', '\u{0}']), ('\u{24bf}', ['\u{24d9}', '\u{0}', '\u{0}']),
+         ('\u{24c0}', ['\u{24da}', '\u{0}', '\u{0}']), ('\u{24c1}', ['\u{24db}', '\u{0}', '\u{0}']),
+         ('\u{24c2}', ['\u{24dc}', '\u{0}', '\u{0}']), ('\u{24c3}', ['\u{24dd}', '\u{0}', '\u{0}']),
+         ('\u{24c4}', ['\u{24de}', '\u{0}', '\u{0}']), ('\u{24c5}', ['\u{24df}', '\u{0}', '\u{0}']),
+         ('\u{24c6}', ['\u{24e0}', '\u{0}', '\u{0}']), ('\u{24c7}', ['\u{24e1}', '\u{0}', '\u{0}']),
+         ('\u{24c8}', ['\u{24e2}', '\u{0}', '\u{0}']), ('\u{24c9}', ['\u{24e3}', '\u{0}', '\u{0}']),
+         ('\u{24ca}', ['\u{24e4}', '\u{0}', '\u{0}']), ('\u{24cb}', ['\u{24e5}', '\u{0}', '\u{0}']),
+         ('\u{24cc}', ['\u{24e6}', '\u{0}', '\u{0}']), ('\u{24cd}', ['\u{24e7}', '\u{0}', '\u{0}']),
+         ('\u{24ce}', ['\u{24e8}', '\u{0}', '\u{0}']), ('\u{24cf}', ['\u{24e9}', '\u{0}', '\u{0}']),
+         ('\u{2c00}', ['\u{2c30}', '\u{0}', '\u{0}']), ('\u{2c01}', ['\u{2c31}', '\u{0}', '\u{0}']),
+         ('\u{2c02}', ['\u{2c32}', '\u{0}', '\u{0}']), ('\u{2c03}', ['\u{2c33}', '\u{0}', '\u{0}']),
+         ('\u{2c04}', ['\u{2c34}', '\u{0}', '\u{0}']), ('\u{2c05}', ['\u{2c35}', '\u{0}', '\u{0}']),
+         ('\u{2c06}', ['\u{2c36}', '\u{0}', '\u{0}']), ('\u{2c07}', ['\u{2c37}', '\u{0}', '\u{0}']),
+         ('\u{2c08}', ['\u{2c38}', '\u{0}', '\u{0}']), ('\u{2c09}', ['\u{2c39}', '\u{0}', '\u{0}']),
+         ('\u{2c0a}', ['\u{2c3a}', '\u{0}', '\u{0}']), ('\u{2c0b}', ['\u{2c3b}', '\u{0}', '\u{0}']),
+         ('\u{2c0c}', ['\u{2c3c}', '\u{0}', '\u{0}']), ('\u{2c0d}', ['\u{2c3d}', '\u{0}', '\u{0}']),
+         ('\u{2c0e}', ['\u{2c3e}', '\u{0}', '\u{0}']), ('\u{2c0f}', ['\u{2c3f}', '\u{0}', '\u{0}']),
+         ('\u{2c10}', ['\u{2c40}', '\u{0}', '\u{0}']), ('\u{2c11}', ['\u{2c41}', '\u{0}', '\u{0}']),
+         ('\u{2c12}', ['\u{2c42}', '\u{0}', '\u{0}']), ('\u{2c13}', ['\u{2c43}', '\u{0}', '\u{0}']),
+         ('\u{2c14}', ['\u{2c44}', '\u{0}', '\u{0}']), ('\u{2c15}', ['\u{2c45}', '\u{0}', '\u{0}']),
+         ('\u{2c16}', ['\u{2c46}', '\u{0}', '\u{0}']), ('\u{2c17}', ['\u{2c47}', '\u{0}', '\u{0}']),
+         ('\u{2c18}', ['\u{2c48}', '\u{0}', '\u{0}']), ('\u{2c19}', ['\u{2c49}', '\u{0}', '\u{0}']),
+         ('\u{2c1a}', ['\u{2c4a}', '\u{0}', '\u{0}']), ('\u{2c1b}', ['\u{2c4b}', '\u{0}', '\u{0}']),
+         ('\u{2c1c}', ['\u{2c4c}', '\u{0}', '\u{0}']), ('\u{2c1d}', ['\u{2c4d}', '\u{0}', '\u{0}']),
+         ('\u{2c1e}', ['\u{2c4e}', '\u{0}', '\u{0}']), ('\u{2c1f}', ['\u{2c4f}', '\u{0}', '\u{0}']),
+         ('\u{2c20}', ['\u{2c50}', '\u{0}', '\u{0}']), ('\u{2c21}', ['\u{2c51}', '\u{0}', '\u{0}']),
+         ('\u{2c22}', ['\u{2c52}', '\u{0}', '\u{0}']), ('\u{2c23}', ['\u{2c53}', '\u{0}', '\u{0}']),
+         ('\u{2c24}', ['\u{2c54}', '\u{0}', '\u{0}']), ('\u{2c25}', ['\u{2c55}', '\u{0}', '\u{0}']),
+         ('\u{2c26}', ['\u{2c56}', '\u{0}', '\u{0}']), ('\u{2c27}', ['\u{2c57}', '\u{0}', '\u{0}']),
+         ('\u{2c28}', ['\u{2c58}', '\u{0}', '\u{0}']), ('\u{2c29}', ['\u{2c59}', '\u{0}', '\u{0}']),
+         ('\u{2c2a}', ['\u{2c5a}', '\u{0}', '\u{0}']), ('\u{2c2b}', ['\u{2c5b}', '\u{0}', '\u{0}']),
+         ('\u{2c2c}', ['\u{2c5c}', '\u{0}', '\u{0}']), ('\u{2c2d}', ['\u{2c5d}', '\u{0}', '\u{0}']),
+         ('\u{2c2e}', ['\u{2c5e}', '\u{0}', '\u{0}']), ('\u{2c60}', ['\u{2c61}', '\u{0}', '\u{0}']),
+         ('\u{2c62}', ['\u{26b}', '\u{0}', '\u{0}']), ('\u{2c63}', ['\u{1d7d}', '\u{0}', '\u{0}']),
+         ('\u{2c64}', ['\u{27d}', '\u{0}', '\u{0}']), ('\u{2c67}', ['\u{2c68}', '\u{0}', '\u{0}']),
+         ('\u{2c69}', ['\u{2c6a}', '\u{0}', '\u{0}']), ('\u{2c6b}', ['\u{2c6c}', '\u{0}', '\u{0}']),
+         ('\u{2c6d}', ['\u{251}', '\u{0}', '\u{0}']), ('\u{2c6e}', ['\u{271}', '\u{0}', '\u{0}']),
+         ('\u{2c6f}', ['\u{250}', '\u{0}', '\u{0}']), ('\u{2c70}', ['\u{252}', '\u{0}', '\u{0}']),
+         ('\u{2c72}', ['\u{2c73}', '\u{0}', '\u{0}']), ('\u{2c75}', ['\u{2c76}', '\u{0}', '\u{0}']),
+         ('\u{2c7e}', ['\u{23f}', '\u{0}', '\u{0}']), ('\u{2c7f}', ['\u{240}', '\u{0}', '\u{0}']),
+         ('\u{2c80}', ['\u{2c81}', '\u{0}', '\u{0}']), ('\u{2c82}', ['\u{2c83}', '\u{0}', '\u{0}']),
+         ('\u{2c84}', ['\u{2c85}', '\u{0}', '\u{0}']), ('\u{2c86}', ['\u{2c87}', '\u{0}', '\u{0}']),
+         ('\u{2c88}', ['\u{2c89}', '\u{0}', '\u{0}']), ('\u{2c8a}', ['\u{2c8b}', '\u{0}', '\u{0}']),
+         ('\u{2c8c}', ['\u{2c8d}', '\u{0}', '\u{0}']), ('\u{2c8e}', ['\u{2c8f}', '\u{0}', '\u{0}']),
+         ('\u{2c90}', ['\u{2c91}', '\u{0}', '\u{0}']), ('\u{2c92}', ['\u{2c93}', '\u{0}', '\u{0}']),
+         ('\u{2c94}', ['\u{2c95}', '\u{0}', '\u{0}']), ('\u{2c96}', ['\u{2c97}', '\u{0}', '\u{0}']),
+         ('\u{2c98}', ['\u{2c99}', '\u{0}', '\u{0}']), ('\u{2c9a}', ['\u{2c9b}', '\u{0}', '\u{0}']),
+         ('\u{2c9c}', ['\u{2c9d}', '\u{0}', '\u{0}']), ('\u{2c9e}', ['\u{2c9f}', '\u{0}', '\u{0}']),
+         ('\u{2ca0}', ['\u{2ca1}', '\u{0}', '\u{0}']), ('\u{2ca2}', ['\u{2ca3}', '\u{0}', '\u{0}']),
+         ('\u{2ca4}', ['\u{2ca5}', '\u{0}', '\u{0}']), ('\u{2ca6}', ['\u{2ca7}', '\u{0}', '\u{0}']),
+         ('\u{2ca8}', ['\u{2ca9}', '\u{0}', '\u{0}']), ('\u{2caa}', ['\u{2cab}', '\u{0}', '\u{0}']),
+         ('\u{2cac}', ['\u{2cad}', '\u{0}', '\u{0}']), ('\u{2cae}', ['\u{2caf}', '\u{0}', '\u{0}']),
+         ('\u{2cb0}', ['\u{2cb1}', '\u{0}', '\u{0}']), ('\u{2cb2}', ['\u{2cb3}', '\u{0}', '\u{0}']),
+         ('\u{2cb4}', ['\u{2cb5}', '\u{0}', '\u{0}']), ('\u{2cb6}', ['\u{2cb7}', '\u{0}', '\u{0}']),
+         ('\u{2cb8}', ['\u{2cb9}', '\u{0}', '\u{0}']), ('\u{2cba}', ['\u{2cbb}', '\u{0}', '\u{0}']),
+         ('\u{2cbc}', ['\u{2cbd}', '\u{0}', '\u{0}']), ('\u{2cbe}', ['\u{2cbf}', '\u{0}', '\u{0}']),
+         ('\u{2cc0}', ['\u{2cc1}', '\u{0}', '\u{0}']), ('\u{2cc2}', ['\u{2cc3}', '\u{0}', '\u{0}']),
+         ('\u{2cc4}', ['\u{2cc5}', '\u{0}', '\u{0}']), ('\u{2cc6}', ['\u{2cc7}', '\u{0}', '\u{0}']),
+         ('\u{2cc8}', ['\u{2cc9}', '\u{0}', '\u{0}']), ('\u{2cca}', ['\u{2ccb}', '\u{0}', '\u{0}']),
+         ('\u{2ccc}', ['\u{2ccd}', '\u{0}', '\u{0}']), ('\u{2cce}', ['\u{2ccf}', '\u{0}', '\u{0}']),
+         ('\u{2cd0}', ['\u{2cd1}', '\u{0}', '\u{0}']), ('\u{2cd2}', ['\u{2cd3}', '\u{0}', '\u{0}']),
+         ('\u{2cd4}', ['\u{2cd5}', '\u{0}', '\u{0}']), ('\u{2cd6}', ['\u{2cd7}', '\u{0}', '\u{0}']),
+         ('\u{2cd8}', ['\u{2cd9}', '\u{0}', '\u{0}']), ('\u{2cda}', ['\u{2cdb}', '\u{0}', '\u{0}']),
+         ('\u{2cdc}', ['\u{2cdd}', '\u{0}', '\u{0}']), ('\u{2cde}', ['\u{2cdf}', '\u{0}', '\u{0}']),
+         ('\u{2ce0}', ['\u{2ce1}', '\u{0}', '\u{0}']), ('\u{2ce2}', ['\u{2ce3}', '\u{0}', '\u{0}']),
+         ('\u{2ceb}', ['\u{2cec}', '\u{0}', '\u{0}']), ('\u{2ced}', ['\u{2cee}', '\u{0}', '\u{0}']),
+         ('\u{2cf2}', ['\u{2cf3}', '\u{0}', '\u{0}']), ('\u{a640}', ['\u{a641}', '\u{0}', '\u{0}']),
+         ('\u{a642}', ['\u{a643}', '\u{0}', '\u{0}']), ('\u{a644}', ['\u{a645}', '\u{0}', '\u{0}']),
+         ('\u{a646}', ['\u{a647}', '\u{0}', '\u{0}']), ('\u{a648}', ['\u{a649}', '\u{0}', '\u{0}']),
+         ('\u{a64a}', ['\u{a64b}', '\u{0}', '\u{0}']), ('\u{a64c}', ['\u{a64d}', '\u{0}', '\u{0}']),
+         ('\u{a64e}', ['\u{a64f}', '\u{0}', '\u{0}']), ('\u{a650}', ['\u{a651}', '\u{0}', '\u{0}']),
+         ('\u{a652}', ['\u{a653}', '\u{0}', '\u{0}']), ('\u{a654}', ['\u{a655}', '\u{0}', '\u{0}']),
+         ('\u{a656}', ['\u{a657}', '\u{0}', '\u{0}']), ('\u{a658}', ['\u{a659}', '\u{0}', '\u{0}']),
+         ('\u{a65a}', ['\u{a65b}', '\u{0}', '\u{0}']), ('\u{a65c}', ['\u{a65d}', '\u{0}', '\u{0}']),
+         ('\u{a65e}', ['\u{a65f}', '\u{0}', '\u{0}']), ('\u{a660}', ['\u{a661}', '\u{0}', '\u{0}']),
+         ('\u{a662}', ['\u{a663}', '\u{0}', '\u{0}']), ('\u{a664}', ['\u{a665}', '\u{0}', '\u{0}']),
+         ('\u{a666}', ['\u{a667}', '\u{0}', '\u{0}']), ('\u{a668}', ['\u{a669}', '\u{0}', '\u{0}']),
+         ('\u{a66a}', ['\u{a66b}', '\u{0}', '\u{0}']), ('\u{a66c}', ['\u{a66d}', '\u{0}', '\u{0}']),
+         ('\u{a680}', ['\u{a681}', '\u{0}', '\u{0}']), ('\u{a682}', ['\u{a683}', '\u{0}', '\u{0}']),
+         ('\u{a684}', ['\u{a685}', '\u{0}', '\u{0}']), ('\u{a686}', ['\u{a687}', '\u{0}', '\u{0}']),
+         ('\u{a688}', ['\u{a689}', '\u{0}', '\u{0}']), ('\u{a68a}', ['\u{a68b}', '\u{0}', '\u{0}']),
+         ('\u{a68c}', ['\u{a68d}', '\u{0}', '\u{0}']), ('\u{a68e}', ['\u{a68f}', '\u{0}', '\u{0}']),
+         ('\u{a690}', ['\u{a691}', '\u{0}', '\u{0}']), ('\u{a692}', ['\u{a693}', '\u{0}', '\u{0}']),
+         ('\u{a694}', ['\u{a695}', '\u{0}', '\u{0}']), ('\u{a696}', ['\u{a697}', '\u{0}', '\u{0}']),
+         ('\u{a698}', ['\u{a699}', '\u{0}', '\u{0}']), ('\u{a69a}', ['\u{a69b}', '\u{0}', '\u{0}']),
+         ('\u{a722}', ['\u{a723}', '\u{0}', '\u{0}']), ('\u{a724}', ['\u{a725}', '\u{0}', '\u{0}']),
+         ('\u{a726}', ['\u{a727}', '\u{0}', '\u{0}']), ('\u{a728}', ['\u{a729}', '\u{0}', '\u{0}']),
+         ('\u{a72a}', ['\u{a72b}', '\u{0}', '\u{0}']), ('\u{a72c}', ['\u{a72d}', '\u{0}', '\u{0}']),
+         ('\u{a72e}', ['\u{a72f}', '\u{0}', '\u{0}']), ('\u{a732}', ['\u{a733}', '\u{0}', '\u{0}']),
+         ('\u{a734}', ['\u{a735}', '\u{0}', '\u{0}']), ('\u{a736}', ['\u{a737}', '\u{0}', '\u{0}']),
+         ('\u{a738}', ['\u{a739}', '\u{0}', '\u{0}']), ('\u{a73a}', ['\u{a73b}', '\u{0}', '\u{0}']),
+         ('\u{a73c}', ['\u{a73d}', '\u{0}', '\u{0}']), ('\u{a73e}', ['\u{a73f}', '\u{0}', '\u{0}']),
+         ('\u{a740}', ['\u{a741}', '\u{0}', '\u{0}']), ('\u{a742}', ['\u{a743}', '\u{0}', '\u{0}']),
+         ('\u{a744}', ['\u{a745}', '\u{0}', '\u{0}']), ('\u{a746}', ['\u{a747}', '\u{0}', '\u{0}']),
+         ('\u{a748}', ['\u{a749}', '\u{0}', '\u{0}']), ('\u{a74a}', ['\u{a74b}', '\u{0}', '\u{0}']),
+         ('\u{a74c}', ['\u{a74d}', '\u{0}', '\u{0}']), ('\u{a74e}', ['\u{a74f}', '\u{0}', '\u{0}']),
+         ('\u{a750}', ['\u{a751}', '\u{0}', '\u{0}']), ('\u{a752}', ['\u{a753}', '\u{0}', '\u{0}']),
+         ('\u{a754}', ['\u{a755}', '\u{0}', '\u{0}']), ('\u{a756}', ['\u{a757}', '\u{0}', '\u{0}']),
+         ('\u{a758}', ['\u{a759}', '\u{0}', '\u{0}']), ('\u{a75a}', ['\u{a75b}', '\u{0}', '\u{0}']),
+         ('\u{a75c}', ['\u{a75d}', '\u{0}', '\u{0}']), ('\u{a75e}', ['\u{a75f}', '\u{0}', '\u{0}']),
+         ('\u{a760}', ['\u{a761}', '\u{0}', '\u{0}']), ('\u{a762}', ['\u{a763}', '\u{0}', '\u{0}']),
+         ('\u{a764}', ['\u{a765}', '\u{0}', '\u{0}']), ('\u{a766}', ['\u{a767}', '\u{0}', '\u{0}']),
+         ('\u{a768}', ['\u{a769}', '\u{0}', '\u{0}']), ('\u{a76a}', ['\u{a76b}', '\u{0}', '\u{0}']),
+         ('\u{a76c}', ['\u{a76d}', '\u{0}', '\u{0}']), ('\u{a76e}', ['\u{a76f}', '\u{0}', '\u{0}']),
+         ('\u{a779}', ['\u{a77a}', '\u{0}', '\u{0}']), ('\u{a77b}', ['\u{a77c}', '\u{0}', '\u{0}']),
+         ('\u{a77d}', ['\u{1d79}', '\u{0}', '\u{0}']), ('\u{a77e}', ['\u{a77f}', '\u{0}', '\u{0}']),
+         ('\u{a780}', ['\u{a781}', '\u{0}', '\u{0}']), ('\u{a782}', ['\u{a783}', '\u{0}', '\u{0}']),
+         ('\u{a784}', ['\u{a785}', '\u{0}', '\u{0}']), ('\u{a786}', ['\u{a787}', '\u{0}', '\u{0}']),
+         ('\u{a78b}', ['\u{a78c}', '\u{0}', '\u{0}']), ('\u{a78d}', ['\u{265}', '\u{0}', '\u{0}']),
+         ('\u{a790}', ['\u{a791}', '\u{0}', '\u{0}']), ('\u{a792}', ['\u{a793}', '\u{0}', '\u{0}']),
+         ('\u{a796}', ['\u{a797}', '\u{0}', '\u{0}']), ('\u{a798}', ['\u{a799}', '\u{0}', '\u{0}']),
+         ('\u{a79a}', ['\u{a79b}', '\u{0}', '\u{0}']), ('\u{a79c}', ['\u{a79d}', '\u{0}', '\u{0}']),
+         ('\u{a79e}', ['\u{a79f}', '\u{0}', '\u{0}']), ('\u{a7a0}', ['\u{a7a1}', '\u{0}', '\u{0}']),
+         ('\u{a7a2}', ['\u{a7a3}', '\u{0}', '\u{0}']), ('\u{a7a4}', ['\u{a7a5}', '\u{0}', '\u{0}']),
+         ('\u{a7a6}', ['\u{a7a7}', '\u{0}', '\u{0}']), ('\u{a7a8}', ['\u{a7a9}', '\u{0}', '\u{0}']),
+         ('\u{a7aa}', ['\u{266}', '\u{0}', '\u{0}']), ('\u{a7ab}', ['\u{25c}', '\u{0}', '\u{0}']),
+         ('\u{a7ac}', ['\u{261}', '\u{0}', '\u{0}']), ('\u{a7ad}', ['\u{26c}', '\u{0}', '\u{0}']),
+         ('\u{a7ae}', ['\u{26a}', '\u{0}', '\u{0}']), ('\u{a7b0}', ['\u{29e}', '\u{0}', '\u{0}']),
+         ('\u{a7b1}', ['\u{287}', '\u{0}', '\u{0}']), ('\u{a7b2}', ['\u{29d}', '\u{0}', '\u{0}']),
+         ('\u{a7b3}', ['\u{ab53}', '\u{0}', '\u{0}']), ('\u{a7b4}', ['\u{a7b5}', '\u{0}', '\u{0}']),
+         ('\u{a7b6}', ['\u{a7b7}', '\u{0}', '\u{0}']), ('\u{a7b8}', ['\u{a7b9}', '\u{0}', '\u{0}']),
+         ('\u{a7ba}', ['\u{a7bb}', '\u{0}', '\u{0}']), ('\u{a7bc}', ['\u{a7bd}', '\u{0}', '\u{0}']),
+         ('\u{a7be}', ['\u{a7bf}', '\u{0}', '\u{0}']), ('\u{a7c2}', ['\u{a7c3}', '\u{0}', '\u{0}']),
+         ('\u{a7c4}', ['\u{a794}', '\u{0}', '\u{0}']), ('\u{a7c5}', ['\u{282}', '\u{0}', '\u{0}']),
+         ('\u{a7c6}', ['\u{1d8e}', '\u{0}', '\u{0}']), ('\u{a7c7}', ['\u{a7c8}', '\u{0}', '\u{0}']),
+         ('\u{a7c9}', ['\u{a7ca}', '\u{0}', '\u{0}']), ('\u{a7f5}', ['\u{a7f6}', '\u{0}', '\u{0}']),
+         ('\u{ff21}', ['\u{ff41}', '\u{0}', '\u{0}']), ('\u{ff22}', ['\u{ff42}', '\u{0}', '\u{0}']),
+         ('\u{ff23}', ['\u{ff43}', '\u{0}', '\u{0}']), ('\u{ff24}', ['\u{ff44}', '\u{0}', '\u{0}']),
+         ('\u{ff25}', ['\u{ff45}', '\u{0}', '\u{0}']), ('\u{ff26}', ['\u{ff46}', '\u{0}', '\u{0}']),
+         ('\u{ff27}', ['\u{ff47}', '\u{0}', '\u{0}']), ('\u{ff28}', ['\u{ff48}', '\u{0}', '\u{0}']),
+         ('\u{ff29}', ['\u{ff49}', '\u{0}', '\u{0}']), ('\u{ff2a}', ['\u{ff4a}', '\u{0}', '\u{0}']),
+         ('\u{ff2b}', ['\u{ff4b}', '\u{0}', '\u{0}']), ('\u{ff2c}', ['\u{ff4c}', '\u{0}', '\u{0}']),
+         ('\u{ff2d}', ['\u{ff4d}', '\u{0}', '\u{0}']), ('\u{ff2e}', ['\u{ff4e}', '\u{0}', '\u{0}']),
+         ('\u{ff2f}', ['\u{ff4f}', '\u{0}', '\u{0}']), ('\u{ff30}', ['\u{ff50}', '\u{0}', '\u{0}']),
+         ('\u{ff31}', ['\u{ff51}', '\u{0}', '\u{0}']), ('\u{ff32}', ['\u{ff52}', '\u{0}', '\u{0}']),
+         ('\u{ff33}', ['\u{ff53}', '\u{0}', '\u{0}']), ('\u{ff34}', ['\u{ff54}', '\u{0}', '\u{0}']),
+         ('\u{ff35}', ['\u{ff55}', '\u{0}', '\u{0}']), ('\u{ff36}', ['\u{ff56}', '\u{0}', '\u{0}']),
+         ('\u{ff37}', ['\u{ff57}', '\u{0}', '\u{0}']), ('\u{ff38}', ['\u{ff58}', '\u{0}', '\u{0}']),
+         ('\u{ff39}', ['\u{ff59}', '\u{0}', '\u{0}']), ('\u{ff3a}', ['\u{ff5a}', '\u{0}', '\u{0}']),
+         ('\u{10400}', ['\u{10428}', '\u{0}', '\u{0}']),
+         ('\u{10401}', ['\u{10429}', '\u{0}', '\u{0}']),
+         ('\u{10402}', ['\u{1042a}', '\u{0}', '\u{0}']),
+         ('\u{10403}', ['\u{1042b}', '\u{0}', '\u{0}']),
+         ('\u{10404}', ['\u{1042c}', '\u{0}', '\u{0}']),
+         ('\u{10405}', ['\u{1042d}', '\u{0}', '\u{0}']),
+         ('\u{10406}', ['\u{1042e}', '\u{0}', '\u{0}']),
+         ('\u{10407}', ['\u{1042f}', '\u{0}', '\u{0}']),
+         ('\u{10408}', ['\u{10430}', '\u{0}', '\u{0}']),
+         ('\u{10409}', ['\u{10431}', '\u{0}', '\u{0}']),
+         ('\u{1040a}', ['\u{10432}', '\u{0}', '\u{0}']),
+         ('\u{1040b}', ['\u{10433}', '\u{0}', '\u{0}']),
+         ('\u{1040c}', ['\u{10434}', '\u{0}', '\u{0}']),
+         ('\u{1040d}', ['\u{10435}', '\u{0}', '\u{0}']),
+         ('\u{1040e}', ['\u{10436}', '\u{0}', '\u{0}']),
+         ('\u{1040f}', ['\u{10437}', '\u{0}', '\u{0}']),
+         ('\u{10410}', ['\u{10438}', '\u{0}', '\u{0}']),
+         ('\u{10411}', ['\u{10439}', '\u{0}', '\u{0}']),
+         ('\u{10412}', ['\u{1043a}', '\u{0}', '\u{0}']),
+         ('\u{10413}', ['\u{1043b}', '\u{0}', '\u{0}']),
+         ('\u{10414}', ['\u{1043c}', '\u{0}', '\u{0}']),
+         ('\u{10415}', ['\u{1043d}', '\u{0}', '\u{0}']),
+         ('\u{10416}', ['\u{1043e}', '\u{0}', '\u{0}']),
+         ('\u{10417}', ['\u{1043f}', '\u{0}', '\u{0}']),
+         ('\u{10418}', ['\u{10440}', '\u{0}', '\u{0}']),
+         ('\u{10419}', ['\u{10441}', '\u{0}', '\u{0}']),
+         ('\u{1041a}', ['\u{10442}', '\u{0}', '\u{0}']),
+         ('\u{1041b}', ['\u{10443}', '\u{0}', '\u{0}']),
+         ('\u{1041c}', ['\u{10444}', '\u{0}', '\u{0}']),
+         ('\u{1041d}', ['\u{10445}', '\u{0}', '\u{0}']),
+         ('\u{1041e}', ['\u{10446}', '\u{0}', '\u{0}']),
+         ('\u{1041f}', ['\u{10447}', '\u{0}', '\u{0}']),
+         ('\u{10420}', ['\u{10448}', '\u{0}', '\u{0}']),
+         ('\u{10421}', ['\u{10449}', '\u{0}', '\u{0}']),
+         ('\u{10422}', ['\u{1044a}', '\u{0}', '\u{0}']),
+         ('\u{10423}', ['\u{1044b}', '\u{0}', '\u{0}']),
+         ('\u{10424}', ['\u{1044c}', '\u{0}', '\u{0}']),
+         ('\u{10425}', ['\u{1044d}', '\u{0}', '\u{0}']),
+         ('\u{10426}', ['\u{1044e}', '\u{0}', '\u{0}']),
+         ('\u{10427}', ['\u{1044f}', '\u{0}', '\u{0}']),
+         ('\u{104b0}', ['\u{104d8}', '\u{0}', '\u{0}']),
+         ('\u{104b1}', ['\u{104d9}', '\u{0}', '\u{0}']),
+         ('\u{104b2}', ['\u{104da}', '\u{0}', '\u{0}']),
+         ('\u{104b3}', ['\u{104db}', '\u{0}', '\u{0}']),
+         ('\u{104b4}', ['\u{104dc}', '\u{0}', '\u{0}']),
+         ('\u{104b5}', ['\u{104dd}', '\u{0}', '\u{0}']),
+         ('\u{104b6}', ['\u{104de}', '\u{0}', '\u{0}']),
+         ('\u{104b7}', ['\u{104df}', '\u{0}', '\u{0}']),
+         ('\u{104b8}', ['\u{104e0}', '\u{0}', '\u{0}']),
+         ('\u{104b9}', ['\u{104e1}', '\u{0}', '\u{0}']),
+         ('\u{104ba}', ['\u{104e2}', '\u{0}', '\u{0}']),
+         ('\u{104bb}', ['\u{104e3}', '\u{0}', '\u{0}']),
+         ('\u{104bc}', ['\u{104e4}', '\u{0}', '\u{0}']),
+         ('\u{104bd}', ['\u{104e5}', '\u{0}', '\u{0}']),
+         ('\u{104be}', ['\u{104e6}', '\u{0}', '\u{0}']),
+         ('\u{104bf}', ['\u{104e7}', '\u{0}', '\u{0}']),
+         ('\u{104c0}', ['\u{104e8}', '\u{0}', '\u{0}']),
+         ('\u{104c1}', ['\u{104e9}', '\u{0}', '\u{0}']),
+         ('\u{104c2}', ['\u{104ea}', '\u{0}', '\u{0}']),
+         ('\u{104c3}', ['\u{104eb}', '\u{0}', '\u{0}']),
+         ('\u{104c4}', ['\u{104ec}', '\u{0}', '\u{0}']),
+         ('\u{104c5}', ['\u{104ed}', '\u{0}', '\u{0}']),
+         ('\u{104c6}', ['\u{104ee}', '\u{0}', '\u{0}']),
+         ('\u{104c7}', ['\u{104ef}', '\u{0}', '\u{0}']),
+         ('\u{104c8}', ['\u{104f0}', '\u{0}', '\u{0}']),
+         ('\u{104c9}', ['\u{104f1}', '\u{0}', '\u{0}']),
+         ('\u{104ca}', ['\u{104f2}', '\u{0}', '\u{0}']),
+         ('\u{104cb}', ['\u{104f3}', '\u{0}', '\u{0}']),
+         ('\u{104cc}', ['\u{104f4}', '\u{0}', '\u{0}']),
+         ('\u{104cd}', ['\u{104f5}', '\u{0}', '\u{0}']),
+         ('\u{104ce}', ['\u{104f6}', '\u{0}', '\u{0}']),
+         ('\u{104cf}', ['\u{104f7}', '\u{0}', '\u{0}']),
+         ('\u{104d0}', ['\u{104f8}', '\u{0}', '\u{0}']),
+         ('\u{104d1}', ['\u{104f9}', '\u{0}', '\u{0}']),
+         ('\u{104d2}', ['\u{104fa}', '\u{0}', '\u{0}']),
+         ('\u{104d3}', ['\u{104fb}', '\u{0}', '\u{0}']),
+         ('\u{10c80}', ['\u{10cc0}', '\u{0}', '\u{0}']),
+         ('\u{10c81}', ['\u{10cc1}', '\u{0}', '\u{0}']),
+         ('\u{10c82}', ['\u{10cc2}', '\u{0}', '\u{0}']),
+         ('\u{10c83}', ['\u{10cc3}', '\u{0}', '\u{0}']),
+         ('\u{10c84}', ['\u{10cc4}', '\u{0}', '\u{0}']),
+         ('\u{10c85}', ['\u{10cc5}', '\u{0}', '\u{0}']),
+         ('\u{10c86}', ['\u{10cc6}', '\u{0}', '\u{0}']),
+         ('\u{10c87}', ['\u{10cc7}', '\u{0}', '\u{0}']),
+         ('\u{10c88}', ['\u{10cc8}', '\u{0}', '\u{0}']),
+         ('\u{10c89}', ['\u{10cc9}', '\u{0}', '\u{0}']),
+         ('\u{10c8a}', ['\u{10cca}', '\u{0}', '\u{0}']),
+         ('\u{10c8b}', ['\u{10ccb}', '\u{0}', '\u{0}']),
+         ('\u{10c8c}', ['\u{10ccc}', '\u{0}', '\u{0}']),
+         ('\u{10c8d}', ['\u{10ccd}', '\u{0}', '\u{0}']),
+         ('\u{10c8e}', ['\u{10cce}', '\u{0}', '\u{0}']),
+         ('\u{10c8f}', ['\u{10ccf}', '\u{0}', '\u{0}']),
+         ('\u{10c90}', ['\u{10cd0}', '\u{0}', '\u{0}']),
+         ('\u{10c91}', ['\u{10cd1}', '\u{0}', '\u{0}']),
+         ('\u{10c92}', ['\u{10cd2}', '\u{0}', '\u{0}']),
+         ('\u{10c93}', ['\u{10cd3}', '\u{0}', '\u{0}']),
+         ('\u{10c94}', ['\u{10cd4}', '\u{0}', '\u{0}']),
+         ('\u{10c95}', ['\u{10cd5}', '\u{0}', '\u{0}']),
+         ('\u{10c96}', ['\u{10cd6}', '\u{0}', '\u{0}']),
+         ('\u{10c97}', ['\u{10cd7}', '\u{0}', '\u{0}']),
+         ('\u{10c98}', ['\u{10cd8}', '\u{0}', '\u{0}']),
+         ('\u{10c99}', ['\u{10cd9}', '\u{0}', '\u{0}']),
+         ('\u{10c9a}', ['\u{10cda}', '\u{0}', '\u{0}']),
+         ('\u{10c9b}', ['\u{10cdb}', '\u{0}', '\u{0}']),
+         ('\u{10c9c}', ['\u{10cdc}', '\u{0}', '\u{0}']),
+         ('\u{10c9d}', ['\u{10cdd}', '\u{0}', '\u{0}']),
+         ('\u{10c9e}', ['\u{10cde}', '\u{0}', '\u{0}']),
+         ('\u{10c9f}', ['\u{10cdf}', '\u{0}', '\u{0}']),
+         ('\u{10ca0}', ['\u{10ce0}', '\u{0}', '\u{0}']),
+         ('\u{10ca1}', ['\u{10ce1}', '\u{0}', '\u{0}']),
+         ('\u{10ca2}', ['\u{10ce2}', '\u{0}', '\u{0}']),
+         ('\u{10ca3}', ['\u{10ce3}', '\u{0}', '\u{0}']),
+         ('\u{10ca4}', ['\u{10ce4}', '\u{0}', '\u{0}']),
+         ('\u{10ca5}', ['\u{10ce5}', '\u{0}', '\u{0}']),
+         ('\u{10ca6}', ['\u{10ce6}', '\u{0}', '\u{0}']),
+         ('\u{10ca7}', ['\u{10ce7}', '\u{0}', '\u{0}']),
+         ('\u{10ca8}', ['\u{10ce8}', '\u{0}', '\u{0}']),
+         ('\u{10ca9}', ['\u{10ce9}', '\u{0}', '\u{0}']),
+         ('\u{10caa}', ['\u{10cea}', '\u{0}', '\u{0}']),
+         ('\u{10cab}', ['\u{10ceb}', '\u{0}', '\u{0}']),
+         ('\u{10cac}', ['\u{10cec}', '\u{0}', '\u{0}']),
+         ('\u{10cad}', ['\u{10ced}', '\u{0}', '\u{0}']),
+         ('\u{10cae}', ['\u{10cee}', '\u{0}', '\u{0}']),
+         ('\u{10caf}', ['\u{10cef}', '\u{0}', '\u{0}']),
+         ('\u{10cb0}', ['\u{10cf0}', '\u{0}', '\u{0}']),
+         ('\u{10cb1}', ['\u{10cf1}', '\u{0}', '\u{0}']),
+         ('\u{10cb2}', ['\u{10cf2}', '\u{0}', '\u{0}']),
+         ('\u{118a0}', ['\u{118c0}', '\u{0}', '\u{0}']),
+         ('\u{118a1}', ['\u{118c1}', '\u{0}', '\u{0}']),
+         ('\u{118a2}', ['\u{118c2}', '\u{0}', '\u{0}']),
+         ('\u{118a3}', ['\u{118c3}', '\u{0}', '\u{0}']),
+         ('\u{118a4}', ['\u{118c4}', '\u{0}', '\u{0}']),
+         ('\u{118a5}', ['\u{118c5}', '\u{0}', '\u{0}']),
+         ('\u{118a6}', ['\u{118c6}', '\u{0}', '\u{0}']),
+         ('\u{118a7}', ['\u{118c7}', '\u{0}', '\u{0}']),
+         ('\u{118a8}', ['\u{118c8}', '\u{0}', '\u{0}']),
+         ('\u{118a9}', ['\u{118c9}', '\u{0}', '\u{0}']),
+         ('\u{118aa}', ['\u{118ca}', '\u{0}', '\u{0}']),
+         ('\u{118ab}', ['\u{118cb}', '\u{0}', '\u{0}']),
+         ('\u{118ac}', ['\u{118cc}', '\u{0}', '\u{0}']),
+         ('\u{118ad}', ['\u{118cd}', '\u{0}', '\u{0}']),
+         ('\u{118ae}', ['\u{118ce}', '\u{0}', '\u{0}']),
+         ('\u{118af}', ['\u{118cf}', '\u{0}', '\u{0}']),
+         ('\u{118b0}', ['\u{118d0}', '\u{0}', '\u{0}']),
+         ('\u{118b1}', ['\u{118d1}', '\u{0}', '\u{0}']),
+         ('\u{118b2}', ['\u{118d2}', '\u{0}', '\u{0}']),
+         ('\u{118b3}', ['\u{118d3}', '\u{0}', '\u{0}']),
+         ('\u{118b4}', ['\u{118d4}', '\u{0}', '\u{0}']),
+         ('\u{118b5}', ['\u{118d5}', '\u{0}', '\u{0}']),
+         ('\u{118b6}', ['\u{118d6}', '\u{0}', '\u{0}']),
+         ('\u{118b7}', ['\u{118d7}', '\u{0}', '\u{0}']),
+         ('\u{118b8}', ['\u{118d8}', '\u{0}', '\u{0}']),
+         ('\u{118b9}', ['\u{118d9}', '\u{0}', '\u{0}']),
+         ('\u{118ba}', ['\u{118da}', '\u{0}', '\u{0}']),
+         ('\u{118bb}', ['\u{118db}', '\u{0}', '\u{0}']),
+         ('\u{118bc}', ['\u{118dc}', '\u{0}', '\u{0}']),
+         ('\u{118bd}', ['\u{118dd}', '\u{0}', '\u{0}']),
+         ('\u{118be}', ['\u{118de}', '\u{0}', '\u{0}']),
+         ('\u{118bf}', ['\u{118df}', '\u{0}', '\u{0}']),
+         ('\u{16e40}', ['\u{16e60}', '\u{0}', '\u{0}']),
+         ('\u{16e41}', ['\u{16e61}', '\u{0}', '\u{0}']),
+         ('\u{16e42}', ['\u{16e62}', '\u{0}', '\u{0}']),
+         ('\u{16e43}', ['\u{16e63}', '\u{0}', '\u{0}']),
+         ('\u{16e44}', ['\u{16e64}', '\u{0}', '\u{0}']),
+         ('\u{16e45}', ['\u{16e65}', '\u{0}', '\u{0}']),
+         ('\u{16e46}', ['\u{16e66}', '\u{0}', '\u{0}']),
+         ('\u{16e47}', ['\u{16e67}', '\u{0}', '\u{0}']),
+         ('\u{16e48}', ['\u{16e68}', '\u{0}', '\u{0}']),
+         ('\u{16e49}', ['\u{16e69}', '\u{0}', '\u{0}']),
+         ('\u{16e4a}', ['\u{16e6a}', '\u{0}', '\u{0}']),
+         ('\u{16e4b}', ['\u{16e6b}', '\u{0}', '\u{0}']),
+         ('\u{16e4c}', ['\u{16e6c}', '\u{0}', '\u{0}']),
+         ('\u{16e4d}', ['\u{16e6d}', '\u{0}', '\u{0}']),
+         ('\u{16e4e}', ['\u{16e6e}', '\u{0}', '\u{0}']),
+         ('\u{16e4f}', ['\u{16e6f}', '\u{0}', '\u{0}']),
+         ('\u{16e50}', ['\u{16e70}', '\u{0}', '\u{0}']),
+         ('\u{16e51}', ['\u{16e71}', '\u{0}', '\u{0}']),
+         ('\u{16e52}', ['\u{16e72}', '\u{0}', '\u{0}']),
+         ('\u{16e53}', ['\u{16e73}', '\u{0}', '\u{0}']),
+         ('\u{16e54}', ['\u{16e74}', '\u{0}', '\u{0}']),
+         ('\u{16e55}', ['\u{16e75}', '\u{0}', '\u{0}']),
+         ('\u{16e56}', ['\u{16e76}', '\u{0}', '\u{0}']),
+         ('\u{16e57}', ['\u{16e77}', '\u{0}', '\u{0}']),
+         ('\u{16e58}', ['\u{16e78}', '\u{0}', '\u{0}']),
+         ('\u{16e59}', ['\u{16e79}', '\u{0}', '\u{0}']),
+         ('\u{16e5a}', ['\u{16e7a}', '\u{0}', '\u{0}']),
+         ('\u{16e5b}', ['\u{16e7b}', '\u{0}', '\u{0}']),
+         ('\u{16e5c}', ['\u{16e7c}', '\u{0}', '\u{0}']),
+         ('\u{16e5d}', ['\u{16e7d}', '\u{0}', '\u{0}']),
+         ('\u{16e5e}', ['\u{16e7e}', '\u{0}', '\u{0}']),
+         ('\u{16e5f}', ['\u{16e7f}', '\u{0}', '\u{0}']),
+         ('\u{1e900}', ['\u{1e922}', '\u{0}', '\u{0}']),
+         ('\u{1e901}', ['\u{1e923}', '\u{0}', '\u{0}']),
+         ('\u{1e902}', ['\u{1e924}', '\u{0}', '\u{0}']),
+         ('\u{1e903}', ['\u{1e925}', '\u{0}', '\u{0}']),
+         ('\u{1e904}', ['\u{1e926}', '\u{0}', '\u{0}']),
+         ('\u{1e905}', ['\u{1e927}', '\u{0}', '\u{0}']),
+         ('\u{1e906}', ['\u{1e928}', '\u{0}', '\u{0}']),
+         ('\u{1e907}', ['\u{1e929}', '\u{0}', '\u{0}']),
+         ('\u{1e908}', ['\u{1e92a}', '\u{0}', '\u{0}']),
+         ('\u{1e909}', ['\u{1e92b}', '\u{0}', '\u{0}']),
+         ('\u{1e90a}', ['\u{1e92c}', '\u{0}', '\u{0}']),
+         ('\u{1e90b}', ['\u{1e92d}', '\u{0}', '\u{0}']),
+         ('\u{1e90c}', ['\u{1e92e}', '\u{0}', '\u{0}']),
+         ('\u{1e90d}', ['\u{1e92f}', '\u{0}', '\u{0}']),
+         ('\u{1e90e}', ['\u{1e930}', '\u{0}', '\u{0}']),
+         ('\u{1e90f}', ['\u{1e931}', '\u{0}', '\u{0}']),
+         ('\u{1e910}', ['\u{1e932}', '\u{0}', '\u{0}']),
+         ('\u{1e911}', ['\u{1e933}', '\u{0}', '\u{0}']),
+         ('\u{1e912}', ['\u{1e934}', '\u{0}', '\u{0}']),
+         ('\u{1e913}', ['\u{1e935}', '\u{0}', '\u{0}']),
+         ('\u{1e914}', ['\u{1e936}', '\u{0}', '\u{0}']),
+         ('\u{1e915}', ['\u{1e937}', '\u{0}', '\u{0}']),
+         ('\u{1e916}', ['\u{1e938}', '\u{0}', '\u{0}']),
+         ('\u{1e917}', ['\u{1e939}', '\u{0}', '\u{0}']),
+         ('\u{1e918}', ['\u{1e93a}', '\u{0}', '\u{0}']),
+         ('\u{1e919}', ['\u{1e93b}', '\u{0}', '\u{0}']),
+         ('\u{1e91a}', ['\u{1e93c}', '\u{0}', '\u{0}']),
+         ('\u{1e91b}', ['\u{1e93d}', '\u{0}', '\u{0}']),
+         ('\u{1e91c}', ['\u{1e93e}', '\u{0}', '\u{0}']),
+         ('\u{1e91d}', ['\u{1e93f}', '\u{0}', '\u{0}']),
+         ('\u{1e91e}', ['\u{1e940}', '\u{0}', '\u{0}']),
+         ('\u{1e91f}', ['\u{1e941}', '\u{0}', '\u{0}']),
+         ('\u{1e920}', ['\u{1e942}', '\u{0}', '\u{0}']),
+         ('\u{1e921}', ['\u{1e943}', '\u{0}', '\u{0}']),
+     ];
+ 
+     static UPPERCASE_TABLE: &[(char, [char; 3])] = &[
+         ('a', ['A', '\u{0}', '\u{0}']), ('b', ['B', '\u{0}', '\u{0}']),
+         ('c', ['C', '\u{0}', '\u{0}']), ('d', ['D', '\u{0}', '\u{0}']),
+         ('e', ['E', '\u{0}', '\u{0}']), ('f', ['F', '\u{0}', '\u{0}']),
+         ('g', ['G', '\u{0}', '\u{0}']), ('h', ['H', '\u{0}', '\u{0}']),
+         ('i', ['I', '\u{0}', '\u{0}']), ('j', ['J', '\u{0}', '\u{0}']),
+         ('k', ['K', '\u{0}', '\u{0}']), ('l', ['L', '\u{0}', '\u{0}']),
+         ('m', ['M', '\u{0}', '\u{0}']), ('n', ['N', '\u{0}', '\u{0}']),
+         ('o', ['O', '\u{0}', '\u{0}']), ('p', ['P', '\u{0}', '\u{0}']),
+         ('q', ['Q', '\u{0}', '\u{0}']), ('r', ['R', '\u{0}', '\u{0}']),
+         ('s', ['S', '\u{0}', '\u{0}']), ('t', ['T', '\u{0}', '\u{0}']),
+         ('u', ['U', '\u{0}', '\u{0}']), ('v', ['V', '\u{0}', '\u{0}']),
+         ('w', ['W', '\u{0}', '\u{0}']), ('x', ['X', '\u{0}', '\u{0}']),
+         ('y', ['Y', '\u{0}', '\u{0}']), ('z', ['Z', '\u{0}', '\u{0}']),
+         ('\u{b5}', ['\u{39c}', '\u{0}', '\u{0}']), ('\u{df}', ['S', 'S', '\u{0}']),
+         ('\u{e0}', ['\u{c0}', '\u{0}', '\u{0}']), ('\u{e1}', ['\u{c1}', '\u{0}', '\u{0}']),
+         ('\u{e2}', ['\u{c2}', '\u{0}', '\u{0}']), ('\u{e3}', ['\u{c3}', '\u{0}', '\u{0}']),
+         ('\u{e4}', ['\u{c4}', '\u{0}', '\u{0}']), ('\u{e5}', ['\u{c5}', '\u{0}', '\u{0}']),
+         ('\u{e6}', ['\u{c6}', '\u{0}', '\u{0}']), ('\u{e7}', ['\u{c7}', '\u{0}', '\u{0}']),
+         ('\u{e8}', ['\u{c8}', '\u{0}', '\u{0}']), ('\u{e9}', ['\u{c9}', '\u{0}', '\u{0}']),
+         ('\u{ea}', ['\u{ca}', '\u{0}', '\u{0}']), ('\u{eb}', ['\u{cb}', '\u{0}', '\u{0}']),
+         ('\u{ec}', ['\u{cc}', '\u{0}', '\u{0}']), ('\u{ed}', ['\u{cd}', '\u{0}', '\u{0}']),
+         ('\u{ee}', ['\u{ce}', '\u{0}', '\u{0}']), ('\u{ef}', ['\u{cf}', '\u{0}', '\u{0}']),
+         ('\u{f0}', ['\u{d0}', '\u{0}', '\u{0}']), ('\u{f1}', ['\u{d1}', '\u{0}', '\u{0}']),
+         ('\u{f2}', ['\u{d2}', '\u{0}', '\u{0}']), ('\u{f3}', ['\u{d3}', '\u{0}', '\u{0}']),
+         ('\u{f4}', ['\u{d4}', '\u{0}', '\u{0}']), ('\u{f5}', ['\u{d5}', '\u{0}', '\u{0}']),
+         ('\u{f6}', ['\u{d6}', '\u{0}', '\u{0}']), ('\u{f8}', ['\u{d8}', '\u{0}', '\u{0}']),
+         ('\u{f9}', ['\u{d9}', '\u{0}', '\u{0}']), ('\u{fa}', ['\u{da}', '\u{0}', '\u{0}']),
+         ('\u{fb}', ['\u{db}', '\u{0}', '\u{0}']), ('\u{fc}', ['\u{dc}', '\u{0}', '\u{0}']),
+         ('\u{fd}', ['\u{dd}', '\u{0}', '\u{0}']), ('\u{fe}', ['\u{de}', '\u{0}', '\u{0}']),
+         ('\u{ff}', ['\u{178}', '\u{0}', '\u{0}']), ('\u{101}', ['\u{100}', '\u{0}', '\u{0}']),
+         ('\u{103}', ['\u{102}', '\u{0}', '\u{0}']), ('\u{105}', ['\u{104}', '\u{0}', '\u{0}']),
+         ('\u{107}', ['\u{106}', '\u{0}', '\u{0}']), ('\u{109}', ['\u{108}', '\u{0}', '\u{0}']),
+         ('\u{10b}', ['\u{10a}', '\u{0}', '\u{0}']), ('\u{10d}', ['\u{10c}', '\u{0}', '\u{0}']),
+         ('\u{10f}', ['\u{10e}', '\u{0}', '\u{0}']), ('\u{111}', ['\u{110}', '\u{0}', '\u{0}']),
+         ('\u{113}', ['\u{112}', '\u{0}', '\u{0}']), ('\u{115}', ['\u{114}', '\u{0}', '\u{0}']),
+         ('\u{117}', ['\u{116}', '\u{0}', '\u{0}']), ('\u{119}', ['\u{118}', '\u{0}', '\u{0}']),
+         ('\u{11b}', ['\u{11a}', '\u{0}', '\u{0}']), ('\u{11d}', ['\u{11c}', '\u{0}', '\u{0}']),
+         ('\u{11f}', ['\u{11e}', '\u{0}', '\u{0}']), ('\u{121}', ['\u{120}', '\u{0}', '\u{0}']),
+         ('\u{123}', ['\u{122}', '\u{0}', '\u{0}']), ('\u{125}', ['\u{124}', '\u{0}', '\u{0}']),
+         ('\u{127}', ['\u{126}', '\u{0}', '\u{0}']), ('\u{129}', ['\u{128}', '\u{0}', '\u{0}']),
+         ('\u{12b}', ['\u{12a}', '\u{0}', '\u{0}']), ('\u{12d}', ['\u{12c}', '\u{0}', '\u{0}']),
+         ('\u{12f}', ['\u{12e}', '\u{0}', '\u{0}']), ('\u{131}', ['I', '\u{0}', '\u{0}']),
+         ('\u{133}', ['\u{132}', '\u{0}', '\u{0}']), ('\u{135}', ['\u{134}', '\u{0}', '\u{0}']),
+         ('\u{137}', ['\u{136}', '\u{0}', '\u{0}']), ('\u{13a}', ['\u{139}', '\u{0}', '\u{0}']),
+         ('\u{13c}', ['\u{13b}', '\u{0}', '\u{0}']), ('\u{13e}', ['\u{13d}', '\u{0}', '\u{0}']),
+         ('\u{140}', ['\u{13f}', '\u{0}', '\u{0}']), ('\u{142}', ['\u{141}', '\u{0}', '\u{0}']),
+         ('\u{144}', ['\u{143}', '\u{0}', '\u{0}']), ('\u{146}', ['\u{145}', '\u{0}', '\u{0}']),
+         ('\u{148}', ['\u{147}', '\u{0}', '\u{0}']), ('\u{149}', ['\u{2bc}', 'N', '\u{0}']),
+         ('\u{14b}', ['\u{14a}', '\u{0}', '\u{0}']), ('\u{14d}', ['\u{14c}', '\u{0}', '\u{0}']),
+         ('\u{14f}', ['\u{14e}', '\u{0}', '\u{0}']), ('\u{151}', ['\u{150}', '\u{0}', '\u{0}']),
+         ('\u{153}', ['\u{152}', '\u{0}', '\u{0}']), ('\u{155}', ['\u{154}', '\u{0}', '\u{0}']),
+         ('\u{157}', ['\u{156}', '\u{0}', '\u{0}']), ('\u{159}', ['\u{158}', '\u{0}', '\u{0}']),
+         ('\u{15b}', ['\u{15a}', '\u{0}', '\u{0}']), ('\u{15d}', ['\u{15c}', '\u{0}', '\u{0}']),
+         ('\u{15f}', ['\u{15e}', '\u{0}', '\u{0}']), ('\u{161}', ['\u{160}', '\u{0}', '\u{0}']),
+         ('\u{163}', ['\u{162}', '\u{0}', '\u{0}']), ('\u{165}', ['\u{164}', '\u{0}', '\u{0}']),
+         ('\u{167}', ['\u{166}', '\u{0}', '\u{0}']), ('\u{169}', ['\u{168}', '\u{0}', '\u{0}']),
+         ('\u{16b}', ['\u{16a}', '\u{0}', '\u{0}']), ('\u{16d}', ['\u{16c}', '\u{0}', '\u{0}']),
+         ('\u{16f}', ['\u{16e}', '\u{0}', '\u{0}']), ('\u{171}', ['\u{170}', '\u{0}', '\u{0}']),
+         ('\u{173}', ['\u{172}', '\u{0}', '\u{0}']), ('\u{175}', ['\u{174}', '\u{0}', '\u{0}']),
+         ('\u{177}', ['\u{176}', '\u{0}', '\u{0}']), ('\u{17a}', ['\u{179}', '\u{0}', '\u{0}']),
+         ('\u{17c}', ['\u{17b}', '\u{0}', '\u{0}']), ('\u{17e}', ['\u{17d}', '\u{0}', '\u{0}']),
+         ('\u{17f}', ['S', '\u{0}', '\u{0}']), ('\u{180}', ['\u{243}', '\u{0}', '\u{0}']),
+         ('\u{183}', ['\u{182}', '\u{0}', '\u{0}']), ('\u{185}', ['\u{184}', '\u{0}', '\u{0}']),
+         ('\u{188}', ['\u{187}', '\u{0}', '\u{0}']), ('\u{18c}', ['\u{18b}', '\u{0}', '\u{0}']),
+         ('\u{192}', ['\u{191}', '\u{0}', '\u{0}']), ('\u{195}', ['\u{1f6}', '\u{0}', '\u{0}']),
+         ('\u{199}', ['\u{198}', '\u{0}', '\u{0}']), ('\u{19a}', ['\u{23d}', '\u{0}', '\u{0}']),
+         ('\u{19e}', ['\u{220}', '\u{0}', '\u{0}']), ('\u{1a1}', ['\u{1a0}', '\u{0}', '\u{0}']),
+         ('\u{1a3}', ['\u{1a2}', '\u{0}', '\u{0}']), ('\u{1a5}', ['\u{1a4}', '\u{0}', '\u{0}']),
+         ('\u{1a8}', ['\u{1a7}', '\u{0}', '\u{0}']), ('\u{1ad}', ['\u{1ac}', '\u{0}', '\u{0}']),
+         ('\u{1b0}', ['\u{1af}', '\u{0}', '\u{0}']), ('\u{1b4}', ['\u{1b3}', '\u{0}', '\u{0}']),
+         ('\u{1b6}', ['\u{1b5}', '\u{0}', '\u{0}']), ('\u{1b9}', ['\u{1b8}', '\u{0}', '\u{0}']),
+         ('\u{1bd}', ['\u{1bc}', '\u{0}', '\u{0}']), ('\u{1bf}', ['\u{1f7}', '\u{0}', '\u{0}']),
+         ('\u{1c5}', ['\u{1c4}', '\u{0}', '\u{0}']), ('\u{1c6}', ['\u{1c4}', '\u{0}', '\u{0}']),
+         ('\u{1c8}', ['\u{1c7}', '\u{0}', '\u{0}']), ('\u{1c9}', ['\u{1c7}', '\u{0}', '\u{0}']),
+         ('\u{1cb}', ['\u{1ca}', '\u{0}', '\u{0}']), ('\u{1cc}', ['\u{1ca}', '\u{0}', '\u{0}']),
+         ('\u{1ce}', ['\u{1cd}', '\u{0}', '\u{0}']), ('\u{1d0}', ['\u{1cf}', '\u{0}', '\u{0}']),
+         ('\u{1d2}', ['\u{1d1}', '\u{0}', '\u{0}']), ('\u{1d4}', ['\u{1d3}', '\u{0}', '\u{0}']),
+         ('\u{1d6}', ['\u{1d5}', '\u{0}', '\u{0}']), ('\u{1d8}', ['\u{1d7}', '\u{0}', '\u{0}']),
+         ('\u{1da}', ['\u{1d9}', '\u{0}', '\u{0}']), ('\u{1dc}', ['\u{1db}', '\u{0}', '\u{0}']),
+         ('\u{1dd}', ['\u{18e}', '\u{0}', '\u{0}']), ('\u{1df}', ['\u{1de}', '\u{0}', '\u{0}']),
+         ('\u{1e1}', ['\u{1e0}', '\u{0}', '\u{0}']), ('\u{1e3}', ['\u{1e2}', '\u{0}', '\u{0}']),
+         ('\u{1e5}', ['\u{1e4}', '\u{0}', '\u{0}']), ('\u{1e7}', ['\u{1e6}', '\u{0}', '\u{0}']),
+         ('\u{1e9}', ['\u{1e8}', '\u{0}', '\u{0}']), ('\u{1eb}', ['\u{1ea}', '\u{0}', '\u{0}']),
+         ('\u{1ed}', ['\u{1ec}', '\u{0}', '\u{0}']), ('\u{1ef}', ['\u{1ee}', '\u{0}', '\u{0}']),
+         ('\u{1f0}', ['J', '\u{30c}', '\u{0}']), ('\u{1f2}', ['\u{1f1}', '\u{0}', '\u{0}']),
+         ('\u{1f3}', ['\u{1f1}', '\u{0}', '\u{0}']), ('\u{1f5}', ['\u{1f4}', '\u{0}', '\u{0}']),
+         ('\u{1f9}', ['\u{1f8}', '\u{0}', '\u{0}']), ('\u{1fb}', ['\u{1fa}', '\u{0}', '\u{0}']),
+         ('\u{1fd}', ['\u{1fc}', '\u{0}', '\u{0}']), ('\u{1ff}', ['\u{1fe}', '\u{0}', '\u{0}']),
+         ('\u{201}', ['\u{200}', '\u{0}', '\u{0}']), ('\u{203}', ['\u{202}', '\u{0}', '\u{0}']),
+         ('\u{205}', ['\u{204}', '\u{0}', '\u{0}']), ('\u{207}', ['\u{206}', '\u{0}', '\u{0}']),
+         ('\u{209}', ['\u{208}', '\u{0}', '\u{0}']), ('\u{20b}', ['\u{20a}', '\u{0}', '\u{0}']),
+         ('\u{20d}', ['\u{20c}', '\u{0}', '\u{0}']), ('\u{20f}', ['\u{20e}', '\u{0}', '\u{0}']),
+         ('\u{211}', ['\u{210}', '\u{0}', '\u{0}']), ('\u{213}', ['\u{212}', '\u{0}', '\u{0}']),
+         ('\u{215}', ['\u{214}', '\u{0}', '\u{0}']), ('\u{217}', ['\u{216}', '\u{0}', '\u{0}']),
+         ('\u{219}', ['\u{218}', '\u{0}', '\u{0}']), ('\u{21b}', ['\u{21a}', '\u{0}', '\u{0}']),
+         ('\u{21d}', ['\u{21c}', '\u{0}', '\u{0}']), ('\u{21f}', ['\u{21e}', '\u{0}', '\u{0}']),
+         ('\u{223}', ['\u{222}', '\u{0}', '\u{0}']), ('\u{225}', ['\u{224}', '\u{0}', '\u{0}']),
+         ('\u{227}', ['\u{226}', '\u{0}', '\u{0}']), ('\u{229}', ['\u{228}', '\u{0}', '\u{0}']),
+         ('\u{22b}', ['\u{22a}', '\u{0}', '\u{0}']), ('\u{22d}', ['\u{22c}', '\u{0}', '\u{0}']),
+         ('\u{22f}', ['\u{22e}', '\u{0}', '\u{0}']), ('\u{231}', ['\u{230}', '\u{0}', '\u{0}']),
+         ('\u{233}', ['\u{232}', '\u{0}', '\u{0}']), ('\u{23c}', ['\u{23b}', '\u{0}', '\u{0}']),
+         ('\u{23f}', ['\u{2c7e}', '\u{0}', '\u{0}']), ('\u{240}', ['\u{2c7f}', '\u{0}', '\u{0}']),
+         ('\u{242}', ['\u{241}', '\u{0}', '\u{0}']), ('\u{247}', ['\u{246}', '\u{0}', '\u{0}']),
+         ('\u{249}', ['\u{248}', '\u{0}', '\u{0}']), ('\u{24b}', ['\u{24a}', '\u{0}', '\u{0}']),
+         ('\u{24d}', ['\u{24c}', '\u{0}', '\u{0}']), ('\u{24f}', ['\u{24e}', '\u{0}', '\u{0}']),
+         ('\u{250}', ['\u{2c6f}', '\u{0}', '\u{0}']), ('\u{251}', ['\u{2c6d}', '\u{0}', '\u{0}']),
+         ('\u{252}', ['\u{2c70}', '\u{0}', '\u{0}']), ('\u{253}', ['\u{181}', '\u{0}', '\u{0}']),
+         ('\u{254}', ['\u{186}', '\u{0}', '\u{0}']), ('\u{256}', ['\u{189}', '\u{0}', '\u{0}']),
+         ('\u{257}', ['\u{18a}', '\u{0}', '\u{0}']), ('\u{259}', ['\u{18f}', '\u{0}', '\u{0}']),
+         ('\u{25b}', ['\u{190}', '\u{0}', '\u{0}']), ('\u{25c}', ['\u{a7ab}', '\u{0}', '\u{0}']),
+         ('\u{260}', ['\u{193}', '\u{0}', '\u{0}']), ('\u{261}', ['\u{a7ac}', '\u{0}', '\u{0}']),
+         ('\u{263}', ['\u{194}', '\u{0}', '\u{0}']), ('\u{265}', ['\u{a78d}', '\u{0}', '\u{0}']),
+         ('\u{266}', ['\u{a7aa}', '\u{0}', '\u{0}']), ('\u{268}', ['\u{197}', '\u{0}', '\u{0}']),
+         ('\u{269}', ['\u{196}', '\u{0}', '\u{0}']), ('\u{26a}', ['\u{a7ae}', '\u{0}', '\u{0}']),
+         ('\u{26b}', ['\u{2c62}', '\u{0}', '\u{0}']), ('\u{26c}', ['\u{a7ad}', '\u{0}', '\u{0}']),
+         ('\u{26f}', ['\u{19c}', '\u{0}', '\u{0}']), ('\u{271}', ['\u{2c6e}', '\u{0}', '\u{0}']),
+         ('\u{272}', ['\u{19d}', '\u{0}', '\u{0}']), ('\u{275}', ['\u{19f}', '\u{0}', '\u{0}']),
+         ('\u{27d}', ['\u{2c64}', '\u{0}', '\u{0}']), ('\u{280}', ['\u{1a6}', '\u{0}', '\u{0}']),
+         ('\u{282}', ['\u{a7c5}', '\u{0}', '\u{0}']), ('\u{283}', ['\u{1a9}', '\u{0}', '\u{0}']),
+         ('\u{287}', ['\u{a7b1}', '\u{0}', '\u{0}']), ('\u{288}', ['\u{1ae}', '\u{0}', '\u{0}']),
+         ('\u{289}', ['\u{244}', '\u{0}', '\u{0}']), ('\u{28a}', ['\u{1b1}', '\u{0}', '\u{0}']),
+         ('\u{28b}', ['\u{1b2}', '\u{0}', '\u{0}']), ('\u{28c}', ['\u{245}', '\u{0}', '\u{0}']),
+         ('\u{292}', ['\u{1b7}', '\u{0}', '\u{0}']), ('\u{29d}', ['\u{a7b2}', '\u{0}', '\u{0}']),
+         ('\u{29e}', ['\u{a7b0}', '\u{0}', '\u{0}']), ('\u{345}', ['\u{399}', '\u{0}', '\u{0}']),
+         ('\u{371}', ['\u{370}', '\u{0}', '\u{0}']), ('\u{373}', ['\u{372}', '\u{0}', '\u{0}']),
+         ('\u{377}', ['\u{376}', '\u{0}', '\u{0}']), ('\u{37b}', ['\u{3fd}', '\u{0}', '\u{0}']),
+         ('\u{37c}', ['\u{3fe}', '\u{0}', '\u{0}']), ('\u{37d}', ['\u{3ff}', '\u{0}', '\u{0}']),
+         ('\u{390}', ['\u{399}', '\u{308}', '\u{301}']), ('\u{3ac}', ['\u{386}', '\u{0}', '\u{0}']),
+         ('\u{3ad}', ['\u{388}', '\u{0}', '\u{0}']), ('\u{3ae}', ['\u{389}', '\u{0}', '\u{0}']),
+         ('\u{3af}', ['\u{38a}', '\u{0}', '\u{0}']), ('\u{3b0}', ['\u{3a5}', '\u{308}', '\u{301}']),
+         ('\u{3b1}', ['\u{391}', '\u{0}', '\u{0}']), ('\u{3b2}', ['\u{392}', '\u{0}', '\u{0}']),
+         ('\u{3b3}', ['\u{393}', '\u{0}', '\u{0}']), ('\u{3b4}', ['\u{394}', '\u{0}', '\u{0}']),
+         ('\u{3b5}', ['\u{395}', '\u{0}', '\u{0}']), ('\u{3b6}', ['\u{396}', '\u{0}', '\u{0}']),
+         ('\u{3b7}', ['\u{397}', '\u{0}', '\u{0}']), ('\u{3b8}', ['\u{398}', '\u{0}', '\u{0}']),
+         ('\u{3b9}', ['\u{399}', '\u{0}', '\u{0}']), ('\u{3ba}', ['\u{39a}', '\u{0}', '\u{0}']),
+         ('\u{3bb}', ['\u{39b}', '\u{0}', '\u{0}']), ('\u{3bc}', ['\u{39c}', '\u{0}', '\u{0}']),
+         ('\u{3bd}', ['\u{39d}', '\u{0}', '\u{0}']), ('\u{3be}', ['\u{39e}', '\u{0}', '\u{0}']),
+         ('\u{3bf}', ['\u{39f}', '\u{0}', '\u{0}']), ('\u{3c0}', ['\u{3a0}', '\u{0}', '\u{0}']),
+         ('\u{3c1}', ['\u{3a1}', '\u{0}', '\u{0}']), ('\u{3c2}', ['\u{3a3}', '\u{0}', '\u{0}']),
+         ('\u{3c3}', ['\u{3a3}', '\u{0}', '\u{0}']), ('\u{3c4}', ['\u{3a4}', '\u{0}', '\u{0}']),
+         ('\u{3c5}', ['\u{3a5}', '\u{0}', '\u{0}']), ('\u{3c6}', ['\u{3a6}', '\u{0}', '\u{0}']),
+         ('\u{3c7}', ['\u{3a7}', '\u{0}', '\u{0}']), ('\u{3c8}', ['\u{3a8}', '\u{0}', '\u{0}']),
+         ('\u{3c9}', ['\u{3a9}', '\u{0}', '\u{0}']), ('\u{3ca}', ['\u{3aa}', '\u{0}', '\u{0}']),
+         ('\u{3cb}', ['\u{3ab}', '\u{0}', '\u{0}']), ('\u{3cc}', ['\u{38c}', '\u{0}', '\u{0}']),
+         ('\u{3cd}', ['\u{38e}', '\u{0}', '\u{0}']), ('\u{3ce}', ['\u{38f}', '\u{0}', '\u{0}']),
+         ('\u{3d0}', ['\u{392}', '\u{0}', '\u{0}']), ('\u{3d1}', ['\u{398}', '\u{0}', '\u{0}']),
+         ('\u{3d5}', ['\u{3a6}', '\u{0}', '\u{0}']), ('\u{3d6}', ['\u{3a0}', '\u{0}', '\u{0}']),
+         ('\u{3d7}', ['\u{3cf}', '\u{0}', '\u{0}']), ('\u{3d9}', ['\u{3d8}', '\u{0}', '\u{0}']),
+         ('\u{3db}', ['\u{3da}', '\u{0}', '\u{0}']), ('\u{3dd}', ['\u{3dc}', '\u{0}', '\u{0}']),
+         ('\u{3df}', ['\u{3de}', '\u{0}', '\u{0}']), ('\u{3e1}', ['\u{3e0}', '\u{0}', '\u{0}']),
+         ('\u{3e3}', ['\u{3e2}', '\u{0}', '\u{0}']), ('\u{3e5}', ['\u{3e4}', '\u{0}', '\u{0}']),
+         ('\u{3e7}', ['\u{3e6}', '\u{0}', '\u{0}']), ('\u{3e9}', ['\u{3e8}', '\u{0}', '\u{0}']),
+         ('\u{3eb}', ['\u{3ea}', '\u{0}', '\u{0}']), ('\u{3ed}', ['\u{3ec}', '\u{0}', '\u{0}']),
+         ('\u{3ef}', ['\u{3ee}', '\u{0}', '\u{0}']), ('\u{3f0}', ['\u{39a}', '\u{0}', '\u{0}']),
+         ('\u{3f1}', ['\u{3a1}', '\u{0}', '\u{0}']), ('\u{3f2}', ['\u{3f9}', '\u{0}', '\u{0}']),
+         ('\u{3f3}', ['\u{37f}', '\u{0}', '\u{0}']), ('\u{3f5}', ['\u{395}', '\u{0}', '\u{0}']),
+         ('\u{3f8}', ['\u{3f7}', '\u{0}', '\u{0}']), ('\u{3fb}', ['\u{3fa}', '\u{0}', '\u{0}']),
+         ('\u{430}', ['\u{410}', '\u{0}', '\u{0}']), ('\u{431}', ['\u{411}', '\u{0}', '\u{0}']),
+         ('\u{432}', ['\u{412}', '\u{0}', '\u{0}']), ('\u{433}', ['\u{413}', '\u{0}', '\u{0}']),
+         ('\u{434}', ['\u{414}', '\u{0}', '\u{0}']), ('\u{435}', ['\u{415}', '\u{0}', '\u{0}']),
+         ('\u{436}', ['\u{416}', '\u{0}', '\u{0}']), ('\u{437}', ['\u{417}', '\u{0}', '\u{0}']),
+         ('\u{438}', ['\u{418}', '\u{0}', '\u{0}']), ('\u{439}', ['\u{419}', '\u{0}', '\u{0}']),
+         ('\u{43a}', ['\u{41a}', '\u{0}', '\u{0}']), ('\u{43b}', ['\u{41b}', '\u{0}', '\u{0}']),
+         ('\u{43c}', ['\u{41c}', '\u{0}', '\u{0}']), ('\u{43d}', ['\u{41d}', '\u{0}', '\u{0}']),
+         ('\u{43e}', ['\u{41e}', '\u{0}', '\u{0}']), ('\u{43f}', ['\u{41f}', '\u{0}', '\u{0}']),
+         ('\u{440}', ['\u{420}', '\u{0}', '\u{0}']), ('\u{441}', ['\u{421}', '\u{0}', '\u{0}']),
+         ('\u{442}', ['\u{422}', '\u{0}', '\u{0}']), ('\u{443}', ['\u{423}', '\u{0}', '\u{0}']),
+         ('\u{444}', ['\u{424}', '\u{0}', '\u{0}']), ('\u{445}', ['\u{425}', '\u{0}', '\u{0}']),
+         ('\u{446}', ['\u{426}', '\u{0}', '\u{0}']), ('\u{447}', ['\u{427}', '\u{0}', '\u{0}']),
+         ('\u{448}', ['\u{428}', '\u{0}', '\u{0}']), ('\u{449}', ['\u{429}', '\u{0}', '\u{0}']),
+         ('\u{44a}', ['\u{42a}', '\u{0}', '\u{0}']), ('\u{44b}', ['\u{42b}', '\u{0}', '\u{0}']),
+         ('\u{44c}', ['\u{42c}', '\u{0}', '\u{0}']), ('\u{44d}', ['\u{42d}', '\u{0}', '\u{0}']),
+         ('\u{44e}', ['\u{42e}', '\u{0}', '\u{0}']), ('\u{44f}', ['\u{42f}', '\u{0}', '\u{0}']),
+         ('\u{450}', ['\u{400}', '\u{0}', '\u{0}']), ('\u{451}', ['\u{401}', '\u{0}', '\u{0}']),
+         ('\u{452}', ['\u{402}', '\u{0}', '\u{0}']), ('\u{453}', ['\u{403}', '\u{0}', '\u{0}']),
+         ('\u{454}', ['\u{404}', '\u{0}', '\u{0}']), ('\u{455}', ['\u{405}', '\u{0}', '\u{0}']),
+         ('\u{456}', ['\u{406}', '\u{0}', '\u{0}']), ('\u{457}', ['\u{407}', '\u{0}', '\u{0}']),
+         ('\u{458}', ['\u{408}', '\u{0}', '\u{0}']), ('\u{459}', ['\u{409}', '\u{0}', '\u{0}']),
+         ('\u{45a}', ['\u{40a}', '\u{0}', '\u{0}']), ('\u{45b}', ['\u{40b}', '\u{0}', '\u{0}']),
+         ('\u{45c}', ['\u{40c}', '\u{0}', '\u{0}']), ('\u{45d}', ['\u{40d}', '\u{0}', '\u{0}']),
+         ('\u{45e}', ['\u{40e}', '\u{0}', '\u{0}']), ('\u{45f}', ['\u{40f}', '\u{0}', '\u{0}']),
+         ('\u{461}', ['\u{460}', '\u{0}', '\u{0}']), ('\u{463}', ['\u{462}', '\u{0}', '\u{0}']),
+         ('\u{465}', ['\u{464}', '\u{0}', '\u{0}']), ('\u{467}', ['\u{466}', '\u{0}', '\u{0}']),
+         ('\u{469}', ['\u{468}', '\u{0}', '\u{0}']), ('\u{46b}', ['\u{46a}', '\u{0}', '\u{0}']),
+         ('\u{46d}', ['\u{46c}', '\u{0}', '\u{0}']), ('\u{46f}', ['\u{46e}', '\u{0}', '\u{0}']),
+         ('\u{471}', ['\u{470}', '\u{0}', '\u{0}']), ('\u{473}', ['\u{472}', '\u{0}', '\u{0}']),
+         ('\u{475}', ['\u{474}', '\u{0}', '\u{0}']), ('\u{477}', ['\u{476}', '\u{0}', '\u{0}']),
+         ('\u{479}', ['\u{478}', '\u{0}', '\u{0}']), ('\u{47b}', ['\u{47a}', '\u{0}', '\u{0}']),
+         ('\u{47d}', ['\u{47c}', '\u{0}', '\u{0}']), ('\u{47f}', ['\u{47e}', '\u{0}', '\u{0}']),
+         ('\u{481}', ['\u{480}', '\u{0}', '\u{0}']), ('\u{48b}', ['\u{48a}', '\u{0}', '\u{0}']),
+         ('\u{48d}', ['\u{48c}', '\u{0}', '\u{0}']), ('\u{48f}', ['\u{48e}', '\u{0}', '\u{0}']),
+         ('\u{491}', ['\u{490}', '\u{0}', '\u{0}']), ('\u{493}', ['\u{492}', '\u{0}', '\u{0}']),
+         ('\u{495}', ['\u{494}', '\u{0}', '\u{0}']), ('\u{497}', ['\u{496}', '\u{0}', '\u{0}']),
+         ('\u{499}', ['\u{498}', '\u{0}', '\u{0}']), ('\u{49b}', ['\u{49a}', '\u{0}', '\u{0}']),
+         ('\u{49d}', ['\u{49c}', '\u{0}', '\u{0}']), ('\u{49f}', ['\u{49e}', '\u{0}', '\u{0}']),
+         ('\u{4a1}', ['\u{4a0}', '\u{0}', '\u{0}']), ('\u{4a3}', ['\u{4a2}', '\u{0}', '\u{0}']),
+         ('\u{4a5}', ['\u{4a4}', '\u{0}', '\u{0}']), ('\u{4a7}', ['\u{4a6}', '\u{0}', '\u{0}']),
+         ('\u{4a9}', ['\u{4a8}', '\u{0}', '\u{0}']), ('\u{4ab}', ['\u{4aa}', '\u{0}', '\u{0}']),
+         ('\u{4ad}', ['\u{4ac}', '\u{0}', '\u{0}']), ('\u{4af}', ['\u{4ae}', '\u{0}', '\u{0}']),
+         ('\u{4b1}', ['\u{4b0}', '\u{0}', '\u{0}']), ('\u{4b3}', ['\u{4b2}', '\u{0}', '\u{0}']),
+         ('\u{4b5}', ['\u{4b4}', '\u{0}', '\u{0}']), ('\u{4b7}', ['\u{4b6}', '\u{0}', '\u{0}']),
+         ('\u{4b9}', ['\u{4b8}', '\u{0}', '\u{0}']), ('\u{4bb}', ['\u{4ba}', '\u{0}', '\u{0}']),
+         ('\u{4bd}', ['\u{4bc}', '\u{0}', '\u{0}']), ('\u{4bf}', ['\u{4be}', '\u{0}', '\u{0}']),
+         ('\u{4c2}', ['\u{4c1}', '\u{0}', '\u{0}']), ('\u{4c4}', ['\u{4c3}', '\u{0}', '\u{0}']),
+         ('\u{4c6}', ['\u{4c5}', '\u{0}', '\u{0}']), ('\u{4c8}', ['\u{4c7}', '\u{0}', '\u{0}']),
+         ('\u{4ca}', ['\u{4c9}', '\u{0}', '\u{0}']), ('\u{4cc}', ['\u{4cb}', '\u{0}', '\u{0}']),
+         ('\u{4ce}', ['\u{4cd}', '\u{0}', '\u{0}']), ('\u{4cf}', ['\u{4c0}', '\u{0}', '\u{0}']),
+         ('\u{4d1}', ['\u{4d0}', '\u{0}', '\u{0}']), ('\u{4d3}', ['\u{4d2}', '\u{0}', '\u{0}']),
+         ('\u{4d5}', ['\u{4d4}', '\u{0}', '\u{0}']), ('\u{4d7}', ['\u{4d6}', '\u{0}', '\u{0}']),
+         ('\u{4d9}', ['\u{4d8}', '\u{0}', '\u{0}']), ('\u{4db}', ['\u{4da}', '\u{0}', '\u{0}']),
+         ('\u{4dd}', ['\u{4dc}', '\u{0}', '\u{0}']), ('\u{4df}', ['\u{4de}', '\u{0}', '\u{0}']),
+         ('\u{4e1}', ['\u{4e0}', '\u{0}', '\u{0}']), ('\u{4e3}', ['\u{4e2}', '\u{0}', '\u{0}']),
+         ('\u{4e5}', ['\u{4e4}', '\u{0}', '\u{0}']), ('\u{4e7}', ['\u{4e6}', '\u{0}', '\u{0}']),
+         ('\u{4e9}', ['\u{4e8}', '\u{0}', '\u{0}']), ('\u{4eb}', ['\u{4ea}', '\u{0}', '\u{0}']),
+         ('\u{4ed}', ['\u{4ec}', '\u{0}', '\u{0}']), ('\u{4ef}', ['\u{4ee}', '\u{0}', '\u{0}']),
+         ('\u{4f1}', ['\u{4f0}', '\u{0}', '\u{0}']), ('\u{4f3}', ['\u{4f2}', '\u{0}', '\u{0}']),
+         ('\u{4f5}', ['\u{4f4}', '\u{0}', '\u{0}']), ('\u{4f7}', ['\u{4f6}', '\u{0}', '\u{0}']),
+         ('\u{4f9}', ['\u{4f8}', '\u{0}', '\u{0}']), ('\u{4fb}', ['\u{4fa}', '\u{0}', '\u{0}']),
+         ('\u{4fd}', ['\u{4fc}', '\u{0}', '\u{0}']), ('\u{4ff}', ['\u{4fe}', '\u{0}', '\u{0}']),
+         ('\u{501}', ['\u{500}', '\u{0}', '\u{0}']), ('\u{503}', ['\u{502}', '\u{0}', '\u{0}']),
+         ('\u{505}', ['\u{504}', '\u{0}', '\u{0}']), ('\u{507}', ['\u{506}', '\u{0}', '\u{0}']),
+         ('\u{509}', ['\u{508}', '\u{0}', '\u{0}']), ('\u{50b}', ['\u{50a}', '\u{0}', '\u{0}']),
+         ('\u{50d}', ['\u{50c}', '\u{0}', '\u{0}']), ('\u{50f}', ['\u{50e}', '\u{0}', '\u{0}']),
+         ('\u{511}', ['\u{510}', '\u{0}', '\u{0}']), ('\u{513}', ['\u{512}', '\u{0}', '\u{0}']),
+         ('\u{515}', ['\u{514}', '\u{0}', '\u{0}']), ('\u{517}', ['\u{516}', '\u{0}', '\u{0}']),
+         ('\u{519}', ['\u{518}', '\u{0}', '\u{0}']), ('\u{51b}', ['\u{51a}', '\u{0}', '\u{0}']),
+         ('\u{51d}', ['\u{51c}', '\u{0}', '\u{0}']), ('\u{51f}', ['\u{51e}', '\u{0}', '\u{0}']),
+         ('\u{521}', ['\u{520}', '\u{0}', '\u{0}']), ('\u{523}', ['\u{522}', '\u{0}', '\u{0}']),
+         ('\u{525}', ['\u{524}', '\u{0}', '\u{0}']), ('\u{527}', ['\u{526}', '\u{0}', '\u{0}']),
+         ('\u{529}', ['\u{528}', '\u{0}', '\u{0}']), ('\u{52b}', ['\u{52a}', '\u{0}', '\u{0}']),
+         ('\u{52d}', ['\u{52c}', '\u{0}', '\u{0}']), ('\u{52f}', ['\u{52e}', '\u{0}', '\u{0}']),
+         ('\u{561}', ['\u{531}', '\u{0}', '\u{0}']), ('\u{562}', ['\u{532}', '\u{0}', '\u{0}']),
+         ('\u{563}', ['\u{533}', '\u{0}', '\u{0}']), ('\u{564}', ['\u{534}', '\u{0}', '\u{0}']),
+         ('\u{565}', ['\u{535}', '\u{0}', '\u{0}']), ('\u{566}', ['\u{536}', '\u{0}', '\u{0}']),
+         ('\u{567}', ['\u{537}', '\u{0}', '\u{0}']), ('\u{568}', ['\u{538}', '\u{0}', '\u{0}']),
+         ('\u{569}', ['\u{539}', '\u{0}', '\u{0}']), ('\u{56a}', ['\u{53a}', '\u{0}', '\u{0}']),
+         ('\u{56b}', ['\u{53b}', '\u{0}', '\u{0}']), ('\u{56c}', ['\u{53c}', '\u{0}', '\u{0}']),
+         ('\u{56d}', ['\u{53d}', '\u{0}', '\u{0}']), ('\u{56e}', ['\u{53e}', '\u{0}', '\u{0}']),
+         ('\u{56f}', ['\u{53f}', '\u{0}', '\u{0}']), ('\u{570}', ['\u{540}', '\u{0}', '\u{0}']),
+         ('\u{571}', ['\u{541}', '\u{0}', '\u{0}']), ('\u{572}', ['\u{542}', '\u{0}', '\u{0}']),
+         ('\u{573}', ['\u{543}', '\u{0}', '\u{0}']), ('\u{574}', ['\u{544}', '\u{0}', '\u{0}']),
+         ('\u{575}', ['\u{545}', '\u{0}', '\u{0}']), ('\u{576}', ['\u{546}', '\u{0}', '\u{0}']),
+         ('\u{577}', ['\u{547}', '\u{0}', '\u{0}']), ('\u{578}', ['\u{548}', '\u{0}', '\u{0}']),
+         ('\u{579}', ['\u{549}', '\u{0}', '\u{0}']), ('\u{57a}', ['\u{54a}', '\u{0}', '\u{0}']),
+         ('\u{57b}', ['\u{54b}', '\u{0}', '\u{0}']), ('\u{57c}', ['\u{54c}', '\u{0}', '\u{0}']),
+         ('\u{57d}', ['\u{54d}', '\u{0}', '\u{0}']), ('\u{57e}', ['\u{54e}', '\u{0}', '\u{0}']),
+         ('\u{57f}', ['\u{54f}', '\u{0}', '\u{0}']), ('\u{580}', ['\u{550}', '\u{0}', '\u{0}']),
+         ('\u{581}', ['\u{551}', '\u{0}', '\u{0}']), ('\u{582}', ['\u{552}', '\u{0}', '\u{0}']),
+         ('\u{583}', ['\u{553}', '\u{0}', '\u{0}']), ('\u{584}', ['\u{554}', '\u{0}', '\u{0}']),
+         ('\u{585}', ['\u{555}', '\u{0}', '\u{0}']), ('\u{586}', ['\u{556}', '\u{0}', '\u{0}']),
+         ('\u{587}', ['\u{535}', '\u{552}', '\u{0}']), ('\u{10d0}', ['\u{1c90}', '\u{0}', '\u{0}']),
+         ('\u{10d1}', ['\u{1c91}', '\u{0}', '\u{0}']), ('\u{10d2}', ['\u{1c92}', '\u{0}', '\u{0}']),
+         ('\u{10d3}', ['\u{1c93}', '\u{0}', '\u{0}']), ('\u{10d4}', ['\u{1c94}', '\u{0}', '\u{0}']),
+         ('\u{10d5}', ['\u{1c95}', '\u{0}', '\u{0}']), ('\u{10d6}', ['\u{1c96}', '\u{0}', '\u{0}']),
+         ('\u{10d7}', ['\u{1c97}', '\u{0}', '\u{0}']), ('\u{10d8}', ['\u{1c98}', '\u{0}', '\u{0}']),
+         ('\u{10d9}', ['\u{1c99}', '\u{0}', '\u{0}']), ('\u{10da}', ['\u{1c9a}', '\u{0}', '\u{0}']),
+         ('\u{10db}', ['\u{1c9b}', '\u{0}', '\u{0}']), ('\u{10dc}', ['\u{1c9c}', '\u{0}', '\u{0}']),
+         ('\u{10dd}', ['\u{1c9d}', '\u{0}', '\u{0}']), ('\u{10de}', ['\u{1c9e}', '\u{0}', '\u{0}']),
+         ('\u{10df}', ['\u{1c9f}', '\u{0}', '\u{0}']), ('\u{10e0}', ['\u{1ca0}', '\u{0}', '\u{0}']),
+         ('\u{10e1}', ['\u{1ca1}', '\u{0}', '\u{0}']), ('\u{10e2}', ['\u{1ca2}', '\u{0}', '\u{0}']),
+         ('\u{10e3}', ['\u{1ca3}', '\u{0}', '\u{0}']), ('\u{10e4}', ['\u{1ca4}', '\u{0}', '\u{0}']),
+         ('\u{10e5}', ['\u{1ca5}', '\u{0}', '\u{0}']), ('\u{10e6}', ['\u{1ca6}', '\u{0}', '\u{0}']),
+         ('\u{10e7}', ['\u{1ca7}', '\u{0}', '\u{0}']), ('\u{10e8}', ['\u{1ca8}', '\u{0}', '\u{0}']),
+         ('\u{10e9}', ['\u{1ca9}', '\u{0}', '\u{0}']), ('\u{10ea}', ['\u{1caa}', '\u{0}', '\u{0}']),
+         ('\u{10eb}', ['\u{1cab}', '\u{0}', '\u{0}']), ('\u{10ec}', ['\u{1cac}', '\u{0}', '\u{0}']),
+         ('\u{10ed}', ['\u{1cad}', '\u{0}', '\u{0}']), ('\u{10ee}', ['\u{1cae}', '\u{0}', '\u{0}']),
+         ('\u{10ef}', ['\u{1caf}', '\u{0}', '\u{0}']), ('\u{10f0}', ['\u{1cb0}', '\u{0}', '\u{0}']),
+         ('\u{10f1}', ['\u{1cb1}', '\u{0}', '\u{0}']), ('\u{10f2}', ['\u{1cb2}', '\u{0}', '\u{0}']),
+         ('\u{10f3}', ['\u{1cb3}', '\u{0}', '\u{0}']), ('\u{10f4}', ['\u{1cb4}', '\u{0}', '\u{0}']),
+         ('\u{10f5}', ['\u{1cb5}', '\u{0}', '\u{0}']), ('\u{10f6}', ['\u{1cb6}', '\u{0}', '\u{0}']),
+         ('\u{10f7}', ['\u{1cb7}', '\u{0}', '\u{0}']), ('\u{10f8}', ['\u{1cb8}', '\u{0}', '\u{0}']),
+         ('\u{10f9}', ['\u{1cb9}', '\u{0}', '\u{0}']), ('\u{10fa}', ['\u{1cba}', '\u{0}', '\u{0}']),
+         ('\u{10fd}', ['\u{1cbd}', '\u{0}', '\u{0}']), ('\u{10fe}', ['\u{1cbe}', '\u{0}', '\u{0}']),
+         ('\u{10ff}', ['\u{1cbf}', '\u{0}', '\u{0}']), ('\u{13f8}', ['\u{13f0}', '\u{0}', '\u{0}']),
+         ('\u{13f9}', ['\u{13f1}', '\u{0}', '\u{0}']), ('\u{13fa}', ['\u{13f2}', '\u{0}', '\u{0}']),
+         ('\u{13fb}', ['\u{13f3}', '\u{0}', '\u{0}']), ('\u{13fc}', ['\u{13f4}', '\u{0}', '\u{0}']),
+         ('\u{13fd}', ['\u{13f5}', '\u{0}', '\u{0}']), ('\u{1c80}', ['\u{412}', '\u{0}', '\u{0}']),
+         ('\u{1c81}', ['\u{414}', '\u{0}', '\u{0}']), ('\u{1c82}', ['\u{41e}', '\u{0}', '\u{0}']),
+         ('\u{1c83}', ['\u{421}', '\u{0}', '\u{0}']), ('\u{1c84}', ['\u{422}', '\u{0}', '\u{0}']),
+         ('\u{1c85}', ['\u{422}', '\u{0}', '\u{0}']), ('\u{1c86}', ['\u{42a}', '\u{0}', '\u{0}']),
+         ('\u{1c87}', ['\u{462}', '\u{0}', '\u{0}']), ('\u{1c88}', ['\u{a64a}', '\u{0}', '\u{0}']),
+         ('\u{1d79}', ['\u{a77d}', '\u{0}', '\u{0}']), ('\u{1d7d}', ['\u{2c63}', '\u{0}', '\u{0}']),
+         ('\u{1d8e}', ['\u{a7c6}', '\u{0}', '\u{0}']), ('\u{1e01}', ['\u{1e00}', '\u{0}', '\u{0}']),
+         ('\u{1e03}', ['\u{1e02}', '\u{0}', '\u{0}']), ('\u{1e05}', ['\u{1e04}', '\u{0}', '\u{0}']),
+         ('\u{1e07}', ['\u{1e06}', '\u{0}', '\u{0}']), ('\u{1e09}', ['\u{1e08}', '\u{0}', '\u{0}']),
+         ('\u{1e0b}', ['\u{1e0a}', '\u{0}', '\u{0}']), ('\u{1e0d}', ['\u{1e0c}', '\u{0}', '\u{0}']),
+         ('\u{1e0f}', ['\u{1e0e}', '\u{0}', '\u{0}']), ('\u{1e11}', ['\u{1e10}', '\u{0}', '\u{0}']),
+         ('\u{1e13}', ['\u{1e12}', '\u{0}', '\u{0}']), ('\u{1e15}', ['\u{1e14}', '\u{0}', '\u{0}']),
+         ('\u{1e17}', ['\u{1e16}', '\u{0}', '\u{0}']), ('\u{1e19}', ['\u{1e18}', '\u{0}', '\u{0}']),
+         ('\u{1e1b}', ['\u{1e1a}', '\u{0}', '\u{0}']), ('\u{1e1d}', ['\u{1e1c}', '\u{0}', '\u{0}']),
+         ('\u{1e1f}', ['\u{1e1e}', '\u{0}', '\u{0}']), ('\u{1e21}', ['\u{1e20}', '\u{0}', '\u{0}']),
+         ('\u{1e23}', ['\u{1e22}', '\u{0}', '\u{0}']), ('\u{1e25}', ['\u{1e24}', '\u{0}', '\u{0}']),
+         ('\u{1e27}', ['\u{1e26}', '\u{0}', '\u{0}']), ('\u{1e29}', ['\u{1e28}', '\u{0}', '\u{0}']),
+         ('\u{1e2b}', ['\u{1e2a}', '\u{0}', '\u{0}']), ('\u{1e2d}', ['\u{1e2c}', '\u{0}', '\u{0}']),
+         ('\u{1e2f}', ['\u{1e2e}', '\u{0}', '\u{0}']), ('\u{1e31}', ['\u{1e30}', '\u{0}', '\u{0}']),
+         ('\u{1e33}', ['\u{1e32}', '\u{0}', '\u{0}']), ('\u{1e35}', ['\u{1e34}', '\u{0}', '\u{0}']),
+         ('\u{1e37}', ['\u{1e36}', '\u{0}', '\u{0}']), ('\u{1e39}', ['\u{1e38}', '\u{0}', '\u{0}']),
+         ('\u{1e3b}', ['\u{1e3a}', '\u{0}', '\u{0}']), ('\u{1e3d}', ['\u{1e3c}', '\u{0}', '\u{0}']),
+         ('\u{1e3f}', ['\u{1e3e}', '\u{0}', '\u{0}']), ('\u{1e41}', ['\u{1e40}', '\u{0}', '\u{0}']),
+         ('\u{1e43}', ['\u{1e42}', '\u{0}', '\u{0}']), ('\u{1e45}', ['\u{1e44}', '\u{0}', '\u{0}']),
+         ('\u{1e47}', ['\u{1e46}', '\u{0}', '\u{0}']), ('\u{1e49}', ['\u{1e48}', '\u{0}', '\u{0}']),
+         ('\u{1e4b}', ['\u{1e4a}', '\u{0}', '\u{0}']), ('\u{1e4d}', ['\u{1e4c}', '\u{0}', '\u{0}']),
+         ('\u{1e4f}', ['\u{1e4e}', '\u{0}', '\u{0}']), ('\u{1e51}', ['\u{1e50}', '\u{0}', '\u{0}']),
+         ('\u{1e53}', ['\u{1e52}', '\u{0}', '\u{0}']), ('\u{1e55}', ['\u{1e54}', '\u{0}', '\u{0}']),
+         ('\u{1e57}', ['\u{1e56}', '\u{0}', '\u{0}']), ('\u{1e59}', ['\u{1e58}', '\u{0}', '\u{0}']),
+         ('\u{1e5b}', ['\u{1e5a}', '\u{0}', '\u{0}']), ('\u{1e5d}', ['\u{1e5c}', '\u{0}', '\u{0}']),
+         ('\u{1e5f}', ['\u{1e5e}', '\u{0}', '\u{0}']), ('\u{1e61}', ['\u{1e60}', '\u{0}', '\u{0}']),
+         ('\u{1e63}', ['\u{1e62}', '\u{0}', '\u{0}']), ('\u{1e65}', ['\u{1e64}', '\u{0}', '\u{0}']),
+         ('\u{1e67}', ['\u{1e66}', '\u{0}', '\u{0}']), ('\u{1e69}', ['\u{1e68}', '\u{0}', '\u{0}']),
+         ('\u{1e6b}', ['\u{1e6a}', '\u{0}', '\u{0}']), ('\u{1e6d}', ['\u{1e6c}', '\u{0}', '\u{0}']),
+         ('\u{1e6f}', ['\u{1e6e}', '\u{0}', '\u{0}']), ('\u{1e71}', ['\u{1e70}', '\u{0}', '\u{0}']),
+         ('\u{1e73}', ['\u{1e72}', '\u{0}', '\u{0}']), ('\u{1e75}', ['\u{1e74}', '\u{0}', '\u{0}']),
+         ('\u{1e77}', ['\u{1e76}', '\u{0}', '\u{0}']), ('\u{1e79}', ['\u{1e78}', '\u{0}', '\u{0}']),
+         ('\u{1e7b}', ['\u{1e7a}', '\u{0}', '\u{0}']), ('\u{1e7d}', ['\u{1e7c}', '\u{0}', '\u{0}']),
+         ('\u{1e7f}', ['\u{1e7e}', '\u{0}', '\u{0}']), ('\u{1e81}', ['\u{1e80}', '\u{0}', '\u{0}']),
+         ('\u{1e83}', ['\u{1e82}', '\u{0}', '\u{0}']), ('\u{1e85}', ['\u{1e84}', '\u{0}', '\u{0}']),
+         ('\u{1e87}', ['\u{1e86}', '\u{0}', '\u{0}']), ('\u{1e89}', ['\u{1e88}', '\u{0}', '\u{0}']),
+         ('\u{1e8b}', ['\u{1e8a}', '\u{0}', '\u{0}']), ('\u{1e8d}', ['\u{1e8c}', '\u{0}', '\u{0}']),
+         ('\u{1e8f}', ['\u{1e8e}', '\u{0}', '\u{0}']), ('\u{1e91}', ['\u{1e90}', '\u{0}', '\u{0}']),
+         ('\u{1e93}', ['\u{1e92}', '\u{0}', '\u{0}']), ('\u{1e95}', ['\u{1e94}', '\u{0}', '\u{0}']),
+         ('\u{1e96}', ['H', '\u{331}', '\u{0}']), ('\u{1e97}', ['T', '\u{308}', '\u{0}']),
+         ('\u{1e98}', ['W', '\u{30a}', '\u{0}']), ('\u{1e99}', ['Y', '\u{30a}', '\u{0}']),
+         ('\u{1e9a}', ['A', '\u{2be}', '\u{0}']), ('\u{1e9b}', ['\u{1e60}', '\u{0}', '\u{0}']),
+         ('\u{1ea1}', ['\u{1ea0}', '\u{0}', '\u{0}']), ('\u{1ea3}', ['\u{1ea2}', '\u{0}', '\u{0}']),
+         ('\u{1ea5}', ['\u{1ea4}', '\u{0}', '\u{0}']), ('\u{1ea7}', ['\u{1ea6}', '\u{0}', '\u{0}']),
+         ('\u{1ea9}', ['\u{1ea8}', '\u{0}', '\u{0}']), ('\u{1eab}', ['\u{1eaa}', '\u{0}', '\u{0}']),
+         ('\u{1ead}', ['\u{1eac}', '\u{0}', '\u{0}']), ('\u{1eaf}', ['\u{1eae}', '\u{0}', '\u{0}']),
+         ('\u{1eb1}', ['\u{1eb0}', '\u{0}', '\u{0}']), ('\u{1eb3}', ['\u{1eb2}', '\u{0}', '\u{0}']),
+         ('\u{1eb5}', ['\u{1eb4}', '\u{0}', '\u{0}']), ('\u{1eb7}', ['\u{1eb6}', '\u{0}', '\u{0}']),
+         ('\u{1eb9}', ['\u{1eb8}', '\u{0}', '\u{0}']), ('\u{1ebb}', ['\u{1eba}', '\u{0}', '\u{0}']),
+         ('\u{1ebd}', ['\u{1ebc}', '\u{0}', '\u{0}']), ('\u{1ebf}', ['\u{1ebe}', '\u{0}', '\u{0}']),
+         ('\u{1ec1}', ['\u{1ec0}', '\u{0}', '\u{0}']), ('\u{1ec3}', ['\u{1ec2}', '\u{0}', '\u{0}']),
+         ('\u{1ec5}', ['\u{1ec4}', '\u{0}', '\u{0}']), ('\u{1ec7}', ['\u{1ec6}', '\u{0}', '\u{0}']),
+         ('\u{1ec9}', ['\u{1ec8}', '\u{0}', '\u{0}']), ('\u{1ecb}', ['\u{1eca}', '\u{0}', '\u{0}']),
+         ('\u{1ecd}', ['\u{1ecc}', '\u{0}', '\u{0}']), ('\u{1ecf}', ['\u{1ece}', '\u{0}', '\u{0}']),
+         ('\u{1ed1}', ['\u{1ed0}', '\u{0}', '\u{0}']), ('\u{1ed3}', ['\u{1ed2}', '\u{0}', '\u{0}']),
+         ('\u{1ed5}', ['\u{1ed4}', '\u{0}', '\u{0}']), ('\u{1ed7}', ['\u{1ed6}', '\u{0}', '\u{0}']),
+         ('\u{1ed9}', ['\u{1ed8}', '\u{0}', '\u{0}']), ('\u{1edb}', ['\u{1eda}', '\u{0}', '\u{0}']),
+         ('\u{1edd}', ['\u{1edc}', '\u{0}', '\u{0}']), ('\u{1edf}', ['\u{1ede}', '\u{0}', '\u{0}']),
+         ('\u{1ee1}', ['\u{1ee0}', '\u{0}', '\u{0}']), ('\u{1ee3}', ['\u{1ee2}', '\u{0}', '\u{0}']),
+         ('\u{1ee5}', ['\u{1ee4}', '\u{0}', '\u{0}']), ('\u{1ee7}', ['\u{1ee6}', '\u{0}', '\u{0}']),
+         ('\u{1ee9}', ['\u{1ee8}', '\u{0}', '\u{0}']), ('\u{1eeb}', ['\u{1eea}', '\u{0}', '\u{0}']),
+         ('\u{1eed}', ['\u{1eec}', '\u{0}', '\u{0}']), ('\u{1eef}', ['\u{1eee}', '\u{0}', '\u{0}']),
+         ('\u{1ef1}', ['\u{1ef0}', '\u{0}', '\u{0}']), ('\u{1ef3}', ['\u{1ef2}', '\u{0}', '\u{0}']),
+         ('\u{1ef5}', ['\u{1ef4}', '\u{0}', '\u{0}']), ('\u{1ef7}', ['\u{1ef6}', '\u{0}', '\u{0}']),
+         ('\u{1ef9}', ['\u{1ef8}', '\u{0}', '\u{0}']), ('\u{1efb}', ['\u{1efa}', '\u{0}', '\u{0}']),
+         ('\u{1efd}', ['\u{1efc}', '\u{0}', '\u{0}']), ('\u{1eff}', ['\u{1efe}', '\u{0}', '\u{0}']),
+         ('\u{1f00}', ['\u{1f08}', '\u{0}', '\u{0}']), ('\u{1f01}', ['\u{1f09}', '\u{0}', '\u{0}']),
+         ('\u{1f02}', ['\u{1f0a}', '\u{0}', '\u{0}']), ('\u{1f03}', ['\u{1f0b}', '\u{0}', '\u{0}']),
+         ('\u{1f04}', ['\u{1f0c}', '\u{0}', '\u{0}']), ('\u{1f05}', ['\u{1f0d}', '\u{0}', '\u{0}']),
+         ('\u{1f06}', ['\u{1f0e}', '\u{0}', '\u{0}']), ('\u{1f07}', ['\u{1f0f}', '\u{0}', '\u{0}']),
+         ('\u{1f10}', ['\u{1f18}', '\u{0}', '\u{0}']), ('\u{1f11}', ['\u{1f19}', '\u{0}', '\u{0}']),
+         ('\u{1f12}', ['\u{1f1a}', '\u{0}', '\u{0}']), ('\u{1f13}', ['\u{1f1b}', '\u{0}', '\u{0}']),
+         ('\u{1f14}', ['\u{1f1c}', '\u{0}', '\u{0}']), ('\u{1f15}', ['\u{1f1d}', '\u{0}', '\u{0}']),
+         ('\u{1f20}', ['\u{1f28}', '\u{0}', '\u{0}']), ('\u{1f21}', ['\u{1f29}', '\u{0}', '\u{0}']),
+         ('\u{1f22}', ['\u{1f2a}', '\u{0}', '\u{0}']), ('\u{1f23}', ['\u{1f2b}', '\u{0}', '\u{0}']),
+         ('\u{1f24}', ['\u{1f2c}', '\u{0}', '\u{0}']), ('\u{1f25}', ['\u{1f2d}', '\u{0}', '\u{0}']),
+         ('\u{1f26}', ['\u{1f2e}', '\u{0}', '\u{0}']), ('\u{1f27}', ['\u{1f2f}', '\u{0}', '\u{0}']),
+         ('\u{1f30}', ['\u{1f38}', '\u{0}', '\u{0}']), ('\u{1f31}', ['\u{1f39}', '\u{0}', '\u{0}']),
+         ('\u{1f32}', ['\u{1f3a}', '\u{0}', '\u{0}']), ('\u{1f33}', ['\u{1f3b}', '\u{0}', '\u{0}']),
+         ('\u{1f34}', ['\u{1f3c}', '\u{0}', '\u{0}']), ('\u{1f35}', ['\u{1f3d}', '\u{0}', '\u{0}']),
+         ('\u{1f36}', ['\u{1f3e}', '\u{0}', '\u{0}']), ('\u{1f37}', ['\u{1f3f}', '\u{0}', '\u{0}']),
+         ('\u{1f40}', ['\u{1f48}', '\u{0}', '\u{0}']), ('\u{1f41}', ['\u{1f49}', '\u{0}', '\u{0}']),
+         ('\u{1f42}', ['\u{1f4a}', '\u{0}', '\u{0}']), ('\u{1f43}', ['\u{1f4b}', '\u{0}', '\u{0}']),
+         ('\u{1f44}', ['\u{1f4c}', '\u{0}', '\u{0}']), ('\u{1f45}', ['\u{1f4d}', '\u{0}', '\u{0}']),
+         ('\u{1f50}', ['\u{3a5}', '\u{313}', '\u{0}']), ('\u{1f51}', ['\u{1f59}', '\u{0}', '\u{0}']),
+         ('\u{1f52}', ['\u{3a5}', '\u{313}', '\u{300}']),
+         ('\u{1f53}', ['\u{1f5b}', '\u{0}', '\u{0}']),
+         ('\u{1f54}', ['\u{3a5}', '\u{313}', '\u{301}']),
+         ('\u{1f55}', ['\u{1f5d}', '\u{0}', '\u{0}']),
+         ('\u{1f56}', ['\u{3a5}', '\u{313}', '\u{342}']),
+         ('\u{1f57}', ['\u{1f5f}', '\u{0}', '\u{0}']), ('\u{1f60}', ['\u{1f68}', '\u{0}', '\u{0}']),
+         ('\u{1f61}', ['\u{1f69}', '\u{0}', '\u{0}']), ('\u{1f62}', ['\u{1f6a}', '\u{0}', '\u{0}']),
+         ('\u{1f63}', ['\u{1f6b}', '\u{0}', '\u{0}']), ('\u{1f64}', ['\u{1f6c}', '\u{0}', '\u{0}']),
+         ('\u{1f65}', ['\u{1f6d}', '\u{0}', '\u{0}']), ('\u{1f66}', ['\u{1f6e}', '\u{0}', '\u{0}']),
+         ('\u{1f67}', ['\u{1f6f}', '\u{0}', '\u{0}']), ('\u{1f70}', ['\u{1fba}', '\u{0}', '\u{0}']),
+         ('\u{1f71}', ['\u{1fbb}', '\u{0}', '\u{0}']), ('\u{1f72}', ['\u{1fc8}', '\u{0}', '\u{0}']),
+         ('\u{1f73}', ['\u{1fc9}', '\u{0}', '\u{0}']), ('\u{1f74}', ['\u{1fca}', '\u{0}', '\u{0}']),
+         ('\u{1f75}', ['\u{1fcb}', '\u{0}', '\u{0}']), ('\u{1f76}', ['\u{1fda}', '\u{0}', '\u{0}']),
+         ('\u{1f77}', ['\u{1fdb}', '\u{0}', '\u{0}']), ('\u{1f78}', ['\u{1ff8}', '\u{0}', '\u{0}']),
+         ('\u{1f79}', ['\u{1ff9}', '\u{0}', '\u{0}']), ('\u{1f7a}', ['\u{1fea}', '\u{0}', '\u{0}']),
+         ('\u{1f7b}', ['\u{1feb}', '\u{0}', '\u{0}']), ('\u{1f7c}', ['\u{1ffa}', '\u{0}', '\u{0}']),
+         ('\u{1f7d}', ['\u{1ffb}', '\u{0}', '\u{0}']),
+         ('\u{1f80}', ['\u{1f08}', '\u{399}', '\u{0}']),
+         ('\u{1f81}', ['\u{1f09}', '\u{399}', '\u{0}']),
+         ('\u{1f82}', ['\u{1f0a}', '\u{399}', '\u{0}']),
+         ('\u{1f83}', ['\u{1f0b}', '\u{399}', '\u{0}']),
+         ('\u{1f84}', ['\u{1f0c}', '\u{399}', '\u{0}']),
+         ('\u{1f85}', ['\u{1f0d}', '\u{399}', '\u{0}']),
+         ('\u{1f86}', ['\u{1f0e}', '\u{399}', '\u{0}']),
+         ('\u{1f87}', ['\u{1f0f}', '\u{399}', '\u{0}']),
+         ('\u{1f88}', ['\u{1f08}', '\u{399}', '\u{0}']),
+         ('\u{1f89}', ['\u{1f09}', '\u{399}', '\u{0}']),
+         ('\u{1f8a}', ['\u{1f0a}', '\u{399}', '\u{0}']),
+         ('\u{1f8b}', ['\u{1f0b}', '\u{399}', '\u{0}']),
+         ('\u{1f8c}', ['\u{1f0c}', '\u{399}', '\u{0}']),
+         ('\u{1f8d}', ['\u{1f0d}', '\u{399}', '\u{0}']),
+         ('\u{1f8e}', ['\u{1f0e}', '\u{399}', '\u{0}']),
+         ('\u{1f8f}', ['\u{1f0f}', '\u{399}', '\u{0}']),
+         ('\u{1f90}', ['\u{1f28}', '\u{399}', '\u{0}']),
+         ('\u{1f91}', ['\u{1f29}', '\u{399}', '\u{0}']),
+         ('\u{1f92}', ['\u{1f2a}', '\u{399}', '\u{0}']),
+         ('\u{1f93}', ['\u{1f2b}', '\u{399}', '\u{0}']),
+         ('\u{1f94}', ['\u{1f2c}', '\u{399}', '\u{0}']),
+         ('\u{1f95}', ['\u{1f2d}', '\u{399}', '\u{0}']),
+         ('\u{1f96}', ['\u{1f2e}', '\u{399}', '\u{0}']),
+         ('\u{1f97}', ['\u{1f2f}', '\u{399}', '\u{0}']),
+         ('\u{1f98}', ['\u{1f28}', '\u{399}', '\u{0}']),
+         ('\u{1f99}', ['\u{1f29}', '\u{399}', '\u{0}']),
+         ('\u{1f9a}', ['\u{1f2a}', '\u{399}', '\u{0}']),
+         ('\u{1f9b}', ['\u{1f2b}', '\u{399}', '\u{0}']),
+         ('\u{1f9c}', ['\u{1f2c}', '\u{399}', '\u{0}']),
+         ('\u{1f9d}', ['\u{1f2d}', '\u{399}', '\u{0}']),
+         ('\u{1f9e}', ['\u{1f2e}', '\u{399}', '\u{0}']),
+         ('\u{1f9f}', ['\u{1f2f}', '\u{399}', '\u{0}']),
+         ('\u{1fa0}', ['\u{1f68}', '\u{399}', '\u{0}']),
+         ('\u{1fa1}', ['\u{1f69}', '\u{399}', '\u{0}']),
+         ('\u{1fa2}', ['\u{1f6a}', '\u{399}', '\u{0}']),
+         ('\u{1fa3}', ['\u{1f6b}', '\u{399}', '\u{0}']),
+         ('\u{1fa4}', ['\u{1f6c}', '\u{399}', '\u{0}']),
+         ('\u{1fa5}', ['\u{1f6d}', '\u{399}', '\u{0}']),
+         ('\u{1fa6}', ['\u{1f6e}', '\u{399}', '\u{0}']),
+         ('\u{1fa7}', ['\u{1f6f}', '\u{399}', '\u{0}']),
+         ('\u{1fa8}', ['\u{1f68}', '\u{399}', '\u{0}']),
+         ('\u{1fa9}', ['\u{1f69}', '\u{399}', '\u{0}']),
+         ('\u{1faa}', ['\u{1f6a}', '\u{399}', '\u{0}']),
+         ('\u{1fab}', ['\u{1f6b}', '\u{399}', '\u{0}']),
+         ('\u{1fac}', ['\u{1f6c}', '\u{399}', '\u{0}']),
+         ('\u{1fad}', ['\u{1f6d}', '\u{399}', '\u{0}']),
+         ('\u{1fae}', ['\u{1f6e}', '\u{399}', '\u{0}']),
+         ('\u{1faf}', ['\u{1f6f}', '\u{399}', '\u{0}']),
+         ('\u{1fb0}', ['\u{1fb8}', '\u{0}', '\u{0}']), ('\u{1fb1}', ['\u{1fb9}', '\u{0}', '\u{0}']),
+         ('\u{1fb2}', ['\u{1fba}', '\u{399}', '\u{0}']),
+         ('\u{1fb3}', ['\u{391}', '\u{399}', '\u{0}']),
+         ('\u{1fb4}', ['\u{386}', '\u{399}', '\u{0}']),
+         ('\u{1fb6}', ['\u{391}', '\u{342}', '\u{0}']),
+         ('\u{1fb7}', ['\u{391}', '\u{342}', '\u{399}']),
+         ('\u{1fbc}', ['\u{391}', '\u{399}', '\u{0}']), ('\u{1fbe}', ['\u{399}', '\u{0}', '\u{0}']),
+         ('\u{1fc2}', ['\u{1fca}', '\u{399}', '\u{0}']),
+         ('\u{1fc3}', ['\u{397}', '\u{399}', '\u{0}']),
+         ('\u{1fc4}', ['\u{389}', '\u{399}', '\u{0}']),
+         ('\u{1fc6}', ['\u{397}', '\u{342}', '\u{0}']),
+         ('\u{1fc7}', ['\u{397}', '\u{342}', '\u{399}']),
+         ('\u{1fcc}', ['\u{397}', '\u{399}', '\u{0}']), ('\u{1fd0}', ['\u{1fd8}', '\u{0}', '\u{0}']),
+         ('\u{1fd1}', ['\u{1fd9}', '\u{0}', '\u{0}']),
+         ('\u{1fd2}', ['\u{399}', '\u{308}', '\u{300}']),
+         ('\u{1fd3}', ['\u{399}', '\u{308}', '\u{301}']),
+         ('\u{1fd6}', ['\u{399}', '\u{342}', '\u{0}']),
+         ('\u{1fd7}', ['\u{399}', '\u{308}', '\u{342}']),
+         ('\u{1fe0}', ['\u{1fe8}', '\u{0}', '\u{0}']), ('\u{1fe1}', ['\u{1fe9}', '\u{0}', '\u{0}']),
+         ('\u{1fe2}', ['\u{3a5}', '\u{308}', '\u{300}']),
+         ('\u{1fe3}', ['\u{3a5}', '\u{308}', '\u{301}']),
+         ('\u{1fe4}', ['\u{3a1}', '\u{313}', '\u{0}']), ('\u{1fe5}', ['\u{1fec}', '\u{0}', '\u{0}']),
+         ('\u{1fe6}', ['\u{3a5}', '\u{342}', '\u{0}']),
+         ('\u{1fe7}', ['\u{3a5}', '\u{308}', '\u{342}']),
+         ('\u{1ff2}', ['\u{1ffa}', '\u{399}', '\u{0}']),
+         ('\u{1ff3}', ['\u{3a9}', '\u{399}', '\u{0}']),
+         ('\u{1ff4}', ['\u{38f}', '\u{399}', '\u{0}']),
+         ('\u{1ff6}', ['\u{3a9}', '\u{342}', '\u{0}']),
+         ('\u{1ff7}', ['\u{3a9}', '\u{342}', '\u{399}']),
+         ('\u{1ffc}', ['\u{3a9}', '\u{399}', '\u{0}']), ('\u{214e}', ['\u{2132}', '\u{0}', '\u{0}']),
+         ('\u{2170}', ['\u{2160}', '\u{0}', '\u{0}']), ('\u{2171}', ['\u{2161}', '\u{0}', '\u{0}']),
+         ('\u{2172}', ['\u{2162}', '\u{0}', '\u{0}']), ('\u{2173}', ['\u{2163}', '\u{0}', '\u{0}']),
+         ('\u{2174}', ['\u{2164}', '\u{0}', '\u{0}']), ('\u{2175}', ['\u{2165}', '\u{0}', '\u{0}']),
+         ('\u{2176}', ['\u{2166}', '\u{0}', '\u{0}']), ('\u{2177}', ['\u{2167}', '\u{0}', '\u{0}']),
+         ('\u{2178}', ['\u{2168}', '\u{0}', '\u{0}']), ('\u{2179}', ['\u{2169}', '\u{0}', '\u{0}']),
+         ('\u{217a}', ['\u{216a}', '\u{0}', '\u{0}']), ('\u{217b}', ['\u{216b}', '\u{0}', '\u{0}']),
+         ('\u{217c}', ['\u{216c}', '\u{0}', '\u{0}']), ('\u{217d}', ['\u{216d}', '\u{0}', '\u{0}']),
+         ('\u{217e}', ['\u{216e}', '\u{0}', '\u{0}']), ('\u{217f}', ['\u{216f}', '\u{0}', '\u{0}']),
+         ('\u{2184}', ['\u{2183}', '\u{0}', '\u{0}']), ('\u{24d0}', ['\u{24b6}', '\u{0}', '\u{0}']),
+         ('\u{24d1}', ['\u{24b7}', '\u{0}', '\u{0}']), ('\u{24d2}', ['\u{24b8}', '\u{0}', '\u{0}']),
+         ('\u{24d3}', ['\u{24b9}', '\u{0}', '\u{0}']), ('\u{24d4}', ['\u{24ba}', '\u{0}', '\u{0}']),
+         ('\u{24d5}', ['\u{24bb}', '\u{0}', '\u{0}']), ('\u{24d6}', ['\u{24bc}', '\u{0}', '\u{0}']),
+         ('\u{24d7}', ['\u{24bd}', '\u{0}', '\u{0}']), ('\u{24d8}', ['\u{24be}', '\u{0}', '\u{0}']),
+         ('\u{24d9}', ['\u{24bf}', '\u{0}', '\u{0}']), ('\u{24da}', ['\u{24c0}', '\u{0}', '\u{0}']),
+         ('\u{24db}', ['\u{24c1}', '\u{0}', '\u{0}']), ('\u{24dc}', ['\u{24c2}', '\u{0}', '\u{0}']),
+         ('\u{24dd}', ['\u{24c3}', '\u{0}', '\u{0}']), ('\u{24de}', ['\u{24c4}', '\u{0}', '\u{0}']),
+         ('\u{24df}', ['\u{24c5}', '\u{0}', '\u{0}']), ('\u{24e0}', ['\u{24c6}', '\u{0}', '\u{0}']),
+         ('\u{24e1}', ['\u{24c7}', '\u{0}', '\u{0}']), ('\u{24e2}', ['\u{24c8}', '\u{0}', '\u{0}']),
+         ('\u{24e3}', ['\u{24c9}', '\u{0}', '\u{0}']), ('\u{24e4}', ['\u{24ca}', '\u{0}', '\u{0}']),
+         ('\u{24e5}', ['\u{24cb}', '\u{0}', '\u{0}']), ('\u{24e6}', ['\u{24cc}', '\u{0}', '\u{0}']),
+         ('\u{24e7}', ['\u{24cd}', '\u{0}', '\u{0}']), ('\u{24e8}', ['\u{24ce}', '\u{0}', '\u{0}']),
+         ('\u{24e9}', ['\u{24cf}', '\u{0}', '\u{0}']), ('\u{2c30}', ['\u{2c00}', '\u{0}', '\u{0}']),
+         ('\u{2c31}', ['\u{2c01}', '\u{0}', '\u{0}']), ('\u{2c32}', ['\u{2c02}', '\u{0}', '\u{0}']),
+         ('\u{2c33}', ['\u{2c03}', '\u{0}', '\u{0}']), ('\u{2c34}', ['\u{2c04}', '\u{0}', '\u{0}']),
+         ('\u{2c35}', ['\u{2c05}', '\u{0}', '\u{0}']), ('\u{2c36}', ['\u{2c06}', '\u{0}', '\u{0}']),
+         ('\u{2c37}', ['\u{2c07}', '\u{0}', '\u{0}']), ('\u{2c38}', ['\u{2c08}', '\u{0}', '\u{0}']),
+         ('\u{2c39}', ['\u{2c09}', '\u{0}', '\u{0}']), ('\u{2c3a}', ['\u{2c0a}', '\u{0}', '\u{0}']),
+         ('\u{2c3b}', ['\u{2c0b}', '\u{0}', '\u{0}']), ('\u{2c3c}', ['\u{2c0c}', '\u{0}', '\u{0}']),
+         ('\u{2c3d}', ['\u{2c0d}', '\u{0}', '\u{0}']), ('\u{2c3e}', ['\u{2c0e}', '\u{0}', '\u{0}']),
+         ('\u{2c3f}', ['\u{2c0f}', '\u{0}', '\u{0}']), ('\u{2c40}', ['\u{2c10}', '\u{0}', '\u{0}']),
+         ('\u{2c41}', ['\u{2c11}', '\u{0}', '\u{0}']), ('\u{2c42}', ['\u{2c12}', '\u{0}', '\u{0}']),
+         ('\u{2c43}', ['\u{2c13}', '\u{0}', '\u{0}']), ('\u{2c44}', ['\u{2c14}', '\u{0}', '\u{0}']),
+         ('\u{2c45}', ['\u{2c15}', '\u{0}', '\u{0}']), ('\u{2c46}', ['\u{2c16}', '\u{0}', '\u{0}']),
+         ('\u{2c47}', ['\u{2c17}', '\u{0}', '\u{0}']), ('\u{2c48}', ['\u{2c18}', '\u{0}', '\u{0}']),
+         ('\u{2c49}', ['\u{2c19}', '\u{0}', '\u{0}']), ('\u{2c4a}', ['\u{2c1a}', '\u{0}', '\u{0}']),
+         ('\u{2c4b}', ['\u{2c1b}', '\u{0}', '\u{0}']), ('\u{2c4c}', ['\u{2c1c}', '\u{0}', '\u{0}']),
+         ('\u{2c4d}', ['\u{2c1d}', '\u{0}', '\u{0}']), ('\u{2c4e}', ['\u{2c1e}', '\u{0}', '\u{0}']),
+         ('\u{2c4f}', ['\u{2c1f}', '\u{0}', '\u{0}']), ('\u{2c50}', ['\u{2c20}', '\u{0}', '\u{0}']),
+         ('\u{2c51}', ['\u{2c21}', '\u{0}', '\u{0}']), ('\u{2c52}', ['\u{2c22}', '\u{0}', '\u{0}']),
+         ('\u{2c53}', ['\u{2c23}', '\u{0}', '\u{0}']), ('\u{2c54}', ['\u{2c24}', '\u{0}', '\u{0}']),
+         ('\u{2c55}', ['\u{2c25}', '\u{0}', '\u{0}']), ('\u{2c56}', ['\u{2c26}', '\u{0}', '\u{0}']),
+         ('\u{2c57}', ['\u{2c27}', '\u{0}', '\u{0}']), ('\u{2c58}', ['\u{2c28}', '\u{0}', '\u{0}']),
+         ('\u{2c59}', ['\u{2c29}', '\u{0}', '\u{0}']), ('\u{2c5a}', ['\u{2c2a}', '\u{0}', '\u{0}']),
+         ('\u{2c5b}', ['\u{2c2b}', '\u{0}', '\u{0}']), ('\u{2c5c}', ['\u{2c2c}', '\u{0}', '\u{0}']),
+         ('\u{2c5d}', ['\u{2c2d}', '\u{0}', '\u{0}']), ('\u{2c5e}', ['\u{2c2e}', '\u{0}', '\u{0}']),
+         ('\u{2c61}', ['\u{2c60}', '\u{0}', '\u{0}']), ('\u{2c65}', ['\u{23a}', '\u{0}', '\u{0}']),
+         ('\u{2c66}', ['\u{23e}', '\u{0}', '\u{0}']), ('\u{2c68}', ['\u{2c67}', '\u{0}', '\u{0}']),
+         ('\u{2c6a}', ['\u{2c69}', '\u{0}', '\u{0}']), ('\u{2c6c}', ['\u{2c6b}', '\u{0}', '\u{0}']),
+         ('\u{2c73}', ['\u{2c72}', '\u{0}', '\u{0}']), ('\u{2c76}', ['\u{2c75}', '\u{0}', '\u{0}']),
+         ('\u{2c81}', ['\u{2c80}', '\u{0}', '\u{0}']), ('\u{2c83}', ['\u{2c82}', '\u{0}', '\u{0}']),
+         ('\u{2c85}', ['\u{2c84}', '\u{0}', '\u{0}']), ('\u{2c87}', ['\u{2c86}', '\u{0}', '\u{0}']),
+         ('\u{2c89}', ['\u{2c88}', '\u{0}', '\u{0}']), ('\u{2c8b}', ['\u{2c8a}', '\u{0}', '\u{0}']),
+         ('\u{2c8d}', ['\u{2c8c}', '\u{0}', '\u{0}']), ('\u{2c8f}', ['\u{2c8e}', '\u{0}', '\u{0}']),
+         ('\u{2c91}', ['\u{2c90}', '\u{0}', '\u{0}']), ('\u{2c93}', ['\u{2c92}', '\u{0}', '\u{0}']),
+         ('\u{2c95}', ['\u{2c94}', '\u{0}', '\u{0}']), ('\u{2c97}', ['\u{2c96}', '\u{0}', '\u{0}']),
+         ('\u{2c99}', ['\u{2c98}', '\u{0}', '\u{0}']), ('\u{2c9b}', ['\u{2c9a}', '\u{0}', '\u{0}']),
+         ('\u{2c9d}', ['\u{2c9c}', '\u{0}', '\u{0}']), ('\u{2c9f}', ['\u{2c9e}', '\u{0}', '\u{0}']),
+         ('\u{2ca1}', ['\u{2ca0}', '\u{0}', '\u{0}']), ('\u{2ca3}', ['\u{2ca2}', '\u{0}', '\u{0}']),
+         ('\u{2ca5}', ['\u{2ca4}', '\u{0}', '\u{0}']), ('\u{2ca7}', ['\u{2ca6}', '\u{0}', '\u{0}']),
+         ('\u{2ca9}', ['\u{2ca8}', '\u{0}', '\u{0}']), ('\u{2cab}', ['\u{2caa}', '\u{0}', '\u{0}']),
+         ('\u{2cad}', ['\u{2cac}', '\u{0}', '\u{0}']), ('\u{2caf}', ['\u{2cae}', '\u{0}', '\u{0}']),
+         ('\u{2cb1}', ['\u{2cb0}', '\u{0}', '\u{0}']), ('\u{2cb3}', ['\u{2cb2}', '\u{0}', '\u{0}']),
+         ('\u{2cb5}', ['\u{2cb4}', '\u{0}', '\u{0}']), ('\u{2cb7}', ['\u{2cb6}', '\u{0}', '\u{0}']),
+         ('\u{2cb9}', ['\u{2cb8}', '\u{0}', '\u{0}']), ('\u{2cbb}', ['\u{2cba}', '\u{0}', '\u{0}']),
+         ('\u{2cbd}', ['\u{2cbc}', '\u{0}', '\u{0}']), ('\u{2cbf}', ['\u{2cbe}', '\u{0}', '\u{0}']),
+         ('\u{2cc1}', ['\u{2cc0}', '\u{0}', '\u{0}']), ('\u{2cc3}', ['\u{2cc2}', '\u{0}', '\u{0}']),
+         ('\u{2cc5}', ['\u{2cc4}', '\u{0}', '\u{0}']), ('\u{2cc7}', ['\u{2cc6}', '\u{0}', '\u{0}']),
+         ('\u{2cc9}', ['\u{2cc8}', '\u{0}', '\u{0}']), ('\u{2ccb}', ['\u{2cca}', '\u{0}', '\u{0}']),
+         ('\u{2ccd}', ['\u{2ccc}', '\u{0}', '\u{0}']), ('\u{2ccf}', ['\u{2cce}', '\u{0}', '\u{0}']),
+         ('\u{2cd1}', ['\u{2cd0}', '\u{0}', '\u{0}']), ('\u{2cd3}', ['\u{2cd2}', '\u{0}', '\u{0}']),
+         ('\u{2cd5}', ['\u{2cd4}', '\u{0}', '\u{0}']), ('\u{2cd7}', ['\u{2cd6}', '\u{0}', '\u{0}']),
+         ('\u{2cd9}', ['\u{2cd8}', '\u{0}', '\u{0}']), ('\u{2cdb}', ['\u{2cda}', '\u{0}', '\u{0}']),
+         ('\u{2cdd}', ['\u{2cdc}', '\u{0}', '\u{0}']), ('\u{2cdf}', ['\u{2cde}', '\u{0}', '\u{0}']),
+         ('\u{2ce1}', ['\u{2ce0}', '\u{0}', '\u{0}']), ('\u{2ce3}', ['\u{2ce2}', '\u{0}', '\u{0}']),
+         ('\u{2cec}', ['\u{2ceb}', '\u{0}', '\u{0}']), ('\u{2cee}', ['\u{2ced}', '\u{0}', '\u{0}']),
+         ('\u{2cf3}', ['\u{2cf2}', '\u{0}', '\u{0}']), ('\u{2d00}', ['\u{10a0}', '\u{0}', '\u{0}']),
+         ('\u{2d01}', ['\u{10a1}', '\u{0}', '\u{0}']), ('\u{2d02}', ['\u{10a2}', '\u{0}', '\u{0}']),
+         ('\u{2d03}', ['\u{10a3}', '\u{0}', '\u{0}']), ('\u{2d04}', ['\u{10a4}', '\u{0}', '\u{0}']),
+         ('\u{2d05}', ['\u{10a5}', '\u{0}', '\u{0}']), ('\u{2d06}', ['\u{10a6}', '\u{0}', '\u{0}']),
+         ('\u{2d07}', ['\u{10a7}', '\u{0}', '\u{0}']), ('\u{2d08}', ['\u{10a8}', '\u{0}', '\u{0}']),
+         ('\u{2d09}', ['\u{10a9}', '\u{0}', '\u{0}']), ('\u{2d0a}', ['\u{10aa}', '\u{0}', '\u{0}']),
+         ('\u{2d0b}', ['\u{10ab}', '\u{0}', '\u{0}']), ('\u{2d0c}', ['\u{10ac}', '\u{0}', '\u{0}']),
+         ('\u{2d0d}', ['\u{10ad}', '\u{0}', '\u{0}']), ('\u{2d0e}', ['\u{10ae}', '\u{0}', '\u{0}']),
+         ('\u{2d0f}', ['\u{10af}', '\u{0}', '\u{0}']), ('\u{2d10}', ['\u{10b0}', '\u{0}', '\u{0}']),
+         ('\u{2d11}', ['\u{10b1}', '\u{0}', '\u{0}']), ('\u{2d12}', ['\u{10b2}', '\u{0}', '\u{0}']),
+         ('\u{2d13}', ['\u{10b3}', '\u{0}', '\u{0}']), ('\u{2d14}', ['\u{10b4}', '\u{0}', '\u{0}']),
+         ('\u{2d15}', ['\u{10b5}', '\u{0}', '\u{0}']), ('\u{2d16}', ['\u{10b6}', '\u{0}', '\u{0}']),
+         ('\u{2d17}', ['\u{10b7}', '\u{0}', '\u{0}']), ('\u{2d18}', ['\u{10b8}', '\u{0}', '\u{0}']),
+         ('\u{2d19}', ['\u{10b9}', '\u{0}', '\u{0}']), ('\u{2d1a}', ['\u{10ba}', '\u{0}', '\u{0}']),
+         ('\u{2d1b}', ['\u{10bb}', '\u{0}', '\u{0}']), ('\u{2d1c}', ['\u{10bc}', '\u{0}', '\u{0}']),
+         ('\u{2d1d}', ['\u{10bd}', '\u{0}', '\u{0}']), ('\u{2d1e}', ['\u{10be}', '\u{0}', '\u{0}']),
+         ('\u{2d1f}', ['\u{10bf}', '\u{0}', '\u{0}']), ('\u{2d20}', ['\u{10c0}', '\u{0}', '\u{0}']),
+         ('\u{2d21}', ['\u{10c1}', '\u{0}', '\u{0}']), ('\u{2d22}', ['\u{10c2}', '\u{0}', '\u{0}']),
+         ('\u{2d23}', ['\u{10c3}', '\u{0}', '\u{0}']), ('\u{2d24}', ['\u{10c4}', '\u{0}', '\u{0}']),
+         ('\u{2d25}', ['\u{10c5}', '\u{0}', '\u{0}']), ('\u{2d27}', ['\u{10c7}', '\u{0}', '\u{0}']),
+         ('\u{2d2d}', ['\u{10cd}', '\u{0}', '\u{0}']), ('\u{a641}', ['\u{a640}', '\u{0}', '\u{0}']),
+         ('\u{a643}', ['\u{a642}', '\u{0}', '\u{0}']), ('\u{a645}', ['\u{a644}', '\u{0}', '\u{0}']),
+         ('\u{a647}', ['\u{a646}', '\u{0}', '\u{0}']), ('\u{a649}', ['\u{a648}', '\u{0}', '\u{0}']),
+         ('\u{a64b}', ['\u{a64a}', '\u{0}', '\u{0}']), ('\u{a64d}', ['\u{a64c}', '\u{0}', '\u{0}']),
+         ('\u{a64f}', ['\u{a64e}', '\u{0}', '\u{0}']), ('\u{a651}', ['\u{a650}', '\u{0}', '\u{0}']),
+         ('\u{a653}', ['\u{a652}', '\u{0}', '\u{0}']), ('\u{a655}', ['\u{a654}', '\u{0}', '\u{0}']),
+         ('\u{a657}', ['\u{a656}', '\u{0}', '\u{0}']), ('\u{a659}', ['\u{a658}', '\u{0}', '\u{0}']),
+         ('\u{a65b}', ['\u{a65a}', '\u{0}', '\u{0}']), ('\u{a65d}', ['\u{a65c}', '\u{0}', '\u{0}']),
+         ('\u{a65f}', ['\u{a65e}', '\u{0}', '\u{0}']), ('\u{a661}', ['\u{a660}', '\u{0}', '\u{0}']),
+         ('\u{a663}', ['\u{a662}', '\u{0}', '\u{0}']), ('\u{a665}', ['\u{a664}', '\u{0}', '\u{0}']),
+         ('\u{a667}', ['\u{a666}', '\u{0}', '\u{0}']), ('\u{a669}', ['\u{a668}', '\u{0}', '\u{0}']),
+         ('\u{a66b}', ['\u{a66a}', '\u{0}', '\u{0}']), ('\u{a66d}', ['\u{a66c}', '\u{0}', '\u{0}']),
+         ('\u{a681}', ['\u{a680}', '\u{0}', '\u{0}']), ('\u{a683}', ['\u{a682}', '\u{0}', '\u{0}']),
+         ('\u{a685}', ['\u{a684}', '\u{0}', '\u{0}']), ('\u{a687}', ['\u{a686}', '\u{0}', '\u{0}']),
+         ('\u{a689}', ['\u{a688}', '\u{0}', '\u{0}']), ('\u{a68b}', ['\u{a68a}', '\u{0}', '\u{0}']),
+         ('\u{a68d}', ['\u{a68c}', '\u{0}', '\u{0}']), ('\u{a68f}', ['\u{a68e}', '\u{0}', '\u{0}']),
+         ('\u{a691}', ['\u{a690}', '\u{0}', '\u{0}']), ('\u{a693}', ['\u{a692}', '\u{0}', '\u{0}']),
+         ('\u{a695}', ['\u{a694}', '\u{0}', '\u{0}']), ('\u{a697}', ['\u{a696}', '\u{0}', '\u{0}']),
+         ('\u{a699}', ['\u{a698}', '\u{0}', '\u{0}']), ('\u{a69b}', ['\u{a69a}', '\u{0}', '\u{0}']),
+         ('\u{a723}', ['\u{a722}', '\u{0}', '\u{0}']), ('\u{a725}', ['\u{a724}', '\u{0}', '\u{0}']),
+         ('\u{a727}', ['\u{a726}', '\u{0}', '\u{0}']), ('\u{a729}', ['\u{a728}', '\u{0}', '\u{0}']),
+         ('\u{a72b}', ['\u{a72a}', '\u{0}', '\u{0}']), ('\u{a72d}', ['\u{a72c}', '\u{0}', '\u{0}']),
+         ('\u{a72f}', ['\u{a72e}', '\u{0}', '\u{0}']), ('\u{a733}', ['\u{a732}', '\u{0}', '\u{0}']),
+         ('\u{a735}', ['\u{a734}', '\u{0}', '\u{0}']), ('\u{a737}', ['\u{a736}', '\u{0}', '\u{0}']),
+         ('\u{a739}', ['\u{a738}', '\u{0}', '\u{0}']), ('\u{a73b}', ['\u{a73a}', '\u{0}', '\u{0}']),
+         ('\u{a73d}', ['\u{a73c}', '\u{0}', '\u{0}']), ('\u{a73f}', ['\u{a73e}', '\u{0}', '\u{0}']),
+         ('\u{a741}', ['\u{a740}', '\u{0}', '\u{0}']), ('\u{a743}', ['\u{a742}', '\u{0}', '\u{0}']),
+         ('\u{a745}', ['\u{a744}', '\u{0}', '\u{0}']), ('\u{a747}', ['\u{a746}', '\u{0}', '\u{0}']),
+         ('\u{a749}', ['\u{a748}', '\u{0}', '\u{0}']), ('\u{a74b}', ['\u{a74a}', '\u{0}', '\u{0}']),
+         ('\u{a74d}', ['\u{a74c}', '\u{0}', '\u{0}']), ('\u{a74f}', ['\u{a74e}', '\u{0}', '\u{0}']),
+         ('\u{a751}', ['\u{a750}', '\u{0}', '\u{0}']), ('\u{a753}', ['\u{a752}', '\u{0}', '\u{0}']),
+         ('\u{a755}', ['\u{a754}', '\u{0}', '\u{0}']), ('\u{a757}', ['\u{a756}', '\u{0}', '\u{0}']),
+         ('\u{a759}', ['\u{a758}', '\u{0}', '\u{0}']), ('\u{a75b}', ['\u{a75a}', '\u{0}', '\u{0}']),
+         ('\u{a75d}', ['\u{a75c}', '\u{0}', '\u{0}']), ('\u{a75f}', ['\u{a75e}', '\u{0}', '\u{0}']),
+         ('\u{a761}', ['\u{a760}', '\u{0}', '\u{0}']), ('\u{a763}', ['\u{a762}', '\u{0}', '\u{0}']),
+         ('\u{a765}', ['\u{a764}', '\u{0}', '\u{0}']), ('\u{a767}', ['\u{a766}', '\u{0}', '\u{0}']),
+         ('\u{a769}', ['\u{a768}', '\u{0}', '\u{0}']), ('\u{a76b}', ['\u{a76a}', '\u{0}', '\u{0}']),
+         ('\u{a76d}', ['\u{a76c}', '\u{0}', '\u{0}']), ('\u{a76f}', ['\u{a76e}', '\u{0}', '\u{0}']),
+         ('\u{a77a}', ['\u{a779}', '\u{0}', '\u{0}']), ('\u{a77c}', ['\u{a77b}', '\u{0}', '\u{0}']),
+         ('\u{a77f}', ['\u{a77e}', '\u{0}', '\u{0}']), ('\u{a781}', ['\u{a780}', '\u{0}', '\u{0}']),
+         ('\u{a783}', ['\u{a782}', '\u{0}', '\u{0}']), ('\u{a785}', ['\u{a784}', '\u{0}', '\u{0}']),
+         ('\u{a787}', ['\u{a786}', '\u{0}', '\u{0}']), ('\u{a78c}', ['\u{a78b}', '\u{0}', '\u{0}']),
+         ('\u{a791}', ['\u{a790}', '\u{0}', '\u{0}']), ('\u{a793}', ['\u{a792}', '\u{0}', '\u{0}']),
+         ('\u{a794}', ['\u{a7c4}', '\u{0}', '\u{0}']), ('\u{a797}', ['\u{a796}', '\u{0}', '\u{0}']),
+         ('\u{a799}', ['\u{a798}', '\u{0}', '\u{0}']), ('\u{a79b}', ['\u{a79a}', '\u{0}', '\u{0}']),
+         ('\u{a79d}', ['\u{a79c}', '\u{0}', '\u{0}']), ('\u{a79f}', ['\u{a79e}', '\u{0}', '\u{0}']),
+         ('\u{a7a1}', ['\u{a7a0}', '\u{0}', '\u{0}']), ('\u{a7a3}', ['\u{a7a2}', '\u{0}', '\u{0}']),
+         ('\u{a7a5}', ['\u{a7a4}', '\u{0}', '\u{0}']), ('\u{a7a7}', ['\u{a7a6}', '\u{0}', '\u{0}']),
+         ('\u{a7a9}', ['\u{a7a8}', '\u{0}', '\u{0}']), ('\u{a7b5}', ['\u{a7b4}', '\u{0}', '\u{0}']),
+         ('\u{a7b7}', ['\u{a7b6}', '\u{0}', '\u{0}']), ('\u{a7b9}', ['\u{a7b8}', '\u{0}', '\u{0}']),
+         ('\u{a7bb}', ['\u{a7ba}', '\u{0}', '\u{0}']), ('\u{a7bd}', ['\u{a7bc}', '\u{0}', '\u{0}']),
+         ('\u{a7bf}', ['\u{a7be}', '\u{0}', '\u{0}']), ('\u{a7c3}', ['\u{a7c2}', '\u{0}', '\u{0}']),
+         ('\u{a7c8}', ['\u{a7c7}', '\u{0}', '\u{0}']), ('\u{a7ca}', ['\u{a7c9}', '\u{0}', '\u{0}']),
+         ('\u{a7f6}', ['\u{a7f5}', '\u{0}', '\u{0}']), ('\u{ab53}', ['\u{a7b3}', '\u{0}', '\u{0}']),
+         ('\u{ab70}', ['\u{13a0}', '\u{0}', '\u{0}']), ('\u{ab71}', ['\u{13a1}', '\u{0}', '\u{0}']),
+         ('\u{ab72}', ['\u{13a2}', '\u{0}', '\u{0}']), ('\u{ab73}', ['\u{13a3}', '\u{0}', '\u{0}']),
+         ('\u{ab74}', ['\u{13a4}', '\u{0}', '\u{0}']), ('\u{ab75}', ['\u{13a5}', '\u{0}', '\u{0}']),
+         ('\u{ab76}', ['\u{13a6}', '\u{0}', '\u{0}']), ('\u{ab77}', ['\u{13a7}', '\u{0}', '\u{0}']),
+         ('\u{ab78}', ['\u{13a8}', '\u{0}', '\u{0}']), ('\u{ab79}', ['\u{13a9}', '\u{0}', '\u{0}']),
+         ('\u{ab7a}', ['\u{13aa}', '\u{0}', '\u{0}']), ('\u{ab7b}', ['\u{13ab}', '\u{0}', '\u{0}']),
+         ('\u{ab7c}', ['\u{13ac}', '\u{0}', '\u{0}']), ('\u{ab7d}', ['\u{13ad}', '\u{0}', '\u{0}']),
+         ('\u{ab7e}', ['\u{13ae}', '\u{0}', '\u{0}']), ('\u{ab7f}', ['\u{13af}', '\u{0}', '\u{0}']),
+         ('\u{ab80}', ['\u{13b0}', '\u{0}', '\u{0}']), ('\u{ab81}', ['\u{13b1}', '\u{0}', '\u{0}']),
+         ('\u{ab82}', ['\u{13b2}', '\u{0}', '\u{0}']), ('\u{ab83}', ['\u{13b3}', '\u{0}', '\u{0}']),
+         ('\u{ab84}', ['\u{13b4}', '\u{0}', '\u{0}']), ('\u{ab85}', ['\u{13b5}', '\u{0}', '\u{0}']),
+         ('\u{ab86}', ['\u{13b6}', '\u{0}', '\u{0}']), ('\u{ab87}', ['\u{13b7}', '\u{0}', '\u{0}']),
+         ('\u{ab88}', ['\u{13b8}', '\u{0}', '\u{0}']), ('\u{ab89}', ['\u{13b9}', '\u{0}', '\u{0}']),
+         ('\u{ab8a}', ['\u{13ba}', '\u{0}', '\u{0}']), ('\u{ab8b}', ['\u{13bb}', '\u{0}', '\u{0}']),
+         ('\u{ab8c}', ['\u{13bc}', '\u{0}', '\u{0}']), ('\u{ab8d}', ['\u{13bd}', '\u{0}', '\u{0}']),
+         ('\u{ab8e}', ['\u{13be}', '\u{0}', '\u{0}']), ('\u{ab8f}', ['\u{13bf}', '\u{0}', '\u{0}']),
+         ('\u{ab90}', ['\u{13c0}', '\u{0}', '\u{0}']), ('\u{ab91}', ['\u{13c1}', '\u{0}', '\u{0}']),
+         ('\u{ab92}', ['\u{13c2}', '\u{0}', '\u{0}']), ('\u{ab93}', ['\u{13c3}', '\u{0}', '\u{0}']),
+         ('\u{ab94}', ['\u{13c4}', '\u{0}', '\u{0}']), ('\u{ab95}', ['\u{13c5}', '\u{0}', '\u{0}']),
+         ('\u{ab96}', ['\u{13c6}', '\u{0}', '\u{0}']), ('\u{ab97}', ['\u{13c7}', '\u{0}', '\u{0}']),
+         ('\u{ab98}', ['\u{13c8}', '\u{0}', '\u{0}']), ('\u{ab99}', ['\u{13c9}', '\u{0}', '\u{0}']),
+         ('\u{ab9a}', ['\u{13ca}', '\u{0}', '\u{0}']), ('\u{ab9b}', ['\u{13cb}', '\u{0}', '\u{0}']),
+         ('\u{ab9c}', ['\u{13cc}', '\u{0}', '\u{0}']), ('\u{ab9d}', ['\u{13cd}', '\u{0}', '\u{0}']),
+         ('\u{ab9e}', ['\u{13ce}', '\u{0}', '\u{0}']), ('\u{ab9f}', ['\u{13cf}', '\u{0}', '\u{0}']),
+         ('\u{aba0}', ['\u{13d0}', '\u{0}', '\u{0}']), ('\u{aba1}', ['\u{13d1}', '\u{0}', '\u{0}']),
+         ('\u{aba2}', ['\u{13d2}', '\u{0}', '\u{0}']), ('\u{aba3}', ['\u{13d3}', '\u{0}', '\u{0}']),
+         ('\u{aba4}', ['\u{13d4}', '\u{0}', '\u{0}']), ('\u{aba5}', ['\u{13d5}', '\u{0}', '\u{0}']),
+         ('\u{aba6}', ['\u{13d6}', '\u{0}', '\u{0}']), ('\u{aba7}', ['\u{13d7}', '\u{0}', '\u{0}']),
+         ('\u{aba8}', ['\u{13d8}', '\u{0}', '\u{0}']), ('\u{aba9}', ['\u{13d9}', '\u{0}', '\u{0}']),
+         ('\u{abaa}', ['\u{13da}', '\u{0}', '\u{0}']), ('\u{abab}', ['\u{13db}', '\u{0}', '\u{0}']),
+         ('\u{abac}', ['\u{13dc}', '\u{0}', '\u{0}']), ('\u{abad}', ['\u{13dd}', '\u{0}', '\u{0}']),
+         ('\u{abae}', ['\u{13de}', '\u{0}', '\u{0}']), ('\u{abaf}', ['\u{13df}', '\u{0}', '\u{0}']),
+         ('\u{abb0}', ['\u{13e0}', '\u{0}', '\u{0}']), ('\u{abb1}', ['\u{13e1}', '\u{0}', '\u{0}']),
+         ('\u{abb2}', ['\u{13e2}', '\u{0}', '\u{0}']), ('\u{abb3}', ['\u{13e3}', '\u{0}', '\u{0}']),
+         ('\u{abb4}', ['\u{13e4}', '\u{0}', '\u{0}']), ('\u{abb5}', ['\u{13e5}', '\u{0}', '\u{0}']),
+         ('\u{abb6}', ['\u{13e6}', '\u{0}', '\u{0}']), ('\u{abb7}', ['\u{13e7}', '\u{0}', '\u{0}']),
+         ('\u{abb8}', ['\u{13e8}', '\u{0}', '\u{0}']), ('\u{abb9}', ['\u{13e9}', '\u{0}', '\u{0}']),
+         ('\u{abba}', ['\u{13ea}', '\u{0}', '\u{0}']), ('\u{abbb}', ['\u{13eb}', '\u{0}', '\u{0}']),
+         ('\u{abbc}', ['\u{13ec}', '\u{0}', '\u{0}']), ('\u{abbd}', ['\u{13ed}', '\u{0}', '\u{0}']),
+         ('\u{abbe}', ['\u{13ee}', '\u{0}', '\u{0}']), ('\u{abbf}', ['\u{13ef}', '\u{0}', '\u{0}']),
+         ('\u{fb00}', ['F', 'F', '\u{0}']), ('\u{fb01}', ['F', 'I', '\u{0}']),
+         ('\u{fb02}', ['F', 'L', '\u{0}']), ('\u{fb03}', ['F', 'F', 'I']),
+         ('\u{fb04}', ['F', 'F', 'L']), ('\u{fb05}', ['S', 'T', '\u{0}']),
+         ('\u{fb06}', ['S', 'T', '\u{0}']), ('\u{fb13}', ['\u{544}', '\u{546}', '\u{0}']),
+         ('\u{fb14}', ['\u{544}', '\u{535}', '\u{0}']),
+         ('\u{fb15}', ['\u{544}', '\u{53b}', '\u{0}']),
+         ('\u{fb16}', ['\u{54e}', '\u{546}', '\u{0}']),
+         ('\u{fb17}', ['\u{544}', '\u{53d}', '\u{0}']), ('\u{ff41}', ['\u{ff21}', '\u{0}', '\u{0}']),
+         ('\u{ff42}', ['\u{ff22}', '\u{0}', '\u{0}']), ('\u{ff43}', ['\u{ff23}', '\u{0}', '\u{0}']),
+         ('\u{ff44}', ['\u{ff24}', '\u{0}', '\u{0}']), ('\u{ff45}', ['\u{ff25}', '\u{0}', '\u{0}']),
+         ('\u{ff46}', ['\u{ff26}', '\u{0}', '\u{0}']), ('\u{ff47}', ['\u{ff27}', '\u{0}', '\u{0}']),
+         ('\u{ff48}', ['\u{ff28}', '\u{0}', '\u{0}']), ('\u{ff49}', ['\u{ff29}', '\u{0}', '\u{0}']),
+         ('\u{ff4a}', ['\u{ff2a}', '\u{0}', '\u{0}']), ('\u{ff4b}', ['\u{ff2b}', '\u{0}', '\u{0}']),
+         ('\u{ff4c}', ['\u{ff2c}', '\u{0}', '\u{0}']), ('\u{ff4d}', ['\u{ff2d}', '\u{0}', '\u{0}']),
+         ('\u{ff4e}', ['\u{ff2e}', '\u{0}', '\u{0}']), ('\u{ff4f}', ['\u{ff2f}', '\u{0}', '\u{0}']),
+         ('\u{ff50}', ['\u{ff30}', '\u{0}', '\u{0}']), ('\u{ff51}', ['\u{ff31}', '\u{0}', '\u{0}']),
+         ('\u{ff52}', ['\u{ff32}', '\u{0}', '\u{0}']), ('\u{ff53}', ['\u{ff33}', '\u{0}', '\u{0}']),
+         ('\u{ff54}', ['\u{ff34}', '\u{0}', '\u{0}']), ('\u{ff55}', ['\u{ff35}', '\u{0}', '\u{0}']),
+         ('\u{ff56}', ['\u{ff36}', '\u{0}', '\u{0}']), ('\u{ff57}', ['\u{ff37}', '\u{0}', '\u{0}']),
+         ('\u{ff58}', ['\u{ff38}', '\u{0}', '\u{0}']), ('\u{ff59}', ['\u{ff39}', '\u{0}', '\u{0}']),
+         ('\u{ff5a}', ['\u{ff3a}', '\u{0}', '\u{0}']),
+         ('\u{10428}', ['\u{10400}', '\u{0}', '\u{0}']),
+         ('\u{10429}', ['\u{10401}', '\u{0}', '\u{0}']),
+         ('\u{1042a}', ['\u{10402}', '\u{0}', '\u{0}']),
+         ('\u{1042b}', ['\u{10403}', '\u{0}', '\u{0}']),
+         ('\u{1042c}', ['\u{10404}', '\u{0}', '\u{0}']),
+         ('\u{1042d}', ['\u{10405}', '\u{0}', '\u{0}']),
+         ('\u{1042e}', ['\u{10406}', '\u{0}', '\u{0}']),
+         ('\u{1042f}', ['\u{10407}', '\u{0}', '\u{0}']),
+         ('\u{10430}', ['\u{10408}', '\u{0}', '\u{0}']),
+         ('\u{10431}', ['\u{10409}', '\u{0}', '\u{0}']),
+         ('\u{10432}', ['\u{1040a}', '\u{0}', '\u{0}']),
+         ('\u{10433}', ['\u{1040b}', '\u{0}', '\u{0}']),
+         ('\u{10434}', ['\u{1040c}', '\u{0}', '\u{0}']),
+         ('\u{10435}', ['\u{1040d}', '\u{0}', '\u{0}']),
+         ('\u{10436}', ['\u{1040e}', '\u{0}', '\u{0}']),
+         ('\u{10437}', ['\u{1040f}', '\u{0}', '\u{0}']),
+         ('\u{10438}', ['\u{10410}', '\u{0}', '\u{0}']),
+         ('\u{10439}', ['\u{10411}', '\u{0}', '\u{0}']),
+         ('\u{1043a}', ['\u{10412}', '\u{0}', '\u{0}']),
+         ('\u{1043b}', ['\u{10413}', '\u{0}', '\u{0}']),
+         ('\u{1043c}', ['\u{10414}', '\u{0}', '\u{0}']),
+         ('\u{1043d}', ['\u{10415}', '\u{0}', '\u{0}']),
+         ('\u{1043e}', ['\u{10416}', '\u{0}', '\u{0}']),
+         ('\u{1043f}', ['\u{10417}', '\u{0}', '\u{0}']),
+         ('\u{10440}', ['\u{10418}', '\u{0}', '\u{0}']),
+         ('\u{10441}', ['\u{10419}', '\u{0}', '\u{0}']),
+         ('\u{10442}', ['\u{1041a}', '\u{0}', '\u{0}']),
+         ('\u{10443}', ['\u{1041b}', '\u{0}', '\u{0}']),
+         ('\u{10444}', ['\u{1041c}', '\u{0}', '\u{0}']),
+         ('\u{10445}', ['\u{1041d}', '\u{0}', '\u{0}']),
+         ('\u{10446}', ['\u{1041e}', '\u{0}', '\u{0}']),
+         ('\u{10447}', ['\u{1041f}', '\u{0}', '\u{0}']),
+         ('\u{10448}', ['\u{10420}', '\u{0}', '\u{0}']),
+         ('\u{10449}', ['\u{10421}', '\u{0}', '\u{0}']),
+         ('\u{1044a}', ['\u{10422}', '\u{0}', '\u{0}']),
+         ('\u{1044b}', ['\u{10423}', '\u{0}', '\u{0}']),
+         ('\u{1044c}', ['\u{10424}', '\u{0}', '\u{0}']),
+         ('\u{1044d}', ['\u{10425}', '\u{0}', '\u{0}']),
+         ('\u{1044e}', ['\u{10426}', '\u{0}', '\u{0}']),
+         ('\u{1044f}', ['\u{10427}', '\u{0}', '\u{0}']),
+         ('\u{104d8}', ['\u{104b0}', '\u{0}', '\u{0}']),
+         ('\u{104d9}', ['\u{104b1}', '\u{0}', '\u{0}']),
+         ('\u{104da}', ['\u{104b2}', '\u{0}', '\u{0}']),
+         ('\u{104db}', ['\u{104b3}', '\u{0}', '\u{0}']),
+         ('\u{104dc}', ['\u{104b4}', '\u{0}', '\u{0}']),
+         ('\u{104dd}', ['\u{104b5}', '\u{0}', '\u{0}']),
+         ('\u{104de}', ['\u{104b6}', '\u{0}', '\u{0}']),
+         ('\u{104df}', ['\u{104b7}', '\u{0}', '\u{0}']),
+         ('\u{104e0}', ['\u{104b8}', '\u{0}', '\u{0}']),
+         ('\u{104e1}', ['\u{104b9}', '\u{0}', '\u{0}']),
+         ('\u{104e2}', ['\u{104ba}', '\u{0}', '\u{0}']),
+         ('\u{104e3}', ['\u{104bb}', '\u{0}', '\u{0}']),
+         ('\u{104e4}', ['\u{104bc}', '\u{0}', '\u{0}']),
+         ('\u{104e5}', ['\u{104bd}', '\u{0}', '\u{0}']),
+         ('\u{104e6}', ['\u{104be}', '\u{0}', '\u{0}']),
+         ('\u{104e7}', ['\u{104bf}', '\u{0}', '\u{0}']),
+         ('\u{104e8}', ['\u{104c0}', '\u{0}', '\u{0}']),
+         ('\u{104e9}', ['\u{104c1}', '\u{0}', '\u{0}']),
+         ('\u{104ea}', ['\u{104c2}', '\u{0}', '\u{0}']),
+         ('\u{104eb}', ['\u{104c3}', '\u{0}', '\u{0}']),
+         ('\u{104ec}', ['\u{104c4}', '\u{0}', '\u{0}']),
+         ('\u{104ed}', ['\u{104c5}', '\u{0}', '\u{0}']),
+         ('\u{104ee}', ['\u{104c6}', '\u{0}', '\u{0}']),
+         ('\u{104ef}', ['\u{104c7}', '\u{0}', '\u{0}']),
+         ('\u{104f0}', ['\u{104c8}', '\u{0}', '\u{0}']),
+         ('\u{104f1}', ['\u{104c9}', '\u{0}', '\u{0}']),
+         ('\u{104f2}', ['\u{104ca}', '\u{0}', '\u{0}']),
+         ('\u{104f3}', ['\u{104cb}', '\u{0}', '\u{0}']),
+         ('\u{104f4}', ['\u{104cc}', '\u{0}', '\u{0}']),
+         ('\u{104f5}', ['\u{104cd}', '\u{0}', '\u{0}']),
+         ('\u{104f6}', ['\u{104ce}', '\u{0}', '\u{0}']),
+         ('\u{104f7}', ['\u{104cf}', '\u{0}', '\u{0}']),
+         ('\u{104f8}', ['\u{104d0}', '\u{0}', '\u{0}']),
+         ('\u{104f9}', ['\u{104d1}', '\u{0}', '\u{0}']),
+         ('\u{104fa}', ['\u{104d2}', '\u{0}', '\u{0}']),
+         ('\u{104fb}', ['\u{104d3}', '\u{0}', '\u{0}']),
+         ('\u{10cc0}', ['\u{10c80}', '\u{0}', '\u{0}']),
+         ('\u{10cc1}', ['\u{10c81}', '\u{0}', '\u{0}']),
+         ('\u{10cc2}', ['\u{10c82}', '\u{0}', '\u{0}']),
+         ('\u{10cc3}', ['\u{10c83}', '\u{0}', '\u{0}']),
+         ('\u{10cc4}', ['\u{10c84}', '\u{0}', '\u{0}']),
+         ('\u{10cc5}', ['\u{10c85}', '\u{0}', '\u{0}']),
+         ('\u{10cc6}', ['\u{10c86}', '\u{0}', '\u{0}']),
+         ('\u{10cc7}', ['\u{10c87}', '\u{0}', '\u{0}']),
+         ('\u{10cc8}', ['\u{10c88}', '\u{0}', '\u{0}']),
+         ('\u{10cc9}', ['\u{10c89}', '\u{0}', '\u{0}']),
+         ('\u{10cca}', ['\u{10c8a}', '\u{0}', '\u{0}']),
+         ('\u{10ccb}', ['\u{10c8b}', '\u{0}', '\u{0}']),
+         ('\u{10ccc}', ['\u{10c8c}', '\u{0}', '\u{0}']),
+         ('\u{10ccd}', ['\u{10c8d}', '\u{0}', '\u{0}']),
+         ('\u{10cce}', ['\u{10c8e}', '\u{0}', '\u{0}']),
+         ('\u{10ccf}', ['\u{10c8f}', '\u{0}', '\u{0}']),
+         ('\u{10cd0}', ['\u{10c90}', '\u{0}', '\u{0}']),
+         ('\u{10cd1}', ['\u{10c91}', '\u{0}', '\u{0}']),
+         ('\u{10cd2}', ['\u{10c92}', '\u{0}', '\u{0}']),
+         ('\u{10cd3}', ['\u{10c93}', '\u{0}', '\u{0}']),
+         ('\u{10cd4}', ['\u{10c94}', '\u{0}', '\u{0}']),
+         ('\u{10cd5}', ['\u{10c95}', '\u{0}', '\u{0}']),
+         ('\u{10cd6}', ['\u{10c96}', '\u{0}', '\u{0}']),
+         ('\u{10cd7}', ['\u{10c97}', '\u{0}', '\u{0}']),
+         ('\u{10cd8}', ['\u{10c98}', '\u{0}', '\u{0}']),
+         ('\u{10cd9}', ['\u{10c99}', '\u{0}', '\u{0}']),
+         ('\u{10cda}', ['\u{10c9a}', '\u{0}', '\u{0}']),
+         ('\u{10cdb}', ['\u{10c9b}', '\u{0}', '\u{0}']),
+         ('\u{10cdc}', ['\u{10c9c}', '\u{0}', '\u{0}']),
+         ('\u{10cdd}', ['\u{10c9d}', '\u{0}', '\u{0}']),
+         ('\u{10cde}', ['\u{10c9e}', '\u{0}', '\u{0}']),
+         ('\u{10cdf}', ['\u{10c9f}', '\u{0}', '\u{0}']),
+         ('\u{10ce0}', ['\u{10ca0}', '\u{0}', '\u{0}']),
+         ('\u{10ce1}', ['\u{10ca1}', '\u{0}', '\u{0}']),
+         ('\u{10ce2}', ['\u{10ca2}', '\u{0}', '\u{0}']),
+         ('\u{10ce3}', ['\u{10ca3}', '\u{0}', '\u{0}']),
+         ('\u{10ce4}', ['\u{10ca4}', '\u{0}', '\u{0}']),
+         ('\u{10ce5}', ['\u{10ca5}', '\u{0}', '\u{0}']),
+         ('\u{10ce6}', ['\u{10ca6}', '\u{0}', '\u{0}']),
+         ('\u{10ce7}', ['\u{10ca7}', '\u{0}', '\u{0}']),
+         ('\u{10ce8}', ['\u{10ca8}', '\u{0}', '\u{0}']),
+         ('\u{10ce9}', ['\u{10ca9}', '\u{0}', '\u{0}']),
+         ('\u{10cea}', ['\u{10caa}', '\u{0}', '\u{0}']),
+         ('\u{10ceb}', ['\u{10cab}', '\u{0}', '\u{0}']),
+         ('\u{10cec}', ['\u{10cac}', '\u{0}', '\u{0}']),
+         ('\u{10ced}', ['\u{10cad}', '\u{0}', '\u{0}']),
+         ('\u{10cee}', ['\u{10cae}', '\u{0}', '\u{0}']),
+         ('\u{10cef}', ['\u{10caf}', '\u{0}', '\u{0}']),
+         ('\u{10cf0}', ['\u{10cb0}', '\u{0}', '\u{0}']),
+         ('\u{10cf1}', ['\u{10cb1}', '\u{0}', '\u{0}']),
+         ('\u{10cf2}', ['\u{10cb2}', '\u{0}', '\u{0}']),
+         ('\u{118c0}', ['\u{118a0}', '\u{0}', '\u{0}']),
+         ('\u{118c1}', ['\u{118a1}', '\u{0}', '\u{0}']),
+         ('\u{118c2}', ['\u{118a2}', '\u{0}', '\u{0}']),
+         ('\u{118c3}', ['\u{118a3}', '\u{0}', '\u{0}']),
+         ('\u{118c4}', ['\u{118a4}', '\u{0}', '\u{0}']),
+         ('\u{118c5}', ['\u{118a5}', '\u{0}', '\u{0}']),
+         ('\u{118c6}', ['\u{118a6}', '\u{0}', '\u{0}']),
+         ('\u{118c7}', ['\u{118a7}', '\u{0}', '\u{0}']),
+         ('\u{118c8}', ['\u{118a8}', '\u{0}', '\u{0}']),
+         ('\u{118c9}', ['\u{118a9}', '\u{0}', '\u{0}']),
+         ('\u{118ca}', ['\u{118aa}', '\u{0}', '\u{0}']),
+         ('\u{118cb}', ['\u{118ab}', '\u{0}', '\u{0}']),
+         ('\u{118cc}', ['\u{118ac}', '\u{0}', '\u{0}']),
+         ('\u{118cd}', ['\u{118ad}', '\u{0}', '\u{0}']),
+         ('\u{118ce}', ['\u{118ae}', '\u{0}', '\u{0}']),
+         ('\u{118cf}', ['\u{118af}', '\u{0}', '\u{0}']),
+         ('\u{118d0}', ['\u{118b0}', '\u{0}', '\u{0}']),
+         ('\u{118d1}', ['\u{118b1}', '\u{0}', '\u{0}']),
+         ('\u{118d2}', ['\u{118b2}', '\u{0}', '\u{0}']),
+         ('\u{118d3}', ['\u{118b3}', '\u{0}', '\u{0}']),
+         ('\u{118d4}', ['\u{118b4}', '\u{0}', '\u{0}']),
+         ('\u{118d5}', ['\u{118b5}', '\u{0}', '\u{0}']),
+         ('\u{118d6}', ['\u{118b6}', '\u{0}', '\u{0}']),
+         ('\u{118d7}', ['\u{118b7}', '\u{0}', '\u{0}']),
+         ('\u{118d8}', ['\u{118b8}', '\u{0}', '\u{0}']),
+         ('\u{118d9}', ['\u{118b9}', '\u{0}', '\u{0}']),
+         ('\u{118da}', ['\u{118ba}', '\u{0}', '\u{0}']),
+         ('\u{118db}', ['\u{118bb}', '\u{0}', '\u{0}']),
+         ('\u{118dc}', ['\u{118bc}', '\u{0}', '\u{0}']),
+         ('\u{118dd}', ['\u{118bd}', '\u{0}', '\u{0}']),
+         ('\u{118de}', ['\u{118be}', '\u{0}', '\u{0}']),
+         ('\u{118df}', ['\u{118bf}', '\u{0}', '\u{0}']),
+         ('\u{16e60}', ['\u{16e40}', '\u{0}', '\u{0}']),
+         ('\u{16e61}', ['\u{16e41}', '\u{0}', '\u{0}']),
+         ('\u{16e62}', ['\u{16e42}', '\u{0}', '\u{0}']),
+         ('\u{16e63}', ['\u{16e43}', '\u{0}', '\u{0}']),
+         ('\u{16e64}', ['\u{16e44}', '\u{0}', '\u{0}']),
+         ('\u{16e65}', ['\u{16e45}', '\u{0}', '\u{0}']),
+         ('\u{16e66}', ['\u{16e46}', '\u{0}', '\u{0}']),
+         ('\u{16e67}', ['\u{16e47}', '\u{0}', '\u{0}']),
+         ('\u{16e68}', ['\u{16e48}', '\u{0}', '\u{0}']),
+         ('\u{16e69}', ['\u{16e49}', '\u{0}', '\u{0}']),
+         ('\u{16e6a}', ['\u{16e4a}', '\u{0}', '\u{0}']),
+         ('\u{16e6b}', ['\u{16e4b}', '\u{0}', '\u{0}']),
+         ('\u{16e6c}', ['\u{16e4c}', '\u{0}', '\u{0}']),
+         ('\u{16e6d}', ['\u{16e4d}', '\u{0}', '\u{0}']),
+         ('\u{16e6e}', ['\u{16e4e}', '\u{0}', '\u{0}']),
+         ('\u{16e6f}', ['\u{16e4f}', '\u{0}', '\u{0}']),
+         ('\u{16e70}', ['\u{16e50}', '\u{0}', '\u{0}']),
+         ('\u{16e71}', ['\u{16e51}', '\u{0}', '\u{0}']),
+         ('\u{16e72}', ['\u{16e52}', '\u{0}', '\u{0}']),
+         ('\u{16e73}', ['\u{16e53}', '\u{0}', '\u{0}']),
+         ('\u{16e74}', ['\u{16e54}', '\u{0}', '\u{0}']),
+         ('\u{16e75}', ['\u{16e55}', '\u{0}', '\u{0}']),
+         ('\u{16e76}', ['\u{16e56}', '\u{0}', '\u{0}']),
+         ('\u{16e77}', ['\u{16e57}', '\u{0}', '\u{0}']),
+         ('\u{16e78}', ['\u{16e58}', '\u{0}', '\u{0}']),
+         ('\u{16e79}', ['\u{16e59}', '\u{0}', '\u{0}']),
+         ('\u{16e7a}', ['\u{16e5a}', '\u{0}', '\u{0}']),
+         ('\u{16e7b}', ['\u{16e5b}', '\u{0}', '\u{0}']),
+         ('\u{16e7c}', ['\u{16e5c}', '\u{0}', '\u{0}']),
+         ('\u{16e7d}', ['\u{16e5d}', '\u{0}', '\u{0}']),
+         ('\u{16e7e}', ['\u{16e5e}', '\u{0}', '\u{0}']),
+         ('\u{16e7f}', ['\u{16e5f}', '\u{0}', '\u{0}']),
+         ('\u{1e922}', ['\u{1e900}', '\u{0}', '\u{0}']),
+         ('\u{1e923}', ['\u{1e901}', '\u{0}', '\u{0}']),
+         ('\u{1e924}', ['\u{1e902}', '\u{0}', '\u{0}']),
+         ('\u{1e925}', ['\u{1e903}', '\u{0}', '\u{0}']),
+         ('\u{1e926}', ['\u{1e904}', '\u{0}', '\u{0}']),
+         ('\u{1e927}', ['\u{1e905}', '\u{0}', '\u{0}']),
+         ('\u{1e928}', ['\u{1e906}', '\u{0}', '\u{0}']),
+         ('\u{1e929}', ['\u{1e907}', '\u{0}', '\u{0}']),
+         ('\u{1e92a}', ['\u{1e908}', '\u{0}', '\u{0}']),
+         ('\u{1e92b}', ['\u{1e909}', '\u{0}', '\u{0}']),
+         ('\u{1e92c}', ['\u{1e90a}', '\u{0}', '\u{0}']),
+         ('\u{1e92d}', ['\u{1e90b}', '\u{0}', '\u{0}']),
+         ('\u{1e92e}', ['\u{1e90c}', '\u{0}', '\u{0}']),
+         ('\u{1e92f}', ['\u{1e90d}', '\u{0}', '\u{0}']),
+         ('\u{1e930}', ['\u{1e90e}', '\u{0}', '\u{0}']),
+         ('\u{1e931}', ['\u{1e90f}', '\u{0}', '\u{0}']),
+         ('\u{1e932}', ['\u{1e910}', '\u{0}', '\u{0}']),
+         ('\u{1e933}', ['\u{1e911}', '\u{0}', '\u{0}']),
+         ('\u{1e934}', ['\u{1e912}', '\u{0}', '\u{0}']),
+         ('\u{1e935}', ['\u{1e913}', '\u{0}', '\u{0}']),
+         ('\u{1e936}', ['\u{1e914}', '\u{0}', '\u{0}']),
+         ('\u{1e937}', ['\u{1e915}', '\u{0}', '\u{0}']),
+         ('\u{1e938}', ['\u{1e916}', '\u{0}', '\u{0}']),
+         ('\u{1e939}', ['\u{1e917}', '\u{0}', '\u{0}']),
+         ('\u{1e93a}', ['\u{1e918}', '\u{0}', '\u{0}']),
+         ('\u{1e93b}', ['\u{1e919}', '\u{0}', '\u{0}']),
+         ('\u{1e93c}', ['\u{1e91a}', '\u{0}', '\u{0}']),
+         ('\u{1e93d}', ['\u{1e91b}', '\u{0}', '\u{0}']),
+         ('\u{1e93e}', ['\u{1e91c}', '\u{0}', '\u{0}']),
+         ('\u{1e93f}', ['\u{1e91d}', '\u{0}', '\u{0}']),
+         ('\u{1e940}', ['\u{1e91e}', '\u{0}', '\u{0}']),
+         ('\u{1e941}', ['\u{1e91f}', '\u{0}', '\u{0}']),
+         ('\u{1e942}', ['\u{1e920}', '\u{0}', '\u{0}']),
+         ('\u{1e943}', ['\u{1e921}', '\u{0}', '\u{0}']),
+     ];
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/src/unit.rs gcc-16-20251102/libgrust/rustc-lib/core/src/unit.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/src/unit.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/src/unit.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,21 ----
+ use crate::iter::FromIterator;
+ 
+ /// Collapses all unit items from an iterator into one.
+ ///
+ /// This is more useful when combined with higher-level abstractions, like
+ /// collecting to a `Result<(), E>` where you only care about errors:
+ ///
+ /// ```
+ /// use std::io::*;
+ /// let data = vec![1, 2, 3, 4, 5];
+ /// let res: Result<()> = data.iter()
+ ///     .map(|x| writeln!(stdout(), "{}", x))
+ ///     .collect();
+ /// assert!(res.is_ok());
+ /// ```
+ #[stable(feature = "unit_from_iter", since = "1.23.0")]
+ impl FromIterator<()> for () {
+     fn from_iter<I: IntoIterator<Item = ()>>(iter: I) -> Self {
+         iter.into_iter().for_each(|()| {})
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/alloc.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/alloc.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/alloc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/alloc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ use core::alloc::Layout;
+ use core::ptr::NonNull;
+ 
+ #[test]
+ fn const_unchecked_layout() {
+     const SIZE: usize = 0x2000;
+     const ALIGN: usize = 0x1000;
+     const LAYOUT: Layout = unsafe { Layout::from_size_align_unchecked(SIZE, ALIGN) };
+     const DANGLING: NonNull<u8> = LAYOUT.dangling();
+     assert_eq!(LAYOUT.size(), SIZE);
+     assert_eq!(LAYOUT.align(), ALIGN);
+     assert_eq!(Some(DANGLING), NonNull::new(ALIGN as *mut u8));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/any.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/any.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/any.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/any.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,116 ----
+ use core::any::*;
+ 
+ #[derive(PartialEq, Debug)]
+ struct Test;
+ 
+ static TEST: &'static str = "Test";
+ 
+ #[test]
+ fn any_referenced() {
+     let (a, b, c) = (&5 as &dyn Any, &TEST as &dyn Any, &Test as &dyn Any);
+ 
+     assert!(a.is::<i32>());
+     assert!(!b.is::<i32>());
+     assert!(!c.is::<i32>());
+ 
+     assert!(!a.is::<&'static str>());
+     assert!(b.is::<&'static str>());
+     assert!(!c.is::<&'static str>());
+ 
+     assert!(!a.is::<Test>());
+     assert!(!b.is::<Test>());
+     assert!(c.is::<Test>());
+ }
+ 
+ #[test]
+ fn any_owning() {
+     let (a, b, c) =
+         (box 5_usize as Box<dyn Any>, box TEST as Box<dyn Any>, box Test as Box<dyn Any>);
+ 
+     assert!(a.is::<usize>());
+     assert!(!b.is::<usize>());
+     assert!(!c.is::<usize>());
+ 
+     assert!(!a.is::<&'static str>());
+     assert!(b.is::<&'static str>());
+     assert!(!c.is::<&'static str>());
+ 
+     assert!(!a.is::<Test>());
+     assert!(!b.is::<Test>());
+     assert!(c.is::<Test>());
+ }
+ 
+ #[test]
+ fn any_downcast_ref() {
+     let a = &5_usize as &dyn Any;
+ 
+     match a.downcast_ref::<usize>() {
+         Some(&5) => {}
+         x => panic!("Unexpected value {:?}", x),
+     }
+ 
+     match a.downcast_ref::<Test>() {
+         None => {}
+         x => panic!("Unexpected value {:?}", x),
+     }
+ }
+ 
+ #[test]
+ fn any_downcast_mut() {
+     let mut a = 5_usize;
+     let mut b: Box<_> = box 7_usize;
+ 
+     let a_r = &mut a as &mut dyn Any;
+     let tmp: &mut usize = &mut *b;
+     let b_r = tmp as &mut dyn Any;
+ 
+     match a_r.downcast_mut::<usize>() {
+         Some(x) => {
+             assert_eq!(*x, 5);
+             *x = 612;
+         }
+         x => panic!("Unexpected value {:?}", x),
+     }
+ 
+     match b_r.downcast_mut::<usize>() {
+         Some(x) => {
+             assert_eq!(*x, 7);
+             *x = 413;
+         }
+         x => panic!("Unexpected value {:?}", x),
+     }
+ 
+     match a_r.downcast_mut::<Test>() {
+         None => (),
+         x => panic!("Unexpected value {:?}", x),
+     }
+ 
+     match b_r.downcast_mut::<Test>() {
+         None => (),
+         x => panic!("Unexpected value {:?}", x),
+     }
+ 
+     match a_r.downcast_mut::<usize>() {
+         Some(&mut 612) => {}
+         x => panic!("Unexpected value {:?}", x),
+     }
+ 
+     match b_r.downcast_mut::<usize>() {
+         Some(&mut 413) => {}
+         x => panic!("Unexpected value {:?}", x),
+     }
+ }
+ 
+ #[test]
+ fn any_fixed_vec() {
+     let test = [0_usize; 8];
+     let test = &test as &dyn Any;
+     assert!(test.is::<[usize; 8]>());
+     assert!(!test.is::<[usize; 10]>());
+ }
+ 
+ #[test]
+ fn any_unsized() {
+     fn is_any<T: Any + ?Sized>() {}
+     is_any::<[i32]>();
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/array.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/array.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/array.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/array.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,376 ----
+ use core::array::{self, FixedSizeArray, IntoIter};
+ use core::convert::TryFrom;
+ 
+ #[test]
+ fn fixed_size_array() {
+     let mut array = [0; 64];
+     let mut zero_sized = [(); 64];
+     let mut empty_array = [0; 0];
+     let mut empty_zero_sized = [(); 0];
+ 
+     assert_eq!(FixedSizeArray::as_slice(&array).len(), 64);
+     assert_eq!(FixedSizeArray::as_slice(&zero_sized).len(), 64);
+     assert_eq!(FixedSizeArray::as_slice(&empty_array).len(), 0);
+     assert_eq!(FixedSizeArray::as_slice(&empty_zero_sized).len(), 0);
+ 
+     assert_eq!(FixedSizeArray::as_mut_slice(&mut array).len(), 64);
+     assert_eq!(FixedSizeArray::as_mut_slice(&mut zero_sized).len(), 64);
+     assert_eq!(FixedSizeArray::as_mut_slice(&mut empty_array).len(), 0);
+     assert_eq!(FixedSizeArray::as_mut_slice(&mut empty_zero_sized).len(), 0);
+ }
+ 
+ #[test]
+ fn array_from_ref() {
+     let value: String = "Hello World!".into();
+     let arr: &[String; 1] = array::from_ref(&value);
+     assert_eq!(&[value.clone()], arr);
+ }
+ 
+ #[test]
+ fn array_from_mut() {
+     let mut value: String = "Hello World".into();
+     let arr: &mut [String; 1] = array::from_mut(&mut value);
+     arr[0].push_str("!");
+     assert_eq!(&value, "Hello World!");
+ }
+ 
+ #[test]
+ fn array_try_from() {
+     macro_rules! test {
+         ($($N:expr)+) => {
+             $({
+                 type Array = [u8; $N];
+                 let array: Array = [0; $N];
+                 let slice: &[u8] = &array[..];
+ 
+                 let result = <&Array>::try_from(slice);
+                 assert_eq!(&array, result.unwrap());
+             })+
+         }
+     }
+     test! {
+          0  1  2  3  4  5  6  7  8  9
+         10 11 12 13 14 15 16 17 18 19
+         20 21 22 23 24 25 26 27 28 29
+         30 31 32
+     }
+ }
+ 
+ #[test]
+ fn iterator_collect() {
+     let arr = [0, 1, 2, 5, 9];
+     let v: Vec<_> = IntoIter::new(arr.clone()).collect();
+     assert_eq!(&arr[..], &v[..]);
+ }
+ 
+ #[test]
+ fn iterator_rev_collect() {
+     let arr = [0, 1, 2, 5, 9];
+     let v: Vec<_> = IntoIter::new(arr.clone()).rev().collect();
+     assert_eq!(&v[..], &[9, 5, 2, 1, 0]);
+ }
+ 
+ #[test]
+ fn iterator_nth() {
+     let v = [0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(IntoIter::new(v.clone()).nth(i).unwrap(), v[i]);
+     }
+     assert_eq!(IntoIter::new(v.clone()).nth(v.len()), None);
+ 
+     let mut iter = IntoIter::new(v);
+     assert_eq!(iter.nth(2).unwrap(), v[2]);
+     assert_eq!(iter.nth(1).unwrap(), v[4]);
+ }
+ 
+ #[test]
+ fn iterator_last() {
+     let v = [0, 1, 2, 3, 4];
+     assert_eq!(IntoIter::new(v).last().unwrap(), 4);
+     assert_eq!(IntoIter::new([0]).last().unwrap(), 0);
+ 
+     let mut it = IntoIter::new([0, 9, 2, 4]);
+     assert_eq!(it.next_back(), Some(4));
+     assert_eq!(it.last(), Some(2));
+ }
+ 
+ #[test]
+ fn iterator_clone() {
+     let mut it = IntoIter::new([0, 2, 4, 6, 8]);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next_back(), Some(8));
+     let mut clone = it.clone();
+     assert_eq!(it.next_back(), Some(6));
+     assert_eq!(clone.next_back(), Some(6));
+     assert_eq!(it.next_back(), Some(4));
+     assert_eq!(clone.next_back(), Some(4));
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(clone.next(), Some(2));
+ }
+ 
+ #[test]
+ fn iterator_fused() {
+     let mut it = IntoIter::new([0, 9, 2]);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next(), Some(9));
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(it.next(), None);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn iterator_len() {
+     let mut it = IntoIter::new([0, 1, 2, 5, 9]);
+     assert_eq!(it.size_hint(), (5, Some(5)));
+     assert_eq!(it.len(), 5);
+     assert_eq!(it.is_empty(), false);
+ 
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.size_hint(), (4, Some(4)));
+     assert_eq!(it.len(), 4);
+     assert_eq!(it.is_empty(), false);
+ 
+     assert_eq!(it.next_back(), Some(9));
+     assert_eq!(it.size_hint(), (3, Some(3)));
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.is_empty(), false);
+ 
+     // Empty
+     let it = IntoIter::new([] as [String; 0]);
+     assert_eq!(it.size_hint(), (0, Some(0)));
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.is_empty(), true);
+ }
+ 
+ #[test]
+ fn iterator_count() {
+     let v = [0, 1, 2, 3, 4];
+     assert_eq!(IntoIter::new(v.clone()).count(), 5);
+ 
+     let mut iter2 = IntoIter::new(v);
+     iter2.next();
+     iter2.next();
+     assert_eq!(iter2.count(), 3);
+ }
+ 
+ #[test]
+ fn iterator_flat_map() {
+     assert!((0..5).flat_map(|i| IntoIter::new([2 * i, 2 * i + 1])).eq(0..10));
+ }
+ 
+ #[test]
+ fn iterator_debug() {
+     let arr = [0, 1, 2, 5, 9];
+     assert_eq!(format!("{:?}", IntoIter::new(arr)), "IntoIter([0, 1, 2, 5, 9])",);
+ }
+ 
+ #[test]
+ fn iterator_drops() {
+     use core::cell::Cell;
+ 
+     // This test makes sure the correct number of elements are dropped. The `R`
+     // type is just a reference to a `Cell` that is incremented when an `R` is
+     // dropped.
+ 
+     #[derive(Clone)]
+     struct Foo<'a>(&'a Cell<usize>);
+ 
+     impl Drop for Foo<'_> {
+         fn drop(&mut self) {
+             self.0.set(self.0.get() + 1);
+         }
+     }
+ 
+     fn five(i: &Cell<usize>) -> [Foo<'_>; 5] {
+         // This is somewhat verbose because `Foo` does not implement `Copy`
+         // since it implements `Drop`. Consequently, we cannot write
+         // `[Foo(i); 5]`.
+         [Foo(i), Foo(i), Foo(i), Foo(i), Foo(i)]
+     }
+ 
+     // Simple: drop new iterator.
+     let i = Cell::new(0);
+     {
+         IntoIter::new(five(&i));
+     }
+     assert_eq!(i.get(), 5);
+ 
+     // Call `next()` once.
+     let i = Cell::new(0);
+     {
+         let mut iter = IntoIter::new(five(&i));
+         let _x = iter.next();
+         assert_eq!(i.get(), 0);
+         assert_eq!(iter.count(), 4);
+         assert_eq!(i.get(), 4);
+     }
+     assert_eq!(i.get(), 5);
+ 
+     // Check `clone` and calling `next`/`next_back`.
+     let i = Cell::new(0);
+     {
+         let mut iter = IntoIter::new(five(&i));
+         iter.next();
+         assert_eq!(i.get(), 1);
+         iter.next_back();
+         assert_eq!(i.get(), 2);
+ 
+         let mut clone = iter.clone();
+         assert_eq!(i.get(), 2);
+ 
+         iter.next();
+         assert_eq!(i.get(), 3);
+ 
+         clone.next();
+         assert_eq!(i.get(), 4);
+ 
+         assert_eq!(clone.count(), 2);
+         assert_eq!(i.get(), 6);
+     }
+     assert_eq!(i.get(), 8);
+ 
+     // Check via `nth`.
+     let i = Cell::new(0);
+     {
+         let mut iter = IntoIter::new(five(&i));
+         let _x = iter.nth(2);
+         assert_eq!(i.get(), 2);
+         let _y = iter.last();
+         assert_eq!(i.get(), 3);
+     }
+     assert_eq!(i.get(), 5);
+ 
+     // Check every element.
+     let i = Cell::new(0);
+     for (index, _x) in IntoIter::new(five(&i)).enumerate() {
+         assert_eq!(i.get(), index);
+     }
+     assert_eq!(i.get(), 5);
+ 
+     let i = Cell::new(0);
+     for (index, _x) in IntoIter::new(five(&i)).rev().enumerate() {
+         assert_eq!(i.get(), index);
+     }
+     assert_eq!(i.get(), 5);
+ }
+ 
+ // This test does not work on targets without panic=unwind support.
+ // To work around this problem, test is marked is should_panic, so it will
+ // be automagically skipped on unsuitable targets, such as
+ // wasm32-unknown-unkown.
+ //
+ // It means that we use panic for indicating success.
+ #[test]
+ #[should_panic(expected = "test succeeded")]
+ fn array_default_impl_avoids_leaks_on_panic() {
+     use core::sync::atomic::{AtomicUsize, Ordering::Relaxed};
+     static COUNTER: AtomicUsize = AtomicUsize::new(0);
+     #[derive(Debug)]
+     struct Bomb(usize);
+ 
+     impl Default for Bomb {
+         fn default() -> Bomb {
+             if COUNTER.load(Relaxed) == 3 {
+                 panic!("bomb limit exceeded");
+             }
+ 
+             COUNTER.fetch_add(1, Relaxed);
+             Bomb(COUNTER.load(Relaxed))
+         }
+     }
+ 
+     impl Drop for Bomb {
+         fn drop(&mut self) {
+             COUNTER.fetch_sub(1, Relaxed);
+         }
+     }
+ 
+     let res = std::panic::catch_unwind(|| <[Bomb; 5]>::default());
+     let panic_msg = match res {
+         Ok(_) => unreachable!(),
+         Err(p) => p.downcast::<&'static str>().unwrap(),
+     };
+     assert_eq!(*panic_msg, "bomb limit exceeded");
+     // check that all bombs are successfully dropped
+     assert_eq!(COUNTER.load(Relaxed), 0);
+     panic!("test succeeded")
+ }
+ 
+ #[test]
+ fn empty_array_is_always_default() {
+     struct DoesNotImplDefault;
+ 
+     let _arr = <[DoesNotImplDefault; 0]>::default();
+ }
+ 
+ #[test]
+ fn array_map() {
+     let a = [1, 2, 3];
+     let b = a.map(|v| v + 1);
+     assert_eq!(b, [2, 3, 4]);
+ 
+     let a = [1u8, 2, 3];
+     let b = a.map(|v| v as u64);
+     assert_eq!(b, [1, 2, 3]);
+ }
+ 
+ // See note on above test for why `should_panic` is used.
+ #[test]
+ #[should_panic(expected = "test succeeded")]
+ fn array_map_drop_safety() {
+     use core::sync::atomic::AtomicUsize;
+     use core::sync::atomic::Ordering;
+     static DROPPED: AtomicUsize = AtomicUsize::new(0);
+     struct DropCounter;
+     impl Drop for DropCounter {
+         fn drop(&mut self) {
+             DROPPED.fetch_add(1, Ordering::SeqCst);
+         }
+     }
+ 
+     let num_to_create = 5;
+     let success = std::panic::catch_unwind(|| {
+         let items = [0; 10];
+         let mut nth = 0;
+         items.map(|_| {
+             assert!(nth < num_to_create);
+             nth += 1;
+             DropCounter
+         });
+     });
+     assert!(success.is_err());
+     assert_eq!(DROPPED.load(Ordering::SeqCst), num_to_create);
+     panic!("test succeeded")
+ }
+ 
+ #[test]
+ fn cell_allows_array_cycle() {
+     use core::cell::Cell;
+ 
+     #[derive(Debug)]
+     struct B<'a> {
+         a: [Cell<Option<&'a B<'a>>>; 2],
+     }
+ 
+     impl<'a> B<'a> {
+         fn new() -> B<'a> {
+             B { a: [Cell::new(None), Cell::new(None)] }
+         }
+     }
+ 
+     let b1 = B::new();
+     let b2 = B::new();
+     let b3 = B::new();
+ 
+     b1.a[0].set(Some(&b2));
+     b1.a[1].set(Some(&b3));
+ 
+     b2.a[0].set(Some(&b2));
+     b2.a[1].set(Some(&b3));
+ 
+     b3.a[0].set(Some(&b1));
+     b3.a[1].set(Some(&b2));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/ascii.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/ascii.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/ascii.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/ascii.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,410 ----
+ use core::char::from_u32;
+ 
+ #[test]
+ fn test_is_ascii() {
+     assert!(b"".is_ascii());
+     assert!(b"banana\0\x7F".is_ascii());
+     assert!(b"banana\0\x7F".iter().all(|b| b.is_ascii()));
+     assert!(!b"Vi\xe1\xbb\x87t Nam".is_ascii());
+     assert!(!b"Vi\xe1\xbb\x87t Nam".iter().all(|b| b.is_ascii()));
+     assert!(!b"\xe1\xbb\x87".iter().any(|b| b.is_ascii()));
+ 
+     assert!("".is_ascii());
+     assert!("banana\0\u{7F}".is_ascii());
+     assert!("banana\0\u{7F}".chars().all(|c| c.is_ascii()));
+     assert!(!"ประเทศไทย中华Việt Nam".chars().all(|c| c.is_ascii()));
+     assert!(!"ประเทศไทย中华ệ ".chars().any(|c| c.is_ascii()));
+ }
+ 
+ #[test]
+ fn test_to_ascii_uppercase() {
+     assert_eq!("url()URL()uRl()ürl".to_ascii_uppercase(), "URL()URL()URL()üRL");
+     assert_eq!("hıKß".to_ascii_uppercase(), "HıKß");
+ 
+     for i in 0..501 {
+         let upper =
+             if 'a' as u32 <= i && i <= 'z' as u32 { i + 'A' as u32 - 'a' as u32 } else { i };
+         assert_eq!(
+             (from_u32(i).unwrap()).to_string().to_ascii_uppercase(),
+             (from_u32(upper).unwrap()).to_string()
+         );
+     }
+ }
+ 
+ #[test]
+ fn test_to_ascii_lowercase() {
+     assert_eq!("url()URL()uRl()Ürl".to_ascii_lowercase(), "url()url()url()Ürl");
+     // Dotted capital I, Kelvin sign, Sharp S.
+     assert_eq!("HİKß".to_ascii_lowercase(), "hİKß");
+ 
+     for i in 0..501 {
+         let lower =
+             if 'A' as u32 <= i && i <= 'Z' as u32 { i + 'a' as u32 - 'A' as u32 } else { i };
+         assert_eq!(
+             (from_u32(i).unwrap()).to_string().to_ascii_lowercase(),
+             (from_u32(lower).unwrap()).to_string()
+         );
+     }
+ }
+ 
+ #[test]
+ fn test_make_ascii_lower_case() {
+     macro_rules! test {
+         ($from: expr, $to: expr) => {{
+             let mut x = $from;
+             x.make_ascii_lowercase();
+             assert_eq!(x, $to);
+         }};
+     }
+     test!(b'A', b'a');
+     test!(b'a', b'a');
+     test!(b'!', b'!');
+     test!('A', 'a');
+     test!('À', 'À');
+     test!('a', 'a');
+     test!('!', '!');
+     test!(b"H\xc3\x89".to_vec(), b"h\xc3\x89");
+     test!("HİKß".to_string(), "hİKß");
+ }
+ 
+ #[test]
+ fn test_make_ascii_upper_case() {
+     macro_rules! test {
+         ($from: expr, $to: expr) => {{
+             let mut x = $from;
+             x.make_ascii_uppercase();
+             assert_eq!(x, $to);
+         }};
+     }
+     test!(b'a', b'A');
+     test!(b'A', b'A');
+     test!(b'!', b'!');
+     test!('a', 'A');
+     test!('à', 'à');
+     test!('A', 'A');
+     test!('!', '!');
+     test!(b"h\xc3\xa9".to_vec(), b"H\xc3\xa9");
+     test!("hıKß".to_string(), "HıKß");
+ 
+     let mut x = "Hello".to_string();
+     x[..3].make_ascii_uppercase(); // Test IndexMut on String.
+     assert_eq!(x, "HELlo")
+ }
+ 
+ #[test]
+ fn test_eq_ignore_ascii_case() {
+     assert!("url()URL()uRl()Ürl".eq_ignore_ascii_case("url()url()url()Ürl"));
+     assert!(!"Ürl".eq_ignore_ascii_case("ürl"));
+     // Dotted capital I, Kelvin sign, Sharp S.
+     assert!("HİKß".eq_ignore_ascii_case("hİKß"));
+     assert!(!"İ".eq_ignore_ascii_case("i"));
+     assert!(!"K".eq_ignore_ascii_case("k"));
+     assert!(!"ß".eq_ignore_ascii_case("s"));
+ 
+     for i in 0..501 {
+         let lower =
+             if 'A' as u32 <= i && i <= 'Z' as u32 { i + 'a' as u32 - 'A' as u32 } else { i };
+         assert!(
+             (from_u32(i).unwrap())
+                 .to_string()
+                 .eq_ignore_ascii_case(&from_u32(lower).unwrap().to_string())
+         );
+     }
+ }
+ 
+ #[test]
+ fn inference_works() {
+     let x = "a".to_string();
+     x.eq_ignore_ascii_case("A");
+ }
+ 
+ // Shorthands used by the is_ascii_* tests.
+ macro_rules! assert_all {
+     ($what:ident, $($str:tt),+) => {{
+         $(
+             for b in $str.chars() {
+                 if !b.$what() {
+                     panic!("expected {}({}) but it isn't",
+                            stringify!($what), b);
+                 }
+             }
+             for b in $str.as_bytes().iter() {
+                 if !b.$what() {
+                     panic!("expected {}(0x{:02x})) but it isn't",
+                            stringify!($what), b);
+                 }
+             }
+         )+
+     }};
+     ($what:ident, $($str:tt),+,) => (assert_all!($what,$($str),+))
+ }
+ macro_rules! assert_none {
+     ($what:ident, $($str:tt),+) => {{
+         $(
+             for b in $str.chars() {
+                 if b.$what() {
+                     panic!("expected not-{}({}) but it is",
+                            stringify!($what), b);
+                 }
+             }
+             for b in $str.as_bytes().iter() {
+                 if b.$what() {
+                     panic!("expected not-{}(0x{:02x})) but it is",
+                            stringify!($what), b);
+                 }
+             }
+         )+
+     }};
+     ($what:ident, $($str:tt),+,) => (assert_none!($what,$($str),+))
+ }
+ 
+ #[test]
+ fn test_is_ascii_alphabetic() {
+     assert_all!(
+         is_ascii_alphabetic,
+         "",
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+     );
+     assert_none!(
+         is_ascii_alphabetic,
+         "0123456789",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_uppercase() {
+     assert_all!(is_ascii_uppercase, "", "ABCDEFGHIJKLMNOQPRSTUVWXYZ",);
+     assert_none!(
+         is_ascii_uppercase,
+         "abcdefghijklmnopqrstuvwxyz",
+         "0123456789",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_lowercase() {
+     assert_all!(is_ascii_lowercase, "abcdefghijklmnopqrstuvwxyz",);
+     assert_none!(
+         is_ascii_lowercase,
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "0123456789",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_alphanumeric() {
+     assert_all!(
+         is_ascii_alphanumeric,
+         "",
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "0123456789",
+     );
+     assert_none!(
+         is_ascii_alphanumeric,
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_digit() {
+     assert_all!(is_ascii_digit, "", "0123456789",);
+     assert_none!(
+         is_ascii_digit,
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_hexdigit() {
+     assert_all!(is_ascii_hexdigit, "", "0123456789", "abcdefABCDEF",);
+     assert_none!(
+         is_ascii_hexdigit,
+         "ghijklmnopqrstuvwxyz",
+         "GHIJKLMNOQPRSTUVWXYZ",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_punctuation() {
+     assert_all!(is_ascii_punctuation, "", "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",);
+     assert_none!(
+         is_ascii_punctuation,
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "0123456789",
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_graphic() {
+     assert_all!(
+         is_ascii_graphic,
+         "",
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "0123456789",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+     );
+     assert_none!(
+         is_ascii_graphic,
+         " \t\n\x0c\r",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_whitespace() {
+     assert_all!(is_ascii_whitespace, "", " \t\n\x0c\r",);
+     assert_none!(
+         is_ascii_whitespace,
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "0123456789",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x0b\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+ }
+ 
+ #[test]
+ fn test_is_ascii_control() {
+     assert_all!(
+         is_ascii_control,
+         "",
+         "\x00\x01\x02\x03\x04\x05\x06\x07",
+         "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+         "\x10\x11\x12\x13\x14\x15\x16\x17",
+         "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+         "\x7f",
+     );
+     assert_none!(
+         is_ascii_control,
+         "abcdefghijklmnopqrstuvwxyz",
+         "ABCDEFGHIJKLMNOQPRSTUVWXYZ",
+         "0123456789",
+         "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~",
+         " ",
+     );
+ }
+ 
+ // `is_ascii` does a good amount of pointer manipulation and has
+ // alignment-dependent computation. This is all sanity-checked via
+ // `debug_assert!`s, so we test various sizes/alignments thoroughly versus an
+ // "obviously correct" baseline function.
+ #[test]
+ fn test_is_ascii_align_size_thoroughly() {
+     // The "obviously-correct" baseline mentioned above.
+     fn is_ascii_baseline(s: &[u8]) -> bool {
+         s.iter().all(|b| b.is_ascii())
+     }
+ 
+     // Helper to repeat `l` copies of `b0` followed by `l` copies of `b1`.
+     fn repeat_concat(b0: u8, b1: u8, l: usize) -> Vec<u8> {
+         use core::iter::repeat;
+         repeat(b0).take(l).chain(repeat(b1).take(l)).collect()
+     }
+ 
+     // Miri is too slow
+     let iter = if cfg!(miri) { 0..20 } else { 0..100 };
+ 
+     for i in iter {
+         #[cfg(not(miri))]
+         let cases = &[
+             b"a".repeat(i),
+             b"\0".repeat(i),
+             b"\x7f".repeat(i),
+             b"\x80".repeat(i),
+             b"\xff".repeat(i),
+             repeat_concat(b'a', 0x80u8, i),
+             repeat_concat(0x80u8, b'a', i),
+         ];
+ 
+         #[cfg(miri)]
+         let cases = &[b"a".repeat(i), b"\x80".repeat(i), repeat_concat(b'a', 0x80u8, i)];
+ 
+         for case in cases {
+             for pos in 0..=case.len() {
+                 // Potentially misaligned head
+                 let prefix = &case[pos..];
+                 assert_eq!(is_ascii_baseline(prefix), prefix.is_ascii(),);
+ 
+                 // Potentially misaligned tail
+                 let suffix = &case[..case.len() - pos];
+ 
+                 assert_eq!(is_ascii_baseline(suffix), suffix.is_ascii(),);
+ 
+                 // Both head and tail are potentially misaligned
+                 let mid = &case[(pos / 2)..(case.len() - (pos / 2))];
+                 assert_eq!(is_ascii_baseline(mid), mid.is_ascii(),);
+             }
+         }
+     }
+ }
+ 
+ #[test]
+ fn ascii_const() {
+     // test that the `is_ascii` methods of `char` and `u8` are usable in a const context
+ 
+     const CHAR_IS_ASCII: bool = 'a'.is_ascii();
+     assert!(CHAR_IS_ASCII);
+ 
+     const BYTE_IS_ASCII: bool = 97u8.is_ascii();
+     assert!(BYTE_IS_ASCII);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/atomic.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/atomic.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/atomic.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/atomic.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,103 ----
+ use core::sync::atomic::Ordering::SeqCst;
+ use core::sync::atomic::*;
+ 
+ #[test]
+ fn bool_() {
+     let a = AtomicBool::new(false);
+     assert_eq!(a.compare_and_swap(false, true, SeqCst), false);
+     assert_eq!(a.compare_and_swap(false, true, SeqCst), true);
+ 
+     a.store(false, SeqCst);
+     assert_eq!(a.compare_and_swap(false, true, SeqCst), false);
+ }
+ 
+ #[test]
+ fn bool_and() {
+     let a = AtomicBool::new(true);
+     assert_eq!(a.fetch_and(false, SeqCst), true);
+     assert_eq!(a.load(SeqCst), false);
+ }
+ 
+ #[test]
+ fn bool_nand() {
+     let a = AtomicBool::new(false);
+     assert_eq!(a.fetch_nand(false, SeqCst), false);
+     assert_eq!(a.load(SeqCst), true);
+     assert_eq!(a.fetch_nand(false, SeqCst), true);
+     assert_eq!(a.load(SeqCst), true);
+     assert_eq!(a.fetch_nand(true, SeqCst), true);
+     assert_eq!(a.load(SeqCst), false);
+     assert_eq!(a.fetch_nand(true, SeqCst), false);
+     assert_eq!(a.load(SeqCst), true);
+ }
+ 
+ #[test]
+ fn uint_and() {
+     let x = AtomicUsize::new(0xf731);
+     assert_eq!(x.fetch_and(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), 0xf731 & 0x137f);
+ }
+ 
+ #[test]
+ fn uint_nand() {
+     let x = AtomicUsize::new(0xf731);
+     assert_eq!(x.fetch_nand(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), !(0xf731 & 0x137f));
+ }
+ 
+ #[test]
+ fn uint_or() {
+     let x = AtomicUsize::new(0xf731);
+     assert_eq!(x.fetch_or(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), 0xf731 | 0x137f);
+ }
+ 
+ #[test]
+ fn uint_xor() {
+     let x = AtomicUsize::new(0xf731);
+     assert_eq!(x.fetch_xor(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), 0xf731 ^ 0x137f);
+ }
+ 
+ #[test]
+ fn int_and() {
+     let x = AtomicIsize::new(0xf731);
+     assert_eq!(x.fetch_and(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), 0xf731 & 0x137f);
+ }
+ 
+ #[test]
+ fn int_nand() {
+     let x = AtomicIsize::new(0xf731);
+     assert_eq!(x.fetch_nand(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), !(0xf731 & 0x137f));
+ }
+ 
+ #[test]
+ fn int_or() {
+     let x = AtomicIsize::new(0xf731);
+     assert_eq!(x.fetch_or(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), 0xf731 | 0x137f);
+ }
+ 
+ #[test]
+ fn int_xor() {
+     let x = AtomicIsize::new(0xf731);
+     assert_eq!(x.fetch_xor(0x137f, SeqCst), 0xf731);
+     assert_eq!(x.load(SeqCst), 0xf731 ^ 0x137f);
+ }
+ 
+ static S_FALSE: AtomicBool = AtomicBool::new(false);
+ static S_TRUE: AtomicBool = AtomicBool::new(true);
+ static S_INT: AtomicIsize = AtomicIsize::new(0);
+ static S_UINT: AtomicUsize = AtomicUsize::new(0);
+ 
+ #[test]
+ fn static_init() {
+     // Note that we're not really testing the mutability here but it's important
+     // on Android at the moment (#49775)
+     assert!(!S_FALSE.swap(true, SeqCst));
+     assert!(S_TRUE.swap(false, SeqCst));
+     assert!(S_INT.fetch_add(1, SeqCst) == 0);
+     assert!(S_UINT.fetch_add(1, SeqCst) == 0);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/bool.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/bool.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/bool.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/bool.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,7 ----
+ #[test]
+ fn test_bool_to_option() {
+     assert_eq!(false.then_some(0), None);
+     assert_eq!(true.then_some(0), Some(0));
+     assert_eq!(false.then(|| 0), None);
+     assert_eq!(true.then(|| 0), Some(0));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/cell.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/cell.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/cell.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/cell.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,436 ----
+ use core::cell::*;
+ use core::default::Default;
+ use std::mem::drop;
+ 
+ #[test]
+ fn smoketest_cell() {
+     let x = Cell::new(10);
+     assert_eq!(x, Cell::new(10));
+     assert_eq!(x.get(), 10);
+     x.set(20);
+     assert_eq!(x, Cell::new(20));
+     assert_eq!(x.get(), 20);
+ 
+     let y = Cell::new((30, 40));
+     assert_eq!(y, Cell::new((30, 40)));
+     assert_eq!(y.get(), (30, 40));
+ }
+ 
+ #[test]
+ fn cell_update() {
+     let x = Cell::new(10);
+ 
+     assert_eq!(x.update(|x| x + 5), 15);
+     assert_eq!(x.get(), 15);
+ 
+     assert_eq!(x.update(|x| x / 3), 5);
+     assert_eq!(x.get(), 5);
+ }
+ 
+ #[test]
+ fn cell_has_sensible_show() {
+     let x = Cell::new("foo bar");
+     assert!(format!("{:?}", x).contains(x.get()));
+ 
+     x.set("baz qux");
+     assert!(format!("{:?}", x).contains(x.get()));
+ }
+ 
+ #[test]
+ fn ref_and_refmut_have_sensible_show() {
+     let refcell = RefCell::new("foo");
+ 
+     let refcell_refmut = refcell.borrow_mut();
+     assert!(format!("{:?}", refcell_refmut).contains("foo"));
+     drop(refcell_refmut);
+ 
+     let refcell_ref = refcell.borrow();
+     assert!(format!("{:?}", refcell_ref).contains("foo"));
+     drop(refcell_ref);
+ }
+ 
+ #[test]
+ fn double_imm_borrow() {
+     let x = RefCell::new(0);
+     let _b1 = x.borrow();
+     x.borrow();
+ }
+ 
+ #[test]
+ fn no_mut_then_imm_borrow() {
+     let x = RefCell::new(0);
+     let _b1 = x.borrow_mut();
+     assert!(x.try_borrow().is_err());
+ }
+ 
+ #[test]
+ fn no_imm_then_borrow_mut() {
+     let x = RefCell::new(0);
+     let _b1 = x.borrow();
+     assert!(x.try_borrow_mut().is_err());
+ }
+ 
+ #[test]
+ fn no_double_borrow_mut() {
+     let x = RefCell::new(0);
+     assert!(x.try_borrow().is_ok());
+     let _b1 = x.borrow_mut();
+     assert!(x.try_borrow().is_err());
+ }
+ 
+ #[test]
+ fn imm_release_borrow_mut() {
+     let x = RefCell::new(0);
+     {
+         let _b1 = x.borrow();
+     }
+     x.borrow_mut();
+ }
+ 
+ #[test]
+ fn mut_release_borrow_mut() {
+     let x = RefCell::new(0);
+     {
+         let _b1 = x.borrow_mut();
+     }
+     x.borrow();
+ }
+ 
+ #[test]
+ fn double_borrow_single_release_no_borrow_mut() {
+     let x = RefCell::new(0);
+     let _b1 = x.borrow();
+     {
+         let _b2 = x.borrow();
+     }
+     assert!(x.try_borrow().is_ok());
+     assert!(x.try_borrow_mut().is_err());
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn discard_doesnt_unborrow() {
+     let x = RefCell::new(0);
+     let _b = x.borrow();
+     let _ = _b;
+     let _b = x.borrow_mut();
+ }
+ 
+ #[test]
+ fn ref_clone_updates_flag() {
+     let x = RefCell::new(0);
+     {
+         let b1 = x.borrow();
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_err());
+         {
+             let _b2 = Ref::clone(&b1);
+             assert!(x.try_borrow().is_ok());
+             assert!(x.try_borrow_mut().is_err());
+         }
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_err());
+     }
+     assert!(x.try_borrow().is_ok());
+     assert!(x.try_borrow_mut().is_ok());
+ }
+ 
+ #[test]
+ fn ref_map_does_not_update_flag() {
+     let x = RefCell::new(Some(5));
+     {
+         let b1: Ref<'_, Option<u32>> = x.borrow();
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_err());
+         {
+             let b2: Ref<'_, u32> = Ref::map(b1, |o| o.as_ref().unwrap());
+             assert_eq!(*b2, 5);
+             assert!(x.try_borrow().is_ok());
+             assert!(x.try_borrow_mut().is_err());
+         }
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_ok());
+     }
+     assert!(x.try_borrow().is_ok());
+     assert!(x.try_borrow_mut().is_ok());
+ }
+ 
+ #[test]
+ fn ref_map_split_updates_flag() {
+     let x = RefCell::new([1, 2]);
+     {
+         let b1 = x.borrow();
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_err());
+         {
+             let (_b2, _b3) = Ref::map_split(b1, |slc| slc.split_at(1));
+             assert!(x.try_borrow().is_ok());
+             assert!(x.try_borrow_mut().is_err());
+         }
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_ok());
+     }
+     assert!(x.try_borrow().is_ok());
+     assert!(x.try_borrow_mut().is_ok());
+ 
+     {
+         let b1 = x.borrow_mut();
+         assert!(x.try_borrow().is_err());
+         assert!(x.try_borrow_mut().is_err());
+         {
+             let (_b2, _b3) = RefMut::map_split(b1, |slc| slc.split_at_mut(1));
+             assert!(x.try_borrow().is_err());
+             assert!(x.try_borrow_mut().is_err());
+             drop(_b2);
+             assert!(x.try_borrow().is_err());
+             assert!(x.try_borrow_mut().is_err());
+         }
+         assert!(x.try_borrow().is_ok());
+         assert!(x.try_borrow_mut().is_ok());
+     }
+     assert!(x.try_borrow().is_ok());
+     assert!(x.try_borrow_mut().is_ok());
+ }
+ 
+ #[test]
+ fn ref_map_split() {
+     let x = RefCell::new([1, 2]);
+     let (b1, b2) = Ref::map_split(x.borrow(), |slc| slc.split_at(1));
+     assert_eq!(*b1, [1]);
+     assert_eq!(*b2, [2]);
+ }
+ 
+ #[test]
+ fn ref_mut_map_split() {
+     let x = RefCell::new([1, 2]);
+     {
+         let (mut b1, mut b2) = RefMut::map_split(x.borrow_mut(), |slc| slc.split_at_mut(1));
+         assert_eq!(*b1, [1]);
+         assert_eq!(*b2, [2]);
+         b1[0] = 2;
+         b2[0] = 1;
+     }
+     assert_eq!(*x.borrow(), [2, 1]);
+ }
+ 
+ #[test]
+ fn ref_map_accessor() {
+     struct X(RefCell<(u32, char)>);
+     impl X {
+         fn accessor(&self) -> Ref<'_, u32> {
+             Ref::map(self.0.borrow(), |tuple| &tuple.0)
+         }
+     }
+     let x = X(RefCell::new((7, 'z')));
+     let d: Ref<'_, u32> = x.accessor();
+     assert_eq!(*d, 7);
+ }
+ 
+ #[test]
+ fn ref_mut_map_accessor() {
+     struct X(RefCell<(u32, char)>);
+     impl X {
+         fn accessor(&self) -> RefMut<'_, u32> {
+             RefMut::map(self.0.borrow_mut(), |tuple| &mut tuple.0)
+         }
+     }
+     let x = X(RefCell::new((7, 'z')));
+     {
+         let mut d: RefMut<'_, u32> = x.accessor();
+         assert_eq!(*d, 7);
+         *d += 1;
+     }
+     assert_eq!(*x.0.borrow(), (8, 'z'));
+ }
+ 
+ #[test]
+ fn as_ptr() {
+     let c1: Cell<usize> = Cell::new(0);
+     c1.set(1);
+     assert_eq!(1, unsafe { *c1.as_ptr() });
+ 
+     let c2: Cell<usize> = Cell::new(0);
+     unsafe {
+         *c2.as_ptr() = 1;
+     }
+     assert_eq!(1, c2.get());
+ 
+     let r1: RefCell<usize> = RefCell::new(0);
+     *r1.borrow_mut() = 1;
+     assert_eq!(1, unsafe { *r1.as_ptr() });
+ 
+     let r2: RefCell<usize> = RefCell::new(0);
+     unsafe {
+         *r2.as_ptr() = 1;
+     }
+     assert_eq!(1, *r2.borrow());
+ }
+ 
+ #[test]
+ fn cell_default() {
+     let cell: Cell<u32> = Default::default();
+     assert_eq!(0, cell.get());
+ }
+ 
+ #[test]
+ fn cell_set() {
+     let cell = Cell::new(10);
+     cell.set(20);
+     assert_eq!(20, cell.get());
+ 
+     let cell = Cell::new("Hello".to_owned());
+     cell.set("World".to_owned());
+     assert_eq!("World".to_owned(), cell.into_inner());
+ }
+ 
+ #[test]
+ fn cell_replace() {
+     let cell = Cell::new(10);
+     assert_eq!(10, cell.replace(20));
+     assert_eq!(20, cell.get());
+ 
+     let cell = Cell::new("Hello".to_owned());
+     assert_eq!("Hello".to_owned(), cell.replace("World".to_owned()));
+     assert_eq!("World".to_owned(), cell.into_inner());
+ }
+ 
+ #[test]
+ fn cell_into_inner() {
+     let cell = Cell::new(10);
+     assert_eq!(10, cell.into_inner());
+ 
+     let cell = Cell::new("Hello world".to_owned());
+     assert_eq!("Hello world".to_owned(), cell.into_inner());
+ }
+ 
+ #[test]
+ fn cell_exterior() {
+     #[derive(Copy, Clone)]
+     #[allow(dead_code)]
+     struct Point {
+         x: isize,
+         y: isize,
+         z: isize,
+     }
+ 
+     fn f(p: &Cell<Point>) {
+         assert_eq!(p.get().z, 12);
+         p.set(Point { x: 10, y: 11, z: 13 });
+         assert_eq!(p.get().z, 13);
+     }
+ 
+     let a = Point { x: 10, y: 11, z: 12 };
+     let b = &Cell::new(a);
+     assert_eq!(b.get().z, 12);
+     f(b);
+     assert_eq!(a.z, 12);
+     assert_eq!(b.get().z, 13);
+ }
+ 
+ #[test]
+ fn cell_does_not_clone() {
+     #[derive(Copy)]
+     #[allow(dead_code)]
+     struct Foo {
+         x: isize,
+     }
+ 
+     impl Clone for Foo {
+         fn clone(&self) -> Foo {
+             // Using Cell in any way should never cause clone() to be
+             // invoked -- after all, that would permit evil user code to
+             // abuse `Cell` and trigger crashes.
+ 
+             panic!();
+         }
+     }
+ 
+     let x = Cell::new(Foo { x: 22 });
+     let _y = x.get();
+     let _z = x.clone();
+ }
+ 
+ #[test]
+ fn refcell_default() {
+     let cell: RefCell<u64> = Default::default();
+     assert_eq!(0, *cell.borrow());
+ }
+ 
+ #[test]
+ fn unsafe_cell_unsized() {
+     let cell: &UnsafeCell<[i32]> = &UnsafeCell::new([1, 2, 3]);
+     {
+         let val: &mut [i32] = unsafe { &mut *cell.get() };
+         val[0] = 4;
+         val[2] = 5;
+     }
+     let comp: &mut [i32] = &mut [4, 2, 5];
+     assert_eq!(unsafe { &mut *cell.get() }, comp);
+ }
+ 
+ #[test]
+ fn refcell_unsized() {
+     let cell: &RefCell<[i32]> = &RefCell::new([1, 2, 3]);
+     {
+         let b = &mut *cell.borrow_mut();
+         b[0] = 4;
+         b[2] = 5;
+     }
+     let comp: &mut [i32] = &mut [4, 2, 5];
+     assert_eq!(&*cell.borrow(), comp);
+ }
+ 
+ #[test]
+ fn refcell_ref_coercion() {
+     let cell: RefCell<[i32; 3]> = RefCell::new([1, 2, 3]);
+     {
+         let mut cellref: RefMut<'_, [i32; 3]> = cell.borrow_mut();
+         cellref[0] = 4;
+         let mut coerced: RefMut<'_, [i32]> = cellref;
+         coerced[2] = 5;
+     }
+     {
+         let comp: &mut [i32] = &mut [4, 2, 5];
+         let cellref: Ref<'_, [i32; 3]> = cell.borrow();
+         assert_eq!(&*cellref, comp);
+         let coerced: Ref<'_, [i32]> = cellref;
+         assert_eq!(&*coerced, comp);
+     }
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn refcell_swap_borrows() {
+     let x = RefCell::new(0);
+     let _b = x.borrow();
+     let y = RefCell::new(1);
+     x.swap(&y);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn refcell_replace_borrows() {
+     let x = RefCell::new(0);
+     let _b = x.borrow();
+     x.replace(1);
+ }
+ 
+ #[test]
+ fn refcell_format() {
+     let name = RefCell::new("rust");
+     let what = RefCell::new("rocks");
+     let msg = format!("{name} {}", &*what.borrow(), name = &*name.borrow());
+     assert_eq!(msg, "rust rocks".to_string());
+ }
+ 
+ #[allow(dead_code)]
+ fn const_cells() {
+     const UNSAFE_CELL: UnsafeCell<i32> = UnsafeCell::new(3);
+     const _: i32 = UNSAFE_CELL.into_inner();
+ 
+     const REF_CELL: RefCell<i32> = RefCell::new(3);
+     const _: i32 = REF_CELL.into_inner();
+ 
+     const CELL: Cell<i32> = Cell::new(3);
+     const _: i32 = CELL.into_inner();
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/char.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/char.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/char.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/char.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,360 ----
+ use std::convert::TryFrom;
+ use std::str::FromStr;
+ use std::{char, str};
+ 
+ #[test]
+ fn test_convert() {
+     assert_eq!(u32::from('a'), 0x61);
+     assert_eq!(char::from(b'\0'), '\0');
+     assert_eq!(char::from(b'a'), 'a');
+     assert_eq!(char::from(b'\xFF'), '\u{FF}');
+     assert_eq!(char::try_from(0_u32), Ok('\0'));
+     assert_eq!(char::try_from(0x61_u32), Ok('a'));
+     assert_eq!(char::try_from(0xD7FF_u32), Ok('\u{D7FF}'));
+     assert!(char::try_from(0xD800_u32).is_err());
+     assert!(char::try_from(0xDFFF_u32).is_err());
+     assert_eq!(char::try_from(0xE000_u32), Ok('\u{E000}'));
+     assert_eq!(char::try_from(0x10FFFF_u32), Ok('\u{10FFFF}'));
+     assert!(char::try_from(0x110000_u32).is_err());
+     assert!(char::try_from(0xFFFF_FFFF_u32).is_err());
+ }
+ 
+ #[test]
+ fn test_from_str() {
+     assert_eq!(char::from_str("a").unwrap(), 'a');
+     assert_eq!(char::from_str("\0").unwrap(), '\0');
+     assert_eq!(char::from_str("\u{D7FF}").unwrap(), '\u{d7FF}');
+     assert!(char::from_str("").is_err());
+     assert!(char::from_str("abc").is_err());
+ }
+ 
+ #[test]
+ fn test_is_lowercase() {
+     assert!('a'.is_lowercase());
+     assert!('ö'.is_lowercase());
+     assert!('ß'.is_lowercase());
+     assert!(!'Ü'.is_lowercase());
+     assert!(!'P'.is_lowercase());
+ }
+ 
+ #[test]
+ fn test_is_uppercase() {
+     assert!(!'h'.is_uppercase());
+     assert!(!'ä'.is_uppercase());
+     assert!(!'ß'.is_uppercase());
+     assert!('Ö'.is_uppercase());
+     assert!('T'.is_uppercase());
+ }
+ 
+ #[test]
+ fn test_is_whitespace() {
+     assert!(' '.is_whitespace());
+     assert!('\u{2007}'.is_whitespace());
+     assert!('\t'.is_whitespace());
+     assert!('\n'.is_whitespace());
+     assert!(!'a'.is_whitespace());
+     assert!(!'_'.is_whitespace());
+     assert!(!'\u{0}'.is_whitespace());
+ }
+ 
+ #[test]
+ fn test_to_digit() {
+     assert_eq!('0'.to_digit(10), Some(0));
+     assert_eq!('1'.to_digit(2), Some(1));
+     assert_eq!('2'.to_digit(3), Some(2));
+     assert_eq!('9'.to_digit(10), Some(9));
+     assert_eq!('a'.to_digit(16), Some(10));
+     assert_eq!('A'.to_digit(16), Some(10));
+     assert_eq!('b'.to_digit(16), Some(11));
+     assert_eq!('B'.to_digit(16), Some(11));
+     assert_eq!('z'.to_digit(36), Some(35));
+     assert_eq!('Z'.to_digit(36), Some(35));
+     assert_eq!(' '.to_digit(10), None);
+     assert_eq!('$'.to_digit(36), None);
+ }
+ 
+ #[test]
+ fn test_to_lowercase() {
+     fn lower(c: char) -> String {
+         let to_lowercase = c.to_lowercase();
+         assert_eq!(to_lowercase.len(), to_lowercase.count());
+         let iter: String = c.to_lowercase().collect();
+         let disp: String = c.to_lowercase().to_string();
+         assert_eq!(iter, disp);
+         iter
+     }
+     assert_eq!(lower('A'), "a");
+     assert_eq!(lower('Ö'), "ö");
+     assert_eq!(lower('ß'), "ß");
+     assert_eq!(lower('Ü'), "ü");
+     assert_eq!(lower('💩'), "💩");
+     assert_eq!(lower('Σ'), "σ");
+     assert_eq!(lower('Τ'), "τ");
+     assert_eq!(lower('Ι'), "ι");
+     assert_eq!(lower('Γ'), "γ");
+     assert_eq!(lower('Μ'), "μ");
+     assert_eq!(lower('Α'), "α");
+     assert_eq!(lower('Σ'), "σ");
+     assert_eq!(lower('ǅ'), "ǆ");
+     assert_eq!(lower('ﬁ'), "ﬁ");
+     assert_eq!(lower('İ'), "i\u{307}");
+ }
+ 
+ #[test]
+ fn test_to_uppercase() {
+     fn upper(c: char) -> String {
+         let to_uppercase = c.to_uppercase();
+         assert_eq!(to_uppercase.len(), to_uppercase.count());
+         let iter: String = c.to_uppercase().collect();
+         let disp: String = c.to_uppercase().to_string();
+         assert_eq!(iter, disp);
+         iter
+     }
+     assert_eq!(upper('a'), "A");
+     assert_eq!(upper('ö'), "Ö");
+     assert_eq!(upper('ß'), "SS"); // not ẞ: Latin capital letter sharp s
+     assert_eq!(upper('ü'), "Ü");
+     assert_eq!(upper('💩'), "💩");
+ 
+     assert_eq!(upper('σ'), "Σ");
+     assert_eq!(upper('τ'), "Τ");
+     assert_eq!(upper('ι'), "Ι");
+     assert_eq!(upper('γ'), "Γ");
+     assert_eq!(upper('μ'), "Μ");
+     assert_eq!(upper('α'), "Α");
+     assert_eq!(upper('ς'), "Σ");
+     assert_eq!(upper('ǅ'), "Ǆ");
+     assert_eq!(upper('ﬁ'), "FI");
+     assert_eq!(upper('ᾀ'), "ἈΙ");
+ }
+ 
+ #[test]
+ fn test_is_control() {
+     assert!('\u{0}'.is_control());
+     assert!('\u{3}'.is_control());
+     assert!('\u{6}'.is_control());
+     assert!('\u{9}'.is_control());
+     assert!('\u{7f}'.is_control());
+     assert!('\u{92}'.is_control());
+     assert!(!'\u{20}'.is_control());
+     assert!(!'\u{55}'.is_control());
+     assert!(!'\u{68}'.is_control());
+ }
+ 
+ #[test]
+ fn test_is_numeric() {
+     assert!('2'.is_numeric());
+     assert!('7'.is_numeric());
+     assert!('¾'.is_numeric());
+     assert!(!'c'.is_numeric());
+     assert!(!'i'.is_numeric());
+     assert!(!'z'.is_numeric());
+     assert!(!'Q'.is_numeric());
+ }
+ 
+ #[test]
+ fn test_escape_debug() {
+     fn string(c: char) -> String {
+         let iter: String = c.escape_debug().collect();
+         let disp: String = c.escape_debug().to_string();
+         assert_eq!(iter, disp);
+         iter
+     }
+     assert_eq!(string('\n'), "\\n");
+     assert_eq!(string('\r'), "\\r");
+     assert_eq!(string('\''), "\\'");
+     assert_eq!(string('"'), "\\\"");
+     assert_eq!(string(' '), " ");
+     assert_eq!(string('a'), "a");
+     assert_eq!(string('~'), "~");
+     assert_eq!(string('é'), "é");
+     assert_eq!(string('文'), "文");
+     assert_eq!(string('\x00'), "\\u{0}");
+     assert_eq!(string('\x1f'), "\\u{1f}");
+     assert_eq!(string('\x7f'), "\\u{7f}");
+     assert_eq!(string('\u{80}'), "\\u{80}");
+     assert_eq!(string('\u{ff}'), "\u{ff}");
+     assert_eq!(string('\u{11b}'), "\u{11b}");
+     assert_eq!(string('\u{1d4b6}'), "\u{1d4b6}");
+     assert_eq!(string('\u{301}'), "\\u{301}"); // combining character
+     assert_eq!(string('\u{200b}'), "\\u{200b}"); // zero width space
+     assert_eq!(string('\u{e000}'), "\\u{e000}"); // private use 1
+     assert_eq!(string('\u{100000}'), "\\u{100000}"); // private use 2
+ }
+ 
+ #[test]
+ fn test_escape_default() {
+     fn string(c: char) -> String {
+         let iter: String = c.escape_default().collect();
+         let disp: String = c.escape_default().to_string();
+         assert_eq!(iter, disp);
+         iter
+     }
+     assert_eq!(string('\n'), "\\n");
+     assert_eq!(string('\r'), "\\r");
+     assert_eq!(string('\''), "\\'");
+     assert_eq!(string('"'), "\\\"");
+     assert_eq!(string(' '), " ");
+     assert_eq!(string('a'), "a");
+     assert_eq!(string('~'), "~");
+     assert_eq!(string('é'), "\\u{e9}");
+     assert_eq!(string('\x00'), "\\u{0}");
+     assert_eq!(string('\x1f'), "\\u{1f}");
+     assert_eq!(string('\x7f'), "\\u{7f}");
+     assert_eq!(string('\u{80}'), "\\u{80}");
+     assert_eq!(string('\u{ff}'), "\\u{ff}");
+     assert_eq!(string('\u{11b}'), "\\u{11b}");
+     assert_eq!(string('\u{1d4b6}'), "\\u{1d4b6}");
+     assert_eq!(string('\u{200b}'), "\\u{200b}"); // zero width space
+     assert_eq!(string('\u{e000}'), "\\u{e000}"); // private use 1
+     assert_eq!(string('\u{100000}'), "\\u{100000}"); // private use 2
+ }
+ 
+ #[test]
+ fn test_escape_unicode() {
+     fn string(c: char) -> String {
+         let iter: String = c.escape_unicode().collect();
+         let disp: String = c.escape_unicode().to_string();
+         assert_eq!(iter, disp);
+         iter
+     }
+ 
+     assert_eq!(string('\x00'), "\\u{0}");
+     assert_eq!(string('\n'), "\\u{a}");
+     assert_eq!(string(' '), "\\u{20}");
+     assert_eq!(string('a'), "\\u{61}");
+     assert_eq!(string('\u{11b}'), "\\u{11b}");
+     assert_eq!(string('\u{1d4b6}'), "\\u{1d4b6}");
+ }
+ 
+ #[test]
+ fn test_encode_utf8() {
+     fn check(input: char, expect: &[u8]) {
+         let mut buf = [0; 4];
+         let ptr = buf.as_ptr();
+         let s = input.encode_utf8(&mut buf);
+         assert_eq!(s.as_ptr() as usize, ptr as usize);
+         assert!(str::from_utf8(s.as_bytes()).is_ok());
+         assert_eq!(s.as_bytes(), expect);
+     }
+ 
+     check('x', &[0x78]);
+     check('\u{e9}', &[0xc3, 0xa9]);
+     check('\u{a66e}', &[0xea, 0x99, 0xae]);
+     check('\u{1f4a9}', &[0xf0, 0x9f, 0x92, 0xa9]);
+ }
+ 
+ #[test]
+ fn test_encode_utf16() {
+     fn check(input: char, expect: &[u16]) {
+         let mut buf = [0; 2];
+         let ptr = buf.as_mut_ptr();
+         let b = input.encode_utf16(&mut buf);
+         assert_eq!(b.as_mut_ptr() as usize, ptr as usize);
+         assert_eq!(b, expect);
+     }
+ 
+     check('x', &[0x0078]);
+     check('\u{e9}', &[0x00e9]);
+     check('\u{a66e}', &[0xa66e]);
+     check('\u{1f4a9}', &[0xd83d, 0xdca9]);
+ }
+ 
+ #[test]
+ fn test_len_utf16() {
+     assert!('x'.len_utf16() == 1);
+     assert!('\u{e9}'.len_utf16() == 1);
+     assert!('\u{a66e}'.len_utf16() == 1);
+     assert!('\u{1f4a9}'.len_utf16() == 2);
+ }
+ 
+ #[test]
+ fn test_decode_utf16() {
+     fn check(s: &[u16], expected: &[Result<char, u16>]) {
+         let v = char::decode_utf16(s.iter().cloned())
+             .map(|r| r.map_err(|e| e.unpaired_surrogate()))
+             .collect::<Vec<_>>();
+         assert_eq!(v, expected);
+     }
+     check(&[0xD800, 0x41, 0x42], &[Err(0xD800), Ok('A'), Ok('B')]);
+     check(&[0xD800, 0], &[Err(0xD800), Ok('\0')]);
+ }
+ 
+ #[test]
+ fn ed_iterator_specializations() {
+     // Check counting
+     assert_eq!('\n'.escape_default().count(), 2);
+     assert_eq!('c'.escape_default().count(), 1);
+     assert_eq!(' '.escape_default().count(), 1);
+     assert_eq!('\\'.escape_default().count(), 2);
+     assert_eq!('\''.escape_default().count(), 2);
+ 
+     // Check nth
+ 
+     // Check that OoB is handled correctly
+     assert_eq!('\n'.escape_default().nth(2), None);
+     assert_eq!('c'.escape_default().nth(1), None);
+     assert_eq!(' '.escape_default().nth(1), None);
+     assert_eq!('\\'.escape_default().nth(2), None);
+     assert_eq!('\''.escape_default().nth(2), None);
+ 
+     // Check the first char
+     assert_eq!('\n'.escape_default().nth(0), Some('\\'));
+     assert_eq!('c'.escape_default().nth(0), Some('c'));
+     assert_eq!(' '.escape_default().nth(0), Some(' '));
+     assert_eq!('\\'.escape_default().nth(0), Some('\\'));
+     assert_eq!('\''.escape_default().nth(0), Some('\\'));
+ 
+     // Check the second char
+     assert_eq!('\n'.escape_default().nth(1), Some('n'));
+     assert_eq!('\\'.escape_default().nth(1), Some('\\'));
+     assert_eq!('\''.escape_default().nth(1), Some('\''));
+ 
+     // Check the last char
+     assert_eq!('\n'.escape_default().last(), Some('n'));
+     assert_eq!('c'.escape_default().last(), Some('c'));
+     assert_eq!(' '.escape_default().last(), Some(' '));
+     assert_eq!('\\'.escape_default().last(), Some('\\'));
+     assert_eq!('\''.escape_default().last(), Some('\''));
+ }
+ 
+ #[test]
+ fn eu_iterator_specializations() {
+     fn check(c: char) {
+         let len = c.escape_unicode().count();
+ 
+         // Check OoB
+         assert_eq!(c.escape_unicode().nth(len), None);
+ 
+         // For all possible in-bound offsets
+         let mut iter = c.escape_unicode();
+         for offset in 0..len {
+             // Check last
+             assert_eq!(iter.clone().last(), Some('}'));
+ 
+             // Check len
+             assert_eq!(iter.len(), len - offset);
+ 
+             // Check size_hint (= len in ExactSizeIterator)
+             assert_eq!(iter.size_hint(), (iter.len(), Some(iter.len())));
+ 
+             // Check counting
+             assert_eq!(iter.clone().count(), len - offset);
+ 
+             // Check nth
+             assert_eq!(c.escape_unicode().nth(offset), iter.next());
+         }
+ 
+         // Check post-last
+         assert_eq!(iter.clone().last(), None);
+         assert_eq!(iter.clone().count(), 0);
+     }
+ 
+     check('\u{0}');
+     check('\u{1}');
+     check('\u{12}');
+     check('\u{123}');
+     check('\u{1234}');
+     check('\u{12340}');
+     check('\u{10FFFF}');
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/clone.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/clone.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/clone.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/clone.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,15 ----
+ #[test]
+ fn test_borrowed_clone() {
+     let x = 5;
+     let y: &i32 = &x;
+     let z: &i32 = (&y).clone();
+     assert_eq!(*z, 5);
+ }
+ 
+ #[test]
+ fn test_clone_from() {
+     let a = box 5;
+     let mut b = box 10;
+     b.clone_from(&a);
+     assert_eq!(*b, 5);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/cmp.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/cmp.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/cmp.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/cmp.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,134 ----
+ use core::cmp::{
+     self,
+     Ordering::{self, *},
+ };
+ 
+ #[test]
+ fn test_int_totalord() {
+     assert_eq!(5.cmp(&10), Less);
+     assert_eq!(10.cmp(&5), Greater);
+     assert_eq!(5.cmp(&5), Equal);
+     assert_eq!((-5).cmp(&12), Less);
+     assert_eq!(12.cmp(&-5), Greater);
+ }
+ 
+ #[test]
+ fn test_bool_totalord() {
+     assert_eq!(true.cmp(&false), Greater);
+     assert_eq!(false.cmp(&true), Less);
+     assert_eq!(true.cmp(&true), Equal);
+     assert_eq!(false.cmp(&false), Equal);
+ }
+ 
+ #[test]
+ fn test_mut_int_totalord() {
+     assert_eq!((&mut 5).cmp(&&mut 10), Less);
+     assert_eq!((&mut 10).cmp(&&mut 5), Greater);
+     assert_eq!((&mut 5).cmp(&&mut 5), Equal);
+     assert_eq!((&mut -5).cmp(&&mut 12), Less);
+     assert_eq!((&mut 12).cmp(&&mut -5), Greater);
+ }
+ 
+ #[test]
+ fn test_ord_max_min() {
+     assert_eq!(1.max(2), 2);
+     assert_eq!(2.max(1), 2);
+     assert_eq!(1.min(2), 1);
+     assert_eq!(2.min(1), 1);
+     assert_eq!(1.max(1), 1);
+     assert_eq!(1.min(1), 1);
+ }
+ 
+ #[test]
+ fn test_ord_min_max_by() {
+     let f = |x: &i32, y: &i32| x.abs().cmp(&y.abs());
+     assert_eq!(cmp::min_by(1, -1, f), 1);
+     assert_eq!(cmp::min_by(1, -2, f), 1);
+     assert_eq!(cmp::min_by(2, -1, f), -1);
+     assert_eq!(cmp::max_by(1, -1, f), -1);
+     assert_eq!(cmp::max_by(1, -2, f), -2);
+     assert_eq!(cmp::max_by(2, -1, f), 2);
+ }
+ 
+ #[test]
+ fn test_ord_min_max_by_key() {
+     let f = |x: &i32| x.abs();
+     assert_eq!(cmp::min_by_key(1, -1, f), 1);
+     assert_eq!(cmp::min_by_key(1, -2, f), 1);
+     assert_eq!(cmp::min_by_key(2, -1, f), -1);
+     assert_eq!(cmp::max_by_key(1, -1, f), -1);
+     assert_eq!(cmp::max_by_key(1, -2, f), -2);
+     assert_eq!(cmp::max_by_key(2, -1, f), 2);
+ }
+ 
+ #[test]
+ fn test_ordering_reverse() {
+     assert_eq!(Less.reverse(), Greater);
+     assert_eq!(Equal.reverse(), Equal);
+     assert_eq!(Greater.reverse(), Less);
+ }
+ 
+ #[test]
+ fn test_ordering_order() {
+     assert!(Less < Equal);
+     assert_eq!(Greater.cmp(&Less), Greater);
+ }
+ 
+ #[test]
+ fn test_ordering_then() {
+     assert_eq!(Equal.then(Less), Less);
+     assert_eq!(Equal.then(Equal), Equal);
+     assert_eq!(Equal.then(Greater), Greater);
+     assert_eq!(Less.then(Less), Less);
+     assert_eq!(Less.then(Equal), Less);
+     assert_eq!(Less.then(Greater), Less);
+     assert_eq!(Greater.then(Less), Greater);
+     assert_eq!(Greater.then(Equal), Greater);
+     assert_eq!(Greater.then(Greater), Greater);
+ }
+ 
+ #[test]
+ fn test_ordering_then_with() {
+     assert_eq!(Equal.then_with(|| Less), Less);
+     assert_eq!(Equal.then_with(|| Equal), Equal);
+     assert_eq!(Equal.then_with(|| Greater), Greater);
+     assert_eq!(Less.then_with(|| Less), Less);
+     assert_eq!(Less.then_with(|| Equal), Less);
+     assert_eq!(Less.then_with(|| Greater), Less);
+     assert_eq!(Greater.then_with(|| Less), Greater);
+     assert_eq!(Greater.then_with(|| Equal), Greater);
+     assert_eq!(Greater.then_with(|| Greater), Greater);
+ }
+ 
+ #[test]
+ fn test_user_defined_eq() {
+     // Our type.
+     struct SketchyNum {
+         num: isize,
+     }
+ 
+     // Our implementation of `PartialEq` to support `==` and `!=`.
+     impl PartialEq for SketchyNum {
+         // Our custom eq allows numbers which are near each other to be equal! :D
+         fn eq(&self, other: &SketchyNum) -> bool {
+             (self.num - other.num).abs() < 5
+         }
+     }
+ 
+     // Now these binary operators will work when applied!
+     assert!(SketchyNum { num: 37 } == SketchyNum { num: 34 });
+     assert!(SketchyNum { num: 25 } != SketchyNum { num: 57 });
+ }
+ 
+ #[test]
+ fn ordering_const() {
+     // test that the methods of `Ordering` are usable in a const context
+ 
+     const ORDERING: Ordering = Greater;
+ 
+     const REVERSE: Ordering = ORDERING.reverse();
+     assert_eq!(REVERSE, Less);
+ 
+     const THEN: Ordering = Equal.then(ORDERING);
+     assert_eq!(THEN, Greater);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/builders.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/builders.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/builders.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/builders.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,730 ----
+ mod debug_struct {
+     use std::fmt;
+ 
+     #[test]
+     fn test_empty() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo").finish()
+             }
+         }
+ 
+         assert_eq!("Foo", format!("{:?}", Foo));
+         assert_eq!("Foo", format!("{:#?}", Foo));
+     }
+ 
+     #[test]
+     fn test_single() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo").field("bar", &true).finish()
+             }
+         }
+ 
+         assert_eq!("Foo { bar: true }", format!("{:?}", Foo));
+         assert_eq!(
+             "Foo {
+     bar: true,
+ }",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_multiple() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo")
+                     .field("bar", &true)
+                     .field("baz", &format_args!("{}/{}", 10, 20))
+                     .finish()
+             }
+         }
+ 
+         assert_eq!("Foo { bar: true, baz: 10/20 }", format!("{:?}", Foo));
+         assert_eq!(
+             "Foo {
+     bar: true,
+     baz: 10/20,
+ }",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_nested() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo")
+                     .field("bar", &true)
+                     .field("baz", &format_args!("{}/{}", 10, 20))
+                     .finish()
+             }
+         }
+ 
+         struct Bar;
+ 
+         impl fmt::Debug for Bar {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Bar").field("foo", &Foo).field("hello", &"world").finish()
+             }
+         }
+ 
+         assert_eq!(
+             "Bar { foo: Foo { bar: true, baz: 10/20 }, hello: \"world\" }",
+             format!("{:?}", Bar)
+         );
+         assert_eq!(
+             "Bar {
+     foo: Foo {
+         bar: true,
+         baz: 10/20,
+     },
+     hello: \"world\",
+ }",
+             format!("{:#?}", Bar)
+         );
+     }
+ 
+     #[test]
+     fn test_only_non_exhaustive() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo").finish_non_exhaustive()
+             }
+         }
+ 
+         assert_eq!("Foo { .. }", format!("{:?}", Foo));
+         assert_eq!(
+             "Foo {
+     ..
+ }",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_multiple_and_non_exhaustive() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo")
+                     .field("bar", &true)
+                     .field("baz", &format_args!("{}/{}", 10, 20))
+                     .finish_non_exhaustive()
+             }
+         }
+ 
+         assert_eq!("Foo { bar: true, baz: 10/20, .. }", format!("{:?}", Foo));
+         assert_eq!(
+             "Foo {
+     bar: true,
+     baz: 10/20,
+     ..
+ }",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_nested_non_exhaustive() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Foo")
+                     .field("bar", &true)
+                     .field("baz", &format_args!("{}/{}", 10, 20))
+                     .finish_non_exhaustive()
+             }
+         }
+ 
+         struct Bar;
+ 
+         impl fmt::Debug for Bar {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_struct("Bar")
+                     .field("foo", &Foo)
+                     .field("hello", &"world")
+                     .finish_non_exhaustive()
+             }
+         }
+ 
+         assert_eq!(
+             "Bar { foo: Foo { bar: true, baz: 10/20, .. }, hello: \"world\", .. }",
+             format!("{:?}", Bar)
+         );
+         assert_eq!(
+             "Bar {
+     foo: Foo {
+         bar: true,
+         baz: 10/20,
+         ..
+     },
+     hello: \"world\",
+     ..
+ }",
+             format!("{:#?}", Bar)
+         );
+     }
+ }
+ 
+ mod debug_tuple {
+     use std::fmt;
+ 
+     #[test]
+     fn test_empty() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_tuple("Foo").finish()
+             }
+         }
+ 
+         assert_eq!("Foo", format!("{:?}", Foo));
+         assert_eq!("Foo", format!("{:#?}", Foo));
+     }
+ 
+     #[test]
+     fn test_single() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_tuple("Foo").field(&true).finish()
+             }
+         }
+ 
+         assert_eq!("Foo(true)", format!("{:?}", Foo));
+         assert_eq!(
+             "Foo(
+     true,
+ )",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_multiple() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_tuple("Foo").field(&true).field(&format_args!("{}/{}", 10, 20)).finish()
+             }
+         }
+ 
+         assert_eq!("Foo(true, 10/20)", format!("{:?}", Foo));
+         assert_eq!(
+             "Foo(
+     true,
+     10/20,
+ )",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_nested() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_tuple("Foo").field(&true).field(&format_args!("{}/{}", 10, 20)).finish()
+             }
+         }
+ 
+         struct Bar;
+ 
+         impl fmt::Debug for Bar {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_tuple("Bar").field(&Foo).field(&"world").finish()
+             }
+         }
+ 
+         assert_eq!("Bar(Foo(true, 10/20), \"world\")", format!("{:?}", Bar));
+         assert_eq!(
+             "Bar(
+     Foo(
+         true,
+         10/20,
+     ),
+     \"world\",
+ )",
+             format!("{:#?}", Bar)
+         );
+     }
+ }
+ 
+ mod debug_map {
+     use std::fmt;
+ 
+     #[test]
+     fn test_empty() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().finish()
+             }
+         }
+ 
+         assert_eq!("{}", format!("{:?}", Foo));
+         assert_eq!("{}", format!("{:#?}", Foo));
+     }
+ 
+     #[test]
+     fn test_single() {
+         struct Entry;
+ 
+         impl fmt::Debug for Entry {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().entry(&"bar", &true).finish()
+             }
+         }
+ 
+         struct KeyValue;
+ 
+         impl fmt::Debug for KeyValue {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().key(&"bar").value(&true).finish()
+             }
+         }
+ 
+         assert_eq!(format!("{:?}", Entry), format!("{:?}", KeyValue));
+         assert_eq!(format!("{:#?}", Entry), format!("{:#?}", KeyValue));
+ 
+         assert_eq!("{\"bar\": true}", format!("{:?}", Entry));
+         assert_eq!(
+             "{
+     \"bar\": true,
+ }",
+             format!("{:#?}", Entry)
+         );
+     }
+ 
+     #[test]
+     fn test_multiple() {
+         struct Entry;
+ 
+         impl fmt::Debug for Entry {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map()
+                     .entry(&"bar", &true)
+                     .entry(&10, &format_args!("{}/{}", 10, 20))
+                     .finish()
+             }
+         }
+ 
+         struct KeyValue;
+ 
+         impl fmt::Debug for KeyValue {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map()
+                     .key(&"bar")
+                     .value(&true)
+                     .key(&10)
+                     .value(&format_args!("{}/{}", 10, 20))
+                     .finish()
+             }
+         }
+ 
+         assert_eq!(format!("{:?}", Entry), format!("{:?}", KeyValue));
+         assert_eq!(format!("{:#?}", Entry), format!("{:#?}", KeyValue));
+ 
+         assert_eq!("{\"bar\": true, 10: 10/20}", format!("{:?}", Entry));
+         assert_eq!(
+             "{
+     \"bar\": true,
+     10: 10/20,
+ }",
+             format!("{:#?}", Entry)
+         );
+     }
+ 
+     #[test]
+     fn test_nested() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map()
+                     .entry(&"bar", &true)
+                     .entry(&10, &format_args!("{}/{}", 10, 20))
+                     .finish()
+             }
+         }
+ 
+         struct Bar;
+ 
+         impl fmt::Debug for Bar {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().entry(&"foo", &Foo).entry(&Foo, &"world").finish()
+             }
+         }
+ 
+         assert_eq!(
+             "{\"foo\": {\"bar\": true, 10: 10/20}, \
+                     {\"bar\": true, 10: 10/20}: \"world\"}",
+             format!("{:?}", Bar)
+         );
+         assert_eq!(
+             "{
+     \"foo\": {
+         \"bar\": true,
+         10: 10/20,
+     },
+     {
+         \"bar\": true,
+         10: 10/20,
+     }: \"world\",
+ }",
+             format!("{:#?}", Bar)
+         );
+     }
+ 
+     #[test]
+     fn test_entry_err() {
+         // Ensure errors in a map entry don't trigger panics (#65231)
+         use std::fmt::Write;
+ 
+         struct ErrorFmt;
+ 
+         impl fmt::Debug for ErrorFmt {
+             fn fmt(&self, _: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 Err(fmt::Error)
+             }
+         }
+ 
+         struct KeyValue<K, V>(usize, K, V);
+ 
+         impl<K, V> fmt::Debug for KeyValue<K, V>
+         where
+             K: fmt::Debug,
+             V: fmt::Debug,
+         {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 let mut map = fmt.debug_map();
+ 
+                 for _ in 0..self.0 {
+                     map.entry(&self.1, &self.2);
+                 }
+ 
+                 map.finish()
+             }
+         }
+ 
+         let mut buf = String::new();
+ 
+         assert!(write!(&mut buf, "{:?}", KeyValue(1, ErrorFmt, "bar")).is_err());
+         assert!(write!(&mut buf, "{:?}", KeyValue(1, "foo", ErrorFmt)).is_err());
+ 
+         assert!(write!(&mut buf, "{:?}", KeyValue(2, ErrorFmt, "bar")).is_err());
+         assert!(write!(&mut buf, "{:?}", KeyValue(2, "foo", ErrorFmt)).is_err());
+     }
+ 
+     #[test]
+     #[should_panic]
+     fn test_invalid_key_when_entry_is_incomplete() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().key(&"bar").key(&"invalid").finish()
+             }
+         }
+ 
+         format!("{:?}", Foo);
+     }
+ 
+     #[test]
+     #[should_panic]
+     fn test_invalid_finish_incomplete_entry() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().key(&"bar").finish()
+             }
+         }
+ 
+         format!("{:?}", Foo);
+     }
+ 
+     #[test]
+     #[should_panic]
+     fn test_invalid_value_before_key() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_map().value(&"invalid").key(&"bar").finish()
+             }
+         }
+ 
+         format!("{:?}", Foo);
+     }
+ }
+ 
+ mod debug_set {
+     use std::fmt;
+ 
+     #[test]
+     fn test_empty() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_set().finish()
+             }
+         }
+ 
+         assert_eq!("{}", format!("{:?}", Foo));
+         assert_eq!("{}", format!("{:#?}", Foo));
+     }
+ 
+     #[test]
+     fn test_single() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_set().entry(&true).finish()
+             }
+         }
+ 
+         assert_eq!("{true}", format!("{:?}", Foo));
+         assert_eq!(
+             "{
+     true,
+ }",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_multiple() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_set().entry(&true).entry(&format_args!("{}/{}", 10, 20)).finish()
+             }
+         }
+ 
+         assert_eq!("{true, 10/20}", format!("{:?}", Foo));
+         assert_eq!(
+             "{
+     true,
+     10/20,
+ }",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_nested() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_set().entry(&true).entry(&format_args!("{}/{}", 10, 20)).finish()
+             }
+         }
+ 
+         struct Bar;
+ 
+         impl fmt::Debug for Bar {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_set().entry(&Foo).entry(&"world").finish()
+             }
+         }
+ 
+         assert_eq!("{{true, 10/20}, \"world\"}", format!("{:?}", Bar));
+         assert_eq!(
+             "{
+     {
+         true,
+         10/20,
+     },
+     \"world\",
+ }",
+             format!("{:#?}", Bar)
+         );
+     }
+ }
+ 
+ mod debug_list {
+     use std::fmt;
+ 
+     #[test]
+     fn test_empty() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_list().finish()
+             }
+         }
+ 
+         assert_eq!("[]", format!("{:?}", Foo));
+         assert_eq!("[]", format!("{:#?}", Foo));
+     }
+ 
+     #[test]
+     fn test_single() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_list().entry(&true).finish()
+             }
+         }
+ 
+         assert_eq!("[true]", format!("{:?}", Foo));
+         assert_eq!(
+             "[
+     true,
+ ]",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_multiple() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_list().entry(&true).entry(&format_args!("{}/{}", 10, 20)).finish()
+             }
+         }
+ 
+         assert_eq!("[true, 10/20]", format!("{:?}", Foo));
+         assert_eq!(
+             "[
+     true,
+     10/20,
+ ]",
+             format!("{:#?}", Foo)
+         );
+     }
+ 
+     #[test]
+     fn test_nested() {
+         struct Foo;
+ 
+         impl fmt::Debug for Foo {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_list().entry(&true).entry(&format_args!("{}/{}", 10, 20)).finish()
+             }
+         }
+ 
+         struct Bar;
+ 
+         impl fmt::Debug for Bar {
+             fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
+                 fmt.debug_list().entry(&Foo).entry(&"world").finish()
+             }
+         }
+ 
+         assert_eq!("[[true, 10/20], \"world\"]", format!("{:?}", Bar));
+         assert_eq!(
+             "[
+     [
+         true,
+         10/20,
+     ],
+     \"world\",
+ ]",
+             format!("{:#?}", Bar)
+         );
+     }
+ }
+ 
+ #[test]
+ fn test_formatting_parameters_are_forwarded() {
+     use std::collections::{BTreeMap, BTreeSet};
+     #[derive(Debug)]
+     struct Foo {
+         bar: u32,
+         baz: u32,
+     }
+     let struct_ = Foo { bar: 1024, baz: 7 };
+     let tuple = (1024, 7);
+     let list = [1024, 7];
+     let mut map = BTreeMap::new();
+     map.insert("bar", 1024);
+     map.insert("baz", 7);
+     let mut set = BTreeSet::new();
+     set.insert(1024);
+     set.insert(7);
+ 
+     assert_eq!(format!("{:03?}", struct_), "Foo { bar: 1024, baz: 007 }");
+     assert_eq!(format!("{:03?}", tuple), "(1024, 007)");
+     assert_eq!(format!("{:03?}", list), "[1024, 007]");
+     assert_eq!(format!("{:03?}", map), r#"{"bar": 1024, "baz": 007}"#);
+     assert_eq!(format!("{:03?}", set), "{007, 1024}");
+     assert_eq!(
+         format!("{:#03?}", struct_),
+         "
+ Foo {
+     bar: 1024,
+     baz: 007,
+ }
+     "
+         .trim()
+     );
+     assert_eq!(
+         format!("{:#03?}", tuple),
+         "
+ (
+     1024,
+     007,
+ )
+     "
+         .trim()
+     );
+     assert_eq!(
+         format!("{:#03?}", list),
+         "
+ [
+     1024,
+     007,
+ ]
+     "
+         .trim()
+     );
+     assert_eq!(
+         format!("{:#03?}", map),
+         r#"
+ {
+     "bar": 1024,
+     "baz": 007,
+ }
+     "#
+         .trim()
+     );
+     assert_eq!(
+         format!("{:#03?}", set),
+         "
+ {
+     007,
+     1024,
+ }
+     "
+         .trim()
+     );
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/float.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/float.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/float.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/float.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,31 ----
+ #[test]
+ fn test_format_f64() {
+     assert_eq!("1", format!("{:.0}", 1.0f64));
+     assert_eq!("9", format!("{:.0}", 9.4f64));
+     assert_eq!("10", format!("{:.0}", 9.9f64));
+     assert_eq!("9.8", format!("{:.1}", 9.849f64));
+     assert_eq!("9.9", format!("{:.1}", 9.851f64));
+     assert_eq!("1", format!("{:.0}", 0.5f64));
+     assert_eq!("1.23456789e6", format!("{:e}", 1234567.89f64));
+     assert_eq!("1.23456789e3", format!("{:e}", 1234.56789f64));
+     assert_eq!("1.23456789E6", format!("{:E}", 1234567.89f64));
+     assert_eq!("1.23456789E3", format!("{:E}", 1234.56789f64));
+     assert_eq!("0.0", format!("{:?}", 0.0f64));
+     assert_eq!("1.01", format!("{:?}", 1.01f64));
+ }
+ 
+ #[test]
+ fn test_format_f32() {
+     assert_eq!("1", format!("{:.0}", 1.0f32));
+     assert_eq!("9", format!("{:.0}", 9.4f32));
+     assert_eq!("10", format!("{:.0}", 9.9f32));
+     assert_eq!("9.8", format!("{:.1}", 9.849f32));
+     assert_eq!("9.9", format!("{:.1}", 9.851f32));
+     assert_eq!("1", format!("{:.0}", 0.5f32));
+     assert_eq!("1.2345679e6", format!("{:e}", 1234567.89f32));
+     assert_eq!("1.2345679e3", format!("{:e}", 1234.56789f32));
+     assert_eq!("1.2345679E6", format!("{:E}", 1234567.89f32));
+     assert_eq!("1.2345679E3", format!("{:E}", 1234.56789f32));
+     assert_eq!("0.0", format!("{:?}", 0.0f32));
+     assert_eq!("1.01", format!("{:?}", 1.01f32));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,45 ----
+ mod builders;
+ mod float;
+ mod num;
+ 
+ #[test]
+ fn test_format_flags() {
+     // No residual flags left by pointer formatting
+     let p = "".as_ptr();
+     assert_eq!(format!("{:p} {:x}", p, 16), format!("{:p} 10", p));
+ 
+     assert_eq!(format!("{: >3}", 'a'), "  a");
+ }
+ 
+ #[test]
+ fn test_pointer_formats_data_pointer() {
+     let b: &[u8] = b"";
+     let s: &str = "";
+     assert_eq!(format!("{:p}", s), format!("{:p}", s.as_ptr()));
+     assert_eq!(format!("{:p}", b), format!("{:p}", b.as_ptr()));
+ }
+ 
+ #[test]
+ fn test_estimated_capacity() {
+     assert_eq!(format_args!("").estimated_capacity(), 0);
+     assert_eq!(format_args!("{}", "").estimated_capacity(), 0);
+     assert_eq!(format_args!("Hello").estimated_capacity(), 5);
+     assert_eq!(format_args!("Hello, {}!", "").estimated_capacity(), 16);
+     assert_eq!(format_args!("{}, hello!", "World").estimated_capacity(), 0);
+     assert_eq!(format_args!("{}. 16-bytes piece", "World").estimated_capacity(), 32);
+ }
+ 
+ #[test]
+ fn pad_integral_resets() {
+     struct Bar;
+ 
+     impl core::fmt::Display for Bar {
+         fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+             "1".fmt(f)?;
+             f.pad_integral(true, "", "5")?;
+             "1".fmt(f)
+         }
+     }
+ 
+     assert_eq!(format!("{:<03}", Bar), "1  0051  ");
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/num.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/num.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/fmt/num.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/fmt/num.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,224 ----
+ #[test]
+ fn test_format_int() {
+     // Formatting integers should select the right implementation based off
+     // the type of the argument. Also, hex/octal/binary should be defined
+     // for integers, but they shouldn't emit the negative sign.
+     assert_eq!(format!("{}", 1isize), "1");
+     assert_eq!(format!("{}", 1i8), "1");
+     assert_eq!(format!("{}", 1i16), "1");
+     assert_eq!(format!("{}", 1i32), "1");
+     assert_eq!(format!("{}", 1i64), "1");
+     assert_eq!(format!("{}", -1isize), "-1");
+     assert_eq!(format!("{}", -1i8), "-1");
+     assert_eq!(format!("{}", -1i16), "-1");
+     assert_eq!(format!("{}", -1i32), "-1");
+     assert_eq!(format!("{}", -1i64), "-1");
+     assert_eq!(format!("{:?}", 1isize), "1");
+     assert_eq!(format!("{:?}", 1i8), "1");
+     assert_eq!(format!("{:?}", 1i16), "1");
+     assert_eq!(format!("{:?}", 1i32), "1");
+     assert_eq!(format!("{:?}", 1i64), "1");
+     assert_eq!(format!("{:b}", 1isize), "1");
+     assert_eq!(format!("{:b}", 1i8), "1");
+     assert_eq!(format!("{:b}", 1i16), "1");
+     assert_eq!(format!("{:b}", 1i32), "1");
+     assert_eq!(format!("{:b}", 1i64), "1");
+     assert_eq!(format!("{:x}", 1isize), "1");
+     assert_eq!(format!("{:x}", 1i8), "1");
+     assert_eq!(format!("{:x}", 1i16), "1");
+     assert_eq!(format!("{:x}", 1i32), "1");
+     assert_eq!(format!("{:x}", 1i64), "1");
+     assert_eq!(format!("{:X}", 1isize), "1");
+     assert_eq!(format!("{:X}", 1i8), "1");
+     assert_eq!(format!("{:X}", 1i16), "1");
+     assert_eq!(format!("{:X}", 1i32), "1");
+     assert_eq!(format!("{:X}", 1i64), "1");
+     assert_eq!(format!("{:o}", 1isize), "1");
+     assert_eq!(format!("{:o}", 1i8), "1");
+     assert_eq!(format!("{:o}", 1i16), "1");
+     assert_eq!(format!("{:o}", 1i32), "1");
+     assert_eq!(format!("{:o}", 1i64), "1");
+     assert_eq!(format!("{:e}", 1isize), "1e0");
+     assert_eq!(format!("{:e}", 1i8), "1e0");
+     assert_eq!(format!("{:e}", 1i16), "1e0");
+     assert_eq!(format!("{:e}", 1i32), "1e0");
+     assert_eq!(format!("{:e}", 1i64), "1e0");
+     assert_eq!(format!("{:E}", 1isize), "1E0");
+     assert_eq!(format!("{:E}", 1i8), "1E0");
+     assert_eq!(format!("{:E}", 1i16), "1E0");
+     assert_eq!(format!("{:E}", 1i32), "1E0");
+     assert_eq!(format!("{:E}", 1i64), "1E0");
+ 
+     assert_eq!(format!("{}", 1usize), "1");
+     assert_eq!(format!("{}", 1u8), "1");
+     assert_eq!(format!("{}", 1u16), "1");
+     assert_eq!(format!("{}", 1u32), "1");
+     assert_eq!(format!("{}", 1u64), "1");
+     assert_eq!(format!("{:?}", 1usize), "1");
+     assert_eq!(format!("{:?}", 1u8), "1");
+     assert_eq!(format!("{:?}", 1u16), "1");
+     assert_eq!(format!("{:?}", 1u32), "1");
+     assert_eq!(format!("{:?}", 1u64), "1");
+     assert_eq!(format!("{:b}", 1usize), "1");
+     assert_eq!(format!("{:b}", 1u8), "1");
+     assert_eq!(format!("{:b}", 1u16), "1");
+     assert_eq!(format!("{:b}", 1u32), "1");
+     assert_eq!(format!("{:b}", 1u64), "1");
+     assert_eq!(format!("{:x}", 1usize), "1");
+     assert_eq!(format!("{:x}", 1u8), "1");
+     assert_eq!(format!("{:x}", 1u16), "1");
+     assert_eq!(format!("{:x}", 1u32), "1");
+     assert_eq!(format!("{:x}", 1u64), "1");
+     assert_eq!(format!("{:X}", 1usize), "1");
+     assert_eq!(format!("{:X}", 1u8), "1");
+     assert_eq!(format!("{:X}", 1u16), "1");
+     assert_eq!(format!("{:X}", 1u32), "1");
+     assert_eq!(format!("{:X}", 1u64), "1");
+     assert_eq!(format!("{:o}", 1usize), "1");
+     assert_eq!(format!("{:o}", 1u8), "1");
+     assert_eq!(format!("{:o}", 1u16), "1");
+     assert_eq!(format!("{:o}", 1u32), "1");
+     assert_eq!(format!("{:o}", 1u64), "1");
+     assert_eq!(format!("{:e}", 1u8), "1e0");
+     assert_eq!(format!("{:e}", 1u16), "1e0");
+     assert_eq!(format!("{:e}", 1u32), "1e0");
+     assert_eq!(format!("{:e}", 1u64), "1e0");
+     assert_eq!(format!("{:E}", 1u8), "1E0");
+     assert_eq!(format!("{:E}", 1u16), "1E0");
+     assert_eq!(format!("{:E}", 1u32), "1E0");
+     assert_eq!(format!("{:E}", 1u64), "1E0");
+ 
+     // Test a larger number
+     assert_eq!(format!("{:b}", 55), "110111");
+     assert_eq!(format!("{:o}", 55), "67");
+     assert_eq!(format!("{}", 55), "55");
+     assert_eq!(format!("{:x}", 55), "37");
+     assert_eq!(format!("{:X}", 55), "37");
+     assert_eq!(format!("{:e}", 55), "5.5e1");
+     assert_eq!(format!("{:E}", 55), "5.5E1");
+     assert_eq!(format!("{:e}", 10000000000u64), "1e10");
+     assert_eq!(format!("{:E}", 10000000000u64), "1E10");
+     assert_eq!(format!("{:e}", 10000000001u64), "1.0000000001e10");
+     assert_eq!(format!("{:E}", 10000000001u64), "1.0000000001E10");
+ }
+ 
+ #[test]
+ fn test_format_int_exp_limits() {
+     assert_eq!(format!("{:e}", i8::MIN), "-1.28e2");
+     assert_eq!(format!("{:e}", i8::MAX), "1.27e2");
+     assert_eq!(format!("{:e}", i16::MIN), "-3.2768e4");
+     assert_eq!(format!("{:e}", i16::MAX), "3.2767e4");
+     assert_eq!(format!("{:e}", i32::MIN), "-2.147483648e9");
+     assert_eq!(format!("{:e}", i32::MAX), "2.147483647e9");
+     assert_eq!(format!("{:e}", i64::MIN), "-9.223372036854775808e18");
+     assert_eq!(format!("{:e}", i64::MAX), "9.223372036854775807e18");
+     assert_eq!(format!("{:e}", i128::MIN), "-1.70141183460469231731687303715884105728e38");
+     assert_eq!(format!("{:e}", i128::MAX), "1.70141183460469231731687303715884105727e38");
+ 
+     assert_eq!(format!("{:e}", u8::MAX), "2.55e2");
+     assert_eq!(format!("{:e}", u16::MAX), "6.5535e4");
+     assert_eq!(format!("{:e}", u32::MAX), "4.294967295e9");
+     assert_eq!(format!("{:e}", u64::MAX), "1.8446744073709551615e19");
+     assert_eq!(format!("{:e}", u128::MAX), "3.40282366920938463463374607431768211455e38");
+ }
+ 
+ #[test]
+ fn test_format_int_exp_precision() {
+     //test that float and integer match
+     let big_int: u32 = 314_159_265;
+     assert_eq!(format!("{:.1e}", big_int), format!("{:.1e}", f64::from(big_int)));
+ 
+     //test adding precision
+     assert_eq!(format!("{:.10e}", i8::MIN), "-1.2800000000e2");
+     assert_eq!(format!("{:.10e}", i16::MIN), "-3.2768000000e4");
+     assert_eq!(format!("{:.10e}", i32::MIN), "-2.1474836480e9");
+     assert_eq!(format!("{:.20e}", i64::MIN), "-9.22337203685477580800e18");
+     assert_eq!(format!("{:.40e}", i128::MIN), "-1.7014118346046923173168730371588410572800e38");
+ 
+     //test rounding
+     assert_eq!(format!("{:.1e}", i8::MIN), "-1.3e2");
+     assert_eq!(format!("{:.1e}", i16::MIN), "-3.3e4");
+     assert_eq!(format!("{:.1e}", i32::MIN), "-2.1e9");
+     assert_eq!(format!("{:.1e}", i64::MIN), "-9.2e18");
+     assert_eq!(format!("{:.1e}", i128::MIN), "-1.7e38");
+ 
+     //test huge precision
+     assert_eq!(format!("{:.1000e}", 1), format!("1.{}e0", "0".repeat(1000)));
+     //test zero precision
+     assert_eq!(format!("{:.0e}", 1), format!("1e0",));
+ 
+     //test padding with precision (and sign)
+     assert_eq!(format!("{:+10.3e}", 1), "  +1.000e0");
+ }
+ 
+ #[test]
+ fn test_format_int_zero() {
+     assert_eq!(format!("{}", 0), "0");
+     assert_eq!(format!("{:?}", 0), "0");
+     assert_eq!(format!("{:b}", 0), "0");
+     assert_eq!(format!("{:o}", 0), "0");
+     assert_eq!(format!("{:x}", 0), "0");
+     assert_eq!(format!("{:X}", 0), "0");
+     assert_eq!(format!("{:e}", 0), "0e0");
+     assert_eq!(format!("{:E}", 0), "0E0");
+ 
+     assert_eq!(format!("{}", 0u32), "0");
+     assert_eq!(format!("{:?}", 0u32), "0");
+     assert_eq!(format!("{:b}", 0u32), "0");
+     assert_eq!(format!("{:o}", 0u32), "0");
+     assert_eq!(format!("{:x}", 0u32), "0");
+     assert_eq!(format!("{:X}", 0u32), "0");
+     assert_eq!(format!("{:e}", 0u32), "0e0");
+     assert_eq!(format!("{:E}", 0u32), "0E0");
+ }
+ 
+ #[test]
+ fn test_format_int_flags() {
+     assert_eq!(format!("{:3}", 1), "  1");
+     assert_eq!(format!("{:>3}", 1), "  1");
+     assert_eq!(format!("{:>+3}", 1), " +1");
+     assert_eq!(format!("{:<3}", 1), "1  ");
+     assert_eq!(format!("{:#}", 1), "1");
+     assert_eq!(format!("{:#x}", 10), "0xa");
+     assert_eq!(format!("{:#X}", 10), "0xA");
+     assert_eq!(format!("{:#5x}", 10), "  0xa");
+     assert_eq!(format!("{:#o}", 10), "0o12");
+     assert_eq!(format!("{:08x}", 10), "0000000a");
+     assert_eq!(format!("{:8x}", 10), "       a");
+     assert_eq!(format!("{:<8x}", 10), "a       ");
+     assert_eq!(format!("{:>8x}", 10), "       a");
+     assert_eq!(format!("{:#08x}", 10), "0x00000a");
+     assert_eq!(format!("{:08}", -10), "-0000010");
+     assert_eq!(format!("{:x}", !0u8), "ff");
+     assert_eq!(format!("{:X}", !0u8), "FF");
+     assert_eq!(format!("{:b}", !0u8), "11111111");
+     assert_eq!(format!("{:o}", !0u8), "377");
+     assert_eq!(format!("{:#x}", !0u8), "0xff");
+     assert_eq!(format!("{:#X}", !0u8), "0xFF");
+     assert_eq!(format!("{:#b}", !0u8), "0b11111111");
+     assert_eq!(format!("{:#o}", !0u8), "0o377");
+ }
+ 
+ #[test]
+ fn test_format_int_sign_padding() {
+     assert_eq!(format!("{:+5}", 1), "   +1");
+     assert_eq!(format!("{:+5}", -1), "   -1");
+     assert_eq!(format!("{:05}", 1), "00001");
+     assert_eq!(format!("{:05}", -1), "-0001");
+     assert_eq!(format!("{:+05}", 1), "+0001");
+     assert_eq!(format!("{:+05}", -1), "-0001");
+ }
+ 
+ #[test]
+ fn test_format_int_twos_complement() {
+     assert_eq!(format!("{}", i8::MIN), "-128");
+     assert_eq!(format!("{}", i16::MIN), "-32768");
+     assert_eq!(format!("{}", i32::MIN), "-2147483648");
+     assert_eq!(format!("{}", i64::MIN), "-9223372036854775808");
+ }
+ 
+ #[test]
+ fn test_format_debug_hex() {
+     assert_eq!(format!("{:02x?}", b"Foo\0"), "[46, 6f, 6f, 00]");
+     assert_eq!(format!("{:02X?}", b"Foo\0"), "[46, 6F, 6F, 00]");
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/hash/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/hash/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/hash/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/hash/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,141 ----
+ mod sip;
+ 
+ use std::default::Default;
+ use std::hash::{Hash, Hasher};
+ use std::rc::Rc;
+ 
+ struct MyHasher {
+     hash: u64,
+ }
+ 
+ impl Default for MyHasher {
+     fn default() -> MyHasher {
+         MyHasher { hash: 0 }
+     }
+ }
+ 
+ impl Hasher for MyHasher {
+     fn write(&mut self, buf: &[u8]) {
+         for byte in buf {
+             self.hash += *byte as u64;
+         }
+     }
+     fn finish(&self) -> u64 {
+         self.hash
+     }
+ }
+ 
+ #[test]
+ fn test_writer_hasher() {
+     fn hash<T: Hash>(t: &T) -> u64 {
+         let mut s = MyHasher { hash: 0 };
+         t.hash(&mut s);
+         s.finish()
+     }
+ 
+     assert_eq!(hash(&()), 0);
+ 
+     assert_eq!(hash(&5_u8), 5);
+     assert_eq!(hash(&5_u16), 5);
+     assert_eq!(hash(&5_u32), 5);
+     assert_eq!(hash(&5_u64), 5);
+     assert_eq!(hash(&5_usize), 5);
+ 
+     assert_eq!(hash(&5_i8), 5);
+     assert_eq!(hash(&5_i16), 5);
+     assert_eq!(hash(&5_i32), 5);
+     assert_eq!(hash(&5_i64), 5);
+     assert_eq!(hash(&5_isize), 5);
+ 
+     assert_eq!(hash(&false), 0);
+     assert_eq!(hash(&true), 1);
+ 
+     assert_eq!(hash(&'a'), 97);
+ 
+     let s: &str = "a";
+     assert_eq!(hash(&s), 97 + 0xFF);
+     let s: Box<str> = String::from("a").into_boxed_str();
+     assert_eq!(hash(&s), 97 + 0xFF);
+     let s: Rc<&str> = Rc::new("a");
+     assert_eq!(hash(&s), 97 + 0xFF);
+     let cs: &[u8] = &[1, 2, 3];
+     assert_eq!(hash(&cs), 9);
+     let cs: Box<[u8]> = Box::new([1, 2, 3]);
+     assert_eq!(hash(&cs), 9);
+     let cs: Rc<[u8]> = Rc::new([1, 2, 3]);
+     assert_eq!(hash(&cs), 9);
+ 
+     let ptr = 5_usize as *const i32;
+     assert_eq!(hash(&ptr), 5);
+ 
+     let ptr = 5_usize as *mut i32;
+     assert_eq!(hash(&ptr), 5);
+ 
+     if cfg!(miri) {
+         // Miri cannot hash pointers
+         return;
+     }
+ 
+     let cs: &mut [u8] = &mut [1, 2, 3];
+     let ptr = cs.as_ptr();
+     let slice_ptr = cs as *const [u8];
+     assert_eq!(hash(&slice_ptr), hash(&ptr) + cs.len() as u64);
+ 
+     let slice_ptr = cs as *mut [u8];
+     assert_eq!(hash(&slice_ptr), hash(&ptr) + cs.len() as u64);
+ }
+ 
+ struct Custom {
+     hash: u64,
+ }
+ struct CustomHasher {
+     output: u64,
+ }
+ 
+ impl Hasher for CustomHasher {
+     fn finish(&self) -> u64 {
+         self.output
+     }
+     fn write(&mut self, _: &[u8]) {
+         panic!()
+     }
+     fn write_u64(&mut self, data: u64) {
+         self.output = data;
+     }
+ }
+ 
+ impl Default for CustomHasher {
+     fn default() -> CustomHasher {
+         CustomHasher { output: 0 }
+     }
+ }
+ 
+ impl Hash for Custom {
+     fn hash<H: Hasher>(&self, state: &mut H) {
+         state.write_u64(self.hash);
+     }
+ }
+ 
+ #[test]
+ fn test_custom_state() {
+     fn hash<T: Hash>(t: &T) -> u64 {
+         let mut c = CustomHasher { output: 0 };
+         t.hash(&mut c);
+         c.finish()
+     }
+ 
+     assert_eq!(hash(&Custom { hash: 5 }), 5);
+ }
+ 
+ // FIXME: Instantiated functions with i128 in the signature is not supported in Emscripten.
+ // See https://github.com/kripken/emscripten-fastcomp/issues/169
+ #[cfg(not(target_os = "emscripten"))]
+ #[test]
+ fn test_indirect_hasher() {
+     let mut hasher = MyHasher { hash: 0 };
+     {
+         let mut indirect_hasher: &mut dyn Hasher = &mut hasher;
+         5u32.hash(&mut indirect_hasher);
+     }
+     assert_eq!(hasher.hash, 5);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/hash/sip.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/hash/sip.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/hash/sip.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/hash/sip.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,331 ----
+ #![allow(deprecated)]
+ 
+ use core::hash::{Hash, Hasher};
+ use core::hash::{SipHasher, SipHasher13};
+ use core::{mem, slice};
+ 
+ // Hash just the bytes of the slice, without length prefix
+ struct Bytes<'a>(&'a [u8]);
+ 
+ impl<'a> Hash for Bytes<'a> {
+     #[allow(unused_must_use)]
+     fn hash<H: Hasher>(&self, state: &mut H) {
+         let Bytes(v) = *self;
+         state.write(v);
+     }
+ }
+ 
+ macro_rules! u8to64_le {
+     ($buf:expr, $i:expr) => {
+         $buf[0 + $i] as u64
+             | ($buf[1 + $i] as u64) << 8
+             | ($buf[2 + $i] as u64) << 16
+             | ($buf[3 + $i] as u64) << 24
+             | ($buf[4 + $i] as u64) << 32
+             | ($buf[5 + $i] as u64) << 40
+             | ($buf[6 + $i] as u64) << 48
+             | ($buf[7 + $i] as u64) << 56
+     };
+     ($buf:expr, $i:expr, $len:expr) => {{
+         let mut t = 0;
+         let mut out = 0;
+         while t < $len {
+             out |= ($buf[t + $i] as u64) << t * 8;
+             t += 1;
+         }
+         out
+     }};
+ }
+ 
+ fn hash_with<H: Hasher, T: Hash>(mut st: H, x: &T) -> u64 {
+     x.hash(&mut st);
+     st.finish()
+ }
+ 
+ fn hash<T: Hash>(x: &T) -> u64 {
+     hash_with(SipHasher::new(), x)
+ }
+ 
+ #[test]
+ #[allow(unused_must_use)]
+ fn test_siphash_1_3() {
+     let vecs: [[u8; 8]; 64] = [
+         [0xdc, 0xc4, 0x0f, 0x05, 0x58, 0x01, 0xac, 0xab],
+         [0x93, 0xca, 0x57, 0x7d, 0xf3, 0x9b, 0xf4, 0xc9],
+         [0x4d, 0xd4, 0xc7, 0x4d, 0x02, 0x9b, 0xcb, 0x82],
+         [0xfb, 0xf7, 0xdd, 0xe7, 0xb8, 0x0a, 0xf8, 0x8b],
+         [0x28, 0x83, 0xd3, 0x88, 0x60, 0x57, 0x75, 0xcf],
+         [0x67, 0x3b, 0x53, 0x49, 0x2f, 0xd5, 0xf9, 0xde],
+         [0xa7, 0x22, 0x9f, 0xc5, 0x50, 0x2b, 0x0d, 0xc5],
+         [0x40, 0x11, 0xb1, 0x9b, 0x98, 0x7d, 0x92, 0xd3],
+         [0x8e, 0x9a, 0x29, 0x8d, 0x11, 0x95, 0x90, 0x36],
+         [0xe4, 0x3d, 0x06, 0x6c, 0xb3, 0x8e, 0xa4, 0x25],
+         [0x7f, 0x09, 0xff, 0x92, 0xee, 0x85, 0xde, 0x79],
+         [0x52, 0xc3, 0x4d, 0xf9, 0xc1, 0x18, 0xc1, 0x70],
+         [0xa2, 0xd9, 0xb4, 0x57, 0xb1, 0x84, 0xa3, 0x78],
+         [0xa7, 0xff, 0x29, 0x12, 0x0c, 0x76, 0x6f, 0x30],
+         [0x34, 0x5d, 0xf9, 0xc0, 0x11, 0xa1, 0x5a, 0x60],
+         [0x56, 0x99, 0x51, 0x2a, 0x6d, 0xd8, 0x20, 0xd3],
+         [0x66, 0x8b, 0x90, 0x7d, 0x1a, 0xdd, 0x4f, 0xcc],
+         [0x0c, 0xd8, 0xdb, 0x63, 0x90, 0x68, 0xf2, 0x9c],
+         [0x3e, 0xe6, 0x73, 0xb4, 0x9c, 0x38, 0xfc, 0x8f],
+         [0x1c, 0x7d, 0x29, 0x8d, 0xe5, 0x9d, 0x1f, 0xf2],
+         [0x40, 0xe0, 0xcc, 0xa6, 0x46, 0x2f, 0xdc, 0xc0],
+         [0x44, 0xf8, 0x45, 0x2b, 0xfe, 0xab, 0x92, 0xb9],
+         [0x2e, 0x87, 0x20, 0xa3, 0x9b, 0x7b, 0xfe, 0x7f],
+         [0x23, 0xc1, 0xe6, 0xda, 0x7f, 0x0e, 0x5a, 0x52],
+         [0x8c, 0x9c, 0x34, 0x67, 0xb2, 0xae, 0x64, 0xf4],
+         [0x79, 0x09, 0x5b, 0x70, 0x28, 0x59, 0xcd, 0x45],
+         [0xa5, 0x13, 0x99, 0xca, 0xe3, 0x35, 0x3e, 0x3a],
+         [0x35, 0x3b, 0xde, 0x4a, 0x4e, 0xc7, 0x1d, 0xa9],
+         [0x0d, 0xd0, 0x6c, 0xef, 0x02, 0xed, 0x0b, 0xfb],
+         [0xf4, 0xe1, 0xb1, 0x4a, 0xb4, 0x3c, 0xd9, 0x88],
+         [0x63, 0xe6, 0xc5, 0x43, 0xd6, 0x11, 0x0f, 0x54],
+         [0xbc, 0xd1, 0x21, 0x8c, 0x1f, 0xdd, 0x70, 0x23],
+         [0x0d, 0xb6, 0xa7, 0x16, 0x6c, 0x7b, 0x15, 0x81],
+         [0xbf, 0xf9, 0x8f, 0x7a, 0xe5, 0xb9, 0x54, 0x4d],
+         [0x3e, 0x75, 0x2a, 0x1f, 0x78, 0x12, 0x9f, 0x75],
+         [0x91, 0x6b, 0x18, 0xbf, 0xbe, 0xa3, 0xa1, 0xce],
+         [0x06, 0x62, 0xa2, 0xad, 0xd3, 0x08, 0xf5, 0x2c],
+         [0x57, 0x30, 0xc3, 0xa3, 0x2d, 0x1c, 0x10, 0xb6],
+         [0xa1, 0x36, 0x3a, 0xae, 0x96, 0x74, 0xf4, 0xb3],
+         [0x92, 0x83, 0x10, 0x7b, 0x54, 0x57, 0x6b, 0x62],
+         [0x31, 0x15, 0xe4, 0x99, 0x32, 0x36, 0xd2, 0xc1],
+         [0x44, 0xd9, 0x1a, 0x3f, 0x92, 0xc1, 0x7c, 0x66],
+         [0x25, 0x88, 0x13, 0xc8, 0xfe, 0x4f, 0x70, 0x65],
+         [0xa6, 0x49, 0x89, 0xc2, 0xd1, 0x80, 0xf2, 0x24],
+         [0x6b, 0x87, 0xf8, 0xfa, 0xed, 0x1c, 0xca, 0xc2],
+         [0x96, 0x21, 0x04, 0x9f, 0xfc, 0x4b, 0x16, 0xc2],
+         [0x23, 0xd6, 0xb1, 0x68, 0x93, 0x9c, 0x6e, 0xa1],
+         [0xfd, 0x14, 0x51, 0x8b, 0x9c, 0x16, 0xfb, 0x49],
+         [0x46, 0x4c, 0x07, 0xdf, 0xf8, 0x43, 0x31, 0x9f],
+         [0xb3, 0x86, 0xcc, 0x12, 0x24, 0xaf, 0xfd, 0xc6],
+         [0x8f, 0x09, 0x52, 0x0a, 0xd1, 0x49, 0xaf, 0x7e],
+         [0x9a, 0x2f, 0x29, 0x9d, 0x55, 0x13, 0xf3, 0x1c],
+         [0x12, 0x1f, 0xf4, 0xa2, 0xdd, 0x30, 0x4a, 0xc4],
+         [0xd0, 0x1e, 0xa7, 0x43, 0x89, 0xe9, 0xfa, 0x36],
+         [0xe6, 0xbc, 0xf0, 0x73, 0x4c, 0xb3, 0x8f, 0x31],
+         [0x80, 0xe9, 0xa7, 0x70, 0x36, 0xbf, 0x7a, 0xa2],
+         [0x75, 0x6d, 0x3c, 0x24, 0xdb, 0xc0, 0xbc, 0xb4],
+         [0x13, 0x15, 0xb7, 0xfd, 0x52, 0xd8, 0xf8, 0x23],
+         [0x08, 0x8a, 0x7d, 0xa6, 0x4d, 0x5f, 0x03, 0x8f],
+         [0x48, 0xf1, 0xe8, 0xb7, 0xe5, 0xd0, 0x9c, 0xd8],
+         [0xee, 0x44, 0xa6, 0xf7, 0xbc, 0xe6, 0xf4, 0xf6],
+         [0xf2, 0x37, 0x18, 0x0f, 0xd8, 0x9a, 0xc5, 0xae],
+         [0xe0, 0x94, 0x66, 0x4b, 0x15, 0xf6, 0xb2, 0xc3],
+         [0xa8, 0xb3, 0xbb, 0xb7, 0x62, 0x90, 0x19, 0x9d],
+     ];
+ 
+     let k0 = 0x_07_06_05_04_03_02_01_00;
+     let k1 = 0x_0f_0e_0d_0c_0b_0a_09_08;
+     let mut buf = Vec::new();
+     let mut t = 0;
+     let mut state_inc = SipHasher13::new_with_keys(k0, k1);
+ 
+     while t < 64 {
+         let vec = u8to64_le!(vecs[t], 0);
+         let out = hash_with(SipHasher13::new_with_keys(k0, k1), &Bytes(&buf));
+         assert_eq!(vec, out);
+ 
+         let full = hash_with(SipHasher13::new_with_keys(k0, k1), &Bytes(&buf));
+         let i = state_inc.finish();
+ 
+         assert_eq!(full, i);
+         assert_eq!(full, vec);
+ 
+         buf.push(t as u8);
+         Hasher::write(&mut state_inc, &[t as u8]);
+ 
+         t += 1;
+     }
+ }
+ 
+ #[test]
+ #[allow(unused_must_use)]
+ fn test_siphash_2_4() {
+     let vecs: [[u8; 8]; 64] = [
+         [0x31, 0x0e, 0x0e, 0xdd, 0x47, 0xdb, 0x6f, 0x72],
+         [0xfd, 0x67, 0xdc, 0x93, 0xc5, 0x39, 0xf8, 0x74],
+         [0x5a, 0x4f, 0xa9, 0xd9, 0x09, 0x80, 0x6c, 0x0d],
+         [0x2d, 0x7e, 0xfb, 0xd7, 0x96, 0x66, 0x67, 0x85],
+         [0xb7, 0x87, 0x71, 0x27, 0xe0, 0x94, 0x27, 0xcf],
+         [0x8d, 0xa6, 0x99, 0xcd, 0x64, 0x55, 0x76, 0x18],
+         [0xce, 0xe3, 0xfe, 0x58, 0x6e, 0x46, 0xc9, 0xcb],
+         [0x37, 0xd1, 0x01, 0x8b, 0xf5, 0x00, 0x02, 0xab],
+         [0x62, 0x24, 0x93, 0x9a, 0x79, 0xf5, 0xf5, 0x93],
+         [0xb0, 0xe4, 0xa9, 0x0b, 0xdf, 0x82, 0x00, 0x9e],
+         [0xf3, 0xb9, 0xdd, 0x94, 0xc5, 0xbb, 0x5d, 0x7a],
+         [0xa7, 0xad, 0x6b, 0x22, 0x46, 0x2f, 0xb3, 0xf4],
+         [0xfb, 0xe5, 0x0e, 0x86, 0xbc, 0x8f, 0x1e, 0x75],
+         [0x90, 0x3d, 0x84, 0xc0, 0x27, 0x56, 0xea, 0x14],
+         [0xee, 0xf2, 0x7a, 0x8e, 0x90, 0xca, 0x23, 0xf7],
+         [0xe5, 0x45, 0xbe, 0x49, 0x61, 0xca, 0x29, 0xa1],
+         [0xdb, 0x9b, 0xc2, 0x57, 0x7f, 0xcc, 0x2a, 0x3f],
+         [0x94, 0x47, 0xbe, 0x2c, 0xf5, 0xe9, 0x9a, 0x69],
+         [0x9c, 0xd3, 0x8d, 0x96, 0xf0, 0xb3, 0xc1, 0x4b],
+         [0xbd, 0x61, 0x79, 0xa7, 0x1d, 0xc9, 0x6d, 0xbb],
+         [0x98, 0xee, 0xa2, 0x1a, 0xf2, 0x5c, 0xd6, 0xbe],
+         [0xc7, 0x67, 0x3b, 0x2e, 0xb0, 0xcb, 0xf2, 0xd0],
+         [0x88, 0x3e, 0xa3, 0xe3, 0x95, 0x67, 0x53, 0x93],
+         [0xc8, 0xce, 0x5c, 0xcd, 0x8c, 0x03, 0x0c, 0xa8],
+         [0x94, 0xaf, 0x49, 0xf6, 0xc6, 0x50, 0xad, 0xb8],
+         [0xea, 0xb8, 0x85, 0x8a, 0xde, 0x92, 0xe1, 0xbc],
+         [0xf3, 0x15, 0xbb, 0x5b, 0xb8, 0x35, 0xd8, 0x17],
+         [0xad, 0xcf, 0x6b, 0x07, 0x63, 0x61, 0x2e, 0x2f],
+         [0xa5, 0xc9, 0x1d, 0xa7, 0xac, 0xaa, 0x4d, 0xde],
+         [0x71, 0x65, 0x95, 0x87, 0x66, 0x50, 0xa2, 0xa6],
+         [0x28, 0xef, 0x49, 0x5c, 0x53, 0xa3, 0x87, 0xad],
+         [0x42, 0xc3, 0x41, 0xd8, 0xfa, 0x92, 0xd8, 0x32],
+         [0xce, 0x7c, 0xf2, 0x72, 0x2f, 0x51, 0x27, 0x71],
+         [0xe3, 0x78, 0x59, 0xf9, 0x46, 0x23, 0xf3, 0xa7],
+         [0x38, 0x12, 0x05, 0xbb, 0x1a, 0xb0, 0xe0, 0x12],
+         [0xae, 0x97, 0xa1, 0x0f, 0xd4, 0x34, 0xe0, 0x15],
+         [0xb4, 0xa3, 0x15, 0x08, 0xbe, 0xff, 0x4d, 0x31],
+         [0x81, 0x39, 0x62, 0x29, 0xf0, 0x90, 0x79, 0x02],
+         [0x4d, 0x0c, 0xf4, 0x9e, 0xe5, 0xd4, 0xdc, 0xca],
+         [0x5c, 0x73, 0x33, 0x6a, 0x76, 0xd8, 0xbf, 0x9a],
+         [0xd0, 0xa7, 0x04, 0x53, 0x6b, 0xa9, 0x3e, 0x0e],
+         [0x92, 0x59, 0x58, 0xfc, 0xd6, 0x42, 0x0c, 0xad],
+         [0xa9, 0x15, 0xc2, 0x9b, 0xc8, 0x06, 0x73, 0x18],
+         [0x95, 0x2b, 0x79, 0xf3, 0xbc, 0x0a, 0xa6, 0xd4],
+         [0xf2, 0x1d, 0xf2, 0xe4, 0x1d, 0x45, 0x35, 0xf9],
+         [0x87, 0x57, 0x75, 0x19, 0x04, 0x8f, 0x53, 0xa9],
+         [0x10, 0xa5, 0x6c, 0xf5, 0xdf, 0xcd, 0x9a, 0xdb],
+         [0xeb, 0x75, 0x09, 0x5c, 0xcd, 0x98, 0x6c, 0xd0],
+         [0x51, 0xa9, 0xcb, 0x9e, 0xcb, 0xa3, 0x12, 0xe6],
+         [0x96, 0xaf, 0xad, 0xfc, 0x2c, 0xe6, 0x66, 0xc7],
+         [0x72, 0xfe, 0x52, 0x97, 0x5a, 0x43, 0x64, 0xee],
+         [0x5a, 0x16, 0x45, 0xb2, 0x76, 0xd5, 0x92, 0xa1],
+         [0xb2, 0x74, 0xcb, 0x8e, 0xbf, 0x87, 0x87, 0x0a],
+         [0x6f, 0x9b, 0xb4, 0x20, 0x3d, 0xe7, 0xb3, 0x81],
+         [0xea, 0xec, 0xb2, 0xa3, 0x0b, 0x22, 0xa8, 0x7f],
+         [0x99, 0x24, 0xa4, 0x3c, 0xc1, 0x31, 0x57, 0x24],
+         [0xbd, 0x83, 0x8d, 0x3a, 0xaf, 0xbf, 0x8d, 0xb7],
+         [0x0b, 0x1a, 0x2a, 0x32, 0x65, 0xd5, 0x1a, 0xea],
+         [0x13, 0x50, 0x79, 0xa3, 0x23, 0x1c, 0xe6, 0x60],
+         [0x93, 0x2b, 0x28, 0x46, 0xe4, 0xd7, 0x06, 0x66],
+         [0xe1, 0x91, 0x5f, 0x5c, 0xb1, 0xec, 0xa4, 0x6c],
+         [0xf3, 0x25, 0x96, 0x5c, 0xa1, 0x6d, 0x62, 0x9f],
+         [0x57, 0x5f, 0xf2, 0x8e, 0x60, 0x38, 0x1b, 0xe5],
+         [0x72, 0x45, 0x06, 0xeb, 0x4c, 0x32, 0x8a, 0x95],
+     ];
+ 
+     let k0 = 0x_07_06_05_04_03_02_01_00;
+     let k1 = 0x_0f_0e_0d_0c_0b_0a_09_08;
+     let mut buf = Vec::new();
+     let mut t = 0;
+     let mut state_inc = SipHasher::new_with_keys(k0, k1);
+ 
+     while t < 64 {
+         let vec = u8to64_le!(vecs[t], 0);
+         let out = hash_with(SipHasher::new_with_keys(k0, k1), &Bytes(&buf));
+         assert_eq!(vec, out);
+ 
+         let full = hash_with(SipHasher::new_with_keys(k0, k1), &Bytes(&buf));
+         let i = state_inc.finish();
+ 
+         assert_eq!(full, i);
+         assert_eq!(full, vec);
+ 
+         buf.push(t as u8);
+         Hasher::write(&mut state_inc, &[t as u8]);
+ 
+         t += 1;
+     }
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "32")]
+ fn test_hash_usize() {
+     let val = 0xdeadbeef_deadbeef_u64;
+     assert_ne!(hash(&(val as u64)), hash(&(val as usize)));
+     assert_eq!(hash(&(val as u32)), hash(&(val as usize)));
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "64")]
+ fn test_hash_usize() {
+     let val = 0xdeadbeef_deadbeef_u64;
+     assert_eq!(hash(&(val as u64)), hash(&(val as usize)));
+     assert_ne!(hash(&(val as u32)), hash(&(val as usize)));
+ }
+ 
+ #[test]
+ fn test_hash_idempotent() {
+     let val64 = 0xdeadbeef_deadbeef_u64;
+     assert_eq!(hash(&val64), hash(&val64));
+     let val32 = 0xdeadbeef_u32;
+     assert_eq!(hash(&val32), hash(&val32));
+ }
+ 
+ #[test]
+ fn test_hash_no_bytes_dropped_64() {
+     let val = 0xdeadbeef_deadbeef_u64;
+ 
+     assert_ne!(hash(&val), hash(&zero_byte(val, 0)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 1)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 2)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 3)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 4)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 5)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 6)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 7)));
+ 
+     fn zero_byte(val: u64, byte: usize) -> u64 {
+         assert!(byte < 8);
+         val & !(0xff << (byte * 8))
+     }
+ }
+ 
+ #[test]
+ fn test_hash_no_bytes_dropped_32() {
+     let val = 0xdeadbeef_u32;
+ 
+     assert_ne!(hash(&val), hash(&zero_byte(val, 0)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 1)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 2)));
+     assert_ne!(hash(&val), hash(&zero_byte(val, 3)));
+ 
+     fn zero_byte(val: u32, byte: usize) -> u32 {
+         assert!(byte < 4);
+         val & !(0xff << (byte * 8))
+     }
+ }
+ 
+ #[test]
+ fn test_hash_no_concat_alias() {
+     let s = ("aa", "bb");
+     let t = ("aabb", "");
+     let u = ("a", "abb");
+ 
+     assert_ne!(s, t);
+     assert_ne!(t, u);
+     assert_ne!(hash(&s), hash(&t));
+     assert_ne!(hash(&s), hash(&u));
+ 
+     let u = [1, 0, 0, 0];
+     let v = (&u[..1], &u[1..3], &u[3..]);
+     let w = (&u[..], &u[4..4], &u[4..4]);
+ 
+     assert_ne!(v, w);
+     assert_ne!(hash(&v), hash(&w));
+ }
+ 
+ #[test]
+ fn test_write_short_works() {
+     let test_usize = 0xd0c0b0a0usize;
+     let mut h1 = SipHasher::new();
+     h1.write_usize(test_usize);
+     h1.write(b"bytes");
+     h1.write(b"string");
+     h1.write_u8(0xFFu8);
+     h1.write_u8(0x01u8);
+     let mut h2 = SipHasher::new();
+     h2.write(unsafe {
+         slice::from_raw_parts(&test_usize as *const _ as *const u8, mem::size_of::<usize>())
+     });
+     h2.write(b"bytes");
+     h2.write(b"string");
+     h2.write(&[0xFFu8, 0x01u8]);
+     assert_eq!(h1.finish(), h2.finish());
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/intrinsics.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/intrinsics.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/intrinsics.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/intrinsics.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,37 ----
+ use core::any::TypeId;
+ use core::intrinsics::assume;
+ 
+ #[test]
+ fn test_typeid_sized_types() {
+     struct X;
+     struct Y(u32);
+ 
+     assert_eq!(TypeId::of::<X>(), TypeId::of::<X>());
+     assert_eq!(TypeId::of::<Y>(), TypeId::of::<Y>());
+     assert!(TypeId::of::<X>() != TypeId::of::<Y>());
+ }
+ 
+ #[test]
+ fn test_typeid_unsized_types() {
+     trait Z {}
+     struct X(str);
+     struct Y(dyn Z + 'static);
+ 
+     assert_eq!(TypeId::of::<X>(), TypeId::of::<X>());
+     assert_eq!(TypeId::of::<Y>(), TypeId::of::<Y>());
+     assert!(TypeId::of::<X>() != TypeId::of::<Y>());
+ }
+ 
+ // Check that `const_assume` feature allow `assume` intrinsic
+ // to be used in const contexts.
+ #[test]
+ fn test_assume_can_be_in_const_contexts() {
+     const unsafe fn foo(x: usize, y: usize) -> usize {
+         // SAFETY: the entire function is not safe,
+         // but it is just an example not used elsewhere.
+         unsafe { assume(y != 0) };
+         x / y
+     }
+     let rs = unsafe { foo(42, 97) };
+     assert_eq!(rs, 0);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/iter.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/iter.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/iter.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/iter.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3484 ----
+ // ignore-tidy-filelength
+ 
+ use core::cell::Cell;
+ use core::convert::TryFrom;
+ use core::iter::*;
+ 
+ /// An iterator wrapper that panics whenever `next` or `next_back` is called
+ /// after `None` has been returned.
+ struct Unfuse<I> {
+     iter: I,
+     exhausted: bool,
+ }
+ 
+ fn unfuse<I: IntoIterator>(iter: I) -> Unfuse<I::IntoIter> {
+     Unfuse { iter: iter.into_iter(), exhausted: false }
+ }
+ 
+ impl<I> Iterator for Unfuse<I>
+ where
+     I: Iterator,
+ {
+     type Item = I::Item;
+ 
+     fn next(&mut self) -> Option<Self::Item> {
+         assert!(!self.exhausted);
+         let next = self.iter.next();
+         self.exhausted = next.is_none();
+         next
+     }
+ }
+ 
+ impl<I> DoubleEndedIterator for Unfuse<I>
+ where
+     I: DoubleEndedIterator,
+ {
+     fn next_back(&mut self) -> Option<Self::Item> {
+         assert!(!self.exhausted);
+         let next = self.iter.next_back();
+         self.exhausted = next.is_none();
+         next
+     }
+ }
+ 
+ #[test]
+ fn test_lt() {
+     let empty: [isize; 0] = [];
+     let xs = [1, 2, 3];
+     let ys = [1, 2, 0];
+ 
+     assert!(!xs.iter().lt(ys.iter()));
+     assert!(!xs.iter().le(ys.iter()));
+     assert!(xs.iter().gt(ys.iter()));
+     assert!(xs.iter().ge(ys.iter()));
+ 
+     assert!(ys.iter().lt(xs.iter()));
+     assert!(ys.iter().le(xs.iter()));
+     assert!(!ys.iter().gt(xs.iter()));
+     assert!(!ys.iter().ge(xs.iter()));
+ 
+     assert!(empty.iter().lt(xs.iter()));
+     assert!(empty.iter().le(xs.iter()));
+     assert!(!empty.iter().gt(xs.iter()));
+     assert!(!empty.iter().ge(xs.iter()));
+ 
+     // Sequence with NaN
+     let u = [1.0f64, 2.0];
+     let v = [0.0f64 / 0.0, 3.0];
+ 
+     assert!(!u.iter().lt(v.iter()));
+     assert!(!u.iter().le(v.iter()));
+     assert!(!u.iter().gt(v.iter()));
+     assert!(!u.iter().ge(v.iter()));
+ 
+     let a = [0.0f64 / 0.0];
+     let b = [1.0f64];
+     let c = [2.0f64];
+ 
+     assert!(a.iter().lt(b.iter()) == (a[0] < b[0]));
+     assert!(a.iter().le(b.iter()) == (a[0] <= b[0]));
+     assert!(a.iter().gt(b.iter()) == (a[0] > b[0]));
+     assert!(a.iter().ge(b.iter()) == (a[0] >= b[0]));
+ 
+     assert!(c.iter().lt(b.iter()) == (c[0] < b[0]));
+     assert!(c.iter().le(b.iter()) == (c[0] <= b[0]));
+     assert!(c.iter().gt(b.iter()) == (c[0] > b[0]));
+     assert!(c.iter().ge(b.iter()) == (c[0] >= b[0]));
+ }
+ 
+ #[test]
+ fn test_multi_iter() {
+     let xs = [1, 2, 3, 4];
+     let ys = [4, 3, 2, 1];
+     assert!(xs.iter().eq(ys.iter().rev()));
+     assert!(xs.iter().lt(xs.iter().skip(2)));
+ }
+ 
+ #[test]
+ fn test_cmp_by() {
+     use core::cmp::Ordering;
+ 
+     let f = |x: i32, y: i32| (x * x).cmp(&y);
+     let xs = || [1, 2, 3, 4].iter().copied();
+     let ys = || [1, 4, 16].iter().copied();
+ 
+     assert_eq!(xs().cmp_by(ys(), f), Ordering::Less);
+     assert_eq!(ys().cmp_by(xs(), f), Ordering::Greater);
+     assert_eq!(xs().cmp_by(xs().map(|x| x * x), f), Ordering::Equal);
+     assert_eq!(xs().rev().cmp_by(ys().rev(), f), Ordering::Greater);
+     assert_eq!(xs().cmp_by(ys().rev(), f), Ordering::Less);
+     assert_eq!(xs().cmp_by(ys().take(2), f), Ordering::Greater);
+ }
+ 
+ #[test]
+ fn test_partial_cmp_by() {
+     use core::cmp::Ordering;
+ 
+     let f = |x: i32, y: i32| (x * x).partial_cmp(&y);
+     let xs = || [1, 2, 3, 4].iter().copied();
+     let ys = || [1, 4, 16].iter().copied();
+ 
+     assert_eq!(xs().partial_cmp_by(ys(), f), Some(Ordering::Less));
+     assert_eq!(ys().partial_cmp_by(xs(), f), Some(Ordering::Greater));
+     assert_eq!(xs().partial_cmp_by(xs().map(|x| x * x), f), Some(Ordering::Equal));
+     assert_eq!(xs().rev().partial_cmp_by(ys().rev(), f), Some(Ordering::Greater));
+     assert_eq!(xs().partial_cmp_by(xs().rev(), f), Some(Ordering::Less));
+     assert_eq!(xs().partial_cmp_by(ys().take(2), f), Some(Ordering::Greater));
+ 
+     let f = |x: f64, y: f64| (x * x).partial_cmp(&y);
+     let xs = || [1.0, 2.0, 3.0, 4.0].iter().copied();
+     let ys = || [1.0, 4.0, f64::NAN, 16.0].iter().copied();
+ 
+     assert_eq!(xs().partial_cmp_by(ys(), f), None);
+     assert_eq!(ys().partial_cmp_by(xs(), f), Some(Ordering::Greater));
+ }
+ 
+ #[test]
+ fn test_eq_by() {
+     let f = |x: i32, y: i32| x * x == y;
+     let xs = || [1, 2, 3, 4].iter().copied();
+     let ys = || [1, 4, 9, 16].iter().copied();
+ 
+     assert!(xs().eq_by(ys(), f));
+     assert!(!ys().eq_by(xs(), f));
+     assert!(!xs().eq_by(xs(), f));
+     assert!(!ys().eq_by(ys(), f));
+ 
+     assert!(!xs().take(3).eq_by(ys(), f));
+     assert!(!xs().eq_by(ys().take(3), f));
+     assert!(xs().take(3).eq_by(ys().take(3), f));
+ }
+ 
+ #[test]
+ fn test_counter_from_iter() {
+     let it = (0..).step_by(5).take(10);
+     let xs: Vec<isize> = FromIterator::from_iter(it);
+     assert_eq!(xs, [0, 5, 10, 15, 20, 25, 30, 35, 40, 45]);
+ }
+ 
+ #[test]
+ fn test_iterator_chain() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [30, 40, 50, 60];
+     let expected = [0, 1, 2, 3, 4, 5, 30, 40, 50, 60];
+     let it = xs.iter().chain(&ys);
+     let mut i = 0;
+     for &x in it {
+         assert_eq!(x, expected[i]);
+         i += 1;
+     }
+     assert_eq!(i, expected.len());
+ 
+     let ys = (30..).step_by(10).take(4);
+     let it = xs.iter().cloned().chain(ys);
+     let mut i = 0;
+     for x in it {
+         assert_eq!(x, expected[i]);
+         i += 1;
+     }
+     assert_eq!(i, expected.len());
+ }
+ 
+ #[test]
+ fn test_iterator_chain_advance_by() {
+     fn test_chain(xs: &[i32], ys: &[i32]) {
+         let len = xs.len() + ys.len();
+ 
+         for i in 0..xs.len() {
+             let mut iter = unfuse(xs).chain(unfuse(ys));
+             iter.advance_by(i).unwrap();
+             assert_eq!(iter.next(), Some(&xs[i]));
+             assert_eq!(iter.advance_by(100), Err(len - i - 1));
+         }
+ 
+         for i in 0..ys.len() {
+             let mut iter = unfuse(xs).chain(unfuse(ys));
+             iter.advance_by(xs.len() + i).unwrap();
+             assert_eq!(iter.next(), Some(&ys[i]));
+             assert_eq!(iter.advance_by(100), Err(ys.len() - i - 1));
+         }
+ 
+         let mut iter = xs.iter().chain(ys);
+         iter.advance_by(len).unwrap();
+         assert_eq!(iter.next(), None);
+ 
+         let mut iter = xs.iter().chain(ys);
+         assert_eq!(iter.advance_by(len + 1), Err(len));
+     }
+ 
+     test_chain(&[], &[]);
+     test_chain(&[], &[0, 1, 2, 3, 4, 5]);
+     test_chain(&[0, 1, 2, 3, 4, 5], &[]);
+     test_chain(&[0, 1, 2, 3, 4, 5], &[30, 40, 50, 60]);
+ }
+ 
+ #[test]
+ fn test_iterator_chain_advance_back_by() {
+     fn test_chain(xs: &[i32], ys: &[i32]) {
+         let len = xs.len() + ys.len();
+ 
+         for i in 0..ys.len() {
+             let mut iter = unfuse(xs).chain(unfuse(ys));
+             iter.advance_back_by(i).unwrap();
+             assert_eq!(iter.next_back(), Some(&ys[ys.len() - i - 1]));
+             assert_eq!(iter.advance_back_by(100), Err(len - i - 1));
+         }
+ 
+         for i in 0..xs.len() {
+             let mut iter = unfuse(xs).chain(unfuse(ys));
+             iter.advance_back_by(ys.len() + i).unwrap();
+             assert_eq!(iter.next_back(), Some(&xs[xs.len() - i - 1]));
+             assert_eq!(iter.advance_back_by(100), Err(xs.len() - i - 1));
+         }
+ 
+         let mut iter = xs.iter().chain(ys);
+         iter.advance_back_by(len).unwrap();
+         assert_eq!(iter.next_back(), None);
+ 
+         let mut iter = xs.iter().chain(ys);
+         assert_eq!(iter.advance_back_by(len + 1), Err(len));
+     }
+ 
+     test_chain(&[], &[]);
+     test_chain(&[], &[0, 1, 2, 3, 4, 5]);
+     test_chain(&[0, 1, 2, 3, 4, 5], &[]);
+     test_chain(&[0, 1, 2, 3, 4, 5], &[30, 40, 50, 60]);
+ }
+ 
+ #[test]
+ fn test_iterator_chain_nth() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [30, 40, 50, 60];
+     let zs = [];
+     let expected = [0, 1, 2, 3, 4, 5, 30, 40, 50, 60];
+     for (i, x) in expected.iter().enumerate() {
+         assert_eq!(Some(x), xs.iter().chain(&ys).nth(i));
+     }
+     assert_eq!(zs.iter().chain(&xs).nth(0), Some(&0));
+ 
+     let mut it = xs.iter().chain(&zs);
+     assert_eq!(it.nth(5), Some(&5));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_chain_nth_back() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [30, 40, 50, 60];
+     let zs = [];
+     let expected = [0, 1, 2, 3, 4, 5, 30, 40, 50, 60];
+     for (i, x) in expected.iter().rev().enumerate() {
+         assert_eq!(Some(x), xs.iter().chain(&ys).nth_back(i));
+     }
+     assert_eq!(zs.iter().chain(&xs).nth_back(0), Some(&5));
+ 
+     let mut it = xs.iter().chain(&zs);
+     assert_eq!(it.nth_back(5), Some(&0));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_chain_last() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [30, 40, 50, 60];
+     let zs = [];
+     assert_eq!(xs.iter().chain(&ys).last(), Some(&60));
+     assert_eq!(zs.iter().chain(&ys).last(), Some(&60));
+     assert_eq!(ys.iter().chain(&zs).last(), Some(&60));
+     assert_eq!(zs.iter().chain(&zs).last(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_chain_count() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [30, 40, 50, 60];
+     let zs = [];
+     assert_eq!(xs.iter().chain(&ys).count(), 10);
+     assert_eq!(zs.iter().chain(&ys).count(), 4);
+ }
+ 
+ #[test]
+ fn test_iterator_chain_find() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [30, 40, 50, 60];
+     let mut iter = xs.iter().chain(&ys);
+     assert_eq!(iter.find(|&&i| i == 4), Some(&4));
+     assert_eq!(iter.next(), Some(&5));
+     assert_eq!(iter.find(|&&i| i == 40), Some(&40));
+     assert_eq!(iter.next(), Some(&50));
+     assert_eq!(iter.find(|&&i| i == 100), None);
+     assert_eq!(iter.next(), None);
+ }
+ 
+ struct Toggle {
+     is_empty: bool,
+ }
+ 
+ impl Iterator for Toggle {
+     type Item = ();
+ 
+     // alternates between `None` and `Some(())`
+     fn next(&mut self) -> Option<Self::Item> {
+         if self.is_empty {
+             self.is_empty = false;
+             None
+         } else {
+             self.is_empty = true;
+             Some(())
+         }
+     }
+ 
+     fn size_hint(&self) -> (usize, Option<usize>) {
+         if self.is_empty { (0, Some(0)) } else { (1, Some(1)) }
+     }
+ }
+ 
+ impl DoubleEndedIterator for Toggle {
+     fn next_back(&mut self) -> Option<Self::Item> {
+         self.next()
+     }
+ }
+ 
+ #[test]
+ fn test_iterator_chain_size_hint() {
+     // this chains an iterator of length 0 with an iterator of length 1,
+     // so after calling `.next()` once, the iterator is empty and the
+     // state is `ChainState::Back`. `.size_hint()` should now disregard
+     // the size hint of the left iterator
+     let mut iter = Toggle { is_empty: true }.chain(once(()));
+     assert_eq!(iter.next(), Some(()));
+     assert_eq!(iter.size_hint(), (0, Some(0)));
+ 
+     let mut iter = once(()).chain(Toggle { is_empty: true });
+     assert_eq!(iter.next_back(), Some(()));
+     assert_eq!(iter.size_hint(), (0, Some(0)));
+ }
+ 
+ #[test]
+ fn test_iterator_chain_unfused() {
+     // Chain shouldn't be fused in its second iterator, depending on direction
+     let mut iter = NonFused::new(empty()).chain(Toggle { is_empty: true });
+     iter.next().unwrap_none();
+     iter.next().unwrap();
+     iter.next().unwrap_none();
+ 
+     let mut iter = Toggle { is_empty: true }.chain(NonFused::new(empty()));
+     iter.next_back().unwrap_none();
+     iter.next_back().unwrap();
+     iter.next_back().unwrap_none();
+ }
+ 
+ #[test]
+ fn test_zip_nth() {
+     let xs = [0, 1, 2, 4, 5];
+     let ys = [10, 11, 12];
+ 
+     let mut it = xs.iter().zip(&ys);
+     assert_eq!(it.nth(0), Some((&0, &10)));
+     assert_eq!(it.nth(1), Some((&2, &12)));
+     assert_eq!(it.nth(0), None);
+ 
+     let mut it = xs.iter().zip(&ys);
+     assert_eq!(it.nth(3), None);
+ 
+     let mut it = ys.iter().zip(&xs);
+     assert_eq!(it.nth(3), None);
+ }
+ 
+ #[test]
+ fn test_zip_nth_side_effects() {
+     let mut a = Vec::new();
+     let mut b = Vec::new();
+     let value = [1, 2, 3, 4, 5, 6]
+         .iter()
+         .cloned()
+         .map(|n| {
+             a.push(n);
+             n * 10
+         })
+         .zip([2, 3, 4, 5, 6, 7, 8].iter().cloned().map(|n| {
+             b.push(n * 100);
+             n * 1000
+         }))
+         .skip(1)
+         .nth(3);
+     assert_eq!(value, Some((50, 6000)));
+     assert_eq!(a, vec![1, 2, 3, 4, 5]);
+     assert_eq!(b, vec![200, 300, 400, 500, 600]);
+ }
+ 
+ #[test]
+ fn test_zip_next_back_side_effects() {
+     let mut a = Vec::new();
+     let mut b = Vec::new();
+     let mut iter = [1, 2, 3, 4, 5, 6]
+         .iter()
+         .cloned()
+         .map(|n| {
+             a.push(n);
+             n * 10
+         })
+         .zip([2, 3, 4, 5, 6, 7, 8].iter().cloned().map(|n| {
+             b.push(n * 100);
+             n * 1000
+         }));
+ 
+     // The second iterator is one item longer, so `next_back` is called on it
+     // one more time.
+     assert_eq!(iter.next_back(), Some((60, 7000)));
+     assert_eq!(iter.next_back(), Some((50, 6000)));
+     assert_eq!(iter.next_back(), Some((40, 5000)));
+     assert_eq!(iter.next_back(), Some((30, 4000)));
+     assert_eq!(a, vec![6, 5, 4, 3]);
+     assert_eq!(b, vec![800, 700, 600, 500, 400]);
+ }
+ 
+ #[test]
+ fn test_zip_nth_back_side_effects() {
+     let mut a = Vec::new();
+     let mut b = Vec::new();
+     let value = [1, 2, 3, 4, 5, 6]
+         .iter()
+         .cloned()
+         .map(|n| {
+             a.push(n);
+             n * 10
+         })
+         .zip([2, 3, 4, 5, 6, 7, 8].iter().cloned().map(|n| {
+             b.push(n * 100);
+             n * 1000
+         }))
+         .nth_back(3);
+     assert_eq!(value, Some((30, 4000)));
+     assert_eq!(a, vec![6, 5, 4, 3]);
+     assert_eq!(b, vec![800, 700, 600, 500, 400]);
+ }
+ 
+ #[test]
+ fn test_zip_next_back_side_effects_exhausted() {
+     let mut a = Vec::new();
+     let mut b = Vec::new();
+     let mut iter = [1, 2, 3, 4, 5, 6]
+         .iter()
+         .cloned()
+         .map(|n| {
+             a.push(n);
+             n * 10
+         })
+         .zip([2, 3, 4].iter().cloned().map(|n| {
+             b.push(n * 100);
+             n * 1000
+         }));
+ 
+     iter.next();
+     iter.next();
+     iter.next();
+     iter.next();
+     assert_eq!(iter.next_back(), None);
+     assert_eq!(a, vec![1, 2, 3, 4, 6, 5]);
+     assert_eq!(b, vec![200, 300, 400]);
+ }
+ 
+ #[derive(Debug)]
+ struct CountClone(Cell<i32>);
+ 
+ fn count_clone() -> CountClone {
+     CountClone(Cell::new(0))
+ }
+ 
+ impl PartialEq<i32> for CountClone {
+     fn eq(&self, rhs: &i32) -> bool {
+         self.0.get() == *rhs
+     }
+ }
+ 
+ impl Clone for CountClone {
+     fn clone(&self) -> Self {
+         let ret = CountClone(self.0.clone());
+         let n = self.0.get();
+         self.0.set(n + 1);
+         ret
+     }
+ }
+ 
+ #[test]
+ fn test_zip_cloned_sideffectful() {
+     let xs = [count_clone(), count_clone(), count_clone(), count_clone()];
+     let ys = [count_clone(), count_clone()];
+ 
+     for _ in xs.iter().cloned().zip(ys.iter().cloned()) {}
+ 
+     assert_eq!(&xs, &[1, 1, 1, 0][..]);
+     assert_eq!(&ys, &[1, 1][..]);
+ 
+     let xs = [count_clone(), count_clone()];
+     let ys = [count_clone(), count_clone(), count_clone(), count_clone()];
+ 
+     for _ in xs.iter().cloned().zip(ys.iter().cloned()) {}
+ 
+     assert_eq!(&xs, &[1, 1][..]);
+     assert_eq!(&ys, &[1, 1, 0, 0][..]);
+ }
+ 
+ #[test]
+ fn test_zip_map_sideffectful() {
+     let mut xs = [0; 6];
+     let mut ys = [0; 4];
+ 
+     for _ in xs.iter_mut().map(|x| *x += 1).zip(ys.iter_mut().map(|y| *y += 1)) {}
+ 
+     assert_eq!(&xs, &[1, 1, 1, 1, 1, 0]);
+     assert_eq!(&ys, &[1, 1, 1, 1]);
+ 
+     let mut xs = [0; 4];
+     let mut ys = [0; 6];
+ 
+     for _ in xs.iter_mut().map(|x| *x += 1).zip(ys.iter_mut().map(|y| *y += 1)) {}
+ 
+     assert_eq!(&xs, &[1, 1, 1, 1]);
+     assert_eq!(&ys, &[1, 1, 1, 1, 0, 0]);
+ }
+ 
+ #[test]
+ fn test_zip_map_rev_sideffectful() {
+     let mut xs = [0; 6];
+     let mut ys = [0; 4];
+ 
+     {
+         let mut it = xs.iter_mut().map(|x| *x += 1).zip(ys.iter_mut().map(|y| *y += 1));
+         it.next_back();
+     }
+     assert_eq!(&xs, &[0, 0, 0, 1, 1, 1]);
+     assert_eq!(&ys, &[0, 0, 0, 1]);
+ 
+     let mut xs = [0; 6];
+     let mut ys = [0; 4];
+ 
+     {
+         let mut it = xs.iter_mut().map(|x| *x += 1).zip(ys.iter_mut().map(|y| *y += 1));
+         (&mut it).take(5).count();
+         it.next_back();
+     }
+     assert_eq!(&xs, &[1, 1, 1, 1, 1, 1]);
+     assert_eq!(&ys, &[1, 1, 1, 1]);
+ }
+ 
+ #[test]
+ fn test_zip_nested_sideffectful() {
+     let mut xs = [0; 6];
+     let ys = [0; 4];
+ 
+     {
+         // test that it has the side effect nested inside enumerate
+         let it = xs.iter_mut().map(|x| *x = 1).enumerate().zip(&ys);
+         it.count();
+     }
+     assert_eq!(&xs, &[1, 1, 1, 1, 1, 0]);
+ }
+ 
+ #[test]
+ fn test_zip_nth_back_side_effects_exhausted() {
+     let mut a = Vec::new();
+     let mut b = Vec::new();
+     let mut iter = [1, 2, 3, 4, 5, 6]
+         .iter()
+         .cloned()
+         .map(|n| {
+             a.push(n);
+             n * 10
+         })
+         .zip([2, 3, 4].iter().cloned().map(|n| {
+             b.push(n * 100);
+             n * 1000
+         }));
+ 
+     iter.next();
+     iter.next();
+     iter.next();
+     iter.next();
+     assert_eq!(iter.nth_back(0), None);
+     assert_eq!(a, vec![1, 2, 3, 4, 6, 5]);
+     assert_eq!(b, vec![200, 300, 400]);
+ }
+ 
+ #[test]
+ fn test_iterator_step_by() {
+     // Identity
+     let mut it = (0..).step_by(1).take(3);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next(), Some(1));
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(it.next(), None);
+ 
+     let mut it = (0..).step_by(3).take(4);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next(), Some(3));
+     assert_eq!(it.next(), Some(6));
+     assert_eq!(it.next(), Some(9));
+     assert_eq!(it.next(), None);
+ 
+     let mut it = (0..3).step_by(1);
+     assert_eq!(it.next_back(), Some(2));
+     assert_eq!(it.next_back(), Some(1));
+     assert_eq!(it.next_back(), Some(0));
+     assert_eq!(it.next_back(), None);
+ 
+     let mut it = (0..11).step_by(3);
+     assert_eq!(it.next_back(), Some(9));
+     assert_eq!(it.next_back(), Some(6));
+     assert_eq!(it.next_back(), Some(3));
+     assert_eq!(it.next_back(), Some(0));
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_step_by_nth() {
+     let mut it = (0..16).step_by(5);
+     assert_eq!(it.nth(0), Some(0));
+     assert_eq!(it.nth(0), Some(5));
+     assert_eq!(it.nth(0), Some(10));
+     assert_eq!(it.nth(0), Some(15));
+     assert_eq!(it.nth(0), None);
+ 
+     let it = (0..18).step_by(5);
+     assert_eq!(it.clone().nth(0), Some(0));
+     assert_eq!(it.clone().nth(1), Some(5));
+     assert_eq!(it.clone().nth(2), Some(10));
+     assert_eq!(it.clone().nth(3), Some(15));
+     assert_eq!(it.clone().nth(4), None);
+     assert_eq!(it.clone().nth(42), None);
+ }
+ 
+ #[test]
+ fn test_iterator_step_by_nth_overflow() {
+     #[cfg(target_pointer_width = "8")]
+     type Bigger = u16;
+     #[cfg(target_pointer_width = "16")]
+     type Bigger = u32;
+     #[cfg(target_pointer_width = "32")]
+     type Bigger = u64;
+     #[cfg(target_pointer_width = "64")]
+     type Bigger = u128;
+ 
+     #[derive(Clone)]
+     struct Test(Bigger);
+     impl Iterator for &mut Test {
+         type Item = i32;
+         fn next(&mut self) -> Option<Self::Item> {
+             Some(21)
+         }
+         fn nth(&mut self, n: usize) -> Option<Self::Item> {
+             self.0 += n as Bigger + 1;
+             Some(42)
+         }
+     }
+ 
+     let mut it = Test(0);
+     let root = usize::MAX >> (usize::BITS / 2);
+     let n = root + 20;
+     (&mut it).step_by(n).nth(n);
+     assert_eq!(it.0, n as Bigger * n as Bigger);
+ 
+     // large step
+     let mut it = Test(0);
+     (&mut it).step_by(usize::MAX).nth(5);
+     assert_eq!(it.0, (usize::MAX as Bigger) * 5);
+ 
+     // n + 1 overflows
+     let mut it = Test(0);
+     (&mut it).step_by(2).nth(usize::MAX);
+     assert_eq!(it.0, (usize::MAX as Bigger) * 2);
+ 
+     // n + 1 overflows
+     let mut it = Test(0);
+     (&mut it).step_by(1).nth(usize::MAX);
+     assert_eq!(it.0, (usize::MAX as Bigger) * 1);
+ }
+ 
+ #[test]
+ fn test_iterator_step_by_nth_try_fold() {
+     let mut it = (0..).step_by(10);
+     assert_eq!(it.try_fold(0, i8::checked_add), None);
+     assert_eq!(it.next(), Some(60));
+     assert_eq!(it.try_fold(0, i8::checked_add), None);
+     assert_eq!(it.next(), Some(90));
+ 
+     let mut it = (100..).step_by(10);
+     assert_eq!(it.try_fold(50, i8::checked_add), None);
+     assert_eq!(it.next(), Some(110));
+ 
+     let mut it = (100..=100).step_by(10);
+     assert_eq!(it.next(), Some(100));
+     assert_eq!(it.try_fold(0, i8::checked_add), Some(0));
+ }
+ 
+ #[test]
+ fn test_iterator_step_by_nth_back() {
+     let mut it = (0..16).step_by(5);
+     assert_eq!(it.nth_back(0), Some(15));
+     assert_eq!(it.nth_back(0), Some(10));
+     assert_eq!(it.nth_back(0), Some(5));
+     assert_eq!(it.nth_back(0), Some(0));
+     assert_eq!(it.nth_back(0), None);
+ 
+     let mut it = (0..16).step_by(5);
+     assert_eq!(it.next(), Some(0)); // to set `first_take` to `false`
+     assert_eq!(it.nth_back(0), Some(15));
+     assert_eq!(it.nth_back(0), Some(10));
+     assert_eq!(it.nth_back(0), Some(5));
+     assert_eq!(it.nth_back(0), None);
+ 
+     let it = || (0..18).step_by(5);
+     assert_eq!(it().nth_back(0), Some(15));
+     assert_eq!(it().nth_back(1), Some(10));
+     assert_eq!(it().nth_back(2), Some(5));
+     assert_eq!(it().nth_back(3), Some(0));
+     assert_eq!(it().nth_back(4), None);
+     assert_eq!(it().nth_back(42), None);
+ }
+ 
+ #[test]
+ fn test_iterator_step_by_nth_try_rfold() {
+     let mut it = (0..100).step_by(10);
+     assert_eq!(it.try_rfold(0, i8::checked_add), None);
+     assert_eq!(it.next_back(), Some(70));
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.try_rfold(0, i8::checked_add), None);
+     assert_eq!(it.next_back(), Some(30));
+ 
+     let mut it = (0..100).step_by(10);
+     assert_eq!(it.try_rfold(50, i8::checked_add), None);
+     assert_eq!(it.next_back(), Some(80));
+ 
+     let mut it = (100..=100).step_by(10);
+     assert_eq!(it.next_back(), Some(100));
+     assert_eq!(it.try_fold(0, i8::checked_add), Some(0));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_iterator_step_by_zero() {
+     let mut it = (0..).step_by(0);
+     it.next();
+ }
+ 
+ #[test]
+ fn test_iterator_step_by_size_hint() {
+     struct StubSizeHint(usize, Option<usize>);
+     impl Iterator for StubSizeHint {
+         type Item = ();
+         fn next(&mut self) -> Option<()> {
+             self.0 -= 1;
+             if let Some(ref mut upper) = self.1 {
+                 *upper -= 1;
+             }
+             Some(())
+         }
+         fn size_hint(&self) -> (usize, Option<usize>) {
+             (self.0, self.1)
+         }
+     }
+ 
+     // The two checks in each case are needed because the logic
+     // is different before the first call to `next()`.
+ 
+     let mut it = StubSizeHint(10, Some(10)).step_by(1);
+     assert_eq!(it.size_hint(), (10, Some(10)));
+     it.next();
+     assert_eq!(it.size_hint(), (9, Some(9)));
+ 
+     // exact multiple
+     let mut it = StubSizeHint(10, Some(10)).step_by(3);
+     assert_eq!(it.size_hint(), (4, Some(4)));
+     it.next();
+     assert_eq!(it.size_hint(), (3, Some(3)));
+ 
+     // larger base range, but not enough to get another element
+     let mut it = StubSizeHint(12, Some(12)).step_by(3);
+     assert_eq!(it.size_hint(), (4, Some(4)));
+     it.next();
+     assert_eq!(it.size_hint(), (3, Some(3)));
+ 
+     // smaller base range, so fewer resulting elements
+     let mut it = StubSizeHint(9, Some(9)).step_by(3);
+     assert_eq!(it.size_hint(), (3, Some(3)));
+     it.next();
+     assert_eq!(it.size_hint(), (2, Some(2)));
+ 
+     // infinite upper bound
+     let mut it = StubSizeHint(usize::MAX, None).step_by(1);
+     assert_eq!(it.size_hint(), (usize::MAX, None));
+     it.next();
+     assert_eq!(it.size_hint(), (usize::MAX - 1, None));
+ 
+     // still infinite with larger step
+     let mut it = StubSizeHint(7, None).step_by(3);
+     assert_eq!(it.size_hint(), (3, None));
+     it.next();
+     assert_eq!(it.size_hint(), (2, None));
+ 
+     // propagates ExactSizeIterator
+     let a = [1, 2, 3, 4, 5];
+     let it = a.iter().step_by(2);
+     assert_eq!(it.len(), 3);
+ 
+     // Cannot be TrustedLen as a step greater than one makes an iterator
+     // with (usize::MAX, None) no longer meet the safety requirements
+     trait TrustedLenCheck {
+         fn test(self) -> bool;
+     }
+     impl<T: Iterator> TrustedLenCheck for T {
+         default fn test(self) -> bool {
+             false
+         }
+     }
+     impl<T: TrustedLen> TrustedLenCheck for T {
+         fn test(self) -> bool {
+             true
+         }
+     }
+     assert!(TrustedLenCheck::test(a.iter()));
+     assert!(!TrustedLenCheck::test(a.iter().step_by(1)));
+ }
+ 
+ #[test]
+ fn test_filter_map() {
+     let it = (0..).step_by(1).take(10).filter_map(|x| if x % 2 == 0 { Some(x * x) } else { None });
+     assert_eq!(it.collect::<Vec<usize>>(), [0 * 0, 2 * 2, 4 * 4, 6 * 6, 8 * 8]);
+ }
+ 
+ #[test]
+ fn test_filter_map_fold() {
+     let xs = [0, 1, 2, 3, 4, 5, 6, 7, 8];
+     let ys = [0 * 0, 2 * 2, 4 * 4, 6 * 6, 8 * 8];
+     let it = xs.iter().filter_map(|&x| if x % 2 == 0 { Some(x * x) } else { None });
+     let i = it.fold(0, |i, x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let it = xs.iter().filter_map(|&x| if x % 2 == 0 { Some(x * x) } else { None });
+     let i = it.rfold(ys.len(), |i, x| {
+         assert_eq!(x, ys[i - 1]);
+         i - 1
+     });
+     assert_eq!(i, 0);
+ }
+ 
+ #[test]
+ fn test_iterator_enumerate() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let it = xs.iter().enumerate();
+     for (i, &x) in it {
+         assert_eq!(i, x);
+     }
+ }
+ 
+ #[test]
+ fn test_iterator_enumerate_nth() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     for (i, &x) in xs.iter().enumerate() {
+         assert_eq!(i, x);
+     }
+ 
+     let mut it = xs.iter().enumerate();
+     while let Some((i, &x)) = it.nth(0) {
+         assert_eq!(i, x);
+     }
+ 
+     let mut it = xs.iter().enumerate();
+     while let Some((i, &x)) = it.nth(1) {
+         assert_eq!(i, x);
+     }
+ 
+     let (i, &x) = xs.iter().enumerate().nth(3).unwrap();
+     assert_eq!(i, x);
+     assert_eq!(i, 3);
+ }
+ 
+ #[test]
+ fn test_iterator_enumerate_nth_back() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let mut it = xs.iter().enumerate();
+     while let Some((i, &x)) = it.nth_back(0) {
+         assert_eq!(i, x);
+     }
+ 
+     let mut it = xs.iter().enumerate();
+     while let Some((i, &x)) = it.nth_back(1) {
+         assert_eq!(i, x);
+     }
+ 
+     let (i, &x) = xs.iter().enumerate().nth_back(3).unwrap();
+     assert_eq!(i, x);
+     assert_eq!(i, 2);
+ }
+ 
+ #[test]
+ fn test_iterator_enumerate_count() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     assert_eq!(xs.iter().enumerate().count(), 6);
+ }
+ 
+ #[test]
+ fn test_iterator_enumerate_fold() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let mut it = xs.iter().enumerate();
+     // steal a couple to get an interesting offset
+     assert_eq!(it.next(), Some((0, &0)));
+     assert_eq!(it.next(), Some((1, &1)));
+     let i = it.fold(2, |i, (j, &x)| {
+         assert_eq!(i, j);
+         assert_eq!(x, xs[j]);
+         i + 1
+     });
+     assert_eq!(i, xs.len());
+ 
+     let mut it = xs.iter().enumerate();
+     assert_eq!(it.next(), Some((0, &0)));
+     let i = it.rfold(xs.len() - 1, |i, (j, &x)| {
+         assert_eq!(i, j);
+         assert_eq!(x, xs[j]);
+         i - 1
+     });
+     assert_eq!(i, 0);
+ }
+ 
+ #[test]
+ fn test_iterator_filter_count() {
+     let xs = [0, 1, 2, 3, 4, 5, 6, 7, 8];
+     assert_eq!(xs.iter().filter(|&&x| x % 2 == 0).count(), 5);
+ }
+ 
+ #[test]
+ fn test_iterator_filter_fold() {
+     let xs = [0, 1, 2, 3, 4, 5, 6, 7, 8];
+     let ys = [0, 2, 4, 6, 8];
+     let it = xs.iter().filter(|&&x| x % 2 == 0);
+     let i = it.fold(0, |i, &x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let it = xs.iter().filter(|&&x| x % 2 == 0);
+     let i = it.rfold(ys.len(), |i, &x| {
+         assert_eq!(x, ys[i - 1]);
+         i - 1
+     });
+     assert_eq!(i, 0);
+ }
+ 
+ #[test]
+ fn test_iterator_peekable() {
+     let xs = vec![0, 1, 2, 3, 4, 5];
+ 
+     let mut it = xs.iter().cloned().peekable();
+     assert_eq!(it.len(), 6);
+     assert_eq!(it.peek().unwrap(), &0);
+     assert_eq!(it.len(), 6);
+     assert_eq!(it.next().unwrap(), 0);
+     assert_eq!(it.len(), 5);
+     assert_eq!(it.next().unwrap(), 1);
+     assert_eq!(it.len(), 4);
+     assert_eq!(it.next().unwrap(), 2);
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.peek().unwrap(), &3);
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.peek().unwrap(), &3);
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.next().unwrap(), 3);
+     assert_eq!(it.len(), 2);
+     assert_eq!(it.next().unwrap(), 4);
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.peek().unwrap(), &5);
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.next().unwrap(), 5);
+     assert_eq!(it.len(), 0);
+     assert!(it.peek().is_none());
+     assert_eq!(it.len(), 0);
+     assert!(it.next().is_none());
+     assert_eq!(it.len(), 0);
+ 
+     let mut it = xs.iter().cloned().peekable();
+     assert_eq!(it.len(), 6);
+     assert_eq!(it.peek().unwrap(), &0);
+     assert_eq!(it.len(), 6);
+     assert_eq!(it.next_back().unwrap(), 5);
+     assert_eq!(it.len(), 5);
+     assert_eq!(it.next_back().unwrap(), 4);
+     assert_eq!(it.len(), 4);
+     assert_eq!(it.next_back().unwrap(), 3);
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.peek().unwrap(), &0);
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.peek().unwrap(), &0);
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.next_back().unwrap(), 2);
+     assert_eq!(it.len(), 2);
+     assert_eq!(it.next_back().unwrap(), 1);
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.peek().unwrap(), &0);
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.next_back().unwrap(), 0);
+     assert_eq!(it.len(), 0);
+     assert!(it.peek().is_none());
+     assert_eq!(it.len(), 0);
+     assert!(it.next_back().is_none());
+     assert_eq!(it.len(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_count() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [10];
+     let zs: [i32; 0] = [];
+ 
+     assert_eq!(xs.iter().peekable().count(), 6);
+ 
+     let mut it = xs.iter().peekable();
+     assert_eq!(it.peek(), Some(&&0));
+     assert_eq!(it.count(), 6);
+ 
+     assert_eq!(ys.iter().peekable().count(), 1);
+ 
+     let mut it = ys.iter().peekable();
+     assert_eq!(it.peek(), Some(&&10));
+     assert_eq!(it.count(), 1);
+ 
+     assert_eq!(zs.iter().peekable().count(), 0);
+ 
+     let mut it = zs.iter().peekable();
+     assert_eq!(it.peek(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_nth() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let mut it = xs.iter().peekable();
+ 
+     assert_eq!(it.peek(), Some(&&0));
+     assert_eq!(it.nth(0), Some(&0));
+     assert_eq!(it.peek(), Some(&&1));
+     assert_eq!(it.nth(1), Some(&2));
+     assert_eq!(it.peek(), Some(&&3));
+     assert_eq!(it.nth(2), Some(&5));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_last() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let ys = [0];
+ 
+     let mut it = xs.iter().peekable();
+     assert_eq!(it.peek(), Some(&&0));
+     assert_eq!(it.last(), Some(&5));
+ 
+     let mut it = ys.iter().peekable();
+     assert_eq!(it.peek(), Some(&&0));
+     assert_eq!(it.last(), Some(&0));
+ 
+     let mut it = ys.iter().peekable();
+     assert_eq!(it.next(), Some(&0));
+     assert_eq!(it.peek(), None);
+     assert_eq!(it.last(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_fold() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let mut it = xs.iter().peekable();
+     assert_eq!(it.peek(), Some(&&0));
+     let i = it.fold(0, |i, &x| {
+         assert_eq!(x, xs[i]);
+         i + 1
+     });
+     assert_eq!(i, xs.len());
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_rfold() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let mut it = xs.iter().peekable();
+     assert_eq!(it.peek(), Some(&&0));
+     let i = it.rfold(0, |i, &x| {
+         assert_eq!(x, xs[xs.len() - 1 - i]);
+         i + 1
+     });
+     assert_eq!(i, xs.len());
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_next_if_eq() {
+     // first, try on references
+     let xs = vec!["Heart", "of", "Gold"];
+     let mut it = xs.into_iter().peekable();
+     // try before `peek()`
+     assert_eq!(it.next_if_eq(&"trillian"), None);
+     assert_eq!(it.next_if_eq(&"Heart"), Some("Heart"));
+     // try after peek()
+     assert_eq!(it.peek(), Some(&"of"));
+     assert_eq!(it.next_if_eq(&"of"), Some("of"));
+     assert_eq!(it.next_if_eq(&"zaphod"), None);
+     // make sure `next()` still behaves
+     assert_eq!(it.next(), Some("Gold"));
+ 
+     // make sure comparison works for owned values
+     let xs = vec![String::from("Ludicrous"), "speed".into()];
+     let mut it = xs.into_iter().peekable();
+     // make sure basic functionality works
+     assert_eq!(it.next_if_eq("Ludicrous"), Some("Ludicrous".into()));
+     assert_eq!(it.next_if_eq("speed"), Some("speed".into()));
+     assert_eq!(it.next_if_eq(""), None);
+ }
+ 
+ /// This is an iterator that follows the Iterator contract,
+ /// but it is not fused. After having returned None once, it will start
+ /// producing elements if .next() is called again.
+ pub struct CycleIter<'a, T> {
+     index: usize,
+     data: &'a [T],
+ }
+ 
+ pub fn cycle<T>(data: &[T]) -> CycleIter<'_, T> {
+     CycleIter { index: 0, data }
+ }
+ 
+ impl<'a, T> Iterator for CycleIter<'a, T> {
+     type Item = &'a T;
+     fn next(&mut self) -> Option<Self::Item> {
+         let elt = self.data.get(self.index);
+         self.index += 1;
+         self.index %= 1 + self.data.len();
+         elt
+     }
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_remember_peek_none_1() {
+     // Check that the loop using .peek() terminates
+     let data = [1, 2, 3];
+     let mut iter = cycle(&data).peekable();
+ 
+     let mut n = 0;
+     while let Some(_) = iter.next() {
+         let is_the_last = iter.peek().is_none();
+         assert_eq!(is_the_last, n == data.len() - 1);
+         n += 1;
+         if n > data.len() {
+             break;
+         }
+     }
+     assert_eq!(n, data.len());
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_remember_peek_none_2() {
+     let data = [0];
+     let mut iter = cycle(&data).peekable();
+     iter.next();
+     assert_eq!(iter.peek(), None);
+     assert_eq!(iter.last(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_peekable_remember_peek_none_3() {
+     let data = [0];
+     let mut iter = cycle(&data).peekable();
+     iter.peek();
+     assert_eq!(iter.nth(0), Some(&0));
+ 
+     let mut iter = cycle(&data).peekable();
+     iter.next();
+     assert_eq!(iter.peek(), None);
+     assert_eq!(iter.nth(0), None);
+ }
+ 
+ #[test]
+ fn test_iterator_take_while() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19];
+     let ys = [0, 1, 2, 3, 5, 13];
+     let it = xs.iter().take_while(|&x| *x < 15);
+     let mut i = 0;
+     for x in it {
+         assert_eq!(*x, ys[i]);
+         i += 1;
+     }
+     assert_eq!(i, ys.len());
+ }
+ 
+ #[test]
+ fn test_iterator_skip_while() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19];
+     let ys = [15, 16, 17, 19];
+     let it = xs.iter().skip_while(|&x| *x < 15);
+     let mut i = 0;
+     for x in it {
+         assert_eq!(*x, ys[i]);
+         i += 1;
+     }
+     assert_eq!(i, ys.len());
+ }
+ 
+ #[test]
+ fn test_iterator_skip_while_fold() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19];
+     let ys = [15, 16, 17, 19];
+     let it = xs.iter().skip_while(|&x| *x < 15);
+     let i = it.fold(0, |i, &x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let mut it = xs.iter().skip_while(|&x| *x < 15);
+     assert_eq!(it.next(), Some(&ys[0])); // process skips before folding
+     let i = it.fold(1, |i, &x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ }
+ 
+ #[test]
+ fn test_iterator_skip() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19, 20, 30];
+     let ys = [13, 15, 16, 17, 19, 20, 30];
+     let mut it = xs.iter().skip(5);
+     let mut i = 0;
+     while let Some(&x) = it.next() {
+         assert_eq!(x, ys[i]);
+         i += 1;
+         assert_eq!(it.len(), xs.len() - 5 - i);
+     }
+     assert_eq!(i, ys.len());
+     assert_eq!(it.len(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_skip_doubleended() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19, 20, 30];
+     let mut it = xs.iter().rev().skip(5);
+     assert_eq!(it.next(), Some(&15));
+     assert_eq!(it.by_ref().rev().next(), Some(&0));
+     assert_eq!(it.next(), Some(&13));
+     assert_eq!(it.by_ref().rev().next(), Some(&1));
+     assert_eq!(it.next(), Some(&5));
+     assert_eq!(it.by_ref().rev().next(), Some(&2));
+     assert_eq!(it.next(), Some(&3));
+     assert_eq!(it.next(), None);
+     let mut it = xs.iter().rev().skip(5).rev();
+     assert_eq!(it.next(), Some(&0));
+     assert_eq!(it.rev().next(), Some(&15));
+     let mut it_base = xs.iter();
+     {
+         let mut it = it_base.by_ref().skip(5).rev();
+         assert_eq!(it.next(), Some(&30));
+         assert_eq!(it.next(), Some(&20));
+         assert_eq!(it.next(), Some(&19));
+         assert_eq!(it.next(), Some(&17));
+         assert_eq!(it.next(), Some(&16));
+         assert_eq!(it.next(), Some(&15));
+         assert_eq!(it.next(), Some(&13));
+         assert_eq!(it.next(), None);
+     }
+     // make sure the skipped parts have not been consumed
+     assert_eq!(it_base.next(), Some(&0));
+     assert_eq!(it_base.next(), Some(&1));
+     assert_eq!(it_base.next(), Some(&2));
+     assert_eq!(it_base.next(), Some(&3));
+     assert_eq!(it_base.next(), Some(&5));
+     assert_eq!(it_base.next(), None);
+     let it = xs.iter().skip(5).rev();
+     assert_eq!(it.last(), Some(&13));
+ }
+ 
+ #[test]
+ fn test_iterator_skip_nth() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19, 20, 30];
+ 
+     let mut it = xs.iter().skip(0);
+     assert_eq!(it.nth(0), Some(&0));
+     assert_eq!(it.nth(1), Some(&2));
+ 
+     let mut it = xs.iter().skip(5);
+     assert_eq!(it.nth(0), Some(&13));
+     assert_eq!(it.nth(1), Some(&16));
+ 
+     let mut it = xs.iter().skip(12);
+     assert_eq!(it.nth(0), None);
+ }
+ 
+ #[test]
+ fn test_iterator_skip_count() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19, 20, 30];
+ 
+     assert_eq!(xs.iter().skip(0).count(), 12);
+     assert_eq!(xs.iter().skip(1).count(), 11);
+     assert_eq!(xs.iter().skip(11).count(), 1);
+     assert_eq!(xs.iter().skip(12).count(), 0);
+     assert_eq!(xs.iter().skip(13).count(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_skip_last() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19, 20, 30];
+ 
+     assert_eq!(xs.iter().skip(0).last(), Some(&30));
+     assert_eq!(xs.iter().skip(1).last(), Some(&30));
+     assert_eq!(xs.iter().skip(11).last(), Some(&30));
+     assert_eq!(xs.iter().skip(12).last(), None);
+     assert_eq!(xs.iter().skip(13).last(), None);
+ 
+     let mut it = xs.iter().skip(5);
+     assert_eq!(it.next(), Some(&13));
+     assert_eq!(it.last(), Some(&30));
+ }
+ 
+ #[test]
+ fn test_iterator_skip_fold() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19, 20, 30];
+     let ys = [13, 15, 16, 17, 19, 20, 30];
+ 
+     let it = xs.iter().skip(5);
+     let i = it.fold(0, |i, &x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let mut it = xs.iter().skip(5);
+     assert_eq!(it.next(), Some(&ys[0])); // process skips before folding
+     let i = it.fold(1, |i, &x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let it = xs.iter().skip(5);
+     let i = it.rfold(ys.len(), |i, &x| {
+         let i = i - 1;
+         assert_eq!(x, ys[i]);
+         i
+     });
+     assert_eq!(i, 0);
+ 
+     let mut it = xs.iter().skip(5);
+     assert_eq!(it.next(), Some(&ys[0])); // process skips before folding
+     let i = it.rfold(ys.len(), |i, &x| {
+         let i = i - 1;
+         assert_eq!(x, ys[i]);
+         i
+     });
+     assert_eq!(i, 1);
+ }
+ 
+ #[test]
+ fn test_iterator_take() {
+     let xs = [0, 1, 2, 3, 5, 13, 15, 16, 17, 19];
+     let ys = [0, 1, 2, 3, 5];
+ 
+     let mut it = xs.iter().take(ys.len());
+     let mut i = 0;
+     assert_eq!(it.len(), ys.len());
+     while let Some(&x) = it.next() {
+         assert_eq!(x, ys[i]);
+         i += 1;
+         assert_eq!(it.len(), ys.len() - i);
+     }
+     assert_eq!(i, ys.len());
+     assert_eq!(it.len(), 0);
+ 
+     let mut it = xs.iter().take(ys.len());
+     let mut i = 0;
+     assert_eq!(it.len(), ys.len());
+     while let Some(&x) = it.next_back() {
+         i += 1;
+         assert_eq!(x, ys[ys.len() - i]);
+         assert_eq!(it.len(), ys.len() - i);
+     }
+     assert_eq!(i, ys.len());
+     assert_eq!(it.len(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_take_nth() {
+     let xs = [0, 1, 2, 4, 5];
+     let mut it = xs.iter();
+     {
+         let mut take = it.by_ref().take(3);
+         let mut i = 0;
+         while let Some(&x) = take.nth(0) {
+             assert_eq!(x, i);
+             i += 1;
+         }
+     }
+     assert_eq!(it.nth(1), Some(&5));
+     assert_eq!(it.nth(0), None);
+ 
+     let xs = [0, 1, 2, 3, 4];
+     let mut it = xs.iter().take(7);
+     let mut i = 1;
+     while let Some(&x) = it.nth(1) {
+         assert_eq!(x, i);
+         i += 2;
+     }
+ }
+ 
+ #[test]
+ fn test_iterator_take_nth_back() {
+     let xs = [0, 1, 2, 4, 5];
+     let mut it = xs.iter();
+     {
+         let mut take = it.by_ref().take(3);
+         let mut i = 0;
+         while let Some(&x) = take.nth_back(0) {
+             i += 1;
+             assert_eq!(x, 3 - i);
+         }
+     }
+     assert_eq!(it.nth_back(0), None);
+ 
+     let xs = [0, 1, 2, 3, 4];
+     let mut it = xs.iter().take(7);
+     assert_eq!(it.nth_back(1), Some(&3));
+     assert_eq!(it.nth_back(1), Some(&1));
+     assert_eq!(it.nth_back(1), None);
+ }
+ 
+ #[test]
+ fn test_iterator_take_short() {
+     let xs = [0, 1, 2, 3];
+ 
+     let mut it = xs.iter().take(5);
+     let mut i = 0;
+     assert_eq!(it.len(), xs.len());
+     while let Some(&x) = it.next() {
+         assert_eq!(x, xs[i]);
+         i += 1;
+         assert_eq!(it.len(), xs.len() - i);
+     }
+     assert_eq!(i, xs.len());
+     assert_eq!(it.len(), 0);
+ 
+     let mut it = xs.iter().take(5);
+     let mut i = 0;
+     assert_eq!(it.len(), xs.len());
+     while let Some(&x) = it.next_back() {
+         i += 1;
+         assert_eq!(x, xs[xs.len() - i]);
+         assert_eq!(it.len(), xs.len() - i);
+     }
+     assert_eq!(i, xs.len());
+     assert_eq!(it.len(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_scan() {
+     // test the type inference
+     fn add(old: &mut isize, new: &usize) -> Option<f64> {
+         *old += *new as isize;
+         Some(*old as f64)
+     }
+     let xs = [0, 1, 2, 3, 4];
+     let ys = [0f64, 1.0, 3.0, 6.0, 10.0];
+ 
+     let it = xs.iter().scan(0, add);
+     let mut i = 0;
+     for x in it {
+         assert_eq!(x, ys[i]);
+         i += 1;
+     }
+     assert_eq!(i, ys.len());
+ }
+ 
+ #[test]
+ fn test_iterator_flat_map() {
+     let xs = [0, 3, 6];
+     let ys = [0, 1, 2, 3, 4, 5, 6, 7, 8];
+     let it = xs.iter().flat_map(|&x| (x..).step_by(1).take(3));
+     let mut i = 0;
+     for x in it {
+         assert_eq!(x, ys[i]);
+         i += 1;
+     }
+     assert_eq!(i, ys.len());
+ }
+ 
+ /// Tests `FlatMap::fold` with items already picked off the front and back,
+ /// to make sure all parts of the `FlatMap` are folded correctly.
+ #[test]
+ fn test_iterator_flat_map_fold() {
+     let xs = [0, 3, 6];
+     let ys = [1, 2, 3, 4, 5, 6, 7];
+     let mut it = xs.iter().flat_map(|&x| x..x + 3);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next_back(), Some(8));
+     let i = it.fold(0, |i, x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let mut it = xs.iter().flat_map(|&x| x..x + 3);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next_back(), Some(8));
+     let i = it.rfold(ys.len(), |i, x| {
+         assert_eq!(x, ys[i - 1]);
+         i - 1
+     });
+     assert_eq!(i, 0);
+ }
+ 
+ #[test]
+ fn test_iterator_flatten() {
+     let xs = [0, 3, 6];
+     let ys = [0, 1, 2, 3, 4, 5, 6, 7, 8];
+     let it = xs.iter().map(|&x| (x..).step_by(1).take(3)).flatten();
+     let mut i = 0;
+     for x in it {
+         assert_eq!(x, ys[i]);
+         i += 1;
+     }
+     assert_eq!(i, ys.len());
+ }
+ 
+ /// Tests `Flatten::fold` with items already picked off the front and back,
+ /// to make sure all parts of the `Flatten` are folded correctly.
+ #[test]
+ fn test_iterator_flatten_fold() {
+     let xs = [0, 3, 6];
+     let ys = [1, 2, 3, 4, 5, 6, 7];
+     let mut it = xs.iter().map(|&x| x..x + 3).flatten();
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next_back(), Some(8));
+     let i = it.fold(0, |i, x| {
+         assert_eq!(x, ys[i]);
+         i + 1
+     });
+     assert_eq!(i, ys.len());
+ 
+     let mut it = xs.iter().map(|&x| x..x + 3).flatten();
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next_back(), Some(8));
+     let i = it.rfold(ys.len(), |i, x| {
+         assert_eq!(x, ys[i - 1]);
+         i - 1
+     });
+     assert_eq!(i, 0);
+ }
+ 
+ #[test]
+ fn test_inspect() {
+     let xs = [1, 2, 3, 4];
+     let mut n = 0;
+ 
+     let ys = xs.iter().cloned().inspect(|_| n += 1).collect::<Vec<usize>>();
+ 
+     assert_eq!(n, xs.len());
+     assert_eq!(&xs[..], &ys[..]);
+ }
+ 
+ #[test]
+ fn test_inspect_fold() {
+     let xs = [1, 2, 3, 4];
+     let mut n = 0;
+     {
+         let it = xs.iter().inspect(|_| n += 1);
+         let i = it.fold(0, |i, &x| {
+             assert_eq!(x, xs[i]);
+             i + 1
+         });
+         assert_eq!(i, xs.len());
+     }
+     assert_eq!(n, xs.len());
+ 
+     let mut n = 0;
+     {
+         let it = xs.iter().inspect(|_| n += 1);
+         let i = it.rfold(xs.len(), |i, &x| {
+             assert_eq!(x, xs[i - 1]);
+             i - 1
+         });
+         assert_eq!(i, 0);
+     }
+     assert_eq!(n, xs.len());
+ }
+ 
+ #[test]
+ fn test_cycle() {
+     let cycle_len = 3;
+     let it = (0..).step_by(1).take(cycle_len).cycle();
+     assert_eq!(it.size_hint(), (usize::MAX, None));
+     for (i, x) in it.take(100).enumerate() {
+         assert_eq!(i % cycle_len, x);
+     }
+ 
+     let mut it = (0..).step_by(1).take(0).cycle();
+     assert_eq!(it.size_hint(), (0, Some(0)));
+     assert_eq!(it.next(), None);
+ 
+     assert_eq!(empty::<i32>().cycle().fold(0, |acc, x| acc + x), 0);
+ 
+     assert_eq!(once(1).cycle().skip(1).take(4).fold(0, |acc, x| acc + x), 4);
+ 
+     assert_eq!((0..10).cycle().take(5).sum::<i32>(), 10);
+     assert_eq!((0..10).cycle().take(15).sum::<i32>(), 55);
+     assert_eq!((0..10).cycle().take(25).sum::<i32>(), 100);
+ 
+     let mut iter = (0..10).cycle();
+     iter.nth(14);
+     assert_eq!(iter.take(8).sum::<i32>(), 38);
+ 
+     let mut iter = (0..10).cycle();
+     iter.nth(9);
+     assert_eq!(iter.take(3).sum::<i32>(), 3);
+ }
+ 
+ #[test]
+ fn test_iterator_nth() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(v.iter().nth(i).unwrap(), &v[i]);
+     }
+     assert_eq!(v.iter().nth(v.len()), None);
+ }
+ 
+ #[test]
+ fn test_iterator_nth_back() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(v.iter().nth_back(i).unwrap(), &v[v.len() - 1 - i]);
+     }
+     assert_eq!(v.iter().nth_back(v.len()), None);
+ }
+ 
+ #[test]
+ fn test_iterator_rev_nth_back() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(v.iter().rev().nth_back(i).unwrap(), &v[i]);
+     }
+     assert_eq!(v.iter().rev().nth_back(v.len()), None);
+ }
+ 
+ #[test]
+ fn test_iterator_rev_nth() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(v.iter().rev().nth(i).unwrap(), &v[v.len() - 1 - i]);
+     }
+     assert_eq!(v.iter().rev().nth(v.len()), None);
+ }
+ 
+ #[test]
+ fn test_iterator_advance_by() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+ 
+     for i in 0..v.len() {
+         let mut iter = v.iter();
+         assert_eq!(iter.advance_by(i), Ok(()));
+         assert_eq!(iter.next().unwrap(), &v[i]);
+         assert_eq!(iter.advance_by(100), Err(v.len() - 1 - i));
+     }
+ 
+     assert_eq!(v.iter().advance_by(v.len()), Ok(()));
+     assert_eq!(v.iter().advance_by(100), Err(v.len()));
+ }
+ 
+ #[test]
+ fn test_iterator_advance_back_by() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+ 
+     for i in 0..v.len() {
+         let mut iter = v.iter();
+         assert_eq!(iter.advance_back_by(i), Ok(()));
+         assert_eq!(iter.next_back().unwrap(), &v[v.len() - 1 - i]);
+         assert_eq!(iter.advance_back_by(100), Err(v.len() - 1 - i));
+     }
+ 
+     assert_eq!(v.iter().advance_back_by(v.len()), Ok(()));
+     assert_eq!(v.iter().advance_back_by(100), Err(v.len()));
+ }
+ 
+ #[test]
+ fn test_iterator_rev_advance_by() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+ 
+     for i in 0..v.len() {
+         let mut iter = v.iter().rev();
+         assert_eq!(iter.advance_by(i), Ok(()));
+         assert_eq!(iter.next().unwrap(), &v[v.len() - 1 - i]);
+         assert_eq!(iter.advance_by(100), Err(v.len() - 1 - i));
+     }
+ 
+     assert_eq!(v.iter().rev().advance_by(v.len()), Ok(()));
+     assert_eq!(v.iter().rev().advance_by(100), Err(v.len()));
+ }
+ 
+ #[test]
+ fn test_iterator_rev_advance_back_by() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+ 
+     for i in 0..v.len() {
+         let mut iter = v.iter().rev();
+         assert_eq!(iter.advance_back_by(i), Ok(()));
+         assert_eq!(iter.next_back().unwrap(), &v[i]);
+         assert_eq!(iter.advance_back_by(100), Err(v.len() - 1 - i));
+     }
+ 
+     assert_eq!(v.iter().rev().advance_back_by(v.len()), Ok(()));
+     assert_eq!(v.iter().rev().advance_back_by(100), Err(v.len()));
+ }
+ 
+ #[test]
+ fn test_iterator_last() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     assert_eq!(v.iter().last().unwrap(), &4);
+     assert_eq!(v[..1].iter().last().unwrap(), &0);
+ }
+ 
+ #[test]
+ fn test_iterator_len() {
+     let v: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+     assert_eq!(v[..4].iter().count(), 4);
+     assert_eq!(v[..10].iter().count(), 10);
+     assert_eq!(v[..0].iter().count(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_sum() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+     assert_eq!(v[..4].iter().cloned().sum::<i32>(), 6);
+     assert_eq!(v.iter().cloned().sum::<i32>(), 55);
+     assert_eq!(v[..0].iter().cloned().sum::<i32>(), 0);
+ }
+ 
+ #[test]
+ fn test_iterator_sum_result() {
+     let v: &[Result<i32, ()>] = &[Ok(1), Ok(2), Ok(3), Ok(4)];
+     assert_eq!(v.iter().cloned().sum::<Result<i32, _>>(), Ok(10));
+     let v: &[Result<i32, ()>] = &[Ok(1), Err(()), Ok(3), Ok(4)];
+     assert_eq!(v.iter().cloned().sum::<Result<i32, _>>(), Err(()));
+ 
+     #[derive(PartialEq, Debug)]
+     struct S(Result<i32, ()>);
+ 
+     impl Sum<Result<i32, ()>> for S {
+         fn sum<I: Iterator<Item = Result<i32, ()>>>(mut iter: I) -> Self {
+             // takes the sum by repeatedly calling `next` on `iter`,
+             // thus testing that repeated calls to `ResultShunt::try_fold`
+             // produce the expected results
+             Self(iter.by_ref().sum())
+         }
+     }
+ 
+     let v: &[Result<i32, ()>] = &[Ok(1), Ok(2), Ok(3), Ok(4)];
+     assert_eq!(v.iter().cloned().sum::<S>(), S(Ok(10)));
+     let v: &[Result<i32, ()>] = &[Ok(1), Err(()), Ok(3), Ok(4)];
+     assert_eq!(v.iter().cloned().sum::<S>(), S(Err(())));
+ }
+ 
+ #[test]
+ fn test_iterator_sum_option() {
+     let v: &[Option<i32>] = &[Some(1), Some(2), Some(3), Some(4)];
+     assert_eq!(v.iter().cloned().sum::<Option<i32>>(), Some(10));
+     let v: &[Option<i32>] = &[Some(1), None, Some(3), Some(4)];
+     assert_eq!(v.iter().cloned().sum::<Option<i32>>(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_product() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+     assert_eq!(v[..4].iter().cloned().product::<i32>(), 0);
+     assert_eq!(v[1..5].iter().cloned().product::<i32>(), 24);
+     assert_eq!(v[..0].iter().cloned().product::<i32>(), 1);
+ }
+ 
+ #[test]
+ fn test_iterator_product_result() {
+     let v: &[Result<i32, ()>] = &[Ok(1), Ok(2), Ok(3), Ok(4)];
+     assert_eq!(v.iter().cloned().product::<Result<i32, _>>(), Ok(24));
+     let v: &[Result<i32, ()>] = &[Ok(1), Err(()), Ok(3), Ok(4)];
+     assert_eq!(v.iter().cloned().product::<Result<i32, _>>(), Err(()));
+ }
+ 
+ /// A wrapper struct that implements `Eq` and `Ord` based on the wrapped
+ /// integer modulo 3. Used to test that `Iterator::max` and `Iterator::min`
+ /// return the correct element if some of them are equal.
+ #[derive(Debug)]
+ struct Mod3(i32);
+ 
+ impl PartialEq for Mod3 {
+     fn eq(&self, other: &Self) -> bool {
+         self.0 % 3 == other.0 % 3
+     }
+ }
+ 
+ impl Eq for Mod3 {}
+ 
+ impl PartialOrd for Mod3 {
+     fn partial_cmp(&self, other: &Self) -> Option<core::cmp::Ordering> {
+         Some(self.cmp(other))
+     }
+ }
+ 
+ impl Ord for Mod3 {
+     fn cmp(&self, other: &Self) -> core::cmp::Ordering {
+         (self.0 % 3).cmp(&(other.0 % 3))
+     }
+ }
+ 
+ #[test]
+ fn test_iterator_product_option() {
+     let v: &[Option<i32>] = &[Some(1), Some(2), Some(3), Some(4)];
+     assert_eq!(v.iter().cloned().product::<Option<i32>>(), Some(24));
+     let v: &[Option<i32>] = &[Some(1), None, Some(3), Some(4)];
+     assert_eq!(v.iter().cloned().product::<Option<i32>>(), None);
+ }
+ 
+ #[test]
+ fn test_iterator_max() {
+     let v: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+     assert_eq!(v[..4].iter().cloned().max(), Some(3));
+     assert_eq!(v.iter().cloned().max(), Some(10));
+     assert_eq!(v[..0].iter().cloned().max(), None);
+     assert_eq!(v.iter().cloned().map(Mod3).max().map(|x| x.0), Some(8));
+ }
+ 
+ #[test]
+ fn test_iterator_min() {
+     let v: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
+     assert_eq!(v[..4].iter().cloned().min(), Some(0));
+     assert_eq!(v.iter().cloned().min(), Some(0));
+     assert_eq!(v[..0].iter().cloned().min(), None);
+     assert_eq!(v.iter().cloned().map(Mod3).min().map(|x| x.0), Some(0));
+ }
+ 
+ #[test]
+ fn test_iterator_size_hint() {
+     let c = (0..).step_by(1);
+     let v: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9];
+     let v2 = &[10, 11, 12];
+     let vi = v.iter();
+ 
+     assert_eq!((0..).size_hint(), (usize::MAX, None));
+     assert_eq!(c.size_hint(), (usize::MAX, None));
+     assert_eq!(vi.clone().size_hint(), (10, Some(10)));
+ 
+     assert_eq!(c.clone().take(5).size_hint(), (5, Some(5)));
+     assert_eq!(c.clone().skip(5).size_hint().1, None);
+     assert_eq!(c.clone().take_while(|_| false).size_hint(), (0, None));
+     assert_eq!(c.clone().map_while(|_| None::<()>).size_hint(), (0, None));
+     assert_eq!(c.clone().skip_while(|_| false).size_hint(), (0, None));
+     assert_eq!(c.clone().enumerate().size_hint(), (usize::MAX, None));
+     assert_eq!(c.clone().chain(vi.clone().cloned()).size_hint(), (usize::MAX, None));
+     assert_eq!(c.clone().zip(vi.clone()).size_hint(), (10, Some(10)));
+     assert_eq!(c.clone().scan(0, |_, _| Some(0)).size_hint(), (0, None));
+     assert_eq!(c.clone().filter(|_| false).size_hint(), (0, None));
+     assert_eq!(c.clone().map(|_| 0).size_hint(), (usize::MAX, None));
+     assert_eq!(c.filter_map(|_| Some(0)).size_hint(), (0, None));
+ 
+     assert_eq!(vi.clone().take(5).size_hint(), (5, Some(5)));
+     assert_eq!(vi.clone().take(12).size_hint(), (10, Some(10)));
+     assert_eq!(vi.clone().skip(3).size_hint(), (7, Some(7)));
+     assert_eq!(vi.clone().skip(12).size_hint(), (0, Some(0)));
+     assert_eq!(vi.clone().take_while(|_| false).size_hint(), (0, Some(10)));
+     assert_eq!(vi.clone().map_while(|_| None::<()>).size_hint(), (0, Some(10)));
+     assert_eq!(vi.clone().skip_while(|_| false).size_hint(), (0, Some(10)));
+     assert_eq!(vi.clone().enumerate().size_hint(), (10, Some(10)));
+     assert_eq!(vi.clone().chain(v2).size_hint(), (13, Some(13)));
+     assert_eq!(vi.clone().zip(v2).size_hint(), (3, Some(3)));
+     assert_eq!(vi.clone().scan(0, |_, _| Some(0)).size_hint(), (0, Some(10)));
+     assert_eq!(vi.clone().filter(|_| false).size_hint(), (0, Some(10)));
+     assert_eq!(vi.clone().map(|&i| i + 1).size_hint(), (10, Some(10)));
+     assert_eq!(vi.filter_map(|_| Some(0)).size_hint(), (0, Some(10)));
+ }
+ 
+ #[test]
+ fn test_collect() {
+     let a = vec![1, 2, 3, 4, 5];
+     let b: Vec<isize> = a.iter().cloned().collect();
+     assert!(a == b);
+ }
+ 
+ #[test]
+ fn test_all() {
+     let v: Box<[isize]> = Box::new([1, 2, 3, 4, 5]);
+     assert!(v.iter().all(|&x| x < 10));
+     assert!(!v.iter().all(|&x| x % 2 == 0));
+     assert!(!v.iter().all(|&x| x > 100));
+     assert!(v[..0].iter().all(|_| panic!()));
+ }
+ 
+ #[test]
+ fn test_any() {
+     let v: Box<[isize]> = Box::new([1, 2, 3, 4, 5]);
+     assert!(v.iter().any(|&x| x < 10));
+     assert!(v.iter().any(|&x| x % 2 == 0));
+     assert!(!v.iter().any(|&x| x > 100));
+     assert!(!v[..0].iter().any(|_| panic!()));
+ }
+ 
+ #[test]
+ fn test_find() {
+     let v: &[isize] = &[1, 3, 9, 27, 103, 14, 11];
+     assert_eq!(*v.iter().find(|&&x| x & 1 == 0).unwrap(), 14);
+     assert_eq!(*v.iter().find(|&&x| x % 3 == 0).unwrap(), 3);
+     assert!(v.iter().find(|&&x| x % 12 == 0).is_none());
+ }
+ 
+ #[test]
+ fn test_find_map() {
+     let xs: &[isize] = &[];
+     assert_eq!(xs.iter().find_map(half_if_even), None);
+     let xs: &[isize] = &[3, 5];
+     assert_eq!(xs.iter().find_map(half_if_even), None);
+     let xs: &[isize] = &[4, 5];
+     assert_eq!(xs.iter().find_map(half_if_even), Some(2));
+     let xs: &[isize] = &[3, 6];
+     assert_eq!(xs.iter().find_map(half_if_even), Some(3));
+ 
+     let xs: &[isize] = &[1, 2, 3, 4, 5, 6, 7];
+     let mut iter = xs.iter();
+     assert_eq!(iter.find_map(half_if_even), Some(1));
+     assert_eq!(iter.find_map(half_if_even), Some(2));
+     assert_eq!(iter.find_map(half_if_even), Some(3));
+     assert_eq!(iter.next(), Some(&7));
+ 
+     fn half_if_even(x: &isize) -> Option<isize> {
+         if x % 2 == 0 { Some(x / 2) } else { None }
+     }
+ }
+ 
+ #[test]
+ fn test_try_find() {
+     let xs: &[isize] = &[];
+     assert_eq!(xs.iter().try_find(testfn), Ok(None));
+     let xs: &[isize] = &[1, 2, 3, 4];
+     assert_eq!(xs.iter().try_find(testfn), Ok(Some(&2)));
+     let xs: &[isize] = &[1, 3, 4];
+     assert_eq!(xs.iter().try_find(testfn), Err(()));
+ 
+     let xs: &[isize] = &[1, 2, 3, 4, 5, 6, 7];
+     let mut iter = xs.iter();
+     assert_eq!(iter.try_find(testfn), Ok(Some(&2)));
+     assert_eq!(iter.try_find(testfn), Err(()));
+     assert_eq!(iter.next(), Some(&5));
+ 
+     fn testfn(x: &&isize) -> Result<bool, ()> {
+         if **x == 2 {
+             return Ok(true);
+         }
+         if **x == 4 {
+             return Err(());
+         }
+         Ok(false)
+     }
+ }
+ 
+ #[test]
+ fn test_try_find_api_usability() -> Result<(), Box<dyn std::error::Error>> {
+     let a = ["1", "2"];
+ 
+     let is_my_num = |s: &str, search: i32| -> Result<bool, std::num::ParseIntError> {
+         Ok(s.parse::<i32>()? == search)
+     };
+ 
+     let val = a.iter().try_find(|&&s| is_my_num(s, 2))?;
+     assert_eq!(val, Some(&"2"));
+ 
+     Ok(())
+ }
+ 
+ #[test]
+ fn test_position() {
+     let v = &[1, 3, 9, 27, 103, 14, 11];
+     assert_eq!(v.iter().position(|x| *x & 1 == 0).unwrap(), 5);
+     assert_eq!(v.iter().position(|x| *x % 3 == 0).unwrap(), 1);
+     assert!(v.iter().position(|x| *x % 12 == 0).is_none());
+ }
+ 
+ #[test]
+ fn test_count() {
+     let xs = &[1, 2, 2, 1, 5, 9, 0, 2];
+     assert_eq!(xs.iter().filter(|x| **x == 2).count(), 3);
+     assert_eq!(xs.iter().filter(|x| **x == 5).count(), 1);
+     assert_eq!(xs.iter().filter(|x| **x == 95).count(), 0);
+ }
+ 
+ #[test]
+ fn test_max_by_key() {
+     let xs: &[isize] = &[-3, 0, 1, 5, -10];
+     assert_eq!(*xs.iter().max_by_key(|x| x.abs()).unwrap(), -10);
+ }
+ 
+ #[test]
+ fn test_max_by() {
+     let xs: &[isize] = &[-3, 0, 1, 5, -10];
+     assert_eq!(*xs.iter().max_by(|x, y| x.abs().cmp(&y.abs())).unwrap(), -10);
+ }
+ 
+ #[test]
+ fn test_min_by_key() {
+     let xs: &[isize] = &[-3, 0, 1, 5, -10];
+     assert_eq!(*xs.iter().min_by_key(|x| x.abs()).unwrap(), 0);
+ }
+ 
+ #[test]
+ fn test_min_by() {
+     let xs: &[isize] = &[-3, 0, 1, 5, -10];
+     assert_eq!(*xs.iter().min_by(|x, y| x.abs().cmp(&y.abs())).unwrap(), 0);
+ }
+ 
+ #[test]
+ fn test_by_ref() {
+     let mut xs = 0..10;
+     // sum the first five values
+     let partial_sum = xs.by_ref().take(5).fold(0, |a, b| a + b);
+     assert_eq!(partial_sum, 10);
+     assert_eq!(xs.next(), Some(5));
+ }
+ 
+ #[test]
+ fn test_rev() {
+     let xs = [2, 4, 6, 8, 10, 12, 14, 16];
+     let mut it = xs.iter();
+     it.next();
+     it.next();
+     assert!(it.rev().cloned().collect::<Vec<isize>>() == vec![16, 14, 12, 10, 8, 6]);
+ }
+ 
+ #[test]
+ fn test_copied() {
+     let xs = [2, 4, 6, 8];
+ 
+     let mut it = xs.iter().copied();
+     assert_eq!(it.len(), 4);
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.next(), Some(4));
+     assert_eq!(it.len(), 2);
+     assert_eq!(it.next_back(), Some(8));
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.next_back(), Some(6));
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_cloned() {
+     let xs = [2, 4, 6, 8];
+ 
+     let mut it = xs.iter().cloned();
+     assert_eq!(it.len(), 4);
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.next(), Some(4));
+     assert_eq!(it.len(), 2);
+     assert_eq!(it.next_back(), Some(8));
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.next_back(), Some(6));
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_cloned_side_effects() {
+     let mut count = 0;
+     {
+         let iter = [1, 2, 3]
+             .iter()
+             .map(|x| {
+                 count += 1;
+                 x
+             })
+             .cloned()
+             .zip(&[1]);
+         for _ in iter {}
+     }
+     assert_eq!(count, 2);
+ }
+ 
+ #[test]
+ fn test_double_ended_map() {
+     let xs = [1, 2, 3, 4, 5, 6];
+     let mut it = xs.iter().map(|&x| x * -1);
+     assert_eq!(it.next(), Some(-1));
+     assert_eq!(it.next(), Some(-2));
+     assert_eq!(it.next_back(), Some(-6));
+     assert_eq!(it.next_back(), Some(-5));
+     assert_eq!(it.next(), Some(-3));
+     assert_eq!(it.next_back(), Some(-4));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_enumerate() {
+     let xs = [1, 2, 3, 4, 5, 6];
+     let mut it = xs.iter().cloned().enumerate();
+     assert_eq!(it.next(), Some((0, 1)));
+     assert_eq!(it.next(), Some((1, 2)));
+     assert_eq!(it.next_back(), Some((5, 6)));
+     assert_eq!(it.next_back(), Some((4, 5)));
+     assert_eq!(it.next_back(), Some((3, 4)));
+     assert_eq!(it.next_back(), Some((2, 3)));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_zip() {
+     let xs = [1, 2, 3, 4, 5, 6];
+     let ys = [1, 2, 3, 7];
+     let a = xs.iter().cloned();
+     let b = ys.iter().cloned();
+     let mut it = a.zip(b);
+     assert_eq!(it.next(), Some((1, 1)));
+     assert_eq!(it.next(), Some((2, 2)));
+     assert_eq!(it.next_back(), Some((4, 7)));
+     assert_eq!(it.next_back(), Some((3, 3)));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_filter() {
+     let xs = [1, 2, 3, 4, 5, 6];
+     let mut it = xs.iter().filter(|&x| *x & 1 == 0);
+     assert_eq!(it.next_back().unwrap(), &6);
+     assert_eq!(it.next_back().unwrap(), &4);
+     assert_eq!(it.next().unwrap(), &2);
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_filter_map() {
+     let xs = [1, 2, 3, 4, 5, 6];
+     let mut it = xs.iter().filter_map(|&x| if x & 1 == 0 { Some(x * 2) } else { None });
+     assert_eq!(it.next_back().unwrap(), 12);
+     assert_eq!(it.next_back().unwrap(), 8);
+     assert_eq!(it.next().unwrap(), 4);
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_chain() {
+     let xs = [1, 2, 3, 4, 5];
+     let ys = [7, 9, 11];
+     let mut it = xs.iter().chain(&ys).rev();
+     assert_eq!(it.next().unwrap(), &11);
+     assert_eq!(it.next().unwrap(), &9);
+     assert_eq!(it.next_back().unwrap(), &1);
+     assert_eq!(it.next_back().unwrap(), &2);
+     assert_eq!(it.next_back().unwrap(), &3);
+     assert_eq!(it.next_back().unwrap(), &4);
+     assert_eq!(it.next_back().unwrap(), &5);
+     assert_eq!(it.next_back().unwrap(), &7);
+     assert_eq!(it.next_back(), None);
+ 
+     // test that .chain() is well behaved with an unfused iterator
+     struct CrazyIterator(bool);
+     impl CrazyIterator {
+         fn new() -> CrazyIterator {
+             CrazyIterator(false)
+         }
+     }
+     impl Iterator for CrazyIterator {
+         type Item = i32;
+         fn next(&mut self) -> Option<i32> {
+             if self.0 {
+                 Some(99)
+             } else {
+                 self.0 = true;
+                 None
+             }
+         }
+     }
+ 
+     impl DoubleEndedIterator for CrazyIterator {
+         fn next_back(&mut self) -> Option<i32> {
+             self.next()
+         }
+     }
+ 
+     assert_eq!(CrazyIterator::new().chain(0..10).rev().last(), Some(0));
+     assert!((0..10).chain(CrazyIterator::new()).rev().any(|i| i == 0));
+ }
+ 
+ #[test]
+ fn test_rposition() {
+     fn f(xy: &(isize, char)) -> bool {
+         let (_x, y) = *xy;
+         y == 'b'
+     }
+     fn g(xy: &(isize, char)) -> bool {
+         let (_x, y) = *xy;
+         y == 'd'
+     }
+     let v = [(0, 'a'), (1, 'b'), (2, 'c'), (3, 'b')];
+ 
+     assert_eq!(v.iter().rposition(f), Some(3));
+     assert!(v.iter().rposition(g).is_none());
+ }
+ 
+ #[test]
+ fn test_rev_rposition() {
+     let v = [0, 0, 1, 1];
+     assert_eq!(v.iter().rev().rposition(|&x| x == 1), Some(1));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_rposition_panic() {
+     let v: [(Box<_>, Box<_>); 4] = [(box 0, box 0), (box 0, box 0), (box 0, box 0), (box 0, box 0)];
+     let mut i = 0;
+     v.iter().rposition(|_elt| {
+         if i == 2 {
+             panic!()
+         }
+         i += 1;
+         false
+     });
+ }
+ 
+ #[test]
+ fn test_double_ended_flat_map() {
+     let u = [0, 1];
+     let v = [5, 6, 7, 8];
+     let mut it = u.iter().flat_map(|x| &v[*x..v.len()]);
+     assert_eq!(it.next_back().unwrap(), &8);
+     assert_eq!(it.next().unwrap(), &5);
+     assert_eq!(it.next_back().unwrap(), &7);
+     assert_eq!(it.next_back().unwrap(), &6);
+     assert_eq!(it.next_back().unwrap(), &8);
+     assert_eq!(it.next().unwrap(), &6);
+     assert_eq!(it.next_back().unwrap(), &7);
+     assert_eq!(it.next_back(), None);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_flatten() {
+     let u = [0, 1];
+     let v = [5, 6, 7, 8];
+     let mut it = u.iter().map(|x| &v[*x..v.len()]).flatten();
+     assert_eq!(it.next_back().unwrap(), &8);
+     assert_eq!(it.next().unwrap(), &5);
+     assert_eq!(it.next_back().unwrap(), &7);
+     assert_eq!(it.next_back().unwrap(), &6);
+     assert_eq!(it.next_back().unwrap(), &8);
+     assert_eq!(it.next().unwrap(), &6);
+     assert_eq!(it.next_back().unwrap(), &7);
+     assert_eq!(it.next_back(), None);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_double_ended_range() {
+     assert_eq!((11..14).rev().collect::<Vec<_>>(), [13, 12, 11]);
+     for _ in (10..0).rev() {
+         panic!("unreachable");
+     }
+ 
+     assert_eq!((11..14).rev().collect::<Vec<_>>(), [13, 12, 11]);
+     for _ in (10..0).rev() {
+         panic!("unreachable");
+     }
+ }
+ 
+ #[test]
+ fn test_range() {
+     assert_eq!((0..5).collect::<Vec<_>>(), [0, 1, 2, 3, 4]);
+     assert_eq!((-10..-1).collect::<Vec<_>>(), [-10, -9, -8, -7, -6, -5, -4, -3, -2]);
+     assert_eq!((0..5).rev().collect::<Vec<_>>(), [4, 3, 2, 1, 0]);
+     assert_eq!((200..-5).count(), 0);
+     assert_eq!((200..-5).rev().count(), 0);
+     assert_eq!((200..200).count(), 0);
+     assert_eq!((200..200).rev().count(), 0);
+ 
+     assert_eq!((0..100).size_hint(), (100, Some(100)));
+     // this test is only meaningful when sizeof usize < sizeof u64
+     assert_eq!((usize::MAX - 1..usize::MAX).size_hint(), (1, Some(1)));
+     assert_eq!((-10..-1).size_hint(), (9, Some(9)));
+     assert_eq!((-1..-10).size_hint(), (0, Some(0)));
+ 
+     assert_eq!((-70..58).size_hint(), (128, Some(128)));
+     assert_eq!((-128..127).size_hint(), (255, Some(255)));
+     assert_eq!(
+         (-2..isize::MAX).size_hint(),
+         (isize::MAX as usize + 2, Some(isize::MAX as usize + 2))
+     );
+ }
+ 
+ #[test]
+ fn test_char_range() {
+     use std::char;
+     // Miri is too slow
+     let from = if cfg!(miri) { char::from_u32(0xD800 - 10).unwrap() } else { '\0' };
+     let to = if cfg!(miri) { char::from_u32(0xDFFF + 10).unwrap() } else { char::MAX };
+     assert!((from..=to).eq((from as u32..=to as u32).filter_map(char::from_u32)));
+     assert!((from..=to).rev().eq((from as u32..=to as u32).filter_map(char::from_u32).rev()));
+ 
+     assert_eq!(('\u{D7FF}'..='\u{E000}').count(), 2);
+     assert_eq!(('\u{D7FF}'..='\u{E000}').size_hint(), (2, Some(2)));
+     assert_eq!(('\u{D7FF}'..'\u{E000}').count(), 1);
+     assert_eq!(('\u{D7FF}'..'\u{E000}').size_hint(), (1, Some(1)));
+ }
+ 
+ #[test]
+ fn test_range_exhaustion() {
+     let mut r = 10..10;
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+     assert_eq!(r.next_back(), None);
+     assert_eq!(r, 10..10);
+ 
+     let mut r = 10..12;
+     assert_eq!(r.next(), Some(10));
+     assert_eq!(r.next(), Some(11));
+     assert!(r.is_empty());
+     assert_eq!(r, 12..12);
+     assert_eq!(r.next(), None);
+ 
+     let mut r = 10..12;
+     assert_eq!(r.next_back(), Some(11));
+     assert_eq!(r.next_back(), Some(10));
+     assert!(r.is_empty());
+     assert_eq!(r, 10..10);
+     assert_eq!(r.next_back(), None);
+ 
+     let mut r = 100..10;
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+     assert_eq!(r.next_back(), None);
+     assert_eq!(r, 100..10);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_exhaustion() {
+     let mut r = 10..=10;
+     assert_eq!(r.next(), Some(10));
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+     assert_eq!(r.next(), None);
+ 
+     assert_eq!(*r.start(), 10);
+     assert_eq!(*r.end(), 10);
+     assert_ne!(r, 10..=10);
+ 
+     let mut r = 10..=10;
+     assert_eq!(r.next_back(), Some(10));
+     assert!(r.is_empty());
+     assert_eq!(r.next_back(), None);
+ 
+     assert_eq!(*r.start(), 10);
+     assert_eq!(*r.end(), 10);
+     assert_ne!(r, 10..=10);
+ 
+     let mut r = 10..=12;
+     assert_eq!(r.next(), Some(10));
+     assert_eq!(r.next(), Some(11));
+     assert_eq!(r.next(), Some(12));
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+ 
+     let mut r = 10..=12;
+     assert_eq!(r.next_back(), Some(12));
+     assert_eq!(r.next_back(), Some(11));
+     assert_eq!(r.next_back(), Some(10));
+     assert!(r.is_empty());
+     assert_eq!(r.next_back(), None);
+ 
+     let mut r = 10..=12;
+     assert_eq!(r.nth(2), Some(12));
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+ 
+     let mut r = 10..=12;
+     assert_eq!(r.nth(5), None);
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+ 
+     let mut r = 100..=10;
+     assert_eq!(r.next(), None);
+     assert!(r.is_empty());
+     assert_eq!(r.next(), None);
+     assert_eq!(r.next(), None);
+     assert_eq!(r, 100..=10);
+ 
+     let mut r = 100..=10;
+     assert_eq!(r.next_back(), None);
+     assert!(r.is_empty());
+     assert_eq!(r.next_back(), None);
+     assert_eq!(r.next_back(), None);
+     assert_eq!(r, 100..=10);
+ }
+ 
+ #[test]
+ fn test_range_nth() {
+     assert_eq!((10..15).nth(0), Some(10));
+     assert_eq!((10..15).nth(1), Some(11));
+     assert_eq!((10..15).nth(4), Some(14));
+     assert_eq!((10..15).nth(5), None);
+ 
+     let mut r = 10..20;
+     assert_eq!(r.nth(2), Some(12));
+     assert_eq!(r, 13..20);
+     assert_eq!(r.nth(2), Some(15));
+     assert_eq!(r, 16..20);
+     assert_eq!(r.nth(10), None);
+     assert_eq!(r, 20..20);
+ }
+ 
+ #[test]
+ fn test_range_nth_back() {
+     assert_eq!((10..15).nth_back(0), Some(14));
+     assert_eq!((10..15).nth_back(1), Some(13));
+     assert_eq!((10..15).nth_back(4), Some(10));
+     assert_eq!((10..15).nth_back(5), None);
+     assert_eq!((-120..80_i8).nth_back(199), Some(-120));
+ 
+     let mut r = 10..20;
+     assert_eq!(r.nth_back(2), Some(17));
+     assert_eq!(r, 10..17);
+     assert_eq!(r.nth_back(2), Some(14));
+     assert_eq!(r, 10..14);
+     assert_eq!(r.nth_back(10), None);
+     assert_eq!(r, 10..10);
+ }
+ 
+ #[test]
+ fn test_range_from_nth() {
+     assert_eq!((10..).nth(0), Some(10));
+     assert_eq!((10..).nth(1), Some(11));
+     assert_eq!((10..).nth(4), Some(14));
+ 
+     let mut r = 10..;
+     assert_eq!(r.nth(2), Some(12));
+     assert_eq!(r, 13..);
+     assert_eq!(r.nth(2), Some(15));
+     assert_eq!(r, 16..);
+     assert_eq!(r.nth(10), Some(26));
+     assert_eq!(r, 27..);
+ 
+     assert_eq!((0..).size_hint(), (usize::MAX, None));
+ }
+ 
+ fn is_trusted_len<I: TrustedLen>(_: I) {}
+ 
+ #[test]
+ fn test_range_from_take() {
+     let mut it = (0..).take(3);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.next(), Some(1));
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(it.next(), None);
+     is_trusted_len((0..).take(3));
+     assert_eq!((0..).take(3).size_hint(), (3, Some(3)));
+     assert_eq!((0..).take(0).size_hint(), (0, Some(0)));
+     assert_eq!((0..).take(usize::MAX).size_hint(), (usize::MAX, Some(usize::MAX)));
+ }
+ 
+ #[test]
+ fn test_range_from_take_collect() {
+     let v: Vec<_> = (0..).take(3).collect();
+     assert_eq!(v, vec![0, 1, 2]);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_nth() {
+     assert_eq!((10..=15).nth(0), Some(10));
+     assert_eq!((10..=15).nth(1), Some(11));
+     assert_eq!((10..=15).nth(5), Some(15));
+     assert_eq!((10..=15).nth(6), None);
+ 
+     let mut exhausted_via_next = 10_u8..=20;
+     while exhausted_via_next.next().is_some() {}
+ 
+     let mut r = 10_u8..=20;
+     assert_eq!(r.nth(2), Some(12));
+     assert_eq!(r, 13..=20);
+     assert_eq!(r.nth(2), Some(15));
+     assert_eq!(r, 16..=20);
+     assert_eq!(r.is_empty(), false);
+     assert_eq!(ExactSizeIterator::is_empty(&r), false);
+     assert_eq!(r.nth(10), None);
+     assert_eq!(r.is_empty(), true);
+     assert_eq!(r, exhausted_via_next);
+     assert_eq!(ExactSizeIterator::is_empty(&r), true);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_nth_back() {
+     assert_eq!((10..=15).nth_back(0), Some(15));
+     assert_eq!((10..=15).nth_back(1), Some(14));
+     assert_eq!((10..=15).nth_back(5), Some(10));
+     assert_eq!((10..=15).nth_back(6), None);
+     assert_eq!((-120..=80_i8).nth_back(200), Some(-120));
+ 
+     let mut exhausted_via_next_back = 10_u8..=20;
+     while exhausted_via_next_back.next_back().is_some() {}
+ 
+     let mut r = 10_u8..=20;
+     assert_eq!(r.nth_back(2), Some(18));
+     assert_eq!(r, 10..=17);
+     assert_eq!(r.nth_back(2), Some(15));
+     assert_eq!(r, 10..=14);
+     assert_eq!(r.is_empty(), false);
+     assert_eq!(ExactSizeIterator::is_empty(&r), false);
+     assert_eq!(r.nth_back(10), None);
+     assert_eq!(r.is_empty(), true);
+     assert_eq!(r, exhausted_via_next_back);
+     assert_eq!(ExactSizeIterator::is_empty(&r), true);
+ }
+ 
+ #[test]
+ fn test_range_len() {
+     assert_eq!((0..10_u8).len(), 10);
+     assert_eq!((9..10_u8).len(), 1);
+     assert_eq!((10..10_u8).len(), 0);
+     assert_eq!((11..10_u8).len(), 0);
+     assert_eq!((100..10_u8).len(), 0);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_len() {
+     assert_eq!((0..=10_u8).len(), 11);
+     assert_eq!((9..=10_u8).len(), 2);
+     assert_eq!((10..=10_u8).len(), 1);
+     assert_eq!((11..=10_u8).len(), 0);
+     assert_eq!((100..=10_u8).len(), 0);
+ }
+ 
+ #[test]
+ fn test_range_step() {
+     #![allow(deprecated)]
+ 
+     assert_eq!((0..20).step_by(5).collect::<Vec<isize>>(), [0, 5, 10, 15]);
+     assert_eq!((1..21).rev().step_by(5).collect::<Vec<isize>>(), [20, 15, 10, 5]);
+     assert_eq!((1..21).rev().step_by(6).collect::<Vec<isize>>(), [20, 14, 8, 2]);
+     assert_eq!((200..255).step_by(50).collect::<Vec<u8>>(), [200, 250]);
+     assert_eq!((200..-5).step_by(1).collect::<Vec<isize>>(), []);
+     assert_eq!((200..200).step_by(1).collect::<Vec<isize>>(), []);
+ 
+     assert_eq!((0..20).step_by(1).size_hint(), (20, Some(20)));
+     assert_eq!((0..20).step_by(21).size_hint(), (1, Some(1)));
+     assert_eq!((0..20).step_by(5).size_hint(), (4, Some(4)));
+     assert_eq!((1..21).rev().step_by(5).size_hint(), (4, Some(4)));
+     assert_eq!((1..21).rev().step_by(6).size_hint(), (4, Some(4)));
+     assert_eq!((20..-5).step_by(1).size_hint(), (0, Some(0)));
+     assert_eq!((20..20).step_by(1).size_hint(), (0, Some(0)));
+     assert_eq!((i8::MIN..i8::MAX).step_by(-(i8::MIN as i32) as usize).size_hint(), (2, Some(2)));
+     assert_eq!((i16::MIN..i16::MAX).step_by(i16::MAX as usize).size_hint(), (3, Some(3)));
+     assert_eq!((isize::MIN..isize::MAX).step_by(1).size_hint(), (usize::MAX, Some(usize::MAX)));
+ }
+ 
+ #[test]
+ fn test_step_by_skip() {
+     assert_eq!((0..640).step_by(128).skip(1).collect::<Vec<_>>(), [128, 256, 384, 512]);
+     assert_eq!((0..=50).step_by(10).nth(3), Some(30));
+     assert_eq!((200..=255u8).step_by(10).nth(3), Some(230));
+ }
+ 
+ #[test]
+ fn test_range_inclusive_step() {
+     assert_eq!((0..=50).step_by(10).collect::<Vec<_>>(), [0, 10, 20, 30, 40, 50]);
+     assert_eq!((0..=5).step_by(1).collect::<Vec<_>>(), [0, 1, 2, 3, 4, 5]);
+     assert_eq!((200..=255u8).step_by(10).collect::<Vec<_>>(), [200, 210, 220, 230, 240, 250]);
+     assert_eq!((250..=255u8).step_by(1).collect::<Vec<_>>(), [250, 251, 252, 253, 254, 255]);
+ }
+ 
+ #[test]
+ fn test_range_last_max() {
+     assert_eq!((0..20).last(), Some(19));
+     assert_eq!((-20..0).last(), Some(-1));
+     assert_eq!((5..5).last(), None);
+ 
+     assert_eq!((0..20).max(), Some(19));
+     assert_eq!((-20..0).max(), Some(-1));
+     assert_eq!((5..5).max(), None);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_last_max() {
+     assert_eq!((0..=20).last(), Some(20));
+     assert_eq!((-20..=0).last(), Some(0));
+     assert_eq!((5..=5).last(), Some(5));
+     let mut r = 10..=10;
+     r.next();
+     assert_eq!(r.last(), None);
+ 
+     assert_eq!((0..=20).max(), Some(20));
+     assert_eq!((-20..=0).max(), Some(0));
+     assert_eq!((5..=5).max(), Some(5));
+     let mut r = 10..=10;
+     r.next();
+     assert_eq!(r.max(), None);
+ }
+ 
+ #[test]
+ fn test_range_min() {
+     assert_eq!((0..20).min(), Some(0));
+     assert_eq!((-20..0).min(), Some(-20));
+     assert_eq!((5..5).min(), None);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_min() {
+     assert_eq!((0..=20).min(), Some(0));
+     assert_eq!((-20..=0).min(), Some(-20));
+     assert_eq!((5..=5).min(), Some(5));
+     let mut r = 10..=10;
+     r.next();
+     assert_eq!(r.min(), None);
+ }
+ 
+ #[test]
+ fn test_range_inclusive_folds() {
+     assert_eq!((1..=10).sum::<i32>(), 55);
+     assert_eq!((1..=10).rev().sum::<i32>(), 55);
+ 
+     let mut it = 44..=50;
+     assert_eq!(it.try_fold(0, i8::checked_add), None);
+     assert_eq!(it, 47..=50);
+     assert_eq!(it.try_fold(0, i8::checked_add), None);
+     assert_eq!(it, 50..=50);
+     assert_eq!(it.try_fold(0, i8::checked_add), Some(50));
+     assert!(it.is_empty());
+     assert_eq!(it.try_fold(0, i8::checked_add), Some(0));
+     assert!(it.is_empty());
+ 
+     let mut it = 40..=47;
+     assert_eq!(it.try_rfold(0, i8::checked_add), None);
+     assert_eq!(it, 40..=44);
+     assert_eq!(it.try_rfold(0, i8::checked_add), None);
+     assert_eq!(it, 40..=41);
+     assert_eq!(it.try_rfold(0, i8::checked_add), Some(81));
+     assert!(it.is_empty());
+     assert_eq!(it.try_rfold(0, i8::checked_add), Some(0));
+     assert!(it.is_empty());
+ 
+     let mut it = 10..=20;
+     assert_eq!(it.try_fold(0, |a, b| Some(a + b)), Some(165));
+     assert!(it.is_empty());
+     assert_eq!(it.try_fold(0, |a, b| Some(a + b)), Some(0));
+     assert!(it.is_empty());
+ 
+     let mut it = 10..=20;
+     assert_eq!(it.try_rfold(0, |a, b| Some(a + b)), Some(165));
+     assert!(it.is_empty());
+     assert_eq!(it.try_rfold(0, |a, b| Some(a + b)), Some(0));
+     assert!(it.is_empty());
+ }
+ 
+ #[test]
+ fn test_range_size_hint() {
+     assert_eq!((0..0usize).size_hint(), (0, Some(0)));
+     assert_eq!((0..100usize).size_hint(), (100, Some(100)));
+     assert_eq!((0..usize::MAX).size_hint(), (usize::MAX, Some(usize::MAX)));
+ 
+     let umax = u128::try_from(usize::MAX).unwrap();
+     assert_eq!((0..0u128).size_hint(), (0, Some(0)));
+     assert_eq!((0..100u128).size_hint(), (100, Some(100)));
+     assert_eq!((0..umax).size_hint(), (usize::MAX, Some(usize::MAX)));
+     assert_eq!((0..umax + 1).size_hint(), (usize::MAX, None));
+ 
+     assert_eq!((0..0isize).size_hint(), (0, Some(0)));
+     assert_eq!((-100..100isize).size_hint(), (200, Some(200)));
+     assert_eq!((isize::MIN..isize::MAX).size_hint(), (usize::MAX, Some(usize::MAX)));
+ 
+     let imin = i128::try_from(isize::MIN).unwrap();
+     let imax = i128::try_from(isize::MAX).unwrap();
+     assert_eq!((0..0i128).size_hint(), (0, Some(0)));
+     assert_eq!((-100..100i128).size_hint(), (200, Some(200)));
+     assert_eq!((imin..imax).size_hint(), (usize::MAX, Some(usize::MAX)));
+     assert_eq!((imin..imax + 1).size_hint(), (usize::MAX, None));
+ }
+ 
+ #[test]
+ fn test_range_inclusive_size_hint() {
+     assert_eq!((1..=0usize).size_hint(), (0, Some(0)));
+     assert_eq!((0..=0usize).size_hint(), (1, Some(1)));
+     assert_eq!((0..=100usize).size_hint(), (101, Some(101)));
+     assert_eq!((0..=usize::MAX - 1).size_hint(), (usize::MAX, Some(usize::MAX)));
+     assert_eq!((0..=usize::MAX).size_hint(), (usize::MAX, None));
+ 
+     let umax = u128::try_from(usize::MAX).unwrap();
+     assert_eq!((1..=0u128).size_hint(), (0, Some(0)));
+     assert_eq!((0..=0u128).size_hint(), (1, Some(1)));
+     assert_eq!((0..=100u128).size_hint(), (101, Some(101)));
+     assert_eq!((0..=umax - 1).size_hint(), (usize::MAX, Some(usize::MAX)));
+     assert_eq!((0..=umax).size_hint(), (usize::MAX, None));
+     assert_eq!((0..=umax + 1).size_hint(), (usize::MAX, None));
+ 
+     assert_eq!((0..=-1isize).size_hint(), (0, Some(0)));
+     assert_eq!((0..=0isize).size_hint(), (1, Some(1)));
+     assert_eq!((-100..=100isize).size_hint(), (201, Some(201)));
+     assert_eq!((isize::MIN..=isize::MAX - 1).size_hint(), (usize::MAX, Some(usize::MAX)));
+     assert_eq!((isize::MIN..=isize::MAX).size_hint(), (usize::MAX, None));
+ 
+     let imin = i128::try_from(isize::MIN).unwrap();
+     let imax = i128::try_from(isize::MAX).unwrap();
+     assert_eq!((0..=-1i128).size_hint(), (0, Some(0)));
+     assert_eq!((0..=0i128).size_hint(), (1, Some(1)));
+     assert_eq!((-100..=100i128).size_hint(), (201, Some(201)));
+     assert_eq!((imin..=imax - 1).size_hint(), (usize::MAX, Some(usize::MAX)));
+     assert_eq!((imin..=imax).size_hint(), (usize::MAX, None));
+     assert_eq!((imin..=imax + 1).size_hint(), (usize::MAX, None));
+ }
+ 
+ #[test]
+ fn test_repeat() {
+     let mut it = repeat(42);
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(repeat(42).size_hint(), (usize::MAX, None));
+ }
+ 
+ #[test]
+ fn test_repeat_take() {
+     let mut it = repeat(42).take(3);
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), None);
+     is_trusted_len(repeat(42).take(3));
+     assert_eq!(repeat(42).take(3).size_hint(), (3, Some(3)));
+     assert_eq!(repeat(42).take(0).size_hint(), (0, Some(0)));
+     assert_eq!(repeat(42).take(usize::MAX).size_hint(), (usize::MAX, Some(usize::MAX)));
+ }
+ 
+ #[test]
+ fn test_repeat_take_collect() {
+     let v: Vec<_> = repeat(42).take(3).collect();
+     assert_eq!(v, vec![42, 42, 42]);
+ }
+ 
+ #[test]
+ fn test_repeat_with() {
+     #[derive(PartialEq, Debug)]
+     struct NotClone(usize);
+     let mut it = repeat_with(|| NotClone(42));
+     assert_eq!(it.next(), Some(NotClone(42)));
+     assert_eq!(it.next(), Some(NotClone(42)));
+     assert_eq!(it.next(), Some(NotClone(42)));
+     assert_eq!(repeat_with(|| NotClone(42)).size_hint(), (usize::MAX, None));
+ }
+ 
+ #[test]
+ fn test_repeat_with_take() {
+     let mut it = repeat_with(|| 42).take(3);
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), None);
+     is_trusted_len(repeat_with(|| 42).take(3));
+     assert_eq!(repeat_with(|| 42).take(3).size_hint(), (3, Some(3)));
+     assert_eq!(repeat_with(|| 42).take(0).size_hint(), (0, Some(0)));
+     assert_eq!(repeat_with(|| 42).take(usize::MAX).size_hint(), (usize::MAX, Some(usize::MAX)));
+ }
+ 
+ #[test]
+ fn test_repeat_with_take_collect() {
+     let mut curr = 1;
+     let v: Vec<_> = repeat_with(|| {
+         let tmp = curr;
+         curr *= 2;
+         tmp
+     })
+     .take(5)
+     .collect();
+     assert_eq!(v, vec![1, 2, 4, 8, 16]);
+ }
+ 
+ #[test]
+ fn test_successors() {
+     let mut powers_of_10 = successors(Some(1_u16), |n| n.checked_mul(10));
+     assert_eq!(powers_of_10.by_ref().collect::<Vec<_>>(), &[1, 10, 100, 1_000, 10_000]);
+     assert_eq!(powers_of_10.next(), None);
+ 
+     let mut empty = successors(None::<u32>, |_| unimplemented!());
+     assert_eq!(empty.next(), None);
+     assert_eq!(empty.next(), None);
+ }
+ 
+ #[test]
+ fn test_fuse() {
+     let mut it = 0..3;
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.next(), Some(0));
+     assert_eq!(it.len(), 2);
+     assert_eq!(it.next(), Some(1));
+     assert_eq!(it.len(), 1);
+     assert_eq!(it.next(), Some(2));
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.next(), None);
+     assert_eq!(it.len(), 0);
+ }
+ 
+ #[test]
+ fn test_fuse_nth() {
+     let xs = [0, 1, 2];
+     let mut it = xs.iter();
+ 
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.nth(2), Some(&2));
+     assert_eq!(it.len(), 0);
+     assert_eq!(it.nth(2), None);
+     assert_eq!(it.len(), 0);
+ }
+ 
+ #[test]
+ fn test_fuse_last() {
+     let xs = [0, 1, 2];
+     let it = xs.iter();
+ 
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.last(), Some(&2));
+ }
+ 
+ #[test]
+ fn test_fuse_count() {
+     let xs = [0, 1, 2];
+     let it = xs.iter();
+ 
+     assert_eq!(it.len(), 3);
+     assert_eq!(it.count(), 3);
+     // Can't check len now because count consumes.
+ }
+ 
+ #[test]
+ fn test_fuse_fold() {
+     let xs = [0, 1, 2];
+     let it = xs.iter(); // `FusedIterator`
+     let i = it.fuse().fold(0, |i, &x| {
+         assert_eq!(x, xs[i]);
+         i + 1
+     });
+     assert_eq!(i, xs.len());
+ 
+     let it = xs.iter(); // `FusedIterator`
+     let i = it.fuse().rfold(xs.len(), |i, &x| {
+         assert_eq!(x, xs[i - 1]);
+         i - 1
+     });
+     assert_eq!(i, 0);
+ 
+     let it = xs.iter().scan((), |_, &x| Some(x)); // `!FusedIterator`
+     let i = it.fuse().fold(0, |i, x| {
+         assert_eq!(x, xs[i]);
+         i + 1
+     });
+     assert_eq!(i, xs.len());
+ }
+ 
+ #[test]
+ fn test_once() {
+     let mut it = once(42);
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_once_with() {
+     let count = Cell::new(0);
+     let mut it = once_with(|| {
+         count.set(count.get() + 1);
+         42
+     });
+ 
+     assert_eq!(count.get(), 0);
+     assert_eq!(it.next(), Some(42));
+     assert_eq!(count.get(), 1);
+     assert_eq!(it.next(), None);
+     assert_eq!(count.get(), 1);
+     assert_eq!(it.next(), None);
+     assert_eq!(count.get(), 1);
+ }
+ 
+ #[test]
+ fn test_empty() {
+     let mut it = empty::<i32>();
+     assert_eq!(it.next(), None);
+ }
+ 
+ #[test]
+ fn test_chain_fold() {
+     let xs = [1, 2, 3];
+     let ys = [1, 2, 0];
+ 
+     let mut iter = xs.iter().chain(&ys);
+     iter.next();
+     let mut result = Vec::new();
+     iter.fold((), |(), &elt| result.push(elt));
+     assert_eq!(&[2, 3, 1, 2, 0], &result[..]);
+ }
+ 
+ #[test]
+ fn test_steps_between() {
+     assert_eq!(Step::steps_between(&20_u8, &200_u8), Some(180_usize));
+     assert_eq!(Step::steps_between(&-20_i8, &80_i8), Some(100_usize));
+     assert_eq!(Step::steps_between(&-120_i8, &80_i8), Some(200_usize));
+     assert_eq!(Step::steps_between(&20_u32, &4_000_100_u32), Some(4_000_080_usize));
+     assert_eq!(Step::steps_between(&-20_i32, &80_i32), Some(100_usize));
+     assert_eq!(Step::steps_between(&-2_000_030_i32, &2_000_050_i32), Some(4_000_080_usize));
+ 
+     // Skip u64/i64 to avoid differences with 32-bit vs 64-bit platforms
+ 
+     assert_eq!(Step::steps_between(&20_u128, &200_u128), Some(180_usize));
+     assert_eq!(Step::steps_between(&-20_i128, &80_i128), Some(100_usize));
+     if cfg!(target_pointer_width = "64") {
+         assert_eq!(Step::steps_between(&10_u128, &0x1_0000_0000_0000_0009_u128), Some(usize::MAX));
+     }
+     assert_eq!(Step::steps_between(&10_u128, &0x1_0000_0000_0000_000a_u128), None);
+     assert_eq!(Step::steps_between(&10_i128, &0x1_0000_0000_0000_000a_i128), None);
+     assert_eq!(
+         Step::steps_between(&-0x1_0000_0000_0000_0000_i128, &0x1_0000_0000_0000_0000_i128,),
+         None,
+     );
+ }
+ 
+ #[test]
+ fn test_step_forward() {
+     assert_eq!(Step::forward_checked(55_u8, 200_usize), Some(255_u8));
+     assert_eq!(Step::forward_checked(252_u8, 200_usize), None);
+     assert_eq!(Step::forward_checked(0_u8, 256_usize), None);
+     assert_eq!(Step::forward_checked(-110_i8, 200_usize), Some(90_i8));
+     assert_eq!(Step::forward_checked(-110_i8, 248_usize), None);
+     assert_eq!(Step::forward_checked(-126_i8, 256_usize), None);
+ 
+     assert_eq!(Step::forward_checked(35_u16, 100_usize), Some(135_u16));
+     assert_eq!(Step::forward_checked(35_u16, 65500_usize), Some(u16::MAX));
+     assert_eq!(Step::forward_checked(36_u16, 65500_usize), None);
+     assert_eq!(Step::forward_checked(-110_i16, 200_usize), Some(90_i16));
+     assert_eq!(Step::forward_checked(-20_030_i16, 50_050_usize), Some(30_020_i16));
+     assert_eq!(Step::forward_checked(-10_i16, 40_000_usize), None);
+     assert_eq!(Step::forward_checked(-10_i16, 70_000_usize), None);
+ 
+     assert_eq!(Step::forward_checked(10_u128, 70_000_usize), Some(70_010_u128));
+     assert_eq!(Step::forward_checked(10_i128, 70_030_usize), Some(70_040_i128));
+     assert_eq!(
+         Step::forward_checked(0xffff_ffff_ffff_ffff__ffff_ffff_ffff_ff00_u128, 0xff_usize),
+         Some(u128::MAX),
+     );
+     assert_eq!(
+         Step::forward_checked(0xffff_ffff_ffff_ffff__ffff_ffff_ffff_ff00_u128, 0x100_usize),
+         None
+     );
+     assert_eq!(
+         Step::forward_checked(0x7fff_ffff_ffff_ffff__ffff_ffff_ffff_ff00_i128, 0xff_usize),
+         Some(i128::MAX),
+     );
+     assert_eq!(
+         Step::forward_checked(0x7fff_ffff_ffff_ffff__ffff_ffff_ffff_ff00_i128, 0x100_usize),
+         None
+     );
+ }
+ 
+ #[test]
+ fn test_step_backward() {
+     assert_eq!(Step::backward_checked(255_u8, 200_usize), Some(55_u8));
+     assert_eq!(Step::backward_checked(100_u8, 200_usize), None);
+     assert_eq!(Step::backward_checked(255_u8, 256_usize), None);
+     assert_eq!(Step::backward_checked(90_i8, 200_usize), Some(-110_i8));
+     assert_eq!(Step::backward_checked(110_i8, 248_usize), None);
+     assert_eq!(Step::backward_checked(127_i8, 256_usize), None);
+ 
+     assert_eq!(Step::backward_checked(135_u16, 100_usize), Some(35_u16));
+     assert_eq!(Step::backward_checked(u16::MAX, 65500_usize), Some(35_u16));
+     assert_eq!(Step::backward_checked(10_u16, 11_usize), None);
+     assert_eq!(Step::backward_checked(90_i16, 200_usize), Some(-110_i16));
+     assert_eq!(Step::backward_checked(30_020_i16, 50_050_usize), Some(-20_030_i16));
+     assert_eq!(Step::backward_checked(-10_i16, 40_000_usize), None);
+     assert_eq!(Step::backward_checked(-10_i16, 70_000_usize), None);
+ 
+     assert_eq!(Step::backward_checked(70_010_u128, 70_000_usize), Some(10_u128));
+     assert_eq!(Step::backward_checked(70_020_i128, 70_030_usize), Some(-10_i128));
+     assert_eq!(Step::backward_checked(10_u128, 7_usize), Some(3_u128));
+     assert_eq!(Step::backward_checked(10_u128, 11_usize), None);
+     assert_eq!(
+         Step::backward_checked(-0x7fff_ffff_ffff_ffff__ffff_ffff_ffff_ff00_i128, 0x100_usize),
+         Some(i128::MIN)
+     );
+ }
+ 
+ #[test]
+ fn test_rev_try_folds() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((1..10).rev().try_fold(7, f), (1..10).try_rfold(7, f));
+     assert_eq!((1..10).rev().try_rfold(7, f), (1..10).try_fold(7, f));
+ 
+     let a = [10, 20, 30, 40, 100, 60, 70, 80, 90];
+     let mut iter = a.iter().rev();
+     assert_eq!(iter.try_fold(0_i8, |acc, &x| acc.checked_add(x)), None);
+     assert_eq!(iter.next(), Some(&70));
+     let mut iter = a.iter().rev();
+     assert_eq!(iter.try_rfold(0_i8, |acc, &x| acc.checked_add(x)), None);
+     assert_eq!(iter.next_back(), Some(&60));
+ }
+ 
+ #[test]
+ fn test_cloned_try_folds() {
+     let a = [1, 2, 3, 4, 5, 6, 7, 8, 9];
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     let f_ref = &|acc, &x| i32::checked_add(2 * acc, x);
+     assert_eq!(a.iter().cloned().try_fold(7, f), a.iter().try_fold(7, f_ref));
+     assert_eq!(a.iter().cloned().try_rfold(7, f), a.iter().try_rfold(7, f_ref));
+ 
+     let a = [10, 20, 30, 40, 100, 60, 70, 80, 90];
+     let mut iter = a.iter().cloned();
+     assert_eq!(iter.try_fold(0_i8, |acc, x| acc.checked_add(x)), None);
+     assert_eq!(iter.next(), Some(60));
+     let mut iter = a.iter().cloned();
+     assert_eq!(iter.try_rfold(0_i8, |acc, x| acc.checked_add(x)), None);
+     assert_eq!(iter.next_back(), Some(70));
+ }
+ 
+ #[test]
+ fn test_chain_try_folds() {
+     let c = || (0..10).chain(10..20);
+ 
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!(c().try_fold(7, f), (0..20).try_fold(7, f));
+     assert_eq!(c().try_rfold(7, f), (0..20).rev().try_fold(7, f));
+ 
+     let mut iter = c();
+     assert_eq!(iter.position(|x| x == 5), Some(5));
+     assert_eq!(iter.next(), Some(6), "stopped in front, state Both");
+     assert_eq!(iter.position(|x| x == 13), Some(6));
+     assert_eq!(iter.next(), Some(14), "stopped in back, state Back");
+     assert_eq!(iter.try_fold(0, |acc, x| Some(acc + x)), Some((15..20).sum()));
+ 
+     let mut iter = c().rev(); // use rev to access try_rfold
+     assert_eq!(iter.position(|x| x == 15), Some(4));
+     assert_eq!(iter.next(), Some(14), "stopped in back, state Both");
+     assert_eq!(iter.position(|x| x == 5), Some(8));
+     assert_eq!(iter.next(), Some(4), "stopped in front, state Front");
+     assert_eq!(iter.try_fold(0, |acc, x| Some(acc + x)), Some((0..4).sum()));
+ 
+     let mut iter = c();
+     iter.by_ref().rev().nth(14); // skip the last 15, ending in state Front
+     assert_eq!(iter.try_fold(7, f), (0..5).try_fold(7, f));
+ 
+     let mut iter = c();
+     iter.nth(14); // skip the first 15, ending in state Back
+     assert_eq!(iter.try_rfold(7, f), (15..20).try_rfold(7, f));
+ }
+ 
+ #[test]
+ fn test_map_try_folds() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((0..10).map(|x| x + 3).try_fold(7, f), (3..13).try_fold(7, f));
+     assert_eq!((0..10).map(|x| x + 3).try_rfold(7, f), (3..13).try_rfold(7, f));
+ 
+     let mut iter = (0..40).map(|x| x + 10);
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(20));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(46));
+ }
+ 
+ #[test]
+ fn test_filter_try_folds() {
+     fn p(&x: &i32) -> bool {
+         0 <= x && x < 10
+     }
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((-10..20).filter(p).try_fold(7, f), (0..10).try_fold(7, f));
+     assert_eq!((-10..20).filter(p).try_rfold(7, f), (0..10).try_rfold(7, f));
+ 
+     let mut iter = (0..40).filter(|&x| x % 2 == 1);
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(25));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(31));
+ }
+ 
+ #[test]
+ fn test_filter_map_try_folds() {
+     let mp = &|x| if 0 <= x && x < 10 { Some(x * 2) } else { None };
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((-9..20).filter_map(mp).try_fold(7, f), (0..10).map(|x| 2 * x).try_fold(7, f));
+     assert_eq!((-9..20).filter_map(mp).try_rfold(7, f), (0..10).map(|x| 2 * x).try_rfold(7, f));
+ 
+     let mut iter = (0..40).filter_map(|x| if x % 2 == 1 { None } else { Some(x * 2 + 10) });
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(38));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(78));
+ }
+ 
+ #[test]
+ fn test_enumerate_try_folds() {
+     let f = &|acc, (i, x)| usize::checked_add(2 * acc, x / (i + 1) + i);
+     assert_eq!((9..18).enumerate().try_fold(7, f), (0..9).map(|i| (i, i + 9)).try_fold(7, f));
+     assert_eq!((9..18).enumerate().try_rfold(7, f), (0..9).map(|i| (i, i + 9)).try_rfold(7, f));
+ 
+     let mut iter = (100..200).enumerate();
+     let f = &|acc, (i, x)| u8::checked_add(acc, u8::checked_div(x, i as u8 + 1)?);
+     assert_eq!(iter.try_fold(0, f), None);
+     assert_eq!(iter.next(), Some((7, 107)));
+     assert_eq!(iter.try_rfold(0, f), None);
+     assert_eq!(iter.next_back(), Some((11, 111)));
+ }
+ 
+ #[test]
+ fn test_peek_try_folds() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+ 
+     assert_eq!((1..20).peekable().try_fold(7, f), (1..20).try_fold(7, f));
+     assert_eq!((1..20).peekable().try_rfold(7, f), (1..20).try_rfold(7, f));
+ 
+     let mut iter = (1..20).peekable();
+     assert_eq!(iter.peek(), Some(&1));
+     assert_eq!(iter.try_fold(7, f), (1..20).try_fold(7, f));
+ 
+     let mut iter = (1..20).peekable();
+     assert_eq!(iter.peek(), Some(&1));
+     assert_eq!(iter.try_rfold(7, f), (1..20).try_rfold(7, f));
+ 
+     let mut iter = [100, 20, 30, 40, 50, 60, 70].iter().cloned().peekable();
+     assert_eq!(iter.peek(), Some(&100));
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.peek(), Some(&40));
+ 
+     let mut iter = [100, 20, 30, 40, 50, 60, 70].iter().cloned().peekable();
+     assert_eq!(iter.peek(), Some(&100));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.peek(), Some(&100));
+     assert_eq!(iter.next_back(), Some(50));
+ 
+     let mut iter = (2..5).peekable();
+     assert_eq!(iter.peek(), Some(&2));
+     assert_eq!(iter.try_for_each(Err), Err(2));
+     assert_eq!(iter.peek(), Some(&3));
+     assert_eq!(iter.try_for_each(Err), Err(3));
+     assert_eq!(iter.peek(), Some(&4));
+     assert_eq!(iter.try_for_each(Err), Err(4));
+     assert_eq!(iter.peek(), None);
+     assert_eq!(iter.try_for_each(Err), Ok(()));
+ 
+     let mut iter = (2..5).peekable();
+     assert_eq!(iter.peek(), Some(&2));
+     assert_eq!(iter.try_rfold((), |(), x| Err(x)), Err(4));
+     assert_eq!(iter.peek(), Some(&2));
+     assert_eq!(iter.try_rfold((), |(), x| Err(x)), Err(3));
+     assert_eq!(iter.peek(), Some(&2));
+     assert_eq!(iter.try_rfold((), |(), x| Err(x)), Err(2));
+     assert_eq!(iter.peek(), None);
+     assert_eq!(iter.try_rfold((), |(), x| Err(x)), Ok(()));
+ }
+ 
+ #[test]
+ fn test_skip_while_try_fold() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     fn p(&x: &i32) -> bool {
+         (x % 10) <= 5
+     }
+     assert_eq!((1..20).skip_while(p).try_fold(7, f), (6..20).try_fold(7, f));
+     let mut iter = (1..20).skip_while(p);
+     assert_eq!(iter.nth(5), Some(11));
+     assert_eq!(iter.try_fold(7, f), (12..20).try_fold(7, f));
+ 
+     let mut iter = (0..50).skip_while(|&x| (x % 20) < 15);
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(23));
+ }
+ 
+ #[test]
+ fn test_take_while_folds() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((1..20).take_while(|&x| x != 10).try_fold(7, f), (1..10).try_fold(7, f));
+     let mut iter = (1..20).take_while(|&x| x != 10);
+     assert_eq!(iter.try_fold(0, |x, y| Some(x + y)), Some((1..10).sum()));
+     assert_eq!(iter.next(), None, "flag should be set");
+     let iter = (1..20).take_while(|&x| x != 10);
+     assert_eq!(iter.fold(0, |x, y| x + y), (1..10).sum());
+ 
+     let mut iter = (10..50).take_while(|&x| x != 40);
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(20));
+ }
+ 
+ #[test]
+ fn test_skip_try_folds() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((1..20).skip(9).try_fold(7, f), (10..20).try_fold(7, f));
+     assert_eq!((1..20).skip(9).try_rfold(7, f), (10..20).try_rfold(7, f));
+ 
+     let mut iter = (0..30).skip(10);
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(20));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(24));
+ }
+ 
+ #[test]
+ fn test_skip_nth_back() {
+     let xs = [0, 1, 2, 3, 4, 5];
+     let mut it = xs.iter().skip(2);
+     assert_eq!(it.nth_back(0), Some(&5));
+     assert_eq!(it.nth_back(1), Some(&3));
+     assert_eq!(it.nth_back(0), Some(&2));
+     assert_eq!(it.nth_back(0), None);
+ 
+     let ys = [2, 3, 4, 5];
+     let mut ity = ys.iter();
+     let mut it = xs.iter().skip(2);
+     assert_eq!(it.nth_back(1), ity.nth_back(1));
+     assert_eq!(it.clone().nth(0), ity.clone().nth(0));
+     assert_eq!(it.nth_back(0), ity.nth_back(0));
+     assert_eq!(it.clone().nth(0), ity.clone().nth(0));
+     assert_eq!(it.nth_back(0), ity.nth_back(0));
+     assert_eq!(it.clone().nth(0), ity.clone().nth(0));
+     assert_eq!(it.nth_back(0), ity.nth_back(0));
+     assert_eq!(it.clone().nth(0), ity.clone().nth(0));
+ 
+     let mut it = xs.iter().skip(2);
+     assert_eq!(it.nth_back(4), None);
+     assert_eq!(it.nth_back(0), None);
+ 
+     let mut it = xs.iter();
+     it.by_ref().skip(2).nth_back(3);
+     assert_eq!(it.next_back(), Some(&1));
+ 
+     let mut it = xs.iter();
+     it.by_ref().skip(2).nth_back(10);
+     assert_eq!(it.next_back(), Some(&1));
+ }
+ 
+ #[test]
+ fn test_take_try_folds() {
+     let f = &|acc, x| i32::checked_add(2 * acc, x);
+     assert_eq!((10..30).take(10).try_fold(7, f), (10..20).try_fold(7, f));
+     assert_eq!((10..30).take(10).try_rfold(7, f), (10..20).try_rfold(7, f));
+ 
+     let mut iter = (10..30).take(20);
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(20));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(24));
+ 
+     let mut iter = (2..20).take(3);
+     assert_eq!(iter.try_for_each(Err), Err(2));
+     assert_eq!(iter.try_for_each(Err), Err(3));
+     assert_eq!(iter.try_for_each(Err), Err(4));
+     assert_eq!(iter.try_for_each(Err), Ok(()));
+ 
+     let mut iter = (2..20).take(3).rev();
+     assert_eq!(iter.try_for_each(Err), Err(4));
+     assert_eq!(iter.try_for_each(Err), Err(3));
+     assert_eq!(iter.try_for_each(Err), Err(2));
+     assert_eq!(iter.try_for_each(Err), Ok(()));
+ }
+ 
+ #[test]
+ fn test_flat_map_try_folds() {
+     let f = &|acc, x| i32::checked_add(acc * 2 / 3, x);
+     let mr = &|x| (5 * x)..(5 * x + 5);
+     assert_eq!((0..10).flat_map(mr).try_fold(7, f), (0..50).try_fold(7, f));
+     assert_eq!((0..10).flat_map(mr).try_rfold(7, f), (0..50).try_rfold(7, f));
+     let mut iter = (0..10).flat_map(mr);
+     iter.next();
+     iter.next_back(); // have front and back iters in progress
+     assert_eq!(iter.try_rfold(7, f), (1..49).try_rfold(7, f));
+ 
+     let mut iter = (0..10).flat_map(|x| (4 * x)..(4 * x + 4));
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(17));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(35));
+ }
+ 
+ #[test]
+ fn test_flatten_try_folds() {
+     let f = &|acc, x| i32::checked_add(acc * 2 / 3, x);
+     let mr = &|x| (5 * x)..(5 * x + 5);
+     assert_eq!((0..10).map(mr).flatten().try_fold(7, f), (0..50).try_fold(7, f));
+     assert_eq!((0..10).map(mr).flatten().try_rfold(7, f), (0..50).try_rfold(7, f));
+     let mut iter = (0..10).map(mr).flatten();
+     iter.next();
+     iter.next_back(); // have front and back iters in progress
+     assert_eq!(iter.try_rfold(7, f), (1..49).try_rfold(7, f));
+ 
+     let mut iter = (0..10).map(|x| (4 * x)..(4 * x + 4)).flatten();
+     assert_eq!(iter.try_fold(0, i8::checked_add), None);
+     assert_eq!(iter.next(), Some(17));
+     assert_eq!(iter.try_rfold(0, i8::checked_add), None);
+     assert_eq!(iter.next_back(), Some(35));
+ }
+ 
+ #[test]
+ fn test_functor_laws() {
+     // identity:
+     fn identity<T>(x: T) -> T {
+         x
+     }
+     assert_eq!((0..10).map(identity).sum::<usize>(), (0..10).sum());
+ 
+     // composition:
+     fn f(x: usize) -> usize {
+         x + 3
+     }
+     fn g(x: usize) -> usize {
+         x * 2
+     }
+     fn h(x: usize) -> usize {
+         g(f(x))
+     }
+     assert_eq!((0..10).map(f).map(g).sum::<usize>(), (0..10).map(h).sum());
+ }
+ 
+ #[test]
+ fn test_monad_laws_left_identity() {
+     fn f(x: usize) -> impl Iterator<Item = usize> {
+         (0..10).map(move |y| x * y)
+     }
+     assert_eq!(once(42).flat_map(f.clone()).sum::<usize>(), f(42).sum());
+ }
+ 
+ #[test]
+ fn test_monad_laws_right_identity() {
+     assert_eq!((0..10).flat_map(|x| once(x)).sum::<usize>(), (0..10).sum());
+ }
+ 
+ #[test]
+ fn test_monad_laws_associativity() {
+     fn f(x: usize) -> impl Iterator<Item = usize> {
+         0..x
+     }
+     fn g(x: usize) -> impl Iterator<Item = usize> {
+         (0..x).rev()
+     }
+     assert_eq!(
+         (0..10).flat_map(f).flat_map(g).sum::<usize>(),
+         (0..10).flat_map(|x| f(x).flat_map(g)).sum::<usize>()
+     );
+ }
+ 
+ #[test]
+ fn test_is_sorted() {
+     assert!([1, 2, 2, 9].iter().is_sorted());
+     assert!(![1, 3, 2].iter().is_sorted());
+     assert!([0].iter().is_sorted());
+     assert!(std::iter::empty::<i32>().is_sorted());
+     assert!(![0.0, 1.0, f32::NAN].iter().is_sorted());
+     assert!([-2, -1, 0, 3].iter().is_sorted());
+     assert!(![-2i32, -1, 0, 3].iter().is_sorted_by_key(|n| n.abs()));
+     assert!(!["c", "bb", "aaa"].iter().is_sorted());
+     assert!(["c", "bb", "aaa"].iter().is_sorted_by_key(|s| s.len()));
+ }
+ 
+ #[test]
+ fn test_partition() {
+     fn check(xs: &mut [i32], ref p: impl Fn(&i32) -> bool, expected: usize) {
+         let i = xs.iter_mut().partition_in_place(p);
+         assert_eq!(expected, i);
+         assert!(xs[..i].iter().all(p));
+         assert!(!xs[i..].iter().any(p));
+         assert!(xs.iter().is_partitioned(p));
+         if i == 0 || i == xs.len() {
+             assert!(xs.iter().rev().is_partitioned(p));
+         } else {
+             assert!(!xs.iter().rev().is_partitioned(p));
+         }
+     }
+ 
+     check(&mut [], |_| true, 0);
+     check(&mut [], |_| false, 0);
+ 
+     check(&mut [0], |_| true, 1);
+     check(&mut [0], |_| false, 0);
+ 
+     check(&mut [-1, 1], |&x| x > 0, 1);
+     check(&mut [-1, 1], |&x| x < 0, 1);
+ 
+     let ref mut xs = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9];
+     check(xs, |_| true, 10);
+     check(xs, |_| false, 0);
+     check(xs, |&x| x % 2 == 0, 5); // evens
+     check(xs, |&x| x % 2 == 1, 5); // odds
+     check(xs, |&x| x % 3 == 0, 4); // multiple of 3
+     check(xs, |&x| x % 4 == 0, 3); // multiple of 4
+     check(xs, |&x| x % 5 == 0, 2); // multiple of 5
+     check(xs, |&x| x < 3, 3); // small
+     check(xs, |&x| x > 6, 3); // large
+ }
+ 
+ /// An iterator that panics whenever `next` or next_back` is called
+ /// after `None` has already been returned. This does not violate
+ /// `Iterator`'s contract. Used to test that iterator adaptors don't
+ /// poll their inner iterators after exhausting them.
+ struct NonFused<I> {
+     iter: I,
+     done: bool,
+ }
+ 
+ impl<I> NonFused<I> {
+     fn new(iter: I) -> Self {
+         Self { iter, done: false }
+     }
+ }
+ 
+ impl<I> Iterator for NonFused<I>
+ where
+     I: Iterator,
+ {
+     type Item = I::Item;
+ 
+     fn next(&mut self) -> Option<Self::Item> {
+         assert!(!self.done, "this iterator has already returned None");
+         self.iter.next().or_else(|| {
+             self.done = true;
+             None
+         })
+     }
+ }
+ 
+ impl<I> DoubleEndedIterator for NonFused<I>
+ where
+     I: DoubleEndedIterator,
+ {
+     fn next_back(&mut self) -> Option<Self::Item> {
+         assert!(!self.done, "this iterator has already returned None");
+         self.iter.next_back().or_else(|| {
+             self.done = true;
+             None
+         })
+     }
+ }
+ 
+ #[test]
+ fn test_peekable_non_fused() {
+     let mut iter = NonFused::new(empty::<i32>()).peekable();
+ 
+     assert_eq!(iter.peek(), None);
+     assert_eq!(iter.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_flatten_non_fused_outer() {
+     let mut iter = NonFused::new(once(0..2)).flatten();
+ 
+     assert_eq!(iter.next_back(), Some(1));
+     assert_eq!(iter.next(), Some(0));
+     assert_eq!(iter.next(), None);
+ }
+ 
+ #[test]
+ fn test_flatten_non_fused_inner() {
+     let mut iter = once(0..1).chain(once(1..3)).flat_map(NonFused::new);
+ 
+     assert_eq!(iter.next_back(), Some(2));
+     assert_eq!(iter.next(), Some(0));
+     assert_eq!(iter.next(), Some(1));
+     assert_eq!(iter.next(), None);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/lazy.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/lazy.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/lazy.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/lazy.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,133 ----
+ use core::{
+     cell::Cell,
+     lazy::{Lazy, OnceCell},
+     sync::atomic::{AtomicUsize, Ordering::SeqCst},
+ };
+ 
+ #[test]
+ fn once_cell() {
+     let c = OnceCell::new();
+     assert!(c.get().is_none());
+     c.get_or_init(|| 92);
+     assert_eq!(c.get(), Some(&92));
+ 
+     c.get_or_init(|| panic!("Kabom!"));
+     assert_eq!(c.get(), Some(&92));
+ }
+ 
+ #[test]
+ fn once_cell_get_mut() {
+     let mut c = OnceCell::new();
+     assert!(c.get_mut().is_none());
+     c.set(90).unwrap();
+     *c.get_mut().unwrap() += 2;
+     assert_eq!(c.get_mut(), Some(&mut 92));
+ }
+ 
+ #[test]
+ fn once_cell_drop() {
+     static DROP_CNT: AtomicUsize = AtomicUsize::new(0);
+     struct Dropper;
+     impl Drop for Dropper {
+         fn drop(&mut self) {
+             DROP_CNT.fetch_add(1, SeqCst);
+         }
+     }
+ 
+     let x = OnceCell::new();
+     x.get_or_init(|| Dropper);
+     assert_eq!(DROP_CNT.load(SeqCst), 0);
+     drop(x);
+     assert_eq!(DROP_CNT.load(SeqCst), 1);
+ }
+ 
+ #[test]
+ fn unsync_once_cell_drop_empty() {
+     let x = OnceCell::<&'static str>::new();
+     drop(x);
+ }
+ 
+ #[test]
+ fn clone() {
+     let s = OnceCell::new();
+     let c = s.clone();
+     assert!(c.get().is_none());
+ 
+     s.set("hello").unwrap();
+     let c = s.clone();
+     assert_eq!(c.get().map(|c| *c), Some("hello"));
+ }
+ 
+ #[test]
+ fn from_impl() {
+     assert_eq!(OnceCell::from("value").get(), Some(&"value"));
+     assert_ne!(OnceCell::from("foo").get(), Some(&"bar"));
+ }
+ 
+ #[test]
+ fn partialeq_impl() {
+     assert!(OnceCell::from("value") == OnceCell::from("value"));
+     assert!(OnceCell::from("foo") != OnceCell::from("bar"));
+ 
+     assert!(OnceCell::<&'static str>::new() == OnceCell::new());
+     assert!(OnceCell::<&'static str>::new() != OnceCell::from("value"));
+ }
+ 
+ #[test]
+ fn into_inner() {
+     let cell: OnceCell<&'static str> = OnceCell::new();
+     assert_eq!(cell.into_inner(), None);
+     let cell = OnceCell::new();
+     cell.set("hello").unwrap();
+     assert_eq!(cell.into_inner(), Some("hello"));
+ }
+ 
+ #[test]
+ fn lazy_new() {
+     let called = Cell::new(0);
+     let x = Lazy::new(|| {
+         called.set(called.get() + 1);
+         92
+     });
+ 
+     assert_eq!(called.get(), 0);
+ 
+     let y = *x - 30;
+     assert_eq!(y, 62);
+     assert_eq!(called.get(), 1);
+ 
+     let y = *x - 30;
+     assert_eq!(y, 62);
+     assert_eq!(called.get(), 1);
+ }
+ 
+ #[test]
+ fn aliasing_in_get() {
+     let x = OnceCell::new();
+     x.set(42).unwrap();
+     let at_x = x.get().unwrap(); // --- (shared) borrow of inner `Option<T>` --+
+     let _ = x.set(27); // <-- temporary (unique) borrow of inner `Option<T>`   |
+     println!("{}", at_x); // <------- up until here ---------------------------+
+ }
+ 
+ #[test]
+ #[should_panic(expected = "reentrant init")]
+ fn reentrant_init() {
+     let x: OnceCell<Box<i32>> = OnceCell::new();
+     let dangling_ref: Cell<Option<&i32>> = Cell::new(None);
+     x.get_or_init(|| {
+         let r = x.get_or_init(|| Box::new(92));
+         dangling_ref.set(Some(r));
+         Box::new(62)
+     });
+     eprintln!("use after free: {:?}", dangling_ref.get().unwrap());
+ }
+ 
+ #[test]
+ fn dropck() {
+     let cell = OnceCell::new();
+     {
+         let s = String::new();
+         cell.set(&s).unwrap();
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/lib.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,97 ----
+ #![feature(alloc_layout_extra)]
+ #![feature(array_chunks)]
+ #![feature(array_from_ref)]
+ #![feature(array_methods)]
+ #![feature(array_map)]
+ #![feature(array_windows)]
+ #![feature(bool_to_option)]
+ #![feature(bound_cloned)]
+ #![feature(box_syntax)]
+ #![feature(cell_update)]
+ #![feature(const_assume)]
+ #![feature(const_cell_into_inner)]
+ #![feature(core_intrinsics)]
+ #![feature(core_private_bignum)]
+ #![feature(core_private_diy_float)]
+ #![feature(debug_non_exhaustive)]
+ #![feature(dec2flt)]
+ #![feature(div_duration)]
+ #![feature(duration_consts_2)]
+ #![feature(duration_constants)]
+ #![feature(duration_saturating_ops)]
+ #![feature(duration_zero)]
+ #![feature(exact_size_is_empty)]
+ #![feature(fixed_size_array)]
+ #![feature(flt2dec)]
+ #![feature(fmt_internals)]
+ #![feature(hashmap_internals)]
+ #![feature(try_find)]
+ #![feature(is_sorted)]
+ #![feature(pattern)]
+ #![feature(raw)]
+ #![feature(sort_internals)]
+ #![feature(slice_partition_at_index)]
+ #![feature(min_specialization)]
+ #![feature(step_trait)]
+ #![feature(step_trait_ext)]
+ #![feature(str_internals)]
+ #![feature(test)]
+ #![feature(trusted_len)]
+ #![feature(try_trait)]
+ #![feature(slice_internals)]
+ #![feature(slice_partition_dedup)]
+ #![feature(int_error_matching)]
+ #![feature(array_value_iter)]
+ #![feature(iter_advance_by)]
+ #![feature(iter_partition_in_place)]
+ #![feature(iter_is_partitioned)]
+ #![feature(iter_order_by)]
+ #![feature(cmp_min_max_by)]
+ #![feature(iter_map_while)]
+ #![feature(const_mut_refs)]
+ #![feature(const_pin)]
+ #![feature(const_slice_from_raw_parts)]
+ #![feature(const_raw_ptr_deref)]
+ #![feature(never_type)]
+ #![feature(unwrap_infallible)]
+ #![feature(option_unwrap_none)]
+ #![feature(peekable_next_if)]
+ #![feature(partition_point)]
+ #![feature(once_cell)]
+ #![feature(unsafe_block_in_unsafe_fn)]
+ #![feature(int_bits_const)]
+ #![deny(unsafe_op_in_unsafe_fn)]
+ 
+ extern crate test;
+ 
+ mod alloc;
+ mod any;
+ mod array;
+ mod ascii;
+ mod atomic;
+ mod bool;
+ mod cell;
+ mod char;
+ mod clone;
+ mod cmp;
+ mod fmt;
+ mod hash;
+ mod intrinsics;
+ mod iter;
+ mod lazy;
+ mod manually_drop;
+ mod mem;
+ mod nonzero;
+ mod num;
+ mod ops;
+ mod option;
+ mod pattern;
+ mod pin;
+ mod ptr;
+ mod result;
+ mod slice;
+ mod str;
+ mod str_lossy;
+ mod task;
+ mod time;
+ mod tuple;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/manually_drop.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/manually_drop.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/manually_drop.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/manually_drop.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,19 ----
+ use core::mem::ManuallyDrop;
+ 
+ #[test]
+ fn smoke() {
+     struct TypeWithDrop;
+     impl Drop for TypeWithDrop {
+         fn drop(&mut self) {
+             unreachable!("Should not get dropped");
+         }
+     }
+ 
+     let x = ManuallyDrop::new(TypeWithDrop);
+     drop(x);
+ 
+     // also test unsizing
+     let x: Box<ManuallyDrop<[TypeWithDrop]>> =
+         Box::new(ManuallyDrop::new([TypeWithDrop, TypeWithDrop]));
+     drop(x);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/mem.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/mem.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/mem.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/mem.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,131 ----
+ use core::mem::*;
+ 
+ #[test]
+ fn size_of_basic() {
+     assert_eq!(size_of::<u8>(), 1);
+     assert_eq!(size_of::<u16>(), 2);
+     assert_eq!(size_of::<u32>(), 4);
+     assert_eq!(size_of::<u64>(), 8);
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "16")]
+ fn size_of_16() {
+     assert_eq!(size_of::<usize>(), 2);
+     assert_eq!(size_of::<*const usize>(), 2);
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "32")]
+ fn size_of_32() {
+     assert_eq!(size_of::<usize>(), 4);
+     assert_eq!(size_of::<*const usize>(), 4);
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "64")]
+ fn size_of_64() {
+     assert_eq!(size_of::<usize>(), 8);
+     assert_eq!(size_of::<*const usize>(), 8);
+ }
+ 
+ #[test]
+ fn size_of_val_basic() {
+     assert_eq!(size_of_val(&1u8), 1);
+     assert_eq!(size_of_val(&1u16), 2);
+     assert_eq!(size_of_val(&1u32), 4);
+     assert_eq!(size_of_val(&1u64), 8);
+ }
+ 
+ #[test]
+ fn align_of_basic() {
+     assert_eq!(align_of::<u8>(), 1);
+     assert_eq!(align_of::<u16>(), 2);
+     assert_eq!(align_of::<u32>(), 4);
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "16")]
+ fn align_of_16() {
+     assert_eq!(align_of::<usize>(), 2);
+     assert_eq!(align_of::<*const usize>(), 2);
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "32")]
+ fn align_of_32() {
+     assert_eq!(align_of::<usize>(), 4);
+     assert_eq!(align_of::<*const usize>(), 4);
+ }
+ 
+ #[test]
+ #[cfg(target_pointer_width = "64")]
+ fn align_of_64() {
+     assert_eq!(align_of::<usize>(), 8);
+     assert_eq!(align_of::<*const usize>(), 8);
+ }
+ 
+ #[test]
+ fn align_of_val_basic() {
+     assert_eq!(align_of_val(&1u8), 1);
+     assert_eq!(align_of_val(&1u16), 2);
+     assert_eq!(align_of_val(&1u32), 4);
+ }
+ 
+ #[test]
+ fn test_swap() {
+     let mut x = 31337;
+     let mut y = 42;
+     swap(&mut x, &mut y);
+     assert_eq!(x, 42);
+     assert_eq!(y, 31337);
+ }
+ 
+ #[test]
+ fn test_replace() {
+     let mut x = Some("test".to_string());
+     let y = replace(&mut x, None);
+     assert!(x.is_none());
+     assert!(y.is_some());
+ }
+ 
+ #[test]
+ fn test_transmute_copy() {
+     assert_eq!(1, unsafe { transmute_copy(&1) });
+ }
+ 
+ #[test]
+ fn test_transmute() {
+     trait Foo {
+         fn dummy(&self) {}
+     }
+     impl Foo for isize {}
+ 
+     let a = box 100isize as Box<dyn Foo>;
+     unsafe {
+         let x: ::core::raw::TraitObject = transmute(a);
+         assert!(*(x.data as *const isize) == 100);
+         let _x: Box<dyn Foo> = transmute(x);
+     }
+ 
+     unsafe {
+         assert_eq!(transmute::<_, Vec<u8>>("L".to_string()), [76]);
+     }
+ }
+ 
+ #[test]
+ #[allow(dead_code)]
+ fn test_discriminant_send_sync() {
+     enum Regular {
+         A,
+         B(i32),
+     }
+     enum NotSendSync {
+         A(*const i32),
+     }
+ 
+     fn is_send_sync<T: Send + Sync>() {}
+ 
+     is_send_sync::<Discriminant<Regular>>();
+     is_send_sync::<Discriminant<NotSendSync>>();
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/nonzero.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/nonzero.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/nonzero.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/nonzero.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,214 ----
+ use core::convert::TryFrom;
+ use core::num::{IntErrorKind, NonZeroI32, NonZeroI8, NonZeroU32, NonZeroU8};
+ use core::option::Option::{self, None, Some};
+ use std::mem::size_of;
+ 
+ #[test]
+ fn test_create_nonzero_instance() {
+     let _a = unsafe { NonZeroU32::new_unchecked(21) };
+ }
+ 
+ #[test]
+ fn test_size_nonzero_in_option() {
+     assert_eq!(size_of::<NonZeroU32>(), size_of::<Option<NonZeroU32>>());
+     assert_eq!(size_of::<NonZeroI32>(), size_of::<Option<NonZeroI32>>());
+ }
+ 
+ #[test]
+ fn test_match_on_nonzero_option() {
+     let a = Some(unsafe { NonZeroU32::new_unchecked(42) });
+     match a {
+         Some(val) => assert_eq!(val.get(), 42),
+         None => panic!("unexpected None while matching on Some(NonZeroU32(_))"),
+     }
+ 
+     match unsafe { Some(NonZeroU32::new_unchecked(43)) } {
+         Some(val) => assert_eq!(val.get(), 43),
+         None => panic!("unexpected None while matching on Some(NonZeroU32(_))"),
+     }
+ }
+ 
+ #[test]
+ fn test_match_option_empty_vec() {
+     let a: Option<Vec<isize>> = Some(vec![]);
+     match a {
+         None => panic!("unexpected None while matching on Some(vec![])"),
+         _ => {}
+     }
+ }
+ 
+ #[test]
+ fn test_match_option_vec() {
+     let a = Some(vec![1, 2, 3, 4]);
+     match a {
+         Some(v) => assert_eq!(v, [1, 2, 3, 4]),
+         None => panic!("unexpected None while matching on Some(vec![1, 2, 3, 4])"),
+     }
+ }
+ 
+ #[test]
+ fn test_match_option_rc() {
+     use std::rc::Rc;
+ 
+     let five = Rc::new(5);
+     match Some(five) {
+         Some(r) => assert_eq!(*r, 5),
+         None => panic!("unexpected None while matching on Some(Rc::new(5))"),
+     }
+ }
+ 
+ #[test]
+ fn test_match_option_arc() {
+     use std::sync::Arc;
+ 
+     let five = Arc::new(5);
+     match Some(five) {
+         Some(a) => assert_eq!(*a, 5),
+         None => panic!("unexpected None while matching on Some(Arc::new(5))"),
+     }
+ }
+ 
+ #[test]
+ fn test_match_option_empty_string() {
+     let a = Some(String::new());
+     match a {
+         None => panic!("unexpected None while matching on Some(String::new())"),
+         _ => {}
+     }
+ }
+ 
+ #[test]
+ fn test_match_option_string() {
+     let five = "Five".to_string();
+     match Some(five) {
+         Some(s) => assert_eq!(s, "Five"),
+         None => panic!("unexpected None while matching on Some(String { ... })"),
+     }
+ }
+ 
+ mod atom {
+     use core::num::NonZeroU32;
+ 
+     #[derive(PartialEq, Eq)]
+     pub struct Atom {
+         index: NonZeroU32, // private
+     }
+     pub const FOO_ATOM: Atom = Atom { index: unsafe { NonZeroU32::new_unchecked(7) } };
+ }
+ 
+ macro_rules! atom {
+     ("foo") => {
+         atom::FOO_ATOM
+     };
+ }
+ 
+ #[test]
+ fn test_match_nonzero_const_pattern() {
+     match atom!("foo") {
+         // Using as a pattern is supported by the compiler:
+         atom!("foo") => {}
+         _ => panic!("Expected the const item as a pattern to match."),
+     }
+ }
+ 
+ #[test]
+ fn test_from_nonzero() {
+     let nz = NonZeroU32::new(1).unwrap();
+     let num: u32 = nz.into();
+     assert_eq!(num, 1u32);
+ }
+ 
+ #[test]
+ fn test_from_signed_nonzero() {
+     let nz = NonZeroI32::new(1).unwrap();
+     let num: i32 = nz.into();
+     assert_eq!(num, 1i32);
+ }
+ 
+ #[test]
+ fn test_from_str() {
+     assert_eq!("123".parse::<NonZeroU8>(), Ok(NonZeroU8::new(123).unwrap()));
+     assert_eq!("0".parse::<NonZeroU8>().err().map(|e| e.kind().clone()), Some(IntErrorKind::Zero));
+     assert_eq!(
+         "-1".parse::<NonZeroU8>().err().map(|e| e.kind().clone()),
+         Some(IntErrorKind::InvalidDigit)
+     );
+     assert_eq!(
+         "-129".parse::<NonZeroI8>().err().map(|e| e.kind().clone()),
+         Some(IntErrorKind::NegOverflow)
+     );
+     assert_eq!(
+         "257".parse::<NonZeroU8>().err().map(|e| e.kind().clone()),
+         Some(IntErrorKind::PosOverflow)
+     );
+ }
+ 
+ #[test]
+ fn test_nonzero_bitor() {
+     let nz_alt = NonZeroU8::new(0b1010_1010).unwrap();
+     let nz_low = NonZeroU8::new(0b0000_1111).unwrap();
+ 
+     let both_nz: NonZeroU8 = nz_alt | nz_low;
+     assert_eq!(both_nz.get(), 0b1010_1111);
+ 
+     let rhs_int: NonZeroU8 = nz_low | 0b1100_0000u8;
+     assert_eq!(rhs_int.get(), 0b1100_1111);
+ 
+     let rhs_zero: NonZeroU8 = nz_alt | 0u8;
+     assert_eq!(rhs_zero.get(), 0b1010_1010);
+ 
+     let lhs_int: NonZeroU8 = 0b0110_0110u8 | nz_alt;
+     assert_eq!(lhs_int.get(), 0b1110_1110);
+ 
+     let lhs_zero: NonZeroU8 = 0u8 | nz_low;
+     assert_eq!(lhs_zero.get(), 0b0000_1111);
+ }
+ 
+ #[test]
+ fn test_nonzero_bitor_assign() {
+     let mut target = NonZeroU8::new(0b1010_1010).unwrap();
+ 
+     target |= NonZeroU8::new(0b0000_1111).unwrap();
+     assert_eq!(target.get(), 0b1010_1111);
+ 
+     target |= 0b0001_0000;
+     assert_eq!(target.get(), 0b1011_1111);
+ 
+     target |= 0;
+     assert_eq!(target.get(), 0b1011_1111);
+ }
+ 
+ #[test]
+ fn test_nonzero_from_int_on_success() {
+     assert_eq!(NonZeroU8::try_from(5), Ok(NonZeroU8::new(5).unwrap()));
+     assert_eq!(NonZeroU32::try_from(5), Ok(NonZeroU32::new(5).unwrap()));
+ 
+     assert_eq!(NonZeroI8::try_from(-5), Ok(NonZeroI8::new(-5).unwrap()));
+     assert_eq!(NonZeroI32::try_from(-5), Ok(NonZeroI32::new(-5).unwrap()));
+ }
+ 
+ #[test]
+ fn test_nonzero_from_int_on_err() {
+     assert!(NonZeroU8::try_from(0).is_err());
+     assert!(NonZeroU32::try_from(0).is_err());
+ 
+     assert!(NonZeroI8::try_from(0).is_err());
+     assert!(NonZeroI32::try_from(0).is_err());
+ }
+ 
+ #[test]
+ fn nonzero_const() {
+     // test that the methods of `NonZeroX>` are usable in a const context
+     // Note: only tests NonZero8
+ 
+     const NONZERO: NonZeroU8 = unsafe { NonZeroU8::new_unchecked(5) };
+ 
+     const GET: u8 = NONZERO.get();
+     assert_eq!(GET, 5);
+ 
+     const ZERO: Option<NonZeroU8> = NonZeroU8::new(0);
+     assert!(ZERO.is_none());
+ 
+     const ONE: Option<NonZeroU8> = NonZeroU8::new(1);
+     assert!(ONE.is_some());
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/bignum.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/bignum.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/bignum.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/bignum.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,241 ----
+ use core::num::bignum::tests::Big8x3 as Big;
+ 
+ #[test]
+ #[should_panic]
+ fn test_from_u64_overflow() {
+     Big::from_u64(0x1000000);
+ }
+ 
+ #[test]
+ fn test_add() {
+     assert_eq!(*Big::from_small(3).add(&Big::from_small(4)), Big::from_small(7));
+     assert_eq!(*Big::from_small(3).add(&Big::from_small(0)), Big::from_small(3));
+     assert_eq!(*Big::from_small(0).add(&Big::from_small(3)), Big::from_small(3));
+     assert_eq!(*Big::from_small(3).add(&Big::from_u64(0xfffe)), Big::from_u64(0x10001));
+     assert_eq!(*Big::from_u64(0xfedc).add(&Big::from_u64(0x789)), Big::from_u64(0x10665));
+     assert_eq!(*Big::from_u64(0x789).add(&Big::from_u64(0xfedc)), Big::from_u64(0x10665));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_add_overflow_1() {
+     Big::from_small(1).add(&Big::from_u64(0xffffff));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_add_overflow_2() {
+     Big::from_u64(0xffffff).add(&Big::from_small(1));
+ }
+ 
+ #[test]
+ fn test_add_small() {
+     assert_eq!(*Big::from_small(3).add_small(4), Big::from_small(7));
+     assert_eq!(*Big::from_small(3).add_small(0), Big::from_small(3));
+     assert_eq!(*Big::from_small(0).add_small(3), Big::from_small(3));
+     assert_eq!(*Big::from_small(7).add_small(250), Big::from_u64(257));
+     assert_eq!(*Big::from_u64(0x7fff).add_small(1), Big::from_u64(0x8000));
+     assert_eq!(*Big::from_u64(0x2ffe).add_small(0x35), Big::from_u64(0x3033));
+     assert_eq!(*Big::from_small(0xdc).add_small(0x89), Big::from_u64(0x165));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_add_small_overflow() {
+     Big::from_u64(0xffffff).add_small(1);
+ }
+ 
+ #[test]
+ fn test_sub() {
+     assert_eq!(*Big::from_small(7).sub(&Big::from_small(4)), Big::from_small(3));
+     assert_eq!(*Big::from_u64(0x10665).sub(&Big::from_u64(0x789)), Big::from_u64(0xfedc));
+     assert_eq!(*Big::from_u64(0x10665).sub(&Big::from_u64(0xfedc)), Big::from_u64(0x789));
+     assert_eq!(*Big::from_u64(0x10665).sub(&Big::from_u64(0x10664)), Big::from_small(1));
+     assert_eq!(*Big::from_u64(0x10665).sub(&Big::from_u64(0x10665)), Big::from_small(0));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_sub_underflow_1() {
+     Big::from_u64(0x10665).sub(&Big::from_u64(0x10666));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_sub_underflow_2() {
+     Big::from_small(0).sub(&Big::from_u64(0x123456));
+ }
+ 
+ #[test]
+ fn test_mul_small() {
+     assert_eq!(*Big::from_small(7).mul_small(5), Big::from_small(35));
+     assert_eq!(*Big::from_small(0xff).mul_small(0xff), Big::from_u64(0xfe01));
+     assert_eq!(*Big::from_u64(0xffffff / 13).mul_small(13), Big::from_u64(0xffffff));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_small_overflow() {
+     Big::from_u64(0x800000).mul_small(2);
+ }
+ 
+ #[test]
+ fn test_mul_pow2() {
+     assert_eq!(*Big::from_small(0x7).mul_pow2(4), Big::from_small(0x70));
+     assert_eq!(*Big::from_small(0xff).mul_pow2(1), Big::from_u64(0x1fe));
+     assert_eq!(*Big::from_small(0xff).mul_pow2(12), Big::from_u64(0xff000));
+     assert_eq!(*Big::from_small(0x1).mul_pow2(23), Big::from_u64(0x800000));
+     assert_eq!(*Big::from_u64(0x123).mul_pow2(0), Big::from_u64(0x123));
+     assert_eq!(*Big::from_u64(0x123).mul_pow2(7), Big::from_u64(0x9180));
+     assert_eq!(*Big::from_u64(0x123).mul_pow2(15), Big::from_u64(0x918000));
+     assert_eq!(*Big::from_small(0).mul_pow2(23), Big::from_small(0));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_pow2_overflow_1() {
+     Big::from_u64(0x1).mul_pow2(24);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_pow2_overflow_2() {
+     Big::from_u64(0x123).mul_pow2(16);
+ }
+ 
+ #[test]
+ fn test_mul_pow5() {
+     assert_eq!(*Big::from_small(42).mul_pow5(0), Big::from_small(42));
+     assert_eq!(*Big::from_small(1).mul_pow5(2), Big::from_small(25));
+     assert_eq!(*Big::from_small(1).mul_pow5(4), Big::from_u64(25 * 25));
+     assert_eq!(*Big::from_small(4).mul_pow5(3), Big::from_u64(500));
+     assert_eq!(*Big::from_small(140).mul_pow5(2), Big::from_u64(25 * 140));
+     assert_eq!(*Big::from_small(25).mul_pow5(1), Big::from_small(125));
+     assert_eq!(*Big::from_small(125).mul_pow5(7), Big::from_u64(9765625));
+     assert_eq!(*Big::from_small(0).mul_pow5(127), Big::from_small(0));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_pow5_overflow_1() {
+     Big::from_small(1).mul_pow5(12);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_pow5_overflow_2() {
+     Big::from_small(230).mul_pow5(8);
+ }
+ 
+ #[test]
+ fn test_mul_digits() {
+     assert_eq!(*Big::from_small(3).mul_digits(&[5]), Big::from_small(15));
+     assert_eq!(*Big::from_small(0xff).mul_digits(&[0xff]), Big::from_u64(0xfe01));
+     assert_eq!(*Big::from_u64(0x123).mul_digits(&[0x56, 0x4]), Big::from_u64(0x4edc2));
+     assert_eq!(*Big::from_u64(0x12345).mul_digits(&[0x67]), Big::from_u64(0x7530c3));
+     assert_eq!(*Big::from_small(0x12).mul_digits(&[0x67, 0x45, 0x3]), Big::from_u64(0x3ae13e));
+     assert_eq!(*Big::from_u64(0xffffff / 13).mul_digits(&[13]), Big::from_u64(0xffffff));
+     assert_eq!(*Big::from_small(13).mul_digits(&[0x3b, 0xb1, 0x13]), Big::from_u64(0xffffff));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_digits_overflow_1() {
+     Big::from_u64(0x800000).mul_digits(&[2]);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_mul_digits_overflow_2() {
+     Big::from_u64(0x1000).mul_digits(&[0, 0x10]);
+ }
+ 
+ #[test]
+ fn test_div_rem_small() {
+     let as_val = |(q, r): (&mut Big, u8)| (q.clone(), r);
+     assert_eq!(as_val(Big::from_small(0xff).div_rem_small(15)), (Big::from_small(17), 0));
+     assert_eq!(as_val(Big::from_small(0xff).div_rem_small(16)), (Big::from_small(15), 15));
+     assert_eq!(as_val(Big::from_small(3).div_rem_small(40)), (Big::from_small(0), 3));
+     assert_eq!(
+         as_val(Big::from_u64(0xffffff).div_rem_small(123)),
+         (Big::from_u64(0xffffff / 123), (0xffffffu64 % 123) as u8)
+     );
+     assert_eq!(
+         as_val(Big::from_u64(0x10000).div_rem_small(123)),
+         (Big::from_u64(0x10000 / 123), (0x10000u64 % 123) as u8)
+     );
+ }
+ 
+ #[test]
+ fn test_div_rem() {
+     fn div_rem(n: u64, d: u64) -> (Big, Big) {
+         let mut q = Big::from_small(42);
+         let mut r = Big::from_small(42);
+         Big::from_u64(n).div_rem(&Big::from_u64(d), &mut q, &mut r);
+         (q, r)
+     }
+     assert_eq!(div_rem(1, 1), (Big::from_small(1), Big::from_small(0)));
+     assert_eq!(div_rem(4, 3), (Big::from_small(1), Big::from_small(1)));
+     assert_eq!(div_rem(1, 7), (Big::from_small(0), Big::from_small(1)));
+     assert_eq!(div_rem(45, 9), (Big::from_small(5), Big::from_small(0)));
+     assert_eq!(div_rem(103, 9), (Big::from_small(11), Big::from_small(4)));
+     assert_eq!(div_rem(123456, 77), (Big::from_u64(1603), Big::from_small(25)));
+     assert_eq!(div_rem(0xffff, 1), (Big::from_u64(0xffff), Big::from_small(0)));
+     assert_eq!(div_rem(0xeeee, 0xffff), (Big::from_small(0), Big::from_u64(0xeeee)));
+     assert_eq!(div_rem(2_000_000, 2), (Big::from_u64(1_000_000), Big::from_u64(0)));
+ }
+ 
+ #[test]
+ fn test_is_zero() {
+     assert!(Big::from_small(0).is_zero());
+     assert!(!Big::from_small(3).is_zero());
+     assert!(!Big::from_u64(0x123).is_zero());
+     assert!(!Big::from_u64(0xffffff).sub(&Big::from_u64(0xfffffe)).is_zero());
+     assert!(Big::from_u64(0xffffff).sub(&Big::from_u64(0xffffff)).is_zero());
+ }
+ 
+ #[test]
+ fn test_get_bit() {
+     let x = Big::from_small(0b1101);
+     assert_eq!(x.get_bit(0), 1);
+     assert_eq!(x.get_bit(1), 0);
+     assert_eq!(x.get_bit(2), 1);
+     assert_eq!(x.get_bit(3), 1);
+     let y = Big::from_u64(1 << 15);
+     assert_eq!(y.get_bit(14), 0);
+     assert_eq!(y.get_bit(15), 1);
+     assert_eq!(y.get_bit(16), 0);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_get_bit_out_of_range() {
+     Big::from_small(42).get_bit(24);
+ }
+ 
+ #[test]
+ fn test_bit_length() {
+     assert_eq!(Big::from_small(0).bit_length(), 0);
+     assert_eq!(Big::from_small(1).bit_length(), 1);
+     assert_eq!(Big::from_small(5).bit_length(), 3);
+     assert_eq!(Big::from_small(0x18).bit_length(), 5);
+     assert_eq!(Big::from_u64(0x4073).bit_length(), 15);
+     assert_eq!(Big::from_u64(0xffffff).bit_length(), 24);
+ }
+ 
+ #[test]
+ fn test_ord() {
+     assert!(Big::from_u64(0) < Big::from_u64(0xffffff));
+     assert!(Big::from_u64(0x102) < Big::from_u64(0x201));
+ }
+ 
+ #[test]
+ fn test_fmt() {
+     assert_eq!(format!("{:?}", Big::from_u64(0)), "0x0");
+     assert_eq!(format!("{:?}", Big::from_u64(0x1)), "0x1");
+     assert_eq!(format!("{:?}", Big::from_u64(0x12)), "0x12");
+     assert_eq!(format!("{:?}", Big::from_u64(0x123)), "0x1_23");
+     assert_eq!(format!("{:?}", Big::from_u64(0x1234)), "0x12_34");
+     assert_eq!(format!("{:?}", Big::from_u64(0x12345)), "0x1_23_45");
+     assert_eq!(format!("{:?}", Big::from_u64(0x123456)), "0x12_34_56");
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/dec2flt/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/dec2flt/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/dec2flt/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/dec2flt/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,155 ----
+ #![allow(overflowing_literals)]
+ 
+ mod parse;
+ mod rawfp;
+ 
+ // Take a float literal, turn it into a string in various ways (that are all trusted
+ // to be correct) and see if those strings are parsed back to the value of the literal.
+ // Requires a *polymorphic literal*, i.e., one that can serve as f64 as well as f32.
+ macro_rules! test_literal {
+     ($x: expr) => {{
+         let x32: f32 = $x;
+         let x64: f64 = $x;
+         let inputs = &[stringify!($x).into(), format!("{:?}", x64), format!("{:e}", x64)];
+         for input in inputs {
+             assert_eq!(input.parse(), Ok(x64));
+             assert_eq!(input.parse(), Ok(x32));
+             let neg_input = &format!("-{}", input);
+             assert_eq!(neg_input.parse(), Ok(-x64));
+             assert_eq!(neg_input.parse(), Ok(-x32));
+         }
+     }};
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn ordinary() {
+     test_literal!(1.0);
+     test_literal!(3e-5);
+     test_literal!(0.1);
+     test_literal!(12345.);
+     test_literal!(0.9999999);
+ 
+     if cfg!(miri) {
+         // Miri is too slow
+         return;
+     }
+ 
+     test_literal!(2.2250738585072014e-308);
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn special_code_paths() {
+     test_literal!(36893488147419103229.0); // 2^65 - 3, triggers half-to-even with even significand
+     test_literal!(101e-33); // Triggers the tricky underflow case in AlgorithmM (for f32)
+     test_literal!(1e23); // Triggers AlgorithmR
+     test_literal!(2075e23); // Triggers another path through AlgorithmR
+     test_literal!(8713e-23); // ... and yet another.
+ }
+ 
+ #[test]
+ fn large() {
+     test_literal!(1e300);
+     test_literal!(123456789.34567e250);
+     test_literal!(943794359898089732078308743689303290943794359843568973207830874368930329.);
+ }
+ 
+ #[test]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn subnormals() {
+     test_literal!(5e-324);
+     test_literal!(91e-324);
+     test_literal!(1e-322);
+     test_literal!(13245643e-320);
+     test_literal!(2.22507385851e-308);
+     test_literal!(2.1e-308);
+     test_literal!(4.9406564584124654e-324);
+ }
+ 
+ #[test]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn infinity() {
+     test_literal!(1e400);
+     test_literal!(1e309);
+     test_literal!(2e308);
+     test_literal!(1.7976931348624e308);
+ }
+ 
+ #[test]
+ fn zero() {
+     test_literal!(0.0);
+     test_literal!(1e-325);
+ 
+     if cfg!(miri) {
+         // Miri is too slow
+         return;
+     }
+ 
+     test_literal!(1e-326);
+     test_literal!(1e-500);
+ }
+ 
+ #[test]
+ fn fast_path_correct() {
+     // This number triggers the fast path and is handled incorrectly when compiling on
+     // x86 without SSE2 (i.e., using the x87 FPU stack).
+     test_literal!(1.448997445238699);
+ }
+ 
+ #[test]
+ fn lonely_dot() {
+     assert!(".".parse::<f32>().is_err());
+     assert!(".".parse::<f64>().is_err());
+ }
+ 
+ #[test]
+ fn exponentiated_dot() {
+     assert!(".e0".parse::<f32>().is_err());
+     assert!(".e0".parse::<f64>().is_err());
+ }
+ 
+ #[test]
+ fn lonely_sign() {
+     assert!("+".parse::<f32>().is_err());
+     assert!("-".parse::<f64>().is_err());
+ }
+ 
+ #[test]
+ fn whitespace() {
+     assert!(" 1.0".parse::<f32>().is_err());
+     assert!("1.0 ".parse::<f64>().is_err());
+ }
+ 
+ #[test]
+ fn nan() {
+     assert!("NaN".parse::<f32>().unwrap().is_nan());
+     assert!("NaN".parse::<f64>().unwrap().is_nan());
+ }
+ 
+ #[test]
+ fn inf() {
+     assert_eq!("inf".parse(), Ok(f64::INFINITY));
+     assert_eq!("-inf".parse(), Ok(f64::NEG_INFINITY));
+     assert_eq!("inf".parse(), Ok(f32::INFINITY));
+     assert_eq!("-inf".parse(), Ok(f32::NEG_INFINITY));
+ }
+ 
+ #[test]
+ fn massive_exponent() {
+     let max = i64::MAX;
+     assert_eq!(format!("1e{}000", max).parse(), Ok(f64::INFINITY));
+     assert_eq!(format!("1e-{}000", max).parse(), Ok(0.0));
+     assert_eq!(format!("1e{}000", max).parse(), Ok(f64::INFINITY));
+ }
+ 
+ #[test]
+ fn borderline_overflow() {
+     let mut s = "0.".to_string();
+     for _ in 0..375 {
+         s.push('3');
+     }
+     // At the time of this writing, this returns Err(..), but this is a bug that should be fixed.
+     // It makes no sense to enshrine that in a test, the important part is that it doesn't panic.
+     let _ = s.parse::<f64>();
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/dec2flt/parse.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/dec2flt/parse.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/dec2flt/parse.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/dec2flt/parse.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,41 ----
+ use core::num::dec2flt::parse::ParseResult::{Invalid, Valid};
+ use core::num::dec2flt::parse::{parse_decimal, Decimal};
+ 
+ #[test]
+ fn missing_pieces() {
+     let permutations = &[".e", "1e", "e4", "e", ".12e", "321.e", "32.12e+", "12.32e-"];
+     for &s in permutations {
+         assert_eq!(parse_decimal(s), Invalid);
+     }
+ }
+ 
+ #[test]
+ fn invalid_chars() {
+     let invalid = "r,?<j";
+     let valid_strings = &["123", "666.", ".1", "5e1", "7e-3", "0.0e+1"];
+     for c in invalid.chars() {
+         for s in valid_strings {
+             for i in 0..s.len() {
+                 let mut input = String::new();
+                 input.push_str(s);
+                 input.insert(i, c);
+                 assert!(parse_decimal(&input) == Invalid, "did not reject invalid {:?}", input);
+             }
+         }
+     }
+ }
+ 
+ #[test]
+ fn valid() {
+     assert_eq!(parse_decimal("123.456e789"), Valid(Decimal::new(b"123", b"456", 789)));
+     assert_eq!(parse_decimal("123.456e+789"), Valid(Decimal::new(b"123", b"456", 789)));
+     assert_eq!(parse_decimal("123.456e-789"), Valid(Decimal::new(b"123", b"456", -789)));
+     assert_eq!(parse_decimal(".050"), Valid(Decimal::new(b"", b"050", 0)));
+     assert_eq!(parse_decimal("999"), Valid(Decimal::new(b"999", b"", 0)));
+     assert_eq!(parse_decimal("1.e300"), Valid(Decimal::new(b"1", b"", 300)));
+     assert_eq!(parse_decimal(".1e300"), Valid(Decimal::new(b"", b"1", 300)));
+     assert_eq!(parse_decimal("101e-33"), Valid(Decimal::new(b"101", b"", -33)));
+     let zeros = "0".repeat(25);
+     let s = format!("1.5e{}", zeros);
+     assert_eq!(parse_decimal(&s), Valid(Decimal::new(b"1", b"5", 0)));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/dec2flt/rawfp.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/dec2flt/rawfp.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/dec2flt/rawfp.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/dec2flt/rawfp.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,175 ----
+ use core::num::dec2flt::rawfp::RawFloat;
+ use core::num::dec2flt::rawfp::{fp_to_float, next_float, prev_float, round_normal};
+ use core::num::diy_float::Fp;
+ 
+ fn integer_decode(f: f64) -> (u64, i16, i8) {
+     RawFloat::integer_decode(f)
+ }
+ 
+ #[test]
+ fn fp_to_float_half_to_even() {
+     fn is_normalized(sig: u64) -> bool {
+         // intentionally written without {min,max}_sig() as a sanity check
+         sig >> 52 == 1 && sig >> 53 == 0
+     }
+ 
+     fn conv(sig: u64) -> u64 {
+         // The significands are perfectly in range, so the exponent should not matter
+         let (m1, e1, _) = integer_decode(fp_to_float::<f64>(Fp { f: sig, e: 0 }));
+         assert_eq!(e1, 0 + 64 - 53);
+         let (m2, e2, _) = integer_decode(fp_to_float::<f64>(Fp { f: sig, e: 55 }));
+         assert_eq!(e2, 55 + 64 - 53);
+         assert_eq!(m2, m1);
+         let (m3, e3, _) = integer_decode(fp_to_float::<f64>(Fp { f: sig, e: -78 }));
+         assert_eq!(e3, -78 + 64 - 53);
+         assert_eq!(m3, m2);
+         m3
+     }
+ 
+     let odd = 0x1F_EDCB_A012_345F;
+     let even = odd - 1;
+     assert!(is_normalized(odd));
+     assert!(is_normalized(even));
+     assert_eq!(conv(odd << 11), odd);
+     assert_eq!(conv(even << 11), even);
+     assert_eq!(conv(odd << 11 | 1 << 10), odd + 1);
+     assert_eq!(conv(even << 11 | 1 << 10), even);
+     assert_eq!(conv(even << 11 | 1 << 10 | 1), even + 1);
+     assert_eq!(conv(odd << 11 | 1 << 9), odd);
+     assert_eq!(conv(even << 11 | 1 << 9), even);
+     assert_eq!(conv(odd << 11 | 0x7FF), odd + 1);
+     assert_eq!(conv(even << 11 | 0x7FF), even + 1);
+     assert_eq!(conv(odd << 11 | 0x3FF), odd);
+     assert_eq!(conv(even << 11 | 0x3FF), even);
+ }
+ 
+ #[test]
+ fn integers_to_f64() {
+     assert_eq!(fp_to_float::<f64>(Fp { f: 1, e: 0 }), 1.0);
+     assert_eq!(fp_to_float::<f64>(Fp { f: 42, e: 7 }), (42 << 7) as f64);
+     assert_eq!(fp_to_float::<f64>(Fp { f: 1 << 20, e: 30 }), (1u64 << 50) as f64);
+     assert_eq!(fp_to_float::<f64>(Fp { f: 4, e: -3 }), 0.5);
+ }
+ 
+ const SOME_FLOATS: [f64; 9] = [
+     0.1f64,
+     33.568,
+     42.1e-5,
+     777.0e9,
+     1.1111,
+     0.347997,
+     9843579834.35892,
+     12456.0e-150,
+     54389573.0e-150,
+ ];
+ 
+ #[test]
+ fn human_f64_roundtrip() {
+     for &x in &SOME_FLOATS {
+         let (f, e, _) = integer_decode(x);
+         let fp = Fp { f: f, e: e };
+         assert_eq!(fp_to_float::<f64>(fp), x);
+     }
+ }
+ 
+ #[test]
+ fn rounding_overflow() {
+     let x = Fp { f: 0xFF_FF_FF_FF_FF_FF_FF_00u64, e: 42 };
+     let rounded = round_normal::<f64>(x);
+     let adjusted_k = x.e + 64 - 53;
+     assert_eq!(rounded.sig, 1 << 52);
+     assert_eq!(rounded.k, adjusted_k + 1);
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn prev_float_monotonic() {
+     let mut x = 1.0;
+     for _ in 0..100 {
+         let x1 = prev_float(x);
+         assert!(x1 < x);
+         assert!(x - x1 < 1e-15);
+         x = x1;
+     }
+ }
+ 
+ const MIN_SUBNORMAL: f64 = 5e-324;
+ 
+ #[test]
+ fn next_float_zero() {
+     let tiny = next_float(0.0);
+     assert_eq!(tiny, MIN_SUBNORMAL);
+     assert!(tiny != 0.0);
+ }
+ 
+ #[test]
+ fn next_float_subnormal() {
+     let second = next_float(MIN_SUBNORMAL);
+     // For subnormals, MIN_SUBNORMAL is the ULP
+     assert!(second != MIN_SUBNORMAL);
+     assert!(second > 0.0);
+     assert_eq!(second - MIN_SUBNORMAL, MIN_SUBNORMAL);
+ }
+ 
+ #[test]
+ fn next_float_inf() {
+     assert_eq!(next_float(f64::MAX), f64::INFINITY);
+     assert_eq!(next_float(f64::INFINITY), f64::INFINITY);
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn next_prev_identity() {
+     for &x in &SOME_FLOATS {
+         assert_eq!(prev_float(next_float(x)), x);
+         assert_eq!(prev_float(prev_float(next_float(next_float(x)))), x);
+         assert_eq!(next_float(prev_float(x)), x);
+         assert_eq!(next_float(next_float(prev_float(prev_float(x)))), x);
+     }
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn next_float_monotonic() {
+     let mut x = 0.49999999999999;
+     assert!(x < 0.5);
+     for _ in 0..200 {
+         let x1 = next_float(x);
+         assert!(x1 > x);
+         assert!(x1 - x < 1e-15, "next_float_monotonic: delta = {:?}", x1 - x);
+         x = x1;
+     }
+     assert!(x > 0.5);
+ }
+ 
+ #[test]
+ fn test_f32_integer_decode() {
+     assert_eq!(3.14159265359f32.integer_decode(), (13176795, -22, 1));
+     assert_eq!((-8573.5918555f32).integer_decode(), (8779358, -10, -1));
+     assert_eq!(2f32.powf(100.0).integer_decode(), (8388608, 77, 1));
+     assert_eq!(0f32.integer_decode(), (0, -150, 1));
+     assert_eq!((-0f32).integer_decode(), (0, -150, -1));
+     assert_eq!(f32::INFINITY.integer_decode(), (8388608, 105, 1));
+     assert_eq!(f32::NEG_INFINITY.integer_decode(), (8388608, 105, -1));
+ 
+     // Ignore the "sign" (quiet / signalling flag) of NAN.
+     // It can vary between runtime operations and LLVM folding.
+     let (nan_m, nan_e, _nan_s) = f32::NAN.integer_decode();
+     assert_eq!((nan_m, nan_e), (12582912, 105));
+ }
+ 
+ #[test]
+ fn test_f64_integer_decode() {
+     assert_eq!(3.14159265359f64.integer_decode(), (7074237752028906, -51, 1));
+     assert_eq!((-8573.5918555f64).integer_decode(), (4713381968463931, -39, -1));
+     assert_eq!(2f64.powf(100.0).integer_decode(), (4503599627370496, 48, 1));
+     assert_eq!(0f64.integer_decode(), (0, -1075, 1));
+     assert_eq!((-0f64).integer_decode(), (0, -1075, -1));
+     assert_eq!(f64::INFINITY.integer_decode(), (4503599627370496, 972, 1));
+     assert_eq!(f64::NEG_INFINITY.integer_decode(), (4503599627370496, 972, -1));
+ 
+     // Ignore the "sign" (quiet / signalling flag) of NAN.
+     // It can vary between runtime operations and LLVM folding.
+     let (nan_m, nan_e, _nan_s) = f64::NAN.integer_decode();
+     assert_eq!((nan_m, nan_e), (6755399441055744, 972));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/estimator.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/estimator.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/estimator.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/estimator.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,62 ----
+ use core::num::flt2dec::estimator::*;
+ 
+ #[test]
+ fn test_estimate_scaling_factor() {
+     macro_rules! assert_almost_eq {
+         ($actual:expr, $expected:expr) => {{
+             let actual = $actual;
+             let expected = $expected;
+             println!(
+                 "{} - {} = {} - {} = {}",
+                 stringify!($expected),
+                 stringify!($actual),
+                 expected,
+                 actual,
+                 expected - actual
+             );
+             assert!(
+                 expected == actual || expected == actual + 1,
+                 "expected {}, actual {}",
+                 expected,
+                 actual
+             );
+         }};
+     }
+ 
+     assert_almost_eq!(estimate_scaling_factor(1, 0), 0);
+     assert_almost_eq!(estimate_scaling_factor(2, 0), 1);
+     assert_almost_eq!(estimate_scaling_factor(10, 0), 1);
+     assert_almost_eq!(estimate_scaling_factor(11, 0), 2);
+     assert_almost_eq!(estimate_scaling_factor(100, 0), 2);
+     assert_almost_eq!(estimate_scaling_factor(101, 0), 3);
+     assert_almost_eq!(estimate_scaling_factor(10000000000000000000, 0), 19);
+     assert_almost_eq!(estimate_scaling_factor(10000000000000000001, 0), 20);
+ 
+     // 1/2^20 = 0.00000095367...
+     assert_almost_eq!(estimate_scaling_factor(1 * 1048576 / 1000000, -20), -6);
+     assert_almost_eq!(estimate_scaling_factor(1 * 1048576 / 1000000 + 1, -20), -5);
+     assert_almost_eq!(estimate_scaling_factor(10 * 1048576 / 1000000, -20), -5);
+     assert_almost_eq!(estimate_scaling_factor(10 * 1048576 / 1000000 + 1, -20), -4);
+     assert_almost_eq!(estimate_scaling_factor(100 * 1048576 / 1000000, -20), -4);
+     assert_almost_eq!(estimate_scaling_factor(100 * 1048576 / 1000000 + 1, -20), -3);
+     assert_almost_eq!(estimate_scaling_factor(1048575, -20), 0);
+     assert_almost_eq!(estimate_scaling_factor(1048576, -20), 0);
+     assert_almost_eq!(estimate_scaling_factor(1048577, -20), 1);
+     assert_almost_eq!(estimate_scaling_factor(10485759999999999999, -20), 13);
+     assert_almost_eq!(estimate_scaling_factor(10485760000000000000, -20), 13);
+     assert_almost_eq!(estimate_scaling_factor(10485760000000000001, -20), 14);
+ 
+     // extreme values:
+     // 2^-1074 = 4.94065... * 10^-324
+     // (2^53-1) * 2^971 = 1.79763... * 10^308
+     assert_almost_eq!(estimate_scaling_factor(1, -1074), -323);
+     assert_almost_eq!(estimate_scaling_factor(0x1fffffffffffff, 971), 309);
+ 
+     // Miri is too slow
+     let step = if cfg!(miri) { 37 } else { 1 };
+ 
+     for i in (-1074..972).step_by(step) {
+         let expected = super::ldexp_f64(1.0, i).log10().ceil();
+         assert_almost_eq!(estimate_scaling_factor(1, i as i16), expected as i16);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1241 ----
+ use std::mem::MaybeUninit;
+ use std::{fmt, str};
+ 
+ use core::num::flt2dec::{decode, DecodableFloat, Decoded, FullDecoded};
+ use core::num::flt2dec::{round_up, Formatted, Part, Sign, MAX_SIG_DIGITS};
+ use core::num::flt2dec::{
+     to_exact_exp_str, to_exact_fixed_str, to_shortest_exp_str, to_shortest_str,
+ };
+ 
+ pub use test::Bencher;
+ 
+ mod estimator;
+ mod strategy {
+     mod dragon;
+     mod grisu;
+ }
+ mod random;
+ 
+ pub fn decode_finite<T: DecodableFloat>(v: T) -> Decoded {
+     match decode(v).1 {
+         FullDecoded::Finite(decoded) => decoded,
+         full_decoded => panic!("expected finite, got {:?} instead", full_decoded),
+     }
+ }
+ 
+ macro_rules! check_shortest {
+     ($f:ident($v:expr) => $buf:expr, $exp:expr) => (
+         check_shortest!($f($v) => $buf, $exp;
+                         "shortest mismatch for v={v}: actual {actual:?}, expected {expected:?}",
+                         v = stringify!($v))
+     );
+ 
+     ($f:ident{$($k:ident: $v:expr),+} => $buf:expr, $exp:expr) => (
+         check_shortest!($f{$($k: $v),+} => $buf, $exp;
+                         "shortest mismatch for {v:?}: actual {actual:?}, expected {expected:?}",
+                         v = Decoded { $($k: $v),+ })
+     );
+ 
+     ($f:ident($v:expr) => $buf:expr, $exp:expr; $fmt:expr, $($key:ident = $val:expr),*) => ({
+         let mut buf = [MaybeUninit::new(b'_'); MAX_SIG_DIGITS];
+         let (buf, k) = $f(&decode_finite($v), &mut buf);
+         assert!((buf, k) == ($buf, $exp),
+                 $fmt, actual = (str::from_utf8(buf).unwrap(), k),
+                       expected = (str::from_utf8($buf).unwrap(), $exp),
+                       $($key = $val),*);
+     });
+ 
+     ($f:ident{$($k:ident: $v:expr),+} => $buf:expr, $exp:expr;
+                                          $fmt:expr, $($key:ident = $val:expr),*) => ({
+         let mut buf = [MaybeUninit::new(b'_'); MAX_SIG_DIGITS];
+         let (buf, k) = $f(&Decoded { $($k: $v),+ }, &mut buf);
+         assert!((buf, k) == ($buf, $exp),
+                 $fmt, actual = (str::from_utf8(buf).unwrap(), k),
+                       expected = (str::from_utf8($buf).unwrap(), $exp),
+                       $($key = $val),*);
+     })
+ }
+ 
+ macro_rules! try_exact {
+     ($f:ident($decoded:expr) => $buf:expr, $expected:expr, $expectedk:expr;
+                                 $fmt:expr, $($key:ident = $val:expr),*) => ({
+         let (buf, k) = $f($decoded, &mut $buf[..$expected.len()], i16::MIN);
+         assert!((buf, k) == ($expected, $expectedk),
+                 $fmt, actual = (str::from_utf8(buf).unwrap(), k),
+                       expected = (str::from_utf8($expected).unwrap(), $expectedk),
+                       $($key = $val),*);
+     })
+ }
+ 
+ macro_rules! try_fixed {
+     ($f:ident($decoded:expr) => $buf:expr, $request:expr, $expected:expr, $expectedk:expr;
+                                 $fmt:expr, $($key:ident = $val:expr),*) => ({
+         let (buf, k) = $f($decoded, &mut $buf[..], $request);
+         assert!((buf, k) == ($expected, $expectedk),
+                 $fmt, actual = (str::from_utf8(buf).unwrap(), k),
+                       expected = (str::from_utf8($expected).unwrap(), $expectedk),
+                       $($key = $val),*);
+     })
+ }
+ 
+ fn ldexp_f32(a: f32, b: i32) -> f32 {
+     ldexp_f64(a as f64, b) as f32
+ }
+ 
+ fn ldexp_f64(a: f64, b: i32) -> f64 {
+     extern "C" {
+         fn ldexp(x: f64, n: i32) -> f64;
+     }
+     // SAFETY: assuming a correct `ldexp` has been supplied, the given arguments cannot possibly
+     // cause undefined behavior
+     unsafe { ldexp(a, b) }
+ }
+ 
+ fn check_exact<F, T>(mut f: F, v: T, vstr: &str, expected: &[u8], expectedk: i16)
+ where
+     T: DecodableFloat,
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     // use a large enough buffer
+     let mut buf = [MaybeUninit::new(b'_'); 1024];
+     let mut expected_ = [b'_'; 1024];
+ 
+     let decoded = decode_finite(v);
+     let cut = expected.iter().position(|&c| c == b' ');
+ 
+     // check significant digits
+     for i in 1..cut.unwrap_or(expected.len() - 1) {
+         expected_[..i].copy_from_slice(&expected[..i]);
+         let mut expectedk_ = expectedk;
+         if expected[i] >= b'5' {
+             // check if this is a rounding-to-even case.
+             // we avoid rounding ...x5000... (with infinite zeroes) to ...(x+1) when x is even.
+             if !(i + 1 < expected.len()
+                 && expected[i - 1] & 1 == 0
+                 && expected[i] == b'5'
+                 && expected[i + 1] == b' ')
+             {
+                 // if this returns true, expected_[..i] is all `9`s and being rounded up.
+                 // we should always return `100..00` (`i` digits) instead, since that's
+                 // what we can came up with `i` digits anyway. `round_up` assumes that
+                 // the adjustment to the length is done by caller, which we simply ignore.
+                 if let Some(_) = round_up(&mut expected_[..i]) {
+                     expectedk_ += 1;
+                 }
+             }
+         }
+ 
+         try_exact!(f(&decoded) => &mut buf, &expected_[..i], expectedk_;
+                    "exact sigdigit mismatch for v={v}, i={i}: \
+                     actual {actual:?}, expected {expected:?}",
+                    v = vstr, i = i);
+         try_fixed!(f(&decoded) => &mut buf, expectedk_ - i as i16, &expected_[..i], expectedk_;
+                    "fixed sigdigit mismatch for v={v}, i={i}: \
+                     actual {actual:?}, expected {expected:?}",
+                    v = vstr, i = i);
+     }
+ 
+     // check exact rounding for zero- and negative-width cases
+     let start;
+     if expected[0] >= b'5' {
+         try_fixed!(f(&decoded) => &mut buf, expectedk, b"1", expectedk + 1;
+                    "zero-width rounding-up mismatch for v={v}: \
+                     actual {actual:?}, expected {expected:?}",
+                    v = vstr);
+         start = 1;
+     } else {
+         start = 0;
+     }
+     for i in start..-10 {
+         try_fixed!(f(&decoded) => &mut buf, expectedk - i, b"", expectedk;
+                    "rounding-down mismatch for v={v}, i={i}: \
+                     actual {actual:?}, expected {expected:?}",
+                    v = vstr, i = -i);
+     }
+ 
+     // check infinite zero digits
+     if let Some(cut) = cut {
+         for i in cut..expected.len() - 1 {
+             expected_[..cut].copy_from_slice(&expected[..cut]);
+             for c in &mut expected_[cut..i] {
+                 *c = b'0';
+             }
+ 
+             try_exact!(f(&decoded) => &mut buf, &expected_[..i], expectedk;
+                        "exact infzero mismatch for v={v}, i={i}: \
+                         actual {actual:?}, expected {expected:?}",
+                        v = vstr, i = i);
+             try_fixed!(f(&decoded) => &mut buf, expectedk - i as i16, &expected_[..i], expectedk;
+                        "fixed infzero mismatch for v={v}, i={i}: \
+                         actual {actual:?}, expected {expected:?}",
+                        v = vstr, i = i);
+         }
+     }
+ }
+ 
+ trait TestableFloat: DecodableFloat + fmt::Display {
+     /// Returns `x * 2^exp`. Almost same to `std::{f32,f64}::ldexp`.
+     /// This is used for testing.
+     fn ldexpi(f: i64, exp: isize) -> Self;
+ }
+ 
+ impl TestableFloat for f32 {
+     fn ldexpi(f: i64, exp: isize) -> Self {
+         f as Self * (exp as Self).exp2()
+     }
+ }
+ 
+ impl TestableFloat for f64 {
+     fn ldexpi(f: i64, exp: isize) -> Self {
+         f as Self * (exp as Self).exp2()
+     }
+ }
+ 
+ fn check_exact_one<F, T>(mut f: F, x: i64, e: isize, tstr: &str, expected: &[u8], expectedk: i16)
+ where
+     T: TestableFloat,
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     // use a large enough buffer
+     let mut buf = [MaybeUninit::new(b'_'); 1024];
+     let v: T = TestableFloat::ldexpi(x, e);
+     let decoded = decode_finite(v);
+ 
+     try_exact!(f(&decoded) => &mut buf, &expected, expectedk;
+                "exact mismatch for v={x}p{e}{t}: actual {actual:?}, expected {expected:?}",
+                x = x, e = e, t = tstr);
+     try_fixed!(f(&decoded) => &mut buf, expectedk - expected.len() as i16, &expected, expectedk;
+                "fixed mismatch for v={x}p{e}{t}: actual {actual:?}, expected {expected:?}",
+                x = x, e = e, t = tstr);
+ }
+ 
+ macro_rules! check_exact {
+     ($f:ident($v:expr) => $buf:expr, $exp:expr) => {
+         check_exact(|d, b, k| $f(d, b, k), $v, stringify!($v), $buf, $exp)
+     };
+ }
+ 
+ macro_rules! check_exact_one {
+     ($f:ident($x:expr, $e:expr; $t:ty) => $buf:expr, $exp:expr) => {
+         check_exact_one::<_, $t>(|d, b, k| $f(d, b, k), $x, $e, stringify!($t), $buf, $exp)
+     };
+ }
+ 
+ // in the following comments, three numbers are spaced by 1 ulp apart,
+ // and the second one is being formatted.
+ //
+ // some tests are derived from [1].
+ //
+ // [1] Vern Paxson, A Program for Testing IEEE Decimal-Binary Conversion
+ //     ftp://ftp.ee.lbl.gov/testbase-report.ps.Z
+ 
+ pub fn f32_shortest_sanity_test<F>(mut f: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     // 0.0999999940395355224609375
+     // 0.100000001490116119384765625
+     // 0.10000000894069671630859375
+     check_shortest!(f(0.1f32) => b"1", 0);
+ 
+     // 0.333333313465118408203125
+     // 0.3333333432674407958984375 (1/3 in the default rounding)
+     // 0.33333337306976318359375
+     check_shortest!(f(1.0f32/3.0) => b"33333334", 0);
+ 
+     // 10^1 * 0.31415917873382568359375
+     // 10^1 * 0.31415920257568359375
+     // 10^1 * 0.31415922641754150390625
+     check_shortest!(f(3.141592f32) => b"3141592", 1);
+ 
+     // 10^18 * 0.31415916243714048
+     // 10^18 * 0.314159196796878848
+     // 10^18 * 0.314159231156617216
+     check_shortest!(f(3.141592e17f32) => b"3141592", 18);
+ 
+     // regression test for decoders
+     // 10^8 * 0.3355443
+     // 10^8 * 0.33554432
+     // 10^8 * 0.33554436
+     check_shortest!(f(ldexp_f32(1.0, 25)) => b"33554432", 8);
+ 
+     // 10^39 * 0.340282326356119256160033759537265639424
+     // 10^39 * 0.34028234663852885981170418348451692544
+     // 10^39 * 0.340282366920938463463374607431768211456
+     check_shortest!(f(f32::MAX) => b"34028235", 39);
+ 
+     // 10^-37 * 0.1175494210692441075487029444849287348827...
+     // 10^-37 * 0.1175494350822287507968736537222245677818...
+     // 10^-37 * 0.1175494490952133940450443629595204006810...
+     check_shortest!(f(f32::MIN_POSITIVE) => b"11754944", -37);
+ 
+     // 10^-44 * 0
+     // 10^-44 * 0.1401298464324817070923729583289916131280...
+     // 10^-44 * 0.2802596928649634141847459166579832262560...
+     let minf32 = ldexp_f32(1.0, -149);
+     check_shortest!(f(minf32) => b"1", -44);
+ }
+ 
+ pub fn f32_exact_sanity_test<F>(mut f: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     let minf32 = ldexp_f32(1.0, -149);
+ 
+     check_exact!(f(0.1f32)            => b"100000001490116119384765625             ", 0);
+     check_exact!(f(0.5f32)            => b"5                                       ", 0);
+     check_exact!(f(1.0f32/3.0)        => b"3333333432674407958984375               ", 0);
+     check_exact!(f(3.141592f32)       => b"31415920257568359375                    ", 1);
+     check_exact!(f(3.141592e17f32)    => b"314159196796878848                      ", 18);
+     check_exact!(f(f32::MAX)          => b"34028234663852885981170418348451692544  ", 39);
+     check_exact!(f(f32::MIN_POSITIVE) => b"1175494350822287507968736537222245677818", -37);
+     check_exact!(f(minf32)            => b"1401298464324817070923729583289916131280", -44);
+ 
+     // [1], Table 16: Stress Inputs for Converting 24-bit Binary to Decimal, < 1/2 ULP
+     check_exact_one!(f(12676506, -102; f32) => b"2",            -23);
+     check_exact_one!(f(12676506, -103; f32) => b"12",           -23);
+     check_exact_one!(f(15445013,   86; f32) => b"119",           34);
+     check_exact_one!(f(13734123, -138; f32) => b"3941",         -34);
+     check_exact_one!(f(12428269, -130; f32) => b"91308",        -32);
+     check_exact_one!(f(15334037, -146; f32) => b"171900",       -36);
+     check_exact_one!(f(11518287,  -41; f32) => b"5237910",       -5);
+     check_exact_one!(f(12584953, -145; f32) => b"28216440",     -36);
+     check_exact_one!(f(15961084, -125; f32) => b"375243281",    -30);
+     check_exact_one!(f(14915817, -146; f32) => b"1672120916",   -36);
+     check_exact_one!(f(10845484, -102; f32) => b"21388945814",  -23);
+     check_exact_one!(f(16431059,  -61; f32) => b"712583594561", -11);
+ 
+     // [1], Table 17: Stress Inputs for Converting 24-bit Binary to Decimal, > 1/2 ULP
+     check_exact_one!(f(16093626,   69; f32) => b"1",             29);
+     check_exact_one!(f( 9983778,   25; f32) => b"34",            15);
+     check_exact_one!(f(12745034,  104; f32) => b"259",           39);
+     check_exact_one!(f(12706553,   72; f32) => b"6001",          29);
+     check_exact_one!(f(11005028,   45; f32) => b"38721",         21);
+     check_exact_one!(f(15059547,   71; f32) => b"355584",        29);
+     check_exact_one!(f(16015691,  -99; f32) => b"2526831",      -22);
+     check_exact_one!(f( 8667859,   56; f32) => b"62458507",      24);
+     check_exact_one!(f(14855922,  -82; f32) => b"307213267",    -17);
+     check_exact_one!(f(14855922,  -83; f32) => b"1536066333",   -17);
+     check_exact_one!(f(10144164, -110; f32) => b"78147796834",  -26);
+     check_exact_one!(f(13248074,   95; f32) => b"524810279937",  36);
+ }
+ 
+ pub fn f64_shortest_sanity_test<F>(mut f: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     // 0.0999999999999999777955395074968691915273...
+     // 0.1000000000000000055511151231257827021181...
+     // 0.1000000000000000333066907387546962127089...
+     check_shortest!(f(0.1f64) => b"1", 0);
+ 
+     // this example is explicitly mentioned in the paper.
+     // 10^3 * 0.0999999999999999857891452847979962825775...
+     // 10^3 * 0.1 (exact)
+     // 10^3 * 0.1000000000000000142108547152020037174224...
+     check_shortest!(f(100.0f64) => b"1", 3);
+ 
+     // 0.3333333333333332593184650249895639717578...
+     // 0.3333333333333333148296162562473909929394... (1/3 in the default rounding)
+     // 0.3333333333333333703407674875052180141210...
+     check_shortest!(f(1.0f64/3.0) => b"3333333333333333", 0);
+ 
+     // explicit test case for equally closest representations.
+     // Dragon has its own tie-breaking rule; Grisu should fall back.
+     // 10^1 * 0.1000007629394531027955395074968691915273...
+     // 10^1 * 0.100000762939453125 (exact)
+     // 10^1 * 0.1000007629394531472044604925031308084726...
+     check_shortest!(f(1.00000762939453125f64) => b"10000076293945313", 1);
+ 
+     // 10^1 * 0.3141591999999999718085064159822650253772...
+     // 10^1 * 0.3141592000000000162174274009885266423225...
+     // 10^1 * 0.3141592000000000606263483859947882592678...
+     check_shortest!(f(3.141592f64) => b"3141592", 1);
+ 
+     // 10^18 * 0.314159199999999936
+     // 10^18 * 0.3141592 (exact)
+     // 10^18 * 0.314159200000000064
+     check_shortest!(f(3.141592e17f64) => b"3141592", 18);
+ 
+     // regression test for decoders
+     // 10^20 * 0.18446744073709549568
+     // 10^20 * 0.18446744073709551616
+     // 10^20 * 0.18446744073709555712
+     check_shortest!(f(ldexp_f64(1.0, 64)) => b"18446744073709552", 20);
+ 
+     // pathological case: high = 10^23 (exact). tie breaking should always prefer that.
+     // 10^24 * 0.099999999999999974834176
+     // 10^24 * 0.099999999999999991611392
+     // 10^24 * 0.100000000000000008388608
+     check_shortest!(f(1.0e23f64) => b"1", 24);
+ 
+     // 10^309 * 0.1797693134862315508561243283845062402343...
+     // 10^309 * 0.1797693134862315708145274237317043567980...
+     // 10^309 * 0.1797693134862315907729305190789024733617...
+     check_shortest!(f(f64::MAX) => b"17976931348623157", 309);
+ 
+     // 10^-307 * 0.2225073858507200889024586876085859887650...
+     // 10^-307 * 0.2225073858507201383090232717332404064219...
+     // 10^-307 * 0.2225073858507201877155878558578948240788...
+     check_shortest!(f(f64::MIN_POSITIVE) => b"22250738585072014", -307);
+ 
+     // 10^-323 * 0
+     // 10^-323 * 0.4940656458412465441765687928682213723650...
+     // 10^-323 * 0.9881312916824930883531375857364427447301...
+     let minf64 = ldexp_f64(1.0, -1074);
+     check_shortest!(f(minf64) => b"5", -323);
+ }
+ 
+ pub fn f64_exact_sanity_test<F>(mut f: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     let minf64 = ldexp_f64(1.0, -1074);
+ 
+     check_exact!(f(0.1f64)            => b"1000000000000000055511151231257827021181", 0);
+     check_exact!(f(0.45f64)           => b"4500000000000000111022302462515654042363", 0);
+     check_exact!(f(0.5f64)            => b"5                                       ", 0);
+     check_exact!(f(0.95f64)           => b"9499999999999999555910790149937383830547", 0);
+     check_exact!(f(100.0f64)          => b"1                                       ", 3);
+     check_exact!(f(999.5f64)          => b"9995000000000000000000000000000000000000", 3);
+     check_exact!(f(1.0f64/3.0)        => b"3333333333333333148296162562473909929394", 0);
+     check_exact!(f(3.141592f64)       => b"3141592000000000162174274009885266423225", 1);
+     check_exact!(f(3.141592e17f64)    => b"3141592                                 ", 18);
+     check_exact!(f(1.0e23f64)         => b"99999999999999991611392                 ", 23);
+     check_exact!(f(f64::MAX)          => b"1797693134862315708145274237317043567980", 309);
+     check_exact!(f(f64::MIN_POSITIVE) => b"2225073858507201383090232717332404064219", -307);
+     check_exact!(f(minf64)            => b"4940656458412465441765687928682213723650\
+                                            5980261432476442558568250067550727020875\
+                                            1865299836361635992379796564695445717730\
+                                            9266567103559397963987747960107818781263\
+                                            0071319031140452784581716784898210368871\
+                                            8636056998730723050006387409153564984387\
+                                            3124733972731696151400317153853980741262\
+                                            3856559117102665855668676818703956031062\
+                                            4931945271591492455329305456544401127480\
+                                            1297099995419319894090804165633245247571\
+                                            4786901472678015935523861155013480352649\
+                                            3472019379026810710749170333222684475333\
+                                            5720832431936092382893458368060106011506\
+                                            1698097530783422773183292479049825247307\
+                                            7637592724787465608477820373446969953364\
+                                            7017972677717585125660551199131504891101\
+                                            4510378627381672509558373897335989936648\
+                                            0994116420570263709027924276754456522908\
+                                            7538682506419718265533447265625         ", -323);
+ 
+     // [1], Table 3: Stress Inputs for Converting 53-bit Binary to Decimal, < 1/2 ULP
+     check_exact_one!(f(8511030020275656,  -342; f64) => b"9",                       -87);
+     check_exact_one!(f(5201988407066741,  -824; f64) => b"46",                     -232);
+     check_exact_one!(f(6406892948269899,   237; f64) => b"141",                      88);
+     check_exact_one!(f(8431154198732492,    72; f64) => b"3981",                     38);
+     check_exact_one!(f(6475049196144587,    99; f64) => b"41040",                    46);
+     check_exact_one!(f(8274307542972842,   726; f64) => b"292084",                  235);
+     check_exact_one!(f(5381065484265332,  -456; f64) => b"2891946",                -121);
+     check_exact_one!(f(6761728585499734, -1057; f64) => b"43787718",               -302);
+     check_exact_one!(f(7976538478610756,   376; f64) => b"122770163",               130);
+     check_exact_one!(f(5982403858958067,   377; f64) => b"1841552452",              130);
+     check_exact_one!(f(5536995190630837,    93; f64) => b"54835744350",              44);
+     check_exact_one!(f(7225450889282194,   710; f64) => b"389190181146",            230);
+     check_exact_one!(f(7225450889282194,   709; f64) => b"1945950905732",           230);
+     check_exact_one!(f(8703372741147379,   117; f64) => b"14460958381605",           52);
+     check_exact_one!(f(8944262675275217, -1001; f64) => b"417367747458531",        -285);
+     check_exact_one!(f(7459803696087692,  -707; f64) => b"1107950772878888",       -196);
+     check_exact_one!(f(6080469016670379,  -381; f64) => b"12345501366327440",       -98);
+     check_exact_one!(f(8385515147034757,   721; f64) => b"925031711960365024",      233);
+     check_exact_one!(f(7514216811389786,  -828; f64) => b"4198047150284889840",    -233);
+     check_exact_one!(f(8397297803260511,  -345; f64) => b"11716315319786511046",    -87);
+     check_exact_one!(f(6733459239310543,   202; f64) => b"432810072844612493629",    77);
+     check_exact_one!(f(8091450587292794,  -473; f64) => b"3317710118160031081518", -126);
+ 
+     // [1], Table 4: Stress Inputs for Converting 53-bit Binary to Decimal, > 1/2 ULP
+     check_exact_one!(f(6567258882077402,   952; f64) => b"3",                       303);
+     check_exact_one!(f(6712731423444934,   535; f64) => b"76",                      177);
+     check_exact_one!(f(6712731423444934,   534; f64) => b"378",                     177);
+     check_exact_one!(f(5298405411573037,  -957; f64) => b"4350",                   -272);
+     check_exact_one!(f(5137311167659507,  -144; f64) => b"23037",                   -27);
+     check_exact_one!(f(6722280709661868,   363; f64) => b"126301",                  126);
+     check_exact_one!(f(5344436398034927,  -169; f64) => b"7142211",                 -35);
+     check_exact_one!(f(8369123604277281,  -853; f64) => b"13934574",               -240);
+     check_exact_one!(f(8995822108487663,  -780; f64) => b"141463449",              -218);
+     check_exact_one!(f(8942832835564782,  -383; f64) => b"4539277920",              -99);
+     check_exact_one!(f(8942832835564782,  -384; f64) => b"22696389598",             -99);
+     check_exact_one!(f(8942832835564782,  -385; f64) => b"113481947988",            -99);
+     check_exact_one!(f(6965949469487146,  -249; f64) => b"7700366561890",           -59);
+     check_exact_one!(f(6965949469487146,  -250; f64) => b"38501832809448",          -59);
+     check_exact_one!(f(6965949469487146,  -251; f64) => b"192509164047238",         -59);
+     check_exact_one!(f(7487252720986826,   548; f64) => b"6898586531774201",        181);
+     check_exact_one!(f(5592117679628511,   164; f64) => b"13076622631878654",        66);
+     check_exact_one!(f(8887055249355788,   665; f64) => b"136052020756121240",      217);
+     check_exact_one!(f(6994187472632449,   690; f64) => b"3592810217475959676",     224);
+     check_exact_one!(f(8797576579012143,   588; f64) => b"89125197712484551899",    193);
+     check_exact_one!(f(7363326733505337,   272; f64) => b"558769757362301140950",    98);
+     check_exact_one!(f(8549497411294502,  -448; f64) => b"1176257830728540379990", -118);
+ }
+ 
+ pub fn more_shortest_sanity_test<F>(mut f: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     check_shortest!(f{mant: 99_999_999_999_999_999, minus: 1, plus: 1,
+                       exp: 0, inclusive: true} => b"1", 18);
+     check_shortest!(f{mant: 99_999_999_999_999_999, minus: 1, plus: 1,
+                       exp: 0, inclusive: false} => b"99999999999999999", 17);
+ }
+ 
+ fn to_string_with_parts<F>(mut f: F) -> String
+ where
+     F: for<'a> FnMut(&'a mut [MaybeUninit<u8>], &'a mut [MaybeUninit<Part<'a>>]) -> Formatted<'a>,
+ {
+     let mut buf = [MaybeUninit::new(0); 1024];
+     let mut parts = [MaybeUninit::new(Part::Zero(0)); 16];
+     let formatted = f(&mut buf, &mut parts);
+     let mut ret = vec![0; formatted.len()];
+     assert_eq!(formatted.write(&mut ret), Some(ret.len()));
+     String::from_utf8(ret).unwrap()
+ }
+ 
+ pub fn to_shortest_str_test<F>(mut f_: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     use core::num::flt2dec::Sign::*;
+ 
+     fn to_string<T, F>(f: &mut F, v: T, sign: Sign, frac_digits: usize) -> String
+     where
+         T: DecodableFloat,
+         F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+     {
+         to_string_with_parts(|buf, parts| {
+             to_shortest_str(|d, b| f(d, b), v, sign, frac_digits, buf, parts)
+         })
+     }
+ 
+     let f = &mut f_;
+ 
+     assert_eq!(to_string(f, 0.0, Minus, 0), "0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, 0), "0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, 0), "+0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, 0), "+0");
+     assert_eq!(to_string(f, -0.0, Minus, 0), "0");
+     assert_eq!(to_string(f, -0.0, MinusRaw, 0), "-0");
+     assert_eq!(to_string(f, -0.0, MinusPlus, 0), "+0");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, 0), "-0");
+     assert_eq!(to_string(f, 0.0, Minus, 1), "0.0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, 1), "0.0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, 1), "+0.0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, 1), "+0.0");
+     assert_eq!(to_string(f, -0.0, Minus, 8), "0.00000000");
+     assert_eq!(to_string(f, -0.0, MinusRaw, 8), "-0.00000000");
+     assert_eq!(to_string(f, -0.0, MinusPlus, 8), "+0.00000000");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, 8), "-0.00000000");
+ 
+     assert_eq!(to_string(f, 1.0 / 0.0, Minus, 0), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusRaw, 0), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlus, 0), "+inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlusRaw, 0), "+inf");
+     assert_eq!(to_string(f, 0.0 / 0.0, Minus, 0), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusRaw, 1), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlus, 8), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlusRaw, 64), "NaN");
+     assert_eq!(to_string(f, -1.0 / 0.0, Minus, 0), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusRaw, 1), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlus, 8), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlusRaw, 64), "-inf");
+ 
+     assert_eq!(to_string(f, 3.14, Minus, 0), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusRaw, 0), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusPlus, 0), "+3.14");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, 0), "+3.14");
+     assert_eq!(to_string(f, -3.14, Minus, 0), "-3.14");
+     assert_eq!(to_string(f, -3.14, MinusRaw, 0), "-3.14");
+     assert_eq!(to_string(f, -3.14, MinusPlus, 0), "-3.14");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, 0), "-3.14");
+     assert_eq!(to_string(f, 3.14, Minus, 1), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusRaw, 2), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusPlus, 3), "+3.140");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, 4), "+3.1400");
+     assert_eq!(to_string(f, -3.14, Minus, 8), "-3.14000000");
+     assert_eq!(to_string(f, -3.14, MinusRaw, 8), "-3.14000000");
+     assert_eq!(to_string(f, -3.14, MinusPlus, 8), "-3.14000000");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, 8), "-3.14000000");
+ 
+     assert_eq!(to_string(f, 7.5e-11, Minus, 0), "0.000000000075");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 3), "0.000000000075");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 12), "0.000000000075");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 13), "0.0000000000750");
+ 
+     assert_eq!(to_string(f, 1.9971e20, Minus, 0), "199710000000000000000");
+     assert_eq!(to_string(f, 1.9971e20, Minus, 1), "199710000000000000000.0");
+     assert_eq!(to_string(f, 1.9971e20, Minus, 8), "199710000000000000000.00000000");
+ 
+     assert_eq!(to_string(f, f32::MAX, Minus, 0), format!("34028235{:0>31}", ""));
+     assert_eq!(to_string(f, f32::MAX, Minus, 1), format!("34028235{:0>31}.0", ""));
+     assert_eq!(to_string(f, f32::MAX, Minus, 8), format!("34028235{:0>31}.00000000", ""));
+ 
+     let minf32 = ldexp_f32(1.0, -149);
+     assert_eq!(to_string(f, minf32, Minus, 0), format!("0.{:0>44}1", ""));
+     assert_eq!(to_string(f, minf32, Minus, 45), format!("0.{:0>44}1", ""));
+     assert_eq!(to_string(f, minf32, Minus, 46), format!("0.{:0>44}10", ""));
+ 
+     assert_eq!(to_string(f, f64::MAX, Minus, 0), format!("17976931348623157{:0>292}", ""));
+     assert_eq!(to_string(f, f64::MAX, Minus, 1), format!("17976931348623157{:0>292}.0", ""));
+     assert_eq!(to_string(f, f64::MAX, Minus, 8), format!("17976931348623157{:0>292}.00000000", ""));
+ 
+     let minf64 = ldexp_f64(1.0, -1074);
+     assert_eq!(to_string(f, minf64, Minus, 0), format!("0.{:0>323}5", ""));
+     assert_eq!(to_string(f, minf64, Minus, 324), format!("0.{:0>323}5", ""));
+     assert_eq!(to_string(f, minf64, Minus, 325), format!("0.{:0>323}50", ""));
+ 
+     if cfg!(miri) {
+         // Miri is too slow
+         return;
+     }
+ 
+     // very large output
+     assert_eq!(to_string(f, 1.1, Minus, 80000), format!("1.1{:0>79999}", ""));
+ }
+ 
+ pub fn to_shortest_exp_str_test<F>(mut f_: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     use core::num::flt2dec::Sign::*;
+ 
+     fn to_string<T, F>(f: &mut F, v: T, sign: Sign, exp_bounds: (i16, i16), upper: bool) -> String
+     where
+         T: DecodableFloat,
+         F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+     {
+         to_string_with_parts(|buf, parts| {
+             to_shortest_exp_str(|d, b| f(d, b), v, sign, exp_bounds, upper, buf, parts)
+         })
+     }
+ 
+     let f = &mut f_;
+ 
+     assert_eq!(to_string(f, 0.0, Minus, (-4, 16), false), "0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, (-4, 16), false), "0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, (-4, 16), false), "+0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, (-4, 16), false), "+0");
+     assert_eq!(to_string(f, -0.0, Minus, (-4, 16), false), "0");
+     assert_eq!(to_string(f, -0.0, MinusRaw, (-4, 16), false), "-0");
+     assert_eq!(to_string(f, -0.0, MinusPlus, (-4, 16), false), "+0");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, (-4, 16), false), "-0");
+     assert_eq!(to_string(f, 0.0, Minus, (0, 0), true), "0E0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, (0, 0), false), "0e0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, (-9, -5), true), "+0E0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, (5, 9), false), "+0e0");
+     assert_eq!(to_string(f, -0.0, Minus, (0, 0), true), "0E0");
+     assert_eq!(to_string(f, -0.0, MinusRaw, (0, 0), false), "-0e0");
+     assert_eq!(to_string(f, -0.0, MinusPlus, (-9, -5), true), "+0E0");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, (5, 9), false), "-0e0");
+ 
+     assert_eq!(to_string(f, 1.0 / 0.0, Minus, (-4, 16), false), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusRaw, (-4, 16), true), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlus, (-4, 16), false), "+inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlusRaw, (-4, 16), true), "+inf");
+     assert_eq!(to_string(f, 0.0 / 0.0, Minus, (0, 0), false), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusRaw, (0, 0), true), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlus, (-9, -5), false), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlusRaw, (5, 9), true), "NaN");
+     assert_eq!(to_string(f, -1.0 / 0.0, Minus, (0, 0), false), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusRaw, (0, 0), true), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlus, (-9, -5), false), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlusRaw, (5, 9), true), "-inf");
+ 
+     assert_eq!(to_string(f, 3.14, Minus, (-4, 16), false), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusRaw, (-4, 16), false), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusPlus, (-4, 16), false), "+3.14");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, (-4, 16), false), "+3.14");
+     assert_eq!(to_string(f, -3.14, Minus, (-4, 16), false), "-3.14");
+     assert_eq!(to_string(f, -3.14, MinusRaw, (-4, 16), false), "-3.14");
+     assert_eq!(to_string(f, -3.14, MinusPlus, (-4, 16), false), "-3.14");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, (-4, 16), false), "-3.14");
+     assert_eq!(to_string(f, 3.14, Minus, (0, 0), true), "3.14E0");
+     assert_eq!(to_string(f, 3.14, MinusRaw, (0, 0), false), "3.14e0");
+     assert_eq!(to_string(f, 3.14, MinusPlus, (-9, -5), true), "+3.14E0");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, (5, 9), false), "+3.14e0");
+     assert_eq!(to_string(f, -3.14, Minus, (0, 0), true), "-3.14E0");
+     assert_eq!(to_string(f, -3.14, MinusRaw, (0, 0), false), "-3.14e0");
+     assert_eq!(to_string(f, -3.14, MinusPlus, (-9, -5), true), "-3.14E0");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, (5, 9), false), "-3.14e0");
+ 
+     assert_eq!(to_string(f, 0.1, Minus, (-4, 16), false), "0.1");
+     assert_eq!(to_string(f, 0.1, MinusRaw, (-4, 16), false), "0.1");
+     assert_eq!(to_string(f, 0.1, MinusPlus, (-4, 16), false), "+0.1");
+     assert_eq!(to_string(f, 0.1, MinusPlusRaw, (-4, 16), false), "+0.1");
+     assert_eq!(to_string(f, -0.1, Minus, (-4, 16), false), "-0.1");
+     assert_eq!(to_string(f, -0.1, MinusRaw, (-4, 16), false), "-0.1");
+     assert_eq!(to_string(f, -0.1, MinusPlus, (-4, 16), false), "-0.1");
+     assert_eq!(to_string(f, -0.1, MinusPlusRaw, (-4, 16), false), "-0.1");
+     assert_eq!(to_string(f, 0.1, Minus, (0, 0), true), "1E-1");
+     assert_eq!(to_string(f, 0.1, MinusRaw, (0, 0), false), "1e-1");
+     assert_eq!(to_string(f, 0.1, MinusPlus, (-9, -5), true), "+1E-1");
+     assert_eq!(to_string(f, 0.1, MinusPlusRaw, (5, 9), false), "+1e-1");
+     assert_eq!(to_string(f, -0.1, Minus, (0, 0), true), "-1E-1");
+     assert_eq!(to_string(f, -0.1, MinusRaw, (0, 0), false), "-1e-1");
+     assert_eq!(to_string(f, -0.1, MinusPlus, (-9, -5), true), "-1E-1");
+     assert_eq!(to_string(f, -0.1, MinusPlusRaw, (5, 9), false), "-1e-1");
+ 
+     assert_eq!(to_string(f, 7.5e-11, Minus, (-4, 16), false), "7.5e-11");
+     assert_eq!(to_string(f, 7.5e-11, Minus, (-11, 10), false), "0.000000000075");
+     assert_eq!(to_string(f, 7.5e-11, Minus, (-10, 11), false), "7.5e-11");
+ 
+     assert_eq!(to_string(f, 1.9971e20, Minus, (-4, 16), false), "1.9971e20");
+     assert_eq!(to_string(f, 1.9971e20, Minus, (-20, 21), false), "199710000000000000000");
+     assert_eq!(to_string(f, 1.9971e20, Minus, (-21, 20), false), "1.9971e20");
+ 
+     // the true value of 1.0e23f64 is less than 10^23, but that shouldn't matter here
+     assert_eq!(to_string(f, 1.0e23, Minus, (22, 23), false), "1e23");
+     assert_eq!(to_string(f, 1.0e23, Minus, (23, 24), false), "100000000000000000000000");
+     assert_eq!(to_string(f, 1.0e23, Minus, (24, 25), false), "1e23");
+ 
+     assert_eq!(to_string(f, f32::MAX, Minus, (-4, 16), false), "3.4028235e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, (-39, 38), false), "3.4028235e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, (-38, 39), false), format!("34028235{:0>31}", ""));
+ 
+     let minf32 = ldexp_f32(1.0, -149);
+     assert_eq!(to_string(f, minf32, Minus, (-4, 16), false), "1e-45");
+     assert_eq!(to_string(f, minf32, Minus, (-44, 45), false), "1e-45");
+     assert_eq!(to_string(f, minf32, Minus, (-45, 44), false), format!("0.{:0>44}1", ""));
+ 
+     assert_eq!(to_string(f, f64::MAX, Minus, (-4, 16), false), "1.7976931348623157e308");
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, (-308, 309), false),
+         format!("17976931348623157{:0>292}", "")
+     );
+     assert_eq!(to_string(f, f64::MAX, Minus, (-309, 308), false), "1.7976931348623157e308");
+ 
+     let minf64 = ldexp_f64(1.0, -1074);
+     assert_eq!(to_string(f, minf64, Minus, (-4, 16), false), "5e-324");
+     assert_eq!(to_string(f, minf64, Minus, (-324, 323), false), format!("0.{:0>323}5", ""));
+     assert_eq!(to_string(f, minf64, Minus, (-323, 324), false), "5e-324");
+ 
+     assert_eq!(to_string(f, 1.1, Minus, (i16::MIN, i16::MAX), false), "1.1");
+ }
+ 
+ pub fn to_exact_exp_str_test<F>(mut f_: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     use core::num::flt2dec::Sign::*;
+ 
+     fn to_string<T, F>(f: &mut F, v: T, sign: Sign, ndigits: usize, upper: bool) -> String
+     where
+         T: DecodableFloat,
+         F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+     {
+         to_string_with_parts(|buf, parts| {
+             to_exact_exp_str(|d, b, l| f(d, b, l), v, sign, ndigits, upper, buf, parts)
+         })
+     }
+ 
+     let f = &mut f_;
+ 
+     assert_eq!(to_string(f, 0.0, Minus, 1, true), "0E0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, 1, false), "0e0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, 1, true), "+0E0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, 1, false), "+0e0");
+     assert_eq!(to_string(f, -0.0, Minus, 1, true), "0E0");
+     assert_eq!(to_string(f, -0.0, MinusRaw, 1, false), "-0e0");
+     assert_eq!(to_string(f, -0.0, MinusPlus, 1, true), "+0E0");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, 1, false), "-0e0");
+     assert_eq!(to_string(f, 0.0, Minus, 2, true), "0.0E0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, 2, false), "0.0e0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, 2, true), "+0.0E0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, 2, false), "+0.0e0");
+     assert_eq!(to_string(f, -0.0, Minus, 8, true), "0.0000000E0");
+     assert_eq!(to_string(f, -0.0, MinusRaw, 8, false), "-0.0000000e0");
+     assert_eq!(to_string(f, -0.0, MinusPlus, 8, true), "+0.0000000E0");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, 8, false), "-0.0000000e0");
+ 
+     assert_eq!(to_string(f, 1.0 / 0.0, Minus, 1, false), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusRaw, 1, true), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlus, 1, false), "+inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlusRaw, 1, true), "+inf");
+     assert_eq!(to_string(f, 0.0 / 0.0, Minus, 8, false), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusRaw, 8, true), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlus, 8, false), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlusRaw, 8, true), "NaN");
+     assert_eq!(to_string(f, -1.0 / 0.0, Minus, 64, false), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusRaw, 64, true), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlus, 64, false), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlusRaw, 64, true), "-inf");
+ 
+     assert_eq!(to_string(f, 3.14, Minus, 1, true), "3E0");
+     assert_eq!(to_string(f, 3.14, MinusRaw, 1, false), "3e0");
+     assert_eq!(to_string(f, 3.14, MinusPlus, 1, true), "+3E0");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, 1, false), "+3e0");
+     assert_eq!(to_string(f, -3.14, Minus, 2, true), "-3.1E0");
+     assert_eq!(to_string(f, -3.14, MinusRaw, 2, false), "-3.1e0");
+     assert_eq!(to_string(f, -3.14, MinusPlus, 2, true), "-3.1E0");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, 2, false), "-3.1e0");
+     assert_eq!(to_string(f, 3.14, Minus, 3, true), "3.14E0");
+     assert_eq!(to_string(f, 3.14, MinusRaw, 3, false), "3.14e0");
+     assert_eq!(to_string(f, 3.14, MinusPlus, 3, true), "+3.14E0");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, 3, false), "+3.14e0");
+     assert_eq!(to_string(f, -3.14, Minus, 4, true), "-3.140E0");
+     assert_eq!(to_string(f, -3.14, MinusRaw, 4, false), "-3.140e0");
+     assert_eq!(to_string(f, -3.14, MinusPlus, 4, true), "-3.140E0");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, 4, false), "-3.140e0");
+ 
+     assert_eq!(to_string(f, 0.195, Minus, 1, false), "2e-1");
+     assert_eq!(to_string(f, 0.195, MinusRaw, 1, true), "2E-1");
+     assert_eq!(to_string(f, 0.195, MinusPlus, 1, false), "+2e-1");
+     assert_eq!(to_string(f, 0.195, MinusPlusRaw, 1, true), "+2E-1");
+     assert_eq!(to_string(f, -0.195, Minus, 2, false), "-2.0e-1");
+     assert_eq!(to_string(f, -0.195, MinusRaw, 2, true), "-2.0E-1");
+     assert_eq!(to_string(f, -0.195, MinusPlus, 2, false), "-2.0e-1");
+     assert_eq!(to_string(f, -0.195, MinusPlusRaw, 2, true), "-2.0E-1");
+     assert_eq!(to_string(f, 0.195, Minus, 3, false), "1.95e-1");
+     assert_eq!(to_string(f, 0.195, MinusRaw, 3, true), "1.95E-1");
+     assert_eq!(to_string(f, 0.195, MinusPlus, 3, false), "+1.95e-1");
+     assert_eq!(to_string(f, 0.195, MinusPlusRaw, 3, true), "+1.95E-1");
+     assert_eq!(to_string(f, -0.195, Minus, 4, false), "-1.950e-1");
+     assert_eq!(to_string(f, -0.195, MinusRaw, 4, true), "-1.950E-1");
+     assert_eq!(to_string(f, -0.195, MinusPlus, 4, false), "-1.950e-1");
+     assert_eq!(to_string(f, -0.195, MinusPlusRaw, 4, true), "-1.950E-1");
+ 
+     assert_eq!(to_string(f, 9.5, Minus, 1, false), "1e1");
+     assert_eq!(to_string(f, 9.5, Minus, 2, false), "9.5e0");
+     assert_eq!(to_string(f, 9.5, Minus, 3, false), "9.50e0");
+     assert_eq!(to_string(f, 9.5, Minus, 30, false), "9.50000000000000000000000000000e0");
+ 
+     assert_eq!(to_string(f, 1.0e25, Minus, 1, false), "1e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 2, false), "1.0e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 15, false), "1.00000000000000e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 16, false), "1.000000000000000e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 17, false), "1.0000000000000001e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 18, false), "1.00000000000000009e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 19, false), "1.000000000000000091e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 20, false), "1.0000000000000000906e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 21, false), "1.00000000000000009060e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 22, false), "1.000000000000000090597e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 23, false), "1.0000000000000000905970e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 24, false), "1.00000000000000009059697e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 25, false), "1.000000000000000090596966e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 26, false), "1.0000000000000000905969664e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 27, false), "1.00000000000000009059696640e25");
+     assert_eq!(to_string(f, 1.0e25, Minus, 30, false), "1.00000000000000009059696640000e25");
+ 
+     assert_eq!(to_string(f, 1.0e-6, Minus, 1, false), "1e-6");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 2, false), "1.0e-6");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 16, false), "1.000000000000000e-6");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 17, false), "9.9999999999999995e-7");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 18, false), "9.99999999999999955e-7");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 19, false), "9.999999999999999547e-7");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 20, false), "9.9999999999999995475e-7");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 30, false), "9.99999999999999954748111825886e-7");
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 40, false),
+         "9.999999999999999547481118258862586856139e-7"
+     );
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 50, false),
+         "9.9999999999999995474811182588625868561393872369081e-7"
+     );
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 60, false),
+         "9.99999999999999954748111825886258685613938723690807819366455e-7"
+     );
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 70, false),
+         "9.999999999999999547481118258862586856139387236908078193664550781250000e-7"
+     );
+ 
+     assert_eq!(to_string(f, f32::MAX, Minus, 1, false), "3e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, 2, false), "3.4e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, 4, false), "3.403e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, 8, false), "3.4028235e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, 16, false), "3.402823466385289e38");
+     assert_eq!(to_string(f, f32::MAX, Minus, 32, false), "3.4028234663852885981170418348452e38");
+     assert_eq!(
+         to_string(f, f32::MAX, Minus, 64, false),
+         "3.402823466385288598117041834845169254400000000000000000000000000e38"
+     );
+ 
+     let minf32 = ldexp_f32(1.0, -149);
+     assert_eq!(to_string(f, minf32, Minus, 1, false), "1e-45");
+     assert_eq!(to_string(f, minf32, Minus, 2, false), "1.4e-45");
+     assert_eq!(to_string(f, minf32, Minus, 4, false), "1.401e-45");
+     assert_eq!(to_string(f, minf32, Minus, 8, false), "1.4012985e-45");
+     assert_eq!(to_string(f, minf32, Minus, 16, false), "1.401298464324817e-45");
+     assert_eq!(to_string(f, minf32, Minus, 32, false), "1.4012984643248170709237295832899e-45");
+     assert_eq!(
+         to_string(f, minf32, Minus, 64, false),
+         "1.401298464324817070923729583289916131280261941876515771757068284e-45"
+     );
+     assert_eq!(
+         to_string(f, minf32, Minus, 128, false),
+         "1.401298464324817070923729583289916131280261941876515771757068283\
+                  8897910826858606014866381883621215820312500000000000000000000000e-45"
+     );
+ 
+     if cfg!(miri) {
+         // Miri is too slow
+         return;
+     }
+ 
+     assert_eq!(to_string(f, f64::MAX, Minus, 1, false), "2e308");
+     assert_eq!(to_string(f, f64::MAX, Minus, 2, false), "1.8e308");
+     assert_eq!(to_string(f, f64::MAX, Minus, 4, false), "1.798e308");
+     assert_eq!(to_string(f, f64::MAX, Minus, 8, false), "1.7976931e308");
+     assert_eq!(to_string(f, f64::MAX, Minus, 16, false), "1.797693134862316e308");
+     assert_eq!(to_string(f, f64::MAX, Minus, 32, false), "1.7976931348623157081452742373170e308");
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, 64, false),
+         "1.797693134862315708145274237317043567980705675258449965989174768e308"
+     );
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, 128, false),
+         "1.797693134862315708145274237317043567980705675258449965989174768\
+                  0315726078002853876058955863276687817154045895351438246423432133e308"
+     );
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, 256, false),
+         "1.797693134862315708145274237317043567980705675258449965989174768\
+                  0315726078002853876058955863276687817154045895351438246423432132\
+                  6889464182768467546703537516986049910576551282076245490090389328\
+                  9440758685084551339423045832369032229481658085593321233482747978e308"
+     );
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, 512, false),
+         "1.797693134862315708145274237317043567980705675258449965989174768\
+                  0315726078002853876058955863276687817154045895351438246423432132\
+                  6889464182768467546703537516986049910576551282076245490090389328\
+                  9440758685084551339423045832369032229481658085593321233482747978\
+                  2620414472316873817718091929988125040402618412485836800000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000e308"
+     );
+ 
+     // okay, this is becoming tough. fortunately for us, this is almost the worst case.
+     let minf64 = ldexp_f64(1.0, -1074);
+     assert_eq!(to_string(f, minf64, Minus, 1, false), "5e-324");
+     assert_eq!(to_string(f, minf64, Minus, 2, false), "4.9e-324");
+     assert_eq!(to_string(f, minf64, Minus, 4, false), "4.941e-324");
+     assert_eq!(to_string(f, minf64, Minus, 8, false), "4.9406565e-324");
+     assert_eq!(to_string(f, minf64, Minus, 16, false), "4.940656458412465e-324");
+     assert_eq!(to_string(f, minf64, Minus, 32, false), "4.9406564584124654417656879286822e-324");
+     assert_eq!(
+         to_string(f, minf64, Minus, 64, false),
+         "4.940656458412465441765687928682213723650598026143247644255856825e-324"
+     );
+     assert_eq!(
+         to_string(f, minf64, Minus, 128, false),
+         "4.940656458412465441765687928682213723650598026143247644255856825\
+                  0067550727020875186529983636163599237979656469544571773092665671e-324"
+     );
+     assert_eq!(
+         to_string(f, minf64, Minus, 256, false),
+         "4.940656458412465441765687928682213723650598026143247644255856825\
+                  0067550727020875186529983636163599237979656469544571773092665671\
+                  0355939796398774796010781878126300713190311404527845817167848982\
+                  1036887186360569987307230500063874091535649843873124733972731696e-324"
+     );
+     assert_eq!(
+         to_string(f, minf64, Minus, 512, false),
+         "4.940656458412465441765687928682213723650598026143247644255856825\
+                  0067550727020875186529983636163599237979656469544571773092665671\
+                  0355939796398774796010781878126300713190311404527845817167848982\
+                  1036887186360569987307230500063874091535649843873124733972731696\
+                  1514003171538539807412623856559117102665855668676818703956031062\
+                  4931945271591492455329305456544401127480129709999541931989409080\
+                  4165633245247571478690147267801593552386115501348035264934720193\
+                  7902681071074917033322268447533357208324319360923828934583680601e-324"
+     );
+     assert_eq!(
+         to_string(f, minf64, Minus, 1024, false),
+         "4.940656458412465441765687928682213723650598026143247644255856825\
+                  0067550727020875186529983636163599237979656469544571773092665671\
+                  0355939796398774796010781878126300713190311404527845817167848982\
+                  1036887186360569987307230500063874091535649843873124733972731696\
+                  1514003171538539807412623856559117102665855668676818703956031062\
+                  4931945271591492455329305456544401127480129709999541931989409080\
+                  4165633245247571478690147267801593552386115501348035264934720193\
+                  7902681071074917033322268447533357208324319360923828934583680601\
+                  0601150616980975307834227731832924790498252473077637592724787465\
+                  6084778203734469699533647017972677717585125660551199131504891101\
+                  4510378627381672509558373897335989936648099411642057026370902792\
+                  4276754456522908753868250641971826553344726562500000000000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000\
+                  0000000000000000000000000000000000000000000000000000000000000000e-324"
+     );
+ 
+     // very large output
+     assert_eq!(to_string(f, 0.0, Minus, 80000, false), format!("0.{:0>79999}e0", ""));
+     assert_eq!(to_string(f, 1.0e1, Minus, 80000, false), format!("1.{:0>79999}e1", ""));
+     assert_eq!(to_string(f, 1.0e0, Minus, 80000, false), format!("1.{:0>79999}e0", ""));
+     assert_eq!(
+         to_string(f, 1.0e-1, Minus, 80000, false),
+         format!(
+             "1.000000000000000055511151231257827021181583404541015625{:0>79945}\
+                         e-1",
+             ""
+         )
+     );
+     assert_eq!(
+         to_string(f, 1.0e-20, Minus, 80000, false),
+         format!(
+             "9.999999999999999451532714542095716517295037027873924471077157760\
+                          66783064379706047475337982177734375{:0>79901}e-21",
+             ""
+         )
+     );
+ }
+ 
+ pub fn to_exact_fixed_str_test<F>(mut f_: F)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+ {
+     use core::num::flt2dec::Sign::*;
+ 
+     fn to_string<T, F>(f: &mut F, v: T, sign: Sign, frac_digits: usize) -> String
+     where
+         T: DecodableFloat,
+         F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>], i16) -> (&'a [u8], i16),
+     {
+         to_string_with_parts(|buf, parts| {
+             to_exact_fixed_str(|d, b, l| f(d, b, l), v, sign, frac_digits, buf, parts)
+         })
+     }
+ 
+     let f = &mut f_;
+ 
+     assert_eq!(to_string(f, 0.0, Minus, 0), "0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, 0), "0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, 0), "+0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, 0), "+0");
+     assert_eq!(to_string(f, -0.0, Minus, 0), "0");
+     assert_eq!(to_string(f, -0.0, MinusRaw, 0), "-0");
+     assert_eq!(to_string(f, -0.0, MinusPlus, 0), "+0");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, 0), "-0");
+     assert_eq!(to_string(f, 0.0, Minus, 1), "0.0");
+     assert_eq!(to_string(f, 0.0, MinusRaw, 1), "0.0");
+     assert_eq!(to_string(f, 0.0, MinusPlus, 1), "+0.0");
+     assert_eq!(to_string(f, 0.0, MinusPlusRaw, 1), "+0.0");
+     assert_eq!(to_string(f, -0.0, Minus, 8), "0.00000000");
+     assert_eq!(to_string(f, -0.0, MinusRaw, 8), "-0.00000000");
+     assert_eq!(to_string(f, -0.0, MinusPlus, 8), "+0.00000000");
+     assert_eq!(to_string(f, -0.0, MinusPlusRaw, 8), "-0.00000000");
+ 
+     assert_eq!(to_string(f, 1.0 / 0.0, Minus, 0), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusRaw, 1), "inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlus, 8), "+inf");
+     assert_eq!(to_string(f, 1.0 / 0.0, MinusPlusRaw, 64), "+inf");
+     assert_eq!(to_string(f, 0.0 / 0.0, Minus, 0), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusRaw, 1), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlus, 8), "NaN");
+     assert_eq!(to_string(f, 0.0 / 0.0, MinusPlusRaw, 64), "NaN");
+     assert_eq!(to_string(f, -1.0 / 0.0, Minus, 0), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusRaw, 1), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlus, 8), "-inf");
+     assert_eq!(to_string(f, -1.0 / 0.0, MinusPlusRaw, 64), "-inf");
+ 
+     assert_eq!(to_string(f, 3.14, Minus, 0), "3");
+     assert_eq!(to_string(f, 3.14, MinusRaw, 0), "3");
+     assert_eq!(to_string(f, 3.14, MinusPlus, 0), "+3");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, 0), "+3");
+     assert_eq!(to_string(f, -3.14, Minus, 0), "-3");
+     assert_eq!(to_string(f, -3.14, MinusRaw, 0), "-3");
+     assert_eq!(to_string(f, -3.14, MinusPlus, 0), "-3");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, 0), "-3");
+     assert_eq!(to_string(f, 3.14, Minus, 1), "3.1");
+     assert_eq!(to_string(f, 3.14, MinusRaw, 2), "3.14");
+     assert_eq!(to_string(f, 3.14, MinusPlus, 3), "+3.140");
+     assert_eq!(to_string(f, 3.14, MinusPlusRaw, 4), "+3.1400");
+     assert_eq!(to_string(f, -3.14, Minus, 8), "-3.14000000");
+     assert_eq!(to_string(f, -3.14, MinusRaw, 8), "-3.14000000");
+     assert_eq!(to_string(f, -3.14, MinusPlus, 8), "-3.14000000");
+     assert_eq!(to_string(f, -3.14, MinusPlusRaw, 8), "-3.14000000");
+ 
+     assert_eq!(to_string(f, 0.195, Minus, 0), "0");
+     assert_eq!(to_string(f, 0.195, MinusRaw, 0), "0");
+     assert_eq!(to_string(f, 0.195, MinusPlus, 0), "+0");
+     assert_eq!(to_string(f, 0.195, MinusPlusRaw, 0), "+0");
+     assert_eq!(to_string(f, -0.195, Minus, 0), "-0");
+     assert_eq!(to_string(f, -0.195, MinusRaw, 0), "-0");
+     assert_eq!(to_string(f, -0.195, MinusPlus, 0), "-0");
+     assert_eq!(to_string(f, -0.195, MinusPlusRaw, 0), "-0");
+     assert_eq!(to_string(f, 0.195, Minus, 1), "0.2");
+     assert_eq!(to_string(f, 0.195, MinusRaw, 2), "0.20");
+     assert_eq!(to_string(f, 0.195, MinusPlus, 3), "+0.195");
+     assert_eq!(to_string(f, 0.195, MinusPlusRaw, 4), "+0.1950");
+     assert_eq!(to_string(f, -0.195, Minus, 5), "-0.19500");
+     assert_eq!(to_string(f, -0.195, MinusRaw, 6), "-0.195000");
+     assert_eq!(to_string(f, -0.195, MinusPlus, 7), "-0.1950000");
+     assert_eq!(to_string(f, -0.195, MinusPlusRaw, 8), "-0.19500000");
+ 
+     assert_eq!(to_string(f, 999.5, Minus, 0), "1000");
+     assert_eq!(to_string(f, 999.5, Minus, 1), "999.5");
+     assert_eq!(to_string(f, 999.5, Minus, 2), "999.50");
+     assert_eq!(to_string(f, 999.5, Minus, 3), "999.500");
+     assert_eq!(to_string(f, 999.5, Minus, 30), "999.500000000000000000000000000000");
+ 
+     assert_eq!(to_string(f, 0.5, Minus, 0), "1");
+     assert_eq!(to_string(f, 0.5, Minus, 1), "0.5");
+     assert_eq!(to_string(f, 0.5, Minus, 2), "0.50");
+     assert_eq!(to_string(f, 0.5, Minus, 3), "0.500");
+ 
+     assert_eq!(to_string(f, 0.95, Minus, 0), "1");
+     assert_eq!(to_string(f, 0.95, Minus, 1), "0.9"); // because it really is less than 0.95
+     assert_eq!(to_string(f, 0.95, Minus, 2), "0.95");
+     assert_eq!(to_string(f, 0.95, Minus, 3), "0.950");
+     assert_eq!(to_string(f, 0.95, Minus, 10), "0.9500000000");
+     assert_eq!(to_string(f, 0.95, Minus, 30), "0.949999999999999955591079014994");
+ 
+     assert_eq!(to_string(f, 0.095, Minus, 0), "0");
+     assert_eq!(to_string(f, 0.095, Minus, 1), "0.1");
+     assert_eq!(to_string(f, 0.095, Minus, 2), "0.10");
+     assert_eq!(to_string(f, 0.095, Minus, 3), "0.095");
+     assert_eq!(to_string(f, 0.095, Minus, 4), "0.0950");
+     assert_eq!(to_string(f, 0.095, Minus, 10), "0.0950000000");
+     assert_eq!(to_string(f, 0.095, Minus, 30), "0.095000000000000001110223024625");
+ 
+     assert_eq!(to_string(f, 0.0095, Minus, 0), "0");
+     assert_eq!(to_string(f, 0.0095, Minus, 1), "0.0");
+     assert_eq!(to_string(f, 0.0095, Minus, 2), "0.01");
+     assert_eq!(to_string(f, 0.0095, Minus, 3), "0.009"); // really is less than 0.0095
+     assert_eq!(to_string(f, 0.0095, Minus, 4), "0.0095");
+     assert_eq!(to_string(f, 0.0095, Minus, 5), "0.00950");
+     assert_eq!(to_string(f, 0.0095, Minus, 10), "0.0095000000");
+     assert_eq!(to_string(f, 0.0095, Minus, 30), "0.009499999999999999764077607267");
+ 
+     assert_eq!(to_string(f, 7.5e-11, Minus, 0), "0");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 3), "0.000");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 10), "0.0000000001");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 11), "0.00000000007"); // ditto
+     assert_eq!(to_string(f, 7.5e-11, Minus, 12), "0.000000000075");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 13), "0.0000000000750");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 20), "0.00000000007500000000");
+     assert_eq!(to_string(f, 7.5e-11, Minus, 30), "0.000000000074999999999999999501");
+ 
+     assert_eq!(to_string(f, 1.0e25, Minus, 0), "10000000000000000905969664");
+     assert_eq!(to_string(f, 1.0e25, Minus, 1), "10000000000000000905969664.0");
+     assert_eq!(to_string(f, 1.0e25, Minus, 3), "10000000000000000905969664.000");
+ 
+     assert_eq!(to_string(f, 1.0e-6, Minus, 0), "0");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 3), "0.000");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 6), "0.000001");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 9), "0.000001000");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 12), "0.000001000000");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 22), "0.0000010000000000000000");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 23), "0.00000099999999999999995");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 24), "0.000000999999999999999955");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 25), "0.0000009999999999999999547");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 35), "0.00000099999999999999995474811182589");
+     assert_eq!(to_string(f, 1.0e-6, Minus, 45), "0.000000999999999999999954748111825886258685614");
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 55),
+         "0.0000009999999999999999547481118258862586856139387236908"
+     );
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 65),
+         "0.00000099999999999999995474811182588625868561393872369080781936646"
+     );
+     assert_eq!(
+         to_string(f, 1.0e-6, Minus, 75),
+         "0.000000999999999999999954748111825886258685613938723690807819366455078125000"
+     );
+ 
+     assert_eq!(to_string(f, f32::MAX, Minus, 0), "340282346638528859811704183484516925440");
+     assert_eq!(to_string(f, f32::MAX, Minus, 1), "340282346638528859811704183484516925440.0");
+     assert_eq!(to_string(f, f32::MAX, Minus, 2), "340282346638528859811704183484516925440.00");
+ 
+     if cfg!(miri) {
+         // Miri is too slow
+         return;
+     }
+ 
+     let minf32 = ldexp_f32(1.0, -149);
+     assert_eq!(to_string(f, minf32, Minus, 0), "0");
+     assert_eq!(to_string(f, minf32, Minus, 1), "0.0");
+     assert_eq!(to_string(f, minf32, Minus, 2), "0.00");
+     assert_eq!(to_string(f, minf32, Minus, 4), "0.0000");
+     assert_eq!(to_string(f, minf32, Minus, 8), "0.00000000");
+     assert_eq!(to_string(f, minf32, Minus, 16), "0.0000000000000000");
+     assert_eq!(to_string(f, minf32, Minus, 32), "0.00000000000000000000000000000000");
+     assert_eq!(
+         to_string(f, minf32, Minus, 64),
+         "0.0000000000000000000000000000000000000000000014012984643248170709"
+     );
+     assert_eq!(
+         to_string(f, minf32, Minus, 128),
+         "0.0000000000000000000000000000000000000000000014012984643248170709\
+                   2372958328991613128026194187651577175706828388979108268586060149"
+     );
+     assert_eq!(
+         to_string(f, minf32, Minus, 256),
+         "0.0000000000000000000000000000000000000000000014012984643248170709\
+                   2372958328991613128026194187651577175706828388979108268586060148\
+                   6638188362121582031250000000000000000000000000000000000000000000\
+                   0000000000000000000000000000000000000000000000000000000000000000"
+     );
+ 
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, 0),
+         "1797693134862315708145274237317043567980705675258449965989174768\
+                 0315726078002853876058955863276687817154045895351438246423432132\
+                 6889464182768467546703537516986049910576551282076245490090389328\
+                 9440758685084551339423045832369032229481658085593321233482747978\
+                 26204144723168738177180919299881250404026184124858368"
+     );
+     assert_eq!(
+         to_string(f, f64::MAX, Minus, 10),
+         "1797693134862315708145274237317043567980705675258449965989174768\
+                 0315726078002853876058955863276687817154045895351438246423432132\
+                 6889464182768467546703537516986049910576551282076245490090389328\
+                 9440758685084551339423045832369032229481658085593321233482747978\
+                 26204144723168738177180919299881250404026184124858368.0000000000"
+     );
+ 
+     let minf64 = ldexp_f64(1.0, -1074);
+     assert_eq!(to_string(f, minf64, Minus, 0), "0");
+     assert_eq!(to_string(f, minf64, Minus, 1), "0.0");
+     assert_eq!(to_string(f, minf64, Minus, 10), "0.0000000000");
+     assert_eq!(
+         to_string(f, minf64, Minus, 100),
+         "0.0000000000000000000000000000000000000000000000000000000000000000\
+                   000000000000000000000000000000000000"
+     );
+     assert_eq!(
+         to_string(f, minf64, Minus, 1000),
+         "0.0000000000000000000000000000000000000000000000000000000000000000\
+                   0000000000000000000000000000000000000000000000000000000000000000\
+                   0000000000000000000000000000000000000000000000000000000000000000\
+                   0000000000000000000000000000000000000000000000000000000000000000\
+                   0000000000000000000000000000000000000000000000000000000000000000\
+                   0004940656458412465441765687928682213723650598026143247644255856\
+                   8250067550727020875186529983636163599237979656469544571773092665\
+                   6710355939796398774796010781878126300713190311404527845817167848\
+                   9821036887186360569987307230500063874091535649843873124733972731\
+                   6961514003171538539807412623856559117102665855668676818703956031\
+                   0624931945271591492455329305456544401127480129709999541931989409\
+                   0804165633245247571478690147267801593552386115501348035264934720\
+                   1937902681071074917033322268447533357208324319360923828934583680\
+                   6010601150616980975307834227731832924790498252473077637592724787\
+                   4656084778203734469699533647017972677717585125660551199131504891\
+                   1014510378627381672509558373897335989937"
+     );
+ 
+     // very large output
+     assert_eq!(to_string(f, 0.0, Minus, 80000), format!("0.{:0>80000}", ""));
+     assert_eq!(to_string(f, 1.0e1, Minus, 80000), format!("10.{:0>80000}", ""));
+     assert_eq!(to_string(f, 1.0e0, Minus, 80000), format!("1.{:0>80000}", ""));
+     assert_eq!(
+         to_string(f, 1.0e-1, Minus, 80000),
+         format!("0.1000000000000000055511151231257827021181583404541015625{:0>79945}", "")
+     );
+     assert_eq!(
+         to_string(f, 1.0e-20, Minus, 80000),
+         format!(
+             "0.0000000000000000000099999999999999994515327145420957165172950370\
+                           2787392447107715776066783064379706047475337982177734375{:0>79881}",
+             ""
+         )
+     );
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/random.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/random.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/random.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/random.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,202 ----
+ #![cfg(not(target_arch = "wasm32"))]
+ 
+ use std::mem::MaybeUninit;
+ use std::str;
+ 
+ use core::num::flt2dec::strategy::grisu::format_exact_opt;
+ use core::num::flt2dec::strategy::grisu::format_shortest_opt;
+ use core::num::flt2dec::MAX_SIG_DIGITS;
+ use core::num::flt2dec::{decode, DecodableFloat, Decoded, FullDecoded};
+ 
+ use rand::distributions::{Distribution, Uniform};
+ use rand::rngs::StdRng;
+ use rand::SeedableRng;
+ 
+ pub fn decode_finite<T: DecodableFloat>(v: T) -> Decoded {
+     match decode(v).1 {
+         FullDecoded::Finite(decoded) => decoded,
+         full_decoded => panic!("expected finite, got {:?} instead", full_decoded),
+     }
+ }
+ 
+ fn iterate<F, G, V>(func: &str, k: usize, n: usize, mut f: F, mut g: G, mut v: V) -> (usize, usize)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> Option<(&'a [u8], i16)>,
+     G: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+     V: FnMut(usize) -> Decoded,
+ {
+     assert!(k <= 1024);
+ 
+     let mut npassed = 0; // f(x) = Some(g(x))
+     let mut nignored = 0; // f(x) = None
+ 
+     for i in 0..n {
+         if (i & 0xfffff) == 0 {
+             println!(
+                 "in progress, {:x}/{:x} (ignored={} passed={} failed={})",
+                 i,
+                 n,
+                 nignored,
+                 npassed,
+                 i - nignored - npassed
+             );
+         }
+ 
+         let decoded = v(i);
+         let mut buf1 = [MaybeUninit::new(0); 1024];
+         if let Some((buf1, e1)) = f(&decoded, &mut buf1[..k]) {
+             let mut buf2 = [MaybeUninit::new(0); 1024];
+             let (buf2, e2) = g(&decoded, &mut buf2[..k]);
+             if e1 == e2 && buf1 == buf2 {
+                 npassed += 1;
+             } else {
+                 println!(
+                     "equivalence test failed, {:x}/{:x}: {:?} f(i)={}e{} g(i)={}e{}",
+                     i,
+                     n,
+                     decoded,
+                     str::from_utf8(buf1).unwrap(),
+                     e1,
+                     str::from_utf8(buf2).unwrap(),
+                     e2
+                 );
+             }
+         } else {
+             nignored += 1;
+         }
+     }
+     println!(
+         "{}({}): done, ignored={} passed={} failed={}",
+         func,
+         k,
+         nignored,
+         npassed,
+         n - nignored - npassed
+     );
+     assert!(
+         nignored + npassed == n,
+         "{}({}): {} out of {} values returns an incorrect value!",
+         func,
+         k,
+         n - nignored - npassed,
+         n
+     );
+     (npassed, nignored)
+ }
+ 
+ pub fn f32_random_equivalence_test<F, G>(f: F, g: G, k: usize, n: usize)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> Option<(&'a [u8], i16)>,
+     G: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     if cfg!(target_os = "emscripten") {
+         return; // using rng pulls in i128 support, which doesn't work
+     }
+     let mut rng = StdRng::from_entropy();
+     let f32_range = Uniform::new(0x0000_0001u32, 0x7f80_0000);
+     iterate("f32_random_equivalence_test", k, n, f, g, |_| {
+         let x = f32::from_bits(f32_range.sample(&mut rng));
+         decode_finite(x)
+     });
+ }
+ 
+ pub fn f64_random_equivalence_test<F, G>(f: F, g: G, k: usize, n: usize)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> Option<(&'a [u8], i16)>,
+     G: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     if cfg!(target_os = "emscripten") {
+         return; // using rng pulls in i128 support, which doesn't work
+     }
+     let mut rng = StdRng::from_entropy();
+     let f64_range = Uniform::new(0x0000_0000_0000_0001u64, 0x7ff0_0000_0000_0000);
+     iterate("f64_random_equivalence_test", k, n, f, g, |_| {
+         let x = f64::from_bits(f64_range.sample(&mut rng));
+         decode_finite(x)
+     });
+ }
+ 
+ pub fn f32_exhaustive_equivalence_test<F, G>(f: F, g: G, k: usize)
+ where
+     F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> Option<(&'a [u8], i16)>,
+     G: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit<u8>]) -> (&'a [u8], i16),
+ {
+     // we have only 2^23 * (2^8 - 1) - 1 = 2,139,095,039 positive finite f32 values,
+     // so why not simply testing all of them?
+     //
+     // this is of course very stressful (and thus should be behind an `#[ignore]` attribute),
+     // but with `-C opt-level=3 -C lto` this only takes about an hour or so.
+ 
+     // iterate from 0x0000_0001 to 0x7f7f_ffff, i.e., all finite ranges
+     let (npassed, nignored) =
+         iterate("f32_exhaustive_equivalence_test", k, 0x7f7f_ffff, f, g, |i: usize| {
+             let x = f32::from_bits(i as u32 + 1);
+             decode_finite(x)
+         });
+     assert_eq!((npassed, nignored), (2121451881, 17643158));
+ }
+ 
+ #[test]
+ fn shortest_random_equivalence_test() {
+     use core::num::flt2dec::strategy::dragon::format_shortest as fallback;
+     // Miri is too slow
+     let n = if cfg!(miri) { 10 } else { 10_000 };
+ 
+     f64_random_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS, n);
+     f32_random_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS, n);
+ }
+ 
+ #[test]
+ #[ignore] // it is too expensive
+ fn shortest_f32_exhaustive_equivalence_test() {
+     // it is hard to directly test the optimality of the output, but we can at least test if
+     // two different algorithms agree to each other.
+     //
+     // this reports the progress and the number of f32 values returned `None`.
+     // with `--nocapture` (and plenty of time and appropriate rustc flags), this should print:
+     // `done, ignored=17643158 passed=2121451881 failed=0`.
+ 
+     use core::num::flt2dec::strategy::dragon::format_shortest as fallback;
+     f32_exhaustive_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS);
+ }
+ 
+ #[test]
+ #[ignore] // it is too expensive
+ fn shortest_f64_hard_random_equivalence_test() {
+     // this again probably has to use appropriate rustc flags.
+ 
+     use core::num::flt2dec::strategy::dragon::format_shortest as fallback;
+     f64_random_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS, 100_000_000);
+ }
+ 
+ #[test]
+ fn exact_f32_random_equivalence_test() {
+     use core::num::flt2dec::strategy::dragon::format_exact as fallback;
+     // Miri is too slow
+     let n = if cfg!(miri) { 3 } else { 1_000 };
+ 
+     for k in 1..21 {
+         f32_random_equivalence_test(
+             |d, buf| format_exact_opt(d, buf, i16::MIN),
+             |d, buf| fallback(d, buf, i16::MIN),
+             k,
+             n,
+         );
+     }
+ }
+ 
+ #[test]
+ fn exact_f64_random_equivalence_test() {
+     use core::num::flt2dec::strategy::dragon::format_exact as fallback;
+     // Miri is too slow
+     let n = if cfg!(miri) { 2 } else { 1_000 };
+ 
+     for k in 1..21 {
+         f64_random_equivalence_test(
+             |d, buf| format_exact_opt(d, buf, i16::MIN),
+             |d, buf| fallback(d, buf, i16::MIN),
+             k,
+             n,
+         );
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/dragon.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/dragon.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/dragon.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/dragon.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,64 ----
+ use super::super::*;
+ use core::num::bignum::Big32x40 as Big;
+ use core::num::flt2dec::strategy::dragon::*;
+ 
+ #[test]
+ fn test_mul_pow10() {
+     let mut prevpow10 = Big::from_small(1);
+     for i in 1..340 {
+         let mut curpow10 = Big::from_small(1);
+         mul_pow10(&mut curpow10, i);
+         assert_eq!(curpow10, *prevpow10.clone().mul_small(10));
+         prevpow10 = curpow10;
+     }
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn shortest_sanity_test() {
+     f64_shortest_sanity_test(format_shortest);
+     f32_shortest_sanity_test(format_shortest);
+     more_shortest_sanity_test(format_shortest);
+ }
+ 
+ #[test]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn exact_sanity_test() {
+     // This test ends up running what I can only assume is some corner-ish case
+     // of the `exp2` library function, defined in whatever C runtime we're
+     // using. In VS 2013 this function apparently had a bug as this test fails
+     // when linked, but with VS 2015 the bug appears fixed as the test runs just
+     // fine.
+     //
+     // The bug seems to be a difference in return value of `exp2(-1057)`, where
+     // in VS 2013 it returns a double with the bit pattern 0x2 and in VS 2015 it
+     // returns 0x20000.
+     //
+     // For now just ignore this test entirely on MSVC as it's tested elsewhere
+     // anyway and we're not super interested in testing each platform's exp2
+     // implementation.
+     if !cfg!(target_env = "msvc") {
+         f64_exact_sanity_test(format_exact);
+     }
+     f32_exact_sanity_test(format_exact);
+ }
+ 
+ #[test]
+ fn test_to_shortest_str() {
+     to_shortest_str_test(format_shortest);
+ }
+ 
+ #[test]
+ fn test_to_shortest_exp_str() {
+     to_shortest_exp_str_test(format_shortest);
+ }
+ 
+ #[test]
+ fn test_to_exact_exp_str() {
+     to_exact_exp_str_test(format_exact);
+ }
+ 
+ #[test]
+ fn test_to_exact_fixed_str() {
+     to_exact_fixed_str_test(format_exact);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/grisu.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/grisu.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/grisu.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/flt2dec/strategy/grisu.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,73 ----
+ use super::super::*;
+ use core::num::flt2dec::strategy::grisu::*;
+ 
+ #[test]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn test_cached_power() {
+     assert_eq!(CACHED_POW10.first().unwrap().1, CACHED_POW10_FIRST_E);
+     assert_eq!(CACHED_POW10.last().unwrap().1, CACHED_POW10_LAST_E);
+ 
+     for e in -1137..961 {
+         // full range for f64
+         let low = ALPHA - e - 64;
+         let high = GAMMA - e - 64;
+         let (_k, cached) = cached_power(low, high);
+         assert!(
+             low <= cached.e && cached.e <= high,
+             "cached_power({}, {}) = {:?} is incorrect",
+             low,
+             high,
+             cached
+         );
+     }
+ }
+ 
+ #[test]
+ fn test_max_pow10_no_more_than() {
+     let mut prevtenk = 1;
+     for k in 1..10 {
+         let tenk = prevtenk * 10;
+         assert_eq!(max_pow10_no_more_than(tenk - 1), (k - 1, prevtenk));
+         assert_eq!(max_pow10_no_more_than(tenk), (k, tenk));
+         prevtenk = tenk;
+     }
+ }
+ 
+ #[cfg_attr(all(target_arch = "wasm32", target_os = "emscripten"), ignore)] // issue 42630
+ #[test]
+ fn shortest_sanity_test() {
+     f64_shortest_sanity_test(format_shortest);
+     f32_shortest_sanity_test(format_shortest);
+     more_shortest_sanity_test(format_shortest);
+ }
+ 
+ #[test]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn exact_sanity_test() {
+     // See comments in dragon.rs's exact_sanity_test for why this test is
+     // ignored on MSVC
+     if !cfg!(target_env = "msvc") {
+         f64_exact_sanity_test(format_exact);
+     }
+     f32_exact_sanity_test(format_exact);
+ }
+ 
+ #[test]
+ fn test_to_shortest_str() {
+     to_shortest_str_test(format_shortest);
+ }
+ 
+ #[test]
+ fn test_to_shortest_exp_str() {
+     to_shortest_exp_str_test(format_shortest);
+ }
+ 
+ #[test]
+ fn test_to_exact_exp_str() {
+     to_exact_exp_str_test(format_exact);
+ }
+ 
+ #[test]
+ fn test_to_exact_fixed_str() {
+     to_exact_fixed_str_test(format_exact);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i16.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i16.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i16.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i16.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ int_module!(i16, i16);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i32.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i32.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,30 ----
+ int_module!(i32, i32);
+ 
+ #[test]
+ fn test_arith_operation() {
+     let a: isize = 10;
+     assert_eq!(a * (a - 1), 90);
+     let i32_a: isize = 10;
+     assert_eq!(i32_a, 10);
+     assert_eq!(i32_a - 10, 0);
+     assert_eq!(i32_a / 10, 1);
+     assert_eq!(i32_a - 20, -10);
+     assert_eq!(i32_a << 10, 10240);
+     assert_eq!(i32_a << 16, 655360);
+     assert_eq!(i32_a * 16, 160);
+     assert_eq!(i32_a * i32_a * i32_a, 1000);
+     assert_eq!(i32_a * i32_a * i32_a * i32_a, 10000);
+     assert_eq!(i32_a * i32_a / i32_a * i32_a, 100);
+     assert_eq!(i32_a * (i32_a - 1) << (2 + i32_a as usize), 368640);
+     let i32_b: isize = 0x10101010;
+     assert_eq!(i32_b + 1 - 1, i32_b);
+     assert_eq!(i32_b << 1, i32_b << 1);
+     assert_eq!(i32_b >> 1, i32_b >> 1);
+     assert_eq!(i32_b & i32_b << 1, 0);
+     assert_eq!(i32_b | i32_b << 1, 0x30303030);
+     let i32_c: isize = 0x10101010;
+     assert_eq!(
+         i32_c + i32_c * 2 / 3 * 2 + (i32_c - 7 % 3),
+         i32_c + i32_c * 2 / 3 * 2 + (i32_c - 7 % 3)
+     );
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i64.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i64.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ int_module!(i64, i64);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i8.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i8.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/i8.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/i8.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ int_module!(i8, i8);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/int_macros.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/int_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/int_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/int_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,294 ----
+ macro_rules! int_module {
+     ($T:ident, $T_i:ident) => {
+         #[cfg(test)]
+         mod tests {
+             use core::ops::{BitAnd, BitOr, BitXor, Not, Shl, Shr};
+             use core::$T_i::*;
+ 
+             use crate::num;
+ 
+             #[test]
+             fn test_overflows() {
+                 assert!(MAX > 0);
+                 assert!(MIN <= 0);
+                 assert_eq!(MIN + MAX + 1, 0);
+             }
+ 
+             #[test]
+             fn test_num() {
+                 num::test_num(10 as $T, 2 as $T);
+             }
+ 
+             #[test]
+             fn test_rem_euclid() {
+                 assert_eq!((-1 as $T).rem_euclid(MIN), MAX);
+             }
+ 
+             #[test]
+             pub fn test_abs() {
+                 assert_eq!((1 as $T).abs(), 1 as $T);
+                 assert_eq!((0 as $T).abs(), 0 as $T);
+                 assert_eq!((-1 as $T).abs(), 1 as $T);
+             }
+ 
+             #[test]
+             fn test_signum() {
+                 assert_eq!((1 as $T).signum(), 1 as $T);
+                 assert_eq!((0 as $T).signum(), 0 as $T);
+                 assert_eq!((-0 as $T).signum(), 0 as $T);
+                 assert_eq!((-1 as $T).signum(), -1 as $T);
+             }
+ 
+             #[test]
+             fn test_is_positive() {
+                 assert!((1 as $T).is_positive());
+                 assert!(!(0 as $T).is_positive());
+                 assert!(!(-0 as $T).is_positive());
+                 assert!(!(-1 as $T).is_positive());
+             }
+ 
+             #[test]
+             fn test_is_negative() {
+                 assert!(!(1 as $T).is_negative());
+                 assert!(!(0 as $T).is_negative());
+                 assert!(!(-0 as $T).is_negative());
+                 assert!((-1 as $T).is_negative());
+             }
+ 
+             #[test]
+             fn test_bitwise_operators() {
+                 assert_eq!(0b1110 as $T, (0b1100 as $T).bitor(0b1010 as $T));
+                 assert_eq!(0b1000 as $T, (0b1100 as $T).bitand(0b1010 as $T));
+                 assert_eq!(0b0110 as $T, (0b1100 as $T).bitxor(0b1010 as $T));
+                 assert_eq!(0b1110 as $T, (0b0111 as $T).shl(1));
+                 assert_eq!(0b0111 as $T, (0b1110 as $T).shr(1));
+                 assert_eq!(-(0b11 as $T) - (1 as $T), (0b11 as $T).not());
+             }
+ 
+             const A: $T = 0b0101100;
+             const B: $T = 0b0100001;
+             const C: $T = 0b1111001;
+ 
+             const _0: $T = 0;
+             const _1: $T = !0;
+ 
+             #[test]
+             fn test_count_ones() {
+                 assert_eq!(A.count_ones(), 3);
+                 assert_eq!(B.count_ones(), 2);
+                 assert_eq!(C.count_ones(), 5);
+             }
+ 
+             #[test]
+             fn test_count_zeros() {
+                 assert_eq!(A.count_zeros(), $T::BITS - 3);
+                 assert_eq!(B.count_zeros(), $T::BITS - 2);
+                 assert_eq!(C.count_zeros(), $T::BITS - 5);
+             }
+ 
+             #[test]
+             fn test_leading_trailing_ones() {
+                 let a: $T = 0b0101_1111;
+                 assert_eq!(a.trailing_ones(), 5);
+                 assert_eq!((!a).leading_ones(), $T::BITS - 7);
+ 
+                 assert_eq!(a.reverse_bits().leading_ones(), 5);
+ 
+                 assert_eq!(_1.leading_ones(), $T::BITS);
+                 assert_eq!(_1.trailing_ones(), $T::BITS);
+ 
+                 assert_eq!((_1 << 1).trailing_ones(), 0);
+                 assert_eq!(MAX.leading_ones(), 0);
+ 
+                 assert_eq!((_1 << 1).leading_ones(), $T::BITS - 1);
+                 assert_eq!(MAX.trailing_ones(), $T::BITS - 1);
+ 
+                 assert_eq!(_0.leading_ones(), 0);
+                 assert_eq!(_0.trailing_ones(), 0);
+ 
+                 let x: $T = 0b0010_1100;
+                 assert_eq!(x.leading_ones(), 0);
+                 assert_eq!(x.trailing_ones(), 0);
+             }
+ 
+             #[test]
+             fn test_rotate() {
+                 assert_eq!(A.rotate_left(6).rotate_right(2).rotate_right(4), A);
+                 assert_eq!(B.rotate_left(3).rotate_left(2).rotate_right(5), B);
+                 assert_eq!(C.rotate_left(6).rotate_right(2).rotate_right(4), C);
+ 
+                 // Rotating these should make no difference
+                 //
+                 // We test using 124 bits because to ensure that overlong bit shifts do
+                 // not cause undefined behaviour. See #10183.
+                 assert_eq!(_0.rotate_left(124), _0);
+                 assert_eq!(_1.rotate_left(124), _1);
+                 assert_eq!(_0.rotate_right(124), _0);
+                 assert_eq!(_1.rotate_right(124), _1);
+ 
+                 // Rotating by 0 should have no effect
+                 assert_eq!(A.rotate_left(0), A);
+                 assert_eq!(B.rotate_left(0), B);
+                 assert_eq!(C.rotate_left(0), C);
+                 // Rotating by a multiple of word size should also have no effect
+                 assert_eq!(A.rotate_left(64), A);
+                 assert_eq!(B.rotate_left(64), B);
+                 assert_eq!(C.rotate_left(64), C);
+             }
+ 
+             #[test]
+             fn test_swap_bytes() {
+                 assert_eq!(A.swap_bytes().swap_bytes(), A);
+                 assert_eq!(B.swap_bytes().swap_bytes(), B);
+                 assert_eq!(C.swap_bytes().swap_bytes(), C);
+ 
+                 // Swapping these should make no difference
+                 assert_eq!(_0.swap_bytes(), _0);
+                 assert_eq!(_1.swap_bytes(), _1);
+             }
+ 
+             #[test]
+             fn test_le() {
+                 assert_eq!($T::from_le(A.to_le()), A);
+                 assert_eq!($T::from_le(B.to_le()), B);
+                 assert_eq!($T::from_le(C.to_le()), C);
+                 assert_eq!($T::from_le(_0), _0);
+                 assert_eq!($T::from_le(_1), _1);
+                 assert_eq!(_0.to_le(), _0);
+                 assert_eq!(_1.to_le(), _1);
+             }
+ 
+             #[test]
+             fn test_be() {
+                 assert_eq!($T::from_be(A.to_be()), A);
+                 assert_eq!($T::from_be(B.to_be()), B);
+                 assert_eq!($T::from_be(C.to_be()), C);
+                 assert_eq!($T::from_be(_0), _0);
+                 assert_eq!($T::from_be(_1), _1);
+                 assert_eq!(_0.to_be(), _0);
+                 assert_eq!(_1.to_be(), _1);
+             }
+ 
+             #[test]
+             fn test_signed_checked_div() {
+                 assert_eq!((10 as $T).checked_div(2), Some(5));
+                 assert_eq!((5 as $T).checked_div(0), None);
+                 assert_eq!(isize::MIN.checked_div(-1), None);
+             }
+ 
+             #[test]
+             fn test_saturating_abs() {
+                 assert_eq!((0 as $T).saturating_abs(), 0);
+                 assert_eq!((123 as $T).saturating_abs(), 123);
+                 assert_eq!((-123 as $T).saturating_abs(), 123);
+                 assert_eq!((MAX - 2).saturating_abs(), MAX - 2);
+                 assert_eq!((MAX - 1).saturating_abs(), MAX - 1);
+                 assert_eq!(MAX.saturating_abs(), MAX);
+                 assert_eq!((MIN + 2).saturating_abs(), MAX - 1);
+                 assert_eq!((MIN + 1).saturating_abs(), MAX);
+                 assert_eq!(MIN.saturating_abs(), MAX);
+             }
+ 
+             #[test]
+             fn test_saturating_neg() {
+                 assert_eq!((0 as $T).saturating_neg(), 0);
+                 assert_eq!((123 as $T).saturating_neg(), -123);
+                 assert_eq!((-123 as $T).saturating_neg(), 123);
+                 assert_eq!((MAX - 2).saturating_neg(), MIN + 3);
+                 assert_eq!((MAX - 1).saturating_neg(), MIN + 2);
+                 assert_eq!(MAX.saturating_neg(), MIN + 1);
+                 assert_eq!((MIN + 2).saturating_neg(), MAX - 1);
+                 assert_eq!((MIN + 1).saturating_neg(), MAX);
+                 assert_eq!(MIN.saturating_neg(), MAX);
+             }
+ 
+             #[test]
+             fn test_from_str() {
+                 fn from_str<T: std::str::FromStr>(t: &str) -> Option<T> {
+                     std::str::FromStr::from_str(t).ok()
+                 }
+                 assert_eq!(from_str::<$T>("0"), Some(0 as $T));
+                 assert_eq!(from_str::<$T>("3"), Some(3 as $T));
+                 assert_eq!(from_str::<$T>("10"), Some(10 as $T));
+                 assert_eq!(from_str::<i32>("123456789"), Some(123456789 as i32));
+                 assert_eq!(from_str::<$T>("00100"), Some(100 as $T));
+ 
+                 assert_eq!(from_str::<$T>("-1"), Some(-1 as $T));
+                 assert_eq!(from_str::<$T>("-3"), Some(-3 as $T));
+                 assert_eq!(from_str::<$T>("-10"), Some(-10 as $T));
+                 assert_eq!(from_str::<i32>("-123456789"), Some(-123456789 as i32));
+                 assert_eq!(from_str::<$T>("-00100"), Some(-100 as $T));
+ 
+                 assert_eq!(from_str::<$T>(""), None);
+                 assert_eq!(from_str::<$T>(" "), None);
+                 assert_eq!(from_str::<$T>("x"), None);
+             }
+ 
+             #[test]
+             fn test_from_str_radix() {
+                 assert_eq!($T::from_str_radix("123", 10), Ok(123 as $T));
+                 assert_eq!($T::from_str_radix("1001", 2), Ok(9 as $T));
+                 assert_eq!($T::from_str_radix("123", 8), Ok(83 as $T));
+                 assert_eq!(i32::from_str_radix("123", 16), Ok(291 as i32));
+                 assert_eq!(i32::from_str_radix("ffff", 16), Ok(65535 as i32));
+                 assert_eq!(i32::from_str_radix("FFFF", 16), Ok(65535 as i32));
+                 assert_eq!($T::from_str_radix("z", 36), Ok(35 as $T));
+                 assert_eq!($T::from_str_radix("Z", 36), Ok(35 as $T));
+ 
+                 assert_eq!($T::from_str_radix("-123", 10), Ok(-123 as $T));
+                 assert_eq!($T::from_str_radix("-1001", 2), Ok(-9 as $T));
+                 assert_eq!($T::from_str_radix("-123", 8), Ok(-83 as $T));
+                 assert_eq!(i32::from_str_radix("-123", 16), Ok(-291 as i32));
+                 assert_eq!(i32::from_str_radix("-ffff", 16), Ok(-65535 as i32));
+                 assert_eq!(i32::from_str_radix("-FFFF", 16), Ok(-65535 as i32));
+                 assert_eq!($T::from_str_radix("-z", 36), Ok(-35 as $T));
+                 assert_eq!($T::from_str_radix("-Z", 36), Ok(-35 as $T));
+ 
+                 assert_eq!($T::from_str_radix("Z", 35).ok(), None::<$T>);
+                 assert_eq!($T::from_str_radix("-9", 2).ok(), None::<$T>);
+             }
+ 
+             #[test]
+             fn test_pow() {
+                 let mut r = 2 as $T;
+                 assert_eq!(r.pow(2), 4 as $T);
+                 assert_eq!(r.pow(0), 1 as $T);
+                 assert_eq!(r.wrapping_pow(2), 4 as $T);
+                 assert_eq!(r.wrapping_pow(0), 1 as $T);
+                 assert_eq!(r.checked_pow(2), Some(4 as $T));
+                 assert_eq!(r.checked_pow(0), Some(1 as $T));
+                 assert_eq!(r.overflowing_pow(2), (4 as $T, false));
+                 assert_eq!(r.overflowing_pow(0), (1 as $T, false));
+                 assert_eq!(r.saturating_pow(2), 4 as $T);
+                 assert_eq!(r.saturating_pow(0), 1 as $T);
+ 
+                 r = MAX;
+                 // use `^` to represent .pow() with no overflow.
+                 // if itest::MAX == 2^j-1, then itest is a `j` bit int,
+                 // so that `itest::MAX*itest::MAX == 2^(2*j)-2^(j+1)+1`,
+                 // thussaturating_pow the overflowing result is exactly 1.
+                 assert_eq!(r.wrapping_pow(2), 1 as $T);
+                 assert_eq!(r.checked_pow(2), None);
+                 assert_eq!(r.overflowing_pow(2), (1 as $T, true));
+                 assert_eq!(r.saturating_pow(2), MAX);
+                 //test for negative exponent.
+                 r = -2 as $T;
+                 assert_eq!(r.pow(2), 4 as $T);
+                 assert_eq!(r.pow(3), -8 as $T);
+                 assert_eq!(r.pow(0), 1 as $T);
+                 assert_eq!(r.wrapping_pow(2), 4 as $T);
+                 assert_eq!(r.wrapping_pow(3), -8 as $T);
+                 assert_eq!(r.wrapping_pow(0), 1 as $T);
+                 assert_eq!(r.checked_pow(2), Some(4 as $T));
+                 assert_eq!(r.checked_pow(3), Some(-8 as $T));
+                 assert_eq!(r.checked_pow(0), Some(1 as $T));
+                 assert_eq!(r.overflowing_pow(2), (4 as $T, false));
+                 assert_eq!(r.overflowing_pow(3), (-8 as $T, false));
+                 assert_eq!(r.overflowing_pow(0), (1 as $T, false));
+                 assert_eq!(r.saturating_pow(2), 4 as $T);
+                 assert_eq!(r.saturating_pow(3), -8 as $T);
+                 assert_eq!(r.saturating_pow(0), 1 as $T);
+             }
+         }
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/mod.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,733 ----
+ use core::cmp::PartialEq;
+ use core::convert::{TryFrom, TryInto};
+ use core::fmt::Debug;
+ use core::marker::Copy;
+ use core::num::{IntErrorKind, ParseIntError, TryFromIntError};
+ use core::ops::{Add, Div, Mul, Rem, Sub};
+ use core::option::Option;
+ use core::option::Option::None;
+ use core::str::FromStr;
+ 
+ #[macro_use]
+ mod int_macros;
+ 
+ mod i16;
+ mod i32;
+ mod i64;
+ mod i8;
+ 
+ #[macro_use]
+ mod uint_macros;
+ 
+ mod u16;
+ mod u32;
+ mod u64;
+ mod u8;
+ 
+ mod bignum;
+ mod dec2flt;
+ mod flt2dec;
+ 
+ mod nan;
+ 
+ /// Adds the attribute to all items in the block.
+ macro_rules! cfg_block {
+     ($(#[$attr:meta]{$($it:item)*})*) => {$($(
+         #[$attr]
+         $it
+     )*)*}
+ }
+ 
+ /// Groups items that assume the pointer width is either 16/32/64, and has to be altered if
+ /// support for larger/smaller pointer widths are added in the future.
+ macro_rules! assume_usize_width {
+     {$($it:item)*} => {#[cfg(not(any(
+         target_pointer_width = "16", target_pointer_width = "32", target_pointer_width = "64")))]
+            compile_error!("The current tests of try_from on usize/isize assume that \
+                            the pointer width is either 16, 32, or 64");
+                     $($it)*
+     }
+ }
+ 
+ /// Helper function for testing numeric operations
+ pub fn test_num<T>(ten: T, two: T)
+ where
+     T: PartialEq
+         + Add<Output = T>
+         + Sub<Output = T>
+         + Mul<Output = T>
+         + Div<Output = T>
+         + Rem<Output = T>
+         + Debug
+         + Copy,
+ {
+     assert_eq!(ten.add(two), ten + two);
+     assert_eq!(ten.sub(two), ten - two);
+     assert_eq!(ten.mul(two), ten * two);
+     assert_eq!(ten.div(two), ten / two);
+     assert_eq!(ten.rem(two), ten % two);
+ }
+ 
+ /// Helper function for asserting number parsing returns a specific error
+ fn test_parse<T>(num_str: &str, expected: Result<T, IntErrorKind>)
+ where
+     T: FromStr<Err = ParseIntError>,
+     Result<T, IntErrorKind>: PartialEq + Debug,
+ {
+     assert_eq!(num_str.parse::<T>().map_err(|e| e.kind().clone()), expected)
+ }
+ 
+ #[test]
+ fn from_str_issue7588() {
+     let u: Option<u8> = u8::from_str_radix("1000", 10).ok();
+     assert_eq!(u, None);
+     let s: Option<i16> = i16::from_str_radix("80000", 10).ok();
+     assert_eq!(s, None);
+ }
+ 
+ #[test]
+ fn test_int_from_str_overflow() {
+     test_parse::<i8>("127", Ok(127));
+     test_parse::<i8>("128", Err(IntErrorKind::PosOverflow));
+ 
+     test_parse::<i8>("-128", Ok(-128));
+     test_parse::<i8>("-129", Err(IntErrorKind::NegOverflow));
+ 
+     test_parse::<i16>("32767", Ok(32_767));
+     test_parse::<i16>("32768", Err(IntErrorKind::PosOverflow));
+ 
+     test_parse::<i16>("-32768", Ok(-32_768));
+     test_parse::<i16>("-32769", Err(IntErrorKind::NegOverflow));
+ 
+     test_parse::<i32>("2147483647", Ok(2_147_483_647));
+     test_parse::<i32>("2147483648", Err(IntErrorKind::PosOverflow));
+ 
+     test_parse::<i32>("-2147483648", Ok(-2_147_483_648));
+     test_parse::<i32>("-2147483649", Err(IntErrorKind::NegOverflow));
+ 
+     test_parse::<i64>("9223372036854775807", Ok(9_223_372_036_854_775_807));
+     test_parse::<i64>("9223372036854775808", Err(IntErrorKind::PosOverflow));
+ 
+     test_parse::<i64>("-9223372036854775808", Ok(-9_223_372_036_854_775_808));
+     test_parse::<i64>("-9223372036854775809", Err(IntErrorKind::NegOverflow));
+ }
+ 
+ #[test]
+ fn test_leading_plus() {
+     test_parse::<u8>("+127", Ok(127));
+     test_parse::<i64>("+9223372036854775807", Ok(9223372036854775807));
+ }
+ 
+ #[test]
+ fn test_invalid() {
+     test_parse::<i8>("--129", Err(IntErrorKind::InvalidDigit));
+     test_parse::<i8>("++129", Err(IntErrorKind::InvalidDigit));
+     test_parse::<u8>("Съешь", Err(IntErrorKind::InvalidDigit));
+     test_parse::<u8>("123Hello", Err(IntErrorKind::InvalidDigit));
+     test_parse::<i8>("--", Err(IntErrorKind::InvalidDigit));
+     test_parse::<i8>("-", Err(IntErrorKind::InvalidDigit));
+     test_parse::<i8>("+", Err(IntErrorKind::InvalidDigit));
+     test_parse::<u8>("-1", Err(IntErrorKind::InvalidDigit));
+ }
+ 
+ #[test]
+ fn test_empty() {
+     test_parse::<u8>("", Err(IntErrorKind::Empty));
+ }
+ 
+ #[test]
+ fn test_infallible_try_from_int_error() {
+     let func = |x: i8| -> Result<i32, TryFromIntError> { Ok(x.try_into()?) };
+ 
+     assert!(func(0).is_ok());
+ }
+ 
+ macro_rules! test_impl_from {
+     ($fn_name:ident, bool, $target: ty) => {
+         #[test]
+         fn $fn_name() {
+             let one: $target = 1;
+             let zero: $target = 0;
+             assert_eq!(one, <$target>::from(true));
+             assert_eq!(zero, <$target>::from(false));
+         }
+     };
+     ($fn_name: ident, $Small: ty, $Large: ty) => {
+         #[test]
+         fn $fn_name() {
+             let small_max = <$Small>::MAX;
+             let small_min = <$Small>::MIN;
+             let large_max: $Large = small_max.into();
+             let large_min: $Large = small_min.into();
+             assert_eq!(large_max as $Small, small_max);
+             assert_eq!(large_min as $Small, small_min);
+         }
+     };
+ }
+ 
+ // Unsigned -> Unsigned
+ test_impl_from! { test_u8u16, u8, u16 }
+ test_impl_from! { test_u8u32, u8, u32 }
+ test_impl_from! { test_u8u64, u8, u64 }
+ test_impl_from! { test_u8usize, u8, usize }
+ test_impl_from! { test_u16u32, u16, u32 }
+ test_impl_from! { test_u16u64, u16, u64 }
+ test_impl_from! { test_u32u64, u32, u64 }
+ 
+ // Signed -> Signed
+ test_impl_from! { test_i8i16, i8, i16 }
+ test_impl_from! { test_i8i32, i8, i32 }
+ test_impl_from! { test_i8i64, i8, i64 }
+ test_impl_from! { test_i8isize, i8, isize }
+ test_impl_from! { test_i16i32, i16, i32 }
+ test_impl_from! { test_i16i64, i16, i64 }
+ test_impl_from! { test_i32i64, i32, i64 }
+ 
+ // Unsigned -> Signed
+ test_impl_from! { test_u8i16, u8, i16 }
+ test_impl_from! { test_u8i32, u8, i32 }
+ test_impl_from! { test_u8i64, u8, i64 }
+ test_impl_from! { test_u16i32, u16, i32 }
+ test_impl_from! { test_u16i64, u16, i64 }
+ test_impl_from! { test_u32i64, u32, i64 }
+ 
+ // Bool -> Integer
+ test_impl_from! { test_boolu8, bool, u8 }
+ test_impl_from! { test_boolu16, bool, u16 }
+ test_impl_from! { test_boolu32, bool, u32 }
+ test_impl_from! { test_boolu64, bool, u64 }
+ test_impl_from! { test_boolu128, bool, u128 }
+ test_impl_from! { test_booli8, bool, i8 }
+ test_impl_from! { test_booli16, bool, i16 }
+ test_impl_from! { test_booli32, bool, i32 }
+ test_impl_from! { test_booli64, bool, i64 }
+ test_impl_from! { test_booli128, bool, i128 }
+ 
+ // Signed -> Float
+ test_impl_from! { test_i8f32, i8, f32 }
+ test_impl_from! { test_i8f64, i8, f64 }
+ test_impl_from! { test_i16f32, i16, f32 }
+ test_impl_from! { test_i16f64, i16, f64 }
+ test_impl_from! { test_i32f64, i32, f64 }
+ 
+ // Unsigned -> Float
+ test_impl_from! { test_u8f32, u8, f32 }
+ test_impl_from! { test_u8f64, u8, f64 }
+ test_impl_from! { test_u16f32, u16, f32 }
+ test_impl_from! { test_u16f64, u16, f64 }
+ test_impl_from! { test_u32f64, u32, f64 }
+ 
+ // Float -> Float
+ #[test]
+ fn test_f32f64() {
+     let max: f64 = f32::MAX.into();
+     assert_eq!(max as f32, f32::MAX);
+     assert!(max.is_normal());
+ 
+     let min: f64 = f32::MIN.into();
+     assert_eq!(min as f32, f32::MIN);
+     assert!(min.is_normal());
+ 
+     let min_positive: f64 = f32::MIN_POSITIVE.into();
+     assert_eq!(min_positive as f32, f32::MIN_POSITIVE);
+     assert!(min_positive.is_normal());
+ 
+     let epsilon: f64 = f32::EPSILON.into();
+     assert_eq!(epsilon as f32, f32::EPSILON);
+     assert!(epsilon.is_normal());
+ 
+     let zero: f64 = (0.0f32).into();
+     assert_eq!(zero as f32, 0.0f32);
+     assert!(zero.is_sign_positive());
+ 
+     let neg_zero: f64 = (-0.0f32).into();
+     assert_eq!(neg_zero as f32, -0.0f32);
+     assert!(neg_zero.is_sign_negative());
+ 
+     let infinity: f64 = f32::INFINITY.into();
+     assert_eq!(infinity as f32, f32::INFINITY);
+     assert!(infinity.is_infinite());
+     assert!(infinity.is_sign_positive());
+ 
+     let neg_infinity: f64 = f32::NEG_INFINITY.into();
+     assert_eq!(neg_infinity as f32, f32::NEG_INFINITY);
+     assert!(neg_infinity.is_infinite());
+     assert!(neg_infinity.is_sign_negative());
+ 
+     let nan: f64 = f32::NAN.into();
+     assert!(nan.is_nan());
+ }
+ 
+ /// Conversions where the full width of $source can be represented as $target
+ macro_rules! test_impl_try_from_always_ok {
+     ($fn_name:ident, $source:ty, $target: ty) => {
+         #[test]
+         fn $fn_name() {
+             let max = <$source>::MAX;
+             let min = <$source>::MIN;
+             let zero: $source = 0;
+             assert_eq!(<$target as TryFrom<$source>>::try_from(max).unwrap(), max as $target);
+             assert_eq!(<$target as TryFrom<$source>>::try_from(min).unwrap(), min as $target);
+             assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target);
+         }
+     };
+ }
+ 
+ test_impl_try_from_always_ok! { test_try_u8u8, u8, u8 }
+ test_impl_try_from_always_ok! { test_try_u8u16, u8, u16 }
+ test_impl_try_from_always_ok! { test_try_u8u32, u8, u32 }
+ test_impl_try_from_always_ok! { test_try_u8u64, u8, u64 }
+ test_impl_try_from_always_ok! { test_try_u8u128, u8, u128 }
+ test_impl_try_from_always_ok! { test_try_u8i16, u8, i16 }
+ test_impl_try_from_always_ok! { test_try_u8i32, u8, i32 }
+ test_impl_try_from_always_ok! { test_try_u8i64, u8, i64 }
+ test_impl_try_from_always_ok! { test_try_u8i128, u8, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_u16u16, u16, u16 }
+ test_impl_try_from_always_ok! { test_try_u16u32, u16, u32 }
+ test_impl_try_from_always_ok! { test_try_u16u64, u16, u64 }
+ test_impl_try_from_always_ok! { test_try_u16u128, u16, u128 }
+ test_impl_try_from_always_ok! { test_try_u16i32, u16, i32 }
+ test_impl_try_from_always_ok! { test_try_u16i64, u16, i64 }
+ test_impl_try_from_always_ok! { test_try_u16i128, u16, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_u32u32, u32, u32 }
+ test_impl_try_from_always_ok! { test_try_u32u64, u32, u64 }
+ test_impl_try_from_always_ok! { test_try_u32u128, u32, u128 }
+ test_impl_try_from_always_ok! { test_try_u32i64, u32, i64 }
+ test_impl_try_from_always_ok! { test_try_u32i128, u32, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_u64u64, u64, u64 }
+ test_impl_try_from_always_ok! { test_try_u64u128, u64, u128 }
+ test_impl_try_from_always_ok! { test_try_u64i128, u64, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_u128u128, u128, u128 }
+ 
+ test_impl_try_from_always_ok! { test_try_i8i8, i8, i8 }
+ test_impl_try_from_always_ok! { test_try_i8i16, i8, i16 }
+ test_impl_try_from_always_ok! { test_try_i8i32, i8, i32 }
+ test_impl_try_from_always_ok! { test_try_i8i64, i8, i64 }
+ test_impl_try_from_always_ok! { test_try_i8i128, i8, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_i16i16, i16, i16 }
+ test_impl_try_from_always_ok! { test_try_i16i32, i16, i32 }
+ test_impl_try_from_always_ok! { test_try_i16i64, i16, i64 }
+ test_impl_try_from_always_ok! { test_try_i16i128, i16, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_i32i32, i32, i32 }
+ test_impl_try_from_always_ok! { test_try_i32i64, i32, i64 }
+ test_impl_try_from_always_ok! { test_try_i32i128, i32, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_i64i64, i64, i64 }
+ test_impl_try_from_always_ok! { test_try_i64i128, i64, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_i128i128, i128, i128 }
+ 
+ test_impl_try_from_always_ok! { test_try_usizeusize, usize, usize }
+ test_impl_try_from_always_ok! { test_try_isizeisize, isize, isize }
+ 
+ assume_usize_width! {
+     test_impl_try_from_always_ok! { test_try_u8usize, u8, usize }
+     test_impl_try_from_always_ok! { test_try_u8isize, u8, isize }
+     test_impl_try_from_always_ok! { test_try_i8isize, i8, isize }
+ 
+     test_impl_try_from_always_ok! { test_try_u16usize, u16, usize }
+     test_impl_try_from_always_ok! { test_try_i16isize, i16, isize }
+ 
+     test_impl_try_from_always_ok! { test_try_usizeu64, usize, u64 }
+     test_impl_try_from_always_ok! { test_try_usizeu128, usize, u128 }
+     test_impl_try_from_always_ok! { test_try_usizei128, usize, i128 }
+ 
+     test_impl_try_from_always_ok! { test_try_isizei64, isize, i64 }
+     test_impl_try_from_always_ok! { test_try_isizei128, isize, i128 }
+ 
+     cfg_block!(
+         #[cfg(target_pointer_width = "16")] {
+             test_impl_try_from_always_ok! { test_try_usizeu16, usize, u16 }
+             test_impl_try_from_always_ok! { test_try_isizei16, isize, i16 }
+             test_impl_try_from_always_ok! { test_try_usizeu32, usize, u32 }
+             test_impl_try_from_always_ok! { test_try_usizei32, usize, i32 }
+             test_impl_try_from_always_ok! { test_try_isizei32, isize, i32 }
+             test_impl_try_from_always_ok! { test_try_usizei64, usize, i64 }
+         }
+ 
+         #[cfg(target_pointer_width = "32")] {
+             test_impl_try_from_always_ok! { test_try_u16isize, u16, isize }
+             test_impl_try_from_always_ok! { test_try_usizeu32, usize, u32 }
+             test_impl_try_from_always_ok! { test_try_isizei32, isize, i32 }
+             test_impl_try_from_always_ok! { test_try_u32usize, u32, usize }
+             test_impl_try_from_always_ok! { test_try_i32isize, i32, isize }
+             test_impl_try_from_always_ok! { test_try_usizei64, usize, i64 }
+         }
+ 
+         #[cfg(target_pointer_width = "64")] {
+             test_impl_try_from_always_ok! { test_try_u16isize, u16, isize }
+             test_impl_try_from_always_ok! { test_try_u32usize, u32, usize }
+             test_impl_try_from_always_ok! { test_try_u32isize, u32, isize }
+             test_impl_try_from_always_ok! { test_try_i32isize, i32, isize }
+             test_impl_try_from_always_ok! { test_try_u64usize, u64, usize }
+             test_impl_try_from_always_ok! { test_try_i64isize, i64, isize }
+         }
+     );
+ }
+ 
+ /// Conversions where max of $source can be represented as $target,
+ macro_rules! test_impl_try_from_signed_to_unsigned_upper_ok {
+     ($fn_name:ident, $source:ty, $target:ty) => {
+         #[test]
+         fn $fn_name() {
+             let max = <$source>::MAX;
+             let min = <$source>::MIN;
+             let zero: $source = 0;
+             let neg_one: $source = -1;
+             assert_eq!(<$target as TryFrom<$source>>::try_from(max).unwrap(), max as $target);
+             assert!(<$target as TryFrom<$source>>::try_from(min).is_err());
+             assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target);
+             assert!(<$target as TryFrom<$source>>::try_from(neg_one).is_err());
+         }
+     };
+ }
+ 
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i8u8, i8, u8 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i8u16, i8, u16 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i8u32, i8, u32 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i8u64, i8, u64 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i8u128, i8, u128 }
+ 
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i16u16, i16, u16 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i16u32, i16, u32 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i16u64, i16, u64 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i16u128, i16, u128 }
+ 
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i32u32, i32, u32 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i32u64, i32, u64 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i32u128, i32, u128 }
+ 
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i64u64, i64, u64 }
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i64u128, i64, u128 }
+ 
+ test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i128u128, i128, u128 }
+ 
+ assume_usize_width! {
+     test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i8usize, i8, usize }
+     test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i16usize, i16, usize }
+ 
+     test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_isizeu64, isize, u64 }
+     test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_isizeu128, isize, u128 }
+     test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_isizeusize, isize, usize }
+ 
+     cfg_block!(
+         #[cfg(target_pointer_width = "16")] {
+             test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_isizeu16, isize, u16 }
+             test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_isizeu32, isize, u32 }
+         }
+ 
+         #[cfg(target_pointer_width = "32")] {
+             test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_isizeu32, isize, u32 }
+ 
+             test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i32usize, i32, usize }
+         }
+ 
+         #[cfg(target_pointer_width = "64")] {
+             test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i32usize, i32, usize }
+             test_impl_try_from_signed_to_unsigned_upper_ok! { test_try_i64usize, i64, usize }
+         }
+     );
+ }
+ 
+ /// Conversions where max of $source can not be represented as $target,
+ /// but min can.
+ macro_rules! test_impl_try_from_unsigned_to_signed_upper_err {
+     ($fn_name:ident, $source:ty, $target:ty) => {
+         #[test]
+         fn $fn_name() {
+             let max = <$source>::MAX;
+             let min = <$source>::MIN;
+             let zero: $source = 0;
+             assert!(<$target as TryFrom<$source>>::try_from(max).is_err());
+             assert_eq!(<$target as TryFrom<$source>>::try_from(min).unwrap(), min as $target);
+             assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target);
+         }
+     };
+ }
+ 
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u8i8, u8, i8 }
+ 
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u16i8, u16, i8 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u16i16, u16, i16 }
+ 
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u32i8, u32, i8 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u32i16, u32, i16 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u32i32, u32, i32 }
+ 
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u64i8, u64, i8 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u64i16, u64, i16 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u64i32, u64, i32 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u64i64, u64, i64 }
+ 
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u128i8, u128, i8 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u128i16, u128, i16 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u128i32, u128, i32 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u128i64, u128, i64 }
+ test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u128i128, u128, i128 }
+ 
+ assume_usize_width! {
+     test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u64isize, u64, isize }
+     test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u128isize, u128, isize }
+ 
+     test_impl_try_from_unsigned_to_signed_upper_err! { test_try_usizei8, usize, i8 }
+     test_impl_try_from_unsigned_to_signed_upper_err! { test_try_usizei16, usize, i16 }
+     test_impl_try_from_unsigned_to_signed_upper_err! { test_try_usizeisize, usize, isize }
+ 
+     cfg_block!(
+         #[cfg(target_pointer_width = "16")] {
+             test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u16isize, u16, isize }
+             test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u32isize, u32, isize }
+         }
+ 
+         #[cfg(target_pointer_width = "32")] {
+             test_impl_try_from_unsigned_to_signed_upper_err! { test_try_u32isize, u32, isize }
+             test_impl_try_from_unsigned_to_signed_upper_err! { test_try_usizei32, usize, i32 }
+         }
+ 
+         #[cfg(target_pointer_width = "64")] {
+             test_impl_try_from_unsigned_to_signed_upper_err! { test_try_usizei32, usize, i32 }
+             test_impl_try_from_unsigned_to_signed_upper_err! { test_try_usizei64, usize, i64 }
+         }
+     );
+ }
+ 
+ /// Conversions where min/max of $source can not be represented as $target.
+ macro_rules! test_impl_try_from_same_sign_err {
+     ($fn_name:ident, $source:ty, $target:ty) => {
+         #[test]
+         fn $fn_name() {
+             let max = <$source>::MAX;
+             let min = <$source>::MIN;
+             let zero: $source = 0;
+             let t_max = <$target>::MAX;
+             let t_min = <$target>::MIN;
+             assert!(<$target as TryFrom<$source>>::try_from(max).is_err());
+             if min != 0 {
+                 assert!(<$target as TryFrom<$source>>::try_from(min).is_err());
+             }
+             assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target);
+             assert_eq!(
+                 <$target as TryFrom<$source>>::try_from(t_max as $source).unwrap(),
+                 t_max as $target
+             );
+             assert_eq!(
+                 <$target as TryFrom<$source>>::try_from(t_min as $source).unwrap(),
+                 t_min as $target
+             );
+         }
+     };
+ }
+ 
+ test_impl_try_from_same_sign_err! { test_try_u16u8, u16, u8 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_u32u8, u32, u8 }
+ test_impl_try_from_same_sign_err! { test_try_u32u16, u32, u16 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_u64u8, u64, u8 }
+ test_impl_try_from_same_sign_err! { test_try_u64u16, u64, u16 }
+ test_impl_try_from_same_sign_err! { test_try_u64u32, u64, u32 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_u128u8, u128, u8 }
+ test_impl_try_from_same_sign_err! { test_try_u128u16, u128, u16 }
+ test_impl_try_from_same_sign_err! { test_try_u128u32, u128, u32 }
+ test_impl_try_from_same_sign_err! { test_try_u128u64, u128, u64 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_i16i8, i16, i8 }
+ test_impl_try_from_same_sign_err! { test_try_isizei8, isize, i8 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_i32i8, i32, i8 }
+ test_impl_try_from_same_sign_err! { test_try_i32i16, i32, i16 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_i64i8, i64, i8 }
+ test_impl_try_from_same_sign_err! { test_try_i64i16, i64, i16 }
+ test_impl_try_from_same_sign_err! { test_try_i64i32, i64, i32 }
+ 
+ test_impl_try_from_same_sign_err! { test_try_i128i8, i128, i8 }
+ test_impl_try_from_same_sign_err! { test_try_i128i16, i128, i16 }
+ test_impl_try_from_same_sign_err! { test_try_i128i32, i128, i32 }
+ test_impl_try_from_same_sign_err! { test_try_i128i64, i128, i64 }
+ 
+ assume_usize_width! {
+     test_impl_try_from_same_sign_err! { test_try_usizeu8, usize, u8 }
+     test_impl_try_from_same_sign_err! { test_try_u128usize, u128, usize }
+     test_impl_try_from_same_sign_err! { test_try_i128isize, i128, isize }
+ 
+     cfg_block!(
+         #[cfg(target_pointer_width = "16")] {
+             test_impl_try_from_same_sign_err! { test_try_u32usize, u32, usize }
+             test_impl_try_from_same_sign_err! { test_try_u64usize, u64, usize }
+ 
+             test_impl_try_from_same_sign_err! { test_try_i32isize, i32, isize }
+             test_impl_try_from_same_sign_err! { test_try_i64isize, i64, isize }
+         }
+ 
+         #[cfg(target_pointer_width = "32")] {
+             test_impl_try_from_same_sign_err! { test_try_u64usize, u64, usize }
+             test_impl_try_from_same_sign_err! { test_try_usizeu16, usize, u16 }
+ 
+             test_impl_try_from_same_sign_err! { test_try_i64isize, i64, isize }
+             test_impl_try_from_same_sign_err! { test_try_isizei16, isize, i16 }
+         }
+ 
+         #[cfg(target_pointer_width = "64")] {
+             test_impl_try_from_same_sign_err! { test_try_usizeu16, usize, u16 }
+             test_impl_try_from_same_sign_err! { test_try_usizeu32, usize, u32 }
+ 
+             test_impl_try_from_same_sign_err! { test_try_isizei16, isize, i16 }
+             test_impl_try_from_same_sign_err! { test_try_isizei32, isize, i32 }
+         }
+     );
+ }
+ 
+ /// Conversions where neither the min nor the max of $source can be represented by
+ /// $target, but max/min of the target can be represented by the source.
+ macro_rules! test_impl_try_from_signed_to_unsigned_err {
+     ($fn_name:ident, $source:ty, $target:ty) => {
+         #[test]
+         fn $fn_name() {
+             let max = <$source>::MAX;
+             let min = <$source>::MIN;
+             let zero: $source = 0;
+             let t_max = <$target>::MAX;
+             let t_min = <$target>::MIN;
+             assert!(<$target as TryFrom<$source>>::try_from(max).is_err());
+             assert!(<$target as TryFrom<$source>>::try_from(min).is_err());
+             assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target);
+             assert_eq!(
+                 <$target as TryFrom<$source>>::try_from(t_max as $source).unwrap(),
+                 t_max as $target
+             );
+             assert_eq!(
+                 <$target as TryFrom<$source>>::try_from(t_min as $source).unwrap(),
+                 t_min as $target
+             );
+         }
+     };
+ }
+ 
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i16u8, i16, u8 }
+ 
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i32u8, i32, u8 }
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i32u16, i32, u16 }
+ 
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i64u8, i64, u8 }
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i64u16, i64, u16 }
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i64u32, i64, u32 }
+ 
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i128u8, i128, u8 }
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i128u16, i128, u16 }
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i128u32, i128, u32 }
+ test_impl_try_from_signed_to_unsigned_err! { test_try_i128u64, i128, u64 }
+ 
+ assume_usize_width! {
+     test_impl_try_from_signed_to_unsigned_err! { test_try_isizeu8, isize, u8 }
+     test_impl_try_from_signed_to_unsigned_err! { test_try_i128usize, i128, usize }
+ 
+     cfg_block! {
+         #[cfg(target_pointer_width = "16")] {
+             test_impl_try_from_signed_to_unsigned_err! { test_try_i32usize, i32, usize }
+             test_impl_try_from_signed_to_unsigned_err! { test_try_i64usize, i64, usize }
+         }
+         #[cfg(target_pointer_width = "32")] {
+             test_impl_try_from_signed_to_unsigned_err! { test_try_i64usize, i64, usize }
+ 
+             test_impl_try_from_signed_to_unsigned_err! { test_try_isizeu16, isize, u16 }
+         }
+         #[cfg(target_pointer_width = "64")] {
+             test_impl_try_from_signed_to_unsigned_err! { test_try_isizeu16, isize, u16 }
+             test_impl_try_from_signed_to_unsigned_err! { test_try_isizeu32, isize, u32 }
+         }
+     }
+ }
+ 
+ macro_rules! test_float {
+     ($modname: ident, $fty: ty, $inf: expr, $neginf: expr, $nan: expr) => {
+         mod $modname {
+             #[test]
+             fn min() {
+                 assert_eq!((0.0 as $fty).min(0.0), 0.0);
+                 assert!((0.0 as $fty).min(0.0).is_sign_positive());
+                 assert_eq!((-0.0 as $fty).min(-0.0), -0.0);
+                 assert!((-0.0 as $fty).min(-0.0).is_sign_negative());
+                 assert_eq!((9.0 as $fty).min(9.0), 9.0);
+                 assert_eq!((-9.0 as $fty).min(0.0), -9.0);
+                 assert_eq!((0.0 as $fty).min(9.0), 0.0);
+                 assert!((0.0 as $fty).min(9.0).is_sign_positive());
+                 assert_eq!((-0.0 as $fty).min(9.0), -0.0);
+                 assert!((-0.0 as $fty).min(9.0).is_sign_negative());
+                 assert_eq!((-0.0 as $fty).min(-9.0), -9.0);
+                 assert_eq!(($inf as $fty).min(9.0), 9.0);
+                 assert_eq!((9.0 as $fty).min($inf), 9.0);
+                 assert_eq!(($inf as $fty).min(-9.0), -9.0);
+                 assert_eq!((-9.0 as $fty).min($inf), -9.0);
+                 assert_eq!(($neginf as $fty).min(9.0), $neginf);
+                 assert_eq!((9.0 as $fty).min($neginf), $neginf);
+                 assert_eq!(($neginf as $fty).min(-9.0), $neginf);
+                 assert_eq!((-9.0 as $fty).min($neginf), $neginf);
+                 assert_eq!(($nan as $fty).min(9.0), 9.0);
+                 assert_eq!(($nan as $fty).min(-9.0), -9.0);
+                 assert_eq!((9.0 as $fty).min($nan), 9.0);
+                 assert_eq!((-9.0 as $fty).min($nan), -9.0);
+                 assert!(($nan as $fty).min($nan).is_nan());
+             }
+             #[test]
+             fn max() {
+                 assert_eq!((0.0 as $fty).max(0.0), 0.0);
+                 assert!((0.0 as $fty).max(0.0).is_sign_positive());
+                 assert_eq!((-0.0 as $fty).max(-0.0), -0.0);
+                 assert!((-0.0 as $fty).max(-0.0).is_sign_negative());
+                 assert_eq!((9.0 as $fty).max(9.0), 9.0);
+                 assert_eq!((-9.0 as $fty).max(0.0), 0.0);
+                 assert!((-9.0 as $fty).max(0.0).is_sign_positive());
+                 assert_eq!((-9.0 as $fty).max(-0.0), -0.0);
+                 assert!((-9.0 as $fty).max(-0.0).is_sign_negative());
+                 assert_eq!((0.0 as $fty).max(9.0), 9.0);
+                 assert_eq!((0.0 as $fty).max(-9.0), 0.0);
+                 assert!((0.0 as $fty).max(-9.0).is_sign_positive());
+                 assert_eq!((-0.0 as $fty).max(-9.0), -0.0);
+                 assert!((-0.0 as $fty).max(-9.0).is_sign_negative());
+                 assert_eq!(($inf as $fty).max(9.0), $inf);
+                 assert_eq!((9.0 as $fty).max($inf), $inf);
+                 assert_eq!(($inf as $fty).max(-9.0), $inf);
+                 assert_eq!((-9.0 as $fty).max($inf), $inf);
+                 assert_eq!(($neginf as $fty).max(9.0), 9.0);
+                 assert_eq!((9.0 as $fty).max($neginf), 9.0);
+                 assert_eq!(($neginf as $fty).max(-9.0), -9.0);
+                 assert_eq!((-9.0 as $fty).max($neginf), -9.0);
+                 assert_eq!(($nan as $fty).max(9.0), 9.0);
+                 assert_eq!(($nan as $fty).max(-9.0), -9.0);
+                 assert_eq!((9.0 as $fty).max($nan), 9.0);
+                 assert_eq!((-9.0 as $fty).max($nan), -9.0);
+                 assert!(($nan as $fty).max($nan).is_nan());
+             }
+             #[test]
+             fn rem_euclid() {
+                 let a: $fty = 42.0;
+                 assert!($inf.rem_euclid(a).is_nan());
+                 assert_eq!(a.rem_euclid($inf), a);
+                 assert!(a.rem_euclid($nan).is_nan());
+                 assert!($inf.rem_euclid($inf).is_nan());
+                 assert!($inf.rem_euclid($nan).is_nan());
+                 assert!($nan.rem_euclid($inf).is_nan());
+             }
+             #[test]
+             fn div_euclid() {
+                 let a: $fty = 42.0;
+                 assert_eq!(a.div_euclid($inf), 0.0);
+                 assert!(a.div_euclid($nan).is_nan());
+                 assert!($inf.div_euclid($inf).is_nan());
+                 assert!($inf.div_euclid($nan).is_nan());
+                 assert!($nan.div_euclid($inf).is_nan());
+             }
+         }
+     };
+ }
+ 
+ test_float!(f32, f32, f32::INFINITY, f32::NEG_INFINITY, f32::NAN);
+ test_float!(f64, f64, f64::INFINITY, f64::NEG_INFINITY, f64::NAN);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/nan.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/nan.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/nan.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/nan.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,8 ----
+ #[test]
+ fn test_nan() {
+     use core::f64;
+     let x = "NaN".to_string();
+     assert_eq!(format!("{}", f64::NAN), x);
+     assert_eq!(format!("{:e}", f64::NAN), x);
+     assert_eq!(format!("{:E}", f64::NAN), x);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u16.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u16.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u16.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u16.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ uint_module!(u16, u16);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u32.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u32.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ uint_module!(u32, u32);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u64.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u64.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ uint_module!(u64, u64);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u8.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u8.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/u8.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/u8.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ uint_module!(u8, u8);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/uint_macros.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/uint_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/uint_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/uint_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,210 ----
+ macro_rules! uint_module {
+     ($T:ident, $T_i:ident) => {
+         #[cfg(test)]
+         mod tests {
+             use core::ops::{BitAnd, BitOr, BitXor, Not, Shl, Shr};
+             use core::$T_i::*;
+             use std::str::FromStr;
+ 
+             use crate::num;
+ 
+             #[test]
+             fn test_overflows() {
+                 assert!(MAX > 0);
+                 assert!(MIN <= 0);
+                 assert!((MIN + MAX).wrapping_add(1) == 0);
+             }
+ 
+             #[test]
+             fn test_num() {
+                 num::test_num(10 as $T, 2 as $T);
+             }
+ 
+             #[test]
+             fn test_bitwise_operators() {
+                 assert!(0b1110 as $T == (0b1100 as $T).bitor(0b1010 as $T));
+                 assert!(0b1000 as $T == (0b1100 as $T).bitand(0b1010 as $T));
+                 assert!(0b0110 as $T == (0b1100 as $T).bitxor(0b1010 as $T));
+                 assert!(0b1110 as $T == (0b0111 as $T).shl(1));
+                 assert!(0b0111 as $T == (0b1110 as $T).shr(1));
+                 assert!(MAX - (0b1011 as $T) == (0b1011 as $T).not());
+             }
+ 
+             const A: $T = 0b0101100;
+             const B: $T = 0b0100001;
+             const C: $T = 0b1111001;
+ 
+             const _0: $T = 0;
+             const _1: $T = !0;
+ 
+             #[test]
+             fn test_count_ones() {
+                 assert!(A.count_ones() == 3);
+                 assert!(B.count_ones() == 2);
+                 assert!(C.count_ones() == 5);
+             }
+ 
+             #[test]
+             fn test_count_zeros() {
+                 assert!(A.count_zeros() == $T::BITS - 3);
+                 assert!(B.count_zeros() == $T::BITS - 2);
+                 assert!(C.count_zeros() == $T::BITS - 5);
+             }
+ 
+             #[test]
+             fn test_leading_trailing_ones() {
+                 let a: $T = 0b0101_1111;
+                 assert_eq!(a.trailing_ones(), 5);
+                 assert_eq!((!a).leading_ones(), $T::BITS - 7);
+ 
+                 assert_eq!(a.reverse_bits().leading_ones(), 5);
+ 
+                 assert_eq!(_1.leading_ones(), $T::BITS);
+                 assert_eq!(_1.trailing_ones(), $T::BITS);
+ 
+                 assert_eq!((_1 << 1).trailing_ones(), 0);
+                 assert_eq!((_1 >> 1).leading_ones(), 0);
+ 
+                 assert_eq!((_1 << 1).leading_ones(), $T::BITS - 1);
+                 assert_eq!((_1 >> 1).trailing_ones(), $T::BITS - 1);
+ 
+                 assert_eq!(_0.leading_ones(), 0);
+                 assert_eq!(_0.trailing_ones(), 0);
+ 
+                 let x: $T = 0b0010_1100;
+                 assert_eq!(x.leading_ones(), 0);
+                 assert_eq!(x.trailing_ones(), 0);
+             }
+ 
+             #[test]
+             fn test_rotate() {
+                 assert_eq!(A.rotate_left(6).rotate_right(2).rotate_right(4), A);
+                 assert_eq!(B.rotate_left(3).rotate_left(2).rotate_right(5), B);
+                 assert_eq!(C.rotate_left(6).rotate_right(2).rotate_right(4), C);
+ 
+                 // Rotating these should make no difference
+                 //
+                 // We test using 124 bits because to ensure that overlong bit shifts do
+                 // not cause undefined behaviour. See #10183.
+                 assert_eq!(_0.rotate_left(124), _0);
+                 assert_eq!(_1.rotate_left(124), _1);
+                 assert_eq!(_0.rotate_right(124), _0);
+                 assert_eq!(_1.rotate_right(124), _1);
+ 
+                 // Rotating by 0 should have no effect
+                 assert_eq!(A.rotate_left(0), A);
+                 assert_eq!(B.rotate_left(0), B);
+                 assert_eq!(C.rotate_left(0), C);
+                 // Rotating by a multiple of word size should also have no effect
+                 assert_eq!(A.rotate_left(64), A);
+                 assert_eq!(B.rotate_left(64), B);
+                 assert_eq!(C.rotate_left(64), C);
+             }
+ 
+             #[test]
+             fn test_swap_bytes() {
+                 assert_eq!(A.swap_bytes().swap_bytes(), A);
+                 assert_eq!(B.swap_bytes().swap_bytes(), B);
+                 assert_eq!(C.swap_bytes().swap_bytes(), C);
+ 
+                 // Swapping these should make no difference
+                 assert_eq!(_0.swap_bytes(), _0);
+                 assert_eq!(_1.swap_bytes(), _1);
+             }
+ 
+             #[test]
+             fn test_reverse_bits() {
+                 assert_eq!(A.reverse_bits().reverse_bits(), A);
+                 assert_eq!(B.reverse_bits().reverse_bits(), B);
+                 assert_eq!(C.reverse_bits().reverse_bits(), C);
+ 
+                 // Swapping these should make no difference
+                 assert_eq!(_0.reverse_bits(), _0);
+                 assert_eq!(_1.reverse_bits(), _1);
+             }
+ 
+             #[test]
+             fn test_le() {
+                 assert_eq!($T::from_le(A.to_le()), A);
+                 assert_eq!($T::from_le(B.to_le()), B);
+                 assert_eq!($T::from_le(C.to_le()), C);
+                 assert_eq!($T::from_le(_0), _0);
+                 assert_eq!($T::from_le(_1), _1);
+                 assert_eq!(_0.to_le(), _0);
+                 assert_eq!(_1.to_le(), _1);
+             }
+ 
+             #[test]
+             fn test_be() {
+                 assert_eq!($T::from_be(A.to_be()), A);
+                 assert_eq!($T::from_be(B.to_be()), B);
+                 assert_eq!($T::from_be(C.to_be()), C);
+                 assert_eq!($T::from_be(_0), _0);
+                 assert_eq!($T::from_be(_1), _1);
+                 assert_eq!(_0.to_be(), _0);
+                 assert_eq!(_1.to_be(), _1);
+             }
+ 
+             #[test]
+             fn test_unsigned_checked_div() {
+                 assert!((10 as $T).checked_div(2) == Some(5));
+                 assert!((5 as $T).checked_div(0) == None);
+             }
+ 
+             fn from_str<T: FromStr>(t: &str) -> Option<T> {
+                 FromStr::from_str(t).ok()
+             }
+ 
+             #[test]
+             pub fn test_from_str() {
+                 assert_eq!(from_str::<$T>("0"), Some(0 as $T));
+                 assert_eq!(from_str::<$T>("3"), Some(3 as $T));
+                 assert_eq!(from_str::<$T>("10"), Some(10 as $T));
+                 assert_eq!(from_str::<u32>("123456789"), Some(123456789 as u32));
+                 assert_eq!(from_str::<$T>("00100"), Some(100 as $T));
+ 
+                 assert_eq!(from_str::<$T>(""), None);
+                 assert_eq!(from_str::<$T>(" "), None);
+                 assert_eq!(from_str::<$T>("x"), None);
+             }
+ 
+             #[test]
+             pub fn test_parse_bytes() {
+                 assert_eq!($T::from_str_radix("123", 10), Ok(123 as $T));
+                 assert_eq!($T::from_str_radix("1001", 2), Ok(9 as $T));
+                 assert_eq!($T::from_str_radix("123", 8), Ok(83 as $T));
+                 assert_eq!(u16::from_str_radix("123", 16), Ok(291 as u16));
+                 assert_eq!(u16::from_str_radix("ffff", 16), Ok(65535 as u16));
+                 assert_eq!($T::from_str_radix("z", 36), Ok(35 as $T));
+ 
+                 assert_eq!($T::from_str_radix("Z", 10).ok(), None::<$T>);
+                 assert_eq!($T::from_str_radix("_", 2).ok(), None::<$T>);
+             }
+ 
+             #[test]
+             fn test_pow() {
+                 let mut r = 2 as $T;
+                 assert_eq!(r.pow(2), 4 as $T);
+                 assert_eq!(r.pow(0), 1 as $T);
+                 assert_eq!(r.wrapping_pow(2), 4 as $T);
+                 assert_eq!(r.wrapping_pow(0), 1 as $T);
+                 assert_eq!(r.checked_pow(2), Some(4 as $T));
+                 assert_eq!(r.checked_pow(0), Some(1 as $T));
+                 assert_eq!(r.overflowing_pow(2), (4 as $T, false));
+                 assert_eq!(r.overflowing_pow(0), (1 as $T, false));
+                 assert_eq!(r.saturating_pow(2), 4 as $T);
+                 assert_eq!(r.saturating_pow(0), 1 as $T);
+ 
+                 r = MAX;
+                 // use `^` to represent .pow() with no overflow.
+                 // if itest::MAX == 2^j-1, then itest is a `j` bit int,
+                 // so that `itest::MAX*itest::MAX == 2^(2*j)-2^(j+1)+1`,
+                 // thussaturating_pow the overflowing result is exactly 1.
+                 assert_eq!(r.wrapping_pow(2), 1 as $T);
+                 assert_eq!(r.checked_pow(2), None);
+                 assert_eq!(r.overflowing_pow(2), (1 as $T, true));
+                 assert_eq!(r.saturating_pow(2), MAX);
+             }
+         }
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/num/wrapping.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/num/wrapping.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/num/wrapping.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/num/wrapping.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,76 ----
+ use core::num::Wrapping;
+ 
+ macro_rules! wrapping_operation {
+     ($result:expr, $lhs:ident $op:tt $rhs:expr) => {
+         assert_eq!($result, $lhs $op $rhs);
+         assert_eq!($result, &$lhs $op $rhs);
+         assert_eq!($result, $lhs $op &$rhs);
+         assert_eq!($result, &$lhs $op &$rhs);
+     };
+     ($result:expr, $op:tt $expr:expr) => {
+         assert_eq!($result, $op $expr);
+         assert_eq!($result, $op &$expr);
+     };
+ }
+ 
+ macro_rules! wrapping_assignment {
+     ($result:expr, $lhs:ident $op:tt $rhs:expr) => {
+         let mut lhs1 = $lhs;
+         lhs1 $op $rhs;
+         assert_eq!($result, lhs1);
+ 
+         let mut lhs2 = $lhs;
+         lhs2 $op &$rhs;
+         assert_eq!($result, lhs2);
+     };
+ }
+ 
+ macro_rules! wrapping_test {
+     ($type:ty, $min:expr, $max:expr) => {
+         #[test]
+         fn wrapping_$type() {
+             let zero: Wrapping<$type> = Wrapping(0);
+             let one: Wrapping<$type> = Wrapping(1);
+             let min: Wrapping<$type> = Wrapping($min);
+             let max: Wrapping<$type> = Wrapping($max);
+ 
+             wrapping_operation!(min, max + one);
+             wrapping_assignment!(min, max += one);
+             wrapping_operation!(max, min - one);
+             wrapping_assignment!(max, min -= one);
+             wrapping_operation!(max, max * one);
+             wrapping_assignment!(max, max *= one);
+             wrapping_operation!(max, max / one);
+             wrapping_assignment!(max, max /= one);
+             wrapping_operation!(zero, max % one);
+             wrapping_assignment!(zero, max %= one);
+             wrapping_operation!(zero, zero & max);
+             wrapping_assignment!(zero, zero &= max);
+             wrapping_operation!(max, zero | max);
+             wrapping_assignment!(max, zero |= max);
+             wrapping_operation!(zero, max ^ max);
+             wrapping_assignment!(zero, max ^= max);
+             wrapping_operation!(zero, zero << 1usize);
+             wrapping_assignment!(zero, zero <<= 1usize);
+             wrapping_operation!(zero, zero >> 1usize);
+             wrapping_assignment!(zero, zero >>= 1usize);
+             wrapping_operation!(zero, -zero);
+             wrapping_operation!(max, !min);
+         }
+     };
+ }
+ 
+ wrapping_test!(i8, i8::MIN, i8::MAX);
+ wrapping_test!(i16, i16::MIN, i16::MAX);
+ wrapping_test!(i32, i32::MIN, i32::MAX);
+ wrapping_test!(i64, i64::MIN, i64::MAX);
+ #[cfg(not(target_os = "emscripten"))]
+ wrapping_test!(i128, i128::MIN, i128::MAX);
+ wrapping_test!(isize, isize::MIN, isize::MAX);
+ wrapping_test!(u8, u8::MIN, u8::MAX);
+ wrapping_test!(u16, u16::MIN, u16::MAX);
+ wrapping_test!(u32, u32::MIN, u32::MAX);
+ wrapping_test!(u64, u64::MIN, u64::MAX);
+ #[cfg(not(target_os = "emscripten"))]
+ wrapping_test!(u128, u128::MIN, u128::MAX);
+ wrapping_test!(usize, usize::MIN, usize::MAX);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/ops.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/ops.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/ops.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/ops.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,153 ----
+ use core::ops::{Bound, Range, RangeFrom, RangeFull, RangeInclusive, RangeTo};
+ 
+ // Test the Range structs and syntax.
+ 
+ #[test]
+ fn test_range() {
+     let r = Range { start: 2, end: 10 };
+     let mut count = 0;
+     for (i, ri) in r.enumerate() {
+         assert_eq!(ri, i + 2);
+         assert!(ri >= 2 && ri < 10);
+         count += 1;
+     }
+     assert_eq!(count, 8);
+ }
+ 
+ #[test]
+ fn test_range_from() {
+     let r = RangeFrom { start: 2 };
+     let mut count = 0;
+     for (i, ri) in r.take(10).enumerate() {
+         assert_eq!(ri, i + 2);
+         assert!(ri >= 2 && ri < 12);
+         count += 1;
+     }
+     assert_eq!(count, 10);
+ }
+ 
+ #[test]
+ fn test_range_to() {
+     // Not much to test.
+     let _ = RangeTo { end: 42 };
+ }
+ 
+ #[test]
+ fn test_full_range() {
+     // Not much to test.
+     let _ = RangeFull;
+ }
+ 
+ #[test]
+ fn test_range_inclusive() {
+     let mut r = RangeInclusive::new(1i8, 2);
+     assert_eq!(r.next(), Some(1));
+     assert_eq!(r.next(), Some(2));
+     assert_eq!(r.next(), None);
+ 
+     r = RangeInclusive::new(127i8, 127);
+     assert_eq!(r.next(), Some(127));
+     assert_eq!(r.next(), None);
+ 
+     r = RangeInclusive::new(-128i8, -128);
+     assert_eq!(r.next_back(), Some(-128));
+     assert_eq!(r.next_back(), None);
+ 
+     // degenerate
+     r = RangeInclusive::new(1, -1);
+     assert_eq!(r.size_hint(), (0, Some(0)));
+     assert_eq!(r.next(), None);
+ }
+ 
+ #[test]
+ fn test_range_is_empty() {
+     assert!(!(0.0..10.0).is_empty());
+     assert!((-0.0..0.0).is_empty());
+     assert!((10.0..0.0).is_empty());
+ 
+     assert!(!(f32::NEG_INFINITY..f32::INFINITY).is_empty());
+     assert!((f32::EPSILON..f32::NAN).is_empty());
+     assert!((f32::NAN..f32::EPSILON).is_empty());
+     assert!((f32::NAN..f32::NAN).is_empty());
+ 
+     assert!(!(0.0..=10.0).is_empty());
+     assert!(!(-0.0..=0.0).is_empty());
+     assert!((10.0..=0.0).is_empty());
+ 
+     assert!(!(f32::NEG_INFINITY..=f32::INFINITY).is_empty());
+     assert!((f32::EPSILON..=f32::NAN).is_empty());
+     assert!((f32::NAN..=f32::EPSILON).is_empty());
+     assert!((f32::NAN..=f32::NAN).is_empty());
+ }
+ 
+ #[test]
+ fn test_bound_cloned_unbounded() {
+     assert_eq!(Bound::<&u32>::Unbounded.cloned(), Bound::Unbounded);
+ }
+ 
+ #[test]
+ fn test_bound_cloned_included() {
+     assert_eq!(Bound::Included(&3).cloned(), Bound::Included(3));
+ }
+ 
+ #[test]
+ fn test_bound_cloned_excluded() {
+     assert_eq!(Bound::Excluded(&3).cloned(), Bound::Excluded(3));
+ }
+ 
+ #[test]
+ #[allow(unused_comparisons)]
+ #[allow(unused_mut)]
+ fn test_range_syntax() {
+     let mut count = 0;
+     for i in 0_usize..10 {
+         assert!(i >= 0 && i < 10);
+         count += i;
+     }
+     assert_eq!(count, 45);
+ 
+     let mut count = 0;
+     let mut range = 0_usize..10;
+     for i in range {
+         assert!(i >= 0 && i < 10);
+         count += i;
+     }
+     assert_eq!(count, 45);
+ 
+     let mut count = 0;
+     let mut rf = 3_usize..;
+     for i in rf.take(10) {
+         assert!(i >= 3 && i < 13);
+         count += i;
+     }
+     assert_eq!(count, 75);
+ 
+     let _ = 0_usize..4 + 4 - 3;
+ 
+     fn foo() -> isize {
+         42
+     }
+     let _ = 0..foo();
+ 
+     let _ = { &42..&100 }; // references to literals are OK
+     let _ = ..42_usize;
+ 
+     // Test we can use two different types with a common supertype.
+     let x = &42;
+     {
+         let y = 42;
+         let _ = x..&y;
+     }
+ }
+ 
+ #[test]
+ #[allow(dead_code)]
+ fn test_range_syntax_in_return_statement() {
+     fn return_range_to() -> RangeTo<i32> {
+         return ..1;
+     }
+     fn return_full_range() -> RangeFull {
+         return ..;
+     }
+     // Not much to test.
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/option.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/option.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/option.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/option.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,404 ----
+ use core::cell::Cell;
+ use core::clone::Clone;
+ use core::mem;
+ use core::ops::DerefMut;
+ use core::option::*;
+ 
+ #[test]
+ fn test_get_ptr() {
+     unsafe {
+         let x: Box<_> = box 0;
+         let addr_x: *const isize = mem::transmute(&*x);
+         let opt = Some(x);
+         let y = opt.unwrap();
+         let addr_y: *const isize = mem::transmute(&*y);
+         assert_eq!(addr_x, addr_y);
+     }
+ }
+ 
+ #[test]
+ fn test_get_str() {
+     let x = "test".to_string();
+     let addr_x = x.as_ptr();
+     let opt = Some(x);
+     let y = opt.unwrap();
+     let addr_y = y.as_ptr();
+     assert_eq!(addr_x, addr_y);
+ }
+ 
+ #[test]
+ fn test_get_resource() {
+     use core::cell::RefCell;
+     use std::rc::Rc;
+ 
+     struct R {
+         i: Rc<RefCell<isize>>,
+     }
+ 
+     impl Drop for R {
+         fn drop(&mut self) {
+             let ii = &*self.i;
+             let i = *ii.borrow();
+             *ii.borrow_mut() = i + 1;
+         }
+     }
+ 
+     fn r(i: Rc<RefCell<isize>>) -> R {
+         R { i }
+     }
+ 
+     let i = Rc::new(RefCell::new(0));
+     {
+         let x = r(i.clone());
+         let opt = Some(x);
+         let _y = opt.unwrap();
+     }
+     assert_eq!(*i.borrow(), 1);
+ }
+ 
+ #[test]
+ fn test_option_dance() {
+     let x = Some(());
+     let mut y = Some(5);
+     let mut y2 = 0;
+     for _x in x {
+         y2 = y.take().unwrap();
+     }
+     assert_eq!(y2, 5);
+     assert!(y.is_none());
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_option_too_much_dance() {
+     struct A;
+     let mut y = Some(A);
+     let _y2 = y.take().unwrap();
+     let _y3 = y.take().unwrap();
+ }
+ 
+ #[test]
+ fn test_and() {
+     let x: Option<isize> = Some(1);
+     assert_eq!(x.and(Some(2)), Some(2));
+     assert_eq!(x.and(None::<isize>), None);
+ 
+     let x: Option<isize> = None;
+     assert_eq!(x.and(Some(2)), None);
+     assert_eq!(x.and(None::<isize>), None);
+ }
+ 
+ #[test]
+ fn test_and_then() {
+     let x: Option<isize> = Some(1);
+     assert_eq!(x.and_then(|x| Some(x + 1)), Some(2));
+     assert_eq!(x.and_then(|_| None::<isize>), None);
+ 
+     let x: Option<isize> = None;
+     assert_eq!(x.and_then(|x| Some(x + 1)), None);
+     assert_eq!(x.and_then(|_| None::<isize>), None);
+ }
+ 
+ #[test]
+ fn test_or() {
+     let x: Option<isize> = Some(1);
+     assert_eq!(x.or(Some(2)), Some(1));
+     assert_eq!(x.or(None), Some(1));
+ 
+     let x: Option<isize> = None;
+     assert_eq!(x.or(Some(2)), Some(2));
+     assert_eq!(x.or(None), None);
+ }
+ 
+ #[test]
+ fn test_or_else() {
+     let x: Option<isize> = Some(1);
+     assert_eq!(x.or_else(|| Some(2)), Some(1));
+     assert_eq!(x.or_else(|| None), Some(1));
+ 
+     let x: Option<isize> = None;
+     assert_eq!(x.or_else(|| Some(2)), Some(2));
+     assert_eq!(x.or_else(|| None), None);
+ }
+ 
+ #[test]
+ fn test_unwrap() {
+     assert_eq!(Some(1).unwrap(), 1);
+     let s = Some("hello".to_string()).unwrap();
+     assert_eq!(s, "hello");
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_unwrap_panic1() {
+     let x: Option<isize> = None;
+     x.unwrap();
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn test_unwrap_panic2() {
+     let x: Option<String> = None;
+     x.unwrap();
+ }
+ 
+ #[test]
+ fn test_unwrap_or() {
+     let x: Option<isize> = Some(1);
+     assert_eq!(x.unwrap_or(2), 1);
+ 
+     let x: Option<isize> = None;
+     assert_eq!(x.unwrap_or(2), 2);
+ }
+ 
+ #[test]
+ fn test_unwrap_or_else() {
+     let x: Option<isize> = Some(1);
+     assert_eq!(x.unwrap_or_else(|| 2), 1);
+ 
+     let x: Option<isize> = None;
+     assert_eq!(x.unwrap_or_else(|| 2), 2);
+ }
+ 
+ #[test]
+ fn test_iter() {
+     let val = 5;
+ 
+     let x = Some(val);
+     let mut it = x.iter();
+ 
+     assert_eq!(it.size_hint(), (1, Some(1)));
+     assert_eq!(it.next(), Some(&val));
+     assert_eq!(it.size_hint(), (0, Some(0)));
+     assert!(it.next().is_none());
+ 
+     let mut it = (&x).into_iter();
+     assert_eq!(it.next(), Some(&val));
+ }
+ 
+ #[test]
+ fn test_mut_iter() {
+     let mut val = 5;
+     let new_val = 11;
+ 
+     let mut x = Some(val);
+     {
+         let mut it = x.iter_mut();
+ 
+         assert_eq!(it.size_hint(), (1, Some(1)));
+ 
+         match it.next() {
+             Some(interior) => {
+                 assert_eq!(*interior, val);
+                 *interior = new_val;
+             }
+             None => assert!(false),
+         }
+ 
+         assert_eq!(it.size_hint(), (0, Some(0)));
+         assert!(it.next().is_none());
+     }
+     assert_eq!(x, Some(new_val));
+ 
+     let mut y = Some(val);
+     let mut it = (&mut y).into_iter();
+     assert_eq!(it.next(), Some(&mut val));
+ }
+ 
+ #[test]
+ fn test_ord() {
+     let small = Some(1.0f64);
+     let big = Some(5.0f64);
+     let nan = Some(0.0f64 / 0.0);
+     assert!(!(nan < big));
+     assert!(!(nan > big));
+     assert!(small < big);
+     assert!(None < big);
+     assert!(big > None);
+ }
+ 
+ #[test]
+ fn test_collect() {
+     let v: Option<Vec<isize>> = (0..0).map(|_| Some(0)).collect();
+     assert!(v == Some(vec![]));
+ 
+     let v: Option<Vec<isize>> = (0..3).map(|x| Some(x)).collect();
+     assert!(v == Some(vec![0, 1, 2]));
+ 
+     let v: Option<Vec<isize>> = (0..3).map(|x| if x > 1 { None } else { Some(x) }).collect();
+     assert!(v == None);
+ 
+     // test that it does not take more elements than it needs
+     let mut functions: [Box<dyn Fn() -> Option<()>>; 3] =
+         [box || Some(()), box || None, box || panic!()];
+ 
+     let v: Option<Vec<()>> = functions.iter_mut().map(|f| (*f)()).collect();
+ 
+     assert!(v == None);
+ }
+ 
+ #[test]
+ fn test_copied() {
+     let val = 1;
+     let val_ref = &val;
+     let opt_none: Option<&'static u32> = None;
+     let opt_ref = Some(&val);
+     let opt_ref_ref = Some(&val_ref);
+ 
+     // None works
+     assert_eq!(opt_none.clone(), None);
+     assert_eq!(opt_none.copied(), None);
+ 
+     // Immutable ref works
+     assert_eq!(opt_ref.clone(), Some(&val));
+     assert_eq!(opt_ref.copied(), Some(1));
+ 
+     // Double Immutable ref works
+     assert_eq!(opt_ref_ref.clone(), Some(&val_ref));
+     assert_eq!(opt_ref_ref.clone().copied(), Some(&val));
+     assert_eq!(opt_ref_ref.copied().copied(), Some(1));
+ }
+ 
+ #[test]
+ fn test_cloned() {
+     let val = 1;
+     let val_ref = &val;
+     let opt_none: Option<&'static u32> = None;
+     let opt_ref = Some(&val);
+     let opt_ref_ref = Some(&val_ref);
+ 
+     // None works
+     assert_eq!(opt_none.clone(), None);
+     assert_eq!(opt_none.cloned(), None);
+ 
+     // Immutable ref works
+     assert_eq!(opt_ref.clone(), Some(&val));
+     assert_eq!(opt_ref.cloned(), Some(1));
+ 
+     // Double Immutable ref works
+     assert_eq!(opt_ref_ref.clone(), Some(&val_ref));
+     assert_eq!(opt_ref_ref.clone().cloned(), Some(&val));
+     assert_eq!(opt_ref_ref.cloned().cloned(), Some(1));
+ }
+ 
+ #[test]
+ fn test_try() {
+     fn try_option_some() -> Option<u8> {
+         let val = Some(1)?;
+         Some(val)
+     }
+     assert_eq!(try_option_some(), Some(1));
+ 
+     fn try_option_none() -> Option<u8> {
+         let val = None?;
+         Some(val)
+     }
+     assert_eq!(try_option_none(), None);
+ 
+     fn try_option_ok() -> Result<u8, NoneError> {
+         let val = Some(1)?;
+         Ok(val)
+     }
+     assert_eq!(try_option_ok(), Ok(1));
+ 
+     fn try_option_err() -> Result<u8, NoneError> {
+         let val = None?;
+         Ok(val)
+     }
+     assert_eq!(try_option_err(), Err(NoneError));
+ }
+ 
+ #[test]
+ fn test_option_as_deref() {
+     // Some: &Option<T: Deref>::Some(T) -> Option<&T::Deref::Target>::Some(&*T)
+     let ref_option = &Some(&42);
+     assert_eq!(ref_option.as_deref(), Some(&42));
+ 
+     let ref_option = &Some(String::from("a result"));
+     assert_eq!(ref_option.as_deref(), Some("a result"));
+ 
+     let ref_option = &Some(vec![1, 2, 3, 4, 5]);
+     assert_eq!(ref_option.as_deref(), Some([1, 2, 3, 4, 5].as_slice()));
+ 
+     // None: &Option<T: Deref>>::None -> None
+     let ref_option: &Option<&i32> = &None;
+     assert_eq!(ref_option.as_deref(), None);
+ }
+ 
+ #[test]
+ fn test_option_as_deref_mut() {
+     // Some: &mut Option<T: Deref>::Some(T) -> Option<&mut T::Deref::Target>::Some(&mut *T)
+     let mut val = 42;
+     let ref_option = &mut Some(&mut val);
+     assert_eq!(ref_option.as_deref_mut(), Some(&mut 42));
+ 
+     let ref_option = &mut Some(String::from("a result"));
+     assert_eq!(ref_option.as_deref_mut(), Some(String::from("a result").deref_mut()));
+ 
+     let ref_option = &mut Some(vec![1, 2, 3, 4, 5]);
+     assert_eq!(ref_option.as_deref_mut(), Some([1, 2, 3, 4, 5].as_mut_slice()));
+ 
+     // None: &mut Option<T: Deref>>::None -> None
+     let ref_option: &mut Option<&mut i32> = &mut None;
+     assert_eq!(ref_option.as_deref_mut(), None);
+ }
+ 
+ #[test]
+ fn test_replace() {
+     let mut x = Some(2);
+     let old = x.replace(5);
+ 
+     assert_eq!(x, Some(5));
+     assert_eq!(old, Some(2));
+ 
+     let mut x = None;
+     let old = x.replace(3);
+ 
+     assert_eq!(x, Some(3));
+     assert_eq!(old, None);
+ }
+ 
+ #[test]
+ fn option_const() {
+     // test that the methods of `Option` are usable in a const context
+ 
+     const OPTION: Option<usize> = Some(32);
+ 
+     const REF: Option<&usize> = OPTION.as_ref();
+     assert_eq!(REF, Some(&32));
+ 
+     const IS_SOME: bool = OPTION.is_some();
+     assert!(IS_SOME);
+ 
+     const IS_NONE: bool = OPTION.is_none();
+     assert!(!IS_NONE);
+ }
+ 
+ #[test]
+ fn test_unwrap_drop() {
+     struct Dtor<'a> {
+         x: &'a Cell<isize>,
+     }
+ 
+     impl<'a> std::ops::Drop for Dtor<'a> {
+         fn drop(&mut self) {
+             self.x.set(self.x.get() - 1);
+         }
+     }
+ 
+     fn unwrap<T>(o: Option<T>) -> T {
+         match o {
+             Some(v) => v,
+             None => panic!(),
+         }
+     }
+ 
+     let x = &Cell::new(1);
+ 
+     {
+         let b = Some(Dtor { x });
+         let _c = unwrap(b);
+     }
+ 
+     assert_eq!(x.get(), 0);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/pattern.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/pattern.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/pattern.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/pattern.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,503 ----
+ use std::str::pattern::*;
+ 
+ // This macro makes it easier to write
+ // tests that do a series of iterations
+ macro_rules! search_asserts {
+     ($haystack:expr, $needle:expr, $testname:expr, [$($func:ident),*], $result:expr) => {
+         let mut searcher = $needle.into_searcher($haystack);
+         let arr = [$( Step::from(searcher.$func()) ),*];
+         assert_eq!(&arr[..], &$result, $testname);
+     }
+ }
+ 
+ /// Combined enum for the results of next() and next_match()/next_reject()
+ #[derive(Debug, PartialEq, Eq)]
+ enum Step {
+     // variant names purposely chosen to
+     // be the same length for easy alignment
+     Matches(usize, usize),
+     Rejects(usize, usize),
+     InRange(usize, usize),
+     Done,
+ }
+ 
+ use self::Step::*;
+ 
+ impl From<SearchStep> for Step {
+     fn from(x: SearchStep) -> Self {
+         match x {
+             SearchStep::Match(a, b) => Matches(a, b),
+             SearchStep::Reject(a, b) => Rejects(a, b),
+             SearchStep::Done => Done,
+         }
+     }
+ }
+ 
+ impl From<Option<(usize, usize)>> for Step {
+     fn from(x: Option<(usize, usize)>) -> Self {
+         match x {
+             Some((a, b)) => InRange(a, b),
+             None => Done,
+         }
+     }
+ }
+ 
+ // FIXME(Manishearth) these tests focus on single-character searching  (CharSearcher)
+ // and on next()/next_match(), not next_reject(). This is because
+ // the memchr changes make next_match() for single chars complex, but next_reject()
+ // continues to use next() under the hood. We should add more test cases for all
+ // of these, as well as tests for StrSearcher and higher level tests for str::find() (etc)
+ 
+ #[test]
+ fn test_simple_iteration() {
+     search_asserts!(
+         "abcdeabcd",
+         'a',
+         "forward iteration for ASCII string",
+         // a            b              c              d              e              a              b              c              d              EOF
+         [next, next, next, next, next, next, next, next, next, next],
+         [
+             Matches(0, 1),
+             Rejects(1, 2),
+             Rejects(2, 3),
+             Rejects(3, 4),
+             Rejects(4, 5),
+             Matches(5, 6),
+             Rejects(6, 7),
+             Rejects(7, 8),
+             Rejects(8, 9),
+             Done
+         ]
+     );
+ 
+     search_asserts!(
+         "abcdeabcd",
+         'a',
+         "reverse iteration for ASCII string",
+         // d            c              b              a            e                d              c              b              a             EOF
+         [
+             next_back, next_back, next_back, next_back, next_back, next_back, next_back, next_back,
+             next_back, next_back
+         ],
+         [
+             Rejects(8, 9),
+             Rejects(7, 8),
+             Rejects(6, 7),
+             Matches(5, 6),
+             Rejects(4, 5),
+             Rejects(3, 4),
+             Rejects(2, 3),
+             Rejects(1, 2),
+             Matches(0, 1),
+             Done
+         ]
+     );
+ 
+     search_asserts!(
+         "我爱我的猫",
+         '我',
+         "forward iteration for Chinese string",
+         // 我           愛             我             的              貓               EOF
+         [next, next, next, next, next, next],
+         [Matches(0, 3), Rejects(3, 6), Matches(6, 9), Rejects(9, 12), Rejects(12, 15), Done]
+     );
+ 
+     search_asserts!(
+         "我的猫说meow",
+         'm',
+         "forward iteration for mixed string",
+         // 我           的             猫             说              m                e                o                w                EOF
+         [next, next, next, next, next, next, next, next, next],
+         [
+             Rejects(0, 3),
+             Rejects(3, 6),
+             Rejects(6, 9),
+             Rejects(9, 12),
+             Matches(12, 13),
+             Rejects(13, 14),
+             Rejects(14, 15),
+             Rejects(15, 16),
+             Done
+         ]
+     );
+ 
+     search_asserts!(
+         "我的猫说meow",
+         '猫',
+         "reverse iteration for mixed string",
+         // w             o                 e                m                说              猫             的             我             EOF
+         [
+             next_back, next_back, next_back, next_back, next_back, next_back, next_back, next_back,
+             next_back
+         ],
+         [
+             Rejects(15, 16),
+             Rejects(14, 15),
+             Rejects(13, 14),
+             Rejects(12, 13),
+             Rejects(9, 12),
+             Matches(6, 9),
+             Rejects(3, 6),
+             Rejects(0, 3),
+             Done
+         ]
+     );
+ }
+ 
+ #[test]
+ fn test_simple_search() {
+     search_asserts!(
+         "abcdeabcdeabcde",
+         'a',
+         "next_match for ASCII string",
+         [next_match, next_match, next_match, next_match],
+         [InRange(0, 1), InRange(5, 6), InRange(10, 11), Done]
+     );
+ 
+     search_asserts!(
+         "abcdeabcdeabcde",
+         'a',
+         "next_match_back for ASCII string",
+         [next_match_back, next_match_back, next_match_back, next_match_back],
+         [InRange(10, 11), InRange(5, 6), InRange(0, 1), Done]
+     );
+ 
+     search_asserts!(
+         "abcdeab",
+         'a',
+         "next_reject for ASCII string",
+         [next_reject, next_reject, next_match, next_reject, next_reject],
+         [InRange(1, 2), InRange(2, 3), InRange(5, 6), InRange(6, 7), Done]
+     );
+ 
+     search_asserts!(
+         "abcdeabcdeabcde",
+         'a',
+         "next_reject_back for ASCII string",
+         [
+             next_reject_back,
+             next_reject_back,
+             next_match_back,
+             next_reject_back,
+             next_reject_back,
+             next_reject_back
+         ],
+         [
+             InRange(14, 15),
+             InRange(13, 14),
+             InRange(10, 11),
+             InRange(9, 10),
+             InRange(8, 9),
+             InRange(7, 8)
+         ]
+     );
+ }
+ 
+ // Á, 각, ก, 😀 all end in 0x81
+ // 🁀, ᘀ do not end in 0x81 but contain the byte
+ // ꁁ has 0x81 as its second and third bytes.
+ //
+ // The memchr-using implementation of next_match
+ // and next_match_back temporarily violate
+ // the property that the search is always on a unicode boundary,
+ // which is fine as long as this never reaches next() or next_back().
+ // So we test if next() is correct after each next_match() as well.
+ const STRESS: &str = "Áa🁀bÁꁁfg😁각กᘀ각aÁ각ꁁก😁a";
+ 
+ #[test]
+ fn test_stress_indices() {
+     // this isn't really a test, more of documentation on the indices of each character in the stresstest string
+ 
+     search_asserts!(
+         STRESS,
+         'x',
+         "Indices of characters in stress test",
+         [
+             next, next, next, next, next, next, next, next, next, next, next, next, next, next,
+             next, next, next, next, next, next, next
+         ],
+         [
+             Rejects(0, 2),   // Á
+             Rejects(2, 3),   // a
+             Rejects(3, 7),   // 🁀
+             Rejects(7, 8),   // b
+             Rejects(8, 10),  // Á
+             Rejects(10, 13), // ꁁ
+             Rejects(13, 14), // f
+             Rejects(14, 15), // g
+             Rejects(15, 19), // 😀
+             Rejects(19, 22), // 각
+             Rejects(22, 25), // ก
+             Rejects(25, 28), // ᘀ
+             Rejects(28, 31), // 각
+             Rejects(31, 32), // a
+             Rejects(32, 34), // Á
+             Rejects(34, 37), // 각
+             Rejects(37, 40), // ꁁ
+             Rejects(40, 43), // ก
+             Rejects(43, 47), // 😀
+             Rejects(47, 48), // a
+             Done
+         ]
+     );
+ }
+ 
+ #[test]
+ fn test_forward_search_shared_bytes() {
+     search_asserts!(
+         STRESS,
+         'Á',
+         "Forward search for two-byte Latin character",
+         [next_match, next_match, next_match, next_match],
+         [InRange(0, 2), InRange(8, 10), InRange(32, 34), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'Á',
+         "Forward search for two-byte Latin character; check if next() still works",
+         [next_match, next, next_match, next, next_match, next, next_match],
+         [
+             InRange(0, 2),
+             Rejects(2, 3),
+             InRange(8, 10),
+             Rejects(10, 13),
+             InRange(32, 34),
+             Rejects(34, 37),
+             Done
+         ]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '각',
+         "Forward search for three-byte Hangul character",
+         [next_match, next, next_match, next_match, next_match],
+         [InRange(19, 22), Rejects(22, 25), InRange(28, 31), InRange(34, 37), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '각',
+         "Forward search for three-byte Hangul character; check if next() still works",
+         [next_match, next, next_match, next, next_match, next, next_match],
+         [
+             InRange(19, 22),
+             Rejects(22, 25),
+             InRange(28, 31),
+             Rejects(31, 32),
+             InRange(34, 37),
+             Rejects(37, 40),
+             Done
+         ]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ก',
+         "Forward search for three-byte Thai character",
+         [next_match, next, next_match, next, next_match],
+         [InRange(22, 25), Rejects(25, 28), InRange(40, 43), Rejects(43, 47), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ก',
+         "Forward search for three-byte Thai character; check if next() still works",
+         [next_match, next, next_match, next, next_match],
+         [InRange(22, 25), Rejects(25, 28), InRange(40, 43), Rejects(43, 47), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '😁',
+         "Forward search for four-byte emoji",
+         [next_match, next, next_match, next, next_match],
+         [InRange(15, 19), Rejects(19, 22), InRange(43, 47), Rejects(47, 48), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '😁',
+         "Forward search for four-byte emoji; check if next() still works",
+         [next_match, next, next_match, next, next_match],
+         [InRange(15, 19), Rejects(19, 22), InRange(43, 47), Rejects(47, 48), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ꁁ',
+         "Forward search for three-byte Yi character with repeated bytes",
+         [next_match, next, next_match, next, next_match],
+         [InRange(10, 13), Rejects(13, 14), InRange(37, 40), Rejects(40, 43), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ꁁ',
+         "Forward search for three-byte Yi character with repeated bytes; check if next() still works",
+         [next_match, next, next_match, next, next_match],
+         [InRange(10, 13), Rejects(13, 14), InRange(37, 40), Rejects(40, 43), Done]
+     );
+ }
+ 
+ #[test]
+ fn test_reverse_search_shared_bytes() {
+     search_asserts!(
+         STRESS,
+         'Á',
+         "Reverse search for two-byte Latin character",
+         [next_match_back, next_match_back, next_match_back, next_match_back],
+         [InRange(32, 34), InRange(8, 10), InRange(0, 2), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'Á',
+         "Reverse search for two-byte Latin character; check if next_back() still works",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back, next_back],
+         [InRange(32, 34), Rejects(31, 32), InRange(8, 10), Rejects(7, 8), InRange(0, 2), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '각',
+         "Reverse search for three-byte Hangul character",
+         [next_match_back, next_back, next_match_back, next_match_back, next_match_back],
+         [InRange(34, 37), Rejects(32, 34), InRange(28, 31), InRange(19, 22), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '각',
+         "Reverse search for three-byte Hangul character; check if next_back() still works",
+         [
+             next_match_back,
+             next_back,
+             next_match_back,
+             next_back,
+             next_match_back,
+             next_back,
+             next_match_back
+         ],
+         [
+             InRange(34, 37),
+             Rejects(32, 34),
+             InRange(28, 31),
+             Rejects(25, 28),
+             InRange(19, 22),
+             Rejects(15, 19),
+             Done
+         ]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ก',
+         "Reverse search for three-byte Thai character",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back],
+         [InRange(40, 43), Rejects(37, 40), InRange(22, 25), Rejects(19, 22), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ก',
+         "Reverse search for three-byte Thai character; check if next_back() still works",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back],
+         [InRange(40, 43), Rejects(37, 40), InRange(22, 25), Rejects(19, 22), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '😁',
+         "Reverse search for four-byte emoji",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back],
+         [InRange(43, 47), Rejects(40, 43), InRange(15, 19), Rejects(14, 15), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         '😁',
+         "Reverse search for four-byte emoji; check if next_back() still works",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back],
+         [InRange(43, 47), Rejects(40, 43), InRange(15, 19), Rejects(14, 15), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ꁁ',
+         "Reverse search for three-byte Yi character with repeated bytes",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back],
+         [InRange(37, 40), Rejects(34, 37), InRange(10, 13), Rejects(8, 10), Done]
+     );
+ 
+     search_asserts!(
+         STRESS,
+         'ꁁ',
+         "Reverse search for three-byte Yi character with repeated bytes; check if next_back() still works",
+         [next_match_back, next_back, next_match_back, next_back, next_match_back],
+         [InRange(37, 40), Rejects(34, 37), InRange(10, 13), Rejects(8, 10), Done]
+     );
+ }
+ 
+ #[test]
+ fn double_ended_regression_test() {
+     // https://github.com/rust-lang/rust/issues/47175
+     // Ensures that double ended searching comes to a convergence
+     search_asserts!(
+         "abcdeabcdeabcde",
+         'a',
+         "alternating double ended search",
+         [next_match, next_match_back, next_match, next_match_back],
+         [InRange(0, 1), InRange(10, 11), InRange(5, 6), Done]
+     );
+     search_asserts!(
+         "abcdeabcdeabcde",
+         'a',
+         "triple double ended search for a",
+         [next_match, next_match_back, next_match_back, next_match_back],
+         [InRange(0, 1), InRange(10, 11), InRange(5, 6), Done]
+     );
+     search_asserts!(
+         "abcdeabcdeabcde",
+         'd',
+         "triple double ended search for d",
+         [next_match, next_match_back, next_match_back, next_match_back],
+         [InRange(3, 4), InRange(13, 14), InRange(8, 9), Done]
+     );
+     search_asserts!(
+         STRESS,
+         'Á',
+         "Double ended search for two-byte Latin character",
+         [next_match, next_match_back, next_match, next_match_back],
+         [InRange(0, 2), InRange(32, 34), InRange(8, 10), Done]
+     );
+     search_asserts!(
+         STRESS,
+         '각',
+         "Reverse double ended search for three-byte Hangul character",
+         [next_match_back, next_back, next_match, next, next_match_back, next_match],
+         [InRange(34, 37), Rejects(32, 34), InRange(19, 22), Rejects(22, 25), InRange(28, 31), Done]
+     );
+     search_asserts!(
+         STRESS,
+         'ก',
+         "Double ended search for three-byte Thai character",
+         [next_match, next_back, next, next_match_back, next_match],
+         [InRange(22, 25), Rejects(47, 48), Rejects(25, 28), InRange(40, 43), Done]
+     );
+     search_asserts!(
+         STRESS,
+         '😁',
+         "Double ended search for four-byte emoji",
+         [next_match_back, next, next_match, next_back, next_match],
+         [InRange(43, 47), Rejects(0, 2), InRange(15, 19), Rejects(40, 43), Done]
+     );
+     search_asserts!(
+         STRESS,
+         'ꁁ',
+         "Double ended search for three-byte Yi character with repeated bytes",
+         [next_match, next, next_match_back, next_back, next_match],
+         [InRange(10, 13), Rejects(13, 14), InRange(37, 40), Rejects(34, 37), Done]
+     );
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/pin.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/pin.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/pin.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/pin.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,31 ----
+ use core::pin::Pin;
+ 
+ #[test]
+ fn pin_const() {
+     // test that the methods of `Pin` are usable in a const context
+ 
+     const POINTER: &'static usize = &2;
+ 
+     const PINNED: Pin<&'static usize> = Pin::new(POINTER);
+     const PINNED_UNCHECKED: Pin<&'static usize> = unsafe { Pin::new_unchecked(POINTER) };
+     assert_eq!(PINNED_UNCHECKED, PINNED);
+ 
+     const INNER: &'static usize = Pin::into_inner(PINNED);
+     assert_eq!(INNER, POINTER);
+ 
+     const INNER_UNCHECKED: &'static usize = unsafe { Pin::into_inner_unchecked(PINNED) };
+     assert_eq!(INNER_UNCHECKED, POINTER);
+ 
+     const REF: &'static usize = PINNED.get_ref();
+     assert_eq!(REF, POINTER);
+ 
+     // Note: `pin_mut_const` tests that the methods of `Pin<&mut T>` are usable in a const context.
+     // A const fn is used because `&mut` is not (yet) usable in constants.
+     const fn pin_mut_const() {
+         let _ = Pin::new(&mut 2).into_ref();
+         let _ = Pin::new(&mut 2).get_mut();
+         let _ = unsafe { Pin::new(&mut 2).get_unchecked_mut() };
+     }
+ 
+     pin_mut_const();
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/ptr.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/ptr.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/ptr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/ptr.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,402 ----
+ use core::cell::RefCell;
+ use core::ptr::*;
+ 
+ #[test]
+ fn test_const_from_raw_parts() {
+     const SLICE: &[u8] = &[1, 2, 3, 4];
+     const FROM_RAW: &[u8] = unsafe { &*slice_from_raw_parts(SLICE.as_ptr(), SLICE.len()) };
+     assert_eq!(SLICE, FROM_RAW);
+ 
+     let slice = &[1, 2, 3, 4, 5];
+     let from_raw = unsafe { &*slice_from_raw_parts(slice.as_ptr(), 2) };
+     assert_eq!(&slice[..2], from_raw);
+ }
+ 
+ #[test]
+ fn test() {
+     unsafe {
+         struct Pair {
+             fst: isize,
+             snd: isize,
+         };
+         let mut p = Pair { fst: 10, snd: 20 };
+         let pptr: *mut Pair = &mut p;
+         let iptr: *mut isize = pptr as *mut isize;
+         assert_eq!(*iptr, 10);
+         *iptr = 30;
+         assert_eq!(*iptr, 30);
+         assert_eq!(p.fst, 30);
+ 
+         *pptr = Pair { fst: 50, snd: 60 };
+         assert_eq!(*iptr, 50);
+         assert_eq!(p.fst, 50);
+         assert_eq!(p.snd, 60);
+ 
+         let v0 = vec![32000u16, 32001u16, 32002u16];
+         let mut v1 = vec![0u16, 0u16, 0u16];
+ 
+         copy(v0.as_ptr().offset(1), v1.as_mut_ptr().offset(1), 1);
+         assert!((v1[0] == 0u16 && v1[1] == 32001u16 && v1[2] == 0u16));
+         copy(v0.as_ptr().offset(2), v1.as_mut_ptr(), 1);
+         assert!((v1[0] == 32002u16 && v1[1] == 32001u16 && v1[2] == 0u16));
+         copy(v0.as_ptr(), v1.as_mut_ptr().offset(2), 1);
+         assert!((v1[0] == 32002u16 && v1[1] == 32001u16 && v1[2] == 32000u16));
+     }
+ }
+ 
+ #[test]
+ fn test_is_null() {
+     let p: *const isize = null();
+     assert!(p.is_null());
+ 
+     let q = p.wrapping_offset(1);
+     assert!(!q.is_null());
+ 
+     let mp: *mut isize = null_mut();
+     assert!(mp.is_null());
+ 
+     let mq = mp.wrapping_offset(1);
+     assert!(!mq.is_null());
+ 
+     // Pointers to unsized types -- slices
+     let s: &mut [u8] = &mut [1, 2, 3];
+     let cs: *const [u8] = s;
+     assert!(!cs.is_null());
+ 
+     let ms: *mut [u8] = s;
+     assert!(!ms.is_null());
+ 
+     let cz: *const [u8] = &[];
+     assert!(!cz.is_null());
+ 
+     let mz: *mut [u8] = &mut [];
+     assert!(!mz.is_null());
+ 
+     let ncs: *const [u8] = null::<[u8; 3]>();
+     assert!(ncs.is_null());
+ 
+     let nms: *mut [u8] = null_mut::<[u8; 3]>();
+     assert!(nms.is_null());
+ 
+     // Pointers to unsized types -- trait objects
+     let ci: *const dyn ToString = &3;
+     assert!(!ci.is_null());
+ 
+     let mi: *mut dyn ToString = &mut 3;
+     assert!(!mi.is_null());
+ 
+     let nci: *const dyn ToString = null::<isize>();
+     assert!(nci.is_null());
+ 
+     let nmi: *mut dyn ToString = null_mut::<isize>();
+     assert!(nmi.is_null());
+ }
+ 
+ #[test]
+ fn test_as_ref() {
+     unsafe {
+         let p: *const isize = null();
+         assert_eq!(p.as_ref(), None);
+ 
+         let q: *const isize = &2;
+         assert_eq!(q.as_ref().unwrap(), &2);
+ 
+         let p: *mut isize = null_mut();
+         assert_eq!(p.as_ref(), None);
+ 
+         let q: *mut isize = &mut 2;
+         assert_eq!(q.as_ref().unwrap(), &2);
+ 
+         // Lifetime inference
+         let u = 2isize;
+         {
+             let p = &u as *const isize;
+             assert_eq!(p.as_ref().unwrap(), &2);
+         }
+ 
+         // Pointers to unsized types -- slices
+         let s: &mut [u8] = &mut [1, 2, 3];
+         let cs: *const [u8] = s;
+         assert_eq!(cs.as_ref(), Some(&*s));
+ 
+         let ms: *mut [u8] = s;
+         assert_eq!(ms.as_ref(), Some(&*s));
+ 
+         let cz: *const [u8] = &[];
+         assert_eq!(cz.as_ref(), Some(&[][..]));
+ 
+         let mz: *mut [u8] = &mut [];
+         assert_eq!(mz.as_ref(), Some(&[][..]));
+ 
+         let ncs: *const [u8] = null::<[u8; 3]>();
+         assert_eq!(ncs.as_ref(), None);
+ 
+         let nms: *mut [u8] = null_mut::<[u8; 3]>();
+         assert_eq!(nms.as_ref(), None);
+ 
+         // Pointers to unsized types -- trait objects
+         let ci: *const dyn ToString = &3;
+         assert!(ci.as_ref().is_some());
+ 
+         let mi: *mut dyn ToString = &mut 3;
+         assert!(mi.as_ref().is_some());
+ 
+         let nci: *const dyn ToString = null::<isize>();
+         assert!(nci.as_ref().is_none());
+ 
+         let nmi: *mut dyn ToString = null_mut::<isize>();
+         assert!(nmi.as_ref().is_none());
+     }
+ }
+ 
+ #[test]
+ fn test_as_mut() {
+     unsafe {
+         let p: *mut isize = null_mut();
+         assert!(p.as_mut() == None);
+ 
+         let q: *mut isize = &mut 2;
+         assert!(q.as_mut().unwrap() == &mut 2);
+ 
+         // Lifetime inference
+         let mut u = 2isize;
+         {
+             let p = &mut u as *mut isize;
+             assert!(p.as_mut().unwrap() == &mut 2);
+         }
+ 
+         // Pointers to unsized types -- slices
+         let s: &mut [u8] = &mut [1, 2, 3];
+         let ms: *mut [u8] = s;
+         assert_eq!(ms.as_mut(), Some(&mut [1, 2, 3][..]));
+ 
+         let mz: *mut [u8] = &mut [];
+         assert_eq!(mz.as_mut(), Some(&mut [][..]));
+ 
+         let nms: *mut [u8] = null_mut::<[u8; 3]>();
+         assert_eq!(nms.as_mut(), None);
+ 
+         // Pointers to unsized types -- trait objects
+         let mi: *mut dyn ToString = &mut 3;
+         assert!(mi.as_mut().is_some());
+ 
+         let nmi: *mut dyn ToString = null_mut::<isize>();
+         assert!(nmi.as_mut().is_none());
+     }
+ }
+ 
+ #[test]
+ fn test_ptr_addition() {
+     unsafe {
+         let xs = vec![5; 16];
+         let mut ptr = xs.as_ptr();
+         let end = ptr.offset(16);
+ 
+         while ptr < end {
+             assert_eq!(*ptr, 5);
+             ptr = ptr.offset(1);
+         }
+ 
+         let mut xs_mut = xs;
+         let mut m_ptr = xs_mut.as_mut_ptr();
+         let m_end = m_ptr.offset(16);
+ 
+         while m_ptr < m_end {
+             *m_ptr += 5;
+             m_ptr = m_ptr.offset(1);
+         }
+ 
+         assert!(xs_mut == vec![10; 16]);
+     }
+ }
+ 
+ #[test]
+ fn test_ptr_subtraction() {
+     unsafe {
+         let xs = vec![0, 1, 2, 3, 4, 5, 6, 7, 8, 9];
+         let mut idx = 9;
+         let ptr = xs.as_ptr();
+ 
+         while idx >= 0 {
+             assert_eq!(*(ptr.offset(idx as isize)), idx as isize);
+             idx = idx - 1;
+         }
+ 
+         let mut xs_mut = xs;
+         let m_start = xs_mut.as_mut_ptr();
+         let mut m_ptr = m_start.offset(9);
+ 
+         loop {
+             *m_ptr += *m_ptr;
+             if m_ptr == m_start {
+                 break;
+             }
+             m_ptr = m_ptr.offset(-1);
+         }
+ 
+         assert_eq!(xs_mut, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18]);
+     }
+ }
+ 
+ #[test]
+ fn test_set_memory() {
+     let mut xs = [0u8; 20];
+     let ptr = xs.as_mut_ptr();
+     unsafe {
+         write_bytes(ptr, 5u8, xs.len());
+     }
+     assert!(xs == [5u8; 20]);
+ }
+ 
+ #[test]
+ fn test_unsized_nonnull() {
+     let xs: &[i32] = &[1, 2, 3];
+     let ptr = unsafe { NonNull::new_unchecked(xs as *const [i32] as *mut [i32]) };
+     let ys = unsafe { ptr.as_ref() };
+     let zs: &[i32] = &[1, 2, 3];
+     assert!(ys == zs);
+ }
+ 
+ #[test]
+ #[allow(warnings)]
+ // Have a symbol for the test below. It doesn’t need to be an actual variadic function, match the
+ // ABI, or even point to an actual executable code, because the function itself is never invoked.
+ #[no_mangle]
+ pub fn test_variadic_fnptr() {
+     use core::hash::{Hash, SipHasher};
+     extern "C" {
+         fn test_variadic_fnptr(_: u64, ...) -> f64;
+     }
+     let p: unsafe extern "C" fn(u64, ...) -> f64 = test_variadic_fnptr;
+     let q = p.clone();
+     assert_eq!(p, q);
+     assert!(!(p < q));
+     let mut s = SipHasher::new();
+     assert_eq!(p.hash(&mut s), q.hash(&mut s));
+ }
+ 
+ #[test]
+ fn write_unaligned_drop() {
+     thread_local! {
+         static DROPS: RefCell<Vec<u32>> = RefCell::new(Vec::new());
+     }
+ 
+     struct Dropper(u32);
+ 
+     impl Drop for Dropper {
+         fn drop(&mut self) {
+             DROPS.with(|d| d.borrow_mut().push(self.0));
+         }
+     }
+ 
+     {
+         let c = Dropper(0);
+         let mut t = Dropper(1);
+         unsafe {
+             write_unaligned(&mut t, c);
+         }
+     }
+     DROPS.with(|d| assert_eq!(*d.borrow(), [0]));
+ }
+ 
+ #[test]
+ fn align_offset_zst() {
+     // For pointers of stride = 0, the pointer is already aligned or it cannot be aligned at
+     // all, because no amount of elements will align the pointer.
+     let mut p = 1;
+     while p < 1024 {
+         assert_eq!((p as *const ()).align_offset(p), 0);
+         if p != 1 {
+             assert_eq!(((p + 1) as *const ()).align_offset(p), !0);
+         }
+         p = (p + 1).next_power_of_two();
+     }
+ }
+ 
+ #[test]
+ fn align_offset_stride1() {
+     // For pointers of stride = 1, the pointer can always be aligned. The offset is equal to
+     // number of bytes.
+     let mut align = 1;
+     while align < 1024 {
+         for ptr in 1..2 * align {
+             let expected = ptr % align;
+             let offset = if expected == 0 { 0 } else { align - expected };
+             assert_eq!(
+                 (ptr as *const u8).align_offset(align),
+                 offset,
+                 "ptr = {}, align = {}, size = 1",
+                 ptr,
+                 align
+             );
+         }
+         align = (align + 1).next_power_of_two();
+     }
+ }
+ 
+ #[test]
+ fn align_offset_weird_strides() {
+     #[repr(packed)]
+     struct A3(u16, u8);
+     struct A4(u32);
+     #[repr(packed)]
+     struct A5(u32, u8);
+     #[repr(packed)]
+     struct A6(u32, u16);
+     #[repr(packed)]
+     struct A7(u32, u16, u8);
+     #[repr(packed)]
+     struct A8(u32, u32);
+     #[repr(packed)]
+     struct A9(u32, u32, u8);
+     #[repr(packed)]
+     struct A10(u32, u32, u16);
+ 
+     unsafe fn test_weird_stride<T>(ptr: *const T, align: usize) -> bool {
+         let numptr = ptr as usize;
+         let mut expected = usize::MAX;
+         // Naive but definitely correct way to find the *first* aligned element of stride::<T>.
+         for el in 0..align {
+             if (numptr + el * ::std::mem::size_of::<T>()) % align == 0 {
+                 expected = el;
+                 break;
+             }
+         }
+         let got = ptr.align_offset(align);
+         if got != expected {
+             eprintln!(
+                 "aligning {:p} (with stride of {}) to {}, expected {}, got {}",
+                 ptr,
+                 ::std::mem::size_of::<T>(),
+                 align,
+                 expected,
+                 got
+             );
+             return true;
+         }
+         return false;
+     }
+ 
+     // For pointers of stride != 1, we verify the algorithm against the naivest possible
+     // implementation
+     let mut align = 1;
+     let mut x = false;
+     // Miri is too slow
+     let limit = if cfg!(miri) { 32 } else { 1024 };
+     while align < limit {
+         for ptr in 1usize..4 * align {
+             unsafe {
+                 x |= test_weird_stride::<A3>(ptr as *const A3, align);
+                 x |= test_weird_stride::<A4>(ptr as *const A4, align);
+                 x |= test_weird_stride::<A5>(ptr as *const A5, align);
+                 x |= test_weird_stride::<A6>(ptr as *const A6, align);
+                 x |= test_weird_stride::<A7>(ptr as *const A7, align);
+                 x |= test_weird_stride::<A8>(ptr as *const A8, align);
+                 x |= test_weird_stride::<A9>(ptr as *const A9, align);
+                 x |= test_weird_stride::<A10>(ptr as *const A10, align);
+             }
+         }
+         align = (align + 1).next_power_of_two();
+     }
+     assert!(!x);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/result.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/result.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/result.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/result.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,322 ----
+ use core::ops::DerefMut;
+ use core::option::*;
+ 
+ fn op1() -> Result<isize, &'static str> {
+     Ok(666)
+ }
+ fn op2() -> Result<isize, &'static str> {
+     Err("sadface")
+ }
+ 
+ #[test]
+ fn test_and() {
+     assert_eq!(op1().and(Ok(667)).unwrap(), 667);
+     assert_eq!(op1().and(Err::<i32, &'static str>("bad")).unwrap_err(), "bad");
+ 
+     assert_eq!(op2().and(Ok(667)).unwrap_err(), "sadface");
+     assert_eq!(op2().and(Err::<i32, &'static str>("bad")).unwrap_err(), "sadface");
+ }
+ 
+ #[test]
+ fn test_and_then() {
+     assert_eq!(op1().and_then(|i| Ok::<isize, &'static str>(i + 1)).unwrap(), 667);
+     assert_eq!(op1().and_then(|_| Err::<isize, &'static str>("bad")).unwrap_err(), "bad");
+ 
+     assert_eq!(op2().and_then(|i| Ok::<isize, &'static str>(i + 1)).unwrap_err(), "sadface");
+     assert_eq!(op2().and_then(|_| Err::<isize, &'static str>("bad")).unwrap_err(), "sadface");
+ }
+ 
+ #[test]
+ fn test_or() {
+     assert_eq!(op1().or(Ok::<_, &'static str>(667)).unwrap(), 666);
+     assert_eq!(op1().or(Err("bad")).unwrap(), 666);
+ 
+     assert_eq!(op2().or(Ok::<_, &'static str>(667)).unwrap(), 667);
+     assert_eq!(op2().or(Err("bad")).unwrap_err(), "bad");
+ }
+ 
+ #[test]
+ fn test_or_else() {
+     assert_eq!(op1().or_else(|_| Ok::<isize, &'static str>(667)).unwrap(), 666);
+     assert_eq!(op1().or_else(|e| Err::<isize, &'static str>(e)).unwrap(), 666);
+ 
+     assert_eq!(op2().or_else(|_| Ok::<isize, &'static str>(667)).unwrap(), 667);
+     assert_eq!(op2().or_else(|e| Err::<isize, &'static str>(e)).unwrap_err(), "sadface");
+ }
+ 
+ #[test]
+ fn test_impl_map() {
+     assert!(Ok::<isize, isize>(1).map(|x| x + 1) == Ok(2));
+     assert!(Err::<isize, isize>(1).map(|x| x + 1) == Err(1));
+ }
+ 
+ #[test]
+ fn test_impl_map_err() {
+     assert!(Ok::<isize, isize>(1).map_err(|x| x + 1) == Ok(1));
+     assert!(Err::<isize, isize>(1).map_err(|x| x + 1) == Err(2));
+ }
+ 
+ #[test]
+ fn test_collect() {
+     let v: Result<Vec<isize>, ()> = (0..0).map(|_| Ok::<isize, ()>(0)).collect();
+     assert!(v == Ok(vec![]));
+ 
+     let v: Result<Vec<isize>, ()> = (0..3).map(|x| Ok::<isize, ()>(x)).collect();
+     assert!(v == Ok(vec![0, 1, 2]));
+ 
+     let v: Result<Vec<isize>, isize> = (0..3).map(|x| if x > 1 { Err(x) } else { Ok(x) }).collect();
+     assert!(v == Err(2));
+ 
+     // test that it does not take more elements than it needs
+     let mut functions: [Box<dyn Fn() -> Result<(), isize>>; 3] =
+         [box || Ok(()), box || Err(1), box || panic!()];
+ 
+     let v: Result<Vec<()>, isize> = functions.iter_mut().map(|f| (*f)()).collect();
+     assert!(v == Err(1));
+ }
+ 
+ #[test]
+ fn test_fmt_default() {
+     let ok: Result<isize, &'static str> = Ok(100);
+     let err: Result<isize, &'static str> = Err("Err");
+ 
+     let s = format!("{:?}", ok);
+     assert_eq!(s, "Ok(100)");
+     let s = format!("{:?}", err);
+     assert_eq!(s, "Err(\"Err\")");
+ }
+ 
+ #[test]
+ fn test_unwrap_or() {
+     let ok: Result<isize, &'static str> = Ok(100);
+     let ok_err: Result<isize, &'static str> = Err("Err");
+ 
+     assert_eq!(ok.unwrap_or(50), 100);
+     assert_eq!(ok_err.unwrap_or(50), 50);
+ }
+ 
+ #[test]
+ fn test_unwrap_or_else() {
+     fn handler(msg: &'static str) -> isize {
+         if msg == "I got this." { 50 } else { panic!("BadBad") }
+     }
+ 
+     let ok: Result<isize, &'static str> = Ok(100);
+     let ok_err: Result<isize, &'static str> = Err("I got this.");
+ 
+     assert_eq!(ok.unwrap_or_else(handler), 100);
+     assert_eq!(ok_err.unwrap_or_else(handler), 50);
+ }
+ 
+ #[test]
+ #[should_panic]
+ pub fn test_unwrap_or_else_panic() {
+     fn handler(msg: &'static str) -> isize {
+         if msg == "I got this." { 50 } else { panic!("BadBad") }
+     }
+ 
+     let bad_err: Result<isize, &'static str> = Err("Unrecoverable mess.");
+     let _: isize = bad_err.unwrap_or_else(handler);
+ }
+ 
+ #[test]
+ pub fn test_expect_ok() {
+     let ok: Result<isize, &'static str> = Ok(100);
+     assert_eq!(ok.expect("Unexpected error"), 100);
+ }
+ #[test]
+ #[should_panic(expected = "Got expected error: \"All good\"")]
+ pub fn test_expect_err() {
+     let err: Result<isize, &'static str> = Err("All good");
+     err.expect("Got expected error");
+ }
+ 
+ #[test]
+ pub fn test_expect_err_err() {
+     let ok: Result<&'static str, isize> = Err(100);
+     assert_eq!(ok.expect_err("Unexpected ok"), 100);
+ }
+ #[test]
+ #[should_panic(expected = "Got expected ok: \"All good\"")]
+ pub fn test_expect_err_ok() {
+     let err: Result<&'static str, isize> = Ok("All good");
+     err.expect_err("Got expected ok");
+ }
+ 
+ #[test]
+ pub fn test_iter() {
+     let ok: Result<isize, &'static str> = Ok(100);
+     let mut it = ok.iter();
+     assert_eq!(it.size_hint(), (1, Some(1)));
+     assert_eq!(it.next(), Some(&100));
+     assert_eq!(it.size_hint(), (0, Some(0)));
+     assert!(it.next().is_none());
+     assert_eq!((&ok).into_iter().next(), Some(&100));
+ 
+     let err: Result<isize, &'static str> = Err("error");
+     assert_eq!(err.iter().next(), None);
+ }
+ 
+ #[test]
+ pub fn test_iter_mut() {
+     let mut ok: Result<isize, &'static str> = Ok(100);
+     for loc in ok.iter_mut() {
+         *loc = 200;
+     }
+     assert_eq!(ok, Ok(200));
+     for loc in &mut ok {
+         *loc = 300;
+     }
+     assert_eq!(ok, Ok(300));
+ 
+     let mut err: Result<isize, &'static str> = Err("error");
+     for loc in err.iter_mut() {
+         *loc = 200;
+     }
+     assert_eq!(err, Err("error"));
+ }
+ 
+ #[test]
+ pub fn test_unwrap_or_default() {
+     assert_eq!(op1().unwrap_or_default(), 666);
+     assert_eq!(op2().unwrap_or_default(), 0);
+ }
+ 
+ #[test]
+ pub fn test_into_ok() {
+     fn infallible_op() -> Result<isize, !> {
+         Ok(666)
+     }
+ 
+     assert_eq!(infallible_op().into_ok(), 666);
+ 
+     enum MyNeverToken {}
+     impl From<MyNeverToken> for ! {
+         fn from(never: MyNeverToken) -> ! {
+             match never {}
+         }
+     }
+ 
+     fn infallible_op2() -> Result<isize, MyNeverToken> {
+         Ok(667)
+     }
+ 
+     assert_eq!(infallible_op2().into_ok(), 667);
+ }
+ 
+ #[test]
+ fn test_try() {
+     fn try_result_some() -> Option<u8> {
+         let val = Ok(1)?;
+         Some(val)
+     }
+     assert_eq!(try_result_some(), Some(1));
+ 
+     fn try_result_none() -> Option<u8> {
+         let val = Err(NoneError)?;
+         Some(val)
+     }
+     assert_eq!(try_result_none(), None);
+ 
+     fn try_result_ok() -> Result<u8, u8> {
+         let result: Result<u8, u8> = Ok(1);
+         let val = result?;
+         Ok(val)
+     }
+     assert_eq!(try_result_ok(), Ok(1));
+ 
+     fn try_result_err() -> Result<u8, u8> {
+         let result: Result<u8, u8> = Err(1);
+         let val = result?;
+         Ok(val)
+     }
+     assert_eq!(try_result_err(), Err(1));
+ }
+ 
+ #[test]
+ fn test_result_as_deref() {
+     // &Result<T: Deref, E>::Ok(T).as_deref() ->
+     //      Result<&T::Deref::Target, &E>::Ok(&*T)
+     let ref_ok = &Result::Ok::<&i32, u8>(&42);
+     let expected_result = Result::Ok::<&i32, &u8>(&42);
+     assert_eq!(ref_ok.as_deref(), expected_result);
+ 
+     let ref_ok = &Result::Ok::<String, u32>(String::from("a result"));
+     let expected_result = Result::Ok::<&str, &u32>("a result");
+     assert_eq!(ref_ok.as_deref(), expected_result);
+ 
+     let ref_ok = &Result::Ok::<Vec<i32>, u32>(vec![1, 2, 3, 4, 5]);
+     let expected_result = Result::Ok::<&[i32], &u32>([1, 2, 3, 4, 5].as_slice());
+     assert_eq!(ref_ok.as_deref(), expected_result);
+ 
+     // &Result<T: Deref, E>::Err(T).as_deref() ->
+     //      Result<&T::Deref::Target, &E>::Err(&*E)
+     let val = 41;
+     let ref_err = &Result::Err::<&u8, i32>(val);
+     let expected_result = Result::Err::<&u8, &i32>(&val);
+     assert_eq!(ref_err.as_deref(), expected_result);
+ 
+     let s = String::from("an error");
+     let ref_err = &Result::Err::<&u32, String>(s.clone());
+     let expected_result = Result::Err::<&u32, &String>(&s);
+     assert_eq!(ref_err.as_deref(), expected_result);
+ 
+     let v = vec![5, 4, 3, 2, 1];
+     let ref_err = &Result::Err::<&u32, Vec<i32>>(v.clone());
+     let expected_result = Result::Err::<&u32, &Vec<i32>>(&v);
+     assert_eq!(ref_err.as_deref(), expected_result);
+ }
+ 
+ #[test]
+ fn test_result_as_deref_mut() {
+     // &mut Result<T: DerefMut, E>::Ok(T).as_deref_mut() ->
+     //      Result<&mut T::DerefMut::Target, &mut E>::Ok(&mut *T)
+     let mut val = 42;
+     let mut expected_val = 42;
+     let mut_ok = &mut Result::Ok::<&mut i32, u8>(&mut val);
+     let expected_result = Result::Ok::<&mut i32, &mut u8>(&mut expected_val);
+     assert_eq!(mut_ok.as_deref_mut(), expected_result);
+ 
+     let mut expected_string = String::from("a result");
+     let mut_ok = &mut Result::Ok::<String, u32>(expected_string.clone());
+     let expected_result = Result::Ok::<&mut str, &mut u32>(expected_string.deref_mut());
+     assert_eq!(mut_ok.as_deref_mut(), expected_result);
+ 
+     let mut expected_vec = vec![1, 2, 3, 4, 5];
+     let mut_ok = &mut Result::Ok::<Vec<i32>, u32>(expected_vec.clone());
+     let expected_result = Result::Ok::<&mut [i32], &mut u32>(expected_vec.as_mut_slice());
+     assert_eq!(mut_ok.as_deref_mut(), expected_result);
+ 
+     // &mut Result<T: DerefMut, E>::Err(T).as_deref_mut() ->
+     //      Result<&mut T, &mut E>::Err(&mut *E)
+     let mut val = 41;
+     let mut_err = &mut Result::Err::<&mut u8, i32>(val);
+     let expected_result = Result::Err::<&mut u8, &mut i32>(&mut val);
+     assert_eq!(mut_err.as_deref_mut(), expected_result);
+ 
+     let mut expected_string = String::from("an error");
+     let mut_err = &mut Result::Err::<&mut u32, String>(expected_string.clone());
+     let expected_result = Result::Err::<&mut u32, &mut String>(&mut expected_string);
+     assert_eq!(mut_err.as_deref_mut(), expected_result);
+ 
+     let mut expected_vec = vec![5, 4, 3, 2, 1];
+     let mut_err = &mut Result::Err::<&mut u32, Vec<i32>>(expected_vec.clone());
+     let expected_result = Result::Err::<&mut u32, &mut Vec<i32>>(&mut expected_vec);
+     assert_eq!(mut_err.as_deref_mut(), expected_result);
+ }
+ 
+ #[test]
+ fn result_const() {
+     // test that the methods of `Result` are usable in a const context
+ 
+     const RESULT: Result<usize, bool> = Ok(32);
+ 
+     const REF: Result<&usize, &bool> = RESULT.as_ref();
+     assert_eq!(REF, Ok(&32));
+ 
+     const IS_OK: bool = RESULT.is_ok();
+     assert!(IS_OK);
+ 
+     const IS_ERR: bool = RESULT.is_err();
+     assert!(!IS_ERR)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/slice.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/slice.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/slice.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/slice.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2040 ----
+ use core::cell::Cell;
+ use core::result::Result::{Err, Ok};
+ 
+ #[test]
+ fn test_position() {
+     let b = [1, 2, 3, 5, 5];
+     assert_eq!(b.iter().position(|&v| v == 9), None);
+     assert_eq!(b.iter().position(|&v| v == 5), Some(3));
+     assert_eq!(b.iter().position(|&v| v == 3), Some(2));
+     assert_eq!(b.iter().position(|&v| v == 0), None);
+ }
+ 
+ #[test]
+ fn test_rposition() {
+     let b = [1, 2, 3, 5, 5];
+     assert_eq!(b.iter().rposition(|&v| v == 9), None);
+     assert_eq!(b.iter().rposition(|&v| v == 5), Some(4));
+     assert_eq!(b.iter().rposition(|&v| v == 3), Some(2));
+     assert_eq!(b.iter().rposition(|&v| v == 0), None);
+ }
+ 
+ #[test]
+ fn test_binary_search() {
+     let b: [i32; 0] = [];
+     assert_eq!(b.binary_search(&5), Err(0));
+ 
+     let b = [4];
+     assert_eq!(b.binary_search(&3), Err(0));
+     assert_eq!(b.binary_search(&4), Ok(0));
+     assert_eq!(b.binary_search(&5), Err(1));
+ 
+     let b = [1, 2, 4, 6, 8, 9];
+     assert_eq!(b.binary_search(&5), Err(3));
+     assert_eq!(b.binary_search(&6), Ok(3));
+     assert_eq!(b.binary_search(&7), Err(4));
+     assert_eq!(b.binary_search(&8), Ok(4));
+ 
+     let b = [1, 2, 4, 5, 6, 8];
+     assert_eq!(b.binary_search(&9), Err(6));
+ 
+     let b = [1, 2, 4, 6, 7, 8, 9];
+     assert_eq!(b.binary_search(&6), Ok(3));
+     assert_eq!(b.binary_search(&5), Err(3));
+     assert_eq!(b.binary_search(&8), Ok(5));
+ 
+     let b = [1, 2, 4, 5, 6, 8, 9];
+     assert_eq!(b.binary_search(&7), Err(5));
+     assert_eq!(b.binary_search(&0), Err(0));
+ 
+     let b = [1, 3, 3, 3, 7];
+     assert_eq!(b.binary_search(&0), Err(0));
+     assert_eq!(b.binary_search(&1), Ok(0));
+     assert_eq!(b.binary_search(&2), Err(1));
+     assert!(match b.binary_search(&3) {
+         Ok(1..=3) => true,
+         _ => false,
+     });
+     assert!(match b.binary_search(&3) {
+         Ok(1..=3) => true,
+         _ => false,
+     });
+     assert_eq!(b.binary_search(&4), Err(4));
+     assert_eq!(b.binary_search(&5), Err(4));
+     assert_eq!(b.binary_search(&6), Err(4));
+     assert_eq!(b.binary_search(&7), Ok(4));
+     assert_eq!(b.binary_search(&8), Err(5));
+ }
+ 
+ #[test]
+ // Test implementation specific behavior when finding equivalent elements.
+ // It is ok to break this test but when you do a crater run is highly advisable.
+ fn test_binary_search_implementation_details() {
+     let b = [1, 1, 2, 2, 3, 3, 3];
+     assert_eq!(b.binary_search(&1), Ok(1));
+     assert_eq!(b.binary_search(&2), Ok(3));
+     assert_eq!(b.binary_search(&3), Ok(6));
+     let b = [1, 1, 1, 1, 1, 3, 3, 3, 3];
+     assert_eq!(b.binary_search(&1), Ok(4));
+     assert_eq!(b.binary_search(&3), Ok(8));
+     let b = [1, 1, 1, 1, 3, 3, 3, 3, 3];
+     assert_eq!(b.binary_search(&1), Ok(3));
+     assert_eq!(b.binary_search(&3), Ok(8));
+ }
+ 
+ #[test]
+ fn test_partition_point() {
+     let b: [i32; 0] = [];
+     assert_eq!(b.partition_point(|&x| x < 5), 0);
+ 
+     let b = [4];
+     assert_eq!(b.partition_point(|&x| x < 3), 0);
+     assert_eq!(b.partition_point(|&x| x < 4), 0);
+     assert_eq!(b.partition_point(|&x| x < 5), 1);
+ 
+     let b = [1, 2, 4, 6, 8, 9];
+     assert_eq!(b.partition_point(|&x| x < 5), 3);
+     assert_eq!(b.partition_point(|&x| x < 6), 3);
+     assert_eq!(b.partition_point(|&x| x < 7), 4);
+     assert_eq!(b.partition_point(|&x| x < 8), 4);
+ 
+     let b = [1, 2, 4, 5, 6, 8];
+     assert_eq!(b.partition_point(|&x| x < 9), 6);
+ 
+     let b = [1, 2, 4, 6, 7, 8, 9];
+     assert_eq!(b.partition_point(|&x| x < 6), 3);
+     assert_eq!(b.partition_point(|&x| x < 5), 3);
+     assert_eq!(b.partition_point(|&x| x < 8), 5);
+ 
+     let b = [1, 2, 4, 5, 6, 8, 9];
+     assert_eq!(b.partition_point(|&x| x < 7), 5);
+     assert_eq!(b.partition_point(|&x| x < 0), 0);
+ 
+     let b = [1, 3, 3, 3, 7];
+     assert_eq!(b.partition_point(|&x| x < 0), 0);
+     assert_eq!(b.partition_point(|&x| x < 1), 0);
+     assert_eq!(b.partition_point(|&x| x < 2), 1);
+     assert_eq!(b.partition_point(|&x| x < 3), 1);
+     assert_eq!(b.partition_point(|&x| x < 4), 4);
+     assert_eq!(b.partition_point(|&x| x < 5), 4);
+     assert_eq!(b.partition_point(|&x| x < 6), 4);
+     assert_eq!(b.partition_point(|&x| x < 7), 4);
+     assert_eq!(b.partition_point(|&x| x < 8), 5);
+ }
+ 
+ #[test]
+ fn test_iterator_nth() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(v.iter().nth(i).unwrap(), &v[i]);
+     }
+     assert_eq!(v.iter().nth(v.len()), None);
+ 
+     let mut iter = v.iter();
+     assert_eq!(iter.nth(2).unwrap(), &v[2]);
+     assert_eq!(iter.nth(1).unwrap(), &v[4]);
+ }
+ 
+ #[test]
+ fn test_iterator_nth_back() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     for i in 0..v.len() {
+         assert_eq!(v.iter().nth_back(i).unwrap(), &v[v.len() - i - 1]);
+     }
+     assert_eq!(v.iter().nth_back(v.len()), None);
+ 
+     let mut iter = v.iter();
+     assert_eq!(iter.nth_back(2).unwrap(), &v[2]);
+     assert_eq!(iter.nth_back(1).unwrap(), &v[0]);
+ }
+ 
+ #[test]
+ fn test_iterator_last() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     assert_eq!(v.iter().last().unwrap(), &4);
+     assert_eq!(v[..1].iter().last().unwrap(), &0);
+ }
+ 
+ #[test]
+ fn test_iterator_count() {
+     let v: &[_] = &[0, 1, 2, 3, 4];
+     assert_eq!(v.iter().count(), 5);
+ 
+     let mut iter2 = v.iter();
+     iter2.next();
+     iter2.next();
+     assert_eq!(iter2.count(), 3);
+ }
+ 
+ #[test]
+ fn test_chunks_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.chunks(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.chunks(2);
+     assert_eq!(c2.count(), 3);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.chunks(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_chunks_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.chunks(3);
+     assert_eq!(c2.nth(1).unwrap(), &[3, 4]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_chunks_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+     assert_eq!(c.next(), None);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.chunks(3);
+     assert_eq!(c2.nth_back(1).unwrap(), &[0, 1, 2]);
+     assert_eq!(c2.next(), None);
+     assert_eq!(c2.next_back(), None);
+ 
+     let v3: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c3 = v3.chunks(10);
+     assert_eq!(c3.nth_back(0).unwrap(), &[0, 1, 2, 3, 4]);
+     assert_eq!(c3.next(), None);
+ 
+     let v4: &[i32] = &[0, 1, 2];
+     let mut c4 = v4.chunks(10);
+     assert_eq!(c4.nth_back(1_000_000_000usize), None);
+ }
+ 
+ #[test]
+ fn test_chunks_last() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.chunks(2);
+     assert_eq!(c.last().unwrap()[1], 5);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.chunks(2);
+     assert_eq!(c2.last().unwrap()[0], 4);
+ }
+ 
+ #[test]
+ fn test_chunks_zip() {
+     let v1: &[i32] = &[0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     let res = v1
+         .chunks(2)
+         .zip(v2.chunks(2))
+         .map(|(a, b)| a.iter().sum::<i32>() + b.iter().sum::<i32>())
+         .collect::<Vec<_>>();
+     assert_eq!(res, vec![14, 22, 14]);
+ }
+ 
+ #[test]
+ fn test_chunks_mut_count() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.chunks_mut(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.chunks_mut(2);
+     assert_eq!(c2.count(), 3);
+ 
+     let v3: &mut [i32] = &mut [];
+     let c3 = v3.chunks_mut(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_chunks_mut_nth() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks_mut(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c2 = v2.chunks_mut(3);
+     assert_eq!(c2.nth(1).unwrap(), &[3, 4]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_chunks_mut_nth_back() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks_mut(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+ 
+     let v1: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c1 = v1.chunks_mut(3);
+     assert_eq!(c1.nth_back(1).unwrap(), &[0, 1, 2]);
+     assert_eq!(c1.next(), None);
+ 
+     let v3: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c3 = v3.chunks_mut(10);
+     assert_eq!(c3.nth_back(0).unwrap(), &[0, 1, 2, 3, 4]);
+     assert_eq!(c3.next(), None);
+ 
+     let v4: &mut [i32] = &mut [0, 1, 2];
+     let mut c4 = v4.chunks_mut(10);
+     assert_eq!(c4.nth_back(1_000_000_000usize), None);
+ }
+ 
+ #[test]
+ fn test_chunks_mut_last() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.chunks_mut(2);
+     assert_eq!(c.last().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.chunks_mut(2);
+     assert_eq!(c2.last().unwrap(), &[4]);
+ }
+ 
+ #[test]
+ fn test_chunks_mut_zip() {
+     let v1: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     for (a, b) in v1.chunks_mut(2).zip(v2.chunks(2)) {
+         let sum = b.iter().sum::<i32>();
+         for v in a {
+             *v += sum;
+         }
+     }
+     assert_eq!(v1, [13, 14, 19, 20, 14]);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.chunks_exact(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.chunks_exact(2);
+     assert_eq!(c2.count(), 2);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.chunks_exact(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks_exact(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.chunks_exact(3);
+     assert_eq!(c2.nth(1).unwrap(), &[3, 4, 5]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks_exact(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+     assert_eq!(c.next(), None);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.chunks_exact(3);
+     assert_eq!(c2.nth_back(0).unwrap(), &[0, 1, 2]);
+     assert_eq!(c2.next(), None);
+     assert_eq!(c2.next_back(), None);
+ 
+     let v3: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c3 = v3.chunks_exact(10);
+     assert_eq!(c3.nth_back(0), None);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_last() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.chunks_exact(2);
+     assert_eq!(c.last().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.chunks_exact(2);
+     assert_eq!(c2.last().unwrap(), &[2, 3]);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_remainder() {
+     let v: &[i32] = &[0, 1, 2, 3, 4];
+     let c = v.chunks_exact(2);
+     assert_eq!(c.remainder(), &[4]);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_zip() {
+     let v1: &[i32] = &[0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     let res = v1
+         .chunks_exact(2)
+         .zip(v2.chunks_exact(2))
+         .map(|(a, b)| a.iter().sum::<i32>() + b.iter().sum::<i32>())
+         .collect::<Vec<_>>();
+     assert_eq!(res, vec![14, 22]);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_mut_count() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.chunks_exact_mut(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.chunks_exact_mut(2);
+     assert_eq!(c2.count(), 2);
+ 
+     let v3: &mut [i32] = &mut [];
+     let c3 = v3.chunks_exact_mut(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_mut_nth() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks_exact_mut(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.chunks_exact_mut(3);
+     assert_eq!(c2.nth(1).unwrap(), &[3, 4, 5]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_mut_nth_back() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.chunks_exact_mut(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+     assert_eq!(c.next(), None);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c2 = v2.chunks_exact_mut(3);
+     assert_eq!(c2.nth_back(0).unwrap(), &[0, 1, 2]);
+     assert_eq!(c2.next(), None);
+     assert_eq!(c2.next_back(), None);
+ 
+     let v3: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c3 = v3.chunks_exact_mut(10);
+     assert_eq!(c3.nth_back(0), None);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_mut_last() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.chunks_exact_mut(2);
+     assert_eq!(c.last().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.chunks_exact_mut(2);
+     assert_eq!(c2.last().unwrap(), &[2, 3]);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_mut_remainder() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c = v.chunks_exact_mut(2);
+     assert_eq!(c.into_remainder(), &[4]);
+ }
+ 
+ #[test]
+ fn test_chunks_exact_mut_zip() {
+     let v1: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     for (a, b) in v1.chunks_exact_mut(2).zip(v2.chunks_exact(2)) {
+         let sum = b.iter().sum::<i32>();
+         for v in a {
+             *v += sum;
+         }
+     }
+     assert_eq!(v1, [13, 14, 19, 20, 4]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_infer() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, -4];
+     let c = v.array_chunks();
+     for &[a, b, c] in c {
+         assert_eq!(a + b + c, 3);
+     }
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4, 5, 6];
+     let total = v2.array_chunks().map(|&[a, b]| a * b).sum::<i32>();
+     assert_eq!(total, 2 * 3 + 4 * 5);
+ }
+ 
+ #[test]
+ fn test_array_chunks_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.array_chunks::<3>();
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.array_chunks::<2>();
+     assert_eq!(c2.count(), 2);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.array_chunks::<2>();
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_array_chunks_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.array_chunks::<2>();
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.array_chunks::<3>();
+     assert_eq!(c2.nth(1).unwrap(), &[3, 4, 5]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_array_chunks_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.array_chunks::<2>();
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+     assert_eq!(c.next(), None);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.array_chunks::<3>();
+     assert_eq!(c2.nth_back(0).unwrap(), &[0, 1, 2]);
+     assert_eq!(c2.next(), None);
+     assert_eq!(c2.next_back(), None);
+ 
+     let v3: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c3 = v3.array_chunks::<10>();
+     assert_eq!(c3.nth_back(0), None);
+ }
+ 
+ #[test]
+ fn test_array_chunks_last() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.array_chunks::<2>();
+     assert_eq!(c.last().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.array_chunks::<2>();
+     assert_eq!(c2.last().unwrap(), &[2, 3]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_remainder() {
+     let v: &[i32] = &[0, 1, 2, 3, 4];
+     let c = v.array_chunks::<2>();
+     assert_eq!(c.remainder(), &[4]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_zip() {
+     let v1: &[i32] = &[0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     let res = v1
+         .array_chunks::<2>()
+         .zip(v2.array_chunks::<2>())
+         .map(|(a, b)| a.iter().sum::<i32>() + b.iter().sum::<i32>())
+         .collect::<Vec<_>>();
+     assert_eq!(res, vec![14, 22]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_infer() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5, 6];
+     for a in v.array_chunks_mut() {
+         let sum = a.iter().sum::<i32>();
+         *a = [sum; 3];
+     }
+     assert_eq!(v, &[3, 3, 3, 12, 12, 12, 6]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4, 5, 6];
+     v2.array_chunks_mut().for_each(|[a, b]| core::mem::swap(a, b));
+     assert_eq!(v2, &[1, 0, 3, 2, 5, 4, 6]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_count() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.array_chunks_mut::<3>();
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.array_chunks_mut::<2>();
+     assert_eq!(c2.count(), 2);
+ 
+     let v3: &mut [i32] = &mut [];
+     let c3 = v3.array_chunks_mut::<2>();
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_nth() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.array_chunks_mut::<2>();
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.array_chunks_mut::<3>();
+     assert_eq!(c2.nth(1).unwrap(), &[3, 4, 5]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_nth_back() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.array_chunks_mut::<2>();
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+     assert_eq!(c.next(), None);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c2 = v2.array_chunks_mut::<3>();
+     assert_eq!(c2.nth_back(0).unwrap(), &[0, 1, 2]);
+     assert_eq!(c2.next(), None);
+     assert_eq!(c2.next_back(), None);
+ 
+     let v3: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c3 = v3.array_chunks_mut::<10>();
+     assert_eq!(c3.nth_back(0), None);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_last() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.array_chunks_mut::<2>();
+     assert_eq!(c.last().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.array_chunks_mut::<2>();
+     assert_eq!(c2.last().unwrap(), &[2, 3]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_remainder() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c = v.array_chunks_mut::<2>();
+     assert_eq!(c.into_remainder(), &[4]);
+ }
+ 
+ #[test]
+ fn test_array_chunks_mut_zip() {
+     let v1: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     for (a, b) in v1.array_chunks_mut::<2>().zip(v2.array_chunks::<2>()) {
+         let sum = b.iter().sum::<i32>();
+         for v in a {
+             *v += sum;
+         }
+     }
+     assert_eq!(v1, [13, 14, 19, 20, 4]);
+ }
+ 
+ #[test]
+ fn test_array_windows_infer() {
+     let v: &[i32] = &[0, 1, 0, 1];
+     assert_eq!(v.array_windows::<2>().count(), 3);
+     let c = v.array_windows();
+     for &[a, b] in c {
+         assert_eq!(a + b, 1);
+     }
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4, 5, 6];
+     let total = v2.array_windows().map(|&[a, b, c]| a + b + c).sum::<i32>();
+     assert_eq!(total, 3 + 6 + 9 + 12 + 15);
+ }
+ 
+ #[test]
+ fn test_array_windows_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.array_windows::<3>();
+     assert_eq!(c.count(), 4);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.array_windows::<6>();
+     assert_eq!(c2.count(), 0);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.array_windows::<2>();
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_array_windows_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let snd = v.array_windows::<4>().nth(1);
+     assert_eq!(snd, Some(&[1, 2, 3, 4]));
+     let mut arr_windows = v.array_windows::<2>();
+     assert_ne!(arr_windows.nth(0), arr_windows.nth(0));
+     let last = v.array_windows::<3>().last();
+     assert_eq!(last, Some(&[3, 4, 5]));
+ }
+ 
+ #[test]
+ fn test_array_windows_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let snd = v.array_windows::<4>().nth_back(1);
+     assert_eq!(snd, Some(&[1, 2, 3, 4]));
+     let mut arr_windows = v.array_windows::<2>();
+     assert_ne!(arr_windows.nth_back(0), arr_windows.nth_back(0));
+ }
+ 
+ #[test]
+ fn test_rchunks_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.rchunks(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.rchunks(2);
+     assert_eq!(c2.count(), 3);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.rchunks(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_rchunks_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.rchunks(3);
+     assert_eq!(c2.nth(1).unwrap(), &[0, 1]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next_back().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.rchunks(3);
+     assert_eq!(c2.nth_back(1).unwrap(), &[2, 3, 4]);
+     assert_eq!(c2.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_last() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.rchunks(2);
+     assert_eq!(c.last().unwrap()[1], 1);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.rchunks(2);
+     assert_eq!(c2.last().unwrap()[0], 0);
+ }
+ 
+ #[test]
+ fn test_rchunks_zip() {
+     let v1: &[i32] = &[0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     let res = v1
+         .rchunks(2)
+         .zip(v2.rchunks(2))
+         .map(|(a, b)| a.iter().sum::<i32>() + b.iter().sum::<i32>())
+         .collect::<Vec<_>>();
+     assert_eq!(res, vec![26, 18, 6]);
+ }
+ 
+ #[test]
+ fn test_rchunks_mut_count() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.rchunks_mut(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.rchunks_mut(2);
+     assert_eq!(c2.count(), 3);
+ 
+     let v3: &mut [i32] = &mut [];
+     let c3 = v3.rchunks_mut(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_rchunks_mut_nth() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks_mut(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c2 = v2.rchunks_mut(3);
+     assert_eq!(c2.nth(1).unwrap(), &[0, 1]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_mut_nth_back() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks_mut(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next_back().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let mut c2 = v2.rchunks_mut(3);
+     assert_eq!(c2.nth_back(1).unwrap(), &[2, 3, 4]);
+     assert_eq!(c2.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_mut_last() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.rchunks_mut(2);
+     assert_eq!(c.last().unwrap(), &[0, 1]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.rchunks_mut(2);
+     assert_eq!(c2.last().unwrap(), &[0]);
+ }
+ 
+ #[test]
+ fn test_rchunks_mut_zip() {
+     let v1: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     for (a, b) in v1.rchunks_mut(2).zip(v2.rchunks(2)) {
+         let sum = b.iter().sum::<i32>();
+         for v in a {
+             *v += sum;
+         }
+     }
+     assert_eq!(v1, [6, 16, 17, 22, 23]);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.rchunks_exact(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.rchunks_exact(2);
+     assert_eq!(c2.count(), 2);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.rchunks_exact(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks_exact(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.rchunks_exact(3);
+     assert_eq!(c2.nth(1).unwrap(), &[1, 2, 3]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks_exact(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next_back().unwrap(), &[4, 5]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.rchunks_exact(3);
+     assert_eq!(c2.nth_back(1).unwrap(), &[4, 5, 6]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_last() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.rchunks_exact(2);
+     assert_eq!(c.last().unwrap(), &[0, 1]);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.rchunks_exact(2);
+     assert_eq!(c2.last().unwrap(), &[1, 2]);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_remainder() {
+     let v: &[i32] = &[0, 1, 2, 3, 4];
+     let c = v.rchunks_exact(2);
+     assert_eq!(c.remainder(), &[0]);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_zip() {
+     let v1: &[i32] = &[0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     let res = v1
+         .rchunks_exact(2)
+         .zip(v2.rchunks_exact(2))
+         .map(|(a, b)| a.iter().sum::<i32>() + b.iter().sum::<i32>())
+         .collect::<Vec<_>>();
+     assert_eq!(res, vec![26, 18]);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_mut_count() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.rchunks_exact_mut(3);
+     assert_eq!(c.count(), 2);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.rchunks_exact_mut(2);
+     assert_eq!(c2.count(), 2);
+ 
+     let v3: &mut [i32] = &mut [];
+     let c3 = v3.rchunks_exact_mut(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_mut_nth() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks_exact_mut(2);
+     assert_eq!(c.nth(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next().unwrap(), &[0, 1]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.rchunks_exact_mut(3);
+     assert_eq!(c2.nth(1).unwrap(), &[1, 2, 3]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_mut_nth_back() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let mut c = v.rchunks_exact_mut(2);
+     assert_eq!(c.nth_back(1).unwrap(), &[2, 3]);
+     assert_eq!(c.next_back().unwrap(), &[4, 5]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4, 5, 6];
+     let mut c2 = v2.rchunks_exact_mut(3);
+     assert_eq!(c2.nth_back(1).unwrap(), &[4, 5, 6]);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_mut_last() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4, 5];
+     let c = v.rchunks_exact_mut(2);
+     assert_eq!(c.last().unwrap(), &[0, 1]);
+ 
+     let v2: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c2 = v2.rchunks_exact_mut(2);
+     assert_eq!(c2.last().unwrap(), &[1, 2]);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_mut_remainder() {
+     let v: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let c = v.rchunks_exact_mut(2);
+     assert_eq!(c.into_remainder(), &[0]);
+ }
+ 
+ #[test]
+ fn test_rchunks_exact_mut_zip() {
+     let v1: &mut [i32] = &mut [0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     for (a, b) in v1.rchunks_exact_mut(2).zip(v2.rchunks_exact(2)) {
+         let sum = b.iter().sum::<i32>();
+         for v in a {
+             *v += sum;
+         }
+     }
+     assert_eq!(v1, [0, 16, 17, 22, 23]);
+ }
+ 
+ #[test]
+ fn test_windows_count() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.windows(3);
+     assert_eq!(c.count(), 4);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.windows(6);
+     assert_eq!(c2.count(), 0);
+ 
+     let v3: &[i32] = &[];
+     let c3 = v3.windows(2);
+     assert_eq!(c3.count(), 0);
+ }
+ 
+ #[test]
+ fn test_windows_nth() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.windows(2);
+     assert_eq!(c.nth(2).unwrap()[1], 3);
+     assert_eq!(c.next().unwrap()[0], 3);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.windows(4);
+     assert_eq!(c2.nth(1).unwrap()[1], 2);
+     assert_eq!(c2.next(), None);
+ }
+ 
+ #[test]
+ fn test_windows_nth_back() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let mut c = v.windows(2);
+     assert_eq!(c.nth_back(2).unwrap()[0], 2);
+     assert_eq!(c.next_back().unwrap()[1], 2);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let mut c2 = v2.windows(4);
+     assert_eq!(c2.nth_back(1).unwrap()[1], 1);
+     assert_eq!(c2.next_back(), None);
+ }
+ 
+ #[test]
+ fn test_windows_last() {
+     let v: &[i32] = &[0, 1, 2, 3, 4, 5];
+     let c = v.windows(2);
+     assert_eq!(c.last().unwrap()[1], 5);
+ 
+     let v2: &[i32] = &[0, 1, 2, 3, 4];
+     let c2 = v2.windows(2);
+     assert_eq!(c2.last().unwrap()[0], 3);
+ }
+ 
+ #[test]
+ fn test_windows_zip() {
+     let v1: &[i32] = &[0, 1, 2, 3, 4];
+     let v2: &[i32] = &[6, 7, 8, 9, 10];
+ 
+     let res = v1
+         .windows(2)
+         .zip(v2.windows(2))
+         .map(|(a, b)| a.iter().sum::<i32>() + b.iter().sum::<i32>())
+         .collect::<Vec<_>>();
+ 
+     assert_eq!(res, [14, 18, 22, 26]);
+ }
+ 
+ #[test]
+ #[allow(const_err)]
+ fn test_iter_ref_consistency() {
+     use std::fmt::Debug;
+ 
+     fn test<T: Copy + Debug + PartialEq>(x: T) {
+         let v: &[T] = &[x, x, x];
+         let v_ptrs: [*const T; 3] = match v {
+             [ref v1, ref v2, ref v3] => [v1 as *const _, v2 as *const _, v3 as *const _],
+             _ => unreachable!(),
+         };
+         let len = v.len();
+ 
+         // nth(i)
+         for i in 0..len {
+             assert_eq!(&v[i] as *const _, v_ptrs[i]); // check the v_ptrs array, just to be sure
+             let nth = v.iter().nth(i).unwrap();
+             assert_eq!(nth as *const _, v_ptrs[i]);
+         }
+         assert_eq!(v.iter().nth(len), None, "nth(len) should return None");
+ 
+         // stepping through with nth(0)
+         {
+             let mut it = v.iter();
+             for i in 0..len {
+                 let next = it.nth(0).unwrap();
+                 assert_eq!(next as *const _, v_ptrs[i]);
+             }
+             assert_eq!(it.nth(0), None);
+         }
+ 
+         // next()
+         {
+             let mut it = v.iter();
+             for i in 0..len {
+                 let remaining = len - i;
+                 assert_eq!(it.size_hint(), (remaining, Some(remaining)));
+ 
+                 let next = it.next().unwrap();
+                 assert_eq!(next as *const _, v_ptrs[i]);
+             }
+             assert_eq!(it.size_hint(), (0, Some(0)));
+             assert_eq!(it.next(), None, "The final call to next() should return None");
+         }
+ 
+         // next_back()
+         {
+             let mut it = v.iter();
+             for i in 0..len {
+                 let remaining = len - i;
+                 assert_eq!(it.size_hint(), (remaining, Some(remaining)));
+ 
+                 let prev = it.next_back().unwrap();
+                 assert_eq!(prev as *const _, v_ptrs[remaining - 1]);
+             }
+             assert_eq!(it.size_hint(), (0, Some(0)));
+             assert_eq!(it.next_back(), None, "The final call to next_back() should return None");
+         }
+     }
+ 
+     fn test_mut<T: Copy + Debug + PartialEq>(x: T) {
+         let v: &mut [T] = &mut [x, x, x];
+         let v_ptrs: [*mut T; 3] = match v {
+             [ref v1, ref v2, ref v3] => {
+                 [v1 as *const _ as *mut _, v2 as *const _ as *mut _, v3 as *const _ as *mut _]
+             }
+             _ => unreachable!(),
+         };
+         let len = v.len();
+ 
+         // nth(i)
+         for i in 0..len {
+             assert_eq!(&mut v[i] as *mut _, v_ptrs[i]); // check the v_ptrs array, just to be sure
+             let nth = v.iter_mut().nth(i).unwrap();
+             assert_eq!(nth as *mut _, v_ptrs[i]);
+         }
+         assert_eq!(v.iter().nth(len), None, "nth(len) should return None");
+ 
+         // stepping through with nth(0)
+         {
+             let mut it = v.iter();
+             for i in 0..len {
+                 let next = it.nth(0).unwrap();
+                 assert_eq!(next as *const _, v_ptrs[i]);
+             }
+             assert_eq!(it.nth(0), None);
+         }
+ 
+         // next()
+         {
+             let mut it = v.iter_mut();
+             for i in 0..len {
+                 let remaining = len - i;
+                 assert_eq!(it.size_hint(), (remaining, Some(remaining)));
+ 
+                 let next = it.next().unwrap();
+                 assert_eq!(next as *mut _, v_ptrs[i]);
+             }
+             assert_eq!(it.size_hint(), (0, Some(0)));
+             assert_eq!(it.next(), None, "The final call to next() should return None");
+         }
+ 
+         // next_back()
+         {
+             let mut it = v.iter_mut();
+             for i in 0..len {
+                 let remaining = len - i;
+                 assert_eq!(it.size_hint(), (remaining, Some(remaining)));
+ 
+                 let prev = it.next_back().unwrap();
+                 assert_eq!(prev as *mut _, v_ptrs[remaining - 1]);
+             }
+             assert_eq!(it.size_hint(), (0, Some(0)));
+             assert_eq!(it.next_back(), None, "The final call to next_back() should return None");
+         }
+     }
+ 
+     // Make sure iterators and slice patterns yield consistent addresses for various types,
+     // including ZSTs.
+     test(0u32);
+     test(());
+     test([0u32; 0]); // ZST with alignment > 0
+     test_mut(0u32);
+     test_mut(());
+     test_mut([0u32; 0]); // ZST with alignment > 0
+ }
+ 
+ // The current implementation of SliceIndex fails to handle methods
+ // orthogonally from range types; therefore, it is worth testing
+ // all of the indexing operations on each input.
+ mod slice_index {
+     // This checks all six indexing methods, given an input range that
+     // should succeed. (it is NOT suitable for testing invalid inputs)
+     macro_rules! assert_range_eq {
+         ($arr:expr, $range:expr, $expected:expr) => {
+             let mut arr = $arr;
+             let mut expected = $expected;
+             {
+                 let s: &[_] = &arr;
+                 let expected: &[_] = &expected;
+ 
+                 assert_eq!(&s[$range], expected, "(in assertion for: index)");
+                 assert_eq!(s.get($range), Some(expected), "(in assertion for: get)");
+                 unsafe {
+                     assert_eq!(
+                         s.get_unchecked($range),
+                         expected,
+                         "(in assertion for: get_unchecked)",
+                     );
+                 }
+             }
+             {
+                 let s: &mut [_] = &mut arr;
+                 let expected: &mut [_] = &mut expected;
+ 
+                 assert_eq!(&mut s[$range], expected, "(in assertion for: index_mut)",);
+                 assert_eq!(
+                     s.get_mut($range),
+                     Some(&mut expected[..]),
+                     "(in assertion for: get_mut)",
+                 );
+                 unsafe {
+                     assert_eq!(
+                         s.get_unchecked_mut($range),
+                         expected,
+                         "(in assertion for: get_unchecked_mut)",
+                     );
+                 }
+             }
+         };
+     }
+ 
+     // Make sure the macro can actually detect bugs,
+     // because if it can't, then what are we even doing here?
+     //
+     // (Be aware this only demonstrates the ability to detect bugs
+     //  in the FIRST method that panics, as the macro is not designed
+     //  to be used in `should_panic`)
+     #[test]
+     #[should_panic(expected = "out of range")]
+     fn assert_range_eq_can_fail_by_panic() {
+         assert_range_eq!([0, 1, 2], 0..5, [0, 1, 2]);
+     }
+ 
+     // (Be aware this only demonstrates the ability to detect bugs
+     //  in the FIRST method it calls, as the macro is not designed
+     //  to be used in `should_panic`)
+     #[test]
+     #[should_panic(expected = "==")]
+     fn assert_range_eq_can_fail_by_inequality() {
+         assert_range_eq!([0, 1, 2], 0..2, [0, 1, 2]);
+     }
+ 
+     // Test cases for bad index operations.
+     //
+     // This generates `should_panic` test cases for Index/IndexMut
+     // and `None` test cases for get/get_mut.
+     macro_rules! panic_cases {
+         ($(
+             // each test case needs a unique name to namespace the tests
+             in mod $case_name:ident {
+                 data: $data:expr;
+ 
+                 // optional:
+                 //
+                 // one or more similar inputs for which data[input] succeeds,
+                 // and the corresponding output as an array.  This helps validate
+                 // "critical points" where an input range straddles the boundary
+                 // between valid and invalid.
+                 // (such as the input `len..len`, which is just barely valid)
+                 $(
+                     good: data[$good:expr] == $output:expr;
+                 )*
+ 
+                 bad: data[$bad:expr];
+                 message: $expect_msg:expr;
+             }
+         )*) => {$(
+             mod $case_name {
+                 #[test]
+                 fn pass() {
+                     let mut v = $data;
+ 
+                     $( assert_range_eq!($data, $good, $output); )*
+ 
+                     {
+                         let v: &[_] = &v;
+                         assert_eq!(v.get($bad), None, "(in None assertion for get)");
+                     }
+ 
+                     {
+                         let v: &mut [_] = &mut v;
+                         assert_eq!(v.get_mut($bad), None, "(in None assertion for get_mut)");
+                     }
+                 }
+ 
+                 #[test]
+                 #[should_panic(expected = $expect_msg)]
+                 fn index_fail() {
+                     let v = $data;
+                     let v: &[_] = &v;
+                     let _v = &v[$bad];
+                 }
+ 
+                 #[test]
+                 #[should_panic(expected = $expect_msg)]
+                 fn index_mut_fail() {
+                     let mut v = $data;
+                     let v: &mut [_] = &mut v;
+                     let _v = &mut v[$bad];
+                 }
+             }
+         )*};
+     }
+ 
+     #[test]
+     fn simple() {
+         let v = [0, 1, 2, 3, 4, 5];
+ 
+         assert_range_eq!(v, .., [0, 1, 2, 3, 4, 5]);
+         assert_range_eq!(v, ..2, [0, 1]);
+         assert_range_eq!(v, ..=1, [0, 1]);
+         assert_range_eq!(v, 2.., [2, 3, 4, 5]);
+         assert_range_eq!(v, 1..4, [1, 2, 3]);
+         assert_range_eq!(v, 1..=3, [1, 2, 3]);
+     }
+ 
+     panic_cases! {
+         in mod rangefrom_len {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[6..] == [];
+             bad: data[7..];
+             message: "out of range";
+         }
+ 
+         in mod rangeto_len {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[..6] == [0, 1, 2, 3, 4, 5];
+             bad: data[..7];
+             message: "out of range";
+         }
+ 
+         in mod rangetoinclusive_len {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[..=5] == [0, 1, 2, 3, 4, 5];
+             bad: data[..=6];
+             message: "out of range";
+         }
+ 
+         in mod rangeinclusive_len {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[0..=5] == [0, 1, 2, 3, 4, 5];
+             bad: data[0..=6];
+             message: "out of range";
+         }
+ 
+         in mod range_len_len {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[6..6] == [];
+             bad: data[7..7];
+             message: "out of range";
+         }
+ 
+         in mod rangeinclusive_len_len {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[6..=5] == [];
+             bad: data[7..=6];
+             message: "out of range";
+         }
+     }
+ 
+     panic_cases! {
+         in mod rangeinclusive_exhausted {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[0..=5] == [0, 1, 2, 3, 4, 5];
+             good: data[{
+                 let mut iter = 0..=5;
+                 iter.by_ref().count(); // exhaust it
+                 iter
+             }] == [];
+ 
+             // 0..=6 is out of range before exhaustion, so it
+             // stands to reason that it still would be after.
+             bad: data[{
+                 let mut iter = 0..=6;
+                 iter.by_ref().count(); // exhaust it
+                 iter
+             }];
+             message: "out of range";
+         }
+     }
+ 
+     panic_cases! {
+         in mod range_neg_width {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[4..4] == [];
+             bad: data[4..3];
+             message: "but ends at";
+         }
+ 
+         in mod rangeinclusive_neg_width {
+             data: [0, 1, 2, 3, 4, 5];
+ 
+             good: data[4..=3] == [];
+             bad: data[4..=2];
+             message: "but ends at";
+         }
+     }
+ 
+     panic_cases! {
+         in mod rangeinclusive_overflow {
+             data: [0, 1];
+ 
+             // note: using 0 specifically ensures that the result of overflowing is 0..0,
+             //       so that `get` doesn't simply return None for the wrong reason.
+             bad: data[0 ..= usize::MAX];
+             message: "maximum usize";
+         }
+ 
+         in mod rangetoinclusive_overflow {
+             data: [0, 1];
+ 
+             bad: data[..= usize::MAX];
+             message: "maximum usize";
+         }
+     } // panic_cases!
+ }
+ 
+ #[test]
+ fn test_find_rfind() {
+     let v = [0, 1, 2, 3, 4, 5];
+     let mut iter = v.iter();
+     let mut i = v.len();
+     while let Some(&elt) = iter.rfind(|_| true) {
+         i -= 1;
+         assert_eq!(elt, v[i]);
+     }
+     assert_eq!(i, 0);
+     assert_eq!(v.iter().rfind(|&&x| x <= 3), Some(&3));
+ }
+ 
+ #[test]
+ fn test_iter_folds() {
+     let a = [1, 2, 3, 4, 5]; // len>4 so the unroll is used
+     assert_eq!(a.iter().fold(0, |acc, &x| 2 * acc + x), 57);
+     assert_eq!(a.iter().rfold(0, |acc, &x| 2 * acc + x), 129);
+     let fold = |acc: i32, &x| acc.checked_mul(2)?.checked_add(x);
+     assert_eq!(a.iter().try_fold(0, &fold), Some(57));
+     assert_eq!(a.iter().try_rfold(0, &fold), Some(129));
+ 
+     // short-circuiting try_fold, through other methods
+     let a = [0, 1, 2, 3, 5, 5, 5, 7, 8, 9];
+     let mut iter = a.iter();
+     assert_eq!(iter.position(|&x| x == 3), Some(3));
+     assert_eq!(iter.rfind(|&&x| x == 5), Some(&5));
+     assert_eq!(iter.len(), 2);
+ }
+ 
+ #[test]
+ fn test_rotate_left() {
+     const N: usize = 600;
+     let a: &mut [_] = &mut [0; N];
+     for i in 0..N {
+         a[i] = i;
+     }
+ 
+     a.rotate_left(42);
+     let k = N - 42;
+ 
+     for i in 0..N {
+         assert_eq!(a[(i + k) % N], i);
+     }
+ }
+ 
+ #[test]
+ fn test_rotate_right() {
+     const N: usize = 600;
+     let a: &mut [_] = &mut [0; N];
+     for i in 0..N {
+         a[i] = i;
+     }
+ 
+     a.rotate_right(42);
+ 
+     for i in 0..N {
+         assert_eq!(a[(i + 42) % N], i);
+     }
+ }
+ 
+ #[test]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn brute_force_rotate_test_0() {
+     // In case of edge cases involving multiple algorithms
+     let n = 300;
+     for len in 0..n {
+         for s in 0..len {
+             let mut v = Vec::with_capacity(len);
+             for i in 0..len {
+                 v.push(i);
+             }
+             v[..].rotate_right(s);
+             for i in 0..v.len() {
+                 assert_eq!(v[i], v.len().wrapping_add(i.wrapping_sub(s)) % v.len());
+             }
+         }
+     }
+ }
+ 
+ #[test]
+ fn brute_force_rotate_test_1() {
+     // `ptr_rotate` covers so many kinds of pointer usage, that this is just a good test for
+     // pointers in general. This uses a `[usize; 4]` to hit all algorithms without overwhelming miri
+     let n = 30;
+     for len in 0..n {
+         for s in 0..len {
+             let mut v: Vec<[usize; 4]> = Vec::with_capacity(len);
+             for i in 0..len {
+                 v.push([i, 0, 0, 0]);
+             }
+             v[..].rotate_right(s);
+             for i in 0..v.len() {
+                 assert_eq!(v[i][0], v.len().wrapping_add(i.wrapping_sub(s)) % v.len());
+             }
+         }
+     }
+ }
+ 
+ #[test]
+ #[cfg(not(target_arch = "wasm32"))]
+ fn sort_unstable() {
+     use core::cmp::Ordering::{Equal, Greater, Less};
+     use core::slice::heapsort;
+     use rand::{rngs::StdRng, seq::SliceRandom, Rng, SeedableRng};
+ 
+     // Miri is too slow (but still need to `chain` to make the types match)
+     let lens = if cfg!(miri) { (2..20).chain(0..0) } else { (2..25).chain(500..510) };
+     let rounds = if cfg!(miri) { 1 } else { 100 };
+ 
+     let mut v = [0; 600];
+     let mut tmp = [0; 600];
+     let mut rng = StdRng::from_entropy();
+ 
+     for len in lens {
+         let v = &mut v[0..len];
+         let tmp = &mut tmp[0..len];
+ 
+         for &modulus in &[5, 10, 100, 1000] {
+             for _ in 0..rounds {
+                 for i in 0..len {
+                     v[i] = rng.gen::<i32>() % modulus;
+                 }
+ 
+                 // Sort in default order.
+                 tmp.copy_from_slice(v);
+                 tmp.sort_unstable();
+                 assert!(tmp.windows(2).all(|w| w[0] <= w[1]));
+ 
+                 // Sort in ascending order.
+                 tmp.copy_from_slice(v);
+                 tmp.sort_unstable_by(|a, b| a.cmp(b));
+                 assert!(tmp.windows(2).all(|w| w[0] <= w[1]));
+ 
+                 // Sort in descending order.
+                 tmp.copy_from_slice(v);
+                 tmp.sort_unstable_by(|a, b| b.cmp(a));
+                 assert!(tmp.windows(2).all(|w| w[0] >= w[1]));
+ 
+                 // Test heapsort using `<` operator.
+                 tmp.copy_from_slice(v);
+                 heapsort(tmp, |a, b| a < b);
+                 assert!(tmp.windows(2).all(|w| w[0] <= w[1]));
+ 
+                 // Test heapsort using `>` operator.
+                 tmp.copy_from_slice(v);
+                 heapsort(tmp, |a, b| a > b);
+                 assert!(tmp.windows(2).all(|w| w[0] >= w[1]));
+             }
+         }
+     }
+ 
+     // Sort using a completely random comparison function.
+     // This will reorder the elements *somehow*, but won't panic.
+     for i in 0..v.len() {
+         v[i] = i as i32;
+     }
+     v.sort_unstable_by(|_, _| *[Less, Equal, Greater].choose(&mut rng).unwrap());
+     v.sort_unstable();
+     for i in 0..v.len() {
+         assert_eq!(v[i], i as i32);
+     }
+ 
+     // Should not panic.
+     [0i32; 0].sort_unstable();
+     [(); 10].sort_unstable();
+     [(); 100].sort_unstable();
+ 
+     let mut v = [0xDEADBEEFu64];
+     v.sort_unstable();
+     assert!(v == [0xDEADBEEF]);
+ }
+ 
+ #[test]
+ #[cfg(not(target_arch = "wasm32"))]
+ #[cfg_attr(miri, ignore)] // Miri is too slow
+ fn select_nth_unstable() {
+     use core::cmp::Ordering::{Equal, Greater, Less};
+     use rand::rngs::StdRng;
+     use rand::seq::SliceRandom;
+     use rand::{Rng, SeedableRng};
+ 
+     let mut rng = StdRng::from_entropy();
+ 
+     for len in (2..21).chain(500..501) {
+         let mut orig = vec![0; len];
+ 
+         for &modulus in &[5, 10, 1000] {
+             for _ in 0..10 {
+                 for i in 0..len {
+                     orig[i] = rng.gen::<i32>() % modulus;
+                 }
+ 
+                 let v_sorted = {
+                     let mut v = orig.clone();
+                     v.sort();
+                     v
+                 };
+ 
+                 // Sort in default order.
+                 for pivot in 0..len {
+                     let mut v = orig.clone();
+                     v.select_nth_unstable(pivot);
+ 
+                     assert_eq!(v_sorted[pivot], v[pivot]);
+                     for i in 0..pivot {
+                         for j in pivot..len {
+                             assert!(v[i] <= v[j]);
+                         }
+                     }
+                 }
+ 
+                 // Sort in ascending order.
+                 for pivot in 0..len {
+                     let mut v = orig.clone();
+                     let (left, pivot, right) = v.select_nth_unstable_by(pivot, |a, b| a.cmp(b));
+ 
+                     assert_eq!(left.len() + right.len(), len - 1);
+ 
+                     for l in left {
+                         assert!(l <= pivot);
+                         for r in right.iter_mut() {
+                             assert!(l <= r);
+                             assert!(pivot <= r);
+                         }
+                     }
+                 }
+ 
+                 // Sort in descending order.
+                 let sort_descending_comparator = |a: &i32, b: &i32| b.cmp(a);
+                 let v_sorted_descending = {
+                     let mut v = orig.clone();
+                     v.sort_by(sort_descending_comparator);
+                     v
+                 };
+ 
+                 for pivot in 0..len {
+                     let mut v = orig.clone();
+                     v.select_nth_unstable_by(pivot, sort_descending_comparator);
+ 
+                     assert_eq!(v_sorted_descending[pivot], v[pivot]);
+                     for i in 0..pivot {
+                         for j in pivot..len {
+                             assert!(v[j] <= v[i]);
+                         }
+                     }
+                 }
+             }
+         }
+     }
+ 
+     // Sort at index using a completely random comparison function.
+     // This will reorder the elements *somehow*, but won't panic.
+     let mut v = [0; 500];
+     for i in 0..v.len() {
+         v[i] = i as i32;
+     }
+ 
+     for pivot in 0..v.len() {
+         v.select_nth_unstable_by(pivot, |_, _| *[Less, Equal, Greater].choose(&mut rng).unwrap());
+         v.sort();
+         for i in 0..v.len() {
+             assert_eq!(v[i], i as i32);
+         }
+     }
+ 
+     // Should not panic.
+     [(); 10].select_nth_unstable(0);
+     [(); 10].select_nth_unstable(5);
+     [(); 10].select_nth_unstable(9);
+     [(); 100].select_nth_unstable(0);
+     [(); 100].select_nth_unstable(50);
+     [(); 100].select_nth_unstable(99);
+ 
+     let mut v = [0xDEADBEEFu64];
+     v.select_nth_unstable(0);
+     assert!(v == [0xDEADBEEF]);
+ }
+ 
+ #[test]
+ #[should_panic(expected = "index 0 greater than length of slice")]
+ fn select_nth_unstable_zero_length() {
+     [0i32; 0].select_nth_unstable(0);
+ }
+ 
+ #[test]
+ #[should_panic(expected = "index 20 greater than length of slice")]
+ fn select_nth_unstable_past_length() {
+     [0i32; 10].select_nth_unstable(20);
+ }
+ 
+ pub mod memchr {
+     use core::slice::memchr::{memchr, memrchr};
+ 
+     // test fallback implementations on all platforms
+     #[test]
+     fn matches_one() {
+         assert_eq!(Some(0), memchr(b'a', b"a"));
+     }
+ 
+     #[test]
+     fn matches_begin() {
+         assert_eq!(Some(0), memchr(b'a', b"aaaa"));
+     }
+ 
+     #[test]
+     fn matches_end() {
+         assert_eq!(Some(4), memchr(b'z', b"aaaaz"));
+     }
+ 
+     #[test]
+     fn matches_nul() {
+         assert_eq!(Some(4), memchr(b'\x00', b"aaaa\x00"));
+     }
+ 
+     #[test]
+     fn matches_past_nul() {
+         assert_eq!(Some(5), memchr(b'z', b"aaaa\x00z"));
+     }
+ 
+     #[test]
+     fn no_match_empty() {
+         assert_eq!(None, memchr(b'a', b""));
+     }
+ 
+     #[test]
+     fn no_match() {
+         assert_eq!(None, memchr(b'a', b"xyz"));
+     }
+ 
+     #[test]
+     fn matches_one_reversed() {
+         assert_eq!(Some(0), memrchr(b'a', b"a"));
+     }
+ 
+     #[test]
+     fn matches_begin_reversed() {
+         assert_eq!(Some(3), memrchr(b'a', b"aaaa"));
+     }
+ 
+     #[test]
+     fn matches_end_reversed() {
+         assert_eq!(Some(0), memrchr(b'z', b"zaaaa"));
+     }
+ 
+     #[test]
+     fn matches_nul_reversed() {
+         assert_eq!(Some(4), memrchr(b'\x00', b"aaaa\x00"));
+     }
+ 
+     #[test]
+     fn matches_past_nul_reversed() {
+         assert_eq!(Some(0), memrchr(b'z', b"z\x00aaaa"));
+     }
+ 
+     #[test]
+     fn no_match_empty_reversed() {
+         assert_eq!(None, memrchr(b'a', b""));
+     }
+ 
+     #[test]
+     fn no_match_reversed() {
+         assert_eq!(None, memrchr(b'a', b"xyz"));
+     }
+ 
+     #[test]
+     fn each_alignment_reversed() {
+         let mut data = [1u8; 64];
+         let needle = 2;
+         let pos = 40;
+         data[pos] = needle;
+         for start in 0..16 {
+             assert_eq!(Some(pos - start), memrchr(needle, &data[start..]));
+         }
+     }
+ }
+ 
+ #[test]
+ fn test_align_to_simple() {
+     let bytes = [1u8, 2, 3, 4, 5, 6, 7];
+     let (prefix, aligned, suffix) = unsafe { bytes.align_to::<u16>() };
+     assert_eq!(aligned.len(), 3);
+     assert!(prefix == [1] || suffix == [7]);
+     let expect1 = [1 << 8 | 2, 3 << 8 | 4, 5 << 8 | 6];
+     let expect2 = [1 | 2 << 8, 3 | 4 << 8, 5 | 6 << 8];
+     let expect3 = [2 << 8 | 3, 4 << 8 | 5, 6 << 8 | 7];
+     let expect4 = [2 | 3 << 8, 4 | 5 << 8, 6 | 7 << 8];
+     assert!(
+         aligned == expect1 || aligned == expect2 || aligned == expect3 || aligned == expect4,
+         "aligned={:?} expected={:?} || {:?} || {:?} || {:?}",
+         aligned,
+         expect1,
+         expect2,
+         expect3,
+         expect4
+     );
+ }
+ 
+ #[test]
+ fn test_align_to_zst() {
+     let bytes = [1, 2, 3, 4, 5, 6, 7];
+     let (prefix, aligned, suffix) = unsafe { bytes.align_to::<()>() };
+     assert_eq!(aligned.len(), 0);
+     assert!(prefix == [1, 2, 3, 4, 5, 6, 7] || suffix == [1, 2, 3, 4, 5, 6, 7]);
+ }
+ 
+ #[test]
+ fn test_align_to_non_trivial() {
+     #[repr(align(8))]
+     struct U64(u64, u64);
+     #[repr(align(8))]
+     struct U64U64U32(u64, u64, u32);
+     let data = [
+         U64(1, 2),
+         U64(3, 4),
+         U64(5, 6),
+         U64(7, 8),
+         U64(9, 10),
+         U64(11, 12),
+         U64(13, 14),
+         U64(15, 16),
+     ];
+     let (prefix, aligned, suffix) = unsafe { data.align_to::<U64U64U32>() };
+     assert_eq!(aligned.len(), 4);
+     assert_eq!(prefix.len() + suffix.len(), 2);
+ }
+ 
+ #[test]
+ fn test_align_to_empty_mid() {
+     use core::mem;
+ 
+     // Make sure that we do not create empty unaligned slices for the mid part, even when the
+     // overall slice is too short to contain an aligned address.
+     let bytes = [1, 2, 3, 4, 5, 6, 7];
+     type Chunk = u32;
+     for offset in 0..4 {
+         let (_, mid, _) = unsafe { bytes[offset..offset + 1].align_to::<Chunk>() };
+         assert_eq!(mid.as_ptr() as usize % mem::align_of::<Chunk>(), 0);
+     }
+ }
+ 
+ #[test]
+ fn test_align_to_mut_aliasing() {
+     let mut val = [1u8, 2, 3, 4, 5];
+     // `align_to_mut` used to create `mid` in a way that there was some intermediate
+     // incorrect aliasing, invalidating the resulting `mid` slice.
+     let (begin, mid, end) = unsafe { val.align_to_mut::<[u8; 2]>() };
+     assert!(begin.len() == 0);
+     assert!(end.len() == 1);
+     mid[0] = mid[1];
+     assert_eq!(val, [3, 4, 3, 4, 5])
+ }
+ 
+ #[test]
+ fn test_slice_partition_dedup_by() {
+     let mut slice: [i32; 9] = [1, -1, 2, 3, 1, -5, 5, -2, 2];
+ 
+     let (dedup, duplicates) = slice.partition_dedup_by(|a, b| a.abs() == b.abs());
+ 
+     assert_eq!(dedup, [1, 2, 3, 1, -5, -2]);
+     assert_eq!(duplicates, [5, -1, 2]);
+ }
+ 
+ #[test]
+ fn test_slice_partition_dedup_empty() {
+     let mut slice: [i32; 0] = [];
+ 
+     let (dedup, duplicates) = slice.partition_dedup();
+ 
+     assert_eq!(dedup, []);
+     assert_eq!(duplicates, []);
+ }
+ 
+ #[test]
+ fn test_slice_partition_dedup_one() {
+     let mut slice = [12];
+ 
+     let (dedup, duplicates) = slice.partition_dedup();
+ 
+     assert_eq!(dedup, [12]);
+     assert_eq!(duplicates, []);
+ }
+ 
+ #[test]
+ fn test_slice_partition_dedup_multiple_ident() {
+     let mut slice = [12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11];
+ 
+     let (dedup, duplicates) = slice.partition_dedup();
+ 
+     assert_eq!(dedup, [12, 11]);
+     assert_eq!(duplicates, [12, 12, 12, 12, 11, 11, 11, 11, 11]);
+ }
+ 
+ #[test]
+ fn test_slice_partition_dedup_partialeq() {
+     #[derive(Debug)]
+     struct Foo(i32, i32);
+ 
+     impl PartialEq for Foo {
+         fn eq(&self, other: &Foo) -> bool {
+             self.0 == other.0
+         }
+     }
+ 
+     let mut slice = [Foo(0, 1), Foo(0, 5), Foo(1, 7), Foo(1, 9)];
+ 
+     let (dedup, duplicates) = slice.partition_dedup();
+ 
+     assert_eq!(dedup, [Foo(0, 1), Foo(1, 7)]);
+     assert_eq!(duplicates, [Foo(0, 5), Foo(1, 9)]);
+ }
+ 
+ #[test]
+ fn test_copy_within() {
+     // Start to end, with a RangeTo.
+     let mut bytes = *b"Hello, World!";
+     bytes.copy_within(..3, 10);
+     assert_eq!(&bytes, b"Hello, WorHel");
+ 
+     // End to start, with a RangeFrom.
+     let mut bytes = *b"Hello, World!";
+     bytes.copy_within(10.., 0);
+     assert_eq!(&bytes, b"ld!lo, World!");
+ 
+     // Overlapping, with a RangeInclusive.
+     let mut bytes = *b"Hello, World!";
+     bytes.copy_within(0..=11, 1);
+     assert_eq!(&bytes, b"HHello, World");
+ 
+     // Whole slice, with a RangeFull.
+     let mut bytes = *b"Hello, World!";
+     bytes.copy_within(.., 0);
+     assert_eq!(&bytes, b"Hello, World!");
+ 
+     // Ensure that copying at the end of slice won't cause UB.
+     let mut bytes = *b"Hello, World!";
+     bytes.copy_within(13..13, 5);
+     assert_eq!(&bytes, b"Hello, World!");
+     bytes.copy_within(5..5, 13);
+     assert_eq!(&bytes, b"Hello, World!");
+ }
+ 
+ #[test]
+ #[should_panic(expected = "range end index 14 out of range for slice of length 13")]
+ fn test_copy_within_panics_src_too_long() {
+     let mut bytes = *b"Hello, World!";
+     // The length is only 13, so 14 is out of bounds.
+     bytes.copy_within(10..14, 0);
+ }
+ 
+ #[test]
+ #[should_panic(expected = "dest is out of bounds")]
+ fn test_copy_within_panics_dest_too_long() {
+     let mut bytes = *b"Hello, World!";
+     // The length is only 13, so a slice of length 4 starting at index 10 is out of bounds.
+     bytes.copy_within(0..4, 10);
+ }
+ #[test]
+ #[should_panic(expected = "slice index starts at 2 but ends at 1")]
+ fn test_copy_within_panics_src_inverted() {
+     let mut bytes = *b"Hello, World!";
+     // 2 is greater than 1, so this range is invalid.
+     bytes.copy_within(2..1, 0);
+ }
+ #[test]
+ #[should_panic(expected = "attempted to index slice up to maximum usize")]
+ fn test_copy_within_panics_src_out_of_bounds() {
+     let mut bytes = *b"Hello, World!";
+     // an inclusive range ending at usize::MAX would make src_end overflow
+     bytes.copy_within(usize::MAX..=usize::MAX, 0);
+ }
+ 
+ #[test]
+ fn test_is_sorted() {
+     let empty: [i32; 0] = [];
+ 
+     assert!([1, 2, 2, 9].is_sorted());
+     assert!(![1, 3, 2].is_sorted());
+     assert!([0].is_sorted());
+     assert!(empty.is_sorted());
+     assert!(![0.0, 1.0, f32::NAN].is_sorted());
+     assert!([-2, -1, 0, 3].is_sorted());
+     assert!(![-2i32, -1, 0, 3].is_sorted_by_key(|n| n.abs()));
+     assert!(!["c", "bb", "aaa"].is_sorted());
+     assert!(["c", "bb", "aaa"].is_sorted_by_key(|s| s.len()));
+ }
+ 
+ #[test]
+ fn test_slice_run_destructors() {
+     // Make sure that destructors get run on slice literals
+     struct Foo<'a> {
+         x: &'a Cell<isize>,
+     }
+ 
+     impl<'a> Drop for Foo<'a> {
+         fn drop(&mut self) {
+             self.x.set(self.x.get() + 1);
+         }
+     }
+ 
+     fn foo(x: &Cell<isize>) -> Foo<'_> {
+         Foo { x }
+     }
+ 
+     let x = &Cell::new(0);
+ 
+     {
+         let l = &[foo(x)];
+         assert_eq!(l[0].x.get(), 0);
+     }
+ 
+     assert_eq!(x.get(), 1);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/str.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/str.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/str.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/str.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ // All `str` tests live in liballoc/tests
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/str_lossy.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/str_lossy.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/str_lossy.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/str_lossy.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,85 ----
+ use core::str::lossy::*;
+ 
+ #[test]
+ fn chunks() {
+     let mut iter = Utf8Lossy::from_bytes(b"hello").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "hello", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes("ศไทย中华Việt Nam".as_bytes()).chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "ศไทย中华Việt Nam", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes(b"Hello\xC2 There\xFF Goodbye").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "Hello", broken: b"\xC2" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: " There", broken: b"\xFF" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: " Goodbye", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes(b"Hello\xC0\x80 There\xE6\x83 Goodbye").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "Hello", broken: b"\xC0" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: " There", broken: b"\xE6\x83" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: " Goodbye", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes(b"\xF5foo\xF5\x80bar").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xF5" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "foo", broken: b"\xF5" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "bar", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes(b"\xF1foo\xF1\x80bar\xF1\x80\x80baz").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xF1" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "foo", broken: b"\xF1\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "bar", broken: b"\xF1\x80\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "baz", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes(b"\xF4foo\xF4\x80bar\xF4\xBFbaz").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xF4" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "foo", broken: b"\xF4\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "bar", broken: b"\xF4" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xBF" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "baz", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     let mut iter = Utf8Lossy::from_bytes(b"\xF0\x80\x80\x80foo\xF0\x90\x80\x80bar").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xF0" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "foo\u{10000}bar", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ 
+     // surrogates
+     let mut iter = Utf8Lossy::from_bytes(b"\xED\xA0\x80foo\xED\xBF\xBFbar").chunks();
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xED" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xA0" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\x80" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "foo", broken: b"\xED" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xBF" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "", broken: b"\xBF" }), iter.next());
+     assert_eq!(Some(Utf8LossyChunk { valid: "bar", broken: b"" }), iter.next());
+     assert_eq!(None, iter.next());
+ }
+ 
+ #[test]
+ fn display() {
+     assert_eq!(
+         "Hello\u{FFFD}\u{FFFD} There\u{FFFD} Goodbye",
+         &Utf8Lossy::from_bytes(b"Hello\xC0\x80 There\xE6\x83 Goodbye").to_string()
+     );
+ }
+ 
+ #[test]
+ fn debug() {
+     assert_eq!(
+         "\"Hello\\xc0\\x80 There\\xe6\\x83 Goodbye\\u{10d4ea}\"",
+         &format!(
+             "{:?}",
+             Utf8Lossy::from_bytes(b"Hello\xC0\x80 There\xE6\x83 Goodbye\xf4\x8d\x93\xaa")
+         )
+     );
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/task.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/task.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/task.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/task.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,14 ----
+ use core::task::Poll;
+ 
+ #[test]
+ fn poll_const() {
+     // test that the methods of `Poll` are usable in a const context
+ 
+     const POLL: Poll<usize> = Poll::Pending;
+ 
+     const IS_READY: bool = POLL.is_ready();
+     assert!(!IS_READY);
+ 
+     const IS_PENDING: bool = POLL.is_pending();
+     assert!(IS_PENDING);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/time.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/time.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/time.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/time.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,419 ----
+ use core::time::Duration;
+ 
+ #[test]
+ fn creation() {
+     assert_ne!(Duration::from_secs(1), Duration::from_secs(0));
+     assert_eq!(Duration::from_secs(1) + Duration::from_secs(2), Duration::from_secs(3));
+     assert_eq!(
+         Duration::from_millis(10) + Duration::from_secs(4),
+         Duration::new(4, 10 * 1_000_000)
+     );
+     assert_eq!(Duration::from_millis(4000), Duration::new(4, 0));
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn new_overflow() {
+     let _ = Duration::new(u64::MAX, 1_000_000_000);
+ }
+ 
+ #[test]
+ fn secs() {
+     assert_eq!(Duration::new(0, 0).as_secs(), 0);
+     assert_eq!(Duration::new(0, 500_000_005).as_secs(), 0);
+     assert_eq!(Duration::new(0, 1_050_000_001).as_secs(), 1);
+     assert_eq!(Duration::from_secs(1).as_secs(), 1);
+     assert_eq!(Duration::from_millis(999).as_secs(), 0);
+     assert_eq!(Duration::from_millis(1001).as_secs(), 1);
+     assert_eq!(Duration::from_micros(999_999).as_secs(), 0);
+     assert_eq!(Duration::from_micros(1_000_001).as_secs(), 1);
+     assert_eq!(Duration::from_nanos(999_999_999).as_secs(), 0);
+     assert_eq!(Duration::from_nanos(1_000_000_001).as_secs(), 1);
+ }
+ 
+ #[test]
+ fn millis() {
+     assert_eq!(Duration::new(0, 0).subsec_millis(), 0);
+     assert_eq!(Duration::new(0, 500_000_005).subsec_millis(), 500);
+     assert_eq!(Duration::new(0, 1_050_000_001).subsec_millis(), 50);
+     assert_eq!(Duration::from_secs(1).subsec_millis(), 0);
+     assert_eq!(Duration::from_millis(999).subsec_millis(), 999);
+     assert_eq!(Duration::from_millis(1001).subsec_millis(), 1);
+     assert_eq!(Duration::from_micros(999_999).subsec_millis(), 999);
+     assert_eq!(Duration::from_micros(1_001_000).subsec_millis(), 1);
+     assert_eq!(Duration::from_nanos(999_999_999).subsec_millis(), 999);
+     assert_eq!(Duration::from_nanos(1_001_000_000).subsec_millis(), 1);
+ }
+ 
+ #[test]
+ fn micros() {
+     assert_eq!(Duration::new(0, 0).subsec_micros(), 0);
+     assert_eq!(Duration::new(0, 500_000_005).subsec_micros(), 500_000);
+     assert_eq!(Duration::new(0, 1_050_000_001).subsec_micros(), 50_000);
+     assert_eq!(Duration::from_secs(1).subsec_micros(), 0);
+     assert_eq!(Duration::from_millis(999).subsec_micros(), 999_000);
+     assert_eq!(Duration::from_millis(1001).subsec_micros(), 1_000);
+     assert_eq!(Duration::from_micros(999_999).subsec_micros(), 999_999);
+     assert_eq!(Duration::from_micros(1_000_001).subsec_micros(), 1);
+     assert_eq!(Duration::from_nanos(999_999_999).subsec_micros(), 999_999);
+     assert_eq!(Duration::from_nanos(1_000_001_000).subsec_micros(), 1);
+ }
+ 
+ #[test]
+ fn nanos() {
+     assert_eq!(Duration::new(0, 0).subsec_nanos(), 0);
+     assert_eq!(Duration::new(0, 5).subsec_nanos(), 5);
+     assert_eq!(Duration::new(0, 1_000_000_001).subsec_nanos(), 1);
+     assert_eq!(Duration::from_secs(1).subsec_nanos(), 0);
+     assert_eq!(Duration::from_millis(999).subsec_nanos(), 999_000_000);
+     assert_eq!(Duration::from_millis(1001).subsec_nanos(), 1_000_000);
+     assert_eq!(Duration::from_micros(999_999).subsec_nanos(), 999_999_000);
+     assert_eq!(Duration::from_micros(1_000_001).subsec_nanos(), 1000);
+     assert_eq!(Duration::from_nanos(999_999_999).subsec_nanos(), 999_999_999);
+     assert_eq!(Duration::from_nanos(1_000_000_001).subsec_nanos(), 1);
+ }
+ 
+ #[test]
+ fn add() {
+     assert_eq!(Duration::new(0, 0) + Duration::new(0, 1), Duration::new(0, 1));
+     assert_eq!(Duration::new(0, 500_000_000) + Duration::new(0, 500_000_001), Duration::new(1, 1));
+ }
+ 
+ #[test]
+ fn checked_add() {
+     assert_eq!(Duration::new(0, 0).checked_add(Duration::new(0, 1)), Some(Duration::new(0, 1)));
+     assert_eq!(
+         Duration::new(0, 500_000_000).checked_add(Duration::new(0, 500_000_001)),
+         Some(Duration::new(1, 1))
+     );
+     assert_eq!(Duration::new(1, 0).checked_add(Duration::new(u64::MAX, 0)), None);
+ }
+ 
+ #[test]
+ fn saturating_add() {
+     assert_eq!(Duration::new(0, 0).saturating_add(Duration::new(0, 1)), Duration::new(0, 1));
+     assert_eq!(
+         Duration::new(0, 500_000_000).saturating_add(Duration::new(0, 500_000_001)),
+         Duration::new(1, 1)
+     );
+     assert_eq!(Duration::new(1, 0).saturating_add(Duration::new(u64::MAX, 0)), Duration::MAX);
+ }
+ 
+ #[test]
+ fn sub() {
+     assert_eq!(Duration::new(0, 1) - Duration::new(0, 0), Duration::new(0, 1));
+     assert_eq!(Duration::new(0, 500_000_001) - Duration::new(0, 500_000_000), Duration::new(0, 1));
+     assert_eq!(Duration::new(1, 0) - Duration::new(0, 1), Duration::new(0, 999_999_999));
+ }
+ 
+ #[test]
+ fn checked_sub() {
+     assert_eq!(Duration::NANOSECOND.checked_sub(Duration::ZERO), Some(Duration::NANOSECOND));
+     assert_eq!(
+         Duration::SECOND.checked_sub(Duration::NANOSECOND),
+         Some(Duration::new(0, 999_999_999))
+     );
+     assert_eq!(Duration::ZERO.checked_sub(Duration::NANOSECOND), None);
+     assert_eq!(Duration::ZERO.checked_sub(Duration::SECOND), None);
+ }
+ 
+ #[test]
+ fn saturating_sub() {
+     assert_eq!(Duration::NANOSECOND.saturating_sub(Duration::ZERO), Duration::NANOSECOND);
+     assert_eq!(
+         Duration::SECOND.saturating_sub(Duration::NANOSECOND),
+         Duration::new(0, 999_999_999)
+     );
+     assert_eq!(Duration::ZERO.saturating_sub(Duration::NANOSECOND), Duration::ZERO);
+     assert_eq!(Duration::ZERO.saturating_sub(Duration::SECOND), Duration::ZERO);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn sub_bad1() {
+     let _ = Duration::new(0, 0) - Duration::new(0, 1);
+ }
+ 
+ #[test]
+ #[should_panic]
+ fn sub_bad2() {
+     let _ = Duration::new(0, 0) - Duration::new(1, 0);
+ }
+ 
+ #[test]
+ fn mul() {
+     assert_eq!(Duration::new(0, 1) * 2, Duration::new(0, 2));
+     assert_eq!(Duration::new(1, 1) * 3, Duration::new(3, 3));
+     assert_eq!(Duration::new(0, 500_000_001) * 4, Duration::new(2, 4));
+     assert_eq!(Duration::new(0, 500_000_001) * 4000, Duration::new(2000, 4000));
+ }
+ 
+ #[test]
+ fn checked_mul() {
+     assert_eq!(Duration::new(0, 1).checked_mul(2), Some(Duration::new(0, 2)));
+     assert_eq!(Duration::new(1, 1).checked_mul(3), Some(Duration::new(3, 3)));
+     assert_eq!(Duration::new(0, 500_000_001).checked_mul(4), Some(Duration::new(2, 4)));
+     assert_eq!(Duration::new(0, 500_000_001).checked_mul(4000), Some(Duration::new(2000, 4000)));
+     assert_eq!(Duration::new(u64::MAX - 1, 0).checked_mul(2), None);
+ }
+ 
+ #[test]
+ fn saturating_mul() {
+     assert_eq!(Duration::new(0, 1).saturating_mul(2), Duration::new(0, 2));
+     assert_eq!(Duration::new(1, 1).saturating_mul(3), Duration::new(3, 3));
+     assert_eq!(Duration::new(0, 500_000_001).saturating_mul(4), Duration::new(2, 4));
+     assert_eq!(Duration::new(0, 500_000_001).saturating_mul(4000), Duration::new(2000, 4000));
+     assert_eq!(Duration::new(u64::MAX - 1, 0).saturating_mul(2), Duration::MAX);
+ }
+ 
+ #[test]
+ fn div() {
+     assert_eq!(Duration::new(0, 1) / 2, Duration::new(0, 0));
+     assert_eq!(Duration::new(1, 1) / 3, Duration::new(0, 333_333_333));
+     assert_eq!(Duration::new(99, 999_999_000) / 100, Duration::new(0, 999_999_990));
+ }
+ 
+ #[test]
+ fn checked_div() {
+     assert_eq!(Duration::new(2, 0).checked_div(2), Some(Duration::new(1, 0)));
+     assert_eq!(Duration::new(1, 0).checked_div(2), Some(Duration::new(0, 500_000_000)));
+     assert_eq!(Duration::new(2, 0).checked_div(0), None);
+ }
+ 
+ #[test]
+ fn correct_sum() {
+     let durations = [
+         Duration::new(1, 999_999_999),
+         Duration::new(2, 999_999_999),
+         Duration::new(0, 999_999_999),
+         Duration::new(0, 999_999_999),
+         Duration::new(0, 999_999_999),
+         Duration::new(5, 0),
+     ];
+     let sum = durations.iter().sum::<Duration>();
+     assert_eq!(sum, Duration::new(1 + 2 + 5 + 4, 1_000_000_000 - 5));
+ }
+ 
+ #[test]
+ fn debug_formatting_extreme_values() {
+     assert_eq!(
+         format!("{:?}", Duration::new(18_446_744_073_709_551_615, 123_456_789)),
+         "18446744073709551615.123456789s"
+     );
+ }
+ 
+ #[test]
+ fn debug_formatting_secs() {
+     assert_eq!(format!("{:?}", Duration::new(7, 000_000_000)), "7s");
+     assert_eq!(format!("{:?}", Duration::new(7, 100_000_000)), "7.1s");
+     assert_eq!(format!("{:?}", Duration::new(7, 000_010_000)), "7.00001s");
+     assert_eq!(format!("{:?}", Duration::new(7, 000_000_001)), "7.000000001s");
+     assert_eq!(format!("{:?}", Duration::new(7, 123_456_789)), "7.123456789s");
+ 
+     assert_eq!(format!("{:?}", Duration::new(88, 000_000_000)), "88s");
+     assert_eq!(format!("{:?}", Duration::new(88, 100_000_000)), "88.1s");
+     assert_eq!(format!("{:?}", Duration::new(88, 000_010_000)), "88.00001s");
+     assert_eq!(format!("{:?}", Duration::new(88, 000_000_001)), "88.000000001s");
+     assert_eq!(format!("{:?}", Duration::new(88, 123_456_789)), "88.123456789s");
+ 
+     assert_eq!(format!("{:?}", Duration::new(999, 000_000_000)), "999s");
+     assert_eq!(format!("{:?}", Duration::new(999, 100_000_000)), "999.1s");
+     assert_eq!(format!("{:?}", Duration::new(999, 000_010_000)), "999.00001s");
+     assert_eq!(format!("{:?}", Duration::new(999, 000_000_001)), "999.000000001s");
+     assert_eq!(format!("{:?}", Duration::new(999, 123_456_789)), "999.123456789s");
+ }
+ 
+ #[test]
+ fn debug_formatting_millis() {
+     assert_eq!(format!("{:?}", Duration::new(0, 7_000_000)), "7ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 7_100_000)), "7.1ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 7_000_001)), "7.000001ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 7_123_456)), "7.123456ms");
+ 
+     assert_eq!(format!("{:?}", Duration::new(0, 88_000_000)), "88ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 88_100_000)), "88.1ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 88_000_001)), "88.000001ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 88_123_456)), "88.123456ms");
+ 
+     assert_eq!(format!("{:?}", Duration::new(0, 999_000_000)), "999ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 999_100_000)), "999.1ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 999_000_001)), "999.000001ms");
+     assert_eq!(format!("{:?}", Duration::new(0, 999_123_456)), "999.123456ms");
+ }
+ 
+ #[test]
+ fn debug_formatting_micros() {
+     assert_eq!(format!("{:?}", Duration::new(0, 7_000)), "7µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 7_100)), "7.1µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 7_001)), "7.001µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 7_123)), "7.123µs");
+ 
+     assert_eq!(format!("{:?}", Duration::new(0, 88_000)), "88µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 88_100)), "88.1µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 88_001)), "88.001µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 88_123)), "88.123µs");
+ 
+     assert_eq!(format!("{:?}", Duration::new(0, 999_000)), "999µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 999_100)), "999.1µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 999_001)), "999.001µs");
+     assert_eq!(format!("{:?}", Duration::new(0, 999_123)), "999.123µs");
+ }
+ 
+ #[test]
+ fn debug_formatting_nanos() {
+     assert_eq!(format!("{:?}", Duration::new(0, 0)), "0ns");
+     assert_eq!(format!("{:?}", Duration::new(0, 1)), "1ns");
+     assert_eq!(format!("{:?}", Duration::new(0, 88)), "88ns");
+     assert_eq!(format!("{:?}", Duration::new(0, 999)), "999ns");
+ }
+ 
+ #[test]
+ fn debug_formatting_precision_zero() {
+     assert_eq!(format!("{:.0?}", Duration::new(0, 0)), "0ns");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 123)), "123ns");
+ 
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_001)), "1µs");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_499)), "1µs");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_500)), "2µs");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_999)), "2µs");
+ 
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_000_001)), "1ms");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_499_999)), "1ms");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_500_000)), "2ms");
+     assert_eq!(format!("{:.0?}", Duration::new(0, 1_999_999)), "2ms");
+ 
+     assert_eq!(format!("{:.0?}", Duration::new(1, 000_000_001)), "1s");
+     assert_eq!(format!("{:.0?}", Duration::new(1, 499_999_999)), "1s");
+     assert_eq!(format!("{:.0?}", Duration::new(1, 500_000_000)), "2s");
+     assert_eq!(format!("{:.0?}", Duration::new(1, 999_999_999)), "2s");
+ }
+ 
+ #[test]
+ fn debug_formatting_precision_two() {
+     assert_eq!(format!("{:.2?}", Duration::new(0, 0)), "0.00ns");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 123)), "123.00ns");
+ 
+     assert_eq!(format!("{:.2?}", Duration::new(0, 1_000)), "1.00µs");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 7_001)), "7.00µs");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 7_100)), "7.10µs");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 7_109)), "7.11µs");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 7_199)), "7.20µs");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 1_999)), "2.00µs");
+ 
+     assert_eq!(format!("{:.2?}", Duration::new(0, 1_000_000)), "1.00ms");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 3_001_000)), "3.00ms");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 3_100_000)), "3.10ms");
+     assert_eq!(format!("{:.2?}", Duration::new(0, 1_999_999)), "2.00ms");
+ 
+     assert_eq!(format!("{:.2?}", Duration::new(1, 000_000_000)), "1.00s");
+     assert_eq!(format!("{:.2?}", Duration::new(4, 001_000_000)), "4.00s");
+     assert_eq!(format!("{:.2?}", Duration::new(2, 100_000_000)), "2.10s");
+     assert_eq!(format!("{:.2?}", Duration::new(2, 104_990_000)), "2.10s");
+     assert_eq!(format!("{:.2?}", Duration::new(2, 105_000_000)), "2.11s");
+     assert_eq!(format!("{:.2?}", Duration::new(8, 999_999_999)), "9.00s");
+ }
+ 
+ #[test]
+ fn debug_formatting_precision_high() {
+     assert_eq!(format!("{:.5?}", Duration::new(0, 23_678)), "23.67800µs");
+ 
+     assert_eq!(format!("{:.9?}", Duration::new(1, 000_000_000)), "1.000000000s");
+     assert_eq!(format!("{:.10?}", Duration::new(4, 001_000_000)), "4.0010000000s");
+     assert_eq!(format!("{:.20?}", Duration::new(4, 001_000_000)), "4.00100000000000000000s");
+ }
+ 
+ #[test]
+ fn duration_const() {
+     // test that the methods of `Duration` are usable in a const context
+ 
+     const DURATION: Duration = Duration::new(0, 123_456_789);
+ 
+     const SUB_SEC_MILLIS: u32 = DURATION.subsec_millis();
+     assert_eq!(SUB_SEC_MILLIS, 123);
+ 
+     const SUB_SEC_MICROS: u32 = DURATION.subsec_micros();
+     assert_eq!(SUB_SEC_MICROS, 123_456);
+ 
+     const SUB_SEC_NANOS: u32 = DURATION.subsec_nanos();
+     assert_eq!(SUB_SEC_NANOS, 123_456_789);
+ 
+     const IS_ZERO: bool = Duration::ZERO.is_zero();
+     assert!(IS_ZERO);
+ 
+     const SECONDS: u64 = Duration::SECOND.as_secs();
+     assert_eq!(SECONDS, 1);
+ 
+     const FROM_SECONDS: Duration = Duration::from_secs(1);
+     assert_eq!(FROM_SECONDS, Duration::SECOND);
+ 
+     const SECONDS_F32: f32 = Duration::SECOND.as_secs_f32();
+     assert_eq!(SECONDS_F32, 1.0);
+ 
+     const FROM_SECONDS_F32: Duration = Duration::from_secs_f32(1.0);
+     assert_eq!(FROM_SECONDS_F32, Duration::SECOND);
+ 
+     const SECONDS_F64: f64 = Duration::SECOND.as_secs_f64();
+     assert_eq!(SECONDS_F64, 1.0);
+ 
+     const FROM_SECONDS_F64: Duration = Duration::from_secs_f64(1.0);
+     assert_eq!(FROM_SECONDS_F64, Duration::SECOND);
+ 
+     const MILLIS: u128 = Duration::SECOND.as_millis();
+     assert_eq!(MILLIS, 1_000);
+ 
+     const FROM_MILLIS: Duration = Duration::from_millis(1_000);
+     assert_eq!(FROM_MILLIS, Duration::SECOND);
+ 
+     const MICROS: u128 = Duration::SECOND.as_micros();
+     assert_eq!(MICROS, 1_000_000);
+ 
+     const FROM_MICROS: Duration = Duration::from_micros(1_000_000);
+     assert_eq!(FROM_MICROS, Duration::SECOND);
+ 
+     const NANOS: u128 = Duration::SECOND.as_nanos();
+     assert_eq!(NANOS, 1_000_000_000);
+ 
+     const FROM_NANOS: Duration = Duration::from_nanos(1_000_000_000);
+     assert_eq!(FROM_NANOS, Duration::SECOND);
+ 
+     const MAX: Duration = Duration::new(u64::MAX, 999_999_999);
+ 
+     const CHECKED_ADD: Option<Duration> = MAX.checked_add(Duration::SECOND);
+     assert_eq!(CHECKED_ADD, None);
+ 
+     const CHECKED_SUB: Option<Duration> = Duration::ZERO.checked_sub(Duration::SECOND);
+     assert_eq!(CHECKED_SUB, None);
+ 
+     const CHECKED_MUL: Option<Duration> = Duration::SECOND.checked_mul(1);
+     assert_eq!(CHECKED_MUL, Some(Duration::SECOND));
+ 
+     const MUL_F32: Duration = Duration::SECOND.mul_f32(1.0);
+     assert_eq!(MUL_F32, Duration::SECOND);
+ 
+     const MUL_F64: Duration = Duration::SECOND.mul_f64(1.0);
+     assert_eq!(MUL_F64, Duration::SECOND);
+ 
+     const CHECKED_DIV: Option<Duration> = Duration::SECOND.checked_div(1);
+     assert_eq!(CHECKED_DIV, Some(Duration::SECOND));
+ 
+     const DIV_F32: Duration = Duration::SECOND.div_f32(1.0);
+     assert_eq!(DIV_F32, Duration::SECOND);
+ 
+     const DIV_F64: Duration = Duration::SECOND.div_f64(1.0);
+     assert_eq!(DIV_F64, Duration::SECOND);
+ 
+     const DIV_DURATION_F32: f32 = Duration::SECOND.div_duration_f32(Duration::SECOND);
+     assert_eq!(DIV_DURATION_F32, 1.0);
+ 
+     const DIV_DURATION_F64: f64 = Duration::SECOND.div_duration_f64(Duration::SECOND);
+     assert_eq!(DIV_DURATION_F64, 1.0);
+ 
+     const SATURATING_ADD: Duration = MAX.saturating_add(Duration::SECOND);
+     assert_eq!(SATURATING_ADD, MAX);
+ 
+     const SATURATING_SUB: Duration = Duration::ZERO.saturating_sub(Duration::SECOND);
+     assert_eq!(SATURATING_SUB, Duration::ZERO);
+ 
+     const SATURATING_MUL: Duration = MAX.saturating_mul(2);
+     assert_eq!(SATURATING_MUL, MAX);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/core/tests/tuple.rs gcc-16-20251102/libgrust/rustc-lib/core/tests/tuple.rs
*** gcc-16-20251026/libgrust/rustc-lib/core/tests/tuple.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/core/tests/tuple.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,61 ----
+ use std::cmp::Ordering::{Equal, Greater, Less};
+ 
+ #[test]
+ fn test_clone() {
+     let a = (1, "2");
+     let b = a.clone();
+     assert_eq!(a, b);
+ }
+ 
+ #[test]
+ fn test_partial_eq() {
+     let (small, big) = ((1, 2, 3), (3, 2, 1));
+     assert_eq!(small, small);
+     assert_eq!(big, big);
+     assert_ne!(small, big);
+     assert_ne!(big, small);
+ }
+ 
+ #[test]
+ fn test_partial_ord() {
+     let (small, big) = ((1, 2, 3), (3, 2, 1));
+ 
+     assert!(small < big);
+     assert!(!(small < small));
+     assert!(!(big < small));
+     assert!(!(big < big));
+ 
+     assert!(small <= small);
+     assert!(big <= big);
+ 
+     assert!(big > small);
+     assert!(small >= small);
+     assert!(big >= small);
+     assert!(big >= big);
+ 
+     assert!(!((1.0f64, 2.0f64) < (f64::NAN, 3.0)));
+     assert!(!((1.0f64, 2.0f64) <= (f64::NAN, 3.0)));
+     assert!(!((1.0f64, 2.0f64) > (f64::NAN, 3.0)));
+     assert!(!((1.0f64, 2.0f64) >= (f64::NAN, 3.0)));
+     assert!(((1.0f64, 2.0f64) < (2.0, f64::NAN)));
+     assert!(!((2.0f64, 2.0f64) < (2.0, f64::NAN)));
+ }
+ 
+ #[test]
+ fn test_ord() {
+     let (small, big) = ((1, 2, 3), (3, 2, 1));
+     assert_eq!(small.cmp(&small), Equal);
+     assert_eq!(big.cmp(&big), Equal);
+     assert_eq!(small.cmp(&big), Less);
+     assert_eq!(big.cmp(&small), Greater);
+ }
+ 
+ #[test]
+ fn test_show() {
+     let s = format!("{:?}", (1,));
+     assert_eq!(s, "(1,)");
+     let s = format!("{:?}", (1, true));
+     assert_eq!(s, "(1, true)");
+     let s = format!("{:?}", (1, "hi", true));
+     assert_eq!(s, "(1, \"hi\", true)");
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/.cirrus.yml gcc-16-20251102/libgrust/rustc-lib/stdarch/.cirrus.yml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/.cirrus.yml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/.cirrus.yml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ task:
+   name: x86_64-unknown-freebsd
+   freebsd_instance:
+     image: freebsd-12-1-release-amd64
+   setup_script:
+     - pkg install -y curl
+     - curl https://sh.rustup.rs -sSf --output rustup.sh
+     - sh rustup.sh --default-toolchain nightly -y
+     - . $HOME/.cargo/env
+     - rustup default nightly
+   test_script:
+     - . $HOME/.cargo/env
+     - cargo build --all
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/.github/workflows/main.yml gcc-16-20251102/libgrust/rustc-lib/stdarch/.github/workflows/main.yml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/.github/workflows/main.yml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/.github/workflows/main.yml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,209 ----
+ name: CI
+ on:
+   push:
+     branches:
+     - auto
+     - try
+   pull_request:
+     branches:
+     - master
+ 
+ jobs:
+   style:
+     name: Check Style
+     runs-on: ubuntu-latest
+     steps:
+     - uses: actions/checkout@master
+     - name: Install Rust
+       run: rustup update nightly && rustup default nightly
+     - run: ci/style.sh
+ 
+   docs:
+     name: Build Documentation
+     needs: [style]
+     runs-on: ubuntu-latest
+     steps:
+     - uses: actions/checkout@master
+     - name: Install Rust
+       run: rustup update nightly && rustup default nightly
+     - run: ci/dox.sh
+       env:
+         CI: 1
+     - name: Publish documentation
+       run: |
+         cd target/doc
+         git init
+         git add .
+         git -c user.name='ci' -c user.email='ci' commit -m init
+         git push -f -q https://git:${{ secrets.github_token }}@github.com/${{ github.repository }} HEAD:gh-pages
+       if: github.event_name == 'push' && github.event.ref == 'refs/heads/master'
+ 
+   verify:
+     name: Automatic intrinsic verification
+     needs: [style]
+     runs-on: ubuntu-latest
+     steps:
+     - uses: actions/checkout@master
+     - name: Install Rust
+       run: rustup update nightly && rustup default nightly
+     - run: cargo test --manifest-path crates/stdarch-verify/Cargo.toml
+ 
+   env_override:
+     name: Env Override
+     needs: [style]
+     runs-on: ubuntu-latest
+     steps:
+     - uses: actions/checkout@master
+     - name: Install Rust
+       run: rustup update nightly && rustup default nightly
+     - run: RUST_STD_DETECT_UNSTABLE=avx cargo test --features=std_detect_env_override --manifest-path crates/std_detect/Cargo.toml env_override_no_avx
+ 
+   test:
+     needs: [style]
+     name: Test
+     runs-on: ${{ matrix.os }}
+     strategy:
+       matrix:
+         target:
+         # Dockers that are run through docker on linux
+         - i686-unknown-linux-gnu
+         - x86_64-unknown-linux-gnu
+         - x86_64-unknown-linux-gnu-emulated
+         - arm-unknown-linux-gnueabihf
+         - armv7-unknown-linux-gnueabihf
+         - aarch64-unknown-linux-gnu
+         - powerpc64le-unknown-linux-gnu
+         - mips-unknown-linux-gnu
+         - mips64-unknown-linux-gnuabi64
+         - mips64el-unknown-linux-gnuabi64
+         - s390x-unknown-linux-gnu
+         - wasm32-wasi
+         - i586-unknown-linux-gnu
+         - x86_64-linux-android
+         - arm-linux-androideabi
+         - mipsel-unknown-linux-musl
+         - aarch64-linux-android
+         - nvptx64-nvidia-cuda
+         - thumbv6m-none-eabi
+         - thumbv7m-none-eabi
+         - thumbv7em-none-eabi
+         - thumbv7em-none-eabihf
+ 
+         # macOS targets
+         - x86_64-apple-darwin
+         # FIXME: gh-actions build environment doesn't have linker support
+         # - i686-apple-darwin
+ 
+         # Windows targets
+         - x86_64-pc-windows-msvc
+         # FIXME: Disassembly not implemented for the # following targets:
+         # - x86_64-pc-windows-gnu:
+         # - i686-pc-windows-gnu:
+         # - i686-pc-windows-msvc:
+ 
+         include:
+         - target: i686-unknown-linux-gnu
+           os: ubuntu-latest
+         - target: x86_64-unknown-linux-gnu
+           os: ubuntu-latest
+         - target: x86_64-unknown-linux-gnu-emulated
+           os: ubuntu-latest
+           test_everything: true
+           rustflags: --cfg stdarch_intel_sde
+         - target: arm-unknown-linux-gnueabihf
+           os: ubuntu-latest
+         - target: armv7-unknown-linux-gnueabihf
+           os: ubuntu-latest
+           rustflags: -C target-feature=+neon
+         - target: mips-unknown-linux-gnu
+           os: ubuntu-latest
+           norun: true
+         - target: mips64-unknown-linux-gnuabi64
+           os: ubuntu-latest
+           norun: true
+         - target: mips64el-unknown-linux-gnuabi64
+           os: ubuntu-latest
+           norun: true
+         - target: powerpc64le-unknown-linux-gnu
+           os: ubuntu-latest
+           disable_assert_instr: true
+         - target: s390x-unknown-linux-gnu
+           os: ubuntu-latest
+         - target: wasm32-wasi
+           os: ubuntu-latest
+         - target: aarch64-unknown-linux-gnu
+           os: ubuntu-latest
+         - target: x86_64-apple-darwin
+           os: macos-latest
+         - target: x86_64-pc-windows-msvc
+           os: windows-latest
+         - target: i586-unknown-linux-gnu
+           os: ubuntu-latest
+         - target: x86_64-linux-android
+           os: ubuntu-latest
+           disable_assert_instr: 1
+         - target: arm-linux-androideabi
+           os: ubuntu-latest
+           disable_assert_instr: 1
+         - target: mipsel-unknown-linux-musl
+           os: ubuntu-latest
+           norun: 1
+         - target: aarch64-linux-android
+           os: ubuntu-latest
+           disable_assert_instr: 1
+         - target: nvptx64-nvidia-cuda
+           os: ubuntu-latest
+         - target: thumbv6m-none-eabi
+           os: ubuntu-latest
+         - target: thumbv7m-none-eabi
+           os: ubuntu-latest
+         - target: thumbv7em-none-eabi
+           os: ubuntu-latest
+         - target: thumbv7em-none-eabihf
+           os: ubuntu-latest
+ 
+     steps:
+     - uses: actions/checkout@master
+     - name: Install Rust (rustup)
+       run: |
+         rustup update nightly --no-self-update
+         rustup default nightly
+       if: matrix.os != 'macos-latest'
+     - name: Install Rust (macos)
+       run: |
+         curl https://sh.rustup.rs | sh -s -- -y --default-toolchain nightly
+         echo "##[add-path]$HOME/.cargo/bin"
+         rustup update nightly --no-self-update
+         rustup default nightly
+       if: matrix.os == 'macos-latest'
+     - run: |
+         rustup default nightly
+         rustup target add ${{ matrix.target }}
+       if: "!endsWith(matrix.target, 'emulated')"
+     - run: cargo generate-lockfile
+ 
+     # Configure some env vars based on matrix configuration
+     - run: echo "##[set-env name=NORUN]1"
+       if: matrix.norun != '' || startsWith(matrix.target, 'thumb') || matrix.target == 'nvptx64-nvidia-cuda'
+     - run: echo "##[set-env name=STDARCH_TEST_EVERYTHING]1"
+       if: matrix.test_everything != ''
+     - run: echo "##[set-env name=RUSTFLAGS]${{ matrix.rustflags }}"
+       if: matrix.rustflags != ''
+     - run: echo "##[set-env name=STDARCH_DISABLE_ASSERT_INSTR]1"
+       if: matrix.disable_assert_instr != ''
+     - run: echo "##[set-env name=NOSTD]1"
+       if: startsWith(matrix.target, 'thumb') || matrix.target == 'nvptx64-nvidia-cuda'
+ 
+     # Windows & OSX go straight to `run.sh` ...
+     - run: ./ci/run.sh
+       shell: bash
+       if: matrix.os != 'ubuntu-latest' || startsWith(matrix.target, 'thumb')
+       env:
+         TARGET: ${{ matrix.target }}
+ 
+     # ... while Linux goes to `run-docker.sh`
+     - run: ./ci/run-docker.sh ${{ matrix.target }}
+       shell: bash
+       if: "matrix.os == 'ubuntu-latest' && !startsWith(matrix.target, 'thumb')"
+       env:
+         TARGET: ${{ matrix.target }}
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/.gitignore gcc-16-20251102/libgrust/rustc-lib/stdarch/.gitignore
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/.gitignore	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/.gitignore	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,6 ----
+ Cargo.lock
+ .*.swp
+ target
+ tags
+ crates/stdarch-gen/aarch64.rs
+ crates/stdarch-gen/arm.rs
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/CONTRIBUTING.md gcc-16-20251102/libgrust/rustc-lib/stdarch/CONTRIBUTING.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/CONTRIBUTING.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/CONTRIBUTING.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,80 ----
+ # Contributing to stdarch
+ 
+ The `stdarch` crate is more than willing to accept contributions! First you'll
+ probably want to check out the repository and make sure that tests pass for you:
+ 
+ ```
+ $ git clone https://github.com/rust-lang/stdarch
+ $ cd stdarch
+ $ cargo +nightly test
+ ```
+ 
+ To run codegen tests, run in release mode:
+ 
+ ```
+ $ cargo +nightly test --release -p coresimd
+ ```
+ 
+ Remember that this repository requires the nightly channel of Rust! If any of
+ the above steps don't work, [please let us know][new]!
+ 
+ Next up you can [find an issue][issues] to help out on, we've selected a few
+ with the [`help wanted`][help] and [`impl-period`][impl] tags which could
+ particularly use some help. You may be most interested in [#40][vendor],
+ implementing all vendor intrinsics on x86. That issue's got some good pointers
+ about where to get started!
+ 
+ If you've got general questions feel free to [join us on gitter][gitter] and ask
+ around! Feel free to ping either @BurntSushi or @alexcrichton with questions.
+ 
+ [gitter]: https://gitter.im/rust-impl-period/WG-libs-simd
+ 
+ # How to write examples for stdarch intrinsics
+ 
+ There are a few features that must be enabled for the given intrinsic to work
+ properly and the example must only be run by `cargo test --doc` when the feature
+ is supported by the CPU. As a result, the default `fn main` that is generated by
+ `rustdoc` will not work (in most cases). Consider using the following as a guide
+ to ensure your example works as expected.
+ 
+ ```rust
+ /// # // We need cfg_target_feature to ensure the example is only
+ /// # // run by `cargo test --doc` when the CPU supports the feature
+ /// # #![feature(cfg_target_feature)]
+ /// # // We need target_feature for the intrinsic to work
+ /// # #![feature(target_feature)]
+ /// #
+ /// # // rustdoc by default uses `extern crate stdarch`, but we need the
+ /// # // `#[macro_use]`
+ /// # #[macro_use] extern crate stdarch;
+ /// #
+ /// # // The real main function
+ /// # fn main() {
+ /// #     // Only run this if `<target feature>` is supported
+ /// #     if cfg_feature_enabled!("<target feature>") {
+ /// #         // Create a `worker` function that will only be run if the target feature
+ /// #         // is supported and ensure that `target_feature` is enabled for your worker
+ /// #         // function
+ /// #         #[target_feature(enable = "<target feature>")]
+ /// #         unsafe fn worker() {
+ ///
+ /// // Write your example here. Feature specific intrinsics will work here! Go wild!
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ ```
+ 
+ If some of the above syntax does not look familiar, the [Documentation as tests] section
+ of the [Rust Book] describes the `rustdoc` syntax quite well. As always, feel free
+ to [join us on gitter][gitter] and ask us if you hit any snags, and thank you for helping
+ to improve the documentation of `stdarch`!
+ 
+ [new]: https://github.com/rust-lang/stdarch/issues/new
+ [issues]: https://github.com/rust-lang/stdarch/issues
+ [help]: https://github.com/rust-lang/stdarch/issues?q=is%3Aissue+is%3Aopen+label%3A%22help+wanted%22
+ [impl]: https://github.com/rust-lang/stdarch/issues?q=is%3Aissue+is%3Aopen+label%3Aimpl-period
+ [vendor]: https://github.com/rust-lang/stdarch/issues/40
+ [Documentation as tests]: https://doc.rust-lang.org/book/first-edition/documentation.html#documentation-as-tests
+ [Rust Book]: https://doc.rust-lang.org/book/first-edition
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,21 ----
+ [workspace]
+ members = [
+   "crates/stdarch-verify",
+   "crates/core_arch",
+   "crates/std_detect",
+   "crates/stdarch-gen",
+   "examples/"
+ ]
+ exclude = [
+   "crates/wasm-assert-instr-tests"
+ ]
+ 
+ [profile.release]
+ debug = true
+ opt-level = 3
+ incremental = true
+ 
+ [profile.bench]
+ debug = 1
+ opt-level = 3
+ incremental = true
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/LICENSE-APACHE gcc-16-20251102/libgrust/rustc-lib/stdarch/LICENSE-APACHE
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/LICENSE-APACHE	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/LICENSE-APACHE	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,201 ----
+                               Apache License
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diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/LICENSE-MIT gcc-16-20251102/libgrust/rustc-lib/stdarch/LICENSE-MIT
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/LICENSE-MIT	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/LICENSE-MIT	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,25 ----
+ Copyright (c) 2017 The Rust Project Developers
+ 
+ Permission is hereby granted, free of charge, to any
+ person obtaining a copy of this software and associated
+ documentation files (the "Software"), to deal in the
+ Software without restriction, including without
+ limitation the rights to use, copy, modify, merge,
+ publish, distribute, sublicense, and/or sell copies of
+ the Software, and to permit persons to whom the Software
+ is furnished to do so, subject to the following
+ conditions:
+ 
+ The above copyright notice and this permission notice
+ shall be included in all copies or substantial portions
+ of the Software.
+ 
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+ SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+ IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/README.md gcc-16-20251102/libgrust/rustc-lib/stdarch/README.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/README.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/README.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,40 ----
+ stdarch - Rust's standard library SIMD components
+ =======
+ 
+ [![Actions Status](https://github.com/rust-lang/stdarch/workflows/CI/badge.svg)](https://github.com/rust-lang/stdarch/actions)
+ 
+ 
+ # Crates
+ 
+ This repository contains two main crates:
+ 
+ * [![core_arch_crate_badge]][core_arch_crate_link]
+   [![core_arch_docs_badge]][core_arch_docs_link]
+   [`core_arch`](crates/core_arch/README.md) implements `core::arch` - Rust's
+   core library architecture-specific intrinsics, and
+   
+ * [![std_detect_crate_badge]][std_detect_crate_link]
+   [![std_detect_docs_badge]][std_detect_docs_link]
+   [`std_detect`](crates/std_detect/README.md) implements `std::detect` - Rust's
+   standard library run-time CPU feature detection.
+ 
+ The `std::simd` component now lives in the
+ [`packed_simd`](https://github.com/rust-lang-nursery/packed_simd) crate.
+ 
+ # How to do a release
+ 
+ To do a release of the `core_arch` and `std_detect` crates, 
+ 
+ * bump up the version appropriately,
+ * comment out the `dev-dependencies` in their `Cargo.toml` files (due to
+   https://github.com/rust-lang/cargo/issues/4242),
+ * publish the crates.
+ 
+ [core_arch_crate_badge]: https://img.shields.io/crates/v/core_arch.svg
+ [core_arch_crate_link]: https://crates.io/crates/core_arch
+ [core_arch_docs_badge]: https://docs.rs/core_arch/badge.svg
+ [core_arch_docs_link]: https://docs.rs/core_arch/
+ [std_detect_crate_badge]: https://img.shields.io/crates/v/std_detect.svg
+ [std_detect_crate_link]: https://crates.io/crates/std_detect
+ [std_detect_docs_badge]: https://docs.rs/std_detect/badge.svg
+ [std_detect_docs_link]: https://docs.rs/std_detect/
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/android-install-ndk.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/android-install-ndk.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/android-install-ndk.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/android-install-ndk.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,38 ----
+ #!/usr/bin/env sh
+ # Copyright 2016 The Rust Project Developers. See the COPYRIGHT
+ # file at the top-level directory of this distribution and at
+ # http://rust-lang.org/COPYRIGHT.
+ #
+ # Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
+ # http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
+ # <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
+ # option. This file may not be copied, modified, or distributed
+ # except according to those terms.
+ 
+ set -ex
+ 
+ curl --retry 5 -O \
+      https://dl.google.com/android/repository/android-ndk-r15b-linux-x86_64.zip
+ unzip -q android-ndk-r15b-linux-x86_64.zip
+ 
+ case "${1}" in
+   aarch64)
+     arch=arm64
+     ;;
+ 
+   i686)
+     arch=x86
+     ;;
+ 
+   *)
+     arch="${1}"
+     ;;
+ esac;
+ 
+ android-ndk-r15b/build/tools/make_standalone_toolchain.py \
+         --unified-headers \
+         --install-dir "/android/ndk-${1}" \
+         --arch "${arch}" \
+         --api 24
+ 
+ rm -rf ./android-ndk-r15b-linux-x86_64.zip ./android-ndk-r15b
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/android-install-sdk.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/android-install-sdk.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/android-install-sdk.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/android-install-sdk.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,60 ----
+ #!/usr/bin/env sh
+ # Copyright 2016 The Rust Project Developers. See the COPYRIGHT
+ # file at the top-level directory of this distribution and at
+ # http://rust-lang.org/COPYRIGHT.
+ #
+ # Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
+ # http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
+ # <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
+ # option. This file may not be copied, modified, or distributed
+ # except according to those terms.
+ 
+ set -ex
+ 
+ # Prep the SDK and emulator
+ #
+ # Note that the update process requires that we accept a bunch of licenses, and
+ # we can't just pipe `yes` into it for some reason, so we take the same strategy
+ # located in https://github.com/appunite/docker by just wrapping it in a script
+ # which apparently magically accepts the licenses.
+ 
+ mkdir sdk
+ curl --retry 5 https://dl.google.com/android/repository/sdk-tools-linux-3859397.zip -O
+ unzip -d sdk sdk-tools-linux-3859397.zip
+ 
+ case "$1" in
+   arm | armv7)
+     abi=armeabi-v7a
+     ;;
+ 
+   aarch64)
+     abi=arm64-v8a
+     ;;
+ 
+   i686)
+     abi=x86
+     ;;
+ 
+   x86_64)
+     abi=x86_64
+     ;;
+ 
+   *)
+     echo "invalid arch: $1"
+     exit 1
+     ;;
+ esac;
+ 
+ # --no_https avoids
+ # javax.net.ssl.SSLHandshakeException: sun.security.validator.ValidatorException: No trusted certificate found
+ yes | ./sdk/tools/bin/sdkmanager --licenses --no_https
+ yes | ./sdk/tools/bin/sdkmanager --no_https \
+     "emulator" \
+     "platform-tools" \
+     "platforms;android-24" \
+     "system-images;android-24;default;$abi"
+ 
+ echo "no" |
+     ./sdk/tools/bin/avdmanager create avd \
+         --name "${1}" \
+         --package "system-images;android-24;default;$abi"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/android-sysimage.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/android-sysimage.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/android-sysimage.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/android-sysimage.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,56 ----
+ #!/usr/bin/env bash
+ 
+ # Copyright 2017 The Rust Project Developers. See the COPYRIGHT
+ # file at the top-level directory of this distribution and at
+ # http://rust-lang.org/COPYRIGHT.
+ #
+ # Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
+ # http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
+ # <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
+ # option. This file may not be copied, modified, or distributed
+ # except according to those terms.
+ 
+ set -ex
+ 
+ URL=https://dl.google.com/android/repository/sys-img/android
+ 
+ main() {
+     local arch="${1}"
+     local name="${2}"
+     local dest=/system
+     local td
+     td="$(mktemp -d)"
+ 
+     apt-get install --no-install-recommends e2tools
+ 
+     pushd "$td"
+     curl --retry 5 -O "${URL}/${name}"
+     unzip -q "${name}"
+ 
+     local system
+     system=$(find . -name system.img)
+     mkdir -p $dest/{bin,lib,lib64}
+ 
+     # Extract android linker and libraries to /system
+     # This allows android executables to be run directly (or with qemu)
+     if [ "${arch}" = "x86_64" ] || [ "${arch}" = "arm64" ]; then
+         e2cp -p "${system}:/bin/linker64" "${dest}/bin/"
+         e2cp -p "${system}:/lib64/libdl.so" "${dest}/lib64/"
+         e2cp -p "${system}:/lib64/libc.so" "${dest}/lib64/"
+         e2cp -p "${system}:/lib64/libm.so" "${dest}/lib64/"
+     else
+         e2cp -p "${system}:/bin/linker" "${dest}/bin/"
+         e2cp -p "${system}:/lib/libdl.so" "${dest}/lib/"
+         e2cp -p "${system}:/lib/libc.so" "${dest}/lib/"
+         e2cp -p "${system}:/lib/libm.so" "${dest}/lib/"
+     fi
+ 
+     # clean up
+     apt-get purge --auto-remove -y e2tools
+ 
+     popd
+ 
+     rm -rf "${td}"
+ }
+ 
+ main "${@}"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,47 ----
+ FROM ubuntu:16.04
+ 
+ RUN dpkg --add-architecture i386 && \
+     apt-get update && \
+     apt-get install -y --no-install-recommends \
+   file \
+   make \
+   curl \
+   ca-certificates \
+   python \
+   unzip \
+   expect \
+   openjdk-9-jre \
+   libstdc++6:i386 \
+   libpulse0 \
+   gcc \
+   libc6-dev
+ 
+ WORKDIR /android/
+ COPY android* /android/
+ 
+ ENV ANDROID_ARCH=aarch64
+ ENV PATH=$PATH:/android/ndk-$ANDROID_ARCH/bin:/android/sdk/tools:/android/sdk/platform-tools
+ 
+ RUN sh /android/android-install-ndk.sh $ANDROID_ARCH
+ RUN sh /android/android-install-sdk.sh $ANDROID_ARCH
+ RUN mv /root/.android /tmp
+ RUN chmod 777 -R /tmp/.android
+ RUN chmod 755 /android/sdk/tools/* /android/sdk/emulator/qemu/linux-x86_64/*
+ 
+ ENV PATH=$PATH:/rust/bin \
+     CARGO_TARGET_AARCH64_LINUX_ANDROID_LINKER=aarch64-linux-android-gcc \
+     CARGO_TARGET_AARCH64_LINUX_ANDROID_RUNNER=/tmp/runtest \
+     OBJDUMP=aarch64-linux-android-objdump \
+     HOME=/tmp
+ 
+ ADD runtest-android.rs /tmp/runtest.rs
+ ENTRYPOINT [ \
+   "bash", \
+   "-c", \
+   # set SHELL so android can detect a 64bits system, see
+   # http://stackoverflow.com/a/41789144
+   "SHELL=/bin/dash /android/sdk/emulator/emulator @aarch64 -no-window & \
+    rustc /tmp/runtest.rs -o /tmp/runtest && \
+    exec \"$@\"", \
+   "--" \
+ ]
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,14 ----
+ FROM ubuntu:20.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc \
+   ca-certificates \
+   libc6-dev \
+   gcc-aarch64-linux-gnu \
+   libc6-dev-arm64-cross \
+   qemu-user \
+   make \
+   file
+ 
+ ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \
+     CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -L /usr/aarch64-linux-gnu" \
+     OBJDUMP=aarch64-linux-gnu-objdump
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,47 ----
+ FROM ubuntu:16.04
+ 
+ RUN dpkg --add-architecture i386 && \
+     apt-get update && \
+     apt-get install -y --no-install-recommends \
+   file \
+   make \
+   curl \
+   ca-certificates \
+   python \
+   unzip \
+   expect \
+   openjdk-9-jre \
+   libstdc++6:i386 \
+   libpulse0 \
+   gcc \
+   libc6-dev
+ 
+ WORKDIR /android/
+ COPY android* /android/
+ 
+ ENV ANDROID_ARCH=arm
+ ENV PATH=$PATH:/android/ndk-$ANDROID_ARCH/bin:/android/sdk/tools:/android/sdk/platform-tools
+ 
+ RUN sh /android/android-install-ndk.sh $ANDROID_ARCH
+ RUN sh /android/android-install-sdk.sh $ANDROID_ARCH
+ RUN mv /root/.android /tmp
+ RUN chmod 777 -R /tmp/.android
+ RUN chmod 755 /android/sdk/tools/* /android/sdk/emulator/qemu/linux-x86_64/*
+ 
+ ENV PATH=$PATH:/rust/bin \
+     CARGO_TARGET_ARM_LINUX_ANDROIDEABI_LINKER=arm-linux-androideabi-gcc \
+     CARGO_TARGET_ARM_LINUX_ANDROIDEABI_RUNNER=/tmp/runtest \
+     OBJDUMP=arm-linux-androideabi-objdump \
+     HOME=/tmp
+ 
+ ADD runtest-android.rs /tmp/runtest.rs
+ ENTRYPOINT [ \
+   "bash", \
+   "-c", \
+   # set SHELL so android can detect a 64bits system, see
+   # http://stackoverflow.com/a/41789144
+   "SHELL=/bin/dash /android/sdk/emulator/emulator @arm -no-window & \
+    rustc /tmp/runtest.rs -o /tmp/runtest && \
+    exec \"$@\"", \
+   "--" \
+ ]
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc \
+   ca-certificates \
+   libc6-dev \
+   gcc-arm-linux-gnueabihf \
+   libc6-dev-armhf-cross \
+   qemu-user \
+   make \
+   file
+ ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \
+     CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -L /usr/arm-linux-gnueabihf" \
+     OBJDUMP=arm-linux-gnueabihf-objdump
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc \
+   ca-certificates \
+   libc6-dev \
+   gcc-arm-linux-gnueabihf \
+   libc6-dev-armhf-cross \
+   qemu-user \
+   make \
+   file
+ ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \
+     CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -L /usr/arm-linux-gnueabihf" \
+     OBJDUMP=arm-linux-gnueabihf-objdump
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,7 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc-multilib \
+   libc6-dev \
+   file \
+   make \
+   ca-certificates
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,7 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc-multilib \
+   libc6-dev \
+   file \
+   make \
+   ca-certificates
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         gcc libc6-dev qemu-user ca-certificates \
+         gcc-mips-linux-gnu libc6-dev-mips-cross \
+         qemu-system-mips \
+         qemu-user \
+         make \
+         file
+ 
+ ENV CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_LINKER=mips-linux-gnu-gcc \
+     CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER="qemu-mips -L /usr/mips-linux-gnu" \
+     OBJDUMP=mips-linux-gnu-objdump
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         gcc libc6-dev qemu-user ca-certificates \
+         gcc-mips64-linux-gnuabi64 libc6-dev-mips64-cross \
+         qemu-system-mips64 qemu-user
+ 
+ ENV CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_LINKER=mips64-linux-gnuabi64-gcc \
+     CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER="qemu-mips64 -L /usr/mips64-linux-gnuabi64" \
+     OBJDUMP=mips64-linux-gnuabi64-objdump
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,10 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         gcc libc6-dev qemu-user ca-certificates \
+         gcc-mips64el-linux-gnuabi64 libc6-dev-mips64el-cross \
+         qemu-system-mips64el
+ 
+ ENV CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_LINKER=mips64el-linux-gnuabi64-gcc \
+     CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER="qemu-mips64el -L /usr/mips64el-linux-gnuabi64" \
+     OBJDUMP=mips64el-linux-gnuabi64-objdump
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,25 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && \
+     apt-get install -y --no-install-recommends \
+     ca-certificates \
+     gcc \
+     libc6-dev \
+     make \
+     qemu-user \
+     qemu-system-mips \
+     bzip2 \
+     curl \
+     file
+ 
+ RUN mkdir /toolchain
+ 
+ # Note that this originally came from:
+ # https://downloads.openwrt.org/snapshots/trunk/malta/generic/OpenWrt-Toolchain-malta-le_gcc-5.3.0_musl-1.1.15.Linux-x86_64.tar.bz2
+ RUN curl -L https://ci-mirrors.rust-lang.org/libc/OpenWrt-Toolchain-malta-le_gcc-5.3.0_musl-1.1.15.Linux-x86_64.tar.bz2 | \
+       tar xjf - -C /toolchain --strip-components=2
+ 
+ ENV PATH=$PATH:/rust/bin:/toolchain/bin \
+     CC_mipsel_unknown_linux_musl=mipsel-openwrt-linux-gcc \
+     CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_MUSL_LINKER=mipsel-openwrt-linux-gcc \
+     CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_MUSL_RUNNER="qemu-mipsel -L /toolchain"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,5 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc \
+   libc6-dev \
+   ca-certificates
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,11 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         gcc libc6-dev qemu-user ca-certificates \
+         gcc-powerpc-linux-gnu libc6-dev-powerpc-cross \
+         qemu-system-ppc make file
+ 
+ ENV CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_LINKER=powerpc-linux-gnu-gcc \
+     CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER="qemu-ppc -cpu Vger -L /usr/powerpc-linux-gnu" \
+     CC=powerpc-linux-gnu-gcc \
+     OBJDUMP=powerpc-linux-gnu-objdump
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,11 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         gcc libc6-dev qemu-user ca-certificates \
+         gcc-powerpc64-linux-gnu libc6-dev-ppc64-cross \
+         qemu-system-ppc file make
+ 
+ ENV CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_LINKER=powerpc64-linux-gnu-gcc \
+     CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER="qemu-ppc64 -cpu power9 -L /usr/powerpc64-linux-gnu" \
+     CC=powerpc64-linux-gnu-gcc \
+     OBJDUMP=powerpc64-linux-gnu-objdump
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,12 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         gcc libc6-dev qemu-user ca-certificates \
+         gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross \
+         qemu-system-ppc file make
+ 
+ # Work around qemu triggering a sigill on vec_subs if the cpu target is not defined.
+ ENV CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_LINKER=powerpc64le-linux-gnu-gcc \
+     CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER="qemu-ppc64le -cpu power9 -L /usr/powerpc64le-linux-gnu" \
+     CC=powerpc64le-linux-gnu-gcc \
+     OBJDUMP=powerpc64le-linux-gnu-objdump
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ FROM ubuntu:18.04
+ 
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+         curl ca-certificates \
+         gcc libc6-dev \
+         gcc-s390x-linux-gnu libc6-dev-s390x-cross \
+         qemu-user \
+         make \
+         file
+ 
+ ENV CARGO_TARGET_S390X_UNKNOWN_LINUX_GNU_LINKER=s390x-linux-gnu-gcc \
+     CARGO_TARGET_S390X_UNKNOWN_LINUX_GNU_RUNNER="qemu-s390x -L /usr/s390x-linux-gnu" \
+     OBJDUMP=s390x-linux-gnu-objdump
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,16 ----
+ FROM ubuntu:20.04
+ 
+ ENV DEBIAN_FRONTEND=noninteractive
+ RUN apt-get update -y && apt-get install -y --no-install-recommends \
+   ca-certificates \
+   curl \
+   xz-utils \
+   clang
+ 
+ RUN curl -L https://github.com/bytecodealliance/wasmtime/releases/download/v0.19.0/wasmtime-v0.19.0-x86_64-linux.tar.xz | tar xJf -
+ ENV PATH=$PATH:/wasmtime-v0.19.0-x86_64-linux
+ 
+ ENV CARGO_TARGET_WASM32_WASI_RUNNER="wasmtime \
+   --enable-simd \
+   --mapdir .::/checkout/target/wasm32-wasi/release/deps \
+   --"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,29 ----
+ FROM ubuntu:16.04
+ 
+ RUN apt-get update && \
+     apt-get install -y --no-install-recommends \
+   ca-certificates \
+   curl \
+   gcc \
+   libc-dev \
+   python \
+   unzip \
+   file \
+   make
+ 
+ WORKDIR /android/
+ ENV ANDROID_ARCH=x86_64
+ COPY android-install-ndk.sh /android/
+ RUN sh /android/android-install-ndk.sh $ANDROID_ARCH
+ 
+ # We do not run x86_64-linux-android tests on an android emulator.
+ # See ci/android-sysimage.sh for informations about how tests are run.
+ COPY android-sysimage.sh /android/
+ RUN bash /android/android-sysimage.sh x86_64 x86_64-24_r07.zip
+ 
+ ENV PATH=$PATH:/rust/bin:/android/ndk-$ANDROID_ARCH/bin \
+     CARGO_TARGET_X86_64_LINUX_ANDROID_LINKER=x86_64-linux-android-gcc \
+     CC_x86_64_linux_android=x86_64-linux-android-gcc \
+     CXX_x86_64_linux_android=x86_64-linux-android-g++ \
+     OBJDUMP=x86_64-linux-android-objdump \
+     HOME=/tmp
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,7 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc \
+   libc6-dev \
+   file \
+   make \
+   ca-certificates
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ FROM ubuntu:18.04
+ RUN apt-get update && apt-get install -y --no-install-recommends \
+   gcc \
+   libc6-dev \
+   file \
+   make \
+   ca-certificates \
+   wget \
+   bzip2
+ 
+ RUN wget https://github.com/gnzlbg/intel_sde/raw/master/sde-external-8.35.0-2019-03-11-lin.tar.bz2
+ RUN tar -xjf sde-external-8.35.0-2019-03-11-lin.tar.bz2
+ ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/sde-external-8.35.0-2019-03-11-lin/sde64 -rtm_mode full --"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/dox.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/dox.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/dox.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/dox.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,55 ----
+ #!/usr/bin/env bash
+ 
+ # Builds documentation for all target triples that we have a registered URL for
+ # in liblibc. This scrapes the list of triples to document from `src/lib.rs`
+ # which has a bunch of `html_root_url` directives we pick up.
+ 
+ set -ex
+ 
+ rm -rf target/doc
+ mkdir -p target/doc
+ 
+ dox() {
+   local arch=$1
+   local target=$2
+ 
+   echo "documenting ${arch}"
+ 
+   if [ "$CI" != "" ]; then
+     rustup target add "${target}" || true
+   fi
+ 
+   rm -rf "target/doc/${arch}"
+   mkdir "target/doc/${arch}"
+ 
+   export RUSTFLAGS="--cfg core_arch_docs"
+   export RUSTDOCFLAGS="--cfg core_arch_docs"
+ 
+   cargo build --verbose --target "${target}" --manifest-path crates/core_arch/Cargo.toml
+   cargo build --verbose --target "${target}" --manifest-path crates/std_detect/Cargo.toml
+ 
+   rustdoc --verbose --target "${target}" \
+           -o "target/doc/${arch}" crates/core_arch/src/lib.rs \
+           --edition=2018 \
+           --crate-name core_arch \
+           --library-path "target/${target}/debug/deps" \
+           --cfg core_arch_docs
+   rustdoc --verbose --target "${target}" \
+           -o "target/doc/${arch}" crates/std_detect/src/lib.rs \
+           --edition=2018 \
+           --crate-name std_detect \
+           --library-path "target/${target}/debug/deps" \
+           --extern cfg_if="$(ls target/"${target}"/debug/deps/libcfg_if-*.rlib)" \
+           --extern libc="$(ls target/"${target}"/debug/deps/liblibc-*.rlib)" \
+           --cfg core_arch_docs
+ }
+ 
+ dox i686 i686-unknown-linux-gnu
+ dox x86_64 x86_64-unknown-linux-gnu
+ dox arm armv7-unknown-linux-gnueabihf
+ dox aarch64 aarch64-unknown-linux-gnu
+ dox powerpc powerpc-unknown-linux-gnu
+ dox powerpc64le powerpc64le-unknown-linux-gnu
+ dox mips mips-unknown-linux-gnu
+ dox mips64 mips64-unknown-linux-gnuabi64
+ dox wasm32 wasm32-unknown-unknown
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/gba.json gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/gba.json
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/gba.json	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/gba.json	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,34 ----
+ {
+   "abi-blacklist": [
+     "stdcall",
+     "fastcall",
+     "vectorcall",
+     "thiscall",
+     "win64",
+     "sysv64"
+   ],
+   "arch": "arm",
+   "atomic-cas": false,
+   "cpu": "arm7tdmi",
+   "data-layout": "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64",
+   "emit-debug-gdb-scripts": false,
+   "env": "agb",
+   "executables": true,
+   "features": "+soft-float,+strict-align",
+   "linker": "arm-none-eabi-ld",
+   "linker-flavor": "ld",
+   "linker-is-gnu": true,
+   "llvm-target": "thumbv4-none-agb",
+   "os": "none",
+   "panic-strategy": "abort",
+   "pre-link-args": {
+     "ld": [
+       "-Tlinker.ld"
+     ]
+   },
+   "relocation-model": "static",
+   "target-c-int-width": "32",
+   "target-endian": "little",
+   "target-pointer-width": "32",
+   "vendor": "nintendo"
+ }
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/run-docker.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/run-docker.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/run-docker.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/run-docker.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,45 ----
+ #!/usr/bin/env sh
+ 
+ # Small script to run tests for a target (or all targets) inside all the
+ # respective docker images.
+ 
+ set -ex
+ 
+ run() {
+     target=$(echo "${1}" | sed 's/-emulated//')
+     echo "Building docker container for TARGET=${1}"
+     docker build -t stdarch -f "ci/docker/${1}/Dockerfile" ci/
+     mkdir -p target
+     echo "Running docker"
+     # shellcheck disable=SC2016
+     docker run \
+       --rm \
+       --user "$(id -u)":"$(id -g)" \
+       --env CARGO_HOME=/cargo \
+       --env CARGO_TARGET_DIR=/checkout/target \
+       --env TARGET="${target}" \
+       --env STDARCH_TEST_EVERYTHING \
+       --env STDARCH_ASSERT_INSTR_IGNORE \
+       --env STDARCH_DISABLE_ASSERT_INSTR \
+       --env NOSTD \
+       --env NORUN \
+       --env RUSTFLAGS \
+       --env STDARCH_TEST_NORUN \
+       --volume "$(dirname "$(dirname "$(command -v cargo)")")":/cargo \
+       --volume "$(rustc --print sysroot)":/rust:ro \
+       --volume "$(pwd)":/checkout:ro \
+       --volume "$(pwd)"/target:/checkout/target \
+       --init \
+       --workdir /checkout \
+       --privileged \
+       stdarch \
+       sh -c "HOME=/tmp PATH=\$PATH:/rust/bin exec ci/run.sh ${1}"
+ }
+ 
+ if [ -z "$1" ]; then
+   for d in ci/docker/*; do
+     run "${d}"
+   done
+ else
+   run "${1}"
+ fi
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/run.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/run.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/run.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/run.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,122 ----
+ #!/usr/bin/env sh
+ 
+ set -ex
+ 
+ : "${TARGET?The TARGET environment variable must be set.}"
+ 
+ # Tests are all super fast anyway, and they fault often enough on travis that
+ # having only one thread increases debuggability to be worth it.
+ #export RUST_BACKTRACE=full
+ #export RUST_TEST_NOCAPTURE=1
+ #export RUST_TEST_THREADS=1
+ 
+ RUSTFLAGS="$RUSTFLAGS -D warnings "
+ 
+ case ${TARGET} in
+     # On 32-bit use a static relocation model which avoids some extra
+     # instructions when dealing with static data, notably allowing some
+     # instruction assertion checks to pass below the 20 instruction limit. If
+     # this is the default, dynamic, then too many instructions are generated
+     # when we assert the instruction for a function and it causes tests to fail.
+     #
+     # It's not clear why `-Z plt=yes` is required here. Probably a bug in LLVM.
+     # If you can remove it and CI passes, please feel free to do so!
+     i686-* | i586-*)
+         export RUSTFLAGS="${RUSTFLAGS} -C relocation-model=static -Z plt=yes"
+         ;;
+     #Unoptimized build uses fast-isel which breaks with msa
+     mips-* | mipsel-*)
+ 	export RUSTFLAGS="${RUSTFLAGS} -C llvm-args=-fast-isel=false"
+ 	;;
+ esac
+ 
+ echo "RUSTFLAGS=${RUSTFLAGS}"
+ echo "FEATURES=${FEATURES}"
+ echo "OBJDUMP=${OBJDUMP}"
+ echo "STDARCH_DISABLE_ASSERT_INSTR=${STDARCH_DISABLE_ASSERT_INSTR}"
+ echo "STDARCH_TEST_EVERYTHING=${STDARCH_TEST_EVERYTHING}"
+ 
+ cargo_test() {
+     cmd="cargo"
+     subcmd="test"
+     if [ "$NORUN" = "1" ]; then
+         export subcmd="build"
+     fi
+     cmd="$cmd ${subcmd} --target=$TARGET $1"
+     cmd="$cmd -- $2"
+ 
+     # wasm targets can't catch panics so if a test failures make sure the test
+     # harness isn't trying to capture output, otherwise we won't get any useful
+     # output.
+     case ${TARGET} in
+         wasm32*)
+             cmd="$cmd --nocapture"
+             ;;
+     esac
+ 
+     $cmd
+ }
+ 
+ CORE_ARCH="--manifest-path=crates/core_arch/Cargo.toml"
+ STD_DETECT="--manifest-path=crates/std_detect/Cargo.toml"
+ STDARCH_EXAMPLES="--manifest-path=examples/Cargo.toml"
+ cargo_test "${CORE_ARCH} --release"
+ 
+ if [ "$NOSTD" != "1" ]; then
+     cargo_test "${STD_DETECT}"
+     cargo_test "${STD_DETECT} --release"
+ 
+     cargo_test "${STD_DETECT} --no-default-features"
+     cargo_test "${STD_DETECT} --no-default-features --features=std_detect_file_io"
+     cargo_test "${STD_DETECT} --no-default-features --features=std_detect_dlsym_getauxval"
+     cargo_test "${STD_DETECT} --no-default-features --features=std_detect_dlsym_getauxval,std_detect_file_io"
+ 
+     cargo_test "${STDARCH_EXAMPLES}"
+     cargo_test "${STDARCH_EXAMPLES} --release"
+ fi
+ 
+ # Test targets compiled with extra features.
+ case ${TARGET} in
+     x86*)
+         export STDARCH_DISABLE_ASSERT_INSTR=1
+         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
+         cargo_test "--release"
+         ;;
+     wasm32*)
+         prev="$RUSTFLAGS"
+         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+simd128,+unimplemented-simd128"
+         cargo_test "--release"
+         export RUSTFLAGS="$prev"
+         ;;
+     # FIXME: don't build anymore
+     #mips-*gnu* | mipsel-*gnu*)
+     #    export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+msa,+fp64,+mips32r5"
+     #    cargo_test "--release"
+ 	  #    ;;
+     mips64*)
+         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+msa"
+         cargo_test "--release"
+ 	      ;;
+     powerpc64*)
+         # We don't build the ppc 32-bit targets with these - these targets
+         # are mostly unsupported for now.
+         OLD_RUSTFLAGS="${RUSTFLAGS}"
+         export RUSTFLAGS="${OLD_RUSTFLAGS} -C target-feature=+altivec"
+         cargo_test "--release"
+ 
+         export RUSTFLAGS="${OLD_RUSTFLAGS} -C target-feature=+vsx"
+         cargo_test "--release"
+         ;;
+     *)
+         ;;
+ 
+ esac
+ 
+ if [ "$NORUN" != "1" ] && [ "$NOSTD" != 1 ]; then
+     # Test examples
+     (
+         cd examples
+         cargo test --target "$TARGET"
+         echo test | cargo run --release hex
+     )
+ fi
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/runtest-android.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/runtest-android.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/runtest-android.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/runtest-android.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,45 ----
+ use std::env;
+ use std::process::Command;
+ use std::path::{Path, PathBuf};
+ 
+ fn main() {
+     let args = env::args_os()
+         .skip(1)
+         .filter(|arg| arg != "--quiet")
+         .collect::<Vec<_>>();
+     assert_eq!(args.len(), 1);
+     let test = PathBuf::from(&args[0]);
+     let dst = Path::new("/data/local/tmp").join(test.file_name().unwrap());
+ 
+     let status = Command::new("adb")
+         .arg("wait-for-device")
+         .status()
+         .expect("failed to run: adb wait-for-device");
+     assert!(status.success());
+ 
+     let status = Command::new("adb")
+         .arg("push")
+         .arg(&test)
+         .arg(&dst)
+         .status()
+         .expect("failed to run: adb pushr");
+     assert!(status.success());
+ 
+     let output = Command::new("adb")
+         .arg("shell")
+         .arg(&dst)
+         .output()
+         .expect("failed to run: adb shell");
+     assert!(status.success());
+ 
+     println!("status: {}\nstdout ---\n{}\nstderr ---\n{}",
+              output.status,
+              String::from_utf8_lossy(&output.stdout),
+              String::from_utf8_lossy(&output.stderr));
+ 
+     let stdout = String::from_utf8_lossy(&output.stdout);
+     let mut lines = stdout.lines().filter(|l| l.starts_with("test result"));
+     if !lines.all(|l| l.contains("test result: ok") && l.contains("0 failed")) {
+         panic!("failed to find successful test run");
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/style.sh gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/style.sh
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/ci/style.sh	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/ci/style.sh	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,22 ----
+ #!/usr/bin/env sh
+ 
+ set -ex
+ 
+ if rustup component add rustfmt-preview ; then
+     command -v rustfmt
+     rustfmt -V
+     cargo fmt --all -- --check
+ fi
+ 
+ # if rustup component add clippy-preview ; then
+ #     cargo clippy -V
+ #     cargo clippy --all -- -D clippy::pedantic
+ # fi
+ 
+ if shellcheck --version ; then
+     shellcheck -e SC2103 ci/*.sh
+ else
+     echo "shellcheck not found"
+     exit 1
+ fi
+ 
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ [package]
+ name = "assert-instr-macro"
+ version = "0.1.0"
+ authors = ["Alex Crichton <alex@alexcrichton.com>"]
+ 
+ [lib]
+ proc-macro = true
+ test = false
+ 
+ [dependencies]
+ proc-macro2 = "1.0"
+ quote = "1.0"
+ syn = { version = "1.0", features = ["full"] }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/build.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/build.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/build.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/build.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,13 ----
+ use std::env;
+ 
+ fn main() {
+     println!("cargo:rerun-if-changed=build.rs");
+     let opt_level = env::var("OPT_LEVEL")
+         .ok()
+         .and_then(|s| s.parse().ok())
+         .unwrap_or(0);
+     let profile = env::var("PROFILE").unwrap_or(String::new());
+     if profile == "release" || opt_level >= 2 {
+         println!("cargo:rustc-cfg=optimized");
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,225 ----
+ //! Implementation of the `#[assert_instr]` macro
+ //!
+ //! This macro is used when testing the `stdarch` crate and is used to generate
+ //! test cases to assert that functions do indeed contain the instructions that
+ //! we're expecting them to contain.
+ //!
+ //! The procedural macro here is relatively simple, it simply appends a
+ //! `#[test]` function to the original token stream which asserts that the
+ //! function itself contains the relevant instruction.
+ 
+ extern crate proc_macro;
+ extern crate proc_macro2;
+ #[macro_use]
+ extern crate quote;
+ extern crate syn;
+ 
+ use proc_macro2::TokenStream;
+ use quote::ToTokens;
+ 
+ #[proc_macro_attribute]
+ pub fn assert_instr(
+     attr: proc_macro::TokenStream,
+     item: proc_macro::TokenStream,
+ ) -> proc_macro::TokenStream {
+     let invoc = match syn::parse::<Invoc>(attr) {
+         Ok(s) => s,
+         Err(e) => return e.to_compile_error().into(),
+     };
+     let item = match syn::parse::<syn::Item>(item) {
+         Ok(s) => s,
+         Err(e) => return e.to_compile_error().into(),
+     };
+     let func = match item {
+         syn::Item::Fn(ref f) => f,
+         _ => panic!("must be attached to a function"),
+     };
+ 
+     let instr = &invoc.instr;
+     let name = &func.sig.ident;
+ 
+     // Disable assert_instr for x86 targets compiled with avx enabled, which
+     // causes LLVM to generate different intrinsics that the ones we are
+     // testing for.
+     let disable_assert_instr = std::env::var("STDARCH_DISABLE_ASSERT_INSTR").is_ok();
+ 
+     // If instruction tests are disabled avoid emitting this shim at all, just
+     // return the original item without our attribute.
+     if !cfg!(optimized) || disable_assert_instr {
+         return (quote! { #item }).into();
+     }
+ 
+     let instr_str = instr
+         .replace('.', "_")
+         .replace('/', "_")
+         .replace(':', "_")
+         .replace(char::is_whitespace, "");
+     let assert_name = syn::Ident::new(&format!("assert_{}_{}", name, instr_str), name.span());
+     // These name has to be unique enough for us to find it in the disassembly later on:
+     let shim_name = syn::Ident::new(
+         &format!("stdarch_test_shim_{}_{}", name, instr_str),
+         name.span(),
+     );
+     let mut inputs = Vec::new();
+     let mut input_vals = Vec::new();
+     let ret = &func.sig.output;
+     for arg in func.sig.inputs.iter() {
+         let capture = match *arg {
+             syn::FnArg::Typed(ref c) => c,
+             ref v => panic!(
+                 "arguments must not have patterns: `{:?}`",
+                 v.clone().into_token_stream()
+             ),
+         };
+         let ident = match *capture.pat {
+             syn::Pat::Ident(ref i) => &i.ident,
+             _ => panic!("must have bare arguments"),
+         };
+         if let Some(&(_, ref tokens)) = invoc.args.iter().find(|a| *ident == a.0) {
+             input_vals.push(quote! { #tokens });
+         } else {
+             inputs.push(capture);
+             input_vals.push(quote! { #ident });
+         }
+     }
+ 
+     let attrs = func
+         .attrs
+         .iter()
+         .filter(|attr| {
+             attr.path
+                 .segments
+                 .first()
+                 .expect("attr.path.segments.first() failed")
+                 .ident
+                 .to_string()
+                 .starts_with("target")
+         })
+         .collect::<Vec<_>>();
+     let attrs = Append(&attrs);
+ 
+     // Use an ABI on Windows that passes SIMD values in registers, like what
+     // happens on Unix (I think?) by default.
+     let abi = if cfg!(windows) {
+         syn::LitStr::new("vectorcall", proc_macro2::Span::call_site())
+     } else {
+         syn::LitStr::new("C", proc_macro2::Span::call_site())
+     };
+     let shim_name_str = format!("{}{}", shim_name, assert_name);
+     let to_test = quote! {
+         #attrs
+         #[no_mangle]
+         #[inline(never)]
+         pub unsafe extern #abi fn #shim_name(#(#inputs),*) #ret {
+             // The compiler in optimized mode by default runs a pass called
+             // "mergefunc" where it'll merge functions that look identical.
+             // Turns out some intrinsics produce identical code and they're
+             // folded together, meaning that one just jumps to another. This
+             // messes up our inspection of the disassembly of this function and
+             // we're not a huge fan of that.
+             //
+             // To thwart this pass and prevent functions from being merged we
+             // generate some code that's hopefully very tight in terms of
+             // codegen but is otherwise unique to prevent code from being
+             // folded.
+             //
+             // This is avoided on Wasm32 right now since these functions aren't
+             // inlined which breaks our tests since each intrinsic looks like it
+             // calls functions. Turns out functions aren't similar enough to get
+             // merged on wasm32 anyway. This bug is tracked at
+             // rust-lang/rust#74320.
+             #[cfg(not(target_arch = "wasm32"))]
+             ::stdarch_test::_DONT_DEDUP.store(
+                 std::mem::transmute(#shim_name_str.as_bytes().as_ptr()),
+                 std::sync::atomic::Ordering::Relaxed,
+             );
+             #name(#(#input_vals),*)
+         }
+     };
+ 
+     let tokens: TokenStream = quote! {
+         #[test]
+         #[allow(non_snake_case)]
+         fn #assert_name() {
+             #to_test
+ 
+             // Make sure that the shim is not removed by leaking it to unknown
+             // code:
+             unsafe { llvm_asm!("" : : "r"(#shim_name as usize) : "memory" : "volatile") };
+ 
+             ::stdarch_test::assert(#shim_name as usize,
+                                    stringify!(#shim_name),
+                                    #instr);
+         }
+     };
+ 
+     let tokens: TokenStream = quote! {
+         #item
+         #tokens
+     };
+     tokens.into()
+ }
+ 
+ struct Invoc {
+     instr: String,
+     args: Vec<(syn::Ident, syn::Expr)>,
+ }
+ 
+ impl syn::parse::Parse for Invoc {
+     fn parse(input: syn::parse::ParseStream) -> syn::Result<Self> {
+         use syn::{ext::IdentExt, Token};
+ 
+         let mut instr = String::new();
+         while !input.is_empty() {
+             if input.parse::<Token![,]>().is_ok() {
+                 break;
+             }
+             if let Ok(ident) = syn::Ident::parse_any(input) {
+                 instr.push_str(&ident.to_string());
+                 continue;
+             }
+             if input.parse::<Token![.]>().is_ok() {
+                 instr.push_str(".");
+                 continue;
+             }
+             if let Ok(s) = input.parse::<syn::LitStr>() {
+                 instr.push_str(&s.value());
+                 continue;
+             }
+             println!("{:?}", input.cursor().token_stream());
+             return Err(input.error("expected an instruction"));
+         }
+         if instr.is_empty() {
+             return Err(input.error("expected an instruction before comma"));
+         }
+         let mut args = Vec::new();
+         while !input.is_empty() {
+             let name = input.parse::<syn::Ident>()?;
+             input.parse::<Token![=]>()?;
+             let expr = input.parse::<syn::Expr>()?;
+             args.push((name, expr));
+ 
+             if input.parse::<Token![,]>().is_err() {
+                 if !input.is_empty() {
+                     return Err(input.error("extra tokens at end"));
+                 }
+                 break;
+             }
+         }
+         Ok(Self { instr, args })
+     }
+ }
+ 
+ struct Append<T>(T);
+ 
+ impl<T> quote::ToTokens for Append<T>
+ where
+     T: Clone + IntoIterator,
+     T::Item: quote::ToTokens,
+ {
+     fn to_tokens(&self, tokens: &mut proc_macro2::TokenStream) {
+         for item in self.0.clone() {
+             item.to_tokens(tokens);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,27 ----
+ [package]
+ name = "core_arch"
+ version = "0.1.5"
+ authors = [
+     "Alex Crichton <alex@alexcrichton.com>",
+     "Andrew Gallant <jamslam@gmail.com>",
+     "Gonzalo Brito Gadeschi <gonzalobg88@gmail.com>",
+ ]
+ description = "`core::arch` - Rust's core library architecture-specific intrinsics."
+ documentation = "https://docs.rs/core_arch"
+ homepage = "https://github.com/rust-lang/stdarch"
+ repository = "https://github.com/rust-lang/stdarch"
+ readme = "README.md"
+ keywords = ["core", "simd", "arch", "intrinsics"]
+ categories = ["hardware-support", "no-std"]
+ license = "MIT/Apache-2.0"
+ build = "build.rs"
+ edition = "2018"
+ 
+ [badges]
+ is-it-maintained-issue-resolution = { repository = "rust-lang/stdarch" }
+ is-it-maintained-open-issues = { repository = "rust-lang/stdarch" }
+ maintenance = { status = "experimental" }
+ 
+ [dev-dependencies]
+ stdarch-test = { version = "0.*", path = "../stdarch-test" }
+ std_detect = { version = "0.*", path = "../std_detect" }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,201 ----
+                               Apache License
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diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-MIT gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-MIT
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-MIT	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/LICENSE-MIT	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,25 ----
+ Copyright (c) 2017 The Rust Project Developers
+ 
+ Permission is hereby granted, free of charge, to any
+ person obtaining a copy of this software and associated
+ documentation files (the "Software"), to deal in the
+ Software without restriction, including without
+ limitation the rights to use, copy, modify, merge,
+ publish, distribute, sublicense, and/or sell copies of
+ the Software, and to permit persons to whom the Software
+ is furnished to do so, subject to the following
+ conditions:
+ 
+ The above copyright notice and this permission notice
+ shall be included in all copies or substantial portions
+ of the Software.
+ 
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+ SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+ IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/README.md gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/README.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/README.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/README.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,68 ----
+ `core::arch` - Rust's core library architecture-specific intrinsics
+ =======
+ 
+ [![core_arch_crate_badge]][core_arch_crate_link] [![core_arch_docs_badge]][core_arch_docs_link]
+ 
+ 
+ The `core::arch` module implements architecture-dependent intrinsics (e.g. SIMD).
+ 
+ # Usage 
+ 
+ `core::arch` is available as part of `libcore` and it is re-exported by
+ `libstd`. Prefer using it via `core::arch` or `std::arch` than via this crate.
+ Unstable features are often available in nightly Rust via the
+ `feature(stdsimd)`.
+ 
+ Using `core::arch` via this crate requires nightly Rust, and it can (and does)
+ break often. The only cases in which you should consider using it via this crate
+ are:
+ 
+ * if you need to re-compile `core::arch` yourself, e.g., with particular
+   target-features enabled that are not enabled for `libcore`/`libstd`. Note: if
+   you need to re-compile it for a non-standard target, please prefer using
+   `xargo` and re-compiling `libcore`/`libstd` as appropriate instead of using
+   this crate.
+   
+ * using some features that might not be available even behind unstable Rust
+   features. We try to keep these to a minimum. If you need to use some of these
+   features, please open an issue so that we can expose them in nightly Rust and
+   you can use them from there.
+ 
+ # Documentation
+ 
+ * [Documentation - i686][i686]
+ * [Documentation - x86\_64][x86_64]
+ * [Documentation - arm][arm]
+ * [Documentation - aarch64][aarch64]
+ * [Documentation - powerpc][powerpc]
+ * [Documentation - powerpc64][powerpc64]
+ * [How to get started][contrib]
+ * [How to help implement intrinsics][help-implement]
+ 
+ [contrib]: https://github.com/rust-lang/stdarch/blob/master/CONTRIBUTING.md
+ [help-implement]: https://github.com/rust-lang/stdarch/issues/40
+ [i686]: https://rust-lang.github.io/stdarch/i686/core_arch/
+ [x86_64]: https://rust-lang.github.io/stdarch/x86_64/core_arch/
+ [arm]: https://rust-lang.github.io/stdarch/arm/core_arch/
+ [aarch64]: https://rust-lang.github.io/stdarch/aarch64/core_arch/
+ [powerpc]: https://rust-lang.github.io/stdarch/powerpc/core_arch/
+ [powerpc64]: https://rust-lang.github.io/stdarch/powerpc64/core_arch/
+ 
+ # License
+ 
+ `core_arch` is primarily distributed under the terms of both the MIT license and
+ the Apache License (Version 2.0), with portions covered by various BSD-like
+ licenses.
+ 
+ See LICENSE-APACHE, and LICENSE-MIT for details.
+ 
+ # Contribution
+ 
+ Unless you explicitly state otherwise, any contribution intentionally submitted
+ for inclusion in `core_arch` by you, as defined in the Apache-2.0 license,
+ shall be dual licensed as above, without any additional terms or conditions.
+ 
+ [core_arch_crate_badge]: https://img.shields.io/crates/v/core_arch.svg
+ [core_arch_crate_link]: https://crates.io/crates/core_arch
+ [core_arch_docs_badge]: https://docs.rs/core_arch/badge.svg
+ [core_arch_docs_link]: https://docs.rs/core_arch/
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/avx512f.md gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/avx512f.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/avx512f.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/avx512f.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1418 ----
+ <summary>["AVX512F"]</summary><p>
+  
+   * [x] [`_mm512_abs_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_epi32&expand=5236)
+   * [x] [`_mm512_abs_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_epi64&expand=5236)
+   * [x] [`_mm512_abs_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_pd&expand=5236)
+   * [x] [`_mm512_abs_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ps&expand=5236)
+   * [x] [`_mm512_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_epi32&expand=5236)
+   * [x] [`_mm512_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_epi64&expand=5236)
+   * [x] [`_mm512_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_pd&expand=5236)
+   * [x] [`_mm512_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_ps&expand=5236)
+   * [x] [`_mm512_add_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_round_pd&expand=5236)
+   * [x] [`_mm512_add_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_round_ps&expand=5236)
+   * [ ] [`_mm512_alignr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_alignr_epi32&expand=5236)
+   * [ ] [`_mm512_alignr_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_alignr_epi64&expand=5236)
+   * [x] [`_mm512_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_and_epi32&expand=5236)
+   * [x] [`_mm512_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_and_epi64&expand=5236)
+   * [x] [`_mm512_and_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_and_si512&expand=5236)
+   * [x] [`_mm512_andnot_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_andnot_epi32&expand=5236)
+   * [x] [`_mm512_andnot_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_andnot_epi64&expand=5236)
+   * [x] [`_mm512_andnot_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_andnot_si512&expand=5236)
+   * [x] [`_mm512_broadcast_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_f32x4&expand=5236)
+   * [x] [`_mm512_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_f64x4&expand=5236)
+   * [x] [`_mm512_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_i32x4&expand=5236)
+   * [x] [`_mm512_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_i64x4&expand=5236)
+   * [x] [`_mm512_broadcastd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastd_epi32&expand=5236)
+   * [x] [`_mm512_broadcastq_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastq_epi64&expand=5236)
+   * [x] [`_mm512_broadcastsd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastsd_pd&expand=5236)
+   * [x] [`_mm512_broadcastss_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastss_ps&expand=5236)
+   * [x] [`_mm512_castpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd128_pd512&expand=5236)
+   * [x] [`_mm512_castpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd256_pd512&expand=5236)
+   * [x] [`_mm512_castpd512_pd128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd512_pd128&expand=5236)
+   * [x] [`_mm512_castpd512_pd256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd512_pd256&expand=5236)
+   * [x] [`_mm512_castpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ps&expand=5236)
+   * [x] [`_mm512_castpd_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_si512&expand=5236)
+   * [x] [`_mm512_castps128_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps128_ps512&expand=5236)
+   * [x] [`_mm512_castps256_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps256_ps512&expand=5236)
+   * [x] [`_mm512_castps512_ps128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps512_ps128&expand=5236)
+   * [x] [`_mm512_castps512_ps256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps512_ps256&expand=5236)
+   * [x] [`_mm512_castps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_pd&expand=5236)
+   * [x] [`_mm512_castps_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_si512&expand=5236)
+   * [x] [`_mm512_castsi128_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi128_si512&expand=5236)
+   * [x] [`_mm512_castsi256_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi256_si512&expand=5236)
+   * [x] [`_mm512_castsi512_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_pd&expand=5236)
+   * [x] [`_mm512_castsi512_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ps&expand=5236)
+   * [x] [`_mm512_castsi512_si128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_si128&expand=5236)
+   * [x] [`_mm512_castsi512_si256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_si256&expand=5236)
+   * [x] [`_mm512_cmp_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmp_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmp_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmp_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmp_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_pd_mask&expand=5236)
+   * [x] [`_mm512_cmp_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_ps_mask&expand=5236)
+   * [x] [`_mm512_cmp_round_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_round_pd_mask&expand=5236)
+   * [x] [`_mm512_cmp_round_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_round_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpeq_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpeq_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmpeq_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpeq_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmpeq_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpeq_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmpeq_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpeq_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmpeq_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpeq_pd_mask&expand=5236)
+   * [x] [`_mm512_cmpeq_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpeq_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpge_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpge_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmpge_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpge_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmpge_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpge_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmpge_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpge_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmpgt_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpgt_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmpgt_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpgt_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmpgt_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpgt_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmpgt_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpgt_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmple_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmple_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmple_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmple_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmple_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmple_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmple_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmple_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmple_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmple_pd_mask&expand=5236)
+   * [x] [`_mm512_cmple_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmple_ps_mask&expand=5236)
+   * [x] [`_mm512_cmplt_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmplt_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmplt_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmplt_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmplt_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmplt_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmplt_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmplt_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmplt_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmplt_pd_mask&expand=5236)
+   * [x] [`_mm512_cmplt_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmplt_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpneq_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpneq_epi32_mask&expand=5236)
+   * [x] [`_mm512_cmpneq_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpneq_epi64_mask&expand=5236)
+   * [x] [`_mm512_cmpneq_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpneq_epu32_mask&expand=5236)
+   * [x] [`_mm512_cmpneq_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpneq_epu64_mask&expand=5236)
+   * [x] [`_mm512_cmpneq_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpneq_pd_mask&expand=5236)
+   * [x] [`_mm512_cmpneq_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpneq_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpnle_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpnle_pd_mask&expand=5236)
+   * [x] [`_mm512_cmpnle_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpnle_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpnlt_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpnlt_pd_mask&expand=5236)
+   * [x] [`_mm512_cmpnlt_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpnlt_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpord_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpord_pd_mask&expand=5236)
+   * [x] [`_mm512_cmpord_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpord_ps_mask&expand=5236)
+   * [x] [`_mm512_cmpunord_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpunord_pd_mask&expand=5236)
+   * [x] [`_mm512_cmpunord_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmpunord_ps_mask&expand=5236)
+   * [ ] [`_mm512_cvt_roundepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepi32_ps&expand=5236)
+   * [ ] [`_mm512_cvt_roundepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepu32_ps&expand=5236)
+   * [ ] [`_mm512_cvt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_epi32&expand=5236)
+   * [ ] [`_mm512_cvt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_epu32&expand=5236)
+   * [ ] [`_mm512_cvt_roundpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_ps&expand=5236)
+   * [ ] [`_mm512_cvt_roundph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_ps&expand=5236)
+   * [x] [`_mm512_cvt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_epi32&expand=5236)
+   * [x] [`_mm512_cvt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_epu32&expand=5236)
+   * [x] [`_mm512_cvt_roundps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_pd&expand=5236)
+   * [ ] [`_mm512_cvt_roundps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_ph&expand=5236)
+   * [ ] [`_mm512_cvtepi16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi16_epi32&expand=5236)
+   * [ ] [`_mm512_cvtepi16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi16_epi64&expand=5236)
+   * [ ] [`_mm512_cvtepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_epi16&expand=5236)
+   * [ ] [`_mm512_cvtepi32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_epi64&expand=5236)
+   * [ ] [`_mm512_cvtepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_epi8&expand=5236)
+   * [ ] [`_mm512_cvtepi32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_pd&expand=5236)
+   * [ ] [`_mm512_cvtepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_ps&expand=5236)
+   * [ ] [`_mm512_cvtepi32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32lo_pd&expand=5236)
+   * [ ] [`_mm512_cvtepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_epi16&expand=5236)
+   * [ ] [`_mm512_cvtepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_epi32&expand=5236)
+   * [ ] [`_mm512_cvtepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_epi8&expand=5236)
+   * [ ] [`_mm512_cvtepi8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi8_epi32&expand=5236)
+   * [ ] [`_mm512_cvtepi8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi8_epi64&expand=5236)
+   * [ ] [`_mm512_cvtepu16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu16_epi32&expand=5236)
+   * [ ] [`_mm512_cvtepu16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu16_epi64&expand=5236)
+   * [ ] [`_mm512_cvtepu32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_epi64&expand=5236)
+   * [ ] [`_mm512_cvtepu32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_pd&expand=5236)
+   * [ ] [`_mm512_cvtepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_ps&expand=5236)
+   * [ ] [`_mm512_cvtepu32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32lo_pd&expand=5236)
+   * [ ] [`_mm512_cvtepu8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu8_epi32&expand=5236)
+   * [ ] [`_mm512_cvtepu8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu8_epi64&expand=5236)
+   * [x] [`_mm512_cvtpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_epi32&expand=5236)
+   * [x] [`_mm512_cvtpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_epu32&expand=5236)
+   * [ ] [`_mm512_cvtpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_ps&expand=5236)
+   * [ ] [`_mm512_cvtpd_pslo`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_pslo&expand=5236)
+   * [ ] [`_mm512_cvtph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_ps&expand=5236)
+   * [x] [`_mm512_cvtps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_epi32&expand=5236)
+   * [x] [`_mm512_cvtps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_epu32&expand=5236)
+   * [ ] [`_mm512_cvtps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_pd&expand=5236)
+   * [ ] [`_mm512_cvtps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_ph&expand=5236)
+   * [ ] [`_mm512_cvtpslo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpslo_pd&expand=5236)
+   * [ ] [`_mm512_cvtsepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi32_epi16&expand=5236)
+   * [ ] [`_mm512_cvtsepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi32_epi8&expand=5236)
+   * [ ] [`_mm512_cvtsepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi64_epi16&expand=5236)
+   * [ ] [`_mm512_cvtsepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi64_epi32&expand=5236)
+   * [ ] [`_mm512_cvtsepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi64_epi8&expand=5236)
+   * [x] [`_mm512_cvtt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundpd_epi32&expand=5236)
+   * [x] [`_mm512_cvtt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundpd_epu32&expand=5236)
+   * [x] [`_mm512_cvtt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundps_epi32&expand=5236)
+   * [x] [`_mm512_cvtt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundps_epu32&expand=5236)
+   * [x] [`_mm512_cvttpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttpd_epi32&expand=5236)
+   * [x] [`_mm512_cvttpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttpd_epu32&expand=5236)
+   * [x] [`_mm512_cvttps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttps_epi32&expand=5236)
+   * [x] [`_mm512_cvttps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttps_epu32&expand=5236)
+   * [ ] [`_mm512_cvtusepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi32_epi16&expand=5236)
+   * [ ] [`_mm512_cvtusepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi32_epi8&expand=5236)
+   * [ ] [`_mm512_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi16&expand=5236)
+   * [ ] [`_mm512_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi32&expand=5236)
+   * [ ] [`_mm512_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi8&expand=5236)
+   * [x] [`_mm512_div_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_pd&expand=5236)
+   * [x] [`_mm512_div_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_ps&expand=5236)
+   * [x] [`_mm512_div_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_round_pd&expand=5236)
+   * [x] [`_mm512_div_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_round_ps&expand=5236)
+   * [x] [`_mm512_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf32x4_ps&expand=5236)
+   * [ ] [`_mm512_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf64x4_pd&expand=5236)
+   * [ ] [`_mm512_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti32x4_epi32&expand=5236)
+   * [ ] [`_mm512_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti64x4_epi64&expand=5236)
+   * [ ] [`_mm512_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_pd&expand=5236)
+   * [ ] [`_mm512_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_ps&expand=5236)
+   * [ ] [`_mm512_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_pd&expand=5236)
+   * [ ] [`_mm512_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_ps&expand=5236)
+   * [x] [`_mm512_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_pd&expand=5236)
+   * [x] [`_mm512_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_ps&expand=5236)
+   * [x] [`_mm512_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_round_pd&expand=5236)
+   * [x] [`_mm512_fmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_round_ps&expand=5236)
+   * [x] [`_mm512_fmaddsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmaddsub_pd&expand=5236)
+   * [x] [`_mm512_fmaddsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmaddsub_ps&expand=5236)
+   * [x] [`_mm512_fmaddsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmaddsub_round_pd&expand=5236)
+   * [x] [`_mm512_fmaddsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmaddsub_round_ps&expand=5236)
+   * [x] [`_mm512_fmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsub_pd&expand=5236)
+   * [x] [`_mm512_fmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsub_ps&expand=5236)
+   * [x] [`_mm512_fmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsub_round_pd&expand=5236)
+   * [x] [`_mm512_fmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsub_round_ps&expand=5236)
+   * [x] [`_mm512_fmsubadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsubadd_pd&expand=5236)
+   * [x] [`_mm512_fmsubadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsubadd_ps&expand=5236)
+   * [x] [`_mm512_fmsubadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsubadd_round_pd&expand=5236)
+   * [x] [`_mm512_fmsubadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmsubadd_round_ps&expand=5236)
+   * [x] [`_mm512_fnmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmadd_pd&expand=5236)
+   * [x] [`_mm512_fnmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmadd_ps&expand=5236)
+   * [x] [`_mm512_fnmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmadd_round_pd&expand=5236)
+   * [x] [`_mm512_fnmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmadd_round_ps&expand=5236)
+   * [x] [`_mm512_fnmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmsub_pd&expand=5236)
+   * [x] [`_mm512_fnmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmsub_ps&expand=5236)
+   * [x] [`_mm512_fnmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmsub_round_pd&expand=5236)
+   * [x] [`_mm512_fnmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fnmsub_round_ps&expand=5236)
+   * [x] [`_mm512_getexp_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getexp_pd&expand=5236)
+   * [x] [`_mm512_getexp_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getexp_ps&expand=5236)
+   * [x] [`_mm512_getexp_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getexp_round_pd&expand=5236)
+   * [x] [`_mm512_getexp_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getexp_round_ps&expand=5236)
+   * [x] [`_mm512_getmant_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_pd&expand=5236)
+   * [x] [`_mm512_getmant_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_ps&expand=5236)
+   * [x] [`_mm512_getmant_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_round_pd&expand=5236)
+   * [x] [`_mm512_getmant_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_round_ps&expand=5236)
+   * [ ] [`_mm512_i32extgather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extgather_epi32&expand=5236)
+   * [ ] [`_mm512_i32extgather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extgather_ps&expand=5236)
+   * [ ] [`_mm512_i32extscatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extscatter_epi32&expand=5236)
+   * [ ] [`_mm512_i32extscatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32extscatter_ps&expand=5236)
+   * [x] [`_mm512_i32gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_epi32&expand=5236)
+   * [x] [`_mm512_i32gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_epi64&expand=5236)
+   * [x] [`_mm512_i32gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_pd&expand=5236)
+   * [x] [`_mm512_i32gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_ps&expand=5236)
+   * [ ] [`_mm512_i32loextgather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextgather_epi64&expand=5236)
+   * [ ] [`_mm512_i32loextgather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextgather_pd&expand=5236)
+   * [ ] [`_mm512_i32loextscatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextscatter_epi64&expand=5236)
+   * [ ] [`_mm512_i32loextscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loextscatter_pd&expand=5236)
+   * [ ] [`_mm512_i32logather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32logather_epi64&expand=5236)
+   * [ ] [`_mm512_i32logather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32logather_pd&expand=5236)
+   * [ ] [`_mm512_i32loscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loscatter_pd&expand=5236)
+   * [x] [`_mm512_i32scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_epi32&expand=5236)
+   * [x] [`_mm512_i32scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_epi64&expand=5236)
+   * [x] [`_mm512_i32scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_pd&expand=5236)
+   * [x] [`_mm512_i32scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_ps&expand=5236)
+   * [x] [`_mm512_i64gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_epi32&expand=5236)
+   * [x] [`_mm512_i64gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_epi64&expand=5236)
+   * [x] [`_mm512_i64gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_pd&expand=5236)
+   * [x] [`_mm512_i64gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_ps&expand=5236)
+   * [x] [`_mm512_i64scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi32&expand=5236)
+   * [x] [`_mm512_i64scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi64&expand=5236)
+   * [x] [`_mm512_i64scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_pd&expand=5236)
+   * [x] [`_mm512_i64scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_ps&expand=5236)
+   * [x] [`_mm512_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf32x4&expand=5236)
+   * [x] [`_mm512_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf64x4&expand=5236)
+   * [x] [`_mm512_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti32x4&expand=5236)
+   * [x] [`_mm512_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti64x4&expand=5236)
+   * [ ] [`_mm512_int2mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_int2mask&expand=5236)
+   * [x] [`_mm512_kand`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kand&expand=5236)
+   * [x] [`_mm512_kandn`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kandn&expand=5236)
+   * [x] [`_mm512_kmov`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kmov&expand=5236)
+   * [x] [`_mm512_knot`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_knot&expand=5236)
+   * [x] [`_mm512_kor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kor&expand=5236)
+   * [ ] [`_mm512_kortestc`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kortestc&expand=5236)
+   * [ ] [`_mm512_kortestz`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kortestz&expand=5236)
+   * [ ] [`_mm512_kunpackb`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kunpackb&expand=5236)
+   * [x] [`_mm512_kxnor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kxnor&expand=5236)
+   * [x] [`_mm512_kxor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kxor&expand=5236)
+   * [ ] [`_mm512_load_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_epi32&expand=5236)
+   * [ ] [`_mm512_load_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_epi64&expand=5236)
+   * [ ] [`_mm512_load_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_pd&expand=5236)
+   * [ ] [`_mm512_load_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_ps&expand=5236)
+   * [ ] [`_mm512_load_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_si512&expand=5236)
+   * [x] [`_mm512_loadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_pd&expand=5236)
+   * [x] [`_mm512_loadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_ps&expand=5236)
+   * [ ] [`_mm512_loadu_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_si512&expand=5236)
+   * [x] [`_mm512_mask2_permutex2var_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_epi32&expand=5236)
+   * [x] [`_mm512_mask2_permutex2var_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_epi64&expand=5236)
+   * [x] [`_mm512_mask2_permutex2var_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_pd&expand=5236)
+   * [x] [`_mm512_mask2_permutex2var_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_ps&expand=5236)
+   * [ ] [`_mm512_mask2int`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2int&expand=5236)
+   * [x] [`_mm512_mask3_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_round_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_round_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmaddsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmaddsub_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmaddsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmaddsub_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmaddsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmaddsub_round_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmaddsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmaddsub_round_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsub_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsub_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsub_round_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsub_round_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmsubadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsubadd_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmsubadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsubadd_ps&expand=5236)
+   * [x] [`_mm512_mask3_fmsubadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsubadd_round_pd&expand=5236)
+   * [x] [`_mm512_mask3_fmsubadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmsubadd_round_ps&expand=5236)
+   * [x] [`_mm512_mask3_fnmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmadd_pd&expand=5236)
+   * [x] [`_mm512_mask3_fnmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmadd_ps&expand=5236)
+   * [x] [`_mm512_mask3_fnmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmadd_round_pd&expand=5236)
+   * [x] [`_mm512_mask3_fnmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmadd_round_ps&expand=5236)
+   * [x] [`_mm512_mask3_fnmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_pd&expand=5236)
+   * [x] [`_mm512_mask3_fnmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_ps&expand=5236)
+   * [x] [`_mm512_mask3_fnmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_round_pd&expand=5236)
+   * [x] [`_mm512_mask3_fnmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_round_ps&expand=5236)
+   * [x] [`_mm512_mask_abs_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_epi32&expand=5236)
+   * [x] [`_mm512_mask_abs_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_epi64&expand=5236)
+   * [x] [`_mm512_mask_abs_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_pd&expand=5236)
+   * [x] [`_mm512_mask_abs_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_ps&expand=5236)
+   * [x] [`_mm512_mask_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_epi32&expand=5236)
+   * [x] [`_mm512_mask_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_epi64&expand=5236)
+   * [x] [`_mm512_mask_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_pd&expand=5236)
+   * [x] [`_mm512_mask_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_ps&expand=5236)
+   * [x] [`_mm512_mask_add_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_round_pd&expand=5236)
+   * [x] [`_mm512_mask_add_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_round_ps&expand=5236)
+   * [ ] [`_mm512_mask_alignr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_alignr_epi32&expand=5236)
+   * [ ] [`_mm512_mask_alignr_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_alignr_epi64&expand=5236)
+   * [x] [`_mm512_mask_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_and_epi32&expand=5236)
+   * [x] [`_mm512_mask_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_and_epi64&expand=5236)
+   * [x] [`_mm512_mask_andnot_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_andnot_epi32&expand=5236)
+   * [x] [`_mm512_mask_andnot_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_andnot_epi64&expand=5236)
+   * [x] [`_mm512_mask_blend_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_epi32&expand=5236)
+   * [x] [`_mm512_mask_blend_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_epi64&expand=5236)
+   * [x] [`_mm512_mask_blend_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_pd&expand=5236)
+   * [x] [`_mm512_mask_blend_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ps&expand=5236)
+   * [x] [`_mm512_mask_broadcast_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_f32x4&expand=5236)
+   * [x] [`_mm512_mask_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_f64x4&expand=5236)
+   * [x] [`_mm512_mask_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_i32x4&expand=5236)
+   * [x] [`_mm512_mask_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_i64x4&expand=5236)
+   * [x] [`_mm512_mask_broadcastd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastd_epi32&expand=5236)
+   * [x] [`_mm512_mask_broadcastq_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastq_epi64&expand=5236)
+   * [x] [`_mm512_mask_broadcastsd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastsd_pd&expand=5236)
+   * [x] [`_mm512_mask_broadcastss_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastss_ps&expand=5236)
+   * [x] [`_mm512_mask_cmp_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_round_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_round_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmp_round_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_round_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpeq_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpeq_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpeq_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpeq_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpeq_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpeq_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpeq_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpeq_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpeq_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpeq_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpeq_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpeq_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpge_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpge_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpge_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpge_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpge_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpge_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpge_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpge_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpgt_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpgt_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpgt_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpgt_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpgt_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpgt_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpgt_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpgt_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmple_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmple_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmple_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmple_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmple_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmple_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmple_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmple_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmple_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmple_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmple_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmple_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmplt_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmplt_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmplt_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmplt_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmplt_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmplt_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmplt_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmplt_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmplt_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmplt_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmplt_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmplt_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpneq_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpneq_epi32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpneq_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpneq_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpneq_epu32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpneq_epu32_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpneq_epu64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpneq_epu64_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpneq_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpneq_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpneq_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpneq_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpnle_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpnle_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpnle_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpnle_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpnlt_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpnlt_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpnlt_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpnlt_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpord_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpord_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpord_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpord_ps_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpunord_pd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpunord_pd_mask&expand=5236)
+   * [x] [`_mm512_mask_cmpunord_ps_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmpunord_ps_mask&expand=5236)
+   * [ ] [`_mm512_mask_compress_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_epi32&expand=5236)
+   * [ ] [`_mm512_mask_compress_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_epi64&expand=5236)
+   * [ ] [`_mm512_mask_compress_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_pd&expand=5236)
+   * [ ] [`_mm512_mask_compress_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_ps&expand=5236)
+   * [ ] [`_mm512_mask_compressstoreu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_compressstoreu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_epi64&expand=5236)
+   * [ ] [`_mm512_mask_compressstoreu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_pd&expand=5236)
+   * [ ] [`_mm512_mask_compressstoreu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepi32_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepu32_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_epu32&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_ps&expand=5236)
+   * [x] [`_mm512_mask_cvt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_epu32&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvt_roundps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_ph&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi16_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi16_epi64&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_epi64&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_storeu_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_storeu_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32lo_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_storeu_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_storeu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_storeu_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi8_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtepi8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi8_epi64&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu16_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu16_epi64&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_epi64&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32lo_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu8_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtepu8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu8_epi64&expand=5236)
+   * [x] [`_mm512_mask_cvtpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvtpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_epu32&expand=5236)
+   * [ ] [`_mm512_mask_cvtpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_ps&expand=5236)
+   * [ ] [`_mm512_mask_cvtpd_pslo`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_pslo&expand=5236)
+   * [ ] [`_mm512_mask_cvtph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_ps&expand=5236)
+   * [x] [`_mm512_mask_cvtps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvtps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_epu32&expand=5236)
+   * [x] [`_mm512_mask_cvtps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvtps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_ph&expand=5236)
+   * [ ] [`_mm512_mask_cvtpslo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpslo_pd&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi32_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_storeu_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi32_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_storeu_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_storeu_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_storeu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtsepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_storeu_epi8&expand=5236)
+   * [x] [`_mm512_mask_cvtt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundpd_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvtt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundpd_epu32&expand=5236)
+   * [x] [`_mm512_mask_cvtt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundps_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvtt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundps_epu32&expand=5236)
+   * [x] [`_mm512_mask_cvttpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttpd_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvttpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttpd_epu32&expand=5236)
+   * [x] [`_mm512_mask_cvttps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttps_epi32&expand=5236)
+   * [x] [`_mm512_mask_cvttps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttps_epu32&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi32_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_storeu_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi32_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_storeu_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_epi8&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi16&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_cvtusepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi8&expand=5236)
+   * [x] [`_mm512_mask_div_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_pd&expand=5236)
+   * [x] [`_mm512_mask_div_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_ps&expand=5236)
+   * [x] [`_mm512_mask_div_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_round_pd&expand=5236)
+   * [x] [`_mm512_mask_div_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_round_ps&expand=5236)
+   * [ ] [`_mm512_mask_expand_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_epi32&expand=5236)
+   * [ ] [`_mm512_mask_expand_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_epi64&expand=5236)
+   * [ ] [`_mm512_mask_expand_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_pd&expand=5236)
+   * [ ] [`_mm512_mask_expand_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_ps&expand=5236)
+   * [ ] [`_mm512_mask_expandloadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_expandloadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_epi64&expand=5236)
+   * [ ] [`_mm512_mask_expandloadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_pd&expand=5236)
+   * [ ] [`_mm512_mask_expandloadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_ps&expand=5236)
+   * [ ] [`_mm512_mask_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extractf32x4_ps&expand=5236)
+   * [ ] [`_mm512_mask_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extractf64x4_pd&expand=5236)
+   * [ ] [`_mm512_mask_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti32x4_epi32&expand=5236)
+   * [ ] [`_mm512_mask_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti64x4_epi64&expand=5236)
+   * [ ] [`_mm512_mask_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_pd&expand=5236)
+   * [ ] [`_mm512_mask_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_ps&expand=5236)
+   * [ ] [`_mm512_mask_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_pd&expand=5236)
+   * [ ] [`_mm512_mask_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_ps&expand=5236)
+   * [x] [`_mm512_mask_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_pd&expand=5236)
+   * [x] [`_mm512_mask_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_ps&expand=5236)
+   * [x] [`_mm512_mask_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_round_pd&expand=5236)
+   * [x] [`_mm512_mask_fmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_round_ps&expand=5236)
+   * [x] [`_mm512_mask_fmaddsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmaddsub_pd&expand=5236)
+   * [x] [`_mm512_mask_fmaddsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmaddsub_ps&expand=5236)
+   * [x] [`_mm512_mask_fmaddsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmaddsub_round_pd&expand=5236)
+   * [x] [`_mm512_mask_fmaddsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmaddsub_round_ps&expand=5236)
+   * [x] [`_mm512_mask_fmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsub_pd&expand=5236)
+   * [x] [`_mm512_mask_fmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsub_ps&expand=5236)
+   * [x] [`_mm512_mask_fmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsub_round_pd&expand=5236)
+   * [x] [`_mm512_mask_fmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsub_round_ps&expand=5236)
+   * [x] [`_mm512_mask_fmsubadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsubadd_pd&expand=5236)
+   * [x] [`_mm512_mask_fmsubadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsubadd_ps&expand=5236)
+   * [x] [`_mm512_mask_fmsubadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsubadd_round_pd&expand=5236)
+   * [x] [`_mm512_mask_fmsubadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmsubadd_round_ps&expand=5236)
+   * [x] [`_mm512_mask_fnmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmadd_pd&expand=5236)
+   * [x] [`_mm512_mask_fnmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmadd_ps&expand=5236)
+   * [x] [`_mm512_mask_fnmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmadd_round_pd&expand=5236)
+   * [x] [`_mm512_mask_fnmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmadd_round_ps&expand=5236)
+   * [x] [`_mm512_mask_fnmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmsub_pd&expand=5236)
+   * [x] [`_mm512_mask_fnmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmsub_ps&expand=5236)
+   * [x] [`_mm512_mask_fnmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmsub_round_pd&expand=5236)
+   * [x] [`_mm512_mask_fnmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fnmsub_round_ps&expand=5236)
+   * [x] [`_mm512_mask_getexp_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getexp_pd&expand=5236)
+   * [x] [`_mm512_mask_getexp_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getexp_ps&expand=5236)
+   * [x] [`_mm512_mask_getexp_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getexp_round_pd&expand=5236)
+   * [x] [`_mm512_mask_getexp_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getexp_round_ps&expand=5236)
+   * [x] [`_mm512_mask_getmant_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_pd&expand=5236)
+   * [x] [`_mm512_mask_getmant_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_ps&expand=5236)
+   * [x] [`_mm512_mask_getmant_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_round_pd&expand=5236)
+   * [x] [`_mm512_mask_getmant_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_round_ps&expand=5236)
+   * [ ] [`_mm512_mask_i32extgather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32extgather_epi32&expand=5236)
+   * [ ] [`_mm512_mask_i32extgather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32extgather_ps&expand=5236)
+   * [ ] [`_mm512_mask_i32extscatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32extscatter_epi32&expand=5236)
+   * [ ] [`_mm512_mask_i32extscatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32extscatter_ps&expand=5236)
+   * [x] [`_mm512_mask_i32gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_epi32&expand=5236)
+   * [x] [`_mm512_mask_i32gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_epi64&expand=5236)
+   * [x] [`_mm512_mask_i32gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_pd&expand=5236)
+   * [x] [`_mm512_mask_i32gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_ps&expand=5236)
+   * [ ] [`_mm512_mask_i32loextgather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextgather_epi64&expand=5236)
+   * [ ] [`_mm512_mask_i32loextgather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextgather_pd&expand=5236)
+   * [ ] [`_mm512_mask_i32loextscatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextscatter_epi64&expand=5236)
+   * [ ] [`_mm512_mask_i32loextscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loextscatter_pd&expand=5236)
+   * [ ] [`_mm512_mask_i32logather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32logather_epi64&expand=5236)
+   * [ ] [`_mm512_mask_i32logather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32logather_pd&expand=5236)
+   * [ ] [`_mm512_mask_i32loscatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32loscatter_pd&expand=5236)
+   * [x] [`_mm512_mask_i32scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_epi32&expand=5236)
+   * [x] [`_mm512_mask_i32scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_epi64&expand=5236)
+   * [x] [`_mm512_mask_i32scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_pd&expand=5236)
+   * [x] [`_mm512_mask_i32scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_ps&expand=5236)
+   * [x] [`_mm512_mask_i64gather_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_epi32&expand=5236)
+   * [x] [`_mm512_mask_i64gather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_epi64&expand=5236)
+   * [x] [`_mm512_mask_i64gather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_pd&expand=5236)
+   * [x] [`_mm512_mask_i64gather_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_ps&expand=5236)
+   * [x] [`_mm512_mask_i64scatter_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_epi32&expand=5236)
+   * [x] [`_mm512_mask_i64scatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_epi64&expand=5236)
+   * [x] [`_mm512_mask_i64scatter_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_pd&expand=5236)
+   * [x] [`_mm512_mask_i64scatter_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_ps&expand=5236)
+   * [x] [`_mm512_mask_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_insertf32x4&expand=5236)
+   * [x] [`_mm512_mask_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_insertf64x4&expand=5236)
+   * [x] [`_mm512_mask_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_inserti32x4&expand=5236)
+   * [x] [`_mm512_mask_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_inserti64x4&expand=5236)
+   * [ ] [`_mm512_mask_load_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_epi32&expand=5236)
+   * [ ] [`_mm512_mask_load_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_epi64&expand=5236)
+   * [ ] [`_mm512_mask_load_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_pd&expand=5236)
+   * [ ] [`_mm512_mask_load_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_ps&expand=5236)
+   * [ ] [`_mm512_mask_loadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_loadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_epi64&expand=5236)
+   * [ ] [`_mm512_mask_loadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_pd&expand=5236)
+   * [ ] [`_mm512_mask_loadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_ps&expand=5236)
+   * [x] [`_mm512_mask_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_epi32&expand=5236)
+   * [x] [`_mm512_mask_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_epi64&expand=5236)
+   * [x] [`_mm512_mask_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_epu32&expand=5236)
+   * [x] [`_mm512_mask_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_epu64&expand=5236)
+   * [x] [`_mm512_mask_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_pd&expand=5236)
+   * [x] [`_mm512_mask_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_ps&expand=5236)
+   * [x] [`_mm512_mask_max_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_round_pd&expand=5236)
+   * [x] [`_mm512_mask_max_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_max_round_ps&expand=5236)
+   * [x] [`_mm512_mask_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_epi32&expand=5236)
+   * [x] [`_mm512_mask_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_epi64&expand=5236)
+   * [x] [`_mm512_mask_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_epu32&expand=5236)
+   * [x] [`_mm512_mask_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_epu64&expand=5236)
+   * [x] [`_mm512_mask_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_pd&expand=5236)
+   * [x] [`_mm512_mask_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_ps&expand=5236)
+   * [x] [`_mm512_mask_min_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_round_pd&expand=5236)
+   * [x] [`_mm512_mask_min_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_round_ps&expand=5236)
+   * [ ] [`_mm512_mask_mov_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_epi32&expand=5236)
+   * [ ] [`_mm512_mask_mov_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_epi64&expand=5236)
+   * [ ] [`_mm512_mask_mov_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_pd&expand=5236)
+   * [ ] [`_mm512_mask_mov_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_ps&expand=5236)
+   * [x] [`_mm512_mask_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_movedup_pd&expand=5236)
+   * [x] [`_mm512_mask_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_movehdup_ps&expand=5236)
+   * [x] [`_mm512_mask_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_moveldup_ps&expand=5236)
+   * [x] [`_mm512_mask_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_epi32&expand=5236)
+   * [x] [`_mm512_mask_mul_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_epu32&expand=5236)
+   * [x] [`_mm512_mask_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_pd&expand=5236)
+   * [x] [`_mm512_mask_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_ps&expand=5236)
+   * [x] [`_mm512_mask_mul_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_round_pd&expand=5236)
+   * [x] [`_mm512_mask_mul_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_round_ps&expand=5236)
+   * [x] [`_mm512_mask_mullo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mullo_epi32&expand=5236)
+   * [x] [`_mm512_mask_mullox_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mullox_epi64&expand=5236)
+   * [x] [`_mm512_mask_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_or_epi32&expand=5236)
+   * [x] [`_mm512_mask_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_or_epi64&expand=5236)
+   * [x] [`_mm512_mask_permute_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permute_pd&expand=5236)
+   * [x] [`_mm512_mask_permute_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permute_ps&expand=5236)
+   * [x] [`_mm512_mask_permutevar_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutevar_epi32&expand=5236)
+   * [x] [`_mm512_mask_permutevar_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutevar_pd&expand=5236)
+   * [x] [`_mm512_mask_permutevar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutevar_ps&expand=5236)
+   * [x] [`_mm512_mask_permutex2var_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex2var_epi32&expand=5236)
+   * [x] [`_mm512_mask_permutex2var_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex2var_epi64&expand=5236)
+   * [x] [`_mm512_mask_permutex2var_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex2var_pd&expand=5236)
+   * [x] [`_mm512_mask_permutex2var_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex2var_ps&expand=5236)
+   * [x] [`_mm512_mask_permutex_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex_epi64&expand=5236)
+   * [x] [`_mm512_mask_permutex_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex_pd&expand=5236)
+   * [x] [`_mm512_mask_permutexvar_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutexvar_epi32&expand=5236)
+   * [x] [`_mm512_mask_permutexvar_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutexvar_epi64&expand=5236)
+   * [x] [`_mm512_mask_permutexvar_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutexvar_pd&expand=5236)
+   * [x] [`_mm512_mask_permutexvar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutexvar_ps&expand=5236)
+   * [x] [`_mm512_mask_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp14_pd&expand=5236)
+   * [x] [`_mm512_mask_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp14_ps&expand=5236)
+   * [ ] [`_mm512_mask_reduce_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_pd&expand=5236)
+   * [ ] [`_mm512_mask_reduce_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_ps&expand=5236)
+   * [ ] [`_mm512_mask_reduce_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_pd&expand=5236)
+   * [ ] [`_mm512_mask_reduce_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_ps&expand=5236)
+   * [ ] [`_mm512_mask_reduce_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_pd&expand=5236)
+   * [ ] [`_mm512_mask_reduce_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_ps&expand=5236)
+   * [ ] [`_mm512_mask_reduce_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi64&expand=5236)
+   * [ ] [`_mm512_mask_reduce_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_pd&expand=5236)
+   * [ ] [`_mm512_mask_reduce_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_ps&expand=5236)
+   * [ ] [`_mm512_mask_reduce_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi32&expand=5236)
+   * [ ] [`_mm512_mask_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi64&expand=5236)
+   * [x] [`_mm512_mask_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rol_epi32&expand=5236)
+   * [x] [`_mm512_mask_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rol_epi64&expand=5236)
+   * [x] [`_mm512_mask_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rolv_epi32&expand=5236)
+   * [x] [`_mm512_mask_rolv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rolv_epi64&expand=5236)
+   * [x] [`_mm512_mask_ror_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ror_epi32&expand=5236)
+   * [x] [`_mm512_mask_ror_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ror_epi64&expand=5236)
+   * [x] [`_mm512_mask_rorv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rorv_epi32&expand=5236)
+   * [x] [`_mm512_mask_rorv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rorv_epi64&expand=5236)
+   * [ ] [`_mm512_mask_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_pd&expand=5236)
+   * [ ] [`_mm512_mask_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_ps&expand=5236)
+   * [ ] [`_mm512_mask_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_pd&expand=5236)
+   * [ ] [`_mm512_mask_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_ps&expand=5236)
+   * [x] [`_mm512_mask_rsqrt14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rsqrt14_pd&expand=5236)
+   * [x] [`_mm512_mask_rsqrt14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rsqrt14_ps&expand=5236)
+   * [ ] [`_mm512_mask_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_pd&expand=5236)
+   * [ ] [`_mm512_mask_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_ps&expand=5236)
+   * [ ] [`_mm512_mask_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_pd&expand=5236)
+   * [ ] [`_mm512_mask_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_ps&expand=5236)
+   * [x] [`_mm512_mask_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi32&expand=5236)
+   * [x] [`_mm512_mask_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi64&expand=5236)
+   * [x] [`_mm512_mask_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_epi32&expand=5236)
+   * [x] [`_mm512_mask_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_f32x4&expand=5236)
+   * [x] [`_mm512_mask_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_f64x2&expand=5236)
+   * [x] [`_mm512_mask_shuffle_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_i32x4&expand=5236)
+   * [x] [`_mm512_mask_shuffle_i64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_i64x2&expand=5236)
+   * [x] [`_mm512_mask_shuffle_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_pd&expand=5236)
+   * [x] [`_mm512_mask_shuffle_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_ps&expand=5236)
+   * [x] [`_mm512_mask_sll_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sll_epi32&expand=5236)
+   * [x] [`_mm512_mask_sll_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sll_epi64&expand=5236)
+   * [x] [`_mm512_mask_slli_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_slli_epi32&expand=5236)
+   * [x] [`_mm512_mask_slli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_slli_epi64&expand=5236)
+   * [x] [`_mm512_mask_sllv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sllv_epi32&expand=5236)
+   * [x] [`_mm512_mask_sllv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sllv_epi64&expand=5236)
+   * [x] [`_mm512_mask_sqrt_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sqrt_pd&expand=5236)
+   * [x] [`_mm512_mask_sqrt_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sqrt_ps&expand=5236)
+   * [x] [`_mm512_mask_sqrt_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sqrt_round_pd&expand=5236)
+   * [x] [`_mm512_mask_sqrt_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sqrt_round_ps&expand=5236)
+   * [x] [`_mm512_mask_sra_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sra_epi32&expand=5236)
+   * [x] [`_mm512_mask_sra_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sra_epi64&expand=5236)
+   * [x] [`_mm512_mask_srai_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srai_epi32&expand=5236)
+   * [x] [`_mm512_mask_srai_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srai_epi64&expand=5236)
+   * [x] [`_mm512_mask_srav_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srav_epi32&expand=5236)
+   * [x] [`_mm512_mask_srav_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srav_epi64&expand=5236)
+   * [x] [`_mm512_mask_srl_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srl_epi32&expand=5236)
+   * [x] [`_mm512_mask_srl_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srl_epi64&expand=5236)
+   * [x] [`_mm512_mask_srli_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srli_epi32&expand=5236)
+   * [x] [`_mm512_mask_srli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srli_epi64&expand=5236)
+   * [x] [`_mm512_mask_srlv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srlv_epi32&expand=5236)
+   * [x] [`_mm512_mask_srlv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srlv_epi64&expand=5236)
+   * [ ] [`_mm512_mask_store_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_epi32&expand=5236)
+   * [ ] [`_mm512_mask_store_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_epi64&expand=5236)
+   * [ ] [`_mm512_mask_store_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_pd&expand=5236)
+   * [ ] [`_mm512_mask_store_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_ps&expand=5236)
+   * [ ] [`_mm512_mask_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_epi32&expand=5236)
+   * [ ] [`_mm512_mask_storeu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_epi64&expand=5236)
+   * [ ] [`_mm512_mask_storeu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_pd&expand=5236)
+   * [ ] [`_mm512_mask_storeu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_ps&expand=5236)
+   * [x] [`_mm512_mask_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_epi32&expand=5236)
+   * [x] [`_mm512_mask_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_epi64&expand=5236)
+   * [x] [`_mm512_mask_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_pd&expand=5236)
+   * [x] [`_mm512_mask_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_ps&expand=5236)
+   * [x] [`_mm512_mask_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_pd&expand=5236)
+   * [x] [`_mm512_mask_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_ps&expand=5236)
+   * [ ] [`_mm512_mask_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi32&expand=5236)
+   * [ ] [`_mm512_mask_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi64&expand=5236)
+   * [ ] [`_mm512_mask_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi32_mask&expand=5236)
+   * [ ] [`_mm512_mask_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi64_mask&expand=5236)
+   * [ ] [`_mm512_mask_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi32_mask&expand=5236)
+   * [ ] [`_mm512_mask_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi64_mask&expand=5236)
+   * [x] [`_mm512_mask_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_epi32&expand=5236)
+   * [x] [`_mm512_mask_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_epi64&expand=5236)
+   * [x] [`_mm512_mask_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_pd&expand=5236)
+   * [x] [`_mm512_mask_unpackhi_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_ps&expand=5236)
+   * [x] [`_mm512_mask_unpacklo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_epi32&expand=5236)
+   * [x] [`_mm512_mask_unpacklo_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_epi64&expand=5236)
+   * [x] [`_mm512_mask_unpacklo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_pd&expand=5236)
+   * [x] [`_mm512_mask_unpacklo_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_ps&expand=5236)
+   * [x] [`_mm512_mask_xor_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_xor_epi32&expand=5236)
+   * [x] [`_mm512_mask_xor_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_xor_epi64&expand=5236)
+   * [x] [`_mm512_maskz_abs_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_abs_epi32&expand=5236)
+   * [x] [`_mm512_maskz_abs_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_abs_epi64&expand=5236)
+   * [x] [`_mm512_maskz_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_epi32&expand=5236)
+   * [x] [`_mm512_maskz_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_epi64&expand=5236)
+   * [x] [`_mm512_maskz_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_pd&expand=5236)
+   * [x] [`_mm512_maskz_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_ps&expand=5236)
+   * [x] [`_mm512_maskz_add_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_add_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_round_ps&expand=5236)
+   * [ ] [`_mm512_maskz_alignr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_alignr_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_alignr_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_alignr_epi64&expand=5236)
+   * [x] [`_mm512_maskz_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_and_epi32&expand=5236)
+   * [x] [`_mm512_maskz_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_and_epi64&expand=5236)
+   * [x] [`_mm512_maskz_andnot_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_andnot_epi32&expand=5236)
+   * [x] [`_mm512_maskz_andnot_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_andnot_epi64&expand=5236)
+   * [x] [`_mm512_maskz_broadcast_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_f32x4&expand=5236)
+   * [x] [`_mm512_maskz_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_f64x4&expand=5236)
+   * [x] [`_mm512_maskz_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_i32x4&expand=5236)
+   * [x] [`_mm512_maskz_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_i64x4&expand=5236)
+   * [x] [`_mm512_maskz_broadcastd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastd_epi32&expand=5236)
+   * [x] [`_mm512_maskz_broadcastq_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastq_epi64&expand=5236)
+   * [x] [`_mm512_maskz_broadcastsd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastsd_pd&expand=5236)
+   * [x] [`_mm512_maskz_broadcastss_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastss_ps&expand=5236)
+   * [ ] [`_mm512_maskz_compress_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_compress_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_compress_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_pd&expand=5236)
+   * [ ] [`_mm512_maskz_compress_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepi32_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepu32_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_epu32&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_ps&expand=5236)
+   * [x] [`_mm512_maskz_cvt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_epu32&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_pd&expand=5236)
+   * [ ] [`_mm512_maskz_cvt_roundps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_ph&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi16_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi16_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_epi16&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_epi8&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_pd&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_epi16&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_epi8&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi8_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepi8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi8_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu16_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu16_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_pd&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu8_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtepu8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu8_epi64&expand=5236)
+   * [x] [`_mm512_maskz_cvtpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvtpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_epu32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_ps&expand=5236)
+   * [ ] [`_mm512_maskz_cvtph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_ps&expand=5236)
+   * [x] [`_mm512_maskz_cvtps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvtps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_epu32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_pd&expand=5236)
+   * [ ] [`_mm512_maskz_cvtps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_ph&expand=5236)
+   * [ ] [`_mm512_maskz_cvtsepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi32_epi16&expand=5236)
+   * [ ] [`_mm512_maskz_cvtsepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi32_epi8&expand=5236)
+   * [ ] [`_mm512_maskz_cvtsepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi64_epi16&expand=5236)
+   * [ ] [`_mm512_maskz_cvtsepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi64_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtsepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi64_epi8&expand=5236)
+   * [x] [`_mm512_maskz_cvtt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundpd_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvtt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundpd_epu32&expand=5236)
+   * [x] [`_mm512_maskz_cvtt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundps_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvtt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundps_epu32&expand=5236)
+   * [x] [`_mm512_maskz_cvttpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttpd_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvttpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttpd_epu32&expand=5236)
+   * [x] [`_mm512_maskz_cvttps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttps_epi32&expand=5236)
+   * [x] [`_mm512_maskz_cvttps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttps_epu32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtusepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi32_epi16&expand=5236)
+   * [ ] [`_mm512_maskz_cvtusepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi32_epi8&expand=5236)
+   * [ ] [`_mm512_maskz_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi16&expand=5236)
+   * [ ] [`_mm512_maskz_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi8&expand=5236)
+   * [x] [`_mm512_maskz_div_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_pd&expand=5236)
+   * [x] [`_mm512_maskz_div_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_ps&expand=5236)
+   * [x] [`_mm512_maskz_div_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_div_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_round_ps&expand=5236)
+   * [ ] [`_mm512_maskz_expand_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_expand_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_expand_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_pd&expand=5236)
+   * [ ] [`_mm512_maskz_expand_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_ps&expand=5236)
+   * [ ] [`_mm512_maskz_expandloadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_expandloadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_expandloadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_pd&expand=5236)
+   * [ ] [`_mm512_maskz_expandloadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_ps&expand=5236)
+   * [ ] [`_mm512_maskz_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extractf32x4_ps&expand=5236)
+   * [ ] [`_mm512_maskz_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extractf64x4_pd&expand=5236)
+   * [ ] [`_mm512_maskz_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extracti32x4_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extracti64x4_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_pd&expand=5236)
+   * [ ] [`_mm512_maskz_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_ps&expand=5236)
+   * [ ] [`_mm512_maskz_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_pd&expand=5236)
+   * [ ] [`_mm512_maskz_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmaddsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmaddsub_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmaddsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmaddsub_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmaddsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmaddsub_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmaddsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmaddsub_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsub_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsub_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsub_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsub_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmsubadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsubadd_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmsubadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsubadd_ps&expand=5236)
+   * [x] [`_mm512_maskz_fmsubadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsubadd_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_fmsubadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmsubadd_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_fnmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmadd_pd&expand=5236)
+   * [x] [`_mm512_maskz_fnmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmadd_ps&expand=5236)
+   * [x] [`_mm512_maskz_fnmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmadd_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_fnmadd_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmadd_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_fnmsub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmsub_pd&expand=5236)
+   * [x] [`_mm512_maskz_fnmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmsub_ps&expand=5236)
+   * [x] [`_mm512_maskz_fnmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmsub_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_fnmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fnmsub_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_getexp_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getexp_pd&expand=5236)
+   * [x] [`_mm512_maskz_getexp_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getexp_ps&expand=5236)
+   * [x] [`_mm512_maskz_getexp_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getexp_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_getexp_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getexp_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_getmant_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_pd&expand=5236)
+   * [x] [`_mm512_maskz_getmant_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_ps&expand=5236)
+   * [x] [`_mm512_maskz_getmant_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_getmant_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_insertf32x4&expand=5236)
+   * [x] [`_mm512_maskz_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_insertf64x4&expand=5236)
+   * [x] [`_mm512_maskz_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_inserti32x4&expand=5236)
+   * [x] [`_mm512_maskz_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_inserti64x4&expand=5236)
+   * [ ] [`_mm512_maskz_load_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_load_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_load_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_pd&expand=5236)
+   * [ ] [`_mm512_maskz_load_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_ps&expand=5236)
+   * [ ] [`_mm512_maskz_loadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_loadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_loadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_pd&expand=5236)
+   * [ ] [`_mm512_maskz_loadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_ps&expand=5236)
+   * [x] [`_mm512_maskz_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_epi32&expand=5236)
+   * [x] [`_mm512_maskz_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_epi64&expand=5236)
+   * [x] [`_mm512_maskz_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_epu32&expand=5236)
+   * [x] [`_mm512_maskz_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_epu64&expand=5236)
+   * [x] [`_mm512_maskz_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_pd&expand=5236)
+   * [x] [`_mm512_maskz_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_ps&expand=5236)
+   * [x] [`_mm512_maskz_max_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_max_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_max_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_epi32&expand=5236)
+   * [x] [`_mm512_maskz_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_epi64&expand=5236)
+   * [x] [`_mm512_maskz_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_epu32&expand=5236)
+   * [x] [`_mm512_maskz_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_epu64&expand=5236)
+   * [x] [`_mm512_maskz_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_pd&expand=5236)
+   * [x] [`_mm512_maskz_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_ps&expand=5236)
+   * [x] [`_mm512_maskz_min_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_min_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_round_ps&expand=5236)
+   * [ ] [`_mm512_maskz_mov_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_mov_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_mov_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_pd&expand=5236)
+   * [ ] [`_mm512_maskz_mov_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_ps&expand=5236)
+   * [x] [`_mm512_maskz_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_movedup_pd&expand=5236)
+   * [x] [`_mm512_maskz_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_movehdup_ps&expand=5236)
+   * [x] [`_mm512_maskz_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_moveldup_ps&expand=5236)
+   * [x] [`_mm512_maskz_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_epi32&expand=5236)
+   * [x] [`_mm512_maskz_mul_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_epu32&expand=5236)
+   * [x] [`_mm512_maskz_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_pd&expand=5236)
+   * [x] [`_mm512_maskz_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_ps&expand=5236)
+   * [x] [`_mm512_maskz_mul_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_mul_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_mullo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mullo_epi32&expand=5236)
+   * [x] [`_mm512_maskz_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_or_epi32&expand=5236)
+   * [x] [`_mm512_maskz_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_or_epi64&expand=5236)
+   * [x] [`_mm512_maskz_permute_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permute_pd&expand=5236)
+   * [x] [`_mm512_maskz_permute_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permute_ps&expand=5236)
+   * [x] [`_mm512_maskz_permutevar_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutevar_pd&expand=5236)
+   * [x] [`_mm512_maskz_permutevar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutevar_ps&expand=5236)
+   * [x] [`_mm512_maskz_permutex2var_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex2var_epi32&expand=5236)
+   * [x] [`_mm512_maskz_permutex2var_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex2var_epi64&expand=5236)
+   * [x] [`_mm512_maskz_permutex2var_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex2var_pd&expand=5236)
+   * [x] [`_mm512_maskz_permutex2var_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex2var_ps&expand=5236)
+   * [x] [`_mm512_maskz_permutex_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex_epi64&expand=5236)
+   * [x] [`_mm512_maskz_permutex_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex_pd&expand=5236)
+   * [x] [`_mm512_maskz_permutexvar_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutexvar_epi32&expand=5236)
+   * [x] [`_mm512_maskz_permutexvar_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutexvar_epi64&expand=5236)
+   * [x] [`_mm512_maskz_permutexvar_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutexvar_pd&expand=5236)
+   * [x] [`_mm512_maskz_permutexvar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutexvar_ps&expand=5236)
+   * [x] [`_mm512_maskz_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rcp14_pd&expand=5236)
+   * [x] [`_mm512_maskz_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rcp14_ps&expand=5236)
+   * [x] [`_mm512_maskz_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rol_epi32&expand=5236)
+   * [x] [`_mm512_maskz_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rol_epi64&expand=5236)
+   * [x] [`_mm512_maskz_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rolv_epi32&expand=5236)
+   * [x] [`_mm512_maskz_rolv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rolv_epi64&expand=5236)
+   * [x] [`_mm512_maskz_ror_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ror_epi32&expand=5236)
+   * [x] [`_mm512_maskz_ror_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ror_epi64&expand=5236)
+   * [x] [`_mm512_maskz_rorv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rorv_epi32&expand=5236)
+   * [x] [`_mm512_maskz_rorv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rorv_epi64&expand=5236)
+   * [ ] [`_mm512_maskz_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_pd&expand=5236)
+   * [ ] [`_mm512_maskz_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_ps&expand=5236)
+   * [ ] [`_mm512_maskz_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_pd&expand=5236)
+   * [ ] [`_mm512_maskz_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_rsqrt14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rsqrt14_pd&expand=5236)
+   * [x] [`_mm512_maskz_rsqrt14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rsqrt14_ps&expand=5236)
+   * [ ] [`_mm512_maskz_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_pd&expand=5236)
+   * [ ] [`_mm512_maskz_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_ps&expand=5236)
+   * [ ] [`_mm512_maskz_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_pd&expand=5236)
+   * [ ] [`_mm512_maskz_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_ps&expand=5236)
+   * [ ] [`_mm512_maskz_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_set1_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_set1_epi64&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_epi32&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_f32x4&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_f64x2&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_i32x4&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_i64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_i64x2&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_pd&expand=5236)
+   * [x] [`_mm512_maskz_shuffle_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_ps&expand=5236)
+   * [x] [`_mm512_maskz_sll_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sll_epi32&expand=5236)
+   * [x] [`_mm512_maskz_sll_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sll_epi64&expand=5236)
+   * [x] [`_mm512_maskz_slli_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_slli_epi32&expand=5236)
+   * [x] [`_mm512_maskz_slli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_slli_epi64&expand=5236)
+   * [x] [`_mm512_maskz_sllv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sllv_epi32&expand=5236)
+   * [x] [`_mm512_maskz_sllv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sllv_epi64&expand=5236)
+   * [x] [`_mm512_maskz_sqrt_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sqrt_pd&expand=5236)
+   * [x] [`_mm512_maskz_sqrt_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sqrt_ps&expand=5236)
+   * [x] [`_mm512_maskz_sqrt_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sqrt_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_sqrt_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sqrt_round_ps&expand=5236)
+   * [x] [`_mm512_maskz_sra_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sra_epi32&expand=5236)
+   * [x] [`_mm512_maskz_sra_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sra_epi64&expand=5236)
+   * [x] [`_mm512_maskz_srai_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srai_epi32&expand=5236)
+   * [x] [`_mm512_maskz_srai_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srai_epi64&expand=5236)
+   * [x] [`_mm512_maskz_srav_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srav_epi32&expand=5236)
+   * [x] [`_mm512_maskz_srav_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srav_epi64&expand=5236)
+   * [x] [`_mm512_maskz_srl_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srl_epi32&expand=5236)
+   * [x] [`_mm512_maskz_srl_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srl_epi64&expand=5236)
+   * [x] [`_mm512_maskz_srli_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srli_epi32&expand=5236)
+   * [x] [`_mm512_maskz_srli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srli_epi64&expand=5236)
+   * [x] [`_mm512_maskz_srlv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srlv_epi32&expand=5236)
+   * [x] [`_mm512_maskz_srlv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srlv_epi64&expand=5236)
+   * [x] [`_mm512_maskz_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_epi32&expand=5236)
+   * [x] [`_mm512_maskz_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_epi64&expand=5236)
+   * [x] [`_mm512_maskz_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_pd&expand=5236)
+   * [x] [`_mm512_maskz_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_ps&expand=5236)
+   * [x] [`_mm512_maskz_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_pd&expand=5236)
+   * [x] [`_mm512_maskz_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_ps&expand=5236)
+   * [ ] [`_mm512_maskz_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi32&expand=5236)
+   * [ ] [`_mm512_maskz_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi64&expand=5236)
+   * [x] [`_mm512_maskz_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_epi32&expand=5236)
+   * [x] [`_mm512_maskz_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_epi64&expand=5236)
+   * [x] [`_mm512_maskz_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_pd&expand=5236)
+   * [x] [`_mm512_maskz_unpackhi_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_ps&expand=5236)
+   * [x] [`_mm512_maskz_unpacklo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpacklo_epi32&expand=5236)
+   * [x] [`_mm512_maskz_unpacklo_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpacklo_epi64&expand=5236)
+   * [x] [`_mm512_maskz_unpacklo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpacklo_pd&expand=5236)
+   * [x] [`_mm512_maskz_unpacklo_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpacklo_ps&expand=5236)
+   * [x] [`_mm512_maskz_xor_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_xor_epi32&expand=5236)
+   * [x] [`_mm512_maskz_xor_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_xor_epi64&expand=5236)
+   * [x] [`_mm512_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_epi32&expand=5236)
+   * [x] [`_mm512_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_epi64&expand=5236)
+   * [x] [`_mm512_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_epu32&expand=5236)
+   * [x] [`_mm512_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_epu64&expand=5236)
+   * [x] [`_mm512_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_pd&expand=5236)
+   * [x] [`_mm512_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_ps&expand=5236)
+   * [x] [`_mm512_max_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_round_pd&expand=5236)
+   * [x] [`_mm512_max_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_max_round_ps&expand=5236)
+   * [x] [`_mm512_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_epi32&expand=5236)
+   * [x] [`_mm512_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_epi64&expand=5236)
+   * [x] [`_mm512_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_epu32&expand=5236)
+   * [x] [`_mm512_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_epu64&expand=5236)
+   * [x] [`_mm512_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_pd&expand=5236)
+   * [x] [`_mm512_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_ps&expand=5236)
+   * [x] [`_mm512_min_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_round_pd&expand=5236)
+   * [x] [`_mm512_min_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_min_round_ps&expand=5236)
+   * [x] [`_mm512_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_movedup_pd&expand=5236)
+   * [x] [`_mm512_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_movehdup_ps&expand=5236)
+   * [x] [`_mm512_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_moveldup_ps&expand=5236)
+   * [x] [`_mm512_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_epi32&expand=5236)
+   * [x] [`_mm512_mul_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_epu32&expand=5236)
+   * [x] [`_mm512_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_pd&expand=5236)
+   * [x] [`_mm512_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_ps&expand=5236)
+   * [x] [`_mm512_mul_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_round_pd&expand=5236)
+   * [x] [`_mm512_mul_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_round_ps&expand=5236)
+   * [x] [`_mm512_mullo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mullo_epi32&expand=5236)
+   * [x] [`_mm512_mullox_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mullox_epi64&expand=5236)
+   * [x] [`_mm512_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_or_epi32&expand=5236)
+   * [x] [`_mm512_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_or_epi64&expand=5236)
+   * [x] [`_mm512_or_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_or_si512&expand=5236)
+   * [x] [`_mm512_permute_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permute_pd&expand=5236)
+   * [x] [`_mm512_permute_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permute_ps&expand=5236)
+   * [x] [`_mm512_permutevar_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutevar_epi32&expand=5236)
+   * [x] [`_mm512_permutevar_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutevar_pd&expand=5236)
+   * [x] [`_mm512_permutevar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutevar_ps&expand=5236)
+   * [x] [`_mm512_permutex2var_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_epi32&expand=5236)
+   * [x] [`_mm512_permutex2var_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_epi64&expand=5236)
+   * [x] [`_mm512_permutex2var_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_pd&expand=5236)
+   * [x] [`_mm512_permutex2var_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ps&expand=5236)
+   * [x] [`_mm512_permutex_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex_epi64&expand=5236)
+   * [x] [`_mm512_permutex_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex_pd&expand=5236)
+   * [x] [`_mm512_permutexvar_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_epi32&expand=5236)
+   * [x] [`_mm512_permutexvar_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_epi64&expand=5236)
+   * [x] [`_mm512_permutexvar_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_pd&expand=5236)
+   * [x] [`_mm512_permutexvar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ps&expand=5236)
+   * [x] [`_mm512_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp14_pd&expand=5236)
+   * [x] [`_mm512_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp14_ps&expand=5236)
+   * [ ] [`_mm512_reduce_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi32&expand=5236)
+   * [ ] [`_mm512_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi64&expand=5236)
+   * [ ] [`_mm512_reduce_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_pd&expand=5236)
+   * [ ] [`_mm512_reduce_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_ps&expand=5236)
+   * [ ] [`_mm512_reduce_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi32&expand=5236)
+   * [ ] [`_mm512_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi64&expand=5236)
+   * [ ] [`_mm512_reduce_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi32&expand=5236)
+   * [ ] [`_mm512_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi64&expand=5236)
+   * [ ] [`_mm512_reduce_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu32&expand=5236)
+   * [ ] [`_mm512_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu64&expand=5236)
+   * [ ] [`_mm512_reduce_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_pd&expand=5236)
+   * [ ] [`_mm512_reduce_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_ps&expand=5236)
+   * [ ] [`_mm512_reduce_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi32&expand=5236)
+   * [ ] [`_mm512_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi64&expand=5236)
+   * [ ] [`_mm512_reduce_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu32&expand=5236)
+   * [ ] [`_mm512_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu64&expand=5236)
+   * [ ] [`_mm512_reduce_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_pd&expand=5236)
+   * [ ] [`_mm512_reduce_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_ps&expand=5236)
+   * [ ] [`_mm512_reduce_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi32&expand=5236)
+   * [ ] [`_mm512_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi64&expand=5236)
+   * [ ] [`_mm512_reduce_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_pd&expand=5236)
+   * [ ] [`_mm512_reduce_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_ps&expand=5236)
+   * [ ] [`_mm512_reduce_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi32&expand=5236)
+   * [ ] [`_mm512_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi64&expand=5236)
+   * [x] [`_mm512_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rol_epi32&expand=5236)
+   * [x] [`_mm512_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rol_epi64&expand=5236)
+   * [x] [`_mm512_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rolv_epi32&expand=5236)
+   * [x] [`_mm512_rolv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rolv_epi64&expand=5236)
+   * [x] [`_mm512_ror_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ror_epi32&expand=5236)
+   * [x] [`_mm512_ror_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ror_epi64&expand=5236)
+   * [x] [`_mm512_rorv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rorv_epi32&expand=5236)
+   * [x] [`_mm512_rorv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rorv_epi64&expand=5236)
+   * [ ] [`_mm512_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_pd&expand=5236)
+   * [ ] [`_mm512_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_ps&expand=5236)
+   * [ ] [`_mm512_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_pd&expand=5236)
+   * [ ] [`_mm512_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_ps&expand=5236)
+   * [x] [`_mm512_rsqrt14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rsqrt14_pd&expand=5236)
+   * [x] [`_mm512_rsqrt14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rsqrt14_ps&expand=5236)
+   * [ ] [`_mm512_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_pd&expand=5236)
+   * [ ] [`_mm512_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_ps&expand=5236)
+   * [ ] [`_mm512_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_pd&expand=5236)
+   * [ ] [`_mm512_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_ps&expand=5236)
+   * [ ] [`_mm512_set1_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi16&expand=5236)
+   * [ ] [`_mm512_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi32&expand=5236)
+   * [ ] [`_mm512_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi64&expand=5236)
+   * [ ] [`_mm512_set1_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi8&expand=5236)
+   * [ ] [`_mm512_set1_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_pd&expand=5236)
+   * [ ] [`_mm512_set1_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_ps&expand=5236)
+   * [ ] [`_mm512_set4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_epi32&expand=5236)
+   * [ ] [`_mm512_set4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_epi64&expand=5236)
+   * [ ] [`_mm512_set4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_pd&expand=5236)
+   * [ ] [`_mm512_set4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_ps&expand=5236)
+   * [ ] [`_mm512_set_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi16&expand=5236)
+   * [ ] [`_mm512_set_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi32&expand=5236)
+   * [x] [`_mm512_set_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi64&expand=5236)
+   * [ ] [`_mm512_set_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi8&expand=5236)
+   * [x] [`_mm512_set_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_pd&expand=5236)
+   * [x] [`_mm512_set_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_ps&expand=5236)
+   * [ ] [`_mm512_setr4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_epi32&expand=5236)
+   * [ ] [`_mm512_setr4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_epi64&expand=5236)
+   * [ ] [`_mm512_setr4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_pd&expand=5236)
+   * [ ] [`_mm512_setr4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_ps&expand=5236)
+   * [x] [`_mm512_setr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_epi32&expand=5236)
+   * [x] [`_mm512_setr_epi64`](https:/software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_epi64&expand=5236)
+   * [x] [`_mm512_setr_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_pd&expand=5236)
+   * [x] [`_mm512_setr_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_ps&expand=5236)
+   * [ ] [`_mm512_setzero_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_epi32&expand=5236)
+   * [x] [`_mm512_setzero_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_pd&expand=5236)
+   * [x] [`_mm512_setzero_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ps&expand=5236)
+   * [x] [`_mm512_setzero_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_si512&expand=5236)
+   * [ ] [`_mm512_setzero`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero&expand=5236)
+   * [x] [`_mm512_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_epi32&expand=5236)
+   * [x] [`_mm512_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_f32x4&expand=5236)
+   * [x] [`_mm512_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_f64x2&expand=5236)
+   * [x] [`_mm512_shuffle_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_i32x4&expand=5236)
+   * [x] [`_mm512_shuffle_i64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_i64x2&expand=5236)
+   * [x] [`_mm512_shuffle_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_pd&expand=5236)
+   * [x] [`_mm512_shuffle_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_ps&expand=5236)
+   * [x] [`_mm512_sll_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sll_epi32&expand=5236)
+   * [x] [`_mm512_sll_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sll_epi64&expand=5236)
+   * [x] [`_mm512_slli_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_slli_epi32&expand=5236)
+   * [x] [`_mm512_slli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_slli_epi64&expand=5236)
+   * [x] [`_mm512_sllv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sllv_epi32&expand=5236)
+   * [x] [`_mm512_sllv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sllv_epi64&expand=5236)
+   * [x] [`_mm512_sqrt_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_pd&expand=5236)
+   * [x] [`_mm512_sqrt_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_ps&expand=5236)
+   * [x] [`_mm512_sqrt_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_round_pd&expand=5236)
+   * [x] [`_mm512_sqrt_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_round_ps&expand=5236)
+   * [x] [`_mm512_sra_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sra_epi32&expand=5236)
+   * [x] [`_mm512_sra_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sra_epi64&expand=5236)
+   * [x] [`_mm512_srai_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srai_epi32&expand=5236)
+   * [x] [`_mm512_srai_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srai_epi64&expand=5236)
+   * [x] [`_mm512_srav_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srav_epi32&expand=5236)
+   * [x] [`_mm512_srav_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srav_epi64&expand=5236)
+   * [x] [`_mm512_srl_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srl_epi32&expand=5236)
+   * [x] [`_mm512_srl_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srl_epi64&expand=5236)
+   * [x] [`_mm512_srli_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srli_epi32&expand=5236)
+   * [x] [`_mm512_srli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srli_epi64&expand=5236)
+   * [x] [`_mm512_srlv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srlv_epi32&expand=5236)
+   * [x] [`_mm512_srlv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srlv_epi64&expand=5236)
+   * [ ] [`_mm512_store_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_epi32&expand=5236)
+   * [ ] [`_mm512_store_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_epi64&expand=5236)
+   * [ ] [`_mm512_store_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_pd&expand=5236)
+   * [ ] [`_mm512_store_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_ps&expand=5236)
+   * [ ] [`_mm512_store_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_si512&expand=5236)
+   * [x] [`_mm512_storeu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_pd&expand=5236)
+   * [x] [`_mm512_storeu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_ps&expand=5236)
+   * [ ] [`_mm512_storeu_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_si512&expand=5236)
+   * [ ] [`_mm512_stream_load_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_load_si512&expand=5236)
+   * [ ] [`_mm512_stream_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_pd&expand=5236)
+   * [ ] [`_mm512_stream_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_ps&expand=5236)
+   * [ ] [`_mm512_stream_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_si512&expand=5236)
+   * [x] [`_mm512_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_epi32&expand=5236)
+   * [x] [`_mm512_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_epi64&expand=5236)
+   * [x] [`_mm512_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_pd&expand=5236)
+   * [x] [`_mm512_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_ps&expand=5236)
+   * [x] [`_mm512_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_pd&expand=5236)
+   * [x] [`_mm512_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_ps&expand=5236)
+   * [ ] [`_mm512_svml_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_svml_round_pd&expand=5236)
+   * [ ] [`_mm512_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi32&expand=5236)
+   * [ ] [`_mm512_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi64&expand=5236)
+   * [ ] [`_mm512_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi32_mask&expand=5236)
+   * [ ] [`_mm512_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi64_mask&expand=5236)
+   * [ ] [`_mm512_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi32_mask&expand=5236)
+   * [ ] [`_mm512_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi64_mask&expand=5236)
+   * [ ] [`_mm512_undefined_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_epi32&expand=5236)
+   * [x] [`_mm512_undefined_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_pd&expand=5236)
+   * [x] [`_mm512_undefined_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ps&expand=5236)
+   * [ ] [`_mm512_undefined`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined&expand=5236)
+   * [x] [`_mm512_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_epi32&expand=5236)
+   * [x] [`_mm512_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_epi64&expand=5236)
+   * [x] [`_mm512_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_pd&expand=5236)
+   * [x] [`_mm512_unpackhi_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_ps&expand=5236)
+   * [x] [`_mm512_unpacklo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_epi32&expand=5236)
+   * [x] [`_mm512_unpacklo_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_epi64&expand=5236)
+   * [x] [`_mm512_unpacklo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_pd&expand=5236)
+   * [x] [`_mm512_unpacklo_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_ps&expand=5236)
+   * [x] [`_mm512_xor_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_xor_epi32&expand=5236)
+   * [x] [`_mm512_xor_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_xor_epi64&expand=5236)
+   * [x] [`_mm512_xor_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_xor_si512&expand=5236)
+   * [ ] [`_mm512_zextpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextpd128_pd512&expand=5236)
+   * [ ] [`_mm512_zextpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextpd256_pd512&expand=5236)
+   * [ ] [`_mm512_zextps128_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextps128_ps512&expand=5236)
+   * [ ] [`_mm512_zextps256_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextps256_ps512&expand=5236)
+   * [ ] [`_mm512_zextsi128_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextsi128_si512&expand=5236)
+   * [ ] [`_mm512_zextsi256_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextsi256_si512&expand=5236)
+   * [ ] [`_mm_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_sd&expand=5236)
+   * [ ] [`_mm_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_ss&expand=5236)
+   * [x] [`_mm_cmp_round_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_sd_mask&expand=5236)
+   * [x] [`_mm_cmp_round_ss_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_ss_mask&expand=5236)
+   * [x] [`_mm_cmp_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_sd_mask&expand=5236)
+   * [x] [`_mm_cmp_ss_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ss_mask&expand=5236)
+   * [ ] [`_mm_comi_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comi_round_sd&expand=5236)
+   * [ ] [`_mm_comi_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comi_round_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundi32_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundi32_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundi64_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundi64_sd&expand=5236)
+   * [ ] [`_mm_cvt_roundi64_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundi64_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_i32&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_i64&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_si32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_si32&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_si64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_si64&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_u32&expand=5236)
+   * [ ] [`_mm_cvt_roundsd_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsd_u64&expand=5236)
+   * [ ] [`_mm_cvt_roundsi32_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsi32_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundsi64_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsi64_sd&expand=5236)
+   * [ ] [`_mm_cvt_roundsi64_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundsi64_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundss_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_i32&expand=5236)
+   * [ ] [`_mm_cvt_roundss_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_i64&expand=5236)
+   * [ ] [`_mm_cvt_roundss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_sd&expand=5236)
+   * [ ] [`_mm_cvt_roundss_si32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_si32&expand=5236)
+   * [ ] [`_mm_cvt_roundss_si64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_si64&expand=5236)
+   * [ ] [`_mm_cvt_roundss_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_u32&expand=5236)
+   * [ ] [`_mm_cvt_roundss_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundss_u64&expand=5236)
+   * [ ] [`_mm_cvt_roundu32_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundu32_ss&expand=5236)
+   * [ ] [`_mm_cvt_roundu64_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundu64_sd&expand=5236)
+   * [ ] [`_mm_cvt_roundu64_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_roundu64_ss&expand=5236)
+   * [ ] [`_mm_cvti32_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvti32_sd&expand=5236)
+   * [ ] [`_mm_cvti32_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvti32_ss&expand=5236)
+   * [ ] [`_mm_cvti64_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvti64_sd&expand=5236)
+   * [ ] [`_mm_cvti64_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvti64_ss&expand=5236)
+   * [ ] [`_mm_cvtsd_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_i32&expand=5236)
+   * [ ] [`_mm_cvtsd_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_i64&expand=5236)
+   * [ ] [`_mm_cvtsd_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_u32&expand=5236)
+   * [ ] [`_mm_cvtsd_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_u64&expand=5236)
+   * [ ] [`_mm_cvtss_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_i32&expand=5236)
+   * [ ] [`_mm_cvtss_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_i64&expand=5236)
+   * [ ] [`_mm_cvtss_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_u32&expand=5236)
+   * [ ] [`_mm_cvtss_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_u64&expand=5236)
+   * [ ] [`_mm_cvtt_roundsd_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsd_i32&expand=5236)
+   * [ ] [`_mm_cvtt_roundsd_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsd_i64&expand=5236)
+   * [ ] [`_mm_cvtt_roundsd_si32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsd_si32&expand=5236)
+   * [ ] [`_mm_cvtt_roundsd_si64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsd_si64&expand=5236)
+   * [ ] [`_mm_cvtt_roundsd_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsd_u32&expand=5236)
+   * [ ] [`_mm_cvtt_roundsd_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundsd_u64&expand=5236)
+   * [ ] [`_mm_cvtt_roundss_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundss_i32&expand=5236)
+   * [ ] [`_mm_cvtt_roundss_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundss_i64&expand=5236)
+   * [ ] [`_mm_cvtt_roundss_si32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundss_si32&expand=5236)
+   * [ ] [`_mm_cvtt_roundss_si64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundss_si64&expand=5236)
+   * [ ] [`_mm_cvtt_roundss_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundss_u32&expand=5236)
+   * [ ] [`_mm_cvtt_roundss_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_roundss_u64&expand=5236)
+   * [ ] [`_mm_cvttsd_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_i32&expand=5236)
+   * [ ] [`_mm_cvttsd_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_i64&expand=5236)
+   * [ ] [`_mm_cvttsd_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_u32&expand=5236)
+   * [ ] [`_mm_cvttsd_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_u64&expand=5236)
+   * [ ] [`_mm_cvttss_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_i32&expand=5236)
+   * [ ] [`_mm_cvttss_i64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_i64&expand=5236)
+   * [ ] [`_mm_cvttss_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_u32&expand=5236)
+   * [ ] [`_mm_cvttss_u64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_u64&expand=5236)
+   * [ ] [`_mm_cvtu32_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu32_sd&expand=5236)
+   * [ ] [`_mm_cvtu32_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu32_ss&expand=5236)
+   * [ ] [`_mm_cvtu64_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu64_sd&expand=5236)
+   * [ ] [`_mm_cvtu64_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu64_ss&expand=5236)
+   * [ ] [`_mm_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_sd&expand=5236)
+   * [ ] [`_mm_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_ss&expand=5236)
+   * [ ] [`_mm_fixupimm_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_round_sd&expand=5236)
+   * [ ] [`_mm_fixupimm_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_round_ss&expand=5236)
+   * [ ] [`_mm_fixupimm_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_sd&expand=5236)
+   * [ ] [`_mm_fixupimm_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_ss&expand=5236)
+   * [ ] [`_mm_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_sd&expand=5236)
+   * [ ] [`_mm_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_ss&expand=5236)
+   * [ ] [`_mm_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_round_sd&expand=5236)
+   * [ ] [`_mm_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_round_ss&expand=5236)
+   * [ ] [`_mm_fnmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_round_sd&expand=5236)
+   * [ ] [`_mm_fnmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_round_ss&expand=5236)
+   * [ ] [`_mm_fnmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_round_sd&expand=5236)
+   * [ ] [`_mm_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_round_ss&expand=5236)
+   * [ ] [`_mm_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_sd&expand=5236)
+   * [ ] [`_mm_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_ss&expand=5236)
+   * [ ] [`_mm_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_sd&expand=5236)
+   * [ ] [`_mm_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_ss&expand=5236)
+   * [ ] [`_mm_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_sd&expand=5236)
+   * [ ] [`_mm_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_ss&expand=5236)
+   * [ ] [`_mm_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_sd&expand=5236)
+   * [ ] [`_mm_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_ss&expand=5236)
+   * [ ] [`_mm_mask3_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_sd&expand=5236)
+   * [ ] [`_mm_mask3_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_ss&expand=5236)
+   * [ ] [`_mm_mask3_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_sd&expand=5236)
+   * [ ] [`_mm_mask3_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_ss&expand=5236)
+   * [ ] [`_mm_mask3_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_round_sd&expand=5236)
+   * [ ] [`_mm_mask3_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_round_ss&expand=5236)
+   * [ ] [`_mm_mask3_fmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_sd&expand=5236)
+   * [ ] [`_mm_mask3_fmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_ss&expand=5236)
+   * [ ] [`_mm_mask3_fnmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_round_sd&expand=5236)
+   * [ ] [`_mm_mask3_fnmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_round_ss&expand=5236)
+   * [ ] [`_mm_mask3_fnmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_sd&expand=5236)
+   * [ ] [`_mm_mask3_fnmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmadd_ss&expand=5236)
+   * [ ] [`_mm_mask3_fnmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_round_sd&expand=5236)
+   * [ ] [`_mm_mask3_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_round_ss&expand=5236)
+   * [ ] [`_mm_mask3_fnmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_sd&expand=5236)
+   * [ ] [`_mm_mask3_fnmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_ss&expand=5236)
+   * [ ] [`_mm_mask_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_sd&expand=5236)
+   * [ ] [`_mm_mask_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_ss&expand=5236)
+   * [ ] [`_mm_mask_add_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_sd&expand=5236)
+   * [ ] [`_mm_mask_add_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_ss&expand=5236)
+   * [x] [`_mm_mask_cmp_round_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_sd_mask&expand=5236)
+   * [x] [`_mm_mask_cmp_round_ss_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_ss_mask&expand=5236)
+   * [x] [`_mm_mask_cmp_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_sd_mask&expand=5236)
+   * [x] [`_mm_mask_cmp_ss_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_ss_mask&expand=5236)
+   * [ ] [`_mm_mask_cvt_roundsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundsd_ss&expand=5236)
+   * [ ] [`_mm_mask_cvt_roundss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundss_sd&expand=5236)
+   * [ ] [`_mm_mask_cvtsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtsd_ss&expand=5236)
+   * [ ] [`_mm_mask_cvtss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtss_sd&expand=5236)
+   * [ ] [`_mm_mask_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_sd&expand=5236)
+   * [ ] [`_mm_mask_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_ss&expand=5236)
+   * [ ] [`_mm_mask_div_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_sd&expand=5236)
+   * [ ] [`_mm_mask_div_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_ss&expand=5236)
+   * [ ] [`_mm_mask_fixupimm_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_round_sd&expand=5236)
+   * [ ] [`_mm_mask_fixupimm_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_round_ss&expand=5236)
+   * [ ] [`_mm_mask_fixupimm_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_sd&expand=5236)
+   * [ ] [`_mm_mask_fixupimm_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_ss&expand=5236)
+   * [ ] [`_mm_mask_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_sd&expand=5236)
+   * [ ] [`_mm_mask_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_ss&expand=5236)
+   * [ ] [`_mm_mask_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_sd&expand=5236)
+   * [ ] [`_mm_mask_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_ss&expand=5236)
+   * [ ] [`_mm_mask_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_round_sd&expand=5236)
+   * [ ] [`_mm_mask_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_round_ss&expand=5236)
+   * [ ] [`_mm_mask_fmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_sd&expand=5236)
+   * [ ] [`_mm_mask_fmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_ss&expand=5236)
+   * [ ] [`_mm_mask_fnmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_round_sd&expand=5236)
+   * [ ] [`_mm_mask_fnmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_round_ss&expand=5236)
+   * [ ] [`_mm_mask_fnmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_sd&expand=5236)
+   * [ ] [`_mm_mask_fnmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmadd_ss&expand=5236)
+   * [ ] [`_mm_mask_fnmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_round_sd&expand=5236)
+   * [ ] [`_mm_mask_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_round_ss&expand=5236)
+   * [ ] [`_mm_mask_fnmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_sd&expand=5236)
+   * [ ] [`_mm_mask_fnmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_ss&expand=5236)
+   * [ ] [`_mm_mask_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_sd&expand=5236)
+   * [ ] [`_mm_mask_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_ss&expand=5236)
+   * [ ] [`_mm_mask_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_sd&expand=5236)
+   * [ ] [`_mm_mask_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_ss&expand=5236)
+   * [ ] [`_mm_mask_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_sd&expand=5236)
+   * [ ] [`_mm_mask_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_ss&expand=5236)
+   * [ ] [`_mm_mask_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_sd&expand=5236)
+   * [ ] [`_mm_mask_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_ss&expand=5236)
+   * [ ] [`_mm_mask_load_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_sd&expand=5236)
+   * [ ] [`_mm_mask_load_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_ss&expand=5236)
+   * [ ] [`_mm_mask_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_sd&expand=5236)
+   * [ ] [`_mm_mask_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_ss&expand=5236)
+   * [ ] [`_mm_mask_max_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_sd&expand=5236)
+   * [ ] [`_mm_mask_max_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_ss&expand=5236)
+   * [ ] [`_mm_mask_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_sd&expand=5236)
+   * [ ] [`_mm_mask_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_ss&expand=5236)
+   * [ ] [`_mm_mask_min_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_sd&expand=5236)
+   * [ ] [`_mm_mask_min_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_ss&expand=5236)
+   * [ ] [`_mm_mask_move_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sd&expand=5236)
+   * [ ] [`_mm_mask_move_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_ss&expand=5236)
+   * [ ] [`_mm_mask_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_sd&expand=5236)
+   * [ ] [`_mm_mask_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_ss&expand=5236)
+   * [ ] [`_mm_mask_mul_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_sd&expand=5236)
+   * [ ] [`_mm_mask_mul_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_ss&expand=5236)
+   * [ ] [`_mm_mask_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp14_sd&expand=5236)
+   * [ ] [`_mm_mask_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp14_ss&expand=5236)
+   * [ ] [`_mm_mask_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_sd&expand=5236)
+   * [ ] [`_mm_mask_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_ss&expand=5236)
+   * [ ] [`_mm_mask_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_sd&expand=5236)
+   * [ ] [`_mm_mask_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_ss&expand=5236)
+   * [ ] [`_mm_mask_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt14_sd&expand=5236)
+   * [ ] [`_mm_mask_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt14_ss&expand=5236)
+   * [ ] [`_mm_mask_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_sd&expand=5236)
+   * [ ] [`_mm_mask_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_ss&expand=5236)
+   * [ ] [`_mm_mask_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_sd&expand=5236)
+   * [ ] [`_mm_mask_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_ss&expand=5236)
+   * [ ] [`_mm_mask_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_sd&expand=5236)
+   * [ ] [`_mm_mask_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_ss&expand=5236)
+   * [ ] [`_mm_mask_sqrt_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_sd&expand=5236)
+   * [ ] [`_mm_mask_sqrt_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_ss&expand=5236)
+   * [ ] [`_mm_mask_store_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_sd&expand=5236)
+   * [ ] [`_mm_mask_store_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_ss&expand=5236)
+   * [ ] [`_mm_mask_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_sd&expand=5236)
+   * [ ] [`_mm_mask_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_ss&expand=5236)
+   * [ ] [`_mm_mask_sub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_sd&expand=5236)
+   * [ ] [`_mm_mask_sub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_ss&expand=5236)
+   * [ ] [`_mm_maskz_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_add_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_sd&expand=5236)
+   * [ ] [`_mm_maskz_add_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_ss&expand=5236)
+   * [ ] [`_mm_maskz_cvt_roundsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundsd_ss&expand=5236)
+   * [ ] [`_mm_maskz_cvt_roundss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundss_sd&expand=5236)
+   * [ ] [`_mm_maskz_cvtsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtsd_ss&expand=5236)
+   * [ ] [`_mm_maskz_cvtss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtss_sd&expand=5236)
+   * [ ] [`_mm_maskz_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_div_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_sd&expand=5236)
+   * [ ] [`_mm_maskz_div_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_ss&expand=5236)
+   * [ ] [`_mm_maskz_fixupimm_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_fixupimm_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_fixupimm_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_sd&expand=5236)
+   * [ ] [`_mm_maskz_fixupimm_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_ss&expand=5236)
+   * [ ] [`_mm_maskz_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_sd&expand=5236)
+   * [ ] [`_mm_maskz_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_ss&expand=5236)
+   * [ ] [`_mm_maskz_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_fmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_sd&expand=5236)
+   * [ ] [`_mm_maskz_fmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_ss&expand=5236)
+   * [ ] [`_mm_maskz_fnmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_fnmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_fnmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_sd&expand=5236)
+   * [ ] [`_mm_maskz_fnmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmadd_ss&expand=5236)
+   * [ ] [`_mm_maskz_fnmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_fnmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_sd&expand=5236)
+   * [ ] [`_mm_maskz_fnmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_ss&expand=5236)
+   * [ ] [`_mm_maskz_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_sd&expand=5236)
+   * [ ] [`_mm_maskz_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_ss&expand=5236)
+   * [ ] [`_mm_maskz_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_sd&expand=5236)
+   * [ ] [`_mm_maskz_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_ss&expand=5236)
+   * [ ] [`_mm_maskz_load_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_sd&expand=5236)
+   * [ ] [`_mm_maskz_load_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_ss&expand=5236)
+   * [ ] [`_mm_maskz_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_max_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_sd&expand=5236)
+   * [ ] [`_mm_maskz_max_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_ss&expand=5236)
+   * [ ] [`_mm_maskz_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_min_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_sd&expand=5236)
+   * [ ] [`_mm_maskz_min_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_ss&expand=5236)
+   * [ ] [`_mm_maskz_move_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sd&expand=5236)
+   * [ ] [`_mm_maskz_move_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_ss&expand=5236)
+   * [ ] [`_mm_maskz_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_mul_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_sd&expand=5236)
+   * [ ] [`_mm_maskz_mul_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_ss&expand=5236)
+   * [ ] [`_mm_maskz_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp14_sd&expand=5236)
+   * [ ] [`_mm_maskz_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp14_ss&expand=5236)
+   * [ ] [`_mm_maskz_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_sd&expand=5236)
+   * [ ] [`_mm_maskz_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_ss&expand=5236)
+   * [ ] [`_mm_maskz_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt14_sd&expand=5236)
+   * [ ] [`_mm_maskz_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt14_ss&expand=5236)
+   * [ ] [`_mm_maskz_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_sd&expand=5236)
+   * [ ] [`_mm_maskz_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_ss&expand=5236)
+   * [ ] [`_mm_maskz_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_sqrt_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_sd&expand=5236)
+   * [ ] [`_mm_maskz_sqrt_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_ss&expand=5236)
+   * [ ] [`_mm_maskz_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_sd&expand=5236)
+   * [ ] [`_mm_maskz_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_ss&expand=5236)
+   * [ ] [`_mm_maskz_sub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_sd&expand=5236)
+   * [ ] [`_mm_maskz_sub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_ss&expand=5236)
+   * [ ] [`_mm_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_sd&expand=5236)
+   * [ ] [`_mm_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_ss&expand=5236)
+   * [ ] [`_mm_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_sd&expand=5236)
+   * [ ] [`_mm_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_ss&expand=5236)
+   * [ ] [`_mm_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_sd&expand=5236)
+   * [ ] [`_mm_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_ss&expand=5236)
+   * [ ] [`_mm_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp14_sd&expand=5236)
+   * [ ] [`_mm_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp14_ss&expand=5236)
+   * [ ] [`_mm_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_sd&expand=5236)
+   * [ ] [`_mm_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_ss&expand=5236)
+   * [ ] [`_mm_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_sd&expand=5236)
+   * [ ] [`_mm_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_ss&expand=5236)
+   * [ ] [`_mm_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt14_sd&expand=5236)
+   * [ ] [`_mm_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt14_ss&expand=5236)
+   * [ ] [`_mm_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_sd&expand=5236)
+   * [ ] [`_mm_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_ss&expand=5236)
+   * [ ] [`_mm_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_sd&expand=5236)
+   * [ ] [`_mm_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_ss&expand=5236)
+   * [ ] [`_mm_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_sd&expand=5236)
+   * [ ] [`_mm_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_ss&expand=5236)
+   * [ ] [`_mm_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_sd&expand=5236)
+   * [ ] [`_mm_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_ss&expand=5236)
+ 
+ </p>
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/build.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/build.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/build.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/build.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,17 ----
+ use std::env;
+ 
+ fn main() {
+     println!("cargo:rustc-cfg=core_arch_docs");
+ 
+     // Used to tell our `#[assert_instr]` annotations that all simd intrinsics
+     // are available to test their codegen, since some are gated behind an extra
+     // `-Ctarget-feature=+unimplemented-simd128` that doesn't have any
+     // equivalent in `#[target_feature]` right now.
+     println!("cargo:rerun-if-env-changed=RUSTFLAGS");
+     if env::var("RUSTFLAGS")
+         .unwrap_or_default()
+         .contains("unimplemented-simd128")
+     {
+         println!("cargo:rustc-cfg=all_simd");
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/rustfmt.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/rustfmt.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/rustfmt.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/rustfmt.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3 ----
+ ignore = [
+     "src/simd.rs",
+ ]
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,45 ----
+ extern "C" {
+     #[link_name = "llvm.aarch64.crc32x"]
+     fn crc32x_(crc: u32, data: u64) -> u32;
+ 
+     #[link_name = "llvm.aarch64.crc32cx"]
+     fn crc32cx_(crc: u32, data: u64) -> u32;
+ }
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// CRC32 single round checksum for quad words (64 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(test, assert_instr(crc32x))]
+ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
+     crc32x_(crc, data)
+ }
+ 
+ /// CRC32-C single round checksum for quad words (64 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(test, assert_instr(crc32cx))]
+ pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
+     crc32cx_(crc, data)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::{aarch64::*, simd::*};
+     use std::mem;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32d() {
+         assert_eq!(__crc32d(0, 0), 0);
+         assert_eq!(__crc32d(0, 18446744073709551615), 1147535477);
+     }
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32cd() {
+         assert_eq!(__crc32cd(0, 0), 0);
+         assert_eq!(__crc32cd(0, 18446744073709551615), 3293575501);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,331 ----
+ use crate::core_arch::arm::{uint32x4_t, uint8x16_t};
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.aarch64.crypto.aese"]
+     fn vaeseq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
+     #[link_name = "llvm.aarch64.crypto.aesd"]
+     fn vaesdq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
+     #[link_name = "llvm.aarch64.crypto.aesmc"]
+     fn vaesmcq_u8_(data: uint8x16_t) -> uint8x16_t;
+     #[link_name = "llvm.aarch64.crypto.aesimc"]
+     fn vaesimcq_u8_(data: uint8x16_t) -> uint8x16_t;
+ 
+     #[link_name = "llvm.aarch64.crypto.sha1h"]
+     fn vsha1h_u32_(hash_e: u32) -> u32;
+     #[link_name = "llvm.aarch64.crypto.sha1su0"]
+     fn vsha1su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha1su1"]
+     fn vsha1su1q_u32_(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha1c"]
+     fn vsha1cq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha1p"]
+     fn vsha1pq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha1m"]
+     fn vsha1mq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
+ 
+     #[link_name = "llvm.aarch64.crypto.sha256h"]
+     fn vsha256hq_u32_(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha256h2"]
+     fn vsha256h2q_u32_(hash_efgh: uint32x4_t, hash_abcd: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha256su0"]
+     fn vsha256su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.crypto.sha256su1"]
+     fn vsha256su1q_u32_(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
+ }
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// AES single round encryption.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(aese))]
+ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
+     vaeseq_u8_(data, key)
+ }
+ 
+ /// AES single round decryption.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(aesd))]
+ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
+     vaesdq_u8_(data, key)
+ }
+ 
+ /// AES mix columns.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(aesmc))]
+ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
+     vaesmcq_u8_(data)
+ }
+ 
+ /// AES inverse mix columns.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(aesimc))]
+ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
+     vaesimcq_u8_(data)
+ }
+ 
+ /// SHA1 fixed rotate.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha1h))]
+ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
+     vsha1h_u32_(hash_e)
+ }
+ 
+ /// SHA1 hash update accelerator, choose.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha1c))]
+ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
+     vsha1cq_u32_(hash_abcd, hash_e, wk)
+ }
+ 
+ /// SHA1 hash update accelerator, majority.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha1m))]
+ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
+     vsha1mq_u32_(hash_abcd, hash_e, wk)
+ }
+ 
+ /// SHA1 hash update accelerator, parity.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha1p))]
+ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
+     vsha1pq_u32_(hash_abcd, hash_e, wk)
+ }
+ 
+ /// SHA1 schedule update accelerator, first part.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha1su0))]
+ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
+     vsha1su0q_u32_(w0_3, w4_7, w8_11)
+ }
+ 
+ /// SHA1 schedule update accelerator, second part.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha1su1))]
+ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
+     vsha1su1q_u32_(tw0_3, w12_15)
+ }
+ 
+ /// SHA256 hash update accelerator.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha256h))]
+ pub unsafe fn vsha256hq_u32(
+     hash_abcd: uint32x4_t,
+     hash_efgh: uint32x4_t,
+     wk: uint32x4_t,
+ ) -> uint32x4_t {
+     vsha256hq_u32_(hash_abcd, hash_efgh, wk)
+ }
+ 
+ /// SHA256 hash update accelerator, upper part.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha256h2))]
+ pub unsafe fn vsha256h2q_u32(
+     hash_efgh: uint32x4_t,
+     hash_abcd: uint32x4_t,
+     wk: uint32x4_t,
+ ) -> uint32x4_t {
+     vsha256h2q_u32_(hash_efgh, hash_abcd, wk)
+ }
+ 
+ /// SHA256 schedule update accelerator, first part.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha256su0))]
+ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
+     vsha256su0q_u32_(w0_3, w4_7)
+ }
+ 
+ /// SHA256 schedule update accelerator, second part.
+ #[inline]
+ #[target_feature(enable = "crypto")]
+ #[cfg_attr(test, assert_instr(sha256su1))]
+ pub unsafe fn vsha256su1q_u32(
+     tw0_3: uint32x4_t,
+     w8_11: uint32x4_t,
+     w12_15: uint32x4_t,
+ ) -> uint32x4_t {
+     vsha256su1q_u32_(tw0_3, w8_11, w12_15)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::{aarch64::*, simd::*};
+     use std::mem;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vaeseq_u8() {
+         let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
+         let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let r: u8x16 = mem::transmute(vaeseq_u8(data, key));
+         assert_eq!(
+             r,
+             u8x16::new(
+                 124, 123, 124, 118, 124, 123, 124, 197, 124, 123, 124, 118, 124, 123, 124, 197
+             )
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vaesdq_u8() {
+         let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
+         let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let r: u8x16 = mem::transmute(vaesdq_u8(data, key));
+         assert_eq!(
+             r,
+             u8x16::new(9, 213, 9, 251, 9, 213, 9, 56, 9, 213, 9, 251, 9, 213, 9, 56)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vaesmcq_u8() {
+         let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
+         let r: u8x16 = mem::transmute(vaesmcq_u8(data));
+         assert_eq!(
+             r,
+             u8x16::new(3, 4, 9, 10, 15, 8, 21, 30, 3, 4, 9, 10, 15, 8, 21, 30)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vaesimcq_u8() {
+         let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
+         let r: u8x16 = mem::transmute(vaesimcq_u8(data));
+         assert_eq!(
+             r,
+             u8x16::new(43, 60, 33, 50, 103, 80, 125, 70, 43, 60, 33, 50, 103, 80, 125, 70)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha1h_u32() {
+         assert_eq!(vsha1h_u32(0x1234), 0x048d);
+         assert_eq!(vsha1h_u32(0x5678), 0x159e);
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha1su0q_u32() {
+         let r: u32x4 = mem::transmute(vsha1su0q_u32(
+             mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
+             mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
+             mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
+         ));
+         assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha1su1q_u32() {
+         let r: u32x4 = mem::transmute(vsha1su1q_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0x00008898, 0x00019988, 0x00008898, 0x0000acd0)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha1cq_u32() {
+         let r: u32x4 = mem::transmute(vsha1cq_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             0x1234,
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0x8a32cbd8, 0x0c518a96, 0x0018a081, 0x0000c168)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha1pq_u32() {
+         let r: u32x4 = mem::transmute(vsha1pq_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             0x1234,
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0x469f0ba3, 0x0a326147, 0x80145d7f, 0x00009f47)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha1mq_u32() {
+         let r: u32x4 = mem::transmute(vsha1mq_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             0x1234,
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0xaa39693b, 0x0d51bf84, 0x001aa109, 0x0000d278)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha256hq_u32() {
+         let r: u32x4 = mem::transmute(vsha256hq_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0x05e9aaa8, 0xec5f4c02, 0x20a1ea61, 0x28738cef)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha256h2q_u32() {
+         let r: u32x4 = mem::transmute(vsha256h2q_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0x3745362e, 0x2fb51d00, 0xbd4c529b, 0x968b8516)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha256su0q_u32() {
+         let r: u32x4 = mem::transmute(vsha256su0q_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0xe59e1c97, 0x5eaf68da, 0xd7bcb51f, 0x6c8de152)
+         );
+     }
+ 
+     #[simd_test(enable = "crypto")]
+     unsafe fn test_vsha256su1q_u32() {
+         let r: u32x4 = mem::transmute(vsha256su1q_u32(
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+             mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
+         ));
+         assert_eq!(
+             r,
+             u32x4::new(0x5e09e8d2, 0x74a6f16b, 0xc966606b, 0xa686ee9f)
+         );
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,40 ----
+ //! AArch64 intrinsics.
+ //!
+ //! The reference for NEON is [ARM's NEON Intrinsics Reference][arm_ref]. The
+ //! [ARM's NEON Intrinsics Online Database][arm_dat] is also useful.
+ //!
+ //! [arm_ref]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
+ //! [arm_dat]: https://developer.arm.com/technologies/neon/intrinsics
+ 
+ mod v8;
+ pub use self::v8::*;
+ 
+ mod neon;
+ pub use self::neon::*;
+ 
+ mod crypto;
+ pub use self::crypto::*;
+ 
+ mod tme;
+ pub use self::tme::*;
+ 
+ mod crc;
+ pub use self::crc::*;
+ 
+ mod prefetch;
+ pub use self::prefetch::*;
+ 
+ pub use super::acle::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Generates the trap instruction `BRK 1`
+ #[cfg_attr(test, assert_instr(brk))]
+ #[inline]
+ pub unsafe fn brk() -> ! {
+     crate::intrinsics::abort()
+ }
+ 
+ #[cfg(test)]
+ pub(crate) mod test_support;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,666 ----
+ // This code is automatically generated. DO NOT MODIFY.
+ //
+ // Instead, modify `crates/stdarch-gen/neon.spec` and run the following command to re-generate this file:
+ //
+ // ```
+ // OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec
+ // ```
+ use super::*;
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmeq))]
+ pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmeq))]
+ pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmeq))]
+ pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmeq))]
+ pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmeq))]
+ pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmeq))]
+ pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Floating-point compare equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmeq))]
+ pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Floating-point compare equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmeq))]
+ pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmgt))]
+ pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmgt))]
+ pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhi))]
+ pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhi))]
+ pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Floating-point compare greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmgt))]
+ pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Floating-point compare greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmgt))]
+ pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmgt))]
+ pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmgt))]
+ pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhi))]
+ pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhi))]
+ pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Floating-point compare less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmgt))]
+ pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Floating-point compare less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmgt))]
+ pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmge))]
+ pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmge))]
+ pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhs))]
+ pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhs))]
+ pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_le(a, b)
+ }
+ 
+ /// Floating-point compare less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmge))]
+ pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
+     simd_le(a, b)
+ }
+ 
+ /// Floating-point compare less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmge))]
+ pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmge))]
+ pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmge))]
+ pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhs))]
+ pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(cmhs))]
+ pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Floating-point compare greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmge))]
+ pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Floating-point compare greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcmge))]
+ pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmul))]
+ pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmul))]
+ pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fsub))]
+ pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fsub))]
+ pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
+     simd_sub(a, b)
+ }
+ 
+ #[cfg(test)]
+ mod test {
+     use super::*;
+     use crate::core_arch::simd::*;
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u64() {
+         let a: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u64() {
+         let a: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0x01);
+         let b: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0x01);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let b: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0);
+         let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s64() {
+         let a: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s64() {
+         let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x01);
+         let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x01);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, -9223372036854775808);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0);
+         let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_p64() {
+         let a: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_p64() {
+         let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x01);
+         let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x01);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x7F_FF_FF_FF_FF_FF_FF_FF);
+         let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, -9223372036854775808);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0);
+         let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_f64() {
+         let a: f64 = 1.2;
+         let b: f64 = 1.2;
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vceq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_f64() {
+         let a: f64x2 = f64x2::new(1.2, 3.4);
+         let b: f64x2 = f64x2::new(1.2, 3.4);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vceqq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s64() {
+         let a: i64x1 = i64x1::new(1);
+         let b: i64x1 = i64x1::new(0);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcgt_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s64() {
+         let a: i64x2 = i64x2::new(1, 2);
+         let b: i64x2 = i64x2::new(0, 1);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcgtq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u64() {
+         let a: u64x1 = u64x1::new(1);
+         let b: u64x1 = u64x1::new(0);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcgt_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u64() {
+         let a: u64x2 = u64x2::new(1, 2);
+         let b: u64x2 = u64x2::new(0, 1);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcgtq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_f64() {
+         let a: f64 = 1.2;
+         let b: f64 = 0.1;
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcgt_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_f64() {
+         let a: f64x2 = f64x2::new(1.2, 2.3);
+         let b: f64x2 = f64x2::new(0.1, 1.2);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcgtq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s64() {
+         let a: i64x1 = i64x1::new(0);
+         let b: i64x1 = i64x1::new(1);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vclt_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s64() {
+         let a: i64x2 = i64x2::new(0, 1);
+         let b: i64x2 = i64x2::new(1, 2);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcltq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u64() {
+         let a: u64x1 = u64x1::new(0);
+         let b: u64x1 = u64x1::new(1);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vclt_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u64() {
+         let a: u64x2 = u64x2::new(0, 1);
+         let b: u64x2 = u64x2::new(1, 2);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcltq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_f64() {
+         let a: f64 = 0.1;
+         let b: f64 = 1.2;
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vclt_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_f64() {
+         let a: f64x2 = f64x2::new(0.1, 1.2);
+         let b: f64x2 = f64x2::new(1.2, 2.3);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcltq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s64() {
+         let a: i64x1 = i64x1::new(0);
+         let b: i64x1 = i64x1::new(1);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcle_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s64() {
+         let a: i64x2 = i64x2::new(0, 1);
+         let b: i64x2 = i64x2::new(1, 2);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcleq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u64() {
+         let a: u64x1 = u64x1::new(0);
+         let b: u64x1 = u64x1::new(1);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcle_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u64() {
+         let a: u64x2 = u64x2::new(0, 1);
+         let b: u64x2 = u64x2::new(1, 2);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcleq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_f64() {
+         let a: f64 = 0.1;
+         let b: f64 = 1.2;
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcle_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_f64() {
+         let a: f64x2 = f64x2::new(0.1, 1.2);
+         let b: f64x2 = f64x2::new(1.2, 2.3);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcleq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s64() {
+         let a: i64x1 = i64x1::new(1);
+         let b: i64x1 = i64x1::new(0);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcge_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s64() {
+         let a: i64x2 = i64x2::new(1, 2);
+         let b: i64x2 = i64x2::new(0, 1);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcgeq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u64() {
+         let a: u64x1 = u64x1::new(1);
+         let b: u64x1 = u64x1::new(0);
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcge_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u64() {
+         let a: u64x2 = u64x2::new(1, 2);
+         let b: u64x2 = u64x2::new(0, 1);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcgeq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_f64() {
+         let a: f64 = 1.2;
+         let b: f64 = 0.1;
+         let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x1 = transmute(vcge_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_f64() {
+         let a: f64x2 = f64x2::new(1.2, 2.3);
+         let b: f64x2 = f64x2::new(0.1, 1.2);
+         let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF);
+         let r: u64x2 = transmute(vcgeq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_f64() {
+         let a: f64 = 1.0;
+         let b: f64 = 2.0;
+         let e: f64 = 2.0;
+         let r: f64 = transmute(vmul_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_f64() {
+         let a: f64x2 = f64x2::new(1.0, 2.0);
+         let b: f64x2 = f64x2::new(2.0, 3.0);
+         let e: f64x2 = f64x2::new(2.0, 6.0);
+         let r: f64x2 = transmute(vmulq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_f64() {
+         let a: f64 = 1.0;
+         let b: f64 = 1.0;
+         let e: f64 = 0.0;
+         let r: f64 = transmute(vsub_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_f64() {
+         let a: f64x2 = f64x2::new(1.0, 4.0);
+         let b: f64x2 = f64x2::new(1.0, 2.0);
+         let e: f64x2 = f64x2::new(0.0, 2.0);
+         let r: f64x2 = transmute(vsubq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3065 ----
+ //! ARMv8 ASIMD intrinsics
+ 
+ #![allow(non_camel_case_types)]
+ 
+ mod generated;
+ pub use self::generated::*;
+ 
+ // FIXME: replace neon with asimd
+ 
+ use crate::{
+     core_arch::{arm::*, simd_llvm::*},
+     mem::{transmute, zeroed},
+ };
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ types! {
+     /// ARM-specific 64-bit wide vector of one packed `f64`.
+     pub struct float64x1_t(f64); // FIXME: check this!
+     /// ARM-specific 128-bit wide vector of two packed `f64`.
+     pub struct float64x2_t(f64, f64);
+     /// ARM-specific 64-bit wide vector of one packed `p64`.
+     pub struct poly64x1_t(i64); // FIXME: check this!
+     /// ARM-specific 64-bit wide vector of one packed `p64`.
+     pub struct poly64_t(i64); // FIXME: check this!
+     /// ARM-specific 64-bit wide vector of two packed `p64`.
+     pub struct poly64x2_t(i64, i64); // FIXME: check this!
+     /// ARM-specific 128-bit wide vector of one packed `p64`.
+     pub struct poly128_t(i128); // FIXME: check this!
+ }
+ 
+ /// ARM-specific type containing two `int8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct int8x16x2_t(pub int8x16_t, pub int8x16_t);
+ /// ARM-specific type containing three `int8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct int8x16x3_t(pub int8x16_t, pub int8x16_t, pub int8x16_t);
+ /// ARM-specific type containing four `int8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct int8x16x4_t(pub int8x16_t, pub int8x16_t, pub int8x16_t, pub int8x16_t);
+ 
+ /// ARM-specific type containing two `uint8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct uint8x16x2_t(pub uint8x16_t, pub uint8x16_t);
+ /// ARM-specific type containing three `uint8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct uint8x16x3_t(pub uint8x16_t, pub uint8x16_t, pub uint8x16_t);
+ /// ARM-specific type containing four `uint8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct uint8x16x4_t(
+     pub uint8x16_t,
+     pub uint8x16_t,
+     pub uint8x16_t,
+     pub uint8x16_t,
+ );
+ 
+ /// ARM-specific type containing two `poly8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct poly8x16x2_t(pub poly8x16_t, pub poly8x16_t);
+ /// ARM-specific type containing three `poly8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct poly8x16x3_t(pub poly8x16_t, pub poly8x16_t, pub poly8x16_t);
+ /// ARM-specific type containing four `poly8x16_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct poly8x16x4_t(
+     pub poly8x16_t,
+     pub poly8x16_t,
+     pub poly8x16_t,
+     pub poly8x16_t,
+ );
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     // absolute value
+     #[link_name = "llvm.aarch64.neon.abs.i64"]
+     fn vabsd_s64_(a: i64) -> i64;
+     #[link_name = "llvm.aarch64.neon.abs.v1i64"]
+     fn vabs_s64_(a: int64x1_t) -> int64x1_t;
+     #[link_name = "llvm.aarch64.neon.abs.v2i64"]
+     fn vabsq_s64_(a: int64x2_t) -> int64x2_t;
+ 
+     #[link_name = "llvm.aarch64.neon.pmull64"]
+     fn vmull_p64_(a: i64, b: i64) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.addp.v8i16"]
+     fn vpaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     #[link_name = "llvm.aarch64.neon.addp.v4i32"]
+     fn vpaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     #[link_name = "llvm.aarch64.neon.addp.v16i8"]
+     fn vpaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.saddv.i32.v4i16"]
+     fn vaddv_s16_(a: int16x4_t) -> i16;
+     #[link_name = "llvm.aarch64.neon.saddv.i32.v2i32"]
+     fn vaddv_s32_(a: int32x2_t) -> i32;
+     #[link_name = "llvm.aarch64.neon.saddv.i32.v8i8"]
+     fn vaddv_s8_(a: int8x8_t) -> i8;
+     #[link_name = "llvm.aarch64.neon.uaddv.i32.v4i16"]
+     fn vaddv_u16_(a: uint16x4_t) -> u16;
+     #[link_name = "llvm.aarch64.neon.uaddv.i32.v2i32"]
+     fn vaddv_u32_(a: uint32x2_t) -> u32;
+     #[link_name = "llvm.aarch64.neon.uaddv.i32.v8i8"]
+     fn vaddv_u8_(a: uint8x8_t) -> u8;
+     #[link_name = "llvm.aarch64.neon.saddv.i32.v8i16"]
+     fn vaddvq_s16_(a: int16x8_t) -> i16;
+     #[link_name = "llvm.aarch64.neon.saddv.i32.v4i32"]
+     fn vaddvq_s32_(a: int32x4_t) -> i32;
+     #[link_name = "llvm.aarch64.neon.saddv.i32.v16i8"]
+     fn vaddvq_s8_(a: int8x16_t) -> i8;
+     #[link_name = "llvm.aarch64.neon.uaddv.i32.v8i16"]
+     fn vaddvq_u16_(a: uint16x8_t) -> u16;
+     #[link_name = "llvm.aarch64.neon.uaddv.i32.v4i32"]
+     fn vaddvq_u32_(a: uint32x4_t) -> u32;
+     #[link_name = "llvm.aarch64.neon.uaddv.i32.v16i8"]
+     fn vaddvq_u8_(a: uint8x16_t) -> u8;
+     #[link_name = "llvm.aarch64.neon.saddv.i64.v2i64"]
+     fn vaddvq_s64_(a: int64x2_t) -> i64;
+     #[link_name = "llvm.aarch64.neon.uaddv.i64.v2i64"]
+     fn vaddvq_u64_(a: uint64x2_t) -> u64;
+ 
+     #[link_name = "llvm.aarch64.neon.smaxv.i8.v8i8"]
+     fn vmaxv_s8_(a: int8x8_t) -> i8;
+     #[link_name = "llvm.aarch64.neon.smaxv.i8.6i8"]
+     fn vmaxvq_s8_(a: int8x16_t) -> i8;
+     #[link_name = "llvm.aarch64.neon.smaxv.i16.v4i16"]
+     fn vmaxv_s16_(a: int16x4_t) -> i16;
+     #[link_name = "llvm.aarch64.neon.smaxv.i16.v8i16"]
+     fn vmaxvq_s16_(a: int16x8_t) -> i16;
+     #[link_name = "llvm.aarch64.neon.smaxv.i32.v2i32"]
+     fn vmaxv_s32_(a: int32x2_t) -> i32;
+     #[link_name = "llvm.aarch64.neon.smaxv.i32.v4i32"]
+     fn vmaxvq_s32_(a: int32x4_t) -> i32;
+ 
+     #[link_name = "llvm.aarch64.neon.umaxv.i8.v8i8"]
+     fn vmaxv_u8_(a: uint8x8_t) -> u8;
+     #[link_name = "llvm.aarch64.neon.umaxv.i8.6i8"]
+     fn vmaxvq_u8_(a: uint8x16_t) -> u8;
+     #[link_name = "llvm.aarch64.neon.umaxv.i16.v4i16"]
+     fn vmaxv_u16_(a: uint16x4_t) -> u16;
+     #[link_name = "llvm.aarch64.neon.umaxv.i16.v8i16"]
+     fn vmaxvq_u16_(a: uint16x8_t) -> u16;
+     #[link_name = "llvm.aarch64.neon.umaxv.i32.v2i32"]
+     fn vmaxv_u32_(a: uint32x2_t) -> u32;
+     #[link_name = "llvm.aarch64.neon.umaxv.i32.v4i32"]
+     fn vmaxvq_u32_(a: uint32x4_t) -> u32;
+ 
+     #[link_name = "llvm.aarch64.neon.fmaxv.f32.v2f32"]
+     fn vmaxv_f32_(a: float32x2_t) -> f32;
+     #[link_name = "llvm.aarch64.neon.fmaxv.f32.v4f32"]
+     fn vmaxvq_f32_(a: float32x4_t) -> f32;
+     #[link_name = "llvm.aarch64.neon.fmaxv.f64.v2f64"]
+     fn vmaxvq_f64_(a: float64x2_t) -> f64;
+ 
+     #[link_name = "llvm.aarch64.neon.sminv.i8.v8i8"]
+     fn vminv_s8_(a: int8x8_t) -> i8;
+     #[link_name = "llvm.aarch64.neon.sminv.i8.6i8"]
+     fn vminvq_s8_(a: int8x16_t) -> i8;
+     #[link_name = "llvm.aarch64.neon.sminv.i16.v4i16"]
+     fn vminv_s16_(a: int16x4_t) -> i16;
+     #[link_name = "llvm.aarch64.neon.sminv.i16.v8i16"]
+     fn vminvq_s16_(a: int16x8_t) -> i16;
+     #[link_name = "llvm.aarch64.neon.sminv.i32.v2i32"]
+     fn vminv_s32_(a: int32x2_t) -> i32;
+     #[link_name = "llvm.aarch64.neon.sminv.i32.v4i32"]
+     fn vminvq_s32_(a: int32x4_t) -> i32;
+ 
+     #[link_name = "llvm.aarch64.neon.uminv.i8.v8i8"]
+     fn vminv_u8_(a: uint8x8_t) -> u8;
+     #[link_name = "llvm.aarch64.neon.uminv.i8.6i8"]
+     fn vminvq_u8_(a: uint8x16_t) -> u8;
+     #[link_name = "llvm.aarch64.neon.uminv.i16.v4i16"]
+     fn vminv_u16_(a: uint16x4_t) -> u16;
+     #[link_name = "llvm.aarch64.neon.uminv.i16.v8i16"]
+     fn vminvq_u16_(a: uint16x8_t) -> u16;
+     #[link_name = "llvm.aarch64.neon.uminv.i32.v2i32"]
+     fn vminv_u32_(a: uint32x2_t) -> u32;
+     #[link_name = "llvm.aarch64.neon.uminv.i32.v4i32"]
+     fn vminvq_u32_(a: uint32x4_t) -> u32;
+ 
+     #[link_name = "llvm.aarch64.neon.fminv.f32.v2f32"]
+     fn vminv_f32_(a: float32x2_t) -> f32;
+     #[link_name = "llvm.aarch64.neon.fminv.f32.v4f32"]
+     fn vminvq_f32_(a: float32x4_t) -> f32;
+     #[link_name = "llvm.aarch64.neon.fminv.f64.v2f64"]
+     fn vminvq_f64_(a: float64x2_t) -> f64;
+ 
+     #[link_name = "llvm.aarch64.neon.sminp.v16i8"]
+     fn vpminq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     #[link_name = "llvm.aarch64.neon.sminp.v8i16"]
+     fn vpminq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     #[link_name = "llvm.aarch64.neon.sminp.v4i32"]
+     fn vpminq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     #[link_name = "llvm.aarch64.neon.uminp.v16i8"]
+     fn vpminq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     #[link_name = "llvm.aarch64.neon.uminp.v8i16"]
+     fn vpminq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     #[link_name = "llvm.aarch64.neon.uminp.v4i32"]
+     fn vpminq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.neon.fminp.4f32"]
+     fn vpminq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+     #[link_name = "llvm.aarch64.neon.fminp.v2f64"]
+     fn vpminq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t;
+ 
+     #[link_name = "llvm.aarch64.neon.smaxp.v16i8"]
+     fn vpmaxq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     #[link_name = "llvm.aarch64.neon.smaxp.v8i16"]
+     fn vpmaxq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     #[link_name = "llvm.aarch64.neon.smaxp.v4i32"]
+     fn vpmaxq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     #[link_name = "llvm.aarch64.neon.umaxp.v16i8"]
+     fn vpmaxq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     #[link_name = "llvm.aarch64.neon.umaxp.v8i16"]
+     fn vpmaxq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     #[link_name = "llvm.aarch64.neon.umaxp.v4i32"]
+     fn vpmaxq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.neon.fmaxp.4f32"]
+     fn vpmaxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+     #[link_name = "llvm.aarch64.neon.fmaxp.v2f64"]
+     fn vpmaxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbl1.v8i8"]
+     fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbl1.v16i8"]
+     fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbx1.v8i8"]
+     fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbx1.v16i8"]
+     fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbl2.v8i8"]
+     fn vqtbl2(a0: int8x16_t, a1: int8x16_t, b: uint8x8_t) -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbl2.v16i8"]
+     fn vqtbl2q(a0: int8x16_t, a1: int8x16_t, b: uint8x16_t) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbx2.v8i8"]
+     fn vqtbx2(a: int8x8_t, b0: int8x16_t, b1: int8x16_t, c: uint8x8_t) -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbx2.v16i8"]
+     fn vqtbx2q(a: int8x16_t, b0: int8x16_t, b1: int8x16_t, c: uint8x16_t) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbl3.v8i8"]
+     fn vqtbl3(a0: int8x16_t, a1: int8x16_t, a2: int8x16_t, b: uint8x8_t) -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbl3.v16i8"]
+     fn vqtbl3q(a0: int8x16_t, a1: int8x16_t, a2: int8x16_t, b: uint8x16_t) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbx3.v8i8"]
+     fn vqtbx3(a: int8x8_t, b0: int8x16_t, b1: int8x16_t, b2: int8x16_t, c: uint8x8_t) -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbx3.v16i8"]
+     fn vqtbx3q(
+         a: int8x16_t,
+         b0: int8x16_t,
+         b1: int8x16_t,
+         b2: int8x16_t,
+         c: uint8x16_t,
+     ) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbl4.v8i8"]
+     fn vqtbl4(a0: int8x16_t, a1: int8x16_t, a2: int8x16_t, a3: int8x16_t, b: uint8x8_t)
+         -> int8x8_t;
+     #[link_name = "llvm.aarch64.neon.tbl4.v16i8"]
+     fn vqtbl4q(
+         a0: int8x16_t,
+         a1: int8x16_t,
+         a2: int8x16_t,
+         a3: int8x16_t,
+         b: uint8x16_t,
+     ) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbx4.v8i8"]
+     fn vqtbx4(
+         a: int8x8_t,
+         b0: int8x16_t,
+         b1: int8x16_t,
+         b2: int8x16_t,
+         b3: int8x16_t,
+         c: uint8x8_t,
+     ) -> int8x8_t;
+ 
+     #[link_name = "llvm.aarch64.neon.tbx4.v16i8"]
+     fn vqtbx4q(
+         a: int8x16_t,
+         b0: int8x16_t,
+         b1: int8x16_t,
+         b2: int8x16_t,
+         b3: int8x16_t,
+         c: uint8x16_t,
+     ) -> int8x16_t;
+ 
+     #[link_name = "llvm.aarch64.neon.fcvtzu.v4i32.v4f32"]
+     fn vcvtq_u32_f32_(a: float32x4_t) -> uint32x4_t;
+     #[link_name = "llvm.aarch64.neon.fcvtzs.v4i32.v4f32"]
+     fn vcvtq_s32_f32_(a: float32x4_t) -> int32x4_t;
+ }
+ 
+ /// Absolute Value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(abs))]
+ pub unsafe fn vabsd_s64(a: i64) -> i64 {
+     vabsd_s64_(a)
+ }
+ /// Absolute Value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(abs))]
+ pub unsafe fn vabs_s64(a: int64x1_t) -> int64x1_t {
+     vabs_s64_(a)
+ }
+ /// Absolute Value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(abs))]
+ pub unsafe fn vabsq_s64(a: int64x2_t) -> int64x2_t {
+     vabsq_s64_(a)
+ }
+ 
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     vpaddq_s16_(a, b)
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     transmute(vpaddq_s16_(transmute(a), transmute(b)))
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     vpaddq_s32_(a, b)
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     transmute(vpaddq_s32_(transmute(a), transmute(b)))
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     vpaddq_s8_(a, b)
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     transmute(vpaddq_s8_(transmute(a), transmute(b)))
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddd_s64(a: int64x2_t) -> i64 {
+     transmute(vaddvq_u64_(transmute(a)))
+ }
+ /// Add pairwise
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vpaddd_u64(a: uint64x2_t) -> u64 {
+     transmute(vaddvq_u64_(transmute(a)))
+ }
+ 
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddv_s16(a: int16x4_t) -> i16 {
+     vaddv_s16_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vaddv_s32(a: int32x2_t) -> i32 {
+     vaddv_s32_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddv_s8(a: int8x8_t) -> i8 {
+     vaddv_s8_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddv_u16(a: uint16x4_t) -> u16 {
+     vaddv_u16_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vaddv_u32(a: uint32x2_t) -> u32 {
+     vaddv_u32_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddv_u8(a: uint8x8_t) -> u8 {
+     vaddv_u8_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddvq_s16(a: int16x8_t) -> i16 {
+     vaddvq_s16_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddvq_s32(a: int32x4_t) -> i32 {
+     vaddvq_s32_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddvq_s8(a: int8x16_t) -> i8 {
+     vaddvq_s8_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddvq_u16(a: uint16x8_t) -> u16 {
+     vaddvq_u16_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddvq_u32(a: uint32x4_t) -> u32 {
+     vaddvq_u32_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addv))]
+ pub unsafe fn vaddvq_u8(a: uint8x16_t) -> u8 {
+     vaddvq_u8_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vaddvq_s64(a: int64x2_t) -> i64 {
+     vaddvq_s64_(a)
+ }
+ /// Add across vector
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(addp))]
+ pub unsafe fn vaddvq_u64(a: uint64x2_t) -> u64 {
+     vaddvq_u64_(a)
+ }
+ 
+ /// Polynomial multiply long
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(pmull))]
+ pub unsafe fn vmull_p64(a: poly64_t, b: poly64_t) -> poly128_t {
+     transmute(vmull_p64_(transmute(a), transmute(b)))
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fadd))]
+ pub unsafe fn vadd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fadd))]
+ pub unsafe fn vaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(add))]
+ pub unsafe fn vadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(add))]
+ pub unsafe fn vadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(add))]
+ pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 {
+     let a: int64x1_t = transmute(a);
+     let b: int64x1_t = transmute(b);
+     simd_extract(simd_add(a, b), 0)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(add))]
+ pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 {
+     let a: uint64x1_t = transmute(a);
+     let b: uint64x1_t = transmute(b);
+     simd_extract(simd_add(a, b), 0)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxv))]
+ pub unsafe fn vmaxv_s8(a: int8x8_t) -> i8 {
+     vmaxv_s8_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxv))]
+ pub unsafe fn vmaxvq_s8(a: int8x16_t) -> i8 {
+     vmaxvq_s8_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxv))]
+ pub unsafe fn vmaxv_s16(a: int16x4_t) -> i16 {
+     vmaxv_s16_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxv))]
+ pub unsafe fn vmaxvq_s16(a: int16x8_t) -> i16 {
+     vmaxvq_s16_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxp))]
+ pub unsafe fn vmaxv_s32(a: int32x2_t) -> i32 {
+     vmaxv_s32_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxv))]
+ pub unsafe fn vmaxvq_s32(a: int32x4_t) -> i32 {
+     vmaxvq_s32_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxv))]
+ pub unsafe fn vmaxv_u8(a: uint8x8_t) -> u8 {
+     vmaxv_u8_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxv))]
+ pub unsafe fn vmaxvq_u8(a: uint8x16_t) -> u8 {
+     vmaxvq_u8_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxv))]
+ pub unsafe fn vmaxv_u16(a: uint16x4_t) -> u16 {
+     vmaxv_u16_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxv))]
+ pub unsafe fn vmaxvq_u16(a: uint16x8_t) -> u16 {
+     vmaxvq_u16_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxp))]
+ pub unsafe fn vmaxv_u32(a: uint32x2_t) -> u32 {
+     vmaxv_u32_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxv))]
+ pub unsafe fn vmaxvq_u32(a: uint32x4_t) -> u32 {
+     vmaxvq_u32_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmaxp))]
+ pub unsafe fn vmaxv_f32(a: float32x2_t) -> f32 {
+     vmaxv_f32_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmaxv))]
+ pub unsafe fn vmaxvq_f32(a: float32x4_t) -> f32 {
+     vmaxvq_f32_(a)
+ }
+ 
+ /// Horizontal vector max.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmaxp))]
+ pub unsafe fn vmaxvq_f64(a: float64x2_t) -> f64 {
+     vmaxvq_f64_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminv))]
+ pub unsafe fn vminv_s8(a: int8x8_t) -> i8 {
+     vminv_s8_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminv))]
+ pub unsafe fn vminvq_s8(a: int8x16_t) -> i8 {
+     vminvq_s8_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminv))]
+ pub unsafe fn vminv_s16(a: int16x4_t) -> i16 {
+     vminv_s16_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminv))]
+ pub unsafe fn vminvq_s16(a: int16x8_t) -> i16 {
+     vminvq_s16_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminp))]
+ pub unsafe fn vminv_s32(a: int32x2_t) -> i32 {
+     vminv_s32_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminv))]
+ pub unsafe fn vminvq_s32(a: int32x4_t) -> i32 {
+     vminvq_s32_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminv))]
+ pub unsafe fn vminv_u8(a: uint8x8_t) -> u8 {
+     vminv_u8_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminv))]
+ pub unsafe fn vminvq_u8(a: uint8x16_t) -> u8 {
+     vminvq_u8_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminv))]
+ pub unsafe fn vminv_u16(a: uint16x4_t) -> u16 {
+     vminv_u16_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminv))]
+ pub unsafe fn vminvq_u16(a: uint16x8_t) -> u16 {
+     vminvq_u16_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminp))]
+ pub unsafe fn vminv_u32(a: uint32x2_t) -> u32 {
+     vminv_u32_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminv))]
+ pub unsafe fn vminvq_u32(a: uint32x4_t) -> u32 {
+     vminvq_u32_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fminp))]
+ pub unsafe fn vminv_f32(a: float32x2_t) -> f32 {
+     vminv_f32_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fminv))]
+ pub unsafe fn vminvq_f32(a: float32x4_t) -> f32 {
+     vminvq_f32_(a)
+ }
+ 
+ /// Horizontal vector min.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fminp))]
+ pub unsafe fn vminvq_f64(a: float64x2_t) -> f64 {
+     vminvq_f64_(a)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminp))]
+ pub unsafe fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     vpminq_s8_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminp))]
+ pub unsafe fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     vpminq_s16_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(sminp))]
+ pub unsafe fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     vpminq_s32_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminp))]
+ pub unsafe fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     vpminq_u8_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminp))]
+ pub unsafe fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     vpminq_u16_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(uminp))]
+ pub unsafe fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     vpminq_u32_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fminp))]
+ pub unsafe fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     vpminq_f32_(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fminp))]
+ pub unsafe fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
+     vpminq_f64_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxp))]
+ pub unsafe fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     vpmaxq_s8_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxp))]
+ pub unsafe fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     vpmaxq_s16_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(smaxp))]
+ pub unsafe fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     vpmaxq_s32_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxp))]
+ pub unsafe fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     vpmaxq_u8_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxp))]
+ pub unsafe fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     vpmaxq_u16_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(umaxp))]
+ pub unsafe fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     vpmaxq_u32_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmaxp))]
+ pub unsafe fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     vpmaxq_f32_(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fmaxp))]
+ pub unsafe fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
+     vpmaxq_f64_(a, b)
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_s8(low: int8x8_t, high: int8x8_t) -> int8x16_t {
+     simd_shuffle16(
+         low,
+         high,
+         [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+     )
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_s16(low: int16x4_t, high: int16x4_t) -> int16x8_t {
+     simd_shuffle8(low, high, [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_s32(low: int32x2_t, high: int32x2_t) -> int32x4_t {
+     simd_shuffle4(low, high, [0, 1, 2, 3])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_s64(low: int64x1_t, high: int64x1_t) -> int64x2_t {
+     simd_shuffle2(low, high, [0, 1])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_u8(low: uint8x8_t, high: uint8x8_t) -> uint8x16_t {
+     simd_shuffle16(
+         low,
+         high,
+         [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+     )
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_u16(low: uint16x4_t, high: uint16x4_t) -> uint16x8_t {
+     simd_shuffle8(low, high, [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_u32(low: uint32x2_t, high: uint32x2_t) -> uint32x4_t {
+     simd_shuffle4(low, high, [0, 1, 2, 3])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_u64(low: uint64x1_t, high: uint64x1_t) -> uint64x2_t {
+     simd_shuffle2(low, high, [0, 1])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_p64(low: poly64x1_t, high: poly64x1_t) -> poly64x2_t {
+     simd_shuffle2(low, high, [0, 1])
+ }
+ 
+ /* FIXME: 16-bit float
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_f16 ( low: float16x4_t,  high: float16x4_t) -> float16x8_t {
+     simd_shuffle8(low, high, [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ */
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_f32(low: float32x2_t, high: float32x2_t) -> float32x4_t {
+     simd_shuffle4(low, high, [0, 1, 2, 3])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_p8(low: poly8x8_t, high: poly8x8_t) -> poly8x16_t {
+     simd_shuffle16(
+         low,
+         high,
+         [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+     )
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_p16(low: poly16x4_t, high: poly16x4_t) -> poly16x8_t {
+     simd_shuffle8(low, high, [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ 
+ /// Vector combine
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(mov))]
+ pub unsafe fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t {
+     simd_shuffle2(low, high, [0, 1])
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     vqtbl1_s8(vcombine_s8(a, zeroed()), transmute(b))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     vqtbl1_u8(vcombine_u8(a, zeroed()), b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
+     vqtbl1_p8(vcombine_p8(a, zeroed()), b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
+     vqtbl1_s8(vcombine_s8(a.0, a.1), transmute(b))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
+     vqtbl1_u8(vcombine_u8(a.0, a.1), b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
+     vqtbl1_p8(vcombine_p8(a.0, a.1), b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
+     vqtbl2_s8(
+         int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, zeroed())),
+         transmute(b),
+     )
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
+     vqtbl2_u8(
+         uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, zeroed())),
+         b,
+     )
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
+     vqtbl2_p8(
+         poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, zeroed())),
+         b,
+     )
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
+     vqtbl2_s8(
+         int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, a.3)),
+         transmute(b),
+     )
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
+     vqtbl2_u8(
+         uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)),
+         b,
+     )
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
+     vqtbl2_p8(
+         poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)),
+         b,
+     )
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
+     use crate::core_arch::simd::i8x8;
+     let r = vqtbx1_s8(a, vcombine_s8(b, zeroed()), transmute(c));
+     let m: int8x8_t = simd_lt(c, transmute(i8x8::splat(8)));
+     simd_select(m, r, a)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
+     use crate::core_arch::simd::u8x8;
+     let r = vqtbx1_u8(a, vcombine_u8(b, zeroed()), c);
+     let m: int8x8_t = simd_lt(c, transmute(u8x8::splat(8)));
+     simd_select(m, r, a)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
+     use crate::core_arch::simd::u8x8;
+     let r = vqtbx1_p8(a, vcombine_p8(b, zeroed()), c);
+     let m: int8x8_t = simd_lt(c, transmute(u8x8::splat(8)));
+     simd_select(m, r, a)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
+     vqtbx1_s8(a, vcombine_s8(b.0, b.1), transmute(c))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
+     vqtbx1_u8(a, vcombine_u8(b.0, b.1), c)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
+     vqtbx1_p8(a, vcombine_p8(b.0, b.1), c)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
+     use crate::core_arch::simd::i8x8;
+     let r = vqtbx2_s8(
+         a,
+         int8x16x2_t(vcombine_s8(b.0, b.1), vcombine_s8(b.2, zeroed())),
+         transmute(c),
+     );
+     let m: int8x8_t = simd_lt(c, transmute(i8x8::splat(24)));
+     simd_select(m, r, a)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
+     use crate::core_arch::simd::u8x8;
+     let r = vqtbx2_u8(
+         a,
+         uint8x16x2_t(vcombine_u8(b.0, b.1), vcombine_u8(b.2, zeroed())),
+         c,
+     );
+     let m: int8x8_t = simd_lt(c, transmute(u8x8::splat(24)));
+     simd_select(m, r, a)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
+     use crate::core_arch::simd::u8x8;
+     let r = vqtbx2_p8(
+         a,
+         poly8x16x2_t(vcombine_p8(b.0, b.1), vcombine_p8(b.2, zeroed())),
+         c,
+     );
+     let m: int8x8_t = simd_lt(c, transmute(u8x8::splat(24)));
+     simd_select(m, r, a)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
+     vqtbx2_s8(
+         a,
+         int8x16x2_t(vcombine_s8(b.0, b.1), vcombine_s8(b.2, b.3)),
+         transmute(c),
+     )
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
+     vqtbx2_u8(
+         a,
+         uint8x16x2_t(vcombine_u8(b.0, b.1), vcombine_u8(b.2, b.3)),
+         c,
+     )
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
+     vqtbx2_p8(
+         a,
+         poly8x16x2_t(vcombine_p8(b.0, b.1), vcombine_p8(b.2, b.3)),
+         c,
+     )
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl1_s8(t: int8x16_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbl1(t, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl1q_s8(t: int8x16_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbl1q(t, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl1_u8(t: uint8x16_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbl1(transmute(t), transmute(idx)))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl1q_u8(t: uint8x16_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbl1q(transmute(t), transmute(idx)))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl1_p8(t: poly8x16_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbl1(transmute(t), transmute(idx)))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl1q_p8(t: poly8x16_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbl1q(transmute(t), transmute(idx)))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx1_s8(a: int8x8_t, t: int8x16_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbx1(a, t, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx1q_s8(a: int8x16_t, t: int8x16_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbx1q(a, t, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx1_u8(a: uint8x8_t, t: uint8x16_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbx1(transmute(a), transmute(t), transmute(idx)))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx1q_u8(a: uint8x16_t, t: uint8x16_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbx1q(transmute(a), transmute(t), transmute(idx)))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx1_p8(a: poly8x8_t, t: poly8x16_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbx1(transmute(a), transmute(t), transmute(idx)))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx1q_p8(a: poly8x16_t, t: poly8x16_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbx1q(transmute(a), transmute(t), transmute(idx)))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl2_s8(t: int8x16x2_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbl2(t.0, t.1, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl2q_s8(t: int8x16x2_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbl2q(t.0, t.1, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl2_u8(t: uint8x16x2_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbl2(transmute(t.0), transmute(t.1), transmute(idx)))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl2q_u8(t: uint8x16x2_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbl2q(transmute(t.0), transmute(t.1), transmute(idx)))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl2_p8(t: poly8x16x2_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbl2(transmute(t.0), transmute(t.1), transmute(idx)))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl2q_p8(t: poly8x16x2_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbl2q(transmute(t.0), transmute(t.1), transmute(idx)))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx2_s8(a: int8x8_t, t: int8x16x2_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbx2(a, t.0, t.1, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx2q_s8(a: int8x16_t, t: int8x16x2_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbx2q(a, t.0, t.1, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx2_u8(a: uint8x8_t, t: uint8x16x2_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbx2(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx2q_u8(a: uint8x16_t, t: uint8x16x2_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbx2q(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx2_p8(a: poly8x8_t, t: poly8x16x2_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbx2(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx2q_p8(a: poly8x16_t, t: poly8x16x2_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbx2q(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(idx),
+     ))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl3_s8(t: int8x16x3_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbl3(t.0, t.1, t.2, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl3q_s8(t: int8x16x3_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbl3q(t.0, t.1, t.2, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl3_u8(t: uint8x16x3_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbl3(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl3q_u8(t: uint8x16x3_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbl3q(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl3_p8(t: poly8x16x3_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbl3(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl3q_p8(t: poly8x16x3_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbl3q(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx3_s8(a: int8x8_t, t: int8x16x3_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbx3(a, t.0, t.1, t.2, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx3q_s8(a: int8x16_t, t: int8x16x3_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbx3q(a, t.0, t.1, t.2, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx3_u8(a: uint8x8_t, t: uint8x16x3_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbx3(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx3q_u8(a: uint8x16_t, t: uint8x16x3_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbx3q(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx3_p8(a: poly8x8_t, t: poly8x16x3_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbx3(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx3q_p8(a: poly8x16_t, t: poly8x16x3_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbx3q(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(idx),
+     ))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl4_s8(t: int8x16x4_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbl4(t.0, t.1, t.2, t.3, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl4q_s8(t: int8x16x4_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbl4q(t.0, t.1, t.2, t.3, idx)
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl4_u8(t: uint8x16x4_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbl4(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl4q_u8(t: uint8x16x4_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbl4q(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl4_p8(t: poly8x16x4_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbl4(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbl))]
+ pub unsafe fn vqtbl4q_p8(t: poly8x16x4_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbl4q(
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx4_s8(a: int8x8_t, t: int8x16x4_t, idx: uint8x8_t) -> int8x8_t {
+     vqtbx4(a, t.0, t.1, t.2, t.3, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx4q_s8(a: int8x16_t, t: int8x16x4_t, idx: uint8x16_t) -> int8x16_t {
+     vqtbx4q(a, t.0, t.1, t.2, t.3, idx)
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx4_u8(a: uint8x8_t, t: uint8x16x4_t, idx: uint8x8_t) -> uint8x8_t {
+     transmute(vqtbx4(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx4q_u8(a: uint8x16_t, t: uint8x16x4_t, idx: uint8x16_t) -> uint8x16_t {
+     transmute(vqtbx4q(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx4_p8(a: poly8x8_t, t: poly8x16x4_t, idx: uint8x8_t) -> poly8x8_t {
+     transmute(vqtbx4(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(tbx))]
+ pub unsafe fn vqtbx4q_p8(a: poly8x16_t, t: poly8x16x4_t, idx: uint8x16_t) -> poly8x16_t {
+     transmute(vqtbx4q(
+         transmute(a),
+         transmute(t.0),
+         transmute(t.1),
+         transmute(t.2),
+         transmute(t.3),
+         transmute(idx),
+     ))
+ }
+ 
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(ldr))]
+ pub unsafe fn vld1q_f32(addr: *const f32) -> float32x4_t {
+     use crate::core_arch::simd::f32x4;
+     transmute(f32x4::new(
+         *addr,
+         *addr.offset(1),
+         *addr.offset(2),
+         *addr.offset(3),
+     ))
+ }
+ 
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(ldr))]
+ pub unsafe fn vld1q_s32(addr: *const i32) -> int32x4_t {
+     use crate::core_arch::simd::i32x4;
+     transmute(i32x4::new(
+         *addr,
+         *addr.offset(1),
+         *addr.offset(2),
+         *addr.offset(3),
+     ))
+ }
+ 
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(ldr))]
+ pub unsafe fn vld1q_u32(addr: *const u32) -> uint32x4_t {
+     use crate::core_arch::simd::u32x4;
+     transmute(u32x4::new(
+         *addr,
+         *addr.offset(1),
+         *addr.offset(2),
+         *addr.offset(3),
+     ))
+ }
+ 
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcvtzs))]
+ pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
+     vcvtq_s32_f32_(a)
+ }
+ 
+ /// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr(fcvtzu))]
+ pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
+     vcvtq_u32_f32_(a)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::aarch64::test_support::*;
+     use crate::core_arch::arm::test_support::*;
+     use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*};
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcvtq_s32_f32() {
+         let f = f32x4::new(-1., 2., 3., 4.);
+         let e = i32x4::new(-1, 2, 3, 4);
+         let r: i32x4 = transmute(vcvtq_s32_f32(transmute(f)));
+         assert_eq!(r, e);
+ 
+         let f = f32x4::new(10e37, 2., 3., 4.);
+         let e = i32x4::new(0x7fffffff, 2, 3, 4);
+         let r: i32x4 = transmute(vcvtq_s32_f32(transmute(f)));
+         assert_eq!(r, e);
+ 
+         let f = f32x4::new(-10e37, 2., 3., 4.);
+         let e = i32x4::new(-0x80000000, 2, 3, 4);
+         let r: i32x4 = transmute(vcvtq_s32_f32(transmute(f)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcvtq_u32_f32() {
+         let f = f32x4::new(1., 2., 3., 4.);
+         let e = u32x4::new(1, 2, 3, 4);
+         let r: u32x4 = transmute(vcvtq_u32_f32(transmute(f)));
+         assert_eq!(r, e);
+ 
+         let f = f32x4::new(-1., 2., 3., 4.);
+         let e = u32x4::new(0, 2, 3, 4);
+         let r: u32x4 = transmute(vcvtq_u32_f32(transmute(f)));
+         assert_eq!(r, e);
+ 
+         let f = f32x4::new(10e37, 2., 3., 4.);
+         let e = u32x4::new(0xffffffff, 2, 3, 4);
+         let r: u32x4 = transmute(vcvtq_u32_f32(transmute(f)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_f32() {
+         let e = f32x4::new(1., 2., 3., 4.);
+         let f = [0., 1., 2., 3., 4.];
+         // do a load that has 4 byte alignment to make sure we're not
+         // over aligning it
+         let r: f32x4 = transmute(vld1q_f32(f[1..].as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_s32() {
+         let e = i32x4::new(1, 2, 3, 4);
+         let f = [0, 1, 2, 3, 4];
+         // do a load that has 4 byte alignment to make sure we're not
+         // over aligning it
+         let r: i32x4 = transmute(vld1q_s32(f[1..].as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_u32() {
+         let e = u32x4::new(1, 2, 3, 4);
+         let f = [0, 1, 2, 3, 4];
+         // do a load that has 4 byte alignment to make sure we're not
+         // over aligning it
+         let r: u32x4 = transmute(vld1q_u32(f[1..].as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddq_s16() {
+         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = i16x8::new(0, -1, -2, -3, -4, -5, -6, -7);
+         let r: i16x8 = transmute(vpaddq_s16(transmute(a), transmute(b)));
+         let e = i16x8::new(3, 7, 11, 15, -1, -5, -9, -13);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddq_s32() {
+         let a = i32x4::new(1, 2, 3, 4);
+         let b = i32x4::new(0, -1, -2, -3);
+         let r: i32x4 = transmute(vpaddq_s32(transmute(a), transmute(b)));
+         let e = i32x4::new(3, 7, -1, -5);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddq_s8() {
+         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = i8x16::new(
+             0, -1, -2, -3, -4, -5, -6, -7, -8, -8, -10, -11, -12, -13, -14, -15,
+         );
+         let r: i8x16 = transmute(vpaddq_s8(transmute(a), transmute(b)));
+         let e = i8x16::new(
+             3, 7, 11, 15, 19, 23, 27, 31, -1, -5, -9, -13, -16, -21, -25, -29,
+         );
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddq_u16() {
+         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = u16x8::new(17, 18, 19, 20, 20, 21, 22, 23);
+         let r: u16x8 = transmute(vpaddq_u16(transmute(a), transmute(b)));
+         let e = u16x8::new(1, 5, 9, 13, 35, 39, 41, 45);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddq_u32() {
+         let a = u32x4::new(0, 1, 2, 3);
+         let b = u32x4::new(17, 18, 19, 20);
+         let r: u32x4 = transmute(vpaddq_u32(transmute(a), transmute(b)));
+         let e = u32x4::new(1, 5, 35, 39);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddq_u8() {
+         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = i8x16::new(
+             17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 26, 27, 29, 29, 30, 31,
+         );
+         let r = i8x16(1, 5, 9, 13, 17, 21, 25, 29, 35, 39, 41, 45, 49, 53, 58, 61);
+         let e: i8x16 = transmute(vpaddq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddd_s64() {
+         let a = i64x2::new(2, -3);
+         let r: i64 = transmute(vpaddd_s64(transmute(a)));
+         let e = -1_i64;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpaddd_u64() {
+         let a = i64x2::new(2, 3);
+         let r: u64 = transmute(vpaddd_u64(transmute(a)));
+         let e = 5_u64;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmull_p64() {
+         // FIXME: I've a hard time writing a test for this as the documentation
+         // from arm is a bit thin as to waht exactly it does
+         let a: i64 = 8;
+         let b: i64 = 7;
+         let e: i128 = 56;
+         let r: i128 = transmute(vmull_p64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         /*
+         let a: i64 = 5;
+         let b: i64 = 5;
+         let e: i128 = 25;
+         let r: i128 = transmute(vmull_p64(a, b));
+ 
+         assert_eq!(r, e);
+         let a: i64 = 6;
+         let b: i64 = 6;
+         let e: i128 = 36;
+         let r: i128 = transmute(vmull_p64(a, b));
+         assert_eq!(r, e);
+ 
+         let a: i64 = 7;
+         let b: i64 = 6;
+         let e: i128 = 42;
+         let r: i128 = transmute(vmull_p64(a, b));
+         assert_eq!(r, e);
+         */
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_f64() {
+         let a = 1.;
+         let b = 8.;
+         let e = 9.;
+         let r: f64 = transmute(vadd_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_f64() {
+         let a = f64x2::new(1., 2.);
+         let b = f64x2::new(8., 7.);
+         let e = f64x2::new(9., 9.);
+         let r: f64x2 = transmute(vaddq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_s64() {
+         let a = 1_i64;
+         let b = 8_i64;
+         let e = 9_i64;
+         let r: i64 = transmute(vadd_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_u64() {
+         let a = 1_u64;
+         let b = 8_u64;
+         let e = 9_u64;
+         let r: u64 = transmute(vadd_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddd_s64() {
+         let a = 1_i64;
+         let b = 8_i64;
+         let e = 9_i64;
+         let r: i64 = transmute(vaddd_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddd_u64() {
+         let a = 1_u64;
+         let b = 8_u64;
+         let e = 9_u64;
+         let r: u64 = transmute(vaddd_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_s8() {
+         let r = vmaxv_s8(transmute(i8x8::new(1, 2, 3, 4, -8, 6, 7, 5)));
+         assert_eq!(r, 7_i8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_s8() {
+         #[rustfmt::skip]
+         let r = vmaxvq_s8(transmute(i8x16::new(
+             1, 2, 3, 4,
+             -16, 6, 7, 5,
+             8, 1, 1, 1,
+             1, 1, 1, 1,
+         )));
+         assert_eq!(r, 8_i8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_s16() {
+         let r = vmaxv_s16(transmute(i16x4::new(1, 2, -4, 3)));
+         assert_eq!(r, 3_i16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_s16() {
+         let r = vmaxvq_s16(transmute(i16x8::new(1, 2, 7, 4, -16, 6, 7, 5)));
+         assert_eq!(r, 7_i16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_s32() {
+         let r = vmaxv_s32(transmute(i32x2::new(1, -4)));
+         assert_eq!(r, 1_i32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_s32() {
+         let r = vmaxvq_s32(transmute(i32x4::new(1, 2, -32, 4)));
+         assert_eq!(r, 4_i32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_u8() {
+         let r = vmaxv_u8(transmute(u8x8::new(1, 2, 3, 4, 8, 6, 7, 5)));
+         assert_eq!(r, 8_u8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_u8() {
+         #[rustfmt::skip]
+         let r = vmaxvq_u8(transmute(u8x16::new(
+             1, 2, 3, 4,
+             16, 6, 7, 5,
+             8, 1, 1, 1,
+             1, 1, 1, 1,
+         )));
+         assert_eq!(r, 16_u8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_u16() {
+         let r = vmaxv_u16(transmute(u16x4::new(1, 2, 4, 3)));
+         assert_eq!(r, 4_u16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_u16() {
+         let r = vmaxvq_u16(transmute(u16x8::new(1, 2, 7, 4, 16, 6, 7, 5)));
+         assert_eq!(r, 16_u16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_u32() {
+         let r = vmaxv_u32(transmute(u32x2::new(1, 4)));
+         assert_eq!(r, 4_u32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_u32() {
+         let r = vmaxvq_u32(transmute(u32x4::new(1, 2, 32, 4)));
+         assert_eq!(r, 32_u32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxv_f32() {
+         let r = vmaxv_f32(transmute(f32x2::new(1., 4.)));
+         assert_eq!(r, 4_f32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_f32() {
+         let r = vmaxvq_f32(transmute(f32x4::new(1., 2., 32., 4.)));
+         assert_eq!(r, 32_f32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxvq_f64() {
+         let r = vmaxvq_f64(transmute(f64x2::new(1., 4.)));
+         assert_eq!(r, 4_f64);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_s8() {
+         let r = vminv_s8(transmute(i8x8::new(1, 2, 3, 4, -8, 6, 7, 5)));
+         assert_eq!(r, -8_i8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_s8() {
+         #[rustfmt::skip]
+         let r = vminvq_s8(transmute(i8x16::new(
+             1, 2, 3, 4,
+             -16, 6, 7, 5,
+             8, 1, 1, 1,
+             1, 1, 1, 1,
+         )));
+         assert_eq!(r, -16_i8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_s16() {
+         let r = vminv_s16(transmute(i16x4::new(1, 2, -4, 3)));
+         assert_eq!(r, -4_i16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_s16() {
+         let r = vminvq_s16(transmute(i16x8::new(1, 2, 7, 4, -16, 6, 7, 5)));
+         assert_eq!(r, -16_i16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_s32() {
+         let r = vminv_s32(transmute(i32x2::new(1, -4)));
+         assert_eq!(r, -4_i32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_s32() {
+         let r = vminvq_s32(transmute(i32x4::new(1, 2, -32, 4)));
+         assert_eq!(r, -32_i32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_u8() {
+         let r = vminv_u8(transmute(u8x8::new(1, 2, 3, 4, 8, 6, 7, 5)));
+         assert_eq!(r, 1_u8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_u8() {
+         #[rustfmt::skip]
+         let r = vminvq_u8(transmute(u8x16::new(
+             1, 2, 3, 4,
+             16, 6, 7, 5,
+             8, 1, 1, 1,
+             1, 1, 1, 1,
+         )));
+         assert_eq!(r, 1_u8);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_u16() {
+         let r = vminv_u16(transmute(u16x4::new(1, 2, 4, 3)));
+         assert_eq!(r, 1_u16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_u16() {
+         let r = vminvq_u16(transmute(u16x8::new(1, 2, 7, 4, 16, 6, 7, 5)));
+         assert_eq!(r, 1_u16);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_u32() {
+         let r = vminv_u32(transmute(u32x2::new(1, 4)));
+         assert_eq!(r, 1_u32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_u32() {
+         let r = vminvq_u32(transmute(u32x4::new(1, 2, 32, 4)));
+         assert_eq!(r, 1_u32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminv_f32() {
+         let r = vminv_f32(transmute(f32x2::new(1., 4.)));
+         assert_eq!(r, 1_f32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_f32() {
+         let r = vminvq_f32(transmute(f32x4::new(1., 2., 32., 4.)));
+         assert_eq!(r, 1_f32);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminvq_f64() {
+         let r = vminvq_f64(transmute(f64x2::new(1., 4.)));
+         assert_eq!(r, 1_f64);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpminq_s8() {
+         #[cfg_attr(rustfmt, skip)]
+         let a = i8x16::new(1, -2, 3, -4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+         #[cfg_attr(rustfmt, skip)]
+         let b = i8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9);
+         #[cfg_attr(rustfmt, skip)]
+         let e = i8x16::new(-2, -4, 5, 7, 1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6);
+         let r: i8x16 = transmute(vpminq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpminq_s16() {
+         let a = i16x8::new(1, -2, 3, 4, 5, 6, 7, 8);
+         let b = i16x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = i16x8::new(-2, 3, 5, 7, 0, 2, 4, 6);
+         let r: i16x8 = transmute(vpminq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpminq_s32() {
+         let a = i32x4::new(1, -2, 3, 4);
+         let b = i32x4::new(0, 3, 2, 5);
+         let e = i32x4::new(-2, 3, 0, 2);
+         let r: i32x4 = transmute(vpminq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpminq_u8() {
+         #[cfg_attr(rustfmt, skip)]
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+         #[cfg_attr(rustfmt, skip)]
+         let b = u8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9);
+         #[cfg_attr(rustfmt, skip)]
+         let e = u8x16::new(1, 3, 5, 7, 1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6);
+         let r: u8x16 = transmute(vpminq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpminq_u16() {
+         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = u16x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = u16x8::new(1, 3, 5, 7, 0, 2, 4, 6);
+         let r: u16x8 = transmute(vpminq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpminq_u32() {
+         let a = u32x4::new(1, 2, 3, 4);
+         let b = u32x4::new(0, 3, 2, 5);
+         let e = u32x4::new(1, 3, 0, 2);
+         let r: u32x4 = transmute(vpminq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_f32() {
+         let a = f32x4::new(1., -2., 3., 4.);
+         let b = f32x4::new(0., 3., 2., 5.);
+         let e = f32x4::new(-2., 3., 0., 2.);
+         let r: f32x4 = transmute(vpminq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_f64() {
+         let a = f64x2::new(1., -2.);
+         let b = f64x2::new(0., 3.);
+         let e = f64x2::new(-2., 0.);
+         let r: f64x2 = transmute(vpminq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmaxq_s8() {
+         #[cfg_attr(rustfmt, skip)]
+         let a = i8x16::new(1, -2, 3, -4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+         #[cfg_attr(rustfmt, skip)]
+         let b = i8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9);
+         #[cfg_attr(rustfmt, skip)]
+         let e = i8x16::new(1, 3, 6, 8, 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9);
+         let r: i8x16 = transmute(vpmaxq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmaxq_s16() {
+         let a = i16x8::new(1, -2, 3, 4, 5, 6, 7, 8);
+         let b = i16x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = i16x8::new(1, 4, 6, 8, 3, 5, 7, 9);
+         let r: i16x8 = transmute(vpmaxq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmaxq_s32() {
+         let a = i32x4::new(1, -2, 3, 4);
+         let b = i32x4::new(0, 3, 2, 5);
+         let e = i32x4::new(1, 4, 3, 5);
+         let r: i32x4 = transmute(vpmaxq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmaxq_u8() {
+         #[cfg_attr(rustfmt, skip)]
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+         #[cfg_attr(rustfmt, skip)]
+         let b = u8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9);
+         #[cfg_attr(rustfmt, skip)]
+         let e = u8x16::new(2, 4, 6, 8, 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9);
+         let r: u8x16 = transmute(vpmaxq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmaxq_u16() {
+         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = u16x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = u16x8::new(2, 4, 6, 8, 3, 5, 7, 9);
+         let r: u16x8 = transmute(vpmaxq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmaxq_u32() {
+         let a = u32x4::new(1, 2, 3, 4);
+         let b = u32x4::new(0, 3, 2, 5);
+         let e = u32x4::new(2, 4, 3, 5);
+         let r: u32x4 = transmute(vpmaxq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_f32() {
+         let a = f32x4::new(1., -2., 3., 4.);
+         let b = f32x4::new(0., 3., 2., 5.);
+         let e = f32x4::new(1., 4., 3., 5.);
+         let r: f32x4 = transmute(vpmaxq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_f64() {
+         let a = f64x2::new(1., -2.);
+         let b = f64x2::new(0., 3.);
+         let e = f64x2::new(1., 3.);
+         let r: f64x2 = transmute(vpmaxq_f64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     macro_rules! test_vcombine {
+         ($test_id:ident => $fn_id:ident ([$($a:expr),*], [$($b:expr),*])) => {
+             #[allow(unused_assignments)]
+             #[simd_test(enable = "neon")]
+             unsafe fn $test_id() {
+                 let a = [$($a),*];
+                 let b = [$($b),*];
+                 let e = [$($a),* $(, $b)*];
+                 let c = $fn_id(transmute(a), transmute(b));
+                 let mut d = e;
+                 d = transmute(c);
+                 assert_eq!(d, e);
+             }
+         }
+     }
+ 
+     test_vcombine!(test_vcombine_s8 => vcombine_s8([3_i8, -4, 5, -6, 7, 8, 9, 10], [13_i8, -14, 15, -16, 17, 18, 19, 110]));
+     test_vcombine!(test_vcombine_u8 => vcombine_u8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110]));
+     test_vcombine!(test_vcombine_p8 => vcombine_p8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110]));
+ 
+     test_vcombine!(test_vcombine_s16 => vcombine_s16([3_i16, -4, 5, -6], [13_i16, -14, 15, -16]));
+     test_vcombine!(test_vcombine_u16 => vcombine_u16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
+     test_vcombine!(test_vcombine_p16 => vcombine_p16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
+     // FIXME: 16-bit floats
+     // test_vcombine!(test_vcombine_f16 => vcombine_f16([3_f16, 4., 5., 6.],
+     // [13_f16, 14., 15., 16.]));
+ 
+     test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14]));
+     test_vcombine!(test_vcombine_u32 => vcombine_u32([3_u32, 4], [13_u32, 14]));
+     // note: poly32x4 does not exist, and neither does vcombine_p32
+     test_vcombine!(test_vcombine_f32 => vcombine_f32([3_f32, -4.], [13_f32, -14.]));
+ 
+     test_vcombine!(test_vcombine_s64 => vcombine_s64([-3_i64], [13_i64]));
+     test_vcombine!(test_vcombine_u64 => vcombine_u64([3_u64], [13_u64]));
+     test_vcombine!(test_vcombine_p64 => vcombine_p64([3_u64], [13_u64]));
+     test_vcombine!(test_vcombine_f64 => vcombine_f64([-3_f64], [13_f64]));
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u64() {
+         test_cmp_u64(
+             |i, j| vceq_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u64() {
+         testq_cmp_u64(
+             |i, j| vceqq_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s64() {
+         test_cmp_s64(
+             |i, j| vceq_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s64() {
+         testq_cmp_s64(
+             |i, j| vceqq_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_p64() {
+         test_cmp_p64(
+             |i, j| vceq_p64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_p64() {
+         testq_cmp_p64(
+             |i, j| vceqq_p64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_f64() {
+         test_cmp_f64(
+             |i, j| vceq_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_f64() {
+         testq_cmp_f64(
+             |i, j| vceqq_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a == b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s64() {
+         test_cmp_s64(
+             |i, j| vcgt_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a > b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s64() {
+         testq_cmp_s64(
+             |i, j| vcgtq_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a > b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u64() {
+         test_cmp_u64(
+             |i, j| vcgt_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a > b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u64() {
+         testq_cmp_u64(
+             |i, j| vcgtq_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a > b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_f64() {
+         test_cmp_f64(
+             |i, j| vcgt_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a > b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_f64() {
+         testq_cmp_f64(
+             |i, j| vcgtq_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a > b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s64() {
+         test_cmp_s64(
+             |i, j| vclt_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a < b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s64() {
+         testq_cmp_s64(
+             |i, j| vcltq_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a < b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u64() {
+         test_cmp_u64(
+             |i, j| vclt_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a < b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u64() {
+         testq_cmp_u64(
+             |i, j| vcltq_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a < b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vltq_f64() {
+         test_cmp_f64(
+             |i, j| vclt_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a < b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_f64() {
+         testq_cmp_f64(
+             |i, j| vcltq_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a < b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s64() {
+         test_cmp_s64(
+             |i, j| vcle_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a <= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s64() {
+         testq_cmp_s64(
+             |i, j| vcleq_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a <= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u64() {
+         test_cmp_u64(
+             |i, j| vcle_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a <= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u64() {
+         testq_cmp_u64(
+             |i, j| vcleq_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a <= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vleq_f64() {
+         test_cmp_f64(
+             |i, j| vcle_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a <= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_f64() {
+         testq_cmp_f64(
+             |i, j| vcleq_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a <= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s64() {
+         test_cmp_s64(
+             |i, j| vcge_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a >= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s64() {
+         testq_cmp_s64(
+             |i, j| vcgeq_s64(i, j),
+             |a: i64, b: i64| -> u64 {
+                 if a >= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u64() {
+         test_cmp_u64(
+             |i, j| vcge_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a >= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u64() {
+         testq_cmp_u64(
+             |i, j| vcgeq_u64(i, j),
+             |a: u64, b: u64| -> u64 {
+                 if a >= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vgeq_f64() {
+         test_cmp_f64(
+             |i, j| vcge_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a >= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_f64() {
+         testq_cmp_f64(
+             |i, j| vcgeq_f64(i, j),
+             |a: f64, b: f64| -> u64 {
+                 if a >= b {
+                     0xFFFFFFFFFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_f64() {
+         test_ari_f64(|i, j| vmul_f64(i, j), |a: f64, b: f64| -> f64 { a * b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_f64() {
+         testq_ari_f64(|i, j| vmulq_f64(i, j), |a: f64, b: f64| -> f64 { a * b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_f64() {
+         test_ari_f64(|i, j| vsub_f64(i, j), |a: f64, b: f64| -> f64 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_f64() {
+         testq_ari_f64(|i, j| vsubq_f64(i, j), |a: f64, b: f64| -> f64 { a - b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabsd_s64() {
+         assert_eq!(vabsd_s64(-1), 1);
+         assert_eq!(vabsd_s64(0), 0);
+         assert_eq!(vabsd_s64(1), 1);
+         assert_eq!(vabsd_s64(i64::MIN), i64::MIN);
+         assert_eq!(vabsd_s64(i64::MIN + 1), i64::MAX);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabs_s64() {
+         let a = i64x1::new(i64::MIN);
+         let r: i64x1 = transmute(vabs_s64(transmute(a)));
+         let e = i64x1::new(i64::MIN);
+         assert_eq!(r, e);
+         let a = i64x1::new(i64::MIN + 1);
+         let r: i64x1 = transmute(vabs_s64(transmute(a)));
+         let e = i64x1::new(i64::MAX);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabsq_s64() {
+         let a = i64x2::new(i64::MIN, i64::MIN + 1);
+         let r: i64x2 = transmute(vabsq_s64(transmute(a)));
+         let e = i64x2::new(i64::MIN, i64::MAX);
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddv_s16() {
+         let a = i16x4::new(1, 2, 3, -4);
+         let r: i16 = transmute(vaddv_s16(transmute(a)));
+         let e = 2_i16;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddv_u16() {
+         let a = u16x4::new(1, 2, 3, 4);
+         let r: u16 = transmute(vaddv_u16(transmute(a)));
+         let e = 10_u16;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddv_s32() {
+         let a = i32x2::new(1, -2);
+         let r: i32 = transmute(vaddv_s32(transmute(a)));
+         let e = -1_i32;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddv_u32() {
+         let a = u32x2::new(1, 2);
+         let r: u32 = transmute(vaddv_u32(transmute(a)));
+         let e = 3_u32;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddv_s8() {
+         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, -8);
+         let r: i8 = transmute(vaddv_s8(transmute(a)));
+         let e = 20_i8;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddv_u8() {
+         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r: u8 = transmute(vaddv_u8(transmute(a)));
+         let e = 36_u8;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_s16() {
+         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, -8);
+         let r: i16 = transmute(vaddvq_s16(transmute(a)));
+         let e = 20_i16;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_u16() {
+         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r: u16 = transmute(vaddvq_u16(transmute(a)));
+         let e = 36_u16;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_s32() {
+         let a = i32x4::new(1, 2, 3, -4);
+         let r: i32 = transmute(vaddvq_s32(transmute(a)));
+         let e = 2_i32;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_u32() {
+         let a = u32x4::new(1, 2, 3, 4);
+         let r: u32 = transmute(vaddvq_u32(transmute(a)));
+         let e = 10_u32;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_s8() {
+         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -16);
+         let r: i8 = transmute(vaddvq_s8(transmute(a)));
+         let e = 104_i8;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_u8() {
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r: u8 = transmute(vaddvq_u8(transmute(a)));
+         let e = 136_u8;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_s64() {
+         let a = i64x2::new(1, -2);
+         let r: i64 = transmute(vaddvq_s64(transmute(a)));
+         let e = -1_i64;
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddvq_u64() {
+         let a = u64x2::new(1, 2);
+         let r: u64 = transmute(vaddvq_u64(transmute(a)));
+         let e = 3_u64;
+         assert_eq!(r, e);
+     }
+ }
+ 
+ #[cfg(test)]
+ #[cfg(target_endian = "little")]
+ #[path = "../../arm/neon/table_lookup_tests.rs"]
+ mod table_lookup_tests;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,89 ----
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ extern "C" {
+     #[link_name = "llvm.prefetch"]
+     fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32);
+ }
+ 
+ /// See [`prefetch`](fn._prefetch.html).
+ pub const _PREFETCH_READ: i32 = 0;
+ 
+ /// See [`prefetch`](fn._prefetch.html).
+ pub const _PREFETCH_WRITE: i32 = 1;
+ 
+ /// See [`prefetch`](fn._prefetch.html).
+ pub const _PREFETCH_LOCALITY0: i32 = 0;
+ 
+ /// See [`prefetch`](fn._prefetch.html).
+ pub const _PREFETCH_LOCALITY1: i32 = 1;
+ 
+ /// See [`prefetch`](fn._prefetch.html).
+ pub const _PREFETCH_LOCALITY2: i32 = 2;
+ 
+ /// See [`prefetch`](fn._prefetch.html).
+ pub const _PREFETCH_LOCALITY3: i32 = 3;
+ 
+ /// Fetch the cache line that contains address `p` using the given `rw` and `locality`.
+ ///
+ /// The `rw` must be one of:
+ ///
+ /// * [`_PREFETCH_READ`](constant._PREFETCH_READ.html): the prefetch is preparing
+ ///   for a read.
+ ///
+ /// * [`_PREFETCH_WRITE`](constant._PREFETCH_WRITE.html): the prefetch is preparing
+ ///   for a write.
+ ///
+ /// The `locality` must be one of:
+ ///
+ /// * [`_PREFETCH_LOCALITY0`](constant._PREFETCH_LOCALITY0.html): Streaming or
+ ///   non-temporal prefetch, for data that is used only once.
+ ///
+ /// * [`_PREFETCH_LOCALITY1`](constant._PREFETCH_LOCALITY1.html): Fetch into level 3 cache.
+ ///
+ /// * [`_PREFETCH_LOCALITY2`](constant._PREFETCH_LOCALITY2.html): Fetch into level 2 cache.
+ ///
+ /// * [`_PREFETCH_LOCALITY3`](constant._PREFETCH_LOCALITY3.html): Fetch into level 1 cache.
+ ///
+ /// The prefetch memory instructions signal to the memory system that memory accesses
+ /// from a specified address are likely to occur in the near future. The memory system
+ /// can respond by taking actions that are expected to speed up the memory access when
+ /// they do occur, such as preloading the specified address into one or more caches.
+ /// Because these signals are only hints, it is valid for a particular CPU to treat
+ /// any or all prefetch instructions as a NOP.
+ ///
+ ///
+ /// [Arm's documentation](https://developer.arm.com/documentation/den0024/a/the-a64-instruction-set/memory-access-instructions/prefetching-memory?lang=en)
+ #[inline(always)]
+ #[cfg_attr(test, assert_instr("prfm pldl1strm", rw = _PREFETCH_READ, locality = _PREFETCH_LOCALITY0))]
+ #[cfg_attr(test, assert_instr("prfm pldl3keep", rw = _PREFETCH_READ, locality = _PREFETCH_LOCALITY1))]
+ #[cfg_attr(test, assert_instr("prfm pldl2keep", rw = _PREFETCH_READ, locality = _PREFETCH_LOCALITY2))]
+ #[cfg_attr(test, assert_instr("prfm pldl1keep", rw = _PREFETCH_READ, locality = _PREFETCH_LOCALITY3))]
+ #[cfg_attr(test, assert_instr("prfm pstl1strm", rw = _PREFETCH_WRITE, locality = _PREFETCH_LOCALITY0))]
+ #[cfg_attr(test, assert_instr("prfm pstl3keep", rw = _PREFETCH_WRITE, locality = _PREFETCH_LOCALITY1))]
+ #[cfg_attr(test, assert_instr("prfm pstl2keep", rw = _PREFETCH_WRITE, locality = _PREFETCH_LOCALITY2))]
+ #[cfg_attr(test, assert_instr("prfm pstl1keep", rw = _PREFETCH_WRITE, locality = _PREFETCH_LOCALITY3))]
+ #[rustc_args_required_const(1, 2)]
+ pub unsafe fn _prefetch(p: *const i8, rw: i32, locality: i32) {
+     // We use the `llvm.prefetch` instrinsic with `cache type` = 1 (data cache).
+     // `rw` and `strategy` are based on the function parameters.
+     macro_rules! pref {
+         ($rdwr:expr, $local:expr) => {
+             match ($rdwr, $local) {
+                 (0, 0) => prefetch(p, 0, 0, 1),
+                 (0, 1) => prefetch(p, 0, 1, 1),
+                 (0, 2) => prefetch(p, 0, 2, 1),
+                 (0, 3) => prefetch(p, 0, 3, 1),
+                 (1, 0) => prefetch(p, 1, 0, 1),
+                 (1, 1) => prefetch(p, 1, 1, 1),
+                 (1, 2) => prefetch(p, 1, 2, 1),
+                 (1, 3) => prefetch(p, 1, 3, 1),
+                 (_, _) => panic!(
+                     "Illegal (rw, locality) pair in prefetch, value ({}, {}).",
+                     $rdwr, $local
+                 ),
+             }
+         };
+     }
+     pref!(rw, locality);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,184 ----
+ use crate::core_arch::{aarch64::neon::*, arm::*, simd::*};
+ use std::{i16, i32, i8, mem::transmute, u16, u32, u8, vec::Vec};
+ 
+ macro_rules! V_u64 {
+     () => {
+         vec![
+             0x0000000000000000u64,
+             0x0101010101010101u64,
+             0x0202020202020202u64,
+             0x0F0F0F0F0F0F0F0Fu64,
+             0x8080808080808080u64,
+             0xF0F0F0F0F0F0F0F0u64,
+             0xFFFFFFFFFFFFFFFFu64,
+         ]
+     };
+ }
+ 
+ macro_rules! V_f64 {
+     () => {
+         vec![
+             0.0f64,
+             1.0f64,
+             -1.0f64,
+             1.2f64,
+             2.4f64,
+             std::f64::MAX,
+             std::f64::MIN,
+             std::f64::INFINITY,
+             std::f64::NEG_INFINITY,
+             std::f64::NAN,
+         ]
+     };
+ }
+ 
+ macro_rules! to64 {
+     ($t : ident) => {
+         |v: $t| -> u64 { transmute(v) }
+     };
+ }
+ 
+ macro_rules! to128 {
+     ($t : ident) => {
+         |v: $t| -> u128 { transmute(v) }
+     };
+ }
+ 
+ pub(crate) fn test<T, U, V, W, X>(
+     vals: Vec<T>,
+     fill1: fn(T) -> V,
+     fill2: fn(U) -> W,
+     cast: fn(W) -> X,
+     test_fun: fn(V, V) -> W,
+     verify_fun: fn(T, T) -> U,
+ ) where
+     T: Copy + core::fmt::Debug,
+     U: Copy + core::fmt::Debug + std::cmp::PartialEq,
+     V: Copy + core::fmt::Debug,
+     W: Copy + core::fmt::Debug,
+     X: Copy + core::fmt::Debug + std::cmp::PartialEq,
+ {
+     let pairs = vals.iter().zip(vals.iter());
+ 
+     for (i, j) in pairs {
+         let a: V = fill1(*i);
+         let b: V = fill1(*j);
+ 
+         let actual_pre: W = test_fun(a, b);
+         let expected_pre: W = fill2(verify_fun(*i, *j));
+ 
+         let actual: X = cast(actual_pre);
+         let expected: X = cast(expected_pre);
+ 
+         assert_eq!(
+             actual, expected,
+             "[{:?}:{:?}] :\nf({:?}, {:?}) = {:?}\ng({:?}, {:?}) = {:?}\n",
+             *i, *j, &a, &b, actual_pre, &a, &b, expected_pre
+         );
+     }
+ }
+ 
+ macro_rules! gen_test_fn {
+     ($n: ident, $t: ident, $u: ident, $v: ident, $w: ident, $x: ident, $vals: expr, $fill1: expr, $fill2: expr, $cast: expr) => {
+         pub(crate) fn $n(test_fun: fn($v, $v) -> $w, verify_fun: fn($t, $t) -> $u) {
+             unsafe {
+                 test::<$t, $u, $v, $w, $x>($vals, $fill1, $fill2, $cast, test_fun, verify_fun)
+             };
+         }
+     };
+ }
+ 
+ macro_rules! gen_fill_fn {
+     ($id: ident, $el_width: expr, $num_els: expr, $in_t : ident, $out_t: ident, $cmp_t: ident) => {
+         pub(crate) fn $id(val: $in_t) -> $out_t {
+             let initial: [$in_t; $num_els] = [val; $num_els];
+             let result: $cmp_t = unsafe { transmute(initial) };
+             let result_out: $out_t = unsafe { transmute(result) };
+ 
+             // println!("FILL: {:016x} as {} x {}: {:016x}", val.reverse_bits(), $el_width, $num_els, (result as u64).reverse_bits());
+ 
+             result_out
+         }
+     };
+ }
+ 
+ gen_fill_fn!(fill_u64, 64, 1, u64, uint64x1_t, u64);
+ gen_fill_fn!(fillq_u64, 64, 2, u64, uint64x2_t, u128);
+ gen_fill_fn!(fill_f64, 64, 1, f64, float64x1_t, u64);
+ gen_fill_fn!(fillq_f64, 64, 2, f64, float64x2_t, u128);
+ gen_fill_fn!(fill_p64, 64, 1, u64, poly64x1_t, u64);
+ gen_fill_fn!(fillq_p64, 64, 2, u64, poly64x2_t, u128);
+ 
+ gen_test_fn!(
+     test_ari_f64,
+     f64,
+     f64,
+     float64x1_t,
+     float64x1_t,
+     u64,
+     V_f64!(),
+     fill_f64,
+     fill_f64,
+     to64!(float64x1_t)
+ );
+ gen_test_fn!(
+     test_cmp_f64,
+     f64,
+     u64,
+     float64x1_t,
+     uint64x1_t,
+     u64,
+     V_f64!(),
+     fill_f64,
+     fill_u64,
+     to64!(uint64x1_t)
+ );
+ gen_test_fn!(
+     testq_ari_f64,
+     f64,
+     f64,
+     float64x2_t,
+     float64x2_t,
+     u128,
+     V_f64!(),
+     fillq_f64,
+     fillq_f64,
+     to128!(float64x2_t)
+ );
+ gen_test_fn!(
+     testq_cmp_f64,
+     f64,
+     u64,
+     float64x2_t,
+     uint64x2_t,
+     u128,
+     V_f64!(),
+     fillq_f64,
+     fillq_u64,
+     to128!(uint64x2_t)
+ );
+ 
+ gen_test_fn!(
+     test_cmp_p64,
+     u64,
+     u64,
+     poly64x1_t,
+     uint64x1_t,
+     u64,
+     V_u64!(),
+     fill_p64,
+     fill_u64,
+     to64!(uint64x1_t)
+ );
+ gen_test_fn!(
+     testq_cmp_p64,
+     u64,
+     u64,
+     poly64x2_t,
+     uint64x2_t,
+     u128,
+     V_u64!(),
+     fillq_p64,
+     fillq_u64,
+     to128!(uint64x2_t)
+ );
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,183 ----
+ //! ARM's Transactional Memory Extensions (TME).
+ //!
+ //! This CPU feature is available on Aarch64 - A architecture profile.
+ //! This feature is in the non-neon feature set. TME specific vendor documentation can
+ //! be found [TME Intrinsics Introduction][tme_intrinsics_intro].
+ //!
+ //! The reference is [ACLE Q4 2019][acle_q4_2019_ref].
+ //!
+ //! ACLE has a section for TME extensions and state masks for aborts and failure codes.
+ //! [ARM A64 Architecture Register Datasheet][a_profile_future] also describes possible failure code scenarios.
+ //!
+ //! [acle_q4_2019_ref]: https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf
+ //! [tme_intrinsics_intro]: https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics
+ //! [llvm_aarch64_int]: https://github.com/llvm/llvm-project/commit/a36d31478c182903523e04eb271bbf102bfab2cc#diff-ff24e1c35f4d54f1110ce5d90c709319R626-R646
+ //! [a_profile_future]: https://static.docs.arm.com/ddi0601/a/SysReg_xml_futureA-2019-04.pdf?_ga=2.116560387.441514988.1590524918-1110153136.1588469296
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ extern "C" {
+     #[link_name = "llvm.aarch64.tstart"]
+     fn aarch64_tstart() -> u64;
+     #[link_name = "llvm.aarch64.tcommit"]
+     fn aarch64_tcommit() -> ();
+     #[link_name = "llvm.aarch64.tcancel"]
+     fn aarch64_tcancel(imm0: u64) -> ();
+     #[link_name = "llvm.aarch64.ttest"]
+     fn aarch64_ttest() -> u64;
+ }
+ 
+ /// Transaction successfully started.
+ pub const _TMSTART_SUCCESS: u64 = 0x00_u64;
+ 
+ /// Extraction mask for failure reason
+ pub const _TMFAILURE_REASON: u64 = 0x00007FFF_u64;
+ 
+ /// Transaction retry is possible.
+ pub const _TMFAILURE_RTRY: u64 = 1 << 15;
+ 
+ /// Transaction executed a TCANCEL instruction
+ pub const _TMFAILURE_CNCL: u64 = 1 << 16;
+ 
+ /// Transaction aborted because a conflict occurred
+ pub const _TMFAILURE_MEM: u64 = 1 << 17;
+ 
+ /// Fallback error type for any other reason
+ pub const _TMFAILURE_IMP: u64 = 1 << 18;
+ 
+ /// Transaction aborted because a non-permissible operation was attempted
+ pub const _TMFAILURE_ERR: u64 = 1 << 19;
+ 
+ /// Transaction aborted due to read or write set limit was exceeded
+ pub const _TMFAILURE_SIZE: u64 = 1 << 20;
+ 
+ /// Transaction aborted due to transactional nesting level was exceeded
+ pub const _TMFAILURE_NEST: u64 = 1 << 21;
+ 
+ /// Transaction aborted due to a debug trap.
+ pub const _TMFAILURE_DBG: u64 = 1 << 22;
+ 
+ /// Transaction failed from interrupt
+ pub const _TMFAILURE_INT: u64 = 1 << 23;
+ 
+ /// Indicates a TRIVIAL version of TM is available
+ pub const _TMFAILURE_TRIVIAL: u64 = 1 << 24;
+ 
+ /// Starts a new transaction. When the transaction starts successfully the return value is 0.
+ /// If the transaction fails, all state modifications are discarded and a cause of the failure
+ /// is encoded in the return value.
+ ///
+ /// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
+ #[inline]
+ #[target_feature(enable = "tme")]
+ #[cfg_attr(test, assert_instr(tstart))]
+ pub unsafe fn __tstart() -> u64 {
+     aarch64_tstart()
+ }
+ 
+ /// Commits the current transaction. For a nested transaction, the only effect is that the
+ /// transactional nesting depth is decreased. For an outer transaction, the state modifications
+ /// performed transactionally are committed to the architectural state.
+ ///
+ /// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
+ #[inline]
+ #[target_feature(enable = "tme")]
+ #[cfg_attr(test, assert_instr(tcommit))]
+ pub unsafe fn __tcommit() {
+     aarch64_tcommit()
+ }
+ 
+ /// Cancels the current transaction and discards all state modifications that were performed transactionally.
+ ///
+ /// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
+ #[inline]
+ #[target_feature(enable = "tme")]
+ #[cfg_attr(test, assert_instr(tcancel, imm0 = 0x0))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __tcancel(imm0: u64) {
+     macro_rules! call {
+         ($imm0:expr) => {
+             aarch64_tcancel($imm0)
+         };
+     }
+     constify_imm8!(imm0, call)
+ }
+ 
+ /// Tests if executing inside a transaction. If no transaction is currently executing,
+ /// the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
+ ///
+ /// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
+ #[inline]
+ #[target_feature(enable = "tme")]
+ #[cfg_attr(test, assert_instr(ttest))]
+ pub unsafe fn __ttest() -> u64 {
+     aarch64_ttest()
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::aarch64::*;
+ 
+     const CANCEL_CODE: u64 = (0 | (0x123 & _TMFAILURE_REASON) as u64) as u64;
+ 
+     #[simd_test(enable = "tme")]
+     unsafe fn test_tstart() {
+         let mut x = 0;
+         for i in 0..10 {
+             let code = tme::__tstart();
+             if code == _TMSTART_SUCCESS {
+                 x += 1;
+                 assert_eq!(x, i + 1);
+                 break;
+             }
+             assert_eq!(x, 0);
+         }
+     }
+ 
+     #[simd_test(enable = "tme")]
+     unsafe fn test_tcommit() {
+         let mut x = 0;
+         for i in 0..10 {
+             let code = tme::__tstart();
+             if code == _TMSTART_SUCCESS {
+                 x += 1;
+                 assert_eq!(x, i + 1);
+                 tme::__tcommit();
+             }
+             assert_eq!(x, i + 1);
+         }
+     }
+ 
+     #[simd_test(enable = "tme")]
+     unsafe fn test_tcancel() {
+         let mut x = 0;
+ 
+         for i in 0..10 {
+             let code = tme::__tstart();
+             if code == _TMSTART_SUCCESS {
+                 x += 1;
+                 assert_eq!(x, i + 1);
+                 tme::__tcancel(CANCEL_CODE);
+                 break;
+             }
+         }
+ 
+         assert_eq!(x, 0);
+     }
+ 
+     #[simd_test(enable = "tme")]
+     unsafe fn test_ttest() {
+         for _ in 0..10 {
+             let code = tme::__tstart();
+             if code == _TMSTART_SUCCESS {
+                 if tme::__ttest() == 2 {
+                     tme::__tcancel(CANCEL_CODE);
+                     break;
+                 }
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,104 ----
+ //! ARMv8 intrinsics.
+ //!
+ //! The reference is [ARMv8-A Reference Manual][armv8].
+ //!
+ //! [armv8]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.
+ //! ddi0487a.k_10775/index.html
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Reverse the order of the bytes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(rev))]
+ pub unsafe fn _rev_u64(x: u64) -> u64 {
+     x.swap_bytes() as u64
+ }
+ 
+ /// Count Leading Zeros.
+ #[inline]
+ #[cfg_attr(test, assert_instr(clz))]
+ pub unsafe fn _clz_u64(x: u64) -> u64 {
+     x.leading_zeros() as u64
+ }
+ 
+ /// Reverse the bit order.
+ #[inline]
+ #[cfg_attr(test, assert_instr(rbit))]
+ pub unsafe fn _rbit_u64(x: u64) -> u64 {
+     crate::intrinsics::bitreverse(x)
+ }
+ 
+ /// Counts the leading most significant bits set.
+ ///
+ /// When all bits of the operand are set it returns the size of the operand in
+ /// bits.
+ #[inline]
+ #[cfg_attr(test, assert_instr(cls))]
+ pub unsafe fn _cls_u32(x: u32) -> u32 {
+     u32::leading_zeros((((((x as i32) >> 31) as u32) ^ x) << 1) | 1) as u32
+ }
+ 
+ /// Counts the leading most significant bits set.
+ ///
+ /// When all bits of the operand are set it returns the size of the operand in
+ /// bits.
+ #[inline]
+ #[cfg_attr(test, assert_instr(cls))]
+ pub unsafe fn _cls_u64(x: u64) -> u64 {
+     u64::leading_zeros((((((x as i64) >> 63) as u64) ^ x) << 1) | 1) as u64
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::aarch64::v8;
+ 
+     #[test]
+     fn _rev_u64() {
+         unsafe {
+             assert_eq!(
+                 v8::_rev_u64(0b0000_0000_1111_1111_0000_0000_1111_1111_u64),
+                 0b1111_1111_0000_0000_1111_1111_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_u64
+             );
+         }
+     }
+ 
+     #[test]
+     fn _clz_u64() {
+         unsafe {
+             assert_eq!(v8::_clz_u64(0b0000_1010u64), 60u64);
+         }
+     }
+ 
+     #[test]
+     fn _rbit_u64() {
+         unsafe {
+             assert_eq!(
+                 v8::_rbit_u64(0b0000_0000_1111_1101_0000_0000_1111_1111_u64),
+                 0b1111_1111_0000_0000_1011_1111_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_u64
+             );
+         }
+     }
+ 
+     #[test]
+     fn _cls_u32() {
+         unsafe {
+             assert_eq!(
+                 v8::_cls_u32(0b1111_1111_1111_1111_0000_0000_1111_1111_u32),
+                 15_u32
+             );
+         }
+     }
+ 
+     #[test]
+     fn _cls_u64() {
+         unsafe {
+             assert_eq!(
+                 v8::_cls_u64(
+                     0b1111_1111_1111_1111_0000_0000_1111_1111_0000_0000_0000_0000_0000_0000_0000_0000_u64
+                 ),
+                 15_u64
+             );
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,14 ----
+ //! Access types available on all architectures
+ 
+ /// Full system is the required shareability domain, reads and writes are the
+ /// required access types
+ pub struct SY;
+ 
+ dmb_dsb!(SY);
+ 
+ impl super::super::sealed::Isb for SY {
+     #[inline(always)]
+     unsafe fn __isb(&self) {
+         super::isb(super::arg::SY)
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,27 ----
+ // Reference: ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360E) Section 3.5 "Summary
+ // of CP15 instructions"
+ 
+ /// Full system is the required shareability domain, reads and writes are the
+ /// required access types
+ pub struct SY;
+ 
+ impl super::super::sealed::Dmb for SY {
+     #[inline(always)]
+     unsafe fn __dmb(&self) {
+         llvm_asm!("mcr p15, 0, r0, c7, c10, 5" : : : "memory" : "volatile")
+     }
+ }
+ 
+ impl super::super::sealed::Dsb for SY {
+     #[inline(always)]
+     unsafe fn __dsb(&self) {
+         llvm_asm!("mcr p15, 0, r0, c7, c10, 4" : : : "memory" : "volatile")
+     }
+ }
+ 
+ impl super::super::sealed::Isb for SY {
+     #[inline(always)]
+     unsafe fn __isb(&self) {
+         llvm_asm!("mcr p15, 0, r0, c7, c5, 4" : : : "memory" : "volatile")
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,154 ----
+ // Reference: Section 7.4 "Hints" of ACLE
+ 
+ // CP15 instruction
+ #[cfg(not(any(
+     // v8
+     target_arch = "aarch64",
+     // v7
+     target_feature = "v7",
+     // v6-M
+     target_feature = "mclass"
+ )))]
+ mod cp15;
+ 
+ #[cfg(not(any(
+     target_arch = "aarch64",
+     target_feature = "v7",
+     target_feature = "mclass"
+ )))]
+ pub use self::cp15::*;
+ 
+ // Dedicated instructions
+ #[cfg(any(
+     target_arch = "aarch64",
+     target_feature = "v7",
+     target_feature = "mclass"
+ ))]
+ macro_rules! dmb_dsb {
+     ($A:ident) => {
+         impl super::super::sealed::Dmb for $A {
+             #[inline(always)]
+             unsafe fn __dmb(&self) {
+                 super::dmb(super::arg::$A)
+             }
+         }
+ 
+         impl super::super::sealed::Dsb for $A {
+             #[inline(always)]
+             unsafe fn __dsb(&self) {
+                 super::dsb(super::arg::$A)
+             }
+         }
+     };
+ }
+ 
+ #[cfg(any(
+     target_arch = "aarch64",
+     target_feature = "v7",
+     target_feature = "mclass"
+ ))]
+ mod common;
+ 
+ #[cfg(any(
+     target_arch = "aarch64",
+     target_feature = "v7",
+     target_feature = "mclass"
+ ))]
+ pub use self::common::*;
+ 
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
+ mod not_mclass;
+ 
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
+ pub use self::not_mclass::*;
+ 
+ #[cfg(target_arch = "aarch64")]
+ mod v8;
+ 
+ #[cfg(target_arch = "aarch64")]
+ pub use self::v8::*;
+ 
+ /// Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
+ ///
+ /// DMB ensures the observed ordering of memory accesses. Memory accesses of the specified type
+ /// issued before the DMB are guaranteed to be observed (in the specified scope) before memory
+ /// accesses issued after the DMB.
+ ///
+ /// For example, DMB should be used between storing data, and updating a flag variable that makes
+ /// that data available to another core.
+ ///
+ /// The __dmb() intrinsic also acts as a compiler memory barrier of the appropriate type.
+ #[inline(always)]
+ pub unsafe fn __dmb<A>(arg: A)
+ where
+     A: super::sealed::Dmb,
+ {
+     arg.__dmb()
+ }
+ 
+ /// Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
+ ///
+ /// DSB ensures the completion of memory accesses. A DSB behaves as the equivalent DMB and has
+ /// additional properties. After a DSB instruction completes, all memory accesses of the specified
+ /// type issued before the DSB are guaranteed to have completed.
+ ///
+ /// The __dsb() intrinsic also acts as a compiler memory barrier of the appropriate type.
+ #[inline(always)]
+ pub unsafe fn __dsb<A>(arg: A)
+ where
+     A: super::sealed::Dsb,
+ {
+     arg.__dsb()
+ }
+ 
+ /// Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15
+ /// instruction.
+ ///
+ /// This instruction flushes the processor pipeline fetch buffers, so that following instructions
+ /// are fetched from cache or memory.
+ ///
+ /// An ISB is needed after some system maintenance operations. An ISB is also needed before
+ /// transferring control to code that has been loaded or modified in memory, for example by an
+ /// overlay mechanism or just-in-time code generator.  (Note that if instruction and data caches are
+ /// separate, privileged cache maintenance operations would be needed in order to unify the caches.)
+ ///
+ /// The only supported argument for the __isb() intrinsic is 15, corresponding to the SY (full
+ /// system) scope of the ISB instruction.
+ #[inline(always)]
+ pub unsafe fn __isb<A>(arg: A)
+ where
+     A: super::sealed::Isb,
+ {
+     arg.__isb()
+ }
+ 
+ extern "C" {
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dmb")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dmb")]
+     fn dmb(_: i32);
+ 
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dsb")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dsb")]
+     fn dsb(_: i32);
+ 
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.isb")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.isb")]
+     fn isb(_: i32);
+ }
+ 
+ // we put these in a module to prevent weirdness with glob re-exports
+ mod arg {
+     // See Section 7.3  Memory barriers of ACLE
+     pub const SY: i32 = 15;
+     pub const ST: i32 = 14;
+     pub const LD: i32 = 13;
+     pub const ISH: i32 = 11;
+     pub const ISHST: i32 = 10;
+     pub const ISHLD: i32 = 9;
+     pub const NSH: i32 = 7;
+     pub const NSHST: i32 = 6;
+     pub const NSHLD: i32 = 5;
+     pub const OSH: i32 = 3;
+     pub const OSHST: i32 = 2;
+     pub const OSHLD: i32 = 1;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,43 ----
+ //! Access types available on v7 and v8 but not on v7(E)-M or v8-M
+ 
+ /// Full system is the required shareability domain, writes are the required
+ /// access type
+ pub struct ST;
+ 
+ dmb_dsb!(ST);
+ 
+ /// Inner Shareable is the required shareability domain, reads and writes are
+ /// the required access types
+ pub struct ISH;
+ 
+ dmb_dsb!(ISH);
+ 
+ /// Inner Shareable is the required shareability domain, writes are the required
+ /// access type
+ pub struct ISHST;
+ 
+ dmb_dsb!(ISHST);
+ 
+ /// Non-shareable is the required shareability domain, reads and writes are the
+ /// required access types
+ pub struct NSH;
+ 
+ dmb_dsb!(NSH);
+ 
+ /// Non-shareable is the required shareability domain, writes are the required
+ /// access type
+ pub struct NSHST;
+ 
+ dmb_dsb!(NSHST);
+ 
+ /// Outer Shareable is the required shareability domain, reads and writes are
+ /// the required access types
+ pub struct OSH;
+ 
+ dmb_dsb!(OSH);
+ 
+ /// Outer Shareable is the required shareability domain, writes are the required
+ /// access type
+ pub struct OSHST;
+ 
+ dmb_dsb!(OSHST);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,23 ----
+ /// Full system is the required shareability domain, reads are the required
+ /// access type
+ pub struct LD;
+ 
+ dmb_dsb!(LD);
+ 
+ /// Inner Shareable is the required shareability domain, reads are the required
+ /// access type
+ pub struct ISHLD;
+ 
+ dmb_dsb!(ISHLD);
+ 
+ /// Non-shareable is the required shareability domain, reads are the required
+ /// access type
+ pub struct NSHLD;
+ 
+ dmb_dsb!(NSHLD);
+ 
+ /// Outher Shareable is the required shareability domain, reads are the required
+ /// access type
+ pub struct OSHLD;
+ 
+ dmb_dsb!(OSHLD);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,384 ----
+ //! # References:
+ //!
+ //! - Section 8.3 "16-bit multiplications"
+ //!
+ //! Intrinsics that could live here:
+ //!
+ //! - \[x\] __smulbb
+ //! - \[x\] __smulbt
+ //! - \[x\] __smultb
+ //! - \[x\] __smultt
+ //! - \[x\] __smulwb
+ //! - \[x\] __smulwt
+ //! - \[x\] __qadd
+ //! - \[x\] __qsub
+ //! - \[x\] __qdbl
+ //! - \[x\] __smlabb
+ //! - \[x\] __smlabt
+ //! - \[x\] __smlatb
+ //! - \[x\] __smlatt
+ //! - \[x\] __smlawb
+ //! - \[x\] __smlawt
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ use crate::mem::transmute;
+ 
+ types! {
+     /// ARM-specific 32-bit wide vector of two packed `i16`.
+     pub struct int16x2_t(i16, i16);
+     /// ARM-specific 32-bit wide vector of two packed `u16`.
+     pub struct uint16x2_t(u16, u16);
+ }
+ 
+ extern "C" {
+     #[link_name = "llvm.arm.smulbb"]
+     fn arm_smulbb(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smulbt"]
+     fn arm_smulbt(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smultb"]
+     fn arm_smultb(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smultt"]
+     fn arm_smultt(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smulwb"]
+     fn arm_smulwb(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smulwt"]
+     fn arm_smulwt(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qadd"]
+     fn arm_qadd(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qsub"]
+     fn arm_qsub(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlabb"]
+     fn arm_smlabb(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlabt"]
+     fn arm_smlabt(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlatb"]
+     fn arm_smlatb(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlatt"]
+     fn arm_smlatt(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlawb"]
+     fn arm_smlawb(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlawt"]
+     fn arm_smlawt(a: i32, b: i32, c: i32) -> i32;
+ }
+ 
+ /// Insert a SMULBB instruction
+ ///
+ /// Returns the equivalent of a\[0\] * b\[0\]
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smulbb))]
+ pub unsafe fn __smulbb(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smulbb(transmute(a), transmute(b))
+ }
+ 
+ /// Insert a SMULTB instruction
+ ///
+ /// Returns the equivalent of a\[0\] * b\[1\]
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smultb))]
+ pub unsafe fn __smultb(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smultb(transmute(a), transmute(b))
+ }
+ 
+ /// Insert a SMULTB instruction
+ ///
+ /// Returns the equivalent of a\[1\] * b\[0\]
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smulbt))]
+ pub unsafe fn __smulbt(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smulbt(transmute(a), transmute(b))
+ }
+ 
+ /// Insert a SMULTT instruction
+ ///
+ /// Returns the equivalent of a\[1\] * b\[1\]
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smultt))]
+ pub unsafe fn __smultt(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smultt(transmute(a), transmute(b))
+ }
+ 
+ /// Insert a SMULWB instruction
+ ///
+ /// Multiplies the 32-bit signed first operand with the low halfword
+ /// (as a 16-bit signed integer) of the second operand.
+ /// Return the top 32 bits of the 48-bit product
+ #[inline]
+ #[cfg_attr(test, assert_instr(smulwb))]
+ pub unsafe fn __smulwb(a: int16x2_t, b: i32) -> i32 {
+     arm_smulwb(transmute(a), b)
+ }
+ 
+ /// Insert a SMULWT instruction
+ ///
+ /// Multiplies the 32-bit signed first operand with the high halfword
+ /// (as a 16-bit signed integer) of the second operand.
+ /// Return the top 32 bits of the 48-bit product
+ #[inline]
+ #[cfg_attr(test, assert_instr(smulwt))]
+ pub unsafe fn __smulwt(a: int16x2_t, b: i32) -> i32 {
+     arm_smulwt(transmute(a), b)
+ }
+ 
+ /// Signed saturating addition
+ ///
+ /// Returns the 32-bit saturating signed equivalent of a + b.
+ /// Sets the Q flag if saturation occurs.
+ #[inline]
+ #[cfg_attr(test, assert_instr(qadd))]
+ pub unsafe fn __qadd(a: i32, b: i32) -> i32 {
+     arm_qadd(a, b)
+ }
+ 
+ /// Signed saturating subtraction
+ ///
+ /// Returns the 32-bit saturating signed equivalent of a - b.
+ /// Sets the Q flag if saturation occurs.
+ #[inline]
+ #[cfg_attr(test, assert_instr(qsub))]
+ pub unsafe fn __qsub(a: i32, b: i32) -> i32 {
+     arm_qsub(a, b)
+ }
+ 
+ /// Insert a QADD instruction
+ ///
+ /// Returns the 32-bit saturating signed equivalent of a + a
+ /// Sets the Q flag if saturation occurs.
+ #[inline]
+ #[cfg_attr(test, assert_instr(qadd))]
+ pub unsafe fn __qdbl(a: i32) -> i32 {
+     arm_qadd(a, a)
+ }
+ 
+ /// Insert a SMLABB instruction
+ ///
+ /// Returns the equivalent of a\[0\] * b\[0\] + c
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ /// Sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlabb))]
+ pub unsafe fn __smlabb(a: int16x2_t, b: int16x2_t, c: i32) -> i32 {
+     arm_smlabb(transmute(a), transmute(b), c)
+ }
+ 
+ /// Insert a SMLABT instruction
+ ///
+ /// Returns the equivalent of a\[0\] * b\[1\] + c
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ /// Sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlabt))]
+ pub unsafe fn __smlabt(a: int16x2_t, b: int16x2_t, c: i32) -> i32 {
+     arm_smlabt(transmute(a), transmute(b), c)
+ }
+ 
+ /// Insert a SMLATB instruction
+ ///
+ /// Returns the equivalent of a\[1\] * b\[0\] + c
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ /// Sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlatb))]
+ pub unsafe fn __smlatb(a: int16x2_t, b: int16x2_t, c: i32) -> i32 {
+     arm_smlatb(transmute(a), transmute(b), c)
+ }
+ 
+ /// Insert a SMLATT instruction
+ ///
+ /// Returns the equivalent of a\[1\] * b\[1\] + c
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ /// Sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlatt))]
+ pub unsafe fn __smlatt(a: int16x2_t, b: int16x2_t, c: i32) -> i32 {
+     arm_smlatt(transmute(a), transmute(b), c)
+ }
+ 
+ /// Insert a SMLAWB instruction
+ ///
+ /// Returns the equivalent of (a * b\[0\] + (c << 16)) >> 16
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ /// Sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlawb))]
+ pub unsafe fn __smlawb(a: i32, b: int16x2_t, c: i32) -> i32 {
+     arm_smlawb(a, transmute(b), c)
+ }
+ 
+ /// Insert a SMLAWT instruction
+ ///
+ /// Returns the equivalent of (a * b\[1\] + (c << 16)) >> 16
+ /// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits.
+ /// Sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlawt))]
+ pub unsafe fn __smlawt(a: i32, b: int16x2_t, c: i32) -> i32 {
+     arm_smlawt(a, transmute(b), c)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::{
+         arm::*,
+         simd::{i16x2, i8x4, u8x4},
+     };
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ 
+     #[test]
+     fn smulbb() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             assert_eq!(super::__smulbb(transmute(a), transmute(b)), 10 * 30);
+         }
+     }
+ 
+     #[test]
+     fn smulbt() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             assert_eq!(super::__smulbt(transmute(a), transmute(b)), 10 * 40);
+         }
+     }
+ 
+     #[test]
+     fn smultb() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             assert_eq!(super::__smultb(transmute(a), transmute(b)), 20 * 30);
+         }
+     }
+ 
+     #[test]
+     fn smultt() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             assert_eq!(super::__smultt(transmute(a), transmute(b)), 20 * 40);
+         }
+     }
+ 
+     #[test]
+     fn smulwb() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = 30;
+             assert_eq!(super::__smulwb(transmute(a), b), 20 * b);
+         }
+     }
+ 
+     #[test]
+     fn smulwt() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = 30;
+             assert_eq!(super::__smulwt(transmute(a), b), (10 * b) >> 16);
+         }
+     }
+ 
+     #[test]
+     fn qadd() {
+         unsafe {
+             assert_eq!(super::__qadd(-10, 60), 50);
+             assert_eq!(super::__qadd(i32::MAX, 10), i32::MAX);
+             assert_eq!(super::__qadd(i32::MIN, -10), i32::MIN);
+         }
+     }
+ 
+     #[test]
+     fn qsub() {
+         unsafe {
+             assert_eq!(super::__qsub(10, 60), -50);
+             assert_eq!(super::__qsub(i32::MAX, -10), i32::MAX);
+             assert_eq!(super::__qsub(i32::MIN, 10), i32::MIN);
+         }
+     }
+ 
+     fn qdbl() {
+         unsafe {
+             assert_eq!(super::__qdbl(10), 20);
+             assert_eq!(super::__qdbl(i32::MAX), i32::MAX);
+         }
+     }
+ 
+     fn smlabb() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             let c = 50;
+             let r = (10 * 30) + c;
+             assert_eq!(super::__smlabb(transmute(a), transmute(b), c), r);
+         }
+     }
+ 
+     fn smlabt() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             let c = 50;
+             let r = (10 * 40) + c;
+             assert_eq!(super::__smlabt(transmute(a), transmute(b), c), r);
+         }
+     }
+ 
+     fn smlatb() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             let c = 50;
+             let r = (20 * 30) + c;
+             assert_eq!(super::__smlabt(transmute(a), transmute(b), c), r);
+         }
+     }
+ 
+     fn smlatt() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(30, 40);
+             let c = 50;
+             let r = (20 * 40) + c;
+             assert_eq!(super::__smlatt(transmute(a), transmute(b), c), r);
+         }
+     }
+ 
+     fn smlawb() {
+         unsafe {
+             let a: i32 = 10;
+             let b = i16x2::new(30, 40);
+             let c: i32 = 50;
+             let r: i32 = ((a * 30) + (c << 16)) >> 16;
+             assert_eq!(super::__smlawb(a, transmute(b), c), r);
+         }
+     }
+ 
+     fn smlawt() {
+         unsafe {
+             let a: i32 = 10;
+             let b = i16x2::new(30, 40);
+             let c: i32 = 50;
+             let r: i32 = ((a * 40) + (c << 16)) >> 16;
+             assert_eq!(super::__smlawt(a, transmute(b), c), r);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,117 ----
+ // Reference: Section 5.4.4 "LDREX / STREX" of ACLE
+ 
+ /// Removes the exclusive lock created by LDREX
+ // Supported: v6, v6K, v7-M, v7-A, v7-R
+ // Not supported: v5, v6-M
+ // NOTE: there's no dedicated CLREX instruction in v6 (<v6k); to clear the exclusive monitor users
+ // have to do a dummy STREX operation
+ #[cfg(any(
+     all(target_feature = "v6k", not(target_feature = "mclass")), // excludes v6-M
+     all(target_feature = "v7", target_feature = "mclass"), // v7-M
+ ))]
+ pub unsafe fn __clrex() {
+     extern "C" {
+         #[link_name = "llvm.arm.clrex"]
+         fn clrex();
+     }
+ 
+     clrex()
+ }
+ 
+ /// Executes a exclusive LDR instruction for 8 bit value.
+ // Supported: v6K, v7-M, v7-A, v7-R
+ // Not supported: v5, v6, v6-M
+ #[cfg(
+     target_feature = "v6k", // includes v7-M but excludes v6-M
+ )]
+ pub unsafe fn __ldrexb(p: *const u8) -> u8 {
+     extern "C" {
+         #[link_name = "llvm.arm.ldrex.p0i8"]
+         fn ldrex8(p: *const u8) -> u32;
+     }
+ 
+     ldrex8(p) as u8
+ }
+ 
+ /// Executes a exclusive LDR instruction for 16 bit value.
+ // Supported: v6K, v7-M, v7-A, v7-R, v8
+ // Not supported: v5, v6, v6-M
+ #[cfg(
+     target_feature = "v6k", // includes v7-M but excludes v6-M
+ )]
+ pub unsafe fn __ldrexh(p: *const u16) -> u16 {
+     extern "C" {
+         #[link_name = "llvm.arm.ldrex.p0i16"]
+         fn ldrex16(p: *const u16) -> u32;
+     }
+ 
+     ldrex16(p) as u16
+ }
+ 
+ /// Executes a exclusive LDR instruction for 32 bit value.
+ // Supported: v6, v7-M, v6K, v7-A, v7-R, v8
+ // Not supported: v5, v6-M
+ #[cfg(any(
+     all(target_feature = "v6", not(target_feature = "mclass")), // excludes v6-M
+     all(target_feature = "v7", target_feature = "mclass"), // v7-M
+ ))]
+ pub unsafe fn __ldrex(p: *const u32) -> u32 {
+     extern "C" {
+         #[link_name = "llvm.arm.ldrex.p0i32"]
+         fn ldrex32(p: *const u32) -> u32;
+     }
+ 
+     ldrex32(p)
+ }
+ 
+ /// Executes a exclusive STR instruction for 8 bit values
+ ///
+ /// Returns `0` if the operation succeeded, or `1` if it failed
+ // supported: v6K, v7-M, v7-A, v7-R
+ // Not supported: v5, v6, v6-M
+ #[cfg(
+     target_feature = "v6k", // includes v7-M but excludes v6-M
+ )]
+ pub unsafe fn __strexb(value: u32, addr: *mut u8) -> u32 {
+     extern "C" {
+         #[link_name = "llvm.arm.strex.p0i8"]
+         fn strex8(value: u32, addr: *mut u8) -> u32;
+     }
+ 
+     strex8(value, addr)
+ }
+ 
+ /// Executes a exclusive STR instruction for 16 bit values
+ ///
+ /// Returns `0` if the operation succeeded, or `1` if it failed
+ // Supported: v6K, v7-M, v7-A, v7-R, v8
+ // Not supported: v5, v6, v6-M
+ #[cfg(
+     target_feature = "v6k", // includes v7-M but excludes v6-M
+ )]
+ pub unsafe fn __strexh(value: u16, addr: *mut u16) -> u32 {
+     extern "C" {
+         #[link_name = "llvm.arm.strex.p0i16"]
+         fn strex16(value: u32, addr: *mut u16) -> u32;
+     }
+ 
+     strex16(value as u32, addr)
+ }
+ 
+ /// Executes a exclusive STR instruction for 32 bit values
+ ///
+ /// Returns `0` if the operation succeeded, or `1` if it failed
+ // Supported: v6, v7-M, v6K, v7-A, v7-R, v8
+ // Not supported: v5, v6-M
+ #[cfg(any(
+     all(target_feature = "v6", not(target_feature = "mclass")), // excludes v6-M
+     all(target_feature = "v7", target_feature = "mclass"), // v7-M
+ ))]
+ pub unsafe fn __strex(value: u32, addr: *mut u32) -> u32 {
+     extern "C" {
+         #[link_name = "llvm.arm.strex.p0i32"]
+         fn strex32(value: u32, addr: *mut u32) -> u32;
+     }
+ 
+     strex32(value, addr)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,135 ----
+ // # References
+ //
+ // - Section 7.4 "Hints" of ACLE
+ // - Section 7.7 "NOP" of ACLE
+ 
+ /// Generates a WFI (wait for interrupt) hint instruction, or nothing.
+ ///
+ /// The WFI instruction allows (but does not require) the processor to enter a
+ /// low-power state until one of a number of asynchronous events occurs.
+ // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
+ // LLVM says "instruction requires: armv6k"
+ #[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+ #[inline(always)]
+ pub unsafe fn __wfi() {
+     hint(HINT_WFI);
+ }
+ 
+ /// Generates a WFE (wait for event) hint instruction, or nothing.
+ ///
+ /// The WFE instruction allows (but does not require) the processor to enter a
+ /// low-power state until some event occurs such as a SEV being issued by
+ /// another processor.
+ // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
+ // LLVM says "instruction requires: armv6k"
+ #[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+ #[inline(always)]
+ pub unsafe fn __wfe() {
+     hint(HINT_WFE);
+ }
+ 
+ /// Generates a SEV (send a global event) hint instruction.
+ ///
+ /// This causes an event to be signaled to all processors in a multiprocessor
+ /// system. It is a NOP on a uniprocessor system.
+ // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M, 7-M
+ // LLVM says "instruction requires: armv6k"
+ #[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+ #[inline(always)]
+ pub unsafe fn __sev() {
+     hint(HINT_SEV);
+ }
+ 
+ /// Generates a send a local event hint instruction.
+ ///
+ /// This causes an event to be signaled to only the processor executing this
+ /// instruction. In a multiprocessor system, it is not required to affect the
+ /// other processors.
+ // LLVM says "instruction requires: armv8"
+ #[cfg(any(
+     target_feature = "v8", // 32-bit ARMv8
+     target_arch = "aarch64", // AArch64
+ ))]
+ #[inline(always)]
+ pub unsafe fn __sevl() {
+     hint(HINT_SEVL);
+ }
+ 
+ /// Generates a YIELD hint instruction.
+ ///
+ /// This enables multithreading software to indicate to the hardware that it is
+ /// performing a task, for example a spin-lock, that could be swapped out to
+ /// improve overall system performance.
+ // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
+ // LLVM says "instruction requires: armv6k"
+ #[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+ #[inline(always)]
+ pub unsafe fn __yield() {
+     hint(HINT_YIELD);
+ }
+ 
+ /// Generates a DBG instruction.
+ ///
+ /// This provides a hint to debugging and related systems. The argument must be
+ /// a constant integer from 0 to 15 inclusive. See implementation documentation
+ /// for the effect (if any) of this instruction and the meaning of the
+ /// argument. This is available only when compliling for AArch32.
+ // Section 10.1 of ACLE says that the supported arches are: 7, 7-M
+ // "The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and
+ // executes as a NOP instruction in ARMv6K and ARMv6T2." - ARM Architecture Reference Manual ARMv7-A
+ // and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2
+ // "Thumb instruction set support"
+ #[cfg(target_feature = "v7")]
+ #[inline(always)]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __dbg(imm4: u32) {
+     macro_rules! call {
+         ($imm4:expr) => {
+             llvm_asm!(concat!("DBG ", stringify!($imm4)) : : : : "volatile")
+         }
+     }
+ 
+     match imm4 & 0b1111 {
+         0 => call!(0),
+         1 => call!(1),
+         2 => call!(2),
+         3 => call!(3),
+         4 => call!(4),
+         5 => call!(5),
+         6 => call!(6),
+         7 => call!(7),
+         8 => call!(8),
+         9 => call!(9),
+         10 => call!(10),
+         11 => call!(11),
+         12 => call!(12),
+         13 => call!(13),
+         14 => call!(14),
+         _ => call!(15),
+     }
+ }
+ 
+ /// Generates an unspecified no-op instruction.
+ ///
+ /// Note that not all architectures provide a distinguished NOP instruction. On
+ /// those that do, it is unspecified whether this intrinsic generates it or
+ /// another instruction. It is not guaranteed that inserting this instruction
+ /// will increase execution time.
+ #[inline(always)]
+ pub unsafe fn __nop() {
+     llvm_asm!("NOP" : : : : "volatile")
+ }
+ 
+ extern "C" {
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.hint")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.hint")]
+     fn hint(_: i32);
+ }
+ 
+ // from LLVM 7.0.1's lib/Target/ARM/{ARMInstrThumb,ARMInstrInfo,ARMInstrThumb2}.td
+ const HINT_NOP: i32 = 0;
+ const HINT_YIELD: i32 = 1;
+ const HINT_WFE: i32 = 2;
+ const HINT_WFI: i32 = 3;
+ const HINT_SEV: i32 = 4;
+ const HINT_SEVL: i32 = 5;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,158 ----
+ //! ARM C Language Extensions (ACLE)
+ //!
+ //! # Developer notes
+ //!
+ //! Below is a list of built-in targets that are representative of the different ARM
+ //! architectures; the list includes the `target_feature`s they possess.
+ //!
+ //! - `armv4t-unknown-linux-gnueabi` - **ARMv4** - `+v4t`
+ //! - `armv5te-unknown-linux-gnueabi` - **ARMv5TE** - `+v4t +v5te`
+ //! - `arm-unknown-linux-gnueabi` - **ARMv6** - `+v4t +v5te +v6`
+ //! - `thumbv6m-none-eabi` - **ARMv6-M** - `+v4t +v5te +v6 +thumb-mode +mclass`
+ //! - `armv7-unknown-linux-gnueabihf` - **ARMv7-A** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +aclass`
+ //! - `armv7r-none-eabi` - **ARMv7-R** - `+v4t +v5te +v6 +v6k +v6t2  +v7 +dsp +thumb2 +rclass`
+ //! - `thumbv7m-none-eabi` - **ARMv7-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +thumb2 +thumb-mode +mclass`
+ //! - `thumbv7em-none-eabi` - **ARMv7E-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +thumb-mode +mclass`
+ //! - `thumbv8m.main-none-eabi` - **ARMv8-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +thumb2 +thumb-mode +mclass`
+ //! - `armv8r-none-eabi` - **ARMv8-R** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +v8 +thumb2 +rclass`
+ //! - `aarch64-unknown-linux-gnu` - **ARMv8-A (AArch64)** - `+fp +neon`
+ //!
+ //! Section 10.1 of ACLE says:
+ //!
+ //! - "In the sequence of Arm architectures { v5, v5TE, v6, v6T2, v7 } each architecture includes
+ //! its predecessor instruction set."
+ //!
+ //! - "In the sequence of Thumb-only architectures { v6-M, v7-M, v7E-M } each architecture includes
+ //! its predecessor instruction set."
+ //!
+ //! From that info and from looking at how LLVM features work (using custom targets) we can identify
+ //! features that are subsets of others:
+ //!
+ //! Legend: `a < b` reads as "`a` is a subset of `b`"; this means that if `b` is enabled then `a` is
+ //! enabled as well.
+ //!
+ //! - `v4t < v5te < v6 < v6k < v6t2 < v7 < v8`
+ //! - `v6 < v8m < v6t2`
+ //! - `v7 < v8m.main`
+ //!
+ //! *NOTE*: Section 5.4.7 of ACLE says:
+ //!
+ //! - "__ARM_FEATURE_DSP is defined to 1 if the DSP (v5E) instructions are supported and the
+ //! intrinsics defined in Saturating intrinsics are available."
+ //!
+ //! This does *not* match how LLVM uses the '+dsp' feature; this feature is not set for v5te
+ //! targets so we have to work around this difference.
+ //!
+ //! # References
+ //!
+ //! - [ACLE Q2 2018](https://developer.arm.com/docs/101028/latest)
+ 
+ // 8, 7 and 6-M are supported via dedicated instructions like DMB. All other arches are supported
+ // via CP15 instructions. See Section 10.1 of ACLE
+ mod barrier;
+ 
+ pub use self::barrier::*;
+ 
+ mod hints;
+ 
+ pub use self::hints::*;
+ 
+ mod registers;
+ 
+ pub use self::registers::*;
+ 
+ mod ex;
+ 
+ pub use self::ex::*;
+ 
+ // Supported arches: 5TE, 7E-M. See Section 10.1 of ACLE (e.g. QADD)
+ // We also include the A profile even though DSP is deprecated on that profile as of ACLE 2.0 (see
+ // section 5.4.7)
+ // Here we workaround the difference between LLVM's +dsp and ACLE's __ARM_FEATURE_DSP by gating on
+ // '+v5te' rather than on '+dsp'
+ #[cfg(all(
+     not(target_arch = "aarch64"),
+     any(
+         // >= v5TE but excludes v7-M
+         all(target_feature = "v5te", not(target_feature = "mclass")),
+         // v7E-M
+         all(target_feature = "mclass", target_feature = "dsp"),
+     )
+ ))]
+ mod dsp;
+ 
+ #[cfg(all(
+     not(target_arch = "aarch64"),
+     any(
+         all(target_feature = "v5te", not(target_feature = "mclass")),
+         all(target_feature = "mclass", target_feature = "dsp"),
+     )
+ ))]
+ pub use self::dsp::*;
+ 
+ // Supported arches: 6, 7-M. See Section 10.1 of ACLE (e.g. SSAT)
+ #[cfg(all(not(target_arch = "aarch64"), target_feature = "v6",))]
+ mod sat;
+ 
+ #[cfg(all(not(target_arch = "aarch64"), target_feature = "v6",))]
+ pub use self::sat::*;
+ 
+ // Deprecated in ACLE 2.0 for the A profile but fully supported on the M and R profiles, says
+ // Section 5.4.9 of ACLE. We'll expose these for the A profile even if deprecated
+ #[cfg(all(
+     not(target_arch = "aarch64"),
+     any(
+         // v7-A, v7-R
+         all(target_feature = "v6", not(target_feature = "mclass")),
+         // v7E-M
+         all(target_feature = "mclass", target_feature = "dsp")
+     )
+ ))]
+ mod simd32;
+ 
+ #[cfg(all(
+     not(target_arch = "aarch64"),
+     any(
+         all(target_feature = "v6", not(target_feature = "mclass")),
+         all(target_feature = "mclass", target_feature = "dsp")
+     )
+ ))]
+ pub use self::simd32::*;
+ 
+ mod sealed {
+     pub trait Dmb {
+         unsafe fn __dmb(&self);
+     }
+ 
+     pub trait Dsb {
+         unsafe fn __dsb(&self);
+     }
+ 
+     pub trait Isb {
+         unsafe fn __isb(&self);
+     }
+ 
+     pub trait Rsr {
+         unsafe fn __rsr(&self) -> u32;
+     }
+ 
+     pub trait Rsr64 {
+         unsafe fn __rsr64(&self) -> u64;
+     }
+ 
+     pub trait Rsrp {
+         unsafe fn __rsrp(&self) -> *const u8;
+     }
+ 
+     pub trait Wsr {
+         unsafe fn __wsr(&self, value: u32);
+     }
+ 
+     pub trait Wsr64 {
+         unsafe fn __wsr64(&self, value: u64);
+     }
+ 
+     pub trait Wsrp {
+         unsafe fn __wsrp(&self, value: *const u8);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,9 ----
+ /// Application Program Status Register
+ pub struct APSR;
+ 
+ // Note (@Lokathor): Because this breaks the use of Rust on the Game Boy
+ // Advance, this change must be reverted until Rust learns to handle cpu state
+ // properly. See also: https://github.com/rust-lang/stdarch/issues/702
+ 
+ //#[cfg(any(not(target_feature = "thumb-state"), target_feature = "v6t2"))]
+ //rsr!(APSR);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,121 ----
+ #[allow(unused_macros)]
+ macro_rules! rsr {
+     ($R:ident) => {
+         impl super::super::sealed::Rsr for $R {
+             unsafe fn __rsr(&self) -> u32 {
+                 let r: u32;
+                 llvm_asm!(concat!("mrs $0,", stringify!($R)) : "=r"(r) : : : "volatile");
+                 r
+             }
+         }
+     };
+ }
+ 
+ #[allow(unused_macros)]
+ macro_rules! rsrp {
+     ($R:ident) => {
+         impl super::super::sealed::Rsrp for $R {
+             unsafe fn __rsrp(&self) -> *const u8 {
+                 let r: *const u8;
+                 llvm_asm!(concat!("mrs $0,", stringify!($R)) : "=r"(r) : : : "volatile");
+                 r
+             }
+         }
+     };
+ }
+ 
+ #[allow(unused_macros)]
+ macro_rules! wsr {
+     ($R:ident) => {
+         impl super::super::sealed::Wsr for $R {
+             unsafe fn __wsr(&self, value: u32) {
+                 llvm_asm!(concat!("msr ", stringify!($R), ",$0") : : "r"(value) : : "volatile");
+             }
+         }
+     };
+ }
+ 
+ #[allow(unused_macros)]
+ macro_rules! wsrp {
+     ($R:ident) => {
+         impl super::super::sealed::Wsrp for $R {
+             unsafe fn __wsrp(&self, value: *const u8) {
+                 llvm_asm!(concat!("msr ", stringify!($R), ",$0") : : "r"(value) : : "volatile");
+             }
+         }
+     };
+ }
+ 
+ #[cfg(target_feature = "mclass")]
+ mod v6m;
+ 
+ #[cfg(target_feature = "mclass")]
+ pub use self::v6m::*;
+ 
+ #[cfg(all(target_feature = "v7", target_feature = "mclass"))]
+ mod v7m;
+ 
+ #[cfg(all(target_feature = "v7", target_feature = "mclass"))]
+ pub use self::v7m::*;
+ 
+ #[cfg(not(target_arch = "aarch64"))]
+ mod aarch32;
+ 
+ #[cfg(not(target_arch = "aarch64"))]
+ pub use self::aarch32::*;
+ 
+ /// Reads a 32-bit system register
+ #[inline(always)]
+ pub unsafe fn __rsr<R>(reg: R) -> u32
+ where
+     R: super::sealed::Rsr,
+ {
+     reg.__rsr()
+ }
+ 
+ /// Reads a 64-bit system register
+ #[cfg(target_arch = "aarch64")]
+ #[inline(always)]
+ pub unsafe fn __rsr64<R>(reg: R) -> u64
+ where
+     R: super::sealed::Rsr64,
+ {
+     reg.__rsr64()
+ }
+ 
+ /// Reads a system register containing an address
+ #[inline(always)]
+ pub unsafe fn __rsrp<R>(reg: R) -> *const u8
+ where
+     R: super::sealed::Rsrp,
+ {
+     reg.__rsrp()
+ }
+ 
+ /// Writes a 32-bit system register
+ #[inline(always)]
+ pub unsafe fn __wsr<R>(reg: R, value: u32)
+ where
+     R: super::sealed::Wsr,
+ {
+     reg.__wsr(value)
+ }
+ 
+ /// Writes a 64-bit system register
+ #[cfg(target_arch = "aarch64")]
+ #[inline(always)]
+ pub unsafe fn __wsr64<R>(reg: R, value: u64)
+ where
+     R: super::sealed::Wsr64,
+ {
+     reg.__wsr64(value)
+ }
+ 
+ /// Writes a system register containing an address
+ #[inline(always)]
+ pub unsafe fn __wsrp<R>(reg: R, value: *const u8)
+ where
+     R: super::sealed::Wsrp,
+ {
+     reg.__wsrp(value)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,39 ----
+ /// CONTROL register
+ pub struct CONTROL;
+ 
+ rsr!(CONTROL);
+ wsr!(CONTROL);
+ 
+ /// Execution Program Status Register
+ pub struct EPSR;
+ 
+ rsr!(EPSR);
+ 
+ /// Interrupt Program Status Register
+ pub struct IPSR;
+ 
+ rsr!(IPSR);
+ 
+ /// Main Stack Pointer
+ pub struct MSP;
+ 
+ rsrp!(MSP);
+ wsrp!(MSP);
+ 
+ /// Priority Mask Register
+ pub struct PRIMASK;
+ 
+ rsr!(PRIMASK);
+ wsr!(PRIMASK);
+ 
+ /// Process Stack Pointer
+ pub struct PSP;
+ 
+ rsrp!(PSP);
+ wsrp!(PSP);
+ 
+ /// Program Status Register
+ #[allow(non_camel_case_types)]
+ pub struct xPSR;
+ 
+ rsr!(xPSR);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,17 ----
+ /// Base Priority Mask Register
+ pub struct BASEPRI;
+ 
+ rsr!(BASEPRI);
+ wsr!(BASEPRI);
+ 
+ /// Base Priority Mask Register (conditional write)
+ #[allow(non_camel_case_types)]
+ pub struct BASEPRI_MAX;
+ 
+ wsr!(BASEPRI_MAX);
+ 
+ /// Fault Mask Register
+ pub struct FAULTMASK;
+ 
+ rsr!(FAULTMASK);
+ wsr!(FAULTMASK);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,8 ----
+ //! # References:
+ //!
+ //! - Section 8.4 "Saturating intrinsics"
+ //!
+ //! Intrinsics that could live here:
+ //!
+ //! - __ssat
+ //! - __usat
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,728 ----
+ //! # References
+ //!
+ //! - Section 8.5 "32-bit SIMD intrinsics" of ACLE
+ //!
+ //! Intrinsics that could live here
+ //!
+ //! - \[x\] __sel
+ //! - \[ \] __ssat16
+ //! - \[ \] __usat16
+ //! - \[ \] __sxtab16
+ //! - \[ \] __sxtb16
+ //! - \[ \] __uxtab16
+ //! - \[ \] __uxtb16
+ //! - \[x\] __qadd8
+ //! - \[x\] __qsub8
+ //! - \[x\] __sadd8
+ //! - \[x\] __shadd8
+ //! - \[x\] __shsub8
+ //! - \[x\] __ssub8
+ //! - \[ \] __uadd8
+ //! - \[ \] __uhadd8
+ //! - \[ \] __uhsub8
+ //! - \[ \] __uqadd8
+ //! - \[ \] __uqsub8
+ //! - \[x\] __usub8
+ //! - \[x\] __usad8
+ //! - \[x\] __usada8
+ //! - \[x\] __qadd16
+ //! - \[x\] __qasx
+ //! - \[x\] __qsax
+ //! - \[x\] __qsub16
+ //! - \[x\] __sadd16
+ //! - \[x\] __sasx
+ //! - \[x\] __shadd16
+ //! - \[ \] __shasx
+ //! - \[ \] __shsax
+ //! - \[x\] __shsub16
+ //! - \[ \] __ssax
+ //! - \[ \] __ssub16
+ //! - \[ \] __uadd16
+ //! - \[ \] __uasx
+ //! - \[ \] __uhadd16
+ //! - \[ \] __uhasx
+ //! - \[ \] __uhsax
+ //! - \[ \] __uhsub16
+ //! - \[ \] __uqadd16
+ //! - \[ \] __uqasx
+ //! - \[x\] __uqsax
+ //! - \[ \] __uqsub16
+ //! - \[ \] __usax
+ //! - \[ \] __usub16
+ //! - \[x\] __smlad
+ //! - \[ \] __smladx
+ //! - \[ \] __smlald
+ //! - \[ \] __smlaldx
+ //! - \[x\] __smlsd
+ //! - \[ \] __smlsdx
+ //! - \[ \] __smlsld
+ //! - \[ \] __smlsldx
+ //! - \[x\] __smuad
+ //! - \[x\] __smuadx
+ //! - \[x\] __smusd
+ //! - \[x\] __smusdx
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ use crate::{core_arch::acle::dsp::int16x2_t, mem::transmute};
+ 
+ types! {
+     /// ARM-specific 32-bit wide vector of four packed `i8`.
+     pub struct int8x4_t(i8, i8, i8, i8);
+     /// ARM-specific 32-bit wide vector of four packed `u8`.
+     pub struct uint8x4_t(u8, u8, u8, u8);
+ }
+ 
+ macro_rules! dsp_call {
+     ($name:expr, $a:expr, $b:expr) => {
+         transmute($name(transmute($a), transmute($b)))
+     };
+ }
+ 
+ extern "C" {
+     #[link_name = "llvm.arm.qadd8"]
+     fn arm_qadd8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qsub8"]
+     fn arm_qsub8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qsub16"]
+     fn arm_qsub16(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qadd16"]
+     fn arm_qadd16(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qasx"]
+     fn arm_qasx(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.qsax"]
+     fn arm_qsax(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.sadd16"]
+     fn arm_sadd16(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.sadd8"]
+     fn arm_sadd8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlad"]
+     fn arm_smlad(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smlsd"]
+     fn arm_smlsd(a: i32, b: i32, c: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.sasx"]
+     fn arm_sasx(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.sel"]
+     fn arm_sel(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.shadd8"]
+     fn arm_shadd8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.shadd16"]
+     fn arm_shadd16(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.shsub8"]
+     fn arm_shsub8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.ssub8"]
+     fn arm_ssub8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.usub8"]
+     fn arm_usub8(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.shsub16"]
+     fn arm_shsub16(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smuad"]
+     fn arm_smuad(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smuadx"]
+     fn arm_smuadx(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smusd"]
+     fn arm_smusd(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.smusdx"]
+     fn arm_smusdx(a: i32, b: i32) -> i32;
+ 
+     #[link_name = "llvm.arm.usad8"]
+     fn arm_usad8(a: i32, b: i32) -> u32;
+ }
+ 
+ /// Saturating four 8-bit integer additions
+ ///
+ /// Returns the 8-bit signed equivalent of
+ ///
+ /// res\[0\] = a\[0\] + b\[0\]
+ /// res\[1\] = a\[1\] + b\[1\]
+ /// res\[2\] = a\[2\] + b\[2\]
+ /// res\[3\] = a\[3\] + b\[3\]
+ #[inline]
+ #[cfg_attr(test, assert_instr(qadd8))]
+ pub unsafe fn __qadd8(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_qadd8, a, b)
+ }
+ 
+ /// Saturating two 8-bit integer subtraction
+ ///
+ /// Returns the 8-bit signed equivalent of
+ ///
+ /// res\[0\] = a\[0\] - b\[0\]
+ /// res\[1\] = a\[1\] - b\[1\]
+ /// res\[2\] = a\[2\] - b\[2\]
+ /// res\[3\] = a\[3\] - b\[3\]
+ #[inline]
+ #[cfg_attr(test, assert_instr(qsub8))]
+ pub unsafe fn __qsub8(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_qsub8, a, b)
+ }
+ 
+ /// Saturating two 16-bit integer subtraction
+ ///
+ /// Returns the 16-bit signed equivalent of
+ ///
+ /// res\[0\] = a\[0\] - b\[0\]
+ /// res\[1\] = a\[1\] - b\[1\]
+ #[inline]
+ #[cfg_attr(test, assert_instr(qsub16))]
+ pub unsafe fn __qsub16(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_qsub16, a, b)
+ }
+ 
+ /// Saturating two 16-bit integer additions
+ ///
+ /// Returns the 16-bit signed equivalent of
+ ///
+ /// res\[0\] = a\[0\] + b\[0\]
+ /// res\[1\] = a\[1\] + b\[1\]
+ #[inline]
+ #[cfg_attr(test, assert_instr(qadd16))]
+ pub unsafe fn __qadd16(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_qadd16, a, b)
+ }
+ 
+ /// Returns the 16-bit signed saturated equivalent of
+ ///
+ /// res\[0\] = a\[0\] - b\[1\]
+ /// res\[1\] = a\[1\] + b\[0\]
+ #[inline]
+ #[cfg_attr(test, assert_instr(qasx))]
+ pub unsafe fn __qasx(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_qasx, a, b)
+ }
+ 
+ /// Returns the 16-bit signed saturated equivalent of
+ ///
+ /// res\[0\] = a\[0\] + b\[1\]
+ /// res\[1\] = a\[1\] - b\[0\]
+ #[inline]
+ #[cfg_attr(test, assert_instr(qsax))]
+ pub unsafe fn __qsax(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_qsax, a, b)
+ }
+ 
+ /// Returns the 16-bit signed saturated equivalent of
+ ///
+ /// res\[0\] = a\[0\] + b\[1\]
+ /// res\[1\] = a\[1\] + b\[0\]
+ ///
+ /// and the GE bits of the APSR are set.
+ #[inline]
+ #[cfg_attr(test, assert_instr(sadd16))]
+ pub unsafe fn __sadd16(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_sadd16, a, b)
+ }
+ 
+ /// Returns the 8-bit signed saturated equivalent of
+ ///
+ /// res\[0\] = a\[0\] + b\[1\]
+ /// res\[1\] = a\[1\] + b\[0\]
+ /// res\[2\] = a\[2\] + b\[2\]
+ /// res\[3\] = a\[3\] + b\[3\]
+ ///
+ /// and the GE bits of the APSR are set.
+ #[inline]
+ #[cfg_attr(test, assert_instr(sadd8))]
+ pub unsafe fn __sadd8(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_sadd8, a, b)
+ }
+ 
+ /// Dual 16-bit Signed Multiply with Addition of products
+ /// and 32-bit accumulation.
+ ///
+ /// Returns the 16-bit signed equivalent of
+ /// res = a\[0\] * b\[0\] + a\[1\] * b\[1\] + c
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlad))]
+ pub unsafe fn __smlad(a: int16x2_t, b: int16x2_t, c: i32) -> i32 {
+     arm_smlad(transmute(a), transmute(b), c)
+ }
+ 
+ /// Dual 16-bit Signed Multiply with Subtraction  of products
+ /// and 32-bit accumulation and overflow detection.
+ ///
+ /// Returns the 16-bit signed equivalent of
+ /// res = a\[0\] * b\[0\] - a\[1\] * b\[1\] + c
+ #[inline]
+ #[cfg_attr(test, assert_instr(smlsd))]
+ pub unsafe fn __smlsd(a: int16x2_t, b: int16x2_t, c: i32) -> i32 {
+     arm_smlsd(transmute(a), transmute(b), c)
+ }
+ 
+ /// Returns the 16-bit signed equivalent of
+ ///
+ /// res\[0\] = a\[0\] - b\[1\]
+ /// res\[1\] = a\[1\] + b\[0\]
+ ///
+ /// and the GE bits of the APSR are set.
+ #[inline]
+ #[cfg_attr(test, assert_instr(sasx))]
+ pub unsafe fn __sasx(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_sasx, a, b)
+ }
+ 
+ /// Select bytes from each operand according to APSR GE flags
+ ///
+ /// Returns the equivalent of
+ ///
+ /// res\[0\] = GE\[0\] ? a\[0\] : b\[0\]
+ /// res\[1\] = GE\[1\] ? a\[1\] : b\[1\]
+ /// res\[2\] = GE\[2\] ? a\[2\] : b\[2\]
+ /// res\[3\] = GE\[3\] ? a\[3\] : b\[3\]
+ ///
+ /// where GE are bits of APSR
+ #[inline]
+ #[cfg_attr(test, assert_instr(sel))]
+ pub unsafe fn __sel(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_sel, a, b)
+ }
+ 
+ /// Signed halving parallel byte-wise addition.
+ ///
+ /// Returns the 8-bit signed equivalent of
+ ///
+ /// res\[0\] = (a\[0\] + b\[0\]) / 2
+ /// res\[1\] = (a\[1\] + b\[1\]) / 2
+ /// res\[2\] = (a\[2\] + b\[2\]) / 2
+ /// res\[3\] = (a\[3\] + b\[3\]) / 2
+ #[inline]
+ #[cfg_attr(test, assert_instr(shadd8))]
+ pub unsafe fn __shadd8(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_shadd8, a, b)
+ }
+ 
+ /// Signed halving parallel halfword-wise addition.
+ ///
+ /// Returns the 16-bit signed equivalent of
+ ///
+ /// res\[0\] = (a\[0\] + b\[0\]) / 2
+ /// res\[1\] = (a\[1\] + b\[1\]) / 2
+ #[inline]
+ #[cfg_attr(test, assert_instr(shadd16))]
+ pub unsafe fn __shadd16(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_shadd16, a, b)
+ }
+ 
+ /// Signed halving parallel byte-wise subtraction.
+ ///
+ /// Returns the 8-bit signed equivalent of
+ ///
+ /// res\[0\] = (a\[0\] - b\[0\]) / 2
+ /// res\[1\] = (a\[1\] - b\[1\]) / 2
+ /// res\[2\] = (a\[2\] - b\[2\]) / 2
+ /// res\[3\] = (a\[3\] - b\[3\]) / 2
+ #[inline]
+ #[cfg_attr(test, assert_instr(shsub8))]
+ pub unsafe fn __shsub8(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_shsub8, a, b)
+ }
+ 
+ /// Inserts a `USUB8` instruction.
+ ///
+ /// Returns the 8-bit unsigned equivalent of
+ ///
+ /// res\[0\] = a\[0\] - a\[0\]
+ /// res\[1\] = a\[1\] - a\[1\]
+ /// res\[2\] = a\[2\] - a\[2\]
+ /// res\[3\] = a\[3\] - a\[3\]
+ ///
+ /// where \[0\] is the lower 8 bits and \[3\] is the upper 8 bits.
+ /// The GE bits of the APSR are set.
+ #[inline]
+ #[cfg_attr(test, assert_instr(usub8))]
+ pub unsafe fn __usub8(a: uint8x4_t, b: uint8x4_t) -> uint8x4_t {
+     dsp_call!(arm_usub8, a, b)
+ }
+ 
+ /// Inserts a `SSUB8` instruction.
+ ///
+ /// Returns the 8-bit signed equivalent of
+ ///
+ /// res\[0\] = a\[0\] - a\[0\]
+ /// res\[1\] = a\[1\] - a\[1\]
+ /// res\[2\] = a\[2\] - a\[2\]
+ /// res\[3\] = a\[3\] - a\[3\]
+ ///
+ /// where \[0\] is the lower 8 bits and \[3\] is the upper 8 bits.
+ /// The GE bits of the APSR are set.
+ #[inline]
+ #[cfg_attr(test, assert_instr(ssub8))]
+ pub unsafe fn __ssub8(a: int8x4_t, b: int8x4_t) -> int8x4_t {
+     dsp_call!(arm_ssub8, a, b)
+ }
+ 
+ /// Signed halving parallel halfword-wise subtraction.
+ ///
+ /// Returns the 16-bit signed equivalent of
+ ///
+ /// res\[0\] = (a\[0\] - b\[0\]) / 2
+ /// res\[1\] = (a\[1\] - b\[1\]) / 2
+ #[inline]
+ #[cfg_attr(test, assert_instr(shsub16))]
+ pub unsafe fn __shsub16(a: int16x2_t, b: int16x2_t) -> int16x2_t {
+     dsp_call!(arm_shsub16, a, b)
+ }
+ 
+ /// Signed Dual Multiply Add.
+ ///
+ /// Returns the equivalent of
+ ///
+ /// res = a\[0\] * b\[0\] + a\[1\] * b\[1\]
+ ///
+ /// and sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smuad))]
+ pub unsafe fn __smuad(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smuad(transmute(a), transmute(b))
+ }
+ 
+ /// Signed Dual Multiply Add Reversed.
+ ///
+ /// Returns the equivalent of
+ ///
+ /// res = a\[0\] * b\[1\] + a\[1\] * b\[0\]
+ ///
+ /// and sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smuadx))]
+ pub unsafe fn __smuadx(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smuadx(transmute(a), transmute(b))
+ }
+ 
+ /// Signed Dual Multiply Subtract.
+ ///
+ /// Returns the equivalent of
+ ///
+ /// res = a\[0\] * b\[0\] - a\[1\] * b\[1\]
+ ///
+ /// and sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smusd))]
+ pub unsafe fn __smusd(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smusd(transmute(a), transmute(b))
+ }
+ 
+ /// Signed Dual Multiply Subtract Reversed.
+ ///
+ /// Returns the equivalent of
+ ///
+ /// res = a\[0\] * b\[1\] - a\[1\] * b\[0\]
+ ///
+ /// and sets the Q flag if overflow occurs on the addition.
+ #[inline]
+ #[cfg_attr(test, assert_instr(smusdx))]
+ pub unsafe fn __smusdx(a: int16x2_t, b: int16x2_t) -> i32 {
+     arm_smusdx(transmute(a), transmute(b))
+ }
+ 
+ /// Sum of 8-bit absolute differences.
+ ///
+ /// Returns the 8-bit unsigned equivalent of
+ ///
+ /// res = abs(a\[0\] - b\[0\]) + abs(a\[1\] - b\[1\]) +\
+ ///          (a\[2\] - b\[2\]) + (a\[3\] - b\[3\])
+ #[inline]
+ #[cfg_attr(test, assert_instr(usad8))]
+ pub unsafe fn __usad8(a: int8x4_t, b: int8x4_t) -> u32 {
+     arm_usad8(transmute(a), transmute(b))
+ }
+ 
+ /// Sum of 8-bit absolute differences and constant.
+ ///
+ /// Returns the 8-bit unsigned equivalent of
+ ///
+ /// res = abs(a\[0\] - b\[0\]) + abs(a\[1\] - b\[1\]) +\
+ ///          (a\[2\] - b\[2\]) + (a\[3\] - b\[3\]) + c
+ #[inline]
+ #[cfg_attr(test, assert_instr(usad8))]
+ pub unsafe fn __usada8(a: int8x4_t, b: int8x4_t, c: u32) -> u32 {
+     __usad8(a, b) + c
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::simd::{i16x2, i8x4, u8x4};
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ 
+     #[test]
+     fn qadd8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, i8::MAX);
+             let b = i8x4::new(2, -1, 0, 1);
+             let c = i8x4::new(3, 1, 3, i8::MAX);
+             let r: i8x4 = dsp_call!(super::__qadd8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn qsub8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, i8::MIN);
+             let b = i8x4::new(2, -1, 0, 1);
+             let c = i8x4::new(-1, 3, 3, i8::MIN);
+             let r: i8x4 = dsp_call!(super::__qsub8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn qadd16() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(2, -1);
+             let c = i16x2::new(3, 1);
+             let r: i16x2 = dsp_call!(super::__qadd16, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn qsub16() {
+         unsafe {
+             let a = i16x2::new(10, 20);
+             let b = i16x2::new(20, -10);
+             let c = i16x2::new(-10, 30);
+             let r: i16x2 = dsp_call!(super::__qsub16, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn qasx() {
+         unsafe {
+             let a = i16x2::new(1, i16::MAX);
+             let b = i16x2::new(2, 2);
+             let c = i16x2::new(-1, i16::MAX);
+             let r: i16x2 = dsp_call!(super::__qasx, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn qsax() {
+         unsafe {
+             let a = i16x2::new(1, i16::MAX);
+             let b = i16x2::new(2, 2);
+             let c = i16x2::new(3, i16::MAX - 2);
+             let r: i16x2 = dsp_call!(super::__qsax, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn sadd16() {
+         unsafe {
+             let a = i16x2::new(1, i16::MAX);
+             let b = i16x2::new(2, 2);
+             let c = i16x2::new(3, -i16::MAX);
+             let r: i16x2 = dsp_call!(super::__sadd16, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn sadd8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, i8::MAX);
+             let b = i8x4::new(4, 3, 2, 2);
+             let c = i8x4::new(5, 5, 5, -i8::MAX);
+             let r: i8x4 = dsp_call!(super::__sadd8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn sasx() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(2, 1);
+             let c = i16x2::new(0, 4);
+             let r: i16x2 = dsp_call!(super::__sasx, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn smlad() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(3, 4);
+             let r = super::__smlad(transmute(a), transmute(b), 10);
+             assert_eq!(r, (1 * 3) + (2 * 4) + 10);
+         }
+     }
+ 
+     #[test]
+     fn smlsd() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(3, 4);
+             let r = super::__smlsd(transmute(a), transmute(b), 10);
+             assert_eq!(r, ((1 * 3) - (2 * 4)) + 10);
+         }
+     }
+ 
+     #[test]
+     fn sel() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, i8::MAX);
+             let b = i8x4::new(4, 3, 2, 2);
+             // call sadd8() to set GE bits
+             super::__sadd8(transmute(a), transmute(b));
+             let c = i8x4::new(1, 2, 3, i8::MAX);
+             let r: i8x4 = dsp_call!(super::__sel, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn shadd8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, 4);
+             let b = i8x4::new(5, 4, 3, 2);
+             let c = i8x4::new(3, 3, 3, 3);
+             let r: i8x4 = dsp_call!(super::__shadd8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn shadd16() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(5, 4);
+             let c = i16x2::new(3, 3);
+             let r: i16x2 = dsp_call!(super::__shadd16, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn shsub8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, 4);
+             let b = i8x4::new(5, 4, 3, 2);
+             let c = i8x4::new(-2, -1, 0, 1);
+             let r: i8x4 = dsp_call!(super::__shsub8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn ssub8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, 4);
+             let b = i8x4::new(5, 4, 3, 2);
+             let c = i8x4::new(-4, -2, 0, 2);
+             let r: i8x4 = dsp_call!(super::__ssub8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn usub8() {
+         unsafe {
+             let a = u8x4::new(1, 2, 3, 4);
+             let b = u8x4::new(5, 4, 3, 2);
+             let c = u8x4::new(252, 254, 0, 2);
+             let r: u8x4 = dsp_call!(super::__usub8, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn shsub16() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(5, 4);
+             let c = i16x2::new(-2, -1);
+             let r: i16x2 = dsp_call!(super::__shsub16, a, b);
+             assert_eq!(r, c);
+         }
+     }
+ 
+     #[test]
+     fn smuad() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(5, 4);
+             let r = super::__smuad(transmute(a), transmute(b));
+             assert_eq!(r, 13);
+         }
+     }
+ 
+     #[test]
+     fn smuadx() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(5, 4);
+             let r = super::__smuadx(transmute(a), transmute(b));
+             assert_eq!(r, 14);
+         }
+     }
+ 
+     #[test]
+     fn smusd() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(5, 4);
+             let r = super::__smusd(transmute(a), transmute(b));
+             assert_eq!(r, -3);
+         }
+     }
+ 
+     #[test]
+     fn smusdx() {
+         unsafe {
+             let a = i16x2::new(1, 2);
+             let b = i16x2::new(5, 4);
+             let r = super::__smusdx(transmute(a), transmute(b));
+             assert_eq!(r, -6);
+         }
+     }
+ 
+     #[test]
+     fn usad8() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, 4);
+             let b = i8x4::new(4, 3, 2, 1);
+             let r = super::__usad8(transmute(a), transmute(b));
+             assert_eq!(r, 8);
+         }
+     }
+ 
+     #[test]
+     fn usad8a() {
+         unsafe {
+             let a = i8x4::new(1, 2, 3, 4);
+             let b = i8x4::new(4, 3, 2, 1);
+             let c = 10;
+             let r = super::__usada8(transmute(a), transmute(b), c);
+             assert_eq!(r, 8 + c);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,68 ----
+ //! ARM compiler specific intrinsics
+ //!
+ //! # References
+ //!
+ //! - [ARM Compiler v 6.10 - armclang Reference Guide][arm_comp_ref]
+ //!
+ //! [arm_comp_ref]: https://developer.arm.com/docs/100067/0610
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Inserts a breakpoint instruction.
+ ///
+ /// `val` is a compile-time constant integer in range `[0, 255]`.
+ ///
+ /// The breakpoint instruction inserted is:
+ ///
+ /// * `BKPT` when compiling as T32,
+ /// * `BRK` when compiling as A32 or A64.
+ ///
+ /// # Safety
+ ///
+ /// If `val` is out-of-range the behavior is **undefined**.
+ ///
+ /// # Note
+ ///
+ /// [ARM's documentation][arm_docs] defines that `__breakpoint` accepts the
+ /// following values for `val`:
+ ///
+ /// - `0...65535` when compiling as A32 or A64,
+ /// - `0...255` when compiling as T32.
+ ///
+ /// The current implementation only accepts values in range `[0, 255]` - if the
+ /// value is out-of-range the behavior is **undefined**.
+ ///
+ /// [arm_docs]: https://developer.arm.com/docs/100067/latest/compiler-specific-intrinsics/__breakpoint-intrinsic
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(bkpt, val = 0))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(brk, val = 0))]
+ #[inline(always)]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __breakpoint(val: i32) {
+     // Ensure that this compiles correctly on non-arm architectures, so libstd
+     // doc builds work. The proper macro will shadow this definition below.
+     #[allow(unused_macros)]
+     macro_rules! call {
+         ($e:expr) => {
+             ()
+         };
+     }
+ 
+     #[cfg(target_arch = "arm")]
+     macro_rules! call {
+         ($imm8:expr) => {
+             llvm_asm!(concat!("BKPT ", stringify!($imm8)) : : : : "volatile")
+         }
+     }
+ 
+     #[cfg(target_arch = "aarch64")]
+     macro_rules! call {
+         ($imm8:expr) => {
+             llvm_asm!(concat!("BRK ", stringify!($imm8)) : : : : "volatile")
+         }
+     }
+ 
+     // We can't `panic!` inside this intrinsic, so we can't really validate the
+     // arguments here. If `val` is out-of-range this macro uses `val == 255`:
+     constify_imm8!(val, call);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,121 ----
+ extern "C" {
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32b")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
+     fn crc32b_(crc: u32, data: u32) -> u32;
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32h")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
+     fn crc32h_(crc: u32, data: u32) -> u32;
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32w")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
+     fn crc32w_(crc: u32, data: u32) -> u32;
+ 
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cb")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
+     fn crc32cb_(crc: u32, data: u32) -> u32;
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32ch")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
+     fn crc32ch_(crc: u32, data: u32) -> u32;
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cw")]
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
+     fn crc32cw_(crc: u32, data: u32) -> u32;
+ }
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// CRC32 single round checksum for bytes (8 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+ #[cfg_attr(test, assert_instr(crc32b))]
+ pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
+     crc32b_(crc, data as u32)
+ }
+ 
+ /// CRC32 single round checksum for half words (16 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+ #[cfg_attr(test, assert_instr(crc32h))]
+ pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
+     crc32h_(crc, data as u32)
+ }
+ 
+ /// CRC32 single round checksum for words (32 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+ #[cfg_attr(test, assert_instr(crc32w))]
+ pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
+     crc32w_(crc, data)
+ }
+ 
+ /// CRC32-C single round checksum for bytes (8 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+ #[cfg_attr(test, assert_instr(crc32cb))]
+ pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
+     crc32cb_(crc, data as u32)
+ }
+ 
+ /// CRC32-C single round checksum for half words (16 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+ #[cfg_attr(test, assert_instr(crc32ch))]
+ pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
+     crc32ch_(crc, data as u32)
+ }
+ 
+ /// CRC32-C single round checksum for words (32 bits).
+ #[inline]
+ #[target_feature(enable = "crc")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+ #[cfg_attr(test, assert_instr(crc32cw))]
+ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
+     crc32cw_(crc, data)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::{arm::*, simd::*};
+     use std::mem;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32b() {
+         assert_eq!(__crc32b(0, 0), 0);
+         assert_eq!(__crc32b(0, 255), 755167117);
+     }
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32h() {
+         assert_eq!(__crc32h(0, 0), 0);
+         assert_eq!(__crc32h(0, 16384), 1994146192);
+     }
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32w() {
+         assert_eq!(__crc32w(0, 0), 0);
+         assert_eq!(__crc32w(0, 4294967295), 3736805603);
+     }
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32cb() {
+         assert_eq!(__crc32cb(0, 0), 0);
+         assert_eq!(__crc32cb(0, 255), 2910671697);
+     }
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32ch() {
+         assert_eq!(__crc32ch(0, 0), 0);
+         assert_eq!(__crc32ch(0, 16384), 1098587580);
+     }
+ 
+     #[simd_test(enable = "crc")]
+     unsafe fn test_crc32cw() {
+         assert_eq!(__crc32cw(0, 0), 0);
+         assert_eq!(__crc32cw(0, 4294967295), 3080238136);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,47 ----
+ //! ARM intrinsics.
+ //!
+ //! The reference for NEON is [ARM's NEON Intrinsics Reference][arm_ref]. The
+ //! [ARM's NEON Intrinsics Online Database][arm_dat] is also useful.
+ //!
+ //! [arm_ref]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
+ //! [arm_dat]: https://developer.arm.com/technologies/neon/intrinsics
+ #![allow(non_camel_case_types)]
+ 
+ mod armclang;
+ 
+ pub use self::armclang::*;
+ 
+ mod v6;
+ pub use self::v6::*;
+ 
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+ mod v7;
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+ pub use self::v7::*;
+ 
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+ mod neon;
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+ pub use self::neon::*;
+ 
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+ mod crc;
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+ pub use self::crc::*;
+ 
+ pub use crate::core_arch::acle::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Generates the trap instruction `UDF`
+ #[cfg(target_arch = "arm")]
+ #[cfg_attr(test, assert_instr(udf))]
+ #[inline]
+ pub unsafe fn udf() -> ! {
+     crate::intrinsics::abort()
+ }
+ 
+ #[cfg(test)]
+ #[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+ pub(crate) mod test_support;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,4537 ----
+ // This code is automatically generated. DO NOT MODIFY.
+ //
+ // Instead, modify `crates/stdarch-gen/neon.spec` and run the following command to re-generate this file:
+ //
+ // ```
+ // OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec
+ // ```
+ use super::*;
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise and
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(and))]
+ pub unsafe fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_and(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(orr))]
+ pub unsafe fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_or(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise exclusive or (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(eor))]
+ pub unsafe fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_xor(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare bitwise Equal (vector)
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmeq))]
+ pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Floating-point compare equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmeq))]
+ pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Floating-point compare equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmeq))]
+ pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
+     simd_eq(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare unsigned highe
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Floating-point compare greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmgt))]
+ pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Floating-point compare greater than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmgt))]
+ pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
+     simd_gt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmgt))]
+ pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare unsigned less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhi))]
+ pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Floating-point compare less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmgt))]
+ pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Floating-point compare less than
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmgt))]
+ pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
+     simd_lt(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare unsigned less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_le(a, b)
+ }
+ 
+ /// Floating-point compare less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmge))]
+ pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
+     simd_le(a, b)
+ }
+ 
+ /// Floating-point compare less than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmge))]
+ pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
+     simd_le(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare signed greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmge))]
+ pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Compare unsigned greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(cmhs))]
+ pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Floating-point compare greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmge))]
+ pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Floating-point compare greater than or equal
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fcmge))]
+ pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
+     simd_ge(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqsub))]
+ pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubu.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.v8i8")]
+         fn vqsub_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     }
+ vqsub_u8_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqsub))]
+ pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubu.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.v16i8")]
+         fn vqsubq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     }
+ vqsubq_u8_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqsub))]
+ pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubu.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.v4i16")]
+         fn vqsub_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     }
+ vqsub_u16_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqsub))]
+ pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubu.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.v8i16")]
+         fn vqsubq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     }
+ vqsubq_u16_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqsub))]
+ pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubu.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.v2i32")]
+         fn vqsub_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     }
+ vqsub_u32_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqsub))]
+ pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubu.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.v4i32")]
+         fn vqsubq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     }
+ vqsubq_u32_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqsub))]
+ pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubs.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.v8i8")]
+         fn vqsub_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     }
+ vqsub_s8_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqsub))]
+ pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubs.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.v16i8")]
+         fn vqsubq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     }
+ vqsubq_s8_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqsub))]
+ pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubs.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.v4i16")]
+         fn vqsub_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     }
+ vqsub_s16_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqsub))]
+ pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubs.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.v8i16")]
+         fn vqsubq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     }
+ vqsubq_s16_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqsub))]
+ pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubs.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.v2i32")]
+         fn vqsub_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     }
+ vqsub_s32_(a, b)
+ }
+ 
+ /// Saturating subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqsub))]
+ pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqsubs.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.v4i32")]
+         fn vqsubq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     }
+ vqsubq_s32_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhadd))]
+ pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhadd.v8i8")]
+         fn vhadd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     }
+ vhadd_u8_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhadd))]
+ pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhadd.v16i8")]
+         fn vhaddq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     }
+ vhaddq_u8_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhadd))]
+ pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhadd.v4i16")]
+         fn vhadd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     }
+ vhadd_u16_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhadd))]
+ pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhadd.v8i16")]
+         fn vhaddq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     }
+ vhaddq_u16_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhadd))]
+ pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhadd.v2i32")]
+         fn vhadd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     }
+ vhadd_u32_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhadd))]
+ pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhadd.v4i32")]
+         fn vhaddq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     }
+ vhaddq_u32_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shadd))]
+ pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shadd.v8i8")]
+         fn vhadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     }
+ vhadd_s8_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shadd))]
+ pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shadd.v16i8")]
+         fn vhaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     }
+ vhaddq_s8_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shadd))]
+ pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shadd.v4i16")]
+         fn vhadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     }
+ vhadd_s16_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shadd))]
+ pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shadd.v8i16")]
+         fn vhaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     }
+ vhaddq_s16_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shadd))]
+ pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shadd.v2i32")]
+         fn vhadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     }
+ vhadd_s32_(a, b)
+ }
+ 
+ /// Halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shadd))]
+ pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shadd.v4i32")]
+         fn vhaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     }
+ vhaddq_s32_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(urhadd))]
+ pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urhadd.v8i8")]
+         fn vrhadd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     }
+ vrhadd_u8_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(urhadd))]
+ pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urhadd.v16i8")]
+         fn vrhaddq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     }
+ vrhaddq_u8_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(urhadd))]
+ pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urhadd.v4i16")]
+         fn vrhadd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     }
+ vrhadd_u16_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(urhadd))]
+ pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urhadd.v8i16")]
+         fn vrhaddq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     }
+ vrhaddq_u16_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(urhadd))]
+ pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urhadd.v2i32")]
+         fn vrhadd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     }
+ vrhadd_u32_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(urhadd))]
+ pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urhadd.v4i32")]
+         fn vrhaddq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     }
+ vrhaddq_u32_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(srhadd))]
+ pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srhadd.v8i8")]
+         fn vrhadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     }
+ vrhadd_s8_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(srhadd))]
+ pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srhadd.v16i8")]
+         fn vrhaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     }
+ vrhaddq_s8_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(srhadd))]
+ pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srhadd.v4i16")]
+         fn vrhadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     }
+ vrhadd_s16_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(srhadd))]
+ pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srhadd.v8i16")]
+         fn vrhaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     }
+ vrhaddq_s16_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(srhadd))]
+ pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srhadd.v2i32")]
+         fn vrhadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     }
+ vrhadd_s32_(a, b)
+ }
+ 
+ /// Rounding halving add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(srhadd))]
+ pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srhadd.v4i32")]
+         fn vrhaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     }
+ vrhaddq_s32_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqadd))]
+ pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqaddu.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.v8i8")]
+         fn vqadd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     }
+ vqadd_u8_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqadd))]
+ pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqaddu.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.v16i8")]
+         fn vqaddq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     }
+ vqaddq_u8_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqadd))]
+ pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqaddu.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.v4i16")]
+         fn vqadd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     }
+ vqadd_u16_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqadd))]
+ pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqaddu.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.v8i16")]
+         fn vqaddq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     }
+ vqaddq_u16_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqadd))]
+ pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqaddu.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.v2i32")]
+         fn vqadd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     }
+ vqadd_u32_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqadd))]
+ pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqaddu.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.v4i32")]
+         fn vqaddq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     }
+ vqaddq_u32_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqadd))]
+ pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqadds.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.v8i8")]
+         fn vqadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     }
+ vqadd_s8_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqadd))]
+ pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqadds.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.v16i8")]
+         fn vqaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     }
+ vqaddq_s8_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqadd))]
+ pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqadds.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.v4i16")]
+         fn vqadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     }
+ vqadd_s16_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqadd))]
+ pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqadds.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.v8i16")]
+         fn vqaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     }
+ vqaddq_s16_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqadd))]
+ pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqadds.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.v2i32")]
+         fn vqadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     }
+ vqadd_s32_(a, b)
+ }
+ 
+ /// Saturating add
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sqadd))]
+ pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqadds.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.v4i32")]
+         fn vqaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     }
+ vqaddq_s32_(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+ pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmul))]
+ pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiply
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmul))]
+ pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     simd_mul(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+ pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fsub))]
+ pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fsub))]
+ pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     simd_sub(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhsub))]
+ pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhsub.v8i8")]
+         fn vhsub_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     }
+ vhsub_u8_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhsub))]
+ pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhsub.v16i8")]
+         fn vhsubq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
+     }
+ vhsubq_u8_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhsub))]
+ pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhsub.v4i16")]
+         fn vhsub_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     }
+ vhsub_u16_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhsub))]
+ pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhsub.v8i16")]
+         fn vhsubq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
+     }
+ vhsubq_u16_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhsub))]
+ pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhsub.v2i32")]
+         fn vhsub_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     }
+ vhsub_u32_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uhsub))]
+ pub unsafe fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uhsub.v4i32")]
+         fn vhsubq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
+     }
+ vhsubq_u32_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shsub))]
+ pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shsub.v8i8")]
+         fn vhsub_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     }
+ vhsub_s8_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shsub))]
+ pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shsub.v16i8")]
+         fn vhsubq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+     }
+ vhsubq_s8_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shsub))]
+ pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shsub.v4i16")]
+         fn vhsub_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     }
+ vhsub_s16_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shsub))]
+ pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shsub.v8i16")]
+         fn vhsubq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t;
+     }
+ vhsubq_s16_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shsub))]
+ pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shsub.v2i32")]
+         fn vhsub_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     }
+ vhsub_s32_(a, b)
+ }
+ 
+ /// Signed halving subtract
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shsub))]
+ pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     #[allow(improper_ctypes)]
+     extern "C" {
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.shsub.v4i32")]
+         fn vhsubq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t;
+     }
+ vhsubq_s32_(a, b)
+ }
+ 
+ #[cfg(test)]
+ #[allow(overflowing_literals)]
+ mod test {
+     use super::*;
+     use crate::core_arch::simd::*;
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s8() {
+         let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i8x8 = i8x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F);
+         let e: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: i8x8 = transmute(vand_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let r: i8x8 = transmute(vand_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s8() {
+         let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00);
+         let b: i8x16 = i8x16::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F);
+         let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00);
+         let r: i8x16 = transmute(vandq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00);
+         let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let r: i8x16 = transmute(vandq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s16() {
+         let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i16x4 = i16x4::new(0x0F, 0x0F, 0x0F, 0x0F);
+         let e: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: i16x4 = transmute(vand_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00);
+         let r: i16x4 = transmute(vand_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s16() {
+         let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i16x8 = i16x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F);
+         let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: i16x8 = transmute(vandq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let r: i16x8 = transmute(vandq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s32() {
+         let a: i32x2 = i32x2::new(0x00, 0x01);
+         let b: i32x2 = i32x2::new(0x0F, 0x0F);
+         let e: i32x2 = i32x2::new(0x00, 0x01);
+         let r: i32x2 = transmute(vand_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i32x2 = i32x2::new(0x00, 0x01);
+         let b: i32x2 = i32x2::new(0x00, 0x00);
+         let e: i32x2 = i32x2::new(0x00, 0x00);
+         let r: i32x2 = transmute(vand_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s32() {
+         let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i32x4 = i32x4::new(0x0F, 0x0F, 0x0F, 0x0F);
+         let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: i32x4 = transmute(vandq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00);
+         let r: i32x4 = transmute(vandq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u8() {
+         let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u8x8 = u8x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F);
+         let e: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: u8x8 = transmute(vand_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let r: u8x8 = transmute(vand_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u8() {
+         let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00);
+         let b: u8x16 = u8x16::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F);
+         let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00);
+         let r: u8x16 = transmute(vandq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00);
+         let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let r: u8x16 = transmute(vandq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u16() {
+         let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u16x4 = u16x4::new(0x0F, 0x0F, 0x0F, 0x0F);
+         let e: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: u16x4 = transmute(vand_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00);
+         let r: u16x4 = transmute(vand_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u16() {
+         let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u16x8 = u16x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F);
+         let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: u16x8 = transmute(vandq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let r: u16x8 = transmute(vandq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u32() {
+         let a: u32x2 = u32x2::new(0x00, 0x01);
+         let b: u32x2 = u32x2::new(0x0F, 0x0F);
+         let e: u32x2 = u32x2::new(0x00, 0x01);
+         let r: u32x2 = transmute(vand_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u32x2 = u32x2::new(0x00, 0x01);
+         let b: u32x2 = u32x2::new(0x00, 0x00);
+         let e: u32x2 = u32x2::new(0x00, 0x00);
+         let r: u32x2 = transmute(vand_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u32() {
+         let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u32x4 = u32x4::new(0x0F, 0x0F, 0x0F, 0x0F);
+         let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: u32x4 = transmute(vandq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00);
+         let r: u32x4 = transmute(vandq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s64() {
+         let a: i64x1 = i64x1::new(0x00);
+         let b: i64x1 = i64x1::new(0x0F);
+         let e: i64x1 = i64x1::new(0x00);
+         let r: i64x1 = transmute(vand_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i64x1 = i64x1::new(0x00);
+         let b: i64x1 = i64x1::new(0x00);
+         let e: i64x1 = i64x1::new(0x00);
+         let r: i64x1 = transmute(vand_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s64() {
+         let a: i64x2 = i64x2::new(0x00, 0x01);
+         let b: i64x2 = i64x2::new(0x0F, 0x0F);
+         let e: i64x2 = i64x2::new(0x00, 0x01);
+         let r: i64x2 = transmute(vandq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i64x2 = i64x2::new(0x00, 0x01);
+         let b: i64x2 = i64x2::new(0x00, 0x00);
+         let e: i64x2 = i64x2::new(0x00, 0x00);
+         let r: i64x2 = transmute(vandq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u64() {
+         let a: u64x1 = u64x1::new(0x00);
+         let b: u64x1 = u64x1::new(0x0F);
+         let e: u64x1 = u64x1::new(0x00);
+         let r: u64x1 = transmute(vand_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u64x1 = u64x1::new(0x00);
+         let b: u64x1 = u64x1::new(0x00);
+         let e: u64x1 = u64x1::new(0x00);
+         let r: u64x1 = transmute(vand_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u64() {
+         let a: u64x2 = u64x2::new(0x00, 0x01);
+         let b: u64x2 = u64x2::new(0x0F, 0x0F);
+         let e: u64x2 = u64x2::new(0x00, 0x01);
+         let r: u64x2 = transmute(vandq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u64x2 = u64x2::new(0x00, 0x01);
+         let b: u64x2 = u64x2::new(0x00, 0x00);
+         let e: u64x2 = u64x2::new(0x00, 0x00);
+         let r: u64x2 = transmute(vandq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s8() {
+         let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: i8x8 = transmute(vorr_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s8() {
+         let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let r: i8x16 = transmute(vorrq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s16() {
+         let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: i16x4 = transmute(vorr_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s16() {
+         let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: i16x8 = transmute(vorrq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s32() {
+         let a: i32x2 = i32x2::new(0x00, 0x01);
+         let b: i32x2 = i32x2::new(0x00, 0x00);
+         let e: i32x2 = i32x2::new(0x00, 0x01);
+         let r: i32x2 = transmute(vorr_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s32() {
+         let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: i32x4 = transmute(vorrq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u8() {
+         let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: u8x8 = transmute(vorr_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u8() {
+         let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let r: u8x16 = transmute(vorrq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u16() {
+         let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: u16x4 = transmute(vorr_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u16() {
+         let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: u16x8 = transmute(vorrq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u32() {
+         let a: u32x2 = u32x2::new(0x00, 0x01);
+         let b: u32x2 = u32x2::new(0x00, 0x00);
+         let e: u32x2 = u32x2::new(0x00, 0x01);
+         let r: u32x2 = transmute(vorr_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u32() {
+         let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: u32x4 = transmute(vorrq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s64() {
+         let a: i64x1 = i64x1::new(0x00);
+         let b: i64x1 = i64x1::new(0x00);
+         let e: i64x1 = i64x1::new(0x00);
+         let r: i64x1 = transmute(vorr_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s64() {
+         let a: i64x2 = i64x2::new(0x00, 0x01);
+         let b: i64x2 = i64x2::new(0x00, 0x00);
+         let e: i64x2 = i64x2::new(0x00, 0x01);
+         let r: i64x2 = transmute(vorrq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u64() {
+         let a: u64x1 = u64x1::new(0x00);
+         let b: u64x1 = u64x1::new(0x00);
+         let e: u64x1 = u64x1::new(0x00);
+         let r: u64x1 = transmute(vorr_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u64() {
+         let a: u64x2 = u64x2::new(0x00, 0x01);
+         let b: u64x2 = u64x2::new(0x00, 0x00);
+         let e: u64x2 = u64x2::new(0x00, 0x01);
+         let r: u64x2 = transmute(vorrq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s8() {
+         let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: i8x8 = transmute(veor_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s8() {
+         let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let r: i8x16 = transmute(veorq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s16() {
+         let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: i16x4 = transmute(veor_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s16() {
+         let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: i16x8 = transmute(veorq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s32() {
+         let a: i32x2 = i32x2::new(0x00, 0x01);
+         let b: i32x2 = i32x2::new(0x00, 0x00);
+         let e: i32x2 = i32x2::new(0x00, 0x01);
+         let r: i32x2 = transmute(veor_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s32() {
+         let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: i32x4 = transmute(veorq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u8() {
+         let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: u8x8 = transmute(veor_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u8() {
+         let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F);
+         let r: u8x16 = transmute(veorq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u16() {
+         let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: u16x4 = transmute(veor_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u16() {
+         let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+         let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let r: u16x8 = transmute(veorq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u32() {
+         let a: u32x2 = u32x2::new(0x00, 0x01);
+         let b: u32x2 = u32x2::new(0x00, 0x00);
+         let e: u32x2 = u32x2::new(0x00, 0x01);
+         let r: u32x2 = transmute(veor_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u32() {
+         let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00);
+         let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03);
+         let r: u32x4 = transmute(veorq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s64() {
+         let a: i64x1 = i64x1::new(0x00);
+         let b: i64x1 = i64x1::new(0x00);
+         let e: i64x1 = i64x1::new(0x00);
+         let r: i64x1 = transmute(veor_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s64() {
+         let a: i64x2 = i64x2::new(0x00, 0x01);
+         let b: i64x2 = i64x2::new(0x00, 0x00);
+         let e: i64x2 = i64x2::new(0x00, 0x01);
+         let r: i64x2 = transmute(veorq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u64() {
+         let a: u64x1 = u64x1::new(0x00);
+         let b: u64x1 = u64x1::new(0x00);
+         let e: u64x1 = u64x1::new(0x00);
+         let r: u64x1 = transmute(veor_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u64() {
+         let a: u64x2 = u64x2::new(0x00, 0x01);
+         let b: u64x2 = u64x2::new(0x00, 0x00);
+         let e: u64x2 = u64x2::new(0x00, 0x01);
+         let r: u64x2 = transmute(veorq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u8() {
+         let a: u8x8 = u8x8::new(0xFF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u8x8 = u8x8::new(0xFF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vceq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u8x8 = u8x8::new(0xFF, 0xFF, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u8x8 = u8x8::new(0xFF, 0, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08);
+         let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0);
+         let r: u8x8 = transmute(vceq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u8() {
+         let a: u8x16 = u8x16::new(0xFF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0);
+         let b: u8x16 = u8x16::new(0xFF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vceqq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u8x16 = u8x16::new(0xFF, 0xFF, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, 0);
+         let b: u8x16 = u8x16::new(0xFF, 0, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, 0xFF);
+         let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0);
+         let r: u8x16 = transmute(vceqq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u16() {
+         let a: u16x4 = u16x4::new(0xFF_FF, 0x01, 0x02, 0x03);
+         let b: u16x4 = u16x4::new(0xFF_FF, 0x01, 0x02, 0x03);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vceq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0x02, 0x03);
+         let b: u16x4 = u16x4::new(0xFF_FF, 0, 0x02, 0x04);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0);
+         let r: u16x4 = transmute(vceq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u16() {
+         let a: u16x8 = u16x8::new(0xFF_FF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u16x8 = u16x8::new(0xFF_FF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vceqq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: u16x8 = u16x8::new(0xFF_FF, 0, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0);
+         let r: u16x8 = transmute(vceqq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u32() {
+         let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0x01);
+         let b: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0x01);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vceq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let b: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0);
+         let r: u32x2 = transmute(vceq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u32() {
+         let a: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0x01, 0x02, 0x03);
+         let b: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0x01, 0x02, 0x03);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vceqq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0x02, 0x03);
+         let b: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0x02, 0x04);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF, 0);
+         let r: u32x4 = transmute(vceqq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s8() {
+         let a: i8x8 = i8x8::new(0x7F, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i8x8 = i8x8::new(0x7F, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vceq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i8x8 = i8x8::new(0x7F, 0x7F, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i8x8 = i8x8::new(0x7F, -128, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08);
+         let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0);
+         let r: u8x8 = transmute(vceq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s8() {
+         let a: i8x16 = i8x16::new(0x7F, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, -128);
+         let b: i8x16 = i8x16::new(0x7F, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, -128);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vceqq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i8x16 = i8x16::new(0x7F, 0x7F, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, -128);
+         let b: i8x16 = i8x16::new(0x7F, -128, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, 0x7F);
+         let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0);
+         let r: u8x16 = transmute(vceqq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s16() {
+         let a: i16x4 = i16x4::new(0x7F_FF, 0x01, 0x02, 0x03);
+         let b: i16x4 = i16x4::new(0x7F_FF, 0x01, 0x02, 0x03);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vceq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x02, 0x03);
+         let b: i16x4 = i16x4::new(0x7F_FF, -32768, 0x02, 0x04);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0);
+         let r: u16x4 = transmute(vceq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s16() {
+         let a: i16x8 = i16x8::new(0x7F_FF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i16x8 = i16x8::new(0x7F_FF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vceqq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07);
+         let b: i16x8 = i16x8::new(0x7F_FF, -32768, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0);
+         let r: u16x8 = transmute(vceqq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s32() {
+         let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x01);
+         let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x01);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vceq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF);
+         let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, -2147483648);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0);
+         let r: u32x2 = transmute(vceq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s32() {
+         let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x01, 0x02, 0x03);
+         let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x01, 0x02, 0x03);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vceqq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ 
+         let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x02, 0x03);
+         let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, -2147483648, 0x02, 0x04);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF, 0);
+         let r: u32x4 = transmute(vceqq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_f32() {
+         let a: f32x2 = f32x2::new(1.2, 3.4);
+         let b: f32x2 = f32x2::new(1.2, 3.4);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vceq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_f32() {
+         let a: f32x4 = f32x4::new(1.2, 3.4, 5.6, 7.8);
+         let b: f32x4 = f32x4::new(1.2, 3.4, 5.6, 7.8);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vceqq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s8() {
+         let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vcgt_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s8() {
+         let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcgtq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s16() {
+         let a: i16x4 = i16x4::new(1, 2, 3, 4);
+         let b: i16x4 = i16x4::new(0, 1, 2, 3);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vcgt_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s16() {
+         let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcgtq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s32() {
+         let a: i32x2 = i32x2::new(1, 2);
+         let b: i32x2 = i32x2::new(0, 1);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcgt_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s32() {
+         let a: i32x4 = i32x4::new(1, 2, 3, 4);
+         let b: i32x4 = i32x4::new(0, 1, 2, 3);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcgtq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u8() {
+         let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vcgt_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u8() {
+         let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcgtq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u16() {
+         let a: u16x4 = u16x4::new(1, 2, 3, 4);
+         let b: u16x4 = u16x4::new(0, 1, 2, 3);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vcgt_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u16() {
+         let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcgtq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u32() {
+         let a: u32x2 = u32x2::new(1, 2);
+         let b: u32x2 = u32x2::new(0, 1);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcgt_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u32() {
+         let a: u32x4 = u32x4::new(1, 2, 3, 4);
+         let b: u32x4 = u32x4::new(0, 1, 2, 3);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcgtq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_f32() {
+         let a: f32x2 = f32x2::new(1.2, 2.3);
+         let b: f32x2 = f32x2::new(0.1, 1.2);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcgt_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_f32() {
+         let a: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5);
+         let b: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcgtq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s8() {
+         let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vclt_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s8() {
+         let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcltq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s16() {
+         let a: i16x4 = i16x4::new(0, 1, 2, 3);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vclt_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s16() {
+         let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcltq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s32() {
+         let a: i32x2 = i32x2::new(0, 1);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vclt_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s32() {
+         let a: i32x4 = i32x4::new(0, 1, 2, 3);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcltq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u8() {
+         let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vclt_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u8() {
+         let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcltq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u16() {
+         let a: u16x4 = u16x4::new(0, 1, 2, 3);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vclt_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u16() {
+         let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcltq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u32() {
+         let a: u32x2 = u32x2::new(0, 1);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vclt_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u32() {
+         let a: u32x4 = u32x4::new(0, 1, 2, 3);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcltq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_f32() {
+         let a: f32x2 = f32x2::new(0.1, 1.2);
+         let b: f32x2 = f32x2::new(1.2, 2.3);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vclt_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_f32() {
+         let a: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4);
+         let b: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcltq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s8() {
+         let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vcle_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s8() {
+         let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcleq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s16() {
+         let a: i16x4 = i16x4::new(0, 1, 2, 3);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vcle_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s16() {
+         let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcleq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s32() {
+         let a: i32x2 = i32x2::new(0, 1);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcle_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s32() {
+         let a: i32x4 = i32x4::new(0, 1, 2, 3);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcleq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u8() {
+         let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vcle_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u8() {
+         let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcleq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u16() {
+         let a: u16x4 = u16x4::new(0, 1, 2, 3);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vcle_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u16() {
+         let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcleq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u32() {
+         let a: u32x2 = u32x2::new(0, 1);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcle_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u32() {
+         let a: u32x4 = u32x4::new(0, 1, 2, 3);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcleq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_f32() {
+         let a: f32x2 = f32x2::new(0.1, 1.2);
+         let b: f32x2 = f32x2::new(1.2, 2.3);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcle_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_f32() {
+         let a: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4);
+         let b: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcleq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s8() {
+         let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vcge_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s8() {
+         let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcgeq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s16() {
+         let a: i16x4 = i16x4::new(1, 2, 3, 4);
+         let b: i16x4 = i16x4::new(0, 1, 2, 3);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vcge_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s16() {
+         let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcgeq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s32() {
+         let a: i32x2 = i32x2::new(1, 2);
+         let b: i32x2 = i32x2::new(0, 1);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcge_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s32() {
+         let a: i32x4 = i32x4::new(1, 2, 3, 4);
+         let b: i32x4 = i32x4::new(0, 1, 2, 3);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcgeq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u8() {
+         let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x8 = transmute(vcge_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u8() {
+         let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
+         let r: u8x16 = transmute(vcgeq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u16() {
+         let a: u16x4 = u16x4::new(1, 2, 3, 4);
+         let b: u16x4 = u16x4::new(0, 1, 2, 3);
+         let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x4 = transmute(vcge_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u16() {
+         let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF);
+         let r: u16x8 = transmute(vcgeq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u32() {
+         let a: u32x2 = u32x2::new(1, 2);
+         let b: u32x2 = u32x2::new(0, 1);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcge_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u32() {
+         let a: u32x4 = u32x4::new(1, 2, 3, 4);
+         let b: u32x4 = u32x4::new(0, 1, 2, 3);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcgeq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_f32() {
+         let a: f32x2 = f32x2::new(1.2, 2.3);
+         let b: f32x2 = f32x2::new(0.1, 1.2);
+         let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x2 = transmute(vcge_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_f32() {
+         let a: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5);
+         let b: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4);
+         let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF);
+         let r: u32x4 = transmute(vcgeq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_u8() {
+         let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(41, 40, 39, 38, 37, 36, 35, 34);
+         let r: u8x8 = transmute(vqsub_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_u8() {
+         let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26);
+         let r: u8x16 = transmute(vqsubq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_u16() {
+         let a: u16x4 = u16x4::new(42, 42, 42, 42);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(41, 40, 39, 38);
+         let r: u16x4 = transmute(vqsub_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_u16() {
+         let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(41, 40, 39, 38, 37, 36, 35, 34);
+         let r: u16x8 = transmute(vqsubq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_u32() {
+         let a: u32x2 = u32x2::new(42, 42);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(41, 40);
+         let r: u32x2 = transmute(vqsub_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_u32() {
+         let a: u32x4 = u32x4::new(42, 42, 42, 42);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(41, 40, 39, 38);
+         let r: u32x4 = transmute(vqsubq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_s8() {
+         let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i8x8 = i8x8::new(41, 40, 39, 38, 37, 36, 35, 34);
+         let r: i8x8 = transmute(vqsub_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_s8() {
+         let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: i8x16 = i8x16::new(41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26);
+         let r: i8x16 = transmute(vqsubq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_s16() {
+         let a: i16x4 = i16x4::new(42, 42, 42, 42);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: i16x4 = i16x4::new(41, 40, 39, 38);
+         let r: i16x4 = transmute(vqsub_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_s16() {
+         let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i16x8 = i16x8::new(41, 40, 39, 38, 37, 36, 35, 34);
+         let r: i16x8 = transmute(vqsubq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_s32() {
+         let a: i32x2 = i32x2::new(42, 42);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(41, 40);
+         let r: i32x2 = transmute(vqsub_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_s32() {
+         let a: i32x4 = i32x4::new(42, 42, 42, 42);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: i32x4 = i32x4::new(41, 40, 39, 38);
+         let r: i32x4 = transmute(vqsubq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_u8() {
+         let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(21, 22, 22, 23, 23, 24, 24, 25);
+         let r: u8x8 = transmute(vhadd_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_u8() {
+         let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29);
+         let r: u8x16 = transmute(vhaddq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_u16() {
+         let a: u16x4 = u16x4::new(42, 42, 42, 42);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(21, 22, 22, 23);
+         let r: u16x4 = transmute(vhadd_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_u16() {
+         let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(21, 22, 22, 23, 23, 24, 24, 25);
+         let r: u16x8 = transmute(vhaddq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_u32() {
+         let a: u32x2 = u32x2::new(42, 42);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(21, 22);
+         let r: u32x2 = transmute(vhadd_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_u32() {
+         let a: u32x4 = u32x4::new(42, 42, 42, 42);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(21, 22, 22, 23);
+         let r: u32x4 = transmute(vhaddq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_s8() {
+         let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i8x8 = i8x8::new(21, 22, 22, 23, 23, 24, 24, 25);
+         let r: i8x8 = transmute(vhadd_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_s8() {
+         let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: i8x16 = i8x16::new(21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29);
+         let r: i8x16 = transmute(vhaddq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_s16() {
+         let a: i16x4 = i16x4::new(42, 42, 42, 42);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: i16x4 = i16x4::new(21, 22, 22, 23);
+         let r: i16x4 = transmute(vhadd_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_s16() {
+         let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i16x8 = i16x8::new(21, 22, 22, 23, 23, 24, 24, 25);
+         let r: i16x8 = transmute(vhaddq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_s32() {
+         let a: i32x2 = i32x2::new(42, 42);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(21, 22);
+         let r: i32x2 = transmute(vhadd_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_s32() {
+         let a: i32x4 = i32x4::new(42, 42, 42, 42);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: i32x4 = i32x4::new(21, 22, 22, 23);
+         let r: i32x4 = transmute(vhaddq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_u8() {
+         let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(22, 22, 23, 23, 24, 24, 25, 25);
+         let r: u8x8 = transmute(vrhadd_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_u8() {
+         let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29);
+         let r: u8x16 = transmute(vrhaddq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_u16() {
+         let a: u16x4 = u16x4::new(42, 42, 42, 42);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(22, 22, 23, 23);
+         let r: u16x4 = transmute(vrhadd_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_u16() {
+         let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(22, 22, 23, 23, 24, 24, 25, 25);
+         let r: u16x8 = transmute(vrhaddq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_u32() {
+         let a: u32x2 = u32x2::new(42, 42);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(22, 22);
+         let r: u32x2 = transmute(vrhadd_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_u32() {
+         let a: u32x4 = u32x4::new(42, 42, 42, 42);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(22, 22, 23, 23);
+         let r: u32x4 = transmute(vrhaddq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_s8() {
+         let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i8x8 = i8x8::new(22, 22, 23, 23, 24, 24, 25, 25);
+         let r: i8x8 = transmute(vrhadd_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_s8() {
+         let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: i8x16 = i8x16::new(22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29);
+         let r: i8x16 = transmute(vrhaddq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_s16() {
+         let a: i16x4 = i16x4::new(42, 42, 42, 42);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: i16x4 = i16x4::new(22, 22, 23, 23);
+         let r: i16x4 = transmute(vrhadd_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_s16() {
+         let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i16x8 = i16x8::new(22, 22, 23, 23, 24, 24, 25, 25);
+         let r: i16x8 = transmute(vrhaddq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_s32() {
+         let a: i32x2 = i32x2::new(42, 42);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(22, 22);
+         let r: i32x2 = transmute(vrhadd_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_s32() {
+         let a: i32x4 = i32x4::new(42, 42, 42, 42);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: i32x4 = i32x4::new(22, 22, 23, 23);
+         let r: i32x4 = transmute(vrhaddq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_u8() {
+         let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(43, 44, 45, 46, 47, 48, 49, 50);
+         let r: u8x8 = transmute(vqadd_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_u8() {
+         let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58);
+         let r: u8x16 = transmute(vqaddq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_u16() {
+         let a: u16x4 = u16x4::new(42, 42, 42, 42);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(43, 44, 45, 46);
+         let r: u16x4 = transmute(vqadd_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_u16() {
+         let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(43, 44, 45, 46, 47, 48, 49, 50);
+         let r: u16x8 = transmute(vqaddq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_u32() {
+         let a: u32x2 = u32x2::new(42, 42);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(43, 44);
+         let r: u32x2 = transmute(vqadd_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_u32() {
+         let a: u32x4 = u32x4::new(42, 42, 42, 42);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(43, 44, 45, 46);
+         let r: u32x4 = transmute(vqaddq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_s8() {
+         let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i8x8 = i8x8::new(43, 44, 45, 46, 47, 48, 49, 50);
+         let r: i8x8 = transmute(vqadd_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_s8() {
+         let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: i8x16 = i8x16::new(43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58);
+         let r: i8x16 = transmute(vqaddq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_s16() {
+         let a: i16x4 = i16x4::new(42, 42, 42, 42);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: i16x4 = i16x4::new(43, 44, 45, 46);
+         let r: i16x4 = transmute(vqadd_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_s16() {
+         let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i16x8 = i16x8::new(43, 44, 45, 46, 47, 48, 49, 50);
+         let r: i16x8 = transmute(vqaddq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_s32() {
+         let a: i32x2 = i32x2::new(42, 42);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(43, 44);
+         let r: i32x2 = transmute(vqadd_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_s32() {
+         let a: i32x4 = i32x4::new(42, 42, 42, 42);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: i32x4 = i32x4::new(43, 44, 45, 46);
+         let r: i32x4 = transmute(vqaddq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_s8() {
+         let a: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i8x8 = i8x8::new(1, 4, 3, 8, 5, 12, 7, 16);
+         let r: i8x8 = transmute(vmul_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_s8() {
+         let a: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2);
+         let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: i8x16 = i8x16::new(1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32);
+         let r: i8x16 = transmute(vmulq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_s16() {
+         let a: i16x4 = i16x4::new(1, 2, 1, 2);
+         let b: i16x4 = i16x4::new(1, 2, 3, 4);
+         let e: i16x4 = i16x4::new(1, 4, 3, 8);
+         let r: i16x4 = transmute(vmul_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_s16() {
+         let a: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: i16x8 = i16x8::new(1, 4, 3, 8, 5, 12, 7, 16);
+         let r: i16x8 = transmute(vmulq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_s32() {
+         let a: i32x2 = i32x2::new(1, 2);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(1, 4);
+         let r: i32x2 = transmute(vmul_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_s32() {
+         let a: i32x4 = i32x4::new(1, 2, 1, 2);
+         let b: i32x4 = i32x4::new(1, 2, 3, 4);
+         let e: i32x4 = i32x4::new(1, 4, 3, 8);
+         let r: i32x4 = transmute(vmulq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_u8() {
+         let a: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u8x8 = u8x8::new(1, 4, 3, 8, 5, 12, 7, 16);
+         let r: u8x8 = transmute(vmul_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_u8() {
+         let a: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2);
+         let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e: u8x16 = u8x16::new(1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32);
+         let r: u8x16 = transmute(vmulq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_u16() {
+         let a: u16x4 = u16x4::new(1, 2, 1, 2);
+         let b: u16x4 = u16x4::new(1, 2, 3, 4);
+         let e: u16x4 = u16x4::new(1, 4, 3, 8);
+         let r: u16x4 = transmute(vmul_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_u16() {
+         let a: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e: u16x8 = u16x8::new(1, 4, 3, 8, 5, 12, 7, 16);
+         let r: u16x8 = transmute(vmulq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_u32() {
+         let a: u32x2 = u32x2::new(1, 2);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(1, 4);
+         let r: u32x2 = transmute(vmul_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_u32() {
+         let a: u32x4 = u32x4::new(1, 2, 1, 2);
+         let b: u32x4 = u32x4::new(1, 2, 3, 4);
+         let e: u32x4 = u32x4::new(1, 4, 3, 8);
+         let r: u32x4 = transmute(vmulq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_f32() {
+         let a: f32x2 = f32x2::new(1.0, 2.0);
+         let b: f32x2 = f32x2::new(2.0, 3.0);
+         let e: f32x2 = f32x2::new(2.0, 6.0);
+         let r: f32x2 = transmute(vmul_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_f32() {
+         let a: f32x4 = f32x4::new(1.0, 2.0, 1.0, 2.0);
+         let b: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0);
+         let e: f32x4 = f32x4::new(2.0, 6.0, 4.0, 10.0);
+         let r: f32x4 = transmute(vmulq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s8() {
+         let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: i8x8 = i8x8::new(0, 0, 2, 2, 4, 4, 6, 6);
+         let r: i8x8 = transmute(vsub_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s8() {
+         let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2);
+         let e: i8x16 = i8x16::new(0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14);
+         let r: i8x16 = transmute(vsubq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s16() {
+         let a: i16x4 = i16x4::new(1, 2, 3, 4);
+         let b: i16x4 = i16x4::new(1, 2, 1, 2);
+         let e: i16x4 = i16x4::new(0, 0, 2, 2);
+         let r: i16x4 = transmute(vsub_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s16() {
+         let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: i16x8 = i16x8::new(0, 0, 2, 2, 4, 4, 6, 6);
+         let r: i16x8 = transmute(vsubq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s32() {
+         let a: i32x2 = i32x2::new(1, 2);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(0, 0);
+         let r: i32x2 = transmute(vsub_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s32() {
+         let a: i32x4 = i32x4::new(1, 2, 3, 4);
+         let b: i32x4 = i32x4::new(1, 2, 1, 2);
+         let e: i32x4 = i32x4::new(0, 0, 2, 2);
+         let r: i32x4 = transmute(vsubq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u8() {
+         let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: u8x8 = u8x8::new(0, 0, 2, 2, 4, 4, 6, 6);
+         let r: u8x8 = transmute(vsub_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u8() {
+         let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2);
+         let e: u8x16 = u8x16::new(0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14);
+         let r: u8x16 = transmute(vsubq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u16() {
+         let a: u16x4 = u16x4::new(1, 2, 3, 4);
+         let b: u16x4 = u16x4::new(1, 2, 1, 2);
+         let e: u16x4 = u16x4::new(0, 0, 2, 2);
+         let r: u16x4 = transmute(vsub_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u16() {
+         let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: u16x8 = u16x8::new(0, 0, 2, 2, 4, 4, 6, 6);
+         let r: u16x8 = transmute(vsubq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u32() {
+         let a: u32x2 = u32x2::new(1, 2);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(0, 0);
+         let r: u32x2 = transmute(vsub_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u32() {
+         let a: u32x4 = u32x4::new(1, 2, 3, 4);
+         let b: u32x4 = u32x4::new(1, 2, 1, 2);
+         let e: u32x4 = u32x4::new(0, 0, 2, 2);
+         let r: u32x4 = transmute(vsubq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s64() {
+         let a: i64x1 = i64x1::new(1);
+         let b: i64x1 = i64x1::new(1);
+         let e: i64x1 = i64x1::new(0);
+         let r: i64x1 = transmute(vsub_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s64() {
+         let a: i64x2 = i64x2::new(1, 2);
+         let b: i64x2 = i64x2::new(1, 2);
+         let e: i64x2 = i64x2::new(0, 0);
+         let r: i64x2 = transmute(vsubq_s64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u64() {
+         let a: u64x1 = u64x1::new(1);
+         let b: u64x1 = u64x1::new(1);
+         let e: u64x1 = u64x1::new(0);
+         let r: u64x1 = transmute(vsub_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u64() {
+         let a: u64x2 = u64x2::new(1, 2);
+         let b: u64x2 = u64x2::new(1, 2);
+         let e: u64x2 = u64x2::new(0, 0);
+         let r: u64x2 = transmute(vsubq_u64(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_f32() {
+         let a: f32x2 = f32x2::new(1.0, 4.0);
+         let b: f32x2 = f32x2::new(1.0, 2.0);
+         let e: f32x2 = f32x2::new(0.0, 2.0);
+         let r: f32x2 = transmute(vsub_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_f32() {
+         let a: f32x4 = f32x4::new(1.0, 4.0, 3.0, 8.0);
+         let b: f32x4 = f32x4::new(1.0, 2.0, 3.0, 4.0);
+         let e: f32x4 = f32x4::new(0.0, 2.0, 0.0, 4.0);
+         let r: f32x4 = transmute(vsubq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_u8() {
+         let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: u8x8 = u8x8::new(0, 0, 1, 1, 2, 2, 3, 3);
+         let r: u8x8 = transmute(vhsub_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_u8() {
+         let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2);
+         let e: u8x16 = u8x16::new(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7);
+         let r: u8x16 = transmute(vhsubq_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_u16() {
+         let a: u16x4 = u16x4::new(1, 2, 3, 4);
+         let b: u16x4 = u16x4::new(1, 2, 1, 2);
+         let e: u16x4 = u16x4::new(0, 0, 1, 1);
+         let r: u16x4 = transmute(vhsub_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_u16() {
+         let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: u16x8 = u16x8::new(0, 0, 1, 1, 2, 2, 3, 3);
+         let r: u16x8 = transmute(vhsubq_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_u32() {
+         let a: u32x2 = u32x2::new(1, 2);
+         let b: u32x2 = u32x2::new(1, 2);
+         let e: u32x2 = u32x2::new(0, 0);
+         let r: u32x2 = transmute(vhsub_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_u32() {
+         let a: u32x4 = u32x4::new(1, 2, 3, 4);
+         let b: u32x4 = u32x4::new(1, 2, 1, 2);
+         let e: u32x4 = u32x4::new(0, 0, 1, 1);
+         let r: u32x4 = transmute(vhsubq_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_s8() {
+         let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: i8x8 = i8x8::new(0, 0, 1, 1, 2, 2, 3, 3);
+         let r: i8x8 = transmute(vhsub_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_s8() {
+         let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2);
+         let e: i8x16 = i8x16::new(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7);
+         let r: i8x16 = transmute(vhsubq_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_s16() {
+         let a: i16x4 = i16x4::new(1, 2, 3, 4);
+         let b: i16x4 = i16x4::new(1, 2, 1, 2);
+         let e: i16x4 = i16x4::new(0, 0, 1, 1);
+         let r: i16x4 = transmute(vhsub_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_s16() {
+         let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2);
+         let e: i16x8 = i16x8::new(0, 0, 1, 1, 2, 2, 3, 3);
+         let r: i16x8 = transmute(vhsubq_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_s32() {
+         let a: i32x2 = i32x2::new(1, 2);
+         let b: i32x2 = i32x2::new(1, 2);
+         let e: i32x2 = i32x2::new(0, 0);
+         let r: i32x2 = transmute(vhsub_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_s32() {
+         let a: i32x4 = i32x4::new(1, 2, 3, 4);
+         let b: i32x4 = i32x4::new(1, 2, 1, 2);
+         let e: i32x4 = i32x4::new(0, 0, 1, 1);
+         let r: i32x4 = transmute(vhsubq_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,4364 ----
+ //! ARMv7 NEON intrinsics
+ 
+ #[rustfmt::skip]
+ mod generated;
+ #[rustfmt::skip]
+ pub use self::generated::*;
+ 
+ use crate::{core_arch::simd_llvm::*, hint::unreachable_unchecked, mem::transmute, ptr};
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ types! {
+     /// ARM-specific 64-bit wide vector of eight packed `i8`.
+     pub struct int8x8_t(i8, i8, i8, i8, i8, i8, i8, i8);
+     /// ARM-specific 64-bit wide vector of eight packed `u8`.
+     pub struct uint8x8_t(u8, u8, u8, u8, u8, u8, u8, u8);
+     /// ARM-specific 64-bit wide polynomial vector of eight packed `u8`.
+     pub struct poly8x8_t(u8, u8, u8, u8, u8, u8, u8, u8);
+     /// ARM-specific 64-bit wide vector of four packed `i16`.
+     pub struct int16x4_t(i16, i16, i16, i16);
+     /// ARM-specific 64-bit wide vector of four packed `u16`.
+     pub struct uint16x4_t(u16, u16, u16, u16);
+     // FIXME: ARM-specific 64-bit wide vector of four packed `f16`.
+     // pub struct float16x4_t(f16, f16, f16, f16);
+     /// ARM-specific 64-bit wide vector of four packed `u16`.
+     pub struct poly16x4_t(u16, u16, u16, u16);
+     /// ARM-specific 64-bit wide vector of two packed `i32`.
+     pub struct int32x2_t(i32, i32);
+     /// ARM-specific 64-bit wide vector of two packed `u32`.
+     pub struct uint32x2_t(u32, u32);
+     /// ARM-specific 64-bit wide vector of two packed `f32`.
+     pub struct float32x2_t(f32, f32);
+     /// ARM-specific 64-bit wide vector of one packed `i64`.
+     pub struct int64x1_t(i64);
+     /// ARM-specific 64-bit wide vector of one packed `u64`.
+     pub struct uint64x1_t(u64);
+ 
+     /// ARM-specific 128-bit wide vector of sixteen packed `i8`.
+     pub struct int8x16_t(
+         i8, i8 ,i8, i8, i8, i8 ,i8, i8,
+         i8, i8 ,i8, i8, i8, i8 ,i8, i8,
+     );
+     /// ARM-specific 128-bit wide vector of sixteen packed `u8`.
+     pub struct uint8x16_t(
+         u8, u8 ,u8, u8, u8, u8 ,u8, u8,
+         u8, u8 ,u8, u8, u8, u8 ,u8, u8,
+     );
+     /// ARM-specific 128-bit wide vector of sixteen packed `u8`.
+     pub struct poly8x16_t(
+         u8, u8, u8, u8, u8, u8, u8, u8,
+         u8, u8, u8, u8, u8, u8, u8, u8
+     );
+     /// ARM-specific 128-bit wide vector of eight packed `i16`.
+     pub struct int16x8_t(i16, i16, i16, i16, i16, i16, i16, i16);
+     /// ARM-specific 128-bit wide vector of eight packed `u16`.
+     pub struct uint16x8_t(u16, u16, u16, u16, u16, u16, u16, u16);
+     // FIXME: ARM-specific 128-bit wide vector of eight packed `f16`.
+     // pub struct float16x8_t(f16, f16, f16, f16, f16, f16, f16);
+     /// ARM-specific 128-bit wide vector of eight packed `u16`.
+     pub struct poly16x8_t(u16, u16, u16, u16, u16, u16, u16, u16);
+     /// ARM-specific 128-bit wide vector of four packed `i32`.
+     pub struct int32x4_t(i32, i32, i32, i32);
+     /// ARM-specific 128-bit wide vector of four packed `u32`.
+     pub struct uint32x4_t(u32, u32, u32, u32);
+     /// ARM-specific 128-bit wide vector of four packed `f32`.
+     pub struct float32x4_t(f32, f32, f32, f32);
+     /// ARM-specific 128-bit wide vector of two packed `i64`.
+     pub struct int64x2_t(i64, i64);
+     /// ARM-specific 128-bit wide vector of two packed `u64`.
+     pub struct uint64x2_t(u64, u64);
+ }
+ 
+ /// ARM-specific type containing two `int8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct int8x8x2_t(pub int8x8_t, pub int8x8_t);
+ /// ARM-specific type containing three `int8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct int8x8x3_t(pub int8x8_t, pub int8x8_t, pub int8x8_t);
+ /// ARM-specific type containing four `int8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct int8x8x4_t(pub int8x8_t, pub int8x8_t, pub int8x8_t, pub int8x8_t);
+ 
+ /// ARM-specific type containing two `uint8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct uint8x8x2_t(pub uint8x8_t, pub uint8x8_t);
+ /// ARM-specific type containing three `uint8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct uint8x8x3_t(pub uint8x8_t, pub uint8x8_t, pub uint8x8_t);
+ /// ARM-specific type containing four `uint8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct uint8x8x4_t(pub uint8x8_t, pub uint8x8_t, pub uint8x8_t, pub uint8x8_t);
+ 
+ /// ARM-specific type containing two `poly8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct poly8x8x2_t(pub poly8x8_t, pub poly8x8_t);
+ /// ARM-specific type containing three `poly8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct poly8x8x3_t(pub poly8x8_t, pub poly8x8_t, pub poly8x8_t);
+ /// ARM-specific type containing four `poly8x8_t` vectors.
+ #[derive(Copy, Clone)]
+ pub struct poly8x8x4_t(pub poly8x8_t, pub poly8x8_t, pub poly8x8_t, pub poly8x8_t);
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     // absolute value (64-bit)
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.abs.v8i8")]
+     fn vabs_s8_(a: int8x8_t) -> int8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.abs.v4i16")]
+     fn vabs_s16_(a: int16x4_t) -> int16x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.abs.v2i32")]
+     fn vabs_s32_(a: int32x2_t) -> int32x2_t;
+     // absolute value (128-bit)
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.abs.v16i8")]
+     fn vabsq_s8_(a: int8x16_t) -> int8x16_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.abs.v8i16")]
+     fn vabsq_s16_(a: int16x8_t) -> int16x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.abs.v4i32")]
+     fn vabsq_s32_(a: int32x4_t) -> int32x4_t;
+ 
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frsqrte.v2f32")]
+     fn frsqrte_v2f32(a: float32x2_t) -> float32x2_t;
+ 
+     //uint32x2_t vqmovn_u64 (uint64x2_t a)
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqxtn.v2i32")]
+     fn vqmovn_u64_(a: uint64x2_t) -> uint32x2_t;
+ 
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sminp.v8i8")]
+     fn vpmins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sminp.v4i16")]
+     fn vpmins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sminp.v2i32")]
+     fn vpmins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uminp.v8i8")]
+     fn vpminu_v8i8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uminp.v4i16")]
+     fn vpminu_v4i16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uminp.v2i32")]
+     fn vpminu_v2i32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminp.v2f32")]
+     fn vpminf_v2f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
+ 
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.smaxp.v8i8")]
+     fn vpmaxs_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.smaxp.v4i16")]
+     fn vpmaxs_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.smaxp.v2i32")]
+     fn vpmaxs_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.umaxp.v8i8")]
+     fn vpmaxu_v8i8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.umaxp.v4i16")]
+     fn vpmaxu_v4i16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.umaxp.v2i32")]
+     fn vpmaxu_v2i32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxp.v2f32")]
+     fn vpmaxf_v2f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
+ 
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.addp.v4i16")]
+     fn vpadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.addp.v2i32")]
+     fn vpadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.addp.v8i8")]
+     fn vpadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v16i8")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.addp.v16i8")]
+     fn vpaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t;
+ 
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmax.v4f32")]
+     fn vmaxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")]
+     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmin.v4f32")]
+     fn vminq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t;
+ }
+ 
+ #[cfg(target_arch = "arm")]
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.arm.neon.vtbl1"]
+     fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
+     #[link_name = "llvm.arm.neon.vtbl2"]
+     fn vtbl2(a: int8x8_t, b: int8x8_t, b: int8x8_t) -> int8x8_t;
+     #[link_name = "llvm.arm.neon.vtbl3"]
+     fn vtbl3(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
+     #[link_name = "llvm.arm.neon.vtbl4"]
+     fn vtbl4(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
+ 
+     #[link_name = "llvm.arm.neon.vtbx1"]
+     fn vtbx1(a: int8x8_t, b: int8x8_t, b: int8x8_t) -> int8x8_t;
+     #[link_name = "llvm.arm.neon.vtbx2"]
+     fn vtbx2(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
+     #[link_name = "llvm.arm.neon.vtbx3"]
+     fn vtbx3(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
+     #[link_name = "llvm.arm.neon.vtbx4"]
+     fn vtbx4(
+         a: int8x8_t,
+         b: int8x8_t,
+         b: int8x8_t,
+         c: int8x8_t,
+         d: int8x8_t,
+         e: int8x8_t,
+     ) -> int8x8_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32.p0i8")]
+     fn vld1q_v4f32(addr: *const u8, align: u32) -> float32x4_t;
+     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32.p0i8")]
+     fn vld1q_v4i32(addr: *const u8, align: u32) -> int32x4_t;
+ }
+ 
+ /// Absolute value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(abs))]
+ pub unsafe fn vabs_s8(a: int8x8_t) -> int8x8_t {
+     vabs_s8_(a)
+ }
+ /// Absolute value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(abs))]
+ pub unsafe fn vabs_s16(a: int16x4_t) -> int16x4_t {
+     vabs_s16_(a)
+ }
+ /// Absolute value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(abs))]
+ pub unsafe fn vabs_s32(a: int32x2_t) -> int32x2_t {
+     vabs_s32_(a)
+ }
+ /// Absolute value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(abs))]
+ pub unsafe fn vabsq_s8(a: int8x16_t) -> int8x16_t {
+     vabsq_s8_(a)
+ }
+ /// Absolute value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(abs))]
+ pub unsafe fn vabsq_s16(a: int16x8_t) -> int16x8_t {
+     vabsq_s16_(a)
+ }
+ /// Absolute value (wrapping).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(abs))]
+ pub unsafe fn vabsq_s32(a: int32x4_t) -> int32x4_t {
+     vabsq_s32_(a)
+ }
+ 
+ /// Add pairwise.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(addp))]
+ pub unsafe fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     vpadd_s16_(a, b)
+ }
+ /// Add pairwise.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(addp))]
+ pub unsafe fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     vpadd_s32_(a, b)
+ }
+ /// Add pairwise.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(addp))]
+ pub unsafe fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     vpadd_s8_(a, b)
+ }
+ /// Add pairwise.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(addp))]
+ pub unsafe fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     transmute(vpadd_s16_(transmute(a), transmute(b)))
+ }
+ /// Add pairwise.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(addp))]
+ pub unsafe fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     transmute(vpadd_s32_(transmute(a), transmute(b)))
+ }
+ /// Add pairwise.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(addp))]
+ pub unsafe fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     transmute(vpadd_s8_(transmute(a), transmute(b)))
+ }
+ 
+ /// Unsigned saturating extract narrow.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn.u64))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uqxtn))]
+ pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
+     vqmovn_u64_(a)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
+ pub unsafe fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fadd))]
+ pub unsafe fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fadd))]
+ pub unsafe fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     simd_add(a, b)
+ }
+ 
+ /// Vector long add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(saddl))]
+ pub unsafe fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
+     let a: int16x8_t = simd_cast(a);
+     let b: int16x8_t = simd_cast(b);
+     simd_add(a, b)
+ }
+ 
+ /// Vector long add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(saddl))]
+ pub unsafe fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
+     let a: int32x4_t = simd_cast(a);
+     let b: int32x4_t = simd_cast(b);
+     simd_add(a, b)
+ }
+ 
+ /// Vector long add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(saddl))]
+ pub unsafe fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
+     let a: int64x2_t = simd_cast(a);
+     let b: int64x2_t = simd_cast(b);
+     simd_add(a, b)
+ }
+ 
+ /// Vector long add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uaddl))]
+ pub unsafe fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
+     let a: uint16x8_t = simd_cast(a);
+     let b: uint16x8_t = simd_cast(b);
+     simd_add(a, b)
+ }
+ 
+ /// Vector long add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uaddl))]
+ pub unsafe fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
+     let a: uint32x4_t = simd_cast(a);
+     let b: uint32x4_t = simd_cast(b);
+     simd_add(a, b)
+ }
+ 
+ /// Vector long add.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uaddl))]
+ pub unsafe fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
+     let a: uint64x2_t = simd_cast(a);
+     let b: uint64x2_t = simd_cast(b);
+     simd_add(a, b)
+ }
+ 
+ /// Vector narrow integer.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
+ pub unsafe fn vmovn_s16(a: int16x8_t) -> int8x8_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector narrow integer.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
+ pub unsafe fn vmovn_s32(a: int32x4_t) -> int16x4_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector narrow integer.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
+ pub unsafe fn vmovn_s64(a: int64x2_t) -> int32x2_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector narrow integer.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
+ pub unsafe fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector narrow integer.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
+ pub unsafe fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector narrow integer.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
+ pub unsafe fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector long move.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sxtl))]
+ pub unsafe fn vmovl_s8(a: int8x8_t) -> int16x8_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector long move.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sxtl))]
+ pub unsafe fn vmovl_s16(a: int16x4_t) -> int32x4_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector long move.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sxtl))]
+ pub unsafe fn vmovl_s32(a: int32x2_t) -> int64x2_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector long move.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uxtl))]
+ pub unsafe fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector long move.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uxtl))]
+ pub unsafe fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
+     simd_cast(a)
+ }
+ 
+ /// Vector long move.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uxtl))]
+ pub unsafe fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
+     simd_cast(a)
+ }
+ 
+ /// Reciprocal square-root estimate.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(frsqrte))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
+ pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
+     frsqrte_v2f32(a)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_s8(a: int8x8_t) -> int8x8_t {
+     let b = int8x8_t(-1, -1, -1, -1, -1, -1, -1, -1);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
+     let b = int8x16_t(
+         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     );
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_s16(a: int16x4_t) -> int16x4_t {
+     let b = int16x4_t(-1, -1, -1, -1);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
+     let b = int16x8_t(-1, -1, -1, -1, -1, -1, -1, -1);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_s32(a: int32x2_t) -> int32x2_t {
+     let b = int32x2_t(-1, -1);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
+     let b = int32x4_t(-1, -1, -1, -1);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
+     let b = uint8x8_t(255, 255, 255, 255, 255, 255, 255, 255);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
+     let b = uint8x16_t(
+         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+     );
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
+     let b = uint16x4_t(65_535, 65_535, 65_535, 65_535);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
+     let b = uint16x8_t(
+         65_535, 65_535, 65_535, 65_535, 65_535, 65_535, 65_535, 65_535,
+     );
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
+     let b = uint32x2_t(4_294_967_295, 4_294_967_295);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
+     let b = uint32x4_t(4_294_967_295, 4_294_967_295, 4_294_967_295, 4_294_967_295);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
+     let b = poly8x8_t(255, 255, 255, 255, 255, 255, 255, 255);
+     simd_xor(a, b)
+ }
+ 
+ /// Vector bitwise not.
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
+ pub unsafe fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
+     let b = poly8x16_t(
+         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+     );
+     simd_xor(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sminp))]
+ pub unsafe fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     vpmins_v8i8(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sminp))]
+ pub unsafe fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     vpmins_v4i16(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sminp))]
+ pub unsafe fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     vpmins_v2i32(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uminp))]
+ pub unsafe fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     vpminu_v8i8(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uminp))]
+ pub unsafe fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     vpminu_v4i16(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uminp))]
+ pub unsafe fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     vpminu_v2i32(a, b)
+ }
+ 
+ /// Folding minimum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fminp))]
+ pub unsafe fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
+     vpminf_v2f32(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(smaxp))]
+ pub unsafe fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     vpmaxs_v8i8(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(smaxp))]
+ pub unsafe fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
+     vpmaxs_v4i16(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(smaxp))]
+ pub unsafe fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
+     vpmaxs_v2i32(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umaxp))]
+ pub unsafe fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     vpmaxu_v8i8(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umaxp))]
+ pub unsafe fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
+     vpmaxu_v4i16(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umaxp))]
+ pub unsafe fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
+     vpmaxu_v2i32(a, b)
+ }
+ 
+ /// Folding maximum of adjacent pairs
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmaxp))]
+ pub unsafe fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
+     vpmaxf_v2f32(a, b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
+     vtbl1(a, b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
+     transmute(vtbl1(transmute(a), transmute(b)))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
+     transmute(vtbl1(transmute(a), transmute(b)))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
+     vtbl2(a.0, a.1, b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
+     transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
+     transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
+     vtbl3(a.0, a.1, a.2, b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
+     transmute(vtbl3(
+         transmute(a.0),
+         transmute(a.1),
+         transmute(a.2),
+         transmute(b),
+     ))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
+     transmute(vtbl3(
+         transmute(a.0),
+         transmute(a.1),
+         transmute(a.2),
+         transmute(b),
+     ))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
+     vtbl4(a.0, a.1, a.2, a.3, b)
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
+     transmute(vtbl4(
+         transmute(a.0),
+         transmute(a.1),
+         transmute(a.2),
+         transmute(a.3),
+         transmute(b),
+     ))
+ }
+ 
+ /// Table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbl))]
+ pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
+     transmute(vtbl4(
+         transmute(a.0),
+         transmute(a.1),
+         transmute(a.2),
+         transmute(a.3),
+         transmute(b),
+     ))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
+     vtbx1(a, b, c)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
+     transmute(vtbx1(transmute(a), transmute(b), transmute(c)))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
+     transmute(vtbx1(transmute(a), transmute(b), transmute(c)))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
+     vtbx2(a, b.0, b.1, c)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
+     transmute(vtbx2(
+         transmute(a),
+         transmute(b.0),
+         transmute(b.1),
+         transmute(c),
+     ))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
+     transmute(vtbx2(
+         transmute(a),
+         transmute(b.0),
+         transmute(b.1),
+         transmute(c),
+     ))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
+     vtbx3(a, b.0, b.1, b.2, c)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
+     transmute(vtbx3(
+         transmute(a),
+         transmute(b.0),
+         transmute(b.1),
+         transmute(b.2),
+         transmute(c),
+     ))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
+     transmute(vtbx3(
+         transmute(a),
+         transmute(b.0),
+         transmute(b.1),
+         transmute(b.2),
+         transmute(c),
+     ))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
+     vtbx4(a, b.0, b.1, b.2, b.3, c)
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
+     transmute(vtbx4(
+         transmute(a),
+         transmute(b.0),
+         transmute(b.1),
+         transmute(b.2),
+         transmute(b.3),
+         transmute(c),
+     ))
+ }
+ 
+ /// Extended table look-up
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[cfg(target_endian = "little")]
+ #[target_feature(enable = "neon,v7")]
+ #[cfg_attr(test, assert_instr(vtbx))]
+ pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
+     transmute(vtbx4(
+         transmute(a),
+         transmute(b.0),
+         transmute(b.1),
+         transmute(b.2),
+         transmute(b.3),
+         transmute(c),
+     ))
+ }
+ 
+ /// Move vector element to general-purpose register
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov.32", imm5 = 1))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mov, imm5 = 1))]
+ // Based on the discussion in https://github.com/rust-lang/stdarch/pull/792
+ // `mov` seems to be an acceptable intrinsic to compile to
+ // #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(vmov, imm5 = 1))]
+ pub unsafe fn vgetq_lane_u64(v: uint64x2_t, imm5: i32) -> u64 {
+     assert!(imm5 >= 0 && imm5 <= 1);
+     simd_extract(v, imm5 as u32)
+ }
+ 
+ /// Move vector element to general-purpose register
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov.32", imm5 = 0))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmov, imm5 = 0))]
+ // FIXME: no 32bit this seems to be turned into two vmov.32 instructions
+ // validate correctness
+ pub unsafe fn vget_lane_u64(v: uint64x1_t, imm5: i32) -> u64 {
+     assert!(imm5 == 0);
+     simd_extract(v, 0)
+ }
+ 
+ /// Move vector element to general-purpose register
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov.u16", imm5 = 2))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umov, imm5 = 2))]
+ pub unsafe fn vgetq_lane_u16(v: uint16x8_t, imm5: i32) -> u16 {
+     assert!(imm5 >= 0 && imm5 <= 7);
+     simd_extract(v, imm5 as u32)
+ }
+ 
+ /// Move vector element to general-purpose register
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov.32", imm5 = 2))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mov, imm5 = 2))]
+ pub unsafe fn vgetq_lane_u32(v: uint32x4_t, imm5: i32) -> u32 {
+     assert!(imm5 >= 0 && imm5 <= 3);
+     simd_extract(v, imm5 as u32)
+ }
+ 
+ /// Move vector element to general-purpose register
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov.32", imm5 = 2))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mov, imm5 = 2))]
+ pub unsafe fn vgetq_lane_s32(v: int32x4_t, imm5: i32) -> i32 {
+     assert!(imm5 >= 0 && imm5 <= 3);
+     simd_extract(v, imm5 as u32)
+ }
+ 
+ /// Move vector element to general-purpose register
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov.u8", imm5 = 2))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umov, imm5 = 2))]
+ pub unsafe fn vget_lane_u8(v: uint8x8_t, imm5: i32) -> u8 {
+     assert!(imm5 >= 0 && imm5 <= 7);
+     simd_extract(v, imm5 as u32)
+ }
+ 
+ /// Duplicate vector element to vector or scalar
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(dup))]
+ pub unsafe fn vdupq_n_s8(value: i8) -> int8x16_t {
+     int8x16_t(
+         value, value, value, value, value, value, value, value, value, value, value, value, value,
+         value, value, value,
+     )
+ }
+ 
+ /// Duplicate vector element to vector or scalar
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(dup))]
+ pub unsafe fn vdupq_n_u8(value: u8) -> uint8x16_t {
+     uint8x16_t(
+         value, value, value, value, value, value, value, value, value, value, value, value, value,
+         value, value, value,
+     )
+ }
+ 
+ /// Duplicate vector element to vector or scalar
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(dup))]
+ pub unsafe fn vmovq_n_u8(value: u8) -> uint8x16_t {
+     vdupq_n_u8(value)
+ }
+ 
+ /// Vector reinterpret cast operation
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(nop))]
+ pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
+     transmute(a)
+ }
+ 
+ /// Vector reinterpret cast operation
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(nop))]
+ pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
+     transmute(a)
+ }
+ 
+ /// Vector reinterpret cast operation
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(nop))]
+ pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
+     transmute(a)
+ }
+ 
+ /// Vector reinterpret cast operation
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(nop))]
+ pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
+     transmute(a)
+ }
+ 
+ /// Vector reinterpret cast operation
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(nop))]
+ pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
+     transmute(a)
+ }
+ 
+ /// Vector reinterpret cast operation
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(nop))]
+ pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
+     transmute(a)
+ }
+ 
+ /// Unsigned shift right
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", imm3 = 1))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr("ushr", imm3 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn vshrq_n_u8(a: uint8x16_t, imm3: i32) -> uint8x16_t {
+     if imm3 < 0 || imm3 > 7 {
+         unreachable_unchecked();
+     } else {
+         uint8x16_t(
+             a.0 >> imm3,
+             a.1 >> imm3,
+             a.2 >> imm3,
+             a.3 >> imm3,
+             a.4 >> imm3,
+             a.5 >> imm3,
+             a.6 >> imm3,
+             a.7 >> imm3,
+             a.8 >> imm3,
+             a.9 >> imm3,
+             a.10 >> imm3,
+             a.11 >> imm3,
+             a.12 >> imm3,
+             a.13 >> imm3,
+             a.14 >> imm3,
+             a.15 >> imm3,
+         )
+     }
+ }
+ 
+ /// Shift right
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshl.s8", imm3 = 1))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(shl, imm3 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn vshlq_n_u8(a: uint8x16_t, imm3: i32) -> uint8x16_t {
+     if imm3 < 0 || imm3 > 7 {
+         unreachable_unchecked();
+     } else {
+         uint8x16_t(
+             a.0 << imm3,
+             a.1 << imm3,
+             a.2 << imm3,
+             a.3 << imm3,
+             a.4 << imm3,
+             a.5 << imm3,
+             a.6 << imm3,
+             a.7 << imm3,
+             a.8 << imm3,
+             a.9 << imm3,
+             a.10 << imm3,
+             a.11 << imm3,
+             a.12 << imm3,
+             a.13 << imm3,
+             a.14 << imm3,
+             a.15 << imm3,
+         )
+     }
+ }
+ 
+ /// Extract vector from pair of vectors
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", n = 3))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, n = 3))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t {
+     if n < 0 || n > 15 {
+         unreachable_unchecked();
+     };
+     match n & 0b1111 {
+         0 => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17],
+         ),
+         3 => simd_shuffle16(
+             a,
+             b,
+             [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18],
+         ),
+         4 => simd_shuffle16(
+             a,
+             b,
+             [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19],
+         ),
+         5 => simd_shuffle16(
+             a,
+             b,
+             [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20],
+         ),
+         6 => simd_shuffle16(
+             a,
+             b,
+             [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21],
+         ),
+         7 => simd_shuffle16(
+             a,
+             b,
+             [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22],
+         ),
+         8 => simd_shuffle16(
+             a,
+             b,
+             [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23],
+         ),
+         9 => simd_shuffle16(
+             a,
+             b,
+             [
+                 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+             ],
+         ),
+         10 => simd_shuffle16(
+             a,
+             b,
+             [
+                 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+             ],
+         ),
+         11 => simd_shuffle16(
+             a,
+             b,
+             [
+                 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+             ],
+         ),
+         12 => simd_shuffle16(
+             a,
+             b,
+             [
+                 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
+             ],
+         ),
+         13 => simd_shuffle16(
+             a,
+             b,
+             [
+                 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
+             ],
+         ),
+         14 => simd_shuffle16(
+             a,
+             b,
+             [
+                 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+             ],
+         ),
+         15 => simd_shuffle16(
+             a,
+             b,
+             [
+                 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+             ],
+         ),
+         _ => unreachable_unchecked(),
+     }
+ }
+ 
+ /// Extract vector from pair of vectors
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", n = 3))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, n = 3))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn vextq_u8(a: uint8x16_t, b: uint8x16_t, n: i32) -> uint8x16_t {
+     if n < 0 || n > 15 {
+         unreachable_unchecked();
+     };
+     match n & 0b1111 {
+         0 => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17],
+         ),
+         3 => simd_shuffle16(
+             a,
+             b,
+             [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18],
+         ),
+         4 => simd_shuffle16(
+             a,
+             b,
+             [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19],
+         ),
+         5 => simd_shuffle16(
+             a,
+             b,
+             [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20],
+         ),
+         6 => simd_shuffle16(
+             a,
+             b,
+             [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21],
+         ),
+         7 => simd_shuffle16(
+             a,
+             b,
+             [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22],
+         ),
+         8 => simd_shuffle16(
+             a,
+             b,
+             [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23],
+         ),
+         9 => simd_shuffle16(
+             a,
+             b,
+             [
+                 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+             ],
+         ),
+         10 => simd_shuffle16(
+             a,
+             b,
+             [
+                 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+             ],
+         ),
+         11 => simd_shuffle16(
+             a,
+             b,
+             [
+                 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+             ],
+         ),
+         12 => simd_shuffle16(
+             a,
+             b,
+             [
+                 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
+             ],
+         ),
+         13 => simd_shuffle16(
+             a,
+             b,
+             [
+                 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
+             ],
+         ),
+         14 => simd_shuffle16(
+             a,
+             b,
+             [
+                 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+             ],
+         ),
+         15 => simd_shuffle16(
+             a,
+             b,
+             [
+                 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+             ],
+         ),
+         _ => unreachable_unchecked(),
+     }
+ }
+ 
+ /// Load multiple single-element structures to one, two, three, or four registers
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(ldr))]
+ // even gcc compiles this to ldr: https://clang.godbolt.org/z/1bvH2x
+ // #[cfg_attr(test, assert_instr(ld1))]
+ pub unsafe fn vld1q_s8(addr: *const i8) -> int8x16_t {
+     ptr::read(addr as *const int8x16_t)
+ }
+ 
+ /// Load multiple single-element structures to one, two, three, or four registers
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(ldr))]
+ // even gcc compiles this to ldr: https://clang.godbolt.org/z/1bvH2x
+ // #[cfg_attr(test, assert_instr(ld1))]
+ pub unsafe fn vld1q_u8(addr: *const u8) -> uint8x16_t {
+     ptr::read(addr as *const uint8x16_t)
+ }
+ 
+ /// Load multiple single-element structures to one, two, three, or four registers
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[target_feature(enable = "neon")]
+ #[target_feature(enable = "v7")]
+ #[cfg_attr(test, assert_instr("vld1.32"))]
+ pub unsafe fn vld1q_s32(addr: *const i32) -> int32x4_t {
+     vld1q_v4i32(addr as *const u8, 4)
+ }
+ 
+ /// Load multiple single-element structures to one, two, three, or four registers
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[target_feature(enable = "neon")]
+ #[target_feature(enable = "v7")]
+ #[cfg_attr(test, assert_instr("vld1.32"))]
+ pub unsafe fn vld1q_u32(addr: *const u32) -> uint32x4_t {
+     transmute(vld1q_v4i32(addr as *const u8, 4))
+ }
+ 
+ /// Load multiple single-element structures to one, two, three, or four registers
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[target_feature(enable = "neon")]
+ #[target_feature(enable = "v7")]
+ #[cfg_attr(test, assert_instr("vld1.32"))]
+ pub unsafe fn vld1q_f32(addr: *const f32) -> float32x4_t {
+     vld1q_v4f32(addr as *const u8, 4)
+ }
+ 
+ /// Load one single-element structure and Replicate to all lanes (of one register).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ld1r))]
+ pub unsafe fn vld1q_dup_f32(addr: *const f32) -> float32x4_t {
+     use crate::core_arch::simd::f32x4;
+     let v = *addr;
+     transmute(f32x4::new(v, v, v, v))
+ }
+ 
+ // These float-to-int implementations have undefined behaviour when `a` overflows
+ // the destination type. Clang has the same problem: https://llvm.org/PR47510
+ 
+ /// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[target_feature(enable = "neon")]
+ #[target_feature(enable = "v7")]
+ #[cfg_attr(test, assert_instr("vcvt.s32.f32"))]
+ pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
+     use crate::core_arch::simd::{f32x4, i32x4};
+     transmute(simd_cast::<_, i32x4>(transmute::<_, f32x4>(a)))
+ }
+ 
+ /// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)
+ #[inline]
+ #[cfg(target_arch = "arm")]
+ #[target_feature(enable = "neon")]
+ #[target_feature(enable = "v7")]
+ #[cfg_attr(test, assert_instr("vcvt.u32.f32"))]
+ pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
+     use crate::core_arch::simd::{f32x4, u32x4};
+     transmute(simd_cast::<_, u32x4>(transmute::<_, f32x4>(a)))
+ }
+ 
+ /// Floating-point minimum (vector).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmin.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmin))]
+ pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     vminq_f32_(a, b)
+ }
+ 
+ /// Floating-point maxmimum (vector).
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmax.f32"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmax))]
+ pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
+     vmaxq_f32_(a, b)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use super::*;
+     use crate::core_arch::arm::test_support::*;
+     use crate::core_arch::{arm::*, simd::*};
+     use std::{i16, i32, i8, mem::transmute, u16, u32, u8, vec::Vec};
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_s8() {
+         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e = a;
+         let r: i8x16 = transmute(vld1q_s8(transmute(&a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_u8() {
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e = a;
+         let r: u8x16 = transmute(vld1q_u8(transmute(&a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[cfg(target_arch = "arm")]
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_f32() {
+         let e = f32x4::new(1., 2., 3., 4.);
+         let f = [0., 1., 2., 3., 4.];
+         // do a load that has 4 byte alignment to make sure we're not
+         // over aligning it
+         let r: f32x4 = transmute(vld1q_f32(f[1..].as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[cfg(target_arch = "arm")]
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_s32() {
+         let e = i32x4::new(1, 2, 3, 4);
+         let f = [0, 1, 2, 3, 4];
+         // do a load that has 4 byte alignment to make sure we're not
+         // over aligning it
+         let r: i32x4 = transmute(vld1q_s32(f[1..].as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[cfg(target_arch = "arm")]
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_u32() {
+         let e = u32x4::new(1, 2, 3, 4);
+         let f = [0, 1, 2, 3, 4];
+         // do a load that has 4 byte alignment to make sure we're not
+         // over aligning it
+         let r: u32x4 = transmute(vld1q_u32(f[1..].as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vld1q_dup_f32() {
+         let e = f32x4::new(1., 1., 1., 1.);
+         let f = [1., 2., 3., 4.];
+         let r: f32x4 = transmute(vld1q_dup_f32(f.as_ptr()));
+         assert_eq!(r, e);
+     }
+ 
+     #[cfg(target_arch = "arm")]
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcvtq_s32_f32() {
+         let f = f32x4::new(-1., 2., 3., 4.);
+         let e = i32x4::new(-1, 2, 3, 4);
+         let r: i32x4 = transmute(vcvtq_s32_f32(transmute(f)));
+         assert_eq!(r, e);
+     }
+ 
+     #[cfg(target_arch = "arm")]
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcvtq_u32_f32() {
+         let f = f32x4::new(1., 2., 3., 4.);
+         let e = u32x4::new(1, 2, 3, 4);
+         let r: u32x4 = transmute(vcvtq_u32_f32(transmute(f)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vget_lane_u8() {
+         let v = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = vget_lane_u8(transmute(v), 1);
+         assert_eq!(r, 2);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vgetq_lane_u32() {
+         let v = i32x4::new(1, 2, 3, 4);
+         let r = vgetq_lane_u32(transmute(v), 1);
+         assert_eq!(r, 2);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vgetq_lane_s32() {
+         let v = i32x4::new(1, 2, 3, 4);
+         let r = vgetq_lane_s32(transmute(v), 1);
+         assert_eq!(r, 2);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vget_lane_u64() {
+         let v: u64 = 1;
+         let r = vget_lane_u64(transmute(v), 0);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vgetq_lane_u16() {
+         let v = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = vgetq_lane_u16(transmute(v), 1);
+         assert_eq!(r, 2);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vextq_s8() {
+         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = i8x16::new(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 31, 32,
+         );
+         let e = i8x16::new(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+         let r: i8x16 = transmute(vextq_s8(transmute(a), transmute(b), 3));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vextq_u8() {
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = u8x16::new(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 31, 32,
+         );
+         let e = u8x16::new(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+         let r: u8x16 = transmute(vextq_u8(transmute(a), transmute(b), 3));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vshrq_n_u8() {
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e = u8x16::new(0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4);
+         let r: u8x16 = transmute(vshrq_n_u8(transmute(a), 2));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vshlq_n_u8() {
+         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let e = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64);
+         let r: u8x16 = transmute(vshlq_n_u8(transmute(a), 2));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqmovn_u64() {
+         let a = u64x2::new(1, 2);
+         let e = u32x2::new(1, 2);
+         let r: u32x2 = transmute(vqmovn_u64(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vreinterpret_u64_u32() {
+         let v: i8 = 42;
+         let e = i8x16::new(
+             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
+         );
+         let r: i8x16 = transmute(vdupq_n_s8(v));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vdupq_n_s8() {
+         let v: i8 = 42;
+         let e = i8x16::new(
+             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
+         );
+         let r: i8x16 = transmute(vdupq_n_s8(v));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vdupq_n_u8() {
+         let v: u8 = 42;
+         let e = u8x16::new(
+             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
+         );
+         let r: u8x16 = transmute(vdupq_n_u8(v));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovq_n_u8() {
+         let v: u8 = 42;
+         let e = u8x16::new(
+             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
+         );
+         let r: u8x16 = transmute(vmovq_n_u8(v));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vgetq_lane_u64() {
+         let v = i64x2::new(1, 2);
+         let r = vgetq_lane_u64(transmute(v), 1);
+         assert_eq!(r, 2);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_s8() {
+         test_ari_s8(
+             |i, j| vadd_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_s8() {
+         testq_ari_s8(
+             |i, j| vaddq_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_s16() {
+         test_ari_s16(
+             |i, j| vadd_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_s16() {
+         testq_ari_s16(
+             |i, j| vaddq_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_s32() {
+         test_ari_s32(
+             |i, j| vadd_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_s32() {
+         testq_ari_s32(
+             |i, j| vaddq_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.overflowing_add(b).0 },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_u8() {
+         test_ari_u8(
+             |i, j| vadd_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_u8() {
+         testq_ari_u8(
+             |i, j| vaddq_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_u16() {
+         test_ari_u16(
+             |i, j| vadd_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_u16() {
+         testq_ari_u16(
+             |i, j| vaddq_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_u32() {
+         test_ari_u32(
+             |i, j| vadd_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.overflowing_add(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_u32() {
+         testq_ari_u32(
+             |i, j| vaddq_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.overflowing_add(b).0 },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vadd_f32() {
+         test_ari_f32(|i, j| vadd_f32(i, j), |a: f32, b: f32| -> f32 { a + b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddq_f32() {
+         testq_ari_f32(|i, j| vaddq_f32(i, j), |a: f32, b: f32| -> f32 { a + b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddl_s8() {
+         let v = i8::MAX;
+         let a = i8x8::new(v, v, v, v, v, v, v, v);
+         let v = 2 * (v as i16);
+         let e = i16x8::new(v, v, v, v, v, v, v, v);
+         let r: i16x8 = transmute(vaddl_s8(transmute(a), transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddl_s16() {
+         let v = i16::MAX;
+         let a = i16x4::new(v, v, v, v);
+         let v = 2 * (v as i32);
+         let e = i32x4::new(v, v, v, v);
+         let r: i32x4 = transmute(vaddl_s16(transmute(a), transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddl_s32() {
+         let v = i32::MAX;
+         let a = i32x2::new(v, v);
+         let v = 2 * (v as i64);
+         let e = i64x2::new(v, v);
+         let r: i64x2 = transmute(vaddl_s32(transmute(a), transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddl_u8() {
+         let v = u8::MAX;
+         let a = u8x8::new(v, v, v, v, v, v, v, v);
+         let v = 2 * (v as u16);
+         let e = u16x8::new(v, v, v, v, v, v, v, v);
+         let r: u16x8 = transmute(vaddl_u8(transmute(a), transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddl_u16() {
+         let v = u16::MAX;
+         let a = u16x4::new(v, v, v, v);
+         let v = 2 * (v as u32);
+         let e = u32x4::new(v, v, v, v);
+         let r: u32x4 = transmute(vaddl_u16(transmute(a), transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vaddl_u32() {
+         let v = u32::MAX;
+         let a = u32x2::new(v, v);
+         let v = 2 * (v as u64);
+         let e = u64x2::new(v, v);
+         let r: u64x2 = transmute(vaddl_u32(transmute(a), transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_s8() {
+         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e = i8x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
+         let r: i8x8 = transmute(vmvn_s8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_s8() {
+         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e = i8x16::new(
+             -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16,
+         );
+         let r: i8x16 = transmute(vmvnq_s8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_s16() {
+         let a = i16x4::new(0, 1, 2, 3);
+         let e = i16x4::new(-1, -2, -3, -4);
+         let r: i16x4 = transmute(vmvn_s16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_s16() {
+         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e = i16x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
+         let r: i16x8 = transmute(vmvnq_s16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_s32() {
+         let a = i32x2::new(0, 1);
+         let e = i32x2::new(-1, -2);
+         let r: i32x2 = transmute(vmvn_s32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_s32() {
+         let a = i32x4::new(0, 1, 2, 3);
+         let e = i32x4::new(-1, -2, -3, -4);
+         let r: i32x4 = transmute(vmvnq_s32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_u8() {
+         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
+         let r: u8x8 = transmute(vmvn_u8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_u8() {
+         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e = u8x16::new(
+             255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
+         );
+         let r: u8x16 = transmute(vmvnq_u8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_u16() {
+         let a = u16x4::new(0, 1, 2, 3);
+         let e = u16x4::new(65_535, 65_534, 65_533, 65_532);
+         let r: u16x4 = transmute(vmvn_u16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_u16() {
+         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e = u16x8::new(
+             65_535, 65_534, 65_533, 65_532, 65_531, 65_530, 65_529, 65_528,
+         );
+         let r: u16x8 = transmute(vmvnq_u16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_u32() {
+         let a = u32x2::new(0, 1);
+         let e = u32x2::new(4_294_967_295, 4_294_967_294);
+         let r: u32x2 = transmute(vmvn_u32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_u32() {
+         let a = u32x4::new(0, 1, 2, 3);
+         let e = u32x4::new(4_294_967_295, 4_294_967_294, 4_294_967_293, 4_294_967_292);
+         let r: u32x4 = transmute(vmvnq_u32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvn_p8() {
+         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
+         let r: u8x8 = transmute(vmvn_p8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmvnq_p8() {
+         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let e = u8x16::new(
+             255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
+         );
+         let r: u8x16 = transmute(vmvnq_p8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovn_s16() {
+         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r: i8x8 = transmute(vmovn_s16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovn_s32() {
+         let a = i32x4::new(1, 2, 3, 4);
+         let e = i16x4::new(1, 2, 3, 4);
+         let r: i16x4 = transmute(vmovn_s32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovn_s64() {
+         let a = i64x2::new(1, 2);
+         let e = i32x2::new(1, 2);
+         let r: i32x2 = transmute(vmovn_s64(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovn_u16() {
+         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r: u8x8 = transmute(vmovn_u16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovn_u32() {
+         let a = u32x4::new(1, 2, 3, 4);
+         let e = u16x4::new(1, 2, 3, 4);
+         let r: u16x4 = transmute(vmovn_u32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovn_u64() {
+         let a = u64x2::new(1, 2);
+         let e = u32x2::new(1, 2);
+         let r: u32x2 = transmute(vmovn_u64(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovl_s8() {
+         let e = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r: i16x8 = transmute(vmovl_s8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovl_s16() {
+         let e = i32x4::new(1, 2, 3, 4);
+         let a = i16x4::new(1, 2, 3, 4);
+         let r: i32x4 = transmute(vmovl_s16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovl_s32() {
+         let e = i64x2::new(1, 2);
+         let a = i32x2::new(1, 2);
+         let r: i64x2 = transmute(vmovl_s32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovl_u8() {
+         let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let r: u16x8 = transmute(vmovl_u8(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovl_u16() {
+         let e = u32x4::new(1, 2, 3, 4);
+         let a = u16x4::new(1, 2, 3, 4);
+         let r: u32x4 = transmute(vmovl_u16(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmovl_u32() {
+         let e = u64x2::new(1, 2);
+         let a = u32x2::new(1, 2);
+         let r: u64x2 = transmute(vmovl_u32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrsqrt_f32() {
+         let a = f32x2::new(1.0, 2.0);
+         let e = f32x2::new(0.9980469, 0.7050781);
+         let r: f32x2 = transmute(vrsqrte_f32(transmute(a)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_s8() {
+         let a = i8x8::new(1, -2, 3, -4, 5, 6, 7, 8);
+         let b = i8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = i8x8::new(-2, -4, 5, 7, 0, 2, 4, 6);
+         let r: i8x8 = transmute(vpmin_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_s16() {
+         let a = i16x4::new(1, 2, 3, -4);
+         let b = i16x4::new(0, 3, 2, 5);
+         let e = i16x4::new(1, -4, 0, 2);
+         let r: i16x4 = transmute(vpmin_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_s32() {
+         let a = i32x2::new(1, -2);
+         let b = i32x2::new(0, 3);
+         let e = i32x2::new(-2, 0);
+         let r: i32x2 = transmute(vpmin_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_u8() {
+         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = u8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = u8x8::new(1, 3, 5, 7, 0, 2, 4, 6);
+         let r: u8x8 = transmute(vpmin_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_u16() {
+         let a = u16x4::new(1, 2, 3, 4);
+         let b = u16x4::new(0, 3, 2, 5);
+         let e = u16x4::new(1, 3, 0, 2);
+         let r: u16x4 = transmute(vpmin_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_u32() {
+         let a = u32x2::new(1, 2);
+         let b = u32x2::new(0, 3);
+         let e = u32x2::new(1, 0);
+         let r: u32x2 = transmute(vpmin_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmin_f32() {
+         let a = f32x2::new(1., -2.);
+         let b = f32x2::new(0., 3.);
+         let e = f32x2::new(-2., 0.);
+         let r: f32x2 = transmute(vpmin_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_s8() {
+         let a = i8x8::new(1, -2, 3, -4, 5, 6, 7, 8);
+         let b = i8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = i8x8::new(1, 3, 6, 8, 3, 5, 7, 9);
+         let r: i8x8 = transmute(vpmax_s8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_s16() {
+         let a = i16x4::new(1, 2, 3, -4);
+         let b = i16x4::new(0, 3, 2, 5);
+         let e = i16x4::new(2, 3, 3, 5);
+         let r: i16x4 = transmute(vpmax_s16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_s32() {
+         let a = i32x2::new(1, -2);
+         let b = i32x2::new(0, 3);
+         let e = i32x2::new(1, 3);
+         let r: i32x2 = transmute(vpmax_s32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_u8() {
+         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = u8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
+         let e = u8x8::new(2, 4, 6, 8, 3, 5, 7, 9);
+         let r: u8x8 = transmute(vpmax_u8(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_u16() {
+         let a = u16x4::new(1, 2, 3, 4);
+         let b = u16x4::new(0, 3, 2, 5);
+         let e = u16x4::new(2, 4, 3, 5);
+         let r: u16x4 = transmute(vpmax_u16(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_u32() {
+         let a = u32x2::new(1, 2);
+         let b = u32x2::new(0, 3);
+         let e = u32x2::new(2, 3);
+         let r: u32x2 = transmute(vpmax_u32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpmax_f32() {
+         let a = f32x2::new(1., -2.);
+         let b = f32x2::new(0., 3.);
+         let e = f32x2::new(1., 3.);
+         let r: f32x2 = transmute(vpmax_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s8() {
+         test_bit_s8(|i, j| vand_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s8() {
+         testq_bit_s8(|i, j| vandq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s16() {
+         test_bit_s16(|i, j| vand_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s16() {
+         testq_bit_s16(|i, j| vandq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s32() {
+         test_bit_s32(|i, j| vand_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s32() {
+         testq_bit_s32(|i, j| vandq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_s64() {
+         test_bit_s64(|i, j| vand_s64(i, j), |a: i64, b: i64| -> i64 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_s64() {
+         testq_bit_s64(|i, j| vandq_s64(i, j), |a: i64, b: i64| -> i64 { a & b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u8() {
+         test_bit_u8(|i, j| vand_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u8() {
+         testq_bit_u8(|i, j| vandq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u16() {
+         test_bit_u16(|i, j| vand_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u16() {
+         testq_bit_u16(|i, j| vandq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u32() {
+         test_bit_u32(|i, j| vand_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u32() {
+         testq_bit_u32(|i, j| vandq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vand_u64() {
+         test_bit_u64(|i, j| vand_u64(i, j), |a: u64, b: u64| -> u64 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vandq_u64() {
+         testq_bit_u64(|i, j| vandq_u64(i, j), |a: u64, b: u64| -> u64 { a & b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s8() {
+         test_bit_s8(|i, j| vorr_s8(i, j), |a: i8, b: i8| -> i8 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s8() {
+         testq_bit_s8(|i, j| vorrq_s8(i, j), |a: i8, b: i8| -> i8 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s16() {
+         test_bit_s16(|i, j| vorr_s16(i, j), |a: i16, b: i16| -> i16 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s16() {
+         testq_bit_s16(|i, j| vorrq_s16(i, j), |a: i16, b: i16| -> i16 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s32() {
+         test_bit_s32(|i, j| vorr_s32(i, j), |a: i32, b: i32| -> i32 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s32() {
+         testq_bit_s32(|i, j| vorrq_s32(i, j), |a: i32, b: i32| -> i32 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_s64() {
+         test_bit_s64(|i, j| vorr_s64(i, j), |a: i64, b: i64| -> i64 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_s64() {
+         testq_bit_s64(|i, j| vorrq_s64(i, j), |a: i64, b: i64| -> i64 { a | b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u8() {
+         test_bit_u8(|i, j| vorr_u8(i, j), |a: u8, b: u8| -> u8 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u8() {
+         testq_bit_u8(|i, j| vorrq_u8(i, j), |a: u8, b: u8| -> u8 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u16() {
+         test_bit_u16(|i, j| vorr_u16(i, j), |a: u16, b: u16| -> u16 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u16() {
+         testq_bit_u16(|i, j| vorrq_u16(i, j), |a: u16, b: u16| -> u16 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u32() {
+         test_bit_u32(|i, j| vorr_u32(i, j), |a: u32, b: u32| -> u32 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u32() {
+         testq_bit_u32(|i, j| vorrq_u32(i, j), |a: u32, b: u32| -> u32 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorr_u64() {
+         test_bit_u64(|i, j| vorr_u64(i, j), |a: u64, b: u64| -> u64 { a | b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vorrq_u64() {
+         testq_bit_u64(|i, j| vorrq_u64(i, j), |a: u64, b: u64| -> u64 { a | b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s8() {
+         test_bit_s8(|i, j| veor_s8(i, j), |a: i8, b: i8| -> i8 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s8() {
+         testq_bit_s8(|i, j| veorq_s8(i, j), |a: i8, b: i8| -> i8 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s16() {
+         test_bit_s16(|i, j| veor_s16(i, j), |a: i16, b: i16| -> i16 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s16() {
+         testq_bit_s16(|i, j| veorq_s16(i, j), |a: i16, b: i16| -> i16 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s32() {
+         test_bit_s32(|i, j| veor_s32(i, j), |a: i32, b: i32| -> i32 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s32() {
+         testq_bit_s32(|i, j| veorq_s32(i, j), |a: i32, b: i32| -> i32 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_s64() {
+         test_bit_s64(|i, j| veor_s64(i, j), |a: i64, b: i64| -> i64 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_s64() {
+         testq_bit_s64(|i, j| veorq_s64(i, j), |a: i64, b: i64| -> i64 { a ^ b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u8() {
+         test_bit_u8(|i, j| veor_u8(i, j), |a: u8, b: u8| -> u8 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u8() {
+         testq_bit_u8(|i, j| veorq_u8(i, j), |a: u8, b: u8| -> u8 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u16() {
+         test_bit_u16(|i, j| veor_u16(i, j), |a: u16, b: u16| -> u16 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u16() {
+         testq_bit_u16(|i, j| veorq_u16(i, j), |a: u16, b: u16| -> u16 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u32() {
+         test_bit_u32(|i, j| veor_u32(i, j), |a: u32, b: u32| -> u32 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u32() {
+         testq_bit_u32(|i, j| veorq_u32(i, j), |a: u32, b: u32| -> u32 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veor_u64() {
+         test_bit_u64(|i, j| veor_u64(i, j), |a: u64, b: u64| -> u64 { a ^ b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_veorq_u64() {
+         testq_bit_u64(|i, j| veorq_u64(i, j), |a: u64, b: u64| -> u64 { a ^ b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s8() {
+         test_cmp_s8(
+             |i, j| vceq_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a == b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s8() {
+         testq_cmp_s8(
+             |i, j| vceqq_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a == b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s16() {
+         test_cmp_s16(
+             |i, j| vceq_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a == b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s16() {
+         testq_cmp_s16(
+             |i, j| vceqq_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a == b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_s32() {
+         test_cmp_s32(
+             |i, j| vceq_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a == b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_s32() {
+         testq_cmp_s32(
+             |i, j| vceqq_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a == b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u8() {
+         test_cmp_u8(
+             |i, j| vceq_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a == b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u8() {
+         testq_cmp_u8(
+             |i, j| vceqq_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a == b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u16() {
+         test_cmp_u16(
+             |i, j| vceq_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a == b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u16() {
+         testq_cmp_u16(
+             |i, j| vceqq_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a == b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_u32() {
+         test_cmp_u32(
+             |i, j| vceq_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a == b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_u32() {
+         testq_cmp_u32(
+             |i, j| vceqq_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a == b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceq_f32() {
+         test_cmp_f32(
+             |i, j| vcge_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a == b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vceqq_f32() {
+         testq_cmp_f32(
+             |i, j| vcgeq_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a == b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s8() {
+         test_cmp_s8(
+             |i, j| vcgt_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a > b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s8() {
+         testq_cmp_s8(
+             |i, j| vcgtq_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a > b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s16() {
+         test_cmp_s16(
+             |i, j| vcgt_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a > b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s16() {
+         testq_cmp_s16(
+             |i, j| vcgtq_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a > b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_s32() {
+         test_cmp_s32(
+             |i, j| vcgt_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a > b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_s32() {
+         testq_cmp_s32(
+             |i, j| vcgtq_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a > b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u8() {
+         test_cmp_u8(
+             |i, j| vcgt_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a > b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u8() {
+         testq_cmp_u8(
+             |i, j| vcgtq_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a > b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u16() {
+         test_cmp_u16(
+             |i, j| vcgt_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a > b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u16() {
+         testq_cmp_u16(
+             |i, j| vcgtq_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a > b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_u32() {
+         test_cmp_u32(
+             |i, j| vcgt_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a > b {
+                     0xFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_u32() {
+         testq_cmp_u32(
+             |i, j| vcgtq_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a > b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgt_f32() {
+         test_cmp_f32(
+             |i, j| vcgt_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a > b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgtq_f32() {
+         testq_cmp_f32(
+             |i, j| vcgtq_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a > b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s8() {
+         test_cmp_s8(
+             |i, j| vclt_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a < b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s8() {
+         testq_cmp_s8(
+             |i, j| vcltq_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a < b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s16() {
+         test_cmp_s16(
+             |i, j| vclt_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a < b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s16() {
+         testq_cmp_s16(
+             |i, j| vcltq_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a < b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_s32() {
+         test_cmp_s32(
+             |i, j| vclt_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a < b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_s32() {
+         testq_cmp_s32(
+             |i, j| vcltq_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a < b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u8() {
+         test_cmp_u8(
+             |i, j| vclt_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a < b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u8() {
+         testq_cmp_u8(
+             |i, j| vcltq_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a < b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u16() {
+         test_cmp_u16(
+             |i, j| vclt_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a < b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u16() {
+         testq_cmp_u16(
+             |i, j| vcltq_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a < b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_u32() {
+         test_cmp_u32(
+             |i, j| vclt_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a < b {
+                     0xFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_u32() {
+         testq_cmp_u32(
+             |i, j| vcltq_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a < b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vclt_f32() {
+         test_cmp_f32(
+             |i, j| vclt_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a < b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcltq_f32() {
+         testq_cmp_f32(
+             |i, j| vcltq_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a < b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s8() {
+         test_cmp_s8(
+             |i, j| vcle_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a <= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s8() {
+         testq_cmp_s8(
+             |i, j| vcleq_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a <= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s16() {
+         test_cmp_s16(
+             |i, j| vcle_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a <= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s16() {
+         testq_cmp_s16(
+             |i, j| vcleq_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a <= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_s32() {
+         test_cmp_s32(
+             |i, j| vcle_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a <= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_s32() {
+         testq_cmp_s32(
+             |i, j| vcleq_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a <= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u8() {
+         test_cmp_u8(
+             |i, j| vcle_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a <= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u8() {
+         testq_cmp_u8(
+             |i, j| vcleq_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a <= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u16() {
+         test_cmp_u16(
+             |i, j| vcle_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a <= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u16() {
+         testq_cmp_u16(
+             |i, j| vcleq_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a <= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_u32() {
+         test_cmp_u32(
+             |i, j| vcle_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a <= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_u32() {
+         testq_cmp_u32(
+             |i, j| vcleq_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a <= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcle_f32() {
+         test_cmp_f32(
+             |i, j| vcle_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a <= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcleq_f32() {
+         testq_cmp_f32(
+             |i, j| vcleq_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a <= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s8() {
+         test_cmp_s8(
+             |i, j| vcge_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a >= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s8() {
+         testq_cmp_s8(
+             |i, j| vcgeq_s8(i, j),
+             |a: i8, b: i8| -> u8 {
+                 if a >= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s16() {
+         test_cmp_s16(
+             |i, j| vcge_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a >= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s16() {
+         testq_cmp_s16(
+             |i, j| vcgeq_s16(i, j),
+             |a: i16, b: i16| -> u16 {
+                 if a >= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_s32() {
+         test_cmp_s32(
+             |i, j| vcge_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a >= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_s32() {
+         testq_cmp_s32(
+             |i, j| vcgeq_s32(i, j),
+             |a: i32, b: i32| -> u32 {
+                 if a >= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u8() {
+         test_cmp_u8(
+             |i, j| vcge_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a >= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u8() {
+         testq_cmp_u8(
+             |i, j| vcgeq_u8(i, j),
+             |a: u8, b: u8| -> u8 {
+                 if a >= b {
+                     0xFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u16() {
+         test_cmp_u16(
+             |i, j| vcge_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a >= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u16() {
+         testq_cmp_u16(
+             |i, j| vcgeq_u16(i, j),
+             |a: u16, b: u16| -> u16 {
+                 if a >= b {
+                     0xFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_u32() {
+         test_cmp_u32(
+             |i, j| vcge_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a >= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_u32() {
+         testq_cmp_u32(
+             |i, j| vcgeq_u32(i, j),
+             |a: u32, b: u32| -> u32 {
+                 if a >= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcge_f32() {
+         test_cmp_f32(
+             |i, j| vcge_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a >= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vcgeq_f32() {
+         testq_cmp_f32(
+             |i, j| vcgeq_f32(i, j),
+             |a: f32, b: f32| -> u32 {
+                 if a >= b {
+                     0xFFFFFFFF
+                 } else {
+                     0
+                 }
+             },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_s8() {
+         test_ari_s8(
+             |i, j| vqsub_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_s8() {
+         testq_ari_s8(
+             |i, j| vqsubq_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_s16() {
+         test_ari_s16(
+             |i, j| vqsub_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_s16() {
+         testq_ari_s16(
+             |i, j| vqsubq_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_s32() {
+         test_ari_s32(
+             |i, j| vqsub_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_s32() {
+         testq_ari_s32(
+             |i, j| vqsubq_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.saturating_sub(b) },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_u8() {
+         test_ari_u8(
+             |i, j| vqsub_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_u8() {
+         testq_ari_u8(
+             |i, j| vqsubq_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_u16() {
+         test_ari_u16(
+             |i, j| vqsub_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_u16() {
+         testq_ari_u16(
+             |i, j| vqsubq_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsub_u32() {
+         test_ari_u32(
+             |i, j| vqsub_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.saturating_sub(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqsubq_u32() {
+         testq_ari_u32(
+             |i, j| vqsubq_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.saturating_sub(b) },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_s8() {
+         test_ari_s8(|i, j| vhadd_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_s8() {
+         testq_ari_s8(|i, j| vhaddq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_s16() {
+         test_ari_s16(|i, j| vhadd_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_s16() {
+         testq_ari_s16(|i, j| vhaddq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_s32() {
+         test_ari_s32(|i, j| vhadd_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_s32() {
+         testq_ari_s32(|i, j| vhaddq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_u8() {
+         test_ari_u8(|i, j| vhadd_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_u8() {
+         testq_ari_u8(|i, j| vhaddq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_u16() {
+         test_ari_u16(|i, j| vhadd_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_u16() {
+         testq_ari_u16(|i, j| vhaddq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhadd_u32() {
+         test_ari_u32(|i, j| vhadd_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhaddq_u32() {
+         testq_ari_u32(|i, j| vhaddq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_s8() {
+         test_ari_s8(|i, j| vrhadd_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_s8() {
+         testq_ari_s8(|i, j| vrhaddq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_s16() {
+         test_ari_s16(|i, j| vrhadd_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_s16() {
+         testq_ari_s16(|i, j| vrhaddq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_s32() {
+         test_ari_s32(|i, j| vrhadd_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_s32() {
+         testq_ari_s32(|i, j| vrhaddq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_u8() {
+         test_ari_u8(|i, j| vrhadd_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_u8() {
+         testq_ari_u8(|i, j| vrhaddq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_u16() {
+         test_ari_u16(|i, j| vrhadd_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_u16() {
+         testq_ari_u16(|i, j| vrhaddq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhadd_u32() {
+         test_ari_u32(|i, j| vrhadd_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vrhaddq_u32() {
+         testq_ari_u32(|i, j| vrhaddq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_s8() {
+         test_ari_s8(
+             |i, j| vqadd_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_s8() {
+         testq_ari_s8(
+             |i, j| vqaddq_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_s16() {
+         test_ari_s16(
+             |i, j| vqadd_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_s16() {
+         testq_ari_s16(
+             |i, j| vqaddq_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_s32() {
+         test_ari_s32(
+             |i, j| vqadd_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_s32() {
+         testq_ari_s32(
+             |i, j| vqaddq_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.saturating_add(b) },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_u8() {
+         test_ari_u8(
+             |i, j| vqadd_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_u8() {
+         testq_ari_u8(
+             |i, j| vqaddq_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_u16() {
+         test_ari_u16(
+             |i, j| vqadd_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_u16() {
+         testq_ari_u16(
+             |i, j| vqaddq_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqadd_u32() {
+         test_ari_u32(
+             |i, j| vqadd_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.saturating_add(b) },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vqaddq_u32() {
+         testq_ari_u32(
+             |i, j| vqaddq_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.saturating_add(b) },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_s8() {
+         test_ari_s8(
+             |i, j| vmul_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_s8() {
+         testq_ari_s8(
+             |i, j| vmulq_s8(i, j),
+             |a: i8, b: i8| -> i8 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_s16() {
+         test_ari_s16(
+             |i, j| vmul_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_s16() {
+         testq_ari_s16(
+             |i, j| vmulq_s16(i, j),
+             |a: i16, b: i16| -> i16 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_s32() {
+         test_ari_s32(
+             |i, j| vmul_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_s32() {
+         testq_ari_s32(
+             |i, j| vmulq_s32(i, j),
+             |a: i32, b: i32| -> i32 { a.overflowing_mul(b).0 },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_u8() {
+         test_ari_u8(
+             |i, j| vmul_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_u8() {
+         testq_ari_u8(
+             |i, j| vmulq_u8(i, j),
+             |a: u8, b: u8| -> u8 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_u16() {
+         test_ari_u16(
+             |i, j| vmul_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_u16() {
+         testq_ari_u16(
+             |i, j| vmulq_u16(i, j),
+             |a: u16, b: u16| -> u16 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_u32() {
+         test_ari_u32(
+             |i, j| vmul_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.overflowing_mul(b).0 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_u32() {
+         testq_ari_u32(
+             |i, j| vmulq_u32(i, j),
+             |a: u32, b: u32| -> u32 { a.overflowing_mul(b).0 },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmul_f32() {
+         test_ari_f32(|i, j| vmul_f32(i, j), |a: f32, b: f32| -> f32 { a * b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmulq_f32() {
+         testq_ari_f32(|i, j| vmulq_f32(i, j), |a: f32, b: f32| -> f32 { a * b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s8() {
+         test_ari_s8(|i, j| vsub_s8(i, j), |a: i8, b: i8| -> i8 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s8() {
+         testq_ari_s8(|i, j| vsubq_s8(i, j), |a: i8, b: i8| -> i8 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s16() {
+         test_ari_s16(|i, j| vsub_s16(i, j), |a: i16, b: i16| -> i16 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s16() {
+         testq_ari_s16(|i, j| vsubq_s16(i, j), |a: i16, b: i16| -> i16 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_s32() {
+         test_ari_s32(|i, j| vsub_s32(i, j), |a: i32, b: i32| -> i32 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_s32() {
+         testq_ari_s32(|i, j| vsubq_s32(i, j), |a: i32, b: i32| -> i32 { a - b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u8() {
+         test_ari_u8(|i, j| vsub_u8(i, j), |a: u8, b: u8| -> u8 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u8() {
+         testq_ari_u8(|i, j| vsubq_u8(i, j), |a: u8, b: u8| -> u8 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u16() {
+         test_ari_u16(|i, j| vsub_u16(i, j), |a: u16, b: u16| -> u16 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u16() {
+         testq_ari_u16(|i, j| vsubq_u16(i, j), |a: u16, b: u16| -> u16 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_u32() {
+         test_ari_u32(|i, j| vsub_u32(i, j), |a: u32, b: u32| -> u32 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_u32() {
+         testq_ari_u32(|i, j| vsubq_u32(i, j), |a: u32, b: u32| -> u32 { a - b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsub_f32() {
+         test_ari_f32(|i, j| vsub_f32(i, j), |a: f32, b: f32| -> f32 { a - b });
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vsubq_f32() {
+         testq_ari_f32(|i, j| vsubq_f32(i, j), |a: f32, b: f32| -> f32 { a - b });
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_s8() {
+         test_ari_s8(
+             |i, j| vhsub_s8(i, j),
+             |a: i8, b: i8| -> i8 { (((a as i16) - (b as i16)) / 2) as i8 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_s8() {
+         testq_ari_s8(
+             |i, j| vhsubq_s8(i, j),
+             |a: i8, b: i8| -> i8 { (((a as i16) - (b as i16)) / 2) as i8 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_s16() {
+         test_ari_s16(
+             |i, j| vhsub_s16(i, j),
+             |a: i16, b: i16| -> i16 { (((a as i32) - (b as i32)) / 2) as i16 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_s16() {
+         testq_ari_s16(
+             |i, j| vhsubq_s16(i, j),
+             |a: i16, b: i16| -> i16 { (((a as i32) - (b as i32)) / 2) as i16 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_s32() {
+         test_ari_s32(
+             |i, j| vhsub_s32(i, j),
+             |a: i32, b: i32| -> i32 { (((a as i64) - (b as i64)) / 2) as i32 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_s32() {
+         testq_ari_s32(
+             |i, j| vhsubq_s32(i, j),
+             |a: i32, b: i32| -> i32 { (((a as i64) - (b as i64)) / 2) as i32 },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_u8() {
+         test_ari_u8(
+             |i, j| vhsub_u8(i, j),
+             |a: u8, b: u8| -> u8 { (((a as u16) - (b as u16)) / 2) as u8 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_u8() {
+         testq_ari_u8(
+             |i, j| vhsubq_u8(i, j),
+             |a: u8, b: u8| -> u8 { (((a as u16) - (b as u16)) / 2) as u8 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_u16() {
+         test_ari_u16(
+             |i, j| vhsub_u16(i, j),
+             |a: u16, b: u16| -> u16 { (((a as u16) - (b as u16)) / 2) as u16 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_u16() {
+         testq_ari_u16(
+             |i, j| vhsubq_u16(i, j),
+             |a: u16, b: u16| -> u16 { (((a as u16) - (b as u16)) / 2) as u16 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsub_u32() {
+         test_ari_u32(
+             |i, j| vhsub_u32(i, j),
+             |a: u32, b: u32| -> u32 { (((a as u64) - (b as u64)) / 2) as u32 },
+         );
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vhsubq_u32() {
+         testq_ari_u32(
+             |i, j| vhsubq_u32(i, j),
+             |a: u32, b: u32| -> u32 { (((a as u64) - (b as u64)) / 2) as u32 },
+         );
+     }
+ 
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vreinterpretq_s8_u8() {
+         let a = i8x16::new(-1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r: u8x16 = transmute(vreinterpretq_s8_u8(transmute(a)));
+         let e = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         assert_eq!(r, e)
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vreinterpretq_u16_u8() {
+         let a = u16x8::new(
+             0x01_00, 0x03_02, 0x05_04, 0x07_06, 0x09_08, 0x0B_0A, 0x0D_0C, 0x0F_0E,
+         );
+         let r: u8x16 = transmute(vreinterpretq_u16_u8(transmute(a)));
+         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq!(r, e)
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vreinterpretq_u32_u8() {
+         let a = u32x4::new(0x03_02_01_00, 0x07_06_05_04, 0x0B_0A_09_08, 0x0F_0E_0D_0C);
+         let r: u8x16 = transmute(vreinterpretq_u32_u8(transmute(a)));
+         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq!(r, e)
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vreinterpretq_u64_u8() {
+         let a: u64x2 = u64x2::new(0x07_06_05_04_03_02_01_00, 0x0F_0E_0D_0C_0B_0A_09_08);
+         let r: u8x16 = transmute(vreinterpretq_u64_u8(transmute(a)));
+         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq!(r, e)
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vreinterpretq_u8_s8() {
+         let a = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r: i8x16 = transmute(vreinterpretq_u8_s8(transmute(a)));
+         let e = i8x16::new(-1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         assert_eq!(r, e)
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabs_s8() {
+         let a = i8x8::new(-1, 0, 1, -2, 0, 2, -128, 127);
+         let r: i8x8 = transmute(vabs_s8(transmute(a)));
+         let e = i8x8::new(1, 0, 1, 2, 0, 2, -128, 127);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabsq_s8() {
+         let a = i8x16::new(-1, 0, 1, -2, 0, 2, -128, 127, -1, 0, 1, -2, 0, 2, -128, 127);
+         let r: i8x16 = transmute(vabsq_s8(transmute(a)));
+         let e = i8x16::new(1, 0, 1, 2, 0, 2, -128, 127, 1, 0, 1, 2, 0, 2, -128, 127);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabs_s16() {
+         let a = i16x4::new(-1, 0, i16::MIN, i16::MAX);
+         let r: i16x4 = transmute(vabs_s16(transmute(a)));
+         let e = i16x4::new(1, 0, i16::MIN, i16::MAX);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabsq_s16() {
+         let a = i16x8::new(-1, 0, i16::MIN, i16::MAX, -1, 0, i16::MIN, i16::MAX);
+         let r: i16x8 = transmute(vabsq_s16(transmute(a)));
+         let e = i16x8::new(1, 0, i16::MIN, i16::MAX, 1, 0, i16::MIN, i16::MAX);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabs_s32() {
+         let a = i32x2::new(i32::MIN, i32::MIN + 1);
+         let r: i32x2 = transmute(vabs_s32(transmute(a)));
+         let e = i32x2::new(i32::MIN, i32::MAX);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vabsq_s32() {
+         let a = i32x4::new(i32::MIN, i32::MIN + 1, 0, -1);
+         let r: i32x4 = transmute(vabsq_s32(transmute(a)));
+         let e = i32x4::new(i32::MIN, i32::MAX, 0, 1);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpadd_s16() {
+         let a = i16x4::new(1, 2, 3, 4);
+         let b = i16x4::new(0, -1, -2, -3);
+         let r: i16x4 = transmute(vpadd_s16(transmute(a), transmute(b)));
+         let e = i16x4::new(3, 7, -1, -5);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpadd_s32() {
+         let a = i32x2::new(1, 2);
+         let b = i32x2::new(0, -1);
+         let r: i32x2 = transmute(vpadd_s32(transmute(a), transmute(b)));
+         let e = i32x2::new(3, -1);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpadd_s8() {
+         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = i8x8::new(0, -1, -2, -3, -4, -5, -6, -7);
+         let r: i8x8 = transmute(vpadd_s8(transmute(a), transmute(b)));
+         let e = i8x8::new(3, 7, 11, 15, -1, -5, -9, -13);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpadd_u16() {
+         let a = u16x4::new(1, 2, 3, 4);
+         let b = u16x4::new(30, 31, 32, 33);
+         let r: u16x4 = transmute(vpadd_u16(transmute(a), transmute(b)));
+         let e = u16x4::new(3, 7, 61, 65);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpadd_u32() {
+         let a = u32x2::new(1, 2);
+         let b = u32x2::new(30, 31);
+         let r: u32x2 = transmute(vpadd_u32(transmute(a), transmute(b)));
+         let e = u32x2::new(3, 61);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vpadd_u8() {
+         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = u8x8::new(30, 31, 32, 33, 34, 35, 36, 37);
+         let r: u8x8 = transmute(vpadd_u8(transmute(a), transmute(b)));
+         let e = u8x8::new(3, 7, 11, 15, 61, 65, 69, 73);
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vminq_f32() {
+         let a = f32x4::new(1., -2., 3., -4.);
+         let b = f32x4::new(0., 3., 2., 8.);
+         let e = f32x4::new(0., -2., 2., -4.);
+         let r: f32x4 = transmute(vminq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+     #[simd_test(enable = "neon")]
+     unsafe fn test_vmaxq_f32() {
+         let a = f32x4::new(1., -2., 3., -4.);
+         let b = f32x4::new(0., 3., 2., 8.);
+         let e = f32x4::new(1., 3., 3., 8.);
+         let r: f32x4 = transmute(vmaxq_f32(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+     }
+ }
+ 
+ #[cfg(test)]
+ #[cfg(target_endian = "little")]
+ mod table_lookup_tests;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1042 ----
+ //! Tests for ARM+v7+neon table lookup (vtbl, vtbx) intrinsics.
+ //!
+ //! These are included in `{arm, aarch64}::neon`.
+ 
+ use super::*;
+ 
+ #[cfg(target_arch = "aarch64")]
+ use crate::core_arch::aarch64::*;
+ 
+ #[cfg(target_arch = "arm")]
+ use crate::core_arch::arm::*;
+ 
+ use crate::core_arch::simd::*;
+ use std::mem;
+ use stdarch_test::simd_test;
+ 
+ macro_rules! test_vtbl {
+     ($test_name:ident => $fn_id:ident:
+      - table[$table_t:ident]: [$($table_v:expr),*] |
+      $(- ctrl[$ctrl_t:ident]: [$($ctrl_v:expr),*] => [$($exp_v:expr),*])|*
+     ) => {
+         #[simd_test(enable = "neon")]
+         unsafe fn $test_name() {
+             // create table as array, and transmute it to
+             // arm's table type
+             let table: $table_t = mem::transmute([$($table_v),*]);
+ 
+             // For each control vector, perform a table lookup and
+             // verify the result:
+             $(
+                 {
+                     let ctrl: $ctrl_t = mem::transmute([$($ctrl_v),*]);
+                     let result = $fn_id(table, mem::transmute(ctrl));
+                     let result: $ctrl_t = mem::transmute(result);
+                     let expected: $ctrl_t = mem::transmute([$($exp_v),*]);
+                     assert_eq!(result, expected);
+                 }
+             )*
+         }
+     }
+ }
+ 
+ // ARM+v7+neon and AArch64+neon tests
+ 
+ test_vtbl!(
+     test_vtbl1_s8 => vtbl1_s8:
+     - table[int8x8_t]: [0_i8, -11, 2, 3, 4, 5, 6, 7] |
+     - ctrl[i8x8]: [3_i8, 4, 1, 6, 0, 2, 7, 5] => [3_i8, 4, -11, 6, 0, 2, 7, 5] |
+     - ctrl[i8x8]: [3_i8, 8, 1, -9, 10, 2, 15, 5] => [3_i8, 0, -11, 0, 0, 2, 0, 5]
+ );
+ 
+ test_vtbl!(
+     test_vtbl1_u8 => vtbl1_u8:
+     - table[uint8x8_t]: [0_u8, 1, 2, 3, 4, 5, 6, 7] |
+     - ctrl[u8x8]: [3_u8, 4, 1, 6, 0, 2, 7, 5] => [3_u8, 4, 1, 6, 0, 2, 7, 5] |
+     - ctrl[u8x8]: [3_u8, 8, 1, 9, 10, 2, 15, 5] => [3_u8, 0, 1, 0, 0, 2, 0, 5]
+ );
+ 
+ test_vtbl!(
+     test_vtbl1_p8 => vtbl1_p8:
+     - table[poly8x8_t]: [0_u8, 1, 2, 3, 4, 5, 6, 7] |
+     - ctrl[u8x8]: [3_u8, 4, 1, 6, 0, 2, 7, 5] => [3_u8, 4, 1, 6, 0, 2, 7, 5] |
+     - ctrl[u8x8]: [3_u8, 8, 1, 9, 10, 2, 15, 5] => [3_u8, 0, 1, 0, 0, 2, 0, 5]
+ );
+ 
+ test_vtbl!(
+     test_vtbl2_s8 => vtbl2_s8:
+     - table[int8x8x2_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121
+     ] |
+     - ctrl[i8x8]: [127_i8, 15, 1, 14, 2, 13, 3, 12] => [0_i8, -121, -17, -72, 34, -116, 51, -104] |
+     - ctrl[i8x8]: [4_i8, 11, 16, 10, 6, -19, 7, 18] => [68_i8, -117, 0, -84, 102, 0, 119, 0]
+ );
+ 
+ test_vtbl!(
+     test_vtbl2_u8 => vtbl2_u8:
+     - table[uint8x8x2_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         136, 153, 170, 187, 204, 221, 238, 255
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 14, 2, 13, 3, 12] => [0_u8, 255, 17, 238, 34, 221, 51, 204] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 19, 7, 18] => [68_u8, 187, 0, 170, 102, 0, 119, 0]
+ );
+ 
+ test_vtbl!(
+     test_vtbl2_p8 => vtbl2_p8:
+     - table[poly8x8x2_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         136, 153, 170, 187, 204, 221, 238, 255
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 14, 2, 13, 3, 12] => [0_u8, 255, 17, 238, 34, 221, 51, 204] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 19, 7, 18] => [68_u8, 187, 0, 170, 102, 0, 119, 0]
+ );
+ 
+ test_vtbl!(
+     test_vtbl3_s8 => vtbl3_s8:
+     - table[int8x8x3_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121,
+         0, 1, -2, 3, 4, -5, 6, 7
+     ] |
+     - ctrl[i8x8]: [127_i8, 15, 1, 19, 2, 13, 21, 12] => [0_i8, -121, -17, 3, 34, -116, -5, -104] |
+     - ctrl[i8x8]: [4_i8, 11, 16, 10, 6, -27, 7, 18] => [68_i8, -117, 0, -84, 102, 0, 119, -2]
+ );
+ 
+ test_vtbl!(
+     test_vtbl3_u8 => vtbl3_u8:
+     - table[uint8x8x3_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         136, 153, 170, 187, 204, 221, 238, 255,
+         0, 1, 2, 3, 4, 5, 6, 7
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 19, 2, 13, 21, 12] => [0_u8, 255, 17, 3, 34, 221, 5, 204] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 27, 7, 18] => [68_u8, 187, 0, 170, 102, 0, 119, 2]
+ );
+ 
+ test_vtbl!(
+     test_vtbl3_p8 => vtbl3_p8:
+     - table[poly8x8x3_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         136, 153, 170, 187, 204, 221, 238, 255,
+         0, 1, 2, 3, 4, 5, 6, 7
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 19, 2, 13, 21, 12] => [0_u8, 255, 17, 3, 34, 221, 5, 204] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 27, 7, 18] => [68_u8, 187, 0, 170, 102, 0, 119, 2]
+ );
+ 
+ test_vtbl!(
+     test_vtbl4_s8 => vtbl4_s8:
+     - table[int8x8x4_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121,
+         0, 1, -2, 3, 4, -5, 6, 7,
+         8, -9, 10, 11, 12, -13, 14, 15
+     ] |
+     - ctrl[i8x8]: [127_i8, 15, 1, 19, 2, 13, 25, 12] => [0_i8, -121, -17, 3, 34, -116, -9, -104] |
+     - ctrl[i8x8]: [4_i8, 11, 32, 10, -33, 27, 7, 18] => [68_i8, -117, 0, -84, 0, 11, 119, -2]
+ );
+ 
+ test_vtbl!(
+     test_vtbl4_u8 => vtbl4_u8:
+     - table[uint8x8x4_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         136, 153, 170, 187, 204, 221, 238, 255,
+         0, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 19, 2, 13, 21, 12] => [0_u8, 255, 17, 3, 34, 221, 5, 204] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 27, 7, 18] => [68_u8, 187, 0, 170, 102, 11, 119, 2]
+ );
+ 
+ test_vtbl!(
+     test_vtbl4_p8 => vtbl4_p8:
+     - table[poly8x8x4_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         136, 153, 170, 187, 204, 221, 238, 255,
+         0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 19, 2, 13, 21, 12] => [0_u8, 255, 17, 3, 34, 221, 5, 204] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 27, 7, 18] => [68_u8, 187, 0, 170, 102, 11, 119, 2]
+ );
+ 
+ macro_rules! test_vtbx {
+     ($test_name:ident => $fn_id:ident:
+      - table[$table_t:ident]: [$($table_v:expr),*] |
+      - ext[$ext_t:ident]: [$($ext_v:expr),*] |
+      $(- ctrl[$ctrl_t:ident]: [$($ctrl_v:expr),*] => [$($exp_v:expr),*])|*
+     ) => {
+         #[simd_test(enable = "neon")]
+         unsafe fn $test_name() {
+             // create table as array, and transmute it to
+             // arm's table type
+             let table: $table_t = mem::transmute([$($table_v),*]);
+             let ext: $ext_t = mem::transmute([$($ext_v),*]);
+ 
+             // For each control vector, perform a table lookup and
+             // verify the result:
+             $(
+                 {
+                     let ctrl: $ctrl_t = mem::transmute([$($ctrl_v),*]);
+                     let result = $fn_id(ext, table, mem::transmute(ctrl));
+                     let result: $ctrl_t = mem::transmute(result);
+                     let expected: $ctrl_t = mem::transmute([$($exp_v),*]);
+                     assert_eq!(result, expected);
+                 }
+             )*
+         }
+     }
+ }
+ 
+ test_vtbx!(
+     test_vtbx1_s8 => vtbx1_s8:
+     - table[int8x8_t]: [0_i8, 1, 2, -3, 4, 5, 6, 7] |
+     - ext[int8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[i8x8]: [3_i8, 4, 1, 6, 0, 2, 7, 5] => [-3_i8, 4, 1, 6, 0, 2, 7, 5] |
+     - ctrl[i8x8]: [3_i8, 8, 1, 9, 10, 2, -15, 5] => [-3_i8, 51, 1, 53, 54, 2, 56, 5]
+ );
+ 
+ test_vtbx!(
+     test_vtbx1_u8 => vtbx1_u8:
+     - table[uint8x8_t]: [0_u8, 1, 2, 3, 4, 5, 6, 7] |
+     - ext[uint8x8_t]: [50_u8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 4, 1, 6, 0, 2, 7, 5] => [3_u8, 4, 1, 6, 0, 2, 7, 5] |
+     - ctrl[u8x8]: [3_u8, 8, 1, 9, 10, 2, 15, 5] => [3_u8, 51, 1, 53, 54, 2, 56, 5]
+ );
+ 
+ test_vtbx!(
+     test_vtbx1_p8 => vtbx1_p8:
+     - table[poly8x8_t]: [0_u8, 1, 2, 3, 4, 5, 6, 7] |
+     - ext[poly8x8_t]: [50_u8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 4, 1, 6, 0, 2, 7, 5] => [3_u8, 4, 1, 6, 0, 2, 7, 5] |
+     - ctrl[u8x8]: [3_u8, 8, 1, 9, 10, 2, 15, 5] => [3_u8, 51, 1, 53, 54, 2, 56, 5]
+ );
+ 
+ test_vtbx!(
+     test_vtbx2_s8 => vtbx2_s8:
+     - table[int8x8x2_t]: [0_i8, 1, 2, -3, 4, 5, 6, 7, 8, 9, -10, 11, 12, -13, 14, 15] |
+     - ext[int8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[i8x8]: [3_i8, 4, 1, 6, 10, 2, 7, 15] => [-3_i8, 4, 1, 6, -10, 2, 7, 15] |
+     - ctrl[i8x8]: [3_i8, 8, 1, 10, 17, 2, 15, -19] => [-3_i8, 8, 1, -10, 54, 2, 15, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx2_u8 => vtbx2_u8:
+     - table[uint8x8x2_t]: [0_i8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] |
+     - ext[uint8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 4, 1, 6, 10, 2, 7, 15] => [3_i8, 4, 1, 6, 10, 2, 7, 15] |
+     - ctrl[u8x8]: [3_u8, 8, 1, 10, 17, 2, 15, 19] => [3_i8, 8, 1, 10, 54, 2, 15, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx2_p8 => vtbx2_p8:
+     - table[poly8x8x2_t]: [0_i8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] |
+     - ext[poly8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 4, 1, 6, 10, 2, 7, 15] => [3_i8, 4, 1, 6, 10, 2, 7, 15] |
+     - ctrl[u8x8]: [3_u8, 8, 1, 10, 17, 2, 15, 19] => [3_i8, 8, 1, 10, 54, 2, 15, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx3_s8 => vtbx3_s8:
+     - table[int8x8x3_t]: [
+         0_i8, 1, 2, -3, 4, 5, 6, 7,
+         8, 9, -10, 11, 12, -13, 14, 15,
+         16, -17, 18, 19, 20, 21, 22, 23 ] |
+     - ext[int8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[i8x8]: [3_i8, 4, 17, 22, 10, 2, 7, 15] => [-3_i8, 4, -17, 22, -10, 2, 7, 15] |
+     - ctrl[i8x8]: [3_i8, 8, 17, 10, 37, 2, 19, -29] => [-3_i8, 8, -17, -10, 54, 2, 19, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx3_u8 => vtbx3_u8:
+     - table[uint8x8x3_t]: [
+         0_i8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23 ] |
+     - ext[uint8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 4, 17, 22, 10, 2, 7, 15] => [3_i8, 4, 17, 22, 10, 2, 7, 15] |
+     - ctrl[u8x8]: [3_u8, 8, 17, 10, 37, 2, 19, 29] => [3_i8, 8, 17, 10, 54, 2, 19, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx3_p8 => vtbx3_p8:
+     - table[poly8x8x3_t]: [
+         0_i8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23 ] |
+     - ext[poly8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 4, 17, 22, 10, 2, 7, 15] => [3_i8, 4, 17, 22, 10, 2, 7, 15] |
+     - ctrl[u8x8]: [3_u8, 8, 17, 10, 37, 2, 19, 29] => [3_i8, 8, 17, 10, 54, 2, 19, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx4_s8 => vtbx4_s8:
+     - table[int8x8x4_t]: [
+         0_i8, 1, 2, -3, 4, 5, 6, 7,
+         8, 9, -10, 11, 12, -13, 14, 15,
+         16, -17, 18, 19, 20, 21, 22, 23,
+         -24, 25, 26, -27, 28, -29, 30, 31] |
+     - ext[int8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[i8x8]: [3_i8, 31, 17, 22, 10, 29, 7, 15] => [-3_i8, 31, -17, 22, -10, -29, 7, 15] |
+     - ctrl[i8x8]: [3_i8, 8, 17, 10, 37, 2, 19, -42] => [-3_i8, 8, -17, -10, 54, 2, 19, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx4_u8 => vtbx4_u8:
+     - table[uint8x8x4_t]: [
+         0_i8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31] |
+     - ext[uint8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 31, 17, 22, 10, 29, 7, 15] => [3_i8, 31, 17, 22, 10, 29, 7, 15] |
+     - ctrl[u8x8]: [3_u8, 8, 17, 10, 37, 2, 19, 42] => [3_i8, 8, 17, 10, 54, 2, 19, 57]
+ );
+ 
+ test_vtbx!(
+     test_vtbx4_p8 => vtbx4_p8:
+     - table[poly8x8x4_t]: [
+         0_i8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31] |
+     - ext[poly8x8_t]: [50_i8, 51, 52, 53, 54, 55, 56, 57] |
+     - ctrl[u8x8]: [3_u8, 31, 17, 22, 10, 29, 7, 15] => [3_i8, 31, 17, 22, 10, 29, 7, 15] |
+     - ctrl[u8x8]: [3_u8, 8, 17, 10, 37, 2, 19, 42] => [3_i8, 8, 17, 10, 54, 2, 19, 57]
+ );
+ 
+ // Aarch64 tests
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl1_s8 => vqtbl1_s8:
+     - table[int8x16_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121
+     ] |
+     - ctrl[i8x8]: [127_i8, 15, 1, 14, 2, 13, 3, 12] => [0_i8, -121, -17, -72, 34, -116, 51, -104] |
+     - ctrl[i8x8]: [4_i8, 11, 16, 10, 6, 19, 7, 18] => [68_i8, -117, 0, -84, 102, 0, 119, 0]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl1q_s8 => vqtbl1q_s8:
+     - table[int8x16_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121
+     ] |
+     - ctrl[i8x16]: [127_i8, 15, 1, 14, 2, 13, 3, 12, 4_i8, 11, 16, 10, 6, 19, 7, 18]
+         => [0_i8, -121, -17, -72, 34, -116, 51, -104, 68, -117, 0, -84, 102, 0, 119, 0]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl1_u8 => vqtbl1_u8:
+     - table[uint8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 14, 2, 13, 3, 12] => [0_u8, 121, 17, 72, 34, 116, 51, 104] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 19, 7, 18] => [68_u8, 117, 0, 84, 102, 0, 119, 0]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl1q_u8 => vqtbl1q_u8:
+     - table[uint8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ctrl[u8x16]: [127_u8, 15, 1, 14, 2, 13, 3, 12, 4_u8, 11, 16, 10, 6, 19, 7, 18]
+         => [0_u8, 121, 17, 72, 34, 116, 51, 104, 68, 117, 0, 84, 102, 0, 119, 0]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl1_p8 => vqtbl1_p8:
+     - table[poly8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 14, 2, 13, 3, 12] => [0_u8, 121, 17, 72, 34, 116, 51, 104] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 19, 7, 18] => [68_u8, 117, 0, 84, 102, 0, 119, 0]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl1q_p8 => vqtbl1q_p8:
+     - table[poly8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ctrl[u8x16]: [127_u8, 15, 1, 14, 2, 13, 3, 12, 4_u8, 11, 16, 10, 6, 19, 7, 18]
+         => [0_u8, 121, 17, 72, 34, 116, 51, 104, 68, 117, 0, 84, 102, 0, 119, 0]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl2_s8 => vqtbl2_s8:
+     - table[int8x16x2_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31
+     ] |
+     - ctrl[i8x8]: [80_i8, 15, 1, 24, 2, 13, 3, 29] => [0_i8, -15, -1, 24, 2, -13, -3, -29] |
+     - ctrl[i8x8]: [4_i8, 31, 32, 10, 6, 49, 7, 18] => [4_i8, -31, 0, 10, 6, 0, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl2q_s8 => vqtbl2q_s8:
+     - table[int8x16x2_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31
+     ] |
+     - ctrl[i8x16]: [80_i8, 15, 1, 24, 2, 13, 3, 29, 4_i8, 31, 32, 10, 6, 49, 7, 18]
+         => [0_i8, -15, -1, 24, 2, -13, -3, -29, 4, -31, 0, 10, 6, 0, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl2_u8 => vqtbl2_u8:
+     - table[uint8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [0_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 31, 32, 10, 6, 49, 7, 18] => [4_u8, 31, 0, 10, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl2q_u8 => vqtbl2q_u8:
+     - table[uint8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 31, 32, 10, 6, 49, 7, 18]
+         => [0_u8, 15, 1, 24, 2, 13, 3, 29, 4, 31, 0, 10, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl2_p8 => vqtbl2_p8:
+     - table[poly8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [0_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 31, 32, 10, 6, 49, 7, 18] => [4_u8, 31, 0, 10, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl2q_p8 => vqtbl2q_p8:
+     - table[poly8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 31, 32, 10, 6, 49, 7, 18]
+         => [0_u8, 15, 1, 24, 2, 13, 3, 29, 4, 31, 0, 10, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl3_s8 => vqtbl3_s8:
+     - table[int8x16x3_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47
+     ] |
+     - ctrl[i8x8]: [80_i8, 15, 1, 24, 2, 13, 3, 29] => [0_i8, -15, -1, 24, 2, -13, -3, -29] |
+     - ctrl[i8x8]: [4_i8, 32, 46, 51, 6, 49, 7, 18] => [4_i8, 32, 46, 0, 6, 0, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl3q_s8 => vqtbl3q_s8:
+     - table[int8x16x3_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47
+     ] |
+     - ctrl[i8x16]: [80_i8, 15, 1, 24, 2, 13, 3, 29, 4_i8, 32, 46, 51, 6, 49, 7, 18]
+         => [0_i8, -15, -1, 24, 2, -13, -3, -29, 4, 32, 46, 0, 6, 0, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl3_u8 => vqtbl3_u8:
+     - table[uint8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [0_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 32, 46, 51, 6, 49, 7, 18] => [4_u8, 32, 46, 0, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl3q_u8 => vqtbl3q_u8:
+     - table[uint8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 32, 46, 51, 6, 49, 7, 18]
+         => [0_u8, 15, 1, 24, 2, 13, 3, 29, 4, 32, 46, 0, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl3_p8 => vqtbl3_p8:
+     - table[poly8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [0_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 32, 46, 51, 6, 49, 7, 18] => [4_u8, 32, 46, 0, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl3q_p8 => vqtbl3q_p8:
+     - table[poly8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 32, 46, 51, 6, 49, 7, 18]
+         => [0_u8, 15, 1, 24, 2, 13, 3, 29, 4, 32, 46, 0, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl4_s8 => vqtbl4_s8:
+     - table[int8x16x4_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47,
+         48, -49, 50, -51, 52, -53, 54, -55,
+         56, -57, 58, -59, 60, -61, 62, -63
+     ] |
+     - ctrl[i8x8]: [80_i8, 15, 1, 24, 2, 13, 3, 29] => [0_i8, -15, -1, 24, 2, -13, -3, -29] |
+     - ctrl[i8x8]: [4_i8, 46, 64, 51, 6, 71, 7, 18] => [4_i8, 46, 0, -51, 6, 0, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl4q_s8 => vqtbl4q_s8:
+     - table[int8x16x4_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47,
+         48, -49, 50, -51, 52, -53, 54, -55,
+         56, -57, 58, -59, 60, -61, 62, -63
+     ] |
+     - ctrl[i8x16]: [80_i8, 15, 1, 24, 2, 13, 3, 29, 4_i8, 46, 64, 51, 6, 71, 7, 18]
+         => [0_i8, -15, -1, 24, 2, -13, -3, -29, 4, 46, 0, -51, 6, 0, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl4_u8 => vqtbl4_u8:
+     - table[uint8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [0_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 46, 64, 51, 6, 71, 7, 18] => [4_u8, 46, 0, 51, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl4q_u8 => vqtbl4q_u8:
+     - table[uint8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 46, 64, 51, 6, 71, 7, 18]
+         => [0_u8, 15, 1, 24, 2, 13, 3, 29, 4, 46, 0, 51, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl4_p8 => vqtbl4_p8:
+     - table[poly8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [0_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 46, 64, 51, 6, 71, 7, 18] => [4_u8, 46, 0, 51, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbl!(
+     test_vqtbl4q_p8 => vqtbl4q_p8:
+     - table[poly8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 46, 64, 51, 6, 71, 7, 18]
+         => [0_u8, 15, 1, 24, 2, 13, 3, 29, 4, 46, 0, 51, 6, 0, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx1_s8 => vqtbx1_s8:
+     - table[int8x16_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121
+     ] |
+     - ext[int8x8_t]: [100_i8, -101, 102, -103, 104, -105, 106, -107] |
+     - ctrl[i8x8]: [127_i8, 15, 1, 14, 2, 13, 3, 12] => [100_i8, -121, -17, -72, 34, -116, 51, -104] |
+     - ctrl[i8x8]: [4_i8, 11, 16, 10, 6, 19, 7, 18] => [68_i8, -117, 102, -84, 102, -105, 119, -107]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx1q_s8 => vqtbx1q_s8:
+     - table[int8x16_t]: [
+         0_i8, -17, 34, 51, 68, 85, 102, 119,
+         -106, -93, -84, -117, -104, -116, -72, -121
+     ] |
+     - ext[int8x16_t]: [
+         100_i8, -101, 102, -103, 104, -105, 106, -107,
+         108, -109, 110, -111, 112, -113, 114, -115
+     ] |
+     - ctrl[i8x16]: [127_i8, 15, 1, 14, 2, 13, 3, 12, 4_i8, 11, 16, 10, 6, 19, 7, 18]
+         => [100_i8, -121, -17, -72, 34, -116, 51, -104, 68, -117, 110, -84, 102, -113, 119, -115]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx1_u8 => vqtbx1_u8:
+     - table[uint8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ext[uint8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 14, 2, 13, 3, 12] => [100_u8, 121, 17, 72, 34, 116, 51, 104] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 19, 7, 18] => [68_u8, 117, 102, 84, 102, 105, 119, 107]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx1q_u8 => vqtbx1q_u8:
+     - table[uint8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ext[uint8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [127_u8, 15, 1, 14, 2, 13, 3, 12, 4_u8, 11, 16, 10, 6, 19, 7, 18]
+         => [100_u8, 121, 17, 72, 34, 116, 51, 104, 68, 117, 110, 84, 102, 113, 119, 115]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx1_p8 => vqtbx1_p8:
+     - table[poly8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ext[poly8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [127_u8, 15, 1, 14, 2, 13, 3, 12] => [100_u8, 121, 17, 72, 34, 116, 51, 104] |
+     - ctrl[u8x8]: [4_u8, 11, 16, 10, 6, 19, 7, 18] => [68_u8, 117, 102, 84, 102, 105, 119, 107]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx1q_p8 => vqtbx1q_p8:
+     - table[poly8x16_t]: [
+         0_u8, 17, 34, 51, 68, 85, 102, 119,
+         106, 93, 84, 117, 104, 116, 72, 121
+     ] |
+     - ext[poly8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [127_u8, 15, 1, 14, 2, 13, 3, 12, 4_u8, 11, 16, 10, 6, 19, 7, 18]
+         => [100_u8, 121, 17, 72, 34, 116, 51, 104, 68, 117, 110, 84, 102, 113, 119, 115]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx2_s8 => vqtbx2_s8:
+     - table[int8x16x2_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31
+     ] |
+     - ext[int8x8_t]: [100_i8, -101, 102, -103, 104, -105, 106, -107] |
+     - ctrl[i8x8]: [80_i8, 15, 1, 24, 2, 13, 3, 29] => [100_i8, -15, -1, 24, 2, -13, -3, -29] |
+     - ctrl[i8x8]: [4_i8, 31, 32, 10, 6, 49, 7, 18] => [4_i8, -31, 102, 10, 6, -105, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx2q_s8 => vqtbx2q_s8:
+     - table[int8x16x2_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31
+     ] |
+     - ext[int8x16_t]: [
+         100_i8, -101, 102, -103, 104, -105, 106, -107,
+         108, -109, 110, -111, 112, -113, 114, -115
+     ] |
+     - ctrl[i8x16]: [80_i8, 15, 1, 24, 2, 13, 3, 29, 4_i8, 31, 32, 10, 6, 49, 7, 18]
+         => [100_i8, -15, -1, 24, 2, -13, -3, -29, 4, -31, 110, 10, 6, -113, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx2_u8 => vqtbx2_u8:
+     - table[uint8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ext[uint8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [100_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 31, 32, 10, 6, 49, 7, 18] => [4_u8, 31, 102, 10, 6, 105, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx2q_u8 => vqtbx2q_u8:
+     - table[uint8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ext[uint8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 31, 32, 10, 6, 49, 7, 18]
+         => [100_u8, 15, 1, 24, 2, 13, 3, 29, 4, 31, 110, 10, 6, 113, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx2_p8 => vqtbx2_p8:
+     - table[poly8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ext[poly8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [100_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 31, 32, 10, 6, 49, 7, 18] => [4_u8, 31, 102, 10, 6, 105, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx2q_p8 => vqtbx2q_p8:
+     - table[poly8x16x2_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31
+     ] |
+     - ext[poly8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 31, 32, 10, 6, 49, 7, 18]
+         => [100_u8, 15, 1, 24, 2, 13, 3, 29, 4, 31, 110, 10, 6, 113, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx3_s8 => vqtbx3_s8:
+     - table[int8x16x3_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47
+     ] |
+     - ext[int8x8_t]: [100_i8, -101, 102, -103, 104, -105, 106, -107] |
+     - ctrl[i8x8]: [80_i8, 15, 1, 24, 2, 13, 3, 29] => [100_i8, -15, -1, 24, 2, -13, -3, -29] |
+     - ctrl[i8x8]: [4_i8, 32, 46, 51, 6, 49, 7, 18] => [4_i8, 32, 46, -103, 6, -105, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx3q_s8 => vqtbx3q_s8:
+     - table[int8x16x3_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47
+     ] |
+     - ext[int8x16_t]: [
+         100_i8, -101, 102, -103, 104, -105, 106, -107,
+         108, -109, 110, -111, 112, -113, 114, -115
+     ] |
+     - ctrl[i8x16]: [80_i8, 15, 1, 24, 2, 13, 3, 29, 4_i8, 32, 46, 51, 6, 49, 7, 18]
+         => [100_i8, -15, -1, 24, 2, -13, -3, -29, 4, 32, 46, -111, 6, -113, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx3_u8 => vqtbx3_u8:
+     - table[uint8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ext[uint8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [100_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 32, 46, 51, 6, 49, 7, 18] => [4_u8, 32, 46, 103, 6, 105, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx3q_u8 => vqtbx3q_u8:
+     - table[uint8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ext[uint8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 32, 46, 51, 6, 49, 7, 18]
+         => [100_u8, 15, 1, 24, 2, 13, 3, 29, 4, 32, 46, 111, 6, 113, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx3_p8 => vqtbx3_p8:
+     - table[poly8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ext[poly8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [100_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 32, 46, 51, 6, 49, 7, 18] => [4_u8, 32, 46, 103, 6, 105, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx3q_p8 => vqtbx3q_p8:
+     - table[poly8x16x3_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47
+     ] |
+     - ext[poly8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 32, 46, 51, 6, 49, 7, 18]
+         => [100_u8, 15, 1, 24, 2, 13, 3, 29, 4, 32, 46, 111, 6, 113, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx4_s8 => vqtbx4_s8:
+     - table[int8x16x4_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47,
+         48, -49, 50, -51, 52, -53, 54, -55,
+         56, -57, 58, -59, 60, -61, 62, -63
+     ] |
+     - ext[int8x8_t]: [100_i8, -101, 102, -103, 104, -105, 106, -107] |
+     - ctrl[i8x8]: [80_i8, 15, 1, 24, 2, 13, 3, 29] => [100_i8, -15, -1, 24, 2, -13, -3, -29] |
+     - ctrl[i8x8]: [4_i8, 46, 64, 51, 6, 71, 7, 18] => [4_i8, 46, 102, -51, 6, -105, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx4q_s8 => vqtbx4q_s8:
+     - table[int8x16x4_t]: [
+         0_i8, -1, 2, -3, 4, -5, 6, -7,
+         8, -9, 10, -11, 12, -13, 14, -15,
+         16, -17, 18, -19, 20, -21, 22, -23,
+         24, -25, 26, -27, 28, -29, 30, -31,
+         32, -33, 34, -35, 36, -37, 38, -39,
+         40, -41, 42, -43, 44, -45, 46, -47,
+         48, -49, 50, -51, 52, -53, 54, -55,
+         56, -57, 58, -59, 60, -61, 62, -63
+     ] |
+     - ext[int8x16_t]: [
+         100_i8, -101, 102, -103, 104, -105, 106, -107,
+         108, -109, 110, -111, 112, -113, 114, -115
+     ] |
+     - ctrl[i8x16]: [80_i8, 15, 1, 24, 2, 13, 3, 29, 4_i8, 46, 64, 51, 6, 71, 7, 18]
+         => [100_i8, -15, -1, 24, 2, -13, -3, -29, 4, 46, 110, -51, 6, -113, -7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx4_u8 => vqtbx4_u8:
+     - table[uint8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ext[uint8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [100_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 46, 64, 51, 6, 71, 7, 18] => [4_u8, 46, 102, 51, 6, 105, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx4q_u8 => vqtbx4q_u8:
+     - table[uint8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ext[uint8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 46, 64, 51, 6, 71, 7, 18]
+         => [100_u8, 15, 1, 24, 2, 13, 3, 29, 4, 46, 110, 51, 6, 113, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx4_p8 => vqtbx4_p8:
+     - table[poly8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ext[poly8x8_t]: [100_u8, 101, 102, 103, 104, 105, 106, 107] |
+     - ctrl[u8x8]: [80_u8, 15, 1, 24, 2, 13, 3, 29] => [100_u8, 15, 1, 24, 2, 13, 3, 29] |
+     - ctrl[u8x8]: [4_u8, 46, 64, 51, 6, 71, 7, 18] => [4_u8, 46, 102, 51, 6, 105, 7, 18]
+ );
+ 
+ #[cfg(target_arch = "aarch64")]
+ test_vtbx!(
+     test_vqtbx4q_p8 => vqtbx4q_p8:
+     - table[poly8x16x4_t]: [
+         0_u8, 1, 2, 3, 4, 5, 6, 7,
+         8, 9, 10, 11, 12, 13, 14, 15,
+         16, 17, 18, 19, 20, 21, 22, 23,
+         24, 25, 26, 27, 28, 29, 30, 31,
+         32, 33, 34, 35, 36, 37, 38, 39,
+         40, 41, 42, 43, 44, 45, 46, 47,
+         48, 49, 50, 51, 52, 53, 54, 55,
+         56, 57, 58, 59, 60, 61, 62, 63
+     ] |
+     - ext[poly8x16_t]: [
+         100_u8, 101, 102, 103, 104, 105, 106, 107,
+         108, 109, 110, 111, 112, 113, 114, 115
+     ] |
+     - ctrl[u8x16]: [80_u8, 15, 1, 24, 2, 13, 3, 29, 4_u8, 46, 64, 51, 6, 71, 7, 18]
+         => [100_u8, 15, 1, 24, 2, 13, 3, 29, 4, 46, 110, 51, 6, 113, 7, 18]
+ );
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,830 ----
+ use crate::core_arch::{arm::*, simd::*};
+ use std::{i16, i32, i8, mem::transmute, u16, u32, u8, vec::Vec};
+ 
+ macro_rules! V_u8 {
+     () => {
+         vec![0x00u8, 0x01u8, 0x02u8, 0x0Fu8, 0x80u8, 0xF0u8, 0xFFu8]
+     };
+ }
+ macro_rules! V_u16 {
+     () => {
+         vec![
+             0x0000u16, 0x0101u16, 0x0202u16, 0x0F0Fu16, 0x8000u16, 0xF0F0u16, 0xFFFFu16,
+         ]
+     };
+ }
+ macro_rules! V_u32 {
+     () => {
+         vec![
+             0x00000000u32,
+             0x01010101u32,
+             0x02020202u32,
+             0x0F0F0F0Fu32,
+             0x80000000u32,
+             0xF0F0F0F0u32,
+             0xFFFFFFFFu32,
+         ]
+     };
+ }
+ macro_rules! V_u64 {
+     () => {
+         vec![
+             0x0000000000000000u64,
+             0x0101010101010101u64,
+             0x0202020202020202u64,
+             0x0F0F0F0F0F0F0F0Fu64,
+             0x8080808080808080u64,
+             0xF0F0F0F0F0F0F0F0u64,
+             0xFFFFFFFFFFFFFFFFu64,
+         ]
+     };
+ }
+ 
+ macro_rules! V_i8 {
+     () => {
+         vec![
+             0x00i8, 0x01i8, 0x02i8, 0x0Fi8, -128i8, /* 0x80 */
+             -16i8,  /* 0xF0 */
+             -1i8,   /* 0xFF */
+         ]
+     };
+ }
+ macro_rules! V_i16 {
+     () => {
+         vec![
+             0x0000i16, 0x0101i16, 0x0202i16, 0x0F0Fi16, -32768i16, /* 0x8000 */
+             -3856i16,  /* 0xF0F0 */
+             -1i16,     /* 0xFFF */
+         ]
+     };
+ }
+ macro_rules! V_i32 {
+     () => {
+         vec![
+             0x00000000i32,
+             0x01010101i32,
+             0x02020202i32,
+             0x0F0F0F0Fi32,
+             -2139062144i32, /* 0x80000000 */
+             -252645136i32,  /* 0xF0F0F0F0 */
+             -1i32,          /* 0xFFFFFFFF */
+         ]
+     };
+ }
+ 
+ macro_rules! V_i64 {
+     () => {
+         vec![
+             0x0000000000000000i64,
+             0x0101010101010101i64,
+             0x0202020202020202i64,
+             0x0F0F0F0F0F0F0F0Fi64,
+             -9223372036854775808i64, /* 0x8000000000000000 */
+             -1152921504606846976i64, /* 0xF000000000000000 */
+             -1i64,                   /* 0xFFFFFFFFFFFFFFFF */
+         ]
+     };
+ }
+ 
+ macro_rules! V_f32 {
+     () => {
+         vec![
+             0.0f32,
+             1.0f32,
+             -1.0f32,
+             1.2f32,
+             2.4f32,
+             std::f32::MAX,
+             std::f32::MIN,
+             std::f32::INFINITY,
+             std::f32::NEG_INFINITY,
+             std::f32::NAN,
+         ]
+     };
+ }
+ 
+ macro_rules! to64 {
+     ($t : ident) => {
+         |v: $t| -> u64 { transmute(v) }
+     };
+ }
+ 
+ macro_rules! to128 {
+     ($t : ident) => {
+         |v: $t| -> u128 { transmute(v) }
+     };
+ }
+ 
+ pub(crate) fn test<T, U, V, W, X>(
+     vals: Vec<T>,
+     fill1: fn(T) -> V,
+     fill2: fn(U) -> W,
+     cast: fn(W) -> X,
+     test_fun: fn(V, V) -> W,
+     verify_fun: fn(T, T) -> U,
+ ) where
+     T: Copy + core::fmt::Debug + std::cmp::PartialEq,
+     U: Copy + core::fmt::Debug + std::cmp::PartialEq,
+     V: Copy + core::fmt::Debug,
+     W: Copy + core::fmt::Debug,
+     X: Copy + core::fmt::Debug + std::cmp::PartialEq,
+ {
+     let pairs = vals.iter().zip(vals.iter());
+ 
+     for (i, j) in pairs {
+         let a: V = fill1(*i);
+         let b: V = fill1(*j);
+ 
+         let actual_pre: W = test_fun(a, b);
+         let expected_pre: W = fill2(verify_fun(*i, *j));
+ 
+         let actual: X = cast(actual_pre);
+         let expected: X = cast(expected_pre);
+ 
+         assert_eq!(
+             actual, expected,
+             "[{:?}:{:?}] :\nf({:?}, {:?}) = {:?}\ng({:?}, {:?}) = {:?}\n",
+             *i, *j, &a, &b, actual_pre, &a, &b, expected_pre
+         );
+     }
+ }
+ 
+ macro_rules! gen_test_fn {
+     ($n: ident, $t: ident, $u: ident, $v: ident, $w: ident, $x: ident, $vals: expr, $fill1: expr, $fill2: expr, $cast: expr) => {
+         pub(crate) fn $n(test_fun: fn($v, $v) -> $w, verify_fun: fn($t, $t) -> $u) {
+             unsafe {
+                 test::<$t, $u, $v, $w, $x>($vals, $fill1, $fill2, $cast, test_fun, verify_fun)
+             };
+         }
+     };
+ }
+ 
+ macro_rules! gen_fill_fn {
+     ($id: ident, $el_width: expr, $num_els: expr, $in_t : ident, $out_t: ident, $cmp_t: ident) => {
+         pub(crate) fn $id(val: $in_t) -> $out_t {
+             let initial: [$in_t; $num_els] = [val; $num_els];
+             let result: $cmp_t = unsafe { transmute(initial) };
+             let result_out: $out_t = unsafe { transmute(result) };
+ 
+             // println!("FILL: {:016x} as {} x {}: {:016x}", val.reverse_bits(), $el_width, $num_els, (result as u64).reverse_bits());
+ 
+             result_out
+         }
+     };
+ }
+ 
+ gen_fill_fn!(fill_u8, 8, 8, u8, uint8x8_t, u64);
+ gen_fill_fn!(fill_s8, 8, 8, i8, int8x8_t, u64);
+ gen_fill_fn!(fillq_u8, 8, 16, u8, uint8x16_t, u128);
+ gen_fill_fn!(fillq_s8, 8, 16, i8, int8x16_t, u128);
+ 
+ gen_fill_fn!(fill_u16, 16, 4, u16, uint16x4_t, u64);
+ gen_fill_fn!(fill_s16, 16, 4, i16, int16x4_t, u64);
+ gen_fill_fn!(fillq_u16, 16, 8, u16, uint16x8_t, u128);
+ gen_fill_fn!(fillq_s16, 16, 8, i16, int16x8_t, u128);
+ 
+ gen_fill_fn!(fill_u32, 32, 2, u32, uint32x2_t, u64);
+ gen_fill_fn!(fill_s32, 32, 2, i32, int32x2_t, u64);
+ gen_fill_fn!(fillq_u32, 32, 4, u32, uint32x4_t, u128);
+ gen_fill_fn!(fillq_s32, 32, 4, i32, int32x4_t, u128);
+ 
+ gen_fill_fn!(fill_u64, 64, 1, u64, uint64x1_t, u64);
+ gen_fill_fn!(fill_s64, 64, 1, i64, int64x1_t, u64);
+ gen_fill_fn!(fillq_u64, 64, 2, u64, uint64x2_t, u128);
+ gen_fill_fn!(fillq_s64, 64, 2, i64, int64x2_t, u128);
+ 
+ gen_fill_fn!(fill_f32, 32, 2, f32, float32x2_t, u64);
+ gen_fill_fn!(fillq_f32, 32, 4, f32, float32x4_t, u128);
+ 
+ gen_test_fn!(
+     test_ari_u8,
+     u8,
+     u8,
+     uint8x8_t,
+     uint8x8_t,
+     u64,
+     V_u8!(),
+     fill_u8,
+     fill_u8,
+     to64!(uint8x8_t)
+ );
+ gen_test_fn!(
+     test_bit_u8,
+     u8,
+     u8,
+     uint8x8_t,
+     uint8x8_t,
+     u64,
+     V_u8!(),
+     fill_u8,
+     fill_u8,
+     to64!(uint8x8_t)
+ );
+ gen_test_fn!(
+     test_cmp_u8,
+     u8,
+     u8,
+     uint8x8_t,
+     uint8x8_t,
+     u64,
+     V_u8!(),
+     fill_u8,
+     fill_u8,
+     to64!(uint8x8_t)
+ );
+ gen_test_fn!(
+     testq_ari_u8,
+     u8,
+     u8,
+     uint8x16_t,
+     uint8x16_t,
+     u128,
+     V_u8!(),
+     fillq_u8,
+     fillq_u8,
+     to128!(uint8x16_t)
+ );
+ gen_test_fn!(
+     testq_bit_u8,
+     u8,
+     u8,
+     uint8x16_t,
+     uint8x16_t,
+     u128,
+     V_u8!(),
+     fillq_u8,
+     fillq_u8,
+     to128!(uint8x16_t)
+ );
+ gen_test_fn!(
+     testq_cmp_u8,
+     u8,
+     u8,
+     uint8x16_t,
+     uint8x16_t,
+     u128,
+     V_u8!(),
+     fillq_u8,
+     fillq_u8,
+     to128!(uint8x16_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_s8,
+     i8,
+     i8,
+     int8x8_t,
+     int8x8_t,
+     u64,
+     V_i8!(),
+     fill_s8,
+     fill_s8,
+     to64!(int8x8_t)
+ );
+ gen_test_fn!(
+     test_bit_s8,
+     i8,
+     i8,
+     int8x8_t,
+     int8x8_t,
+     u64,
+     V_i8!(),
+     fill_s8,
+     fill_s8,
+     to64!(int8x8_t)
+ );
+ gen_test_fn!(
+     test_cmp_s8,
+     i8,
+     u8,
+     int8x8_t,
+     uint8x8_t,
+     u64,
+     V_i8!(),
+     fill_s8,
+     fill_u8,
+     to64!(uint8x8_t)
+ );
+ gen_test_fn!(
+     testq_ari_s8,
+     i8,
+     i8,
+     int8x16_t,
+     int8x16_t,
+     u128,
+     V_i8!(),
+     fillq_s8,
+     fillq_s8,
+     to128!(int8x16_t)
+ );
+ gen_test_fn!(
+     testq_bit_s8,
+     i8,
+     i8,
+     int8x16_t,
+     int8x16_t,
+     u128,
+     V_i8!(),
+     fillq_s8,
+     fillq_s8,
+     to128!(int8x16_t)
+ );
+ gen_test_fn!(
+     testq_cmp_s8,
+     i8,
+     u8,
+     int8x16_t,
+     uint8x16_t,
+     u128,
+     V_i8!(),
+     fillq_s8,
+     fillq_u8,
+     to128!(uint8x16_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_u16,
+     u16,
+     u16,
+     uint16x4_t,
+     uint16x4_t,
+     u64,
+     V_u16!(),
+     fill_u16,
+     fill_u16,
+     to64!(uint16x4_t)
+ );
+ gen_test_fn!(
+     test_bit_u16,
+     u16,
+     u16,
+     uint16x4_t,
+     uint16x4_t,
+     u64,
+     V_u16!(),
+     fill_u16,
+     fill_u16,
+     to64!(uint16x4_t)
+ );
+ gen_test_fn!(
+     test_cmp_u16,
+     u16,
+     u16,
+     uint16x4_t,
+     uint16x4_t,
+     u64,
+     V_u16!(),
+     fill_u16,
+     fill_u16,
+     to64!(uint16x4_t)
+ );
+ gen_test_fn!(
+     testq_ari_u16,
+     u16,
+     u16,
+     uint16x8_t,
+     uint16x8_t,
+     u128,
+     V_u16!(),
+     fillq_u16,
+     fillq_u16,
+     to128!(uint16x8_t)
+ );
+ gen_test_fn!(
+     testq_bit_u16,
+     u16,
+     u16,
+     uint16x8_t,
+     uint16x8_t,
+     u128,
+     V_u16!(),
+     fillq_u16,
+     fillq_u16,
+     to128!(uint16x8_t)
+ );
+ gen_test_fn!(
+     testq_cmp_u16,
+     u16,
+     u16,
+     uint16x8_t,
+     uint16x8_t,
+     u128,
+     V_u16!(),
+     fillq_u16,
+     fillq_u16,
+     to128!(uint16x8_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_s16,
+     i16,
+     i16,
+     int16x4_t,
+     int16x4_t,
+     u64,
+     V_i16!(),
+     fill_s16,
+     fill_s16,
+     to64!(int16x4_t)
+ );
+ gen_test_fn!(
+     test_bit_s16,
+     i16,
+     i16,
+     int16x4_t,
+     int16x4_t,
+     u64,
+     V_i16!(),
+     fill_s16,
+     fill_s16,
+     to64!(int16x4_t)
+ );
+ gen_test_fn!(
+     test_cmp_s16,
+     i16,
+     u16,
+     int16x4_t,
+     uint16x4_t,
+     u64,
+     V_i16!(),
+     fill_s16,
+     fill_u16,
+     to64!(uint16x4_t)
+ );
+ gen_test_fn!(
+     testq_ari_s16,
+     i16,
+     i16,
+     int16x8_t,
+     int16x8_t,
+     u128,
+     V_i16!(),
+     fillq_s16,
+     fillq_s16,
+     to128!(int16x8_t)
+ );
+ gen_test_fn!(
+     testq_bit_s16,
+     i16,
+     i16,
+     int16x8_t,
+     int16x8_t,
+     u128,
+     V_i16!(),
+     fillq_s16,
+     fillq_s16,
+     to128!(int16x8_t)
+ );
+ gen_test_fn!(
+     testq_cmp_s16,
+     i16,
+     u16,
+     int16x8_t,
+     uint16x8_t,
+     u128,
+     V_i16!(),
+     fillq_s16,
+     fillq_u16,
+     to128!(uint16x8_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_u32,
+     u32,
+     u32,
+     uint32x2_t,
+     uint32x2_t,
+     u64,
+     V_u32!(),
+     fill_u32,
+     fill_u32,
+     to64!(uint32x2_t)
+ );
+ gen_test_fn!(
+     test_bit_u32,
+     u32,
+     u32,
+     uint32x2_t,
+     uint32x2_t,
+     u64,
+     V_u32!(),
+     fill_u32,
+     fill_u32,
+     to64!(uint32x2_t)
+ );
+ gen_test_fn!(
+     test_cmp_u32,
+     u32,
+     u32,
+     uint32x2_t,
+     uint32x2_t,
+     u64,
+     V_u32!(),
+     fill_u32,
+     fill_u32,
+     to64!(uint32x2_t)
+ );
+ gen_test_fn!(
+     testq_ari_u32,
+     u32,
+     u32,
+     uint32x4_t,
+     uint32x4_t,
+     u128,
+     V_u32!(),
+     fillq_u32,
+     fillq_u32,
+     to128!(uint32x4_t)
+ );
+ gen_test_fn!(
+     testq_bit_u32,
+     u32,
+     u32,
+     uint32x4_t,
+     uint32x4_t,
+     u128,
+     V_u32!(),
+     fillq_u32,
+     fillq_u32,
+     to128!(uint32x4_t)
+ );
+ gen_test_fn!(
+     testq_cmp_u32,
+     u32,
+     u32,
+     uint32x4_t,
+     uint32x4_t,
+     u128,
+     V_u32!(),
+     fillq_u32,
+     fillq_u32,
+     to128!(uint32x4_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_s32,
+     i32,
+     i32,
+     int32x2_t,
+     int32x2_t,
+     u64,
+     V_i32!(),
+     fill_s32,
+     fill_s32,
+     to64!(int32x2_t)
+ );
+ gen_test_fn!(
+     test_bit_s32,
+     i32,
+     i32,
+     int32x2_t,
+     int32x2_t,
+     u64,
+     V_i32!(),
+     fill_s32,
+     fill_s32,
+     to64!(int32x2_t)
+ );
+ gen_test_fn!(
+     test_cmp_s32,
+     i32,
+     u32,
+     int32x2_t,
+     uint32x2_t,
+     u64,
+     V_i32!(),
+     fill_s32,
+     fill_u32,
+     to64!(uint32x2_t)
+ );
+ gen_test_fn!(
+     testq_ari_s32,
+     i32,
+     i32,
+     int32x4_t,
+     int32x4_t,
+     u128,
+     V_i32!(),
+     fillq_s32,
+     fillq_s32,
+     to128!(int32x4_t)
+ );
+ gen_test_fn!(
+     testq_bit_s32,
+     i32,
+     i32,
+     int32x4_t,
+     int32x4_t,
+     u128,
+     V_i32!(),
+     fillq_s32,
+     fillq_s32,
+     to128!(int32x4_t)
+ );
+ gen_test_fn!(
+     testq_cmp_s32,
+     i32,
+     u32,
+     int32x4_t,
+     uint32x4_t,
+     u128,
+     V_i32!(),
+     fillq_s32,
+     fillq_u32,
+     to128!(uint32x4_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_u64,
+     u64,
+     u64,
+     uint64x1_t,
+     uint64x1_t,
+     u64,
+     V_u64!(),
+     fill_u64,
+     fill_u64,
+     to64!(uint64x1_t)
+ );
+ gen_test_fn!(
+     test_bit_u64,
+     u64,
+     u64,
+     uint64x1_t,
+     uint64x1_t,
+     u64,
+     V_u64!(),
+     fill_u64,
+     fill_u64,
+     to64!(uint64x1_t)
+ );
+ gen_test_fn!(
+     test_cmp_u64,
+     u64,
+     u64,
+     uint64x1_t,
+     uint64x1_t,
+     u64,
+     V_u64!(),
+     fill_u64,
+     fill_u64,
+     to64!(uint64x1_t)
+ );
+ gen_test_fn!(
+     testq_ari_u64,
+     u64,
+     u64,
+     uint64x2_t,
+     uint64x2_t,
+     u128,
+     V_u64!(),
+     fillq_u64,
+     fillq_u64,
+     to128!(uint64x2_t)
+ );
+ gen_test_fn!(
+     testq_bit_u64,
+     u64,
+     u64,
+     uint64x2_t,
+     uint64x2_t,
+     u128,
+     V_u64!(),
+     fillq_u64,
+     fillq_u64,
+     to128!(uint64x2_t)
+ );
+ gen_test_fn!(
+     testq_cmp_u64,
+     u64,
+     u64,
+     uint64x2_t,
+     uint64x2_t,
+     u128,
+     V_u64!(),
+     fillq_u64,
+     fillq_u64,
+     to128!(uint64x2_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_s64,
+     i64,
+     i64,
+     int64x1_t,
+     int64x1_t,
+     u64,
+     V_i64!(),
+     fill_s64,
+     fill_s64,
+     to64!(int64x1_t)
+ );
+ gen_test_fn!(
+     test_bit_s64,
+     i64,
+     i64,
+     int64x1_t,
+     int64x1_t,
+     u64,
+     V_i64!(),
+     fill_s64,
+     fill_s64,
+     to64!(int64x1_t)
+ );
+ gen_test_fn!(
+     test_cmp_s64,
+     i64,
+     u64,
+     int64x1_t,
+     uint64x1_t,
+     u64,
+     V_i64!(),
+     fill_s64,
+     fill_u64,
+     to64!(uint64x1_t)
+ );
+ gen_test_fn!(
+     testq_ari_s64,
+     i64,
+     i64,
+     int64x2_t,
+     int64x2_t,
+     u128,
+     V_i64!(),
+     fillq_s64,
+     fillq_s64,
+     to128!(int64x2_t)
+ );
+ gen_test_fn!(
+     testq_bit_s64,
+     i64,
+     i64,
+     int64x2_t,
+     int64x2_t,
+     u128,
+     V_i64!(),
+     fillq_s64,
+     fillq_s64,
+     to128!(int64x2_t)
+ );
+ gen_test_fn!(
+     testq_cmp_s64,
+     i64,
+     u64,
+     int64x2_t,
+     uint64x2_t,
+     u128,
+     V_i64!(),
+     fillq_s64,
+     fillq_u64,
+     to128!(uint64x2_t)
+ );
+ 
+ gen_test_fn!(
+     test_ari_f32,
+     f32,
+     f32,
+     float32x2_t,
+     float32x2_t,
+     u64,
+     V_f32!(),
+     fill_f32,
+     fill_f32,
+     to64!(float32x2_t)
+ );
+ gen_test_fn!(
+     test_cmp_f32,
+     f32,
+     u32,
+     float32x2_t,
+     uint32x2_t,
+     u64,
+     V_f32!(),
+     fill_f32,
+     fill_u32,
+     to64!(uint32x2_t)
+ );
+ gen_test_fn!(
+     testq_ari_f32,
+     f32,
+     f32,
+     float32x4_t,
+     float32x4_t,
+     u128,
+     V_f32!(),
+     fillq_f32,
+     fillq_f32,
+     to128!(float32x4_t)
+ );
+ gen_test_fn!(
+     testq_cmp_f32,
+     f32,
+     u32,
+     float32x4_t,
+     uint32x4_t,
+     u128,
+     V_f32!(),
+     fillq_f32,
+     fillq_u32,
+     to128!(uint32x4_t)
+ );
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v6.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v6.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v6.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v6.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,49 ----
+ //! ARMv6 intrinsics.
+ //!
+ //! The reference is [ARMv6-M Architecture Reference Manual][armv6m].
+ //!
+ //! [armv6m]:
+ //! http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0419c/index.
+ //! html
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Reverse the order of the bytes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(rev))]
+ pub unsafe fn _rev_u16(x: u16) -> u16 {
+     x.swap_bytes() as u16
+ }
+ 
+ /// Reverse the order of the bytes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(rev))]
+ pub unsafe fn _rev_u32(x: u32) -> u32 {
+     x.swap_bytes() as u32
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arm::v6;
+ 
+     #[test]
+     fn _rev_u16() {
+         unsafe {
+             assert_eq!(
+                 v6::_rev_u16(0b0000_0000_1111_1111_u16),
+                 0b1111_1111_0000_0000_u16
+             );
+         }
+     }
+ 
+     #[test]
+     fn _rev_u32() {
+         unsafe {
+             assert_eq!(
+                 v6::_rev_u32(0b0000_0000_1111_1111_0000_0000_1111_1111_u32),
+                 0b1111_1111_0000_0000_1111_1111_0000_0000_u32
+             );
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v7.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v7.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v7.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/arm/v7.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,88 ----
+ //! ARMv7 intrinsics.
+ //!
+ //! The reference is [ARMv7-M Architecture Reference Manual (Issue
+ //! E.b)][armv7m].
+ //!
+ //! [armv7m]:
+ //! http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403e.
+ //! b/index.html
+ 
+ pub use super::v6::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Count Leading Zeros.
+ #[inline]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(clz))]
+ // FIXME: https://github.com/rust-lang/stdarch/issues/382
+ // #[cfg_attr(all(test, target_arch = "arm"), assert_instr(clz))]
+ pub unsafe fn _clz_u8(x: u8) -> u8 {
+     x.leading_zeros() as u8
+ }
+ 
+ /// Count Leading Zeros.
+ #[inline]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(clz))]
+ // FIXME: https://github.com/rust-lang/stdarch/issues/382
+ // #[cfg_attr(all(test, target_arch = "arm"), assert_instr(clz))]
+ pub unsafe fn _clz_u16(x: u16) -> u16 {
+     x.leading_zeros() as u16
+ }
+ 
+ /// Count Leading Zeros.
+ #[inline]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(clz))]
+ // FIXME: https://github.com/rust-lang/stdarch/issues/382
+ // #[cfg_attr(all(test, target_arch = "arm"), assert_instr(clz))]
+ pub unsafe fn _clz_u32(x: u32) -> u32 {
+     x.leading_zeros() as u32
+ }
+ 
+ /// Reverse the bit order.
+ #[inline]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(test, assert_instr(rbit))]
+ pub unsafe fn _rbit_u32(x: u32) -> u32 {
+     crate::intrinsics::bitreverse(x)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arm::v7;
+ 
+     #[test]
+     fn _clz_u8() {
+         unsafe {
+             assert_eq!(v7::_clz_u8(0b0000_1010u8), 4u8);
+         }
+     }
+ 
+     #[test]
+     fn _clz_u16() {
+         unsafe {
+             assert_eq!(v7::_clz_u16(0b0000_1010u16), 12u16);
+         }
+     }
+ 
+     #[test]
+     fn _clz_u32() {
+         unsafe {
+             assert_eq!(v7::_clz_u32(0b0000_1010u32), 28u32);
+         }
+     }
+ 
+     #[test]
+     #[cfg(dont_compile_me)] // FIXME need to add `v7` upstream in rustc
+     fn _rbit_u32() {
+         unsafe {
+             assert_eq!(
+                 v7::_rbit_u32(0b0000_1010u32),
+                 0b0101_0000_0000_0000_0000_0000_0000_0000u32
+             );
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/core_arch_docs.md gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/core_arch_docs.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/core_arch_docs.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/core_arch_docs.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,340 ----
+ SIMD and vendor intrinsics module.
+ 
+ This module is intended to be the gateway to architecture-specific
+ intrinsic functions, typically related to SIMD (but not always!). Each
+ architecture that Rust compiles to may contain a submodule here, which
+ means that this is not a portable module! If you're writing a portable
+ library take care when using these APIs!
+ 
+ Under this module you'll find an architecture-named module, such as
+ `x86_64`. Each `#[cfg(target_arch)]` that Rust can compile to may have a
+ module entry here, only present on that particular target. For example the
+ `i686-pc-windows-msvc` target will have an `x86` module here, whereas
+ `x86_64-pc-windows-msvc` has `x86_64`.
+ 
+ [rfc]: https://github.com/rust-lang/rfcs/pull/2325
+ [tracked]: https://github.com/rust-lang/rust/issues/48556
+ 
+ # Overview
+ 
+ This module exposes vendor-specific intrinsics that typically correspond to
+ a single machine instruction. These intrinsics are not portable: their
+ availability is architecture-dependent, and not all machines of that
+ architecture might provide the intrinsic.
+ 
+ The `arch` module is intended to be a low-level implementation detail for
+ higher-level APIs. Using it correctly can be quite tricky as you need to
+ ensure at least a few guarantees are upheld:
+ 
+ * The correct architecture's module is used. For example the `arm` module
+   isn't available on the `x86_64-unknown-linux-gnu` target. This is
+   typically done by ensuring that `#[cfg]` is used appropriately when using
+   this module.
+ * The CPU the program is currently running on supports the function being
+   called. For example it is unsafe to call an AVX2 function on a CPU that
+   doesn't actually support AVX2.
+ 
+ As a result of the latter of these guarantees all intrinsics in this module
+ are `unsafe` and extra care needs to be taken when calling them!
+ 
+ # CPU Feature Detection
+ 
+ In order to call these APIs in a safe fashion there's a number of
+ mechanisms available to ensure that the correct CPU feature is available
+ to call an intrinsic. Let's consider, for example, the `_mm256_add_epi64`
+ intrinsics on the `x86` and `x86_64` architectures. This function requires
+ the AVX2 feature as [documented by Intel][intel-dox] so to correctly call
+ this function we need to (a) guarantee we only call it on `x86`/`x86_64`
+ and (b) ensure that the CPU feature is available
+ 
+ [intel-dox]: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_epi64&expand=100
+ 
+ ## Static CPU Feature Detection
+ 
+ The first option available to us is to conditionally compile code via the
+ `#[cfg]` attribute. CPU features correspond to the `target_feature` cfg
+ available, and can be used like so:
+ 
+ ```ignore
+ #[cfg(
+     all(
+         any(target_arch = "x86", target_arch = "x86_64"),
+         target_feature = "avx2"
+     )
+ )]
+ fn foo() {
+     #[cfg(target_arch = "x86")]
+     use std::arch::x86::_mm256_add_epi64;
+     #[cfg(target_arch = "x86_64")]
+     use std::arch::x86_64::_mm256_add_epi64;
+ 
+     unsafe {
+         _mm256_add_epi64(...);
+     }
+ }
+ ```
+ 
+ Here we're using `#[cfg(target_feature = "avx2")]` to conditionally compile
+ this function into our module. This means that if the `avx2` feature is
+ *enabled statically* then we'll use the `_mm256_add_epi64` function at
+ runtime. The `unsafe` block here can be justified through the usage of
+ `#[cfg]` to only compile the code in situations where the safety guarantees
+ are upheld.
+ 
+ Statically enabling a feature is typically done with the `-C
+ target-feature` or `-C target-cpu` flags to the compiler. For example if
+ your local CPU supports AVX2 then you can compile the above function with:
+ 
+ ```sh
+ $ RUSTFLAGS='-C target-cpu=native' cargo build
+ ```
+ 
+ Or otherwise you can specifically enable just the AVX2 feature:
+ 
+ ```sh
+ $ RUSTFLAGS='-C target-feature=+avx2' cargo build
+ ```
+ 
+ Note that when you compile a binary with a particular feature enabled it's
+ important to ensure that you only run the binary on systems which satisfy
+ the required feature set.
+ 
+ ## Dynamic CPU Feature Detection
+ 
+ Sometimes statically dispatching isn't quite what you want. Instead you
+ might want to build a portable binary that runs across a variety of CPUs,
+ but at runtime it selects the most optimized implementation available. This
+ allows you to build a "least common denominator" binary which has certain
+ sections more optimized for different CPUs.
+ 
+ Taking our previous example from before, we're going to compile our binary
+ *without* AVX2 support, but we'd like to enable it for just one function.
+ We can do that in a manner like:
+ 
+ ```ignore
+ fn foo() {
+     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+     {
+         if is_x86_feature_detected!("avx2") {
+             return unsafe { foo_avx2() };
+         }
+     }
+ 
+     // fallback implementation without using AVX2
+ }
+ 
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ #[target_feature(enable = "avx2")]
+ unsafe fn foo_avx2() {
+     #[cfg(target_arch = "x86")]
+     use std::arch::x86::_mm256_add_epi64;
+     #[cfg(target_arch = "x86_64")]
+     use std::arch::x86_64::_mm256_add_epi64;
+ 
+     _mm256_add_epi64(...);
+ }
+ ```
+ 
+ There's a couple of components in play here, so let's go through them in
+ detail!
+ 
+ * First up we notice the `is_x86_feature_detected!` macro. Provided by
+   the standard library, this macro will perform necessary runtime detection
+   to determine whether the CPU the program is running on supports the
+   specified feature. In this case the macro will expand to a boolean
+ expression evaluating to whether the local CPU has the AVX2 feature or
+ not.
+ 
+   Note that this macro, like the `arch` module, is platform-specific. For
+   example calling `is_x86_feature_detected!("avx2")` on ARM will be a
+   compile time error. To ensure we don't hit this error a statement level
+   `#[cfg]` is used to only compile usage of the macro on `x86`/`x86_64`.
+ 
+ * Next up we see our AVX2-enabled function, `foo_avx2`. This function is
+   decorated with the `#[target_feature]` attribute which enables a CPU
+   feature for just this one function. Using a compiler flag like `-C
+   target-feature=+avx2` will enable AVX2 for the entire program, but using
+   an attribute will only enable it for the one function. Usage of the
+   `#[target_feature]` attribute currently requires the function to also be
+   `unsafe`, as we see here. This is because the function can only be
+   correctly called on systems which have the AVX2 (like the intrinsics
+   themselves).
+ 
+ And with all that we should have a working program! This program will run
+ across all machines and it'll use the optimized AVX2 implementation on
+ machines where support is detected.
+ 
+ # Ergonomics
+ 
+ It's important to note that using the `arch` module is not the easiest
+ thing in the world, so if you're curious to try it out you may want to
+ brace yourself for some wordiness!
+ 
+ The primary purpose of this module is to enable stable crates on crates.io
+ to build up much more ergonomic abstractions which end up using SIMD under
+ the hood. Over time these abstractions may also move into the standard
+ library itself, but for now this module is tasked with providing the bare
+ minimum necessary to use vendor intrinsics on stable Rust.
+ 
+ # Other architectures
+ 
+ This documentation is only for one particular architecture, you can find
+ others at:
+ 
+ * [`x86`]
+ * [`x86_64`]
+ * [`arm`]
+ * [`aarch64`]
+ * [`mips`]
+ * [`mips64`]
+ * [`powerpc`]
+ * [`powerpc64`]
+ * [`nvptx`]
+ * [`wasm32`]
+ 
+ [`x86`]: x86/index.html
+ [`x86_64`]: x86_64/index.html
+ [`arm`]: arm/index.html
+ [`aarch64`]: aarch64/index.html
+ [`mips`]: mips/index.html
+ [`mips64`]: mips64/index.html
+ [`powerpc`]: powerpc/index.html
+ [`powerpc64`]: powerpc64/index.html
+ [`nvptx`]: nvptx/index.html
+ [`wasm32`]: wasm32/index.html
+ 
+ # Examples
+ 
+ First let's take a look at not actually using any intrinsics but instead
+ using LLVM's auto-vectorization to produce optimized vectorized code for
+ AVX2 and also for the default platform.
+ 
+ ```rust
+ fn main() {
+     let mut dst = [0];
+     add_quickly(&[1], &[2], &mut dst);
+     assert_eq!(dst[0], 3);
+ }
+ 
+ fn add_quickly(a: &[u8], b: &[u8], c: &mut [u8]) {
+     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+     {
+         // Note that this `unsafe` block is safe because we're testing
+         // that the `avx2` feature is indeed available on our CPU.
+         if is_x86_feature_detected!("avx2") {
+             return unsafe { add_quickly_avx2(a, b, c) };
+         }
+     }
+ 
+     add_quickly_fallback(a, b, c)
+ }
+ 
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ #[target_feature(enable = "avx2")]
+ unsafe fn add_quickly_avx2(a: &[u8], b: &[u8], c: &mut [u8]) {
+     add_quickly_fallback(a, b, c) // the function below is inlined here
+ }
+ 
+ fn add_quickly_fallback(a: &[u8], b: &[u8], c: &mut [u8]) {
+     for ((a, b), c) in a.iter().zip(b).zip(c) {
+         *c = *a + *b;
+     }
+ }
+ ```
+ 
+ Next up let's take a look at an example of manually using intrinsics. Here
+ we'll be using SSE4.1 features to implement hex encoding.
+ 
+ ```
+ fn main() {
+     let mut dst = [0; 32];
+     hex_encode(b"\x01\x02\x03", &mut dst);
+     assert_eq!(&dst[..6], b"010203");
+ 
+     let mut src = [0; 16];
+     for i in 0..16 {
+         src[i] = (i + 1) as u8;
+     }
+     hex_encode(&src, &mut dst);
+     assert_eq!(&dst, b"0102030405060708090a0b0c0d0e0f10");
+ }
+ 
+ pub fn hex_encode(src: &[u8], dst: &mut [u8]) {
+     let len = src.len().checked_mul(2).unwrap();
+     assert!(dst.len() >= len);
+ 
+     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+     {
+         if is_x86_feature_detected!("sse4.1") {
+             return unsafe { hex_encode_sse41(src, dst) };
+         }
+     }
+ 
+     hex_encode_fallback(src, dst)
+ }
+ 
+ // translated from
+ // https://github.com/Matherunner/bin2hex-sse/blob/master/base16_sse4.cpp
+ #[target_feature(enable = "sse4.1")]
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ unsafe fn hex_encode_sse41(mut src: &[u8], dst: &mut [u8]) {
+     #[cfg(target_arch = "x86")]
+     use std::arch::x86::*;
+     #[cfg(target_arch = "x86_64")]
+     use std::arch::x86_64::*;
+ 
+     let ascii_zero = _mm_set1_epi8(b'0' as i8);
+     let nines = _mm_set1_epi8(9);
+     let ascii_a = _mm_set1_epi8((b'a' - 9 - 1) as i8);
+     let and4bits = _mm_set1_epi8(0xf);
+ 
+     let mut i = 0_isize;
+     while src.len() >= 16 {
+         let invec = _mm_loadu_si128(src.as_ptr() as *const _);
+ 
+         let masked1 = _mm_and_si128(invec, and4bits);
+         let masked2 = _mm_and_si128(_mm_srli_epi64(invec, 4), and4bits);
+ 
+         // return 0xff corresponding to the elements > 9, or 0x00 otherwise
+         let cmpmask1 = _mm_cmpgt_epi8(masked1, nines);
+         let cmpmask2 = _mm_cmpgt_epi8(masked2, nines);
+ 
+         // add '0' or the offset depending on the masks
+         let masked1 = _mm_add_epi8(
+             masked1,
+             _mm_blendv_epi8(ascii_zero, ascii_a, cmpmask1),
+         );
+         let masked2 = _mm_add_epi8(
+             masked2,
+             _mm_blendv_epi8(ascii_zero, ascii_a, cmpmask2),
+         );
+ 
+         // interleave masked1 and masked2 bytes
+         let res1 = _mm_unpacklo_epi8(masked2, masked1);
+         let res2 = _mm_unpackhi_epi8(masked2, masked1);
+ 
+         _mm_storeu_si128(dst.as_mut_ptr().offset(i * 2) as *mut _, res1);
+         _mm_storeu_si128(
+             dst.as_mut_ptr().offset(i * 2 + 16) as *mut _,
+             res2,
+         );
+         src = &src[16..];
+         i += 16;
+     }
+ 
+     let i = i as usize;
+     hex_encode_fallback(src, &mut dst[i * 2..]);
+ }
+ 
+ fn hex_encode_fallback(src: &[u8], dst: &mut [u8]) {
+     fn hex(byte: u8) -> u8 {
+         static TABLE: &[u8] = b"0123456789abcdef";
+         TABLE[byte as usize]
+     }
+ 
+     for (byte, slots) in src.iter().zip(dst.chunks_mut(2)) {
+         slots[0] = hex((*byte >> 4) & 0xf);
+         slots[1] = hex(*byte & 0xf);
+     }
+ }
+ ```
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,81 ----
+ #![doc(include = "core_arch_docs.md")]
+ #![allow(improper_ctypes_definitions)]
+ #![allow(dead_code)]
+ #![allow(unused_features)]
+ #![allow(incomplete_features)]
+ #![feature(
+     const_fn,
+     const_fn_union,
+     const_fn_transmute,
+     const_generics,
+     custom_inner_attributes,
+     link_llvm_intrinsics,
+     platform_intrinsics,
+     repr_simd,
+     simd_ffi,
+     llvm_asm,
+     proc_macro_hygiene,
+     stmt_expr_attributes,
+     core_intrinsics,
+     no_core,
+     rustc_attrs,
+     stdsimd,
+     staged_api,
+     doc_cfg,
+     tbm_target_feature,
+     sse4a_target_feature,
+     arm_target_feature,
+     aarch64_target_feature,
+     cmpxchg16b_target_feature,
+     avx512_target_feature,
+     mips_target_feature,
+     powerpc_target_feature,
+     wasm_target_feature,
+     abi_unadjusted,
+     adx_target_feature,
+     rtm_target_feature,
+     f16c_target_feature,
+     external_doc,
+     allow_internal_unstable,
+     decl_macro
+ )]
+ #![cfg_attr(test, feature(test, abi_vectorcall, untagged_unions))]
+ #![cfg_attr(all(test, target_arch = "wasm32"), feature(wasm_simd))]
+ #![deny(clippy::missing_inline_in_public_items)]
+ #![allow(
+     clippy::inline_always,
+     clippy::too_many_arguments,
+     clippy::cast_sign_loss,
+     clippy::cast_lossless,
+     clippy::cast_possible_wrap,
+     clippy::cast_possible_truncation,
+     clippy::cast_precision_loss,
+     clippy::shadow_reuse,
+     clippy::cognitive_complexity,
+     clippy::similar_names,
+     clippy::many_single_char_names
+ )]
+ #![cfg_attr(test, allow(unused_imports))]
+ #![no_std]
+ #![unstable(feature = "stdsimd", issue = "27731")]
+ #![doc(
+     test(attr(deny(warnings))),
+     test(attr(allow(dead_code, deprecated, unused_variables, unused_mut)))
+ )]
+ 
+ #[cfg(test)]
+ #[macro_use]
+ extern crate std;
+ #[cfg(test)]
+ #[macro_use]
+ extern crate std_detect;
+ #[cfg(test)]
+ extern crate stdarch_test;
+ 
+ #[path = "mod.rs"]
+ mod core_arch;
+ 
+ pub use self::core_arch::arch;
+ 
+ #[allow(unused_imports)]
+ use core::{ffi, hint, intrinsics, marker, mem, ops, ptr, sync};
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/macros.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,409 ----
+ //! Utility macros.
+ 
+ #[allow(unused)]
+ macro_rules! constify_imm8 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             31 => $expand!(31),
+             32 => $expand!(32),
+             33 => $expand!(33),
+             34 => $expand!(34),
+             35 => $expand!(35),
+             36 => $expand!(36),
+             37 => $expand!(37),
+             38 => $expand!(38),
+             39 => $expand!(39),
+             40 => $expand!(40),
+             41 => $expand!(41),
+             42 => $expand!(42),
+             43 => $expand!(43),
+             44 => $expand!(44),
+             45 => $expand!(45),
+             46 => $expand!(46),
+             47 => $expand!(47),
+             48 => $expand!(48),
+             49 => $expand!(49),
+             50 => $expand!(50),
+             51 => $expand!(51),
+             52 => $expand!(52),
+             53 => $expand!(53),
+             54 => $expand!(54),
+             55 => $expand!(55),
+             56 => $expand!(56),
+             57 => $expand!(57),
+             58 => $expand!(58),
+             59 => $expand!(59),
+             60 => $expand!(60),
+             61 => $expand!(61),
+             62 => $expand!(62),
+             63 => $expand!(63),
+             64 => $expand!(64),
+             65 => $expand!(65),
+             66 => $expand!(66),
+             67 => $expand!(67),
+             68 => $expand!(68),
+             69 => $expand!(69),
+             70 => $expand!(70),
+             71 => $expand!(71),
+             72 => $expand!(72),
+             73 => $expand!(73),
+             74 => $expand!(74),
+             75 => $expand!(75),
+             76 => $expand!(76),
+             77 => $expand!(77),
+             78 => $expand!(78),
+             79 => $expand!(79),
+             80 => $expand!(80),
+             81 => $expand!(81),
+             82 => $expand!(82),
+             83 => $expand!(83),
+             84 => $expand!(84),
+             85 => $expand!(85),
+             86 => $expand!(86),
+             87 => $expand!(87),
+             88 => $expand!(88),
+             89 => $expand!(89),
+             90 => $expand!(90),
+             91 => $expand!(91),
+             92 => $expand!(92),
+             93 => $expand!(93),
+             94 => $expand!(94),
+             95 => $expand!(95),
+             96 => $expand!(96),
+             97 => $expand!(97),
+             98 => $expand!(98),
+             99 => $expand!(99),
+             100 => $expand!(100),
+             101 => $expand!(101),
+             102 => $expand!(102),
+             103 => $expand!(103),
+             104 => $expand!(104),
+             105 => $expand!(105),
+             106 => $expand!(106),
+             107 => $expand!(107),
+             108 => $expand!(108),
+             109 => $expand!(109),
+             110 => $expand!(110),
+             111 => $expand!(111),
+             112 => $expand!(112),
+             113 => $expand!(113),
+             114 => $expand!(114),
+             115 => $expand!(115),
+             116 => $expand!(116),
+             117 => $expand!(117),
+             118 => $expand!(118),
+             119 => $expand!(119),
+             120 => $expand!(120),
+             121 => $expand!(121),
+             122 => $expand!(122),
+             123 => $expand!(123),
+             124 => $expand!(124),
+             125 => $expand!(125),
+             126 => $expand!(126),
+             127 => $expand!(127),
+             128 => $expand!(128),
+             129 => $expand!(129),
+             130 => $expand!(130),
+             131 => $expand!(131),
+             132 => $expand!(132),
+             133 => $expand!(133),
+             134 => $expand!(134),
+             135 => $expand!(135),
+             136 => $expand!(136),
+             137 => $expand!(137),
+             138 => $expand!(138),
+             139 => $expand!(139),
+             140 => $expand!(140),
+             141 => $expand!(141),
+             142 => $expand!(142),
+             143 => $expand!(143),
+             144 => $expand!(144),
+             145 => $expand!(145),
+             146 => $expand!(146),
+             147 => $expand!(147),
+             148 => $expand!(148),
+             149 => $expand!(149),
+             150 => $expand!(150),
+             151 => $expand!(151),
+             152 => $expand!(152),
+             153 => $expand!(153),
+             154 => $expand!(154),
+             155 => $expand!(155),
+             156 => $expand!(156),
+             157 => $expand!(157),
+             158 => $expand!(158),
+             159 => $expand!(159),
+             160 => $expand!(160),
+             161 => $expand!(161),
+             162 => $expand!(162),
+             163 => $expand!(163),
+             164 => $expand!(164),
+             165 => $expand!(165),
+             166 => $expand!(166),
+             167 => $expand!(167),
+             168 => $expand!(168),
+             169 => $expand!(169),
+             170 => $expand!(170),
+             171 => $expand!(171),
+             172 => $expand!(172),
+             173 => $expand!(173),
+             174 => $expand!(174),
+             175 => $expand!(175),
+             176 => $expand!(176),
+             177 => $expand!(177),
+             178 => $expand!(178),
+             179 => $expand!(179),
+             180 => $expand!(180),
+             181 => $expand!(181),
+             182 => $expand!(182),
+             183 => $expand!(183),
+             184 => $expand!(184),
+             185 => $expand!(185),
+             186 => $expand!(186),
+             187 => $expand!(187),
+             188 => $expand!(188),
+             189 => $expand!(189),
+             190 => $expand!(190),
+             191 => $expand!(191),
+             192 => $expand!(192),
+             193 => $expand!(193),
+             194 => $expand!(194),
+             195 => $expand!(195),
+             196 => $expand!(196),
+             197 => $expand!(197),
+             198 => $expand!(198),
+             199 => $expand!(199),
+             200 => $expand!(200),
+             201 => $expand!(201),
+             202 => $expand!(202),
+             203 => $expand!(203),
+             204 => $expand!(204),
+             205 => $expand!(205),
+             206 => $expand!(206),
+             207 => $expand!(207),
+             208 => $expand!(208),
+             209 => $expand!(209),
+             210 => $expand!(210),
+             211 => $expand!(211),
+             212 => $expand!(212),
+             213 => $expand!(213),
+             214 => $expand!(214),
+             215 => $expand!(215),
+             216 => $expand!(216),
+             217 => $expand!(217),
+             218 => $expand!(218),
+             219 => $expand!(219),
+             220 => $expand!(220),
+             221 => $expand!(221),
+             222 => $expand!(222),
+             223 => $expand!(223),
+             224 => $expand!(224),
+             225 => $expand!(225),
+             226 => $expand!(226),
+             227 => $expand!(227),
+             228 => $expand!(228),
+             229 => $expand!(229),
+             230 => $expand!(230),
+             231 => $expand!(231),
+             232 => $expand!(232),
+             233 => $expand!(233),
+             234 => $expand!(234),
+             235 => $expand!(235),
+             236 => $expand!(236),
+             237 => $expand!(237),
+             238 => $expand!(238),
+             239 => $expand!(239),
+             240 => $expand!(240),
+             241 => $expand!(241),
+             242 => $expand!(242),
+             243 => $expand!(243),
+             244 => $expand!(244),
+             245 => $expand!(245),
+             246 => $expand!(246),
+             247 => $expand!(247),
+             248 => $expand!(248),
+             249 => $expand!(249),
+             250 => $expand!(250),
+             251 => $expand!(251),
+             252 => $expand!(252),
+             253 => $expand!(253),
+             254 => $expand!(254),
+             _ => $expand!(255),
+         }
+     };
+ }
+ 
+ //immediate value: 0:31
+ #[allow(unused)]
+ macro_rules! constify_imm5 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             _ => $expand!(31),
+         }
+     };
+ }
+ 
+ //immediate value: -16:15
+ #[allow(unused)]
+ macro_rules! constify_imm5 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             _ => $expand!(31),
+         }
+     };
+ }
+ 
+ //immediate value: 0:16
+ #[allow(unused)]
+ macro_rules! constify_imm4 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             _ => $expand!(15),
+         }
+     };
+ }
+ 
+ //immediate value: 0:7
+ #[allow(unused)]
+ macro_rules! constify_imm3 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             _ => $expand!(7),
+         }
+     };
+ }
+ 
+ #[allow(unused)]
+ macro_rules! types {
+     ($(
+         $(#[$doc:meta])*
+         pub struct $name:ident($($fields:tt)*);
+     )*) => ($(
+         $(#[$doc])*
+         #[derive(Copy, Clone, Debug)]
+         #[allow(non_camel_case_types)]
+         #[repr(simd)]
+         #[allow(clippy::missing_inline_in_public_items)]
+         pub struct $name($($fields)*);
+     )*)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,18 ----
+ //! MIPS
+ 
+ // Building this module (even if unused) for non-fp64 targets fails with an LLVM
+ // error.
+ #[cfg(target_feature = "fp64")]
+ mod msa;
+ #[cfg(target_feature = "fp64")]
+ pub use self::msa::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Generates the trap instruction `BREAK`
+ #[cfg_attr(test, assert_instr(break))]
+ #[inline]
+ pub unsafe fn break_() -> ! {
+     crate::intrinsics::abort()
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa/macros.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa/macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa/macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa/macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,4353 ----
+ //! Utility macros.
+ 
+ //immediate value: -4096:4088
+ macro_rules! constify_imm_s13 {
+     ($imm_s13:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm_s13) & 0b1_1111_1111_1111 {
+             0 => $expand!(0),
+             8 => $expand!(8),
+             16 => $expand!(16),
+             24 => $expand!(24),
+             32 => $expand!(32),
+             40 => $expand!(40),
+             48 => $expand!(48),
+             56 => $expand!(56),
+             64 => $expand!(64),
+             72 => $expand!(72),
+             80 => $expand!(80),
+             88 => $expand!(88),
+             96 => $expand!(96),
+             104 => $expand!(104),
+             112 => $expand!(112),
+             120 => $expand!(120),
+             128 => $expand!(128),
+             136 => $expand!(136),
+             144 => $expand!(144),
+             152 => $expand!(152),
+             160 => $expand!(160),
+             168 => $expand!(168),
+             176 => $expand!(176),
+             184 => $expand!(184),
+             192 => $expand!(192),
+             200 => $expand!(200),
+             208 => $expand!(208),
+             216 => $expand!(216),
+             224 => $expand!(224),
+             232 => $expand!(232),
+             240 => $expand!(240),
+             248 => $expand!(248),
+             256 => $expand!(256),
+             264 => $expand!(264),
+             272 => $expand!(272),
+             280 => $expand!(280),
+             288 => $expand!(288),
+             296 => $expand!(296),
+             304 => $expand!(304),
+             312 => $expand!(312),
+             320 => $expand!(320),
+             328 => $expand!(328),
+             336 => $expand!(336),
+             344 => $expand!(344),
+             352 => $expand!(352),
+             360 => $expand!(360),
+             368 => $expand!(368),
+             376 => $expand!(376),
+             384 => $expand!(384),
+             392 => $expand!(392),
+             400 => $expand!(400),
+             408 => $expand!(408),
+             416 => $expand!(416),
+             424 => $expand!(424),
+             432 => $expand!(432),
+             440 => $expand!(440),
+             448 => $expand!(448),
+             456 => $expand!(456),
+             464 => $expand!(464),
+             472 => $expand!(472),
+             480 => $expand!(480),
+             488 => $expand!(488),
+             496 => $expand!(496),
+             504 => $expand!(504),
+             512 => $expand!(512),
+             520 => $expand!(520),
+             528 => $expand!(528),
+             536 => $expand!(536),
+             544 => $expand!(544),
+             552 => $expand!(552),
+             560 => $expand!(560),
+             568 => $expand!(568),
+             576 => $expand!(576),
+             584 => $expand!(584),
+             592 => $expand!(592),
+             600 => $expand!(600),
+             608 => $expand!(608),
+             616 => $expand!(616),
+             624 => $expand!(624),
+             632 => $expand!(632),
+             640 => $expand!(640),
+             648 => $expand!(648),
+             656 => $expand!(656),
+             664 => $expand!(664),
+             672 => $expand!(672),
+             680 => $expand!(680),
+             688 => $expand!(688),
+             696 => $expand!(696),
+             704 => $expand!(704),
+             712 => $expand!(712),
+             720 => $expand!(720),
+             728 => $expand!(728),
+             736 => $expand!(736),
+             744 => $expand!(744),
+             752 => $expand!(752),
+             760 => $expand!(760),
+             768 => $expand!(768),
+             776 => $expand!(776),
+             784 => $expand!(784),
+             792 => $expand!(792),
+             800 => $expand!(800),
+             808 => $expand!(808),
+             816 => $expand!(816),
+             824 => $expand!(824),
+             832 => $expand!(832),
+             840 => $expand!(840),
+             848 => $expand!(848),
+             856 => $expand!(856),
+             864 => $expand!(864),
+             872 => $expand!(872),
+             880 => $expand!(880),
+             888 => $expand!(888),
+             896 => $expand!(896),
+             904 => $expand!(904),
+             912 => $expand!(912),
+             920 => $expand!(920),
+             928 => $expand!(928),
+             936 => $expand!(936),
+             944 => $expand!(944),
+             952 => $expand!(952),
+             960 => $expand!(960),
+             968 => $expand!(968),
+             976 => $expand!(976),
+             984 => $expand!(984),
+             992 => $expand!(992),
+             1000 => $expand!(1000),
+             1008 => $expand!(1008),
+             1016 => $expand!(1016),
+             1024 => $expand!(1024),
+             1032 => $expand!(1032),
+             1040 => $expand!(1040),
+             1048 => $expand!(1048),
+             1056 => $expand!(1056),
+             1064 => $expand!(1064),
+             1072 => $expand!(1072),
+             1080 => $expand!(1080),
+             1088 => $expand!(1088),
+             1096 => $expand!(1096),
+             1104 => $expand!(1104),
+             1112 => $expand!(1112),
+             1120 => $expand!(1120),
+             1128 => $expand!(1128),
+             1136 => $expand!(1136),
+             1144 => $expand!(1144),
+             1152 => $expand!(1152),
+             1160 => $expand!(1160),
+             1168 => $expand!(1168),
+             1176 => $expand!(1176),
+             1184 => $expand!(1184),
+             1192 => $expand!(1192),
+             1200 => $expand!(1200),
+             1208 => $expand!(1208),
+             1216 => $expand!(1216),
+             1224 => $expand!(1224),
+             1232 => $expand!(1232),
+             1240 => $expand!(1240),
+             1248 => $expand!(1248),
+             1256 => $expand!(1256),
+             1264 => $expand!(1264),
+             1272 => $expand!(1272),
+             1280 => $expand!(1280),
+             1288 => $expand!(1288),
+             1296 => $expand!(1296),
+             1304 => $expand!(1304),
+             1312 => $expand!(1312),
+             1320 => $expand!(1320),
+             1328 => $expand!(1328),
+             1336 => $expand!(1336),
+             1344 => $expand!(1344),
+             1352 => $expand!(1352),
+             1360 => $expand!(1360),
+             1368 => $expand!(1368),
+             1376 => $expand!(1376),
+             1384 => $expand!(1384),
+             1392 => $expand!(1392),
+             1400 => $expand!(1400),
+             1408 => $expand!(1408),
+             1416 => $expand!(1416),
+             1424 => $expand!(1424),
+             1432 => $expand!(1432),
+             1440 => $expand!(1440),
+             1448 => $expand!(1448),
+             1456 => $expand!(1456),
+             1464 => $expand!(1464),
+             1472 => $expand!(1472),
+             1480 => $expand!(1480),
+             1488 => $expand!(1488),
+             1496 => $expand!(1496),
+             1504 => $expand!(1504),
+             1512 => $expand!(1512),
+             1520 => $expand!(1520),
+             1528 => $expand!(1528),
+             1536 => $expand!(1536),
+             1544 => $expand!(1544),
+             1552 => $expand!(1552),
+             1560 => $expand!(1560),
+             1568 => $expand!(1568),
+             1576 => $expand!(1576),
+             1584 => $expand!(1584),
+             1592 => $expand!(1592),
+             1600 => $expand!(1600),
+             1608 => $expand!(1608),
+             1616 => $expand!(1616),
+             1624 => $expand!(1624),
+             1632 => $expand!(1632),
+             1640 => $expand!(1640),
+             1648 => $expand!(1648),
+             1656 => $expand!(1656),
+             1664 => $expand!(1664),
+             1672 => $expand!(1672),
+             1680 => $expand!(1680),
+             1688 => $expand!(1688),
+             1696 => $expand!(1696),
+             1704 => $expand!(1704),
+             1712 => $expand!(1712),
+             1720 => $expand!(1720),
+             1728 => $expand!(1728),
+             1736 => $expand!(1736),
+             1744 => $expand!(1744),
+             1752 => $expand!(1752),
+             1760 => $expand!(1760),
+             1768 => $expand!(1768),
+             1776 => $expand!(1776),
+             1784 => $expand!(1784),
+             1792 => $expand!(1792),
+             1800 => $expand!(1800),
+             1808 => $expand!(1808),
+             1816 => $expand!(1816),
+             1824 => $expand!(1824),
+             1832 => $expand!(1832),
+             1840 => $expand!(1840),
+             1848 => $expand!(1848),
+             1856 => $expand!(1856),
+             1864 => $expand!(1864),
+             1872 => $expand!(1872),
+             1880 => $expand!(1880),
+             1888 => $expand!(1888),
+             1896 => $expand!(1896),
+             1904 => $expand!(1904),
+             1912 => $expand!(1912),
+             1920 => $expand!(1920),
+             1928 => $expand!(1928),
+             1936 => $expand!(1936),
+             1944 => $expand!(1944),
+             1952 => $expand!(1952),
+             1960 => $expand!(1960),
+             1968 => $expand!(1968),
+             1976 => $expand!(1976),
+             1984 => $expand!(1984),
+             1992 => $expand!(1992),
+             2000 => $expand!(2000),
+             2008 => $expand!(2008),
+             2016 => $expand!(2016),
+             2024 => $expand!(2024),
+             2032 => $expand!(2032),
+             2040 => $expand!(2040),
+             2048 => $expand!(2048),
+             2056 => $expand!(2056),
+             2064 => $expand!(2064),
+             2072 => $expand!(2072),
+             2080 => $expand!(2080),
+             2088 => $expand!(2088),
+             2096 => $expand!(2096),
+             2104 => $expand!(2104),
+             2112 => $expand!(2112),
+             2120 => $expand!(2120),
+             2128 => $expand!(2128),
+             2136 => $expand!(2136),
+             2144 => $expand!(2144),
+             2152 => $expand!(2152),
+             2160 => $expand!(2160),
+             2168 => $expand!(2168),
+             2176 => $expand!(2176),
+             2184 => $expand!(2184),
+             2192 => $expand!(2192),
+             2200 => $expand!(2200),
+             2208 => $expand!(2208),
+             2216 => $expand!(2216),
+             2224 => $expand!(2224),
+             2232 => $expand!(2232),
+             2240 => $expand!(2240),
+             2248 => $expand!(2248),
+             2256 => $expand!(2256),
+             2264 => $expand!(2264),
+             2272 => $expand!(2272),
+             2280 => $expand!(2280),
+             2288 => $expand!(2288),
+             2296 => $expand!(2296),
+             2304 => $expand!(2304),
+             2312 => $expand!(2312),
+             2320 => $expand!(2320),
+             2328 => $expand!(2328),
+             2336 => $expand!(2336),
+             2344 => $expand!(2344),
+             2352 => $expand!(2352),
+             2360 => $expand!(2360),
+             2368 => $expand!(2368),
+             2376 => $expand!(2376),
+             2384 => $expand!(2384),
+             2392 => $expand!(2392),
+             2400 => $expand!(2400),
+             2408 => $expand!(2408),
+             2416 => $expand!(2416),
+             2424 => $expand!(2424),
+             2432 => $expand!(2432),
+             2440 => $expand!(2440),
+             2448 => $expand!(2448),
+             2456 => $expand!(2456),
+             2464 => $expand!(2464),
+             2472 => $expand!(2472),
+             2480 => $expand!(2480),
+             2488 => $expand!(2488),
+             2496 => $expand!(2496),
+             2504 => $expand!(2504),
+             2512 => $expand!(2512),
+             2520 => $expand!(2520),
+             2528 => $expand!(2528),
+             2536 => $expand!(2536),
+             2544 => $expand!(2544),
+             2552 => $expand!(2552),
+             2560 => $expand!(2560),
+             2568 => $expand!(2568),
+             2576 => $expand!(2576),
+             2584 => $expand!(2584),
+             2592 => $expand!(2592),
+             2600 => $expand!(2600),
+             2608 => $expand!(2608),
+             2616 => $expand!(2616),
+             2624 => $expand!(2624),
+             2632 => $expand!(2632),
+             2640 => $expand!(2640),
+             2648 => $expand!(2648),
+             2656 => $expand!(2656),
+             2664 => $expand!(2664),
+             2672 => $expand!(2672),
+             2680 => $expand!(2680),
+             2688 => $expand!(2688),
+             2696 => $expand!(2696),
+             2704 => $expand!(2704),
+             2712 => $expand!(2712),
+             2720 => $expand!(2720),
+             2728 => $expand!(2728),
+             2736 => $expand!(2736),
+             2744 => $expand!(2744),
+             2752 => $expand!(2752),
+             2760 => $expand!(2760),
+             2768 => $expand!(2768),
+             2776 => $expand!(2776),
+             2784 => $expand!(2784),
+             2792 => $expand!(2792),
+             2800 => $expand!(2800),
+             2808 => $expand!(2808),
+             2816 => $expand!(2816),
+             2824 => $expand!(2824),
+             2832 => $expand!(2832),
+             2840 => $expand!(2840),
+             2848 => $expand!(2848),
+             2856 => $expand!(2856),
+             2864 => $expand!(2864),
+             2872 => $expand!(2872),
+             2880 => $expand!(2880),
+             2888 => $expand!(2888),
+             2896 => $expand!(2896),
+             2904 => $expand!(2904),
+             2912 => $expand!(2912),
+             2920 => $expand!(2920),
+             2928 => $expand!(2928),
+             2936 => $expand!(2936),
+             2944 => $expand!(2944),
+             2952 => $expand!(2952),
+             2960 => $expand!(2960),
+             2968 => $expand!(2968),
+             2976 => $expand!(2976),
+             2984 => $expand!(2984),
+             2992 => $expand!(2992),
+             3000 => $expand!(3000),
+             3008 => $expand!(3008),
+             3016 => $expand!(3016),
+             3024 => $expand!(3024),
+             3032 => $expand!(3032),
+             3040 => $expand!(3040),
+             3048 => $expand!(3048),
+             3056 => $expand!(3056),
+             3064 => $expand!(3064),
+             3072 => $expand!(3072),
+             3080 => $expand!(3080),
+             3088 => $expand!(3088),
+             3096 => $expand!(3096),
+             3104 => $expand!(3104),
+             3112 => $expand!(3112),
+             3120 => $expand!(3120),
+             3128 => $expand!(3128),
+             3136 => $expand!(3136),
+             3144 => $expand!(3144),
+             3152 => $expand!(3152),
+             3160 => $expand!(3160),
+             3168 => $expand!(3168),
+             3176 => $expand!(3176),
+             3184 => $expand!(3184),
+             3192 => $expand!(3192),
+             3200 => $expand!(3200),
+             3208 => $expand!(3208),
+             3216 => $expand!(3216),
+             3224 => $expand!(3224),
+             3232 => $expand!(3232),
+             3240 => $expand!(3240),
+             3248 => $expand!(3248),
+             3256 => $expand!(3256),
+             3264 => $expand!(3264),
+             3272 => $expand!(3272),
+             3280 => $expand!(3280),
+             3288 => $expand!(3288),
+             3296 => $expand!(3296),
+             3304 => $expand!(3304),
+             3312 => $expand!(3312),
+             3320 => $expand!(3320),
+             3328 => $expand!(3328),
+             3336 => $expand!(3336),
+             3344 => $expand!(3344),
+             3352 => $expand!(3352),
+             3360 => $expand!(3360),
+             3368 => $expand!(3368),
+             3376 => $expand!(3376),
+             3384 => $expand!(3384),
+             3392 => $expand!(3392),
+             3400 => $expand!(3400),
+             3408 => $expand!(3408),
+             3416 => $expand!(3416),
+             3424 => $expand!(3424),
+             3432 => $expand!(3432),
+             3440 => $expand!(3440),
+             3448 => $expand!(3448),
+             3456 => $expand!(3456),
+             3464 => $expand!(3464),
+             3472 => $expand!(3472),
+             3480 => $expand!(3480),
+             3488 => $expand!(3488),
+             3496 => $expand!(3496),
+             3504 => $expand!(3504),
+             3512 => $expand!(3512),
+             3520 => $expand!(3520),
+             3528 => $expand!(3528),
+             3536 => $expand!(3536),
+             3544 => $expand!(3544),
+             3552 => $expand!(3552),
+             3560 => $expand!(3560),
+             3568 => $expand!(3568),
+             3576 => $expand!(3576),
+             3584 => $expand!(3584),
+             3592 => $expand!(3592),
+             3600 => $expand!(3600),
+             3608 => $expand!(3608),
+             3616 => $expand!(3616),
+             3624 => $expand!(3624),
+             3632 => $expand!(3632),
+             3640 => $expand!(3640),
+             3648 => $expand!(3648),
+             3656 => $expand!(3656),
+             3664 => $expand!(3664),
+             3672 => $expand!(3672),
+             3680 => $expand!(3680),
+             3688 => $expand!(3688),
+             3696 => $expand!(3696),
+             3704 => $expand!(3704),
+             3712 => $expand!(3712),
+             3720 => $expand!(3720),
+             3728 => $expand!(3728),
+             3736 => $expand!(3736),
+             3744 => $expand!(3744),
+             3752 => $expand!(3752),
+             3760 => $expand!(3760),
+             3768 => $expand!(3768),
+             3776 => $expand!(3776),
+             3784 => $expand!(3784),
+             3792 => $expand!(3792),
+             3700 => $expand!(3700),
+             3808 => $expand!(3808),
+             3816 => $expand!(3816),
+             3824 => $expand!(3824),
+             3832 => $expand!(3832),
+             3840 => $expand!(3840),
+             3848 => $expand!(3848),
+             3856 => $expand!(3856),
+             3864 => $expand!(3864),
+             3872 => $expand!(3872),
+             3880 => $expand!(3880),
+             3888 => $expand!(3888),
+             3896 => $expand!(3896),
+             3904 => $expand!(3904),
+             3912 => $expand!(3912),
+             3920 => $expand!(3920),
+             3928 => $expand!(3928),
+             3936 => $expand!(3936),
+             3944 => $expand!(3944),
+             3952 => $expand!(3952),
+             3960 => $expand!(3960),
+             3968 => $expand!(3968),
+             3976 => $expand!(3976),
+             3984 => $expand!(3984),
+             3992 => $expand!(3992),
+             4000 => $expand!(4000),
+             4008 => $expand!(4008),
+             4016 => $expand!(4016),
+             4024 => $expand!(4024),
+             4032 => $expand!(4032),
+             4040 => $expand!(4040),
+             4048 => $expand!(4048),
+             4056 => $expand!(4056),
+             4064 => $expand!(4064),
+             4072 => $expand!(4072),
+             4080 => $expand!(4080),
+             4096 => $expand!(-4096),
+             4104 => $expand!(-4088),
+             4112 => $expand!(-4080),
+             4120 => $expand!(-4072),
+             4128 => $expand!(-4064),
+             4136 => $expand!(-4056),
+             4144 => $expand!(-4048),
+             4152 => $expand!(-4040),
+             4160 => $expand!(-4032),
+             4168 => $expand!(-4024),
+             4176 => $expand!(-4016),
+             4184 => $expand!(-4008),
+             4192 => $expand!(-4000),
+             4200 => $expand!(-3992),
+             4208 => $expand!(-3984),
+             4216 => $expand!(-3976),
+             4224 => $expand!(-3968),
+             4232 => $expand!(-3960),
+             4240 => $expand!(-3952),
+             4248 => $expand!(-3944),
+             4256 => $expand!(-3936),
+             4264 => $expand!(-3928),
+             4272 => $expand!(-3920),
+             4280 => $expand!(-3912),
+             4288 => $expand!(-3904),
+             4296 => $expand!(-3896),
+             4304 => $expand!(-3888),
+             4312 => $expand!(-3880),
+             4320 => $expand!(-3872),
+             4328 => $expand!(-3864),
+             4336 => $expand!(-3856),
+             4344 => $expand!(-3848),
+             4352 => $expand!(-3840),
+             4360 => $expand!(-3832),
+             4368 => $expand!(-3824),
+             4376 => $expand!(-3816),
+             4384 => $expand!(-3808),
+             4392 => $expand!(-3800),
+             4400 => $expand!(-3792),
+             4408 => $expand!(-3784),
+             4416 => $expand!(-3776),
+             4424 => $expand!(-3768),
+             4432 => $expand!(-3760),
+             4440 => $expand!(-3752),
+             4448 => $expand!(-3744),
+             4456 => $expand!(-3736),
+             4464 => $expand!(-3728),
+             4472 => $expand!(-3720),
+             4480 => $expand!(-3712),
+             4488 => $expand!(-3704),
+             4496 => $expand!(-3696),
+             4504 => $expand!(-3688),
+             4512 => $expand!(-3680),
+             4520 => $expand!(-3672),
+             4528 => $expand!(-3664),
+             4536 => $expand!(-3656),
+             4544 => $expand!(-3648),
+             4552 => $expand!(-3640),
+             4560 => $expand!(-3632),
+             4568 => $expand!(-3624),
+             4576 => $expand!(-3616),
+             4584 => $expand!(-3608),
+             4592 => $expand!(-3600),
+             4600 => $expand!(-3592),
+             4608 => $expand!(-3584),
+             4616 => $expand!(-3576),
+             4624 => $expand!(-3568),
+             4632 => $expand!(-3560),
+             4640 => $expand!(-3552),
+             4648 => $expand!(-3544),
+             4656 => $expand!(-3536),
+             4664 => $expand!(-3528),
+             4672 => $expand!(-3520),
+             4680 => $expand!(-3512),
+             4688 => $expand!(-3504),
+             4696 => $expand!(-3496),
+             4704 => $expand!(-3488),
+             4712 => $expand!(-3480),
+             4720 => $expand!(-3472),
+             4728 => $expand!(-3464),
+             4736 => $expand!(-3456),
+             4744 => $expand!(-3448),
+             4752 => $expand!(-3440),
+             4760 => $expand!(-3432),
+             4768 => $expand!(-3424),
+             4776 => $expand!(-3416),
+             4784 => $expand!(-3408),
+             4792 => $expand!(-3400),
+             4800 => $expand!(-3392),
+             4808 => $expand!(-3384),
+             4816 => $expand!(-3376),
+             4824 => $expand!(-3368),
+             4832 => $expand!(-3360),
+             4840 => $expand!(-3352),
+             4848 => $expand!(-3344),
+             4856 => $expand!(-3336),
+             4864 => $expand!(-3328),
+             4872 => $expand!(-3320),
+             4880 => $expand!(-3312),
+             4888 => $expand!(-3304),
+             4896 => $expand!(-3296),
+             4904 => $expand!(-3288),
+             4912 => $expand!(-3280),
+             4920 => $expand!(-3272),
+             4928 => $expand!(-3264),
+             4936 => $expand!(-3256),
+             4944 => $expand!(-3248),
+             4952 => $expand!(-3240),
+             4960 => $expand!(-3232),
+             4968 => $expand!(-3224),
+             4976 => $expand!(-3216),
+             4984 => $expand!(-3208),
+             4992 => $expand!(-3200),
+             5000 => $expand!(-3192),
+             5008 => $expand!(-3184),
+             5016 => $expand!(-3176),
+             5024 => $expand!(-3168),
+             5032 => $expand!(-3160),
+             5040 => $expand!(-3152),
+             5048 => $expand!(-3144),
+             5056 => $expand!(-3136),
+             5064 => $expand!(-3128),
+             5072 => $expand!(-3120),
+             5080 => $expand!(-3112),
+             5088 => $expand!(-3104),
+             5096 => $expand!(-3096),
+             5104 => $expand!(-3088),
+             5112 => $expand!(-3080),
+             5120 => $expand!(-3072),
+             5128 => $expand!(-3064),
+             5136 => $expand!(-3056),
+             5144 => $expand!(-3048),
+             5152 => $expand!(-3040),
+             5160 => $expand!(-3032),
+             5168 => $expand!(-3024),
+             5176 => $expand!(-3016),
+             5184 => $expand!(-3008),
+             5192 => $expand!(-3000),
+             5200 => $expand!(-2992),
+             5208 => $expand!(-2984),
+             5216 => $expand!(-2976),
+             5224 => $expand!(-2968),
+             5232 => $expand!(-2960),
+             5240 => $expand!(-2952),
+             5248 => $expand!(-2944),
+             5256 => $expand!(-2936),
+             5264 => $expand!(-2928),
+             5272 => $expand!(-2920),
+             5280 => $expand!(-2912),
+             5288 => $expand!(-2904),
+             5296 => $expand!(-2896),
+             5304 => $expand!(-2888),
+             5312 => $expand!(-2880),
+             5320 => $expand!(-2872),
+             5328 => $expand!(-2864),
+             5336 => $expand!(-2856),
+             5344 => $expand!(-2848),
+             5352 => $expand!(-2840),
+             5360 => $expand!(-2832),
+             5368 => $expand!(-2824),
+             5376 => $expand!(-2816),
+             5384 => $expand!(-2808),
+             5392 => $expand!(-2800),
+             5400 => $expand!(-2792),
+             5408 => $expand!(-2784),
+             5416 => $expand!(-2776),
+             5424 => $expand!(-2768),
+             5432 => $expand!(-2760),
+             5440 => $expand!(-2752),
+             5448 => $expand!(-2744),
+             5456 => $expand!(-2736),
+             5464 => $expand!(-2728),
+             5472 => $expand!(-2720),
+             5480 => $expand!(-2712),
+             5488 => $expand!(-2704),
+             5496 => $expand!(-2696),
+             5504 => $expand!(-2688),
+             5512 => $expand!(-2680),
+             5520 => $expand!(-2672),
+             5528 => $expand!(-2664),
+             5536 => $expand!(-2656),
+             5544 => $expand!(-2648),
+             5552 => $expand!(-2640),
+             5560 => $expand!(-2632),
+             5568 => $expand!(-2624),
+             5576 => $expand!(-2616),
+             5584 => $expand!(-2608),
+             5592 => $expand!(-2600),
+             5600 => $expand!(-2592),
+             5608 => $expand!(-2584),
+             5616 => $expand!(-2576),
+             5624 => $expand!(-2568),
+             5632 => $expand!(-2560),
+             5640 => $expand!(-2552),
+             5648 => $expand!(-2544),
+             5656 => $expand!(-2536),
+             5664 => $expand!(-2528),
+             5672 => $expand!(-2520),
+             5680 => $expand!(-2512),
+             5688 => $expand!(-2504),
+             5696 => $expand!(-2496),
+             5704 => $expand!(-2488),
+             5712 => $expand!(-2480),
+             5720 => $expand!(-2472),
+             5728 => $expand!(-2464),
+             5736 => $expand!(-2456),
+             5744 => $expand!(-2448),
+             5752 => $expand!(-2440),
+             5760 => $expand!(-2432),
+             5768 => $expand!(-2424),
+             5776 => $expand!(-2416),
+             5784 => $expand!(-2408),
+             5792 => $expand!(-2400),
+             5800 => $expand!(-2392),
+             5808 => $expand!(-2384),
+             5816 => $expand!(-2376),
+             5824 => $expand!(-2368),
+             5832 => $expand!(-2360),
+             5840 => $expand!(-2352),
+             5848 => $expand!(-2344),
+             5856 => $expand!(-2336),
+             5864 => $expand!(-2328),
+             5872 => $expand!(-2320),
+             5880 => $expand!(-2312),
+             5888 => $expand!(-2304),
+             5896 => $expand!(-2296),
+             5904 => $expand!(-2288),
+             5912 => $expand!(-2280),
+             5920 => $expand!(-2272),
+             5928 => $expand!(-2264),
+             5936 => $expand!(-2256),
+             5944 => $expand!(-2248),
+             5952 => $expand!(-2240),
+             5960 => $expand!(-2232),
+             5968 => $expand!(-2224),
+             5976 => $expand!(-2216),
+             5984 => $expand!(-2208),
+             5992 => $expand!(-2200),
+             6000 => $expand!(-2192),
+             6008 => $expand!(-2184),
+             6016 => $expand!(-2176),
+             6024 => $expand!(-2168),
+             6032 => $expand!(-2160),
+             6040 => $expand!(-2152),
+             6048 => $expand!(-2144),
+             6056 => $expand!(-2136),
+             6064 => $expand!(-2128),
+             6072 => $expand!(-2120),
+             6080 => $expand!(-2112),
+             6088 => $expand!(-2104),
+             6096 => $expand!(-2096),
+             6104 => $expand!(-2088),
+             6112 => $expand!(-2080),
+             6120 => $expand!(-2072),
+             6128 => $expand!(-2064),
+             6136 => $expand!(-2056),
+             6144 => $expand!(-2048),
+             6152 => $expand!(-2040),
+             6160 => $expand!(-2032),
+             6168 => $expand!(-2024),
+             6176 => $expand!(-2016),
+             6184 => $expand!(-2008),
+             6192 => $expand!(-2000),
+             6200 => $expand!(-1992),
+             6208 => $expand!(-1984),
+             6216 => $expand!(-1976),
+             6224 => $expand!(-1968),
+             6232 => $expand!(-1960),
+             6240 => $expand!(-1952),
+             6248 => $expand!(-1944),
+             6256 => $expand!(-1936),
+             6264 => $expand!(-1928),
+             6272 => $expand!(-1920),
+             6280 => $expand!(-1912),
+             6288 => $expand!(-1904),
+             6296 => $expand!(-1896),
+             6304 => $expand!(-1888),
+             6312 => $expand!(-1880),
+             6320 => $expand!(-1872),
+             6328 => $expand!(-1864),
+             6336 => $expand!(-1856),
+             6344 => $expand!(-1848),
+             6352 => $expand!(-1840),
+             6360 => $expand!(-1832),
+             6368 => $expand!(-1824),
+             6376 => $expand!(-1816),
+             6384 => $expand!(-1808),
+             6392 => $expand!(-1800),
+             6400 => $expand!(-1792),
+             6408 => $expand!(-1784),
+             6416 => $expand!(-1776),
+             6424 => $expand!(-1768),
+             6432 => $expand!(-1760),
+             6440 => $expand!(-1752),
+             6448 => $expand!(-1744),
+             6456 => $expand!(-1736),
+             6464 => $expand!(-1728),
+             6472 => $expand!(-1720),
+             6480 => $expand!(-1712),
+             6488 => $expand!(-1704),
+             6496 => $expand!(-1696),
+             6504 => $expand!(-1688),
+             6512 => $expand!(-1680),
+             6520 => $expand!(-1672),
+             6528 => $expand!(-1664),
+             6536 => $expand!(-1656),
+             6544 => $expand!(-1648),
+             6552 => $expand!(-1640),
+             6560 => $expand!(-1632),
+             6568 => $expand!(-1624),
+             6576 => $expand!(-1616),
+             6584 => $expand!(-1608),
+             6592 => $expand!(-1600),
+             6600 => $expand!(-1592),
+             6608 => $expand!(-1584),
+             6616 => $expand!(-1576),
+             6624 => $expand!(-1568),
+             6632 => $expand!(-1560),
+             6640 => $expand!(-1552),
+             6648 => $expand!(-1544),
+             6656 => $expand!(-1536),
+             6664 => $expand!(-1528),
+             6672 => $expand!(-1520),
+             6680 => $expand!(-1512),
+             6688 => $expand!(-1504),
+             6696 => $expand!(-1496),
+             6704 => $expand!(-1488),
+             6712 => $expand!(-1480),
+             6720 => $expand!(-1472),
+             6728 => $expand!(-1464),
+             6736 => $expand!(-1456),
+             6744 => $expand!(-1448),
+             6752 => $expand!(-1440),
+             6760 => $expand!(-1432),
+             6768 => $expand!(-1424),
+             6776 => $expand!(-1416),
+             6784 => $expand!(-1408),
+             6792 => $expand!(-1400),
+             6800 => $expand!(-1392),
+             6808 => $expand!(-1384),
+             6816 => $expand!(-1376),
+             6824 => $expand!(-1368),
+             6832 => $expand!(-1360),
+             6840 => $expand!(-1352),
+             6848 => $expand!(-1344),
+             6856 => $expand!(-1336),
+             6864 => $expand!(-1328),
+             6872 => $expand!(-1320),
+             6880 => $expand!(-1312),
+             6888 => $expand!(-1304),
+             6896 => $expand!(-1296),
+             6904 => $expand!(-1288),
+             6912 => $expand!(-1280),
+             6920 => $expand!(-1272),
+             6928 => $expand!(-1264),
+             6936 => $expand!(-1256),
+             6944 => $expand!(-1248),
+             6952 => $expand!(-1240),
+             6960 => $expand!(-1232),
+             6968 => $expand!(-1224),
+             6976 => $expand!(-1216),
+             6984 => $expand!(-1208),
+             6992 => $expand!(-1200),
+             6900 => $expand!(-1192),
+             7008 => $expand!(-1184),
+             7016 => $expand!(-1176),
+             7024 => $expand!(-1168),
+             7032 => $expand!(-1160),
+             7040 => $expand!(-1152),
+             7048 => $expand!(-1144),
+             7056 => $expand!(-1136),
+             7064 => $expand!(-1128),
+             7072 => $expand!(-1120),
+             7080 => $expand!(-1112),
+             7088 => $expand!(-1104),
+             7096 => $expand!(-1096),
+             7104 => $expand!(-1088),
+             7112 => $expand!(-1080),
+             7120 => $expand!(-1072),
+             7128 => $expand!(-1064),
+             7136 => $expand!(-1056),
+             7144 => $expand!(-1048),
+             7152 => $expand!(-1040),
+             7160 => $expand!(-1032),
+             7168 => $expand!(-1024),
+             7176 => $expand!(-1016),
+             7184 => $expand!(-1008),
+             7192 => $expand!(-1000),
+             7100 => $expand!(-992),
+             7208 => $expand!(-984),
+             7216 => $expand!(-976),
+             7224 => $expand!(-968),
+             7232 => $expand!(-960),
+             7240 => $expand!(-952),
+             7248 => $expand!(-944),
+             7256 => $expand!(-936),
+             7264 => $expand!(-928),
+             7272 => $expand!(-920),
+             7280 => $expand!(-912),
+             7288 => $expand!(-904),
+             7296 => $expand!(-896),
+             7304 => $expand!(-888),
+             7312 => $expand!(-880),
+             7320 => $expand!(-872),
+             7328 => $expand!(-864),
+             7336 => $expand!(-856),
+             7344 => $expand!(-848),
+             7352 => $expand!(-840),
+             7360 => $expand!(-832),
+             7368 => $expand!(-824),
+             7376 => $expand!(-816),
+             7384 => $expand!(-808),
+             7392 => $expand!(-800),
+             7400 => $expand!(-792),
+             7408 => $expand!(-784),
+             7416 => $expand!(-776),
+             7424 => $expand!(-768),
+             7432 => $expand!(-760),
+             7440 => $expand!(-752),
+             7448 => $expand!(-744),
+             7456 => $expand!(-736),
+             7464 => $expand!(-728),
+             7472 => $expand!(-720),
+             7480 => $expand!(-712),
+             7488 => $expand!(-704),
+             7496 => $expand!(-696),
+             7504 => $expand!(-688),
+             7512 => $expand!(-680),
+             7520 => $expand!(-672),
+             7528 => $expand!(-664),
+             7536 => $expand!(-656),
+             7544 => $expand!(-648),
+             7552 => $expand!(-640),
+             7560 => $expand!(-632),
+             7568 => $expand!(-624),
+             7576 => $expand!(-616),
+             7584 => $expand!(-608),
+             7592 => $expand!(-600),
+             7600 => $expand!(-592),
+             7608 => $expand!(-584),
+             7616 => $expand!(-576),
+             7624 => $expand!(-568),
+             7632 => $expand!(-560),
+             7640 => $expand!(-552),
+             7648 => $expand!(-544),
+             7656 => $expand!(-536),
+             7664 => $expand!(-528),
+             7672 => $expand!(-520),
+             7680 => $expand!(-512),
+             7688 => $expand!(-504),
+             7696 => $expand!(-496),
+             7704 => $expand!(-488),
+             7712 => $expand!(-480),
+             7720 => $expand!(-472),
+             7728 => $expand!(-464),
+             7736 => $expand!(-456),
+             7744 => $expand!(-448),
+             7752 => $expand!(-440),
+             7760 => $expand!(-432),
+             7768 => $expand!(-424),
+             7776 => $expand!(-416),
+             7784 => $expand!(-408),
+             7792 => $expand!(-400),
+             7700 => $expand!(-392),
+             7808 => $expand!(-384),
+             7816 => $expand!(-376),
+             7824 => $expand!(-368),
+             7832 => $expand!(-360),
+             7840 => $expand!(-352),
+             7848 => $expand!(-344),
+             7856 => $expand!(-336),
+             7864 => $expand!(-328),
+             7872 => $expand!(-320),
+             7880 => $expand!(-312),
+             7888 => $expand!(-304),
+             7896 => $expand!(-296),
+             7904 => $expand!(-288),
+             7912 => $expand!(-280),
+             7920 => $expand!(-272),
+             7928 => $expand!(-264),
+             7936 => $expand!(-256),
+             7944 => $expand!(-248),
+             7952 => $expand!(-240),
+             7960 => $expand!(-232),
+             7968 => $expand!(-224),
+             7976 => $expand!(-216),
+             7984 => $expand!(-208),
+             7992 => $expand!(-200),
+             8000 => $expand!(-192),
+             8008 => $expand!(-184),
+             8016 => $expand!(-176),
+             8024 => $expand!(-168),
+             8032 => $expand!(-160),
+             8040 => $expand!(-152),
+             8048 => $expand!(-144),
+             8056 => $expand!(-136),
+             8064 => $expand!(-128),
+             8072 => $expand!(-120),
+             8080 => $expand!(-112),
+             8088 => $expand!(-104),
+             8096 => $expand!(-96),
+             8104 => $expand!(-88),
+             8112 => $expand!(-80),
+             8120 => $expand!(-72),
+             8128 => $expand!(-64),
+             8136 => $expand!(-56),
+             8144 => $expand!(-48),
+             8152 => $expand!(-40),
+             8160 => $expand!(-32),
+             8168 => $expand!(-24),
+             8176 => $expand!(-16),
+             8184 => $expand!(-8),
+             _ => $expand!(4088),
+         }
+     };
+ }
+ 
+ //immediate value: -2048:2044
+ macro_rules! constify_imm_s12 {
+     ($imm_s12:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm_s12) & 0b1111_1111_1111 {
+             0 => $expand!(0),
+             4 => $expand!(4),
+             8 => $expand!(8),
+             12 => $expand!(12),
+             16 => $expand!(16),
+             20 => $expand!(20),
+             24 => $expand!(24),
+             28 => $expand!(28),
+             32 => $expand!(32),
+             36 => $expand!(36),
+             40 => $expand!(40),
+             44 => $expand!(44),
+             48 => $expand!(48),
+             52 => $expand!(52),
+             56 => $expand!(56),
+             60 => $expand!(60),
+             64 => $expand!(64),
+             68 => $expand!(68),
+             72 => $expand!(72),
+             76 => $expand!(76),
+             80 => $expand!(80),
+             84 => $expand!(84),
+             88 => $expand!(88),
+             92 => $expand!(92),
+             96 => $expand!(96),
+             100 => $expand!(100),
+             104 => $expand!(104),
+             108 => $expand!(108),
+             112 => $expand!(112),
+             116 => $expand!(116),
+             120 => $expand!(120),
+             124 => $expand!(124),
+             128 => $expand!(128),
+             132 => $expand!(132),
+             136 => $expand!(136),
+             140 => $expand!(140),
+             144 => $expand!(144),
+             148 => $expand!(148),
+             152 => $expand!(152),
+             156 => $expand!(156),
+             160 => $expand!(160),
+             164 => $expand!(164),
+             168 => $expand!(168),
+             172 => $expand!(172),
+             176 => $expand!(176),
+             180 => $expand!(180),
+             184 => $expand!(184),
+             188 => $expand!(188),
+             192 => $expand!(192),
+             196 => $expand!(196),
+             200 => $expand!(200),
+             204 => $expand!(204),
+             208 => $expand!(208),
+             212 => $expand!(212),
+             216 => $expand!(216),
+             220 => $expand!(220),
+             224 => $expand!(224),
+             228 => $expand!(228),
+             232 => $expand!(232),
+             236 => $expand!(236),
+             240 => $expand!(240),
+             244 => $expand!(244),
+             248 => $expand!(248),
+             252 => $expand!(252),
+             256 => $expand!(256),
+             260 => $expand!(260),
+             264 => $expand!(264),
+             268 => $expand!(268),
+             272 => $expand!(272),
+             276 => $expand!(276),
+             280 => $expand!(280),
+             284 => $expand!(284),
+             288 => $expand!(288),
+             292 => $expand!(292),
+             296 => $expand!(296),
+             300 => $expand!(300),
+             304 => $expand!(304),
+             308 => $expand!(308),
+             312 => $expand!(312),
+             316 => $expand!(316),
+             320 => $expand!(320),
+             324 => $expand!(324),
+             328 => $expand!(328),
+             332 => $expand!(332),
+             336 => $expand!(336),
+             340 => $expand!(340),
+             344 => $expand!(344),
+             348 => $expand!(348),
+             352 => $expand!(352),
+             356 => $expand!(356),
+             360 => $expand!(360),
+             364 => $expand!(364),
+             368 => $expand!(368),
+             372 => $expand!(372),
+             376 => $expand!(376),
+             380 => $expand!(380),
+             384 => $expand!(384),
+             388 => $expand!(388),
+             392 => $expand!(392),
+             396 => $expand!(396),
+             400 => $expand!(400),
+             404 => $expand!(404),
+             408 => $expand!(408),
+             412 => $expand!(412),
+             416 => $expand!(416),
+             420 => $expand!(420),
+             424 => $expand!(424),
+             428 => $expand!(428),
+             432 => $expand!(432),
+             436 => $expand!(436),
+             440 => $expand!(440),
+             444 => $expand!(444),
+             448 => $expand!(448),
+             452 => $expand!(452),
+             456 => $expand!(456),
+             460 => $expand!(460),
+             464 => $expand!(464),
+             468 => $expand!(468),
+             472 => $expand!(472),
+             476 => $expand!(476),
+             480 => $expand!(480),
+             484 => $expand!(484),
+             488 => $expand!(488),
+             492 => $expand!(492),
+             496 => $expand!(496),
+             500 => $expand!(500),
+             504 => $expand!(504),
+             508 => $expand!(508),
+             512 => $expand!(512),
+             516 => $expand!(516),
+             520 => $expand!(520),
+             524 => $expand!(524),
+             528 => $expand!(528),
+             532 => $expand!(532),
+             536 => $expand!(536),
+             540 => $expand!(540),
+             544 => $expand!(544),
+             548 => $expand!(548),
+             552 => $expand!(552),
+             556 => $expand!(556),
+             560 => $expand!(560),
+             564 => $expand!(564),
+             568 => $expand!(568),
+             572 => $expand!(572),
+             576 => $expand!(576),
+             580 => $expand!(580),
+             584 => $expand!(584),
+             588 => $expand!(588),
+             592 => $expand!(592),
+             596 => $expand!(596),
+             600 => $expand!(600),
+             604 => $expand!(604),
+             608 => $expand!(608),
+             612 => $expand!(612),
+             616 => $expand!(616),
+             620 => $expand!(620),
+             624 => $expand!(624),
+             628 => $expand!(628),
+             632 => $expand!(632),
+             636 => $expand!(636),
+             640 => $expand!(640),
+             644 => $expand!(644),
+             648 => $expand!(648),
+             652 => $expand!(652),
+             656 => $expand!(656),
+             660 => $expand!(660),
+             664 => $expand!(664),
+             668 => $expand!(668),
+             672 => $expand!(672),
+             676 => $expand!(676),
+             680 => $expand!(680),
+             684 => $expand!(684),
+             688 => $expand!(688),
+             692 => $expand!(692),
+             696 => $expand!(696),
+             700 => $expand!(700),
+             704 => $expand!(704),
+             708 => $expand!(708),
+             712 => $expand!(712),
+             716 => $expand!(716),
+             720 => $expand!(720),
+             724 => $expand!(724),
+             728 => $expand!(728),
+             732 => $expand!(732),
+             736 => $expand!(736),
+             740 => $expand!(740),
+             744 => $expand!(744),
+             748 => $expand!(748),
+             752 => $expand!(752),
+             756 => $expand!(756),
+             760 => $expand!(760),
+             764 => $expand!(764),
+             768 => $expand!(768),
+             772 => $expand!(772),
+             776 => $expand!(776),
+             780 => $expand!(780),
+             784 => $expand!(784),
+             788 => $expand!(788),
+             792 => $expand!(792),
+             800 => $expand!(800),
+             804 => $expand!(804),
+             808 => $expand!(808),
+             812 => $expand!(812),
+             816 => $expand!(816),
+             820 => $expand!(820),
+             824 => $expand!(824),
+             828 => $expand!(828),
+             832 => $expand!(832),
+             836 => $expand!(836),
+             840 => $expand!(840),
+             844 => $expand!(844),
+             848 => $expand!(848),
+             852 => $expand!(852),
+             856 => $expand!(856),
+             860 => $expand!(860),
+             864 => $expand!(864),
+             868 => $expand!(868),
+             872 => $expand!(872),
+             876 => $expand!(876),
+             880 => $expand!(880),
+             884 => $expand!(884),
+             888 => $expand!(888),
+             892 => $expand!(892),
+             896 => $expand!(896),
+             900 => $expand!(900),
+             904 => $expand!(904),
+             908 => $expand!(908),
+             912 => $expand!(912),
+             916 => $expand!(916),
+             920 => $expand!(920),
+             924 => $expand!(924),
+             928 => $expand!(928),
+             932 => $expand!(932),
+             936 => $expand!(936),
+             940 => $expand!(940),
+             944 => $expand!(944),
+             948 => $expand!(948),
+             952 => $expand!(952),
+             956 => $expand!(956),
+             960 => $expand!(960),
+             964 => $expand!(964),
+             968 => $expand!(968),
+             972 => $expand!(972),
+             976 => $expand!(976),
+             980 => $expand!(980),
+             984 => $expand!(984),
+             988 => $expand!(988),
+             992 => $expand!(992),
+             996 => $expand!(996),
+             1000 => $expand!(1000),
+             1004 => $expand!(1004),
+             1008 => $expand!(1008),
+             1012 => $expand!(1012),
+             1016 => $expand!(1016),
+             1020 => $expand!(1020),
+             1024 => $expand!(1024),
+             1028 => $expand!(1028),
+             1032 => $expand!(1032),
+             1036 => $expand!(1036),
+             1040 => $expand!(1040),
+             1044 => $expand!(1044),
+             1048 => $expand!(1048),
+             1052 => $expand!(1052),
+             1056 => $expand!(1056),
+             1060 => $expand!(1060),
+             1064 => $expand!(1064),
+             1068 => $expand!(1068),
+             1072 => $expand!(1072),
+             1076 => $expand!(1076),
+             1080 => $expand!(1080),
+             1084 => $expand!(1084),
+             1088 => $expand!(1088),
+             1092 => $expand!(1092),
+             1096 => $expand!(1096),
+             1100 => $expand!(1100),
+             1104 => $expand!(1104),
+             1108 => $expand!(1108),
+             1112 => $expand!(1112),
+             1116 => $expand!(1116),
+             1120 => $expand!(1120),
+             1124 => $expand!(1124),
+             1128 => $expand!(1128),
+             1132 => $expand!(1132),
+             1136 => $expand!(1136),
+             1140 => $expand!(1140),
+             1144 => $expand!(1144),
+             1148 => $expand!(1148),
+             1152 => $expand!(1152),
+             1156 => $expand!(1156),
+             1160 => $expand!(1160),
+             1164 => $expand!(1164),
+             1168 => $expand!(1168),
+             1172 => $expand!(1172),
+             1176 => $expand!(1176),
+             1180 => $expand!(1180),
+             1184 => $expand!(1184),
+             1188 => $expand!(1188),
+             1192 => $expand!(1192),
+             1196 => $expand!(1196),
+             1200 => $expand!(1200),
+             1204 => $expand!(1204),
+             1208 => $expand!(1208),
+             1212 => $expand!(1212),
+             1216 => $expand!(1216),
+             1220 => $expand!(1220),
+             1224 => $expand!(1224),
+             1228 => $expand!(1228),
+             1232 => $expand!(1232),
+             1236 => $expand!(1236),
+             1240 => $expand!(1240),
+             1244 => $expand!(1244),
+             1248 => $expand!(1248),
+             1252 => $expand!(1252),
+             1256 => $expand!(1256),
+             1260 => $expand!(1260),
+             1264 => $expand!(1264),
+             1268 => $expand!(1268),
+             1272 => $expand!(1272),
+             1276 => $expand!(1276),
+             1280 => $expand!(1280),
+             1284 => $expand!(1284),
+             1288 => $expand!(1288),
+             1292 => $expand!(1292),
+             1296 => $expand!(1296),
+             1300 => $expand!(1300),
+             1304 => $expand!(1304),
+             1308 => $expand!(1308),
+             1312 => $expand!(1312),
+             1316 => $expand!(1316),
+             1320 => $expand!(1320),
+             1324 => $expand!(1324),
+             1328 => $expand!(1328),
+             1332 => $expand!(1332),
+             1336 => $expand!(1336),
+             1340 => $expand!(1340),
+             1344 => $expand!(1344),
+             1348 => $expand!(1348),
+             1352 => $expand!(1352),
+             1356 => $expand!(1356),
+             1360 => $expand!(1360),
+             1364 => $expand!(1364),
+             1368 => $expand!(1368),
+             1372 => $expand!(1372),
+             1376 => $expand!(1376),
+             1380 => $expand!(1380),
+             1384 => $expand!(1384),
+             1388 => $expand!(1388),
+             1392 => $expand!(1392),
+             1396 => $expand!(1396),
+             1400 => $expand!(1400),
+             1404 => $expand!(1404),
+             1408 => $expand!(1408),
+             1412 => $expand!(1412),
+             1416 => $expand!(1416),
+             1420 => $expand!(1420),
+             1424 => $expand!(1424),
+             1428 => $expand!(1428),
+             1432 => $expand!(1432),
+             1436 => $expand!(1436),
+             1440 => $expand!(1440),
+             1444 => $expand!(1444),
+             1448 => $expand!(1448),
+             1452 => $expand!(1452),
+             1456 => $expand!(1456),
+             1460 => $expand!(1460),
+             1464 => $expand!(1464),
+             1468 => $expand!(1468),
+             1472 => $expand!(1472),
+             1476 => $expand!(1476),
+             1480 => $expand!(1480),
+             1484 => $expand!(1484),
+             1488 => $expand!(1488),
+             1492 => $expand!(1492),
+             1496 => $expand!(1496),
+             1500 => $expand!(1500),
+             1504 => $expand!(1504),
+             1508 => $expand!(1508),
+             1512 => $expand!(1512),
+             1516 => $expand!(1516),
+             1520 => $expand!(1520),
+             1524 => $expand!(1524),
+             1528 => $expand!(1528),
+             1532 => $expand!(1532),
+             1536 => $expand!(1536),
+             1540 => $expand!(1540),
+             1544 => $expand!(1544),
+             1548 => $expand!(1548),
+             1552 => $expand!(1552),
+             1556 => $expand!(1556),
+             1560 => $expand!(1560),
+             1564 => $expand!(1564),
+             1568 => $expand!(1568),
+             1572 => $expand!(1572),
+             1576 => $expand!(1576),
+             1580 => $expand!(1580),
+             1584 => $expand!(1584),
+             1588 => $expand!(1588),
+             1592 => $expand!(1592),
+             1596 => $expand!(1596),
+             1600 => $expand!(1600),
+             1604 => $expand!(1604),
+             1608 => $expand!(1608),
+             1612 => $expand!(1612),
+             1616 => $expand!(1616),
+             1620 => $expand!(1620),
+             1624 => $expand!(1624),
+             1628 => $expand!(1628),
+             1632 => $expand!(1632),
+             1636 => $expand!(1636),
+             1640 => $expand!(1640),
+             1644 => $expand!(1644),
+             1648 => $expand!(1648),
+             1652 => $expand!(1652),
+             1656 => $expand!(1656),
+             1660 => $expand!(1660),
+             1664 => $expand!(1664),
+             1668 => $expand!(1668),
+             1672 => $expand!(1672),
+             1676 => $expand!(1676),
+             1680 => $expand!(1680),
+             1684 => $expand!(1684),
+             1688 => $expand!(1688),
+             1692 => $expand!(1692),
+             1696 => $expand!(1696),
+             1700 => $expand!(1700),
+             1704 => $expand!(1704),
+             1708 => $expand!(1708),
+             1712 => $expand!(1712),
+             1716 => $expand!(1716),
+             1720 => $expand!(1720),
+             1724 => $expand!(1724),
+             1728 => $expand!(1728),
+             1732 => $expand!(1732),
+             1736 => $expand!(1736),
+             1740 => $expand!(1740),
+             1744 => $expand!(1744),
+             1748 => $expand!(1748),
+             1752 => $expand!(1752),
+             1756 => $expand!(1756),
+             1760 => $expand!(1760),
+             1764 => $expand!(1764),
+             1768 => $expand!(1768),
+             1772 => $expand!(1772),
+             1776 => $expand!(1776),
+             1780 => $expand!(1780),
+             1784 => $expand!(1784),
+             1788 => $expand!(1788),
+             1792 => $expand!(1792),
+             1796 => $expand!(1796),
+             1800 => $expand!(1800),
+             1804 => $expand!(1804),
+             1808 => $expand!(1808),
+             1812 => $expand!(1812),
+             1816 => $expand!(1816),
+             1820 => $expand!(1820),
+             1824 => $expand!(1824),
+             1828 => $expand!(1828),
+             1832 => $expand!(1832),
+             1836 => $expand!(1836),
+             1840 => $expand!(1840),
+             1844 => $expand!(1844),
+             1848 => $expand!(1848),
+             1852 => $expand!(1852),
+             1856 => $expand!(1856),
+             1860 => $expand!(1860),
+             1864 => $expand!(1864),
+             1868 => $expand!(1868),
+             1872 => $expand!(1872),
+             1876 => $expand!(1876),
+             1880 => $expand!(1880),
+             1884 => $expand!(1884),
+             1888 => $expand!(1888),
+             1892 => $expand!(1892),
+             1896 => $expand!(1896),
+             1900 => $expand!(1900),
+             1904 => $expand!(1904),
+             1908 => $expand!(1908),
+             1912 => $expand!(1912),
+             1916 => $expand!(1916),
+             1920 => $expand!(1920),
+             1924 => $expand!(1924),
+             1928 => $expand!(1928),
+             1932 => $expand!(1932),
+             1936 => $expand!(1936),
+             1940 => $expand!(1940),
+             1944 => $expand!(1944),
+             1948 => $expand!(1948),
+             1952 => $expand!(1952),
+             1956 => $expand!(1956),
+             1960 => $expand!(1960),
+             1964 => $expand!(1964),
+             1968 => $expand!(1968),
+             1972 => $expand!(1972),
+             1976 => $expand!(1976),
+             1980 => $expand!(1980),
+             1984 => $expand!(1984),
+             1988 => $expand!(1988),
+             1992 => $expand!(1992),
+             1996 => $expand!(1996),
+             2000 => $expand!(2000),
+             2004 => $expand!(2004),
+             2008 => $expand!(2008),
+             2012 => $expand!(2012),
+             2016 => $expand!(2016),
+             2020 => $expand!(2020),
+             2024 => $expand!(2024),
+             2028 => $expand!(2028),
+             2032 => $expand!(2032),
+             2036 => $expand!(2036),
+             2040 => $expand!(2040),
+             2048 => $expand!(-2048),
+             2052 => $expand!(-2044),
+             2056 => $expand!(-2040),
+             2060 => $expand!(-2036),
+             2064 => $expand!(-2032),
+             2068 => $expand!(-2028),
+             2072 => $expand!(-2024),
+             2076 => $expand!(-2020),
+             2080 => $expand!(-2016),
+             2084 => $expand!(-2012),
+             2088 => $expand!(-2008),
+             2092 => $expand!(-2004),
+             2096 => $expand!(-2000),
+             2100 => $expand!(-1996),
+             2104 => $expand!(-1992),
+             2108 => $expand!(-1988),
+             2112 => $expand!(-1984),
+             2116 => $expand!(-1980),
+             2120 => $expand!(-1976),
+             2124 => $expand!(-1972),
+             2128 => $expand!(-1968),
+             2132 => $expand!(-1964),
+             2136 => $expand!(-1960),
+             2140 => $expand!(-1956),
+             2144 => $expand!(-1952),
+             2148 => $expand!(-1948),
+             2152 => $expand!(-1944),
+             2156 => $expand!(-1940),
+             2160 => $expand!(-1936),
+             2164 => $expand!(-1932),
+             2168 => $expand!(-1928),
+             2172 => $expand!(-1924),
+             2176 => $expand!(-1920),
+             2180 => $expand!(-1916),
+             2184 => $expand!(-1912),
+             2188 => $expand!(-1908),
+             2192 => $expand!(-1904),
+             2196 => $expand!(-1900),
+             2200 => $expand!(-1896),
+             2204 => $expand!(-1892),
+             2208 => $expand!(-1888),
+             2212 => $expand!(-1884),
+             2216 => $expand!(-1880),
+             2220 => $expand!(-1876),
+             2224 => $expand!(-1872),
+             2228 => $expand!(-1868),
+             2232 => $expand!(-1864),
+             2236 => $expand!(-1860),
+             2240 => $expand!(-1856),
+             2244 => $expand!(-1852),
+             2248 => $expand!(-1848),
+             2252 => $expand!(-1844),
+             2256 => $expand!(-1840),
+             2260 => $expand!(-1836),
+             2264 => $expand!(-1832),
+             2268 => $expand!(-1828),
+             2272 => $expand!(-1824),
+             2276 => $expand!(-1820),
+             2280 => $expand!(-1816),
+             2284 => $expand!(-1812),
+             2288 => $expand!(-1808),
+             2292 => $expand!(-1804),
+             2296 => $expand!(-1800),
+             2300 => $expand!(-1796),
+             2304 => $expand!(-1792),
+             2308 => $expand!(-1788),
+             2312 => $expand!(-1784),
+             2316 => $expand!(-1780),
+             2320 => $expand!(-1776),
+             2324 => $expand!(-1772),
+             2328 => $expand!(-1768),
+             2332 => $expand!(-1764),
+             2336 => $expand!(-1760),
+             2340 => $expand!(-1756),
+             2344 => $expand!(-1752),
+             2348 => $expand!(-1748),
+             2352 => $expand!(-1744),
+             2356 => $expand!(-1740),
+             2360 => $expand!(-1736),
+             2364 => $expand!(-1732),
+             2368 => $expand!(-1728),
+             2372 => $expand!(-1724),
+             2376 => $expand!(-1720),
+             2380 => $expand!(-1716),
+             2384 => $expand!(-1712),
+             2388 => $expand!(-1708),
+             2392 => $expand!(-1704),
+             2396 => $expand!(-1700),
+             2400 => $expand!(-1696),
+             2404 => $expand!(-1692),
+             2408 => $expand!(-1688),
+             2412 => $expand!(-1684),
+             2416 => $expand!(-1680),
+             2420 => $expand!(-1676),
+             2424 => $expand!(-1672),
+             2428 => $expand!(-1668),
+             2432 => $expand!(-1664),
+             2436 => $expand!(-1660),
+             2440 => $expand!(-1656),
+             2444 => $expand!(-1652),
+             2448 => $expand!(-1648),
+             2452 => $expand!(-1644),
+             2456 => $expand!(-1640),
+             2460 => $expand!(-1636),
+             2464 => $expand!(-1632),
+             2468 => $expand!(-1628),
+             2472 => $expand!(-1624),
+             2476 => $expand!(-1620),
+             2480 => $expand!(-1616),
+             2484 => $expand!(-1612),
+             2488 => $expand!(-1608),
+             2492 => $expand!(-1604),
+             2496 => $expand!(-1600),
+             2500 => $expand!(-1596),
+             2504 => $expand!(-1592),
+             2508 => $expand!(-1588),
+             2512 => $expand!(-1584),
+             2516 => $expand!(-1580),
+             2520 => $expand!(-1576),
+             2524 => $expand!(-1572),
+             2528 => $expand!(-1568),
+             2532 => $expand!(-1564),
+             2536 => $expand!(-1560),
+             2540 => $expand!(-1556),
+             2544 => $expand!(-1552),
+             2548 => $expand!(-1548),
+             2552 => $expand!(-1544),
+             2556 => $expand!(-1540),
+             2560 => $expand!(-1536),
+             2564 => $expand!(-1532),
+             2568 => $expand!(-1528),
+             2572 => $expand!(-1524),
+             2576 => $expand!(-1520),
+             2580 => $expand!(-1516),
+             2584 => $expand!(-1512),
+             2588 => $expand!(-1508),
+             2592 => $expand!(-1504),
+             2596 => $expand!(-1500),
+             2600 => $expand!(-1496),
+             2604 => $expand!(-1492),
+             2608 => $expand!(-1488),
+             2612 => $expand!(-1484),
+             2616 => $expand!(-1480),
+             2620 => $expand!(-1476),
+             2624 => $expand!(-1472),
+             2628 => $expand!(-1468),
+             2632 => $expand!(-1464),
+             2636 => $expand!(-1460),
+             2640 => $expand!(-1456),
+             2644 => $expand!(-1452),
+             2648 => $expand!(-1448),
+             2652 => $expand!(-1444),
+             2656 => $expand!(-1440),
+             2660 => $expand!(-1436),
+             2664 => $expand!(-1432),
+             2668 => $expand!(-1428),
+             2672 => $expand!(-1424),
+             2676 => $expand!(-1420),
+             2680 => $expand!(-1416),
+             2684 => $expand!(-1412),
+             2688 => $expand!(-1408),
+             2692 => $expand!(-1404),
+             2696 => $expand!(-1400),
+             2700 => $expand!(-1396),
+             2704 => $expand!(-1392),
+             2708 => $expand!(-1388),
+             2712 => $expand!(-1384),
+             2716 => $expand!(-1380),
+             2720 => $expand!(-1376),
+             2724 => $expand!(-1372),
+             2728 => $expand!(-1368),
+             2732 => $expand!(-1364),
+             2736 => $expand!(-1360),
+             2740 => $expand!(-1356),
+             2744 => $expand!(-1352),
+             2748 => $expand!(-1348),
+             2752 => $expand!(-1344),
+             2756 => $expand!(-1340),
+             2760 => $expand!(-1336),
+             2764 => $expand!(-1332),
+             2768 => $expand!(-1328),
+             2772 => $expand!(-1324),
+             2776 => $expand!(-1320),
+             2780 => $expand!(-1316),
+             2784 => $expand!(-1312),
+             2788 => $expand!(-1308),
+             2792 => $expand!(-1304),
+             2796 => $expand!(-1300),
+             2800 => $expand!(-1296),
+             2804 => $expand!(-1292),
+             2808 => $expand!(-1288),
+             2812 => $expand!(-1284),
+             2816 => $expand!(-1280),
+             2820 => $expand!(-1276),
+             2824 => $expand!(-1272),
+             2828 => $expand!(-1268),
+             2832 => $expand!(-1264),
+             2836 => $expand!(-1260),
+             2840 => $expand!(-1256),
+             2844 => $expand!(-1252),
+             2848 => $expand!(-1248),
+             2852 => $expand!(-1244),
+             2856 => $expand!(-1240),
+             2860 => $expand!(-1236),
+             2864 => $expand!(-1232),
+             2868 => $expand!(-1228),
+             2872 => $expand!(-1224),
+             2876 => $expand!(-1220),
+             2880 => $expand!(-1216),
+             2884 => $expand!(-1212),
+             2888 => $expand!(-1208),
+             2892 => $expand!(-1204),
+             2896 => $expand!(-1200),
+             2900 => $expand!(-1196),
+             2904 => $expand!(-1192),
+             2908 => $expand!(-1188),
+             2912 => $expand!(-1184),
+             2916 => $expand!(-1180),
+             2920 => $expand!(-1176),
+             2924 => $expand!(-1172),
+             2928 => $expand!(-1168),
+             2932 => $expand!(-1164),
+             2936 => $expand!(-1160),
+             2940 => $expand!(-1156),
+             2944 => $expand!(-1152),
+             2948 => $expand!(-1148),
+             2952 => $expand!(-1144),
+             2956 => $expand!(-1140),
+             2960 => $expand!(-1136),
+             2964 => $expand!(-1132),
+             2968 => $expand!(-1128),
+             2972 => $expand!(-1124),
+             2976 => $expand!(-1120),
+             2980 => $expand!(-1116),
+             2984 => $expand!(-1112),
+             2988 => $expand!(-1108),
+             2992 => $expand!(-1104),
+             2996 => $expand!(-1100),
+             3000 => $expand!(-1096),
+             3004 => $expand!(-1092),
+             3008 => $expand!(-1088),
+             3012 => $expand!(-1084),
+             3016 => $expand!(-1080),
+             3020 => $expand!(-1076),
+             3024 => $expand!(-1072),
+             3028 => $expand!(-1068),
+             3032 => $expand!(-1064),
+             3036 => $expand!(-1060),
+             3040 => $expand!(-1056),
+             3044 => $expand!(-1052),
+             3048 => $expand!(-1048),
+             3052 => $expand!(-1044),
+             3056 => $expand!(-1040),
+             3060 => $expand!(-1036),
+             3064 => $expand!(-1032),
+             3068 => $expand!(-1028),
+             3072 => $expand!(-1024),
+             3076 => $expand!(-1020),
+             3080 => $expand!(-1016),
+             3084 => $expand!(-1012),
+             3088 => $expand!(-1008),
+             3092 => $expand!(-1004),
+             3096 => $expand!(-1000),
+             3100 => $expand!(-996),
+             3104 => $expand!(-992),
+             3108 => $expand!(-988),
+             3112 => $expand!(-984),
+             3116 => $expand!(-980),
+             3120 => $expand!(-976),
+             3124 => $expand!(-972),
+             3128 => $expand!(-968),
+             3132 => $expand!(-964),
+             3136 => $expand!(-960),
+             3140 => $expand!(-956),
+             3144 => $expand!(-952),
+             3148 => $expand!(-948),
+             3152 => $expand!(-944),
+             3156 => $expand!(-940),
+             3160 => $expand!(-936),
+             3164 => $expand!(-932),
+             3168 => $expand!(-928),
+             3172 => $expand!(-924),
+             3176 => $expand!(-920),
+             3180 => $expand!(-916),
+             3184 => $expand!(-912),
+             3188 => $expand!(-908),
+             3192 => $expand!(-904),
+             3196 => $expand!(-900),
+             3200 => $expand!(-896),
+             3204 => $expand!(-892),
+             3208 => $expand!(-888),
+             3212 => $expand!(-884),
+             3216 => $expand!(-880),
+             3220 => $expand!(-876),
+             3224 => $expand!(-872),
+             3228 => $expand!(-868),
+             3232 => $expand!(-864),
+             3236 => $expand!(-860),
+             3240 => $expand!(-856),
+             3244 => $expand!(-852),
+             3248 => $expand!(-848),
+             3252 => $expand!(-844),
+             3256 => $expand!(-840),
+             3260 => $expand!(-836),
+             3264 => $expand!(-832),
+             3268 => $expand!(-828),
+             3272 => $expand!(-824),
+             3276 => $expand!(-820),
+             3280 => $expand!(-816),
+             3284 => $expand!(-812),
+             3288 => $expand!(-808),
+             3292 => $expand!(-804),
+             3296 => $expand!(-800),
+             3300 => $expand!(-796),
+             3304 => $expand!(-792),
+             3308 => $expand!(-788),
+             3312 => $expand!(-784),
+             3316 => $expand!(-780),
+             3320 => $expand!(-776),
+             3324 => $expand!(-772),
+             3328 => $expand!(-768),
+             3332 => $expand!(-764),
+             3336 => $expand!(-760),
+             3340 => $expand!(-756),
+             3344 => $expand!(-752),
+             3348 => $expand!(-748),
+             3352 => $expand!(-744),
+             3356 => $expand!(-740),
+             3360 => $expand!(-736),
+             3364 => $expand!(-732),
+             3368 => $expand!(-728),
+             3372 => $expand!(-724),
+             3376 => $expand!(-720),
+             3380 => $expand!(-716),
+             3384 => $expand!(-712),
+             3388 => $expand!(-708),
+             3392 => $expand!(-704),
+             3396 => $expand!(-700),
+             3400 => $expand!(-696),
+             3404 => $expand!(-692),
+             3408 => $expand!(-688),
+             3412 => $expand!(-684),
+             3416 => $expand!(-680),
+             3420 => $expand!(-676),
+             3424 => $expand!(-672),
+             3428 => $expand!(-668),
+             3432 => $expand!(-664),
+             3436 => $expand!(-660),
+             3440 => $expand!(-656),
+             3444 => $expand!(-652),
+             3448 => $expand!(-648),
+             3452 => $expand!(-644),
+             3456 => $expand!(-640),
+             3460 => $expand!(-636),
+             3464 => $expand!(-632),
+             3468 => $expand!(-628),
+             3472 => $expand!(-624),
+             3476 => $expand!(-620),
+             3480 => $expand!(-616),
+             3484 => $expand!(-612),
+             3488 => $expand!(-608),
+             3492 => $expand!(-604),
+             3496 => $expand!(-600),
+             3500 => $expand!(-596),
+             3504 => $expand!(-592),
+             3508 => $expand!(-588),
+             3512 => $expand!(-584),
+             3516 => $expand!(-580),
+             3520 => $expand!(-576),
+             3524 => $expand!(-572),
+             3528 => $expand!(-568),
+             3532 => $expand!(-564),
+             3536 => $expand!(-560),
+             3540 => $expand!(-556),
+             3544 => $expand!(-552),
+             3548 => $expand!(-548),
+             3552 => $expand!(-544),
+             3556 => $expand!(-540),
+             3560 => $expand!(-536),
+             3564 => $expand!(-532),
+             3568 => $expand!(-528),
+             3572 => $expand!(-524),
+             3576 => $expand!(-520),
+             3580 => $expand!(-516),
+             3584 => $expand!(-512),
+             3588 => $expand!(-508),
+             3592 => $expand!(-504),
+             3596 => $expand!(-500),
+             3600 => $expand!(-496),
+             3604 => $expand!(-492),
+             3608 => $expand!(-488),
+             3612 => $expand!(-484),
+             3616 => $expand!(-480),
+             3620 => $expand!(-476),
+             3624 => $expand!(-472),
+             3628 => $expand!(-468),
+             3632 => $expand!(-464),
+             3636 => $expand!(-460),
+             3640 => $expand!(-456),
+             3644 => $expand!(-452),
+             3648 => $expand!(-448),
+             3652 => $expand!(-444),
+             3656 => $expand!(-440),
+             3660 => $expand!(-436),
+             3664 => $expand!(-432),
+             3668 => $expand!(-428),
+             3672 => $expand!(-424),
+             3676 => $expand!(-420),
+             3680 => $expand!(-416),
+             3684 => $expand!(-412),
+             3688 => $expand!(-408),
+             3692 => $expand!(-404),
+             3696 => $expand!(-400),
+             3700 => $expand!(-396),
+             3704 => $expand!(-392),
+             3708 => $expand!(-388),
+             3712 => $expand!(-384),
+             3716 => $expand!(-380),
+             3720 => $expand!(-376),
+             3724 => $expand!(-372),
+             3728 => $expand!(-368),
+             3732 => $expand!(-364),
+             3736 => $expand!(-360),
+             3740 => $expand!(-356),
+             3744 => $expand!(-352),
+             3748 => $expand!(-348),
+             3752 => $expand!(-344),
+             3756 => $expand!(-340),
+             3760 => $expand!(-336),
+             3764 => $expand!(-332),
+             3768 => $expand!(-328),
+             3772 => $expand!(-324),
+             3776 => $expand!(-320),
+             3780 => $expand!(-316),
+             3784 => $expand!(-312),
+             3788 => $expand!(-308),
+             3792 => $expand!(-304),
+             3796 => $expand!(-300),
+             3800 => $expand!(-296),
+             3804 => $expand!(-292),
+             3808 => $expand!(-288),
+             3812 => $expand!(-284),
+             3816 => $expand!(-280),
+             3820 => $expand!(-276),
+             3824 => $expand!(-272),
+             3828 => $expand!(-268),
+             3832 => $expand!(-264),
+             3836 => $expand!(-260),
+             3840 => $expand!(-256),
+             3844 => $expand!(-252),
+             3848 => $expand!(-248),
+             3852 => $expand!(-244),
+             3856 => $expand!(-240),
+             3860 => $expand!(-236),
+             3864 => $expand!(-232),
+             3868 => $expand!(-228),
+             3872 => $expand!(-224),
+             3876 => $expand!(-220),
+             3880 => $expand!(-216),
+             3884 => $expand!(-212),
+             3888 => $expand!(-208),
+             3892 => $expand!(-204),
+             3896 => $expand!(-200),
+             3900 => $expand!(-196),
+             3904 => $expand!(-192),
+             3908 => $expand!(-188),
+             3912 => $expand!(-184),
+             3916 => $expand!(-180),
+             3920 => $expand!(-176),
+             3924 => $expand!(-172),
+             3928 => $expand!(-168),
+             3932 => $expand!(-164),
+             3936 => $expand!(-160),
+             3940 => $expand!(-156),
+             3944 => $expand!(-152),
+             3948 => $expand!(-148),
+             3952 => $expand!(-144),
+             3956 => $expand!(-140),
+             3960 => $expand!(-136),
+             3964 => $expand!(-132),
+             3968 => $expand!(-128),
+             3972 => $expand!(-124),
+             3976 => $expand!(-120),
+             3980 => $expand!(-116),
+             3984 => $expand!(-112),
+             3988 => $expand!(-108),
+             3992 => $expand!(-104),
+             3996 => $expand!(-100),
+             4000 => $expand!(-96),
+             4004 => $expand!(-92),
+             4008 => $expand!(-88),
+             4012 => $expand!(-84),
+             4016 => $expand!(-80),
+             4020 => $expand!(-76),
+             4024 => $expand!(-72),
+             4028 => $expand!(-68),
+             4032 => $expand!(-64),
+             4036 => $expand!(-60),
+             4040 => $expand!(-56),
+             4044 => $expand!(-52),
+             4048 => $expand!(-48),
+             4052 => $expand!(-44),
+             4056 => $expand!(-40),
+             4060 => $expand!(-36),
+             4064 => $expand!(-32),
+             4068 => $expand!(-28),
+             4072 => $expand!(-24),
+             4076 => $expand!(-20),
+             4080 => $expand!(-16),
+             4084 => $expand!(-12),
+             4088 => $expand!(-8),
+             4092 => $expand!(-4),
+             _ => $expand!(2044),
+         }
+     };
+ }
+ 
+ //immediate value: -1024:1022
+ macro_rules! constify_imm_s11 {
+     ($imm_s11:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm_s11) & 0b111_1111_1111 {
+             0 => $expand!(0),
+             2 => $expand!(2),
+             4 => $expand!(4),
+             6 => $expand!(6),
+             8 => $expand!(8),
+             10 => $expand!(10),
+             12 => $expand!(12),
+             14 => $expand!(14),
+             16 => $expand!(16),
+             18 => $expand!(18),
+             20 => $expand!(20),
+             22 => $expand!(22),
+             24 => $expand!(24),
+             26 => $expand!(26),
+             28 => $expand!(28),
+             30 => $expand!(30),
+             32 => $expand!(32),
+             34 => $expand!(34),
+             36 => $expand!(36),
+             38 => $expand!(38),
+             40 => $expand!(40),
+             42 => $expand!(42),
+             44 => $expand!(44),
+             46 => $expand!(46),
+             48 => $expand!(48),
+             50 => $expand!(50),
+             52 => $expand!(52),
+             54 => $expand!(54),
+             56 => $expand!(56),
+             58 => $expand!(58),
+             60 => $expand!(60),
+             62 => $expand!(62),
+             64 => $expand!(64),
+             66 => $expand!(66),
+             68 => $expand!(68),
+             70 => $expand!(70),
+             72 => $expand!(72),
+             74 => $expand!(74),
+             76 => $expand!(76),
+             78 => $expand!(78),
+             80 => $expand!(80),
+             82 => $expand!(82),
+             84 => $expand!(84),
+             86 => $expand!(86),
+             88 => $expand!(88),
+             90 => $expand!(90),
+             92 => $expand!(92),
+             94 => $expand!(94),
+             96 => $expand!(96),
+             98 => $expand!(98),
+             100 => $expand!(100),
+             102 => $expand!(102),
+             104 => $expand!(104),
+             106 => $expand!(106),
+             108 => $expand!(108),
+             110 => $expand!(110),
+             112 => $expand!(112),
+             114 => $expand!(114),
+             116 => $expand!(116),
+             118 => $expand!(118),
+             120 => $expand!(120),
+             122 => $expand!(122),
+             124 => $expand!(124),
+             126 => $expand!(126),
+             128 => $expand!(128),
+             130 => $expand!(130),
+             132 => $expand!(132),
+             134 => $expand!(134),
+             136 => $expand!(136),
+             138 => $expand!(138),
+             140 => $expand!(140),
+             142 => $expand!(142),
+             144 => $expand!(144),
+             146 => $expand!(146),
+             148 => $expand!(148),
+             150 => $expand!(150),
+             152 => $expand!(152),
+             154 => $expand!(154),
+             156 => $expand!(156),
+             158 => $expand!(158),
+             160 => $expand!(160),
+             162 => $expand!(162),
+             164 => $expand!(164),
+             166 => $expand!(166),
+             168 => $expand!(168),
+             170 => $expand!(170),
+             172 => $expand!(172),
+             174 => $expand!(174),
+             176 => $expand!(176),
+             178 => $expand!(178),
+             180 => $expand!(180),
+             182 => $expand!(182),
+             184 => $expand!(184),
+             186 => $expand!(186),
+             188 => $expand!(188),
+             190 => $expand!(190),
+             192 => $expand!(192),
+             194 => $expand!(194),
+             196 => $expand!(196),
+             198 => $expand!(198),
+             200 => $expand!(200),
+             202 => $expand!(202),
+             204 => $expand!(204),
+             206 => $expand!(206),
+             208 => $expand!(208),
+             210 => $expand!(210),
+             212 => $expand!(212),
+             214 => $expand!(214),
+             216 => $expand!(216),
+             218 => $expand!(218),
+             220 => $expand!(220),
+             222 => $expand!(222),
+             224 => $expand!(224),
+             226 => $expand!(226),
+             228 => $expand!(228),
+             230 => $expand!(230),
+             232 => $expand!(232),
+             234 => $expand!(234),
+             236 => $expand!(236),
+             238 => $expand!(238),
+             240 => $expand!(240),
+             242 => $expand!(242),
+             244 => $expand!(244),
+             246 => $expand!(246),
+             248 => $expand!(248),
+             250 => $expand!(250),
+             252 => $expand!(252),
+             254 => $expand!(254),
+             256 => $expand!(256),
+             258 => $expand!(258),
+             260 => $expand!(260),
+             262 => $expand!(262),
+             264 => $expand!(264),
+             266 => $expand!(266),
+             268 => $expand!(268),
+             270 => $expand!(270),
+             272 => $expand!(272),
+             274 => $expand!(274),
+             276 => $expand!(276),
+             278 => $expand!(278),
+             280 => $expand!(280),
+             282 => $expand!(282),
+             284 => $expand!(284),
+             286 => $expand!(286),
+             288 => $expand!(288),
+             290 => $expand!(290),
+             292 => $expand!(292),
+             294 => $expand!(294),
+             296 => $expand!(296),
+             298 => $expand!(298),
+             300 => $expand!(300),
+             302 => $expand!(302),
+             304 => $expand!(304),
+             306 => $expand!(306),
+             308 => $expand!(308),
+             310 => $expand!(310),
+             312 => $expand!(312),
+             314 => $expand!(314),
+             316 => $expand!(316),
+             318 => $expand!(318),
+             320 => $expand!(320),
+             322 => $expand!(322),
+             324 => $expand!(324),
+             326 => $expand!(326),
+             328 => $expand!(328),
+             330 => $expand!(330),
+             332 => $expand!(332),
+             334 => $expand!(334),
+             336 => $expand!(336),
+             338 => $expand!(338),
+             340 => $expand!(340),
+             342 => $expand!(342),
+             344 => $expand!(344),
+             346 => $expand!(346),
+             348 => $expand!(348),
+             350 => $expand!(350),
+             352 => $expand!(352),
+             354 => $expand!(354),
+             356 => $expand!(356),
+             358 => $expand!(358),
+             360 => $expand!(360),
+             362 => $expand!(362),
+             364 => $expand!(364),
+             366 => $expand!(366),
+             368 => $expand!(368),
+             370 => $expand!(370),
+             372 => $expand!(372),
+             374 => $expand!(374),
+             376 => $expand!(376),
+             378 => $expand!(378),
+             380 => $expand!(380),
+             382 => $expand!(382),
+             384 => $expand!(384),
+             386 => $expand!(386),
+             388 => $expand!(388),
+             390 => $expand!(390),
+             392 => $expand!(392),
+             394 => $expand!(394),
+             396 => $expand!(396),
+             398 => $expand!(398),
+             400 => $expand!(400),
+             402 => $expand!(402),
+             404 => $expand!(404),
+             406 => $expand!(406),
+             408 => $expand!(408),
+             410 => $expand!(410),
+             412 => $expand!(412),
+             414 => $expand!(414),
+             416 => $expand!(416),
+             418 => $expand!(418),
+             420 => $expand!(420),
+             422 => $expand!(422),
+             424 => $expand!(424),
+             426 => $expand!(426),
+             428 => $expand!(428),
+             430 => $expand!(430),
+             432 => $expand!(432),
+             434 => $expand!(434),
+             436 => $expand!(436),
+             438 => $expand!(438),
+             440 => $expand!(440),
+             442 => $expand!(442),
+             444 => $expand!(444),
+             446 => $expand!(446),
+             448 => $expand!(448),
+             450 => $expand!(450),
+             452 => $expand!(452),
+             454 => $expand!(454),
+             456 => $expand!(456),
+             458 => $expand!(458),
+             460 => $expand!(460),
+             462 => $expand!(462),
+             464 => $expand!(464),
+             466 => $expand!(466),
+             468 => $expand!(468),
+             470 => $expand!(470),
+             472 => $expand!(472),
+             474 => $expand!(474),
+             476 => $expand!(476),
+             478 => $expand!(478),
+             480 => $expand!(480),
+             482 => $expand!(482),
+             484 => $expand!(484),
+             486 => $expand!(486),
+             488 => $expand!(488),
+             490 => $expand!(490),
+             492 => $expand!(492),
+             494 => $expand!(494),
+             496 => $expand!(496),
+             498 => $expand!(498),
+             500 => $expand!(500),
+             502 => $expand!(502),
+             504 => $expand!(504),
+             506 => $expand!(506),
+             508 => $expand!(508),
+             510 => $expand!(510),
+             512 => $expand!(512),
+             514 => $expand!(514),
+             516 => $expand!(516),
+             518 => $expand!(518),
+             520 => $expand!(520),
+             522 => $expand!(522),
+             524 => $expand!(524),
+             526 => $expand!(526),
+             528 => $expand!(528),
+             530 => $expand!(530),
+             532 => $expand!(532),
+             534 => $expand!(534),
+             536 => $expand!(536),
+             538 => $expand!(538),
+             540 => $expand!(540),
+             542 => $expand!(542),
+             544 => $expand!(544),
+             546 => $expand!(546),
+             548 => $expand!(548),
+             550 => $expand!(550),
+             552 => $expand!(552),
+             554 => $expand!(554),
+             556 => $expand!(556),
+             558 => $expand!(558),
+             560 => $expand!(560),
+             562 => $expand!(562),
+             564 => $expand!(564),
+             566 => $expand!(566),
+             568 => $expand!(568),
+             570 => $expand!(570),
+             572 => $expand!(572),
+             574 => $expand!(574),
+             576 => $expand!(576),
+             578 => $expand!(578),
+             580 => $expand!(580),
+             582 => $expand!(582),
+             584 => $expand!(584),
+             586 => $expand!(586),
+             588 => $expand!(588),
+             590 => $expand!(590),
+             592 => $expand!(592),
+             594 => $expand!(594),
+             596 => $expand!(596),
+             598 => $expand!(598),
+             600 => $expand!(600),
+             602 => $expand!(602),
+             604 => $expand!(604),
+             606 => $expand!(606),
+             608 => $expand!(608),
+             610 => $expand!(610),
+             612 => $expand!(612),
+             614 => $expand!(614),
+             616 => $expand!(616),
+             618 => $expand!(618),
+             620 => $expand!(620),
+             622 => $expand!(622),
+             624 => $expand!(624),
+             626 => $expand!(626),
+             628 => $expand!(628),
+             630 => $expand!(630),
+             632 => $expand!(632),
+             634 => $expand!(634),
+             636 => $expand!(636),
+             638 => $expand!(638),
+             640 => $expand!(640),
+             642 => $expand!(642),
+             644 => $expand!(644),
+             646 => $expand!(646),
+             648 => $expand!(648),
+             650 => $expand!(650),
+             652 => $expand!(652),
+             654 => $expand!(654),
+             656 => $expand!(656),
+             658 => $expand!(658),
+             660 => $expand!(660),
+             662 => $expand!(662),
+             664 => $expand!(664),
+             666 => $expand!(666),
+             668 => $expand!(668),
+             670 => $expand!(670),
+             672 => $expand!(672),
+             674 => $expand!(674),
+             676 => $expand!(676),
+             678 => $expand!(678),
+             680 => $expand!(680),
+             682 => $expand!(682),
+             684 => $expand!(684),
+             686 => $expand!(686),
+             688 => $expand!(688),
+             690 => $expand!(690),
+             692 => $expand!(692),
+             694 => $expand!(694),
+             696 => $expand!(696),
+             698 => $expand!(698),
+             700 => $expand!(700),
+             702 => $expand!(702),
+             704 => $expand!(704),
+             706 => $expand!(706),
+             708 => $expand!(708),
+             710 => $expand!(710),
+             712 => $expand!(712),
+             714 => $expand!(714),
+             716 => $expand!(716),
+             718 => $expand!(718),
+             720 => $expand!(720),
+             722 => $expand!(722),
+             724 => $expand!(724),
+             726 => $expand!(726),
+             728 => $expand!(728),
+             730 => $expand!(730),
+             732 => $expand!(732),
+             734 => $expand!(734),
+             736 => $expand!(736),
+             738 => $expand!(738),
+             740 => $expand!(740),
+             742 => $expand!(742),
+             744 => $expand!(744),
+             746 => $expand!(746),
+             748 => $expand!(748),
+             750 => $expand!(750),
+             752 => $expand!(752),
+             754 => $expand!(754),
+             756 => $expand!(756),
+             758 => $expand!(758),
+             760 => $expand!(760),
+             762 => $expand!(762),
+             764 => $expand!(764),
+             766 => $expand!(766),
+             768 => $expand!(768),
+             770 => $expand!(770),
+             772 => $expand!(772),
+             774 => $expand!(774),
+             776 => $expand!(776),
+             778 => $expand!(778),
+             780 => $expand!(780),
+             782 => $expand!(782),
+             784 => $expand!(784),
+             786 => $expand!(786),
+             788 => $expand!(788),
+             790 => $expand!(790),
+             792 => $expand!(792),
+             794 => $expand!(794),
+             796 => $expand!(796),
+             798 => $expand!(798),
+             800 => $expand!(800),
+             802 => $expand!(802),
+             804 => $expand!(804),
+             806 => $expand!(806),
+             808 => $expand!(808),
+             810 => $expand!(810),
+             812 => $expand!(812),
+             814 => $expand!(814),
+             816 => $expand!(816),
+             818 => $expand!(818),
+             820 => $expand!(820),
+             822 => $expand!(822),
+             824 => $expand!(824),
+             826 => $expand!(826),
+             828 => $expand!(828),
+             830 => $expand!(830),
+             832 => $expand!(832),
+             834 => $expand!(834),
+             836 => $expand!(836),
+             838 => $expand!(838),
+             840 => $expand!(840),
+             842 => $expand!(842),
+             844 => $expand!(844),
+             846 => $expand!(846),
+             848 => $expand!(848),
+             850 => $expand!(850),
+             852 => $expand!(852),
+             854 => $expand!(854),
+             856 => $expand!(856),
+             858 => $expand!(858),
+             860 => $expand!(860),
+             862 => $expand!(862),
+             864 => $expand!(864),
+             866 => $expand!(866),
+             868 => $expand!(868),
+             870 => $expand!(870),
+             872 => $expand!(872),
+             874 => $expand!(874),
+             876 => $expand!(876),
+             878 => $expand!(878),
+             880 => $expand!(880),
+             882 => $expand!(882),
+             884 => $expand!(884),
+             886 => $expand!(886),
+             888 => $expand!(888),
+             890 => $expand!(890),
+             892 => $expand!(892),
+             894 => $expand!(894),
+             896 => $expand!(896),
+             898 => $expand!(898),
+             900 => $expand!(900),
+             902 => $expand!(902),
+             904 => $expand!(904),
+             906 => $expand!(906),
+             908 => $expand!(908),
+             910 => $expand!(910),
+             912 => $expand!(912),
+             914 => $expand!(914),
+             916 => $expand!(916),
+             918 => $expand!(918),
+             920 => $expand!(920),
+             922 => $expand!(922),
+             924 => $expand!(924),
+             926 => $expand!(926),
+             928 => $expand!(928),
+             930 => $expand!(930),
+             932 => $expand!(932),
+             934 => $expand!(934),
+             936 => $expand!(936),
+             938 => $expand!(938),
+             940 => $expand!(940),
+             942 => $expand!(942),
+             944 => $expand!(944),
+             946 => $expand!(946),
+             948 => $expand!(948),
+             950 => $expand!(950),
+             952 => $expand!(952),
+             954 => $expand!(954),
+             956 => $expand!(956),
+             958 => $expand!(958),
+             960 => $expand!(960),
+             962 => $expand!(962),
+             964 => $expand!(964),
+             966 => $expand!(966),
+             968 => $expand!(968),
+             970 => $expand!(970),
+             972 => $expand!(972),
+             974 => $expand!(974),
+             976 => $expand!(976),
+             978 => $expand!(978),
+             980 => $expand!(980),
+             982 => $expand!(982),
+             984 => $expand!(984),
+             986 => $expand!(986),
+             988 => $expand!(988),
+             990 => $expand!(990),
+             992 => $expand!(992),
+             994 => $expand!(994),
+             996 => $expand!(996),
+             998 => $expand!(998),
+             1000 => $expand!(1000),
+             1002 => $expand!(1002),
+             1004 => $expand!(1004),
+             1006 => $expand!(1006),
+             1008 => $expand!(1008),
+             1010 => $expand!(1010),
+             1012 => $expand!(1012),
+             1014 => $expand!(1014),
+             1016 => $expand!(1016),
+             1018 => $expand!(1018),
+             1020 => $expand!(1020),
+             1024 => $expand!(-1024),
+             1026 => $expand!(-1022),
+             1028 => $expand!(-1020),
+             1030 => $expand!(-1018),
+             1032 => $expand!(-1016),
+             1034 => $expand!(-1014),
+             1036 => $expand!(-1012),
+             1038 => $expand!(-1010),
+             1040 => $expand!(-1008),
+             1042 => $expand!(-1006),
+             1044 => $expand!(-1004),
+             1046 => $expand!(-1002),
+             1048 => $expand!(-1000),
+             1050 => $expand!(-998),
+             1052 => $expand!(-996),
+             1054 => $expand!(-994),
+             1056 => $expand!(-992),
+             1058 => $expand!(-990),
+             1060 => $expand!(-988),
+             1062 => $expand!(-986),
+             1064 => $expand!(-984),
+             1066 => $expand!(-982),
+             1068 => $expand!(-980),
+             1070 => $expand!(-978),
+             1072 => $expand!(-976),
+             1074 => $expand!(-974),
+             1076 => $expand!(-972),
+             1078 => $expand!(-970),
+             1080 => $expand!(-968),
+             1082 => $expand!(-966),
+             1084 => $expand!(-964),
+             1086 => $expand!(-962),
+             1088 => $expand!(-960),
+             1090 => $expand!(-958),
+             1092 => $expand!(-956),
+             1094 => $expand!(-954),
+             1096 => $expand!(-952),
+             1098 => $expand!(-950),
+             1100 => $expand!(-948),
+             1102 => $expand!(-946),
+             1104 => $expand!(-944),
+             1106 => $expand!(-942),
+             1108 => $expand!(-940),
+             1110 => $expand!(-938),
+             1112 => $expand!(-936),
+             1114 => $expand!(-934),
+             1116 => $expand!(-932),
+             1118 => $expand!(-930),
+             1120 => $expand!(-928),
+             1122 => $expand!(-926),
+             1124 => $expand!(-924),
+             1126 => $expand!(-922),
+             1128 => $expand!(-920),
+             1130 => $expand!(-918),
+             1132 => $expand!(-916),
+             1134 => $expand!(-914),
+             1136 => $expand!(-912),
+             1138 => $expand!(-910),
+             1140 => $expand!(-908),
+             1142 => $expand!(-906),
+             1144 => $expand!(-904),
+             1146 => $expand!(-902),
+             1148 => $expand!(-900),
+             1150 => $expand!(-898),
+             1152 => $expand!(-896),
+             1154 => $expand!(-894),
+             1156 => $expand!(-892),
+             1158 => $expand!(-890),
+             1160 => $expand!(-888),
+             1162 => $expand!(-886),
+             1164 => $expand!(-884),
+             1166 => $expand!(-882),
+             1168 => $expand!(-880),
+             1170 => $expand!(-878),
+             1172 => $expand!(-876),
+             1174 => $expand!(-874),
+             1176 => $expand!(-872),
+             1178 => $expand!(-870),
+             1180 => $expand!(-868),
+             1182 => $expand!(-866),
+             1184 => $expand!(-864),
+             1186 => $expand!(-862),
+             1188 => $expand!(-860),
+             1190 => $expand!(-858),
+             1192 => $expand!(-856),
+             1194 => $expand!(-854),
+             1196 => $expand!(-852),
+             1198 => $expand!(-850),
+             1200 => $expand!(-848),
+             1202 => $expand!(-846),
+             1204 => $expand!(-844),
+             1206 => $expand!(-842),
+             1208 => $expand!(-840),
+             1210 => $expand!(-838),
+             1212 => $expand!(-836),
+             1214 => $expand!(-834),
+             1216 => $expand!(-832),
+             1218 => $expand!(-830),
+             1220 => $expand!(-828),
+             1222 => $expand!(-826),
+             1224 => $expand!(-824),
+             1226 => $expand!(-822),
+             1228 => $expand!(-820),
+             1230 => $expand!(-818),
+             1232 => $expand!(-816),
+             1234 => $expand!(-814),
+             1236 => $expand!(-812),
+             1238 => $expand!(-810),
+             1240 => $expand!(-808),
+             1242 => $expand!(-806),
+             1244 => $expand!(-804),
+             1246 => $expand!(-802),
+             1248 => $expand!(-800),
+             1250 => $expand!(-798),
+             1252 => $expand!(-796),
+             1254 => $expand!(-794),
+             1256 => $expand!(-792),
+             1258 => $expand!(-790),
+             1260 => $expand!(-788),
+             1262 => $expand!(-786),
+             1264 => $expand!(-784),
+             1266 => $expand!(-782),
+             1268 => $expand!(-780),
+             1270 => $expand!(-778),
+             1272 => $expand!(-776),
+             1274 => $expand!(-774),
+             1276 => $expand!(-772),
+             1278 => $expand!(-770),
+             1280 => $expand!(-768),
+             1282 => $expand!(-766),
+             1284 => $expand!(-764),
+             1286 => $expand!(-762),
+             1288 => $expand!(-760),
+             1290 => $expand!(-758),
+             1292 => $expand!(-756),
+             1294 => $expand!(-754),
+             1296 => $expand!(-752),
+             1298 => $expand!(-750),
+             1300 => $expand!(-748),
+             1302 => $expand!(-746),
+             1304 => $expand!(-744),
+             1306 => $expand!(-742),
+             1308 => $expand!(-740),
+             1310 => $expand!(-738),
+             1312 => $expand!(-736),
+             1314 => $expand!(-734),
+             1316 => $expand!(-732),
+             1318 => $expand!(-730),
+             1320 => $expand!(-728),
+             1322 => $expand!(-726),
+             1324 => $expand!(-724),
+             1326 => $expand!(-722),
+             1328 => $expand!(-720),
+             1330 => $expand!(-718),
+             1332 => $expand!(-716),
+             1334 => $expand!(-714),
+             1336 => $expand!(-712),
+             1338 => $expand!(-710),
+             1340 => $expand!(-708),
+             1342 => $expand!(-706),
+             1344 => $expand!(-704),
+             1346 => $expand!(-702),
+             1348 => $expand!(-700),
+             1350 => $expand!(-698),
+             1352 => $expand!(-696),
+             1354 => $expand!(-694),
+             1356 => $expand!(-692),
+             1358 => $expand!(-690),
+             1360 => $expand!(-688),
+             1362 => $expand!(-686),
+             1364 => $expand!(-684),
+             1366 => $expand!(-682),
+             1368 => $expand!(-680),
+             1370 => $expand!(-678),
+             1372 => $expand!(-676),
+             1374 => $expand!(-674),
+             1376 => $expand!(-672),
+             1378 => $expand!(-670),
+             1380 => $expand!(-668),
+             1382 => $expand!(-666),
+             1384 => $expand!(-664),
+             1386 => $expand!(-662),
+             1388 => $expand!(-660),
+             1390 => $expand!(-658),
+             1392 => $expand!(-656),
+             1394 => $expand!(-654),
+             1396 => $expand!(-652),
+             1398 => $expand!(-650),
+             1400 => $expand!(-648),
+             1402 => $expand!(-646),
+             1404 => $expand!(-644),
+             1406 => $expand!(-642),
+             1408 => $expand!(-640),
+             1410 => $expand!(-638),
+             1412 => $expand!(-636),
+             1414 => $expand!(-634),
+             1416 => $expand!(-632),
+             1418 => $expand!(-630),
+             1420 => $expand!(-628),
+             1422 => $expand!(-626),
+             1424 => $expand!(-624),
+             1426 => $expand!(-622),
+             1428 => $expand!(-620),
+             1430 => $expand!(-618),
+             1432 => $expand!(-616),
+             1434 => $expand!(-614),
+             1436 => $expand!(-612),
+             1438 => $expand!(-610),
+             1440 => $expand!(-608),
+             1442 => $expand!(-606),
+             1444 => $expand!(-604),
+             1446 => $expand!(-602),
+             1448 => $expand!(-600),
+             1450 => $expand!(-598),
+             1452 => $expand!(-596),
+             1454 => $expand!(-594),
+             1456 => $expand!(-592),
+             1458 => $expand!(-590),
+             1460 => $expand!(-588),
+             1462 => $expand!(-586),
+             1464 => $expand!(-584),
+             1466 => $expand!(-582),
+             1468 => $expand!(-580),
+             1470 => $expand!(-578),
+             1472 => $expand!(-576),
+             1474 => $expand!(-574),
+             1476 => $expand!(-572),
+             1478 => $expand!(-570),
+             1480 => $expand!(-568),
+             1482 => $expand!(-566),
+             1484 => $expand!(-564),
+             1486 => $expand!(-562),
+             1488 => $expand!(-560),
+             1490 => $expand!(-558),
+             1492 => $expand!(-556),
+             1494 => $expand!(-554),
+             1496 => $expand!(-552),
+             1498 => $expand!(-550),
+             1500 => $expand!(-548),
+             1502 => $expand!(-546),
+             1504 => $expand!(-544),
+             1506 => $expand!(-542),
+             1508 => $expand!(-540),
+             1510 => $expand!(-538),
+             1512 => $expand!(-536),
+             1514 => $expand!(-534),
+             1516 => $expand!(-532),
+             1518 => $expand!(-530),
+             1520 => $expand!(-528),
+             1522 => $expand!(-526),
+             1524 => $expand!(-524),
+             1526 => $expand!(-522),
+             1528 => $expand!(-520),
+             1530 => $expand!(-518),
+             1532 => $expand!(-516),
+             1534 => $expand!(-514),
+             1536 => $expand!(-512),
+             1538 => $expand!(-510),
+             1540 => $expand!(-508),
+             1542 => $expand!(-506),
+             1544 => $expand!(-504),
+             1546 => $expand!(-502),
+             1548 => $expand!(-500),
+             1550 => $expand!(-498),
+             1552 => $expand!(-496),
+             1554 => $expand!(-494),
+             1556 => $expand!(-492),
+             1558 => $expand!(-490),
+             1560 => $expand!(-488),
+             1562 => $expand!(-486),
+             1564 => $expand!(-484),
+             1566 => $expand!(-482),
+             1568 => $expand!(-480),
+             1570 => $expand!(-478),
+             1572 => $expand!(-476),
+             1574 => $expand!(-474),
+             1576 => $expand!(-472),
+             1578 => $expand!(-470),
+             1580 => $expand!(-468),
+             1582 => $expand!(-466),
+             1584 => $expand!(-464),
+             1586 => $expand!(-462),
+             1588 => $expand!(-460),
+             1590 => $expand!(-458),
+             1592 => $expand!(-456),
+             1594 => $expand!(-454),
+             1596 => $expand!(-452),
+             1598 => $expand!(-450),
+             1600 => $expand!(-448),
+             1602 => $expand!(-446),
+             1604 => $expand!(-444),
+             1606 => $expand!(-442),
+             1608 => $expand!(-440),
+             1610 => $expand!(-438),
+             1612 => $expand!(-436),
+             1614 => $expand!(-434),
+             1616 => $expand!(-432),
+             1618 => $expand!(-430),
+             1620 => $expand!(-428),
+             1622 => $expand!(-426),
+             1624 => $expand!(-424),
+             1626 => $expand!(-422),
+             1628 => $expand!(-420),
+             1630 => $expand!(-418),
+             1632 => $expand!(-416),
+             1634 => $expand!(-414),
+             1636 => $expand!(-412),
+             1638 => $expand!(-410),
+             1640 => $expand!(-408),
+             1642 => $expand!(-406),
+             1644 => $expand!(-404),
+             1646 => $expand!(-402),
+             1648 => $expand!(-400),
+             1650 => $expand!(-398),
+             1652 => $expand!(-396),
+             1654 => $expand!(-394),
+             1656 => $expand!(-392),
+             1658 => $expand!(-390),
+             1660 => $expand!(-388),
+             1662 => $expand!(-386),
+             1664 => $expand!(-384),
+             1666 => $expand!(-382),
+             1668 => $expand!(-380),
+             1670 => $expand!(-378),
+             1672 => $expand!(-376),
+             1674 => $expand!(-374),
+             1676 => $expand!(-372),
+             1678 => $expand!(-370),
+             1680 => $expand!(-368),
+             1682 => $expand!(-366),
+             1684 => $expand!(-364),
+             1686 => $expand!(-362),
+             1688 => $expand!(-360),
+             1690 => $expand!(-358),
+             1692 => $expand!(-356),
+             1694 => $expand!(-354),
+             1696 => $expand!(-352),
+             1698 => $expand!(-350),
+             1700 => $expand!(-348),
+             1702 => $expand!(-346),
+             1704 => $expand!(-344),
+             1706 => $expand!(-342),
+             1708 => $expand!(-340),
+             1710 => $expand!(-338),
+             1712 => $expand!(-336),
+             1714 => $expand!(-334),
+             1716 => $expand!(-332),
+             1718 => $expand!(-330),
+             1720 => $expand!(-328),
+             1722 => $expand!(-326),
+             1724 => $expand!(-324),
+             1726 => $expand!(-322),
+             1728 => $expand!(-320),
+             1730 => $expand!(-318),
+             1732 => $expand!(-316),
+             1734 => $expand!(-314),
+             1736 => $expand!(-312),
+             1738 => $expand!(-310),
+             1740 => $expand!(-308),
+             1742 => $expand!(-306),
+             1744 => $expand!(-304),
+             1746 => $expand!(-302),
+             1748 => $expand!(-300),
+             1750 => $expand!(-298),
+             1752 => $expand!(-296),
+             1754 => $expand!(-294),
+             1756 => $expand!(-292),
+             1758 => $expand!(-290),
+             1760 => $expand!(-288),
+             1762 => $expand!(-286),
+             1764 => $expand!(-284),
+             1766 => $expand!(-282),
+             1768 => $expand!(-280),
+             1770 => $expand!(-278),
+             1772 => $expand!(-276),
+             1774 => $expand!(-274),
+             1776 => $expand!(-272),
+             1778 => $expand!(-270),
+             1780 => $expand!(-268),
+             1782 => $expand!(-266),
+             1784 => $expand!(-264),
+             1786 => $expand!(-262),
+             1788 => $expand!(-260),
+             1790 => $expand!(-258),
+             1792 => $expand!(-256),
+             1794 => $expand!(-254),
+             1796 => $expand!(-252),
+             1798 => $expand!(-250),
+             1800 => $expand!(-248),
+             1802 => $expand!(-246),
+             1804 => $expand!(-244),
+             1806 => $expand!(-242),
+             1808 => $expand!(-240),
+             1810 => $expand!(-238),
+             1812 => $expand!(-236),
+             1814 => $expand!(-234),
+             1816 => $expand!(-232),
+             1818 => $expand!(-230),
+             1820 => $expand!(-228),
+             1822 => $expand!(-226),
+             1824 => $expand!(-224),
+             1826 => $expand!(-222),
+             1828 => $expand!(-220),
+             1830 => $expand!(-218),
+             1832 => $expand!(-216),
+             1834 => $expand!(-214),
+             1836 => $expand!(-212),
+             1838 => $expand!(-210),
+             1840 => $expand!(-208),
+             1842 => $expand!(-206),
+             1844 => $expand!(-204),
+             1846 => $expand!(-202),
+             1848 => $expand!(-200),
+             1850 => $expand!(-198),
+             1852 => $expand!(-196),
+             1854 => $expand!(-194),
+             1856 => $expand!(-192),
+             1858 => $expand!(-190),
+             1860 => $expand!(-188),
+             1862 => $expand!(-186),
+             1864 => $expand!(-184),
+             1866 => $expand!(-182),
+             1868 => $expand!(-180),
+             1870 => $expand!(-178),
+             1872 => $expand!(-176),
+             1874 => $expand!(-174),
+             1876 => $expand!(-172),
+             1878 => $expand!(-170),
+             1880 => $expand!(-168),
+             1882 => $expand!(-166),
+             1884 => $expand!(-164),
+             1886 => $expand!(-162),
+             1888 => $expand!(-160),
+             1890 => $expand!(-158),
+             1892 => $expand!(-156),
+             1894 => $expand!(-154),
+             1896 => $expand!(-152),
+             1898 => $expand!(-150),
+             1900 => $expand!(-148),
+             1902 => $expand!(-146),
+             1904 => $expand!(-144),
+             1906 => $expand!(-142),
+             1908 => $expand!(-140),
+             1910 => $expand!(-138),
+             1912 => $expand!(-136),
+             1914 => $expand!(-134),
+             1916 => $expand!(-132),
+             1918 => $expand!(-130),
+             1920 => $expand!(-128),
+             1922 => $expand!(-126),
+             1924 => $expand!(-124),
+             1926 => $expand!(-122),
+             1928 => $expand!(-120),
+             1930 => $expand!(-118),
+             1932 => $expand!(-116),
+             1934 => $expand!(-114),
+             1936 => $expand!(-112),
+             1938 => $expand!(-110),
+             1940 => $expand!(-108),
+             1942 => $expand!(-106),
+             1944 => $expand!(-104),
+             1946 => $expand!(-102),
+             1948 => $expand!(-100),
+             1950 => $expand!(-98),
+             1952 => $expand!(-96),
+             1954 => $expand!(-94),
+             1956 => $expand!(-92),
+             1958 => $expand!(-90),
+             1960 => $expand!(-88),
+             1962 => $expand!(-86),
+             1964 => $expand!(-84),
+             1966 => $expand!(-82),
+             1968 => $expand!(-80),
+             1970 => $expand!(-78),
+             1972 => $expand!(-76),
+             1974 => $expand!(-74),
+             1976 => $expand!(-72),
+             1978 => $expand!(-70),
+             1980 => $expand!(-68),
+             1982 => $expand!(-66),
+             1984 => $expand!(-64),
+             1986 => $expand!(-62),
+             1988 => $expand!(-60),
+             1990 => $expand!(-58),
+             1992 => $expand!(-56),
+             1994 => $expand!(-54),
+             1996 => $expand!(-52),
+             1998 => $expand!(-50),
+             2000 => $expand!(-48),
+             2002 => $expand!(-46),
+             2004 => $expand!(-44),
+             2006 => $expand!(-42),
+             2008 => $expand!(-40),
+             2010 => $expand!(-38),
+             2012 => $expand!(-36),
+             2014 => $expand!(-34),
+             2016 => $expand!(-32),
+             2018 => $expand!(-30),
+             2020 => $expand!(-28),
+             2022 => $expand!(-26),
+             2024 => $expand!(-24),
+             2026 => $expand!(-22),
+             2028 => $expand!(-20),
+             2030 => $expand!(-18),
+             2032 => $expand!(-16),
+             2034 => $expand!(-14),
+             2036 => $expand!(-12),
+             2038 => $expand!(-10),
+             2040 => $expand!(-8),
+             2042 => $expand!(-6),
+             2044 => $expand!(-4),
+             2046 => $expand!(-2),
+             _ => $expand!(1022),
+         }
+     };
+ }
+ 
+ //immediate value: -512:511
+ macro_rules! constify_imm_s10 {
+     ($imm_s10:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm_s10) & 0b11_1111_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             31 => $expand!(31),
+             32 => $expand!(32),
+             33 => $expand!(33),
+             34 => $expand!(34),
+             35 => $expand!(35),
+             36 => $expand!(36),
+             37 => $expand!(37),
+             38 => $expand!(38),
+             39 => $expand!(39),
+             40 => $expand!(40),
+             41 => $expand!(41),
+             42 => $expand!(42),
+             43 => $expand!(43),
+             44 => $expand!(44),
+             45 => $expand!(45),
+             46 => $expand!(46),
+             47 => $expand!(47),
+             48 => $expand!(48),
+             49 => $expand!(49),
+             50 => $expand!(50),
+             51 => $expand!(51),
+             52 => $expand!(52),
+             53 => $expand!(53),
+             54 => $expand!(54),
+             55 => $expand!(55),
+             56 => $expand!(56),
+             57 => $expand!(57),
+             58 => $expand!(58),
+             59 => $expand!(59),
+             60 => $expand!(60),
+             61 => $expand!(61),
+             62 => $expand!(62),
+             63 => $expand!(63),
+             64 => $expand!(64),
+             65 => $expand!(65),
+             66 => $expand!(66),
+             67 => $expand!(67),
+             68 => $expand!(68),
+             69 => $expand!(69),
+             70 => $expand!(70),
+             71 => $expand!(71),
+             72 => $expand!(72),
+             73 => $expand!(73),
+             74 => $expand!(74),
+             75 => $expand!(75),
+             76 => $expand!(76),
+             77 => $expand!(77),
+             78 => $expand!(78),
+             79 => $expand!(79),
+             80 => $expand!(80),
+             81 => $expand!(81),
+             82 => $expand!(82),
+             83 => $expand!(83),
+             84 => $expand!(84),
+             85 => $expand!(85),
+             86 => $expand!(86),
+             87 => $expand!(87),
+             88 => $expand!(88),
+             89 => $expand!(89),
+             90 => $expand!(90),
+             91 => $expand!(91),
+             92 => $expand!(92),
+             93 => $expand!(93),
+             94 => $expand!(94),
+             95 => $expand!(95),
+             96 => $expand!(96),
+             97 => $expand!(97),
+             98 => $expand!(98),
+             99 => $expand!(99),
+             100 => $expand!(100),
+             101 => $expand!(101),
+             102 => $expand!(102),
+             103 => $expand!(103),
+             104 => $expand!(104),
+             105 => $expand!(105),
+             106 => $expand!(106),
+             107 => $expand!(107),
+             108 => $expand!(108),
+             109 => $expand!(109),
+             110 => $expand!(110),
+             111 => $expand!(111),
+             112 => $expand!(112),
+             113 => $expand!(113),
+             114 => $expand!(114),
+             115 => $expand!(115),
+             116 => $expand!(116),
+             117 => $expand!(117),
+             118 => $expand!(118),
+             119 => $expand!(119),
+             120 => $expand!(120),
+             121 => $expand!(121),
+             122 => $expand!(122),
+             123 => $expand!(123),
+             124 => $expand!(124),
+             125 => $expand!(125),
+             126 => $expand!(126),
+             127 => $expand!(127),
+             128 => $expand!(128),
+             129 => $expand!(129),
+             130 => $expand!(130),
+             131 => $expand!(131),
+             132 => $expand!(132),
+             133 => $expand!(133),
+             134 => $expand!(134),
+             135 => $expand!(135),
+             136 => $expand!(136),
+             137 => $expand!(137),
+             138 => $expand!(138),
+             139 => $expand!(139),
+             140 => $expand!(140),
+             141 => $expand!(141),
+             142 => $expand!(142),
+             143 => $expand!(143),
+             144 => $expand!(144),
+             145 => $expand!(145),
+             146 => $expand!(146),
+             147 => $expand!(147),
+             148 => $expand!(148),
+             149 => $expand!(149),
+             150 => $expand!(150),
+             151 => $expand!(151),
+             152 => $expand!(152),
+             153 => $expand!(153),
+             154 => $expand!(154),
+             155 => $expand!(155),
+             156 => $expand!(156),
+             157 => $expand!(157),
+             158 => $expand!(158),
+             159 => $expand!(159),
+             160 => $expand!(160),
+             161 => $expand!(161),
+             162 => $expand!(162),
+             163 => $expand!(163),
+             164 => $expand!(164),
+             165 => $expand!(165),
+             166 => $expand!(166),
+             167 => $expand!(167),
+             168 => $expand!(168),
+             169 => $expand!(169),
+             170 => $expand!(170),
+             171 => $expand!(171),
+             172 => $expand!(172),
+             173 => $expand!(173),
+             174 => $expand!(174),
+             175 => $expand!(175),
+             176 => $expand!(176),
+             177 => $expand!(177),
+             178 => $expand!(178),
+             179 => $expand!(179),
+             180 => $expand!(180),
+             181 => $expand!(181),
+             182 => $expand!(182),
+             183 => $expand!(183),
+             184 => $expand!(184),
+             185 => $expand!(185),
+             186 => $expand!(186),
+             187 => $expand!(187),
+             188 => $expand!(188),
+             189 => $expand!(189),
+             190 => $expand!(190),
+             191 => $expand!(191),
+             192 => $expand!(192),
+             193 => $expand!(193),
+             194 => $expand!(194),
+             195 => $expand!(195),
+             196 => $expand!(196),
+             197 => $expand!(197),
+             198 => $expand!(198),
+             199 => $expand!(199),
+             200 => $expand!(200),
+             201 => $expand!(201),
+             202 => $expand!(202),
+             203 => $expand!(203),
+             204 => $expand!(204),
+             205 => $expand!(205),
+             206 => $expand!(206),
+             207 => $expand!(207),
+             208 => $expand!(208),
+             209 => $expand!(209),
+             210 => $expand!(210),
+             211 => $expand!(211),
+             212 => $expand!(212),
+             213 => $expand!(213),
+             214 => $expand!(214),
+             215 => $expand!(215),
+             216 => $expand!(216),
+             217 => $expand!(217),
+             218 => $expand!(218),
+             219 => $expand!(219),
+             220 => $expand!(220),
+             221 => $expand!(221),
+             222 => $expand!(222),
+             223 => $expand!(223),
+             224 => $expand!(224),
+             225 => $expand!(225),
+             226 => $expand!(226),
+             227 => $expand!(227),
+             228 => $expand!(228),
+             229 => $expand!(229),
+             230 => $expand!(230),
+             231 => $expand!(231),
+             232 => $expand!(232),
+             233 => $expand!(233),
+             234 => $expand!(234),
+             235 => $expand!(235),
+             236 => $expand!(236),
+             237 => $expand!(237),
+             238 => $expand!(238),
+             239 => $expand!(239),
+             240 => $expand!(240),
+             241 => $expand!(241),
+             242 => $expand!(242),
+             243 => $expand!(243),
+             244 => $expand!(244),
+             245 => $expand!(245),
+             246 => $expand!(246),
+             247 => $expand!(247),
+             248 => $expand!(248),
+             249 => $expand!(249),
+             250 => $expand!(250),
+             251 => $expand!(251),
+             252 => $expand!(252),
+             253 => $expand!(253),
+             254 => $expand!(254),
+             255 => $expand!(255),
+             256 => $expand!(256),
+             257 => $expand!(257),
+             258 => $expand!(258),
+             259 => $expand!(259),
+             260 => $expand!(260),
+             261 => $expand!(261),
+             262 => $expand!(262),
+             263 => $expand!(263),
+             264 => $expand!(264),
+             265 => $expand!(265),
+             266 => $expand!(266),
+             267 => $expand!(267),
+             268 => $expand!(268),
+             269 => $expand!(269),
+             270 => $expand!(270),
+             271 => $expand!(271),
+             272 => $expand!(272),
+             273 => $expand!(273),
+             274 => $expand!(274),
+             275 => $expand!(275),
+             276 => $expand!(276),
+             277 => $expand!(277),
+             278 => $expand!(278),
+             279 => $expand!(279),
+             280 => $expand!(280),
+             281 => $expand!(281),
+             282 => $expand!(282),
+             283 => $expand!(283),
+             284 => $expand!(284),
+             285 => $expand!(285),
+             286 => $expand!(286),
+             287 => $expand!(287),
+             288 => $expand!(288),
+             289 => $expand!(289),
+             290 => $expand!(290),
+             291 => $expand!(291),
+             292 => $expand!(292),
+             293 => $expand!(293),
+             294 => $expand!(294),
+             295 => $expand!(295),
+             296 => $expand!(296),
+             297 => $expand!(297),
+             298 => $expand!(298),
+             299 => $expand!(299),
+             300 => $expand!(300),
+             301 => $expand!(301),
+             302 => $expand!(302),
+             303 => $expand!(303),
+             304 => $expand!(304),
+             305 => $expand!(305),
+             306 => $expand!(306),
+             307 => $expand!(307),
+             308 => $expand!(308),
+             309 => $expand!(309),
+             310 => $expand!(310),
+             311 => $expand!(311),
+             312 => $expand!(312),
+             313 => $expand!(313),
+             314 => $expand!(314),
+             315 => $expand!(315),
+             316 => $expand!(316),
+             317 => $expand!(317),
+             318 => $expand!(318),
+             319 => $expand!(319),
+             320 => $expand!(320),
+             321 => $expand!(321),
+             322 => $expand!(322),
+             323 => $expand!(323),
+             324 => $expand!(324),
+             325 => $expand!(325),
+             326 => $expand!(326),
+             327 => $expand!(327),
+             328 => $expand!(328),
+             329 => $expand!(329),
+             330 => $expand!(330),
+             331 => $expand!(331),
+             332 => $expand!(332),
+             333 => $expand!(333),
+             334 => $expand!(334),
+             335 => $expand!(335),
+             336 => $expand!(336),
+             337 => $expand!(337),
+             338 => $expand!(338),
+             339 => $expand!(339),
+             340 => $expand!(340),
+             341 => $expand!(341),
+             342 => $expand!(342),
+             343 => $expand!(343),
+             344 => $expand!(344),
+             345 => $expand!(345),
+             346 => $expand!(346),
+             347 => $expand!(347),
+             348 => $expand!(348),
+             349 => $expand!(349),
+             350 => $expand!(350),
+             351 => $expand!(351),
+             352 => $expand!(352),
+             353 => $expand!(353),
+             354 => $expand!(354),
+             355 => $expand!(355),
+             356 => $expand!(356),
+             357 => $expand!(357),
+             358 => $expand!(358),
+             359 => $expand!(359),
+             360 => $expand!(360),
+             361 => $expand!(361),
+             362 => $expand!(362),
+             363 => $expand!(363),
+             364 => $expand!(364),
+             365 => $expand!(365),
+             366 => $expand!(366),
+             367 => $expand!(367),
+             368 => $expand!(368),
+             369 => $expand!(369),
+             370 => $expand!(370),
+             371 => $expand!(371),
+             372 => $expand!(372),
+             373 => $expand!(373),
+             374 => $expand!(374),
+             375 => $expand!(375),
+             376 => $expand!(376),
+             377 => $expand!(377),
+             378 => $expand!(378),
+             379 => $expand!(379),
+             380 => $expand!(380),
+             381 => $expand!(381),
+             382 => $expand!(382),
+             383 => $expand!(383),
+             384 => $expand!(384),
+             385 => $expand!(385),
+             386 => $expand!(386),
+             387 => $expand!(387),
+             388 => $expand!(388),
+             389 => $expand!(389),
+             390 => $expand!(390),
+             391 => $expand!(391),
+             392 => $expand!(392),
+             393 => $expand!(393),
+             394 => $expand!(394),
+             395 => $expand!(395),
+             396 => $expand!(396),
+             397 => $expand!(397),
+             398 => $expand!(398),
+             399 => $expand!(399),
+             400 => $expand!(400),
+             401 => $expand!(401),
+             402 => $expand!(402),
+             403 => $expand!(403),
+             404 => $expand!(404),
+             405 => $expand!(405),
+             406 => $expand!(406),
+             407 => $expand!(407),
+             408 => $expand!(408),
+             409 => $expand!(409),
+             410 => $expand!(410),
+             411 => $expand!(411),
+             412 => $expand!(412),
+             413 => $expand!(413),
+             414 => $expand!(414),
+             415 => $expand!(415),
+             416 => $expand!(416),
+             417 => $expand!(417),
+             418 => $expand!(418),
+             419 => $expand!(419),
+             420 => $expand!(420),
+             421 => $expand!(421),
+             422 => $expand!(422),
+             423 => $expand!(423),
+             424 => $expand!(424),
+             425 => $expand!(425),
+             426 => $expand!(426),
+             427 => $expand!(427),
+             428 => $expand!(428),
+             429 => $expand!(429),
+             430 => $expand!(430),
+             431 => $expand!(431),
+             432 => $expand!(432),
+             433 => $expand!(433),
+             434 => $expand!(434),
+             435 => $expand!(435),
+             436 => $expand!(436),
+             437 => $expand!(437),
+             438 => $expand!(438),
+             439 => $expand!(439),
+             440 => $expand!(440),
+             441 => $expand!(441),
+             442 => $expand!(442),
+             443 => $expand!(443),
+             444 => $expand!(444),
+             445 => $expand!(445),
+             446 => $expand!(446),
+             447 => $expand!(447),
+             448 => $expand!(448),
+             449 => $expand!(449),
+             450 => $expand!(450),
+             451 => $expand!(451),
+             452 => $expand!(452),
+             453 => $expand!(453),
+             454 => $expand!(454),
+             455 => $expand!(455),
+             456 => $expand!(456),
+             457 => $expand!(457),
+             458 => $expand!(458),
+             459 => $expand!(459),
+             460 => $expand!(460),
+             461 => $expand!(461),
+             462 => $expand!(462),
+             463 => $expand!(463),
+             464 => $expand!(464),
+             465 => $expand!(465),
+             466 => $expand!(466),
+             467 => $expand!(467),
+             468 => $expand!(468),
+             469 => $expand!(469),
+             470 => $expand!(470),
+             471 => $expand!(471),
+             472 => $expand!(472),
+             473 => $expand!(473),
+             474 => $expand!(474),
+             475 => $expand!(475),
+             476 => $expand!(476),
+             477 => $expand!(477),
+             478 => $expand!(478),
+             479 => $expand!(479),
+             480 => $expand!(480),
+             481 => $expand!(481),
+             482 => $expand!(482),
+             483 => $expand!(483),
+             484 => $expand!(484),
+             485 => $expand!(485),
+             486 => $expand!(486),
+             487 => $expand!(487),
+             488 => $expand!(488),
+             489 => $expand!(489),
+             490 => $expand!(490),
+             491 => $expand!(491),
+             492 => $expand!(492),
+             493 => $expand!(493),
+             494 => $expand!(494),
+             495 => $expand!(495),
+             496 => $expand!(496),
+             497 => $expand!(497),
+             498 => $expand!(498),
+             499 => $expand!(499),
+             500 => $expand!(500),
+             501 => $expand!(501),
+             502 => $expand!(502),
+             503 => $expand!(503),
+             504 => $expand!(504),
+             505 => $expand!(505),
+             506 => $expand!(506),
+             507 => $expand!(507),
+             508 => $expand!(508),
+             509 => $expand!(509),
+             510 => $expand!(510),
+             512 => $expand!(-512),
+             513 => $expand!(-511),
+             514 => $expand!(-510),
+             515 => $expand!(-509),
+             516 => $expand!(-508),
+             517 => $expand!(-507),
+             518 => $expand!(-506),
+             519 => $expand!(-505),
+             520 => $expand!(-504),
+             521 => $expand!(-503),
+             522 => $expand!(-502),
+             523 => $expand!(-501),
+             524 => $expand!(-500),
+             525 => $expand!(-499),
+             526 => $expand!(-498),
+             527 => $expand!(-497),
+             528 => $expand!(-496),
+             529 => $expand!(-495),
+             530 => $expand!(-494),
+             531 => $expand!(-493),
+             532 => $expand!(-492),
+             533 => $expand!(-491),
+             534 => $expand!(-490),
+             535 => $expand!(-489),
+             536 => $expand!(-488),
+             537 => $expand!(-487),
+             538 => $expand!(-486),
+             539 => $expand!(-485),
+             540 => $expand!(-484),
+             541 => $expand!(-483),
+             542 => $expand!(-482),
+             543 => $expand!(-481),
+             544 => $expand!(-480),
+             545 => $expand!(-479),
+             546 => $expand!(-478),
+             547 => $expand!(-477),
+             548 => $expand!(-476),
+             549 => $expand!(-475),
+             550 => $expand!(-474),
+             551 => $expand!(-473),
+             552 => $expand!(-472),
+             553 => $expand!(-471),
+             554 => $expand!(-470),
+             555 => $expand!(-469),
+             556 => $expand!(-468),
+             557 => $expand!(-467),
+             558 => $expand!(-466),
+             559 => $expand!(-465),
+             560 => $expand!(-464),
+             561 => $expand!(-463),
+             562 => $expand!(-462),
+             563 => $expand!(-461),
+             564 => $expand!(-460),
+             565 => $expand!(-459),
+             566 => $expand!(-458),
+             567 => $expand!(-457),
+             568 => $expand!(-456),
+             569 => $expand!(-455),
+             570 => $expand!(-454),
+             571 => $expand!(-453),
+             572 => $expand!(-452),
+             573 => $expand!(-451),
+             574 => $expand!(-450),
+             575 => $expand!(-449),
+             576 => $expand!(-448),
+             577 => $expand!(-447),
+             578 => $expand!(-446),
+             579 => $expand!(-445),
+             580 => $expand!(-444),
+             581 => $expand!(-443),
+             582 => $expand!(-442),
+             583 => $expand!(-441),
+             584 => $expand!(-440),
+             585 => $expand!(-439),
+             586 => $expand!(-438),
+             587 => $expand!(-437),
+             588 => $expand!(-436),
+             589 => $expand!(-435),
+             590 => $expand!(-434),
+             591 => $expand!(-433),
+             592 => $expand!(-432),
+             593 => $expand!(-431),
+             594 => $expand!(-430),
+             595 => $expand!(-429),
+             596 => $expand!(-428),
+             597 => $expand!(-427),
+             598 => $expand!(-426),
+             599 => $expand!(-425),
+             600 => $expand!(-424),
+             601 => $expand!(-423),
+             602 => $expand!(-422),
+             603 => $expand!(-421),
+             604 => $expand!(-420),
+             605 => $expand!(-419),
+             606 => $expand!(-418),
+             607 => $expand!(-417),
+             608 => $expand!(-416),
+             609 => $expand!(-415),
+             610 => $expand!(-414),
+             611 => $expand!(-413),
+             612 => $expand!(-412),
+             613 => $expand!(-411),
+             614 => $expand!(-410),
+             615 => $expand!(-409),
+             616 => $expand!(-408),
+             617 => $expand!(-407),
+             618 => $expand!(-406),
+             619 => $expand!(-405),
+             620 => $expand!(-404),
+             621 => $expand!(-403),
+             622 => $expand!(-402),
+             623 => $expand!(-401),
+             624 => $expand!(-400),
+             625 => $expand!(-399),
+             626 => $expand!(-398),
+             627 => $expand!(-397),
+             628 => $expand!(-396),
+             629 => $expand!(-395),
+             630 => $expand!(-394),
+             631 => $expand!(-393),
+             632 => $expand!(-392),
+             633 => $expand!(-391),
+             634 => $expand!(-390),
+             635 => $expand!(-389),
+             636 => $expand!(-388),
+             637 => $expand!(-387),
+             638 => $expand!(-386),
+             639 => $expand!(-385),
+             640 => $expand!(-384),
+             641 => $expand!(-383),
+             642 => $expand!(-382),
+             643 => $expand!(-381),
+             644 => $expand!(-380),
+             645 => $expand!(-379),
+             646 => $expand!(-378),
+             647 => $expand!(-377),
+             648 => $expand!(-376),
+             649 => $expand!(-375),
+             650 => $expand!(-374),
+             651 => $expand!(-373),
+             652 => $expand!(-372),
+             653 => $expand!(-371),
+             654 => $expand!(-370),
+             655 => $expand!(-369),
+             656 => $expand!(-368),
+             657 => $expand!(-367),
+             658 => $expand!(-366),
+             659 => $expand!(-365),
+             660 => $expand!(-364),
+             661 => $expand!(-363),
+             662 => $expand!(-362),
+             663 => $expand!(-361),
+             664 => $expand!(-360),
+             665 => $expand!(-359),
+             666 => $expand!(-358),
+             667 => $expand!(-357),
+             668 => $expand!(-356),
+             669 => $expand!(-355),
+             670 => $expand!(-354),
+             671 => $expand!(-353),
+             672 => $expand!(-352),
+             673 => $expand!(-351),
+             674 => $expand!(-350),
+             675 => $expand!(-349),
+             676 => $expand!(-348),
+             677 => $expand!(-347),
+             678 => $expand!(-346),
+             679 => $expand!(-345),
+             680 => $expand!(-344),
+             681 => $expand!(-343),
+             682 => $expand!(-342),
+             683 => $expand!(-341),
+             684 => $expand!(-340),
+             685 => $expand!(-339),
+             686 => $expand!(-338),
+             687 => $expand!(-337),
+             688 => $expand!(-336),
+             689 => $expand!(-335),
+             690 => $expand!(-334),
+             691 => $expand!(-333),
+             692 => $expand!(-332),
+             693 => $expand!(-331),
+             694 => $expand!(-330),
+             695 => $expand!(-329),
+             696 => $expand!(-328),
+             697 => $expand!(-327),
+             698 => $expand!(-326),
+             699 => $expand!(-325),
+             700 => $expand!(-324),
+             701 => $expand!(-323),
+             702 => $expand!(-322),
+             703 => $expand!(-321),
+             704 => $expand!(-320),
+             705 => $expand!(-319),
+             706 => $expand!(-318),
+             707 => $expand!(-317),
+             708 => $expand!(-316),
+             709 => $expand!(-315),
+             710 => $expand!(-314),
+             711 => $expand!(-313),
+             712 => $expand!(-312),
+             713 => $expand!(-311),
+             714 => $expand!(-310),
+             715 => $expand!(-309),
+             716 => $expand!(-308),
+             717 => $expand!(-307),
+             718 => $expand!(-306),
+             719 => $expand!(-305),
+             720 => $expand!(-304),
+             721 => $expand!(-303),
+             722 => $expand!(-302),
+             723 => $expand!(-301),
+             724 => $expand!(-300),
+             725 => $expand!(-299),
+             726 => $expand!(-298),
+             727 => $expand!(-297),
+             728 => $expand!(-296),
+             729 => $expand!(-295),
+             730 => $expand!(-294),
+             731 => $expand!(-293),
+             732 => $expand!(-292),
+             733 => $expand!(-291),
+             734 => $expand!(-290),
+             735 => $expand!(-289),
+             736 => $expand!(-288),
+             737 => $expand!(-287),
+             738 => $expand!(-286),
+             739 => $expand!(-285),
+             740 => $expand!(-284),
+             741 => $expand!(-283),
+             742 => $expand!(-282),
+             743 => $expand!(-281),
+             744 => $expand!(-280),
+             745 => $expand!(-279),
+             746 => $expand!(-278),
+             747 => $expand!(-277),
+             748 => $expand!(-276),
+             749 => $expand!(-275),
+             750 => $expand!(-274),
+             751 => $expand!(-273),
+             752 => $expand!(-272),
+             753 => $expand!(-271),
+             754 => $expand!(-270),
+             755 => $expand!(-269),
+             756 => $expand!(-268),
+             757 => $expand!(-267),
+             758 => $expand!(-266),
+             759 => $expand!(-265),
+             760 => $expand!(-264),
+             761 => $expand!(-263),
+             762 => $expand!(-262),
+             763 => $expand!(-261),
+             764 => $expand!(-260),
+             765 => $expand!(-259),
+             766 => $expand!(-258),
+             767 => $expand!(-257),
+             768 => $expand!(-256),
+             769 => $expand!(-255),
+             770 => $expand!(-254),
+             771 => $expand!(-253),
+             772 => $expand!(-252),
+             773 => $expand!(-251),
+             774 => $expand!(-250),
+             775 => $expand!(-249),
+             776 => $expand!(-248),
+             777 => $expand!(-247),
+             778 => $expand!(-246),
+             779 => $expand!(-245),
+             780 => $expand!(-244),
+             781 => $expand!(-243),
+             782 => $expand!(-242),
+             783 => $expand!(-241),
+             784 => $expand!(-240),
+             785 => $expand!(-239),
+             786 => $expand!(-238),
+             787 => $expand!(-237),
+             788 => $expand!(-236),
+             789 => $expand!(-235),
+             790 => $expand!(-234),
+             791 => $expand!(-233),
+             792 => $expand!(-232),
+             793 => $expand!(-231),
+             794 => $expand!(-230),
+             795 => $expand!(-229),
+             796 => $expand!(-228),
+             797 => $expand!(-227),
+             798 => $expand!(-226),
+             799 => $expand!(-225),
+             800 => $expand!(-224),
+             801 => $expand!(-223),
+             802 => $expand!(-222),
+             803 => $expand!(-221),
+             804 => $expand!(-220),
+             805 => $expand!(-219),
+             806 => $expand!(-218),
+             807 => $expand!(-217),
+             808 => $expand!(-216),
+             809 => $expand!(-215),
+             810 => $expand!(-214),
+             811 => $expand!(-213),
+             812 => $expand!(-212),
+             813 => $expand!(-211),
+             814 => $expand!(-210),
+             815 => $expand!(-209),
+             816 => $expand!(-208),
+             817 => $expand!(-207),
+             818 => $expand!(-206),
+             819 => $expand!(-205),
+             820 => $expand!(-204),
+             821 => $expand!(-203),
+             822 => $expand!(-202),
+             823 => $expand!(-201),
+             824 => $expand!(-200),
+             825 => $expand!(-199),
+             826 => $expand!(-198),
+             827 => $expand!(-197),
+             828 => $expand!(-196),
+             829 => $expand!(-195),
+             830 => $expand!(-194),
+             831 => $expand!(-193),
+             832 => $expand!(-192),
+             833 => $expand!(-191),
+             834 => $expand!(-190),
+             835 => $expand!(-189),
+             836 => $expand!(-188),
+             837 => $expand!(-187),
+             838 => $expand!(-186),
+             839 => $expand!(-185),
+             840 => $expand!(-184),
+             841 => $expand!(-183),
+             842 => $expand!(-182),
+             843 => $expand!(-181),
+             844 => $expand!(-180),
+             845 => $expand!(-179),
+             846 => $expand!(-178),
+             847 => $expand!(-177),
+             848 => $expand!(-176),
+             849 => $expand!(-175),
+             850 => $expand!(-174),
+             851 => $expand!(-173),
+             852 => $expand!(-172),
+             853 => $expand!(-171),
+             854 => $expand!(-170),
+             855 => $expand!(-169),
+             856 => $expand!(-168),
+             857 => $expand!(-167),
+             858 => $expand!(-166),
+             859 => $expand!(-165),
+             860 => $expand!(-164),
+             861 => $expand!(-163),
+             862 => $expand!(-162),
+             863 => $expand!(-161),
+             864 => $expand!(-160),
+             865 => $expand!(-159),
+             866 => $expand!(-158),
+             867 => $expand!(-157),
+             868 => $expand!(-156),
+             869 => $expand!(-155),
+             870 => $expand!(-154),
+             871 => $expand!(-153),
+             872 => $expand!(-152),
+             873 => $expand!(-151),
+             874 => $expand!(-150),
+             875 => $expand!(-149),
+             876 => $expand!(-148),
+             877 => $expand!(-147),
+             878 => $expand!(-146),
+             879 => $expand!(-145),
+             880 => $expand!(-144),
+             881 => $expand!(-143),
+             882 => $expand!(-142),
+             883 => $expand!(-141),
+             884 => $expand!(-140),
+             885 => $expand!(-139),
+             886 => $expand!(-138),
+             887 => $expand!(-137),
+             888 => $expand!(-136),
+             889 => $expand!(-135),
+             890 => $expand!(-134),
+             891 => $expand!(-133),
+             892 => $expand!(-132),
+             893 => $expand!(-131),
+             894 => $expand!(-130),
+             895 => $expand!(-129),
+             896 => $expand!(-128),
+             897 => $expand!(-127),
+             898 => $expand!(-126),
+             899 => $expand!(-125),
+             900 => $expand!(-124),
+             901 => $expand!(-123),
+             902 => $expand!(-122),
+             903 => $expand!(-121),
+             904 => $expand!(-120),
+             905 => $expand!(-119),
+             906 => $expand!(-118),
+             907 => $expand!(-117),
+             908 => $expand!(-116),
+             909 => $expand!(-115),
+             910 => $expand!(-114),
+             911 => $expand!(-113),
+             912 => $expand!(-112),
+             913 => $expand!(-111),
+             914 => $expand!(-110),
+             915 => $expand!(-109),
+             916 => $expand!(-108),
+             917 => $expand!(-107),
+             918 => $expand!(-106),
+             919 => $expand!(-105),
+             920 => $expand!(-104),
+             921 => $expand!(-103),
+             922 => $expand!(-102),
+             923 => $expand!(-101),
+             924 => $expand!(-100),
+             925 => $expand!(-99),
+             926 => $expand!(-98),
+             927 => $expand!(-97),
+             928 => $expand!(-96),
+             929 => $expand!(-95),
+             930 => $expand!(-94),
+             931 => $expand!(-93),
+             932 => $expand!(-92),
+             933 => $expand!(-91),
+             934 => $expand!(-90),
+             935 => $expand!(-89),
+             936 => $expand!(-88),
+             937 => $expand!(-87),
+             938 => $expand!(-86),
+             939 => $expand!(-85),
+             940 => $expand!(-84),
+             941 => $expand!(-83),
+             942 => $expand!(-82),
+             943 => $expand!(-81),
+             944 => $expand!(-80),
+             945 => $expand!(-79),
+             946 => $expand!(-78),
+             947 => $expand!(-77),
+             948 => $expand!(-76),
+             949 => $expand!(-75),
+             950 => $expand!(-74),
+             951 => $expand!(-73),
+             952 => $expand!(-72),
+             953 => $expand!(-71),
+             954 => $expand!(-70),
+             955 => $expand!(-69),
+             956 => $expand!(-68),
+             957 => $expand!(-67),
+             958 => $expand!(-66),
+             959 => $expand!(-65),
+             960 => $expand!(-64),
+             961 => $expand!(-63),
+             962 => $expand!(-62),
+             963 => $expand!(-61),
+             964 => $expand!(-60),
+             965 => $expand!(-59),
+             966 => $expand!(-58),
+             967 => $expand!(-57),
+             968 => $expand!(-56),
+             969 => $expand!(-55),
+             970 => $expand!(-54),
+             971 => $expand!(-53),
+             972 => $expand!(-52),
+             973 => $expand!(-51),
+             974 => $expand!(-50),
+             975 => $expand!(-49),
+             976 => $expand!(-48),
+             977 => $expand!(-47),
+             978 => $expand!(-46),
+             979 => $expand!(-45),
+             980 => $expand!(-44),
+             981 => $expand!(-43),
+             982 => $expand!(-42),
+             983 => $expand!(-41),
+             984 => $expand!(-40),
+             985 => $expand!(-39),
+             986 => $expand!(-38),
+             987 => $expand!(-37),
+             988 => $expand!(-36),
+             989 => $expand!(-35),
+             990 => $expand!(-34),
+             991 => $expand!(-33),
+             992 => $expand!(-32),
+             993 => $expand!(-31),
+             994 => $expand!(-30),
+             995 => $expand!(-29),
+             996 => $expand!(-28),
+             997 => $expand!(-27),
+             998 => $expand!(-26),
+             999 => $expand!(-25),
+             1000 => $expand!(-24),
+             1001 => $expand!(-23),
+             1002 => $expand!(-22),
+             1003 => $expand!(-21),
+             1004 => $expand!(-20),
+             1005 => $expand!(-19),
+             1006 => $expand!(-18),
+             1007 => $expand!(-17),
+             1008 => $expand!(-16),
+             1009 => $expand!(-15),
+             1010 => $expand!(-14),
+             1011 => $expand!(-13),
+             1012 => $expand!(-12),
+             1013 => $expand!(-11),
+             1014 => $expand!(-10),
+             1015 => $expand!(-9),
+             1016 => $expand!(-8),
+             1017 => $expand!(-7),
+             1018 => $expand!(-6),
+             1019 => $expand!(-5),
+             1020 => $expand!(-4),
+             1021 => $expand!(-3),
+             1022 => $expand!(-2),
+             1023 => $expand!(-1),
+             _ => $expand!(511),
+         }
+     };
+ }
+ 
+ //immediate value: 0:63
+ macro_rules! constify_imm6 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b11_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             31 => $expand!(31),
+             32 => $expand!(32),
+             33 => $expand!(33),
+             34 => $expand!(34),
+             35 => $expand!(35),
+             36 => $expand!(36),
+             37 => $expand!(37),
+             38 => $expand!(38),
+             39 => $expand!(39),
+             40 => $expand!(40),
+             41 => $expand!(41),
+             42 => $expand!(42),
+             43 => $expand!(43),
+             44 => $expand!(44),
+             45 => $expand!(45),
+             46 => $expand!(46),
+             47 => $expand!(47),
+             48 => $expand!(48),
+             49 => $expand!(49),
+             50 => $expand!(50),
+             51 => $expand!(51),
+             52 => $expand!(52),
+             53 => $expand!(53),
+             54 => $expand!(54),
+             55 => $expand!(55),
+             56 => $expand!(56),
+             57 => $expand!(57),
+             58 => $expand!(58),
+             59 => $expand!(59),
+             60 => $expand!(60),
+             61 => $expand!(61),
+             62 => $expand!(62),
+             _ => $expand!(63),
+         }
+     };
+ }
+ 
+ //immediate value: 0:31
+ macro_rules! constify_imm5 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             _ => $expand!(31),
+         }
+     };
+ }
+ 
+ //immediate value: -16:15
+ macro_rules! constify_imm_s5 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             16 => $expand!(-16),
+             17 => $expand!(-15),
+             18 => $expand!(-14),
+             19 => $expand!(-13),
+             20 => $expand!(-12),
+             21 => $expand!(-11),
+             22 => $expand!(-10),
+             23 => $expand!(-9),
+             24 => $expand!(-8),
+             25 => $expand!(-7),
+             26 => $expand!(-6),
+             27 => $expand!(-5),
+             28 => $expand!(-4),
+             29 => $expand!(-3),
+             30 => $expand!(-2),
+             31 => $expand!(-1),
+             _ => $expand!(15),
+         }
+     };
+ }
+ 
+ //immediate value: 0:15
+ macro_rules! constify_imm4 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             _ => $expand!(15),
+         }
+     };
+ }
+ 
+ //immediate value: 0:7
+ macro_rules! constify_imm3 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             _ => $expand!(7),
+         }
+     };
+ }
+ 
+ //immediate value: 0:3
+ macro_rules! constify_imm2 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b11 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             _ => $expand!(3),
+         }
+     };
+ }
+ 
+ //immediate value: 0:1
+ macro_rules! constify_imm1 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1 {
+             0 => $expand!(0),
+             _ => $expand!(1),
+         }
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mips/msa.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,18448 ----
+ //! MIPS SIMD Architecture intrinsics
+ //!
+ //! The reference is [MIPS Architecture for Programmers Volume IV-j: The
+ //! MIPS32 SIMD Architecture Module Revision 1.12][msa_ref].
+ //!
+ //! [msa_ref]: http://cdn2.imgtec.com/documentation/MD00866-2B-MSA32-AFP-01.12.pdf
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ use crate::mem;
+ 
+ #[macro_use]
+ mod macros;
+ 
+ types! {
+     // / MIPS-specific 128-bit wide vector of 16 packed `i8`.
+    pub struct v16i8(
+        i8, i8, i8, i8, i8, i8, i8, i8,
+        i8, i8, i8, i8, i8, i8, i8, i8,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 8 packed `i16`.
+    pub struct v8i16(
+        i16, i16, i16, i16, i16, i16, i16, i16,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 4 packed `i32`.
+    pub struct v4i32(
+        i32, i32, i32, i32,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 2 packed `i64`.
+    pub struct v2i64(
+        i64, i64,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 16 packed `u8`.
+    pub struct v16u8(
+        u8, u8, u8, u8, u8, u8, u8, u8,
+        u8, u8, u8, u8, u8, u8, u8, u8,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 8 packed `u16`.
+    pub struct v8u16(
+        u16, u16, u16, u16, u16, u16, u16, u16,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 4 packed `u32`.
+    pub struct v4u32(
+        u32, u32, u32, u32,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 2 packed `u64`.
+    pub struct v2u64(
+        u64, u64,
+    );
+ 
+    // / MIPS-specific 128-bit wide vector of 4 packed `f32`.
+    pub struct v4f32(
+        f32, f32, f32, f32,
+    );
+ 
+     // / MIPS-specific 128-bit wide vector of 2 packed `f64`.
+    pub struct v2f64(
+        f64, f64,
+    );
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.mips.add.a.b"]
+     fn msa_add_a_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.add.a.h"]
+     fn msa_add_a_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.add.a.w"]
+     fn msa_add_a_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.add.a.d"]
+     fn msa_add_a_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.adds.a.b"]
+     fn msa_adds_a_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.adds.a.h"]
+     fn msa_adds_a_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.adds.a.w"]
+     fn msa_adds_a_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.adds.a.d"]
+     fn msa_adds_a_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.adds.s.b"]
+     fn msa_adds_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.adds.s.h"]
+     fn msa_adds_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.adds.s.w"]
+     fn msa_adds_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.adds.s.d"]
+     fn msa_adds_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.adds.u.b"]
+     fn msa_adds_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.adds.u.h"]
+     fn msa_adds_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.adds.u.w"]
+     fn msa_adds_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.adds.u.d"]
+     fn msa_adds_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.addv.b"]
+     fn msa_addv_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.addv.h"]
+     fn msa_addv_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.addv.w"]
+     fn msa_addv_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.addv.d"]
+     fn msa_addv_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.addvi.b"]
+     fn msa_addvi_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.addvi.h"]
+     fn msa_addvi_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.addvi.w"]
+     fn msa_addvi_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.addvi.d"]
+     fn msa_addvi_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.and.v"]
+     fn msa_and_v(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.andi.b"]
+     fn msa_andi_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.asub.s.b"]
+     fn msa_asub_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.asub.s.h"]
+     fn msa_asub_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.asub.s.w"]
+     fn msa_asub_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.asub.s.d"]
+     fn msa_asub_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.asub.u.b"]
+     fn msa_asub_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.asub.u.h"]
+     fn msa_asub_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.asub.u.w"]
+     fn msa_asub_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.asub.u.d"]
+     fn msa_asub_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.ave.s.b"]
+     fn msa_ave_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.ave.s.h"]
+     fn msa_ave_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.ave.s.w"]
+     fn msa_ave_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.ave.s.d"]
+     fn msa_ave_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.ave.u.b"]
+     fn msa_ave_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.ave.u.h"]
+     fn msa_ave_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.ave.u.w"]
+     fn msa_ave_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.ave.u.d"]
+     fn msa_ave_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.aver.s.b"]
+     fn msa_aver_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.aver.s.h"]
+     fn msa_aver_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.aver.s.w"]
+     fn msa_aver_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.aver.s.d"]
+     fn msa_aver_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.aver.u.b"]
+     fn msa_aver_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.aver.u.h"]
+     fn msa_aver_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.aver.u.w"]
+     fn msa_aver_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.aver.u.d"]
+     fn msa_aver_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.bclr.b"]
+     fn msa_bclr_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.bclr.h"]
+     fn msa_bclr_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.bclr.w"]
+     fn msa_bclr_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.bclr.d"]
+     fn msa_bclr_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.bclri.b"]
+     fn msa_bclri_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.bclri.h"]
+     fn msa_bclri_h(a: v8u16, b: i32) -> v8u16;
+     #[link_name = "llvm.mips.bclri.w"]
+     fn msa_bclri_w(a: v4u32, b: i32) -> v4u32;
+     #[link_name = "llvm.mips.bclri.d"]
+     fn msa_bclri_d(a: v2u64, b: i32) -> v2u64;
+     #[link_name = "llvm.mips.binsl.b"]
+     fn msa_binsl_b(a: v16u8, b: v16u8, c: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.binsl.h"]
+     fn msa_binsl_h(a: v8u16, b: v8u16, c: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.binsl.w"]
+     fn msa_binsl_w(a: v4u32, b: v4u32, c: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.binsl.d"]
+     fn msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.binsli.b"]
+     fn msa_binsli_b(a: v16u8, b: v16u8, c: i32) -> v16u8;
+     #[link_name = "llvm.mips.binsli.h"]
+     fn msa_binsli_h(a: v8u16, b: v8u16, c: i32) -> v8u16;
+     #[link_name = "llvm.mips.binsli.w"]
+     fn msa_binsli_w(a: v4u32, b: v4u32, c: i32) -> v4u32;
+     #[link_name = "llvm.mips.binsli.d"]
+     fn msa_binsli_d(a: v2u64, b: v2u64, c: i32) -> v2u64;
+     #[link_name = "llvm.mips.binsr.b"]
+     fn msa_binsr_b(a: v16u8, b: v16u8, c: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.binsr.h"]
+     fn msa_binsr_h(a: v8u16, b: v8u16, c: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.binsr.w"]
+     fn msa_binsr_w(a: v4u32, b: v4u32, c: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.binsr.d"]
+     fn msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.binsri.b"]
+     fn msa_binsri_b(a: v16u8, b: v16u8, c: i32) -> v16u8;
+     #[link_name = "llvm.mips.binsri.h"]
+     fn msa_binsri_h(a: v8u16, b: v8u16, c: i32) -> v8u16;
+     #[link_name = "llvm.mips.binsri.w"]
+     fn msa_binsri_w(a: v4u32, b: v4u32, c: i32) -> v4u32;
+     #[link_name = "llvm.mips.binsri.d"]
+     fn msa_binsri_d(a: v2u64, b: v2u64, c: i32) -> v2u64;
+     #[link_name = "llvm.mips.bmnz.v"]
+     fn msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.bmnzi.b"]
+     fn msa_bmnzi_b(a: v16u8, b: v16u8, c: i32) -> v16u8;
+     #[link_name = "llvm.mips.bmz.v"]
+     fn msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.bmzi.b"]
+     fn msa_bmzi_b(a: v16u8, b: v16u8, c: i32) -> v16u8;
+     #[link_name = "llvm.mips.bneg.b"]
+     fn msa_bneg_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.bneg.h"]
+     fn msa_bneg_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.bneg.w"]
+     fn msa_bneg_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.bneg.d"]
+     fn msa_bneg_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.bnegi.b"]
+     fn msa_bnegi_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.bnegi.h"]
+     fn msa_bnegi_h(a: v8u16, b: i32) -> v8u16;
+     #[link_name = "llvm.mips.bnegi.w"]
+     fn msa_bnegi_w(a: v4u32, b: i32) -> v4u32;
+     #[link_name = "llvm.mips.bnegi.d"]
+     fn msa_bnegi_d(a: v2u64, b: i32) -> v2u64;
+     #[link_name = "llvm.mips.bnz.b"]
+     fn msa_bnz_b(a: v16u8) -> i32;
+     #[link_name = "llvm.mips.bnz.h"]
+     fn msa_bnz_h(a: v8u16) -> i32;
+     #[link_name = "llvm.mips.bnz.w"]
+     fn msa_bnz_w(a: v4u32) -> i32;
+     #[link_name = "llvm.mips.bnz.d"]
+     fn msa_bnz_d(a: v2u64) -> i32;
+     #[link_name = "llvm.mips.bnz.v"]
+     fn msa_bnz_v(a: v16u8) -> i32;
+     #[link_name = "llvm.mips.bsel.v"]
+     fn msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.bseli.b"]
+     fn msa_bseli_b(a: v16u8, b: v16u8, c: i32) -> v16u8;
+     #[link_name = "llvm.mips.bset.b"]
+     fn msa_bset_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.bset.h"]
+     fn msa_bset_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.bset.w"]
+     fn msa_bset_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.bset.d"]
+     fn msa_bset_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.bseti.b"]
+     fn msa_bseti_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.bseti.h"]
+     fn msa_bseti_h(a: v8u16, b: i32) -> v8u16;
+     #[link_name = "llvm.mips.bseti.w"]
+     fn msa_bseti_w(a: v4u32, b: i32) -> v4u32;
+     #[link_name = "llvm.mips.bseti.d"]
+     fn msa_bseti_d(a: v2u64, b: i32) -> v2u64;
+     #[link_name = "llvm.mips.bz.b"]
+     fn msa_bz_b(a: v16u8) -> i32;
+     #[link_name = "llvm.mips.bz.h"]
+     fn msa_bz_h(a: v8u16) -> i32;
+     #[link_name = "llvm.mips.bz.w"]
+     fn msa_bz_w(a: v4u32) -> i32;
+     #[link_name = "llvm.mips.bz.d"]
+     fn msa_bz_d(a: v2u64) -> i32;
+     #[link_name = "llvm.mips.bz.v"]
+     fn msa_bz_v(a: v16u8) -> i32;
+     #[link_name = "llvm.mips.ceq.b"]
+     fn msa_ceq_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.ceq.h"]
+     fn msa_ceq_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.ceq.w"]
+     fn msa_ceq_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.ceq.d"]
+     fn msa_ceq_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.ceqi.b"]
+     fn msa_ceqi_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.ceqi.h"]
+     fn msa_ceqi_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.ceqi.w"]
+     fn msa_ceqi_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.ceqi.d"]
+     fn msa_ceqi_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.cfcmsa"]
+     fn msa_cfcmsa(a: i32) -> i32;
+     #[link_name = "llvm.mips.cle.s.b"]
+     fn msa_cle_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.cle.s.h"]
+     fn msa_cle_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.cle.s.w"]
+     fn msa_cle_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.cle.s.d"]
+     fn msa_cle_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.cle.u.b"]
+     fn msa_cle_u_b(a: v16u8, b: v16u8) -> v16i8;
+     #[link_name = "llvm.mips.cle.u.h"]
+     fn msa_cle_u_h(a: v8u16, b: v8u16) -> v8i16;
+     #[link_name = "llvm.mips.cle.u.w"]
+     fn msa_cle_u_w(a: v4u32, b: v4u32) -> v4i32;
+     #[link_name = "llvm.mips.cle.u.d"]
+     fn msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64;
+     #[link_name = "llvm.mips.clei.s.b"]
+     fn msa_clei_s_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.clei.s.h"]
+     fn msa_clei_s_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.clei.s.w"]
+     fn msa_clei_s_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.clei.s.d"]
+     fn msa_clei_s_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.clei.u.b"]
+     fn msa_clei_u_b(a: v16u8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.clei.u.h"]
+     fn msa_clei_u_h(a: v8u16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.clei.u.w"]
+     fn msa_clei_u_w(a: v4u32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.clei.u.d"]
+     fn msa_clei_u_d(a: v2u64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.clt.s.b"]
+     fn msa_clt_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.clt.s.h"]
+     fn msa_clt_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.clt.s.w"]
+     fn msa_clt_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.clt.s.d"]
+     fn msa_clt_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.clt.u.b"]
+     fn msa_clt_u_b(a: v16u8, b: v16u8) -> v16i8;
+     #[link_name = "llvm.mips.clt.u.h"]
+     fn msa_clt_u_h(a: v8u16, b: v8u16) -> v8i16;
+     #[link_name = "llvm.mips.clt.u.w"]
+     fn msa_clt_u_w(a: v4u32, b: v4u32) -> v4i32;
+     #[link_name = "llvm.mips.clt.u.d"]
+     fn msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64;
+     #[link_name = "llvm.mips.clti.s.b"]
+     fn msa_clti_s_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.clti.s.h"]
+     fn msa_clti_s_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.clti.s.w"]
+     fn msa_clti_s_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.clti.s.d"]
+     fn msa_clti_s_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.clti.u.b"]
+     fn msa_clti_u_b(a: v16u8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.clti.u.h"]
+     fn msa_clti_u_h(a: v8u16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.clti.u.w"]
+     fn msa_clti_u_w(a: v4u32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.clti.u.d"]
+     fn msa_clti_u_d(a: v2u64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.copy.s.b"]
+     fn msa_copy_s_b(a: v16i8, b: i32) -> i32;
+     #[link_name = "llvm.mips.copy.s.h"]
+     fn msa_copy_s_h(a: v8i16, b: i32) -> i32;
+     #[link_name = "llvm.mips.copy.s.w"]
+     fn msa_copy_s_w(a: v4i32, b: i32) -> i32;
+     #[link_name = "llvm.mips.copy.s.d"]
+     fn msa_copy_s_d(a: v2i64, b: i32) -> i64;
+     #[link_name = "llvm.mips.copy.u.b"]
+     fn msa_copy_u_b(a: v16i8, b: i32) -> u32;
+     #[link_name = "llvm.mips.copy.u.h"]
+     fn msa_copy_u_h(a: v8i16, b: i32) -> u32;
+     #[link_name = "llvm.mips.copy.u.w"]
+     fn msa_copy_u_w(a: v4i32, b: i32) -> u32;
+     #[link_name = "llvm.mips.copy.u.d"]
+     fn msa_copy_u_d(a: v2i64, b: i32) -> u64;
+     #[link_name = "llvm.mips.ctcmsa"]
+     fn msa_ctcmsa(imm5: i32, a: i32) -> ();
+     #[link_name = "llvm.mips.div.s.b"]
+     fn msa_div_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.div.s.h"]
+     fn msa_div_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.div.s.w"]
+     fn msa_div_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.div.s.d"]
+     fn msa_div_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.div.u.b"]
+     fn msa_div_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.div.u.h"]
+     fn msa_div_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.div.u.w"]
+     fn msa_div_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.div.u.d"]
+     fn msa_div_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.dotp.s.h"]
+     fn msa_dotp_s_h(a: v16i8, b: v16i8) -> v8i16;
+     #[link_name = "llvm.mips.dotp.s.w"]
+     fn msa_dotp_s_w(a: v8i16, b: v8i16) -> v4i32;
+     #[link_name = "llvm.mips.dotp.s.d"]
+     fn msa_dotp_s_d(a: v4i32, b: v4i32) -> v2i64;
+     #[link_name = "llvm.mips.dotp.u.h"]
+     fn msa_dotp_u_h(a: v16u8, b: v16u8) -> v8u16;
+     #[link_name = "llvm.mips.dotp.u.w"]
+     fn msa_dotp_u_w(a: v8u16, b: v8u16) -> v4u32;
+     #[link_name = "llvm.mips.dotp.u.d"]
+     fn msa_dotp_u_d(a: v4u32, b: v4u32) -> v2u64;
+     #[link_name = "llvm.mips.dpadd.s.h"]
+     fn msa_dpadd_s_h(a: v8i16, b: v16i8, c: v16i8) -> v8i16;
+     #[link_name = "llvm.mips.dpadd.s.w"]
+     fn msa_dpadd_s_w(a: v4i32, b: v8i16, c: v8i16) -> v4i32;
+     #[link_name = "llvm.mips.dpadd.s.d"]
+     fn msa_dpadd_s_d(a: v2i64, b: v4i32, c: v4i32) -> v2i64;
+     #[link_name = "llvm.mips.dpadd.u.h"]
+     fn msa_dpadd_u_h(a: v8u16, b: v16u8, c: v16u8) -> v8u16;
+     #[link_name = "llvm.mips.dpadd.u.w"]
+     fn msa_dpadd_u_w(a: v4u32, b: v8u16, c: v8u16) -> v4u32;
+     #[link_name = "llvm.mips.dpadd.u.d"]
+     fn msa_dpadd_u_d(a: v2u64, b: v4u32, c: v4u32) -> v2u64;
+     #[link_name = "llvm.mips.dpsub.s.h"]
+     fn msa_dpsub_s_h(a: v8i16, b: v16i8, c: v16i8) -> v8i16;
+     #[link_name = "llvm.mips.dpsub.s.w"]
+     fn msa_dpsub_s_w(a: v4i32, b: v8i16, c: v8i16) -> v4i32;
+     #[link_name = "llvm.mips.dpsub.s.d"]
+     fn msa_dpsub_s_d(a: v2i64, b: v4i32, c: v4i32) -> v2i64;
+     #[link_name = "llvm.mips.dpsub.u.h"]
+     fn msa_dpsub_u_h(a: v8i16, b: v16u8, c: v16u8) -> v8i16;
+     #[link_name = "llvm.mips.dpsub.u.w"]
+     fn msa_dpsub_u_w(a: v4i32, b: v8u16, c: v8u16) -> v4i32;
+     #[link_name = "llvm.mips.dpsub.u.d"]
+     fn msa_dpsub_u_d(a: v2i64, b: v4u32, c: v4u32) -> v2i64;
+     #[link_name = "llvm.mips.fadd.w"]
+     fn msa_fadd_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fadd.d"]
+     fn msa_fadd_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fcaf.w"]
+     fn msa_fcaf_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcaf.d"]
+     fn msa_fcaf_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fceq.w"]
+     fn msa_fceq_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fceq.d"]
+     fn msa_fceq_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fclass.w"]
+     fn msa_fclass_w(a: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fclass.d"]
+     fn msa_fclass_d(a: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcle.w"]
+     fn msa_fcle_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcle.d"]
+     fn msa_fcle_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fclt.w"]
+     fn msa_fclt_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fclt.d"]
+     fn msa_fclt_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcne.w"]
+     fn msa_fcne_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcne.d"]
+     fn msa_fcne_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcor.w"]
+     fn msa_fcor_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcor.d"]
+     fn msa_fcor_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcueq.w"]
+     fn msa_fcueq_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcueq.d"]
+     fn msa_fcueq_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcule.w"]
+     fn msa_fcule_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcule.d"]
+     fn msa_fcule_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcult.w"]
+     fn msa_fcult_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcult.d"]
+     fn msa_fcult_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcun.w"]
+     fn msa_fcun_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcun.d"]
+     fn msa_fcun_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fcune.w"]
+     fn msa_fcune_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fcune.d"]
+     fn msa_fcune_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fdiv.w"]
+     fn msa_fdiv_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fdiv.d"]
+     fn msa_fdiv_d(a: v2f64, b: v2f64) -> v2f64;
+     // FIXME: 16-bit floats
+     // #[link_name = "llvm.mips.fexdo.h"]
+     // fn msa_fexdo_h(a: v4f32, b: v4f32) -> f16x8;
+     #[link_name = "llvm.mips.fexdo.w"]
+     fn msa_fexdo_w(a: v2f64, b: v2f64) -> v4f32;
+     #[link_name = "llvm.mips.fexp2.w"]
+     fn msa_fexp2_w(a: v4f32, b: v4i32) -> v4f32;
+     #[link_name = "llvm.mips.fexp2.d"]
+     fn msa_fexp2_d(a: v2f64, b: v2i64) -> v2f64;
+     #[link_name = "llvm.mips.fexupl.w"]
+     // FIXME: 16-bit floats
+     // fn msa_fexupl_w(a: f16x8) -> v4f32;
+     #[link_name = "llvm.mips.fexupl.d"]
+     fn msa_fexupl_d(a: v4f32) -> v2f64;
+     // FIXME: 16-bit floats
+     // #[link_name = "llvm.mips.fexupr.w"]
+     // fn msa_fexupr_w(a: f16x8) -> v4f32;
+     #[link_name = "llvm.mips.fexupr.d"]
+     fn msa_fexupr_d(a: v4f32) -> v2f64;
+     #[link_name = "llvm.mips.ffint.s.w"]
+     fn msa_ffint_s_w(a: v4i32) -> v4f32;
+     #[link_name = "llvm.mips.ffint.s.d"]
+     fn msa_ffint_s_d(a: v2i64) -> v2f64;
+     #[link_name = "llvm.mips.ffint.u.w"]
+     fn msa_ffint_u_w(a: v4u32) -> v4f32;
+     #[link_name = "llvm.mips.ffint.u.d"]
+     fn msa_ffint_u_d(a: v2u64) -> v2f64;
+     #[link_name = "llvm.mips.ffql.w"]
+     fn msa_ffql_w(a: v8i16) -> v4f32;
+     #[link_name = "llvm.mips.ffql.d"]
+     fn msa_ffql_d(a: v4i32) -> v2f64;
+     #[link_name = "llvm.mips.ffqr.w"]
+     fn msa_ffqr_w(a: v8i16) -> v4f32;
+     #[link_name = "llvm.mips.ffqr.d"]
+     fn msa_ffqr_d(a: v4i32) -> v2f64;
+     #[link_name = "llvm.mips.fill.b"]
+     fn msa_fill_b(a: i32) -> v16i8;
+     #[link_name = "llvm.mips.fill.h"]
+     fn msa_fill_h(a: i32) -> v8i16;
+     #[link_name = "llvm.mips.fill.w"]
+     fn msa_fill_w(a: i32) -> v4i32;
+     #[link_name = "llvm.mips.fill.d"]
+     fn msa_fill_d(a: i64) -> v2i64;
+     #[link_name = "llvm.mips.flog2.w"]
+     fn msa_flog2_w(a: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.flog2.d"]
+     fn msa_flog2_d(a: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmadd.w"]
+     fn msa_fmadd_w(a: v4f32, b: v4f32, c: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmadd.d"]
+     fn msa_fmadd_d(a: v2f64, b: v2f64, c: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmax.w"]
+     fn msa_fmax_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmax.d"]
+     fn msa_fmax_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmax.a.w"]
+     fn msa_fmax_a_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmax.a.d"]
+     fn msa_fmax_a_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmin.w"]
+     fn msa_fmin_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmin.d"]
+     fn msa_fmin_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmin.a.w"]
+     fn msa_fmin_a_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmin.a.d"]
+     fn msa_fmin_a_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmsub.w"]
+     fn msa_fmsub_w(a: v4f32, b: v4f32, c: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmsub.d"]
+     fn msa_fmsub_d(a: v2f64, b: v2f64, c: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fmul.w"]
+     fn msa_fmul_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fmul.d"]
+     fn msa_fmul_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.frint.w"]
+     fn msa_frint_w(a: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.frint.d"]
+     fn msa_frint_d(a: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.frcp.w"]
+     fn msa_frcp_w(a: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.frcp.d"]
+     fn msa_frcp_d(a: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.frsqrt.w"]
+     fn msa_frsqrt_w(a: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.frsqrt.d"]
+     fn msa_frsqrt_d(a: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fsaf.w"]
+     fn msa_fsaf_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsaf.d"]
+     fn msa_fsaf_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fseq.w"]
+     fn msa_fseq_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fseq.d"]
+     fn msa_fseq_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsle.w"]
+     fn msa_fsle_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsle.d"]
+     fn msa_fsle_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fslt.w"]
+     fn msa_fslt_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fslt.d"]
+     fn msa_fslt_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsne.w"]
+     fn msa_fsne_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsne.d"]
+     fn msa_fsne_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsor.w"]
+     fn msa_fsor_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsor.d"]
+     fn msa_fsor_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsqrt.w"]
+     fn msa_fsqrt_w(a: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fsqrt.d"]
+     fn msa_fsqrt_d(a: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fsub.w"]
+     fn msa_fsub_w(a: v4f32, b: v4f32) -> v4f32;
+     #[link_name = "llvm.mips.fsub.d"]
+     fn msa_fsub_d(a: v2f64, b: v2f64) -> v2f64;
+     #[link_name = "llvm.mips.fsueq.w"]
+     fn msa_fsueq_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsueq.d"]
+     fn msa_fsueq_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsule.w"]
+     fn msa_fsule_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsule.d"]
+     fn msa_fsule_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsult.w"]
+     fn msa_fsult_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsult.d"]
+     fn msa_fsult_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsun.w"]
+     fn msa_fsun_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsun.d"]
+     fn msa_fsun_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.fsune.w"]
+     fn msa_fsune_w(a: v4f32, b: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.fsune.d"]
+     fn msa_fsune_d(a: v2f64, b: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.ftint.s.w"]
+     fn msa_ftint_s_w(a: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.ftint.s.d"]
+     fn msa_ftint_s_d(a: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.ftint.u.w"]
+     fn msa_ftint_u_w(a: v4f32) -> v4u32;
+     #[link_name = "llvm.mips.ftint.u.d"]
+     fn msa_ftint_u_d(a: v2f64) -> v2u64;
+     #[link_name = "llvm.mips.ftq.h"]
+     fn msa_ftq_h(a: v4f32, b: v4f32) -> v8i16;
+     #[link_name = "llvm.mips.ftq.w"]
+     fn msa_ftq_w(a: v2f64, b: v2f64) -> v4i32;
+     #[link_name = "llvm.mips.ftrunc.s.w"]
+     fn msa_ftrunc_s_w(a: v4f32) -> v4i32;
+     #[link_name = "llvm.mips.ftrunc.s.d"]
+     fn msa_ftrunc_s_d(a: v2f64) -> v2i64;
+     #[link_name = "llvm.mips.ftrunc.u.w"]
+     fn msa_ftrunc_u_w(a: v4f32) -> v4u32;
+     #[link_name = "llvm.mips.ftrunc.u.d"]
+     fn msa_ftrunc_u_d(a: v2f64) -> v2u64;
+     #[link_name = "llvm.mips.hadd.s.h"]
+     fn msa_hadd_s_h(a: v16i8, b: v16i8) -> v8i16;
+     #[link_name = "llvm.mips.hadd.s.w"]
+     fn msa_hadd_s_w(a: v8i16, b: v8i16) -> v4i32;
+     #[link_name = "llvm.mips.hadd.s.d"]
+     fn msa_hadd_s_d(a: v4i32, b: v4i32) -> v2i64;
+     #[link_name = "llvm.mips.hadd.u.h"]
+     fn msa_hadd_u_h(a: v16u8, b: v16u8) -> v8u16;
+     #[link_name = "llvm.mips.hadd.u.w"]
+     fn msa_hadd_u_w(a: v8u16, b: v8u16) -> v4u32;
+     #[link_name = "llvm.mips.hadd.u.d"]
+     fn msa_hadd_u_d(a: v4u32, b: v4u32) -> v2u64;
+     #[link_name = "llvm.mips.hsub.s.h"]
+     fn msa_hsub_s_h(a: v16i8, b: v16i8) -> v8i16;
+     #[link_name = "llvm.mips.hsub.s.w"]
+     fn msa_hsub_s_w(a: v8i16, b: v8i16) -> v4i32;
+     #[link_name = "llvm.mips.hsub.s.d"]
+     fn msa_hsub_s_d(a: v4i32, b: v4i32) -> v2i64;
+     #[link_name = "llvm.mips.hsub.u.h"]
+     fn msa_hsub_u_h(a: v16u8, b: v16u8) -> v8i16;
+     #[link_name = "llvm.mips.hsub.u.w"]
+     fn msa_hsub_u_w(a: v8u16, b: v8u16) -> v4i32;
+     #[link_name = "llvm.mips.hsub.u.d"]
+     fn msa_hsub_u_d(a: v4u32, b: v4u32) -> v2i64;
+     #[link_name = "llvm.mips.ilvev.b"]
+     fn msa_ilvev_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.ilvev.h"]
+     fn msa_ilvev_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.ilvev.w"]
+     fn msa_ilvev_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.ilvev.d"]
+     fn msa_ilvev_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.ilvl.b"]
+     fn msa_ilvl_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.ilvl.h"]
+     fn msa_ilvl_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.ilvl.w"]
+     fn msa_ilvl_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.ilvl.d"]
+     fn msa_ilvl_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.ilvod.b"]
+     fn msa_ilvod_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.ilvod.h"]
+     fn msa_ilvod_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.ilvod.w"]
+     fn msa_ilvod_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.ilvod.d"]
+     fn msa_ilvod_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.ilvr.b"]
+     fn msa_ilvr_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.ilvr.h"]
+     fn msa_ilvr_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.ilvr.w"]
+     fn msa_ilvr_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.ilvr.d"]
+     fn msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.insert.b"]
+     fn msa_insert_b(a: v16i8, b: i32, c: i32) -> v16i8;
+     #[link_name = "llvm.mips.insert.h"]
+     fn msa_insert_h(a: v8i16, b: i32, c: i32) -> v8i16;
+     #[link_name = "llvm.mips.insert.w"]
+     fn msa_insert_w(a: v4i32, b: i32, c: i32) -> v4i32;
+     #[link_name = "llvm.mips.insert.d"]
+     fn msa_insert_d(a: v2i64, b: i32, c: i64) -> v2i64;
+     #[link_name = "llvm.mips.insve.b"]
+     fn msa_insve_b(a: v16i8, b: i32, c: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.insve.h"]
+     fn msa_insve_h(a: v8i16, b: i32, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.insve.w"]
+     fn msa_insve_w(a: v4i32, b: i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.insve.d"]
+     fn msa_insve_d(a: v2i64, b: i32, c: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.ld.b"]
+     fn msa_ld_b(mem_addr: *mut u8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.ld.h"]
+     fn msa_ld_h(mem_addr: *mut u8, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.ld.w"]
+     fn msa_ld_w(mem_addr: *mut u8, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.ld.d"]
+     fn msa_ld_d(mem_addr: *mut u8, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.ldi.b"]
+     fn msa_ldi_b(a: i32) -> v16i8;
+     #[link_name = "llvm.mips.ldi.h"]
+     fn msa_ldi_h(a: i32) -> v8i16;
+     #[link_name = "llvm.mips.ldi.w"]
+     fn msa_ldi_w(a: i32) -> v4i32;
+     #[link_name = "llvm.mips.ldi.d"]
+     fn msa_ldi_d(a: i32) -> v2i64;
+     #[link_name = "llvm.mips.madd.q.h"]
+     fn msa_madd_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.madd.q.w"]
+     fn msa_madd_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.maddr.q.h"]
+     fn msa_maddr_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.maddr.q.w"]
+     fn msa_maddr_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.maddv.b"]
+     fn msa_maddv_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.maddv.h"]
+     fn msa_maddv_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.maddv.w"]
+     fn msa_maddv_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.maddv.d"]
+     fn msa_maddv_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.max.a.b"]
+     fn msa_max_a_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.max.a.h"]
+     fn msa_max_a_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.max.a.w"]
+     fn msa_max_a_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.max.a.d"]
+     fn msa_max_a_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.max.s.b"]
+     fn msa_max_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.max.s.h"]
+     fn msa_max_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.max.s.w"]
+     fn msa_max_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.max.s.d"]
+     fn msa_max_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.max.u.b"]
+     fn msa_max_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.max.u.h"]
+     fn msa_max_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.max.u.w"]
+     fn msa_max_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.max.u.d"]
+     fn msa_max_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.maxi.s.b"]
+     fn msa_maxi_s_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.maxi.s.h"]
+     fn msa_maxi_s_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.maxi.s.w"]
+     fn msa_maxi_s_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.maxi.s.d"]
+     fn msa_maxi_s_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.maxi.u.b"]
+     fn msa_maxi_u_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.maxi.u.h"]
+     fn msa_maxi_u_h(a: v8u16, b: i32) -> v8u16;
+     #[link_name = "llvm.mips.maxi.u.w"]
+     fn msa_maxi_u_w(a: v4u32, b: i32) -> v4u32;
+     #[link_name = "llvm.mips.maxi.u.d"]
+     fn msa_maxi_u_d(a: v2u64, b: i32) -> v2u64;
+     #[link_name = "llvm.mips.min.a.b"]
+     fn msa_min_a_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.min.a.h"]
+     fn msa_min_a_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.min.a.w"]
+     fn msa_min_a_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.min.a.d"]
+     fn msa_min_a_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.min.s.b"]
+     fn msa_min_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.min.s.h"]
+     fn msa_min_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.min.s.w"]
+     fn msa_min_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.min.s.d"]
+     fn msa_min_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.min.u.b"]
+     fn msa_min_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.min.u.h"]
+     fn msa_min_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.min.u.w"]
+     fn msa_min_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.min.u.d"]
+     fn msa_min_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.mini.s.b"]
+     fn msa_mini_s_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.mini.s.h"]
+     fn msa_mini_s_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.mini.s.w"]
+     fn msa_mini_s_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.mini.s.d"]
+     fn msa_mini_s_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.mini.u.b"]
+     fn msa_mini_u_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.mini.u.h"]
+     fn msa_mini_u_h(a: v8u16, b: i32) -> v8u16;
+     #[link_name = "llvm.mips.mini.u.w"]
+     fn msa_mini_u_w(a: v4u32, b: i32) -> v4u32;
+     #[link_name = "llvm.mips.mini.u.d"]
+     fn msa_mini_u_d(a: v2u64, b: i32) -> v2u64;
+     #[link_name = "llvm.mips.mod.s.b"]
+     fn msa_mod_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.mod.s.h"]
+     fn msa_mod_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.mod.s.w"]
+     fn msa_mod_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.mod.s.d"]
+     fn msa_mod_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.mod.u.b"]
+     fn msa_mod_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.mod.u.h"]
+     fn msa_mod_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.mod.u.w"]
+     fn msa_mod_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.mod.u.d"]
+     fn msa_mod_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.move.v"]
+     fn msa_move_v(a: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.msub.q.h"]
+     fn msa_msub_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.msub.q.w"]
+     fn msa_msub_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.msubr.q.h"]
+     fn msa_msubr_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.msubr.q.w"]
+     fn msa_msubr_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.msubv.b"]
+     fn msa_msubv_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.msubv.h"]
+     fn msa_msubv_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.msubv.w"]
+     fn msa_msubv_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.msubv.d"]
+     fn msa_msubv_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.mul.q.h"]
+     fn msa_mul_q_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.mul.q.w"]
+     fn msa_mul_q_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.mulr.q.h"]
+     fn msa_mulr_q_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.mulr.q.w"]
+     fn msa_mulr_q_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.mulv.b"]
+     fn msa_mulv_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.mulv.h"]
+     fn msa_mulv_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.mulv.w"]
+     fn msa_mulv_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.mulv.d"]
+     fn msa_mulv_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.nloc.b"]
+     fn msa_nloc_b(a: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.nloc.h"]
+     fn msa_nloc_h(a: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.nloc.w"]
+     fn msa_nloc_w(a: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.nloc.d"]
+     fn msa_nloc_d(a: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.nlzc.b"]
+     fn msa_nlzc_b(a: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.nlzc.h"]
+     fn msa_nlzc_h(a: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.nlzc.w"]
+     fn msa_nlzc_w(a: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.nlzc.d"]
+     fn msa_nlzc_d(a: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.nor.v"]
+     fn msa_nor_v(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.nori.b"]
+     fn msa_nori_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.or.v"]
+     fn msa_or_v(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.ori.b"]
+     fn msa_ori_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.pckev.b"]
+     fn msa_pckev_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.pckev.h"]
+     fn msa_pckev_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.pckev.w"]
+     fn msa_pckev_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.pckev.d"]
+     fn msa_pckev_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.pckod.b"]
+     fn msa_pckod_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.pckod.h"]
+     fn msa_pckod_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.pckod.w"]
+     fn msa_pckod_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.pckod.d"]
+     fn msa_pckod_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.pcnt.b"]
+     fn msa_pcnt_b(a: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.pcnt.h"]
+     fn msa_pcnt_h(a: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.pcnt.w"]
+     fn msa_pcnt_w(a: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.pcnt.d"]
+     fn msa_pcnt_d(a: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.sat.s.b"]
+     fn msa_sat_s_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.sat.s.h"]
+     fn msa_sat_s_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.sat.s.w"]
+     fn msa_sat_s_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.sat.s.d"]
+     fn msa_sat_s_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.sat.u.b"]
+     fn msa_sat_u_b(a: v16u8, b: i32) -> v16u8;
+     #[link_name = "llvm.mips.sat.u.h"]
+     fn msa_sat_u_h(a: v8u16, b: i32) -> v8u16;
+     #[link_name = "llvm.mips.sat.u.w"]
+     fn msa_sat_u_w(a: v4u32, b: i32) -> v4u32;
+     #[link_name = "llvm.mips.sat.u.d"]
+     fn msa_sat_u_d(a: v2u64, b: i32) -> v2u64;
+     #[link_name = "llvm.mips.shf.b"]
+     fn msa_shf_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.shf.h"]
+     fn msa_shf_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.shf.w"]
+     fn msa_shf_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.sld.b"]
+     fn msa_sld_b(a: v16i8, b: v16i8, c: i32) -> v16i8;
+     #[link_name = "llvm.mips.sld.h"]
+     fn msa_sld_h(a: v8i16, b: v8i16, c: i32) -> v8i16;
+     #[link_name = "llvm.mips.sld.w"]
+     fn msa_sld_w(a: v4i32, b: v4i32, c: i32) -> v4i32;
+     #[link_name = "llvm.mips.sld.d"]
+     fn msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64;
+     #[link_name = "llvm.mips.sldi.b"]
+     fn msa_sldi_b(a: v16i8, b: v16i8, c: i32) -> v16i8;
+     #[link_name = "llvm.mips.sldi.h"]
+     fn msa_sldi_h(a: v8i16, b: v8i16, c: i32) -> v8i16;
+     #[link_name = "llvm.mips.sldi.w"]
+     fn msa_sldi_w(a: v4i32, b: v4i32, c: i32) -> v4i32;
+     #[link_name = "llvm.mips.sldi.d"]
+     fn msa_sldi_d(a: v2i64, b: v2i64, c: i32) -> v2i64;
+     #[link_name = "llvm.mips.sll.b"]
+     fn msa_sll_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.sll.h"]
+     fn msa_sll_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.sll.w"]
+     fn msa_sll_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.sll.d"]
+     fn msa_sll_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.slli.b"]
+     fn msa_slli_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.slli.h"]
+     fn msa_slli_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.slli.w"]
+     fn msa_slli_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.slli.d"]
+     fn msa_slli_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.splat.b"]
+     fn msa_splat_b(a: v16i8, c: i32) -> v16i8;
+     #[link_name = "llvm.mips.splat.h"]
+     fn msa_splat_h(a: v8i16, c: i32) -> v8i16;
+     #[link_name = "llvm.mips.splat.w"]
+     fn msa_splat_w(a: v4i32, w: i32) -> v4i32;
+     #[link_name = "llvm.mips.splat.d"]
+     fn msa_splat_d(a: v2i64, c: i32) -> v2i64;
+     #[link_name = "llvm.mips.splati.b"]
+     fn msa_splati_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.splati.h"]
+     fn msa_splati_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.splati.w"]
+     fn msa_splati_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.splati.d"]
+     fn msa_splati_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.sra.b"]
+     fn msa_sra_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.sra.h"]
+     fn msa_sra_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.sra.w"]
+     fn msa_sra_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.sra.d"]
+     fn msa_sra_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.srai.b"]
+     fn msa_srai_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.srai.h"]
+     fn msa_srai_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.srai.w"]
+     fn msa_srai_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.srai.d"]
+     fn msa_srai_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.srar.b"]
+     fn msa_srar_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.srar.h"]
+     fn msa_srar_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.srar.w"]
+     fn msa_srar_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.srar.d"]
+     fn msa_srar_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.srari.b"]
+     fn msa_srari_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.srari.h"]
+     fn msa_srari_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.srari.w"]
+     fn msa_srari_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.srari.d"]
+     fn msa_srari_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.srl.b"]
+     fn msa_srl_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.srl.h"]
+     fn msa_srl_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.srl.w"]
+     fn msa_srl_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.srl.d"]
+     fn msa_srl_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.srli.b"]
+     fn msa_srli_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.srli.h"]
+     fn msa_srli_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.srli.w"]
+     fn msa_srli_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.srli.d"]
+     fn msa_srli_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.srlr.b"]
+     fn msa_srlr_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.srlr.h"]
+     fn msa_srlr_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.srlr.w"]
+     fn msa_srlr_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.srlr.d"]
+     fn msa_srlr_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.srlri.b"]
+     fn msa_srlri_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.srlri.h"]
+     fn msa_srlri_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.srlri.w"]
+     fn msa_srlri_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.srlri.d"]
+     fn msa_srlri_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.st.b"]
+     fn msa_st_b(a: v16i8, mem_addr: *mut u8, imm_s10: i32) -> ();
+     #[link_name = "llvm.mips.st.h"]
+     fn msa_st_h(a: v8i16, mem_addr: *mut u8, imm_s11: i32) -> ();
+     #[link_name = "llvm.mips.st.w"]
+     fn msa_st_w(a: v4i32, mem_addr: *mut u8, imm_s12: i32) -> ();
+     #[link_name = "llvm.mips.st.d"]
+     fn msa_st_d(a: v2i64, mem_addr: *mut u8, imm_s13: i32) -> ();
+     #[link_name = "llvm.mips.subs.s.b"]
+     fn msa_subs_s_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.subs.s.h"]
+     fn msa_subs_s_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.subs.s.w"]
+     fn msa_subs_s_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.subs.s.d"]
+     fn msa_subs_s_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.subs.u.b"]
+     fn msa_subs_u_b(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.subs.u.h"]
+     fn msa_subs_u_h(a: v8u16, b: v8u16) -> v8u16;
+     #[link_name = "llvm.mips.subs.u.w"]
+     fn msa_subs_u_w(a: v4u32, b: v4u32) -> v4u32;
+     #[link_name = "llvm.mips.subs.u.d"]
+     fn msa_subs_u_d(a: v2u64, b: v2u64) -> v2u64;
+     #[link_name = "llvm.mips.subsus.u.b"]
+     fn msa_subsus_u_b(a: v16u8, b: v16i8) -> v16u8;
+     #[link_name = "llvm.mips.subsus.u.h"]
+     fn msa_subsus_u_h(a: v8u16, b: v8i16) -> v8u16;
+     #[link_name = "llvm.mips.subsus.u.w"]
+     fn msa_subsus_u_w(a: v4u32, b: v4i32) -> v4u32;
+     #[link_name = "llvm.mips.subsus.u.d"]
+     fn msa_subsus_u_d(a: v2u64, b: v2i64) -> v2u64;
+     #[link_name = "llvm.mips.subsuu.s.b"]
+     fn msa_subsuu_s_b(a: v16u8, b: v16u8) -> v16i8;
+     #[link_name = "llvm.mips.subsuu.s.h"]
+     fn msa_subsuu_s_h(a: v8u16, b: v8u16) -> v8i16;
+     #[link_name = "llvm.mips.subsuu.s.w"]
+     fn msa_subsuu_s_w(a: v4u32, b: v4u32) -> v4i32;
+     #[link_name = "llvm.mips.subsuu.s.d"]
+     fn msa_subsuu_s_d(a: v2u64, b: v2u64) -> v2i64;
+     #[link_name = "llvm.mips.subv.b"]
+     fn msa_subv_b(a: v16i8, b: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.subv.h"]
+     fn msa_subv_h(a: v8i16, b: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.subv.w"]
+     fn msa_subv_w(a: v4i32, b: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.subv.d"]
+     fn msa_subv_d(a: v2i64, b: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.subvi.b"]
+     fn msa_subvi_b(a: v16i8, b: i32) -> v16i8;
+     #[link_name = "llvm.mips.subvi.h"]
+     fn msa_subvi_h(a: v8i16, b: i32) -> v8i16;
+     #[link_name = "llvm.mips.subvi.w"]
+     fn msa_subvi_w(a: v4i32, b: i32) -> v4i32;
+     #[link_name = "llvm.mips.subvi.d"]
+     fn msa_subvi_d(a: v2i64, b: i32) -> v2i64;
+     #[link_name = "llvm.mips.vshf.b"]
+     fn msa_vshf_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8;
+     #[link_name = "llvm.mips.vshf.h"]
+     fn msa_vshf_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16;
+     #[link_name = "llvm.mips.vshf.w"]
+     fn msa_vshf_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32;
+     #[link_name = "llvm.mips.vshf.d"]
+     fn msa_vshf_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64;
+     #[link_name = "llvm.mips.xor.v"]
+     fn msa_xor_v(a: v16u8, b: v16u8) -> v16u8;
+     #[link_name = "llvm.mips.xori.b"]
+     fn msa_xori_b(a: v16u8, b: i32) -> v16u8;
+ }
+ 
+ /// Vector Add Absolute Values.
+ ///
+ /// The absolute values of the elements in vector in `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(add_a.b))]
+ pub unsafe fn __msa_add_a_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_add_a_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (eight signed 16-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(add_a.h))]
+ pub unsafe fn __msa_add_a_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_add_a_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (four signed 32-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(add_a.w))]
+ pub unsafe fn __msa_add_a_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_add_a_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (two signed 64-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(add_a.d))]
+ pub unsafe fn __msa_add_a_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_add_a_d(a, mem::transmute(b))
+ }
+ 
+ /// Signed Saturated Vector Saturated Add of Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The saturated signed result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_a.b))]
+ pub unsafe fn __msa_adds_a_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_adds_a_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Saturated Add of Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (eight signed 16-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The saturated signed result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_a.h))]
+ pub unsafe fn __msa_adds_a_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_adds_a_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Saturated Add of Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (four signed 32-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (four signed 32-bit integer numbers).
+ /// The saturated signed result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_a.w))]
+ pub unsafe fn __msa_adds_a_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_adds_a_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Saturated Add of Absolute Values
+ ///
+ /// The absolute values of the elements in vector in `a` (two signed 64-bit integer numbers)
+ /// are added to the absolute values of the elements in vector `b` (two signed 64-bit integer numbers).
+ /// The saturated signed result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_a.d))]
+ pub unsafe fn __msa_adds_a_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_adds_a_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Add of Signed Values
+ ///
+ /// The elements in vector in `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_s.b))]
+ pub unsafe fn __msa_adds_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_adds_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Add of Signed Values
+ ///
+ /// The elements in vector in `a` (eight signed 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight signed 16-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_s.h))]
+ pub unsafe fn __msa_adds_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_adds_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Add of Signed Values
+ ///
+ /// The elements in vector in `a` (four signed 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four signed 32-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_s.w))]
+ pub unsafe fn __msa_adds_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_adds_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Add of Signed Values
+ ///
+ /// The elements in vector in `a` (two signed 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two signed 64-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_s.d))]
+ pub unsafe fn __msa_adds_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_adds_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Add of Unsigned Values
+ ///
+ /// The elements in vector in `a` (sixteen unsigned 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen unsigned 8-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_u.b))]
+ pub unsafe fn __msa_adds_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_adds_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Add of Unsigned Values
+ ///
+ /// The elements in vector in `a` (eight unsigned 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight unsigned 16-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_u.h))]
+ pub unsafe fn __msa_adds_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_adds_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Add of Unsigned Values
+ ///
+ /// The elements in vector in `a` (four unsigned 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four unsigned 32-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_u.w))]
+ pub unsafe fn __msa_adds_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_adds_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Add of Unsigned Values
+ ///
+ /// The elements in vector in `a` (two unsigned 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two unsigned 64-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(adds_u.d))]
+ pub unsafe fn __msa_adds_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_adds_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add
+ ///
+ /// The elements in vector in `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addv.b))]
+ pub unsafe fn __msa_addv_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_addv_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add
+ ///
+ /// The elements in vector in `a` (eight signed 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addv.h))]
+ pub unsafe fn __msa_addv_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_addv_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add
+ ///
+ /// The elements in vector in `a` (four signed 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addv.w))]
+ pub unsafe fn __msa_addv_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_addv_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Add
+ ///
+ /// The elements in vector in `a` (two signed 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addv.d))]
+ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_addv_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Add
+ ///
+ /// The 5-bit immediate unsigned value `imm5` is added to the elements
+ /// vector in `a` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addvi.b, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_addvi_b(a: v16i8, imm5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_addvi_b(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Add
+ ///
+ /// The 5-bit immediate unsigned value `imm5` is added to the elements
+ /// vector in `a` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addvi.h, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_addvi_h(a: v8i16, imm5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_addvi_h(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Add
+ ///
+ /// The 5-bit immediate unsigned value `imm5` is added to the elements
+ /// vector in `a` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addvi.w, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_addvi_w(a: v4i32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_addvi_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Add
+ ///
+ /// The 5-bit immediate unsigned value `imm5` is added to the elements
+ /// vector in `a` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(addvi.d, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_addvi_d(a: v2i64, imm5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_addvi_d(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Logical And
+ ///
+ /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// in a bitwise logical AND operation.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(and.v))]
+ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 {
+     msa_and_v(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Logical And
+ ///
+ /// Each byte element of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the 8-bit immediate i8 (signed 8-bit integer number) in a bitwise logical AND operation.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(andi.b, imm8 = 0b10010111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_andi_b(a: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_andi_b(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Vector Absolute Values of Signed Subtract
+ ///
+ /// The signed elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are subtracted from the signed elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The absolute value of the signed result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_s.b))]
+ pub unsafe fn __msa_asub_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_asub_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Signed Subtract
+ ///
+ /// The signed elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are subtracted from the signed elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The absolute value of the signed result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_s.h))]
+ pub unsafe fn __msa_asub_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_asub_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Signed Subtract
+ ///
+ /// The signed elements in vector `a` (four signed 32-bit integer numbers)
+ /// are subtracted from the signed elements in vector `b` (four signed 32-bit integer numbers).
+ /// The absolute value of the signed result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_s.w))]
+ pub unsafe fn __msa_asub_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_asub_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Signed Subtract
+ ///
+ /// The signed elements in vector `a` (two signed 64-bit integer numbers)
+ /// are subtracted from the signed elements in vector `b` (two signed 64-bit integer numbers).
+ /// The absolute value of the signed result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_s.d))]
+ pub unsafe fn __msa_asub_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_asub_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Unsigned Subtract
+ ///
+ /// The unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `b` (sixteen unsigned 8-bit integer numbers).
+ /// The absolute value of the unsigned result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_u.b))]
+ pub unsafe fn __msa_asub_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_asub_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Unsigned Subtract
+ ///
+ /// The unsigned elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `b` (eight unsigned 16-bit integer numbers).
+ /// The absolute value of the unsigned result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_u.h))]
+ pub unsafe fn __msa_asub_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_asub_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Unsigned Subtract
+ ///
+ /// The unsigned elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `b` (four unsigned 32-bit integer numbers).
+ /// The absolute value of the unsigned result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_u.w))]
+ pub unsafe fn __msa_asub_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_asub_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Absolute Values of Unsigned Subtract
+ ///
+ /// The unsigned elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `b` (two unsigned 64-bit integer numbers).
+ /// The absolute value of the unsigned result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(asub_u.d))]
+ pub unsafe fn __msa_asub_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_asub_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The addition is done signed with full precision, i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_s.b))]
+ pub unsafe fn __msa_ave_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_ave_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The addition is done signed with full precision, i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_s.h))]
+ pub unsafe fn __msa_ave_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_ave_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four signed 32-bit integer numbers).
+ /// The addition is done signed with full precision, i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_s.w))]
+ pub unsafe fn __msa_ave_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_ave_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two signed 64-bit integer numbers).
+ /// The addition is done signed with full precision, i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_s.d))]
+ pub unsafe fn __msa_ave_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_ave_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average
+ ///
+ /// The elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen unsigned 8-bit integer numbers).
+ /// The addition is done unsigned with full precision, i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_u.b))]
+ pub unsafe fn __msa_ave_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_ave_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average
+ ///
+ /// The elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight unsigned 16-bit integer numbers).
+ /// The addition is done unsigned with full precision, i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_u.h))]
+ pub unsafe fn __msa_ave_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_ave_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average
+ ///
+ /// The elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four unsigned 32-bit integer numbers).
+ /// The addition is done unsigned with full precision, i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_u.w))]
+ pub unsafe fn __msa_ave_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_ave_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average
+ ///
+ /// The elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two unsigned 64-bit integer numbers).
+ /// The addition is done unsigned with full precision, i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ave_u.d))]
+ pub unsafe fn __msa_ave_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_ave_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average Rounded
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done signed with full precision,
+ /// i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_s.b))]
+ pub unsafe fn __msa_aver_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_aver_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average Rounded
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done signed with full precision,
+ /// i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_s.h))]
+ pub unsafe fn __msa_aver_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_aver_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average Rounded
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four signed 32-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done signed with full precision,
+ /// i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_s.w))]
+ pub unsafe fn __msa_aver_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_aver_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Average Rounded
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two signed 64-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done signed with full precision,
+ /// i.e. the result has one extra bit.
+ /// Signed division by 2 (or arithmetic shift right by one bit) is performed before
+ /// writing the result to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_s.d))]
+ pub unsafe fn __msa_aver_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_aver_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average Rounded
+ ///
+ /// The elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are added to the elements in vector `b` (sixteen unsigned 8-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done unsigned with full precision,
+ /// i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_u.b))]
+ pub unsafe fn __msa_aver_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_aver_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average Rounded
+ ///
+ /// The elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are added to the elements in vector `b` (eight unsigned 16-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done unsigned with full precision,
+ /// i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_u.h))]
+ pub unsafe fn __msa_aver_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_aver_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average Rounded
+ ///
+ /// The elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are added to the elements in vector `b` (four unsigned 32-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done unsigned with full precision,
+ /// i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_u.w))]
+ pub unsafe fn __msa_aver_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_aver_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Average Rounded
+ ///
+ /// The elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are added to the elements in vector `b` (two unsigned 64-bit integer numbers).
+ /// The addition of the elements plus 1 (for rounding) is done unsigned with full precision,
+ /// i.e. the result has one extra bit.
+ /// Unsigned division by 2 (or logical shift right by one bit) is performed before
+ /// writing the result to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(aver_u.d))]
+ pub unsafe fn __msa_aver_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_aver_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The bit position is given by the elements in `b` (sixteen unsigned 8-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclr.b))]
+ pub unsafe fn __msa_bclr_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_bclr_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (eight unsigned 16-bit integer numbers).
+ /// The bit position is given by the elements in `b` (eight unsigned 16-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclr.h))]
+ pub unsafe fn __msa_bclr_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_bclr_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (four unsigned 32-bit integer numbers).
+ /// The bit position is given by the elements in `b` (four unsigned 32-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclr.w))]
+ pub unsafe fn __msa_bclr_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_bclr_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (two unsigned 64-bit integer numbers).
+ /// The bit position is given by the elements in `b` (two unsigned 64-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclr.d))]
+ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_bclr_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The bit position is given by the immediate `m` modulo the size of the element in bits.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclri.b, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bclri_b(a: v16u8, imm3: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_bclri_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (eight unsigned 16-bit integer numbers).
+ /// The bit position is given by the immediate `m` modulo the size of the element in bits.
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclri.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bclri_h(a: v8u16, imm4: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_bclri_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (four unsigned 32-bit integer numbers).
+ /// The bit position is given by the immediate `m` modulo the size of the element in bits.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclri.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bclri_w(a: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_bclri_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Bit Clear
+ ///
+ /// Clear (set to 0) one bit in each element of vector `a` (two unsigned 64-bit integer numbers).
+ /// The bit position is given by the immediate `m` modulo the size of the element in bits.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bclri.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bclri_d(a: v2u64, imm6: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_bclri_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Vector Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (sixteen unsigned 8-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsl.b))]
+ pub unsafe fn __msa_binsl_b(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
+     msa_binsl_b(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (eight unsigned 16-bit integer numbers)
+ /// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (eight unsigned 16-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsl.h))]
+ pub unsafe fn __msa_binsl_h(a: v8u16, b: v8u16, c: v8u16) -> v8u16 {
+     msa_binsl_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (four unsigned 32-bit integer numbers)
+ /// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (four unsigned 32-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsl.w))]
+ pub unsafe fn __msa_binsl_w(a: v4u32, b: v4u32, c: v4u32) -> v4u32 {
+     msa_binsl_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (two unsigned 64-bit integer numbers)
+ /// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (two unsigned 64-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsl.d))]
+ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 {
+     msa_binsl_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Immediate Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the immediate `imm3` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsli.b, imm3 = 0b111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_binsli_b(a, mem::transmute(b), $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (eight unsigned 16-bit integer numbers)
+ /// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the immediate `imm4` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsli.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_binsli_h(a, mem::transmute(b), $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (four unsigned 32-bit integer numbers)
+ /// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the immediate `imm5` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsli.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_binsli_w(a, mem::transmute(b), $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Bit Insert Left
+ ///
+ /// Copy most significant (left) bits in each element of vector `b` (two unsigned 64-bit integer numbers)
+ /// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (right) bits.
+ /// The number of bits to copy is given by the immediate `imm6` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsli.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64, imm6: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_binsli_d(a, mem::transmute(b), $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Vector Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (sixteen unsigned 8-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsr.b))]
+ pub unsafe fn __msa_binsr_b(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
+     msa_binsr_b(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (eight unsigned 16-bit integer numbers)
+ /// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (eight unsigned 16-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsr.h))]
+ pub unsafe fn __msa_binsr_h(a: v8u16, b: v8u16, c: v8u16) -> v8u16 {
+     msa_binsr_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (four unsigned 32-bit integer numbers)
+ /// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (four unsigned 32-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsr.w))]
+ pub unsafe fn __msa_binsr_w(a: v4u32, b: v4u32, c: v4u32) -> v4u32 {
+     msa_binsr_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (two unsigned 64-bit integer numbers)
+ /// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the elements in vector `c` (two unsigned 64-bit integer numbers)
+ /// modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsr.d))]
+ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 {
+     msa_binsr_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Immediate Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the immediate `imm3` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsri.b, imm3 = 0b111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_binsri_b(a, mem::transmute(b), $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (eight unsigned 16-bit integer numbers)
+ /// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the immediate `imm4` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsri.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_binsri_h(a, mem::transmute(b), $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (four unsigned 32-bit integer numbers)
+ /// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the immediate `imm5` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsri.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_binsri_w(a, mem::transmute(b), $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Bit Insert Right
+ ///
+ /// Copy most significant (right) bits in each element of vector `b` (two unsigned 64-bit integer numbers)
+ /// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (left) bits.
+ /// The number of bits to copy is given by the immediate `imm6` modulo the size of the element in bits plus 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(binsri.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64, imm6: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_binsri_d(a, mem::transmute(b), $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Vector Bit Move If Not Zero
+ ///
+ /// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector
+ /// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from target vector `c`
+ /// (sixteen unsigned 8-bit integer numbers) are 1 and leaves unchanged all destination bits
+ /// for which the corresponding target bits are 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bmnz.v))]
+ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
+     msa_bmnz_v(a, mem::transmute(b), c)
+ }
+ 
+ /// Immediate Bit Move If Not Zero
+ ///
+ /// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector
+ /// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from from immediate `imm8`
+ /// are 1 and leaves unchanged all destination bits for which the corresponding target bits are 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bmnzi.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_bmnzi_b(a, mem::transmute(b), $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Vector Bit Move If Zero
+ ///
+ /// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector
+ /// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from target vector `c`
+ /// (sixteen unsigned 8-bit integer numbers) are 0 and leaves unchanged all destination bits
+ /// for which the corresponding target bits are 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bmz.v))]
+ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
+     msa_bmz_v(a, mem::transmute(b), c)
+ }
+ 
+ /// Immediate Bit Move If Zero
+ ///
+ /// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector
+ /// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from from immediate `imm8`
+ /// are 0 and leaves unchanged all destination bits for which the corresponding immediate bits are 1.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bmzi.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_bmzi_b(a, mem::transmute(b), $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Vector Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bneg.b))]
+ pub unsafe fn __msa_bneg_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_bneg_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (eight unsigned 16-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bneg.h))]
+ pub unsafe fn __msa_bneg_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_bneg_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (four unsigned 32-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bneg.w))]
+ pub unsafe fn __msa_bneg_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_bneg_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (two unsigned 64-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (two unsigned 64-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bneg.d))]
+ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_bneg_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The bit position is given by immediate `imm3` modulo the size of the element in bits.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnegi.b, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bnegi_b(a: v16u8, imm3: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_bnegi_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (eight unsigned 16-bit integer numbers).
+ /// The bit position is given by immediate `imm4` modulo the size of the element in bits.
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnegi.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bnegi_h(a: v8u16, imm4: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_bnegi_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (four unsigned 32-bit integer numbers).
+ /// The bit position is given by immediate `imm5` modulo the size of the element in bits.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnegi.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bnegi_w(a: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_bnegi_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Bit Negate
+ ///
+ /// Negate (complement) one bit in each element of vector `a` (two unsigned 64-bit integer numbers).
+ /// The bit position is given by immediate `imm6` modulo the size of the element in bits.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnegi.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bnegi_d(a: v2u64, imm6: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_bnegi_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Immediate Branch If All Elements Are Not Zero
+ ///
+ /// PC-relative branch if all elements in `a` (sixteen unsigned 8-bit integer numbers) are not zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnz.b))]
+ pub unsafe fn __msa_bnz_b(a: v16u8) -> i32 {
+     msa_bnz_b(a)
+ }
+ 
+ /// Immediate Branch If All Elements Are Not Zero
+ ///
+ /// PC-relative branch if all elements in `a` (eight unsigned 16-bit integer numbers) are not zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnz.h))]
+ pub unsafe fn __msa_bnz_h(a: v8u16) -> i32 {
+     msa_bnz_h(a)
+ }
+ 
+ /// Immediate Branch If All Elements Are Not Zero
+ ///
+ /// PC-relative branch if all elements in `a` (four unsigned 32-bit integer numbers) are not zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnz.w))]
+ pub unsafe fn __msa_bnz_w(a: v4u32) -> i32 {
+     msa_bnz_w(a)
+ }
+ 
+ /// Immediate Branch If All Elements Are Not Zero
+ ///
+ /// PC-relative branch if all elements in `a` (two unsigned 64-bit integer numbers) are not zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnz.d))]
+ pub unsafe fn __msa_bnz_d(a: v2u64) -> i32 {
+     msa_bnz_d(a)
+ }
+ 
+ /// Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero)
+ ///
+ /// PC-relative branch if at least one bit in `a` (four unsigned 32-bit integer numbers) are not zero.
+ /// i.e at least one element is not zero regardless of the data format.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bnz.v))]
+ pub unsafe fn __msa_bnz_v(a: v16u8) -> i32 {
+     msa_bnz_v(a)
+ }
+ 
+ /// Vector Bit Select
+ ///
+ /// Selectively copy bits from the source vectors `b` (eight unsigned 16-bit integer numbers)
+ /// and `c` (eight unsigned 16-bit integer numbers)
+ /// into destination vector `a` (eight unsigned 16-bit integer numbers) based on the corresponding bit in `a`:
+ /// if 0 copies the bit from `b`, if 1 copies the bit from `c`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bsel.v))]
+ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
+     msa_bsel_v(a, mem::transmute(b), c)
+ }
+ 
+ /// Immediate Bit Select
+ ///
+ /// Selectively copy bits from the 8-bit immediate `imm8` and `c` (eight unsigned 16-bit integer numbers)
+ /// into destination vector `a` (eight unsigned 16-bit integer numbers) based on the corresponding bit in `a`:
+ /// if 0 copies the bit from `b`, if 1 copies the bit from `c`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bseli.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_bseli_b(a, mem::transmute(b), $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Vector Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bset.b))]
+ pub unsafe fn __msa_bset_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_bset_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (eight unsigned 16-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bset.h))]
+ pub unsafe fn __msa_bset_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_bset_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (four unsigned 32-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bset.w))]
+ pub unsafe fn __msa_bset_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_bset_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (two unsigned 64-bit integer numbers).
+ /// The bit position is given by the elements in vector `b` (two unsigned 64-bit integer numbers)
+ /// modulo the size of the element in bits.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bset.d))]
+ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_bset_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The bit position is given by immediate `imm3`.
+ /// The result is written to vector `a` (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bseti.b, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bseti_b(a: v16u8, imm3: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_bseti_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (eight unsigned 16-bit integer numbers).
+ /// The bit position is given by immediate `imm4`.
+ /// The result is written to vector `a` (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bseti.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bseti_h(a: v8u16, imm4: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_bseti_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (four unsigned 32-bit integer numbers).
+ /// The bit position is given by immediate `imm5`.
+ /// The result is written to vector `a` (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bseti.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bseti_w(a: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_bseti_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Bit Set
+ ///
+ /// Set to 1 one bit in each element of vector `a` (two unsigned 64-bit integer numbers).
+ /// The bit position is given by immediate `imm6`.
+ /// The result is written to vector `a` (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bseti.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_bseti_d(a: v2u64, imm6: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_bseti_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Immediate Branch If At Least One Element Is Zero
+ ///
+ /// PC-relative branch if at least one element in `a` (sixteen unsigned 8-bit integer numbers) is zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bz.b))]
+ pub unsafe fn __msa_bz_b(a: v16u8) -> i32 {
+     msa_bz_b(a)
+ }
+ 
+ /// Immediate Branch If At Least One Element Is Zero
+ ///
+ /// PC-relative branch if at least one element in `a` (eight unsigned 16-bit integer numbers) is zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bz.h))]
+ pub unsafe fn __msa_bz_h(a: v8u16) -> i32 {
+     msa_bz_h(a)
+ }
+ 
+ /// Immediate Branch If At Least One Element Is Zero
+ ///
+ /// PC-relative branch if at least one element in `a` (four unsigned 32-bit integer numbers) is zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bz.w))]
+ pub unsafe fn __msa_bz_w(a: v4u32) -> i32 {
+     msa_bz_w(a)
+ }
+ 
+ /// Immediate Branch If At Least One Element Is Zero
+ ///
+ /// PC-relative branch if at least one element in `a` (two unsigned 64-bit integer numbers) is zero.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bz.d))]
+ pub unsafe fn __msa_bz_d(a: v2u64) -> i32 {
+     msa_bz_d(a)
+ }
+ 
+ /// Immediate Branch If Zero (All Elements of Any Format Are Zero)
+ ///
+ /// PC-relative branch if all elements in `a` (sixteen unsigned 8-bit integer numbers) bits are zero,
+ /// i.e. all elements are zero regardless of the data format.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(bz.v))]
+ pub unsafe fn __msa_bz_v(a: v16u8) -> i32 {
+     msa_bz_v(a)
+ }
+ 
+ /// Vector Compare Equal
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen signed 8-bit integer numbers) and `b` (sixteen signed 8-bit integer numbers)
+ /// elements are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceq.b))]
+ pub unsafe fn __msa_ceq_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_ceq_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Equal
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight signed 16-bit integer numbers) and `b` (eight signed 16-bit integer numbers)
+ /// elements are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceq.h))]
+ pub unsafe fn __msa_ceq_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_ceq_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four signed 32-bit integer numbers) and `b` (four signed 32-bit integer numbers)
+ /// elements are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceq.w))]
+ pub unsafe fn __msa_ceq_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_ceq_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two signed 64-bit integer numbers) and `b` (two signed 64-bit integer numbers)
+ /// elements are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceq.d))]
+ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_ceq_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Compare Equal
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen signed 8-bit integer numbers) the 5-bit signed immediate imm_s5
+ /// are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceqi.b, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ceqi_b(a: v16i8, imm_s5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_ceqi_b(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Equal
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight signed 16-bit integer numbers) the 5-bit signed immediate imm_s5
+ /// are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceqi.h, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ceqi_h(a: v8i16, imm_s5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_ceqi_h(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four signed 32-bit integer numbers) the 5-bit signed immediate imm_s5
+ /// are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceqi.w, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ceqi_w(a: v4i32, imm_s5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_ceqi_w(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two signed 64-bit integer numbers) the 5-bit signed immediate imm_s5
+ /// are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ceqi.d, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ceqi_d(a: v2i64, imm_s5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_ceqi_d(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// GPR Copy from MSA Control Register
+ ///
+ /// The sign extended content of MSA control register cs is copied to GPR rd.
+ ///
+ /// Can not be tested in user mode
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cfcmsa, imm5 = 0b11111))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __msa_cfcmsa(imm5: i32) -> i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_cfcmsa($imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen signed 8-bit integer numbers) element
+ /// are signed less than or equal to `b` (sixteen signed 8-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_s.b))]
+ pub unsafe fn __msa_cle_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_cle_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight signed 16-bit integer numbers) element
+ /// are signed less than or equal to `b` (eight signed 16-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_s.h))]
+ pub unsafe fn __msa_cle_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_cle_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four signed 32-bit integer numbers) element
+ /// are signed less than or equal to `b` (four signed 32-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_s.w))]
+ pub unsafe fn __msa_cle_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_cle_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two signed 64-bit integer numbers) element
+ /// are signed less than or equal to `b` (two signed 64-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_s.d))]
+ pub unsafe fn __msa_cle_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_cle_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element
+ /// are unsigned less than or equal to `b` (sixteen unsigned 8-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_u.b))]
+ pub unsafe fn __msa_cle_u_b(a: v16u8, b: v16u8) -> v16i8 {
+     msa_cle_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight unsigned 16-bit integer numbers) element
+ /// are unsigned less than or equal to `b` (eight unsigned 16-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_u.h))]
+ pub unsafe fn __msa_cle_u_h(a: v8u16, b: v8u16) -> v8i16 {
+     msa_cle_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four unsigned 32-bit integer numbers) element
+ /// are unsigned less than or equal to `b` (four unsigned 32-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_u.w))]
+ pub unsafe fn __msa_cle_u_w(a: v4u32, b: v4u32) -> v4i32 {
+     msa_cle_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two unsigned 64-bit integer numbers) element
+ /// are unsigned less than or equal to `b` (two unsigned 64-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(cle_u.d))]
+ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 {
+     msa_cle_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen signed 8-bit integer numbers) element
+ /// is less than or equal to the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_s.b, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clei_s_b(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight signed 16-bit integer numbers) element
+ /// is less than or equal to the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_s.h, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clei_s_h(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four signed 32-bit integer numbers) element
+ /// is less than or equal to the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_s.w, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clei_s_w(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Signed Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two signed 64-bit integer numbers) element
+ /// is less than or equal to the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_s.d, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clei_s_d(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element
+ /// is unsigned less than or equal to the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_u.b, imm5 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_u_b(a: v16u8, imm5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clei_u_b(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight unsigned 16-bit integer numbers) element
+ /// is unsigned less than or equal to the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_u.h, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_u_h(a: v8u16, imm5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clei_u_h(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four unsigned 32-bit integer numbers) element
+ /// is unsigned less than or equal to the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_u.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_u_w(a: v4u32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clei_u_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two unsigned 64-bit integer numbers) element
+ /// is unsigned less than or equal to the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clei_u.d, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clei_u_d(a: v2u64, imm5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clei_u_d(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen signed 8-bit integer numbers) element
+ /// are signed less than `b` (sixteen signed 8-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_s.b))]
+ pub unsafe fn __msa_clt_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_clt_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight signed 16-bit integer numbers) element
+ /// are signed less than `b` (eight signed 16-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_s.h))]
+ pub unsafe fn __msa_clt_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_clt_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four signed 32-bit integer numbers) element
+ /// are signed less than `b` (four signed 32-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_s.w))]
+ pub unsafe fn __msa_clt_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_clt_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two signed 64-bit integer numbers) element
+ /// are signed less than `b` (two signed 64-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_s.d))]
+ pub unsafe fn __msa_clt_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_clt_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element
+ /// are unsigned less than `b` (sixteen unsigned 8-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_u.b))]
+ pub unsafe fn __msa_clt_u_b(a: v16u8, b: v16u8) -> v16i8 {
+     msa_clt_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight unsigned 16-bit integer numbers) element
+ /// are unsigned less than `b` (eight unsigned 16-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_u.h))]
+ pub unsafe fn __msa_clt_u_h(a: v8u16, b: v8u16) -> v8i16 {
+     msa_clt_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four unsigned 32-bit integer numbers) element
+ /// are unsigned less than `b` (four unsigned 32-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_u.w))]
+ pub unsafe fn __msa_clt_u_w(a: v4u32, b: v4u32) -> v4i32 {
+     msa_clt_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two unsigned 64-bit integer numbers) element
+ /// are unsigned less than `b` (two unsigned 64-bit integer numbers) element.
+ /// Otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clt_u.d))]
+ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 {
+     msa_clt_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen signed 8-bit integer numbers) element
+ /// is less than the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_s.b, imm_s5 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clti_s_b(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight signed 16-bit integer numbers) element
+ /// is less than the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_s.h, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clti_s_h(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four signed 32-bit integer numbers) element
+ /// is less than the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_s.w, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clti_s_w(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Signed Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two signed 64-bit integer numbers) element
+ /// is less than the 5-bit signed immediate imm_s5,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_s.d, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_clti_s_d(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements
+ /// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element
+ /// is unsigned less than the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_u.b, imm5 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_u_b(a: v16u8, imm5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clti_u_b(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements
+ /// if the corresponding `a` (eight unsigned 16-bit integer numbers) element
+ /// is unsigned less than the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_u.h, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_u_h(a: v8u16, imm5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clti_u_h(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four unsigned 32-bit integer numbers) element
+ /// is unsigned less than the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_u.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_u_w(a: v4u32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clti_u_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Compare Unsigned Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two unsigned 64-bit integer numbers) element
+ /// is unsigned less than the 5-bit unsigned immediate `imm5`,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(clti_u.d, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_clti_u_d(a: v2u64, imm5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_clti_u_d(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Element Copy to GPR Signed
+ ///
+ /// Sign-extend element `imm4` of vector `a` (sixteen signed 8-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_s.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_s_b(a: v16i8, imm4: i32) -> i32 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_copy_s_b(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Element Copy to GPR Signed
+ ///
+ /// Sign-extend element `imm3` of vector `a` (eight signed 16-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_s.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_s_h(a: v8i16, imm3: i32) -> i32 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_copy_s_h(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Element Copy to GPR Signed
+ ///
+ /// Sign-extend element `imm2` of vector `a` (four signed 32-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_s.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_s_w(a: v4i32, imm2: i32) -> i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_copy_s_w(a, $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Element Copy to GPR Signed
+ ///
+ /// Sign-extend element `imm1` of vector `a` (two signed 64-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_s.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_s_d(a: v2i64, imm1: i32) -> i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_copy_s_d(a, $imm1)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// Element Copy to GPR Unsigned
+ ///
+ /// Zero-extend element `imm4` of vector `a` (sixteen signed 8-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_u.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_u_b(a: v16i8, imm4: i32) -> u32 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_copy_u_b(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Element Copy to GPR Unsigned
+ ///
+ /// Zero-extend element `imm3` of vector `a` (eight signed 16-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_u.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_u_h(a: v8i16, imm3: i32) -> u32 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_copy_u_h(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Element Copy to GPR Unsigned
+ ///
+ /// Zero-extend element `imm2` of vector `a` (four signed 32-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_u.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_u_w(a: v4i32, imm2: i32) -> u32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_copy_u_w(a, $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Element Copy to GPR Unsigned
+ ///
+ /// Zero-extend element `imm1` of vector `a` (two signed 64-bit integer numbers)
+ /// and copy the result to GPR rd.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(copy_u.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_copy_u_d(a: v2i64, imm1: i32) -> u64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_copy_u_d(a, $imm1)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// GPR Copy to MSA Control Register
+ ///
+ /// The content of the least significant 31 bits of GPR `imm1` is copied to
+ /// MSA control register cd.
+ ///
+ /// Can not be tested in user mode
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ctcmsa, imm1 = 0b1))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __msa_ctcmsa(imm5: i32, a: i32) -> () {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_ctcmsa($imm5, a)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Signed Divide
+ ///
+ /// The signed integer elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_s.b))]
+ pub unsafe fn __msa_div_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_div_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Divide
+ ///
+ /// The signed integer elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_s.h))]
+ pub unsafe fn __msa_div_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_div_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Divide
+ ///
+ /// The signed integer elements in vector `a` (four signed 32-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_s.w))]
+ pub unsafe fn __msa_div_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_div_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Divide
+ ///
+ /// The signed integer elements in vector `a` (two signed 64-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_s.d))]
+ pub unsafe fn __msa_div_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_div_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Divide
+ ///
+ /// The unsigned integer elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers).
+ /// The result is written to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_u.b))]
+ pub unsafe fn __msa_div_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_div_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Divide
+ ///
+ /// The unsigned integer elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers).
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_u.h))]
+ pub unsafe fn __msa_div_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_div_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Divide
+ ///
+ /// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers).
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_u.w))]
+ pub unsafe fn __msa_div_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_div_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Divide
+ ///
+ /// The unsigned integer elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (two unsigned 64-bit integer numbers).
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(div_u.d))]
+ pub unsafe fn __msa_div_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_div_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Dot Product
+ ///
+ /// The signed integer elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// producing a result the size of the input operands. The multiplication results of
+ /// adjacent odd/even elements are added and stored to the destination
+ /// vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dotp_s.h))]
+ pub unsafe fn __msa_dotp_s_h(a: v16i8, b: v16i8) -> v8i16 {
+     msa_dotp_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Dot Product
+ ///
+ /// The signed integer elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `b` (eight signed 16-bit integer numbers)
+ /// producing a result the size of the input operands. The multiplication results of
+ /// adjacent odd/even elements are added and stored to the destination
+ /// vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dotp_s.w))]
+ pub unsafe fn __msa_dotp_s_w(a: v8i16, b: v8i16) -> v4i32 {
+     msa_dotp_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Dot Product
+ ///
+ /// The signed integer elements in vector `a` (four signed 32-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `b` (four signed 32-bit integer numbers)
+ /// producing a result the size of the input operands. The multiplication results of
+ /// adjacent odd/even elements are added and stored to the destination
+ /// vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dotp_s.d))]
+ pub unsafe fn __msa_dotp_s_d(a: v4i32, b: v4i32) -> v2i64 {
+     msa_dotp_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Dot Product
+ ///
+ /// The unsigned integer elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// producing a result the size of the input operands. The multiplication results of
+ /// adjacent odd/even elements are added and stored to the destination
+ /// vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dotp_u.h))]
+ pub unsafe fn __msa_dotp_u_h(a: v16u8, b: v16u8) -> v8u16 {
+     msa_dotp_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Dot Product
+ ///
+ /// The unsigned integer elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// producing a result the size of the input operands. The multiplication results of
+ /// adjacent odd/even elements are added and stored to the destination
+ /// vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dotp_u.w))]
+ pub unsafe fn __msa_dotp_u_w(a: v8u16, b: v8u16) -> v4u32 {
+     msa_dotp_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Dot Product
+ ///
+ /// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// producing a result the size of the input operands. The multiplication results of
+ /// adjacent odd/even elements are added and stored to the destination
+ /// vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dotp_u.d))]
+ pub unsafe fn __msa_dotp_u_d(a: v4u32, b: v4u32) -> v2u64 {
+     msa_dotp_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Dot Product and Add
+ ///
+ /// The signed integer elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `c` (sixteen signed 8-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are added to the vector `a` (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpadd_s.h))]
+ pub unsafe fn __msa_dpadd_s_h(a: v8i16, b: v16i8, c: v16i8) -> v8i16 {
+     msa_dpadd_s_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Signed Dot Product and Add
+ ///
+ /// The signed integer elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `c` (eight signed 16-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are added to the vector `a` (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpadd_s.w))]
+ pub unsafe fn __msa_dpadd_s_w(a: v4i32, b: v8i16, c: v8i16) -> v4i32 {
+     msa_dpadd_s_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Signed Dot Product and Add
+ ///
+ /// The signed integer elements in vector `b` (four signed 32-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `c` (four signed 32-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are added to the vector `a` (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpadd_s.d))]
+ pub unsafe fn __msa_dpadd_s_d(a: v2i64, b: v4i32, c: v4i32) -> v2i64 {
+     msa_dpadd_s_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Unsigned Dot Product and Add
+ ///
+ /// The unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `c` (sixteen unsigned 8-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are added to the vector `a` (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpadd_u.h))]
+ pub unsafe fn __msa_dpadd_u_h(a: v8u16, b: v16u8, c: v16u8) -> v8u16 {
+     msa_dpadd_u_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Unsigned Dot Product and Add
+ ///
+ /// The unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `c` (eight unsigned 16-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are added to the vector `a` (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpadd_u.w))]
+ pub unsafe fn __msa_dpadd_u_w(a: v4u32, b: v8u16, c: v8u16) -> v4u32 {
+     msa_dpadd_u_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Unsigned Dot Product and Add
+ ///
+ /// The unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `c` (four unsigned 32-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are added to the vector `a` (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpadd_u.d))]
+ pub unsafe fn __msa_dpadd_u_d(a: v2u64, b: v4u32, c: v4u32) -> v2u64 {
+     msa_dpadd_u_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Signed Dot Product and Add
+ ///
+ /// The signed integer elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `c` (sixteen signed 8-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are subtracted from the integer elements in vector `a`
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpsub_s.h))]
+ pub unsafe fn __msa_dpsub_s_h(a: v8i16, b: v16i8, c: v16i8) -> v8i16 {
+     msa_dpsub_s_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Signed Dot Product and Add
+ ///
+ /// The signed integer elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `c` (eight signed 16-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are subtracted from the integer elements in vector `a`
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpsub_s.w))]
+ pub unsafe fn __msa_dpsub_s_w(a: v4i32, b: v8i16, c: v8i16) -> v4i32 {
+     msa_dpsub_s_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Signed Dot Product and Add
+ ///
+ /// The signed integer elements in vector `b` (four signed 32-bit integer numbers)
+ /// are multiplied by signed integer elements in vector `c` (four signed 32-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are subtracted from the integer elements in vector `a`
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpsub_s.d))]
+ pub unsafe fn __msa_dpsub_s_d(a: v2i64, b: v4i32, c: v4i32) -> v2i64 {
+     msa_dpsub_s_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Unsigned Dot Product and Add
+ ///
+ /// The unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `c` (sixteen unsigned 8-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are subtracted from the integer elements in vector `a`
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpsub_u.h))]
+ pub unsafe fn __msa_dpsub_u_h(a: v8i16, b: v16u8, c: v16u8) -> v8i16 {
+     msa_dpsub_u_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Unsigned Dot Product and Add
+ ///
+ /// The unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `c` (eight unsigned 16-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are subtracted from the integer elements in vector `a`
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpsub_u.w))]
+ pub unsafe fn __msa_dpsub_u_w(a: v4i32, b: v8u16, c: v8u16) -> v4i32 {
+     msa_dpsub_u_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Unsigned Dot Product and Add
+ ///
+ /// The unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// are multiplied by unsigned integer elements in vector `c` (four unsigned 32-bit integer numbers)
+ /// producing a result twice the size of the input operands. The multiplication results
+ /// of adjacent odd/even elements are subtracted from the integer elements in vector `a`
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(dpsub_u.d))]
+ pub unsafe fn __msa_dpsub_u_d(a: v2i64, b: v4u32, c: v4u32) -> v2i64 {
+     msa_dpsub_u_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Floating-Point Addition
+ ///
+ /// The floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are added to the floating-point elements in `bc` (four 32-bit floating point numbers).
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fadd.w))]
+ pub unsafe fn __msa_fadd_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fadd_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Addition
+ ///
+ /// The floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// are added to the floating-point elements in `bc` (two 64-bit floating point numbers).
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fadd.d))]
+ pub unsafe fn __msa_fadd_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fadd_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Always False
+ ///
+ /// Set all bits to 0 in vector (four signed 32-bit integer numbers).
+ /// Signaling NaN elements in `a` (four 32-bit floating point numbers)
+ /// or `b` (four 32-bit floating point numbers) signal Invalid Operation exception.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcaf.w))]
+ pub unsafe fn __msa_fcaf_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcaf_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Always False
+ ///
+ /// Set all bits to 0 in vector (two signed 64-bit integer numbers).
+ /// Signaling NaN elements in `a` (two 64-bit floating point numbers)
+ /// or `b` (two 64-bit floating point numbers) signal Invalid Operation exception.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcaf.d))]
+ pub unsafe fn __msa_fcaf_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcaf_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding in `a` (four 32-bit floating point numbers)
+ /// and `b` (four 32-bit floating point numbers) elements are ordered and equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fceq.w))]
+ pub unsafe fn __msa_fceq_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fceq_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding in `a` (two 64-bit floating point numbers)
+ /// and `b` (two 64-bit floating point numbers) elements are ordered and equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fceq.d))]
+ pub unsafe fn __msa_fceq_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fceq_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Class Mask
+ ///
+ /// Store in each element of vector (four signed 32-bit integer numbers)
+ /// a bit mask reflecting the floating-point class of the corresponding element of vector
+ /// `a` (four 32-bit floating point numbers).
+ /// The mask has 10 bits as follows. Bits 0 and 1 indicate NaN values: signaling NaN (bit 0) and quiet NaN (bit 1).
+ /// Bits 2, 3, 4, 5 classify negative values: infinity (bit 2), normal (bit 3), subnormal (bit 4), and zero (bit 5).
+ /// Bits 6, 7, 8, 9 classify positive values: infinity (bit 6), normal (bit 7), subnormal (bit 8), and zero (bit 9).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fclass.w))]
+ pub unsafe fn __msa_fclass_w(a: v4f32) -> v4i32 {
+     msa_fclass_w(a)
+ }
+ 
+ /// Vector Floating-Point Class Mask
+ ///
+ /// Store in each element of vector (two signed 64-bit integer numbers)
+ /// a bit mask reflecting the floating-point class of the corresponding element of vector
+ /// `a` (two 64-bit floating point numbers).
+ /// The mask has 10 bits as follows. Bits 0 and 1 indicate NaN values: signaling NaN (bit 0) and quiet NaN (bit 1).
+ /// Bits 2, 3, 4, 5 classify negative values: infinity (bit 2), normal (bit 3), subnormal (bit 4), and zero (bit 5).
+ /// Bits 6, 7, 8, 9 classify positive values: infinity (bit 6), normal (bit 7), subnormal (bit 8), and zero (bit 9).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fclass.d))]
+ pub unsafe fn __msa_fclass_d(a: v2f64) -> v2i64 {
+     msa_fclass_d(a)
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Less or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers) elements are ordered
+ /// and either less than or equal to `b` (four 32-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcle.w))]
+ pub unsafe fn __msa_fcle_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcle_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Less or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers) elements are ordered
+ /// and either less than or equal to `b` (two 64-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcle.d))]
+ pub unsafe fn __msa_fcle_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcle_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers) elements are ordered
+ /// and less than `b` (four 32-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fclt.w))]
+ pub unsafe fn __msa_fclt_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fclt_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers) elements are ordered
+ /// and less than `b` (two 64-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fclt.d))]
+ pub unsafe fn __msa_fclt_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fclt_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Not Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are ordered and not equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcne.w))]
+ pub unsafe fn __msa_fcne_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcne_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Not Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are ordered and not equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcne.d))]
+ pub unsafe fn __msa_fcne_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcne_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Ordered
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are ordered, i.e. both elements are not NaN values,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcor.w))]
+ pub unsafe fn __msa_fcor_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcor_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Ordered
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are ordered, i.e. both elements are not NaN values,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcor.d))]
+ pub unsafe fn __msa_fcor_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcor_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are unordered or equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcueq.w))]
+ pub unsafe fn __msa_fcueq_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcueq_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are unordered or equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcueq.d))]
+ pub unsafe fn __msa_fcueq_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcueq_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Less or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding elements in `a` (four 32-bit floating point numbers)
+ /// are unordered or less than or equal to `b` (four 32-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcule.w))]
+ pub unsafe fn __msa_fcule_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcule_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Less or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding elements in `a` (two 64-bit floating point numbers)
+ /// are unordered or less than or equal to `b` (two 64-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcule.d))]
+ pub unsafe fn __msa_fcule_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcule_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding elements in `a` (four 32-bit floating point numbers)
+ /// are unordered or less than `b` (four 32-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcult.w))]
+ pub unsafe fn __msa_fcult_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcult_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding elements in `a` (two 64-bit floating point numbers)
+ /// are unordered or less than `b` (two 64-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcult.d))]
+ pub unsafe fn __msa_fcult_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcult_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers)
+ /// and `b` (four 32-bit floating point numbers) elements are unordered,
+ /// i.e. at least one element is a NaN value, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcun.w))]
+ pub unsafe fn __msa_fcun_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcun_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers)
+ /// and `b` (two 64-bit floating point numbers) elements are unordered,
+ /// i.e. at least one element is a NaN value, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcun.d))]
+ pub unsafe fn __msa_fcun_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcun_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Not Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers)
+ /// elements if the corresponding `a` (four 32-bit floating point numbers)
+ /// and `b` (four 32-bit floating point numbers) elements are unordered or not equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcune.w))]
+ pub unsafe fn __msa_fcune_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fcune_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Quiet Compare Unordered or Not Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers)
+ /// elements if the corresponding `a` (two 64-bit floating point numbers)
+ /// and `b` (two 64-bit floating point numbers) elements are unordered or not equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fcune.d))]
+ pub unsafe fn __msa_fcune_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fcune_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Division
+ ///
+ /// The floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are divided by the floating-point elements in vector `b` (four 32-bit floating point numbers).
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fdiv.w))]
+ pub unsafe fn __msa_fdiv_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fdiv_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Division
+ ///
+ /// The floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// are divided by the floating-point elements in vector `b` (two 64-bit floating point numbers).
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fdiv.d))]
+ pub unsafe fn __msa_fdiv_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fdiv_d(a, mem::transmute(b))
+ }
+ 
+ /* FIXME: 16-bit float
+ /// Vector Floating-Point Down-Convert Interchange Format
+ ///
+ /// The floating-point elements in vector `a` (four 64-bit floating point numbers)
+ /// and vector `b` (four 64-bit floating point numbers) are down-converted
+ /// to a smaller interchange format, i.e. from 64-bit to 32-bit, or from 32-bit to 16-bit.
+ /// The result is written to vector (8 16-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexdo.h))]
+ pub unsafe fn __msa_fexdo_h(a: v4f32, b: v4f32) -> f16x8 {
+     msa_fexdo_h(a, mem::transmute(b))
+ }*/
+ 
+ /// Vector Floating-Point Down-Convert Interchange Format
+ ///
+ /// The floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// and vector `b` (two 64-bit floating point numbers) are down-converted
+ /// to a smaller interchange format, i.e. from 64-bit to 32-bit, or from 32-bit to 16-bit.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexdo.w))]
+ pub unsafe fn __msa_fexdo_w(a: v2f64, b: v2f64) -> v4f32 {
+     msa_fexdo_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Down-Convert Interchange Format
+ ///
+ /// The floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are scaled, i.e. multiplied, by 2 to the power of integer elements in vector `b`
+ /// (four signed 32-bit integer numbers).
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexp2.w))]
+ pub unsafe fn __msa_fexp2_w(a: v4f32, b: v4i32) -> v4f32 {
+     msa_fexp2_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Down-Convert Interchange Format
+ ///
+ /// The floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// are scaled, i.e. multiplied, by 2 to the power of integer elements in vector `b`
+ /// (two signed 64-bit integer numbers).
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexp2.d))]
+ pub unsafe fn __msa_fexp2_d(a: v2f64, b: v2i64) -> v2f64 {
+     msa_fexp2_d(a, mem::transmute(b))
+ }
+ 
+ /* FIXME: 16-bit float
+ /// Vector Floating-Point Up-Convert Interchange Format Left
+ ///
+ /// The left half floating-point elements in vector `a` (two 16-bit floating point numbers)
+ /// are up-converted to a larger interchange format,
+ /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexupl.w))]
+ pub unsafe fn __msa_fexupl_w(a: f16x8) -> v4f32 {
+     msa_fexupl_w(a)
+ }*/
+ 
+ /// Vector Floating-Point Up-Convert Interchange Format Left
+ ///
+ /// The left half floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are up-converted to a larger interchange format,
+ /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit.
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexupl.d))]
+ pub unsafe fn __msa_fexupl_d(a: v4f32) -> v2f64 {
+     msa_fexupl_d(a)
+ }
+ 
+ /* FIXME: 16-bit float
+ /// Vector Floating-Point Up-Convert Interchange Format Left
+ ///
+ /// The right half floating-point elements in vector `a` (two 16-bit floating point numbers)
+ /// are up-converted to a larger interchange format,
+ /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexupr.w))]
+ pub unsafe fn __msa_fexupr_w(a: f16x8) -> v4f32 {
+     msa_fexupr_w(a)
+ } */
+ 
+ /// Vector Floating-Point Up-Convert Interchange Format Left
+ ///
+ /// The right half floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are up-converted to a larger interchange format,
+ /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit.
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fexupr.d))]
+ pub unsafe fn __msa_fexupr_d(a: v4f32) -> v2f64 {
+     msa_fexupr_d(a)
+ }
+ 
+ /// Vector Floating-Point Round and Convert from Signed Integer
+ ///
+ /// The signed integer elements in vector `a` (four signed 32-bit integer numbers)
+ /// are converted to floating-point values.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffint_s.w))]
+ pub unsafe fn __msa_ffint_s_w(a: v4i32) -> v4f32 {
+     msa_ffint_s_w(a)
+ }
+ 
+ /// Vector Floating-Point Round and Convert from Signed Integer
+ ///
+ /// The signed integer elements in vector `a` (two signed 64-bit integer numbers)
+ /// are converted to floating-point values.
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffint_s.d))]
+ pub unsafe fn __msa_ffint_s_d(a: v2i64) -> v2f64 {
+     msa_ffint_s_d(a)
+ }
+ 
+ /// Vector Floating-Point Round and Convert from Unsigned Integer
+ ///
+ /// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are converted to floating-point values.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffint_u.w))]
+ pub unsafe fn __msa_ffint_u_w(a: v4u32) -> v4f32 {
+     msa_ffint_u_w(a)
+ }
+ 
+ /// Vector Floating-Point Round and Convert from Unsigned Integer
+ ///
+ /// The unsigned integer elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are converted to floating-point values.
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffint_u.d))]
+ pub unsafe fn __msa_ffint_u_d(a: v2u64) -> v2f64 {
+     msa_ffint_u_d(a)
+ }
+ 
+ /// Vector Floating-Point Convert from Fixed-Point Left
+ ///
+ /// The left half fixed-point elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are up-converted to floating-point data format.
+ /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffql.w))]
+ pub unsafe fn __msa_ffql_w(a: v8i16) -> v4f32 {
+     msa_ffql_w(a)
+ }
+ 
+ /// Vector Floating-Point Convert from Fixed-Point Left
+ ///
+ /// The left half fixed-point elements in vector `a` (four signed 32-bit integer numbers)
+ /// are up-converted to floating-point data format.
+ /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point.
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffql.d))]
+ pub unsafe fn __msa_ffql_d(a: v4i32) -> v2f64 {
+     msa_ffql_d(a)
+ }
+ 
+ /// Vector Floating-Point Convert from Fixed-Point Left
+ ///
+ /// The right half fixed-point elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are up-converted to floating-point data format.
+ /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point.
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffqr.w))]
+ pub unsafe fn __msa_ffqr_w(a: v8i16) -> v4f32 {
+     msa_ffqr_w(a)
+ }
+ 
+ /// Vector Floating-Point Convert from Fixed-Point Left
+ ///
+ /// The right half fixed-point elements in vector `a` (four signed 32-bit integer numbers)
+ /// are up-converted to floating-point data format.
+ /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point.
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ffqr.d))]
+ pub unsafe fn __msa_ffqr_d(a: v4i32) -> v2f64 {
+     msa_ffqr_d(a)
+ }
+ 
+ /// Vector Fill from GPR
+ ///
+ /// Replicate GPR rs value to all elements in vector (sixteen signed 8-bit integer numbers).
+ /// If the source GPR is wider than the destination data format, the destination's elements
+ /// will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fill.b))]
+ pub unsafe fn __msa_fill_b(a: i32) -> v16i8 {
+     msa_fill_b(a)
+ }
+ 
+ /// Vector Fill from GPR
+ ///
+ /// Replicate GPR rs value to all elements in vector (eight signed 16-bit integer numbers).
+ /// If the source GPR is wider than the destination data format, the destination's elements
+ /// will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fill.h))]
+ pub unsafe fn __msa_fill_h(a: i32) -> v8i16 {
+     msa_fill_h(a)
+ }
+ 
+ /// Vector Fill from GPR
+ ///
+ /// Replicate GPR rs value to all elements in vector (four signed 32-bit integer numbers).
+ /// If the source GPR is wider than the destination data format, the destination's elements
+ /// will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fill.w))]
+ pub unsafe fn __msa_fill_w(a: i32) -> v4i32 {
+     msa_fill_w(a)
+ }
+ 
+ /// Vector Fill from GPR
+ ///
+ /// Replicate GPR rs value to all elements in vector (two signed 64-bit integer numbers).
+ /// If the source GPR is wider than the destination data format, the destination's elements
+ /// will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fill.d))]
+ pub unsafe fn __msa_fill_d(a: i64) -> v2i64 {
+     msa_fill_d(a)
+ }
+ 
+ /// Vector Floating-Point Base 2 Logarithm
+ ///
+ /// The signed integral base 2 exponents of floating-point elements in vector `a`
+ /// (four 32-bit floating point numbers) are written as floating-point values to vector elements
+ /// (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(flog2.w))]
+ pub unsafe fn __msa_flog2_w(a: v4f32) -> v4f32 {
+     msa_flog2_w(a)
+ }
+ 
+ /// Vector Floating-Point Base 2 Logarithm
+ ///
+ /// The signed integral base 2 exponents of floating-point elements in vector `a`
+ /// (two 64-bit floating point numbers) are written as floating-point values to vector elements
+ /// (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(flog2.d))]
+ pub unsafe fn __msa_flog2_d(a: v2f64) -> v2f64 {
+     msa_flog2_d(a)
+ }
+ 
+ /// Vector Floating-Point Multiply-Add
+ ///
+ /// The floating-point elements in vector `b` (four 32-bit floating point numbers)
+ /// multiplied by floating-point elements in vector `c` (four 32-bit floating point numbers)
+ /// are added to the floating-point elements in vector `a` (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmadd.w))]
+ pub unsafe fn __msa_fmadd_w(a: v4f32, b: v4f32, c: v4f32) -> v4f32 {
+     msa_fmadd_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Floating-Point Multiply-Add
+ ///
+ /// The floating-point elements in vector `b` (two 64-bit floating point numbers)
+ /// multiplied by floating-point elements in vector `c` (two 64-bit floating point numbers)
+ /// are added to the floating-point elements in vector `a` (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmadd.d))]
+ pub unsafe fn __msa_fmadd_d(a: v2f64, b: v2f64, c: v2f64) -> v2f64 {
+     msa_fmadd_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Floating-Point Maximum
+ ///
+ /// The largest values between corresponding floating-point elements in vector `a`
+ /// (four 32-bit floating point numbers) and vector `b` (four 32-bit floating point numbers)
+ /// are written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmax.w))]
+ pub unsafe fn __msa_fmax_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fmax_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Maximum
+ ///
+ /// The largest values between corresponding floating-point elements in vector `a`
+ /// (two 64-bit floating point numbers) and vector `b` (two 64-bit floating point numbers)
+ /// are written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmax.d))]
+ pub unsafe fn __msa_fmax_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fmax_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Maximum Based on Absolute Values
+ ///
+ /// The value with the largest magnitude, i.e. absolute value, between corresponding
+ /// floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// and vector `b` (four 32-bit floating point numbers)
+ /// are written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmax_a.w))]
+ pub unsafe fn __msa_fmax_a_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fmax_a_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Maximum Based on Absolute Values
+ ///
+ /// The value with the largest magnitude, i.e. absolute value, between corresponding
+ /// floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// and vector `b` (two 64-bit floating point numbers)
+ /// are written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmax_a.d))]
+ pub unsafe fn __msa_fmax_a_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fmax_a_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Minimum
+ ///
+ /// The smallest values between corresponding floating-point elements in vector `a`
+ /// (four 32-bit floating point numbers) and vector `b` (four 32-bit floating point numbers)
+ /// are written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmin.w))]
+ pub unsafe fn __msa_fmin_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fmin_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Minimum
+ ///
+ /// The smallest values between corresponding floating-point elements in vector `a`
+ /// (two 64-bit floating point numbers) and vector `b` (two 64-bit floating point numbers)
+ /// are written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmin.d))]
+ pub unsafe fn __msa_fmin_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fmin_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Minimum Based on Absolute Values
+ ///
+ /// The value with the smallest magnitude, i.e. absolute value, between corresponding
+ /// floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// and vector `b` (four 32-bit floating point numbers)
+ /// are written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmin_a.w))]
+ pub unsafe fn __msa_fmin_a_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fmin_a_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Minimum Based on Absolute Values
+ ///
+ /// The value with the smallest magnitude, i.e. absolute value, between corresponding
+ /// floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// and vector `b` (two 64-bit floating point numbers)
+ /// are written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmin_a.d))]
+ pub unsafe fn __msa_fmin_a_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fmin_a_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Multiply-Sub
+ ///
+ /// The floating-point elements in vector `b` (four 32-bit floating point numbers)
+ /// multiplied by floating-point elements in vector `c` (four 32-bit floating point numbers)
+ /// are subtracted from the floating-point elements in vector `a` (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmsub.w))]
+ pub unsafe fn __msa_fmsub_w(a: v4f32, b: v4f32, c: v4f32) -> v4f32 {
+     msa_fmsub_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Floating-Point Multiply-Sub
+ ///
+ /// The floating-point elements in vector `b` (two 64-bit floating point numbers)
+ /// multiplied by floating-point elements in vector `c` (two 64-bit floating point numbers)
+ /// are subtracted from the floating-point elements in vector `a` (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmsub.d))]
+ pub unsafe fn __msa_fmsub_d(a: v2f64, b: v2f64, c: v2f64) -> v2f64 {
+     msa_fmsub_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Floating-Point Multiplication
+ ///
+ /// The floating-point elements in vector `a` (four 32-bit floating point numbers) are
+ /// multiplied by floating-point elements in vector `b` (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmul.w))]
+ pub unsafe fn __msa_fmul_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fmul_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Multiplication
+ ///
+ /// The floating-point elements in vector `a` (two 64-bit floating point numbers) are
+ /// multiplied by floating-point elements in vector `b` (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fmul.d))]
+ pub unsafe fn __msa_fmul_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fmul_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Round to Integer
+ ///
+ /// The floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are rounded to an integral valued floating-point number in the same format based
+ /// on the rounding mode bits RM in MSA Control and Status Register MSACSR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(frint.w))]
+ pub unsafe fn __msa_frint_w(a: v4f32) -> v4f32 {
+     msa_frint_w(a)
+ }
+ 
+ /// Vector Floating-Point Round to Integer
+ ///
+ /// The floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// are rounded to an integral valued floating-point number in the same format based
+ /// on the rounding mode bits RM in MSA Control and Status Register MSACSR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(frint.d))]
+ pub unsafe fn __msa_frint_d(a: v2f64) -> v2f64 {
+     msa_frint_d(a)
+ }
+ 
+ /// Vector Approximate Floating-Point Reciprocal
+ ///
+ /// The reciprocals of floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are calculated and the result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(frcp.w))]
+ pub unsafe fn __msa_frcp_w(a: v4f32) -> v4f32 {
+     msa_frcp_w(a)
+ }
+ 
+ /// Vector Approximate Floating-Point Reciprocal
+ ///
+ /// The reciprocals of floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// are calculated and the result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(frcp.d))]
+ pub unsafe fn __msa_frcp_d(a: v2f64) -> v2f64 {
+     msa_frcp_d(a)
+ }
+ 
+ /// Vector Approximate Floating-Point Reciprocal of Square Root
+ ///
+ /// The reciprocals of the square roots of floating-point elements in vector `a` (four 32-bit floating point numbers)
+ /// are calculated and the result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(frsqrt.w))]
+ pub unsafe fn __msa_frsqrt_w(a: v4f32) -> v4f32 {
+     msa_frsqrt_w(a)
+ }
+ 
+ /// Vector Approximate Floating-Point Reciprocal of Square Root
+ ///
+ /// The reciprocals of the square roots of floating-point elements in vector `a` (two 64-bit floating point numbers)
+ /// are calculated and the result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(frsqrt.d))]
+ pub unsafe fn __msa_frsqrt_d(a: v2f64) -> v2f64 {
+     msa_frsqrt_d(a)
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Always False
+ ///
+ /// Set all bits to 0 in vector (four signed 32-bit integer numbers) elements.
+ /// Signaling and quiet NaN elements in vector `a` (four 32-bit floating point numbers)
+ /// or `b` (four 32-bit floating point numbers) signal Invalid Operation exception.
+ /// In case of a floating-point exception, the default result has all bits set to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsaf.w))]
+ pub unsafe fn __msa_fsaf_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsaf_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Always False
+ ///
+ /// Set all bits to 0 in vector (two signed 64-bit integer numbers) elements.
+ /// Signaling and quiet NaN elements in vector `a` (two 64-bit floating point numbers)
+ /// or `b` (two 64-bit floating point numbers) signal Invalid Operation exception.
+ /// In case of a floating-point exception, the default result has all bits set to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsaf.d))]
+ pub unsafe fn __msa_fsaf_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsaf_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers)
+ /// and `b` (four 32-bit floating point numbers) elements are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fseq.w))]
+ pub unsafe fn __msa_fseq_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fseq_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers)
+ /// and `b` (two 64-bit floating point numbers) elements are equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fseq.d))]
+ pub unsafe fn __msa_fseq_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fseq_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Less or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) elements
+ /// are less than or equal to `b` (four 32-bit floating point numbers) elements, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsle.w))]
+ pub unsafe fn __msa_fsle_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsle_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Less or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) elements
+ /// are less than or equal to `b` (two 64-bit floating point numbers) elements, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsle.d))]
+ pub unsafe fn __msa_fsle_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsle_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) elements
+ /// are less than `b` (four 32-bit floating point numbers) elements, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fslt.w))]
+ pub unsafe fn __msa_fslt_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fslt_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) elements
+ /// are less than `b` (two 64-bit floating point numbers) elements, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fslt.d))]
+ pub unsafe fn __msa_fslt_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fslt_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Not Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are not equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsne.w))]
+ pub unsafe fn __msa_fsne_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsne_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Not Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are not equal, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsne.d))]
+ pub unsafe fn __msa_fsne_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsne_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Ordered
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are ordered,
+ /// i.e. both elements are not NaN values, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsor.w))]
+ pub unsafe fn __msa_fsor_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsor_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Ordered
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are ordered,
+ /// i.e. both elements are not NaN values, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsor.d))]
+ pub unsafe fn __msa_fsor_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsor_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Square Root
+ ///
+ /// The square roots of floating-point elements in vector `a`
+ /// (four 32-bit floating point numbers) are written to vector
+ /// (four 32-bit floating point numbers) elements are ordered,.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsqrt.w))]
+ pub unsafe fn __msa_fsqrt_w(a: v4f32) -> v4f32 {
+     msa_fsqrt_w(a)
+ }
+ 
+ /// Vector Floating-Point Square Root
+ ///
+ /// The square roots of floating-point elements in vector `a`
+ /// (two 64-bit floating point numbers) are written to vector
+ /// (two 64-bit floating point numbers) elements are ordered,.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsqrt.d))]
+ pub unsafe fn __msa_fsqrt_d(a: v2f64) -> v2f64 {
+     msa_fsqrt_d(a)
+ }
+ 
+ /// Vector Floating-Point Subtraction
+ ///
+ /// The floating-point elements in vector `b` (four 32-bit floating point numbers)
+ /// are subtracted from the floating-point elements in vector `a`
+ /// (four 32-bit floating point numbers).
+ /// The result is written to vector (four 32-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsub.w))]
+ pub unsafe fn __msa_fsub_w(a: v4f32, b: v4f32) -> v4f32 {
+     msa_fsub_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Subtraction
+ ///
+ /// The floating-point elements in vector `b` (two 64-bit floating point numbers)
+ /// are subtracted from the floating-point elements in vector `a`
+ /// (two 64-bit floating point numbers).
+ /// The result is written to vector (two 64-bit floating point numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsub.d))]
+ pub unsafe fn __msa_fsub_d(a: v2f64, b: v2f64) -> v2f64 {
+     msa_fsub_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Ordered
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are unordered or equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsueq.w))]
+ pub unsafe fn __msa_fsueq_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsueq_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Ordered
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are unordered or equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsueq.d))]
+ pub unsafe fn __msa_fsueq_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsueq_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered or Less or Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) elements are
+ /// unordered or less than or equal to `b` (four 32-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsule.w))]
+ pub unsafe fn __msa_fsule_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsule_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered or Less or Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) elements are
+ /// unordered or less than or equal to `b` (two 64-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsule.d))]
+ pub unsafe fn __msa_fsule_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsule_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered or Less Than
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) elements
+ /// are unordered or less than `b` (four 32-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsult.w))]
+ pub unsafe fn __msa_fsult_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsult_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered or Less Than
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) elements
+ /// are unordered or less than `b` (two 64-bit floating point numbers) elements,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsult.d))]
+ pub unsafe fn __msa_fsult_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsult_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are unordered,
+ /// i.e. at least one element is a NaN value, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsun.w))]
+ pub unsafe fn __msa_fsun_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsun_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are unordered,
+ /// i.e. at least one element is a NaN value, otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsun.d))]
+ pub unsafe fn __msa_fsun_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsun_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered or Not Equal
+ ///
+ /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements
+ /// if the corresponding `a` (four 32-bit floating point numbers) and
+ /// `b` (four 32-bit floating point numbers) elements are unordered or not equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsune.w))]
+ pub unsafe fn __msa_fsune_w(a: v4f32, b: v4f32) -> v4i32 {
+     msa_fsune_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Signaling Compare Unordered or Not Equal
+ ///
+ /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements
+ /// if the corresponding `a` (two 64-bit floating point numbers) and
+ /// `b` (two 64-bit floating point numbers) elements are unordered or not equal,
+ /// otherwise set all bits to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(fsune.d))]
+ pub unsafe fn __msa_fsune_d(a: v2f64, b: v2f64) -> v2i64 {
+     msa_fsune_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Convert to Signed Integer
+ ///
+ ///The elements in vector `a` (four 32-bit floating point numbers)
+ /// are rounded and converted to signed integer values based on the
+ /// rounding mode bits RM in MSA Control and Status Register MSACSR.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftint_s.w))]
+ pub unsafe fn __msa_ftint_s_w(a: v4f32) -> v4i32 {
+     msa_ftint_s_w(a)
+ }
+ 
+ /// Vector Floating-Point Convert to Signed Integer
+ ///
+ ///The elements in vector `a` (two 64-bit floating point numbers)
+ /// are rounded and converted to signed integer values based on the
+ /// rounding mode bits RM in MSA Control and Status Register MSACSR.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftint_s.d))]
+ pub unsafe fn __msa_ftint_s_d(a: v2f64) -> v2i64 {
+     msa_ftint_s_d(a)
+ }
+ 
+ /// Vector Floating-Point Convert to Unsigned Integer
+ ///
+ /// The elements in vector `a` (four 32-bit floating point numbers)
+ /// are rounded and converted to signed integer values based on the
+ /// rounding mode bits RM in MSA Control and Status Register MSACSR.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftint_u.w))]
+ pub unsafe fn __msa_ftint_u_w(a: v4f32) -> v4u32 {
+     msa_ftint_u_w(a)
+ }
+ 
+ /// Vector Floating-Point Convert to Unsigned Integer
+ ///
+ /// The elements in vector `a` (two 64-bit floating point numbers)
+ /// are rounded and converted to signed integer values based on the
+ /// rounding mode bits RM in MSA Control and Status Register MSACSR.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftint_u.d))]
+ pub unsafe fn __msa_ftint_u_d(a: v2f64) -> v2u64 {
+     msa_ftint_u_d(a)
+ }
+ 
+ /// Vector Floating-Point Convert to Fixed-Point
+ ///
+ /// The elements in vector `a` (four 32-bit floating point numbers)
+ /// and `b` (four 32-bit floating point numbers) are down-converted to a fixed-point
+ /// representation, i.e. from 64-bit floating-point to 32-bit Q31 fixed-point
+ /// representation, or from 32-bit floating-point to 16-bit Q15 fixed-point representation.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftq.h))]
+ pub unsafe fn __msa_ftq_h(a: v4f32, b: v4f32) -> v8i16 {
+     msa_ftq_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Convert to Fixed-Point
+ ///
+ /// The elements in vector `a` (two 64-bit floating point numbers)
+ /// and `b` (two 64-bit floating point numbers) are down-converted to a fixed-point
+ /// representation, i.e. from 64-bit floating-point to 32-bit Q31 fixed-point
+ /// representation, or from 32-bit floating-point to 16-bit Q15 fixed-point representation.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftq.w))]
+ pub unsafe fn __msa_ftq_w(a: v2f64, b: v2f64) -> v4i32 {
+     msa_ftq_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Floating-Point Truncate and Convert to Signed Integer
+ ///
+ /// The elements in vector `a` (four 32-bit floating point numbers)
+ /// are truncated, i.e. rounded toward zero, to signed integer values.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftrunc_s.w))]
+ pub unsafe fn __msa_ftrunc_s_w(a: v4f32) -> v4i32 {
+     msa_ftrunc_s_w(a)
+ }
+ 
+ /// Vector Floating-Point Truncate and Convert to Signed Integer
+ ///
+ /// The elements in vector `a` (two 64-bit floating point numbers)
+ /// are truncated, i.e. rounded toward zero, to signed integer values.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftrunc_s.d))]
+ pub unsafe fn __msa_ftrunc_s_d(a: v2f64) -> v2i64 {
+     msa_ftrunc_s_d(a)
+ }
+ 
+ /// Vector Floating-Point Truncate and Convert to Unsigned Integer
+ ///
+ /// The elements in vector `a` (four 32-bit floating point numbers)
+ /// are truncated, i.e. rounded toward zero, to unsigned integer values.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftrunc_u.w))]
+ pub unsafe fn __msa_ftrunc_u_w(a: v4f32) -> v4u32 {
+     msa_ftrunc_u_w(a)
+ }
+ 
+ /// Vector Floating-Point Truncate and Convert to Unsigned Integer
+ ///
+ /// The elements in vector `a` (two 64-bit floating point numbers)
+ /// are truncated, i.e. rounded toward zero, to unsigned integer values.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ftrunc_u.d))]
+ pub unsafe fn __msa_ftrunc_u_d(a: v2f64) -> v2u64 {
+     msa_ftrunc_u_d(a)
+ }
+ 
+ /// Vector Signed Horizontal Add
+ ///
+ /// The sign-extended odd elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are added to the sign-extended even elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hadd_s.h))]
+ pub unsafe fn __msa_hadd_s_h(a: v16i8, b: v16i8) -> v8i16 {
+     msa_hadd_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Horizontal Add
+ ///
+ /// The sign-extended odd elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are added to the sign-extended even elements in vector `b` (eight signed 16-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hadd_s.w))]
+ pub unsafe fn __msa_hadd_s_w(a: v8i16, b: v8i16) -> v4i32 {
+     msa_hadd_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Horizontal Add
+ ///
+ /// The sign-extended odd elements in vector `a` (four signed 32-bit integer numbers)
+ /// are added to the sign-extended even elements in vector `b` (four signed 32-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hadd_s.d))]
+ pub unsafe fn __msa_hadd_s_d(a: v4i32, b: v4i32) -> v2i64 {
+     msa_hadd_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Horizontal Add
+ ///
+ /// The zero-extended odd elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are added to the zero-extended even elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hadd_u.h))]
+ pub unsafe fn __msa_hadd_u_h(a: v16u8, b: v16u8) -> v8u16 {
+     msa_hadd_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Horizontal Add
+ ///
+ /// The zero-extended odd elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are added to the zero-extended even elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hadd_u.w))]
+ pub unsafe fn __msa_hadd_u_w(a: v8u16, b: v8u16) -> v4u32 {
+     msa_hadd_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Horizontal Add
+ ///
+ /// The zero-extended odd elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are added to the zero-extended even elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hadd_u.d))]
+ pub unsafe fn __msa_hadd_u_d(a: v4u32, b: v4u32) -> v2u64 {
+     msa_hadd_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Horizontal Subtract
+ ///
+ /// The sign-extended odd elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are subtracted from the sign-extended elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hsub_s.h))]
+ pub unsafe fn __msa_hsub_s_h(a: v16i8, b: v16i8) -> v8i16 {
+     msa_hsub_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Horizontal Subtract
+ ///
+ /// The sign-extended odd elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are subtracted from the sign-extended elements in vector `a` (eight signed 16-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hsub_s.w))]
+ pub unsafe fn __msa_hsub_s_w(a: v8i16, b: v8i16) -> v4i32 {
+     msa_hsub_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Horizontal Subtract
+ ///
+ /// The sign-extended odd elements in vector `b` (four signed 32-bit integer numbers)
+ /// are subtracted from the sign-extended elements in vector `a` (four signed 32-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hsub_s.d))]
+ pub unsafe fn __msa_hsub_s_d(a: v4i32, b: v4i32) -> v2i64 {
+     msa_hsub_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Horizontal Subtract
+ ///
+ /// The zero-extended odd elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// are subtracted from the zero-extended elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hsub_u.h))]
+ pub unsafe fn __msa_hsub_u_h(a: v16u8, b: v16u8) -> v8i16 {
+     msa_hsub_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Horizontal Subtract
+ ///
+ /// The zero-extended odd elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// are subtracted from the zero-extended elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hsub_u.w))]
+ pub unsafe fn __msa_hsub_u_w(a: v8u16, b: v8u16) -> v4i32 {
+     msa_hsub_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Horizontal Subtract
+ ///
+ /// The zero-extended odd elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// are subtracted from the zero-extended elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// producing a result twice the size of the input operands.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(hsub_u.d))]
+ pub unsafe fn __msa_hsub_u_d(a: v4u32, b: v4u32) -> v2i64 {
+     msa_hsub_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Even
+ ///
+ /// Even elements in vectors `a` (sixteen signed 8-bit integer numbers)
+ /// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result
+ /// (sixteen signed 8-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvev.b))]
+ pub unsafe fn __msa_ilvev_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_ilvev_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Even
+ ///
+ /// Even elements in vectors `a` (eight signed 16-bit integer numbers)
+ /// and vector `b` (eight signed 16-bit integer numbers) are copied to the result
+ /// (eight signed 16-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvev.h))]
+ pub unsafe fn __msa_ilvev_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_ilvev_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Even
+ ///
+ /// Even elements in vectors `a` (four signed 32-bit integer numbers)
+ /// and vector `b` (four signed 32-bit integer numbers) are copied to the result
+ /// (four signed 32-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvev.w))]
+ pub unsafe fn __msa_ilvev_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_ilvev_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Even
+ ///
+ /// Even elements in vectors `a` (two signed 64-bit integer numbers)
+ /// and vector `b` (two signed 64-bit integer numbers) are copied to the result
+ /// (two signed 64-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvev.d))]
+ pub unsafe fn __msa_ilvev_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_ilvev_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Left
+ ///
+ /// The left half elements in vectors `a` (sixteen signed 8-bit integer numbers)
+ /// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result
+ /// (sixteen signed 8-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvl.b))]
+ pub unsafe fn __msa_ilvl_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_ilvl_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Left
+ ///
+ /// The left half elements in vectors `a` (eight signed 16-bit integer numbers)
+ /// and vector `b` (eight signed 16-bit integer numbers) are copied to the result
+ /// (eight signed 16-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvl.h))]
+ pub unsafe fn __msa_ilvl_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_ilvl_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Left
+ ///
+ /// The left half elements in vectors `a` (four signed 32-bit integer numbers)
+ /// and vector `b` (four signed 32-bit integer numbers) are copied to the result
+ /// (four signed 32-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvl.w))]
+ pub unsafe fn __msa_ilvl_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_ilvl_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Left
+ ///
+ /// The left half elements in vectors `a` (two signed 64-bit integer numbers)
+ /// and vector `b` (two signed 64-bit integer numbers) are copied to the result
+ /// (two signed 64-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvl.d))]
+ pub unsafe fn __msa_ilvl_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_ilvl_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Odd
+ ///
+ /// Odd elements in vectors `a` (sixteen signed 8-bit integer numbers)
+ /// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result
+ /// (sixteen signed 8-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvod.b))]
+ pub unsafe fn __msa_ilvod_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_ilvod_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Odd
+ ///
+ /// Odd elements in vectors `a` (eight signed 16-bit integer numbers)
+ /// and vector `b` (eight signed 16-bit integer numbers) are copied to the result
+ /// (eight signed 16-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvod.h))]
+ pub unsafe fn __msa_ilvod_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_ilvod_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Odd
+ ///
+ /// Odd elements in vectors `a` (four signed 32-bit integer numbers)
+ /// and vector `b` (four signed 32-bit integer numbers) are copied to the result
+ /// (four signed 32-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvod.w))]
+ pub unsafe fn __msa_ilvod_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_ilvod_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Odd
+ ///
+ /// Odd elements in vectors `a` (two signed 64-bit integer numbers)
+ /// and vector `b` (two signed 64-bit integer numbers) are copied to the result
+ /// (two signed 64-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvod.d))]
+ pub unsafe fn __msa_ilvod_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_ilvod_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Right
+ ///
+ /// The right half elements in vectors `a` (sixteen signed 8-bit integer numbers)
+ /// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result
+ /// (sixteen signed 8-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvr.b))]
+ pub unsafe fn __msa_ilvr_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_ilvr_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Right
+ ///
+ /// The right half elements in vectors `a` (eight signed 16-bit integer numbers)
+ /// and vector `b` (eight signed 16-bit integer numbers) are copied to the result
+ /// (eight signed 16-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvr.h))]
+ pub unsafe fn __msa_ilvr_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_ilvr_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Right
+ ///
+ /// The right half elements in vectors `a` (four signed 32-bit integer numbers)
+ /// and vector `b` (four signed 32-bit integer numbers) are copied to the result
+ /// (four signed 32-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvr.w))]
+ pub unsafe fn __msa_ilvr_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_ilvr_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Interleave Right
+ ///
+ /// The right half elements in vectors `a` (two signed 64-bit integer numbers)
+ /// and vector `b` (two signed 64-bit integer numbers) are copied to the result
+ /// (two signed 64-bit integer numbers)
+ /// alternating one element from `a` with one element from `b`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ilvr.d))]
+ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_ilvr_d(a, mem::transmute(b))
+ }
+ 
+ /// GPR Insert Element
+ ///
+ /// Set element `imm4` in vector `a` (sixteen signed 8-bit integer numbers) to GPR `c` value.
+ /// All other elements in vector `a` are unchanged. If the source GPR is wider than the
+ /// destination data format, the destination's elements will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insert.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insert_b(a: v16i8, imm4: i32, c: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_insert_b(a, $imm4, c)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// GPR Insert Element
+ ///
+ /// Set element `imm3` in vector `a` (eight signed 16-bit integer numbers) to GPR `c` value.
+ /// All other elements in vector `a` are unchanged. If the source GPR is wider than the
+ /// destination data format, the destination's elements will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insert.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insert_h(a: v8i16, imm3: i32, c: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_insert_h(a, $imm3, c)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// GPR Insert Element
+ ///
+ /// Set element `imm2` in vector `a` (four signed 32-bit integer numbers) to GPR `c` value.
+ /// All other elements in vector `a` are unchanged. If the source GPR is wider than the
+ /// destination data format, the destination's elements will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insert.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insert_w(a: v4i32, imm2: i32, c: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_insert_w(a, $imm2, c)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// GPR Insert Element
+ ///
+ /// Set element `imm1` in vector `a` (two signed 64-bit integer numbers) to GPR `c` value.
+ /// All other elements in vector `a` are unchanged. If the source GPR is wider than the
+ /// destination data format, the destination's elements will be set to the least significant bits of the GPR.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insert.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insert_d(a: v2i64, imm1: i32, c: i64) -> v2i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_insert_d(a, $imm1, c)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// Element Insert Element
+ ///
+ /// Set element `imm1` in the result vector `a` (sixteen signed 8-bit integer numbers) to element 0
+ /// in vector `c` (sixteen signed 8-bit integer numbers) value.
+ /// All other elements in vector `a` are unchanged.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insve.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insve_b(a: v16i8, imm4: i32, c: v16i8) -> v16i8 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_insve_b(a, $imm4, c)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Element Insert Element
+ ///
+ /// Set element `imm1` in the result vector `a` (eight signed 16-bit integer numbers) to element 0
+ /// in vector `c` (eight signed 16-bit integer numbers) value.
+ /// All other elements in vector `a` are unchanged.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insve.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insve_h(a: v8i16, imm3: i32, c: v8i16) -> v8i16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_insve_h(a, $imm3, c)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Element Insert Element
+ ///
+ /// Set element `imm1` in the result vector `a` (four signed 32-bit integer numbers) to element 0
+ /// in vector `c` (four signed 32-bit integer numbers) value.
+ /// All other elements in vector `a` are unchanged.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insve.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insve_w(a: v4i32, imm2: i32, c: v4i32) -> v4i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_insve_w(a, $imm2, c)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Element Insert Element
+ ///
+ /// Set element `imm1` in the result vector `a` (two signed 64-bit integer numbers) to element 0
+ /// in vector `c` (two signed 64-bit integer numbers) value.
+ /// All other elements in vector `a` are unchanged.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(insve.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_insve_d(a: v2i64, imm1: i32, c: v2i64) -> v2i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_insve_d(a, $imm1, c)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// Vector Load
+ ///
+ /// The WRLEN / 8 bytes at the effective memory location addressed by the base
+ /// `mem_addr` and the 10-bit signed immediate offset `imm_s10` are fetched and placed in
+ /// the vector (sixteen signed 8-bit integer numbers) value.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ld.b, imm_s10 = 0b1111111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ld_b(mem_addr: *mut u8, imm_s10: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s10:expr) => {
+             msa_ld_b(mem_addr, $imm_s10)
+         };
+     }
+     constify_imm_s10!(imm_s10, call)
+ }
+ 
+ /// Vector Load
+ ///
+ /// The WRLEN / 8 bytes at the effective memory location addressed by the base
+ /// `mem_addr` and the 10-bit signed immediate offset `imm_s11` are fetched and placed in
+ /// the vector (eight signed 16-bit integer numbers) value.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ld.h, imm_s11 = 0b11111111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ld_h(mem_addr: *mut u8, imm_s11: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s11:expr) => {
+             msa_ld_h(mem_addr, $imm_s11)
+         };
+     }
+     constify_imm_s11!(imm_s11, call)
+ }
+ 
+ /// Vector Load
+ ///
+ /// The WRLEN / 8 bytes at the effective memory location addressed by the base
+ /// `mem_addr` and the 10-bit signed immediate offset `imm_s12` are fetched and placed in
+ /// the vector (four signed 32-bit integer numbers) value.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ld.w, imm_s12 = 0b111111111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ld_w(mem_addr: *mut u8, imm_s12: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s12:expr) => {
+             msa_ld_w(mem_addr, $imm_s12)
+         };
+     }
+     constify_imm_s12!(imm_s12, call)
+ }
+ 
+ /// Vector Load
+ ///
+ /// The WRLEN / 8 bytes at the effective memory location addressed by the base
+ /// `mem_addr` and the 10-bit signed immediate offset `imm_s13` are fetched and placed in
+ /// the vector (two signed 64-bit integer numbers) value.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ld.d, imm_s13 = 0b1111111111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ld_d(mem_addr: *mut u8, imm_s13: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s13:expr) => {
+             msa_ld_d(mem_addr, $imm_s13)
+         };
+     }
+     constify_imm_s13!(imm_s13, call)
+ }
+ 
+ /// Immediate Load
+ ///
+ /// The signed immediate imm_s10 is replicated in all vector
+ /// (sixteen signed 8-bit integer numbers) elements. For byte elements,
+ /// only the least significant 8 bits of imm_s10 will be used.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ldi.b, imm_s10 = 0b1111111111))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __msa_ldi_b(imm_s10: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s10:expr) => {
+             msa_ldi_b($imm_s10)
+         };
+     }
+     constify_imm_s10!(imm_s10, call)
+ }
+ 
+ /// Immediate Load
+ ///
+ /// The signed immediate imm_s10 is replicated in all vector
+ /// (eight signed 16-bit integer numbers) elements. For byte elements,
+ /// only the least significant 8 bits of imm_s10 will be used.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ldi.h, imm_s10 = 0b1111111111))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __msa_ldi_h(imm_s10: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s10:expr) => {
+             msa_ldi_h($imm_s10)
+         };
+     }
+     constify_imm_s10!(imm_s10, call)
+ }
+ 
+ /// Immediate Load
+ ///
+ /// The signed immediate imm_s10 is replicated in all vector
+ /// (four signed 32-bit integer numbers) elements. For byte elements,
+ /// only the least significant 8 bits of imm_s10 will be used.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ldi.w, imm_s10 = 0b1111111111))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __msa_ldi_w(imm_s10: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s10:expr) => {
+             msa_ldi_w($imm_s10)
+         };
+     }
+     constify_imm_s10!(imm_s10, call)
+ }
+ 
+ /// Immediate Load
+ ///
+ /// The signed immediate imm_s10 is replicated in all vector
+ /// (two signed 64-bit integer numbers) elements. For byte elements,
+ /// only the least significant 8 bits of imm_s10 will be used.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ldi.d, imm_s10 = 0b1111111111))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn __msa_ldi_d(imm_s10: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s10:expr) => {
+             msa_ldi_d($imm_s10)
+         };
+     }
+     constify_imm_s10!(imm_s10, call)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Add
+ ///
+ /// The products of fixed-point elements in `b` (eight signed 16-bit integer numbers)
+ /// by fixed-point elements in vector `c` (eight signed 16-bit integer numbers)
+ /// are added to the fixed-point elements in vector `a` (eight signed 16-bit integer numbers).
+ /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination.
+ /// The saturated fixed-point results are stored to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(madd_q.h))]
+ pub unsafe fn __msa_madd_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_madd_q_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Add
+ ///
+ /// The products of fixed-point elements in `b` (four signed 32-bit integer numbers)
+ /// by fixed-point elements in vector `c` (four signed 32-bit integer numbers)
+ /// are added to the fixed-point elements in vector `a` (four signed 32-bit integer numbers).
+ /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination.
+ /// The saturated fixed-point results are stored to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(madd_q.w))]
+ pub unsafe fn __msa_madd_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_madd_q_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Add Rounded
+ ///
+ /// The products of fixed-point elements in `b` (eight signed 16-bit integer numbers)
+ /// by fixed-point elements in vector `c` (eight signed 16-bit integer numbers)
+ /// are added to the fixed-point elements in vector `a` (eight signed 16-bit integer numbers).
+ /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination.
+ /// The rounded and saturated fixed-point results are stored to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maddr_q.h))]
+ pub unsafe fn __msa_maddr_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_maddr_q_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Add Rounded
+ ///
+ /// The products of fixed-point elements in `b` (four signed 32-bit integer numbers)
+ /// by fixed-point elements in vector `c` (four signed 32-bit integer numbers)
+ /// are added to the fixed-point elements in vector `a` (four signed 32-bit integer numbers).
+ /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination.
+ /// The rounded and saturated fixed-point results are stored to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maddr_q.w))]
+ pub unsafe fn __msa_maddr_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_maddr_q_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Add
+ ///
+ /// The integer elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are multiplied by integer elements in vector `c` (sixteen signed 8-bit integer numbers)
+ /// and added to the integer elements in vector `a` (sixteen signed 8-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maddv.b))]
+ pub unsafe fn __msa_maddv_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8 {
+     msa_maddv_b(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Add
+ ///
+ /// The integer elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are multiplied by integer elements in vector `c` (eight signed 16-bit integer numbers)
+ /// and added to the integer elements in vector `a` (eight signed 16-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maddv.h))]
+ pub unsafe fn __msa_maddv_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_maddv_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Add
+ ///
+ /// The integer elements in vector `b` (four signed 32-bit integer numbers)
+ /// are multiplied by integer elements in vector `c` (four signed 32-bit integer numbers)
+ /// and added to the integer elements in vector `a` (four signed 32-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maddv.w))]
+ pub unsafe fn __msa_maddv_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_maddv_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Add
+ ///
+ /// The integer elements in vector `b` (two signed 64-bit integer numbers)
+ /// are multiplied by integer elements in vector `c` (two signed 64-bit integer numbers)
+ /// and added to the integer elements in vector `a` (two signed 64-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maddv.d))]
+ pub unsafe fn __msa_maddv_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64 {
+     msa_maddv_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Maximum Based on Absolute Values
+ ///
+ /// The value with the largest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (sixteen signed 8-bit integer numbers) and
+ /// `b` (sixteen signed 8-bit integer numbers) are written to vector
+ /// (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_a.b))]
+ pub unsafe fn __msa_max_a_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_max_a_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Maximum Based on Absolute Values
+ ///
+ /// The value with the largest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (eight signed 16-bit integer numbers) and
+ /// `b` (eight signed 16-bit integer numbers) are written to vector
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_a.h))]
+ pub unsafe fn __msa_max_a_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_max_a_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Maximum Based on Absolute Values
+ ///
+ /// The value with the largest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (four signed 32-bit integer numbers) and
+ /// `b` (four signed 32-bit integer numbers) are written to vector
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_a.w))]
+ pub unsafe fn __msa_max_a_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_max_a_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Maximum Based on Absolute Values
+ ///
+ /// The value with the largest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (two signed 64-bit integer numbers) and
+ /// `b` (two signed 64-bit integer numbers) are written to vector
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_a.d))]
+ pub unsafe fn __msa_max_a_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_max_a_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// and signed elements in vector `b` (sixteen signed 8-bit integer numbers) are written to vector
+ /// (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_s.b))]
+ pub unsafe fn __msa_max_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_max_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (eight signed 16-bit integer numbers)
+ /// and signed elements in vector `b` (eight signed 16-bit integer numbers) are written to vector
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_s.h))]
+ pub unsafe fn __msa_max_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_max_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (four signed 32-bit integer numbers)
+ /// and signed elements in vector `b` (four signed 32-bit integer numbers) are written to vector
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_s.w))]
+ pub unsafe fn __msa_max_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_max_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (two signed 64-bit integer numbers)
+ /// and signed elements in vector `b` (two signed 64-bit integer numbers) are written to vector
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_s.d))]
+ pub unsafe fn __msa_max_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_max_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// and unsigned elements in vector `b` (sixteen unsigned 8-bit integer numbers) are written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_u.b))]
+ pub unsafe fn __msa_max_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_max_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// and unsigned elements in vector `b` (eight unsigned 16-bit integer numbers) are written to vector
+ /// (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_u.h))]
+ pub unsafe fn __msa_max_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_max_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// and unsigned elements in vector `b` (four unsigned 32-bit integer numbers) are written to vector
+ /// (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_u.w))]
+ pub unsafe fn __msa_max_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_max_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// and unsigned elements in vector `b` (two unsigned 64-bit integer numbers) are written to vector
+ /// (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(max_u.d))]
+ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_max_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_s.b, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_maxi_s_b(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (eight signed 16-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_s.h, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_maxi_s_h(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (four signed 32-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_s.w, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_maxi_s_w(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Signed Maximum
+ ///
+ /// Maximum values between signed elements in vector `a` (two signed 64-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_s.d, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_maxi_s_d(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_u.b, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_u_b(a: v16u8, imm5: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_maxi_u_b(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_u.h, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_u_h(a: v8u16, imm5: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_maxi_u_h(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_u.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_u_w(a: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_maxi_u_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Maximum
+ ///
+ /// Maximum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(maxi_u.d, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_maxi_u_d(a: v2u64, imm5: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_maxi_u_d(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Minimum Based on Absolute Value
+ ///
+ /// The value with the smallest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (sixteen signed 8-bit integer numbers) and
+ /// `b` (sixteen signed 8-bit integer numbers) are written to vector
+ /// (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_a.b))]
+ pub unsafe fn __msa_min_a_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_min_a_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Minimum Based on Absolute Value
+ ///
+ /// The value with the smallest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (eight signed 16-bit integer numbers) and
+ /// `b` (eight signed 16-bit integer numbers) are written to vector
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_a.h))]
+ pub unsafe fn __msa_min_a_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_min_a_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Minimum Based on Absolute Value
+ ///
+ /// The value with the smallest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (four signed 32-bit integer numbers) and
+ /// `b` (four signed 32-bit integer numbers) are written to vector
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_a.w))]
+ pub unsafe fn __msa_min_a_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_min_a_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Minimum Based on Absolute Value
+ ///
+ /// The value with the smallest magnitude, i.e. absolute value, between corresponding
+ /// signed elements in vector `a` (two signed 64-bit integer numbers) and
+ /// `b` (two signed 64-bit integer numbers) are written to vector
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_a.d))]
+ pub unsafe fn __msa_min_a_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_min_a_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// and signed elements in vector `b` (sixteen signed 8-bit integer numbers) are written to vector
+ /// (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_s.b))]
+ pub unsafe fn __msa_min_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_min_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (eight signed 16-bit integer numbers)
+ /// and signed elements in vector `b` (eight signed 16-bit integer numbers) are written to vector
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_s.h))]
+ pub unsafe fn __msa_min_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_min_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (four signed 32-bit integer numbers)
+ /// and signed elements in vector `b` (four signed 32-bit integer numbers) are written to vector
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_s.w))]
+ pub unsafe fn __msa_min_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_min_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (two signed 64-bit integer numbers)
+ /// and signed elements in vector `b` (two signed 64-bit integer numbers) are written to vector
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_s.d))]
+ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_min_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_s.b, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_mini_s_b(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (eight signed 16-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_s.h, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_mini_s_h(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (four signed 32-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_s.w, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_mini_s_w(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Immediate Signed Minimum
+ ///
+ /// Minimum values between signed elements in vector `a` (two signed 64-bit integer numbers)
+ /// and the 5-bit signed immediate imm_s5 are written to vector
+ /// (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_s.d, imm_s5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm_s5:expr) => {
+             msa_mini_s_d(a, $imm_s5)
+         };
+     }
+     constify_imm_s5!(imm_s5, call)
+ }
+ 
+ /// Vector Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// and unsigned elements in vector `b` (sixteen unsigned 8-bit integer numbers) are written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_u.b))]
+ pub unsafe fn __msa_min_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_min_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// and unsigned elements in vector `b` (eight unsigned 16-bit integer numbers) are written to vector
+ /// (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_u.h))]
+ pub unsafe fn __msa_min_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_min_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// and unsigned elements in vector `b` (four unsigned 32-bit integer numbers) are written to vector
+ /// (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_u.w))]
+ pub unsafe fn __msa_min_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_min_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// and unsigned elements in vector `b` (two unsigned 64-bit integer numbers) are written to vector
+ /// (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(min_u.d))]
+ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_min_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_u.b, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_u_b(a: v16u8, imm5: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_mini_u_b(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_u.h, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_u_h(a: v8u16, imm5: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_mini_u_h(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_u.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_u_w(a: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_mini_u_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Minimum
+ ///
+ /// Minimum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// and the 5-bit unsigned immediate `imm5` are written to vector
+ /// (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mini_u.d, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_mini_u_d(a: v2u64, imm5: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_mini_u_d(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Signed Modulo
+ ///
+ /// The signed integer elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (sixteen signed 8-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_s.b))]
+ pub unsafe fn __msa_mod_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_mod_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Modulo
+ ///
+ /// The signed integer elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (eight signed 16-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_s.h))]
+ pub unsafe fn __msa_mod_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_mod_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Modulo
+ ///
+ /// The signed integer elements in vector `a` (four signed 32-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (four signed 32-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (four signed 32-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_s.w))]
+ pub unsafe fn __msa_mod_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_mod_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Modulo
+ ///
+ /// The signed integer elements in vector `a` (two signed 64-bit integer numbers)
+ /// are divided by signed integer elements in vector `b` (two signed 64-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (two signed 64-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_s.d))]
+ pub unsafe fn __msa_mod_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_mod_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Modulo
+ ///
+ /// The unsigned integer elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (sixteen unsigned 8-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_u.b))]
+ pub unsafe fn __msa_mod_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_mod_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Modulo
+ ///
+ /// The unsigned integer elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (eight unsigned 16-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_u.h))]
+ pub unsafe fn __msa_mod_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_mod_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Modulo
+ ///
+ /// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (four unsigned 32-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_u.w))]
+ pub unsafe fn __msa_mod_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_mod_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Modulo
+ ///
+ /// The unsigned integer elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are divided by unsigned integer elements in vector `b` (two unsigned 64-bit integer numbers).
+ /// The remainder of the same sign as the dividend is written to vector
+ /// (two unsigned 64-bit integer numbers). If a divisor element vector `b` is zero,
+ /// the result value is UNPREDICTABLE.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mod_u.d))]
+ pub unsafe fn __msa_mod_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_mod_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Move
+ ///
+ /// Copy all WRLEN bits in vector `a` (eight signed 16-bit integer numbers)
+ /// to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(move.v))]
+ pub unsafe fn __msa_move_v(a: v16i8) -> v16i8 {
+     msa_move_v(a)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Subtract
+ ///
+ /// The product of fixed-point elements in vector `c` (eight signed 16-bit integer numbers)
+ /// by fixed-point elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are subtracted from the fixed-point elements in vector `a`
+ /// (eight signed 16-bit integer numbers). The multiplication result is not saturated,
+ /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination.
+ /// The saturated fixed-point results are stored back to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msub_q.h))]
+ pub unsafe fn __msa_msub_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_msub_q_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Subtract
+ ///
+ /// The product of fixed-point elements in vector `c` (four signed 32-bit integer numbers)
+ /// by fixed-point elements in vector `b` (four signed 32-bit integer numbers)
+ /// are subtracted from the fixed-point elements in vector `a`
+ /// (four signed 32-bit integer numbers). The multiplication result is not saturated,
+ /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination.
+ /// The saturated fixed-point results are stored back to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msub_q.w))]
+ pub unsafe fn __msa_msub_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_msub_q_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Subtract Rounded
+ ///
+ /// The product of fixed-point elements in vector `c` (eight signed 16-bit integer numbers)
+ /// by fixed-point elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are subtracted from the fixed-point elements in vector `a`
+ /// (eight signed 16-bit integer numbers). The multiplication result is not saturated,
+ /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination.
+ /// The rounded and saturated fixed-point results are stored back to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msubr_q.h))]
+ pub unsafe fn __msa_msubr_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_msubr_q_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply and Subtract Rounded
+ ///
+ /// The product of fixed-point elements in vector `c` (four signed 32-bit integer numbers)
+ /// by fixed-point elements in vector `b` (four signed 32-bit integer numbers)
+ /// are subtracted from the fixed-point elements in vector `a`
+ /// (four signed 32-bit integer numbers). The multiplication result is not saturated,
+ /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination.
+ /// The rounded and saturated fixed-point results are stored back to vector `a`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msubr_q.w))]
+ pub unsafe fn __msa_msubr_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_msubr_q_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Subtract
+ ///
+ /// The integer elements in vector `c` (sixteen signed 8-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// and subtracted from the integer elements in vector `a` (sixteen signed 8-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msubv.b))]
+ pub unsafe fn __msa_msubv_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8 {
+     msa_msubv_b(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Subtract
+ ///
+ /// The integer elements in vector `c` (eight signed 16-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (eight signed 16-bit integer numbers)
+ /// and subtracted from the integer elements in vector `a` (eight signed 16-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msubv.h))]
+ pub unsafe fn __msa_msubv_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_msubv_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Subtract
+ ///
+ /// The integer elements in vector `c` (four signed 32-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (four signed 32-bit integer numbers)
+ /// and subtracted from the integer elements in vector `a` (four signed 32-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msubv.w))]
+ pub unsafe fn __msa_msubv_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_msubv_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Multiply and Subtract
+ ///
+ /// The integer elements in vector `c` (two signed 64-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (two signed 64-bit integer numbers)
+ /// and subtracted from the integer elements in vector `a` (two signed 64-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(msubv.d))]
+ pub unsafe fn __msa_msubv_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64 {
+     msa_msubv_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Fixed-Point Multiply
+ ///
+ /// The fixed-point elements in vector `a` (eight signed 16-bit integer numbers)
+ /// multiplied by fixed-point elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mul_q.h))]
+ pub unsafe fn __msa_mul_q_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_mul_q_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Fixed-Point Multiply
+ ///
+ /// The fixed-point elements in vector `a` (four signed 32-bit integer numbers)
+ /// multiplied by fixed-point elements in vector `b` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mul_q.w))]
+ pub unsafe fn __msa_mul_q_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_mul_q_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Fixed-Point Multiply Rounded
+ ///
+ /// The fixed-point elements in vector `a` (eight signed 16-bit integer numbers)
+ /// multiplied by fixed-point elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The rounded result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mulr_q.h))]
+ pub unsafe fn __msa_mulr_q_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_mulr_q_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Fixed-Point Multiply Rounded
+ ///
+ /// The fixed-point elements in vector `a` (four signed 32-bit integer numbers)
+ /// multiplied by fixed-point elements in vector `b` (four signed 32-bit integer numbers).
+ /// The rounded result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mulr_q.w))]
+ pub unsafe fn __msa_mulr_q_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_mulr_q_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Multiply
+ ///
+ /// The integer elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mulv.b))]
+ pub unsafe fn __msa_mulv_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_mulv_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Multiply
+ ///
+ /// The integer elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mulv.h))]
+ pub unsafe fn __msa_mulv_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_mulv_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Multiply
+ ///
+ /// The integer elements in vector `a` (four signed 32-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mulv.w))]
+ pub unsafe fn __msa_mulv_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_mulv_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Multiply
+ ///
+ /// The integer elements in vector `a` (two signed 64-bit integer numbers)
+ /// are multiplied by integer elements in vector `b` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ /// The most significant half of the multiplication result is discarded.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(mulv.d))]
+ pub unsafe fn __msa_mulv_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_mulv_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Leading Ones Count
+ ///
+ /// The number of leading ones for elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// is stored to the elements in vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nloc.b))]
+ pub unsafe fn __msa_nloc_b(a: v16i8) -> v16i8 {
+     msa_nloc_b(a)
+ }
+ 
+ /// Vector Leading Ones Count
+ ///
+ /// The number of leading ones for elements in vector `a` (eight signed 16-bit integer numbers)
+ /// is stored to the elements in vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nloc.h))]
+ pub unsafe fn __msa_nloc_h(a: v8i16) -> v8i16 {
+     msa_nloc_h(a)
+ }
+ 
+ /// Vector Leading Ones Count
+ ///
+ /// The number of leading ones for elements in vector `a` (four signed 32-bit integer numbers)
+ /// is stored to the elements in vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nloc.w))]
+ pub unsafe fn __msa_nloc_w(a: v4i32) -> v4i32 {
+     msa_nloc_w(a)
+ }
+ 
+ /// Vector Leading Ones Count
+ ///
+ /// The number of leading ones for elements in vector `a` (two signed 64-bit integer numbers)
+ /// is stored to the elements in vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nloc.d))]
+ pub unsafe fn __msa_nloc_d(a: v2i64) -> v2i64 {
+     msa_nloc_d(a)
+ }
+ 
+ /// Vector Leading Zeros Count
+ ///
+ /// The number of leading zeros for elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// is stored to the elements in vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nlzc.b))]
+ pub unsafe fn __msa_nlzc_b(a: v16i8) -> v16i8 {
+     msa_nlzc_b(a)
+ }
+ 
+ /// Vector Leading Zeros Count
+ ///
+ /// The number of leading zeros for elements in vector `a` (eight signed 16-bit integer numbers)
+ /// is stored to the elements in vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nlzc.h))]
+ pub unsafe fn __msa_nlzc_h(a: v8i16) -> v8i16 {
+     msa_nlzc_h(a)
+ }
+ 
+ /// Vector Leading Zeros Count
+ ///
+ /// The number of leading zeros for elements in vector `a` (four signed 32-bit integer numbers)
+ /// is stored to the elements in vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nlzc.w))]
+ pub unsafe fn __msa_nlzc_w(a: v4i32) -> v4i32 {
+     msa_nlzc_w(a)
+ }
+ 
+ /// Vector Leading Zeros Count
+ ///
+ /// The number of leading zeros for elements in vector `a` (two signed 64-bit integer numbers)
+ /// is stored to the elements in vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nlzc.d))]
+ pub unsafe fn __msa_nlzc_d(a: v2i64) -> v2i64 {
+     msa_nlzc_d(a)
+ }
+ 
+ /// Vector Logical Negated Or
+ ///
+ /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// in a bitwise logical NOR operation. The result is written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nor.v))]
+ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 {
+     msa_nor_v(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Logical Negated Or
+ ///
+ /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the 8-bit immediate `imm8`
+ /// in a bitwise logical NOR operation. The result is written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(nori.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_nori_b(a: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_nori_b(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Vector Logical Or
+ ///
+ /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// in a bitwise logical OR operation. The result is written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(or.v))]
+ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 {
+     msa_or_v(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Logical Or
+ ///
+ /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the 8-bit immediate `imm8`
+ /// in a bitwise logical OR operation. The result is written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(ori.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_ori_b(a: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_ori_b(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Vector Pack Even
+ ///
+ /// Even elements in vectors `a` (sixteen signed 8-bit integer numbers)
+ /// are copied to the left half of the result vector and even elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckev.b))]
+ pub unsafe fn __msa_pckev_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_pckev_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Even
+ ///
+ /// Even elements in vectors `a` (eight signed 16-bit integer numbers)
+ /// are copied to the left half of the result vector and even elements in vector `b`
+ /// (eight signed 16-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckev.h))]
+ pub unsafe fn __msa_pckev_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_pckev_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Even
+ ///
+ /// Even elements in vectors `a` (four signed 32-bit integer numbers)
+ /// are copied to the left half of the result vector and even elements in vector `b`
+ /// (four signed 32-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckev.w))]
+ pub unsafe fn __msa_pckev_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_pckev_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Even
+ ///
+ /// Even elements in vectors `a` (two signed 64-bit integer numbers)
+ /// are copied to the left half of the result vector and even elements in vector `b`
+ /// (two signed 64-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckev.d))]
+ pub unsafe fn __msa_pckev_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_pckev_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Odd
+ ///
+ /// Odd elements in vectors `a` (sixteen signed 8-bit integer numbers)
+ /// are copied to the left half of the result vector and odd elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckod.b))]
+ pub unsafe fn __msa_pckod_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_pckod_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Odd
+ ///
+ /// Odd elements in vectors `a` (eight signed 16-bit integer numbers)
+ /// are copied to the left half of the result vector and odd elements in vector `b`
+ /// (eight signed 16-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckod.h))]
+ pub unsafe fn __msa_pckod_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_pckod_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Odd
+ ///
+ /// Odd elements in vectors `a` (four signed 32-bit integer numbers)
+ /// are copied to the left half of the result vector and odd elements in vector `b`
+ /// (four signed 32-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckod.w))]
+ pub unsafe fn __msa_pckod_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_pckod_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Pack Odd
+ ///
+ /// Odd elements in vectors `a` (two signed 64-bit integer numbers)
+ /// are copied to the left half of the result vector and odd elements in vector `b`
+ /// (two signed 64-bit integer numbers) are copied to the right half of the result vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pckod.d))]
+ pub unsafe fn __msa_pckod_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_pckod_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Population Count
+ ///
+ /// The number of bits set to 1 for elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// is stored to the elements in the result vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pcnt.b))]
+ pub unsafe fn __msa_pcnt_b(a: v16i8) -> v16i8 {
+     msa_pcnt_b(a)
+ }
+ 
+ /// Vector Population Count
+ ///
+ /// The number of bits set to 1 for elements in vector `a` (eight signed 16-bit integer numbers)
+ /// is stored to the elements in the result vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pcnt.h))]
+ pub unsafe fn __msa_pcnt_h(a: v8i16) -> v8i16 {
+     msa_pcnt_h(a)
+ }
+ 
+ /// Vector Population Count
+ ///
+ /// The number of bits set to 1 for elements in vector `a` (four signed 32-bit integer numbers)
+ /// is stored to the elements in the result vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pcnt.w))]
+ pub unsafe fn __msa_pcnt_w(a: v4i32) -> v4i32 {
+     msa_pcnt_w(a)
+ }
+ 
+ /// Vector Population Count
+ ///
+ /// The number of bits set to 1 for elements in vector `a` (two signed 64-bit integer numbers)
+ /// is stored to the elements in the result vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(pcnt.d))]
+ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 {
+     msa_pcnt_d(a)
+ }
+ 
+ /// Immediate Signed Saturate
+ ///
+ /// Signed elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are saturated to signed values of `imm3+1` bits without changing the data width.
+ /// The result is stored in the vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_s.b, imm4 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_s_b(a: v16i8, imm3: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_sat_s_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Signed Saturate
+ ///
+ /// Signed elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are saturated to signed values of `imm4+1` bits without changing the data width.
+ /// The result is stored in the vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_s.h, imm3 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_s_h(a: v8i16, imm4: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_sat_s_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Signed Saturate
+ ///
+ /// Signed elements in vector `a` (four signed 32-bit integer numbers)
+ /// are saturated to signed values of `imm5+1` bits without changing the data width.
+ /// The result is stored in the vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_s.w, imm2 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_s_w(a: v4i32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_sat_s_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Signed Saturate
+ ///
+ /// Signed elements in vector `a` (two signed 64-bit integer numbers)
+ /// are saturated to signed values of `imm6+1` bits without changing the data width.
+ /// The result is stored in the vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_s.d, imm1 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_s_d(a: v2i64, imm6: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_sat_s_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Immediate Unsigned Saturate
+ ///
+ /// Unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// are saturated to unsigned values of `imm3+1` bits without changing the data width.
+ /// The result is stored in the vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_u.b, imm4 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_u_b(a: v16u8, imm3: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_sat_u_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Unsigned Saturate
+ ///
+ /// Unsigned elements in vector `a` (eight unsigned 16-bit integer numbers)
+ /// are saturated to unsigned values of `imm4+1` bits without changing the data width.
+ /// The result is stored in the vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_u.h, imm3 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_u_h(a: v8u16, imm4: i32) -> v8u16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_sat_u_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Unsigned Saturate
+ ///
+ /// Unsigned elements in vector `a` (four unsigned 32-bit integer numbers)
+ /// are saturated to unsigned values of `imm5+1` bits without changing the data width.
+ /// The result is stored in the vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_u.w, imm2 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_u_w(a: v4u32, imm5: i32) -> v4u32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_sat_u_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Unsigned Saturate
+ ///
+ /// Unsigned elements in vector `a` (two unsigned 64-bit integer numbers)
+ /// are saturated to unsigned values of `imm6+1` bits without changing the data width.
+ /// The result is stored in the vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sat_u.d, imm1 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_sat_u_d(a: v2u64, imm6: i32) -> v2u64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_sat_u_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Immediate Set Shuffle Elements
+ ///
+ /// The set shuffle instruction works on 4-element sets.
+ /// All sets are shuffled in the same way: the element i82i+1..2i in `a`
+ /// (sixteen signed 8-bit integer numbers) is copied over the element i in result vector
+ /// (sixteen signed 8-bit integer numbers), where i is 0, 1, 2, 3.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(shf.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_shf_b(a: v16i8, imm8: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_shf_b(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Immediate Set Shuffle Elements
+ ///
+ /// The set shuffle instruction works on 4-element sets.
+ /// All sets are shuffled in the same way: the element i82i+1..2i in `a`
+ /// (eight signed 16-bit integer numbers) is copied over the element i in result vector
+ /// (eight signed 16-bit integer numbers), where i is 0, 1, 2, 3.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(shf.h, imm8 = 0b11111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_shf_h(a: v8i16, imm8: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_shf_h(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Immediate Set Shuffle Elements
+ ///
+ /// The set shuffle instruction works on 4-element sets.
+ /// All sets are shuffled in the same way: the element i82i+1..2i in `a`
+ /// (four signed 32-bit integer numbers) is copied over the element i in result vector
+ /// (four signed 32-bit integer numbers), where i is 0, 1, 2, 3.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(shf.w, imm8 = 0b11111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_shf_w(a: v4i32, imm8: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_shf_w(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// GPR Columns Slide
+ ///
+ /// Vector registers `a` (sixteen signed 8-bit integer numbers) and `b`
+ /// (sixteen signed 8-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by the number of columns given in GPR `c`.
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ /// GPR `c` value is interpreted modulo the number of columns in destination rectangle,
+ /// or equivalently, the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sld.b))]
+ pub unsafe fn __msa_sld_b(a: v16i8, b: v16i8, c: i32) -> v16i8 {
+     msa_sld_b(a, mem::transmute(b), c)
+ }
+ 
+ /// GPR Columns Slide
+ ///
+ /// Vector registers `a` (eight signed 16-bit integer numbers) and `b`
+ /// (eight signed 16-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by the number of columns given in GPR `c`.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ /// GPR `c` value is interpreted modulo the number of columns in destination rectangle,
+ /// or equivalently, the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sld.h))]
+ pub unsafe fn __msa_sld_h(a: v8i16, b: v8i16, c: i32) -> v8i16 {
+     msa_sld_h(a, mem::transmute(b), c)
+ }
+ 
+ /// GPR Columns Slide
+ ///
+ /// Vector registers `a` (four signed 32-bit integer numbers) and `b`
+ /// (four signed 32-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by the number of columns given in GPR `c`.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ /// GPR `c` value is interpreted modulo the number of columns in destination rectangle,
+ /// or equivalently, the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sld.w))]
+ pub unsafe fn __msa_sld_w(a: v4i32, b: v4i32, c: i32) -> v4i32 {
+     msa_sld_w(a, mem::transmute(b), c)
+ }
+ 
+ /// GPR Columns Slide
+ ///
+ /// Vector registers `a` (two signed 64-bit integer numbers) and `b`
+ /// (two signed 64-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by the number of columns given in GPR `c`.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ /// GPR `c` value is interpreted modulo the number of columns in destination rectangle,
+ /// or equivalently, the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sld.d))]
+ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 {
+     msa_sld_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Immediate Columns Slide
+ ///
+ /// Vector registers `a` (sixteen signed 8-bit integer numbers) and `b`
+ /// (sixteen signed 8-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by `imm1` columns.
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sldi.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8, imm4: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_sldi_b(a, mem::transmute(b), $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Columns Slide
+ ///
+ /// Vector registers `a` (eight signed 16-bit integer numbers) and `b`
+ /// (eight signed 16-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by `imm1` columns.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sldi.h, imm3 = 0b111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16, imm3: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_sldi_h(a, mem::transmute(b), $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Columns Slide
+ ///
+ /// Vector registers `a` (four signed 32-bit integer numbers) and `b`
+ /// (four signed 32-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by `imm1` columns.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sldi.w, imm2 = 0b11))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32, imm2: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_sldi_w(a, mem::transmute(b), $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Immediate Columns Slide
+ ///
+ /// Vector registers `a` (two signed 64-bit integer numbers) and `b`
+ /// (two signed 64-bit integer numbers) contain 2-dimensional byte arrays (rectangles)
+ /// stored row-wise with as many rows as bytes in integer data format df.
+ /// The two source rectangles `b` and `a` are concatenated horizontally in the order
+ /// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination
+ /// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b`
+ /// by `imm1` columns.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sldi.d, imm1 = 0b1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64, imm1: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_sldi_d(a, mem::transmute(b), $imm1)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// Vector Shift Left
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted left by the number of bits the elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) specify modulo the size of the
+ /// element in bits. The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sll.b))]
+ pub unsafe fn __msa_sll_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_sll_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Left
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted left by the number of bits the elements in vector `b`
+ /// (eight signed 16-bit integer numbers) specify modulo the size of the
+ /// element in bits. The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sll.h))]
+ pub unsafe fn __msa_sll_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_sll_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Left
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted left by the number of bits the elements in vector `b`
+ /// (four signed 32-bit integer numbers) specify modulo the size of the
+ /// element in bits. The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sll.w))]
+ pub unsafe fn __msa_sll_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_sll_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Left
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted left by the number of bits the elements in vector `b`
+ /// (two signed 64-bit integer numbers) specify modulo the size of the
+ /// element in bits. The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sll.d))]
+ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_sll_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Shift Left
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted left by `imm4` bits.
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(slli.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_slli_b(a: v16i8, imm4: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_slli_b(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Shift Left
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted left by `imm3` bits.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(slli.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_slli_h(a: v8i16, imm3: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_slli_h(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Shift Left
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted left by `imm2` bits.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(slli.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_slli_w(a: v4i32, imm2: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_slli_w(a, $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Immediate Shift Left
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted left by `imm1` bits.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(slli.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_slli_d(a: v2i64, imm1: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_slli_d(a, $imm1)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// GPR Element Splat
+ ///
+ /// Replicate vector `a` (sixteen signed 8-bit integer numbers)
+ /// element with index given by GPR `b` to all elements in vector
+ /// (sixteen signed 8-bit integer numbers) GPR `b` value is interpreted
+ /// modulo the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splat.b))]
+ pub unsafe fn __msa_splat_b(a: v16i8, b: i32) -> v16i8 {
+     msa_splat_b(a, mem::transmute(b))
+ }
+ 
+ /// GPR Element Splat
+ ///
+ /// Replicate vector `a` (eight signed 16-bit integer numbers)
+ /// element with index given by GPR `b` to all elements in vector
+ /// (eight signed 16-bit integer numbers) GPR `b` value is interpreted
+ /// modulo the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splat.h))]
+ pub unsafe fn __msa_splat_h(a: v8i16, b: i32) -> v8i16 {
+     msa_splat_h(a, mem::transmute(b))
+ }
+ 
+ /// GPR Element Splat
+ ///
+ /// Replicate vector `a` (four signed 32-bit integer numbers)
+ /// element with index given by GPR `b` to all elements in vector
+ /// (four signed 32-bit integer numbers) GPR `b` value is interpreted
+ /// modulo the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splat.w))]
+ pub unsafe fn __msa_splat_w(a: v4i32, b: i32) -> v4i32 {
+     msa_splat_w(a, mem::transmute(b))
+ }
+ 
+ /// GPR Element Splat
+ ///
+ /// Replicate vector `a` (two signed 64-bit integer numbers)
+ /// element with index given by GPR `b` to all elements in vector
+ /// (two signed 64-bit integer numbers) GPR `b` value is interpreted
+ /// modulo the number of data format df elements in the destination vector.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splat.d))]
+ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 {
+     msa_splat_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Element Splat
+ ///
+ /// Replicate element `imm4` in vector `a` (sixteen signed 8-bit integer numbers)
+ /// to all elements in vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splati.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_splati_b(a: v16i8, imm4: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_splati_b(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Element Splat
+ ///
+ /// Replicate element `imm3` in vector `a` (eight signed 16-bit integer numbers)
+ /// to all elements in vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splati.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_splati_h(a: v8i16, imm3: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_splati_h(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Element Splat
+ ///
+ /// Replicate element `imm2` in vector `a` (four signed 32-bit integer numbers)
+ /// to all elements in vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splati.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_splati_w(a: v4i32, imm2: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_splati_w(a, $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Immediate Element Splat
+ ///
+ /// Replicate element `imm1` in vector `a` (two signed 64-bit integer numbers)
+ /// to all elements in vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(splati.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_splati_d(a: v2i64, imm1: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_splati_d(a, $imm1)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// Vector Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sra.b))]
+ pub unsafe fn __msa_sra_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_sra_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (eight signed 16-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sra.h))]
+ pub unsafe fn __msa_sra_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_sra_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (four signed 32-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sra.w))]
+ pub unsafe fn __msa_sra_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_sra_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (two signed 64-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(sra.d))]
+ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_sra_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right arithmetic by `imm3` bits.
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srai.b, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srai_b(a: v16i8, imm3: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_srai_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right arithmetic by `imm4` bits.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srai.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srai_h(a: v8i16, imm4: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_srai_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right arithmetic by `imm5` bits.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srai.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srai_w(a: v4i32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_srai_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Shift Right Arithmetic
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right arithmetic by `imm6` bits.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srai.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srai_d(a: v2i64, imm6: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_srai_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Vector Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srar.b))]
+ pub unsafe fn __msa_srar_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_srar_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (eight signed 16-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srar.h))]
+ pub unsafe fn __msa_srar_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_srar_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (four signed 32-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srar.w))]
+ pub unsafe fn __msa_srar_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_srar_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right arithmetic by the number of bits the elements in vector `b`
+ /// (two signed 64-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srar.d))]
+ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_srar_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right arithmetic by `imm3` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srari.b, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srari_b(a: v16i8, imm3: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_srari_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right arithmetic by `imm4` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srari.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srari_h(a: v8i16, imm4: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_srari_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right arithmetic by `imm5` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srari.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srari_w(a: v4i32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_srari_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Shift Right Arithmetic Rounded
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right arithmetic by `imm6` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srari.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srari_d(a: v2i64, imm6: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_srari_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Vector Shift Right Logical
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srl.b))]
+ pub unsafe fn __msa_srl_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_srl_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Logical
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (eight signed 16-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srl.h))]
+ pub unsafe fn __msa_srl_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_srl_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Logical
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (four signed 32-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srl.w))]
+ pub unsafe fn __msa_srl_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_srl_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Logical
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (two signed 64-bit integer numbers) specify modulo the size of the
+ /// element in bits.The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srl.d))]
+ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_srl_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Shift Right Logical
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right logical by `imm4` bits.
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srli.b, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srli_b(a: v16i8, imm4: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_srli_b(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Shift Right Logical
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right logical by `imm3` bits.
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srli.h, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srli_h(a: v8i16, imm3: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_srli_h(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Shift Right Logical
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right logical by `imm2` bits.
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srli.w, imm2 = 0b11))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srli_w(a: v4i32, imm2: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             msa_srli_w(a, $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Immediate Shift Right Logical
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right logical by `imm1` bits.
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srli.d, imm1 = 0b1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srli_d(a: v2i64, imm1: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm1:expr) => {
+             msa_srli_d(a, $imm1)
+         };
+     }
+     constify_imm1!(imm1, call)
+ }
+ 
+ /// Vector Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (sixteen signed 8-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlr.b))]
+ pub unsafe fn __msa_srlr_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_srlr_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (eight signed 16-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlr.h))]
+ pub unsafe fn __msa_srlr_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_srlr_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (four signed 32-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlr.w))]
+ pub unsafe fn __msa_srlr_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_srlr_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right logical by the number of bits the elements in vector `b`
+ /// (two signed 64-bit integer numbers) specify modulo the size of the
+ /// element in bits.The most significant discarded bit is added to the shifted
+ /// value (for rounding) and the result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlr.d))]
+ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_srlr_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are shifted right logical by `imm6` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlri.b, imm3 = 0b111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srlri_b(a: v16i8, imm3: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             msa_srlri_b(a, $imm3)
+         };
+     }
+     constify_imm3!(imm3, call)
+ }
+ 
+ /// Immediate Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (eight signed 16-bit integer numbers)
+ /// are shifted right logical by `imm6` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlri.h, imm4 = 0b1111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srlri_h(a: v8i16, imm4: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             msa_srlri_h(a, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Immediate Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (four signed 32-bit integer numbers)
+ /// are shifted right logical by `imm6` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlri.w, imm5 = 0b11111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srlri_w(a: v4i32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_srlri_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Shift Right Logical Rounded
+ ///
+ /// The elements in vector `a` (two signed 64-bit integer numbers)
+ /// are shifted right logical by `imm6` bits.The most significant
+ /// discarded bit is added to the shifted value (for rounding) and
+ /// the result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(srlri.d, imm6 = 0b111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_srlri_d(a: v2i64, imm6: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm6:expr) => {
+             msa_srlri_d(a, $imm6)
+         };
+     }
+     constify_imm6!(imm6, call)
+ }
+ 
+ /// Vector Store
+ ///
+ /// The WRLEN / 8 bytes in vector `a` (sixteen signed 8-bit integer numbers)
+ /// are stored as elements of data format df at the effective memory location
+ /// addressed by the base `mem_addr` and the 10-bit signed immediate offset `imm_s10`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(st.b, imm_s10 = 0b1111111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8, imm_s10: i32) -> () {
+     macro_rules! call {
+         ($imm_s10:expr) => {
+             msa_st_b(a, mem_addr, $imm_s10)
+         };
+     }
+     constify_imm_s10!(imm_s10, call)
+ }
+ 
+ /// Vector Store
+ ///
+ /// The WRLEN / 8 bytes in vector `a` (eight signed 16-bit integer numbers)
+ /// are stored as elements of data format df at the effective memory location
+ /// addressed by the base `mem_addr` and the 11-bit signed immediate offset `imm_s11`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(st.h, imm_s11 = 0b11111111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8, imm_s11: i32) -> () {
+     macro_rules! call {
+         ($imm_s11:expr) => {
+             msa_st_h(a, mem_addr, $imm_s11)
+         };
+     }
+     constify_imm_s11!(imm_s11, call)
+ }
+ 
+ /// Vector Store
+ ///
+ /// The WRLEN / 8 bytes in vector `a` (four signed 32-bit integer numbers)
+ /// are stored as elements of data format df at the effective memory location
+ /// addressed by the base `mem_addr` and the 12-bit signed immediate offset `imm_s12`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(st.w, imm_s12 = 0b111111111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8, imm_s12: i32) -> () {
+     macro_rules! call {
+         ($imm_s12:expr) => {
+             msa_st_w(a, mem_addr, $imm_s12)
+         };
+     }
+     constify_imm_s12!(imm_s12, call)
+ }
+ 
+ /// Vector Store
+ ///
+ /// The WRLEN / 8 bytes in vector `a` (two signed 64-bit integer numbers)
+ /// are stored as elements of data format df at the effective memory location
+ /// addressed by the base `mem_addr` and the 13-bit signed immediate offset `imm_s13`.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(st.d, imm_s13 = 0b1111111111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn __msa_st_d(a: v2i64, mem_addr: *mut u8, imm_s13: i32) -> () {
+     macro_rules! call {
+         ($imm_s13:expr) => {
+             msa_st_d(a, mem_addr, $imm_s13)
+         };
+     }
+     constify_imm_s13!(imm_s13, call)
+ }
+ 
+ /// Vector Signed Saturated Subtract of Signed Values
+ ///
+ /// The elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (sixteen signed 8-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_s.b))]
+ pub unsafe fn __msa_subs_s_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_subs_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Signed Values
+ ///
+ /// The elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (eight signed 16-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_s.h))]
+ pub unsafe fn __msa_subs_s_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_subs_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Signed Values
+ ///
+ /// The elements in vector `b` (four signed 32-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (four signed 32-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_s.w))]
+ pub unsafe fn __msa_subs_s_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_subs_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Signed Values
+ ///
+ /// The elements in vector `b` (two signed 64-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (two signed 64-bit integer numbers).
+ /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest
+ /// representable signed values before writing the result to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_s.d))]
+ pub unsafe fn __msa_subs_s_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_subs_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Unsigned Values
+ ///
+ /// The elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// Unsigned arithmetic is performed and under-flows clamp to 0 before writing
+ /// the result to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_u.b))]
+ pub unsafe fn __msa_subs_u_b(a: v16u8, b: v16u8) -> v16u8 {
+     msa_subs_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Unsigned Values
+ ///
+ /// The elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (eight unsigned 16-bit integer numbers).
+ /// Unsigned arithmetic is performed and under-flows clamp to 0 before writing
+ /// the result to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_u.h))]
+ pub unsafe fn __msa_subs_u_h(a: v8u16, b: v8u16) -> v8u16 {
+     msa_subs_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Unsigned Values
+ ///
+ /// The elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (four unsigned 32-bit integer numbers).
+ /// Unsigned arithmetic is performed and under-flows clamp to 0 before writing
+ /// the result to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_u.w))]
+ pub unsafe fn __msa_subs_u_w(a: v4u32, b: v4u32) -> v4u32 {
+     msa_subs_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Unsigned Values
+ ///
+ /// The elements in vector `b` (two unsigned 64-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (two unsigned 64-bit integer numbers).
+ /// Unsigned arithmetic is performed and under-flows clamp to 0 before writing
+ /// the result to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subs_u.d))]
+ pub unsafe fn __msa_subs_u_d(a: v2u64, b: v2u64) -> v2u64 {
+     msa_subs_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Signed from Unsigned
+ ///
+ /// The signed elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The signed result is unsigned saturated and written to
+ /// to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsus_u.b))]
+ pub unsafe fn __msa_subsus_u_b(a: v16u8, b: v16i8) -> v16u8 {
+     msa_subsus_u_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Signed from Unsigned
+ ///
+ /// The signed elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (eight unsigned 16-bit integer numbers).
+ /// The signed result is unsigned saturated and written to
+ /// to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsus_u.h))]
+ pub unsafe fn __msa_subsus_u_h(a: v8u16, b: v8i16) -> v8u16 {
+     msa_subsus_u_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Signed from Unsigned
+ ///
+ /// The signed elements in vector `b` (four signed 6432it integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (four unsigned 32-bit integer numbers).
+ /// The signed result is unsigned saturated and written to
+ /// to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsus_u.w))]
+ pub unsafe fn __msa_subsus_u_w(a: v4u32, b: v4i32) -> v4u32 {
+     msa_subsus_u_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Unsigned Saturated Subtract of Signed from Unsigned
+ ///
+ /// The signed elements in vector `b` (two signed 64-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (two unsigned 64-bit integer numbers).
+ /// The signed result is unsigned saturated and written to
+ /// to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsus_u.d))]
+ pub unsafe fn __msa_subsus_u_d(a: v2u64, b: v2i64) -> v2u64 {
+     msa_subsus_u_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Unsigned Values
+ ///
+ /// The unsigned elements in vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers).
+ /// The signed result is signed saturated and written to
+ /// to vector (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsuu_s.b))]
+ pub unsafe fn __msa_subsuu_s_b(a: v16u8, b: v16u8) -> v16i8 {
+     msa_subsuu_s_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Unsigned Values
+ ///
+ /// The unsigned elements in vector `b` (eight unsigned 16-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (eight unsigned 16-bit integer numbers).
+ /// The signed result is signed saturated and written to
+ /// to vector (eight unsigned 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsuu_s.h))]
+ pub unsafe fn __msa_subsuu_s_h(a: v8u16, b: v8u16) -> v8i16 {
+     msa_subsuu_s_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Unsigned Values
+ ///
+ /// The unsigned elements in vector `b` (four unsigned 32-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (four unsigned 32-bit integer numbers).
+ /// The signed result is signed saturated and written to
+ /// to vector (four unsigned 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsuu_s.w))]
+ pub unsafe fn __msa_subsuu_s_w(a: v4u32, b: v4u32) -> v4i32 {
+     msa_subsuu_s_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Signed Saturated Subtract of Unsigned Values
+ ///
+ /// The unsigned elements in vector `b` (two unsigned 64-bit integer numbers)
+ /// are subtracted from the unsigned elements in vector `a` (two unsigned 64-bit integer numbers).
+ /// The signed result is signed saturated and written to
+ /// to vector (two unsigned 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subsuu_s.d))]
+ pub unsafe fn __msa_subsuu_s_d(a: v2u64, b: v2u64) -> v2i64 {
+     msa_subsuu_s_d(a, mem::transmute(b))
+ }
+ 
+ /// Vector Subtract
+ ///
+ /// The elements in vector `b` (sixteen signed 8-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subv.b))]
+ pub unsafe fn __msa_subv_b(a: v16i8, b: v16i8) -> v16i8 {
+     msa_subv_b(a, mem::transmute(b))
+ }
+ 
+ /// Vector Subtract
+ ///
+ /// The elements in vector `b` (eight signed 16-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subv.h))]
+ pub unsafe fn __msa_subv_h(a: v8i16, b: v8i16) -> v8i16 {
+     msa_subv_h(a, mem::transmute(b))
+ }
+ 
+ /// Vector Subtract
+ ///
+ /// The elements in vector `b` (four signed 32-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subv.w))]
+ pub unsafe fn __msa_subv_w(a: v4i32, b: v4i32) -> v4i32 {
+     msa_subv_w(a, mem::transmute(b))
+ }
+ 
+ /// Vector Subtract
+ ///
+ /// The elements in vector `b` (two signed 64-bit integer numbers)
+ /// are subtracted from the elements in vector `a` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subv.d))]
+ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 {
+     msa_subv_d(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Subtract
+ ///
+ /// The 5-bit immediate unsigned value `imm5`
+ /// are subtracted from the elements in vector `a` (sixteen signed 8-bit integer numbers).
+ /// The result is written to vector (sixteen signed 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subvi.b, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_subvi_b(a: v16i8, imm5: i32) -> v16i8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_subvi_b(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Subtract
+ ///
+ /// The 5-bit immediate unsigned value `imm5`
+ /// are subtracted from the elements in vector `a` (eight signed 16-bit integer numbers).
+ /// The result is written to vector (eight signed 16-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subvi.h, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_subvi_h(a: v8i16, imm5: i32) -> v8i16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_subvi_h(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Subtract
+ ///
+ /// The 5-bit immediate unsigned value `imm5`
+ /// are subtracted from the elements in vector `a` (four signed 32-bit integer numbers).
+ /// The result is written to vector (four signed 32-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subvi.w, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_subvi_w(a: v4i32, imm5: i32) -> v4i32 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_subvi_w(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Immediate Subtract
+ ///
+ /// The 5-bit immediate unsigned value `imm5`
+ /// are subtracted from the elements in vector `a` (two signed 64-bit integer numbers).
+ /// The result is written to vector (two signed 64-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(subvi.d, imm5 = 0b10111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_subvi_d(a: v2i64, imm5: i32) -> v2i64 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             msa_subvi_d(a, $imm5)
+         };
+     }
+     constify_imm5!(imm5, call)
+ }
+ 
+ /// Vector Data Preserving Shuffle
+ ///
+ /// The vector shuffle instructions selectively copy data elements from the
+ /// concatenation of vectors `b` (sixteen signed 8-bit integer numbers)
+ /// and `c` (sixteen signed 8-bit integer numbers) in to vector `a`
+ /// (sixteen signed 8-bit integer numbers) based on the corresponding control element in `a`.
+ /// The least significant 6 bits in `a` control elements modulo the number of elements in
+ /// the concatenated vectors `b`, `a` specify the index of the source element.
+ /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination element is set to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(vshf.b))]
+ pub unsafe fn __msa_vshf_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8 {
+     msa_vshf_b(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Data Preserving Shuffle
+ ///
+ /// The vector shuffle instructions selectively copy data elements from the
+ /// concatenation of vectors `b` (eight signed 16-bit integer numbers)
+ /// and `c` (eight signed 16-bit integer numbers) in to vector `a`
+ /// (eight signed 16-bit integer numbers) based on the corresponding control element in `a`.
+ /// The least significant 6 bits in `a` control elements modulo the number of elements in
+ /// the concatenated vectors `b`, `a` specify the index of the source element.
+ /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination element is set to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(vshf.h))]
+ pub unsafe fn __msa_vshf_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 {
+     msa_vshf_h(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Data Preserving Shuffle
+ ///
+ /// The vector shuffle instructions selectively copy data elements from the
+ /// concatenation of vectors `b` (four signed 32-bit integer numbers)
+ /// and `c` (four signed 32-bit integer numbers) in to vector `a`
+ /// (four signed 32-bit integer numbers) based on the corresponding control element in `a`.
+ /// The least significant 6 bits in `a` control elements modulo the number of elements in
+ /// the concatenated vectors `b`, `a` specify the index of the source element.
+ /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination element is set to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(vshf.w))]
+ pub unsafe fn __msa_vshf_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 {
+     msa_vshf_w(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Data Preserving Shuffle
+ ///
+ /// The vector shuffle instructions selectively copy data elements from the
+ /// concatenation of vectors `b` (two signed 64-bit integer numbers)
+ /// and `c` (two signed 64-bit integer numbers) in to vector `a`
+ /// (two signed 64-bit integer numbers) based on the corresponding control element in `a`.
+ /// The least significant 6 bits in `a` control elements modulo the number of elements in
+ /// the concatenated vectors `b`, `a` specify the index of the source element.
+ /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination element is set to 0.
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(vshf.d))]
+ pub unsafe fn __msa_vshf_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64 {
+     msa_vshf_d(a, mem::transmute(b), c)
+ }
+ 
+ /// Vector Logical Exclusive Or
+ ///
+ /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers)
+ /// in a bitwise logical XOR operation. The result is written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(xor.v))]
+ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 {
+     msa_xor_v(a, mem::transmute(b))
+ }
+ 
+ /// Immediate Logical Exclusive Or
+ ///
+ /// Each byte of vector `a` (sixteen unsigned 8-bit integer numbers)
+ /// is combined with the 8-bit immediate `imm8`
+ /// in a bitwise logical XOR operation. The result is written to vector
+ /// (sixteen unsigned 8-bit integer numbers).
+ ///
+ #[inline]
+ #[target_feature(enable = "msa")]
+ #[cfg_attr(test, assert_instr(xori.b, imm8 = 0b11111111))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn __msa_xori_b(a: v16u8, imm8: i32) -> v16u8 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             msa_xori_b(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::{
+         core_arch::{mips::msa::*, simd::*},
+         mem,
+     };
+     use std::{f32, f64};
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_add_a_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -4, -3, -2, -1,
+             -4, -3, -2, -1,
+             -4, -3, -2, -1,
+             -4, -3, -2, -1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             5, 5, 5, 5,
+             5, 5, 5, 5, 
+             5, 5, 5, 5, 
+             5, 5, 5, 5
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_add_a_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_add_a_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-4, -3, -2, -1, -4, -3, -2, -1);
+         #[rustfmt::skip]
+         let r = i16x8::new(5, 5, 5, 5, 5, 5, 5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_add_a_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_add_a_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(-4, -3, -2, -1);
+         #[rustfmt::skip]
+         let r = i32x4::new(5, 5, 5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_add_a_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_add_a_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(-4, -3);
+         #[rustfmt::skip]
+         let r = i64x2::new(5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_add_a_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_a_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, i8::MAX, 100, i8::MAX,
+             100, i8::MAX, 100, i8::MAX,
+             100, i8::MAX, 100, i8::MAX,
+             100, i8::MAX, 100, i8::MAX
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -4, -3, -2, -100,
+             -4, -3, -2, -100,
+             -4, -3, -2, -100,
+             -4, -3, -2, -100
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             104, 127, 102, 127, 
+             104, 127, 102, 127, 
+             104, 127, 102, 127, 
+             104, 127, 102, 127
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_a_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_a_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             100, i16::MAX, 100, i16::MAX, 
+             100, i16::MAX, 100, i16::MAX
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(-4, -3, -2, -1, -4, -3, -2, -1);
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             104, i16::MAX, 102, i16::MAX,
+             104, i16::MAX, 102, i16::MAX
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_a_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_a_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, i32::MAX, 100, i32::MAX);
+         #[rustfmt::skip]
+         let b = i32x4::new(-4, -3, -2, -1);
+         #[rustfmt::skip]
+         let r = i32x4::new(104, i32::MAX, 102, i32::MAX);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_a_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_a_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MAX);
+         #[rustfmt::skip]
+         let b = i64x2::new(-4, -3);
+         #[rustfmt::skip]
+         let r = i64x2::new(104, i64::MAX);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_a_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, i8::MIN, 100, i8::MAX,
+             100, i8::MIN, 100, i8::MAX,
+             100, i8::MIN, 100, i8::MAX,
+             100, i8::MIN, 100, i8::MAX
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -4, -3, -2, 100,
+             -4, -3, -2, 100,
+             -4, -3, -2, 100,
+             -4, -3, -2, 100
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             96, i8::MIN, 98, i8::MAX, 
+             96, i8::MIN, 98, i8::MAX, 
+             96, i8::MIN, 98, i8::MAX, 
+             96, i8::MIN, 98, i8::MAX
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             100, i16::MIN, 100, i16::MAX, 
+             100, i16::MIN, 100, i16::MAX
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(-4, -3, -2, 1, -4, -3, -2, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             96, i16::MIN, 98, i16::MAX, 
+             96, i16::MIN, 98, i16::MAX
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, i32::MAX, 100, i32::MIN);
+         #[rustfmt::skip]
+         let b = i32x4::new(-4, 3, -2, -1);
+         #[rustfmt::skip]
+         let r = i32x4::new(96, i32::MAX, 98, i32::MIN);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MIN);
+         #[rustfmt::skip]
+         let b = i64x2::new(-4, -3);
+         #[rustfmt::skip]
+         let r = i64x2::new(96, i64::MIN);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             4, 3, 2, 100,
+             4, 3, 2, 100,
+             4, 3, 2, 100,
+             4, 3, 2, 100
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             104, u8::MAX, 102, u8::MAX, 
+             104, u8::MAX, 102, u8::MAX, 
+             104, u8::MAX, 102, u8::MAX, 
+             104, u8::MAX, 102, u8::MAX
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             100, u16::MAX, 100, u16::MAX, 
+             100, u16::MAX, 100, u16::MAX
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(4, 3, 2, 1, 4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = u16x8::new(
+             104, u16::MAX, 102, u16::MAX, 
+             104, u16::MAX, 102, u16::MAX
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(100, u32::MAX, 100, u32::MAX);
+         #[rustfmt::skip]
+         let b = u32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = u32x4::new(104, u32::MAX, 102, u32::MAX);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_adds_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(100, u64::MAX);
+         #[rustfmt::skip]
+         let b = u64x2::new(4, 3);
+         #[rustfmt::skip]
+         let r = u64x2::new(104, u64::MAX);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_adds_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addv_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, i8::MIN, 100, i8::MAX,
+             100, i8::MIN, 100, i8::MAX,
+             100, i8::MIN, 100, i8::MAX,
+             100, i8::MIN, 100, i8::MAX
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -4, -3, -2, 100,
+             -4, -3, -2, 100,
+             -4, -3, -2, 100,
+             -4, -3, -2, 100
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             96, 125, 98, -29, 
+             96, 125, 98, -29, 
+             96, 125, 98, -29, 
+             96, 125, 98, -29
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_addv_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addv_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             100, i16::MIN, 100, i16::MAX, 
+             100, i16::MIN, 100, i16::MAX
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(-4, -3, -2, 1, -4, -3, -2, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(96, 32765, 98, -32768, 96, 32765, 98, -32768);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_addv_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addv_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, i32::MAX, 100, i32::MIN);
+         #[rustfmt::skip]
+         let b = i32x4::new(-4, 3, -2, -1);
+         #[rustfmt::skip]
+         let r = i32x4::new(96, -2147483646, 98, 2147483647);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_addv_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addv_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MIN);
+         #[rustfmt::skip]
+         let b = i64x2::new(-4, -3);
+         #[rustfmt::skip]
+         let r = i64x2::new(96, 9223372036854775805);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_addv_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addvi_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, i8::MAX, 100, i8::MAX,
+             100, i8::MAX, 100, i8::MAX,
+             100, i8::MAX, 100, i8::MAX,
+             100, i8::MAX, 100, i8::MAX
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             103, -126, 103, -126, 
+             103, -126, 103, -126, 
+             103, -126, 103, -126, 
+             103, -126, 103, -126
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_addvi_b(mem::transmute(a), 67)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addvi_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 3276, -100, -127, 
+             i16::MAX, 3276, -100, -127
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             -32766, 3279, -97, -124, 
+             -32766, 3279, -97, -124
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_addvi_h(mem::transmute(a), 67)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addvi_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, i32::MAX, 100, i32::MIN);
+         #[rustfmt::skip]
+         let r = i32x4::new(103, -2147483646, 103, -2147483645);
+ 
+         assert_eq!(r, mem::transmute(__msa_addvi_w(mem::transmute(a), 67)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_addvi_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MIN);
+         #[rustfmt::skip]
+         let r = i64x2::new(117, -9223372036854775791);
+ 
+         assert_eq!(r, mem::transmute(__msa_addvi_d(mem::transmute(a), 17)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_and_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX
+     );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             4, 3, 2, 100,
+             4, 3, 2, 100,
+             4, 3, 2, 100,
+             4, 3, 2, 100
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             4, 3, 0, 100, 
+             4, 3, 0, 100, 
+             4, 3, 0, 100, 
+             4, 3, 0, 100
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_and_v(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_andi_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX,
+             100, u8::MAX, 100, u8::MAX
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             4, 5, 4, 5, 
+             4, 5, 4, 5, 
+             4, 5, 4, 5, 
+             4, 5, 4, 5
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_andi_b(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -1, -2, -3, -4,
+             -1, -2, -3, -4,
+             -1, -2, -3, -4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             5, 5, 5, 5, 
+             5, 5, 5, 5, 
+             5, 5, 5, 5, 
+             5, 5, 5, 5
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-1, -2, -3, -4, -1, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, -7, -8, -9, -6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = i16x8::new(5, 5, 5, 5, 5, 5, 5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(-6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = i32x4::new(5, 5, 5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, -2);
+         #[rustfmt::skip]
+         let b = i64x2::new(-6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             5, 5, 5, 5, 
+             5, 5, 5, 5, 
+             5, 5, 5, 5, 
+             5, 5, 5, 5
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(5, 5, 5, 5, 5, 5, 5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(5, 5, 5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_asub_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(5, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_asub_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -1, -2, -3, -4,
+             -1, -2, -3, -4,
+             -1, -2, -3, -4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             6, -7, 8, -9,
+             6, -7, 8, -9,
+             6, -7, 8, -9,
+             6, -7, 8, -9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             2, -5, 2, -7, 
+             2, -5, 2, -7, 
+             2, -5, 2, -7, 
+             2, -5, 2, -7
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-1, -2, -3, -4, -1, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(6, -7, 8, -9, 6, -7, 8, -9);
+         #[rustfmt::skip]
+         let r = i16x8::new(2, -5, 2, -7, 2, -5, 2, -7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, -7, 8, -9);
+         #[rustfmt::skip]
+         let r = i32x4::new(2, -5, 2, -7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, -2);
+         #[rustfmt::skip]
+         let b = i64x2::new(-6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(-4, -5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             3, 4, 5, 6, 
+             3, 4, 5, 6, 
+             3, 4, 5, 6, 
+             3, 4, 5, 6
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(3, 4, 5, 6, 3, 4, 5, 6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(3, 4, 5, 6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ave_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(3, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ave_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -1, -2, 3, -4,
+             -1, -2, 3, -4,
+             -1, -2, 3, -4,
+             -1, -2, 3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, 7, -8, -9,
+             -6, 7, -8, -9,
+             -6, 7, -8, -9,
+             -6, 7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -3, 3, -2, -6, 
+             -3, 3, -2, -6, 
+             -3, 3, -2, -6, 
+             -3, 3, -2, -6
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-1, -2, 3, -4, -1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, 7, -8, -9, -6, 7, -8, -9);
+         #[rustfmt::skip]
+         let r = i16x8::new(-3, 3, -2, -6, -3, 3, -2, -6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(-6, 7, -8, -9);
+         #[rustfmt::skip]
+         let r = i32x4::new(-3, 3, -2, -6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, -2);
+         #[rustfmt::skip]
+         let b = i64x2::new(-6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(-3, -4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             4, 5, 6, 7, 
+             4, 5, 6, 7, 
+             4, 5, 6, 7, 
+             4, 5, 6, 7
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(4, 5, 6, 7, 4, 5, 6, 7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(4, 5, 6, 7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_aver_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(4, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_aver_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclr_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             191, 27, 54, 1, 
+             191, 27, 54, 1, 
+             191, 27, 54, 1, 
+             191, 27, 54, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bclr_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclr_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(255, 155, 55, 1, 255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(191, 27, 55, 1, 191, 27, 55, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bclr_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclr_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(191, 27, 55, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bclr_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclr_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(255, 155);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(191, 27);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bclr_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclri_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             247, 147, 55, 1, 
+             247, 147, 55, 1, 
+             247, 147, 55, 1, 
+             247, 147, 55, 1
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_bclri_b(mem::transmute(a), 3)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclri_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(2155, 1155, 155, 1, 2155, 1155, 155, 1);
+         #[rustfmt::skip]
+         let r = u16x8::new(107, 1155, 155, 1, 107, 1155, 155, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_bclri_h(mem::transmute(a), 11)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclri_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(211111155, 111111155, 11111155, 1);
+         #[rustfmt::skip]
+         let r = u32x4::new(202722547, 102722547, 2722547, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_bclri_w(mem::transmute(a), 23)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bclri_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(211111111155, 11111111111111155);
+         #[rustfmt::skip]
+         let r = u64x2::new(73672157683, 11110973672157683);
+ 
+         assert_eq!(r, mem::transmute(__msa_bclri_d(mem::transmute(a), 37)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsl_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             1, 3, 5, 9,
+             1, 3, 5, 9,
+             1, 3, 5, 9,
+             1, 3, 5, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             63, 11, 11, 1, 
+             63, 11, 11, 1, 
+             63, 11, 11, 1, 
+             63, 11, 11, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsl_b(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsl_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             32767, 16384, 8192, 4096, 
+             32767, 16384, 8192, 4096
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             21656, 5273, 7081, 2985, 
+             21656, 5273, 7081, 2985
+         );
+         #[rustfmt::skip]
+         let c = u16x8::new(
+             3, 7, 9, 13, 
+             15, 17, 21, 23
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(
+             24575, 5120, 7040, 2984, 
+             21656, 0, 6144, 2816
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsl_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsl_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(2147483647, 536870912, 67108864, 8388608);
+         #[rustfmt::skip]
+         let b = u32x4::new(1036372536, 259093134, 78219975, 1119499719);
+         #[rustfmt::skip]
+         let c = u32x4::new(11, 15, 31, 37);
+         #[rustfmt::skip]
+         let r = u32x4::new(1037041663, 259063808, 78219975, 1082130432);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsl_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsl_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(8006399338, 2882303762);
+         #[rustfmt::skip]
+         let b = u64x2::new(9223372036854775805, 536870912);
+         #[rustfmt::skip]
+         let c = u64x2::new(12, 48);
+         #[rustfmt::skip]
+         let r = u64x2::new(9221120245047489898, 536901394);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsl_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsli_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             7, 7, 11, 9, 
+             7, 7, 11, 9, 
+             7, 7, 11, 9, 
+             7, 7, 11, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsli_b(mem::transmute(a), mem::transmute(b), 5))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsli_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             32767, 16384, 8192, 4096, 
+             32767, 16384, 8192, 4096
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             21656, 5273, 7081, 2985, 
+             21656, 5273, 7081, 2985
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(
+             21659, 5272, 7080, 2984, 
+             21659, 5272, 7080, 2984
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsli_h(mem::transmute(a), mem::transmute(b), 13))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsli_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(2147483647, 536870912, 67108864, 8388608);
+         #[rustfmt::skip]
+         let b = u32x4::new(1036372536, 259093134, 78219975, 1119499719);
+         #[rustfmt::skip]
+         let r = u32x4::new(1036386303, 259080192, 78217216, 1119485952);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsli_w(mem::transmute(a), mem::transmute(b), 17))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsli_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(8006399338, 2882303762);
+         #[rustfmt::skip]
+         let b = u64x2::new(9223372036854775805, 536870912);
+         #[rustfmt::skip]
+         let r = u64x2::new(9223372036854773098, 536901394);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsli_d(mem::transmute(a), mem::transmute(b), 48))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsr_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             1, 3, 5, 9,
+             1, 3, 5, 9,
+             1, 3, 5, 9,
+             1, 3, 5, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             254, 151, 8, 1, 
+             254, 151, 8, 1, 
+             254, 151, 8, 1, 
+             254, 151, 8, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsr_b(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsr_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             32767, 16384, 8192, 4096, 
+             32767, 16384, 8192, 4096
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             21656, 5273, 7081, 2985, 
+             21656, 5273, 7081, 2985
+         );
+         #[rustfmt::skip]
+         let c = u16x8::new(
+             3, 7, 9, 13, 
+             15, 17, 21, 23
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(
+             32760, 16537, 9129, 2985, 
+             21656, 16385, 8233, 4265
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsr_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsr_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(2147483647, 536870912, 67108864, 8388608);
+         #[rustfmt::skip]
+         let b = u32x4::new(1036372536, 259093134, 78219975, 1119499719);
+         #[rustfmt::skip]
+         let c = u32x4::new(11, 15, 31, 37);
+         #[rustfmt::skip]
+         let r = u32x4::new(2147482168, 536900238, 78219975, 8388615);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsr_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsr_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(8006399338, 2882303762);
+         #[rustfmt::skip]
+         let b = u64x2::new(9223372036854775805, 536870912);
+         #[rustfmt::skip]
+         let c = u64x2::new(12, 48);
+         #[rustfmt::skip]
+         let r = u64x2::new(8006402045, 536870912);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsr_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsri_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             198, 135, 8, 9, 
+             198, 135, 8, 9, 
+             198, 135, 8, 9, 
+             198, 135, 8, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsri_b(mem::transmute(a), mem::transmute(b), 5))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsri_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             32767, 16384, 8192, 4096, 
+             32767, 16384, 8192, 4096
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             21656, 5273, 7081, 2985, 
+             21656, 5273, 7081, 2985
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(
+             21656, 21657, 7081, 2985, 
+             21656, 21657, 7081, 2985
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsri_h(mem::transmute(a), mem::transmute(b), 13))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsri_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(2147483647, 536870912, 67108864, 8388608);
+         #[rustfmt::skip]
+         let b = u32x4::new(1036372536, 259093134, 78219975, 1119499719);
+         #[rustfmt::skip]
+         let r = u32x4::new(2147338808, 536965774, 67209927, 8533447);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsri_w(mem::transmute(a), mem::transmute(b), 17))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_binsri_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(8006399338, 2882303762);
+         #[rustfmt::skip]
+         let b = u64x2::new(9223372036854775805, 536870912);
+         #[rustfmt::skip]
+         let r = u64x2::new(562949953421309, 536870912);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_binsri_d(mem::transmute(a), mem::transmute(b), 48))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bmnz_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             3, 5, 7, 1,
+             3, 5, 7, 1,
+             3, 5, 7, 1,
+             3, 5, 7, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             254, 159, 48, 1, 
+             254, 159, 48, 1, 
+             254, 159, 48, 1, 
+             254, 159, 48, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bmnz_v(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bmnzi_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, u8::MAX, 155, 55,
+             1, u8::MAX, 155, 55,
+             1, u8::MAX, 155, 55,
+             1, u8::MAX, 155, 55
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             249, 159, 51, 7, 
+             249, 159, 51, 7, 
+             249, 159, 51, 7, 
+             249, 159, 51, 7
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bmnzi_b(mem::transmute(a), mem::transmute(b), 7))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bmz_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             3, 5, 7, 1,
+             3, 5, 7, 1,
+             3, 5, 7, 1,
+             3, 5, 7, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             7, 3, 15, 9, 
+             7, 3, 15, 9, 
+             7, 3, 15, 9, 
+             7, 3, 15, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bmz_v(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bmzi_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1,
+             u8::MAX, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 255, 155, 55,
+             1, 255, 155, 55,
+             1, 255, 155, 55,
+             1, 255, 155, 55
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             7, 251, 159, 49, 
+             7, 251, 159, 49, 
+             7, 251, 159, 49, 
+             7, 251, 159, 49
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bmzi_b(mem::transmute(a), mem::transmute(b), 7))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bneg_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             191, 27, 54, 3, 
+             191, 27, 54, 3, 
+             191, 27, 54, 3, 
+             191, 27, 54, 3
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bneg_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bneg_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(255, 155, 55, 1, 255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(191, 27, 311, 513, 191, 27, 311, 513);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bneg_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bneg_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(191, 27, 311, 513);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bneg_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bneg_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(255, 155);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(191, 27);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bneg_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnegi_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             50, 100, 127, u8::MAX,
+             50, 100, 127, u8::MAX,
+             50, 100, 127, u8::MAX,
+             50, 100, 127, u8::MAX
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             34, 116, 111, 239, 
+             34, 116, 111, 239, 
+             34, 116, 111, 239, 
+             34, 116, 111, 239
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_bnegi_b(mem::transmute(a), 4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnegi_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             32767, 3276, 100, 127,
+             32767, 3276, 100, 127
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(
+             30719, 1228, 2148, 2175, 
+             30719, 1228, 2148, 2175
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_bnegi_h(mem::transmute(a), 11)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnegi_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(100, 2147483647, 100, 2147483648);
+         #[rustfmt::skip]
+         let r = u32x4::new(16777316, 2130706431, 16777316, 2164260864);
+ 
+         assert_eq!(r, mem::transmute(__msa_bnegi_w(mem::transmute(a), 24)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnegi_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(100, 9223372036854775808);
+         #[rustfmt::skip]
+         let r = u64x2::new(4398046511204, 9223376434901286912);
+ 
+         assert_eq!(r, mem::transmute(__msa_bnegi_d(mem::transmute(a), 42)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnz_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 1, 1, 1,
+             1, 1, 1, 1,
+             2, 2, 2, 2,
+             4, 4, 0, 4,
+         );
+         let r = 0 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bnz_b(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnz_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             32767, 3276, 100, 127,
+             32767, 0, 100, 127
+         );
+         let r = 0 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bnz_h(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnz_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(100, 2147483647, 0, 2147483648);
+         let r = 0 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bnz_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnz_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(100, 9223372036854775808);
+         #[rustfmt::skip]
+         let r = 1 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bnz_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bnz_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             0, 0, 0, 1,
+             0, 0, 0, 0,
+             0, 0, 0, 0,
+             0, 0, 0, 0,
+         );
+         let r = 1 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bnz_v(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bsel_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             3, 5, 7, 1,
+             3, 5, 7, 1,
+             3, 5, 7, 1,
+             3, 5, 7, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             7, 3, 15, 9, 
+             7, 3, 15, 9, 
+             7, 3, 15, 9, 
+             7, 3, 15, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bsel_v(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bseli_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             121, 29, 57, 9, 
+             121, 29, 57, 9, 
+             121, 29, 57, 9, 
+             121, 29, 57, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bseli_b(mem::transmute(a), mem::transmute(b), 121))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bset_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             255, 155, 55, 3, 
+             255, 155, 55, 3, 
+             255, 155, 55, 3, 
+             255, 155, 55, 3
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bset_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bset_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(255, 155, 55, 1, 255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(255, 155, 311, 513, 255, 155, 311, 513);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bset_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bset_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(255, 155, 311, 513);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bset_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bset_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(255, 155);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(255, 155);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_bset_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bseti_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             255, 159, 55, 5, 
+             255, 159, 55, 5, 
+             255, 159, 55, 5, 
+             255, 159, 55, 5
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_bseti_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bseti_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(255, 155, 55, 1, 255, 155, 55, 1);
+         #[rustfmt::skip]
+         let r = u16x8::new(255, 159, 55, 5, 255, 159, 55, 5);
+ 
+         assert_eq!(r, mem::transmute(__msa_bseti_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bseti_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(255, 155, 55, 1);
+         #[rustfmt::skip]
+         let r = u32x4::new(255, 159, 55, 5);
+ 
+         assert_eq!(r, mem::transmute(__msa_bseti_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bseti_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(255, 155);
+         #[rustfmt::skip]
+         let r = u64x2::new(255, 159);
+ 
+         assert_eq!(r, mem::transmute(__msa_bseti_d(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bz_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1,
+             255, 155, 55, 1
+         );
+         let r = 0 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bz_b(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bz_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
+         let r = 1 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bz_h(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bz_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(255, 0, 55, 1);
+         let r = 1 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bz_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bz_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(255, 0);
+         let r = 1 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bz_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_bz_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             0, 0, 0, 0,
+             0, 0, 0, 0,
+             0, 0, 0, 0,
+             0, 0, 0, 0
+         );
+         let r = 1 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_bz_v(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceq_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, 127, 55, 1,
+             -128, 127, 55, 1,
+             -128, 127, 55, 1,
+             -128, 127, 55, 1
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -128, 126, 55, 1,
+             -128, 126, 55, 1,
+             -128, 126, 55, 1,
+             -128, 126, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -1, 0, -1, -1, 
+             -1, 0, -1, -1, 
+             -1, 0, -1, -1, 
+             -1, 0, -1, -1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ceq_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceq_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(255, 155, 55, 1, 255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = i16x8::new(255, 155, 56, 1, 255, 155, 56, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(-1, -1, 0, -1, -1, -1, 0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ceq_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceq_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(255, 155, 55, 1);
+         #[rustfmt::skip]
+         let b = i32x4::new(255, 156, 55, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, -1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ceq_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceq_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(255, 155);
+         #[rustfmt::skip]
+         let b = i64x2::new(255, 156);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ceq_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceqi_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, -1, -4, 15,
+             100, -1, -4, 15,
+             100, -1, -4, 15,
+             100, -1, -4, 15
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             0, 0, -1, 0,
+             0, 0, -1, 0,
+             0, 0, -1, 0,
+             0, 0, -1, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ceqi_b(mem::transmute(a), -4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceqi_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             32767, 3276, 100, -11,
+             32767, 3276, 100, -11
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1);
+ 
+         assert_eq!(r, mem::transmute(__msa_ceqi_h(mem::transmute(a), -11)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ceqi_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 3, 5, -3);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, -1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ceqi_w(mem::transmute(a), 5)));
+     }
+ 
+     // FIXME: https://reviews.llvm.org/D59884
+     // If target type is i64, negative immediate loses the sign
+     // Test passes if 4294967293 is used instead -3 in vector `a`
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_ceqi_d() {
+     //     #[rustfmt::skip]
+     //     let a = i64x2::new(-3, 2);
+     //     #[rustfmt::skip]
+     //     let r = i64x2::new(-1, 0);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_ceqi_d(mem::transmute(a), -3)));
+     // }
+ 
+     // Can not be tested in user mode
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_cfcmsa() {
+     //     let r = 5;
+ 
+     //     assert_eq!(r, mem::transmute(__msa_cfcmsa(5));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, 127, 55, 2,
+             -128, 127, 55, 2,
+             -128, 127, 55, 2,
+             -128, 127, 55, 2
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -128, 126, 55, 1,
+             -128, 126, 55, 1,
+             -128, 126, 55, 1,
+             -128, 126, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -1, 0, -1, 0, 
+             -1, 0, -1, 0, 
+             -1, 0, -1, 0, 
+             -1, 0, -1, 0
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(255, 155, 55, 2, 255, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = i16x8::new(255, 155, 56, 1, 255, 155, 56, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(-1, -1, -1, 0, -1, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(255, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(255, 156, 55, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(255, 155);
+         #[rustfmt::skip]
+         let b = i64x2::new(255, 156);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 127, 55, 2,
+             u8::MAX, 127, 55, 2,
+             u8::MAX, 127, 55, 2,
+             u8::MAX, 127, 55, 2
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             u8::MAX, 126, 55, 1,
+             u8::MAX, 126, 55, 1,
+             u8::MAX, 126, 55, 1,
+             u8::MAX, 126, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(-1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             u16::MAX, 155, 55, 2, 
+             u16::MAX, 155, 55, 2
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             u16::MAX, 155, 56, 1, 
+             u16::MAX, 155, 56, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-1, -1, -1, 0, -1, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(u32::MAX, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = u32x4::new(u32::MAX, 156, 55, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_cle_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(u64::MAX, 155);
+         #[rustfmt::skip]
+         let b = u64x2::new(u64::MAX, 156);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_cle_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -2, -127, 100, -127,
+             -2, -127, 100, -127,
+             -2, -127, 100, -127,
+             -2, -127, 100, -127
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(-1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1);
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_s_b(mem::transmute(a), -2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             32767, 3276, 10, -1,
+             32767, 3276, 10, -1,
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1);
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_s_h(mem::transmute(a), -1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 2147483647, 6, 2147483647);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, -1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_s_w(mem::transmute(a), 6)));
+     }
+ 
+     // FIXME: https://reviews.llvm.org/D59884
+     // If target type is i64, negative immediate loses the sign
+     // -3 is represented as 4294967293
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_clei_s_d() {
+     //     #[rustfmt::skip]
+     //     let a = i64x2::new(-3, 11);
+     //     #[rustfmt::skip]
+     //     let r = i64x2::new(-1, 0);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_clei_s_d(mem::transmute(a), -3)));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             2, 127, 100, 127,
+             2, 127, 100, 127,
+             2, 127, 100, 127,
+             2, 127, 100, 127,
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -1, 0, 0, 0, 
+             -1, 0, 0, 0, 
+             -1, 0, 0, 0, 
+             -1, 0, 0, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_u_b(mem::transmute(a), 25)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             1, 26, 15, 36,
+             1, 26, 15, 36
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-1, 0, -1, 0, -1, 0, -1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_u_h(mem::transmute(a), 25)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(25, 32, 25, 32);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, -1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_u_w(mem::transmute(a), 31)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clei_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(10, 26);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clei_u_d(mem::transmute(a), 25)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, 127, 55, 2,
+             -128, 127, 55, 2,
+             -128, 127, 55, 2,
+             -128, 127, 55, 2
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -127, 126, 56, 1,
+             -127, 126, 56, 1,
+             -127, 126, 56, 1,
+             -127, 126, 56, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -1, 0, -1, 0, 
+             -1, 0, -1, 0, 
+             -1, 0, -1, 0, 
+             -1, 0, -1, 0
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-255, 155, 55, 2, -255, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = i16x8::new(255, 156, 56, 1, 255, 156, 56, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(-1, -1, -1, 0, -1, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-255, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(255, 156, 55, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-255, 155);
+         #[rustfmt::skip]
+         let b = i64x2::new(255, 156);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             128, 127, 55, 2,
+             128, 127, 55, 2,
+             128, 127, 55, 2,
+             128, 127, 55, 2
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             127, 126, 56, 1,
+             127, 126, 56, 1,
+             127, 126, 56, 1,
+             127, 126, 56, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             0, 0, -1, 0, 
+             0, 0, -1, 0, 
+             0, 0, -1, 0, 
+             0, 0, -1, 0
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(255, 155, 55, 2, 255, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = u16x8::new(255, 156, 56, 1, 255, 156, 56, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(0, -1, -1, 0, 0, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(255, 155, 55, 2);
+         #[rustfmt::skip]
+         let b = u32x4::new(255, 156, 55, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clt_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(255, 155);
+         #[rustfmt::skip]
+         let b = u64x2::new(255, 156);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_clt_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             2, -127, -5, 127,
+             2, -127, -5, 127,
+             2, -127, -5, 127,
+             2, -127, -5, 127
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             0, -1, 0, 0, 
+             0, -1, 0, 0, 
+             0, -1, 0, 0, 
+             0, -1, 0, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_s_b(mem::transmute(a), -5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             -1024, 3276, 15, 127,
+             -1024, 3276, 15, 127
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-1, 0, 0, 0, -1, 0, 0, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_s_h(mem::transmute(a), 15)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-15, 2147483647, -15, 2147483647);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, -1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_s_w(mem::transmute(a), -10)));
+     }
+ 
+     // FIXME: https://reviews.llvm.org/D59884
+     // If target type is i64, negative immediate loses the sign
+     // -3 is represented as 4294967293
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_clti_s_d() {
+     //     #[rustfmt::skip]
+     //     let a = i64x2::new(-5, -2);
+     //     #[rustfmt::skip]
+     //     let r = i64x2::new(-1, 0);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_clti_s_d(mem::transmute(a), -3)));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             2, 127, 49, 127,
+             2, 127, 49, 127,
+             2, 127, 49, 127,
+             2, 127, 49, 127,
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -1, 0, 0, 0,
+             -1, 0, 0, 0,
+             -1, 0, 0, 0,
+             -1, 0, 0, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_u_b(mem::transmute(a), 50)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             327, 3276, 100, 127,
+             327, 3276, 100, 127
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_u_h(mem::transmute(a), 30)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(100, 2147483647, 100, 2147483647);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, 0, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_u_w(mem::transmute(a), 10)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_clti_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 9223372036854775807);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_clti_u_d(mem::transmute(a), 10)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             -100, 127, 4, 127
+         );
+         #[rustfmt::skip]
+         let r = -100 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_s_b(mem::transmute(a), 12)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             32767, 3276, 100, 11,
+             32767, 3276, 100, 11
+         );
+         #[rustfmt::skip]
+         let r = 32767 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_s_h(mem::transmute(a), 4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 2147483647, 5, -2147483647);
+         let r = 2147483647 as i32;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_s_w(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(3, 9223372036854775807);
+         #[rustfmt::skip]
+         let r = 9223372036854775807 as i64;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_s_d(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_u_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, 127, 4, 127,
+             100, 127, 4, 127,
+             100, 127, 4, 127,
+             100, 127, 4, 127
+         );
+         #[rustfmt::skip]
+         let r = 100 as u32;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_u_b(mem::transmute(a), 12)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_u_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             32767, 3276, 100, 11,
+             32767, 3276, 100, 11
+         );
+         #[rustfmt::skip]
+         let r = 32767 as u32;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_u_h(mem::transmute(a), 4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_u_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 2147483647, 5, 2147483647);
+         #[rustfmt::skip]
+         let r = 2147483647 as u32;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_u_w(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_copy_u_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(3, i64::MAX);
+         #[rustfmt::skip]
+         let r = 9223372036854775807 as u64;
+ 
+         assert_eq!(r, mem::transmute(__msa_copy_u_d(mem::transmute(a), 1)));
+     }
+ 
+     // Can not be tested in user mode
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_ctcmsa() {
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -1, -2, -3, -4,
+             -1, -2, -3, -4,
+             -1, -2, -3, -4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             6, 3, 2, 2, 
+             6, 3, 2, 2, 
+             6, 3, 2, 2, 
+             6, 3, 2, 2
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-6, -7, -8, -9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let b = i16x8::new(-1, -2, -3, -4, -1, -2, -3, -4);
+         #[rustfmt::skip]
+         let r = i16x8::new(6, 3, 2, 2, -6, -3, -2, -2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-6, -7, 8, 9);
+         #[rustfmt::skip]
+         let b = i32x4::new(-1, -2, -3, -4);
+         #[rustfmt::skip]
+         let r = i32x4::new(6, 3, -2, -2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-6, 7);
+         #[rustfmt::skip]
+         let b = i64x2::new(-1, -2);
+         #[rustfmt::skip]
+         let r = i64x2::new(6, -3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             6, 3, 2, 2, 
+             6, 3, 2, 2, 
+             6, 3, 2, 2, 
+             6, 3, 2, 2
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let b = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = u16x8::new(6, 3, 2, 2, 6, 3, 2, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let b = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = u32x4::new(6, 3, 2, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_div_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let b = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = u64x2::new(6, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_div_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dotp_s_h() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -1, -2, -3, 4,
+             -1, -2, -3, -4,
+             -1, -2, -3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(20, -12, 20, 60, 20, -12, 20, 60);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dotp_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dotp_s_w() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-1, -2, -3, -4, -1, -2, -3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, -7, -8, -9, -6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = i32x4::new(20, 60, 20, -12);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dotp_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dotp_s_d() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, -2, -3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(-6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = i64x2::new(20, -12);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dotp_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dotp_u_h() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(20, 60, 20, 60, 20, 60, 20, 60);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dotp_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dotp_u_w() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(20, 60, 20, 60);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dotp_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dotp_u_d() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u64x2::new(20, 60);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dotp_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpadd_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-1, -2, -3, -4, -1, -2, -3, 4);
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -1, -2, -3, 4,
+             -1, -2, -3, -4,
+             -1, -2, -3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let c = i8x16::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(19, -14, 17, 56, 19, -14, 17, 64);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpadd_s_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpadd_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             -1, -2, -3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(19, -14, 17, 56);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpadd_s_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpadd_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, -2);
+         #[rustfmt::skip]
+         let b = i32x4::new(-1, -2, -3, 4);
+         #[rustfmt::skip]
+         let c = i32x4::new(-6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = i64x2::new(19, -14);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpadd_s_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpadd_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(21, 62, 23, 64, 21, 62, 23, 64);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpadd_u_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpadd_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let c = u16x8::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u32x4::new(21, 62, 23, 64);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpadd_u_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpadd_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let c = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u64x2::new(21, 62);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpadd_u_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpsub_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-1, -2, -3, -4, -1, -2, -3, 4);
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -1, -2, -3, 4,
+             -1, -2, -3, -4,
+             -1, -2, -3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let c = i8x16::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-21, 10, -23, -64, -21, 10, -23, -56);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpsub_s_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpsub_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             -1, -2, -3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(-21, 10, -23, -64);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpsub_s_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpsub_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, -2);
+         #[rustfmt::skip]
+         let b = i32x4::new(-1, -2, -3, 4);
+         #[rustfmt::skip]
+         let c = i32x4::new(-6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = i64x2::new(-21, 10);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpsub_s_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpsub_u_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, -2, 3, -4, -1, 2,-3, 4);
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4        
+         );
+         #[rustfmt::skip]
+         let c = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9       
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-19, -62, -17, -64, -21, -58, -23, -56);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpsub_u_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpsub_u_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let c = u16x8::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(-19, -62, -17, -64);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpsub_u_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_dpsub_u_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, -2);
+         #[rustfmt::skip]
+         let b = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let c = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = i64x2::new(-19, -62);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_dpsub_u_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fadd_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, -4.4);
+         #[rustfmt::skip]
+         let b = f32x4::new(4.4, -3.3, 2.2, -1.1);
+         #[rustfmt::skip]
+         let r = f32x4::new(5.5, -5.5, 5.5, -5.5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fadd_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fadd_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(4.4, -3.3);
+         #[rustfmt::skip]
+         let r = f64x2::new(5.5, -5.5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fadd_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     // Only observed beahiour should be SIGFPE signal
+     // Can not be tested
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcaf_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, -4.4);
+         #[rustfmt::skip]
+         let b = f32x4::new(0.0, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcaf_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     // Only observed beahiour should be SIGFPE signal
+     // Can not be tested
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcaf_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(-2.2, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcaf_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fceq_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(-4.4, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fceq_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fceq_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fceq_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fclass_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(128, 8, 128, 2);
+ 
+         assert_eq!(r, mem::transmute(__msa_fclass_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fclass_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let r = i64x2::new(128, 8);
+ 
+         assert_eq!(r, mem::transmute(__msa_fclass_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcle_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(-4.4, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcle_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcle_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcle_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fclt_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(-4.4, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fclt_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fclt_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fclt_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcne_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(-4.4, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcne_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcne_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcne_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcor_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(f32::NAN, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcor_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcor_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcor_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcueq_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(f32::NAN, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, -1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcueq_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcueq_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcueq_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcule_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(f32::NAN, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, -1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcule_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcule_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcule_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcult_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(f32::NAN, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcult_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcult_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcult_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcun_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(f32::NAN, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, 0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcun_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcun_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcun_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcune_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(f32::NAN, -1.2, 3.3, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcune_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fcune_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(1.1, 1.1);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fcune_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fdiv_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.25, -20.2, 333.333, -425.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(4.0, -2.1, 11.11, 8.2);
+         #[rustfmt::skip]
+         let r = f32x4::new(1.3125, 9.619048, 30.002972, -51.82927);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fdiv_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fdiv_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1111.11, -222222.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(-4.85, 3.33);
+         #[rustfmt::skip]
+         let r = f64x2::new(-229.09484536082473, -66733.3933933934);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fdiv_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     /*// FIXME: 16-bit floats
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fexdo_h() {
+         #[rustfmt::skip]
+         let a = f32x4::new(20.5, 2.3, 4.5, 5.4);
+         #[rustfmt::skip]
+         let b = f32x4::new(1.1, 1.0, 1.0, 1.0);
+         let r = i16x8::new(1, 9, 30, 51, 1, 9, 30, 51);
+ 
+         assert_eq!(r, mem::transmute(__msa_fexdo_h(mem::transmute(a), mem::transmute(b))));
+     }*/
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fexdo_w() {
+         #[rustfmt::skip]
+         let a = f64x2::new(2000005.5, 2.3);
+         #[rustfmt::skip]
+         let b = f64x2::new(1235689784512.1, 2147483649998.5);
+         #[rustfmt::skip]
+         let r = f32x4::new(
+             1235689800000.0, 2147483600000.0, 
+             2000005.5, 2.3
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fexdo_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fexp2_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, -4.4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, -3, 2, 1);
+         #[rustfmt::skip]
+         let r = f32x4::new(17.6, -0.275, 13.2, -8.8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fexp2_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fexp2_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = i64x2::new(-4, 3);
+         #[rustfmt::skip]
+         let r = f64x2::new(0.06875, -17.6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fexp2_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     // FIXME: 16-bit floats
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_fexupl_w() {
+     //     #[rustfmt::skip]
+     //     let a = f16x8(1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5);
+     //     #[rustfmt::skip]
+     //     let r = f32x4::new(5.5, 6.5, 7.5, 8.5);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_fexupl_w(mem::transmute(a))));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fexupl_d() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 6.5, 7.5, 8.5);
+         #[rustfmt::skip]
+         let r = f64x2::new(7.5, 8.5);
+ 
+         assert_eq!(r, mem::transmute(__msa_fexupl_d(mem::transmute(a))));
+     }
+ 
+     // FIXME: 16-bit floats
+     //     #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_fexupr_w() {
+     //     #[rustfmt::skip]
+     //     let a = f16x8(1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5);
+     //     #[rustfmt::skip]
+     //     let r = f32x4::new(1.5, 2.5, 3.5, 4.5);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_fexupr_w(mem::transmute(a))));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fexupr_d() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 6.5, 7.5, 8.5);
+         #[rustfmt::skip]
+         let r = f64x2::new(5.5, 6.5);
+ 
+         assert_eq!(r, mem::transmute(__msa_fexupr_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffint_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(-1, 2, -3, 4);
+         #[rustfmt::skip]
+         let r = f32x4::new(-1.0, 2.0, -3.0, 4.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ffint_s_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffint_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, 2);
+         #[rustfmt::skip]
+         let r = f64x2::new(-1.0,     2.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ffint_s_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffint_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = f32x4::new(1.0, 2.0, 3.0, 4.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ffint_u_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffint_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = f64x2::new(1.0, 2.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ffint_u_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffql_w() {
+         #[rustfmt::skip]
+         let a = i16x8::new(11, 25, 33, 47, 11, 25, 33, 47);
+         #[rustfmt::skip]
+         let r = f32x4::new(
+             0.00033569336, 0.00076293945,
+             0.0010070801, 0.0014343262
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ffql_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffql_d() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1111, 2222, 3333, 4444);
+         #[rustfmt::skip]
+         let r = f64x2::new(
+             0.000001552049070596695,
+             0.0000020693987607955933
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ffql_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffqr_w() {
+         #[rustfmt::skip]
+         let a = i16x8::new(12, 26, 34, 48, 11, 25, 33, 47);
+         #[rustfmt::skip]
+         let r = f32x4::new(
+             0.00036621094, 0.00079345703, 
+             0.0010375977, 0.0014648438
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ffqr_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ffqr_d() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1111, 2555, 3333, 475);
+         #[rustfmt::skip]
+         let r = f64x2::new(
+             0.0000005173496901988983, 
+             0.0000011897645890712738
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ffqr_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fill_b() {
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             2, 2, 2, 2,
+             2, 2, 2, 2,
+             2, 2, 2, 2,
+             2, 2, 2, 2
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_fill_b(2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fill_h() {
+         #[rustfmt::skip]
+         let r = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2);
+ 
+         assert_eq!(r, mem::transmute(__msa_fill_h(2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fill_w() {
+         #[rustfmt::skip]
+         let r = i32x4::new(2, 2, 2, 2);
+ 
+         assert_eq!(r, mem::transmute(__msa_fill_w(2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fill_d() {
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 2);
+ 
+         assert_eq!(r, mem::transmute(__msa_fill_d(2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_flog2_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(8.0, 16.0, 32.0, 64.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(3.0, 4.0, 5.0, 6.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_flog2_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_flog2_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(8.0, 16.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(3.0, 4.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_flog2_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmadd_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.0, 6.0, 7.0, 8.0);
+         #[rustfmt::skip]
+         let c = f32x4::new(9.0, 10.0, 11.0, 12.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(46.0, 62.0, 80.0, 100.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmadd_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmadd_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.0, 2.0);
+         #[rustfmt::skip]
+         let b = f64x2::new(3.0, 4.0);
+         #[rustfmt::skip]
+         let c = f64x2::new(5.0, 6.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(16.0, 26.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmadd_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmax_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.0, -6.0, 7.0, 8.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.0, -2.0, 3.0, 4.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(5.0, -2.0, 7.0, 8.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmax_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmax_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.0, 4.0);
+         #[rustfmt::skip]
+         let b = f64x2::new(3.0, 2.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(3.0, 4.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmax_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmax_a_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.0, -6.0, -7.0, -8.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.0, -2.0, 3.0, 4.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(5.0, -6.0, -7.0, -8.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmax_a_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmax_a_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.0, -4.0);
+         #[rustfmt::skip]
+         let b = f64x2::new(3.0, 2.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(3.0, -4.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmax_a_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmin_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.0, -6.0, 7.0, 8.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.0, -2.0, 3.0, 4.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(1.0, -6.0, 3.0, 4.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmin_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmin_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.0, 4.0);
+         #[rustfmt::skip]
+         let b = f64x2::new(3.0, 2.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(1.0, 2.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmin_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmin_a_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.0, -6.0, -7.0, -8.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.0, -2.0, 3.0, 4.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(1.0, -2.0, 3.0, 4.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmin_a_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmin_a_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.0, -4.0);
+         #[rustfmt::skip]
+         let b = f64x2::new(3.0, 2.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(1.0, 2.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmin_a_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmsub_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.0, 6.0, 7.0, 8.0);
+         #[rustfmt::skip]
+         let c = f32x4::new(9.0, 10.0, 11.0, 12.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(-44.0, -58.0, -74.0, -92.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmsub_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmsub_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.0, 2.0);
+         #[rustfmt::skip]
+         let b = f64x2::new(3.0, 4.0);
+         #[rustfmt::skip]
+         let c = f64x2::new(5.0, 6.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(-14.0, -22.0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmsub_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmul_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(1.1, -2.2, 3.3, 4.4);
+         #[rustfmt::skip]
+         let b = f32x4::new(4.4, 3.3, 2.2, -1.1);
+         #[rustfmt::skip]
+         let r = f32x4::new(4.84, -7.26, 7.26, -4.84);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmul_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fmul_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(1.1, -2.2);
+         #[rustfmt::skip]
+         let b = f64x2::new(4.0, -3.3);
+         #[rustfmt::skip]
+         let r = f64x2::new(4.4, 7.26);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fmul_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_frint_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(2.6, -2.7, 1.3, -1.7);
+         #[rustfmt::skip]
+         let r = f32x4::new(3.0, -3.0, 1.0, -2.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_frint_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_frint_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(2.6, 1.3);
+         #[rustfmt::skip]
+         let r = f64x2::new(3.0, 1.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_frint_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_frcp_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(2.6, -2.7, 1.3, -1.7);
+         #[rustfmt::skip]
+         let r = f32x4::new(
+             0.3846154, -0.37037036, 
+             0.7692308, -0.58823526
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_frcp_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_frcp_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(2.6, 1.3);
+         #[rustfmt::skip]
+         let r = f64x2::new(0.3846153846153846, 0.7692307692307692);
+ 
+         assert_eq!(r, mem::transmute(__msa_frcp_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_frsqrt_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(2.6, 2.7, 1.3, 1.7);
+         #[rustfmt::skip]
+         let r = f32x4::new(
+             0.6201737, 0.6085806, 
+             0.87705797, 0.766965
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_frsqrt_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_frsqrt_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(2.6, 1.3);
+         #[rustfmt::skip]
+         let r = f64x2::new(0.6201736729460422, 0.8770580193070292);
+ 
+         assert_eq!(r, mem::transmute(__msa_frsqrt_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsaf_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 5.5, 5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(-5.5, 5.5, 5.5, 5.5);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsaf_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsaf_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-125.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(125.5, 3.3);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsaf_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fseq_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, -3.3, f32::NAN, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.5, -3.3, f32::NAN, 1.1);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fseq_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fseq_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-125.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(125.5, 5.5);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fseq_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsle_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 5.5, 5.5, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(-5.5, 3.3, 5.5, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsle_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsle_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-125.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(125.5, 3.3);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsle_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fslt_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 5.5, 5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.5, 3.3, 5.5, 1.1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fslt_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fslt_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-125.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(125.5, 3.3);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fslt_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsne_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 5.5, 5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.5, 3.3, 5.5, 1.1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsne_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsne_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-125.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(125.5, 5.5);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsne_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsor_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, f32::NAN, 5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.5, 3.3, 5.5, 1.1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, 0, -1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsor_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsor_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-125.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(125.5, f64::NAN);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsor_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsqrt_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(9.0, 81.0, 1089.0, 10000.0);
+         #[rustfmt::skip]
+         let r = f32x4::new(3.0, 9.0, 33.0, 100.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_fsqrt_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsqrt_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(81.0, 10000.0);
+         #[rustfmt::skip]
+         let r = f64x2::new(9.0, 100.0);
+ 
+         assert_eq!(r, mem::transmute(__msa_fsqrt_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsub_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 6.5, 7.5, 8.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(1.25, 1.75, 2.25, 2.75);
+         #[rustfmt::skip]
+         let r = f32x4::new(4.25, 4.75, 5.25, 5.75);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsub_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsub_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(555.5, 55.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(4.25, 3.25);
+         #[rustfmt::skip]
+         let r = f64x2::new(551.25, 52.25);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsub_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsueq_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, f32::NAN, 5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.5, 5.5, -5.5, 5.5);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsueq_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsueq_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(5.5, f64::NAN);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsueq_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsule_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.7, 5.8, 5.9, f32::NAN);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.6, 5.9, 5.9, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, -1, -1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsule_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsule_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f64x2::new(5.5, 5.5);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsule_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsult_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 5.5, 5.5, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(5.6, f32::NAN, 2.2, 1.1);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsult_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsult_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(5.5, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(4.4, 3.3);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsult_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsun_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 5.5, f32::NAN, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(4.4, 3.3, 2.2, f32::NAN);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 0, -1, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsun_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsun_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(5.5, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(4.4, 3.3);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsun_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsune_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(5.5, 5.5, f32::NAN, 5.5);
+         #[rustfmt::skip]
+         let b = f32x4::new(4.4, 3.3, 2.2, 5.5);
+         #[rustfmt::skip]
+         let r = i32x4::new(-1, -1, -1, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsune_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_fsune_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(5.5, f64::NAN);
+         #[rustfmt::skip]
+         let b = f64x2::new(5.5, 3.3);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_fsune_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftint_s_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 75.6, -1000.7, 1219.3);
+         #[rustfmt::skip]
+         let r = i32x4::new(-6, 76, -1001, 1219);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftint_s_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftint_s_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-5.5, 25656.4);
+         #[rustfmt::skip]
+         let r = i64x2::new(-6, 25656);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftint_s_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftint_u_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 75.6, -1000.7, 1219.3);
+         #[rustfmt::skip]
+         let r = u32x4::new(0, 76, 0, 1219);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftint_u_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftint_u_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(5.5, -25656.4);
+         #[rustfmt::skip]
+         let r = u64x2::new(6, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftint_u_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftq_h() {
+         #[rustfmt::skip]
+         let a = f32x4::new(0.00001, 0.0002, 0.00001, -0.0002);
+         #[rustfmt::skip]
+         let b = f32x4::new(0.0001, -0.002, 0.0001, 0.002);
+         #[rustfmt::skip]
+         let r = i16x8::new(3, -66, 3, 66, 0, 7, 0, -7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ftq_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftq_w() {
+         #[rustfmt::skip]
+         let a = f64x2::new(0.00001, -0.0002);
+         #[rustfmt::skip]
+         let b = f64x2::new(0.00000045, 0.000015);
+         #[rustfmt::skip]
+         let r = i32x4::new(966, 32212, 21475, -429497);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ftq_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftrunc_s_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 75.6, -1000.7, 1219.3);
+         #[rustfmt::skip]
+         let r = i32x4::new(-5, 75, -1000, 1219);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftrunc_s_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftrunc_s_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(-5.5, 25656.4);
+         #[rustfmt::skip]
+         let r = i64x2::new(-5, 25656);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftrunc_s_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftrunc_u_w() {
+         #[rustfmt::skip]
+         let a = f32x4::new(-5.5, 75.6, -1000.7, 1219.3);
+         #[rustfmt::skip]
+         let r = u32x4::new(0, 75, 0, 1219);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftrunc_u_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ftrunc_u_d() {
+         #[rustfmt::skip]
+         let a = f64x2::new(5.5, -25656.4);
+         #[rustfmt::skip]
+         let r = u64x2::new(5, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_ftrunc_u_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hadd_s_h() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(6, 6, 2, -2, 6, 6, 2, -2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hadd_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hadd_s_w() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(6, 6, 2, -2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hadd_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hadd_s_d() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, -2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hadd_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hadd_u_h() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(6, 6, 6, 6, 6, 6, 6, 6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hadd_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hadd_u_w() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = u32x4::new(6, 6, 6, 6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hadd_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hadd_u_d() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = u64x2::new(6, 6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hadd_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hsub_s_h() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-2, 2, -6, -6, -2, 2, -6, -6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hsub_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hsub_s_w() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(-2, 2, -6, -6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hsub_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hsub_s_d() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-6, -6);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hsub_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hsub_u_h() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(-2, 2, -2, 2, -2, 2, -2, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hsub_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hsub_u_w() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(-2, 2, -2, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hsub_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_hsub_u_d() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(-2, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_hsub_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvev_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             4, 1, 2, 3,
+             4, 1, 2, 3,
+             4, 1, 2, 3,
+             4, 1, 2, 3
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvev_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvev_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(4, 1, 2, 3, 4, 1, 2, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvev_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvev_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 1, 2, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvev_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvev_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(4, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(4, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvev_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvl_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             16, 15, 14, 13,
+             12, 11, 10, 9,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             8, 9, 7, 10,
+             6, 11, 5, 12,
+             4, 13, 3, 14,
+             2, 15, 1, 16
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvl_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvl_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(4, 5, 3, 6, 2, 7, 1, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvl_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvl_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(2, 3, 1, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvl_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvl_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(1, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvl_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvod_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             16, 15, 14, 13,
+             12, 11, 10, 9,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             15, 2, 13, 4,
+             11, 6, 9, 8,
+             7, 10, 5, 12,
+             3, 14, 1, 16
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvod_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvod_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(7, 2, 5, 4, 3, 6, 1, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvod_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvod_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(3, 2, 1, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvod_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvod_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(1, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvod_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvr_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             16, 15, 14, 13,
+             12, 11, 10, 9,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             16, 1, 15, 2,
+             14, 3, 13, 4,
+             12, 5, 11, 6,
+             10, 7, 9, 8
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvr_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvr_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1,
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(8, 1, 7, 2, 6, 3, 5, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvr_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvr_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 1, 3, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvr_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ilvr_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_ilvr_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insert_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             -100, 127, 4, 127
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             5, 127, 4, 127
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_insert_b(mem::transmute(a), 12, 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insert_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             32767, 3276, 100, 11,
+             32767, 3276, 100, 11
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             32767, 3276, 100, 11,
+             5, 3276, 100, 11
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_insert_h(mem::transmute(a), 4, 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insert_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 2147483647, 5, -2147483647);
+         #[rustfmt::skip]
+         let r = i32x4::new(100, 7, 5, -2147483647);
+ 
+         assert_eq!(r, mem::transmute(__msa_insert_w(mem::transmute(a), 1, 7)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insert_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(3, i64::MAX);
+         #[rustfmt::skip]
+         let r = i64x2::new(3, 100);
+ 
+         assert_eq!(r, mem::transmute(__msa_insert_d(mem::transmute(a), 1, 100)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insve_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -100, i8::MAX, 4, i8::MAX,
+             -100, i8::MAX, 4, i8::MAX,
+             -100, i8::MAX, 4, i8::MAX,
+             -100, i8::MAX, 4, i8::MAX
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             5, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             -100, 127, 4, 127,
+             5, 127, 4, 127
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_insve_b(mem::transmute(a), 12, mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insve_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 3276, 100, 11,
+             i16::MAX, 3276, 100, 11
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             32767, 3276, 100, 11,
+             1, 3276, 100, 11
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_insve_h(mem::transmute(a), 4, mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insve_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 2147483647, 5, -2147483647);
+         #[rustfmt::skip]
+         let b = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = i32x4::new(100, 2147483647, 5, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_insve_w(mem::transmute(a), 3, mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_insve_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(3, i64::MAX);
+         #[rustfmt::skip]
+         let b = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = i64x2::new(3, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_insve_d(mem::transmute(a), 1, mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ld_b() {
+         #[rustfmt::skip]
+         let mut a : [i8; 32] = [
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31
+         ];
+         let p = &mut a[4] as *mut _ as *mut u8;
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             13, 14, 15, 16, 
+             17, 18, 19, 20, 
+             21, 22, 23, 24, 
+             25, 26, 27, 28
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ld_b(p, 9)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ld_h() {
+         #[rustfmt::skip]
+         let mut a : [i16; 16] = [
+             0, 1, 2, 3, 4, 5, 6, 7, 
+             8, 9, 10, 11, 12, 13, 14, 15
+         ];
+         let p = &mut a[4] as *mut _ as *mut u8;
+         #[rustfmt::skip]
+         let r = i16x8::new(3, 4, 5, 6, 7, 8, 9, 10);
+ 
+         assert_eq!(r, mem::transmute(__msa_ld_h(p, -2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ld_w() {
+         #[rustfmt::skip]
+         let mut a : [i32; 8] = [0, 1, 2, 3, 4, 5, 6, 7];
+         let p = &mut a[3] as *mut _ as *mut u8;
+         #[rustfmt::skip]
+         let r = i32x4::new(2, 3, 4, 5);
+ 
+         assert_eq!(r, mem::transmute(__msa_ld_w(p, -4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ld_d() {
+         #[rustfmt::skip]
+         let mut a : [i64; 8] = [0, 1, 2, 3, 4, 5, 6, 7];
+         let p = &mut a[4] as *mut _ as *mut u8;
+         #[rustfmt::skip]
+         let r = i64x2::new(0, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_ld_d(p, -32)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ldi_b() {
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -20, -20, -20, -20,
+             -20, -20, -20, -20,
+             -20, -20, -20, -20,
+             -20, -20, -20, -20
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ldi_b(-20)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ldi_h() {
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             255, 255, 255, 255,
+             255, 255, 255, 255
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ldi_h(255)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ldi_w() {
+         #[rustfmt::skip]
+         let r = i32x4::new(-509, -509, -509, -509);
+ 
+         assert_eq!(r, mem::transmute(__msa_ldi_w(-509)));
+     }
+ 
+     // FIXME: https://reviews.llvm.org/D59884
+     // If target type is i64, negative immediate loses the sign
+     // Test passes if 4294967185 is used instead -111 in vector `r`
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_ldi_d() {
+     //     let r = i64x2::new(-111, -111);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_ldi_d(-111)));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_madd_q_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 1024, i16::MIN, -1024,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1024, 1024, 1024, 1024,
+             1024, 1024, 1024, 1024
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             i16::MAX, i16::MAX, 1, -1,
+             33, 66, 99, 132
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(32767, 2047, -32768, -1025, 2, 4, 6, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_madd_q_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_madd_q_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MAX, i32::MIN, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(102401, 102401, 102401, 102401);
+         #[rustfmt::skip]
+         let c = i32x4::new(10240, 20480, 30720, 40960);
+         #[rustfmt::skip]
+         let r = i32x4::new(2147483647, -2147483648, 2, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_madd_q_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maddr_q_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             32767, 1024, -32768, -1024,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1024, 1024, 1024, 1024,
+             1024, 1024, 1024, 1024
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             32767, 32767, 32767, 32767,
+             33, 66, 99, 132
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(32767, 2048, -31744, 0, 2, 4, 6, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_maddr_q_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maddr_q_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MAX, i32::MIN, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(102401, 102401, 102401, 102401);
+         #[rustfmt::skip]
+         let c = i32x4::new(10240, 20480, 30720, 40960);
+         #[rustfmt::skip]
+         let r = i32x4::new(2147483647, -2147483647, 2, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_maddr_q_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maddv_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             5, 6, 7, 8,
+             5, 6, 7, 8,
+             5, 6, 7, 8,
+             5, 6, 7, 8
+         );
+         #[rustfmt::skip]
+         let c = i8x16::new(
+             9, 10, 11, 12,
+             9, 10, 11, 12,
+             9, 10, 11, 12,
+             9, 10, 11, 12
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             46, 62, 80, 100,
+             46, 62, 80, 100,
+             46, 62, 80, 100,
+             46, 62, 80, 100
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_maddv_b(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maddv_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(5, 6, 7, 8, 5, 6, 7, 8);
+         #[rustfmt::skip]
+         let c = i16x8::new(9, 10, 11, 12, 9, 10, 11, 12);
+         #[rustfmt::skip]
+         let r = i16x8::new(46, 62, 80, 100, 46, 62, 80, 100);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_maddv_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maddv_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(3, 4, 3, 4);
+         #[rustfmt::skip]
+         let c = i32x4::new(5, 6, 5, 6);
+         #[rustfmt::skip]
+         let r = i32x4::new(16, 26, 16, 26);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_maddv_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maddv_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(3, 4);
+         #[rustfmt::skip]
+         let c = i64x2::new(5, 6);
+         #[rustfmt::skip]
+         let r = i64x2::new(16, 26);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_maddv_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_a_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             6, 7, 8, 9,
+             -6, -7, -8, -9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -6, -7, -8, -9,
+             6, 7, 8, 9,
+             -6, -7, -8, -9,
+             6, 7, 8, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_a_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_a_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, 7, -8, 9, -6, 7, -8, 9);
+         #[rustfmt::skip]
+         let r = i16x8::new(-6, 7, -8, 9, -6, 7, -8, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_a_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_a_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = i32x4::new(6, 7, 8, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_a_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_a_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(6, -7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_a_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             6, 7, 8, 9,
+             -6, -7, -8, -9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             1, 2, 3, 4,
+             6, 7, 8, 9,
+             1, 2, 3, 4,
+             6, 7, 8, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, 7, -8, 9, -6, 7, -8, 9);
+         #[rustfmt::skip]
+         let r = i16x8::new(1, 7, 3, 9, 1, 7, 3, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = i32x4::new(6, 7, 8, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(6, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(6, 7, 8, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_max_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(6, 7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_max_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, -20, -6, 8,
+             1, -20, -6, 8,
+             1, -20, -6, 8,
+             1, -20, -6, 8
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             1, -16, -6, 8,
+             1, -16, -6, 8,
+             1, -16, -6, 8,
+             1, -16, -6, 8
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_s_b(mem::transmute(a), -16)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 3, -60, -8, 1, 3, -6, -8);
+         #[rustfmt::skip]
+         let r = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15);
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_s_h(mem::transmute(a), 15)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 3, -6, -8);
+         #[rustfmt::skip]
+         let r = i32x4::new(1, 3, -5, -5);
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_s_w(mem::transmute(a), -5)));
+     }
+ 
+     // FIXME: https://reviews.llvm.org/D59884
+     // If target type is i64, negative immediate loses the sign
+     // Test passes if 4294967293 is used instead -3 in vector `r`
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_maxi_s_d() {
+     //     #[rustfmt::skip]
+     //     let a = i64x2::new(1, -8);
+     //     #[rustfmt::skip]
+     //     let r = i64x2::new(-3, -3);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_maxi_s_d(mem::transmute(a), -3)));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 3, 6, 8,
+             1, 3, 6, 8,
+             1, 3, 6, 8,
+             1, 3, 6, 8
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             5, 5, 6, 8,
+             5, 5, 6, 8,
+             5, 5, 6, 8,
+             5, 5, 6, 8
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_u_b(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 3, 6, 8, 1, 3, 6, 8);
+         #[rustfmt::skip]
+         let r = u16x8::new(5, 5, 6, 8, 5, 5, 6, 8);
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_u_h(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 3, 6, 8);
+         #[rustfmt::skip]
+         let r = u32x4::new(5, 5, 6, 8);
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_u_w(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_maxi_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 8);
+         #[rustfmt::skip]
+         let r = u64x2::new(5, 8);
+ 
+         assert_eq!(r, mem::transmute(__msa_maxi_u_d(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_a_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             6, 7, 8, 9,
+             -6, -7, -8, -9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_a_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_a_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, 7, -8, 9, -6, 7, -8, 9);
+         #[rustfmt::skip]
+         let r = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_a_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_a_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = i32x4::new(1, -2, 3, -4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_a_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_a_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_a_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             6, 7, 8, 9,
+             -6, -7, -8, -9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -6, -7, -8, -9,
+             -1, -2, -3, -4,
+             -6, -7, -8, -9,
+             -1, -2, -3, -4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, 7, -8, 9, -6, 7, -8, 9);
+         #[rustfmt::skip]
+         let r = i16x8::new(-6, -2, -8, -4, -6, -2, -8, -4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = i32x4::new(1, -2, 3, -4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(-1, -7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -10, -10, -10, -10,
+             -10, -10, -10, -10,
+             -10, -10, -10, -10,
+             -10, -10, -10, -10
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_s_b(mem::transmute(a), -10)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+         #[rustfmt::skip]
+         let r = i16x8::new(-3, -3, -3, -4, -3, -3, -3, -4);
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_s_h(mem::transmute(a), -3)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let r = i32x4::new(-3, -3, -3, -4);
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_s_w(mem::transmute(a), -3)));
+     }
+ 
+     // FIXME: https://reviews.llvm.org/D59884
+     // If target type is i64, negative immediate loses the sign
+     // -3 is represented as 4294967293
+     // #[simd_test(enable = "msa")]
+     // unsafe fn test_msa_mini_s_d() {
+     //     #[rustfmt::skip]
+     //     let a = i64x2::new(-3, 2);
+     //     #[rustfmt::skip]
+     //     let r = i64x2::new(-1, -3);
+ 
+     //     assert_eq!(r, mem::transmute(__msa_mini_s_d(mem::transmute(a), -3)));
+     // }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4,);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(1, 2, 3, 4,);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_min_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(1, 2,);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_min_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 3, 6, 8,
+             1, 3, 6, 8,
+             1, 3, 6, 8,
+             1, 3, 6, 8
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             1, 3, 5, 5,
+             1, 3, 5, 5,
+             1, 3, 5, 5,
+             1, 3, 5, 5
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_u_b(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(1, 3, 6, 8, 1, 3, 6, 8);
+         #[rustfmt::skip]
+         let r = u16x8::new(1, 3, 5, 5, 1, 3, 5, 5);
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_u_h(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(1, 3, 6, 8);
+         #[rustfmt::skip]
+         let r = u32x4::new(1, 3, 5, 5);
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_u_w(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mini_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(1, 8);
+         #[rustfmt::skip]
+         let r = u64x2::new(1, 5);
+ 
+         assert_eq!(r, mem::transmute(__msa_mini_u_d(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -6, -7, -8, -9,
+             6, 7, 8, 9,
+             -6, -7, -8, -9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             1, 2, 3, 4,
+             -1, -2, -3, -4,
+             1, 2, 3, 4,
+             -1, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             0, -1, -2, -1,
+             0, 1, 2, 1,
+             0, -1, -2, -1,
+             0, 1, 2, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(-6, 7, -8, 9, -6, 7, -8, 9);
+         #[rustfmt::skip]
+         let b = i16x8::new(1, -2, 3, -4, 1, -2, 3, -4);
+         #[rustfmt::skip]
+         let r = i16x8::new(0, 1, -2, 1, 0, 1, -2, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let b = i32x4::new(1, -2, 3, -4);
+         #[rustfmt::skip]
+         let r = i32x4::new(0, 1, 2, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let b = i64x2::new(-1, 2);
+         #[rustfmt::skip]
+         let r = i64x2::new(0, -1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             0, 1, 2, 1,
+             0, 1, 2, 1,
+             0, 1, 2, 1,
+             0, 1, 2, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let b = u16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = u16x8::new(0, 1, 2, 1, 0, 1, 2, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let b = u32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = u32x4::new(0, 1, 2, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mod_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let b = u64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = u64x2::new(0, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mod_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_move_v() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             1, 2, 3, 4,
+             5, 6, 7, 8
+             );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             1, 2, 3, 4,
+             5, 6, 7, 8
+             );
+ 
+         assert_eq!(r, mem::transmute(__msa_move_v(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msub_q_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1024, -1024, 1024, -1024,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1025, 1025, 1025, 1025,
+             1025, 1025, 1025, 1025
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             1024, 2048, 3072, 4096,
+             1024, 2048, 3072, 4096
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(991, -1089, 927, -1153, -32, -63, -94, -125);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msub_q_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msub_q_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(2147483647, -2147483647, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(10240, 10240, 10240, 10240);
+         #[rustfmt::skip]
+         let c = i32x4::new(10240, 20480, 30720, 40960);
+         #[rustfmt::skip]
+         let r = i32x4::new(2147483646, -2147483648, 0, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msub_q_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msubr_q_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1024, -1024, 1024, -1024,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1025, 1025, 1025, 1025, 
+             1025, 1025, 1025, 1025
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             1024, 2048, 3072, 4096,
+             1024, 2048, 3072, 4096
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(992, -1088, 928, -1152, -31, -62, -93, -124);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msubr_q_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msubr_q_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MAX, -2147483647, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(10240, 10240, 10240, 10240);
+         #[rustfmt::skip]
+         let c = i32x4::new(10240, 20480, 30720, 40960);
+         #[rustfmt::skip]
+         let r = i32x4::new(2147483647, -2147483647, 1, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msubr_q_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msubv_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             5, 6, 7, 8,
+             5, 6, 7, 8,
+             5, 6, 7, 8,
+             5, 6, 7, 8
+         );
+         #[rustfmt::skip]
+         let c = i8x16::new(
+             9, 10, 11, 12,
+             9, 10, 11, 12,
+             9, 10, 11, 12,
+             9, 10, 11, 12
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -44, -58, -74, -92,
+             -44, -58, -74, -92,
+             -44, -58, -74, -92,
+             -44, -58, -74, -92
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msubv_b(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msubv_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(5, 6, 7, 8, 5, 6, 7, 8);
+         #[rustfmt::skip]
+         let c = i16x8::new(9, 10, 11, 12, 9, 10, 11, 12);
+         #[rustfmt::skip]
+         let r = i16x8::new(-44, -58, -74, -92, -44, -58, -74, -92);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msubv_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msubv_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(3, 4, 3, 4);
+         #[rustfmt::skip]
+         let c = i32x4::new(5, 6, 5, 6);
+         #[rustfmt::skip]
+         let r = i32x4::new(-14, -22, -14, -22);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msubv_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_msubv_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(3, 4);
+         #[rustfmt::skip]
+         let c = i64x2::new(5, 6);
+         #[rustfmt::skip]
+         let r = i64x2::new(-14, -22);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_msubv_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mul_q_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             12500, -20, -300, 400,
+             12500, 20, 300, 400
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1250, 10240, -7585, 8456,
+             1250, 10240, -7585, 8456
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(476, -7, 69, 103, 476, 6, -70, 103);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mul_q_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mul_q_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(
+             i32::MAX, i32::MAX,
+             i32::MIN, i32::MIN
+         );
+         #[rustfmt::skip]
+         let b = i32x4::new(30, 60, 30, 60);
+         #[rustfmt::skip]
+         let r = i32x4::new(29, 59, -30, -60);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mul_q_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mulr_q_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             12500, -20, -300, 400,
+             12500, 20, 300, 400
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             1250, 10240, -7585, 8456,
+             1250, 10240, -7585, 8456
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(477, -6, 69, 103, 477, 6, -69, 103);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mulr_q_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mulr_q_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(
+             i32::MAX, i32::MAX,
+             i32::MIN, i32::MIN
+         );
+         #[rustfmt::skip]
+         let b = i32x4::new(30, 60, 30, 60);
+         #[rustfmt::skip]
+         let r = i32x4::new(30, 60, -30, -60);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mulr_q_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mulv_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             16, 15, 14, 13,
+             12, 11, 10, 9,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             16, 30, 42, 52,
+             60, 66, 70, 72,
+             72, 70, 66, 60,
+             52, 42, 30, 16
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mulv_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mulv_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(8, 14, 18, 20, 20, 18, 14, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mulv_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mulv_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 6, 6, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mulv_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_mulv_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(2, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_mulv_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nloc_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, -64, -32, -16,
+             -8, -4, -2, -1,
+             1, 2, 4, 8,
+             16, 32, 64, 127
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             0, 0, 0, 0,
+             0, 0, 0, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_nloc_b(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nloc_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             -32768, -16384, -8192, -4096,
+             4096, 8192, 16384, 32767
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(1, 2, 3, 4, 0, 0, 0, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_nloc_h(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nloc_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(
+             i32::MIN, -1073741824,
+             1073741824, i32::MAX
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(1, 2, 0, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_nloc_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nloc_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MIN, i64::MAX);
+         #[rustfmt::skip]
+         let r = i64x2::new(1, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_nloc_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nlzc_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             7, 6, 6, 5,
+             5, 5, 5, 4,
+             4, 4, 4, 4,
+             4, 4, 4, 3
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_nlzc_b(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nlzc_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(15, 14, 14, 13, 13, 13, 13, 12);
+ 
+         assert_eq!(r, mem::transmute(__msa_nlzc_h(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nlzc_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = i32x4::new(31, 30, 30, 29);
+ 
+         assert_eq!(r, mem::transmute(__msa_nlzc_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nlzc_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = i64x2::new(63, 62);
+ 
+         assert_eq!(r, mem::transmute(__msa_nlzc_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nor_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             254, 253, 252, 251,
+             250, 249, 248, 247,
+             246, 245, 244, 243,
+             242, 241, 240, 239
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_nor_v(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_nori_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             250, 249, 248, 251,
+             250, 249, 248, 243,
+             242, 241, 240, 243,
+             242, 241, 240, 235
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_nori_b(mem::transmute(a), 4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_or_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_or_v(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_ori_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             5, 6, 7, 4,
+             5, 6, 7, 12,
+             13, 14, 15, 12,
+             13, 14, 15, 20
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_ori_b(mem::transmute(a), 4)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckev_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             4, 2, 4, 2,
+             4, 2, 4, 2,
+             1, 3, 1, 3,
+             1, 3, 1, 3
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckev_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckev_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(4, 3, 2, 1, 4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(4, 2, 4, 2, 1, 3, 1, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckev_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckev_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 2, 1, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckev_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckev_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(4, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(4, 1);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckev_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckod_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             3, 1, 3, 1,
+             3, 1, 3, 1,
+             2, 4, 2, 4,
+             2, 4, 2, 4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckod_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckod_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(4, 3, 2, 1, 4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(3, 1, 3, 1, 2, 4, 2, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckod_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckod_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(3, 1, 2, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckod_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pckod_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(4, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(3, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_pckod_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pcnt_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, -64, -32, -16,
+             -8, -4, -2, -1,
+             1, 2, 4, 8,
+             16, 32, 64, 127
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             1, 1, 1, 1,
+             1, 1, 1, 7
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_pcnt_b(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pcnt_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             -32768, -16384, -8192, -4096,
+             4096, 8192, 16384, 32767
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(1, 2, 3, 4, 1, 1, 1, 15);
+ 
+         assert_eq!(r, mem::transmute(__msa_pcnt_h(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pcnt_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(
+             i32::MIN, -1073741824,
+             1073741824, i32::MAX
+         );
+         #[rustfmt::skip]
+         let r = i32x4::new(1, 2, 1, 31);
+ 
+         assert_eq!(r, mem::transmute(__msa_pcnt_w(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_pcnt_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(-2147483648, 2147483647);
+         #[rustfmt::skip]
+         let r = i64x2::new(33, 31);
+ 
+         assert_eq!(r, mem::transmute(__msa_pcnt_d(mem::transmute(a))));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             i8::MAX, 105, 30, 1,
+             i8::MAX, 105, 30, 1,
+             i8::MAX, 105, 30, 1,
+             i8::MAX, 105, 30, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             3, 3, 3, 1,
+             3, 3, 3, 1,
+             3, 3, 3, 1,
+             3, 3, 3, 1
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_s_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 1155, 155, 1,
+             i16::MAX, 1155, 155, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(127, 127, 127, 1, 127, 127, 127, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_s_h(mem::transmute(a), 7)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MAX, 111111155, i32::MAX, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(131071, 131071, 131071, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_s_w(mem::transmute(a), 17)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MAX, 1);
+         #[rustfmt::skip]
+         let r = i64x2::new(137438953471, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_s_d(mem::transmute(a), 37)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 105, 30, 1,
+             u8::MAX, 105, 30, 1,
+             u8::MAX, 105, 30, 1,
+             u8::MAX, 105, 30, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             7, 7, 7, 1,
+             7, 7, 7, 1,
+             7, 7, 7, 1,
+             7, 7, 7, 1
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_u_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             u16::MAX, 1155, 155, 1,
+             u16::MAX, 1155, 155, 1
+         );
+         #[rustfmt::skip]
+         let r = u16x8::new(255, 255, 155, 1, 255, 255, 155, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_u_h(mem::transmute(a), 7)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(u32::MAX, 111111155, u32::MAX, 1);
+         #[rustfmt::skip]
+         let r = u32x4::new(262143, 262143, 262143, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_u_w(mem::transmute(a), 17)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sat_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(u64::MAX, 1);
+         #[rustfmt::skip]
+         let r = u64x2::new(274877906943, 1);
+ 
+         assert_eq!(r, mem::transmute(__msa_sat_u_d(mem::transmute(a), 37)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_shf_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             11, 12, 3, 4,
+             11, 12, 3, 4,
+             11, 12, 3, 4,
+             11, 12, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             11, 3, 4, 12,
+             11, 3, 4, 12,
+             11, 3, 4, 12,
+             11, 3, 4, 12
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_shf_b(mem::transmute(a), 120)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_shf_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             11, 12, 13, 14,
+             11, 12, 13, 14
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(11, 14, 12, 13, 11, 14, 12, 13);
+ 
+         assert_eq!(r, mem::transmute(__msa_shf_h(mem::transmute(a), 156)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_shf_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = i32x4::new(1, 3, 2, 4);
+ 
+         assert_eq!(r, mem::transmute(__msa_shf_w(mem::transmute(a), 216)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sld_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             0, 1, 2, 3,
+             4, 5, 6, 7,
+             8, 9, 10, 11,
+             12, 13, 14, 15
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             16, 17, 18, 19,
+             20, 21, 22, 23,
+             24, 25, 26, 27,
+             28, 29, 30, 31
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             21, 22, 23, 24,
+             25, 26, 27, 28,
+             29, 30, 31, 0,
+             1, 2, 3, 4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sld_b(mem::transmute(a), mem::transmute(b), 5))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sld_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         #[rustfmt::skip]
+         let b = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15);
+         // let c = 5 as i32;
+         let r = i16x8::new(9, 10, 11, 0, 13, 14, 15, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sld_h(mem::transmute(a), mem::transmute(b), 2))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sld_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(0, 1, 2, 3);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 5, 6, 7);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 5, 6, 7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sld_w(mem::transmute(a), mem::transmute(b), 4))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sld_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(0, 1);
+         #[rustfmt::skip]
+         let b = i64x2::new(2, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sld_d(mem::transmute(a), mem::transmute(b), 2))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sldi_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             0, 1, 2, 3,
+             4, 5, 6, 7,
+             8, 9, 10, 11,
+             12, 13, 14, 15
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             16, 17, 18, 19,
+             20, 21, 22, 23,
+             24, 25, 26, 27,
+             28, 29, 30, 31
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             21, 22, 23, 24,
+             25, 26, 27, 28,
+             29, 30, 31, 0,
+             1, 2, 3, 4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sldi_b(mem::transmute(a), mem::transmute(b), 5))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sldi_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+         #[rustfmt::skip]
+         let b = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15);
+         // let c = 5 as i32;
+         let r = i16x8::new(9, 10, 11, 0, 13, 14, 15, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sldi_h(mem::transmute(a), mem::transmute(b), 2))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sldi_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(0, 1, 2, 3);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 5, 6, 7);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 5, 6, 7);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sldi_w(mem::transmute(a), mem::transmute(b), 4))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sldi_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(0, 1);
+         #[rustfmt::skip]
+         let b = i64x2::new(2, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 3);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sldi_d(mem::transmute(a), mem::transmute(b), 2))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sll_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             16, 16, 12, 8,
+             16, 16, 12, 8,
+             16, 16, 12, 8,
+             16, 16, 12, 8
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sll_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sll_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(1, 2, 3, 4, 1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i16x8::new(4, 3, 2, 1, 4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(16, 16, 12, 8, 16, 16, 12, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sll_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sll_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(16, 16, 12, 8);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sll_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sll_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(4, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(16, 16);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sll_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_slli_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             4, 8, 12, 16,
+             4, 8, 12, 16,
+             4, 8, 12, 16,
+             4, 8, 12, 16
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_slli_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_slli_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4  
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(4, 8, 12, 16, 4, 8, 12, 16);
+ 
+         assert_eq!(r, mem::transmute(__msa_slli_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_slli_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 8, 12, 16);
+ 
+         assert_eq!(r, mem::transmute(__msa_slli_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_slli_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 4);
+ 
+         assert_eq!(r, mem::transmute(__msa_slli_d(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splat_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             4, 4, 4, 4,
+             4, 4, 4, 4,
+             4, 4, 4, 4,
+             4, 4, 4, 4
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_splat_b(mem::transmute(a), 3)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splat_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(4, 4, 4, 4, 4, 4, 4, 4);
+ 
+         assert_eq!(r, mem::transmute(__msa_splat_h(mem::transmute(a), 3)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splat_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = i32x4::new(4, 4, 4, 4);
+ 
+         assert_eq!(r, mem::transmute(__msa_splat_w(mem::transmute(a), 3)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splat_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 2);
+ 
+         assert_eq!(r, mem::transmute(__msa_splat_d(mem::transmute(a), 3)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splati_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             3, 3, 3, 3,
+             3, 3, 3, 3,
+             3, 3, 3, 3,
+             3, 3, 3, 3
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_splati_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splati_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3);
+ 
+         assert_eq!(r, mem::transmute(__msa_splati_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splati_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let r = i32x4::new(3, 3, 3, 3);
+ 
+         assert_eq!(r, mem::transmute(__msa_splati_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_splati_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let r = i64x2::new(2, 2);
+ 
+         assert_eq!(r, mem::transmute(__msa_splati_d(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sra_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, -64, -32, -16,
+             -8, -4, -2, -1,
+             1, 2, 4, 8,
+             16, 32, 64, 127
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -128, -1, -1, -1,
+             -1, -1, -1, -1,
+             1, 0, 0, 0,
+             1, 4, 16, 63
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sra_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sra_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             -32768, -16384, -8192, -4096,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             15, 14, 13, 12,
+             12, 13, 14, 15
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             -1, -1, -1, -1,
+             0, 0, 0, 0
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sra_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sra_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MIN, -1073741824, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(16, 15, 16, 15);
+         #[rustfmt::skip]
+         let r = i32x4::new(-32768, -32768, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sra_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_sra_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MIN, i64::MAX);
+         #[rustfmt::skip]
+         let b = i64x2::new(32, 31);
+         #[rustfmt::skip]
+         let r = i64x2::new(-2147483648, 4294967295);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_sra_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srai_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             i8::MAX, 125, 55, 1,
+             i8::MAX, 125, 55, 1,
+             i8::MAX, 125, 55, 1,
+             i8::MAX, 125, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             31, 31, 13, 0,
+             31, 31, 13, 0,
+             31, 31, 13, 0,
+             31, 31, 13, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_srai_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srai_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 125, 55, 1, 
+             i16::MAX, 125, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(8191, 31, 13, 0, 8191, 31, 13, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_srai_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srai_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MAX, 125, 55, 1);
+         let r = i32x4::new(536870911, 31, 13, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_srai_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srai_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MAX, 55);
+         #[rustfmt::skip]
+         let r = i64x2::new(2305843009213693951, 13);
+ 
+         assert_eq!(r, mem::transmute(__msa_srai_d(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srar_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, -64, -32, -16,
+             -8, -4, -2, -1,
+             1, 2, 4, 8,
+             16, 32, 64, 127
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -8, -8, -8, -8,
+             0, 0, 0, 0,
+             1, 0, 0, 0,
+             1, 4, 16, 64
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srar_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srar_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MIN, -16384, -8192, -4096,
+             150, 50, 25, 15
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             4, 3, 2, 1,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             -2048, -2048, -2048, -2048, 
+             75, 13, 3, 1
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srar_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srar_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MIN, -1073741824, 100, 50);
+         #[rustfmt::skip]
+         let b = i32x4::new(16, 15, 1, 2);
+         #[rustfmt::skip]
+         let r = i32x4::new(-32768, -32768, 50, 13);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srar_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srar_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MIN, i64::MAX);
+         #[rustfmt::skip]
+         let b = i64x2::new(32, 31);
+         #[rustfmt::skip]
+         let r = i64x2::new(-2147483648, 4294967296);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srar_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srari_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             125, i8::MAX, 55, 1,
+             125, i8::MAX, 55, 1,
+             125, i8::MAX, 55, 1,
+             125, i8::MAX, 55, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             31, 32, 14, 0,
+             31, 32, 14, 0,
+             31, 32, 14, 0,
+             31, 32, 14, 0
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_srari_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srari_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(2155, 1155, 155, 1, 2155, 1155, 155, 1);
+         #[rustfmt::skip]
+         let r = i16x8::new(539, 289, 39, 0, 539, 289, 39, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_srari_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srari_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(211111155, 111111155, 11111155, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(52777789, 27777789, 2777789, 0);
+ 
+         assert_eq!(r, mem::transmute(__msa_srari_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srari_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(211111111155, 111111111155);
+         #[rustfmt::skip]
+         let r = i64x2::new(52777777789, 27777777789);
+ 
+         assert_eq!(r, mem::transmute(__msa_srari_d(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srl_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, -64, -32, -16,
+             -8, -4, -2, -1,
+             1, 2, 4, 8,
+             16, 32, 64, 127
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -128, 1, 3, 7,
+             15, 31, 63, 127,
+             1, 0, 0, 0,
+             1, 4, 16, 63
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srl_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srl_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             -32768, -16384, -8192, -4096,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             15, 14, 13, 12,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(1, 3, 7, 15, 0, 0, 0, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srl_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srl_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MIN, -1073741824, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(16, 15, 16, 15);
+         #[rustfmt::skip]
+         let r = i32x4::new(32768, 98304, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srl_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srl_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MIN, i64::MAX);
+         #[rustfmt::skip]
+         let b = i64x2::new(32, 31);
+         #[rustfmt::skip]
+         let r = i64x2::new(2147483648, 4294967295);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srl_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srli_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             25, 50, 100, 127,
+             25, 50, 100, 127,
+             25, 50, 100, 127,
+             25, 50, 100, 127
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             6, 12, 25, 31,
+             6, 12, 25, 31, 
+             6, 12, 25, 31, 
+             6, 12, 25, 31
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_srli_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srli_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 3276, 100, 127,
+             i16::MAX, 3276, 100, 127
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             8191, 819, 25, 31,
+             8191, 819, 25, 31
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_srli_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srli_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, i32::MAX, 100, i32::MAX);
+         #[rustfmt::skip]
+         let r = i32x4::new(25, 536870911, 25, 536870911);
+ 
+         assert_eq!(r, mem::transmute(__msa_srli_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srli_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MAX);
+         #[rustfmt::skip]
+         let r = i64x2::new(50, 4611686018427387903);
+ 
+         assert_eq!(r, mem::transmute(__msa_srli_d(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlr_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             -128, -64, -32, -16,
+             -8, -4, -2, -1,
+             1, 2, 4, 8,
+             16, 32, 64, 127
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             8, 7, 6, 5,
+             4, 3, 2, 1,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             -128, 2, 4, 8,
+             16, 32, 64, -128,
+             1, 0, 0, 0,
+             1, 4, 16, 64
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srlr_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlr_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             -32768, -16384, -8192, -4096,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             15, 14, 13, 12,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(1, 3, 7, 15, 0, 0, 1, 2);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srlr_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlr_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MIN, -1073741824, 1, 2);
+         #[rustfmt::skip]
+         let b = i32x4::new(16, 15, 16, 15);
+         let r = i32x4::new(32768, 98304, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srlr_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlr_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MIN, i64::MAX);
+         #[rustfmt::skip]
+         let b = i64x2::new(32, 31);
+         #[rustfmt::skip]
+         let r = i64x2::new(2147483648, 4294967296);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_srlr_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlri_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             25, 50, 100, i8::MAX,
+             25, 50, 100, i8::MAX,
+             25, 50, 100, i8::MAX,
+             25, 50, 100, i8::MAX
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             6, 13, 25, 32, 
+             6, 13, 25, 32, 
+             6, 13, 25, 32, 
+             6, 13, 25, 32
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_srlri_b(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlri_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 3276, 100, 127,
+             i16::MAX, 3276, 100, 127
+         );
+         let r = i16x8::new(8192, 819, 25, 32, 8192, 819, 25, 32);
+ 
+         assert_eq!(r, mem::transmute(__msa_srlri_h(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlri_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 150, 200, i32::MAX);
+         #[rustfmt::skip]
+         let r = i32x4::new(25, 38, 50, 536870912);
+ 
+         assert_eq!(r, mem::transmute(__msa_srlri_w(mem::transmute(a), 2)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_srlri_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MAX);
+         #[rustfmt::skip]
+         let r = i64x2::new(50, 4611686018427387904);
+ 
+         assert_eq!(r, mem::transmute(__msa_srlri_d(mem::transmute(a), 1)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_st_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             13, 14, 15, 16, 
+             17, 18, 19, 20, 
+             21, 22, 23, 24, 
+             25, 26, 27, 28
+         );
+         #[rustfmt::skip]
+         let mut arr : [i8; 16] = [
+             0, 0, 0, 0,
+             0, 0, 0, 0,
+             0, 0, 0, 0,
+             0, 0, 0, 0
+         ];
+         #[rustfmt::skip]
+         let r : [i8; 16] = [
+             13, 14, 15, 16, 
+             17, 18, 19, 20, 
+             21, 22, 23, 24, 
+             25, 26, 27, 28
+         ];
+         __msa_st_b(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+         assert_eq!(arr, r);
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_st_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(13, 14, 15, 16, 17, 18, 19, 20);
+         let mut arr: [i16; 8] = [0, 0, 0, 0, 0, 0, 0, 0];
+         #[rustfmt::skip]
+         let r  : [i16; 8] = [13, 14, 15, 16, 17, 18, 19, 20];
+         __msa_st_h(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+         assert_eq!(arr, r);
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_st_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(13, 14, 15, 16);
+         let mut arr: [i32; 4] = [0, 0, 0, 0];
+         #[rustfmt::skip]
+         let r  : [i32; 4] = [13, 14, 15, 16];
+         __msa_st_w(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+         assert_eq!(arr, r);
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_st_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(13, 14);
+         let mut arr: [i64; 2] = [0, 0];
+         #[rustfmt::skip]
+         let r : [i64; 2] = [13, 14];
+         __msa_st_d(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0);
+         assert_eq!(arr, r);
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_s_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             i8::MIN, -2, -3, -4,
+             i8::MIN, -2, -3, -4,
+             i8::MIN, -2, -3, -4,
+             i8::MIN, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             6, -7, 8, -9,
+             6, -7, 8, -9,
+             6, -7, 8, -9,
+             6, -7, 8, -9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             i8::MIN, 5, -11, 5,
+             i8::MIN, 5, -11, 5,
+             i8::MIN, 5, -11, 5,
+             i8::MIN, 5, -11, 5
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_s_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MIN, -2, -3, -4,
+             i16::MIN, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(6, -7, 8, -9, 6, -7, 8, -9);
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             i16::MIN, 5, -11, 5,
+             i16::MIN, 5, -11, 5
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_s_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MIN, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, -7, 8, -9);
+         #[rustfmt::skip]
+         let r = i32x4::new(i32::MIN, 5, -11, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_s_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MIN, -2);
+         #[rustfmt::skip]
+         let b = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(i64::MIN, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9,
+             6, 7, 8, 9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             249, 0, 0, 0,
+             249, 0, 0, 0,
+             249, 0, 0, 0,
+             249, 0, 0, 0
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             u16::MAX, 2, 3, 4, 
+             u16::MAX, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 9, 6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u16x8::new(65529, 0, 0, 0, 65529, 0, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(u32::MAX, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 9);
+         #[rustfmt::skip]
+         let r = u32x4::new(4294967289, 0, 0, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subs_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(u64::MAX, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = u64x2::new(18446744073709551609, 0);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subs_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsus_u_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9,
+             -6, -7, -8, -9
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             255, 9, 11, 13,
+             255, 9, 11, 13,
+             255, 9, 11, 13,
+             255, 9, 11, 13
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsus_u_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsus_u_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             u16::MAX, 2, 3, 4,
+             u16::MAX, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(-6, -7, -8, -9, -6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = u16x8::new(65535, 9, 11, 13, 65535, 9, 11, 13);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsus_u_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsus_u_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(u32::MAX, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(-6, -7, -8, -9);
+         #[rustfmt::skip]
+         let r = u32x4::new(4294967295, 9, 11, 13);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsus_u_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsus_u_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(u64::MAX, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(-6, -7);
+         #[rustfmt::skip]
+         let r = u64x2::new(18446744073709551615, 9);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsus_u_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsuu_s_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4,
+             u8::MAX, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             6, 7, 8, u8::MAX,
+             6, 7, 8, u8::MAX,
+             6, 7, 8, u8::MAX,
+             6, 7, 8, u8::MAX
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             127, -5, -5, -128,
+             127, -5, -5, -128,
+             127, -5, -5, -128,
+             127, -5, -5, -128
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsuu_s_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsuu_s_h() {
+         #[rustfmt::skip]
+         let a = u16x8::new(
+             u16::MAX, 2, 3, 
+             4, u16::MAX, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = u16x8::new(6, 7, 8, 65535, 6, 7, 8, 65535);
+         #[rustfmt::skip]
+         let r = i16x8::new(32767, -5, -5, -32768, 32767, -5, -5, -32768);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsuu_s_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsuu_s_w() {
+         #[rustfmt::skip]
+         let a = u32x4::new(u32::MAX, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = u32x4::new(6, 7, 8, 4294967295);
+         #[rustfmt::skip]
+         let r = i32x4::new(2147483647, -5, -5, -2147483648);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsuu_s_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subsuu_s_d() {
+         #[rustfmt::skip]
+         let a = u64x2::new(u64::MAX, 2);
+         #[rustfmt::skip]
+         let b = u64x2::new(6, 7);
+         #[rustfmt::skip]
+         let r = i64x2::new(i64::MAX, -5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subsuu_s_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subv_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             i8::MIN, -2, -3, -4,
+             i8::MIN, -2, -3, -4,
+             i8::MIN, -2, -3, -4,
+             i8::MIN, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             6, -7, 8, -9,
+             6, -7, 8, -9,
+             6, -7, 8, -9,
+             6, -7, 8, -9
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             122, 5, -11, 5,
+             122, 5, -11, 5,
+             122, 5, -11, 5,
+             122, 5, -11, 5
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subv_b(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subv_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MIN, -2, -3, -4,
+             i16::MIN, -2, -3, -4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(6, -7, 8, -9, 6, -7, 8, -9);
+         #[rustfmt::skip]
+         let r = i16x8::new(32762, 5, -11, 5, 32762, 5, -11, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subv_h(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subv_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(i32::MIN, -2, -3, -4);
+         #[rustfmt::skip]
+         let b = i32x4::new(6, -7, 8, -9);
+         #[rustfmt::skip]
+         let r = i32x4::new(2147483642, 5, -11, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subv_w(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subv_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(i64::MAX, -2);
+         #[rustfmt::skip]
+         let b = i64x2::new(6, -7);
+         #[rustfmt::skip]
+         let r = i64x2::new(9223372036854775801, 5);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_subv_d(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subvi_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             100, i8::MAX, 50, i8::MIN,
+             100, i8::MAX, 50, i8::MIN,
+             100, i8::MAX, 50, i8::MIN,
+             100, i8::MAX, 50, i8::MIN
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             95, 122, 45, 123,
+             95, 122, 45, 123,
+             95, 122, 45, 123,
+             95, 122, 45, 123
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_subvi_b(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subvi_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             i16::MAX, 3276, -100, i16::MIN,
+             i16::MAX, 3276, -100, i16::MIN
+         );
+         #[rustfmt::skip]
+         let r = i16x8::new(
+             32762, 3271, -105, 32763,
+             32762, 3271, -105, 32763
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_subvi_h(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subvi_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(100, 150, 200, i32::MAX);
+         #[rustfmt::skip]
+         let r = i32x4::new(95, 145, 195, 2147483642);
+ 
+         assert_eq!(r, mem::transmute(__msa_subvi_w(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_subvi_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(100, i64::MAX);
+         #[rustfmt::skip]
+         let r = i64x2::new(95, 9223372036854775802);
+ 
+         assert_eq!(r, mem::transmute(__msa_subvi_d(mem::transmute(a), 5)));
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_vshf_b() {
+         #[rustfmt::skip]
+         let a = i8x16::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let c = i8x16::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = i8x16::new(
+             3, 2, 1, 4, 
+             3, 2, 1, 4, 
+             3, 2, 1, 4, 
+             3, 2, 1, 4
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_vshf_b(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_vshf_h() {
+         #[rustfmt::skip]
+         let a = i16x8::new(
+             1, 2, 3, 4,
+             1, 2, 3, 4
+         );
+         #[rustfmt::skip]
+         let b = i16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let c = i16x8::new(
+             4, 3, 2, 1,
+             4, 3, 2, 1
+         );
+         let r = i16x8::new(3, 2, 1, 4, 3, 2, 1, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_vshf_h(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_vshf_w() {
+         #[rustfmt::skip]
+         let a = i32x4::new(1, 2, 3, 4);
+         #[rustfmt::skip]
+         let b = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let c = i32x4::new(4, 3, 2, 1);
+         #[rustfmt::skip]
+         let r = i32x4::new(3, 2, 1, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_vshf_w(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_vshf_d() {
+         #[rustfmt::skip]
+         let a = i64x2::new(1, 2);
+         #[rustfmt::skip]
+         let b = i64x2::new(4, 3);
+         #[rustfmt::skip]
+         let c = i64x2::new(4, 3);
+         #[rustfmt::skip]
+         let r = i64x2::new(3, 4);
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_vshf_d(
+                 mem::transmute(a),
+                 mem::transmute(b),
+                 mem::transmute(c)
+             ))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_xor_v() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let b = u8x16::new(
+             16, 15, 14, 13,
+             12, 11, 10, 9,
+             8, 7, 6, 5,
+             4, 3, 2, 1
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             17, 13, 13, 9, 
+             9, 13, 13, 1, 
+             1, 13, 13, 9, 
+             9, 13, 13, 17
+         );
+ 
+         assert_eq!(
+             r,
+             mem::transmute(__msa_xor_v(mem::transmute(a), mem::transmute(b)))
+         );
+     }
+ 
+     #[simd_test(enable = "msa")]
+     unsafe fn test_msa_xori_b() {
+         #[rustfmt::skip]
+         let a = u8x16::new(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16
+         );
+         #[rustfmt::skip]
+         let r = u8x16::new(
+             5, 6, 7, 0, 
+             1, 2, 3, 12, 
+             13, 14, 15, 8, 
+             9, 10, 11, 20
+         );
+ 
+         assert_eq!(r, mem::transmute(__msa_xori_b(mem::transmute(a), 4)));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,257 ----
+ //! `core_arch`
+ 
+ #[macro_use]
+ mod macros;
+ 
+ #[cfg(any(target_arch = "arm", target_arch = "aarch64", doc))]
+ mod acle;
+ 
+ mod simd;
+ 
+ #[doc(include = "core_arch_docs.md")]
+ #[stable(feature = "simd_arch", since = "1.27.0")]
+ pub mod arch {
+     /// Platform-specific intrinsics for the `x86` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "x86", doc))]
+     #[doc(cfg(target_arch = "x86"))]
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub mod x86 {
+         #[stable(feature = "simd_x86", since = "1.27.0")]
+         pub use crate::core_arch::x86::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `x86_64` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "x86_64", doc))]
+     #[doc(cfg(target_arch = "x86_64"))]
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub mod x86_64 {
+         #[stable(feature = "simd_x86", since = "1.27.0")]
+         pub use crate::core_arch::x86::*;
+         #[stable(feature = "simd_x86", since = "1.27.0")]
+         pub use crate::core_arch::x86_64::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `arm` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "arm", doc))]
+     #[doc(cfg(target_arch = "arm"))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod arm {
+         pub use crate::core_arch::arm::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `aarch64` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "aarch64", doc))]
+     #[doc(cfg(target_arch = "aarch64"))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod aarch64 {
+         pub use crate::core_arch::{aarch64::*, arm::*};
+     }
+ 
+     /// Platform-specific intrinsics for the `wasm32` platform.
+     ///
+     /// This module provides intrinsics specific to the WebAssembly
+     /// architecture. Here you'll find intrinsics necessary for leveraging
+     /// WebAssembly proposals such as [atomics] and [simd]. These proposals are
+     /// evolving over time and as such the support here is unstable and requires
+     /// the nightly channel. As WebAssembly proposals stabilize these functions
+     /// will also become stable.
+     ///
+     /// [atomics]: https://github.com/webassembly/threads
+     /// [simd]: https://github.com/webassembly/simd
+     ///
+     /// See the [module documentation](../index.html) for general information
+     /// about the `arch` module and platform intrinsics.
+     ///
+     /// ## Atomics
+     ///
+     /// The [threads proposal][atomics] for WebAssembly adds a number of
+     /// instructions for dealing with multithreaded programs. Atomic
+     /// instructions can all be generated through `std::sync::atomic` types, but
+     /// some instructions have no equivalent in Rust such as
+     /// `memory.atomic.notify` so this module will provide these intrinsics.
+     ///
+     /// At this time, however, these intrinsics are only available **when the
+     /// standard library itself is compiled with atomics**. Compiling with
+     /// atomics is not enabled by default and requires passing
+     /// `-Ctarget-feature=+atomics` to rustc. The standard library shipped via
+     /// `rustup` is not compiled with atomics. To get access to these intrinsics
+     /// you'll need to compile the standard library from source with the
+     /// requisite compiler flags.
+     ///
+     /// ## SIMD
+     ///
+     /// The [simd proposal][simd] for WebAssembly adds a new `v128` type for a
+     /// 128-bit SIMD register. It also adds a large array of instructions to
+     /// operate on the `v128` type to perform data processing. The SIMD proposal
+     /// has been in progress for quite some time and many instructions have come
+     /// and gone. This module attempts to keep up with the proposal, but if you
+     /// notice anything awry please feel free to [open an
+     /// issue](https://github.com/rust-lang/stdarch/issues/new).
+     ///
+     /// It's important to be aware that the current state of development of SIMD
+     /// in WebAssembly is still somewhat early days. There's lots of pieces to
+     /// demo and prototype with, but discussions and support are still in
+     /// progress. There's a number of pitfalls and gotchas in various places,
+     /// which will attempt to be documented here, but there may be others
+     /// lurking!
+     ///
+     /// Using SIMD is intended to be similar to as you would on `x86_64`, for
+     /// example. You'd write a function such as:
+     ///
+     /// ```rust,ignore
+     /// #[cfg(target_arch = "wasm32")]
+     /// #[target_feature(enable = "simd128")]
+     /// unsafe fn uses_simd() {
+     ///     use std::arch::wasm32::*;
+     ///     // ...
+     /// }
+     /// ```
+     ///
+     /// Unlike `x86_64`, however, WebAssembly does not currently have dynamic
+     /// detection at runtime as to whether SIMD is supported (this is one of the
+     /// motivators for the [conditional sections proposal][condsections], but
+     /// that is still pretty early days). This means that your binary will
+     /// either have SIMD and can only run on engines which support SIMD, or it
+     /// will not have SIMD at all. For compatibility the standard library itself
+     /// does not use any SIMD internally. Determining how best to ship your
+     /// WebAssembly binary with SIMD is largely left up to you as it can can be
+     /// pretty nuanced depending on your situation.
+     ///
+     /// [condsections]: https://github.com/webassembly/conditional-sections
+     ///
+     /// To enable SIMD support at compile time you need to do one of two things:
+     ///
+     /// * First you can annotate functions with `#[target_feature(enable =
+     ///   "simd128")]`. This causes just that one function to have SIMD support
+     ///   available to it, and intrinsics will get inlined as usual in this
+     ///   situation.
+     ///
+     /// * Second you can compile your program with `-Ctarget-feature=+simd128`.
+     ///   This compilation flag blanket enables SIMD support for your entire
+     ///   compilation. Note that this does not include the standard library
+     ///   unless you recompile the standard library.
+     ///
+     /// If you enable SIMD via either of these routes then you'll have a
+     /// WebAssembly binary that uses SIMD instructions, and you'll need to ship
+     /// that accordingly. Also note that if you call SIMD intrinsics but don't
+     /// enable SIMD via either of these mechanisms, you'll still have SIMD
+     /// generated in your program. This means to generate a binary without SIMD
+     /// you'll need to avoid both options above plus calling into any intrinsics
+     /// in this module.
+     ///
+     /// > **Note**: Due to
+     /// > [rust-lang/rust#74320](https://github.com/rust-lang/rust/issues/74320)
+     /// > it's recommended to compile your entire program with SIMD support
+     /// > (using `RUSTFLAGS`) or otherwise functions may not be inlined
+     /// > correctly.
+     ///
+     /// > **Note**: LLVM's SIMD support is actually split into two features:
+     /// > `simd128` and `unimplemented-simd128`. Rust code can enable `simd128`
+     /// > with `#[target_feature]` (and test for it with `#[cfg(target_feature =
+     /// > "simd128")]`, but it cannot enable `unimplemented-simd128`. The only
+     /// > way to enable this feature is to compile with
+     /// > `-Ctarget-feature=+simd128,+unimplemented-simd128`. This second
+     /// > feature enables more recent instructions implemented in LLVM which
+     /// > haven't always had enough time to make their way to runtimes.
+     #[cfg(any(target_arch = "wasm32", doc))]
+     #[doc(cfg(target_arch = "wasm32"))]
+     #[stable(feature = "simd_wasm32", since = "1.33.0")]
+     pub mod wasm32 {
+         #[stable(feature = "simd_wasm32", since = "1.33.0")]
+         pub use crate::core_arch::wasm32::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `mips` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "mips", doc))]
+     #[doc(cfg(target_arch = "mips"))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod mips {
+         pub use crate::core_arch::mips::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `mips64` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "mips64", doc))]
+     #[doc(cfg(target_arch = "mips64"))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod mips64 {
+         pub use crate::core_arch::mips::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `PowerPC` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "powerpc", doc))]
+     #[doc(cfg(target_arch = "powerpc"))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod powerpc {
+         pub use crate::core_arch::powerpc::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `PowerPC64` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "powerpc64", doc))]
+     #[doc(cfg(target_arch = "powerpc64"))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod powerpc64 {
+         pub use crate::core_arch::powerpc64::*;
+     }
+ 
+     /// Platform-specific intrinsics for the `NVPTX` platform.
+     ///
+     /// See the [module documentation](../index.html) for more details.
+     #[cfg(any(target_arch = "nvptx", target_arch = "nvptx64", doc))]
+     #[doc(cfg(any(target_arch = "nvptx", target_arch = "nvptx64")))]
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     pub mod nvptx {
+         pub use crate::core_arch::nvptx::*;
+     }
+ }
+ 
+ mod simd_llvm;
+ 
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64", doc))]
+ #[doc(cfg(any(target_arch = "x86", target_arch = "x86_64")))]
+ mod x86;
+ #[cfg(any(target_arch = "x86_64", doc))]
+ #[doc(cfg(target_arch = "x86_64"))]
+ mod x86_64;
+ 
+ #[cfg(any(target_arch = "aarch64", doc))]
+ #[doc(cfg(target_arch = "aarch64"))]
+ mod aarch64;
+ #[cfg(any(target_arch = "arm", target_arch = "aarch64", doc))]
+ #[doc(cfg(any(target_arch = "arm", target_arch = "aarch64")))]
+ mod arm;
+ 
+ #[cfg(any(target_arch = "wasm32", doc))]
+ #[doc(cfg(target_arch = "wasm32"))]
+ mod wasm32;
+ 
+ #[cfg(any(target_arch = "mips", target_arch = "mips64", doc))]
+ #[doc(cfg(any(target_arch = "mips", target_arch = "mips64")))]
+ mod mips;
+ 
+ #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64", doc))]
+ #[doc(cfg(any(target_arch = "powerpc", target_arch = "powerpc64")))]
+ mod powerpc;
+ 
+ #[cfg(any(target_arch = "powerpc64", doc))]
+ #[doc(cfg(target_arch = "powerpc64"))]
+ mod powerpc64;
+ 
+ #[cfg(any(target_arch = "nvptx", target_arch = "nvptx64", doc))]
+ #[doc(cfg(any(target_arch = "nvptx", target_arch = "nvptx64")))]
+ mod nvptx;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/nvptx/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/nvptx/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/nvptx/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/nvptx/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,213 ----
+ //! NVPTX intrinsics (experimental)
+ //!
+ //! These intrinsics form the foundation of the CUDA
+ //! programming model.
+ //!
+ //! The reference is the [CUDA C Programming Guide][cuda_c]. Relevant is also
+ //! the [LLVM NVPTX Backend documentation][llvm_docs].
+ //!
+ //! [cuda_c]:
+ //! http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
+ //! [llvm_docs]:
+ //! https://llvm.org/docs/NVPTXUsage.html
+ 
+ use crate::ffi::c_void;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.nvvm.barrier0"]
+     fn syncthreads() -> ();
+     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.x"]
+     fn block_dim_x() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.y"]
+     fn block_dim_y() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.z"]
+     fn block_dim_z() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.x"]
+     fn block_idx_x() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.y"]
+     fn block_idx_y() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.z"]
+     fn block_idx_z() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.x"]
+     fn grid_dim_x() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.y"]
+     fn grid_dim_y() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.z"]
+     fn grid_dim_z() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.x"]
+     fn thread_idx_x() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.y"]
+     fn thread_idx_y() -> i32;
+     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.z"]
+     fn thread_idx_z() -> i32;
+ }
+ 
+ /// Synchronizes all threads in the block.
+ #[inline]
+ pub unsafe fn _syncthreads() -> () {
+     syncthreads()
+ }
+ 
+ /// x-th thread-block dimension.
+ #[inline]
+ pub unsafe fn _block_dim_x() -> i32 {
+     block_dim_x()
+ }
+ 
+ /// y-th thread-block dimension.
+ #[inline]
+ pub unsafe fn _block_dim_y() -> i32 {
+     block_dim_y()
+ }
+ 
+ /// z-th thread-block dimension.
+ #[inline]
+ pub unsafe fn _block_dim_z() -> i32 {
+     block_dim_z()
+ }
+ 
+ /// x-th thread-block index.
+ #[inline]
+ pub unsafe fn _block_idx_x() -> i32 {
+     block_idx_x()
+ }
+ 
+ /// y-th thread-block index.
+ #[inline]
+ pub unsafe fn _block_idx_y() -> i32 {
+     block_idx_y()
+ }
+ 
+ /// z-th thread-block index.
+ #[inline]
+ pub unsafe fn _block_idx_z() -> i32 {
+     block_idx_z()
+ }
+ 
+ /// x-th block-grid dimension.
+ #[inline]
+ pub unsafe fn _grid_dim_x() -> i32 {
+     grid_dim_x()
+ }
+ 
+ /// y-th block-grid dimension.
+ #[inline]
+ pub unsafe fn _grid_dim_y() -> i32 {
+     grid_dim_y()
+ }
+ 
+ /// z-th block-grid dimension.
+ #[inline]
+ pub unsafe fn _grid_dim_z() -> i32 {
+     grid_dim_z()
+ }
+ 
+ /// x-th thread index.
+ #[inline]
+ pub unsafe fn _thread_idx_x() -> i32 {
+     thread_idx_x()
+ }
+ 
+ /// y-th thread index.
+ #[inline]
+ pub unsafe fn _thread_idx_y() -> i32 {
+     thread_idx_y()
+ }
+ 
+ /// z-th thread index.
+ #[inline]
+ pub unsafe fn _thread_idx_z() -> i32 {
+     thread_idx_z()
+ }
+ 
+ /// Generates the trap instruction `TRAP`
+ #[inline]
+ pub unsafe fn trap() -> ! {
+     crate::intrinsics::abort()
+ }
+ 
+ // Basic CUDA syscall declarations.
+ extern "C" {
+     /// Print formatted output from a kernel to a host-side output stream.
+     ///
+     /// Syscall arguments:
+     /// * `status`: The status value that is returned by `vprintf`.
+     /// * `format`: A pointer to the format specifier input (uses common `printf` format).
+     /// * `valist`: A pointer to the valist input.
+     ///
+     /// ```
+     /// #[repr(C)]
+     /// struct PrintArgs(f32, f32, f32, i32);
+     ///
+     /// vprintf(
+     ///     "int(%f + %f) = int(%f) = %d\n".as_ptr(),
+     ///     transmute(&PrintArgs(a, b, a + b, (a + b) as i32)),
+     /// );
+     /// ```
+     ///
+     /// Sources:
+     /// [Programming Guide](https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#formatted-output),
+     /// [PTX Interoperability](https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#system-calls).
+     pub fn vprintf(format: *const u8, valist: *const c_void) -> i32;
+ 
+     /// Allocate memory dynamically from a fixed-size heap in global memory.
+     ///
+     /// The CUDA in-kernel `malloc()` function allocates at least `size` bytes
+     /// from the device heap and returns a pointer to the allocated memory
+     /// or `NULL` if insufficient memory exists to fulfill the request.
+     ///
+     /// The returned pointer is guaranteed to be aligned to a 16-byte boundary.
+     ///
+     /// The memory allocated by a given CUDA thread via `malloc()` remains allocated
+     /// for the lifetime of the CUDA context, or until it is explicitly released
+     /// by a call to `free()`. It can be used by any other CUDA threads
+     /// even from subsequent kernel launches.
+     ///
+     /// Sources:
+     /// [Programming Guide](https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#dynamic-global-memory-allocation-and-operations),
+     /// [PTX Interoperability](https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#system-calls).
+     // FIXME(denzp): assign `malloc` and `nothrow` attributes.
+     pub fn malloc(size: usize) -> *mut c_void;
+ 
+     /// Free previously dynamically allocated memory.
+     ///
+     /// The CUDA in-kernel `free()` function deallocates the memory pointed to by `ptr`,
+     /// which must have been returned by a previous call to `malloc()`. If `ptr` is NULL,
+     /// the call to `free()` is ignored.
+     ///
+     /// Any CUDA thread may free memory allocated by another thread, but care should be taken
+     /// to ensure that the same pointer is not freed more than once. Repeated calls to `free()`
+     /// with the same `ptr` has undefined behavior.
+     ///
+     /// Sources:
+     /// [Programming Guide](https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#dynamic-global-memory-allocation-and-operations),
+     /// [PTX Interoperability](https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#system-calls).
+     // FIXME(denzp): assign `nothrow` attribute.
+     pub fn free(ptr: *mut c_void);
+ 
+     // Internal declaration of the syscall. Exported variant has
+     // the `char_size` parameter set to `1` (single char size in bytes).
+     fn __assertfail(
+         message: *const u8,
+         file: *const u8,
+         line: u32,
+         function: *const u8,
+         char_size: usize,
+     );
+ }
+ 
+ /// Syscall to be used whenever the *assert expression produces a `false` value*.
+ ///
+ /// Syscall arguments:
+ /// * `message`: The pointer to the string that should be output.
+ /// * `file`: The pointer to the file name string associated with the assert.
+ /// * `line`: The line number associated with the assert.
+ /// * `function`: The pointer to the function name string associated with the assert.
+ ///
+ /// Source:
+ /// [PTX Interoperability](https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#system-calls).
+ #[inline]
+ pub unsafe fn __assert_fail(message: *const u8, file: *const u8, line: u32, function: *const u8) {
+     __assertfail(message, file, line, function, 1)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/altivec.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/altivec.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/altivec.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/altivec.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2777 ----
+ //! PowerPC AltiVec intrinsics.
+ //!
+ //! AltiVec is a brandname trademarked by Freescale (previously Motorola) for
+ //! the standard `Category:Vector` part of the Power ISA v.2.03 specification.
+ //! This Category is also known as VMX (used by IBM), and "Velocity Engine" (a
+ //! brand name previously used by Apple).
+ //!
+ //! The references are: [POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA
+ //! NVlink)] and [POWER ISA v3.0B (for POWER9)].
+ //!
+ //! [POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA NVlink)]: https://ibm.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u
+ //! [POWER ISA v3.0B (for POWER9)]: https://ibm.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv
+ 
+ #![allow(non_camel_case_types)]
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*},
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ types! {
+     /// PowerPC-specific 128-bit wide vector of sixteen packed `i8`
+     pub struct vector_signed_char(i8, i8, i8, i8, i8, i8, i8, i8,
+                                   i8, i8, i8, i8, i8, i8, i8, i8);
+     /// PowerPC-specific 128-bit wide vector of sixteen packed `u8`
+     pub struct vector_unsigned_char(u8, u8, u8, u8, u8, u8, u8, u8,
+                                     u8, u8, u8, u8, u8, u8, u8, u8);
+ 
+     /// PowerPC-specific 128-bit wide vector mask of sixteen packed elements
+     pub struct vector_bool_char(i8, i8, i8, i8, i8, i8, i8, i8,
+                                 i8, i8, i8, i8, i8, i8, i8, i8);
+     /// PowerPC-specific 128-bit wide vector of eight packed `i16`
+     pub struct vector_signed_short(i16, i16, i16, i16, i16, i16, i16, i16);
+     /// PowerPC-specific 128-bit wide vector of eight packed `u16`
+     pub struct vector_unsigned_short(u16, u16, u16, u16, u16, u16, u16, u16);
+     /// PowerPC-specific 128-bit wide vector mask of eight packed elements
+     pub struct vector_bool_short(i16, i16, i16, i16, i16, i16, i16, i16);
+     // pub struct vector_pixel(???);
+     /// PowerPC-specific 128-bit wide vector of four packed `i32`
+     pub struct vector_signed_int(i32, i32, i32, i32);
+     /// PowerPC-specific 128-bit wide vector of four packed `u32`
+     pub struct vector_unsigned_int(u32, u32, u32, u32);
+     /// PowerPC-specific 128-bit wide vector mask of four packed elements
+     pub struct vector_bool_int(i32, i32, i32, i32);
+     /// PowerPC-specific 128-bit wide vector of four packed `f32`
+     pub struct vector_float(f32, f32, f32, f32);
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.ppc.altivec.vperm"]
+     fn vperm(
+         a: vector_signed_int,
+         b: vector_signed_int,
+         c: vector_unsigned_char,
+     ) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vmhaddshs"]
+     fn vmhaddshs(
+         a: vector_signed_short,
+         b: vector_signed_short,
+         c: vector_signed_short,
+     ) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vmhraddshs"]
+     fn vmhraddshs(
+         a: vector_signed_short,
+         b: vector_signed_short,
+         c: vector_signed_short,
+     ) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vmsumuhs"]
+     fn vmsumuhs(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+         c: vector_unsigned_int,
+     ) -> vector_unsigned_int;
+     #[link_name = "llvm.ppc.altivec.vmsumshs"]
+     fn vmsumshs(
+         a: vector_signed_short,
+         b: vector_signed_short,
+         c: vector_signed_int,
+     ) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vmsumubm"]
+     fn vmsumubm(
+         a: vector_unsigned_char,
+         b: vector_unsigned_char,
+         c: vector_unsigned_int,
+     ) -> vector_unsigned_int;
+     #[link_name = "llvm.ppc.altivec.vmsummbm"]
+     fn vmsummbm(
+         a: vector_signed_char,
+         b: vector_unsigned_char,
+         c: vector_signed_int,
+     ) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vmsumuhm"]
+     fn vmsumuhm(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+         c: vector_unsigned_int,
+     ) -> vector_unsigned_int;
+     #[link_name = "llvm.ppc.altivec.vmsumshm"]
+     fn vmsumshm(
+         a: vector_signed_short,
+         b: vector_signed_short,
+         c: vector_signed_int,
+     ) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vmaddfp"]
+     fn vmaddfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float;
+     #[link_name = "llvm.ppc.altivec.vnmsubfp"]
+     fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float;
+     #[link_name = "llvm.ppc.altivec.vsum2sws"]
+     fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vsum4ubs"]
+     fn vsum4ubs(a: vector_unsigned_char, b: vector_unsigned_int) -> vector_unsigned_int;
+     #[link_name = "llvm.ppc.altivec.vsum4sbs"]
+     fn vsum4sbs(a: vector_signed_char, b: vector_signed_int) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vsum4shs"]
+     fn vsum4shs(a: vector_signed_short, b: vector_signed_int) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vmuleub"]
+     fn vmuleub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vmulesb"]
+     fn vmulesb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vmuleuh"]
+     fn vmuleuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_int;
+     #[link_name = "llvm.ppc.altivec.vmulesh"]
+     fn vmulesh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;
+     #[link_name = "llvm.ppc.altivec.vmuloub"]
+     fn vmuloub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vmulosb"]
+     fn vmulosb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vmulouh"]
+     fn vmulouh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_int;
+     #[link_name = "llvm.ppc.altivec.vmulosh"]
+     fn vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vmaxsb"]
+     fn vmaxsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
+     #[link_name = "llvm.ppc.altivec.vmaxsh"]
+     fn vmaxsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vmaxsw"]
+     fn vmaxsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vmaxub"]
+     fn vmaxub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
+     #[link_name = "llvm.ppc.altivec.vmaxuh"]
+     fn vmaxuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vmaxuw"]
+     fn vmaxuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vminsb"]
+     fn vminsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
+     #[link_name = "llvm.ppc.altivec.vminsh"]
+     fn vminsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vminsw"]
+     fn vminsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vminub"]
+     fn vminub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
+     #[link_name = "llvm.ppc.altivec.vminuh"]
+     fn vminuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vminuw"]
+     fn vminuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vsubsbs"]
+     fn vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
+     #[link_name = "llvm.ppc.altivec.vsubshs"]
+     fn vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vsubsws"]
+     fn vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vsububs"]
+     fn vsububs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
+     #[link_name = "llvm.ppc.altivec.vsubuhs"]
+     fn vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vsubuws"]
+     fn vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vaddcuw"]
+     fn vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vaddsbs"]
+     fn vaddsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
+     #[link_name = "llvm.ppc.altivec.vaddshs"]
+     fn vaddshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vaddsws"]
+     fn vaddsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vaddubs"]
+     fn vaddubs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
+     #[link_name = "llvm.ppc.altivec.vadduhs"]
+     fn vadduhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vadduws"]
+     fn vadduws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vavgsb"]
+     fn vavgsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
+     #[link_name = "llvm.ppc.altivec.vavgsh"]
+     fn vavgsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
+     #[link_name = "llvm.ppc.altivec.vavgsw"]
+     fn vavgsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vavgub"]
+     fn vavgub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
+     #[link_name = "llvm.ppc.altivec.vavguh"]
+     fn vavguh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
+     #[link_name = "llvm.ppc.altivec.vavguw"]
+     fn vavguw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
+ 
+     #[link_name = "llvm.ceil.v4f32"]
+     fn vceil(a: vector_float) -> vector_float;
+ 
+     #[link_name = "llvm.ppc.altivec.vcmpbfp"]
+     fn vcmpbfp(a: vector_float, b: vector_float) -> vector_signed_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vcmpequb"]
+     fn vcmpequb(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char;
+     #[link_name = "llvm.ppc.altivec.vcmpequh"]
+     fn vcmpequh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short;
+     #[link_name = "llvm.ppc.altivec.vcmpequw"]
+     fn vcmpequw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vcmpgefp"]
+     fn vcmpgefp(a: vector_float, b: vector_float) -> vector_bool_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vcmpgtub"]
+     fn vcmpgtub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char;
+     #[link_name = "llvm.ppc.altivec.vcmpgtuh"]
+     fn vcmpgtuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short;
+     #[link_name = "llvm.ppc.altivec.vcmpgtuw"]
+     fn vcmpgtuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vcmpgtsb"]
+     fn vcmpgtsb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char;
+     #[link_name = "llvm.ppc.altivec.vcmpgtsh"]
+     fn vcmpgtsh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short;
+     #[link_name = "llvm.ppc.altivec.vcmpgtsw"]
+     fn vcmpgtsw(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int;
+ 
+     #[link_name = "llvm.ppc.altivec.vexptefp"]
+     fn vexptefp(a: vector_float) -> vector_float;
+ 
+     #[link_name = "llvm.floor.v4f32"]
+     fn vfloor(a: vector_float) -> vector_float;
+ }
+ 
+ macro_rules! s_t_l {
+     (i32x4) => {
+         vector_signed_int
+     };
+     (i16x8) => {
+         vector_signed_short
+     };
+     (i8x16) => {
+         vector_signed_char
+     };
+ 
+     (u32x4) => {
+         vector_unsigned_int
+     };
+     (u16x8) => {
+         vector_unsigned_short
+     };
+     (u8x16) => {
+         vector_unsigned_char
+     };
+ 
+     (f32x4) => {
+         vector_float
+     };
+ }
+ 
+ macro_rules! t_t_l {
+     (i32) => {
+         vector_signed_int
+     };
+     (i16) => {
+         vector_signed_short
+     };
+     (i8) => {
+         vector_signed_char
+     };
+ 
+     (u32) => {
+         vector_unsigned_int
+     };
+     (u16) => {
+         vector_unsigned_short
+     };
+     (u8) => {
+         vector_unsigned_char
+     };
+ 
+     (f32) => {
+         vector_float
+     };
+ }
+ 
+ macro_rules! impl_from {
+     ($s: ident) => {
+         impl From<$s> for s_t_l!($s) {
+             fn from (v: $s) -> Self {
+                 unsafe {
+                     transmute(v)
+                 }
+             }
+         }
+     };
+     ($($s: ident),*) => {
+         $(
+             impl_from! { $s }
+         )*
+     };
+ }
+ 
+ impl_from! { i8x16, u8x16,  i16x8, u16x8, i32x4, u32x4, f32x4 }
+ 
+ macro_rules! impl_neg {
+     ($s: ident : $zero: expr) => {
+         impl crate::ops::Neg for s_t_l!($s) {
+             type Output = s_t_l!($s);
+             fn neg(self) -> Self::Output {
+                 let zero = $s::splat($zero);
+                 unsafe { transmute(simd_sub(zero, transmute(self))) }
+             }
+         }
+     };
+ }
+ 
+ impl_neg! { i8x16 : 0 }
+ impl_neg! { i16x8 : 0 }
+ impl_neg! { i32x4 : 0 }
+ impl_neg! { f32x4 : 0f32 }
+ 
+ mod sealed {
+     use super::*;
+ 
+     macro_rules! test_impl {
+         ($fun:ident ($($v:ident : $ty:ty),*) -> $r:ty [$call:ident, $instr:ident]) => {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             #[cfg_attr(test, assert_instr($instr))]
+             pub unsafe fn $fun ($($v : $ty),*) -> $r {
+                 $call ($($v),*)
+             }
+         };
+         ($fun:ident ($($v:ident : $ty:ty),*) -> $r:ty [$call:ident, $instr_altivec:ident / $instr_vsx:ident]) => {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             #[cfg_attr(all(test, not(target_feature="vsx")), assert_instr($instr_altivec))]
+             #[cfg_attr(all(test, target_feature="vsx"), assert_instr($instr_vsx))]
+             pub unsafe fn $fun ($($v : $ty),*) -> $r {
+                 $call ($($v),*)
+             }
+         }
+ 
+     }
+ 
+     macro_rules! impl_vec_trait {
+         ([$Trait:ident $m:ident] $fun:ident ($a:ty)) => {
+             impl $Trait for $a {
+                 #[inline]
+                 #[target_feature(enable = "altivec")]
+                 unsafe fn $m(self) -> Self {
+                     $fun(transmute(self))
+                 }
+             }
+         };
+         ([$Trait:ident $m:ident] $fun:ident ($a:ty) -> $r:ty) => {
+             impl $Trait for $a {
+                 type Result = $r;
+                 #[inline]
+                 #[target_feature(enable = "altivec")]
+                 unsafe fn $m(self) -> Self::Result {
+                     $fun(transmute(self))
+                 }
+             }
+         };
+         ([$Trait:ident $m:ident] 1 ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident, $sf: ident)) => {
+             impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char) -> vector_unsigned_char }
+             impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char) -> vector_signed_char }
+             impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short) -> vector_unsigned_short }
+             impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short) -> vector_signed_short }
+             impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int) -> vector_unsigned_int }
+             impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int) -> vector_signed_int }
+             impl_vec_trait!{ [$Trait $m] $sf (vector_float) -> vector_float }
+         };
+         ([$Trait:ident $m:ident] $fun:ident ($a:ty, $b:ty) -> $r:ty) => {
+             impl $Trait<$b> for $a {
+                 type Result = $r;
+                 #[inline]
+                 #[target_feature(enable = "altivec")]
+                 unsafe fn $m(self, b: $b) -> Self::Result {
+                     $fun(transmute(self), transmute(b))
+                 }
+             }
+         };
+         ([$Trait:ident $m:ident] $fun:ident ($a:ty, ~$b:ty) -> $r:ty) => {
+             impl_vec_trait!{ [$Trait $m] $fun ($a, $a) -> $r }
+             impl_vec_trait!{ [$Trait $m] $fun ($a, $b) -> $r }
+             impl_vec_trait!{ [$Trait $m] $fun ($b, $a) -> $r }
+         };
+         ([$Trait:ident $m:ident] ~($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
+             impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, ~vector_bool_char) -> vector_unsigned_char }
+             impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, ~vector_bool_char) -> vector_signed_char }
+             impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, ~vector_bool_short) -> vector_unsigned_short }
+             impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, ~vector_bool_short) -> vector_signed_short }
+             impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, ~vector_bool_int) -> vector_unsigned_int }
+             impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, ~vector_bool_int) -> vector_signed_int }
+         };
+         ([$Trait:ident $m:ident] ~($fn:ident)) => {
+             impl_vec_trait!{ [$Trait $m] ~($fn, $fn, $fn, $fn, $fn, $fn) }
+         };
+         ([$Trait:ident $m:ident] 2 ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
+             impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
+             impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, vector_signed_char) -> vector_signed_char }
+             impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_short }
+             impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, vector_signed_short) -> vector_signed_short }
+             impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_int }
+             impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, vector_signed_int) -> vector_signed_int }
+         };
+         ([$Trait:ident $m:ident] 2 ($fn:ident)) => {
+             impl_vec_trait!{ [$Trait $m] ($fn, $fn, $fn, $fn, $fn, $fn) }
+         }
+     }
+ 
+     macro_rules! impl_vec_cmp {
+         ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
+             impl_vec_cmp! { [$Trait $m] ($b, $b, $h, $h, $w, $w) }
+         };
+         ([$Trait:ident $m:ident] ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
+             impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, vector_unsigned_char) -> vector_bool_char }
+             impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, vector_signed_char) -> vector_bool_char }
+             impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, vector_unsigned_short) -> vector_bool_short }
+             impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, vector_signed_short) -> vector_bool_short }
+             impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, vector_unsigned_int) -> vector_bool_int }
+             impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, vector_signed_int) -> vector_bool_int }
+         }
+     }
+ 
+     #[inline(always)]
+     unsafe fn load(off: i32, p: *const i8) -> u32x4 {
+         let addr = p.offset(off as isize);
+ 
+         *(addr as *const u32x4)
+     }
+ 
+     pub trait VectorLd {
+         type Result;
+         unsafe fn vec_ld(self, off: i32) -> Self::Result;
+     }
+ 
+     macro_rules! impl_vec_ld {
+         ($fun:ident $ty:ident [$instr:ident]) => {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             #[cfg_attr(test, assert_instr($instr))]
+             pub unsafe fn $fun(off: i32, p: *const $ty) -> t_t_l!($ty) {
+                 transmute(load(off, p as *const i8))
+             }
+ 
+             impl VectorLd for *const $ty {
+                 type Result = t_t_l!($ty);
+                 #[inline]
+                 #[target_feature(enable = "altivec")]
+                 unsafe fn vec_ld(self, off: i32) -> Self::Result {
+                     $fun(off, self)
+                 }
+             }
+         };
+         ($fun:ident $ty:ident) => {
+             impl_vec_ld! { $fun $ty [lvx] }
+         };
+     }
+ 
+     impl_vec_ld! { vec_ld_u8 u8 }
+     impl_vec_ld! { vec_ld_i8 i8 }
+ 
+     impl_vec_ld! { vec_ld_u16 u16 }
+     impl_vec_ld! { vec_ld_i16 i16 }
+ 
+     impl_vec_ld! { vec_ld_u32 u32 }
+     impl_vec_ld! { vec_ld_i32 i32 }
+ 
+     impl_vec_ld! { vec_ld_f32 f32 }
+ 
+     test_impl! { vec_floor(a: vector_float) -> vector_float [ vfloor, vrfim / xvrspim ] }
+ 
+     test_impl! { vec_vexptefp(a: vector_float) -> vector_float [ vexptefp, vexptefp ] }
+ 
+     test_impl! { vec_vcmpgtub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char [ vcmpgtub, vcmpgtub ] }
+     test_impl! { vec_vcmpgtuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short [ vcmpgtuh, vcmpgtuh ] }
+     test_impl! { vec_vcmpgtuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int [ vcmpgtuw, vcmpgtuw ] }
+ 
+     test_impl! { vec_vcmpgtsb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char [ vcmpgtsb, vcmpgtsb ] }
+     test_impl! { vec_vcmpgtsh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short [ vcmpgtsh, vcmpgtsh ] }
+     test_impl! { vec_vcmpgtsw(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int [ vcmpgtsw, vcmpgtsw ] }
+ 
+     pub trait VectorCmpGt<Other> {
+         type Result;
+         unsafe fn vec_cmpgt(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_cmp! { [VectorCmpGt vec_cmpgt] ( vec_vcmpgtub, vec_vcmpgtsb, vec_vcmpgtuh, vec_vcmpgtsh, vec_vcmpgtuw, vec_vcmpgtsw ) }
+ 
+     test_impl! { vec_vcmpgefp(a: vector_float, b: vector_float) -> vector_bool_int [ vcmpgefp, vcmpgefp ] }
+ 
+     test_impl! { vec_vcmpequb(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char [ vcmpequb, vcmpequb ] }
+     test_impl! { vec_vcmpequh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short [ vcmpequh, vcmpequh ] }
+     test_impl! { vec_vcmpequw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int [ vcmpequw, vcmpequw ] }
+ 
+     pub trait VectorCmpEq<Other> {
+         type Result;
+         unsafe fn vec_cmpeq(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_cmp! { [VectorCmpEq vec_cmpeq] (vec_vcmpequb, vec_vcmpequh, vec_vcmpequw) }
+ 
+     test_impl! { vec_vcmpbfp(a: vector_float, b: vector_float) -> vector_signed_int [vcmpbfp, vcmpbfp] }
+ 
+     test_impl! { vec_vceil(a: vector_float) -> vector_float [vceil, vrfip / xvrspip ] }
+ 
+     test_impl! { vec_vavgsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vavgsb, vavgsb ] }
+     test_impl! { vec_vavgsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vavgsh, vavgsh ] }
+     test_impl! { vec_vavgsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vavgsw, vavgsw ] }
+     test_impl! { vec_vavgub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vavgub, vavgub ] }
+     test_impl! { vec_vavguh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vavguh, vavguh ] }
+     test_impl! { vec_vavguw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vavguw, vavguw ] }
+ 
+     pub trait VectorAvg<Other> {
+         type Result;
+         unsafe fn vec_avg(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorAvg vec_avg] 2 (vec_vavgub, vec_vavgsb, vec_vavguh, vec_vavgsh, vec_vavguw, vec_vavgsw) }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vandc))]
+     #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlandc))]
+     unsafe fn andc(a: u8x16, b: u8x16) -> u8x16 {
+         simd_and(simd_xor(u8x16::splat(0xff), b), a)
+     }
+ 
+     pub trait VectorAndc<Other> {
+         type Result;
+         unsafe fn vec_andc(self, b: Other) -> Self::Result;
+     }
+ 
+     macro_rules! impl_vec_andc {
+         (($a:ty, $b:ty) -> $r:ty) => {
+             impl VectorAndc<$b> for $a {
+                 type Result = $r;
+                 #[inline]
+                 #[target_feature(enable = "altivec")]
+                 unsafe fn vec_andc(self, b: $b) -> Self::Result {
+                     transmute(andc(transmute(self), transmute(b)))
+                 }
+             }
+         };
+         (($a:ty, ~$b:ty) -> $r:ty) => {
+             impl_vec_andc! { ($a, $a) -> $r }
+             impl_vec_andc! { ($a, $b) -> $r }
+             impl_vec_andc! { ($b, $a) -> $r }
+         };
+     }
+ 
+     impl_vec_andc! { (vector_unsigned_char, ~vector_bool_char) -> vector_unsigned_char }
+     impl_vec_andc! { (vector_signed_char, ~vector_bool_char) -> vector_signed_char }
+     impl_vec_andc! { (vector_unsigned_short, ~vector_bool_short) -> vector_unsigned_short }
+     impl_vec_andc! { (vector_signed_short, ~vector_bool_short) -> vector_signed_short }
+     impl_vec_andc! { (vector_unsigned_int, ~vector_bool_int) -> vector_unsigned_int }
+     impl_vec_andc! { (vector_signed_int, ~vector_bool_int) -> vector_signed_int }
+ 
+     test_impl! { vec_vand(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ simd_and, vand / xxland ] }
+ 
+     pub trait VectorAnd<Other> {
+         type Result;
+         unsafe fn vec_and(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorAnd vec_and] ~(simd_and) }
+ 
+     test_impl! { vec_vaddsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vaddsbs, vaddsbs ] }
+     test_impl! { vec_vaddshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vaddshs, vaddshs ] }
+     test_impl! { vec_vaddsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vaddsws, vaddsws ] }
+     test_impl! { vec_vaddubs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vaddubs, vaddubs ] }
+     test_impl! { vec_vadduhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vadduhs, vadduhs ] }
+     test_impl! { vec_vadduws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vadduws, vadduws ] }
+ 
+     pub trait VectorAdds<Other> {
+         type Result;
+         unsafe fn vec_adds(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorAdds vec_adds] ~(vaddubs, vaddsbs, vadduhs, vaddshs, vadduws, vaddsws) }
+ 
+     test_impl! { vec_vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vaddcuw, vaddcuw] }
+ 
+     test_impl! { vec_vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vsubsbs, vsubsbs ] }
+     test_impl! { vec_vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vsubshs, vsubshs ] }
+     test_impl! { vec_vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vsubsws, vsubsws ] }
+     test_impl! { vec_vsububs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vsububs, vsububs ] }
+     test_impl! { vec_vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vsubuhs, vsubuhs ] }
+     test_impl! { vec_vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vsubuws, vsubuws ] }
+ 
+     pub trait VectorSubs<Other> {
+         type Result;
+         unsafe fn vec_subs(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorSubs vec_subs] ~(vsububs, vsubsbs, vsubuhs, vsubshs, vsubuws, vsubsws) }
+ 
+     pub trait VectorAbs {
+         unsafe fn vec_abs(self) -> Self;
+     }
+ 
+     macro_rules! impl_abs {
+         ($name:ident,  $ty: ident) => {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
+                 v.vec_max(-v)
+             }
+ 
+             impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
+         };
+     }
+ 
+     impl_abs! { vec_abs_i8, i8x16 }
+     impl_abs! { vec_abs_i16, i16x8 }
+     impl_abs! { vec_abs_i32, i32x4 }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     unsafe fn vec_abs_f32(v: vector_float) -> vector_float {
+         let v: u32x4 = transmute(v);
+ 
+         transmute(simd_and(v, u32x4::splat(0x7FFFFFFF)))
+     }
+ 
+     impl_vec_trait! { [VectorAbs vec_abs] vec_abs_f32 (vector_float) }
+ 
+     pub trait VectorAbss {
+         unsafe fn vec_abss(self) -> Self;
+     }
+ 
+     macro_rules! impl_abss {
+         ($name:ident,  $ty: ident) => {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
+                 let zero: s_t_l!($ty) = transmute(0u8.vec_splats());
+                 v.vec_max(zero.vec_subs(v))
+             }
+ 
+             impl_vec_trait! { [VectorAbss vec_abss] $name (s_t_l!($ty)) }
+         };
+     }
+ 
+     impl_abss! { vec_abss_i8, i8x16 }
+     impl_abss! { vec_abss_i16, i16x8 }
+     impl_abss! { vec_abss_i32, i32x4 }
+ 
+     macro_rules! splats {
+         ($name:ident, $v:ident, $r:ident) => {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             unsafe fn $name(v: $v) -> s_t_l!($r) {
+                 transmute($r::splat(v))
+             }
+         };
+     }
+ 
+     splats! { splats_u8, u8, u8x16 }
+     splats! { splats_u16, u16, u16x8 }
+     splats! { splats_u32, u32, u32x4 }
+     splats! { splats_i8, i8, i8x16 }
+     splats! { splats_i16, i16, i16x8 }
+     splats! { splats_i32, i32, i32x4 }
+     splats! { splats_f32, f32, f32x4 }
+ 
+     test_impl! { vec_splats_u8 (v: u8) -> vector_unsigned_char [splats_u8, vspltb] }
+     test_impl! { vec_splats_u16 (v: u16) -> vector_unsigned_short [splats_u16, vsplth] }
+     test_impl! { vec_splats_u32 (v: u32) -> vector_unsigned_int [splats_u32, vspltw / xxspltw] }
+     test_impl! { vec_splats_i8 (v: i8) -> vector_signed_char [splats_i8, vspltb] }
+     test_impl! { vec_splats_i16 (v: i16) -> vector_signed_short [splats_i16, vsplth] }
+     test_impl! { vec_splats_i32 (v: i32) -> vector_signed_int [splats_i32, vspltw / xxspltw] }
+     test_impl! { vec_splats_f32 (v: f32) -> vector_float [splats_f32, vspltw / xxspltw] }
+ 
+     pub trait VectorSplats {
+         type Result;
+         unsafe fn vec_splats(self) -> Self::Result;
+     }
+ 
+     macro_rules! impl_vec_splats {
+         ($(($fn:ident ($ty:ty) -> $r:ty)),*) => {
+             $(
+                 impl_vec_trait!{ [VectorSplats vec_splats] $fn ($ty) -> $r }
+             )*
+         }
+     }
+ 
+     impl_vec_splats! {
+         (vec_splats_u8 (u8) -> vector_unsigned_char),
+         (vec_splats_i8 (i8) -> vector_signed_char),
+         (vec_splats_u16 (u16) -> vector_unsigned_short),
+         (vec_splats_i16 (i16) -> vector_signed_short),
+         (vec_splats_u32 (u32) -> vector_unsigned_int),
+         (vec_splats_i32 (i32) -> vector_signed_int),
+         (vec_splats_f32 (f32) -> vector_float)
+     }
+ 
+     test_impl! { vec_vsububm (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [simd_sub, vsububm] }
+     test_impl! { vec_vsubuhm (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [simd_sub, vsubuhm] }
+     test_impl! { vec_vsubuwm (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [simd_sub, vsubuwm] }
+ 
+     pub trait VectorSub<Other> {
+         type Result;
+         unsafe fn vec_sub(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorSub vec_sub] ~(simd_sub, simd_sub, simd_sub, simd_sub, simd_sub, simd_sub) }
+     impl_vec_trait! { [VectorSub vec_sub] simd_sub(vector_float, vector_float) -> vector_float }
+ 
+     test_impl! { vec_vminsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vminsb, vminsb] }
+     test_impl! { vec_vminsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vminsh, vminsh] }
+     test_impl! { vec_vminsw (a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [vminsw, vminsw] }
+ 
+     test_impl! { vec_vminub (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [vminub, vminub] }
+     test_impl! { vec_vminuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vminuh, vminuh] }
+     test_impl! { vec_vminuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vminuw, vminuw] }
+ 
+     pub trait VectorMin<Other> {
+         type Result;
+         unsafe fn vec_min(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorMin vec_min] ~(vminub, vminsb, vminuh, vminsh, vminuw, vminsw) }
+ 
+     test_impl! { vec_vmaxsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vmaxsb, vmaxsb] }
+     test_impl! { vec_vmaxsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vmaxsh, vmaxsh] }
+     test_impl! { vec_vmaxsw (a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [vmaxsw, vmaxsw] }
+ 
+     test_impl! { vec_vmaxub (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [vmaxub, vmaxub] }
+     test_impl! { vec_vmaxuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vmaxuh, vmaxuh] }
+     test_impl! { vec_vmaxuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vmaxuw, vmaxuw] }
+ 
+     pub trait VectorMax<Other> {
+         type Result;
+         unsafe fn vec_max(self, b: Other) -> Self::Result;
+     }
+ 
+     impl_vec_trait! { [VectorMax vec_max] ~(vmaxub, vmaxsb, vmaxuh, vmaxsh, vmaxuw, vmaxsw) }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmuleub))]
+     unsafe fn vec_vmuleub(
+         a: vector_unsigned_char,
+         b: vector_unsigned_char,
+     ) -> vector_unsigned_short {
+         vmuleub(a, b)
+     }
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmulesb))]
+     unsafe fn vec_vmulesb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short {
+         vmulesb(a, b)
+     }
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmuleuh))]
+     unsafe fn vec_vmuleuh(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+     ) -> vector_unsigned_int {
+         vmuleuh(a, b)
+     }
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmulesh))]
+     unsafe fn vec_vmulesh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int {
+         vmulesh(a, b)
+     }
+ 
+     pub trait VectorMule<Result> {
+         unsafe fn vec_mule(self, b: Self) -> Result;
+     }
+ 
+     impl VectorMule<vector_unsigned_short> for vector_unsigned_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mule(self, b: Self) -> vector_unsigned_short {
+             vmuleub(self, b)
+         }
+     }
+     impl VectorMule<vector_signed_short> for vector_signed_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mule(self, b: Self) -> vector_signed_short {
+             vmulesb(self, b)
+         }
+     }
+     impl VectorMule<vector_unsigned_int> for vector_unsigned_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mule(self, b: Self) -> vector_unsigned_int {
+             vmuleuh(self, b)
+         }
+     }
+     impl VectorMule<vector_signed_int> for vector_signed_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mule(self, b: Self) -> vector_signed_int {
+             vmulesh(self, b)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmuloub))]
+     unsafe fn vec_vmuloub(
+         a: vector_unsigned_char,
+         b: vector_unsigned_char,
+     ) -> vector_unsigned_short {
+         vmuloub(a, b)
+     }
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmulosb))]
+     unsafe fn vec_vmulosb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short {
+         vmulosb(a, b)
+     }
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmulouh))]
+     unsafe fn vec_vmulouh(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+     ) -> vector_unsigned_int {
+         vmulouh(a, b)
+     }
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmulosh))]
+     unsafe fn vec_vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int {
+         vmulosh(a, b)
+     }
+ 
+     pub trait VectorMulo<Result> {
+         unsafe fn vec_mulo(self, b: Self) -> Result;
+     }
+ 
+     impl VectorMulo<vector_unsigned_short> for vector_unsigned_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mulo(self, b: Self) -> vector_unsigned_short {
+             vmuloub(self, b)
+         }
+     }
+     impl VectorMulo<vector_signed_short> for vector_signed_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mulo(self, b: Self) -> vector_signed_short {
+             vmulosb(self, b)
+         }
+     }
+     impl VectorMulo<vector_unsigned_int> for vector_unsigned_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mulo(self, b: Self) -> vector_unsigned_int {
+             vmulouh(self, b)
+         }
+     }
+     impl VectorMulo<vector_signed_int> for vector_signed_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_mulo(self, b: Self) -> vector_signed_int {
+             vmulosh(self, b)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vsum4ubs))]
+     unsafe fn vec_vsum4ubs(a: vector_unsigned_char, b: vector_unsigned_int) -> vector_unsigned_int {
+         vsum4ubs(a, b)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vsum4sbs))]
+     unsafe fn vec_vsum4sbs(a: vector_signed_char, b: vector_signed_int) -> vector_signed_int {
+         vsum4sbs(a, b)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vsum4shs))]
+     unsafe fn vec_vsum4shs(a: vector_signed_short, b: vector_signed_int) -> vector_signed_int {
+         vsum4shs(a, b)
+     }
+ 
+     pub trait VectorSum4s<Other> {
+         unsafe fn vec_sum4s(self, b: Other) -> Other;
+     }
+ 
+     impl VectorSum4s<vector_unsigned_int> for vector_unsigned_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_sum4s(self, b: vector_unsigned_int) -> vector_unsigned_int {
+             vsum4ubs(self, b)
+         }
+     }
+ 
+     impl VectorSum4s<vector_signed_int> for vector_signed_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_sum4s(self, b: vector_signed_int) -> vector_signed_int {
+             vsum4sbs(self, b)
+         }
+     }
+ 
+     impl VectorSum4s<vector_signed_int> for vector_signed_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_sum4s(self, b: vector_signed_int) -> vector_signed_int {
+             vsum4shs(self, b)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vsum2sws))]
+     unsafe fn vec_vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
+         vsum2sws(a, b)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vnmsubfp))]
+     unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
+         vnmsubfp(a, b, c)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmaddfp))]
+     unsafe fn vec_vmaddfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
+         vmaddfp(a, b, c)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmsumubm))]
+     unsafe fn vec_vmsumubm(
+         a: vector_unsigned_char,
+         b: vector_unsigned_char,
+         c: vector_unsigned_int,
+     ) -> vector_unsigned_int {
+         vmsumubm(a, b, c)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmsummbm))]
+     unsafe fn vec_vmsummbm(
+         a: vector_signed_char,
+         b: vector_unsigned_char,
+         c: vector_signed_int,
+     ) -> vector_signed_int {
+         vmsummbm(a, b, c)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmsumuhm))]
+     unsafe fn vec_vmsumuhm(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+         c: vector_unsigned_int,
+     ) -> vector_unsigned_int {
+         vmsumuhm(a, b, c)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmsumshm))]
+     unsafe fn vec_vmsumshm(
+         a: vector_signed_short,
+         b: vector_signed_short,
+         c: vector_signed_int,
+     ) -> vector_signed_int {
+         vmsumshm(a, b, c)
+     }
+ 
+     pub trait VectorMsum<B, Other> {
+         unsafe fn vec_msum(self, b: B, c: Other) -> Other;
+     }
+ 
+     impl VectorMsum<vector_unsigned_char, vector_unsigned_int> for vector_unsigned_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_msum(
+             self,
+             b: vector_unsigned_char,
+             c: vector_unsigned_int,
+         ) -> vector_unsigned_int {
+             vmsumubm(self, b, c)
+         }
+     }
+ 
+     impl VectorMsum<vector_unsigned_char, vector_signed_int> for vector_signed_char {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_msum(
+             self,
+             b: vector_unsigned_char,
+             c: vector_signed_int,
+         ) -> vector_signed_int {
+             vmsummbm(self, b, c)
+         }
+     }
+ 
+     impl VectorMsum<vector_unsigned_short, vector_unsigned_int> for vector_unsigned_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_msum(
+             self,
+             b: vector_unsigned_short,
+             c: vector_unsigned_int,
+         ) -> vector_unsigned_int {
+             vmsumuhm(self, b, c)
+         }
+     }
+ 
+     impl VectorMsum<vector_signed_short, vector_signed_int> for vector_signed_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_msum(
+             self,
+             b: vector_signed_short,
+             c: vector_signed_int,
+         ) -> vector_signed_int {
+             vmsumshm(self, b, c)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmsumuhs))]
+     unsafe fn vec_vmsumuhs(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+         c: vector_unsigned_int,
+     ) -> vector_unsigned_int {
+         vmsumuhs(a, b, c)
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmsumshs))]
+     unsafe fn vec_vmsumshs(
+         a: vector_signed_short,
+         b: vector_signed_short,
+         c: vector_signed_int,
+     ) -> vector_signed_int {
+         vmsumshs(a, b, c)
+     }
+ 
+     pub trait VectorMsums<Other> {
+         unsafe fn vec_msums(self, b: Self, c: Other) -> Other;
+     }
+ 
+     impl VectorMsums<vector_unsigned_int> for vector_unsigned_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_msums(self, b: Self, c: vector_unsigned_int) -> vector_unsigned_int {
+             vmsumuhs(self, b, c)
+         }
+     }
+ 
+     impl VectorMsums<vector_signed_int> for vector_signed_short {
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_msums(self, b: Self, c: vector_signed_int) -> vector_signed_int {
+             vmsumshs(self, b, c)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vperm))]
+     unsafe fn vec_vperm(
+         a: vector_signed_int,
+         b: vector_signed_int,
+         c: vector_unsigned_char,
+     ) -> vector_signed_int {
+         vperm(a, b, c)
+     }
+ 
+     pub trait VectorPerm {
+         unsafe fn vec_vperm(self, b: Self, c: vector_unsigned_char) -> Self;
+     }
+ 
+     macro_rules! vector_perm {
+         {$impl: ident} => {
+             impl VectorPerm for $impl {
+             #[inline]
+             #[target_feature(enable = "altivec")]
+             unsafe fn vec_vperm(self, b: Self, c: vector_unsigned_char) -> Self {
+                     transmute(vec_vperm(transmute(self), transmute(b), c))
+                 }
+             }
+         }
+     }
+ 
+     vector_perm! { vector_signed_char }
+     vector_perm! { vector_unsigned_char }
+     vector_perm! { vector_bool_char }
+ 
+     vector_perm! { vector_signed_short }
+     vector_perm! { vector_unsigned_short }
+     vector_perm! { vector_bool_short }
+ 
+     vector_perm! { vector_signed_int }
+     vector_perm! { vector_unsigned_int }
+     vector_perm! { vector_bool_int }
+ 
+     vector_perm! { vector_float }
+ 
+     pub trait VectorAdd<Other> {
+         type Result;
+         unsafe fn vec_add(self, other: Other) -> Self::Result;
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vaddubm))]
+     pub unsafe fn vec_add_bc_sc(a: vector_bool_char, b: vector_signed_char) -> vector_signed_char {
+         simd_add(transmute(a), b)
+     }
+     impl VectorAdd<vector_signed_char> for vector_bool_char {
+         type Result = vector_signed_char;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_signed_char) -> Self::Result {
+             vec_add_bc_sc(self, other)
+         }
+     }
+     impl VectorAdd<vector_bool_char> for vector_signed_char {
+         type Result = vector_signed_char;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_bool_char) -> Self::Result {
+             other.vec_add(self)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vaddubm))]
+     pub unsafe fn vec_add_sc_sc(
+         a: vector_signed_char,
+         b: vector_signed_char,
+     ) -> vector_signed_char {
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_signed_char> for vector_signed_char {
+         type Result = vector_signed_char;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_signed_char) -> Self::Result {
+             vec_add_sc_sc(self, other)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vaddubm))]
+     pub unsafe fn vec_add_bc_uc(
+         a: vector_bool_char,
+         b: vector_unsigned_char,
+     ) -> vector_unsigned_char {
+         simd_add(transmute(a), b)
+     }
+     impl VectorAdd<vector_unsigned_char> for vector_bool_char {
+         type Result = vector_unsigned_char;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_unsigned_char) -> Self::Result {
+             vec_add_bc_uc(self, other)
+         }
+     }
+     impl VectorAdd<vector_bool_char> for vector_unsigned_char {
+         type Result = vector_unsigned_char;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_bool_char) -> Self::Result {
+             other.vec_add(self)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vaddubm))]
+     pub unsafe fn vec_add_uc_uc(
+         a: vector_unsigned_char,
+         b: vector_unsigned_char,
+     ) -> vector_unsigned_char {
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_unsigned_char> for vector_unsigned_char {
+         type Result = vector_unsigned_char;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_unsigned_char) -> Self::Result {
+             vec_add_uc_uc(self, other)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduhm))]
+     pub unsafe fn vec_add_bs_ss(
+         a: vector_bool_short,
+         b: vector_signed_short,
+     ) -> vector_signed_short {
+         let a: i16x8 = transmute(a);
+         let a: vector_signed_short = simd_cast(a);
+         simd_add(a, b)
+     }
+ 
+     impl VectorAdd<vector_signed_short> for vector_bool_short {
+         type Result = vector_signed_short;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_signed_short) -> Self::Result {
+             vec_add_bs_ss(self, other)
+         }
+     }
+     impl VectorAdd<vector_bool_short> for vector_signed_short {
+         type Result = vector_signed_short;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_bool_short) -> Self::Result {
+             other.vec_add(self)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduhm))]
+     pub unsafe fn vec_add_ss_ss(
+         a: vector_signed_short,
+         b: vector_signed_short,
+     ) -> vector_signed_short {
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_signed_short> for vector_signed_short {
+         type Result = vector_signed_short;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_signed_short) -> Self::Result {
+             vec_add_ss_ss(self, other)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduhm))]
+     pub unsafe fn vec_add_bs_us(
+         a: vector_bool_short,
+         b: vector_unsigned_short,
+     ) -> vector_unsigned_short {
+         let a: i16x8 = transmute(a);
+         let a: vector_unsigned_short = simd_cast(a);
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_unsigned_short> for vector_bool_short {
+         type Result = vector_unsigned_short;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_unsigned_short) -> Self::Result {
+             vec_add_bs_us(self, other)
+         }
+     }
+     impl VectorAdd<vector_bool_short> for vector_unsigned_short {
+         type Result = vector_unsigned_short;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_bool_short) -> Self::Result {
+             other.vec_add(self)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduhm))]
+     pub unsafe fn vec_add_us_us(
+         a: vector_unsigned_short,
+         b: vector_unsigned_short,
+     ) -> vector_unsigned_short {
+         simd_add(a, b)
+     }
+ 
+     impl VectorAdd<vector_unsigned_short> for vector_unsigned_short {
+         type Result = vector_unsigned_short;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_unsigned_short) -> Self::Result {
+             vec_add_us_us(self, other)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduwm))]
+     pub unsafe fn vec_add_bi_si(a: vector_bool_int, b: vector_signed_int) -> vector_signed_int {
+         let a: i32x4 = transmute(a);
+         let a: vector_signed_int = simd_cast(a);
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_signed_int> for vector_bool_int {
+         type Result = vector_signed_int;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_signed_int) -> Self::Result {
+             vec_add_bi_si(self, other)
+         }
+     }
+     impl VectorAdd<vector_bool_int> for vector_signed_int {
+         type Result = vector_signed_int;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_bool_int) -> Self::Result {
+             other.vec_add(self)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduwm))]
+     pub unsafe fn vec_add_si_si(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_signed_int> for vector_signed_int {
+         type Result = vector_signed_int;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_signed_int) -> Self::Result {
+             vec_add_si_si(self, other)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduwm))]
+     pub unsafe fn vec_add_bi_ui(a: vector_bool_int, b: vector_unsigned_int) -> vector_unsigned_int {
+         let a: i32x4 = transmute(a);
+         let a: vector_unsigned_int = simd_cast(a);
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_unsigned_int> for vector_bool_int {
+         type Result = vector_unsigned_int;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_unsigned_int) -> Self::Result {
+             vec_add_bi_ui(self, other)
+         }
+     }
+     impl VectorAdd<vector_bool_int> for vector_unsigned_int {
+         type Result = vector_unsigned_int;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_bool_int) -> Self::Result {
+             other.vec_add(self)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vadduwm))]
+     pub unsafe fn vec_add_ui_ui(
+         a: vector_unsigned_int,
+         b: vector_unsigned_int,
+     ) -> vector_unsigned_int {
+         simd_add(a, b)
+     }
+     impl VectorAdd<vector_unsigned_int> for vector_unsigned_int {
+         type Result = vector_unsigned_int;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_unsigned_int) -> Self::Result {
+             vec_add_ui_ui(self, other)
+         }
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(xvaddsp))]
+     pub unsafe fn vec_add_float_float(a: vector_float, b: vector_float) -> vector_float {
+         simd_add(a, b)
+     }
+ 
+     impl VectorAdd<vector_float> for vector_float {
+         type Result = vector_float;
+         #[inline]
+         #[target_feature(enable = "altivec")]
+         unsafe fn vec_add(self, other: vector_float) -> Self::Result {
+             vec_add_float_float(self, other)
+         }
+     }
+ 
+     pub trait VectorMladd<Other> {
+         type Result;
+         unsafe fn vec_mladd(self, b: Other, c: Other) -> Self::Result;
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     #[cfg_attr(test, assert_instr(vmladduhm))]
+     unsafe fn mladd(a: i16x8, b: i16x8, c: i16x8) -> i16x8 {
+         simd_add(simd_mul(a, b), c)
+     }
+ 
+     macro_rules! vector_mladd {
+         ($a: ident, $bc: ident, $d: ident) => {
+             impl VectorMladd<$bc> for $a {
+                 type Result = $d;
+                 #[inline]
+                 #[target_feature(enable = "altivec")]
+                 unsafe fn vec_mladd(self, b: $bc, c: $bc) -> Self::Result {
+                     let a: i16x8 = transmute(self);
+                     let b: i16x8 = transmute(b);
+                     let c: i16x8 = transmute(c);
+ 
+                     transmute(mladd(a, b, c))
+                 }
+             }
+         };
+     }
+ 
+     vector_mladd! { vector_unsigned_short, vector_unsigned_short, vector_unsigned_short }
+     vector_mladd! { vector_unsigned_short, vector_signed_short, vector_signed_short }
+     vector_mladd! { vector_signed_short, vector_unsigned_short, vector_signed_short }
+     vector_mladd! { vector_signed_short, vector_signed_short, vector_signed_short }
+ }
+ 
+ /// Vector ld.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_ld<T>(off: i32, p: T) -> <T as sealed::VectorLd>::Result
+ where
+     T: sealed::VectorLd,
+ {
+     p.vec_ld(off)
+ }
+ 
+ /// Vector floor.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_floor(a: vector_float) -> vector_float {
+     sealed::vec_floor(a)
+ }
+ 
+ /// Vector expte.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_expte(a: vector_float) -> vector_float {
+     sealed::vec_vexptefp(a)
+ }
+ 
+ /// Vector cmplt.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_cmplt<T, U>(a: U, b: T) -> <T as sealed::VectorCmpGt<U>>::Result
+ where
+     T: sealed::VectorCmpGt<U>,
+ {
+     vec_cmpgt(b, a)
+ }
+ 
+ /// Vector cmple.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_cmple(a: vector_float, b: vector_float) -> vector_bool_int {
+     vec_cmpge(b, a)
+ }
+ 
+ /// Vector cmpgt.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_cmpgt<T, U>(a: T, b: U) -> <T as sealed::VectorCmpGt<U>>::Result
+ where
+     T: sealed::VectorCmpGt<U>,
+ {
+     a.vec_cmpgt(b)
+ }
+ 
+ /// Vector cmpge.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_cmpge(a: vector_float, b: vector_float) -> vector_bool_int {
+     sealed::vec_vcmpgefp(a, b)
+ }
+ 
+ /// Vector cmpeq.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_cmpeq<T, U>(a: T, b: U) -> <T as sealed::VectorCmpEq<U>>::Result
+ where
+     T: sealed::VectorCmpEq<U>,
+ {
+     a.vec_cmpeq(b)
+ }
+ 
+ /// Vector cmpb.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_cmpb(a: vector_float, b: vector_float) -> vector_signed_int {
+     sealed::vec_vcmpbfp(a, b)
+ }
+ 
+ /// Vector cmpb.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_ceil(a: vector_float) -> vector_float {
+     sealed::vec_vceil(a)
+ }
+ 
+ /// Vector avg.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_avg<T, U>(a: T, b: U) -> <T as sealed::VectorAvg<U>>::Result
+ where
+     T: sealed::VectorAvg<U>,
+ {
+     a.vec_avg(b)
+ }
+ 
+ /// Vector andc.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_andc<T, U>(a: T, b: U) -> <T as sealed::VectorAndc<U>>::Result
+ where
+     T: sealed::VectorAndc<U>,
+ {
+     a.vec_andc(b)
+ }
+ 
+ /// Vector and.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_and<T, U>(a: T, b: U) -> <T as sealed::VectorAnd<U>>::Result
+ where
+     T: sealed::VectorAnd<U>,
+ {
+     a.vec_and(b)
+ }
+ 
+ /// Vector adds.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_adds<T, U>(a: T, b: U) -> <T as sealed::VectorAdds<U>>::Result
+ where
+     T: sealed::VectorAdds<U>,
+ {
+     a.vec_adds(b)
+ }
+ 
+ /// Vector addc.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_addc(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int {
+     sealed::vec_vaddcuw(a, b)
+ }
+ 
+ /// Vector abs.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_abs<T>(a: T) -> T
+ where
+     T: sealed::VectorAbs,
+ {
+     a.vec_abs()
+ }
+ 
+ /// Vector abss.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_abss<T>(a: T) -> T
+ where
+     T: sealed::VectorAbss,
+ {
+     a.vec_abss()
+ }
+ 
+ /// Vector splats.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_splats<T>(a: T) -> <T as sealed::VectorSplats>::Result
+ where
+     T: sealed::VectorSplats,
+ {
+     a.vec_splats()
+ }
+ 
+ /// Vector sub.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_sub<T, U>(a: T, b: U) -> <T as sealed::VectorSub<U>>::Result
+ where
+     T: sealed::VectorSub<U>,
+ {
+     a.vec_sub(b)
+ }
+ 
+ /// Vector subs.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_subs<T, U>(a: T, b: U) -> <T as sealed::VectorSubs<U>>::Result
+ where
+     T: sealed::VectorSubs<U>,
+ {
+     a.vec_subs(b)
+ }
+ 
+ /// Vector min.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_min<T, U>(a: T, b: U) -> <T as sealed::VectorMin<U>>::Result
+ where
+     T: sealed::VectorMin<U>,
+ {
+     a.vec_min(b)
+ }
+ 
+ /// Vector max.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_max<T, U>(a: T, b: U) -> <T as sealed::VectorMax<U>>::Result
+ where
+     T: sealed::VectorMax<U>,
+ {
+     a.vec_max(b)
+ }
+ 
+ /// Vector add.
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_add<T, U>(a: T, b: U) -> <T as sealed::VectorAdd<U>>::Result
+ where
+     T: sealed::VectorAdd<U>,
+ {
+     a.vec_add(b)
+ }
+ 
+ /// Endian-biased intrinsics
+ #[cfg(target_endian = "little")]
+ mod endian {
+     use super::*;
+     /// Vector permute.
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
+     where
+         T: sealed::VectorPerm,
+     {
+         // vperm has big-endian bias
+         //
+         // Xor the mask and flip the arguments
+         let d = transmute(u8x16::new(
+             255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+         ));
+         let c = simd_xor(c, d);
+ 
+         b.vec_vperm(a, c)
+     }
+ 
+     /// Vector Sum Across Partial (1/2) Saturated
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
+         // vsum2sws has big-endian bias
+         //
+         // swap the even b elements with the odd ones
+         let flip = transmute(u8x16::new(
+             4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11,
+         ));
+         let b = vec_perm(b, b, flip);
+         let c = vsum2sws(a, b);
+ 
+         vec_perm(c, c, flip)
+     }
+ 
+     // Even and Odd are swapped in little-endian
+     /// Vector Multiply Even
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
+     where
+         T: sealed::VectorMulo<U>,
+     {
+         a.vec_mulo(b)
+     }
+     /// Vector Multiply Odd
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
+     where
+         T: sealed::VectorMule<U>,
+     {
+         a.vec_mule(b)
+     }
+ }
+ 
+ /// Vector Multiply Add Saturated
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ #[cfg_attr(test, assert_instr(vmhaddshs))]
+ pub unsafe fn vec_madds(
+     a: vector_signed_short,
+     b: vector_signed_short,
+     c: vector_signed_short,
+ ) -> vector_signed_short {
+     vmhaddshs(a, b, c)
+ }
+ 
+ /// Vector Multiply Low and Add Unsigned Half Word
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_mladd<T, U>(a: T, b: U, c: U) -> <T as sealed::VectorMladd<U>>::Result
+ where
+     T: sealed::VectorMladd<U>,
+ {
+     a.vec_mladd(b, c)
+ }
+ 
+ /// Vector Multiply Round and Add Saturated
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ #[cfg_attr(test, assert_instr(vmhraddshs))]
+ pub unsafe fn vec_mradds(
+     a: vector_signed_short,
+     b: vector_signed_short,
+     c: vector_signed_short,
+ ) -> vector_signed_short {
+     vmhraddshs(a, b, c)
+ }
+ 
+ /// Vector Multiply Sum
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_msum<T, B, U>(a: T, b: B, c: U) -> U
+ where
+     T: sealed::VectorMsum<B, U>,
+ {
+     a.vec_msum(b, c)
+ }
+ 
+ /// Vector Multiply Sum Saturated
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_msums<T, U>(a: T, b: T, c: U) -> U
+ where
+     T: sealed::VectorMsums<U>,
+ {
+     a.vec_msums(b, c)
+ }
+ 
+ /// Vector Multiply Add
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
+     vmaddfp(a, b, c)
+ }
+ 
+ /// Vector Negative Multiply Subtract
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
+     vnmsubfp(a, b, c)
+ }
+ 
+ /// Vector Sum Across Partial (1/4) Saturated
+ #[inline]
+ #[target_feature(enable = "altivec")]
+ pub unsafe fn vec_sum4s<T, U>(a: T, b: U) -> U
+ where
+     T: sealed::VectorSum4s<U>,
+ {
+     a.vec_sum4s(b)
+ }
+ 
+ #[cfg(target_endian = "big")]
+ mod endian {
+     use super::*;
+     /// Vector permute.
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
+     where
+         T: sealed::VectorPerm,
+     {
+         a.vec_vperm(b, c)
+     }
+ 
+     /// Vector Sum Across Partial (1/2) Saturated
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
+         vsum2sws(a, b)
+     }
+ 
+     /// Vector Multiply Even
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
+     where
+         T: sealed::VectorMule<U>,
+     {
+         a.vec_mule(b)
+     }
+     /// Vector Multiply Odd
+     #[inline]
+     #[target_feature(enable = "altivec")]
+     pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
+     where
+         T: sealed::VectorMulo<U>,
+     {
+         a.vec_mulo(b)
+     }
+ }
+ 
+ pub use self::endian::*;
+ 
+ #[cfg(test)]
+ mod tests {
+     #[cfg(target_arch = "powerpc")]
+     use crate::core_arch::arch::powerpc::*;
+ 
+     #[cfg(target_arch = "powerpc64")]
+     use crate::core_arch::arch::powerpc64::*;
+ 
+     use std::mem::transmute;
+ 
+     use crate::core_arch::simd::*;
+     use stdarch_test::simd_test;
+ 
+     macro_rules! test_vec_2 {
+         { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             test_vec_2! { $name, $fn, $ty -> $ty, [$($a),+], [$($b),+], [$($d),+] }
+         };
+         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
+                 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+ 
+                 let d = $ty_out::new($($d),+);
+                 let r : $ty_out = transmute($fn(a, b));
+                 assert_eq!(d, r);
+             }
+          }
+     }
+ 
+     macro_rules! test_vec_1 {
+         { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: vector_float = transmute(f32x4::new($($a),+));
+ 
+                 let d: vector_float = transmute(f32x4::new($($d),+));
+                 let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(std::f32::EPSILON)));
+                 let e = m32x4::new(true, true, true, true);
+                 assert_eq!(e, r);
+             }
+         };
+         { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => {
+             test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] }
+         };
+         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
+ 
+                 let d = $ty_out::new($($d),+);
+                 let r : $ty_out = transmute($fn(a));
+                 assert_eq!(d, r);
+             }
+         }
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_ld() {
+         let pat = [
+             u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
+             u8x16::new(
+                 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+             ),
+         ];
+ 
+         for off in 0..16 {
+             let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
+             assert_eq!(
+                 v,
+                 u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
+             );
+         }
+         for off in 16..32 {
+             let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
+             assert_eq!(
+                 v,
+                 u8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
+             );
+         }
+     }
+ 
+     test_vec_1! { test_vec_floor, vec_floor, f32x4,
+         [1.1, 1.9, -0.5, -0.9],
+         [1.0, 1.0, -1.0, -1.0]
+     }
+ 
+     test_vec_1! { test_vec_expte, vec_expte, f32x4,
+         [0.0, 2.0, 2.0, -1.0],
+         ~[1.0, 4.0, 4.0, 0.5]
+     }
+ 
+     test_vec_2! { test_vec_cmpgt_i8, vec_cmpgt, i8x16 -> m8x16,
+         [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpgt_u8, vec_cmpgt, u8x16 -> m8x16,
+         [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpgt_i16, vec_cmpgt, i16x8 -> m16x8,
+         [1, -1, 0, 0, 0, 0, 0, 0],
+         [0, 0, -1, 1, 0, 0, 0, 0],
+         [true, false, true, false, false, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpgt_u16, vec_cmpgt, u16x8 -> m16x8,
+         [1, 255, 0, 0, 0, 0, 0, 0],
+         [0, 0, 255, 1, 0, 0, 0, 0],
+         [true, true, false, false, false, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpgt_i32, vec_cmpgt, i32x4 -> m32x4,
+         [1, -1, 0, 0],
+         [0, -1, 0, 1],
+         [true, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpgt_u32, vec_cmpgt, u32x4 -> m32x4,
+         [1, 255, 0, 0],
+         [0, 255,  0, 1],
+         [true, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpge, vec_cmpge, f32x4 -> m32x4,
+         [0.1, -0.1, 0.0, 0.99],
+         [0.1, 0.0, 0.1, 1.0],
+         [true, false, false, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpeq_i8, vec_cmpeq, i8x16 -> m8x16,
+         [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true]
+     }
+ 
+     test_vec_2! { test_vec_cmpeq_u8, vec_cmpeq, u8x16 -> m8x16,
+         [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+         [false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true]
+     }
+ 
+     test_vec_2! { test_vec_cmpeq_i16, vec_cmpeq, i16x8 -> m16x8,
+         [1, -1, 0, 0, 0, 0, 0, 0],
+         [0, 0, -1, 1, 0, 0, 0, 0],
+         [false, false, false, false, true, true, true, true]
+     }
+ 
+     test_vec_2! { test_vec_cmpeq_u16, vec_cmpeq, u16x8 -> m16x8,
+         [1, 255, 0, 0, 0, 0, 0, 0],
+         [0, 0, 255, 1, 0, 0, 0, 0],
+         [false, false, false, false, true, true, true, true]
+     }
+ 
+     test_vec_2! { test_vec_cmpeq_i32, vec_cmpeq, i32x4 -> m32x4,
+         [1, -1, 0, 0],
+         [0, -1, 0, 1],
+         [false, true, true, false]
+     }
+ 
+     test_vec_2! { test_vec_cmpeq_u32, vec_cmpeq, u32x4 -> m32x4,
+         [1, 255, 0, 0],
+         [0, 255,  0, 1],
+         [false, true, true, false]
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_cmpb() {
+         let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
+         let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9));
+         let d = i32x4::new(
+             -0b10000000000000000000000000000000,
+             0,
+             -0b10000000000000000000000000000000,
+             0,
+         );
+ 
+         assert_eq!(d, transmute(vec_cmpb(a, b)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_ceil() {
+         let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
+         let d = f32x4::new(1.0, 1.0, 1.0, 1.0);
+ 
+         assert_eq!(d, transmute(vec_ceil(a)));
+     }
+ 
+     test_vec_2! { test_vec_andc, vec_andc, i32x4,
+     [0b11001100, 0b11001100, 0b11001100, 0b11001100],
+     [0b00110011, 0b11110011, 0b00001100, 0b10000000],
+     [0b11001100, 0b00001100, 0b11000000, 0b01001100] }
+ 
+     test_vec_2! { test_vec_and, vec_and, i32x4,
+     [0b11001100, 0b11001100, 0b11001100, 0b11001100],
+     [0b00110011, 0b11110011, 0b00001100, 0b00000000],
+     [0b00000000, 0b11000000, 0b00001100, 0b00000000] }
+ 
+     macro_rules! test_vec_avg {
+         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             test_vec_2! {$name, vec_avg, $ty, [$($a),+], [$($b),+], [$($d),+] }
+         }
+     }
+ 
+     test_vec_avg! { test_vec_avg_i32x4, i32x4,
+     [i32::MIN, i32::MAX, 1, -1],
+     [-1, 1, 1, -1],
+     [-1073741824, 1073741824, 1, -1] }
+ 
+     test_vec_avg! { test_vec_avg_u32x4, u32x4,
+     [u32::MAX, 0, 1, 2],
+     [2, 1, 0, 0],
+     [2147483649, 1, 1, 1] }
+ 
+     test_vec_avg! { test_vec_avg_i16x8, i16x8,
+     [i16::MIN, i16::MAX, 1, -1, 0, 0, 0, 0],
+     [-1, 1, 1, -1, 0, 0, 0, 0],
+     [-16384, 16384, 1, -1, 0, 0, 0, 0] }
+ 
+     test_vec_avg! { test_vec_avg_u16x8, u16x8,
+     [u16::MAX, 0, 1, 2, 0, 0, 0, 0],
+     [2, 1, 0, 0, 0, 0, 0, 0],
+     [32769, 1, 1, 1, 0, 0, 0, 0] }
+ 
+     test_vec_avg! { test_vec_avg_i8x16, i8x16,
+     [i8::MIN, i8::MAX, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [-1, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [-64, 64, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
+ 
+     test_vec_avg! { test_vec_avg_u8x16, u8x16,
+     [u8::MAX, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [129, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
+ 
+     macro_rules! test_vec_adds {
+         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             test_vec_2! {$name, vec_adds, $ty, [$($a),+], [$($b),+], [$($d),+] }
+         }
+     }
+ 
+     test_vec_adds! { test_vec_adds_i32x4, i32x4,
+     [i32::MIN, i32::MAX, 1, -1],
+     [-1, 1, 1, -1],
+     [i32::MIN, i32::MAX, 2, -2] }
+ 
+     test_vec_adds! { test_vec_adds_u32x4, u32x4,
+     [u32::MAX, 0, 1, 2],
+     [2, 1, 0, 0],
+     [u32::MAX, 1, 1, 2] }
+ 
+     test_vec_adds! { test_vec_adds_i16x8, i16x8,
+     [i16::MIN, i16::MAX, 1, -1, 0, 0, 0, 0],
+     [-1, 1, 1, -1, 0, 0, 0, 0],
+     [i16::MIN, i16::MAX, 2, -2, 0, 0, 0, 0] }
+ 
+     test_vec_adds! { test_vec_adds_u16x8, u16x8,
+     [u16::MAX, 0, 1, 2, 0, 0, 0, 0],
+     [2, 1, 0, 0, 0, 0, 0, 0],
+     [u16::MAX, 1, 1, 2, 0, 0, 0, 0] }
+ 
+     test_vec_adds! { test_vec_adds_i8x16, i8x16,
+     [i8::MIN, i8::MAX, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [-1, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [i8::MIN, i8::MAX, 2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
+ 
+     test_vec_adds! { test_vec_adds_u8x16, u8x16,
+     [u8::MAX, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+     [u8::MAX, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
+ 
+     test_vec_2! { test_vec_addc, vec_addc, u32x4, [u32::MAX, 0, 0, 0], [1, 1, 1, 1], [1, 0, 0, 0] }
+ 
+     macro_rules! test_vec_abs {
+         { $name: ident, $ty: ident, $a: expr, $d: expr } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a = vec_splats($a);
+                 let a: s_t_l!($ty) = vec_abs(a);
+                 let d = $ty::splat($d);
+                 assert_eq!(d, transmute(a));
+             }
+         }
+     }
+ 
+     test_vec_abs! { test_vec_abs_i8, i8x16, -42i8, 42i8 }
+     test_vec_abs! { test_vec_abs_i16, i16x8, -42i16, 42i16 }
+     test_vec_abs! { test_vec_abs_i32, i32x4, -42i32, 42i32 }
+     test_vec_abs! { test_vec_abs_f32, f32x4, -42f32, 42f32 }
+ 
+     macro_rules! test_vec_abss {
+         { $name: ident, $ty: ident, $a: expr, $d: expr } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a = vec_splats($a);
+                 let a: s_t_l!($ty) = vec_abss(a);
+                 let d = $ty::splat($d);
+                 assert_eq!(d, transmute(a));
+             }
+         }
+     }
+ 
+     test_vec_abss! { test_vec_abss_i8, i8x16, -127i8, 127i8 }
+     test_vec_abss! { test_vec_abss_i16, i16x8, -42i16, 42i16 }
+     test_vec_abss! { test_vec_abss_i32, i32x4, -42i32, 42i32 }
+ 
+     macro_rules! test_vec_splats {
+         { $name: ident, $ty: ident, $a: expr } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: s_t_l!($ty) = vec_splats($a);
+                 let d = $ty::splat($a);
+                 assert_eq!(d, transmute(a));
+             }
+         }
+     }
+ 
+     test_vec_splats! { test_vec_splats_u8, u8x16, 42u8 }
+     test_vec_splats! { test_vec_splats_u16, u16x8, 42u16 }
+     test_vec_splats! { test_vec_splats_u32, u32x4, 42u32 }
+     test_vec_splats! { test_vec_splats_i8, i8x16, 42i8 }
+     test_vec_splats! { test_vec_splats_i16, i16x8, 42i16 }
+     test_vec_splats! { test_vec_splats_i32, i32x4, 42i32 }
+     test_vec_splats! { test_vec_splats_f32, f32x4, 42f32 }
+ 
+     macro_rules! test_vec_sub {
+         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             test_vec_2! {$name, vec_sub, $ty, [$($a),+], [$($b),+], [$($d),+] }
+         }
+     }
+ 
+     test_vec_sub! { test_vec_sub_f32x4, f32x4,
+     [-1.0, 0.0, 1.0, 2.0],
+     [2.0, 1.0, -1.0, -2.0],
+     [-3.0, -1.0, 2.0, 4.0] }
+ 
+     test_vec_sub! { test_vec_sub_i32x4, i32x4,
+     [-1, 0, 1, 2],
+     [2, 1, -1, -2],
+     [-3, -1, 2, 4] }
+ 
+     test_vec_sub! { test_vec_sub_u32x4, u32x4,
+     [0, 0, 1, 2],
+     [2, 1, 0, 0],
+     [4294967294, 4294967295, 1, 2] }
+ 
+     test_vec_sub! { test_vec_sub_i16x8, i16x8,
+     [-1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2],
+     [-3, -1, 2, 4, -3, -1, 2, 4] }
+ 
+     test_vec_sub! { test_vec_sub_u16x8, u16x8,
+     [0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0],
+     [65534, 65535, 1, 2, 65534, 65535, 1, 2] }
+ 
+     test_vec_sub! { test_vec_sub_i8x16, i8x16,
+     [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
+     [-3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4] }
+ 
+     test_vec_sub! { test_vec_sub_u8x16, u8x16,
+     [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
+     [254, 255, 1, 2, 254, 255, 1, 2, 254, 255, 1, 2, 254, 255, 1, 2] }
+ 
+     macro_rules! test_vec_subs {
+         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             test_vec_2! {$name, vec_subs, $ty, [$($a),+], [$($b),+], [$($d),+] }
+         }
+     }
+ 
+     test_vec_subs! { test_vec_subs_i32x4, i32x4,
+     [-1, 0, 1, 2],
+     [2, 1, -1, -2],
+     [-3, -1, 2, 4] }
+ 
+     test_vec_subs! { test_vec_subs_u32x4, u32x4,
+     [0, 0, 1, 2],
+     [2, 1, 0, 0],
+     [0, 0, 1, 2] }
+ 
+     test_vec_subs! { test_vec_subs_i16x8, i16x8,
+     [-1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2],
+     [-3, -1, 2, 4, -3, -1, 2, 4] }
+ 
+     test_vec_subs! { test_vec_subs_u16x8, u16x8,
+     [0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0],
+     [0, 0, 1, 2, 0, 0, 1, 2] }
+ 
+     test_vec_subs! { test_vec_subs_i8x16, i8x16,
+     [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
+     [-3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4] }
+ 
+     test_vec_subs! { test_vec_subs_u8x16, u8x16,
+     [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
+     [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2] }
+ 
+     macro_rules! test_vec_min {
+         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
+                 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+ 
+                 let d = $ty::new($($d),+);
+                 let r : $ty = transmute(vec_min(a, b));
+                 assert_eq!(d, r);
+             }
+          }
+     }
+ 
+     test_vec_min! { test_vec_min_i32x4, i32x4,
+     [-1, 0, 1, 2],
+     [2, 1, -1, -2],
+     [-1, 0, -1, -2] }
+ 
+     test_vec_min! { test_vec_min_u32x4, u32x4,
+     [0, 0, 1, 2],
+     [2, 1, 0, 0],
+     [0, 0, 0, 0] }
+ 
+     test_vec_min! { test_vec_min_i16x8, i16x8,
+     [-1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2],
+     [-1, 0, -1, -2, -1, 0, -1, -2] }
+ 
+     test_vec_min! { test_vec_min_u16x8, u16x8,
+     [0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0],
+     [0, 0, 0, 0, 0, 0, 0, 0] }
+ 
+     test_vec_min! { test_vec_min_i8x16, i8x16,
+     [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
+     [-1, 0, -1, -2, -1, 0, -1, -2, -1, 0, -1, -2, -1, 0, -1, -2] }
+ 
+     test_vec_min! { test_vec_min_u8x16, u8x16,
+     [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
+     [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
+ 
+     macro_rules! test_vec_max {
+         { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: s_t_l!($ty) = transmute($ty::new($($a),+));
+                 let b: s_t_l!($ty) = transmute($ty::new($($b),+));
+ 
+                 let d = $ty::new($($d),+);
+                 let r : $ty = transmute(vec_max(a, b));
+                 assert_eq!(d, r);
+             }
+          }
+     }
+ 
+     test_vec_max! { test_vec_max_i32x4, i32x4,
+     [-1, 0, 1, 2],
+     [2, 1, -1, -2],
+     [2, 1, 1, 2] }
+ 
+     test_vec_max! { test_vec_max_u32x4, u32x4,
+     [0, 0, 1, 2],
+     [2, 1, 0, 0],
+     [2, 1, 1, 2] }
+ 
+     test_vec_max! { test_vec_max_i16x8, i16x8,
+     [-1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2],
+     [2, 1, 1, 2, 2, 1, 1, 2] }
+ 
+     test_vec_max! { test_vec_max_u16x8, u16x8,
+     [0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0],
+     [2, 1, 1, 2, 2, 1, 1, 2] }
+ 
+     test_vec_max! { test_vec_max_i8x16, i8x16,
+     [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
+     [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
+     [2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }
+ 
+     test_vec_max! { test_vec_max_u8x16, u8x16,
+     [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
+     [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
+     [2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }
+ 
+     macro_rules! test_vec_perm {
+         {$name:ident,
+          $shorttype:ident, $longtype:ident,
+          [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: $longtype = transmute($shorttype::new($($a),+));
+                 let b: $longtype = transmute($shorttype::new($($b),+));
+                 let c: vector_unsigned_char = transmute(u8x16::new($($c),+));
+                 let d = $shorttype::new($($d),+);
+ 
+                 let r: $shorttype = transmute(vec_perm(a, b, c));
+                 assert_eq!(d, r);
+             }
+         }
+     }
+ 
+     test_vec_perm! {test_vec_perm_u8x16,
+     u8x16, vector_unsigned_char,
+     [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+     [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
+     [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+      0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+     [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
+     test_vec_perm! {test_vec_perm_i8x16,
+     i8x16, vector_signed_char,
+     [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+     [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
+     [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+      0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+     [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
+ 
+     test_vec_perm! {test_vec_perm_m8x16,
+     m8x16, vector_bool_char,
+     [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false],
+     [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true],
+     [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+      0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+     [false, false, true, true, false, false, true, true, false, false, true, true, false, false, true, true]}
+     test_vec_perm! {test_vec_perm_u16x8,
+     u16x8, vector_unsigned_short,
+     [0, 1, 2, 3, 4, 5, 6, 7],
+     [10, 11, 12, 13, 14, 15, 16, 17],
+     [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+      0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+     [0, 10, 1, 11, 2, 12, 3, 13]}
+     test_vec_perm! {test_vec_perm_i16x8,
+     i16x8, vector_signed_short,
+     [0, 1, 2, 3, 4, 5, 6, 7],
+     [10, 11, 12, 13, 14, 15, 16, 17],
+     [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+      0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+     [0, 10, 1, 11, 2, 12, 3, 13]}
+     test_vec_perm! {test_vec_perm_m16x8,
+     m16x8, vector_bool_short,
+     [false, false, false, false, false, false, false, false],
+     [true, true, true, true, true, true, true, true],
+     [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
+      0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
+     [false, true, false, true, false, true, false, true]}
+ 
+     test_vec_perm! {test_vec_perm_u32x4,
+     u32x4, vector_unsigned_int,
+     [0, 1, 2, 3],
+     [10, 11, 12, 13],
+     [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+      0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+     [0, 10, 1, 11]}
+     test_vec_perm! {test_vec_perm_i32x4,
+     i32x4, vector_signed_int,
+     [0, 1, 2, 3],
+     [10, 11, 12, 13],
+     [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+      0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+     [0, 10, 1, 11]}
+     test_vec_perm! {test_vec_perm_m32x4,
+     m32x4, vector_bool_int,
+     [false, false, false, false],
+     [true, true, true, true],
+     [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+      0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+     [false, true, false, true]}
+     test_vec_perm! {test_vec_perm_f32x4,
+     f32x4, vector_float,
+     [0.0, 1.0, 2.0, 3.0],
+     [1.0, 1.1, 1.2, 1.3],
+     [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
+      0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
+     [0.0, 1.0, 1.0, 1.1]}
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_madds() {
+         let a: vector_signed_short = transmute(i16x8::new(
+             0 * 256,
+             1 * 256,
+             2 * 256,
+             3 * 256,
+             4 * 256,
+             5 * 256,
+             6 * 256,
+             7 * 256,
+         ));
+         let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+         let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+ 
+         let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21);
+ 
+         assert_eq!(d, transmute(vec_madds(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_madd_float() {
+         let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+         let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+         let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+         let d = f32x4::new(
+             0.1 * 0.1 + 0.1,
+             0.2 * 0.2 + 0.2,
+             0.3 * 0.3 + 0.3,
+             0.4 * 0.4 + 0.4,
+         );
+ 
+         assert_eq!(d, transmute(vec_madd(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_nmsub_float() {
+         let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+         let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+         let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
+         let d = f32x4::new(
+             -(0.1 * 0.1 - 0.1),
+             -(0.2 * 0.2 - 0.2),
+             -(0.3 * 0.3 - 0.3),
+             -(0.4 * 0.4 - 0.4),
+         );
+         assert_eq!(d, transmute(vec_nmsub(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mradds() {
+         let a: vector_signed_short = transmute(i16x8::new(
+             0 * 256,
+             1 * 256,
+             2 * 256,
+             3 * 256,
+             4 * 256,
+             5 * 256,
+             6 * 256,
+             7 * 256,
+         ));
+         let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+         let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
+ 
+         let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX);
+ 
+         assert_eq!(d, transmute(vec_mradds(a, b, c)));
+     }
+ 
+     macro_rules! test_vec_mladd {
+         {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident,
+             [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
+             #[simd_test(enable = "altivec")]
+             unsafe fn $name() {
+                 let a: $la = transmute($sa::new($($a),+));
+                 let b: $lbc = transmute($sbc::new($($b),+));
+                 let c = transmute($sbc::new($($c),+));
+                 let d = $sd::new($($d),+);
+ 
+                 assert_eq!(d, transmute(vec_mladd(a, b, c)));
+             }
+         }
+     }
+ 
+     test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8,
+         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
+     }
+     test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8,
+         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
+     }
+     test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8,
+         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
+     }
+     test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8,
+         [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_msum_unsigned_char() {
+         let a: vector_unsigned_char =
+             transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let b: vector_unsigned_char = transmute(u8x16::new(
+             255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+         ));
+         let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+         let d = u32x4::new(
+             (0 + 1 + 2 + 3) * 255 + 0,
+             (4 + 5 + 6 + 7) * 255 + 1,
+             (0 + 1 + 2 + 3) * 255 + 2,
+             (4 + 5 + 6 + 7) * 255 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_msum(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_msum_signed_char() {
+         let a: vector_signed_char = transmute(i8x16::new(
+             0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7,
+         ));
+         let b: vector_unsigned_char =
+             transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
+         let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3));
+         let d = i32x4::new(
+             (0 - 1 + 2 - 3) + 0,
+             (0) + 1,
+             (0 + 1 + 2 + 3) + 2,
+             (4 - 5 - 6 - 7) + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_msum(a, b, c)));
+     }
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_msum_unsigned_short() {
+         let a: vector_unsigned_short = transmute(u16x8::new(
+             0 * 256,
+             1 * 256,
+             2 * 256,
+             3 * 256,
+             4 * 256,
+             5 * 256,
+             6 * 256,
+             7 * 256,
+         ));
+         let b: vector_unsigned_short =
+             transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+         let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+         let d = u32x4::new(
+             (0 + 1) * 256 * 256 + 0,
+             (2 + 3) * 256 * 256 + 1,
+             (4 + 5) * 256 * 256 + 2,
+             (6 + 7) * 256 * 256 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_msum(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_msum_signed_short() {
+         let a: vector_signed_short = transmute(i16x8::new(
+             0 * 256,
+             -1 * 256,
+             2 * 256,
+             -3 * 256,
+             4 * 256,
+             -5 * 256,
+             6 * 256,
+             -7 * 256,
+         ));
+         let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+         let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+         let d = i32x4::new(
+             (0 - 1) * 256 * 256 + 0,
+             (2 - 3) * 256 * 256 + 1,
+             (4 - 5) * 256 * 256 + 2,
+             (6 - 7) * 256 * 256 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_msum(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_msums_unsigned() {
+         let a: vector_unsigned_short = transmute(u16x8::new(
+             0 * 256,
+             1 * 256,
+             2 * 256,
+             3 * 256,
+             4 * 256,
+             5 * 256,
+             6 * 256,
+             7 * 256,
+         ));
+         let b: vector_unsigned_short =
+             transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+         let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+         let d = u32x4::new(
+             (0 + 1) * 256 * 256 + 0,
+             (2 + 3) * 256 * 256 + 1,
+             (4 + 5) * 256 * 256 + 2,
+             (6 + 7) * 256 * 256 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_msums(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_msums_signed() {
+         let a: vector_signed_short = transmute(i16x8::new(
+             0 * 256,
+             -1 * 256,
+             2 * 256,
+             -3 * 256,
+             4 * 256,
+             -5 * 256,
+             6 * 256,
+             -7 * 256,
+         ));
+         let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
+         let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+         let d = i32x4::new(
+             (0 - 1) * 256 * 256 + 0,
+             (2 - 3) * 256 * 256 + 1,
+             (4 - 5) * 256 * 256 + 2,
+             (6 - 7) * 256 * 256 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_msums(a, b, c)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_sum2s() {
+         let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+         let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+         let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3);
+ 
+         assert_eq!(d, transmute(vec_sum2s(a, b)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_sum4s_unsigned_char() {
+         let a: vector_unsigned_char =
+             transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
+         let d = u32x4::new(
+             0 + 1 + 2 + 3 + 0,
+             4 + 5 + 6 + 7 + 1,
+             0 + 1 + 2 + 3 + 2,
+             4 + 5 + 6 + 7 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_sum4s(a, b)));
+     }
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_sum4s_signed_char() {
+         let a: vector_signed_char =
+             transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+         let d = i32x4::new(
+             0 + 1 + 2 + 3 + 0,
+             4 + 5 + 6 + 7 + 1,
+             0 + 1 + 2 + 3 + 2,
+             4 + 5 + 6 + 7 + 3,
+         );
+ 
+         assert_eq!(d, transmute(vec_sum4s(a, b)));
+     }
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_sum4s_signed_short() {
+         let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+         let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
+         let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3);
+ 
+         assert_eq!(d, transmute(vec_sum4s(a, b)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mule_unsigned_char() {
+         let a: vector_unsigned_char =
+             transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
+ 
+         assert_eq!(d, transmute(vec_mule(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mule_signed_char() {
+         let a: vector_signed_char = transmute(i8x16::new(
+             0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
+         ));
+         let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
+ 
+         assert_eq!(d, transmute(vec_mule(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mule_unsigned_short() {
+         let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+         let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
+ 
+         assert_eq!(d, transmute(vec_mule(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mule_signed_short() {
+         let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
+         let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
+ 
+         assert_eq!(d, transmute(vec_mule(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mulo_unsigned_char() {
+         let a: vector_unsigned_char =
+             transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
+         let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
+ 
+         assert_eq!(d, transmute(vec_mulo(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mulo_signed_char() {
+         let a: vector_signed_char = transmute(i8x16::new(
+             0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
+         ));
+         let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
+ 
+         assert_eq!(d, transmute(vec_mulo(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mulo_unsigned_short() {
+         let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
+         let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
+ 
+         assert_eq!(d, transmute(vec_mulo(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn test_vec_mulo_signed_short() {
+         let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
+         let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
+ 
+         assert_eq!(d, transmute(vec_mulo(a, a)));
+     }
+ 
+     #[simd_test(enable = "altivec")]
+     unsafe fn vec_add_i32x4_i32x4() {
+         let x = i32x4::new(1, 2, 3, 4);
+         let y = i32x4::new(4, 3, 2, 1);
+         let x: vector_signed_int = transmute(x);
+         let y: vector_signed_int = transmute(y);
+         let z = vec_add(x, y);
+         assert_eq!(i32x4::splat(5), transmute(z));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,19 ----
+ //! PowerPC intrinsics
+ 
+ #[cfg(target_feature = "altivec")]
+ mod altivec;
+ #[cfg(target_feature = "altivec")]
+ pub use self::altivec::*;
+ 
+ mod vsx;
+ pub use self::vsx::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Generates the trap instruction `TRAP`
+ #[cfg_attr(test, assert_instr(trap))]
+ #[inline]
+ pub unsafe fn trap() -> ! {
+     crate::intrinsics::abort()
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/vsx.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/vsx.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/vsx.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc/vsx.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,117 ----
+ //! PowerPC Vector Scalar eXtensions (VSX) intrinsics.
+ //!
+ //! The references are: [POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA
+ //! NVlink)] and [POWER ISA v3.0B (for POWER9)].
+ //!
+ //! [POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA NVlink)]: https://ibm.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u
+ //! [POWER ISA v3.0B (for POWER9)]: https://ibm.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv
+ 
+ #![allow(non_camel_case_types)]
+ 
+ use crate::core_arch::simd_llvm::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ use crate::mem;
+ 
+ types! {
+     // pub struct vector_Float16 = f16x8;
+     /// PowerPC-specific 128-bit wide vector of two packed `i64`
+     pub struct vector_signed_long(i64, i64);
+     /// PowerPC-specific 128-bit wide vector of two packed `u64`
+     pub struct vector_unsigned_long(u64, u64);
+     /// PowerPC-specific 128-bit wide vector mask of two elements
+     pub struct vector_bool_long(i64, i64);
+     /// PowerPC-specific 128-bit wide vector of two packed `f64`
+     pub struct vector_double(f64, f64);
+     // pub struct vector_signed_long_long = vector_signed_long;
+     // pub struct vector_unsigned_long_long = vector_unsigned_long;
+     // pub struct vector_bool_long_long = vector_bool_long;
+     // pub struct vector_signed___int128 = i128x1;
+     // pub struct vector_unsigned___int128 = i128x1;
+ }
+ 
+ mod sealed {
+     use super::*;
+     use crate::core_arch::simd::*;
+ 
+     pub trait VectorPermDI {
+         unsafe fn vec_xxpermdi(self, b: Self, dm: u8) -> Self;
+     }
+ 
+     // xxpermdi has an big-endian bias and extended mnemonics
+     #[inline]
+     #[target_feature(enable = "vsx")]
+     #[cfg_attr(all(test, target_endian = "little"), assert_instr(xxmrgld, dm = 0x0))]
+     #[cfg_attr(all(test, target_endian = "big"), assert_instr(xxspltd, dm = 0x0))]
+     unsafe fn xxpermdi(a: i64x2, b: i64x2, dm: u8) -> i64x2 {
+         match dm & 0b11 {
+             0 => simd_shuffle2(a, b, [0b00, 0b10]),
+             1 => simd_shuffle2(a, b, [0b01, 0b10]),
+             2 => simd_shuffle2(a, b, [0b00, 0b11]),
+             _ => simd_shuffle2(a, b, [0b01, 0b11]),
+         }
+     }
+ 
+     macro_rules! vec_xxpermdi {
+         {$impl: ident} => {
+             impl VectorPermDI for $impl {
+                 #[inline]
+                 #[target_feature(enable = "vsx")]
+                 unsafe fn vec_xxpermdi(self, b: Self, dm: u8) -> Self {
+                     mem::transmute(xxpermdi(mem::transmute(self), mem::transmute(b), dm))
+                 }
+             }
+         }
+     }
+ 
+     vec_xxpermdi! { vector_unsigned_long }
+     vec_xxpermdi! { vector_signed_long }
+     vec_xxpermdi! { vector_bool_long }
+     vec_xxpermdi! { vector_double }
+ }
+ 
+ /// Vector permute.
+ #[inline]
+ #[target_feature(enable = "vsx")]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn vec_xxpermdi<T>(a: T, b: T, dm: u8) -> T
+ where
+     T: sealed::VectorPermDI,
+ {
+     a.vec_xxpermdi(b, dm)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     #[cfg(target_arch = "powerpc")]
+     use crate::core_arch::arch::powerpc::*;
+ 
+     #[cfg(target_arch = "powerpc64")]
+     use crate::core_arch::arch::powerpc64::*;
+ 
+     use super::mem;
+     use crate::core_arch::simd::*;
+     use stdarch_test::simd_test;
+ 
+     macro_rules! test_vec_xxpermdi {
+         {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
+             #[simd_test(enable = "vsx")]
+             unsafe fn $name() {
+                 let a: $longtype = mem::transmute($shorttype::new($($a),+, $($b),+));
+                 let b = mem::transmute($shorttype::new($($c),+, $($d),+));
+ 
+                 assert_eq!($shorttype::new($($a),+, $($c),+), mem::transmute(vec_xxpermdi(a, b, 0)));
+                 assert_eq!($shorttype::new($($b),+, $($c),+), mem::transmute(vec_xxpermdi(a, b, 1)));
+                 assert_eq!($shorttype::new($($a),+, $($d),+), mem::transmute(vec_xxpermdi(a, b, 2)));
+                 assert_eq!($shorttype::new($($b),+, $($d),+), mem::transmute(vec_xxpermdi(a, b, 3)));
+             }
+         }
+     }
+ 
+     test_vec_xxpermdi! {test_vec_xxpermdi_u64x2, u64x2, vector_unsigned_long, [0], [1], [2], [3]}
+     test_vec_xxpermdi! {test_vec_xxpermdi_i64x2, i64x2, vector_signed_long, [0], [-1], [2], [-3]}
+     test_vec_xxpermdi! {test_vec_xxpermdi_m64x2, m64x2, vector_bool_long, [false], [true], [false], [true]}
+     test_vec_xxpermdi! {test_vec_xxpermdi_f64x2, f64x2, vector_double, [0.0], [1.0], [2.0], [3.0]}
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc64/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc64/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc64/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/powerpc64/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,8 ----
+ //! PowerPC 64
+ //!
+ //! The reference is the [64-Bit ELF V2 ABI Specification - Power
+ //! Architecture].
+ //!
+ //! [64-Bit ELF V2 ABI Specification - Power Architecture]: http://openpowerfoundation.org/wp-content/uploads/resources/leabi/leabi-20170510.pdf
+ 
+ pub use crate::core_arch::powerpc::*;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,711 ----
+ //! Internal `#[repr(simd)]` types
+ 
+ #![allow(non_camel_case_types)]
+ 
+ macro_rules! simd_ty {
+     ($id:ident [$ety:ident]: $($elem_ty:ident),* | $($elem_name:ident),*) => {
+         #[repr(simd)]
+         #[derive(Copy, Clone, Debug, PartialEq)]
+         pub(crate) struct $id($(pub $elem_ty),*);
+ 
+         #[allow(clippy::use_self)]
+         impl $id {
+             #[inline]
+             pub(crate) const fn new($($elem_name: $elem_ty),*) -> Self {
+                 $id($($elem_name),*)
+             }
+             // FIXME: Workaround rust@60637
+             #[inline(always)]
+             pub(crate) const fn splat(value: $ety) -> Self {
+                 $id($({
+                     #[allow(non_camel_case_types, dead_code)]
+                     struct $elem_name;
+                     value
+                 }),*)
+             }
+ 
+             // FIXME: Workaround rust@60637
+             #[inline(always)]
+             pub(crate) fn extract(self, index: usize) -> $ety {
+                 unsafe {
+                     crate::core_arch::simd_llvm::simd_extract(self, index as u32)
+                 }
+             }
+         }
+     }
+ }
+ 
+ macro_rules! simd_m_ty {
+     ($id:ident [$ety:ident]: $($elem_ty:ident),* | $($elem_name:ident),*) => {
+         #[repr(simd)]
+         #[derive(Copy, Clone, Debug, PartialEq)]
+         pub(crate) struct $id($(pub $elem_ty),*);
+ 
+         #[allow(clippy::use_self)]
+         impl $id {
+             #[inline]
+             const fn bool_to_internal(x: bool) -> $ety {
+                 [0 as $ety, !(0 as $ety)][x as usize]
+             }
+ 
+             #[inline]
+             pub(crate) const fn new($($elem_name: bool),*) -> Self {
+                 $id($(Self::bool_to_internal($elem_name)),*)
+             }
+ 
+             // FIXME: Workaround rust@60637
+             #[inline(always)]
+             pub(crate) const fn splat(value: bool) -> Self {
+                 $id($({
+                     #[allow(non_camel_case_types, dead_code)]
+                     struct $elem_name;
+                     Self::bool_to_internal(value)
+                 }),*)
+             }
+ 
+             // FIXME: Workaround rust@60637
+             #[inline(always)]
+             pub(crate) fn extract(self, index: usize) -> bool {
+                 let r: $ety = unsafe {
+                     crate::core_arch::simd_llvm::simd_extract(self, index as u32)
+                 };
+                 r != 0
+             }
+         }
+     }
+ }
+ 
+ // 16-bit wide types:
+ 
+ simd_ty!(u8x2[u8]: u8, u8 | x0, x1);
+ simd_ty!(i8x2[i8]: i8, i8 | x0, x1);
+ 
+ // 32-bit wide types:
+ 
+ simd_ty!(u8x4[u8]: u8, u8, u8, u8 | x0, x1, x2, x3);
+ simd_ty!(u16x2[u16]: u16, u16 | x0, x1);
+ 
+ simd_ty!(i8x4[i8]: i8, i8, i8, i8 | x0, x1, x2, x3);
+ simd_ty!(i16x2[i16]: i16, i16 | x0, x1);
+ 
+ // 64-bit wide types:
+ 
+ simd_ty!(
+     u8x8[u8]: u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_ty!(u16x4[u16]: u16, u16, u16, u16 | x0, x1, x2, x3);
+ simd_ty!(u32x2[u32]: u32, u32 | x0, x1);
+ simd_ty!(u64x1[u64]: u64 | x1);
+ 
+ simd_ty!(
+     i8x8[i8]: i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_ty!(i16x4[i16]: i16, i16, i16, i16 | x0, x1, x2, x3);
+ simd_ty!(i32x2[i32]: i32, i32 | x0, x1);
+ simd_ty!(i64x1[i64]: i64 | x1);
+ 
+ simd_ty!(f32x2[f32]: f32, f32 | x0, x1);
+ 
+ // 128-bit wide types:
+ 
+ simd_ty!(
+     u8x16[u8]: u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ simd_ty!(
+     u16x8[u16]: u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_ty!(u32x4[u32]: u32, u32, u32, u32 | x0, x1, x2, x3);
+ simd_ty!(u64x2[u64]: u64, u64 | x0, x1);
+ 
+ simd_ty!(
+     i8x16[i8]: i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ simd_ty!(
+     i16x8[i16]: i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_ty!(i32x4[i32]: i32, i32, i32, i32 | x0, x1, x2, x3);
+ simd_ty!(i64x2[i64]: i64, i64 | x0, x1);
+ 
+ simd_ty!(f32x4[f32]: f32, f32, f32, f32 | x0, x1, x2, x3);
+ simd_ty!(f64x2[f64]: f64, f64 | x0, x1);
+ 
+ simd_m_ty!(
+     m8x16[i8]: i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ simd_m_ty!(
+     m16x8[i16]: i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_m_ty!(m32x4[i32]: i32, i32, i32, i32 | x0, x1, x2, x3);
+ simd_m_ty!(m64x2[i64]: i64, i64 | x0, x1);
+ 
+ // 256-bit wide types:
+ 
+ simd_ty!(
+     u8x32[u8]: u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8,
+     u8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15,
+     x16,
+     x17,
+     x18,
+     x19,
+     x20,
+     x21,
+     x22,
+     x23,
+     x24,
+     x25,
+     x26,
+     x27,
+     x28,
+     x29,
+     x30,
+     x31
+ );
+ simd_ty!(
+     u16x16[u16]: u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16,
+     u16 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ simd_ty!(
+     u32x8[u32]: u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_ty!(u64x4[u64]: u64, u64, u64, u64 | x0, x1, x2, x3);
+ 
+ simd_ty!(
+     i8x32[i8]: i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8,
+     i8 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15,
+     x16,
+     x17,
+     x18,
+     x19,
+     x20,
+     x21,
+     x22,
+     x23,
+     x24,
+     x25,
+     x26,
+     x27,
+     x28,
+     x29,
+     x30,
+     x31
+ );
+ simd_ty!(
+     i16x16[i16]: i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16,
+     i16 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ simd_ty!(
+     i32x8[i32]: i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ simd_ty!(i64x4[i64]: i64, i64, i64, i64 | x0, x1, x2, x3);
+ 
+ simd_ty!(
+     f32x8[f32]: f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ 
+ // 512-bit wide types:
+ 
+ simd_ty!(
+     i32x16[i32]: i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32,
+     i32 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ 
+ simd_ty!(
+     u32x16[u32]: u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32,
+     u32 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ 
+ simd_ty!(
+     f32x16[f32]: f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32,
+     f32 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7,
+     x8,
+     x9,
+     x10,
+     x11,
+     x12,
+     x13,
+     x14,
+     x15
+ );
+ 
+ simd_ty!(
+     i64x8[i64]: i64,
+     i64,
+     i64,
+     i64,
+     i64,
+     i64,
+     i64,
+     i64 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ 
+ simd_ty!(
+     u64x8[u64]: u64,
+     u64,
+     u64,
+     u64,
+     u64,
+     u64,
+     u64,
+     u64 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
+ 
+ simd_ty!(
+     f64x8[f64]: f64,
+     f64,
+     f64,
+     f64,
+     f64,
+     f64,
+     f64,
+     f64 | x0,
+     x1,
+     x2,
+     x3,
+     x4,
+     x5,
+     x6,
+     x7
+ );
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd_llvm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd_llvm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd_llvm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/simd_llvm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,86 ----
+ //! LLVM's SIMD platform intrinsics
+ 
+ extern "platform-intrinsic" {
+     //pub fn simd_select_bitmask
+     pub fn simd_eq<T, U>(x: T, y: T) -> U;
+     pub fn simd_ne<T, U>(x: T, y: T) -> U;
+     pub fn simd_lt<T, U>(x: T, y: T) -> U;
+     pub fn simd_le<T, U>(x: T, y: T) -> U;
+     pub fn simd_gt<T, U>(x: T, y: T) -> U;
+     pub fn simd_ge<T, U>(x: T, y: T) -> U;
+ 
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle2<T, U>(x: T, y: T, idx: [u32; 2]) -> U;
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle4<T, U>(x: T, y: T, idx: [u32; 4]) -> U;
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle8<T, U>(x: T, y: T, idx: [u32; 8]) -> U;
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle16<T, U>(x: T, y: T, idx: [u32; 16]) -> U;
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U;
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle64<T, U>(x: T, y: T, idx: [u32; 64]) -> U;
+     #[rustc_args_required_const(2)]
+     pub fn simd_shuffle128<T, U>(x: T, y: T, idx: [u32; 128]) -> U;
+ 
+     #[rustc_const_unstable(feature = "const_simd_insert", issue = "none")]
+     pub fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
+     #[rustc_const_unstable(feature = "const_simd_extract", issue = "none")]
+     pub fn simd_extract<T, U>(x: T, idx: u32) -> U;
+     //pub fn simd_select
+     pub fn simd_bitmask<T, U>(x: T) -> U;
+ 
+     pub fn simd_cast<T, U>(x: T) -> U;
+ 
+     pub fn simd_add<T>(x: T, y: T) -> T;
+     pub fn simd_sub<T>(x: T, y: T) -> T;
+     pub fn simd_mul<T>(x: T, y: T) -> T;
+     pub fn simd_div<T>(x: T, y: T) -> T;
+     pub fn simd_shl<T>(x: T, y: T) -> T;
+     pub fn simd_shr<T>(x: T, y: T) -> T;
+     pub fn simd_and<T>(x: T, y: T) -> T;
+     pub fn simd_or<T>(x: T, y: T) -> T;
+     pub fn simd_xor<T>(x: T, y: T) -> T;
+ 
+     pub fn simd_saturating_add<T>(x: T, y: T) -> T;
+     pub fn simd_saturating_sub<T>(x: T, y: T) -> T;
+ 
+     pub fn simd_gather<T, U, V>(values: T, pointers: U, mask: V) -> T;
+     pub fn simd_scatter<T, U, V>(values: T, pointers: U, mask: V);
+ 
+     pub fn simd_reduce_add_unordered<T, U>(x: T) -> U;
+     pub fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
+     pub fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
+     pub fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
+     pub fn simd_reduce_min<T, U>(x: T) -> U;
+     pub fn simd_reduce_max<T, U>(x: T) -> U;
+     pub fn simd_reduce_min_nanless<T, U>(x: T) -> U;
+     pub fn simd_reduce_max_nanless<T, U>(x: T) -> U;
+     pub fn simd_reduce_and<T, U>(x: T) -> U;
+     pub fn simd_reduce_or<T, U>(x: T) -> U;
+     pub fn simd_reduce_xor<T, U>(x: T) -> U;
+     pub fn simd_reduce_all<T>(x: T) -> bool;
+     pub fn simd_reduce_any<T>(x: T) -> bool;
+ 
+     pub fn simd_select<M, T>(m: M, a: T, b: T) -> T;
+     pub fn simd_select_bitmask<M, T>(m: M, a: T, b: T) -> T;
+ 
+     pub fn simd_fmin<T>(a: T, b: T) -> T;
+     pub fn simd_fmax<T>(a: T, b: T) -> T;
+ 
+     pub fn simd_fsqrt<T>(a: T) -> T;
+     pub fn simd_fsin<T>(a: T) -> T;
+     pub fn simd_fcos<T>(a: T) -> T;
+     pub fn simd_fabs<T>(a: T) -> T;
+     pub fn simd_floor<T>(a: T) -> T;
+     pub fn simd_ceil<T>(a: T) -> T;
+     pub fn simd_fexp<T>(a: T) -> T;
+     pub fn simd_fexp2<T>(a: T) -> T;
+     pub fn simd_flog10<T>(a: T) -> T;
+     pub fn simd_flog2<T>(a: T) -> T;
+     pub fn simd_flog<T>(a: T) -> T;
+     //pub fn simd_fpowi
+     //pub fn simd_fpow
+     pub fn simd_fma<T>(a: T, b: T, c: T) -> T;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/v64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/v64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/v64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/v64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,85 ----
+ //! 64-bit wide vector types
+ 
+ use crate::prelude::v1::*;
+ 
+ use crate::core_arch::simd_llvm::*;
+ 
+ define_ty_doc! {
+     f32x2, f32, f32 |
+     /// A 64-bit vector with 2 `f32` lanes.
+ }
+ define_impl! { f32x2, f32, 2, i32x2, x0, x1 }
+ 
+ define_ty_doc! {
+     u32x2, u32, u32 |
+     /// A 64-bit vector with 2 `u32` lanes.
+ }
+ define_impl! { u32x2, u32, 2, i32x2, x0, x1 }
+ 
+ define_ty! { i32x2, i32, i32 }
+ define_impl! { i32x2, i32, 2, i32x2, x0, x1 }
+ 
+ define_ty! { u16x4, u16, u16, u16, u16 }
+ define_impl! { u16x4, u16, 4, i16x4, x0, x1, x2, x3 }
+ 
+ define_ty! { i16x4, i16, i16, i16, i16 }
+ define_impl! { i16x4, i16, 4, i16x4, x0, x1, x2, x3 }
+ 
+ define_ty! { u8x8, u8, u8, u8, u8, u8, u8, u8, u8 }
+ define_impl! { u8x8, u8, 8, i8x8, x0, x1, x2, x3, x4, x5, x6, x7 }
+ 
+ define_ty! { i8x8, i8, i8, i8, i8, i8, i8, i8, i8 }
+ define_impl! { i8x8, i8, 8, i8x8, x0, x1, x2, x3, x4, x5, x6, x7 }
+ 
+ define_from!(u32x2, i32x2, u16x4, i16x4, u8x8, i8x8);
+ define_from!(i32x2, u32x2, u16x4, i16x4, u8x8, i8x8);
+ define_from!(u16x4, u32x2, i32x2, i16x4, u8x8, i8x8);
+ define_from!(i16x4, u32x2, i32x2, u16x4, u8x8, i8x8);
+ define_from!(u8x8, u32x2, i32x2, u16x4, i16x4, i8x8);
+ define_from!(i8x8, u32x2, i32x2, u16x4, i16x4, u8x8);
+ 
+ define_common_ops!(f32x2, u32x2, i32x2, u16x4, i16x4, u8x8, i8x8);
+ define_float_ops!(f32x2);
+ define_integer_ops!(
+     (u32x2, u32),
+     (i32x2, i32),
+     (u16x4, u16),
+     (i16x4, i16),
+     (u8x8, u8),
+     (i8x8, i8)
+ );
+ define_signed_integer_ops!(i32x2, i16x4, i8x8);
+ define_casts!(
+     (f32x2, f64x2, as_f64x2),
+     (f32x2, u32x2, as_u32x2),
+     (f32x2, i32x2, as_i32x2),
+     (u32x2, f32x2, as_f32x2),
+     (u32x2, i32x2, as_i32x2),
+     (i32x2, f32x2, as_f32x2),
+     (i32x2, u32x2, as_u32x2),
+     (u16x4, i16x4, as_i16x4),
+     (i16x4, u16x4, as_u16x4),
+     (u8x8, i8x8, as_i8x8),
+     (i8x8, u8x8, as_u8x8),
+     (i8x8, i16x8, as_i16x8),
+     (u8x8, i16x8, as_i16x8),
+     (i16x4, i32x4, as_i32x4),
+     (i32x2, i64x2, as_i64x2),
+     (u8x8, u16x8, as_u16x8),
+     (u16x4, u32x4, as_u32x4),
+     (u16x4, i32x4, as_i32x4),
+     (u32x2, u64x2, as_u64x2),
+     (u32x2, i64x2, as_i64x2)
+ );
+ 
+ #[cfg(test)]
+ mod tests {
+     use super::*;
+ 
+     #[test]
+     fn operators() {
+         test_ops_si!(i8x8, i16x4, i32x2);
+         test_ops_ui!(u8x8, u16x4, u32x2);
+         test_ops_f!(f32x2);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/atomic.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/atomic.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/atomic.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/atomic.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,118 ----
+ //! Intrinsics associated with WebAssembly's upcoming threads proposal.
+ //!
+ //! These intrinsics are all unstable because they're not actually stable in
+ //! WebAssembly itself yet. The signatures may change as [the
+ //! specification][spec] is updated.
+ //!
+ //! [spec]: https://github.com/WebAssembly/threads
+ 
+ #![cfg(any(target_feature = "atomics", doc))]
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ extern "C" {
+     #[link_name = "llvm.wasm.atomic.wait.i32"]
+     fn llvm_atomic_wait_i32(ptr: *mut i32, exp: i32, timeout: i64) -> i32;
+     #[link_name = "llvm.wasm.atomic.wait.i64"]
+     fn llvm_atomic_wait_i64(ptr: *mut i64, exp: i64, timeout: i64) -> i32;
+     #[link_name = "llvm.wasm.atomic.notify"]
+     fn llvm_atomic_notify(ptr: *mut i32, cnt: i32) -> i32;
+ }
+ 
+ /// Corresponding intrinsic to wasm's [`memory.atomic.wait32` instruction][instr]
+ ///
+ /// This function, when called, will block the current thread if the memory
+ /// pointed to by `ptr` is equal to `expression` (performing this action
+ /// atomically).
+ ///
+ /// The argument `timeout_ns` is a maxinum number of nanoseconds the calling
+ /// thread will be blocked for, if it blocks. If the timeout is negative then
+ /// the calling thread will be blocked forever.
+ ///
+ /// The calling thread can only be woken up with a call to the `wake` intrinsic
+ /// once it has been blocked. Changing the memory behind `ptr` will not wake
+ /// the thread once it's blocked.
+ ///
+ /// # Return value
+ ///
+ /// * 0 - indicates that the thread blocked and then was woken up
+ /// * 1 - the loaded value from `ptr` didn't match `expression`, the thread
+ ///   didn't block
+ /// * 2 - the thread blocked, but the timeout expired.
+ ///
+ /// # Availability
+ ///
+ /// This intrinsic is only available **when the standard library itself is
+ /// compiled with the `atomics` target feature**. This version of the standard
+ /// library is not obtainable via `rustup`, but rather will require the
+ /// standard library to be compiled from source.
+ ///
+ /// [instr]: https://webassembly.github.io/threads/syntax/instructions.html#syntax-instr-atomic-memory
+ #[inline]
+ #[cfg_attr(test, assert_instr("i32.atomic.wait"))]
+ pub unsafe fn memory_atomic_wait32(ptr: *mut i32, expression: i32, timeout_ns: i64) -> i32 {
+     llvm_atomic_wait_i32(ptr, expression, timeout_ns)
+ }
+ 
+ /// Corresponding intrinsic to wasm's [`memory.atomic.wait64` instruction][instr]
+ ///
+ /// This function, when called, will block the current thread if the memory
+ /// pointed to by `ptr` is equal to `expression` (performing this action
+ /// atomically).
+ ///
+ /// The argument `timeout_ns` is a maxinum number of nanoseconds the calling
+ /// thread will be blocked for, if it blocks. If the timeout is negative then
+ /// the calling thread will be blocked forever.
+ ///
+ /// The calling thread can only be woken up with a call to the `wake` intrinsic
+ /// once it has been blocked. Changing the memory behind `ptr` will not wake
+ /// the thread once it's blocked.
+ ///
+ /// # Return value
+ ///
+ /// * 0 - indicates that the thread blocked and then was woken up
+ /// * 1 - the loaded value from `ptr` didn't match `expression`, the thread
+ ///   didn't block
+ /// * 2 - the thread blocked, but the timeout expired.
+ ///
+ /// # Availability
+ ///
+ /// This intrinsic is only available **when the standard library itself is
+ /// compiled with the `atomics` target feature**. This version of the standard
+ /// library is not obtainable via `rustup`, but rather will require the
+ /// standard library to be compiled from source.
+ ///
+ /// [instr]: https://webassembly.github.io/threads/syntax/instructions.html#syntax-instr-atomic-memory
+ #[inline]
+ #[cfg_attr(test, assert_instr("i64.atomic.wait"))]
+ pub unsafe fn memory_atomic_wait64(ptr: *mut i64, expression: i64, timeout_ns: i64) -> i32 {
+     llvm_atomic_wait_i64(ptr, expression, timeout_ns)
+ }
+ 
+ /// Corresponding intrinsic to wasm's [`memory.atomic.notify` instruction][instr]
+ ///
+ /// This function will notify a number of threads blocked on the address
+ /// indicated by `ptr`. Threads previously blocked with the `i32_atomic_wait`
+ /// and `i64_atomic_wait` functions above will be woken up.
+ ///
+ /// The `waiters` argument indicates how many waiters should be woken up (a
+ /// maximum). If the value is zero no waiters are woken up.
+ ///
+ /// # Return value
+ ///
+ /// Returns the number of waiters which were actually notified.
+ ///
+ /// # Availability
+ ///
+ /// This intrinsic is only available **when the standard library itself is
+ /// compiled with the `atomics` target feature**. This version of the standard
+ /// library is not obtainable via `rustup`, but rather will require the
+ /// standard library to be compiled from source.
+ ///
+ /// [instr]: https://webassembly.github.io/threads/syntax/instructions.html#syntax-instr-atomic-memory
+ #[inline]
+ #[cfg_attr(test, assert_instr("atomic.wake"))]
+ pub unsafe fn memory_atomic_notify(ptr: *mut i32, waiters: u32) -> u32 {
+     llvm_atomic_notify(ptr, waiters as i32) as u32
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/memory.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/memory.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/memory.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/memory.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,62 ----
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ extern "C" {
+     #[link_name = "llvm.wasm.memory.grow.i32"]
+     fn llvm_memory_grow(mem: i32, pages: i32) -> i32;
+     #[link_name = "llvm.wasm.memory.size.i32"]
+     fn llvm_memory_size(mem: i32) -> i32;
+ }
+ 
+ /// Corresponding intrinsic to wasm's [`memory.size` instruction][instr]
+ ///
+ /// This function, when called, will return the current memory size in units of
+ /// pages. The current WebAssembly page size is 65536 bytes (64 KB).
+ ///
+ /// The argument `mem` is the numerical index of which memory to return the
+ /// size of. Note that currently the WebAssembly specification only supports one
+ /// memory, so it is required that zero is passed in. The argument is present to
+ /// be forward-compatible with future WebAssembly revisions. If a nonzero
+ /// argument is passed to this function it will currently unconditionally abort.
+ ///
+ /// [instr]: http://webassembly.github.io/spec/core/exec/instructions.html#exec-memory-size
+ #[inline]
+ #[cfg_attr(test, assert_instr("memory.size", mem = 0))]
+ #[rustc_args_required_const(0)]
+ #[stable(feature = "simd_wasm32", since = "1.33.0")]
+ pub fn memory_size(mem: u32) -> usize {
+     unsafe {
+         if mem != 0 {
+             crate::intrinsics::abort();
+         }
+         llvm_memory_size(0) as usize
+     }
+ }
+ 
+ /// Corresponding intrinsic to wasm's [`memory.grow` instruction][instr]
+ ///
+ /// This function, when called, will attempt to grow the default linear memory
+ /// by the specified `delta` of pages. The current WebAssembly page size is
+ /// 65536 bytes (64 KB). If memory is successfully grown then the previous size
+ /// of memory, in pages, is returned. If memory cannot be grown then
+ /// `usize::MAX` is returned.
+ ///
+ /// The argument `mem` is the numerical index of which memory to return the
+ /// size of. Note that currently the WebAssembly specification only supports one
+ /// memory, so it is required that zero is passed in. The argument is present to
+ /// be forward-compatible with future WebAssembly revisions. If a nonzero
+ /// argument is passed to this function it will currently unconditionally abort.
+ ///
+ /// [instr]: http://webassembly.github.io/spec/core/exec/instructions.html#exec-memory-grow
+ #[inline]
+ #[cfg_attr(test, assert_instr("memory.grow", mem = 0))]
+ #[rustc_args_required_const(0)]
+ #[stable(feature = "simd_wasm32", since = "1.33.0")]
+ pub fn memory_grow(mem: u32, delta: usize) -> usize {
+     unsafe {
+         if mem != 0 {
+             crate::intrinsics::abort();
+         }
+         llvm_memory_grow(0, delta as i32) as isize as usize
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,23 ----
+ //! WASM32 intrinsics
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[cfg(any(target_feature = "atomics", doc))]
+ mod atomic;
+ #[cfg(any(target_feature = "atomics", doc))]
+ pub use self::atomic::*;
+ 
+ mod simd128;
+ pub use self::simd128::*;
+ 
+ mod memory;
+ pub use self::memory::*;
+ 
+ /// Generates the trap instruction `UNREACHABLE`
+ #[cfg_attr(test, assert_instr(unreachable))]
+ #[inline]
+ #[stable(feature = "unreachable_wasm32", since = "1.37.0")]
+ pub unsafe fn unreachable() -> ! {
+     crate::intrinsics::abort()
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/simd128.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/simd128.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/simd128.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/wasm32/simd128.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3017 ----
+ //! This module implements the [WebAssembly `SIMD128` ISA].
+ //!
+ //! [WebAssembly `SIMD128` ISA]:
+ //! https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md
+ 
+ #![unstable(feature = "wasm_simd", issue = "74372")]
+ #![allow(non_camel_case_types)]
+ #![allow(unused_imports)]
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*},
+     marker::Sized,
+     mem::transmute,
+     ptr,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ types! {
+     /// WASM-specific 128-bit wide SIMD vector type.
+     // N.B., internals here are arbitrary.
+     pub struct v128(i32, i32, i32, i32);
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait v128Ext: Sized {
+     unsafe fn as_v128(self) -> v128;
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_u8x16(self) -> u8x16 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_u16x8(self) -> u16x8 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_u32x4(self) -> u32x4 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_u64x2(self) -> u64x2 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_i8x16(self) -> i8x16 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_i16x8(self) -> i16x8 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_i32x4(self) -> i32x4 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_i64x2(self) -> i64x2 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_f32x4(self) -> f32x4 {
+         transmute(self.as_v128())
+     }
+ 
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_f64x2(self) -> f64x2 {
+         transmute(self.as_v128())
+     }
+ }
+ 
+ impl v128Ext for v128 {
+     #[inline]
+     #[target_feature(enable = "simd128")]
+     unsafe fn as_v128(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.wasm.anytrue.v16i8"]
+     fn llvm_i8x16_any_true(x: i8x16) -> i32;
+     #[link_name = "llvm.wasm.alltrue.v16i8"]
+     fn llvm_i8x16_all_true(x: i8x16) -> i32;
+     #[link_name = "llvm.sadd.sat.v16i8"]
+     fn llvm_i8x16_add_saturate_s(a: i8x16, b: i8x16) -> i8x16;
+     #[link_name = "llvm.uadd.sat.v16i8"]
+     fn llvm_i8x16_add_saturate_u(a: i8x16, b: i8x16) -> i8x16;
+     #[link_name = "llvm.wasm.sub.saturate.signed.v16i8"]
+     fn llvm_i8x16_sub_saturate_s(a: i8x16, b: i8x16) -> i8x16;
+     #[link_name = "llvm.wasm.sub.saturate.unsigned.v16i8"]
+     fn llvm_i8x16_sub_saturate_u(a: i8x16, b: i8x16) -> i8x16;
+ 
+     #[link_name = "llvm.wasm.anytrue.v8i16"]
+     fn llvm_i16x8_any_true(x: i16x8) -> i32;
+     #[link_name = "llvm.wasm.alltrue.v8i16"]
+     fn llvm_i16x8_all_true(x: i16x8) -> i32;
+     #[link_name = "llvm.sadd.sat.v8i16"]
+     fn llvm_i16x8_add_saturate_s(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.uadd.sat.v8i16"]
+     fn llvm_i16x8_add_saturate_u(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.wasm.sub.saturate.signed.v8i16"]
+     fn llvm_i16x8_sub_saturate_s(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.wasm.sub.saturate.unsigned.v8i16"]
+     fn llvm_i16x8_sub_saturate_u(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.wasm.anytrue.v4i32"]
+     fn llvm_i32x4_any_true(x: i32x4) -> i32;
+     #[link_name = "llvm.wasm.alltrue.v4i32"]
+     fn llvm_i32x4_all_true(x: i32x4) -> i32;
+ 
+     #[link_name = "llvm.fabs.v4f32"]
+     fn llvm_f32x4_abs(x: f32x4) -> f32x4;
+     #[link_name = "llvm.sqrt.v4f32"]
+     fn llvm_f32x4_sqrt(x: f32x4) -> f32x4;
+     #[link_name = "llvm.minimum.v4f32"]
+     fn llvm_f32x4_min(x: f32x4, y: f32x4) -> f32x4;
+     #[link_name = "llvm.maximum.v4f32"]
+     fn llvm_f32x4_max(x: f32x4, y: f32x4) -> f32x4;
+     #[link_name = "llvm.fabs.v2f64"]
+     fn llvm_f64x2_abs(x: f64x2) -> f64x2;
+     #[link_name = "llvm.sqrt.v2f64"]
+     fn llvm_f64x2_sqrt(x: f64x2) -> f64x2;
+     #[link_name = "llvm.minimum.v2f64"]
+     fn llvm_f64x2_min(x: f64x2, y: f64x2) -> f64x2;
+     #[link_name = "llvm.maximum.v2f64"]
+     fn llvm_f64x2_max(x: f64x2, y: f64x2) -> f64x2;
+ 
+     #[link_name = "llvm.wasm.bitselect.v16i8"]
+     fn llvm_bitselect(a: i8x16, b: i8x16, c: i8x16) -> i8x16;
+     #[link_name = "llvm.wasm.swizzle"]
+     fn llvm_swizzle(a: i8x16, b: i8x16) -> i8x16;
+ 
+     #[link_name = "llvm.wasm.bitmask.v16i8"]
+     fn llvm_bitmask_i8x16(a: i8x16) -> i32;
+     #[link_name = "llvm.wasm.narrow.signed.v16i8.v8i16"]
+     fn llvm_narrow_i8x16_s(a: i16x8, b: i16x8) -> i8x16;
+     #[link_name = "llvm.wasm.narrow.unsigned.v16i8.v8i16"]
+     fn llvm_narrow_i8x16_u(a: i16x8, b: i16x8) -> i8x16;
+     #[link_name = "llvm.wasm.avgr.unsigned.v16i8"]
+     fn llvm_avgr_u_i8x16(a: i8x16, b: i8x16) -> i8x16;
+ 
+     #[link_name = "llvm.wasm.bitmask.v8i16"]
+     fn llvm_bitmask_i16x8(a: i16x8) -> i32;
+     #[link_name = "llvm.wasm.narrow.signed.v8i16.v8i16"]
+     fn llvm_narrow_i16x8_s(a: i32x4, b: i32x4) -> i16x8;
+     #[link_name = "llvm.wasm.narrow.unsigned.v8i16.v8i16"]
+     fn llvm_narrow_i16x8_u(a: i32x4, b: i32x4) -> i16x8;
+     #[link_name = "llvm.wasm.avgr.unsigned.v8i16"]
+     fn llvm_avgr_u_i16x8(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.wasm.widen.low.signed.v8i16.v16i8"]
+     fn llvm_widen_low_i16x8_s(a: i8x16) -> i16x8;
+     #[link_name = "llvm.wasm.widen.high.signed.v8i16.v16i8"]
+     fn llvm_widen_high_i16x8_s(a: i8x16) -> i16x8;
+     #[link_name = "llvm.wasm.widen.low.unsigned.v8i16.v16i8"]
+     fn llvm_widen_low_i16x8_u(a: i8x16) -> i16x8;
+     #[link_name = "llvm.wasm.widen.high.unsigned.v8i16.v16i8"]
+     fn llvm_widen_high_i16x8_u(a: i8x16) -> i16x8;
+ 
+     #[link_name = "llvm.wasm.bitmask.v4i32"]
+     fn llvm_bitmask_i32x4(a: i32x4) -> i32;
+     #[link_name = "llvm.wasm.avgr.unsigned.v4i32"]
+     fn llvm_avgr_u_i32x4(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.wasm.widen.low.signed.v4i32.v8i16"]
+     fn llvm_widen_low_i32x4_s(a: i16x8) -> i32x4;
+     #[link_name = "llvm.wasm.widen.high.signed.v4i32.v8i16"]
+     fn llvm_widen_high_i32x4_s(a: i16x8) -> i32x4;
+     #[link_name = "llvm.wasm.widen.low.unsigned.v4i32.v8i16"]
+     fn llvm_widen_low_i32x4_u(a: i16x8) -> i32x4;
+     #[link_name = "llvm.wasm.widen.high.unsigned.v4i32.v8i16"]
+     fn llvm_widen_high_i32x4_u(a: i16x8) -> i32x4;
+ }
+ 
+ /// Loads a `v128` vector from the given heap address.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.load))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_load(m: *const v128) -> v128 {
+     *m
+ }
+ 
+ /// Load eight 8-bit integers and sign extend each one to a 16-bit lane
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(i16x8.load8x8_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_load8x8_s(m: *const i8) -> v128 {
+     transmute(simd_cast::<_, i16x8>(*(m as *const i8x8)))
+ }
+ 
+ /// Load eight 8-bit integers and zero extend each one to a 16-bit lane
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(i16x8.load8x8_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_load8x8_u(m: *const u8) -> v128 {
+     transmute(simd_cast::<_, u16x8>(*(m as *const u8x8)))
+ }
+ 
+ /// Load four 16-bit integers and sign extend each one to a 32-bit lane
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(i32x4.load16x4_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_load16x4_s(m: *const i16) -> v128 {
+     transmute(simd_cast::<_, i32x4>(*(m as *const i16x4)))
+ }
+ 
+ /// Load four 16-bit integers and zero extend each one to a 32-bit lane
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(i32x4.load16x4_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_load16x4_u(m: *const u16) -> v128 {
+     transmute(simd_cast::<_, u32x4>(*(m as *const u16x4)))
+ }
+ 
+ /// Load two 32-bit integers and sign extend each one to a 64-bit lane
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(i64x2.load32x2_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_load32x2_s(m: *const i32) -> v128 {
+     transmute(simd_cast::<_, i64x2>(*(m as *const i32x2)))
+ }
+ 
+ /// Load two 32-bit integers and zero extend each one to a 64-bit lane
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(i64x2.load32x2_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_load32x2_u(m: *const u32) -> v128 {
+     transmute(simd_cast::<_, u64x2>(*(m as *const u32x2)))
+ }
+ 
+ /// Load a single element and splat to all lanes of a v128 vector.
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(v8x16.load_splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v8x16_load_splat(m: *const u8) -> v128 {
+     let v = *m;
+     transmute(u8x16(v, v, v, v, v, v, v, v, v, v, v, v, v, v, v, v))
+ }
+ 
+ /// Load a single element and splat to all lanes of a v128 vector.
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(v16x8.load_splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v16x8_load_splat(m: *const u16) -> v128 {
+     let v = *m;
+     transmute(u16x8(v, v, v, v, v, v, v, v))
+ }
+ 
+ /// Load a single element and splat to all lanes of a v128 vector.
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(v32x4.load_splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v32x4_load_splat(m: *const u32) -> v128 {
+     let v = *m;
+     transmute(u32x4(v, v, v, v))
+ }
+ 
+ /// Load a single element and splat to all lanes of a v128 vector.
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(v64x2.load_splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v64x2_load_splat(m: *const u64) -> v128 {
+     let v = *m;
+     transmute(u64x2(v, v))
+ }
+ 
+ /// Stores a `v128` vector to the given heap address.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.store))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_store(m: *mut v128, a: v128) {
+     *m = a;
+ }
+ 
+ /// Materializes a constant SIMD value from the immediate operands.
+ ///
+ /// This function generates a `v128.const` instruction as if the generated
+ /// vector was interpreted as sixteen 8-bit integers.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ #[cfg_attr(
+     all(test, all_simd),
+     assert_instr(
+         v128.const,
+         a0 = 0,
+         a1 = 1,
+         a2 = 2,
+         a3 = 3,
+         a4 = 4,
+         a5 = 5,
+         a6 = 6,
+         a7 = 7,
+         a8 = 8,
+         a9 = 9,
+         a10 = 10,
+         a11 = 11,
+         a12 = 12,
+         a13 = 13,
+         a14 = 14,
+         a15 = 15,
+     )
+ )]
+ pub const unsafe fn i8x16_const(
+     a0: i8,
+     a1: i8,
+     a2: i8,
+     a3: i8,
+     a4: i8,
+     a5: i8,
+     a6: i8,
+     a7: i8,
+     a8: i8,
+     a9: i8,
+     a10: i8,
+     a11: i8,
+     a12: i8,
+     a13: i8,
+     a14: i8,
+     a15: i8,
+ ) -> v128 {
+     transmute(i8x16(
+         a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15,
+     ))
+ }
+ 
+ /// Materializes a constant SIMD value from the immediate operands.
+ ///
+ /// This function generates a `v128.const` instruction as if the generated
+ /// vector was interpreted as eight 16-bit integers.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ #[cfg_attr(
+     all(test, all_simd),
+     assert_instr(
+         v128.const,
+         a0 = 0,
+         a1 = 1,
+         a2 = 2,
+         a3 = 3,
+         a4 = 4,
+         a5 = 5,
+         a6 = 6,
+         a7 = 7,
+     )
+ )]
+ pub const unsafe fn i16x8_const(
+     a0: i16,
+     a1: i16,
+     a2: i16,
+     a3: i16,
+     a4: i16,
+     a5: i16,
+     a6: i16,
+     a7: i16,
+ ) -> v128 {
+     transmute(i16x8(a0, a1, a2, a3, a4, a5, a6, a7))
+ }
+ 
+ /// Materializes a constant SIMD value from the immediate operands.
+ ///
+ /// This function generates a `v128.const` instruction as if the generated
+ /// vector was interpreted as four 32-bit integers.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ #[cfg_attr(all(test, all_simd), assert_instr(v128.const, a0 = 0, a1 = 1, a2 = 2, a3 = 3))]
+ pub const unsafe fn i32x4_const(a0: i32, a1: i32, a2: i32, a3: i32) -> v128 {
+     transmute(i32x4(a0, a1, a2, a3))
+ }
+ 
+ /// Materializes a constant SIMD value from the immediate operands.
+ ///
+ /// This function generates a `v128.const` instruction as if the generated
+ /// vector was interpreted as two 64-bit integers.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ #[cfg_attr(all(test, all_simd), assert_instr(v128.const, a0 = 0, a1 = 1))]
+ pub const unsafe fn i64x2_const(a0: i64, a1: i64) -> v128 {
+     transmute(i64x2(a0, a1))
+ }
+ 
+ /// Materializes a constant SIMD value from the immediate operands.
+ ///
+ /// This function generates a `v128.const` instruction as if the generated
+ /// vector was interpreted as four 32-bit floats.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ #[cfg_attr(all(test, all_simd), assert_instr(v128.const, a0 = 0.0, a1 = 1.0, a2 = 2.0, a3 = 3.0))]
+ pub const unsafe fn f32x4_const(a0: f32, a1: f32, a2: f32, a3: f32) -> v128 {
+     transmute(f32x4(a0, a1, a2, a3))
+ }
+ 
+ /// Materializes a constant SIMD value from the immediate operands.
+ ///
+ /// This function generates a `v128.const` instruction as if the generated
+ /// vector was interpreted as two 64-bit floats.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ #[cfg_attr(all(test, all_simd), assert_instr(v128.const, a0 = 0.0, a1 = 1.0))]
+ pub const unsafe fn f64x2_const(a0: f64, a1: f64) -> v128 {
+     transmute(f64x2(a0, a1))
+ }
+ 
+ /// Returns a new vector with lanes selected from the lanes of the two input
+ /// vectors `$a` and `$b` specified in the 16 immediate operands.
+ ///
+ /// The `$a` and `$b` expressions must have type `v128`, and this macro
+ /// generates a wasm instruction that is encoded with 16 bytes providing the
+ /// indices of the elements to return. The indices `i` in range [0, 15] select
+ /// the `i`-th element of `a`. The indices in range [16, 31] select the `i -
+ /// 16`-th element of `b`.
+ ///
+ /// Note that this is a macro due to the codegen requirements of all of the
+ /// index expressions `$i*` must be constant. A compiler error will be
+ /// generated if any of the expressions are not constant.
+ ///
+ /// All indexes `$i*` must have the type `u32`.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v8x16_shuffle<
+     const I0: usize,
+     const I1: usize,
+     const I2: usize,
+     const I3: usize,
+     const I4: usize,
+     const I5: usize,
+     const I6: usize,
+     const I7: usize,
+     const I8: usize,
+     const I9: usize,
+     const I10: usize,
+     const I11: usize,
+     const I12: usize,
+     const I13: usize,
+     const I14: usize,
+     const I15: usize,
+ >(
+     a: v128,
+     b: v128,
+ ) -> v128 {
+     let shuf = simd_shuffle16::<u8x16, u8x16>(
+         a.as_u8x16(),
+         b.as_u8x16(),
+         [
+             I0 as u32, I1 as u32, I2 as u32, I3 as u32, I4 as u32, I5 as u32, I6 as u32, I7 as u32,
+             I8 as u32, I9 as u32, I10 as u32, I11 as u32, I12 as u32, I13 as u32, I14 as u32,
+             I15 as u32,
+         ],
+     );
+     transmute(shuf)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(v8x16.shuffle)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn v8x16_shuffle_test(a: v128, b: v128) -> v128 {
+     v8x16_shuffle::<0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30>(a, b)
+ }
+ 
+ /// Same as [`v8x16_shuffle`], except operates as if the inputs were eight
+ /// 16-bit integers, only taking 8 indices to shuffle.
+ ///
+ /// Indices in the range [0, 7] select from `a` while [8, 15] select from `b`.
+ /// Note that this will generate the `v8x16.shuffle` instruction, since there
+ /// is no native `v16x8.shuffle` instruction (there is no need for one since
+ /// `v8x16.shuffle` suffices).
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v16x8_shuffle<
+     const I0: usize,
+     const I1: usize,
+     const I2: usize,
+     const I3: usize,
+     const I4: usize,
+     const I5: usize,
+     const I6: usize,
+     const I7: usize,
+ >(
+     a: v128,
+     b: v128,
+ ) -> v128 {
+     let shuf = simd_shuffle8::<u16x8, u16x8>(
+         a.as_u16x8(),
+         b.as_u16x8(),
+         [
+             I0 as u32, I1 as u32, I2 as u32, I3 as u32, I4 as u32, I5 as u32, I6 as u32, I7 as u32,
+         ],
+     );
+     transmute(shuf)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(v8x16.shuffle)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn v16x8_shuffle_test(a: v128, b: v128) -> v128 {
+     v16x8_shuffle::<0, 2, 4, 6, 8, 10, 12, 14>(a, b)
+ }
+ 
+ /// Same as [`v8x16_shuffle`], except operates as if the inputs were four
+ /// 32-bit integers, only taking 4 indices to shuffle.
+ ///
+ /// Indices in the range [0, 3] select from `a` while [4, 7] select from `b`.
+ /// Note that this will generate the `v8x16.shuffle` instruction, since there
+ /// is no native `v32x4.shuffle` instruction (there is no need for one since
+ /// `v8x16.shuffle` suffices).
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v32x4_shuffle<const I0: usize, const I1: usize, const I2: usize, const I3: usize>(
+     a: v128,
+     b: v128,
+ ) -> v128 {
+     let shuf = simd_shuffle4::<u32x4, u32x4>(
+         a.as_u32x4(),
+         b.as_u32x4(),
+         [I0 as u32, I1 as u32, I2 as u32, I3 as u32],
+     );
+     transmute(shuf)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(v8x16.shuffle)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn v32x4_shuffle_test(a: v128, b: v128) -> v128 {
+     v32x4_shuffle::<0, 2, 4, 6>(a, b)
+ }
+ 
+ /// Same as [`v8x16_shuffle`], except operates as if the inputs were two
+ /// 64-bit integers, only taking 2 indices to shuffle.
+ ///
+ /// Indices in the range [0, 1] select from `a` while [2, 3] select from `b`.
+ /// Note that this will generate the `v8x16.shuffle` instruction, since there
+ /// is no native `v64x2.shuffle` instruction (there is no need for one since
+ /// `v8x16.shuffle` suffices).
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v64x2_shuffle<const I0: usize, const I1: usize>(a: v128, b: v128) -> v128 {
+     let shuf = simd_shuffle2::<u64x2, u64x2>(a.as_u64x2(), b.as_u64x2(), [I0 as u32, I1 as u32]);
+     transmute(shuf)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(v8x16.shuffle)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn v64x2_shuffle_test(a: v128, b: v128) -> v128 {
+     v64x2_shuffle::<0, 2>(a, b)
+ }
+ 
+ /// Returns a new vector with lanes selected from the lanes of the first input
+ /// vector `a` specified in the second input vector `s`.
+ ///
+ /// The indices `i` in range [0, 15] select the `i`-th element of `a`. For
+ /// indices outside of the range the resulting lane is 0.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v8x16.swizzle))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v8x16_swizzle(a: v128, s: v128) -> v128 {
+     transmute(llvm_swizzle(transmute(a), transmute(s)))
+ }
+ 
+ /// Creates a vector with identical lanes.
+ ///
+ /// Constructs a vector with `x` replicated to all 16 lanes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_splat(a: i8) -> v128 {
+     transmute(i8x16::splat(a))
+ }
+ 
+ /// Creates a vector with identical lanes.
+ ///
+ /// Construct a vector with `x` replicated to all 8 lanes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_splat(a: i16) -> v128 {
+     transmute(i16x8::splat(a))
+ }
+ 
+ /// Creates a vector with identical lanes.
+ ///
+ /// Constructs a vector with `x` replicated to all 4 lanes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_splat(a: i32) -> v128 {
+     transmute(i32x4::splat(a))
+ }
+ 
+ /// Creates a vector with identical lanes.
+ ///
+ /// Construct a vector with `x` replicated to all 2 lanes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_splat(a: i64) -> v128 {
+     transmute(i64x2::splat(a))
+ }
+ 
+ /// Creates a vector with identical lanes.
+ ///
+ /// Constructs a vector with `x` replicated to all 4 lanes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_splat(a: f32) -> v128 {
+     transmute(f32x4::splat(a))
+ }
+ 
+ /// Creates a vector with identical lanes.
+ ///
+ /// Constructs a vector with `x` replicated to all 2 lanes.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.splat))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_splat(a: f64) -> v128 {
+     transmute(f64x2::splat(a))
+ }
+ 
+ /// Extracts a lane from a 128-bit vector interpreted as 16 packed i8 numbers.
+ ///
+ /// Extracts the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_extract_lane<const N: usize>(a: v128) -> i8 {
+     simd_extract(a.as_i8x16(), N as u32)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i8x16.extract_lane_s)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i8x16_extract_lane_s(a: v128) -> i32 {
+     i8x16_extract_lane::<0>(a) as i32
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i8x16.extract_lane_u)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i8x16_extract_lane_u(a: v128) -> u32 {
+     i8x16_extract_lane::<0>(a) as u8 as u32
+ }
+ 
+ /// Replaces a lane from a 128-bit vector interpreted as 16 packed i8 numbers.
+ ///
+ /// Replaces the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_replace_lane<const N: usize>(a: v128, val: i8) -> v128 {
+     transmute(simd_insert(a.as_i8x16(), N as u32, val))
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i8x16.replace_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i8x16_replace_lane_test(a: v128, val: i8) -> v128 {
+     i8x16_replace_lane::<0>(a, val)
+ }
+ 
+ /// Extracts a lane from a 128-bit vector interpreted as 8 packed i16 numbers.
+ ///
+ /// Extracts a the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_extract_lane<const N: usize>(a: v128) -> i16 {
+     simd_extract(a.as_i16x8(), N as u32)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i16x8.extract_lane_s)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i16x8_extract_lane_s(a: v128) -> i32 {
+     i16x8_extract_lane::<0>(a) as i32
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i16x8.extract_lane_u)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i16x8_extract_lane_u(a: v128) -> u32 {
+     i16x8_extract_lane::<0>(a) as u16 as u32
+ }
+ 
+ /// Replaces a lane from a 128-bit vector interpreted as 8 packed i16 numbers.
+ ///
+ /// Replaces the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_replace_lane<const N: usize>(a: v128, val: i16) -> v128 {
+     transmute(simd_insert(a.as_i16x8(), N as u32, val))
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i16x8.replace_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i16x8_replace_lane_test(a: v128, val: i16) -> v128 {
+     i16x8_replace_lane::<0>(a, val)
+ }
+ 
+ /// Extracts a lane from a 128-bit vector interpreted as 4 packed i32 numbers.
+ ///
+ /// Extracts the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_extract_lane<const N: usize>(a: v128) -> i32 {
+     simd_extract(a.as_i32x4(), N as u32)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i32x4.extract_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i32x4_extract_lane_test(a: v128) -> i32 {
+     i32x4_extract_lane::<0>(a)
+ }
+ 
+ /// Replaces a lane from a 128-bit vector interpreted as 4 packed i32 numbers.
+ ///
+ /// Replaces the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_replace_lane<const N: usize>(a: v128, val: i32) -> v128 {
+     transmute(simd_insert(a.as_i32x4(), N as u32, val))
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i32x4.replace_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i32x4_replace_lane_test(a: v128, val: i32) -> v128 {
+     i32x4_replace_lane::<0>(a, val)
+ }
+ 
+ /// Extracts a lane from a 128-bit vector interpreted as 2 packed i64 numbers.
+ ///
+ /// Extracts the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_extract_lane<const N: usize>(a: v128) -> i64 {
+     simd_extract(a.as_i64x2(), N as u32)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i64x2.extract_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i64x2_extract_lane_test(a: v128) -> i64 {
+     i64x2_extract_lane::<0>(a)
+ }
+ 
+ /// Replaces a lane from a 128-bit vector interpreted as 2 packed i64 numbers.
+ ///
+ /// Replaces the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_replace_lane<const N: usize>(a: v128, val: i64) -> v128 {
+     transmute(simd_insert(a.as_i64x2(), N as u32, val))
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(i64x2.replace_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn i64x2_replace_lane_test(a: v128, val: i64) -> v128 {
+     i64x2_replace_lane::<0>(a, val)
+ }
+ 
+ /// Extracts a lane from a 128-bit vector interpreted as 4 packed f32 numbers.
+ ///
+ /// Extracts the scalar value of lane specified fn the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_extract_lane<const N: usize>(a: v128) -> f32 {
+     simd_extract(a.as_f32x4(), N as u32)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(f32x4.extract_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn f32x4_extract_lane_test(a: v128) -> f32 {
+     f32x4_extract_lane::<0>(a)
+ }
+ 
+ /// Replaces a lane from a 128-bit vector interpreted as 4 packed f32 numbers.
+ ///
+ /// Replaces the scalar value of lane specified fn the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_replace_lane<const N: usize>(a: v128, val: f32) -> v128 {
+     transmute(simd_insert(a.as_f32x4(), N as u32, val))
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(f32x4.replace_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn f32x4_replace_lane_test(a: v128, val: f32) -> v128 {
+     f32x4_replace_lane::<0>(a, val)
+ }
+ 
+ /// Extracts a lane from a 128-bit vector interpreted as 2 packed f64 numbers.
+ ///
+ /// Extracts the scalar value of lane specified fn the immediate mode operand
+ /// `N` from `a`. If `N` fs out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_extract_lane<const N: usize>(a: v128) -> f64 {
+     simd_extract(a.as_f64x2(), N as u32)
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(f64x2.extract_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn f64x2_extract_lane_test(a: v128) -> f64 {
+     f64x2_extract_lane::<0>(a)
+ }
+ 
+ /// Replaces a lane from a 128-bit vector interpreted as 2 packed f64 numbers.
+ ///
+ /// Replaces the scalar value of lane specified in the immediate mode operand
+ /// `N` from `a`. If `N` is out of bounds then it is a compile time error.
+ #[inline]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_replace_lane<const N: usize>(a: v128, val: f64) -> v128 {
+     transmute(simd_insert(a.as_f64x2(), N as u32, val))
+ }
+ 
+ #[cfg(test)]
+ #[assert_instr(f64x2.replace_lane)]
+ #[target_feature(enable = "simd128")]
+ unsafe fn f64x2_replace_lane_test(a: v128, val: f64) -> v128 {
+     f64x2_replace_lane::<0>(a, val)
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were equal, or all zeros if the elements were not equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.eq))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_eq(a: v128, b: v128) -> v128 {
+     transmute(simd_eq::<_, i8x16>(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were not equal, or all zeros if the elements were equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.ne))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_ne(a: v128, b: v128) -> v128 {
+     transmute(simd_ne::<_, i8x16>(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.lt_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_lt_s(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i8x16>(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.lt_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_lt_u(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i8x16>(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.gt_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_gt_s(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i8x16>(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.gt_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_gt_u(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i8x16>(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.le_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_le_s(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i8x16>(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.le_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_le_u(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i8x16>(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.ge_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_ge_s(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i8x16>(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 16 eight-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.ge_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_ge_u(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i8x16>(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were equal, or all zeros if the elements were not equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.eq))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_eq(a: v128, b: v128) -> v128 {
+     transmute(simd_eq::<_, i16x8>(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were not equal, or all zeros if the elements were equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.ne))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_ne(a: v128, b: v128) -> v128 {
+     transmute(simd_ne::<_, i16x8>(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.lt_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_lt_s(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i16x8>(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.lt_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_lt_u(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i16x8>(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.gt_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_gt_s(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i16x8>(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.gt_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_gt_u(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i16x8>(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.le_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_le_s(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i16x8>(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.le_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_le_u(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i16x8>(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.ge_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_ge_s(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i16x8>(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.ge_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_ge_u(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i16x8>(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were equal, or all zeros if the elements were not equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.eq))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_eq(a: v128, b: v128) -> v128 {
+     transmute(simd_eq::<_, i32x4>(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were not equal, or all zeros if the elements were equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.ne))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_ne(a: v128, b: v128) -> v128 {
+     transmute(simd_ne::<_, i32x4>(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.lt_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_lt_s(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i32x4>(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.lt_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_lt_u(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i32x4>(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.gt_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_gt_s(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i32x4>(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.gt_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_gt_u(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i32x4>(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.le_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_le_s(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i32x4>(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.le_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_le_u(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i32x4>(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// signed integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.ge_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_ge_s(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i32x4>(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// unsigned integers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.ge_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_ge_u(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i32x4>(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were equal, or all zeros if the elements were not equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.eq))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_eq(a: v128, b: v128) -> v128 {
+     transmute(simd_eq::<_, i32x4>(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were not equal, or all zeros if the elements were equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.ne))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_ne(a: v128, b: v128) -> v128 {
+     transmute(simd_ne::<_, i32x4>(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.lt))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_lt(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i32x4>(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.gt))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_gt(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i32x4>(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.le))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_le(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i32x4>(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.ge))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_ge(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i32x4>(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were equal, or all zeros if the elements were not equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.eq))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_eq(a: v128, b: v128) -> v128 {
+     transmute(simd_eq::<_, i64x2>(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise elements
+ /// were not equal, or all zeros if the elements were equal.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.ne))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_ne(a: v128, b: v128) -> v128 {
+     transmute(simd_ne::<_, i64x2>(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.lt))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_lt(a: v128, b: v128) -> v128 {
+     transmute(simd_lt::<_, i64x2>(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.gt))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_gt(a: v128, b: v128) -> v128 {
+     transmute(simd_gt::<_, i64x2>(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is less than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.le))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_le(a: v128, b: v128) -> v128 {
+     transmute(simd_le::<_, i64x2>(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit
+ /// floating point numbers.
+ ///
+ /// Returns a new vector where each lane is all ones if the pairwise left
+ /// element is greater than the pairwise right element, or all zeros otherwise.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.ge))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_ge(a: v128, b: v128) -> v128 {
+     transmute(simd_ge::<_, i64x2>(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Flips each bit of the 128-bit input vector.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.not))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_not(a: v128) -> v128 {
+     transmute(simd_xor(a.as_i64x2(), i64x2(!0, !0)))
+ }
+ 
+ /// Performs a bitwise and of the two input 128-bit vectors, returning the
+ /// resulting vector.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.and))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_and(a: v128, b: v128) -> v128 {
+     transmute(simd_and(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Bitwise AND of bits of `a` and the logical inverse of bits of `b`.
+ ///
+ /// This operation is equivalent to `v128.and(a, v128.not(b))`
+ #[inline]
+ #[cfg_attr(all(test, all_simd), assert_instr(v128.andnot))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_andnot(a: v128, b: v128) -> v128 {
+     transmute(simd_and(
+         a.as_i64x2(),
+         simd_xor(b.as_i64x2(), i64x2(-1, -1)),
+     ))
+ }
+ 
+ /// Performs a bitwise or of the two input 128-bit vectors, returning the
+ /// resulting vector.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.or))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_or(a: v128, b: v128) -> v128 {
+     transmute(simd_or(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Performs a bitwise xor of the two input 128-bit vectors, returning the
+ /// resulting vector.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.xor))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_xor(a: v128, b: v128) -> v128 {
+     transmute(simd_xor(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Use the bitmask in `c` to select bits from `v1` when 1 and `v2` when 0.
+ #[inline]
+ #[cfg_attr(test, assert_instr(v128.bitselect))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn v128_bitselect(v1: v128, v2: v128, c: v128) -> v128 {
+     transmute(llvm_bitselect(v1.as_i8x16(), v2.as_i8x16(), c.as_i8x16()))
+ }
+ 
+ /// Lane-wise wrapping absolute value.
+ #[inline]
+ // #[cfg_attr(test, assert_instr(i8x16.abs))] // FIXME support not in our LLVM yet
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_abs(a: v128) -> v128 {
+     let a = transmute::<_, i8x16>(a);
+     let zero = i8x16::splat(0);
+     transmute(simd_select::<m8x16, i8x16>(
+         simd_lt(a, zero),
+         simd_sub(zero, a),
+         a,
+     ))
+ }
+ 
+ /// Negates a 128-bit vectors intepreted as sixteen 8-bit signed integers
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.neg))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_neg(a: v128) -> v128 {
+     transmute(simd_mul(a.as_i8x16(), i8x16::splat(-1)))
+ }
+ 
+ /// Returns 1 if any lane is nonzero or 0 if all lanes are zero.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.any_true))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_any_true(a: v128) -> i32 {
+     llvm_i8x16_any_true(a.as_i8x16())
+ }
+ 
+ /// Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.all_true))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_all_true(a: v128) -> i32 {
+     llvm_i8x16_all_true(a.as_i8x16())
+ }
+ 
+ // FIXME: not available in our LLVM yet
+ // /// Extracts the high bit for each lane in `a` and produce a scalar mask with
+ // /// all bits concatenated.
+ // #[inline]
+ // #[cfg_attr(test, assert_instr(i8x16.all_true))]
+ // pub unsafe fn i8x16_bitmask(a: v128) -> i32 {
+ //     llvm_bitmask_i8x16(transmute(a))
+ // }
+ 
+ /// Converts two input vectors into a smaller lane vector by narrowing each
+ /// lane.
+ ///
+ /// Signed saturation to 0x7f or 0x80 is used and the input lanes are always
+ /// interpreted as signed integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.narrow_i16x8_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_narrow_i16x8_s(a: v128, b: v128) -> v128 {
+     transmute(llvm_narrow_i8x16_s(transmute(a), transmute(b)))
+ }
+ 
+ /// Converts two input vectors into a smaller lane vector by narrowing each
+ /// lane.
+ ///
+ /// Signed saturation to 0x00 or 0xff is used and the input lanes are always
+ /// interpreted as signed integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.narrow_i16x8_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_narrow_i16x8_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_narrow_i8x16_u(transmute(a), transmute(b)))
+ }
+ 
+ /// Shifts each lane to the left by the specified number of bits.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.shl))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_shl(a: v128, amt: u32) -> v128 {
+     transmute(simd_shl(a.as_i8x16(), i8x16::splat(amt as i8)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, sign
+ /// extending.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.shr_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_shr_s(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_i8x16(), i8x16::splat(amt as i8)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, shifting in
+ /// zeros.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.shr_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_shr_u(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_u8x16(), u8x16::splat(amt as u8)))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed sixteen 8-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.add))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_add(a: v128, b: v128) -> v128 {
+     transmute(simd_add(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed sixteen 8-bit signed
+ /// integers, saturating on overflow to `i8::MAX`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.add_saturate_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_add_saturate_s(a: v128, b: v128) -> v128 {
+     transmute(llvm_i8x16_add_saturate_s(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed sixteen 8-bit unsigned
+ /// integers, saturating on overflow to `u8::MAX`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.add_saturate_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_add_saturate_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_i8x16_add_saturate_u(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.sub))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_sub(a: v128, b: v128) -> v128 {
+     transmute(simd_sub(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit
+ /// signed integers, saturating on overflow to `i8::MIN`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.sub_saturate_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_sub_saturate_s(a: v128, b: v128) -> v128 {
+     transmute(llvm_i8x16_sub_saturate_s(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit
+ /// unsigned integers, saturating on overflow to 0.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.sub_saturate_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_sub_saturate_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_i8x16_sub_saturate_u(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares lane-wise signed integers, and returns the minimum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.min_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_min_s(a: v128, b: v128) -> v128 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     transmute(simd_select::<i8x16, _>(simd_lt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise unsigned integers, and returns the minimum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.min_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_min_u(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, u8x16>(a);
+     let b = transmute::<_, u8x16>(b);
+     transmute(simd_select::<i8x16, _>(simd_lt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise signed integers, and returns the maximum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.max_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_max_s(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, i8x16>(a);
+     let b = transmute::<_, i8x16>(b);
+     transmute(simd_select::<i8x16, _>(simd_gt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise unsigned integers, and returns the maximum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.max_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_max_u(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, u8x16>(a);
+     let b = transmute::<_, u8x16>(b);
+     transmute(simd_select::<i8x16, _>(simd_gt(a, b), a, b))
+ }
+ 
+ /// Lane-wise rounding average.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i8x16.avgr_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i8x16_avgr_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_avgr_u_i8x16(transmute(a), transmute(b)))
+ }
+ 
+ /// Lane-wise wrapping absolute value.
+ #[inline]
+ // #[cfg_attr(test, assert_instr(i16x8.abs))] // FIXME support not in our LLVM yet
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_abs(a: v128) -> v128 {
+     let a = transmute::<_, i16x8>(a);
+     let zero = i16x8::splat(0);
+     transmute(simd_select::<m16x8, i16x8>(
+         simd_lt(a, zero),
+         simd_sub(zero, a),
+         a,
+     ))
+ }
+ 
+ /// Negates a 128-bit vectors intepreted as eight 16-bit signed integers
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.neg))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_neg(a: v128) -> v128 {
+     transmute(simd_mul(a.as_i16x8(), i16x8::splat(-1)))
+ }
+ 
+ /// Returns 1 if any lane is nonzero or 0 if all lanes are zero.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.any_true))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_any_true(a: v128) -> i32 {
+     llvm_i16x8_any_true(a.as_i16x8())
+ }
+ 
+ /// Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.all_true))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_all_true(a: v128) -> i32 {
+     llvm_i16x8_all_true(a.as_i16x8())
+ }
+ 
+ // FIXME: not available in our LLVM yet
+ // /// Extracts the high bit for each lane in `a` and produce a scalar mask with
+ // /// all bits concatenated.
+ // #[inline]
+ // #[cfg_attr(test, assert_instr(i16x8.all_true))]
+ // pub unsafe fn i16x8_bitmask(a: v128) -> i32 {
+ //     llvm_bitmask_i16x8(transmute(a))
+ // }
+ 
+ /// Converts two input vectors into a smaller lane vector by narrowing each
+ /// lane.
+ ///
+ /// Signed saturation to 0x7fff or 0x8000 is used and the input lanes are always
+ /// interpreted as signed integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.narrow_i32x4_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_narrow_i32x4_s(a: v128, b: v128) -> v128 {
+     transmute(llvm_narrow_i16x8_s(transmute(a), transmute(b)))
+ }
+ 
+ /// Converts two input vectors into a smaller lane vector by narrowing each
+ /// lane.
+ ///
+ /// Signed saturation to 0x0000 or 0xffff is used and the input lanes are always
+ /// interpreted as signed integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.narrow_i32x4_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_narrow_i32x4_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_narrow_i16x8_u(transmute(a), transmute(b)))
+ }
+ 
+ /// Converts low half of the smaller lane vector to a larger lane
+ /// vector, sign extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.widen_low_i8x16_s))]
+ pub unsafe fn i16x8_widen_low_i8x16_s(a: v128) -> v128 {
+     transmute(llvm_widen_low_i16x8_s(transmute(a)))
+ }
+ 
+ /// Converts high half of the smaller lane vector to a larger lane
+ /// vector, sign extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.widen_high_i8x16_s))]
+ pub unsafe fn i16x8_widen_high_i8x16_s(a: v128) -> v128 {
+     transmute(llvm_widen_high_i16x8_s(transmute(a)))
+ }
+ 
+ /// Converts low half of the smaller lane vector to a larger lane
+ /// vector, zero extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.widen_low_i8x16_u))]
+ pub unsafe fn i16x8_widen_low_i8x16_u(a: v128) -> v128 {
+     transmute(llvm_widen_low_i16x8_u(transmute(a)))
+ }
+ 
+ /// Converts high half of the smaller lane vector to a larger lane
+ /// vector, zero extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.widen_high_i8x16_u))]
+ pub unsafe fn i16x8_widen_high_i8x16_u(a: v128) -> v128 {
+     transmute(llvm_widen_high_i16x8_u(transmute(a)))
+ }
+ 
+ /// Shifts each lane to the left by the specified number of bits.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.shl))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_shl(a: v128, amt: u32) -> v128 {
+     transmute(simd_shl(a.as_i16x8(), i16x8::splat(amt as i16)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, sign
+ /// extending.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.shr_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_shr_s(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_i16x8(), i16x8::splat(amt as i16)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, shifting in
+ /// zeros.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.shr_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_shr_u(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_u16x8(), u16x8::splat(amt as u16)))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed eight 16-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.add))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_add(a: v128, b: v128) -> v128 {
+     transmute(simd_add(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed eight 16-bit signed
+ /// integers, saturating on overflow to `i16::MAX`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.add_saturate_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_add_saturate_s(a: v128, b: v128) -> v128 {
+     transmute(llvm_i16x8_add_saturate_s(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed eight 16-bit unsigned
+ /// integers, saturating on overflow to `u16::MAX`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.add_saturate_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_add_saturate_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_i16x8_add_saturate_u(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed eight 16-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.sub))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_sub(a: v128, b: v128) -> v128 {
+     transmute(simd_sub(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed eight 16-bit
+ /// signed integers, saturating on overflow to `i16::MIN`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.sub_saturate_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_sub_saturate_s(a: v128, b: v128) -> v128 {
+     transmute(llvm_i16x8_sub_saturate_s(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed eight 16-bit
+ /// unsigned integers, saturating on overflow to 0.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.sub_saturate_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_sub_saturate_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_i16x8_sub_saturate_u(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Multiplies two 128-bit vectors as if they were two packed eight 16-bit
+ /// signed integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.mul))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_mul(a: v128, b: v128) -> v128 {
+     transmute(simd_mul(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares lane-wise signed integers, and returns the minimum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.min_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_min_s(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, i16x8>(a);
+     let b = transmute::<_, i16x8>(b);
+     transmute(simd_select::<i16x8, _>(simd_lt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise unsigned integers, and returns the minimum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.min_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_min_u(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, u16x8>(a);
+     let b = transmute::<_, u16x8>(b);
+     transmute(simd_select::<i16x8, _>(simd_lt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise signed integers, and returns the maximum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.max_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_max_s(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, i16x8>(a);
+     let b = transmute::<_, i16x8>(b);
+     transmute(simd_select::<i16x8, _>(simd_gt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise unsigned integers, and returns the maximum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.max_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_max_u(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, u16x8>(a);
+     let b = transmute::<_, u16x8>(b);
+     transmute(simd_select::<i16x8, _>(simd_gt(a, b), a, b))
+ }
+ 
+ /// Lane-wise rounding average.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i16x8.avgr_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i16x8_avgr_u(a: v128, b: v128) -> v128 {
+     transmute(llvm_avgr_u_i16x8(transmute(a), transmute(b)))
+ }
+ 
+ /// Lane-wise wrapping absolute value.
+ #[inline]
+ // #[cfg_attr(test, assert_instr(i32x4.abs))] // FIXME support not in our LLVM yet
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_abs(a: v128) -> v128 {
+     let a = transmute::<_, i32x4>(a);
+     let zero = i32x4::splat(0);
+     transmute(simd_select::<m32x4, i32x4>(
+         simd_lt(a, zero),
+         simd_sub(zero, a),
+         a,
+     ))
+ }
+ 
+ /// Negates a 128-bit vectors intepreted as four 32-bit signed integers
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.neg))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_neg(a: v128) -> v128 {
+     transmute(simd_mul(a.as_i32x4(), i32x4::splat(-1)))
+ }
+ 
+ /// Returns 1 if any lane is nonzero or 0 if all lanes are zero.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.any_true))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_any_true(a: v128) -> i32 {
+     llvm_i32x4_any_true(a.as_i32x4())
+ }
+ 
+ /// Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.all_true))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_all_true(a: v128) -> i32 {
+     llvm_i32x4_all_true(a.as_i32x4())
+ }
+ 
+ // FIXME: not available in our LLVM yet
+ // /// Extracts the high bit for each lane in `a` and produce a scalar mask with
+ // /// all bits concatenated.
+ // #[inline]
+ // #[cfg_attr(test, assert_instr(i32x4.all_true))]
+ // pub unsafe fn i32x4_bitmask(a: v128) -> i32 {
+ //     llvm_bitmask_i32x4(transmute(a))
+ // }
+ 
+ /// Converts low half of the smaller lane vector to a larger lane
+ /// vector, sign extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.widen_low_i16x8_s))]
+ pub unsafe fn i32x4_widen_low_i16x8_s(a: v128) -> v128 {
+     transmute(llvm_widen_low_i32x4_s(transmute(a)))
+ }
+ 
+ /// Converts high half of the smaller lane vector to a larger lane
+ /// vector, sign extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.widen_high_i16x8_s))]
+ pub unsafe fn i32x4_widen_high_i16x8_s(a: v128) -> v128 {
+     transmute(llvm_widen_high_i32x4_s(transmute(a)))
+ }
+ 
+ /// Converts low half of the smaller lane vector to a larger lane
+ /// vector, zero extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.widen_low_i16x8_u))]
+ pub unsafe fn i32x4_widen_low_i16x8_u(a: v128) -> v128 {
+     transmute(llvm_widen_low_i32x4_u(transmute(a)))
+ }
+ 
+ /// Converts high half of the smaller lane vector to a larger lane
+ /// vector, zero extended.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.widen_high_i16x8_u))]
+ pub unsafe fn i32x4_widen_high_i16x8_u(a: v128) -> v128 {
+     transmute(llvm_widen_high_i32x4_u(transmute(a)))
+ }
+ 
+ /// Shifts each lane to the left by the specified number of bits.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.shl))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_shl(a: v128, amt: u32) -> v128 {
+     transmute(simd_shl(a.as_i32x4(), i32x4::splat(amt as i32)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, sign
+ /// extending.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.shr_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_shr_s(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_i32x4(), i32x4::splat(amt as i32)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, shifting in
+ /// zeros.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.shr_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_shr_u(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_u32x4(), u32x4::splat(amt as u32)))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed four 32-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.add))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_add(a: v128, b: v128) -> v128 {
+     transmute(simd_add(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed four 32-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.sub))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_sub(a: v128, b: v128) -> v128 {
+     transmute(simd_sub(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Multiplies two 128-bit vectors as if they were two packed four 32-bit
+ /// signed integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.mul))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_mul(a: v128, b: v128) -> v128 {
+     transmute(simd_mul(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares lane-wise signed integers, and returns the minimum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.min_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_min_s(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, i32x4>(a);
+     let b = transmute::<_, i32x4>(b);
+     transmute(simd_select::<i32x4, _>(simd_lt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise unsigned integers, and returns the minimum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.min_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_min_u(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, u32x4>(a);
+     let b = transmute::<_, u32x4>(b);
+     transmute(simd_select::<i32x4, _>(simd_lt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise signed integers, and returns the maximum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.max_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_max_s(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, i32x4>(a);
+     let b = transmute::<_, i32x4>(b);
+     transmute(simd_select::<i32x4, _>(simd_gt(a, b), a, b))
+ }
+ 
+ /// Compares lane-wise unsigned integers, and returns the maximum of
+ /// each pair.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i32x4.max_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_max_u(a: v128, b: v128) -> v128 {
+     let a = transmute::<_, u32x4>(a);
+     let b = transmute::<_, u32x4>(b);
+     transmute(simd_select::<i32x4, _>(simd_gt(a, b), a, b))
+ }
+ 
+ /// Negates a 128-bit vectors intepreted as two 64-bit signed integers
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.neg))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_neg(a: v128) -> v128 {
+     transmute(simd_mul(a.as_i64x2(), i64x2::splat(-1)))
+ }
+ 
+ /// Shifts each lane to the left by the specified number of bits.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.shl))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_shl(a: v128, amt: u32) -> v128 {
+     transmute(simd_shl(a.as_i64x2(), i64x2::splat(amt as i64)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, sign
+ /// extending.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.shr_s))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_shr_s(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_i64x2(), i64x2::splat(amt as i64)))
+ }
+ 
+ /// Shifts each lane to the right by the specified number of bits, shifting in
+ /// zeros.
+ ///
+ /// Only the low bits of the shift amount are used if the shift amount is
+ /// greater than the lane width.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.shr_u))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_shr_u(a: v128, amt: u32) -> v128 {
+     transmute(simd_shr(a.as_u64x2(), u64x2::splat(amt as u64)))
+ }
+ 
+ /// Adds two 128-bit vectors as if they were two packed two 64-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.add))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_add(a: v128, b: v128) -> v128 {
+     transmute(simd_add(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Subtracts two 128-bit vectors as if they were two packed two 64-bit integers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(i64x2.sub))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_sub(a: v128, b: v128) -> v128 {
+     transmute(simd_sub(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Multiplies two 128-bit vectors as if they were two packed two 64-bit integers.
+ #[inline]
+ // #[cfg_attr(test, assert_instr(i64x2.mul))] // FIXME: not present in our LLVM
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i64x2_mul(a: v128, b: v128) -> v128 {
+     transmute(simd_mul(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Calculates the absolute value of each lane of a 128-bit vector interpreted
+ /// as four 32-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.abs))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_abs(a: v128) -> v128 {
+     transmute(llvm_f32x4_abs(a.as_f32x4()))
+ }
+ 
+ /// Negates each lane of a 128-bit vector interpreted as four 32-bit floating
+ /// point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.neg))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_neg(a: v128) -> v128 {
+     f32x4_mul(a, transmute(f32x4(-1.0, -1.0, -1.0, -1.0)))
+ }
+ 
+ /// Calculates the square root of each lane of a 128-bit vector interpreted as
+ /// four 32-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.sqrt))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_sqrt(a: v128) -> v128 {
+     transmute(llvm_f32x4_sqrt(a.as_f32x4()))
+ }
+ 
+ /// Adds pairwise lanes of two 128-bit vectors interpreted as four 32-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.add))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_add(a: v128, b: v128) -> v128 {
+     transmute(simd_add(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Subtracts pairwise lanes of two 128-bit vectors interpreted as four 32-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.sub))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_sub(a: v128, b: v128) -> v128 {
+     transmute(simd_sub(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Multiplies pairwise lanes of two 128-bit vectors interpreted as four 32-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.mul))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_mul(a: v128, b: v128) -> v128 {
+     transmute(simd_mul(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Divides pairwise lanes of two 128-bit vectors interpreted as four 32-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.div))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_div(a: v128, b: v128) -> v128 {
+     transmute(simd_div(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Calculates the minimum of pairwise lanes of two 128-bit vectors interpreted
+ /// as four 32-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.min))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_min(a: v128, b: v128) -> v128 {
+     transmute(llvm_f32x4_min(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Calculates the maximum of pairwise lanes of two 128-bit vectors interpreted
+ /// as four 32-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f32x4.max))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_max(a: v128, b: v128) -> v128 {
+     transmute(llvm_f32x4_max(a.as_f32x4(), b.as_f32x4()))
+ }
+ 
+ /// Calculates the absolute value of each lane of a 128-bit vector interpreted
+ /// as two 64-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.abs))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_abs(a: v128) -> v128 {
+     transmute(llvm_f64x2_abs(a.as_f64x2()))
+ }
+ 
+ /// Negates each lane of a 128-bit vector interpreted as two 64-bit floating
+ /// point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.neg))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_neg(a: v128) -> v128 {
+     f64x2_mul(a, transmute(f64x2(-1.0, -1.0)))
+ }
+ 
+ /// Calculates the square root of each lane of a 128-bit vector interpreted as
+ /// two 64-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.sqrt))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_sqrt(a: v128) -> v128 {
+     transmute(llvm_f64x2_sqrt(a.as_f64x2()))
+ }
+ 
+ /// Adds pairwise lanes of two 128-bit vectors interpreted as two 64-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.add))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_add(a: v128, b: v128) -> v128 {
+     transmute(simd_add(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Subtracts pairwise lanes of two 128-bit vectors interpreted as two 64-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.sub))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_sub(a: v128, b: v128) -> v128 {
+     transmute(simd_sub(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Multiplies pairwise lanes of two 128-bit vectors interpreted as two 64-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.mul))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_mul(a: v128, b: v128) -> v128 {
+     transmute(simd_mul(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Divides pairwise lanes of two 128-bit vectors interpreted as two 64-bit
+ /// floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.div))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_div(a: v128, b: v128) -> v128 {
+     transmute(simd_div(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Calculates the minimum of pairwise lanes of two 128-bit vectors interpreted
+ /// as two 64-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.min))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_min(a: v128, b: v128) -> v128 {
+     transmute(llvm_f64x2_min(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Calculates the maximum of pairwise lanes of two 128-bit vectors interpreted
+ /// as two 64-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr(f64x2.max))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f64x2_max(a: v128, b: v128) -> v128 {
+     transmute(llvm_f64x2_max(a.as_f64x2(), b.as_f64x2()))
+ }
+ 
+ /// Converts a 128-bit vector interpreted as four 32-bit floating point numbers
+ /// into a 128-bit vector of four 32-bit signed integers.
+ ///
+ /// NaN is converted to 0 and if it's out of bounds it becomes the nearest
+ /// representable intger.
+ #[inline]
+ #[cfg_attr(test, assert_instr("i32x4.trunc_sat_f32x4_s"))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_trunc_sat_f32x4_s(a: v128) -> v128 {
+     transmute(simd_cast::<_, i32x4>(a.as_f32x4()))
+ }
+ 
+ /// Converts a 128-bit vector interpreted as four 32-bit floating point numbers
+ /// into a 128-bit vector of four 32-bit unsigned integers.
+ ///
+ /// NaN is converted to 0 and if it's out of bounds it becomes the nearest
+ /// representable intger.
+ #[inline]
+ #[cfg_attr(test, assert_instr("i32x4.trunc_sat_f32x4_u"))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn i32x4_trunc_sat_f32x4_u(a: v128) -> v128 {
+     transmute(simd_cast::<_, u32x4>(a.as_f32x4()))
+ }
+ 
+ /// Converts a 128-bit vector interpreted as four 32-bit signed integers into a
+ /// 128-bit vector of four 32-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr("f32x4.convert_i32x4_s"))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_convert_i32x4_s(a: v128) -> v128 {
+     transmute(simd_cast::<_, f32x4>(a.as_i32x4()))
+ }
+ 
+ /// Converts a 128-bit vector interpreted as four 32-bit unsigned integers into a
+ /// 128-bit vector of four 32-bit floating point numbers.
+ #[inline]
+ #[cfg_attr(test, assert_instr("f32x4.convert_i32x4_u"))]
+ #[target_feature(enable = "simd128")]
+ pub unsafe fn f32x4_convert_i32x4_u(a: v128) -> v128 {
+     transmute(simd_cast::<_, f32x4>(a.as_u32x4()))
+ }
+ 
+ #[cfg(test)]
+ pub mod tests {
+     use super::*;
+     use std;
+     use std::mem;
+     use std::num::Wrapping;
+     use std::prelude::v1::*;
+ 
+     fn compare_bytes(a: v128, b: v128) {
+         let a: [u8; 16] = unsafe { transmute(a) };
+         let b: [u8; 16] = unsafe { transmute(b) };
+         assert_eq!(a, b);
+     }
+ 
+     #[test]
+     fn test_v128_const() {
+         const A: v128 =
+             unsafe { super::i8x16_const(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) };
+         compare_bytes(A, A);
+     }
+ 
+     macro_rules! test_splat {
+         ($test_id:ident: $val:expr => $($vals:expr),*) => {
+             #[test]
+             fn $test_id() {
+                 unsafe {
+                 let a = super::$test_id($val);
+                 let b: v128 = transmute([$($vals as u8),*]);
+                 compare_bytes(a, b);
+                 }
+             }
+         }
+     }
+ 
+     test_splat!(i8x16_splat: 42 => 42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42);
+     test_splat!(i16x8_splat: 42 => 42, 0, 42, 0, 42, 0, 42, 0, 42, 0, 42, 0, 42, 0, 42, 0);
+     test_splat!(i32x4_splat: 42 => 42, 0, 0, 0, 42, 0, 0, 0, 42, 0, 0, 0, 42, 0, 0, 0);
+     test_splat!(i64x2_splat: 42 => 42, 0, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0);
+     test_splat!(f32x4_splat: 42. => 0, 0, 40, 66, 0, 0, 40, 66, 0, 0, 40, 66, 0, 0, 40, 66);
+     test_splat!(f64x2_splat: 42. => 0, 0, 0, 0, 0, 0, 69, 64, 0, 0, 0, 0, 0, 0, 69, 64);
+ 
+     // tests extract and replace lanes
+     macro_rules! test_extract {
+         (
+             name: $test_id:ident,
+             extract: $extract:ident,
+             replace: $replace:ident,
+             elem: $elem:ty,
+             count: $count:expr,
+             indices: [$($idx:expr),*],
+         ) => {
+             #[test]
+             fn $test_id() {
+                 unsafe {
+                     let arr: [$elem; $count] = [123 as $elem; $count];
+                     let vec: v128 = transmute(arr);
+                     $(
+                         assert_eq!($extract::<$idx>(vec), 123 as $elem);
+                     )*
+ 
+                     // create a vector from array and check that the indices contain
+                     // the same values as in the array:
+                     let arr: [$elem; $count] = [$($idx as $elem),*];
+                     let vec: v128 = transmute(arr);
+                     $(
+                         assert_eq!($extract::<$idx>(vec), $idx as $elem);
+ 
+                         let tmp = $replace::<$idx>(vec, 124 as $elem);
+                         assert_eq!($extract::<$idx>(tmp), 124 as $elem);
+                     )*
+                 }
+             }
+         }
+     }
+ 
+     test_extract! {
+         name: test_i8x16_extract_replace,
+         extract: i8x16_extract_lane,
+         replace: i8x16_replace_lane,
+         elem: i8,
+         count: 16,
+         indices: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+     }
+     test_extract! {
+         name: test_i16x8_extract_replace,
+         extract: i16x8_extract_lane,
+         replace: i16x8_replace_lane,
+         elem: i16,
+         count: 8,
+         indices: [0, 1, 2, 3, 4, 5, 6, 7],
+     }
+     test_extract! {
+         name: test_i32x4_extract_replace,
+         extract: i32x4_extract_lane,
+         replace: i32x4_replace_lane,
+         elem: i32,
+         count: 4,
+         indices: [0, 1, 2, 3],
+     }
+     test_extract! {
+         name: test_i64x2_extract_replace,
+         extract: i64x2_extract_lane,
+         replace: i64x2_replace_lane,
+         elem: i64,
+         count: 2,
+         indices: [0, 1],
+     }
+     test_extract! {
+         name: test_f32x4_extract_replace,
+         extract: f32x4_extract_lane,
+         replace: f32x4_replace_lane,
+         elem: f32,
+         count: 4,
+         indices: [0, 1, 2, 3],
+     }
+     test_extract! {
+         name: test_f64x2_extract_replace,
+         extract: f64x2_extract_lane,
+         replace: f64x2_replace_lane,
+         elem: f64,
+         count: 2,
+         indices: [0, 1],
+     }
+ 
+     macro_rules! test_binop {
+         (
+             $($name:ident => {
+                 $([$($vec1:tt)*] ($op:tt | $f:ident) [$($vec2:tt)*],)*
+             })*
+         ) => ($(
+             #[test]
+             fn $name() {
+                 unsafe {
+                     $(
+                         let v1 = [$($vec1)*];
+                         let v2 = [$($vec2)*];
+                         let v1_v128: v128 = mem::transmute(v1);
+                         let v2_v128: v128 = mem::transmute(v2);
+                         let v3_v128 = super::$f(v1_v128, v2_v128);
+                         let mut v3 = [$($vec1)*];
+                         drop(v3);
+                         v3 = mem::transmute(v3_v128);
+ 
+                         for (i, actual) in v3.iter().enumerate() {
+                             let expected = (Wrapping(v1[i]) $op Wrapping(v2[i])).0;
+                             assert_eq!(*actual, expected);
+                         }
+                     )*
+                 }
+             }
+         )*)
+     }
+ 
+     macro_rules! test_unop {
+         (
+             $($name:ident => {
+                 $(($op:tt | $f:ident) [$($vec1:tt)*],)*
+             })*
+         ) => ($(
+             #[test]
+             fn $name() {
+                 unsafe {
+                     $(
+                         let v1 = [$($vec1)*];
+                         let v1_v128: v128 = mem::transmute(v1);
+                         let v2_v128 = super::$f(v1_v128);
+                         let mut v2 = [$($vec1)*];
+                         drop(v2);
+                         v2 = mem::transmute(v2_v128);
+ 
+                         for (i, actual) in v2.iter().enumerate() {
+                             let expected = ($op Wrapping(v1[i])).0;
+                             assert_eq!(*actual, expected);
+                         }
+                     )*
+                 }
+             }
+         )*)
+     }
+ 
+     test_binop! {
+         test_i8x16_add => {
+             [0i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+                 (+ | i8x16_add)
+             [1i8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
+ 
+             [1i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+                 (+ | i8x16_add)
+             [-2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16, -18],
+ 
+             [1i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+                 (+ | i8x16_add)
+             [127, -44, 43, 126, 4, 2, 9, -3, -59, -43, 39, -69, 79, -3, 9, -24],
+         }
+         test_i8x16_sub => {
+             [0i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+                 (- | i8x16_sub)
+             [1i8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
+ 
+             [1i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+                 (- | i8x16_sub)
+             [-2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16, -18],
+ 
+             [1i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+                 (- | i8x16_sub)
+             [-127, -44, 43, 126, 4, 2, 9, -3, -59, -43, 39, -69, 79, -3, 4, 8],
+         }
+ 
+         test_i16x8_add => {
+             [0i16, 0, 0, 0, 0, 0, 0, 0]
+                 (+ | i16x8_add)
+             [1i16, 1, 1, 1, 1, 1, 1, 1],
+ 
+             [1i16, 2, 3, 4, 5, 6, 7, 8]
+                 (+ | i16x8_add)
+             [32767, 8, -2494,-4, 4882, -4, 848, 3830],
+         }
+ 
+         test_i16x8_sub => {
+             [0i16, 0, 0, 0, 0, 0, 0, 0]
+                 (- | i16x8_sub)
+             [1i16, 1, 1, 1, 1, 1, 1, 1],
+ 
+             [1i16, 2, 3, 4, 5, 6, 7, 8]
+                 (- | i16x8_sub)
+             [32767, 8, -2494,-4, 4882, -4, 848, 3830],
+         }
+ 
+         test_i16x8_mul => {
+             [0i16, 0, 0, 0, 0, 0, 0, 0]
+                 (* | i16x8_mul)
+             [1i16, 1, 1, 1, 1, 1, 1, 1],
+ 
+             [1i16, 2, 3, 4, 5, 6, 7, 8]
+                 (* | i16x8_mul)
+             [32767, 8, -2494,-4, 4882, -4, 848, 3830],
+         }
+ 
+         test_i32x4_add => {
+             [0i32, 0, 0, 0] (+ | i32x4_add) [1, 2, 3, 4],
+             [1i32, 1283, i32::MAX, i32::MIN]
+                 (+ | i32x4_add)
+             [i32::MAX; 4],
+         }
+ 
+         test_i32x4_sub => {
+             [0i32, 0, 0, 0] (- | i32x4_sub) [1, 2, 3, 4],
+             [1i32, 1283, i32::MAX, i32::MIN]
+                 (- | i32x4_sub)
+             [i32::MAX; 4],
+         }
+ 
+         test_i32x4_mul => {
+             [0i32, 0, 0, 0] (* | i32x4_mul) [1, 2, 3, 4],
+             [1i32, 1283, i32::MAX, i32::MIN]
+                 (* | i32x4_mul)
+             [i32::MAX; 4],
+         }
+ 
+         // TODO: test_i64x2_add
+         // TODO: test_i64x2_sub
+     }
+ 
+     test_unop! {
+         test_i8x16_neg => {
+             (- | i8x16_neg)
+             [1i8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
+ 
+             (- | i8x16_neg)
+             [-2i8, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16, -18],
+ 
+             (- | i8x16_neg)
+             [-127i8, -44, 43, 126, 4, -128, 127, -59, -43, 39, -69, 79, -3, 35, 83, 13],
+         }
+ 
+         test_i16x8_neg => {
+             (- | i16x8_neg) [1i16, 1, 1, 1, 1, 1, 1, 1],
+             (- | i16x8_neg) [2i16, 0x7fff, !0, 4, 42, -5, 33, -4847],
+         }
+ 
+         test_i32x4_neg => {
+             (- | i32x4_neg) [1i32, 2, 3, 4],
+             (- | i32x4_neg) [i32::MIN, i32::MAX, 0, 4],
+         }
+ 
+         // TODO: test_i64x2_neg
+     }
+ 
+     #[test]
+     fn test_v8x16_shuffle() {
+         unsafe {
+             let a = [0_u8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
+             let b = [
+                 16_u8, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+             ];
+ 
+             let vec_a: v128 = transmute(a);
+             let vec_b: v128 = transmute(b);
+ 
+             let vec_r = v8x16_shuffle::<0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30>(
+                 vec_a, vec_b,
+             );
+ 
+             let e = [0_u8, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30];
+             let vec_e: v128 = transmute(e);
+             compare_bytes(vec_r, vec_e);
+         }
+     }
+ 
+     macro_rules! floating_point {
+         (f32) => {
+             true
+         };
+         (f64) => {
+             true
+         };
+         ($id:ident) => {
+             false
+         };
+     }
+ 
+     trait IsNan: Sized {
+         fn is_nan(self) -> bool {
+             false
+         }
+     }
+     impl IsNan for i8 {}
+     impl IsNan for i16 {}
+     impl IsNan for i32 {}
+     impl IsNan for i64 {}
+ 
+     macro_rules! test_bop {
+          ($id:ident[$ety:ident; $ecount:expr] |
+           $binary_op:ident [$op_test_id:ident] :
+           ([$($in_a:expr),*], [$($in_b:expr),*]) => [$($out:expr),*]) => {
+              test_bop!(
+                  $id[$ety; $ecount] => $ety | $binary_op [ $op_test_id ]:
+                  ([$($in_a),*], [$($in_b),*]) => [$($out),*]
+              );
+ 
+          };
+          ($id:ident[$ety:ident; $ecount:expr] => $oty:ident |
+           $binary_op:ident [$op_test_id:ident] :
+           ([$($in_a:expr),*], [$($in_b:expr),*]) => [$($out:expr),*]) => {
+              #[test]
+              fn $op_test_id() {
+                  unsafe {
+                      let a_input: [$ety; $ecount] = [$($in_a),*];
+                      let b_input: [$ety; $ecount] = [$($in_b),*];
+                      let output: [$oty; $ecount] = [$($out),*];
+ 
+                      let a_vec_in: v128 = transmute(a_input);
+                      let b_vec_in: v128 = transmute(b_input);
+                      let vec_res: v128 = $binary_op(a_vec_in, b_vec_in);
+ 
+                      let res: [$oty; $ecount] = transmute(vec_res);
+ 
+                      if !floating_point!($ety) {
+                          assert_eq!(res, output);
+                      } else {
+                          for i in 0..$ecount {
+                              let r = res[i];
+                              let o = output[i];
+                              assert_eq!(r.is_nan(), o.is_nan());
+                              if !r.is_nan() {
+                                  assert_eq!(r, o);
+                              }
+                          }
+                      }
+                  }
+              }
+          }
+      }
+ 
+     macro_rules! test_bops {
+          ($id:ident[$ety:ident; $ecount:expr] |
+           $binary_op:ident [$op_test_id:ident]:
+           ([$($in_a:expr),*], $in_b:expr) => [$($out:expr),*]) => {
+              #[test]
+              fn $op_test_id() {
+                  unsafe {
+                      let a_input: [$ety; $ecount] = [$($in_a),*];
+                      let output: [$ety; $ecount] = [$($out),*];
+ 
+                      let a_vec_in: v128 = transmute(a_input);
+                      let vec_res: v128 = $binary_op(a_vec_in, $in_b);
+ 
+                      let res: [$ety; $ecount] = transmute(vec_res);
+                      assert_eq!(res, output);
+                  }
+              }
+          }
+      }
+ 
+     macro_rules! test_uop {
+          ($id:ident[$ety:ident; $ecount:expr] |
+           $unary_op:ident [$op_test_id:ident]: [$($in_a:expr),*] => [$($out:expr),*]) => {
+              #[test]
+              fn $op_test_id() {
+                  unsafe {
+                      let a_input: [$ety; $ecount] = [$($in_a),*];
+                      let output: [$ety; $ecount] = [$($out),*];
+ 
+                      let a_vec_in: v128 = transmute(a_input);
+                      let vec_res: v128 = $unary_op(a_vec_in);
+ 
+                      let res: [$ety; $ecount] = transmute(vec_res);
+                      assert_eq!(res, output);
+                  }
+              }
+          }
+      }
+ 
+     test_bops!(i8x16[i8; 16] | i8x16_shl[i8x16_shl_test]:
+                ([0, -1, 2, 3, 4, 5, 6, i8::MAX, 1, 1, 1, 1, 1, 1, 1, 1], 1) =>
+                [0, -2, 4, 6, 8, 10, 12, -2, 2, 2, 2, 2, 2, 2, 2, 2]);
+     test_bops!(i16x8[i16; 8] | i16x8_shl[i16x8_shl_test]:
+                 ([0, -1, 2, 3, 4, 5, 6, i16::MAX], 1) =>
+                 [0, -2, 4, 6, 8, 10, 12, -2]);
+     test_bops!(i32x4[i32; 4] | i32x4_shl[i32x4_shl_test]:
+                 ([0, -1, 2, 3], 1) => [0, -2, 4, 6]);
+     test_bops!(i64x2[i64; 2] | i64x2_shl[i64x2_shl_test]:
+                 ([0, -1], 1) => [0, -2]);
+ 
+     test_bops!(i8x16[i8; 16] | i8x16_shr_s[i8x16_shr_s_test]:
+                ([0, -1, 2, 3, 4, 5, 6, i8::MAX, 1, 1, 1, 1, 1, 1, 1, 1], 1) =>
+                [0, -1, 1, 1, 2, 2, 3, 63, 0, 0, 0, 0, 0, 0, 0, 0]);
+     test_bops!(i16x8[i16; 8] | i16x8_shr_s[i16x8_shr_s_test]:
+                ([0, -1, 2, 3, 4, 5, 6, i16::MAX], 1) =>
+                [0, -1, 1, 1, 2, 2, 3, i16::MAX / 2]);
+     test_bops!(i32x4[i32; 4] | i32x4_shr_s[i32x4_shr_s_test]:
+                ([0, -1, 2, 3], 1) => [0, -1, 1, 1]);
+     test_bops!(i64x2[i64; 2] | i64x2_shr_s[i64x2_shr_s_test]:
+                ([0, -1], 1) => [0, -1]);
+ 
+     test_bops!(i8x16[i8; 16] | i8x16_shr_u[i8x16_uhr_u_test]:
+                 ([0, -1, 2, 3, 4, 5, 6, i8::MAX, 1, 1, 1, 1, 1, 1, 1, 1], 1) =>
+                 [0, i8::MAX, 1, 1, 2, 2, 3, 63, 0, 0, 0, 0, 0, 0, 0, 0]);
+     test_bops!(i16x8[i16; 8] | i16x8_shr_u[i16x8_uhr_u_test]:
+                 ([0, -1, 2, 3, 4, 5, 6, i16::MAX], 1) =>
+                 [0, i16::MAX, 1, 1, 2, 2, 3, i16::MAX / 2]);
+     test_bops!(i32x4[i32; 4] | i32x4_shr_u[i32x4_uhr_u_test]:
+                 ([0, -1, 2, 3], 1) => [0, i32::MAX, 1, 1]);
+     test_bops!(i64x2[i64; 2] | i64x2_shr_u[i64x2_uhr_u_test]:
+                 ([0, -1], 1) => [0, i64::MAX]);
+ 
+     #[test]
+     fn v128_bitwise_logical_ops() {
+         unsafe {
+             let a: [u32; 4] = [u32::MAX, 0, u32::MAX, 0];
+             let b: [u32; 4] = [u32::MAX; 4];
+             let c: [u32; 4] = [0; 4];
+ 
+             let vec_a: v128 = transmute(a);
+             let vec_b: v128 = transmute(b);
+             let vec_c: v128 = transmute(c);
+ 
+             let r: v128 = v128_and(vec_a, vec_a);
+             compare_bytes(r, vec_a);
+             let r: v128 = v128_and(vec_a, vec_b);
+             compare_bytes(r, vec_a);
+             let r: v128 = v128_or(vec_a, vec_b);
+             compare_bytes(r, vec_b);
+             let r: v128 = v128_not(vec_b);
+             compare_bytes(r, vec_c);
+             let r: v128 = v128_xor(vec_a, vec_c);
+             compare_bytes(r, vec_a);
+ 
+             let r: v128 = v128_bitselect(vec_b, vec_c, vec_b);
+             compare_bytes(r, vec_b);
+             let r: v128 = v128_bitselect(vec_b, vec_c, vec_c);
+             compare_bytes(r, vec_c);
+             let r: v128 = v128_bitselect(vec_b, vec_c, vec_a);
+             compare_bytes(r, vec_a);
+         }
+     }
+ 
+     macro_rules! test_bool_red {
+          ([$test_id:ident, $any:ident, $all:ident] | [$($true:expr),*] | [$($false:expr),*] | [$($alt:expr),*]) => {
+              #[test]
+              fn $test_id() {
+                  unsafe {
+                      let vec_a: v128 = transmute([$($true),*]); // true
+                      let vec_b: v128 = transmute([$($false),*]); // false
+                      let vec_c: v128 = transmute([$($alt),*]); // alternating
+ 
+                      assert_eq!($any(vec_a), 1);
+                      assert_eq!($any(vec_b), 0);
+                      assert_eq!($any(vec_c), 1);
+ 
+                      assert_eq!($all(vec_a), 1);
+                      assert_eq!($all(vec_b), 0);
+                      assert_eq!($all(vec_c), 0);
+                  }
+              }
+          }
+      }
+ 
+     test_bool_red!(
+         [i8x16_boolean_reductions, i8x16_any_true, i8x16_all_true]
+             | [1_i8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+             | [0_i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+             | [1_i8, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+     );
+     test_bool_red!(
+         [i16x8_boolean_reductions, i16x8_any_true, i16x8_all_true]
+             | [1_i16, 1, 1, 1, 1, 1, 1, 1]
+             | [0_i16, 0, 0, 0, 0, 0, 0, 0]
+             | [1_i16, 0, 1, 0, 1, 0, 1, 0]
+     );
+     test_bool_red!(
+         [i32x4_boolean_reductions, i32x4_any_true, i32x4_all_true]
+             | [1_i32, 1, 1, 1]
+             | [0_i32, 0, 0, 0]
+             | [1_i32, 0, 1, 0]
+     );
+ 
+     test_bop!(i8x16[i8; 16] | i8x16_eq[i8x16_eq_test]:
+               ([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+                [0, 2, 2, 4, 4, 6, 6, 7, 8, 10, 10, 12, 12, 14, 14, 15]) =>
+               [-1, 0, -1, 0 ,-1, 0, -1, -1, -1, 0, -1, 0 ,-1, 0, -1, -1]);
+     test_bop!(i16x8[i16; 8] | i16x8_eq[i16x8_eq_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 2, 4, 4, 6, 6, 7]) =>
+                [-1, 0, -1, 0 ,-1, 0, -1, -1]);
+     test_bop!(i32x4[i32; 4] | i32x4_eq[i32x4_eq_test]:
+                ([0, 1, 2, 3], [0, 2, 2, 4]) => [-1, 0, -1, 0]);
+     test_bop!(f32x4[f32; 4] => i32 | f32x4_eq[f32x4_eq_test]:
+                ([0., 1., 2., 3.], [0., 2., 2., 4.]) => [-1, 0, -1, 0]);
+     test_bop!(f64x2[f64; 2] => i64 | f64x2_eq[f64x2_eq_test]: ([0., 1.], [0., 2.]) => [-1, 0]);
+ 
+     test_bop!(i8x16[i8; 16] | i8x16_ne[i8x16_ne_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+                 [0, 2, 2, 4, 4, 6, 6, 7, 8, 10, 10, 12, 12, 14, 14, 15]) =>
+                [0, -1, 0, -1 ,0, -1, 0, 0, 0, -1, 0, -1 ,0, -1, 0, 0]);
+     test_bop!(i16x8[i16; 8] | i16x8_ne[i16x8_ne_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 2, 4, 4, 6, 6, 7]) =>
+                [0, -1, 0, -1 ,0, -1, 0, 0]);
+     test_bop!(i32x4[i32; 4] | i32x4_ne[i32x4_ne_test]:
+                ([0, 1, 2, 3], [0, 2, 2, 4]) => [0, -1, 0, -1]);
+     test_bop!(f32x4[f32; 4] => i32 | f32x4_ne[f32x4_ne_test]:
+                ([0., 1., 2., 3.], [0., 2., 2., 4.]) => [0, -1, 0, -1]);
+     test_bop!(f64x2[f64; 2] => i64 | f64x2_ne[f64x2_ne_test]: ([0., 1.], [0., 2.]) => [0, -1]);
+ 
+     test_bop!(i8x16[i8; 16] | i8x16_lt_s[i8x16_lt_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+                 [0, 2, 2, 4, 4, 6, 6, 7, 8, 10, 10, 12, 12, 14, 14, 15]) =>
+                [0, -1, 0, -1 ,0, -1, 0, 0, 0, -1, 0, -1 ,0, -1, 0, 0]);
+     test_bop!(i16x8[i16; 8] | i16x8_lt_s[i16x8_lt_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 2, 4, 4, 6, 6, 7]) =>
+                [0, -1, 0, -1 ,0, -1, 0, 0]);
+     test_bop!(i32x4[i32; 4] | i32x4_lt_s[i32x4_lt_test]:
+                ([0, 1, 2, 3], [0, 2, 2, 4]) => [0, -1, 0, -1]);
+     test_bop!(f32x4[f32; 4] => i32 | f32x4_lt[f32x4_lt_test]:
+                ([0., 1., 2., 3.], [0., 2., 2., 4.]) => [0, -1, 0, -1]);
+     test_bop!(f64x2[f64; 2] => i64 | f64x2_lt[f64x2_lt_test]: ([0., 1.], [0., 2.]) => [0, -1]);
+ 
+     test_bop!(i8x16[i8; 16] | i8x16_gt_s[i8x16_gt_test]:
+            ([0, 2, 2, 4, 4, 6, 6, 7, 8, 10, 10, 12, 12, 14, 14, 15],
+             [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) =>
+                [0, -1, 0, -1 ,0, -1, 0, 0, 0, -1, 0, -1 ,0, -1, 0, 0]);
+     test_bop!(i16x8[i16; 8] | i16x8_gt_s[i16x8_gt_test]:
+                ([0, 2, 2, 4, 4, 6, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7]) =>
+                [0, -1, 0, -1 ,0, -1, 0, 0]);
+     test_bop!(i32x4[i32; 4] | i32x4_gt_s[i32x4_gt_test]:
+                ([0, 2, 2, 4], [0, 1, 2, 3]) => [0, -1, 0, -1]);
+     test_bop!(f32x4[f32; 4] => i32 | f32x4_gt[f32x4_gt_test]:
+                ([0., 2., 2., 4.], [0., 1., 2., 3.]) => [0, -1, 0, -1]);
+     test_bop!(f64x2[f64; 2] => i64 | f64x2_gt[f64x2_gt_test]: ([0., 2.], [0., 1.]) => [0, -1]);
+ 
+     test_bop!(i8x16[i8; 16] | i8x16_ge_s[i8x16_ge_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+                 [0, 2, 2, 4, 4, 6, 6, 7, 8, 10, 10, 12, 12, 14, 14, 15]) =>
+                [-1, 0, -1, 0 ,-1, 0, -1, -1, -1, 0, -1, 0 ,-1, 0, -1, -1]);
+     test_bop!(i16x8[i16; 8] | i16x8_ge_s[i16x8_ge_test]:
+                ([0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 2, 4, 4, 6, 6, 7]) =>
+                [-1, 0, -1, 0 ,-1, 0, -1, -1]);
+     test_bop!(i32x4[i32; 4] | i32x4_ge_s[i32x4_ge_test]:
+                ([0, 1, 2, 3], [0, 2, 2, 4]) => [-1, 0, -1, 0]);
+     test_bop!(f32x4[f32; 4] => i32 | f32x4_ge[f32x4_ge_test]:
+                ([0., 1., 2., 3.], [0., 2., 2., 4.]) => [-1, 0, -1, 0]);
+     test_bop!(f64x2[f64; 2] => i64 | f64x2_ge[f64x2_ge_test]: ([0., 1.], [0., 2.]) => [-1, 0]);
+ 
+     test_bop!(i8x16[i8; 16] | i8x16_le_s[i8x16_le_test]:
+                ([0, 2, 2, 4, 4, 6, 6, 7, 8, 10, 10, 12, 12, 14, 14, 15],
+                 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
+                ) =>
+                [-1, 0, -1, 0 ,-1, 0, -1, -1, -1, 0, -1, 0 ,-1, 0, -1, -1]);
+     test_bop!(i16x8[i16; 8] | i16x8_le_s[i16x8_le_test]:
+                ([0, 2, 2, 4, 4, 6, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7]) =>
+                [-1, 0, -1, 0 ,-1, 0, -1, -1]);
+     test_bop!(i32x4[i32; 4] | i32x4_le_s[i32x4_le_test]:
+                ([0, 2, 2, 4], [0, 1, 2, 3]) => [-1, 0, -1, 0]);
+     test_bop!(f32x4[f32; 4] => i32 | f32x4_le[f32x4_le_test]:
+                ([0., 2., 2., 4.], [0., 1., 2., 3.]) => [-1, 0, -1, -0]);
+     test_bop!(f64x2[f64; 2] => i64 | f64x2_le[f64x2_le_test]: ([0., 2.], [0., 1.]) => [-1, 0]);
+ 
+     #[test]
+     fn v128_bitwise_load_store() {
+         unsafe {
+             let mut arr: [i32; 4] = [0, 1, 2, 3];
+ 
+             let vec = v128_load(arr.as_ptr() as *const v128);
+             let vec = i32x4_add(vec, vec);
+             v128_store(arr.as_mut_ptr() as *mut v128, vec);
+ 
+             assert_eq!(arr, [0, 2, 4, 6]);
+         }
+     }
+ 
+     test_uop!(f32x4[f32; 4] | f32x4_neg[f32x4_neg_test]: [0., 1., 2., 3.] => [ 0., -1., -2., -3.]);
+     test_uop!(f32x4[f32; 4] | f32x4_abs[f32x4_abs_test]: [0., -1., 2., -3.] => [ 0., 1., 2., 3.]);
+     test_bop!(f32x4[f32; 4] | f32x4_min[f32x4_min_test]:
+               ([0., -1., 7., 8.], [1., -3., -4., 10.]) => [0., -3., -4., 8.]);
+     test_bop!(f32x4[f32; 4] | f32x4_min[f32x4_min_test_nan]:
+               ([0., -1., 7., 8.], [1., -3., -4., std::f32::NAN])
+               => [0., -3., -4., std::f32::NAN]);
+     test_bop!(f32x4[f32; 4] | f32x4_max[f32x4_max_test]:
+               ([0., -1., 7., 8.], [1., -3., -4., 10.]) => [1., -1., 7., 10.]);
+     test_bop!(f32x4[f32; 4] | f32x4_max[f32x4_max_test_nan]:
+               ([0., -1., 7., 8.], [1., -3., -4., std::f32::NAN])
+               => [1., -1., 7., std::f32::NAN]);
+     test_bop!(f32x4[f32; 4] | f32x4_add[f32x4_add_test]:
+               ([0., -1., 7., 8.], [1., -3., -4., 10.]) => [1., -4., 3., 18.]);
+     test_bop!(f32x4[f32; 4] | f32x4_sub[f32x4_sub_test]:
+               ([0., -1., 7., 8.], [1., -3., -4., 10.]) => [-1., 2., 11., -2.]);
+     test_bop!(f32x4[f32; 4] | f32x4_mul[f32x4_mul_test]:
+               ([0., -1., 7., 8.], [1., -3., -4., 10.]) => [0., 3., -28., 80.]);
+     test_bop!(f32x4[f32; 4] | f32x4_div[f32x4_div_test]:
+               ([0., -8., 70., 8.], [1., 4., 10., 2.]) => [0., -2., 7., 4.]);
+ 
+     test_uop!(f64x2[f64; 2] | f64x2_neg[f64x2_neg_test]: [0., 1.] => [ 0., -1.]);
+     test_uop!(f64x2[f64; 2] | f64x2_abs[f64x2_abs_test]: [0., -1.] => [ 0., 1.]);
+     test_bop!(f64x2[f64; 2] | f64x2_min[f64x2_min_test]:
+                ([0., -1.], [1., -3.]) => [0., -3.]);
+     test_bop!(f64x2[f64; 2] | f64x2_min[f64x2_min_test_nan]:
+                ([7., 8.], [-4., std::f64::NAN])
+                => [ -4., std::f64::NAN]);
+     test_bop!(f64x2[f64; 2] | f64x2_max[f64x2_max_test]:
+                ([0., -1.], [1., -3.]) => [1., -1.]);
+     test_bop!(f64x2[f64; 2] | f64x2_max[f64x2_max_test_nan]:
+                ([7., 8.], [ -4., std::f64::NAN])
+                => [7., std::f64::NAN]);
+     test_bop!(f64x2[f64; 2] | f64x2_add[f64x2_add_test]:
+                ([0., -1.], [1., -3.]) => [1., -4.]);
+     test_bop!(f64x2[f64; 2] | f64x2_sub[f64x2_sub_test]:
+                ([0., -1.], [1., -3.]) => [-1., 2.]);
+     test_bop!(f64x2[f64; 2] | f64x2_mul[f64x2_mul_test]:
+                ([0., -1.], [1., -3.]) => [0., 3.]);
+     test_bop!(f64x2[f64; 2] | f64x2_div[f64x2_div_test]:
+                ([0., -8.], [1., 4.]) => [0., -2.]);
+ 
+     macro_rules! test_conv {
+         ($test_id:ident | $conv_id:ident | $to_ty:ident | $from:expr,  $to:expr) => {
+             #[test]
+             fn $test_id() {
+                 unsafe {
+                     let from: v128 = transmute($from);
+                     let to: v128 = transmute($to);
+ 
+                     let r: v128 = $conv_id(from);
+ 
+                     compare_bytes(r, to);
+                 }
+             }
+         };
+     }
+ 
+     test_conv!(
+         f32x4_convert_s_i32x4 | f32x4_convert_i32x4_s | f32x4 | [1_i32, 2, 3, 4],
+         [1_f32, 2., 3., 4.]
+     );
+     test_conv!(
+         f32x4_convert_u_i32x4 | f32x4_convert_i32x4_u | f32x4 | [u32::MAX, 2, 3, 4],
+         [u32::MAX as f32, 2., 3., 4.]
+     );
+ 
+     // FIXME: this fails, and produces 0 instead of saturating at i32::MAX
+     // test_conv!(
+     //     i32x4_trunc_s_f32x4_sat
+     //         | i32x4_trunc_sat_f32x4_s
+     //         | i32x4
+     //         | [f32::NAN, 2., (i32::MAX as f32 + 1.), 4.],
+     //     [0, 2, i32::MAX, 4]
+     // );
+     // FIXME: add other saturating tests
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/abm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/abm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/abm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/abm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,62 ----
+ //! Advanced Bit Manipulation (ABM) instructions
+ //!
+ //! The POPCNT and LZCNT have their own CPUID bits to indicate support.
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //! Instruction Set Reference, A-Z][intel64_ref].
+ //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ //! System Instructions][amd64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
+ //! available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wikipedia_bmi]:
+ //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Counts the leading most significant zero bits.
+ ///
+ /// When the operand is zero, it returns its size in bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_lzcnt_u32)
+ #[inline]
+ #[target_feature(enable = "lzcnt")]
+ #[cfg_attr(test, assert_instr(lzcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _lzcnt_u32(x: u32) -> u32 {
+     x.leading_zeros()
+ }
+ 
+ /// Counts the bits that are set.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_popcnt32)
+ #[inline]
+ #[target_feature(enable = "popcnt")]
+ #[cfg_attr(test, assert_instr(popcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _popcnt32(x: i32) -> i32 {
+     x.count_ones() as i32
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "lzcnt")]
+     unsafe fn test_lzcnt_u32() {
+         assert_eq!(_lzcnt_u32(0b0101_1010), 25);
+     }
+ 
+     #[simd_test(enable = "popcnt")]
+     unsafe fn test_popcnt32() {
+         assert_eq!(_popcnt32(0b0101_1010), 4);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/adx.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/adx.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/adx.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/adx.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,158 ----
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "unadjusted" {
+     #[link_name = "llvm.x86.addcarry.32"]
+     fn llvm_addcarry_u32(a: u8, b: u32, c: u32) -> (u8, u32);
+     #[link_name = "llvm.x86.addcarryx.u32"]
+     fn llvm_addcarryx_u32(a: u8, b: u32, c: u32, d: *mut u8) -> u8;
+     #[link_name = "llvm.x86.subborrow.32"]
+     fn llvm_subborrow_u32(a: u8, b: u32, c: u32) -> (u8, u32);
+ }
+ 
+ /// Adds unsigned 32-bit integers `a` and `b` with unsigned 8-bit carry-in `c_in`
+ /// (carry flag), and store the unsigned 32-bit result in `out`, and the carry-out
+ /// is returned (carry or overflow flag).
+ #[inline]
+ #[cfg_attr(test, assert_instr(adc))]
+ #[stable(feature = "simd_x86_adx", since = "1.33.0")]
+ pub unsafe fn _addcarry_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
+     let (a, b) = llvm_addcarry_u32(c_in, a, b);
+     *out = b;
+     a
+ }
+ 
+ /// Adds unsigned 32-bit integers `a` and `b` with unsigned 8-bit carry-in `c_in`
+ /// (carry or overflow flag), and store the unsigned 32-bit result in `out`, and
+ /// the carry-out is returned (carry or overflow flag).
+ #[inline]
+ #[target_feature(enable = "adx")]
+ #[cfg_attr(test, assert_instr(adc))]
+ #[stable(feature = "simd_x86_adx", since = "1.33.0")]
+ pub unsafe fn _addcarryx_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
+     llvm_addcarryx_u32(c_in, a, b, out as *mut _ as *mut u8)
+ }
+ 
+ /// Adds unsigned 32-bit integers `a` and `b` with unsigned 8-bit carry-in `c_in`
+ /// (carry or overflow flag), and store the unsigned 32-bit result in `out`, and
+ /// the carry-out is returned (carry or overflow flag).
+ #[inline]
+ #[cfg_attr(test, assert_instr(sbb))]
+ #[stable(feature = "simd_x86_adx", since = "1.33.0")]
+ pub unsafe fn _subborrow_u32(c_in: u8, a: u32, b: u32, out: &mut u32) -> u8 {
+     let (a, b) = llvm_subborrow_u32(c_in, a, b);
+     *out = b;
+     a
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[test]
+     fn test_addcarry_u32() {
+         unsafe {
+             let a = u32::MAX;
+             let mut out = 0;
+ 
+             let r = _addcarry_u32(0, a, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, 0);
+ 
+             let r = _addcarry_u32(0, a, 0, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, a);
+ 
+             let r = _addcarry_u32(1, a, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, 1);
+ 
+             let r = _addcarry_u32(1, a, 0, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, 0);
+ 
+             let r = _addcarry_u32(0, 3, 4, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 7);
+ 
+             let r = _addcarry_u32(1, 3, 4, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 8);
+         }
+     }
+ 
+     #[simd_test(enable = "adx")]
+     unsafe fn test_addcarryx_u32() {
+         let a = u32::MAX;
+         let mut out = 0;
+ 
+         let r = _addcarryx_u32(0, a, 1, &mut out);
+         assert_eq!(r, 1);
+         assert_eq!(out, 0);
+ 
+         let r = _addcarryx_u32(0, a, 0, &mut out);
+         assert_eq!(r, 0);
+         assert_eq!(out, a);
+ 
+         let r = _addcarryx_u32(1, a, 1, &mut out);
+         assert_eq!(r, 1);
+         assert_eq!(out, 1);
+ 
+         let r = _addcarryx_u32(1, a, 0, &mut out);
+         assert_eq!(r, 1);
+         assert_eq!(out, 0);
+ 
+         let r = _addcarryx_u32(0, 3, 4, &mut out);
+         assert_eq!(r, 0);
+         assert_eq!(out, 7);
+ 
+         let r = _addcarryx_u32(1, 3, 4, &mut out);
+         assert_eq!(r, 0);
+         assert_eq!(out, 8);
+     }
+ 
+     #[simd_test(enable = "adx")]
+     unsafe fn test_addcarryx_u32_2() {
+         unsafe fn add_1_2_3() -> u32 {
+             let mut out = 0;
+             _addcarryx_u32(1, 2, 3, &mut out);
+             out
+         }
+         assert_eq!(6, add_1_2_3());
+     }
+ 
+     #[test]
+     fn test_subborrow_u32() {
+         unsafe {
+             let a = u32::MAX;
+             let mut out = 0;
+ 
+             let r = _subborrow_u32(0, 0, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, a);
+ 
+             let r = _subborrow_u32(0, 0, 0, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 0);
+ 
+             let r = _subborrow_u32(1, 0, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, a - 1);
+ 
+             let r = _subborrow_u32(1, 0, 0, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, a);
+ 
+             let r = _subborrow_u32(0, 7, 3, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 4);
+ 
+             let r = _subborrow_u32(1, 7, 3, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 3);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/aes.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/aes.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/aes.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/aes.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,175 ----
+ //! AES New Instructions (AES-NI)
+ //!
+ //! The intrinsics here correspond to those in the `wmmintrin.h` C header.
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ 
+ use crate::core_arch::x86::__m128i;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.aesni.aesdec"]
+     fn aesdec(a: __m128i, round_key: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.aesni.aesdeclast"]
+     fn aesdeclast(a: __m128i, round_key: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.aesni.aesenc"]
+     fn aesenc(a: __m128i, round_key: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.aesni.aesenclast"]
+     fn aesenclast(a: __m128i, round_key: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.aesni.aesimc"]
+     fn aesimc(a: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.aesni.aeskeygenassist"]
+     fn aeskeygenassist(a: __m128i, imm8: u8) -> __m128i;
+ }
+ 
+ /// Performs one round of an AES decryption flow on data (state) in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesdec_si128)
+ #[inline]
+ #[target_feature(enable = "aes")]
+ #[cfg_attr(test, assert_instr(aesdec))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_aesdec_si128(a: __m128i, round_key: __m128i) -> __m128i {
+     aesdec(a, round_key)
+ }
+ 
+ /// Performs the last round of an AES decryption flow on data (state) in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesdeclast_si128)
+ #[inline]
+ #[target_feature(enable = "aes")]
+ #[cfg_attr(test, assert_instr(aesdeclast))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_aesdeclast_si128(a: __m128i, round_key: __m128i) -> __m128i {
+     aesdeclast(a, round_key)
+ }
+ 
+ /// Performs one round of an AES encryption flow on data (state) in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesenc_si128)
+ #[inline]
+ #[target_feature(enable = "aes")]
+ #[cfg_attr(test, assert_instr(aesenc))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_aesenc_si128(a: __m128i, round_key: __m128i) -> __m128i {
+     aesenc(a, round_key)
+ }
+ 
+ /// Performs the last round of an AES encryption flow on data (state) in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesenclast_si128)
+ #[inline]
+ #[target_feature(enable = "aes")]
+ #[cfg_attr(test, assert_instr(aesenclast))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_aesenclast_si128(a: __m128i, round_key: __m128i) -> __m128i {
+     aesenclast(a, round_key)
+ }
+ 
+ /// Performs the `InvMixColumns` transformation on `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesimc_si128)
+ #[inline]
+ #[target_feature(enable = "aes")]
+ #[cfg_attr(test, assert_instr(aesimc))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_aesimc_si128(a: __m128i) -> __m128i {
+     aesimc(a)
+ }
+ 
+ /// Assist in expanding the AES cipher key.
+ ///
+ /// Assist in expanding the AES cipher key by computing steps towards
+ /// generating a round key for encryption cipher using data from `a` and an
+ /// 8-bit round constant `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aeskeygenassist_si128)
+ #[inline]
+ #[target_feature(enable = "aes")]
+ #[cfg_attr(test, assert_instr(aeskeygenassist, imm8 = 0))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_aeskeygenassist_si128(a: __m128i, imm8: i32) -> __m128i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             aeskeygenassist(a, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     // The constants in the tests below are just bit patterns. They should not
+     // be interpreted as integers; signedness does not make sense for them, but
+     // __m128i happens to be defined in terms of signed integers.
+     #![allow(overflowing_literals)]
+ 
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "aes")]
+     unsafe fn test_mm_aesdec_si128() {
+         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664949.aspx.
+         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
+         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
+         let e = _mm_set_epi64x(0x044e4f5176fec48f, 0xb57ecfa381da39ee);
+         let r = _mm_aesdec_si128(a, k);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "aes")]
+     unsafe fn test_mm_aesdeclast_si128() {
+         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714178.aspx.
+         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
+         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
+         let e = _mm_set_epi64x(0x36cad57d9072bf9e, 0xf210dd981fa4a493);
+         let r = _mm_aesdeclast_si128(a, k);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "aes")]
+     unsafe fn test_mm_aesenc_si128() {
+         // Constants taken from https://msdn.microsoft.com/en-us/library/cc664810.aspx.
+         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
+         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
+         let e = _mm_set_epi64x(0x16ab0e57dfc442ed, 0x28e4ee1884504333);
+         let r = _mm_aesenc_si128(a, k);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "aes")]
+     unsafe fn test_mm_aesenclast_si128() {
+         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714136.aspx.
+         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
+         let k = _mm_set_epi64x(0x1133557799bbddff, 0x0022446688aaccee);
+         let e = _mm_set_epi64x(0xb6dd7df25d7ab320, 0x4b04f98cf4c860f8);
+         let r = _mm_aesenclast_si128(a, k);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "aes")]
+     unsafe fn test_mm_aesimc_si128() {
+         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714195.aspx.
+         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
+         let e = _mm_set_epi64x(0xc66c82284ee40aa0, 0x6633441122770055);
+         let r = _mm_aesimc_si128(a);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "aes")]
+     unsafe fn test_mm_aeskeygenassist_si128() {
+         // Constants taken from https://msdn.microsoft.com/en-us/library/cc714138.aspx.
+         let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff);
+         let e = _mm_set_epi64x(0x857c266b7c266e85, 0xeac4eea9c4eeacea);
+         let r = _mm_aeskeygenassist_si128(a, 5);
+         assert_eq_m128i(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,5064 ----
+ //! Advanced Vector Extensions (AVX)
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //! Instruction Set Reference, A-Z][intel64_ref]. - [AMD64 Architecture
+ //! Programmer's Manual, Volume 3: General-Purpose and System
+ //! Instructions][amd64_ref].
+ //!
+ //! [Wikipedia][wiki] provides a quick overview of the instructions available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     intrinsics,
+     mem::{self, transmute},
+     ptr,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Adds packed double-precision (64-bit) floating-point elements
+ /// in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vaddpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_add_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_add(a, b)
+ }
+ 
+ /// Adds packed single-precision (32-bit) floating-point elements in `a` and
+ /// `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vaddps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_add_ps(a: __m256, b: __m256) -> __m256 {
+     simd_add(a, b)
+ }
+ 
+ /// Computes the bitwise AND of a packed double-precision (64-bit)
+ /// floating-point elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_and_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // FIXME: Should be 'vandpd' instuction.
+ // See https://github.com/rust-lang/stdarch/issues/71
+ #[cfg_attr(test, assert_instr(vandps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_and_pd(a: __m256d, b: __m256d) -> __m256d {
+     let a: u64x4 = transmute(a);
+     let b: u64x4 = transmute(b);
+     transmute(simd_and(a, b))
+ }
+ 
+ /// Computes the bitwise AND of packed single-precision (32-bit) floating-point
+ /// elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_and_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vandps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_and_ps(a: __m256, b: __m256) -> __m256 {
+     let a: u32x8 = transmute(a);
+     let b: u32x8 = transmute(b);
+     transmute(simd_and(a, b))
+ }
+ 
+ /// Computes the bitwise OR packed double-precision (64-bit) floating-point
+ /// elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_or_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // FIXME: should be `vorpd` instuction.
+ // See <https://github.com/rust-lang/stdarch/issues/71>.
+ #[cfg_attr(test, assert_instr(vorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_or_pd(a: __m256d, b: __m256d) -> __m256d {
+     let a: u64x4 = transmute(a);
+     let b: u64x4 = transmute(b);
+     transmute(simd_or(a, b))
+ }
+ 
+ /// Computes the bitwise OR packed single-precision (32-bit) floating-point
+ /// elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_or_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_or_ps(a: __m256, b: __m256) -> __m256 {
+     let a: u32x8 = transmute(a);
+     let b: u32x8 = transmute(b);
+     transmute(simd_or(a, b))
+ }
+ 
+ /// Shuffles double-precision (64-bit) floating-point elements within 128-bit
+ /// lanes using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_shuffle_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vshufpd, imm8 = 0x1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_shuffle_pd(a: __m256d, b: __m256d, imm8: i32) -> __m256d {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle4(a, b, [$a, $b, $c, $d]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 3) & 0x1 {
+                 0 => shuffle4!($a, $b, $c, 6),
+                 _ => shuffle4!($a, $b, $c, 7),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0x1 {
+                 0 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 1) & 0x1 {
+                 0 => shuffle2!($a, 4),
+                 _ => shuffle2!($a, 5),
+             }
+         };
+     }
+     match imm8 & 0x1 {
+         0 => shuffle1!(0),
+         _ => shuffle1!(1),
+     }
+ }
+ 
+ /// Shuffles single-precision (32-bit) floating-point elements in `a` within
+ /// 128-bit lanes using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_shuffle_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vshufps, imm8 = 0x0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_shuffle_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 8, $e, $f, $g, 12),
+                 1 => shuffle4!($a, $b, $c, 9, $e, $f, $g, 13),
+                 2 => shuffle4!($a, $b, $c, 10, $e, $f, $g, 14),
+                 _ => shuffle4!($a, $b, $c, 11, $e, $f, $g, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 8, $e, $f, 12),
+                 1 => shuffle3!($a, $b, 9, $e, $f, 13),
+                 2 => shuffle3!($a, $b, 10, $e, $f, 14),
+                 _ => shuffle3!($a, $b, 11, $e, $f, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4),
+                 1 => shuffle2!($a, 1, $e, 5),
+                 2 => shuffle2!($a, 2, $e, 6),
+                 _ => shuffle2!($a, 3, $e, 7),
+             }
+         };
+     }
+     match imm8 & 0x3 {
+         0 => shuffle1!(0, 4),
+         1 => shuffle1!(1, 5),
+         2 => shuffle1!(2, 6),
+         _ => shuffle1!(3, 7),
+     }
+ }
+ 
+ /// Computes the bitwise NOT of packed double-precision (64-bit) floating-point
+ /// elements in `a`, and then AND with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_andnot_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // FIXME: should be `vandnpd` instruction.
+ #[cfg_attr(test, assert_instr(vandnps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_andnot_pd(a: __m256d, b: __m256d) -> __m256d {
+     let a: u64x4 = transmute(a);
+     let b: u64x4 = transmute(b);
+     transmute(simd_and(simd_xor(u64x4::splat(!(0_u64)), a), b))
+ }
+ 
+ /// Computes the bitwise NOT of packed single-precision (32-bit) floating-point
+ /// elements in `a`
+ /// and then AND with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_andnot_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vandnps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_andnot_ps(a: __m256, b: __m256) -> __m256 {
+     let a: u32x8 = transmute(a);
+     let b: u32x8 = transmute(b);
+     transmute(simd_and(simd_xor(u32x8::splat(!(0_u32)), a), b))
+ }
+ 
+ /// Compares packed double-precision (64-bit) floating-point elements
+ /// in `a` and `b`, and returns packed maximum values
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaxpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_fmax(a, b)
+ }
+ 
+ /// Compares packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and returns packed maximum values
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaxps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_ps(a: __m256, b: __m256) -> __m256 {
+     simd_fmax(a, b)
+ }
+ 
+ /// Compares packed double-precision (64-bit) floating-point elements
+ /// in `a` and `b`, and returns packed minimum values
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vminpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_fmin(a, b)
+ }
+ 
+ /// Compares packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and returns packed minimum values
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vminps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_ps(a: __m256, b: __m256) -> __m256 {
+     simd_fmin(a, b)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements
+ /// in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mul_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmulpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mul_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_mul(a, b)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a` and
+ /// `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mul_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmulps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mul_ps(a: __m256, b: __m256) -> __m256 {
+     simd_mul(a, b)
+ }
+ 
+ /// Alternatively adds and subtracts packed double-precision (64-bit)
+ /// floating-point elements in `a` to/from packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_addsub_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vaddsubpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_addsub_pd(a: __m256d, b: __m256d) -> __m256d {
+     addsubpd256(a, b)
+ }
+ 
+ /// Alternatively adds and subtracts packed single-precision (32-bit)
+ /// floating-point elements in `a` to/from packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_addsub_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vaddsubps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_addsub_ps(a: __m256, b: __m256) -> __m256 {
+     addsubps256(a, b)
+ }
+ 
+ /// Subtracts packed double-precision (64-bit) floating-point elements in `b`
+ /// from packed elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vsubpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sub_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_sub(a, b)
+ }
+ 
+ /// Subtracts packed single-precision (32-bit) floating-point elements in `b`
+ /// from packed elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vsubps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sub_ps(a: __m256, b: __m256) -> __m256 {
+     simd_sub(a, b)
+ }
+ 
+ /// Computes the division of each of the 8 packed 32-bit floating-point elements
+ /// in `a` by the corresponding packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_div_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vdivps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_div_ps(a: __m256, b: __m256) -> __m256 {
+     simd_div(a, b)
+ }
+ 
+ /// Computes the division of each of the 4 packed 64-bit floating-point elements
+ /// in `a` by the corresponding packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_div_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vdivpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_div_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_div(a, b)
+ }
+ 
+ /// Rounds packed double-precision (64-bit) floating point elements in `a`
+ /// according to the flag `b`. The value of `b` may be as follows:
+ ///
+ /// - `0x00`: Round to the nearest whole number.
+ /// - `0x01`: Round down, toward negative infinity.
+ /// - `0x02`: Round up, toward positive infinity.
+ /// - `0x03`: Truncate the values.
+ ///
+ /// For a complete list of options, check [the LLVM docs][llvm_docs].
+ ///
+ /// [llvm_docs]: https://github.com/llvm-mirror/clang/blob/dcd8d797b20291f1a6b3e0ddda085aa2bbb382a8/lib/Headers/avxintrin.h#L382
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_round_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vroundpd, b = 0x3))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_round_pd(a: __m256d, b: i32) -> __m256d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             roundpd256(a, $imm8)
+         };
+     }
+     constify_imm8!(b, call)
+ }
+ 
+ /// Rounds packed double-precision (64-bit) floating point elements in `a`
+ /// toward positive infinity.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_ceil_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vroundpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_ceil_pd(a: __m256d) -> __m256d {
+     simd_ceil(a)
+ }
+ 
+ /// Rounds packed double-precision (64-bit) floating point elements in `a`
+ /// toward negative infinity.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_floor_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vroundpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_floor_pd(a: __m256d) -> __m256d {
+     simd_floor(a)
+ }
+ 
+ /// Rounds packed single-precision (32-bit) floating point elements in `a`
+ /// according to the flag `b`. The value of `b` may be as follows:
+ ///
+ /// - `0x00`: Round to the nearest whole number.
+ /// - `0x01`: Round down, toward negative infinity.
+ /// - `0x02`: Round up, toward positive infinity.
+ /// - `0x03`: Truncate the values.
+ ///
+ /// For a complete list of options, check [the LLVM docs][llvm_docs].
+ ///
+ /// [llvm_docs]: https://github.com/llvm-mirror/clang/blob/dcd8d797b20291f1a6b3e0ddda085aa2bbb382a8/lib/Headers/avxintrin.h#L382
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_round_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vroundps, b = 0x00))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_round_ps(a: __m256, b: i32) -> __m256 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             roundps256(a, $imm8)
+         };
+     }
+     constify_imm8!(b, call)
+ }
+ 
+ /// Rounds packed single-precision (32-bit) floating point elements in `a`
+ /// toward positive infinity.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_ceil_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vroundps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_ceil_ps(a: __m256) -> __m256 {
+     simd_ceil(a)
+ }
+ 
+ /// Rounds packed single-precision (32-bit) floating point elements in `a`
+ /// toward negative infinity.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_floor_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vroundps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_floor_ps(a: __m256) -> __m256 {
+     simd_floor(a)
+ }
+ 
+ /// Returns the square root of packed single-precision (32-bit) floating point
+ /// elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sqrt_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vsqrtps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sqrt_ps(a: __m256) -> __m256 {
+     sqrtps256(a)
+ }
+ 
+ /// Returns the square root of packed double-precision (64-bit) floating point
+ /// elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sqrt_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vsqrtpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sqrt_pd(a: __m256d) -> __m256d {
+     simd_fsqrt(a)
+ }
+ 
+ /// Blends packed double-precision (64-bit) floating-point elements from
+ /// `a` and `b` using control mask `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blend_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // Note: LLVM7 prefers single-precision blend instructions when
+ // possible, see: https://bugs.llvm.org/show_bug.cgi?id=38194
+ // #[cfg_attr(test, assert_instr(vblendpd, imm8 = 9))]
+ #[cfg_attr(test, assert_instr(vblendps, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blend_pd(a: __m256d, b: __m256d, imm8: i32) -> __m256d {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! blend4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle4(a, b, [$a, $b, $c, $d]);
+         };
+     }
+     macro_rules! blend3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match imm8 & 0x8 {
+                 0 => blend4!($a, $b, $c, 3),
+                 _ => blend4!($a, $b, $c, 7),
+             }
+         };
+     }
+     macro_rules! blend2 {
+         ($a:expr, $b:expr) => {
+             match imm8 & 0x4 {
+                 0 => blend3!($a, $b, 2),
+                 _ => blend3!($a, $b, 6),
+             }
+         };
+     }
+     macro_rules! blend1 {
+         ($a:expr) => {
+             match imm8 & 0x2 {
+                 0 => blend2!($a, 1),
+                 _ => blend2!($a, 5),
+             }
+         };
+     }
+     match imm8 & 0x1 {
+         0 => blend1!(0),
+         _ => blend1!(4),
+     }
+ }
+ 
+ /// Blends packed single-precision (32-bit) floating-point elements from
+ /// `a` and `b` using control mask `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blend_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vblendps, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blend_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! blend4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! blend3 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => blend4!($a, $b, $c, $d, $e, $f, 6, 7),
+                 0b01 => blend4!($a, $b, $c, $d, $e, $f, 14, 7),
+                 0b10 => blend4!($a, $b, $c, $d, $e, $f, 6, 15),
+                 _ => blend4!($a, $b, $c, $d, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! blend2 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => blend3!($a, $b, $c, $d, 4, 5),
+                 0b01 => blend3!($a, $b, $c, $d, 12, 5),
+                 0b10 => blend3!($a, $b, $c, $d, 4, 13),
+                 _ => blend3!($a, $b, $c, $d, 12, 13),
+             }
+         };
+     }
+     macro_rules! blend1 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => blend2!($a, $b, 2, 3),
+                 0b01 => blend2!($a, $b, 10, 3),
+                 0b10 => blend2!($a, $b, 2, 11),
+                 _ => blend2!($a, $b, 10, 11),
+             }
+         };
+     }
+     match imm8 & 0b11 {
+         0b00 => blend1!(0, 1),
+         0b01 => blend1!(8, 1),
+         0b10 => blend1!(0, 9),
+         _ => blend1!(8, 9),
+     }
+ }
+ 
+ /// Blends packed double-precision (64-bit) floating-point elements from
+ /// `a` and `b` using `c` as a mask.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blendv_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vblendvpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blendv_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     vblendvpd(a, b, c)
+ }
+ 
+ /// Blends packed single-precision (32-bit) floating-point elements from
+ /// `a` and `b` using `c` as a mask.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blendv_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vblendvps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blendv_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     vblendvps(a, b, c)
+ }
+ 
+ /// Conditionally multiplies the packed single-precision (32-bit) floating-point
+ /// elements in `a` and `b` using the high 4 bits in `imm8`,
+ /// sum the four products, and conditionally return the sum
+ ///  using the low 4 bits of `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_dp_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vdpps, imm8 = 0x0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_dp_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vdpps(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Horizontal addition of adjacent pairs in the two packed vectors
+ /// of 4 64-bit floating points `a` and `b`.
+ /// In the result, sums of elements from `a` are returned in even locations,
+ /// while sums of elements from `b` are returned in odd locations.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vhaddpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hadd_pd(a: __m256d, b: __m256d) -> __m256d {
+     vhaddpd(a, b)
+ }
+ 
+ /// Horizontal addition of adjacent pairs in the two packed vectors
+ /// of 8 32-bit floating points `a` and `b`.
+ /// In the result, sums of elements from `a` are returned in locations of
+ /// indices 0, 1, 4, 5; while sums of elements from `b` are locations
+ /// 2, 3, 6, 7.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vhaddps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hadd_ps(a: __m256, b: __m256) -> __m256 {
+     vhaddps(a, b)
+ }
+ 
+ /// Horizontal subtraction of adjacent pairs in the two packed vectors
+ /// of 4 64-bit floating points `a` and `b`.
+ /// In the result, sums of elements from `a` are returned in even locations,
+ /// while sums of elements from `b` are returned in odd locations.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hsub_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vhsubpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hsub_pd(a: __m256d, b: __m256d) -> __m256d {
+     vhsubpd(a, b)
+ }
+ 
+ /// Horizontal subtraction of adjacent pairs in the two packed vectors
+ /// of 8 32-bit floating points `a` and `b`.
+ /// In the result, sums of elements from `a` are returned in locations of
+ /// indices 0, 1, 4, 5; while sums of elements from `b` are locations
+ /// 2, 3, 6, 7.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hsub_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vhsubps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hsub_ps(a: __m256, b: __m256) -> __m256 {
+     vhsubps(a, b)
+ }
+ 
+ /// Computes the bitwise XOR of packed double-precision (64-bit) floating-point
+ /// elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_xor_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // FIXME Should be 'vxorpd' instruction.
+ #[cfg_attr(test, assert_instr(vxorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_xor_pd(a: __m256d, b: __m256d) -> __m256d {
+     let a: u64x4 = transmute(a);
+     let b: u64x4 = transmute(b);
+     transmute(simd_xor(a, b))
+ }
+ 
+ /// Computes the bitwise XOR of packed single-precision (32-bit) floating-point
+ /// elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_xor_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vxorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_xor_ps(a: __m256, b: __m256) -> __m256 {
+     let a: u32x8 = transmute(a);
+     let b: u32x8 = transmute(b);
+     transmute(simd_xor(a, b))
+ }
+ 
+ /// Equal (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_EQ_OQ: i32 = 0x00;
+ /// Less-than (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_LT_OS: i32 = 0x01;
+ /// Less-than-or-equal (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_LE_OS: i32 = 0x02;
+ /// Unordered (non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_UNORD_Q: i32 = 0x03;
+ /// Not-equal (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NEQ_UQ: i32 = 0x04;
+ /// Not-less-than (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NLT_US: i32 = 0x05;
+ /// Not-less-than-or-equal (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NLE_US: i32 = 0x06;
+ /// Ordered (non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_ORD_Q: i32 = 0x07;
+ /// Equal (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_EQ_UQ: i32 = 0x08;
+ /// Not-greater-than-or-equal (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NGE_US: i32 = 0x09;
+ /// Not-greater-than (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NGT_US: i32 = 0x0a;
+ /// False (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_FALSE_OQ: i32 = 0x0b;
+ /// Not-equal (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NEQ_OQ: i32 = 0x0c;
+ /// Greater-than-or-equal (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_GE_OS: i32 = 0x0d;
+ /// Greater-than (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_GT_OS: i32 = 0x0e;
+ /// True (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_TRUE_UQ: i32 = 0x0f;
+ /// Equal (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_EQ_OS: i32 = 0x10;
+ /// Less-than (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_LT_OQ: i32 = 0x11;
+ /// Less-than-or-equal (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_LE_OQ: i32 = 0x12;
+ /// Unordered (signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_UNORD_S: i32 = 0x13;
+ /// Not-equal (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NEQ_US: i32 = 0x14;
+ /// Not-less-than (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NLT_UQ: i32 = 0x15;
+ /// Not-less-than-or-equal (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NLE_UQ: i32 = 0x16;
+ /// Ordered (signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_ORD_S: i32 = 0x17;
+ /// Equal (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_EQ_US: i32 = 0x18;
+ /// Not-greater-than-or-equal (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NGE_UQ: i32 = 0x19;
+ /// Not-greater-than (unordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NGT_UQ: i32 = 0x1a;
+ /// False (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_FALSE_OS: i32 = 0x1b;
+ /// Not-equal (ordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_NEQ_OS: i32 = 0x1c;
+ /// Greater-than-or-equal (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_GE_OQ: i32 = 0x1d;
+ /// Greater-than (ordered, non-signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_GT_OQ: i32 = 0x1e;
+ /// True (unordered, signaling)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _CMP_TRUE_US: i32 = 0x1f;
+ 
+ /// Compares packed double-precision (64-bit) floating-point
+ /// elements in `a` and `b` based on the comparison operand
+ /// specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_pd)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ #[cfg_attr(test, assert_instr(vcmpeqpd, imm8 = 0))] // TODO Validate vcmppd
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmp_pd(a: __m128d, b: __m128d, imm8: i32) -> __m128d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vcmppd(a, b, $imm8)
+         };
+     }
+     constify_imm6!(imm8, call)
+ }
+ 
+ /// Compares packed double-precision (64-bit) floating-point
+ /// elements in `a` and `b` based on the comparison operand
+ /// specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcmpeqpd, imm8 = 0))] // TODO Validate vcmppd
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmp_pd(a: __m256d, b: __m256d, imm8: i32) -> __m256d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vcmppd256(a, b, $imm8)
+         };
+     }
+     constify_imm6!(imm8, call)
+ }
+ 
+ /// Compares packed single-precision (32-bit) floating-point
+ /// elements in `a` and `b` based on the comparison operand
+ /// specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ps)
+ #[inline]
+ #[target_feature(enable = "avx,sse")]
+ #[cfg_attr(test, assert_instr(vcmpeqps, imm8 = 0))] // TODO Validate vcmpps
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmp_ps(a: __m128, b: __m128, imm8: i32) -> __m128 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vcmpps(a, b, $imm8)
+         };
+     }
+     constify_imm6!(imm8, call)
+ }
+ 
+ /// Compares packed single-precision (32-bit) floating-point
+ /// elements in `a` and `b` based on the comparison operand
+ /// specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcmpeqps, imm8 = 0))] // TODO Validate vcmpps
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmp_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vcmpps256(a, b, $imm8)
+         };
+     }
+     constify_imm6!(imm8, call)
+ }
+ 
+ /// Compares the lower double-precision (64-bit) floating-point element in
+ /// `a` and `b` based on the comparison operand specified by `imm8`,
+ /// store the result in the lower element of returned vector,
+ /// and copies the upper element from `a` to the upper element of returned
+ /// vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_sd)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ #[cfg_attr(test, assert_instr(vcmpeqsd, imm8 = 0))] // TODO Validate vcmpsd
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmp_sd(a: __m128d, b: __m128d, imm8: i32) -> __m128d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vcmpsd(a, b, $imm8)
+         };
+     }
+     constify_imm6!(imm8, call)
+ }
+ 
+ /// Compares the lower single-precision (32-bit) floating-point element in
+ /// `a` and `b` based on the comparison operand specified by `imm8`,
+ /// store the result in the lower element of returned vector,
+ /// and copies the upper 3 packed elements from `a` to the upper elements of
+ /// returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ss)
+ #[inline]
+ #[target_feature(enable = "avx,sse")]
+ #[cfg_attr(test, assert_instr(vcmpeqss, imm8 = 0))] // TODO Validate vcmpss
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmp_ss(a: __m128, b: __m128, imm8: i32) -> __m128 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vcmpss(a, b, $imm8)
+         };
+     }
+     constify_imm6!(imm8, call)
+ }
+ 
+ /// Converts packed 32-bit integers in `a` to packed double-precision (64-bit)
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi32_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvtdq2pd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi32_pd(a: __m128i) -> __m256d {
+     simd_cast(a.as_i32x4())
+ }
+ 
+ /// Converts packed 32-bit integers in `a` to packed single-precision (32-bit)
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi32_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvtdq2ps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi32_ps(a: __m256i) -> __m256 {
+     vcvtdq2ps(a.as_i32x8())
+ }
+ 
+ /// Converts packed double-precision (64-bit) floating-point elements in `a`
+ /// to packed single-precision (32-bit) floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtpd_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvtpd2ps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtpd_ps(a: __m256d) -> __m128 {
+     vcvtpd2ps(a)
+ }
+ 
+ /// Converts packed single-precision (32-bit) floating-point elements in `a`
+ /// to packed 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtps_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtps_epi32(a: __m256) -> __m256i {
+     transmute(vcvtps2dq(a))
+ }
+ 
+ /// Converts packed single-precision (32-bit) floating-point elements in `a`
+ /// to packed double-precision (64-bit) floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtps_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtps_pd(a: __m128) -> __m256d {
+     simd_cast(a)
+ }
+ 
+ /// Converts packed double-precision (64-bit) floating-point elements in `a`
+ /// to packed 32-bit integers with truncation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttpd_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvttpd_epi32(a: __m256d) -> __m128i {
+     transmute(vcvttpd2dq(a))
+ }
+ 
+ /// Converts packed double-precision (64-bit) floating-point elements in `a`
+ /// to packed 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtpd_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvtpd2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtpd_epi32(a: __m256d) -> __m128i {
+     transmute(vcvtpd2dq(a))
+ }
+ 
+ /// Converts packed single-precision (32-bit) floating-point elements in `a`
+ /// to packed 32-bit integers with truncation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvttps_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvttps_epi32(a: __m256) -> __m256i {
+     transmute(vcvttps2dq(a))
+ }
+ 
+ /// Extracts 128 bits (composed of 4 packed single-precision (32-bit)
+ /// floating-point elements) from `a`, selected with `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extractf128_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vextractf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extractf128_ps(a: __m256, imm8: i32) -> __m128 {
+     match imm8 & 1 {
+         0 => simd_shuffle4(a, _mm256_undefined_ps(), [0, 1, 2, 3]),
+         _ => simd_shuffle4(a, _mm256_undefined_ps(), [4, 5, 6, 7]),
+     }
+ }
+ 
+ /// Extracts 128 bits (composed of 2 packed double-precision (64-bit)
+ /// floating-point elements) from `a`, selected with `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extractf128_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vextractf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extractf128_pd(a: __m256d, imm8: i32) -> __m128d {
+     match imm8 & 1 {
+         0 => simd_shuffle2(a, _mm256_undefined_pd(), [0, 1]),
+         _ => simd_shuffle2(a, _mm256_undefined_pd(), [2, 3]),
+     }
+ }
+ 
+ /// Extracts 128 bits (composed of integer data) from `a`, selected with `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extractf128_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vextractf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extractf128_si256(a: __m256i, imm8: i32) -> __m128i {
+     let b = _mm256_undefined_si256().as_i64x4();
+     let dst: i64x2 = match imm8 & 1 {
+         0 => simd_shuffle2(a.as_i64x4(), b, [0, 1]),
+         _ => simd_shuffle2(a.as_i64x4(), b, [2, 3]),
+     };
+     transmute(dst)
+ }
+ 
+ /// Zeroes the contents of all XMM or YMM registers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zeroall)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vzeroall))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_zeroall() {
+     vzeroall()
+ }
+ 
+ /// Zeroes the upper 128 bits of all YMM registers;
+ /// the lower 128-bits of the registers are unmodified.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zeroupper)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vzeroupper))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_zeroupper() {
+     vzeroupper()
+ }
+ 
+ /// Shuffles single-precision (32-bit) floating-point elements in `a`
+ /// within 128-bit lanes using the control in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutevar_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpermilps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permutevar_ps(a: __m256, b: __m256i) -> __m256 {
+     vpermilps256(a, b.as_i32x8())
+ }
+ 
+ /// Shuffles single-precision (32-bit) floating-point elements in `a`
+ /// using the control in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutevar_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpermilps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_permutevar_ps(a: __m128, b: __m128i) -> __m128 {
+     vpermilps(a, b.as_i32x4())
+ }
+ 
+ /// Shuffles single-precision (32-bit) floating-point elements in `a`
+ /// within 128-bit lanes using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute_ps(a: __m256, imm8: i32) -> __m256 {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle8(
+                 a,
+                 _mm256_undefined_ps(),
+                 [$a, $b, $c, $d, $a + 4, $b + 4, $c + 4, $d + 4],
+             )
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle4!($a, $b, $c, 0),
+                 0b01 => shuffle4!($a, $b, $c, 1),
+                 0b10 => shuffle4!($a, $b, $c, 2),
+                 _ => shuffle4!($a, $b, $c, 3),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle3!($a, $b, 0),
+                 0b01 => shuffle3!($a, $b, 1),
+                 0b10 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle2!($a, 0),
+                 0b01 => shuffle2!($a, 1),
+                 0b10 => shuffle2!($a, 2),
+                 _ => shuffle2!($a, 3),
+             }
+         };
+     }
+     match imm8 & 0b11 {
+         0b00 => shuffle1!(0),
+         0b01 => shuffle1!(1),
+         0b10 => shuffle1!(2),
+         _ => shuffle1!(3),
+     }
+ }
+ 
+ /// Shuffles single-precision (32-bit) floating-point elements in `a`
+ /// using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permute_ps)
+ #[inline]
+ #[target_feature(enable = "avx,sse")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_permute_ps(a: __m128, imm8: i32) -> __m128 {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle4(a, _mm_undefined_ps(), [$a, $b, $c, $d])
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle4!($a, $b, $c, 0),
+                 0b01 => shuffle4!($a, $b, $c, 1),
+                 0b10 => shuffle4!($a, $b, $c, 2),
+                 _ => shuffle4!($a, $b, $c, 3),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle3!($a, $b, 0),
+                 0b01 => shuffle3!($a, $b, 1),
+                 0b10 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle2!($a, 0),
+                 0b01 => shuffle2!($a, 1),
+                 0b10 => shuffle2!($a, 2),
+                 _ => shuffle2!($a, 3),
+             }
+         };
+     }
+     match imm8 & 0b11 {
+         0b00 => shuffle1!(0),
+         0b01 => shuffle1!(1),
+         0b10 => shuffle1!(2),
+         _ => shuffle1!(3),
+     }
+ }
+ 
+ /// Shuffles double-precision (64-bit) floating-point elements in `a`
+ /// within 256-bit lanes using the control in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutevar_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpermilpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permutevar_pd(a: __m256d, b: __m256i) -> __m256d {
+     vpermilpd256(a, b.as_i64x4())
+ }
+ 
+ /// Shuffles double-precision (64-bit) floating-point elements in `a`
+ /// using the control in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutevar_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpermilpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_permutevar_pd(a: __m128d, b: __m128i) -> __m128d {
+     vpermilpd(a, b.as_i64x2())
+ }
+ 
+ /// Shuffles double-precision (64-bit) floating-point elements in `a`
+ /// within 128-bit lanes using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpermilpd, imm8 = 0x1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute_pd(a: __m256d, imm8: i32) -> __m256d {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle4(a, _mm256_undefined_pd(), [$a, $b, $c, $d]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 3) & 0x1 {
+                 0 => shuffle4!($a, $b, $c, 2),
+                 _ => shuffle4!($a, $b, $c, 3),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0x1 {
+                 0 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 1) & 0x1 {
+                 0 => shuffle2!($a, 0),
+                 _ => shuffle2!($a, 1),
+             }
+         };
+     }
+     match imm8 & 0x1 {
+         0 => shuffle1!(0),
+         _ => shuffle1!(1),
+     }
+ }
+ 
+ /// Shuffles double-precision (64-bit) floating-point elements in `a`
+ /// using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permute_pd)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ #[cfg_attr(test, assert_instr(vpermilpd, imm8 = 0x1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_permute_pd(a: __m128d, imm8: i32) -> __m128d {
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             simd_shuffle2(a, _mm_undefined_pd(), [$a, $b]);
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 1) & 0x1 {
+                 0 => shuffle2!($a, 0),
+                 _ => shuffle2!($a, 1),
+             }
+         };
+     }
+     match imm8 & 0x1 {
+         0 => shuffle1!(0),
+         _ => shuffle1!(1),
+     }
+ }
+ 
+ /// Shuffles 256 bits (composed of 8 packed single-precision (32-bit)
+ /// floating-point elements) selected by `imm8` from `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute2f128_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vperm2f128, imm8 = 0x5))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute2f128_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vperm2f128ps256(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shuffles 256 bits (composed of 4 packed double-precision (64-bit)
+ /// floating-point elements) selected by `imm8` from `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute2f128_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vperm2f128, imm8 = 0x31))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute2f128_pd(a: __m256d, b: __m256d, imm8: i32) -> __m256d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vperm2f128pd256(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shuffles 128-bits (composed of integer data) selected by `imm8`
+ /// from `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute2f128_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vperm2f128, imm8 = 0x31))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute2f128_si256(a: __m256i, b: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_i32x8();
+     let b = b.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vperm2f128si256(a, b, $imm8)
+         };
+     }
+     let r = constify_imm8!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Broadcasts a single-precision (32-bit) floating-point element from memory
+ /// to all elements of the returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcast_ss)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::trivially_copy_pass_by_ref)]
+ pub unsafe fn _mm256_broadcast_ss(f: &f32) -> __m256 {
+     _mm256_set1_ps(*f)
+ }
+ 
+ /// Broadcasts a single-precision (32-bit) floating-point element from memory
+ /// to all elements of the returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcast_ss)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::trivially_copy_pass_by_ref)]
+ pub unsafe fn _mm_broadcast_ss(f: &f32) -> __m128 {
+     _mm_set1_ps(*f)
+ }
+ 
+ /// Broadcasts a double-precision (64-bit) floating-point element from memory
+ /// to all elements of the returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcast_sd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vbroadcastsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::trivially_copy_pass_by_ref)]
+ pub unsafe fn _mm256_broadcast_sd(f: &f64) -> __m256d {
+     _mm256_set1_pd(*f)
+ }
+ 
+ /// Broadcasts 128 bits from memory (composed of 4 packed single-precision
+ /// (32-bit) floating-point elements) to all elements of the returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcast_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vbroadcastf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcast_ps(a: &__m128) -> __m256 {
+     vbroadcastf128ps256(a)
+ }
+ 
+ /// Broadcasts 128 bits from memory (composed of 2 packed double-precision
+ /// (64-bit) floating-point elements) to all elements of the returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcast_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vbroadcastf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcast_pd(a: &__m128d) -> __m256d {
+     vbroadcastf128pd256(a)
+ }
+ 
+ /// Copies `a` to result, then inserts 128 bits (composed of 4 packed
+ /// single-precision (32-bit) floating-point elements) from `b` into result
+ /// at the location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insertf128_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vinsertf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insertf128_ps(a: __m256, b: __m128, imm8: i32) -> __m256 {
+     let b = _mm256_castps128_ps256(b);
+     match imm8 & 1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     }
+ }
+ 
+ /// Copies `a` to result, then inserts 128 bits (composed of 2 packed
+ /// double-precision (64-bit) floating-point elements) from `b` into result
+ /// at the location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insertf128_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vinsertf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insertf128_pd(a: __m256d, b: __m128d, imm8: i32) -> __m256d {
+     match imm8 & 1 {
+         0 => simd_shuffle4(a, _mm256_castpd128_pd256(b), [4, 5, 2, 3]),
+         _ => simd_shuffle4(a, _mm256_castpd128_pd256(b), [0, 1, 4, 5]),
+     }
+ }
+ 
+ /// Copies `a` to result, then inserts 128 bits from `b` into result
+ /// at the location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insertf128_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vinsertf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insertf128_si256(a: __m256i, b: __m128i, imm8: i32) -> __m256i {
+     let b = _mm256_castsi128_si256(b).as_i64x4();
+     let dst: i64x4 = match imm8 & 1 {
+         0 => simd_shuffle4(a.as_i64x4(), b, [4, 5, 2, 3]),
+         _ => simd_shuffle4(a.as_i64x4(), b, [0, 1, 4, 5]),
+     };
+     transmute(dst)
+ }
+ 
+ /// Copies `a` to result, and inserts the 8-bit integer `i` into result
+ /// at the location specified by `index`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insert_epi8)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insert_epi8(a: __m256i, i: i8, index: i32) -> __m256i {
+     let a = a.as_i8x32();
+     macro_rules! call {
+         ($index:expr) => {
+             simd_insert(a, $index, i)
+         };
+     }
+     transmute(constify_imm5!(index, call))
+ }
+ 
+ /// Copies `a` to result, and inserts the 16-bit integer `i` into result
+ /// at the location specified by `index`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insert_epi16)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insert_epi16(a: __m256i, i: i16, index: i32) -> __m256i {
+     let a = a.as_i16x16();
+     macro_rules! call {
+         ($index:expr) => {
+             simd_insert(a, $index, i)
+         };
+     }
+     transmute(constify_imm4!((index & 15), call))
+ }
+ 
+ /// Copies `a` to result, and inserts the 32-bit integer `i` into result
+ /// at the location specified by `index`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insert_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insert_epi32(a: __m256i, i: i32, index: i32) -> __m256i {
+     let a = a.as_i32x8();
+     macro_rules! call {
+         ($index:expr) => {
+             simd_insert(a, $index, i)
+         };
+     }
+     transmute(constify_imm8!((index & 7), call))
+ }
+ 
+ /// Loads 256-bits (composed of 4 packed double-precision (64-bit)
+ /// floating-point elements) from memory into result.
+ /// `mem_addr` must be aligned on a 32-byte boundary or a
+ /// general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_load_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovapd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
+     *(mem_addr as *const __m256d)
+ }
+ 
+ /// Stores 256-bits (composed of 4 packed double-precision (64-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` must be aligned on a 32-byte boundary or a
+ /// general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_store_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovapd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
+     *(mem_addr as *mut __m256d) = a;
+ }
+ 
+ /// Loads 256-bits (composed of 8 packed single-precision (32-bit)
+ /// floating-point elements) from memory into result.
+ /// `mem_addr` must be aligned on a 32-byte boundary or a
+ /// general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_load_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
+     *(mem_addr as *const __m256)
+ }
+ 
+ /// Stores 256-bits (composed of 8 packed single-precision (32-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` must be aligned on a 32-byte boundary or a
+ /// general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_store_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm256_store_ps(mem_addr: *mut f32, a: __m256) {
+     *(mem_addr as *mut __m256) = a;
+ }
+ 
+ /// Loads 256-bits (composed of 4 packed double-precision (64-bit)
+ /// floating-point elements) from memory into result.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovups))] // FIXME vmovupd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_loadu_pd(mem_addr: *const f64) -> __m256d {
+     let mut dst = _mm256_undefined_pd();
+     ptr::copy_nonoverlapping(
+         mem_addr as *const u8,
+         &mut dst as *mut __m256d as *mut u8,
+         mem::size_of::<__m256d>(),
+     );
+     dst
+ }
+ 
+ /// Stores 256-bits (composed of 4 packed double-precision (64-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovups))] // FIXME vmovupd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_storeu_pd(mem_addr: *mut f64, a: __m256d) {
+     storeupd256(mem_addr, a);
+ }
+ 
+ /// Loads 256-bits (composed of 8 packed single-precision (32-bit)
+ /// floating-point elements) from memory into result.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_loadu_ps(mem_addr: *const f32) -> __m256 {
+     let mut dst = _mm256_undefined_ps();
+     ptr::copy_nonoverlapping(
+         mem_addr as *const u8,
+         &mut dst as *mut __m256 as *mut u8,
+         mem::size_of::<__m256>(),
+     );
+     dst
+ }
+ 
+ /// Stores 256-bits (composed of 8 packed single-precision (32-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_storeu_ps(mem_addr: *mut f32, a: __m256) {
+     storeups256(mem_addr, a);
+ }
+ 
+ /// Loads 256-bits of integer data from memory into result.
+ /// `mem_addr` must be aligned on a 32-byte boundary or a
+ /// general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_load_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovdqa expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
+     *mem_addr
+ }
+ 
+ /// Stores 256-bits of integer data from `a` into memory.
+ /// `mem_addr` must be aligned on a 32-byte boundary or a
+ /// general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_store_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovdqa expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_store_si256(mem_addr: *mut __m256i, a: __m256i) {
+     *mem_addr = a;
+ }
+ 
+ /// Loads 256-bits of integer data from memory into result.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovups))] // FIXME vmovdqu expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_loadu_si256(mem_addr: *const __m256i) -> __m256i {
+     let mut dst = _mm256_undefined_si256();
+     ptr::copy_nonoverlapping(
+         mem_addr as *const u8,
+         &mut dst as *mut __m256i as *mut u8,
+         mem::size_of::<__m256i>(),
+     );
+     dst
+ }
+ 
+ /// Stores 256-bits of integer data from `a` into memory.
+ /// 	`mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovups))] // FIXME vmovdqu expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_storeu_si256(mem_addr: *mut __m256i, a: __m256i) {
+     storeudq256(mem_addr as *mut i8, a.as_i8x32());
+ }
+ 
+ /// Loads packed double-precision (64-bit) floating-point elements from memory
+ /// into result using `mask` (elements are zeroed out when the high bit of the
+ /// corresponding element is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskload_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskload_pd(mem_addr: *const f64, mask: __m256i) -> __m256d {
+     maskloadpd256(mem_addr as *const i8, mask.as_i64x4())
+ }
+ 
+ /// Stores packed double-precision (64-bit) floating-point elements from `a`
+ /// into memory using `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskstore_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskstore_pd(mem_addr: *mut f64, mask: __m256i, a: __m256d) {
+     maskstorepd256(mem_addr as *mut i8, mask.as_i64x4(), a);
+ }
+ 
+ /// Loads packed double-precision (64-bit) floating-point elements from memory
+ /// into result using `mask` (elements are zeroed out when the high bit of the
+ /// corresponding element is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskload_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskload_pd(mem_addr: *const f64, mask: __m128i) -> __m128d {
+     maskloadpd(mem_addr as *const i8, mask.as_i64x2())
+ }
+ 
+ /// Stores packed double-precision (64-bit) floating-point elements from `a`
+ /// into memory using `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskstore_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskstore_pd(mem_addr: *mut f64, mask: __m128i, a: __m128d) {
+     maskstorepd(mem_addr as *mut i8, mask.as_i64x2(), a);
+ }
+ 
+ /// Loads packed single-precision (32-bit) floating-point elements from memory
+ /// into result using `mask` (elements are zeroed out when the high bit of the
+ /// corresponding element is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskload_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskload_ps(mem_addr: *const f32, mask: __m256i) -> __m256 {
+     maskloadps256(mem_addr as *const i8, mask.as_i32x8())
+ }
+ 
+ /// Stores packed single-precision (32-bit) floating-point elements from `a`
+ /// into memory using `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskstore_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskstore_ps(mem_addr: *mut f32, mask: __m256i, a: __m256) {
+     maskstoreps256(mem_addr as *mut i8, mask.as_i32x8(), a);
+ }
+ 
+ /// Loads packed single-precision (32-bit) floating-point elements from memory
+ /// into result using `mask` (elements are zeroed out when the high bit of the
+ /// corresponding element is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskload_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskload_ps(mem_addr: *const f32, mask: __m128i) -> __m128 {
+     maskloadps(mem_addr as *const i8, mask.as_i32x4())
+ }
+ 
+ /// Stores packed single-precision (32-bit) floating-point elements from `a`
+ /// into memory using `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskstore_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmaskmovps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskstore_ps(mem_addr: *mut f32, mask: __m128i, a: __m128) {
+     maskstoreps(mem_addr as *mut i8, mask.as_i32x4(), a);
+ }
+ 
+ /// Duplicate odd-indexed single-precision (32-bit) floating-point elements
+ /// from `a`, and returns the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_movehdup_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovshdup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_movehdup_ps(a: __m256) -> __m256 {
+     simd_shuffle8(a, a, [1, 1, 3, 3, 5, 5, 7, 7])
+ }
+ 
+ /// Duplicate even-indexed single-precision (32-bit) floating-point elements
+ /// from `a`, and returns the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_moveldup_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovsldup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_moveldup_ps(a: __m256) -> __m256 {
+     simd_shuffle8(a, a, [0, 0, 2, 2, 4, 4, 6, 6])
+ }
+ 
+ /// Duplicate even-indexed double-precision (64-bit) floating-point elements
+ /// from `a`, and returns the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_movedup_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovddup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_movedup_pd(a: __m256d) -> __m256d {
+     simd_shuffle4(a, a, [0, 0, 2, 2])
+ }
+ 
+ /// Loads 256-bits of integer data from unaligned memory into result.
+ /// This intrinsic may perform better than `_mm256_loadu_si256` when the
+ /// data crosses a cache line boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_lddqu_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vlddqu))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_lddqu_si256(mem_addr: *const __m256i) -> __m256i {
+     transmute(vlddqu(mem_addr as *const i8))
+ }
+ 
+ /// Moves integer data from a 256-bit integer vector to a 32-byte
+ /// aligned memory location. To minimize caching, the data is flagged as
+ /// non-temporal (unlikely to be used again soon)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_stream_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovntps))] // FIXME vmovntdq
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_stream_si256(mem_addr: *mut __m256i, a: __m256i) {
+     intrinsics::nontemporal_store(mem_addr, a);
+ }
+ 
+ /// Moves double-precision values from a 256-bit vector of `[4 x double]`
+ /// to a 32-byte aligned memory location. To minimize caching, the data is
+ /// flagged as non-temporal (unlikely to be used again soon).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_stream_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovntps))] // FIXME vmovntpd
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm256_stream_pd(mem_addr: *mut f64, a: __m256d) {
+     intrinsics::nontemporal_store(mem_addr as *mut __m256d, a);
+ }
+ 
+ /// Moves single-precision floating point values from a 256-bit vector
+ /// of `[8 x float]` to a 32-byte aligned memory location. To minimize
+ /// caching, the data is flagged as non-temporal (unlikely to be used again
+ /// soon).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_stream_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovntps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm256_stream_ps(mem_addr: *mut f32, a: __m256) {
+     intrinsics::nontemporal_store(mem_addr as *mut __m256, a);
+ }
+ 
+ /// Computes the approximate reciprocal of packed single-precision (32-bit)
+ /// floating-point elements in `a`, and returns the results. The maximum
+ /// relative error for this approximation is less than 1.5*2^-12.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rcp_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vrcpps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_rcp_ps(a: __m256) -> __m256 {
+     vrcpps(a)
+ }
+ 
+ /// Computes the approximate reciprocal square root of packed single-precision
+ /// (32-bit) floating-point elements in `a`, and returns the results.
+ /// The maximum relative error for this approximation is less than 1.5*2^-12.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rsqrt_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vrsqrtps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_rsqrt_ps(a: __m256) -> __m256 {
+     vrsqrtps(a)
+ }
+ 
+ /// Unpacks and interleave double-precision (64-bit) floating-point elements
+ /// from the high half of each 128-bit lane in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpackhi_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vunpckhpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpackhi_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_shuffle4(a, b, [1, 5, 3, 7])
+ }
+ 
+ /// Unpacks and interleave single-precision (32-bit) floating-point elements
+ /// from the high half of each 128-bit lane in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpackhi_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vunpckhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpackhi_ps(a: __m256, b: __m256) -> __m256 {
+     simd_shuffle8(a, b, [2, 10, 3, 11, 6, 14, 7, 15])
+ }
+ 
+ /// Unpacks and interleave double-precision (64-bit) floating-point elements
+ /// from the low half of each 128-bit lane in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpacklo_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vunpcklpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpacklo_pd(a: __m256d, b: __m256d) -> __m256d {
+     simd_shuffle4(a, b, [0, 4, 2, 6])
+ }
+ 
+ /// Unpacks and interleave single-precision (32-bit) floating-point elements
+ /// from the low half of each 128-bit lane in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpacklo_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vunpcklps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpacklo_ps(a: __m256, b: __m256) -> __m256 {
+     simd_shuffle8(a, b, [0, 8, 1, 9, 4, 12, 5, 13])
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing integer data) in `a` and
+ /// `b`, and set `ZF` to 1 if the result is zero, otherwise set `ZF` to 0.
+ /// Computes the bitwise NOT of `a` and then AND with `b`, and set `CF` to 1 if
+ /// the result is zero, otherwise set `CF` to 0. Return the `ZF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testz_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testz_si256(a: __m256i, b: __m256i) -> i32 {
+     ptestz256(a.as_i64x4(), b.as_i64x4())
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing integer data) in `a` and
+ /// `b`, and set `ZF` to 1 if the result is zero, otherwise set `ZF` to 0.
+ /// Computes the bitwise NOT of `a` and then AND with `b`, and set `CF` to 1 if
+ /// the result is zero, otherwise set `CF` to 0. Return the `CF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testc_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testc_si256(a: __m256i, b: __m256i) -> i32 {
+     ptestc256(a.as_i64x4(), b.as_i64x4())
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing integer data) in `a` and
+ /// `b`, and set `ZF` to 1 if the result is zero, otherwise set `ZF` to 0.
+ /// Computes the bitwise NOT of `a` and then AND with `b`, and set `CF` to 1 if
+ /// the result is zero, otherwise set `CF` to 0. Return 1 if both the `ZF` and
+ /// `CF` values are zero, otherwise return 0.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testnzc_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testnzc_si256(a: __m256i, b: __m256i) -> i32 {
+     ptestnzc256(a.as_i64x4(), b.as_i64x4())
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing double-precision (64-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 256-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 64-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 64-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `ZF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testz_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testz_pd(a: __m256d, b: __m256d) -> i32 {
+     vtestzpd256(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing double-precision (64-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 256-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 64-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 64-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `CF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testc_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testc_pd(a: __m256d, b: __m256d) -> i32 {
+     vtestcpd256(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing double-precision (64-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 256-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 64-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 64-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return 1 if both the `ZF` and `CF` values
+ /// are zero, otherwise return 0.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testnzc_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testnzc_pd(a: __m256d, b: __m256d) -> i32 {
+     vtestnzcpd256(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing double-precision (64-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 128-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 64-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 64-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `ZF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testz_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testz_pd(a: __m128d, b: __m128d) -> i32 {
+     vtestzpd(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing double-precision (64-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 128-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 64-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 64-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `CF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testc_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testc_pd(a: __m128d, b: __m128d) -> i32 {
+     vtestcpd(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing double-precision (64-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 128-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 64-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 64-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return 1 if both the `ZF` and `CF` values
+ /// are zero, otherwise return 0.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testnzc_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testnzc_pd(a: __m128d, b: __m128d) -> i32 {
+     vtestnzcpd(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing single-precision (32-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 256-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 32-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 32-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `ZF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testz_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testz_ps(a: __m256, b: __m256) -> i32 {
+     vtestzps256(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing single-precision (32-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 256-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 32-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 32-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `CF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testc_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testc_ps(a: __m256, b: __m256) -> i32 {
+     vtestcps256(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing single-precision (32-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 256-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 32-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 32-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return 1 if both the `ZF` and `CF` values
+ /// are zero, otherwise return 0.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_testnzc_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_testnzc_ps(a: __m256, b: __m256) -> i32 {
+     vtestnzcps256(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing single-precision (32-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 128-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 32-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 32-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `ZF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testz_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testz_ps(a: __m128, b: __m128) -> i32 {
+     vtestzps(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing single-precision (32-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 128-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 32-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 32-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return the `CF` value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testc_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testc_ps(a: __m128, b: __m128) -> i32 {
+     vtestcps(a, b)
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing single-precision (32-bit)
+ /// floating-point elements) in `a` and `b`, producing an intermediate 128-bit
+ /// value, and set `ZF` to 1 if the sign bit of each 32-bit element in the
+ /// intermediate value is zero, otherwise set `ZF` to 0. Compute the bitwise
+ /// NOT of `a` and then AND with `b`, producing an intermediate value, and set
+ /// `CF` to 1 if the sign bit of each 32-bit element in the intermediate value
+ /// is zero, otherwise set `CF` to 0. Return 1 if both the `ZF` and `CF` values
+ /// are zero, otherwise return 0.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testnzc_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vtestps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testnzc_ps(a: __m128, b: __m128) -> i32 {
+     vtestnzcps(a, b)
+ }
+ 
+ /// Sets each bit of the returned mask based on the most significant bit of the
+ /// corresponding packed double-precision (64-bit) floating-point element in
+ /// `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_movemask_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovmskpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_movemask_pd(a: __m256d) -> i32 {
+     movmskpd256(a)
+ }
+ 
+ /// Sets each bit of the returned mask based on the most significant bit of the
+ /// corresponding packed single-precision (32-bit) floating-point element in
+ /// `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_movemask_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vmovmskps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_movemask_ps(a: __m256) -> i32 {
+     movmskps256(a)
+ }
+ 
+ /// Returns vector of type __m256d with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vxorps))] // FIXME vxorpd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setzero_pd() -> __m256d {
+     _mm256_set1_pd(0.0)
+ }
+ 
+ /// Returns vector of type __m256 with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vxorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setzero_ps() -> __m256 {
+     _mm256_set1_ps(0.0)
+ }
+ 
+ /// Returns vector of type __m256i with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vxor))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setzero_si256() -> __m256i {
+     _mm256_set1_epi8(0)
+ }
+ 
+ /// Sets packed double-precision (64-bit) floating-point elements in returned
+ /// vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
+     _mm256_setr_pd(d, c, b, a)
+ }
+ 
+ /// Sets packed single-precision (32-bit) floating-point elements in returned
+ /// vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_ps(
+     a: f32,
+     b: f32,
+     c: f32,
+     d: f32,
+     e: f32,
+     f: f32,
+     g: f32,
+     h: f32,
+ ) -> __m256 {
+     _mm256_setr_ps(h, g, f, e, d, c, b, a)
+ }
+ 
+ /// Sets packed 8-bit integers in returned vector with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi8)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_epi8(
+     e00: i8,
+     e01: i8,
+     e02: i8,
+     e03: i8,
+     e04: i8,
+     e05: i8,
+     e06: i8,
+     e07: i8,
+     e08: i8,
+     e09: i8,
+     e10: i8,
+     e11: i8,
+     e12: i8,
+     e13: i8,
+     e14: i8,
+     e15: i8,
+     e16: i8,
+     e17: i8,
+     e18: i8,
+     e19: i8,
+     e20: i8,
+     e21: i8,
+     e22: i8,
+     e23: i8,
+     e24: i8,
+     e25: i8,
+     e26: i8,
+     e27: i8,
+     e28: i8,
+     e29: i8,
+     e30: i8,
+     e31: i8,
+ ) -> __m256i {
+     #[rustfmt::skip]
+     _mm256_setr_epi8(
+         e31, e30, e29, e28, e27, e26, e25, e24,
+         e23, e22, e21, e20, e19, e18, e17, e16,
+         e15, e14, e13, e12, e11, e10, e09, e08,
+         e07, e06, e05, e04, e03, e02, e01, e00,
+     )
+ }
+ 
+ /// Sets packed 16-bit integers in returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi16)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_epi16(
+     e00: i16,
+     e01: i16,
+     e02: i16,
+     e03: i16,
+     e04: i16,
+     e05: i16,
+     e06: i16,
+     e07: i16,
+     e08: i16,
+     e09: i16,
+     e10: i16,
+     e11: i16,
+     e12: i16,
+     e13: i16,
+     e14: i16,
+     e15: i16,
+ ) -> __m256i {
+     #[rustfmt::skip]
+     _mm256_setr_epi16(
+         e15, e14, e13, e12,
+         e11, e10, e09, e08,
+         e07, e06, e05, e04,
+         e03, e02, e01, e00,
+     )
+ }
+ 
+ /// Sets packed 32-bit integers in returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_epi32(
+     e0: i32,
+     e1: i32,
+     e2: i32,
+     e3: i32,
+     e4: i32,
+     e5: i32,
+     e6: i32,
+     e7: i32,
+ ) -> __m256i {
+     _mm256_setr_epi32(e7, e6, e5, e4, e3, e2, e1, e0)
+ }
+ 
+ /// Sets packed 64-bit integers in returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi64x)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
+     _mm256_setr_epi64x(d, c, b, a)
+ }
+ 
+ /// Sets packed double-precision (64-bit) floating-point elements in returned
+ /// vector with the supplied values in reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {
+     __m256d(a, b, c, d)
+ }
+ 
+ /// Sets packed single-precision (32-bit) floating-point elements in returned
+ /// vector with the supplied values in reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_ps(
+     a: f32,
+     b: f32,
+     c: f32,
+     d: f32,
+     e: f32,
+     f: f32,
+     g: f32,
+     h: f32,
+ ) -> __m256 {
+     __m256(a, b, c, d, e, f, g, h)
+ }
+ 
+ /// Sets packed 8-bit integers in returned vector with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi8)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_epi8(
+     e00: i8,
+     e01: i8,
+     e02: i8,
+     e03: i8,
+     e04: i8,
+     e05: i8,
+     e06: i8,
+     e07: i8,
+     e08: i8,
+     e09: i8,
+     e10: i8,
+     e11: i8,
+     e12: i8,
+     e13: i8,
+     e14: i8,
+     e15: i8,
+     e16: i8,
+     e17: i8,
+     e18: i8,
+     e19: i8,
+     e20: i8,
+     e21: i8,
+     e22: i8,
+     e23: i8,
+     e24: i8,
+     e25: i8,
+     e26: i8,
+     e27: i8,
+     e28: i8,
+     e29: i8,
+     e30: i8,
+     e31: i8,
+ ) -> __m256i {
+     #[rustfmt::skip]
+     transmute(i8x32::new(
+         e00, e01, e02, e03, e04, e05, e06, e07,
+         e08, e09, e10, e11, e12, e13, e14, e15,
+         e16, e17, e18, e19, e20, e21, e22, e23,
+         e24, e25, e26, e27, e28, e29, e30, e31,
+     ))
+ }
+ 
+ /// Sets packed 16-bit integers in returned vector with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi16)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_epi16(
+     e00: i16,
+     e01: i16,
+     e02: i16,
+     e03: i16,
+     e04: i16,
+     e05: i16,
+     e06: i16,
+     e07: i16,
+     e08: i16,
+     e09: i16,
+     e10: i16,
+     e11: i16,
+     e12: i16,
+     e13: i16,
+     e14: i16,
+     e15: i16,
+ ) -> __m256i {
+     #[rustfmt::skip]
+     transmute(i16x16::new(
+         e00, e01, e02, e03,
+         e04, e05, e06, e07,
+         e08, e09, e10, e11,
+         e12, e13, e14, e15,
+     ))
+ }
+ 
+ /// Sets packed 32-bit integers in returned vector with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_epi32(
+     e0: i32,
+     e1: i32,
+     e2: i32,
+     e3: i32,
+     e4: i32,
+     e5: i32,
+     e6: i32,
+     e7: i32,
+ ) -> __m256i {
+     transmute(i32x8::new(e0, e1, e2, e3, e4, e5, e6, e7))
+ }
+ 
+ /// Sets packed 64-bit integers in returned vector with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi64x)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
+     transmute(i64x4::new(a, b, c, d))
+ }
+ 
+ /// Broadcasts double-precision (64-bit) floating-point value `a` to all
+ /// elements of returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set1_pd(a: f64) -> __m256d {
+     _mm256_setr_pd(a, a, a, a)
+ }
+ 
+ /// Broadcasts single-precision (32-bit) floating-point value `a` to all
+ /// elements of returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set1_ps(a: f32) -> __m256 {
+     _mm256_setr_ps(a, a, a, a, a, a, a, a)
+ }
+ 
+ /// Broadcasts 8-bit integer `a` to all elements of returned vector.
+ /// This intrinsic may generate the `vpbroadcastb`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_epi8)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vpshufb))]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set1_epi8(a: i8) -> __m256i {
+     #[rustfmt::skip]
+     _mm256_setr_epi8(
+         a, a, a, a, a, a, a, a,
+         a, a, a, a, a, a, a, a,
+         a, a, a, a, a, a, a, a,
+         a, a, a, a, a, a, a, a,
+     )
+ }
+ 
+ /// Broadcasts 16-bit integer `a` to all all elements of returned vector.
+ /// This intrinsic may generate the `vpbroadcastw`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_epi16)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ //#[cfg_attr(test, assert_instr(vpshufb))]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set1_epi16(a: i16) -> __m256i {
+     _mm256_setr_epi16(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
+ }
+ 
+ /// Broadcasts 32-bit integer `a` to all elements of returned vector.
+ /// This intrinsic may generate the `vpbroadcastd`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_epi32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set1_epi32(a: i32) -> __m256i {
+     _mm256_setr_epi32(a, a, a, a, a, a, a, a)
+ }
+ 
+ /// Broadcasts 64-bit integer `a` to all elements of returned vector.
+ /// This intrinsic may generate the `vpbroadcastq`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_epi64x)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(vinsertf128))]
+ #[cfg_attr(all(test, target_arch = "x86"), assert_instr(vbroadcastsd))]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set1_epi64x(a: i64) -> __m256i {
+     _mm256_setr_epi64x(a, a, a, a)
+ }
+ 
+ /// Cast vector of type __m256d to type __m256.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castpd_ps(a: __m256d) -> __m256 {
+     transmute(a)
+ }
+ 
+ /// Cast vector of type __m256 to type __m256d.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castps_pd(a: __m256) -> __m256d {
+     transmute(a)
+ }
+ 
+ /// Casts vector of type __m256 to type __m256i.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castps_si256(a: __m256) -> __m256i {
+     transmute(a)
+ }
+ 
+ /// Casts vector of type __m256i to type __m256.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castsi256_ps(a: __m256i) -> __m256 {
+     transmute(a)
+ }
+ 
+ /// Casts vector of type __m256d to type __m256i.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castpd_si256(a: __m256d) -> __m256i {
+     transmute(a)
+ }
+ 
+ /// Casts vector of type __m256i to type __m256d.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castsi256_pd(a: __m256i) -> __m256d {
+     transmute(a)
+ }
+ 
+ /// Casts vector of type __m256 to type __m128.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps256_ps128)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castps256_ps128(a: __m256) -> __m128 {
+     simd_shuffle4(a, a, [0, 1, 2, 3])
+ }
+ 
+ /// Casts vector of type __m256d to type __m128d.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd256_pd128)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castpd256_pd128(a: __m256d) -> __m128d {
+     simd_shuffle2(a, a, [0, 1])
+ }
+ 
+ /// Casts vector of type __m256i to type __m128i.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_si128)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castsi256_si128(a: __m256i) -> __m128i {
+     let a = a.as_i64x4();
+     let dst: i64x2 = simd_shuffle2(a, a, [0, 1]);
+     transmute(dst)
+ }
+ 
+ /// Casts vector of type __m128 to type __m256;
+ /// the upper 128 bits of the result are undefined.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps128_ps256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castps128_ps256(a: __m128) -> __m256 {
+     // FIXME simd_shuffle8(a, a, [0, 1, 2, 3, -1, -1, -1, -1])
+     simd_shuffle8(a, a, [0, 1, 2, 3, 0, 0, 0, 0])
+ }
+ 
+ /// Casts vector of type __m128d to type __m256d;
+ /// the upper 128 bits of the result are undefined.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd128_pd256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castpd128_pd256(a: __m128d) -> __m256d {
+     // FIXME simd_shuffle4(a, a, [0, 1, -1, -1])
+     simd_shuffle4(a, a, [0, 1, 0, 0])
+ }
+ 
+ /// Casts vector of type __m128i to type __m256i;
+ /// the upper 128 bits of the result are undefined.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi128_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_castsi128_si256(a: __m128i) -> __m256i {
+     let a = a.as_i64x2();
+     // FIXME simd_shuffle4(a, a, [0, 1, -1, -1])
+     let dst: i64x4 = simd_shuffle4(a, a, [0, 1, 0, 0]);
+     transmute(dst)
+ }
+ 
+ /// Constructs a 256-bit floating-point vector of `[8 x float]` from a
+ /// 128-bit floating-point vector of `[4 x float]`. The lower 128 bits contain
+ /// the value of the source vector. The upper 128 bits are set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextps128_ps256)
+ #[inline]
+ #[target_feature(enable = "avx,sse")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_zextps128_ps256(a: __m128) -> __m256 {
+     simd_shuffle8(a, _mm_setzero_ps(), [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ 
+ /// Constructs a 256-bit integer vector from a 128-bit integer vector.
+ /// The lower 128 bits contain the value of the source vector. The upper
+ /// 128 bits are set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextsi128_si256)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_zextsi128_si256(a: __m128i) -> __m256i {
+     let b = _mm_setzero_si128().as_i64x2();
+     let dst: i64x4 = simd_shuffle4(a.as_i64x2(), b, [0, 1, 2, 3]);
+     transmute(dst)
+ }
+ 
+ /// Constructs a 256-bit floating-point vector of `[4 x double]` from a
+ /// 128-bit floating-point vector of `[2 x double]`. The lower 128 bits
+ /// contain the value of the source vector. The upper 128 bits are set
+ /// to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextpd128_pd256)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ // This intrinsic is only used for compilation and does not generate any
+ // instructions, thus it has zero latency.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_zextpd128_pd256(a: __m128d) -> __m256d {
+     simd_shuffle4(a, _mm_setzero_pd(), [0, 1, 2, 3])
+ }
+ 
+ /// Returns vector of type `__m256` with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ps)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_undefined_ps() -> __m256 {
+     _mm256_set1_ps(0.0)
+ }
+ 
+ /// Returns vector of type `__m256d` with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_pd)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_undefined_pd() -> __m256d {
+     _mm256_set1_pd(0.0)
+ }
+ 
+ /// Returns vector of type __m256i with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_si256)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_undefined_si256() -> __m256i {
+     // FIXME: this function should return MaybeUninit<__m256i>
+     mem::MaybeUninit::<__m256i>::uninit().assume_init()
+ }
+ 
+ /// Sets packed __m256 returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_m128)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_m128(hi: __m128, lo: __m128) -> __m256 {
+     simd_shuffle8(lo, hi, [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ 
+ /// Sets packed __m256d returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_m128d)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_m128d(hi: __m128d, lo: __m128d) -> __m256d {
+     let hi: __m128 = transmute(hi);
+     let lo: __m128 = transmute(lo);
+     transmute(_mm256_set_m128(hi, lo))
+ }
+ 
+ /// Sets packed __m256i returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_m128i)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_set_m128i(hi: __m128i, lo: __m128i) -> __m256i {
+     let hi: __m128 = transmute(hi);
+     let lo: __m128 = transmute(lo);
+     transmute(_mm256_set_m128(hi, lo))
+ }
+ 
+ /// Sets packed __m256 returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_m128)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_m128(lo: __m128, hi: __m128) -> __m256 {
+     _mm256_set_m128(hi, lo)
+ }
+ 
+ /// Sets packed __m256d returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_m128d)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_m128d(lo: __m128d, hi: __m128d) -> __m256d {
+     _mm256_set_m128d(hi, lo)
+ }
+ 
+ /// Sets packed __m256i returned vector with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_m128i)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ #[cfg_attr(test, assert_instr(vinsertf128))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_setr_m128i(lo: __m128i, hi: __m128i) -> __m256i {
+     _mm256_set_m128i(hi, lo)
+ }
+ 
+ /// Loads two 128-bit values (composed of 4 packed single-precision (32-bit)
+ /// floating-point elements) from memory, and combine them into a 256-bit
+ /// value.
+ /// `hiaddr` and `loaddr` do not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu2_m128)
+ #[inline]
+ #[target_feature(enable = "avx,sse")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_loadu2_m128(hiaddr: *const f32, loaddr: *const f32) -> __m256 {
+     let a = _mm256_castps128_ps256(_mm_loadu_ps(loaddr));
+     _mm256_insertf128_ps(a, _mm_loadu_ps(hiaddr), 1)
+ }
+ 
+ /// Loads two 128-bit values (composed of 2 packed double-precision (64-bit)
+ /// floating-point elements) from memory, and combine them into a 256-bit
+ /// value.
+ /// `hiaddr` and `loaddr` do not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu2_m128d)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_loadu2_m128d(hiaddr: *const f64, loaddr: *const f64) -> __m256d {
+     let a = _mm256_castpd128_pd256(_mm_loadu_pd(loaddr));
+     _mm256_insertf128_pd(a, _mm_loadu_pd(hiaddr), 1)
+ }
+ 
+ /// Loads two 128-bit values (composed of integer data) from memory, and combine
+ /// them into a 256-bit value.
+ /// `hiaddr` and `loaddr` do not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_loadu2_m128i)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_loadu2_m128i(hiaddr: *const __m128i, loaddr: *const __m128i) -> __m256i {
+     let a = _mm256_castsi128_si256(_mm_loadu_si128(loaddr));
+     _mm256_insertf128_si256(a, _mm_loadu_si128(hiaddr), 1)
+ }
+ 
+ /// Stores the high and low 128-bit halves (each composed of 4 packed
+ /// single-precision (32-bit) floating-point elements) from `a` into memory two
+ /// different 128-bit locations.
+ /// `hiaddr` and `loaddr` do not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu2_m128)
+ #[inline]
+ #[target_feature(enable = "avx,sse")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_storeu2_m128(hiaddr: *mut f32, loaddr: *mut f32, a: __m256) {
+     let lo = _mm256_castps256_ps128(a);
+     _mm_storeu_ps(loaddr, lo);
+     let hi = _mm256_extractf128_ps(a, 1);
+     _mm_storeu_ps(hiaddr, hi);
+ }
+ 
+ /// Stores the high and low 128-bit halves (each composed of 2 packed
+ /// double-precision (64-bit) floating-point elements) from `a` into memory two
+ /// different 128-bit locations.
+ /// `hiaddr` and `loaddr` do not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu2_m128d)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_storeu2_m128d(hiaddr: *mut f64, loaddr: *mut f64, a: __m256d) {
+     let lo = _mm256_castpd256_pd128(a);
+     _mm_storeu_pd(loaddr, lo);
+     let hi = _mm256_extractf128_pd(a, 1);
+     _mm_storeu_pd(hiaddr, hi);
+ }
+ 
+ /// Stores the high and low 128-bit halves (each composed of integer data) from
+ /// `a` into memory two different 128-bit locations.
+ /// `hiaddr` and `loaddr` do not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu2_m128i)
+ #[inline]
+ #[target_feature(enable = "avx,sse2")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_storeu2_m128i(hiaddr: *mut __m128i, loaddr: *mut __m128i, a: __m256i) {
+     let lo = _mm256_castsi256_si128(a);
+     _mm_storeu_si128(loaddr, lo);
+     let hi = _mm256_extractf128_si256(a, 1);
+     _mm_storeu_si128(hiaddr, hi);
+ }
+ 
+ /// Returns the first element of the input vector of `[8 x float]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtss_f32)
+ #[inline]
+ #[target_feature(enable = "avx")]
+ //#[cfg_attr(test, assert_instr(movss))] FIXME
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtss_f32(a: __m256) -> f32 {
+     simd_extract(a, 0)
+ }
+ 
+ /// LLVM intrinsics used in the above functions
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.avx.addsub.pd.256"]
+     fn addsubpd256(a: __m256d, b: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.avx.addsub.ps.256"]
+     fn addsubps256(a: __m256, b: __m256) -> __m256;
+     #[link_name = "llvm.x86.avx.round.pd.256"]
+     fn roundpd256(a: __m256d, b: i32) -> __m256d;
+     #[link_name = "llvm.x86.avx.round.ps.256"]
+     fn roundps256(a: __m256, b: i32) -> __m256;
+     #[link_name = "llvm.x86.avx.sqrt.ps.256"]
+     fn sqrtps256(a: __m256) -> __m256;
+     #[link_name = "llvm.x86.avx.blendv.pd.256"]
+     fn vblendvpd(a: __m256d, b: __m256d, c: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.avx.blendv.ps.256"]
+     fn vblendvps(a: __m256, b: __m256, c: __m256) -> __m256;
+     #[link_name = "llvm.x86.avx.dp.ps.256"]
+     fn vdpps(a: __m256, b: __m256, imm8: i32) -> __m256;
+     #[link_name = "llvm.x86.avx.hadd.pd.256"]
+     fn vhaddpd(a: __m256d, b: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.avx.hadd.ps.256"]
+     fn vhaddps(a: __m256, b: __m256) -> __m256;
+     #[link_name = "llvm.x86.avx.hsub.pd.256"]
+     fn vhsubpd(a: __m256d, b: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.avx.hsub.ps.256"]
+     fn vhsubps(a: __m256, b: __m256) -> __m256;
+     #[link_name = "llvm.x86.sse2.cmp.pd"]
+     fn vcmppd(a: __m128d, b: __m128d, imm8: i8) -> __m128d;
+     #[link_name = "llvm.x86.avx.cmp.pd.256"]
+     fn vcmppd256(a: __m256d, b: __m256d, imm8: u8) -> __m256d;
+     #[link_name = "llvm.x86.sse.cmp.ps"]
+     fn vcmpps(a: __m128, b: __m128, imm8: i8) -> __m128;
+     #[link_name = "llvm.x86.avx.cmp.ps.256"]
+     fn vcmpps256(a: __m256, b: __m256, imm8: u8) -> __m256;
+     #[link_name = "llvm.x86.sse2.cmp.sd"]
+     fn vcmpsd(a: __m128d, b: __m128d, imm8: i8) -> __m128d;
+     #[link_name = "llvm.x86.sse.cmp.ss"]
+     fn vcmpss(a: __m128, b: __m128, imm8: i8) -> __m128;
+     #[link_name = "llvm.x86.avx.cvtdq2.ps.256"]
+     fn vcvtdq2ps(a: i32x8) -> __m256;
+     #[link_name = "llvm.x86.avx.cvt.pd2.ps.256"]
+     fn vcvtpd2ps(a: __m256d) -> __m128;
+     #[link_name = "llvm.x86.avx.cvt.ps2dq.256"]
+     fn vcvtps2dq(a: __m256) -> i32x8;
+     #[link_name = "llvm.x86.avx.cvtt.pd2dq.256"]
+     fn vcvttpd2dq(a: __m256d) -> i32x4;
+     #[link_name = "llvm.x86.avx.cvt.pd2dq.256"]
+     fn vcvtpd2dq(a: __m256d) -> i32x4;
+     #[link_name = "llvm.x86.avx.cvtt.ps2dq.256"]
+     fn vcvttps2dq(a: __m256) -> i32x8;
+     #[link_name = "llvm.x86.avx.vzeroall"]
+     fn vzeroall();
+     #[link_name = "llvm.x86.avx.vzeroupper"]
+     fn vzeroupper();
+     #[link_name = "llvm.x86.avx.vpermilvar.ps.256"]
+     fn vpermilps256(a: __m256, b: i32x8) -> __m256;
+     #[link_name = "llvm.x86.avx.vpermilvar.ps"]
+     fn vpermilps(a: __m128, b: i32x4) -> __m128;
+     #[link_name = "llvm.x86.avx.vpermilvar.pd.256"]
+     fn vpermilpd256(a: __m256d, b: i64x4) -> __m256d;
+     #[link_name = "llvm.x86.avx.vpermilvar.pd"]
+     fn vpermilpd(a: __m128d, b: i64x2) -> __m128d;
+     #[link_name = "llvm.x86.avx.vperm2f128.ps.256"]
+     fn vperm2f128ps256(a: __m256, b: __m256, imm8: i8) -> __m256;
+     #[link_name = "llvm.x86.avx.vperm2f128.pd.256"]
+     fn vperm2f128pd256(a: __m256d, b: __m256d, imm8: i8) -> __m256d;
+     #[link_name = "llvm.x86.avx.vperm2f128.si.256"]
+     fn vperm2f128si256(a: i32x8, b: i32x8, imm8: i8) -> i32x8;
+     #[link_name = "llvm.x86.avx.vbroadcastf128.ps.256"]
+     fn vbroadcastf128ps256(a: &__m128) -> __m256;
+     #[link_name = "llvm.x86.avx.vbroadcastf128.pd.256"]
+     fn vbroadcastf128pd256(a: &__m128d) -> __m256d;
+     #[link_name = "llvm.x86.avx.storeu.pd.256"]
+     fn storeupd256(mem_addr: *mut f64, a: __m256d);
+     #[link_name = "llvm.x86.avx.storeu.ps.256"]
+     fn storeups256(mem_addr: *mut f32, a: __m256);
+     #[link_name = "llvm.x86.avx.storeu.dq.256"]
+     fn storeudq256(mem_addr: *mut i8, a: i8x32);
+     #[link_name = "llvm.x86.avx.maskload.pd.256"]
+     fn maskloadpd256(mem_addr: *const i8, mask: i64x4) -> __m256d;
+     #[link_name = "llvm.x86.avx.maskstore.pd.256"]
+     fn maskstorepd256(mem_addr: *mut i8, mask: i64x4, a: __m256d);
+     #[link_name = "llvm.x86.avx.maskload.pd"]
+     fn maskloadpd(mem_addr: *const i8, mask: i64x2) -> __m128d;
+     #[link_name = "llvm.x86.avx.maskstore.pd"]
+     fn maskstorepd(mem_addr: *mut i8, mask: i64x2, a: __m128d);
+     #[link_name = "llvm.x86.avx.maskload.ps.256"]
+     fn maskloadps256(mem_addr: *const i8, mask: i32x8) -> __m256;
+     #[link_name = "llvm.x86.avx.maskstore.ps.256"]
+     fn maskstoreps256(mem_addr: *mut i8, mask: i32x8, a: __m256);
+     #[link_name = "llvm.x86.avx.maskload.ps"]
+     fn maskloadps(mem_addr: *const i8, mask: i32x4) -> __m128;
+     #[link_name = "llvm.x86.avx.maskstore.ps"]
+     fn maskstoreps(mem_addr: *mut i8, mask: i32x4, a: __m128);
+     #[link_name = "llvm.x86.avx.ldu.dq.256"]
+     fn vlddqu(mem_addr: *const i8) -> i8x32;
+     #[link_name = "llvm.x86.avx.rcp.ps.256"]
+     fn vrcpps(a: __m256) -> __m256;
+     #[link_name = "llvm.x86.avx.rsqrt.ps.256"]
+     fn vrsqrtps(a: __m256) -> __m256;
+     #[link_name = "llvm.x86.avx.ptestz.256"]
+     fn ptestz256(a: i64x4, b: i64x4) -> i32;
+     #[link_name = "llvm.x86.avx.ptestc.256"]
+     fn ptestc256(a: i64x4, b: i64x4) -> i32;
+     #[link_name = "llvm.x86.avx.ptestnzc.256"]
+     fn ptestnzc256(a: i64x4, b: i64x4) -> i32;
+     #[link_name = "llvm.x86.avx.vtestz.pd.256"]
+     fn vtestzpd256(a: __m256d, b: __m256d) -> i32;
+     #[link_name = "llvm.x86.avx.vtestc.pd.256"]
+     fn vtestcpd256(a: __m256d, b: __m256d) -> i32;
+     #[link_name = "llvm.x86.avx.vtestnzc.pd.256"]
+     fn vtestnzcpd256(a: __m256d, b: __m256d) -> i32;
+     #[link_name = "llvm.x86.avx.vtestz.pd"]
+     fn vtestzpd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.avx.vtestc.pd"]
+     fn vtestcpd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.avx.vtestnzc.pd"]
+     fn vtestnzcpd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.avx.vtestz.ps.256"]
+     fn vtestzps256(a: __m256, b: __m256) -> i32;
+     #[link_name = "llvm.x86.avx.vtestc.ps.256"]
+     fn vtestcps256(a: __m256, b: __m256) -> i32;
+     #[link_name = "llvm.x86.avx.vtestnzc.ps.256"]
+     fn vtestnzcps256(a: __m256, b: __m256) -> i32;
+     #[link_name = "llvm.x86.avx.vtestz.ps"]
+     fn vtestzps(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.avx.vtestc.ps"]
+     fn vtestcps(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.avx.vtestnzc.ps"]
+     fn vtestnzcps(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.avx.movmsk.pd.256"]
+     fn movmskpd256(a: __m256d) -> i32;
+     #[link_name = "llvm.x86.avx.movmsk.ps.256"]
+     fn movmskps256(a: __m256) -> i32;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::hint::black_box;
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_add_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_add_pd(a, b);
+         let e = _mm256_setr_pd(6., 8., 10., 12.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_add_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
+         let r = _mm256_add_ps(a, b);
+         let e = _mm256_setr_ps(10., 12., 14., 16., 18., 20., 22., 24.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_and_pd() {
+         let a = _mm256_set1_pd(1.);
+         let b = _mm256_set1_pd(0.6);
+         let r = _mm256_and_pd(a, b);
+         let e = _mm256_set1_pd(0.5);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_and_ps() {
+         let a = _mm256_set1_ps(1.);
+         let b = _mm256_set1_ps(0.6);
+         let r = _mm256_and_ps(a, b);
+         let e = _mm256_set1_ps(0.5);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_or_pd() {
+         let a = _mm256_set1_pd(1.);
+         let b = _mm256_set1_pd(0.6);
+         let r = _mm256_or_pd(a, b);
+         let e = _mm256_set1_pd(1.2);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_or_ps() {
+         let a = _mm256_set1_ps(1.);
+         let b = _mm256_set1_ps(0.6);
+         let r = _mm256_or_ps(a, b);
+         let e = _mm256_set1_ps(1.2);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_shuffle_pd() {
+         let a = _mm256_setr_pd(1., 4., 5., 8.);
+         let b = _mm256_setr_pd(2., 3., 6., 7.);
+         let r = _mm256_shuffle_pd(a, b, 0xF);
+         let e = _mm256_setr_pd(4., 3., 8., 7.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_shuffle_ps() {
+         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm256_shuffle_ps(a, b, 0x0F);
+         let e = _mm256_setr_ps(8., 8., 2., 2., 16., 16., 10., 10.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_andnot_pd() {
+         let a = _mm256_set1_pd(0.);
+         let b = _mm256_set1_pd(0.6);
+         let r = _mm256_andnot_pd(a, b);
+         assert_eq_m256d(r, b);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_andnot_ps() {
+         let a = _mm256_set1_ps(0.);
+         let b = _mm256_set1_ps(0.6);
+         let r = _mm256_andnot_ps(a, b);
+         assert_eq_m256(r, b);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_max_pd() {
+         let a = _mm256_setr_pd(1., 4., 5., 8.);
+         let b = _mm256_setr_pd(2., 3., 6., 7.);
+         let r = _mm256_max_pd(a, b);
+         let e = _mm256_setr_pd(2., 4., 6., 8.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_max_ps() {
+         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm256_max_ps(a, b);
+         let e = _mm256_setr_ps(2., 4., 6., 8., 10., 12., 14., 16.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_min_pd() {
+         let a = _mm256_setr_pd(1., 4., 5., 8.);
+         let b = _mm256_setr_pd(2., 3., 6., 7.);
+         let r = _mm256_min_pd(a, b);
+         let e = _mm256_setr_pd(1., 3., 5., 7.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_min_ps() {
+         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm256_min_ps(a, b);
+         let e = _mm256_setr_ps(1., 3., 5., 7., 9., 11., 13., 15.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_mul_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_mul_pd(a, b);
+         let e = _mm256_setr_pd(5., 12., 21., 32.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_mul_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
+         let r = _mm256_mul_ps(a, b);
+         let e = _mm256_setr_ps(9., 20., 33., 48., 65., 84., 105., 128.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_addsub_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_addsub_pd(a, b);
+         let e = _mm256_setr_pd(-4., 8., -4., 12.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_addsub_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
+         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
+         let r = _mm256_addsub_ps(a, b);
+         let e = _mm256_setr_ps(-4., 8., -4., 12., -4., 8., -4., 12.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_sub_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_sub_pd(a, b);
+         let e = _mm256_setr_pd(-4., -4., -4., -4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_sub_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., -1., -2., -3., -4.);
+         let b = _mm256_setr_ps(5., 6., 7., 8., 3., 2., 1., 0.);
+         let r = _mm256_sub_ps(a, b);
+         let e = _mm256_setr_ps(-4., -4., -4., -4., -4., -4., -4., -4.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_round_pd() {
+         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
+         let result_closest = _mm256_round_pd(a, 0b00000000);
+         let result_down = _mm256_round_pd(a, 0b00000001);
+         let result_up = _mm256_round_pd(a, 0b00000010);
+         let expected_closest = _mm256_setr_pd(2., 2., 4., -1.);
+         let expected_down = _mm256_setr_pd(1., 2., 3., -2.);
+         let expected_up = _mm256_setr_pd(2., 3., 4., -1.);
+         assert_eq_m256d(result_closest, expected_closest);
+         assert_eq_m256d(result_down, expected_down);
+         assert_eq_m256d(result_up, expected_up);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_floor_pd() {
+         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
+         let result_down = _mm256_floor_pd(a);
+         let expected_down = _mm256_setr_pd(1., 2., 3., -2.);
+         assert_eq_m256d(result_down, expected_down);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_ceil_pd() {
+         let a = _mm256_setr_pd(1.55, 2.2, 3.99, -1.2);
+         let result_up = _mm256_ceil_pd(a);
+         let expected_up = _mm256_setr_pd(2., 3., 4., -1.);
+         assert_eq_m256d(result_up, expected_up);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_round_ps() {
+         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
+         let result_closest = _mm256_round_ps(a, 0b00000000);
+         let result_down = _mm256_round_ps(a, 0b00000001);
+         let result_up = _mm256_round_ps(a, 0b00000010);
+         let expected_closest = _mm256_setr_ps(2., 2., 4., -1., 2., 2., 4., -1.);
+         let expected_down = _mm256_setr_ps(1., 2., 3., -2., 1., 2., 3., -2.);
+         let expected_up = _mm256_setr_ps(2., 3., 4., -1., 2., 3., 4., -1.);
+         assert_eq_m256(result_closest, expected_closest);
+         assert_eq_m256(result_down, expected_down);
+         assert_eq_m256(result_up, expected_up);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_floor_ps() {
+         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
+         let result_down = _mm256_floor_ps(a);
+         let expected_down = _mm256_setr_ps(1., 2., 3., -2., 1., 2., 3., -2.);
+         assert_eq_m256(result_down, expected_down);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_ceil_ps() {
+         let a = _mm256_setr_ps(1.55, 2.2, 3.99, -1.2, 1.55, 2.2, 3.99, -1.2);
+         let result_up = _mm256_ceil_ps(a);
+         let expected_up = _mm256_setr_ps(2., 3., 4., -1., 2., 3., 4., -1.);
+         assert_eq_m256(result_up, expected_up);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_sqrt_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let r = _mm256_sqrt_pd(a);
+         let e = _mm256_setr_pd(2., 3., 4., 5.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_sqrt_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let r = _mm256_sqrt_ps(a);
+         let e = _mm256_setr_ps(2., 3., 4., 5., 2., 3., 4., 5.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_div_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let r = _mm256_div_ps(a, b);
+         let e = _mm256_setr_ps(1., 3., 8., 5., 0.5, 1., 0.25, 0.5);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_div_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let b = _mm256_setr_pd(4., 3., 2., 5.);
+         let r = _mm256_div_pd(a, b);
+         let e = _mm256_setr_pd(1., 3., 8., 5.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_blend_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let b = _mm256_setr_pd(4., 3., 2., 5.);
+         let r = _mm256_blend_pd(a, b, 0x0);
+         assert_eq_m256d(r, _mm256_setr_pd(4., 9., 16., 25.));
+         let r = _mm256_blend_pd(a, b, 0x3);
+         assert_eq_m256d(r, _mm256_setr_pd(4., 3., 16., 25.));
+         let r = _mm256_blend_pd(a, b, 0xF);
+         assert_eq_m256d(r, _mm256_setr_pd(4., 3., 2., 5.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_blend_ps() {
+         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm256_blend_ps(a, b, 0x0);
+         assert_eq_m256(r, _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.));
+         let r = _mm256_blend_ps(a, b, 0x3);
+         assert_eq_m256(r, _mm256_setr_ps(2., 3., 5., 8., 9., 12., 13., 16.));
+         let r = _mm256_blend_ps(a, b, 0xF);
+         assert_eq_m256(r, _mm256_setr_ps(2., 3., 6., 7., 9., 12., 13., 16.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_blendv_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let b = _mm256_setr_pd(4., 3., 2., 5.);
+         let c = _mm256_setr_pd(0., 0., !0 as f64, !0 as f64);
+         let r = _mm256_blendv_pd(a, b, c);
+         let e = _mm256_setr_pd(4., 9., 2., 5.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_blendv_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         #[rustfmt::skip]
+         let c = _mm256_setr_ps(
+             0., 0., 0., 0., !0 as f32, !0 as f32, !0 as f32, !0 as f32,
+         );
+         let r = _mm256_blendv_ps(a, b, c);
+         let e = _mm256_setr_ps(4., 9., 16., 25., 8., 9., 64., 50.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_dp_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let r = _mm256_dp_ps(a, b, 0xFF);
+         let e = _mm256_setr_ps(200., 200., 200., 200., 2387., 2387., 2387., 2387.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_hadd_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let b = _mm256_setr_pd(4., 3., 2., 5.);
+         let r = _mm256_hadd_pd(a, b);
+         let e = _mm256_setr_pd(13., 7., 41., 7.);
+         assert_eq_m256d(r, e);
+ 
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_hadd_pd(a, b);
+         let e = _mm256_setr_pd(3., 11., 7., 15.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_hadd_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let r = _mm256_hadd_ps(a, b);
+         let e = _mm256_setr_ps(13., 41., 7., 7., 13., 41., 17., 114.);
+         assert_eq_m256(r, e);
+ 
+         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
+         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
+         let r = _mm256_hadd_ps(a, b);
+         let e = _mm256_setr_ps(3., 7., 11., 15., 3., 7., 11., 15.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_hsub_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let b = _mm256_setr_pd(4., 3., 2., 5.);
+         let r = _mm256_hsub_pd(a, b);
+         let e = _mm256_setr_pd(-5., 1., -9., -3.);
+         assert_eq_m256d(r, e);
+ 
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_hsub_pd(a, b);
+         let e = _mm256_setr_pd(-1., -1., -1., -1.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_hsub_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let b = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let r = _mm256_hsub_ps(a, b);
+         let e = _mm256_setr_ps(-5., -9., 1., -3., -5., -9., -1., 14.);
+         assert_eq_m256(r, e);
+ 
+         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
+         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
+         let r = _mm256_hsub_ps(a, b);
+         let e = _mm256_setr_ps(-1., -1., -1., -1., -1., -1., -1., -1.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_xor_pd() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let b = _mm256_set1_pd(0.);
+         let r = _mm256_xor_pd(a, b);
+         assert_eq_m256d(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_xor_ps() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let b = _mm256_set1_ps(0.);
+         let r = _mm256_xor_ps(a, b);
+         assert_eq_m256(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_cmp_pd() {
+         let a = _mm_setr_pd(4., 9.);
+         let b = _mm_setr_pd(4., 3.);
+         let r = _mm_cmp_pd(a, b, _CMP_GE_OS);
+         assert!(get_m128d(r, 0).is_nan());
+         assert!(get_m128d(r, 1).is_nan());
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cmp_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_cmp_pd(a, b, _CMP_GE_OS);
+         let e = _mm256_set1_pd(0.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_cmp_ps() {
+         let a = _mm_setr_ps(4., 3., 2., 5.);
+         let b = _mm_setr_ps(4., 9., 16., 25.);
+         let r = _mm_cmp_ps(a, b, _CMP_GE_OS);
+         assert!(get_m128(r, 0).is_nan());
+         assert_eq!(get_m128(r, 1), 0.);
+         assert_eq!(get_m128(r, 2), 0.);
+         assert_eq!(get_m128(r, 3), 0.);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cmp_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
+         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
+         let r = _mm256_cmp_ps(a, b, _CMP_GE_OS);
+         let e = _mm256_set1_ps(0.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_cmp_sd() {
+         let a = _mm_setr_pd(4., 9.);
+         let b = _mm_setr_pd(4., 3.);
+         let r = _mm_cmp_sd(a, b, _CMP_GE_OS);
+         assert!(get_m128d(r, 0).is_nan());
+         assert_eq!(get_m128d(r, 1), 9.);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_cmp_ss() {
+         let a = _mm_setr_ps(4., 3., 2., 5.);
+         let b = _mm_setr_ps(4., 9., 16., 25.);
+         let r = _mm_cmp_ss(a, b, _CMP_GE_OS);
+         assert!(get_m128(r, 0).is_nan());
+         assert_eq!(get_m128(r, 1), 3.);
+         assert_eq!(get_m128(r, 2), 2.);
+         assert_eq!(get_m128(r, 3), 5.);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtepi32_pd() {
+         let a = _mm_setr_epi32(4, 9, 16, 25);
+         let r = _mm256_cvtepi32_pd(a);
+         let e = _mm256_setr_pd(4., 9., 16., 25.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtepi32_ps() {
+         let a = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
+         let r = _mm256_cvtepi32_ps(a);
+         let e = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtpd_ps() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let r = _mm256_cvtpd_ps(a);
+         let e = _mm_setr_ps(4., 9., 16., 25.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtps_epi32() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let r = _mm256_cvtps_epi32(a);
+         let e = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtps_pd() {
+         let a = _mm_setr_ps(4., 9., 16., 25.);
+         let r = _mm256_cvtps_pd(a);
+         let e = _mm256_setr_pd(4., 9., 16., 25.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvttpd_epi32() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let r = _mm256_cvttpd_epi32(a);
+         let e = _mm_setr_epi32(4, 9, 16, 25);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtpd_epi32() {
+         let a = _mm256_setr_pd(4., 9., 16., 25.);
+         let r = _mm256_cvtpd_epi32(a);
+         let e = _mm_setr_epi32(4, 9, 16, 25);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvttps_epi32() {
+         let a = _mm256_setr_ps(4., 9., 16., 25., 4., 9., 16., 25.);
+         let r = _mm256_cvttps_epi32(a);
+         let e = _mm256_setr_epi32(4, 9, 16, 25, 4, 9, 16, 25);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_extractf128_ps() {
+         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let r = _mm256_extractf128_ps(a, 0);
+         let e = _mm_setr_ps(4., 3., 2., 5.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_extractf128_pd() {
+         let a = _mm256_setr_pd(4., 3., 2., 5.);
+         let r = _mm256_extractf128_pd(a, 0);
+         let e = _mm_setr_pd(4., 3.);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_extractf128_si256() {
+         let a = _mm256_setr_epi64x(4, 3, 2, 5);
+         let r = _mm256_extractf128_si256(a, 0);
+         let e = _mm_setr_epi64x(4, 3);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_zeroall() {
+         _mm256_zeroall();
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_zeroupper() {
+         _mm256_zeroupper();
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permutevar_ps() {
+         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = _mm256_permutevar_ps(a, b);
+         let e = _mm256_setr_ps(3., 2., 5., 4., 9., 64., 50., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_permutevar_ps() {
+         let a = _mm_setr_ps(4., 3., 2., 5.);
+         let b = _mm_setr_epi32(1, 2, 3, 4);
+         let r = _mm_permutevar_ps(a, b);
+         let e = _mm_setr_ps(3., 2., 5., 4.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permute_ps() {
+         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let r = _mm256_permute_ps(a, 0x1b);
+         let e = _mm256_setr_ps(5., 2., 3., 4., 50., 64., 9., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_permute_ps() {
+         let a = _mm_setr_ps(4., 3., 2., 5.);
+         let r = _mm_permute_ps(a, 0x1b);
+         let e = _mm_setr_ps(5., 2., 3., 4.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permutevar_pd() {
+         let a = _mm256_setr_pd(4., 3., 2., 5.);
+         let b = _mm256_setr_epi64x(1, 2, 3, 4);
+         let r = _mm256_permutevar_pd(a, b);
+         let e = _mm256_setr_pd(4., 3., 5., 2.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_permutevar_pd() {
+         let a = _mm_setr_pd(4., 3.);
+         let b = _mm_setr_epi64x(3, 0);
+         let r = _mm_permutevar_pd(a, b);
+         let e = _mm_setr_pd(3., 4.);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permute_pd() {
+         let a = _mm256_setr_pd(4., 3., 2., 5.);
+         let r = _mm256_permute_pd(a, 5);
+         let e = _mm256_setr_pd(3., 4., 5., 2.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_permute_pd() {
+         let a = _mm_setr_pd(4., 3.);
+         let r = _mm_permute_pd(a, 1);
+         let e = _mm_setr_pd(3., 4.);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permute2f128_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 1., 2., 3., 4.);
+         let b = _mm256_setr_ps(5., 6., 7., 8., 5., 6., 7., 8.);
+         let r = _mm256_permute2f128_ps(a, b, 0x13);
+         let e = _mm256_setr_ps(5., 6., 7., 8., 1., 2., 3., 4.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permute2f128_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_permute2f128_pd(a, b, 0x31);
+         let e = _mm256_setr_pd(3., 4., 7., 8.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_permute2f128_si256() {
+         let a = _mm256_setr_epi32(1, 2, 3, 4, 1, 2, 3, 4);
+         let b = _mm256_setr_epi32(5, 6, 7, 8, 5, 6, 7, 8);
+         let r = _mm256_permute2f128_si256(a, b, 0x20);
+         let e = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_broadcast_ss() {
+         let r = _mm256_broadcast_ss(&3.);
+         let e = _mm256_set1_ps(3.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_broadcast_ss() {
+         let r = _mm_broadcast_ss(&3.);
+         let e = _mm_set1_ps(3.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_broadcast_sd() {
+         let r = _mm256_broadcast_sd(&3.);
+         let e = _mm256_set1_pd(3.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_broadcast_ps() {
+         let a = _mm_setr_ps(4., 3., 2., 5.);
+         let r = _mm256_broadcast_ps(&a);
+         let e = _mm256_setr_ps(4., 3., 2., 5., 4., 3., 2., 5.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_broadcast_pd() {
+         let a = _mm_setr_pd(4., 3.);
+         let r = _mm256_broadcast_pd(&a);
+         let e = _mm256_setr_pd(4., 3., 4., 3.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insertf128_ps() {
+         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let b = _mm_setr_ps(4., 9., 16., 25.);
+         let r = _mm256_insertf128_ps(a, b, 0);
+         let e = _mm256_setr_ps(4., 9., 16., 25., 8., 9., 64., 50.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insertf128_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm_setr_pd(5., 6.);
+         let r = _mm256_insertf128_pd(a, b, 0);
+         let e = _mm256_setr_pd(5., 6., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insertf128_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let b = _mm_setr_epi64x(5, 6);
+         let r = _mm256_insertf128_si256(a, b, 0);
+         let e = _mm256_setr_epi64x(5, 6, 3, 4);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insert_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm256_insert_epi8(a, 0, 31);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 0,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insert_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         let r = _mm256_insert_epi16(a, 0, 15);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 0,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insert_epi32() {
+         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = _mm256_insert_epi32(a, 0, 7);
+         let e = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_load_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let p = &a as *const _ as *const f64;
+         let r = _mm256_load_pd(p);
+         let e = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_store_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let mut r = _mm256_undefined_pd();
+         _mm256_store_pd(&mut r as *mut _ as *mut f64, a);
+         assert_eq_m256d(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_load_ps() {
+         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let p = &a as *const _ as *const f32;
+         let r = _mm256_load_ps(p);
+         let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_store_ps() {
+         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         let mut r = _mm256_undefined_ps();
+         _mm256_store_ps(&mut r as *mut _ as *mut f32, a);
+         assert_eq_m256(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_loadu_pd() {
+         let a = &[1.0f64, 2., 3., 4.];
+         let p = a.as_ptr();
+         let r = _mm256_loadu_pd(black_box(p));
+         let e = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_storeu_pd() {
+         let a = _mm256_set1_pd(9.);
+         let mut r = _mm256_undefined_pd();
+         _mm256_storeu_pd(&mut r as *mut _ as *mut f64, a);
+         assert_eq_m256d(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_loadu_ps() {
+         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
+         let p = a.as_ptr();
+         let r = _mm256_loadu_ps(black_box(p));
+         let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_storeu_ps() {
+         let a = _mm256_set1_ps(9.);
+         let mut r = _mm256_undefined_ps();
+         _mm256_storeu_ps(&mut r as *mut _ as *mut f32, a);
+         assert_eq_m256(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_load_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let p = &a as *const _;
+         let r = _mm256_load_si256(p);
+         let e = _mm256_setr_epi64x(1, 2, 3, 4);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_store_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let mut r = _mm256_undefined_si256();
+         _mm256_store_si256(&mut r as *mut _, a);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_loadu_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let p = &a as *const _;
+         let r = _mm256_loadu_si256(black_box(p));
+         let e = _mm256_setr_epi64x(1, 2, 3, 4);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_storeu_si256() {
+         let a = _mm256_set1_epi8(9);
+         let mut r = _mm256_undefined_si256();
+         _mm256_storeu_si256(&mut r as *mut _, a);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_maskload_pd() {
+         let a = &[1.0f64, 2., 3., 4.];
+         let p = a.as_ptr();
+         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
+         let r = _mm256_maskload_pd(black_box(p), mask);
+         let e = _mm256_setr_pd(0., 2., 0., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_maskstore_pd() {
+         let mut r = _mm256_set1_pd(0.);
+         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         _mm256_maskstore_pd(&mut r as *mut _ as *mut f64, mask, a);
+         let e = _mm256_setr_pd(0., 2., 0., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_maskload_pd() {
+         let a = &[1.0f64, 2.];
+         let p = a.as_ptr();
+         let mask = _mm_setr_epi64x(0, !0);
+         let r = _mm_maskload_pd(black_box(p), mask);
+         let e = _mm_setr_pd(0., 2.);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_maskstore_pd() {
+         let mut r = _mm_set1_pd(0.);
+         let mask = _mm_setr_epi64x(0, !0);
+         let a = _mm_setr_pd(1., 2.);
+         _mm_maskstore_pd(&mut r as *mut _ as *mut f64, mask, a);
+         let e = _mm_setr_pd(0., 2.);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_maskload_ps() {
+         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
+         let p = a.as_ptr();
+         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
+         let r = _mm256_maskload_ps(black_box(p), mask);
+         let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_maskstore_ps() {
+         let mut r = _mm256_set1_ps(0.);
+         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         _mm256_maskstore_ps(&mut r as *mut _ as *mut f32, mask, a);
+         let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_maskload_ps() {
+         let a = &[1.0f32, 2., 3., 4.];
+         let p = a.as_ptr();
+         let mask = _mm_setr_epi32(0, !0, 0, !0);
+         let r = _mm_maskload_ps(black_box(p), mask);
+         let e = _mm_setr_ps(0., 2., 0., 4.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_maskstore_ps() {
+         let mut r = _mm_set1_ps(0.);
+         let mask = _mm_setr_epi32(0, !0, 0, !0);
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         _mm_maskstore_ps(&mut r as *mut _ as *mut f32, mask, a);
+         let e = _mm_setr_ps(0., 2., 0., 4.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_movehdup_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_movehdup_ps(a);
+         let e = _mm256_setr_ps(2., 2., 4., 4., 6., 6., 8., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_moveldup_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_moveldup_ps(a);
+         let e = _mm256_setr_ps(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_movedup_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let r = _mm256_movedup_pd(a);
+         let e = _mm256_setr_pd(1., 1., 3., 3.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_lddqu_si256() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let p = &a as *const _;
+         let r = _mm256_lddqu_si256(black_box(p));
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_stream_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let mut r = _mm256_undefined_si256();
+         _mm256_stream_si256(&mut r as *mut _, a);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_stream_pd() {
+         #[repr(align(32))]
+         struct Memory {
+             pub data: [f64; 4],
+         }
+         let a = _mm256_set1_pd(7.0);
+         let mut mem = Memory { data: [-1.0; 4] };
+ 
+         _mm256_stream_pd(&mut mem.data[0] as *mut f64, a);
+         for i in 0..4 {
+             assert_eq!(mem.data[i], get_m256d(a, i));
+         }
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_stream_ps() {
+         #[repr(align(32))]
+         struct Memory {
+             pub data: [f32; 8],
+         }
+         let a = _mm256_set1_ps(7.0);
+         let mut mem = Memory { data: [-1.0; 8] };
+ 
+         _mm256_stream_ps(&mut mem.data[0] as *mut f32, a);
+         for i in 0..8 {
+             assert_eq!(mem.data[i], get_m256(a, i));
+         }
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_rcp_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_rcp_ps(a);
+         #[rustfmt::skip]
+         let e = _mm256_setr_ps(
+             0.99975586, 0.49987793, 0.33325195, 0.24993896,
+             0.19995117, 0.16662598, 0.14282227, 0.12496948,
+         );
+         let rel_err = 0.00048828125;
+         for i in 0..8 {
+             assert_approx_eq!(get_m256(r, i), get_m256(e, i), 2. * rel_err);
+         }
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_rsqrt_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_rsqrt_ps(a);
+         #[rustfmt::skip]
+         let e = _mm256_setr_ps(
+             0.99975586, 0.7069092, 0.5772705, 0.49987793,
+             0.44714355, 0.40820313, 0.3779297, 0.3534546,
+         );
+         let rel_err = 0.00048828125;
+         for i in 0..8 {
+             assert_approx_eq!(get_m256(r, i), get_m256(e, i), 2. * rel_err);
+         }
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_unpackhi_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_unpackhi_pd(a, b);
+         let e = _mm256_setr_pd(2., 6., 4., 8.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_unpackhi_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
+         let r = _mm256_unpackhi_ps(a, b);
+         let e = _mm256_setr_ps(3., 11., 4., 12., 7., 15., 8., 16.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_unpacklo_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_unpacklo_pd(a, b);
+         let e = _mm256_setr_pd(1., 5., 3., 7.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_unpacklo_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
+         let r = _mm256_unpacklo_ps(a, b);
+         let e = _mm256_setr_ps(1., 9., 2., 10., 5., 13., 6., 14.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testz_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let b = _mm256_setr_epi64x(5, 6, 7, 8);
+         let r = _mm256_testz_si256(a, b);
+         assert_eq!(r, 0);
+         let b = _mm256_set1_epi64x(0);
+         let r = _mm256_testz_si256(a, b);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testc_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let b = _mm256_setr_epi64x(5, 6, 7, 8);
+         let r = _mm256_testc_si256(a, b);
+         assert_eq!(r, 0);
+         let b = _mm256_set1_epi64x(0);
+         let r = _mm256_testc_si256(a, b);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testnzc_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let b = _mm256_setr_epi64x(5, 6, 7, 8);
+         let r = _mm256_testnzc_si256(a, b);
+         assert_eq!(r, 1);
+         let a = _mm256_setr_epi64x(0, 0, 0, 0);
+         let b = _mm256_setr_epi64x(0, 0, 0, 0);
+         let r = _mm256_testnzc_si256(a, b);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testz_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_testz_pd(a, b);
+         assert_eq!(r, 1);
+         let a = _mm256_set1_pd(-1.);
+         let r = _mm256_testz_pd(a, a);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testc_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_testc_pd(a, b);
+         assert_eq!(r, 1);
+         let a = _mm256_set1_pd(1.);
+         let b = _mm256_set1_pd(-1.);
+         let r = _mm256_testc_pd(a, b);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testnzc_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 6., 7., 8.);
+         let r = _mm256_testnzc_pd(a, b);
+         assert_eq!(r, 0);
+         let a = _mm256_setr_pd(1., -1., -1., -1.);
+         let b = _mm256_setr_pd(-1., -1., 1., 1.);
+         let r = _mm256_testnzc_pd(a, b);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_testz_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 6.);
+         let r = _mm_testz_pd(a, b);
+         assert_eq!(r, 1);
+         let a = _mm_set1_pd(-1.);
+         let r = _mm_testz_pd(a, a);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_testc_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 6.);
+         let r = _mm_testc_pd(a, b);
+         assert_eq!(r, 1);
+         let a = _mm_set1_pd(1.);
+         let b = _mm_set1_pd(-1.);
+         let r = _mm_testc_pd(a, b);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_testnzc_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 6.);
+         let r = _mm_testnzc_pd(a, b);
+         assert_eq!(r, 0);
+         let a = _mm_setr_pd(1., -1.);
+         let b = _mm_setr_pd(-1., -1.);
+         let r = _mm_testnzc_pd(a, b);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testz_ps() {
+         let a = _mm256_set1_ps(1.);
+         let r = _mm256_testz_ps(a, a);
+         assert_eq!(r, 1);
+         let a = _mm256_set1_ps(-1.);
+         let r = _mm256_testz_ps(a, a);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testc_ps() {
+         let a = _mm256_set1_ps(1.);
+         let r = _mm256_testc_ps(a, a);
+         assert_eq!(r, 1);
+         let b = _mm256_set1_ps(-1.);
+         let r = _mm256_testc_ps(a, b);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_testnzc_ps() {
+         let a = _mm256_set1_ps(1.);
+         let r = _mm256_testnzc_ps(a, a);
+         assert_eq!(r, 0);
+         let a = _mm256_setr_ps(1., -1., -1., -1., -1., -1., -1., -1.);
+         let b = _mm256_setr_ps(-1., -1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm256_testnzc_ps(a, b);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_testz_ps() {
+         let a = _mm_set1_ps(1.);
+         let r = _mm_testz_ps(a, a);
+         assert_eq!(r, 1);
+         let a = _mm_set1_ps(-1.);
+         let r = _mm_testz_ps(a, a);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_testc_ps() {
+         let a = _mm_set1_ps(1.);
+         let r = _mm_testc_ps(a, a);
+         assert_eq!(r, 1);
+         let b = _mm_set1_ps(-1.);
+         let r = _mm_testc_ps(a, b);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm_testnzc_ps() {
+         let a = _mm_set1_ps(1.);
+         let r = _mm_testnzc_ps(a, a);
+         assert_eq!(r, 0);
+         let a = _mm_setr_ps(1., -1., -1., -1.);
+         let b = _mm_setr_ps(-1., -1., 1., 1.);
+         let r = _mm_testnzc_ps(a, b);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_movemask_pd() {
+         let a = _mm256_setr_pd(1., -2., 3., -4.);
+         let r = _mm256_movemask_pd(a);
+         assert_eq!(r, 0xA);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_movemask_ps() {
+         let a = _mm256_setr_ps(1., -2., 3., -4., 1., -2., 3., -4.);
+         let r = _mm256_movemask_ps(a);
+         assert_eq!(r, 0xAA);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setzero_pd() {
+         let r = _mm256_setzero_pd();
+         assert_eq_m256d(r, _mm256_set1_pd(0.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setzero_ps() {
+         let r = _mm256_setzero_ps();
+         assert_eq_m256(r, _mm256_set1_ps(0.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setzero_si256() {
+         let r = _mm256_setzero_si256();
+         assert_eq_m256i(r, _mm256_set1_epi8(0));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_pd() {
+         let r = _mm256_set_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, _mm256_setr_pd(4., 3., 2., 1.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_ps() {
+         let r = _mm256_set_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m256(r, _mm256_setr_ps(8., 7., 6., 5., 4., 3., 2., 1.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_epi8() {
+         #[rustfmt::skip]
+         let r = _mm256_set_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             32, 31, 30, 29, 28, 27, 26, 25,
+             24, 23, 22, 21, 20, 19, 18, 17,
+             16, 15, 14, 13, 12, 11, 10, 9,
+             8, 7, 6, 5, 4, 3, 2, 1
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_epi16() {
+         #[rustfmt::skip]
+         let r = _mm256_set_epi16(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             16, 15, 14, 13, 12, 11, 10, 9, 8,
+             7, 6, 5, 4, 3, 2, 1,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_epi32() {
+         let r = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         assert_eq_m256i(r, _mm256_setr_epi32(8, 7, 6, 5, 4, 3, 2, 1));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_epi64x() {
+         let r = _mm256_set_epi64x(1, 2, 3, 4);
+         assert_eq_m256i(r, _mm256_setr_epi64x(4, 3, 2, 1));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_pd() {
+         let r = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, _mm256_setr_pd(1., 2., 3., 4.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_ps() {
+         let r = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m256(r, _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_epi8() {
+         #[rustfmt::skip]
+         let r = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32
+         );
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_epi16() {
+         #[rustfmt::skip]
+         let r = _mm256_setr_epi16(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_epi32() {
+         let r = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         assert_eq_m256i(r, _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_epi64x() {
+         let r = _mm256_setr_epi64x(1, 2, 3, 4);
+         assert_eq_m256i(r, _mm256_setr_epi64x(1, 2, 3, 4));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set1_pd() {
+         let r = _mm256_set1_pd(1.);
+         assert_eq_m256d(r, _mm256_set1_pd(1.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set1_ps() {
+         let r = _mm256_set1_ps(1.);
+         assert_eq_m256(r, _mm256_set1_ps(1.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set1_epi8() {
+         let r = _mm256_set1_epi8(1);
+         assert_eq_m256i(r, _mm256_set1_epi8(1));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set1_epi16() {
+         let r = _mm256_set1_epi16(1);
+         assert_eq_m256i(r, _mm256_set1_epi16(1));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set1_epi32() {
+         let r = _mm256_set1_epi32(1);
+         assert_eq_m256i(r, _mm256_set1_epi32(1));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set1_epi64x() {
+         let r = _mm256_set1_epi64x(1);
+         assert_eq_m256i(r, _mm256_set1_epi64x(1));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castpd_ps() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let r = _mm256_castpd_ps(a);
+         let e = _mm256_setr_ps(0., 1.875, 0., 2., 0., 2.125, 0., 2.25);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castps_pd() {
+         let a = _mm256_setr_ps(0., 1.875, 0., 2., 0., 2.125, 0., 2.25);
+         let r = _mm256_castps_pd(a);
+         let e = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castps_si256() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_castps_si256(a);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             0, 0, -128, 63, 0, 0, 0, 64,
+             0, 0, 64, 64, 0, 0, -128, 64,
+             0, 0, -96, 64, 0, 0, -64, 64,
+             0, 0, -32, 64, 0, 0, 0, 65,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castsi256_ps() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             0, 0, -128, 63, 0, 0, 0, 64,
+             0, 0, 64, 64, 0, 0, -128, 64,
+             0, 0, -96, 64, 0, 0, -64, 64,
+             0, 0, -32, 64, 0, 0, 0, 65,
+         );
+         let r = _mm256_castsi256_ps(a);
+         let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castpd_si256() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let r = _mm256_castpd_si256(a);
+         assert_eq_m256d(transmute(r), a);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castsi256_pd() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let r = _mm256_castsi256_pd(a);
+         assert_eq_m256d(r, transmute(a));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castps256_ps128() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_castps256_ps128(a);
+         assert_eq_m128(r, _mm_setr_ps(1., 2., 3., 4.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castpd256_pd128() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let r = _mm256_castpd256_pd128(a);
+         assert_eq_m128d(r, _mm_setr_pd(1., 2.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_castsi256_si128() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let r = _mm256_castsi256_si128(a);
+         assert_eq_m128i(r, _mm_setr_epi64x(1, 2));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_zextps128_ps256() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let r = _mm256_zextps128_ps256(a);
+         let e = _mm256_setr_ps(1., 2., 3., 4., 0., 0., 0., 0.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_zextsi128_si256() {
+         let a = _mm_setr_epi64x(1, 2);
+         let r = _mm256_zextsi128_si256(a);
+         let e = _mm256_setr_epi64x(1, 2, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_zextpd128_pd256() {
+         let a = _mm_setr_pd(1., 2.);
+         let r = _mm256_zextpd128_pd256(a);
+         let e = _mm256_setr_pd(1., 2., 0., 0.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_m128() {
+         let hi = _mm_setr_ps(5., 6., 7., 8.);
+         let lo = _mm_setr_ps(1., 2., 3., 4.);
+         let r = _mm256_set_m128(hi, lo);
+         let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_m128d() {
+         let hi = _mm_setr_pd(3., 4.);
+         let lo = _mm_setr_pd(1., 2.);
+         let r = _mm256_set_m128d(hi, lo);
+         let e = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_set_m128i() {
+         #[rustfmt::skip]
+         let hi = _mm_setr_epi8(
+             17, 18, 19, 20,
+             21, 22, 23, 24,
+             25, 26, 27, 28,
+             29, 30, 31, 32,
+         );
+         #[rustfmt::skip]
+         let lo = _mm_setr_epi8(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16,
+         );
+         let r = _mm256_set_m128i(hi, lo);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_m128() {
+         let lo = _mm_setr_ps(1., 2., 3., 4.);
+         let hi = _mm_setr_ps(5., 6., 7., 8.);
+         let r = _mm256_setr_m128(lo, hi);
+         let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_m128d() {
+         let lo = _mm_setr_pd(1., 2.);
+         let hi = _mm_setr_pd(3., 4.);
+         let r = _mm256_setr_m128d(lo, hi);
+         let e = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_setr_m128i() {
+         #[rustfmt::skip]
+         let lo = _mm_setr_epi8(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16,
+         );
+         #[rustfmt::skip]
+         let hi = _mm_setr_epi8(
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm256_setr_m128i(lo, hi);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_loadu2_m128() {
+         let hi = &[5., 6., 7., 8.];
+         let hiaddr = hi.as_ptr();
+         let lo = &[1., 2., 3., 4.];
+         let loaddr = lo.as_ptr();
+         let r = _mm256_loadu2_m128(hiaddr, loaddr);
+         let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_loadu2_m128d() {
+         let hi = &[3., 4.];
+         let hiaddr = hi.as_ptr();
+         let lo = &[1., 2.];
+         let loaddr = lo.as_ptr();
+         let r = _mm256_loadu2_m128d(hiaddr, loaddr);
+         let e = _mm256_setr_pd(1., 2., 3., 4.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_loadu2_m128i() {
+         #[rustfmt::skip]
+         let hi = _mm_setr_epi8(
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         #[rustfmt::skip]
+         let lo = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm256_loadu2_m128i(&hi as *const _ as *const _, &lo as *const _ as *const _);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_storeu2_m128() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let mut hi = _mm_undefined_ps();
+         let mut lo = _mm_undefined_ps();
+         _mm256_storeu2_m128(
+             &mut hi as *mut _ as *mut f32,
+             &mut lo as *mut _ as *mut f32,
+             a,
+         );
+         assert_eq_m128(hi, _mm_setr_ps(5., 6., 7., 8.));
+         assert_eq_m128(lo, _mm_setr_ps(1., 2., 3., 4.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_storeu2_m128d() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let mut hi = _mm_undefined_pd();
+         let mut lo = _mm_undefined_pd();
+         _mm256_storeu2_m128d(
+             &mut hi as *mut _ as *mut f64,
+             &mut lo as *mut _ as *mut f64,
+             a,
+         );
+         assert_eq_m128d(hi, _mm_setr_pd(3., 4.));
+         assert_eq_m128d(lo, _mm_setr_pd(1., 2.));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_storeu2_m128i() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let mut hi = _mm_undefined_si128();
+         let mut lo = _mm_undefined_si128();
+         _mm256_storeu2_m128i(&mut hi as *mut _, &mut lo as *mut _, a);
+         #[rustfmt::skip]
+         let e_hi = _mm_setr_epi8(
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32
+         );
+         #[rustfmt::skip]
+         let e_lo = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16
+         );
+ 
+         assert_eq_m128i(hi, e_hi);
+         assert_eq_m128i(lo, e_lo);
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_cvtss_f32() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm256_cvtss_f32(a);
+         assert_eq!(r, 1.);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx2.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx2.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx2.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,6172 ----
+ //! Advanced Vector Extensions 2 (AVX)
+ //!
+ //! AVX2 expands most AVX commands to 256-bit wide vector registers and
+ //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //!   Instruction Set Reference, A-Z][intel64_ref].
+ //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ //!   System Instructions][amd64_ref].
+ //!
+ //! Wikipedia's [AVX][wiki_avx] and [FMA][wiki_fma] pages provide a quick
+ //! overview of the instructions available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wiki_avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
+ //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Computes the absolute values of packed 32-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpabsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_abs_epi32(a: __m256i) -> __m256i {
+     transmute(pabsd(a.as_i32x8()))
+ }
+ 
+ /// Computes the absolute values of packed 16-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpabsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_abs_epi16(a: __m256i) -> __m256i {
+     transmute(pabsw(a.as_i16x16()))
+ }
+ 
+ /// Computes the absolute values of packed 8-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpabsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_abs_epi8(a: __m256i) -> __m256i {
+     transmute(pabsb(a.as_i8x32()))
+ }
+ 
+ /// Adds packed 64-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_add_epi64(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_add(a.as_i64x4(), b.as_i64x4()))
+ }
+ 
+ /// Adds packed 32-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_add_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_add(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Adds packed 16-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_add_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_add(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Adds packed 8-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_add_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_add_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_add(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Adds packed 8-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_adds_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_adds_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_add(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Adds packed 16-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_adds_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_adds_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_add(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Adds packed unsigned 8-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_adds_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddusb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_adds_epu8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_add(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Adds packed unsigned 16-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_adds_epu16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpaddusw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_adds_epu16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_add(a.as_u16x16(), b.as_u16x16()))
+ }
+ 
+ /// Concatenates pairs of 16-byte blocks in `a` and `b` into a 32-byte temporary
+ /// result, shifts the result right by `n` bytes, and returns the low 16 bytes.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_alignr_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpalignr, n = 7))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_alignr_epi8(a: __m256i, b: __m256i, n: i32) -> __m256i {
+     let n = n as u32;
+     // If `palignr` is shifting the pair of vectors more than the size of two
+     // lanes, emit zero.
+     if n > 32 {
+         return _mm256_set1_epi8(0);
+     }
+     // If `palignr` is shifting the pair of input vectors more than one lane,
+     // but less than two lanes, convert to shifting in zeroes.
+     let (a, b, n) = if n > 16 {
+         (_mm256_set1_epi8(0), a, n - 16)
+     } else {
+         (a, b, n)
+     };
+ 
+     let a = a.as_i8x32();
+     let b = b.as_i8x32();
+ 
+     let r: i8x32 = match n {
+         0 => simd_shuffle32(
+             b,
+             a,
+             [
+                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
+                 23, 24, 25, 26, 27, 28, 29, 30, 31,
+             ],
+         ),
+         1 => simd_shuffle32(
+             b,
+             a,
+             [
+                 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 17, 18, 19, 20, 21, 22, 23,
+                 24, 25, 26, 27, 28, 29, 30, 31, 48,
+             ],
+         ),
+         2 => simd_shuffle32(
+             b,
+             a,
+             [
+                 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 18, 19, 20, 21, 22, 23, 24,
+                 25, 26, 27, 28, 29, 30, 31, 48, 49,
+             ],
+         ),
+         3 => simd_shuffle32(
+             b,
+             a,
+             [
+                 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 19, 20, 21, 22, 23, 24,
+                 25, 26, 27, 28, 29, 30, 31, 48, 49, 50,
+             ],
+         ),
+         4 => simd_shuffle32(
+             b,
+             a,
+             [
+                 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 20, 21, 22, 23, 24, 25,
+                 26, 27, 28, 29, 30, 31, 48, 49, 50, 51,
+             ],
+         ),
+         5 => simd_shuffle32(
+             b,
+             a,
+             [
+                 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 21, 22, 23, 24, 25, 26,
+                 27, 28, 29, 30, 31, 48, 49, 50, 51, 52,
+             ],
+         ),
+         6 => simd_shuffle32(
+             b,
+             a,
+             [
+                 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 22, 23, 24, 25, 26, 27,
+                 28, 29, 30, 31, 48, 49, 50, 51, 52, 53,
+             ],
+         ),
+         7 => simd_shuffle32(
+             b,
+             a,
+             [
+                 7, 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 23, 24, 25, 26, 27,
+                 28, 29, 30, 31, 48, 49, 50, 51, 52, 53, 54,
+             ],
+         ),
+         8 => simd_shuffle32(
+             b,
+             a,
+             [
+                 8, 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 24, 25, 26, 27, 28,
+                 29, 30, 31, 48, 49, 50, 51, 52, 53, 54, 55,
+             ],
+         ),
+         9 => simd_shuffle32(
+             b,
+             a,
+             [
+                 9, 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 25, 26, 27, 28, 29,
+                 30, 31, 48, 49, 50, 51, 52, 53, 54, 55, 56,
+             ],
+         ),
+         10 => simd_shuffle32(
+             b,
+             a,
+             [
+                 10, 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 26, 27, 28, 29, 30,
+                 31, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
+             ],
+         ),
+         11 => simd_shuffle32(
+             b,
+             a,
+             [
+                 11, 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 27, 28, 29, 30, 31,
+                 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
+             ],
+         ),
+         12 => simd_shuffle32(
+             b,
+             a,
+             [
+                 12, 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 28, 29, 30, 31, 48,
+                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
+             ],
+         ),
+         13 => simd_shuffle32(
+             b,
+             a,
+             [
+                 13, 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 29, 30, 31, 48, 49,
+                 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+             ],
+         ),
+         14 => simd_shuffle32(
+             b,
+             a,
+             [
+                 14, 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 30, 31, 48, 49, 50,
+                 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+             ],
+         ),
+         15 => simd_shuffle32(
+             b,
+             a,
+             [
+                 15, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 31, 48, 49, 50, 51,
+                 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,
+             ],
+         ),
+         _ => b,
+     };
+     transmute(r)
+ }
+ 
+ /// Computes the bitwise AND of 256 bits (representing integer data)
+ /// in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_and_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vandps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_and_si256(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_and(a.as_i64x4(), b.as_i64x4()))
+ }
+ 
+ /// Computes the bitwise NOT of 256 bits (representing integer data)
+ /// in `a` and then AND with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_andnot_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vandnps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_andnot_si256(a: __m256i, b: __m256i) -> __m256i {
+     let all_ones = _mm256_set1_epi8(-1);
+     transmute(simd_and(
+         simd_xor(a.as_i64x4(), all_ones.as_i64x4()),
+         b.as_i64x4(),
+     ))
+ }
+ 
+ /// Averages packed unsigned 16-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_avg_epu16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpavgw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_avg_epu16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pavgw(a.as_u16x16(), b.as_u16x16()))
+ }
+ 
+ /// Averages packed unsigned 8-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_avg_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpavgb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_avg_epu8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pavgb(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Blends packed 32-bit integers from `a` and `b` using control mask `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blend_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vblendps, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blend_epi32(a: __m128i, b: __m128i, imm8: i32) -> __m128i {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i32x4();
+     let b = b.as_i32x4();
+     macro_rules! blend2 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle4(a, b, [$a, $b, $c, $d]);
+         };
+     }
+     macro_rules! blend1 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => blend2!($a, $b, 2, 3),
+                 0b01 => blend2!($a, $b, 6, 3),
+                 0b10 => blend2!($a, $b, 2, 7),
+                 _ => blend2!($a, $b, 6, 7),
+             }
+         };
+     }
+     let r: i32x4 = match imm8 & 0b11 {
+         0b00 => blend1!(0, 1),
+         0b01 => blend1!(4, 1),
+         0b10 => blend1!(0, 5),
+         _ => blend1!(4, 5),
+     };
+     transmute(r)
+ }
+ 
+ /// Blends packed 32-bit integers from `a` and `b` using control mask `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blend_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vblendps, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blend_epi32(a: __m256i, b: __m256i, imm8: i32) -> __m256i {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i32x8();
+     let b = b.as_i32x8();
+     macro_rules! blend4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! blend3 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => blend4!($a, $b, $c, $d, $e, $f, 6, 7),
+                 0b01 => blend4!($a, $b, $c, $d, $e, $f, 14, 7),
+                 0b10 => blend4!($a, $b, $c, $d, $e, $f, 6, 15),
+                 _ => blend4!($a, $b, $c, $d, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! blend2 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => blend3!($a, $b, $c, $d, 4, 5),
+                 0b01 => blend3!($a, $b, $c, $d, 12, 5),
+                 0b10 => blend3!($a, $b, $c, $d, 4, 13),
+                 _ => blend3!($a, $b, $c, $d, 12, 13),
+             }
+         };
+     }
+     macro_rules! blend1 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => blend2!($a, $b, 2, 3),
+                 0b01 => blend2!($a, $b, 10, 3),
+                 0b10 => blend2!($a, $b, 2, 11),
+                 _ => blend2!($a, $b, 10, 11),
+             }
+         };
+     }
+     let r: i32x8 = match imm8 & 0b11 {
+         0b00 => blend1!(0, 1),
+         0b01 => blend1!(8, 1),
+         0b10 => blend1!(0, 9),
+         _ => blend1!(8, 9),
+     };
+     transmute(r)
+ }
+ 
+ /// Blends packed 16-bit integers from `a` and `b` using control mask `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blend_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpblendw, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blend_epi16(a: __m256i, b: __m256i, imm8: i32) -> __m256i {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i16x16();
+     let b = b.as_i16x16();
+     macro_rules! blend4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             )
+         };
+     }
+     macro_rules! blend3 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $a2:expr,
+             $b2:expr,
+             $c2:expr,
+             $d2:expr,
+             $e2:expr,
+             $f2:expr
+         ) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => blend4!($a, $b, $c, $d, $e, $f, 6, 7, $a2, $b2, $c2, $d2, $e2, $f2, 14, 15),
+                 0b01 => {
+                     blend4!($a, $b, $c, $d, $e, $f, 22, 7, $a2, $b2, $c2, $d2, $e2, $f2, 30, 15)
+                 }
+                 0b10 => {
+                     blend4!($a, $b, $c, $d, $e, $f, 6, 23, $a2, $b2, $c2, $d2, $e2, $f2, 14, 31)
+                 }
+                 _ => blend4!($a, $b, $c, $d, $e, $f, 22, 23, $a2, $b2, $c2, $d2, $e2, $f2, 30, 31),
+             }
+         };
+     }
+     macro_rules! blend2 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $a2:expr,
+             $b2:expr,
+             $c2:expr,
+             $d2:expr
+         ) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => blend3!($a, $b, $c, $d, 4, 5, $a2, $b2, $c2, $d2, 12, 13),
+                 0b01 => blend3!($a, $b, $c, $d, 20, 5, $a2, $b2, $c2, $d2, 28, 13),
+                 0b10 => blend3!($a, $b, $c, $d, 4, 21, $a2, $b2, $c2, $d2, 12, 29),
+                 _ => blend3!($a, $b, $c, $d, 20, 21, $a2, $b2, $c2, $d2, 28, 29),
+             }
+         };
+     }
+     macro_rules! blend1 {
+         ($a1:expr, $b1:expr, $a2:expr, $b2:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => blend2!($a1, $b1, 2, 3, $a2, $b2, 10, 11),
+                 0b01 => blend2!($a1, $b1, 18, 3, $a2, $b2, 26, 11),
+                 0b10 => blend2!($a1, $b1, 2, 19, $a2, $b2, 10, 27),
+                 _ => blend2!($a1, $b1, 18, 19, $a2, $b2, 26, 27),
+             }
+         };
+     }
+     let r: i16x16 = match imm8 & 0b11 {
+         0b00 => blend1!(0, 1, 8, 9),
+         0b01 => blend1!(16, 1, 24, 9),
+         0b10 => blend1!(0, 17, 8, 25),
+         _ => blend1!(16, 17, 24, 25),
+     };
+     transmute(r)
+ }
+ 
+ /// Blends packed 8-bit integers from `a` and `b` using `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_blendv_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpblendvb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_blendv_epi8(a: __m256i, b: __m256i, mask: __m256i) -> __m256i {
+     transmute(pblendvb(a.as_i8x32(), b.as_i8x32(), mask.as_i8x32()))
+ }
+ 
+ /// Broadcasts the low packed 8-bit integer from `a` to all elements of
+ /// the 128-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcastb_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpbroadcastb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_broadcastb_epi8(a: __m128i) -> __m128i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle16(a.as_i8x16(), zero.as_i8x16(), [0_u32; 16]);
+     transmute::<i8x16, _>(ret)
+ }
+ 
+ /// Broadcasts the low packed 8-bit integer from `a` to all elements of
+ /// the 256-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastb_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpbroadcastb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastb_epi8(a: __m128i) -> __m256i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle32(a.as_i8x16(), zero.as_i8x16(), [0_u32; 32]);
+     transmute::<i8x32, _>(ret)
+ }
+ 
+ // N.B., `simd_shuffle4` with integer data types for `a` and `b` is
+ // often compiled to `vbroadcastss`.
+ /// Broadcasts the low packed 32-bit integer from `a` to all elements of
+ /// the 128-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcastd_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_broadcastd_epi32(a: __m128i) -> __m128i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle4(a.as_i32x4(), zero.as_i32x4(), [0_u32; 4]);
+     transmute::<i32x4, _>(ret)
+ }
+ 
+ // N.B., `simd_shuffle4`` with integer data types for `a` and `b` is
+ // often compiled to `vbroadcastss`.
+ /// Broadcasts the low packed 32-bit integer from `a` to all elements of
+ /// the 256-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastd_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastd_epi32(a: __m128i) -> __m256i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle8(a.as_i32x4(), zero.as_i32x4(), [0_u32; 8]);
+     transmute::<i32x8, _>(ret)
+ }
+ 
+ /// Broadcasts the low packed 64-bit integer from `a` to all elements of
+ /// the 128-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcastq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ // FIXME: https://github.com/rust-lang/stdarch/issues/791
+ #[cfg_attr(test, assert_instr(vmovddup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_broadcastq_epi64(a: __m128i) -> __m128i {
+     let ret = simd_shuffle2(a.as_i64x2(), a.as_i64x2(), [0_u32; 2]);
+     transmute::<i64x2, _>(ret)
+ }
+ 
+ /// Broadcasts the low packed 64-bit integer from `a` to all elements of
+ /// the 256-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vbroadcastsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastq_epi64(a: __m128i) -> __m256i {
+     let ret = simd_shuffle4(a.as_i64x2(), a.as_i64x2(), [0_u32; 4]);
+     transmute::<i64x4, _>(ret)
+ }
+ 
+ /// Broadcasts the low double-precision (64-bit) floating-point element
+ /// from `a` to all elements of the 128-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcastsd_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vmovddup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_broadcastsd_pd(a: __m128d) -> __m128d {
+     simd_shuffle2(a, _mm_setzero_pd(), [0_u32; 2])
+ }
+ 
+ /// Broadcasts the low double-precision (64-bit) floating-point element
+ /// from `a` to all elements of the 256-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastsd_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vbroadcastsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastsd_pd(a: __m128d) -> __m256d {
+     simd_shuffle4(a, _mm_setzero_pd(), [0_u32; 4])
+ }
+ 
+ // N.B., `broadcastsi128_si256` is often compiled to `vinsertf128` or
+ // `vbroadcastf128`.
+ /// Broadcasts 128 bits of integer data from a to all 128-bit lanes in
+ /// the 256-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastsi128_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastsi128_si256(a: __m128i) -> __m256i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle4(a.as_i64x2(), zero.as_i64x2(), [0, 1, 0, 1]);
+     transmute::<i64x4, _>(ret)
+ }
+ 
+ /// Broadcasts the low single-precision (32-bit) floating-point element
+ /// from `a` to all elements of the 128-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcastss_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_broadcastss_ps(a: __m128) -> __m128 {
+     simd_shuffle4(a, _mm_setzero_ps(), [0_u32; 4])
+ }
+ 
+ /// Broadcasts the low single-precision (32-bit) floating-point element
+ /// from `a` to all elements of the 256-bit returned value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastss_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastss_ps(a: __m128) -> __m256 {
+     simd_shuffle8(a, _mm_setzero_ps(), [0_u32; 8])
+ }
+ 
+ /// Broadcasts the low packed 16-bit integer from a to all elements of
+ /// the 128-bit returned value
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_broadcastw_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpbroadcastw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_broadcastw_epi16(a: __m128i) -> __m128i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle8(a.as_i16x8(), zero.as_i16x8(), [0_u32; 8]);
+     transmute::<i16x8, _>(ret)
+ }
+ 
+ /// Broadcasts the low packed 16-bit integer from a to all elements of
+ /// the 256-bit returned value
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_broadcastw_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpbroadcastw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_broadcastw_epi16(a: __m128i) -> __m256i {
+     let zero = _mm_setzero_si128();
+     let ret = simd_shuffle16(a.as_i16x8(), zero.as_i16x8(), [0_u32; 16]);
+     transmute::<i16x16, _>(ret)
+ }
+ 
+ /// Compares packed 64-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpeq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpeqq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpeq_epi64(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i64x4, _>(simd_eq(a.as_i64x4(), b.as_i64x4()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpeq_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpeqd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpeq_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i32x8, _>(simd_eq(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpeq_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpeqw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpeq_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i16x16, _>(simd_eq(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpeq_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpeqb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpeq_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i8x32, _>(simd_eq(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Compares packed 64-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpgt_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpgtq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpgt_epi64(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i64x4, _>(simd_gt(a.as_i64x4(), b.as_i64x4()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpgt_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpgtd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpgt_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i32x8, _>(simd_gt(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpgt_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpgtw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpgt_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i16x16, _>(simd_gt(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmpgt_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpcmpgtb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cmpgt_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute::<i8x32, _>(simd_gt(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Sign-extend 16-bit integers to 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi16_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovsxwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi16_epi32(a: __m128i) -> __m256i {
+     transmute::<i32x8, _>(simd_cast(a.as_i16x8()))
+ }
+ 
+ /// Sign-extend 16-bit integers to 64-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi16_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovsxwq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi16_epi64(a: __m128i) -> __m256i {
+     let a = a.as_i16x8();
+     let v64: i16x4 = simd_shuffle4(a, a, [0, 1, 2, 3]);
+     transmute::<i64x4, _>(simd_cast(v64))
+ }
+ 
+ /// Sign-extend 32-bit integers to 64-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi32_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovsxdq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi32_epi64(a: __m128i) -> __m256i {
+     transmute::<i64x4, _>(simd_cast(a.as_i32x4()))
+ }
+ 
+ /// Sign-extend 8-bit integers to 16-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi8_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovsxbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi8_epi16(a: __m128i) -> __m256i {
+     transmute::<i16x16, _>(simd_cast(a.as_i8x16()))
+ }
+ 
+ /// Sign-extend 8-bit integers to 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi8_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovsxbd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi8_epi32(a: __m128i) -> __m256i {
+     let a = a.as_i8x16();
+     let v64: i8x8 = simd_shuffle8(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
+     transmute::<i32x8, _>(simd_cast(v64))
+ }
+ 
+ /// Sign-extend 8-bit integers to 64-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepi8_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovsxbq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepi8_epi64(a: __m128i) -> __m256i {
+     let a = a.as_i8x16();
+     let v32: i8x4 = simd_shuffle4(a, a, [0, 1, 2, 3]);
+     transmute::<i64x4, _>(simd_cast(v32))
+ }
+ 
+ /// Zeroes extend packed unsigned 16-bit integers in `a` to packed 32-bit
+ /// integers, and stores the results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu16_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovzxwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepu16_epi32(a: __m128i) -> __m256i {
+     transmute::<i32x8, _>(simd_cast(a.as_u16x8()))
+ }
+ 
+ /// Zero-extend the lower four unsigned 16-bit integers in `a` to 64-bit
+ /// integers. The upper four elements of `a` are unused.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu16_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovzxwq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepu16_epi64(a: __m128i) -> __m256i {
+     let a = a.as_u16x8();
+     let v64: u16x4 = simd_shuffle4(a, a, [0, 1, 2, 3]);
+     transmute::<i64x4, _>(simd_cast(v64))
+ }
+ 
+ /// Zero-extend unsigned 32-bit integers in `a` to 64-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu32_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovzxdq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepu32_epi64(a: __m128i) -> __m256i {
+     transmute::<i64x4, _>(simd_cast(a.as_u32x4()))
+ }
+ 
+ /// Zero-extend unsigned 8-bit integers in `a` to 16-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu8_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovzxbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepu8_epi16(a: __m128i) -> __m256i {
+     transmute::<i16x16, _>(simd_cast(a.as_u8x16()))
+ }
+ 
+ /// Zero-extend the lower eight unsigned 8-bit integers in `a` to 32-bit
+ /// integers. The upper eight elements of `a` are unused.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu8_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovzxbd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepu8_epi32(a: __m128i) -> __m256i {
+     let a = a.as_u8x16();
+     let v64: u8x8 = simd_shuffle8(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
+     transmute::<i32x8, _>(simd_cast(v64))
+ }
+ 
+ /// Zero-extend the lower four unsigned 8-bit integers in `a` to 64-bit
+ /// integers. The upper twelve elements of `a` are unused.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtepu8_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovzxbq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtepu8_epi64(a: __m128i) -> __m256i {
+     let a = a.as_u8x16();
+     let v32: u8x4 = simd_shuffle4(a, a, [0, 1, 2, 3]);
+     transmute::<i64x4, _>(simd_cast(v32))
+ }
+ 
+ /// Extracts 128 bits (of integer data) from `a` selected with `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extracti128_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vextractf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extracti128_si256(a: __m256i, imm8: i32) -> __m128i {
+     let a = a.as_i64x4();
+     let b = _mm256_undefined_si256().as_i64x4();
+     let dst: i64x2 = match imm8 & 0b01 {
+         0 => simd_shuffle2(a, b, [0, 1]),
+         _ => simd_shuffle2(a, b, [2, 3]),
+     };
+     transmute(dst)
+ }
+ 
+ /// Horizontally adds adjacent pairs of 16-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vphaddw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hadd_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(phaddw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Horizontally adds adjacent pairs of 32-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vphaddd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(phaddd(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Horizontally adds adjacent pairs of 16-bit integers in `a` and `b`
+ /// using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadds_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vphaddsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(phaddsw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hsub_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vphsubw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hsub_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(phsubw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Horizontally subtract adjacent pairs of 32-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hsub_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vphsubd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(phsubd(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`
+ /// using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hsubs_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vphsubsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_hsubs_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(phsubsw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i32gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i32gather_epi32(slice: *const i32, offsets: __m128i, scale: i32) -> __m128i {
+     let zero = _mm_setzero_si128().as_i32x4();
+     let neg_one = _mm_set1_epi32(-1).as_i32x4();
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i32gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i32gather_epi32(
+     src: __m128i,
+     slice: *const i32,
+     offsets: __m128i,
+     mask: __m128i,
+     scale: i32,
+ ) -> __m128i {
+     let src = src.as_i32x4();
+     let mask = mask.as_i32x4();
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i32gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i32gather_epi32(slice: *const i32, offsets: __m256i, scale: i32) -> __m256i {
+     let zero = _mm256_setzero_si256().as_i32x8();
+     let neg_one = _mm256_set1_epi32(-1).as_i32x8();
+     let offsets = offsets.as_i32x8();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i32gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i32gather_epi32(
+     src: __m256i,
+     slice: *const i32,
+     offsets: __m256i,
+     mask: __m256i,
+     scale: i32,
+ ) -> __m256i {
+     let src = src.as_i32x8();
+     let mask = mask.as_i32x8();
+     let offsets = offsets.as_i32x8();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i32gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdps, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i32gather_ps(slice: *const f32, offsets: __m128i, scale: i32) -> __m128 {
+     let zero = _mm_setzero_ps();
+     let neg_one = _mm_set1_ps(-1.0);
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdps(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i32gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i32gather_ps(
+     src: __m128,
+     slice: *const f32,
+     offsets: __m128i,
+     mask: __m128,
+     scale: i32,
+ ) -> __m128 {
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdps(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i32gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdps, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i32gather_ps(slice: *const f32, offsets: __m256i, scale: i32) -> __m256 {
+     let zero = _mm256_setzero_ps();
+     let neg_one = _mm256_set1_ps(-1.0);
+     let offsets = offsets.as_i32x8();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdps(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i32gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i32gather_ps(
+     src: __m256,
+     slice: *const f32,
+     offsets: __m256i,
+     mask: __m256,
+     scale: i32,
+ ) -> __m256 {
+     let offsets = offsets.as_i32x8();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdps(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i32gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdq, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i32gather_epi64(slice: *const i64, offsets: __m128i, scale: i32) -> __m128i {
+     let zero = _mm_setzero_si128().as_i64x2();
+     let neg_one = _mm_set1_epi64x(-1).as_i64x2();
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdq(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i32gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i32gather_epi64(
+     src: __m128i,
+     slice: *const i64,
+     offsets: __m128i,
+     mask: __m128i,
+     scale: i32,
+ ) -> __m128i {
+     let src = src.as_i64x2();
+     let mask = mask.as_i64x2();
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdq(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i32gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdq, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i32gather_epi64(slice: *const i64, offsets: __m128i, scale: i32) -> __m256i {
+     let zero = _mm256_setzero_si256().as_i64x4();
+     let neg_one = _mm256_set1_epi64x(-1).as_i64x4();
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdq(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i32gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherdq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i32gather_epi64(
+     src: __m256i,
+     slice: *const i64,
+     offsets: __m128i,
+     mask: __m256i,
+     scale: i32,
+ ) -> __m256i {
+     let src = src.as_i64x4();
+     let mask = mask.as_i64x4();
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdq(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i32gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdpd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i32gather_pd(slice: *const f64, offsets: __m128i, scale: i32) -> __m128d {
+     let zero = _mm_setzero_pd();
+     let neg_one = _mm_set1_pd(-1.0);
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdpd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i32gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i32gather_pd(
+     src: __m128d,
+     slice: *const f64,
+     offsets: __m128i,
+     mask: __m128d,
+     scale: i32,
+ ) -> __m128d {
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherdpd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i32gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdpd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i32gather_pd(slice: *const f64, offsets: __m128i, scale: i32) -> __m256d {
+     let zero = _mm256_setzero_pd();
+     let neg_one = _mm256_set1_pd(-1.0);
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdpd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i32gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherdpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i32gather_pd(
+     src: __m256d,
+     slice: *const f64,
+     offsets: __m128i,
+     mask: __m256d,
+     scale: i32,
+ ) -> __m256d {
+     let offsets = offsets.as_i32x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdpd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i64gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i64gather_epi32(slice: *const i32, offsets: __m128i, scale: i32) -> __m128i {
+     let zero = _mm_setzero_si128().as_i32x4();
+     let neg_one = _mm_set1_epi64x(-1).as_i32x4();
+     let offsets = offsets.as_i64x2();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i64gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i64gather_epi32(
+     src: __m128i,
+     slice: *const i32,
+     offsets: __m128i,
+     mask: __m128i,
+     scale: i32,
+ ) -> __m128i {
+     let src = src.as_i32x4();
+     let mask = mask.as_i32x4();
+     let offsets = offsets.as_i64x2();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i64gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i64gather_epi32(slice: *const i32, offsets: __m256i, scale: i32) -> __m128i {
+     let zero = _mm_setzero_si128().as_i32x4();
+     let neg_one = _mm_set1_epi64x(-1).as_i32x4();
+     let offsets = offsets.as_i64x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i64gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i64gather_epi32(
+     src: __m128i,
+     slice: *const i32,
+     offsets: __m256i,
+     mask: __m128i,
+     scale: i32,
+ ) -> __m128i {
+     let src = src.as_i32x4();
+     let mask = mask.as_i32x4();
+     let offsets = offsets.as_i64x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i64gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqps, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i64gather_ps(slice: *const f32, offsets: __m128i, scale: i32) -> __m128 {
+     let zero = _mm_setzero_ps();
+     let neg_one = _mm_set1_ps(-1.0);
+     let offsets = offsets.as_i64x2();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqps(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i64gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i64gather_ps(
+     src: __m128,
+     slice: *const f32,
+     offsets: __m128i,
+     mask: __m128,
+     scale: i32,
+ ) -> __m128 {
+     let offsets = offsets.as_i64x2();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqps(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i64gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqps, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i64gather_ps(slice: *const f32, offsets: __m256i, scale: i32) -> __m128 {
+     let zero = _mm_setzero_ps();
+     let neg_one = _mm_set1_ps(-1.0);
+     let offsets = offsets.as_i64x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqps(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i64gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i64gather_ps(
+     src: __m128,
+     slice: *const f32,
+     offsets: __m256i,
+     mask: __m128,
+     scale: i32,
+ ) -> __m128 {
+     let offsets = offsets.as_i64x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqps(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i64gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i64gather_epi64(slice: *const i64, offsets: __m128i, scale: i32) -> __m128i {
+     let zero = _mm_setzero_si128().as_i64x2();
+     let neg_one = _mm_set1_epi64x(-1).as_i64x2();
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x2();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqq(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i64gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i64gather_epi64(
+     src: __m128i,
+     slice: *const i64,
+     offsets: __m128i,
+     mask: __m128i,
+     scale: i32,
+ ) -> __m128i {
+     let src = src.as_i64x2();
+     let mask = mask.as_i64x2();
+     let offsets = offsets.as_i64x2();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqq(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i64gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i64gather_epi64(slice: *const i64, offsets: __m256i, scale: i32) -> __m256i {
+     let zero = _mm256_setzero_si256().as_i64x4();
+     let neg_one = _mm256_set1_epi64x(-1).as_i64x4();
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqq(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i64gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i64gather_epi64(
+     src: __m256i,
+     slice: *const i64,
+     offsets: __m256i,
+     mask: __m256i,
+     scale: i32,
+ ) -> __m256i {
+     let src = src.as_i64x4();
+     let mask = mask.as_i64x4();
+     let offsets = offsets.as_i64x4();
+     let slice = slice as *const i8;
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqq(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_i64gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_i64gather_pd(slice: *const f64, offsets: __m128i, scale: i32) -> __m128d {
+     let zero = _mm_setzero_pd();
+     let neg_one = _mm_set1_pd(-1.0);
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x2();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqpd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i64gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mask_i64gather_pd(
+     src: __m128d,
+     slice: *const f64,
+     offsets: __m128i,
+     mask: __m128d,
+     scale: i32,
+ ) -> __m128d {
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x2();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pgatherqpd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_i64gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_i64gather_pd(slice: *const f64, offsets: __m256i, scale: i32) -> __m256d {
+     let zero = _mm256_setzero_pd();
+     let neg_one = _mm256_set1_pd(-1.0);
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqpd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Returns values from `slice` at offsets determined by `offsets * scale`,
+ /// where
+ /// `scale` is between 1 and 8. If mask is set, load the value from `src` in
+ /// that position instead.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i64gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mask_i64gather_pd(
+     src: __m256d,
+     slice: *const f64,
+     offsets: __m256i,
+     mask: __m256d,
+     scale: i32,
+ ) -> __m256d {
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqpd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     constify_imm8!(scale, call)
+ }
+ 
+ /// Copies `a` to `dst`, then insert 128 bits (of integer data) from `b` at the
+ /// location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_inserti128_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vinsertf128, imm8 = 1)
+ )]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_inserti128_si256(a: __m256i, b: __m128i, imm8: i32) -> __m256i {
+     let a = a.as_i64x4();
+     let b = _mm256_castsi128_si256(b).as_i64x4();
+     let dst: i64x4 = match imm8 & 0b01 {
+         0 => simd_shuffle4(a, b, [4, 5, 2, 3]),
+         _ => simd_shuffle4(a, b, [0, 1, 4, 5]),
+     };
+     transmute(dst)
+ }
+ 
+ /// Multiplies packed signed 16-bit integers in `a` and `b`, producing
+ /// intermediate signed 32-bit integers. Horizontally add adjacent pairs
+ /// of intermediate 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_madd_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaddwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_madd_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaddwd(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Vertically multiplies each unsigned 8-bit integer from `a` with the
+ /// corresponding signed 8-bit integer from `b`, producing intermediate
+ /// signed 16-bit integers. Horizontally add adjacent pairs of intermediate
+ /// signed 16-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maddubs_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaddubsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maddubs_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaddubsw(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Loads packed 32-bit integers from memory pointed by `mem_addr` using `mask`
+ /// (elements are zeroed out when the highest bit is not set in the
+ /// corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskload_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskload_epi32(mem_addr: *const i32, mask: __m128i) -> __m128i {
+     transmute(maskloadd(mem_addr as *const i8, mask.as_i32x4()))
+ }
+ 
+ /// Loads packed 32-bit integers from memory pointed by `mem_addr` using `mask`
+ /// (elements are zeroed out when the highest bit is not set in the
+ /// corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskload_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskload_epi32(mem_addr: *const i32, mask: __m256i) -> __m256i {
+     transmute(maskloadd256(mem_addr as *const i8, mask.as_i32x8()))
+ }
+ 
+ /// Loads packed 64-bit integers from memory pointed by `mem_addr` using `mask`
+ /// (elements are zeroed out when the highest bit is not set in the
+ /// corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskload_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskload_epi64(mem_addr: *const i64, mask: __m128i) -> __m128i {
+     transmute(maskloadq(mem_addr as *const i8, mask.as_i64x2()))
+ }
+ 
+ /// Loads packed 64-bit integers from memory pointed by `mem_addr` using `mask`
+ /// (elements are zeroed out when the highest bit is not set in the
+ /// corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskload_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskload_epi64(mem_addr: *const i64, mask: __m256i) -> __m256i {
+     transmute(maskloadq256(mem_addr as *const i8, mask.as_i64x4()))
+ }
+ 
+ /// Stores packed 32-bit integers from `a` into memory pointed by `mem_addr`
+ /// using `mask` (elements are not stored when the highest bit is not set
+ /// in the corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskstore_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskstore_epi32(mem_addr: *mut i32, mask: __m128i, a: __m128i) {
+     maskstored(mem_addr as *mut i8, mask.as_i32x4(), a.as_i32x4())
+ }
+ 
+ /// Stores packed 32-bit integers from `a` into memory pointed by `mem_addr`
+ /// using `mask` (elements are not stored when the highest bit is not set
+ /// in the corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskstore_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskstore_epi32(mem_addr: *mut i32, mask: __m256i, a: __m256i) {
+     maskstored256(mem_addr as *mut i8, mask.as_i32x8(), a.as_i32x8())
+ }
+ 
+ /// Stores packed 64-bit integers from `a` into memory pointed by `mem_addr`
+ /// using `mask` (elements are not stored when the highest bit is not set
+ /// in the corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskstore_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskstore_epi64(mem_addr: *mut i64, mask: __m128i, a: __m128i) {
+     maskstoreq(mem_addr as *mut i8, mask.as_i64x2(), a.as_i64x2())
+ }
+ 
+ /// Stores packed 64-bit integers from `a` into memory pointed by `mem_addr`
+ /// using `mask` (elements are not stored when the highest bit is not set
+ /// in the corresponding element).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskstore_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaskmovq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_maskstore_epi64(mem_addr: *mut i64, mask: __m256i, a: __m256i) {
+     maskstoreq256(mem_addr as *mut i8, mask.as_i64x4(), a.as_i64x4())
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
+ /// maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaxsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaxsw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b`, and returns the packed
+ /// maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaxsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaxsd(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b`, and returns the packed
+ /// maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaxsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaxsb(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns
+ /// the packed maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_epu16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaxuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_epu16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaxuw(a.as_u16x16(), b.as_u16x16()))
+ }
+ 
+ /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns
+ /// the packed maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_epu32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaxud))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_epu32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaxud(a.as_u32x8(), b.as_u32x8()))
+ }
+ 
+ /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns
+ /// the packed maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_max_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmaxub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_max_epu8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmaxub(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
+ /// minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpminsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pminsw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b`, and returns the packed
+ /// minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpminsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pminsd(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b`, and returns the packed
+ /// minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpminsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pminsb(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns
+ /// the packed minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_epu16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpminuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_epu16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pminuw(a.as_u16x16(), b.as_u16x16()))
+ }
+ 
+ /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns
+ /// the packed minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_epu32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpminud))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_epu32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pminud(a.as_u32x8(), b.as_u32x8()))
+ }
+ 
+ /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns
+ /// the packed minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_min_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpminub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_min_epu8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pminub(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Creates mask from the most significant bit of each 8-bit element in `a`,
+ /// return the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_movemask_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmovmskb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_movemask_epi8(a: __m256i) -> i32 {
+     pmovmskb(a.as_i8x32())
+ }
+ 
+ /// Computes the sum of absolute differences (SADs) of quadruplets of unsigned
+ /// 8-bit integers in `a` compared to those in `b`, and stores the 16-bit
+ /// results in dst. Eight SADs are performed for each 128-bit lane using one
+ /// quadruplet from `b` and eight quadruplets from `a`. One quadruplet is
+ /// selected from `b` starting at on the offset specified in `imm8`. Eight
+ /// quadruplets are formed from sequential 8-bit integers selected from `a`
+ /// starting at the offset specified in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mpsadbw_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vmpsadbw, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mpsadbw_epu8(a: __m256i, b: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_u8x32();
+     let b = b.as_u8x32();
+     macro_rules! call {
+         ($imm8:expr) => {
+             mpsadbw(a, b, $imm8)
+         };
+     }
+     let r = constify_imm8!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Multiplies the low 32-bit integers from each packed 64-bit element in
+ /// `a` and `b`
+ ///
+ /// Returns the 64-bit results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mul_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmuldq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mul_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmuldq(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Multiplies the low unsigned 32-bit integers from each packed 64-bit
+ /// element in `a` and `b`
+ ///
+ /// Returns the unsigned 64-bit results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mul_epu32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmuludq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mul_epu32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmuludq(a.as_u32x8(), b.as_u32x8()))
+ }
+ 
+ /// Multiplies the packed 16-bit integers in `a` and `b`, producing
+ /// intermediate 32-bit integers and returning the high 16 bits of the
+ /// intermediate integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mulhi_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmulhw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mulhi_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmulhw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Multiplies the packed unsigned 16-bit integers in `a` and `b`, producing
+ /// intermediate 32-bit integers and returning the high 16 bits of the
+ /// intermediate integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mulhi_epu16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmulhuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mulhi_epu16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmulhuw(a.as_u16x16(), b.as_u16x16()))
+ }
+ 
+ /// Multiplies the packed 16-bit integers in `a` and `b`, producing
+ /// intermediate 32-bit integers, and returns the low 16 bits of the
+ /// intermediate integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mullo_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmullw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mullo_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_mul(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Multiplies the packed 32-bit integers in `a` and `b`, producing
+ /// intermediate 64-bit integers, and returns the low 32 bits of the
+ /// intermediate integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mullo_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmulld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mullo_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_mul(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Multiplies packed 16-bit integers in `a` and `b`, producing
+ /// intermediate signed 32-bit integers. Truncate each intermediate
+ /// integer to the 18 most significant bits, round by adding 1, and
+ /// return bits `[16:1]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mulhrs_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpmulhrsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_mulhrs_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pmulhrsw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Computes the bitwise OR of 256 bits (representing integer data) in `a`
+ /// and `b`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_or_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_or(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+ /// using signed saturation
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_packs_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpacksswb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(packsswb(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+ /// using signed saturation
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_packs_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpackssdw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(packssdw(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+ /// using unsigned saturation
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_packus_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpackuswb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(packuswb(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+ /// using unsigned saturation
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_packus_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpackusdw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(packusdw(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Permutes packed 32-bit integers from `a` according to the content of `b`.
+ ///
+ /// The last 3 bits of each integer of `b` are used as addresses into the 8
+ /// integers of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutevar8x32_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpermps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permutevar8x32_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(permd(a.as_u32x8(), b.as_u32x8()))
+ }
+ 
+ /// Permutes 64-bit integers from `a` using control mask `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute4x64_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpermpd, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute4x64_epi64(a: __m256i, imm8: i32) -> __m256i {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let zero = _mm256_setzero_si256().as_i64x4();
+     let a = a.as_i64x4();
+     macro_rules! permute4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             simd_shuffle4(a, zero, [$a, $b, $c, $d]);
+         };
+     }
+     macro_rules! permute3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => permute4!($a, $b, $c, 0),
+                 0b01 => permute4!($a, $b, $c, 1),
+                 0b10 => permute4!($a, $b, $c, 2),
+                 _ => permute4!($a, $b, $c, 3),
+             }
+         };
+     }
+     macro_rules! permute2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => permute3!($a, $b, 0),
+                 0b01 => permute3!($a, $b, 1),
+                 0b10 => permute3!($a, $b, 2),
+                 _ => permute3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! permute1 {
+         ($a:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => permute2!($a, 0),
+                 0b01 => permute2!($a, 1),
+                 0b10 => permute2!($a, 2),
+                 _ => permute2!($a, 3),
+             }
+         };
+     }
+     let r: i64x4 = match imm8 & 0b11 {
+         0b00 => permute1!(0),
+         0b01 => permute1!(1),
+         0b10 => permute1!(2),
+         _ => permute1!(3),
+     };
+     transmute(r)
+ }
+ 
+ /// Shuffles 128-bits of integer data selected by `imm8` from `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute2x128_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vperm2f128, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute2x128_si256(a: __m256i, b: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_i64x4();
+     let b = b.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vperm2i128(a, b, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8, call))
+ }
+ 
+ /// Shuffles 64-bit floating-point elements in `a` across lanes using the
+ /// control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permute4x64_pd)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpermpd, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permute4x64_pd(a: __m256d, imm8: i32) -> __m256d {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let undef = _mm256_undefined_pd();
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             simd_shuffle4(a, undef, [$x01, $x23, $x45, $x67])
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     }
+ }
+ 
+ /// Shuffles eight 32-bit foating-point elements in `a` across lanes using
+ /// the corresponding 32-bit integer index in `idx`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutevar8x32_ps)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpermps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_permutevar8x32_ps(a: __m256, idx: __m256i) -> __m256 {
+     permps(a, idx.as_i32x8())
+ }
+ 
+ /// Computes the absolute differences of packed unsigned 8-bit integers in `a`
+ /// and `b`, then horizontally sum each consecutive 8 differences to
+ /// produce four unsigned 16-bit integers, and pack these unsigned 16-bit
+ /// integers in the low 16 bits of the 64-bit return value
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sad_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsadbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sad_epu8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(psadbw(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Shuffles bytes from `a` according to the content of `b`.
+ ///
+ /// The last 4 bits of each byte of `b` are used as addresses into the 32 bytes
+ /// of `a`.
+ ///
+ /// In addition, if the highest significant bit of a byte of `b` is set, the
+ /// respective destination byte is set to 0.
+ ///
+ /// The low and high halves of the vectors are shuffled separately.
+ ///
+ /// Picturing `a` and `b` as `[u8; 32]`, `_mm256_shuffle_epi8` is logically
+ /// equivalent to:
+ ///
+ /// ```
+ /// fn mm256_shuffle_epi8(a: [u8; 32], b: [u8; 32]) -> [u8; 32] {
+ ///     let mut r = [0; 32];
+ ///     for i in 0..16 {
+ ///         // if the most significant bit of b is set,
+ ///         // then the destination byte is set to 0.
+ ///         if b[i] & 0x80 == 0u8 {
+ ///             r[i] = a[(b[i] % 16) as usize];
+ ///         }
+ ///         if b[i + 16] & 0x80 == 0u8 {
+ ///             r[i + 16] = a[(b[i + 16] % 16 + 16) as usize];
+ ///         }
+ ///     }
+ ///     r
+ /// }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_shuffle_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpshufb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_shuffle_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(pshufb(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Shuffles 32-bit integers in 128-bit lanes of `a` using the control in
+ /// `imm8`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
+ ///
+ /// let c1 = _mm256_shuffle_epi32(a, 0b00_11_10_01);
+ /// let c2 = _mm256_shuffle_epi32(a, 0b01_00_10_11);
+ ///
+ /// let expected1 = _mm256_setr_epi32(1, 2, 3, 0, 5, 6, 7, 4);
+ /// let expected2 = _mm256_setr_epi32(3, 2, 0, 1, 7, 6, 4, 5);
+ ///
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c1, expected1)), !0);
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c2, expected2)), !0);
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_shuffle_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_shuffle_epi32(a: __m256i, imm8: i32) -> __m256i {
+     // simd_shuffleX requires that its selector parameter be made up of
+     // constant values, but we can't enforce that here. In spirit, we need
+     // to write a `match` on all possible values of a byte, and for each value,
+     // hard-code the correct `simd_shuffleX` call using only constants. We
+     // then hope for LLVM to do the rest.
+     //
+     // Of course, that's... awful. So we try to use macros to do it for us.
+     let imm8 = (imm8 & 0xFF) as u8;
+ 
+     let a = a.as_i32x8();
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             simd_shuffle8(
+                 a,
+                 a,
+                 [
+                     $x01,
+                     $x23,
+                     $x45,
+                     $x67,
+                     4 + $x01,
+                     4 + $x23,
+                     4 + $x45,
+                     4 + $x67,
+                 ],
+             )
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     let r: i32x8 = match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     };
+     transmute(r)
+ }
+ 
+ /// Shuffles 16-bit integers in the high 64 bits of 128-bit lanes of `a` using
+ /// the control in `imm8`. The low 64 bits of 128-bit lanes of `a` are copied
+ /// to the output.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_shufflehi_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpshufhw, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_shufflehi_epi16(a: __m256i, imm8: i32) -> __m256i {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i16x16();
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             #[rustfmt::skip]
+                         simd_shuffle16(a, a, [
+                             0, 1, 2, 3, 4+$x01, 4+$x23, 4+$x45, 4+$x67,
+                             8, 9, 10, 11, 12+$x01, 12+$x23, 12+$x45, 12+$x67
+                         ]);
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     let r: i16x16 = match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     };
+     transmute(r)
+ }
+ 
+ /// Shuffles 16-bit integers in the low 64 bits of 128-bit lanes of `a` using
+ /// the control in `imm8`. The high 64 bits of 128-bit lanes of `a` are copied
+ /// to the output.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_shufflelo_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpshuflw, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_shufflelo_epi16(a: __m256i, imm8: i32) -> __m256i {
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i16x16();
+     macro_rules! shuffle_done {
+         ($x01: expr, $x23: expr, $x45: expr, $x67: expr) => {
+             #[rustfmt::skip]
+                         simd_shuffle16(a, a, [
+                             0+$x01, 0+$x23, 0+$x45, 0+$x67, 4, 5, 6, 7,
+                             8+$x01, 8+$x23, 8+$x45, 8+$x67, 12, 13, 14, 15,
+                         ]);
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     let r: i16x16 = match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     };
+     transmute(r)
+ }
+ 
+ /// Negates packed 16-bit integers in `a` when the corresponding signed
+ /// 16-bit integer in `b` is negative, and returns the results.
+ /// Results are zeroed out when the corresponding element in `b` is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sign_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsignw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sign_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(psignw(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Negates packed 32-bit integers in `a` when the corresponding signed
+ /// 32-bit integer in `b` is negative, and returns the results.
+ /// Results are zeroed out when the corresponding element in `b` is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sign_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsignd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sign_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(psignd(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Negates packed 8-bit integers in `a` when the corresponding signed
+ /// 8-bit integer in `b` is negative, and returns the results.
+ /// Results are zeroed out when the corresponding element in `b` is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sign_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsignb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sign_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(psignb(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` left by `count` while
+ /// shifting in zeros, and returns the result
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sll_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sll_epi16(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psllw(a.as_i16x16(), count.as_i16x8()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` left by `count` while
+ /// shifting in zeros, and returns the result
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sll_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpslld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sll_epi32(a: __m256i, count: __m128i) -> __m256i {
+     transmute(pslld(a.as_i32x8(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` left by `count` while
+ /// shifting in zeros, and returns the result
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sll_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sll_epi64(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psllq(a.as_i64x4(), count.as_i64x2()))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` left by `imm8` while
+ /// shifting in zeros, return the results;
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_slli_epi16(a: __m256i, imm8: i32) -> __m256i {
+     transmute(pslliw(a.as_i16x16(), imm8))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` left by `imm8` while
+ /// shifting in zeros, return the results;
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpslld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_slli_epi32(a: __m256i, imm8: i32) -> __m256i {
+     transmute(psllid(a.as_i32x8(), imm8))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` left by `imm8` while
+ /// shifting in zeros, return the results;
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_slli_epi64(a: __m256i, imm8: i32) -> __m256i {
+     transmute(pslliq(a.as_i64x4(), imm8))
+ }
+ 
+ /// Shifts 128-bit lanes in `a` left by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_slli_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpslldq, imm8 = 3))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_slli_si256(a: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpslldq(a, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8 * 8, call))
+ }
+ 
+ /// Shifts 128-bit lanes in `a` left by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_bslli_epi128)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpslldq, imm8 = 3))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_bslli_epi128(a: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpslldq(a, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8 * 8, call))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` left by the amount
+ /// specified by the corresponding element in `count` while
+ /// shifting in zeros, and returns the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sllv_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllvd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sllv_epi32(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psllvd(a.as_i32x4(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` left by the amount
+ /// specified by the corresponding element in `count` while
+ /// shifting in zeros, and returns the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sllv_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllvd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sllv_epi32(a: __m256i, count: __m256i) -> __m256i {
+     transmute(psllvd256(a.as_i32x8(), count.as_i32x8()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` left by the amount
+ /// specified by the corresponding element in `count` while
+ /// shifting in zeros, and returns the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sllv_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllvq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sllv_epi64(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psllvq(a.as_i64x2(), count.as_i64x2()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` left by the amount
+ /// specified by the corresponding element in `count` while
+ /// shifting in zeros, and returns the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sllv_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsllvq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sllv_epi64(a: __m256i, count: __m256i) -> __m256i {
+     transmute(psllvq256(a.as_i64x4(), count.as_i64x4()))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `count` while
+ /// shifting in sign bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sra_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsraw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sra_epi16(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psraw(a.as_i16x16(), count.as_i16x8()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `count` while
+ /// shifting in sign bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sra_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrad))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sra_epi32(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psrad(a.as_i32x8(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `imm8` while
+ /// shifting in sign bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srai_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsraw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srai_epi16(a: __m256i, imm8: i32) -> __m256i {
+     transmute(psraiw(a.as_i16x16(), imm8))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `imm8` while
+ /// shifting in sign bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srai_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrad))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srai_epi32(a: __m256i, imm8: i32) -> __m256i {
+     transmute(psraid(a.as_i32x8(), imm8))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by the amount specified by the
+ /// corresponding element in `count` while shifting in sign bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srav_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsravd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srav_epi32(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psravd(a.as_i32x4(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by the amount specified by the
+ /// corresponding element in `count` while shifting in sign bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srav_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsravd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srav_epi32(a: __m256i, count: __m256i) -> __m256i {
+     transmute(psravd256(a.as_i32x8(), count.as_i32x8()))
+ }
+ 
+ /// Shifts 128-bit lanes in `a` right by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrldq, imm8 = 3))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srli_si256(a: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrldq(a, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8 * 8, call))
+ }
+ 
+ /// Shifts 128-bit lanes in `a` right by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_bsrli_epi128)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrldq, imm8 = 3))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_bsrli_epi128(a: __m256i, imm8: i32) -> __m256i {
+     let a = a.as_i64x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrldq(a, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8 * 8, call))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srl_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srl_epi16(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psrlw(a.as_i16x16(), count.as_i16x8()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srl_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srl_epi32(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psrld(a.as_i32x8(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` right by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srl_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srl_epi64(a: __m256i, count: __m128i) -> __m256i {
+     transmute(psrlq(a.as_i64x4(), count.as_i64x2()))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `imm8` while shifting in
+ /// zeros
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srli_epi16(a: __m256i, imm8: i32) -> __m256i {
+     transmute(psrliw(a.as_i16x16(), imm8))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `imm8` while shifting in
+ /// zeros
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srli_epi32(a: __m256i, imm8: i32) -> __m256i {
+     transmute(psrlid(a.as_i32x8(), imm8))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` right by `imm8` while shifting in
+ /// zeros
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srli_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srli_epi64(a: __m256i, imm8: i32) -> __m256i {
+     transmute(psrliq(a.as_i64x4(), imm8))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by the amount specified by
+ /// the corresponding element in `count` while shifting in zeros,
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srlv_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlvd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srlv_epi32(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psrlvd(a.as_i32x4(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by the amount specified by
+ /// the corresponding element in `count` while shifting in zeros,
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srlv_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlvd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srlv_epi32(a: __m256i, count: __m256i) -> __m256i {
+     transmute(psrlvd256(a.as_i32x8(), count.as_i32x8()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` right by the amount specified by
+ /// the corresponding element in `count` while shifting in zeros,
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srlv_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlvq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srlv_epi64(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psrlvq(a.as_i64x2(), count.as_i64x2()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` right by the amount specified by
+ /// the corresponding element in `count` while shifting in zeros,
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_srlv_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsrlvq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
+     transmute(psrlvq256(a.as_i64x4(), count.as_i64x4()))
+ }
+ 
+ // TODO _mm256_stream_load_si256 (__m256i const* mem_addr)
+ 
+ /// Subtract packed 16-bit integers in `b` from packed 16-bit integers in `a`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sub_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_sub(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Subtract packed 32-bit integers in `b` from packed 32-bit integers in `a`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sub_epi32(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_sub(a.as_i32x8(), b.as_i32x8()))
+ }
+ 
+ /// Subtract packed 64-bit integers in `b` from packed 64-bit integers in `a`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sub_epi64(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_sub(a.as_i64x4(), b.as_i64x4()))
+ }
+ 
+ /// Subtract packed 8-bit integers in `b` from packed 8-bit integers in `a`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sub_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_sub_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_sub(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Subtract packed 16-bit integers in `b` from packed 16-bit integers in
+ /// `a` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_subs_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_subs_epi16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_sub(a.as_i16x16(), b.as_i16x16()))
+ }
+ 
+ /// Subtract packed 8-bit integers in `b` from packed 8-bit integers in
+ /// `a` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_subs_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_subs_epi8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_sub(a.as_i8x32(), b.as_i8x32()))
+ }
+ 
+ /// Subtract packed unsigned 16-bit integers in `b` from packed 16-bit
+ /// integers in `a` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_subs_epu16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubusw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_subs_epu16(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_sub(a.as_u16x16(), b.as_u16x16()))
+ }
+ 
+ /// Subtract packed unsigned 8-bit integers in `b` from packed 8-bit
+ /// integers in `a` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_subs_epu8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpsubusb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_subs_epu8(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_saturating_sub(a.as_u8x32(), b.as_u8x32()))
+ }
+ 
+ /// Unpacks and interleave 8-bit integers from the high half of each
+ /// 128-bit lane in `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi8(
+ ///     0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ ///     20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ /// );
+ /// let b = _mm256_setr_epi8(
+ ///     0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
+ ///     -16, -17, -18, -19, -20, -21, -22, -23, -24, -25, -26, -27, -28, -29,
+ ///     -30, -31,
+ /// );
+ ///
+ /// let c = _mm256_unpackhi_epi8(a, b);
+ ///
+ /// let expected = _mm256_setr_epi8(
+ ///     8, -8, 9, -9, 10, -10, 11, -11, 12, -12, 13, -13, 14, -14, 15, -15,
+ ///     24, -24, 25, -25, 26, -26, 27, -27, 28, -28, 29, -29, 30, -30, 31,
+ ///     -31,
+ /// );
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpackhi_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpunpckhbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpackhi_epi8(a: __m256i, b: __m256i) -> __m256i {
+     #[rustfmt::skip]
+     let r: i8x32 = simd_shuffle32(a.as_i8x32(), b.as_i8x32(), [
+             8, 40, 9, 41, 10, 42, 11, 43,
+             12, 44, 13, 45, 14, 46, 15, 47,
+             24, 56, 25, 57, 26, 58, 27, 59,
+             28, 60, 29, 61, 30, 62, 31, 63,
+     ]);
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 8-bit integers from the low half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi8(
+ ///     0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ ///     20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ /// );
+ /// let b = _mm256_setr_epi8(
+ ///     0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
+ ///     -16, -17, -18, -19, -20, -21, -22, -23, -24, -25, -26, -27, -28, -29,
+ ///     -30, -31,
+ /// );
+ ///
+ /// let c = _mm256_unpacklo_epi8(a, b);
+ ///
+ /// let expected = _mm256_setr_epi8(
+ ///     0, 0, 1, -1, 2, -2, 3, -3, 4, -4, 5, -5, 6, -6, 7, -7, 16, -16, 17,
+ ///     -17, 18, -18, 19, -19, 20, -20, 21, -21, 22, -22, 23, -23,
+ /// );
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpacklo_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpunpcklbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpacklo_epi8(a: __m256i, b: __m256i) -> __m256i {
+     #[rustfmt::skip]
+     let r: i8x32 = simd_shuffle32(a.as_i8x32(), b.as_i8x32(), [
+         0, 32, 1, 33, 2, 34, 3, 35,
+         4, 36, 5, 37, 6, 38, 7, 39,
+         16, 48, 17, 49, 18, 50, 19, 51,
+         20, 52, 21, 53, 22, 54, 23, 55,
+     ]);
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 16-bit integers from the high half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi16(
+ ///     0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ /// );
+ /// let b = _mm256_setr_epi16(
+ ///     0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
+ /// );
+ ///
+ /// let c = _mm256_unpackhi_epi16(a, b);
+ ///
+ /// let expected = _mm256_setr_epi16(
+ ///     4, -4, 5, -5, 6, -6, 7, -7, 12, -12, 13, -13, 14, -14, 15, -15,
+ /// );
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpackhi_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpunpckhwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpackhi_epi16(a: __m256i, b: __m256i) -> __m256i {
+     let r: i16x16 = simd_shuffle16(
+         a.as_i16x16(),
+         b.as_i16x16(),
+         [4, 20, 5, 21, 6, 22, 7, 23, 12, 28, 13, 29, 14, 30, 15, 31],
+     );
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 16-bit integers from the low half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ ///
+ /// let a = _mm256_setr_epi16(
+ ///     0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ /// );
+ /// let b = _mm256_setr_epi16(
+ ///     0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
+ /// );
+ ///
+ /// let c = _mm256_unpacklo_epi16(a, b);
+ ///
+ /// let expected = _mm256_setr_epi16(
+ ///     0, 0, 1, -1, 2, -2, 3, -3, 8, -8, 9, -9, 10, -10, 11, -11,
+ /// );
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpacklo_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vpunpcklwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpacklo_epi16(a: __m256i, b: __m256i) -> __m256i {
+     let r: i16x16 = simd_shuffle16(
+         a.as_i16x16(),
+         b.as_i16x16(),
+         [0, 16, 1, 17, 2, 18, 3, 19, 8, 24, 9, 25, 10, 26, 11, 27],
+     );
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 32-bit integers from the high half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
+ /// let b = _mm256_setr_epi32(0, -1, -2, -3, -4, -5, -6, -7);
+ ///
+ /// let c = _mm256_unpackhi_epi32(a, b);
+ ///
+ /// let expected = _mm256_setr_epi32(2, -2, 3, -3, 6, -6, 7, -7);
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpackhi_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vunpckhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpackhi_epi32(a: __m256i, b: __m256i) -> __m256i {
+     let r: i32x8 = simd_shuffle8(a.as_i32x8(), b.as_i32x8(), [2, 10, 3, 11, 6, 14, 7, 15]);
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 32-bit integers from the low half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
+ /// let b = _mm256_setr_epi32(0, -1, -2, -3, -4, -5, -6, -7);
+ ///
+ /// let c = _mm256_unpacklo_epi32(a, b);
+ ///
+ /// let expected = _mm256_setr_epi32(0, 0, 1, -1, 4, -4, 5, -5);
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpacklo_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vunpcklps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpacklo_epi32(a: __m256i, b: __m256i) -> __m256i {
+     let r: i32x8 = simd_shuffle8(a.as_i32x8(), b.as_i32x8(), [0, 8, 1, 9, 4, 12, 5, 13]);
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 64-bit integers from the high half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi64x(0, 1, 2, 3);
+ /// let b = _mm256_setr_epi64x(0, -1, -2, -3);
+ ///
+ /// let c = _mm256_unpackhi_epi64(a, b);
+ ///
+ /// let expected = _mm256_setr_epi64x(1, -1, 3, -3);
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpackhi_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vunpckhpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpackhi_epi64(a: __m256i, b: __m256i) -> __m256i {
+     let r: i64x4 = simd_shuffle4(a.as_i64x4(), b.as_i64x4(), [1, 5, 3, 7]);
+     transmute(r)
+ }
+ 
+ /// Unpacks and interleave 64-bit integers from the low half of each
+ /// 128-bit lane of `a` and `b`.
+ ///
+ /// ```rust
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("avx2") {
+ /// #         #[target_feature(enable = "avx2")]
+ /// #         unsafe fn worker() {
+ /// let a = _mm256_setr_epi64x(0, 1, 2, 3);
+ /// let b = _mm256_setr_epi64x(0, -1, -2, -3);
+ ///
+ /// let c = _mm256_unpacklo_epi64(a, b);
+ ///
+ /// let expected = _mm256_setr_epi64x(0, 0, 2, -2);
+ /// assert_eq!(_mm256_movemask_epi8(_mm256_cmpeq_epi8(c, expected)), !0);
+ ///
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_unpacklo_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vunpcklpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_unpacklo_epi64(a: __m256i, b: __m256i) -> __m256i {
+     let r: i64x4 = simd_shuffle4(a.as_i64x4(), b.as_i64x4(), [0, 4, 2, 6]);
+     transmute(r)
+ }
+ 
+ /// Computes the bitwise XOR of 256 bits (representing integer data)
+ /// in `a` and `b`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_xor_si256)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[cfg_attr(test, assert_instr(vxorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_xor_si256(a: __m256i, b: __m256i) -> __m256i {
+     transmute(simd_xor(a.as_i64x4(), b.as_i64x4()))
+ }
+ 
+ /// Extracts an 8-bit integer from `a`, selected with `imm8`. Returns a 32-bit
+ /// integer containing the zero-extended integer data.
+ ///
+ /// See [LLVM commit D20468][https://reviews.llvm.org/D20468].
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extract_epi8)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ // This intrinsic has no corresponding instruction.
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extract_epi8(a: __m256i, imm8: i32) -> i32 {
+     let a = a.as_u8x32();
+     macro_rules! call {
+         ($imm5:expr) => {
+             simd_extract::<_, u8>(a, $imm5) as i32
+         };
+     }
+     constify_imm5!(imm8, call)
+ }
+ 
+ /// Extracts a 16-bit integer from `a`, selected with `imm8`. Returns a 32-bit
+ /// integer containing the zero-extended integer data.
+ ///
+ /// See [LLVM commit D20468][https://reviews.llvm.org/D20468].
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extract_epi16)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ // This intrinsic has no corresponding instruction.
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extract_epi16(a: __m256i, imm8: i32) -> i32 {
+     let a = a.as_u16x16();
+     macro_rules! call {
+         ($imm4:expr) => {
+             simd_extract::<_, u16>(a, $imm4) as i32
+         };
+     }
+     constify_imm4!((imm8 & 15), call)
+ }
+ 
+ /// Extracts a 32-bit integer from `a`, selected with `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extract_epi32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ // This intrinsic has no corresponding instruction.
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extract_epi32(a: __m256i, imm8: i32) -> i32 {
+     let a = a.as_i32x8();
+     macro_rules! call {
+         ($imm3:expr) => {
+             simd_extract(a, $imm3)
+         };
+     }
+     constify_imm3!((imm8 & 7), call)
+ }
+ 
+ /// Returns the first element of the input vector of `[4 x double]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtsd_f64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ //#[cfg_attr(test, assert_instr(movsd))] FIXME
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
+     simd_extract(a, 0)
+ }
+ 
+ /// Returns the first element of the input vector of `[8 x i32]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtsi256_si32)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ //#[cfg_attr(test, assert_instr(movd))] FIXME
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_cvtsi256_si32(a: __m256i) -> i32 {
+     simd_extract(a.as_i32x8(), 0)
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.avx2.pabs.b"]
+     fn pabsb(a: i8x32) -> u8x32;
+     #[link_name = "llvm.x86.avx2.pabs.w"]
+     fn pabsw(a: i16x16) -> u16x16;
+     #[link_name = "llvm.x86.avx2.pabs.d"]
+     fn pabsd(a: i32x8) -> u32x8;
+     #[link_name = "llvm.x86.avx2.pavg.b"]
+     fn pavgb(a: u8x32, b: u8x32) -> u8x32;
+     #[link_name = "llvm.x86.avx2.pavg.w"]
+     fn pavgw(a: u16x16, b: u16x16) -> u16x16;
+     #[link_name = "llvm.x86.avx2.pblendvb"]
+     fn pblendvb(a: i8x32, b: i8x32, mask: i8x32) -> i8x32;
+     #[link_name = "llvm.x86.avx2.phadd.w"]
+     fn phaddw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.phadd.d"]
+     fn phaddd(a: i32x8, b: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.phadd.sw"]
+     fn phaddsw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.phsub.w"]
+     fn phsubw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.phsub.d"]
+     fn phsubd(a: i32x8, b: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.phsub.sw"]
+     fn phsubsw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.pmadd.wd"]
+     fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
+     #[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
+     fn pmaddubsw(a: u8x32, b: u8x32) -> i16x16;
+     #[link_name = "llvm.x86.avx2.maskload.d"]
+     fn maskloadd(mem_addr: *const i8, mask: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.avx2.maskload.d.256"]
+     fn maskloadd256(mem_addr: *const i8, mask: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.maskload.q"]
+     fn maskloadq(mem_addr: *const i8, mask: i64x2) -> i64x2;
+     #[link_name = "llvm.x86.avx2.maskload.q.256"]
+     fn maskloadq256(mem_addr: *const i8, mask: i64x4) -> i64x4;
+     #[link_name = "llvm.x86.avx2.maskstore.d"]
+     fn maskstored(mem_addr: *mut i8, mask: i32x4, a: i32x4);
+     #[link_name = "llvm.x86.avx2.maskstore.d.256"]
+     fn maskstored256(mem_addr: *mut i8, mask: i32x8, a: i32x8);
+     #[link_name = "llvm.x86.avx2.maskstore.q"]
+     fn maskstoreq(mem_addr: *mut i8, mask: i64x2, a: i64x2);
+     #[link_name = "llvm.x86.avx2.maskstore.q.256"]
+     fn maskstoreq256(mem_addr: *mut i8, mask: i64x4, a: i64x4);
+     #[link_name = "llvm.x86.avx2.pmaxs.w"]
+     fn pmaxsw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.pmaxs.d"]
+     fn pmaxsd(a: i32x8, b: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.pmaxs.b"]
+     fn pmaxsb(a: i8x32, b: i8x32) -> i8x32;
+     #[link_name = "llvm.x86.avx2.pmaxu.w"]
+     fn pmaxuw(a: u16x16, b: u16x16) -> u16x16;
+     #[link_name = "llvm.x86.avx2.pmaxu.d"]
+     fn pmaxud(a: u32x8, b: u32x8) -> u32x8;
+     #[link_name = "llvm.x86.avx2.pmaxu.b"]
+     fn pmaxub(a: u8x32, b: u8x32) -> u8x32;
+     #[link_name = "llvm.x86.avx2.pmins.w"]
+     fn pminsw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.pmins.d"]
+     fn pminsd(a: i32x8, b: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.pmins.b"]
+     fn pminsb(a: i8x32, b: i8x32) -> i8x32;
+     #[link_name = "llvm.x86.avx2.pminu.w"]
+     fn pminuw(a: u16x16, b: u16x16) -> u16x16;
+     #[link_name = "llvm.x86.avx2.pminu.d"]
+     fn pminud(a: u32x8, b: u32x8) -> u32x8;
+     #[link_name = "llvm.x86.avx2.pminu.b"]
+     fn pminub(a: u8x32, b: u8x32) -> u8x32;
+     #[link_name = "llvm.x86.avx2.pmovmskb"]
+     fn pmovmskb(a: i8x32) -> i32;
+     #[link_name = "llvm.x86.avx2.mpsadbw"]
+     fn mpsadbw(a: u8x32, b: u8x32, imm8: i32) -> u16x16;
+     #[link_name = "llvm.x86.avx2.pmulhu.w"]
+     fn pmulhuw(a: u16x16, b: u16x16) -> u16x16;
+     #[link_name = "llvm.x86.avx2.pmulh.w"]
+     fn pmulhw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.pmul.dq"]
+     fn pmuldq(a: i32x8, b: i32x8) -> i64x4;
+     #[link_name = "llvm.x86.avx2.pmulu.dq"]
+     fn pmuludq(a: u32x8, b: u32x8) -> u64x4;
+     #[link_name = "llvm.x86.avx2.pmul.hr.sw"]
+     fn pmulhrsw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.packsswb"]
+     fn packsswb(a: i16x16, b: i16x16) -> i8x32;
+     #[link_name = "llvm.x86.avx2.packssdw"]
+     fn packssdw(a: i32x8, b: i32x8) -> i16x16;
+     #[link_name = "llvm.x86.avx2.packuswb"]
+     fn packuswb(a: i16x16, b: i16x16) -> u8x32;
+     #[link_name = "llvm.x86.avx2.packusdw"]
+     fn packusdw(a: i32x8, b: i32x8) -> u16x16;
+     #[link_name = "llvm.x86.avx2.psad.bw"]
+     fn psadbw(a: u8x32, b: u8x32) -> u64x4;
+     #[link_name = "llvm.x86.avx2.psign.b"]
+     fn psignb(a: i8x32, b: i8x32) -> i8x32;
+     #[link_name = "llvm.x86.avx2.psign.w"]
+     fn psignw(a: i16x16, b: i16x16) -> i16x16;
+     #[link_name = "llvm.x86.avx2.psign.d"]
+     fn psignd(a: i32x8, b: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psll.w"]
+     fn psllw(a: i16x16, count: i16x8) -> i16x16;
+     #[link_name = "llvm.x86.avx2.psll.d"]
+     fn pslld(a: i32x8, count: i32x4) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psll.q"]
+     fn psllq(a: i64x4, count: i64x2) -> i64x4;
+     #[link_name = "llvm.x86.avx2.pslli.w"]
+     fn pslliw(a: i16x16, imm8: i32) -> i16x16;
+     #[link_name = "llvm.x86.avx2.pslli.d"]
+     fn psllid(a: i32x8, imm8: i32) -> i32x8;
+     #[link_name = "llvm.x86.avx2.pslli.q"]
+     fn pslliq(a: i64x4, imm8: i32) -> i64x4;
+     #[link_name = "llvm.x86.avx2.psllv.d"]
+     fn psllvd(a: i32x4, count: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.avx2.psllv.d.256"]
+     fn psllvd256(a: i32x8, count: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psllv.q"]
+     fn psllvq(a: i64x2, count: i64x2) -> i64x2;
+     #[link_name = "llvm.x86.avx2.psllv.q.256"]
+     fn psllvq256(a: i64x4, count: i64x4) -> i64x4;
+     #[link_name = "llvm.x86.avx2.psra.w"]
+     fn psraw(a: i16x16, count: i16x8) -> i16x16;
+     #[link_name = "llvm.x86.avx2.psra.d"]
+     fn psrad(a: i32x8, count: i32x4) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psrai.w"]
+     fn psraiw(a: i16x16, imm8: i32) -> i16x16;
+     #[link_name = "llvm.x86.avx2.psrai.d"]
+     fn psraid(a: i32x8, imm8: i32) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psrav.d"]
+     fn psravd(a: i32x4, count: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.avx2.psrav.d.256"]
+     fn psravd256(a: i32x8, count: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psrl.w"]
+     fn psrlw(a: i16x16, count: i16x8) -> i16x16;
+     #[link_name = "llvm.x86.avx2.psrl.d"]
+     fn psrld(a: i32x8, count: i32x4) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psrl.q"]
+     fn psrlq(a: i64x4, count: i64x2) -> i64x4;
+     #[link_name = "llvm.x86.avx2.psrli.w"]
+     fn psrliw(a: i16x16, imm8: i32) -> i16x16;
+     #[link_name = "llvm.x86.avx2.psrli.d"]
+     fn psrlid(a: i32x8, imm8: i32) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psrli.q"]
+     fn psrliq(a: i64x4, imm8: i32) -> i64x4;
+     #[link_name = "llvm.x86.avx2.psrlv.d"]
+     fn psrlvd(a: i32x4, count: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.avx2.psrlv.d.256"]
+     fn psrlvd256(a: i32x8, count: i32x8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.psrlv.q"]
+     fn psrlvq(a: i64x2, count: i64x2) -> i64x2;
+     #[link_name = "llvm.x86.avx2.psrlv.q.256"]
+     fn psrlvq256(a: i64x4, count: i64x4) -> i64x4;
+     #[link_name = "llvm.x86.avx2.pshuf.b"]
+     fn pshufb(a: u8x32, b: u8x32) -> u8x32;
+     #[link_name = "llvm.x86.avx2.permd"]
+     fn permd(a: u32x8, b: u32x8) -> u32x8;
+     #[link_name = "llvm.x86.avx2.permps"]
+     fn permps(a: __m256, b: i32x8) -> __m256;
+     #[link_name = "llvm.x86.avx2.vperm2i128"]
+     fn vperm2i128(a: i64x4, b: i64x4, imm8: i8) -> i64x4;
+     #[link_name = "llvm.x86.avx2.gather.d.d"]
+     fn pgatherdd(src: i32x4, slice: *const i8, offsets: i32x4, mask: i32x4, scale: i8) -> i32x4;
+     #[link_name = "llvm.x86.avx2.gather.d.d.256"]
+     fn vpgatherdd(src: i32x8, slice: *const i8, offsets: i32x8, mask: i32x8, scale: i8) -> i32x8;
+     #[link_name = "llvm.x86.avx2.gather.d.q"]
+     fn pgatherdq(src: i64x2, slice: *const i8, offsets: i32x4, mask: i64x2, scale: i8) -> i64x2;
+     #[link_name = "llvm.x86.avx2.gather.d.q.256"]
+     fn vpgatherdq(src: i64x4, slice: *const i8, offsets: i32x4, mask: i64x4, scale: i8) -> i64x4;
+     #[link_name = "llvm.x86.avx2.gather.q.d"]
+     fn pgatherqd(src: i32x4, slice: *const i8, offsets: i64x2, mask: i32x4, scale: i8) -> i32x4;
+     #[link_name = "llvm.x86.avx2.gather.q.d.256"]
+     fn vpgatherqd(src: i32x4, slice: *const i8, offsets: i64x4, mask: i32x4, scale: i8) -> i32x4;
+     #[link_name = "llvm.x86.avx2.gather.q.q"]
+     fn pgatherqq(src: i64x2, slice: *const i8, offsets: i64x2, mask: i64x2, scale: i8) -> i64x2;
+     #[link_name = "llvm.x86.avx2.gather.q.q.256"]
+     fn vpgatherqq(src: i64x4, slice: *const i8, offsets: i64x4, mask: i64x4, scale: i8) -> i64x4;
+     #[link_name = "llvm.x86.avx2.gather.d.pd"]
+     fn pgatherdpd(
+         src: __m128d,
+         slice: *const i8,
+         offsets: i32x4,
+         mask: __m128d,
+         scale: i8,
+     ) -> __m128d;
+     #[link_name = "llvm.x86.avx2.gather.d.pd.256"]
+     fn vpgatherdpd(
+         src: __m256d,
+         slice: *const i8,
+         offsets: i32x4,
+         mask: __m256d,
+         scale: i8,
+     ) -> __m256d;
+     #[link_name = "llvm.x86.avx2.gather.q.pd"]
+     fn pgatherqpd(
+         src: __m128d,
+         slice: *const i8,
+         offsets: i64x2,
+         mask: __m128d,
+         scale: i8,
+     ) -> __m128d;
+     #[link_name = "llvm.x86.avx2.gather.q.pd.256"]
+     fn vpgatherqpd(
+         src: __m256d,
+         slice: *const i8,
+         offsets: i64x4,
+         mask: __m256d,
+         scale: i8,
+     ) -> __m256d;
+     #[link_name = "llvm.x86.avx2.gather.d.ps"]
+     fn pgatherdps(src: __m128, slice: *const i8, offsets: i32x4, mask: __m128, scale: i8)
+         -> __m128;
+     #[link_name = "llvm.x86.avx2.gather.d.ps.256"]
+     fn vpgatherdps(
+         src: __m256,
+         slice: *const i8,
+         offsets: i32x8,
+         mask: __m256,
+         scale: i8,
+     ) -> __m256;
+     #[link_name = "llvm.x86.avx2.gather.q.ps"]
+     fn pgatherqps(src: __m128, slice: *const i8, offsets: i64x2, mask: __m128, scale: i8)
+         -> __m128;
+     #[link_name = "llvm.x86.avx2.gather.q.ps.256"]
+     fn vpgatherqps(
+         src: __m128,
+         slice: *const i8,
+         offsets: i64x4,
+         mask: __m128,
+         scale: i8,
+     ) -> __m128;
+     #[link_name = "llvm.x86.avx2.psll.dq"]
+     fn vpslldq(a: i64x4, b: i32) -> i64x4;
+     #[link_name = "llvm.x86.avx2.psrl.dq"]
+     fn vpsrldq(a: i64x4, b: i32) -> i64x4;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std;
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_abs_epi32() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi32(
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+         );
+         let r = _mm256_abs_epi32(a);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi32(
+             0, 1, 1, i32::MAX,
+             i32::MAX.wrapping_add(1), 100, 100, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_abs_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0,  1, -1, 2, -2, 3, -3, 4,
+             -4, 5, -5, i16::MAX, i16::MIN, 100, -100, -32,
+         );
+         let r = _mm256_abs_epi16(a);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             0, 1, 1, 2, 2, 3, 3, 4,
+             4, 5, 5, i16::MAX, i16::MAX.wrapping_add(1), 100, 100, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_abs_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             0, 1, -1, 2, -2, 3, -3, 4,
+             -4, 5, -5, i8::MAX, i8::MIN, 100, -100, -32,
+             0, 1, -1, 2, -2, 3, -3, 4,
+             -4, 5, -5, i8::MAX, i8::MIN, 100, -100, -32,
+         );
+         let r = _mm256_abs_epi8(a);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             0, 1, 1, 2, 2, 3, 3, 4,
+             4, 5, 5, i8::MAX, i8::MAX.wrapping_add(1), 100, 100, 32,
+             0, 1, 1, 2, 2, 3, 3, 4,
+             4, 5, 5, i8::MAX, i8::MAX.wrapping_add(1), 100, 100, 32,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_add_epi64() {
+         let a = _mm256_setr_epi64x(-10, 0, 100, 1_000_000_000);
+         let b = _mm256_setr_epi64x(-1, 0, 1, 2);
+         let r = _mm256_add_epi64(a, b);
+         let e = _mm256_setr_epi64x(-11, 0, 101, 1_000_000_002);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_add_epi32() {
+         let a = _mm256_setr_epi32(-1, 0, 1, 2, 3, 4, 5, 6);
+         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = _mm256_add_epi32(a, b);
+         let e = _mm256_setr_epi32(0, 2, 4, 6, 8, 10, 12, 14);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_add_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         let r = _mm256_add_epi16(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             0, 2, 4, 6, 8, 10, 12, 14,
+             16, 18, 20, 22, 24, 26, 28, 30,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_add_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         let r = _mm256_add_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             0, 2, 4, 6, 8, 10, 12, 14,
+             16, 18, 20, 22, 24, 26, 28, 30,
+             32, 34, 36, 38, 40, 42, 44, 46,
+             48, 50, 52, 54, 56, 58, 60, 62,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi8(
+             32, 33, 34, 35, 36, 37, 38, 39,
+             40, 41, 42, 43, 44, 45, 46, 47,
+             48, 49, 50, 51, 52, 53, 54, 55,
+             56, 57, 58, 59, 60, 61, 62, 63,
+         );
+         let r = _mm256_adds_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             32, 34, 36, 38, 40, 42, 44, 46,
+             48, 50, 52, 54, 56, 58, 60, 62,
+             64, 66, 68, 70, 72, 74, 76, 78,
+             80, 82, 84, 86, 88, 90, 92, 94,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epi8_saturate_positive() {
+         let a = _mm256_set1_epi8(0x7F);
+         let b = _mm256_set1_epi8(1);
+         let r = _mm256_adds_epi8(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epi8_saturate_negative() {
+         let a = _mm256_set1_epi8(-0x80);
+         let b = _mm256_set1_epi8(-1);
+         let r = _mm256_adds_epi8(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi16(
+             32, 33, 34, 35, 36, 37, 38, 39,
+             40, 41, 42, 43, 44, 45, 46, 47,
+         );
+         let r = _mm256_adds_epi16(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             32, 34, 36, 38, 40, 42, 44, 46,
+             48, 50, 52, 54, 56, 58, 60, 62,
+         );
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epi16_saturate_positive() {
+         let a = _mm256_set1_epi16(0x7FFF);
+         let b = _mm256_set1_epi16(1);
+         let r = _mm256_adds_epi16(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epi16_saturate_negative() {
+         let a = _mm256_set1_epi16(-0x8000);
+         let b = _mm256_set1_epi16(-1);
+         let r = _mm256_adds_epi16(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epu8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi8(
+             32, 33, 34, 35, 36, 37, 38, 39,
+             40, 41, 42, 43, 44, 45, 46, 47,
+             48, 49, 50, 51, 52, 53, 54, 55,
+             56, 57, 58, 59, 60, 61, 62, 63,
+         );
+         let r = _mm256_adds_epu8(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             32, 34, 36, 38, 40, 42, 44, 46,
+             48, 50, 52, 54, 56, 58, 60, 62,
+             64, 66, 68, 70, 72, 74, 76, 78,
+             80, 82, 84, 86, 88, 90, 92, 94,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epu8_saturate() {
+         let a = _mm256_set1_epi8(!0);
+         let b = _mm256_set1_epi8(1);
+         let r = _mm256_adds_epu8(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epu16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi16(
+             32, 33, 34, 35, 36, 37, 38, 39,
+             40, 41, 42, 43, 44, 45, 46, 47,
+         );
+         let r = _mm256_adds_epu16(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             32, 34, 36, 38, 40, 42, 44, 46,
+             48, 50, 52, 54, 56, 58, 60, 62,
+         );
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_adds_epu16_saturate() {
+         let a = _mm256_set1_epi16(!0);
+         let b = _mm256_set1_epi16(1);
+         let r = _mm256_adds_epu16(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_and_si256() {
+         let a = _mm256_set1_epi8(5);
+         let b = _mm256_set1_epi8(3);
+         let got = _mm256_and_si256(a, b);
+         assert_eq_m256i(got, _mm256_set1_epi8(1));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_andnot_si256() {
+         let a = _mm256_set1_epi8(5);
+         let b = _mm256_set1_epi8(3);
+         let got = _mm256_andnot_si256(a, b);
+         assert_eq_m256i(got, _mm256_set1_epi8(2));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_avg_epu8() {
+         let (a, b) = (_mm256_set1_epi8(3), _mm256_set1_epi8(9));
+         let r = _mm256_avg_epu8(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi8(6));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_avg_epu16() {
+         let (a, b) = (_mm256_set1_epi16(3), _mm256_set1_epi16(9));
+         let r = _mm256_avg_epu16(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi16(6));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_blend_epi32() {
+         let (a, b) = (_mm_set1_epi32(3), _mm_set1_epi32(9));
+         let e = _mm_setr_epi32(9, 3, 3, 3);
+         let r = _mm_blend_epi32(a, b, 0x01 as i32);
+         assert_eq_m128i(r, e);
+ 
+         let r = _mm_blend_epi32(b, a, 0x0E as i32);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_blend_epi32() {
+         let (a, b) = (_mm256_set1_epi32(3), _mm256_set1_epi32(9));
+         let e = _mm256_setr_epi32(9, 3, 3, 3, 3, 3, 3, 3);
+         let r = _mm256_blend_epi32(a, b, 0x01 as i32);
+         assert_eq_m256i(r, e);
+ 
+         let e = _mm256_setr_epi32(3, 9, 3, 3, 3, 3, 3, 9);
+         let r = _mm256_blend_epi32(a, b, 0x82 as i32);
+         assert_eq_m256i(r, e);
+ 
+         let e = _mm256_setr_epi32(3, 3, 9, 9, 9, 9, 9, 3);
+         let r = _mm256_blend_epi32(a, b, 0x7C as i32);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_blend_epi16() {
+         let (a, b) = (_mm256_set1_epi16(3), _mm256_set1_epi16(9));
+         let e = _mm256_setr_epi16(9, 3, 3, 3, 3, 3, 3, 3, 9, 3, 3, 3, 3, 3, 3, 3);
+         let r = _mm256_blend_epi16(a, b, 0x01 as i32);
+         assert_eq_m256i(r, e);
+ 
+         let r = _mm256_blend_epi16(b, a, 0xFE as i32);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_blendv_epi8() {
+         let (a, b) = (_mm256_set1_epi8(4), _mm256_set1_epi8(2));
+         let mask = _mm256_insert_epi8(_mm256_set1_epi8(0), -1, 2);
+         let e = _mm256_insert_epi8(_mm256_set1_epi8(4), 2, 2);
+         let r = _mm256_blendv_epi8(a, b, mask);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_broadcastb_epi8() {
+         let a = _mm_insert_epi8(_mm_set1_epi8(0x00), 0x2a, 0);
+         let res = _mm_broadcastb_epi8(a);
+         assert_eq_m128i(res, _mm_set1_epi8(0x2a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastb_epi8() {
+         let a = _mm_insert_epi8(_mm_set1_epi8(0x00), 0x2a, 0);
+         let res = _mm256_broadcastb_epi8(a);
+         assert_eq_m256i(res, _mm256_set1_epi8(0x2a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_broadcastd_epi32() {
+         let a = _mm_setr_epi32(0x2a, 0x8000000, 0, 0);
+         let res = _mm_broadcastd_epi32(a);
+         assert_eq_m128i(res, _mm_set1_epi32(0x2a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastd_epi32() {
+         let a = _mm_setr_epi32(0x2a, 0x8000000, 0, 0);
+         let res = _mm256_broadcastd_epi32(a);
+         assert_eq_m256i(res, _mm256_set1_epi32(0x2a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_broadcastq_epi64() {
+         let a = _mm_setr_epi64x(0x1ffffffff, 0);
+         let res = _mm_broadcastq_epi64(a);
+         assert_eq_m128i(res, _mm_set1_epi64x(0x1ffffffff));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastq_epi64() {
+         let a = _mm_setr_epi64x(0x1ffffffff, 0);
+         let res = _mm256_broadcastq_epi64(a);
+         assert_eq_m256i(res, _mm256_set1_epi64x(0x1ffffffff));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_broadcastsd_pd() {
+         let a = _mm_setr_pd(6.28, 3.14);
+         let res = _mm_broadcastsd_pd(a);
+         assert_eq_m128d(res, _mm_set1_pd(6.28f64));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastsd_pd() {
+         let a = _mm_setr_pd(6.28, 3.14);
+         let res = _mm256_broadcastsd_pd(a);
+         assert_eq_m256d(res, _mm256_set1_pd(6.28f64));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastsi128_si256() {
+         let a = _mm_setr_epi64x(0x0987654321012334, 0x5678909876543210);
+         let res = _mm256_broadcastsi128_si256(a);
+         let retval = _mm256_setr_epi64x(
+             0x0987654321012334,
+             0x5678909876543210,
+             0x0987654321012334,
+             0x5678909876543210,
+         );
+         assert_eq_m256i(res, retval);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_broadcastss_ps() {
+         let a = _mm_setr_ps(6.28, 3.14, 0.0, 0.0);
+         let res = _mm_broadcastss_ps(a);
+         assert_eq_m128(res, _mm_set1_ps(6.28f32));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastss_ps() {
+         let a = _mm_setr_ps(6.28, 3.14, 0.0, 0.0);
+         let res = _mm256_broadcastss_ps(a);
+         assert_eq_m256(res, _mm256_set1_ps(6.28f32));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_broadcastw_epi16() {
+         let a = _mm_insert_epi16(_mm_set1_epi16(0x2a), 0x22b, 0);
+         let res = _mm_broadcastw_epi16(a);
+         assert_eq_m128i(res, _mm_set1_epi16(0x22b));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_broadcastw_epi16() {
+         let a = _mm_insert_epi16(_mm_set1_epi16(0x2a), 0x22b, 0);
+         let res = _mm256_broadcastw_epi16(a);
+         assert_eq_m256i(res, _mm256_set1_epi16(0x22b));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpeq_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi8(
+             31, 30, 2, 28, 27, 26, 25, 24,
+             23, 22, 21, 20, 19, 18, 17, 16,
+             15, 14, 13, 12, 11, 10, 9, 8,
+             7, 6, 5, 4, 3, 2, 1, 0,
+         );
+         let r = _mm256_cmpeq_epi8(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi8(_mm256_set1_epi8(0), !0, 2));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpeq_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi16(
+             15, 14, 2, 12, 11, 10, 9, 8,
+             7, 6, 5, 4, 3, 2, 1, 0,
+         );
+         let r = _mm256_cmpeq_epi16(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi16(_mm256_set1_epi16(0), !0, 2));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpeq_epi32() {
+         let a = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm256_setr_epi32(7, 6, 2, 4, 3, 2, 1, 0);
+         let r = _mm256_cmpeq_epi32(a, b);
+         let e = _mm256_set1_epi32(0);
+         let e = _mm256_insert_epi32(e, !0, 2);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpeq_epi64() {
+         let a = _mm256_setr_epi64x(0, 1, 2, 3);
+         let b = _mm256_setr_epi64x(3, 2, 2, 0);
+         let r = _mm256_cmpeq_epi64(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi64(_mm256_set1_epi64x(0), !0, 2));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpgt_epi8() {
+         let a = _mm256_insert_epi8(_mm256_set1_epi8(0), 5, 0);
+         let b = _mm256_set1_epi8(0);
+         let r = _mm256_cmpgt_epi8(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi8(_mm256_set1_epi8(0), !0, 0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpgt_epi16() {
+         let a = _mm256_insert_epi16(_mm256_set1_epi16(0), 5, 0);
+         let b = _mm256_set1_epi16(0);
+         let r = _mm256_cmpgt_epi16(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi16(_mm256_set1_epi16(0), !0, 0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpgt_epi32() {
+         let a = _mm256_insert_epi32(_mm256_set1_epi32(0), 5, 0);
+         let b = _mm256_set1_epi32(0);
+         let r = _mm256_cmpgt_epi32(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi32(_mm256_set1_epi32(0), !0, 0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cmpgt_epi64() {
+         let a = _mm256_insert_epi64(_mm256_set1_epi64x(0), 5, 0);
+         let b = _mm256_set1_epi64x(0);
+         let r = _mm256_cmpgt_epi64(a, b);
+         assert_eq_m256i(r, _mm256_insert_epi64(_mm256_set1_epi64x(0), !0, 0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepi8_epi16() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 0, -1, 1, -2, 2, -3, 3,
+             -4, 4, -5, 5, -6, 6, -7, 7,
+         );
+         #[rustfmt::skip]
+         let r = _mm256_setr_epi16(
+             0, 0, -1, 1, -2, 2, -3, 3,
+             -4, 4, -5, 5, -6, 6, -7, 7,
+         );
+         assert_eq_m256i(r, _mm256_cvtepi8_epi16(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepi8_epi32() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 0, -1, 1, -2, 2, -3, 3,
+             -4, 4, -5, 5, -6, 6, -7, 7,
+         );
+         let r = _mm256_setr_epi32(0, 0, -1, 1, -2, 2, -3, 3);
+         assert_eq_m256i(r, _mm256_cvtepi8_epi32(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepi8_epi64() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 0, -1, 1, -2, 2, -3, 3,
+             -4, 4, -5, 5, -6, 6, -7, 7,
+         );
+         let r = _mm256_setr_epi64x(0, 0, -1, 1);
+         assert_eq_m256i(r, _mm256_cvtepi8_epi64(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepi16_epi32() {
+         let a = _mm_setr_epi16(0, 0, -1, 1, -2, 2, -3, 3);
+         let r = _mm256_setr_epi32(0, 0, -1, 1, -2, 2, -3, 3);
+         assert_eq_m256i(r, _mm256_cvtepi16_epi32(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepi16_epi64() {
+         let a = _mm_setr_epi16(0, 0, -1, 1, -2, 2, -3, 3);
+         let r = _mm256_setr_epi64x(0, 0, -1, 1);
+         assert_eq_m256i(r, _mm256_cvtepi16_epi64(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepi32_epi64() {
+         let a = _mm_setr_epi32(0, 0, -1, 1);
+         let r = _mm256_setr_epi64x(0, 0, -1, 1);
+         assert_eq_m256i(r, _mm256_cvtepi32_epi64(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepu16_epi32() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m256i(r, _mm256_cvtepu16_epi32(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepu16_epi64() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm256_setr_epi64x(0, 1, 2, 3);
+         assert_eq_m256i(r, _mm256_cvtepu16_epi64(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepu32_epi64() {
+         let a = _mm_setr_epi32(0, 1, 2, 3);
+         let r = _mm256_setr_epi64x(0, 1, 2, 3);
+         assert_eq_m256i(r, _mm256_cvtepu32_epi64(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepu8_epi16() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let r = _mm256_setr_epi16(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         assert_eq_m256i(r, _mm256_cvtepu8_epi16(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepu8_epi32() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         let r = _mm256_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m256i(r, _mm256_cvtepu8_epi32(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtepu8_epi64() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         let r = _mm256_setr_epi64x(0, 1, 2, 3);
+         assert_eq_m256i(r, _mm256_cvtepu8_epi64(a));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_extracti128_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let r = _mm256_extracti128_si256(a, 0b01);
+         let e = _mm_setr_epi64x(3, 4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_hadd_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_hadd_epi16(a, b);
+         let e = _mm256_setr_epi16(4, 4, 4, 4, 8, 8, 8, 8, 4, 4, 4, 4, 8, 8, 8, 8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_hadd_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_hadd_epi32(a, b);
+         let e = _mm256_setr_epi32(4, 4, 8, 8, 4, 4, 8, 8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_hadds_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let a = _mm256_insert_epi16(a, 0x7fff, 0);
+         let a = _mm256_insert_epi16(a, 1, 1);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_hadds_epi16(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             0x7FFF, 4, 4, 4, 8, 8, 8, 8,
+             4, 4, 4, 4, 8, 8, 8, 8,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_hsub_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_hsub_epi16(a, b);
+         let e = _mm256_set1_epi16(0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_hsub_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_hsub_epi32(a, b);
+         let e = _mm256_set1_epi32(0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_hsubs_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let a = _mm256_insert_epi16(a, 0x7fff, 0);
+         let a = _mm256_insert_epi16(a, -1, 1);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_hsubs_epi16(a, b);
+         let e = _mm256_insert_epi16(_mm256_set1_epi16(0), 0x7FFF, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_madd_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_madd_epi16(a, b);
+         let e = _mm256_set1_epi32(16);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_inserti128_si256() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let b = _mm_setr_epi64x(7, 8);
+         let r = _mm256_inserti128_si256(a, b, 0b01);
+         let e = _mm256_setr_epi64x(1, 2, 7, 8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_maddubs_epi16() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_maddubs_epi16(a, b);
+         let e = _mm256_set1_epi16(16);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_maskload_epi32() {
+         let nums = [1, 2, 3, 4];
+         let a = &nums as *const i32;
+         let mask = _mm_setr_epi32(-1, 0, 0, -1);
+         let r = _mm_maskload_epi32(a, mask);
+         let e = _mm_setr_epi32(1, 0, 0, 4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_maskload_epi32() {
+         let nums = [1, 2, 3, 4, 5, 6, 7, 8];
+         let a = &nums as *const i32;
+         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
+         let r = _mm256_maskload_epi32(a, mask);
+         let e = _mm256_setr_epi32(1, 0, 0, 4, 0, 6, 7, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_maskload_epi64() {
+         let nums = [1_i64, 2_i64];
+         let a = &nums as *const i64;
+         let mask = _mm_setr_epi64x(0, -1);
+         let r = _mm_maskload_epi64(a, mask);
+         let e = _mm_setr_epi64x(0, 2);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_maskload_epi64() {
+         let nums = [1_i64, 2_i64, 3_i64, 4_i64];
+         let a = &nums as *const i64;
+         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
+         let r = _mm256_maskload_epi64(a, mask);
+         let e = _mm256_setr_epi64x(0, 2, 3, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_maskstore_epi32() {
+         let a = _mm_setr_epi32(1, 2, 3, 4);
+         let mut arr = [-1, -1, -1, -1];
+         let mask = _mm_setr_epi32(-1, 0, 0, -1);
+         _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+         let e = [1, -1, -1, 4];
+         assert_eq!(arr, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_maskstore_epi32() {
+         let a = _mm256_setr_epi32(1, 0x6d726f, 3, 42, 0x777161, 6, 7, 8);
+         let mut arr = [-1, -1, -1, 0x776173, -1, 0x68657265, -1, -1];
+         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
+         _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+         let e = [1, -1, -1, 42, -1, 6, 7, -1];
+         assert_eq!(arr, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_maskstore_epi64() {
+         let a = _mm_setr_epi64x(1_i64, 2_i64);
+         let mut arr = [-1_i64, -1_i64];
+         let mask = _mm_setr_epi64x(0, -1);
+         _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+         let e = [-1, 2];
+         assert_eq!(arr, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_maskstore_epi64() {
+         let a = _mm256_setr_epi64x(1_i64, 2_i64, 3_i64, 4_i64);
+         let mut arr = [-1_i64, -1_i64, -1_i64, -1_i64];
+         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
+         _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+         let e = [-1, 2, 3, -1];
+         assert_eq!(arr, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_max_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_max_epi16(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_max_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_max_epi32(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_max_epi8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_max_epi8(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_max_epu16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_max_epu16(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_max_epu32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_max_epu32(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_max_epu8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_max_epu8(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_min_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_min_epi16(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_min_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_min_epi32(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_min_epi8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_min_epi8(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_min_epu16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_min_epu16(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_min_epu32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_min_epu32(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_min_epu8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_min_epu8(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_movemask_epi8() {
+         let a = _mm256_set1_epi8(-1);
+         let r = _mm256_movemask_epi8(a);
+         let e = -1;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mpsadbw_epu8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_mpsadbw_epu8(a, b, 0);
+         let e = _mm256_set1_epi16(8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mul_epi32() {
+         let a = _mm256_setr_epi32(0, 0, 0, 0, 2, 2, 2, 2);
+         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = _mm256_mul_epi32(a, b);
+         let e = _mm256_setr_epi64x(0, 0, 10, 14);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mul_epu32() {
+         let a = _mm256_setr_epi32(0, 0, 0, 0, 2, 2, 2, 2);
+         let b = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = _mm256_mul_epu32(a, b);
+         let e = _mm256_setr_epi64x(0, 0, 10, 14);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mulhi_epi16() {
+         let a = _mm256_set1_epi16(6535);
+         let b = _mm256_set1_epi16(6535);
+         let r = _mm256_mulhi_epi16(a, b);
+         let e = _mm256_set1_epi16(651);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mulhi_epu16() {
+         let a = _mm256_set1_epi16(6535);
+         let b = _mm256_set1_epi16(6535);
+         let r = _mm256_mulhi_epu16(a, b);
+         let e = _mm256_set1_epi16(651);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mullo_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_mullo_epi16(a, b);
+         let e = _mm256_set1_epi16(8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mullo_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_mullo_epi32(a, b);
+         let e = _mm256_set1_epi32(8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mulhrs_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_mullo_epi16(a, b);
+         let e = _mm256_set1_epi16(8);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_or_si256() {
+         let a = _mm256_set1_epi8(-1);
+         let b = _mm256_set1_epi8(0);
+         let r = _mm256_or_si256(a, b);
+         assert_eq_m256i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_packs_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_packs_epi16(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             2, 2, 2, 2, 2, 2, 2, 2,
+             4, 4, 4, 4, 4, 4, 4, 4,
+             2, 2, 2, 2, 2, 2, 2, 2,
+             4, 4, 4, 4, 4, 4, 4, 4,
+         );
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_packs_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_packs_epi32(a, b);
+         let e = _mm256_setr_epi16(2, 2, 2, 2, 4, 4, 4, 4, 2, 2, 2, 2, 4, 4, 4, 4);
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_packus_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(4);
+         let r = _mm256_packus_epi16(a, b);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             2, 2, 2, 2, 2, 2, 2, 2,
+             4, 4, 4, 4, 4, 4, 4, 4,
+             2, 2, 2, 2, 2, 2, 2, 2,
+             4, 4, 4, 4, 4, 4, 4, 4,
+         );
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_packus_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(4);
+         let r = _mm256_packus_epi32(a, b);
+         let e = _mm256_setr_epi16(2, 2, 2, 2, 4, 4, 4, 4, 2, 2, 2, 2, 4, 4, 4, 4);
+ 
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sad_epu8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(4);
+         let r = _mm256_sad_epu8(a, b);
+         let e = _mm256_set1_epi64x(16);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_shufflehi_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             0, 1, 2, 3, 11, 22, 33, 44,
+             4, 5, 6, 7, 55, 66, 77, 88,
+         );
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             0, 1, 2, 3, 44, 22, 22, 11,
+             4, 5, 6, 7, 88, 66, 66, 55,
+         );
+         let r = _mm256_shufflehi_epi16(a, 0b00_01_01_11);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_shufflelo_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             11, 22, 33, 44, 0, 1, 2, 3,
+             55, 66, 77, 88, 4, 5, 6, 7,
+         );
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi16(
+             44, 22, 22, 11, 0, 1, 2, 3,
+             88, 66, 66, 55, 4, 5, 6, 7,
+         );
+         let r = _mm256_shufflelo_epi16(a, 0b00_01_01_11);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sign_epi16() {
+         let a = _mm256_set1_epi16(2);
+         let b = _mm256_set1_epi16(-1);
+         let r = _mm256_sign_epi16(a, b);
+         let e = _mm256_set1_epi16(-2);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sign_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(-1);
+         let r = _mm256_sign_epi32(a, b);
+         let e = _mm256_set1_epi32(-2);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sign_epi8() {
+         let a = _mm256_set1_epi8(2);
+         let b = _mm256_set1_epi8(-1);
+         let r = _mm256_sign_epi8(a, b);
+         let e = _mm256_set1_epi8(-2);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sll_epi16() {
+         let a = _mm256_set1_epi16(0xFF);
+         let b = _mm_insert_epi16(_mm_set1_epi16(0), 4, 0);
+         let r = _mm256_sll_epi16(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi16(0xFF0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sll_epi32() {
+         let a = _mm256_set1_epi32(0xFFFF);
+         let b = _mm_insert_epi32(_mm_set1_epi32(0), 4, 0);
+         let r = _mm256_sll_epi32(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi32(0xFFFF0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sll_epi64() {
+         let a = _mm256_set1_epi64x(0xFFFFFFFF);
+         let b = _mm_insert_epi64(_mm_set1_epi64x(0), 4, 0);
+         let r = _mm256_sll_epi64(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi64x(0xFFFFFFFF0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_slli_epi16() {
+         assert_eq_m256i(
+             _mm256_slli_epi16(_mm256_set1_epi16(0xFF), 4),
+             _mm256_set1_epi16(0xFF0),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_slli_epi32() {
+         assert_eq_m256i(
+             _mm256_slli_epi32(_mm256_set1_epi32(0xFFFF), 4),
+             _mm256_set1_epi32(0xFFFF0),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_slli_epi64() {
+         assert_eq_m256i(
+             _mm256_slli_epi64(_mm256_set1_epi64x(0xFFFFFFFF), 4),
+             _mm256_set1_epi64x(0xFFFFFFFF0),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_slli_si256() {
+         let a = _mm256_set1_epi64x(0xFFFFFFFF);
+         let r = _mm256_slli_si256(a, 3);
+         assert_eq_m256i(r, _mm256_set1_epi64x(0xFFFFFFFF000000));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_sllv_epi32() {
+         let a = _mm_set1_epi32(2);
+         let b = _mm_set1_epi32(1);
+         let r = _mm_sllv_epi32(a, b);
+         let e = _mm_set1_epi32(4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sllv_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let b = _mm256_set1_epi32(1);
+         let r = _mm256_sllv_epi32(a, b);
+         let e = _mm256_set1_epi32(4);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_sllv_epi64() {
+         let a = _mm_set1_epi64x(2);
+         let b = _mm_set1_epi64x(1);
+         let r = _mm_sllv_epi64(a, b);
+         let e = _mm_set1_epi64x(4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sllv_epi64() {
+         let a = _mm256_set1_epi64x(2);
+         let b = _mm256_set1_epi64x(1);
+         let r = _mm256_sllv_epi64(a, b);
+         let e = _mm256_set1_epi64x(4);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sra_epi16() {
+         let a = _mm256_set1_epi16(-1);
+         let b = _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm256_sra_epi16(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi16(-1));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sra_epi32() {
+         let a = _mm256_set1_epi32(-1);
+         let b = _mm_insert_epi32(_mm_set1_epi32(0), 1, 0);
+         let r = _mm256_sra_epi32(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi32(-1));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srai_epi16() {
+         assert_eq_m256i(
+             _mm256_srai_epi16(_mm256_set1_epi16(-1), 1),
+             _mm256_set1_epi16(-1),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srai_epi32() {
+         assert_eq_m256i(
+             _mm256_srai_epi32(_mm256_set1_epi32(-1), 1),
+             _mm256_set1_epi32(-1),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_srav_epi32() {
+         let a = _mm_set1_epi32(4);
+         let count = _mm_set1_epi32(1);
+         let r = _mm_srav_epi32(a, count);
+         let e = _mm_set1_epi32(2);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srav_epi32() {
+         let a = _mm256_set1_epi32(4);
+         let count = _mm256_set1_epi32(1);
+         let r = _mm256_srav_epi32(a, count);
+         let e = _mm256_set1_epi32(2);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srli_si256() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm256_srli_si256(a, 3);
+         #[rustfmt::skip]
+         let e = _mm256_setr_epi8(
+             4, 5, 6, 7, 8, 9, 10, 11,
+             12, 13, 14, 15, 16, 0, 0, 0,
+             20, 21, 22, 23, 24, 25, 26, 27,
+             28, 29, 30, 31, 32, 0, 0, 0,
+         );
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srl_epi16() {
+         let a = _mm256_set1_epi16(0xFF);
+         let b = _mm_insert_epi16(_mm_set1_epi16(0), 4, 0);
+         let r = _mm256_srl_epi16(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi16(0xF));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srl_epi32() {
+         let a = _mm256_set1_epi32(0xFFFF);
+         let b = _mm_insert_epi32(_mm_set1_epi32(0), 4, 0);
+         let r = _mm256_srl_epi32(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi32(0xFFF));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srl_epi64() {
+         let a = _mm256_set1_epi64x(0xFFFFFFFF);
+         let b = _mm_setr_epi64x(4, 0);
+         let r = _mm256_srl_epi64(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi64x(0xFFFFFFF));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srli_epi16() {
+         assert_eq_m256i(
+             _mm256_srli_epi16(_mm256_set1_epi16(0xFF), 4),
+             _mm256_set1_epi16(0xF),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srli_epi32() {
+         assert_eq_m256i(
+             _mm256_srli_epi32(_mm256_set1_epi32(0xFFFF), 4),
+             _mm256_set1_epi32(0xFFF),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srli_epi64() {
+         assert_eq_m256i(
+             _mm256_srli_epi64(_mm256_set1_epi64x(0xFFFFFFFF), 4),
+             _mm256_set1_epi64x(0xFFFFFFF),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_srlv_epi32() {
+         let a = _mm_set1_epi32(2);
+         let count = _mm_set1_epi32(1);
+         let r = _mm_srlv_epi32(a, count);
+         let e = _mm_set1_epi32(1);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srlv_epi32() {
+         let a = _mm256_set1_epi32(2);
+         let count = _mm256_set1_epi32(1);
+         let r = _mm256_srlv_epi32(a, count);
+         let e = _mm256_set1_epi32(1);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_srlv_epi64() {
+         let a = _mm_set1_epi64x(2);
+         let count = _mm_set1_epi64x(1);
+         let r = _mm_srlv_epi64(a, count);
+         let e = _mm_set1_epi64x(1);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_srlv_epi64() {
+         let a = _mm256_set1_epi64x(2);
+         let count = _mm256_set1_epi64x(1);
+         let r = _mm256_srlv_epi64(a, count);
+         let e = _mm256_set1_epi64x(1);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sub_epi16() {
+         let a = _mm256_set1_epi16(4);
+         let b = _mm256_set1_epi16(2);
+         let r = _mm256_sub_epi16(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sub_epi32() {
+         let a = _mm256_set1_epi32(4);
+         let b = _mm256_set1_epi32(2);
+         let r = _mm256_sub_epi32(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sub_epi64() {
+         let a = _mm256_set1_epi64x(4);
+         let b = _mm256_set1_epi64x(2);
+         let r = _mm256_sub_epi64(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_sub_epi8() {
+         let a = _mm256_set1_epi8(4);
+         let b = _mm256_set1_epi8(2);
+         let r = _mm256_sub_epi8(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_subs_epi16() {
+         let a = _mm256_set1_epi16(4);
+         let b = _mm256_set1_epi16(2);
+         let r = _mm256_subs_epi16(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_subs_epi8() {
+         let a = _mm256_set1_epi8(4);
+         let b = _mm256_set1_epi8(2);
+         let r = _mm256_subs_epi8(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_subs_epu16() {
+         let a = _mm256_set1_epi16(4);
+         let b = _mm256_set1_epi16(2);
+         let r = _mm256_subs_epu16(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_subs_epu8() {
+         let a = _mm256_set1_epi8(4);
+         let b = _mm256_set1_epi8(2);
+         let r = _mm256_subs_epu8(a, b);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_xor_si256() {
+         let a = _mm256_set1_epi8(5);
+         let b = _mm256_set1_epi8(3);
+         let r = _mm256_xor_si256(a, b);
+         assert_eq_m256i(r, _mm256_set1_epi8(6));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_alignr_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi8(
+             -1, -2, -3, -4, -5, -6, -7, -8,
+             -9, -10, -11, -12, -13, -14, -15, -16,
+             -17, -18, -19, -20, -21, -22, -23, -24,
+             -25, -26, -27, -28, -29, -30, -31, -32,
+         );
+         let r = _mm256_alignr_epi8(a, b, 33);
+         assert_eq_m256i(r, _mm256_set1_epi8(0));
+ 
+         let r = _mm256_alignr_epi8(a, b, 17);
+         #[rustfmt::skip]
+         let expected = _mm256_setr_epi8(
+             2, 3, 4, 5, 6, 7, 8, 9,
+             10, 11, 12, 13, 14, 15, 16, 0,
+             18, 19, 20, 21, 22, 23, 24, 25,
+             26, 27, 28, 29, 30, 31, 32, 0,
+         );
+         assert_eq_m256i(r, expected);
+ 
+         let r = _mm256_alignr_epi8(a, b, 4);
+         #[rustfmt::skip]
+         let expected = _mm256_setr_epi8(
+             -5, -6, -7, -8, -9, -10, -11, -12,
+             -13, -14, -15, -16, 1, 2, 3, 4,
+             -21, -22, -23, -24, -25, -26, -27, -28,
+             -29, -30, -31, -32, 17, 18, 19, 20,
+         );
+         assert_eq_m256i(r, expected);
+ 
+         #[rustfmt::skip]
+         let expected = _mm256_setr_epi8(
+             -1, -2, -3, -4, -5, -6, -7, -8,
+             -9, -10, -11, -12, -13, -14, -15, -16, -17,
+             -18, -19, -20, -21, -22, -23, -24, -25,
+             -26, -27, -28, -29, -30, -31, -32,
+         );
+         let r = _mm256_alignr_epi8(a, b, 16);
+         assert_eq_m256i(r, expected);
+ 
+         let r = _mm256_alignr_epi8(a, b, 15);
+         #[rustfmt::skip]
+         let expected = _mm256_setr_epi8(
+             -16, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             -32, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         assert_eq_m256i(r, expected);
+ 
+         let r = _mm256_alignr_epi8(a, b, 0);
+         assert_eq_m256i(r, b);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_shuffle_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+             17, 18, 19, 20, 21, 22, 23, 24,
+             25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         #[rustfmt::skip]
+         let b = _mm256_setr_epi8(
+             4, 128u8 as i8, 4, 3, 24, 12, 6, 19,
+             12, 5, 5, 10, 4, 1, 8, 0,
+             4, 128u8 as i8, 4, 3, 24, 12, 6, 19,
+             12, 5, 5, 10, 4, 1, 8, 0,
+         );
+         #[rustfmt::skip]
+         let expected = _mm256_setr_epi8(
+             5, 0, 5, 4, 9, 13, 7, 4,
+             13, 6, 6, 11, 5, 2, 9, 1,
+             21, 0, 21, 20, 25, 29, 23, 20,
+             29, 22, 22, 27, 21, 18, 25, 17,
+         );
+         let r = _mm256_shuffle_epi8(a, b);
+         assert_eq_m256i(r, expected);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_permutevar8x32_epi32() {
+         let a = _mm256_setr_epi32(100, 200, 300, 400, 500, 600, 700, 800);
+         let b = _mm256_setr_epi32(5, 0, 5, 1, 7, 6, 3, 4);
+         let expected = _mm256_setr_epi32(600, 100, 600, 200, 800, 700, 400, 500);
+         let r = _mm256_permutevar8x32_epi32(a, b);
+         assert_eq_m256i(r, expected);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_permute4x64_epi64() {
+         let a = _mm256_setr_epi64x(100, 200, 300, 400);
+         let expected = _mm256_setr_epi64x(400, 100, 200, 100);
+         let r = _mm256_permute4x64_epi64(a, 0b00010011);
+         assert_eq_m256i(r, expected);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_permute2x128_si256() {
+         let a = _mm256_setr_epi64x(100, 200, 500, 600);
+         let b = _mm256_setr_epi64x(300, 400, 700, 800);
+         let r = _mm256_permute2x128_si256(a, b, 0b00_01_00_11);
+         let e = _mm256_setr_epi64x(700, 800, 500, 600);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_permute4x64_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let r = _mm256_permute4x64_pd(a, 0b00_01_00_11);
+         let e = _mm256_setr_pd(4., 1., 2., 1.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_permutevar8x32_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_epi32(5, 0, 5, 1, 7, 6, 3, 4);
+         let r = _mm256_permutevar8x32_ps(a, b);
+         let e = _mm256_setr_ps(6., 1., 6., 2., 8., 7., 4., 5.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i32gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm_i32gather_epi32(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48), 4);
+         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i32gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm_mask_i32gather_epi32(
+             _mm_set1_epi32(256),
+             arr.as_ptr(),
+             _mm_setr_epi32(0, 16, 64, 96),
+             _mm_setr_epi32(-1, -1, -1, 0),
+             4,
+         );
+         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i32gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm256_i32gather_epi32(
+             arr.as_ptr(),
+             _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4),
+             4,
+         );
+         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i32gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm256_mask_i32gather_epi32(
+             _mm256_set1_epi32(256),
+             arr.as_ptr(),
+             _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
+             _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0),
+             4,
+         );
+         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 64, 256, 256, 256, 256, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i32gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm_i32gather_ps(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48), 4);
+         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i32gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm_mask_i32gather_ps(
+             _mm_set1_ps(256.0),
+             arr.as_ptr(),
+             _mm_setr_epi32(0, 16, 64, 96),
+             _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
+             4,
+         );
+         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i32gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm256_i32gather_ps(
+             arr.as_ptr(),
+             _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4),
+             4,
+         );
+         assert_eq_m256(r, _mm256_setr_ps(0.0, 16.0, 32.0, 48.0, 1.0, 2.0, 3.0, 4.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i32gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm256_mask_i32gather_ps(
+             _mm256_set1_ps(256.0),
+             arr.as_ptr(),
+             _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
+             _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0),
+             4,
+         );
+         assert_eq_m256(
+             r,
+             _mm256_setr_ps(0.0, 16.0, 64.0, 256.0, 256.0, 256.0, 256.0, 256.0),
+         );
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i32gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm_i32gather_epi64(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0), 8);
+         assert_eq_m128i(r, _mm_setr_epi64x(0, 16));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i32gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm_mask_i32gather_epi64(
+             _mm_set1_epi64x(256),
+             arr.as_ptr(),
+             _mm_setr_epi32(16, 16, 16, 16),
+             _mm_setr_epi64x(-1, 0),
+             8,
+         );
+         assert_eq_m128i(r, _mm_setr_epi64x(16, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i32gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm256_i32gather_epi64(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48), 8);
+         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i32gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm256_mask_i32gather_epi64(
+             _mm256_set1_epi64x(256),
+             arr.as_ptr(),
+             _mm_setr_epi32(0, 16, 64, 96),
+             _mm256_setr_epi64x(-1, -1, -1, 0),
+             8,
+         );
+         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i32gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm_i32gather_pd(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0), 8);
+         assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i32gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm_mask_i32gather_pd(
+             _mm_set1_pd(256.0),
+             arr.as_ptr(),
+             _mm_setr_epi32(16, 16, 16, 16),
+             _mm_setr_pd(-1.0, 0.0),
+             8,
+         );
+         assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i32gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm256_i32gather_pd(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48), 8);
+         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i32gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm256_mask_i32gather_pd(
+             _mm256_set1_pd(256.0),
+             arr.as_ptr(),
+             _mm_setr_epi32(0, 16, 64, 96),
+             _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
+             8,
+         );
+         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i64gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm_i64gather_epi32(arr.as_ptr(), _mm_setr_epi64x(0, 16), 4);
+         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 0, 0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i64gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm_mask_i64gather_epi32(
+             _mm_set1_epi32(256),
+             arr.as_ptr(),
+             _mm_setr_epi64x(0, 16),
+             _mm_setr_epi32(-1, 0, -1, 0),
+             4,
+         );
+         assert_eq_m128i(r, _mm_setr_epi32(0, 256, 0, 0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i64gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm256_i64gather_epi32(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48), 4);
+         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i64gather_epi32() {
+         let mut arr = [0i32; 128];
+         for i in 0..128i32 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 4 is word-addressing
+         let r = _mm256_mask_i64gather_epi32(
+             _mm_set1_epi32(256),
+             arr.as_ptr(),
+             _mm256_setr_epi64x(0, 16, 64, 96),
+             _mm_setr_epi32(-1, -1, -1, 0),
+             4,
+         );
+         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i64gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm_i64gather_ps(arr.as_ptr(), _mm_setr_epi64x(0, 16), 4);
+         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 0.0, 0.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i64gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm_mask_i64gather_ps(
+             _mm_set1_ps(256.0),
+             arr.as_ptr(),
+             _mm_setr_epi64x(0, 16),
+             _mm_setr_ps(-1.0, 0.0, -1.0, 0.0),
+             4,
+         );
+         assert_eq_m128(r, _mm_setr_ps(0.0, 256.0, 0.0, 0.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i64gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm256_i64gather_ps(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48), 4);
+         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i64gather_ps() {
+         let mut arr = [0.0f32; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 4 is word-addressing for f32s
+         let r = _mm256_mask_i64gather_ps(
+             _mm_set1_ps(256.0),
+             arr.as_ptr(),
+             _mm256_setr_epi64x(0, 16, 64, 96),
+             _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
+             4,
+         );
+         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i64gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm_i64gather_epi64(arr.as_ptr(), _mm_setr_epi64x(0, 16), 8);
+         assert_eq_m128i(r, _mm_setr_epi64x(0, 16));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i64gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm_mask_i64gather_epi64(
+             _mm_set1_epi64x(256),
+             arr.as_ptr(),
+             _mm_setr_epi64x(16, 16),
+             _mm_setr_epi64x(-1, 0),
+             8,
+         );
+         assert_eq_m128i(r, _mm_setr_epi64x(16, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i64gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm256_i64gather_epi64(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48), 8);
+         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i64gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing for i64s
+         let r = _mm256_mask_i64gather_epi64(
+             _mm256_set1_epi64x(256),
+             arr.as_ptr(),
+             _mm256_setr_epi64x(0, 16, 64, 96),
+             _mm256_setr_epi64x(-1, -1, -1, 0),
+             8,
+         );
+         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_i64gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm_i64gather_pd(arr.as_ptr(), _mm_setr_epi64x(0, 16), 8);
+         assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm_mask_i64gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm_mask_i64gather_pd(
+             _mm_set1_pd(256.0),
+             arr.as_ptr(),
+             _mm_setr_epi64x(16, 16),
+             _mm_setr_pd(-1.0, 0.0),
+             8,
+         );
+         assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_i64gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm256_i64gather_pd(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48), 8);
+         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0));
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_mask_i64gather_pd() {
+         let mut arr = [0.0f64; 128];
+         let mut j = 0.0;
+         for i in 0..128usize {
+             arr[i] = j;
+             j += 1.0;
+         }
+         // A multiplier of 8 is word-addressing for f64s
+         let r = _mm256_mask_i64gather_pd(
+             _mm256_set1_pd(256.0),
+             arr.as_ptr(),
+             _mm256_setr_epi64x(0, 16, 64, 96),
+             _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
+             8,
+         );
+         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
+     }
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_extract_epi8() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi8(
+             -1, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+             16, 17, 18, 19, 20, 21, 22, 23,
+             24, 25, 26, 27, 28, 29, 30, 31
+         );
+         let r1 = _mm256_extract_epi8(a, 0);
+         let r2 = _mm256_extract_epi8(a, 35);
+         assert_eq!(r1, 0xFF);
+         assert_eq!(r2, 3);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_extract_epi16() {
+         #[rustfmt::skip]
+         let a = _mm256_setr_epi16(
+             -1, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         let r1 = _mm256_extract_epi16(a, 0);
+         let r2 = _mm256_extract_epi16(a, 19);
+         assert_eq!(r1, 0xFFFF);
+         assert_eq!(r2, 3);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_extract_epi32() {
+         let a = _mm256_setr_epi32(-1, 1, 2, 3, 4, 5, 6, 7);
+         let r1 = _mm256_extract_epi32(a, 0);
+         let r2 = _mm256_extract_epi32(a, 11);
+         assert_eq!(r1, -1);
+         assert_eq!(r2, 3);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtsd_f64() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let r = _mm256_cvtsd_f64(a);
+         assert_eq!(r, 1.);
+     }
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_cvtsi256_si32() {
+         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         let r = _mm256_cvtsi256_si32(a);
+         assert_eq!(r, 1);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512f.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512f.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512f.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512f.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,20921 ----
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     mem::{self, transmute},
+     ptr,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Computes the absolute values of packed 32-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512F&expand=33,34,4990,33&text=_mm512_abs_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpabsd))]
+ pub unsafe fn _mm512_abs_epi32(a: __m512i) -> __m512i {
+     let a = a.as_i32x16();
+     // all-0 is a properly initialized i32x16
+     let zero: i32x16 = mem::zeroed();
+     let sub = simd_sub(zero, a);
+     let cmp: i32x16 = simd_gt(a, zero);
+     transmute(simd_select(cmp, a, sub))
+ }
+ 
+ /// Computes the absolute value of packed 32-bit integers in `a`, and store the
+ /// unsigned results in `dst` using writemask `k` (elements are copied from
+ /// `src` when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512F&expand=33,34,4990,33&text=_mm512_abs_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpabsd))]
+ pub unsafe fn _mm512_mask_abs_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
+     let abs = _mm512_abs_epi32(a).as_i32x16();
+     transmute(simd_select_bitmask(k, abs, src.as_i32x16()))
+ }
+ 
+ /// Computes the absolute value of packed 32-bit integers in `a`, and store the
+ /// unsigned results in `dst` using zeromask `k` (elements are zeroed out when
+ /// the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512F&expand=33,34,4990,33,34,35,35&text=_mm512_maskz_abs_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpabsd))]
+ pub unsafe fn _mm512_maskz_abs_epi32(k: __mmask16, a: __m512i) -> __m512i {
+     let abs = _mm512_abs_epi32(a).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, abs, zero))
+ }
+ 
+ /// Compute the absolute value of packed signed 64-bit integers in a, and store the unsigned results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_abs_epi64&expand=48)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpabsq))]
+ pub unsafe fn _mm512_abs_epi64(a: __m512i) -> __m512i {
+     let a = a.as_i64x8();
+     // all-0 is a properly initialized i64x8
+     let zero: i64x8 = mem::zeroed();
+     let sub = simd_sub(zero, a);
+     let cmp: i64x8 = simd_gt(a, zero);
+     transmute(simd_select(cmp, a, sub))
+ }
+ 
+ /// Compute the absolute value of packed signed 64-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_abs_epi64&expand=49)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpabsq))]
+ pub unsafe fn _mm512_mask_abs_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
+     let abs = _mm512_abs_epi64(a).as_i64x8();
+     transmute(simd_select_bitmask(k, abs, src.as_i64x8()))
+ }
+ 
+ /// Compute the absolute value of packed signed 64-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_abs_epi64&expand=50)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpabsq))]
+ pub unsafe fn _mm512_maskz_abs_epi64(k: __mmask8, a: __m512i) -> __m512i {
+     let abs = _mm512_abs_epi64(a).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, abs, zero))
+ }
+ 
+ /// Finds the absolute value of each packed single-precision (32-bit) floating-point element in v2, storing the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_abs_ps&expand=65)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_abs_ps(v2: __m512) -> __m512 {
+     let a = _mm512_set1_epi32(0x7FFFFFFF); // from LLVM code
+     let b = transmute::<f32x16, __m512i>(v2.as_f32x16());
+     let abs = _mm512_and_epi32(a, b);
+     transmute(abs)
+ }
+ 
+ /// Finds the absolute value of each packed single-precision (32-bit) floating-point element in v2, storing the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_abs_ps&expand=66)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandd))]
+ pub unsafe fn _mm512_mask_abs_ps(src: __m512, k: __mmask16, v2: __m512) -> __m512 {
+     let abs = _mm512_abs_ps(v2).as_f32x16();
+     transmute(simd_select_bitmask(k, abs, src.as_f32x16()))
+ }
+ 
+ /// Finds the absolute value of each packed double-precision (64-bit) floating-point element in v2, storing the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_abs_pd&expand=60)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_abs_pd(v2: __m512d) -> __m512d {
+     let a = _mm512_set1_epi64(0x7FFFFFFFFFFFFFFF); // from LLVM code
+     let b = transmute::<f64x8, __m512i>(v2.as_f64x8());
+     let abs = _mm512_and_epi64(a, b);
+     transmute(abs)
+ }
+ 
+ /// Finds the absolute value of each packed double-precision (64-bit) floating-point element in v2, storing the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_abs_pd&expand=61)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_mask_abs_pd(src: __m512d, k: __mmask8, v2: __m512d) -> __m512d {
+     let abs = _mm512_abs_pd(v2).as_f64x8();
+     transmute(simd_select_bitmask(k, abs, src.as_f64x8()))
+ }
+ 
+ /// Add packed 32-bit integers in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_add_epi32&expand=100)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpaddd))]
+ pub unsafe fn _mm512_add_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_add(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Add packed 32-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_add_epi32&expand=101)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpaddd))]
+ pub unsafe fn _mm512_mask_add_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let add = _mm512_add_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, add, src.as_i32x16()))
+ }
+ 
+ /// Add packed 32-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_add_epi32&expand=102)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpaddd))]
+ pub unsafe fn _mm512_maskz_add_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let add = _mm512_add_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, add, zero))
+ }
+ 
+ /// Add packed 64-bit integers in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_add_epi64&expand=109)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpaddq))]
+ pub unsafe fn _mm512_add_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_add(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Add packed 64-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_add_epi64&expand=110)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpaddq))]
+ pub unsafe fn _mm512_mask_add_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let add = _mm512_add_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, add, src.as_i64x8()))
+ }
+ 
+ /// Add packed 64-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_add_epi64&expand=111)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpaddq))]
+ pub unsafe fn _mm512_maskz_add_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let add = _mm512_add_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, add, zero))
+ }
+ 
+ /// Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_add_ps&expand=139)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddps))]
+ pub unsafe fn _mm512_add_ps(a: __m512, b: __m512) -> __m512 {
+     transmute(simd_add(a.as_f32x16(), b.as_f32x16()))
+ }
+ 
+ /// Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_add_ps&expand=140)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddps))]
+ pub unsafe fn _mm512_mask_add_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let add = _mm512_add_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, add, src.as_f32x16()))
+ }
+ 
+ /// Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_add_ps&expand=141)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddps))]
+ pub unsafe fn _mm512_maskz_add_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let add = _mm512_add_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, add, zero))
+ }
+ 
+ /// Add packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_add_pd&expand=127)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddpd))]
+ pub unsafe fn _mm512_add_pd(a: __m512d, b: __m512d) -> __m512d {
+     transmute(simd_add(a.as_f64x8(), b.as_f64x8()))
+ }
+ 
+ /// Add packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_add_pd&expand=128)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddpd))]
+ pub unsafe fn _mm512_mask_add_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let add = _mm512_add_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, add, src.as_f64x8()))
+ }
+ 
+ /// Add packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_add_pd&expand=129)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddpd))]
+ pub unsafe fn _mm512_maskz_add_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let add = _mm512_add_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, add, zero))
+ }
+ 
+ /// Subtract packed 32-bit integers in b from packed 32-bit integers in a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sub_epi32&expand=5694)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsubd))]
+ pub unsafe fn _mm512_sub_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_sub(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Subtract packed 32-bit integers in b from packed 32-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sub_epi32&expand=5692)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsubd))]
+ pub unsafe fn _mm512_mask_sub_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let sub = _mm512_sub_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, sub, src.as_i32x16()))
+ }
+ 
+ /// Subtract packed 32-bit integers in b from packed 32-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sub_epi32&expand=5693)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsubd))]
+ pub unsafe fn _mm512_maskz_sub_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let sub = _mm512_sub_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, sub, zero))
+ }
+ 
+ /// Subtract packed 64-bit integers in b from packed 64-bit integers in a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sub_epi64&expand=5703)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsubq))]
+ pub unsafe fn _mm512_sub_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_sub(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Subtract packed 64-bit integers in b from packed 64-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sub_epi64&expand=5701)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsubq))]
+ pub unsafe fn _mm512_mask_sub_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let sub = _mm512_sub_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, sub, src.as_i64x8()))
+ }
+ 
+ /// Subtract packed 64-bit integers in b from packed 64-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sub_epi64&expand=5702)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsubq))]
+ pub unsafe fn _mm512_maskz_sub_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let add = _mm512_sub_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, add, zero))
+ }
+ 
+ /// Subtract packed single-precision (32-bit) floating-point elements in b from packed single-precision (32-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sub_ps&expand=5733)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubps))]
+ pub unsafe fn _mm512_sub_ps(a: __m512, b: __m512) -> __m512 {
+     transmute(simd_sub(a.as_f32x16(), b.as_f32x16()))
+ }
+ 
+ /// Subtract packed single-precision (32-bit) floating-point elements in b from packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sub_ps&expand=5731)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubps))]
+ pub unsafe fn _mm512_mask_sub_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let sub = _mm512_sub_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, sub, src.as_f32x16()))
+ }
+ 
+ /// Subtract packed single-precision (32-bit) floating-point elements in b from packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sub_ps&expand=5732)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubps))]
+ pub unsafe fn _mm512_maskz_sub_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let sub = _mm512_sub_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, sub, zero))
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sub_pd&expand=5721)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubpd))]
+ pub unsafe fn _mm512_sub_pd(a: __m512d, b: __m512d) -> __m512d {
+     transmute(simd_sub(a.as_f64x8(), b.as_f64x8()))
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sub_pd&expand=5719)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubpd))]
+ pub unsafe fn _mm512_mask_sub_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let sub = _mm512_sub_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, sub, src.as_f64x8()))
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sub_pd&expand=5720)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubpd))]
+ pub unsafe fn _mm512_maskz_sub_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let sub = _mm512_sub_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, sub, zero))
+ }
+ 
+ /// Multiply the low signed 32-bit integers from each packed 64-bit element in a and b, and store the signed 64-bit results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mul_epi32&expand=3907)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmuldq))]
+ pub unsafe fn _mm512_mul_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpmuldq(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Multiply the low signed 32-bit integers from each packed 64-bit element in a and b, and store the signed 64-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mul_epi32&expand=3905)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmuldq))]
+ pub unsafe fn _mm512_mask_mul_epi32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let mul = _mm512_mul_epi32(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, mul, src.as_i64x8()))
+ }
+ 
+ /// Multiply the low signed 32-bit integers from each packed 64-bit element in a and b, and store the signed 64-bit results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mul_epi32&expand=3906)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmuldq))]
+ pub unsafe fn _mm512_maskz_mul_epi32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let mul = _mm512_mul_epi32(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, mul, zero))
+ }
+ 
+ /// Multiply the packed 32-bit integers in a and b, producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mullo_epi&expand=4005)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmulld))]
+ pub unsafe fn _mm512_mullo_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_mul(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Multiply the packed 32-bit integers in a and b, producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mullo_epi32&expand=4003)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmulld))]
+ pub unsafe fn _mm512_mask_mullo_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let mul = _mm512_mullo_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, mul, src.as_i32x16()))
+ }
+ 
+ /// Multiply the packed 32-bit integers in a and b, producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mullo_epi32&expand=4004)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmulld))]
+ pub unsafe fn _mm512_maskz_mullo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let mul = _mm512_mullo_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, mul, zero))
+ }
+ 
+ /// Multiplies elements in packed 64-bit integer vectors a and b together, storing the lower 64 bits of the result in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mullox_epi64&expand=4017)
+ ///
+ /// This intrinsic generates a sequence of instructions, which may perform worse than a native instruction. Consider the performance impact of this intrinsic.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_mullox_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_mul(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Multiplies elements in packed 64-bit integer vectors a and b together, storing the lower 64 bits of the result in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mullox&expand=4016)
+ ///
+ /// This intrinsic generates a sequence of instructions, which may perform worse than a native instruction. Consider the performance impact of this intrinsic.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_mask_mullox_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let mul = _mm512_mullox_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, mul, src.as_i64x8()))
+ }
+ 
+ /// Multiply the low unsigned 32-bit integers from each packed 64-bit element in a and b, and store the unsigned 64-bit results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mul_epu32&expand=3916)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmuludq))]
+ pub unsafe fn _mm512_mul_epu32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpmuludq(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Multiply the low unsigned 32-bit integers from each packed 64-bit element in a and b, and store the unsigned 64-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mul_epu32&expand=3914)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmuludq))]
+ pub unsafe fn _mm512_mask_mul_epu32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let mul = _mm512_mul_epu32(a, b).as_u64x8();
+     transmute(simd_select_bitmask(k, mul, src.as_u64x8()))
+ }
+ 
+ /// Multiply the low unsigned 32-bit integers from each packed 64-bit element in a and b, and store the unsigned 64-bit results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mul_epu32&expand=3915)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmuludq))]
+ pub unsafe fn _mm512_maskz_mul_epu32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let mul = _mm512_mul_epu32(a, b).as_u64x8();
+     let zero = _mm512_setzero_si512().as_u64x8();
+     transmute(simd_select_bitmask(k, mul, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm512_mul_ps&expand=3934)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulps))]
+ pub unsafe fn _mm512_mul_ps(a: __m512, b: __m512) -> __m512 {
+     transmute(simd_mul(a.as_f32x16(), b.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). RM.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mul_ps&expand=3932)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulps))]
+ pub unsafe fn _mm512_mask_mul_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let mul = _mm512_mul_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, mul, src.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mul_ps&expand=3933)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulps))]
+ pub unsafe fn _mm512_maskz_mul_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let mul = _mm512_mul_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, mul, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mul_pd&expand=3925)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulpd))]
+ pub unsafe fn _mm512_mul_pd(a: __m512d, b: __m512d) -> __m512d {
+     transmute(simd_mul(a.as_f64x8(), b.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). RM.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mul_pd&expand=3923)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulpd))]
+ pub unsafe fn _mm512_mask_mul_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let mul = _mm512_mul_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, mul, src.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mul_pd&expand=3924)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulpd))]
+ pub unsafe fn _mm512_maskz_mul_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let mul = _mm512_mul_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, mul, zero))
+ }
+ 
+ /// Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_div_ps&expand=2162)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivps))]
+ pub unsafe fn _mm512_div_ps(a: __m512, b: __m512) -> __m512 {
+     transmute(simd_div(a.as_f32x16(), b.as_f32x16()))
+ }
+ 
+ /// Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_div_ps&expand=2163)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivps))]
+ pub unsafe fn _mm512_mask_div_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let div = _mm512_div_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, div, src.as_f32x16()))
+ }
+ 
+ /// Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_div_ps&expand=2164)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivps))]
+ pub unsafe fn _mm512_maskz_div_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let div = _mm512_div_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, div, zero))
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_div_pd&expand=2153)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivpd))]
+ pub unsafe fn _mm512_div_pd(a: __m512d, b: __m512d) -> __m512d {
+     transmute(simd_div(a.as_f64x8(), b.as_f64x8()))
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_div_pd&expand=2154)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivpd))]
+ pub unsafe fn _mm512_mask_div_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let div = _mm512_div_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, div, src.as_f64x8()))
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_div_pd&expand=2155)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivpd))]
+ pub unsafe fn _mm512_maskz_div_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let div = _mm512_div_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, div, zero))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b, and store packed maximum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_max_epi32&expand=3582)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxsd))]
+ pub unsafe fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpmaxsd(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_epi32&expand=3580)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxsd))]
+ pub unsafe fn _mm512_mask_max_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, max, src.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_epi32&expand=3581)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxsd))]
+ pub unsafe fn _mm512_maskz_max_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b, and store packed maximum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_max_epi64&expand=3591)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxsq))]
+ pub unsafe fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpmaxsq(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_epi64&expand=3589)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxsq))]
+ pub unsafe fn _mm512_mask_max_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, max, src.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_epi64&expand=3590)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxsq))]
+ pub unsafe fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_max_ps&expand=3655)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxps))]
+ pub unsafe fn _mm512_max_ps(a: __m512, b: __m512) -> __m512 {
+     transmute(vmaxps(
+         a.as_f32x16(),
+         b.as_f32x16(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_ps&expand=3653)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxps))]
+ pub unsafe fn _mm512_mask_max_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let max = _mm512_max_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, max, src.as_f32x16()))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_ps&expand=3654)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxps))]
+ pub unsafe fn _mm512_maskz_max_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let max = _mm512_max_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_max_pd&expand=3645)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxpd))]
+ pub unsafe fn _mm512_max_pd(a: __m512d, b: __m512d) -> __m512d {
+     transmute(vmaxpd(a.as_f64x8(), b.as_f64x8(), _MM_FROUND_CUR_DIRECTION))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_pd&expand=3643)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxpd))]
+ pub unsafe fn _mm512_mask_max_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let max = _mm512_max_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, max, src.as_f64x8()))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_pd&expand=3644)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxpd))]
+ pub unsafe fn _mm512_maskz_max_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let max = _mm512_max_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b, and store packed maximum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_max_epu32&expand=3618)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxud))]
+ pub unsafe fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpmaxud(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_epu32&expand=3616)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxud))]
+ pub unsafe fn _mm512_mask_max_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epu32(a, b).as_u32x16();
+     transmute(simd_select_bitmask(k, max, src.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_epu32&expand=3617)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxud))]
+ pub unsafe fn _mm512_maskz_max_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epu32(a, b).as_u32x16();
+     let zero = _mm512_setzero_si512().as_u32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b, and store packed maximum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=max_epu64&expand=3627)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxuq))]
+ pub unsafe fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpmaxuq(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_epu64&expand=3625)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxuq))]
+ pub unsafe fn _mm512_mask_max_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epu64(a, b).as_u64x8();
+     transmute(simd_select_bitmask(k, max, src.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_epu&expand=3626)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpmaxuq))]
+ pub unsafe fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_max_epu64(a, b).as_u64x8();
+     let zero = _mm512_setzero_si512().as_u64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b, and store packed minimum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_epi32&expand=3696)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminsd))]
+ pub unsafe fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpminsd(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_epi32&expand=3694)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminsd))]
+ pub unsafe fn _mm512_mask_min_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, max, src.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_epi32&expand=3695)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminsd))]
+ pub unsafe fn _mm512_maskz_min_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b, and store packed minimum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_epi64&expand=3705)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminsq))]
+ pub unsafe fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpminsq(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_epi64&expand=3703)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminsq))]
+ pub unsafe fn _mm512_mask_min_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, max, src.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_epi64&expand=3704)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminsq))]
+ pub unsafe fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_ps&expand=3769)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminps))]
+ pub unsafe fn _mm512_min_ps(a: __m512, b: __m512) -> __m512 {
+     transmute(vminps(
+         a.as_f32x16(),
+         b.as_f32x16(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_ps&expand=3767)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminps))]
+ pub unsafe fn _mm512_mask_min_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let max = _mm512_min_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, max, src.as_f32x16()))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_ps&expand=3768)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminps))]
+ pub unsafe fn _mm512_maskz_min_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let max = _mm512_min_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_pd&expand=3759)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminpd))]
+ pub unsafe fn _mm512_min_pd(a: __m512d, b: __m512d) -> __m512d {
+     transmute(vminpd(a.as_f64x8(), b.as_f64x8(), _MM_FROUND_CUR_DIRECTION))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_pd&expand=3757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminpd))]
+ pub unsafe fn _mm512_mask_min_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let max = _mm512_min_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, max, src.as_f64x8()))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_pd&expand=3758)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminpd))]
+ pub unsafe fn _mm512_maskz_min_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let max = _mm512_min_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b, and store packed minimum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_epu32&expand=3732)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminud))]
+ pub unsafe fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpminud(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_epu32&expand=3730)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminud))]
+ pub unsafe fn _mm512_mask_min_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epu32(a, b).as_u32x16();
+     transmute(simd_select_bitmask(k, max, src.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_epu32&expand=3731)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminud))]
+ pub unsafe fn _mm512_maskz_min_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epu32(a, b).as_u32x16();
+     let zero = _mm512_setzero_si512().as_u32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b, and store packed minimum values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_epu64&expand=3741)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminuq))]
+ pub unsafe fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vpminuq(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_epu64&expand=3739)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminuq))]
+ pub unsafe fn _mm512_mask_min_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epu64(a, b).as_u64x8();
+     transmute(simd_select_bitmask(k, max, src.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_epu64&expand=3740)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpminuq))]
+ pub unsafe fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let max = _mm512_min_epu64(a, b).as_u64x8();
+     let zero = _mm512_setzero_si512().as_u64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sqrt_ps&expand=5371)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtps))]
+ pub unsafe fn _mm512_sqrt_ps(a: __m512) -> __m512 {
+     transmute(vsqrtps(a.as_f32x16(), _MM_FROUND_CUR_DIRECTION))
+ }
+ 
+ /// Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sqrt_ps&expand=5369)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtps))]
+ pub unsafe fn _mm512_mask_sqrt_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+     let sqrt = _mm512_sqrt_ps(a).as_f32x16();
+     transmute(simd_select_bitmask(k, sqrt, src.as_f32x16()))
+ }
+ 
+ /// Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sqrt_ps&expand=5370)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtps))]
+ pub unsafe fn _mm512_maskz_sqrt_ps(k: __mmask16, a: __m512) -> __m512 {
+     let sqrt = _mm512_sqrt_ps(a).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, sqrt, zero))
+ }
+ 
+ /// Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sqrt_pd&expand=5362)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtpd))]
+ pub unsafe fn _mm512_sqrt_pd(a: __m512d) -> __m512d {
+     transmute(vsqrtpd(a.as_f64x8(), _MM_FROUND_CUR_DIRECTION))
+ }
+ 
+ /// Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sqrt_pd&expand=5360)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtpd))]
+ pub unsafe fn _mm512_mask_sqrt_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+     let sqrt = _mm512_sqrt_pd(a).as_f64x8();
+     transmute(simd_select_bitmask(k, sqrt, src.as_f64x8()))
+ }
+ 
+ /// Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sqrt_pd&expand=5361)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtpd))]
+ pub unsafe fn _mm512_maskz_sqrt_pd(k: __mmask8, a: __m512d) -> __m512d {
+     let sqrt = _mm512_sqrt_pd(a).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, sqrt, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=fmadd_ps&expand=2557)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ pub unsafe fn _mm512_fmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+     transmute(vfmadd132ps(
+         a.as_f32x16(),
+         b.as_f32x16(),
+         c.as_f32x16(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmadd_ps&expand=2558)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ pub unsafe fn _mm512_mask_fmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+     let fmadd = _mm512_fmadd_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmadd, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmadd_ps&expand=2560)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ pub unsafe fn _mm512_maskz_fmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+     let fmadd = _mm512_fmadd_ps(a, b, c).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fmadd, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmadd_ps&expand=2559)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ pub unsafe fn _mm512_mask3_fmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+     let fmadd = _mm512_fmadd_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmadd, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmadd_pd&expand=2545)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ pub unsafe fn _mm512_fmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     transmute(vfmadd132pd(
+         a.as_f64x8(),
+         b.as_f64x8(),
+         c.as_f64x8(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmadd_pd&expand=2546)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ pub unsafe fn _mm512_mask_fmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+     let fmadd = _mm512_fmadd_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmadd, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmadd_pd&expand=2548)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ pub unsafe fn _mm512_maskz_fmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let fmadd = _mm512_fmadd_pd(a, b, c).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fmadd, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmadd_pd&expand=2547)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ pub unsafe fn _mm512_mask3_fmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+     let fmadd = _mm512_fmadd_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmadd, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsub_ps&expand=2643)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
+ pub unsafe fn _mm512_fmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     transmute(vfmadd132ps(
+         a.as_f32x16(),
+         b.as_f32x16(),
+         sub,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsub_ps&expand=2644)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
+ pub unsafe fn _mm512_mask_fmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+     let fmsub = _mm512_fmsub_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmsub, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsub_ps&expand=2646)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
+ pub unsafe fn _mm512_maskz_fmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+     let fmsub = _mm512_fmsub_ps(a, b, c).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fmsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsub_ps&expand=2645)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub
+ pub unsafe fn _mm512_mask3_fmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+     let fmsub = _mm512_fmsub_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmsub, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsub_pd&expand=2631)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
+ pub unsafe fn _mm512_fmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     transmute(vfmadd132pd(
+         a.as_f64x8(),
+         b.as_f64x8(),
+         sub,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsub_pd&expand=2632)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
+ pub unsafe fn _mm512_mask_fmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+     let fmsub = _mm512_fmsub_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmsub, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsub_pd&expand=2634)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
+ pub unsafe fn _mm512_maskz_fmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let fmsub = _mm512_fmsub_pd(a, b, c).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fmsub, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsub_pd&expand=2633)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub
+ pub unsafe fn _mm512_mask3_fmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+     let fmsub = _mm512_fmsub_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmsub, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmaddsub_ps&expand=2611)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ pub unsafe fn _mm512_fmaddsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+     transmute(vfmaddsub213ps(
+         a.as_f32x16(),
+         b.as_f32x16(),
+         c.as_f32x16(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmaddsub_ps&expand=2612)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ pub unsafe fn _mm512_mask_fmaddsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+     let fmaddsub = _mm512_fmaddsub_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmaddsub, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmaddsub_ps&expand=2614)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ pub unsafe fn _mm512_maskz_fmaddsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+     let fmaddsub = _mm512_fmaddsub_ps(a, b, c).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fmaddsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmaddsub_ps&expand=2613)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ pub unsafe fn _mm512_mask3_fmaddsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+     let fmaddsub = _mm512_fmaddsub_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmaddsub, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmaddsub_pd&expand=2599)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ pub unsafe fn _mm512_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     transmute(vfmaddsub213pd(
+         a.as_f64x8(),
+         b.as_f64x8(),
+         c.as_f64x8(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmaddsub_pd&expand=2600)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ pub unsafe fn _mm512_mask_fmaddsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+     let fmaddsub = _mm512_fmaddsub_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmaddsub, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmaddsub_pd&expand=2602)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ pub unsafe fn _mm512_maskz_fmaddsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let fmaddsub = _mm512_fmaddsub_pd(a, b, c).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fmaddsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmaddsub_ps&expand=2613)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ pub unsafe fn _mm512_mask3_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+     let fmaddsub = _mm512_fmaddsub_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmaddsub, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsubadd_ps&expand=2691)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ pub unsafe fn _mm512_fmsubadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     transmute(vfmaddsub213ps(
+         a.as_f32x16(),
+         b.as_f32x16(),
+         sub,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsubadd_ps&expand=2692)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ pub unsafe fn _mm512_mask_fmsubadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+     let fmsubadd = _mm512_fmsubadd_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmsubadd, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsubadd_ps&expand=2694)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ pub unsafe fn _mm512_maskz_fmsubadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+     let fmsubadd = _mm512_fmsubadd_ps(a, b, c).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fmsubadd, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsubadd_ps&expand=2693)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ pub unsafe fn _mm512_mask3_fmsubadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+     let fmsubadd = _mm512_fmsubadd_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fmsubadd, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsubadd_pd&expand=2679)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ pub unsafe fn _mm512_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     transmute(vfmaddsub213pd(
+         a.as_f64x8(),
+         b.as_f64x8(),
+         sub,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsubadd_pd&expand=2680)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ pub unsafe fn _mm512_mask_fmsubadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+     let fmsubadd = _mm512_fmsubadd_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmsubadd, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsubadd_pd&expand=2682)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ pub unsafe fn _mm512_maskz_fmsubadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let fmsubadd = _mm512_fmsubadd_pd(a, b, c).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fmsubadd, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsubadd_pd&expand=2681)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ pub unsafe fn _mm512_mask3_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+     let fmsubadd = _mm512_fmsubadd_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fmsubadd, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmadd_ps&expand=2723)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ pub unsafe fn _mm512_fnmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f32x16());
+     transmute(vfmadd132ps(
+         sub,
+         b.as_f32x16(),
+         c.as_f32x16(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmadd_ps&expand=2724)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ pub unsafe fn _mm512_mask_fnmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+     let fnmadd = _mm512_fnmadd_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fnmadd, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmadd_ps&expand=2726)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ pub unsafe fn _mm512_maskz_fnmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+     let fnmadd = _mm512_fnmadd_ps(a, b, c).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fnmadd, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmadd_ps&expand=2725)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ pub unsafe fn _mm512_mask3_fnmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+     let fnmadd = _mm512_fnmadd_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fnmadd, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmadd_pd&expand=2711)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ pub unsafe fn _mm512_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f64x8());
+     transmute(vfmadd132pd(
+         sub,
+         b.as_f64x8(),
+         c.as_f64x8(),
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmadd_pd&expand=2712)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ pub unsafe fn _mm512_mask_fnmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+     let fnmadd = _mm512_fnmadd_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fnmadd, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmadd_pd&expand=2714)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ pub unsafe fn _mm512_maskz_fnmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let fnmadd = _mm512_fnmadd_pd(a, b, c).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fnmadd, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmadd_pd&expand=2713)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ pub unsafe fn _mm512_mask3_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+     let fnmadd = _mm512_fnmadd_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fnmadd, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmsub_ps&expand=2771)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ pub unsafe fn _mm512_fnmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f32x16());
+     let subc = simd_sub(zero, c.as_f32x16());
+     transmute(vfmadd132ps(
+         suba,
+         b.as_f32x16(),
+         subc,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmsub_ps&expand=2772)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ pub unsafe fn _mm512_mask_fnmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 {
+     let fnmsub = _mm512_fnmsub_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fnmsub, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmsub_ps&expand=2774)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ pub unsafe fn _mm512_maskz_fnmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 {
+     let fnmsub = _mm512_fnmsub_ps(a, b, c).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fnmsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmsub_ps&expand=2773)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ pub unsafe fn _mm512_mask3_fnmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 {
+     let fnmsub = _mm512_fnmsub_ps(a, b, c).as_f32x16();
+     transmute(simd_select_bitmask(k, fnmsub, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmsub_pd&expand=2759)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ pub unsafe fn _mm512_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f64x8());
+     let subc = simd_sub(zero, c.as_f64x8());
+     transmute(vfmadd132pd(
+         suba,
+         b.as_f64x8(),
+         subc,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmsub_pd&expand=2760)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ pub unsafe fn _mm512_mask_fnmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d {
+     let fnmsub = _mm512_fnmsub_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fnmsub, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmsub_pd&expand=2762)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ pub unsafe fn _mm512_maskz_fnmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d {
+     let fnmsub = _mm512_fnmsub_pd(a, b, c).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fnmsub, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmsub_pd&expand=2761)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ pub unsafe fn _mm512_mask3_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d {
+     let fnmsub = _mm512_fnmsub_pd(a, b, c).as_f64x8();
+     transmute(simd_select_bitmask(k, fnmsub, c.as_f64x8()))
+ }
+ 
+ /// Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rcp14_ps&expand=4502)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrcp14ps))]
+ pub unsafe fn _mm512_rcp14_ps(a: __m512) -> __m512 {
+     transmute(vrcp14ps(
+         a.as_f32x16(),
+         _mm512_setzero_ps().as_f32x16(),
+         0b11111111_11111111,
+     ))
+ }
+ 
+ /// Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rcp14_ps&expand=4500)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrcp14ps))]
+ pub unsafe fn _mm512_mask_rcp14_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+     transmute(vrcp14ps(a.as_f32x16(), src.as_f32x16(), k))
+ }
+ 
+ /// Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rcp14_ps&expand=4501)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrcp14ps))]
+ pub unsafe fn _mm512_maskz_rcp14_ps(k: __mmask16, a: __m512) -> __m512 {
+     transmute(vrcp14ps(a.as_f32x16(), _mm512_setzero_ps().as_f32x16(), k))
+ }
+ 
+ /// Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rcp14_pd&expand=4493)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrcp14pd))]
+ pub unsafe fn _mm512_rcp14_pd(a: __m512d) -> __m512d {
+     transmute(vrcp14pd(
+         a.as_f64x8(),
+         _mm512_setzero_pd().as_f64x8(),
+         0b11111111,
+     ))
+ }
+ 
+ /// Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rcp14_pd&expand=4491)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrcp14pd))]
+ pub unsafe fn _mm512_mask_rcp14_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+     transmute(vrcp14pd(a.as_f64x8(), src.as_f64x8(), k))
+ }
+ 
+ /// Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rcp14_pd&expand=4492)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrcp14pd))]
+ pub unsafe fn _mm512_maskz_rcp14_pd(k: __mmask8, a: __m512d) -> __m512d {
+     transmute(vrcp14pd(a.as_f64x8(), _mm512_setzero_pd().as_f64x8(), k))
+ }
+ 
+ /// Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rsqrt14_ps&expand=4819)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrsqrt14ps))]
+ pub unsafe fn _mm512_rsqrt14_ps(a: __m512) -> __m512 {
+     transmute(vrsqrt14ps(
+         a.as_f32x16(),
+         _mm512_setzero_ps().as_f32x16(),
+         0b11111111_11111111,
+     ))
+ }
+ 
+ /// Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rsqrt14_ps&expand=4817)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrsqrt14ps))]
+ pub unsafe fn _mm512_mask_rsqrt14_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+     transmute(vrsqrt14ps(a.as_f32x16(), src.as_f32x16(), k))
+ }
+ 
+ /// Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rsqrt14_ps&expand=4818)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrsqrt14ps))]
+ pub unsafe fn _mm512_maskz_rsqrt14_ps(k: __mmask16, a: __m512) -> __m512 {
+     transmute(vrsqrt14ps(
+         a.as_f32x16(),
+         _mm512_setzero_ps().as_f32x16(),
+         k,
+     ))
+ }
+ 
+ /// Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rsqrt14_pd&expand=4812)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrsqrt14pd))]
+ pub unsafe fn _mm512_rsqrt14_pd(a: __m512d) -> __m512d {
+     transmute(vrsqrt14pd(
+         a.as_f64x8(),
+         _mm512_setzero_pd().as_f64x8(),
+         0b11111111,
+     ))
+ }
+ 
+ /// Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rsqrt14_pd&expand=4810)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrsqrt14pd))]
+ pub unsafe fn _mm512_mask_rsqrt14_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+     transmute(vrsqrt14pd(a.as_f64x8(), src.as_f64x8(), k))
+ }
+ 
+ /// Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rsqrt14_pd&expand=4811)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vrsqrt14pd))]
+ pub unsafe fn _mm512_maskz_rsqrt14_pd(k: __mmask8, a: __m512d) -> __m512d {
+     transmute(vrsqrt14pd(a.as_f64x8(), _mm512_setzero_pd().as_f64x8(), k))
+ }
+ 
+ /// Convert the exponent of each packed single-precision (32-bit) floating-point element in a to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in dst. This intrinsic essentially calculates floor(log2(x)) for each element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getexp_ps&expand=2844)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexpps))]
+ pub unsafe fn _mm512_getexp_ps(a: __m512) -> __m512 {
+     transmute(vgetexpps(
+         a.as_f32x16(),
+         _mm512_setzero_ps().as_f32x16(),
+         0b11111111_11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert the exponent of each packed single-precision (32-bit) floating-point element in a to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getexp_ps&expand=2845)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexpps))]
+ pub unsafe fn _mm512_mask_getexp_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+     transmute(vgetexpps(
+         a.as_f32x16(),
+         src.as_f32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert the exponent of each packed single-precision (32-bit) floating-point element in a to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getexp_ps&expand=2846)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexpps))]
+ pub unsafe fn _mm512_maskz_getexp_ps(k: __mmask16, a: __m512) -> __m512 {
+     transmute(vgetexpps(
+         a.as_f32x16(),
+         _mm512_setzero_ps().as_f32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert the exponent of each packed double-precision (64-bit) floating-point element in a to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in dst. This intrinsic essentially calculates floor(log2(x)) for each element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getexp_pd&expand=2835)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexppd))]
+ pub unsafe fn _mm512_getexp_pd(a: __m512d) -> __m512d {
+     transmute(vgetexppd(
+         a.as_f64x8(),
+         _mm512_setzero_pd().as_f64x8(),
+         0b11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert the exponent of each packed double-precision (64-bit) floating-point element in a to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getexp_pd&expand=2836)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexppd))]
+ pub unsafe fn _mm512_mask_getexp_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+     transmute(vgetexppd(
+         a.as_f64x8(),
+         src.as_f64x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert the exponent of each packed double-precision (64-bit) floating-point element in a to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getexp_pd&expand=2837)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexppd))]
+ pub unsafe fn _mm512_maskz_getexp_pd(k: __mmask8, a: __m512d) -> __m512d {
+     transmute(vgetexppd(
+         a.as_f64x8(),
+         _mm512_setzero_pd().as_f64x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Normalize the mantissas of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getmant_ps&expand=2880)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))]
+ #[rustc_args_required_const(1, 2)]
+ pub unsafe fn _mm512_getmant_ps(
+     a: __m512,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr, $imm2:expr) => {
+             vgetmantps(
+                 a.as_f32x16(),
+                 $imm2 << 2 | $imm4,
+                 _mm512_setzero_ps().as_f32x16(),
+                 0b11111111_11111111,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas!(norm, sign, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getmant_ps&expand=2881)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))]
+ #[rustc_args_required_const(3, 4)]
+ pub unsafe fn _mm512_mask_getmant_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr, $imm2:expr) => {
+             vgetmantps(
+                 a.as_f32x16(),
+                 $imm2 << 2 | $imm4,
+                 src.as_f32x16(),
+                 k,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas!(norm, sign, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getmant_ps&expand=2882)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))]
+ #[rustc_args_required_const(2, 3)]
+ pub unsafe fn _mm512_maskz_getmant_ps(
+     k: __mmask16,
+     a: __m512,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr, $imm2:expr) => {
+             vgetmantps(
+                 a.as_f32x16(),
+                 $imm2 << 2 | $imm4,
+                 _mm512_setzero_ps().as_f32x16(),
+                 k,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas!(norm, sign, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getmant_pd&expand=2871)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))]
+ #[rustc_args_required_const(1, 2)]
+ pub unsafe fn _mm512_getmant_pd(
+     a: __m512d,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr, $imm2:expr) => {
+             vgetmantpd(
+                 a.as_f64x8(),
+                 $imm2 << 2 | $imm4,
+                 _mm512_setzero_pd().as_f64x8(),
+                 0b11111111,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas!(norm, sign, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getmant_pd&expand=2872)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))]
+ #[rustc_args_required_const(3, 4)]
+ pub unsafe fn _mm512_mask_getmant_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr, $imm2:expr) => {
+             vgetmantpd(
+                 a.as_f64x8(),
+                 $imm2 << 2 | $imm4,
+                 src.as_f64x8(),
+                 k,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas!(norm, sign, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getmant_pd&expand=2873)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))]
+ #[rustc_args_required_const(2, 3)]
+ pub unsafe fn _mm512_maskz_getmant_pd(
+     k: __mmask8,
+     a: __m512d,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr, $imm2:expr) => {
+             vgetmantpd(
+                 a.as_f64x8(),
+                 $imm2 << 2 | $imm4,
+                 _mm512_setzero_pd().as_f64x8(),
+                 k,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas!(norm, sign, call);
+     transmute(r)
+ }
+ 
+ /// Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_add_round_ps&expand=145)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddps, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_add_round_ps(a: __m512, b: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vaddps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_add_round_ps&expand=146)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddps, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_add_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vaddps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let addround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, addround, src.as_f32x16()))
+ }
+ 
+ /// Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_add_round_ps&expand=147)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddps, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_add_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vaddps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let addround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, addround, zero))
+ }
+ 
+ /// Add packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_add_round_pd&expand=142)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddpd, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_add_round_pd(a: __m512d, b: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vaddpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Add packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_add_round_pd&expand=143)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddpd, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_add_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vaddpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let addround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, addround, src.as_f64x8()))
+ }
+ 
+ /// Add packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_add_round_pd&expand=144)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vaddpd, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_add_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vaddpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let addround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, addround, zero))
+ }
+ 
+ /// Subtract packed single-precision (32-bit) floating-point elements in b from packed single-precision (32-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sub_round_ps&expand=5739)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubps, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_sub_round_ps(a: __m512, b: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsubps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Subtract packed single-precision (32-bit) floating-point elements in b from packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sub_round_ps&expand=5737)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubps, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_sub_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsubps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let subround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, subround, src.as_f32x16()))
+ }
+ 
+ /// Subtract packed single-precision (32-bit) floating-point elements in b from packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sub_round_ps&expand=5738)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubps, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_sub_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsubps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let subround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, subround, zero))
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sub_round_pd&expand=5736)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubpd, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_sub_round_pd(a: __m512d, b: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsubpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sub_round_pd&expand=5734)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubpd, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_sub_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsubpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let subround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, subround, src.as_f64x8()))
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sub_round_pd&expand=5735)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsubpd, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_sub_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsubpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let subround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, subround, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mul_round_ps&expand=3940)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulps, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_mul_round_ps(a: __m512, b: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmulps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mul_round_ps&expand=3938)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulps, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_mul_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmulps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let mulround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, mulround, src.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mul_round_ps&expand=3939)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulps, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_mul_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmulps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let mulround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, mulround, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mul_round_pd&expand=3937)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulpd, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_mul_round_pd(a: __m512d, b: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmulpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_mul_round_pd&expand=3935)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulpd, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_mul_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmulpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let mulround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, mulround, src.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_mul_round_ps&expand=3939)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmulpd, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_mul_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmulpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let mulround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, mulround, zero))
+ }
+ 
+ /// Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_div_round_ps&expand=2168)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivps, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_div_round_ps(a: __m512, b: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vdivps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_div_round_ps&expand=2169)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivps, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_div_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vdivps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let divround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, divround, src.as_f32x16()))
+ }
+ 
+ /// Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_div_round_ps&expand=2170)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivps, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_div_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vdivps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let divround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, divround, zero))
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, =and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_div_round_pd&expand=2165)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivpd, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_div_round_pd(a: __m512d, b: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vdivpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_div_round_pd&expand=2166)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivpd, rounding = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_div_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vdivpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let divround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, divround, src.as_f64x8()))
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_div_round_pd&expand=2167)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vdivpd, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_div_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vdivpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let divround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, divround, zero))
+ }
+ 
+ /// Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sqrt_round_ps&expand=5377)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtps, rounding = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_sqrt_round_ps(a: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsqrtps(a.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sqrt_round_ps&expand=5375)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtps, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_sqrt_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsqrtps(a.as_f32x16(), $imm4)
+         };
+     }
+     let sqrtround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, sqrtround, src.as_f32x16()))
+ }
+ 
+ /// Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sqrt_round_ps&expand=5376)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtps, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_sqrt_round_ps(k: __mmask16, a: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsqrtps(a.as_f32x16(), $imm4)
+         };
+     }
+     let sqrtround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, sqrtround, zero))
+ }
+ 
+ /// Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sqrt_round_pd&expand=5374)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtpd, rounding = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_sqrt_round_pd(a: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsqrtpd(a.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sqrt_round_pd&expand=5372)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtpd, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_sqrt_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsqrtpd(a.as_f64x8(), $imm4)
+         };
+     }
+     let sqrtround = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, sqrtround, src.as_f64x8()))
+ }
+ 
+ /// Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sqrt_round_pd&expand=5373)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vsqrtpd, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_sqrt_round_pd(k: __mmask8, a: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vsqrtpd(a.as_f64x8(), $imm4)
+         };
+     }
+     let sqrtround = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, sqrtround, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmadd_round_ps&expand=2565)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmadd_round_ps(a: __m512, b: __m512, c: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmadd_round_ps&expand=2566)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmadd_round_ps(
+     a: __m512,
+     k: __mmask16,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmadd, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in a using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmadd_round_ps&expand=2568)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmadd_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fmadd = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fmadd, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmadd_round_ps&expand=2567)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmadd_round_ps(
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     k: __mmask16,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmadd, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmadd_round_pd&expand=2561)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmadd_round_pd(a: __m512d, b: __m512d, c: __m512d, rounding: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmadd_round_pd&expand=2562)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmadd_round_pd(
+     a: __m512d,
+     k: __mmask8,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmadd, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmadd_round_pd&expand=2564)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmadd_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fmadd = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fmadd, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmadd_round_pd&expand=2563)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmadd_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     k: __mmask8,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmadd, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsub_round_ps&expand=2651)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmsub_round_ps(a: __m512, b: __m512, c: __m512, rounding: i32) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsub_round_ps&expand=2652)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmsub_round_ps(
+     a: __m512,
+     k: __mmask16,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let fmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsub, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsub_round_ps&expand=2654)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmsub_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let fmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsub_round_ps&expand=2653)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmsub_round_ps(
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     k: __mmask16,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let fmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsub, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsub_round_pd&expand=2647)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmsub_round_pd(a: __m512d, b: __m512d, c: __m512d, rounding: i32) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsub_round_pd&expand=2648)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmsub_round_pd(
+     a: __m512d,
+     k: __mmask8,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let fmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsub, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsub_round_pd&expand=2650)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmsub_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let fmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsub, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsub_round_pd&expand=2649)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmsub_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     k: __mmask8,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let fmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsub, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmaddsub_round_ps&expand=2619)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmaddsub_round_ps(a: __m512, b: __m512, c: __m512, rounding: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmaddsub_round_ps&expand=2620)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmaddsub_round_ps(
+     a: __m512,
+     k: __mmask16,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fmaddsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmaddsub, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmaddsub_round_ps&expand=2622)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmaddsub_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fmaddsub = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, fmaddsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmaddsub_round_ps&expand=2621)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmaddsub_round_ps(
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     k: __mmask16,
+     rounding: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fmaddsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmaddsub, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmaddsub_round_pd&expand=2615)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmaddsub_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmaddsub_round_pd&expand=2616)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmaddsub_round_pd(
+     a: __m512d,
+     k: __mmask8,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fmaddsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmaddsub, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmaddsub_round_pd&expand=2618)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmaddsub_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fmaddsub = constify_imm4_round!(rounding, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, fmaddsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmaddsub_round_pd&expand=2617)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmaddsub_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     k: __mmask8,
+     rounding: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fmaddsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmaddsub, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsubadd_round_ps&expand=2699)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmsubadd_round_ps(a: __m512, b: __m512, c: __m512, rounding: i32) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsubadd_round_ps&expand=2700)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmsubadd_round_ps(
+     a: __m512,
+     k: __mmask16,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let fmsubadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsubadd, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsubadd_round_ps&expand=2702)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmsubadd_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let fmsubadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsubadd, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsubadd_round_ps&expand=2701)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmsubadd_round_ps(
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     k: __mmask16,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213ps(a.as_f32x16(), b.as_f32x16(), sub, $imm4)
+         };
+     }
+     let fmsubadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsubadd, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fmsubadd_round_pd&expand=2695)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fmsubadd_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fmsubadd_round_pd&expand=2696)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fmsubadd_round_pd(
+     a: __m512d,
+     k: __mmask8,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let fmsubadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsubadd, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively add and subtract packed elements in c to/from the intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fmsubadd_round_pd&expand=2698)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fmsubadd_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let fmsubadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsubadd, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, alternatively subtract and add packed elements in c from/to the intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fmsubadd_round_pd&expand=2697)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmaddsub, rounding = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fmsubadd_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     k: __mmask8,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmaddsub213pd(a.as_f64x8(), b.as_f64x8(), sub, $imm4)
+         };
+     }
+     let fmsubadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fmsubadd, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmadd_round_ps&expand=2731)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fnmadd_round_ps(a: __m512, b: __m512, c: __m512, rounding: i32) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(sub, b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmadd_round_ps&expand=2732)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fnmadd_round_ps(
+     a: __m512,
+     k: __mmask16,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(sub, b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fnmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmadd, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmadd_round_ps&expand=2734)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fnmadd_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(sub, b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fnmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmadd, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmadd_round_ps&expand=2733)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fnmadd_round_ps(
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     k: __mmask16,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(sub, b.as_f32x16(), c.as_f32x16(), $imm4)
+         };
+     }
+     let fnmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmadd, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmadd_pd&expand=2711)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fnmadd_round_pd(a: __m512d, b: __m512d, c: __m512d, rounding: i32) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(sub, b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmadd_round_pd&expand=2728)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fnmadd_round_pd(
+     a: __m512d,
+     k: __mmask8,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(sub, b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fnmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmadd, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmadd_round_pd&expand=2730)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fnmadd_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(sub, b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fnmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmadd, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, add the negated intermediate result to packed elements in c, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmadd_round_pd&expand=2729)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fnmadd_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     k: __mmask8,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let sub = simd_sub(zero, a.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(sub, b.as_f64x8(), c.as_f64x8(), $imm4)
+         };
+     }
+     let fnmadd = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmadd, c.as_f64x8()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmsub_round_ps&expand=2779)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fnmsub_round_ps(a: __m512, b: __m512, c: __m512, rounding: i32) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f32x16());
+     let subc = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(suba, b.as_f32x16(), subc, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmsub_round_ps&expand=2780)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fnmsub_round_ps(
+     a: __m512,
+     k: __mmask16,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f32x16());
+     let subc = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(suba, b.as_f32x16(), subc, $imm4)
+         };
+     }
+     let fnmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmsub, a.as_f32x16()))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmsub_round_ps&expand=2782)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fnmsub_round_ps(
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f32x16());
+     let subc = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(suba, b.as_f32x16(), subc, $imm4)
+         };
+     }
+     let fnmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmsub, zero))
+ }
+ 
+ /// Multiply packed single-precision (32-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmsub_round_ps&expand=2781)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fnmsub_round_ps(
+     a: __m512,
+     b: __m512,
+     c: __m512,
+     k: __mmask16,
+     rounding: i32,
+ ) -> __m512 {
+     let zero: f32x16 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f32x16());
+     let subc = simd_sub(zero, c.as_f32x16());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132ps(suba, b.as_f32x16(), subc, $imm4)
+         };
+     }
+     let fnmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmsub, c.as_f32x16()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_fnmsub_round_pd&expand=2775)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_fnmsub_round_pd(a: __m512d, b: __m512d, c: __m512d, rounding: i32) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f64x8());
+     let subc = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(suba, b.as_f64x8(), subc, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_fnmsub_round_pd&expand=2776)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_fnmsub_round_pd(
+     a: __m512d,
+     k: __mmask8,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f64x8());
+     let subc = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(suba, b.as_f64x8(), subc, $imm4)
+         };
+     }
+     let fnmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmsub, a.as_f64x8()))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_fnmsub_round_pd&expand=2778)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_maskz_fnmsub_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f64x8());
+     let subc = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(suba, b.as_f64x8(), subc, $imm4)
+         };
+     }
+     let fnmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmsub, zero))
+ }
+ 
+ /// Multiply packed double-precision (64-bit) floating-point elements in a and b, subtract packed elements in c from the negated intermediate result, and store the results in dst using writemask k (elements are copied from c when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask3_fnmsub_round_pd&expand=2777)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vfmadd, rounding = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask3_fnmsub_round_pd(
+     a: __m512d,
+     b: __m512d,
+     c: __m512d,
+     k: __mmask8,
+     rounding: i32,
+ ) -> __m512d {
+     let zero: f64x8 = mem::zeroed();
+     let suba = simd_sub(zero, a.as_f64x8());
+     let subc = simd_sub(zero, c.as_f64x8());
+     macro_rules! call {
+         ($imm4:expr) => {
+             vfmadd132pd(suba, b.as_f64x8(), subc, $imm4)
+         };
+     }
+     let fnmsub = constify_imm4_round!(rounding, call);
+     transmute(simd_select_bitmask(k, fnmsub, c.as_f64x8()))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=max_round_ps&expand=3662)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxps, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_max_round_ps(a: __m512, b: __m512, sae: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmaxps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_round_ps&expand=3660)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxps, sae = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_max_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     sae: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmaxps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     transmute(simd_select_bitmask(k, max, src.as_f32x16()))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_round_ps&expand=3661)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxps, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_max_round_ps(k: __mmask16, a: __m512, b: __m512, sae: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmaxps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_max_round_pd&expand=3659)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxpd, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_max_round_pd(a: __m512d, b: __m512d, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmaxpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_max_round_pd&expand=3657)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxpd, sae = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_max_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmaxpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     transmute(simd_select_bitmask(k, max, src.as_f64x8()))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_max_round_pd&expand=3658)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmaxpd, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_max_round_pd(k: __mmask8, a: __m512d, b: __m512d, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vmaxpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_round_ps&expand=3776)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminps, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_min_round_ps(a: __m512, b: __m512, sae: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vminps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_round_ps&expand=3774)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminps, sae = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_min_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     sae: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vminps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     transmute(simd_select_bitmask(k, max, src.as_f32x16()))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_round_ps&expand=3775)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminps, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_min_round_ps(k: __mmask16, a: __m512, b: __m512, sae: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vminps(a.as_f32x16(), b.as_f32x16(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_min_round_pd&expand=3773)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminpd, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_min_round_pd(a: __m512d, b: __m512d, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vminpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_min_round_pd&expand=3771)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminpd, sae = 8))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_min_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vminpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     transmute(simd_select_bitmask(k, max, src.as_f64x8()))
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_min_round_pd&expand=3772)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vminpd, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_min_round_pd(k: __mmask8, a: __m512d, b: __m512d, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vminpd(a.as_f64x8(), b.as_f64x8(), $imm4)
+         };
+     }
+     let max = constify_imm4_sae!(sae, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, max, zero))
+ }
+ 
+ /// Convert the exponent of each packed single-precision (32-bit) floating-point element in a to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in dst. This intrinsic essentially calculates floor(log2(x)) for each element.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getexp_round_ps&expand=2850)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexpps, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_getexp_round_ps(a: __m512, sae: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vgetexpps(
+                 a.as_f32x16(),
+                 _mm512_setzero_ps().as_f32x16(),
+                 0b11111111_11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert the exponent of each packed single-precision (32-bit) floating-point element in a to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getexp_round_ps&expand=2851)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexpps, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_getexp_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     sae: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vgetexpps(a.as_f32x16(), src.as_f32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert the exponent of each packed single-precision (32-bit) floating-point element in a to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getexp_round_ps&expand=2852)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexpps, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_getexp_round_ps(k: __mmask16, a: __m512, sae: i32) -> __m512 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vgetexpps(a.as_f32x16(), _mm512_setzero_ps().as_f32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert the exponent of each packed double-precision (64-bit) floating-point element in a to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in dst. This intrinsic essentially calculates floor(log2(x)) for each element.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getexp_round_pd&expand=2847)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexppd, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_getexp_round_pd(a: __m512d, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vgetexppd(
+                 a.as_f64x8(),
+                 _mm512_setzero_pd().as_f64x8(),
+                 0b11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert the exponent of each packed double-precision (64-bit) floating-point element in a to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getexp_round_pd&expand=2848)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexppd, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_getexp_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vgetexppd(a.as_f64x8(), src.as_f64x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert the exponent of each packed double-precision (64-bit) floating-point element in a to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates floor(log2(x)) for each element.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getexp_round_pd&expand=2849)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetexppd, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_getexp_round_pd(k: __mmask8, a: __m512d, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vgetexppd(a.as_f64x8(), _mm512_setzero_pd().as_f64x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getmant_round_ps&expand=2886)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0, sae = 4))]
+ #[rustc_args_required_const(1, 2, 3)]
+ pub unsafe fn _mm512_getmant_round_ps(
+     a: __m512,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+     sae: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => {
+             vgetmantps(
+                 a.as_f32x16(),
+                 $imm2 << 2 | $imm4_1,
+                 _mm512_setzero_ps().as_f32x16(),
+                 0b11111111_11111111,
+                 $imm4_2,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas_sae!(norm, sign, sae, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getmant_round_ps&expand=2887)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0, sae = 4))]
+ #[rustc_args_required_const(3, 4, 5)]
+ pub unsafe fn _mm512_mask_getmant_round_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+     sae: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => {
+             vgetmantps(
+                 a.as_f32x16(),
+                 $imm2 << 2 | $imm4_1,
+                 src.as_f32x16(),
+                 k,
+                 $imm4_2,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas_sae!(norm, sign, sae, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed single-precision (32-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getmant_round_ps&expand=2888)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0, sae = 4))]
+ #[rustc_args_required_const(2, 3, 4)]
+ pub unsafe fn _mm512_maskz_getmant_round_ps(
+     k: __mmask16,
+     a: __m512,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+     sae: i32,
+ ) -> __m512 {
+     macro_rules! call {
+         ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => {
+             vgetmantps(
+                 a.as_f32x16(),
+                 $imm2 << 2 | $imm4_1,
+                 _mm512_setzero_ps().as_f32x16(),
+                 k,
+                 $imm4_2,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas_sae!(norm, sign, sae, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_getmant_round_pd&expand=2883)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0, sae = 4))]
+ #[rustc_args_required_const(1, 2, 3)]
+ pub unsafe fn _mm512_getmant_round_pd(
+     a: __m512d,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => {
+             vgetmantpd(
+                 a.as_f64x8(),
+                 $imm2 << 2 | $imm4_1,
+                 _mm512_setzero_pd().as_f64x8(),
+                 0b11111111,
+                 $imm4_2,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas_sae!(norm, sign, sae, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_getmant_round_pd&expand=2884)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0, sae = 4))]
+ #[rustc_args_required_const(3, 4, 5)]
+ pub unsafe fn _mm512_mask_getmant_round_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => {
+             vgetmantpd(
+                 a.as_f64x8(),
+                 $imm2 << 2 | $imm4_1,
+                 src.as_f64x8(),
+                 k,
+                 $imm4_2,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas_sae!(norm, sign, sae, call);
+     transmute(r)
+ }
+ 
+ /// Normalize the mantissas of packed double-precision (64-bit) floating-point elements in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates ±(2^k)*|x.significand|, where k depends on the interval range defined by interv and the sign depends on sc and the source sign.
+ /// The mantissa is normalized to the interval specified by interv, which can take the following values:
+ ///    _MM_MANT_NORM_1_2     // interval [1, 2)
+ ///    _MM_MANT_NORM_p5_2    // interval [0.5, 2)
+ ///    _MM_MANT_NORM_p5_1    // interval [0.5, 1)
+ ///    _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)
+ /// The sign is determined by sc which can take the following values:
+ ///    _MM_MANT_SIGN_src     // sign = sign(src)
+ ///    _MM_MANT_SIGN_zero    // sign = 0
+ ///    _MM_MANT_SIGN_nan     // dst = NaN if sign(src) = 1
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_getmant_round_pd&expand=2885)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0, sae = 4))]
+ #[rustc_args_required_const(2, 3, 4)]
+ pub unsafe fn _mm512_maskz_getmant_round_pd(
+     k: __mmask8,
+     a: __m512d,
+     norm: _MM_MANTISSA_NORM_ENUM,
+     sign: _MM_MANTISSA_SIGN_ENUM,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => {
+             vgetmantpd(
+                 a.as_f64x8(),
+                 $imm2 << 2 | $imm4_1,
+                 _mm512_setzero_pd().as_f64x8(),
+                 k,
+                 $imm4_2,
+             )
+         };
+     }
+     let r = constify_imm4_mantissas_sae!(norm, sign, sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=cvtps_epi32&expand=1737)   
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq))]
+ pub unsafe fn _mm512_cvtps_epi32(a: __m512) -> __m512i {
+     transmute(vcvtps2dq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_i32x16(),
+         0b11111111_11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtps_epi32&expand=1738)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq))]
+ pub unsafe fn _mm512_mask_cvtps_epi32(src: __m512i, k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvtps2dq(
+         a.as_f32x16(),
+         src.as_i32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvtps_epi32&expand=1739)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq))]
+ pub unsafe fn _mm512_maskz_cvtps_epi32(k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvtps2dq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_i32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers, and store the results in dst.
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvtps_epu32&expand=1755)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2udq))]
+ pub unsafe fn _mm512_cvtps_epu32(a: __m512) -> __m512i {
+     transmute(vcvtps2udq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_u32x16(),
+         0b11111111_11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtps_epu32&expand=1756)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2udq))]
+ pub unsafe fn _mm512_mask_cvtps_epu32(src: __m512i, k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvtps2udq(
+         a.as_f32x16(),
+         src.as_u32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=maskz_cvt_roundps_epu32&expand=1343)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2udq))]
+ pub unsafe fn _mm512_maskz_cvtps_epu32(k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvtps2udq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_u32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed double-precision (64-bit) floating-point elements, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvtps_pd&expand=1769)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd))]
+ pub unsafe fn _mm512_cvtps_pd(a: __m256) -> __m512d {
+     transmute(vcvtps2pd(
+         a.as_f32x8(),
+         _mm512_setzero_pd().as_f64x8(),
+         0b11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed double-precision (64-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtps_pd&expand=1770)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd))]
+ pub unsafe fn _mm512_mask_cvtps_pd(src: __m512d, k: __mmask8, a: __m256) -> __m512d {
+     transmute(vcvtps2pd(
+         a.as_f32x8(),
+         src.as_f64x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed double-precision (64-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvtps_pd&expand=1771)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd))]
+ pub unsafe fn _mm512_maskz_cvtps_pd(k: __mmask8, a: __m256) -> __m512d {
+     transmute(vcvtps2pd(
+         a.as_f32x8(),
+         _mm512_setzero_pd().as_f64x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvt_roundps_epi32&expand=1335)   
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq, rounding = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvt_roundps_epi32(a: __m512, rounding: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2dq(
+                 a.as_f32x16(),
+                 _mm512_setzero_si512().as_i32x16(),
+                 0b11111111_11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvt_roundps_epi32&expand=1336)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvt_roundps_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512,
+     rounding: i32,
+ ) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2dq(a.as_f32x16(), src.as_i32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvt_roundps_epi32&expand=1337)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2dq, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvt_roundps_epi32(k: __mmask16, a: __m512, rounding: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2dq(a.as_f32x16(), _mm512_setzero_si512().as_i32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers, and store the results in dst.
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvt_roundps_epu32&expand=1341)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2udq, rounding = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvt_roundps_epu32(a: __m512, rounding: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2udq(
+                 a.as_f32x16(),
+                 _mm512_setzero_si512().as_u32x16(),
+                 0b11111111_11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvt_roundps_epu32&expand=1342)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2udq, rounding = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvt_roundps_epu32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512,
+     rounding: i32,
+ ) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2udq(a.as_f32x16(), src.as_u32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:
+ ///    (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+ ///    (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+ ///    (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+ ///    (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+ ///    _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=maskz_cvt_roundps_epu32&expand=1343)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2udq, rounding = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvt_roundps_epu32(k: __mmask16, a: __m512, rounding: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2udq(a.as_f32x16(), _mm512_setzero_si512().as_u32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_round!(rounding, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed double-precision (64-bit) floating-point elements, and store the results in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=cvt_roundps_pd&expand=1347)   
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvt_roundps_pd(a: __m256, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2pd(
+                 a.as_f32x8(),
+                 _mm512_setzero_pd().as_f64x8(),
+                 0b11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed double-precision (64-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvt_roundps_epi32&expand=1336)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvt_roundps_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m256,
+     sae: i32,
+ ) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2pd(a.as_f32x8(), src.as_f64x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed double-precision (64-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvt_roundps_epi32&expand=1337)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvtps2pd, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvt_roundps_pd(k: __mmask8, a: __m256, sae: i32) -> __m512d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvtps2pd(a.as_f32x8(), _mm512_setzero_pd().as_f64x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvtt_roundps_epi32&expand=1916)   
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvtt_roundps_epi32(a: __m512, sae: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttps2dq(
+                 a.as_f32x16(),
+                 _mm512_setzero_si512().as_i32x16(),
+                 0b11111111_11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtt_roundps_epi32&expand=1917)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvtt_roundps_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512,
+     sae: i32,
+ ) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttps2dq(a.as_f32x16(), src.as_i32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvtt_roundps_epi32&expand=1918)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvtt_roundps_epi32(k: __mmask16, a: __m512, sae: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttps2dq(a.as_f32x16(), _mm512_setzero_si512().as_i32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvtt_roundps_epu32&expand=1922)   
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2udq, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvtt_roundps_epu32(a: __m512, sae: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttps2udq(
+                 a.as_f32x16(),
+                 _mm512_setzero_si512().as_i32x16(),
+                 0b11111111_11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtt_roundps_epu32&expand=1923)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2udq, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvtt_roundps_epu32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512,
+     sae: i32,
+ ) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttps2udq(a.as_f32x16(), src.as_i32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvtt_roundps_epu32&expand=1924)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2udq, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvtt_roundps_epu32(k: __mmask16, a: __m512, sae: i32) -> __m512i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttps2udq(a.as_f32x16(), _mm512_setzero_si512().as_i32x16(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvtt_roundpd_epi32&expand=1904)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvtt_roundpd_epi32(a: __m512d, sae: i32) -> __m256i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttpd2dq(
+                 a.as_f64x8(),
+                 _mm256_setzero_si256().as_i32x8(),
+                 0b11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtt_roundpd_epi32&expand=1905)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvtt_roundpd_epi32(
+     src: __m256i,
+     k: __mmask8,
+     a: __m512d,
+     sae: i32,
+ ) -> __m256i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttpd2dq(a.as_f64x8(), src.as_i32x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvtt_roundps_epi32&expand=1918)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvtt_roundpd_epi32(k: __mmask8, a: __m512d, sae: i32) -> __m256i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttpd2dq(a.as_f64x8(), _mm256_setzero_si256().as_i32x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst.
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///    
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvtt_roundpd_epu32&expand=1910)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2udq, sae = 8))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_cvtt_roundpd_epu32(a: __m512d, sae: i32) -> __m256i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttpd2udq(
+                 a.as_f64x8(),
+                 _mm256_setzero_si256().as_i32x8(),
+                 0b11111111,
+                 $imm4,
+             )
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvtt_roundpd_epu32&expand=1911)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2udq, sae = 8))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_cvtt_roundpd_epu32(
+     src: __m256i,
+     k: __mmask8,
+     a: __m512d,
+     sae: i32,
+ ) -> __m256i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttpd2udq(a.as_f64x8(), src.as_i32x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst.    
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvttps_epi32&expand=1984)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq))]
+ pub unsafe fn _mm512_cvttps_epi32(a: __m512) -> __m512i {
+     transmute(vcvttps2dq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_i32x16(),
+         0b11111111_11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvttps_epi32&expand=1985)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq))]
+ pub unsafe fn _mm512_mask_cvttps_epi32(src: __m512i, k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvttps2dq(
+         a.as_f32x16(),
+         src.as_i32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvttps_epi32&expand=1986)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2dq))]
+ pub unsafe fn _mm512_maskz_cvttps_epi32(k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvttps2dq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_i32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst.    
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvttps_epu32&expand=2002)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2udq))]
+ pub unsafe fn _mm512_cvttps_epu32(a: __m512) -> __m512i {
+     transmute(vcvttps2udq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_i32x16(),
+         0b11111111_11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvttps_epu32&expand=2003)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2udq))]
+ pub unsafe fn _mm512_mask_cvttps_epu32(src: __m512i, k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvttps2udq(
+         a.as_f32x16(),
+         src.as_i32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvttps_epu32&expand=2004)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttps2udq))]
+ pub unsafe fn _mm512_maskz_cvttps_epu32(k: __mmask16, a: __m512) -> __m512i {
+     transmute(vcvttps2udq(
+         a.as_f32x16(),
+         _mm512_setzero_si512().as_i32x16(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvtt_roundpd_epu32&expand=1912)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2udq, sae = 8))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_cvtt_roundpd_epu32(k: __mmask8, a: __m512d, sae: i32) -> __m256i {
+     macro_rules! call {
+         ($imm4:expr) => {
+             vcvttpd2udq(a.as_f64x8(), _mm256_setzero_si256().as_i32x8(), k, $imm4)
+         };
+     }
+     let r = constify_imm4_sae!(sae, call);
+     transmute(r)
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst.  
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvttpd_epi32&expand=1947)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq))]
+ pub unsafe fn _mm512_cvttpd_epi32(a: __m512d) -> __m256i {
+     transmute(vcvttpd2dq(
+         a.as_f64x8(),
+         _mm256_setzero_si256().as_i32x8(),
+         0b11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvttpd_epi32&expand=1948)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq))]
+ pub unsafe fn _mm512_mask_cvttpd_epi32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i {
+     transmute(vcvttpd2dq(
+         a.as_f64x8(),
+         src.as_i32x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvttpd_epi32&expand=1949)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2dq))]
+ pub unsafe fn _mm512_maskz_cvttpd_epi32(k: __mmask8, a: __m512d) -> __m256i {
+     transmute(vcvttpd2dq(
+         a.as_f64x8(),
+         _mm256_setzero_si256().as_i32x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst.    
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_cvttpd_epu32&expand=1965)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2udq))]
+ pub unsafe fn _mm512_cvttpd_epu32(a: __m512d) -> __m256i {
+     transmute(vcvttpd2udq(
+         a.as_f64x8(),
+         _mm256_setzero_si256().as_i32x8(),
+         0b11111111,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_cvttpd_epu32&expand=1966)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2udq))]
+ pub unsafe fn _mm512_mask_cvttpd_epu32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i {
+     transmute(vcvttpd2udq(
+         a.as_f64x8(),
+         src.as_i32x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Convert packed double-precision (64-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_cvttpd_epu32&expand=1967)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcvttpd2udq))]
+ pub unsafe fn _mm512_maskz_cvttpd_epu32(k: __mmask8, a: __m512d) -> __m256i {
+     transmute(vcvttpd2udq(
+         a.as_f64x8(),
+         _mm256_setzero_si256().as_i32x8(),
+         k,
+         _MM_FROUND_CUR_DIRECTION,
+     ))
+ }
+ 
+ /// Returns vector of type `__m512d` with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512F&expand=33,34,4990&text=_mm512_setzero_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vxorps))]
+ pub unsafe fn _mm512_setzero_pd() -> __m512d {
+     // All-0 is a properly initialized __m512d
+     mem::zeroed()
+ }
+ 
+ /// Returns vector of type `__m512d` with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512F&expand=33,34,4990&text=_mm512_setzero_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vxorps))]
+ pub unsafe fn _mm512_setzero_ps() -> __m512 {
+     // All-0 is a properly initialized __m512
+     mem::zeroed()
+ }
+ 
+ /// Returns vector of type `__m512i` with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512F&expand=33,34,4990&text=_mm512_setzero_si512)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vxorps))]
+ pub unsafe fn _mm512_setzero_si512() -> __m512i {
+     // All-0 is a properly initialized __m512i
+     mem::zeroed()
+ }
+ 
+ /// Sets packed 32-bit integers in `dst` with the supplied values in reverse
+ /// order.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_setr_epi32(
+     e15: i32,
+     e14: i32,
+     e13: i32,
+     e12: i32,
+     e11: i32,
+     e10: i32,
+     e9: i32,
+     e8: i32,
+     e7: i32,
+     e6: i32,
+     e5: i32,
+     e4: i32,
+     e3: i32,
+     e2: i32,
+     e1: i32,
+     e0: i32,
+ ) -> __m512i {
+     let r = i32x16(
+         e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0,
+     );
+     transmute(r)
+ }
+ 
+ /// Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherdpd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i32gather_pd(offsets: __m256i, slice: *const u8, scale: i32) -> __m512d {
+     let zero = _mm512_setzero_pd().as_f64x8();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherdpd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherdpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32gather_pd(
+     src: __m512d,
+     mask: __mmask8,
+     offsets: __m256i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m512d {
+     let src = src.as_f64x8();
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherdpd(src, slice, offsets, mask as i8, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i64gather_pd(offsets: __m512i, slice: *const u8, scale: i32) -> __m512d {
+     let zero = _mm512_setzero_pd().as_f64x8();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherqpd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64gather_pd(
+     src: __m512d,
+     mask: __mmask8,
+     offsets: __m512i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m512d {
+     let src = src.as_f64x8();
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherqpd(src, slice, offsets, mask as i8, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherqps, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i64gather_ps(offsets: __m512i, slice: *const u8, scale: i32) -> __m256 {
+     let zero = _mm256_setzero_ps().as_f32x8();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherqps(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherqps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64gather_ps(
+     src: __m256,
+     mask: __mmask8,
+     offsets: __m512i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m256 {
+     let src = src.as_f32x8();
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherqps(src, slice, offsets, mask as i8, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherdps, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i32gather_ps(offsets: __m512i, slice: *const u8, scale: i32) -> __m512 {
+     let zero = _mm512_setzero_ps().as_f32x16();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherdps(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vgatherdps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32gather_ps(
+     src: __m512,
+     mask: __mmask16,
+     offsets: __m512i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m512 {
+     let src = src.as_f32x16();
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vgatherdps(src, slice, offsets, mask as i16, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 32-bit integers from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherdd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i32gather_epi32(offsets: __m512i, slice: *const u8, scale: i32) -> __m512i {
+     let zero = _mm512_setzero_si512().as_i32x16();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdd(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 32-bit integers from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherdd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32gather_epi32(
+     src: __m512i,
+     mask: __mmask16,
+     offsets: __m512i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m512i {
+     let src = src.as_i32x16();
+     let mask = mask as i16;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 64-bit integers from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherdq, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i32gather_epi64(offsets: __m256i, slice: *const u8, scale: i32) -> __m512i {
+     let zero = _mm512_setzero_si512().as_i64x8();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdq(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 64-bit integers from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherdq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32gather_epi64(
+     src: __m512i,
+     mask: __mmask8,
+     offsets: __m256i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m512i {
+     let src = src.as_i64x8();
+     let mask = mask as i8;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherdq(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 64-bit integers from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i64gather_epi64(offsets: __m512i, slice: *const u8, scale: i32) -> __m512i {
+     let zero = _mm512_setzero_si512().as_i64x8();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqq(zero, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 64-bit integers from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64gather_epi64(
+     src: __m512i,
+     mask: __mmask8,
+     offsets: __m512i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m512i {
+     let src = src.as_i64x8();
+     let mask = mask as i8;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqq(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 32-bit integers from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherqd, scale = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_i64gather_epi32(offsets: __m512i, slice: *const u8, scale: i32) -> __m256i {
+     let zeros = _mm256_setzero_si256().as_i32x8();
+     let neg_one = -1;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqd(zeros, slice, offsets, neg_one, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Gather 32-bit integers from memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64gather_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpgatherqd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64gather_epi32(
+     src: __m256i,
+     mask: __mmask8,
+     offsets: __m512i,
+     slice: *const u8,
+     scale: i32,
+ ) -> __m256i {
+     let src = src.as_i32x8();
+     let mask = mask as i8;
+     let slice = slice as *const i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpgatherqd(src, slice, offsets, mask, $imm8)
+         };
+     }
+     let r = constify_imm8_gather!(scale, call);
+     transmute(r)
+ }
+ 
+ /// Scatter double-precision (64-bit) floating-point elements from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterdpd, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i32scatter_pd(slice: *mut u8, offsets: __m256i, src: __m512d, scale: i32) {
+     let src = src.as_f64x8();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterdpd(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter double-precision (64-bit) floating-point elements from src into memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterdpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32scatter_pd(
+     slice: *mut u8,
+     mask: __mmask8,
+     offsets: __m256i,
+     src: __m512d,
+     scale: i32,
+ ) {
+     let src = src.as_f64x8();
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterdpd(slice, mask as i8, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter double-precision (64-bit) floating-point elements from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterqpd, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i64scatter_pd(slice: *mut u8, offsets: __m512i, src: __m512d, scale: i32) {
+     let src = src.as_f64x8();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterqpd(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter double-precision (64-bit) floating-point elements from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterqpd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64scatter_pd(
+     slice: *mut u8,
+     mask: __mmask8,
+     offsets: __m512i,
+     src: __m512d,
+     scale: i32,
+ ) {
+     let src = src.as_f64x8();
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterqpd(slice, mask as i8, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter single-precision (32-bit) floating-point elements from memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterdps, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i32scatter_ps(slice: *mut u8, offsets: __m512i, src: __m512, scale: i32) {
+     let src = src.as_f32x16();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterdps(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter single-precision (32-bit) floating-point elements from src into memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterdps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32scatter_ps(
+     slice: *mut u8,
+     mask: __mmask16,
+     offsets: __m512i,
+     src: __m512,
+     scale: i32,
+ ) {
+     let src = src.as_f32x16();
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterdps(slice, mask as i16, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter single-precision (32-bit) floating-point elements from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterqps, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i64scatter_ps(slice: *mut u8, offsets: __m512i, src: __m256, scale: i32) {
+     let src = src.as_f32x8();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterqps(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter single-precision (32-bit) floating-point elements from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vscatterqps, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64scatter_ps(
+     slice: *mut u8,
+     mask: __mmask8,
+     offsets: __m512i,
+     src: __m256,
+     scale: i32,
+ ) {
+     let src = src.as_f32x8();
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vscatterqps(slice, mask as i8, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 64-bit integers from src into memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32scatter_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterdq, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i32scatter_epi64(slice: *mut u8, offsets: __m256i, src: __m512i, scale: i32) {
+     let src = src.as_i64x8();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterdq(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 64-bit integers from src into memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterdq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32scatter_epi64(
+     slice: *mut u8,
+     mask: __mmask8,
+     offsets: __m256i,
+     src: __m512i,
+     scale: i32,
+ ) {
+     let src = src.as_i64x8();
+     let mask = mask as i8;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterdq(slice, mask, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 64-bit integers from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterqq, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i64scatter_epi64(slice: *mut u8, offsets: __m512i, src: __m512i, scale: i32) {
+     let src = src.as_i64x8();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterqq(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 64-bit integers from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterqq, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64scatter_epi64(
+     slice: *mut u8,
+     mask: __mmask8,
+     offsets: __m512i,
+     src: __m512i,
+     scale: i32,
+ ) {
+     let src = src.as_i64x8();
+     let mask = mask as i8;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterqq(slice, mask, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 32-bit integers from src into memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterdd, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i32scatter_epi32(slice: *mut u8, offsets: __m512i, src: __m512i, scale: i32) {
+     let src = src.as_i32x16();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterdd(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 32-bit integers from src into memory using 32-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i32scatter_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterdd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i32scatter_epi32(
+     slice: *mut u8,
+     mask: __mmask16,
+     offsets: __m512i,
+     src: __m512i,
+     scale: i32,
+ ) {
+     let src = src.as_i32x16();
+     let mask = mask as i16;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i32x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterdd(slice, mask, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 32-bit integers from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i64scatter_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterqd, scale = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_i64scatter_epi32(slice: *mut u8, offsets: __m512i, src: __m256i, scale: i32) {
+     let src = src.as_i32x8();
+     let neg_one = -1;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterqd(slice, neg_one, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Scatter 32-bit integers from src into memory using 64-bit indices.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_i64scatter_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpscatterqd, scale = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_i64scatter_epi32(
+     slice: *mut u8,
+     mask: __mmask8,
+     offsets: __m512i,
+     src: __m256i,
+     scale: i32,
+ ) {
+     let src = src.as_i32x8();
+     let mask = mask as i8;
+     let slice = slice as *mut i8;
+     let offsets = offsets.as_i64x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpscatterqd(slice, mask, offsets, src, $imm8)
+         };
+     }
+     constify_imm8_gather!(scale, call);
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the left by the number of bits specified in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rol_epi32&expand=4685)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprold, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_rol_epi32(a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprold(a.as_i32x16(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the left by the number of bits specified in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rol_epi32&expand=4683)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprold, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_rol_epi32(src: __m512i, k: __mmask16, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprold(a.as_i32x16(), $imm8)
+         };
+     }
+     let rol = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, rol, src.as_i32x16()))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the left by the number of bits specified in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rol_epi32&expand=4684)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprold, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_rol_epi32(k: __mmask16, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprold(a.as_i32x16(), $imm8)
+         };
+     }
+     let rol = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, rol, zero))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the right by the number of bits specified in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_ror_epi32&expand=4721)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprold, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_ror_epi32(a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprord(a.as_i32x16(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the right by the number of bits specified in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_ror_epi32&expand=4719)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprold, imm8 = 123))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_ror_epi32(src: __m512i, k: __mmask16, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprord(a.as_i32x16(), $imm8)
+         };
+     }
+     let ror = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, ror, src.as_i32x16()))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the right by the number of bits specified in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_ror_epi32&expand=4720)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprold, imm8 = 123))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_ror_epi32(k: __mmask16, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprord(a.as_i32x16(), $imm8)
+         };
+     }
+     let ror = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, ror, zero))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the left by the number of bits specified in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rol_epi64&expand=4694)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_rol_epi64(a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprolq(a.as_i64x8(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the left by the number of bits specified in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rol_epi64&expand=4692)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolq, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_rol_epi64(src: __m512i, k: __mmask8, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprolq(a.as_i64x8(), $imm8)
+         };
+     }
+     let rol = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, rol, src.as_i64x8()))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the left by the number of bits specified in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rol_epi64&expand=4693)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolq, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_rol_epi64(k: __mmask8, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprolq(a.as_i64x8(), $imm8)
+         };
+     }
+     let rol = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, rol, zero))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the right by the number of bits specified in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_ror_epi64&expand=4730)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolq, imm8 = 15))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_ror_epi64(a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprorq(a.as_i64x8(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the right by the number of bits specified in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_ror_epi64&expand=4728)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolq, imm8 = 15))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_ror_epi64(src: __m512i, k: __mmask8, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprorq(a.as_i64x8(), $imm8)
+         };
+     }
+     let ror = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, ror, src.as_i64x8()))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the right by the number of bits specified in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_ror_epi64&expand=4729)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolq, imm8 = 15))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_ror_epi64(k: __mmask8, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vprorq(a.as_i64x8(), $imm8)
+         };
+     }
+     let ror = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, ror, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by imm8 while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_slli_epi32&expand=5310)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpslld, imm8 = 5))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_slli_epi32(a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsllid(a.as_i32x16(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shift packed 32-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_slli_epi32&expand=5308)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpslld, imm8 = 5))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_slli_epi32(src: __m512i, k: __mmask16, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsllid(a.as_i32x16(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_slli_epi32&expand=5309)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpslld, imm8 = 5))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_slli_epi32(k: __mmask16, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsllid(a.as_i32x16(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by imm8 while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srli_epi32&expand=5522)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrld, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_srli_epi32(a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrlid(a.as_i32x16(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shift packed 32-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srli_epi32&expand=5520)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrld, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_srli_epi32(src: __m512i, k: __mmask16, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrlid(a.as_i32x16(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srli_epi32&expand=5521)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrld, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_srli_epi32(k: __mmask16, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrlid(a.as_i32x16(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by imm8 while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_slli_epi64&expand=5319)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllq, imm8 = 5))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_slli_epi64(a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpslliq(a.as_i64x8(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shift packed 64-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_slli_epi64&expand=5317)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllq, imm8 = 5))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_slli_epi64(src: __m512i, k: __mmask8, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpslliq(a.as_i64x8(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_slli_epi64&expand=5318)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllq, imm8 = 5))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_slli_epi64(k: __mmask8, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpslliq(a.as_i64x8(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by imm8 while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srli_epi64&expand=5531)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_srli_epi64(a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrliq(a.as_i64x8(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shift packed 64-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srli_epi64&expand=5529)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlq, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_srli_epi64(src: __m512i, k: __mmask8, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrliq(a.as_i64x8(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srli_epi64&expand=5530)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlq, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_srli_epi64(k: __mmask8, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsrliq(a.as_i64x8(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sll_epi32&expand=5280)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpslld))]
+ pub unsafe fn _mm512_sll_epi32(a: __m512i, count: __m128i) -> __m512i {
+     transmute(vpslld(a.as_i32x16(), count.as_i32x4()))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sll_epi32&expand=5278)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpslld))]
+ pub unsafe fn _mm512_mask_sll_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     count: __m128i,
+ ) -> __m512i {
+     let shf = _mm512_sll_epi32(a, count).as_i32x16();
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sll_epi32&expand=5279)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpslld))]
+ pub unsafe fn _mm512_maskz_sll_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m512i {
+     let shf = _mm512_sll_epi32(a, count).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srl_epi32&expand=5492)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrld))]
+ pub unsafe fn _mm512_srl_epi32(a: __m512i, count: __m128i) -> __m512i {
+     transmute(vpsrld(a.as_i32x16(), count.as_i32x4()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srl_epi32&expand=5490)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrld))]
+ pub unsafe fn _mm512_mask_srl_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     count: __m128i,
+ ) -> __m512i {
+     let shf = _mm512_srl_epi32(a, count).as_i32x16();
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srl_epi32&expand=5491)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrld))]
+ pub unsafe fn _mm512_maskz_srl_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m512i {
+     let shf = _mm512_srl_epi32(a, count).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sll_epi64&expand=5289)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllq))]
+ pub unsafe fn _mm512_sll_epi64(a: __m512i, count: __m128i) -> __m512i {
+     transmute(vpsllq(a.as_i64x8(), count.as_i64x2()))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sll_epi64&expand=5287)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllq))]
+ pub unsafe fn _mm512_mask_sll_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     count: __m128i,
+ ) -> __m512i {
+     let shf = _mm512_sll_epi64(a, count).as_i64x8();
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sll_epi64&expand=5288)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllq))]
+ pub unsafe fn _mm512_maskz_sll_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512i {
+     let shf = _mm512_sll_epi64(a, count).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srl_epi64&expand=5501)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlq))]
+ pub unsafe fn _mm512_srl_epi64(a: __m512i, count: __m128i) -> __m512i {
+     transmute(vpsrlq(a.as_i64x8(), count.as_i64x2()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srl_epi64&expand=5499)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlq))]
+ pub unsafe fn _mm512_mask_srl_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     count: __m128i,
+ ) -> __m512i {
+     let shf = _mm512_srl_epi64(a, count).as_i64x8();
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sll_epi64&expand=5288)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlq))]
+ pub unsafe fn _mm512_maskz_srl_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512i {
+     let shf = _mm512_srl_epi64(a, count).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by count while shifting in sign bits, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sra_epi32&expand=5407)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrad))]
+ pub unsafe fn _mm512_sra_epi32(a: __m512i, count: __m128i) -> __m512i {
+     transmute(vpsrad(a.as_i32x16(), count.as_i32x4()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sra_epi32&expand=5405)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrad))]
+ pub unsafe fn _mm512_mask_sra_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     count: __m128i,
+ ) -> __m512i {
+     let shf = _mm512_sra_epi32(a, count).as_i32x16();
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sra_epi32&expand=5406)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrad))]
+ pub unsafe fn _mm512_maskz_sra_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m512i {
+     let shf = _mm512_sra_epi32(a, count).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by count while shifting in sign bits, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sra_epi64&expand=5416)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsraq))]
+ pub unsafe fn _mm512_sra_epi64(a: __m512i, count: __m128i) -> __m512i {
+     transmute(vpsraq(a.as_i64x8(), count.as_i64x2()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sra_epi64&expand=5414)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsraq))]
+ pub unsafe fn _mm512_mask_sra_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     count: __m128i,
+ ) -> __m512i {
+     let shf = _mm512_sra_epi64(a, count).as_i64x8();
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sra_epi64&expand=5415)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsraq))]
+ pub unsafe fn _mm512_maskz_sra_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512i {
+     let shf = _mm512_sra_epi64(a, count).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srai_epi32&expand=5436)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrad, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_srai_epi32(a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsraid(a.as_i32x16(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shift packed 32-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srai_epi32&expand=5434)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrad, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_srai_epi32(src: __m512i, k: __mmask16, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsraid(a.as_i32x16(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srai_epi32&expand=5435)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrad, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_srai_epi32(k: __mmask16, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsraid(a.as_i32x16(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srai_epi64&expand=5445)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsraq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_srai_epi64(a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsraiq(a.as_i64x8(), $imm8)
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shift packed 64-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srai_epi64&expand=5443)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsraq, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_srai_epi64(src: __m512i, k: __mmask8, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsraiq(a.as_i64x8(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srai_epi64&expand=5444)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsraq, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_srai_epi64(k: __mmask8, a: __m512i, imm8: u32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpsraiq(a.as_i64x8(), $imm8)
+         };
+     }
+     let shf = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srav_epi32&expand=5465)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsravd))]
+ pub unsafe fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i {
+     transmute(vpsravd(a.as_i32x16(), count.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srav_epi32&expand=5463)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsravd))]
+ pub unsafe fn _mm512_mask_srav_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     count: __m512i,
+ ) -> __m512i {
+     let shf = _mm512_srav_epi32(a, count).as_i32x16();
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srav_epi32&expand=5464)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsravd))]
+ pub unsafe fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+     let shf = _mm512_srav_epi32(a, count).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srav_epi64&expand=5474)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsravq))]
+ pub unsafe fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i {
+     transmute(vpsravq(a.as_i64x8(), count.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srav_epi64&expand=5472)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsravq))]
+ pub unsafe fn _mm512_mask_srav_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     count: __m512i,
+ ) -> __m512i {
+     let shf = _mm512_srav_epi64(a, count).as_i64x8();
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srav_epi64&expand=5473)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsravq))]
+ pub unsafe fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+     let shf = _mm512_srav_epi64(a, count).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the left by the number of bits specified in the corresponding element of b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rolv_epi32&expand=4703)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolvd))]
+ pub unsafe fn _mm512_rolv_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vprolvd(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the left by the number of bits specified in the corresponding element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rolv_epi32&expand=4701)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolvd))]
+ pub unsafe fn _mm512_mask_rolv_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let rol = _mm512_rolv_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, rol, src.as_i32x16()))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the left by the number of bits specified in the corresponding element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rolv_epi32&expand=4702)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolvd))]
+ pub unsafe fn _mm512_maskz_rolv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let rol = _mm512_rolv_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, rol, zero))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the right by the number of bits specified in the corresponding element of b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rorv_epi32&expand=4739)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprorvd))]
+ pub unsafe fn _mm512_rorv_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vprorvd(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the right by the number of bits specified in the corresponding element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rorv_epi32&expand=4737)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprorvd))]
+ pub unsafe fn _mm512_mask_rorv_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let ror = _mm512_rorv_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, ror, src.as_i32x16()))
+ }
+ 
+ /// Rotate the bits in each packed 32-bit integer in a to the right by the number of bits specified in the corresponding element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rorv_epi32&expand=4738)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprorvd))]
+ pub unsafe fn _mm512_maskz_rorv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let ror = _mm512_rorv_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, ror, zero))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the left by the number of bits specified in the corresponding element of b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rolv_epi64&expand=4712)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolvq))]
+ pub unsafe fn _mm512_rolv_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vprolvq(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the left by the number of bits specified in the corresponding element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rolv_epi64&expand=4710)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolvq))]
+ pub unsafe fn _mm512_mask_rolv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let rol = _mm512_rolv_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, rol, src.as_i64x8()))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the left by the number of bits specified in the corresponding element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rolv_epi64&expand=4711)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprolvq))]
+ pub unsafe fn _mm512_maskz_rolv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let rol = _mm512_rolv_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, rol, zero))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the right by the number of bits specified in the corresponding element of b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_rorv_epi64&expand=4748)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprorvq))]
+ pub unsafe fn _mm512_rorv_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(vprorvq(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the right by the number of bits specified in the corresponding element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_rorv_epi64&expand=4746)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprorvq))]
+ pub unsafe fn _mm512_mask_rorv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let ror = _mm512_rorv_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, ror, src.as_i64x8()))
+ }
+ 
+ /// Rotate the bits in each packed 64-bit integer in a to the right by the number of bits specified in the corresponding element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_rorv_epi64&expand=4747)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vprorvq))]
+ pub unsafe fn _mm512_maskz_rorv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let ror = _mm512_rorv_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, ror, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sllv_epi32&expand=5342)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllvd))]
+ pub unsafe fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i {
+     transmute(vpsllvd(a.as_i32x16(), count.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sllv_epi32&expand=5340)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllvd))]
+ pub unsafe fn _mm512_mask_sllv_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     count: __m512i,
+ ) -> __m512i {
+     let shf = _mm512_sllv_epi32(a, count).as_i32x16();
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sllv_epi32&expand=5341)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllvd))]
+ pub unsafe fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+     let shf = _mm512_sllv_epi32(a, count).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srlv_epi32&expand=5554)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlvd))]
+ pub unsafe fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i {
+     transmute(vpsrlvd(a.as_i32x16(), count.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_srlv_epi32&expand=5552)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlvd))]
+ pub unsafe fn _mm512_mask_srlv_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     count: __m512i,
+ ) -> __m512i {
+     let shf = _mm512_srlv_epi32(a, count).as_i32x16();
+     transmute(simd_select_bitmask(k, shf, src.as_i32x16()))
+ }
+ 
+ /// Shift packed 32-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srlv_epi32&expand=5553)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlvd))]
+ pub unsafe fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i {
+     let shf = _mm512_srlv_epi32(a, count).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_sllv_epi64&expand=5351)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllvq))]
+ pub unsafe fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i {
+     transmute(vpsllvq(a.as_i64x8(), count.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_sllv_epi64&expand=5349)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllvq))]
+ pub unsafe fn _mm512_mask_sllv_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     count: __m512i,
+ ) -> __m512i {
+     let shf = _mm512_sllv_epi64(a, count).as_i64x8();
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_sllv_epi64&expand=5350)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsllvq))]
+ pub unsafe fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+     let shf = _mm512_sllv_epi64(a, count).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_srlv_epi64&expand=5563)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlvq))]
+ pub unsafe fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i {
+     transmute(vpsrlvq(a.as_i64x8(), count.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mask_srlv_epi64&expand=5561)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlvq))]
+ pub unsafe fn _mm512_mask_srlv_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     count: __m512i,
+ ) -> __m512i {
+     let shf = _mm512_srlv_epi64(a, count).as_i64x8();
+     transmute(simd_select_bitmask(k, shf, src.as_i64x8()))
+ }
+ 
+ /// Shift packed 64-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_srlv_epi64&expand=5562)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpsrlvq))]
+ pub unsafe fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i {
+     let shf = _mm512_srlv_epi64(a, count).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shf, zero))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permute_ps&expand=4170)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_permute_ps(a: __m512, imm8: i32) -> __m512 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermilps(a.as_f32x16(), _mm512_set1_epi32($imm8).as_i32x16())
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permute_ps&expand=4168)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_permute_ps(src: __m512, k: __mmask16, a: __m512, imm8: i32) -> __m512 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermilps(a.as_f32x16(), _mm512_set1_epi32($imm8).as_i32x16())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, permute, src.as_f32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permute_ps&expand=4169)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_permute_ps(k: __mmask16, a: __m512, imm8: i32) -> __m512 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermilps(a.as_f32x16(), _mm512_set1_epi32($imm8).as_i32x16())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permute_pd&expand=4161)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_permute_pd(a: __m512d, imm8: i32) -> __m512d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermilpd(a.as_f64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permute_pd&expand=4159)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_permute_pd(src: __m512d, k: __mmask8, a: __m512d, imm8: i32) -> __m512d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermilpd(a.as_f64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, permute, src.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permute_pd&expand=4160)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_permute_pd(k: __mmask8, a: __m512d, imm8: i32) -> __m512d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermilpd(a.as_f64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 64-bit integers in a within 256-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutex_epi64&expand=4208)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcast, imm8 = 0b11111111))]
+ //shoud be vpermq, but generate vpermpd. It generates vpermq with mask. change to vbroadcast becaise CI Windows
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_permutex_epi64(a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermq(a.as_i64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shuffle 64-bit integers in a within 256-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutex_epi64&expand=4206)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpbroadcast, imm8 = 0b11111111))] //shoud be vpermq. change to vpbroadcast becaise CI Windows
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_permutex_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     imm8: i32,
+ ) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermq(a.as_i64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, permute, src.as_i64x8()))
+ }
+ 
+ /// Shuffle 64-bit integers in a within 256-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutex_epi64&expand=4207)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpbroadcast, imm8 = 0b11111111))] //shoud be vpermq. change to vpbroadcast becaise CI Windows
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_permutex_epi64(k: __mmask8, a: __m512i, imm8: i32) -> __m512i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermq(a.as_i64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 256-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutex_pd&expand=4214)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcast, imm8 = 0b11111111))] //shoud be vpermpd. change to vbroadcast becaise CI Windows
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_permutex_pd(a: __m512d, imm8: i32) -> __m512d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermpd(a.as_f64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let r = constify_imm8_sae!(imm8, call);
+     transmute(r)
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 256-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutex_pd&expand=4212)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcast, imm8 = 0b11111111))] //shoud be vpermpd. change to vbroadcast becaise CI Windows
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_permutex_pd(src: __m512d, k: __mmask8, a: __m512d, imm8: i32) -> __m512d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermpd(a.as_f64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     transmute(simd_select_bitmask(k, permute, src.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 256-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutex_pd&expand=4213)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcast, imm8 = 0b11111111))] //shoud be vpermpd. change to vbroadcast becaise CI Windows
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_permutex_pd(k: __mmask8, a: __m512d, imm8: i32) -> __m512d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             vpermpd(a.as_f64x8(), _mm512_set1_epi64($imm8).as_i64x8())
+         };
+     }
+     let permute = constify_imm8_sae!(imm8, call);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 32-bit integers in a across lanes using the corresponding index in idx, and store the results in dst. Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the permutevar name. This intrinsic is identical to _mm512_permutexvar_epi32, and it is recommended that you use that intrinsic name.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutevar_epi32&expand=4182)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //should be vpermd, but generate vpermps. It generates vpermd with mask
+ pub unsafe fn _mm512_permutevar_epi32(idx: __m512i, a: __m512i) -> __m512i {
+     transmute(vpermd(a.as_i32x16(), idx.as_i32x16()))
+ }
+ 
+ /// Shuffle 32-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the permutevar name. This intrinsic is identical to _mm512_mask_permutexvar_epi32, and it is recommended that you use that intrinsic name.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutevar_epi32&expand=4181)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermd))]
+ pub unsafe fn _mm512_mask_permutevar_epi32(
+     src: __m512i,
+     k: __mmask16,
+     idx: __m512i,
+     a: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutevar_epi32(idx, a).as_i32x16();
+     transmute(simd_select_bitmask(k, permute, src.as_i32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutevar_ps&expand=4200)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps))]
+ pub unsafe fn _mm512_permutevar_ps(a: __m512, b: __m512i) -> __m512 {
+     transmute(vpermilps(a.as_f32x16(), b.as_i32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutevar_ps&expand=4198)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps))]
+ pub unsafe fn _mm512_mask_permutevar_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512i,
+ ) -> __m512 {
+     let permute = _mm512_permutevar_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, permute, src.as_f32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutevar_ps&expand=4199)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps))]
+ pub unsafe fn _mm512_maskz_permutevar_ps(k: __mmask16, a: __m512, b: __m512i) -> __m512 {
+     let permute = _mm512_permutevar_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutevar_pd&expand=4191)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilpd))]
+ pub unsafe fn _mm512_permutevar_pd(a: __m512d, b: __m512i) -> __m512d {
+     transmute(vpermilpd(a.as_f64x8(), b.as_i64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutevar_pd&expand=4189)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilpd))]
+ pub unsafe fn _mm512_mask_permutevar_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512i,
+ ) -> __m512d {
+     let permute = _mm512_permutevar_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, permute, src.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutevar_pd&expand=4190)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilpd))]
+ pub unsafe fn _mm512_maskz_permutevar_pd(k: __mmask8, a: __m512d, b: __m512i) -> __m512d {
+     let permute = _mm512_permutevar_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 32-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutexvar_epi32&expand=4301)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //should be vpermd, but generate vpermps. It generates vpermd with mask
+ pub unsafe fn _mm512_permutexvar_epi32(idx: __m512i, a: __m512i) -> __m512i {
+     transmute(vpermd(a.as_i32x16(), idx.as_i32x16()))
+ }
+ 
+ /// Shuffle 32-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutexvar_epi32&expand=4299)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermd))]
+ pub unsafe fn _mm512_mask_permutexvar_epi32(
+     src: __m512i,
+     k: __mmask16,
+     idx: __m512i,
+     a: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutexvar_epi32(idx, a).as_i32x16();
+     transmute(simd_select_bitmask(k, permute, src.as_i32x16()))
+ }
+ 
+ /// Shuffle 32-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutexvar_epi32&expand=4300)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermd))]
+ pub unsafe fn _mm512_maskz_permutexvar_epi32(k: __mmask16, idx: __m512i, a: __m512i) -> __m512i {
+     let permute = _mm512_permutexvar_epi32(idx, a).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 64-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutexvar_epi64&expand=4307)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //should be vpermq, but generate vpermpd. It generates vpermd with mask
+ pub unsafe fn _mm512_permutexvar_epi64(idx: __m512i, a: __m512i) -> __m512i {
+     transmute(vpermq(a.as_i64x8(), idx.as_i64x8()))
+ }
+ 
+ /// Shuffle 64-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutexvar_epi64&expand=4305)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermq))]
+ pub unsafe fn _mm512_mask_permutexvar_epi64(
+     src: __m512i,
+     k: __mmask8,
+     idx: __m512i,
+     a: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutexvar_epi64(idx, a).as_i64x8();
+     transmute(simd_select_bitmask(k, permute, src.as_i64x8()))
+ }
+ 
+ /// Shuffle 64-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutexvar_epi64&expand=4306)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermq))]
+ pub unsafe fn _mm512_maskz_permutexvar_epi64(k: __mmask8, idx: __m512i, a: __m512i) -> __m512i {
+     let permute = _mm512_permutexvar_epi64(idx, a).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a across lanes using the corresponding index in idx.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutevar_ps&expand=4200)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermps))]
+ pub unsafe fn _mm512_permutexvar_ps(idx: __m512i, a: __m512) -> __m512 {
+     transmute(vpermps(a.as_f32x16(), idx.as_i32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutexvar_ps&expand=4326)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermps))]
+ pub unsafe fn _mm512_mask_permutexvar_ps(
+     src: __m512,
+     k: __mmask16,
+     idx: __m512i,
+     a: __m512,
+ ) -> __m512 {
+     let permute = _mm512_permutexvar_ps(idx, a).as_f32x16();
+     transmute(simd_select_bitmask(k, permute, src.as_f32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutexvar_ps&expand=4327)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermps))]
+ pub unsafe fn _mm512_maskz_permutexvar_ps(k: __mmask16, idx: __m512i, a: __m512) -> __m512 {
+     let permute = _mm512_permutexvar_ps(idx, a).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a across lanes using the corresponding index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutexvar_pd&expand=4322)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermpd))]
+ pub unsafe fn _mm512_permutexvar_pd(idx: __m512i, a: __m512d) -> __m512d {
+     transmute(vpermpd(a.as_f64x8(), idx.as_i64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutexvar_pd&expand=4320)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermpd))]
+ pub unsafe fn _mm512_mask_permutexvar_pd(
+     src: __m512d,
+     k: __mmask8,
+     idx: __m512i,
+     a: __m512d,
+ ) -> __m512d {
+     let permute = _mm512_permutexvar_pd(idx, a).as_f64x8();
+     transmute(simd_select_bitmask(k, permute, src.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutexvar_pd&expand=4321)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermpd))]
+ pub unsafe fn _mm512_maskz_permutexvar_pd(k: __mmask8, idx: __m512i, a: __m512d) -> __m512d {
+     let permute = _mm512_permutexvar_pd(idx, a).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 32-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutex2var_epi32&expand=4238)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d
+ pub unsafe fn _mm512_permutex2var_epi32(a: __m512i, idx: __m512i, b: __m512i) -> __m512i {
+     transmute(vpermi2d(a.as_i32x16(), idx.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Shuffle 32-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutex2var_epi32&expand=4235)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermt2d))]
+ pub unsafe fn _mm512_mask_permutex2var_epi32(
+     a: __m512i,
+     k: __mmask16,
+     idx: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutex2var_epi32(a, idx, b).as_i32x16();
+     transmute(simd_select_bitmask(k, permute, a.as_i32x16()))
+ }
+ 
+ /// Shuffle 32-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutex2var_epi32&expand=4237)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d
+ pub unsafe fn _mm512_maskz_permutex2var_epi32(
+     k: __mmask16,
+     a: __m512i,
+     idx: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutex2var_epi32(a, idx, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 32-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask2_permutex2var_epi32&expand=4236)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermi2d))]
+ pub unsafe fn _mm512_mask2_permutex2var_epi32(
+     a: __m512i,
+     idx: __m512i,
+     k: __mmask16,
+     b: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutex2var_epi32(a, idx, b).as_i32x16();
+     transmute(simd_select_bitmask(k, permute, idx.as_i32x16()))
+ }
+ 
+ /// Shuffle 64-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutex2var_epi64&expand=4250)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q
+ pub unsafe fn _mm512_permutex2var_epi64(a: __m512i, idx: __m512i, b: __m512i) -> __m512i {
+     transmute(vpermi2q(a.as_i64x8(), idx.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Shuffle 64-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutex2var_epi64&expand=4247)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermt2q))]
+ pub unsafe fn _mm512_mask_permutex2var_epi64(
+     a: __m512i,
+     k: __mmask8,
+     idx: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutex2var_epi64(a, idx, b).as_i64x8();
+     transmute(simd_select_bitmask(k, permute, a.as_i64x8()))
+ }
+ 
+ /// Shuffle 64-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutex2var_epi64&expand=4249)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q
+ pub unsafe fn _mm512_maskz_permutex2var_epi64(
+     k: __mmask8,
+     a: __m512i,
+     idx: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutex2var_epi64(a, idx, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle 64-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask2_permutex2var_epi64&expand=4248)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermi2q))]
+ pub unsafe fn _mm512_mask2_permutex2var_epi64(
+     a: __m512i,
+     idx: __m512i,
+     k: __mmask8,
+     b: __m512i,
+ ) -> __m512i {
+     let permute = _mm512_permutex2var_epi64(a, idx, b).as_i64x8();
+     transmute(simd_select_bitmask(k, permute, idx.as_i64x8()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutex2var_ps&expand=4286)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps
+ pub unsafe fn _mm512_permutex2var_ps(a: __m512, idx: __m512i, b: __m512) -> __m512 {
+     transmute(vpermi2ps(a.as_f32x16(), idx.as_i32x16(), b.as_f32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutex2var_ps&expand=4283)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermt2ps))]
+ pub unsafe fn _mm512_mask_permutex2var_ps(
+     a: __m512,
+     k: __mmask16,
+     idx: __m512i,
+     b: __m512,
+ ) -> __m512 {
+     let permute = _mm512_permutex2var_ps(a, idx, b).as_f32x16();
+     transmute(simd_select_bitmask(k, permute, a.as_f32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutex2var_ps&expand=4285)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps
+ pub unsafe fn _mm512_maskz_permutex2var_ps(
+     k: __mmask16,
+     a: __m512,
+     idx: __m512i,
+     b: __m512,
+ ) -> __m512 {
+     let permute = _mm512_permutex2var_ps(a, idx, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask2_permutex2var_ps&expand=4284)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2ps, but it shows vpermt2ps
+ pub unsafe fn _mm512_mask2_permutex2var_ps(
+     a: __m512,
+     idx: __m512i,
+     k: __mmask16,
+     b: __m512,
+ ) -> __m512 {
+     let permute = _mm512_permutex2var_ps(a, idx, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_permutex2var_pd&expand=4274)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd
+ pub unsafe fn _mm512_permutex2var_pd(a: __m512d, idx: __m512i, b: __m512d) -> __m512d {
+     transmute(vpermi2pd(a.as_f64x8(), idx.as_i64x8(), b.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_permutex2var_pd&expand=4271)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermt2pd))]
+ pub unsafe fn _mm512_mask_permutex2var_pd(
+     a: __m512d,
+     k: __mmask8,
+     idx: __m512i,
+     b: __m512d,
+ ) -> __m512d {
+     let permute = _mm512_permutex2var_pd(a, idx, b).as_f64x8();
+     transmute(simd_select_bitmask(k, permute, a.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_permutex2var_pd&expand=4273)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd
+ pub unsafe fn _mm512_maskz_permutex2var_pd(
+     k: __mmask8,
+     a: __m512d,
+     idx: __m512i,
+     b: __m512d,
+ ) -> __m512d {
+     let permute = _mm512_permutex2var_pd(a, idx, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask2_permutex2var_pd&expand=4272)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2pd, but it shows vpermt2pd
+ pub unsafe fn _mm512_mask2_permutex2var_pd(
+     a: __m512d,
+     idx: __m512i,
+     k: __mmask8,
+     b: __m512d,
+ ) -> __m512d {
+     let permute = _mm512_permutex2var_pd(a, idx, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, permute, zero))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_epi32&expand=5150)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpermilps, imm8 = 9))] //should be vpshufd, but generate vpermilps
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_shuffle_epi32(a: __m512i, imm8: _MM_PERM_ENUM) -> __m512i {
+     let imm8 = (imm8 & 0xFF) as u8;
+ 
+     let a = a.as_i32x16();
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 a,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 16, $e, $f, $g, 20, $i, $j, $k, 24, $m, $n, $o, 28),
+                 1 => shuffle4!($a, $b, $c, 17, $e, $f, $g, 21, $i, $j, $k, 25, $m, $n, $o, 29),
+                 2 => shuffle4!($a, $b, $c, 18, $e, $f, $g, 22, $i, $j, $k, 26, $m, $n, $o, 30),
+                 _ => shuffle4!($a, $b, $c, 19, $e, $f, $g, 23, $i, $j, $k, 27, $m, $n, $o, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 16, $e, $f, 20, $i, $j, 24, $m, $n, 28),
+                 1 => shuffle3!($a, $b, 17, $e, $f, 21, $i, $j, 25, $m, $n, 29),
+                 2 => shuffle3!($a, $b, 18, $e, $f, 22, $i, $j, 26, $m, $n, 30),
+                 _ => shuffle3!($a, $b, 19, $e, $f, 23, $i, $j, 27, $m, $n, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4, $i, 8, $m, 12),
+                 1 => shuffle2!($a, 1, $e, 5, $i, 9, $m, 13),
+                 2 => shuffle2!($a, 2, $e, 6, $i, 10, $m, 14),
+                 _ => shuffle2!($a, 3, $e, 7, $i, 11, $m, 15),
+             }
+         };
+     }
+     let r: i32x16 = match imm8 & 0x3 {
+         0 => shuffle1!(0, 4, 8, 12),
+         1 => shuffle1!(1, 5, 9, 13),
+         2 => shuffle1!(2, 6, 10, 14),
+         _ => shuffle1!(3, 7, 11, 15),
+     };
+     transmute(r)
+ }
+ 
+ /// Shuffle 32-bit integers in a within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_epi32&expand=5148)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpshufd, imm8 = 9))] //should be vpshufd, but generate vpermilps
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_mask_shuffle_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     imm8: _MM_PERM_ENUM,
+ ) -> __m512i {
+     let imm8 = (imm8 & 0xFF) as u8;
+ 
+     let a = a.as_i32x16();
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 a,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 16, $e, $f, $g, 20, $i, $j, $k, 24, $m, $n, $o, 28),
+                 1 => shuffle4!($a, $b, $c, 17, $e, $f, $g, 21, $i, $j, $k, 25, $m, $n, $o, 29),
+                 2 => shuffle4!($a, $b, $c, 18, $e, $f, $g, 22, $i, $j, $k, 26, $m, $n, $o, 30),
+                 _ => shuffle4!($a, $b, $c, 19, $e, $f, $g, 23, $i, $j, $k, 27, $m, $n, $o, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 16, $e, $f, 20, $i, $j, 24, $m, $n, 28),
+                 1 => shuffle3!($a, $b, 17, $e, $f, 21, $i, $j, 25, $m, $n, 29),
+                 2 => shuffle3!($a, $b, 18, $e, $f, 22, $i, $j, 26, $m, $n, 30),
+                 _ => shuffle3!($a, $b, 19, $e, $f, 23, $i, $j, 27, $m, $n, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4, $i, 8, $m, 12),
+                 1 => shuffle2!($a, 1, $e, 5, $i, 9, $m, 13),
+                 2 => shuffle2!($a, 2, $e, 6, $i, 10, $m, 14),
+                 _ => shuffle2!($a, 3, $e, 7, $i, 11, $m, 15),
+             }
+         };
+     }
+     let shuffle: i32x16 = match imm8 & 0x3 {
+         0 => shuffle1!(0, 4, 8, 12),
+         1 => shuffle1!(1, 5, 9, 13),
+         2 => shuffle1!(2, 6, 10, 14),
+         _ => shuffle1!(3, 7, 11, 15),
+     };
+     transmute(simd_select_bitmask(k, shuffle, src.as_i32x16()))
+ }
+ 
+ /// Shuffle 32-bit integers in a within 128-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_epi32&expand=5149)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpshufd, imm8 = 9))] //should be vpshufd, but generate vpermilps
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_maskz_shuffle_epi32(k: __mmask16, a: __m512i, imm8: _MM_PERM_ENUM) -> __m512i {
+     let imm8 = (imm8 & 0xFF) as u8;
+ 
+     let a = a.as_i32x16();
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 a,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 16, $e, $f, $g, 20, $i, $j, $k, 24, $m, $n, $o, 28),
+                 1 => shuffle4!($a, $b, $c, 17, $e, $f, $g, 21, $i, $j, $k, 25, $m, $n, $o, 29),
+                 2 => shuffle4!($a, $b, $c, 18, $e, $f, $g, 22, $i, $j, $k, 26, $m, $n, $o, 30),
+                 _ => shuffle4!($a, $b, $c, 19, $e, $f, $g, 23, $i, $j, $k, 27, $m, $n, $o, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 16, $e, $f, 20, $i, $j, 24, $m, $n, 28),
+                 1 => shuffle3!($a, $b, 17, $e, $f, 21, $i, $j, 25, $m, $n, 29),
+                 2 => shuffle3!($a, $b, 18, $e, $f, 22, $i, $j, 26, $m, $n, 30),
+                 _ => shuffle3!($a, $b, 19, $e, $f, 23, $i, $j, 27, $m, $n, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4, $i, 8, $m, 12),
+                 1 => shuffle2!($a, 1, $e, 5, $i, 9, $m, 13),
+                 2 => shuffle2!($a, 2, $e, 6, $i, 10, $m, 14),
+                 _ => shuffle2!($a, 3, $e, 7, $i, 11, $m, 15),
+             }
+         };
+     }
+     let shuffle: i32x16 = match imm8 & 0x3 {
+         0 => shuffle1!(0, 4, 8, 12),
+         1 => shuffle1!(1, 5, 9, 13),
+         2 => shuffle1!(2, 6, 10, 14),
+         _ => shuffle1!(3, 7, 11, 15),
+     };
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_ps&expand=5203)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufps, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_shuffle_ps(a: __m512, b: __m512, imm8: i32) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 16, $e, $f, $g, 20, $i, $j, $k, 24, $m, $n, $o, 28),
+                 1 => shuffle4!($a, $b, $c, 17, $e, $f, $g, 21, $i, $j, $k, 25, $m, $n, $o, 29),
+                 2 => shuffle4!($a, $b, $c, 18, $e, $f, $g, 22, $i, $j, $k, 26, $m, $n, $o, 30),
+                 _ => shuffle4!($a, $b, $c, 19, $e, $f, $g, 23, $i, $j, $k, 27, $m, $n, $o, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 16, $e, $f, 20, $i, $j, 24, $m, $n, 28),
+                 1 => shuffle3!($a, $b, 17, $e, $f, 21, $i, $j, 25, $m, $n, 29),
+                 2 => shuffle3!($a, $b, 18, $e, $f, 22, $i, $j, 26, $m, $n, 30),
+                 _ => shuffle3!($a, $b, 19, $e, $f, 23, $i, $j, 27, $m, $n, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4, $i, 8, $m, 12),
+                 1 => shuffle2!($a, 1, $e, 5, $i, 9, $m, 13),
+                 2 => shuffle2!($a, 2, $e, 6, $i, 10, $m, 14),
+                 _ => shuffle2!($a, 3, $e, 7, $i, 11, $m, 15),
+             }
+         };
+     }
+     match imm8 & 0x3 {
+         0 => shuffle1!(0, 4, 8, 12),
+         1 => shuffle1!(1, 5, 9, 13),
+         2 => shuffle1!(2, 6, 10, 14),
+         _ => shuffle1!(3, 7, 11, 15),
+     }
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_ps&expand=5201)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufps, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_shuffle_ps(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     imm8: i32,
+ ) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 16, $e, $f, $g, 20, $i, $j, $k, 24, $m, $n, $o, 28),
+                 1 => shuffle4!($a, $b, $c, 17, $e, $f, $g, 21, $i, $j, $k, 25, $m, $n, $o, 29),
+                 2 => shuffle4!($a, $b, $c, 18, $e, $f, $g, 22, $i, $j, $k, 26, $m, $n, $o, 30),
+                 _ => shuffle4!($a, $b, $c, 19, $e, $f, $g, 23, $i, $j, $k, 27, $m, $n, $o, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 16, $e, $f, 20, $i, $j, 24, $m, $n, 28),
+                 1 => shuffle3!($a, $b, 17, $e, $f, 21, $i, $j, 25, $m, $n, 29),
+                 2 => shuffle3!($a, $b, 18, $e, $f, 22, $i, $j, 26, $m, $n, 30),
+                 _ => shuffle3!($a, $b, 19, $e, $f, 23, $i, $j, 27, $m, $n, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4, $i, 8, $m, 12),
+                 1 => shuffle2!($a, 1, $e, 5, $i, 9, $m, 13),
+                 2 => shuffle2!($a, 2, $e, 6, $i, 10, $m, 14),
+                 _ => shuffle2!($a, 3, $e, 7, $i, 11, $m, 15),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 4, 8, 12),
+         1 => shuffle1!(1, 5, 9, 13),
+         2 => shuffle1!(2, 6, 10, 14),
+         _ => shuffle1!(3, 7, 11, 15),
+     };
+ 
+     transmute(simd_select_bitmask(k, shuffle, src.as_f32x16()))
+ }
+ 
+ /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_ps&expand=5202)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufps, imm8 = 0))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_shuffle_ps(k: __mmask16, a: __m512, b: __m512, imm8: i32) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, 16, $e, $f, $g, 20, $i, $j, $k, 24, $m, $n, $o, 28),
+                 1 => shuffle4!($a, $b, $c, 17, $e, $f, $g, 21, $i, $j, $k, 25, $m, $n, $o, 29),
+                 2 => shuffle4!($a, $b, $c, 18, $e, $f, $g, 22, $i, $j, $k, 26, $m, $n, $o, 30),
+                 _ => shuffle4!($a, $b, $c, 19, $e, $f, $g, 23, $i, $j, $k, 27, $m, $n, $o, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, 16, $e, $f, 20, $i, $j, 24, $m, $n, 28),
+                 1 => shuffle3!($a, $b, 17, $e, $f, 21, $i, $j, 25, $m, $n, 29),
+                 2 => shuffle3!($a, $b, 18, $e, $f, 22, $i, $j, 26, $m, $n, 30),
+                 _ => shuffle3!($a, $b, 19, $e, $f, 23, $i, $j, 27, $m, $n, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, 0, $e, 4, $i, 8, $m, 12),
+                 1 => shuffle2!($a, 1, $e, 5, $i, 9, $m, 13),
+                 2 => shuffle2!($a, 2, $e, 6, $i, 10, $m, 14),
+                 _ => shuffle2!($a, 3, $e, 7, $i, 11, $m, 15),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 4, 8, 12),
+         1 => shuffle1!(1, 5, 9, 13),
+         2 => shuffle1!(2, 6, 10, 14),
+         _ => shuffle1!(3, 7, 11, 15),
+     };
+ 
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in imm8, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_pd&expand=5192)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufpd, imm8 = 3))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_shuffle_pd(a: __m512d, b: __m512d, imm8: i32) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle8 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr, $h:expr) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle7 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 7) & 0x1 {
+                 0 => shuffle8!($a, $b, $c, $d, $e, $f, $g, 14),
+                 _ => shuffle8!($a, $b, $c, $d, $e, $f, $g, 15),
+             }
+         };
+     }
+     macro_rules! shuffle6 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 6) & 0x1 {
+                 0 => shuffle7!($a, $b, $c, $d, $e, $f, 6),
+                 _ => shuffle7!($a, $b, $c, $d, $e, $f, 7),
+             }
+         };
+     }
+     macro_rules! shuffle5 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr) => {
+             match (imm8 >> 5) & 0x1 {
+                 0 => shuffle6!($a, $b, $c, $d, $e, 12),
+                 _ => shuffle6!($a, $b, $c, $d, $e, 13),
+             }
+         };
+     }
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             match (imm8 >> 4) & 0x1 {
+                 0 => shuffle5!($a, $b, $c, $d, 4),
+                 _ => shuffle5!($a, $b, $c, $d, 5),
+             }
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 3) & 0x1 {
+                 0 => shuffle4!($a, $b, $c, 10),
+                 _ => shuffle4!($a, $b, $c, 11),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0x1 {
+                 0 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 1) & 0x1 {
+                 0 => shuffle2!($a, 8),
+                 _ => shuffle2!($a, 9),
+             }
+         };
+     }
+     match imm8 & 0x1 {
+         0 => shuffle1!(0),
+         _ => shuffle1!(1),
+     }
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_pd&expand=5190)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufpd, imm8 = 3))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_shuffle_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     imm8: i32,
+ ) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle8 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr, $h:expr) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle7 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 7) & 0x1 {
+                 0 => shuffle8!($a, $b, $c, $d, $e, $f, $g, 14),
+                 _ => shuffle8!($a, $b, $c, $d, $e, $f, $g, 15),
+             }
+         };
+     }
+     macro_rules! shuffle6 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 6) & 0x1 {
+                 0 => shuffle7!($a, $b, $c, $d, $e, $f, 6),
+                 _ => shuffle7!($a, $b, $c, $d, $e, $f, 7),
+             }
+         };
+     }
+     macro_rules! shuffle5 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr) => {
+             match (imm8 >> 5) & 0x1 {
+                 0 => shuffle6!($a, $b, $c, $d, $e, 12),
+                 _ => shuffle6!($a, $b, $c, $d, $e, 13),
+             }
+         };
+     }
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             match (imm8 >> 4) & 0x1 {
+                 0 => shuffle5!($a, $b, $c, $d, 4),
+                 _ => shuffle5!($a, $b, $c, $d, 5),
+             }
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 3) & 0x1 {
+                 0 => shuffle4!($a, $b, $c, 10),
+                 _ => shuffle4!($a, $b, $c, 11),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0x1 {
+                 0 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 1) & 0x1 {
+                 0 => shuffle2!($a, 8),
+                 _ => shuffle2!($a, 9),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x1 {
+         0 => shuffle1!(0),
+         _ => shuffle1!(1),
+     };
+ 
+     transmute(simd_select_bitmask(k, shuffle, src.as_f64x8()))
+ }
+ 
+ /// Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in imm8, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_pd&expand=5191)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufpd, imm8 = 3))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_shuffle_pd(k: __mmask8, a: __m512d, b: __m512d, imm8: i32) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle8 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr, $h:expr) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle7 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 7) & 0x1 {
+                 0 => shuffle8!($a, $b, $c, $d, $e, $f, $g, 14),
+                 _ => shuffle8!($a, $b, $c, $d, $e, $f, $g, 15),
+             }
+         };
+     }
+     macro_rules! shuffle6 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 6) & 0x1 {
+                 0 => shuffle7!($a, $b, $c, $d, $e, $f, 6),
+                 _ => shuffle7!($a, $b, $c, $d, $e, $f, 7),
+             }
+         };
+     }
+     macro_rules! shuffle5 {
+         ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr) => {
+             match (imm8 >> 5) & 0x1 {
+                 0 => shuffle6!($a, $b, $c, $d, $e, 12),
+                 _ => shuffle6!($a, $b, $c, $d, $e, 13),
+             }
+         };
+     }
+     macro_rules! shuffle4 {
+         ($a:expr, $b:expr, $c:expr, $d:expr) => {
+             match (imm8 >> 4) & 0x1 {
+                 0 => shuffle5!($a, $b, $c, $d, 4),
+                 _ => shuffle5!($a, $b, $c, $d, 5),
+             }
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr) => {
+             match (imm8 >> 3) & 0x1 {
+                 0 => shuffle4!($a, $b, $c, 10),
+                 _ => shuffle4!($a, $b, $c, 11),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr) => {
+             match (imm8 >> 2) & 0x1 {
+                 0 => shuffle3!($a, $b, 2),
+                 _ => shuffle3!($a, $b, 3),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr) => {
+             match (imm8 >> 1) & 0x1 {
+                 0 => shuffle2!($a, 8),
+                 _ => shuffle2!($a, 9),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x1 {
+         0 => shuffle1!(0),
+         _ => shuffle1!(1),
+     };
+ 
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Shuffle 128-bits (composed of 4 32-bit integers) selected by imm8 from a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_i32&expand=5177)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufi64x2, imm8 = 0b10111111))] //should be vshufi32x4, but generate vshufi64x2
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_shuffle_i32x4(a: __m512i, b: __m512i, imm8: i32) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i32x16();
+     let b = b.as_i32x16();
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 16, 17, 18, 19),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 20, 21, 22, 23),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 24, 25, 26, 27),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 16, 17, 18, 19),
+                 1 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 20, 21, 22, 23),
+                 2 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 24, 25, 26, 27),
+                 _ => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, $i, $m, 0, 1, 2, 3),
+                 1 => shuffle2!($a, $e, $i, $m, 4, 5, 6, 7),
+                 2 => shuffle2!($a, $e, $i, $m, 8, 9, 10, 11),
+                 _ => shuffle2!($a, $e, $i, $m, 12, 13, 14, 15),
+             }
+         };
+     }
+     let r: i32x16 = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1, 2, 3),
+         1 => shuffle1!(4, 5, 6, 7),
+         2 => shuffle1!(8, 9, 10, 11),
+         _ => shuffle1!(12, 13, 14, 15),
+     };
+ 
+     transmute(r)
+ }
+ 
+ /// Shuffle 128-bits (composed of 4 32-bit integers) selected by imm8 from a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_i32x&expand=5175)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufi32x4, imm8 = 0b10111111))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_shuffle_i32x4(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+     imm8: i32,
+ ) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i32x16();
+     let b = b.as_i32x16();
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 16, 17, 18, 19),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 20, 21, 22, 23),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 24, 25, 26, 27),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 16, 17, 18, 19),
+                 1 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 20, 21, 22, 23),
+                 2 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 24, 25, 26, 27),
+                 _ => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, $i, $m, 0, 1, 2, 3),
+                 1 => shuffle2!($a, $e, $i, $m, 4, 5, 6, 7),
+                 2 => shuffle2!($a, $e, $i, $m, 8, 9, 10, 11),
+                 _ => shuffle2!($a, $e, $i, $m, 12, 13, 14, 15),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1, 2, 3),
+         1 => shuffle1!(4, 5, 6, 7),
+         2 => shuffle1!(8, 9, 10, 11),
+         _ => shuffle1!(12, 13, 14, 15),
+     };
+ 
+     transmute(simd_select_bitmask(k, shuffle, src.as_i32x16()))
+ }
+ 
+ /// Shuffle 128-bits (composed of 4 32-bit integers) selected by imm8 from a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_i32&expand=5176)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufi32x4, imm8 = 0b10111111))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_shuffle_i32x4(
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+     imm8: i32,
+ ) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i32x16();
+     let b = b.as_i32x16();
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 16, 17, 18, 19),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 20, 21, 22, 23),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 24, 25, 26, 27),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 16, 17, 18, 19),
+                 1 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 20, 21, 22, 23),
+                 2 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 24, 25, 26, 27),
+                 _ => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, $i, $m, 0, 1, 2, 3),
+                 1 => shuffle2!($a, $e, $i, $m, 4, 5, 6, 7),
+                 2 => shuffle2!($a, $e, $i, $m, 8, 9, 10, 11),
+                 _ => shuffle2!($a, $e, $i, $m, 12, 13, 14, 15),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1, 2, 3),
+         1 => shuffle1!(4, 5, 6, 7),
+         2 => shuffle1!(8, 9, 10, 11),
+         _ => shuffle1!(12, 13, 14, 15),
+     };
+ 
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Shuffle 128-bits (composed of 2 64-bit integers) selected by imm8 from a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_i64x2&expand=5183)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufi64x2, imm8 = 0b10111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_shuffle_i64x2(a: __m512i, b: __m512i, imm8: i32) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, 8, 9),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, 10, 11),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, 12, 13),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, 8, 9),
+                 1 => shuffle3!($a, $b, $e, $f, 10, 11),
+                 2 => shuffle3!($a, $b, $e, $f, 12, 13),
+                 _ => shuffle3!($a, $b, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, 0, 1),
+                 1 => shuffle2!($a, $e, 2, 3),
+                 2 => shuffle2!($a, $e, 4, 5),
+                 _ => shuffle2!($a, $e, 6, 7),
+             }
+         };
+     }
+     match imm8 & 0x3 {
+         0 => shuffle1!(0, 1),
+         1 => shuffle1!(2, 3),
+         2 => shuffle1!(4, 5),
+         _ => shuffle1!(6, 7),
+     }
+ }
+ 
+ /// Shuffle 128-bits (composed of 2 64-bit integers) selected by imm8 from a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_i64x&expand=5181)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufi64x2, imm8 = 0b10111111))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_shuffle_i64x2(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     b: __m512i,
+     imm8: i32,
+ ) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, 8, 9),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, 10, 11),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, 12, 13),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, 8, 9),
+                 1 => shuffle3!($a, $b, $e, $f, 10, 11),
+                 2 => shuffle3!($a, $b, $e, $f, 12, 13),
+                 _ => shuffle3!($a, $b, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, 0, 1),
+                 1 => shuffle2!($a, $e, 2, 3),
+                 2 => shuffle2!($a, $e, 4, 5),
+                 _ => shuffle2!($a, $e, 6, 7),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1),
+         1 => shuffle1!(2, 3),
+         2 => shuffle1!(4, 5),
+         _ => shuffle1!(6, 7),
+     };
+ 
+     transmute(simd_select_bitmask(k, shuffle, src.as_i64x8()))
+ }
+ 
+ /// Shuffle 128-bits (composed of 2 64-bit integers) selected by imm8 from a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_i64&expand=5182)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshufi64x2, imm8 = 0b10111111))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_shuffle_i64x2(
+     k: __mmask8,
+     a: __m512i,
+     b: __m512i,
+     imm8: i32,
+ ) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, 8, 9),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, 10, 11),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, 12, 13),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, 8, 9),
+                 1 => shuffle3!($a, $b, $e, $f, 10, 11),
+                 2 => shuffle3!($a, $b, $e, $f, 12, 13),
+                 _ => shuffle3!($a, $b, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, 0, 1),
+                 1 => shuffle2!($a, $e, 2, 3),
+                 2 => shuffle2!($a, $e, 4, 5),
+                 _ => shuffle2!($a, $e, 6, 7),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1),
+         1 => shuffle1!(2, 3),
+         2 => shuffle1!(4, 5),
+         _ => shuffle1!(6, 7),
+     };
+ 
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by imm8 from a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_f32x4&expand=5165)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshuff64x2, imm8 = 0b10111111))] //should be vshuff32x4, but generate vshuff64x2
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_shuffle_f32x4(a: __m512, b: __m512, imm8: i32) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 16, 17, 18, 19),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 20, 21, 22, 23),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 24, 25, 26, 27),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 16, 17, 18, 19),
+                 1 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 20, 21, 22, 23),
+                 2 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 24, 25, 26, 27),
+                 _ => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, $i, $m, 0, 1, 2, 3),
+                 1 => shuffle2!($a, $e, $i, $m, 4, 5, 6, 7),
+                 2 => shuffle2!($a, $e, $i, $m, 8, 9, 10, 11),
+                 _ => shuffle2!($a, $e, $i, $m, 12, 13, 14, 15),
+             }
+         };
+     }
+     match imm8 & 0x3 {
+         0 => shuffle1!(0, 1, 2, 3),
+         1 => shuffle1!(4, 5, 6, 7),
+         2 => shuffle1!(8, 9, 10, 11),
+         _ => shuffle1!(12, 13, 14, 15),
+     }
+ }
+ 
+ /// Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by imm8 from a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_f32&expand=5163)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshuff32x4, imm8 = 0b10111111))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_shuffle_f32x4(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m512,
+     imm8: i32,
+ ) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 16, 17, 18, 19),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 20, 21, 22, 23),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 24, 25, 26, 27),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 16, 17, 18, 19),
+                 1 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 20, 21, 22, 23),
+                 2 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 24, 25, 26, 27),
+                 _ => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, $i, $m, 0, 1, 2, 3),
+                 1 => shuffle2!($a, $e, $i, $m, 4, 5, 6, 7),
+                 2 => shuffle2!($a, $e, $i, $m, 8, 9, 10, 11),
+                 _ => shuffle2!($a, $e, $i, $m, 12, 13, 14, 15),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1, 2, 3),
+         1 => shuffle1!(4, 5, 6, 7),
+         2 => shuffle1!(8, 9, 10, 11),
+         _ => shuffle1!(12, 13, 14, 15),
+     };
+ 
+     transmute(simd_select_bitmask(k, shuffle, src.as_f32x16()))
+ }
+ 
+ /// Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by imm8 from a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_f32&expand=5164)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshuff32x4, imm8 = 0b10111111))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_shuffle_f32x4(k: __mmask16, a: __m512, b: __m512, imm8: i32) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr,
+             $i:expr,
+             $j:expr,
+             $k:expr,
+             $l:expr,
+             $m:expr,
+             $n:expr,
+             $o:expr,
+             $p:expr
+         ) => {
+             simd_shuffle16(
+                 a,
+                 b,
+                 [
+                     $a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n, $o, $p,
+                 ],
+             );
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr, $i:expr, $j:expr, $k:expr, $m:expr, $n:expr, $o:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 16, 17, 18, 19),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 20, 21, 22, 23),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 24, 25, 26, 27),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, $i, $j, $k, $m, $n, $o, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr, $i:expr, $j:expr, $m:expr, $n:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 16, 17, 18, 19),
+                 1 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 20, 21, 22, 23),
+                 2 => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 24, 25, 26, 27),
+                 _ => shuffle3!($a, $b, $e, $f, $i, $j, $m, $n, 28, 29, 30, 31),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr, $i: expr, $m: expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, $i, $m, 0, 1, 2, 3),
+                 1 => shuffle2!($a, $e, $i, $m, 4, 5, 6, 7),
+                 2 => shuffle2!($a, $e, $i, $m, 8, 9, 10, 11),
+                 _ => shuffle2!($a, $e, $i, $m, 12, 13, 14, 15),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1, 2, 3),
+         1 => shuffle1!(4, 5, 6, 7),
+         2 => shuffle1!(8, 9, 10, 11),
+         _ => shuffle1!(12, 13, 14, 15),
+     };
+ 
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by imm8 from a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_shuffle_f64x2&expand=5171)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshuff64x2, imm8 = 0b10111111))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_shuffle_f64x2(a: __m512d, b: __m512d, imm8: i32) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, 8, 9),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, 10, 11),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, 12, 13),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, 8, 9),
+                 1 => shuffle3!($a, $b, $e, $f, 10, 11),
+                 2 => shuffle3!($a, $b, $e, $f, 12, 13),
+                 _ => shuffle3!($a, $b, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, 0, 1),
+                 1 => shuffle2!($a, $e, 2, 3),
+                 2 => shuffle2!($a, $e, 4, 5),
+                 _ => shuffle2!($a, $e, 6, 7),
+             }
+         };
+     }
+     match imm8 & 0x3 {
+         0 => shuffle1!(0, 1),
+         1 => shuffle1!(2, 3),
+         2 => shuffle1!(4, 5),
+         _ => shuffle1!(6, 7),
+     }
+ }
+ 
+ /// Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by imm8 from a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_shuffle_f64x2&expand=5169)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshuff64x2, imm8 = 0b10111111))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_shuffle_f64x2(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     imm8: i32,
+ ) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, 8, 9),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, 10, 11),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, 12, 13),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, 8, 9),
+                 1 => shuffle3!($a, $b, $e, $f, 10, 11),
+                 2 => shuffle3!($a, $b, $e, $f, 12, 13),
+                 _ => shuffle3!($a, $b, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, 0, 1),
+                 1 => shuffle2!($a, $e, 2, 3),
+                 2 => shuffle2!($a, $e, 4, 5),
+                 _ => shuffle2!($a, $e, 6, 7),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1),
+         1 => shuffle1!(2, 3),
+         2 => shuffle1!(4, 5),
+         _ => shuffle1!(6, 7),
+     };
+ 
+     transmute(simd_select_bitmask(k, shuffle, src.as_f64x8()))
+ }
+ 
+ /// Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by imm8 from a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_shuffle_f64x2&expand=5170)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vshuff64x2, imm8 = 0b10111111))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_shuffle_f64x2(
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     imm8: i32,
+ ) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 255);
+     let imm8 = (imm8 & 0xFF) as u8;
+     macro_rules! shuffle4 {
+         (
+             $a:expr,
+             $b:expr,
+             $c:expr,
+             $d:expr,
+             $e:expr,
+             $f:expr,
+             $g:expr,
+             $h:expr
+         ) => {
+             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
+         };
+     }
+     macro_rules! shuffle3 {
+         ($a:expr, $b:expr, $c:expr, $e:expr, $f:expr, $g:expr) => {
+             match (imm8 >> 6) & 0x3 {
+                 0 => shuffle4!($a, $b, $c, $e, $f, $g, 8, 9),
+                 1 => shuffle4!($a, $b, $c, $e, $f, $g, 10, 11),
+                 2 => shuffle4!($a, $b, $c, $e, $f, $g, 12, 13),
+                 _ => shuffle4!($a, $b, $c, $e, $f, $g, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle2 {
+         ($a:expr, $b:expr, $e:expr, $f:expr) => {
+             match (imm8 >> 4) & 0x3 {
+                 0 => shuffle3!($a, $b, $e, $f, 8, 9),
+                 1 => shuffle3!($a, $b, $e, $f, 10, 11),
+                 2 => shuffle3!($a, $b, $e, $f, 12, 13),
+                 _ => shuffle3!($a, $b, $e, $f, 14, 15),
+             }
+         };
+     }
+     macro_rules! shuffle1 {
+         ($a:expr, $e:expr) => {
+             match (imm8 >> 2) & 0x3 {
+                 0 => shuffle2!($a, $e, 0, 1),
+                 1 => shuffle2!($a, $e, 2, 3),
+                 2 => shuffle2!($a, $e, 4, 5),
+                 _ => shuffle2!($a, $e, 6, 7),
+             }
+         };
+     }
+     let shuffle = match imm8 & 0x3 {
+         0 => shuffle1!(0, 1),
+         1 => shuffle1!(2, 3),
+         2 => shuffle1!(4, 5),
+         _ => shuffle1!(6, 7),
+     };
+ 
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, shuffle, zero))
+ }
+ 
+ /// Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from a, selected with imm8, and store the result in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_extractf32x4_ps&expand=2442)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(vextractf32x4, imm8 = 3)
+ )]
+ #[rustc_args_required_const(1)]
+ pub unsafe fn _mm512_extractf32x4_ps(a: __m512, imm8: i32) -> __m128 {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     match imm8 & 0x3 {
+         0 => simd_shuffle4(a, _mm512_undefined_ps(), [0, 1, 2, 3]),
+         1 => simd_shuffle4(a, _mm512_undefined_ps(), [4, 5, 6, 7]),
+         2 => simd_shuffle4(a, _mm512_undefined_ps(), [8, 9, 10, 11]),
+         _ => simd_shuffle4(a, _mm512_undefined_ps(), [12, 13, 14, 15]),
+     }
+ }
+ 
+ /// Duplicate even-indexed single-precision (32-bit) floating-point elements from a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_moveldup_ps&expand=3862)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovsldup))]
+ pub unsafe fn _mm512_moveldup_ps(a: __m512) -> __m512 {
+     let r: f32x16 = simd_shuffle16(a, a, [0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14]);
+     transmute(r)
+ }
+ 
+ /// Duplicate even-indexed single-precision (32-bit) floating-point elements from a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_moveldup_ps&expand=3860)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovsldup))]
+ pub unsafe fn _mm512_mask_moveldup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+     let mov: f32x16 = simd_shuffle16(a, a, [0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14]);
+     transmute(simd_select_bitmask(k, mov, src.as_f32x16()))
+ }
+ 
+ /// Duplicate even-indexed single-precision (32-bit) floating-point elements from a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_moveldup_ps&expand=3861)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovsldup))]
+ pub unsafe fn _mm512_maskz_moveldup_ps(k: __mmask16, a: __m512) -> __m512 {
+     let mov: f32x16 = simd_shuffle16(a, a, [0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14]);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, mov, zero))
+ }
+ 
+ /// Duplicate odd-indexed single-precision (32-bit) floating-point elements from a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_movehdup_ps&expand=3852)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovshdup))]
+ pub unsafe fn _mm512_movehdup_ps(a: __m512) -> __m512 {
+     let r: f32x16 = simd_shuffle16(a, a, [1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15]);
+     transmute(r)
+ }
+ 
+ /// Duplicate odd-indexed single-precision (32-bit) floating-point elements from a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_movehdup&expand=3850)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovshdup))]
+ pub unsafe fn _mm512_mask_movehdup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 {
+     let mov: f32x16 = simd_shuffle16(a, a, [1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15]);
+     transmute(simd_select_bitmask(k, mov, src.as_f32x16()))
+ }
+ 
+ /// Duplicate odd-indexed single-precision (32-bit) floating-point elements from a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_moveh&expand=3851)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovshdup))]
+ pub unsafe fn _mm512_maskz_movehdup_ps(k: __mmask16, a: __m512) -> __m512 {
+     let mov: f32x16 = simd_shuffle16(a, a, [1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15]);
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, mov, zero))
+ }
+ 
+ /// Duplicate even-indexed double-precision (64-bit) floating-point elements from a, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_movedup_pd&expand=3843)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovddup))]
+ pub unsafe fn _mm512_movedup_pd(a: __m512d) -> __m512d {
+     let r: f64x8 = simd_shuffle8(a, a, [0, 0, 2, 2, 4, 4, 6, 6]);
+     transmute(r)
+ }
+ 
+ /// Duplicate even-indexed double-precision (64-bit) floating-point elements from a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_movedup_pd&expand=3841)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovddup))]
+ pub unsafe fn _mm512_mask_movedup_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d {
+     let mov: f64x8 = simd_shuffle8(a, a, [0, 0, 2, 2, 4, 4, 6, 6]);
+     transmute(simd_select_bitmask(k, mov, src.as_f64x8()))
+ }
+ 
+ /// Duplicate even-indexed double-precision (64-bit) floating-point elements from a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_movedup_pd&expand=3842)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovddup))]
+ pub unsafe fn _mm512_maskz_movedup_pd(k: __mmask8, a: __m512d) -> __m512d {
+     let mov: f64x8 = simd_shuffle8(a, a, [0, 0, 2, 2, 4, 4, 6, 6]);
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, mov, zero))
+ }
+ 
+ /// Copy a to dst, then insert 128 bits (composed of 4 packed 32-bit integers) from b into dst at the location specified by imm8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_inserti32x4&expand=3174)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf32x4, imm8 = 2))] //should be vinserti32x4
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_inserti32x4(a: __m512i, b: __m128i, imm8: i32) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     let a = a.as_i32x16();
+     let b = _mm512_castsi128_si512(b).as_i32x16();
+     let ret: i32x16 = match imm8 & 0b11 {
+         0 => simd_shuffle16(
+             a,
+             b,
+             [16, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 12, 13, 14, 15],
+         ),
+         _ => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19]),
+     };
+     transmute(ret)
+ }
+ 
+ /// Copy a to tmp, then insert 128 bits (composed of 4 packed 32-bit integers) from b into tmp at the location specified by imm8. Store tmp to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_inserti32x4&expand=3175)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinserti32x4, imm8 = 2))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_inserti32x4(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m128i,
+     imm8: i32,
+ ) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     let a = a.as_i32x16();
+     let b = _mm512_castsi128_si512(b).as_i32x16();
+     let insert: i32x16 = match imm8 & 0b11 {
+         0 => simd_shuffle16(
+             a,
+             b,
+             [16, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 12, 13, 14, 15],
+         ),
+         _ => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19]),
+     };
+     transmute(simd_select_bitmask(k, insert, src.as_i32x16()))
+ }
+ 
+ /// Copy a to tmp, then insert 128 bits (composed of 4 packed 32-bit integers) from b into tmp at the location specified by imm8. Store tmp to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_inserti32x4&expand=3176)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinserti32x4, imm8 = 2))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_inserti32x4(k: __mmask16, a: __m512i, b: __m128i, imm8: i32) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     let a = a.as_i32x16();
+     let b = _mm512_castsi128_si512(b).as_i32x16();
+     let insert = match imm8 & 0b11 {
+         0 => simd_shuffle16(
+             a,
+             b,
+             [16, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 12, 13, 14, 15],
+         ),
+         _ => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19]),
+     };
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, insert, zero))
+ }
+ 
+ /// Copy a to dst, then insert 256 bits (composed of 4 packed 64-bit integers) from b into dst at the location specified by imm8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_inserti64x4&expand=3186)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf64x4, imm8 = 1))] //should be vinserti64x4
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_inserti64x4(a: __m512i, b: __m256i, imm8: i32) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 1);
+     let b = _mm512_castsi256_si512(b);
+     match imm8 & 0b1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     }
+ }
+ 
+ /// Copy a to tmp, then insert 256 bits (composed of 4 packed 64-bit integers) from b into tmp at the location specified by imm8. Store tmp to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_inserti64x4&expand=3187)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinserti64x4, imm8 = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_inserti64x4(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     b: __m256i,
+     imm8: i32,
+ ) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 1);
+     let b = _mm512_castsi256_si512(b);
+     let insert = match imm8 & 0b1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     };
+     transmute(simd_select_bitmask(k, insert, src.as_i64x8()))
+ }
+ 
+ /// Copy a to tmp, then insert 256 bits (composed of 4 packed 64-bit integers) from b into tmp at the location specified by imm8. Store tmp to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_inserti64x4&expand=3188)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinserti64x4, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_inserti64x4(k: __mmask8, a: __m512i, b: __m256i, imm8: i32) -> __m512i {
+     assert!(imm8 >= 0 && imm8 <= 1);
+     let b = _mm512_castsi256_si512(b);
+     let insert = match imm8 & 0b1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     };
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, insert, zero))
+ }
+ 
+ /// Copy a to dst, then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from b into dst at the location specified by imm8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_insertf32x4&expand=3155)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf32x4, imm8 = 2))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_insertf32x4(a: __m512, b: __m128, imm8: i32) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     let b = _mm512_castps128_ps512(b);
+     match imm8 & 0b11 {
+         0 => simd_shuffle16(
+             a,
+             b,
+             [16, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 12, 13, 14, 15],
+         ),
+         _ => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19]),
+     }
+ }
+ 
+ /// Copy a to tmp, then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from b into tmp at the location specified by imm8. Store tmp to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_insertf32x4&expand=3156)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf32x4, imm8 = 2))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_insertf32x4(
+     src: __m512,
+     k: __mmask16,
+     a: __m512,
+     b: __m128,
+     imm8: i32,
+ ) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     let b = _mm512_castps128_ps512(b);
+     let insert = match imm8 & 0b11 {
+         0 => simd_shuffle16(
+             a,
+             b,
+             [16, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 12, 13, 14, 15],
+         ),
+         _ => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19]),
+     };
+     transmute(simd_select_bitmask(k, insert, src.as_f32x16()))
+ }
+ 
+ /// Copy a to tmp, then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from b into tmp at the location specified by imm8. Store tmp to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_insertf32x4&expand=3157)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf32x4, imm8 = 2))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_insertf32x4(k: __mmask16, a: __m512, b: __m128, imm8: i32) -> __m512 {
+     assert!(imm8 >= 0 && imm8 <= 3);
+     let b = _mm512_castps128_ps512(b);
+     let insert = match imm8 & 0b11 {
+         0 => simd_shuffle16(
+             a,
+             b,
+             [16, 17, 18, 19, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         1 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 12, 13, 14, 15],
+         ),
+         2 => simd_shuffle16(
+             a,
+             b,
+             [0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 12, 13, 14, 15],
+         ),
+         _ => simd_shuffle16(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19]),
+     };
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, insert, zero))
+ }
+ 
+ /// Copy a to dst, then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from b into dst at the location specified by imm8.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_insertf64x4&expand=3167)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf64x4, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ pub unsafe fn _mm512_insertf64x4(a: __m512d, b: __m256d, imm8: i32) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 1);
+     let b = _mm512_castpd256_pd512(b);
+     match imm8 & 0b1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     }
+ }
+ 
+ /// Copy a to tmp, then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from b into tmp at the location specified by imm8. Store tmp to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_insertf64x4&expand=3168)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf64x4, imm8 = 1))]
+ #[rustc_args_required_const(4)]
+ pub unsafe fn _mm512_mask_insertf64x4(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m256d,
+     imm8: i32,
+ ) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 1);
+     let b = _mm512_castpd256_pd512(b);
+     let insert = match imm8 & 0b1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     };
+     transmute(simd_select_bitmask(k, insert, src.as_f64x8()))
+ }
+ 
+ /// Copy a to tmp, then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from b into tmp at the location specified by imm8. Store tmp to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_insertf64x4&expand=3169)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vinsertf64x4, imm8 = 1))]
+ #[rustc_args_required_const(3)]
+ pub unsafe fn _mm512_maskz_insertf64x4(k: __mmask8, a: __m512d, b: __m256d, imm8: i32) -> __m512d {
+     assert!(imm8 >= 0 && imm8 <= 1);
+     let b = _mm512_castpd256_pd512(b);
+     let insert = match imm8 & 0b1 {
+         0 => simd_shuffle8(a, b, [8, 9, 10, 11, 4, 5, 6, 7]),
+         _ => simd_shuffle8(a, b, [0, 1, 2, 3, 8, 9, 10, 11]),
+     };
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, insert, zero))
+ }
+ 
+ /// Unpack and interleave 32-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpackhi_epi32&expand=6021)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhps))] //should be vpunpckhdq
+ pub unsafe fn _mm512_unpackhi_epi32(a: __m512i, b: __m512i) -> __m512i {
+     let a = a.as_i32x16();
+     let b = b.as_i32x16();
+     let r: i32x16 = simd_shuffle16(
+         a,
+         b,
+         [
+             2,
+             18,
+             3,
+             19,
+             2 + 4,
+             18 + 4,
+             3 + 4,
+             19 + 4,
+             2 + 8,
+             18 + 8,
+             3 + 8,
+             19 + 8,
+             2 + 12,
+             18 + 12,
+             3 + 12,
+             19 + 12,
+         ],
+     );
+     transmute(r)
+ }
+ 
+ /// Unpack and interleave 32-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpackhi_epi32&expand=6019)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpckhdq))]
+ pub unsafe fn _mm512_mask_unpackhi_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let unpackhi = _mm512_unpackhi_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_i32x16()))
+ }
+ 
+ /// Unpack and interleave 32-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpackhi_epi32&expand=6020)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpckhdq))]
+ pub unsafe fn _mm512_maskz_unpackhi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let unpackhi = _mm512_unpackhi_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave 64-bit integers from the high half of each 128-bit lane in a and b, and
+ /// store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpackhi_epi64&expand=6030)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhpd))] //should be vpunpckhqdq
+ pub unsafe fn _mm512_unpackhi_epi64(a: __m512i, b: __m512i) -> __m512i {
+     simd_shuffle8(a, b, [1, 9, 1 + 2, 9 + 2, 1 + 4, 9 + 4, 1 + 6, 9 + 6])
+ }
+ 
+ /// Unpack and interleave 64-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpackhi_epi64&expand=6028)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpckhqdq))]
+ pub unsafe fn _mm512_mask_unpackhi_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let unpackhi = _mm512_unpackhi_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_i64x8()))
+ }
+ 
+ /// Unpack and interleave 64-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpackhi_epi64&expand=6029)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpckhqdq))]
+ pub unsafe fn _mm512_maskz_unpackhi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let unpackhi = _mm512_unpackhi_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpackhi_ps&expand=6060)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhps))]
+ pub unsafe fn _mm512_unpackhi_ps(a: __m512, b: __m512) -> __m512 {
+     simd_shuffle16(
+         a,
+         b,
+         [
+             2,
+             18,
+             3,
+             19,
+             2 + 4,
+             18 + 4,
+             3 + 4,
+             19 + 4,
+             2 + 8,
+             18 + 8,
+             3 + 8,
+             19 + 8,
+             2 + 12,
+             18 + 12,
+             3 + 12,
+             19 + 12,
+         ],
+     )
+ }
+ 
+ /// Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpackhi_ps&expand=6058)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhps))]
+ pub unsafe fn _mm512_mask_unpackhi_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let unpackhi = _mm512_unpackhi_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_f32x16()))
+ }
+ 
+ /// Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpackhi_ps&expand=6059)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhps))]
+ pub unsafe fn _mm512_maskz_unpackhi_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let unpackhi = _mm512_unpackhi_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpackhi_pd&expand=6048)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhpd))]
+ pub unsafe fn _mm512_unpackhi_pd(a: __m512d, b: __m512d) -> __m512d {
+     simd_shuffle8(a, b, [1, 9, 1 + 2, 9 + 2, 1 + 4, 9 + 4, 1 + 6, 9 + 6])
+ }
+ 
+ /// Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpackhi_pd&expand=6046)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhpd))]
+ pub unsafe fn _mm512_mask_unpackhi_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+ ) -> __m512d {
+     let unpackhi = _mm512_unpackhi_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_f64x8()))
+ }
+ 
+ /// Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpackhi_pd&expand=6047)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpckhpd))]
+ pub unsafe fn _mm512_maskz_unpackhi_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let unpackhi = _mm512_unpackhi_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave 32-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpacklo_epi32&expand=6078)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklps))] //should be vpunpckldq
+ pub unsafe fn _mm512_unpacklo_epi32(a: __m512i, b: __m512i) -> __m512i {
+     let a = a.as_i32x16();
+     let b = b.as_i32x16();
+     let r: i32x16 = simd_shuffle16(
+         a,
+         b,
+         [
+             0,
+             16,
+             1,
+             17,
+             0 + 4,
+             16 + 4,
+             1 + 4,
+             17 + 4,
+             0 + 8,
+             16 + 8,
+             1 + 8,
+             17 + 8,
+             0 + 12,
+             16 + 12,
+             1 + 12,
+             17 + 12,
+         ],
+     );
+     transmute(r)
+ }
+ 
+ /// Unpack and interleave 32-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpacklo_epi32&expand=6076)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpckldq))]
+ pub unsafe fn _mm512_mask_unpacklo_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let unpackhi = _mm512_unpacklo_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_i32x16()))
+ }
+ 
+ /// Unpack and interleave 32-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpacklo_epi32&expand=6077)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpckldq))]
+ pub unsafe fn _mm512_maskz_unpacklo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let unpackhi = _mm512_unpacklo_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave 64-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpacklo_epi64&expand=6087)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklpd))] //should be vpunpcklqdq
+ pub unsafe fn _mm512_unpacklo_epi64(a: __m512i, b: __m512i) -> __m512i {
+     simd_shuffle8(a, b, [0, 8, 0 + 2, 8 + 2, 0 + 4, 8 + 4, 0 + 6, 8 + 6])
+ }
+ 
+ /// Unpack and interleave 64-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpacklo_epi64&expand=6085)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpcklqdq))]
+ pub unsafe fn _mm512_mask_unpacklo_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let unpackhi = _mm512_unpacklo_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_i64x8()))
+ }
+ 
+ /// Unpack and interleave 64-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpacklo_epi64&expand=6086)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpunpcklqdq))]
+ pub unsafe fn _mm512_maskz_unpacklo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let unpackhi = _mm512_unpacklo_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpacklo_ps&expand=6117)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklps))]
+ pub unsafe fn _mm512_unpacklo_ps(a: __m512, b: __m512) -> __m512 {
+     simd_shuffle16(
+         a,
+         b,
+         [
+             0,
+             16,
+             1,
+             17,
+             0 + 4,
+             16 + 4,
+             1 + 4,
+             17 + 4,
+             0 + 8,
+             16 + 8,
+             1 + 8,
+             17 + 8,
+             0 + 12,
+             16 + 12,
+             1 + 12,
+             17 + 12,
+         ],
+     )
+ }
+ 
+ /// Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpacklo_ps&expand=6115)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklps))]
+ pub unsafe fn _mm512_mask_unpacklo_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let unpackhi = _mm512_unpacklo_ps(a, b).as_f32x16();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_f32x16()))
+ }
+ 
+ /// Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpacklo_ps&expand=6116)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklps))]
+ pub unsafe fn _mm512_maskz_unpacklo_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     let unpackhi = _mm512_unpacklo_ps(a, b).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_unpacklo_pd&expand=6105)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklpd))]
+ pub unsafe fn _mm512_unpacklo_pd(a: __m512d, b: __m512d) -> __m512d {
+     simd_shuffle8(a, b, [0, 8, 0 + 2, 8 + 2, 0 + 4, 8 + 4, 0 + 6, 8 + 6])
+ }
+ 
+ /// Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_unpacklo_pd&expand=6103)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklpd))]
+ pub unsafe fn _mm512_mask_unpacklo_pd(
+     src: __m512d,
+     k: __mmask8,
+     a: __m512d,
+     b: __m512d,
+ ) -> __m512d {
+     let unpackhi = _mm512_unpacklo_pd(a, b).as_f64x8();
+     transmute(simd_select_bitmask(k, unpackhi, src.as_f64x8()))
+ }
+ 
+ /// Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_unpacklo_pd&expand=6104)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vunpcklpd))]
+ pub unsafe fn _mm512_maskz_unpacklo_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     let unpackhi = _mm512_unpacklo_pd(a, b).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, unpackhi, zero))
+ }
+ 
+ /// Cast vector of type __m128 to type __m512; the upper 384 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castps128_ps512&expand=621)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castps128_ps512(a: __m128) -> __m512 {
+     simd_shuffle16(
+         a,
+         _mm_set1_ps(-1.),
+         [0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4],
+     )
+ }
+ 
+ /// Cast vector of type __m256 to type __m512; the upper 256 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castps256_ps512&expand=623)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castps256_ps512(a: __m256) -> __m512 {
+     simd_shuffle16(
+         a,
+         _mm256_set1_ps(-1.),
+         [0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 8, 8, 8, 8, 8],
+     )
+ }
+ 
+ /// Cast vector of type __m512 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castps512_ps128&expand=624)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castps512_ps128(a: __m512) -> __m128 {
+     simd_shuffle4(a, a, [0, 1, 2, 3])
+ }
+ 
+ /// Cast vector of type __m512 to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castps512_ps256&expand=625)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castps512_ps256(a: __m512) -> __m256 {
+     simd_shuffle8(a, a, [0, 1, 2, 3, 4, 5, 6, 7])
+ }
+ 
+ /// Cast vector of type __m512 to type __m512d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castps_pd&expand=616)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castps_pd(a: __m512) -> __m512d {
+     transmute(a.as_m512())
+ }
+ 
+ /// Cast vector of type __m512 to type __m512i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castps_si512&expand=619)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castps_si512(a: __m512) -> __m512i {
+     transmute(a.as_m512())
+ }
+ 
+ /// Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castpd128_pd512&expand=609)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castpd128_pd512(a: __m128d) -> __m512d {
+     simd_shuffle8(a, _mm_set1_pd(-1.), [0, 1, 2, 2, 2, 2, 2, 2])
+ }
+ 
+ /// Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castpd256_pd512&expand=611)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castpd256_pd512(a: __m256d) -> __m512d {
+     simd_shuffle8(a, _mm256_set1_pd(-1.), [0, 1, 2, 3, 4, 4, 4, 4])
+ }
+ 
+ /// Cast vector of type __m512d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castpd512_pd128&expand=612)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castpd512_pd128(a: __m512d) -> __m128d {
+     simd_shuffle2(a, a, [0, 1])
+ }
+ 
+ /// Cast vector of type __m512d to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castpd512_pd256&expand=613)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castpd512_pd256(a: __m512d) -> __m256d {
+     simd_shuffle4(a, a, [0, 1, 2, 3])
+ }
+ 
+ /// Cast vector of type __m512d to type __m512. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castpd_ps&expand=604)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castpd_ps(a: __m512d) -> __m512 {
+     transmute(a.as_m512d())
+ }
+ 
+ /// Cast vector of type __m512d to type __m512i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castpd_si512&expand=607)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castpd_si512(a: __m512d) -> __m512i {
+     transmute(a.as_m512d())
+ }
+ 
+ /// Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castsi128_si512&expand=629)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castsi128_si512(a: __m128i) -> __m512i {
+     simd_shuffle8(a, _mm_set1_epi64x(-1), [0, 1, 2, 2, 2, 2, 2, 2])
+ }
+ 
+ /// Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castsi256_si512&expand=633)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castsi256_si512(a: __m256i) -> __m512i {
+     simd_shuffle8(a, _mm256_set1_epi64x(-1), [0, 1, 2, 3, 4, 4, 4, 4])
+ }
+ 
+ /// Cast vector of type __m512i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castsi512_si128&expand=636)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castsi512_si128(a: __m512i) -> __m128i {
+     simd_shuffle2(a, a, [0, 1])
+ }
+ 
+ /// Cast vector of type __m512i to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castsi512_si256&expand=637)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castsi512_si256(a: __m512i) -> __m256i {
+     simd_shuffle4(a, a, [0, 1, 2, 3])
+ }
+ 
+ /// Cast vector of type __m512i to type __m512. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castsi512_ps&expand=635)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castsi512_ps(a: __m512i) -> __m512 {
+     transmute(a)
+ }
+ 
+ /// Cast vector of type __m512i to type __m512d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_castsi512_pd&expand=634)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_castsi512_pd(a: __m512i) -> __m512d {
+     transmute(a)
+ }
+ 
+ /// Broadcast the low packed 32-bit integer from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcastd_epi32&expand=545)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcast))] //should be vpbroadcastd
+ pub unsafe fn _mm512_broadcastd_epi32(a: __m128i) -> __m512i {
+     let a = _mm512_castsi128_si512(a).as_i32x16();
+     let ret: i32x16 = simd_shuffle16(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]);
+     transmute(ret)
+ }
+ 
+ /// Broadcast the low packed 32-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcastd_epi32&expand=546)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
+ pub unsafe fn _mm512_mask_broadcastd_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+     let broadcast = _mm512_broadcastd_epi32(a).as_i32x16();
+     transmute(simd_select_bitmask(k, broadcast, src.as_i32x16()))
+ }
+ 
+ /// Broadcast the low packed 32-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcastd_epi32&expand=547)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd
+ pub unsafe fn _mm512_maskz_broadcastd_epi32(k: __mmask16, a: __m128i) -> __m512i {
+     let broadcast = _mm512_broadcastd_epi32(a).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the low packed 64-bit integer from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcastq_epi64&expand=560)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcas))] //should be vpbroadcastq
+ pub unsafe fn _mm512_broadcastq_epi64(a: __m128i) -> __m512i {
+     simd_shuffle8(a, a, [0, 0, 0, 0, 0, 0, 0, 0])
+ }
+ 
+ /// Broadcast the low packed 64-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcastq_epi64&expand=561)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
+ pub unsafe fn _mm512_mask_broadcastq_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i {
+     let broadcast = _mm512_broadcastq_epi64(a).as_i64x8();
+     transmute(simd_select_bitmask(k, broadcast, src.as_i64x8()))
+ }
+ 
+ /// Broadcast the low packed 64-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcastq_epi64&expand=562)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq
+ pub unsafe fn _mm512_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m512i {
+     let broadcast = _mm512_broadcastq_epi64(a).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the low single-precision (32-bit) floating-point element from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcastss_ps&expand=578)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ pub unsafe fn _mm512_broadcastss_ps(a: __m128) -> __m512 {
+     simd_shuffle16(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
+ }
+ 
+ /// Broadcast the low single-precision (32-bit) floating-point element from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcastss_ps&expand=579)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ pub unsafe fn _mm512_mask_broadcastss_ps(src: __m512, k: __mmask16, a: __m128) -> __m512 {
+     let broadcast = _mm512_broadcastss_ps(a).as_f32x16();
+     transmute(simd_select_bitmask(k, broadcast, src.as_f32x16()))
+ }
+ 
+ /// Broadcast the low single-precision (32-bit) floating-point element from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcastss_ps&expand=580)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcastss))]
+ pub unsafe fn _mm512_maskz_broadcastss_ps(k: __mmask16, a: __m128) -> __m512 {
+     let broadcast = _mm512_broadcastss_ps(a).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the low double-precision (64-bit) floating-point element from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcastsd_pd&expand=567)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcastsd))]
+ pub unsafe fn _mm512_broadcastsd_pd(a: __m128d) -> __m512d {
+     simd_shuffle8(a, a, [1, 1, 1, 1, 1, 1, 1, 1])
+ }
+ 
+ /// Broadcast the low double-precision (64-bit) floating-point element from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcastsd_pd&expand=568)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcastsd))]
+ pub unsafe fn _mm512_mask_broadcastsd_pd(src: __m512d, k: __mmask8, a: __m128d) -> __m512d {
+     let broadcast = _mm512_broadcastsd_pd(a).as_f64x8();
+     transmute(simd_select_bitmask(k, broadcast, src.as_f64x8()))
+ }
+ 
+ /// Broadcast the low double-precision (64-bit) floating-point element from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcastsd_pd&expand=569)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vbroadcastsd))]
+ pub unsafe fn _mm512_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m512d {
+     let broadcast = _mm512_broadcastsd_pd(a).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the 4 packed 32-bit integers from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcast_i32x4&expand=510)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf
+ pub unsafe fn _mm512_broadcast_i32x4(a: __m128i) -> __m512i {
+     let a = _mm512_castsi128_si512(a).as_i32x16();
+     let ret: i32x16 = simd_shuffle16(a, a, [0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3]);
+     transmute(ret)
+ }
+ 
+ /// Broadcast the 4 packed 32-bit integers from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcast_i32x4&expand=511)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf
+ pub unsafe fn _mm512_mask_broadcast_i32x4(src: __m512i, k: __mmask16, a: __m128i) -> __m512i {
+     let broadcast = _mm512_broadcast_i32x4(a).as_i32x16();
+     transmute(simd_select_bitmask(k, broadcast, src.as_i32x16()))
+ }
+ 
+ /// Broadcast the 4 packed 32-bit integers from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcast_i32x4&expand=512)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf
+ pub unsafe fn _mm512_maskz_broadcast_i32x4(k: __mmask16, a: __m128i) -> __m512i {
+     let broadcast = _mm512_broadcast_i32x4(a).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the 4 packed 64-bit integers from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcast_i64x4&expand=522)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm
+ pub unsafe fn _mm512_broadcast_i64x4(a: __m256i) -> __m512i {
+     simd_shuffle8(a, a, [0, 1, 2, 3, 0, 1, 2, 3])
+ }
+ 
+ /// Broadcast the 4 packed 64-bit integers from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcast_i64x4&expand=523)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm
+ pub unsafe fn _mm512_mask_broadcast_i64x4(src: __m512i, k: __mmask8, a: __m256i) -> __m512i {
+     let broadcast = _mm512_broadcast_i64x4(a).as_i64x8();
+     transmute(simd_select_bitmask(k, broadcast, src.as_i64x8()))
+ }
+ 
+ /// Broadcast the 4 packed 64-bit integers from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcast_i64x4&expand=524)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm
+ pub unsafe fn _mm512_maskz_broadcast_i64x4(k: __mmask8, a: __m256i) -> __m512i {
+     let broadcast = _mm512_broadcast_i64x4(a).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the 4 packed single-precision (32-bit) floating-point elements from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcast_f32x4&expand=483)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshuf
+ pub unsafe fn _mm512_broadcast_f32x4(a: __m128) -> __m512 {
+     simd_shuffle16(a, a, [0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3])
+ }
+ 
+ /// Broadcast the 4 packed single-precision (32-bit) floating-point elements from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcast_f32x4&expand=484)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshu
+ pub unsafe fn _mm512_mask_broadcast_f32x4(src: __m512, k: __mmask16, a: __m128) -> __m512 {
+     let broadcast = _mm512_broadcast_f32x4(a).as_f32x16();
+     transmute(simd_select_bitmask(k, broadcast, src.as_f32x16()))
+ }
+ 
+ /// Broadcast the 4 packed single-precision (32-bit) floating-point elements from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcast_f32x4&expand=485)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshu
+ pub unsafe fn _mm512_maskz_broadcast_f32x4(k: __mmask16, a: __m128) -> __m512 {
+     let broadcast = _mm512_broadcast_f32x4(a).as_f32x16();
+     let zero = _mm512_setzero_ps().as_f32x16();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Broadcast the 4 packed double-precision (64-bit) floating-point elements from a to all elements of dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_broadcast_f64x4&expand=495)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vperm
+ pub unsafe fn _mm512_broadcast_f64x4(a: __m256d) -> __m512d {
+     simd_shuffle8(a, a, [0, 1, 2, 3, 0, 1, 2, 3])
+ }
+ 
+ /// Broadcast the 4 packed double-precision (64-bit) floating-point elements from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_broadcast_f64x4&expand=496)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vper
+ pub unsafe fn _mm512_mask_broadcast_f64x4(src: __m512d, k: __mmask8, a: __m256d) -> __m512d {
+     let broadcast = _mm512_broadcast_f64x4(a).as_f64x8();
+     transmute(simd_select_bitmask(k, broadcast, src.as_f64x8()))
+ }
+ 
+ /// Broadcast the 4 packed double-precision (64-bit) floating-point elements from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_broadcast_f64x4&expand=497)
+ #[inline]
+ #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vper
+ pub unsafe fn _mm512_maskz_broadcast_f64x4(k: __mmask8, a: __m256d) -> __m512d {
+     let broadcast = _mm512_broadcast_f64x4(a).as_f64x8();
+     let zero = _mm512_setzero_pd().as_f64x8();
+     transmute(simd_select_bitmask(k, broadcast, zero))
+ }
+ 
+ /// Blend packed 32-bit integers from a and b using control mask k, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_blend_epi32&expand=435)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd
+ pub unsafe fn _mm512_mask_blend_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_select_bitmask(k, b.as_i32x16(), a.as_i32x16()))
+ }
+ 
+ /// Blend packed 64-bit integers from a and b using control mask k, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_blend_epi64&expand=438)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq
+ pub unsafe fn _mm512_mask_blend_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_select_bitmask(k, b.as_i64x8(), a.as_i64x8()))
+ }
+ 
+ /// Blend packed single-precision (32-bit) floating-point elements from a and b using control mask k, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_blend_ps&expand=451)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps
+ pub unsafe fn _mm512_mask_blend_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 {
+     transmute(simd_select_bitmask(k, b.as_f32x16(), a.as_f32x16()))
+ }
+ 
+ /// Blend packed double-precision (64-bit) floating-point elements from a and b using control mask k, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_blend_pd&expand=446)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd
+ pub unsafe fn _mm512_mask_blend_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d {
+     transmute(simd_select_bitmask(k, b.as_f64x8(), a.as_f64x8()))
+ }
+ 
+ /// Compute the bitwise AND of packed 32-bit integers in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_and_epi32&expand=272)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))] //should be vpandd, but generate vpandq
+ pub unsafe fn _mm512_and_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_and(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Performs element-by-element bitwise AND between packed 32-bit integer elements of v2 and v3, storing the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_and_epi32&expand=273)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandd))]
+ pub unsafe fn _mm512_mask_and_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let and = _mm512_and_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, and, src.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise AND of packed 32-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_and_epi32&expand=274)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandd))]
+ pub unsafe fn _mm512_maskz_and_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let and = _mm512_and_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, and, zero))
+ }
+ 
+ /// Compute the bitwise AND of 512 bits (composed of packed 64-bit integers) in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_and_epi64&expand=279)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_and_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_and(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise AND of packed 64-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_and_epi64&expand=280)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_mask_and_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let and = _mm512_and_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, and, src.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise AND of packed 32-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_and_Epi32&expand=274)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_maskz_and_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let and = _mm512_and_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, and, zero))
+ }
+ 
+ /// Compute the bitwise AND of 512 bits (representing integer data) in a and b, and store the result in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_and_si512&expand=302)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandq))]
+ pub unsafe fn _mm512_and_si512(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_and(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise OR of packed 32-bit integers in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_or_epi32&expand=4042)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vporq))]
+ pub unsafe fn _mm512_or_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_or(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise OR of packed 32-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_or_epi32&expand=4040)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpord))]
+ pub unsafe fn _mm512_mask_or_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let or = _mm512_or_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, or, src.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise OR of packed 32-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_or_epi32&expand=4041)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpord))]
+ pub unsafe fn _mm512_maskz_or_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let or = _mm512_or_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, or, zero))
+ }
+ 
+ /// Compute the bitwise OR of packed 64-bit integers in a and b, and store the resut in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_or_epi64&expand=4051)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vporq))]
+ pub unsafe fn _mm512_or_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_or(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise OR of packed 64-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_or_epi64&expand=4049)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vporq))]
+ pub unsafe fn _mm512_mask_or_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let or = _mm512_or_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, or, src.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise OR of packed 64-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_or_epi64&expand=4050)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vporq))]
+ pub unsafe fn _mm512_maskz_or_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let or = _mm512_or_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, or, zero))
+ }
+ 
+ /// Compute the bitwise OR of 512 bits (representing integer data) in a and b, and store the result in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_or_si512&expand=4072)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vporq))]
+ pub unsafe fn _mm512_or_si512(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_or(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise XOR of packed 32-bit integers in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_xor_epi32&expand=6142)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxorq))]
+ pub unsafe fn _mm512_xor_epi32(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_xor(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise XOR of packed 32-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_xor_epi32&expand=6140)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxord))]
+ pub unsafe fn _mm512_mask_xor_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let xor = _mm512_xor_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, xor, src.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise XOR of packed 32-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_xor_epi32&expand=6141)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxord))]
+ pub unsafe fn _mm512_maskz_xor_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let xor = _mm512_xor_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, xor, zero))
+ }
+ 
+ /// Compute the bitwise XOR of packed 64-bit integers in a and b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_xor_epi64&expand=6151)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxorq))]
+ pub unsafe fn _mm512_xor_epi64(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_xor(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise XOR of packed 64-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_xor_epi64&expand=6149)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxorq))]
+ pub unsafe fn _mm512_mask_xor_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let xor = _mm512_xor_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, xor, src.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise XOR of packed 64-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_xor_epi64&expand=6150)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxorq))]
+ pub unsafe fn _mm512_maskz_xor_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let xor = _mm512_xor_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, xor, zero))
+ }
+ 
+ /// Compute the bitwise XOR of 512 bits (representing integer data) in a and b, and store the result in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_xor_si512&expand=6172)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpxorq))]
+ pub unsafe fn _mm512_xor_si512(a: __m512i, b: __m512i) -> __m512i {
+     transmute(simd_xor(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise NOT of packed 32-bit integers in a and then AND with b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_andnot_epi32&expand=310)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnq))] //should be vpandnd
+ pub unsafe fn _mm512_andnot_epi32(a: __m512i, b: __m512i) -> __m512i {
+     _mm512_and_epi32(_mm512_xor_epi32(a, _mm512_set1_epi32(u32::MAX as i32)), b)
+ }
+ 
+ /// Compute the bitwise NOT of packed 32-bit integers in a and then AND with b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_andnot_epi32&expand=311)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnd))]
+ pub unsafe fn _mm512_mask_andnot_epi32(
+     src: __m512i,
+     k: __mmask16,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let andnot = _mm512_andnot_epi32(a, b).as_i32x16();
+     transmute(simd_select_bitmask(k, andnot, src.as_i32x16()))
+ }
+ 
+ /// Compute the bitwise NOT of packed 32-bit integers in a and then AND with b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_andnot_epi32&expand=312)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnd))]
+ pub unsafe fn _mm512_maskz_andnot_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
+     let andnot = _mm512_andnot_epi32(a, b).as_i32x16();
+     let zero = _mm512_setzero_si512().as_i32x16();
+     transmute(simd_select_bitmask(k, andnot, zero))
+ }
+ 
+ /// Compute the bitwise NOT of 512 bits (composed of packed 64-bit integers) in a and then AND with b, and store the results in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_andnot_epi64&expand=317)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnq))] //should be vpandnd
+ pub unsafe fn _mm512_andnot_epi64(a: __m512i, b: __m512i) -> __m512i {
+     _mm512_and_epi64(_mm512_xor_epi64(a, _mm512_set1_epi64(u64::MAX as i64)), b)
+ }
+ 
+ /// Compute the bitwise NOT of packed 64-bit integers in a and then AND with b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_andnot_epi64&expand=318)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnq))]
+ pub unsafe fn _mm512_mask_andnot_epi64(
+     src: __m512i,
+     k: __mmask8,
+     a: __m512i,
+     b: __m512i,
+ ) -> __m512i {
+     let andnot = _mm512_andnot_epi64(a, b).as_i64x8();
+     transmute(simd_select_bitmask(k, andnot, src.as_i64x8()))
+ }
+ 
+ /// Compute the bitwise NOT of packed 64-bit integers in a and then AND with b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_andnot_epi64&expand=319)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnq))]
+ pub unsafe fn _mm512_maskz_andnot_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i {
+     let andnot = _mm512_andnot_epi64(a, b).as_i64x8();
+     let zero = _mm512_setzero_si512().as_i64x8();
+     transmute(simd_select_bitmask(k, andnot, zero))
+ }
+ 
+ /// Compute the bitwise NOT of 512 bits (representing integer data) in a and then AND with b, and store the result in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_andnot_si512&expand=340)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpandnq))]
+ pub unsafe fn _mm512_andnot_si512(a: __m512i, b: __m512i) -> __m512i {
+     _mm512_and_epi64(_mm512_xor_epi64(a, _mm512_set1_epi64(u64::MAX as i64)), b)
+ }
+ 
+ /// Compute the bitwise AND of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=kand_mask16&expand=3212)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(and))] // generate normal and code instead of kandw
+ pub unsafe fn _kand_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+     transmute(a & b)
+ }
+ 
+ /// Compute the bitwise AND of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_kand&expand=3210)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(and))] // generate normal and code instead of kandw
+ pub unsafe fn _mm512_kand(a: __mmask16, b: __mmask16) -> __mmask16 {
+     transmute(a & b)
+ }
+ 
+ /// Compute the bitwise OR of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=kor_mask16&expand=3239)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(or))] // generate normal or code instead of korw
+ pub unsafe fn _kor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+     transmute(a | b)
+ }
+ 
+ /// Compute the bitwise OR of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_kor&expand=3237)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(or))] // generate normal or code instead of korw
+ pub unsafe fn _mm512_kor(a: __mmask16, b: __mmask16) -> __mmask16 {
+     transmute(a | b)
+ }
+ 
+ /// Compute the bitwise XOR of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=kxor_mask16&expand=3291)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(xor))] // generate normal xor code instead of kxorw
+ pub unsafe fn _kxor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+     transmute(a ^ b)
+ }
+ 
+ /// Compute the bitwise XOR of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_kxor&expand=3289)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(xor))] // generate normal xor code instead of kxorw
+ pub unsafe fn _mm512_kxor(a: __mmask16, b: __mmask16) -> __mmask16 {
+     transmute(a ^ b)
+ }
+ 
+ /// Compute the bitwise NOT of 16-bit mask a, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=knot_mask16&expand=3233)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _knot_mask16(a: __mmask16) -> __mmask16 {
+     transmute(a ^ 0b11111111_11111111)
+ }
+ 
+ /// Compute the bitwise NOT of 16-bit mask a, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_knot&expand=3231)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_knot(a: __mmask16) -> __mmask16 {
+     transmute(a ^ 0b11111111_11111111)
+ }
+ 
+ /// Compute the bitwise NOT of 16-bit masks a and then AND with b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=kandn_mask16&expand=3218)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(not))] // generate normal and, not code instead of kandnw
+ pub unsafe fn _kandn_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+     _mm512_kand(_mm512_knot(a), b)
+ }
+ 
+ /// Compute the bitwise NOT of 16-bit masks a and then AND with b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_kandn&expand=3216)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(not))] // generate normal and code instead of kandw
+ pub unsafe fn _mm512_kandn(a: __mmask16, b: __mmask16) -> __mmask16 {
+     _mm512_kand(_mm512_knot(a), b)
+ }
+ 
+ /// Compute the bitwise XNOR of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=kxnor_mask16&expand=3285)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(xor))] // generate normal xor, not code instead of kxnorw
+ pub unsafe fn _kxnor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 {
+     _mm512_knot(_mm512_kxor(a, b))
+ }
+ 
+ /// Compute the bitwise XNOR of 16-bit masks a and b, and store the result in k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_kxnor&expand=3283)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(xor))] // generate normal and code instead of kandw
+ pub unsafe fn _mm512_kxnor(a: __mmask16, b: __mmask16) -> __mmask16 {
+     _mm512_knot(_mm512_kxor(a, b))
+ }
+ 
+ /// Copy 16-bit mask a to k.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm512_kmov&expand=3228)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kmovw
+ pub unsafe fn _mm512_kmov(a: __mmask16) -> __mmask16 {
+     let r: u16 = a;
+     transmute(r)
+ }
+ 
+ /// Sets packed 32-bit integers in `dst` with the supplied values.
+ ///
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set_ps(
+     e0: f32,
+     e1: f32,
+     e2: f32,
+     e3: f32,
+     e4: f32,
+     e5: f32,
+     e6: f32,
+     e7: f32,
+     e8: f32,
+     e9: f32,
+     e10: f32,
+     e11: f32,
+     e12: f32,
+     e13: f32,
+     e14: f32,
+     e15: f32,
+ ) -> __m512 {
+     _mm512_setr_ps(
+         e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0,
+     )
+ }
+ 
+ /// Sets packed 32-bit integers in `dst` with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_setr_ps(
+     e0: f32,
+     e1: f32,
+     e2: f32,
+     e3: f32,
+     e4: f32,
+     e5: f32,
+     e6: f32,
+     e7: f32,
+     e8: f32,
+     e9: f32,
+     e10: f32,
+     e11: f32,
+     e12: f32,
+     e13: f32,
+     e14: f32,
+     e15: f32,
+ ) -> __m512 {
+     let r = f32x16::new(
+         e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15,
+     );
+     transmute(r)
+ }
+ 
+ /// Broadcast 64-bit float `a` to all elements of `dst`.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set1_pd(a: f64) -> __m512d {
+     transmute(f64x8::splat(a))
+ }
+ 
+ /// Broadcast 32-bit float `a` to all elements of `dst`.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set1_ps(a: f32) -> __m512 {
+     transmute(f32x16::splat(a))
+ }
+ 
+ /// Sets packed 32-bit integers in `dst` with the supplied values.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set_epi32(
+     e15: i32,
+     e14: i32,
+     e13: i32,
+     e12: i32,
+     e11: i32,
+     e10: i32,
+     e9: i32,
+     e8: i32,
+     e7: i32,
+     e6: i32,
+     e5: i32,
+     e4: i32,
+     e3: i32,
+     e2: i32,
+     e1: i32,
+     e0: i32,
+ ) -> __m512i {
+     _mm512_setr_epi32(
+         e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15,
+     )
+ }
+ 
+ /// Broadcast 32-bit integer `a` to all elements of `dst`.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set1_epi32(a: i32) -> __m512i {
+     transmute(i32x16::splat(a))
+ }
+ 
+ /// Broadcast 64-bit integer `a` to all elements of `dst`.
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set1_epi64(a: i64) -> __m512i {
+     transmute(i64x8::splat(a))
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmplt_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_LT_OS)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmplt_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpnlt_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpnlt_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_NLT_US)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpnlt_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpnlt_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmple_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_LE_OS)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmple_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpnle_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpnle_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_NLE_US)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpnle_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpnle_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for equality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpeq_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_EQ_OQ)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for equality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpeq_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for inequality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpneq_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_NEQ_UQ)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for inequality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpneq_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_cmp_ps_mask(a: __m512, b: __m512, op: i32) -> __mmask16 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmpps(
+                 a.as_f32x16(),
+                 b.as_f32x16(),
+                 $imm5,
+                 neg_one,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmp_ps_mask(m: __mmask16, a: __m512, b: __m512, op: i32) -> __mmask16 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmpps(
+                 a.as_f32x16(),
+                 b.as_f32x16(),
+                 $imm5,
+                 m as i16,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_round_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2, 3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm512_cmp_round_ps_mask(a: __m512, b: __m512, op: i32, sae: i32) -> __mmask16 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmpps(a.as_f32x16(), b.as_f32x16(), $imm5, neg_one, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_round_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3, 4)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm512_mask_cmp_round_ps_mask(
+     m: __mmask16,
+     a: __m512,
+     b: __m512,
+     op: i32,
+     sae: i32,
+ ) -> __mmask16 {
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmpps(a.as_f32x16(), b.as_f32x16(), $imm5, m as i16, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b to see if neither is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpord_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_cmpord_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_ORD_Q)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b to see if neither is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpord_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmpord_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b to see if either is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpunord_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_cmpunord_ps_mask(a: __m512, b: __m512) -> __mmask16 {
+     _mm512_cmp_ps_mask(a, b, _CMP_UNORD_Q)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b to see if either is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpunord_ps_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmpunord_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
+     _mm512_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for less-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmplt_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_LT_OS)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for less-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmplt_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpnlt_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpnlt_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_NLT_US)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpnlt_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpnlt_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for less-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmple_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_LE_OS)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for less-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmple_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpnle_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpnle_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_NLE_US)
+ }
+ 
+ /// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpnle_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpnle_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for equality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpeq_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_EQ_OQ)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for equality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpeq_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for inequality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_cmpneq_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_NEQ_UQ)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b for inequality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp))]
+ pub unsafe fn _mm512_mask_cmpneq_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_cmp_pd_mask(a: __m512d, b: __m512d, op: i32) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmppd(
+                 a.as_f64x8(),
+                 b.as_f64x8(),
+                 $imm5,
+                 neg_one,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmp_pd_mask(m: __mmask8, a: __m512d, b: __m512d, op: i32) -> __mmask8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmppd(
+                 a.as_f64x8(),
+                 b.as_f64x8(),
+                 $imm5,
+                 m as i8,
+                 _MM_FROUND_CUR_DIRECTION,
+             )
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_round_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2, 3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm512_cmp_round_pd_mask(a: __m512d, b: __m512d, op: i32, sae: i32) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmppd(a.as_f64x8(), b.as_f64x8(), $imm5, neg_one, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_round_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3, 4)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm512_mask_cmp_round_pd_mask(
+     m: __mmask8,
+     a: __m512d,
+     b: __m512d,
+     op: i32,
+     sae: i32,
+ ) -> __mmask8 {
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmppd(a.as_f64x8(), b.as_f64x8(), $imm5, m as i8, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b to see if neither is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpord_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_cmpord_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_ORD_Q)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b to see if neither is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpord_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmpord_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b to see if either is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpunord_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_cmpunord_pd_mask(a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_cmp_pd_mask(a, b, _CMP_UNORD_Q)
+ }
+ 
+ /// Compare packed double-precision (64-bit) floating-point elements in a and b to see if either is NaN, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpunord_pd_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmpunord_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 {
+     _mm512_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ss_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_cmp_ss_mask(a: __m128, b: __m128, op: i32) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmpss(a, b, $imm5, neg_one, _MM_FROUND_CUR_DIRECTION)
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector using zeromask m (the element is zeroed out when mask bit 0 is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_ss_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_mask_cmp_ss_mask(m: __mmask8, a: __m128, b: __m128, op: i32) -> __mmask8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmpss(a, b, $imm5, m as i8, _MM_FROUND_CUR_DIRECTION)
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_ss_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2, 3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_cmp_round_ss_mask(a: __m128, b: __m128, op: i32, sae: i32) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmpss(a, b, $imm5, neg_one, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector using zeromask m (the element is zeroed out when mask bit 0 is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_ss_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3, 4)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_mask_cmp_round_ss_mask(
+     m: __mmask8,
+     a: __m128,
+     b: __m128,
+     op: i32,
+     sae: i32,
+ ) -> __mmask8 {
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmpss(a, b, $imm5, m as i8, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_sd_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_cmp_sd_mask(a: __m128d, b: __m128d, op: i32) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmpsd(a, b, $imm5, neg_one, _MM_FROUND_CUR_DIRECTION)
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector using zeromask m (the element is zeroed out when mask bit 0 is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_sd_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_mask_cmp_sd_mask(m: __mmask8, a: __m128d, b: __m128d, op: i32) -> __mmask8 {
+     macro_rules! call {
+         ($imm5:expr) => {
+             vcmpsd(a, b, $imm5, m as i8, _MM_FROUND_CUR_DIRECTION)
+         };
+     }
+     let r = constify_imm5!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_sd_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2, 3)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_cmp_round_sd_mask(a: __m128d, b: __m128d, op: i32, sae: i32) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmpsd(a, b, $imm5, neg_one, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare the lower single-precision (32-bit) floating-point element in a and b based on the comparison operand specified by imm8, and store the result in a mask vector using zeromask m (the element is zeroed out when mask bit 0 is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_sd_mask&expand=5236,755,757)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3, 4)]
+ #[cfg_attr(test, assert_instr(vcmp, op = 0, sae = 4))]
+ pub unsafe fn _mm_mask_cmp_round_sd_mask(
+     m: __mmask8,
+     a: __m128d,
+     b: __m128d,
+     op: i32,
+     sae: i32,
+ ) -> __mmask8 {
+     macro_rules! call {
+         ($imm5:expr, $imm4:expr) => {
+             vcmpsd(a, b, $imm5, m as i8, $imm4)
+         };
+     }
+     let r = constify_imm5_sae!(op, sae, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for less-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmplt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<u32x16, _>(simd_lt(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for less-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmplt_epu32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmplt_epu32_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpgt_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpgt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<u32x16, _>(simd_gt(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpgt_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpgt_epu32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpgt_epu32_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for less-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmple_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<u32x16, _>(simd_le(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for less-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmple_epu32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmple_epu32_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpge_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpge_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<u32x16, _>(simd_ge(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpge_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpge_epu32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpge_epu32_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for equality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpeq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<u32x16, _>(simd_eq(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for equality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpeq_epu32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpeq_epu32_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for inequality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_epu32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpneq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<u32x16, _>(simd_ne(a.as_u32x16(), b.as_u32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for inequality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_epu32_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpneq_epu32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpneq_epu32_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epu32_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_cmp_epu32_mask(a: __m512i, b: __m512i, op: _MM_CMPINT_ENUM) -> __mmask16 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpud(a.as_i32x16(), b.as_i32x16(), $imm3, neg_one)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epu32_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmp_epu32_mask(
+     m: __mmask16,
+     a: __m512i,
+     b: __m512i,
+     op: _MM_CMPINT_ENUM,
+ ) -> __mmask16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpud(a.as_i32x16(), b.as_i32x16(), $imm3, m as i16)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for less-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmplt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<i32x16, _>(simd_lt(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed unsigned 32-bit integers in a and b for less-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmplt_epi32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmplt_epi32_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpgt_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpgt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<i32x16, _>(simd_gt(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpgt_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpgt_epi32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpgt_epi32_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for less-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmple_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<i32x16, _>(simd_le(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for less-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmple_epi32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmple_epi32_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpge_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpge_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<i32x16, _>(simd_ge(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpge_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpge_epi32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpge_epi32_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for equality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpeq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<i32x16, _>(simd_eq(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for equality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpeq_epi32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpeq_epi32_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for inequality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpneq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 {
+     simd_bitmask::<i32x16, _>(simd_ne(a.as_i32x16(), b.as_i32x16()))
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b for inequality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_epi32)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpneq_epi32_mask(m: __mmask16, a: __m512i, b: __m512i) -> __mmask16 {
+     _mm512_cmpneq_epi32_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epi32_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_cmp_epi32_mask(a: __m512i, b: __m512i, op: _MM_CMPINT_ENUM) -> __mmask16 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpd(a.as_i32x16(), b.as_i32x16(), $imm3, neg_one)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed signed 32-bit integers in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epi32_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmp_epi32_mask(
+     m: __mmask16,
+     a: __m512i,
+     b: __m512i,
+     op: _MM_CMPINT_ENUM,
+ ) -> __mmask16 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpd(a.as_i32x16(), b.as_i32x16(), $imm3, m as i16)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for less-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_lt(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for less-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmplt_epu64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmplt_epu64_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpgt_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpgt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_gt(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpgt_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpgt_epu64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpgt_epu64_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for less-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmple_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_le(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for less-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmple_epu64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmple_epu64_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpge_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpge_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_ge(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpge_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpge_epu64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpge_epu64_mask(b, a) & m
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for equality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpeq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_eq(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for equality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpeq_epu64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpeq_epu64_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for inequality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_epu64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpneq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_ne(a.as_u64x8(), b.as_u64x8()))
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b for inequality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_epu64_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpneq_epu64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpneq_epu64_mask(a, b) & m
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epu64_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_cmp_epu64_mask(a: __m512i, b: __m512i, op: _MM_CMPINT_ENUM) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpuq(a.as_i64x8(), b.as_i64x8(), $imm3, neg_one)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed unsigned 64-bit integers in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epu64_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmp_epu64_mask(
+     m: __mmask8,
+     a: __m512i,
+     b: __m512i,
+     op: _MM_CMPINT_ENUM,
+ ) -> __mmask8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpuq(a.as_i64x8(), b.as_i64x8(), $imm3, m as i8)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for less-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmplt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_lt(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for less-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmplt_epi64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmplt_epi64_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for greater-than, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpgt_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpgt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_gt(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for greater-than, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpgt_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpgt_epi64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpgt_epi64_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for less-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmple_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_le(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for less-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmple_epi64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmple_epi64_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpge_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpge_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_ge(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for greater-than-or-equal, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpge_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpge_epi64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpge_epi64_mask(b, a) & m
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for equality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpeq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_eq(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for equality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpeq_epi64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpeq_epi64_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for inequality, and store the results in a mask vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_cmpneq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 {
+     simd_bitmask::<__m512i, _>(simd_ne(a.as_i64x8(), b.as_i64x8()))
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b for inequality, and store the results in a mask vector k
+ /// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vpcmp))]
+ pub unsafe fn _mm512_mask_cmpneq_epi64_mask(m: __mmask8, a: __m512i, b: __m512i) -> __mmask8 {
+     _mm512_cmpneq_epi64_mask(a, b) & m
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b based on the comparison operand specified by op.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epi64_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(2)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_cmp_epi64_mask(a: __m512i, b: __m512i, op: _MM_CMPINT_ENUM) -> __mmask8 {
+     let neg_one = -1;
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpq(a.as_i64x8(), b.as_i64x8(), $imm3, neg_one)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Compare packed signed 64-bit integers in a and b based on the comparison operand specified by op,
+ ///  using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_epi64_mask)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[rustc_args_required_const(3)]
+ #[cfg_attr(test, assert_instr(vpcmp, op = 0))]
+ pub unsafe fn _mm512_mask_cmp_epi64_mask(
+     m: __mmask8,
+     a: __m512i,
+     b: __m512i,
+     op: _MM_CMPINT_ENUM,
+ ) -> __mmask8 {
+     macro_rules! call {
+         ($imm3:expr) => {
+             vpcmpq(a.as_i64x8(), b.as_i64x8(), $imm3, m as i8)
+         };
+     }
+     let r = constify_imm3!(op, call);
+     transmute(r)
+ }
+ 
+ /// Returns vector of type `__m512d` with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ // This intrinsic has no corresponding instruction.
+ pub unsafe fn _mm512_undefined_pd() -> __m512d {
+     _mm512_set1_pd(0.0)
+ }
+ 
+ /// Returns vector of type `__m512` with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ // This intrinsic has no corresponding instruction.
+ pub unsafe fn _mm512_undefined_ps() -> __m512 {
+     _mm512_set1_ps(0.0)
+ }
+ 
+ /// Loads 512-bits (composed of 8 packed double-precision (64-bit)
+ /// floating-point elements) from memory into result.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovups))]
+ pub unsafe fn _mm512_loadu_pd(mem_addr: *const f64) -> __m512d {
+     ptr::read_unaligned(mem_addr as *const __m512d)
+ }
+ 
+ /// Stores 512-bits (composed of 8 packed double-precision (64-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovups))]
+ pub unsafe fn _mm512_storeu_pd(mem_addr: *mut f64, a: __m512d) {
+     ptr::write_unaligned(mem_addr as *mut __m512d, a);
+ }
+ 
+ /// Loads 512-bits (composed of 16 packed single-precision (32-bit)
+ /// floating-point elements) from memory into result.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovups))]
+ pub unsafe fn _mm512_loadu_ps(mem_addr: *const f32) -> __m512 {
+     ptr::read_unaligned(mem_addr as *const __m512)
+ }
+ 
+ /// Stores 512-bits (composed of 16 packed single-precision (32-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_ps)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ #[cfg_attr(test, assert_instr(vmovups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) {
+     ptr::write_unaligned(mem_addr as *mut __m512, a);
+ }
+ 
+ /// Sets packed 64-bit integers in `dst` with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_setr_pd(
+     e0: f64,
+     e1: f64,
+     e2: f64,
+     e3: f64,
+     e4: f64,
+     e5: f64,
+     e6: f64,
+     e7: f64,
+ ) -> __m512d {
+     let r = f64x8::new(e0, e1, e2, e3, e4, e5, e6, e7);
+     transmute(r)
+ }
+ 
+ /// Sets packed 64-bit integers in `dst` with the supplied values.
+ ///
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_pd)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set_pd(
+     e0: f64,
+     e1: f64,
+     e2: f64,
+     e3: f64,
+     e4: f64,
+     e5: f64,
+     e6: f64,
+     e7: f64,
+ ) -> __m512d {
+     _mm512_setr_pd(e7, e6, e5, e4, e3, e2, e1, e0)
+ }
+ 
+ /// Equal
+ pub const _MM_CMPINT_EQ: _MM_CMPINT_ENUM = 0x00;
+ /// Less-than
+ pub const _MM_CMPINT_LT: _MM_CMPINT_ENUM = 0x01;
+ /// Less-than-or-equal
+ pub const _MM_CMPINT_LE: _MM_CMPINT_ENUM = 0x02;
+ /// False
+ pub const _MM_CMPINT_FALSE: _MM_CMPINT_ENUM = 0x03;
+ /// Not-equal
+ pub const _MM_CMPINT_NE: _MM_CMPINT_ENUM = 0x04;
+ /// Not less-than
+ pub const _MM_CMPINT_NLT: _MM_CMPINT_ENUM = 0x05;
+ /// Not less-than-or-equal
+ pub const _MM_CMPINT_NLE: _MM_CMPINT_ENUM = 0x06;
+ /// True
+ pub const _MM_CMPINT_TRUE: _MM_CMPINT_ENUM = 0x07;
+ 
+ /// interval [1, 2)
+ pub const _MM_MANT_NORM_1_2: _MM_MANTISSA_NORM_ENUM = 0x00;
+ /// interval [0.5, 2)
+ pub const _MM_MANT_NORM_P5_2: _MM_MANTISSA_NORM_ENUM = 0x01;
+ /// interval [0.5, 1)
+ pub const _MM_MANT_NORM_P5_1: _MM_MANTISSA_NORM_ENUM = 0x02;
+ /// interval [0.75, 1.5)
+ pub const _MM_MANT_NORM_P75_1P5: _MM_MANTISSA_NORM_ENUM = 0x03;
+ 
+ /// sign = sign(SRC)
+ pub const _MM_MANT_SIGN_SRC: _MM_MANTISSA_SIGN_ENUM = 0x00;
+ /// sign = 0
+ pub const _MM_MANT_SIGN_ZERO: _MM_MANTISSA_SIGN_ENUM = 0x01;
+ /// DEST = NaN if sign(SRC) = 1
+ pub const _MM_MANT_SIGN_NAN: _MM_MANTISSA_SIGN_ENUM = 0x02;
+ 
+ pub const _MM_PERM_AAAA: _MM_PERM_ENUM = 0x00;
+ pub const _MM_PERM_AAAB: _MM_PERM_ENUM = 0x01;
+ pub const _MM_PERM_AAAC: _MM_PERM_ENUM = 0x02;
+ pub const _MM_PERM_AAAD: _MM_PERM_ENUM = 0x03;
+ pub const _MM_PERM_AABA: _MM_PERM_ENUM = 0x04;
+ pub const _MM_PERM_AABB: _MM_PERM_ENUM = 0x05;
+ pub const _MM_PERM_AABC: _MM_PERM_ENUM = 0x06;
+ pub const _MM_PERM_AABD: _MM_PERM_ENUM = 0x07;
+ pub const _MM_PERM_AACA: _MM_PERM_ENUM = 0x08;
+ pub const _MM_PERM_AACB: _MM_PERM_ENUM = 0x09;
+ pub const _MM_PERM_AACC: _MM_PERM_ENUM = 0x0A;
+ pub const _MM_PERM_AACD: _MM_PERM_ENUM = 0x0B;
+ pub const _MM_PERM_AADA: _MM_PERM_ENUM = 0x0C;
+ pub const _MM_PERM_AADB: _MM_PERM_ENUM = 0x0D;
+ pub const _MM_PERM_AADC: _MM_PERM_ENUM = 0x0E;
+ pub const _MM_PERM_AADD: _MM_PERM_ENUM = 0x0F;
+ pub const _MM_PERM_ABAA: _MM_PERM_ENUM = 0x10;
+ pub const _MM_PERM_ABAB: _MM_PERM_ENUM = 0x11;
+ pub const _MM_PERM_ABAC: _MM_PERM_ENUM = 0x12;
+ pub const _MM_PERM_ABAD: _MM_PERM_ENUM = 0x13;
+ pub const _MM_PERM_ABBA: _MM_PERM_ENUM = 0x14;
+ pub const _MM_PERM_ABBB: _MM_PERM_ENUM = 0x15;
+ pub const _MM_PERM_ABBC: _MM_PERM_ENUM = 0x16;
+ pub const _MM_PERM_ABBD: _MM_PERM_ENUM = 0x17;
+ pub const _MM_PERM_ABCA: _MM_PERM_ENUM = 0x18;
+ pub const _MM_PERM_ABCB: _MM_PERM_ENUM = 0x19;
+ pub const _MM_PERM_ABCC: _MM_PERM_ENUM = 0x1A;
+ pub const _MM_PERM_ABCD: _MM_PERM_ENUM = 0x1B;
+ pub const _MM_PERM_ABDA: _MM_PERM_ENUM = 0x1C;
+ pub const _MM_PERM_ABDB: _MM_PERM_ENUM = 0x1D;
+ pub const _MM_PERM_ABDC: _MM_PERM_ENUM = 0x1E;
+ pub const _MM_PERM_ABDD: _MM_PERM_ENUM = 0x1F;
+ pub const _MM_PERM_ACAA: _MM_PERM_ENUM = 0x20;
+ pub const _MM_PERM_ACAB: _MM_PERM_ENUM = 0x21;
+ pub const _MM_PERM_ACAC: _MM_PERM_ENUM = 0x22;
+ pub const _MM_PERM_ACAD: _MM_PERM_ENUM = 0x23;
+ pub const _MM_PERM_ACBA: _MM_PERM_ENUM = 0x24;
+ pub const _MM_PERM_ACBB: _MM_PERM_ENUM = 0x25;
+ pub const _MM_PERM_ACBC: _MM_PERM_ENUM = 0x26;
+ pub const _MM_PERM_ACBD: _MM_PERM_ENUM = 0x27;
+ pub const _MM_PERM_ACCA: _MM_PERM_ENUM = 0x28;
+ pub const _MM_PERM_ACCB: _MM_PERM_ENUM = 0x29;
+ pub const _MM_PERM_ACCC: _MM_PERM_ENUM = 0x2A;
+ pub const _MM_PERM_ACCD: _MM_PERM_ENUM = 0x2B;
+ pub const _MM_PERM_ACDA: _MM_PERM_ENUM = 0x2C;
+ pub const _MM_PERM_ACDB: _MM_PERM_ENUM = 0x2D;
+ pub const _MM_PERM_ACDC: _MM_PERM_ENUM = 0x2E;
+ pub const _MM_PERM_ACDD: _MM_PERM_ENUM = 0x2F;
+ pub const _MM_PERM_ADAA: _MM_PERM_ENUM = 0x30;
+ pub const _MM_PERM_ADAB: _MM_PERM_ENUM = 0x31;
+ pub const _MM_PERM_ADAC: _MM_PERM_ENUM = 0x32;
+ pub const _MM_PERM_ADAD: _MM_PERM_ENUM = 0x33;
+ pub const _MM_PERM_ADBA: _MM_PERM_ENUM = 0x34;
+ pub const _MM_PERM_ADBB: _MM_PERM_ENUM = 0x35;
+ pub const _MM_PERM_ADBC: _MM_PERM_ENUM = 0x36;
+ pub const _MM_PERM_ADBD: _MM_PERM_ENUM = 0x37;
+ pub const _MM_PERM_ADCA: _MM_PERM_ENUM = 0x38;
+ pub const _MM_PERM_ADCB: _MM_PERM_ENUM = 0x39;
+ pub const _MM_PERM_ADCC: _MM_PERM_ENUM = 0x3A;
+ pub const _MM_PERM_ADCD: _MM_PERM_ENUM = 0x3B;
+ pub const _MM_PERM_ADDA: _MM_PERM_ENUM = 0x3C;
+ pub const _MM_PERM_ADDB: _MM_PERM_ENUM = 0x3D;
+ pub const _MM_PERM_ADDC: _MM_PERM_ENUM = 0x3E;
+ pub const _MM_PERM_ADDD: _MM_PERM_ENUM = 0x3F;
+ pub const _MM_PERM_BAAA: _MM_PERM_ENUM = 0x40;
+ pub const _MM_PERM_BAAB: _MM_PERM_ENUM = 0x41;
+ pub const _MM_PERM_BAAC: _MM_PERM_ENUM = 0x42;
+ pub const _MM_PERM_BAAD: _MM_PERM_ENUM = 0x43;
+ pub const _MM_PERM_BABA: _MM_PERM_ENUM = 0x44;
+ pub const _MM_PERM_BABB: _MM_PERM_ENUM = 0x45;
+ pub const _MM_PERM_BABC: _MM_PERM_ENUM = 0x46;
+ pub const _MM_PERM_BABD: _MM_PERM_ENUM = 0x47;
+ pub const _MM_PERM_BACA: _MM_PERM_ENUM = 0x48;
+ pub const _MM_PERM_BACB: _MM_PERM_ENUM = 0x49;
+ pub const _MM_PERM_BACC: _MM_PERM_ENUM = 0x4A;
+ pub const _MM_PERM_BACD: _MM_PERM_ENUM = 0x4B;
+ pub const _MM_PERM_BADA: _MM_PERM_ENUM = 0x4C;
+ pub const _MM_PERM_BADB: _MM_PERM_ENUM = 0x4D;
+ pub const _MM_PERM_BADC: _MM_PERM_ENUM = 0x4E;
+ pub const _MM_PERM_BADD: _MM_PERM_ENUM = 0x4F;
+ pub const _MM_PERM_BBAA: _MM_PERM_ENUM = 0x50;
+ pub const _MM_PERM_BBAB: _MM_PERM_ENUM = 0x51;
+ pub const _MM_PERM_BBAC: _MM_PERM_ENUM = 0x52;
+ pub const _MM_PERM_BBAD: _MM_PERM_ENUM = 0x53;
+ pub const _MM_PERM_BBBA: _MM_PERM_ENUM = 0x54;
+ pub const _MM_PERM_BBBB: _MM_PERM_ENUM = 0x55;
+ pub const _MM_PERM_BBBC: _MM_PERM_ENUM = 0x56;
+ pub const _MM_PERM_BBBD: _MM_PERM_ENUM = 0x57;
+ pub const _MM_PERM_BBCA: _MM_PERM_ENUM = 0x58;
+ pub const _MM_PERM_BBCB: _MM_PERM_ENUM = 0x59;
+ pub const _MM_PERM_BBCC: _MM_PERM_ENUM = 0x5A;
+ pub const _MM_PERM_BBCD: _MM_PERM_ENUM = 0x5B;
+ pub const _MM_PERM_BBDA: _MM_PERM_ENUM = 0x5C;
+ pub const _MM_PERM_BBDB: _MM_PERM_ENUM = 0x5D;
+ pub const _MM_PERM_BBDC: _MM_PERM_ENUM = 0x5E;
+ pub const _MM_PERM_BBDD: _MM_PERM_ENUM = 0x5F;
+ pub const _MM_PERM_BCAA: _MM_PERM_ENUM = 0x60;
+ pub const _MM_PERM_BCAB: _MM_PERM_ENUM = 0x61;
+ pub const _MM_PERM_BCAC: _MM_PERM_ENUM = 0x62;
+ pub const _MM_PERM_BCAD: _MM_PERM_ENUM = 0x63;
+ pub const _MM_PERM_BCBA: _MM_PERM_ENUM = 0x64;
+ pub const _MM_PERM_BCBB: _MM_PERM_ENUM = 0x65;
+ pub const _MM_PERM_BCBC: _MM_PERM_ENUM = 0x66;
+ pub const _MM_PERM_BCBD: _MM_PERM_ENUM = 0x67;
+ pub const _MM_PERM_BCCA: _MM_PERM_ENUM = 0x68;
+ pub const _MM_PERM_BCCB: _MM_PERM_ENUM = 0x69;
+ pub const _MM_PERM_BCCC: _MM_PERM_ENUM = 0x6A;
+ pub const _MM_PERM_BCCD: _MM_PERM_ENUM = 0x6B;
+ pub const _MM_PERM_BCDA: _MM_PERM_ENUM = 0x6C;
+ pub const _MM_PERM_BCDB: _MM_PERM_ENUM = 0x6D;
+ pub const _MM_PERM_BCDC: _MM_PERM_ENUM = 0x6E;
+ pub const _MM_PERM_BCDD: _MM_PERM_ENUM = 0x6F;
+ pub const _MM_PERM_BDAA: _MM_PERM_ENUM = 0x70;
+ pub const _MM_PERM_BDAB: _MM_PERM_ENUM = 0x71;
+ pub const _MM_PERM_BDAC: _MM_PERM_ENUM = 0x72;
+ pub const _MM_PERM_BDAD: _MM_PERM_ENUM = 0x73;
+ pub const _MM_PERM_BDBA: _MM_PERM_ENUM = 0x74;
+ pub const _MM_PERM_BDBB: _MM_PERM_ENUM = 0x75;
+ pub const _MM_PERM_BDBC: _MM_PERM_ENUM = 0x76;
+ pub const _MM_PERM_BDBD: _MM_PERM_ENUM = 0x77;
+ pub const _MM_PERM_BDCA: _MM_PERM_ENUM = 0x78;
+ pub const _MM_PERM_BDCB: _MM_PERM_ENUM = 0x79;
+ pub const _MM_PERM_BDCC: _MM_PERM_ENUM = 0x7A;
+ pub const _MM_PERM_BDCD: _MM_PERM_ENUM = 0x7B;
+ pub const _MM_PERM_BDDA: _MM_PERM_ENUM = 0x7C;
+ pub const _MM_PERM_BDDB: _MM_PERM_ENUM = 0x7D;
+ pub const _MM_PERM_BDDC: _MM_PERM_ENUM = 0x7E;
+ pub const _MM_PERM_BDDD: _MM_PERM_ENUM = 0x7F;
+ pub const _MM_PERM_CAAA: _MM_PERM_ENUM = 0x80;
+ pub const _MM_PERM_CAAB: _MM_PERM_ENUM = 0x81;
+ pub const _MM_PERM_CAAC: _MM_PERM_ENUM = 0x82;
+ pub const _MM_PERM_CAAD: _MM_PERM_ENUM = 0x83;
+ pub const _MM_PERM_CABA: _MM_PERM_ENUM = 0x84;
+ pub const _MM_PERM_CABB: _MM_PERM_ENUM = 0x85;
+ pub const _MM_PERM_CABC: _MM_PERM_ENUM = 0x86;
+ pub const _MM_PERM_CABD: _MM_PERM_ENUM = 0x87;
+ pub const _MM_PERM_CACA: _MM_PERM_ENUM = 0x88;
+ pub const _MM_PERM_CACB: _MM_PERM_ENUM = 0x89;
+ pub const _MM_PERM_CACC: _MM_PERM_ENUM = 0x8A;
+ pub const _MM_PERM_CACD: _MM_PERM_ENUM = 0x8B;
+ pub const _MM_PERM_CADA: _MM_PERM_ENUM = 0x8C;
+ pub const _MM_PERM_CADB: _MM_PERM_ENUM = 0x8D;
+ pub const _MM_PERM_CADC: _MM_PERM_ENUM = 0x8E;
+ pub const _MM_PERM_CADD: _MM_PERM_ENUM = 0x8F;
+ pub const _MM_PERM_CBAA: _MM_PERM_ENUM = 0x90;
+ pub const _MM_PERM_CBAB: _MM_PERM_ENUM = 0x91;
+ pub const _MM_PERM_CBAC: _MM_PERM_ENUM = 0x92;
+ pub const _MM_PERM_CBAD: _MM_PERM_ENUM = 0x93;
+ pub const _MM_PERM_CBBA: _MM_PERM_ENUM = 0x94;
+ pub const _MM_PERM_CBBB: _MM_PERM_ENUM = 0x95;
+ pub const _MM_PERM_CBBC: _MM_PERM_ENUM = 0x96;
+ pub const _MM_PERM_CBBD: _MM_PERM_ENUM = 0x97;
+ pub const _MM_PERM_CBCA: _MM_PERM_ENUM = 0x98;
+ pub const _MM_PERM_CBCB: _MM_PERM_ENUM = 0x99;
+ pub const _MM_PERM_CBCC: _MM_PERM_ENUM = 0x9A;
+ pub const _MM_PERM_CBCD: _MM_PERM_ENUM = 0x9B;
+ pub const _MM_PERM_CBDA: _MM_PERM_ENUM = 0x9C;
+ pub const _MM_PERM_CBDB: _MM_PERM_ENUM = 0x9D;
+ pub const _MM_PERM_CBDC: _MM_PERM_ENUM = 0x9E;
+ pub const _MM_PERM_CBDD: _MM_PERM_ENUM = 0x9F;
+ pub const _MM_PERM_CCAA: _MM_PERM_ENUM = 0xA0;
+ pub const _MM_PERM_CCAB: _MM_PERM_ENUM = 0xA1;
+ pub const _MM_PERM_CCAC: _MM_PERM_ENUM = 0xA2;
+ pub const _MM_PERM_CCAD: _MM_PERM_ENUM = 0xA3;
+ pub const _MM_PERM_CCBA: _MM_PERM_ENUM = 0xA4;
+ pub const _MM_PERM_CCBB: _MM_PERM_ENUM = 0xA5;
+ pub const _MM_PERM_CCBC: _MM_PERM_ENUM = 0xA6;
+ pub const _MM_PERM_CCBD: _MM_PERM_ENUM = 0xA7;
+ pub const _MM_PERM_CCCA: _MM_PERM_ENUM = 0xA8;
+ pub const _MM_PERM_CCCB: _MM_PERM_ENUM = 0xA9;
+ pub const _MM_PERM_CCCC: _MM_PERM_ENUM = 0xAA;
+ pub const _MM_PERM_CCCD: _MM_PERM_ENUM = 0xAB;
+ pub const _MM_PERM_CCDA: _MM_PERM_ENUM = 0xAC;
+ pub const _MM_PERM_CCDB: _MM_PERM_ENUM = 0xAD;
+ pub const _MM_PERM_CCDC: _MM_PERM_ENUM = 0xAE;
+ pub const _MM_PERM_CCDD: _MM_PERM_ENUM = 0xAF;
+ pub const _MM_PERM_CDAA: _MM_PERM_ENUM = 0xB0;
+ pub const _MM_PERM_CDAB: _MM_PERM_ENUM = 0xB1;
+ pub const _MM_PERM_CDAC: _MM_PERM_ENUM = 0xB2;
+ pub const _MM_PERM_CDAD: _MM_PERM_ENUM = 0xB3;
+ pub const _MM_PERM_CDBA: _MM_PERM_ENUM = 0xB4;
+ pub const _MM_PERM_CDBB: _MM_PERM_ENUM = 0xB5;
+ pub const _MM_PERM_CDBC: _MM_PERM_ENUM = 0xB6;
+ pub const _MM_PERM_CDBD: _MM_PERM_ENUM = 0xB7;
+ pub const _MM_PERM_CDCA: _MM_PERM_ENUM = 0xB8;
+ pub const _MM_PERM_CDCB: _MM_PERM_ENUM = 0xB9;
+ pub const _MM_PERM_CDCC: _MM_PERM_ENUM = 0xBA;
+ pub const _MM_PERM_CDCD: _MM_PERM_ENUM = 0xBB;
+ pub const _MM_PERM_CDDA: _MM_PERM_ENUM = 0xBC;
+ pub const _MM_PERM_CDDB: _MM_PERM_ENUM = 0xBD;
+ pub const _MM_PERM_CDDC: _MM_PERM_ENUM = 0xBE;
+ pub const _MM_PERM_CDDD: _MM_PERM_ENUM = 0xBF;
+ pub const _MM_PERM_DAAA: _MM_PERM_ENUM = 0xC0;
+ pub const _MM_PERM_DAAB: _MM_PERM_ENUM = 0xC1;
+ pub const _MM_PERM_DAAC: _MM_PERM_ENUM = 0xC2;
+ pub const _MM_PERM_DAAD: _MM_PERM_ENUM = 0xC3;
+ pub const _MM_PERM_DABA: _MM_PERM_ENUM = 0xC4;
+ pub const _MM_PERM_DABB: _MM_PERM_ENUM = 0xC5;
+ pub const _MM_PERM_DABC: _MM_PERM_ENUM = 0xC6;
+ pub const _MM_PERM_DABD: _MM_PERM_ENUM = 0xC7;
+ pub const _MM_PERM_DACA: _MM_PERM_ENUM = 0xC8;
+ pub const _MM_PERM_DACB: _MM_PERM_ENUM = 0xC9;
+ pub const _MM_PERM_DACC: _MM_PERM_ENUM = 0xCA;
+ pub const _MM_PERM_DACD: _MM_PERM_ENUM = 0xCB;
+ pub const _MM_PERM_DADA: _MM_PERM_ENUM = 0xCC;
+ pub const _MM_PERM_DADB: _MM_PERM_ENUM = 0xCD;
+ pub const _MM_PERM_DADC: _MM_PERM_ENUM = 0xCE;
+ pub const _MM_PERM_DADD: _MM_PERM_ENUM = 0xCF;
+ pub const _MM_PERM_DBAA: _MM_PERM_ENUM = 0xD0;
+ pub const _MM_PERM_DBAB: _MM_PERM_ENUM = 0xD1;
+ pub const _MM_PERM_DBAC: _MM_PERM_ENUM = 0xD2;
+ pub const _MM_PERM_DBAD: _MM_PERM_ENUM = 0xD3;
+ pub const _MM_PERM_DBBA: _MM_PERM_ENUM = 0xD4;
+ pub const _MM_PERM_DBBB: _MM_PERM_ENUM = 0xD5;
+ pub const _MM_PERM_DBBC: _MM_PERM_ENUM = 0xD6;
+ pub const _MM_PERM_DBBD: _MM_PERM_ENUM = 0xD7;
+ pub const _MM_PERM_DBCA: _MM_PERM_ENUM = 0xD8;
+ pub const _MM_PERM_DBCB: _MM_PERM_ENUM = 0xD9;
+ pub const _MM_PERM_DBCC: _MM_PERM_ENUM = 0xDA;
+ pub const _MM_PERM_DBCD: _MM_PERM_ENUM = 0xDB;
+ pub const _MM_PERM_DBDA: _MM_PERM_ENUM = 0xDC;
+ pub const _MM_PERM_DBDB: _MM_PERM_ENUM = 0xDD;
+ pub const _MM_PERM_DBDC: _MM_PERM_ENUM = 0xDE;
+ pub const _MM_PERM_DBDD: _MM_PERM_ENUM = 0xDF;
+ pub const _MM_PERM_DCAA: _MM_PERM_ENUM = 0xE0;
+ pub const _MM_PERM_DCAB: _MM_PERM_ENUM = 0xE1;
+ pub const _MM_PERM_DCAC: _MM_PERM_ENUM = 0xE2;
+ pub const _MM_PERM_DCAD: _MM_PERM_ENUM = 0xE3;
+ pub const _MM_PERM_DCBA: _MM_PERM_ENUM = 0xE4;
+ pub const _MM_PERM_DCBB: _MM_PERM_ENUM = 0xE5;
+ pub const _MM_PERM_DCBC: _MM_PERM_ENUM = 0xE6;
+ pub const _MM_PERM_DCBD: _MM_PERM_ENUM = 0xE7;
+ pub const _MM_PERM_DCCA: _MM_PERM_ENUM = 0xE8;
+ pub const _MM_PERM_DCCB: _MM_PERM_ENUM = 0xE9;
+ pub const _MM_PERM_DCCC: _MM_PERM_ENUM = 0xEA;
+ pub const _MM_PERM_DCCD: _MM_PERM_ENUM = 0xEB;
+ pub const _MM_PERM_DCDA: _MM_PERM_ENUM = 0xEC;
+ pub const _MM_PERM_DCDB: _MM_PERM_ENUM = 0xED;
+ pub const _MM_PERM_DCDC: _MM_PERM_ENUM = 0xEE;
+ pub const _MM_PERM_DCDD: _MM_PERM_ENUM = 0xEF;
+ pub const _MM_PERM_DDAA: _MM_PERM_ENUM = 0xF0;
+ pub const _MM_PERM_DDAB: _MM_PERM_ENUM = 0xF1;
+ pub const _MM_PERM_DDAC: _MM_PERM_ENUM = 0xF2;
+ pub const _MM_PERM_DDAD: _MM_PERM_ENUM = 0xF3;
+ pub const _MM_PERM_DDBA: _MM_PERM_ENUM = 0xF4;
+ pub const _MM_PERM_DDBB: _MM_PERM_ENUM = 0xF5;
+ pub const _MM_PERM_DDBC: _MM_PERM_ENUM = 0xF6;
+ pub const _MM_PERM_DDBD: _MM_PERM_ENUM = 0xF7;
+ pub const _MM_PERM_DDCA: _MM_PERM_ENUM = 0xF8;
+ pub const _MM_PERM_DDCB: _MM_PERM_ENUM = 0xF9;
+ pub const _MM_PERM_DDCC: _MM_PERM_ENUM = 0xFA;
+ pub const _MM_PERM_DDCD: _MM_PERM_ENUM = 0xFB;
+ pub const _MM_PERM_DDDA: _MM_PERM_ENUM = 0xFC;
+ pub const _MM_PERM_DDDB: _MM_PERM_ENUM = 0xFD;
+ pub const _MM_PERM_DDDC: _MM_PERM_ENUM = 0xFE;
+ pub const _MM_PERM_DDDD: _MM_PERM_ENUM = 0xFF;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.avx512.pmul.dq.512"]
+     fn vpmuldq(a: i32x16, b: i32x16) -> i64x8;
+     #[link_name = "llvm.x86.avx512.pmulu.dq.512"]
+     fn vpmuludq(a: u32x16, b: u32x16) -> u64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.pmaxs.d.512"]
+     fn vpmaxsd(a: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.pmaxs.q.512"]
+     fn vpmaxsq(a: i64x8, b: i64x8) -> i64x8;
+     #[link_name = "llvm.x86.avx512.mask.pmins.d.512"]
+     fn vpminsd(a: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.pmins.q.512"]
+     fn vpminsq(a: i64x8, b: i64x8) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.pmaxu.d.512"]
+     fn vpmaxud(a: u32x16, b: u32x16) -> u32x16;
+     #[link_name = "llvm.x86.avx512.mask.pmaxu.q.512"]
+     fn vpmaxuq(a: u64x8, b: u64x8) -> i64x8;
+     #[link_name = "llvm.x86.avx512.mask.pminu.d.512"]
+     fn vpminud(a: u32x16, b: u32x16) -> u32x16;
+     #[link_name = "llvm.x86.avx512.mask.pminu.q.512"]
+     fn vpminuq(a: u64x8, b: u64x8) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.sqrt.ps.512"]
+     fn vsqrtps(a: f32x16, rounding: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.sqrt.pd.512"]
+     fn vsqrtpd(a: f64x8, rounding: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.vfmadd.ps.512"]
+     fn vfmadd132ps(a: f32x16, b: f32x16, c: f32x16, rounding: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.vfmadd.pd.512"]
+     fn vfmadd132pd(a: f64x8, b: f64x8, c: f64x8, rounding: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.vfmaddsub.ps.512"]
+     fn vfmaddsub213ps(a: f32x16, b: f32x16, c: f32x16, d: i32) -> f32x16; //from clang
+     #[link_name = "llvm.x86.avx512.vfmaddsub.pd.512"]
+     fn vfmaddsub213pd(a: f64x8, b: f64x8, c: f64x8, d: i32) -> f64x8; //from clang
+ 
+     #[link_name = "llvm.x86.avx512.add.ps.512"]
+     fn vaddps(a: f32x16, b: f32x16, rounding: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.add.pd.512"]
+     fn vaddpd(a: f64x8, b: f64x8, rounding: i32) -> f64x8;
+     #[link_name = "llvm.x86.avx512.sub.ps.512"]
+     fn vsubps(a: f32x16, b: f32x16, rounding: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.sub.pd.512"]
+     fn vsubpd(a: f64x8, b: f64x8, rounding: i32) -> f64x8;
+     #[link_name = "llvm.x86.avx512.mul.ps.512"]
+     fn vmulps(a: f32x16, b: f32x16, rounding: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.mul.pd.512"]
+     fn vmulpd(a: f64x8, b: f64x8, rounding: i32) -> f64x8;
+     #[link_name = "llvm.x86.avx512.div.ps.512"]
+     fn vdivps(a: f32x16, b: f32x16, rounding: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.div.pd.512"]
+     fn vdivpd(a: f64x8, b: f64x8, rounding: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.max.ps.512"]
+     fn vmaxps(a: f32x16, b: f32x16, sae: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.max.pd.512"]
+     fn vmaxpd(a: f64x8, b: f64x8, sae: i32) -> f64x8;
+     #[link_name = "llvm.x86.avx512.min.ps.512"]
+     fn vminps(a: f32x16, b: f32x16, sae: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.min.pd.512"]
+     fn vminpd(a: f64x8, b: f64x8, sae: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.getexp.ps.512"]
+     fn vgetexpps(a: f32x16, src: f32x16, m: u16, sae: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.mask.getexp.pd.512"]
+     fn vgetexppd(a: f64x8, src: f64x8, m: u8, sae: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.getmant.ps.512"]
+     fn vgetmantps(a: f32x16, mantissas: i32, src: f32x16, m: u16, sae: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.mask.getmant.pd.512"]
+     fn vgetmantpd(a: f64x8, mantissas: i32, src: f64x8, m: u8, sae: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.rcp14.ps.512"]
+     fn vrcp14ps(a: f32x16, src: f32x16, m: u16) -> f32x16;
+     #[link_name = "llvm.x86.avx512.rcp14.pd.512"]
+     fn vrcp14pd(a: f64x8, src: f64x8, m: u8) -> f64x8;
+     #[link_name = "llvm.x86.avx512.rsqrt14.ps.512"]
+     fn vrsqrt14ps(a: f32x16, src: f32x16, m: u16) -> f32x16;
+     #[link_name = "llvm.x86.avx512.rsqrt14.pd.512"]
+     fn vrsqrt14pd(a: f64x8, src: f64x8, m: u8) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.cvtps2dq.512"]
+     fn vcvtps2dq(a: f32x16, src: i32x16, mask: u16, rounding: i32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.cvtps2udq.512"]
+     fn vcvtps2udq(a: f32x16, src: u32x16, mask: u16, rounding: i32) -> u32x16;
+     #[link_name = "llvm.x86.avx512.mask.cvtps2pd.512"]
+     fn vcvtps2pd(a: f32x8, src: f64x8, mask: u8, sae: i32) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.cvttps2dq.512"]
+     fn vcvttps2dq(a: f32x16, src: i32x16, mask: u16, rounding: i32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.cvttps2udq.512"]
+     fn vcvttps2udq(a: f32x16, src: i32x16, mask: u16, rounding: i32) -> u32x16;
+     #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.512"]
+     fn vcvttpd2dq(a: f64x8, src: i32x8, mask: u8, rounding: i32) -> i32x8;
+     #[link_name = "llvm.x86.avx512.mask.cvttpd2udq.512"]
+     fn vcvttpd2udq(a: f64x8, src: i32x8, mask: u8, rounding: i32) -> u32x8;
+ 
+     #[link_name = "llvm.x86.avx512.gather.dpd.512"]
+     fn vgatherdpd(src: f64x8, slice: *const i8, offsets: i32x8, mask: i8, scale: i32) -> f64x8;
+     #[link_name = "llvm.x86.avx512.gather.dps.512"]
+     fn vgatherdps(src: f32x16, slice: *const i8, offsets: i32x16, mask: i16, scale: i32) -> f32x16;
+     #[link_name = "llvm.x86.avx512.gather.qpd.512"]
+     fn vgatherqpd(src: f64x8, slice: *const i8, offsets: i64x8, mask: i8, scale: i32) -> f64x8;
+     #[link_name = "llvm.x86.avx512.gather.qps.512"]
+     fn vgatherqps(src: f32x8, slice: *const i8, offsets: i64x8, mask: i8, scale: i32) -> f32x8;
+     #[link_name = "llvm.x86.avx512.gather.dpq.512"]
+     fn vpgatherdq(src: i64x8, slice: *const i8, offsets: i32x8, mask: i8, scale: i32) -> i64x8;
+     #[link_name = "llvm.x86.avx512.gather.dpi.512"]
+     fn vpgatherdd(src: i32x16, slice: *const i8, offsets: i32x16, mask: i16, scale: i32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.gather.qpq.512"]
+     fn vpgatherqq(src: i64x8, slice: *const i8, offsets: i64x8, mask: i8, scale: i32) -> i64x8;
+     #[link_name = "llvm.x86.avx512.gather.qpi.512"]
+     fn vpgatherqd(src: i32x8, slice: *const i8, offsets: i64x8, mask: i8, scale: i32) -> i32x8;
+ 
+     #[link_name = "llvm.x86.avx512.scatter.dpd.512"]
+     fn vscatterdpd(slice: *mut i8, mask: i8, offsets: i32x8, src: f64x8, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.dps.512"]
+     fn vscatterdps(slice: *mut i8, mask: i16, offsets: i32x16, src: f32x16, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.qpd.512"]
+     fn vscatterqpd(slice: *mut i8, mask: i8, offsets: i64x8, src: f64x8, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.qps.512"]
+     fn vscatterqps(slice: *mut i8, mask: i8, offsets: i64x8, src: f32x8, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.dpq.512"]
+     fn vpscatterdq(slice: *mut i8, mask: i8, offsets: i32x8, src: i64x8, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.dpi.512"]
+     fn vpscatterdd(slice: *mut i8, mask: i16, offsets: i32x16, src: i32x16, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.qpq.512"]
+     fn vpscatterqq(slice: *mut i8, mask: i8, offsets: i64x8, src: i64x8, scale: i32);
+     #[link_name = "llvm.x86.avx512.scatter.qpi.512"]
+     fn vpscatterqd(slice: *mut i8, mask: i8, offsets: i64x8, src: i32x8, scale: i32);
+ 
+     #[link_name = "llvm.x86.avx512.mask.cmp.ss"]
+     fn vcmpss(a: __m128, b: __m128, op: i32, m: i8, sae: i32) -> i8;
+     #[link_name = "llvm.x86.avx512.mask.cmp.sd"]
+     fn vcmpsd(a: __m128d, b: __m128d, op: i32, m: i8, sae: i32) -> i8;
+     #[link_name = "llvm.x86.avx512.mask.cmp.ps.512"]
+     fn vcmpps(a: f32x16, b: f32x16, op: i32, m: i16, sae: i32) -> i16;
+     #[link_name = "llvm.x86.avx512.mask.cmp.pd.512"]
+     fn vcmppd(a: f64x8, b: f64x8, op: i32, m: i8, sae: i32) -> i8;
+     #[link_name = "llvm.x86.avx512.mask.ucmp.q.512"]
+     fn vpcmpuq(a: i64x8, b: i64x8, op: i32, m: i8) -> i8;
+     #[link_name = "llvm.x86.avx512.mask.cmp.q.512"]
+     fn vpcmpq(a: i64x8, b: i64x8, op: i32, m: i8) -> i8;
+     #[link_name = "llvm.x86.avx512.mask.ucmp.d.512"]
+     fn vpcmpud(a: i32x16, b: i32x16, op: i32, m: i16) -> i16;
+     #[link_name = "llvm.x86.avx512.mask.cmp.d.512"]
+     fn vpcmpd(a: i32x16, b: i32x16, op: i32, m: i16) -> i16;
+ 
+     #[link_name = "llvm.x86.avx512.mask.prol.d.512"]
+     fn vprold(a: i32x16, i8: i32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.pror.d.512"]
+     fn vprord(a: i32x16, i8: i32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.prol.q.512"]
+     fn vprolq(a: i64x8, i8: i32) -> i64x8;
+     #[link_name = "llvm.x86.avx512.mask.pror.q.512"]
+     fn vprorq(a: i64x8, i8: i32) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.mask.prolv.d.512"]
+     fn vprolvd(a: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.prorv.d.512"]
+     fn vprorvd(a: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.mask.prolv.q.512"]
+     fn vprolvq(a: i64x8, b: i64x8) -> i64x8;
+     #[link_name = "llvm.x86.avx512.mask.prorv.q.512"]
+     fn vprorvq(a: i64x8, b: i64x8) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.psllv.d.512"]
+     fn vpsllvd(a: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psrlv.d.512"]
+     fn vpsrlvd(a: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psllv.q.512"]
+     fn vpsllvq(a: i64x8, b: i64x8) -> i64x8;
+     #[link_name = "llvm.x86.avx512.psrlv.q.512"]
+     fn vpsrlvq(a: i64x8, b: i64x8) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.pslli.d.512"]
+     fn vpsllid(a: i32x16, imm8: u32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psrli.d.512"]
+     fn vpsrlid(a: i32x16, imm8: u32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.pslli.q.512"]
+     fn vpslliq(a: i64x8, imm8: u32) -> i64x8;
+     #[link_name = "llvm.x86.avx512.psrli.q.512"]
+     fn vpsrliq(a: i64x8, imm8: u32) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.psll.d.512"]
+     fn vpslld(a: i32x16, count: i32x4) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psrl.d.512"]
+     fn vpsrld(a: i32x16, count: i32x4) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psll.q.512"]
+     fn vpsllq(a: i64x8, count: i64x2) -> i64x8;
+     #[link_name = "llvm.x86.avx512.psrl.q.512"]
+     fn vpsrlq(a: i64x8, count: i64x2) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.psra.d.512"]
+     fn vpsrad(a: i32x16, count: i32x4) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psra.q.512"]
+     fn vpsraq(a: i64x8, count: i64x2) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.psrai.d.512"]
+     fn vpsraid(a: i32x16, imm8: u32) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psrai.q.512"]
+     fn vpsraiq(a: i64x8, imm8: u32) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.psrav.d.512"]
+     fn vpsravd(a: i32x16, count: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.psrav.q.512"]
+     fn vpsravq(a: i64x8, count: i64x8) -> i64x8;
+ 
+     #[link_name = "llvm.x86.avx512.vpermilvar.ps.512"]
+     fn vpermilps(a: f32x16, b: i32x16) -> f32x16;
+     #[link_name = "llvm.x86.avx512.vpermilvar.pd.512"]
+     fn vpermilpd(a: f64x8, b: i64x8) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.permvar.si.512"]
+     fn vpermd(a: i32x16, idx: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.permvar.di.512"]
+     fn vpermq(a: i64x8, idx: i64x8) -> i64x8;
+     #[link_name = "llvm.x86.avx512.permvar.sf.512"]
+     fn vpermps(a: f32x16, idx: i32x16) -> f32x16;
+     #[link_name = "llvm.x86.avx512.permvar.df.512"]
+     fn vpermpd(a: f64x8, idx: i64x8) -> f64x8;
+ 
+     #[link_name = "llvm.x86.avx512.vpermi2var.d.512"]
+     fn vpermi2d(a: i32x16, idx: i32x16, b: i32x16) -> i32x16;
+     #[link_name = "llvm.x86.avx512.vpermi2var.q.512"]
+     fn vpermi2q(a: i64x8, idx: i64x8, b: i64x8) -> i64x8;
+     #[link_name = "llvm.x86.avx512.vpermi2var.ps.512"]
+     fn vpermi2ps(a: f32x16, idx: i32x16, b: f32x16) -> f32x16;
+     #[link_name = "llvm.x86.avx512.vpermi2var.pd.512"]
+     fn vpermi2pd(a: f64x8, idx: i64x8, b: f64x8) -> f64x8;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std;
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+     use crate::hint::black_box;
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_abs_epi32() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi32(
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+         );
+         let r = _mm512_abs_epi32(a);
+         let e = _mm512_setr_epi32(
+             0,
+             1,
+             1,
+             i32::MAX,
+             i32::MAX.wrapping_add(1),
+             100,
+             100,
+             32,
+             0,
+             1,
+             1,
+             i32::MAX,
+             i32::MAX.wrapping_add(1),
+             100,
+             100,
+             32,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_abs_epi32() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi32(
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+         );
+         let r = _mm512_mask_abs_epi32(a, 0, a);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_abs_epi32(a, 0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(
+             0,
+             1,
+             1,
+             i32::MAX,
+             i32::MAX.wrapping_add(1),
+             100,
+             100,
+             32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_abs_epi32() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi32(
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+         );
+         let r = _mm512_maskz_abs_epi32(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_abs_epi32(0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(
+             0,
+             1,
+             1,
+             i32::MAX,
+             i32::MAX.wrapping_add(1),
+             100,
+             100,
+             32,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_abs_ps() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_ps(
+             0., 1., -1., f32::MAX,
+             f32::MIN, 100., -100., -32.,
+             0., 1., -1., f32::MAX,
+             f32::MIN, 100., -100., -32.,
+         );
+         let r = _mm512_abs_ps(a);
+         let e = _mm512_setr_ps(
+             0.,
+             1.,
+             1.,
+             f32::MAX,
+             f32::MAX,
+             100.,
+             100.,
+             32.,
+             0.,
+             1.,
+             1.,
+             f32::MAX,
+             f32::MAX,
+             100.,
+             100.,
+             32.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_abs_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let r = _mm512_mask_abs_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_abs_ps(a, 0b00000000_11111111, a);
+         let e = _mm512_setr_ps(
+             0.,
+             1.,
+             1.,
+             f32::MAX,
+             f32::MAX,
+             100.,
+             100.,
+             32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_add_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_add_epi32(a, b);
+         let e = _mm512_setr_epi32(
+             1,
+             2,
+             0,
+             i32::MIN,
+             i32::MIN + 1,
+             101,
+             -99,
+             -31,
+             1,
+             2,
+             0,
+             i32::MIN,
+             i32::MIN + 1,
+             101,
+             -99,
+             -31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_add_epi32() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi32(
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_mask_add_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_add_epi32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(
+             1,
+             2,
+             0,
+             i32::MIN,
+             i32::MIN + 1,
+             101,
+             -99,
+             -31,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_add_epi32() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi32(
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+             0, 1, -1, i32::MAX,
+             i32::MIN, 100, -100, -32,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_maskz_add_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_add_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(
+             1,
+             2,
+             0,
+             i32::MIN,
+             i32::MIN + 1,
+             101,
+             -99,
+             -31,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_add_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_add_ps(a, b);
+         let e = _mm512_setr_ps(
+             1.,
+             2.,
+             0.,
+             f32::MAX,
+             f32::MIN + 1.,
+             101.,
+             -99.,
+             -31.,
+             1.,
+             2.,
+             0.,
+             f32::MAX,
+             f32::MIN + 1.,
+             101.,
+             -99.,
+             -31.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_add_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_mask_add_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_add_ps(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             1.,
+             2.,
+             0.,
+             f32::MAX,
+             f32::MIN + 1.,
+             101.,
+             -99.,
+             -31.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_add_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_maskz_add_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_add_ps(0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             1.,
+             2.,
+             0.,
+             f32::MAX,
+             f32::MIN + 1.,
+             101.,
+             -99.,
+             -31.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sub_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_sub_epi32(a, b);
+         let e = _mm512_setr_epi32(
+             -1,
+             0,
+             -2,
+             i32::MAX - 1,
+             i32::MAX,
+             99,
+             -101,
+             -33,
+             -1,
+             0,
+             -2,
+             i32::MAX - 1,
+             i32::MAX,
+             99,
+             -101,
+             -33,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sub_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_mask_sub_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_sub_epi32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(
+             -1,
+             0,
+             -2,
+             i32::MAX - 1,
+             i32::MAX,
+             99,
+             -101,
+             -33,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sub_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_maskz_sub_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_sub_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(
+             -1,
+             0,
+             -2,
+             i32::MAX - 1,
+             i32::MAX,
+             99,
+             -101,
+             -33,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sub_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_sub_ps(a, b);
+         let e = _mm512_setr_ps(
+             -1.,
+             0.,
+             -2.,
+             f32::MAX - 1.,
+             f32::MIN,
+             99.,
+             -101.,
+             -33.,
+             -1.,
+             0.,
+             -2.,
+             f32::MAX - 1.,
+             f32::MIN,
+             99.,
+             -101.,
+             -33.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sub_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_mask_sub_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_sub_ps(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             -1.,
+             0.,
+             -2.,
+             f32::MAX - 1.,
+             f32::MIN,
+             99.,
+             -101.,
+             -33.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sub_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_maskz_sub_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_sub_ps(0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             -1.,
+             0.,
+             -2.,
+             f32::MAX - 1.,
+             f32::MIN,
+             99.,
+             -101.,
+             -33.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mullo_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(2);
+         let r = _mm512_mullo_epi32(a, b);
+         let e = _mm512_setr_epi32(
+             0, 2, -2, -2, 0, 200, -200, -64, 0, 2, -2, -2, 0, 200, -200, -64,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mullo_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(2);
+         let r = _mm512_mask_mullo_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_mullo_epi32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(
+             0,
+             2,
+             -2,
+             -2,
+             0,
+             200,
+             -200,
+             -64,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mullo_epi32() {
+         let a = _mm512_setr_epi32(
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+             0,
+             1,
+             -1,
+             i32::MAX,
+             i32::MIN,
+             100,
+             -100,
+             -32,
+         );
+         let b = _mm512_set1_epi32(2);
+         let r = _mm512_maskz_mullo_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_mullo_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(0, 2, -2, -2, 0, 200, -200, -64, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mul_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(2.);
+         let r = _mm512_mul_ps(a, b);
+         let e = _mm512_setr_ps(
+             0.,
+             2.,
+             -2.,
+             f32::INFINITY,
+             f32::NEG_INFINITY,
+             200.,
+             -200.,
+             -64.,
+             0.,
+             2.,
+             -2.,
+             f32::INFINITY,
+             f32::NEG_INFINITY,
+             200.,
+             -200.,
+             -64.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mul_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(2.);
+         let r = _mm512_mask_mul_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_mul_ps(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             0.,
+             2.,
+             -2.,
+             f32::INFINITY,
+             f32::NEG_INFINITY,
+             200.,
+             -200.,
+             -64.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mul_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+             0.,
+             1.,
+             -1.,
+             f32::MAX,
+             f32::MIN,
+             100.,
+             -100.,
+             -32.,
+         );
+         let b = _mm512_set1_ps(2.);
+         let r = _mm512_maskz_mul_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_mul_ps(0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             0.,
+             2.,
+             -2.,
+             f32::INFINITY,
+             f32::NEG_INFINITY,
+             200.,
+             -200.,
+             -64.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_div_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
+         );
+         let b = _mm512_setr_ps(
+             2., 2., 2., 2., 2., 0., 2., 2., 2., 2., 2., 2., 0., 2., 2., 2.,
+         );
+         let r = _mm512_div_ps(a, b);
+         let e = _mm512_setr_ps(
+             0.,
+             0.5,
+             -0.5,
+             -1.,
+             50.,
+             f32::INFINITY,
+             -50.,
+             -16.,
+             0.,
+             0.5,
+             -0.5,
+             500.,
+             f32::NEG_INFINITY,
+             50.,
+             -50.,
+             -16.,
+         );
+         assert_eq_m512(r, e); // 0/0 = NAN
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_div_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
+         );
+         let b = _mm512_setr_ps(
+             2., 2., 2., 2., 2., 0., 2., 2., 2., 2., 2., 2., 0., 2., 2., 2.,
+         );
+         let r = _mm512_mask_div_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_div_ps(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             0.,
+             0.5,
+             -0.5,
+             -1.,
+             50.,
+             f32::INFINITY,
+             -50.,
+             -16.,
+             0.,
+             1.,
+             -1.,
+             1000.,
+             -131.,
+             100.,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_div_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., -1., -2., 100., 100., -100., -32., 0., 1., -1., 1000., -131., 100., -100., -32.,
+         );
+         let b = _mm512_setr_ps(
+             2., 2., 2., 2., 2., 0., 2., 2., 2., 2., 2., 2., 0., 2., 2., 2.,
+         );
+         let r = _mm512_maskz_div_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_div_ps(0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             0.,
+             0.5,
+             -0.5,
+             -1.,
+             50.,
+             f32::INFINITY,
+             -50.,
+             -16.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_epi32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_max_epi32(a, b);
+         let e = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_epi32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_max_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_max_epi32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_epi32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_max_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_max_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_max_ps(a, b);
+         let e = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_mask_max_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_max_ps(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_maskz_max_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_max_ps(0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_epu32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_max_epu32(a, b);
+         let e = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_epu32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_max_epu32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_max_epu32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_epu32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_max_epu32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_max_epu32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_epi32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_min_epi32(a, b);
+         let e = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_epi32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_min_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_min_epi32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_epi32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_min_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_min_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_min_ps(a, b);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_mask_min_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_min_ps(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_maskz_min_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_min_ps(0b00000000_11111111, a, b);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_epu32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_min_epu32(a, b);
+         let e = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_epu32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_min_epu32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_min_epu32(a, 0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_epu32() {
+         let a = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_min_epu32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_min_epu32(0b00000000_11111111, a, b);
+         let e = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sqrt_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 4., 9., 16., 25., 36., 49., 64., 81., 100., 121., 144., 169., 196., 225.,
+         );
+         let r = _mm512_sqrt_ps(a);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sqrt_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 4., 9., 16., 25., 36., 49., 64., 81., 100., 121., 144., 169., 196., 225.,
+         );
+         let r = _mm512_mask_sqrt_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_sqrt_ps(a, 0b00000000_11111111, a);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 64., 81., 100., 121., 144., 169., 196., 225.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sqrt_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 4., 9., 16., 25., 36., 49., 64., 81., 100., 121., 144., 169., 196., 225.,
+         );
+         let r = _mm512_maskz_sqrt_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_sqrt_ps(0b00000000_11111111, a);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_fmadd_ps(a, b, c);
+         let e = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_mask_fmadd_ps(a, 0, b, c);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmadd_ps(a, 0b00000000_11111111, b, c);
+         let e = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_maskz_fmadd_ps(0, a, b, c);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmadd_ps(0b00000000_11111111, a, b, c);
+         let e = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         let r = _mm512_mask3_fmadd_ps(a, b, c, 0);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmadd_ps(a, b, c, 0b00000000_11111111);
+         let e = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_fmsub_ps(a, b, c);
+         let e = _mm512_setr_ps(
+             -1., 0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_mask_fmsub_ps(a, 0, b, c);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmsub_ps(a, 0b00000000_11111111, b, c);
+         let e = _mm512_setr_ps(
+             -1., 0., 1., 2., 3., 4., 5., 6., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_maskz_fmsub_ps(0, a, b, c);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmsub_ps(0b00000000_11111111, a, b, c);
+         let e = _mm512_setr_ps(
+             -1., 0., 1., 2., 3., 4., 5., 6., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         let r = _mm512_mask3_fmsub_ps(a, b, c, 0);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmsub_ps(a, b, c, 0b00000000_11111111);
+         let e = _mm512_setr_ps(
+             -1., 0., 1., 2., 3., 4., 5., 6., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmaddsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_fmaddsub_ps(a, b, c);
+         let e = _mm512_setr_ps(
+             -1., 2., 1., 4., 3., 6., 5., 8., 7., 10., 9., 12., 11., 14., 13., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmaddsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_mask_fmaddsub_ps(a, 0, b, c);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmaddsub_ps(a, 0b00000000_11111111, b, c);
+         let e = _mm512_setr_ps(
+             -1., 2., 1., 4., 3., 6., 5., 8., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmaddsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_maskz_fmaddsub_ps(0, a, b, c);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmaddsub_ps(0b00000000_11111111, a, b, c);
+         let e = _mm512_setr_ps(
+             -1., 2., 1., 4., 3., 6., 5., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmaddsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         let r = _mm512_mask3_fmaddsub_ps(a, b, c, 0);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmaddsub_ps(a, b, c, 0b00000000_11111111);
+         let e = _mm512_setr_ps(
+             -1., 2., 1., 4., 3., 6., 5., 8., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsubadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_fmsubadd_ps(a, b, c);
+         let e = _mm512_setr_ps(
+             1., 0., 3., 2., 5., 4., 7., 6., 9., 8., 11., 10., 13., 12., 15., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsubadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_mask_fmsubadd_ps(a, 0, b, c);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmsubadd_ps(a, 0b00000000_11111111, b, c);
+         let e = _mm512_setr_ps(
+             1., 0., 3., 2., 5., 4., 7., 6., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsubadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_maskz_fmsubadd_ps(0, a, b, c);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmsubadd_ps(0b00000000_11111111, a, b, c);
+         let e = _mm512_setr_ps(
+             1., 0., 3., 2., 5., 4., 7., 6., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsubadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         let r = _mm512_mask3_fmsubadd_ps(a, b, c, 0);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmsubadd_ps(a, b, c, 0b00000000_11111111);
+         let e = _mm512_setr_ps(
+             1., 0., 3., 2., 5., 4., 7., 6., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_fnmadd_ps(a, b, c);
+         let e = _mm512_setr_ps(
+             1., 0., -1., -2., -3., -4., -5., -6., -7., -8., -9., -10., -11., -12., -13., -14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_mask_fnmadd_ps(a, 0, b, c);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fnmadd_ps(a, 0b00000000_11111111, b, c);
+         let e = _mm512_setr_ps(
+             1., 0., -1., -2., -3., -4., -5., -6., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_maskz_fnmadd_ps(0, a, b, c);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fnmadd_ps(0b00000000_11111111, a, b, c);
+         let e = _mm512_setr_ps(
+             1., 0., -1., -2., -3., -4., -5., -6., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmadd_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         let r = _mm512_mask3_fnmadd_ps(a, b, c, 0);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fnmadd_ps(a, b, c, 0b00000000_11111111);
+         let e = _mm512_setr_ps(
+             1., 0., -1., -2., -3., -4., -5., -6., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_fnmsub_ps(a, b, c);
+         let e = _mm512_setr_ps(
+             -1., -2., -3., -4., -5., -6., -7., -8., -9., -10., -11., -12., -13., -14., -15., -16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_mask_fnmsub_ps(a, 0, b, c);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fnmsub_ps(a, 0b00000000_11111111, b, c);
+         let e = _mm512_setr_ps(
+             -1., -2., -3., -4., -5., -6., -7., -8., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let r = _mm512_maskz_fnmsub_ps(0, a, b, c);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fnmsub_ps(0b00000000_11111111, a, b, c);
+         let e = _mm512_setr_ps(
+             -1., -2., -3., -4., -5., -6., -7., -8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmsub_ps() {
+         let a = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         let b = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let c = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         let r = _mm512_mask3_fnmsub_ps(a, b, c, 0);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fnmsub_ps(a, b, c, 0b00000000_11111111);
+         let e = _mm512_setr_ps(
+             -1., -2., -3., -4., -5., -6., -7., -8., 2., 2., 2., 2., 2., 2., 2., 2.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rcp14_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_rcp14_ps(a);
+         let e = _mm512_set1_ps(0.33333206);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rcp14_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_mask_rcp14_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_rcp14_ps(a, 0b11111111_00000000, a);
+         let e = _mm512_setr_ps(
+             3., 3., 3., 3., 3., 3., 3., 3., 0.33333206, 0.33333206, 0.33333206, 0.33333206,
+             0.33333206, 0.33333206, 0.33333206, 0.33333206,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rcp14_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_maskz_rcp14_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_rcp14_ps(0b11111111_00000000, a);
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 0.33333206, 0.33333206, 0.33333206, 0.33333206,
+             0.33333206, 0.33333206, 0.33333206, 0.33333206,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rsqrt14_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_rsqrt14_ps(a);
+         let e = _mm512_set1_ps(0.5773392);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rsqrt14_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_mask_rsqrt14_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_rsqrt14_ps(a, 0b11111111_00000000, a);
+         let e = _mm512_setr_ps(
+             3., 3., 3., 3., 3., 3., 3., 3., 0.5773392, 0.5773392, 0.5773392, 0.5773392, 0.5773392,
+             0.5773392, 0.5773392, 0.5773392,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rsqrt14_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_maskz_rsqrt14_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_rsqrt14_ps(0b11111111_00000000, a);
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 0.5773392, 0.5773392, 0.5773392, 0.5773392, 0.5773392,
+             0.5773392, 0.5773392, 0.5773392,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getexp_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_getexp_ps(a);
+         let e = _mm512_set1_ps(1.);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getexp_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_mask_getexp_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_getexp_ps(a, 0b11111111_00000000, a);
+         let e = _mm512_setr_ps(
+             3., 3., 3., 3., 3., 3., 3., 3., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getexp_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_maskz_getexp_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_getexp_ps(0b11111111_00000000, a);
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getmant_ps() {
+         let a = _mm512_set1_ps(10.);
+         let r = _mm512_getmant_ps(a, _MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN);
+         let e = _mm512_set1_ps(1.25);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getmant_ps() {
+         let a = _mm512_set1_ps(10.);
+         let r = _mm512_mask_getmant_ps(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_getmant_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+         );
+         let e = _mm512_setr_ps(
+             10., 10., 10., 10., 10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getmant_ps() {
+         let a = _mm512_set1_ps(10.);
+         let r = _mm512_maskz_getmant_ps(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r =
+             _mm512_maskz_getmant_ps(0b11111111_00000000, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_add_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
+         );
+         let b = _mm512_set1_ps(-1.);
+         let r = _mm512_add_round_ps(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             -1.,
+             0.5,
+             1.,
+             2.5,
+             3.,
+             4.5,
+             5.,
+             6.5,
+             7.,
+             8.5,
+             9.,
+             10.5,
+             11.,
+             12.5,
+             13.,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+         let r = _mm512_add_round_ps(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             -1., 0.5, 1., 2.5, 3., 4.5, 5., 6.5, 7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_add_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
+         );
+         let b = _mm512_set1_ps(-1.);
+         let r = _mm512_mask_add_round_ps(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_add_round_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.,
+             1.5,
+             2.,
+             3.5,
+             4.,
+             5.5,
+             6.,
+             7.5,
+             7.,
+             8.5,
+             9.,
+             10.5,
+             11.,
+             12.5,
+             13.,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_add_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
+         );
+         let b = _mm512_set1_ps(-1.);
+         let r = _mm512_maskz_add_round_ps(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_add_round_ps(
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             7.,
+             8.5,
+             9.,
+             10.5,
+             11.,
+             12.5,
+             13.,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sub_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_sub_round_ps(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             -1.,
+             0.5,
+             1.,
+             2.5,
+             3.,
+             4.5,
+             5.,
+             6.5,
+             7.,
+             8.5,
+             9.,
+             10.5,
+             11.,
+             12.5,
+             13.,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+         let r = _mm512_sub_round_ps(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             -1., 0.5, 1., 2.5, 3., 4.5, 5., 6.5, 7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sub_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_mask_sub_round_ps(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_sub_round_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.,
+             1.5,
+             2.,
+             3.5,
+             4.,
+             5.5,
+             6.,
+             7.5,
+             7.,
+             8.5,
+             9.,
+             10.5,
+             11.,
+             12.5,
+             13.,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sub_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 0.00000007,
+         );
+         let b = _mm512_set1_ps(1.);
+         let r = _mm512_maskz_sub_round_ps(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_sub_round_ps(
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             7.,
+             8.5,
+             9.,
+             10.5,
+             11.,
+             12.5,
+             13.,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mul_round_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.5,
+             2.,
+             3.5,
+             4.,
+             5.5,
+             6.,
+             7.5,
+             8.,
+             9.5,
+             10.,
+             11.5,
+             12.,
+             13.5,
+             14.,
+             0.00000000000000000000007,
+         );
+         let b = _mm512_set1_ps(0.1);
+         let r = _mm512_mul_round_ps(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             0.,
+             0.15,
+             0.2,
+             0.35,
+             0.4,
+             0.55,
+             0.6,
+             0.75,
+             0.8,
+             0.95,
+             1.0,
+             1.15,
+             1.2,
+             1.35,
+             1.4,
+             0.000000000000000000000007000001,
+         );
+         assert_eq_m512(r, e);
+         let r = _mm512_mul_round_ps(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             0.,
+             0.14999999,
+             0.2,
+             0.35,
+             0.4,
+             0.54999995,
+             0.59999996,
+             0.75,
+             0.8,
+             0.95,
+             1.0,
+             1.15,
+             1.1999999,
+             1.3499999,
+             1.4,
+             0.000000000000000000000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mul_round_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.5,
+             2.,
+             3.5,
+             4.,
+             5.5,
+             6.,
+             7.5,
+             8.,
+             9.5,
+             10.,
+             11.5,
+             12.,
+             13.5,
+             14.,
+             0.00000000000000000000007,
+         );
+         let b = _mm512_set1_ps(0.1);
+         let r = _mm512_mask_mul_round_ps(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_mul_round_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.,
+             1.5,
+             2.,
+             3.5,
+             4.,
+             5.5,
+             6.,
+             7.5,
+             0.8,
+             0.95,
+             1.0,
+             1.15,
+             1.2,
+             1.35,
+             1.4,
+             0.000000000000000000000007000001,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mul_round_ps() {
+         let a = _mm512_setr_ps(
+             0.,
+             1.5,
+             2.,
+             3.5,
+             4.,
+             5.5,
+             6.,
+             7.5,
+             8.,
+             9.5,
+             10.,
+             11.5,
+             12.,
+             13.5,
+             14.,
+             0.00000000000000000000007,
+         );
+         let b = _mm512_set1_ps(0.1);
+         let r = _mm512_maskz_mul_round_ps(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_mul_round_ps(
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.8,
+             0.95,
+             1.0,
+             1.15,
+             1.2,
+             1.35,
+             1.4,
+             0.000000000000000000000007000001,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_div_round_ps() {
+         let a = _mm512_set1_ps(1.);
+         let b = _mm512_set1_ps(3.);
+         let r = _mm512_div_round_ps(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(0.33333334);
+         assert_eq_m512(r, e);
+         let r = _mm512_div_round_ps(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(0.3333333);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_div_round_ps() {
+         let a = _mm512_set1_ps(1.);
+         let b = _mm512_set1_ps(3.);
+         let r = _mm512_mask_div_round_ps(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_div_round_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             1., 1., 1., 1., 1., 1., 1., 1., 0.33333334, 0.33333334, 0.33333334, 0.33333334,
+             0.33333334, 0.33333334, 0.33333334, 0.33333334,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_div_round_ps() {
+         let a = _mm512_set1_ps(1.);
+         let b = _mm512_set1_ps(3.);
+         let r = _mm512_maskz_div_round_ps(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_div_round_ps(
+             0b11111111_00000000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 0.33333334, 0.33333334, 0.33333334, 0.33333334,
+             0.33333334, 0.33333334, 0.33333334, 0.33333334,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sqrt_round_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_sqrt_round_ps(a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(1.7320508);
+         assert_eq_m512(r, e);
+         let r = _mm512_sqrt_round_ps(a, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(1.7320509);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sqrt_round_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_mask_sqrt_round_ps(a, 0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_sqrt_round_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             3., 3., 3., 3., 3., 3., 3., 3., 1.7320508, 1.7320508, 1.7320508, 1.7320508, 1.7320508,
+             1.7320508, 1.7320508, 1.7320508,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sqrt_round_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_maskz_sqrt_round_ps(0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_sqrt_round_ps(
+             0b11111111_00000000,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 1.7320508, 1.7320508, 1.7320508, 1.7320508, 1.7320508,
+             1.7320508, 1.7320508, 1.7320508,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_fmadd_round_ps(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(-0.99999994);
+         assert_eq_m512(r, e);
+         let r = _mm512_fmadd_round_ps(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(-0.9999999);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r =
+             _mm512_mask_fmadd_round_ps(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmadd_round_ps(
+             a,
+             0b00000000_11111111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r =
+             _mm512_maskz_fmadd_round_ps(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmadd_round_ps(
+             0b00000000_11111111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r =
+             _mm512_mask3_fmadd_round_ps(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmadd_round_ps(
+             a,
+             b,
+             c,
+             0b00000000_11111111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r = _mm512_fmsub_round_ps(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(-0.99999994);
+         assert_eq_m512(r, e);
+         let r = _mm512_fmsub_round_ps(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(-0.9999999);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r =
+             _mm512_mask_fmsub_round_ps(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmsub_round_ps(
+             a,
+             0b00000000_11111111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r =
+             _mm512_maskz_fmsub_round_ps(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmsub_round_ps(
+             0b00000000_11111111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r =
+             _mm512_mask3_fmsub_round_ps(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmsub_round_ps(
+             a,
+             b,
+             c,
+             0b00000000_11111111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             -0.99999994,
+             1.,
+             1.,
+             1.,
+             1.,
+             1.,
+             1.,
+             1.,
+             1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmaddsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_fmaddsub_round_ps(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+         );
+         assert_eq_m512(r, e);
+         let r = _mm512_fmaddsub_round_ps(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             1., -0.9999999, 1., -0.9999999, 1., -0.9999999, 1., -0.9999999, 1., -0.9999999, 1.,
+             -0.9999999, 1., -0.9999999, 1., -0.9999999,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmaddsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_mask_fmaddsub_round_ps(
+             a,
+             0,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmaddsub_round_ps(
+             a,
+             0b00000000_11111111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmaddsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_maskz_fmaddsub_round_ps(
+             0,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmaddsub_round_ps(
+             0b00000000_11111111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmaddsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_mask3_fmaddsub_round_ps(
+             a,
+             b,
+             c,
+             0,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmaddsub_round_ps(
+             a,
+             b,
+             c,
+             0b00000000_11111111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsubadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_fmsubadd_round_ps(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+         );
+         assert_eq_m512(r, e);
+         let r = _mm512_fmsubadd_round_ps(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_ps(
+             -0.9999999, 1., -0.9999999, 1., -0.9999999, 1., -0.9999999, 1., -0.9999999, 1.,
+             -0.9999999, 1., -0.9999999, 1., -0.9999999, 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsubadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_mask_fmsubadd_round_ps(
+             a,
+             0,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fmsubadd_round_ps(
+             a,
+             0b00000000_11111111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+             0.00000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsubadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_maskz_fmsubadd_round_ps(
+             0,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fmsubadd_round_ps(
+             0b00000000_11111111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+             0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsubadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_mask3_fmsubadd_round_ps(
+             a,
+             b,
+             c,
+             0,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fmsubadd_round_ps(
+             a,
+             b,
+             c,
+             0b00000000_11111111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -0.99999994,
+             1.0000001,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r = _mm512_fnmadd_round_ps(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(0.99999994);
+         assert_eq_m512(r, e);
+         let r = _mm512_fnmadd_round_ps(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(0.9999999);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r =
+             _mm512_mask_fnmadd_round_ps(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fnmadd_round_ps(
+             a,
+             0b00000000_11111111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994,
+             0.99999994, 0.00000007, 0.00000007, 0.00000007, 0.00000007, 0.00000007, 0.00000007,
+             0.00000007, 0.00000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r =
+             _mm512_maskz_fnmadd_round_ps(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fnmadd_round_ps(
+             0b00000000_11111111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994,
+             0.99999994, 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmadd_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(1.);
+         let r =
+             _mm512_mask3_fnmadd_round_ps(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fnmadd_round_ps(
+             a,
+             b,
+             c,
+             0b00000000_11111111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994,
+             0.99999994, 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r = _mm512_fnmsub_round_ps(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(0.99999994);
+         assert_eq_m512(r, e);
+         let r = _mm512_fnmsub_round_ps(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(0.9999999);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r =
+             _mm512_mask_fnmsub_round_ps(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_fnmsub_round_ps(
+             a,
+             0b00000000_11111111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994,
+             0.99999994, 0.00000007, 0.00000007, 0.00000007, 0.00000007, 0.00000007, 0.00000007,
+             0.00000007, 0.00000007,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r =
+             _mm512_maskz_fnmsub_round_ps(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_fnmsub_round_ps(
+             0b00000000_11111111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994,
+             0.99999994, 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmsub_round_ps() {
+         let a = _mm512_set1_ps(0.00000007);
+         let b = _mm512_set1_ps(1.);
+         let c = _mm512_set1_ps(-1.);
+         let r =
+             _mm512_mask3_fnmsub_round_ps(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512(r, c);
+         let r = _mm512_mask3_fnmsub_round_ps(
+             a,
+             b,
+             c,
+             0b00000000_11111111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_ps(
+             0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994, 0.99999994,
+             0.99999994, -1., -1., -1., -1., -1., -1., -1., -1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_max_round_ps(a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_mask_max_round_ps(a, 0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_max_round_ps(a, 0b00000000_11111111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_maskz_max_round_ps(0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_max_round_ps(0b00000000_11111111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_min_round_ps(a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_mask_min_round_ps(a, 0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_min_round_ps(a, 0b00000000_11111111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_round_ps() {
+         let a = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_setr_ps(
+             15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+         );
+         let r = _mm512_maskz_min_round_ps(0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_min_round_ps(0b00000000_11111111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getexp_round_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_getexp_round_ps(a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_set1_ps(1.);
+         assert_eq_m512(r, e);
+         let r = _mm512_getexp_round_ps(a, _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_ps(1.);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getexp_round_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_mask_getexp_round_ps(a, 0, a, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_getexp_round_ps(a, 0b11111111_00000000, a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             3., 3., 3., 3., 3., 3., 3., 3., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getexp_round_ps() {
+         let a = _mm512_set1_ps(3.);
+         let r = _mm512_maskz_getexp_round_ps(0, a, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_getexp_round_ps(0b11111111_00000000, a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getmant_round_ps() {
+         let a = _mm512_set1_ps(10.);
+         let r = _mm512_getmant_round_ps(
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         let e = _mm512_set1_ps(1.25);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getmant_round_ps() {
+         let a = _mm512_set1_ps(10.);
+         let r = _mm512_mask_getmant_round_ps(
+             a,
+             0,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_getmant_round_ps(
+             a,
+             0b11111111_00000000,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         let e = _mm512_setr_ps(
+             10., 10., 10., 10., 10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getmant_round_ps() {
+         let a = _mm512_set1_ps(10.);
+         let r = _mm512_maskz_getmant_round_ps(
+             0,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_getmant_round_ps(
+             0b11111111_00000000,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         let e = _mm512_setr_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvtps_epi32(a);
+         let e = _mm512_setr_epi32(0, -1, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r = _mm512_mask_cvtps_epi32(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvtps_epi32(src, 0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -4, 4, -6, 6, -8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvtps_epi32(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvtps_epi32(0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -4, 4, -6, 6, -8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvtps_epu32(a);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 8, 10, 10, 12, 12, 14, 14, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r = _mm512_mask_cvtps_epu32(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvtps_epu32(src, 0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.4, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvtps_epu32(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvtps_epu32(0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvt_roundps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvt_roundps_epi32(a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 10, 10, 12, 12, 14, 14, 16);
+         assert_eq_m512i(r, e);
+         let r = _mm512_cvt_roundps_epi32(a, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvt_roundps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r =
+             _mm512_mask_cvt_roundps_epi32(src, 0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvt_roundps_epi32(
+             src,
+             0b00000000_11111111,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvt_roundps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvt_roundps_epi32(0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvt_roundps_epi32(
+             0b00000000_11111111,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvt_roundps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvt_roundps_epu32(a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 8, 10, 10, 12, 12, 14, 14, 16);
+         assert_eq_m512i(r, e);
+         let r = _mm512_cvt_roundps_epu32(a, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvt_roundps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r =
+             _mm512_mask_cvt_roundps_epu32(src, 0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvt_roundps_epu32(
+             src,
+             0b00000000_11111111,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvt_roundps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvt_roundps_epu32(0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvt_roundps_epu32(
+             0b00000000_11111111,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtt_roundps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvtt_roundps_epi32(a, _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtt_roundps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r = _mm512_mask_cvtt_roundps_epi32(src, 0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvtt_roundps_epi32(src, 0b00000000_11111111, a, _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtt_roundps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvtt_roundps_epi32(0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvtt_roundps_epi32(0b00000000_11111111, a, _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtt_roundps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvtt_roundps_epu32(a, _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtt_roundps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r = _mm512_mask_cvtt_roundps_epu32(src, 0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvtt_roundps_epu32(src, 0b00000000_11111111, a, _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtt_roundps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvtt_roundps_epu32(0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvtt_roundps_epu32(0b00000000_11111111, a, _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvttps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvttps_epi32(a);
+         let e = _mm512_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvttps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r = _mm512_mask_cvttps_epi32(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvttps_epi32(src, 0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvttps_epi32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvttps_epi32(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvttps_epi32(0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvttps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_cvttps_epu32(a);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvttps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let src = _mm512_set1_epi32(0);
+         let r = _mm512_mask_cvttps_epu32(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_cvttps_epu32(src, 0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvttps_epu32() {
+         let a = _mm512_setr_ps(
+             0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 8., 9.5, 10., 11.5, 12., 13.5, 14., 15.5,
+         );
+         let r = _mm512_maskz_cvttps_epu32(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_cvttps_epu32(0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32gather_ps() {
+         let mut arr = [0f32; 256];
+         for i in 0..256 {
+             arr[i] = i as f32;
+         }
+         // A multiplier of 4 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       120, 128, 136, 144, 152, 160, 168, 176);
+         let r = _mm512_i32gather_ps(index, arr.as_ptr() as *const u8, 4);
+         #[rustfmt::skip]
+         assert_eq_m512(r, _mm512_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.,
+                                          120., 128., 136., 144., 152., 160., 168., 176.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32gather_ps() {
+         let mut arr = [0f32; 256];
+         for i in 0..256 {
+             arr[i] = i as f32;
+         }
+         let src = _mm512_set1_ps(2.);
+         let mask = 0b10101010_10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       120, 128, 136, 144, 152, 160, 168, 176);
+         // A multiplier of 4 is word-addressing
+         let r = _mm512_mask_i32gather_ps(src, mask, index, arr.as_ptr() as *const u8, 4);
+         #[rustfmt::skip]
+         assert_eq_m512(r, _mm512_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.,
+                                          2., 128., 2., 144., 2., 160., 2., 176.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32gather_epi32() {
+         let mut arr = [0i32; 256];
+         for i in 0..256 {
+             arr[i] = i as i32;
+         }
+         // A multiplier of 4 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       120, 128, 136, 144, 152, 160, 168, 176);
+         let r = _mm512_i32gather_epi32(index, arr.as_ptr() as *const u8, 4);
+         #[rustfmt::skip]
+         assert_eq_m512i(r, _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                              120, 128, 136, 144, 152, 160, 168, 176));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32gather_epi32() {
+         let mut arr = [0i32; 256];
+         for i in 0..256 {
+             arr[i] = i as i32;
+         }
+         let src = _mm512_set1_epi32(2);
+         let mask = 0b10101010_10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       128, 144, 160, 176, 192, 208, 224, 240);
+         // A multiplier of 4 is word-addressing
+         let r = _mm512_mask_i32gather_epi32(src, mask, index, arr.as_ptr() as *const u8, 4);
+         #[rustfmt::skip]
+         assert_eq_m512i(r, _mm512_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112,
+                                              2, 144, 2, 176, 2, 208, 2, 240));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32scatter_ps() {
+         let mut arr = [0f32; 256];
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       128, 144, 160, 176, 192, 208, 224, 240);
+         let src = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         // A multiplier of 4 is word-addressing
+         _mm512_i32scatter_ps(arr.as_mut_ptr() as *mut u8, index, src, 4);
+         let mut expected = [0f32; 256];
+         for i in 0..16 {
+             expected[i * 16] = (i + 1) as f32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32scatter_ps() {
+         let mut arr = [0f32; 256];
+         let mask = 0b10101010_10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       128, 144, 160, 176, 192, 208, 224, 240);
+         let src = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         // A multiplier of 4 is word-addressing
+         _mm512_mask_i32scatter_ps(arr.as_mut_ptr() as *mut u8, mask, index, src, 4);
+         let mut expected = [0f32; 256];
+         for i in 0..8 {
+             expected[i * 32 + 16] = 2. * (i + 1) as f32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32scatter_epi32() {
+         let mut arr = [0i32; 256];
+         #[rustfmt::skip]
+ 
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       128, 144, 160, 176, 192, 208, 224, 240);
+         let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         // A multiplier of 4 is word-addressing
+         _mm512_i32scatter_epi32(arr.as_mut_ptr() as *mut u8, index, src, 4);
+         let mut expected = [0i32; 256];
+         for i in 0..16 {
+             expected[i * 16] = (i + 1) as i32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32scatter_epi32() {
+         let mut arr = [0i32; 256];
+         let mask = 0b10101010_10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
+                                       128, 144, 160, 176, 192, 208, 224, 240);
+         let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         // A multiplier of 4 is word-addressing
+         _mm512_mask_i32scatter_epi32(arr.as_mut_ptr() as *mut u8, mask, index, src, 4);
+         let mut expected = [0i32; 256];
+         for i in 0..8 {
+             expected[i * 32 + 16] = 2 * (i + 1) as i32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmplt_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let m = _mm512_cmplt_ps_mask(a, b);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmplt_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmplt_ps_mask(mask, a, b);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpnlt_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         assert_eq!(_mm512_cmpnlt_ps_mask(a, b), !_mm512_cmplt_ps_mask(a, b));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpnlt_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let mask = 0b01111010_01111010;
+         assert_eq!(_mm512_mask_cmpnlt_ps_mask(mask, a, b), 0b01111010_01111010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpnle_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let m = _mm512_cmpnle_ps_mask(b, a);
+         assert_eq!(m, 0b00001101_00001101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpnle_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmpnle_ps_mask(mask, b, a);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmple_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         assert_eq!(_mm512_cmple_ps_mask(a, b), 0b00100101_00100101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmple_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.,
+                               0., 1., -1., f32::MAX, f32::NAN, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let mask = 0b01111010_01111010;
+         assert_eq!(_mm512_mask_cmple_ps_mask(mask, a, b), 0b00100000_00100000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpeq_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.);
+         let m = _mm512_cmpeq_ps_mask(b, a);
+         assert_eq!(m, 0b11001101_11001101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpeq_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpeq_ps_mask(mask, b, a);
+         assert_eq!(r, 0b01001000_01001000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpneq_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.);
+         let m = _mm512_cmpneq_ps_mask(b, a);
+         assert_eq!(m, 0b00110010_00110010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpneq_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, f32::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.,
+                               0., 1., 13., 42., f32::MAX, f32::MIN, f32::NAN, -100.);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpneq_ps_mask(mask, b, a);
+         assert_eq!(r, 0b00110010_00110010)
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let m = _mm512_cmp_ps_mask(a, b, _CMP_LT_OQ);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmp_ps_mask(mask, a, b, _CMP_LT_OQ);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_round_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let m = _mm512_cmp_round_ps_mask(a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_round_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.,
+                               0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.);
+         let b = _mm512_set1_ps(-1.);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmp_round_ps_mask(mask, a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpord_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
+                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 0.,
+                               f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 2.);
+         let m = _mm512_cmpord_ps_mask(a, b);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpord_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
+                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 0.,
+                               f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 2.);
+         let mask = 0b11000011_11000011;
+         let m = _mm512_mask_cmpord_ps_mask(mask, a, b);
+         assert_eq!(m, 0b00000001_00000001);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpunord_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
+                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 0.,
+                               f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 2.);
+         let m = _mm512_cmpunord_ps_mask(a, b);
+ 
+         assert_eq!(m, 0b11111010_11111010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpunord_ps_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_ps(f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, -1., f32::NAN, 0.,
+                               f32::NAN, f32::MAX, f32::NAN, f32::MIN, f32::NAN, 1., f32::NAN, 2.);
+         #[rustfmt::skip]
+         let b = _mm512_set_ps(f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 0.,
+                               f32::NAN, f32::NAN, f32::NAN, f32::NAN, f32::MIN, f32::MAX, -1., 2.);
+         let mask = 0b00001111_00001111;
+         let m = _mm512_mask_cmpunord_ps_mask(mask, a, b);
+         assert_eq!(m, 0b000001010_00001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_cmp_ss_mask() {
+         let a = _mm_setr_ps(2., 1., 1., 1.);
+         let b = _mm_setr_ps(1., 2., 2., 2.);
+         let m = _mm_cmp_ss_mask(a, b, _CMP_GE_OS);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_mask_cmp_ss_mask() {
+         let a = _mm_setr_ps(2., 1., 1., 1.);
+         let b = _mm_setr_ps(1., 2., 2., 2.);
+         let m = _mm_mask_cmp_ss_mask(0b10, a, b, _CMP_GE_OS);
+         assert_eq!(m, 0);
+         let m = _mm_mask_cmp_ss_mask(0b1, a, b, _CMP_GE_OS);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_cmp_round_ss_mask() {
+         let a = _mm_setr_ps(2., 1., 1., 1.);
+         let b = _mm_setr_ps(1., 2., 2., 2.);
+         let m = _mm_cmp_round_ss_mask(a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_mask_cmp_round_ss_mask() {
+         let a = _mm_setr_ps(2., 1., 1., 1.);
+         let b = _mm_setr_ps(1., 2., 2., 2.);
+         let m = _mm_mask_cmp_round_ss_mask(0b10, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 0);
+         let m = _mm_mask_cmp_round_ss_mask(0b1, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_cmp_sd_mask() {
+         let a = _mm_setr_pd(2., 1.);
+         let b = _mm_setr_pd(1., 2.);
+         let m = _mm_cmp_sd_mask(a, b, _CMP_GE_OS);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_mask_cmp_sd_mask() {
+         let a = _mm_setr_pd(2., 1.);
+         let b = _mm_setr_pd(1., 2.);
+         let m = _mm_mask_cmp_sd_mask(0b10, a, b, _CMP_GE_OS);
+         assert_eq!(m, 0);
+         let m = _mm_mask_cmp_sd_mask(0b1, a, b, _CMP_GE_OS);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_cmp_round_sd_mask() {
+         let a = _mm_setr_pd(2., 1.);
+         let b = _mm_setr_pd(1., 2.);
+         let m = _mm_cmp_round_sd_mask(a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm_mask_cmp_round_sd_mask() {
+         let a = _mm_setr_pd(2., 1.);
+         let b = _mm_setr_pd(1., 2.);
+         let m = _mm_mask_cmp_round_sd_mask(0b10, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 0);
+         let m = _mm_mask_cmp_round_sd_mask(0b1, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 1);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmplt_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let m = _mm512_cmplt_epu32_mask(a, b);
+         assert_eq!(m, 0b11001111_11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmplt_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmplt_epu32_mask(mask, a, b);
+         assert_eq!(r, 0b01001010_01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpgt_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let m = _mm512_cmpgt_epu32_mask(b, a);
+         assert_eq!(m, 0b11001111_11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpgt_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpgt_epu32_mask(mask, b, a);
+         assert_eq!(r, 0b01001010_01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmple_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         assert_eq!(
+             _mm512_cmple_epu32_mask(a, b),
+             !_mm512_cmpgt_epu32_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmple_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         assert_eq!(
+             _mm512_mask_cmple_epu32_mask(mask, a, b),
+             0b01111010_01111010
+         );
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpge_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         assert_eq!(
+             _mm512_cmpge_epu32_mask(a, b),
+             !_mm512_cmplt_epu32_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpge_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         assert_eq!(_mm512_mask_cmpge_epu32_mask(mask, a, b), 0b01100000_0110000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpeq_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let m = _mm512_cmpeq_epu32_mask(b, a);
+         assert_eq!(m, 0b11001111_11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpeq_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpeq_epu32_mask(mask, b, a);
+         assert_eq!(r, 0b01001010_01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpneq_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let m = _mm512_cmpneq_epu32_mask(b, a);
+         assert_eq!(m, !_mm512_cmpeq_epu32_mask(b, a));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpneq_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, -100, 100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpneq_epu32_mask(mask, b, a);
+         assert_eq!(r, 0b00110010_00110010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let m = _mm512_cmp_epu32_mask(a, b, _MM_CMPINT_LT);
+         assert_eq!(m, 0b11001111_11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_epu32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmp_epu32_mask(mask, a, b, _MM_CMPINT_LT);
+         assert_eq!(r, 0b01001010_01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmplt_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let m = _mm512_cmplt_epi32_mask(a, b);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmplt_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmplt_epi32_mask(mask, a, b);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpgt_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let m = _mm512_cmpgt_epi32_mask(b, a);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpgt_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmpgt_epi32_mask(mask, b, a);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmple_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         assert_eq!(
+             _mm512_cmple_epi32_mask(a, b),
+             !_mm512_cmpgt_epi32_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmple_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         assert_eq!(_mm512_mask_cmple_epi32_mask(mask, a, b), 0b01100000_0110000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpge_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         assert_eq!(
+             _mm512_cmpge_epi32_mask(a, b),
+             !_mm512_cmplt_epi32_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpge_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, u32::MAX as i32, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01111010_01111010;
+         assert_eq!(
+             _mm512_mask_cmpge_epi32_mask(mask, a, b),
+             0b01111010_01111010
+         );
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpeq_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let m = _mm512_cmpeq_epi32_mask(b, a);
+         assert_eq!(m, 0b11001111_11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpeq_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpeq_epi32_mask(mask, b, a);
+         assert_eq!(r, 0b01001010_01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpneq_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let m = _mm512_cmpneq_epi32_mask(b, a);
+         assert_eq!(m, !_mm512_cmpeq_epi32_mask(b, a));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpneq_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, -100, 100);
+         #[rustfmt::skip]
+         let b = _mm512_set_epi32(0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, 13, 42, i32::MAX, i32::MIN, 100, -100);
+         let mask = 0b01111010_01111010;
+         let r = _mm512_mask_cmpneq_epi32_mask(mask, b, a);
+         assert_eq!(r, 0b00110010_00110010)
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let m = _mm512_cmp_epi32_mask(a, b, _MM_CMPINT_LT);
+         assert_eq!(m, 0b00000101_00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_epi32_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_epi32(0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100,
+                                  0, 1, -1, 13, i32::MAX, i32::MIN, 100, -100);
+         let b = _mm512_set1_epi32(-1);
+         let mask = 0b01100110_01100110;
+         let r = _mm512_mask_cmp_epi32_mask(mask, a, b, _MM_CMPINT_LT);
+         assert_eq!(r, 0b00000100_00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set_epi32() {
+         let r = _mm512_setr_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(
+             r,
+             _mm512_set_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0),
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setr_epi32() {
+         let r = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m512i(
+             r,
+             _mm512_setr_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0),
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set1_epi32() {
+         let r = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, _mm512_set1_epi32(2));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setzero_si512() {
+         assert_eq_m512i(_mm512_set1_epi32(0), _mm512_setzero_si512());
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set_ps() {
+         let r = _mm512_setr_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(
+             r,
+             _mm512_set_ps(
+                 15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+             ),
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setr_ps() {
+         let r = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         assert_eq_m512(
+             r,
+             _mm512_setr_ps(
+                 15., 14., 13., 12., 11., 10., 9., 8., 7., 6., 5., 4., 3., 2., 1., 0.,
+             ),
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set1_ps() {
+         #[rustfmt::skip]
+         let expected = _mm512_set_ps(2., 2., 2., 2., 2., 2., 2., 2.,
+                                      2., 2., 2., 2., 2., 2., 2., 2.);
+         assert_eq_m512(expected, _mm512_set1_ps(2.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setzero_ps() {
+         assert_eq_m512(_mm512_setzero_ps(), _mm512_set1_ps(0.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_loadu_pd() {
+         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
+         let p = a.as_ptr();
+         let r = _mm512_loadu_pd(black_box(p));
+         let e = _mm512_setr_pd(4., 3., 2., 5., 8., 9., 64., 50.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_storeu_pd() {
+         let a = _mm512_set1_pd(9.);
+         let mut r = _mm512_undefined_pd();
+         _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a);
+         assert_eq_m512d(r, a);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_loadu_ps() {
+         let a = &[
+             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
+         ];
+         let p = a.as_ptr();
+         let r = _mm512_loadu_ps(black_box(p));
+         let e = _mm512_setr_ps(
+             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_storeu_ps() {
+         let a = _mm512_set1_ps(9.);
+         let mut r = _mm512_undefined_ps();
+         _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a);
+         assert_eq_m512(r, a);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setr_pd() {
+         let r = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         assert_eq_m512d(r, _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set_pd() {
+         let r = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         assert_eq_m512d(r, _mm512_set_pd(7., 6., 5., 4., 3., 2., 1., 0.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rol_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let r = _mm512_rol_epi32(a, 1);
+         let e = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rol_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let r = _mm512_mask_rol_epi32(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_rol_epi32(a, 0b11111111_11111111, a, 1);
+         let e = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rol_epi32() {
+         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
+         let r = _mm512_maskz_rol_epi32(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_rol_epi32(0b00000000_11111111, a, 1);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_ror_epi32() {
+         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let r = _mm512_ror_epi32(a, 1);
+         let e = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_ror_epi32() {
+         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let r = _mm512_mask_ror_epi32(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_ror_epi32(a, 0b11111111_11111111, a, 1);
+         let e = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_ror_epi32() {
+         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
+         let r = _mm512_maskz_ror_epi32(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_ror_epi32(0b00000000_11111111, a, 1);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_slli_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let r = _mm512_slli_epi32(a, 1);
+         let e = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_slli_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let r = _mm512_mask_slli_epi32(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_slli_epi32(a, 0b11111111_11111111, a, 1);
+         let e = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_slli_epi32() {
+         let a = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
+         let r = _mm512_maskz_slli_epi32(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_slli_epi32(0b00000000_11111111, a, 1);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srli_epi32() {
+         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let r = _mm512_srli_epi32(a, 1);
+         let e = _mm512_set_epi32(0 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srli_epi32() {
+         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let r = _mm512_mask_srli_epi32(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srli_epi32(a, 0b11111111_11111111, a, 1);
+         let e = _mm512_set_epi32(0 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srli_epi32() {
+         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
+         let r = _mm512_maskz_srli_epi32(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srli_epi32(0b00000000_11111111, a, 1);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0 << 31);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rolv_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_rolv_epi32(a, b);
+ 
+         let e = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rolv_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_mask_rolv_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_rolv_epi32(a, 0b11111111_11111111, a, b);
+ 
+         let e = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rolv_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
+         let b = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_maskz_rolv_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_rolv_epi32(0b00000000_11111111, a, b);
+ 
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rorv_epi32() {
+         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let b = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_rorv_epi32(a, b);
+ 
+         let e = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rorv_epi32() {
+         let a = _mm512_set_epi32(1 << 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let b = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_mask_rorv_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_rorv_epi32(a, 0b11111111_11111111, a, b);
+ 
+         let e = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rorv_epi32() {
+         let a = _mm512_set_epi32(3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1 << 0);
+         let b = _mm512_set_epi32(2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_maskz_rorv_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_rorv_epi32(0b00000000_11111111, a, b);
+ 
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sllv_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let count = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_sllv_epi32(a, count);
+ 
+         let e = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sllv_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let count = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_mask_sllv_epi32(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_sllv_epi32(a, 0b11111111_11111111, a, count);
+ 
+         let e = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sllv_epi32() {
+         let a = _mm512_set_epi32(1 << 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 31);
+         let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_maskz_sllv_epi32(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_sllv_epi32(0b00000000_11111111, a, count);
+ 
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srlv_epi32() {
+         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let count = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_srlv_epi32(a, count);
+ 
+         let e = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srlv_epi32() {
+         let a = _mm512_set_epi32(0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+         let count = _mm512_set_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_mask_srlv_epi32(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srlv_epi32(a, 0b11111111_11111111, a, count);
+ 
+         let e = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srlv_epi32() {
+         let a = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0);
+         let count = _mm512_set_epi32(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+ 
+         let r = _mm512_maskz_srlv_epi32(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srlv_epi32(0b00000000_11111111, a, count);
+ 
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sll_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 31,
+             1 << 0,
+             1 << 1,
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         let count = _mm_set_epi32(0, 0, 0, 2);
+         let r = _mm512_sll_epi32(a, count);
+         let e = _mm512_set_epi32(
+             0,
+             1 << 2,
+             1 << 3,
+             1 << 4,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sll_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 31,
+             1 << 0,
+             1 << 1,
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         let count = _mm_set_epi32(0, 0, 0, 2);
+         let r = _mm512_mask_sll_epi32(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_sll_epi32(a, 0b11111111_11111111, a, count);
+         let e = _mm512_set_epi32(
+             0,
+             1 << 2,
+             1 << 3,
+             1 << 4,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sll_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 31,
+             1 << 0,
+             1 << 1,
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 31,
+         );
+         let count = _mm_set_epi32(2, 0, 0, 2);
+         let r = _mm512_maskz_sll_epi32(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_sll_epi32(0b00000000_11111111, a, count);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srl_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 31,
+             1 << 0,
+             1 << 1,
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         let count = _mm_set_epi32(0, 0, 0, 2);
+         let r = _mm512_srl_epi32(a, count);
+         let e = _mm512_set_epi32(1 << 29, 0, 0, 1 << 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srl_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 31,
+             1 << 0,
+             1 << 1,
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+         );
+         let count = _mm_set_epi32(0, 0, 0, 2);
+         let r = _mm512_mask_srl_epi32(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srl_epi32(a, 0b11111111_11111111, a, count);
+         let e = _mm512_set_epi32(1 << 29, 0, 0, 1 << 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srl_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 31,
+             1 << 0,
+             1 << 1,
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 31,
+         );
+         let count = _mm_set_epi32(2, 0, 0, 2);
+         let r = _mm512_maskz_srl_epi32(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srl_epi32(0b00000000_11111111, a, count);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 << 29);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sra_epi32() {
+         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
+         let count = _mm_set_epi32(1, 0, 0, 2);
+         let r = _mm512_sra_epi32(a, count);
+         let e = _mm512_set_epi32(2, -2, 4, -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sra_epi32() {
+         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16);
+         let count = _mm_set_epi32(0, 0, 0, 2);
+         let r = _mm512_mask_sra_epi32(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_sra_epi32(a, 0b11111111_11111111, a, count);
+         let e = _mm512_set_epi32(2, -2, 4, -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sra_epi32() {
+         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -15, -14);
+         let count = _mm_set_epi32(2, 0, 0, 2);
+         let r = _mm512_maskz_sra_epi32(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_sra_epi32(0b00000000_11111111, a, count);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -4, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srav_epi32() {
+         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
+         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm512_srav_epi32(a, count);
+         let e = _mm512_set_epi32(2, -2, 4, -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srav_epi32() {
+         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16);
+         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
+         let r = _mm512_mask_srav_epi32(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srav_epi32(a, 0b11111111_11111111, a, count);
+         let e = _mm512_set_epi32(2, -2, 4, -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srav_epi32() {
+         let a = _mm512_set_epi32(8, -8, 16, -15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -15, -14);
+         let count = _mm512_set_epi32(2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2);
+         let r = _mm512_maskz_srav_epi32(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srav_epi32(0b00000000_11111111, a, count);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -4, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srai_epi32() {
+         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, -15);
+         let r = _mm512_srai_epi32(a, 2);
+         let e = _mm512_set_epi32(2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srai_epi32() {
+         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, -15);
+         let r = _mm512_mask_srai_epi32(a, 0, a, 2);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srai_epi32(a, 0b11111111_11111111, a, 2);
+         let e = _mm512_set_epi32(2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srai_epi32() {
+         let a = _mm512_set_epi32(8, -8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, -15);
+         let r = _mm512_maskz_srai_epi32(0, a, 2);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srai_epi32(0b00000000_11111111, a, 2);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permute_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let r = _mm512_permute_ps(a, 1);
+         let e = _mm512_set_ps(
+             2., 2., 2., 2., 6., 6., 6., 6., 10., 10., 10., 10., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permute_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let r = _mm512_mask_permute_ps(a, 0b00000000_00000000, a, 1);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_permute_ps(a, 0b11111111_11111111, a, 1);
+         let e = _mm512_set_ps(
+             2., 2., 2., 2., 6., 6., 6., 6., 10., 10., 10., 10., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permute_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let r = _mm512_maskz_permute_ps(0, a, 1);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_permute_ps(0b00000000_11111111, a, 1);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 10., 10., 10., 10., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutevar_epi32() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm512_permutevar_epi32(idx, a);
+         let e = _mm512_set1_epi32(14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutevar_epi32() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm512_mask_permutevar_epi32(a, 0, idx, a);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_permutevar_epi32(a, 0b11111111_11111111, idx, a);
+         let e = _mm512_set1_epi32(14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutevar_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_permutevar_ps(a, b);
+         let e = _mm512_set_ps(
+             2., 2., 2., 2., 6., 6., 6., 6., 10., 10., 10., 10., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutevar_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_mask_permutevar_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_permutevar_ps(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set_ps(
+             2., 2., 2., 2., 6., 6., 6., 6., 10., 10., 10., 10., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutevar_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let b = _mm512_set1_epi32(1);
+         let r = _mm512_maskz_permutevar_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_permutevar_ps(0b00000000_11111111, a, b);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 10., 10., 10., 10., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutexvar_epi32() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm512_permutexvar_epi32(idx, a);
+         let e = _mm512_set1_epi32(14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutexvar_epi32() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm512_mask_permutexvar_epi32(a, 0, idx, a);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_permutexvar_epi32(a, 0b11111111_11111111, idx, a);
+         let e = _mm512_set1_epi32(14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutexvar_epi32() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm512_maskz_permutexvar_epi32(0, idx, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_permutexvar_epi32(0b00000000_11111111, idx, a);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 14, 14, 14, 14, 14, 14, 14, 14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutexvar_ps() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let r = _mm512_permutexvar_ps(idx, a);
+         let e = _mm512_set1_ps(14.);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutexvar_ps() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let r = _mm512_mask_permutexvar_ps(a, 0, idx, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_permutexvar_ps(a, 0b11111111_11111111, idx, a);
+         let e = _mm512_set1_ps(14.);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutexvar_ps() {
+         let idx = _mm512_set1_epi32(1);
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let r = _mm512_maskz_permutexvar_ps(0, idx, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_permutexvar_ps(0b00000000_11111111, idx, a);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 14., 14., 14., 14., 14., 14., 14., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutex2var_epi32() {
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_epi32(100);
+         let r = _mm512_permutex2var_epi32(a, idx, b);
+         let e = _mm512_set_epi32(
+             14, 100, 13, 100, 12, 100, 11, 100, 10, 100, 9, 100, 8, 100, 7, 100,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutex2var_epi32() {
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_epi32(100);
+         let r = _mm512_mask_permutex2var_epi32(a, 0, idx, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_permutex2var_epi32(a, 0b11111111_11111111, idx, b);
+         let e = _mm512_set_epi32(
+             14, 100, 13, 100, 12, 100, 11, 100, 10, 100, 9, 100, 8, 100, 7, 100,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutex2var_epi32() {
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_epi32(100);
+         let r = _mm512_maskz_permutex2var_epi32(0, a, idx, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_permutex2var_epi32(0b00000000_11111111, a, idx, b);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 10, 100, 9, 100, 8, 100, 7, 100);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask2_permutex2var_epi32() {
+         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let idx = _mm512_set_epi32(
+             1000,
+             1 << 4,
+             2000,
+             1 << 4,
+             3000,
+             1 << 4,
+             4000,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_epi32(100);
+         let r = _mm512_mask2_permutex2var_epi32(a, idx, 0, b);
+         assert_eq_m512i(r, idx);
+         let r = _mm512_mask2_permutex2var_epi32(a, idx, 0b00000000_11111111, b);
+         let e = _mm512_set_epi32(
+             1000,
+             1 << 4,
+             2000,
+             1 << 4,
+             3000,
+             1 << 4,
+             4000,
+             1 << 4,
+             10,
+             100,
+             9,
+             100,
+             8,
+             100,
+             7,
+             100,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutex2var_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_ps(100.);
+         let r = _mm512_permutex2var_ps(a, idx, b);
+         let e = _mm512_set_ps(
+             14., 100., 13., 100., 12., 100., 11., 100., 10., 100., 9., 100., 8., 100., 7., 100.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutex2var_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_ps(100.);
+         let r = _mm512_mask_permutex2var_ps(a, 0, idx, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_permutex2var_ps(a, 0b11111111_11111111, idx, b);
+         let e = _mm512_set_ps(
+             14., 100., 13., 100., 12., 100., 11., 100., 10., 100., 9., 100., 8., 100., 7., 100.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutex2var_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_ps(100.);
+         let r = _mm512_maskz_permutex2var_ps(0, a, idx, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_permutex2var_ps(0b00000000_11111111, a, idx, b);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 10., 100., 9., 100., 8., 100., 7., 100.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask2_permutex2var_ps() {
+         let a = _mm512_set_ps(
+             0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15.,
+         );
+         let idx = _mm512_set_epi32(
+             1,
+             1 << 4,
+             2,
+             1 << 4,
+             3,
+             1 << 4,
+             4,
+             1 << 4,
+             5,
+             1 << 4,
+             6,
+             1 << 4,
+             7,
+             1 << 4,
+             8,
+             1 << 4,
+         );
+         let b = _mm512_set1_ps(100.);
+         let r = _mm512_mask2_permutex2var_ps(a, idx, 0, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_mask2_permutex2var_ps(a, idx, 0b00000000_11111111, b);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 10., 100., 9., 100., 8., 100., 7., 100.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_epi32() {
+         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
+         let r = _mm512_shuffle_epi32(a, _MM_PERM_AADD);
+         let e = _mm512_setr_epi32(8, 8, 1, 1, 16, 16, 9, 9, 8, 8, 1, 1, 16, 16, 9, 9);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_epi32() {
+         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
+         let r = _mm512_mask_shuffle_epi32(a, 0, a, _MM_PERM_AADD);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_shuffle_epi32(a, 0b11111111_11111111, a, _MM_PERM_AADD);
+         let e = _mm512_setr_epi32(8, 8, 1, 1, 16, 16, 9, 9, 8, 8, 1, 1, 16, 16, 9, 9);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_epi32() {
+         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
+         let r = _mm512_maskz_shuffle_epi32(0, a, _MM_PERM_AADD);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_shuffle_epi32(0b00000000_11111111, a, _MM_PERM_AADD);
+         let e = _mm512_setr_epi32(8, 8, 1, 1, 16, 16, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_ps() {
+         let a = _mm512_setr_ps(
+             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
+         );
+         let b = _mm512_setr_ps(
+             2., 3., 6., 7., 10., 11., 14., 15., 2., 3., 6., 7., 10., 11., 14., 15.,
+         );
+         let r = _mm512_shuffle_ps(a, b, 0x0F);
+         let e = _mm512_setr_ps(
+             8., 8., 2., 2., 16., 16., 10., 10., 8., 8., 2., 2., 16., 16., 10., 10.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_ps() {
+         let a = _mm512_setr_ps(
+             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
+         );
+         let b = _mm512_setr_ps(
+             2., 3., 6., 7., 10., 11., 14., 15., 2., 3., 6., 7., 10., 11., 14., 15.,
+         );
+         let r = _mm512_mask_shuffle_ps(a, 0, a, b, 0x0F);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_shuffle_ps(a, 0b11111111_11111111, a, b, 0x0F);
+         let e = _mm512_setr_ps(
+             8., 8., 2., 2., 16., 16., 10., 10., 8., 8., 2., 2., 16., 16., 10., 10.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_ps() {
+         let a = _mm512_setr_ps(
+             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
+         );
+         let b = _mm512_setr_ps(
+             2., 3., 6., 7., 10., 11., 14., 15., 2., 3., 6., 7., 10., 11., 14., 15.,
+         );
+         let r = _mm512_maskz_shuffle_ps(0, a, b, 0x0F);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_shuffle_ps(0b00000000_11111111, a, b, 0x0F);
+         let e = _mm512_setr_ps(
+             8., 8., 2., 2., 16., 16., 10., 10., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_i32x4() {
+         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm512_shuffle_i32x4(a, b, 0b00000000);
+         let e = _mm512_setr_epi32(1, 4, 5, 8, 1, 4, 5, 8, 2, 3, 6, 7, 2, 3, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_i32x4() {
+         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm512_mask_shuffle_i32x4(a, 0, a, b, 0b00000000);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_shuffle_i32x4(a, 0b11111111_11111111, a, b, 0b00000000);
+         let e = _mm512_setr_epi32(1, 4, 5, 8, 1, 4, 5, 8, 2, 3, 6, 7, 2, 3, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_i32x4() {
+         let a = _mm512_setr_epi32(1, 4, 5, 8, 9, 12, 13, 16, 1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm512_setr_epi32(2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm512_maskz_shuffle_i32x4(0, a, b, 0b00000000);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_shuffle_i32x4(0b00000000_11111111, a, b, 0b00000000);
+         let e = _mm512_setr_epi32(1, 4, 5, 8, 1, 4, 5, 8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_f32x4() {
+         let a = _mm512_setr_ps(
+             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
+         );
+         let b = _mm512_setr_ps(
+             2., 3., 6., 7., 10., 11., 14., 15., 2., 3., 6., 7., 10., 11., 14., 15.,
+         );
+         let r = _mm512_shuffle_f32x4(a, b, 0b00000000);
+         let e = _mm512_setr_ps(
+             1., 4., 5., 8., 1., 4., 5., 8., 2., 3., 6., 7., 2., 3., 6., 7.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_f32x4() {
+         let a = _mm512_setr_ps(
+             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
+         );
+         let b = _mm512_setr_ps(
+             2., 3., 6., 7., 10., 11., 14., 15., 2., 3., 6., 7., 10., 11., 14., 15.,
+         );
+         let r = _mm512_mask_shuffle_f32x4(a, 0, a, b, 0b00000000);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_shuffle_f32x4(a, 0b11111111_11111111, a, b, 0b00000000);
+         let e = _mm512_setr_ps(
+             1., 4., 5., 8., 1., 4., 5., 8., 2., 3., 6., 7., 2., 3., 6., 7.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_f32x4() {
+         let a = _mm512_setr_ps(
+             1., 4., 5., 8., 9., 12., 13., 16., 1., 4., 5., 8., 9., 12., 13., 16.,
+         );
+         let b = _mm512_setr_ps(
+             2., 3., 6., 7., 10., 11., 14., 15., 2., 3., 6., 7., 10., 11., 14., 15.,
+         );
+         let r = _mm512_maskz_shuffle_f32x4(0, a, b, 0b00000000);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_shuffle_f32x4(0b00000000_11111111, a, b, 0b00000000);
+         let e = _mm512_setr_ps(
+             1., 4., 5., 8., 1., 4., 5., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_extractf32x4_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_extractf32x4_ps(a, 0x1);
+         let e = _mm_setr_ps(5., 6., 7., 8.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_moveldup_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_moveldup_ps(a);
+         let e = _mm512_setr_ps(
+             1., 1., 3., 3., 5., 5., 7., 7., 9., 9., 11., 11., 13., 13., 15., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_moveldup_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_mask_moveldup_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_moveldup_ps(a, 0b11111111_11111111, a);
+         let e = _mm512_setr_ps(
+             1., 1., 3., 3., 5., 5., 7., 7., 9., 9., 11., 11., 13., 13., 15., 15.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_moveldup_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_maskz_moveldup_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_moveldup_ps(0b00000000_11111111, a);
+         let e = _mm512_setr_ps(
+             1., 1., 3., 3., 5., 5., 7., 7., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_movehdup_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_movehdup_ps(a);
+         let e = _mm512_setr_ps(
+             2., 2., 4., 4., 6., 6., 8., 8., 10., 10., 12., 12., 14., 14., 16., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_movehdup_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_mask_movehdup_ps(a, 0, a);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_movehdup_ps(a, 0b11111111_11111111, a);
+         let e = _mm512_setr_ps(
+             2., 2., 4., 4., 6., 6., 8., 8., 10., 10., 12., 12., 14., 14., 16., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_movehdup_ps() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let r = _mm512_maskz_movehdup_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_movehdup_ps(0b00000000_11111111, a);
+         let e = _mm512_setr_ps(
+             2., 2., 4., 4., 6., 6., 8., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_inserti32x4() {
+         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm_setr_epi32(17, 18, 19, 20);
+         let r = _mm512_inserti32x4(a, b, 0);
+         let e = _mm512_setr_epi32(17, 18, 19, 20, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_inserti32x4() {
+         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm_setr_epi32(17, 18, 19, 20);
+         let r = _mm512_mask_inserti32x4(a, 0, a, b, 0);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_inserti32x4(a, 0b11111111_11111111, a, b, 0);
+         let e = _mm512_setr_epi32(17, 18, 19, 20, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_inserti32x4() {
+         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm_setr_epi32(17, 18, 19, 20);
+         let r = _mm512_maskz_inserti32x4(0, a, b, 0);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_inserti32x4(0b00000000_11111111, a, b, 0);
+         let e = _mm512_setr_epi32(17, 18, 19, 20, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_insertf32x4() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm_setr_ps(17., 18., 19., 20.);
+         let r = _mm512_insertf32x4(a, b, 0);
+         let e = _mm512_setr_ps(
+             17., 18., 19., 20., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_insertf32x4() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm_setr_ps(17., 18., 19., 20.);
+         let r = _mm512_mask_insertf32x4(a, 0, a, b, 0);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_insertf32x4(a, 0b11111111_11111111, a, b, 0);
+         let e = _mm512_setr_ps(
+             17., 18., 19., 20., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_insertf32x4() {
+         let a = _mm512_setr_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm_setr_ps(17., 18., 19., 20.);
+         let r = _mm512_maskz_insertf32x4(0, a, b, 0);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_insertf32x4(0b00000000_11111111, a, b, 0);
+         let e = _mm512_setr_ps(
+             17., 18., 19., 20., 5., 6., 7., 8., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castps128_ps512() {
+         let a = _mm_setr_ps(17., 18., 19., 20.);
+         let r = _mm512_castps128_ps512(a);
+         let e = _mm512_setr_ps(
+             17., 18., 19., 20., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castps256_ps512() {
+         let a = _mm256_setr_ps(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_castps256_ps512(a);
+         let e = _mm512_setr_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., -1., -1., -1., -1., -1., -1., -1., -1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castps512_ps128() {
+         let a = _mm512_setr_ps(
+             17., 18., 19., 20., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1., -1.,
+         );
+         let r = _mm512_castps512_ps128(a);
+         let e = _mm_setr_ps(17., 18., 19., 20.);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castps512_ps256() {
+         let a = _mm512_setr_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., -1., -1., -1., -1., -1., -1., -1., -1.,
+         );
+         let r = _mm512_castps512_ps256(a);
+         let e = _mm256_setr_ps(17., 18., 19., 20., 21., 22., 23., 24.);
+         assert_eq_m256(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castps_pd() {
+         let a = _mm512_set1_ps(1.);
+         let r = _mm512_castps_pd(a);
+         let e = _mm512_set1_pd(0.007812501848093234);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castps_si512() {
+         let a = _mm512_set1_ps(1.);
+         let r = _mm512_castps_si512(a);
+         let e = _mm512_set1_epi32(1065353216);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcastd_epi32() {
+         let a = _mm_set_epi32(17, 18, 19, 20);
+         let r = _mm512_broadcastd_epi32(a);
+         let e = _mm512_set1_epi32(20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcastd_epi32() {
+         let src = _mm512_set1_epi32(20);
+         let a = _mm_set_epi32(17, 18, 19, 20);
+         let r = _mm512_mask_broadcastd_epi32(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_broadcastd_epi32(src, 0b11111111_11111111, a);
+         let e = _mm512_set1_epi32(20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcastd_epi32() {
+         let a = _mm_set_epi32(17, 18, 19, 20);
+         let r = _mm512_maskz_broadcastd_epi32(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_broadcastd_epi32(0b00000000_11111111, a);
+         let e = _mm512_setr_epi32(20, 20, 20, 20, 20, 20, 20, 20, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcastss_ps() {
+         let a = _mm_set_ps(17., 18., 19., 20.);
+         let r = _mm512_broadcastss_ps(a);
+         let e = _mm512_set1_ps(20.);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcastss_ps() {
+         let src = _mm512_set1_ps(20.);
+         let a = _mm_set_ps(17., 18., 19., 20.);
+         let r = _mm512_mask_broadcastss_ps(src, 0, a);
+         assert_eq_m512(r, src);
+         let r = _mm512_mask_broadcastss_ps(src, 0b11111111_11111111, a);
+         let e = _mm512_set1_ps(20.);
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcastss_ps() {
+         let a = _mm_set_ps(17., 18., 19., 20.);
+         let r = _mm512_maskz_broadcastss_ps(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_broadcastss_ps(0b00000000_11111111, a);
+         let e = _mm512_setr_ps(
+             20., 20., 20., 20., 20., 20., 20., 20., 0., 0., 0., 0., 0., 0., 0., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcast_i32x4() {
+         let a = _mm_set_epi32(17, 18, 19, 20);
+         let r = _mm512_broadcast_i32x4(a);
+         let e = _mm512_set_epi32(
+             17, 18, 19, 20, 17, 18, 19, 20, 17, 18, 19, 20, 17, 18, 19, 20,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcast_i32x4() {
+         let src = _mm512_set1_epi32(20);
+         let a = _mm_set_epi32(17, 18, 19, 20);
+         let r = _mm512_mask_broadcast_i32x4(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_broadcast_i32x4(src, 0b11111111_11111111, a);
+         let e = _mm512_set_epi32(
+             17, 18, 19, 20, 17, 18, 19, 20, 17, 18, 19, 20, 17, 18, 19, 20,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcast_i32x4() {
+         let a = _mm_set_epi32(17, 18, 19, 20);
+         let r = _mm512_maskz_broadcast_i32x4(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_broadcast_i32x4(0b00000000_11111111, a);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 17, 18, 19, 20, 17, 18, 19, 20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcast_f32x4() {
+         let a = _mm_set_ps(17., 18., 19., 20.);
+         let r = _mm512_broadcast_f32x4(a);
+         let e = _mm512_set_ps(
+             17., 18., 19., 20., 17., 18., 19., 20., 17., 18., 19., 20., 17., 18., 19., 20.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcast_f32x4() {
+         let src = _mm512_set1_ps(20.);
+         let a = _mm_set_ps(17., 18., 19., 20.);
+         let r = _mm512_mask_broadcast_f32x4(src, 0, a);
+         assert_eq_m512(r, src);
+         let r = _mm512_mask_broadcast_f32x4(src, 0b11111111_11111111, a);
+         let e = _mm512_set_ps(
+             17., 18., 19., 20., 17., 18., 19., 20., 17., 18., 19., 20., 17., 18., 19., 20.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcast_f32x4() {
+         let a = _mm_set_ps(17., 18., 19., 20.);
+         let r = _mm512_maskz_broadcast_f32x4(0, a);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_broadcast_f32x4(0b00000000_11111111, a);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 17., 18., 19., 20., 17., 18., 19., 20.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_blend_epi32() {
+         let a = _mm512_set1_epi32(1);
+         let b = _mm512_set1_epi32(2);
+         let r = _mm512_mask_blend_epi32(0b11111111_00000000, a, b);
+         let e = _mm512_set_epi32(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_blend_ps() {
+         let a = _mm512_set1_ps(1.);
+         let b = _mm512_set1_ps(2.);
+         let r = _mm512_mask_blend_ps(0b11111111_00000000, a, b);
+         let e = _mm512_set_ps(
+             2., 2., 2., 2., 2., 2., 2., 2., 1., 1., 1., 1., 1., 1., 1., 1.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpackhi_epi32() {
+         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm512_set_epi32(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm512_unpackhi_epi32(a, b);
+         let e = _mm512_set_epi32(17, 1, 18, 2, 21, 5, 22, 6, 25, 9, 26, 10, 29, 13, 30, 14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpackhi_epi32() {
+         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm512_set_epi32(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm512_mask_unpackhi_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_unpackhi_epi32(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set_epi32(17, 1, 18, 2, 21, 5, 22, 6, 25, 9, 26, 10, 29, 13, 30, 14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpackhi_epi32() {
+         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm512_set_epi32(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm512_maskz_unpackhi_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_unpackhi_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 25, 9, 26, 10, 29, 13, 30, 14);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpackhi_ps() {
+         let a = _mm512_set_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm512_set_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
+         );
+         let r = _mm512_unpackhi_ps(a, b);
+         let e = _mm512_set_ps(
+             17., 1., 18., 2., 21., 5., 22., 6., 25., 9., 26., 10., 29., 13., 30., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpackhi_ps() {
+         let a = _mm512_set_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm512_set_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
+         );
+         let r = _mm512_mask_unpackhi_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_unpackhi_ps(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set_ps(
+             17., 1., 18., 2., 21., 5., 22., 6., 25., 9., 26., 10., 29., 13., 30., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpackhi_ps() {
+         let a = _mm512_set_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm512_set_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
+         );
+         let r = _mm512_maskz_unpackhi_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_unpackhi_ps(0b00000000_11111111, a, b);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 25., 9., 26., 10., 29., 13., 30., 14.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpacklo_epi32() {
+         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm512_set_epi32(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm512_unpacklo_epi32(a, b);
+         let e = _mm512_set_epi32(19, 3, 20, 4, 23, 7, 24, 8, 27, 11, 28, 12, 31, 15, 32, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpacklo_epi32() {
+         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm512_set_epi32(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm512_mask_unpacklo_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_unpacklo_epi32(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set_epi32(19, 3, 20, 4, 23, 7, 24, 8, 27, 11, 28, 12, 31, 15, 32, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpacklo_epi32() {
+         let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let b = _mm512_set_epi32(
+             17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+         );
+         let r = _mm512_maskz_unpacklo_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_unpacklo_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 27, 11, 28, 12, 31, 15, 32, 16);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpacklo_ps() {
+         let a = _mm512_set_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm512_set_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
+         );
+         let r = _mm512_unpacklo_ps(a, b);
+         let e = _mm512_set_ps(
+             19., 3., 20., 4., 23., 7., 24., 8., 27., 11., 28., 12., 31., 15., 32., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpacklo_ps() {
+         let a = _mm512_set_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm512_set_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
+         );
+         let r = _mm512_mask_unpacklo_ps(a, 0, a, b);
+         assert_eq_m512(r, a);
+         let r = _mm512_mask_unpacklo_ps(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set_ps(
+             19., 3., 20., 4., 23., 7., 24., 8., 27., 11., 28., 12., 31., 15., 32., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpacklo_ps() {
+         let a = _mm512_set_ps(
+             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
+         );
+         let b = _mm512_set_ps(
+             17., 18., 19., 20., 21., 22., 23., 24., 25., 26., 27., 28., 29., 30., 31., 32.,
+         );
+         let r = _mm512_maskz_unpacklo_ps(0, a, b);
+         assert_eq_m512(r, _mm512_setzero_ps());
+         let r = _mm512_maskz_unpacklo_ps(0b00000000_11111111, a, b);
+         let e = _mm512_set_ps(
+             0., 0., 0., 0., 0., 0., 0., 0., 27., 11., 28., 12., 31., 15., 32., 16.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_and_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_and_epi32(a, b);
+         let e = _mm512_set_epi32(1 << 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_and_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_mask_and_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_and_epi32(a, 0b01111111_11111111, a, b);
+         let e = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_and_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_maskz_and_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_and_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_and_si512() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_and_epi32(a, b);
+         let e = _mm512_set_epi32(1 << 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_or_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_or_epi32(a, b);
+         let e = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_or_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_mask_or_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_or_epi32(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_or_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_maskz_or_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_or_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_set_epi32(
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_or_si512() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_or_epi32(a, b);
+         let e = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_xor_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_xor_epi32(a, b);
+         let e = _mm512_set_epi32(
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_xor_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_mask_xor_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_xor_epi32(a, 0b01111111_11111111, a, b);
+         let e = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_xor_epi32() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_maskz_xor_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_xor_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_xor_si512() {
+         let a = _mm512_set_epi32(
+             1 << 1 | 1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 3,
+         );
+         let b = _mm512_set_epi32(
+             1 << 1,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+         );
+         let r = _mm512_xor_epi32(a, b);
+         let e = _mm512_set_epi32(
+             1 << 2,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_andnot_epi32() {
+         let a = _mm512_set1_epi32(0);
+         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
+         let r = _mm512_andnot_epi32(a, b);
+         let e = _mm512_set1_epi32(1 << 3 | 1 << 4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_andnot_epi32() {
+         let a = _mm512_set1_epi32(1 << 1 | 1 << 2);
+         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
+         let r = _mm512_mask_andnot_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_andnot_epi32(a, 0b11111111_11111111, a, b);
+         let e = _mm512_set1_epi32(1 << 3 | 1 << 4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_andnot_epi32() {
+         let a = _mm512_set1_epi32(1 << 1 | 1 << 2);
+         let b = _mm512_set1_epi32(1 << 3 | 1 << 4);
+         let r = _mm512_maskz_andnot_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_andnot_epi32(0b00000000_11111111, a, b);
+         let e = _mm512_set_epi32(
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_kand() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b11001100_00110011;
+         let r = _mm512_kand(a, b);
+         let e: u16 = 0b11001100_00110011;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_kand_mask16() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b11001100_00110011;
+         let r = _kand_mask16(a, b);
+         let e: u16 = 0b11001100_00110011;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_kor() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _mm512_kor(a, b);
+         let e: u16 = 0b11101110_00111011;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_kor_mask16() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _kor_mask16(a, b);
+         let e: u16 = 0b11101110_00111011;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_kxor() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _mm512_kxor(a, b);
+         let e: u16 = 0b11100010_00111000;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_kxor_mask16() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _kxor_mask16(a, b);
+         let e: u16 = 0b11100010_00111000;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_knot() {
+         let a: u16 = 0b11001100_00110011;
+         let r = _mm512_knot(a);
+         let e: u16 = 0b00110011_11001100;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_knot_mask16() {
+         let a: u16 = 0b11001100_00110011;
+         let r = _knot_mask16(a);
+         let e: u16 = 0b00110011_11001100;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_kandn() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _mm512_kandn(a, b);
+         let e: u16 = 0b00100010_00001000;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_kandn_mask16() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _kandn_mask16(a, b);
+         let e: u16 = 0b00100010_00001000;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_kxnor() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _mm512_kxnor(a, b);
+         let e: u16 = 0b00011101_11000111;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_kxnor_mask16() {
+         let a: u16 = 0b11001100_00110011;
+         let b: u16 = 0b00101110_00001011;
+         let r = _kxnor_mask16(a, b);
+         let e: u16 = 0b00011101_11000111;
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_kmov() {
+         let a: u16 = 0b11001100_00110011;
+         let r = _mm512_kmov(a);
+         let e: u16 = 0b11001100_00110011;
+         assert_eq!(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,196 ----
+ use crate::core_arch::x86::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Multiply packed unsigned 52-bit integers in each 64-bit element of
+ /// `b` and `c` to form a 104-bit intermediate result. Add the high 52-bit
+ /// unsigned integer from the intermediate result with the
+ /// corresponding unsigned 64-bit integer in `a`, and store the
+ /// results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#avx512techs=AVX512IFMA52&expand=3488)
+ #[inline]
+ #[target_feature(enable = "avx512ifma")]
+ #[cfg_attr(test, assert_instr(vpmadd52huq))]
+ pub unsafe fn _mm512_madd52hi_epu64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+     vpmadd52huq_512(a, b, c)
+ }
+ 
+ /// Multiply packed unsigned 52-bit integers in each 64-bit element of
+ /// `b` and `c` to form a 104-bit intermediate result. Add the low 52-bit
+ /// unsigned integer from the intermediate result with the
+ /// corresponding unsigned 64-bit integer in `a`, and store the
+ /// results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=3497&avx512techs=AVX512IFMA52)
+ #[inline]
+ #[target_feature(enable = "avx512ifma")]
+ #[cfg_attr(test, assert_instr(vpmadd52luq))]
+ pub unsafe fn _mm512_madd52lo_epu64(a: __m512i, b: __m512i, c: __m512i) -> __m512i {
+     vpmadd52luq_512(a, b, c)
+ }
+ 
+ /// Multiply packed unsigned 52-bit integers in each 64-bit element of
+ /// `b` and `c` to form a 104-bit intermediate result. Add the high 52-bit
+ /// unsigned integer from the intermediate result with the
+ /// corresponding unsigned 64-bit integer in `a`, and store the
+ /// results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=vpmadd52&avx512techs=AVX512IFMA52,AVX512VL&expand=3485)
+ #[inline]
+ #[target_feature(enable = "avx512ifma,avx512vl")]
+ #[cfg_attr(test, assert_instr(vpmadd52huq))]
+ pub unsafe fn _mm256_madd52hi_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+     vpmadd52huq_256(a, b, c)
+ }
+ 
+ /// Multiply packed unsigned 52-bit integers in each 64-bit element of
+ /// `b` and `c` to form a 104-bit intermediate result. Add the low 52-bit
+ /// unsigned integer from the intermediate result with the
+ /// corresponding unsigned 64-bit integer in `a`, and store the
+ /// results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=vpmadd52&avx512techs=AVX512IFMA52,AVX512VL&expand=3494)
+ #[inline]
+ #[target_feature(enable = "avx512ifma,avx512vl")]
+ #[cfg_attr(test, assert_instr(vpmadd52luq))]
+ pub unsafe fn _mm256_madd52lo_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
+     vpmadd52luq_256(a, b, c)
+ }
+ 
+ /// Multiply packed unsigned 52-bit integers in each 64-bit element of
+ /// `b` and `c` to form a 104-bit intermediate result. Add the high 52-bit
+ /// unsigned integer from the intermediate result with the
+ /// corresponding unsigned 64-bit integer in `a`, and store the
+ /// results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=3488,3482&text=vpmadd52&avx512techs=AVX512IFMA52,AVX512VL)
+ #[inline]
+ #[target_feature(enable = "avx512ifma,avx512vl")]
+ #[cfg_attr(test, assert_instr(vpmadd52huq))]
+ pub unsafe fn _mm_madd52hi_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+     vpmadd52huq_128(a, b, c)
+ }
+ 
+ /// Multiply packed unsigned 52-bit integers in each 64-bit element of
+ /// `b` and `c` to form a 104-bit intermediate result. Add the low 52-bit
+ /// unsigned integer from the intermediate result with the
+ /// corresponding unsigned 64-bit integer in `a`, and store the
+ /// results in `dst`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=3488,3491&text=vpmadd52&avx512techs=AVX512IFMA52,AVX512VL)
+ #[inline]
+ #[target_feature(enable = "avx512ifma,avx512vl")]
+ #[cfg_attr(test, assert_instr(vpmadd52luq))]
+ pub unsafe fn _mm_madd52lo_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
+     vpmadd52luq_128(a, b, c)
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.avx512.vpmadd52l.uq.128"]
+     fn vpmadd52luq_128(z: __m128i, x: __m128i, y: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.avx512.vpmadd52h.uq.128"]
+     fn vpmadd52huq_128(z: __m128i, x: __m128i, y: __m128i) -> __m128i;
+     #[link_name = "llvm.x86.avx512.vpmadd52l.uq.256"]
+     fn vpmadd52luq_256(z: __m256i, x: __m256i, y: __m256i) -> __m256i;
+     #[link_name = "llvm.x86.avx512.vpmadd52h.uq.256"]
+     fn vpmadd52huq_256(z: __m256i, x: __m256i, y: __m256i) -> __m256i;
+     #[link_name = "llvm.x86.avx512.vpmadd52l.uq.512"]
+     fn vpmadd52luq_512(z: __m512i, x: __m512i, y: __m512i) -> __m512i;
+     #[link_name = "llvm.x86.avx512.vpmadd52h.uq.512"]
+     fn vpmadd52huq_512(z: __m512i, x: __m512i, y: __m512i) -> __m512i;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std;
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "avx512ifma")]
+     unsafe fn test_mm512_madd52hi_epu64() {
+         let mut a = _mm512_set1_epi64(10 << 40);
+         let b = _mm512_set1_epi64((11 << 40) + 4);
+         let c = _mm512_set1_epi64((12 << 40) + 3);
+ 
+         a = _mm512_madd52hi_epu64(a, b, c);
+ 
+         // (10 << 40) + ((((11 << 40) + 4) * ((12 << 40) + 3)) >> 52)
+         let expected = _mm512_set1_epi64(11030549757952);
+ 
+         assert_eq_m512i(a, expected);
+     }
+ 
+     #[simd_test(enable = "avx512ifma")]
+     unsafe fn test_mm512_madd52lo_epu64() {
+         let mut a = _mm512_set1_epi64(10 << 40);
+         let b = _mm512_set1_epi64((11 << 40) + 4);
+         let c = _mm512_set1_epi64((12 << 40) + 3);
+ 
+         a = _mm512_madd52lo_epu64(a, b, c);
+ 
+         // (10 << 40) + ((((11 << 40) + 4) * ((12 << 40) + 3)) % (1 << 52))
+         let expected = _mm512_set1_epi64(100055558127628);
+ 
+         assert_eq_m512i(a, expected);
+     }
+ 
+     #[simd_test(enable = "avx512ifma,avx512vl")]
+     unsafe fn test_mm256_madd52hi_epu64() {
+         let mut a = _mm256_set1_epi64x(10 << 40);
+         let b = _mm256_set1_epi64x((11 << 40) + 4);
+         let c = _mm256_set1_epi64x((12 << 40) + 3);
+ 
+         a = _mm256_madd52hi_epu64(a, b, c);
+ 
+         // (10 << 40) + ((((11 << 40) + 4) * ((12 << 40) + 3)) >> 52)
+         let expected = _mm256_set1_epi64x(11030549757952);
+ 
+         assert_eq_m256i(a, expected);
+     }
+ 
+     #[simd_test(enable = "avx512ifma,avx512vl")]
+     unsafe fn test_mm256_madd52lo_epu64() {
+         let mut a = _mm256_set1_epi64x(10 << 40);
+         let b = _mm256_set1_epi64x((11 << 40) + 4);
+         let c = _mm256_set1_epi64x((12 << 40) + 3);
+ 
+         a = _mm256_madd52lo_epu64(a, b, c);
+ 
+         // (10 << 40) + ((((11 << 40) + 4) * ((12 << 40) + 3)) % (1 << 52))
+         let expected = _mm256_set1_epi64x(100055558127628);
+ 
+         assert_eq_m256i(a, expected);
+     }
+ 
+     #[simd_test(enable = "avx512ifma,avx512vl")]
+     unsafe fn test_mm_madd52hi_epu64() {
+         let mut a = _mm_set1_epi64x(10 << 40);
+         let b = _mm_set1_epi64x((11 << 40) + 4);
+         let c = _mm_set1_epi64x((12 << 40) + 3);
+ 
+         a = _mm_madd52hi_epu64(a, b, c);
+ 
+         // (10 << 40) + ((((11 << 40) + 4) * ((12 << 40) + 3)) >> 52)
+         let expected = _mm_set1_epi64x(11030549757952);
+ 
+         assert_eq_m128i(a, expected);
+     }
+ 
+     #[simd_test(enable = "avx512ifma,avx512vl")]
+     unsafe fn test_mm_madd52lo_epu64() {
+         let mut a = _mm_set1_epi64x(10 << 40);
+         let b = _mm_set1_epi64x((11 << 40) + 4);
+         let c = _mm_set1_epi64x((12 << 40) + 3);
+ 
+         a = _mm_madd52hi_epu64(a, b, c);
+ 
+         // (10 << 40) + ((((11 << 40) + 4) * ((12 << 40) + 3)) >> 52)
+         let expected = _mm_set1_epi64x(11030549757952);
+ 
+         assert_eq_m128i(a, expected);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi1.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi1.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi1.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi1.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,178 ----
+ //! Bit Manipulation Instruction (BMI) Set 1.0.
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
+ //! available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [wikipedia_bmi]: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Extracts bits in range [`start`, `start` + `length`) from `a` into
+ /// the least significant bits of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(bextr))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
+     _bextr2_u32(a, (start & 0xff_u32) | ((len & 0xff_u32) << 8_u32))
+ }
+ 
+ /// Extracts bits of `a` specified by `control` into
+ /// the least significant bits of the result.
+ ///
+ /// Bits `[7,0]` of `control` specify the index to the first bit in the range
+ /// to be extracted, and bits `[15,8]` specify the length of the range.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr2_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(bextr))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bextr2_u32(a: u32, control: u32) -> u32 {
+     x86_bmi_bextr_32(a, control)
+ }
+ 
+ /// Bitwise logical `AND` of inverted `a` with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_andn_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(andn))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _andn_u32(a: u32, b: u32) -> u32 {
+     !a & b
+ }
+ 
+ /// Extracts lowest set isolated bit.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsi_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(blsi))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsi_u32(x: u32) -> u32 {
+     x & x.wrapping_neg()
+ }
+ 
+ /// Gets mask up to lowest set bit.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsmsk_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(blsmsk))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
+     x ^ (x.wrapping_sub(1_u32))
+ }
+ 
+ /// Resets the lowest set bit of `x`.
+ ///
+ /// If `x` is sets CF.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsr_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(blsr))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsr_u32(x: u32) -> u32 {
+     x & (x.wrapping_sub(1))
+ }
+ 
+ /// Counts the number of trailing least significant zero bits.
+ ///
+ /// When the source operand is `0`, it returns its size in bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_tzcnt_u32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(tzcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _tzcnt_u32(x: u32) -> u32 {
+     x.trailing_zeros()
+ }
+ 
+ /// Counts the number of trailing least significant zero bits.
+ ///
+ /// When the source operand is `0`, it returns its size in bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_tzcnt_32)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(tzcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_tzcnt_32(x: u32) -> i32 {
+     x.trailing_zeros() as i32
+ }
+ 
+ extern "C" {
+     #[link_name = "llvm.x86.bmi.bextr.32"]
+     fn x86_bmi_bextr_32(x: u32, y: u32) -> u32;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_bextr_u32() {
+         let r = _bextr_u32(0b0101_0000u32, 4, 4);
+         assert_eq!(r, 0b0000_0101u32);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_andn_u32() {
+         assert_eq!(_andn_u32(0, 0), 0);
+         assert_eq!(_andn_u32(0, 1), 1);
+         assert_eq!(_andn_u32(1, 0), 0);
+         assert_eq!(_andn_u32(1, 1), 0);
+ 
+         let r = _andn_u32(0b0000_0000u32, 0b0000_0000u32);
+         assert_eq!(r, 0b0000_0000u32);
+ 
+         let r = _andn_u32(0b0000_0000u32, 0b1111_1111u32);
+         assert_eq!(r, 0b1111_1111u32);
+ 
+         let r = _andn_u32(0b1111_1111u32, 0b0000_0000u32);
+         assert_eq!(r, 0b0000_0000u32);
+ 
+         let r = _andn_u32(0b1111_1111u32, 0b1111_1111u32);
+         assert_eq!(r, 0b0000_0000u32);
+ 
+         let r = _andn_u32(0b0100_0000u32, 0b0101_1101u32);
+         assert_eq!(r, 0b0001_1101u32);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_blsi_u32() {
+         assert_eq!(_blsi_u32(0b1101_0000u32), 0b0001_0000u32);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_blsmsk_u32() {
+         let r = _blsmsk_u32(0b0011_0000u32);
+         assert_eq!(r, 0b0001_1111u32);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_blsr_u32() {
+         // TODO: test the behavior when the input is `0`.
+         let r = _blsr_u32(0b0011_0000u32);
+         assert_eq!(r, 0b0010_0000u32);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_tzcnt_u32() {
+         assert_eq!(_tzcnt_u32(0b0000_0001u32), 0u32);
+         assert_eq!(_tzcnt_u32(0b0000_0000u32), 32u32);
+         assert_eq!(_tzcnt_u32(0b1001_0000u32), 4u32);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi2.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi2.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bmi2.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,133 ----
+ //! Bit Manipulation Instruction (BMI) Set 2.0.
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
+ //! available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [wikipedia_bmi]:
+ //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Unsigned multiply without affecting flags.
+ ///
+ /// Unsigned multiplication of `a` with `b` returning a pair `(lo, hi)` with
+ /// the low half and the high half of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mulx_u32)
+ #[inline]
+ // LLVM BUG (should be mulxl): https://bugs.llvm.org/show_bug.cgi?id=34232
+ #[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(imul))]
+ #[cfg_attr(all(test, target_arch = "x86"), assert_instr(mul))]
+ #[target_feature(enable = "bmi2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mulx_u32(a: u32, b: u32, hi: &mut u32) -> u32 {
+     let result: u64 = (a as u64) * (b as u64);
+     *hi = (result >> 32) as u32;
+     result as u32
+ }
+ 
+ /// Zeroes higher bits of `a` >= `index`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bzhi_u32)
+ #[inline]
+ #[target_feature(enable = "bmi2")]
+ #[cfg_attr(test, assert_instr(bzhi))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bzhi_u32(a: u32, index: u32) -> u32 {
+     x86_bmi2_bzhi_32(a, index)
+ }
+ 
+ /// Scatter contiguous low order bits of `a` to the result at the positions
+ /// specified by the `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_pdep_u32)
+ #[inline]
+ #[target_feature(enable = "bmi2")]
+ #[cfg_attr(test, assert_instr(pdep))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _pdep_u32(a: u32, mask: u32) -> u32 {
+     x86_bmi2_pdep_32(a, mask)
+ }
+ 
+ /// Gathers the bits of `x` specified by the `mask` into the contiguous low
+ /// order bit positions of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_pext_u32)
+ #[inline]
+ #[target_feature(enable = "bmi2")]
+ #[cfg_attr(test, assert_instr(pext))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _pext_u32(a: u32, mask: u32) -> u32 {
+     x86_bmi2_pext_32(a, mask)
+ }
+ 
+ extern "C" {
+     #[link_name = "llvm.x86.bmi.bzhi.32"]
+     fn x86_bmi2_bzhi_32(x: u32, y: u32) -> u32;
+     #[link_name = "llvm.x86.bmi.pdep.32"]
+     fn x86_bmi2_pdep_32(x: u32, y: u32) -> u32;
+     #[link_name = "llvm.x86.bmi.pext.32"]
+     fn x86_bmi2_pext_32(x: u32, y: u32) -> u32;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_pext_u32() {
+         let n = 0b1011_1110_1001_0011u32;
+ 
+         let m0 = 0b0110_0011_1000_0101u32;
+         let s0 = 0b0000_0000_0011_0101u32;
+ 
+         let m1 = 0b1110_1011_1110_1111u32;
+         let s1 = 0b0001_0111_0100_0011u32;
+ 
+         assert_eq!(_pext_u32(n, m0), s0);
+         assert_eq!(_pext_u32(n, m1), s1);
+     }
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_pdep_u32() {
+         let n = 0b1011_1110_1001_0011u32;
+ 
+         let m0 = 0b0110_0011_1000_0101u32;
+         let s0 = 0b0000_0010_0000_0101u32;
+ 
+         let m1 = 0b1110_1011_1110_1111u32;
+         let s1 = 0b1110_1001_0010_0011u32;
+ 
+         assert_eq!(_pdep_u32(n, m0), s0);
+         assert_eq!(_pdep_u32(n, m1), s1);
+     }
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_bzhi_u32() {
+         let n = 0b1111_0010u32;
+         let s = 0b0001_0010u32;
+         assert_eq!(_bzhi_u32(n, 5), s);
+     }
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_mulx_u32() {
+         let a: u32 = 4_294_967_200;
+         let b: u32 = 2;
+         let mut hi = 0;
+         let lo = _mulx_u32(a, b, &mut hi);
+         /*
+         result = 8589934400
+                = 0b0001_1111_1111_1111_1111_1111_1111_0100_0000u64
+                    ^~hi ^~lo~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                 */
+         assert_eq!(lo, 0b1111_1111_1111_1111_1111_1111_0100_0000u32);
+         assert_eq!(hi, 0b0001u32);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bswap.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bswap.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bswap.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bswap.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,28 ----
+ //! Byte swap intrinsics.
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Returns an integer with the reversed byte order of x
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bswap)
+ #[inline]
+ #[cfg_attr(test, assert_instr(bswap))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bswap(x: i32) -> i32 {
+     x.swap_bytes()
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use super::*;
+ 
+     #[test]
+     fn test_bswap() {
+         unsafe {
+             assert_eq!(_bswap(0x0EADBE0F), 0x0FBEAD0E);
+             assert_eq!(_bswap(0x00000000), 0x00000000);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bt.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bt.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bt.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/bt.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,102 ----
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(bt))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittest(p: *const i32, b: i32) -> u8 {
+     let r: u8;
+     llvm_asm!("btl $2, $1\n\tsetc ${0:b}"
+               : "=r"(r)
+               : "*m"(p), "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`, then sets the bit to `1`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(bts))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittestandset(p: *mut i32, b: i32) -> u8 {
+     let r: u8;
+     llvm_asm!("btsl $2, $1\n\tsetc ${0:b}"
+               : "=r"(r), "+*m"(p)
+               : "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`, then resets that bit to `0`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(btr))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittestandreset(p: *mut i32, b: i32) -> u8 {
+     let r: u8;
+     llvm_asm!("btrl $2, $1\n\tsetc ${0:b}"
+               : "=r"(r), "+*m"(p)
+               : "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`, then inverts that bit.
+ #[inline]
+ #[cfg_attr(test, assert_instr(btc))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittestandcomplement(p: *mut i32, b: i32) -> u8 {
+     let r: u8;
+     llvm_asm!("btcl $2, $1\n\tsetc ${0:b}"
+               : "=r"(r), "+*m"(p)
+               : "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+ 
+     #[test]
+     fn test_bittest() {
+         unsafe {
+             let a = 0b0101_0000i32;
+             assert_eq!(_bittest(&a as _, 4), 1);
+             assert_eq!(_bittest(&a as _, 5), 0);
+         }
+     }
+ 
+     #[test]
+     fn test_bittestandset() {
+         unsafe {
+             let mut a = 0b0101_0000i32;
+             assert_eq!(_bittestandset(&mut a as _, 4), 1);
+             assert_eq!(_bittestandset(&mut a as _, 4), 1);
+             assert_eq!(_bittestandset(&mut a as _, 5), 0);
+             assert_eq!(_bittestandset(&mut a as _, 5), 1);
+         }
+     }
+ 
+     #[test]
+     fn test_bittestandreset() {
+         unsafe {
+             let mut a = 0b0101_0000i32;
+             assert_eq!(_bittestandreset(&mut a as _, 4), 1);
+             assert_eq!(_bittestandreset(&mut a as _, 4), 0);
+             assert_eq!(_bittestandreset(&mut a as _, 5), 0);
+             assert_eq!(_bittestandreset(&mut a as _, 5), 0);
+         }
+     }
+ 
+     #[test]
+     fn test_bittestandcomplement() {
+         unsafe {
+             let mut a = 0b0101_0000i32;
+             assert_eq!(_bittestandcomplement(&mut a as _, 4), 1);
+             assert_eq!(_bittestandcomplement(&mut a as _, 4), 0);
+             assert_eq!(_bittestandcomplement(&mut a as _, 4), 1);
+             assert_eq!(_bittestandcomplement(&mut a as _, 5), 0);
+             assert_eq!(_bittestandcomplement(&mut a as _, 5), 1);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/cpuid.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/cpuid.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/cpuid.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/cpuid.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,193 ----
+ //! `cpuid` intrinsics
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Result of the `cpuid` instruction.
+ #[allow(clippy::missing_inline_in_public_items)]
+ // ^^ the derived impl of Debug for CpuidResult is not #[inline] and that's OK.
+ #[derive(Copy, Clone, Debug, Eq, Ord, PartialEq, PartialOrd)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub struct CpuidResult {
+     /// EAX register.
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub eax: u32,
+     /// EBX register.
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub ebx: u32,
+     /// ECX register.
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub ecx: u32,
+     /// EDX register.
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub edx: u32,
+ }
+ 
+ /// Returns the result of the `cpuid` instruction for a given `leaf` (`EAX`)
+ /// and
+ /// `sub_leaf` (`ECX`).
+ ///
+ /// The highest-supported leaf value is returned by the first tuple argument of
+ /// [`__get_cpuid_max(0)`](fn.__get_cpuid_max.html). For leaves containung
+ /// sub-leaves, the second tuple argument returns the highest-supported
+ /// sub-leaf
+ /// value.
+ ///
+ /// The [CPUID Wikipedia page][wiki_cpuid] contains how to query which
+ /// information using the `EAX` and `ECX` registers, and the interpretation of
+ /// the results returned in `EAX`, `EBX`, `ECX`, and `EDX`.
+ ///
+ /// The references are:
+ /// - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ ///   Instruction Set Reference, A-Z][intel64_ref].
+ /// - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ ///   System Instructions][amd64_ref].
+ ///
+ /// [wiki_cpuid]: https://en.wikipedia.org/wiki/CPUID
+ /// [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ /// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ #[inline]
+ #[cfg_attr(test, assert_instr(cpuid))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn __cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
+     let eax;
+     let ebx;
+     let ecx;
+     let edx;
+     #[cfg(target_arch = "x86")]
+     {
+         llvm_asm!("cpuid"
+                   : "={eax}"(eax), "={ebx}"(ebx), "={ecx}"(ecx), "={edx}"(edx)
+                   : "{eax}"(leaf), "{ecx}"(sub_leaf)
+                   : :);
+     }
+     #[cfg(target_arch = "x86_64")]
+     {
+         // x86-64 uses %rbx as the base register, so preserve it.
+         // This works around a bug in LLVM with ASAN enabled:
+         // https://bugs.llvm.org/show_bug.cgi?id=17907
+         llvm_asm!(r#"
+                   mov %rbx, %rsi
+                   cpuid
+                   xchg %rbx, %rsi
+                   "#
+                   : "={eax}"(eax), "={esi}"(ebx), "={ecx}"(ecx), "={edx}"(edx)
+                   : "{eax}"(leaf), "{ecx}"(sub_leaf)
+                   : :);
+     }
+     CpuidResult { eax, ebx, ecx, edx }
+ }
+ 
+ /// See [`__cpuid_count`](fn.__cpuid_count.html).
+ #[inline]
+ #[cfg_attr(test, assert_instr(cpuid))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn __cpuid(leaf: u32) -> CpuidResult {
+     __cpuid_count(leaf, 0)
+ }
+ 
+ /// Does the host support the `cpuid` instruction?
+ #[inline]
+ pub fn has_cpuid() -> bool {
+     #[cfg(target_env = "sgx")]
+     {
+         false
+     }
+     #[cfg(all(not(target_env = "sgx"), target_arch = "x86_64"))]
+     {
+         true
+     }
+     #[cfg(all(not(target_env = "sgx"), target_arch = "x86"))]
+     {
+         // Optimization for i586 and i686 Rust targets which SSE enabled
+         // and support cpuid:
+         #[cfg(target_feature = "sse")]
+         {
+             true
+         }
+ 
+         // If SSE is not enabled, detect whether cpuid is available:
+         #[cfg(not(target_feature = "sse"))]
+         unsafe {
+             // On `x86` the `cpuid` instruction is not always available.
+             // This follows the approach indicated in:
+             // http://wiki.osdev.org/CPUID#Checking_CPUID_availability
+             // https://software.intel.com/en-us/articles/using-cpuid-to-detect-the-presence-of-sse-41-and-sse-42-instruction-sets/
+             // which detects whether `cpuid` is available by checking whether
+             // the 21st bit of the EFLAGS register is modifiable or not.
+             // If it is, then `cpuid` is available.
+             let result: u32;
+             let _temp: u32;
+             llvm_asm!(r#"
+                       # Read eflags into $0 and copy it into $1:
+                       pushfd
+                       pop     $0
+                       mov     $1, $0
+                       # Flip 21st bit of $0.
+                       xor     $0, 0x200000
+                       # Set eflags to the value of $0
+                       #
+                       # Bit 21st can only be modified if cpuid is available
+                       push    $0
+                       popfd          # A
+                       # Read eflags into $0:
+                       pushfd         # B
+                       pop     $0
+                       # xor with the original eflags sets the bits that
+                       # have been modified:
+                       xor     $0, $1
+                       "#
+                       : "=r"(result), "=r"(_temp)
+                       :
+                       : "cc", "memory"
+                       : "intel");
+             // There is a race between popfd (A) and pushfd (B)
+             // where other bits beyond 21st may have been modified due to
+             // interrupts, a debugger stepping through the asm, etc.
+             //
+             // Therefore, explicitly check whether the 21st bit
+             // was modified or not.
+             //
+             // If the result is zero, the cpuid bit was not modified.
+             // If the result is `0x200000` (non-zero), then the cpuid
+             // was correctly modified and the CPU supports the cpuid
+             // instruction:
+             (result & 0x200000) != 0
+         }
+     }
+ }
+ 
+ /// Returns the highest-supported `leaf` (`EAX`) and sub-leaf (`ECX`) `cpuid`
+ /// values.
+ ///
+ /// If `cpuid` is supported, and `leaf` is zero, then the first tuple argument
+ /// contains the highest `leaf` value that `cpuid` supports. For `leaf`s
+ /// containing sub-leafs, the second tuple argument contains the
+ /// highest-supported sub-leaf value.
+ ///
+ /// See also [`__cpuid`](fn.__cpuid.html) and
+ /// [`__cpuid_count`](fn.__cpuid_count.html).
+ #[inline]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn __get_cpuid_max(leaf: u32) -> (u32, u32) {
+     let CpuidResult { eax, ebx, .. } = __cpuid(leaf);
+     (eax, ebx)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+ 
+     #[test]
+     fn test_always_has_cpuid() {
+         // all currently-tested targets have the instruction
+         // FIXME: add targets without `cpuid` to CI
+         assert!(cpuid::has_cpuid());
+     }
+ 
+     #[test]
+     fn test_has_cpuid_idempotent() {
+         assert_eq!(cpuid::has_cpuid(), cpuid::has_cpuid());
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/eflags.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/eflags.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/eflags.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/eflags.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,83 ----
+ //! `i386` intrinsics
+ 
+ /// Reads EFLAGS.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__readeflags)
+ #[cfg(target_arch = "x86")]
+ #[inline(always)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[rustc_deprecated(
+     since = "1.29.0",
+     reason = "See issue #51810 - use inline assembly instead"
+ )]
+ #[doc(hidden)]
+ pub unsafe fn __readeflags() -> u32 {
+     let eflags: u32;
+     llvm_asm!("pushfd; popl $0" : "=r"(eflags) : : : "volatile");
+     eflags
+ }
+ 
+ /// Reads EFLAGS.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__readeflags)
+ #[cfg(target_arch = "x86_64")]
+ #[inline(always)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[rustc_deprecated(
+     since = "1.29.0",
+     reason = "See issue #51810 - use inline assembly instead"
+ )]
+ #[doc(hidden)]
+ pub unsafe fn __readeflags() -> u64 {
+     let eflags: u64;
+     llvm_asm!("pushfq; popq $0" : "=r"(eflags) : : : "volatile");
+     eflags
+ }
+ 
+ /// Write EFLAGS.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__writeeflags)
+ #[cfg(target_arch = "x86")]
+ #[inline(always)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[rustc_deprecated(
+     since = "1.29.0",
+     reason = "See issue #51810 - use inline assembly instead"
+ )]
+ #[doc(hidden)]
+ pub unsafe fn __writeeflags(eflags: u32) {
+     llvm_asm!("pushl $0; popfd" : : "r"(eflags) : "cc", "flags" : "volatile");
+ }
+ 
+ /// Write EFLAGS.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__writeeflags)
+ #[cfg(target_arch = "x86_64")]
+ #[inline(always)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[rustc_deprecated(
+     since = "1.29.0",
+     reason = "See issue #51810 - use inline assembly instead"
+ )]
+ #[doc(hidden)]
+ pub unsafe fn __writeeflags(eflags: u64) {
+     llvm_asm!("pushq $0; popfq" : : "r"(eflags) : "cc", "flags" : "volatile");
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+ 
+     #[test]
+     #[allow(deprecated)]
+     fn test_eflags() {
+         unsafe {
+             // reads eflags, writes them back, reads them again,
+             // and compare for equality:
+             let v = __readeflags();
+             __writeeflags(v);
+             let u = __readeflags();
+             assert_eq!(v, u);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/f16c.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/f16c.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/f16c.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/f16c.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,134 ----
+ //! [F16C intrinsics].
+ //!
+ //! [F16C intrinsics]: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=fp16&expand=1769
+ 
+ use crate::{
+     core_arch::{simd::*, x86::*},
+     hint::unreachable_unchecked,
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "unadjusted" {
+     #[link_name = "llvm.x86.vcvtph2ps.128"]
+     fn llvm_vcvtph2ps_128(a: i16x8) -> f32x4;
+     #[link_name = "llvm.x86.vcvtph2ps.256"]
+     fn llvm_vcvtph2ps_256(a: i16x8) -> f32x8;
+     #[link_name = "llvm.x86.vcvtps2ph.128"]
+     fn llvm_vcvtps2ph_128(a: f32x4, rounding: i32) -> i16x8;
+     #[link_name = "llvm.x86.vcvtps2ph.256"]
+     fn llvm_vcvtps2ph_256(a: f32x8, rounding: i32) -> i16x8;
+ }
+ 
+ /// Converts the 4 x 16-bit half-precision float values in the lowest 64-bit of
+ /// the 128-bit vector `a` into 4 x 32-bit float values stored in a 128-bit wide
+ /// vector.
+ #[inline]
+ #[target_feature(enable = "f16c")]
+ #[cfg_attr(test, assert_instr("vcvtph2ps"))]
+ pub unsafe fn _mm_cvtph_ps(a: __m128i) -> __m128 {
+     transmute(llvm_vcvtph2ps_128(transmute(a)))
+ }
+ 
+ /// Converts the 8 x 16-bit half-precision float values in the 128-bit vector
+ /// `a` into 8 x 32-bit float values stored in a 256-bit wide vector.
+ #[inline]
+ #[target_feature(enable = "f16c")]
+ #[cfg_attr(test, assert_instr("vcvtph2ps"))]
+ pub unsafe fn _mm256_cvtph_ps(a: __m128i) -> __m256 {
+     transmute(llvm_vcvtph2ps_256(transmute(a)))
+ }
+ 
+ macro_rules! dispatch_rounding {
+     ($rounding:ident, $call:ident) => {{
+         match $rounding {
+             0 => call!(0),
+             1 => call!(1),
+             2 => call!(2),
+             3 => call!(3),
+             4 => call!(4),
+             5 => call!(5),
+             6 => call!(6),
+             7 => call!(7),
+             _ => unreachable_unchecked(),
+         }
+     }};
+ }
+ 
+ /// Converts the 4 x 32-bit float values in the 128-bit vector `a` into 4 x
+ /// 16-bit half-precision float values stored in the lowest 64-bit of a 128-bit
+ /// vector.
+ ///
+ /// Rounding is done according to the `imm_rounding` parameter, which can be one of:
+ ///
+ /// * `_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC`: round to nearest and suppress exceptions,
+ /// * `_MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC`: round down and suppress exceptions,
+ /// * `_MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC`: round up and suppress exceptions,
+ /// * `_MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC`: truncate and suppress exceptions,
+ /// * `_MM_FROUND_CUR_DIRECTION`: use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`].
+ #[inline]
+ #[target_feature(enable = "f16c")]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(test, assert_instr("vcvtps2ph", imm_rounding = 0))]
+ pub unsafe fn _mm_cvtps_ph(a: __m128, imm_rounding: i32) -> __m128i {
+     let a = transmute(a);
+     macro_rules! call {
+         ($rounding:expr) => {
+             llvm_vcvtps2ph_128(a, $rounding)
+         };
+     }
+     transmute(dispatch_rounding!(imm_rounding, call))
+ }
+ 
+ /// Converts the 8 x 32-bit float values in the 256-bit vector `a` into 8 x
+ /// 16-bit half-precision float values stored in a 128-bit wide vector.
+ ///
+ /// Rounding is done according to the `imm_rounding` parameter, which can be one of:
+ ///
+ /// * `_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC`: round to nearest and suppress exceptions,
+ /// * `_MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC`: round down and suppress exceptions,
+ /// * `_MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC`: round up and suppress exceptions,
+ /// * `_MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC`: truncate and suppress exceptions,
+ /// * `_MM_FROUND_CUR_DIRECTION`: use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`].
+ #[inline]
+ #[target_feature(enable = "f16c")]
+ #[rustc_args_required_const(1)]
+ #[cfg_attr(test, assert_instr("vcvtps2ph", imm_rounding = 0))]
+ pub unsafe fn _mm256_cvtps_ph(a: __m256, imm_rounding: i32) -> __m128i {
+     let a = transmute(a);
+     macro_rules! call {
+         ($rounding:expr) => {
+             llvm_vcvtps2ph_256(a, $rounding)
+         };
+     }
+     transmute(dispatch_rounding!(imm_rounding, call))
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::{core_arch::x86::*, mem::transmute};
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "f16c")]
+     unsafe fn test_mm_cvtph_ps() {
+         let array = [1_f32, 2_f32, 3_f32, 4_f32];
+         let float_vec: __m128 = transmute(array);
+         let halfs: __m128i = _mm_cvtps_ph(float_vec, 0);
+         let floats: __m128 = _mm_cvtph_ps(halfs);
+         let result: [f32; 4] = transmute(floats);
+         assert_eq!(result, array);
+     }
+ 
+     #[simd_test(enable = "f16c")]
+     unsafe fn test_mm256_cvtph_ps() {
+         let array = [1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32];
+         let float_vec: __m256 = transmute(array);
+         let halfs: __m128i = _mm256_cvtps_ph(float_vec, 0);
+         let floats: __m256 = _mm256_cvtph_ps(halfs);
+         let result: [f32; 8] = transmute(floats);
+         assert_eq!(result, array);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fma.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fma.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fma.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fma.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,795 ----
+ //! Fused Multiply-Add instruction set (FMA)
+ //!
+ //! The FMA instruction set is an extension to the 128 and 256-bit SSE
+ //! instructions in the x86 microprocessor instruction set to perform fused
+ //! multiply–add (FMA) operations.
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //!   Instruction Set Reference, A-Z][intel64_ref].
+ //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ //!   System Instructions][amd64_ref].
+ //!
+ //! Wikipedia's [FMA][wiki_fma] page provides a quick overview of the
+ //! instructions available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
+ 
+ use crate::core_arch::simd_llvm::simd_fma;
+ use crate::core_arch::x86::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and add the intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     simd_fma(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and add the intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmadd_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     simd_fma(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and add the intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+     simd_fma(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and add the intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmadd_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     simd_fma(a, b, c)
+ }
+ 
+ /// Multiplies the lower double-precision (64-bit) floating-point elements in
+ /// `a` and `b`, and add the intermediate result to the lower element in `c`.
+ /// Stores the result in the lower element of the returned value, and copy the
+ /// upper element from `a` to the upper elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_sd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfmaddsd(a, b, c)
+ }
+ 
+ /// Multiplies the lower single-precision (32-bit) floating-point elements in
+ /// `a` and `b`, and add the intermediate result to the lower element in `c`.
+ /// Stores the result in the lower element of the returned value, and copy the
+ /// 3 upper elements from `a` to the upper elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_ss)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfmaddss(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and alternatively add and subtract packed elements in `c` to/from
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmaddsub_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfmaddsubpd(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and alternatively add and subtract packed elements in `c` to/from
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmaddsub_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     vfmaddsubpd256(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and alternatively add and subtract packed elements in `c` to/from
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmaddsub_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmaddsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfmaddsubps(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and alternatively add and subtract packed elements in `c` to/from
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmaddsub_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmaddsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmaddsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     vfmaddsubps256(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfmsubpd(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmsub_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     vfmsubpd256(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsub213ps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfmsubps(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmsub_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsub213ps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     vfmsubps256(a, b, c)
+ }
+ 
+ /// Multiplies the lower double-precision (64-bit) floating-point elements in
+ /// `a` and `b`, and subtract the lower element in `c` from the intermediate
+ /// result. Store the result in the lower element of the returned value, and
+ /// copy the upper element from `a` to the upper elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_sd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfmsubsd(a, b, c)
+ }
+ 
+ /// Multiplies the lower single-precision (32-bit) floating-point elements in
+ /// `a` and `b`,  and subtract the lower element in `c` from the intermediate
+ /// result. Store the result in the lower element of the returned value, and
+ /// copy the 3 upper elements from `a` to the upper elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_ss)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfmsubss(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and alternatively subtract and add packed elements in `c` from/to
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsubadd_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsubadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfmsubaddpd(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and alternatively subtract and add packed elements in `c` from/to
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmsubadd_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsubadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     vfmsubaddpd256(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and alternatively subtract and add packed elements in `c` from/to
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsubadd_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsubadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fmsubadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfmsubaddps(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and alternatively subtract and add packed elements in `c` from/to
+ /// the intermediate result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fmsubadd_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfmsubadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fmsubadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     vfmsubaddps256(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and add the negated intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfnmaddpd(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and add the negated intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fnmadd_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     vfnmaddpd256(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and add the negated intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmadd_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfnmaddps(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and add the negated intermediate result to packed elements in `c`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fnmadd_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fnmadd_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     vfnmaddps256(a, b, c)
+ }
+ 
+ /// Multiplies the lower double-precision (64-bit) floating-point elements in
+ /// `a` and `b`, and add the negated intermediate result to the lower element
+ /// in `c`. Store the result in the lower element of the returned value, and
+ /// copy the upper element from `a` to the upper elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_sd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfnmaddsd(a, b, c)
+ }
+ 
+ /// Multiplies the lower single-precision (32-bit) floating-point elements in
+ /// `a` and `b`, and add the negated intermediate result to the lower element
+ /// in `c`. Store the result in the lower element of the returned value, and
+ /// copy the 3 upper elements from `a` to the upper elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_ss)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmadd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmadd_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfnmaddss(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the negated intermediate
+ /// result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfnmsubpd(a, b, c)
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the negated intermediate
+ /// result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fnmsub_pd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d) -> __m256d {
+     vfnmsubpd256(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the negated intermediate
+ /// result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmsub_ps(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfnmsubps(a, b, c)
+ }
+ 
+ /// Multiplies packed single-precision (32-bit) floating-point elements in `a`
+ /// and `b`, and subtract packed elements in `c` from the negated intermediate
+ /// result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fnmsub_ps)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_fnmsub_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
+     vfnmsubps256(a, b, c)
+ }
+ 
+ /// Multiplies the lower double-precision (64-bit) floating-point elements in
+ /// `a` and `b`, and subtract packed elements in `c` from the negated
+ /// intermediate result. Store the result in the lower element of the returned
+ /// value, and copy the upper element from `a` to the upper elements of the
+ /// result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_sd)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d {
+     vfnmsubsd(a, b, c)
+ }
+ 
+ /// Multiplies the lower single-precision (32-bit) floating-point elements in
+ /// `a` and `b`, and subtract packed elements in `c` from the negated
+ /// intermediate result. Store the result in the lower element of the
+ /// returned value, and copy the 3 upper elements from `a` to the upper
+ /// elements of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_ss)
+ #[inline]
+ #[target_feature(enable = "fma")]
+ #[cfg_attr(test, assert_instr(vfnmsub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_fnmsub_ss(a: __m128, b: __m128, c: __m128) -> __m128 {
+     vfnmsubss(a, b, c)
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.fma.vfmadd.sd"]
+     fn vfmaddsd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfmadd.ss"]
+     fn vfmaddss(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfmaddsub.pd"]
+     fn vfmaddsubpd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfmaddsub.pd.256"]
+     fn vfmaddsubpd256(a: __m256d, b: __m256d, c: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.fma.vfmaddsub.ps"]
+     fn vfmaddsubps(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfmaddsub.ps.256"]
+     fn vfmaddsubps256(a: __m256, b: __m256, c: __m256) -> __m256;
+     #[link_name = "llvm.x86.fma.vfmsub.pd"]
+     fn vfmsubpd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfmsub.pd.256"]
+     fn vfmsubpd256(a: __m256d, b: __m256d, c: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.fma.vfmsub.ps"]
+     fn vfmsubps(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfmsub.ps.256"]
+     fn vfmsubps256(a: __m256, b: __m256, c: __m256) -> __m256;
+     #[link_name = "llvm.x86.fma.vfmsub.sd"]
+     fn vfmsubsd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfmsub.ss"]
+     fn vfmsubss(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfmsubadd.pd"]
+     fn vfmsubaddpd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfmsubadd.pd.256"]
+     fn vfmsubaddpd256(a: __m256d, b: __m256d, c: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.fma.vfmsubadd.ps"]
+     fn vfmsubaddps(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfmsubadd.ps.256"]
+     fn vfmsubaddps256(a: __m256, b: __m256, c: __m256) -> __m256;
+     #[link_name = "llvm.x86.fma.vfnmadd.pd"]
+     fn vfnmaddpd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfnmadd.pd.256"]
+     fn vfnmaddpd256(a: __m256d, b: __m256d, c: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.fma.vfnmadd.ps"]
+     fn vfnmaddps(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfnmadd.ps.256"]
+     fn vfnmaddps256(a: __m256, b: __m256, c: __m256) -> __m256;
+     #[link_name = "llvm.x86.fma.vfnmadd.sd"]
+     fn vfnmaddsd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfnmadd.ss"]
+     fn vfnmaddss(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfnmsub.pd"]
+     fn vfnmsubpd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfnmsub.pd.256"]
+     fn vfnmsubpd256(a: __m256d, b: __m256d, c: __m256d) -> __m256d;
+     #[link_name = "llvm.x86.fma.vfnmsub.ps"]
+     fn vfnmsubps(a: __m128, b: __m128, c: __m128) -> __m128;
+     #[link_name = "llvm.x86.fma.vfnmsub.ps.256"]
+     fn vfnmsubps256(a: __m256, b: __m256, c: __m256) -> __m256;
+     #[link_name = "llvm.x86.fma.vfnmsub.sd"]
+     fn vfnmsubsd(a: __m128d, b: __m128d, c: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.fma.vfnmsub.ss"]
+     fn vfnmsubss(a: __m128, b: __m128, c: __m128) -> __m128;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std;
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmadd_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(9., 15.);
+         assert_eq_m128d(_mm_fmadd_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmadd_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 3., 7., 2.);
+         let c = _mm256_setr_pd(4., 9., 1., 7.);
+         let r = _mm256_setr_pd(9., 15., 22., 15.);
+         assert_eq_m256d(_mm256_fmadd_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmadd_ps() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(9., 15., 22., 15.);
+         assert_eq_m128(_mm_fmadd_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmadd_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
+         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
+         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
+         let r = _mm256_setr_ps(9., 15., 22., 15., -5., -49., -2., -31.);
+         assert_eq_m256(_mm256_fmadd_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmadd_sd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(9., 2.);
+         assert_eq_m128d(_mm_fmadd_sd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmadd_ss() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(9., 2., 3., 4.);
+         assert_eq_m128(_mm_fmadd_ss(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmaddsub_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(1., 15.);
+         assert_eq_m128d(_mm_fmaddsub_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmaddsub_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 3., 7., 2.);
+         let c = _mm256_setr_pd(4., 9., 1., 7.);
+         let r = _mm256_setr_pd(1., 15., 20., 15.);
+         assert_eq_m256d(_mm256_fmaddsub_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmaddsub_ps() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(1., 15., 20., 15.);
+         assert_eq_m128(_mm_fmaddsub_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmaddsub_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
+         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
+         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
+         let r = _mm256_setr_ps(1., 15., 20., 15., 5., -49., 2., -31.);
+         assert_eq_m256(_mm256_fmaddsub_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmsub_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(1., -3.);
+         assert_eq_m128d(_mm_fmsub_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmsub_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 3., 7., 2.);
+         let c = _mm256_setr_pd(4., 9., 1., 7.);
+         let r = _mm256_setr_pd(1., -3., 20., 1.);
+         assert_eq_m256d(_mm256_fmsub_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmsub_ps() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(1., -3., 20., 1.);
+         assert_eq_m128(_mm_fmsub_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmsub_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
+         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
+         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
+         let r = _mm256_setr_ps(1., -3., 20., 1., 5., -71., 2., -25.);
+         assert_eq_m256(_mm256_fmsub_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmsub_sd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(1., 2.);
+         assert_eq_m128d(_mm_fmsub_sd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmsub_ss() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(1., 2., 3., 4.);
+         assert_eq_m128(_mm_fmsub_ss(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmsubadd_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(9., -3.);
+         assert_eq_m128d(_mm_fmsubadd_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmsubadd_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 3., 7., 2.);
+         let c = _mm256_setr_pd(4., 9., 1., 7.);
+         let r = _mm256_setr_pd(9., -3., 22., 1.);
+         assert_eq_m256d(_mm256_fmsubadd_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fmsubadd_ps() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(9., -3., 22., 1.);
+         assert_eq_m128(_mm_fmsubadd_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fmsubadd_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
+         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
+         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
+         let r = _mm256_setr_ps(9., -3., 22., 1., -5., -71., -2., -25.);
+         assert_eq_m256(_mm256_fmsubadd_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmadd_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(-1., 3.);
+         assert_eq_m128d(_mm_fnmadd_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fnmadd_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 3., 7., 2.);
+         let c = _mm256_setr_pd(4., 9., 1., 7.);
+         let r = _mm256_setr_pd(-1., 3., -20., -1.);
+         assert_eq_m256d(_mm256_fnmadd_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmadd_ps() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(-1., 3., -20., -1.);
+         assert_eq_m128(_mm_fnmadd_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fnmadd_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
+         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
+         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
+         let r = _mm256_setr_ps(-1., 3., -20., -1., -5., 71., -2., 25.);
+         assert_eq_m256(_mm256_fnmadd_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmadd_sd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(-1., 2.);
+         assert_eq_m128d(_mm_fnmadd_sd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmadd_ss() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(-1., 2., 3., 4.);
+         assert_eq_m128(_mm_fnmadd_ss(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmsub_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(-9., -15.);
+         assert_eq_m128d(_mm_fnmsub_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fnmsub_pd() {
+         let a = _mm256_setr_pd(1., 2., 3., 4.);
+         let b = _mm256_setr_pd(5., 3., 7., 2.);
+         let c = _mm256_setr_pd(4., 9., 1., 7.);
+         let r = _mm256_setr_pd(-9., -15., -22., -15.);
+         assert_eq_m256d(_mm256_fnmsub_pd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmsub_ps() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(-9., -15., -22., -15.);
+         assert_eq_m128(_mm_fnmsub_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm256_fnmsub_ps() {
+         let a = _mm256_setr_ps(1., 2., 3., 4., 0., 10., -1., -2.);
+         let b = _mm256_setr_ps(5., 3., 7., 2., 4., -6., 0., 14.);
+         let c = _mm256_setr_ps(4., 9., 1., 7., -5., 11., -2., -3.);
+         let r = _mm256_setr_ps(-9., -15., -22., -15., 5., 49., 2., 31.);
+         assert_eq_m256(_mm256_fnmsub_ps(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmsub_sd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(5., 3.);
+         let c = _mm_setr_pd(4., 9.);
+         let r = _mm_setr_pd(-9., 2.);
+         assert_eq_m128d(_mm_fnmsub_sd(a, b, c), r);
+     }
+ 
+     #[simd_test(enable = "fma")]
+     unsafe fn test_mm_fnmsub_ss() {
+         let a = _mm_setr_ps(1., 2., 3., 4.);
+         let b = _mm_setr_ps(5., 3., 7., 2.);
+         let c = _mm_setr_ps(4., 9., 1., 7.);
+         let r = _mm_setr_ps(-9., 2., 3., 4.);
+         assert_eq_m128(_mm_fnmsub_ss(a, b, c), r);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fxsr.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fxsr.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fxsr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/fxsr.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,112 ----
+ //! FXSR floating-point context fast save and restor.
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.fxsave"]
+     fn fxsave(p: *mut u8) -> ();
+     #[link_name = "llvm.x86.fxrstor"]
+     fn fxrstor(p: *const u8) -> ();
+ }
+ 
+ /// Saves the `x87` FPU, `MMX` technology, `XMM`, and `MXCSR` registers to the
+ /// 512-byte-long 16-byte-aligned memory region `mem_addr`.
+ ///
+ /// A misaligned destination operand raises a general-protection (#GP) or an
+ /// alignment check exception (#AC).
+ ///
+ /// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor].
+ ///
+ /// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html
+ /// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_fxsave)
+ #[inline]
+ #[target_feature(enable = "fxsr")]
+ #[cfg_attr(test, assert_instr(fxsave))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _fxsave(mem_addr: *mut u8) {
+     fxsave(mem_addr)
+ }
+ 
+ /// Restores the `XMM`, `MMX`, `MXCSR`, and `x87` FPU registers from the
+ /// 512-byte-long 16-byte-aligned memory region `mem_addr`.
+ ///
+ /// The contents of this memory region should have been written to by a
+ /// previous
+ /// `_fxsave` or `_fxsave64` intrinsic.
+ ///
+ /// A misaligned destination operand raises a general-protection (#GP) or an
+ /// alignment check exception (#AC).
+ ///
+ /// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor].
+ ///
+ /// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html
+ /// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_fxrstor)
+ #[inline]
+ #[target_feature(enable = "fxsr")]
+ #[cfg_attr(test, assert_instr(fxrstor))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _fxrstor(mem_addr: *const u8) {
+     fxrstor(mem_addr)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+     use std::{cmp::PartialEq, fmt};
+     use stdarch_test::simd_test;
+ 
+     #[repr(align(16))]
+     struct FxsaveArea {
+         data: [u8; 512], // 512 bytes
+     }
+ 
+     impl FxsaveArea {
+         fn new() -> FxsaveArea {
+             FxsaveArea { data: [0; 512] }
+         }
+         fn ptr(&mut self) -> *mut u8 {
+             &mut self.data[0] as *mut _ as *mut u8
+         }
+     }
+ 
+     impl PartialEq<FxsaveArea> for FxsaveArea {
+         fn eq(&self, other: &FxsaveArea) -> bool {
+             for i in 0..self.data.len() {
+                 if self.data[i] != other.data[i] {
+                     return false;
+                 }
+             }
+             true
+         }
+     }
+ 
+     impl fmt::Debug for FxsaveArea {
+         fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+             write!(f, "[")?;
+             for i in 0..self.data.len() {
+                 write!(f, "{}", self.data[i])?;
+                 if i != self.data.len() - 1 {
+                     write!(f, ", ")?;
+                 }
+             }
+             write!(f, "]")
+         }
+     }
+ 
+     #[simd_test(enable = "fxsr")]
+     unsafe fn fxsave() {
+         let mut a = FxsaveArea::new();
+         let mut b = FxsaveArea::new();
+ 
+         fxsr::_fxsave(a.ptr());
+         fxsr::_fxrstor(a.ptr());
+         fxsr::_fxsave(b.ptr());
+         assert_eq!(a, b);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/macros.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,750 ----
+ //! Utility macros.
+ 
+ macro_rules! constify_imm6 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             _ => $expand!(31),
+         }
+     };
+ }
+ 
+ macro_rules! constify_imm4 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             _ => $expand!(15),
+         }
+     };
+ }
+ 
+ macro_rules! constify_imm3 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             _ => $expand!(7),
+         }
+     };
+ }
+ 
+ macro_rules! constify_imm2 {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b11 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             _ => $expand!(3),
+         }
+     };
+ }
+ 
+ // Constifies 5 bits along with an sae option without rounding control.
+ // See: https://github.com/llvm/llvm-project/blob/bd50cf905fa7c0c7caa134301c6ca0658c81eeb1/clang/lib/Sema/SemaChecking.cpp#L3497
+ #[allow(unused)]
+ macro_rules! constify_imm5_sae {
+     ($imm5:expr, $imm4:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm5 & 0b1111_1, $imm4 & 0b1111) {
+             (0, 4) => $expand!(0, 4),
+             (0, 8) => $expand!(0, 8),
+             (0, 12) => $expand!(0, 12),
+             (1, 4) => $expand!(1, 4),
+             (1, 8) => $expand!(1, 8),
+             (1, 12) => $expand!(1, 12),
+             (2, 4) => $expand!(2, 4),
+             (2, 8) => $expand!(2, 8),
+             (2, 12) => $expand!(2, 12),
+             (3, 4) => $expand!(3, 4),
+             (3, 8) => $expand!(3, 8),
+             (3, 12) => $expand!(3, 12),
+             (4, 4) => $expand!(4, 4),
+             (4, 8) => $expand!(4, 8),
+             (4, 12) => $expand!(4, 12),
+             (5, 4) => $expand!(5, 4),
+             (5, 8) => $expand!(5, 8),
+             (5, 12) => $expand!(5, 12),
+             (6, 4) => $expand!(6, 4),
+             (6, 8) => $expand!(6, 8),
+             (6, 12) => $expand!(6, 12),
+             (7, 4) => $expand!(7, 4),
+             (7, 8) => $expand!(7, 8),
+             (7, 12) => $expand!(7, 12),
+             (8, 4) => $expand!(8, 4),
+             (8, 8) => $expand!(8, 8),
+             (8, 12) => $expand!(8, 12),
+             (9, 4) => $expand!(9, 4),
+             (9, 8) => $expand!(9, 8),
+             (9, 12) => $expand!(9, 12),
+             (10, 4) => $expand!(10, 4),
+             (10, 8) => $expand!(10, 8),
+             (10, 12) => $expand!(10, 12),
+             (11, 4) => $expand!(11, 4),
+             (11, 8) => $expand!(11, 8),
+             (11, 12) => $expand!(11, 12),
+             (12, 4) => $expand!(12, 4),
+             (12, 8) => $expand!(12, 8),
+             (12, 12) => $expand!(12, 12),
+             (13, 4) => $expand!(13, 4),
+             (13, 8) => $expand!(13, 8),
+             (13, 12) => $expand!(13, 12),
+             (14, 4) => $expand!(14, 4),
+             (14, 8) => $expand!(14, 8),
+             (14, 12) => $expand!(14, 12),
+             (15, 4) => $expand!(15, 4),
+             (15, 8) => $expand!(15, 8),
+             (15, 12) => $expand!(15, 12),
+             (16, 4) => $expand!(16, 4),
+             (16, 8) => $expand!(16, 8),
+             (16, 12) => $expand!(16, 12),
+             (17, 4) => $expand!(17, 4),
+             (17, 8) => $expand!(17, 8),
+             (17, 12) => $expand!(17, 12),
+             (18, 4) => $expand!(18, 4),
+             (18, 8) => $expand!(18, 8),
+             (18, 12) => $expand!(18, 12),
+             (19, 4) => $expand!(19, 4),
+             (19, 8) => $expand!(19, 8),
+             (19, 12) => $expand!(19, 12),
+             (20, 4) => $expand!(20, 4),
+             (20, 8) => $expand!(20, 8),
+             (20, 12) => $expand!(20, 12),
+             (21, 4) => $expand!(21, 4),
+             (21, 8) => $expand!(21, 8),
+             (21, 12) => $expand!(21, 12),
+             (22, 4) => $expand!(22, 4),
+             (22, 8) => $expand!(22, 8),
+             (22, 12) => $expand!(22, 12),
+             (23, 4) => $expand!(23, 4),
+             (23, 8) => $expand!(23, 8),
+             (23, 12) => $expand!(23, 12),
+             (24, 4) => $expand!(24, 4),
+             (24, 8) => $expand!(24, 8),
+             (24, 12) => $expand!(24, 12),
+             (25, 4) => $expand!(25, 4),
+             (25, 8) => $expand!(25, 8),
+             (25, 12) => $expand!(25, 12),
+             (26, 4) => $expand!(26, 4),
+             (26, 8) => $expand!(26, 8),
+             (26, 12) => $expand!(26, 12),
+             (27, 4) => $expand!(27, 4),
+             (27, 8) => $expand!(27, 8),
+             (27, 12) => $expand!(27, 12),
+             (28, 4) => $expand!(28, 4),
+             (28, 8) => $expand!(28, 8),
+             (28, 12) => $expand!(28, 12),
+             (29, 4) => $expand!(29, 4),
+             (29, 8) => $expand!(29, 8),
+             (29, 12) => $expand!(29, 12),
+             (30, 4) => $expand!(30, 4),
+             (30, 8) => $expand!(30, 8),
+             (30, 12) => $expand!(30, 12),
+             (31, 4) => $expand!(31, 4),
+             (31, 8) => $expand!(31, 8),
+             (31, 12) => $expand!(31, 12),
+             (_, _) => panic!("Invalid sae value"),
+         }
+     };
+ }
+ 
+ // For gather instructions, the only valid values for scale are 1, 2, 4 and 8.
+ // This macro enforces that.
+ #[allow(unused)]
+ macro_rules! constify_imm8_gather {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) {
+             1 => $expand!(1),
+             2 => $expand!(2),
+             4 => $expand!(4),
+             8 => $expand!(8),
+             _ => panic!("Only 1, 2, 4, and 8 are valid values"),
+         }
+     };
+ }
+ 
+ // For round instructions, the only valid values for rounding are 4, 8, 9, 10 and 11.
+ // This macro enforces that.
+ #[allow(unused)]
+ macro_rules! constify_imm4_round {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111 {
+             4 => $expand!(4),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             _ => panic!("Invalid round value"),
+         }
+     };
+ }
+ 
+ // For sae instructions, the only valid values for sae are 4 and 8.
+ // This macro enforces that.
+ #[allow(unused)]
+ macro_rules! constify_imm4_sae {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111 {
+             4 => $expand!(4),
+             8 => $expand!(8),
+             _ => panic!("Invalid sae value"),
+         }
+     };
+ }
+ 
+ // Two mantissas parameters.
+ // This macro enforces that.
+ #[allow(unused)]
+ macro_rules! constify_imm4_mantissas {
+     ($imm4:expr, $imm2:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm4, $imm2) {
+             (0, 0) => $expand!(0, 0),
+             (0, 1) => $expand!(0, 1),
+             (0, 2) => $expand!(0, 2),
+             (0, 3) => $expand!(0, 3),
+             (1, 0) => $expand!(1, 0),
+             (1, 1) => $expand!(1, 1),
+             (1, 2) => $expand!(1, 2),
+             (1, 3) => $expand!(1, 3),
+             (2, 0) => $expand!(2, 0),
+             (2, 1) => $expand!(2, 1),
+             (2, 2) => $expand!(2, 2),
+             (2, 3) => $expand!(2, 3),
+             (3, 0) => $expand!(3, 0),
+             (3, 1) => $expand!(3, 1),
+             (3, 2) => $expand!(3, 2),
+             (3, 3) => $expand!(3, 3),
+             (4, 0) => $expand!(4, 0),
+             (4, 1) => $expand!(4, 1),
+             (4, 2) => $expand!(4, 2),
+             (4, 3) => $expand!(4, 3),
+             (5, 0) => $expand!(5, 0),
+             (5, 1) => $expand!(5, 1),
+             (5, 2) => $expand!(5, 2),
+             (5, 3) => $expand!(5, 3),
+             (6, 0) => $expand!(6, 0),
+             (6, 1) => $expand!(6, 1),
+             (6, 2) => $expand!(6, 2),
+             (6, 3) => $expand!(6, 3),
+             (7, 0) => $expand!(7, 0),
+             (7, 1) => $expand!(7, 1),
+             (7, 2) => $expand!(7, 2),
+             (7, 3) => $expand!(7, 3),
+             (8, 0) => $expand!(8, 0),
+             (8, 1) => $expand!(8, 1),
+             (8, 2) => $expand!(8, 2),
+             (8, 3) => $expand!(8, 3),
+             (9, 0) => $expand!(9, 0),
+             (9, 1) => $expand!(9, 1),
+             (9, 2) => $expand!(9, 2),
+             (9, 3) => $expand!(9, 3),
+             (10, 0) => $expand!(10, 0),
+             (10, 1) => $expand!(10, 1),
+             (10, 2) => $expand!(10, 2),
+             (10, 3) => $expand!(10, 3),
+             (11, 0) => $expand!(11, 0),
+             (11, 1) => $expand!(11, 1),
+             (11, 2) => $expand!(11, 2),
+             (11, 3) => $expand!(11, 3),
+             (12, 0) => $expand!(12, 0),
+             (12, 1) => $expand!(12, 1),
+             (12, 2) => $expand!(12, 2),
+             (12, 3) => $expand!(12, 3),
+             (13, 0) => $expand!(13, 0),
+             (13, 1) => $expand!(13, 1),
+             (13, 2) => $expand!(13, 2),
+             (13, 3) => $expand!(13, 3),
+             (14, 0) => $expand!(14, 0),
+             (14, 1) => $expand!(14, 1),
+             (14, 2) => $expand!(14, 2),
+             (14, 3) => $expand!(14, 3),
+             (15, 0) => $expand!(15, 0),
+             (15, 1) => $expand!(15, 1),
+             (15, 2) => $expand!(15, 2),
+             (15, 3) => $expand!(15, 3),
+             (_, _) => panic!("Invalid sae value"),
+         }
+     };
+ }
+ 
+ // Include mantissas parameters.
+ // For sae instructions, the only valid values for sae are 4 and 8.
+ // This macro enforces that.
+ #[allow(unused)]
+ macro_rules! constify_imm4_mantissas_sae {
+     ($imm4_1:expr, $imm2:expr, $imm4_2:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm4_1, $imm2, $imm4_2) {
+             (0, 0, 4) => $expand!(0, 0, 4),
+             (0, 0, 8) => $expand!(0, 0, 8),
+             (0, 1, 4) => $expand!(0, 1, 4),
+             (0, 1, 8) => $expand!(0, 1, 8),
+             (0, 2, 4) => $expand!(0, 2, 4),
+             (0, 2, 8) => $expand!(0, 2, 8),
+             (0, 3, 4) => $expand!(0, 3, 4),
+             (0, 3, 8) => $expand!(0, 3, 8),
+             (1, 0, 4) => $expand!(1, 0, 4),
+             (1, 0, 8) => $expand!(1, 0, 8),
+             (1, 1, 4) => $expand!(1, 1, 4),
+             (1, 1, 8) => $expand!(1, 1, 8),
+             (1, 2, 4) => $expand!(1, 2, 4),
+             (1, 2, 8) => $expand!(1, 2, 8),
+             (1, 3, 4) => $expand!(1, 3, 4),
+             (1, 3, 8) => $expand!(1, 3, 8),
+             (2, 0, 4) => $expand!(2, 0, 4),
+             (2, 0, 8) => $expand!(2, 0, 8),
+             (2, 1, 4) => $expand!(2, 1, 4),
+             (2, 1, 8) => $expand!(2, 1, 8),
+             (2, 2, 4) => $expand!(2, 2, 4),
+             (2, 2, 8) => $expand!(2, 2, 8),
+             (2, 3, 4) => $expand!(2, 3, 4),
+             (2, 3, 8) => $expand!(2, 3, 8),
+             (3, 0, 4) => $expand!(3, 0, 4),
+             (3, 0, 8) => $expand!(3, 0, 8),
+             (3, 1, 4) => $expand!(3, 1, 4),
+             (3, 1, 8) => $expand!(3, 1, 8),
+             (3, 2, 4) => $expand!(3, 2, 4),
+             (3, 2, 8) => $expand!(3, 2, 8),
+             (3, 3, 4) => $expand!(3, 3, 4),
+             (3, 3, 8) => $expand!(3, 3, 8),
+             (4, 0, 4) => $expand!(4, 0, 4),
+             (4, 0, 8) => $expand!(4, 0, 8),
+             (4, 1, 4) => $expand!(4, 1, 4),
+             (4, 1, 8) => $expand!(4, 1, 8),
+             (4, 2, 4) => $expand!(4, 2, 4),
+             (4, 2, 8) => $expand!(4, 2, 8),
+             (4, 3, 4) => $expand!(4, 3, 4),
+             (4, 3, 8) => $expand!(4, 3, 8),
+             (5, 0, 4) => $expand!(5, 0, 4),
+             (5, 0, 8) => $expand!(5, 0, 8),
+             (5, 1, 4) => $expand!(5, 1, 4),
+             (5, 1, 8) => $expand!(5, 1, 8),
+             (5, 2, 4) => $expand!(5, 2, 4),
+             (5, 2, 8) => $expand!(5, 2, 8),
+             (5, 3, 4) => $expand!(5, 3, 4),
+             (5, 3, 8) => $expand!(5, 3, 8),
+             (6, 0, 4) => $expand!(6, 0, 4),
+             (6, 0, 8) => $expand!(6, 0, 8),
+             (6, 1, 4) => $expand!(6, 1, 4),
+             (6, 1, 8) => $expand!(6, 1, 8),
+             (6, 2, 4) => $expand!(6, 2, 4),
+             (6, 2, 8) => $expand!(6, 2, 8),
+             (6, 3, 4) => $expand!(6, 3, 4),
+             (6, 3, 8) => $expand!(6, 3, 8),
+             (7, 0, 4) => $expand!(7, 0, 4),
+             (7, 0, 8) => $expand!(7, 0, 8),
+             (7, 1, 4) => $expand!(7, 1, 4),
+             (7, 1, 8) => $expand!(7, 1, 8),
+             (7, 2, 4) => $expand!(7, 2, 4),
+             (7, 2, 8) => $expand!(7, 2, 8),
+             (7, 3, 4) => $expand!(7, 3, 4),
+             (7, 3, 8) => $expand!(7, 3, 8),
+             (8, 0, 4) => $expand!(8, 0, 4),
+             (8, 0, 8) => $expand!(8, 0, 8),
+             (8, 1, 4) => $expand!(8, 1, 4),
+             (8, 1, 8) => $expand!(8, 1, 8),
+             (8, 2, 4) => $expand!(8, 2, 4),
+             (8, 2, 8) => $expand!(8, 2, 8),
+             (8, 3, 4) => $expand!(8, 3, 4),
+             (8, 3, 8) => $expand!(8, 3, 8),
+             (9, 0, 4) => $expand!(9, 0, 4),
+             (9, 0, 8) => $expand!(9, 0, 8),
+             (9, 1, 4) => $expand!(9, 1, 4),
+             (9, 1, 8) => $expand!(9, 1, 8),
+             (9, 2, 4) => $expand!(9, 2, 4),
+             (9, 2, 8) => $expand!(9, 2, 8),
+             (9, 3, 4) => $expand!(9, 3, 4),
+             (9, 3, 8) => $expand!(9, 3, 8),
+             (10, 0, 4) => $expand!(10, 0, 4),
+             (10, 0, 8) => $expand!(10, 0, 8),
+             (10, 1, 4) => $expand!(10, 1, 4),
+             (10, 1, 8) => $expand!(10, 1, 8),
+             (10, 2, 4) => $expand!(10, 2, 4),
+             (10, 2, 8) => $expand!(10, 2, 8),
+             (10, 3, 4) => $expand!(10, 3, 4),
+             (10, 3, 8) => $expand!(10, 3, 8),
+             (11, 0, 4) => $expand!(11, 0, 4),
+             (11, 0, 8) => $expand!(11, 0, 8),
+             (11, 1, 4) => $expand!(11, 1, 4),
+             (11, 1, 8) => $expand!(11, 1, 8),
+             (11, 2, 4) => $expand!(11, 2, 4),
+             (11, 2, 8) => $expand!(11, 2, 8),
+             (11, 3, 4) => $expand!(11, 3, 4),
+             (11, 3, 8) => $expand!(11, 3, 8),
+             (12, 0, 4) => $expand!(12, 0, 4),
+             (12, 0, 8) => $expand!(12, 0, 8),
+             (12, 1, 4) => $expand!(12, 1, 4),
+             (12, 1, 8) => $expand!(12, 1, 8),
+             (12, 2, 4) => $expand!(12, 2, 4),
+             (12, 2, 8) => $expand!(12, 2, 8),
+             (12, 3, 4) => $expand!(12, 3, 4),
+             (12, 3, 8) => $expand!(12, 3, 8),
+             (13, 0, 4) => $expand!(13, 0, 4),
+             (13, 0, 8) => $expand!(13, 0, 8),
+             (13, 1, 4) => $expand!(13, 1, 4),
+             (13, 1, 8) => $expand!(13, 1, 8),
+             (13, 2, 4) => $expand!(13, 2, 4),
+             (13, 2, 8) => $expand!(13, 2, 8),
+             (13, 3, 4) => $expand!(13, 3, 4),
+             (13, 3, 8) => $expand!(13, 3, 8),
+             (14, 0, 4) => $expand!(14, 0, 4),
+             (14, 0, 8) => $expand!(14, 0, 8),
+             (14, 1, 4) => $expand!(14, 1, 4),
+             (14, 1, 8) => $expand!(14, 1, 8),
+             (14, 2, 4) => $expand!(14, 2, 4),
+             (14, 2, 8) => $expand!(14, 2, 8),
+             (14, 3, 4) => $expand!(14, 3, 4),
+             (14, 3, 8) => $expand!(14, 3, 8),
+             (15, 0, 4) => $expand!(15, 0, 4),
+             (15, 0, 8) => $expand!(15, 0, 8),
+             (15, 1, 4) => $expand!(15, 1, 4),
+             (15, 1, 8) => $expand!(15, 1, 8),
+             (15, 2, 4) => $expand!(15, 2, 4),
+             (15, 2, 8) => $expand!(15, 2, 8),
+             (15, 3, 4) => $expand!(15, 3, 4),
+             (15, 3, 8) => $expand!(15, 3, 8),
+             (_, _, _) => panic!("Invalid sae value"),
+         }
+     };
+ }
+ 
+ // Constifies 8 bits along with an sae option without rounding control.
+ // The only valid values are 0 to 255.
+ // This macro enforces that.
+ #[allow(unused)]
+ macro_rules! constify_imm8_sae {
+     ($imm8:expr, $expand:ident) => {
+         #[allow(overflowing_literals)]
+         match ($imm8) & 0b1111_1111 {
+             0 => $expand!(0),
+             1 => $expand!(1),
+             2 => $expand!(2),
+             3 => $expand!(3),
+             4 => $expand!(4),
+             5 => $expand!(5),
+             6 => $expand!(6),
+             7 => $expand!(7),
+             8 => $expand!(8),
+             9 => $expand!(9),
+             10 => $expand!(10),
+             11 => $expand!(11),
+             12 => $expand!(12),
+             13 => $expand!(13),
+             14 => $expand!(14),
+             15 => $expand!(15),
+             16 => $expand!(16),
+             17 => $expand!(17),
+             18 => $expand!(18),
+             19 => $expand!(19),
+             20 => $expand!(20),
+             21 => $expand!(21),
+             22 => $expand!(22),
+             23 => $expand!(23),
+             24 => $expand!(24),
+             25 => $expand!(25),
+             26 => $expand!(26),
+             27 => $expand!(27),
+             28 => $expand!(28),
+             29 => $expand!(29),
+             30 => $expand!(30),
+             31 => $expand!(31),
+             32 => $expand!(32),
+             33 => $expand!(33),
+             34 => $expand!(34),
+             35 => $expand!(35),
+             36 => $expand!(36),
+             37 => $expand!(37),
+             38 => $expand!(38),
+             39 => $expand!(39),
+             40 => $expand!(40),
+             41 => $expand!(41),
+             42 => $expand!(42),
+             43 => $expand!(43),
+             44 => $expand!(44),
+             45 => $expand!(45),
+             46 => $expand!(46),
+             47 => $expand!(47),
+             48 => $expand!(48),
+             49 => $expand!(49),
+             50 => $expand!(50),
+             51 => $expand!(51),
+             52 => $expand!(52),
+             53 => $expand!(53),
+             54 => $expand!(54),
+             55 => $expand!(55),
+             56 => $expand!(56),
+             57 => $expand!(57),
+             58 => $expand!(58),
+             59 => $expand!(59),
+             60 => $expand!(60),
+             61 => $expand!(61),
+             62 => $expand!(62),
+             63 => $expand!(63),
+             64 => $expand!(64),
+             65 => $expand!(65),
+             66 => $expand!(66),
+             67 => $expand!(67),
+             68 => $expand!(68),
+             69 => $expand!(69),
+             70 => $expand!(70),
+             71 => $expand!(71),
+             72 => $expand!(72),
+             73 => $expand!(73),
+             74 => $expand!(74),
+             75 => $expand!(75),
+             76 => $expand!(76),
+             77 => $expand!(77),
+             78 => $expand!(78),
+             79 => $expand!(79),
+             80 => $expand!(80),
+             81 => $expand!(81),
+             82 => $expand!(82),
+             83 => $expand!(83),
+             84 => $expand!(84),
+             85 => $expand!(85),
+             86 => $expand!(86),
+             87 => $expand!(87),
+             88 => $expand!(88),
+             89 => $expand!(89),
+             90 => $expand!(90),
+             91 => $expand!(91),
+             92 => $expand!(92),
+             93 => $expand!(93),
+             94 => $expand!(94),
+             95 => $expand!(95),
+             96 => $expand!(96),
+             97 => $expand!(97),
+             98 => $expand!(98),
+             99 => $expand!(99),
+             100 => $expand!(100),
+             101 => $expand!(101),
+             102 => $expand!(102),
+             103 => $expand!(103),
+             104 => $expand!(104),
+             105 => $expand!(105),
+             106 => $expand!(106),
+             107 => $expand!(107),
+             108 => $expand!(108),
+             109 => $expand!(109),
+             110 => $expand!(110),
+             111 => $expand!(111),
+             112 => $expand!(112),
+             113 => $expand!(113),
+             114 => $expand!(114),
+             115 => $expand!(115),
+             116 => $expand!(116),
+             117 => $expand!(117),
+             118 => $expand!(118),
+             119 => $expand!(119),
+             120 => $expand!(120),
+             121 => $expand!(121),
+             122 => $expand!(122),
+             123 => $expand!(123),
+             124 => $expand!(124),
+             125 => $expand!(125),
+             126 => $expand!(126),
+             127 => $expand!(127),
+             128 => $expand!(128),
+             129 => $expand!(129),
+             130 => $expand!(130),
+             131 => $expand!(131),
+             132 => $expand!(132),
+             133 => $expand!(133),
+             134 => $expand!(134),
+             135 => $expand!(135),
+             136 => $expand!(136),
+             137 => $expand!(137),
+             138 => $expand!(138),
+             139 => $expand!(139),
+             140 => $expand!(140),
+             141 => $expand!(141),
+             142 => $expand!(142),
+             143 => $expand!(143),
+             144 => $expand!(144),
+             145 => $expand!(145),
+             146 => $expand!(146),
+             147 => $expand!(147),
+             148 => $expand!(148),
+             149 => $expand!(149),
+             150 => $expand!(150),
+             151 => $expand!(151),
+             152 => $expand!(152),
+             153 => $expand!(153),
+             154 => $expand!(154),
+             155 => $expand!(155),
+             156 => $expand!(156),
+             157 => $expand!(157),
+             158 => $expand!(158),
+             159 => $expand!(159),
+             160 => $expand!(160),
+             161 => $expand!(161),
+             162 => $expand!(162),
+             163 => $expand!(163),
+             164 => $expand!(164),
+             165 => $expand!(165),
+             166 => $expand!(166),
+             167 => $expand!(167),
+             168 => $expand!(168),
+             169 => $expand!(169),
+             170 => $expand!(170),
+             171 => $expand!(171),
+             172 => $expand!(172),
+             173 => $expand!(173),
+             174 => $expand!(174),
+             175 => $expand!(175),
+             176 => $expand!(176),
+             177 => $expand!(177),
+             178 => $expand!(178),
+             179 => $expand!(179),
+             180 => $expand!(180),
+             181 => $expand!(181),
+             182 => $expand!(182),
+             183 => $expand!(183),
+             184 => $expand!(184),
+             185 => $expand!(185),
+             186 => $expand!(186),
+             187 => $expand!(187),
+             188 => $expand!(188),
+             189 => $expand!(189),
+             190 => $expand!(190),
+             191 => $expand!(191),
+             192 => $expand!(192),
+             193 => $expand!(193),
+             194 => $expand!(194),
+             195 => $expand!(195),
+             196 => $expand!(196),
+             197 => $expand!(197),
+             198 => $expand!(198),
+             199 => $expand!(199),
+             200 => $expand!(200),
+             201 => $expand!(201),
+             202 => $expand!(202),
+             203 => $expand!(203),
+             204 => $expand!(204),
+             205 => $expand!(205),
+             206 => $expand!(206),
+             207 => $expand!(207),
+             208 => $expand!(208),
+             209 => $expand!(209),
+             210 => $expand!(210),
+             211 => $expand!(211),
+             212 => $expand!(212),
+             213 => $expand!(213),
+             214 => $expand!(214),
+             215 => $expand!(215),
+             216 => $expand!(216),
+             217 => $expand!(217),
+             218 => $expand!(218),
+             219 => $expand!(219),
+             220 => $expand!(220),
+             221 => $expand!(221),
+             222 => $expand!(222),
+             223 => $expand!(223),
+             224 => $expand!(224),
+             225 => $expand!(225),
+             226 => $expand!(226),
+             227 => $expand!(227),
+             228 => $expand!(228),
+             229 => $expand!(229),
+             230 => $expand!(230),
+             231 => $expand!(231),
+             232 => $expand!(232),
+             233 => $expand!(233),
+             234 => $expand!(234),
+             235 => $expand!(235),
+             236 => $expand!(236),
+             237 => $expand!(237),
+             238 => $expand!(238),
+             239 => $expand!(239),
+             240 => $expand!(240),
+             241 => $expand!(241),
+             242 => $expand!(242),
+             243 => $expand!(243),
+             244 => $expand!(244),
+             245 => $expand!(245),
+             246 => $expand!(246),
+             247 => $expand!(247),
+             248 => $expand!(248),
+             249 => $expand!(249),
+             250 => $expand!(250),
+             251 => $expand!(251),
+             252 => $expand!(252),
+             253 => $expand!(253),
+             254 => $expand!(254),
+             255 => $expand!(255),
+             _ => panic!("Invalid sae value"),
+         }
+     };
+ }
+ 
+ #[cfg(test)]
+ macro_rules! assert_approx_eq {
+     ($a:expr, $b:expr, $eps:expr) => {{
+         let (a, b) = (&$a, &$b);
+         assert!(
+             (*a - *b).abs() < $eps,
+             "assertion failed: `(left !== right)` \
+              (left: `{:?}`, right: `{:?}`, expect diff: `{:?}`, real diff: `{:?}`)",
+             *a,
+             *b,
+             $eps,
+             (*a - *b).abs()
+         );
+     }};
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,633 ----
+ //! `x86` and `x86_64` intrinsics.
+ 
+ use crate::{intrinsics, marker::Sized, mem::transmute};
+ 
+ #[macro_use]
+ mod macros;
+ 
+ types! {
+     /// 128-bit wide integer vector type, x86-specific
+     ///
+     /// This type is the same as the `__m128i` type defined by Intel,
+     /// representing a 128-bit SIMD register. Usage of this type typically
+     /// corresponds to the `sse` and up target features for x86/x86_64.
+     ///
+     /// Internally this type may be viewed as:
+     ///
+     /// * `i8x16` - sixteen `i8` variables packed together
+     /// * `i16x8` - eight `i16` variables packed together
+     /// * `i32x4` - four `i32` variables packed together
+     /// * `i64x2` - two `i64` variables packed together
+     ///
+     /// (as well as unsigned versions). Each intrinsic may interpret the
+     /// internal bits differently, check the documentation of the intrinsic
+     /// to see how it's being used.
+     ///
+     /// Note that this means that an instance of `__m128i` typically just means
+     /// a "bag of bits" which is left up to interpretation at the point of use.
+     ///
+     /// Most intrinsics using `__m128i` are prefixed with `_mm_` and the
+     /// integer types tend to correspond to suffixes like "epi8" or "epi32".
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[cfg(target_arch = "x86")]
+     /// use std::arch::x86::*;
+     /// #[cfg(target_arch = "x86_64")]
+     /// use std::arch::x86_64::*;
+     ///
+     /// # fn main() {
+     /// # #[target_feature(enable = "sse2")]
+     /// # unsafe fn foo() {
+     /// let all_bytes_zero = _mm_setzero_si128();
+     /// let all_bytes_one = _mm_set1_epi8(1);
+     /// let four_i32 = _mm_set_epi32(1, 2, 3, 4);
+     /// # }
+     /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } }
+     /// # }
+     /// ```
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub struct __m128i(i64, i64);
+ 
+     /// 128-bit wide set of four `f32` types, x86-specific
+     ///
+     /// This type is the same as the `__m128` type defined by Intel,
+     /// representing a 128-bit SIMD register which internally is consisted of
+     /// four packed `f32` instances. Usage of this type typically corresponds
+     /// to the `sse` and up target features for x86/x86_64.
+     ///
+     /// Note that unlike `__m128i`, the integer version of the 128-bit
+     /// registers, this `__m128` type has *one* interpretation. Each instance
+     /// of `__m128` always corresponds to `f32x4`, or four `f32` types packed
+     /// together.
+     ///
+     /// Most intrinsics using `__m128` are prefixed with `_mm_` and are
+     /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
+     /// "pd" which is used for `__m128d`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[cfg(target_arch = "x86")]
+     /// use std::arch::x86::*;
+     /// #[cfg(target_arch = "x86_64")]
+     /// use std::arch::x86_64::*;
+     ///
+     /// # fn main() {
+     /// # #[target_feature(enable = "sse")]
+     /// # unsafe fn foo() {
+     /// let four_zeros = _mm_setzero_ps();
+     /// let four_ones = _mm_set1_ps(1.0);
+     /// let four_floats = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
+     /// # }
+     /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
+     /// # }
+     /// ```
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub struct __m128(f32, f32, f32, f32);
+ 
+     /// 128-bit wide set of two `f64` types, x86-specific
+     ///
+     /// This type is the same as the `__m128d` type defined by Intel,
+     /// representing a 128-bit SIMD register which internally is consisted of
+     /// two packed `f64` instances. Usage of this type typically corresponds
+     /// to the `sse` and up target features for x86/x86_64.
+     ///
+     /// Note that unlike `__m128i`, the integer version of the 128-bit
+     /// registers, this `__m128d` type has *one* interpretation. Each instance
+     /// of `__m128d` always corresponds to `f64x2`, or two `f64` types packed
+     /// together.
+     ///
+     /// Most intrinsics using `__m128d` are prefixed with `_mm_` and are
+     /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
+     /// "ps" which is used for `__m128`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[cfg(target_arch = "x86")]
+     /// use std::arch::x86::*;
+     /// #[cfg(target_arch = "x86_64")]
+     /// use std::arch::x86_64::*;
+     ///
+     /// # fn main() {
+     /// # #[target_feature(enable = "sse")]
+     /// # unsafe fn foo() {
+     /// let two_zeros = _mm_setzero_pd();
+     /// let two_ones = _mm_set1_pd(1.0);
+     /// let two_floats = _mm_set_pd(1.0, 2.0);
+     /// # }
+     /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
+     /// # }
+     /// ```
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub struct __m128d(f64, f64);
+ 
+     /// 256-bit wide integer vector type, x86-specific
+     ///
+     /// This type is the same as the `__m256i` type defined by Intel,
+     /// representing a 256-bit SIMD register. Usage of this type typically
+     /// corresponds to the `avx` and up target features for x86/x86_64.
+     ///
+     /// Internally this type may be viewed as:
+     ///
+     /// * `i8x32` - thirty two `i8` variables packed together
+     /// * `i16x16` - sixteen `i16` variables packed together
+     /// * `i32x8` - eight `i32` variables packed together
+     /// * `i64x4` - four `i64` variables packed together
+     ///
+     /// (as well as unsigned versions). Each intrinsic may interpret the
+     /// internal bits differently, check the documentation of the intrinsic
+     /// to see how it's being used.
+     ///
+     /// Note that this means that an instance of `__m256i` typically just means
+     /// a "bag of bits" which is left up to interpretation at the point of use.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[cfg(target_arch = "x86")]
+     /// use std::arch::x86::*;
+     /// #[cfg(target_arch = "x86_64")]
+     /// use std::arch::x86_64::*;
+     ///
+     /// # fn main() {
+     /// # #[target_feature(enable = "avx")]
+     /// # unsafe fn foo() {
+     /// let all_bytes_zero = _mm256_setzero_si256();
+     /// let all_bytes_one = _mm256_set1_epi8(1);
+     /// let eight_i32 = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+     /// # }
+     /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
+     /// # }
+     /// ```
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub struct __m256i(i64, i64, i64, i64);
+ 
+     /// 256-bit wide set of eight `f32` types, x86-specific
+     ///
+     /// This type is the same as the `__m256` type defined by Intel,
+     /// representing a 256-bit SIMD register which internally is consisted of
+     /// eight packed `f32` instances. Usage of this type typically corresponds
+     /// to the `avx` and up target features for x86/x86_64.
+     ///
+     /// Note that unlike `__m256i`, the integer version of the 256-bit
+     /// registers, this `__m256` type has *one* interpretation. Each instance
+     /// of `__m256` always corresponds to `f32x8`, or eight `f32` types packed
+     /// together.
+     ///
+     /// Most intrinsics using `__m256` are prefixed with `_mm256_` and are
+     /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
+     /// "pd" which is used for `__m256d`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[cfg(target_arch = "x86")]
+     /// use std::arch::x86::*;
+     /// #[cfg(target_arch = "x86_64")]
+     /// use std::arch::x86_64::*;
+     ///
+     /// # fn main() {
+     /// # #[target_feature(enable = "avx")]
+     /// # unsafe fn foo() {
+     /// let eight_zeros = _mm256_setzero_ps();
+     /// let eight_ones = _mm256_set1_ps(1.0);
+     /// let eight_floats = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
+     /// # }
+     /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
+     /// # }
+     /// ```
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub struct __m256(f32, f32, f32, f32, f32, f32, f32, f32);
+ 
+     /// 256-bit wide set of four `f64` types, x86-specific
+     ///
+     /// This type is the same as the `__m256d` type defined by Intel,
+     /// representing a 256-bit SIMD register which internally is consisted of
+     /// four packed `f64` instances. Usage of this type typically corresponds
+     /// to the `avx` and up target features for x86/x86_64.
+     ///
+     /// Note that unlike `__m256i`, the integer version of the 256-bit
+     /// registers, this `__m256d` type has *one* interpretation. Each instance
+     /// of `__m256d` always corresponds to `f64x4`, or four `f64` types packed
+     /// together.
+     ///
+     /// Most intrinsics using `__m256d` are prefixed with `_mm256_` and are
+     /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
+     /// "ps" which is used for `__m256`.
+     ///
+     /// # Examples
+     ///
+     /// ```
+     /// #[cfg(target_arch = "x86")]
+     /// use std::arch::x86::*;
+     /// #[cfg(target_arch = "x86_64")]
+     /// use std::arch::x86_64::*;
+     ///
+     /// # fn main() {
+     /// # #[target_feature(enable = "avx")]
+     /// # unsafe fn foo() {
+     /// let four_zeros = _mm256_setzero_pd();
+     /// let four_ones = _mm256_set1_pd(1.0);
+     /// let four_floats = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
+     /// # }
+     /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
+     /// # }
+     /// ```
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     pub struct __m256d(f64, f64, f64, f64);
+ 
+     /// 512-bit wide integer vector type, x86-specific
+     ///
+     /// This type is the same as the `__m512i` type defined by Intel,
+     /// representing a 512-bit SIMD register. Usage of this type typically
+     /// corresponds to the `avx512*` and up target features for x86/x86_64.
+     ///
+     /// Internally this type may be viewed as:
+     ///
+     /// * `i8x64` - sixty-four `i8` variables packed together
+     /// * `i16x32` - thirty-two `i16` variables packed together
+     /// * `i32x16` - sixteen `i32` variables packed together
+     /// * `i64x8` - eight `i64` variables packed together
+     ///
+     /// (as well as unsigned versions). Each intrinsic may interpret the
+     /// internal bits differently, check the documentation of the intrinsic
+     /// to see how it's being used.
+     ///
+     /// Note that this means that an instance of `__m512i` typically just means
+     /// a "bag of bits" which is left up to interpretation at the point of use.
+     pub struct __m512i(i64, i64, i64, i64, i64, i64, i64, i64);
+ 
+     /// 512-bit wide set of sixteen `f32` types, x86-specific
+     ///
+     /// This type is the same as the `__m512` type defined by Intel,
+     /// representing a 512-bit SIMD register which internally is consisted of
+     /// eight packed `f32` instances. Usage of this type typically corresponds
+     /// to the `avx512*` and up target features for x86/x86_64.
+     ///
+     /// Note that unlike `__m512i`, the integer version of the 512-bit
+     /// registers, this `__m512` type has *one* interpretation. Each instance
+     /// of `__m512` always corresponds to `f32x16`, or sixteen `f32` types
+     /// packed together.
+     ///
+     /// Most intrinsics using `__m512` are prefixed with `_mm512_` and are
+     /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
+     /// "pd" which is used for `__m512d`.
+     pub struct __m512(
+         f32, f32, f32, f32, f32, f32, f32, f32,
+         f32, f32, f32, f32, f32, f32, f32, f32,
+     );
+ 
+     /// 512-bit wide set of eight `f64` types, x86-specific
+     ///
+     /// This type is the same as the `__m512d` type defined by Intel,
+     /// representing a 512-bit SIMD register which internally is consisted of
+     /// eight packed `f64` instances. Usage of this type typically corresponds
+     /// to the `avx` and up target features for x86/x86_64.
+     ///
+     /// Note that unlike `__m512i`, the integer version of the 512-bit
+     /// registers, this `__m512d` type has *one* interpretation. Each instance
+     /// of `__m512d` always corresponds to `f64x4`, or eight `f64` types packed
+     /// together.
+     ///
+     /// Most intrinsics using `__m512d` are prefixed with `_mm512_` and are
+     /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
+     /// "ps" which is used for `__m512`.
+     pub struct __m512d(f64, f64, f64, f64, f64, f64, f64, f64);
+ }
+ 
+ /// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer
+ #[allow(non_camel_case_types)]
+ pub type __mmask16 = u16;
+ 
+ /// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer
+ #[allow(non_camel_case_types)]
+ pub type __mmask8 = u8;
+ 
+ /// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics.
+ #[allow(non_camel_case_types)]
+ pub type _MM_CMPINT_ENUM = i32;
+ 
+ /// The `MM_MANTISSA_NORM_ENUM` type used to specify mantissa normalized operations in AVX-512 intrinsics.
+ #[allow(non_camel_case_types)]
+ pub type _MM_MANTISSA_NORM_ENUM = i32;
+ 
+ /// The `MM_MANTISSA_SIGN_ENUM` type used to specify mantissa signed operations in AVX-512 intrinsics.
+ #[allow(non_camel_case_types)]
+ pub type _MM_MANTISSA_SIGN_ENUM = i32;
+ 
+ /// The `MM_PERM_ENUM` type used to specify shuffle operations in AVX-512 intrinsics.
+ #[allow(non_camel_case_types)]
+ pub type _MM_PERM_ENUM = i32;
+ 
+ #[cfg(test)]
+ mod test;
+ #[cfg(test)]
+ pub use self::test::*;
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait m128iExt: Sized {
+     fn as_m128i(self) -> __m128i;
+ 
+     #[inline]
+     fn as_u8x16(self) -> crate::core_arch::simd::u8x16 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_u64x2(self) -> crate::core_arch::simd::u64x2 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_i8x16(self) -> crate::core_arch::simd::i8x16 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ 
+     #[inline]
+     fn as_i64x2(self) -> crate::core_arch::simd::i64x2 {
+         unsafe { transmute(self.as_m128i()) }
+     }
+ }
+ 
+ impl m128iExt for __m128i {
+     #[inline]
+     fn as_m128i(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait m256iExt: Sized {
+     fn as_m256i(self) -> __m256i;
+ 
+     #[inline]
+     fn as_u8x32(self) -> crate::core_arch::simd::u8x32 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_u64x4(self) -> crate::core_arch::simd::u64x4 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_i8x32(self) -> crate::core_arch::simd::i8x32 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ 
+     #[inline]
+     fn as_i64x4(self) -> crate::core_arch::simd::i64x4 {
+         unsafe { transmute(self.as_m256i()) }
+     }
+ }
+ 
+ impl m256iExt for __m256i {
+     #[inline]
+     fn as_m256i(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdimd_internal", issue = "none")]
+ pub(crate) trait m128Ext: Sized {
+     fn as_m128(self) -> __m128;
+ 
+     #[inline]
+     fn as_f32x4(self) -> crate::core_arch::simd::f32x4 {
+         unsafe { transmute(self.as_m128()) }
+     }
+ }
+ 
+ impl m128Ext for __m128 {
+     #[inline]
+     fn as_m128(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait m256Ext: Sized {
+     fn as_m256(self) -> __m256;
+ 
+     #[inline]
+     fn as_f32x8(self) -> crate::core_arch::simd::f32x8 {
+         unsafe { transmute(self.as_m256()) }
+     }
+ }
+ 
+ impl m256Ext for __m256 {
+     #[inline]
+     fn as_m256(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait m512iExt: Sized {
+     fn as_m512i(self) -> __m512i;
+ 
+     #[inline]
+     fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
+         unsafe { transmute(self.as_m512i()) }
+     }
+ 
+     #[inline]
+     fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
+         unsafe { transmute(self.as_m512i()) }
+     }
+ 
+     #[inline]
+     fn as_u64x8(self) -> crate::core_arch::simd::u64x8 {
+         unsafe { transmute(self.as_m512i()) }
+     }
+ 
+     #[inline]
+     fn as_i64x8(self) -> crate::core_arch::simd::i64x8 {
+         unsafe { transmute(self.as_m512i()) }
+     }
+ }
+ 
+ impl m512iExt for __m512i {
+     #[inline]
+     fn as_m512i(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait m512Ext: Sized {
+     fn as_m512(self) -> __m512;
+ 
+     #[inline]
+     fn as_f32x16(self) -> crate::core_arch::simd::f32x16 {
+         unsafe { transmute(self.as_m512()) }
+     }
+ }
+ 
+ impl m512Ext for __m512 {
+     #[inline]
+     fn as_m512(self) -> Self {
+         self
+     }
+ }
+ 
+ #[allow(non_camel_case_types)]
+ #[unstable(feature = "stdsimd_internal", issue = "none")]
+ pub(crate) trait m512dExt: Sized {
+     fn as_m512d(self) -> __m512d;
+ 
+     #[inline]
+     fn as_f64x8(self) -> crate::core_arch::simd::f64x8 {
+         unsafe { transmute(self.as_m512d()) }
+     }
+ }
+ 
+ impl m512dExt for __m512d {
+     #[inline]
+     fn as_m512d(self) -> Self {
+         self
+     }
+ }
+ 
+ mod eflags;
+ pub use self::eflags::*;
+ 
+ mod fxsr;
+ pub use self::fxsr::*;
+ 
+ mod bswap;
+ pub use self::bswap::*;
+ 
+ mod rdtsc;
+ pub use self::rdtsc::*;
+ 
+ mod cpuid;
+ pub use self::cpuid::*;
+ mod xsave;
+ pub use self::xsave::*;
+ 
+ mod sse;
+ pub use self::sse::*;
+ mod sse2;
+ pub use self::sse2::*;
+ mod sse3;
+ pub use self::sse3::*;
+ mod ssse3;
+ pub use self::ssse3::*;
+ mod sse41;
+ pub use self::sse41::*;
+ mod sse42;
+ pub use self::sse42::*;
+ mod avx;
+ pub use self::avx::*;
+ mod avx2;
+ pub use self::avx2::*;
+ mod fma;
+ pub use self::fma::*;
+ 
+ mod abm;
+ pub use self::abm::*;
+ mod bmi1;
+ pub use self::bmi1::*;
+ 
+ mod bmi2;
+ pub use self::bmi2::*;
+ 
+ #[cfg(not(stdarch_intel_sde))]
+ mod sse4a;
+ #[cfg(not(stdarch_intel_sde))]
+ pub use self::sse4a::*;
+ 
+ #[cfg(not(stdarch_intel_sde))]
+ mod tbm;
+ #[cfg(not(stdarch_intel_sde))]
+ pub use self::tbm::*;
+ 
+ mod pclmulqdq;
+ pub use self::pclmulqdq::*;
+ 
+ mod aes;
+ pub use self::aes::*;
+ 
+ mod rdrand;
+ pub use self::rdrand::*;
+ 
+ mod sha;
+ pub use self::sha::*;
+ 
+ mod adx;
+ pub use self::adx::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Generates the trap instruction `UD2`
+ #[cfg_attr(test, assert_instr(ud2))]
+ #[inline]
+ pub unsafe fn ud2() -> ! {
+     intrinsics::abort()
+ }
+ 
+ mod avx512f;
+ pub use self::avx512f::*;
+ 
+ mod avx512ifma;
+ pub use self::avx512ifma::*;
+ 
+ mod bt;
+ pub use self::bt::*;
+ 
+ mod rtm;
+ pub use self::rtm::*;
+ 
+ mod f16c;
+ pub use self::f16c::*;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/pclmulqdq.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/pclmulqdq.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/pclmulqdq.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/pclmulqdq.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,74 ----
+ //! Carry-less Multiplication (CLMUL)
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref] (p. 4-241).
+ //!
+ //! [intel64_ref]: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ 
+ use crate::core_arch::x86::__m128i;
+ 
+ #[cfg(test)]
+ use crate::stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.pclmulqdq"]
+     fn pclmulqdq(a: __m128i, round_key: __m128i, imm8: u8) -> __m128i;
+ }
+ 
+ /// Performs a carry-less multiplication of two 64-bit polynomials over the
+ /// finite field GF(2^k).
+ ///
+ /// The immediate byte is used for determining which halves of `a` and `b`
+ /// should be used. Immediate bits other than 0 and 4 are ignored.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clmulepi64_si128)
+ #[inline]
+ #[target_feature(enable = "pclmulqdq")]
+ #[cfg_attr(all(test, not(target_os = "linux")), assert_instr(pclmulqdq, imm8 = 0))]
+ #[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmullqlqdq, imm8 = 0))]
+ #[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmulhqlqdq, imm8 = 1))]
+ #[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmullqhqdq, imm8 = 16))]
+ #[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmulhqhqdq, imm8 = 17))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_clmulepi64_si128(a: __m128i, b: __m128i, imm8: i32) -> __m128i {
+     macro_rules! call {
+         ($imm8:expr) => {
+             pclmulqdq(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     // The constants in the tests below are just bit patterns. They should not
+     // be interpreted as integers; signedness does not make sense for them, but
+     // __m128i happens to be defined in terms of signed integers.
+     #![allow(overflowing_literals)]
+ 
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "pclmulqdq")]
+     unsafe fn test_mm_clmulepi64_si128() {
+         // Constants taken from https://software.intel.com/sites/default/files/managed/72/cc/clmul-wp-rev-2.02-2014-04-20.pdf
+         let a = _mm_set_epi64x(0x7b5b546573745665, 0x63746f725d53475d);
+         let b = _mm_set_epi64x(0x4869285368617929, 0x5b477565726f6e5d);
+         let r00 = _mm_set_epi64x(0x1d4d84c85c3440c0, 0x929633d5d36f0451);
+         let r01 = _mm_set_epi64x(0x1bd17c8d556ab5a1, 0x7fa540ac2a281315);
+         let r10 = _mm_set_epi64x(0x1a2bf6db3a30862f, 0xbabf262df4b7d5c9);
+         let r11 = _mm_set_epi64x(0x1d1e1f2c592e7c45, 0xd66ee03e410fd4ed);
+ 
+         assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x00), r00);
+         assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x10), r01);
+         assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x01), r10);
+         assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x11), r11);
+ 
+         let a0 = _mm_set_epi64x(0x0000000000000000, 0x8000000000000000);
+         let r = _mm_set_epi64x(0x4000000000000000, 0x0000000000000000);
+         assert_eq_m128i(_mm_clmulepi64_si128(a0, a0, 0x00), r);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdrand.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdrand.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdrand.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdrand.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,75 ----
+ //! RDRAND and RDSEED instructions for returning random numbers from an Intel
+ //! on-chip hardware random number generator which has been seeded by an
+ //! on-chip entropy source.
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[allow(improper_ctypes)]
+ extern "unadjusted" {
+     #[link_name = "llvm.x86.rdrand.16"]
+     fn x86_rdrand16_step() -> (u16, i32);
+     #[link_name = "llvm.x86.rdrand.32"]
+     fn x86_rdrand32_step() -> (u32, i32);
+     #[link_name = "llvm.x86.rdseed.16"]
+     fn x86_rdseed16_step() -> (u16, i32);
+     #[link_name = "llvm.x86.rdseed.32"]
+     fn x86_rdseed32_step() -> (u32, i32);
+ }
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Read a hardware generated 16-bit random value and store the result in val.
+ /// Returns 1 if a random value was generated, and 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdrand16_step)
+ #[inline]
+ #[target_feature(enable = "rdrand")]
+ #[cfg_attr(test, assert_instr(rdrand))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdrand16_step(val: &mut u16) -> i32 {
+     let (v, flag) = x86_rdrand16_step();
+     *val = v;
+     flag
+ }
+ 
+ /// Read a hardware generated 32-bit random value and store the result in val.
+ /// Returns 1 if a random value was generated, and 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdrand32_step)
+ #[inline]
+ #[target_feature(enable = "rdrand")]
+ #[cfg_attr(test, assert_instr(rdrand))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdrand32_step(val: &mut u32) -> i32 {
+     let (v, flag) = x86_rdrand32_step();
+     *val = v;
+     flag
+ }
+ 
+ /// Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store
+ /// in val. Return 1 if a random value was generated, and 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdseed16_step)
+ #[inline]
+ #[target_feature(enable = "rdseed")]
+ #[cfg_attr(test, assert_instr(rdseed))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdseed16_step(val: &mut u16) -> i32 {
+     let (v, flag) = x86_rdseed16_step();
+     *val = v;
+     flag
+ }
+ 
+ /// Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store
+ /// in val. Return 1 if a random value was generated, and 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdseed32_step)
+ #[inline]
+ #[target_feature(enable = "rdseed")]
+ #[cfg_attr(test, assert_instr(rdseed))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdseed32_step(val: &mut u32) -> i32 {
+     let (v, flag) = x86_rdseed32_step();
+     *val = v;
+     flag
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdtsc.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdtsc.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdtsc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rdtsc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,77 ----
+ //! RDTSC instructions.
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Reads the current value of the processor’s time-stamp counter.
+ ///
+ /// The processor monotonically increments the time-stamp counter MSR
+ /// every clock cycle and resets it to 0 whenever the processor is
+ /// reset.
+ ///
+ /// The RDTSC instruction is not a serializing instruction. It does
+ /// not necessarily wait until all previous instructions have been
+ /// executed before reading the counter. Similarly, subsequent
+ /// instructions may begin execution before the read operation is
+ /// performed.
+ ///
+ /// On processors that support the Intel 64 architecture, the
+ /// high-order 32 bits of each of RAX and RDX are cleared.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdtsc)
+ #[inline]
+ #[cfg_attr(test, assert_instr(rdtsc))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdtsc() -> u64 {
+     rdtsc()
+ }
+ 
+ /// Reads the current value of the processor’s time-stamp counter and
+ /// the `IA32_TSC_AUX MSR`.
+ ///
+ /// The processor monotonically increments the time-stamp counter MSR
+ /// every clock cycle and resets it to 0 whenever the processor is
+ /// reset.
+ ///
+ /// The RDTSCP instruction waits until all previous instructions have
+ /// been executed before reading the counter. However, subsequent
+ /// instructions may begin execution before the read operation is
+ /// performed.
+ ///
+ /// On processors that support the Intel 64 architecture, the
+ /// high-order 32 bits of each of RAX, RDX, and RCX are cleared.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__rdtscp)
+ #[inline]
+ #[cfg_attr(test, assert_instr(rdtscp))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn __rdtscp(aux: *mut u32) -> u64 {
+     rdtscp(aux as *mut _)
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.rdtsc"]
+     fn rdtsc() -> u64;
+     #[link_name = "llvm.x86.rdtscp"]
+     fn rdtscp(aux: *mut u8) -> u64;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn _rdtsc() {
+         let r = rdtsc::_rdtsc();
+         assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn _rdtscp() {
+         let mut aux = 0;
+         let r = rdtsc::__rdtscp(&mut aux);
+         assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rtm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rtm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rtm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/rtm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,166 ----
+ //! Intel's Restricted Transactional Memory (RTM).
+ //!
+ //! This CPU feature is available on Intel Broadwell or later CPUs (and some Haswell).
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
+ //!
+ //! [Wikipedia][wikipedia_rtm] provides a quick overview of the assembly instructions, and
+ //! Intel's [programming considerations][intel_consid] details what sorts of instructions within a
+ //! transaction are likely to cause an abort.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [wikipedia_rtm]: https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions#Restricted_Transactional_Memory
+ //! [intel_consid]: https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-intel-transactional-synchronization-extensions-intel-tsx-programming-considerations
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ extern "C" {
+     #[link_name = "llvm.x86.xbegin"]
+     fn x86_xbegin() -> i32;
+     #[link_name = "llvm.x86.xend"]
+     fn x86_xend() -> ();
+     #[link_name = "llvm.x86.xabort"]
+     fn x86_xabort(imm8: i8) -> ();
+     #[link_name = "llvm.x86.xtest"]
+     fn x86_xtest() -> i32;
+ }
+ 
+ /// Transaction successfully started.
+ pub const _XBEGIN_STARTED: u32 = !0;
+ 
+ /// Transaction explicitly aborted with xabort. The parameter passed to xabort is available with
+ /// `_xabort_code(status)`.
+ #[allow(clippy::identity_op)]
+ pub const _XABORT_EXPLICIT: u32 = 1 << 0;
+ 
+ /// Transaction retry is possible.
+ pub const _XABORT_RETRY: u32 = 1 << 1;
+ 
+ /// Transaction abort due to a memory conflict with another thread.
+ pub const _XABORT_CONFLICT: u32 = 1 << 2;
+ 
+ /// Transaction abort due to the transaction using too much memory.
+ pub const _XABORT_CAPACITY: u32 = 1 << 3;
+ 
+ /// Transaction abort due to a debug trap.
+ pub const _XABORT_DEBUG: u32 = 1 << 4;
+ 
+ /// Transaction abort in a inner nested transaction.
+ pub const _XABORT_NESTED: u32 = 1 << 5;
+ 
+ /// Specifies the start of a restricted transactional memory (RTM) code region and returns a value
+ /// indicating status.
+ ///
+ /// [Intel's documentation](https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xbegin).
+ #[inline]
+ #[target_feature(enable = "rtm")]
+ #[cfg_attr(test, assert_instr(xbegin))]
+ pub unsafe fn _xbegin() -> u32 {
+     x86_xbegin() as _
+ }
+ 
+ /// Specifies the end of a restricted transactional memory (RTM) code region.
+ ///
+ /// [Intel's documentation](https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xend).
+ #[inline]
+ #[target_feature(enable = "rtm")]
+ #[cfg_attr(test, assert_instr(xend))]
+ pub unsafe fn _xend() {
+     x86_xend()
+ }
+ 
+ /// Forces a restricted transactional memory (RTM) region to abort.
+ ///
+ /// [Intel's documentation](https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xabort).
+ #[inline]
+ #[target_feature(enable = "rtm")]
+ #[cfg_attr(test, assert_instr(xabort, imm8 = 0x0))]
+ #[rustc_args_required_const(0)]
+ pub unsafe fn _xabort(imm8: u32) {
+     macro_rules! call {
+         ($imm8:expr) => {
+             x86_xabort($imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Queries whether the processor is executing in a transactional region identified by restricted
+ /// transactional memory (RTM) or hardware lock elision (HLE).
+ ///
+ /// [Intel's documentation](https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xtest).
+ #[inline]
+ #[target_feature(enable = "rtm")]
+ #[cfg_attr(test, assert_instr(xtest))]
+ pub unsafe fn _xtest() -> u8 {
+     x86_xtest() as _
+ }
+ 
+ /// Retrieves the parameter passed to [`_xabort`] when [`_xbegin`]'s status has the
+ /// `_XABORT_EXPLICIT` flag set.
+ #[inline]
+ pub const fn _xabort_code(status: u32) -> u32 {
+     (status >> 24) & 0xFF
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "rtm")]
+     unsafe fn test_xbegin_xend() {
+         let mut x = 0;
+         for _ in 0..10 {
+             let code = rtm::_xbegin();
+             if code == _XBEGIN_STARTED {
+                 x += 1;
+                 rtm::_xend();
+                 assert_eq!(x, 1);
+                 break;
+             }
+             assert_eq!(x, 0);
+         }
+     }
+ 
+     #[simd_test(enable = "rtm")]
+     unsafe fn test_xabort() {
+         const ABORT_CODE: u32 = 42;
+         // aborting outside a transactional region does nothing
+         _xabort(ABORT_CODE);
+ 
+         for _ in 0..10 {
+             let mut x = 0;
+             let code = rtm::_xbegin();
+             if code == _XBEGIN_STARTED {
+                 x += 1;
+                 rtm::_xabort(ABORT_CODE);
+             } else if code & _XABORT_EXPLICIT != 0 {
+                 let test_abort_code = rtm::_xabort_code(code);
+                 assert_eq!(test_abort_code, ABORT_CODE);
+             }
+             assert_eq!(x, 0);
+         }
+     }
+ 
+     #[simd_test(enable = "rtm")]
+     unsafe fn test_xtest() {
+         assert_eq!(_xtest(), 0);
+ 
+         for _ in 0..10 {
+             let code = rtm::_xbegin();
+             if code == _XBEGIN_STARTED {
+                 let in_tx = _xtest();
+                 rtm::_xend();
+ 
+                 // putting the assert inside the transaction would abort the transaction on fail
+                 // without any output/panic/etc
+                 assert_eq!(in_tx, 1);
+                 break;
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sha.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sha.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sha.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sha.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,228 ----
+ use crate::{
+     core_arch::{simd::*, x86::*},
+     mem::transmute,
+ };
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sha1msg1"]
+     fn sha1msg1(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sha1msg2"]
+     fn sha1msg2(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sha1nexte"]
+     fn sha1nexte(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sha1rnds4"]
+     fn sha1rnds4(a: i32x4, b: i32x4, c: i8) -> i32x4;
+     #[link_name = "llvm.x86.sha256msg1"]
+     fn sha256msg1(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sha256msg2"]
+     fn sha256msg2(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sha256rnds2"]
+     fn sha256rnds2(a: i32x4, b: i32x4, k: i32x4) -> i32x4;
+ }
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Performs an intermediate calculation for the next four SHA1 message values
+ /// (unsigned 32-bit integers) using previous message values from `a` and `b`,
+ /// and returning the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha1msg1_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha1msg1))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha1msg1_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(sha1msg1(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Performs the final calculation for the next four SHA1 message values
+ /// (unsigned 32-bit integers) using the intermediate result in `a` and the
+ /// previous message values in `b`, and returns the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha1msg2_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha1msg2))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha1msg2_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(sha1msg2(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Calculate SHA1 state variable E after four rounds of operation from the
+ /// current SHA1 state variable `a`, add that value to the scheduled values
+ /// (unsigned 32-bit integers) in `b`, and returns the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha1nexte_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha1nexte))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha1nexte_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(sha1nexte(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Performs four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D)
+ /// from `a` and some pre-computed sum of the next 4 round message values
+ /// (unsigned 32-bit integers), and state variable E from `b`, and return the
+ /// updated SHA1 state (A,B,C,D). `func` contains the logic functions and round
+ /// constants.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha1rnds4_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha1rnds4, func = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha1rnds4_epu32(a: __m128i, b: __m128i, func: i32) -> __m128i {
+     let a = a.as_i32x4();
+     let b = b.as_i32x4();
+     macro_rules! call {
+         ($imm2:expr) => {
+             sha1rnds4(a, b, $imm2)
+         };
+     }
+     let ret = constify_imm2!(func, call);
+     transmute(ret)
+ }
+ 
+ /// Performs an intermediate calculation for the next four SHA256 message values
+ /// (unsigned 32-bit integers) using previous message values from `a` and `b`,
+ /// and return the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha256msg1_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha256msg1))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha256msg1_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(sha256msg1(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Performs the final calculation for the next four SHA256 message values
+ /// (unsigned 32-bit integers) using previous message values from `a` and `b`,
+ /// and return the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha256msg2_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha256msg2))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha256msg2_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(sha256msg2(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Performs 2 rounds of SHA256 operation using an initial SHA256 state
+ /// (C,D,G,H) from `a`, an initial SHA256 state (A,B,E,F) from `b`, and a
+ /// pre-computed sum of the next 2 round message values (unsigned 32-bit
+ /// integers) and the corresponding round constants from `k`, and store the
+ /// updated SHA256 state (A,B,E,F) in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha256rnds2_epu32)
+ #[inline]
+ #[target_feature(enable = "sha")]
+ #[cfg_attr(test, assert_instr(sha256rnds2))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sha256rnds2_epu32(a: __m128i, b: __m128i, k: __m128i) -> __m128i {
+     transmute(sha256rnds2(a.as_i32x4(), b.as_i32x4(), k.as_i32x4()))
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std::{
+         f32,
+         f64::{self, NAN},
+         i32,
+         mem::{self, transmute},
+     };
+ 
+     use crate::{
+         core_arch::{simd::*, x86::*},
+         hint::black_box,
+     };
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha1msg1_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let expected = _mm_set_epi64x(0x98829f34f74ad457, 0xda2b1a44d0b5ad3c);
+         let r = _mm_sha1msg1_epu32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha1msg2_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let expected = _mm_set_epi64x(0xf714b202d863d47d, 0x90c30d946b3d3b35);
+         let r = _mm_sha1msg2_epu32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha1nexte_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let expected = _mm_set_epi64x(0x2589d5be923f82a4, 0x59f111f13956c25b);
+         let r = _mm_sha1nexte_epu32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha1rnds4_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let expected = _mm_set_epi64x(0x32b13cd8322f5268, 0xc54420862bd9246f);
+         let r = _mm_sha1rnds4_epu32(a, b, 0);
+         assert_eq_m128i(r, expected);
+ 
+         let expected = _mm_set_epi64x(0x6d4c43e56a3c25d9, 0xa7e00fb775cbd3fe);
+         let r = _mm_sha1rnds4_epu32(a, b, 1);
+         assert_eq_m128i(r, expected);
+ 
+         let expected = _mm_set_epi64x(0xb304e383c01222f4, 0x66f6b3b1f89d8001);
+         let r = _mm_sha1rnds4_epu32(a, b, 2);
+         assert_eq_m128i(r, expected);
+ 
+         let expected = _mm_set_epi64x(0x8189b758bfabfa79, 0xdb08f6e78cae098b);
+         let r = _mm_sha1rnds4_epu32(a, b, 3);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha256msg1_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let expected = _mm_set_epi64x(0xeb84973fd5cda67d, 0x2857b88f406b09ee);
+         let r = _mm_sha256msg1_epu32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha256msg2_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let expected = _mm_set_epi64x(0xb58777ce887fd851, 0x15d1ec8b73ac8450);
+         let r = _mm_sha256msg2_epu32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sha")]
+     #[allow(overflowing_literals)]
+     unsafe fn test_mm_sha256rnds2_epu32() {
+         let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98);
+         let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b);
+         let k = _mm_set_epi64x(0, 0x12835b01d807aa98);
+         let expected = _mm_set_epi64x(0xd3063037effb15ea, 0x187ee3db0d6d1d19);
+         let r = _mm_sha256rnds2_epu32(a, b, k);
+         assert_eq_m128i(r, expected);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,3303 ----
+ //! Streaming SIMD Extensions (SSE)
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     intrinsics, mem, ptr,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Adds the first component of `a` and `b`, the other components are copied
+ /// from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(addss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_ss(a: __m128, b: __m128) -> __m128 {
+     addss(a, b)
+ }
+ 
+ /// Adds __m128 vectors.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(addps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_ps(a: __m128, b: __m128) -> __m128 {
+     simd_add(a, b)
+ }
+ 
+ /// Subtracts the first component of `b` from `a`, the other components are
+ /// copied from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(subss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_ss(a: __m128, b: __m128) -> __m128 {
+     subss(a, b)
+ }
+ 
+ /// Subtracts __m128 vectors.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(subps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_ps(a: __m128, b: __m128) -> __m128 {
+     simd_sub(a, b)
+ }
+ 
+ /// Multiplies the first component of `a` and `b`, the other components are
+ /// copied from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(mulss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mul_ss(a: __m128, b: __m128) -> __m128 {
+     mulss(a, b)
+ }
+ 
+ /// Multiplies __m128 vectors.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(mulps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mul_ps(a: __m128, b: __m128) -> __m128 {
+     simd_mul(a, b)
+ }
+ 
+ /// Divides the first component of `b` by `a`, the other components are
+ /// copied from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(divss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_div_ss(a: __m128, b: __m128) -> __m128 {
+     divss(a, b)
+ }
+ 
+ /// Divides __m128 vectors.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(divps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_div_ps(a: __m128, b: __m128) -> __m128 {
+     simd_div(a, b)
+ }
+ 
+ /// Returns the square root of the first single-precision (32-bit)
+ /// floating-point element in `a`, the other elements are unchanged.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(sqrtss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sqrt_ss(a: __m128) -> __m128 {
+     sqrtss(a)
+ }
+ 
+ /// Returns the square root of packed single-precision (32-bit) floating-point
+ /// elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(sqrtps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sqrt_ps(a: __m128) -> __m128 {
+     sqrtps(a)
+ }
+ 
+ /// Returns the approximate reciprocal of the first single-precision
+ /// (32-bit) floating-point element in `a`, the other elements are unchanged.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(rcpss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_rcp_ss(a: __m128) -> __m128 {
+     rcpss(a)
+ }
+ 
+ /// Returns the approximate reciprocal of packed single-precision (32-bit)
+ /// floating-point elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(rcpps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_rcp_ps(a: __m128) -> __m128 {
+     rcpps(a)
+ }
+ 
+ /// Returns the approximate reciprocal square root of the fist single-precision
+ /// (32-bit) floating-point elements in `a`, the other elements are unchanged.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(rsqrtss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_rsqrt_ss(a: __m128) -> __m128 {
+     rsqrtss(a)
+ }
+ 
+ /// Returns the approximate reciprocal square root of packed single-precision
+ /// (32-bit) floating-point elements in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(rsqrtps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_rsqrt_ps(a: __m128) -> __m128 {
+     rsqrtps(a)
+ }
+ 
+ /// Compares the first single-precision (32-bit) floating-point element of `a`
+ /// and `b`, and return the minimum value in the first element of the return
+ /// value, the other elements are copied from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(minss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_ss(a: __m128, b: __m128) -> __m128 {
+     minss(a, b)
+ }
+ 
+ /// Compares packed single-precision (32-bit) floating-point elements in `a` and
+ /// `b`, and return the corresponding minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(minps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_ps(a: __m128, b: __m128) -> __m128 {
+     // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmin`.
+     minps(a, b)
+ }
+ 
+ /// Compares the first single-precision (32-bit) floating-point element of `a`
+ /// and `b`, and return the maximum value in the first element of the return
+ /// value, the other elements are copied from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(maxss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_ss(a: __m128, b: __m128) -> __m128 {
+     maxss(a, b)
+ }
+ 
+ /// Compares packed single-precision (32-bit) floating-point elements in `a` and
+ /// `b`, and return the corresponding maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(maxps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_ps(a: __m128, b: __m128) -> __m128 {
+     // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmax`.
+     maxps(a, b)
+ }
+ 
+ /// Bitwise AND of packed single-precision (32-bit) floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_and_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ // i586 only seems to generate plain `and` instructions, so ignore it.
+ #[cfg_attr(
+     all(test, any(target_arch = "x86_64", target_feature = "sse2")),
+     assert_instr(andps)
+ )]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_and_ps(a: __m128, b: __m128) -> __m128 {
+     let a: __m128i = mem::transmute(a);
+     let b: __m128i = mem::transmute(b);
+     mem::transmute(simd_and(a, b))
+ }
+ 
+ /// Bitwise AND-NOT of packed single-precision (32-bit) floating-point
+ /// elements.
+ ///
+ /// Computes `!a & b` for each bit in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_andnot_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ // i586 only seems to generate plain `not` and `and` instructions, so ignore
+ // it.
+ #[cfg_attr(
+     all(test, any(target_arch = "x86_64", target_feature = "sse2")),
+     assert_instr(andnps)
+ )]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_andnot_ps(a: __m128, b: __m128) -> __m128 {
+     let a: __m128i = mem::transmute(a);
+     let b: __m128i = mem::transmute(b);
+     let mask: __m128i = mem::transmute(i32x4::splat(-1));
+     mem::transmute(simd_and(simd_xor(mask, a), b))
+ }
+ 
+ /// Bitwise OR of packed single-precision (32-bit) floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_or_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ // i586 only seems to generate plain `or` instructions, so we ignore it.
+ #[cfg_attr(
+     all(test, any(target_arch = "x86_64", target_feature = "sse2")),
+     assert_instr(orps)
+ )]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_or_ps(a: __m128, b: __m128) -> __m128 {
+     let a: __m128i = mem::transmute(a);
+     let b: __m128i = mem::transmute(b);
+     mem::transmute(simd_or(a, b))
+ }
+ 
+ /// Bitwise exclusive OR of packed single-precision (32-bit) floating-point
+ /// elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_xor_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ // i586 only seems to generate plain `xor` instructions, so we ignore it.
+ #[cfg_attr(
+     all(test, any(target_arch = "x86_64", target_feature = "sse2")),
+     assert_instr(xorps)
+ )]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_xor_ps(a: __m128, b: __m128) -> __m128 {
+     let a: __m128i = mem::transmute(a);
+     let b: __m128i = mem::transmute(b);
+     mem::transmute(simd_xor(a, b))
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for equality. The lowest 32 bits of
+ /// the result will be `0xffffffff` if the two inputs are equal, or `0`
+ /// otherwise. The upper 96 bits of the result are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpeqss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 0)
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for less than. The lowest 32 bits
+ /// of the result will be `0xffffffff` if `a.extract(0)` is less than
+ /// `b.extract(0)`, or `0` otherwise. The upper 96 bits of the result are the
+ /// upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpltss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 1)
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for less than or equal. The lowest
+ /// 32 bits of the result will be `0xffffffff` if `a.extract(0)` is less than
+ /// or equal `b.extract(0)`, or `0` otherwise. The upper 96 bits of the result
+ /// are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmple_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpless))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmple_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 2)
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for greater than. The lowest 32
+ /// bits of the result will be `0xffffffff` if `a.extract(0)` is greater
+ /// than `b.extract(0)`, or `0` otherwise. The upper 96 bits of the result
+ /// are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpltss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_ss(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, cmpss(b, a, 1), [4, 1, 2, 3])
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for greater than or equal. The
+ /// lowest 32 bits of the result will be `0xffffffff` if `a.extract(0)` is
+ /// greater than or equal `b.extract(0)`, or `0` otherwise. The upper 96 bits
+ /// of the result are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpge_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpless))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpge_ss(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, cmpss(b, a, 2), [4, 1, 2, 3])
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for inequality. The lowest 32 bits
+ /// of the result will be `0xffffffff` if `a.extract(0)` is not equal to
+ /// `b.extract(0)`, or `0` otherwise. The upper 96 bits of the result are the
+ /// upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpneq_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpneqss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpneq_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 4)
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for not-less-than. The lowest 32
+ /// bits of the result will be `0xffffffff` if `a.extract(0)` is not less than
+ /// `b.extract(0)`, or `0` otherwise. The upper 96 bits of the result are the
+ /// upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnlt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnltss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnlt_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 5)
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for not-less-than-or-equal. The
+ /// lowest 32 bits of the result will be `0xffffffff` if `a.extract(0)` is not
+ /// less than or equal to `b.extract(0)`, or `0` otherwise. The upper 96 bits
+ /// of the result are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnle_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnless))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnle_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 6)
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for not-greater-than. The lowest 32
+ /// bits of the result will be `0xffffffff` if `a.extract(0)` is not greater
+ /// than `b.extract(0)`, or `0` otherwise. The upper 96 bits of the result are
+ /// the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpngt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnltss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpngt_ss(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, cmpss(b, a, 5), [4, 1, 2, 3])
+ }
+ 
+ /// Compares the lowest `f32` of both inputs for not-greater-than-or-equal. The
+ /// lowest 32 bits of the result will be `0xffffffff` if `a.extract(0)` is not
+ /// greater than or equal to `b.extract(0)`, or `0` otherwise. The upper 96
+ /// bits of the result are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnge_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnless))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnge_ss(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, cmpss(b, a, 6), [4, 1, 2, 3])
+ }
+ 
+ /// Checks if the lowest `f32` of both inputs are ordered. The lowest 32 bits of
+ /// the result will be `0xffffffff` if neither of `a.extract(0)` or
+ /// `b.extract(0)` is a NaN, or `0` otherwise. The upper 96 bits of the result
+ /// are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpord_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpordss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpord_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 7)
+ }
+ 
+ /// Checks if the lowest `f32` of both inputs are unordered. The lowest 32 bits
+ /// of the result will be `0xffffffff` if any of `a.extract(0)` or
+ /// `b.extract(0)` is a NaN, or `0` otherwise. The upper 96 bits of the result
+ /// are the upper 96 bits of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpunord_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpunordss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpunord_ss(a: __m128, b: __m128) -> __m128 {
+     cmpss(a, b, 3)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input elements
+ /// were equal, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpeqps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(a, b, 0)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is less than the corresponding element in `b`, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpltps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(a, b, 1)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is less than or equal to the corresponding element in `b`, or `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmple_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpleps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmple_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(a, b, 2)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is greater than the corresponding element in `b`, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpltps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(b, a, 1)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is greater than or equal to the corresponding element in `b`, or `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpge_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpleps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpge_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(b, a, 2)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input elements
+ /// are **not** equal, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpneq_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpneqps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpneq_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(a, b, 4)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is **not** less than the corresponding element in `b`, or `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnlt_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnltps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnlt_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(a, b, 5)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is **not** less than or equal to the corresponding element in `b`, or
+ /// `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnle_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnleps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnle_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(a, b, 6)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is **not** greater than the corresponding element in `b`, or `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpngt_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnltps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpngt_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(b, a, 5)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// The result in the output vector will be `0xffffffff` if the input element
+ /// in `a` is **not** greater than or equal to the corresponding element in `b`,
+ /// or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnge_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpnleps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnge_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(b, a, 6)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// Returns four floats that have one of two possible bit patterns. The element
+ /// in the output vector will be `0xffffffff` if the input elements in `a` and
+ /// `b` are ordered (i.e., neither of them is a NaN), or 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpord_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpordps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpord_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(b, a, 7)
+ }
+ 
+ /// Compares each of the four floats in `a` to the corresponding element in `b`.
+ /// Returns four floats that have one of two possible bit patterns. The element
+ /// in the output vector will be `0xffffffff` if the input elements in `a` and
+ /// `b` are unordered (i.e., at least on of them is a NaN), or 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpunord_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cmpunordps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpunord_ps(a: __m128, b: __m128) -> __m128 {
+     cmpps(b, a, 3)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if they are equal, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(comiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comieq_ss(a: __m128, b: __m128) -> i32 {
+     comieq_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is less than the one from `b`, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(comiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comilt_ss(a: __m128, b: __m128) -> i32 {
+     comilt_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is less than or equal to the one from `b`, or `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(comiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comile_ss(a: __m128, b: __m128) -> i32 {
+     comile_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is greater than the one from `b`, or `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(comiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comigt_ss(a: __m128, b: __m128) -> i32 {
+     comigt_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is greater than or equal to the one from `b`, or
+ /// `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(comiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comige_ss(a: __m128, b: __m128) -> i32 {
+     comige_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if they are **not** equal, or `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(comiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comineq_ss(a: __m128, b: __m128) -> i32 {
+     comineq_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if they are equal, or `0` otherwise. This instruction will not signal
+ /// an exception if either argument is a quiet NaN.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ucomiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomieq_ss(a: __m128, b: __m128) -> i32 {
+     ucomieq_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is less than the one from `b`, or `0` otherwise.
+ /// This instruction will not signal an exception if either argument is a quiet
+ /// NaN.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ucomiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomilt_ss(a: __m128, b: __m128) -> i32 {
+     ucomilt_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is less than or equal to the one from `b`, or `0`
+ /// otherwise. This instruction will not signal an exception if either argument
+ /// is a quiet NaN.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ucomiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomile_ss(a: __m128, b: __m128) -> i32 {
+     ucomile_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is greater than the one from `b`, or `0`
+ /// otherwise. This instruction will not signal an exception if either argument
+ /// is a quiet NaN.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ucomiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomigt_ss(a: __m128, b: __m128) -> i32 {
+     ucomigt_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if the value from `a` is greater than or equal to the one from `b`, or
+ /// `0` otherwise. This instruction will not signal an exception if either
+ /// argument is a quiet NaN.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ucomiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomige_ss(a: __m128, b: __m128) -> i32 {
+     ucomige_ss(a, b)
+ }
+ 
+ /// Compares two 32-bit floats from the low-order bits of `a` and `b`. Returns
+ /// `1` if they are **not** equal, or `0` otherwise. This instruction will not
+ /// signal an exception if either argument is a quiet NaN.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ucomiss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomineq_ss(a: __m128, b: __m128) -> i32 {
+     ucomineq_ss(a, b)
+ }
+ 
+ /// Converts the lowest 32 bit float in the input vector to a 32 bit integer.
+ ///
+ /// The result is rounded according to the current rounding mode. If the result
+ /// cannot be represented as a 32 bit integer the result will be `0x8000_0000`
+ /// (`i32::MIN`) or an invalid operation floating point exception if
+ /// unmasked (see [`_mm_setcsr`](fn._mm_setcsr.html)).
+ ///
+ /// This corresponds to the `CVTSS2SI` instruction (with 32 bit output).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_si32)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvtss2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtss_si32(a: __m128) -> i32 {
+     cvtss2si(a)
+ }
+ 
+ /// Alias for [`_mm_cvtss_si32`](fn._mm_cvtss_si32.html).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_ss2si)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvtss2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvt_ss2si(a: __m128) -> i32 {
+     _mm_cvtss_si32(a)
+ }
+ 
+ /// Converts the lowest 32 bit float in the input vector to a 32 bit integer
+ /// with
+ /// truncation.
+ ///
+ /// The result is rounded always using truncation (round towards zero). If the
+ /// result cannot be represented as a 32 bit integer the result will be
+ /// `0x8000_0000` (`i32::MIN`) or an invalid operation floating point
+ /// exception if unmasked (see [`_mm_setcsr`](fn._mm_setcsr.html)).
+ ///
+ /// This corresponds to the `CVTTSS2SI` instruction (with 32 bit output).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_si32)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvttss2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttss_si32(a: __m128) -> i32 {
+     cvttss2si(a)
+ }
+ 
+ /// Alias for [`_mm_cvttss_si32`](fn._mm_cvttss_si32.html).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtt_ss2si)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvttss2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtt_ss2si(a: __m128) -> i32 {
+     _mm_cvttss_si32(a)
+ }
+ 
+ /// Extracts the lowest 32 bit float from the input vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_f32)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ // No point in using assert_instrs. In Unix x86_64 calling convention this is a
+ // no-op, and on Windows it's just a `mov`.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtss_f32(a: __m128) -> f32 {
+     simd_extract(a, 0)
+ }
+ 
+ /// Converts a 32 bit integer to a 32 bit float. The result vector is the input
+ /// vector `a` with the lowest 32 bit float replaced by the converted integer.
+ ///
+ /// This intrinsic corresponds to the `CVTSI2SS` instruction (with 32 bit
+ /// input).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi32_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvtsi2ss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi32_ss(a: __m128, b: i32) -> __m128 {
+     cvtsi2ss(a, b)
+ }
+ 
+ /// Alias for [`_mm_cvtsi32_ss`](fn._mm_cvtsi32_ss.html).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvt_si2ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvtsi2ss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvt_si2ss(a: __m128, b: i32) -> __m128 {
+     _mm_cvtsi32_ss(a, b)
+ }
+ 
+ /// Construct a `__m128` with the lowest element set to `a` and the rest set to
+ /// zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_ss(a: f32) -> __m128 {
+     __m128(a, 0.0, 0.0, 0.0)
+ }
+ 
+ /// Construct a `__m128` with all element set to `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(shufps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set1_ps(a: f32) -> __m128 {
+     __m128(a, a, a, a)
+ }
+ 
+ /// Alias for [`_mm_set1_ps`](fn._mm_set1_ps.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_ps1)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(shufps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_ps1(a: f32) -> __m128 {
+     _mm_set1_ps(a)
+ }
+ 
+ /// Construct a `__m128` from four floating point values highest to lowest.
+ ///
+ /// Note that `a` will be the highest 32 bits of the result, and `d` the
+ /// lowest. This matches the standard way of writing bit patterns on x86:
+ ///
+ /// ```text
+ ///  bit    127 .. 96  95 .. 64  63 .. 32  31 .. 0
+ ///        +---------+---------+---------+---------+
+ ///        |    a    |    b    |    c    |    d    |   result
+ ///        +---------+---------+---------+---------+
+ /// ```
+ ///
+ /// Alternatively:
+ ///
+ /// ```text
+ /// let v = _mm_set_ps(d, c, b, a);
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(unpcklps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
+     __m128(d, c, b, a)
+ }
+ 
+ /// Construct a `__m128` from four floating point values lowest to highest.
+ ///
+ /// This matches the memory order of `__m128`, i.e., `a` will be the lowest 32
+ /// bits of the result, and `d` the highest.
+ ///
+ /// ```text
+ /// assert_eq!(__m128::new(a, b, c, d), _mm_setr_ps(a, b, c, d));
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(unpcklps))]
+ // On a 32-bit architecture it just copies the operands from the stack.
+ #[cfg_attr(all(test, target_arch = "x86"), assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setr_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {
+     __m128(a, b, c, d)
+ }
+ 
+ /// Construct a `__m128` with all elements initialized to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(xorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setzero_ps() -> __m128 {
+     __m128(0.0, 0.0, 0.0, 0.0)
+ }
+ 
+ /// A utility function for creating masks to use with Intel shuffle and
+ /// permute intrinsics.
+ #[inline]
+ #[allow(non_snake_case)]
+ #[unstable(feature = "stdarch", issue = "27731")]
+ pub const fn _MM_SHUFFLE(z: u32, y: u32, x: u32, w: u32) -> i32 {
+     ((z << 6) | (y << 4) | (x << 2) | w) as i32
+ }
+ 
+ /// Shuffles packed single-precision (32-bit) floating-point elements in `a` and
+ /// `b` using `mask`.
+ ///
+ /// The lower half of result takes values from `a` and the higher half from
+ /// `b`. Mask is split to 2 control bits each to index the element from inputs.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_ps)
+ ///
+ /// Note that there appears to be a mistake within Intel's Intrinsics Guide.
+ /// `_mm_shuffle_ps` is supposed to take an `i32` instead of an `u32`
+ /// as is the case for [other shuffle intrinsics](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_).
+ /// Performing an implicit type conversion between an unsigned integer and a signed integer
+ /// does not cause a problem in C, however Rust's commitment to strong typing does not allow this.
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(shufps, mask = 3))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_shuffle_ps(a: __m128, b: __m128, mask: i32) -> __m128 {
+     let mask = (mask & 0xFF) as u8;
+ 
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             simd_shuffle4(a, b, [$x01, $x23, $x45, $x67])
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (mask >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 4),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 5),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 6),
+                 _ => shuffle_done!($x01, $x23, $x45, 7),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (mask >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 4),
+                 0b01 => shuffle_x67!($x01, $x23, 5),
+                 0b10 => shuffle_x67!($x01, $x23, 6),
+                 _ => shuffle_x67!($x01, $x23, 7),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (mask >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     match mask & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     }
+ }
+ 
+ /// Unpacks and interleave single-precision (32-bit) floating-point elements
+ /// from the higher half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(unpckhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpackhi_ps(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, b, [2, 6, 3, 7])
+ }
+ 
+ /// Unpacks and interleave single-precision (32-bit) floating-point elements
+ /// from the lower half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(unpcklps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpacklo_ps(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, b, [0, 4, 1, 5])
+ }
+ 
+ /// Combine higher half of `a` and `b`. The highwe half of `b` occupies the
+ /// lower half of result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movehl_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movhlps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movehl_ps(a: __m128, b: __m128) -> __m128 {
+     // TODO; figure why this is a different instruction on Windows?
+     simd_shuffle4(a, b, [6, 7, 2, 3])
+ }
+ 
+ /// Combine lower half of `a` and `b`. The lower half of `b` occupies the
+ /// higher half of result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movelh_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movelh_ps(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, b, [0, 1, 4, 5])
+ }
+ 
+ /// Returns a mask of the most significant bit of each element in `a`.
+ ///
+ /// The mask is stored in the 4 least significant bits of the return value.
+ /// All other bits are set to `0`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movemask_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ // FIXME: LLVM9 trunk has the following bug:
+ // https://github.com/rust-lang/stdarch/issues/794
+ // so we only temporarily test this on i686 and x86_64 but not on i586:
+ #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(movmskps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movemask_ps(a: __m128) -> i32 {
+     movmskps(a)
+ }
+ 
+ /// Construct a `__m128` with the lowest element read from `p` and the other
+ /// elements set to zero.
+ ///
+ /// This corresponds to instructions `VMOVSS` / `MOVSS`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load_ss(p: *const f32) -> __m128 {
+     __m128(*p, 0.0, 0.0, 0.0)
+ }
+ 
+ /// Construct a `__m128` by duplicating the value read from `p` into all
+ /// elements.
+ ///
+ /// This corresponds to instructions `VMOVSS` / `MOVSS` followed by some
+ /// shuffling.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load1_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load1_ps(p: *const f32) -> __m128 {
+     let a = *p;
+     __m128(a, a, a, a)
+ }
+ 
+ /// Alias for [`_mm_load1_ps`](fn._mm_load1_ps.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_ps1)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load_ps1(p: *const f32) -> __m128 {
+     _mm_load1_ps(p)
+ }
+ 
+ /// Loads four `f32` values from *aligned* memory into a `__m128`. If the
+ /// pointer is not aligned to a 128-bit boundary (16 bytes) a general
+ /// protection fault will be triggered (fatal program crash).
+ ///
+ /// Use [`_mm_loadu_ps`](fn._mm_loadu_ps.html) for potentially unaligned
+ /// memory.
+ ///
+ /// This corresponds to instructions `VMOVAPS` / `MOVAPS`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_load_ps(p: *const f32) -> __m128 {
+     *(p as *const __m128)
+ }
+ 
+ /// Loads four `f32` values from memory into a `__m128`. There are no
+ /// restrictions
+ /// on memory alignment. For aligned memory
+ /// [`_mm_load_ps`](fn._mm_load_ps.html)
+ /// may be faster.
+ ///
+ /// This corresponds to instructions `VMOVUPS` / `MOVUPS`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadu_ps(p: *const f32) -> __m128 {
+     // Note: Using `*p` would require `f32` alignment, but `movups` has no
+     // alignment restrictions.
+     let mut dst = _mm_undefined_ps();
+     ptr::copy_nonoverlapping(
+         p as *const u8,
+         &mut dst as *mut __m128 as *mut u8,
+         mem::size_of::<__m128>(),
+     );
+     dst
+ }
+ 
+ /// Loads four `f32` values from aligned memory into a `__m128` in reverse
+ /// order.
+ ///
+ /// If the pointer is not aligned to a 128-bit boundary (16 bytes) a general
+ /// protection fault will be triggered (fatal program crash).
+ ///
+ /// Functionally equivalent to the following code sequence (assuming `p`
+ /// satisfies the alignment restrictions):
+ ///
+ /// ```text
+ /// let a0 = *p;
+ /// let a1 = *p.offset(1);
+ /// let a2 = *p.offset(2);
+ /// let a3 = *p.offset(3);
+ /// __m128::new(a3, a2, a1, a0)
+ /// ```
+ ///
+ /// This corresponds to instructions `VMOVAPS` / `MOVAPS` followed by some
+ /// shuffling.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadr_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
+     let a = _mm_load_ps(p);
+     simd_shuffle4(a, a, [3, 2, 1, 0])
+ }
+ 
+ /// Loads unaligned 64-bits of integer data from memory into new vector.
+ ///
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_si64)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(all(test, not(target_arch = "x86")), assert_instr(movq))]
+ #[stable(feature = "simd_x86_mm_loadu_si64", since = "1.46.0")]
+ pub unsafe fn _mm_loadu_si64(mem_addr: *const u8) -> __m128i {
+     transmute(i64x2(0, ptr::read_unaligned(mem_addr as *const i64)))
+ }
+ 
+ /// Stores the lowest 32 bit float of `a` into memory.
+ ///
+ /// This intrinsic corresponds to the `MOVSS` instruction.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_store_ss(p: *mut f32, a: __m128) {
+     *p = simd_extract(a, 0);
+ }
+ 
+ /// Stores the lowest 32 bit float of `a` repeated four times into *aligned*
+ /// memory.
+ ///
+ /// If the pointer is not aligned to a 128-bit boundary (16 bytes) a general
+ /// protection fault will be triggered (fatal program crash).
+ ///
+ /// Functionally equivalent to the following code sequence (assuming `p`
+ /// satisfies the alignment restrictions):
+ ///
+ /// ```text
+ /// let x = a.extract(0);
+ /// *p = x;
+ /// *p.offset(1) = x;
+ /// *p.offset(2) = x;
+ /// *p.offset(3) = x;
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store1_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
+     let b: __m128 = simd_shuffle4(a, a, [0, 0, 0, 0]);
+     *(p as *mut __m128) = b;
+ }
+ 
+ /// Alias for [`_mm_store1_ps`](fn._mm_store1_ps.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_ps1)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
+     _mm_store1_ps(p, a);
+ }
+ 
+ /// Stores four 32-bit floats into *aligned* memory.
+ ///
+ /// If the pointer is not aligned to a 128-bit boundary (16 bytes) a general
+ /// protection fault will be triggered (fatal program crash).
+ ///
+ /// Use [`_mm_storeu_ps`](fn._mm_storeu_ps.html) for potentially unaligned
+ /// memory.
+ ///
+ /// This corresponds to instructions `VMOVAPS` / `MOVAPS`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_store_ps(p: *mut f32, a: __m128) {
+     *(p as *mut __m128) = a;
+ }
+ 
+ /// Stores four 32-bit floats into memory. There are no restrictions on memory
+ /// alignment. For aligned memory [`_mm_store_ps`](fn._mm_store_ps.html) may be
+ /// faster.
+ ///
+ /// This corresponds to instructions `VMOVUPS` / `MOVUPS`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_storeu_ps(p: *mut f32, a: __m128) {
+     ptr::copy_nonoverlapping(
+         &a as *const __m128 as *const u8,
+         p as *mut u8,
+         mem::size_of::<__m128>(),
+     );
+ }
+ 
+ /// Stores four 32-bit floats into *aligned* memory in reverse order.
+ ///
+ /// If the pointer is not aligned to a 128-bit boundary (16 bytes) a general
+ /// protection fault will be triggered (fatal program crash).
+ ///
+ /// Functionally equivalent to the following code sequence (assuming `p`
+ /// satisfies the alignment restrictions):
+ ///
+ /// ```text
+ /// *p = a.extract(3);
+ /// *p.offset(1) = a.extract(2);
+ /// *p.offset(2) = a.extract(1);
+ /// *p.offset(3) = a.extract(0);
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storer_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_storer_ps(p: *mut f32, a: __m128) {
+     let b: __m128 = simd_shuffle4(a, a, [3, 2, 1, 0]);
+     *(p as *mut __m128) = b;
+ }
+ 
+ /// Returns a `__m128` with the first component from `b` and the remaining
+ /// components from `a`.
+ ///
+ /// In other words for any `a` and `b`:
+ /// ```text
+ /// _mm_move_ss(a, b) == a.replace(0, b.extract(0))
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_move_ss(a: __m128, b: __m128) -> __m128 {
+     simd_shuffle4(a, b, [4, 1, 2, 3])
+ }
+ 
+ /// Performs a serializing operation on all store-to-memory instructions that
+ /// were issued prior to this instruction.
+ ///
+ /// Guarantees that every store instruction that precedes, in program order, is
+ /// globally visible before any store instruction which follows the fence in
+ /// program order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sfence)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(sfence))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sfence() {
+     sfence()
+ }
+ 
+ /// Gets the unsigned 32-bit value of the MXCSR control and status register.
+ ///
+ /// For more info see [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getcsr)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(stmxcsr))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_getcsr() -> u32 {
+     let mut result = 0_i32;
+     stmxcsr((&mut result) as *mut _ as *mut i8);
+     result as u32
+ }
+ 
+ /// Sets the MXCSR register with the 32-bit unsigned integer value.
+ ///
+ /// This register constrols how SIMD instructions handle floating point
+ /// operations. Modifying this register only affects the current thread.
+ ///
+ /// It contains several groups of flags:
+ ///
+ /// * *Exception flags* report which exceptions occurred since last they were
+ /// reset.
+ ///
+ /// * *Masking flags* can be used to mask (ignore) certain exceptions. By
+ /// default
+ /// these flags are all set to 1, so all exceptions are masked. When an
+ /// an exception is masked, the processor simply sets the exception flag and
+ /// continues the operation. If the exception is unmasked, the flag is also set
+ /// but additionally an exception handler is invoked.
+ ///
+ /// * *Rounding mode flags* control the rounding mode of floating point
+ /// instructions.
+ ///
+ /// * The *denormals-are-zero mode flag* turns all numbers which would be
+ /// denormalized (exponent bits are all zeros) into zeros.
+ ///
+ /// ## Exception Flags
+ ///
+ /// * `_MM_EXCEPT_INVALID`: An invalid operation was performed (e.g., dividing
+ ///   Infinity by Infinity).
+ ///
+ /// * `_MM_EXCEPT_DENORM`: An operation attempted to operate on a denormalized
+ ///   number. Mainly this can cause loss of precision.
+ ///
+ /// * `_MM_EXCEPT_DIV_ZERO`: Division by zero occured.
+ ///
+ /// * `_MM_EXCEPT_OVERFLOW`: A numeric overflow exception occured, i.e., a
+ /// result was too large to be represented (e.g., an `f32` with absolute
+ /// value
+ ///   greater than `2^128`).
+ ///
+ /// * `_MM_EXCEPT_UNDERFLOW`: A numeric underflow exception occured, i.e., a
+ /// result was too small to be represented in a normalized way (e.g., an
+ /// `f32`
+ ///   with absulte value smaller than `2^-126`.)
+ ///
+ /// * `_MM_EXCEPT_INEXACT`: An inexact-result exception occured (a.k.a.
+ ///   precision exception). This means some precision was lost due to rounding.
+ ///   For example, the fraction `1/3` cannot be represented accurately in a
+ ///   32 or 64 bit float and computing it would cause this exception to be
+ ///   raised. Precision exceptions are very common, so they are usually masked.
+ ///
+ /// Exception flags can be read and set using the convenience functions
+ /// `_MM_GET_EXCEPTION_STATE` and `_MM_SET_EXCEPTION_STATE`. For example, to
+ /// check if an operation caused some overflow:
+ ///
+ /// ```rust,ignore
+ /// _MM_SET_EXCEPTION_STATE(0); // clear all exception flags
+ ///                             // perform calculations
+ /// if _MM_GET_EXCEPTION_STATE() & _MM_EXCEPT_OVERFLOW != 0 {
+ ///     // handle overflow
+ /// }
+ /// ```
+ ///
+ /// ## Masking Flags
+ ///
+ /// There is one masking flag for each exception flag: `_MM_MASK_INVALID`,
+ /// `_MM_MASK_DENORM`, `_MM_MASK_DIV_ZERO`, `_MM_MASK_OVERFLOW`,
+ /// `_MM_MASK_UNDERFLOW`, `_MM_MASK_INEXACT`.
+ ///
+ /// A single masking bit can be set via
+ ///
+ /// ```rust,ignore
+ /// _MM_SET_EXCEPTION_MASK(_MM_MASK_UNDERFLOW);
+ /// ```
+ ///
+ /// However, since mask bits are by default all set to 1, it is more common to
+ /// want to *disable* certain bits. For example, to unmask the underflow
+ /// exception, use:
+ ///
+ /// ```rust,ignore
+ /// _mm_setcsr(_mm_getcsr() & !_MM_MASK_UNDERFLOW); // unmask underflow
+ /// exception
+ /// ```
+ ///
+ /// Warning: an unmasked exception will cause an exception handler to be
+ /// called.
+ /// The standard handler will simply terminate the process. So, in this case
+ /// any underflow exception would terminate the current process with something
+ /// like `signal: 8, SIGFPE: erroneous arithmetic operation`.
+ ///
+ /// ## Rounding Mode
+ ///
+ /// The rounding mode is describe using two bits. It can be read and set using
+ /// the convenience wrappers `_MM_GET_ROUNDING_MODE()` and
+ /// `_MM_SET_ROUNDING_MODE(mode)`.
+ ///
+ /// The rounding modes are:
+ ///
+ /// * `_MM_ROUND_NEAREST`: (default) Round to closest to the infinite precision
+ ///   value. If two values are equally close, round to even (i.e., least
+ ///   significant bit will be zero).
+ ///
+ /// * `_MM_ROUND_DOWN`: Round toward negative Infinity.
+ ///
+ /// * `_MM_ROUND_UP`: Round toward positive Infinity.
+ ///
+ /// * `_MM_ROUND_TOWARD_ZERO`: Round towards zero (truncate).
+ ///
+ /// Example:
+ ///
+ /// ```rust,ignore
+ /// _MM_SET_ROUNDING_MODE(_MM_ROUND_DOWN)
+ /// ```
+ ///
+ /// ## Denormals-are-zero/Flush-to-zero Mode
+ ///
+ /// If this bit is set, values that would be denormalized will be set to zero
+ /// instead. This is turned off by default.
+ ///
+ /// You can read and enable/disable this mode via the helper functions
+ /// `_MM_GET_FLUSH_ZERO_MODE()` and `_MM_SET_FLUSH_ZERO_MODE()`:
+ ///
+ /// ```rust,ignore
+ /// _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_OFF); // turn off (default)
+ /// _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON); // turn on
+ /// ```
+ ///
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setcsr)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(ldmxcsr))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setcsr(val: u32) {
+     ldmxcsr(&val as *const _ as *const i8);
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_INVALID: u32 = 0x0001;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_DENORM: u32 = 0x0002;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_DIV_ZERO: u32 = 0x0004;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_OVERFLOW: u32 = 0x0008;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_UNDERFLOW: u32 = 0x0010;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_INEXACT: u32 = 0x0020;
+ /// See [`_MM_GET_EXCEPTION_STATE`](fn._MM_GET_EXCEPTION_STATE.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_EXCEPT_MASK: u32 = 0x003f;
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_INVALID: u32 = 0x0080;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_DENORM: u32 = 0x0100;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_DIV_ZERO: u32 = 0x0200;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_OVERFLOW: u32 = 0x0400;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_UNDERFLOW: u32 = 0x0800;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_INEXACT: u32 = 0x1000;
+ /// See [`_MM_GET_EXCEPTION_MASK`](fn._MM_GET_EXCEPTION_MASK.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_MASK_MASK: u32 = 0x1f80;
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_ROUND_NEAREST: u32 = 0x0000;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_ROUND_DOWN: u32 = 0x2000;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_ROUND_UP: u32 = 0x4000;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_ROUND_TOWARD_ZERO: u32 = 0x6000;
+ 
+ /// See [`_MM_GET_ROUNDING_MODE`](fn._MM_GET_ROUNDING_MODE.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_ROUND_MASK: u32 = 0x6000;
+ 
+ /// See [`_MM_GET_FLUSH_ZERO_MODE`](fn._MM_GET_FLUSH_ZERO_MODE.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FLUSH_ZERO_MASK: u32 = 0x8000;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FLUSH_ZERO_ON: u32 = 0x8000;
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FLUSH_ZERO_OFF: u32 = 0x0000;
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_GET_EXCEPTION_MASK)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_GET_EXCEPTION_MASK() -> u32 {
+     _mm_getcsr() & _MM_MASK_MASK
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_GET_EXCEPTION_STATE)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_GET_EXCEPTION_STATE() -> u32 {
+     _mm_getcsr() & _MM_EXCEPT_MASK
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_GET_FLUSH_ZERO_MODE)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_GET_FLUSH_ZERO_MODE() -> u32 {
+     _mm_getcsr() & _MM_FLUSH_ZERO_MASK
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_GET_ROUNDING_MODE)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_GET_ROUNDING_MODE() -> u32 {
+     _mm_getcsr() & _MM_ROUND_MASK
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_SET_EXCEPTION_MASK)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_SET_EXCEPTION_MASK(x: u32) {
+     _mm_setcsr((_mm_getcsr() & !_MM_MASK_MASK) | x)
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_SET_EXCEPTION_STATE)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_SET_EXCEPTION_STATE(x: u32) {
+     _mm_setcsr((_mm_getcsr() & !_MM_EXCEPT_MASK) | x)
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_SET_FLUSH_ZERO_MODE)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_SET_FLUSH_ZERO_MODE(x: u32) {
+     let val = (_mm_getcsr() & !_MM_FLUSH_ZERO_MASK) | x;
+     // println!("setting csr={:x}", val);
+     _mm_setcsr(val)
+ }
+ 
+ /// See [`_mm_setcsr`](fn._mm_setcsr.html)
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_SET_ROUNDING_MODE)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_SET_ROUNDING_MODE(x: u32) {
+     _mm_setcsr((_mm_getcsr() & !_MM_ROUND_MASK) | x)
+ }
+ 
+ /// See [`_mm_prefetch`](fn._mm_prefetch.html).
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_HINT_T0: i32 = 3;
+ 
+ /// See [`_mm_prefetch`](fn._mm_prefetch.html).
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_HINT_T1: i32 = 2;
+ 
+ /// See [`_mm_prefetch`](fn._mm_prefetch.html).
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_HINT_T2: i32 = 1;
+ 
+ /// See [`_mm_prefetch`](fn._mm_prefetch.html).
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_HINT_NTA: i32 = 0;
+ 
+ /// Fetch the cache line that contains address `p` using the given `strategy`.
+ ///
+ /// The `strategy` must be one of:
+ ///
+ /// * [`_MM_HINT_T0`](constant._MM_HINT_T0.html): Fetch into all levels of the
+ ///   cache hierarchy.
+ ///
+ /// * [`_MM_HINT_T1`](constant._MM_HINT_T1.html): Fetch into L2 and higher.
+ ///
+ /// * [`_MM_HINT_T2`](constant._MM_HINT_T2.html): Fetch into L3 and higher or
+ /// an   implementation-specific choice (e.g., L2 if there is no L3).
+ ///
+ /// * [`_MM_HINT_NTA`](constant._MM_HINT_NTA.html): Fetch data using the
+ ///   non-temporal access (NTA) hint. It may be a place closer than main memory
+ ///   but outside of the cache hierarchy. This is used to reduce access latency
+ ///   without polluting the cache.
+ ///
+ /// The actual implementation depends on the particular CPU. This instruction
+ /// is considered a hint, so the CPU is also free to simply ignore the request.
+ ///
+ /// The amount of prefetched data depends on the cache line size of the
+ /// specific CPU, but it will be at least 32 bytes.
+ ///
+ /// Common caveats:
+ ///
+ /// * Most modern CPUs already automatically prefetch data based on predicted
+ ///   access patterns.
+ ///
+ /// * Data is usually not fetched if this would cause a TLB miss or a page
+ ///   fault.
+ ///
+ /// * Too much prefetching can cause unnecessary cache evictions.
+ ///
+ /// * Prefetching may also fail if there are not enough memory-subsystem
+ ///   resources (e.g., request buffers).
+ ///
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_prefetch)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(prefetcht0, strategy = _MM_HINT_T0))]
+ #[cfg_attr(test, assert_instr(prefetcht1, strategy = _MM_HINT_T1))]
+ #[cfg_attr(test, assert_instr(prefetcht2, strategy = _MM_HINT_T2))]
+ #[cfg_attr(test, assert_instr(prefetchnta, strategy = _MM_HINT_NTA))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_prefetch(p: *const i8, strategy: i32) {
+     // The `strategy` must be a compile-time constant, so we use a short form
+     // of `constify_imm8!` for now.
+     // We use the `llvm.prefetch` instrinsic with `rw` = 0 (read), and
+     // `cache type` = 1 (data cache). `locality` is based on our `strategy`.
+     macro_rules! pref {
+         ($imm8:expr) => {
+             match $imm8 {
+                 0 => prefetch(p, 0, 0, 1),
+                 1 => prefetch(p, 0, 1, 1),
+                 2 => prefetch(p, 0, 2, 1),
+                 _ => prefetch(p, 0, 3, 1),
+             }
+         };
+     }
+     pref!(strategy)
+ }
+ 
+ /// Returns vector of type __m128 with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_undefined_ps() -> __m128 {
+     _mm_set1_ps(0.0)
+ }
+ 
+ /// Transpose the 4x4 matrix formed by 4 rows of __m128 in place.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_MM_TRANSPOSE4_PS)
+ #[inline]
+ #[allow(non_snake_case)]
+ #[target_feature(enable = "sse")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _MM_TRANSPOSE4_PS(
+     row0: &mut __m128,
+     row1: &mut __m128,
+     row2: &mut __m128,
+     row3: &mut __m128,
+ ) {
+     let tmp0 = _mm_unpacklo_ps(*row0, *row1);
+     let tmp2 = _mm_unpacklo_ps(*row2, *row3);
+     let tmp1 = _mm_unpackhi_ps(*row0, *row1);
+     let tmp3 = _mm_unpackhi_ps(*row2, *row3);
+ 
+     *row0 = _mm_movelh_ps(tmp0, tmp2);
+     *row1 = _mm_movehl_ps(tmp2, tmp0);
+     *row2 = _mm_movelh_ps(tmp1, tmp3);
+     *row3 = _mm_movehl_ps(tmp3, tmp1);
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse.add.ss"]
+     fn addss(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.sub.ss"]
+     fn subss(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.mul.ss"]
+     fn mulss(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.div.ss"]
+     fn divss(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.sqrt.ss"]
+     fn sqrtss(a: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.sqrt.ps"]
+     fn sqrtps(a: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.rcp.ss"]
+     fn rcpss(a: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.rcp.ps"]
+     fn rcpps(a: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.rsqrt.ss"]
+     fn rsqrtss(a: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.rsqrt.ps"]
+     fn rsqrtps(a: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.min.ss"]
+     fn minss(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.min.ps"]
+     fn minps(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.max.ss"]
+     fn maxss(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.max.ps"]
+     fn maxps(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse.movmsk.ps"]
+     fn movmskps(a: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.cmp.ps"]
+     fn cmpps(a: __m128, b: __m128, imm8: i8) -> __m128;
+     #[link_name = "llvm.x86.sse.comieq.ss"]
+     fn comieq_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.comilt.ss"]
+     fn comilt_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.comile.ss"]
+     fn comile_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.comigt.ss"]
+     fn comigt_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.comige.ss"]
+     fn comige_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.comineq.ss"]
+     fn comineq_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.ucomieq.ss"]
+     fn ucomieq_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.ucomilt.ss"]
+     fn ucomilt_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.ucomile.ss"]
+     fn ucomile_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.ucomigt.ss"]
+     fn ucomigt_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.ucomige.ss"]
+     fn ucomige_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.ucomineq.ss"]
+     fn ucomineq_ss(a: __m128, b: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.cvtss2si"]
+     fn cvtss2si(a: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.cvttss2si"]
+     fn cvttss2si(a: __m128) -> i32;
+     #[link_name = "llvm.x86.sse.cvtsi2ss"]
+     fn cvtsi2ss(a: __m128, b: i32) -> __m128;
+     #[link_name = "llvm.x86.sse.sfence"]
+     fn sfence();
+     #[link_name = "llvm.x86.sse.stmxcsr"]
+     fn stmxcsr(p: *mut i8);
+     #[link_name = "llvm.x86.sse.ldmxcsr"]
+     fn ldmxcsr(p: *const i8);
+     #[link_name = "llvm.prefetch"]
+     fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32);
+     #[link_name = "llvm.x86.sse.cmp.ss"]
+     fn cmpss(a: __m128, b: __m128, imm8: i8) -> __m128;
+ }
+ 
+ /// Stores `a` into the memory at `mem_addr` using a non-temporal memory hint.
+ ///
+ /// `mem_addr` must be aligned on a 16-byte boundary or a general-protection
+ /// exception _may_ be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_ps)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(movntps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_stream_ps(mem_addr: *mut f32, a: __m128) {
+     intrinsics::nontemporal_store(mem_addr as *mut __m128, a);
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::{hint::black_box, mem::transmute};
+     use std::{boxed, f32::NAN};
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::{simd::*, x86::*};
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_add_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_add_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(-101.0, 25.0, 0.0, -15.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_add_ss() {
+         let a = _mm_set_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_set_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_add_ss(a, b);
+         assert_eq_m128(r, _mm_set_ps(-1.0, 5.0, 0.0, -15.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_sub_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_sub_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(99.0, -15.0, 0.0, -5.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_sub_ss() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_sub_ss(a, b);
+         assert_eq_m128(r, _mm_setr_ps(99.0, 5.0, 0.0, -10.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_mul_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_mul_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(100.0, 100.0, 0.0, 50.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_mul_ss() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_mul_ss(a, b);
+         assert_eq_m128(r, _mm_setr_ps(100.0, 5.0, 0.0, -10.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_div_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 2.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.2, -5.0);
+         let r = _mm_div_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(0.01, 0.25, 10.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_div_ss() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_div_ss(a, b);
+         assert_eq_m128(r, _mm_setr_ps(0.01, 5.0, 0.0, -10.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_sqrt_ss() {
+         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
+         let r = _mm_sqrt_ss(a);
+         let e = _mm_setr_ps(2.0, 13.0, 16.0, 100.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_sqrt_ps() {
+         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
+         let r = _mm_sqrt_ps(a);
+         let e = _mm_setr_ps(2.0, 3.6055512, 4.0, 10.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_rcp_ss() {
+         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
+         let r = _mm_rcp_ss(a);
+         let e = _mm_setr_ps(0.24993896, 13.0, 16.0, 100.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_rcp_ps() {
+         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
+         let r = _mm_rcp_ps(a);
+         let e = _mm_setr_ps(0.24993896, 0.0769043, 0.06248474, 0.0099983215);
+         let rel_err = 0.00048828125;
+         for i in 0..4 {
+             assert_approx_eq!(get_m128(r, i), get_m128(e, i), 2. * rel_err);
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_rsqrt_ss() {
+         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
+         let r = _mm_rsqrt_ss(a);
+         let e = _mm_setr_ps(0.49987793, 13.0, 16.0, 100.0);
+         let rel_err = 0.00048828125;
+         for i in 0..4 {
+             assert_approx_eq!(get_m128(r, i), get_m128(e, i), 2. * rel_err);
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_rsqrt_ps() {
+         let a = _mm_setr_ps(4.0, 13.0, 16.0, 100.0);
+         let r = _mm_rsqrt_ps(a);
+         let e = _mm_setr_ps(0.49987793, 0.2772827, 0.24993896, 0.099990845);
+         let rel_err = 0.00048828125;
+         for i in 0..4 {
+             assert_approx_eq!(get_m128(r, i), get_m128(e, i), 2. * rel_err);
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_min_ss() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_min_ss(a, b);
+         assert_eq_m128(r, _mm_setr_ps(-100.0, 5.0, 0.0, -10.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_min_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_min_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(-100.0, 5.0, 0.0, -10.0));
+ 
+         // `_mm_min_ps` can **not** be implemented using the `simd_min` rust intrinsic. `simd_min`
+         // is lowered by the llvm codegen backend to `llvm.minnum.v*` llvm intrinsic. This intrinsic
+         // doesn't specify how -0.0 is handled. Unfortunately it happens to behave different from
+         // the `minps` x86 instruction on x86. The `llvm.minnum.v*` llvm intrinsic equals
+         // `r1` to `a` and `r2` to `b`.
+         let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0);
+         let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0);
+         let r1: [u8; 16] = transmute(_mm_min_ps(a, b));
+         let r2: [u8; 16] = transmute(_mm_min_ps(b, a));
+         let a: [u8; 16] = transmute(a);
+         let b: [u8; 16] = transmute(b);
+         assert_eq!(r1, b);
+         assert_eq!(r2, a);
+         assert_ne!(a, b); // sanity check that -0.0 is actually present
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_max_ss() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_max_ss(a, b);
+         assert_eq_m128(r, _mm_setr_ps(-1.0, 5.0, 0.0, -10.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_max_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_max_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(-1.0, 20.0, 0.0, -5.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_and_ps() {
+         let a = transmute(u32x4::splat(0b0011));
+         let b = transmute(u32x4::splat(0b0101));
+         let r = _mm_and_ps(*black_box(&a), *black_box(&b));
+         let e = transmute(u32x4::splat(0b0001));
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_andnot_ps() {
+         let a = transmute(u32x4::splat(0b0011));
+         let b = transmute(u32x4::splat(0b0101));
+         let r = _mm_andnot_ps(*black_box(&a), *black_box(&b));
+         let e = transmute(u32x4::splat(0b0100));
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_or_ps() {
+         let a = transmute(u32x4::splat(0b0011));
+         let b = transmute(u32x4::splat(0b0101));
+         let r = _mm_or_ps(*black_box(&a), *black_box(&b));
+         let e = transmute(u32x4::splat(0b0111));
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_xor_ps() {
+         let a = transmute(u32x4::splat(0b0011));
+         let b = transmute(u32x4::splat(0b0101));
+         let r = _mm_xor_ps(*black_box(&a), *black_box(&b));
+         let e = transmute(u32x4::splat(0b0110));
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpeq_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(-1.0, 5.0, 6.0, 7.0);
+         let r: u32x4 = transmute(_mm_cmpeq_ss(a, b));
+         let e: u32x4 = transmute(_mm_setr_ps(transmute(0u32), 2.0, 3.0, 4.0));
+         assert_eq!(r, e);
+ 
+         let b2 = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let r2: u32x4 = transmute(_mm_cmpeq_ss(a, b2));
+         let e2: u32x4 = transmute(_mm_setr_ps(transmute(0xffffffffu32), 2.0, 3.0, 4.0));
+         assert_eq!(r2, e2);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmplt_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = 0u32; // a.extract(0) < b.extract(0)
+         let c1 = 0u32; // a.extract(0) < c.extract(0)
+         let d1 = !0u32; // a.extract(0) < d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmplt_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmplt_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmplt_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmple_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = 0u32; // a.extract(0) <= b.extract(0)
+         let c1 = !0u32; // a.extract(0) <= c.extract(0)
+         let d1 = !0u32; // a.extract(0) <= d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmple_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmple_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmple_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpgt_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = !0u32; // a.extract(0) > b.extract(0)
+         let c1 = 0u32; // a.extract(0) > c.extract(0)
+         let d1 = 0u32; // a.extract(0) > d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpgt_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpgt_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpgt_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpge_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = !0u32; // a.extract(0) >= b.extract(0)
+         let c1 = !0u32; // a.extract(0) >= c.extract(0)
+         let d1 = 0u32; // a.extract(0) >= d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpge_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpge_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpge_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpneq_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = !0u32; // a.extract(0) != b.extract(0)
+         let c1 = 0u32; // a.extract(0) != c.extract(0)
+         let d1 = !0u32; // a.extract(0) != d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpneq_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpneq_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpneq_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpnlt_ss() {
+         // TODO: this test is exactly the same as for `_mm_cmpge_ss`, but there
+         // must be a difference. It may have to do with behavior in the
+         // presence of NaNs (signaling or quiet). If so, we should add tests
+         // for those.
+ 
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = !0u32; // a.extract(0) >= b.extract(0)
+         let c1 = !0u32; // a.extract(0) >= c.extract(0)
+         let d1 = 0u32; // a.extract(0) >= d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpnlt_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpnlt_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpnlt_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpnle_ss() {
+         // TODO: this test is exactly the same as for `_mm_cmpgt_ss`, but there
+         // must be a difference. It may have to do with behavior in the
+         // presence
+         // of NaNs (signaling or quiet). If so, we should add tests for those.
+ 
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = !0u32; // a.extract(0) > b.extract(0)
+         let c1 = 0u32; // a.extract(0) > c.extract(0)
+         let d1 = 0u32; // a.extract(0) > d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpnle_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpnle_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpnle_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpngt_ss() {
+         // TODO: this test is exactly the same as for `_mm_cmple_ss`, but there
+         // must be a difference. It may have to do with behavior in the
+         // presence of NaNs (signaling or quiet). If so, we should add tests
+         // for those.
+ 
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = 0u32; // a.extract(0) <= b.extract(0)
+         let c1 = !0u32; // a.extract(0) <= c.extract(0)
+         let d1 = !0u32; // a.extract(0) <= d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpngt_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpngt_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpngt_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpnge_ss() {
+         // TODO: this test is exactly the same as for `_mm_cmplt_ss`, but there
+         // must be a difference. It may have to do with behavior in the
+         // presence of NaNs (signaling or quiet). If so, we should add tests
+         // for those.
+ 
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = 0u32; // a.extract(0) < b.extract(0)
+         let c1 = 0u32; // a.extract(0) < c.extract(0)
+         let d1 = !0u32; // a.extract(0) < d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpnge_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpnge_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpnge_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpord_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(NAN, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = !0u32; // a.extract(0) ord b.extract(0)
+         let c1 = 0u32; // a.extract(0) ord c.extract(0)
+         let d1 = !0u32; // a.extract(0) ord d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpord_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpord_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpord_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpunord_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
+         let c = _mm_setr_ps(NAN, 5.0, 6.0, 7.0);
+         let d = _mm_setr_ps(2.0, 5.0, 6.0, 7.0);
+ 
+         let b1 = 0u32; // a.extract(0) unord b.extract(0)
+         let c1 = !0u32; // a.extract(0) unord c.extract(0)
+         let d1 = 0u32; // a.extract(0) unord d.extract(0)
+ 
+         let rb: u32x4 = transmute(_mm_cmpunord_ss(a, b));
+         let eb: u32x4 = transmute(_mm_setr_ps(transmute(b1), 2.0, 3.0, 4.0));
+         assert_eq!(rb, eb);
+ 
+         let rc: u32x4 = transmute(_mm_cmpunord_ss(a, c));
+         let ec: u32x4 = transmute(_mm_setr_ps(transmute(c1), 2.0, 3.0, 4.0));
+         assert_eq!(rc, ec);
+ 
+         let rd: u32x4 = transmute(_mm_cmpunord_ss(a, d));
+         let ed: u32x4 = transmute(_mm_setr_ps(transmute(d1), 2.0, 3.0, 4.0));
+         assert_eq!(rd, ed);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpeq_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(fls, fls, tru, fls);
+         let r: u32x4 = transmute(_mm_cmpeq_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmplt_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(tru, fls, fls, fls);
+         let r: u32x4 = transmute(_mm_cmplt_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmple_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, 4.0);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(tru, fls, tru, fls);
+         let r: u32x4 = transmute(_mm_cmple_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpgt_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, 42.0);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(fls, tru, fls, fls);
+         let r: u32x4 = transmute(_mm_cmpgt_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpge_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, 42.0);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(fls, tru, tru, fls);
+         let r: u32x4 = transmute(_mm_cmpge_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpneq_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(tru, tru, fls, tru);
+         let r: u32x4 = transmute(_mm_cmpneq_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpnlt_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(fls, tru, tru, tru);
+         let r: u32x4 = transmute(_mm_cmpnlt_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpnle_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(fls, tru, fls, tru);
+         let r: u32x4 = transmute(_mm_cmpnle_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpngt_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(tru, fls, tru, tru);
+         let r: u32x4 = transmute(_mm_cmpngt_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpnge_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
+         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(tru, fls, fls, tru);
+         let r: u32x4 = transmute(_mm_cmpnge_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpord_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, NAN, NAN);
+         let b = _mm_setr_ps(15.0, NAN, 1.0, NAN);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(tru, fls, fls, fls);
+         let r: u32x4 = transmute(_mm_cmpord_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cmpunord_ps() {
+         let a = _mm_setr_ps(10.0, 50.0, NAN, NAN);
+         let b = _mm_setr_ps(15.0, NAN, 1.0, NAN);
+         let tru = !0u32;
+         let fls = 0u32;
+ 
+         let e = u32x4::new(fls, tru, tru, tru);
+         let r: u32x4 = transmute(_mm_cmpunord_ps(a, b));
+         assert_eq!(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_comieq_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[1i32, 0, 0, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_comieq_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_comieq_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_comilt_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[0i32, 1, 0, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_comilt_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_comilt_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_comile_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[1i32, 1, 0, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_comile_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_comile_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_comigt_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[1i32, 0, 1, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_comige_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_comige_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_comineq_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[0i32, 1, 1, 1];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_comineq_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_comineq_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_ucomieq_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[1i32, 0, 0, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_ucomieq_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_ucomieq_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_ucomilt_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[0i32, 1, 0, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_ucomilt_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_ucomilt_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_ucomile_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[1i32, 1, 0, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_ucomile_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_ucomile_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_ucomigt_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[0i32, 0, 1, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_ucomigt_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_ucomigt_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_ucomige_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[1i32, 0, 1, 0];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_ucomige_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_ucomige_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_ucomineq_ss() {
+         let aa = &[3.0f32, 12.0, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, 1.5, NAN];
+ 
+         let ee = &[0i32, 1, 1, 1];
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             let r = _mm_ucomineq_ss(a, b);
+ 
+             assert_eq!(
+                 ee[i], r,
+                 "_mm_ucomineq_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r, ee[i], i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_comieq_ss_vs_ucomieq_ss() {
+         // If one of the arguments is a quiet NaN `comieq_ss` should signal an
+         // Invalid Operation Exception while `ucomieq_ss` should not.
+         let aa = &[3.0f32, NAN, 23.0, NAN];
+         let bb = &[3.0f32, 47.5, NAN, NAN];
+ 
+         let ee = &[1i32, 0, 0, 0];
+         let exc = &[0u32, 1, 1, 1]; // Should comieq_ss signal an exception?
+ 
+         for i in 0..4 {
+             let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0);
+             let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0);
+ 
+             _MM_SET_EXCEPTION_STATE(0);
+             let r1 = _mm_comieq_ss(*black_box(&a), b);
+             let s1 = _MM_GET_EXCEPTION_STATE();
+ 
+             _MM_SET_EXCEPTION_STATE(0);
+             let r2 = _mm_ucomieq_ss(*black_box(&a), b);
+             let s2 = _MM_GET_EXCEPTION_STATE();
+ 
+             assert_eq!(
+                 ee[i], r1,
+                 "_mm_comeq_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r1, ee[i], i
+             );
+             assert_eq!(
+                 ee[i], r2,
+                 "_mm_ucomeq_ss({:?}, {:?}) = {}, expected: {} (i={})",
+                 a, b, r2, ee[i], i
+             );
+             assert_eq!(
+                 s1,
+                 exc[i] * _MM_EXCEPT_INVALID,
+                 "_mm_comieq_ss() set exception flags: {} (i={})",
+                 s1,
+                 i
+             );
+             assert_eq!(
+                 s2,
+                 0, // ucomieq_ss should not signal an exception
+                 "_mm_ucomieq_ss() set exception flags: {} (i={})",
+                 s2,
+                 i
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvtss_si32() {
+         let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1];
+         let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520];
+         for i in 0..inputs.len() {
+             let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0);
+             let e = result[i];
+             let r = _mm_cvtss_si32(x);
+             assert_eq!(
+                 e, r,
+                 "TestCase #{} _mm_cvtss_si32({:?}) = {}, expected: {}",
+                 i, x, r, e
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvttss_si32() {
+         let inputs = &[
+             (42.0f32, 42i32),
+             (-31.4, -31),
+             (-33.5, -33),
+             (-34.5, -34),
+             (10.999, 10),
+             (-5.99, -5),
+             (4.0e10, i32::MIN),
+             (4.0e-10, 0),
+             (NAN, i32::MIN),
+             (2147483500.1, 2147483520),
+         ];
+         for i in 0..inputs.len() {
+             let (xi, e) = inputs[i];
+             let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+             let r = _mm_cvttss_si32(x);
+             assert_eq!(
+                 e, r,
+                 "TestCase #{} _mm_cvttss_si32({:?}) = {}, expected: {}",
+                 i, x, r, e
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvtsi32_ss() {
+         let inputs = &[
+             (4555i32, 4555.0f32),
+             (322223333, 322223330.0),
+             (-432, -432.0),
+             (-322223333, -322223330.0),
+         ];
+ 
+         for i in 0..inputs.len() {
+             let (x, f) = inputs[i];
+             let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+             let r = _mm_cvtsi32_ss(a, x);
+             let e = _mm_setr_ps(f, 6.0, 7.0, 8.0);
+             assert_eq_m128(e, r);
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvtss_f32() {
+         let a = _mm_setr_ps(312.0134, 5.0, 6.0, 7.0);
+         assert_eq!(_mm_cvtss_f32(a), 312.0134);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_set_ss() {
+         let r = _mm_set_ss(black_box(4.25));
+         assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_set1_ps() {
+         let r1 = _mm_set1_ps(black_box(4.25));
+         let r2 = _mm_set_ps1(black_box(4.25));
+         assert_eq!(get_m128(r1, 0), 4.25);
+         assert_eq!(get_m128(r1, 1), 4.25);
+         assert_eq!(get_m128(r1, 2), 4.25);
+         assert_eq!(get_m128(r1, 3), 4.25);
+         assert_eq!(get_m128(r2, 0), 4.25);
+         assert_eq!(get_m128(r2, 1), 4.25);
+         assert_eq!(get_m128(r2, 2), 4.25);
+         assert_eq!(get_m128(r2, 3), 4.25);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_set_ps() {
+         let r = _mm_set_ps(
+             black_box(1.0),
+             black_box(2.0),
+             black_box(3.0),
+             black_box(4.0),
+         );
+         assert_eq!(get_m128(r, 0), 4.0);
+         assert_eq!(get_m128(r, 1), 3.0);
+         assert_eq!(get_m128(r, 2), 2.0);
+         assert_eq!(get_m128(r, 3), 1.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_setr_ps() {
+         let r = _mm_setr_ps(
+             black_box(1.0),
+             black_box(2.0),
+             black_box(3.0),
+             black_box(4.0),
+         );
+         assert_eq_m128(r, _mm_setr_ps(1.0, 2.0, 3.0, 4.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_setzero_ps() {
+         let r = *black_box(&_mm_setzero_ps());
+         assert_eq_m128(r, _mm_set1_ps(0.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_shuffle() {
+         assert_eq!(_MM_SHUFFLE(0, 1, 1, 3), 0b00_01_01_11);
+         assert_eq!(_MM_SHUFFLE(3, 1, 1, 0), 0b11_01_01_00);
+         assert_eq!(_MM_SHUFFLE(1, 2, 2, 1), 0b01_10_10_01);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_shuffle_ps() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+         let r = _mm_shuffle_ps(a, b, 0b00_01_01_11);
+         assert_eq_m128(r, _mm_setr_ps(4.0, 2.0, 6.0, 5.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_unpackhi_ps() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+         let r = _mm_unpackhi_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(3.0, 7.0, 4.0, 8.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_unpacklo_ps() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+         let r = _mm_unpacklo_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(1.0, 5.0, 2.0, 6.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_movehl_ps() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+         let r = _mm_movehl_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(7.0, 8.0, 3.0, 4.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_movelh_ps() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+         let r = _mm_movelh_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(1.0, 2.0, 5.0, 6.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_load_ss() {
+         let a = 42.0f32;
+         let r = _mm_load_ss(&a as *const f32);
+         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_load1_ps() {
+         let a = 42.0f32;
+         let r = _mm_load1_ps(&a as *const f32);
+         assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_load_ps() {
+         let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
+ 
+         let mut p = vals.as_ptr();
+         let mut fixup = 0.0f32;
+ 
+         // Make sure p is aligned, otherwise we might get a
+         // (signal: 11, SIGSEGV: invalid memory reference)
+ 
+         let unalignment = (p as usize) & 0xf;
+         if unalignment != 0 {
+             let delta = ((16 - unalignment) >> 2) as isize;
+             fixup = delta as f32;
+             p = p.offset(delta);
+         }
+ 
+         let r = _mm_load_ps(p);
+         let e = _mm_add_ps(_mm_setr_ps(1.0, 2.0, 3.0, 4.0), _mm_set1_ps(fixup));
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_loadu_ps() {
+         let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
+         let p = vals.as_ptr().offset(3);
+         let r = _mm_loadu_ps(black_box(p));
+         assert_eq_m128(r, _mm_setr_ps(4.0, 5.0, 6.0, 7.0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_loadr_ps() {
+         let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
+ 
+         let mut p = vals.as_ptr();
+         let mut fixup = 0.0f32;
+ 
+         // Make sure p is aligned, otherwise we might get a
+         // (signal: 11, SIGSEGV: invalid memory reference)
+ 
+         let unalignment = (p as usize) & 0xf;
+         if unalignment != 0 {
+             let delta = ((16 - unalignment) >> 2) as isize;
+             fixup = delta as f32;
+             p = p.offset(delta);
+         }
+ 
+         let r = _mm_loadr_ps(p);
+         let e = _mm_add_ps(_mm_setr_ps(4.0, 3.0, 2.0, 1.0), _mm_set1_ps(fixup));
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadu_si64() {
+         let a = _mm_setr_epi64x(5, 6);
+         let r = _mm_loadu_si64(&a as *const _ as *const _);
+         assert_eq_m128i(r, _mm_set_epi64x(5, 0));
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_store_ss() {
+         let mut vals = [0.0f32; 8];
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         _mm_store_ss(vals.as_mut_ptr().offset(1), a);
+ 
+         assert_eq!(vals[0], 0.0);
+         assert_eq!(vals[1], 1.0);
+         assert_eq!(vals[2], 0.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_store1_ps() {
+         let mut vals = [0.0f32; 8];
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+ 
+         let mut ofs = 0;
+         let mut p = vals.as_mut_ptr();
+ 
+         if (p as usize) & 0xf != 0 {
+             ofs = (16 - (p as usize) & 0xf) >> 2;
+             p = p.offset(ofs as isize);
+         }
+ 
+         _mm_store1_ps(p, *black_box(&a));
+ 
+         if ofs > 0 {
+             assert_eq!(vals[ofs - 1], 0.0);
+         }
+         assert_eq!(vals[ofs + 0], 1.0);
+         assert_eq!(vals[ofs + 1], 1.0);
+         assert_eq!(vals[ofs + 2], 1.0);
+         assert_eq!(vals[ofs + 3], 1.0);
+         assert_eq!(vals[ofs + 4], 0.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_store_ps() {
+         let mut vals = [0.0f32; 8];
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+ 
+         let mut ofs = 0;
+         let mut p = vals.as_mut_ptr();
+ 
+         // Align p to 16-byte boundary
+         if (p as usize) & 0xf != 0 {
+             ofs = (16 - (p as usize) & 0xf) >> 2;
+             p = p.offset(ofs as isize);
+         }
+ 
+         _mm_store_ps(p, *black_box(&a));
+ 
+         if ofs > 0 {
+             assert_eq!(vals[ofs - 1], 0.0);
+         }
+         assert_eq!(vals[ofs + 0], 1.0);
+         assert_eq!(vals[ofs + 1], 2.0);
+         assert_eq!(vals[ofs + 2], 3.0);
+         assert_eq!(vals[ofs + 3], 4.0);
+         assert_eq!(vals[ofs + 4], 0.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_storer_ps() {
+         let mut vals = [0.0f32; 8];
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+ 
+         let mut ofs = 0;
+         let mut p = vals.as_mut_ptr();
+ 
+         // Align p to 16-byte boundary
+         if (p as usize) & 0xf != 0 {
+             ofs = (16 - (p as usize) & 0xf) >> 2;
+             p = p.offset(ofs as isize);
+         }
+ 
+         _mm_storer_ps(p, *black_box(&a));
+ 
+         if ofs > 0 {
+             assert_eq!(vals[ofs - 1], 0.0);
+         }
+         assert_eq!(vals[ofs + 0], 4.0);
+         assert_eq!(vals[ofs + 1], 3.0);
+         assert_eq!(vals[ofs + 2], 2.0);
+         assert_eq!(vals[ofs + 3], 1.0);
+         assert_eq!(vals[ofs + 4], 0.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_storeu_ps() {
+         let mut vals = [0.0f32; 8];
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+ 
+         let mut ofs = 0;
+         let mut p = vals.as_mut_ptr();
+ 
+         // Make sure p is **not** aligned to 16-byte boundary
+         if (p as usize) & 0xf == 0 {
+             ofs = 1;
+             p = p.offset(1);
+         }
+ 
+         _mm_storeu_ps(p, *black_box(&a));
+ 
+         if ofs > 0 {
+             assert_eq!(vals[ofs - 1], 0.0);
+         }
+         assert_eq!(vals[ofs + 0], 1.0);
+         assert_eq!(vals[ofs + 1], 2.0);
+         assert_eq!(vals[ofs + 2], 3.0);
+         assert_eq!(vals[ofs + 3], 4.0);
+         assert_eq!(vals[ofs + 4], 0.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_move_ss() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+ 
+         let r = _mm_move_ss(a, b);
+         let e = _mm_setr_ps(5.0, 2.0, 3.0, 4.0);
+         assert_eq_m128(e, r);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_movemask_ps() {
+         let r = _mm_movemask_ps(_mm_setr_ps(-1.0, 5.0, -5.0, 0.0));
+         assert_eq!(r, 0b0101);
+ 
+         let r = _mm_movemask_ps(_mm_setr_ps(-1.0, -5.0, -5.0, 0.0));
+         assert_eq!(r, 0b0111);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_sfence() {
+         _mm_sfence();
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_getcsr_setcsr_1() {
+         let saved_csr = _mm_getcsr();
+ 
+         let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0);
+         let b = _mm_setr_ps(0.001, 0.0, 0.0, 1.0);
+ 
+         _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON);
+         let r = _mm_mul_ps(*black_box(&a), *black_box(&b));
+ 
+         _mm_setcsr(saved_csr);
+ 
+         let exp = _mm_setr_ps(0.0, 0.0, 0.0, 1.0);
+         assert_eq_m128(r, exp); // first component is a denormalized f32
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_getcsr_setcsr_2() {
+         // Same as _mm_setcsr_1 test, but with opposite flag value.
+ 
+         let saved_csr = _mm_getcsr();
+ 
+         let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0);
+         let b = _mm_setr_ps(0.001, 0.0, 0.0, 1.0);
+ 
+         _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_OFF);
+         let r = _mm_mul_ps(*black_box(&a), *black_box(&b));
+ 
+         _mm_setcsr(saved_csr);
+ 
+         let exp = _mm_setr_ps(1.1e-39, 0.0, 0.0, 1.0);
+         assert_eq_m128(r, exp); // first component is a denormalized f32
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_getcsr_setcsr_underflow() {
+         _MM_SET_EXCEPTION_STATE(0);
+ 
+         let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0);
+         let b = _mm_setr_ps(1e-5, 0.0, 0.0, 1.0);
+ 
+         assert_eq!(_MM_GET_EXCEPTION_STATE(), 0); // just to be sure
+ 
+         let r = _mm_mul_ps(*black_box(&a), *black_box(&b));
+ 
+         let exp = _mm_setr_ps(1.1e-41, 0.0, 0.0, 1.0);
+         assert_eq_m128(r, exp);
+ 
+         let underflow = _MM_GET_EXCEPTION_STATE() & _MM_EXCEPT_UNDERFLOW != 0;
+         assert_eq!(underflow, true);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_MM_TRANSPOSE4_PS() {
+         let mut a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let mut b = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+         let mut c = _mm_setr_ps(9.0, 10.0, 11.0, 12.0);
+         let mut d = _mm_setr_ps(13.0, 14.0, 15.0, 16.0);
+ 
+         _MM_TRANSPOSE4_PS(&mut a, &mut b, &mut c, &mut d);
+ 
+         assert_eq_m128(a, _mm_setr_ps(1.0, 5.0, 9.0, 13.0));
+         assert_eq_m128(b, _mm_setr_ps(2.0, 6.0, 10.0, 14.0));
+         assert_eq_m128(c, _mm_setr_ps(3.0, 7.0, 11.0, 15.0));
+         assert_eq_m128(d, _mm_setr_ps(4.0, 8.0, 12.0, 16.0));
+     }
+ 
+     #[repr(align(16))]
+     struct Memory {
+         pub data: [f32; 4],
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_stream_ps() {
+         let a = _mm_set1_ps(7.0);
+         let mut mem = Memory { data: [-1.0; 4] };
+ 
+         _mm_stream_ps(&mut mem.data[0] as *mut f32, a);
+         for i in 0..4 {
+             assert_eq!(mem.data[i], get_m128(a, i));
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse2.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse2.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse2.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,5092 ----
+ //! Streaming SIMD Extensions 2 (SSE2)
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     intrinsics,
+     mem::{self, transmute},
+     ptr,
+ };
+ 
+ /// Provides a hint to the processor that the code sequence is a spin-wait loop.
+ ///
+ /// This can help improve the performance and power consumption of spin-wait
+ /// loops.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_pause)
+ #[inline]
+ #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_pause() {
+     // note: `pause` is guaranteed to be interpreted as a `nop` by CPUs without
+     // the SSE2 target-feature - therefore it does not require any target features
+     pause()
+ }
+ 
+ /// Invalidates and flushes the cache line that contains `p` from all levels of
+ /// the cache hierarchy.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clflush)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(clflush))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_clflush(p: *const u8) {
+     clflush(p)
+ }
+ 
+ /// Performs a serializing operation on all load-from-memory instructions
+ /// that were issued prior to this instruction.
+ ///
+ /// Guarantees that every load instruction that precedes, in program order, is
+ /// globally visible before any load instruction which follows the fence in
+ /// program order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_lfence)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(lfence))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_lfence() {
+     lfence()
+ }
+ 
+ /// Performs a serializing operation on all load-from-memory and store-to-memory
+ /// instructions that were issued prior to this instruction.
+ ///
+ /// Guarantees that every memory access that precedes, in program order, the
+ /// memory fence instruction is globally visible before any memory instruction
+ /// which follows the fence in program order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mfence)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(mfence))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mfence() {
+     mfence()
+ }
+ 
+ /// Adds packed 8-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_add(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Adds packed 16-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_add(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Adds packed 32-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_add(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Adds packed 64-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_epi64(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_add(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Adds packed 8-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_adds_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_add(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Adds packed 16-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_adds_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_add(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Adds packed unsigned 8-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epu8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddusb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_adds_epu8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_add(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Adds packed unsigned 16-bit integers in `a` and `b` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epu16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(paddusw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_adds_epu16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_add(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Averages packed unsigned 8-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_avg_epu8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pavgb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_avg_epu8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pavgb(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Averages packed unsigned 16-bit integers in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_avg_epu16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pavgw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pavgw(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Multiplies and then horizontally add signed 16 bit integers in `a` and `b`.
+ ///
+ /// Multiplies packed signed 16-bit integers in `a` and `b`, producing
+ /// intermediate signed 32-bit integers. Horizontally add adjacent pairs of
+ /// intermediate 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_madd_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmaddwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaddwd(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
+ /// maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmaxsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaxsw(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns the
+ /// packed maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epu8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmaxub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaxub(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b`, and returns the packed
+ /// minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pminsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pminsw(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns the
+ /// packed minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epu8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pminub))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_epu8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pminub(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Multiplies the packed 16-bit integers in `a` and `b`.
+ ///
+ /// The multiplication produces intermediate 32-bit integers, and returns the
+ /// high 16 bits of the intermediate integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mulhi_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmulhw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mulhi_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmulhw(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Multiplies the packed unsigned 16-bit integers in `a` and `b`.
+ ///
+ /// The multiplication produces intermediate 32-bit integers, and returns the
+ /// high 16 bits of the intermediate integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mulhi_epu16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmulhuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mulhi_epu16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmulhuw(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Multiplies the packed 16-bit integers in `a` and `b`.
+ ///
+ /// The multiplication produces intermediate 32-bit integers, and returns the
+ /// low 16 bits of the intermediate integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mullo_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmullw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mullo_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_mul(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Multiplies the low unsigned 32-bit integers from each packed 64-bit element
+ /// in `a` and `b`.
+ ///
+ /// Returns the unsigned 64-bit results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_epu32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmuludq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mul_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmuludq(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Sum the absolute differences of packed unsigned 8-bit integers.
+ ///
+ /// Computes the absolute differences of packed unsigned 8-bit integers in `a`
+ /// and `b`, then horizontally sum each consecutive 8 differences to produce
+ /// two unsigned 16-bit integers, and pack these unsigned 16-bit integers in
+ /// the low 16 bits of 64-bit elements returned.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sad_epu8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psadbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sad_epu8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(psadbw(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Subtracts packed 8-bit integers in `b` from packed 8-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_sub(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Subtracts packed 16-bit integers in `b` from packed 16-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_sub(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Subtract packed 32-bit integers in `b` from packed 32-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_sub(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Subtract packed 64-bit integers in `b` from packed 64-bit integers in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_epi64(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_sub(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Subtract packed 8-bit integers in `b` from packed 8-bit integers in `a`
+ /// using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_subs_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_sub(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Subtract packed 16-bit integers in `b` from packed 16-bit integers in `a`
+ /// using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_subs_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_sub(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Subtract packed unsigned 8-bit integers in `b` from packed unsigned 8-bit
+ /// integers in `a` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epu8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubusb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_subs_epu8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_sub(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Subtract packed unsigned 16-bit integers in `b` from packed unsigned 16-bit
+ /// integers in `a` using saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epu16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psubusw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_subs_epu16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_saturating_sub(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Shifts `a` left by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pslldq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_slli_si128(a: __m128i, imm8: i32) -> __m128i {
+     _mm_slli_si128_impl(a, imm8)
+ }
+ 
+ /// Implementation detail: converts the immediate argument of the
+ /// `_mm_slli_si128` intrinsic into a compile-time constant.
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ unsafe fn _mm_slli_si128_impl(a: __m128i, imm8: i32) -> __m128i {
+     let (zero, imm8) = (_mm_set1_epi8(0).as_i8x16(), imm8 as u32);
+     let a = a.as_i8x16();
+     macro_rules! shuffle {
+         ($shift:expr) => {
+             simd_shuffle16::<i8x16, i8x16>(
+                 zero,
+                 a,
+                 [
+                     16 - $shift,
+                     17 - $shift,
+                     18 - $shift,
+                     19 - $shift,
+                     20 - $shift,
+                     21 - $shift,
+                     22 - $shift,
+                     23 - $shift,
+                     24 - $shift,
+                     25 - $shift,
+                     26 - $shift,
+                     27 - $shift,
+                     28 - $shift,
+                     29 - $shift,
+                     30 - $shift,
+                     31 - $shift,
+                 ],
+             )
+         };
+     }
+     let x = match imm8 {
+         0 => shuffle!(0),
+         1 => shuffle!(1),
+         2 => shuffle!(2),
+         3 => shuffle!(3),
+         4 => shuffle!(4),
+         5 => shuffle!(5),
+         6 => shuffle!(6),
+         7 => shuffle!(7),
+         8 => shuffle!(8),
+         9 => shuffle!(9),
+         10 => shuffle!(10),
+         11 => shuffle!(11),
+         12 => shuffle!(12),
+         13 => shuffle!(13),
+         14 => shuffle!(14),
+         15 => shuffle!(15),
+         _ => shuffle!(16),
+     };
+     transmute(x)
+ }
+ 
+ /// Shifts `a` left by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_bslli_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pslldq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_bslli_si128(a: __m128i, imm8: i32) -> __m128i {
+     _mm_slli_si128_impl(a, imm8)
+ }
+ 
+ /// Shifts `a` right by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_bsrli_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrldq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_bsrli_si128(a: __m128i, imm8: i32) -> __m128i {
+     _mm_srli_si128_impl(a, imm8)
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` left by `imm8` while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psllw, imm8 = 7))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_slli_epi16(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i16x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(pslliw(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` left by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sll_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psllw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sll_epi16(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psllw(a.as_i16x8(), count.as_i16x8()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` left by `imm8` while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pslld, imm8 = 7))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_slli_epi32(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i32x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(psllid(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` left by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sll_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pslld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sll_epi32(a: __m128i, count: __m128i) -> __m128i {
+     transmute(pslld(a.as_i32x4(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` left by `imm8` while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psllq, imm8 = 7))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_slli_epi64(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i64x2();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(pslliq(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` left by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sll_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psllq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sll_epi64(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psllq(a.as_i64x2(), count.as_i64x2()))
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `imm8` while shifting in sign
+ /// bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srai_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psraw, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srai_epi16(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i16x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(psraiw(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `count` while shifting in sign
+ /// bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sra_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psraw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sra_epi16(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psraw(a.as_i16x8(), count.as_i16x8()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `imm8` while shifting in sign
+ /// bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srai_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrad, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srai_epi32(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i32x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(psraid(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `count` while shifting in sign
+ /// bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sra_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrad))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sra_epi32(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psrad(a.as_i32x4(), count.as_i32x4()))
+ }
+ 
+ /// Shifts `a` right by `imm8` bytes while shifting in zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrldq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srli_si128(a: __m128i, imm8: i32) -> __m128i {
+     _mm_srli_si128_impl(a, imm8)
+ }
+ 
+ /// Implementation detail: converts the immediate argument of the
+ /// `_mm_srli_si128` intrinsic into a compile-time constant.
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ unsafe fn _mm_srli_si128_impl(a: __m128i, imm8: i32) -> __m128i {
+     let (zero, imm8) = (_mm_set1_epi8(0).as_i8x16(), imm8 as u32);
+     let a = a.as_i8x16();
+     macro_rules! shuffle {
+         ($shift:expr) => {
+             simd_shuffle16(
+                 a,
+                 zero,
+                 [
+                     0 + $shift,
+                     1 + $shift,
+                     2 + $shift,
+                     3 + $shift,
+                     4 + $shift,
+                     5 + $shift,
+                     6 + $shift,
+                     7 + $shift,
+                     8 + $shift,
+                     9 + $shift,
+                     10 + $shift,
+                     11 + $shift,
+                     12 + $shift,
+                     13 + $shift,
+                     14 + $shift,
+                     15 + $shift,
+                 ],
+             )
+         };
+     }
+     let x: i8x16 = match imm8 {
+         0 => shuffle!(0),
+         1 => shuffle!(1),
+         2 => shuffle!(2),
+         3 => shuffle!(3),
+         4 => shuffle!(4),
+         5 => shuffle!(5),
+         6 => shuffle!(6),
+         7 => shuffle!(7),
+         8 => shuffle!(8),
+         9 => shuffle!(9),
+         10 => shuffle!(10),
+         11 => shuffle!(11),
+         12 => shuffle!(12),
+         13 => shuffle!(13),
+         14 => shuffle!(14),
+         15 => shuffle!(15),
+         _ => shuffle!(16),
+     };
+     transmute(x)
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `imm8` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrlw, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srli_epi16(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i16x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(psrliw(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 16-bit integers in `a` right by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srl_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrlw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srl_epi16(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psrlw(a.as_i16x8(), count.as_i16x8()))
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `imm8` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrld, imm8 = 8))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srli_epi32(a: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i32x4();
+     macro_rules! call {
+         ($imm8:expr) => {
+             transmute(psrlid(a, $imm8))
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Shifts packed 32-bit integers in `a` right by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srl_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srl_epi32(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psrld(a.as_i32x4(), count.as_i32x4()))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` right by `imm8` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrlq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srli_epi64(a: __m128i, imm8: i32) -> __m128i {
+     transmute(psrliq(a.as_i64x2(), imm8))
+ }
+ 
+ /// Shifts packed 64-bit integers in `a` right by `count` while shifting in
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srl_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(psrlq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_srl_epi64(a: __m128i, count: __m128i) -> __m128i {
+     transmute(psrlq(a.as_i64x2(), count.as_i64x2()))
+ }
+ 
+ /// Computes the bitwise AND of 128 bits (representing integer data) in `a` and
+ /// `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_and_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(andps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_and_si128(a: __m128i, b: __m128i) -> __m128i {
+     simd_and(a, b)
+ }
+ 
+ /// Computes the bitwise NOT of 128 bits (representing integer data) in `a` and
+ /// then AND with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_andnot_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(andnps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_andnot_si128(a: __m128i, b: __m128i) -> __m128i {
+     simd_and(simd_xor(_mm_set1_epi8(-1), a), b)
+ }
+ 
+ /// Computes the bitwise OR of 128 bits (representing integer data) in `a` and
+ /// `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_or_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(orps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_or_si128(a: __m128i, b: __m128i) -> __m128i {
+     simd_or(a, b)
+ }
+ 
+ /// Computes the bitwise XOR of 128 bits (representing integer data) in `a` and
+ /// `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_xor_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(xorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_xor_si128(a: __m128i, b: __m128i) -> __m128i {
+     simd_xor(a, b)
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpeqb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i8x16, _>(simd_eq(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpeqw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i16x8, _>(simd_eq(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpeqd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i32x4, _>(simd_eq(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpgtb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i8x16, _>(simd_gt(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpgtw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i16x8, _>(simd_gt(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpgtd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i32x4, _>(simd_gt(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` for less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpgtb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i8x16, _>(simd_lt(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares packed 16-bit integers in `a` and `b` for less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpgtw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i16x8, _>(simd_lt(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b` for less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pcmpgtd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i32x4, _>(simd_lt(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Converts the lower two packed 32-bit integers in `a` to packed
+ /// double-precision (64-bit) floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi32_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtdq2pd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi32_pd(a: __m128i) -> __m128d {
+     let a = a.as_i32x4();
+     simd_cast::<i32x2, __m128d>(simd_shuffle2(a, a, [0, 1]))
+ }
+ 
+ /// Returns `a` with its lower element replaced by `b` after converting it to
+ /// an `f64`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi32_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsi2sd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi32_sd(a: __m128d, b: i32) -> __m128d {
+     simd_insert(a, 0, b as f64)
+ }
+ 
+ /// Converts packed 32-bit integers in `a` to packed single-precision (32-bit)
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi32_ps)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtdq2ps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi32_ps(a: __m128i) -> __m128 {
+     cvtdq2ps(a.as_i32x4())
+ }
+ 
+ /// Converts packed single-precision (32-bit) floating-point elements in `a`
+ /// to packed 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtps_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtps2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtps_epi32(a: __m128) -> __m128i {
+     transmute(cvtps2dq(a))
+ }
+ 
+ /// Returns a vector whose lowest element is `a` and all higher elements are
+ /// `0`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi32_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(movd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi32_si128(a: i32) -> __m128i {
+     transmute(i32x4::new(a, 0, 0, 0))
+ }
+ 
+ /// Returns the lowest element of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi128_si32(a: __m128i) -> i32 {
+     simd_extract(a.as_i32x4(), 0)
+ }
+ 
+ /// Sets packed 64-bit integers with the supplied values, from highest to
+ /// lowest.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi64x)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_epi64x(e1: i64, e0: i64) -> __m128i {
+     transmute(i64x2::new(e0, e1))
+ }
+ 
+ /// Sets packed 32-bit integers with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
+     transmute(i32x4::new(e0, e1, e2, e3))
+ }
+ 
+ /// Sets packed 16-bit integers with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_epi16(
+     e7: i16,
+     e6: i16,
+     e5: i16,
+     e4: i16,
+     e3: i16,
+     e2: i16,
+     e1: i16,
+     e0: i16,
+ ) -> __m128i {
+     transmute(i16x8::new(e0, e1, e2, e3, e4, e5, e6, e7))
+ }
+ 
+ /// Sets packed 8-bit integers with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_epi8(
+     e15: i8,
+     e14: i8,
+     e13: i8,
+     e12: i8,
+     e11: i8,
+     e10: i8,
+     e9: i8,
+     e8: i8,
+     e7: i8,
+     e6: i8,
+     e5: i8,
+     e4: i8,
+     e3: i8,
+     e2: i8,
+     e1: i8,
+     e0: i8,
+ ) -> __m128i {
+     #[rustfmt::skip]
+     transmute(i8x16::new(
+         e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15,
+     ))
+ }
+ 
+ /// Broadcasts 64-bit integer `a` to all elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi64x)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set1_epi64x(a: i64) -> __m128i {
+     _mm_set_epi64x(a, a)
+ }
+ 
+ /// Broadcasts 32-bit integer `a` to all elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set1_epi32(a: i32) -> __m128i {
+     _mm_set_epi32(a, a, a, a)
+ }
+ 
+ /// Broadcasts 16-bit integer `a` to all elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set1_epi16(a: i16) -> __m128i {
+     _mm_set_epi16(a, a, a, a, a, a, a, a)
+ }
+ 
+ /// Broadcasts 8-bit integer `a` to all elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set1_epi8(a: i8) -> __m128i {
+     _mm_set_epi8(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
+ }
+ 
+ /// Sets packed 32-bit integers with the supplied values in reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setr_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i {
+     _mm_set_epi32(e0, e1, e2, e3)
+ }
+ 
+ /// Sets packed 16-bit integers with the supplied values in reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setr_epi16(
+     e7: i16,
+     e6: i16,
+     e5: i16,
+     e4: i16,
+     e3: i16,
+     e2: i16,
+     e1: i16,
+     e0: i16,
+ ) -> __m128i {
+     _mm_set_epi16(e0, e1, e2, e3, e4, e5, e6, e7)
+ }
+ 
+ /// Sets packed 8-bit integers with the supplied values in reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // no particular instruction to test
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setr_epi8(
+     e15: i8,
+     e14: i8,
+     e13: i8,
+     e12: i8,
+     e11: i8,
+     e10: i8,
+     e9: i8,
+     e8: i8,
+     e7: i8,
+     e6: i8,
+     e5: i8,
+     e4: i8,
+     e3: i8,
+     e2: i8,
+     e1: i8,
+     e0: i8,
+ ) -> __m128i {
+     #[rustfmt::skip]
+     _mm_set_epi8(
+         e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15,
+     )
+ }
+ 
+ /// Returns a vector with all elements set to zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(xorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setzero_si128() -> __m128i {
+     _mm_set1_epi64x(0)
+ }
+ 
+ /// Loads 64-bit integer from memory into first element of returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadl_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // FIXME movsd on windows
+ #[cfg_attr(
+     all(
+         test,
+         not(windows),
+         not(all(target_os = "linux", target_arch = "x86_64")),
+         target_arch = "x86_64"
+     ),
+     assert_instr(movq)
+ )]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadl_epi64(mem_addr: *const __m128i) -> __m128i {
+     _mm_set_epi64x(0, ptr::read_unaligned(mem_addr as *const i64))
+ }
+ 
+ /// Loads 128-bits of integer data from memory into a new vector.
+ ///
+ /// `mem_addr` must be aligned on a 16-byte boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load_si128(mem_addr: *const __m128i) -> __m128i {
+     *mem_addr
+ }
+ 
+ /// Loads 128-bits of integer data from memory into a new vector.
+ ///
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadu_si128(mem_addr: *const __m128i) -> __m128i {
+     let mut dst: __m128i = _mm_undefined_si128();
+     ptr::copy_nonoverlapping(
+         mem_addr as *const u8,
+         &mut dst as *mut __m128i as *mut u8,
+         mem::size_of::<__m128i>(),
+     );
+     dst
+ }
+ 
+ /// Conditionally store 8-bit integer elements from `a` into memory using
+ /// `mask`.
+ ///
+ /// Elements are not stored when the highest bit is not set in the
+ /// corresponding element.
+ ///
+ /// `mem_addr` should correspond to a 128-bit memory location and does not need
+ /// to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskmoveu_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(maskmovdqu))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maskmoveu_si128(a: __m128i, mask: __m128i, mem_addr: *mut i8) {
+     maskmovdqu(a.as_i8x16(), mask.as_i8x16(), mem_addr)
+ }
+ 
+ /// Stores 128-bits of integer data from `a` into memory.
+ ///
+ /// `mem_addr` must be aligned on a 16-byte boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_store_si128(mem_addr: *mut __m128i, a: __m128i) {
+     *mem_addr = a;
+ }
+ 
+ /// Stores 128-bits of integer data from `a` into memory.
+ ///
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movups))] // FIXME movdqu expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_storeu_si128(mem_addr: *mut __m128i, a: __m128i) {
+     storeudq(mem_addr as *mut i8, a);
+ }
+ 
+ /// Stores the lower 64-bit integer `a` to a memory location.
+ ///
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storel_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // FIXME mov on windows, movlps on i686
+ #[cfg_attr(
+     all(
+         test,
+         not(windows),
+         not(all(target_os = "linux", target_arch = "x86_64")),
+         target_arch = "x86_64"
+     ),
+     assert_instr(movq)
+ )]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_storel_epi64(mem_addr: *mut __m128i, a: __m128i) {
+     ptr::copy_nonoverlapping(&a as *const _ as *const u8, mem_addr as *mut u8, 8);
+ }
+ 
+ /// Stores a 128-bit integer vector to a 128-bit aligned memory location.
+ /// To minimize caching, the data is flagged as non-temporal (unlikely to be
+ /// used again soon).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movntps))] // FIXME movntdq
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_stream_si128(mem_addr: *mut __m128i, a: __m128i) {
+     intrinsics::nontemporal_store(mem_addr, a);
+ }
+ 
+ /// Stores a 32-bit integer value in the specified memory location.
+ /// To minimize caching, the data is flagged as non-temporal (unlikely to be
+ /// used again soon).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_si32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movnti))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_stream_si32(mem_addr: *mut i32, a: i32) {
+     intrinsics::nontemporal_store(mem_addr, a);
+ }
+ 
+ /// Returns a vector where the low element is extracted from `a` and its upper
+ /// element is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // FIXME movd on windows, movd on i686
+ #[cfg_attr(all(test, not(windows), target_arch = "x86_64"), assert_instr(movq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_move_epi64(a: __m128i) -> __m128i {
+     let zero = _mm_setzero_si128();
+     let r: i64x2 = simd_shuffle2(a.as_i64x2(), zero.as_i64x2(), [0, 2]);
+     transmute(r)
+ }
+ 
+ /// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+ /// using signed saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packs_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(packsswb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(packsswb(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+ /// using signed saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packs_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(packssdw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(packssdw(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers
+ /// using unsigned saturation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packus_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(packuswb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(packuswb(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Returns the `imm8` element of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pextrw, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_extract_epi16(a: __m128i, imm8: i32) -> i32 {
+     let a = a.as_u16x8();
+     macro_rules! call {
+         ($imm3:expr) => {
+             simd_extract::<_, u16>(a, $imm3) as i32
+         };
+     }
+     constify_imm3!(imm8, call)
+ }
+ 
+ /// Returns a new vector where the `imm8` element of `a` is replaced with `i`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pinsrw, imm8 = 9))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_insert_epi16(a: __m128i, i: i32, imm8: i32) -> __m128i {
+     let a = a.as_i16x8();
+     macro_rules! call {
+         ($imm3:expr) => {
+             transmute(simd_insert(a, $imm3, i as i16))
+         };
+     }
+     constify_imm3!(imm8, call)
+ }
+ 
+ /// Returns a mask of the most significant bit of each element in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movemask_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pmovmskb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movemask_epi8(a: __m128i) -> i32 {
+     pmovmskb(a.as_i8x16())
+ }
+ 
+ /// Shuffles 32-bit integers in `a` using the control in `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pshufd, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_shuffle_epi32(a: __m128i, imm8: i32) -> __m128i {
+     // simd_shuffleX requires that its selector parameter be made up of
+     // constant values, but we can't enforce that here. In spirit, we need
+     // to write a `match` on all possible values of a byte, and for each value,
+     // hard-code the correct `simd_shuffleX` call using only constants. We
+     // then hope for LLVM to do the rest.
+     //
+     // Of course, that's... awful. So we try to use macros to do it for us.
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i32x4();
+ 
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             simd_shuffle4(a, a, [$x01, $x23, $x45, $x67])
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     let x: i32x4 = match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     };
+     transmute(x)
+ }
+ 
+ /// Shuffles 16-bit integers in the high 64 bits of `a` using the control in
+ /// `imm8`.
+ ///
+ /// Put the results in the high 64 bits of the returned vector, with the low 64
+ /// bits being copied from from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shufflehi_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pshufhw, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_shufflehi_epi16(a: __m128i, imm8: i32) -> __m128i {
+     // See _mm_shuffle_epi32.
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i16x8();
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             simd_shuffle8(a, a, [0, 1, 2, 3, $x01 + 4, $x23 + 4, $x45 + 4, $x67 + 4])
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     let x: i16x8 = match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     };
+     transmute(x)
+ }
+ 
+ /// Shuffles 16-bit integers in the low 64 bits of `a` using the control in
+ /// `imm8`.
+ ///
+ /// Put the results in the low 64 bits of the returned vector, with the high 64
+ /// bits being copied from from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shufflelo_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(pshuflw, imm8 = 9))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_shufflelo_epi16(a: __m128i, imm8: i32) -> __m128i {
+     // See _mm_shuffle_epi32.
+     let imm8 = (imm8 & 0xFF) as u8;
+     let a = a.as_i16x8();
+ 
+     macro_rules! shuffle_done {
+         ($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
+             simd_shuffle8(a, a, [$x01, $x23, $x45, $x67, 4, 5, 6, 7])
+         };
+     }
+     macro_rules! shuffle_x67 {
+         ($x01:expr, $x23:expr, $x45:expr) => {
+             match (imm8 >> 6) & 0b11 {
+                 0b00 => shuffle_done!($x01, $x23, $x45, 0),
+                 0b01 => shuffle_done!($x01, $x23, $x45, 1),
+                 0b10 => shuffle_done!($x01, $x23, $x45, 2),
+                 _ => shuffle_done!($x01, $x23, $x45, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x45 {
+         ($x01:expr, $x23:expr) => {
+             match (imm8 >> 4) & 0b11 {
+                 0b00 => shuffle_x67!($x01, $x23, 0),
+                 0b01 => shuffle_x67!($x01, $x23, 1),
+                 0b10 => shuffle_x67!($x01, $x23, 2),
+                 _ => shuffle_x67!($x01, $x23, 3),
+             }
+         };
+     }
+     macro_rules! shuffle_x23 {
+         ($x01:expr) => {
+             match (imm8 >> 2) & 0b11 {
+                 0b00 => shuffle_x45!($x01, 0),
+                 0b01 => shuffle_x45!($x01, 1),
+                 0b10 => shuffle_x45!($x01, 2),
+                 _ => shuffle_x45!($x01, 3),
+             }
+         };
+     }
+     let x: i16x8 = match imm8 & 0b11 {
+         0b00 => shuffle_x23!(0),
+         0b01 => shuffle_x23!(1),
+         0b10 => shuffle_x23!(2),
+         _ => shuffle_x23!(3),
+     };
+     transmute(x)
+ }
+ 
+ /// Unpacks and interleave 8-bit integers from the high half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(punpckhbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpackhi_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i8x16, _>(simd_shuffle16(
+         a.as_i8x16(),
+         b.as_i8x16(),
+         [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31],
+     ))
+ }
+ 
+ /// Unpacks and interleave 16-bit integers from the high half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(punpckhwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpackhi_epi16(a: __m128i, b: __m128i) -> __m128i {
+     let x = simd_shuffle8(a.as_i16x8(), b.as_i16x8(), [4, 12, 5, 13, 6, 14, 7, 15]);
+     transmute::<i16x8, _>(x)
+ }
+ 
+ /// Unpacks and interleave 32-bit integers from the high half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(unpckhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpackhi_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i32x4, _>(simd_shuffle4(a.as_i32x4(), b.as_i32x4(), [2, 6, 3, 7]))
+ }
+ 
+ /// Unpacks and interleave 64-bit integers from the high half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(unpckhpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpackhi_epi64(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i64x2, _>(simd_shuffle2(a.as_i64x2(), b.as_i64x2(), [1, 3]))
+ }
+ 
+ /// Unpacks and interleave 8-bit integers from the low half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi8)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(punpcklbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpacklo_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i8x16, _>(simd_shuffle16(
+         a.as_i8x16(),
+         b.as_i8x16(),
+         [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23],
+     ))
+ }
+ 
+ /// Unpacks and interleave 16-bit integers from the low half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi16)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(punpcklwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpacklo_epi16(a: __m128i, b: __m128i) -> __m128i {
+     let x = simd_shuffle8(a.as_i16x8(), b.as_i16x8(), [0, 8, 1, 9, 2, 10, 3, 11]);
+     transmute::<i16x8, _>(x)
+ }
+ 
+ /// Unpacks and interleave 32-bit integers from the low half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(unpcklps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpacklo_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i32x4, _>(simd_shuffle4(a.as_i32x4(), b.as_i32x4(), [0, 4, 1, 5]))
+ }
+ 
+ /// Unpacks and interleave 64-bit integers from the low half of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpacklo_epi64(a: __m128i, b: __m128i) -> __m128i {
+     transmute::<i64x2, _>(simd_shuffle2(a.as_i64x2(), b.as_i64x2(), [0, 2]))
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the sum of the
+ /// low elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(addsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(a, 0, _mm_cvtsd_f64(a) + _mm_cvtsd_f64(b))
+ }
+ 
+ /// Adds packed double-precision (64-bit) floating-point elements in `a` and
+ /// `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(addpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_add_pd(a: __m128d, b: __m128d) -> __m128d {
+     simd_add(a, b)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the result of
+ /// diving the lower element of `a` by the lower element of `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(divsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_div_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(a, 0, _mm_cvtsd_f64(a) / _mm_cvtsd_f64(b))
+ }
+ 
+ /// Divide packed double-precision (64-bit) floating-point elements in `a` by
+ /// packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(divpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_div_pd(a: __m128d, b: __m128d) -> __m128d {
+     simd_div(a, b)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the maximum
+ /// of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(maxsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_sd(a: __m128d, b: __m128d) -> __m128d {
+     maxsd(a, b)
+ }
+ 
+ /// Returns a new vector with the maximum values from corresponding elements in
+ /// `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(maxpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_pd(a: __m128d, b: __m128d) -> __m128d {
+     maxpd(a, b)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the minimum
+ /// of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(minsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_sd(a: __m128d, b: __m128d) -> __m128d {
+     minsd(a, b)
+ }
+ 
+ /// Returns a new vector with the minimum values from corresponding elements in
+ /// `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(minpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_pd(a: __m128d, b: __m128d) -> __m128d {
+     minpd(a, b)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by multiplying the
+ /// low elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(mulsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mul_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(a, 0, _mm_cvtsd_f64(a) * _mm_cvtsd_f64(b))
+ }
+ 
+ /// Multiplies packed double-precision (64-bit) floating-point elements in `a`
+ /// and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(mulpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mul_pd(a: __m128d, b: __m128d) -> __m128d {
+     simd_mul(a, b)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the square
+ /// root of the lower element `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(sqrtsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sqrt_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(a, 0, _mm_cvtsd_f64(sqrtsd(b)))
+ }
+ 
+ /// Returns a new vector with the square root of each of the values in `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(sqrtpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sqrt_pd(a: __m128d) -> __m128d {
+     simd_fsqrt(a)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by subtracting the
+ /// low element by `b` from the low element of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(subsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(a, 0, _mm_cvtsd_f64(a) - _mm_cvtsd_f64(b))
+ }
+ 
+ /// Subtract packed double-precision (64-bit) floating-point elements in `b`
+ /// from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(subpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sub_pd(a: __m128d, b: __m128d) -> __m128d {
+     simd_sub(a, b)
+ }
+ 
+ /// Computes the bitwise AND of packed double-precision (64-bit) floating-point
+ /// elements in `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_and_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(andps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_and_pd(a: __m128d, b: __m128d) -> __m128d {
+     let a: __m128i = transmute(a);
+     let b: __m128i = transmute(b);
+     transmute(_mm_and_si128(a, b))
+ }
+ 
+ /// Computes the bitwise NOT of `a` and then AND with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_andnot_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(andnps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_andnot_pd(a: __m128d, b: __m128d) -> __m128d {
+     let a: __m128i = transmute(a);
+     let b: __m128i = transmute(b);
+     transmute(_mm_andnot_si128(a, b))
+ }
+ 
+ /// Computes the bitwise OR of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_or_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(orps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_or_pd(a: __m128d, b: __m128d) -> __m128d {
+     let a: __m128i = transmute(a);
+     let b: __m128i = transmute(b);
+     transmute(_mm_or_si128(a, b))
+ }
+ 
+ /// Computes the bitwise OR of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_xor_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(xorps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_xor_pd(a: __m128d, b: __m128d) -> __m128d {
+     let a: __m128i = transmute(a);
+     let b: __m128i = transmute(b);
+     transmute(_mm_xor_si128(a, b))
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the equality
+ /// comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpeqsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 0)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the less-than
+ /// comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpltsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 1)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// less-than-or-equal comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmple_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmplesd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmple_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 2)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// greater-than comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpltsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(_mm_cmplt_sd(b, a), 1, simd_extract::<_, f64>(a, 1))
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// greater-than-or-equal comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpge_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmplesd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpge_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(_mm_cmple_sd(b, a), 1, simd_extract::<_, f64>(a, 1))
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the result
+ /// of comparing both of the lower elements of `a` and `b` to `NaN`. If
+ /// neither are equal to `NaN` then `0xFFFFFFFFFFFFFFFF` is used and `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpord_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpordsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpord_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 7)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the result of
+ /// comparing both of the lower elements of `a` and `b` to `NaN`. If either is
+ /// equal to `NaN` then `0xFFFFFFFFFFFFFFFF` is used and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpunord_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpunordsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpunord_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 3)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the not-equal
+ /// comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpneq_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpneqsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpneq_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 4)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// not-less-than comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnlt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnltsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnlt_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 5)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// not-less-than-or-equal comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnle_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnlesd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnle_sd(a: __m128d, b: __m128d) -> __m128d {
+     cmpsd(a, b, 6)
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// not-greater-than comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpngt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnltsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpngt_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(_mm_cmpnlt_sd(b, a), 1, simd_extract::<_, f64>(a, 1))
+ }
+ 
+ /// Returns a new vector with the low element of `a` replaced by the
+ /// not-greater-than-or-equal comparison of the lower elements of `a` and `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnge_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnlesd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnge_sd(a: __m128d, b: __m128d) -> __m128d {
+     simd_insert(_mm_cmpnle_sd(b, a), 1, simd_extract::<_, f64>(a, 1))
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpeqpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 0)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpltpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmplt_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 1)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for less-than-or-equal
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmple_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmplepd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmple_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 2)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpltpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_pd(a: __m128d, b: __m128d) -> __m128d {
+     _mm_cmplt_pd(b, a)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for greater-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpge_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmplepd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpge_pd(a: __m128d, b: __m128d) -> __m128d {
+     _mm_cmple_pd(b, a)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` to see if neither is `NaN`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpord_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpordpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpord_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 7)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` to see if either is `NaN`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpunord_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpunordpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpunord_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 3)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for not-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpneq_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpneqpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpneq_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 4)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for not-less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnlt_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnltpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnlt_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 5)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for not-less-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnle_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnlepd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnle_pd(a: __m128d, b: __m128d) -> __m128d {
+     cmppd(a, b, 6)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for not-greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpngt_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnltpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpngt_pd(a: __m128d, b: __m128d) -> __m128d {
+     _mm_cmpnlt_pd(b, a)
+ }
+ 
+ /// Compares corresponding elements in `a` and `b` for
+ /// not-greater-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnge_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cmpnlepd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpnge_pd(a: __m128d, b: __m128d) -> __m128d {
+     _mm_cmpnle_pd(b, a)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(comisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comieq_sd(a: __m128d, b: __m128d) -> i32 {
+     comieqsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(comisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comilt_sd(a: __m128d, b: __m128d) -> i32 {
+     comiltsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for less-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(comisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comile_sd(a: __m128d, b: __m128d) -> i32 {
+     comilesd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(comisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comigt_sd(a: __m128d, b: __m128d) -> i32 {
+     comigtsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for greater-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(comisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comige_sd(a: __m128d, b: __m128d) -> i32 {
+     comigesd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for not-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(comisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_comineq_sd(a: __m128d, b: __m128d) -> i32 {
+     comineqsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for equality.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(ucomisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomieq_sd(a: __m128d, b: __m128d) -> i32 {
+     ucomieqsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for less-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(ucomisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomilt_sd(a: __m128d, b: __m128d) -> i32 {
+     ucomiltsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for less-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(ucomisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomile_sd(a: __m128d, b: __m128d) -> i32 {
+     ucomilesd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for greater-than.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(ucomisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomigt_sd(a: __m128d, b: __m128d) -> i32 {
+     ucomigtsd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for greater-than-or-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(ucomisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomige_sd(a: __m128d, b: __m128d) -> i32 {
+     ucomigesd(a, b)
+ }
+ 
+ /// Compares the lower element of `a` and `b` for not-equal.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(ucomisd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ucomineq_sd(a: __m128d, b: __m128d) -> i32 {
+     ucomineqsd(a, b)
+ }
+ 
+ /// Converts packed double-precision (64-bit) floating-point elements in `a` to
+ /// packed single-precision (32-bit) floating-point elements
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_ps)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtpd2ps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtpd_ps(a: __m128d) -> __m128 {
+     cvtpd2ps(a)
+ }
+ 
+ /// Converts packed single-precision (32-bit) floating-point elements in `a` to
+ /// packed
+ /// double-precision (64-bit) floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtps_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtps2pd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtps_pd(a: __m128) -> __m128d {
+     cvtps2pd(a)
+ }
+ 
+ /// Converts packed double-precision (64-bit) floating-point elements in `a` to
+ /// packed 32-bit integers.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtpd2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtpd_epi32(a: __m128d) -> __m128i {
+     transmute(cvtpd2dq(a))
+ }
+ 
+ /// Converts the lower double-precision (64-bit) floating-point element in a to
+ /// a 32-bit integer.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_si32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsd2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsd_si32(a: __m128d) -> i32 {
+     cvtsd2si(a)
+ }
+ 
+ /// Converts the lower double-precision (64-bit) floating-point element in `b`
+ /// to a single-precision (32-bit) floating-point element, store the result in
+ /// the lower element of the return value, and copies the upper element from `a`
+ /// to the upper element the return value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_ss)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsd2ss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsd_ss(a: __m128, b: __m128d) -> __m128 {
+     cvtsd2ss(a, b)
+ }
+ 
+ /// Returns the lower double-precision (64-bit) floating-point element of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_f64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsd_f64(a: __m128d) -> f64 {
+     simd_extract(a, 0)
+ }
+ 
+ /// Converts the lower single-precision (32-bit) floating-point element in `b`
+ /// to a double-precision (64-bit) floating-point element, store the result in
+ /// the lower element of the return value, and copies the upper element from `a`
+ /// to the upper element the return value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtss2sd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtss_sd(a: __m128d, b: __m128) -> __m128d {
+     cvtss2sd(a, b)
+ }
+ 
+ /// Converts packed double-precision (64-bit) floating-point elements in `a` to
+ /// packed 32-bit integers with truncation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttpd_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvttpd2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttpd_epi32(a: __m128d) -> __m128i {
+     transmute(cvttpd2dq(a))
+ }
+ 
+ /// Converts the lower double-precision (64-bit) floating-point element in `a`
+ /// to a 32-bit integer with truncation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_si32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvttsd2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttsd_si32(a: __m128d) -> i32 {
+     cvttsd2si(a)
+ }
+ 
+ /// Converts packed single-precision (32-bit) floating-point elements in `a` to
+ /// packed 32-bit integers with truncation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttps_epi32)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvttps2dq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttps_epi32(a: __m128) -> __m128i {
+     transmute(cvttps2dq(a))
+ }
+ 
+ /// Copies double-precision (64-bit) floating-point element `a` to the lower
+ /// element of the packed 64-bit return value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_sd(a: f64) -> __m128d {
+     _mm_set_pd(0.0, a)
+ }
+ 
+ /// Broadcasts double-precision (64-bit) floating-point value a to all elements
+ /// of the return value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set1_pd(a: f64) -> __m128d {
+     _mm_set_pd(a, a)
+ }
+ 
+ /// Broadcasts double-precision (64-bit) floating-point value a to all elements
+ /// of the return value.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_pd1)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_pd1(a: f64) -> __m128d {
+     _mm_set_pd(a, a)
+ }
+ 
+ /// Sets packed double-precision (64-bit) floating-point elements in the return
+ /// value with the supplied values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_set_pd(a: f64, b: f64) -> __m128d {
+     __m128d(b, a)
+ }
+ 
+ /// Sets packed double-precision (64-bit) floating-point elements in the return
+ /// value with the supplied values in reverse order.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setr_pd(a: f64, b: f64) -> __m128d {
+     _mm_set_pd(b, a)
+ }
+ 
+ /// Returns packed double-precision (64-bit) floating-point elements with all
+ /// zeros.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(xorps))] // FIXME xorpd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_setzero_pd() -> __m128d {
+     _mm_set_pd(0.0, 0.0)
+ }
+ 
+ /// Returns a mask of the most significant bit of each element in `a`.
+ ///
+ /// The mask is stored in the 2 least significant bits of the return value.
+ /// All other bits are set to `0`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movemask_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movmskpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movemask_pd(a: __m128d) -> i32 {
+     movmskpd(a)
+ }
+ 
+ /// Loads 128-bits (composed of 2 packed double-precision (64-bit)
+ /// floating-point elements) from memory into the returned vector.
+ /// `mem_addr` must be aligned on a 16-byte boundary or a general-protection
+ /// exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_load_pd(mem_addr: *const f64) -> __m128d {
+     *(mem_addr as *const __m128d)
+ }
+ 
+ /// Loads a 64-bit double-precision value to the low element of a
+ /// 128-bit integer vector and clears the upper element.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load_sd(mem_addr: *const f64) -> __m128d {
+     _mm_setr_pd(*mem_addr, 0.)
+ }
+ 
+ /// Loads a double-precision value into the high-order bits of a 128-bit
+ /// vector of `[2 x double]`. The low-order bits are copied from the low-order
+ /// bits of the first operand.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadh_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadh_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
+     _mm_setr_pd(simd_extract(a, 0), *mem_addr)
+ }
+ 
+ /// Loads a double-precision value into the low-order bits of a 128-bit
+ /// vector of `[2 x double]`. The high-order bits are copied from the
+ /// high-order bits of the first operand.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadl_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movlps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadl_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
+     _mm_setr_pd(*mem_addr, simd_extract(a, 1))
+ }
+ 
+ /// Stores a 128-bit floating point vector of `[2 x double]` to a 128-bit
+ /// aligned memory location.
+ /// To minimize caching, the data is flagged as non-temporal (unlikely to be
+ /// used again soon).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movntps))] // FIXME movntpd
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_stream_pd(mem_addr: *mut f64, a: __m128d) {
+     intrinsics::nontemporal_store(mem_addr as *mut __m128d, a);
+ }
+ 
+ /// Stores the lower 64 bits of a 128-bit vector of `[2 x double]` to a
+ /// memory location.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) {
+     *mem_addr = simd_extract(a, 0)
+ }
+ 
+ /// Stores 128-bits (composed of 2 packed double-precision (64-bit)
+ /// floating-point elements) from `a` into memory. `mem_addr` must be aligned
+ /// on a 16-byte boundary or a general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_store_pd(mem_addr: *mut f64, a: __m128d) {
+     *(mem_addr as *mut __m128d) = a;
+ }
+ 
+ /// Stores 128-bits (composed of 2 packed double-precision (64-bit)
+ /// floating-point elements) from `a` into memory.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movups))] // FIXME movupd expected
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_storeu_pd(mem_addr: *mut f64, a: __m128d) {
+     storeupd(mem_addr as *mut i8, a);
+ }
+ 
+ /// Stores the lower double-precision (64-bit) floating-point element from `a`
+ /// into 2 contiguous elements in memory. `mem_addr` must be aligned on a
+ /// 16-byte boundary or a general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store1_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_store1_pd(mem_addr: *mut f64, a: __m128d) {
+     let b: __m128d = simd_shuffle2(a, a, [0, 0]);
+     *(mem_addr as *mut __m128d) = b;
+ }
+ 
+ /// Stores the lower double-precision (64-bit) floating-point element from `a`
+ /// into 2 contiguous elements in memory. `mem_addr` must be aligned on a
+ /// 16-byte boundary or a general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_pd1)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_store_pd1(mem_addr: *mut f64, a: __m128d) {
+     let b: __m128d = simd_shuffle2(a, a, [0, 0]);
+     *(mem_addr as *mut __m128d) = b;
+ }
+ 
+ /// Stores 2 double-precision (64-bit) floating-point elements from `a` into
+ /// memory in reverse order.
+ /// `mem_addr` must be aligned on a 16-byte boundary or a general-protection
+ /// exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storer_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ #[allow(clippy::cast_ptr_alignment)]
+ pub unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) {
+     let b: __m128d = simd_shuffle2(a, a, [1, 0]);
+     *(mem_addr as *mut __m128d) = b;
+ }
+ 
+ /// Stores the upper 64 bits of a 128-bit vector of `[2 x double]` to a
+ /// memory location.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeh_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
+     *mem_addr = simd_extract(a, 1);
+ }
+ 
+ /// Stores the lower 64 bits of a 128-bit vector of `[2 x double]` to a
+ /// memory location.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storel_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_storel_pd(mem_addr: *mut f64, a: __m128d) {
+     *mem_addr = simd_extract(a, 0);
+ }
+ 
+ /// Loads a double-precision (64-bit) floating-point element from memory
+ /// into both elements of returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load1_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // #[cfg_attr(test, assert_instr(movapd))] // FIXME LLVM uses different codegen
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load1_pd(mem_addr: *const f64) -> __m128d {
+     let d = *mem_addr;
+     _mm_setr_pd(d, d)
+ }
+ 
+ /// Loads a double-precision (64-bit) floating-point element from memory
+ /// into both elements of returned vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_pd1)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ // #[cfg_attr(test, assert_instr(movapd))] // FIXME same as _mm_load1_pd
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_load_pd1(mem_addr: *const f64) -> __m128d {
+     _mm_load1_pd(mem_addr)
+ }
+ 
+ /// Loads 2 double-precision (64-bit) floating-point elements from memory into
+ /// the returned vector in reverse order. `mem_addr` must be aligned on a
+ /// 16-byte boundary or a general-protection exception may be generated.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadr_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movaps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadr_pd(mem_addr: *const f64) -> __m128d {
+     let a = _mm_load_pd(mem_addr);
+     simd_shuffle2(a, a, [1, 0])
+ }
+ 
+ /// Loads 128-bits (composed of 2 packed double-precision (64-bit)
+ /// floating-point elements) from memory into the returned vector.
+ /// `mem_addr` does not need to be aligned on any particular boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movups))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loadu_pd(mem_addr: *const f64) -> __m128d {
+     let mut dst = _mm_undefined_pd();
+     ptr::copy_nonoverlapping(
+         mem_addr as *const u8,
+         &mut dst as *mut __m128d as *mut u8,
+         mem::size_of::<__m128d>(),
+     );
+     dst
+ }
+ 
+ /// Constructs a 128-bit floating-point vector of `[2 x double]` from two
+ /// 128-bit vector parameters of `[2 x double]`, using the immediate-value
+ /// parameter as a specifier.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(shufps, imm8 = 1))]
+ #[cfg_attr(all(test, target_os = "windows"), assert_instr(shufpd, imm8 = 1))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_shuffle_pd(a: __m128d, b: __m128d, imm8: i32) -> __m128d {
+     match imm8 & 0b11 {
+         0b00 => simd_shuffle2(a, b, [0, 2]),
+         0b01 => simd_shuffle2(a, b, [1, 2]),
+         0b10 => simd_shuffle2(a, b, [0, 3]),
+         _ => simd_shuffle2(a, b, [1, 3]),
+     }
+ }
+ 
+ /// Constructs a 128-bit floating-point vector of `[2 x double]`. The lower
+ /// 64 bits are set to the lower 64 bits of the second parameter. The upper
+ /// 64 bits are set to the upper 64 bits of the first parameter.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movsd))]
+ #[cfg_attr(all(test, target_os = "windows"), assert_instr(movlps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_move_sd(a: __m128d, b: __m128d) -> __m128d {
+     _mm_setr_pd(simd_extract(b, 0), simd_extract(a, 1))
+ }
+ 
+ /// Casts a 128-bit floating-point vector of `[2 x double]` into a 128-bit
+ /// floating-point vector of `[4 x float]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ps)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_castpd_ps(a: __m128d) -> __m128 {
+     transmute(a)
+ }
+ 
+ /// Casts a 128-bit floating-point vector of `[2 x double]` into a 128-bit
+ /// integer vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_castpd_si128(a: __m128d) -> __m128i {
+     transmute(a)
+ }
+ 
+ /// Casts a 128-bit floating-point vector of `[4 x float]` into a 128-bit
+ /// floating-point vector of `[2 x double]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_castps_pd(a: __m128) -> __m128d {
+     transmute(a)
+ }
+ 
+ /// Casts a 128-bit floating-point vector of `[4 x float]` into a 128-bit
+ /// integer vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_castps_si128(a: __m128) -> __m128i {
+     transmute(a)
+ }
+ 
+ /// Casts a 128-bit integer vector into a 128-bit floating-point vector
+ /// of `[2 x double]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_castsi128_pd(a: __m128i) -> __m128d {
+     transmute(a)
+ }
+ 
+ /// Casts a 128-bit integer vector into a 128-bit floating-point vector
+ /// of `[4 x float]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ps)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_castsi128_ps(a: __m128i) -> __m128 {
+     transmute(a)
+ }
+ 
+ /// Returns vector of type __m128d with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_undefined_pd() -> __m128d {
+     // FIXME: this function should return MaybeUninit<__m128d>
+     mem::MaybeUninit::<__m128d>::uninit().assume_init()
+ }
+ 
+ /// Returns vector of type __m128i with undefined elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_undefined_si128() -> __m128i {
+     // FIXME: this function should return MaybeUninit<__m128i>
+     mem::MaybeUninit::<__m128i>::uninit().assume_init()
+ }
+ 
+ /// The resulting `__m128d` element is composed by the low-order values of
+ /// the two `__m128d` interleaved input elements, i.e.:
+ ///
+ /// * The `[127:64]` bits are copied from the `[127:64]` bits of the second
+ /// input * The `[63:0]` bits are copied from the `[127:64]` bits of the first
+ /// input
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(unpckhpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d {
+     simd_shuffle2(a, b, [1, 3])
+ }
+ 
+ /// The resulting `__m128d` element is composed by the high-order values of
+ /// the two `__m128d` interleaved input elements, i.e.:
+ ///
+ /// * The `[127:64]` bits are copied from the `[63:0]` bits of the second input
+ /// * The `[63:0]` bits are copied from the `[63:0]` bits of the first input
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_pd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlhps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d {
+     simd_shuffle2(a, b, [0, 2])
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse2.pause"]
+     fn pause();
+     #[link_name = "llvm.x86.sse2.clflush"]
+     fn clflush(p: *const u8);
+     #[link_name = "llvm.x86.sse2.lfence"]
+     fn lfence();
+     #[link_name = "llvm.x86.sse2.mfence"]
+     fn mfence();
+     #[link_name = "llvm.x86.sse2.pavg.b"]
+     fn pavgb(a: u8x16, b: u8x16) -> u8x16;
+     #[link_name = "llvm.x86.sse2.pavg.w"]
+     fn pavgw(a: u16x8, b: u16x8) -> u16x8;
+     #[link_name = "llvm.x86.sse2.pmadd.wd"]
+     fn pmaddwd(a: i16x8, b: i16x8) -> i32x4;
+     #[link_name = "llvm.x86.sse2.pmaxs.w"]
+     fn pmaxsw(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.x86.sse2.pmaxu.b"]
+     fn pmaxub(a: u8x16, b: u8x16) -> u8x16;
+     #[link_name = "llvm.x86.sse2.pmins.w"]
+     fn pminsw(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.x86.sse2.pminu.b"]
+     fn pminub(a: u8x16, b: u8x16) -> u8x16;
+     #[link_name = "llvm.x86.sse2.pmulh.w"]
+     fn pmulhw(a: i16x8, b: i16x8) -> i16x8;
+     #[link_name = "llvm.x86.sse2.pmulhu.w"]
+     fn pmulhuw(a: u16x8, b: u16x8) -> u16x8;
+     #[link_name = "llvm.x86.sse2.pmulu.dq"]
+     fn pmuludq(a: u32x4, b: u32x4) -> u64x2;
+     #[link_name = "llvm.x86.sse2.psad.bw"]
+     fn psadbw(a: u8x16, b: u8x16) -> u64x2;
+     #[link_name = "llvm.x86.sse2.pslli.w"]
+     fn pslliw(a: i16x8, imm8: i32) -> i16x8;
+     #[link_name = "llvm.x86.sse2.psll.w"]
+     fn psllw(a: i16x8, count: i16x8) -> i16x8;
+     #[link_name = "llvm.x86.sse2.pslli.d"]
+     fn psllid(a: i32x4, imm8: i32) -> i32x4;
+     #[link_name = "llvm.x86.sse2.psll.d"]
+     fn pslld(a: i32x4, count: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sse2.pslli.q"]
+     fn pslliq(a: i64x2, imm8: i32) -> i64x2;
+     #[link_name = "llvm.x86.sse2.psll.q"]
+     fn psllq(a: i64x2, count: i64x2) -> i64x2;
+     #[link_name = "llvm.x86.sse2.psrai.w"]
+     fn psraiw(a: i16x8, imm8: i32) -> i16x8;
+     #[link_name = "llvm.x86.sse2.psra.w"]
+     fn psraw(a: i16x8, count: i16x8) -> i16x8;
+     #[link_name = "llvm.x86.sse2.psrai.d"]
+     fn psraid(a: i32x4, imm8: i32) -> i32x4;
+     #[link_name = "llvm.x86.sse2.psra.d"]
+     fn psrad(a: i32x4, count: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sse2.psrli.w"]
+     fn psrliw(a: i16x8, imm8: i32) -> i16x8;
+     #[link_name = "llvm.x86.sse2.psrl.w"]
+     fn psrlw(a: i16x8, count: i16x8) -> i16x8;
+     #[link_name = "llvm.x86.sse2.psrli.d"]
+     fn psrlid(a: i32x4, imm8: i32) -> i32x4;
+     #[link_name = "llvm.x86.sse2.psrl.d"]
+     fn psrld(a: i32x4, count: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sse2.psrli.q"]
+     fn psrliq(a: i64x2, imm8: i32) -> i64x2;
+     #[link_name = "llvm.x86.sse2.psrl.q"]
+     fn psrlq(a: i64x2, count: i64x2) -> i64x2;
+     #[link_name = "llvm.x86.sse2.cvtdq2ps"]
+     fn cvtdq2ps(a: i32x4) -> __m128;
+     #[link_name = "llvm.x86.sse2.cvtps2dq"]
+     fn cvtps2dq(a: __m128) -> i32x4;
+     #[link_name = "llvm.x86.sse2.maskmov.dqu"]
+     fn maskmovdqu(a: i8x16, mask: i8x16, mem_addr: *mut i8);
+     #[link_name = "llvm.x86.sse2.packsswb.128"]
+     fn packsswb(a: i16x8, b: i16x8) -> i8x16;
+     #[link_name = "llvm.x86.sse2.packssdw.128"]
+     fn packssdw(a: i32x4, b: i32x4) -> i16x8;
+     #[link_name = "llvm.x86.sse2.packuswb.128"]
+     fn packuswb(a: i16x8, b: i16x8) -> u8x16;
+     #[link_name = "llvm.x86.sse2.pmovmskb.128"]
+     fn pmovmskb(a: i8x16) -> i32;
+     #[link_name = "llvm.x86.sse2.max.sd"]
+     fn maxsd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse2.max.pd"]
+     fn maxpd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse2.min.sd"]
+     fn minsd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse2.min.pd"]
+     fn minpd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse2.sqrt.sd"]
+     fn sqrtsd(a: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse2.sqrt.pd"]
+     fn sqrtpd(a: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse2.cmp.sd"]
+     fn cmpsd(a: __m128d, b: __m128d, imm8: i8) -> __m128d;
+     #[link_name = "llvm.x86.sse2.cmp.pd"]
+     fn cmppd(a: __m128d, b: __m128d, imm8: i8) -> __m128d;
+     #[link_name = "llvm.x86.sse2.comieq.sd"]
+     fn comieqsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.comilt.sd"]
+     fn comiltsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.comile.sd"]
+     fn comilesd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.comigt.sd"]
+     fn comigtsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.comige.sd"]
+     fn comigesd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.comineq.sd"]
+     fn comineqsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.ucomieq.sd"]
+     fn ucomieqsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.ucomilt.sd"]
+     fn ucomiltsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.ucomile.sd"]
+     fn ucomilesd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.ucomigt.sd"]
+     fn ucomigtsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.ucomige.sd"]
+     fn ucomigesd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.ucomineq.sd"]
+     fn ucomineqsd(a: __m128d, b: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.movmsk.pd"]
+     fn movmskpd(a: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.cvtpd2ps"]
+     fn cvtpd2ps(a: __m128d) -> __m128;
+     #[link_name = "llvm.x86.sse2.cvtps2pd"]
+     fn cvtps2pd(a: __m128) -> __m128d;
+     #[link_name = "llvm.x86.sse2.cvtpd2dq"]
+     fn cvtpd2dq(a: __m128d) -> i32x4;
+     #[link_name = "llvm.x86.sse2.cvtsd2si"]
+     fn cvtsd2si(a: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.cvtsd2ss"]
+     fn cvtsd2ss(a: __m128, b: __m128d) -> __m128;
+     #[link_name = "llvm.x86.sse2.cvtss2sd"]
+     fn cvtss2sd(a: __m128d, b: __m128) -> __m128d;
+     #[link_name = "llvm.x86.sse2.cvttpd2dq"]
+     fn cvttpd2dq(a: __m128d) -> i32x4;
+     #[link_name = "llvm.x86.sse2.cvttsd2si"]
+     fn cvttsd2si(a: __m128d) -> i32;
+     #[link_name = "llvm.x86.sse2.cvttps2dq"]
+     fn cvttps2dq(a: __m128) -> i32x4;
+     #[link_name = "llvm.x86.sse2.storeu.dq"]
+     fn storeudq(mem_addr: *mut i8, a: __m128i);
+     #[link_name = "llvm.x86.sse2.storeu.pd"]
+     fn storeupd(mem_addr: *mut i8, a: __m128d);
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::{
+         core_arch::{simd::*, x86::*},
+         hint::black_box,
+     };
+     use std::{
+         boxed, f32,
+         f64::{self, NAN},
+         i32,
+         mem::{self, transmute},
+     };
+     use stdarch_test::simd_test;
+ 
+     #[test]
+     fn test_mm_pause() {
+         unsafe { _mm_pause() }
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_clflush() {
+         let x = 0_u8;
+         _mm_clflush(&x as *const _);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_lfence() {
+         _mm_lfence();
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mfence() {
+         _mm_mfence();
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_epi8() {
+         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         let r = _mm_add_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_epi8_overflow() {
+         let a = _mm_set1_epi8(0x7F);
+         let b = _mm_set1_epi8(1);
+         let r = _mm_add_epi8(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(-128));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_epi16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm_add_epi16(a, b);
+         let e = _mm_setr_epi16(8, 10, 12, 14, 16, 18, 20, 22);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_epi32() {
+         let a = _mm_setr_epi32(0, 1, 2, 3);
+         let b = _mm_setr_epi32(4, 5, 6, 7);
+         let r = _mm_add_epi32(a, b);
+         let e = _mm_setr_epi32(4, 6, 8, 10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_epi64() {
+         let a = _mm_setr_epi64x(0, 1);
+         let b = _mm_setr_epi64x(2, 3);
+         let r = _mm_add_epi64(a, b);
+         let e = _mm_setr_epi64x(2, 4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epi8() {
+         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         let r = _mm_adds_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epi8_saturate_positive() {
+         let a = _mm_set1_epi8(0x7F);
+         let b = _mm_set1_epi8(1);
+         let r = _mm_adds_epi8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epi8_saturate_negative() {
+         let a = _mm_set1_epi8(-0x80);
+         let b = _mm_set1_epi8(-1);
+         let r = _mm_adds_epi8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epi16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm_adds_epi16(a, b);
+         let e = _mm_setr_epi16(8, 10, 12, 14, 16, 18, 20, 22);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epi16_saturate_positive() {
+         let a = _mm_set1_epi16(0x7FFF);
+         let b = _mm_set1_epi16(1);
+         let r = _mm_adds_epi16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epi16_saturate_negative() {
+         let a = _mm_set1_epi16(-0x8000);
+         let b = _mm_set1_epi16(-1);
+         let r = _mm_adds_epi16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epu8() {
+         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         let r = _mm_adds_epu8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epu8_saturate() {
+         let a = _mm_set1_epi8(!0);
+         let b = _mm_set1_epi8(1);
+         let r = _mm_adds_epu8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epu16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm_adds_epu16(a, b);
+         let e = _mm_setr_epi16(8, 10, 12, 14, 16, 18, 20, 22);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_adds_epu16_saturate() {
+         let a = _mm_set1_epi16(!0);
+         let b = _mm_set1_epi16(1);
+         let r = _mm_adds_epu16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_avg_epu8() {
+         let (a, b) = (_mm_set1_epi8(3), _mm_set1_epi8(9));
+         let r = _mm_avg_epu8(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(6));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_avg_epu16() {
+         let (a, b) = (_mm_set1_epi16(3), _mm_set1_epi16(9));
+         let r = _mm_avg_epu16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(6));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_madd_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm_madd_epi16(a, b);
+         let e = _mm_setr_epi32(29, 81, 149, 233);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_max_epi16() {
+         let a = _mm_set1_epi16(1);
+         let b = _mm_set1_epi16(-1);
+         let r = _mm_max_epi16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_max_epu8() {
+         let a = _mm_set1_epi8(1);
+         let b = _mm_set1_epi8(!0);
+         let r = _mm_max_epu8(a, b);
+         assert_eq_m128i(r, b);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_min_epi16() {
+         let a = _mm_set1_epi16(1);
+         let b = _mm_set1_epi16(-1);
+         let r = _mm_min_epi16(a, b);
+         assert_eq_m128i(r, b);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_min_epu8() {
+         let a = _mm_set1_epi8(1);
+         let b = _mm_set1_epi8(!0);
+         let r = _mm_min_epu8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mulhi_epi16() {
+         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(-1001));
+         let r = _mm_mulhi_epi16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(-16));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mulhi_epu16() {
+         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(1001));
+         let r = _mm_mulhi_epu16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(15));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mullo_epi16() {
+         let (a, b) = (_mm_set1_epi16(1000), _mm_set1_epi16(-1001));
+         let r = _mm_mullo_epi16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(-17960));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mul_epu32() {
+         let a = _mm_setr_epi64x(1_000_000_000, 1 << 34);
+         let b = _mm_setr_epi64x(1_000_000_000, 1 << 35);
+         let r = _mm_mul_epu32(a, b);
+         let e = _mm_setr_epi64x(1_000_000_000 * 1_000_000_000, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sad_epu8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             255u8 as i8, 254u8 as i8, 253u8 as i8, 252u8 as i8,
+             1, 2, 3, 4,
+             155u8 as i8, 154u8 as i8, 153u8 as i8, 152u8 as i8,
+             1, 2, 3, 4,
+         );
+         let b = _mm_setr_epi8(0, 0, 0, 0, 2, 1, 2, 1, 1, 1, 1, 1, 1, 2, 1, 2);
+         let r = _mm_sad_epu8(a, b);
+         let e = _mm_setr_epi64x(1020, 614);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sub_epi8() {
+         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(6));
+         let r = _mm_sub_epi8(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sub_epi16() {
+         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(6));
+         let r = _mm_sub_epi16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sub_epi32() {
+         let (a, b) = (_mm_set1_epi32(5), _mm_set1_epi32(6));
+         let r = _mm_sub_epi32(a, b);
+         assert_eq_m128i(r, _mm_set1_epi32(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sub_epi64() {
+         let (a, b) = (_mm_set1_epi64x(5), _mm_set1_epi64x(6));
+         let r = _mm_sub_epi64(a, b);
+         assert_eq_m128i(r, _mm_set1_epi64x(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epi8() {
+         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(2));
+         let r = _mm_subs_epi8(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(3));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epi8_saturate_positive() {
+         let a = _mm_set1_epi8(0x7F);
+         let b = _mm_set1_epi8(-1);
+         let r = _mm_subs_epi8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epi8_saturate_negative() {
+         let a = _mm_set1_epi8(-0x80);
+         let b = _mm_set1_epi8(1);
+         let r = _mm_subs_epi8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epi16() {
+         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(2));
+         let r = _mm_subs_epi16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(3));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epi16_saturate_positive() {
+         let a = _mm_set1_epi16(0x7FFF);
+         let b = _mm_set1_epi16(-1);
+         let r = _mm_subs_epi16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epi16_saturate_negative() {
+         let a = _mm_set1_epi16(-0x8000);
+         let b = _mm_set1_epi16(1);
+         let r = _mm_subs_epi16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epu8() {
+         let (a, b) = (_mm_set1_epi8(5), _mm_set1_epi8(2));
+         let r = _mm_subs_epu8(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(3));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epu8_saturate() {
+         let a = _mm_set1_epi8(0);
+         let b = _mm_set1_epi8(1);
+         let r = _mm_subs_epu8(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epu16() {
+         let (a, b) = (_mm_set1_epi16(5), _mm_set1_epi16(2));
+         let r = _mm_subs_epu16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(3));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_subs_epu16_saturate() {
+         let a = _mm_set1_epi16(0);
+         let b = _mm_set1_epi16(1);
+         let r = _mm_subs_epu16(a, b);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_slli_si128() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_slli_si128(a, 1);
+         let e = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         assert_eq_m128i(r, e);
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_slli_si128(a, 15);
+         let e = _mm_setr_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1);
+         assert_eq_m128i(r, e);
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_slli_si128(a, 16);
+         assert_eq_m128i(r, _mm_set1_epi8(0));
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_slli_si128(a, -1);
+         assert_eq_m128i(_mm_set1_epi8(0), r);
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_slli_si128(a, -0x80000000);
+         assert_eq_m128i(r, _mm_set1_epi8(0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_slli_epi16() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi16(
+             0xFFFF as u16 as i16, 0x0FFF, 0x00FF, 0x000F, 0, 0, 0, 0,
+         );
+         let r = _mm_slli_epi16(a, 4);
+ 
+         #[rustfmt::skip]
+         let e = _mm_setr_epi16(
+             0xFFF0 as u16 as i16, 0xFFF0 as u16 as i16, 0x0FF0, 0x00F0,
+             0, 0, 0, 0,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sll_epi16() {
+         let a = _mm_setr_epi16(0xFF, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm_sll_epi16(a, _mm_setr_epi16(4, 0, 0, 0, 0, 0, 0, 0));
+         assert_eq_m128i(r, _mm_setr_epi16(0xFF0, 0, 0, 0, 0, 0, 0, 0));
+         let r = _mm_sll_epi16(a, _mm_setr_epi16(0, 0, 0, 0, 4, 0, 0, 0));
+         assert_eq_m128i(r, _mm_setr_epi16(0xFF, 0, 0, 0, 0, 0, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_slli_epi32() {
+         let r = _mm_slli_epi32(_mm_set1_epi32(0xFFFF), 4);
+         assert_eq_m128i(r, _mm_set1_epi32(0xFFFF0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sll_epi32() {
+         let a = _mm_set1_epi32(0xFFFF);
+         let b = _mm_setr_epi32(4, 0, 0, 0);
+         let r = _mm_sll_epi32(a, b);
+         assert_eq_m128i(r, _mm_set1_epi32(0xFFFF0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_slli_epi64() {
+         let r = _mm_slli_epi64(_mm_set1_epi64x(0xFFFFFFFF), 4);
+         assert_eq_m128i(r, _mm_set1_epi64x(0xFFFFFFFF0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sll_epi64() {
+         let a = _mm_set1_epi64x(0xFFFFFFFF);
+         let b = _mm_setr_epi64x(4, 0);
+         let r = _mm_sll_epi64(a, b);
+         assert_eq_m128i(r, _mm_set1_epi64x(0xFFFFFFFF0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srai_epi16() {
+         let r = _mm_srai_epi16(_mm_set1_epi16(-1), 1);
+         assert_eq_m128i(r, _mm_set1_epi16(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sra_epi16() {
+         let a = _mm_set1_epi16(-1);
+         let b = _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm_sra_epi16(a, b);
+         assert_eq_m128i(r, _mm_set1_epi16(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srai_epi32() {
+         let r = _mm_srai_epi32(_mm_set1_epi32(-1), 1);
+         assert_eq_m128i(r, _mm_set1_epi32(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sra_epi32() {
+         let a = _mm_set1_epi32(-1);
+         let b = _mm_setr_epi32(1, 0, 0, 0);
+         let r = _mm_sra_epi32(a, b);
+         assert_eq_m128i(r, _mm_set1_epi32(-1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srli_si128() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_srli_si128(a, 1);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0,
+         );
+         assert_eq_m128i(r, e);
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_srli_si128(a, 15);
+         let e = _mm_setr_epi8(16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_srli_si128(a, 16);
+         assert_eq_m128i(r, _mm_set1_epi8(0));
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_srli_si128(a, -1);
+         assert_eq_m128i(r, _mm_set1_epi8(0));
+ 
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         let r = _mm_srli_si128(a, -0x80000000);
+         assert_eq_m128i(r, _mm_set1_epi8(0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srli_epi16() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi16(
+             0xFFFF as u16 as i16, 0x0FFF, 0x00FF, 0x000F, 0, 0, 0, 0,
+         );
+         let r = _mm_srli_epi16(a, 4);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi16(
+             0xFFF as u16 as i16, 0xFF as u16 as i16, 0xF, 0, 0, 0, 0, 0,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srl_epi16() {
+         let a = _mm_setr_epi16(0xFF, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm_srl_epi16(a, _mm_setr_epi16(4, 0, 0, 0, 0, 0, 0, 0));
+         assert_eq_m128i(r, _mm_setr_epi16(0xF, 0, 0, 0, 0, 0, 0, 0));
+         let r = _mm_srl_epi16(a, _mm_setr_epi16(0, 0, 0, 0, 4, 0, 0, 0));
+         assert_eq_m128i(r, _mm_setr_epi16(0xFF, 0, 0, 0, 0, 0, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srli_epi32() {
+         let r = _mm_srli_epi32(_mm_set1_epi32(0xFFFF), 4);
+         assert_eq_m128i(r, _mm_set1_epi32(0xFFF));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srl_epi32() {
+         let a = _mm_set1_epi32(0xFFFF);
+         let b = _mm_setr_epi32(4, 0, 0, 0);
+         let r = _mm_srl_epi32(a, b);
+         assert_eq_m128i(r, _mm_set1_epi32(0xFFF));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srli_epi64() {
+         let r = _mm_srli_epi64(_mm_set1_epi64x(0xFFFFFFFF), 4);
+         assert_eq_m128i(r, _mm_set1_epi64x(0xFFFFFFF));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_srl_epi64() {
+         let a = _mm_set1_epi64x(0xFFFFFFFF);
+         let b = _mm_setr_epi64x(4, 0);
+         let r = _mm_srl_epi64(a, b);
+         assert_eq_m128i(r, _mm_set1_epi64x(0xFFFFFFF));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_and_si128() {
+         let a = _mm_set1_epi8(5);
+         let b = _mm_set1_epi8(3);
+         let r = _mm_and_si128(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_andnot_si128() {
+         let a = _mm_set1_epi8(5);
+         let b = _mm_set1_epi8(3);
+         let r = _mm_andnot_si128(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(2));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_or_si128() {
+         let a = _mm_set1_epi8(5);
+         let b = _mm_set1_epi8(3);
+         let r = _mm_or_si128(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(7));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_xor_si128() {
+         let a = _mm_set1_epi8(5);
+         let b = _mm_set1_epi8(3);
+         let r = _mm_xor_si128(a, b);
+         assert_eq_m128i(r, _mm_set1_epi8(6));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpeq_epi8() {
+         let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+         let b = _mm_setr_epi8(15, 14, 2, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm_cmpeq_epi8(a, b);
+         #[rustfmt::skip]
+         assert_eq_m128i(
+             r,
+             _mm_setr_epi8(
+                 0, 0, 0xFFu8 as i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+             )
+         );
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpeq_epi16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm_setr_epi16(7, 6, 2, 4, 3, 2, 1, 0);
+         let r = _mm_cmpeq_epi16(a, b);
+         assert_eq_m128i(r, _mm_setr_epi16(0, 0, !0, 0, 0, 0, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpeq_epi32() {
+         let a = _mm_setr_epi32(0, 1, 2, 3);
+         let b = _mm_setr_epi32(3, 2, 2, 0);
+         let r = _mm_cmpeq_epi32(a, b);
+         assert_eq_m128i(r, _mm_setr_epi32(0, 0, !0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpgt_epi8() {
+         let a = _mm_set_epi8(5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         let b = _mm_set1_epi8(0);
+         let r = _mm_cmpgt_epi8(a, b);
+         let e = _mm_set_epi8(!0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpgt_epi16() {
+         let a = _mm_set_epi16(5, 0, 0, 0, 0, 0, 0, 0);
+         let b = _mm_set1_epi16(0);
+         let r = _mm_cmpgt_epi16(a, b);
+         let e = _mm_set_epi16(!0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpgt_epi32() {
+         let a = _mm_set_epi32(5, 0, 0, 0);
+         let b = _mm_set1_epi32(0);
+         let r = _mm_cmpgt_epi32(a, b);
+         assert_eq_m128i(r, _mm_set_epi32(!0, 0, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmplt_epi8() {
+         let a = _mm_set1_epi8(0);
+         let b = _mm_set_epi8(5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm_cmplt_epi8(a, b);
+         let e = _mm_set_epi8(!0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmplt_epi16() {
+         let a = _mm_set1_epi16(0);
+         let b = _mm_set_epi16(5, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm_cmplt_epi16(a, b);
+         let e = _mm_set_epi16(!0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmplt_epi32() {
+         let a = _mm_set1_epi32(0);
+         let b = _mm_set_epi32(5, 0, 0, 0);
+         let r = _mm_cmplt_epi32(a, b);
+         assert_eq_m128i(r, _mm_set_epi32(!0, 0, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtepi32_pd() {
+         let a = _mm_set_epi32(35, 25, 15, 5);
+         let r = _mm_cvtepi32_pd(a);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 15.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsi32_sd() {
+         let a = _mm_set1_pd(3.5);
+         let r = _mm_cvtsi32_sd(a, 5);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtepi32_ps() {
+         let a = _mm_setr_epi32(1, 2, 3, 4);
+         let r = _mm_cvtepi32_ps(a);
+         assert_eq_m128(r, _mm_setr_ps(1.0, 2.0, 3.0, 4.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtps_epi32() {
+         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let r = _mm_cvtps_epi32(a);
+         assert_eq_m128i(r, _mm_setr_epi32(1, 2, 3, 4));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsi32_si128() {
+         let r = _mm_cvtsi32_si128(5);
+         assert_eq_m128i(r, _mm_setr_epi32(5, 0, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsi128_si32() {
+         let r = _mm_cvtsi128_si32(_mm_setr_epi32(5, 0, 0, 0));
+         assert_eq!(r, 5);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_epi64x() {
+         let r = _mm_set_epi64x(0, 1);
+         assert_eq_m128i(r, _mm_setr_epi64x(1, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_epi32() {
+         let r = _mm_set_epi32(0, 1, 2, 3);
+         assert_eq_m128i(r, _mm_setr_epi32(3, 2, 1, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_epi16() {
+         let r = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m128i(r, _mm_setr_epi16(7, 6, 5, 4, 3, 2, 1, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_epi8() {
+         #[rustfmt::skip]
+         let r = _mm_set_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             15, 14, 13, 12, 11, 10, 9, 8,
+             7, 6, 5, 4, 3, 2, 1, 0,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set1_epi64x() {
+         let r = _mm_set1_epi64x(1);
+         assert_eq_m128i(r, _mm_set1_epi64x(1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set1_epi32() {
+         let r = _mm_set1_epi32(1);
+         assert_eq_m128i(r, _mm_set1_epi32(1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set1_epi16() {
+         let r = _mm_set1_epi16(1);
+         assert_eq_m128i(r, _mm_set1_epi16(1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set1_epi8() {
+         let r = _mm_set1_epi8(1);
+         assert_eq_m128i(r, _mm_set1_epi8(1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_setr_epi32() {
+         let r = _mm_setr_epi32(0, 1, 2, 3);
+         assert_eq_m128i(r, _mm_setr_epi32(0, 1, 2, 3));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_setr_epi16() {
+         let r = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m128i(r, _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_setr_epi8() {
+         #[rustfmt::skip]
+         let r = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_setzero_si128() {
+         let r = _mm_setzero_si128();
+         assert_eq_m128i(r, _mm_set1_epi64x(0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadl_epi64() {
+         let a = _mm_setr_epi64x(6, 5);
+         let r = _mm_loadl_epi64(&a as *const _);
+         assert_eq_m128i(r, _mm_setr_epi64x(6, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_load_si128() {
+         let a = _mm_set_epi64x(5, 6);
+         let r = _mm_load_si128(&a as *const _ as *const _);
+         assert_eq_m128i(a, r);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadu_si128() {
+         let a = _mm_set_epi64x(5, 6);
+         let r = _mm_loadu_si128(&a as *const _ as *const _);
+         assert_eq_m128i(a, r);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_maskmoveu_si128() {
+         let a = _mm_set1_epi8(9);
+         #[rustfmt::skip]
+         let mask = _mm_set_epi8(
+             0, 0, 0x80u8 as i8, 0, 0, 0, 0, 0,
+             0, 0, 0, 0, 0, 0, 0, 0,
+         );
+         let mut r = _mm_set1_epi8(0);
+         _mm_maskmoveu_si128(a, mask, &mut r as *mut _ as *mut i8);
+         let e = _mm_set_epi8(0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_store_si128() {
+         let a = _mm_set1_epi8(9);
+         let mut r = _mm_set1_epi8(0);
+         _mm_store_si128(&mut r as *mut _ as *mut __m128i, a);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_storeu_si128() {
+         let a = _mm_set1_epi8(9);
+         let mut r = _mm_set1_epi8(0);
+         _mm_storeu_si128(&mut r as *mut _ as *mut __m128i, a);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_storel_epi64() {
+         let a = _mm_setr_epi64x(2, 9);
+         let mut r = _mm_set1_epi8(0);
+         _mm_storel_epi64(&mut r as *mut _ as *mut __m128i, a);
+         assert_eq_m128i(r, _mm_setr_epi64x(2, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_stream_si128() {
+         let a = _mm_setr_epi32(1, 2, 3, 4);
+         let mut r = _mm_undefined_si128();
+         _mm_stream_si128(&mut r as *mut _, a);
+         assert_eq_m128i(r, a);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_stream_si32() {
+         let a: i32 = 7;
+         let mut mem = boxed::Box::<i32>::new(-1);
+         _mm_stream_si32(&mut *mem as *mut i32, a);
+         assert_eq!(a, *mem);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_move_epi64() {
+         let a = _mm_setr_epi64x(5, 6);
+         let r = _mm_move_epi64(a);
+         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_packs_epi16() {
+         let a = _mm_setr_epi16(0x80, -0x81, 0, 0, 0, 0, 0, 0);
+         let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -0x81, 0x80);
+         let r = _mm_packs_epi16(a, b);
+         #[rustfmt::skip]
+         assert_eq_m128i(
+             r,
+             _mm_setr_epi8(
+                 0x7F, -0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0x80, 0x7F
+             )
+         );
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_packs_epi32() {
+         let a = _mm_setr_epi32(0x8000, -0x8001, 0, 0);
+         let b = _mm_setr_epi32(0, 0, -0x8001, 0x8000);
+         let r = _mm_packs_epi32(a, b);
+         assert_eq_m128i(
+             r,
+             _mm_setr_epi16(0x7FFF, -0x8000, 0, 0, 0, 0, -0x8000, 0x7FFF),
+         );
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_packus_epi16() {
+         let a = _mm_setr_epi16(0x100, -1, 0, 0, 0, 0, 0, 0);
+         let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -1, 0x100);
+         let r = _mm_packus_epi16(a, b);
+         assert_eq_m128i(
+             r,
+             _mm_setr_epi8(!0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, !0),
+         );
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_extract_epi16() {
+         let a = _mm_setr_epi16(-1, 1, 2, 3, 4, 5, 6, 7);
+         let r1 = _mm_extract_epi16(a, 0);
+         let r2 = _mm_extract_epi16(a, 11);
+         assert_eq!(r1, 0xFFFF);
+         assert_eq!(r2, 3);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_insert_epi16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm_insert_epi16(a, 9, 0);
+         let e = _mm_setr_epi16(9, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_movemask_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0b1000_0000u8 as i8, 0b0, 0b1000_0000u8 as i8, 0b01,
+             0b0101, 0b1111_0000u8 as i8, 0, 0,
+             0, 0b1011_0101u8 as i8, 0b1111_0000u8 as i8, 0b0101,
+             0b01, 0b1000_0000u8 as i8, 0b0, 0b1000_0000u8 as i8,
+         );
+         let r = _mm_movemask_epi8(a);
+         assert_eq!(r, 0b10100110_00100101);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_shuffle_epi32() {
+         let a = _mm_setr_epi32(5, 10, 15, 20);
+         let r = _mm_shuffle_epi32(a, 0b00_01_01_11);
+         let e = _mm_setr_epi32(20, 10, 10, 5);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_shufflehi_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 10, 15, 20);
+         let r = _mm_shufflehi_epi16(a, 0b00_01_01_11);
+         let e = _mm_setr_epi16(1, 2, 3, 4, 20, 10, 10, 5);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_shufflelo_epi16() {
+         let a = _mm_setr_epi16(5, 10, 15, 20, 1, 2, 3, 4);
+         let r = _mm_shufflelo_epi16(a, 0b00_01_01_11);
+         let e = _mm_setr_epi16(20, 10, 10, 5, 1, 2, 3, 4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpackhi_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         let r = _mm_unpackhi_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpackhi_epi16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm_unpackhi_epi16(a, b);
+         let e = _mm_setr_epi16(4, 12, 5, 13, 6, 14, 7, 15);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpackhi_epi32() {
+         let a = _mm_setr_epi32(0, 1, 2, 3);
+         let b = _mm_setr_epi32(4, 5, 6, 7);
+         let r = _mm_unpackhi_epi32(a, b);
+         let e = _mm_setr_epi32(2, 6, 3, 7);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpackhi_epi64() {
+         let a = _mm_setr_epi64x(0, 1);
+         let b = _mm_setr_epi64x(2, 3);
+         let r = _mm_unpackhi_epi64(a, b);
+         let e = _mm_setr_epi64x(1, 3);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpacklo_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         let r = _mm_unpacklo_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             0, 16, 1, 17, 2, 18, 3, 19,
+             4, 20, 5, 21, 6, 22, 7, 23,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpacklo_epi16() {
+         let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm_setr_epi16(8, 9, 10, 11, 12, 13, 14, 15);
+         let r = _mm_unpacklo_epi16(a, b);
+         let e = _mm_setr_epi16(0, 8, 1, 9, 2, 10, 3, 11);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpacklo_epi32() {
+         let a = _mm_setr_epi32(0, 1, 2, 3);
+         let b = _mm_setr_epi32(4, 5, 6, 7);
+         let r = _mm_unpacklo_epi32(a, b);
+         let e = _mm_setr_epi32(0, 4, 1, 5);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpacklo_epi64() {
+         let a = _mm_setr_epi64x(0, 1);
+         let b = _mm_setr_epi64x(2, 3);
+         let r = _mm_unpacklo_epi64(a, b);
+         let e = _mm_setr_epi64x(0, 2);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_add_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(6.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_add_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_add_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(6.0, 12.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_div_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_div_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(0.2, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_div_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_div_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(0.2, 0.2));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_max_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_max_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_max_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_max_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 10.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_min_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_min_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_min_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_min_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mul_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_mul_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_mul_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_mul_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 20.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sqrt_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_sqrt_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(5.0f64.sqrt(), 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sqrt_pd() {
+         let r = _mm_sqrt_pd(_mm_setr_pd(1.0, 2.0));
+         assert_eq_m128d(r, _mm_setr_pd(1.0f64.sqrt(), 2.0f64.sqrt()));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sub_sd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_sub_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(-4.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_sub_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(5.0, 10.0);
+         let r = _mm_sub_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(-4.0, -8.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_and_pd() {
+         let a = transmute(u64x2::splat(5));
+         let b = transmute(u64x2::splat(3));
+         let r = _mm_and_pd(a, b);
+         let e = transmute(u64x2::splat(1));
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_andnot_pd() {
+         let a = transmute(u64x2::splat(5));
+         let b = transmute(u64x2::splat(3));
+         let r = _mm_andnot_pd(a, b);
+         let e = transmute(u64x2::splat(2));
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_or_pd() {
+         let a = transmute(u64x2::splat(5));
+         let b = transmute(u64x2::splat(3));
+         let r = _mm_or_pd(a, b);
+         let e = transmute(u64x2::splat(7));
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_xor_pd() {
+         let a = transmute(u64x2::splat(5));
+         let b = transmute(u64x2::splat(3));
+         let r = _mm_xor_pd(a, b);
+         let e = transmute(u64x2::splat(6));
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpeq_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpeq_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmplt_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmplt_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmple_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmple_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpgt_sd() {
+         let (a, b) = (_mm_setr_pd(5.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpgt_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpge_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpge_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpord_sd() {
+         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpord_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpunord_sd() {
+         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpunord_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpneq_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(!0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpneq_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpnlt_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpnlt_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpnle_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpnle_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpngt_sd() {
+         let (a, b) = (_mm_setr_pd(5.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpngt_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpnge_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, transmute(2.0f64));
+         let r = transmute::<_, __m128i>(_mm_cmpnge_sd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpeq_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, 0);
+         let r = transmute::<_, __m128i>(_mm_cmpeq_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmplt_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, !0);
+         let r = transmute::<_, __m128i>(_mm_cmplt_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmple_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, !0);
+         let r = transmute::<_, __m128i>(_mm_cmple_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpgt_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, 0);
+         let r = transmute::<_, __m128i>(_mm_cmpgt_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpge_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(!0, 0);
+         let r = transmute::<_, __m128i>(_mm_cmpge_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpord_pd() {
+         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(0, !0);
+         let r = transmute::<_, __m128i>(_mm_cmpord_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpunord_pd() {
+         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(!0, 0);
+         let r = transmute::<_, __m128i>(_mm_cmpunord_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpneq_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(!0, !0);
+         let r = transmute::<_, __m128i>(_mm_cmpneq_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpnlt_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(5.0, 3.0));
+         let e = _mm_setr_epi64x(0, 0);
+         let r = transmute::<_, __m128i>(_mm_cmpnlt_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpnle_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, 0);
+         let r = transmute::<_, __m128i>(_mm_cmpnle_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpngt_pd() {
+         let (a, b) = (_mm_setr_pd(5.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, !0);
+         let r = transmute::<_, __m128i>(_mm_cmpngt_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cmpnge_pd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         let e = _mm_setr_epi64x(0, !0);
+         let r = transmute::<_, __m128i>(_mm_cmpnge_pd(a, b));
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_comieq_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comieq_sd(a, b) != 0);
+ 
+         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comieq_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_comilt_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comilt_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_comile_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comile_sd(a, b) != 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_comigt_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comigt_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_comige_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comige_sd(a, b) != 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_comineq_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_comineq_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_ucomieq_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_ucomieq_sd(a, b) != 0);
+ 
+         let (a, b) = (_mm_setr_pd(NAN, 2.0), _mm_setr_pd(NAN, 3.0));
+         assert!(_mm_ucomieq_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_ucomilt_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_ucomilt_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_ucomile_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_ucomile_sd(a, b) != 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_ucomigt_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_ucomigt_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_ucomige_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_ucomige_sd(a, b) != 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_ucomineq_sd() {
+         let (a, b) = (_mm_setr_pd(1.0, 2.0), _mm_setr_pd(1.0, 3.0));
+         assert!(_mm_ucomineq_sd(a, b) == 0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_movemask_pd() {
+         let r = _mm_movemask_pd(_mm_setr_pd(-1.0, 5.0));
+         assert_eq!(r, 0b01);
+ 
+         let r = _mm_movemask_pd(_mm_setr_pd(-1.0, -5.0));
+         assert_eq!(r, 0b11);
+     }
+ 
+     #[repr(align(16))]
+     struct Memory {
+         data: [f64; 4],
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_load_pd() {
+         let mem = Memory {
+             data: [1.0f64, 2.0, 3.0, 4.0],
+         };
+         let vals = &mem.data;
+         let d = vals.as_ptr();
+ 
+         let r = _mm_load_pd(d);
+         assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_load_sd() {
+         let a = 1.;
+         let expected = _mm_setr_pd(a, 0.);
+         let r = _mm_load_sd(&a);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadh_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = 3.;
+         let expected = _mm_setr_pd(_mm_cvtsd_f64(a), 3.);
+         let r = _mm_loadh_pd(a, &b);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadl_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = 3.;
+         let expected = _mm_setr_pd(3., get_m128d(a, 1));
+         let r = _mm_loadl_pd(a, &b);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_stream_pd() {
+         #[repr(align(128))]
+         struct Memory {
+             pub data: [f64; 2],
+         }
+         let a = _mm_set1_pd(7.0);
+         let mut mem = Memory { data: [-1.0; 2] };
+ 
+         _mm_stream_pd(&mut mem.data[0] as *mut f64, a);
+         for i in 0..2 {
+             assert_eq!(mem.data[i], get_m128d(a, i));
+         }
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_store_sd() {
+         let mut dest = 0.;
+         let a = _mm_setr_pd(1., 2.);
+         _mm_store_sd(&mut dest, a);
+         assert_eq!(dest, _mm_cvtsd_f64(a));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_store_pd() {
+         let mut mem = Memory { data: [0.0f64; 4] };
+         let vals = &mut mem.data;
+         let a = _mm_setr_pd(1.0, 2.0);
+         let d = vals.as_mut_ptr();
+ 
+         _mm_store_pd(d, *black_box(&a));
+         assert_eq!(vals[0], 1.0);
+         assert_eq!(vals[1], 2.0);
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_storeu_pd() {
+         let mut mem = Memory { data: [0.0f64; 4] };
+         let vals = &mut mem.data;
+         let a = _mm_setr_pd(1.0, 2.0);
+ 
+         let mut ofs = 0;
+         let mut p = vals.as_mut_ptr();
+ 
+         // Make sure p is **not** aligned to 16-byte boundary
+         if (p as usize) & 0xf == 0 {
+             ofs = 1;
+             p = p.offset(1);
+         }
+ 
+         _mm_storeu_pd(p, *black_box(&a));
+ 
+         if ofs > 0 {
+             assert_eq!(vals[ofs - 1], 0.0);
+         }
+         assert_eq!(vals[ofs + 0], 1.0);
+         assert_eq!(vals[ofs + 1], 2.0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_store1_pd() {
+         let mut mem = Memory { data: [0.0f64; 4] };
+         let vals = &mut mem.data;
+         let a = _mm_setr_pd(1.0, 2.0);
+         let d = vals.as_mut_ptr();
+ 
+         _mm_store1_pd(d, *black_box(&a));
+         assert_eq!(vals[0], 1.0);
+         assert_eq!(vals[1], 1.0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_store_pd1() {
+         let mut mem = Memory { data: [0.0f64; 4] };
+         let vals = &mut mem.data;
+         let a = _mm_setr_pd(1.0, 2.0);
+         let d = vals.as_mut_ptr();
+ 
+         _mm_store_pd1(d, *black_box(&a));
+         assert_eq!(vals[0], 1.0);
+         assert_eq!(vals[1], 1.0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_storer_pd() {
+         let mut mem = Memory { data: [0.0f64; 4] };
+         let vals = &mut mem.data;
+         let a = _mm_setr_pd(1.0, 2.0);
+         let d = vals.as_mut_ptr();
+ 
+         _mm_storer_pd(d, *black_box(&a));
+         assert_eq!(vals[0], 2.0);
+         assert_eq!(vals[1], 1.0);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_storeh_pd() {
+         let mut dest = 0.;
+         let a = _mm_setr_pd(1., 2.);
+         _mm_storeh_pd(&mut dest, a);
+         assert_eq!(dest, get_m128d(a, 1));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_storel_pd() {
+         let mut dest = 0.;
+         let a = _mm_setr_pd(1., 2.);
+         _mm_storel_pd(&mut dest, a);
+         assert_eq!(dest, _mm_cvtsd_f64(a));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadr_pd() {
+         let mut mem = Memory {
+             data: [1.0f64, 2.0, 3.0, 4.0],
+         };
+         let vals = &mut mem.data;
+         let d = vals.as_ptr();
+ 
+         let r = _mm_loadr_pd(d);
+         assert_eq_m128d(r, _mm_setr_pd(2.0, 1.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_loadu_pd() {
+         let mut mem = Memory {
+             data: [1.0f64, 2.0, 3.0, 4.0],
+         };
+         let vals = &mut mem.data;
+         let mut d = vals.as_ptr();
+ 
+         // make sure d is not aligned to 16-byte boundary
+         let mut offset = 0;
+         if (d as usize) & 0xf == 0 {
+             offset = 1;
+             d = d.offset(offset as isize);
+         }
+ 
+         let r = _mm_loadu_pd(d);
+         let e = _mm_add_pd(_mm_setr_pd(1.0, 2.0), _mm_set1_pd(offset as f64));
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtpd_ps() {
+         let r = _mm_cvtpd_ps(_mm_setr_pd(-1.0, 5.0));
+         assert_eq_m128(r, _mm_setr_ps(-1.0, 5.0, 0.0, 0.0));
+ 
+         let r = _mm_cvtpd_ps(_mm_setr_pd(-1.0, -5.0));
+         assert_eq_m128(r, _mm_setr_ps(-1.0, -5.0, 0.0, 0.0));
+ 
+         let r = _mm_cvtpd_ps(_mm_setr_pd(f64::MAX, f64::MIN));
+         assert_eq_m128(r, _mm_setr_ps(f32::INFINITY, f32::NEG_INFINITY, 0.0, 0.0));
+ 
+         let r = _mm_cvtpd_ps(_mm_setr_pd(f32::MAX as f64, f32::MIN as f64));
+         assert_eq_m128(r, _mm_setr_ps(f32::MAX, f32::MIN, 0.0, 0.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtps_pd() {
+         let r = _mm_cvtps_pd(_mm_setr_ps(-1.0, 2.0, -3.0, 5.0));
+         assert_eq_m128d(r, _mm_setr_pd(-1.0, 2.0));
+ 
+         let r = _mm_cvtps_pd(_mm_setr_ps(
+             f32::MAX,
+             f32::INFINITY,
+             f32::NEG_INFINITY,
+             f32::MIN,
+         ));
+         assert_eq_m128d(r, _mm_setr_pd(f32::MAX as f64, f64::INFINITY));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtpd_epi32() {
+         let r = _mm_cvtpd_epi32(_mm_setr_pd(-1.0, 5.0));
+         assert_eq_m128i(r, _mm_setr_epi32(-1, 5, 0, 0));
+ 
+         let r = _mm_cvtpd_epi32(_mm_setr_pd(-1.0, -5.0));
+         assert_eq_m128i(r, _mm_setr_epi32(-1, -5, 0, 0));
+ 
+         let r = _mm_cvtpd_epi32(_mm_setr_pd(f64::MAX, f64::MIN));
+         assert_eq_m128i(r, _mm_setr_epi32(i32::MIN, i32::MIN, 0, 0));
+ 
+         let r = _mm_cvtpd_epi32(_mm_setr_pd(f64::INFINITY, f64::NEG_INFINITY));
+         assert_eq_m128i(r, _mm_setr_epi32(i32::MIN, i32::MIN, 0, 0));
+ 
+         let r = _mm_cvtpd_epi32(_mm_setr_pd(f64::NAN, f64::NAN));
+         assert_eq_m128i(r, _mm_setr_epi32(i32::MIN, i32::MIN, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsd_si32() {
+         let r = _mm_cvtsd_si32(_mm_setr_pd(-2.0, 5.0));
+         assert_eq!(r, -2);
+ 
+         let r = _mm_cvtsd_si32(_mm_setr_pd(f64::MAX, f64::MIN));
+         assert_eq!(r, i32::MIN);
+ 
+         let r = _mm_cvtsd_si32(_mm_setr_pd(f64::NAN, f64::NAN));
+         assert_eq!(r, i32::MIN);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsd_ss() {
+         let a = _mm_setr_ps(-1.1, -2.2, 3.3, 4.4);
+         let b = _mm_setr_pd(2.0, -5.0);
+ 
+         let r = _mm_cvtsd_ss(a, b);
+ 
+         assert_eq_m128(r, _mm_setr_ps(2.0, -2.2, 3.3, 4.4));
+ 
+         let a = _mm_setr_ps(-1.1, f32::NEG_INFINITY, f32::MAX, f32::NEG_INFINITY);
+         let b = _mm_setr_pd(f64::INFINITY, -5.0);
+ 
+         let r = _mm_cvtsd_ss(a, b);
+ 
+         assert_eq_m128(
+             r,
+             _mm_setr_ps(
+                 f32::INFINITY,
+                 f32::NEG_INFINITY,
+                 f32::MAX,
+                 f32::NEG_INFINITY,
+             ),
+         );
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsd_f64() {
+         let r = _mm_cvtsd_f64(_mm_setr_pd(-1.1, 2.2));
+         assert_eq!(r, -1.1);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtss_sd() {
+         let a = _mm_setr_pd(-1.1, 2.2);
+         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+ 
+         let r = _mm_cvtss_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(1.0, 2.2));
+ 
+         let a = _mm_setr_pd(-1.1, f64::INFINITY);
+         let b = _mm_setr_ps(f32::NEG_INFINITY, 2.0, 3.0, 4.0);
+ 
+         let r = _mm_cvtss_sd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(f64::NEG_INFINITY, f64::INFINITY));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvttpd_epi32() {
+         let a = _mm_setr_pd(-1.1, 2.2);
+         let r = _mm_cvttpd_epi32(a);
+         assert_eq_m128i(r, _mm_setr_epi32(-1, 2, 0, 0));
+ 
+         let a = _mm_setr_pd(f64::NEG_INFINITY, f64::NAN);
+         let r = _mm_cvttpd_epi32(a);
+         assert_eq_m128i(r, _mm_setr_epi32(i32::MIN, i32::MIN, 0, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvttsd_si32() {
+         let a = _mm_setr_pd(-1.1, 2.2);
+         let r = _mm_cvttsd_si32(a);
+         assert_eq!(r, -1);
+ 
+         let a = _mm_setr_pd(f64::NEG_INFINITY, f64::NAN);
+         let r = _mm_cvttsd_si32(a);
+         assert_eq!(r, i32::MIN);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvttps_epi32() {
+         let a = _mm_setr_ps(-1.1, 2.2, -3.3, 6.6);
+         let r = _mm_cvttps_epi32(a);
+         assert_eq_m128i(r, _mm_setr_epi32(-1, 2, -3, 6));
+ 
+         let a = _mm_setr_ps(f32::NEG_INFINITY, f32::INFINITY, f32::MIN, f32::MAX);
+         let r = _mm_cvttps_epi32(a);
+         assert_eq_m128i(r, _mm_setr_epi32(i32::MIN, i32::MIN, i32::MIN, i32::MIN));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_sd() {
+         let r = _mm_set_sd(-1.0_f64);
+         assert_eq_m128d(r, _mm_setr_pd(-1.0_f64, 0_f64));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set1_pd() {
+         let r = _mm_set1_pd(-1.0_f64);
+         assert_eq_m128d(r, _mm_setr_pd(-1.0_f64, -1.0_f64));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_pd1() {
+         let r = _mm_set_pd1(-2.0_f64);
+         assert_eq_m128d(r, _mm_setr_pd(-2.0_f64, -2.0_f64));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_set_pd() {
+         let r = _mm_set_pd(1.0_f64, 5.0_f64);
+         assert_eq_m128d(r, _mm_setr_pd(5.0_f64, 1.0_f64));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_setr_pd() {
+         let r = _mm_setr_pd(1.0_f64, -5.0_f64);
+         assert_eq_m128d(r, _mm_setr_pd(1.0_f64, -5.0_f64));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_setzero_pd() {
+         let r = _mm_setzero_pd();
+         assert_eq_m128d(r, _mm_setr_pd(0_f64, 0_f64));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_load1_pd() {
+         let d = -5.0;
+         let r = _mm_load1_pd(&d);
+         assert_eq_m128d(r, _mm_setr_pd(d, d));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_load_pd1() {
+         let d = -5.0;
+         let r = _mm_load_pd1(&d);
+         assert_eq_m128d(r, _mm_setr_pd(d, d));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpackhi_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(3.0, 4.0);
+         let r = _mm_unpackhi_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(2.0, 4.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_unpacklo_pd() {
+         let a = _mm_setr_pd(1.0, 2.0);
+         let b = _mm_setr_pd(3.0, 4.0);
+         let r = _mm_unpacklo_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(1.0, 3.0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_shuffle_pd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(3., 4.);
+         let expected = _mm_setr_pd(1., 3.);
+         let r = _mm_shuffle_pd(a, b, 0);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_move_sd() {
+         let a = _mm_setr_pd(1., 2.);
+         let b = _mm_setr_pd(3., 4.);
+         let expected = _mm_setr_pd(3., 2.);
+         let r = _mm_move_sd(a, b);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_castpd_ps() {
+         let a = _mm_set1_pd(0.);
+         let expected = _mm_set1_ps(0.);
+         let r = _mm_castpd_ps(a);
+         assert_eq_m128(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_castpd_si128() {
+         let a = _mm_set1_pd(0.);
+         let expected = _mm_set1_epi64x(0);
+         let r = _mm_castpd_si128(a);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_castps_pd() {
+         let a = _mm_set1_ps(0.);
+         let expected = _mm_set1_pd(0.);
+         let r = _mm_castps_pd(a);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_castps_si128() {
+         let a = _mm_set1_ps(0.);
+         let expected = _mm_set1_epi32(0);
+         let r = _mm_castps_si128(a);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_castsi128_pd() {
+         let a = _mm_set1_epi64x(0);
+         let expected = _mm_set1_pd(0.);
+         let r = _mm_castsi128_pd(a);
+         assert_eq_m128d(r, expected);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_castsi128_ps() {
+         let a = _mm_set1_epi32(0);
+         let expected = _mm_set1_ps(0.);
+         let r = _mm_castsi128_ps(a);
+         assert_eq_m128(r, expected);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse3.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse3.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse3.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse3.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,260 ----
+ //! Streaming SIMD Extensions 3 (SSE3)
+ 
+ use crate::{
+     core_arch::{
+         simd::*,
+         simd_llvm::{simd_shuffle2, simd_shuffle4},
+         x86::*,
+     },
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Alternatively add and subtract packed single-precision (32-bit)
+ /// floating-point elements in `a` to/from packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_addsub_ps)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(addsubps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_addsub_ps(a: __m128, b: __m128) -> __m128 {
+     addsubps(a, b)
+ }
+ 
+ /// Alternatively add and subtract packed double-precision (64-bit)
+ /// floating-point elements in `a` to/from packed elements in `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_addsub_pd)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(addsubpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_addsub_pd(a: __m128d, b: __m128d) -> __m128d {
+     addsubpd(a, b)
+ }
+ 
+ /// Horizontally adds adjacent pairs of double-precision (64-bit)
+ /// floating-point elements in `a` and `b`, and pack the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hadd_pd)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(haddpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hadd_pd(a: __m128d, b: __m128d) -> __m128d {
+     haddpd(a, b)
+ }
+ 
+ /// Horizontally adds adjacent pairs of single-precision (32-bit)
+ /// floating-point elements in `a` and `b`, and pack the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hadd_ps)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(haddps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hadd_ps(a: __m128, b: __m128) -> __m128 {
+     haddps(a, b)
+ }
+ 
+ /// Horizontally subtract adjacent pairs of double-precision (64-bit)
+ /// floating-point elements in `a` and `b`, and pack the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hsub_pd)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(hsubpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hsub_pd(a: __m128d, b: __m128d) -> __m128d {
+     hsubpd(a, b)
+ }
+ 
+ /// Horizontally adds adjacent pairs of single-precision (32-bit)
+ /// floating-point elements in `a` and `b`, and pack the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hsub_ps)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(hsubps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hsub_ps(a: __m128, b: __m128) -> __m128 {
+     hsubps(a, b)
+ }
+ 
+ /// Loads 128-bits of integer data from unaligned memory.
+ /// This intrinsic may perform better than `_mm_loadu_si128`
+ /// when the data crosses a cache line boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_lddqu_si128)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(lddqu))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_lddqu_si128(mem_addr: *const __m128i) -> __m128i {
+     transmute(lddqu(mem_addr as *const _))
+ }
+ 
+ /// Duplicate the low double-precision (64-bit) floating-point element
+ /// from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movedup_pd)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(movddup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movedup_pd(a: __m128d) -> __m128d {
+     simd_shuffle2(a, a, [0, 0])
+ }
+ 
+ /// Loads a double-precision (64-bit) floating-point element from memory
+ /// into both elements of return vector.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loaddup_pd)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(movddup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_loaddup_pd(mem_addr: *const f64) -> __m128d {
+     _mm_load1_pd(mem_addr)
+ }
+ 
+ /// Duplicate odd-indexed single-precision (32-bit) floating-point elements
+ /// from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movehdup_ps)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(movshdup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_movehdup_ps(a: __m128) -> __m128 {
+     simd_shuffle4(a, a, [1, 1, 3, 3])
+ }
+ 
+ /// Duplicate even-indexed single-precision (32-bit) floating-point elements
+ /// from `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_moveldup_ps)
+ #[inline]
+ #[target_feature(enable = "sse3")]
+ #[cfg_attr(test, assert_instr(movsldup))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_moveldup_ps(a: __m128) -> __m128 {
+     simd_shuffle4(a, a, [0, 0, 2, 2])
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse3.addsub.ps"]
+     fn addsubps(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse3.addsub.pd"]
+     fn addsubpd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse3.hadd.pd"]
+     fn haddpd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse3.hadd.ps"]
+     fn haddps(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse3.hsub.pd"]
+     fn hsubpd(a: __m128d, b: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse3.hsub.ps"]
+     fn hsubps(a: __m128, b: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse3.ldu.dq"]
+     fn lddqu(mem_addr: *const i8) -> i8x16;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_addsub_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_addsub_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(99.0, 25.0, 0.0, -15.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_addsub_pd() {
+         let a = _mm_setr_pd(-1.0, 5.0);
+         let b = _mm_setr_pd(-100.0, 20.0);
+         let r = _mm_addsub_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(99.0, 25.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_hadd_pd() {
+         let a = _mm_setr_pd(-1.0, 5.0);
+         let b = _mm_setr_pd(-100.0, 20.0);
+         let r = _mm_hadd_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(4.0, -80.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_hadd_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_hadd_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(4.0, -10.0, -80.0, -5.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_hsub_pd() {
+         let a = _mm_setr_pd(-1.0, 5.0);
+         let b = _mm_setr_pd(-100.0, 20.0);
+         let r = _mm_hsub_pd(a, b);
+         assert_eq_m128d(r, _mm_setr_pd(-6.0, -120.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_hsub_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
+         let r = _mm_hsub_ps(a, b);
+         assert_eq_m128(r, _mm_setr_ps(-6.0, 10.0, -120.0, 5.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_lddqu_si128() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4,
+             5, 6, 7, 8,
+             9, 10, 11, 12,
+             13, 14, 15, 16,
+         );
+         let r = _mm_lddqu_si128(&a);
+         assert_eq_m128i(a, r);
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_movedup_pd() {
+         let a = _mm_setr_pd(-1.0, 5.0);
+         let r = _mm_movedup_pd(a);
+         assert_eq_m128d(r, _mm_setr_pd(-1.0, -1.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_movehdup_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let r = _mm_movehdup_ps(a);
+         assert_eq_m128(r, _mm_setr_ps(5.0, 5.0, -10.0, -10.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_moveldup_ps() {
+         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
+         let r = _mm_moveldup_ps(a);
+         assert_eq_m128(r, _mm_setr_ps(-1.0, -1.0, 0.0, 0.0));
+     }
+ 
+     #[simd_test(enable = "sse3")]
+     unsafe fn test_mm_loaddup_pd() {
+         let d = -5.0;
+         let r = _mm_loaddup_pd(&d);
+         assert_eq_m128d(r, _mm_setr_pd(d, d));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse41.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse41.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse41.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse41.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,1936 ----
+ //! Streaming SIMD Extensions 4.1 (SSE4.1)
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ // SSE4 rounding constans
+ /// round to nearest
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_TO_NEAREST_INT: i32 = 0x00;
+ /// round down
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_TO_NEG_INF: i32 = 0x01;
+ /// round up
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_TO_POS_INF: i32 = 0x02;
+ /// truncate
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_TO_ZERO: i32 = 0x03;
+ /// use MXCSR.RC; see `vendor::_MM_SET_ROUNDING_MODE`
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_CUR_DIRECTION: i32 = 0x04;
+ /// do not suppress exceptions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_RAISE_EXC: i32 = 0x00;
+ /// suppress exceptions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_NO_EXC: i32 = 0x08;
+ /// round to nearest and do not suppress exceptions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_NINT: i32 = 0x00;
+ /// round down and do not suppress exceptions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_FLOOR: i32 = _MM_FROUND_RAISE_EXC | _MM_FROUND_TO_NEG_INF;
+ /// round up and do not suppress exceptions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_CEIL: i32 = _MM_FROUND_RAISE_EXC | _MM_FROUND_TO_POS_INF;
+ /// truncate and do not suppress exceptions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_TRUNC: i32 = _MM_FROUND_RAISE_EXC | _MM_FROUND_TO_ZERO;
+ /// use MXCSR.RC and do not suppress exceptions; see
+ /// `vendor::_MM_SET_ROUNDING_MODE`
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_RINT: i32 = _MM_FROUND_RAISE_EXC | _MM_FROUND_CUR_DIRECTION;
+ /// use MXCSR.RC and suppress exceptions; see `vendor::_MM_SET_ROUNDING_MODE`
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _MM_FROUND_NEARBYINT: i32 = _MM_FROUND_NO_EXC | _MM_FROUND_CUR_DIRECTION;
+ 
+ /// Blend packed 8-bit integers from `a` and `b` using `mask`
+ ///
+ /// The high bit of each corresponding mask byte determines the selection.
+ /// If the high bit is set the element of `a` is selected. The element
+ /// of `b` is selected otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blendv_epi8)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pblendvb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blendv_epi8(a: __m128i, b: __m128i, mask: __m128i) -> __m128i {
+     transmute(pblendvb(a.as_i8x16(), b.as_i8x16(), mask.as_i8x16()))
+ }
+ 
+ /// Blend packed 16-bit integers from `a` and `b` using the mask `imm8`.
+ ///
+ /// The mask bits determine the selection. A clear bit selects the
+ /// corresponding element of `a`, and a set bit the corresponding
+ /// element of `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blend_epi16)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ // Note: LLVM7 prefers the single-precision floating-point domain when possible
+ // see https://bugs.llvm.org/show_bug.cgi?id=38195
+ // #[cfg_attr(test, assert_instr(pblendw, imm8 = 0xF0))]
+ #[cfg_attr(test, assert_instr(blendps, imm8 = 0xF0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blend_epi16(a: __m128i, b: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i16x8();
+     let b = b.as_i16x8();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pblendw(a, b, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8, call))
+ }
+ 
+ /// Blend packed double-precision (64-bit) floating-point elements from `a`
+ /// and `b` using `mask`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blendv_pd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(blendvpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blendv_pd(a: __m128d, b: __m128d, mask: __m128d) -> __m128d {
+     blendvpd(a, b, mask)
+ }
+ 
+ /// Blend packed single-precision (32-bit) floating-point elements from `a`
+ /// and `b` using `mask`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blendv_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(blendvps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blendv_ps(a: __m128, b: __m128, mask: __m128) -> __m128 {
+     blendvps(a, b, mask)
+ }
+ 
+ /// Blend packed double-precision (64-bit) floating-point elements from `a`
+ /// and `b` using control mask `imm2`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blend_pd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ // Note: LLVM7 prefers the single-precision floating-point domain when possible
+ // see https://bugs.llvm.org/show_bug.cgi?id=38195
+ // #[cfg_attr(test, assert_instr(blendpd, imm2 = 0b10))]
+ #[cfg_attr(test, assert_instr(blendps, imm2 = 0b10))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blend_pd(a: __m128d, b: __m128d, imm2: i32) -> __m128d {
+     macro_rules! call {
+         ($imm2:expr) => {
+             blendpd(a, b, $imm2)
+         };
+     }
+     constify_imm2!(imm2, call)
+ }
+ 
+ /// Blend packed single-precision (32-bit) floating-point elements from `a`
+ /// and `b` using mask `imm4`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_blend_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(blendps, imm4 = 0b0101))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_blend_ps(a: __m128, b: __m128, imm4: i32) -> __m128 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             blendps(a, b, $imm4)
+         };
+     }
+     constify_imm4!(imm4, call)
+ }
+ 
+ /// Extracts a single-precision (32-bit) floating-point element from `a`,
+ /// selected with `imm8`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(extractps, imm8 = 0)
+ )]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_extract_ps(a: __m128, imm8: i32) -> i32 {
+     macro_rules! call {
+         ($imm2:expr) => {
+             transmute(simd_extract::<_, f32>(a, $imm2))
+         };
+     }
+     constify_imm2!(imm8, call)
+ }
+ 
+ /// Extracts an 8-bit integer from `a`, selected with `imm8`. Returns a 32-bit
+ /// integer containing the zero-extended integer data.
+ ///
+ /// See [LLVM commit D20468][https://reviews.llvm.org/D20468].
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_epi8)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pextrb, imm8 = 0))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_extract_epi8(a: __m128i, imm8: i32) -> i32 {
+     let a = a.as_u8x16();
+     macro_rules! call {
+         ($imm4:expr) => {
+             simd_extract::<_, u8>(a, $imm4) as i32
+         };
+     }
+     constify_imm4!(imm8, call)
+ }
+ 
+ /// Extracts an 32-bit integer from `a` selected with `imm8`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(
+     all(test, not(target_os = "windows")),
+     assert_instr(extractps, imm8 = 1)
+ )]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_extract_epi32(a: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i32x4();
+     macro_rules! call {
+         ($imm2:expr) => {
+             simd_extract::<_, i32>(a, $imm2)
+         };
+     }
+     constify_imm2!(imm8, call)
+ }
+ 
+ /// Select a single value in `a` to store at some position in `b`,
+ /// Then zero elements according to `imm8`.
+ ///
+ /// `imm8` specifies which bits from operand `a` will be copied, which bits in
+ /// the result they will be copied to, and which bits in the result will be
+ /// cleared. The following assignments are made:
+ ///
+ /// * Bits `[7:6]` specify the bits to copy from operand `a`:
+ ///     - `00`: Selects bits `[31:0]` from operand `a`.
+ ///     - `01`: Selects bits `[63:32]` from operand `a`.
+ ///     - `10`: Selects bits `[95:64]` from operand `a`.
+ ///     - `11`: Selects bits `[127:96]` from operand `a`.
+ ///
+ /// * Bits `[5:4]` specify the bits in the result to which the selected bits
+ /// from operand `a` are copied:
+ ///     - `00`: Copies the selected bits from `a` to result bits `[31:0]`.
+ ///     - `01`: Copies the selected bits from `a` to result bits `[63:32]`.
+ ///     - `10`: Copies the selected bits from `a` to result bits `[95:64]`.
+ ///     - `11`: Copies the selected bits from `a` to result bits `[127:96]`.
+ ///
+ /// * Bits `[3:0]`: If any of these bits are set, the corresponding result
+ /// element is cleared.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(insertps, imm8 = 0b1010))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_insert_ps(a: __m128, b: __m128, imm8: i32) -> __m128 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             insertps(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Returns a copy of `a` with the 8-bit integer from `i` inserted at a
+ /// location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_epi8)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pinsrb, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_insert_epi8(a: __m128i, i: i32, imm8: i32) -> __m128i {
+     let a = a.as_i8x16();
+     macro_rules! call {
+         ($imm4:expr) => {
+             transmute(simd_insert(a, $imm4, i as i8))
+         };
+     }
+     constify_imm4!(imm8, call)
+ }
+ 
+ /// Returns a copy of `a` with the 32-bit integer from `i` inserted at a
+ /// location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pinsrd, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_insert_epi32(a: __m128i, i: i32, imm8: i32) -> __m128i {
+     let a = a.as_i32x4();
+     macro_rules! call {
+         ($imm2:expr) => {
+             transmute(simd_insert(a, $imm2, i))
+         };
+     }
+     constify_imm2!(imm8, call)
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` and returns packed maximum
+ /// values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epi8)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmaxsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaxsb(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns packed
+ /// maximum.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epu16)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmaxuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_epu16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaxuw(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b`, and returns packed maximum
+ /// values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmaxsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaxsd(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns packed
+ /// maximum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epu32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmaxud))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_max_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaxud(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Compares packed 8-bit integers in `a` and `b` and returns packed minimum
+ /// values in dst.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epi8)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pminsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pminsb(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Compares packed unsigned 16-bit integers in `a` and `b`, and returns packed
+ /// minimum.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epu16)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pminuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_epu16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pminuw(a.as_u16x8(), b.as_u16x8()))
+ }
+ 
+ /// Compares packed 32-bit integers in `a` and `b`, and returns packed minimum
+ /// values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pminsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pminsd(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares packed unsigned 32-bit integers in `a` and `b`, and returns packed
+ /// minimum values.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epu32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pminud))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pminud(a.as_u32x4(), b.as_u32x4()))
+ }
+ 
+ /// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers
+ /// using unsigned saturation
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packus_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(packusdw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(packusdw(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Compares packed 64-bit integers in `a` and `b` for equality
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pcmpeqq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpeq_epi64(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_eq::<_, i64x2>(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ /// Sign extend packed 8-bit integers in `a` to packed 16-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi8_epi16)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovsxbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi8_epi16(a: __m128i) -> __m128i {
+     let a = a.as_i8x16();
+     let a = simd_shuffle8::<_, i8x8>(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
+     transmute(simd_cast::<_, i16x8>(a))
+ }
+ 
+ /// Sign extend packed 8-bit integers in `a` to packed 32-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi8_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovsxbd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi8_epi32(a: __m128i) -> __m128i {
+     let a = a.as_i8x16();
+     let a = simd_shuffle4::<_, i8x4>(a, a, [0, 1, 2, 3]);
+     transmute(simd_cast::<_, i32x4>(a))
+ }
+ 
+ /// Sign extend packed 8-bit integers in the low 8 bytes of `a` to packed
+ /// 64-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi8_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovsxbq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi8_epi64(a: __m128i) -> __m128i {
+     let a = a.as_i8x16();
+     let a = simd_shuffle2::<_, i8x2>(a, a, [0, 1]);
+     transmute(simd_cast::<_, i64x2>(a))
+ }
+ 
+ /// Sign extend packed 16-bit integers in `a` to packed 32-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi16_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovsxwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi16_epi32(a: __m128i) -> __m128i {
+     let a = a.as_i16x8();
+     let a = simd_shuffle4::<_, i16x4>(a, a, [0, 1, 2, 3]);
+     transmute(simd_cast::<_, i32x4>(a))
+ }
+ 
+ /// Sign extend packed 16-bit integers in `a` to packed 64-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi16_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovsxwq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi16_epi64(a: __m128i) -> __m128i {
+     let a = a.as_i16x8();
+     let a = simd_shuffle2::<_, i16x2>(a, a, [0, 1]);
+     transmute(simd_cast::<_, i64x2>(a))
+ }
+ 
+ /// Sign extend packed 32-bit integers in `a` to packed 64-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi32_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovsxdq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepi32_epi64(a: __m128i) -> __m128i {
+     let a = a.as_i32x4();
+     let a = simd_shuffle2::<_, i32x2>(a, a, [0, 1]);
+     transmute(simd_cast::<_, i64x2>(a))
+ }
+ 
+ /// Zeroes extend packed unsigned 8-bit integers in `a` to packed 16-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu8_epi16)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovzxbw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepu8_epi16(a: __m128i) -> __m128i {
+     let a = a.as_u8x16();
+     let a = simd_shuffle8::<_, u8x8>(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);
+     transmute(simd_cast::<_, i16x8>(a))
+ }
+ 
+ /// Zeroes extend packed unsigned 8-bit integers in `a` to packed 32-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu8_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovzxbd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepu8_epi32(a: __m128i) -> __m128i {
+     let a = a.as_u8x16();
+     let a = simd_shuffle4::<_, u8x4>(a, a, [0, 1, 2, 3]);
+     transmute(simd_cast::<_, i32x4>(a))
+ }
+ 
+ /// Zeroes extend packed unsigned 8-bit integers in `a` to packed 64-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu8_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovzxbq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepu8_epi64(a: __m128i) -> __m128i {
+     let a = a.as_u8x16();
+     let a = simd_shuffle2::<_, u8x2>(a, a, [0, 1]);
+     transmute(simd_cast::<_, i64x2>(a))
+ }
+ 
+ /// Zeroes extend packed unsigned 16-bit integers in `a`
+ /// to packed 32-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu16_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovzxwd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepu16_epi32(a: __m128i) -> __m128i {
+     let a = a.as_u16x8();
+     let a = simd_shuffle4::<_, u16x4>(a, a, [0, 1, 2, 3]);
+     transmute(simd_cast::<_, i32x4>(a))
+ }
+ 
+ /// Zeroes extend packed unsigned 16-bit integers in `a`
+ /// to packed 64-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu16_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovzxwq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepu16_epi64(a: __m128i) -> __m128i {
+     let a = a.as_u16x8();
+     let a = simd_shuffle2::<_, u16x2>(a, a, [0, 1]);
+     transmute(simd_cast::<_, i64x2>(a))
+ }
+ 
+ /// Zeroes extend packed unsigned 32-bit integers in `a`
+ /// to packed 64-bit integers
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepu32_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmovzxdq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtepu32_epi64(a: __m128i) -> __m128i {
+     let a = a.as_u32x4();
+     let a = simd_shuffle2::<_, u32x2>(a, a, [0, 1]);
+     transmute(simd_cast::<_, i64x2>(a))
+ }
+ 
+ /// Returns the dot product of two __m128d vectors.
+ ///
+ /// `imm8[1:0]` is the broadcast mask, and `imm8[5:4]` is the condition mask.
+ /// If a condition mask bit is zero, the corresponding multiplication is
+ /// replaced by a value of `0.0`. If a broadcast mask bit is one, the result of
+ /// the dot product will be stored in the return value component. Otherwise if
+ /// the broadcast mask bit is zero then the return component will be zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_dp_pd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(dppd, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_dp_pd(a: __m128d, b: __m128d, imm8: i32) -> __m128d {
+     macro_rules! call {
+         ($imm8:expr) => {
+             dppd(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Returns the dot product of two __m128 vectors.
+ ///
+ /// `imm8[3:0]` is the broadcast mask, and `imm8[7:4]` is the condition mask.
+ /// If a condition mask bit is zero, the corresponding multiplication is
+ /// replaced by a value of `0.0`. If a broadcast mask bit is one, the result of
+ /// the dot product will be stored in the return value component. Otherwise if
+ /// the broadcast mask bit is zero then the return component will be zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_dp_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(dpps, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_dp_ps(a: __m128, b: __m128, imm8: i32) -> __m128 {
+     macro_rules! call {
+         ($imm8:expr) => {
+             dpps(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Round the packed double-precision (64-bit) floating-point elements in `a`
+ /// down to an integer value, and stores the results as packed double-precision
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_floor_pd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_floor_pd(a: __m128d) -> __m128d {
+     simd_floor(a)
+ }
+ 
+ /// Round the packed single-precision (32-bit) floating-point elements in `a`
+ /// down to an integer value, and stores the results as packed single-precision
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_floor_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_floor_ps(a: __m128) -> __m128 {
+     simd_floor(a)
+ }
+ 
+ /// Round the lower double-precision (64-bit) floating-point element in `b`
+ /// down to an integer value, store the result as a double-precision
+ /// floating-point element in the lower element of the intrinsic result,
+ /// and copies the upper element from `a` to the upper element of the intrinsic
+ /// result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_floor_sd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_floor_sd(a: __m128d, b: __m128d) -> __m128d {
+     roundsd(a, b, _MM_FROUND_FLOOR)
+ }
+ 
+ /// Round the lower single-precision (32-bit) floating-point element in `b`
+ /// down to an integer value, store the result as a single-precision
+ /// floating-point element in the lower element of the intrinsic result,
+ /// and copies the upper 3 packed elements from `a` to the upper elements
+ /// of the intrinsic result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_floor_ss)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_floor_ss(a: __m128, b: __m128) -> __m128 {
+     roundss(a, b, _MM_FROUND_FLOOR)
+ }
+ 
+ /// Round the packed double-precision (64-bit) floating-point elements in `a`
+ /// up to an integer value, and stores the results as packed double-precision
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ceil_pd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundpd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ceil_pd(a: __m128d) -> __m128d {
+     simd_ceil(a)
+ }
+ 
+ /// Round the packed single-precision (32-bit) floating-point elements in `a`
+ /// up to an integer value, and stores the results as packed single-precision
+ /// floating-point elements.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ceil_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundps))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ceil_ps(a: __m128) -> __m128 {
+     simd_ceil(a)
+ }
+ 
+ /// Round the lower double-precision (64-bit) floating-point element in `b`
+ /// up to an integer value, store the result as a double-precision
+ /// floating-point element in the lower element of the intrisic result,
+ /// and copies the upper element from `a` to the upper element
+ /// of the intrinsic result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ceil_sd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ceil_sd(a: __m128d, b: __m128d) -> __m128d {
+     roundsd(a, b, _MM_FROUND_CEIL)
+ }
+ 
+ /// Round the lower single-precision (32-bit) floating-point element in `b`
+ /// up to an integer value, store the result as a single-precision
+ /// floating-point element in the lower element of the intrinsic result,
+ /// and copies the upper 3 packed elements from `a` to the upper elements
+ /// of the intrinsic result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ceil_ss)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_ceil_ss(a: __m128, b: __m128) -> __m128 {
+     roundss(a, b, _MM_FROUND_CEIL)
+ }
+ 
+ /// Round the packed double-precision (64-bit) floating-point elements in `a`
+ /// using the `rounding` parameter, and stores the results as packed
+ /// double-precision floating-point elements.
+ /// Rounding is done according to the rounding parameter, which can be one of:
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// // round to nearest, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC;
+ /// // round down, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC;
+ /// // round up, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC;
+ /// // truncate, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC;
+ /// // use MXCSR.RC; see `_MM_SET_ROUNDING_MODE`:
+ /// # let _x =
+ /// _MM_FROUND_CUR_DIRECTION;
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_round_pd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundpd, rounding = 0))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_round_pd(a: __m128d, rounding: i32) -> __m128d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             roundpd(a, $imm4)
+         };
+     }
+     constify_imm4!(rounding, call)
+ }
+ 
+ /// Round the packed single-precision (32-bit) floating-point elements in `a`
+ /// using the `rounding` parameter, and stores the results as packed
+ /// single-precision floating-point elements.
+ /// Rounding is done according to the rounding parameter, which can be one of:
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// // round to nearest, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC;
+ /// // round down, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC;
+ /// // round up, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC;
+ /// // truncate, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC;
+ /// // use MXCSR.RC; see `_MM_SET_ROUNDING_MODE`:
+ /// # let _x =
+ /// _MM_FROUND_CUR_DIRECTION;
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_round_ps)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundps, rounding = 0))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_round_ps(a: __m128, rounding: i32) -> __m128 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             roundps(a, $imm4)
+         };
+     }
+     constify_imm4!(rounding, call)
+ }
+ 
+ /// Round the lower double-precision (64-bit) floating-point element in `b`
+ /// using the `rounding` parameter, store the result as a double-precision
+ /// floating-point element in the lower element of the intrinsic result,
+ /// and copies the upper element from `a` to the upper element of the intrinsic
+ /// result.
+ /// Rounding is done according to the rounding parameter, which can be one of:
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// // round to nearest, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC;
+ /// // round down, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC;
+ /// // round up, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC;
+ /// // truncate, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC;
+ /// // use MXCSR.RC; see `_MM_SET_ROUNDING_MODE`:
+ /// # let _x =
+ /// _MM_FROUND_CUR_DIRECTION;
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_round_sd)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundsd, rounding = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_round_sd(a: __m128d, b: __m128d, rounding: i32) -> __m128d {
+     macro_rules! call {
+         ($imm4:expr) => {
+             roundsd(a, b, $imm4)
+         };
+     }
+     constify_imm4!(rounding, call)
+ }
+ 
+ /// Round the lower single-precision (32-bit) floating-point element in `b`
+ /// using the `rounding` parameter, store the result as a single-precision
+ /// floating-point element in the lower element of the intrinsic result,
+ /// and copies the upper 3 packed elements from `a` to the upper elements
+ /// of the instrinsic result.
+ /// Rounding is done according to the rounding parameter, which can be one of:
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// // round to nearest, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC;
+ /// // round down, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC;
+ /// // round up, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC;
+ /// // truncate, and suppress exceptions:
+ /// # let _x =
+ /// _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC;
+ /// // use MXCSR.RC; see `_MM_SET_ROUNDING_MODE`:
+ /// # let _x =
+ /// _MM_FROUND_CUR_DIRECTION;
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_round_ss)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(roundss, rounding = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_round_ss(a: __m128, b: __m128, rounding: i32) -> __m128 {
+     macro_rules! call {
+         ($imm4:expr) => {
+             roundss(a, b, $imm4)
+         };
+     }
+     constify_imm4!(rounding, call)
+ }
+ 
+ /// Finds the minimum unsigned 16-bit element in the 128-bit __m128i vector,
+ /// returning a vector containing its value in its first position, and its
+ /// index
+ /// in its second position; all other elements are set to zero.
+ ///
+ /// This intrinsic corresponds to the <c> VPHMINPOSUW / PHMINPOSUW </c>
+ /// instruction.
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit vector of type `__m128i`.
+ ///
+ /// Returns:
+ ///
+ /// A 128-bit value where:
+ ///
+ /// * bits `[15:0]` - contain the minimum value found in parameter `a`,
+ /// * bits `[18:16]` - contain the index of the minimum value
+ /// * remaining bits are set to `0`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_minpos_epu16)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(phminposuw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_minpos_epu16(a: __m128i) -> __m128i {
+     transmute(phminposuw(a.as_u16x8()))
+ }
+ 
+ /// Multiplies the low 32-bit integers from each packed 64-bit
+ /// element in `a` and `b`, and returns the signed 64-bit result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmuldq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mul_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmuldq(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Multiplies the packed 32-bit integers in `a` and `b`, producing intermediate
+ /// 64-bit integers, and returns the lowest 32-bit, whatever they might be,
+ /// reinterpreted as a signed integer. While `pmulld __m128i::splat(2),
+ /// __m128i::splat(2)` returns the obvious `__m128i::splat(4)`, due to wrapping
+ /// arithmetic `pmulld __m128i::splat(i32::MAX), __m128i::splat(2)` would
+ /// return a negative number.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mullo_epi32)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pmulld))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mullo_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_mul(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Subtracts 8-bit unsigned integer values and computes the absolute
+ /// values of the differences to the corresponding bits in the destination.
+ /// Then sums of the absolute differences are returned according to the bit
+ /// fields in the immediate operand.
+ ///
+ /// The following algorithm is performed:
+ ///
+ /// ```ignore
+ /// i = imm8[2] * 4
+ /// j = imm8[1:0] * 4
+ /// for k := 0 to 7
+ ///     d0 = abs(a[i + k + 0] - b[j + 0])
+ ///     d1 = abs(a[i + k + 1] - b[j + 1])
+ ///     d2 = abs(a[i + k + 2] - b[j + 2])
+ ///     d3 = abs(a[i + k + 3] - b[j + 3])
+ ///     r[k] = d0 + d1 + d2 + d3
+ /// ```
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit vector of type `__m128i`.
+ /// * `b` - A 128-bit vector of type `__m128i`.
+ /// * `imm8` - An 8-bit immediate operand specifying how the absolute
+ ///   differences are to be calculated
+ ///     * Bit `[2]` specify the offset for operand `a`
+ ///     * Bits `[1:0]` specify the offset for operand `b`
+ ///
+ /// Returns:
+ ///
+ /// * A `__m128i` vector containing the sums of the sets of   absolute
+ ///   differences between both operands.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mpsadbw_epu8)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(mpsadbw, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mpsadbw_epu8(a: __m128i, b: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_u8x16();
+     let b = b.as_u8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             mpsadbw(a, b, $imm8)
+         };
+     }
+     transmute(constify_imm3!(imm8, call))
+ }
+ 
+ /// Tests whether the specified bits in a 128-bit integer vector are all
+ /// zeros.
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit integer vector containing the bits to be tested.
+ /// * `mask` - A 128-bit integer vector selecting which bits to test in
+ ///   operand `a`.
+ ///
+ /// Returns:
+ ///
+ /// * `1` - if the specified bits are all zeros,
+ /// * `0` - otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testz_si128)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(ptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testz_si128(a: __m128i, mask: __m128i) -> i32 {
+     ptestz(a.as_i64x2(), mask.as_i64x2())
+ }
+ 
+ /// Tests whether the specified bits in a 128-bit integer vector are all
+ /// ones.
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit integer vector containing the bits to be tested.
+ /// * `mask` - A 128-bit integer vector selecting which bits to test in
+ ///   operand `a`.
+ ///
+ /// Returns:
+ ///
+ /// * `1` - if the specified bits are all ones,
+ /// * `0` - otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testc_si128)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(ptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testc_si128(a: __m128i, mask: __m128i) -> i32 {
+     ptestc(a.as_i64x2(), mask.as_i64x2())
+ }
+ 
+ /// Tests whether the specified bits in a 128-bit integer vector are
+ /// neither all zeros nor all ones.
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit integer vector containing the bits to be tested.
+ /// * `mask` - A 128-bit integer vector selecting which bits to test in
+ ///   operand `a`.
+ ///
+ /// Returns:
+ ///
+ /// * `1` - if the specified bits are neither all zeros nor all ones,
+ /// * `0` - otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_testnzc_si128)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(ptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_testnzc_si128(a: __m128i, mask: __m128i) -> i32 {
+     ptestnzc(a.as_i64x2(), mask.as_i64x2())
+ }
+ 
+ /// Tests whether the specified bits in a 128-bit integer vector are all
+ /// zeros.
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit integer vector containing the bits to be tested.
+ /// * `mask` - A 128-bit integer vector selecting which bits to test in
+ ///   operand `a`.
+ ///
+ /// Returns:
+ ///
+ /// * `1` - if the specified bits are all zeros,
+ /// * `0` - otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_test_all_zeros)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(ptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_test_all_zeros(a: __m128i, mask: __m128i) -> i32 {
+     _mm_testz_si128(a, mask)
+ }
+ 
+ /// Tests whether the specified bits in `a` 128-bit integer vector are all
+ /// ones.
+ ///
+ /// Argument:
+ ///
+ /// * `a` - A 128-bit integer vector containing the bits to be tested.
+ ///
+ /// Returns:
+ ///
+ /// * `1` - if the bits specified in the operand are all set to 1,
+ /// * `0` - otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_test_all_ones)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pcmpeqd))]
+ #[cfg_attr(test, assert_instr(ptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_test_all_ones(a: __m128i) -> i32 {
+     _mm_testc_si128(a, _mm_cmpeq_epi32(a, a))
+ }
+ 
+ /// Tests whether the specified bits in a 128-bit integer vector are
+ /// neither all zeros nor all ones.
+ ///
+ /// Arguments:
+ ///
+ /// * `a` - A 128-bit integer vector containing the bits to be tested.
+ /// * `mask` - A 128-bit integer vector selecting which bits to test in
+ ///   operand `a`.
+ ///
+ /// Returns:
+ ///
+ /// * `1` - if the specified bits are neither all zeros nor all ones,
+ /// * `0` - otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_test_mix_ones_zeros)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(ptest))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_test_mix_ones_zeros(a: __m128i, mask: __m128i) -> i32 {
+     _mm_testnzc_si128(a, mask)
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse41.pblendvb"]
+     fn pblendvb(a: i8x16, b: i8x16, mask: i8x16) -> i8x16;
+     #[link_name = "llvm.x86.sse41.blendvpd"]
+     fn blendvpd(a: __m128d, b: __m128d, mask: __m128d) -> __m128d;
+     #[link_name = "llvm.x86.sse41.blendvps"]
+     fn blendvps(a: __m128, b: __m128, mask: __m128) -> __m128;
+     #[link_name = "llvm.x86.sse41.blendpd"]
+     fn blendpd(a: __m128d, b: __m128d, imm2: u8) -> __m128d;
+     #[link_name = "llvm.x86.sse41.blendps"]
+     fn blendps(a: __m128, b: __m128, imm4: u8) -> __m128;
+     #[link_name = "llvm.x86.sse41.pblendw"]
+     fn pblendw(a: i16x8, b: i16x8, imm8: u8) -> i16x8;
+     #[link_name = "llvm.x86.sse41.insertps"]
+     fn insertps(a: __m128, b: __m128, imm8: u8) -> __m128;
+     #[link_name = "llvm.x86.sse41.pmaxsb"]
+     fn pmaxsb(a: i8x16, b: i8x16) -> i8x16;
+     #[link_name = "llvm.x86.sse41.pmaxuw"]
+     fn pmaxuw(a: u16x8, b: u16x8) -> u16x8;
+     #[link_name = "llvm.x86.sse41.pmaxsd"]
+     fn pmaxsd(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sse41.pmaxud"]
+     fn pmaxud(a: u32x4, b: u32x4) -> u32x4;
+     #[link_name = "llvm.x86.sse41.pminsb"]
+     fn pminsb(a: i8x16, b: i8x16) -> i8x16;
+     #[link_name = "llvm.x86.sse41.pminuw"]
+     fn pminuw(a: u16x8, b: u16x8) -> u16x8;
+     #[link_name = "llvm.x86.sse41.pminsd"]
+     fn pminsd(a: i32x4, b: i32x4) -> i32x4;
+     #[link_name = "llvm.x86.sse41.pminud"]
+     fn pminud(a: u32x4, b: u32x4) -> u32x4;
+     #[link_name = "llvm.x86.sse41.packusdw"]
+     fn packusdw(a: i32x4, b: i32x4) -> u16x8;
+     #[link_name = "llvm.x86.sse41.dppd"]
+     fn dppd(a: __m128d, b: __m128d, imm8: u8) -> __m128d;
+     #[link_name = "llvm.x86.sse41.dpps"]
+     fn dpps(a: __m128, b: __m128, imm8: u8) -> __m128;
+     #[link_name = "llvm.x86.sse41.round.pd"]
+     fn roundpd(a: __m128d, rounding: i32) -> __m128d;
+     #[link_name = "llvm.x86.sse41.round.ps"]
+     fn roundps(a: __m128, rounding: i32) -> __m128;
+     #[link_name = "llvm.x86.sse41.round.sd"]
+     fn roundsd(a: __m128d, b: __m128d, rounding: i32) -> __m128d;
+     #[link_name = "llvm.x86.sse41.round.ss"]
+     fn roundss(a: __m128, b: __m128, rounding: i32) -> __m128;
+     #[link_name = "llvm.x86.sse41.phminposuw"]
+     fn phminposuw(a: u16x8) -> u16x8;
+     #[link_name = "llvm.x86.sse41.pmuldq"]
+     fn pmuldq(a: i32x4, b: i32x4) -> i64x2;
+     #[link_name = "llvm.x86.sse41.mpsadbw"]
+     fn mpsadbw(a: u8x16, b: u8x16, imm8: u8) -> u16x8;
+     #[link_name = "llvm.x86.sse41.ptestz"]
+     fn ptestz(a: i64x2, mask: i64x2) -> i32;
+     #[link_name = "llvm.x86.sse41.ptestc"]
+     fn ptestc(a: i64x2, mask: i64x2) -> i32;
+     #[link_name = "llvm.x86.sse41.ptestnzc"]
+     fn ptestnzc(a: i64x2, mask: i64x2) -> i32;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+     use std::mem;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_blendv_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+         );
+         #[rustfmt::skip]
+         let mask = _mm_setr_epi8(
+             0, -1, 0, -1, 0, -1, 0, -1,
+             0, -1, 0, -1, 0, -1, 0, -1,
+         );
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31,
+         );
+         assert_eq_m128i(_mm_blendv_epi8(a, b, mask), e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_blendv_pd() {
+         let a = _mm_set1_pd(0.0);
+         let b = _mm_set1_pd(1.0);
+         let mask = transmute(_mm_setr_epi64x(0, -1));
+         let r = _mm_blendv_pd(a, b, mask);
+         let e = _mm_setr_pd(0.0, 1.0);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_blendv_ps() {
+         let a = _mm_set1_ps(0.0);
+         let b = _mm_set1_ps(1.0);
+         let mask = transmute(_mm_setr_epi32(0, -1, 0, -1));
+         let r = _mm_blendv_ps(a, b, mask);
+         let e = _mm_setr_ps(0.0, 1.0, 0.0, 1.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_blend_pd() {
+         let a = _mm_set1_pd(0.0);
+         let b = _mm_set1_pd(1.0);
+         let r = _mm_blend_pd(a, b, 0b10);
+         let e = _mm_setr_pd(0.0, 1.0);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_blend_ps() {
+         let a = _mm_set1_ps(0.0);
+         let b = _mm_set1_ps(1.0);
+         let r = _mm_blend_ps(a, b, 0b1010);
+         let e = _mm_setr_ps(0.0, 1.0, 0.0, 1.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_blend_epi16() {
+         let a = _mm_set1_epi16(0);
+         let b = _mm_set1_epi16(1);
+         let r = _mm_blend_epi16(a, b, 0b1010_1100);
+         let e = _mm_setr_epi16(0, 0, 1, 1, 0, 1, 0, 1);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_extract_ps() {
+         let a = _mm_setr_ps(0.0, 1.0, 2.0, 3.0);
+         let r: f32 = transmute(_mm_extract_ps(a, 1));
+         assert_eq!(r, 1.0);
+         let r: f32 = transmute(_mm_extract_ps(a, 5));
+         assert_eq!(r, 1.0);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_extract_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             -1, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15
+         );
+         let r1 = _mm_extract_epi8(a, 0);
+         let r2 = _mm_extract_epi8(a, 19);
+         assert_eq!(r1, 0xFF);
+         assert_eq!(r2, 3);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_extract_epi32() {
+         let a = _mm_setr_epi32(0, 1, 2, 3);
+         let r = _mm_extract_epi32(a, 1);
+         assert_eq!(r, 1);
+         let r = _mm_extract_epi32(a, 5);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_insert_ps() {
+         let a = _mm_set1_ps(1.0);
+         let b = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
+         let r = _mm_insert_ps(a, b, 0b11_00_1100);
+         let e = _mm_setr_ps(4.0, 1.0, 0.0, 0.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_insert_epi8() {
+         let a = _mm_set1_epi8(0);
+         let e = _mm_setr_epi8(0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+         let r = _mm_insert_epi8(a, 32, 1);
+         assert_eq_m128i(r, e);
+         let r = _mm_insert_epi8(a, 32, 17);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_insert_epi32() {
+         let a = _mm_set1_epi32(0);
+         let e = _mm_setr_epi32(0, 32, 0, 0);
+         let r = _mm_insert_epi32(a, 32, 1);
+         assert_eq_m128i(r, e);
+         let r = _mm_insert_epi32(a, 32, 5);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_max_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 4, 5, 8, 9, 12, 13, 16,
+             17, 20, 21, 24, 25, 28, 29, 32,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             2, 3, 6, 7, 10, 11, 14, 15,
+             18, 19, 22, 23, 26, 27, 30, 31,
+         );
+         let r = _mm_max_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             2, 4, 6, 8, 10, 12, 14, 16,
+             18, 20, 22, 24, 26, 28, 30, 32,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_max_epu16() {
+         let a = _mm_setr_epi16(1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm_setr_epi16(2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm_max_epu16(a, b);
+         let e = _mm_setr_epi16(2, 4, 6, 8, 10, 12, 14, 16);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_max_epi32() {
+         let a = _mm_setr_epi32(1, 4, 5, 8);
+         let b = _mm_setr_epi32(2, 3, 6, 7);
+         let r = _mm_max_epi32(a, b);
+         let e = _mm_setr_epi32(2, 4, 6, 8);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_max_epu32() {
+         let a = _mm_setr_epi32(1, 4, 5, 8);
+         let b = _mm_setr_epi32(2, 3, 6, 7);
+         let r = _mm_max_epu32(a, b);
+         let e = _mm_setr_epi32(2, 4, 6, 8);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_min_epi8_1() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 4, 5, 8, 9, 12, 13, 16,
+             17, 20, 21, 24, 25, 28, 29, 32,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             2, 3, 6, 7, 10, 11, 14, 15,
+             18, 19, 22, 23, 26, 27, 30, 31,
+         );
+         let r = _mm_min_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             1, 3, 5, 7, 9, 11, 13, 15,
+             17, 19, 21, 23, 25, 27, 29, 31,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_min_epi8_2() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, -4, -5, 8, -9, -12, 13, -16,
+             17, 20, 21, 24, 25, 28, 29, 32,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             2, -3, -6, 7, -10, -11, 14, -15,
+             18, 19, 22, 23, 26, 27, 30, 31,
+         );
+         let r = _mm_min_epi8(a, b);
+         #[rustfmt::skip]
+         let e = _mm_setr_epi8(
+             1, -4, -6, 7, -10, -12, 13, -16,
+             17, 19, 21, 23, 25, 27, 29, 31,
+         );
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_min_epu16() {
+         let a = _mm_setr_epi16(1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm_setr_epi16(2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm_min_epu16(a, b);
+         let e = _mm_setr_epi16(1, 3, 5, 7, 9, 11, 13, 15);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_min_epi32_1() {
+         let a = _mm_setr_epi32(1, 4, 5, 8);
+         let b = _mm_setr_epi32(2, 3, 6, 7);
+         let r = _mm_min_epi32(a, b);
+         let e = _mm_setr_epi32(1, 3, 5, 7);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_min_epi32_2() {
+         let a = _mm_setr_epi32(-1, 4, 5, -7);
+         let b = _mm_setr_epi32(-2, 3, -6, 8);
+         let r = _mm_min_epi32(a, b);
+         let e = _mm_setr_epi32(-2, 3, -6, -7);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_min_epu32() {
+         let a = _mm_setr_epi32(1, 4, 5, 8);
+         let b = _mm_setr_epi32(2, 3, 6, 7);
+         let r = _mm_min_epu32(a, b);
+         let e = _mm_setr_epi32(1, 3, 5, 7);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_packus_epi32() {
+         let a = _mm_setr_epi32(1, 2, 3, 4);
+         let b = _mm_setr_epi32(-1, -2, -3, -4);
+         let r = _mm_packus_epi32(a, b);
+         let e = _mm_setr_epi16(1, 2, 3, 4, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cmpeq_epi64() {
+         let a = _mm_setr_epi64x(0, 1);
+         let b = _mm_setr_epi64x(0, 0);
+         let r = _mm_cmpeq_epi64(a, b);
+         let e = _mm_setr_epi64x(-1, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepi8_epi16() {
+         let a = _mm_set1_epi8(10);
+         let r = _mm_cvtepi8_epi16(a);
+         let e = _mm_set1_epi16(10);
+         assert_eq_m128i(r, e);
+         let a = _mm_set1_epi8(-10);
+         let r = _mm_cvtepi8_epi16(a);
+         let e = _mm_set1_epi16(-10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepi8_epi32() {
+         let a = _mm_set1_epi8(10);
+         let r = _mm_cvtepi8_epi32(a);
+         let e = _mm_set1_epi32(10);
+         assert_eq_m128i(r, e);
+         let a = _mm_set1_epi8(-10);
+         let r = _mm_cvtepi8_epi32(a);
+         let e = _mm_set1_epi32(-10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepi8_epi64() {
+         let a = _mm_set1_epi8(10);
+         let r = _mm_cvtepi8_epi64(a);
+         let e = _mm_set1_epi64x(10);
+         assert_eq_m128i(r, e);
+         let a = _mm_set1_epi8(-10);
+         let r = _mm_cvtepi8_epi64(a);
+         let e = _mm_set1_epi64x(-10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepi16_epi32() {
+         let a = _mm_set1_epi16(10);
+         let r = _mm_cvtepi16_epi32(a);
+         let e = _mm_set1_epi32(10);
+         assert_eq_m128i(r, e);
+         let a = _mm_set1_epi16(-10);
+         let r = _mm_cvtepi16_epi32(a);
+         let e = _mm_set1_epi32(-10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepi16_epi64() {
+         let a = _mm_set1_epi16(10);
+         let r = _mm_cvtepi16_epi64(a);
+         let e = _mm_set1_epi64x(10);
+         assert_eq_m128i(r, e);
+         let a = _mm_set1_epi16(-10);
+         let r = _mm_cvtepi16_epi64(a);
+         let e = _mm_set1_epi64x(-10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepi32_epi64() {
+         let a = _mm_set1_epi32(10);
+         let r = _mm_cvtepi32_epi64(a);
+         let e = _mm_set1_epi64x(10);
+         assert_eq_m128i(r, e);
+         let a = _mm_set1_epi32(-10);
+         let r = _mm_cvtepi32_epi64(a);
+         let e = _mm_set1_epi64x(-10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepu8_epi16() {
+         let a = _mm_set1_epi8(10);
+         let r = _mm_cvtepu8_epi16(a);
+         let e = _mm_set1_epi16(10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepu8_epi32() {
+         let a = _mm_set1_epi8(10);
+         let r = _mm_cvtepu8_epi32(a);
+         let e = _mm_set1_epi32(10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepu8_epi64() {
+         let a = _mm_set1_epi8(10);
+         let r = _mm_cvtepu8_epi64(a);
+         let e = _mm_set1_epi64x(10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepu16_epi32() {
+         let a = _mm_set1_epi16(10);
+         let r = _mm_cvtepu16_epi32(a);
+         let e = _mm_set1_epi32(10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepu16_epi64() {
+         let a = _mm_set1_epi16(10);
+         let r = _mm_cvtepu16_epi64(a);
+         let e = _mm_set1_epi64x(10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_cvtepu32_epi64() {
+         let a = _mm_set1_epi32(10);
+         let r = _mm_cvtepu32_epi64(a);
+         let e = _mm_set1_epi64x(10);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_dp_pd() {
+         let a = _mm_setr_pd(2.0, 3.0);
+         let b = _mm_setr_pd(1.0, 4.0);
+         let e = _mm_setr_pd(14.0, 0.0);
+         assert_eq_m128d(_mm_dp_pd(a, b, 0b00110001), e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_dp_ps() {
+         let a = _mm_setr_ps(2.0, 3.0, 1.0, 10.0);
+         let b = _mm_setr_ps(1.0, 4.0, 0.5, 10.0);
+         let e = _mm_setr_ps(14.5, 0.0, 14.5, 0.0);
+         assert_eq_m128(_mm_dp_ps(a, b, 0b01110101), e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_floor_pd() {
+         let a = _mm_setr_pd(2.5, 4.5);
+         let r = _mm_floor_pd(a);
+         let e = _mm_setr_pd(2.0, 4.0);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_floor_ps() {
+         let a = _mm_setr_ps(2.5, 4.5, 8.5, 16.5);
+         let r = _mm_floor_ps(a);
+         let e = _mm_setr_ps(2.0, 4.0, 8.0, 16.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_floor_sd() {
+         let a = _mm_setr_pd(2.5, 4.5);
+         let b = _mm_setr_pd(-1.5, -3.5);
+         let r = _mm_floor_sd(a, b);
+         let e = _mm_setr_pd(-2.0, 4.5);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_floor_ss() {
+         let a = _mm_setr_ps(2.5, 4.5, 8.5, 16.5);
+         let b = _mm_setr_ps(-1.5, -3.5, -7.5, -15.5);
+         let r = _mm_floor_ss(a, b);
+         let e = _mm_setr_ps(-2.0, 4.5, 8.5, 16.5);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_ceil_pd() {
+         let a = _mm_setr_pd(1.5, 3.5);
+         let r = _mm_ceil_pd(a);
+         let e = _mm_setr_pd(2.0, 4.0);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_ceil_ps() {
+         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
+         let r = _mm_ceil_ps(a);
+         let e = _mm_setr_ps(2.0, 4.0, 8.0, 16.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_ceil_sd() {
+         let a = _mm_setr_pd(1.5, 3.5);
+         let b = _mm_setr_pd(-2.5, -4.5);
+         let r = _mm_ceil_sd(a, b);
+         let e = _mm_setr_pd(-2.0, 3.5);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_ceil_ss() {
+         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
+         let b = _mm_setr_ps(-2.5, -4.5, -8.5, -16.5);
+         let r = _mm_ceil_ss(a, b);
+         let e = _mm_setr_ps(-2.0, 3.5, 7.5, 15.5);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_round_pd() {
+         let a = _mm_setr_pd(1.25, 3.75);
+         let r = _mm_round_pd(a, _MM_FROUND_TO_NEAREST_INT);
+         let e = _mm_setr_pd(1.0, 4.0);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_round_ps() {
+         let a = _mm_setr_ps(2.25, 4.75, -1.75, -4.25);
+         let r = _mm_round_ps(a, _MM_FROUND_TO_ZERO);
+         let e = _mm_setr_ps(2.0, 4.0, -1.0, -4.0);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_round_sd() {
+         let a = _mm_setr_pd(1.5, 3.5);
+         let b = _mm_setr_pd(-2.5, -4.5);
+         let old_mode = _MM_GET_ROUNDING_MODE();
+         _MM_SET_ROUNDING_MODE(_MM_ROUND_TOWARD_ZERO);
+         let r = _mm_round_sd(a, b, _MM_FROUND_CUR_DIRECTION);
+         _MM_SET_ROUNDING_MODE(old_mode);
+         let e = _mm_setr_pd(-2.0, 3.5);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_round_ss() {
+         let a = _mm_setr_ps(1.5, 3.5, 7.5, 15.5);
+         let b = _mm_setr_ps(-1.75, -4.5, -8.5, -16.5);
+         let old_mode = _MM_GET_ROUNDING_MODE();
+         _MM_SET_ROUNDING_MODE(_MM_ROUND_NEAREST);
+         let r = _mm_round_ss(a, b, _MM_FROUND_CUR_DIRECTION);
+         _MM_SET_ROUNDING_MODE(old_mode);
+         let e = _mm_setr_ps(-2.0, 3.5, 7.5, 15.5);
+         assert_eq_m128(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_minpos_epu16_1() {
+         let a = _mm_setr_epi16(23, 18, 44, 97, 50, 13, 67, 66);
+         let r = _mm_minpos_epu16(a);
+         let e = _mm_setr_epi16(13, 5, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_minpos_epu16_2() {
+         let a = _mm_setr_epi16(0, 18, 44, 97, 50, 13, 67, 66);
+         let r = _mm_minpos_epu16(a);
+         let e = _mm_setr_epi16(0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_mul_epi32() {
+         {
+             let a = _mm_setr_epi32(1, 1, 1, 1);
+             let b = _mm_setr_epi32(1, 2, 3, 4);
+             let r = _mm_mul_epi32(a, b);
+             let e = _mm_setr_epi64x(1, 3);
+             assert_eq_m128i(r, e);
+         }
+         {
+             let a = _mm_setr_epi32(15, 2 /* ignored */, 1234567, 4 /* ignored */);
+             let b = _mm_setr_epi32(
+                 -20, -256, /* ignored */
+                 666666, 666666, /* ignored */
+             );
+             let r = _mm_mul_epi32(a, b);
+             let e = _mm_setr_epi64x(-300, 823043843622);
+             assert_eq_m128i(r, e);
+         }
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_mullo_epi32() {
+         {
+             let a = _mm_setr_epi32(1, 1, 1, 1);
+             let b = _mm_setr_epi32(1, 2, 3, 4);
+             let r = _mm_mullo_epi32(a, b);
+             let e = _mm_setr_epi32(1, 2, 3, 4);
+             assert_eq_m128i(r, e);
+         }
+         {
+             let a = _mm_setr_epi32(15, -2, 1234567, 99999);
+             let b = _mm_setr_epi32(-20, -256, 666666, -99999);
+             let r = _mm_mullo_epi32(a, b);
+             // Attention, most significant bit in r[2] is treated
+             // as a sign bit:
+             // 1234567 * 666666 = -1589877210
+             let e = _mm_setr_epi32(-300, 512, -1589877210, -1409865409);
+             assert_eq_m128i(r, e);
+         }
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_minpos_epu16() {
+         let a = _mm_setr_epi16(8, 7, 6, 5, 4, 1, 2, 3);
+         let r = _mm_minpos_epu16(a);
+         let e = _mm_setr_epi16(1, 5, 0, 0, 0, 0, 0, 0);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_mpsadbw_epu8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+ 
+         let r = _mm_mpsadbw_epu8(a, a, 0b000);
+         let e = _mm_setr_epi16(0, 4, 8, 12, 16, 20, 24, 28);
+         assert_eq_m128i(r, e);
+ 
+         let r = _mm_mpsadbw_epu8(a, a, 0b001);
+         let e = _mm_setr_epi16(16, 12, 8, 4, 0, 4, 8, 12);
+         assert_eq_m128i(r, e);
+ 
+         let r = _mm_mpsadbw_epu8(a, a, 0b100);
+         let e = _mm_setr_epi16(16, 20, 24, 28, 32, 36, 40, 44);
+         assert_eq_m128i(r, e);
+ 
+         let r = _mm_mpsadbw_epu8(a, a, 0b101);
+         let e = _mm_setr_epi16(0, 4, 8, 12, 16, 20, 24, 28);
+         assert_eq_m128i(r, e);
+ 
+         let r = _mm_mpsadbw_epu8(a, a, 0b111);
+         let e = _mm_setr_epi16(32, 28, 24, 20, 16, 12, 8, 4);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_testz_si128() {
+         let a = _mm_set1_epi8(1);
+         let mask = _mm_set1_epi8(0);
+         let r = _mm_testz_si128(a, mask);
+         assert_eq!(r, 1);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b110);
+         let r = _mm_testz_si128(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(0b011);
+         let mask = _mm_set1_epi8(0b100);
+         let r = _mm_testz_si128(a, mask);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_testc_si128() {
+         let a = _mm_set1_epi8(-1);
+         let mask = _mm_set1_epi8(0);
+         let r = _mm_testc_si128(a, mask);
+         assert_eq!(r, 1);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b110);
+         let r = _mm_testc_si128(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b100);
+         let r = _mm_testc_si128(a, mask);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_testnzc_si128() {
+         let a = _mm_set1_epi8(0);
+         let mask = _mm_set1_epi8(1);
+         let r = _mm_testnzc_si128(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(-1);
+         let mask = _mm_set1_epi8(0);
+         let r = _mm_testnzc_si128(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b110);
+         let r = _mm_testnzc_si128(a, mask);
+         assert_eq!(r, 1);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b101);
+         let r = _mm_testnzc_si128(a, mask);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_test_all_zeros() {
+         let a = _mm_set1_epi8(1);
+         let mask = _mm_set1_epi8(0);
+         let r = _mm_test_all_zeros(a, mask);
+         assert_eq!(r, 1);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b110);
+         let r = _mm_test_all_zeros(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(0b011);
+         let mask = _mm_set1_epi8(0b100);
+         let r = _mm_test_all_zeros(a, mask);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_test_all_ones() {
+         let a = _mm_set1_epi8(-1);
+         let r = _mm_test_all_ones(a);
+         assert_eq!(r, 1);
+         let a = _mm_set1_epi8(0b101);
+         let r = _mm_test_all_ones(a);
+         assert_eq!(r, 0);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_test_mix_ones_zeros() {
+         let a = _mm_set1_epi8(0);
+         let mask = _mm_set1_epi8(1);
+         let r = _mm_test_mix_ones_zeros(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(-1);
+         let mask = _mm_set1_epi8(0);
+         let r = _mm_test_mix_ones_zeros(a, mask);
+         assert_eq!(r, 0);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b110);
+         let r = _mm_test_mix_ones_zeros(a, mask);
+         assert_eq!(r, 1);
+         let a = _mm_set1_epi8(0b101);
+         let mask = _mm_set1_epi8(0b101);
+         let r = _mm_test_mix_ones_zeros(a, mask);
+         assert_eq!(r, 0);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse42.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse42.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse42.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse42.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,886 ----
+ //! Streaming SIMD Extensions 4.2 (SSE4.2)
+ //!
+ //! Extends SSE4.1 with STTNI (String and Text New Instructions).
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     mem::transmute,
+ };
+ 
+ /// String contains unsigned 8-bit characters *(Default)*
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_UBYTE_OPS: i32 = 0b0000_0000;
+ /// String contains unsigned 16-bit characters
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_UWORD_OPS: i32 = 0b0000_0001;
+ /// String contains signed 8-bit characters
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_SBYTE_OPS: i32 = 0b0000_0010;
+ /// String contains unsigned 16-bit characters
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_SWORD_OPS: i32 = 0b0000_0011;
+ 
+ /// For each character in `a`, find if it is in `b` *(Default)*
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_CMP_EQUAL_ANY: i32 = 0b0000_0000;
+ /// For each character in `a`, determine if
+ /// `b[0] <= c <= b[1] or b[1] <= c <= b[2]...`
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_CMP_RANGES: i32 = 0b0000_0100;
+ /// The strings defined by `a` and `b` are equal
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_CMP_EQUAL_EACH: i32 = 0b0000_1000;
+ /// Search for the defined substring in the target
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_CMP_EQUAL_ORDERED: i32 = 0b0000_1100;
+ 
+ /// Do not negate results *(Default)*
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_POSITIVE_POLARITY: i32 = 0b0000_0000;
+ /// Negates results
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_NEGATIVE_POLARITY: i32 = 0b0001_0000;
+ /// Do not negate results before the end of the string
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_MASKED_POSITIVE_POLARITY: i32 = 0b0010_0000;
+ /// Negates results only before the end of the string
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_MASKED_NEGATIVE_POLARITY: i32 = 0b0011_0000;
+ 
+ /// **Index only**: return the least significant bit *(Default)*
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_LEAST_SIGNIFICANT: i32 = 0b0000_0000;
+ /// **Index only**: return the most significant bit
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_MOST_SIGNIFICANT: i32 = 0b0100_0000;
+ 
+ /// **Mask only**: return the bit mask
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_BIT_MASK: i32 = 0b0000_0000;
+ /// **Mask only**: return the byte mask
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _SIDD_UNIT_MASK: i32 = 0b0100_0000;
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8`, and return the generated mask.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistrm)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistrm, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistrm(a: __m128i, b: __m128i, imm8: i32) -> __m128i {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistrm128(a, b, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8, call))
+ }
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8` and return the generated index. Similar to
+ /// [`_mm_cmpestri`] with the exception that [`_mm_cmpestri`] requires the
+ /// lengths of `a` and `b` to be explicitly specified.
+ ///
+ /// # Control modes
+ ///
+ /// The control specified by `imm8` may be one or more of the following.
+ ///
+ /// ## Data size and signedness
+ ///
+ ///  - [`_SIDD_UBYTE_OPS`] - Default
+ ///  - [`_SIDD_UWORD_OPS`]
+ ///  - [`_SIDD_SBYTE_OPS`]
+ ///  - [`_SIDD_SWORD_OPS`]
+ ///
+ /// ## Comparison options
+ ///  - [`_SIDD_CMP_EQUAL_ANY`] - Default
+ ///  - [`_SIDD_CMP_RANGES`]
+ ///  - [`_SIDD_CMP_EQUAL_EACH`]
+ ///  - [`_SIDD_CMP_EQUAL_ORDERED`]
+ ///
+ /// ## Result polarity
+ ///  - [`_SIDD_POSITIVE_POLARITY`] - Default
+ ///  - [`_SIDD_NEGATIVE_POLARITY`]
+ ///
+ /// ## Bit returned
+ ///  - [`_SIDD_LEAST_SIGNIFICANT`] - Default
+ ///  - [`_SIDD_MOST_SIGNIFICANT`]
+ ///
+ /// # Examples
+ ///
+ /// Finds a substring using [`_SIDD_CMP_EQUAL_ORDERED`]
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("sse4.2") {
+ /// #         #[target_feature(enable = "sse4.2")]
+ /// #         unsafe fn worker() {
+ /// let haystack = b"This is a long string of text data\r\n\tthat extends
+ /// multiple lines";
+ /// let needle = b"\r\n\t\0\0\0\0\0\0\0\0\0\0\0\0\0";
+ ///
+ /// let a = _mm_loadu_si128(needle.as_ptr() as *const _);
+ /// let hop = 16;
+ /// let mut indexes = Vec::new();
+ ///
+ /// // Chunk the haystack into 16 byte chunks and find
+ /// // the first "\r\n\t" in the chunk.
+ /// for (i, chunk) in haystack.chunks(hop).enumerate() {
+ ///     let b = _mm_loadu_si128(chunk.as_ptr() as *const _);
+ ///     let idx = _mm_cmpistri(a, b, _SIDD_CMP_EQUAL_ORDERED);
+ ///     if idx != 16 {
+ ///         indexes.push((idx as usize) + (i * hop));
+ ///     }
+ /// }
+ /// assert_eq!(indexes, vec![34]);
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// The `_mm_cmpistri` intrinsic may also be used to find the existance of
+ /// one or more of a given set of characters in the haystack.
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("sse4.2") {
+ /// #         #[target_feature(enable = "sse4.2")]
+ /// #         unsafe fn worker() {
+ /// // Ensure your input is 16 byte aligned
+ /// let password = b"hunter2\0\0\0\0\0\0\0\0\0";
+ /// let special_chars = b"!@#$%^&*()[]:;<>";
+ ///
+ /// // Load the input
+ /// let a = _mm_loadu_si128(special_chars.as_ptr() as *const _);
+ /// let b = _mm_loadu_si128(password.as_ptr() as *const _);
+ ///
+ /// // Use _SIDD_CMP_EQUAL_ANY to find the index of any bytes in b
+ /// let idx = _mm_cmpistri(a.into(), b.into(), _SIDD_CMP_EQUAL_ANY);
+ ///
+ /// if idx < 16 {
+ ///     println!("Congrats! Your password contains a special character");
+ ///     # panic!("{:?} does not contain a special character", password);
+ /// } else {
+ ///     println!("Your password should contain a special character");
+ /// }
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// Finds the index of the first character in the haystack that is within a
+ /// range of characters.
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("sse4.2") {
+ /// #         #[target_feature(enable = "sse4.2")]
+ /// #         unsafe fn worker() {
+ /// # let b = b":;<=>?@[\\]^_`abc";
+ /// # let b = _mm_loadu_si128(b.as_ptr() as *const _);
+ ///
+ /// // Specify the ranges of values to be searched for [A-Za-z0-9].
+ /// let a = b"AZaz09\0\0\0\0\0\0\0\0\0\0";
+ /// let a = _mm_loadu_si128(a.as_ptr() as *const _);
+ ///
+ /// // Use _SIDD_CMP_RANGES to find the index of first byte in ranges.
+ /// // Which in this case will be the first alpha numeric byte found
+ /// // in the string.
+ /// let idx = _mm_cmpistri(a, b, _SIDD_CMP_RANGES);
+ ///
+ /// if idx < 16 {
+ ///     println!("Found an alpha numeric character");
+ ///     # assert_eq!(idx, 13);
+ /// } else {
+ ///     println!("Did not find an alpha numeric character");
+ /// }
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// Working with 16-bit characters.
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("sse4.2") {
+ /// #         #[target_feature(enable = "sse4.2")]
+ /// #         unsafe fn worker() {
+ /// # let mut some_utf16_words = [0u16; 8];
+ /// # let mut more_utf16_words = [0u16; 8];
+ /// # '❤'.encode_utf16(&mut some_utf16_words);
+ /// # '𝕊'.encode_utf16(&mut more_utf16_words);
+ /// // Load the input
+ /// let a = _mm_loadu_si128(some_utf16_words.as_ptr() as *const _);
+ /// let b = _mm_loadu_si128(more_utf16_words.as_ptr() as *const _);
+ ///
+ /// // Specify _SIDD_UWORD_OPS to compare words instead of bytes, and
+ /// // use _SIDD_CMP_EQUAL_EACH to compare the two strings.
+ /// let idx = _mm_cmpistri(a, b, _SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_EACH);
+ ///
+ /// if idx == 0 {
+ ///     println!("16-bit unicode strings were equal!");
+ ///     # panic!("Strings should not be equal!")
+ /// } else {
+ ///     println!("16-bit unicode strings were not equal!");
+ /// }
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistri)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistri, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistri(a: __m128i, b: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistri128(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8`, and return `1` if any character in `b` was null.
+ /// and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistrz)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistri, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistrz(a: __m128i, b: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistriz128(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8`, and return `1` if the resulting mask was non-zero,
+ /// and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistrc)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistri, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistrc(a: __m128i, b: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistric128(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8`, and returns `1` if any character in `a` was null,
+ /// and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistrs)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistri, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistrs(a: __m128i, b: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistris128(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8`, and return bit `0` of the resulting bit mask.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistro)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistri, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistro(a: __m128i, b: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistrio128(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings with implicit lengths in `a` and `b` using the
+ /// control in `imm8`, and return `1` if `b` did not contain a null
+ /// character and the resulting mask was zero, and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpistra)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpistri, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpistra(a: __m128i, b: __m128i, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpistria128(a, b, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings in `a` and `b` with lengths `la` and `lb`
+ /// using the control in `imm8`, and return the generated mask.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestrm)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestrm, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestrm(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> __m128i {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestrm128(a, la, b, lb, $imm8)
+         };
+     }
+     transmute(constify_imm8!(imm8, call))
+ }
+ 
+ /// Compares packed strings `a` and `b` with lengths `la` and `lb` using the
+ /// control in `imm8` and return the generated index. Similar to
+ /// [`_mm_cmpistri`] with the exception that [`_mm_cmpistri`] implicitly
+ /// determines the length of `a` and `b`.
+ ///
+ /// # Control modes
+ ///
+ /// The control specified by `imm8` may be one or more of the following.
+ ///
+ /// ## Data size and signedness
+ ///
+ ///  - [`_SIDD_UBYTE_OPS`] - Default
+ ///  - [`_SIDD_UWORD_OPS`]
+ ///  - [`_SIDD_SBYTE_OPS`]
+ ///  - [`_SIDD_SWORD_OPS`]
+ ///
+ /// ## Comparison options
+ ///  - [`_SIDD_CMP_EQUAL_ANY`] - Default
+ ///  - [`_SIDD_CMP_RANGES`]
+ ///  - [`_SIDD_CMP_EQUAL_EACH`]
+ ///  - [`_SIDD_CMP_EQUAL_ORDERED`]
+ ///
+ /// ## Result polarity
+ ///  - [`_SIDD_POSITIVE_POLARITY`] - Default
+ ///  - [`_SIDD_NEGATIVE_POLARITY`]
+ ///
+ /// ## Bit returned
+ ///  - [`_SIDD_LEAST_SIGNIFICANT`] - Default
+ ///  - [`_SIDD_MOST_SIGNIFICANT`]
+ ///
+ /// # Examples
+ ///
+ /// ```
+ /// #[cfg(target_arch = "x86")]
+ /// use std::arch::x86::*;
+ /// #[cfg(target_arch = "x86_64")]
+ /// use std::arch::x86_64::*;
+ ///
+ /// # fn main() {
+ /// #     if is_x86_feature_detected!("sse4.2") {
+ /// #         #[target_feature(enable = "sse4.2")]
+ /// #         unsafe fn worker() {
+ ///
+ /// // The string we want to find a substring in
+ /// let haystack = b"Split \r\n\t line  ";
+ ///
+ /// // The string we want to search for with some
+ /// // extra bytes we do not want to search for.
+ /// let needle = b"\r\n\t ignore this ";
+ ///
+ /// let a = _mm_loadu_si128(needle.as_ptr() as *const _);
+ /// let b = _mm_loadu_si128(haystack.as_ptr() as *const _);
+ ///
+ /// // Note: We explicitly specify we only want to search `b` for the
+ /// // first 3 characters of a.
+ /// let idx = _mm_cmpestri(a, 3, b, 15, _SIDD_CMP_EQUAL_ORDERED);
+ ///
+ /// assert_eq!(idx, 6);
+ /// #         }
+ /// #         unsafe { worker(); }
+ /// #     }
+ /// # }
+ /// ```
+ ///
+ /// [`_SIDD_UBYTE_OPS`]: constant._SIDD_UBYTE_OPS.html
+ /// [`_SIDD_UWORD_OPS`]: constant._SIDD_UWORD_OPS.html
+ /// [`_SIDD_SBYTE_OPS`]: constant._SIDD_SBYTE_OPS.html
+ /// [`_SIDD_SWORD_OPS`]: constant._SIDD_SWORD_OPS.html
+ /// [`_SIDD_CMP_EQUAL_ANY`]: constant._SIDD_CMP_EQUAL_ANY.html
+ /// [`_SIDD_CMP_RANGES`]: constant._SIDD_CMP_RANGES.html
+ /// [`_SIDD_CMP_EQUAL_EACH`]: constant._SIDD_CMP_EQUAL_EACH.html
+ /// [`_SIDD_CMP_EQUAL_ORDERED`]: constant._SIDD_CMP_EQUAL_ORDERED.html
+ /// [`_SIDD_POSITIVE_POLARITY`]: constant._SIDD_POSITIVE_POLARITY.html
+ /// [`_SIDD_NEGATIVE_POLARITY`]: constant._SIDD_NEGATIVE_POLARITY.html
+ /// [`_SIDD_LEAST_SIGNIFICANT`]: constant._SIDD_LEAST_SIGNIFICANT.html
+ /// [`_SIDD_MOST_SIGNIFICANT`]: constant._SIDD_MOST_SIGNIFICANT.html
+ /// [`_mm_cmpistri`]: fn._mm_cmpistri.html
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestri)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestri, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestri(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestri128(a, la, b, lb, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings in `a` and `b` with lengths `la` and `lb`
+ /// using the control in `imm8`, and return `1` if any character in
+ /// `b` was null, and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestrz)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestri, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestrz(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestriz128(a, la, b, lb, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings in `a` and `b` with lengths `la` and `lb`
+ /// using the control in `imm8`, and return `1` if the resulting mask
+ /// was non-zero, and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestrc)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestri, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestrc(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestric128(a, la, b, lb, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings in `a` and `b` with lengths `la` and `lb`
+ /// using the control in `imm8`, and return `1` if any character in
+ /// a was null, and `0` otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestrs)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestri, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestrs(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestris128(a, la, b, lb, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings in `a` and `b` with lengths `la` and `lb`
+ /// using the control in `imm8`, and return bit `0` of the resulting
+ /// bit mask.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestro)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestri, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestro(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestrio128(a, la, b, lb, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Compares packed strings in `a` and `b` with lengths `la` and `lb`
+ /// using the control in `imm8`, and return `1` if `b` did not
+ /// contain a null character and the resulting mask was zero, and `0`
+ /// otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpestra)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpestri, imm8 = 0))]
+ #[rustc_args_required_const(4)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpestra(a: __m128i, la: i32, b: __m128i, lb: i32, imm8: i32) -> i32 {
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+     macro_rules! call {
+         ($imm8:expr) => {
+             pcmpestria128(a, la, b, lb, $imm8)
+         };
+     }
+     constify_imm8!(imm8, call)
+ }
+ 
+ /// Starting with the initial value in `crc`, return the accumulated
+ /// CRC32 value for unsigned 8-bit integer `v`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_crc32_u8)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(crc32))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_crc32_u8(crc: u32, v: u8) -> u32 {
+     crc32_32_8(crc, v)
+ }
+ 
+ /// Starting with the initial value in `crc`, return the accumulated
+ /// CRC32 value for unsigned 16-bit integer `v`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_crc32_u16)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(crc32))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_crc32_u16(crc: u32, v: u16) -> u32 {
+     crc32_32_16(crc, v)
+ }
+ 
+ /// Starting with the initial value in `crc`, return the accumulated
+ /// CRC32 value for unsigned 32-bit integer `v`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_crc32_u32)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(crc32))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_crc32_u32(crc: u32, v: u32) -> u32 {
+     crc32_32_32(crc, v)
+ }
+ 
+ /// Compares packed 64-bit integers in `a` and `b` for greater-than,
+ /// return the results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(pcmpgtq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cmpgt_epi64(a: __m128i, b: __m128i) -> __m128i {
+     transmute(simd_gt::<_, i64x2>(a.as_i64x2(), b.as_i64x2()))
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     // SSE 4.2 string and text comparison ops
+     #[link_name = "llvm.x86.sse42.pcmpestrm128"]
+     fn pcmpestrm128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> u8x16;
+     #[link_name = "llvm.x86.sse42.pcmpestri128"]
+     fn pcmpestri128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpestriz128"]
+     fn pcmpestriz128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpestric128"]
+     fn pcmpestric128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpestris128"]
+     fn pcmpestris128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpestrio128"]
+     fn pcmpestrio128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpestria128"]
+     fn pcmpestria128(a: i8x16, la: i32, b: i8x16, lb: i32, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpistrm128"]
+     fn pcmpistrm128(a: i8x16, b: i8x16, imm8: i8) -> i8x16;
+     #[link_name = "llvm.x86.sse42.pcmpistri128"]
+     fn pcmpistri128(a: i8x16, b: i8x16, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpistriz128"]
+     fn pcmpistriz128(a: i8x16, b: i8x16, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpistric128"]
+     fn pcmpistric128(a: i8x16, b: i8x16, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpistris128"]
+     fn pcmpistris128(a: i8x16, b: i8x16, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpistrio128"]
+     fn pcmpistrio128(a: i8x16, b: i8x16, imm8: i8) -> i32;
+     #[link_name = "llvm.x86.sse42.pcmpistria128"]
+     fn pcmpistria128(a: i8x16, b: i8x16, imm8: i8) -> i32;
+     // SSE 4.2 CRC instructions
+     #[link_name = "llvm.x86.sse42.crc32.32.8"]
+     fn crc32_32_8(crc: u32, v: u8) -> u32;
+     #[link_name = "llvm.x86.sse42.crc32.32.16"]
+     fn crc32_32_16(crc: u32, v: u16) -> u32;
+     #[link_name = "llvm.x86.sse42.crc32.32.32"]
+     fn crc32_32_32(crc: u32, v: u32) -> u32;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+     use std::ptr;
+ 
+     // Currently one cannot `load` a &[u8] that is is less than 16
+     // in length. This makes loading strings less than 16 in length
+     // a bit difficult. Rather than `load` and mutate the __m128i,
+     // it is easier to memcpy the given string to a local slice with
+     // length 16 and `load` the local slice.
+     #[target_feature(enable = "sse4.2")]
+     unsafe fn str_to_m128i(s: &[u8]) -> __m128i {
+         assert!(s.len() <= 16);
+         let slice = &mut [0u8; 16];
+         ptr::copy_nonoverlapping(
+             s.get_unchecked(0) as *const u8 as *const u8,
+             slice.get_unchecked_mut(0) as *mut u8 as *mut u8,
+             s.len(),
+         );
+         _mm_loadu_si128(slice.as_ptr() as *const _)
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistrm() {
+         let a = str_to_m128i(b"Hello! Good-Bye!");
+         let b = str_to_m128i(b"hello! good-bye!");
+         let i = _mm_cmpistrm(a, b, _SIDD_UNIT_MASK);
+         #[rustfmt::skip]
+         let res = _mm_setr_epi8(
+             0x00, !0, !0, !0, !0, !0, !0, 0x00,
+             !0, !0, !0, !0, 0x00, !0, !0, !0,
+         );
+         assert_eq_m128i(i, res);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistri() {
+         let a = str_to_m128i(b"Hello");
+         let b = str_to_m128i(b"   Hello        ");
+         let i = _mm_cmpistri(a, b, _SIDD_CMP_EQUAL_ORDERED);
+         assert_eq!(3, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistrz() {
+         let a = str_to_m128i(b"");
+         let b = str_to_m128i(b"Hello");
+         let i = _mm_cmpistrz(a, b, _SIDD_CMP_EQUAL_ORDERED);
+         assert_eq!(1, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistrc() {
+         let a = str_to_m128i(b"                ");
+         let b = str_to_m128i(b"       !        ");
+         let i = _mm_cmpistrc(a, b, _SIDD_UNIT_MASK);
+         assert_eq!(1, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistrs() {
+         let a = str_to_m128i(b"Hello");
+         let b = str_to_m128i(b"");
+         let i = _mm_cmpistrs(a, b, _SIDD_CMP_EQUAL_ORDERED);
+         assert_eq!(1, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistro() {
+         #[rustfmt::skip]
+         let a_bytes = _mm_setr_epi8(
+             0x00, 0x47, 0x00, 0x65, 0x00, 0x6c, 0x00, 0x6c,
+             0x00, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+         );
+         #[rustfmt::skip]
+         let b_bytes = _mm_setr_epi8(
+             0x00, 0x48, 0x00, 0x65, 0x00, 0x6c, 0x00, 0x6c,
+             0x00, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+         );
+         let a = a_bytes;
+         let b = b_bytes;
+         let i = _mm_cmpistro(a, b, _SIDD_UWORD_OPS | _SIDD_UNIT_MASK);
+         assert_eq!(0, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpistra() {
+         let a = str_to_m128i(b"");
+         let b = str_to_m128i(b"Hello!!!!!!!!!!!");
+         let i = _mm_cmpistra(a, b, _SIDD_UNIT_MASK);
+         assert_eq!(1, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestrm() {
+         let a = str_to_m128i(b"Hello!");
+         let b = str_to_m128i(b"Hello.");
+         let i = _mm_cmpestrm(a, 5, b, 5, _SIDD_UNIT_MASK);
+         #[rustfmt::skip]
+         let r = _mm_setr_epi8(
+             !0, !0, !0, !0, !0, 0x00, 0x00, 0x00,
+             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+         );
+         assert_eq_m128i(i, r);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestri() {
+         let a = str_to_m128i(b"bar - garbage");
+         let b = str_to_m128i(b"foobar");
+         let i = _mm_cmpestri(a, 3, b, 6, _SIDD_CMP_EQUAL_ORDERED);
+         assert_eq!(3, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestrz() {
+         let a = str_to_m128i(b"");
+         let b = str_to_m128i(b"Hello");
+         let i = _mm_cmpestrz(a, 16, b, 6, _SIDD_CMP_EQUAL_ORDERED);
+         assert_eq!(1, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestrc() {
+         let va = str_to_m128i(b"!!!!!!!!");
+         let vb = str_to_m128i(b"        ");
+         let i = _mm_cmpestrc(va, 7, vb, 7, _SIDD_UNIT_MASK);
+         assert_eq!(0, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestrs() {
+         #[rustfmt::skip]
+         let a_bytes = _mm_setr_epi8(
+             0x00, 0x48, 0x00, 0x65, 0x00, 0x6c, 0x00, 0x6c,
+             0x00, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+         );
+         let a = a_bytes;
+         let b = _mm_set1_epi8(0x00);
+         let i = _mm_cmpestrs(a, 8, b, 0, _SIDD_UWORD_OPS);
+         assert_eq!(0, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestro() {
+         let a = str_to_m128i(b"Hello");
+         let b = str_to_m128i(b"World");
+         let i = _mm_cmpestro(a, 5, b, 5, _SIDD_UBYTE_OPS);
+         assert_eq!(0, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpestra() {
+         let a = str_to_m128i(b"Cannot match a");
+         let b = str_to_m128i(b"Null after 14");
+         let i = _mm_cmpestra(a, 14, b, 16, _SIDD_CMP_EQUAL_EACH | _SIDD_UNIT_MASK);
+         assert_eq!(1, i);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_crc32_u8() {
+         let crc = 0x2aa1e72b;
+         let v = 0x2a;
+         let i = _mm_crc32_u8(crc, v);
+         assert_eq!(i, 0xf24122e4);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_crc32_u16() {
+         let crc = 0x8ecec3b5;
+         let v = 0x22b;
+         let i = _mm_crc32_u16(crc, v);
+         assert_eq!(i, 0x13bb2fb);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_crc32_u32() {
+         let crc = 0xae2912c8;
+         let v = 0x845fed;
+         let i = _mm_crc32_u32(crc, v);
+         assert_eq!(i, 0xffae2ed1);
+     }
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_cmpgt_epi64() {
+         let a = _mm_setr_epi64x(0, 0x2a);
+         let b = _mm_set1_epi64x(0x00);
+         let i = _mm_cmpgt_epi64(a, b);
+         assert_eq_m128i(i, _mm_setr_epi64x(0x00, 0xffffffffffffffffu64 as i64));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse4a.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse4a.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse4a.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/sse4a.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,164 ----
+ //! `i686`'s Streaming SIMD Extensions 4a (`SSE4a`)
+ 
+ use crate::{
+     core_arch::{simd::*, x86::*},
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse4a.extrq"]
+     fn extrq(x: i64x2, y: i8x16) -> i64x2;
+     #[link_name = "llvm.x86.sse4a.insertq"]
+     fn insertq(x: i64x2, y: i64x2) -> i64x2;
+     #[link_name = "llvm.x86.sse4a.movnt.sd"]
+     fn movntsd(x: *mut f64, y: __m128d);
+     #[link_name = "llvm.x86.sse4a.movnt.ss"]
+     fn movntss(x: *mut f32, y: __m128);
+ }
+ 
+ // FIXME(blocked on #248): _mm_extracti_si64(x, len, idx) // EXTRQ
+ // FIXME(blocked on #248): _mm_inserti_si64(x, y, len, idx) // INSERTQ
+ 
+ /// Extracts the bit range specified by `y` from the lower 64 bits of `x`.
+ ///
+ /// The `[13:8]` bits of `y` specify the index of the bit-range to extract. The
+ /// `[5:0]` bits of `y` specify the length of the bit-range to extract. All
+ /// other bits are ignored.
+ ///
+ /// If the length is zero, it is interpreted as `64`. If the length and index
+ /// are zero, the lower 64 bits of `x` are extracted.
+ ///
+ /// If `length == 0 && index > 0` or `lenght + index > 64` the result is
+ /// undefined.
+ #[inline]
+ #[target_feature(enable = "sse4a")]
+ #[cfg_attr(test, assert_instr(extrq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_extract_si64(x: __m128i, y: __m128i) -> __m128i {
+     transmute(extrq(x.as_i64x2(), y.as_i8x16()))
+ }
+ 
+ /// Inserts the `[length:0]` bits of `y` into `x` at `index`.
+ ///
+ /// The bits of `y`:
+ ///
+ /// - `[69:64]` specify the `length`,
+ /// - `[77:72]` specify the index.
+ ///
+ /// If the `length` is zero it is interpreted as `64`. If `index + length > 64`
+ /// or `index > 0 && length == 0` the result is undefined.
+ #[inline]
+ #[target_feature(enable = "sse4a")]
+ #[cfg_attr(test, assert_instr(insertq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_insert_si64(x: __m128i, y: __m128i) -> __m128i {
+     transmute(insertq(x.as_i64x2(), y.as_i64x2()))
+ }
+ 
+ /// Non-temporal store of `a.0` into `p`.
+ ///
+ /// Writes 64-bit data to a memory location without polluting the caches.
+ #[inline]
+ #[target_feature(enable = "sse4a")]
+ #[cfg_attr(test, assert_instr(movntsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_stream_sd(p: *mut f64, a: __m128d) {
+     movntsd(p, a);
+ }
+ 
+ /// Non-temporal store of `a.0` into `p`.
+ ///
+ /// Writes 32-bit data to a memory location without polluting the caches.
+ #[inline]
+ #[target_feature(enable = "sse4a")]
+ #[cfg_attr(test, assert_instr(movntss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_stream_ss(p: *mut f32, a: __m128) {
+     movntss(p, a);
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::*;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse4a")]
+     unsafe fn test_mm_extract_si64() {
+         let b = 0b0110_0000_0000_i64;
+         //        ^^^^ bit range extracted
+         let x = _mm_setr_epi64x(b, 0);
+         let v = 0b001000___00___000100_i64;
+         //        ^idx: 2^3 = 8 ^length = 2^2 = 4
+         let y = _mm_setr_epi64x(v, 0);
+         let e = _mm_setr_epi64x(0b0110_i64, 0);
+         let r = _mm_extract_si64(x, y);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "sse4a")]
+     unsafe fn test_mm_insert_si64() {
+         let i = 0b0110_i64;
+         //        ^^^^ bit range inserted
+         let z = 0b1010_1010_1010i64;
+         //        ^^^^ bit range replaced
+         let e = 0b0110_1010_1010i64;
+         //        ^^^^ replaced 1010 with 0110
+         let x = _mm_setr_epi64x(z, 0);
+         let expected = _mm_setr_epi64x(e, 0);
+         let v = 0b001000___00___000100_i64;
+         //        ^idx: 2^3 = 8 ^length = 2^2 = 4
+         let y = _mm_setr_epi64x(i, v);
+         let r = _mm_insert_si64(x, y);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[repr(align(16))]
+     struct MemoryF64 {
+         data: [f64; 2],
+     }
+ 
+     #[simd_test(enable = "sse4a")]
+     unsafe fn test_mm_stream_sd() {
+         let mut mem = MemoryF64 {
+             data: [1.0_f64, 2.0],
+         };
+         {
+             let vals = &mut mem.data;
+             let d = vals.as_mut_ptr();
+ 
+             let x = _mm_setr_pd(3.0, 4.0);
+ 
+             _mm_stream_sd(d, x);
+         }
+         assert_eq!(mem.data[0], 3.0);
+         assert_eq!(mem.data[1], 2.0);
+     }
+ 
+     #[repr(align(16))]
+     struct MemoryF32 {
+         data: [f32; 4],
+     }
+ 
+     #[simd_test(enable = "sse4a")]
+     unsafe fn test_mm_stream_ss() {
+         let mut mem = MemoryF32 {
+             data: [1.0_f32, 2.0, 3.0, 4.0],
+         };
+         {
+             let vals = &mut mem.data;
+             let d = vals.as_mut_ptr();
+ 
+             let x = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+ 
+             _mm_stream_ss(d, x);
+         }
+         assert_eq!(mem.data[0], 5.0);
+         assert_eq!(mem.data[1], 2.0);
+         assert_eq!(mem.data[2], 3.0);
+         assert_eq!(mem.data[3], 4.0);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,553 ----
+ //! Supplemental Streaming SIMD Extensions 3 (SSSE3)
+ 
+ use crate::{
+     core_arch::{simd::*, simd_llvm::*, x86::*},
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Computes the absolute value of packed 8-bit signed integers in `a` and
+ /// return the unsigned results.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_epi8)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(pabsb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_abs_epi8(a: __m128i) -> __m128i {
+     transmute(pabsb128(a.as_i8x16()))
+ }
+ 
+ /// Computes the absolute value of each of the packed 16-bit signed integers in
+ /// `a` and
+ /// return the 16-bit unsigned integer
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(pabsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_abs_epi16(a: __m128i) -> __m128i {
+     transmute(pabsw128(a.as_i16x8()))
+ }
+ 
+ /// Computes the absolute value of each of the packed 32-bit signed integers in
+ /// `a` and
+ /// return the 32-bit unsigned integer
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_epi32)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(pabsd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_abs_epi32(a: __m128i) -> __m128i {
+     transmute(pabsd128(a.as_i32x4()))
+ }
+ 
+ /// Shuffles bytes from `a` according to the content of `b`.
+ ///
+ /// The last 4 bits of each byte of `b` are used as addresses
+ /// into the 16 bytes of `a`.
+ ///
+ /// In addition, if the highest significant bit of a byte of `b`
+ /// is set, the respective destination byte is set to 0.
+ ///
+ /// Picturing `a` and `b` as `[u8; 16]`, `_mm_shuffle_epi8` is
+ /// logically equivalent to:
+ ///
+ /// ```
+ /// fn mm_shuffle_epi8(a: [u8; 16], b: [u8; 16]) -> [u8; 16] {
+ ///     let mut r = [0u8; 16];
+ ///     for i in 0..16 {
+ ///         // if the most significant bit of b is set,
+ ///         // then the destination byte is set to 0.
+ ///         if b[i] & 0x80 == 0u8 {
+ ///             r[i] = a[(b[i] % 16) as usize];
+ ///         }
+ ///     }
+ ///     r
+ /// }
+ /// ```
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_epi8)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(pshufb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_shuffle_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pshufb128(a.as_u8x16(), b.as_u8x16()))
+ }
+ 
+ /// Concatenate 16-byte blocks in `a` and `b` into a 32-byte temporary result,
+ /// shift the result right by `n` bytes, and returns the low 16 bytes.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_alignr_epi8)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(palignr, n = 15))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_alignr_epi8(a: __m128i, b: __m128i, n: i32) -> __m128i {
+     let n = n as u32;
+     // If palignr is shifting the pair of vectors more than the size of two
+     // lanes, emit zero.
+     if n > 32 {
+         return _mm_set1_epi8(0);
+     }
+     // If palignr is shifting the pair of input vectors more than one lane,
+     // but less than two lanes, convert to shifting in zeroes.
+     let (a, b, n) = if n > 16 {
+         (_mm_set1_epi8(0), a, n - 16)
+     } else {
+         (a, b, n)
+     };
+     let a = a.as_i8x16();
+     let b = b.as_i8x16();
+ 
+     macro_rules! shuffle {
+         ($shift:expr) => {
+             simd_shuffle16(
+                 b,
+                 a,
+                 [
+                     0 + $shift,
+                     1 + $shift,
+                     2 + $shift,
+                     3 + $shift,
+                     4 + $shift,
+                     5 + $shift,
+                     6 + $shift,
+                     7 + $shift,
+                     8 + $shift,
+                     9 + $shift,
+                     10 + $shift,
+                     11 + $shift,
+                     12 + $shift,
+                     13 + $shift,
+                     14 + $shift,
+                     15 + $shift,
+                 ],
+             )
+         };
+     }
+     let r: i8x16 = match n {
+         0 => shuffle!(0),
+         1 => shuffle!(1),
+         2 => shuffle!(2),
+         3 => shuffle!(3),
+         4 => shuffle!(4),
+         5 => shuffle!(5),
+         6 => shuffle!(6),
+         7 => shuffle!(7),
+         8 => shuffle!(8),
+         9 => shuffle!(9),
+         10 => shuffle!(10),
+         11 => shuffle!(11),
+         12 => shuffle!(12),
+         13 => shuffle!(13),
+         14 => shuffle!(14),
+         15 => shuffle!(15),
+         _ => shuffle!(16),
+     };
+     transmute(r)
+ }
+ 
+ /// Horizontally adds the adjacent pairs of values contained in 2 packed
+ /// 128-bit vectors of `[8 x i16]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hadd_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(phaddw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(phaddw128(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Horizontally adds the adjacent pairs of values contained in 2 packed
+ /// 128-bit vectors of `[8 x i16]`. Positive sums greater than 7FFFh are
+ /// saturated to 7FFFh. Negative sums less than 8000h are saturated to 8000h.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hadds_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(phaddsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(phaddsw128(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Horizontally adds the adjacent pairs of values contained in 2 packed
+ /// 128-bit vectors of `[4 x i32]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hadd_epi32)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(phaddd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hadd_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(phaddd128(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Horizontally subtract the adjacent pairs of values contained in 2
+ /// packed 128-bit vectors of `[8 x i16]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hsub_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(phsubw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(phsubw128(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Horizontally subtract the adjacent pairs of values contained in 2
+ /// packed 128-bit vectors of `[8 x i16]`. Positive differences greater than
+ /// 7FFFh are saturated to 7FFFh. Negative differences less than 8000h are
+ /// saturated to 8000h.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hsubs_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(phsubsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(phsubsw128(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Horizontally subtract the adjacent pairs of values contained in 2
+ /// packed 128-bit vectors of `[4 x i32]`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_hsub_epi32)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(phsubd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_hsub_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(phsubd128(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ /// Multiplies corresponding pairs of packed 8-bit unsigned integer
+ /// values contained in the first source operand and packed 8-bit signed
+ /// integer values contained in the second source operand, add pairs of
+ /// contiguous products with signed saturation, and writes the 16-bit sums to
+ /// the corresponding bits in the destination.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maddubs_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(pmaddubsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_maddubs_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmaddubsw128(a.as_u8x16(), b.as_i8x16()))
+ }
+ 
+ /// Multiplies packed 16-bit signed integer values, truncate the 32-bit
+ /// product to the 18 most significant bits by right-shifting, round the
+ /// truncated value by adding 1, and write bits `[16:1]` to the destination.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mulhrs_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(pmulhrsw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_mulhrs_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(pmulhrsw128(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Negates packed 8-bit integers in `a` when the corresponding signed 8-bit
+ /// integer in `b` is negative, and returns the result.
+ /// Elements in result are zeroed out when the corresponding element in `b`
+ /// is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sign_epi8)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(psignb))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sign_epi8(a: __m128i, b: __m128i) -> __m128i {
+     transmute(psignb128(a.as_i8x16(), b.as_i8x16()))
+ }
+ 
+ /// Negates packed 16-bit integers in `a` when the corresponding signed 16-bit
+ /// integer in `b` is negative, and returns the results.
+ /// Elements in result are zeroed out when the corresponding element in `b`
+ /// is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sign_epi16)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(psignw))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sign_epi16(a: __m128i, b: __m128i) -> __m128i {
+     transmute(psignw128(a.as_i16x8(), b.as_i16x8()))
+ }
+ 
+ /// Negates packed 32-bit integers in `a` when the corresponding signed 32-bit
+ /// integer in `b` is negative, and returns the results.
+ /// Element in result are zeroed out when the corresponding element in `b`
+ /// is zero.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sign_epi32)
+ #[inline]
+ #[target_feature(enable = "ssse3")]
+ #[cfg_attr(test, assert_instr(psignd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_sign_epi32(a: __m128i, b: __m128i) -> __m128i {
+     transmute(psignd128(a.as_i32x4(), b.as_i32x4()))
+ }
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.ssse3.pabs.b.128"]
+     fn pabsb128(a: i8x16) -> u8x16;
+ 
+     #[link_name = "llvm.x86.ssse3.pabs.w.128"]
+     fn pabsw128(a: i16x8) -> u16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.pabs.d.128"]
+     fn pabsd128(a: i32x4) -> u32x4;
+ 
+     #[link_name = "llvm.x86.ssse3.pshuf.b.128"]
+     fn pshufb128(a: u8x16, b: u8x16) -> u8x16;
+ 
+     #[link_name = "llvm.x86.ssse3.phadd.w.128"]
+     fn phaddw128(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.phadd.sw.128"]
+     fn phaddsw128(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.phadd.d.128"]
+     fn phaddd128(a: i32x4, b: i32x4) -> i32x4;
+ 
+     #[link_name = "llvm.x86.ssse3.phsub.w.128"]
+     fn phsubw128(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.phsub.sw.128"]
+     fn phsubsw128(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.phsub.d.128"]
+     fn phsubd128(a: i32x4, b: i32x4) -> i32x4;
+ 
+     #[link_name = "llvm.x86.ssse3.pmadd.ub.sw.128"]
+     fn pmaddubsw128(a: u8x16, b: i8x16) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.pmul.hr.sw.128"]
+     fn pmulhrsw128(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.psign.b.128"]
+     fn psignb128(a: i8x16, b: i8x16) -> i8x16;
+ 
+     #[link_name = "llvm.x86.ssse3.psign.w.128"]
+     fn psignw128(a: i16x8, b: i16x8) -> i16x8;
+ 
+     #[link_name = "llvm.x86.ssse3.psign.d.128"]
+     fn psignd128(a: i32x4, b: i32x4) -> i32x4;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_abs_epi8() {
+         let r = _mm_abs_epi8(_mm_set1_epi8(-5));
+         assert_eq_m128i(r, _mm_set1_epi8(5));
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_abs_epi16() {
+         let r = _mm_abs_epi16(_mm_set1_epi16(-5));
+         assert_eq_m128i(r, _mm_set1_epi16(5));
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_abs_epi32() {
+         let r = _mm_abs_epi32(_mm_set1_epi32(-5));
+         assert_eq_m128i(r, _mm_set1_epi32(5));
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_shuffle_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             4, 128_u8 as i8, 4, 3,
+             24, 12, 6, 19,
+             12, 5, 5, 10,
+             4, 1, 8, 0,
+         );
+         let expected = _mm_setr_epi8(5, 0, 5, 4, 9, 13, 7, 4, 13, 6, 6, 11, 5, 2, 9, 1);
+         let r = _mm_shuffle_epi8(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_alignr_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             4, 63, 4, 3,
+             24, 12, 6, 19,
+             12, 5, 5, 10,
+             4, 1, 8, 0,
+         );
+         let r = _mm_alignr_epi8(a, b, 33);
+         assert_eq_m128i(r, _mm_set1_epi8(0));
+ 
+         let r = _mm_alignr_epi8(a, b, 17);
+         #[rustfmt::skip]
+         let expected = _mm_setr_epi8(
+             2, 3, 4, 5, 6, 7, 8, 9,
+             10, 11, 12, 13, 14, 15, 16, 0,
+         );
+         assert_eq_m128i(r, expected);
+ 
+         let r = _mm_alignr_epi8(a, b, 16);
+         assert_eq_m128i(r, a);
+ 
+         let r = _mm_alignr_epi8(a, b, 15);
+         #[rustfmt::skip]
+         let expected = _mm_setr_epi8(
+             0, 1, 2, 3, 4, 5, 6, 7,
+             8, 9, 10, 11, 12, 13, 14, 15,
+         );
+         assert_eq_m128i(r, expected);
+ 
+         let r = _mm_alignr_epi8(a, b, 0);
+         assert_eq_m128i(r, b);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_hadd_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm_setr_epi16(4, 128, 4, 3, 24, 12, 6, 19);
+         let expected = _mm_setr_epi16(3, 7, 11, 15, 132, 7, 36, 25);
+         let r = _mm_hadd_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_hadds_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm_setr_epi16(4, 128, 4, 3, 32767, 1, -32768, -1);
+         let expected = _mm_setr_epi16(3, 7, 11, 15, 132, 7, 32767, -32768);
+         let r = _mm_hadds_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_hadd_epi32() {
+         let a = _mm_setr_epi32(1, 2, 3, 4);
+         let b = _mm_setr_epi32(4, 128, 4, 3);
+         let expected = _mm_setr_epi32(3, 7, 132, 7);
+         let r = _mm_hadd_epi32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_hsub_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm_setr_epi16(4, 128, 4, 3, 24, 12, 6, 19);
+         let expected = _mm_setr_epi16(-1, -1, -1, -1, -124, 1, 12, -13);
+         let r = _mm_hsub_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_hsubs_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm_setr_epi16(4, 128, 4, 3, 32767, -1, -32768, 1);
+         let expected = _mm_setr_epi16(-1, -1, -1, -1, -124, 1, 32767, -32768);
+         let r = _mm_hsubs_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_hsub_epi32() {
+         let a = _mm_setr_epi32(1, 2, 3, 4);
+         let b = _mm_setr_epi32(4, 128, 4, 3);
+         let expected = _mm_setr_epi32(-1, -1, -124, 1);
+         let r = _mm_hsub_epi32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_maddubs_epi16() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, 14, 15, 16,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             4, 63, 4, 3,
+             24, 12, 6, 19,
+             12, 5, 5, 10,
+             4, 1, 8, 0,
+         );
+         let expected = _mm_setr_epi16(130, 24, 192, 194, 158, 175, 66, 120);
+         let r = _mm_maddubs_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_mulhrs_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm_setr_epi16(4, 128, 4, 3, 32767, -1, -32768, 1);
+         let expected = _mm_setr_epi16(0, 0, 0, 0, 5, 0, -7, 0);
+         let r = _mm_mulhrs_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_sign_epi8() {
+         #[rustfmt::skip]
+         let a = _mm_setr_epi8(
+             1, 2, 3, 4, 5, 6, 7, 8,
+             9, 10, 11, 12, 13, -14, -15, 16,
+         );
+         #[rustfmt::skip]
+         let b = _mm_setr_epi8(
+             4, 63, -4, 3, 24, 12, -6, -19,
+             12, 5, -5, 10, 4, 1, -8, 0,
+         );
+         #[rustfmt::skip]
+         let expected = _mm_setr_epi8(
+             1, 2, -3, 4, 5, 6, -7, -8,
+             9, 10, -11, 12, 13, -14, 15, 0,
+         );
+         let r = _mm_sign_epi8(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_sign_epi16() {
+         let a = _mm_setr_epi16(1, 2, 3, 4, -5, -6, 7, 8);
+         let b = _mm_setr_epi16(4, 128, 0, 3, 1, -1, -2, 1);
+         let expected = _mm_setr_epi16(1, 2, 0, 4, -5, 6, -7, 8);
+         let r = _mm_sign_epi16(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ 
+     #[simd_test(enable = "ssse3")]
+     unsafe fn test_mm_sign_epi32() {
+         let a = _mm_setr_epi32(-1, 2, 3, 4);
+         let b = _mm_setr_epi32(1, -1, 1, 0);
+         let expected = _mm_setr_epi32(-1, -2, 3, 0);
+         let r = _mm_sign_epi32(a, b);
+         assert_eq_m128i(r, expected);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,460 ----
+ //! Trailing Bit Manipulation (TBM) instruction set.
+ //!
+ //! The reference is [AMD64 Architecture Programmer's Manual, Volume 3:
+ //! General-Purpose and System Instructions][amd64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the available
+ //! instructions.
+ //!
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wikipedia_bmi]:
+ //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ // FIXME(blocked on #248)
+ // TODO: LLVM-CODEGEN ERROR: LLVM ERROR: Cannot select:
+ // intrinsic %llvm.x86.tbm.bextri.u32
+ /*
+ #[allow(dead_code)]
+ extern "C" {
+     #[link_name="llvm.x86.tbm.bextri.u32"]
+     fn x86_tbm_bextri_u32(a: u32, y: u32) -> u32;
+     #[link_name="llvm.x86.tbm.bextri.u64"]
+     fn x86_tbm_bextri_u64(x: u64, y: u64) -> u64;
+ }
+ 
+ /// Extracts bits in range [`start`, `start` + `length`) from `a` into
+ /// the least significant bits of the result.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ pub fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
+     _bextr2_u32(a, (start & 0xffu32) | ((len & 0xffu32) << 8u32))
+ }
+ 
+ /// Extracts bits in range [`start`, `start` + `length`) from `a` into
+ /// the least significant bits of the result.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ pub fn _bextr_u64(a: u64, start: u64, len: u64) -> u64 {
+     _bextr2_u64(a, (start & 0xffu64) | ((len & 0xffu64) << 8u64))
+ }
+ 
+ /// Extracts bits of `a` specified by `control` into
+ /// the least significant bits of the result.
+ ///
+ /// Bits `[7,0]` of `control` specify the index to the first bit in the range to
+ /// be extracted, and bits `[15,8]` specify the length of the range.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ pub fn _bextr2_u32(a: u32, control: u32) -> u32 {
+     unsafe { x86_tbm_bextri_u32(a, control) }
+ }
+ 
+ /// Extracts bits of `a` specified by `control` into
+ /// the least significant bits of the result.
+ ///
+ /// Bits `[7,0]` of `control` specify the index to the first bit in the range to
+ /// be extracted, and bits `[15,8]` specify the length of the range.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ pub fn _bextr2_u64(a: u64, control: u64) -> u64 {
+     unsafe { x86_tbm_bextri_u64(a, control) }
+ }
+ */
+ 
+ /// Clears all bits below the least significant zero bit of `x`.
+ ///
+ /// If there is no zero bit in `x`, it returns zero.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcfill))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcfill_u32(x: u32) -> u32 {
+     x & (x.wrapping_add(1))
+ }
+ 
+ /// Clears all bits below the least significant zero bit of `x`.
+ ///
+ /// If there is no zero bit in `x`, it returns zero.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcfill))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcfill_u64(x: u64) -> u64 {
+     x & (x.wrapping_add(1))
+ }
+ 
+ /// Sets all bits of `x` to 1 except for the least significant zero bit.
+ ///
+ /// If there is no zero bit in `x`, it sets all bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blci))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blci_u32(x: u32) -> u32 {
+     x | !(x.wrapping_add(1))
+ }
+ 
+ /// Sets all bits of `x` to 1 except for the least significant zero bit.
+ ///
+ /// If there is no zero bit in `x`, it sets all bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blci))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blci_u64(x: u64) -> u64 {
+     x | !(x.wrapping_add(1))
+ }
+ 
+ /// Sets the least significant zero bit of `x` and clears all other bits.
+ ///
+ /// If there is no zero bit in `x`, it returns zero.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcic))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcic_u32(x: u32) -> u32 {
+     !x & (x.wrapping_add(1))
+ }
+ 
+ /// Sets the least significant zero bit of `x` and clears all other bits.
+ ///
+ /// If there is no zero bit in `x`, it returns zero.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcic))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcic_u64(x: u64) -> u64 {
+     !x & (x.wrapping_add(1))
+ }
+ 
+ /// Sets the least significant zero bit of `x` and clears all bits above
+ /// that bit.
+ ///
+ /// If there is no zero bit in `x`, it sets all the bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcmsk))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcmsk_u32(x: u32) -> u32 {
+     x ^ (x.wrapping_add(1))
+ }
+ 
+ /// Sets the least significant zero bit of `x` and clears all bits above
+ /// that bit.
+ ///
+ /// If there is no zero bit in `x`, it sets all the bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcmsk))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcmsk_u64(x: u64) -> u64 {
+     x ^ (x.wrapping_add(1))
+ }
+ 
+ /// Sets the least significant zero bit of `x`.
+ ///
+ /// If there is no zero bit in `x`, it returns `x`.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcs))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcs_u32(x: u32) -> u32 {
+     x | (x.wrapping_add(1))
+ }
+ 
+ /// Sets the least significant zero bit of `x`.
+ ///
+ /// If there is no zero bit in `x`, it returns `x`.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blcs))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blcs_u64(x: u64) -> u64 {
+     x | x.wrapping_add(1)
+ }
+ 
+ /// Sets all bits of `x` below the least significant one.
+ ///
+ /// If there is no set bit in `x`, it sets all the bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blsfill))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsfill_u32(x: u32) -> u32 {
+     x | (x.wrapping_sub(1))
+ }
+ 
+ /// Sets all bits of `x` below the least significant one.
+ ///
+ /// If there is no set bit in `x`, it sets all the bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blsfill))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsfill_u64(x: u64) -> u64 {
+     x | (x.wrapping_sub(1))
+ }
+ 
+ /// Clears least significant bit and sets all other bits.
+ ///
+ /// If there is no set bit in `x`, it sets all the bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blsic))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsic_u32(x: u32) -> u32 {
+     !x | (x.wrapping_sub(1))
+ }
+ 
+ /// Clears least significant bit and sets all other bits.
+ ///
+ /// If there is no set bit in `x`, it sets all the bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(blsic))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsic_u64(x: u64) -> u64 {
+     !x | (x.wrapping_sub(1))
+ }
+ 
+ /// Clears all bits below the least significant zero of `x` and sets all other
+ /// bits.
+ ///
+ /// If the least significant bit of `x` is `0`, it sets all bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(t1mskc))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _t1mskc_u32(x: u32) -> u32 {
+     !x | (x.wrapping_add(1))
+ }
+ 
+ /// Clears all bits below the least significant zero of `x` and sets all other
+ /// bits.
+ ///
+ /// If the least significant bit of `x` is `0`, it sets all bits.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(t1mskc))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _t1mskc_u64(x: u64) -> u64 {
+     !x | (x.wrapping_add(1))
+ }
+ 
+ /// Sets all bits below the least significant one of `x` and clears all other
+ /// bits.
+ ///
+ /// If the least significant bit of `x` is 1, it returns zero.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(tzmsk))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _tzmsk_u32(x: u32) -> u32 {
+     !x & (x.wrapping_sub(1))
+ }
+ 
+ /// Sets all bits below the least significant one of `x` and clears all other
+ /// bits.
+ ///
+ /// If the least significant bit of `x` is 1, it returns zero.
+ #[inline]
+ #[target_feature(enable = "tbm")]
+ #[cfg_attr(test, assert_instr(tzmsk))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _tzmsk_u64(x: u64) -> u64 {
+     !x & (x.wrapping_sub(1))
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     /*
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_bextr_u32() {
+         assert_eq!(_bextr_u32(0b0101_0000u32, 4, 4), 0b0000_0101u32);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_bextr_u64() {
+         assert_eq!(_bextr_u64(0b0101_0000u64, 4, 4), 0b0000_0101u64);
+     }
+     */
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blcfill_u32() {
+         assert_eq!(_blcfill_u32(0b0101_0111u32), 0b0101_0000u32);
+         assert_eq!(_blcfill_u32(0b1111_1111u32), 0u32);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     unsafe fn test_blcfill_u64() {
+         assert_eq!(_blcfill_u64(0b0101_0111u64), 0b0101_0000u64);
+         assert_eq!(_blcfill_u64(0b1111_1111u64), 0u64);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blci_u32() {
+         assert_eq!(
+             _blci_u32(0b0101_0000u32),
+             0b1111_1111_1111_1111_1111_1111_1111_1110u32
+         );
+         assert_eq!(
+             _blci_u32(0b1111_1111u32),
+             0b1111_1111_1111_1111_1111_1110_1111_1111u32
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     #[rustfmt::skip]
+     unsafe fn test_blci_u64() {
+         assert_eq!(
+             _blci_u64(0b0101_0000u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1110u64
+         );
+         assert_eq!(
+             _blci_u64(0b1111_1111u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1110_1111_1111u64
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blcic_u32() {
+         assert_eq!(_blcic_u32(0b0101_0001u32), 0b0000_0010u32);
+         assert_eq!(_blcic_u32(0b1111_1111u32), 0b1_0000_0000u32);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     unsafe fn test_blcic_u64() {
+         assert_eq!(_blcic_u64(0b0101_0001u64), 0b0000_0010u64);
+         assert_eq!(_blcic_u64(0b1111_1111u64), 0b1_0000_0000u64);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blcmsk_u32() {
+         assert_eq!(_blcmsk_u32(0b0101_0001u32), 0b0000_0011u32);
+         assert_eq!(_blcmsk_u32(0b1111_1111u32), 0b1_1111_1111u32);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     unsafe fn test_blcmsk_u64() {
+         assert_eq!(_blcmsk_u64(0b0101_0001u64), 0b0000_0011u64);
+         assert_eq!(_blcmsk_u64(0b1111_1111u64), 0b1_1111_1111u64);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blcs_u32() {
+         assert_eq!(_blcs_u32(0b0101_0001u32), 0b0101_0011u32);
+         assert_eq!(_blcs_u32(0b1111_1111u32), 0b1_1111_1111u32);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     unsafe fn test_blcs_u64() {
+         assert_eq!(_blcs_u64(0b0101_0001u64), 0b0101_0011u64);
+         assert_eq!(_blcs_u64(0b1111_1111u64), 0b1_1111_1111u64);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blsfill_u32() {
+         assert_eq!(_blsfill_u32(0b0101_0100u32), 0b0101_0111u32);
+         assert_eq!(
+             _blsfill_u32(0u32),
+             0b1111_1111_1111_1111_1111_1111_1111_1111u32
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     #[rustfmt::skip]
+     unsafe fn test_blsfill_u64() {
+         assert_eq!(_blsfill_u64(0b0101_0100u64), 0b0101_0111u64);
+         assert_eq!(
+             _blsfill_u64(0u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111u64
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_blsic_u32() {
+         assert_eq!(
+             _blsic_u32(0b0101_0100u32),
+             0b1111_1111_1111_1111_1111_1111_1111_1011u32
+         );
+         assert_eq!(
+             _blsic_u32(0u32),
+             0b1111_1111_1111_1111_1111_1111_1111_1111u32
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     #[rustfmt::skip]
+     unsafe fn test_blsic_u64() {
+         assert_eq!(
+             _blsic_u64(0b0101_0100u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1011u64
+         );
+         assert_eq!(
+             _blsic_u64(0u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111u64
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_t1mskc_u32() {
+         assert_eq!(
+             _t1mskc_u32(0b0101_0111u32),
+             0b1111_1111_1111_1111_1111_1111_1111_1000u32
+         );
+         assert_eq!(
+             _t1mskc_u32(0u32),
+             0b1111_1111_1111_1111_1111_1111_1111_1111u32
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     #[rustfmt::skip]
+     unsafe fn test_t1mksc_u64() {
+         assert_eq!(
+             _t1mskc_u64(0b0101_0111u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64
+         );
+         assert_eq!(
+             _t1mskc_u64(0u64),
+             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111u64
+         );
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     unsafe fn test_tzmsk_u32() {
+         assert_eq!(_tzmsk_u32(0b0101_1000u32), 0b0000_0111u32);
+         assert_eq!(_tzmsk_u32(0b0101_1001u32), 0b0000_0000u32);
+     }
+ 
+     #[simd_test(enable = "tbm")]
+     #[cfg(not(target_arch = "x86"))]
+     unsafe fn test_tzmsk_u64() {
+         assert_eq!(_tzmsk_u64(0b0101_1000u64), 0b0000_0111u64);
+         assert_eq!(_tzmsk_u64(0b0101_1001u64), 0b0000_0000u64);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/test.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/test.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/test.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/test.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,150 ----
+ //! Utilities used in testing the x86 intrinsics
+ 
+ use crate::core_arch::x86::*;
+ 
+ #[target_feature(enable = "sse2")]
+ pub unsafe fn assert_eq_m128i(a: __m128i, b: __m128i) {
+     union A {
+         a: __m128i,
+         b: [u64; 2],
+     }
+     assert_eq!(A { a }.b, A { a: b }.b)
+ }
+ 
+ #[target_feature(enable = "sse2")]
+ pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) {
+     if _mm_movemask_pd(_mm_cmpeq_pd(a, b)) != 0b11 {
+         panic!("{:?} != {:?}", a, b);
+     }
+ }
+ 
+ #[target_feature(enable = "sse2")]
+ pub unsafe fn get_m128d(a: __m128d, idx: usize) -> f64 {
+     union A {
+         a: __m128d,
+         b: [f64; 2],
+     };
+     A { a }.b[idx]
+ }
+ 
+ #[target_feature(enable = "sse")]
+ pub unsafe fn assert_eq_m128(a: __m128, b: __m128) {
+     let r = _mm_cmpeq_ps(a, b);
+     if _mm_movemask_ps(r) != 0b1111 {
+         panic!("{:?} != {:?}", a, b);
+     }
+ }
+ 
+ #[target_feature(enable = "sse")]
+ pub unsafe fn get_m128(a: __m128, idx: usize) -> f32 {
+     union A {
+         a: __m128,
+         b: [f32; 4],
+     };
+     A { a }.b[idx]
+ }
+ 
+ // not actually an intrinsic but useful in various tests as we proted from
+ // `i64x2::new` which is backwards from `_mm_set_epi64x`
+ #[target_feature(enable = "sse2")]
+ pub unsafe fn _mm_setr_epi64x(a: i64, b: i64) -> __m128i {
+     _mm_set_epi64x(b, a)
+ }
+ 
+ #[target_feature(enable = "avx")]
+ pub unsafe fn assert_eq_m256i(a: __m256i, b: __m256i) {
+     union A {
+         a: __m256i,
+         b: [u64; 4],
+     }
+     assert_eq!(A { a }.b, A { a: b }.b)
+ }
+ 
+ #[target_feature(enable = "avx")]
+ pub unsafe fn assert_eq_m256d(a: __m256d, b: __m256d) {
+     let cmp = _mm256_cmp_pd(a, b, _CMP_EQ_OQ);
+     if _mm256_movemask_pd(cmp) != 0b1111 {
+         panic!("{:?} != {:?}", a, b);
+     }
+ }
+ 
+ #[target_feature(enable = "avx")]
+ pub unsafe fn get_m256d(a: __m256d, idx: usize) -> f64 {
+     union A {
+         a: __m256d,
+         b: [f64; 4],
+     };
+     A { a }.b[idx]
+ }
+ 
+ #[target_feature(enable = "avx")]
+ pub unsafe fn assert_eq_m256(a: __m256, b: __m256) {
+     let cmp = _mm256_cmp_ps(a, b, _CMP_EQ_OQ);
+     if _mm256_movemask_ps(cmp) != 0b11111111 {
+         panic!("{:?} != {:?}", a, b);
+     }
+ }
+ 
+ #[target_feature(enable = "avx")]
+ pub unsafe fn get_m256(a: __m256, idx: usize) -> f32 {
+     union A {
+         a: __m256,
+         b: [f32; 8],
+     };
+     A { a }.b[idx]
+ }
+ 
+ // These intrinsics doesn't exist on x86 b/c it requires a 64-bit register,
+ // which doesn't exist on x86!
+ #[cfg(target_arch = "x86")]
+ mod x86_polyfill {
+     use crate::core_arch::x86::*;
+ 
+     pub unsafe fn _mm_insert_epi64(a: __m128i, val: i64, idx: i32) -> __m128i {
+         union A {
+             a: __m128i,
+             b: [i64; 2],
+         };
+         let mut a = A { a };
+         a.b[idx as usize] = val;
+         a.a
+     }
+ 
+     #[target_feature(enable = "avx2")]
+     pub unsafe fn _mm256_insert_epi64(a: __m256i, val: i64, idx: i32) -> __m256i {
+         union A {
+             a: __m256i,
+             b: [i64; 4],
+         };
+         let mut a = A { a };
+         a.b[idx as usize] = val;
+         a.a
+     }
+ }
+ #[cfg(target_arch = "x86_64")]
+ mod x86_polyfill {
+     pub use crate::core_arch::x86_64::{_mm256_insert_epi64, _mm_insert_epi64};
+ }
+ pub use self::x86_polyfill::*;
+ 
+ pub unsafe fn assert_eq_m512i(a: __m512i, b: __m512i) {
+     union A {
+         a: __m512i,
+         b: [i32; 16],
+     }
+     assert_eq!(A { a }.b, A { a: b }.b)
+ }
+ 
+ pub unsafe fn assert_eq_m512(a: __m512, b: __m512) {
+     let cmp = _mm512_cmp_ps_mask(a, b, _CMP_EQ_OQ);
+     if cmp != 0b11111111_11111111 {
+         panic!("{:?} != {:?}", a, b);
+     }
+ }
+ 
+ pub unsafe fn assert_eq_m512d(a: __m512d, b: __m512d) {
+     let cmp = _mm512_cmp_pd_mask(a, b, _CMP_EQ_OQ);
+     if cmp != 0b11111111 {
+         panic!("{:?} != {:?}", a, b);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/xsave.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/xsave.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/xsave.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86/xsave.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,283 ----
+ //! `i586`'s `xsave` and `xsaveopt` target feature intrinsics
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.xsave"]
+     fn xsave(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xrstor"]
+     fn xrstor(p: *const u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsetbv"]
+     fn xsetbv(v: u32, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsaveopt"]
+     fn xsaveopt(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsavec"]
+     fn xsavec(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsaves"]
+     fn xsaves(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xrstors"]
+     fn xrstors(p: *const u8, hi: u32, lo: u32) -> ();
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory at
+ /// `mem_addr`.
+ ///
+ /// State is saved based on bits `[62:0]` in `save_mask` and XCR0.
+ /// `mem_addr` must be aligned on a 64-byte boundary.
+ ///
+ /// The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of
+ /// Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsave)
+ #[inline]
+ #[target_feature(enable = "xsave")]
+ #[cfg_attr(test, assert_instr(xsave))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsave(mem_addr: *mut u8, save_mask: u64) {
+     xsave(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial restore of the enabled processor states using
+ /// the state information stored in memory at `mem_addr`.
+ ///
+ /// State is restored based on bits `[62:0]` in `rs_mask`, `XCR0`, and
+ /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte
+ /// boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstor)
+ #[inline]
+ #[target_feature(enable = "xsave")]
+ #[cfg_attr(test, assert_instr(xrstor))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xrstor(mem_addr: *const u8, rs_mask: u64) {
+     xrstor(mem_addr, (rs_mask >> 32) as u32, rs_mask as u32);
+ }
+ 
+ /// `XFEATURE_ENABLED_MASK` for `XCR`
+ ///
+ /// This intrinsic maps to `XSETBV` instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub const _XCR_XFEATURE_ENABLED_MASK: u32 = 0;
+ 
+ /// Copies 64-bits from `val` to the extended control register (`XCR`) specified
+ /// by `a`.
+ ///
+ /// Currently only `XFEATURE_ENABLED_MASK` `XCR` is supported.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsetbv)
+ #[inline]
+ #[target_feature(enable = "xsave")]
+ #[cfg_attr(test, assert_instr(xsetbv))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsetbv(a: u32, val: u64) {
+     xsetbv(a, (val >> 32) as u32, val as u32);
+ }
+ 
+ /// Reads the contents of the extended control register `XCR`
+ /// specified in `xcr_no`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xgetbv)
+ #[inline]
+ #[target_feature(enable = "xsave")]
+ #[cfg_attr(test, assert_instr(xgetbv))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xgetbv(xcr_no: u32) -> u64 {
+     let eax: u32;
+     let edx: u32;
+     llvm_asm!("xgetbv" : "={eax}"(eax), "={edx}"(edx) : "{ecx}"(xcr_no));
+     ((edx as u64) << 32) | (eax as u64)
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory at
+ /// `mem_addr`.
+ ///
+ /// State is saved based on bits `[62:0]` in `save_mask` and `XCR0`.
+ /// `mem_addr` must be aligned on a 64-byte boundary. The hardware may optimize
+ /// the manner in which data is saved. The performance of this instruction will
+ /// be equal to or better than using the `XSAVE` instruction.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaveopt)
+ #[inline]
+ #[target_feature(enable = "xsave,xsaveopt")]
+ #[cfg_attr(test, assert_instr(xsaveopt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsaveopt(mem_addr: *mut u8, save_mask: u64) {
+     xsaveopt(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory
+ /// at `mem_addr`.
+ ///
+ /// `xsavec` differs from `xsave` in that it uses compaction and that it may
+ /// use init optimization. State is saved based on bits `[62:0]` in `save_mask`
+ /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsavec)
+ #[inline]
+ #[target_feature(enable = "xsave,xsavec")]
+ #[cfg_attr(test, assert_instr(xsavec))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsavec(mem_addr: *mut u8, save_mask: u64) {
+     xsavec(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory at
+ /// `mem_addr`
+ ///
+ /// `xsaves` differs from xsave in that it can save state components
+ /// corresponding to bits set in `IA32_XSS` `MSR` and that it may use the
+ /// modified optimization. State is saved based on bits `[62:0]` in `save_mask`
+ /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaves)
+ #[inline]
+ #[target_feature(enable = "xsave,xsaves")]
+ #[cfg_attr(test, assert_instr(xsaves))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsaves(mem_addr: *mut u8, save_mask: u64) {
+     xsaves(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial restore of the enabled processor states using the
+ /// state information stored in memory at `mem_addr`.
+ ///
+ /// `xrstors` differs from `xrstor` in that it can restore state components
+ /// corresponding to bits set in the `IA32_XSS` `MSR`; `xrstors` cannot restore
+ /// from an `xsave` area in which the extended region is in the standard form.
+ /// State is restored based on bits `[62:0]` in `rs_mask`, `XCR0`, and
+ /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte
+ /// boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstors)
+ #[inline]
+ #[target_feature(enable = "xsave,xsaves")]
+ #[cfg_attr(test, assert_instr(xrstors))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xrstors(mem_addr: *const u8, rs_mask: u64) {
+     xrstors(mem_addr, (rs_mask >> 32) as u32, rs_mask as u32);
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std::{fmt, prelude::v1::*};
+ 
+     use crate::core_arch::x86::*;
+     use stdarch_test::simd_test;
+ 
+     #[repr(align(64))]
+     struct XsaveArea {
+         // max size for 256-bit registers is 800 bytes:
+         // see https://software.intel.com/en-us/node/682996
+         // max size for 512-bit registers is 2560 bytes:
+         // FIXME: add source
+         data: [u8; 2560],
+     }
+ 
+     impl XsaveArea {
+         fn new() -> XsaveArea {
+             XsaveArea { data: [0; 2560] }
+         }
+         fn ptr(&mut self) -> *mut u8 {
+             &mut self.data[0] as *mut _ as *mut u8
+         }
+     }
+ 
+     impl PartialEq<XsaveArea> for XsaveArea {
+         fn eq(&self, other: &XsaveArea) -> bool {
+             for i in 0..self.data.len() {
+                 if self.data[i] != other.data[i] {
+                     return false;
+                 }
+             }
+             true
+         }
+     }
+ 
+     impl fmt::Debug for XsaveArea {
+         fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+             write!(f, "[")?;
+             for i in 0..self.data.len() {
+                 write!(f, "{}", self.data[i])?;
+                 if i != self.data.len() - 1 {
+                     write!(f, ", ")?;
+                 }
+             }
+             write!(f, "]")
+         }
+     }
+ 
+     // FIXME: https://github.com/rust-lang/stdarch/issues/209
+     /*
+     #[simd_test(enable = "xsave")]
+     unsafe fn xsave() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         _xsave(a.ptr(), m);
+         _xrstor(a.ptr(), m);
+         _xsave(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+     */
+ 
+     #[simd_test(enable = "xsave")]
+     unsafe fn xgetbv_xsetbv() {
+         let xcr_n: u32 = _XCR_XFEATURE_ENABLED_MASK;
+ 
+         let xcr: u64 = _xgetbv(xcr_n);
+         // FIXME: XSETBV is a privileged instruction we should only test this
+         // when running in privileged mode:
+         //
+         // _xsetbv(xcr_n, xcr);
+         let xcr_cpy: u64 = _xgetbv(xcr_n);
+         assert_eq!(xcr, xcr_cpy);
+     }
+ 
+     // FIXME: https://github.com/rust-lang/stdarch/issues/209
+     /*
+     #[simd_test(enable = "xsave,xsaveopt")]
+     unsafe fn xsaveopt() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         _xsaveopt(a.ptr(), m);
+         _xrstor(a.ptr(), m);
+         _xsaveopt(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+     */
+ 
+     // FIXME: this looks like a bug in Intel's SDE:
+     #[cfg(not(stdarch_intel_sde))]
+     #[simd_test(enable = "xsave,xsavec")]
+     unsafe fn xsavec() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         _xsavec(a.ptr(), m);
+         _xrstor(a.ptr(), m);
+         _xsavec(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+ 
+     // FIXME: https://github.com/rust-lang/stdarch/issues/209
+     /*
+     #[simd_test(enable = "xsave,xsaves")]
+     unsafe fn xsaves() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         _xsaves(a.ptr(), m);
+         _xrstors(a.ptr(), m);
+         _xsaves(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+     */
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,62 ----
+ //! Advanced Bit Manipulation (ABM) instructions
+ //!
+ //! The POPCNT and LZCNT have their own CPUID bits to indicate support.
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //! Instruction Set Reference, A-Z][intel64_ref].
+ //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ //! System Instructions][amd64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
+ //! available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wikipedia_bmi]:
+ //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Counts the leading most significant zero bits.
+ ///
+ /// When the operand is zero, it returns its size in bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_lzcnt_u64)
+ #[inline]
+ #[target_feature(enable = "lzcnt")]
+ #[cfg_attr(test, assert_instr(lzcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _lzcnt_u64(x: u64) -> u64 {
+     x.leading_zeros() as u64
+ }
+ 
+ /// Counts the bits that are set.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_popcnt64)
+ #[inline]
+ #[target_feature(enable = "popcnt")]
+ #[cfg_attr(test, assert_instr(popcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _popcnt64(x: i64) -> i32 {
+     x.count_ones() as i32
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::arch::x86_64::*;
+ 
+     #[simd_test(enable = "lzcnt")]
+     unsafe fn test_lzcnt_u64() {
+         assert_eq!(_lzcnt_u64(0b0101_1010), 57);
+     }
+ 
+     #[simd_test(enable = "popcnt")]
+     unsafe fn test_popcnt64() {
+         assert_eq!(_popcnt64(0b0101_1010), 4);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/adx.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/adx.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/adx.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/adx.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,148 ----
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "unadjusted" {
+     #[link_name = "llvm.x86.addcarry.64"]
+     fn llvm_addcarry_u64(a: u8, b: u64, c: u64) -> (u8, u64);
+     #[link_name = "llvm.x86.addcarryx.u64"]
+     fn llvm_addcarryx_u64(a: u8, b: u64, c: u64, d: *mut u8) -> u8;
+     #[link_name = "llvm.x86.subborrow.64"]
+     fn llvm_subborrow_u64(a: u8, b: u64, c: u64) -> (u8, u64);
+ }
+ 
+ /// Adds unsigned 64-bit integers `a` and `b` with unsigned 8-bit carry-in `c_in`
+ /// (carry flag), and store the unsigned 64-bit result in `out`, and the carry-out
+ /// is returned (carry or overflow flag).
+ #[inline]
+ #[cfg_attr(test, assert_instr(adc))]
+ #[stable(feature = "simd_x86_adx", since = "1.33.0")]
+ pub unsafe fn _addcarry_u64(c_in: u8, a: u64, b: u64, out: &mut u64) -> u8 {
+     let (a, b) = llvm_addcarry_u64(c_in, a, b);
+     *out = b;
+     a
+ }
+ 
+ /// Adds unsigned 64-bit integers `a` and `b` with unsigned 8-bit carry-in `c_in`
+ /// (carry or overflow flag), and store the unsigned 64-bit result in `out`, and
+ /// the carry-out is returned (carry or overflow flag).
+ #[inline]
+ #[target_feature(enable = "adx")]
+ #[cfg_attr(test, assert_instr(adc))]
+ #[stable(feature = "simd_x86_adx", since = "1.33.0")]
+ pub unsafe fn _addcarryx_u64(c_in: u8, a: u64, b: u64, out: &mut u64) -> u8 {
+     llvm_addcarryx_u64(c_in, a, b, out as *mut _ as *mut u8)
+ }
+ 
+ /// Adds unsigned 64-bit integers `a` and `b` with unsigned 8-bit carry-in `c_in`.
+ /// (carry or overflow flag), and store the unsigned 64-bit result in `out`, and
+ /// the carry-out is returned (carry or overflow flag).
+ #[inline]
+ #[cfg_attr(test, assert_instr(sbb))]
+ #[stable(feature = "simd_x86_adx", since = "1.33.0")]
+ pub unsafe fn _subborrow_u64(c_in: u8, a: u64, b: u64, out: &mut u64) -> u8 {
+     let (a, b) = llvm_subborrow_u64(c_in, a, b);
+     *out = b;
+     a
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86_64::*;
+ 
+     #[test]
+     fn test_addcarry_u64() {
+         unsafe {
+             let a = u64::MAX;
+             let mut out = 0;
+ 
+             let r = _addcarry_u64(0, a, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, 0);
+ 
+             let r = _addcarry_u64(0, a, 0, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, a);
+ 
+             let r = _addcarry_u64(1, a, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, 1);
+ 
+             let r = _addcarry_u64(1, a, 0, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, 0);
+ 
+             let r = _addcarry_u64(0, 3, 4, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 7);
+ 
+             let r = _addcarry_u64(1, 3, 4, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 8);
+         }
+     }
+ 
+     #[simd_test(enable = "adx")]
+     unsafe fn test_addcarryx_u64() {
+         let a = u64::MAX;
+         let mut out = 0;
+ 
+         let r = _addcarry_u64(0, a, 1, &mut out);
+         assert_eq!(r, 1);
+         assert_eq!(out, 0);
+ 
+         let r = _addcarry_u64(0, a, 0, &mut out);
+         assert_eq!(r, 0);
+         assert_eq!(out, a);
+ 
+         let r = _addcarry_u64(1, a, 1, &mut out);
+         assert_eq!(r, 1);
+         assert_eq!(out, 1);
+ 
+         let r = _addcarry_u64(1, a, 0, &mut out);
+         assert_eq!(r, 1);
+         assert_eq!(out, 0);
+ 
+         let r = _addcarry_u64(0, 3, 4, &mut out);
+         assert_eq!(r, 0);
+         assert_eq!(out, 7);
+ 
+         let r = _addcarry_u64(1, 3, 4, &mut out);
+         assert_eq!(r, 0);
+         assert_eq!(out, 8);
+     }
+ 
+     #[test]
+     fn test_subborrow_u64() {
+         unsafe {
+             let a = u64::MAX;
+             let mut out = 0;
+ 
+             let r = _subborrow_u64(0, 0, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, a);
+ 
+             let r = _subborrow_u64(0, 0, 0, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 0);
+ 
+             let r = _subborrow_u64(1, 0, 1, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, a - 1);
+ 
+             let r = _subborrow_u64(1, 0, 0, &mut out);
+             assert_eq!(r, 1);
+             assert_eq!(out, a);
+ 
+             let r = _subborrow_u64(0, 7, 3, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 4);
+ 
+             let r = _subborrow_u64(1, 7, 3, &mut out);
+             assert_eq!(r, 0);
+             assert_eq!(out, 3);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,53 ----
+ //! Advanced Vector Extensions (AVX)
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //! Instruction Set Reference, A-Z][intel64_ref]. - [AMD64 Architecture
+ //! Programmer's Manual, Volume 3: General-Purpose and System
+ //! Instructions][amd64_ref].
+ //!
+ //! [Wikipedia][wiki] provides a quick overview of the instructions available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
+ 
+ use crate::{
+     core_arch::{simd_llvm::*, x86::*},
+     mem::transmute,
+ };
+ 
+ /// Copies `a` to result, and insert the 64-bit integer `i` into result
+ /// at the location specified by `index`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insert_epi64)
+ #[inline]
+ #[rustc_args_required_const(2)]
+ #[target_feature(enable = "avx")]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_insert_epi64(a: __m256i, i: i64, index: i32) -> __m256i {
+     let a = a.as_i64x4();
+     match index & 3 {
+         0 => transmute(simd_insert(a, 0, i)),
+         1 => transmute(simd_insert(a, 1, i)),
+         2 => transmute(simd_insert(a, 2, i)),
+         _ => transmute(simd_insert(a, 3, i)),
+     }
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+ 
+     #[simd_test(enable = "avx")]
+     unsafe fn test_mm256_insert_epi64() {
+         let a = _mm256_setr_epi64x(1, 2, 3, 4);
+         let r = _mm256_insert_epi64(a, 0, 3);
+         let e = _mm256_setr_epi64x(1, 2, 3, 0);
+         assert_eq_m256i(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx2.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx2.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx2.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,52 ----
+ //! Advanced Vector Extensions 2 (AVX)
+ //!
+ //! AVX2 expands most AVX commands to 256-bit wide vector registers and
+ //! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
+ //!
+ //! The references are:
+ //!
+ //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ //!   Instruction Set Reference, A-Z][intel64_ref].
+ //! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ //!   System Instructions][amd64_ref].
+ //!
+ //! Wikipedia's [AVX][wiki_avx] and [FMA][wiki_fma] pages provide a quick
+ //! overview of the instructions available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ //! [wiki_avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
+ //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
+ 
+ use crate::core_arch::{simd_llvm::*, x86::*};
+ 
+ /// Extracts a 64-bit integer from `a`, selected with `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extract_epi64)
+ #[inline]
+ #[target_feature(enable = "avx2")]
+ #[rustc_args_required_const(1)]
+ // This intrinsic has no corresponding instruction.
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm256_extract_epi64(a: __m256i, imm8: i32) -> i64 {
+     let a = a.as_i64x4();
+     match imm8 & 3 {
+         0 => simd_extract(a, 0),
+         1 => simd_extract(a, 1),
+         2 => simd_extract(a, 2),
+         _ => simd_extract(a, 3),
+     }
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arch::x86_64::*;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "avx2")]
+     unsafe fn test_mm256_extract_epi64() {
+         let a = _mm256_setr_epi64x(0, 1, 2, 3);
+         let r = _mm256_extract_epi64(a, 3);
+         assert_eq!(r, 3);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,4914 ----
+ use crate::{
+     core_arch::{simd::*, x86::*},
+     mem::transmute,
+ };
+ 
+ /// Sets packed 64-bit integers in `dst` with the supplied values.
+ ///
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_set_epi64(
+     e0: i64,
+     e1: i64,
+     e2: i64,
+     e3: i64,
+     e4: i64,
+     e5: i64,
+     e6: i64,
+     e7: i64,
+ ) -> __m512i {
+     _mm512_setr_epi64(e7, e6, e5, e4, e3, e2, e1, e0)
+ }
+ 
+ /// Sets packed 64-bit integers in `dst` with the supplied values in
+ /// reverse order.
+ ///
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_epi64)
+ #[inline]
+ #[target_feature(enable = "avx512f")]
+ pub unsafe fn _mm512_setr_epi64(
+     e0: i64,
+     e1: i64,
+     e2: i64,
+     e3: i64,
+     e4: i64,
+     e5: i64,
+     e6: i64,
+     e7: i64,
+ ) -> __m512i {
+     let r = i64x8::new(e0, e1, e2, e3, e4, e5, e6, e7);
+     transmute(r)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use std;
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86::*;
+     use crate::core_arch::x86_64::*;
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_abs_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let r = _mm512_abs_epi64(a);
+         let e = _mm512_setr_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_abs_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let r = _mm512_mask_abs_epi64(a, 0, a);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_abs_epi64(a, 0b00001111, a);
+         let e = _mm512_setr_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, -100, -32);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_abs_epi64() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let r = _mm512_maskz_abs_epi64(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_abs_epi64(0b00001111, a);
+         let e = _mm512_setr_epi64(0, 1, 1, i64::MAX, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_abs_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let r = _mm512_abs_pd(a);
+         let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_abs_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let r = _mm512_mask_abs_pd(a, 0, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_abs_pd(a, 0b00001111, a);
+         let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_add_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_add_epi64(a, b);
+         let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_add_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_mask_add_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_add_epi64() {
+         #[rustfmt::skip]
+         let a = _mm512_setr_epi64(
+             0, 1, -1, i64::MAX,
+             i64::MIN, 100, -100, -32
+         );
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_maskz_add_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_add_epi64(0b00001111, a, b);
+         let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_add_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_add_pd(a, b);
+         let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_add_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_mask_add_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
+         let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_add_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_maskz_add_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_add_pd(0b00001111, a, b);
+         let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sub_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_sub_epi64(a, b);
+         let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sub_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_mask_sub_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sub_epi64() {
+         let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_maskz_sub_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
+         let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sub_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_sub_pd(a, b);
+         let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sub_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_mask_sub_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
+         let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sub_pd() {
+         let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_maskz_sub_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_sub_pd(0b00001111, a, b);
+         let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mul_epi32() {
+         let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm512_mul_epi32(a, b);
+         let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mul_epi32() {
+         let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm512_mask_mul_epi32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
+         let e = _mm512_set_epi64(
+             1 | 1 << 32,
+             1 | 1 << 32,
+             1 | 1 << 32,
+             1 | 1 << 32,
+             7,
+             5,
+             3,
+             1,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mul_epi32() {
+         let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm512_maskz_mul_epi32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mul_epu32() {
+         let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm512_mul_epu32(a, b);
+         let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mul_epu32() {
+         let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm512_mask_mul_epu32(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
+         let e = _mm512_set_epi64(
+             1 | 1 << 32,
+             1 | 1 << 32,
+             1 | 1 << 32,
+             1 | 1 << 32,
+             7,
+             5,
+             3,
+             1,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mul_epu32() {
+         let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+         let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+         let r = _mm512_maskz_mul_epu32(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mullox_epi64() {
+         let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
+         let b = _mm512_set1_epi64(2);
+         let r = _mm512_mullox_epi64(a, b);
+         let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mullox_epi64() {
+         let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
+         let b = _mm512_set1_epi64(2);
+         let r = _mm512_mask_mullox_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mul_pd() {
+         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
+         let b = _mm512_set1_pd(2.);
+         let r = _mm512_mul_pd(a, b);
+         let e = _mm512_setr_pd(
+             0.,
+             2.,
+             f64::INFINITY,
+             f64::NEG_INFINITY,
+             f64::INFINITY,
+             f64::NEG_INFINITY,
+             -200.,
+             -64.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mul_pd() {
+         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
+         let b = _mm512_set1_pd(2.);
+         let r = _mm512_mask_mul_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
+         let e = _mm512_setr_pd(
+             0.,
+             2.,
+             f64::INFINITY,
+             f64::NEG_INFINITY,
+             f64::MAX,
+             f64::MIN,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mul_pd() {
+         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
+         let b = _mm512_set1_pd(2.);
+         let r = _mm512_maskz_mul_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_mul_pd(0b00001111, a, b);
+         let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_div_pd() {
+         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
+         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
+         let r = _mm512_div_pd(a, b);
+         let e = _mm512_setr_pd(
+             0.,
+             0.5,
+             f64::INFINITY,
+             f64::NEG_INFINITY,
+             f64::INFINITY,
+             f64::NEG_INFINITY,
+             -50.,
+             -16.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_div_pd() {
+         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
+         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
+         let r = _mm512_mask_div_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
+         let e = _mm512_setr_pd(
+             0.,
+             0.5,
+             f64::INFINITY,
+             f64::NEG_INFINITY,
+             f64::MAX,
+             f64::MIN,
+             -100.,
+             -32.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_div_pd() {
+         let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
+         let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
+         let r = _mm512_maskz_div_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_div_pd(0b00001111, a, b);
+         let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_epi64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_max_epi64(a, b);
+         let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_epi64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_max_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_epi64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_max_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_max_epi64(0b00001111, a, b);
+         let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_max_pd(a, b);
+         let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_mask_max_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
+         let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_maskz_max_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_max_pd(0b00001111, a, b);
+         let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_epu64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_max_epu64(a, b);
+         let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_epu64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_max_epu64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_epu64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_max_epu64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_max_epu64(0b00001111, a, b);
+         let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_epi64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_min_epi64(a, b);
+         let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_epi64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_min_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_epi64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_min_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_min_epi64(0b00001111, a, b);
+         let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_min_pd(a, b);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_mask_min_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_maskz_min_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_min_pd(0b00001111, a, b);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_epu64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_min_epu64(a, b);
+         let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_epu64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_mask_min_epu64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
+         let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_epu64() {
+         let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
+         let r = _mm512_maskz_min_epu64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_min_epu64(0b00001111, a, b);
+         let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sqrt_pd() {
+         let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
+         let r = _mm512_sqrt_pd(a);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sqrt_pd() {
+         let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
+         let r = _mm512_mask_sqrt_pd(a, 0, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sqrt_pd() {
+         let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
+         let r = _mm512_maskz_sqrt_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_sqrt_pd(0b00001111, a);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_fmadd_pd(a, b, c);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_mask_fmadd_pd(a, 0, b, c);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_maskz_fmadd_pd(0, a, b, c);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
+         let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_fmsub_pd(a, b, c);
+         let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_mask_fmsub_pd(a, 0, b, c);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
+         let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_maskz_fmsub_pd(0, a, b, c);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
+         let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
+         let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
+         let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmaddsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_fmaddsub_pd(a, b, c);
+         let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmaddsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
+         let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmaddsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
+         let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmaddsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
+         let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
+         let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsubadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_fmsubadd_pd(a, b, c);
+         let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsubadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
+         let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsubadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
+         let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsubadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
+         let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
+         let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_fnmadd_pd(a, b, c);
+         let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
+         let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
+         let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmadd_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
+         let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
+         let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_fnmsub_pd(a, b, c);
+         let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
+         let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
+         let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmsub_pd() {
+         let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
+         let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
+         let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rcp14_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_rcp14_pd(a);
+         let e = _mm512_set1_pd(0.3333320617675781);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rcp14_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_mask_rcp14_pd(a, 0, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
+         let e = _mm512_setr_pd(
+             3.,
+             3.,
+             3.,
+             3.,
+             0.3333320617675781,
+             0.3333320617675781,
+             0.3333320617675781,
+             0.3333320617675781,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rcp14_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_maskz_rcp14_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_rcp14_pd(0b11110000, a);
+         let e = _mm512_setr_pd(
+             0.,
+             0.,
+             0.,
+             0.,
+             0.3333320617675781,
+             0.3333320617675781,
+             0.3333320617675781,
+             0.3333320617675781,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rsqrt14_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_rsqrt14_pd(a);
+         let e = _mm512_set1_pd(0.5773391723632813);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rsqrt14_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_mask_rsqrt14_pd(a, 0, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
+         let e = _mm512_setr_pd(
+             3.,
+             3.,
+             3.,
+             3.,
+             0.5773391723632813,
+             0.5773391723632813,
+             0.5773391723632813,
+             0.5773391723632813,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rsqrt14_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_maskz_rsqrt14_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
+         let e = _mm512_setr_pd(
+             0.,
+             0.,
+             0.,
+             0.,
+             0.5773391723632813,
+             0.5773391723632813,
+             0.5773391723632813,
+             0.5773391723632813,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getexp_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_getexp_pd(a);
+         let e = _mm512_set1_pd(1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getexp_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_mask_getexp_pd(a, 0, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
+         let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getexp_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_maskz_getexp_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_getexp_pd(0b11110000, a);
+         let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getmant_pd() {
+         let a = _mm512_set1_pd(10.);
+         let r = _mm512_getmant_pd(a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         let e = _mm512_set1_pd(1.25);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getmant_pd() {
+         let a = _mm512_set1_pd(10.);
+         let r = _mm512_mask_getmant_pd(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_getmant_pd(a, 0b11110000, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getmant_pd() {
+         let a = _mm512_set1_pd(10.);
+         let r = _mm512_maskz_getmant_pd(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_getmant_pd(0b11110000, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC);
+         let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtps_pd() {
+         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_cvtps_pd(a);
+         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtps_pd() {
+         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let src = _mm512_set1_pd(0.);
+         let r = _mm512_mask_cvtps_pd(src, 0, a);
+         assert_eq_m512d(r, src);
+         let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
+         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtps_pd() {
+         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_maskz_cvtps_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_cvtps_pd(0b00001111, a);
+         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtt_roundpd_epi32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_cvtt_roundpd_epi32(a, _MM_FROUND_NO_EXC);
+         let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let src = _mm256_set1_epi32(0);
+         let r = _mm512_mask_cvtt_roundpd_epi32(src, 0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m256i(r, src);
+         let r = _mm512_mask_cvtt_roundpd_epi32(src, 0b00001111, a, _MM_FROUND_NO_EXC);
+         let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_maskz_cvtt_roundpd_epi32(0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m256i(r, _mm256_setzero_si256());
+         let r = _mm512_maskz_cvtt_roundpd_epi32(0b00001111, a, _MM_FROUND_NO_EXC);
+         let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvtt_roundpd_epu32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_cvtt_roundpd_epu32(a, _MM_FROUND_NO_EXC);
+         let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let src = _mm256_set1_epi32(0);
+         let r = _mm512_mask_cvtt_roundpd_epu32(src, 0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m256i(r, src);
+         let r = _mm512_mask_cvtt_roundpd_epu32(src, 0b00001111, a, _MM_FROUND_NO_EXC);
+         let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_maskz_cvtt_roundpd_epu32(0, a, _MM_FROUND_NO_EXC);
+         assert_eq_m256i(r, _mm256_setzero_si256());
+         let r = _mm512_maskz_cvtt_roundpd_epu32(0b00001111, a, _MM_FROUND_NO_EXC);
+         let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvttpd_epi32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_cvttpd_epi32(a);
+         let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvttpd_epi32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let src = _mm256_set1_epi32(0);
+         let r = _mm512_mask_cvttpd_epi32(src, 0, a);
+         assert_eq_m256i(r, src);
+         let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
+         let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvttpd_epi32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_maskz_cvttpd_epi32(0, a);
+         assert_eq_m256i(r, _mm256_setzero_si256());
+         let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
+         let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvttpd_epu32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_cvttpd_epu32(a);
+         let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvttpd_epu32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let src = _mm256_set1_epi32(0);
+         let r = _mm512_mask_cvttpd_epu32(src, 0, a);
+         assert_eq_m256i(r, src);
+         let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
+         let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvttpd_epu32() {
+         let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_maskz_cvttpd_epu32(0, a);
+         assert_eq_m256i(r, _mm256_setzero_si256());
+         let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
+         let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_add_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
+         let b = _mm512_set1_pd(-1.);
+         let r = _mm512_add_round_pd(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
+         assert_eq_m512d(r, e);
+         let r = _mm512_add_round_pd(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_add_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
+         let b = _mm512_set1_pd(-1.);
+         let r = _mm512_mask_add_round_pd(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_add_round_pd(
+             a,
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_add_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
+         let b = _mm512_set1_pd(-1.);
+         let r = _mm512_maskz_add_round_pd(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_add_round_pd(
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sub_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_sub_round_pd(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
+         assert_eq_m512d(r, e);
+         let r = _mm512_sub_round_pd(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sub_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_mask_sub_round_pd(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_sub_round_pd(
+             a,
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sub_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let r = _mm512_maskz_sub_round_pd(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_sub_round_pd(
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mul_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
+         let b = _mm512_set1_pd(0.1);
+         let r = _mm512_mul_round_pd(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(
+             0.8,
+             0.9500000000000001,
+             1.,
+             1.1500000000000001,
+             1.2000000000000002,
+             1.35,
+             1.4000000000000001,
+             0.,
+         );
+         assert_eq_m512d(r, e);
+         let r = _mm512_mul_round_pd(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_mul_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
+         let b = _mm512_set1_pd(0.1);
+         let r = _mm512_mask_mul_round_pd(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_mul_round_pd(
+             a,
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             8.,
+             9.5,
+             10.,
+             11.5,
+             1.2000000000000002,
+             1.35,
+             1.4000000000000001,
+             0.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_mul_round_pd() {
+         let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
+         let b = _mm512_set1_pd(0.1);
+         let r = _mm512_maskz_mul_round_pd(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_mul_round_pd(
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             0.,
+             0.,
+             0.,
+             0.,
+             1.2000000000000002,
+             1.35,
+             1.4000000000000001,
+             0.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_div_round_pd() {
+         let a = _mm512_set1_pd(1.);
+         let b = _mm512_set1_pd(3.);
+         let r = _mm512_div_round_pd(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(0.3333333333333333);
+         assert_eq_m512d(r, e);
+         let r = _mm512_div_round_pd(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(0.33333333333333334);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_div_round_pd() {
+         let a = _mm512_set1_pd(1.);
+         let b = _mm512_set1_pd(3.);
+         let r = _mm512_mask_div_round_pd(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_div_round_pd(
+             a,
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             1.,
+             1.,
+             1.,
+             1.,
+             0.3333333333333333,
+             0.3333333333333333,
+             0.3333333333333333,
+             0.3333333333333333,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_div_round_pd() {
+         let a = _mm512_set1_pd(1.);
+         let b = _mm512_set1_pd(3.);
+         let r = _mm512_maskz_div_round_pd(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_div_round_pd(
+             0b11110000,
+             a,
+             b,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             0.,
+             0.,
+             0.,
+             0.,
+             0.3333333333333333,
+             0.3333333333333333,
+             0.3333333333333333,
+             0.3333333333333333,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sqrt_round_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_sqrt_round_pd(a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(1.7320508075688772);
+         assert_eq_m512d(r, e);
+         let r = _mm512_sqrt_round_pd(a, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(1.7320508075688774);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sqrt_round_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_mask_sqrt_round_pd(a, 0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_sqrt_round_pd(
+             a,
+             0b11110000,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             3.,
+             3.,
+             3.,
+             3.,
+             1.7320508075688772,
+             1.7320508075688772,
+             1.7320508075688772,
+             1.7320508075688772,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sqrt_round_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_maskz_sqrt_round_pd(0, a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_sqrt_round_pd(
+             0b11110000,
+             a,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             0.,
+             0.,
+             0.,
+             0.,
+             1.7320508075688772,
+             1.7320508075688772,
+             1.7320508075688772,
+             1.7320508075688772,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_fmadd_round_pd(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(-1.);
+         assert_eq_m512d(r, e);
+         let r = _mm512_fmadd_round_pd(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(-0.9999999999999999);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r =
+             _mm512_mask_fmadd_round_pd(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmadd_round_pd(
+             a,
+             0b00001111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r =
+             _mm512_maskz_fmadd_round_pd(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmadd_round_pd(
+             0b00001111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r =
+             _mm512_mask3_fmadd_round_pd(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmadd_round_pd(
+             a,
+             b,
+             c,
+             0b00001111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r = _mm512_fmsub_round_pd(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(-1.);
+         assert_eq_m512d(r, e);
+         let r = _mm512_fmsub_round_pd(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(-0.9999999999999999);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r =
+             _mm512_mask_fmsub_round_pd(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmsub_round_pd(
+             a,
+             0b00001111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             -1.,
+             -1.,
+             -1.,
+             -1.,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r =
+             _mm512_maskz_fmsub_round_pd(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmsub_round_pd(
+             0b00001111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r =
+             _mm512_mask3_fmsub_round_pd(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmsub_round_pd(
+             a,
+             b,
+             c,
+             0b00001111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmaddsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_fmaddsub_round_pd(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
+         assert_eq_m512d(r, e);
+         let r = _mm512_fmaddsub_round_pd(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(
+             1.,
+             -0.9999999999999999,
+             1.,
+             -0.9999999999999999,
+             1.,
+             -0.9999999999999999,
+             1.,
+             -0.9999999999999999,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmaddsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_mask_fmaddsub_round_pd(
+             a,
+             0,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmaddsub_round_pd(
+             a,
+             0b00001111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             1.,
+             -1.,
+             1.,
+             -1.,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_maskz_fmaddsub_round_pd(
+             0,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmaddsub_round_pd(
+             0b00001111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_mask3_fmaddsub_round_pd(
+             a,
+             b,
+             c,
+             0,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmaddsub_round_pd(
+             a,
+             b,
+             c,
+             0b00001111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fmsubadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_fmsubadd_round_pd(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
+         assert_eq_m512d(r, e);
+         let r = _mm512_fmsubadd_round_pd(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_setr_pd(
+             -0.9999999999999999,
+             1.,
+             -0.9999999999999999,
+             1.,
+             -0.9999999999999999,
+             1.,
+             -0.9999999999999999,
+             1.,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fmsubadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_mask_fmsubadd_round_pd(
+             a,
+             0,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fmsubadd_round_pd(
+             a,
+             0b00001111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             -1.,
+             1.,
+             -1.,
+             1.,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_maskz_fmsubadd_round_pd(
+             0,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fmsubadd_round_pd(
+             0b00001111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_mask3_fmsubadd_round_pd(
+             a,
+             b,
+             c,
+             0,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fmsubadd_round_pd(
+             a,
+             b,
+             c,
+             0b00001111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r = _mm512_fnmadd_round_pd(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(1.);
+         assert_eq_m512d(r, e);
+         let r = _mm512_fnmadd_round_pd(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(0.9999999999999999);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r =
+             _mm512_mask_fnmadd_round_pd(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fnmadd_round_pd(
+             a,
+             0b00001111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             1.,
+             1.,
+             1.,
+             1.,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r =
+             _mm512_maskz_fnmadd_round_pd(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fnmadd_round_pd(
+             0b00001111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmadd_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(1.);
+         let r =
+             _mm512_mask3_fnmadd_round_pd(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fnmadd_round_pd(
+             a,
+             b,
+             c,
+             0b00001111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_fnmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r = _mm512_fnmsub_round_pd(a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(1.);
+         assert_eq_m512d(r, e);
+         let r = _mm512_fnmsub_round_pd(a, b, c, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+         let e = _mm512_set1_pd(0.9999999999999999);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_fnmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r =
+             _mm512_mask_fnmsub_round_pd(a, 0, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_fnmsub_round_pd(
+             a,
+             0b00001111,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(
+             1.,
+             1.,
+             1.,
+             1.,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+             0.000000000000000007,
+         );
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_fnmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r =
+             _mm512_maskz_fnmsub_round_pd(0, a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_fnmsub_round_pd(
+             0b00001111,
+             a,
+             b,
+             c,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask3_fnmsub_round_pd() {
+         let a = _mm512_set1_pd(0.000000000000000007);
+         let b = _mm512_set1_pd(1.);
+         let c = _mm512_set1_pd(-1.);
+         let r =
+             _mm512_mask3_fnmsub_round_pd(a, b, c, 0, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+         assert_eq_m512d(r, c);
+         let r = _mm512_mask3_fnmsub_round_pd(
+             a,
+             b,
+             c,
+             0b00001111,
+             _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
+         );
+         let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_max_round_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_max_round_pd(a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_max_round_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_mask_max_round_pd(a, 0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_max_round_pd(a, 0b00001111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_max_round_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_maskz_max_round_pd(0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_max_round_pd(0b00001111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_min_round_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_min_round_pd(a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_min_round_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_mask_min_round_pd(a, 0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_min_round_pd(a, 0b00001111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_min_round_pd() {
+         let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
+         let r = _mm512_maskz_min_round_pd(0, a, b, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_min_round_pd(0b00001111, a, b, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getexp_round_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_getexp_round_pd(a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_set1_pd(1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getexp_round_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_mask_getexp_round_pd(a, 0, a, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_getexp_round_pd(a, 0b11110000, a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getexp_round_pd() {
+         let a = _mm512_set1_pd(3.);
+         let r = _mm512_maskz_getexp_round_pd(0, a, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_getexp_round_pd(0b11110000, a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_getmant_round_pd() {
+         let a = _mm512_set1_pd(10.);
+         let r = _mm512_getmant_round_pd(
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         let e = _mm512_set1_pd(1.25);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_getmant_round_pd() {
+         let a = _mm512_set1_pd(10.);
+         let r = _mm512_mask_getmant_round_pd(
+             a,
+             0,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_getmant_round_pd(
+             a,
+             0b11110000,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_getmant_round_pd() {
+         let a = _mm512_set1_pd(10.);
+         let r = _mm512_maskz_getmant_round_pd(
+             0,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_getmant_round_pd(
+             0b11110000,
+             a,
+             _MM_MANT_NORM_1_2,
+             _MM_MANT_SIGN_SRC,
+             _MM_FROUND_CUR_DIRECTION,
+         );
+         let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cvt_roundps_pd() {
+         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_cvt_roundps_pd(a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cvt_roundps_pd() {
+         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let src = _mm512_set1_pd(0.);
+         let r = _mm512_mask_cvt_roundps_pd(src, 0, a, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, src);
+         let r = _mm512_mask_cvt_roundps_pd(src, 0b00001111, a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_cvt_roundps_pd() {
+         let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
+         let r = _mm512_maskz_cvt_roundps_pd(0, a, _MM_FROUND_CUR_DIRECTION);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_cvt_roundps_pd(0b00001111, a, _MM_FROUND_CUR_DIRECTION);
+         let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setzero_pd() {
+         assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set1_pd() {
+         let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
+         assert_eq_m512d(expected, _mm512_set1_pd(2.));
+     }
+ 
+     unsafe fn test_mm512_set1_epi64() {
+         let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
+         assert_eq_m512i(r, _mm512_set1_epi64(2));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmplt_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let m = _mm512_cmplt_pd_mask(a, b);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmplt_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpnlt_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let mask = 0b01111010;
+         assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmple_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmple_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let mask = 0b01111010;
+         assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpnle_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let m = _mm512_cmpnle_pd_mask(b, a);
+         assert_eq!(m, 0b00001101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpnle_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpeq_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
+         let m = _mm512_cmpeq_pd_mask(b, a);
+         assert_eq!(m, 0b11001101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpeq_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
+         assert_eq!(r, 0b01001000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpneq_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
+         let m = _mm512_cmpneq_pd_mask(b, a);
+         assert_eq!(m, 0b00110010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpneq_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
+         assert_eq!(r, 0b00110010)
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let m = _mm512_cmp_pd_mask(a, b, _CMP_LT_OQ);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmp_pd_mask(mask, a, b, _CMP_LT_OQ);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_round_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let m = _mm512_cmp_round_pd_mask(a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_round_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
+         let b = _mm512_set1_pd(-1.);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmp_round_pd_mask(mask, a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpord_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
+         let m = _mm512_cmpord_pd_mask(a, b);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpord_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
+         let mask = 0b11000011;
+         let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
+         assert_eq!(m, 0b00000001);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpunord_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
+         let m = _mm512_cmpunord_pd_mask(a, b);
+ 
+         assert_eq!(m, 0b11111010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpunord_pd_mask() {
+         #[rustfmt::skip]
+         let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
+         #[rustfmt::skip]
+         let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
+         let mask = 0b00001111;
+         let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
+         assert_eq!(m, 0b000001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmplt_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let m = _mm512_cmplt_epu64_mask(a, b);
+         assert_eq!(m, 0b11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmplt_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
+         assert_eq!(r, 0b01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpgt_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let m = _mm512_cmpgt_epu64_mask(b, a);
+         assert_eq!(m, 0b11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
+         assert_eq!(r, 0b01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmple_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         assert_eq!(
+             _mm512_cmple_epu64_mask(a, b),
+             !_mm512_cmpgt_epu64_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmple_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpge_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         assert_eq!(
+             _mm512_cmpge_epu64_mask(a, b),
+             !_mm512_cmplt_epu64_mask(a, b)
+         );
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpge_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         assert_eq!(_mm512_mask_cmpge_epu64_mask(mask, a, b), 0b01111010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpeq_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let m = _mm512_cmpeq_epu64_mask(b, a);
+         assert_eq!(m, 0b11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
+         assert_eq!(r, 0b01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpneq_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let m = _mm512_cmpneq_epu64_mask(b, a);
+         assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
+         assert_eq!(r, 0b00110010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let m = _mm512_cmp_epu64_mask(a, b, _MM_CMPINT_LT);
+         assert_eq!(m, 0b11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_epu64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmp_epu64_mask(mask, a, b, _MM_CMPINT_LT);
+         assert_eq!(r, 0b01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmplt_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let m = _mm512_cmplt_epi64_mask(a, b);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmplt_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpgt_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let m = _mm512_cmpgt_epi64_mask(b, a);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmple_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         assert_eq!(
+             _mm512_cmple_epi64_mask(a, b),
+             !_mm512_cmpgt_epi64_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmple_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpge_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         assert_eq!(
+             _mm512_cmpge_epi64_mask(a, b),
+             !_mm512_cmplt_epi64_mask(a, b)
+         )
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpge_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01111010;
+         assert_eq!(_mm512_mask_cmpge_epi64_mask(mask, a, b), 0b0110000);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmpeq_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let m = _mm512_cmpeq_epi64_mask(b, a);
+         assert_eq!(m, 0b11001111);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
+         assert_eq!(r, 0b01001010);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_set_epi64() {
+         let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_setr_epi64() {
+         let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
+     }
+ 
+     unsafe fn test_mm512_cmpneq_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let m = _mm512_cmpneq_epi64_mask(b, a);
+         assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
+         let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
+         let mask = 0b01111010;
+         let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
+         assert_eq!(r, 0b00110010)
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_cmp_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let m = _mm512_cmp_epi64_mask(a, b, _MM_CMPINT_LT);
+         assert_eq!(m, 0b00000101);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_cmp_epi64_mask() {
+         let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
+         let b = _mm512_set1_epi64(-1);
+         let mask = 0b01100110;
+         let r = _mm512_mask_cmp_epi64_mask(mask, a, b, _MM_CMPINT_LT);
+         assert_eq!(r, 0b00000100);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32gather_pd() {
+         let mut arr = [0f64; 128];
+         for i in 0..128 {
+             arr[i] = i as f64;
+         }
+         // A multiplier of 8 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         let r = _mm512_i32gather_pd(index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32gather_pd() {
+         let mut arr = [0f64; 128];
+         for i in 0..128 {
+             arr[i] = i as f64;
+         }
+         let src = _mm512_set1_pd(2.);
+         let mask = 0b10101010;
+         #[rustfmt::skip]
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         // A multiplier of 8 is word-addressing
+         let r = _mm512_mask_i32gather_pd(src, mask, index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64gather_pd() {
+         let mut arr = [0f64; 128];
+         for i in 0..128 {
+             arr[i] = i as f64;
+         }
+         // A multiplier of 8 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let r = _mm512_i64gather_pd(index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64gather_pd() {
+         let mut arr = [0f64; 128];
+         for i in 0..128 {
+             arr[i] = i as f64;
+         }
+         let src = _mm512_set1_pd(2.);
+         let mask = 0b10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         // A multiplier of 8 is word-addressing
+         let r = _mm512_mask_i64gather_pd(src, mask, index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64gather_ps() {
+         let mut arr = [0f32; 128];
+         for i in 0..128 {
+             arr[i] = i as f32;
+         }
+         // A multiplier of 4 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let r = _mm512_i64gather_ps(index, arr.as_ptr() as *const u8, 4);
+         assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64gather_ps() {
+         let mut arr = [0f32; 128];
+         for i in 0..128 {
+             arr[i] = i as f32;
+         }
+         let src = _mm256_set1_ps(2.);
+         let mask = 0b10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         // A multiplier of 4 is word-addressing
+         let r = _mm512_mask_i64gather_ps(src, mask, index, arr.as_ptr() as *const u8, 4);
+         assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         let r = _mm512_i32gather_epi64(index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         let src = _mm512_set1_epi64(2);
+         let mask = 0b10101010;
+         #[rustfmt::skip]
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         // A multiplier of 8 is word-addressing
+         let r = _mm512_mask_i32gather_epi64(src, mask, index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let r = _mm512_i64gather_epi64(index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64gather_epi64() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         let src = _mm512_set1_epi64(2);
+         let mask = 0b10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         // A multiplier of 8 is word-addressing
+         let r = _mm512_mask_i64gather_epi64(src, mask, index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64gather_epi32() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         // A multiplier of 8 is word-addressing
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let r = _mm512_i64gather_epi32(index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64gather_epi32() {
+         let mut arr = [0i64; 128];
+         for i in 0..128i64 {
+             arr[i as usize] = i;
+         }
+         let src = _mm256_set1_epi32(2);
+         let mask = 0b10101010;
+         #[rustfmt::skip]
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         // A multiplier of 8 is word-addressing
+         let r = _mm512_mask_i64gather_epi32(src, mask, index, arr.as_ptr() as *const u8, 8);
+         assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32scatter_pd() {
+         let mut arr = [0f64; 128];
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         // A multiplier of 8 is word-addressing
+         _mm512_i32scatter_pd(arr.as_mut_ptr() as *mut u8, index, src, 8);
+         let mut expected = [0f64; 128];
+         for i in 0..8 {
+             expected[i * 16] = (i + 1) as f64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32scatter_pd() {
+         let mut arr = [0f64; 128];
+         let mask = 0b10101010;
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         // A multiplier of 8 is word-addressing
+         _mm512_mask_i32scatter_pd(arr.as_mut_ptr() as *mut u8, mask, index, src, 8);
+         let mut expected = [0f64; 128];
+         for i in 0..4 {
+             expected[i * 32 + 16] = 2. * (i + 1) as f64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64scatter_pd() {
+         let mut arr = [0f64; 128];
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         // A multiplier of 8 is word-addressing
+         _mm512_i64scatter_pd(arr.as_mut_ptr() as *mut u8, index, src, 8);
+         let mut expected = [0f64; 128];
+         for i in 0..8 {
+             expected[i * 16] = (i + 1) as f64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64scatter_pd() {
+         let mut arr = [0f64; 128];
+         let mask = 0b10101010;
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         // A multiplier of 8 is word-addressing
+         _mm512_mask_i64scatter_pd(arr.as_mut_ptr() as *mut u8, mask, index, src, 8);
+         let mut expected = [0f64; 128];
+         for i in 0..4 {
+             expected[i * 32 + 16] = 2. * (i + 1) as f64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64scatter_ps() {
+         let mut arr = [0f32; 128];
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         // A multiplier of 4 is word-addressing
+         _mm512_i64scatter_ps(arr.as_mut_ptr() as *mut u8, index, src, 4);
+         let mut expected = [0f32; 128];
+         for i in 0..8 {
+             expected[i * 16] = (i + 1) as f32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64scatter_ps() {
+         let mut arr = [0f32; 128];
+         let mask = 0b10101010;
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
+         // A multiplier of 4 is word-addressing
+         _mm512_mask_i64scatter_ps(arr.as_mut_ptr() as *mut u8, mask, index, src, 4);
+         let mut expected = [0f32; 128];
+         for i in 0..4 {
+             expected[i * 32 + 16] = 2. * (i + 1) as f32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i32scatter_epi64() {
+         let mut arr = [0i64; 128];
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         // A multiplier of 8 is word-addressing
+         _mm512_i32scatter_epi64(arr.as_mut_ptr() as *mut u8, index, src, 8);
+         let mut expected = [0i64; 128];
+         for i in 0..8 {
+             expected[i * 16] = (i + 1) as i64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i32scatter_epi64() {
+         let mut arr = [0i64; 128];
+         let mask = 0b10101010;
+         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         // A multiplier of 8 is word-addressing
+         _mm512_mask_i32scatter_epi64(arr.as_mut_ptr() as *mut u8, mask, index, src, 8);
+         let mut expected = [0i64; 128];
+         for i in 0..4 {
+             expected[i * 32 + 16] = 2 * (i + 1) as i64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64scatter_epi64() {
+         let mut arr = [0i64; 128];
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         // A multiplier of 8 is word-addressing
+         _mm512_i64scatter_epi64(arr.as_mut_ptr() as *mut u8, index, src, 8);
+         let mut expected = [0i64; 128];
+         for i in 0..8 {
+             expected[i * 16] = (i + 1) as i64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64scatter_epi64() {
+         let mut arr = [0i64; 128];
+         let mask = 0b10101010;
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         // A multiplier of 8 is word-addressing
+         _mm512_mask_i64scatter_epi64(arr.as_mut_ptr() as *mut u8, mask, index, src, 8);
+         let mut expected = [0i64; 128];
+         for i in 0..4 {
+             expected[i * 32 + 16] = 2 * (i + 1) as i64;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_i64scatter_epi32() {
+         let mut arr = [0i32; 128];
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         // A multiplier of 4 is word-addressing
+         _mm512_i64scatter_epi32(arr.as_mut_ptr() as *mut u8, index, src, 4);
+         let mut expected = [0i32; 128];
+         for i in 0..8 {
+             expected[i * 16] = (i + 1) as i32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_i64scatter_epi32() {
+         let mut arr = [0i32; 128];
+         let mask = 0b10101010;
+         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
+         let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
+         // A multiplier of 4 is word-addressing
+         _mm512_mask_i64scatter_epi32(arr.as_mut_ptr() as *mut u8, mask, index, src, 4);
+         let mut expected = [0i32; 128];
+         for i in 0..4 {
+             expected[i * 32 + 16] = 2 * (i + 1) as i32;
+         }
+         assert_eq!(&arr[..], &expected[..],);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rol_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_rol_epi64(a, 1);
+         let e = _mm512_set_epi64(
+             1 << 0,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rol_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_mask_rol_epi64(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_rol_epi64(a, 0b11111111, a, 1);
+         let e = _mm512_set_epi64(
+             1 << 0,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rol_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 63,
+         );
+         let r = _mm512_maskz_rol_epi64(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_rol_epi64(0b00001111, a, 1);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_ror_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_ror_epi64(a, 1);
+         let e = _mm512_set_epi64(
+             1 << 63,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_ror_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_mask_ror_epi64(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_ror_epi64(a, 0b11111111, a, 1);
+         let e = _mm512_set_epi64(
+             1 << 63,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_ror_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 0,
+         );
+         let r = _mm512_maskz_ror_epi64(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_ror_epi64(0b00001111, a, 1);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_slli_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_slli_epi64(a, 1);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_slli_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_mask_slli_epi64(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_slli_epi64(a, 0b11111111, a, 1);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_slli_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 63,
+         );
+         let r = _mm512_maskz_slli_epi64(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_slli_epi64(0b00001111, a, 1);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srli_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_srli_epi64(a, 1);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srli_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let r = _mm512_mask_srli_epi64(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srli_epi64(a, 0b11111111, a, 1);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srli_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 0,
+         );
+         let r = _mm512_maskz_srli_epi64(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srli_epi64(0b00001111, a, 1);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rolv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_rolv_epi64(a, b);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             1 << 0,
+             1 << 34,
+             1 << 35,
+             1 << 36,
+             1 << 37,
+             1 << 38,
+             1 << 39,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rolv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_mask_rolv_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             1 << 0,
+             1 << 34,
+             1 << 35,
+             1 << 36,
+             1 << 37,
+             1 << 38,
+             1 << 39,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rolv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 62,
+         );
+         let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
+         let r = _mm512_maskz_rolv_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_rorv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_rorv_epi64(a, b);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             1 << 63,
+             1 << 30,
+             1 << 29,
+             1 << 28,
+             1 << 27,
+             1 << 26,
+             1 << 25,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_rorv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_mask_rorv_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             1 << 63,
+             1 << 30,
+             1 << 29,
+             1 << 28,
+             1 << 27,
+             1 << 26,
+             1 << 25,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_rorv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 0,
+         );
+         let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
+         let r = _mm512_maskz_rorv_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sllv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_sllv_epi64(a, count);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             0,
+             1 << 34,
+             1 << 35,
+             1 << 36,
+             1 << 37,
+             1 << 38,
+             1 << 39,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sllv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_mask_sllv_epi64(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             1 << 33,
+             0,
+             1 << 35,
+             1 << 36,
+             1 << 37,
+             1 << 38,
+             1 << 39,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sllv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 63,
+         );
+         let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
+         let r = _mm512_maskz_sllv_epi64(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srlv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_srlv_epi64(a, count);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             0,
+             1 << 30,
+             1 << 29,
+             1 << 28,
+             1 << 27,
+             1 << 26,
+             1 << 25,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srlv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_mask_srlv_epi64(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
+         let e = _mm512_set_epi64(
+             1 << 32,
+             0,
+             1 << 30,
+             1 << 29,
+             1 << 28,
+             1 << 27,
+             1 << 26,
+             1 << 25,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srlv_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 0,
+         );
+         let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_maskz_srlv_epi64(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sll_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm_set_epi64x(0, 1);
+         let r = _mm512_sll_epi64(a, count);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+         );
+         assert_eq_m512i(r, e);
+ 
+         let count = _mm_set_epi64x(1, 0);
+         let r = _mm512_sll_epi64(a, count);
+         assert_eq_m512i(r, a);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sll_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 63,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm_set_epi64x(0, 1);
+         let r = _mm512_mask_sll_epi64(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+             1 << 33,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sll_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 63,
+         );
+         let count = _mm_set_epi64x(0, 1);
+         let r = _mm512_maskz_sll_epi64(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srl_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm_set_epi64x(0, 1);
+         let r = _mm512_srl_epi64(a, count);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srl_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 0,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+         );
+         let count = _mm_set_epi64x(0, 1);
+         let r = _mm512_mask_srl_epi64(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
+         let e = _mm512_set_epi64(
+             0,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+             1 << 31,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srl_epi64() {
+         let a = _mm512_set_epi64(
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 32,
+             1 << 0,
+         );
+         let count = _mm_set_epi64x(0, 1);
+         let r = _mm512_maskz_srl_epi64(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_sra_epi64() {
+         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
+         let count = _mm_set_epi64x(0, 2);
+         let r = _mm512_sra_epi64(a, count);
+         let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_sra_epi64() {
+         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
+         let count = _mm_set_epi64x(0, 2);
+         let r = _mm512_mask_sra_epi64(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
+         let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_sra_epi64() {
+         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
+         let count = _mm_set_epi64x(0, 2);
+         let r = _mm512_maskz_sra_epi64(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srav_epi64() {
+         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
+         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
+         let r = _mm512_srav_epi64(a, count);
+         let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srav_epi64() {
+         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
+         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
+         let r = _mm512_mask_srav_epi64(a, 0, a, count);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
+         let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srav_epi64() {
+         let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
+         let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
+         let r = _mm512_maskz_srav_epi64(0, a, count);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_srai_epi64() {
+         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
+         let r = _mm512_srai_epi64(a, 2);
+         let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_srai_epi64() {
+         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
+         let r = _mm512_mask_srai_epi64(a, 0, a, 2);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_srai_epi64(a, 0b11111111, a, 2);
+         let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_srai_epi64() {
+         let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
+         let r = _mm512_maskz_srai_epi64(0, a, 2);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_srai_epi64(0b00001111, a, 2);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permute_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_permute_pd(a, 1);
+         let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permute_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_mask_permute_pd(a, 0, a, 1);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_permute_pd(a, 0b11111111, a, 1);
+         let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permute_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_maskz_permute_pd(0, a, 1);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_permute_pd(0b00001111, a, 1);
+         let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutex_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_permutex_epi64(a, 1);
+         let e = _mm512_set_epi64(6, 6, 6, 6, 6, 6, 6, 6);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutex_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_mask_permutex_epi64(a, 0, a, 1);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_permutex_epi64(a, 0b11111111, a, 1);
+         let e = _mm512_set_epi64(6, 6, 6, 6, 6, 6, 6, 6);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutex_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_maskz_permutex_epi64(0, a, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_permutex_epi64(0b00001111, a, 1);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutex_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_permutex_pd(a, 1);
+         let e = _mm512_set_pd(6., 6., 6., 6., 6., 6., 6., 6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutex_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_mask_permutex_pd(a, 0, a, 1);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_permutex_pd(a, 0b11111111, a, 1);
+         let e = _mm512_set_pd(6., 6., 6., 6., 6., 6., 6., 6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutex_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_maskz_permutex_pd(0, a, 1);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_permutex_pd(0b00001111, a, 1);
+         let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutevar_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_permutevar_pd(a, b);
+         let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutevar_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_mask_permutevar_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
+         let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutevar_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let b = _mm512_set1_epi64(1);
+         let r = _mm512_maskz_permutevar_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
+         let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutexvar_epi64() {
+         let idx = _mm512_set1_epi64(1);
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_permutexvar_epi64(idx, a);
+         let e = _mm512_set1_epi64(6);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutexvar_epi64() {
+         let idx = _mm512_set1_epi64(1);
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
+         let e = _mm512_set1_epi64(6);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutexvar_epi64() {
+         let idx = _mm512_set1_epi64(1);
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutexvar_pd() {
+         let idx = _mm512_set1_epi64(1);
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_permutexvar_pd(idx, a);
+         let e = _mm512_set1_pd(6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutexvar_pd() {
+         let idx = _mm512_set1_epi64(1);
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
+         let e = _mm512_set1_pd(6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutexvar_pd() {
+         let idx = _mm512_set1_epi64(1);
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let r = _mm512_maskz_permutexvar_pd(0, idx, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
+         let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutex2var_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_epi64(100);
+         let r = _mm512_permutex2var_epi64(a, idx, b);
+         let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutex2var_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_epi64(100);
+         let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
+         let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutex2var_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_epi64(100);
+         let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask2_permutex2var_epi64() {
+         let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
+         let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_epi64(100);
+         let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
+         assert_eq_m512i(r, idx);
+         let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
+         let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_permutex2var_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_pd(100.);
+         let r = _mm512_permutex2var_pd(a, idx, b);
+         let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_permutex2var_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_pd(100.);
+         let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
+         let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_permutex2var_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_pd(100.);
+         let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
+         let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask2_permutex2var_pd() {
+         let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
+         let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
+         let b = _mm512_set1_pd(100.);
+         let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_mask2_permutex2var_pd(a, idx, 0b00001111, b);
+         let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_pd() {
+         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
+         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
+         let r = _mm512_shuffle_pd(
+             a,
+             b,
+             1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7,
+         );
+         let e = _mm512_setr_pd(4., 3., 8., 7., 4., 3., 8., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_pd() {
+         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
+         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
+         let r = _mm512_mask_shuffle_pd(
+             a,
+             0,
+             a,
+             b,
+             1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7,
+         );
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_shuffle_pd(
+             a,
+             0b11111111,
+             a,
+             b,
+             1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7,
+         );
+         let e = _mm512_setr_pd(4., 3., 8., 7., 4., 3., 8., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_pd() {
+         let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);
+         let b = _mm512_setr_pd(2., 3., 6., 7., 2., 3., 6., 7.);
+         let r = _mm512_maskz_shuffle_pd(
+             0,
+             a,
+             b,
+             1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7,
+         );
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_shuffle_pd(
+             0b00001111,
+             a,
+             b,
+             1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7,
+         );
+         let e = _mm512_setr_pd(4., 3., 8., 7., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_i64x2() {
+         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm512_shuffle_i64x2(a, b, 0b00000000);
+         let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_i64x2() {
+         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm512_mask_shuffle_i64x2(a, 0, a, b, 0b00000000);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_shuffle_i64x2(a, 0b11111111, a, b, 0b00000000);
+         let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_i64x2() {
+         let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
+         let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
+         let r = _mm512_maskz_shuffle_i64x2(0, a, b, 0b00000000);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_shuffle_i64x2(0b00001111, a, b, 0b00000000);
+         let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_shuffle_f64x2() {
+         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm512_shuffle_f64x2(a, b, 0b00000000);
+         let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_shuffle_f64x2() {
+         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm512_mask_shuffle_f64x2(a, 0, a, b, 0b00000000);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_shuffle_f64x2(a, 0b11111111, a, b, 0b00000000);
+         let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_shuffle_f64x2() {
+         let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
+         let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
+         let r = _mm512_maskz_shuffle_f64x2(0, a, b, 0b00000000);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_shuffle_f64x2(0b00001111, a, b, 0b00000000);
+         let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_movedup_pd() {
+         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm512_movedup_pd(a);
+         let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_movedup_pd() {
+         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm512_mask_movedup_pd(a, 0, a);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
+         let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_movedup_pd() {
+         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let r = _mm512_maskz_movedup_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_movedup_pd(0b00001111, a);
+         let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_inserti64x4() {
+         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm256_setr_epi64x(17, 18, 19, 20);
+         let r = _mm512_inserti64x4(a, b, 1);
+         let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_inserti64x4() {
+         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm256_setr_epi64x(17, 18, 19, 20);
+         let r = _mm512_mask_inserti64x4(a, 0, a, b, 1);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_inserti64x4(a, 0b11111111, a, b, 1);
+         let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_inserti64x4() {
+         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm256_setr_epi64x(17, 18, 19, 20);
+         let r = _mm512_maskz_inserti64x4(0, a, b, 1);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_inserti64x4(0b00001111, a, b, 1);
+         let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_insertf64x4() {
+         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_pd(17., 18., 19., 20.);
+         let r = _mm512_insertf64x4(a, b, 1);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_insertf64x4() {
+         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_pd(17., 18., 19., 20.);
+         let r = _mm512_mask_insertf64x4(a, 0, a, b, 1);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_insertf64x4(a, 0b11111111, a, b, 1);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_insertf64x4() {
+         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm256_setr_pd(17., 18., 19., 20.);
+         let r = _mm512_maskz_insertf64x4(0, a, b, 1);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_insertf64x4(0b00001111, a, b, 1);
+         let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castpd128_pd512() {
+         let a = _mm_setr_pd(17., 18.);
+         let r = _mm512_castpd128_pd512(a);
+         let e = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castpd256_pd512() {
+         let a = _mm256_setr_pd(17., 18., 19., 20.);
+         let r = _mm512_castpd256_pd512(a);
+         let e = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castpd512_pd128() {
+         let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
+         let r = _mm512_castpd512_pd128(a);
+         let e = _mm_setr_pd(17., 18.);
+         assert_eq_m128d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castpd512_pd256() {
+         let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
+         let r = _mm512_castpd512_pd256(a);
+         let e = _mm256_setr_pd(17., 18., 19., 20.);
+         assert_eq_m256d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castpd_ps() {
+         let a = _mm512_set1_pd(1.);
+         let r = _mm512_castpd_ps(a);
+         let e = _mm512_set_ps(
+             1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
+             1.875, 0.0,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castpd_si512() {
+         let a = _mm512_set1_pd(1.);
+         let r = _mm512_castpd_si512(a);
+         let e = _mm512_set_epi32(
+             1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
+             0, 1072693248, 0, 1072693248, 0,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castsi128_si512() {
+         let a = _mm_setr_epi64x(17, 18);
+         let r = _mm512_castsi128_si512(a);
+         let e = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castsi256_si512() {
+         let a = _mm256_setr_epi64x(17, 18, 19, 20);
+         let r = _mm512_castsi256_si512(a);
+         let e = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castsi512_si128() {
+         let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
+         let r = _mm512_castsi512_si128(a);
+         let e = _mm_setr_epi64x(17, 18);
+         assert_eq_m128i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castsi512_si256() {
+         let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
+         let r = _mm512_castsi512_si256(a);
+         let e = _mm256_setr_epi64x(17, 18, 19, 20);
+         assert_eq_m256i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castsi512_ps() {
+         let a = _mm512_set1_epi64(1 << 62);
+         let r = _mm512_castsi512_ps(a);
+         let e = _mm512_set_ps(
+             2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
+         );
+         assert_eq_m512(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_castsi512_pd() {
+         let a = _mm512_set1_epi64(1 << 62);
+         let r = _mm512_castsi512_pd(a);
+         let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcastq_epi64() {
+         let a = _mm_setr_epi64x(17, 18);
+         let r = _mm512_broadcastq_epi64(a);
+         let e = _mm512_set1_epi64(17);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcastq_epi64() {
+         let src = _mm512_set1_epi64(18);
+         let a = _mm_setr_epi64x(17, 18);
+         let r = _mm512_mask_broadcastq_epi64(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
+         let e = _mm512_set1_epi64(17);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcastq_epi64() {
+         let a = _mm_setr_epi64x(17, 18);
+         let r = _mm512_maskz_broadcastq_epi64(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcastsd_pd() {
+         let a = _mm_setr_pd(17., 18.);
+         let r = _mm512_broadcastsd_pd(a);
+         let e = _mm512_set1_pd(18.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcastsd_pd() {
+         let src = _mm512_set1_pd(18.);
+         let a = _mm_setr_pd(17., 18.);
+         let r = _mm512_mask_broadcastsd_pd(src, 0, a);
+         assert_eq_m512d(r, src);
+         let r = _mm512_mask_broadcastsd_pd(src, 0b01111111, a);
+         let e = _mm512_set1_pd(18.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcastsd_pd() {
+         let a = _mm_setr_pd(17., 18.);
+         let r = _mm512_maskz_broadcastsd_pd(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
+         let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcast_i64x4() {
+         let a = _mm256_set_epi64x(17, 18, 19, 20);
+         let r = _mm512_broadcast_i64x4(a);
+         let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcast_i64x4() {
+         let src = _mm512_set1_epi64(18);
+         let a = _mm256_set_epi64x(17, 18, 19, 20);
+         let r = _mm512_mask_broadcast_i64x4(src, 0, a);
+         assert_eq_m512i(r, src);
+         let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
+         let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcast_i64x4() {
+         let a = _mm256_set_epi64x(17, 18, 19, 20);
+         let r = _mm512_maskz_broadcast_i64x4(0, a);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_broadcast_f64x4() {
+         let a = _mm256_set_pd(17., 18., 19., 20.);
+         let r = _mm512_broadcast_f64x4(a);
+         let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_broadcast_f64x4() {
+         let src = _mm512_set1_pd(18.);
+         let a = _mm256_set_pd(17., 18., 19., 20.);
+         let r = _mm512_mask_broadcast_f64x4(src, 0, a);
+         assert_eq_m512d(r, src);
+         let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
+         let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_broadcast_f64x4() {
+         let a = _mm256_set_pd(17., 18., 19., 20.);
+         let r = _mm512_maskz_broadcast_f64x4(0, a);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
+         let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_blend_epi64() {
+         let a = _mm512_set1_epi64(1);
+         let b = _mm512_set1_epi64(2);
+         let r = _mm512_mask_blend_epi64(0b11110000, a, b);
+         let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_blend_pd() {
+         let a = _mm512_set1_pd(1.);
+         let b = _mm512_set1_pd(2.);
+         let r = _mm512_mask_blend_pd(0b11110000, a, b);
+         let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpackhi_epi64() {
+         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
+         let r = _mm512_unpackhi_epi64(a, b);
+         let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpackhi_epi64() {
+         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
+         let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpackhi_epi64() {
+         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
+         let r = _mm512_maskz_unpackhi_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpackhi_pd() {
+         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_unpackhi_pd(a, b);
+         let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpackhi_pd() {
+         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
+         let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpackhi_pd() {
+         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_maskz_unpackhi_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
+         let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpacklo_epi64() {
+         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
+         let r = _mm512_unpacklo_epi64(a, b);
+         let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpacklo_epi64() {
+         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
+         let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+         let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpacklo_epi64() {
+         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
+         let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
+         let r = _mm512_maskz_unpacklo_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+         let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_unpacklo_pd() {
+         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_unpacklo_pd(a, b);
+         let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_unpacklo_pd() {
+         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
+         assert_eq_m512d(r, a);
+         let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
+         let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_unpacklo_pd() {
+         let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
+         let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
+         let r = _mm512_maskz_unpacklo_pd(0, a, b);
+         assert_eq_m512d(r, _mm512_setzero_pd());
+         let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
+         let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
+         assert_eq_m512d(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_and_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_and_epi64(a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_and_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_mask_and_epi64(a, 0, a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+ 
+         let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_and_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_maskz_and_epi64(0, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+ 
+         let r = _mm512_maskz_and_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_and_si512() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_and_epi64(a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_or_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_or_epi64(a, b);
+         let e = _mm512_set_epi64(
+             1 << 0 | 1 << 13 | 1 << 15,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 2 | 1 << 3,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_or_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_mask_or_epi64(a, 0, a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+ 
+         let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set_epi64(
+             1 << 0 | 1 << 13 | 1 << 15,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 2 | 1 << 3,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_or_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_maskz_or_epi64(0, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+ 
+         let r = _mm512_maskz_or_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_or_si512() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_or_epi64(a, b);
+         let e = _mm512_set_epi64(
+             1 << 0 | 1 << 13 | 1 << 15,
+             0,
+             0,
+             0,
+             0,
+             0,
+             0,
+             1 << 1 | 1 << 2 | 1 << 3,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_xor_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_xor_epi64(a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_xor_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_mask_xor_epi64(a, 0, a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         assert_eq_m512i(r, e);
+ 
+         let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_xor_epi64() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_maskz_xor_epi64(0, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+ 
+         let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_xor_si512() {
+         let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
+         let r = _mm512_xor_epi64(a, b);
+         let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_andnot_epi64() {
+         let a = _mm512_set1_epi64(0);
+         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         let r = _mm512_andnot_epi64(a, b);
+         let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_mask_andnot_epi64() {
+         let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
+         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         let r = _mm512_mask_andnot_epi64(a, 0, a, b);
+         assert_eq_m512i(r, a);
+ 
+         let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
+         let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_maskz_andnot_epi64() {
+         let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
+         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         let r = _mm512_maskz_andnot_epi64(0, a, b);
+         assert_eq_m512i(r, _mm512_setzero_si512());
+ 
+         let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
+         let e = _mm512_set_epi64(
+             0,
+             0,
+             0,
+             0,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+             1 << 3 | 1 << 4,
+         );
+         assert_eq_m512i(r, e);
+     }
+ 
+     #[simd_test(enable = "avx512f")]
+     unsafe fn test_mm512_andnot_si512() {
+         let a = _mm512_set1_epi64(0);
+         let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         let r = _mm512_andnot_si512(a, b);
+         let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
+         assert_eq_m512i(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,183 ----
+ //! Bit Manipulation Instruction (BMI) Set 1.0.
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
+ //! available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [wikipedia_bmi]: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Extracts bits in range [`start`, `start` + `length`) from `a` into
+ /// the least significant bits of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(bextr))]
+ #[cfg(not(target_arch = "x86"))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
+     _bextr2_u64(a, ((start & 0xff) | ((len & 0xff) << 8)) as u64)
+ }
+ 
+ /// Extracts bits of `a` specified by `control` into
+ /// the least significant bits of the result.
+ ///
+ /// Bits `[7,0]` of `control` specify the index to the first bit in the range
+ /// to be extracted, and bits `[15,8]` specify the length of the range.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr2_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(bextr))]
+ #[cfg(not(target_arch = "x86"))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 {
+     x86_bmi_bextr_64(a, control)
+ }
+ 
+ /// Bitwise logical `AND` of inverted `a` with `b`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_andn_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(andn))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _andn_u64(a: u64, b: u64) -> u64 {
+     !a & b
+ }
+ 
+ /// Extracts lowest set isolated bit.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsi_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(blsi))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsi_u64(x: u64) -> u64 {
+     x & x.wrapping_neg()
+ }
+ 
+ /// Gets mask up to lowest set bit.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsmsk_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(blsmsk))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
+     x ^ (x.wrapping_sub(1_u64))
+ }
+ 
+ /// Resets the lowest set bit of `x`.
+ ///
+ /// If `x` is sets CF.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsr_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(blsr))]
+ #[cfg(not(target_arch = "x86"))] // generates lots of instructions
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _blsr_u64(x: u64) -> u64 {
+     x & (x.wrapping_sub(1))
+ }
+ 
+ /// Counts the number of trailing least significant zero bits.
+ ///
+ /// When the source operand is `0`, it returns its size in bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_tzcnt_u64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(tzcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _tzcnt_u64(x: u64) -> u64 {
+     x.trailing_zeros() as u64
+ }
+ 
+ /// Counts the number of trailing least significant zero bits.
+ ///
+ /// When the source operand is `0`, it returns its size in bits.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_tzcnt_64)
+ #[inline]
+ #[target_feature(enable = "bmi1")]
+ #[cfg_attr(test, assert_instr(tzcnt))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_tzcnt_64(x: u64) -> i64 {
+     x.trailing_zeros() as i64
+ }
+ 
+ extern "C" {
+     #[link_name = "llvm.x86.bmi.bextr.64"]
+     fn x86_bmi_bextr_64(x: u64, y: u64) -> u64;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::{x86::*, x86_64::*};
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_bextr_u64() {
+         let r = _bextr_u64(0b0101_0000u64, 4, 4);
+         assert_eq!(r, 0b0000_0101u64);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_andn_u64() {
+         assert_eq!(_andn_u64(0, 0), 0);
+         assert_eq!(_andn_u64(0, 1), 1);
+         assert_eq!(_andn_u64(1, 0), 0);
+         assert_eq!(_andn_u64(1, 1), 0);
+ 
+         let r = _andn_u64(0b0000_0000u64, 0b0000_0000u64);
+         assert_eq!(r, 0b0000_0000u64);
+ 
+         let r = _andn_u64(0b0000_0000u64, 0b1111_1111u64);
+         assert_eq!(r, 0b1111_1111u64);
+ 
+         let r = _andn_u64(0b1111_1111u64, 0b0000_0000u64);
+         assert_eq!(r, 0b0000_0000u64);
+ 
+         let r = _andn_u64(0b1111_1111u64, 0b1111_1111u64);
+         assert_eq!(r, 0b0000_0000u64);
+ 
+         let r = _andn_u64(0b0100_0000u64, 0b0101_1101u64);
+         assert_eq!(r, 0b0001_1101u64);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_blsi_u64() {
+         assert_eq!(_blsi_u64(0b1101_0000u64), 0b0001_0000u64);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_blsmsk_u64() {
+         let r = _blsmsk_u64(0b0011_0000u64);
+         assert_eq!(r, 0b0001_1111u64);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_blsr_u64() {
+         // TODO: test the behavior when the input is `0`.
+         let r = _blsr_u64(0b0011_0000u64);
+         assert_eq!(r, 0b0010_0000u64);
+     }
+ 
+     #[simd_test(enable = "bmi1")]
+     unsafe fn test_tzcnt_u64() {
+         assert_eq!(_tzcnt_u64(0b0000_0001u64), 0u64);
+         assert_eq!(_tzcnt_u64(0b0000_0000u64), 64u64);
+         assert_eq!(_tzcnt_u64(0b1001_0000u64), 4u64);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,139 ----
+ //! Bit Manipulation Instruction (BMI) Set 2.0.
+ //!
+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
+ //!
+ //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions
+ //! available.
+ //!
+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ //! [wikipedia_bmi]:
+ //! https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Unsigned multiply without affecting flags.
+ ///
+ /// Unsigned multiplication of `a` with `b` returning a pair `(lo, hi)` with
+ /// the low half and the high half of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mulx_u64)
+ #[inline]
+ #[cfg_attr(test, assert_instr(mul))]
+ #[target_feature(enable = "bmi2")]
+ #[cfg(not(target_arch = "x86"))] // calls an intrinsic
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mulx_u64(a: u64, b: u64, hi: &mut u64) -> u64 {
+     let result: u128 = (a as u128) * (b as u128);
+     *hi = (result >> 64) as u64;
+     result as u64
+ }
+ 
+ /// Zeroes higher bits of `a` >= `index`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bzhi_u64)
+ #[inline]
+ #[target_feature(enable = "bmi2")]
+ #[cfg_attr(test, assert_instr(bzhi))]
+ #[cfg(not(target_arch = "x86"))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bzhi_u64(a: u64, index: u32) -> u64 {
+     x86_bmi2_bzhi_64(a, index as u64)
+ }
+ 
+ /// Scatter contiguous low order bits of `a` to the result at the positions
+ /// specified by the `mask`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_pdep_u64)
+ #[inline]
+ #[target_feature(enable = "bmi2")]
+ #[cfg_attr(test, assert_instr(pdep))]
+ #[cfg(not(target_arch = "x86"))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _pdep_u64(a: u64, mask: u64) -> u64 {
+     x86_bmi2_pdep_64(a, mask)
+ }
+ 
+ /// Gathers the bits of `x` specified by the `mask` into the contiguous low
+ /// order bit positions of the result.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_pext_u64)
+ #[inline]
+ #[target_feature(enable = "bmi2")]
+ #[cfg_attr(test, assert_instr(pext))]
+ #[cfg(not(target_arch = "x86"))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _pext_u64(a: u64, mask: u64) -> u64 {
+     x86_bmi2_pext_64(a, mask)
+ }
+ 
+ extern "C" {
+     #[link_name = "llvm.x86.bmi.bzhi.64"]
+     fn x86_bmi2_bzhi_64(x: u64, y: u64) -> u64;
+     #[link_name = "llvm.x86.bmi.pdep.64"]
+     fn x86_bmi2_pdep_64(x: u64, y: u64) -> u64;
+     #[link_name = "llvm.x86.bmi.pext.64"]
+     fn x86_bmi2_pext_64(x: u64, y: u64) -> u64;
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use stdarch_test::simd_test;
+ 
+     use crate::core_arch::x86_64::*;
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_pext_u64() {
+         let n = 0b1011_1110_1001_0011u64;
+ 
+         let m0 = 0b0110_0011_1000_0101u64;
+         let s0 = 0b0000_0000_0011_0101u64;
+ 
+         let m1 = 0b1110_1011_1110_1111u64;
+         let s1 = 0b0001_0111_0100_0011u64;
+ 
+         assert_eq!(_pext_u64(n, m0), s0);
+         assert_eq!(_pext_u64(n, m1), s1);
+     }
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_pdep_u64() {
+         let n = 0b1011_1110_1001_0011u64;
+ 
+         let m0 = 0b0110_0011_1000_0101u64;
+         let s0 = 0b0000_0010_0000_0101u64;
+ 
+         let m1 = 0b1110_1011_1110_1111u64;
+         let s1 = 0b1110_1001_0010_0011u64;
+ 
+         assert_eq!(_pdep_u64(n, m0), s0);
+         assert_eq!(_pdep_u64(n, m1), s1);
+     }
+ 
+     #[simd_test(enable = "bmi2")]
+     unsafe fn test_bzhi_u64() {
+         let n = 0b1111_0010u64;
+         let s = 0b0001_0010u64;
+         assert_eq!(_bzhi_u64(n, 5), s);
+     }
+ 
+     #[simd_test(enable = "bmi2")]
+     #[rustfmt::skip]
+     unsafe fn test_mulx_u64() {
+         let a: u64 = 9_223_372_036_854_775_800;
+         let b: u64 = 100;
+         let mut hi = 0;
+         let lo = _mulx_u64(a, b, &mut hi);
+         /*
+ result = 922337203685477580000 =
+ 0b00110001_1111111111111111_1111111111111111_1111111111111111_1111110011100000
+   ^~hi~~~~ ^~lo~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+         */
+         assert_eq!(
+             lo,
+             0b11111111_11111111_11111111_11111111_11111111_11111111_11111100_11100000u64
+         );
+         assert_eq!(hi, 0b00110001u64);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,29 ----
+ //! Byte swap intrinsics.
+ 
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Returns an integer with the reversed byte order of x
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bswap64)
+ #[inline]
+ #[cfg_attr(test, assert_instr(bswap))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _bswap64(x: i64) -> i64 {
+     x.swap_bytes()
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use super::*;
+ 
+     #[test]
+     fn test_bswap64() {
+         unsafe {
+             assert_eq!(_bswap64(0x0EADBEEFFADECA0E), 0x0ECADEFAEFBEAD0E);
+             assert_eq!(_bswap64(0x0000000000000000), 0x0000000000000000);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,102 ----
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(bt))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittest64(p: *const i64, b: i64) -> u8 {
+     let r: u8;
+     llvm_asm!("btq $2, $1\n\tsetc ${0:b}"
+               : "=r"(r)
+               : "*m"(p), "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`, then sets the bit to `1`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(bts))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittestandset64(p: *mut i64, b: i64) -> u8 {
+     let r: u8;
+     llvm_asm!("btsq $2, $1\n\tsetc ${0:b}"
+               : "=r"(r), "+*m"(p)
+               : "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`, then resets that bit to `0`.
+ #[inline]
+ #[cfg_attr(test, assert_instr(btr))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittestandreset64(p: *mut i64, b: i64) -> u8 {
+     let r: u8;
+     llvm_asm!("btrq $2, $1\n\tsetc ${0:b}"
+               : "=r"(r), "+*m"(p)
+               : "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ /// Returns the bit in position `b` of the memory addressed by `p`, then inverts that bit.
+ #[inline]
+ #[cfg_attr(test, assert_instr(btc))]
+ #[unstable(feature = "simd_x86_bittest", issue = "59414")]
+ pub unsafe fn _bittestandcomplement64(p: *mut i64, b: i64) -> u8 {
+     let r: u8;
+     llvm_asm!("btcq $2, $1\n\tsetc ${0:b}"
+               : "=r"(r), "+*m"(p)
+               : "r"(b)
+               : "cc", "memory");
+     r
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86_64::*;
+ 
+     #[test]
+     fn test_bittest64() {
+         unsafe {
+             let a = 0b0101_0000i64;
+             assert_eq!(_bittest64(&a as _, 4), 1);
+             assert_eq!(_bittest64(&a as _, 5), 0);
+         }
+     }
+ 
+     #[test]
+     fn test_bittestandset64() {
+         unsafe {
+             let mut a = 0b0101_0000i64;
+             assert_eq!(_bittestandset64(&mut a as _, 4), 1);
+             assert_eq!(_bittestandset64(&mut a as _, 4), 1);
+             assert_eq!(_bittestandset64(&mut a as _, 5), 0);
+             assert_eq!(_bittestandset64(&mut a as _, 5), 1);
+         }
+     }
+ 
+     #[test]
+     fn test_bittestandreset64() {
+         unsafe {
+             let mut a = 0b0101_0000i64;
+             assert_eq!(_bittestandreset64(&mut a as _, 4), 1);
+             assert_eq!(_bittestandreset64(&mut a as _, 4), 0);
+             assert_eq!(_bittestandreset64(&mut a as _, 5), 0);
+             assert_eq!(_bittestandreset64(&mut a as _, 5), 0);
+         }
+     }
+ 
+     #[test]
+     fn test_bittestandcomplement64() {
+         unsafe {
+             let mut a = 0b0101_0000i64;
+             assert_eq!(_bittestandcomplement64(&mut a as _, 4), 1);
+             assert_eq!(_bittestandcomplement64(&mut a as _, 4), 0);
+             assert_eq!(_bittestandcomplement64(&mut a as _, 4), 1);
+             assert_eq!(_bittestandcomplement64(&mut a as _, 5), 0);
+             assert_eq!(_bittestandcomplement64(&mut a as _, 5), 1);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,73 ----
+ use crate::sync::atomic::Ordering;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Compares and exchange 16 bytes (128 bits) of data atomically.
+ ///
+ /// This intrinsic corresponds to the `cmpxchg16b` instruction on `x86_64`
+ /// processors. It performs an atomic compare-and-swap, updating the `ptr`
+ /// memory location to `val` if the current value in memory equals `old`.
+ ///
+ /// # Return value
+ ///
+ /// This function returns the previous value at the memory location. If it is
+ /// equal to `old` then the memory was updated to `new`.
+ ///
+ /// # Memory Orderings
+ ///
+ /// This atomic operations has the same semantics of memory orderings as
+ /// `AtomicUsize::compare_exchange` does, only operating on 16 bytes of memory
+ /// instead of just a pointer.
+ ///
+ /// For more information on memory orderings here see the `compare_exchange`
+ /// documentation for other `Atomic*` types in the standard library.
+ ///
+ /// # Unsafety
+ ///
+ /// This method is unsafe because it takes a raw pointer and will attempt to
+ /// read and possibly write the memory at the pointer. The pointer must also be
+ /// aligned on a 16-byte boundary.
+ ///
+ /// This method also requires the `cmpxchg16b` CPU feature to be available at
+ /// runtime to work correctly. If the CPU running the binary does not actually
+ /// support `cmpxchg16b` and the program enters an execution path that
+ /// eventually would reach this function the behavior is undefined.
+ ///
+ /// The `success` ordering must also be stronger or equal to `failure`, or this
+ /// function call is undefined. See the `Atomic*` documentation's
+ /// `compare_exchange` function for more information. When `compare_exchange`
+ /// panics, this is undefined behavior. Currently this function aborts the
+ /// process with an undefined instruction.
+ #[inline]
+ #[cfg_attr(test, assert_instr(cmpxchg16b, success = Ordering::SeqCst, failure = Ordering::SeqCst))]
+ #[target_feature(enable = "cmpxchg16b")]
+ pub unsafe fn cmpxchg16b(
+     dst: *mut u128,
+     old: u128,
+     new: u128,
+     success: Ordering,
+     failure: Ordering,
+ ) -> u128 {
+     use crate::{intrinsics, sync::atomic::Ordering::*};
+ 
+     debug_assert!(dst as usize % 16 == 0);
+ 
+     let (val, _ok) = match (success, failure) {
+         (Acquire, Acquire) => intrinsics::atomic_cxchg_acq(dst, old, new),
+         (Release, Relaxed) => intrinsics::atomic_cxchg_rel(dst, old, new),
+         (AcqRel, Acquire) => intrinsics::atomic_cxchg_acqrel(dst, old, new),
+         (Relaxed, Relaxed) => intrinsics::atomic_cxchg_relaxed(dst, old, new),
+         (SeqCst, SeqCst) => intrinsics::atomic_cxchg(dst, old, new),
+         (Acquire, Relaxed) => intrinsics::atomic_cxchg_acq_failrelaxed(dst, old, new),
+         (AcqRel, Relaxed) => intrinsics::atomic_cxchg_acqrel_failrelaxed(dst, old, new),
+         (SeqCst, Relaxed) => intrinsics::atomic_cxchg_failrelaxed(dst, old, new),
+         (SeqCst, Acquire) => intrinsics::atomic_cxchg_failacq(dst, old, new),
+ 
+         // The above block is all copied from libcore, and this statement is
+         // also copied from libcore except that it's a panic in libcore and we
+         // have a little bit more of a lightweight panic here.
+         _ => crate::core_arch::x86::ud2(),
+     };
+     val
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,112 ----
+ //! FXSR floating-point context fast save and restor.
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.fxsave64"]
+     fn fxsave64(p: *mut u8) -> ();
+     #[link_name = "llvm.x86.fxrstor64"]
+     fn fxrstor64(p: *const u8) -> ();
+ }
+ 
+ /// Saves the `x87` FPU, `MMX` technology, `XMM`, and `MXCSR` registers to the
+ /// 512-byte-long 16-byte-aligned memory region `mem_addr`.
+ ///
+ /// A misaligned destination operand raises a general-protection (#GP) or an
+ /// alignment check exception (#AC).
+ ///
+ /// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor].
+ ///
+ /// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html
+ /// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_fxsave64)
+ #[inline]
+ #[target_feature(enable = "fxsr")]
+ #[cfg_attr(test, assert_instr(fxsave64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _fxsave64(mem_addr: *mut u8) {
+     fxsave64(mem_addr)
+ }
+ 
+ /// Restores the `XMM`, `MMX`, `MXCSR`, and `x87` FPU registers from the
+ /// 512-byte-long 16-byte-aligned memory region `mem_addr`.
+ ///
+ /// The contents of this memory region should have been written to by a
+ /// previous
+ /// `_fxsave` or `_fxsave64` intrinsic.
+ ///
+ /// A misaligned destination operand raises a general-protection (#GP) or an
+ /// alignment check exception (#AC).
+ ///
+ /// See [`FXSAVE`][fxsave] and [`FXRSTOR`][fxrstor].
+ ///
+ /// [fxsave]: http://www.felixcloutier.com/x86/FXSAVE.html
+ /// [fxrstor]: http://www.felixcloutier.com/x86/FXRSTOR.html
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_fxrstor64)
+ #[inline]
+ #[target_feature(enable = "fxsr")]
+ #[cfg_attr(test, assert_instr(fxrstor64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _fxrstor64(mem_addr: *const u8) {
+     fxrstor64(mem_addr)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86_64::*;
+     use std::{cmp::PartialEq, fmt};
+     use stdarch_test::simd_test;
+ 
+     #[repr(align(16))]
+     struct FxsaveArea {
+         data: [u8; 512], // 512 bytes
+     }
+ 
+     impl FxsaveArea {
+         fn new() -> FxsaveArea {
+             FxsaveArea { data: [0; 512] }
+         }
+         fn ptr(&mut self) -> *mut u8 {
+             &mut self.data[0] as *mut _ as *mut u8
+         }
+     }
+ 
+     impl PartialEq<FxsaveArea> for FxsaveArea {
+         fn eq(&self, other: &FxsaveArea) -> bool {
+             for i in 0..self.data.len() {
+                 if self.data[i] != other.data[i] {
+                     return false;
+                 }
+             }
+             true
+         }
+     }
+ 
+     impl fmt::Debug for FxsaveArea {
+         fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+             write!(f, "[")?;
+             for i in 0..self.data.len() {
+                 write!(f, "{}", self.data[i])?;
+                 if i != self.data.len() - 1 {
+                     write!(f, ", ")?;
+                 }
+             }
+             write!(f, "]")
+         }
+     }
+ 
+     #[simd_test(enable = "fxsr")]
+     unsafe fn fxsave64() {
+         let mut a = FxsaveArea::new();
+         let mut b = FxsaveArea::new();
+ 
+         fxsr::_fxsave64(a.ptr());
+         fxsr::_fxrstor64(a.ptr());
+         fxsr::_fxsave64(b.ptr());
+         assert_eq!(a, b);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,52 ----
+ //! `x86_64` intrinsics
+ 
+ mod fxsr;
+ pub use self::fxsr::*;
+ 
+ mod sse;
+ pub use self::sse::*;
+ 
+ mod sse2;
+ pub use self::sse2::*;
+ 
+ mod sse41;
+ pub use self::sse41::*;
+ 
+ mod sse42;
+ pub use self::sse42::*;
+ 
+ mod xsave;
+ pub use self::xsave::*;
+ 
+ mod abm;
+ pub use self::abm::*;
+ 
+ mod avx;
+ pub use self::avx::*;
+ 
+ mod bmi;
+ pub use self::bmi::*;
+ 
+ mod bmi2;
+ pub use self::bmi2::*;
+ 
+ mod avx2;
+ pub use self::avx2::*;
+ 
+ mod avx512f;
+ pub use self::avx512f::*;
+ 
+ mod bswap;
+ pub use self::bswap::*;
+ 
+ mod rdrand;
+ pub use self::rdrand::*;
+ 
+ mod cmpxchg16b;
+ pub use self::cmpxchg16b::*;
+ 
+ mod adx;
+ pub use self::adx::*;
+ 
+ mod bt;
+ pub use self::bt::*;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,44 ----
+ //! RDRAND and RDSEED instructions for returning random numbers from an Intel
+ //! on-chip hardware random number generator which has been seeded by an
+ //! on-chip entropy source.
+ 
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[allow(improper_ctypes)]
+ extern "unadjusted" {
+     #[link_name = "llvm.x86.rdrand.64"]
+     fn x86_rdrand64_step() -> (u64, i32);
+     #[link_name = "llvm.x86.rdseed.64"]
+     fn x86_rdseed64_step() -> (u64, i32);
+ }
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Read a hardware generated 64-bit random value and store the result in val.
+ /// Returns 1 if a random value was generated, and 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdrand64_step)
+ #[inline]
+ #[target_feature(enable = "rdrand")]
+ #[cfg_attr(test, assert_instr(rdrand))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdrand64_step(val: &mut u64) -> i32 {
+     let (v, flag) = x86_rdrand64_step();
+     *val = v;
+     flag
+ }
+ 
+ /// Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store
+ /// in val. Return 1 if a random value was generated, and 0 otherwise.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdseed64_step)
+ #[inline]
+ #[target_feature(enable = "rdseed")]
+ #[cfg_attr(test, assert_instr(rdseed))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _rdseed64_step(val: &mut u64) -> i32 {
+     let (v, flag) = x86_rdseed64_step();
+     *val = v;
+     flag
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,148 ----
+ //! `x86_64` Streaming SIMD Extensions (SSE)
+ 
+ use crate::core_arch::x86::*;
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse.cvtss2si64"]
+     fn cvtss2si64(a: __m128) -> i64;
+     #[link_name = "llvm.x86.sse.cvttss2si64"]
+     fn cvttss2si64(a: __m128) -> i64;
+     #[link_name = "llvm.x86.sse.cvtsi642ss"]
+     fn cvtsi642ss(a: __m128, b: i64) -> __m128;
+ }
+ 
+ /// Converts the lowest 32 bit float in the input vector to a 64 bit integer.
+ ///
+ /// The result is rounded according to the current rounding mode. If the result
+ /// cannot be represented as a 64 bit integer the result will be
+ /// `0x8000_0000_0000_0000` (`i64::MIN`) or trigger an invalid operation
+ /// floating point exception if unmasked (see
+ /// [`_mm_setcsr`](fn._mm_setcsr.html)).
+ ///
+ /// This corresponds to the `CVTSS2SI` instruction (with 64 bit output).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_si64)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvtss2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtss_si64(a: __m128) -> i64 {
+     cvtss2si64(a)
+ }
+ 
+ /// Converts the lowest 32 bit float in the input vector to a 64 bit integer
+ /// with truncation.
+ ///
+ /// The result is rounded always using truncation (round towards zero). If the
+ /// result cannot be represented as a 64 bit integer the result will be
+ /// `0x8000_0000_0000_0000` (`i64::MIN`) or an invalid operation floating
+ /// point exception if unmasked (see [`_mm_setcsr`](fn._mm_setcsr.html)).
+ ///
+ /// This corresponds to the `CVTTSS2SI` instruction (with 64 bit output).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_si64)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvttss2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttss_si64(a: __m128) -> i64 {
+     cvttss2si64(a)
+ }
+ 
+ /// Converts a 64 bit integer to a 32 bit float. The result vector is the input
+ /// vector `a` with the lowest 32 bit float replaced by the converted integer.
+ ///
+ /// This intrinsic corresponds to the `CVTSI2SS` instruction (with 64 bit
+ /// input).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi64_ss)
+ #[inline]
+ #[target_feature(enable = "sse")]
+ #[cfg_attr(test, assert_instr(cvtsi2ss))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi64_ss(a: __m128, b: i64) -> __m128 {
+     cvtsi642ss(a, b)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arch::x86_64::*;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvtss_si64() {
+         let inputs = &[
+             (42.0f32, 42i64),
+             (-31.4, -31),
+             (-33.5, -34),
+             (-34.5, -34),
+             (4.0e10, 40_000_000_000),
+             (4.0e-10, 0),
+             (f32::NAN, i64::MIN),
+             (2147483500.1, 2147483520),
+             (9.223371e18, 9223370937343148032),
+         ];
+         for i in 0..inputs.len() {
+             let (xi, e) = inputs[i];
+             let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+             let r = _mm_cvtss_si64(x);
+             assert_eq!(
+                 e, r,
+                 "TestCase #{} _mm_cvtss_si64({:?}) = {}, expected: {}",
+                 i, x, r, e
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvttss_si64() {
+         let inputs = &[
+             (42.0f32, 42i64),
+             (-31.4, -31),
+             (-33.5, -33),
+             (-34.5, -34),
+             (10.999, 10),
+             (-5.99, -5),
+             (4.0e10, 40_000_000_000),
+             (4.0e-10, 0),
+             (f32::NAN, i64::MIN),
+             (2147483500.1, 2147483520),
+             (9.223371e18, 9223370937343148032),
+             (9.223372e18, i64::MIN),
+         ];
+         for i in 0..inputs.len() {
+             let (xi, e) = inputs[i];
+             let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0);
+             let r = _mm_cvttss_si64(x);
+             assert_eq!(
+                 e, r,
+                 "TestCase #{} _mm_cvttss_si64({:?}) = {}, expected: {}",
+                 i, x, r, e
+             );
+         }
+     }
+ 
+     #[simd_test(enable = "sse")]
+     unsafe fn test_mm_cvtsi64_ss() {
+         let inputs = &[
+             (4555i64, 4555.0f32),
+             (322223333, 322223330.0),
+             (-432, -432.0),
+             (-322223333, -322223330.0),
+             (9223372036854775807, 9.223372e18),
+             (-9223372036854775808, -9.223372e18),
+         ];
+ 
+         for i in 0..inputs.len() {
+             let (x, f) = inputs[i];
+             let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
+             let r = _mm_cvtsi64_ss(a, x);
+             let e = _mm_setr_ps(f, 6.0, 7.0, 8.0);
+             assert_eq_m128(e, r);
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse2.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse2.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse2.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse2.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,209 ----
+ //! `x86_64`'s Streaming SIMD Extensions 2 (SSE2)
+ 
+ use crate::{
+     core_arch::{simd_llvm::*, x86::*},
+     intrinsics,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse2.cvtsd2si64"]
+     fn cvtsd2si64(a: __m128d) -> i64;
+     #[link_name = "llvm.x86.sse2.cvttsd2si64"]
+     fn cvttsd2si64(a: __m128d) -> i64;
+ }
+ 
+ /// Converts the lower double-precision (64-bit) floating-point element in a to
+ /// a 64-bit integer.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_si64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsd2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsd_si64(a: __m128d) -> i64 {
+     cvtsd2si64(a)
+ }
+ 
+ /// Alias for `_mm_cvtsd_si64`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_si64x)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsd2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsd_si64x(a: __m128d) -> i64 {
+     _mm_cvtsd_si64(a)
+ }
+ 
+ /// Converts the lower double-precision (64-bit) floating-point element in `a`
+ /// to a 64-bit integer with truncation.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_si64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvttsd2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttsd_si64(a: __m128d) -> i64 {
+     cvttsd2si64(a)
+ }
+ 
+ /// Alias for `_mm_cvttsd_si64`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_si64x)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvttsd2si))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvttsd_si64x(a: __m128d) -> i64 {
+     _mm_cvttsd_si64(a)
+ }
+ 
+ /// Stores a 64-bit integer value in the specified memory location.
+ /// To minimize caching, the data is flagged as non-temporal (unlikely to be
+ /// used again soon).
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_si64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(movnti))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_stream_si64(mem_addr: *mut i64, a: i64) {
+     intrinsics::nontemporal_store(mem_addr, a);
+ }
+ 
+ /// Returns a vector whose lowest element is `a` and all higher elements are
+ /// `0`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi64_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(windows)), assert_instr(movq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi64_si128(a: i64) -> __m128i {
+     _mm_set_epi64x(0, a)
+ }
+ 
+ /// Returns a vector whose lowest element is `a` and all higher elements are
+ /// `0`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi64x_si128)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(windows)), assert_instr(movq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
+     _mm_cvtsi64_si128(a)
+ }
+ 
+ /// Returns the lowest element of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si64)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(windows)), assert_instr(movq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
+     simd_extract(a.as_i64x2(), 0)
+ }
+ 
+ /// Returns the lowest element of `a`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si64x)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(all(test, not(windows)), assert_instr(movq))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi128_si64x(a: __m128i) -> i64 {
+     _mm_cvtsi128_si64(a)
+ }
+ 
+ /// Returns `a` with its lower element replaced by `b` after converting it to
+ /// an `f64`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi64_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsi2sd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi64_sd(a: __m128d, b: i64) -> __m128d {
+     simd_insert(a, 0, b as f64)
+ }
+ 
+ /// Returns `a` with its lower element replaced by `b` after converting it to
+ /// an `f64`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi64x_sd)
+ #[inline]
+ #[target_feature(enable = "sse2")]
+ #[cfg_attr(test, assert_instr(cvtsi2sd))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_cvtsi64x_sd(a: __m128d, b: i64) -> __m128d {
+     _mm_cvtsi64_sd(a, b)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arch::x86_64::*;
+     use std::boxed;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsd_si64() {
+         let r = _mm_cvtsd_si64(_mm_setr_pd(-2.0, 5.0));
+         assert_eq!(r, -2_i64);
+ 
+         let r = _mm_cvtsd_si64(_mm_setr_pd(f64::MAX, f64::MIN));
+         assert_eq!(r, i64::MIN);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsd_si64x() {
+         let r = _mm_cvtsd_si64x(_mm_setr_pd(f64::NAN, f64::NAN));
+         assert_eq!(r, i64::MIN);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvttsd_si64() {
+         let a = _mm_setr_pd(-1.1, 2.2);
+         let r = _mm_cvttsd_si64(a);
+         assert_eq!(r, -1_i64);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvttsd_si64x() {
+         let a = _mm_setr_pd(f64::NEG_INFINITY, f64::NAN);
+         let r = _mm_cvttsd_si64x(a);
+         assert_eq!(r, i64::MIN);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_stream_si64() {
+         let a: i64 = 7;
+         let mut mem = boxed::Box::<i64>::new(-1);
+         _mm_stream_si64(&mut *mem as *mut i64, a);
+         assert_eq!(a, *mem);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsi64_si128() {
+         let r = _mm_cvtsi64_si128(5);
+         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsi128_si64() {
+         let r = _mm_cvtsi128_si64(_mm_setr_epi64x(5, 0));
+         assert_eq!(r, 5);
+     }
+ 
+     #[simd_test(enable = "sse2")]
+     unsafe fn test_mm_cvtsi64_sd() {
+         let a = _mm_set1_pd(3.5);
+         let r = _mm_cvtsi64_sd(a, 5);
+         assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,67 ----
+ //! `i686`'s Streaming SIMD Extensions 4.1 (SSE4.1)
+ 
+ use crate::{
+     core_arch::{simd_llvm::*, x86::*},
+     mem::transmute,
+ };
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ /// Extracts an 64-bit integer from `a` selected with `imm8`
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(pextrq, imm8 = 1))]
+ #[rustc_args_required_const(1)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_extract_epi64(a: __m128i, imm8: i32) -> i64 {
+     let a = a.as_i64x2();
+     match imm8 & 1 {
+         0 => simd_extract(a, 0),
+         _ => simd_extract(a, 1),
+     }
+ }
+ 
+ /// Returns a copy of `a` with the 64-bit integer from `i` inserted at a
+ /// location specified by `imm8`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_epi64)
+ #[inline]
+ #[target_feature(enable = "sse4.1")]
+ #[cfg_attr(test, assert_instr(pinsrq, imm8 = 0))]
+ #[rustc_args_required_const(2)]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_insert_epi64(a: __m128i, i: i64, imm8: i32) -> __m128i {
+     let a = a.as_i64x2();
+     match imm8 & 1 {
+         0 => transmute(simd_insert(a, 0, i)),
+         _ => transmute(simd_insert(a, 1, i)),
+     }
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arch::x86_64::*;
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_extract_epi64() {
+         let a = _mm_setr_epi64x(0, 1);
+         let r = _mm_extract_epi64(a, 1);
+         assert_eq!(r, 1);
+         let r = _mm_extract_epi64(a, 3);
+         assert_eq!(r, 1);
+     }
+ 
+     #[simd_test(enable = "sse4.1")]
+     unsafe fn test_mm_insert_epi64() {
+         let a = _mm_set1_epi64x(0);
+         let e = _mm_setr_epi64x(0, 32);
+         let r = _mm_insert_epi64(a, 32, 1);
+         assert_eq_m128i(r, e);
+         let r = _mm_insert_epi64(a, 32, 3);
+         assert_eq_m128i(r, e);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,37 ----
+ //! `x86_64`'s Streaming SIMD Extensions 4.2 (SSE4.2)
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.sse42.crc32.64.64"]
+     fn crc32_64_64(crc: u64, v: u64) -> u64;
+ }
+ 
+ /// Starting with the initial value in `crc`, return the accumulated
+ /// CRC32 value for unsigned 64-bit integer `v`.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_crc32_u64)
+ #[inline]
+ #[target_feature(enable = "sse4.2")]
+ #[cfg_attr(test, assert_instr(crc32))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _mm_crc32_u64(crc: u64, v: u64) -> u64 {
+     crc32_64_64(crc, v)
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::arch::x86_64::*;
+ 
+     use stdarch_test::simd_test;
+ 
+     #[simd_test(enable = "sse4.2")]
+     unsafe fn test_mm_crc32_u64() {
+         let crc = 0x7819dccd3e824;
+         let v = 0x2a22b845fed;
+         let i = _mm_crc32_u64(crc, v);
+         assert_eq!(i, 0xbb6cdc6c);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,227 ----
+ //! `x86_64`'s `xsave` and `xsaveopt` target feature intrinsics
+ 
+ #![allow(clippy::module_name_repetitions)]
+ 
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ 
+ #[allow(improper_ctypes)]
+ extern "C" {
+     #[link_name = "llvm.x86.xsave64"]
+     fn xsave64(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xrstor64"]
+     fn xrstor64(p: *const u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsaveopt64"]
+     fn xsaveopt64(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsavec64"]
+     fn xsavec64(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xsaves64"]
+     fn xsaves64(p: *mut u8, hi: u32, lo: u32) -> ();
+     #[link_name = "llvm.x86.xrstors64"]
+     fn xrstors64(p: *const u8, hi: u32, lo: u32) -> ();
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory at
+ /// `mem_addr`.
+ ///
+ /// State is saved based on bits `[62:0]` in `save_mask` and XCR0.
+ /// `mem_addr` must be aligned on a 64-byte boundary.
+ ///
+ /// The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of
+ /// Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsave64)
+ #[inline]
+ #[target_feature(enable = "xsave")]
+ #[cfg_attr(test, assert_instr(xsave64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsave64(mem_addr: *mut u8, save_mask: u64) {
+     xsave64(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial restore of the enabled processor states using
+ /// the state information stored in memory at `mem_addr`.
+ ///
+ /// State is restored based on bits `[62:0]` in `rs_mask`, `XCR0`, and
+ /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte
+ /// boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstor64)
+ #[inline]
+ #[target_feature(enable = "xsave")]
+ #[cfg_attr(test, assert_instr(xrstor64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xrstor64(mem_addr: *const u8, rs_mask: u64) {
+     xrstor64(mem_addr, (rs_mask >> 32) as u32, rs_mask as u32);
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory at
+ /// `mem_addr`.
+ ///
+ /// State is saved based on bits `[62:0]` in `save_mask` and `XCR0`.
+ /// `mem_addr` must be aligned on a 64-byte boundary. The hardware may optimize
+ /// the manner in which data is saved. The performance of this instruction will
+ /// be equal to or better than using the `XSAVE64` instruction.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaveopt64)
+ #[inline]
+ #[target_feature(enable = "xsave,xsaveopt")]
+ #[cfg_attr(test, assert_instr(xsaveopt64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsaveopt64(mem_addr: *mut u8, save_mask: u64) {
+     xsaveopt64(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory
+ /// at `mem_addr`.
+ ///
+ /// `xsavec` differs from `xsave` in that it uses compaction and that it may
+ /// use init optimization. State is saved based on bits `[62:0]` in `save_mask`
+ /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsavec64)
+ #[inline]
+ #[target_feature(enable = "xsave,xsavec")]
+ #[cfg_attr(test, assert_instr(xsavec64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsavec64(mem_addr: *mut u8, save_mask: u64) {
+     xsavec64(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial save of the enabled processor states to memory at
+ /// `mem_addr`
+ ///
+ /// `xsaves` differs from xsave in that it can save state components
+ /// corresponding to bits set in `IA32_XSS` `MSR` and that it may use the
+ /// modified optimization. State is saved based on bits `[62:0]` in `save_mask`
+ /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaves64)
+ #[inline]
+ #[target_feature(enable = "xsave,xsaves")]
+ #[cfg_attr(test, assert_instr(xsaves64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xsaves64(mem_addr: *mut u8, save_mask: u64) {
+     xsaves64(mem_addr, (save_mask >> 32) as u32, save_mask as u32);
+ }
+ 
+ /// Performs a full or partial restore of the enabled processor states using the
+ /// state information stored in memory at `mem_addr`.
+ ///
+ /// `xrstors` differs from `xrstor` in that it can restore state components
+ /// corresponding to bits set in the `IA32_XSS` `MSR`; `xrstors` cannot restore
+ /// from an `xsave` area in which the extended region is in the standard form.
+ /// State is restored based on bits `[62:0]` in `rs_mask`, `XCR0`, and
+ /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte
+ /// boundary.
+ ///
+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstors64)
+ #[inline]
+ #[target_feature(enable = "xsave,xsaves")]
+ #[cfg_attr(test, assert_instr(xrstors64))]
+ #[stable(feature = "simd_x86", since = "1.27.0")]
+ pub unsafe fn _xrstors64(mem_addr: *const u8, rs_mask: u64) {
+     xrstors64(mem_addr, (rs_mask >> 32) as u32, rs_mask as u32);
+ }
+ 
+ // FIXME: https://github.com/rust-lang/stdarch/issues/209
+ // All these tests fail with Intel SDE.
+ /*
+ #[cfg(test)]
+ mod tests {
+     use crate::core_arch::x86::x86_64::xsave;
+     use stdarch_test::simd_test;
+     use std::fmt;
+ 
+     // FIXME: https://github.com/rust-lang/stdarch/issues/209
+     #[repr(align(64))]
+     struct XsaveArea {
+         // max size for 256-bit registers is 800 bytes:
+         // see https://software.intel.com/en-us/node/682996
+         // max size for 512-bit registers is 2560 bytes:
+         // FIXME: add source
+         data: [u8; 2560],
+     }
+ 
+     impl XsaveArea {
+         fn new() -> XsaveArea {
+             XsaveArea { data: [0; 2560] }
+         }
+         fn ptr(&mut self) -> *mut u8 {
+             &mut self.data[0] as *mut _ as *mut u8
+         }
+     }
+ 
+     impl PartialEq<XsaveArea> for XsaveArea {
+         fn eq(&self, other: &XsaveArea) -> bool {
+             for i in 0..self.data.len() {
+                 if self.data[i] != other.data[i] {
+                     return false;
+                 }
+             }
+             true
+         }
+     }
+ 
+     impl fmt::Debug for XsaveArea {
+         fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+             write!(f, "[")?;
+             for i in 0..self.data.len() {
+                 write!(f, "{}", self.data[i])?;
+                 if i != self.data.len() - 1 {
+                     write!(f, ", ")?;
+                 }
+             }
+             write!(f, "]")
+         }
+     }
+ 
+     #[simd_test(enable = "xsave")]
+     unsafe fn xsave64() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         xsave::_xsave64(a.ptr(), m);
+         xsave::_xrstor64(a.ptr(), m);
+         xsave::_xsave64(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+ 
+     #[simd_test(enable = "xsave,xsaveopt")]
+     unsafe fn xsaveopt64() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         xsave::_xsaveopt64(a.ptr(), m);
+         xsave::_xrstor64(a.ptr(), m);
+         xsave::_xsaveopt64(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+ 
+     #[simd_test(enable = "xsave,xsavec")]
+     unsafe fn xsavec64() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         xsave::_xsavec64(a.ptr(), m);
+         xsave::_xrstor64(a.ptr(), m);
+         xsave::_xsavec64(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+ 
+     #[simd_test(enable = "xsave,xsaves")]
+     unsafe fn xsaves64() {
+         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
+         let mut a = XsaveArea::new();
+         let mut b = XsaveArea::new();
+ 
+         xsave::_xsaves64(a.ptr(), m);
+         xsave::_xrstors64(a.ptr(), m);
+         xsave::_xsaves64(b.ptr(), m);
+         assert_eq!(a, b);
+     }
+ }
+ */
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,63 ----
+ #![feature(stdsimd)]
+ #![allow(clippy::option_unwrap_used, clippy::print_stdout, clippy::use_debug)]
+ 
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ #[macro_use]
+ extern crate std_detect;
+ 
+ #[test]
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ fn x86_all() {
+     println!("sse: {:?}", is_x86_feature_detected!("sse"));
+     println!("sse2: {:?}", is_x86_feature_detected!("sse2"));
+     println!("sse3: {:?}", is_x86_feature_detected!("sse3"));
+     println!("ssse3: {:?}", is_x86_feature_detected!("ssse3"));
+     println!("sse4.1: {:?}", is_x86_feature_detected!("sse4.1"));
+     println!("sse4.2: {:?}", is_x86_feature_detected!("sse4.2"));
+     println!("sse4a: {:?}", is_x86_feature_detected!("sse4a"));
+     println!("avx: {:?}", is_x86_feature_detected!("avx"));
+     println!("avx2: {:?}", is_x86_feature_detected!("avx2"));
+     println!("avx512f {:?}", is_x86_feature_detected!("avx512f"));
+     println!("avx512cd {:?}", is_x86_feature_detected!("avx512cd"));
+     println!("avx512er {:?}", is_x86_feature_detected!("avx512er"));
+     println!("avx512pf {:?}", is_x86_feature_detected!("avx512pf"));
+     println!("avx512bw {:?}", is_x86_feature_detected!("avx512bw"));
+     println!("avx512dq {:?}", is_x86_feature_detected!("avx512dq"));
+     println!("avx512vl {:?}", is_x86_feature_detected!("avx512vl"));
+     println!("avx512_ifma {:?}", is_x86_feature_detected!("avx512ifma"));
+     println!("avx512_vbmi {:?}", is_x86_feature_detected!("avx512vbmi"));
+     println!(
+         "avx512_vpopcntdq {:?}",
+         is_x86_feature_detected!("avx512vpopcntdq")
+     );
+     println!("avx512vbmi2 {:?}", is_x86_feature_detected!("avx512vbmi2"));
+     println!("avx512gfni {:?}", is_x86_feature_detected!("avx512gfni"));
+     println!("avx512vaes {:?}", is_x86_feature_detected!("avx512vaes"));
+     println!(
+         "avx512vpclmulqdq {:?}",
+         is_x86_feature_detected!("avx512vpclmulqdq")
+     );
+     println!("avx512vnni {:?}", is_x86_feature_detected!("avx512vnni"));
+     println!(
+         "avx512bitalg {:?}",
+         is_x86_feature_detected!("avx512bitalg")
+     );
+     println!("avx512bf16 {:?}", is_x86_feature_detected!("avx512bf16"));
+     println!(
+         "avx512vp2intersect {:?}",
+         is_x86_feature_detected!("avx512vp2intersect")
+     );
+     println!("f16c: {:?}", is_x86_feature_detected!("f16c"));
+     println!("fma: {:?}", is_x86_feature_detected!("fma"));
+     println!("abm: {:?}", is_x86_feature_detected!("abm"));
+     println!("bmi: {:?}", is_x86_feature_detected!("bmi1"));
+     println!("bmi2: {:?}", is_x86_feature_detected!("bmi2"));
+     println!("tbm: {:?}", is_x86_feature_detected!("tbm"));
+     println!("popcnt: {:?}", is_x86_feature_detected!("popcnt"));
+     println!("lzcnt: {:?}", is_x86_feature_detected!("lzcnt"));
+     println!("fxsr: {:?}", is_x86_feature_detected!("fxsr"));
+     println!("xsave: {:?}", is_x86_feature_detected!("xsave"));
+     println!("xsaveopt: {:?}", is_x86_feature_detected!("xsaveopt"));
+     println!("xsaves: {:?}", is_x86_feature_detected!("xsaves"));
+     println!("xsavec: {:?}", is_x86_feature_detected!("xsavec"));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/simd-test-macro/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/simd-test-macro/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/simd-test-macro/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/simd-test-macro/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,12 ----
+ [package]
+ name = "simd-test-macro"
+ version = "0.1.0"
+ authors = ["Alex Crichton <alex@alexcrichton.com>"]
+ 
+ [lib]
+ proc-macro = true
+ test = false
+ 
+ [dependencies]
+ proc-macro2 = "1.0"
+ quote = "1.0"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/simd-test-macro/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/simd-test-macro/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/simd-test-macro/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/simd-test-macro/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,151 ----
+ //! Implementation of the `#[simd_test]` macro
+ //!
+ //! This macro expands to a `#[test]` function which tests the local machine
+ //! for the appropriate cfg before calling the inner test function.
+ 
+ extern crate proc_macro;
+ extern crate proc_macro2;
+ #[macro_use]
+ extern crate quote;
+ 
+ use proc_macro2::{Delimiter, Ident, Literal, Span, TokenStream, TokenTree};
+ use quote::ToTokens;
+ use std::env;
+ 
+ fn string(s: &str) -> TokenTree {
+     Literal::string(s).into()
+ }
+ 
+ #[proc_macro_attribute]
+ pub fn simd_test(
+     attr: proc_macro::TokenStream,
+     item: proc_macro::TokenStream,
+ ) -> proc_macro::TokenStream {
+     let tokens = TokenStream::from(attr).into_iter().collect::<Vec<_>>();
+     if tokens.len() != 3 {
+         panic!("expected #[simd_test(enable = \"feature\")]");
+     }
+     match &tokens[0] {
+         TokenTree::Ident(tt) if *tt == "enable" => {}
+         _ => panic!("expected #[simd_test(enable = \"feature\")]"),
+     }
+     match &tokens[1] {
+         TokenTree::Punct(tt) if tt.as_char() == '=' => {}
+         _ => panic!("expected #[simd_test(enable = \"feature\")]"),
+     }
+     let enable_feature = match &tokens[2] {
+         TokenTree::Literal(tt) => tt.to_string(),
+         _ => panic!("expected #[simd_test(enable = \"feature\")]"),
+     };
+     let enable_feature = enable_feature.trim_start_matches('"').trim_end_matches('"');
+     let target_features: Vec<String> = enable_feature
+         .replace('+', "")
+         .split(',')
+         .map(String::from)
+         .collect();
+ 
+     let enable_feature = string(enable_feature);
+     let item = TokenStream::from(item);
+     let name = find_name(item.clone());
+ 
+     let name: TokenStream = name
+         .to_string()
+         .parse()
+         .unwrap_or_else(|_| panic!("failed to parse name: {}", name.to_string()));
+ 
+     let target = env::var("TARGET").expect(
+         "TARGET environment variable should be set for rustc (e.g. TARGET=x86_64-apple-darwin cargo test)"
+     );
+     let mut force_test = false;
+     let macro_test = match target
+         .split('-')
+         .next()
+         .unwrap_or_else(|| panic!("target triple contained no \"-\": {}", target))
+     {
+         "i686" | "x86_64" | "i586" => "is_x86_feature_detected",
+         "arm" | "armv7" => "is_arm_feature_detected",
+         "aarch64" => "is_aarch64_feature_detected",
+         "powerpc" | "powerpcle" => "is_powerpc_feature_detected",
+         "powerpc64" | "powerpc64le" => "is_powerpc64_feature_detected",
+         "mips" | "mipsel" | "mipsisa32r6" | "mipsisa32r6el" => {
+             // FIXME:
+             // On MIPS CI run-time feature detection always returns false due
+             // to this qemu bug: https://bugs.launchpad.net/qemu/+bug/1754372
+             //
+             // This is a workaround to force the MIPS tests to always run on
+             // CI.
+             force_test = true;
+             "is_mips_feature_detected"
+         }
+         "mips64" | "mips64el" | "mipsisa64r6" | "mipsisa64r6el" => {
+             // FIXME: see above
+             force_test = true;
+             "is_mips64_feature_detected"
+         }
+         t => panic!("unknown target: {}", t),
+     };
+     let macro_test = Ident::new(macro_test, Span::call_site());
+ 
+     let mut cfg_target_features = TokenStream::new();
+     for feature in target_features {
+         let q = quote_spanned! {
+             proc_macro2::Span::call_site() =>
+             #macro_test!(#feature) &&
+         };
+         q.to_tokens(&mut cfg_target_features);
+     }
+     let q = quote! { true };
+     q.to_tokens(&mut cfg_target_features);
+ 
+     let test_norun = std::env::var("STDSIMD_TEST_NORUN").is_ok();
+     let maybe_ignore = if test_norun {
+         quote! { #[ignore] }
+     } else {
+         TokenStream::new()
+     };
+ 
+     let ret: TokenStream = quote_spanned! {
+         proc_macro2::Span::call_site() =>
+         #[allow(non_snake_case)]
+         #[test]
+         #maybe_ignore
+         fn #name() {
+             if #force_test | (#cfg_target_features) {
+                 let v = unsafe { #name() };
+                 return v;
+             } else {
+                 ::stdarch_test::assert_skip_test_ok(stringify!(#name));
+             }
+ 
+             #[target_feature(enable = #enable_feature)]
+             #item
+         }
+     };
+     ret.into()
+ }
+ 
+ fn find_name(item: TokenStream) -> Ident {
+     let mut tokens = item.into_iter();
+     while let Some(tok) = tokens.next() {
+         if let TokenTree::Ident(word) = tok {
+             if word == "fn" {
+                 break;
+             }
+         }
+     }
+ 
+     fn get_ident(tt: TokenTree) -> Option<Ident> {
+         match tt {
+             TokenTree::Ident(i) => Some(i),
+             TokenTree::Group(g) if g.delimiter() == Delimiter::None => {
+                 get_ident(g.stream().into_iter().next()?)
+             }
+             _ => None,
+         }
+     }
+ 
+     tokens
+         .next()
+         .and_then(get_ident)
+         .expect("failed to find function name")
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,36 ----
+ [package]
+ name = "std_detect"
+ version = "0.1.5"
+ authors = [
+     "Alex Crichton <alex@alexcrichton.com>",
+     "Andrew Gallant <jamslam@gmail.com>",
+     "Gonzalo Brito Gadeschi <gonzalobg88@gmail.com>",
+ ]
+ description = "`std::detect` - Rust's standard library run-time CPU feature detection."
+ documentation = "https://docs.rs/std_detect"
+ homepage = "https://github.com/rust-lang/stdarch"
+ repository = "https://github.com/rust-lang/stdarch"
+ readme = "README.md"
+ keywords = ["std", "run-time", "feature", "detection"]
+ categories = ["hardware-support"]
+ license = "MIT/Apache-2.0"
+ edition = "2018"
+ 
+ [badges]
+ is-it-maintained-issue-resolution = { repository = "rust-lang/stdarch" }
+ is-it-maintained-open-issues = { repository = "rust-lang/stdarch" }
+ maintenance = { status = "experimental" }
+ 
+ [dependencies]
+ libc = { version = "0.2", optional = true, default-features = false }
+ cfg-if = "0.1.10"
+ 
+ [dev-dependencies]
+ auxv = "0.3.3"
+ cupid = "0.6.0"
+ 
+ [features]
+ default = [ "std_detect_dlsym_getauxval", "std_detect_file_io" ]
+ std_detect_file_io = []
+ std_detect_dlsym_getauxval = [ "libc" ]
+ std_detect_env_override = []
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-APACHE gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-APACHE
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-APACHE	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-APACHE	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,201 ----
+                               Apache License
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diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-MIT gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-MIT
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-MIT	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/LICENSE-MIT	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,25 ----
+ Copyright (c) 2017 The Rust Project Developers
+ 
+ Permission is hereby granted, free of charge, to any
+ person obtaining a copy of this software and associated
+ documentation files (the "Software"), to deal in the
+ Software without restriction, including without
+ limitation the rights to use, copy, modify, merge,
+ publish, distribute, sublicense, and/or sell copies of
+ the Software, and to permit persons to whom the Software
+ is furnished to do so, subject to the following
+ conditions:
+ 
+ The above copyright notice and this permission notice
+ shall be included in all copies or substantial portions
+ of the Software.
+ 
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+ SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+ IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/README.md gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/README.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/README.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/README.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,81 ----
+ `std::detect` - Rust's standard library run-time CPU feature detection
+ =======
+ 
+ [![std_detect_crate_badge]][std_detect_crate_link] [![std_detect_docs_badge]][std_detect_docs_link]
+ 
+ 
+ The private `std::detect` module implements run-time feature detection in Rust's
+ standard library. This allows detecting whether the CPU the binary runs on
+ supports certain features, like SIMD instructions.
+ 
+ # Usage 
+ 
+ `std::detect` APIs are available as part of `libstd`. Prefer using it via the
+ standard library than through this crate. Unstable features of `std::detect` are
+ available on nightly Rust behind the `feature(stdsimd)` feature-gate.
+ 
+ If you need run-time feature detection in `#[no_std]` environments, Rust `core`
+ library cannot help you. By design, Rust `core` is platform independent, but
+ performing run-time feature detection requires a certain level of cooperation
+ from the platform.
+ 
+ You can then manually include `std_detect` as a dependency to get similar
+ run-time feature detection support than the one offered by Rust's standard
+ library. We intend to make `std_detect` more flexible and configurable in this
+ regard to better serve the needs of `#[no_std]` targets. 
+ 
+ # Features
+ 
+ * `std_detect_dlsym_getauxval` (enabled by default, requires `libc`): Enable to
+ use `libc::dlsym` to query whether [`getauxval`] is linked into the binary. When
+ this is not the case, this feature allows other fallback methods to perform
+ run-time feature detection. When this feature is disabled, `std_detect` assumes
+ that [`getauxval`] is linked to the binary. If that is not the case the behavior
+ is undefined.
+ 
+ * `std_detect_file_io` (enabled by default, requires `std`): Enable to perform run-time feature
+ detection using file APIs (e.g. `/proc/cpuinfo`, etc.) if other more performant
+ methods fail. This feature requires `libstd` as a dependency, preventing the
+ crate from working on applications in which `std` is not available.
+ 
+ [`getauxval`]: http://man7.org/linux/man-pages/man3/getauxval.3.html
+ 
+ # Platform support
+ 
+ * All `x86`/`x86_64` targets are supported on all platforms by querying the
+   `cpuid` instruction directly for the features supported by the hardware and
+   the operating system. `std_detect` assumes that the binary is an user-space
+   application. If you need raw support for querying `cpuid`, consider using the
+   [`cupid`](https://crates.io/crates/cupid) crate.
+   
+ * Linux:
+   * `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`: `std_detect`
+     supports these on Linux by querying ELF auxiliary vectors (using `getauxval`
+     when available), and if that fails, by querying `/proc/cpuinfo`. 
+   * `arm64`: partial support for doing run-time feature detection by directly
+     querying `mrs` is implemented for Linux >= 4.11, but not enabled by default.
+ 
+ * FreeBSD:
+   * `arm64`: run-time feature detection is implemented by directly querying `mrs`.
+ 
+ # License
+ 
+ This project is licensed under either of
+ 
+  * Apache License, Version 2.0, ([LICENSE-APACHE](LICENSE-APACHE) or
+    http://www.apache.org/licenses/LICENSE-2.0)
+  * MIT license ([LICENSE-MIT](LICENSE-MIT) or
+    http://opensource.org/licenses/MIT)
+ 
+ at your option.
+ 
+ # Contribution
+ 
+ Unless you explicitly state otherwise, any contribution intentionally submitted
+ for inclusion in `std_detect` by you, as defined in the Apache-2.0 license,
+ shall be dual licensed as above, without any additional terms or conditions.
+ 
+ [std_detect_crate_badge]: https://img.shields.io/crates/v/std_detect.svg
+ [std_detect_crate_link]: https://crates.io/crates/std_detect
+ [std_detect_docs_badge]: https://docs.rs/std_detect/badge.svg
+ [std_detect_docs_link]: https://docs.rs/std_detect/
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,38 ----
+ //! Aarch64 run-time features.
+ 
+ features! {
+     @TARGET: aarch64;
+     @MACRO_NAME: is_aarch64_feature_detected;
+     @MACRO_ATTRS:
+     /// Checks if `aarch64` feature is enabled.
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     @BIND_FEATURE_NAME: "asimd"; "neon";
+     @NO_RUNTIME_DETECTION: "ras";
+     @NO_RUNTIME_DETECTION: "v8.1a";
+     @NO_RUNTIME_DETECTION: "v8.2a";
+     @NO_RUNTIME_DETECTION: "v8.3a";
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] asimd: "neon";
+     /// ARM Advanced SIMD (ASIMD)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] pmull: "pmull";
+     /// Polynomial Multiply
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] fp: "fp";
+     /// Floating point support
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] fp16: "fp16";
+     /// Half-float support.
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] sve: "sve";
+     /// Scalable Vector Extension (SVE)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] crc: "crc";
+     /// CRC32 (Cyclic Redundancy Check)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] crypto: "crypto";
+     /// Crypto: AES + PMULL + SHA1 + SHA2
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] lse: "lse";
+     /// Atomics (Large System Extension)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rdm: "rdm";
+     /// Rounding Double Multiply (ASIMDRDM)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rcpc: "rcpc";
+     /// Release consistent Processor consistent (RcPc)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] dotprod: "dotprod";
+     /// Vector Dot-Product (ASIMDDP)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] tme: "tme";
+     /// Transactional Memory Extensions (TME)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/arm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/arm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/arm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/arm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,21 ----
+ //! Run-time feature detection on ARM Aarch32.
+ 
+ features! {
+     @TARGET: arm;
+     @MACRO_NAME: is_arm_feature_detected;
+     @MACRO_ATTRS:
+     /// Checks if `arm` feature is enabled.
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     @NO_RUNTIME_DETECTION: "v7";
+     @NO_RUNTIME_DETECTION: "vfp2";
+     @NO_RUNTIME_DETECTION: "vfp3";
+     @NO_RUNTIME_DETECTION: "vfp4";
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] neon: "neon";
+     /// ARM Advanced SIMD (NEON) - Aarch32
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] pmull: "pmull";
+     /// Polynomial Multiply
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] crc: "crc";
+     /// CRC32 (Cyclic Redundancy Check)
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] crypto: "crypto";
+     /// Crypto: AES + PMULL + SHA1 + SHA2
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,11 ----
+ //! Run-time feature detection on MIPS.
+ 
+ features! {
+     @TARGET: mips;
+     @MACRO_NAME: is_mips_feature_detected;
+     @MACRO_ATTRS:
+     /// Checks if `mips` feature is enabled.
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] msa: "msa";
+     /// MIPS SIMD Architecture (MSA)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,11 ----
+ //! Run-time feature detection on MIPS64.
+ 
+ features! {
+     @TARGET: mips64;
+     @MACRO_NAME: is_mips64_feature_detected;
+     @MACRO_ATTRS:
+     /// Checks if `mips64` feature is enabled.
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] msa: "msa";
+     /// MIPS SIMD Architecture (MSA)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,15 ----
+ //! Run-time feature detection on PowerPC.
+ 
+ features! {
+     @TARGET: powerpc;
+     @MACRO_NAME: is_powerpc_feature_detected;
+     @MACRO_ATTRS:
+     /// Checks if `powerpc` feature is enabled.
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] altivec: "altivec";
+     /// Altivec
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] vsx: "vsx";
+     /// VSX
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] power8: "power8";
+     /// Power8
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,15 ----
+ //! Run-time feature detection on PowerPC64.
+ 
+ features! {
+     @TARGET: powerpc64;
+     @MACRO_NAME: is_powerpc64_feature_detected;
+     @MACRO_ATTRS:
+     /// Checks if `powerpc` feature is enabled.
+     #[unstable(feature = "stdsimd", issue = "27731")]
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] altivec: "altivec";
+     /// Altivec
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] vsx: "vsx";
+     /// VSX
+     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] power8: "power8";
+     /// Power8
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,196 ----
+ //! This module implements minimal run-time feature detection for x86.
+ //!
+ //! The features are detected using the `detect_features` function below.
+ //! This function uses the CPUID instruction to read the feature flags from the
+ //! CPU and encodes them in an `usize` where each bit position represents
+ //! whether a feature is available (bit is set) or unavaiable (bit is cleared).
+ //!
+ //! The enum `Feature` is used to map bit positions to feature names, and the
+ //! the `__crate::detect::check_for!` macro is used to map string literals (e.g.,
+ //! "avx") to these bit positions (e.g., `Feature::avx`).
+ //!
+ //! The run-time feature detection is performed by the
+ //! `__crate::detect::check_for(Feature) -> bool` function. On its first call,
+ //! this functions queries the CPU for the available features and stores them
+ //! in a global `AtomicUsize` variable. The query is performed by just checking
+ //! whether the feature bit in this global variable is set or cleared.
+ 
+ features! {
+     @TARGET: x86;
+     @MACRO_NAME: is_x86_feature_detected;
+     @MACRO_ATTRS:
+     /// A macro to test at *runtime* whether a CPU feature is available on
+     /// x86/x86-64 platforms.
+     ///
+     /// This macro is provided in the standard library and will detect at runtime
+     /// whether the specified CPU feature is detected. This does **not** resolve at
+     /// compile time unless the specified feature is already enabled for the entire
+     /// crate. Runtime detection currently relies mostly on the `cpuid` instruction.
+     ///
+     /// This macro only takes one argument which is a string literal of the feature
+     /// being tested for. The feature names supported are the lowercase versions of
+     /// the ones defined by Intel in [their documentation][docs].
+     ///
+     /// ## Supported arguments
+     ///
+     /// This macro supports the same names that `#[target_feature]` supports. Unlike
+     /// `#[target_feature]`, however, this macro does not support names separated
+     /// with a comma. Instead testing for multiple features must be done through
+     /// separate macro invocations for now.
+     ///
+     /// Supported arguments are:
+     ///
+     /// * `"aes"`
+     /// * `"pclmulqdq"`
+     /// * `"rdrand"`
+     /// * `"rdseed"`
+     /// * `"tsc"`
+     /// * `"mmx"`
+     /// * `"sse"`
+     /// * `"sse2"`
+     /// * `"sse3"`
+     /// * `"ssse3"`
+     /// * `"sse4.1"`
+     /// * `"sse4.2"`
+     /// * `"sse4a"`
+     /// * `"sha"`
+     /// * `"avx"`
+     /// * `"avx2"`
+     /// * `"avx512f"`
+     /// * `"avx512cd"`
+     /// * `"avx512er"`
+     /// * `"avx512pf"`
+     /// * `"avx512bw"`
+     /// * `"avx512dq"`
+     /// * `"avx512vl"`
+     /// * `"avx512ifma"`
+     /// * `"avx512vbmi"`
+     /// * `"avx512vpopcntdq"`
+     /// * `"avx512vbmi2"`
+     /// * `"avx512gfni"`
+     /// * `"avx512vaes"`
+     /// * `"avx512vpclmulqdq"`
+     /// * `"avx512vnni"`
+     /// * `"avx512bitalg"`
+     /// * `"avx512bf16"`
+     /// * `"avx512vp2intersect"`
+     /// * `"f16c"`
+     /// * `"fma"`
+     /// * `"bmi1"`
+     /// * `"bmi2"`
+     /// * `"abm"`
+     /// * `"lzcnt"`
+     /// * `"tbm"`
+     /// * `"popcnt"`
+     /// * `"fxsr"`
+     /// * `"xsave"`
+     /// * `"xsaveopt"`
+     /// * `"xsaves"`
+     /// * `"xsavec"`
+     /// * `"cmpxchg16b"`
+     /// * `"adx"`
+     /// * `"rtm"`
+     ///
+     /// [docs]: https://software.intel.com/sites/landingpage/IntrinsicsGuide
+     #[stable(feature = "simd_x86", since = "1.27.0")]
+     @BIND_FEATURE_NAME: "abm"; "lzcnt"; // abm is a synonym for lzcnt
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] aes: "aes";
+     /// AES (Advanced Encryption Standard New Instructions AES-NI)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] pclmulqdq: "pclmulqdq";
+     /// CLMUL (Carry-less Multiplication)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdrand: "rdrand";
+     /// RDRAND
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdseed: "rdseed";
+     /// RDSEED
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tsc: "tsc";
+     /// TSC (Time Stamp Counter)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] mmx: "mmx";
+     /// MMX (MultiMedia eXtensions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse: "sse";
+     /// SSE (Streaming SIMD Extensions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse2: "sse2";
+     /// SSE2 (Streaming SIMD Extensions 2)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse3: "sse3";
+     /// SSE3 (Streaming SIMD Extensions 3)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] ssse3: "ssse3";
+     /// SSSE3 (Supplemental Streaming SIMD Extensions 3)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_1: "sse4.1";
+     /// SSE4.1 (Streaming SIMD Extensions 4.1)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4_2: "sse4.2";
+     /// SSE4.2 (Streaming SIMD Extensions 4.2)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse4a: "sse4a";
+     /// SSE4a (Streaming SIMD Extensions 4a)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sha: "sha";
+     /// SHA
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx: "avx";
+     /// AVX (Advanced Vector Extensions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx2: "avx2";
+     /// AVX2 (Advanced Vector Extensions 2)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512f: "avx512f" ;
+     /// AVX-512 F (Foundation)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512cd: "avx512cd" ;
+     /// AVX-512 CD (Conflict Detection Instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512er: "avx512er";
+     /// AVX-512 ER (Expo nential and Reciprocal Instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512pf: "avx512pf";
+     /// AVX-512 PF (Prefetch Instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bw: "avx512bw";
+     /// AVX-512 BW (Byte and Word Instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512dq: "avx512dq";
+     /// AVX-512 DQ (Doubleword and Quadword)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vl: "avx512vl";
+     /// AVX-512 VL (Vector Length Extensions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512ifma: "avx512ifma";
+     /// AVX-512 IFMA (Integer Fused Multiply Add)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi: "avx512vbmi";
+     /// AVX-512 VBMI (Vector Byte Manipulation Instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vpopcntdq: "avx512vpopcntdq";
+     /// AVX-512 VPOPCNTDQ (Vector Population Count Doubleword and
+     /// Quadword)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vbmi2: "avx512vbmi2";
+     /// AVX-512 VBMI2 (Additional byte, word, dword and qword capabilities)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512gfni: "avx512gfni";
+     /// AVX-512 GFNI (Galois Field New Instruction)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vaes: "avx512vaes";
+     /// AVX-512 VAES (Vector AES instruction)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vpclmulqdq: "avx512vpclmulqdq";
+     /// AVX-512 VPCLMULQDQ (Vector PCLMULQDQ instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vnni: "avx512vnni";
+     /// AVX-512 VNNI (Vector Neural Network Instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bitalg: "avx512bitalg";
+     /// AVX-512 BITALG (Support for VPOPCNT[B,W] and VPSHUFBITQMB)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bf16: "avx512bf16";
+     /// AVX-512 BF16 (BFLOAT16 instructions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512vp2intersect: "avx512vp2intersect";
+     /// AVX-512 P2INTERSECT
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] f16c: "f16c";
+     /// F16C (Conversions between IEEE-754 `binary16` and `binary32` formats)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fma: "fma";
+     /// FMA (Fused Multiply Add)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi1: "bmi1" ;
+     /// BMI1 (Bit Manipulation Instructions 1)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] bmi2: "bmi2" ;
+     /// BMI2 (Bit Manipulation Instructions 2)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] lzcnt: "lzcnt";
+     /// ABM (Advanced Bit Manipulation) / LZCNT (Leading Zero Count)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tbm: "tbm";
+     /// TBM (Trailing Bit Manipulation)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] popcnt: "popcnt";
+     /// POPCNT (Population Count)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fxsr: "fxsr";
+     /// FXSR (Floating-point context fast save and restor)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsave: "xsave";
+     /// XSAVE (Save Processor Extended States)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaveopt: "xsaveopt";
+     /// XSAVEOPT (Save Processor Extended States Optimized)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsaves: "xsaves";
+     /// XSAVES (Save Processor Extended States Supervisor)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] xsavec: "xsavec";
+     /// XSAVEC (Save Processor Extended States Compacted)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] cmpxchg16b: "cmpxchg16b";
+     /// CMPXCH16B (16-byte compare-and-swap instruction)
+     @FEATURE: #[stable(feature = "simd_x86_adx", since = "1.33.0")] adx: "adx";
+     /// ADX, Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
+     @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rtm: "rtm";
+     /// RTM, Intel (Restricted Transactional Memory)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,9 ----
+ //! Bit manipulation utilities.
+ 
+ /// Tests the `bit` of `x`.
+ #[allow(dead_code)]
+ #[inline]
+ pub(crate) fn test(x: usize, bit: u32) -> bool {
+     debug_assert!(bit < 32, "bit index out-of-bounds");
+     x & (1 << bit) != 0
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,187 ----
+ //! Caches run-time feature detection so that it only needs to be computed
+ //! once.
+ 
+ #![allow(dead_code)] // not used on all platforms
+ 
+ use crate::sync::atomic::Ordering;
+ 
+ use crate::sync::atomic::AtomicUsize;
+ 
+ /// Sets the `bit` of `x`.
+ #[inline]
+ const fn set_bit(x: u64, bit: u32) -> u64 {
+     x | 1 << bit
+ }
+ 
+ /// Tests the `bit` of `x`.
+ #[inline]
+ const fn test_bit(x: u64, bit: u32) -> bool {
+     x & (1 << bit) != 0
+ }
+ 
+ /// Unset the `bit of `x`.
+ #[inline]
+ const fn unset_bit(x: u64, bit: u32) -> u64 {
+     x & !(1 << bit)
+ }
+ 
+ /// Maximum number of features that can be cached.
+ const CACHE_CAPACITY: u32 = 62;
+ 
+ /// This type is used to initialize the cache
+ #[derive(Copy, Clone)]
+ pub(crate) struct Initializer(u64);
+ 
+ #[allow(clippy::use_self)]
+ impl Default for Initializer {
+     fn default() -> Self {
+         Initializer(0)
+     }
+ }
+ 
+ // NOTE: the `debug_assert!` would catch that we do not add more Features than
+ // the one fitting our cache.
+ impl Initializer {
+     /// Tests the `bit` of the cache.
+     #[inline]
+     pub(crate) fn test(self, bit: u32) -> bool {
+         debug_assert!(
+             bit < CACHE_CAPACITY,
+             "too many features, time to increase the cache size!"
+         );
+         test_bit(self.0, bit)
+     }
+ 
+     /// Sets the `bit` of the cache.
+     #[inline]
+     pub(crate) fn set(&mut self, bit: u32) {
+         debug_assert!(
+             bit < CACHE_CAPACITY,
+             "too many features, time to increase the cache size!"
+         );
+         let v = self.0;
+         self.0 = set_bit(v, bit);
+     }
+ 
+     /// Unsets the `bit` of the cache.
+     #[inline]
+     pub(crate) fn unset(&mut self, bit: u32) {
+         debug_assert!(
+             bit < CACHE_CAPACITY,
+             "too many features, time to increase the cache size!"
+         );
+         let v = self.0;
+         self.0 = unset_bit(v, bit);
+     }
+ }
+ 
+ /// This global variable is a cache of the features supported by the CPU.
+ // Note: on x64, we only use the first slot
+ static CACHE: [Cache; 2] = [Cache::uninitialized(), Cache::uninitialized()];
+ 
+ /// Feature cache with capacity for `size_of::<usize::MAX>() * 8 - 1` features.
+ ///
+ /// Note: 0 is used to represent an uninitialized cache, and (at least) the most
+ /// significant bit is set on any cache which has been initialized.
+ ///
+ /// Note: we use `Relaxed` atomic operations, because we are only interested in
+ /// the effects of operations on a single memory location. That is, we only need
+ /// "modification order", and not the full-blown "happens before".
+ struct Cache(AtomicUsize);
+ 
+ impl Cache {
+     const CAPACITY: u32 = (core::mem::size_of::<usize>() * 8 - 1) as u32;
+     const MASK: usize = (1 << Cache::CAPACITY) - 1;
+     const INITIALIZED_BIT: usize = 1usize << Cache::CAPACITY;
+ 
+     /// Creates an uninitialized cache.
+     #[allow(clippy::declare_interior_mutable_const)]
+     const fn uninitialized() -> Self {
+         Cache(AtomicUsize::new(0))
+     }
+ 
+     /// Is the `bit` in the cache set? Returns `None` if the cache has not been initialized.
+     #[inline]
+     pub(crate) fn test(&self, bit: u32) -> Option<bool> {
+         let cached = self.0.load(Ordering::Relaxed);
+         if cached == 0 {
+             None
+         } else {
+             Some(test_bit(cached as u64, bit))
+         }
+     }
+ 
+     /// Initializes the cache.
+     #[inline]
+     fn initialize(&self, value: usize) -> usize {
+         debug_assert_eq!((value & !Cache::MASK), 0);
+         self.0
+             .store(value | Cache::INITIALIZED_BIT, Ordering::Relaxed);
+         value
+     }
+ }
+ 
+ cfg_if::cfg_if! {
+     if #[cfg(feature = "std_detect_env_override")] {
+         #[inline]
+         fn initialize(mut value: Initializer) -> Initializer {
+             if let Ok(disable) = crate::env::var("RUST_STD_DETECT_UNSTABLE") {
+                 for v in disable.split(" ") {
+                     let _ = super::Feature::from_str(v).map(|v| value.unset(v as u32));
+                 }
+             }
+             do_initialize(value);
+             value
+         }
+     } else {
+         #[inline]
+         fn initialize(value: Initializer) -> Initializer {
+             do_initialize(value);
+             value
+         }
+     }
+ }
+ 
+ #[inline]
+ fn do_initialize(value: Initializer) {
+     CACHE[0].initialize((value.0) as usize & Cache::MASK);
+     CACHE[1].initialize((value.0 >> Cache::CAPACITY) as usize & Cache::MASK);
+ }
+ 
+ // We only have to detect features once, and it's fairly costly, so hint to LLVM
+ // that it should assume that cache hits are more common than misses (which is
+ // the point of caching). It's possibly unfortunate that this function needs to
+ // reach across modules like this to call `os::detect_features`, but it produces
+ // the best code out of several attempted variants.
+ //
+ // The `Initializer` that the cache was initialized with is returned, so that
+ // the caller can call `test()` on it without having to load the value from the
+ // cache again.
+ #[cold]
+ fn detect_and_initialize() -> Initializer {
+     initialize(super::os::detect_features())
+ }
+ 
+ /// Tests the `bit` of the storage. If the storage has not been initialized,
+ /// initializes it with the result of `os::detect_features()`.
+ ///
+ /// On its first invocation, it detects the CPU features and caches them in the
+ /// `CACHE` global variable as an `AtomicU64`.
+ ///
+ /// It uses the `Feature` variant to index into this variable as a bitset. If
+ /// the bit is set, the feature is enabled, and otherwise it is disabled.
+ ///
+ /// If the feature `std_detect_env_override` is enabled looks for the env
+ /// variable `RUST_STD_DETECT_UNSTABLE` and uses its its content to disable
+ /// Features that would had been otherwise detected.
+ #[inline]
+ pub(crate) fn test(bit: u32) -> bool {
+     let (relative_bit, idx) = if bit < Cache::CAPACITY {
+         (bit, 0)
+     } else {
+         (bit - Cache::CAPACITY, 1)
+     };
+     CACHE[idx]
+         .test(relative_bit)
+         .unwrap_or_else(|| detect_and_initialize().test(bit))
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,150 ----
+ //! The `is_{target_arch}_feature_detected!` macro are only available on their
+ //! architecture. These macros provide a better error messages when the user
+ //! attempts to call them in a different architecture.
+ 
+ /// Prevents compilation if `is_x86_feature_detected` is used somewhere
+ /// else than `x86` and `x86_64` targets.
+ #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_x86_feature_detected {
+     ($t: tt) => {
+         compile_error!(
+             r#"
+         is_x86_feature_detected can only be used on x86 and x86_64 targets.
+         You can prevent it from being used in other architectures by
+         guarding it behind a cfg(target_arch) as follows:
+ 
+             #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] {
+                 if is_x86_feature_detected(...) { ... }
+             }
+         "#
+         )
+     };
+ }
+ 
+ /// Prevents compilation if `is_arm_feature_detected` is used somewhere else
+ /// than `ARM` targets.
+ #[cfg(not(target_arch = "arm"))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_arm_feature_detected {
+     ($t:tt) => {
+         compile_error!(
+             r#"
+         is_arm_feature_detected can only be used on ARM targets.
+         You can prevent it from being used in other architectures by
+         guarding it behind a cfg(target_arch) as follows:
+ 
+             #[cfg(target_arch = "arm")] {
+                 if is_arm_feature_detected(...) { ... }
+             }
+         "#
+         )
+     };
+ }
+ 
+ /// Prevents compilation if `is_aarch64_feature_detected` is used somewhere else
+ /// than `aarch64` targets.
+ #[cfg(not(target_arch = "aarch64"))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_aarch64_feature_detected {
+     ($t: tt) => {
+         compile_error!(
+             r#"
+         is_aarch64_feature_detected can only be used on AArch64 targets.
+         You can prevent it from being used in other architectures by
+         guarding it behind a cfg(target_arch) as follows:
+ 
+             #[cfg(target_arch = "aarch64")] {
+                 if is_aarch64_feature_detected(...) { ... }
+             }
+         "#
+         )
+     };
+ }
+ 
+ /// Prevents compilation if `is_powerpc_feature_detected` is used somewhere else
+ /// than `PowerPC` targets.
+ #[cfg(not(target_arch = "powerpc"))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_powerpc_feature_detected {
+     ($t:tt) => {
+         compile_error!(
+             r#"
+ is_powerpc_feature_detected can only be used on PowerPC targets.
+ You can prevent it from being used in other architectures by
+ guarding it behind a cfg(target_arch) as follows:
+ 
+     #[cfg(target_arch = "powerpc")] {
+         if is_powerpc_feature_detected(...) { ... }
+     }
+ "#
+         )
+     };
+ }
+ 
+ /// Prevents compilation if `is_powerpc64_feature_detected` is used somewhere
+ /// else than `PowerPC64` targets.
+ #[cfg(not(target_arch = "powerpc64"))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_powerpc64_feature_detected {
+     ($t:tt) => {
+         compile_error!(
+             r#"
+ is_powerpc64_feature_detected can only be used on PowerPC64 targets.
+ You can prevent it from being used in other architectures by
+ guarding it behind a cfg(target_arch) as follows:
+ 
+     #[cfg(target_arch = "powerpc64")] {
+         if is_powerpc64_feature_detected(...) { ... }
+     }
+ "#
+         )
+     };
+ }
+ 
+ /// Prevents compilation if `is_mips_feature_detected` is used somewhere else
+ /// than `MIPS` targets.
+ #[cfg(not(target_arch = "mips"))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_mips_feature_detected {
+     ($t:tt) => {
+         compile_error!(
+             r#"
+         is_mips_feature_detected can only be used on MIPS targets.
+         You can prevent it from being used in other architectures by
+         guarding it behind a cfg(target_arch) as follows:
+ 
+             #[cfg(target_arch = "mips")] {
+                 if is_mips_feature_detected(...) { ... }
+             }
+         "#
+         )
+     };
+ }
+ 
+ /// Prevents compilation if `is_mips64_feature_detected` is used somewhere else
+ /// than `MIPS64` targets.
+ #[cfg(not(target_arch = "mips64"))]
+ #[macro_export]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ macro_rules! is_mips64_feature_detected {
+     ($t:tt) => {
+         compile_error!(
+             r#"
+         is_mips64_feature_detected can only be used on MIPS64 targets.
+         You can prevent it from being used in other architectures by
+         guarding it behind a cfg(target_arch) as follows:
+ 
+             #[cfg(target_arch = "mips64")] {
+                 if is_mips64_feature_detected(...) { ... }
+             }
+         "#
+         )
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,103 ----
+ #[allow(unused)]
+ macro_rules! features {
+     (
+       @TARGET: $target:ident;
+       @MACRO_NAME: $macro_name:ident;
+       @MACRO_ATTRS: $(#[$macro_attrs:meta])*
+       $(@BIND_FEATURE_NAME: $bind_feature:tt; $feature_impl:tt; )*
+       $(@NO_RUNTIME_DETECTION: $nort_feature:tt; )*
+       $(@FEATURE: #[$stability_attr:meta] $feature:ident: $feature_lit:tt; $(#[$feature_comment:meta])*)*
+     ) => {
+         #[macro_export]
+         $(#[$macro_attrs])*
+         #[allow_internal_unstable(stdsimd_internal)]
+         macro_rules! $macro_name {
+             $(
+                 ($feature_lit) => {
+                     $crate::detect::__is_feature_detected::$feature()
+                 };
+             )*
+             $(
+                 ($bind_feature) => { $macro_name!($feature_impl); };
+             )*
+             $(
+                 ($nort_feature) => {
+                     compile_error!(
+                         concat!(
+                             stringify!(nort_feature),
+                             " feature cannot be detected at run-time"
+                         )
+                     )
+                 };
+             )*
+             ($t:tt,) => {
+                     $macro_name!($t);
+             };
+             ($t:tt) => {
+                 compile_error!(
+                     concat!(
+                         concat!("unknown ", stringify!($target)),
+                         concat!(" target feature: ", $t)
+                     )
+                 )
+             };
+         }
+ 
+         /// Each variant denotes a position in a bitset for a particular feature.
+         ///
+         /// PLEASE: do not use this, it is an implementation detail subject
+         /// to change.
+         #[doc(hidden)]
+         #[allow(non_camel_case_types)]
+         #[derive(Copy, Clone)]
+         #[repr(u8)]
+         #[unstable(feature = "stdsimd_internal", issue = "none")]
+         pub(crate) enum Feature {
+             $(
+                 $(#[$feature_comment])*
+                 $feature,
+             )*
+ 
+             // Do not add variants after last:
+             _last
+         }
+ 
+         impl Feature {
+             pub(crate) fn to_str(self) -> &'static str {
+                 match self {
+                     $(Feature::$feature => $feature_lit,)*
+                     Feature::_last => unreachable!(),
+                 }
+             }
+             #[cfg(feature = "std_detect_env_override")]
+             pub(crate) fn from_str(s: &str) -> Result<Feature, ()> {
+                 match s {
+                     $($feature_lit => Ok(Feature::$feature),)*
+                     _ => Err(())
+                 }
+             }
+         }
+ 
+         /// Each function performs run-time feature detection for a single
+         /// feature. This allow us to use stability attributes on a per feature
+         /// basis.
+         ///
+         /// PLEASE: do not use this, it is an implementation detail subject
+         /// to change.
+         #[doc(hidden)]
+         pub mod __is_feature_detected {
+             $(
+ 
+                 /// PLEASE: do not use this, it is an implementation detail
+                 /// subject to change.
+                 #[inline]
+                 #[doc(hidden)]
+                 #[$stability_attr]
+                 pub fn $feature() -> bool {
+                     cfg!(target_feature = $feature_lit) ||
+                         $crate::detect::check_for($crate::detect::Feature::$feature)
+                 }
+             )*
+         }
+     };
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,152 ----
+ //! This module implements run-time feature detection.
+ //!
+ //! The `is_{arch}_feature_detected!("feature-name")` macros take the name of a
+ //! feature as a string-literal, and return a boolean indicating whether the
+ //! feature is enabled at run-time or not.
+ //!
+ //! These macros do two things:
+ //! * map the string-literal into an integer stored as a `Feature` enum,
+ //! * call a `os::check_for(x: Feature)` function that returns `true` if the
+ //! feature is enabled.
+ //!
+ //! The `Feature` enums are also implemented in the `arch/{target_arch}.rs`
+ //! modules.
+ //!
+ //! The `check_for` functions are, in general, Operating System dependent. Most
+ //! architectures do not allow user-space programs to query the feature bits
+ //! due to security concerns (x86 is the big exception). These functions are
+ //! implemented in the `os/{target_os}.rs` modules.
+ 
+ use cfg_if::cfg_if;
+ 
+ #[macro_use]
+ mod error_macros;
+ 
+ #[macro_use]
+ mod macros;
+ 
+ cfg_if! {
+     if #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] {
+         #[path = "arch/x86.rs"]
+         #[macro_use]
+         mod arch;
+     } else if #[cfg(target_arch = "arm")] {
+         #[path = "arch/arm.rs"]
+         #[macro_use]
+         mod arch;
+     } else if #[cfg(target_arch = "aarch64")] {
+         #[path = "arch/aarch64.rs"]
+         #[macro_use]
+         mod arch;
+     } else if #[cfg(target_arch = "powerpc")] {
+         #[path = "arch/powerpc.rs"]
+         #[macro_use]
+         mod arch;
+     } else if #[cfg(target_arch = "powerpc64")] {
+         #[path = "arch/powerpc64.rs"]
+         #[macro_use]
+         mod arch;
+     } else if #[cfg(target_arch = "mips")] {
+         #[path = "arch/mips.rs"]
+         #[macro_use]
+         mod arch;
+     } else if #[cfg(target_arch = "mips64")] {
+         #[path = "arch/mips64.rs"]
+         #[macro_use]
+         mod arch;
+     } else {
+         // Unimplemented architecture:
+         #[allow(dead_code)]
+         mod arch {
+             #[doc(hidden)]
+             pub(crate) enum Feature {
+                 Null
+             }
+             #[doc(hidden)]
+             pub mod __is_feature_detected {}
+ 
+             impl Feature {
+                 #[doc(hidden)]
+                 pub(crate) fn from_str(_s: &str) -> Result<Feature, ()> { Err(()) }
+                 #[doc(hidden)]
+                 pub(crate) fn to_str(self) -> &'static str { "" }
+             }
+         }
+     }
+ }
+ 
+ // This module needs to be public because the `is_{arch}_feature_detected!`
+ // macros expand calls to items within it in user crates.
+ #[doc(hidden)]
+ pub use self::arch::__is_feature_detected;
+ 
+ pub(crate) use self::arch::Feature;
+ 
+ mod bit;
+ mod cache;
+ 
+ cfg_if! {
+     if #[cfg(miri)] {
+         // When running under miri all target-features that are not enabled at
+         // compile-time are reported as disabled at run-time.
+         //
+         // For features for which `cfg(target_feature)` returns true,
+         // this run-time detection logic is never called.
+         #[path = "os/other.rs"]
+         mod os;
+     } else if #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] {
+         // On x86/x86_64 no OS specific functionality is required.
+         #[path = "os/x86.rs"]
+         mod os;
+     } else if #[cfg(all(target_os = "linux", feature = "use_std"))] {
+         #[path = "os/linux/mod.rs"]
+         mod os;
+     } else if #[cfg(all(target_os = "freebsd", feature = "use_std"))] {
+         #[cfg(target_arch = "aarch64")]
+         #[path = "os/aarch64.rs"]
+         mod aarch64;
+         #[path = "os/freebsd/mod.rs"]
+         mod os;
+     } else if #[cfg(all(target_os = "windows", target_arch = "aarch64"))] {
+         #[path = "os/windows/aarch64.rs"]
+         mod os;
+     } else {
+         #[path = "os/other.rs"]
+         mod os;
+     }
+ }
+ 
+ /// Performs run-time feature detection.
+ #[inline]
+ #[allow(dead_code)]
+ fn check_for(x: Feature) -> bool {
+     cache::test(x as u32)
+ }
+ 
+ /// Returns an `Iterator<Item=(&'static str, bool)>` where
+ /// `Item.0` is the feature name, and `Item.1` is a `bool` which
+ /// is `true` if the feature is supported by the host and `false` otherwise.
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ pub fn features() -> impl Iterator<Item = (&'static str, bool)> {
+     cfg_if! {
+         if #[cfg(any(
+             target_arch = "x86",
+             target_arch = "x86_64",
+             target_arch = "arm",
+             target_arch = "aarch64",
+             target_arch = "powerpc",
+             target_arch = "powerpc64",
+             target_arch = "mips",
+             target_arch = "mips64",
+         ))] {
+             (0_u8..Feature::_last as u8).map(|discriminant: u8| {
+                 let f: Feature = unsafe { crate::mem::transmute(discriminant) };
+                 let name: &'static str = f.to_str();
+                 let enabled: bool = check_for(f);
+                 (name, enabled)
+             })
+         } else {
+             None.into_iter()
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,89 ----
+ //! Run-time feature detection for Aarch64 on any OS that emulates the mrs instruction.
+ //!
+ //! On FreeBSD >= 12.0, Linux >= 4.11 and other operating systems, it is possible to use
+ //! privileged system registers from userspace to check CPU feature support.
+ //!
+ //! AArch64 system registers ID_AA64ISAR0_EL1, ID_AA64PFR0_EL1, ID_AA64ISAR1_EL1
+ //! have bits dedicated to features like AdvSIMD, CRC32, AES, atomics (LSE), etc.
+ //! Each part of the register indicates the level of support for a certain feature, e.g.
+ //! when ID_AA64ISAR0_EL1\[7:4\] is >= 1, AES is supported; when it's >= 2, PMULL is supported.
+ //!
+ //! For proper support of [SoCs where different cores have different capabilities](https://medium.com/@jadr2ddude/a-big-little-problem-a-tale-of-big-little-gone-wrong-e7778ce744bb),
+ //! the OS has to always report only the features supported by all cores, like [FreeBSD does](https://reviews.freebsd.org/D17137#393947).
+ //!
+ //! References:
+ //!
+ //! - [Zircon implementation](https://fuchsia.googlesource.com/zircon/+/master/kernel/arch/arm64/feature.cpp)
+ //! - [Linux documentation](https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt)
+ 
+ use crate::detect::{cache, Feature};
+ 
+ /// Try to read the features from the system registers.
+ ///
+ /// This will cause SIGILL if the current OS is not trapping the mrs instruction.
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+ 
+     {
+         let mut enable_feature = |f, enable| {
+             if enable {
+                 value.set(f as u32);
+             }
+         };
+ 
+         // ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+         let aa64isar0: u64;
+         unsafe {
+             llvm_asm!("mrs $0, ID_AA64ISAR0_EL1" : "=r"(aa64isar0));
+         }
+ 
+         let aes = bits_shift(aa64isar0, 7, 4) >= 1;
+         let pmull = bits_shift(aa64isar0, 7, 4) >= 2;
+         let sha1 = bits_shift(aa64isar0, 11, 8) >= 1;
+         let sha2 = bits_shift(aa64isar0, 15, 12) >= 1;
+         enable_feature(Feature::pmull, pmull);
+         // Crypto is specified as AES + PMULL + SHA1 + SHA2 per LLVM/hosts.cpp
+         enable_feature(Feature::crypto, aes && pmull && sha1 && sha2);
+         enable_feature(Feature::tme, bits_shift(aa64isar0, 27, 24) == 1);
+         enable_feature(Feature::lse, bits_shift(aa64isar0, 23, 20) >= 1);
+         enable_feature(Feature::crc, bits_shift(aa64isar0, 19, 16) >= 1);
+ 
+         // ID_AA64PFR0_EL1 - Processor Feature Register 0
+         let aa64pfr0: u64;
+         unsafe {
+             llvm_asm!("mrs $0, ID_AA64PFR0_EL1" : "=r"(aa64pfr0));
+         }
+ 
+         let fp = bits_shift(aa64pfr0, 19, 16) < 0xF;
+         let fphp = bits_shift(aa64pfr0, 19, 16) >= 1;
+         let asimd = bits_shift(aa64pfr0, 23, 20) < 0xF;
+         let asimdhp = bits_shift(aa64pfr0, 23, 20) >= 1;
+         enable_feature(Feature::fp, fp);
+         enable_feature(Feature::fp16, fphp);
+         // SIMD support requires float support - if half-floats are
+         // supported, it also requires half-float support:
+         enable_feature(Feature::asimd, fp && asimd && (!fphp | asimdhp));
+         // SIMD extensions require SIMD support:
+         enable_feature(Feature::rdm, asimd && bits_shift(aa64isar0, 31, 28) >= 1);
+         enable_feature(
+             Feature::dotprod,
+             asimd && bits_shift(aa64isar0, 47, 44) >= 1,
+         );
+         enable_feature(Feature::sve, asimd && bits_shift(aa64pfr0, 35, 32) >= 1);
+ 
+         // ID_AA64ISAR1_EL1 - Instruction Set Attribute Register 1
+         let aa64isar1: u64;
+         unsafe {
+             llvm_asm!("mrs $0, ID_AA64ISAR1_EL1" : "=r"(aa64isar1));
+         }
+ 
+         enable_feature(Feature::rcpc, bits_shift(aa64isar1, 23, 20) >= 1);
+     }
+ 
+     value
+ }
+ 
+ #[inline]
+ fn bits_shift(x: u64, high: usize, low: usize) -> u64 {
+     (x >> low) & ((1 << (high - low + 1)) - 1)
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,22 ----
+ //! Run-time feature detection for Aarch64 on FreeBSD.
+ 
+ pub use super::super::aarch64::detect_features;
+ 
+ #[cfg(test)]
+ mod tests {
+     #[test]
+     fn dump() {
+         println!("asimd: {:?}", is_aarch64_feature_detected!("asimd"));
+         println!("pmull: {:?}", is_aarch64_feature_detected!("pmull"));
+         println!("fp: {:?}", is_aarch64_feature_detected!("fp"));
+         println!("fp16: {:?}", is_aarch64_feature_detected!("fp16"));
+         println!("sve: {:?}", is_aarch64_feature_detected!("sve"));
+         println!("crc: {:?}", is_aarch64_feature_detected!("crc"));
+         println!("crypto: {:?}", is_aarch64_feature_detected!("crypto"));
+         println!("lse: {:?}", is_aarch64_feature_detected!("lse"));
+         println!("rdm: {:?}", is_aarch64_feature_detected!("rdm"));
+         println!("rcpc: {:?}", is_aarch64_feature_detected!("rcpc"));
+         println!("dotprod: {:?}", is_aarch64_feature_detected!("dotprod"));
+         println!("tme: {:?}", is_aarch64_feature_detected!("tme"));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,21 ----
+ //! Run-time feature detection for ARM on FreeBSD
+ 
+ use super::auxvec;
+ use crate::detect::{cache, Feature};
+ 
+ /// Try to read the features from the auxiliary vector
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+     let enable_feature = |value: &mut cache::Initializer, f, enable| {
+         if enable {
+             value.set(f as u32);
+         }
+     };
+ 
+     if let Ok(auxv) = auxvec::auxv() {
+         enable_feature(&mut value, Feature::neon, auxv.hwcap & 0x00001000 != 0);
+         enable_feature(&mut value, Feature::pmull, auxv.hwcap2 & 0x00000002 != 0);
+         return value;
+     }
+     value
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,94 ----
+ //! Parses ELF auxiliary vectors.
+ #![cfg_attr(any(target_arch = "arm", target_arch = "powerpc64"), allow(dead_code))]
+ 
+ /// Key to access the CPU Hardware capabilities bitfield.
+ pub(crate) const AT_HWCAP: usize = 25;
+ /// Key to access the CPU Hardware capabilities 2 bitfield.
+ pub(crate) const AT_HWCAP2: usize = 26;
+ 
+ /// Cache HWCAP bitfields of the ELF Auxiliary Vector.
+ ///
+ /// If an entry cannot be read all the bits in the bitfield are set to zero.
+ /// This should be interpreted as all the features being disabled.
+ #[derive(Debug, Copy, Clone)]
+ pub(crate) struct AuxVec {
+     pub hwcap: usize,
+     pub hwcap2: usize,
+ }
+ 
+ /// ELF Auxiliary Vector
+ ///
+ /// The auxiliary vector is a memory region in a running ELF program's stack
+ /// composed of (key: usize, value: usize) pairs.
+ ///
+ /// The keys used in the aux vector are platform dependent. For FreeBSD, they are
+ /// defined in [sys/elf_common.h][elf_common_h]. The hardware capabilities of a given
+ /// CPU can be queried with the  `AT_HWCAP` and `AT_HWCAP2` keys.
+ ///
+ /// Note that run-time feature detection is not invoked for features that can
+ /// be detected at compile-time.
+ ///
+ /// [elf_common.h]: https://svnweb.freebsd.org/base/release/12.0.0/sys/sys/elf_common.h?revision=341707
+ pub(crate) fn auxv() -> Result<AuxVec, ()> {
+     if let Ok(hwcap) = archauxv(AT_HWCAP) {
+         if let Ok(hwcap2) = archauxv(AT_HWCAP2) {
+             if hwcap != 0 && hwcap2 != 0 {
+                 return Ok(AuxVec { hwcap, hwcap2 });
+             }
+         }
+     }
+     Err(())
+ }
+ 
+ /// Tries to read the `key` from the auxiliary vector.
+ fn archauxv(key: usize) -> Result<usize, ()> {
+     use crate::mem;
+ 
+     #[derive(Copy, Clone)]
+     #[repr(C)]
+     pub struct Elf_Auxinfo {
+         pub a_type: usize,
+         pub a_un: unnamed,
+     }
+     #[derive(Copy, Clone)]
+     #[repr(C)]
+     pub union unnamed {
+         pub a_val: libc::c_long,
+         pub a_ptr: *mut libc::c_void,
+         pub a_fcn: Option<unsafe extern "C" fn() -> ()>,
+     }
+ 
+     let mut auxv: [Elf_Auxinfo; 27] = [Elf_Auxinfo {
+         a_type: 0,
+         a_un: unnamed { a_val: 0 },
+     }; 27];
+ 
+     let mut len: libc::c_uint = mem::size_of_val(&auxv) as libc::c_uint;
+ 
+     unsafe {
+         let mut mib = [
+             libc::CTL_KERN,
+             libc::KERN_PROC,
+             libc::KERN_PROC_AUXV,
+             libc::getpid(),
+         ];
+ 
+         let ret = libc::sysctl(
+             mib.as_mut_ptr(),
+             mib.len() as u32,
+             &mut auxv as *mut _ as *mut _,
+             &mut len as *mut _ as *mut _,
+             0 as *mut libc::c_void,
+             0,
+         );
+ 
+         if ret != -1 {
+             for i in 0..auxv.len() {
+                 if auxv[i].a_type == key {
+                     return Ok(auxv[i].a_un.a_val as usize);
+                 }
+             }
+         }
+     }
+     return Ok(0);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,22 ----
+ //! Run-time feature detection on FreeBSD
+ 
+ mod auxvec;
+ 
+ cfg_if::cfg_if! {
+     if #[cfg(target_arch = "aarch64")] {
+         mod aarch64;
+         pub use self::aarch64::check_for;
+     } else if #[cfg(target_arch = "arm")] {
+         mod arm;
+         pub use self::arm::check_for;
+     } else if #[cfg(target_arch = "powerpc64")] {
+         mod powerpc;
+         pub use self::powerpc::check_for;
+     } else {
+         use crate::arch::detect::Feature;
+         /// Performs run-time feature detection.
+         pub fn check_for(_x: Feature) -> bool {
+             false
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,21 ----
+ //! Run-time feature detection for PowerPC on FreeBSD.
+ 
+ use super::auxvec;
+ use crate::detect::{cache, Feature};
+ 
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+     let enable_feature = |value: &mut cache::Initializer, f, enable| {
+         if enable {
+             value.set(f as u32);
+         }
+     };
+ 
+     if let Ok(auxv) = auxvec::auxv() {
+         enable_feature(&mut value, Feature::altivec, auxv.hwcap & 0x10000000 != 0);
+         enable_feature(&mut value, Feature::vsx, auxv.hwcap & 0x00000080 != 0);
+         enable_feature(&mut value, Feature::power8, auxv.hwcap2 & 0x80000000 != 0);
+         return value;
+     }
+     value
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,154 ----
+ //! Run-time feature detection for Aarch64 on Linux.
+ 
+ use super::{auxvec, cpuinfo};
+ use crate::detect::{bit, cache, Feature};
+ 
+ /// Try to read the features from the auxiliary vector, and if that fails, try
+ /// to read them from /proc/cpuinfo.
+ pub(crate) fn detect_features() -> cache::Initializer {
+     if let Ok(auxv) = auxvec::auxv() {
+         let hwcap: AtHwcap = auxv.into();
+         return hwcap.cache();
+     }
+     if let Ok(c) = cpuinfo::CpuInfo::new() {
+         let hwcap: AtHwcap = c.into();
+         return hwcap.cache();
+     }
+     cache::Initializer::default()
+ }
+ 
+ /// These values are part of the platform-specific [asm/hwcap.h][hwcap] .
+ ///
+ /// [hwcap]: https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/hwcap.h
+ struct AtHwcap {
+     fp: bool,    // 0
+     asimd: bool, // 1
+     // evtstrm: bool, // 2
+     aes: bool,     // 3
+     pmull: bool,   // 4
+     sha1: bool,    // 5
+     sha2: bool,    // 6
+     crc32: bool,   // 7
+     atomics: bool, // 8
+     fphp: bool,    // 9
+     asimdhp: bool, // 10
+     // cpuid: bool, // 11
+     asimdrdm: bool, // 12
+     // jscvt: bool, // 13
+     // fcma: bool, // 14
+     lrcpc: bool, // 15
+     // dcpop: bool, // 16
+     // sha3: bool, // 17
+     // sm3: bool, // 18
+     // sm4: bool, // 19
+     asimddp: bool, // 20
+     // sha512: bool, // 21
+     sve: bool, // 22
+ }
+ 
+ impl From<auxvec::AuxVec> for AtHwcap {
+     /// Reads AtHwcap from the auxiliary vector.
+     fn from(auxv: auxvec::AuxVec) -> Self {
+         AtHwcap {
+             fp: bit::test(auxv.hwcap, 0),
+             asimd: bit::test(auxv.hwcap, 1),
+             // evtstrm: bit::test(auxv.hwcap, 2),
+             aes: bit::test(auxv.hwcap, 3),
+             pmull: bit::test(auxv.hwcap, 4),
+             sha1: bit::test(auxv.hwcap, 5),
+             sha2: bit::test(auxv.hwcap, 6),
+             crc32: bit::test(auxv.hwcap, 7),
+             atomics: bit::test(auxv.hwcap, 8),
+             fphp: bit::test(auxv.hwcap, 9),
+             asimdhp: bit::test(auxv.hwcap, 10),
+             // cpuid: bit::test(auxv.hwcap, 11),
+             asimdrdm: bit::test(auxv.hwcap, 12),
+             // jscvt: bit::test(auxv.hwcap, 13),
+             // fcma: bit::test(auxv.hwcap, 14),
+             lrcpc: bit::test(auxv.hwcap, 15),
+             // dcpop: bit::test(auxv.hwcap, 16),
+             // sha3: bit::test(auxv.hwcap, 17),
+             // sm3: bit::test(auxv.hwcap, 18),
+             // sm4: bit::test(auxv.hwcap, 19),
+             asimddp: bit::test(auxv.hwcap, 20),
+             // sha512: bit::test(auxv.hwcap, 21),
+             sve: bit::test(auxv.hwcap, 22),
+         }
+     }
+ }
+ 
+ impl From<cpuinfo::CpuInfo> for AtHwcap {
+     /// Reads AtHwcap from /proc/cpuinfo .
+     fn from(c: cpuinfo::CpuInfo) -> Self {
+         let f = &c.field("Features");
+         AtHwcap {
+             // 64-bit names. FIXME: In 32-bit compatibility mode /proc/cpuinfo will
+             // map some of the 64-bit names to some 32-bit feature names. This does not
+             // cover that yet.
+             fp: f.has("fp"),
+             asimd: f.has("asimd"),
+             // evtstrm: f.has("evtstrm"),
+             aes: f.has("aes"),
+             pmull: f.has("pmull"),
+             sha1: f.has("sha1"),
+             sha2: f.has("sha2"),
+             crc32: f.has("crc32"),
+             atomics: f.has("atomics"),
+             fphp: f.has("fphp"),
+             asimdhp: f.has("asimdhp"),
+             // cpuid: f.has("cpuid"),
+             asimdrdm: f.has("asimdrdm"),
+             // jscvt: f.has("jscvt"),
+             // fcma: f.has("fcma"),
+             lrcpc: f.has("lrcpc"),
+             // dcpop: f.has("dcpop"),
+             // sha3: f.has("sha3"),
+             // sm3: f.has("sm3"),
+             // sm4: f.has("sm4"),
+             asimddp: f.has("asimddp"),
+             // sha512: f.has("sha512"),
+             sve: f.has("sve"),
+         }
+     }
+ }
+ 
+ impl AtHwcap {
+     /// Initializes the cache from the feature -bits.
+     ///
+     /// The features are enabled approximately like in LLVM host feature detection:
+     /// https://github.com/llvm-mirror/llvm/blob/master/lib/Support/Host.cpp#L1273
+     fn cache(self) -> cache::Initializer {
+         let mut value = cache::Initializer::default();
+         {
+             let mut enable_feature = |f, enable| {
+                 if enable {
+                     value.set(f as u32);
+                 }
+             };
+ 
+             enable_feature(Feature::fp, self.fp);
+             // Half-float support requires float support
+             enable_feature(Feature::fp16, self.fp && self.fphp);
+             enable_feature(Feature::pmull, self.pmull);
+             enable_feature(Feature::crc, self.crc32);
+             enable_feature(Feature::lse, self.atomics);
+             enable_feature(Feature::rcpc, self.lrcpc);
+ 
+             // SIMD support requires float support - if half-floats are
+             // supported, it also requires half-float support:
+             let asimd = self.fp && self.asimd && (!self.fphp | self.asimdhp);
+             enable_feature(Feature::asimd, asimd);
+             // SIMD extensions require SIMD support:
+             enable_feature(Feature::rdm, self.asimdrdm && asimd);
+             enable_feature(Feature::dotprod, self.asimddp && asimd);
+             enable_feature(Feature::sve, self.sve && asimd);
+ 
+             // Crypto is specified as AES + PMULL + SHA1 + SHA2 per LLVM/hosts.cpp
+             enable_feature(
+                 Feature::crypto,
+                 self.aes && self.pmull && self.sha1 && self.sha2,
+             );
+         }
+         value
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,64 ----
+ //! Run-time feature detection for ARM on Linux.
+ 
+ use super::{auxvec, cpuinfo};
+ use crate::detect::{bit, cache, Feature};
+ 
+ /// Try to read the features from the auxiliary vector, and if that fails, try
+ /// to read them from /proc/cpuinfo.
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+     let enable_feature = |value: &mut cache::Initializer, f, enable| {
+         if enable {
+             value.set(f as u32);
+         }
+     };
+ 
+     // The values are part of the platform-specific [asm/hwcap.h][hwcap]
+     //
+     // [hwcap]: https://github.com/torvalds/linux/blob/master/arch/arm/include/uapi/asm/hwcap.h
+     if let Ok(auxv) = auxvec::auxv() {
+         enable_feature(&mut value, Feature::neon, bit::test(auxv.hwcap, 12));
+         enable_feature(&mut value, Feature::pmull, bit::test(auxv.hwcap2, 1));
+         enable_feature(&mut value, Feature::crc, bit::test(auxv.hwcap2, 4));
+         enable_feature(
+             &mut value,
+             Feature::crypto,
+             bit::test(auxv.hwcap2, 0)
+                 && bit::test(auxv.hwcap2, 1)
+                 && bit::test(auxv.hwcap2, 2)
+                 && bit::test(auxv.hwcap2, 3),
+         );
+         return value;
+     }
+ 
+     if let Ok(c) = cpuinfo::CpuInfo::new() {
+         enable_feature(
+             &mut value,
+             Feature::neon,
+             c.field("Features").has("neon") && !has_broken_neon(&c),
+         );
+         enable_feature(&mut value, Feature::pmull, c.field("Features").has("pmull"));
+         enable_feature(&mut value, Feature::crc, c.field("Features").has("crc32"));
+         enable_feature(
+             &mut value,
+             Feature::crypto,
+             c.field("Features").has("aes")
+                 && c.field("Features").has("pmull")
+                 && c.field("Features").has("sha1")
+                 && c.field("Features").has("sha2"),
+         );
+         return value;
+     }
+     value
+ }
+ 
+ /// Is the CPU known to have a broken NEON unit?
+ ///
+ /// See https://crbug.com/341598.
+ fn has_broken_neon(cpuinfo: &cpuinfo::CpuInfo) -> bool {
+     cpuinfo.field("CPU implementer") == "0x51"
+         && cpuinfo.field("CPU architecture") == "7"
+         && cpuinfo.field("CPU variant") == "0x1"
+         && cpuinfo.field("CPU part") == "0x04d"
+         && cpuinfo.field("CPU revision") == "0"
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,304 ----
+ //! Parses ELF auxiliary vectors.
+ #![cfg_attr(not(target_arch = "aarch64"), allow(dead_code))]
+ 
+ #[cfg(feature = "std_detect_file_io")]
+ use crate::{fs::File, io::Read};
+ 
+ /// Key to access the CPU Hardware capabilities bitfield.
+ pub(crate) const AT_HWCAP: usize = 16;
+ /// Key to access the CPU Hardware capabilities 2 bitfield.
+ #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+ pub(crate) const AT_HWCAP2: usize = 26;
+ 
+ /// Cache HWCAP bitfields of the ELF Auxiliary Vector.
+ ///
+ /// If an entry cannot be read all the bits in the bitfield are set to zero.
+ /// This should be interpreted as all the features being disabled.
+ #[derive(Debug, Copy, Clone)]
+ pub(crate) struct AuxVec {
+     pub hwcap: usize,
+     #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+     pub hwcap2: usize,
+ }
+ 
+ /// ELF Auxiliary Vector
+ ///
+ /// The auxiliary vector is a memory region in a running ELF program's stack
+ /// composed of (key: usize, value: usize) pairs.
+ ///
+ /// The keys used in the aux vector are platform dependent. For Linux, they are
+ /// defined in [linux/auxvec.h][auxvec_h]. The hardware capabilities of a given
+ /// CPU can be queried with the  `AT_HWCAP` and `AT_HWCAP2` keys.
+ ///
+ /// There is no perfect way of reading the auxiliary vector.
+ ///
+ /// - If the `std_detect_dlsym_getauxval` cargo feature is enabled, this will use
+ /// `getauxval` if its linked to the binary, and otherwise proceed to a fallback implementation.
+ /// When `std_detect_dlsym_getauxval` is disabled, this will assume that `getauxval` is
+ /// linked to the binary - if that is not the case the behavior is undefined.
+ /// - Otherwise, if the `std_detect_file_io` cargo feature is enabled, it will
+ ///   try to read `/proc/self/auxv`.
+ /// - If that fails, this function returns an error.
+ ///
+ /// Note that run-time feature detection is not invoked for features that can
+ /// be detected at compile-time. Also note that if this function returns an
+ /// error, cpuinfo still can (and will) be used to try to perform run-time
+ /// feature detecton on some platforms.
+ ///
+ /// For more information about when `getauxval` is available check the great
+ /// [`auxv` crate documentation][auxv_docs].
+ ///
+ /// [auxvec_h]: https://github.com/torvalds/linux/blob/master/include/uapi/linux/auxvec.h
+ /// [auxv_docs]: https://docs.rs/auxv/0.3.3/auxv/
+ pub(crate) fn auxv() -> Result<AuxVec, ()> {
+     #[cfg(feature = "std_detect_dlsym_getauxval")]
+     {
+         // Try to call a dynamically-linked getauxval function.
+         if let Ok(hwcap) = getauxval(AT_HWCAP) {
+             // Targets with only AT_HWCAP:
+             #[cfg(any(target_arch = "aarch64", target_arch = "mips", target_arch = "mips64"))]
+             {
+                 if hwcap != 0 {
+                     return Ok(AuxVec { hwcap });
+                 }
+             }
+ 
+             // Targets with AT_HWCAP and AT_HWCAP2:
+             #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+             {
+                 if let Ok(hwcap2) = getauxval(AT_HWCAP2) {
+                     if hwcap != 0 && hwcap2 != 0 {
+                         return Ok(AuxVec { hwcap, hwcap2 });
+                     }
+                 }
+             }
+             drop(hwcap);
+         }
+         #[cfg(feature = "std_detect_file_io")]
+         {
+             // If calling getauxval fails, try to read the auxiliary vector from
+             // its file:
+             auxv_from_file("/proc/self/auxv")
+         }
+         #[cfg(not(feature = "std_detect_file_io"))]
+         {
+             Err(())
+         }
+     }
+ 
+     #[cfg(not(feature = "std_detect_dlsym_getauxval"))]
+     {
+         let hwcap = unsafe { ffi_getauxval(AT_HWCAP) };
+ 
+         // Targets with only AT_HWCAP:
+         #[cfg(any(target_arch = "aarch64", target_arch = "mips", target_arch = "mips64"))]
+         {
+             if hwcap != 0 {
+                 return Ok(AuxVec { hwcap });
+             }
+         }
+ 
+         // Targets with AT_HWCAP and AT_HWCAP2:
+         #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+         {
+             let hwcap2 = unsafe { ffi_getauxval(AT_HWCAP2) };
+             if hwcap != 0 && hwcap2 != 0 {
+                 return Ok(AuxVec { hwcap, hwcap2 });
+             }
+         }
+     }
+ }
+ 
+ /// Tries to read the `key` from the auxiliary vector by calling the
+ /// dynamically-linked `getauxval` function. If the function is not linked,
+ /// this function return `Err`.
+ #[cfg(feature = "std_detect_dlsym_getauxval")]
+ fn getauxval(key: usize) -> Result<usize, ()> {
+     use libc;
+     pub type F = unsafe extern "C" fn(usize) -> usize;
+     unsafe {
+         let ptr = libc::dlsym(libc::RTLD_DEFAULT, "getauxval\0".as_ptr() as *const _);
+         if ptr.is_null() {
+             return Err(());
+         }
+ 
+         let ffi_getauxval: F = mem::transmute(ptr);
+         Ok(ffi_getauxval(key))
+     }
+ }
+ 
+ /// Tries to read the auxiliary vector from the `file`. If this fails, this
+ /// function returns `Err`.
+ #[cfg(feature = "std_detect_file_io")]
+ fn auxv_from_file(file: &str) -> Result<AuxVec, ()> {
+     let mut file = File::open(file).map_err(|_| ())?;
+ 
+     // See <https://github.com/torvalds/linux/blob/v3.19/include/uapi/linux/auxvec.h>.
+     //
+     // The auxiliary vector contains at most 32 (key,value) fields: from
+     // `AT_EXECFN = 31` to `AT_NULL = 0`. That is, a buffer of
+     // 2*32 `usize` elements is enough to read the whole vector.
+     let mut buf = [0_usize; 64];
+     {
+         let raw: &mut [u8; 64 * mem::size_of::<usize>()] = unsafe { mem::transmute(&mut buf) };
+         file.read(raw).map_err(|_| ())?;
+     }
+     auxv_from_buf(&buf)
+ }
+ 
+ /// Tries to interpret the `buffer` as an auxiliary vector. If that fails, this
+ /// function returns `Err`.
+ #[cfg(feature = "std_detect_file_io")]
+ fn auxv_from_buf(buf: &[usize; 64]) -> Result<AuxVec, ()> {
+     // Targets with only AT_HWCAP:
+     #[cfg(any(target_arch = "aarch64", target_arch = "mips", target_arch = "mips64"))]
+     {
+         for el in buf.chunks(2) {
+             match el[0] {
+                 AT_HWCAP => return Ok(AuxVec { hwcap: el[1] }),
+                 _ => (),
+             }
+         }
+     }
+     // Targets with AT_HWCAP and AT_HWCAP2:
+     #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+     {
+         let mut hwcap = None;
+         let mut hwcap2 = None;
+         for el in buf.chunks(2) {
+             match el[0] {
+                 AT_HWCAP => hwcap = Some(el[1]),
+                 AT_HWCAP2 => hwcap2 = Some(el[1]),
+                 _ => (),
+             }
+         }
+ 
+         if let (Some(hwcap), Some(hwcap2)) = (hwcap, hwcap2) {
+             return Ok(AuxVec { hwcap, hwcap2 });
+         }
+     }
+     drop(buf);
+     Err(())
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     extern crate auxv as auxv_crate;
+     use super::*;
+ 
+     // Reads the Auxiliary Vector key from /proc/self/auxv
+     // using the auxv crate.
+     #[cfg(feature = "std_detect_file_io")]
+     fn auxv_crate_getprocfs(key: usize) -> Option<usize> {
+         use self::auxv_crate::procfs::search_procfs_auxv;
+         use self::auxv_crate::AuxvType;
+         let k = key as AuxvType;
+         match search_procfs_auxv(&[k]) {
+             Ok(v) => Some(v[&k] as usize),
+             Err(_) => None,
+         }
+     }
+ 
+     // Reads the Auxiliary Vector key from getauxval()
+     // using the auxv crate.
+     #[cfg(not(any(target_arch = "mips", target_arch = "mips64")))]
+     fn auxv_crate_getauxval(key: usize) -> Option<usize> {
+         use self::auxv_crate::getauxval::Getauxval;
+         use self::auxv_crate::AuxvType;
+         let q = auxv_crate::getauxval::NativeGetauxval {};
+         match q.getauxval(key as AuxvType) {
+             Ok(v) => Some(v as usize),
+             Err(_) => None,
+         }
+     }
+ 
+     // FIXME: on mips/mips64 getauxval returns 0, and /proc/self/auxv
+     // does not always contain the AT_HWCAP key under qemu.
+     #[cfg(not(any(target_arch = "mips", target_arch = "mips64", target_arch = "powerpc")))]
+     #[test]
+     fn auxv_crate() {
+         let v = auxv();
+         if let Some(hwcap) = auxv_crate_getauxval(AT_HWCAP) {
+             let rt_hwcap = v.expect("failed to find hwcap key").hwcap;
+             assert_eq!(rt_hwcap, hwcap);
+         }
+ 
+         // Targets with AT_HWCAP and AT_HWCAP2:
+         #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+         {
+             if let Some(hwcap2) = auxv_crate_getauxval(AT_HWCAP2) {
+                 let rt_hwcap2 = v.expect("failed to find hwcap2 key").hwcap2;
+                 assert_eq!(rt_hwcap2, hwcap2);
+             }
+         }
+     }
+ 
+     #[test]
+     fn auxv_dump() {
+         if let Ok(auxvec) = auxv() {
+             println!("{:?}", auxvec);
+         } else {
+             println!("both getauxval() and reading /proc/self/auxv failed!");
+         }
+     }
+ 
+     #[cfg(feature = "std_detect_file_io")]
+     cfg_if! {
+         if #[cfg(target_arch = "arm")] {
+             #[test]
+             fn linux_rpi3() {
+                 let file = concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/linux-rpi3.auxv");
+                 println!("file: {}", file);
+                 let v = auxv_from_file(file).unwrap();
+                 assert_eq!(v.hwcap, 4174038);
+                 assert_eq!(v.hwcap2, 16);
+             }
+ 
+             #[test]
+             #[should_panic]
+             fn linux_macos_vb() {
+                 let file = concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv");
+                 println!("file: {}", file);
+                 let v = auxv_from_file(file).unwrap();
+                 // this file is incomplete (contains hwcap but not hwcap2), we
+                 // want to fall back to /proc/cpuinfo in this case, so
+                 // reading should fail. assert_eq!(v.hwcap, 126614527);
+                 // assert_eq!(v.hwcap2, 0);
+             }
+         } else if #[cfg(target_arch = "aarch64")] {
+             #[test]
+             fn linux_x64() {
+                 let file = concat!(env!("CARGO_MANIFEST_DIR"), "/src/detect/test_data/linux-x64-i7-6850k.auxv");
+                 println!("file: {}", file);
+                 let v = auxv_from_file(file).unwrap();
+                 assert_eq!(v.hwcap, 3219913727);
+             }
+         }
+     }
+ 
+     #[test]
+     #[cfg(feature = "std_detect_file_io")]
+     fn auxv_dump_procfs() {
+         if let Ok(auxvec) = auxv_from_file("/proc/self/auxv") {
+             println!("{:?}", auxvec);
+         } else {
+             println!("reading /proc/self/auxv failed!");
+         }
+     }
+ 
+     #[test]
+     fn auxv_crate_procfs() {
+         let v = auxv();
+         if let Some(hwcap) = auxv_crate_getprocfs(AT_HWCAP) {
+             assert_eq!(v.unwrap().hwcap, hwcap);
+         }
+ 
+         // Targets with AT_HWCAP and AT_HWCAP2:
+         #[cfg(any(target_arch = "arm", target_arch = "powerpc64"))]
+         {
+             if let Some(hwcap2) = auxv_crate_getprocfs(AT_HWCAP2) {
+                 assert_eq!(v.unwrap().hwcap2, hwcap2);
+             }
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,300 ----
+ //! Parses /proc/cpuinfo
+ #![cfg_attr(not(target_arch = "arm"), allow(dead_code))]
+ 
+ extern crate std;
+ use self::std::{fs::File, io, io::Read, prelude::v1::*};
+ 
+ /// cpuinfo
+ pub(crate) struct CpuInfo {
+     raw: String,
+ }
+ 
+ impl CpuInfo {
+     /// Reads /proc/cpuinfo into CpuInfo.
+     pub(crate) fn new() -> Result<Self, io::Error> {
+         let mut file = File::open("/proc/cpuinfo")?;
+         let mut cpui = Self { raw: String::new() };
+         file.read_to_string(&mut cpui.raw)?;
+         Ok(cpui)
+     }
+     /// Returns the value of the cpuinfo `field`.
+     pub(crate) fn field(&self, field: &str) -> CpuInfoField {
+         for l in self.raw.lines() {
+             if l.trim().starts_with(field) {
+                 return CpuInfoField::new(l.split(": ").nth(1));
+             }
+         }
+         CpuInfoField(None)
+     }
+ 
+     /// Returns the `raw` contents of `/proc/cpuinfo`
+     #[cfg(test)]
+     fn raw(&self) -> &String {
+         &self.raw
+     }
+ 
+     #[cfg(test)]
+     fn from_str(other: &str) -> Result<Self, ::std::io::Error> {
+         Ok(Self {
+             raw: String::from(other),
+         })
+     }
+ }
+ 
+ /// Field of cpuinfo
+ #[derive(Debug)]
+ pub(crate) struct CpuInfoField<'a>(Option<&'a str>);
+ 
+ impl<'a> PartialEq<&'a str> for CpuInfoField<'a> {
+     fn eq(&self, other: &&'a str) -> bool {
+         match self.0 {
+             None => other.is_empty(),
+             Some(f) => f == other.trim(),
+         }
+     }
+ }
+ 
+ impl<'a> CpuInfoField<'a> {
+     pub(crate) fn new<'b>(v: Option<&'b str>) -> CpuInfoField<'b> {
+         match v {
+             None => CpuInfoField::<'b>(None),
+             Some(f) => CpuInfoField::<'b>(Some(f.trim())),
+         }
+     }
+     /// Does the field exist?
+     #[cfg(test)]
+     pub(crate) fn exists(&self) -> bool {
+         self.0.is_some()
+     }
+     /// Does the field contain `other`?
+     pub(crate) fn has(&self, other: &str) -> bool {
+         match self.0 {
+             None => other.is_empty(),
+             Some(f) => {
+                 let other = other.trim();
+                 for v in f.split(' ') {
+                     if v == other {
+                         return true;
+                     }
+                 }
+                 false
+             }
+         }
+     }
+ }
+ 
+ #[cfg(test)]
+ mod tests {
+     use super::*;
+ 
+     #[test]
+     fn raw_dump() {
+         let cpuinfo = CpuInfo::new().unwrap();
+         if cpuinfo.field("vendor_id") == "GenuineIntel" {
+             assert!(cpuinfo.field("flags").exists());
+             assert!(!cpuinfo.field("vendor33_id").exists());
+             assert!(cpuinfo.field("flags").has("sse"));
+             assert!(!cpuinfo.field("flags").has("avx314"));
+         }
+         println!("{}", cpuinfo.raw());
+     }
+ 
+     const CORE_DUO_T6500: &str = r"processor       : 0
+ vendor_id       : GenuineIntel
+ cpu family      : 6
+ model           : 23
+ model name      : Intel(R) Core(TM)2 Duo CPU     T6500  @ 2.10GHz
+ stepping        : 10
+ microcode       : 0xa0b
+ cpu MHz         : 1600.000
+ cache size      : 2048 KB
+ physical id     : 0
+ siblings        : 2
+ core id         : 0
+ cpu cores       : 2
+ apicid          : 0
+ initial apicid  : 0
+ fdiv_bug        : no
+ hlt_bug         : no
+ f00f_bug        : no
+ coma_bug        : no
+ fpu             : yes
+ fpu_exception   : yes
+ cpuid level     : 13
+ wp              : yes
+ flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm dtherm
+ bogomips        : 4190.43
+ clflush size    : 64
+ cache_alignment : 64
+ address sizes   : 36 bits physical, 48 bits virtual
+ power management:
+ ";
+ 
+     #[test]
+     fn core_duo_t6500() {
+         let cpuinfo = CpuInfo::from_str(CORE_DUO_T6500).unwrap();
+         assert_eq!(cpuinfo.field("vendor_id"), "GenuineIntel");
+         assert_eq!(cpuinfo.field("cpu family"), "6");
+         assert_eq!(cpuinfo.field("model"), "23");
+         assert_eq!(
+             cpuinfo.field("model name"),
+             "Intel(R) Core(TM)2 Duo CPU     T6500  @ 2.10GHz"
+         );
+         assert_eq!(
+             cpuinfo.field("flags"),
+             "fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm dtherm"
+         );
+         assert!(cpuinfo.field("flags").has("fpu"));
+         assert!(cpuinfo.field("flags").has("dtherm"));
+         assert!(cpuinfo.field("flags").has("sse2"));
+         assert!(!cpuinfo.field("flags").has("avx"));
+     }
+ 
+     const ARM_CORTEX_A53: &str = r"Processor   : AArch64 Processor rev 3 (aarch64)
+         processor   : 0
+         processor   : 1
+         processor   : 2
+         processor   : 3
+         processor   : 4
+         processor   : 5
+         processor   : 6
+         processor   : 7
+         Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
+         CPU implementer : 0x41
+         CPU architecture: AArch64
+         CPU variant : 0x0
+         CPU part    : 0xd03
+         CPU revision    : 3
+ 
+         Hardware    : HiKey Development Board
+         ";
+ 
+     #[test]
+     fn arm_cortex_a53() {
+         let cpuinfo = CpuInfo::from_str(ARM_CORTEX_A53).unwrap();
+         assert_eq!(
+             cpuinfo.field("Processor"),
+             "AArch64 Processor rev 3 (aarch64)"
+         );
+         assert_eq!(
+             cpuinfo.field("Features"),
+             "fp asimd evtstrm aes pmull sha1 sha2 crc32"
+         );
+         assert!(cpuinfo.field("Features").has("pmull"));
+         assert!(!cpuinfo.field("Features").has("neon"));
+         assert!(cpuinfo.field("Features").has("asimd"));
+     }
+ 
+     const ARM_CORTEX_A57: &str = r"Processor	: Cortex A57 Processor rev 1 (aarch64)
+ processor	: 0
+ processor	: 1
+ processor	: 2
+ processor	: 3
+ Features	: fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt
+ CPU implementer	: 0x41
+ CPU architecture: 8
+ CPU variant	: 0x1
+ CPU part	: 0xd07
+ CPU revision	: 1";
+ 
+     #[test]
+     fn arm_cortex_a57() {
+         let cpuinfo = CpuInfo::from_str(ARM_CORTEX_A57).unwrap();
+         assert_eq!(
+             cpuinfo.field("Processor"),
+             "Cortex A57 Processor rev 1 (aarch64)"
+         );
+         assert_eq!(
+             cpuinfo.field("Features"),
+             "fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt"
+         );
+         assert!(cpuinfo.field("Features").has("pmull"));
+         assert!(cpuinfo.field("Features").has("neon"));
+         assert!(cpuinfo.field("Features").has("asimd"));
+     }
+ 
+     const POWER8E_POWERKVM: &str = r"processor       : 0
+ cpu             : POWER8E (raw), altivec supported
+ clock           : 3425.000000MHz
+ revision        : 2.1 (pvr 004b 0201)
+ 
+ processor       : 1
+ cpu             : POWER8E (raw), altivec supported
+ clock           : 3425.000000MHz
+ revision        : 2.1 (pvr 004b 0201)
+ 
+ processor       : 2
+ cpu             : POWER8E (raw), altivec supported
+ clock           : 3425.000000MHz
+ revision        : 2.1 (pvr 004b 0201)
+ 
+ processor       : 3
+ cpu             : POWER8E (raw), altivec supported
+ clock           : 3425.000000MHz
+ revision        : 2.1 (pvr 004b 0201)
+ 
+ timebase        : 512000000
+ platform        : pSeries
+ model           : IBM pSeries (emulated by qemu)
+ machine         : CHRP IBM pSeries (emulated by qemu)";
+ 
+     #[test]
+     fn power8_powerkvm() {
+         let cpuinfo = CpuInfo::from_str(POWER8E_POWERKVM).unwrap();
+         assert_eq!(cpuinfo.field("cpu"), "POWER8E (raw), altivec supported");
+ 
+         assert!(cpuinfo.field("cpu").has("altivec"));
+     }
+ 
+     const POWER5P: &str = r"processor       : 0
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 1
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 2
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 3
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 4
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 5
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 6
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ processor       : 7
+ cpu             : POWER5+ (gs)
+ clock           : 1900.098000MHz
+ revision        : 2.1 (pvr 003b 0201)
+ 
+ timebase        : 237331000
+ platform        : pSeries
+ machine         : CHRP IBM,9133-55A";
+ 
+     #[test]
+     fn power5p() {
+         let cpuinfo = CpuInfo::from_str(POWER5P).unwrap();
+         assert_eq!(cpuinfo.field("cpu"), "POWER5+ (gs)");
+ 
+         assert!(!cpuinfo.field("cpu").has("altivec"));
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,25 ----
+ //! Run-time feature detection for MIPS on Linux.
+ 
+ use super::auxvec;
+ use crate::detect::{bit, cache, Feature};
+ 
+ /// Try to read the features from the auxiliary vector, and if that fails, try
+ /// to read them from `/proc/cpuinfo`.
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+     let enable_feature = |value: &mut cache::Initializer, f, enable| {
+         if enable {
+             value.set(f as u32);
+         }
+     };
+ 
+     // The values are part of the platform-specific [asm/hwcap.h][hwcap]
+     //
+     // [hwcap]: https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/hwcap.h
+     if let Ok(auxv) = auxvec::auxv() {
+         enable_feature(&mut value, Feature::msa, bit::test(auxv.hwcap, 1));
+         return value;
+     }
+     // TODO: fall back via `cpuinfo`.
+     value
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,28 ----
+ //! Run-time feature detection on Linux
+ 
+ mod auxvec;
+ 
+ #[cfg(feature = "std_detect_file_io")]
+ mod cpuinfo;
+ 
+ cfg_if! {
+     if #[cfg(target_arch = "aarch64")] {
+         mod aarch64;
+         pub use self::aarch64::check_for;
+     } else if #[cfg(target_arch = "arm")] {
+         mod arm;
+         pub use self::arm::check_for;
+     } else  if #[cfg(any(target_arch = "mips", target_arch = "mips64"))] {
+         mod mips;
+         pub use self::mips::check_for;
+     } else if #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] {
+         mod powerpc;
+         pub use self::powerpc::check_for;
+     } else {
+         use crate::detect::Feature;
+         /// Performs run-time feature detection.
+         pub fn check_for(_x: Feature) -> bool {
+             false
+         }
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,35 ----
+ //! Run-time feature detection for PowerPC on Linux.
+ 
+ use super::{auxvec, cpuinfo};
+ use crate::detect::{cache, Feature};
+ 
+ /// Try to read the features from the auxiliary vector, and if that fails, try
+ /// to read them from /proc/cpuinfo.
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+     let enable_feature = |value: &mut cache::Initializer, f, enable| {
+         if enable {
+             value.set(f as u32);
+         }
+     };
+ 
+     // The values are part of the platform-specific [asm/cputable.h][cputable]
+     //
+     // [cputable]: https://github.com/torvalds/linux/blob/master/arch/powerpc/include/uapi/asm/cputable.h
+     if let Ok(auxv) = auxvec::auxv() {
+         // note: the PowerPC values are the mask to do the test (instead of the
+         // index of the bit to test like in ARM and Aarch64)
+         enable_feature(&mut value, Feature::altivec, auxv.hwcap & 0x10000000 != 0);
+         enable_feature(&mut value, Feature::vsx, auxv.hwcap & 0x00000080 != 0);
+         enable_feature(&mut value, Feature::power8, auxv.hwcap2 & 0x80000000 != 0);
+         return value;
+     }
+ 
+     // PowerPC's /proc/cpuinfo lacks a proper Feature field,
+     // but `altivec` support is indicated in the `cpu` field.
+     if let Ok(c) = cpuinfo::CpuInfo::new() {
+         enable_feature(&mut value, Feature::altivec, c.field("cpu").has("altivec"));
+         return value;
+     }
+     value
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,8 ----
+ //! Other operating systems
+ 
+ use crate::detect::cache;
+ 
+ #[allow(dead_code)]
+ pub(crate) fn detect_features() -> cache::Initializer {
+     cache::Initializer::default()
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,55 ----
+ //! Run-time feature detection for Aarch64 on Windows.
+ 
+ use crate::detect::{cache, Feature};
+ 
+ /// Try to read the features using IsProcessorFeaturePresent.
+ pub(crate) fn detect_features() -> cache::Initializer {
+     type DWORD = u32;
+     type BOOL = i32;
+ 
+     const FALSE: BOOL = 0;
+     // The following Microsoft documents isn't updated for aarch64.
+     // https://docs.microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent
+     // These are defined in winnt.h of Windows SDK
+     const PF_ARM_NEON_INSTRUCTIONS_AVAILABLE: u32 = 19;
+     const PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE: u32 = 30;
+     const PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE: u32 = 31;
+ 
+     extern "system" {
+         pub fn IsProcessorFeaturePresent(ProcessorFeature: DWORD) -> BOOL;
+     }
+ 
+     let mut value = cache::Initializer::default();
+     {
+         let mut enable_feature = |f, enable| {
+             if enable {
+                 value.set(f as u32);
+             }
+         };
+ 
+         // Some features such Feature::fp may be supported on current CPU,
+         // but no way to detect it by OS API.
+         // Also, we require unsafe block for the extern "system" calls.
+         unsafe {
+             enable_feature(
+                 Feature::asimd,
+                 IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE) != FALSE,
+             );
+             enable_feature(
+                 Feature::crc,
+                 IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) != FALSE,
+             );
+             // PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE means aes, sha1, sha2 and
+             // pmull support
+             enable_feature(
+                 Feature::crypto,
+                 IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != FALSE,
+             );
+             enable_feature(
+                 Feature::pmull,
+                 IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != FALSE,
+             );
+         }
+     }
+     value
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,253 ----
+ //! x86 run-time feature detection is OS independent.
+ 
+ #[cfg(target_arch = "x86")]
+ use crate::arch::x86::*;
+ #[cfg(target_arch = "x86_64")]
+ use crate::arch::x86_64::*;
+ 
+ use crate::mem;
+ 
+ use crate::detect::{bit, cache, Feature};
+ 
+ /// Run-time feature detection on x86 works by using the CPUID instruction.
+ ///
+ /// The [CPUID Wikipedia page][wiki_cpuid] contains
+ /// all the information about which flags to set to query which values, and in
+ /// which registers these are reported.
+ ///
+ /// The definitive references are:
+ /// - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+ ///   Instruction Set Reference, A-Z][intel64_ref].
+ /// - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+ ///   System Instructions][amd64_ref].
+ ///
+ /// [wiki_cpuid]: https://en.wikipedia.org/wiki/CPUID
+ /// [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+ /// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+ #[allow(clippy::similar_names)]
+ pub(crate) fn detect_features() -> cache::Initializer {
+     let mut value = cache::Initializer::default();
+ 
+     // If the x86 CPU does not support the CPUID instruction then it is too
+     // old to support any of the currently-detectable features.
+     if !has_cpuid() {
+         return value;
+     }
+ 
+     // Calling `__cpuid`/`__cpuid_count` from here on is safe because the CPU
+     // has `cpuid` support.
+ 
+     // 0. EAX = 0: Basic Information:
+     // - EAX returns the "Highest Function Parameter", that is, the maximum
+     // leaf value for subsequent calls of `cpuinfo` in range [0,
+     // 0x8000_0000]. - The vendor ID is stored in 12 u8 ascii chars,
+     // returned in EBX, EDX, and   ECX (in that order):
+     let (max_basic_leaf, vendor_id) = unsafe {
+         let CpuidResult {
+             eax: max_basic_leaf,
+             ebx,
+             ecx,
+             edx,
+         } = __cpuid(0);
+         let vendor_id: [[u8; 4]; 3] = [
+             mem::transmute(ebx),
+             mem::transmute(edx),
+             mem::transmute(ecx),
+         ];
+         let vendor_id: [u8; 12] = mem::transmute(vendor_id);
+         (max_basic_leaf, vendor_id)
+     };
+ 
+     if max_basic_leaf < 1 {
+         // Earlier Intel 486, CPUID not implemented
+         return value;
+     }
+ 
+     // EAX = 1, ECX = 0: Queries "Processor Info and Feature Bits";
+     // Contains information about most x86 features.
+     let CpuidResult {
+         ecx: proc_info_ecx,
+         edx: proc_info_edx,
+         ..
+     } = unsafe { __cpuid(0x0000_0001_u32) };
+ 
+     // EAX = 7, ECX = 0: Queries "Extended Features";
+     // Contains information about bmi,bmi2, and avx2 support.
+     let (extended_features_ebx, extended_features_ecx) = if max_basic_leaf >= 7 {
+         let CpuidResult { ebx, ecx, .. } = unsafe { __cpuid(0x0000_0007_u32) };
+         (ebx, ecx)
+     } else {
+         (0, 0) // CPUID does not support "Extended Features"
+     };
+ 
+     // EAX = 0x8000_0000, ECX = 0: Get Highest Extended Function Supported
+     // - EAX returns the max leaf value for extended information, that is,
+     // `cpuid` calls in range [0x8000_0000; u32::MAX]:
+     let CpuidResult {
+         eax: extended_max_basic_leaf,
+         ..
+     } = unsafe { __cpuid(0x8000_0000_u32) };
+ 
+     // EAX = 0x8000_0001, ECX=0: Queries "Extended Processor Info and Feature
+     // Bits"
+     let extended_proc_info_ecx = if extended_max_basic_leaf >= 1 {
+         let CpuidResult { ecx, .. } = unsafe { __cpuid(0x8000_0001_u32) };
+         ecx
+     } else {
+         0
+     };
+ 
+     {
+         // borrows value till the end of this scope:
+         let mut enable = |r, rb, f| {
+             if bit::test(r as usize, rb) {
+                 value.set(f as u32);
+             }
+         };
+ 
+         enable(proc_info_ecx, 0, Feature::sse3);
+         enable(proc_info_ecx, 1, Feature::pclmulqdq);
+         enable(proc_info_ecx, 9, Feature::ssse3);
+         enable(proc_info_ecx, 13, Feature::cmpxchg16b);
+         enable(proc_info_ecx, 19, Feature::sse4_1);
+         enable(proc_info_ecx, 20, Feature::sse4_2);
+         enable(proc_info_ecx, 23, Feature::popcnt);
+         enable(proc_info_ecx, 25, Feature::aes);
+         enable(proc_info_ecx, 29, Feature::f16c);
+         enable(proc_info_ecx, 30, Feature::rdrand);
+         enable(extended_features_ebx, 18, Feature::rdseed);
+         enable(extended_features_ebx, 19, Feature::adx);
+         enable(extended_features_ebx, 11, Feature::rtm);
+         enable(proc_info_edx, 4, Feature::tsc);
+         enable(proc_info_edx, 23, Feature::mmx);
+         enable(proc_info_edx, 24, Feature::fxsr);
+         enable(proc_info_edx, 25, Feature::sse);
+         enable(proc_info_edx, 26, Feature::sse2);
+         enable(extended_features_ebx, 29, Feature::sha);
+ 
+         enable(extended_features_ebx, 3, Feature::bmi1);
+         enable(extended_features_ebx, 8, Feature::bmi2);
+ 
+         // `XSAVE` and `AVX` support:
+         let cpu_xsave = bit::test(proc_info_ecx as usize, 26);
+         if cpu_xsave {
+             // 0. Here the CPU supports `XSAVE`.
+ 
+             // 1. Detect `OSXSAVE`, that is, whether the OS is AVX enabled and
+             // supports saving the state of the AVX/AVX2 vector registers on
+             // context-switches, see:
+             //
+             // - [intel: is avx enabled?][is_avx_enabled],
+             // - [mozilla: sse.cpp][mozilla_sse_cpp].
+             //
+             // [is_avx_enabled]: https://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
+             // [mozilla_sse_cpp]: https://hg.mozilla.org/mozilla-central/file/64bab5cbb9b6/mozglue/build/SSE.cpp#l190
+             let cpu_osxsave = bit::test(proc_info_ecx as usize, 27);
+ 
+             if cpu_osxsave {
+                 // 2. The OS must have signaled the CPU that it supports saving and
+                 // restoring the:
+                 //
+                 // * SSE -> `XCR0.SSE[1]`
+                 // * AVX -> `XCR0.AVX[2]`
+                 // * AVX-512 -> `XCR0.AVX-512[7:5]`.
+                 //
+                 // by setting the corresponding bits of `XCR0` to `1`.
+                 //
+                 // This is safe because the CPU supports `xsave`
+                 // and the OS has set `osxsave`.
+                 let xcr0 = unsafe { _xgetbv(0) };
+                 // Test `XCR0.SSE[1]` and `XCR0.AVX[2]` with the mask `0b110 == 6`:
+                 let os_avx_support = xcr0 & 6 == 6;
+                 // Test `XCR0.AVX-512[7:5]` with the mask `0b1110_0000 == 224`:
+                 let os_avx512_support = xcr0 & 224 == 224;
+ 
+                 // Only if the OS and the CPU support saving/restoring the AVX
+                 // registers we enable `xsave` support:
+                 if os_avx_support {
+                     // See "13.3 ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED
+                     // FEATURES" in the "Intel® 64 and IA-32 Architectures Software
+                     // Developer’s Manual, Volume 1: Basic Architecture":
+                     //
+                     // "Software enables the XSAVE feature set by setting
+                     // CR4.OSXSAVE[bit 18] to 1 (e.g., with the MOV to CR4
+                     // instruction). If this bit is 0, execution of any of XGETBV,
+                     // XRSTOR, XRSTORS, XSAVE, XSAVEC, XSAVEOPT, XSAVES, and XSETBV
+                     // causes an invalid-opcode exception (#UD)"
+                     //
+                     enable(proc_info_ecx, 26, Feature::xsave);
+ 
+                     // For `xsaveopt`, `xsavec`, and `xsaves` we need to query:
+                     // Processor Extended State Enumeration Sub-leaf (EAX = 0DH,
+                     // ECX = 1):
+                     if max_basic_leaf >= 0xd {
+                         let CpuidResult {
+                             eax: proc_extended_state1_eax,
+                             ..
+                         } = unsafe { __cpuid_count(0xd_u32, 1) };
+                         enable(proc_extended_state1_eax, 0, Feature::xsaveopt);
+                         enable(proc_extended_state1_eax, 1, Feature::xsavec);
+                         enable(proc_extended_state1_eax, 3, Feature::xsaves);
+                     }
+ 
+                     // FMA (uses 256-bit wide registers):
+                     enable(proc_info_ecx, 12, Feature::fma);
+ 
+                     // And AVX/AVX2:
+                     enable(proc_info_ecx, 28, Feature::avx);
+                     enable(extended_features_ebx, 5, Feature::avx2);
+ 
+                     // For AVX-512 the OS also needs to support saving/restoring
+                     // the extended state, only then we enable AVX-512 support:
+                     if os_avx512_support {
+                         enable(extended_features_ebx, 16, Feature::avx512f);
+                         enable(extended_features_ebx, 17, Feature::avx512dq);
+                         enable(extended_features_ebx, 21, Feature::avx512ifma);
+                         enable(extended_features_ebx, 26, Feature::avx512pf);
+                         enable(extended_features_ebx, 27, Feature::avx512er);
+                         enable(extended_features_ebx, 28, Feature::avx512cd);
+                         enable(extended_features_ebx, 30, Feature::avx512bw);
+                         enable(extended_features_ebx, 31, Feature::avx512vl);
+                         enable(extended_features_ecx, 1, Feature::avx512vbmi);
+                         enable(extended_features_ecx, 5, Feature::avx512bf16);
+                         enable(extended_features_ecx, 6, Feature::avx512vbmi2);
+                         enable(extended_features_ecx, 8, Feature::avx512gfni);
+                         enable(extended_features_ecx, 8, Feature::avx512vp2intersect);
+                         enable(extended_features_ecx, 9, Feature::avx512vaes);
+                         enable(extended_features_ecx, 10, Feature::avx512vpclmulqdq);
+                         enable(extended_features_ecx, 11, Feature::avx512vnni);
+                         enable(extended_features_ecx, 12, Feature::avx512bitalg);
+                         enable(extended_features_ecx, 14, Feature::avx512vpopcntdq);
+                     }
+                 }
+             }
+         }
+ 
+         // This detects ABM on AMD CPUs and LZCNT on Intel CPUs.
+         // On intel CPUs with popcnt, lzcnt implements the
+         // "missing part" of ABM, so we map both to the same
+         // internal feature.
+         //
+         // The `is_x86_feature_detected!("lzcnt")` macro then
+         // internally maps to Feature::abm.
+         enable(extended_proc_info_ecx, 5, Feature::lzcnt);
+ 
+         // As Hygon Dhyana originates from AMD technology and shares most of the architecture with
+         // AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/Family series
+         // number(Family 18h).
+         //
+         // For CPUID feature bits, Hygon Dhyana(family 18h) share the same definition with AMD
+         // family 17h.
+         //
+         // Related AMD CPUID specification is https://www.amd.com/system/files/TechDocs/25481.pdf.
+         // Related Hygon kernel patch can be found on
+         // http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
+         if vendor_id == *b"AuthenticAMD" || vendor_id == *b"HygonGenuine" {
+             // These features are available on AMD arch CPUs:
+             enable(extended_proc_info_ecx, 6, Feature::sse4a);
+             enable(extended_proc_info_ecx, 21, Feature::tbm);
+         }
+     }
+ 
+     value
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ !Ї~ְ?d4 	��v	y��
���N�~�O�~�N�~
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-x64-i7-6850k.auxv gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-x64-i7-6850k.auxv
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-x64-i7-6850k.auxv	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-x64-i7-6850k.auxv	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,2 ----
+ ! ������d@@8
+ �G�8	`&@��
��ɘ���￁��٘���
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+  �|w�!pw����d4� 	�w�	h�
kJ��_�{J�
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,45 ----
+ //! Run-time feature detection for the Rust standard library.
+ //!
+ //! To detect whether a feature is enabled in the system running the binary
+ //! use one of the appropriate macro for the target:
+ //!
+ //! * `x86` and `x86_64`: [`is_x86_feature_detected`]
+ //! * `arm`: [`is_arm_feature_detected`]
+ //! * `aarch64`: [`is_aarch64_feature_detected`]
+ //! * `mips`: [`is_mips_feature_detected`]
+ //! * `mips64`: [`is_mips64_feature_detected`]
+ //! * `powerpc`: [`is_powerpc_feature_detected`]
+ //! * `powerpc64`: [`is_powerpc64_feature_detected`]
+ 
+ #![unstable(feature = "stdsimd", issue = "27731")]
+ #![feature(const_fn, staged_api, stdsimd, doc_cfg, allow_internal_unstable)]
+ #![allow(clippy::shadow_reuse)]
+ #![deny(clippy::missing_inline_in_public_items)]
+ #![cfg_attr(target_os = "linux", feature(linkage))]
+ #![cfg_attr(all(target_os = "freebsd", target_arch = "aarch64"), feature(llvm_asm))]
+ #![cfg_attr(test, allow(unused_imports))]
+ #![no_std]
+ 
+ cfg_if::cfg_if! {
+     if #[cfg(any(feature = "std_detect_file_io", feature = "std_detect_env_override"))] {
+         #[cfg_attr(test, macro_use(println))]
+         extern crate std;
+ 
+         #[allow(unused_imports)]
+         use std::{arch, env, fs, io, mem, sync};
+     } else {
+         #[cfg(test)]
+         #[macro_use(println)]
+         extern crate std;
+ 
+         #[allow(unused_imports)]
+         use core::{arch, mem, sync};
+     }
+ }
+ 
+ #[cfg(feature = "std_detect_dlsym_getauxval")]
+ extern crate libc;
+ 
+ #[doc(hidden)]
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ pub mod detect;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/mod.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/mod.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/src/mod.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/src/mod.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,5 ----
+ //! `std_detect`
+ 
+ #[doc(hidden)] // unstable implementation detail
+ #[unstable(feature = "stdsimd", issue = "27731")]
+ pub mod detect;
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,129 ----
+ #![feature(stdsimd)]
+ #![allow(clippy::option_unwrap_used, clippy::use_debug, clippy::print_stdout)]
+ #![cfg(any(
+     target_arch = "arm",
+     target_arch = "aarch64",
+     target_arch = "x86",
+     target_arch = "x86_64",
+     target_arch = "powerpc",
+     target_arch = "powerpc64"
+ ))]
+ 
+ #[macro_use]
+ extern crate std_detect;
+ 
+ #[test]
+ fn all() {
+     for (f, e) in std_detect::detect::features() {
+         println!("{}: {}", f, e);
+     }
+ }
+ 
+ #[test]
+ #[cfg(all(target_arch = "arm", any(target_os = "linux", target_os = "android")))]
+ fn arm_linux() {
+     println!("neon: {}", is_arm_feature_detected!("neon"));
+     println!("pmull: {}", is_arm_feature_detected!("pmull"));
+     println!("crc: {}", is_arm_feature_detected!("crc"));
+     println!("crypto: {}", is_arm_feature_detected!("crypto"));
+ }
+ 
+ #[test]
+ #[cfg(all(
+     target_arch = "aarch64",
+     any(target_os = "linux", target_os = "android")
+ ))]
+ fn aarch64_linux() {
+     println!("fp: {}", is_aarch64_feature_detected!("fp"));
+     println!("fp16: {}", is_aarch64_feature_detected!("fp16"));
+     println!("neon: {}", is_aarch64_feature_detected!("neon"));
+     println!("asimd: {}", is_aarch64_feature_detected!("asimd"));
+     println!("sve: {}", is_aarch64_feature_detected!("sve"));
+     println!("crc: {}", is_aarch64_feature_detected!("crc"));
+     println!("crypto: {}", is_aarch64_feature_detected!("crypto"));
+     println!("lse: {}", is_aarch64_feature_detected!("lse"));
+     println!("rdm: {}", is_aarch64_feature_detected!("rdm"));
+     println!("rcpc: {}", is_aarch64_feature_detected!("rcpc"));
+     println!("dotprod: {}", is_aarch64_feature_detected!("dotprod"));
+     println!("tme: {}", is_aarch64_feature_detected!("tme"));
+ }
+ 
+ #[test]
+ #[cfg(all(target_arch = "powerpc", target_os = "linux"))]
+ fn powerpc_linux() {
+     println!("altivec: {}", is_powerpc_feature_detected!("altivec"));
+     println!("vsx: {}", is_powerpc_feature_detected!("vsx"));
+     println!("power8: {}", is_powerpc_feature_detected!("power8"));
+ }
+ 
+ #[test]
+ #[cfg(all(target_arch = "powerpc64", target_os = "linux"))]
+ fn powerpc64_linux() {
+     println!("altivec: {}", is_powerpc64_feature_detected!("altivec"));
+     println!("vsx: {}", is_powerpc64_feature_detected!("vsx"));
+     println!("power8: {}", is_powerpc64_feature_detected!("power8"));
+ }
+ 
+ #[test]
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ fn x86_all() {
+     println!("aes: {:?}", is_x86_feature_detected!("aes"));
+     println!("pcmulqdq: {:?}", is_x86_feature_detected!("pclmulqdq"));
+     println!("rdrand: {:?}", is_x86_feature_detected!("rdrand"));
+     println!("rdseed: {:?}", is_x86_feature_detected!("rdseed"));
+     println!("tsc: {:?}", is_x86_feature_detected!("tsc"));
+     println!("mmx: {:?}", is_x86_feature_detected!("mmx"));
+     println!("sse: {:?}", is_x86_feature_detected!("sse"));
+     println!("sse2: {:?}", is_x86_feature_detected!("sse2"));
+     println!("sse3: {:?}", is_x86_feature_detected!("sse3"));
+     println!("ssse3: {:?}", is_x86_feature_detected!("ssse3"));
+     println!("sse4.1: {:?}", is_x86_feature_detected!("sse4.1"));
+     println!("sse4.2: {:?}", is_x86_feature_detected!("sse4.2"));
+     println!("sse4a: {:?}", is_x86_feature_detected!("sse4a"));
+     println!("sha: {:?}", is_x86_feature_detected!("sha"));
+     println!("avx: {:?}", is_x86_feature_detected!("avx"));
+     println!("avx2: {:?}", is_x86_feature_detected!("avx2"));
+     println!("avx512f: {:?}", is_x86_feature_detected!("avx512f"));
+     println!("avx512cd: {:?}", is_x86_feature_detected!("avx512cd"));
+     println!("avx512er: {:?}", is_x86_feature_detected!("avx512er"));
+     println!("avx512pf: {:?}", is_x86_feature_detected!("avx512pf"));
+     println!("avx512bw: {:?}", is_x86_feature_detected!("avx512bw"));
+     println!("avx512dq: {:?}", is_x86_feature_detected!("avx512dq"));
+     println!("avx512vl: {:?}", is_x86_feature_detected!("avx512vl"));
+     println!("avx512ifma: {:?}", is_x86_feature_detected!("avx512ifma"));
+     println!("avx512vbmi: {:?}", is_x86_feature_detected!("avx512vbmi"));
+     println!(
+         "avx512vpopcntdq: {:?}",
+         is_x86_feature_detected!("avx512vpopcntdq")
+     );
+     println!("avx512vbmi2 {:?}", is_x86_feature_detected!("avx512vbmi2"));
+     println!("avx512gfni {:?}", is_x86_feature_detected!("avx512gfni"));
+     println!("avx512vaes {:?}", is_x86_feature_detected!("avx512vaes"));
+     println!(
+         "avx512vpclmulqdq {:?}",
+         is_x86_feature_detected!("avx512vpclmulqdq")
+     );
+     println!("avx512vnni {:?}", is_x86_feature_detected!("avx512vnni"));
+     println!(
+         "avx512bitalg {:?}",
+         is_x86_feature_detected!("avx512bitalg")
+     );
+     println!("avx512bf16 {:?}", is_x86_feature_detected!("avx512bf16"));
+     println!(
+         "avx512vp2intersect {:?}",
+         is_x86_feature_detected!("avx512vp2intersect")
+     );
+     println!("f16c: {:?}", is_x86_feature_detected!("f16c"));
+     println!("fma: {:?}", is_x86_feature_detected!("fma"));
+     println!("bmi1: {:?}", is_x86_feature_detected!("bmi1"));
+     println!("bmi2: {:?}", is_x86_feature_detected!("bmi2"));
+     println!("abm: {:?}", is_x86_feature_detected!("abm"));
+     println!("lzcnt: {:?}", is_x86_feature_detected!("lzcnt"));
+     println!("tbm: {:?}", is_x86_feature_detected!("tbm"));
+     println!("popcnt: {:?}", is_x86_feature_detected!("popcnt"));
+     println!("fxsr: {:?}", is_x86_feature_detected!("fxsr"));
+     println!("xsave: {:?}", is_x86_feature_detected!("xsave"));
+     println!("xsaveopt: {:?}", is_x86_feature_detected!("xsaveopt"));
+     println!("xsaves: {:?}", is_x86_feature_detected!("xsaves"));
+     println!("xsavec: {:?}", is_x86_feature_detected!("xsavec"));
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,51 ----
+ #![feature(stdsimd)]
+ #![allow(clippy::option_unwrap_used, clippy::use_debug, clippy::print_stdout)]
+ 
+ #[cfg(any(
+     target_arch = "arm",
+     target_arch = "aarch64",
+     target_arch = "x86",
+     target_arch = "x86_64",
+     target_arch = "powerpc",
+     target_arch = "powerpc64"
+ ))]
+ #[macro_use]
+ extern crate std_detect;
+ 
+ #[test]
+ #[cfg(all(target_arch = "arm", any(target_os = "linux", target_os = "android")))]
+ fn arm_linux() {
+     let _ = is_arm_feature_detected!("neon");
+     let _ = is_arm_feature_detected!("neon",);
+ }
+ 
+ #[test]
+ #[cfg(all(
+     target_arch = "aarch64",
+     any(target_os = "linux", target_os = "android")
+ ))]
+ fn aarch64_linux() {
+     let _ = is_aarch64_feature_detected!("fp");
+     let _ = is_aarch64_feature_detected!("fp",);
+ }
+ 
+ #[test]
+ #[cfg(all(target_arch = "powerpc", target_os = "linux"))]
+ fn powerpc_linux() {
+     let _ = is_powerpc_feature_detected!("altivec");
+     let _ = is_powerpc_feature_detected!("altivec",);
+ }
+ 
+ #[test]
+ #[cfg(all(target_arch = "powerpc64", target_os = "linux"))]
+ fn powerpc64_linux() {
+     let _ = is_powerpc64_feature_detected!("altivec");
+     let _ = is_powerpc64_feature_detected!("altivec",);
+ }
+ 
+ #[test]
+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ fn x86_all() {
+     let _ = is_x86_feature_detected!("sse");
+     let _ = is_x86_feature_detected!("sse",);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,158 ----
+ #![feature(stdsimd)]
+ #![cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+ 
+ extern crate cupid;
+ #[macro_use]
+ extern crate std_detect;
+ 
+ #[test]
+ fn dump() {
+     println!("aes: {:?}", is_x86_feature_detected!("aes"));
+     println!("pclmulqdq: {:?}", is_x86_feature_detected!("pclmulqdq"));
+     println!("rdrand: {:?}", is_x86_feature_detected!("rdrand"));
+     println!("rdseed: {:?}", is_x86_feature_detected!("rdseed"));
+     println!("tsc: {:?}", is_x86_feature_detected!("tsc"));
+     println!("sse: {:?}", is_x86_feature_detected!("sse"));
+     println!("sse2: {:?}", is_x86_feature_detected!("sse2"));
+     println!("sse3: {:?}", is_x86_feature_detected!("sse3"));
+     println!("ssse3: {:?}", is_x86_feature_detected!("ssse3"));
+     println!("sse4.1: {:?}", is_x86_feature_detected!("sse4.1"));
+     println!("sse4.2: {:?}", is_x86_feature_detected!("sse4.2"));
+     println!("sse4a: {:?}", is_x86_feature_detected!("sse4a"));
+     println!("sha: {:?}", is_x86_feature_detected!("sha"));
+     println!("avx: {:?}", is_x86_feature_detected!("avx"));
+     println!("avx2: {:?}", is_x86_feature_detected!("avx2"));
+     println!("avx512f {:?}", is_x86_feature_detected!("avx512f"));
+     println!("avx512cd {:?}", is_x86_feature_detected!("avx512cd"));
+     println!("avx512er {:?}", is_x86_feature_detected!("avx512er"));
+     println!("avx512pf {:?}", is_x86_feature_detected!("avx512pf"));
+     println!("avx512bw {:?}", is_x86_feature_detected!("avx512bw"));
+     println!("avx512dq {:?}", is_x86_feature_detected!("avx512dq"));
+     println!("avx512vl {:?}", is_x86_feature_detected!("avx512vl"));
+     println!("avx512_ifma {:?}", is_x86_feature_detected!("avx512ifma"));
+     println!("avx512_vbmi {:?}", is_x86_feature_detected!("avx512vbmi"));
+     println!(
+         "avx512_vpopcntdq {:?}",
+         is_x86_feature_detected!("avx512vpopcntdq")
+     );
+     println!("avx512vbmi2 {:?}", is_x86_feature_detected!("avx512vbmi2"));
+     println!("avx512gfni {:?}", is_x86_feature_detected!("avx512gfni"));
+     println!("avx512vaes {:?}", is_x86_feature_detected!("avx512vaes"));
+     println!(
+         "avx512vpclmulqdq {:?}",
+         is_x86_feature_detected!("avx512vpclmulqdq")
+     );
+     println!("avx512vnni {:?}", is_x86_feature_detected!("avx512vnni"));
+     println!(
+         "avx512bitalg {:?}",
+         is_x86_feature_detected!("avx512bitalg")
+     );
+     println!("avx512bf16 {:?}", is_x86_feature_detected!("avx512bf16"));
+     println!(
+         "avx512vp2intersect {:?}",
+         is_x86_feature_detected!("avx512vp2intersect")
+     );
+     println!("fma: {:?}", is_x86_feature_detected!("fma"));
+     println!("abm: {:?}", is_x86_feature_detected!("abm"));
+     println!("bmi: {:?}", is_x86_feature_detected!("bmi1"));
+     println!("bmi2: {:?}", is_x86_feature_detected!("bmi2"));
+     println!("tbm: {:?}", is_x86_feature_detected!("tbm"));
+     println!("popcnt: {:?}", is_x86_feature_detected!("popcnt"));
+     println!("lzcnt: {:?}", is_x86_feature_detected!("lzcnt"));
+     println!("fxsr: {:?}", is_x86_feature_detected!("fxsr"));
+     println!("xsave: {:?}", is_x86_feature_detected!("xsave"));
+     println!("xsaveopt: {:?}", is_x86_feature_detected!("xsaveopt"));
+     println!("xsaves: {:?}", is_x86_feature_detected!("xsaves"));
+     println!("xsavec: {:?}", is_x86_feature_detected!("xsavec"));
+     println!("cmpxchg16b: {:?}", is_x86_feature_detected!("cmpxchg16b"));
+     println!("adx: {:?}", is_x86_feature_detected!("adx"));
+     println!("rtm: {:?}", is_x86_feature_detected!("rtm"));
+ }
+ 
+ #[cfg(feature = "std_detect_env_override")]
+ #[test]
+ fn env_override_no_avx() {
+     if let Ok(disable) = std::env::var("RUST_STD_DETECT_UNSTABLE") {
+         let information = cupid::master().unwrap();
+         for d in disable.split(" ") {
+             match d {
+                 "avx" => {
+                     if information.avx() {
+                         assert_ne!(is_x86_feature_detected!("avx"), information.avx())
+                     }
+                 }
+                 "avx2" => {
+                     if information.avx2() {
+                         assert_ne!(is_x86_feature_detected!("avx2"), information.avx2())
+                     }
+                 }
+                 _ => {}
+             }
+         }
+     }
+ }
+ 
+ #[test]
+ fn compare_with_cupid() {
+     let information = cupid::master().unwrap();
+     assert_eq!(is_x86_feature_detected!("aes"), information.aesni());
+     assert_eq!(
+         is_x86_feature_detected!("pclmulqdq"),
+         information.pclmulqdq()
+     );
+     assert_eq!(is_x86_feature_detected!("rdrand"), information.rdrand());
+     assert_eq!(is_x86_feature_detected!("rdseed"), information.rdseed());
+     assert_eq!(is_x86_feature_detected!("tsc"), information.tsc());
+     assert_eq!(is_x86_feature_detected!("sse"), information.sse());
+     assert_eq!(is_x86_feature_detected!("sse2"), information.sse2());
+     assert_eq!(is_x86_feature_detected!("sse3"), information.sse3());
+     assert_eq!(is_x86_feature_detected!("ssse3"), information.ssse3());
+     assert_eq!(is_x86_feature_detected!("sse4.1"), information.sse4_1());
+     assert_eq!(is_x86_feature_detected!("sse4.2"), information.sse4_2());
+     assert_eq!(is_x86_feature_detected!("sse4a"), information.sse4a());
+     assert_eq!(is_x86_feature_detected!("sha"), information.sha());
+     assert_eq!(is_x86_feature_detected!("avx"), information.avx());
+     assert_eq!(is_x86_feature_detected!("avx2"), information.avx2());
+     assert_eq!(is_x86_feature_detected!("avx512f"), information.avx512f());
+     assert_eq!(is_x86_feature_detected!("avx512cd"), information.avx512cd());
+     assert_eq!(is_x86_feature_detected!("avx512er"), information.avx512er());
+     assert_eq!(is_x86_feature_detected!("avx512pf"), information.avx512pf());
+     assert_eq!(is_x86_feature_detected!("avx512bw"), information.avx512bw());
+     assert_eq!(is_x86_feature_detected!("avx512dq"), information.avx512dq());
+     assert_eq!(is_x86_feature_detected!("avx512vl"), information.avx512vl());
+     assert_eq!(
+         is_x86_feature_detected!("avx512ifma"),
+         information.avx512_ifma()
+     );
+     assert_eq!(
+         is_x86_feature_detected!("avx512vbmi"),
+         information.avx512_vbmi()
+     );
+     assert_eq!(
+         is_x86_feature_detected!("avx512vpopcntdq"),
+         information.avx512_vpopcntdq()
+     );
+     assert_eq!(is_x86_feature_detected!("fma"), information.fma());
+     assert_eq!(is_x86_feature_detected!("bmi1"), information.bmi1());
+     assert_eq!(is_x86_feature_detected!("bmi2"), information.bmi2());
+     assert_eq!(is_x86_feature_detected!("popcnt"), information.popcnt());
+     assert_eq!(is_x86_feature_detected!("abm"), information.lzcnt());
+     assert_eq!(is_x86_feature_detected!("tbm"), information.tbm());
+     assert_eq!(is_x86_feature_detected!("lzcnt"), information.lzcnt());
+     assert_eq!(is_x86_feature_detected!("xsave"), information.xsave());
+     assert_eq!(is_x86_feature_detected!("xsaveopt"), information.xsaveopt());
+     assert_eq!(
+         is_x86_feature_detected!("xsavec"),
+         information.xsavec_and_xrstor()
+     );
+     assert_eq!(
+         is_x86_feature_detected!("xsaves"),
+         information.xsaves_xrstors_and_ia32_xss()
+     );
+     assert_eq!(
+         is_x86_feature_detected!("cmpxchg16b"),
+         information.cmpxchg16b(),
+     );
+     assert_eq!(is_x86_feature_detected!("adx"), information.adx(),);
+     assert_eq!(is_x86_feature_detected!("rtm"), information.rtm(),);
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,9 ----
+ [package]
+ name = "stdarch-gen"
+ version = "0.1.0"
+ authors = ["Heinz Gies <heinz@licenser.net>"]
+ edition = "2018"
+ 
+ # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+ 
+ [dependencies]
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/README.md gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/README.md
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/README.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/README.md	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,11 ----
+ # Neon intrinsic code generator
+ 
+ A small tool that allows to quickly generate intrinsics for the NEON architecture.
+ 
+ The specification for the intrinsics can be found in `neon.spec`.
+ 
+ To run and re-generate the code run the following from the root of the `stdarch` crate.
+ 
+ ```
+ OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec
+ ```
\ No newline at end of file
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/neon.spec gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/neon.spec
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/neon.spec	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/neon.spec	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,469 ----
+ // ARM Neon intrinsic specification.
+ // 
+ // This file contains the specification for a number of 
+ // intrinsics that allows us to generate them along with
+ // their test cases.
+ //
+ // To the syntax of the file - it's not very intelligently parsed!
+ //
+ // # Comments
+ // start with AT LEAST two, or four or more slashes  so // is a
+ // comment /////// is too.
+ //
+ // # Sections
+ // Sections start with EXACTLY three slashes followed
+ // by AT LEAST one space. Sections are used for two things:
+ //
+ // 1) they serve as the doc comment for the given intrinics.
+ // 2) they reset all variables (name, fn, etc.)
+ //
+ // # Variables
+ //
+ // name    - The prefix of the function, suffixes are auto
+ //           generated by the type they get passed.
+ //
+ // fn      - The function to call in rust-land.
+ //
+ // aarch64 - The intrinsic to check on aarch64 architecture.
+ //           If this is given but no arm intrinsic is provided,
+ //           the function will exclusively be generated for
+ //           aarch64.
+ //           This is used to generate both aarch64 specific and
+ //           shared intrinics by first only specifying th aarch64
+ //           variant then the arm variant.
+ // 
+ // arm     - The arm v7 intrinics used to checked for arm code
+ //           generation. All neon functions available in arm are
+ //           also available in aarch64. If no aarch64 intrinic was
+ //           set they are assumed to be the same.
+ //           Intrinics ending with a `.` will have a size suffixes
+ //           added (such as `i8` or `i64`) that is not sign specific
+ //           Intrinics ending with a `.s` will have a size suffixes
+ //           added (such as `s8` or `u64`) that is sign specific
+ //
+ // a       - First input for tests, it gets scaled to the size of
+ //           the type.
+ //
+ // b       - Second input for tests, it gets scaled to the size of
+ //           the type.
+ //
+ // # special values
+ //
+ // TRUE - 'true' all bits are set to 1
+ // FALSE - 'false' all bits are set to 0
+ // FF - same as 'true'
+ // MIN - minimal value (either 0 or the lowest negative number)
+ // MAX - maximal value propr to overflow
+ //
+ // # validate <values>
+ // Validates a and b aginst the expected result of the test.
+ // The special values 'TRUE' and 'FALSE' can be used to
+ // represent the corect NEON representation of true or
+ // false values. It too gets scaled to the type.
+ // 
+ // Validate needs to be called before generate as it sets
+ // up the rules for validation that get generated for each
+ // type.
+ // # generate <types>
+ // The generate command generates the intrinsics, it uses the
+ // Variables set and can be called multiple times while overwriting
+ // some of the variables.
+ 
+ /// Vector bitwise and
+ name = vand
+ fn = simd_and
+ arm = vand
+ aarch64 = and
+ a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00
+ b = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F
+ validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00
+ b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ validate 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ generate int*_t, uint*_t, int64x*_t, uint64x*_t
+ 
+ /// Vector bitwise or (immediate, inclusive)
+ name = vorr
+ fn = simd_or
+ arm = vorr
+ aarch64 = orr
+ a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+ b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+ generate int*_t, uint*_t, int64x*_t, uint64x*_t
+ 
+ 
+ /// Vector bitwise exclusive or (vector)
+ name = veor
+ fn = simd_xor
+ arm = veor
+ aarch64 = eor
+ a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+ b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+ generate int*_t, uint*_t, int64x*_t, uint64x*_t
+ 
+ ////////////////////
+ // equality
+ ////////////////////
+ 
+ /// Compare bitwise Equal (vector)
+ name = vceq
+ fn = simd_eq
+ a = MIN, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, MAX
+ b = MIN, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, MAX
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ a = MIN, MIN, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, MAX
+ b = MIN, MAX, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, MIN
+ validate TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE
+ 
+ aarch64 = cmeq
+ generate uint64x*_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t, poly64x1_t:uint64x1_t, poly64x2_t:uint64x2_t
+ 
+ arm = vceq.
+ generate uint*_t, int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t
+ 
+ /// Floating-point compare equal
+ name = vceq
+ fn = simd_eq
+ a = 1.2, 3.4, 5.6, 7.8
+ b = 1.2, 3.4, 5.6, 7.8
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = fcmeq
+ generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t
+ 
+ arm = vceq.
+ // we are missing float16x4_t:uint16x4_t, float16x8_t:uint16x8_t
+ generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t
+ 
+ ////////////////////
+ // greater then
+ ////////////////////
+ 
+ /// Compare signed greater than
+ name = vcgt
+ fn = simd_gt
+ a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ aarch64 = cmgt
+ generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
+ 
+ arm = vcgt.s
+ generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t
+ 
+ /// Compare unsigned highe
+ name = vcgt
+ fn = simd_gt
+ a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = cmhi
+ generate uint64x*_t
+ 
+ arm = vcgt.s
+ generate uint*_t
+ 
+ /// Floating-point compare greater than
+ name = vcgt
+ fn = simd_gt
+ a = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 
+ b = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = fcmgt
+ generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t
+ 
+ arm = vcgt.s
+ // we are missing float16x4_t:uint16x4_t, float16x8_t:uint16x8_t
+ generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t
+ 
+ ////////////////////
+ // lesser then
+ ////////////////////
+ 
+ /// Compare signed less than
+ name = vclt
+ fn = simd_lt
+ a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ aarch64 = cmgt
+ generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
+ 
+ arm = vcgt.s
+ generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t
+ 
+ /// Compare unsigned less than
+ name = vclt
+ fn = simd_lt
+ a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = cmhi
+ generate uint64x*_t
+ 
+ arm = vcgt.s
+ generate uint*_t
+ 
+ /// Floating-point compare less than
+ name = vclt
+ fn = simd_lt
+ a = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8
+ b = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = fcmgt
+ generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t
+ 
+ arm = vcgt.s
+ // we are missing float16x4_t:uint16x4_t, float16x8_t:uint16x8_t
+ generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t
+ 
+ ////////////////////
+ // lesser then equals
+ ////////////////////
+ 
+ /// Compare signed less than or equal
+ name = vcle
+ fn = simd_le
+ a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = cmge
+ generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
+ 
+ arm = vcge.s
+ generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t
+ 
+ /// Compare unsigned less than or equal
+ name = vcle
+ fn = simd_le
+ a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = cmhs
+ generate uint64x*_t
+ 
+ arm = vcge.s
+ generate uint*_t
+ 
+ /// Floating-point compare less than or equal
+ name = vcle
+ fn = simd_le
+ a = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8
+ b = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ aarch64 = fcmge
+ generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t
+ 
+ // we are missing float16x4_t:uint16x4_t, float16x8_t:uint16x8_t
+ arm = vcge.s
+ generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t
+ 
+ ////////////////////
+ // greater then equals
+ ////////////////////
+ 
+ /// Compare signed greater than or equal
+ name = vcge
+ fn = simd_ge
+ a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = cmge
+ generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
+ 
+ arm = vcge.s
+ generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t
+ 
+ /// Compare unsigned greater than or equal
+ name = vcge
+ fn = simd_ge
+ a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = cmhs
+ generate uint64x*_t
+ 
+ arm = vcge.s
+ generate uint*_t
+ 
+ /// Floating-point compare greater than or equal
+ name = vcge
+ fn = simd_ge
+ a = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 
+ b = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8
+ validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
+ 
+ aarch64 = fcmge
+ generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t
+ 
+ arm = vcge.s
+ // we are missing float16x4_t:uint16x4_t, float16x8_t:uint16x8_t
+ generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t
+ 
+ /// Saturating subtract
+ name = vqsub
+ a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26
+ 
+ arm = vqsub.s
+ aarch64 = uqsub
+ link-arm = vqsubu._EXT_
+ link-aarch64 = uqsub._EXT_
+ generate uint*_t
+ 
+ arm = vqsub.s
+ aarch64 = sqsub
+ link-arm = vqsubs._EXT_
+ link-aarch64 = sqsub._EXT_
+ generate int*_t
+ 
+ /// Halving add
+ name = vhadd
+ a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate 21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29
+ 
+ 
+ arm = vhadd.s
+ aarch64 = uhadd
+ link-aarch64 = uhadd._EXT_
+ link-arm = vhaddu._EXT_
+ generate uint*_t
+ 
+ 
+ arm = vhadd.s
+ aarch64 = shadd
+ link-aarch64 = shadd._EXT_
+ link-arm = vhadds._EXT_
+ generate int*_t
+ 
+ /// Rounding halving add
+ name = vrhadd
+ a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29
+ 
+ arm = vrhadd.s
+ aarch64 = urhadd
+ link-arm = vrhaddu._EXT_
+ link-aarch64 = urhadd._EXT_
+ generate uint*_t
+ 
+ arm = vrhadd.s
+ aarch64 = srhadd
+ link-arm = vrhadds._EXT_
+ link-aarch64 = srhadd._EXT_
+ generate int*_t
+ 
+ /// Saturating add
+ name = vqadd
+ a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58
+ 
+ arm = vqadd.s
+ aarch64 = uqadd
+ link-arm = vqaddu._EXT_
+ link-aarch64 = uqadd._EXT_
+ generate uint*_t
+ 
+ arm = vqadd.s
+ aarch64 = sqadd
+ link-arm = vqadds._EXT_
+ link-aarch64 = sqadd._EXT_
+ generate int*_t
+ 
+ // requires 1st and second argument to be different, this not implemented yet
+ // /// Signed saturating accumulate of unsigned value
+ // 
+ // name = vuqadd
+ // a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42
+ // b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ // e = 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58
+ 
+ // it seems like we don't have those in rustland :( 
+ // aarch64 = suqadd 
+ // link-aarch64 = usqadd._EXT_
+ // generate int64x*_t
+ 
+ / arm = suqadd
+ // link-arm = vuqadds._EXT_
+ // link-aarch64 = suqadd._EXT_
+ // generate int*_t
+ 
+ 
+ /// Multiply
+ name = vmul
+ a = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2
+ b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ validate 1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32
+ arm = vmul.
+ aarch64 = mul
+ fn = simd_mul
+ generate int*_t, uint*_t
+ 
+ /// Multiply
+ name = vmul
+ fn = simd_mul
+ a = 1.0, 2.0, 1.0, 2.0
+ b = 2.0, 3.0, 4.0, 5.0
+ validate 2.0, 6.0, 4.0, 10.0
+ 
+ aarch64 = fmul
+ generate float64x*_t
+ 
+ arm = vmul.
+ generate float*_t
+ 
+ 
+ /// Subtract
+ name = vsub
+ a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2
+ validate 0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14
+ arm = vsub.
+ aarch64 = sub
+ fn = simd_sub
+ generate int*_t, uint*_t, int64x*_t, uint64x*_t
+ 
+ /// Subtract
+ name = vsub
+ fn = simd_sub
+ a = 1.0, 4.0, 3.0, 8.0
+ b = 1.0, 2.0, 3.0, 4.0
+ validate 0.0, 2.0, 0.0, 4.0
+ 
+ aarch64 = fsub
+ generate float64x*_t
+ 
+ arm = vsub.
+ generate float*_t
+ 
+ 
+ /// Signed halving subtract
+ name = vhsub
+ a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2
+ validate 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7
+ 
+ arm = vhsub.s
+ aarch64 = uhsub
+ link-arm = vhsubu._EXT_
+ link-aarch64 = uhsub._EXT_
+ generate uint*_t
+ 
+ arm = vhsub.s
+ aarch64 = shsub
+ link-arm = vhsubs._EXT_
+ link-aarch64 = shsub._EXT_
+ generate int*_t
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/src/main.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/src/main.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-gen/src/main.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-gen/src/main.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,750 ----
+ use std::env;
+ use std::fs::File;
+ use std::io::prelude::*;
+ use std::io::{self, BufReader};
+ use std::path::PathBuf;
+ 
+ const IN: &str = "neon.spec";
+ const ARM_OUT: &str = "generated.rs";
+ const AARCH64_OUT: &str = "generated.rs";
+ 
+ const UINT_TYPES: [&str; 6] = [
+     "uint8x8_t",
+     "uint8x16_t",
+     "uint16x4_t",
+     "uint16x8_t",
+     "uint32x2_t",
+     "uint32x4_t",
+ ];
+ 
+ const UINT_TYPES_64: [&str; 2] = ["uint64x1_t", "uint64x2_t"];
+ 
+ const INT_TYPES: [&str; 6] = [
+     "int8x8_t",
+     "int8x16_t",
+     "int16x4_t",
+     "int16x8_t",
+     "int32x2_t",
+     "int32x4_t",
+ ];
+ 
+ const INT_TYPES_64: [&str; 2] = ["int64x1_t", "int64x2_t"];
+ 
+ const FLOAT_TYPES: [&str; 2] = [
+     //"float8x8_t", not supported by rust
+     //"float8x16_t", not supported by rust
+     //"float16x4_t", not supported by rust
+     //"float16x8_t", not supported by rust
+     "float32x2_t",
+     "float32x4_t",
+ ];
+ 
+ const FLOAT_TYPES_64: [&str; 2] = [
+     //"float8x8_t", not supported by rust
+     //"float8x16_t", not supported by rust
+     //"float16x4_t", not supported by rust
+     //"float16x8_t", not supported by rust
+     "float64x1_t",
+     "float64x2_t",
+ ];
+ 
+ fn type_len(t: &str) -> usize {
+     match t {
+         "int8x8_t" => 8,
+         "int8x16_t" => 16,
+         "int16x4_t" => 4,
+         "int16x8_t" => 8,
+         "int32x2_t" => 2,
+         "int32x4_t" => 4,
+         "int64x1_t" => 1,
+         "int64x2_t" => 2,
+         "uint8x8_t" => 8,
+         "uint8x16_t" => 16,
+         "uint16x4_t" => 4,
+         "uint16x8_t" => 8,
+         "uint32x2_t" => 2,
+         "uint32x4_t" => 4,
+         "uint64x1_t" => 1,
+         "uint64x2_t" => 2,
+         "float16x4_t" => 4,
+         "float16x8_t" => 8,
+         "float32x2_t" => 2,
+         "float32x4_t" => 4,
+         "float64x1_t" => 1,
+         "float64x2_t" => 2,
+         "poly64x1_t" => 1,
+         "poly64x2_t" => 2,
+         _ => panic!("unknown type: {}", t),
+     }
+ }
+ 
+ fn type_to_suffix(t: &str) -> &str {
+     match t {
+         "int8x8_t" => "_s8",
+         "int8x16_t" => "q_s8",
+         "int16x4_t" => "_s16",
+         "int16x8_t" => "q_s16",
+         "int32x2_t" => "_s32",
+         "int32x4_t" => "q_s32",
+         "int64x1_t" => "_s64",
+         "int64x2_t" => "q_s64",
+         "uint8x8_t" => "_u8",
+         "uint8x16_t" => "q_u8",
+         "uint16x4_t" => "_u16",
+         "uint16x8_t" => "q_u16",
+         "uint32x2_t" => "_u32",
+         "uint32x4_t" => "q_u32",
+         "uint64x1_t" => "_u64",
+         "uint64x2_t" => "q_u64",
+         "float16x4_t" => "_f16",
+         "float16x8_t" => "q_f16",
+         "float32x2_t" => "_f32",
+         "float32x4_t" => "q_f32",
+         "float64x1_t" => "_f64",
+         "float64x2_t" => "q_f64",
+         "poly64x1_t" => "_p64",
+         "poly64x2_t" => "q_p64",
+         _ => panic!("unknown type: {}", t),
+     }
+ }
+ 
+ fn type_to_global_type(t: &str) -> &str {
+     match t {
+         "int8x8_t" => "i8x8",
+         "int8x16_t" => "i8x16",
+         "int16x4_t" => "i16x4",
+         "int16x8_t" => "i16x8",
+         "int32x2_t" => "i32x2",
+         "int32x4_t" => "i32x4",
+         "int64x1_t" => "i64x1",
+         "int64x2_t" => "i64x2",
+         "uint8x8_t" => "u8x8",
+         "uint8x16_t" => "u8x16",
+         "uint16x4_t" => "u16x4",
+         "uint16x8_t" => "u16x8",
+         "uint32x2_t" => "u32x2",
+         "uint32x4_t" => "u32x4",
+         "uint64x1_t" => "u64x1",
+         "uint64x2_t" => "u64x2",
+         "float16x4_t" => "f16x4",
+         "float16x8_t" => "f16x8",
+         "float32x2_t" => "f32x2",
+         "float32x4_t" => "f32x4",
+         "float64x1_t" => "f64",
+         "float64x2_t" => "f64x2",
+         "poly64x1_t" => "i64x1",
+         "poly64x2_t" => "i64x2",
+         _ => panic!("unknown type: {}", t),
+     }
+ }
+ 
+ // fn type_to_native_type(t: &str) -> &str {
+ //     match t {
+ //         "int8x8_t" => "i8",
+ //         "int8x16_t" => "i8",
+ //         "int16x4_t" => "i16",
+ //         "int16x8_t" => "i16",
+ //         "int32x2_t" => "i32",
+ //         "int32x4_t" => "i32",
+ //         "int64x1_t" => "i64",
+ //         "int64x2_t" => "i64",
+ //         "uint8x8_t" => "u8",
+ //         "uint8x16_t" => "u8",
+ //         "uint16x4_t" => "u16",
+ //         "uint16x8_t" => "u16",
+ //         "uint32x2_t" => "u32",
+ //         "uint32x4_t" => "u32",
+ //         "uint64x1_t" => "u64",
+ //         "uint64x2_t" => "u64",
+ //         "float16x4_t" => "f16",
+ //         "float16x8_t" => "f16",
+ //         "float32x2_t" => "f32",
+ //         "float32x4_t" => "f32",
+ //         "float64x1_t" => "f64",
+ //         "float64x2_t" => "f64",
+ //         "poly64x1_t" => "i64",
+ //         "poly64x2_t" => "i64",
+ //         _ => panic!("unknown type: {}", t),
+ //     }
+ // }
+ 
+ fn type_to_ext(t: &str) -> &str {
+     match t {
+         "int8x8_t" => "v8i8",
+         "int8x16_t" => "v16i8",
+         "int16x4_t" => "v4i16",
+         "int16x8_t" => "v8i16",
+         "int32x2_t" => "v2i32",
+         "int32x4_t" => "v4i32",
+         "int64x1_t" => "v1i64",
+         "int64x2_t" => "v2i64",
+         "uint8x8_t" => "v8i8",
+         "uint8x16_t" => "v16i8",
+         "uint16x4_t" => "v4i16",
+         "uint16x8_t" => "v8i16",
+         "uint32x2_t" => "v2i32",
+         "uint32x4_t" => "v4i32",
+         "uint64x1_t" => "v1i64",
+         "uint64x2_t" => "v2i64",
+         "float16x4_t" => "v4f16",
+         "float16x8_t" => "v8f16",
+         "float32x2_t" => "v2f32",
+         "float32x4_t" => "v4f32",
+         "float64x1_t" => "v1f64",
+         "float64x2_t" => "v2f64",
+         /*
+         "poly64x1_t" => "i64x1",
+         "poly64x2_t" => "i64x2",
+         */
+         _ => panic!("unknown type for extension: {}", t),
+     }
+ }
+ 
+ fn values(t: &str, vs: &[String]) -> String {
+     if vs.len() == 1 && !t.contains('x') {
+         format!(": {} = {}", t, vs[0])
+     } else if vs.len() == 1 && type_to_global_type(t) == "f64" {
+         format!(": {} = {}", type_to_global_type(t), vs[0])
+     } else {
+         format!(
+             ": {} = {}::new({})",
+             type_to_global_type(t),
+             type_to_global_type(t),
+             vs.iter()
+                 .map(|v| map_val(type_to_global_type(t), v))
+                 //.map(|v| format!("{}{}", v, type_to_native_type(t)))
+                 .collect::<Vec<_>>()
+                 .join(", ")
+         )
+     }
+ }
+ 
+ fn max_val(t: &str) -> &'static str {
+     match &t[..3] {
+         "u8x" => "0xFF",
+         "u16" => "0xFF_FF",
+         "u32" => "0xFF_FF_FF_FF",
+         "u64" => "0xFF_FF_FF_FF_FF_FF_FF_FF",
+         "i8x" => "0x7F",
+         "i16" => "0x7F_FF",
+         "i32" => "0x7F_FF_FF_FF",
+         "i64" => "0x7F_FF_FF_FF_FF_FF_FF_FF",
+         "f32" => "3.40282347e+38",
+         "f64" => "1.7976931348623157e+308",
+         _ => panic!("No TRUE for type {}", t),
+     }
+ }
+ 
+ fn min_val(t: &str) -> &'static str {
+     match &t[..3] {
+         "u8x" => "0",
+         "u16" => "0",
+         "u32" => "0",
+         "u64" => "0",
+         "i8x" => "-128",
+         "i16" => "-32768",
+         "i32" => "-2147483648",
+         "i64" => "-9223372036854775808",
+         "f32" => "-3.40282347e+38",
+         "f64" => "-1.7976931348623157e+308",
+         _ => panic!("No TRUE for type {}", t),
+     }
+ }
+ 
+ fn true_val(t: &str) -> &'static str {
+     match &t[..3] {
+         "u8x" => "0xFF",
+         "u16" => "0xFF_FF",
+         "u32" => "0xFF_FF_FF_FF",
+         "u64" => "0xFF_FF_FF_FF_FF_FF_FF_FF",
+         _ => panic!("No TRUE for type {}", t),
+     }
+ }
+ 
+ fn ff_val(t: &str) -> &'static str {
+     match &t[..3] {
+         "u8x" => "0xFF",
+         "u16" => "0xFF_FF",
+         "u32" => "0xFF_FF_FF_FF",
+         "u64" => "0xFF_FF_FF_FF_FF_FF_FF_FF",
+         "i8x" => "0xFF",
+         "i16" => "0xFF_FF",
+         "i32" => "0xFF_FF_FF_FF",
+         "i64" => "0xFF_FF_FF_FF_FF_FF_FF_FF",
+         _ => panic!("No TRUE for type {}", t),
+     }
+ }
+ 
+ fn false_val(_t: &str) -> &'static str {
+     "0"
+ }
+ fn map_val<'v>(t: &str, v: &'v str) -> &'v str {
+     match v {
+         "FALSE" => false_val(t),
+         "TRUE" => true_val(t),
+         "MAX" => min_val(t),
+         "MIN" => max_val(t),
+         "FF" => ff_val(t),
+         o => o,
+     }
+ }
+ 
+ #[allow(clippy::too_many_arguments)]
+ fn gen_aarch64(
+     current_comment: &str,
+     current_fn: &Option<String>,
+     name: &str,
+     current_aarch64: &Option<String>,
+     link_aarch64: &Option<String>,
+     in_t: &str,
+     out_t: &str,
+     current_tests: &[(Vec<String>, Vec<String>, Vec<String>)],
+ ) -> (String, String) {
+     let _global_t = type_to_global_type(in_t);
+     let _global_ret_t = type_to_global_type(out_t);
+     let current_fn = if let Some(current_fn) = current_fn.clone() {
+         if link_aarch64.is_some() {
+             panic!("[{}] Can't specify link and fn at the same time.", name)
+         }
+         current_fn
+     } else {
+         if link_aarch64.is_none() {
+             panic!("[{}] Either fn or link-aarch have to be specified.", name)
+         }
+         format!("{}_", name)
+     };
+     let current_aarch64 = current_aarch64.clone().unwrap();
+     let ext_c = if let Some(link_aarch64) = link_aarch64.clone() {
+         let ext = type_to_ext(in_t);
+ 
+         format!(
+             r#"
+     #[allow(improper_ctypes)]
+     extern "C" {{
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.{}")]
+         fn {}(a: {}, a: {}) -> {};
+     }}
+ "#,
+             link_aarch64.replace("_EXT_", ext),
+             current_fn,
+             in_t,
+             in_t,
+             out_t
+         )
+     } else {
+         String::new()
+     };
+     let function = format!(
+         r#"
+ {}
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(test, assert_instr({}))]
+ pub unsafe fn {}(a: {}, b: {}) -> {} {{
+     {}{}(a, b)
+ }}
+ "#,
+         current_comment, current_aarch64, name, in_t, in_t, out_t, ext_c, current_fn,
+     );
+ 
+     let test = gen_test(name, &in_t, &out_t, current_tests, type_len(in_t));
+     (function, test)
+ }
+ 
+ fn gen_test(
+     name: &str,
+     in_t: &str,
+     out_t: &str,
+     current_tests: &[(Vec<String>, Vec<String>, Vec<String>)],
+     len: usize,
+ ) -> String {
+     let mut test = format!(
+         r#"
+     #[simd_test(enable = "neon")]
+     unsafe fn test_{}() {{"#,
+         name,
+     );
+     for (a, b, e) in current_tests {
+         let a: Vec<String> = a.iter().take(len).cloned().collect();
+         let b: Vec<String> = b.iter().take(len).cloned().collect();
+         let e: Vec<String> = e.iter().take(len).cloned().collect();
+         let t = format!(
+             r#"
+         let a{};
+         let b{};
+         let e{};
+         let r: {} = transmute({}(transmute(a), transmute(b)));
+         assert_eq!(r, e);
+ "#,
+             values(in_t, &a),
+             values(in_t, &b),
+             values(out_t, &e),
+             type_to_global_type(out_t),
+             name
+         );
+         test.push_str(&t);
+     }
+     test.push_str("    }\n");
+     test
+ }
+ 
+ #[allow(clippy::too_many_arguments)]
+ fn gen_arm(
+     current_comment: &str,
+     current_fn: &Option<String>,
+     name: &str,
+     current_arm: &str,
+     link_arm: &Option<String>,
+     current_aarch64: &Option<String>,
+     link_aarch64: &Option<String>,
+     in_t: &str,
+     out_t: &str,
+     current_tests: &[(Vec<String>, Vec<String>, Vec<String>)],
+ ) -> (String, String) {
+     let _global_t = type_to_global_type(in_t);
+     let _global_ret_t = type_to_global_type(out_t);
+     let current_aarch64 = current_aarch64
+         .clone()
+         .unwrap_or_else(|| current_arm.to_string());
+ 
+     let current_fn = if let Some(current_fn) = current_fn.clone() {
+         if link_aarch64.is_some() || link_arm.is_some() {
+             panic!(
+                 "[{}] Can't specify link and function at the same time. {} / {:?} / {:?}",
+                 name, current_fn, link_aarch64, link_arm
+             )
+         }
+         current_fn
+     } else {
+         if link_aarch64.is_none() || link_arm.is_none() {
+             panic!(
+                 "[{}] Either fn or link-arm and link-aarch have to be specified.",
+                 name
+             )
+         }
+         format!("{}_", name)
+     };
+ 
+     let ext_c =
+         if let (Some(link_arm), Some(link_aarch64)) = (link_arm.clone(), link_aarch64.clone()) {
+             let ext = type_to_ext(in_t);
+ 
+             format!(
+                 r#"#[allow(improper_ctypes)]
+     extern "C" {{
+         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.{}")]
+         #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.{}")]
+         fn {}(a: {}, b: {}) -> {};
+     }}
+ "#,
+                 link_arm.replace("_EXT_", ext),
+                 link_aarch64.replace("_EXT_", ext),
+                 current_fn,
+                 in_t,
+                 in_t,
+                 out_t
+             )
+         } else {
+             String::new()
+         };
+ 
+     let function = format!(
+         r#"
+ {}
+ #[inline]
+ #[target_feature(enable = "neon")]
+ #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+ #[cfg_attr(all(test, target_arch = "arm"), assert_instr({}))]
+ #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr({}))]
+ pub unsafe fn {}(a: {}, b: {}) -> {} {{
+     {}{}(a, b)
+ }}
+ "#,
+         current_comment,
+         expand_intrinsic(&current_arm, in_t),
+         expand_intrinsic(&current_aarch64, in_t),
+         name,
+         in_t,
+         in_t,
+         out_t,
+         ext_c,
+         current_fn,
+     );
+     let test = gen_test(name, &in_t, &out_t, current_tests, type_len(in_t));
+ 
+     (function, test)
+ }
+ 
+ fn expand_intrinsic(intr: &str, t: &str) -> String {
+     if intr.ends_with(".") {
+         let ext = match t {
+             "int8x8_t" => "i8",
+             "int8x16_t" => "i8",
+             "int16x4_t" => "i16",
+             "int16x8_t" => "i16",
+             "int32x2_t" => "i32",
+             "int32x4_t" => "i32",
+             "int64x1_t" => "i64",
+             "int64x2_t" => "i64",
+             "uint8x8_t" => "i8",
+             "uint8x16_t" => "i8",
+             "uint16x4_t" => "i16",
+             "uint16x8_t" => "i16",
+             "uint32x2_t" => "i32",
+             "uint32x4_t" => "i32",
+             "uint64x1_t" => "i64",
+             "uint64x2_t" => "i64",
+             "float16x4_t" => "f16",
+             "float16x8_t" => "f16",
+             "float32x2_t" => "f32",
+             "float32x4_t" => "f32",
+             "float64x1_t" => "f64",
+             "float64x2_t" => "f64",
+             /*
+             "poly64x1_t" => "i64x1",
+             "poly64x2_t" => "i64x2",
+             */
+             _ => panic!("unknown type for extension: {}", t),
+         };
+         format!(r#""{}{}""#, intr, ext)
+     } else if intr.ends_with(".s") {
+         let ext = match t {
+             "int8x8_t" => "s8",
+             "int8x16_t" => "s8",
+             "int16x4_t" => "s16",
+             "int16x8_t" => "s16",
+             "int32x2_t" => "s32",
+             "int32x4_t" => "s32",
+             "int64x1_t" => "s64",
+             "int64x2_t" => "s64",
+             "uint8x8_t" => "u8",
+             "uint8x16_t" => "u8",
+             "uint16x4_t" => "u16",
+             "uint16x8_t" => "u16",
+             "uint32x2_t" => "u32",
+             "uint32x4_t" => "u32",
+             "uint64x1_t" => "u64",
+             "uint64x2_t" => "u64",
+             "float16x4_t" => "f16",
+             "float16x8_t" => "f16",
+             "float32x2_t" => "f32",
+             "float32x4_t" => "f32",
+             "float64x1_t" => "f64",
+             "float64x2_t" => "f64",
+             /*
+             "poly64x1_t" => "i64x1",
+             "poly64x2_t" => "i64x2",
+             */
+             _ => panic!("unknown type for extension: {}", t),
+         };
+         format!(r#""{}{}""#, &intr[..intr.len() - 1], ext)
+     } else {
+         intr.to_string()
+     }
+ }
+ 
+ fn main() -> io::Result<()> {
+     let args: Vec<String> = env::args().collect();
+     let in_file = args.get(1).cloned().unwrap_or_else(|| IN.to_string());
+ 
+     let f = File::open(in_file).expect("Failed to open neon.spec");
+     let f = BufReader::new(f);
+ 
+     let mut current_comment = String::new();
+     let mut current_name: Option<String> = None;
+     let mut current_fn: Option<String> = None;
+     let mut current_arm: Option<String> = None;
+     let mut current_aarch64: Option<String> = None;
+     let mut link_arm: Option<String> = None;
+     let mut link_aarch64: Option<String> = None;
+     let mut a: Vec<String> = Vec::new();
+     let mut b: Vec<String> = Vec::new();
+     let mut current_tests: Vec<(Vec<String>, Vec<String>, Vec<String>)> = Vec::new();
+ 
+     //
+     // THIS FILE IS GENERATED FORM neon.spec DO NOT CHANGE IT MANUALLY
+     //
+     let mut out_arm = String::from(
+         r#"// This code is automatically generated. DO NOT MODIFY.
+ //
+ // Instead, modify `crates/stdarch-gen/neon.spec` and run the following command to re-generate this file:
+ //
+ // ```
+ // OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec
+ // ```
+ use super::*;
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ "#,
+     );
+     let mut tests_arm = String::from(
+         r#"
+ #[cfg(test)]
+ #[allow(overflowing_literals)]
+ mod test {
+     use super::*;
+     use crate::core_arch::simd::*;
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ "#,
+     );
+     //
+     // THIS FILE IS GENERATED FORM neon.spec DO NOT CHANGE IT MANUALLY
+     //
+     let mut out_aarch64 = String::from(
+         r#"// This code is automatically generated. DO NOT MODIFY.
+ //
+ // Instead, modify `crates/stdarch-gen/neon.spec` and run the following command to re-generate this file:
+ //
+ // ```
+ // OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec
+ // ```
+ use super::*;
+ #[cfg(test)]
+ use stdarch_test::assert_instr;
+ "#,
+     );
+     let mut tests_aarch64 = String::from(
+         r#"
+ #[cfg(test)]
+ mod test {
+     use super::*;
+     use crate::core_arch::simd::*;
+     use std::mem::transmute;
+     use stdarch_test::simd_test;
+ "#,
+     );
+ 
+     for line in f.lines() {
+         let line = line.unwrap();
+         if line.is_empty() {
+             continue;
+         }
+         if line.starts_with("/// ") {
+             current_comment = line;
+             current_name = None;
+             current_fn = None;
+             current_arm = None;
+             current_aarch64 = None;
+             link_aarch64 = None;
+             link_arm = None;
+             current_tests = Vec::new();
+         } else if line.starts_with("//") {
+         } else if line.starts_with("name = ") {
+             current_name = Some(String::from(&line[7..]));
+         } else if line.starts_with("fn = ") {
+             current_fn = Some(String::from(&line[5..]));
+         } else if line.starts_with("arm = ") {
+             current_arm = Some(String::from(&line[6..]));
+         } else if line.starts_with("aarch64 = ") {
+             current_aarch64 = Some(String::from(&line[10..]));
+         } else if line.starts_with("a = ") {
+             a = line[4..].split(',').map(|v| v.trim().to_string()).collect();
+         } else if line.starts_with("b = ") {
+             b = line[4..].split(',').map(|v| v.trim().to_string()).collect();
+         } else if line.starts_with("validate ") {
+             let e = line[9..].split(',').map(|v| v.trim().to_string()).collect();
+             current_tests.push((a.clone(), b.clone(), e));
+         } else if line.starts_with("link-aarch64 = ") {
+             link_aarch64 = Some(String::from(&line[15..]));
+         } else if line.starts_with("link-arm = ") {
+             link_arm = Some(String::from(&line[11..]));
+         } else if line.starts_with("generate ") {
+             let line = &line[9..];
+             let types: Vec<String> = line
+                 .split(',')
+                 .map(|v| v.trim().to_string())
+                 .flat_map(|v| match v.as_str() {
+                     "uint*_t" => UINT_TYPES.iter().map(|v| v.to_string()).collect(),
+                     "uint64x*_t" => UINT_TYPES_64.iter().map(|v| v.to_string()).collect(),
+                     "int*_t" => INT_TYPES.iter().map(|v| v.to_string()).collect(),
+                     "int64x*_t" => INT_TYPES_64.iter().map(|v| v.to_string()).collect(),
+                     "float*_t" => FLOAT_TYPES.iter().map(|v| v.to_string()).collect(),
+                     "float64x*_t" => FLOAT_TYPES_64.iter().map(|v| v.to_string()).collect(),
+                     _ => vec![v],
+                 })
+                 .collect();
+ 
+             for line in types {
+                 let spec: Vec<&str> = line.split(':').map(|e| e.trim()).collect();
+                 let in_t;
+                 let out_t;
+                 if spec.len() == 1 {
+                     in_t = spec[0];
+                     out_t = spec[0];
+                 } else if spec.len() == 2 {
+                     in_t = spec[0];
+                     out_t = spec[1];
+                 } else {
+                     panic!("Bad spec: {}", line)
+                 }
+                 let current_name = current_name.clone().unwrap();
+                 let name = format!("{}{}", current_name, type_to_suffix(in_t),);
+ 
+                 if let Some(current_arm) = current_arm.clone() {
+                     let (function, test) = gen_arm(
+                         &current_comment,
+                         &current_fn,
+                         &name,
+                         &current_arm,
+                         &link_arm,
+                         &current_aarch64,
+                         &link_aarch64,
+                         &in_t,
+                         &out_t,
+                         &current_tests,
+                     );
+                     out_arm.push_str(&function);
+                     tests_arm.push_str(&test);
+                 } else {
+                     let (function, test) = gen_aarch64(
+                         &current_comment,
+                         &current_fn,
+                         &name,
+                         &current_aarch64,
+                         &link_aarch64,
+                         &in_t,
+                         &out_t,
+                         &current_tests,
+                     );
+                     out_aarch64.push_str(&function);
+                     tests_aarch64.push_str(&test);
+                 }
+             }
+         }
+     }
+     tests_arm.push('}');
+     tests_arm.push('\n');
+     tests_aarch64.push('}');
+     tests_aarch64.push('\n');
+ 
+     let arm_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap())
+         .join("src")
+         .join("arm")
+         .join("neon");
+     std::fs::create_dir_all(&arm_out_path)?;
+ 
+     let mut file_arm = File::create(arm_out_path.join(ARM_OUT))?;
+     file_arm.write_all(out_arm.as_bytes())?;
+     file_arm.write_all(tests_arm.as_bytes())?;
+ 
+     let aarch64_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap())
+         .join("src")
+         .join("aarch64")
+         .join("neon");
+     std::fs::create_dir_all(&aarch64_out_path)?;
+ 
+     let mut file_aarch = File::create(aarch64_out_path.join(AARCH64_OUT))?;
+     file_aarch.write_all(out_aarch64.as_bytes())?;
+     file_aarch.write_all(tests_aarch64.as_bytes())?;
+     /*
+     if let Err(e) = Command::new("rustfmt")
+         .arg(&arm_out_path)
+         .arg(&aarch64_out_path)
+         .status() {
+             eprintln!("Could not format `{}`: {}", arm_out_path.to_str().unwrap(), e);
+             eprintln!("Could not format `{}`: {}", aarch64_out_path.to_str().unwrap(), e);
+     };
+     */
+     Ok(())
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,23 ----
+ [package]
+ name = "stdarch-test"
+ version = "0.1.0"
+ authors = ["Alex Crichton <alex@alexcrichton.com>"]
+ 
+ [dependencies]
+ assert-instr-macro = { path = "../assert-instr-macro" }
+ simd-test-macro = { path = "../simd-test-macro" }
+ cc = "1.0"
+ lazy_static = "1.0"
+ rustc-demangle = "0.1.8"
+ cfg-if = "0.1"
+ 
+ # We use a crates.io dependency to disassemble wasm binaries to look for
+ # instructions for `#[assert_instr]`. Note that we use an `=` dependency here
+ # instead of a floating dependency because the text format for wasm changes over
+ # time, and we want to make updates to this explicit rather than automatically
+ # picking up updates which might break CI with new instruction names.
+ [target.'cfg(target_arch = "wasm32")'.dependencies]
+ wasmprinter = "=0.2.6"
+ 
+ [features]
+ default = []
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,183 ----
+ //! Disassembly calling function for most targets.
+ 
+ use crate::Function;
+ use std::{collections::HashSet, env, process::Command, str};
+ 
+ // Extracts the "shim" name from the `symbol`.
+ fn normalize(mut symbol: &str) -> String {
+     // Remove trailing colon:
+     if symbol.ends_with(':') {
+         symbol = &symbol[..symbol.len() - 1];
+     }
+     if symbol.ends_with('>') {
+         symbol = &symbol[..symbol.len() - 1];
+     }
+     if let Some(idx) = symbol.find('<') {
+         symbol = &symbol[idx + 1..];
+     }
+ 
+     let mut symbol = rustc_demangle::demangle(symbol).to_string();
+     symbol = match symbol.rfind("::h") {
+         Some(i) => symbol[..i].to_string(),
+         None => symbol.to_string(),
+     };
+ 
+     // Remove Rust paths
+     if let Some(last_colon) = symbol.rfind(':') {
+         symbol = (&symbol[last_colon + 1..]).to_string();
+     }
+ 
+     // Normalize to no leading underscore to handle platforms that may
+     // inject extra ones in symbol names.
+     while symbol.starts_with('_') {
+         symbol.remove(0);
+     }
+     symbol
+ }
+ 
+ pub(crate) fn disassemble_myself() -> HashSet<Function> {
+     let me = env::current_exe().expect("failed to get current exe");
+ 
+     let disassembly =
+         if cfg!(target_arch = "x86_64") && cfg!(target_os = "windows") && cfg!(target_env = "msvc")
+         {
+             let mut cmd = cc::windows_registry::find("x86_64-pc-windows-msvc", "dumpbin.exe")
+                 .expect("failed to find `dumpbin` tool");
+             let output = cmd
+                 .arg("/DISASM")
+                 .arg(&me)
+                 .output()
+                 .expect("failed to execute dumpbin");
+             println!(
+                 "{}\n{}",
+                 output.status,
+                 String::from_utf8_lossy(&output.stderr)
+             );
+             assert!(output.status.success());
+             // Windows does not return valid UTF-8 output:
+             String::from_utf8_lossy(Vec::leak(output.stdout))
+         } else if cfg!(target_os = "windows") {
+             panic!("disassembly unimplemented")
+         } else if cfg!(target_os = "macos") {
+             let output = Command::new("otool")
+                 .arg("-vt")
+                 .arg(&me)
+                 .output()
+                 .expect("failed to execute otool");
+             println!(
+                 "{}\n{}",
+                 output.status,
+                 String::from_utf8_lossy(&output.stderr)
+             );
+             assert!(output.status.success());
+ 
+             String::from_utf8_lossy(Vec::leak(output.stdout))
+         } else {
+             let objdump = env::var("OBJDUMP").unwrap_or_else(|_| "objdump".to_string());
+             let output = Command::new(objdump.clone())
+                 .arg("--disassemble")
+                 .arg(&me)
+                 .output()
+                 .unwrap_or_else(|_| panic!("failed to execute objdump. OBJDUMP={}", objdump));
+             println!(
+                 "{}\n{}",
+                 output.status,
+                 String::from_utf8_lossy(&output.stderr)
+             );
+             assert!(output.status.success());
+ 
+             String::from_utf8_lossy(Vec::leak(output.stdout))
+         };
+ 
+     parse(&disassembly)
+ }
+ 
+ fn parse(output: &str) -> HashSet<Function> {
+     let mut lines = output.lines();
+ 
+     println!(
+         "First 100 lines of the disassembly input containing {} lines:",
+         lines.clone().count()
+     );
+     for line in output.lines().take(100) {
+         println!("{}", line);
+     }
+ 
+     let mut functions = HashSet::new();
+     let mut cached_header = None;
+     while let Some(header) = cached_header.take().or_else(|| lines.next()) {
+         if !header.ends_with(':') || !header.contains("stdarch_test_shim") {
+             continue;
+         }
+         eprintln!("header: {}", header);
+         let symbol = normalize(header);
+         eprintln!("normalized symbol: {}", symbol);
+         let mut instructions = Vec::new();
+         while let Some(instruction) = lines.next() {
+             if instruction.ends_with(':') {
+                 cached_header = Some(instruction);
+                 break;
+             }
+             if instruction.is_empty() {
+                 cached_header = None;
+                 break;
+             }
+             let parts = if cfg!(target_os = "macos") {
+                 // Each line of instructions should look like:
+                 //
+                 //      $addr    $instruction...
+                 instruction
+                     .split_whitespace()
+                     .skip(1)
+                     .map(std::string::ToString::to_string)
+                     .collect::<Vec<String>>()
+             } else if cfg!(target_env = "msvc") {
+                 // Each line looks like:
+                 //
+                 // >  $addr: ab cd ef     $instr..
+                 // >         00 12          # this line os optional
+                 if instruction.starts_with("       ") {
+                     continue;
+                 }
+                 instruction
+                     .split_whitespace()
+                     .skip(1)
+                     .skip_while(|s| s.len() == 2 && usize::from_str_radix(s, 16).is_ok())
+                     .map(std::string::ToString::to_string)
+                     .skip_while(|s| *s == "lock") // skip x86-specific prefix
+                     .collect::<Vec<String>>()
+             } else {
+                 // objdump
+                 // Each line of instructions should look like:
+                 //
+                 //      $rel_offset: ab cd ef 00    $instruction...
+                 let expected_len = if cfg!(target_arch = "arm") || cfg!(target_arch = "aarch64") {
+                     8
+                 } else {
+                     2
+                 };
+ 
+                 instruction
+                     .split_whitespace()
+                     .skip(1)
+                     .skip_while(|s| s.len() == expected_len && usize::from_str_radix(s, 16).is_ok())
+                     .skip_while(|s| *s == "lock") // skip x86-specific prefix
+                     .map(std::string::ToString::to_string)
+                     .collect::<Vec<String>>()
+             };
+             instructions.push(parts.join(" "));
+         }
+         let function = Function {
+             name: symbol,
+             instrs: instructions,
+         };
+         assert!(functions.insert(function));
+     }
+ 
+     eprintln!("all found functions dump:");
+     for k in &functions {
+         eprintln!("  f: {}", k.name);
+     }
+ 
+     functions
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,171 ----
+ //! Runtime support needed for testing the stdarch crate.
+ //!
+ //! This basically just disassembles the current executable and then parses the
+ //! output once globally and then provides the `assert` function which makes
+ //! assertions about the disassembly of a function.
+ #![allow(clippy::missing_docs_in_private_items, clippy::print_stdout)]
+ 
+ extern crate assert_instr_macro;
+ extern crate cc;
+ #[macro_use]
+ extern crate lazy_static;
+ extern crate rustc_demangle;
+ extern crate simd_test_macro;
+ #[macro_use]
+ extern crate cfg_if;
+ 
+ pub use assert_instr_macro::*;
+ pub use simd_test_macro::*;
+ use std::{cmp, collections::HashSet, env, hash, str, sync::atomic::AtomicPtr};
+ 
+ cfg_if! {
+     if #[cfg(target_arch = "wasm32")] {
+         pub mod wasm;
+         use wasm::disassemble_myself;
+     } else {
+         mod disassembly;
+         use disassembly::disassemble_myself;
+     }
+ }
+ 
+ lazy_static! {
+     static ref DISASSEMBLY: HashSet<Function> = disassemble_myself();
+ }
+ 
+ #[derive(Debug)]
+ struct Function {
+     name: String,
+     instrs: Vec<String>,
+ }
+ impl Function {
+     fn new(n: &str) -> Self {
+         Self {
+             name: n.to_string(),
+             instrs: Vec::new(),
+         }
+     }
+ }
+ 
+ impl cmp::PartialEq for Function {
+     fn eq(&self, other: &Self) -> bool {
+         self.name == other.name
+     }
+ }
+ impl cmp::Eq for Function {}
+ 
+ impl hash::Hash for Function {
+     fn hash<H: hash::Hasher>(&self, state: &mut H) {
+         self.name.hash(state)
+     }
+ }
+ 
+ /// Main entry point for this crate, called by the `#[assert_instr]` macro.
+ ///
+ /// This asserts that the function at `fnptr` contains the instruction
+ /// `expected` provided.
+ pub fn assert(_fnptr: usize, fnname: &str, expected: &str) {
+     //eprintln!("shim name: {}", fnname);
+     let function = &DISASSEMBLY
+         .get(&Function::new(fnname))
+         .unwrap_or_else(|| panic!("function \"{}\" not found in the disassembly", fnname));
+     //eprintln!("  function: {:?}", function);
+ 
+     let mut instrs = &function.instrs[..];
+     while instrs.last().map_or(false, |s| s == "nop") {
+         instrs = &instrs[..instrs.len() - 1];
+     }
+ 
+     // If the expected intrinsic is a nop it is compiled away so we
+     // can't check for it - aka the intrinsic is not generating any code
+     if expected == "nop" {
+         return;
+     }
+ 
+     // Look for `expected` as the first part of any instruction in this
+     // function, e.g., tzcntl in tzcntl %rax,%rax.
+     let found = instrs.iter().any(|s| s.starts_with(expected));
+ 
+     // Look for `call` instructions in the disassembly to detect whether
+     // inlining failed: all intrinsics are `#[inline(always)]`, so
+     // calling one intrinsic from another should not generate `call`
+     // instructions.
+     let inlining_failed = instrs.windows(2).any(|s| {
+         // On 32-bit x86 position independent code will call itself and be
+         // immediately followed by a `pop` to learn about the current address.
+         // Let's not take that into account when considering whether a function
+         // failed inlining something.
+         s[0].contains("call") && (!cfg!(target_arch = "x86") || s[1].contains("pop"))
+     });
+ 
+     let instruction_limit = std::env::var("STDARCH_ASSERT_INSTR_LIMIT")
+         .ok()
+         .map_or_else(
+             || match expected {
+                 // `cpuid` returns a pretty big aggregate structure, so exempt
+                 // it from the slightly more restrictive 22 instructions below.
+                 "cpuid" => 30,
+ 
+                 // Apparently, on Windows, LLVM generates a bunch of
+                 // saves/restores of xmm registers around these intstructions,
+                 // which exceeds the limit of 20 below. As it seems dictated by
+                 // Windows's ABI (I believe?), we probably can't do much
+                 // about it.
+                 "vzeroall" | "vzeroupper" if cfg!(windows) => 30,
+ 
+                 // Intrinsics using `cvtpi2ps` are typically "composites" and
+                 // in some cases exceed the limit.
+                 "cvtpi2ps" => 25,
+ 
+                 // core_arch/src/acle/simd32
+                 "usad8" => 27,
+                 "qadd8" | "qsub8" | "sadd8" | "sel" | "shadd8" | "shsub8" | "usub8" | "ssub8" => 29,
+ 
+                 // Original limit was 20 instructions, but ARM DSP Intrinsics
+                 // are exactly 20 instructions long. So, bump the limit to 22
+                 // instead of adding here a long list of exceptions.
+                 _ => 22,
+             },
+             |v| v.parse().unwrap(),
+         );
+     let probably_only_one_instruction = instrs.len() < instruction_limit;
+ 
+     if found && probably_only_one_instruction && !inlining_failed {
+         return;
+     }
+ 
+     // Help debug by printing out the found disassembly, and then panic as we
+     // didn't find the instruction.
+     println!("disassembly for {}: ", fnname,);
+     for (i, instr) in instrs.iter().enumerate() {
+         println!("\t{:2}: {}", i, instr);
+     }
+ 
+     if !found {
+         panic!(
+             "failed to find instruction `{}` in the disassembly",
+             expected
+         );
+     } else if !probably_only_one_instruction {
+         panic!(
+             "instruction found, but the disassembly contains too many \
+              instructions: #instructions = {} >= {} (limit)",
+             instrs.len(),
+             instruction_limit
+         );
+     } else if inlining_failed {
+         panic!(
+             "instruction found, but the disassembly contains `call` \
+              instructions, which hint that inlining failed"
+         );
+     }
+ }
+ 
+ pub fn assert_skip_test_ok(name: &str) {
+     if env::var("STDARCH_TEST_EVERYTHING").is_err() {
+         return;
+     }
+     panic!("skipped test `{}` when it shouldn't be skipped", name);
+ }
+ 
+ // See comment in `assert-instr-macro` crate for why this exists
+ pub static _DONT_DEDUP: AtomicPtr<u8> = AtomicPtr::new(b"".as_ptr() as *mut _);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,55 ----
+ //! Disassembly calling function for `wasm32` targets.
+ 
+ use crate::Function;
+ use std::collections::HashSet;
+ 
+ pub(crate) fn disassemble_myself() -> HashSet<Function> {
+     // Use `std::env::args` to find the path to our executable. Assume the
+     // environment is configured such that we can read that file. Read it and
+     // use the `wasmprinter` crate to transform the binary to text, then search
+     // the text for appropriately named functions.
+     let me = std::env::args()
+         .next()
+         .expect("failed to find current wasm file");
+     let output = wasmprinter::print_file(&me).unwrap();
+ 
+     let mut ret: HashSet<Function> = HashSet::new();
+     let mut lines = output.lines().map(|s| s.trim());
+     while let Some(line) = lines.next() {
+         // If this isn't a function, we don't care about it.
+         if !line.starts_with("(func ") {
+             continue;
+         }
+ 
+         let mut function = Function {
+             name: String::new(),
+             instrs: Vec::new(),
+         };
+ 
+         // Empty functions will end in `))` so there's nothing to do, otherwise
+         // we'll have a bunch of following lines which are instructions.
+         //
+         // Lines that have an imbalanced `)` mark the end of a function.
+         if !line.ends_with("))") {
+             while let Some(line) = lines.next() {
+                 function.instrs.push(line.to_string());
+                 if !line.starts_with("(") && line.ends_with(")") {
+                     break;
+                 }
+             }
+         }
+         // The second element here split on whitespace should be the name of
+         // the function, skipping the type/params/results
+         function.name = line.split_whitespace().nth(1).unwrap().to_string();
+         if function.name.starts_with("$") {
+             function.name = function.name[1..].to_string()
+         }
+ 
+         if !function.name.contains("stdarch_test_shim") {
+             continue;
+         }
+ 
+         assert!(ret.insert(function));
+     }
+     return ret;
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/.gitattributes gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/.gitattributes
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/.gitattributes	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/.gitattributes	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1 ----
+ *.xml binary
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,19 ----
+ [package]
+ name = "stdarch-verify"
+ version = "0.1.0"
+ authors = ["Alex Crichton <alex@alexcrichton.com>"]
+ edition = "2018"
+ 
+ [dependencies]
+ proc-macro2 = "1.0"
+ quote = "1.0"
+ syn = { version = "1.0", features = ["full"] }
+ 
+ [lib]
+ proc-macro = true
+ test = false
+ 
+ [dev-dependencies]
+ serde = { version = "1.0", features = ['derive'] }
+ serde-xml-rs = "0.3"
+ html5ever = "0.23.0"
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,93399 ----
+ 
+ 
+ <!DOCTYPE html>
+ <html class="page no-js" lang="en">
+ <head>
+     <script>
+         if ((window.location.href.indexOf('<') || window.location.href.indexOf('>')) > -1) {
+             window.location.href = window.location.href.replace(/<.*>/g, '');            
+         }
+     </script>
+ 
+     <title>Technologies | NEON Intrinsics Reference – Arm Developer</title>
+     
+ <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge">
+ <meta content="en" http-equiv="content-language">
+ <meta name="viewport" content="width=device-width, initial-scale=1.0">
+ <meta name="author" content="Arm Ltd.">
+ <meta name="description" content="All the NEON intrinsics reference in an interactive page.">
+ <meta name="keywords" content="">
+ <meta content="Copyright &#169; 1995-2018 Arm Limited (or its affiliates). All rights reserved." name="copyright">
+ <meta name="apple-mobile-web-app-capable" content="yes">
+ <meta name="msapplication-config" content="https://developer.arm.com:443/shared/common/img/favicon/browserconfig.xml">
+ <meta name="msapplication-TileColor" content="#2b5797">
+ <meta name="msapplication-TileImage" content="https://developer.arm.com:443/shared/common/img/favicon/mstile-144x144.png">
+ <meta name="theme-color" content="#ffffff">
+ <meta name="server" content="ARMGPCD2" />
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+             <h2 class="c-panel__subtitle">NEON Intrinsics</h2>
+             <p>Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.</p>
+         </section>
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+ <section class="intrinsic-accordion">
+ <div class="intrinsic"><input id="vadd_s8" type="checkbox"><label for="vadd_s8"><div>int8x8_t <b><b>vadd_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_s8" type="checkbox"><label for="vaddq_s8"><div>int8x16_t <b><b>vaddq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_s16" type="checkbox"><label for="vadd_s16"><div>int16x4_t <b><b>vadd_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_s16" type="checkbox"><label for="vaddq_s16"><div>int16x8_t <b><b>vaddq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_s32" type="checkbox"><label for="vadd_s32"><div>int32x2_t <b><b>vadd_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_s32" type="checkbox"><label for="vaddq_s32"><div>int32x4_t <b><b>vaddq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_s64" type="checkbox"><label for="vadd_s64"><div>int64x1_t <b><b>vadd_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_s64" type="checkbox"><label for="vaddq_s64"><div>int64x2_t <b><b>vaddq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_u8" type="checkbox"><label for="vadd_u8"><div>uint8x8_t <b><b>vadd_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_u8" type="checkbox"><label for="vaddq_u8"><div>uint8x16_t <b><b>vaddq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_u16" type="checkbox"><label for="vadd_u16"><div>uint16x4_t <b><b>vadd_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_u16" type="checkbox"><label for="vaddq_u16"><div>uint16x8_t <b><b>vaddq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_u32" type="checkbox"><label for="vadd_u32"><div>uint32x2_t <b><b>vadd_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_u32" type="checkbox"><label for="vaddq_u32"><div>uint32x4_t <b><b>vaddq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_u64" type="checkbox"><label for="vadd_u64"><div>uint64x1_t <b><b>vadd_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_u64" type="checkbox"><label for="vaddq_u64"><div>uint64x2_t <b><b>vaddq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_f32" type="checkbox"><label for="vadd_f32"><div>float32x2_t <b><b>vadd_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&amp;FP registers, writes the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fadd-vector-floating-point-add-vector">FADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_f32" type="checkbox"><label for="vaddq_f32"><div>float32x4_t <b><b>vaddq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&amp;FP registers, writes the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fadd-vector-floating-point-add-vector">FADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vadd_f64" type="checkbox"><label for="vadd_f64"><div>float64x1_t <b><b>vadd_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&amp;FP registers, writes the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fadd-vector-floating-point-add-vector">FADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddq_f64" type="checkbox"><label for="vaddq_f64"><div>float64x2_t <b><b>vaddq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&amp;FP registers, writes the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fadd-vector-floating-point-add-vector">FADD</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddd_s64" type="checkbox"><label for="vaddd_s64"><div>int64_t <b><b>vaddd_s64</b></b> (int64_t a, int64_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddd_u64" type="checkbox"><label for="vaddd_u64"><div>uint64_t <b><b>vaddd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add (vector). This instruction adds corresponding elements in the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/add-vector-add-vector">ADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_s8" type="checkbox"><label for="vaddl_s8"><div>int16x8_t <b><b>vaddl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddl-saddl2-signed-add-long-vector">SADDL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_s16" type="checkbox"><label for="vaddl_s16"><div>int32x4_t <b><b>vaddl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddl-saddl2-signed-add-long-vector">SADDL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_s32" type="checkbox"><label for="vaddl_s32"><div>int64x2_t <b><b>vaddl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddl-saddl2-signed-add-long-vector">SADDL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_u8" type="checkbox"><label for="vaddl_u8"><div>uint16x8_t <b><b>vaddl_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddl-uaddl2-unsigned-add-long-vector">UADDL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_u16" type="checkbox"><label for="vaddl_u16"><div>uint32x4_t <b><b>vaddl_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddl-uaddl2-unsigned-add-long-vector">UADDL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_u32" type="checkbox"><label for="vaddl_u32"><div>uint64x2_t <b><b>vaddl_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddl-uaddl2-unsigned-add-long-vector">UADDL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_high_s8" type="checkbox"><label for="vaddl_high_s8"><div>int16x8_t <b><b>vaddl_high_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddl-saddl2-signed-add-long-vector">SADDL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_high_s16" type="checkbox"><label for="vaddl_high_s16"><div>int32x4_t <b><b>vaddl_high_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddl-saddl2-signed-add-long-vector">SADDL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_high_s32" type="checkbox"><label for="vaddl_high_s32"><div>int64x2_t <b><b>vaddl_high_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddl-saddl2-signed-add-long-vector">SADDL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_high_u8" type="checkbox"><label for="vaddl_high_u8"><div>uint16x8_t <b><b>vaddl_high_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddl-uaddl2-unsigned-add-long-vector">UADDL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_high_u16" type="checkbox"><label for="vaddl_high_u16"><div>uint32x4_t <b><b>vaddl_high_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddl-uaddl2-unsigned-add-long-vector">UADDL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddl_high_u32" type="checkbox"><label for="vaddl_high_u32"><div>uint64x2_t <b><b>vaddl_high_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&amp;FP register to the corresponding vector element of the second source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddl-uaddl2-unsigned-add-long-vector">UADDL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_s8" type="checkbox"><label for="vaddw_s8"><div>int16x8_t <b><b>vaddw_s8</b></b> (int16x8_t a, int8x8_t b)<span class="right">Signed add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Wide. This instruction adds vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddw-saddw2-signed-add-wide">SADDW</a> Vd.8H,Vn.8H,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_s16" type="checkbox"><label for="vaddw_s16"><div>int32x4_t <b><b>vaddw_s16</b></b> (int32x4_t a, int16x4_t b)<span class="right">Signed add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Wide. This instruction adds vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddw-saddw2-signed-add-wide">SADDW</a> Vd.4S,Vn.4S,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_s32" type="checkbox"><label for="vaddw_s32"><div>int64x2_t <b><b>vaddw_s32</b></b> (int64x2_t a, int32x2_t b)<span class="right">Signed add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Wide. This instruction adds vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddw-saddw2-signed-add-wide">SADDW</a> Vd.2D,Vn.2D,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_u8" type="checkbox"><label for="vaddw_u8"><div>uint16x8_t <b><b>vaddw_u8</b></b> (uint16x8_t a, uint8x8_t b)<span class="right">Unsigned add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddw-uaddw2-unsigned-add-wide">UADDW</a> Vd.8H,Vn.8H,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_u16" type="checkbox"><label for="vaddw_u16"><div>uint32x4_t <b><b>vaddw_u16</b></b> (uint32x4_t a, uint16x4_t b)<span class="right">Unsigned add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddw-uaddw2-unsigned-add-wide">UADDW</a> Vd.4S,Vn.4S,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_u32" type="checkbox"><label for="vaddw_u32"><div>uint64x2_t <b><b>vaddw_u32</b></b> (uint64x2_t a, uint32x2_t b)<span class="right">Unsigned add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddw-uaddw2-unsigned-add-wide">UADDW</a> Vd.2D,Vn.2D,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_high_s8" type="checkbox"><label for="vaddw_high_s8"><div>int16x8_t <b><b>vaddw_high_s8</b></b> (int16x8_t a, int8x16_t b)<span class="right">Signed add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Wide. This instruction adds vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddw-saddw2-signed-add-wide">SADDW2</a> Vd.8H,Vn.8H,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_high_s16" type="checkbox"><label for="vaddw_high_s16"><div>int32x4_t <b><b>vaddw_high_s16</b></b> (int32x4_t a, int16x8_t b)<span class="right">Signed add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Wide. This instruction adds vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddw-saddw2-signed-add-wide">SADDW2</a> Vd.4S,Vn.4S,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_high_s32" type="checkbox"><label for="vaddw_high_s32"><div>int64x2_t <b><b>vaddw_high_s32</b></b> (int64x2_t a, int32x4_t b)<span class="right">Signed add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Wide. This instruction adds vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddw-saddw2-signed-add-wide">SADDW2</a> Vd.2D,Vn.2D,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_high_u8" type="checkbox"><label for="vaddw_high_u8"><div>uint16x8_t <b><b>vaddw_high_u8</b></b> (uint16x8_t a, uint8x16_t b)<span class="right">Unsigned add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddw-uaddw2-unsigned-add-wide">UADDW2</a> Vd.8H,Vn.8H,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_high_u16" type="checkbox"><label for="vaddw_high_u16"><div>uint32x4_t <b><b>vaddw_high_u16</b></b> (uint32x4_t a, uint16x8_t b)<span class="right">Unsigned add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddw-uaddw2-unsigned-add-wide">UADDW2</a> Vd.4S,Vn.4S,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddw_high_u32" type="checkbox"><label for="vaddw_high_u32"><div>uint64x2_t <b><b>vaddw_high_u32</b></b> (uint64x2_t a, uint32x4_t b)<span class="right">Unsigned add wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&amp;FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddw-uaddw2-unsigned-add-wide">UADDW2</a> Vd.2D,Vn.2D,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vhadd_s8" type="checkbox"><label for="vhadd_s8"><div>int8x8_t <b><b>vhadd_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shadd-signed-halving-add">SHADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhaddq_s8" type="checkbox"><label for="vhaddq_s8"><div>int8x16_t <b><b>vhaddq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shadd-signed-halving-add">SHADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhadd_s16" type="checkbox"><label for="vhadd_s16"><div>int16x4_t <b><b>vhadd_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shadd-signed-halving-add">SHADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhaddq_s16" type="checkbox"><label for="vhaddq_s16"><div>int16x8_t <b><b>vhaddq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shadd-signed-halving-add">SHADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhadd_s32" type="checkbox"><label for="vhadd_s32"><div>int32x2_t <b><b>vhadd_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shadd-signed-halving-add">SHADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhaddq_s32" type="checkbox"><label for="vhaddq_s32"><div>int32x4_t <b><b>vhaddq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shadd-signed-halving-add">SHADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhadd_u8" type="checkbox"><label for="vhadd_u8"><div>uint8x8_t <b><b>vhadd_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhadd-unsigned-halving-add">UHADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhaddq_u8" type="checkbox"><label for="vhaddq_u8"><div>uint8x16_t <b><b>vhaddq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhadd-unsigned-halving-add">UHADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhadd_u16" type="checkbox"><label for="vhadd_u16"><div>uint16x4_t <b><b>vhadd_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhadd-unsigned-halving-add">UHADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhaddq_u16" type="checkbox"><label for="vhaddq_u16"><div>uint16x8_t <b><b>vhaddq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhadd-unsigned-halving-add">UHADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhadd_u32" type="checkbox"><label for="vhadd_u32"><div>uint32x2_t <b><b>vhadd_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhadd-unsigned-halving-add">UHADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhaddq_u32" type="checkbox"><label for="vhaddq_u32"><div>uint32x4_t <b><b>vhaddq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhadd-unsigned-halving-add">UHADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhadd_s8" type="checkbox"><label for="vrhadd_s8"><div>int8x8_t <b><b>vrhadd_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srhadd-signed-rounding-halving-add">SRHADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhaddq_s8" type="checkbox"><label for="vrhaddq_s8"><div>int8x16_t <b><b>vrhaddq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srhadd-signed-rounding-halving-add">SRHADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhadd_s16" type="checkbox"><label for="vrhadd_s16"><div>int16x4_t <b><b>vrhadd_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srhadd-signed-rounding-halving-add">SRHADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhaddq_s16" type="checkbox"><label for="vrhaddq_s16"><div>int16x8_t <b><b>vrhaddq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srhadd-signed-rounding-halving-add">SRHADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhadd_s32" type="checkbox"><label for="vrhadd_s32"><div>int32x2_t <b><b>vrhadd_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srhadd-signed-rounding-halving-add">SRHADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhaddq_s32" type="checkbox"><label for="vrhaddq_s32"><div>int32x4_t <b><b>vrhaddq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srhadd-signed-rounding-halving-add">SRHADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhadd_u8" type="checkbox"><label for="vrhadd_u8"><div>uint8x8_t <b><b>vrhadd_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urhadd-unsigned-rounding-halving-add">URHADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhaddq_u8" type="checkbox"><label for="vrhaddq_u8"><div>uint8x16_t <b><b>vrhaddq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urhadd-unsigned-rounding-halving-add">URHADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhadd_u16" type="checkbox"><label for="vrhadd_u16"><div>uint16x4_t <b><b>vrhadd_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urhadd-unsigned-rounding-halving-add">URHADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhaddq_u16" type="checkbox"><label for="vrhaddq_u16"><div>uint16x8_t <b><b>vrhaddq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urhadd-unsigned-rounding-halving-add">URHADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhadd_u32" type="checkbox"><label for="vrhadd_u32"><div>uint32x2_t <b><b>vrhadd_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urhadd-unsigned-rounding-halving-add">URHADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrhaddq_u32" type="checkbox"><label for="vrhaddq_u32"><div>uint32x4_t <b><b>vrhaddq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned rounding halving add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&amp;FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urhadd-unsigned-rounding-halving-add">URHADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1+element2+1)&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_s8" type="checkbox"><label for="vqadd_s8"><div>int8x8_t <b><b>vqadd_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_s8" type="checkbox"><label for="vqaddq_s8"><div>int8x16_t <b><b>vqaddq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_s16" type="checkbox"><label for="vqadd_s16"><div>int16x4_t <b><b>vqadd_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_s16" type="checkbox"><label for="vqaddq_s16"><div>int16x8_t <b><b>vqaddq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_s32" type="checkbox"><label for="vqadd_s32"><div>int32x2_t <b><b>vqadd_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_s32" type="checkbox"><label for="vqaddq_s32"><div>int32x4_t <b><b>vqaddq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_s64" type="checkbox"><label for="vqadd_s64"><div>int64x1_t <b><b>vqadd_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_s64" type="checkbox"><label for="vqaddq_s64"><div>int64x2_t <b><b>vqaddq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_u8" type="checkbox"><label for="vqadd_u8"><div>uint8x8_t <b><b>vqadd_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_u8" type="checkbox"><label for="vqaddq_u8"><div>uint8x16_t <b><b>vqaddq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_u16" type="checkbox"><label for="vqadd_u16"><div>uint16x4_t <b><b>vqadd_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_u16" type="checkbox"><label for="vqaddq_u16"><div>uint16x8_t <b><b>vqaddq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_u32" type="checkbox"><label for="vqadd_u32"><div>uint32x2_t <b><b>vqadd_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_u32" type="checkbox"><label for="vqaddq_u32"><div>uint32x4_t <b><b>vqaddq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqadd_u64" type="checkbox"><label for="vqadd_u64"><div>uint64x1_t <b><b>vqadd_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddq_u64" type="checkbox"><label for="vqaddq_u64"><div>uint64x2_t <b><b>vqaddq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqaddb_s8" type="checkbox"><label for="vqaddb_s8"><div>int8_t <b><b>vqaddb_s8</b></b> (int8_t a, int8_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqaddh_s16" type="checkbox"><label for="vqaddh_s16"><div>int16_t <b><b>vqaddh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqadds_s32" type="checkbox"><label for="vqadds_s32"><div>int32_t <b><b>vqadds_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqaddd_s64" type="checkbox"><label for="vqaddd_s64"><div>int64_t <b><b>vqaddd_s64</b></b> (int64_t a, int64_t b)<span class="right">Signed saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqadd-signed-saturating-add">SQADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqaddb_u8" type="checkbox"><label for="vqaddb_u8"><div>uint8_t <b><b>vqaddb_u8</b></b> (uint8_t a, uint8_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqaddh_u16" type="checkbox"><label for="vqaddh_u16"><div>uint16_t <b><b>vqaddh_u16</b></b> (uint16_t a, uint16_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqadds_u32" type="checkbox"><label for="vqadds_u32"><div>uint32_t <b><b>vqadds_u32</b></b> (uint32_t a, uint32_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqaddd_u64" type="checkbox"><label for="vqaddd_u64"><div>uint64_t <b><b>vqaddd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Unsigned saturating add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&amp;FP registers, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqadd-unsigned-saturating-add">UQADD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     sum = element1 + element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqadd_s8" type="checkbox"><label for="vuqadd_s8"><div>int8x8_t <b><b>vuqadd_s8</b></b> (int8x8_t a, uint8x8_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddq_s8" type="checkbox"><label for="vuqaddq_s8"><div>int8x16_t <b><b>vuqaddq_s8</b></b> (int8x16_t a, uint8x16_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqadd_s16" type="checkbox"><label for="vuqadd_s16"><div>int16x4_t <b><b>vuqadd_s16</b></b> (int16x4_t a, uint16x4_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddq_s16" type="checkbox"><label for="vuqaddq_s16"><div>int16x8_t <b><b>vuqaddq_s16</b></b> (int16x8_t a, uint16x8_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqadd_s32" type="checkbox"><label for="vuqadd_s32"><div>int32x2_t <b><b>vuqadd_s32</b></b> (int32x2_t a, uint32x2_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddq_s32" type="checkbox"><label for="vuqaddq_s32"><div>int32x4_t <b><b>vuqaddq_s32</b></b> (int32x4_t a, uint32x4_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqadd_s64" type="checkbox"><label for="vuqadd_s64"><div>int64x1_t <b><b>vuqadd_s64</b></b> (int64x1_t a, uint64x1_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddq_s64" type="checkbox"><label for="vuqaddq_s64"><div>int64x2_t <b><b>vuqaddq_s64</b></b> (int64x2_t a, uint64x2_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddb_s8" type="checkbox"><label for="vuqaddb_s8"><div>int8_t <b><b>vuqaddb_s8</b></b> (int8_t a, uint8_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Bd,Bn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bd <br />
+ b &rarr; Bn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddh_s16" type="checkbox"><label for="vuqaddh_s16"><div>int16_t <b><b>vuqaddh_s16</b></b> (int16_t a, uint16_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Hd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hd <br />
+ b &rarr; Hn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqadds_s32" type="checkbox"><label for="vuqadds_s32"><div>int32_t <b><b>vuqadds_s32</b></b> (int32_t a, uint32_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuqaddd_s64" type="checkbox"><label for="vuqaddd_s64"><div>int64_t <b><b>vuqaddd_s64</b></b> (int64_t a, uint64_t b)<span class="right">Signed saturating accumulate of unsigned value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&amp;FP register to corresponding signed integer values of the vector elements in the destination SIMD&amp;FP register, and writes the resulting signed integer values to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/suqadd-signed-saturating-accumulate-of-unsigned-value">SUQADD</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqadd_u8" type="checkbox"><label for="vsqadd_u8"><div>uint8x8_t <b><b>vsqadd_u8</b></b> (uint8x8_t a, int8x8_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddq_u8" type="checkbox"><label for="vsqaddq_u8"><div>uint8x16_t <b><b>vsqaddq_u8</b></b> (uint8x16_t a, int8x16_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqadd_u16" type="checkbox"><label for="vsqadd_u16"><div>uint16x4_t <b><b>vsqadd_u16</b></b> (uint16x4_t a, int16x4_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddq_u16" type="checkbox"><label for="vsqaddq_u16"><div>uint16x8_t <b><b>vsqaddq_u16</b></b> (uint16x8_t a, int16x8_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqadd_u32" type="checkbox"><label for="vsqadd_u32"><div>uint32x2_t <b><b>vsqadd_u32</b></b> (uint32x2_t a, int32x2_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddq_u32" type="checkbox"><label for="vsqaddq_u32"><div>uint32x4_t <b><b>vsqaddq_u32</b></b> (uint32x4_t a, int32x4_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqadd_u64" type="checkbox"><label for="vsqadd_u64"><div>uint64x1_t <b><b>vsqadd_u64</b></b> (uint64x1_t a, int64x1_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddq_u64" type="checkbox"><label for="vsqaddq_u64"><div>uint64x2_t <b><b>vsqaddq_u64</b></b> (uint64x2_t a, int64x2_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddb_u8" type="checkbox"><label for="vsqaddb_u8"><div>uint8_t <b><b>vsqaddb_u8</b></b> (uint8_t a, int8_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Bd,Bn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bd <br />
+ b &rarr; Bn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddh_u16" type="checkbox"><label for="vsqaddh_u16"><div>uint16_t <b><b>vsqaddh_u16</b></b> (uint16_t a, int16_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Hd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hd <br />
+ b &rarr; Hn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqadds_u32" type="checkbox"><label for="vsqadds_u32"><div>uint32_t <b><b>vsqadds_u32</b></b> (uint32_t a, int32_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqaddd_u64" type="checkbox"><label for="vsqaddd_u64"><div>uint64_t <b><b>vsqaddd_u64</b></b> (uint64_t a, int64_t b)<span class="right">Unsigned saturating accumulate of signed value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&amp;FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&amp;FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usqadd-unsigned-saturating-accumulate-of-signed-value">USQADD</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ integer op1;
+ integer op2;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], !unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(op1 + op2, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_s16" type="checkbox"><label for="vaddhn_s16"><div>int8x8_t <b><b>vaddhn_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_s32" type="checkbox"><label for="vaddhn_s32"><div>int16x4_t <b><b>vaddhn_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_s64" type="checkbox"><label for="vaddhn_s64"><div>int32x2_t <b><b>vaddhn_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_u16" type="checkbox"><label for="vaddhn_u16"><div>uint8x8_t <b><b>vaddhn_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_u32" type="checkbox"><label for="vaddhn_u32"><div>uint16x4_t <b><b>vaddhn_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_u64" type="checkbox"><label for="vaddhn_u64"><div>uint32x2_t <b><b>vaddhn_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_high_s16" type="checkbox"><label for="vaddhn_high_s16"><div>int8x16_t <b><b>vaddhn_high_s16</b></b> (int8x8_t r, int16x8_t a, int16x8_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_high_s32" type="checkbox"><label for="vaddhn_high_s32"><div>int16x8_t <b><b>vaddhn_high_s32</b></b> (int16x4_t r, int32x4_t a, int32x4_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_high_s64" type="checkbox"><label for="vaddhn_high_s64"><div>int32x4_t <b><b>vaddhn_high_s64</b></b> (int32x2_t r, int64x2_t a, int64x2_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_high_u16" type="checkbox"><label for="vaddhn_high_u16"><div>uint8x16_t <b><b>vaddhn_high_u16</b></b> (uint8x8_t r, uint16x8_t a, uint16x8_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_high_u32" type="checkbox"><label for="vaddhn_high_u32"><div>uint16x8_t <b><b>vaddhn_high_u32</b></b> (uint16x4_t r, uint32x4_t a, uint32x4_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddhn_high_u64" type="checkbox"><label for="vaddhn_high_u64"><div>uint32x4_t <b><b>vaddhn_high_u64</b></b> (uint32x2_t r, uint64x2_t a, uint64x2_t b)<span class="right">Add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addhn-addhn2-add-returning-high-narrow">ADDHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_s16" type="checkbox"><label for="vraddhn_s16"><div>int8x8_t <b><b>vraddhn_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_s32" type="checkbox"><label for="vraddhn_s32"><div>int16x4_t <b><b>vraddhn_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_s64" type="checkbox"><label for="vraddhn_s64"><div>int32x2_t <b><b>vraddhn_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_u16" type="checkbox"><label for="vraddhn_u16"><div>uint8x8_t <b><b>vraddhn_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_u32" type="checkbox"><label for="vraddhn_u32"><div>uint16x4_t <b><b>vraddhn_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_u64" type="checkbox"><label for="vraddhn_u64"><div>uint32x2_t <b><b>vraddhn_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_high_s16" type="checkbox"><label for="vraddhn_high_s16"><div>int8x16_t <b><b>vraddhn_high_s16</b></b> (int8x8_t r, int16x8_t a, int16x8_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_high_s32" type="checkbox"><label for="vraddhn_high_s32"><div>int16x8_t <b><b>vraddhn_high_s32</b></b> (int16x4_t r, int32x4_t a, int32x4_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_high_s64" type="checkbox"><label for="vraddhn_high_s64"><div>int32x4_t <b><b>vraddhn_high_s64</b></b> (int32x2_t r, int64x2_t a, int64x2_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_high_u16" type="checkbox"><label for="vraddhn_high_u16"><div>uint8x16_t <b><b>vraddhn_high_u16</b></b> (uint8x8_t r, uint16x8_t a, uint16x8_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_high_u32" type="checkbox"><label for="vraddhn_high_u32"><div>uint16x8_t <b><b>vraddhn_high_u32</b></b> (uint16x4_t r, uint32x4_t a, uint32x4_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vraddhn_high_u64" type="checkbox"><label for="vraddhn_high_u64"><div>uint32x4_t <b><b>vraddhn_high_u64</b></b> (uint32x2_t r, uint64x2_t a, uint64x2_t b)<span class="right">Rounding add returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&amp;FP register to the corresponding vector element in the second source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/raddhn-raddhn2-rounding-add-returning-high-narrow">RADDHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_s8" type="checkbox"><label for="vmul_s8"><div>int8x8_t <b><b>vmul_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_s8" type="checkbox"><label for="vmulq_s8"><div>int8x16_t <b><b>vmulq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_s16" type="checkbox"><label for="vmul_s16"><div>int16x4_t <b><b>vmul_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_s16" type="checkbox"><label for="vmulq_s16"><div>int16x8_t <b><b>vmulq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_s32" type="checkbox"><label for="vmul_s32"><div>int32x2_t <b><b>vmul_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_s32" type="checkbox"><label for="vmulq_s32"><div>int32x4_t <b><b>vmulq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_u8" type="checkbox"><label for="vmul_u8"><div>uint8x8_t <b><b>vmul_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_u8" type="checkbox"><label for="vmulq_u8"><div>uint8x16_t <b><b>vmulq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_u16" type="checkbox"><label for="vmul_u16"><div>uint16x4_t <b><b>vmul_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_u16" type="checkbox"><label for="vmulq_u16"><div>uint16x8_t <b><b>vmulq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_u32" type="checkbox"><label for="vmul_u32"><div>uint32x2_t <b><b>vmul_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_u32" type="checkbox"><label for="vmulq_u32"><div>uint32x4_t <b><b>vmulq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_f32" type="checkbox"><label for="vmul_f32"><div>float32x2_t <b><b>vmul_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_f32" type="checkbox"><label for="vmulq_f32"><div>float32x4_t <b><b>vmulq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_p8" type="checkbox"><label for="vmul_p8"><div>poly8x8_t <b><b>vmul_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Polynomial multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/pmul-polynomial-multiply">PMUL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_p8" type="checkbox"><label for="vmulq_p8"><div>poly8x16_t <b><b>vmulq_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Polynomial multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/pmul-polynomial-multiply">PMUL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_f64" type="checkbox"><label for="vmul_f64"><div>float64x1_t <b><b>vmul_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_f64" type="checkbox"><label for="vmulq_f64"><div>float64x2_t <b><b>vmulq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulx_f32" type="checkbox"><label for="vmulx_f32"><div>float32x2_t <b><b>vmulx_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxq_f32" type="checkbox"><label for="vmulxq_f32"><div>float32x4_t <b><b>vmulxq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulx_f64" type="checkbox"><label for="vmulx_f64"><div>float64x1_t <b><b>vmulx_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxq_f64" type="checkbox"><label for="vmulxq_f64"><div>float64x2_t <b><b>vmulxq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxs_f32" type="checkbox"><label for="vmulxs_f32"><div>float32_t <b><b>vmulxs_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxd_f64" type="checkbox"><label for="vmulxd_f64"><div>float64_t <b><b>vmulxd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulx_lane_f32" type="checkbox"><label for="vmulx_lane_f32"><div>float32x2_t <b><b>vmulx_lane_f32</b></b> (float32x2_t a, float32x2_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxq_lane_f32" type="checkbox"><label for="vmulxq_lane_f32"><div>float32x4_t <b><b>vmulxq_lane_f32</b></b> (float32x4_t a, float32x2_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulx_lane_f64" type="checkbox"><label for="vmulx_lane_f64"><div>float64x1_t <b><b>vmulx_lane_f64</b></b> (float64x1_t a, float64x1_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxq_lane_f64" type="checkbox"><label for="vmulxq_lane_f64"><div>float64x2_t <b><b>vmulxq_lane_f64</b></b> (float64x2_t a, float64x1_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxs_lane_f32" type="checkbox"><label for="vmulxs_lane_f32"><div>float32_t <b><b>vmulxs_lane_f32</b></b> (float32_t a, float32x2_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxd_lane_f64" type="checkbox"><label for="vmulxd_lane_f64"><div>float64_t <b><b>vmulxd_lane_f64</b></b> (float64_t a, float64x1_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulx_laneq_f32" type="checkbox"><label for="vmulx_laneq_f32"><div>float32x2_t <b><b>vmulx_laneq_f32</b></b> (float32x2_t a, float32x4_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxq_laneq_f32" type="checkbox"><label for="vmulxq_laneq_f32"><div>float32x4_t <b><b>vmulxq_laneq_f32</b></b> (float32x4_t a, float32x4_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulx_laneq_f64" type="checkbox"><label for="vmulx_laneq_f64"><div>float64x1_t <b><b>vmulx_laneq_f64</b></b> (float64x1_t a, float64x2_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxq_laneq_f64" type="checkbox"><label for="vmulxq_laneq_f64"><div>float64x2_t <b><b>vmulxq_laneq_f64</b></b> (float64x2_t a, float64x2_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxs_laneq_f32" type="checkbox"><label for="vmulxs_laneq_f32"><div>float32_t <b><b>vmulxs_laneq_f32</b></b> (float32_t a, float32x4_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulxd_laneq_f64" type="checkbox"><label for="vmulxd_laneq_f64"><div>float64_t <b><b>vmulxd_laneq_f64</b></b> (float64_t a, float64x2_t v, const int lane)<span class="right">Floating-point multiply extended (by element)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&amp;FP register by the specified floating-point value in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmulx-by-element-floating-point-multiply-extended-by-element">FMULX</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(idxdsize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     if mulx_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulX.3" title="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdiv_f32" type="checkbox"><label for="vdiv_f32"><div>float32x2_t <b><b>vdiv_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point divide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&amp;FP register, by the floating-point values in the corresponding elements in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fdiv-vector-floating-point-divide-vector">FDIV</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPDiv.3" title="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdivq_f32" type="checkbox"><label for="vdivq_f32"><div>float32x4_t <b><b>vdivq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point divide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&amp;FP register, by the floating-point values in the corresponding elements in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fdiv-vector-floating-point-divide-vector">FDIV</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPDiv.3" title="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdiv_f64" type="checkbox"><label for="vdiv_f64"><div>float64x1_t <b><b>vdiv_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point divide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&amp;FP register, by the floating-point values in the corresponding elements in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fdiv-vector-floating-point-divide-vector">FDIV</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPDiv.3" title="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdivq_f64" type="checkbox"><label for="vdivq_f64"><div>float64x2_t <b><b>vdivq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point divide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&amp;FP register, by the floating-point values in the corresponding elements in the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fdiv-vector-floating-point-divide-vector">FDIV</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPDiv.3" title="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_s8" type="checkbox"><label for="vmla_s8"><div>int8x8_t <b><b>vmla_s8</b></b> (int8x8_t a, int8x8_t b, int8x8_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_s8" type="checkbox"><label for="vmlaq_s8"><div>int8x16_t <b><b>vmlaq_s8</b></b> (int8x16_t a, int8x16_t b, int8x16_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_s16" type="checkbox"><label for="vmla_s16"><div>int16x4_t <b><b>vmla_s16</b></b> (int16x4_t a, int16x4_t b, int16x4_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_s16" type="checkbox"><label for="vmlaq_s16"><div>int16x8_t <b><b>vmlaq_s16</b></b> (int16x8_t a, int16x8_t b, int16x8_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_s32" type="checkbox"><label for="vmla_s32"><div>int32x2_t <b><b>vmla_s32</b></b> (int32x2_t a, int32x2_t b, int32x2_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_s32" type="checkbox"><label for="vmlaq_s32"><div>int32x4_t <b><b>vmlaq_s32</b></b> (int32x4_t a, int32x4_t b, int32x4_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_u8" type="checkbox"><label for="vmla_u8"><div>uint8x8_t <b><b>vmla_u8</b></b> (uint8x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_u8" type="checkbox"><label for="vmlaq_u8"><div>uint8x16_t <b><b>vmlaq_u8</b></b> (uint8x16_t a, uint8x16_t b, uint8x16_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_u16" type="checkbox"><label for="vmla_u16"><div>uint16x4_t <b><b>vmla_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_u16" type="checkbox"><label for="vmlaq_u16"><div>uint16x8_t <b><b>vmlaq_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x8_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_u32" type="checkbox"><label for="vmla_u32"><div>uint32x2_t <b><b>vmla_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_u32" type="checkbox"><label for="vmlaq_u32"><div>uint32x4_t <b><b>vmlaq_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x4_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_f32" type="checkbox"><label for="vmla_f32"><div>float32x2_t <b><b>vmla_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t c)<span class="right">Floating-point multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_f32" type="checkbox"><label for="vmlaq_f32"><div>float32x4_t <b><b>vmlaq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t c)<span class="right">Floating-point multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_f64" type="checkbox"><label for="vmla_f64"><div>float64x1_t <b><b>vmla_f64</b></b> (float64x1_t a, float64x1_t b, float64x1_t c)<span class="right">Floating-point multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_f64" type="checkbox"><label for="vmlaq_f64"><div>float64x2_t <b><b>vmlaq_f64</b></b> (float64x2_t a, float64x2_t b, float64x2_t c)<span class="right">Floating-point multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_s8" type="checkbox"><label for="vmlal_s8"><div>int16x8_t <b><b>vmlal_s8</b></b> (int16x8_t a, int8x8_t b, int8x8_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_s16" type="checkbox"><label for="vmlal_s16"><div>int32x4_t <b><b>vmlal_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_s32" type="checkbox"><label for="vmlal_s32"><div>int64x2_t <b><b>vmlal_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_u8" type="checkbox"><label for="vmlal_u8"><div>uint16x8_t <b><b>vmlal_u8</b></b> (uint16x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_u16" type="checkbox"><label for="vmlal_u16"><div>uint32x4_t <b><b>vmlal_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_u32" type="checkbox"><label for="vmlal_u32"><div>uint64x2_t <b><b>vmlal_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_s8" type="checkbox"><label for="vmlal_high_s8"><div>int16x8_t <b><b>vmlal_high_s8</b></b> (int16x8_t a, int8x16_t b, int8x16_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_s16" type="checkbox"><label for="vmlal_high_s16"><div>int32x4_t <b><b>vmlal_high_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_s32" type="checkbox"><label for="vmlal_high_s32"><div>int64x2_t <b><b>vmlal_high_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_u8" type="checkbox"><label for="vmlal_high_u8"><div>uint16x8_t <b><b>vmlal_high_u8</b></b> (uint16x8_t a, uint8x16_t b, uint8x16_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_u16" type="checkbox"><label for="vmlal_high_u16"><div>uint32x4_t <b><b>vmlal_high_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x8_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_u32" type="checkbox"><label for="vmlal_high_u32"><div>uint64x2_t <b><b>vmlal_high_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x4_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_s8" type="checkbox"><label for="vmls_s8"><div>int8x8_t <b><b>vmls_s8</b></b> (int8x8_t a, int8x8_t b, int8x8_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_s8" type="checkbox"><label for="vmlsq_s8"><div>int8x16_t <b><b>vmlsq_s8</b></b> (int8x16_t a, int8x16_t b, int8x16_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_s16" type="checkbox"><label for="vmls_s16"><div>int16x4_t <b><b>vmls_s16</b></b> (int16x4_t a, int16x4_t b, int16x4_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_s16" type="checkbox"><label for="vmlsq_s16"><div>int16x8_t <b><b>vmlsq_s16</b></b> (int16x8_t a, int16x8_t b, int16x8_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_s32" type="checkbox"><label for="vmls_s32"><div>int32x2_t <b><b>vmls_s32</b></b> (int32x2_t a, int32x2_t b, int32x2_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_s32" type="checkbox"><label for="vmlsq_s32"><div>int32x4_t <b><b>vmlsq_s32</b></b> (int32x4_t a, int32x4_t b, int32x4_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_u8" type="checkbox"><label for="vmls_u8"><div>uint8x8_t <b><b>vmls_u8</b></b> (uint8x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_u8" type="checkbox"><label for="vmlsq_u8"><div>uint8x16_t <b><b>vmlsq_u8</b></b> (uint8x16_t a, uint8x16_t b, uint8x16_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_u16" type="checkbox"><label for="vmls_u16"><div>uint16x4_t <b><b>vmls_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_u16" type="checkbox"><label for="vmlsq_u16"><div>uint16x8_t <b><b>vmlsq_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x8_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_u32" type="checkbox"><label for="vmls_u32"><div>uint32x2_t <b><b>vmls_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_u32" type="checkbox"><label for="vmlsq_u32"><div>uint32x4_t <b><b>vmlsq_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x4_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_f32" type="checkbox"><label for="vmls_f32"><div>float32x2_t <b><b>vmls_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_f32" type="checkbox"><label for="vmlsq_f32"><div>float32x4_t <b><b>vmlsq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_f64" type="checkbox"><label for="vmls_f64"><div>float64x1_t <b><b>vmls_f64</b></b> (float64x1_t a, float64x1_t b, float64x1_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_f64" type="checkbox"><label for="vmlsq_f64"><div>float64x2_t <b><b>vmlsq_f64</b></b> (float64x2_t a, float64x2_t b, float64x2_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_s8" type="checkbox"><label for="vmlsl_s8"><div>int16x8_t <b><b>vmlsl_s8</b></b> (int16x8_t a, int8x8_t b, int8x8_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_s16" type="checkbox"><label for="vmlsl_s16"><div>int32x4_t <b><b>vmlsl_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_s32" type="checkbox"><label for="vmlsl_s32"><div>int64x2_t <b><b>vmlsl_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_u8" type="checkbox"><label for="vmlsl_u8"><div>uint16x8_t <b><b>vmlsl_u8</b></b> (uint16x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_u16" type="checkbox"><label for="vmlsl_u16"><div>uint32x4_t <b><b>vmlsl_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_u32" type="checkbox"><label for="vmlsl_u32"><div>uint64x2_t <b><b>vmlsl_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_s8" type="checkbox"><label for="vmlsl_high_s8"><div>int16x8_t <b><b>vmlsl_high_s8</b></b> (int16x8_t a, int8x16_t b, int8x16_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_s16" type="checkbox"><label for="vmlsl_high_s16"><div>int32x4_t <b><b>vmlsl_high_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_s32" type="checkbox"><label for="vmlsl_high_s32"><div>int64x2_t <b><b>vmlsl_high_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_u8" type="checkbox"><label for="vmlsl_high_u8"><div>uint16x8_t <b><b>vmlsl_high_u8</b></b> (uint16x8_t a, uint8x16_t b, uint8x16_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_u16" type="checkbox"><label for="vmlsl_high_u16"><div>uint32x4_t <b><b>vmlsl_high_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x8_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_u32" type="checkbox"><label for="vmlsl_high_u32"><div>uint64x2_t <b><b>vmlsl_high_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x4_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_f32" type="checkbox"><label for="vfma_f32"><div>float32x2_t <b><b>vfma_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t c)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_f32" type="checkbox"><label for="vfmaq_f32"><div>float32x4_t <b><b>vfmaq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t c)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vfma_f64" type="checkbox"><label for="vfma_f64"><div>float64x1_t <b><b>vfma_f64</b></b> (float64x1_t a, float64x1_t b, float64x1_t c)<span class="right">Floating-point fused multiply-add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&amp;FP source registers, adds the product to the value of the third SIMD&amp;FP source register, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmadd-floating-point-fused-multiply-add-scalar">FMADD</a> Dd,Dn,Dm,Da
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Da <br />
+ b &rarr; Dn <br />
+ c &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) result;
+ bits(datasize) operanda = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[a];
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(operanda, operand1, operand2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_f64" type="checkbox"><label for="vfmaq_f64"><div>float64x2_t <b><b>vfmaq_f64</b></b> (float64x2_t a, float64x2_t b, float64x2_t c)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ c &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_lane_f32" type="checkbox"><label for="vfma_lane_f32"><div>float32x2_t <b><b>vfma_lane_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_lane_f32" type="checkbox"><label for="vfmaq_lane_f32"><div>float32x4_t <b><b>vfmaq_lane_f32</b></b> (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_lane_f64" type="checkbox"><label for="vfma_lane_f64"><div>float64x1_t <b><b>vfma_lane_f64</b></b> (float64x1_t a, float64x1_t b, float64x1_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_lane_f64" type="checkbox"><label for="vfmaq_lane_f64"><div>float64x2_t <b><b>vfmaq_lane_f64</b></b> (float64x2_t a, float64x2_t b, float64x1_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmas_lane_f32" type="checkbox"><label for="vfmas_lane_f32"><div>float32_t <b><b>vfmas_lane_f32</b></b> (float32_t a, float32_t b, float32x2_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmad_lane_f64" type="checkbox"><label for="vfmad_lane_f64"><div>float64_t <b><b>vfmad_lane_f64</b></b> (float64_t a, float64_t b, float64x1_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_laneq_f32" type="checkbox"><label for="vfma_laneq_f32"><div>float32x2_t <b><b>vfma_laneq_f32</b></b> (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_laneq_f32" type="checkbox"><label for="vfmaq_laneq_f32"><div>float32x4_t <b><b>vfmaq_laneq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_laneq_f64" type="checkbox"><label for="vfma_laneq_f64"><div>float64x1_t <b><b>vfma_laneq_f64</b></b> (float64x1_t a, float64x1_t b, float64x2_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_laneq_f64" type="checkbox"><label for="vfmaq_laneq_f64"><div>float64x2_t <b><b>vfmaq_laneq_f64</b></b> (float64x2_t a, float64x2_t b, float64x2_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmas_laneq_f32" type="checkbox"><label for="vfmas_laneq_f32"><div>float32_t <b><b>vfmas_laneq_f32</b></b> (float32_t a, float32_t b, float32x4_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmad_laneq_f64" type="checkbox"><label for="vfmad_laneq_f64"><div>float64_t <b><b>vfmad_laneq_f64</b></b> (float64_t a, float64_t b, float64x2_t v, const int lane)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfms_f32" type="checkbox"><label for="vfms_f32"><div>float32x2_t <b><b>vfms_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t c)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_f32" type="checkbox"><label for="vfmsq_f32"><div>float32x4_t <b><b>vfmsq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t c)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vfms_f64" type="checkbox"><label for="vfms_f64"><div>float64x1_t <b><b>vfms_f64</b></b> (float64x1_t a, float64x1_t b, float64x1_t c)<span class="right">Floating-point fused multiply-subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&amp;FP source registers, negates the product, adds that to the value of the third SIMD&amp;FP source register, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmsub-floating-point-fused-multiply-subtract-scalar">FMSUB</a> Dd,Dn,Dm,Da
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Da <br />
+ b &rarr; Dn <br />
+ c &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) result;
+ bits(datasize) operanda = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[a];
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(operand1);
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(operanda, operand1, operand2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_f64" type="checkbox"><label for="vfmsq_f64"><div>float64x2_t <b><b>vfmsq_f64</b></b> (float64x2_t a, float64x2_t b, float64x2_t c)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ c &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfms_lane_f32" type="checkbox"><label for="vfms_lane_f32"><div>float32x2_t <b><b>vfms_lane_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_lane_f32" type="checkbox"><label for="vfmsq_lane_f32"><div>float32x4_t <b><b>vfmsq_lane_f32</b></b> (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfms_lane_f64" type="checkbox"><label for="vfms_lane_f64"><div>float64x1_t <b><b>vfms_lane_f64</b></b> (float64x1_t a, float64x1_t b, float64x1_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_lane_f64" type="checkbox"><label for="vfmsq_lane_f64"><div>float64x2_t <b><b>vfmsq_lane_f64</b></b> (float64x2_t a, float64x2_t b, float64x1_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmss_lane_f32" type="checkbox"><label for="vfmss_lane_f32"><div>float32_t <b><b>vfmss_lane_f32</b></b> (float32_t a, float32_t b, float32x2_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsd_lane_f64" type="checkbox"><label for="vfmsd_lane_f64"><div>float64_t <b><b>vfmsd_lane_f64</b></b> (float64_t a, float64_t b, float64x1_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfms_laneq_f32" type="checkbox"><label for="vfms_laneq_f32"><div>float32x2_t <b><b>vfms_laneq_f32</b></b> (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_laneq_f32" type="checkbox"><label for="vfmsq_laneq_f32"><div>float32x4_t <b><b>vfmsq_laneq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfms_laneq_f64" type="checkbox"><label for="vfms_laneq_f64"><div>float64x1_t <b><b>vfms_laneq_f64</b></b> (float64x1_t a, float64x1_t b, float64x2_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_laneq_f64" type="checkbox"><label for="vfmsq_laneq_f64"><div>float64x2_t <b><b>vfmsq_laneq_f64</b></b> (float64x2_t a, float64x2_t b, float64x2_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmss_laneq_f32" type="checkbox"><label for="vfmss_laneq_f32"><div>float32_t <b><b>vfmss_laneq_f32</b></b> (float32_t a, float32_t b, float32x4_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsd_laneq_f64" type="checkbox"><label for="vfmsd_laneq_f64"><div>float64_t <b><b>vfmsd_laneq_f64</b></b> (float64_t a, float64_t b, float64x2_t v, const int lane)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_s16" type="checkbox"><label for="vqdmulh_s16"><div>int16x4_t <b><b>vqdmulh_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_s16" type="checkbox"><label for="vqdmulhq_s16"><div>int16x8_t <b><b>vqdmulhq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_s32" type="checkbox"><label for="vqdmulh_s32"><div>int32x2_t <b><b>vqdmulh_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_s32" type="checkbox"><label for="vqdmulhq_s32"><div>int32x4_t <b><b>vqdmulhq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhh_s16" type="checkbox"><label for="vqdmulhh_s16"><div>int16_t <b><b>vqdmulhh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhs_s32" type="checkbox"><label for="vqdmulhs_s32"><div>int32_t <b><b>vqdmulhs_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_s16" type="checkbox"><label for="vqrdmulh_s16"><div>int16x4_t <b><b>vqrdmulh_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_s16" type="checkbox"><label for="vqrdmulhq_s16"><div>int16x8_t <b><b>vqrdmulhq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_s32" type="checkbox"><label for="vqrdmulh_s32"><div>int32x2_t <b><b>vqrdmulh_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_s32" type="checkbox"><label for="vqrdmulhq_s32"><div>int32x4_t <b><b>vqrdmulhq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhh_s16" type="checkbox"><label for="vqrdmulhh_s16"><div>int16_t <b><b>vqrdmulhh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhs_s32" type="checkbox"><label for="vqrdmulhs_s32"><div>int32_t <b><b>vqrdmulhs_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_s16" type="checkbox"><label for="vqdmlal_s16"><div>int32x4_t <b><b>vqdmlal_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_s32" type="checkbox"><label for="vqdmlal_s32"><div>int64x2_t <b><b>vqdmlal_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlalh_s16" type="checkbox"><label for="vqdmlalh_s16"><div>int32_t <b><b>vqdmlalh_s16</b></b> (int32_t a, int16_t b, int16_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Sd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Hn <br />
+ c &rarr; Hm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlals_s32" type="checkbox"><label for="vqdmlals_s32"><div>int64_t <b><b>vqdmlals_s32</b></b> (int64_t a, int32_t b, int32_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Dd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Sn <br />
+ c &rarr; Sm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_s16" type="checkbox"><label for="vqdmlal_high_s16"><div>int32x4_t <b><b>vqdmlal_high_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_s32" type="checkbox"><label for="vqdmlal_high_s32"><div>int64x2_t <b><b>vqdmlal_high_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_s16" type="checkbox"><label for="vqdmlsl_s16"><div>int32x4_t <b><b>vqdmlsl_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_s32" type="checkbox"><label for="vqdmlsl_s32"><div>int64x2_t <b><b>vqdmlsl_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlslh_s16" type="checkbox"><label for="vqdmlslh_s16"><div>int32_t <b><b>vqdmlslh_s16</b></b> (int32_t a, int16_t b, int16_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Sd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Hn <br />
+ c &rarr; Hm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsls_s32" type="checkbox"><label for="vqdmlsls_s32"><div>int64_t <b><b>vqdmlsls_s32</b></b> (int64_t a, int32_t b, int32_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Dd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Sn <br />
+ c &rarr; Sm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_s16" type="checkbox"><label for="vqdmlsl_high_s16"><div>int32x4_t <b><b>vqdmlsl_high_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_s32" type="checkbox"><label for="vqdmlsl_high_s32"><div>int64x2_t <b><b>vqdmlsl_high_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_s8" type="checkbox"><label for="vmull_s8"><div>int16x8_t <b><b>vmull_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_s16" type="checkbox"><label for="vmull_s16"><div>int32x4_t <b><b>vmull_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_s32" type="checkbox"><label for="vmull_s32"><div>int64x2_t <b><b>vmull_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_u8" type="checkbox"><label for="vmull_u8"><div>uint16x8_t <b><b>vmull_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_u16" type="checkbox"><label for="vmull_u16"><div>uint32x4_t <b><b>vmull_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_u32" type="checkbox"><label for="vmull_u32"><div>uint64x2_t <b><b>vmull_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_p8" type="checkbox"><label for="vmull_p8"><div>poly16x8_t <b><b>vmull_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Polynomial multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/pmull-pmull2-polynomial-multiply-long">PMULL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_s8" type="checkbox"><label for="vmull_high_s8"><div>int16x8_t <b><b>vmull_high_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_s16" type="checkbox"><label for="vmull_high_s16"><div>int32x4_t <b><b>vmull_high_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_s32" type="checkbox"><label for="vmull_high_s32"><div>int64x2_t <b><b>vmull_high_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_u8" type="checkbox"><label for="vmull_high_u8"><div>uint16x8_t <b><b>vmull_high_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_u16" type="checkbox"><label for="vmull_high_u16"><div>uint32x4_t <b><b>vmull_high_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_u32" type="checkbox"><label for="vmull_high_u32"><div>uint64x2_t <b><b>vmull_high_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_p8" type="checkbox"><label for="vmull_high_p8"><div>poly16x8_t <b><b>vmull_high_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Polynomial multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/pmull-pmull2-polynomial-multiply-long">PMULL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_s16" type="checkbox"><label for="vqdmull_s16"><div>int32x4_t <b><b>vqdmull_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_s32" type="checkbox"><label for="vqdmull_s32"><div>int64x2_t <b><b>vqdmull_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmullh_s16" type="checkbox"><label for="vqdmullh_s16"><div>int32_t <b><b>vqdmullh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Sd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulls_s32" type="checkbox"><label for="vqdmulls_s32"><div>int64_t <b><b>vqdmulls_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Dd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_s16" type="checkbox"><label for="vqdmull_high_s16"><div>int32x4_t <b><b>vqdmull_high_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_s32" type="checkbox"><label for="vqdmull_high_s32"><div>int64x2_t <b><b>vqdmull_high_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsub_s8" type="checkbox"><label for="vsub_s8"><div>int8x8_t <b><b>vsub_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_s8" type="checkbox"><label for="vsubq_s8"><div>int8x16_t <b><b>vsubq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_s16" type="checkbox"><label for="vsub_s16"><div>int16x4_t <b><b>vsub_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_s16" type="checkbox"><label for="vsubq_s16"><div>int16x8_t <b><b>vsubq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_s32" type="checkbox"><label for="vsub_s32"><div>int32x2_t <b><b>vsub_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_s32" type="checkbox"><label for="vsubq_s32"><div>int32x4_t <b><b>vsubq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_s64" type="checkbox"><label for="vsub_s64"><div>int64x1_t <b><b>vsub_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_s64" type="checkbox"><label for="vsubq_s64"><div>int64x2_t <b><b>vsubq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_u8" type="checkbox"><label for="vsub_u8"><div>uint8x8_t <b><b>vsub_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_u8" type="checkbox"><label for="vsubq_u8"><div>uint8x16_t <b><b>vsubq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_u16" type="checkbox"><label for="vsub_u16"><div>uint16x4_t <b><b>vsub_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_u16" type="checkbox"><label for="vsubq_u16"><div>uint16x8_t <b><b>vsubq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_u32" type="checkbox"><label for="vsub_u32"><div>uint32x2_t <b><b>vsub_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_u32" type="checkbox"><label for="vsubq_u32"><div>uint32x4_t <b><b>vsubq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_u64" type="checkbox"><label for="vsub_u64"><div>uint64x1_t <b><b>vsub_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_u64" type="checkbox"><label for="vsubq_u64"><div>uint64x2_t <b><b>vsubq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_f32" type="checkbox"><label for="vsub_f32"><div>float32x2_t <b><b>vsub_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register, from the corresponding elements in the vector in the first source SIMD&amp;FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsub-vector-floating-point-subtract-vector">FSUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_f32" type="checkbox"><label for="vsubq_f32"><div>float32x4_t <b><b>vsubq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register, from the corresponding elements in the vector in the first source SIMD&amp;FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsub-vector-floating-point-subtract-vector">FSUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsub_f64" type="checkbox"><label for="vsub_f64"><div>float64x1_t <b><b>vsub_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register, from the corresponding elements in the vector in the first source SIMD&amp;FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsub-vector-floating-point-subtract-vector">FSUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubq_f64" type="checkbox"><label for="vsubq_f64"><div>float64x2_t <b><b>vsubq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register, from the corresponding elements in the vector in the first source SIMD&amp;FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsub-vector-floating-point-subtract-vector">FSUB</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubd_s64" type="checkbox"><label for="vsubd_s64"><div>int64_t <b><b>vsubd_s64</b></b> (int64_t a, int64_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubd_u64" type="checkbox"><label for="vsubd_u64"><div>uint64_t <b><b>vsubd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract (vector). This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sub-vector-subtract-vector">SUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_s8" type="checkbox"><label for="vsubl_s8"><div>int16x8_t <b><b>vsubl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubl-ssubl2-signed-subtract-long">SSUBL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_s16" type="checkbox"><label for="vsubl_s16"><div>int32x4_t <b><b>vsubl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubl-ssubl2-signed-subtract-long">SSUBL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_s32" type="checkbox"><label for="vsubl_s32"><div>int64x2_t <b><b>vsubl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubl-ssubl2-signed-subtract-long">SSUBL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_u8" type="checkbox"><label for="vsubl_u8"><div>uint16x8_t <b><b>vsubl_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubl-usubl2-unsigned-subtract-long">USUBL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_u16" type="checkbox"><label for="vsubl_u16"><div>uint32x4_t <b><b>vsubl_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubl-usubl2-unsigned-subtract-long">USUBL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_u32" type="checkbox"><label for="vsubl_u32"><div>uint64x2_t <b><b>vsubl_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubl-usubl2-unsigned-subtract-long">USUBL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_high_s8" type="checkbox"><label for="vsubl_high_s8"><div>int16x8_t <b><b>vsubl_high_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubl-ssubl2-signed-subtract-long">SSUBL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_high_s16" type="checkbox"><label for="vsubl_high_s16"><div>int32x4_t <b><b>vsubl_high_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubl-ssubl2-signed-subtract-long">SSUBL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_high_s32" type="checkbox"><label for="vsubl_high_s32"><div>int64x2_t <b><b>vsubl_high_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubl-ssubl2-signed-subtract-long">SSUBL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_high_u8" type="checkbox"><label for="vsubl_high_u8"><div>uint16x8_t <b><b>vsubl_high_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubl-usubl2-unsigned-subtract-long">USUBL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_high_u16" type="checkbox"><label for="vsubl_high_u16"><div>uint32x4_t <b><b>vsubl_high_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubl-usubl2-unsigned-subtract-long">USUBL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubl_high_u32" type="checkbox"><label for="vsubl_high_u32"><div>uint64x2_t <b><b>vsubl_high_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubl-usubl2-unsigned-subtract-long">USUBL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_s8" type="checkbox"><label for="vsubw_s8"><div>int16x8_t <b><b>vsubw_s8</b></b> (int16x8_t a, int8x8_t b)<span class="right">Signed subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubw-ssubw2-signed-subtract-wide">SSUBW</a> Vd.8H,Vn.8H,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_s16" type="checkbox"><label for="vsubw_s16"><div>int32x4_t <b><b>vsubw_s16</b></b> (int32x4_t a, int16x4_t b)<span class="right">Signed subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubw-ssubw2-signed-subtract-wide">SSUBW</a> Vd.4S,Vn.4S,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_s32" type="checkbox"><label for="vsubw_s32"><div>int64x2_t <b><b>vsubw_s32</b></b> (int64x2_t a, int32x2_t b)<span class="right">Signed subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubw-ssubw2-signed-subtract-wide">SSUBW</a> Vd.2D,Vn.2D,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_u8" type="checkbox"><label for="vsubw_u8"><div>uint16x8_t <b><b>vsubw_u8</b></b> (uint16x8_t a, uint8x8_t b)<span class="right">Unsigned subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element in the lower or upper half of the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubw-usubw2-unsigned-subtract-wide">USUBW</a> Vd.8H,Vn.8H,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_u16" type="checkbox"><label for="vsubw_u16"><div>uint32x4_t <b><b>vsubw_u16</b></b> (uint32x4_t a, uint16x4_t b)<span class="right">Unsigned subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element in the lower or upper half of the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubw-usubw2-unsigned-subtract-wide">USUBW</a> Vd.4S,Vn.4S,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_u32" type="checkbox"><label for="vsubw_u32"><div>uint64x2_t <b><b>vsubw_u32</b></b> (uint64x2_t a, uint32x2_t b)<span class="right">Unsigned subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element in the lower or upper half of the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubw-usubw2-unsigned-subtract-wide">USUBW</a> Vd.2D,Vn.2D,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_high_s8" type="checkbox"><label for="vsubw_high_s8"><div>int16x8_t <b><b>vsubw_high_s8</b></b> (int16x8_t a, int8x16_t b)<span class="right">Signed subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubw-ssubw2-signed-subtract-wide">SSUBW2</a> Vd.8H,Vn.8H,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_high_s16" type="checkbox"><label for="vsubw_high_s16"><div>int32x4_t <b><b>vsubw_high_s16</b></b> (int32x4_t a, int16x8_t b)<span class="right">Signed subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubw-ssubw2-signed-subtract-wide">SSUBW2</a> Vd.4S,Vn.4S,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_high_s32" type="checkbox"><label for="vsubw_high_s32"><div>int64x2_t <b><b>vsubw_high_s32</b></b> (int64x2_t a, int32x4_t b)<span class="right">Signed subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssubw-ssubw2-signed-subtract-wide">SSUBW2</a> Vd.2D,Vn.2D,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_high_u8" type="checkbox"><label for="vsubw_high_u8"><div>uint16x8_t <b><b>vsubw_high_u8</b></b> (uint16x8_t a, uint8x16_t b)<span class="right">Unsigned subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element in the lower or upper half of the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubw-usubw2-unsigned-subtract-wide">USUBW2</a> Vd.8H,Vn.8H,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_high_u16" type="checkbox"><label for="vsubw_high_u16"><div>uint32x4_t <b><b>vsubw_high_u16</b></b> (uint32x4_t a, uint16x8_t b)<span class="right">Unsigned subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element in the lower or upper half of the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubw-usubw2-unsigned-subtract-wide">USUBW2</a> Vd.4S,Vn.4S,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubw_high_u32" type="checkbox"><label for="vsubw_high_u32"><div>uint64x2_t <b><b>vsubw_high_u32</b></b> (uint64x2_t a, uint32x4_t b)<span class="right">Unsigned subtract wide</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element in the lower or upper half of the first source SIMD&amp;FP register, places the result in a vector, and writes the vector to the SIMD&amp;FP destination register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usubw-usubw2-unsigned-subtract-wide">USUBW2</a> Vd.2D,Vn.2D,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ integer sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = sum&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vhsub_s8" type="checkbox"><label for="vhsub_s8"><div>int8x8_t <b><b>vhsub_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register from the corresponding elements in the vector in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shsub-signed-halving-subtract">SHSUB</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsubq_s8" type="checkbox"><label for="vhsubq_s8"><div>int8x16_t <b><b>vhsubq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register from the corresponding elements in the vector in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shsub-signed-halving-subtract">SHSUB</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsub_s16" type="checkbox"><label for="vhsub_s16"><div>int16x4_t <b><b>vhsub_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register from the corresponding elements in the vector in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shsub-signed-halving-subtract">SHSUB</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsubq_s16" type="checkbox"><label for="vhsubq_s16"><div>int16x8_t <b><b>vhsubq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register from the corresponding elements in the vector in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shsub-signed-halving-subtract">SHSUB</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsub_s32" type="checkbox"><label for="vhsub_s32"><div>int32x2_t <b><b>vhsub_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register from the corresponding elements in the vector in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shsub-signed-halving-subtract">SHSUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsubq_s32" type="checkbox"><label for="vhsubq_s32"><div>int32x4_t <b><b>vhsubq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&amp;FP register from the corresponding elements in the vector in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shsub-signed-halving-subtract">SHSUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsub_u8" type="checkbox"><label for="vhsub_u8"><div>uint8x8_t <b><b>vhsub_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&amp;FP register from the corresponding vector elements in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhsub-unsigned-halving-subtract">UHSUB</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsubq_u8" type="checkbox"><label for="vhsubq_u8"><div>uint8x16_t <b><b>vhsubq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&amp;FP register from the corresponding vector elements in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhsub-unsigned-halving-subtract">UHSUB</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsub_u16" type="checkbox"><label for="vhsub_u16"><div>uint16x4_t <b><b>vhsub_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&amp;FP register from the corresponding vector elements in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhsub-unsigned-halving-subtract">UHSUB</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsubq_u16" type="checkbox"><label for="vhsubq_u16"><div>uint16x8_t <b><b>vhsubq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&amp;FP register from the corresponding vector elements in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhsub-unsigned-halving-subtract">UHSUB</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsub_u32" type="checkbox"><label for="vhsub_u32"><div>uint32x2_t <b><b>vhsub_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&amp;FP register from the corresponding vector elements in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhsub-unsigned-halving-subtract">UHSUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vhsubq_u32" type="checkbox"><label for="vhsubq_u32"><div>uint32x4_t <b><b>vhsubq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned halving subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&amp;FP register from the corresponding vector elements in the first source SIMD&amp;FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uhsub-unsigned-halving-subtract">UHSUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = diff&lt;esize:1&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_s8" type="checkbox"><label for="vqsub_s8"><div>int8x8_t <b><b>vqsub_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_s8" type="checkbox"><label for="vqsubq_s8"><div>int8x16_t <b><b>vqsubq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_s16" type="checkbox"><label for="vqsub_s16"><div>int16x4_t <b><b>vqsub_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_s16" type="checkbox"><label for="vqsubq_s16"><div>int16x8_t <b><b>vqsubq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_s32" type="checkbox"><label for="vqsub_s32"><div>int32x2_t <b><b>vqsub_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_s32" type="checkbox"><label for="vqsubq_s32"><div>int32x4_t <b><b>vqsubq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_s64" type="checkbox"><label for="vqsub_s64"><div>int64x1_t <b><b>vqsub_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_s64" type="checkbox"><label for="vqsubq_s64"><div>int64x2_t <b><b>vqsubq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_u8" type="checkbox"><label for="vqsub_u8"><div>uint8x8_t <b><b>vqsub_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_u8" type="checkbox"><label for="vqsubq_u8"><div>uint8x16_t <b><b>vqsubq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_u16" type="checkbox"><label for="vqsub_u16"><div>uint16x4_t <b><b>vqsub_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_u16" type="checkbox"><label for="vqsubq_u16"><div>uint16x8_t <b><b>vqsubq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_u32" type="checkbox"><label for="vqsub_u32"><div>uint32x2_t <b><b>vqsub_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_u32" type="checkbox"><label for="vqsubq_u32"><div>uint32x4_t <b><b>vqsubq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsub_u64" type="checkbox"><label for="vqsub_u64"><div>uint64x1_t <b><b>vqsub_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubq_u64" type="checkbox"><label for="vqsubq_u64"><div>uint64x2_t <b><b>vqsubq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqsubb_s8" type="checkbox"><label for="vqsubb_s8"><div>int8_t <b><b>vqsubb_s8</b></b> (int8_t a, int8_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubh_s16" type="checkbox"><label for="vqsubh_s16"><div>int16_t <b><b>vqsubh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubs_s32" type="checkbox"><label for="vqsubs_s32"><div>int32_t <b><b>vqsubs_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubd_s64" type="checkbox"><label for="vqsubd_s64"><div>int64_t <b><b>vqsubd_s64</b></b> (int64_t a, int64_t b)<span class="right">Signed saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqsub-signed-saturating-subtract">SQSUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubb_u8" type="checkbox"><label for="vqsubb_u8"><div>uint8_t <b><b>vqsubb_u8</b></b> (uint8_t a, uint8_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubh_u16" type="checkbox"><label for="vqsubh_u16"><div>uint16_t <b><b>vqsubh_u16</b></b> (uint16_t a, uint16_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubs_u32" type="checkbox"><label for="vqsubs_u32"><div>uint32_t <b><b>vqsubs_u32</b></b> (uint32_t a, uint32_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqsubd_u64" type="checkbox"><label for="vqsubd_u64"><div>uint64_t <b><b>vqsubd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Unsigned saturating subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&amp;FP register from the corresponding element values of the first source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqsub-unsigned-saturating-subtract">UQSUB</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer diff;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     diff = element1 - element2;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_s16" type="checkbox"><label for="vsubhn_s16"><div>int8x8_t <b><b>vsubhn_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_s32" type="checkbox"><label for="vsubhn_s32"><div>int16x4_t <b><b>vsubhn_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_s64" type="checkbox"><label for="vsubhn_s64"><div>int32x2_t <b><b>vsubhn_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_u16" type="checkbox"><label for="vsubhn_u16"><div>uint8x8_t <b><b>vsubhn_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_u32" type="checkbox"><label for="vsubhn_u32"><div>uint16x4_t <b><b>vsubhn_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_u64" type="checkbox"><label for="vsubhn_u64"><div>uint32x2_t <b><b>vsubhn_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_high_s16" type="checkbox"><label for="vsubhn_high_s16"><div>int8x16_t <b><b>vsubhn_high_s16</b></b> (int8x8_t r, int16x8_t a, int16x8_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_high_s32" type="checkbox"><label for="vsubhn_high_s32"><div>int16x8_t <b><b>vsubhn_high_s32</b></b> (int16x4_t r, int32x4_t a, int32x4_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_high_s64" type="checkbox"><label for="vsubhn_high_s64"><div>int32x4_t <b><b>vsubhn_high_s64</b></b> (int32x2_t r, int64x2_t a, int64x2_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_high_u16" type="checkbox"><label for="vsubhn_high_u16"><div>uint8x16_t <b><b>vsubhn_high_u16</b></b> (uint8x8_t r, uint16x8_t a, uint16x8_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_high_u32" type="checkbox"><label for="vsubhn_high_u32"><div>uint16x8_t <b><b>vsubhn_high_u32</b></b> (uint16x4_t r, uint32x4_t a, uint32x4_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsubhn_high_u64" type="checkbox"><label for="vsubhn_high_u64"><div>uint32x4_t <b><b>vsubhn_high_u64</b></b> (uint32x2_t r, uint64x2_t a, uint64x2_t b)<span class="right">Subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&amp;FP register from the corresponding vector element in the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/subhn-subhn2-subtract-returning-high-narrow">SUBHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_s16" type="checkbox"><label for="vrsubhn_s16"><div>int8x8_t <b><b>vrsubhn_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_s32" type="checkbox"><label for="vrsubhn_s32"><div>int16x4_t <b><b>vrsubhn_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_s64" type="checkbox"><label for="vrsubhn_s64"><div>int32x2_t <b><b>vrsubhn_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_u16" type="checkbox"><label for="vrsubhn_u16"><div>uint8x8_t <b><b>vrsubhn_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN</a> Vd.8B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_u32" type="checkbox"><label for="vrsubhn_u32"><div>uint16x4_t <b><b>vrsubhn_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN</a> Vd.4H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_u64" type="checkbox"><label for="vrsubhn_u64"><div>uint32x2_t <b><b>vrsubhn_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN</a> Vd.2S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_high_s16" type="checkbox"><label for="vrsubhn_high_s16"><div>int8x16_t <b><b>vrsubhn_high_s16</b></b> (int8x8_t r, int16x8_t a, int16x8_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_high_s32" type="checkbox"><label for="vrsubhn_high_s32"><div>int16x8_t <b><b>vrsubhn_high_s32</b></b> (int16x4_t r, int32x4_t a, int32x4_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_high_s64" type="checkbox"><label for="vrsubhn_high_s64"><div>int32x4_t <b><b>vrsubhn_high_s64</b></b> (int32x2_t r, int64x2_t a, int64x2_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_high_u16" type="checkbox"><label for="vrsubhn_high_u16"><div>uint8x16_t <b><b>vrsubhn_high_u16</b></b> (uint8x8_t r, uint16x8_t a, uint16x8_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN2</a> Vd.16B,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_high_u32" type="checkbox"><label for="vrsubhn_high_u32"><div>uint16x8_t <b><b>vrsubhn_high_u32</b></b> (uint16x4_t r, uint32x4_t a, uint32x4_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN2</a> Vd.8H,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsubhn_high_u64" type="checkbox"><label for="vrsubhn_high_u64"><div>uint32x4_t <b><b>vrsubhn_high_u64</b></b> (uint32x2_t r, uint64x2_t a, uint64x2_t b)<span class="right">Rounding subtract returning high narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&amp;FP register from the corresponding vector element of the first source SIMD&amp;FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rsubhn-rsubhn2-rounding-subtract-returning-high-narrow">RSUBHN2</a> Vd.4S,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(2*datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if round then 1 &lt;&lt; (esize - 1) else 0;
+ bits(2*esize) element1;
+ bits(2*esize) element2;
+ bits(2*esize) sum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
+     if sub_op then
+         sum = element1 - element2;
+     else
+         sum = element1 + element2;
+     sum = sum + round_const;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum&lt;2*esize-1:esize&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceq_s8" type="checkbox"><label for="vceq_s8"><div>uint8x8_t <b><b>vceq_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_s8" type="checkbox"><label for="vceqq_s8"><div>uint8x16_t <b><b>vceqq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_s16" type="checkbox"><label for="vceq_s16"><div>uint16x4_t <b><b>vceq_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_s16" type="checkbox"><label for="vceqq_s16"><div>uint16x8_t <b><b>vceqq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_s32" type="checkbox"><label for="vceq_s32"><div>uint32x2_t <b><b>vceq_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_s32" type="checkbox"><label for="vceqq_s32"><div>uint32x4_t <b><b>vceqq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_u8" type="checkbox"><label for="vceq_u8"><div>uint8x8_t <b><b>vceq_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_u8" type="checkbox"><label for="vceqq_u8"><div>uint8x16_t <b><b>vceqq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_u16" type="checkbox"><label for="vceq_u16"><div>uint16x4_t <b><b>vceq_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_u16" type="checkbox"><label for="vceqq_u16"><div>uint16x8_t <b><b>vceqq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_u32" type="checkbox"><label for="vceq_u32"><div>uint32x2_t <b><b>vceq_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_u32" type="checkbox"><label for="vceqq_u32"><div>uint32x4_t <b><b>vceqq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_f32" type="checkbox"><label for="vceq_f32"><div>uint32x2_t <b><b>vceq_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_f32" type="checkbox"><label for="vceqq_f32"><div>uint32x4_t <b><b>vceqq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_p8" type="checkbox"><label for="vceq_p8"><div>uint8x8_t <b><b>vceq_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_p8" type="checkbox"><label for="vceqq_p8"><div>uint8x16_t <b><b>vceqq_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_s64" type="checkbox"><label for="vceq_s64"><div>uint64x1_t <b><b>vceq_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_s64" type="checkbox"><label for="vceqq_s64"><div>uint64x2_t <b><b>vceqq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceq_u64" type="checkbox"><label for="vceq_u64"><div>uint64x1_t <b><b>vceq_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_u64" type="checkbox"><label for="vceqq_u64"><div>uint64x2_t <b><b>vceqq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceq_p64" type="checkbox"><label for="vceq_p64"><div>uint64x1_t <b><b>vceq_p64</b></b> (poly64x1_t a, poly64x1_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_p64" type="checkbox"><label for="vceqq_p64"><div>uint64x2_t <b><b>vceqq_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceq_f64" type="checkbox"><label for="vceq_f64"><div>uint64x1_t <b><b>vceq_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqq_f64" type="checkbox"><label for="vceqq_f64"><div>uint64x2_t <b><b>vceqq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqd_s64" type="checkbox"><label for="vceqd_s64"><div>uint64_t <b><b>vceqd_s64</b></b> (int64_t a, int64_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqd_u64" type="checkbox"><label for="vceqd_u64"><div>uint64_t <b><b>vceqd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqs_f32" type="checkbox"><label for="vceqs_f32"><div>uint32_t <b><b>vceqs_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqd_f64" type="checkbox"><label for="vceqd_f64"><div>uint64_t <b><b>vceqd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_s8" type="checkbox"><label for="vceqz_s8"><div>uint8x8_t <b><b>vceqz_s8</b></b> (int8x8_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_s8" type="checkbox"><label for="vceqzq_s8"><div>uint8x16_t <b><b>vceqzq_s8</b></b> (int8x16_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_s16" type="checkbox"><label for="vceqz_s16"><div>uint16x4_t <b><b>vceqz_s16</b></b> (int16x4_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4H,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_s16" type="checkbox"><label for="vceqzq_s16"><div>uint16x8_t <b><b>vceqzq_s16</b></b> (int16x8_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8H,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_s32" type="checkbox"><label for="vceqz_s32"><div>uint32x2_t <b><b>vceqz_s32</b></b> (int32x2_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_s32" type="checkbox"><label for="vceqzq_s32"><div>uint32x4_t <b><b>vceqzq_s32</b></b> (int32x4_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_u8" type="checkbox"><label for="vceqz_u8"><div>uint8x8_t <b><b>vceqz_u8</b></b> (uint8x8_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_u8" type="checkbox"><label for="vceqzq_u8"><div>uint8x16_t <b><b>vceqzq_u8</b></b> (uint8x16_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_u16" type="checkbox"><label for="vceqz_u16"><div>uint16x4_t <b><b>vceqz_u16</b></b> (uint16x4_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4H,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_u16" type="checkbox"><label for="vceqzq_u16"><div>uint16x8_t <b><b>vceqzq_u16</b></b> (uint16x8_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8H,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_u32" type="checkbox"><label for="vceqz_u32"><div>uint32x2_t <b><b>vceqz_u32</b></b> (uint32x2_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_u32" type="checkbox"><label for="vceqzq_u32"><div>uint32x4_t <b><b>vceqzq_u32</b></b> (uint32x4_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_f32" type="checkbox"><label for="vceqz_f32"><div>uint32x2_t <b><b>vceqz_f32</b></b> (float32x2_t a)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_f32" type="checkbox"><label for="vceqzq_f32"><div>uint32x4_t <b><b>vceqzq_f32</b></b> (float32x4_t a)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_p8" type="checkbox"><label for="vceqz_p8"><div>uint8x8_t <b><b>vceqz_p8</b></b> (poly8x8_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_p8" type="checkbox"><label for="vceqzq_p8"><div>uint8x16_t <b><b>vceqzq_p8</b></b> (poly8x16_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_s64" type="checkbox"><label for="vceqz_s64"><div>uint64x1_t <b><b>vceqz_s64</b></b> (int64x1_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_s64" type="checkbox"><label for="vceqzq_s64"><div>uint64x2_t <b><b>vceqzq_s64</b></b> (int64x2_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_u64" type="checkbox"><label for="vceqz_u64"><div>uint64x1_t <b><b>vceqz_u64</b></b> (uint64x1_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_u64" type="checkbox"><label for="vceqzq_u64"><div>uint64x2_t <b><b>vceqzq_u64</b></b> (uint64x2_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_p64" type="checkbox"><label for="vceqz_p64"><div>uint64x1_t <b><b>vceqz_p64</b></b> (poly64x1_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_p64" type="checkbox"><label for="vceqzq_p64"><div>uint64x2_t <b><b>vceqzq_p64</b></b> (poly64x2_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vceqz_f64" type="checkbox"><label for="vceqz_f64"><div>uint64x1_t <b><b>vceqz_f64</b></b> (float64x1_t a)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzq_f64" type="checkbox"><label for="vceqzq_f64"><div>uint64x2_t <b><b>vceqzq_f64</b></b> (float64x2_t a)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzd_s64" type="checkbox"><label for="vceqzd_s64"><div>uint64_t <b><b>vceqzd_s64</b></b> (int64_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzd_u64" type="checkbox"><label for="vceqzd_u64"><div>uint64_t <b><b>vceqzd_u64</b></b> (uint64_t a)<span class="right">Compare bitwise equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmeq-zero-compare-bitwise-equal-to-zero-vector">CMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzs_f32" type="checkbox"><label for="vceqzs_f32"><div>uint32_t <b><b>vceqzs_f32</b></b> (float32_t a)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Sd,Sn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vceqzd_f64" type="checkbox"><label for="vceqzd_f64"><div>uint64_t <b><b>vceqzd_f64</b></b> (float64_t a)<span class="right">Floating-point compare equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmeq-zero-floating-point-compare-equal-to-zero-vector">FCMEQ</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcge_s8" type="checkbox"><label for="vcge_s8"><div>uint8x8_t <b><b>vcge_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.8B,Vm.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_s8" type="checkbox"><label for="vcgeq_s8"><div>uint8x16_t <b><b>vcgeq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.16B,Vm.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_s16" type="checkbox"><label for="vcge_s16"><div>uint16x4_t <b><b>vcge_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.4H,Vm.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_s16" type="checkbox"><label for="vcgeq_s16"><div>uint16x8_t <b><b>vcgeq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.8H,Vm.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_s32" type="checkbox"><label for="vcge_s32"><div>uint32x2_t <b><b>vcge_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_s32" type="checkbox"><label for="vcgeq_s32"><div>uint32x4_t <b><b>vcgeq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_u8" type="checkbox"><label for="vcge_u8"><div>uint8x8_t <b><b>vcge_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.8B,Vm.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_u8" type="checkbox"><label for="vcgeq_u8"><div>uint8x16_t <b><b>vcgeq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.16B,Vm.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_u16" type="checkbox"><label for="vcge_u16"><div>uint16x4_t <b><b>vcge_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.4H,Vm.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_u16" type="checkbox"><label for="vcgeq_u16"><div>uint16x8_t <b><b>vcgeq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.8H,Vm.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_u32" type="checkbox"><label for="vcge_u32"><div>uint32x2_t <b><b>vcge_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_u32" type="checkbox"><label for="vcgeq_u32"><div>uint32x4_t <b><b>vcgeq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_f32" type="checkbox"><label for="vcge_f32"><div>uint32x2_t <b><b>vcge_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_f32" type="checkbox"><label for="vcgeq_f32"><div>uint32x4_t <b><b>vcgeq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcge_s64" type="checkbox"><label for="vcge_s64"><div>uint64x1_t <b><b>vcge_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_s64" type="checkbox"><label for="vcgeq_s64"><div>uint64x2_t <b><b>vcgeq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcge_u64" type="checkbox"><label for="vcge_u64"><div>uint64x1_t <b><b>vcge_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_u64" type="checkbox"><label for="vcgeq_u64"><div>uint64x2_t <b><b>vcgeq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcge_f64" type="checkbox"><label for="vcge_f64"><div>uint64x1_t <b><b>vcge_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgeq_f64" type="checkbox"><label for="vcgeq_f64"><div>uint64x2_t <b><b>vcgeq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcged_s64" type="checkbox"><label for="vcged_s64"><div>uint64_t <b><b>vcged_s64</b></b> (int64_t a, int64_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcged_u64" type="checkbox"><label for="vcged_u64"><div>uint64_t <b><b>vcged_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcges_f32" type="checkbox"><label for="vcges_f32"><div>uint32_t <b><b>vcges_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcged_f64" type="checkbox"><label for="vcged_f64"><div>uint64_t <b><b>vcged_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgez_s8" type="checkbox"><label for="vcgez_s8"><div>uint8x8_t <b><b>vcgez_s8</b></b> (int8x8_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezq_s8" type="checkbox"><label for="vcgezq_s8"><div>uint8x16_t <b><b>vcgezq_s8</b></b> (int8x16_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgez_s16" type="checkbox"><label for="vcgez_s16"><div>uint16x4_t <b><b>vcgez_s16</b></b> (int16x4_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.4H,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezq_s16" type="checkbox"><label for="vcgezq_s16"><div>uint16x8_t <b><b>vcgezq_s16</b></b> (int16x8_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.8H,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgez_s32" type="checkbox"><label for="vcgez_s32"><div>uint32x2_t <b><b>vcgez_s32</b></b> (int32x2_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezq_s32" type="checkbox"><label for="vcgezq_s32"><div>uint32x4_t <b><b>vcgezq_s32</b></b> (int32x4_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgez_s64" type="checkbox"><label for="vcgez_s64"><div>uint64x1_t <b><b>vcgez_s64</b></b> (int64x1_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezq_s64" type="checkbox"><label for="vcgezq_s64"><div>uint64x2_t <b><b>vcgezq_s64</b></b> (int64x2_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgez_f32" type="checkbox"><label for="vcgez_f32"><div>uint32x2_t <b><b>vcgez_f32</b></b> (float32x2_t a)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezq_f32" type="checkbox"><label for="vcgezq_f32"><div>uint32x4_t <b><b>vcgezq_f32</b></b> (float32x4_t a)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgez_f64" type="checkbox"><label for="vcgez_f64"><div>uint64x1_t <b><b>vcgez_f64</b></b> (float64x1_t a)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezq_f64" type="checkbox"><label for="vcgezq_f64"><div>uint64x2_t <b><b>vcgezq_f64</b></b> (float64x2_t a)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezd_s64" type="checkbox"><label for="vcgezd_s64"><div>uint64_t <b><b>vcgezd_s64</b></b> (int64_t a)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezs_f32" type="checkbox"><label for="vcgezs_f32"><div>uint32_t <b><b>vcgezs_f32</b></b> (float32_t a)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Sd,Sn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgezd_f64" type="checkbox"><label for="vcgezd_f64"><div>uint64_t <b><b>vcgezd_f64</b></b> (float64_t a)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcle_s8" type="checkbox"><label for="vcle_s8"><div>uint8x8_t <b><b>vcle_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.8B,Vm.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_s8" type="checkbox"><label for="vcleq_s8"><div>uint8x16_t <b><b>vcleq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.16B,Vm.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_s16" type="checkbox"><label for="vcle_s16"><div>uint16x4_t <b><b>vcle_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.4H,Vm.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_s16" type="checkbox"><label for="vcleq_s16"><div>uint16x8_t <b><b>vcleq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.8H,Vm.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_s32" type="checkbox"><label for="vcle_s32"><div>uint32x2_t <b><b>vcle_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_s32" type="checkbox"><label for="vcleq_s32"><div>uint32x4_t <b><b>vcleq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_u8" type="checkbox"><label for="vcle_u8"><div>uint8x8_t <b><b>vcle_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.8B,Vm.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_u8" type="checkbox"><label for="vcleq_u8"><div>uint8x16_t <b><b>vcleq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.16B,Vm.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_u16" type="checkbox"><label for="vcle_u16"><div>uint16x4_t <b><b>vcle_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.4H,Vm.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_u16" type="checkbox"><label for="vcleq_u16"><div>uint16x8_t <b><b>vcleq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.8H,Vm.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_u32" type="checkbox"><label for="vcle_u32"><div>uint32x2_t <b><b>vcle_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_u32" type="checkbox"><label for="vcleq_u32"><div>uint32x4_t <b><b>vcleq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_f32" type="checkbox"><label for="vcle_f32"><div>uint32x2_t <b><b>vcle_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_f32" type="checkbox"><label for="vcleq_f32"><div>uint32x4_t <b><b>vcleq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcle_s64" type="checkbox"><label for="vcle_s64"><div>uint64x1_t <b><b>vcle_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_s64" type="checkbox"><label for="vcleq_s64"><div>uint64x2_t <b><b>vcleq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcle_u64" type="checkbox"><label for="vcle_u64"><div>uint64x1_t <b><b>vcle_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_u64" type="checkbox"><label for="vcleq_u64"><div>uint64x2_t <b><b>vcleq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcle_f64" type="checkbox"><label for="vcle_f64"><div>uint64x1_t <b><b>vcle_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcleq_f64" type="checkbox"><label for="vcleq_f64"><div>uint64x2_t <b><b>vcleq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcled_s64" type="checkbox"><label for="vcled_s64"><div>uint64_t <b><b>vcled_s64</b></b> (int64_t a, int64_t b)<span class="right">Compare signed greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmge-zero-compare-signed-greater-than-or-equal-to-zero-vector">CMGE</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcled_u64" type="checkbox"><label for="vcled_u64"><div>uint64_t <b><b>vcled_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Compare unsigned higher or same</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcles_f32" type="checkbox"><label for="vcles_f32"><div>uint32_t <b><b>vcles_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Sd,Sm,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcled_f64" type="checkbox"><label for="vcled_f64"><div>uint64_t <b><b>vcled_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point compare greater than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmge-zero-floating-point-compare-greater-than-or-equal-to-zero-vector">FCMGE</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclez_s8" type="checkbox"><label for="vclez_s8"><div>uint8x8_t <b><b>vclez_s8</b></b> (int8x8_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezq_s8" type="checkbox"><label for="vclezq_s8"><div>uint8x16_t <b><b>vclezq_s8</b></b> (int8x16_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclez_s16" type="checkbox"><label for="vclez_s16"><div>uint16x4_t <b><b>vclez_s16</b></b> (int16x4_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.4H,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezq_s16" type="checkbox"><label for="vclezq_s16"><div>uint16x8_t <b><b>vclezq_s16</b></b> (int16x8_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.8H,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclez_s32" type="checkbox"><label for="vclez_s32"><div>uint32x2_t <b><b>vclez_s32</b></b> (int32x2_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezq_s32" type="checkbox"><label for="vclezq_s32"><div>uint32x4_t <b><b>vclezq_s32</b></b> (int32x4_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclez_s64" type="checkbox"><label for="vclez_s64"><div>uint64x1_t <b><b>vclez_s64</b></b> (int64x1_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezq_s64" type="checkbox"><label for="vclezq_s64"><div>uint64x2_t <b><b>vclezq_s64</b></b> (int64x2_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclez_f32" type="checkbox"><label for="vclez_f32"><div>uint32x2_t <b><b>vclez_f32</b></b> (float32x2_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezq_f32" type="checkbox"><label for="vclezq_f32"><div>uint32x4_t <b><b>vclezq_f32</b></b> (float32x4_t a)<span class="right">Floating-point compare less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmle-zero-floating-point-compare-less-than-or-equal-to-zero-vector">FCMLE</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclez_f64" type="checkbox"><label for="vclez_f64"><div>uint64x1_t <b><b>vclez_f64</b></b> (float64x1_t a)<span class="right">Floating-point compare less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmle-zero-floating-point-compare-less-than-or-equal-to-zero-vector">FCMLE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezq_f64" type="checkbox"><label for="vclezq_f64"><div>uint64x2_t <b><b>vclezq_f64</b></b> (float64x2_t a)<span class="right">Floating-point compare less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmle-zero-floating-point-compare-less-than-or-equal-to-zero-vector">FCMLE</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezd_s64" type="checkbox"><label for="vclezd_s64"><div>uint64_t <b><b>vclezd_s64</b></b> (int64_t a)<span class="right">Compare signed less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmle-zero-compare-signed-less-than-or-equal-to-zero-vector">CMLE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezs_f32" type="checkbox"><label for="vclezs_f32"><div>uint32_t <b><b>vclezs_f32</b></b> (float32_t a)<span class="right">Floating-point compare less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmle-zero-floating-point-compare-less-than-or-equal-to-zero-vector">FCMLE</a> Sd,Sn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclezd_f64" type="checkbox"><label for="vclezd_f64"><div>uint64_t <b><b>vclezd_f64</b></b> (float64_t a)<span class="right">Floating-point compare less than or equal to zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmle-zero-floating-point-compare-less-than-or-equal-to-zero-vector">FCMLE</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_s8" type="checkbox"><label for="vcgt_s8"><div>uint8x8_t <b><b>vcgt_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_s8" type="checkbox"><label for="vcgtq_s8"><div>uint8x16_t <b><b>vcgtq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_s16" type="checkbox"><label for="vcgt_s16"><div>uint16x4_t <b><b>vcgt_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_s16" type="checkbox"><label for="vcgtq_s16"><div>uint16x8_t <b><b>vcgtq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_s32" type="checkbox"><label for="vcgt_s32"><div>uint32x2_t <b><b>vcgt_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_s32" type="checkbox"><label for="vcgtq_s32"><div>uint32x4_t <b><b>vcgtq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_u8" type="checkbox"><label for="vcgt_u8"><div>uint8x8_t <b><b>vcgt_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_u8" type="checkbox"><label for="vcgtq_u8"><div>uint8x16_t <b><b>vcgtq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_u16" type="checkbox"><label for="vcgt_u16"><div>uint16x4_t <b><b>vcgt_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_u16" type="checkbox"><label for="vcgtq_u16"><div>uint16x8_t <b><b>vcgtq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_u32" type="checkbox"><label for="vcgt_u32"><div>uint32x2_t <b><b>vcgt_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_u32" type="checkbox"><label for="vcgtq_u32"><div>uint32x4_t <b><b>vcgtq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_f32" type="checkbox"><label for="vcgt_f32"><div>uint32x2_t <b><b>vcgt_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_f32" type="checkbox"><label for="vcgtq_f32"><div>uint32x4_t <b><b>vcgtq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_s64" type="checkbox"><label for="vcgt_s64"><div>uint64x1_t <b><b>vcgt_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_s64" type="checkbox"><label for="vcgtq_s64"><div>uint64x2_t <b><b>vcgtq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_u64" type="checkbox"><label for="vcgt_u64"><div>uint64x1_t <b><b>vcgt_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_u64" type="checkbox"><label for="vcgtq_u64"><div>uint64x2_t <b><b>vcgtq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgt_f64" type="checkbox"><label for="vcgt_f64"><div>uint64x1_t <b><b>vcgt_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtq_f64" type="checkbox"><label for="vcgtq_f64"><div>uint64x2_t <b><b>vcgtq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtd_s64" type="checkbox"><label for="vcgtd_s64"><div>uint64_t <b><b>vcgtd_s64</b></b> (int64_t a, int64_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtd_u64" type="checkbox"><label for="vcgtd_u64"><div>uint64_t <b><b>vcgtd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgts_f32" type="checkbox"><label for="vcgts_f32"><div>uint32_t <b><b>vcgts_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtd_f64" type="checkbox"><label for="vcgtd_f64"><div>uint64_t <b><b>vcgtd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtz_s8" type="checkbox"><label for="vcgtz_s8"><div>uint8x8_t <b><b>vcgtz_s8</b></b> (int8x8_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzq_s8" type="checkbox"><label for="vcgtzq_s8"><div>uint8x16_t <b><b>vcgtzq_s8</b></b> (int8x16_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtz_s16" type="checkbox"><label for="vcgtz_s16"><div>uint16x4_t <b><b>vcgtz_s16</b></b> (int16x4_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.4H,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzq_s16" type="checkbox"><label for="vcgtzq_s16"><div>uint16x8_t <b><b>vcgtzq_s16</b></b> (int16x8_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.8H,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtz_s32" type="checkbox"><label for="vcgtz_s32"><div>uint32x2_t <b><b>vcgtz_s32</b></b> (int32x2_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzq_s32" type="checkbox"><label for="vcgtzq_s32"><div>uint32x4_t <b><b>vcgtzq_s32</b></b> (int32x4_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtz_s64" type="checkbox"><label for="vcgtz_s64"><div>uint64x1_t <b><b>vcgtz_s64</b></b> (int64x1_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzq_s64" type="checkbox"><label for="vcgtzq_s64"><div>uint64x2_t <b><b>vcgtzq_s64</b></b> (int64x2_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtz_f32" type="checkbox"><label for="vcgtz_f32"><div>uint32x2_t <b><b>vcgtz_f32</b></b> (float32x2_t a)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzq_f32" type="checkbox"><label for="vcgtzq_f32"><div>uint32x4_t <b><b>vcgtzq_f32</b></b> (float32x4_t a)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtz_f64" type="checkbox"><label for="vcgtz_f64"><div>uint64x1_t <b><b>vcgtz_f64</b></b> (float64x1_t a)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzq_f64" type="checkbox"><label for="vcgtzq_f64"><div>uint64x2_t <b><b>vcgtzq_f64</b></b> (float64x2_t a)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzd_s64" type="checkbox"><label for="vcgtzd_s64"><div>uint64_t <b><b>vcgtzd_s64</b></b> (int64_t a)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzs_f32" type="checkbox"><label for="vcgtzs_f32"><div>uint32_t <b><b>vcgtzs_f32</b></b> (float32_t a)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Sd,Sn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcgtzd_f64" type="checkbox"><label for="vcgtzd_f64"><div>uint64_t <b><b>vcgtzd_f64</b></b> (float64_t a)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclt_s8" type="checkbox"><label for="vclt_s8"><div>uint8x8_t <b><b>vclt_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.8B,Vm.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_s8" type="checkbox"><label for="vcltq_s8"><div>uint8x16_t <b><b>vcltq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.16B,Vm.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_s16" type="checkbox"><label for="vclt_s16"><div>uint16x4_t <b><b>vclt_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.4H,Vm.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_s16" type="checkbox"><label for="vcltq_s16"><div>uint16x8_t <b><b>vcltq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.8H,Vm.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_s32" type="checkbox"><label for="vclt_s32"><div>uint32x2_t <b><b>vclt_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_s32" type="checkbox"><label for="vcltq_s32"><div>uint32x4_t <b><b>vcltq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_u8" type="checkbox"><label for="vclt_u8"><div>uint8x8_t <b><b>vclt_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.8B,Vm.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_u8" type="checkbox"><label for="vcltq_u8"><div>uint8x16_t <b><b>vcltq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.16B,Vm.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_u16" type="checkbox"><label for="vclt_u16"><div>uint16x4_t <b><b>vclt_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.4H,Vm.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_u16" type="checkbox"><label for="vcltq_u16"><div>uint16x8_t <b><b>vcltq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.8H,Vm.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_u32" type="checkbox"><label for="vclt_u32"><div>uint32x2_t <b><b>vclt_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_u32" type="checkbox"><label for="vcltq_u32"><div>uint32x4_t <b><b>vcltq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_f32" type="checkbox"><label for="vclt_f32"><div>uint32x2_t <b><b>vclt_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_f32" type="checkbox"><label for="vcltq_f32"><div>uint32x4_t <b><b>vcltq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclt_s64" type="checkbox"><label for="vclt_s64"><div>uint64x1_t <b><b>vclt_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_s64" type="checkbox"><label for="vcltq_s64"><div>uint64x2_t <b><b>vcltq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclt_u64" type="checkbox"><label for="vclt_u64"><div>uint64x1_t <b><b>vclt_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_u64" type="checkbox"><label for="vcltq_u64"><div>uint64x2_t <b><b>vcltq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclt_f64" type="checkbox"><label for="vclt_f64"><div>uint64x1_t <b><b>vclt_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltq_f64" type="checkbox"><label for="vcltq_f64"><div>uint64x2_t <b><b>vcltq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltd_s64" type="checkbox"><label for="vcltd_s64"><div>uint64_t <b><b>vcltd_s64</b></b> (int64_t a, int64_t b)<span class="right">Compare signed greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmgt-zero-compare-signed-greater-than-zero-vector">CMGT</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltd_u64" type="checkbox"><label for="vcltd_u64"><div>uint64_t <b><b>vcltd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Compare unsigned higher</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&amp;FP register with the corresponding vector element in the second source SIMD&amp;FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhi-register-compare-unsigned-higher-vector">CMHI</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     test_passed = if cmp_eq then element1 &gt;= element2 else element1 &gt; element2;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vclts_f32" type="checkbox"><label for="vclts_f32"><div>uint32_t <b><b>vclts_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Sd,Sm,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltd_f64" type="checkbox"><label for="vcltd_f64"><div>uint64_t <b><b>vcltd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point compare greater than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmgt-zero-floating-point-compare-greater-than-zero-vector">FCMGT</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltz_s8" type="checkbox"><label for="vcltz_s8"><div>uint8x8_t <b><b>vcltz_s8</b></b> (int8x8_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.8B,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzq_s8" type="checkbox"><label for="vcltzq_s8"><div>uint8x16_t <b><b>vcltzq_s8</b></b> (int8x16_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.16B,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltz_s16" type="checkbox"><label for="vcltz_s16"><div>uint16x4_t <b><b>vcltz_s16</b></b> (int16x4_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.4H,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzq_s16" type="checkbox"><label for="vcltzq_s16"><div>uint16x8_t <b><b>vcltzq_s16</b></b> (int16x8_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.8H,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltz_s32" type="checkbox"><label for="vcltz_s32"><div>uint32x2_t <b><b>vcltz_s32</b></b> (int32x2_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzq_s32" type="checkbox"><label for="vcltzq_s32"><div>uint32x4_t <b><b>vcltzq_s32</b></b> (int32x4_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltz_s64" type="checkbox"><label for="vcltz_s64"><div>uint64x1_t <b><b>vcltz_s64</b></b> (int64x1_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzq_s64" type="checkbox"><label for="vcltzq_s64"><div>uint64x2_t <b><b>vcltzq_s64</b></b> (int64x2_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltz_f32" type="checkbox"><label for="vcltz_f32"><div>uint32x2_t <b><b>vcltz_f32</b></b> (float32x2_t a)<span class="right">Floating-point compare less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmlt-zero-floating-point-compare-less-than-zero-vector">FCMLT</a> Vd.2S,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzq_f32" type="checkbox"><label for="vcltzq_f32"><div>uint32x4_t <b><b>vcltzq_f32</b></b> (float32x4_t a)<span class="right">Floating-point compare less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmlt-zero-floating-point-compare-less-than-zero-vector">FCMLT</a> Vd.4S,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltz_f64" type="checkbox"><label for="vcltz_f64"><div>uint64x1_t <b><b>vcltz_f64</b></b> (float64x1_t a)<span class="right">Floating-point compare less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmlt-zero-floating-point-compare-less-than-zero-vector">FCMLT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzq_f64" type="checkbox"><label for="vcltzq_f64"><div>uint64x2_t <b><b>vcltzq_f64</b></b> (float64x2_t a)<span class="right">Floating-point compare less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmlt-zero-floating-point-compare-less-than-zero-vector">FCMLT</a> Vd.2D,Vn.2D,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzd_s64" type="checkbox"><label for="vcltzd_s64"><div>uint64_t <b><b>vcltzd_s64</b></b> (int64_t a)<span class="right">Compare signed less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&amp;FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmlt-zero-compare-signed-less-than-zero-vector">CMLT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = element &gt; 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = element &gt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = element == 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = element &lt;= 0;
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = element &lt; 0;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzs_f32" type="checkbox"><label for="vcltzs_f32"><div>uint32_t <b><b>vcltzs_f32</b></b> (float32_t a)<span class="right">Floating-point compare less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmlt-zero-floating-point-compare-less-than-zero-vector">FCMLT</a> Sd,Sn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcltzd_f64" type="checkbox"><label for="vcltzd_f64"><div>uint64_t <b><b>vcltzd_f64</b></b> (float64_t a)<span class="right">Floating-point compare less than zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&amp;FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcmlt-zero-floating-point-compare-less-than-zero-vector">FCMLT</a> Dd,Dn,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) zero = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPZero.1" title="function: bits(N) FPZero(bit sign)">FPZero</a>('0');
+ bits(esize) element;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     case comparison of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_LT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcage_f32" type="checkbox"><label for="vcage_f32"><div>uint32x2_t <b><b>vcage_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcageq_f32" type="checkbox"><label for="vcageq_f32"><div>uint32x4_t <b><b>vcageq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcage_f64" type="checkbox"><label for="vcage_f64"><div>uint64x1_t <b><b>vcage_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcageq_f64" type="checkbox"><label for="vcageq_f64"><div>uint64x2_t <b><b>vcageq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcages_f32" type="checkbox"><label for="vcages_f32"><div>uint32_t <b><b>vcages_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcaged_f64" type="checkbox"><label for="vcaged_f64"><div>uint64_t <b><b>vcaged_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcale_f32" type="checkbox"><label for="vcale_f32"><div>uint32x2_t <b><b>vcale_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcaleq_f32" type="checkbox"><label for="vcaleq_f32"><div>uint32x4_t <b><b>vcaleq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcale_f64" type="checkbox"><label for="vcale_f64"><div>uint64x1_t <b><b>vcale_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcaleq_f64" type="checkbox"><label for="vcaleq_f64"><div>uint64x2_t <b><b>vcaleq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Vd.2D,Vm.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcales_f32" type="checkbox"><label for="vcales_f32"><div>uint32_t <b><b>vcales_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Sd,Sm,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcaled_f64" type="checkbox"><label for="vcaled_f64"><div>uint64_t <b><b>vcaled_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point absolute compare greater than or equal</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&amp;FP register with the absolute value of the corresponding floating-point value in the second source SIMD&amp;FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facge-floating-point-absolute-compare-greater-than-or-equal-vector">FACGE</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcagt_f32" type="checkbox"><label for="vcagt_f32"><div>uint32x2_t <b><b>vcagt_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcagtq_f32" type="checkbox"><label for="vcagtq_f32"><div>uint32x4_t <b><b>vcagtq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcagt_f64" type="checkbox"><label for="vcagt_f64"><div>uint64x1_t <b><b>vcagt_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcagtq_f64" type="checkbox"><label for="vcagtq_f64"><div>uint64x2_t <b><b>vcagtq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcagts_f32" type="checkbox"><label for="vcagts_f32"><div>uint32_t <b><b>vcagts_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcagtd_f64" type="checkbox"><label for="vcagtd_f64"><div>uint64_t <b><b>vcagtd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcalt_f32" type="checkbox"><label for="vcalt_f32"><div>uint32x2_t <b><b>vcalt_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Vd.2S,Vm.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcaltq_f32" type="checkbox"><label for="vcaltq_f32"><div>uint32x4_t <b><b>vcaltq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Vd.4S,Vm.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcalt_f64" type="checkbox"><label for="vcalt_f64"><div>uint64x1_t <b><b>vcalt_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcaltq_f64" type="checkbox"><label for="vcaltq_f64"><div>uint64x2_t <b><b>vcaltq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcalts_f32" type="checkbox"><label for="vcalts_f32"><div>uint32_t <b><b>vcalts_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Sd,Sm,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcaltd_f64" type="checkbox"><label for="vcaltd_f64"><div>uint64_t <b><b>vcaltd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point absolute compare greater than</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&amp;FP register with the absolute value of the corresponding vector element in the second source SIMD&amp;FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/facgt-floating-point-absolute-compare-greater-than-vector">FACGT</a> Dd,Dm,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if abs then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element1);
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element2);
+     case cmp of
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_EQ" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareEQ.3" title="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GE" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGE.3" title="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element1, element2, FPCR);
+         when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CompareOp_GT" title="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ,
+  CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPCompareGT.3" title="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtst_s8" type="checkbox"><label for="vtst_s8"><div>uint8x8_t <b><b>vtst_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_s8" type="checkbox"><label for="vtstq_s8"><div>uint8x16_t <b><b>vtstq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_s16" type="checkbox"><label for="vtst_s16"><div>uint16x4_t <b><b>vtst_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_s16" type="checkbox"><label for="vtstq_s16"><div>uint16x8_t <b><b>vtstq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_s32" type="checkbox"><label for="vtst_s32"><div>uint32x2_t <b><b>vtst_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_s32" type="checkbox"><label for="vtstq_s32"><div>uint32x4_t <b><b>vtstq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_u8" type="checkbox"><label for="vtst_u8"><div>uint8x8_t <b><b>vtst_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_u8" type="checkbox"><label for="vtstq_u8"><div>uint8x16_t <b><b>vtstq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_u16" type="checkbox"><label for="vtst_u16"><div>uint16x4_t <b><b>vtst_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_u16" type="checkbox"><label for="vtstq_u16"><div>uint16x8_t <b><b>vtstq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_u32" type="checkbox"><label for="vtst_u32"><div>uint32x2_t <b><b>vtst_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_u32" type="checkbox"><label for="vtstq_u32"><div>uint32x4_t <b><b>vtstq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_p8" type="checkbox"><label for="vtst_p8"><div>uint8x8_t <b><b>vtst_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_p8" type="checkbox"><label for="vtstq_p8"><div>uint8x16_t <b><b>vtstq_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtst_s64" type="checkbox"><label for="vtst_s64"><div>uint64x1_t <b><b>vtst_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_s64" type="checkbox"><label for="vtstq_s64"><div>uint64x2_t <b><b>vtstq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtst_u64" type="checkbox"><label for="vtst_u64"><div>uint64x1_t <b><b>vtst_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_u64" type="checkbox"><label for="vtstq_u64"><div>uint64x2_t <b><b>vtstq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtst_p64" type="checkbox"><label for="vtst_p64"><div>uint64x1_t <b><b>vtst_p64</b></b> (poly64x1_t a, poly64x1_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstq_p64" type="checkbox"><label for="vtstq_p64"><div>uint64x2_t <b><b>vtstq_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtstd_s64" type="checkbox"><label for="vtstd_s64"><div>uint64_t <b><b>vtstd_s64</b></b> (int64_t a, int64_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtstd_u64" type="checkbox"><label for="vtstd_u64"><div>uint64_t <b><b>vtstd_u64</b></b> (uint64_t a, uint64_t b)<span class="right">Compare bitwise test bits nonzero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&amp;FP register, performs an AND with the corresponding vector element in the second source SIMD&amp;FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&amp;FP register to zero.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmtst-compare-bitwise-test-bits-nonzero-vector">CMTST</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ boolean test_passed;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if and_test then
+         test_passed = !<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(element1 AND element2);
+     else
+         test_passed = (element1 == element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabd_s8" type="checkbox"><label for="vabd_s8"><div>int8x8_t <b><b>vabd_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabd-signed-absolute-difference">SABD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_s8" type="checkbox"><label for="vabdq_s8"><div>int8x16_t <b><b>vabdq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabd-signed-absolute-difference">SABD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_s16" type="checkbox"><label for="vabd_s16"><div>int16x4_t <b><b>vabd_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabd-signed-absolute-difference">SABD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_s16" type="checkbox"><label for="vabdq_s16"><div>int16x8_t <b><b>vabdq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabd-signed-absolute-difference">SABD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_s32" type="checkbox"><label for="vabd_s32"><div>int32x2_t <b><b>vabd_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabd-signed-absolute-difference">SABD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_s32" type="checkbox"><label for="vabdq_s32"><div>int32x4_t <b><b>vabdq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabd-signed-absolute-difference">SABD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_u8" type="checkbox"><label for="vabd_u8"><div>uint8x8_t <b><b>vabd_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabd-unsigned-absolute-difference-vector">UABD</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_u8" type="checkbox"><label for="vabdq_u8"><div>uint8x16_t <b><b>vabdq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabd-unsigned-absolute-difference-vector">UABD</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_u16" type="checkbox"><label for="vabd_u16"><div>uint16x4_t <b><b>vabd_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabd-unsigned-absolute-difference-vector">UABD</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_u16" type="checkbox"><label for="vabdq_u16"><div>uint16x8_t <b><b>vabdq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabd-unsigned-absolute-difference-vector">UABD</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_u32" type="checkbox"><label for="vabd_u32"><div>uint32x2_t <b><b>vabd_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabd-unsigned-absolute-difference-vector">UABD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_u32" type="checkbox"><label for="vabdq_u32"><div>uint32x4_t <b><b>vabdq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabd-unsigned-absolute-difference-vector">UABD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_f32" type="checkbox"><label for="vabd_f32"><div>float32x2_t <b><b>vabd_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&amp;FP register, from the corresponding floating-point values in the elements of the first source SIMD&amp;FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabd-floating-point-absolute-difference-vector">FABD</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_f32" type="checkbox"><label for="vabdq_f32"><div>float32x4_t <b><b>vabdq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&amp;FP register, from the corresponding floating-point values in the elements of the first source SIMD&amp;FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabd-floating-point-absolute-difference-vector">FABD</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabd_f64" type="checkbox"><label for="vabd_f64"><div>float64x1_t <b><b>vabd_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&amp;FP register, from the corresponding floating-point values in the elements of the first source SIMD&amp;FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabd-floating-point-absolute-difference-vector">FABD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdq_f64" type="checkbox"><label for="vabdq_f64"><div>float64x2_t <b><b>vabdq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&amp;FP register, from the corresponding floating-point values in the elements of the first source SIMD&amp;FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabd-floating-point-absolute-difference-vector">FABD</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabds_f32" type="checkbox"><label for="vabds_f32"><div>float32_t <b><b>vabds_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&amp;FP register, from the corresponding floating-point values in the elements of the first source SIMD&amp;FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabd-floating-point-absolute-difference-vector">FABD</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdd_f64" type="checkbox"><label for="vabdd_f64"><div>float64_t <b><b>vabdd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point absolute difference</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&amp;FP register, from the corresponding floating-point values in the elements of the first source SIMD&amp;FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabd-floating-point-absolute-difference-vector">FABD</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) diff;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     diff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSub.3" title="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(element1, element2, FPCR);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if abs then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(diff) else diff;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_s8" type="checkbox"><label for="vabdl_s8"><div>int16x8_t <b><b>vabdl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabdl-sabdl2-signed-absolute-difference-long">SABDL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_s16" type="checkbox"><label for="vabdl_s16"><div>int32x4_t <b><b>vabdl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabdl-sabdl2-signed-absolute-difference-long">SABDL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_s32" type="checkbox"><label for="vabdl_s32"><div>int64x2_t <b><b>vabdl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabdl-sabdl2-signed-absolute-difference-long">SABDL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_u8" type="checkbox"><label for="vabdl_u8"><div>uint16x8_t <b><b>vabdl_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabdl-uabdl2-unsigned-absolute-difference-long">UABDL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_u16" type="checkbox"><label for="vabdl_u16"><div>uint32x4_t <b><b>vabdl_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabdl-uabdl2-unsigned-absolute-difference-long">UABDL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_u32" type="checkbox"><label for="vabdl_u32"><div>uint64x2_t <b><b>vabdl_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabdl-uabdl2-unsigned-absolute-difference-long">UABDL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_high_s8" type="checkbox"><label for="vabdl_high_s8"><div>int16x8_t <b><b>vabdl_high_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabdl-sabdl2-signed-absolute-difference-long">SABDL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_high_s16" type="checkbox"><label for="vabdl_high_s16"><div>int32x4_t <b><b>vabdl_high_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabdl-sabdl2-signed-absolute-difference-long">SABDL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_high_s32" type="checkbox"><label for="vabdl_high_s32"><div>int64x2_t <b><b>vabdl_high_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabdl-sabdl2-signed-absolute-difference-long">SABDL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_high_u8" type="checkbox"><label for="vabdl_high_u8"><div>uint16x8_t <b><b>vabdl_high_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabdl-uabdl2-unsigned-absolute-difference-long">UABDL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_high_u16" type="checkbox"><label for="vabdl_high_u16"><div>uint32x4_t <b><b>vabdl_high_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabdl-uabdl2-unsigned-absolute-difference-long">UABDL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabdl_high_u32" type="checkbox"><label for="vabdl_high_u32"><div>uint64x2_t <b><b>vabdl_high_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned absolute difference long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabdl-uabdl2-unsigned-absolute-difference-long">UABDL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaba_s8" type="checkbox"><label for="vaba_s8"><div>int8x8_t <b><b>vaba_s8</b></b> (int8x8_t a, int8x8_t b, int8x8_t c)<span class="right">Signed absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saba-signed-absolute-difference-and-accumulate">SABA</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabaq_s8" type="checkbox"><label for="vabaq_s8"><div>int8x16_t <b><b>vabaq_s8</b></b> (int8x16_t a, int8x16_t b, int8x16_t c)<span class="right">Signed absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saba-signed-absolute-difference-and-accumulate">SABA</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaba_s16" type="checkbox"><label for="vaba_s16"><div>int16x4_t <b><b>vaba_s16</b></b> (int16x4_t a, int16x4_t b, int16x4_t c)<span class="right">Signed absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saba-signed-absolute-difference-and-accumulate">SABA</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabaq_s16" type="checkbox"><label for="vabaq_s16"><div>int16x8_t <b><b>vabaq_s16</b></b> (int16x8_t a, int16x8_t b, int16x8_t c)<span class="right">Signed absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saba-signed-absolute-difference-and-accumulate">SABA</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaba_s32" type="checkbox"><label for="vaba_s32"><div>int32x2_t <b><b>vaba_s32</b></b> (int32x2_t a, int32x2_t b, int32x2_t c)<span class="right">Signed absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saba-signed-absolute-difference-and-accumulate">SABA</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabaq_s32" type="checkbox"><label for="vabaq_s32"><div>int32x4_t <b><b>vabaq_s32</b></b> (int32x4_t a, int32x4_t b, int32x4_t c)<span class="right">Signed absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saba-signed-absolute-difference-and-accumulate">SABA</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaba_u8" type="checkbox"><label for="vaba_u8"><div>uint8x8_t <b><b>vaba_u8</b></b> (uint8x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Unsigned absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaba-unsigned-absolute-difference-and-accumulate">UABA</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabaq_u8" type="checkbox"><label for="vabaq_u8"><div>uint8x16_t <b><b>vabaq_u8</b></b> (uint8x16_t a, uint8x16_t b, uint8x16_t c)<span class="right">Unsigned absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaba-unsigned-absolute-difference-and-accumulate">UABA</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaba_u16" type="checkbox"><label for="vaba_u16"><div>uint16x4_t <b><b>vaba_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Unsigned absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaba-unsigned-absolute-difference-and-accumulate">UABA</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabaq_u16" type="checkbox"><label for="vabaq_u16"><div>uint16x8_t <b><b>vabaq_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x8_t c)<span class="right">Unsigned absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaba-unsigned-absolute-difference-and-accumulate">UABA</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaba_u32" type="checkbox"><label for="vaba_u32"><div>uint32x2_t <b><b>vaba_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Unsigned absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaba-unsigned-absolute-difference-and-accumulate">UABA</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabaq_u32" type="checkbox"><label for="vabaq_u32"><div>uint32x4_t <b><b>vabaq_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x4_t c)<span class="right">Unsigned absolute difference and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&amp;FP register from the corresponding elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaba-unsigned-absolute-difference-and-accumulate">UABA</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ bits(esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_s8" type="checkbox"><label for="vabal_s8"><div>int16x8_t <b><b>vabal_s8</b></b> (int16x8_t a, int8x8_t b, int8x8_t c)<span class="right">Signed absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabal-sabal2-signed-absolute-difference-and-accumulate-long">SABAL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_s16" type="checkbox"><label for="vabal_s16"><div>int32x4_t <b><b>vabal_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t c)<span class="right">Signed absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabal-sabal2-signed-absolute-difference-and-accumulate-long">SABAL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_s32" type="checkbox"><label for="vabal_s32"><div>int64x2_t <b><b>vabal_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t c)<span class="right">Signed absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabal-sabal2-signed-absolute-difference-and-accumulate-long">SABAL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_u8" type="checkbox"><label for="vabal_u8"><div>uint16x8_t <b><b>vabal_u8</b></b> (uint16x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Unsigned absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabal-uabal2-unsigned-absolute-difference-and-accumulate-long">UABAL</a> Vd.8H,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_u16" type="checkbox"><label for="vabal_u16"><div>uint32x4_t <b><b>vabal_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Unsigned absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabal-uabal2-unsigned-absolute-difference-and-accumulate-long">UABAL</a> Vd.4S,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_u32" type="checkbox"><label for="vabal_u32"><div>uint64x2_t <b><b>vabal_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Unsigned absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabal-uabal2-unsigned-absolute-difference-and-accumulate-long">UABAL</a> Vd.2D,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabal_high_s8" type="checkbox"><label for="vabal_high_s8"><div>int16x8_t <b><b>vabal_high_s8</b></b> (int16x8_t a, int8x16_t b, int8x16_t c)<span class="right">Signed absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabal-sabal2-signed-absolute-difference-and-accumulate-long">SABAL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabal_high_s16" type="checkbox"><label for="vabal_high_s16"><div>int32x4_t <b><b>vabal_high_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t c)<span class="right">Signed absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabal-sabal2-signed-absolute-difference-and-accumulate-long">SABAL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabal_high_s32" type="checkbox"><label for="vabal_high_s32"><div>int64x2_t <b><b>vabal_high_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t c)<span class="right">Signed absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sabal-sabal2-signed-absolute-difference-and-accumulate-long">SABAL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabal_high_u8" type="checkbox"><label for="vabal_high_u8"><div>uint16x8_t <b><b>vabal_high_u8</b></b> (uint16x8_t a, uint8x16_t b, uint8x16_t c)<span class="right">Unsigned absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabal-uabal2-unsigned-absolute-difference-and-accumulate-long">UABAL2</a> Vd.8H,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabal_high_u16" type="checkbox"><label for="vabal_high_u16"><div>uint32x4_t <b><b>vabal_high_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x8_t c)<span class="right">Unsigned absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabal-uabal2-unsigned-absolute-difference-and-accumulate-long">UABAL2</a> Vd.4S,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabal_high_u32" type="checkbox"><label for="vabal_high_u32"><div>uint64x2_t <b><b>vabal_high_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x4_t c)<span class="right">Unsigned absolute difference and accumulate long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&amp;FP register from the corresponding vector elements of the first source SIMD&amp;FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uabal-uabal2-unsigned-absolute-difference-and-accumulate-long">UABAL2</a> Vd.2D,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) absdiff;
+ 
+ result = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     absdiff = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element1-element2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmax_s8" type="checkbox"><label for="vmax_s8"><div>int8x8_t <b><b>vmax_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smax-signed-maximum-vector">SMAX</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_s8" type="checkbox"><label for="vmaxq_s8"><div>int8x16_t <b><b>vmaxq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smax-signed-maximum-vector">SMAX</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_s16" type="checkbox"><label for="vmax_s16"><div>int16x4_t <b><b>vmax_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smax-signed-maximum-vector">SMAX</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_s16" type="checkbox"><label for="vmaxq_s16"><div>int16x8_t <b><b>vmaxq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smax-signed-maximum-vector">SMAX</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_s32" type="checkbox"><label for="vmax_s32"><div>int32x2_t <b><b>vmax_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smax-signed-maximum-vector">SMAX</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_s32" type="checkbox"><label for="vmaxq_s32"><div>int32x4_t <b><b>vmaxq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smax-signed-maximum-vector">SMAX</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_u8" type="checkbox"><label for="vmax_u8"><div>uint8x8_t <b><b>vmax_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umax-unsigned-maximum-vector">UMAX</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_u8" type="checkbox"><label for="vmaxq_u8"><div>uint8x16_t <b><b>vmaxq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umax-unsigned-maximum-vector">UMAX</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_u16" type="checkbox"><label for="vmax_u16"><div>uint16x4_t <b><b>vmax_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umax-unsigned-maximum-vector">UMAX</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_u16" type="checkbox"><label for="vmaxq_u16"><div>uint16x8_t <b><b>vmaxq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umax-unsigned-maximum-vector">UMAX</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_u32" type="checkbox"><label for="vmax_u32"><div>uint32x2_t <b><b>vmax_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umax-unsigned-maximum-vector">UMAX</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_u32" type="checkbox"><label for="vmaxq_u32"><div>uint32x4_t <b><b>vmaxq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umax-unsigned-maximum-vector">UMAX</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_f32" type="checkbox"><label for="vmax_f32"><div>float32x2_t <b><b>vmax_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmax-vector-floating-point-maximum-vector">FMAX</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_f32" type="checkbox"><label for="vmaxq_f32"><div>float32x4_t <b><b>vmaxq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmax-vector-floating-point-maximum-vector">FMAX</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmax_f64" type="checkbox"><label for="vmax_f64"><div>float64x1_t <b><b>vmax_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmax-vector-floating-point-maximum-vector">FMAX</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxq_f64" type="checkbox"><label for="vmaxq_f64"><div>float64x2_t <b><b>vmaxq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point maximum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmax-vector-floating-point-maximum-vector">FMAX</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmin_s8" type="checkbox"><label for="vmin_s8"><div>int8x8_t <b><b>vmin_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smin-signed-minimum-vector">SMIN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_s8" type="checkbox"><label for="vminq_s8"><div>int8x16_t <b><b>vminq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smin-signed-minimum-vector">SMIN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_s16" type="checkbox"><label for="vmin_s16"><div>int16x4_t <b><b>vmin_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smin-signed-minimum-vector">SMIN</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_s16" type="checkbox"><label for="vminq_s16"><div>int16x8_t <b><b>vminq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smin-signed-minimum-vector">SMIN</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_s32" type="checkbox"><label for="vmin_s32"><div>int32x2_t <b><b>vmin_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smin-signed-minimum-vector">SMIN</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_s32" type="checkbox"><label for="vminq_s32"><div>int32x4_t <b><b>vminq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smin-signed-minimum-vector">SMIN</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_u8" type="checkbox"><label for="vmin_u8"><div>uint8x8_t <b><b>vmin_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umin-unsigned-minimum-vector">UMIN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_u8" type="checkbox"><label for="vminq_u8"><div>uint8x16_t <b><b>vminq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umin-unsigned-minimum-vector">UMIN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_u16" type="checkbox"><label for="vmin_u16"><div>uint16x4_t <b><b>vmin_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umin-unsigned-minimum-vector">UMIN</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_u16" type="checkbox"><label for="vminq_u16"><div>uint16x8_t <b><b>vminq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umin-unsigned-minimum-vector">UMIN</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_u32" type="checkbox"><label for="vmin_u32"><div>uint32x2_t <b><b>vmin_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umin-unsigned-minimum-vector">UMIN</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_u32" type="checkbox"><label for="vminq_u32"><div>uint32x4_t <b><b>vminq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umin-unsigned-minimum-vector">UMIN</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_f32" type="checkbox"><label for="vmin_f32"><div>float32x2_t <b><b>vmin_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmin-vector-floating-point-minimum-vector">FMIN</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminq_f32" type="checkbox"><label for="vminq_f32"><div>float32x4_t <b><b>vminq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmin-vector-floating-point-minimum-vector">FMIN</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmin_f64" type="checkbox"><label for="vmin_f64"><div>float64x1_t <b><b>vmin_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmin-vector-floating-point-minimum-vector">FMIN</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminq_f64" type="checkbox"><label for="vminq_f64"><div>float64x2_t <b><b>vminq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point minimum</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&amp;FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmin-vector-floating-point-minimum-vector">FMIN</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnm_f32" type="checkbox"><label for="vmaxnm_f32"><div>float32x2_t <b><b>vmaxnm_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point maximum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnm-vector-floating-point-maximum-number-vector">FMAXNM</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnmq_f32" type="checkbox"><label for="vmaxnmq_f32"><div>float32x4_t <b><b>vmaxnmq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point maximum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnm-vector-floating-point-maximum-number-vector">FMAXNM</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnm_f64" type="checkbox"><label for="vmaxnm_f64"><div>float64x1_t <b><b>vmaxnm_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point maximum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnm-vector-floating-point-maximum-number-vector">FMAXNM</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnmq_f64" type="checkbox"><label for="vmaxnmq_f64"><div>float64x2_t <b><b>vmaxnmq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point maximum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnm-vector-floating-point-maximum-number-vector">FMAXNM</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminnm_f32" type="checkbox"><label for="vminnm_f32"><div>float32x2_t <b><b>vminnm_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point minimum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnm-vector-floating-point-minimum-number-vector">FMINNM</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminnmq_f32" type="checkbox"><label for="vminnmq_f32"><div>float32x4_t <b><b>vminnmq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point minimum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnm-vector-floating-point-minimum-number-vector">FMINNM</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vminnm_f64" type="checkbox"><label for="vminnm_f64"><div>float64x1_t <b><b>vminnm_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point minimum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnm-vector-floating-point-minimum-number-vector">FMINNM</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminnmq_f64" type="checkbox"><label for="vminnmq_f64"><div>float64x2_t <b><b>vminnmq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point minimum number</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&amp;FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnm-vector-floating-point-minimum-number-vector">FMINNM</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshl_s8" type="checkbox"><label for="vshl_s8"><div>int8x8_t <b><b>vshl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_s8" type="checkbox"><label for="vshlq_s8"><div>int8x16_t <b><b>vshlq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_s16" type="checkbox"><label for="vshl_s16"><div>int16x4_t <b><b>vshl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_s16" type="checkbox"><label for="vshlq_s16"><div>int16x8_t <b><b>vshlq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_s32" type="checkbox"><label for="vshl_s32"><div>int32x2_t <b><b>vshl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_s32" type="checkbox"><label for="vshlq_s32"><div>int32x4_t <b><b>vshlq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_s64" type="checkbox"><label for="vshl_s64"><div>int64x1_t <b><b>vshl_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_s64" type="checkbox"><label for="vshlq_s64"><div>int64x2_t <b><b>vshlq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_u8" type="checkbox"><label for="vshl_u8"><div>uint8x8_t <b><b>vshl_u8</b></b> (uint8x8_t a, int8x8_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_u8" type="checkbox"><label for="vshlq_u8"><div>uint8x16_t <b><b>vshlq_u8</b></b> (uint8x16_t a, int8x16_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_u16" type="checkbox"><label for="vshl_u16"><div>uint16x4_t <b><b>vshl_u16</b></b> (uint16x4_t a, int16x4_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_u16" type="checkbox"><label for="vshlq_u16"><div>uint16x8_t <b><b>vshlq_u16</b></b> (uint16x8_t a, int16x8_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_u32" type="checkbox"><label for="vshl_u32"><div>uint32x2_t <b><b>vshl_u32</b></b> (uint32x2_t a, int32x2_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_u32" type="checkbox"><label for="vshlq_u32"><div>uint32x4_t <b><b>vshlq_u32</b></b> (uint32x4_t a, int32x4_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_u64" type="checkbox"><label for="vshl_u64"><div>uint64x1_t <b><b>vshl_u64</b></b> (uint64x1_t a, int64x1_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_u64" type="checkbox"><label for="vshlq_u64"><div>uint64x2_t <b><b>vshlq_u64</b></b> (uint64x2_t a, int64x2_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshld_s64" type="checkbox"><label for="vshld_s64"><div>int64_t <b><b>vshld_s64</b></b> (int64_t a, int64_t b)<span class="right">Signed shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshl-signed-shift-left-register">SSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshld_u64" type="checkbox"><label for="vshld_u64"><div>uint64_t <b><b>vshld_u64</b></b> (uint64_t a, int64_t b)<span class="right">Unsigned shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushl-unsigned-shift-left-register">USHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_s8" type="checkbox"><label for="vqshl_s8"><div>int8x8_t <b><b>vqshl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_s8" type="checkbox"><label for="vqshlq_s8"><div>int8x16_t <b><b>vqshlq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_s16" type="checkbox"><label for="vqshl_s16"><div>int16x4_t <b><b>vqshl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_s16" type="checkbox"><label for="vqshlq_s16"><div>int16x8_t <b><b>vqshlq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_s32" type="checkbox"><label for="vqshl_s32"><div>int32x2_t <b><b>vqshl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_s32" type="checkbox"><label for="vqshlq_s32"><div>int32x4_t <b><b>vqshlq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_s64" type="checkbox"><label for="vqshl_s64"><div>int64x1_t <b><b>vqshl_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_s64" type="checkbox"><label for="vqshlq_s64"><div>int64x2_t <b><b>vqshlq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_u8" type="checkbox"><label for="vqshl_u8"><div>uint8x8_t <b><b>vqshl_u8</b></b> (uint8x8_t a, int8x8_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_u8" type="checkbox"><label for="vqshlq_u8"><div>uint8x16_t <b><b>vqshlq_u8</b></b> (uint8x16_t a, int8x16_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_u16" type="checkbox"><label for="vqshl_u16"><div>uint16x4_t <b><b>vqshl_u16</b></b> (uint16x4_t a, int16x4_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_u16" type="checkbox"><label for="vqshlq_u16"><div>uint16x8_t <b><b>vqshlq_u16</b></b> (uint16x8_t a, int16x8_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_u32" type="checkbox"><label for="vqshl_u32"><div>uint32x2_t <b><b>vqshl_u32</b></b> (uint32x2_t a, int32x2_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_u32" type="checkbox"><label for="vqshlq_u32"><div>uint32x4_t <b><b>vqshlq_u32</b></b> (uint32x4_t a, int32x4_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_u64" type="checkbox"><label for="vqshl_u64"><div>uint64x1_t <b><b>vqshl_u64</b></b> (uint64x1_t a, int64x1_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_u64" type="checkbox"><label for="vqshlq_u64"><div>uint64x2_t <b><b>vqshlq_u64</b></b> (uint64x2_t a, int64x2_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlb_s8" type="checkbox"><label for="vqshlb_s8"><div>int8_t <b><b>vqshlb_s8</b></b> (int8_t a, int8_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlh_s16" type="checkbox"><label for="vqshlh_s16"><div>int16_t <b><b>vqshlh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshls_s32" type="checkbox"><label for="vqshls_s32"><div>int32_t <b><b>vqshls_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshld_s64" type="checkbox"><label for="vqshld_s64"><div>int64_t <b><b>vqshld_s64</b></b> (int64_t a, int64_t b)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlb_u8" type="checkbox"><label for="vqshlb_u8"><div>uint8_t <b><b>vqshlb_u8</b></b> (uint8_t a, int8_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlh_u16" type="checkbox"><label for="vqshlh_u16"><div>uint16_t <b><b>vqshlh_u16</b></b> (uint16_t a, int16_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshls_u32" type="checkbox"><label for="vqshls_u32"><div>uint32_t <b><b>vqshls_u32</b></b> (uint32_t a, int32_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshld_u64" type="checkbox"><label for="vqshld_u64"><div>uint64_t <b><b>vqshld_u64</b></b> (uint64_t a, int64_t b)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_s8" type="checkbox"><label for="vrshl_s8"><div>int8x8_t <b><b>vrshl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_s8" type="checkbox"><label for="vrshlq_s8"><div>int8x16_t <b><b>vrshlq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_s16" type="checkbox"><label for="vrshl_s16"><div>int16x4_t <b><b>vrshl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_s16" type="checkbox"><label for="vrshlq_s16"><div>int16x8_t <b><b>vrshlq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_s32" type="checkbox"><label for="vrshl_s32"><div>int32x2_t <b><b>vrshl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_s32" type="checkbox"><label for="vrshlq_s32"><div>int32x4_t <b><b>vrshlq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_s64" type="checkbox"><label for="vrshl_s64"><div>int64x1_t <b><b>vrshl_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_s64" type="checkbox"><label for="vrshlq_s64"><div>int64x2_t <b><b>vrshlq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_u8" type="checkbox"><label for="vrshl_u8"><div>uint8x8_t <b><b>vrshl_u8</b></b> (uint8x8_t a, int8x8_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_u8" type="checkbox"><label for="vrshlq_u8"><div>uint8x16_t <b><b>vrshlq_u8</b></b> (uint8x16_t a, int8x16_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_u16" type="checkbox"><label for="vrshl_u16"><div>uint16x4_t <b><b>vrshl_u16</b></b> (uint16x4_t a, int16x4_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_u16" type="checkbox"><label for="vrshlq_u16"><div>uint16x8_t <b><b>vrshlq_u16</b></b> (uint16x8_t a, int16x8_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_u32" type="checkbox"><label for="vrshl_u32"><div>uint32x2_t <b><b>vrshl_u32</b></b> (uint32x2_t a, int32x2_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_u32" type="checkbox"><label for="vrshlq_u32"><div>uint32x4_t <b><b>vrshlq_u32</b></b> (uint32x4_t a, int32x4_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshl_u64" type="checkbox"><label for="vrshl_u64"><div>uint64x1_t <b><b>vrshl_u64</b></b> (uint64x1_t a, int64x1_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshlq_u64" type="checkbox"><label for="vrshlq_u64"><div>uint64x2_t <b><b>vrshlq_u64</b></b> (uint64x2_t a, int64x2_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshld_s64" type="checkbox"><label for="vrshld_s64"><div>int64_t <b><b>vrshld_s64</b></b> (int64_t a, int64_t b)<span class="right">Signed rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshl-signed-rounding-shift-left-register">SRSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshld_u64" type="checkbox"><label for="vrshld_u64"><div>uint64_t <b><b>vrshld_u64</b></b> (uint64_t a, int64_t b)<span class="right">Unsigned rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshl-unsigned-rounding-shift-left-register">URSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_s8" type="checkbox"><label for="vqrshl_s8"><div>int8x8_t <b><b>vqrshl_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_s8" type="checkbox"><label for="vqrshlq_s8"><div>int8x16_t <b><b>vqrshlq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_s16" type="checkbox"><label for="vqrshl_s16"><div>int16x4_t <b><b>vqrshl_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_s16" type="checkbox"><label for="vqrshlq_s16"><div>int16x8_t <b><b>vqrshlq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_s32" type="checkbox"><label for="vqrshl_s32"><div>int32x2_t <b><b>vqrshl_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_s32" type="checkbox"><label for="vqrshlq_s32"><div>int32x4_t <b><b>vqrshlq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_s64" type="checkbox"><label for="vqrshl_s64"><div>int64x1_t <b><b>vqrshl_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_s64" type="checkbox"><label for="vqrshlq_s64"><div>int64x2_t <b><b>vqrshlq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_u8" type="checkbox"><label for="vqrshl_u8"><div>uint8x8_t <b><b>vqrshl_u8</b></b> (uint8x8_t a, int8x8_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_u8" type="checkbox"><label for="vqrshlq_u8"><div>uint8x16_t <b><b>vqrshlq_u8</b></b> (uint8x16_t a, int8x16_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_u16" type="checkbox"><label for="vqrshl_u16"><div>uint16x4_t <b><b>vqrshl_u16</b></b> (uint16x4_t a, int16x4_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_u16" type="checkbox"><label for="vqrshlq_u16"><div>uint16x8_t <b><b>vqrshlq_u16</b></b> (uint16x8_t a, int16x8_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_u32" type="checkbox"><label for="vqrshl_u32"><div>uint32x2_t <b><b>vqrshl_u32</b></b> (uint32x2_t a, int32x2_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_u32" type="checkbox"><label for="vqrshlq_u32"><div>uint32x4_t <b><b>vqrshlq_u32</b></b> (uint32x4_t a, int32x4_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshl_u64" type="checkbox"><label for="vqrshl_u64"><div>uint64x1_t <b><b>vqrshl_u64</b></b> (uint64x1_t a, int64x1_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlq_u64" type="checkbox"><label for="vqrshlq_u64"><div>uint64x2_t <b><b>vqrshlq_u64</b></b> (uint64x2_t a, int64x2_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlb_s8" type="checkbox"><label for="vqrshlb_s8"><div>int8_t <b><b>vqrshlb_s8</b></b> (int8_t a, int8_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlh_s16" type="checkbox"><label for="vqrshlh_s16"><div>int16_t <b><b>vqrshlh_s16</b></b> (int16_t a, int16_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshls_s32" type="checkbox"><label for="vqrshls_s32"><div>int32_t <b><b>vqrshls_s32</b></b> (int32_t a, int32_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshld_s64" type="checkbox"><label for="vqrshld_s64"><div>int64_t <b><b>vqrshld_s64</b></b> (int64_t a, int64_t b)<span class="right">Signed saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&amp;FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshl-signed-saturating-rounding-shift-left-register">SQRSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlb_u8" type="checkbox"><label for="vqrshlb_u8"><div>uint8_t <b><b>vqrshlb_u8</b></b> (uint8_t a, int8_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Bd,Bn,Bm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ b &rarr; Bm </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshlh_u16" type="checkbox"><label for="vqrshlh_u16"><div>uint16_t <b><b>vqrshlh_u16</b></b> (uint16_t a, int16_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Hd,Hn,Hm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ b &rarr; Hm </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshls_u32" type="checkbox"><label for="vqrshls_u32"><div>uint32_t <b><b>vqrshls_u32</b></b> (uint32_t a, int32_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshld_u64" type="checkbox"><label for="vqrshld_u64"><div>uint64_t <b><b>vqrshld_u64</b></b> (uint64_t a, int64_t b)<span class="right">Unsigned saturating rounding shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&amp;FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshl-unsigned-saturating-rounding-shift-left-register">UQRSHL</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_s8" type="checkbox"><label for="vshr_n_s8"><div>int8x8_t <b><b>vshr_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_s8" type="checkbox"><label for="vshrq_n_s8"><div>int8x16_t <b><b>vshrq_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_s16" type="checkbox"><label for="vshr_n_s16"><div>int16x4_t <b><b>vshr_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_s16" type="checkbox"><label for="vshrq_n_s16"><div>int16x8_t <b><b>vshrq_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_s32" type="checkbox"><label for="vshr_n_s32"><div>int32x2_t <b><b>vshr_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_s32" type="checkbox"><label for="vshrq_n_s32"><div>int32x4_t <b><b>vshrq_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_s64" type="checkbox"><label for="vshr_n_s64"><div>int64x1_t <b><b>vshr_n_s64</b></b> (int64x1_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_s64" type="checkbox"><label for="vshrq_n_s64"><div>int64x2_t <b><b>vshrq_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_u8" type="checkbox"><label for="vshr_n_u8"><div>uint8x8_t <b><b>vshr_n_u8</b></b> (uint8x8_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_u8" type="checkbox"><label for="vshrq_n_u8"><div>uint8x16_t <b><b>vshrq_n_u8</b></b> (uint8x16_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_u16" type="checkbox"><label for="vshr_n_u16"><div>uint16x4_t <b><b>vshr_n_u16</b></b> (uint16x4_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_u16" type="checkbox"><label for="vshrq_n_u16"><div>uint16x8_t <b><b>vshrq_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_u32" type="checkbox"><label for="vshr_n_u32"><div>uint32x2_t <b><b>vshr_n_u32</b></b> (uint32x2_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_u32" type="checkbox"><label for="vshrq_n_u32"><div>uint32x4_t <b><b>vshrq_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshr_n_u64" type="checkbox"><label for="vshr_n_u64"><div>uint64x1_t <b><b>vshr_n_u64</b></b> (uint64x1_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrq_n_u64" type="checkbox"><label for="vshrq_n_u64"><div>uint64x2_t <b><b>vshrq_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrd_n_s64" type="checkbox"><label for="vshrd_n_s64"><div>int64_t <b><b>vshrd_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshr-signed-shift-right-immediate">SSHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrd_n_u64" type="checkbox"><label for="vshrd_n_u64"><div>uint64_t <b><b>vshrd_n_u64</b></b> (uint64_t a, const int n)<span class="right">Unsigned shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushr-unsigned-shift-right-immediate">USHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_s8" type="checkbox"><label for="vshl_n_s8"><div>int8x8_t <b><b>vshl_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_s8" type="checkbox"><label for="vshlq_n_s8"><div>int8x16_t <b><b>vshlq_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_s16" type="checkbox"><label for="vshl_n_s16"><div>int16x4_t <b><b>vshl_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_s16" type="checkbox"><label for="vshlq_n_s16"><div>int16x8_t <b><b>vshlq_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_s32" type="checkbox"><label for="vshl_n_s32"><div>int32x2_t <b><b>vshl_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_s32" type="checkbox"><label for="vshlq_n_s32"><div>int32x4_t <b><b>vshlq_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_s64" type="checkbox"><label for="vshl_n_s64"><div>int64x1_t <b><b>vshl_n_s64</b></b> (int64x1_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_s64" type="checkbox"><label for="vshlq_n_s64"><div>int64x2_t <b><b>vshlq_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_u8" type="checkbox"><label for="vshl_n_u8"><div>uint8x8_t <b><b>vshl_n_u8</b></b> (uint8x8_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_u8" type="checkbox"><label for="vshlq_n_u8"><div>uint8x16_t <b><b>vshlq_n_u8</b></b> (uint8x16_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_u16" type="checkbox"><label for="vshl_n_u16"><div>uint16x4_t <b><b>vshl_n_u16</b></b> (uint16x4_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_u16" type="checkbox"><label for="vshlq_n_u16"><div>uint16x8_t <b><b>vshlq_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_u32" type="checkbox"><label for="vshl_n_u32"><div>uint32x2_t <b><b>vshl_n_u32</b></b> (uint32x2_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_u32" type="checkbox"><label for="vshlq_n_u32"><div>uint32x4_t <b><b>vshlq_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshl_n_u64" type="checkbox"><label for="vshl_n_u64"><div>uint64x1_t <b><b>vshl_n_u64</b></b> (uint64x1_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshlq_n_u64" type="checkbox"><label for="vshlq_n_u64"><div>uint64x2_t <b><b>vshlq_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshld_n_s64" type="checkbox"><label for="vshld_n_s64"><div>int64_t <b><b>vshld_n_s64</b></b> (int64_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshld_n_u64" type="checkbox"><label for="vshld_n_u64"><div>uint64_t <b><b>vshld_n_u64</b></b> (uint64_t a, const int n)<span class="right">Shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shl-shift-left-immediate">SHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_s8" type="checkbox"><label for="vrshr_n_s8"><div>int8x8_t <b><b>vrshr_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_s8" type="checkbox"><label for="vrshrq_n_s8"><div>int8x16_t <b><b>vrshrq_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_s16" type="checkbox"><label for="vrshr_n_s16"><div>int16x4_t <b><b>vrshr_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_s16" type="checkbox"><label for="vrshrq_n_s16"><div>int16x8_t <b><b>vrshrq_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_s32" type="checkbox"><label for="vrshr_n_s32"><div>int32x2_t <b><b>vrshr_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_s32" type="checkbox"><label for="vrshrq_n_s32"><div>int32x4_t <b><b>vrshrq_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_s64" type="checkbox"><label for="vrshr_n_s64"><div>int64x1_t <b><b>vrshr_n_s64</b></b> (int64x1_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_s64" type="checkbox"><label for="vrshrq_n_s64"><div>int64x2_t <b><b>vrshrq_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_u8" type="checkbox"><label for="vrshr_n_u8"><div>uint8x8_t <b><b>vrshr_n_u8</b></b> (uint8x8_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_u8" type="checkbox"><label for="vrshrq_n_u8"><div>uint8x16_t <b><b>vrshrq_n_u8</b></b> (uint8x16_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_u16" type="checkbox"><label for="vrshr_n_u16"><div>uint16x4_t <b><b>vrshr_n_u16</b></b> (uint16x4_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_u16" type="checkbox"><label for="vrshrq_n_u16"><div>uint16x8_t <b><b>vrshrq_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_u32" type="checkbox"><label for="vrshr_n_u32"><div>uint32x2_t <b><b>vrshr_n_u32</b></b> (uint32x2_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_u32" type="checkbox"><label for="vrshrq_n_u32"><div>uint32x4_t <b><b>vrshrq_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshr_n_u64" type="checkbox"><label for="vrshr_n_u64"><div>uint64x1_t <b><b>vrshr_n_u64</b></b> (uint64x1_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrq_n_u64" type="checkbox"><label for="vrshrq_n_u64"><div>uint64x2_t <b><b>vrshrq_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrd_n_s64" type="checkbox"><label for="vrshrd_n_s64"><div>int64_t <b><b>vrshrd_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srshr-signed-rounding-shift-right-immediate">SRSHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrd_n_u64" type="checkbox"><label for="vrshrd_n_u64"><div>uint64_t <b><b>vrshrd_n_u64</b></b> (uint64_t a, const int n)<span class="right">Unsigned rounding shift right</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USHR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urshr-unsigned-rounding-shift-right-immediate">URSHR</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_s8" type="checkbox"><label for="vsra_n_s8"><div>int8x8_t <b><b>vsra_n_s8</b></b> (int8x8_t a, int8x8_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_s8" type="checkbox"><label for="vsraq_n_s8"><div>int8x16_t <b><b>vsraq_n_s8</b></b> (int8x16_t a, int8x16_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_s16" type="checkbox"><label for="vsra_n_s16"><div>int16x4_t <b><b>vsra_n_s16</b></b> (int16x4_t a, int16x4_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_s16" type="checkbox"><label for="vsraq_n_s16"><div>int16x8_t <b><b>vsraq_n_s16</b></b> (int16x8_t a, int16x8_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_s32" type="checkbox"><label for="vsra_n_s32"><div>int32x2_t <b><b>vsra_n_s32</b></b> (int32x2_t a, int32x2_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_s32" type="checkbox"><label for="vsraq_n_s32"><div>int32x4_t <b><b>vsraq_n_s32</b></b> (int32x4_t a, int32x4_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_s64" type="checkbox"><label for="vsra_n_s64"><div>int64x1_t <b><b>vsra_n_s64</b></b> (int64x1_t a, int64x1_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_s64" type="checkbox"><label for="vsraq_n_s64"><div>int64x2_t <b><b>vsraq_n_s64</b></b> (int64x2_t a, int64x2_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_u8" type="checkbox"><label for="vsra_n_u8"><div>uint8x8_t <b><b>vsra_n_u8</b></b> (uint8x8_t a, uint8x8_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_u8" type="checkbox"><label for="vsraq_n_u8"><div>uint8x16_t <b><b>vsraq_n_u8</b></b> (uint8x16_t a, uint8x16_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_u16" type="checkbox"><label for="vsra_n_u16"><div>uint16x4_t <b><b>vsra_n_u16</b></b> (uint16x4_t a, uint16x4_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_u16" type="checkbox"><label for="vsraq_n_u16"><div>uint16x8_t <b><b>vsraq_n_u16</b></b> (uint16x8_t a, uint16x8_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_u32" type="checkbox"><label for="vsra_n_u32"><div>uint32x2_t <b><b>vsra_n_u32</b></b> (uint32x2_t a, uint32x2_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_u32" type="checkbox"><label for="vsraq_n_u32"><div>uint32x4_t <b><b>vsraq_n_u32</b></b> (uint32x4_t a, uint32x4_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsra_n_u64" type="checkbox"><label for="vsra_n_u64"><div>uint64x1_t <b><b>vsra_n_u64</b></b> (uint64x1_t a, uint64x1_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsraq_n_u64" type="checkbox"><label for="vsraq_n_u64"><div>uint64x2_t <b><b>vsraq_n_u64</b></b> (uint64x2_t a, uint64x2_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsrad_n_s64" type="checkbox"><label for="vsrad_n_s64"><div>int64_t <b><b>vsrad_n_s64</b></b> (int64_t a, int64_t b, const int n)<span class="right">Signed shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SRSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ssra-signed-shift-right-and-accumulate-immediate">SSRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsrad_n_u64" type="checkbox"><label for="vsrad_n_u64"><div>uint64_t <b><b>vsrad_n_u64</b></b> (uint64_t a, uint64_t b, const int n)<span class="right">Unsigned shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">URSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/usra-unsigned-shift-right-and-accumulate-immediate">USRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_s8" type="checkbox"><label for="vrsra_n_s8"><div>int8x8_t <b><b>vrsra_n_s8</b></b> (int8x8_t a, int8x8_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_s8" type="checkbox"><label for="vrsraq_n_s8"><div>int8x16_t <b><b>vrsraq_n_s8</b></b> (int8x16_t a, int8x16_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_s16" type="checkbox"><label for="vrsra_n_s16"><div>int16x4_t <b><b>vrsra_n_s16</b></b> (int16x4_t a, int16x4_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_s16" type="checkbox"><label for="vrsraq_n_s16"><div>int16x8_t <b><b>vrsraq_n_s16</b></b> (int16x8_t a, int16x8_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_s32" type="checkbox"><label for="vrsra_n_s32"><div>int32x2_t <b><b>vrsra_n_s32</b></b> (int32x2_t a, int32x2_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_s32" type="checkbox"><label for="vrsraq_n_s32"><div>int32x4_t <b><b>vrsraq_n_s32</b></b> (int32x4_t a, int32x4_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_s64" type="checkbox"><label for="vrsra_n_s64"><div>int64x1_t <b><b>vrsra_n_s64</b></b> (int64x1_t a, int64x1_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_s64" type="checkbox"><label for="vrsraq_n_s64"><div>int64x2_t <b><b>vrsraq_n_s64</b></b> (int64x2_t a, int64x2_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_u8" type="checkbox"><label for="vrsra_n_u8"><div>uint8x8_t <b><b>vrsra_n_u8</b></b> (uint8x8_t a, uint8x8_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_u8" type="checkbox"><label for="vrsraq_n_u8"><div>uint8x16_t <b><b>vrsraq_n_u8</b></b> (uint8x16_t a, uint8x16_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_u16" type="checkbox"><label for="vrsra_n_u16"><div>uint16x4_t <b><b>vrsra_n_u16</b></b> (uint16x4_t a, uint16x4_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_u16" type="checkbox"><label for="vrsraq_n_u16"><div>uint16x8_t <b><b>vrsraq_n_u16</b></b> (uint16x8_t a, uint16x8_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_u32" type="checkbox"><label for="vrsra_n_u32"><div>uint32x2_t <b><b>vrsra_n_u32</b></b> (uint32x2_t a, uint32x2_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_u32" type="checkbox"><label for="vrsraq_n_u32"><div>uint32x4_t <b><b>vrsraq_n_u32</b></b> (uint32x4_t a, uint32x4_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsra_n_u64" type="checkbox"><label for="vrsra_n_u64"><div>uint64x1_t <b><b>vrsra_n_u64</b></b> (uint64x1_t a, uint64x1_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsraq_n_u64" type="checkbox"><label for="vrsraq_n_u64"><div>uint64x2_t <b><b>vrsraq_n_u64</b></b> (uint64x2_t a, uint64x2_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsrad_n_s64" type="checkbox"><label for="vrsrad_n_s64"><div>int64_t <b><b>vrsrad_n_s64</b></b> (int64_t a, int64_t b, const int n)<span class="right">Signed rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SSRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/srsra-signed-rounding-shift-right-and-accumulate-immediate">SRSRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsrad_n_u64" type="checkbox"><label for="vrsrad_n_u64"><div>uint64_t <b><b>vrsrad_n_u64</b></b> (uint64_t a, uint64_t b, const int n)<span class="right">Unsigned rounding shift right and accumulate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">USRA</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursra-unsigned-rounding-shift-right-and-accumulate-immediate">URSRA</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2;
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ operand2 = if accumulate then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] + element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_s8" type="checkbox"><label for="vqshl_n_s8"><div>int8x8_t <b><b>vqshl_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_s8" type="checkbox"><label for="vqshlq_n_s8"><div>int8x16_t <b><b>vqshlq_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_s16" type="checkbox"><label for="vqshl_n_s16"><div>int16x4_t <b><b>vqshl_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_s16" type="checkbox"><label for="vqshlq_n_s16"><div>int16x8_t <b><b>vqshlq_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_s32" type="checkbox"><label for="vqshl_n_s32"><div>int32x2_t <b><b>vqshl_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_s32" type="checkbox"><label for="vqshlq_n_s32"><div>int32x4_t <b><b>vqshlq_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_s64" type="checkbox"><label for="vqshl_n_s64"><div>int64x1_t <b><b>vqshl_n_s64</b></b> (int64x1_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_s64" type="checkbox"><label for="vqshlq_n_s64"><div>int64x2_t <b><b>vqshlq_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_u8" type="checkbox"><label for="vqshl_n_u8"><div>uint8x8_t <b><b>vqshl_n_u8</b></b> (uint8x8_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_u8" type="checkbox"><label for="vqshlq_n_u8"><div>uint8x16_t <b><b>vqshlq_n_u8</b></b> (uint8x16_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_u16" type="checkbox"><label for="vqshl_n_u16"><div>uint16x4_t <b><b>vqshl_n_u16</b></b> (uint16x4_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_u16" type="checkbox"><label for="vqshlq_n_u16"><div>uint16x8_t <b><b>vqshlq_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_u32" type="checkbox"><label for="vqshl_n_u32"><div>uint32x2_t <b><b>vqshl_n_u32</b></b> (uint32x2_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_u32" type="checkbox"><label for="vqshlq_n_u32"><div>uint32x4_t <b><b>vqshlq_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshl_n_u64" type="checkbox"><label for="vqshl_n_u64"><div>uint64x1_t <b><b>vqshl_n_u64</b></b> (uint64x1_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlq_n_u64" type="checkbox"><label for="vqshlq_n_u64"><div>uint64x2_t <b><b>vqshlq_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlb_n_s8" type="checkbox"><label for="vqshlb_n_s8"><div>int8_t <b><b>vqshlb_n_s8</b></b> (int8_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Bd,Bn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlh_n_s16" type="checkbox"><label for="vqshlh_n_s16"><div>int16_t <b><b>vqshlh_n_s16</b></b> (int16_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Hd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshls_n_s32" type="checkbox"><label for="vqshls_n_s32"><div>int32_t <b><b>vqshls_n_s32</b></b> (int32_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshld_n_s64" type="checkbox"><label for="vqshld_n_s64"><div>int64_t <b><b>vqshld_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshl-register-signed-saturating-shift-left-register">SQSHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlb_n_u8" type="checkbox"><label for="vqshlb_n_u8"><div>uint8_t <b><b>vqshlb_n_u8</b></b> (uint8_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Bd,Bn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlh_n_u16" type="checkbox"><label for="vqshlh_n_u16"><div>uint16_t <b><b>vqshlh_n_u16</b></b> (uint16_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Hd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshls_n_u32" type="checkbox"><label for="vqshls_n_u32"><div>uint32_t <b><b>vqshls_n_u32</b></b> (uint32_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshld_n_u64" type="checkbox"><label for="vqshld_n_u64"><div>uint64_t <b><b>vqshld_n_u64</b></b> (uint64_t a, const int n)<span class="right">Unsigned saturating shift left</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&amp;FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&amp;FP register, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshl-register-unsigned-saturating-shift-left-register">UQSHL</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer round_const = 0;
+ integer shift;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     shift = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]&lt;7:0&gt;);
+     if rounding then
+         round_const = 1 &lt;&lt; (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned) + round_const) &lt;&lt; shift;
+     if saturating then
+         (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+         if sat then FPSR.QC = '1';
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlu_n_s8" type="checkbox"><label for="vqshlu_n_s8"><div>uint8x8_t <b><b>vqshlu_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshluq_n_s8" type="checkbox"><label for="vqshluq_n_s8"><div>uint8x16_t <b><b>vqshluq_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlu_n_s16" type="checkbox"><label for="vqshlu_n_s16"><div>uint16x4_t <b><b>vqshlu_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshluq_n_s16" type="checkbox"><label for="vqshluq_n_s16"><div>uint16x8_t <b><b>vqshluq_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlu_n_s32" type="checkbox"><label for="vqshlu_n_s32"><div>uint32x2_t <b><b>vqshlu_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshluq_n_s32" type="checkbox"><label for="vqshluq_n_s32"><div>uint32x4_t <b><b>vqshluq_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlu_n_s64" type="checkbox"><label for="vqshlu_n_s64"><div>uint64x1_t <b><b>vqshlu_n_s64</b></b> (int64x1_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshluq_n_s64" type="checkbox"><label for="vqshluq_n_s64"><div>uint64x2_t <b><b>vqshluq_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshlub_n_s8" type="checkbox"><label for="vqshlub_n_s8"><div>uint8_t <b><b>vqshlub_n_s8</b></b> (int8_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Bd,Bn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshluh_n_s16" type="checkbox"><label for="vqshluh_n_s16"><div>uint16_t <b><b>vqshluh_n_s16</b></b> (int16_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Hd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlus_n_s32" type="checkbox"><label for="vqshlus_n_s32"><div>uint32_t <b><b>vqshlus_n_s32</b></b> (int32_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshlud_n_s64" type="checkbox"><label for="vqshlud_n_s64"><div>uint64_t <b><b>vqshlud_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed saturating shift left unsigned</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHL</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshlu-signed-saturating-shift-left-unsigned-immediate">SQSHLU</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], src_unsigned) &lt;&lt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, dst_unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_n_s16" type="checkbox"><label for="vshrn_n_s16"><div>int8x8_t <b><b>vshrn_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_n_s32" type="checkbox"><label for="vshrn_n_s32"><div>int16x4_t <b><b>vshrn_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_n_s64" type="checkbox"><label for="vshrn_n_s64"><div>int32x2_t <b><b>vshrn_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_n_u16" type="checkbox"><label for="vshrn_n_u16"><div>uint8x8_t <b><b>vshrn_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_n_u32" type="checkbox"><label for="vshrn_n_u32"><div>uint16x4_t <b><b>vshrn_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_n_u64" type="checkbox"><label for="vshrn_n_u64"><div>uint32x2_t <b><b>vshrn_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_high_n_s16" type="checkbox"><label for="vshrn_high_n_s16"><div>int8x16_t <b><b>vshrn_high_n_s16</b></b> (int8x8_t r, int16x8_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_high_n_s32" type="checkbox"><label for="vshrn_high_n_s32"><div>int16x8_t <b><b>vshrn_high_n_s32</b></b> (int16x4_t r, int32x4_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_high_n_s64" type="checkbox"><label for="vshrn_high_n_s64"><div>int32x4_t <b><b>vshrn_high_n_s64</b></b> (int32x2_t r, int64x2_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_high_n_u16" type="checkbox"><label for="vshrn_high_n_u16"><div>uint8x16_t <b><b>vshrn_high_n_u16</b></b> (uint8x8_t r, uint16x8_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_high_n_u32" type="checkbox"><label for="vshrn_high_n_u32"><div>uint16x8_t <b><b>vshrn_high_n_u32</b></b> (uint16x4_t r, uint32x4_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshrn_high_n_u64" type="checkbox"><label for="vshrn_high_n_u64"><div>uint32x4_t <b><b>vshrn_high_n_u64</b></b> (uint32x2_t r, uint64x2_t a, const int n)<span class="right">Shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">RSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shrn-shrn2-shift-right-narrow-immediate">SHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrun_n_s16" type="checkbox"><label for="vqshrun_n_s16"><div>uint8x8_t <b><b>vqshrun_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrun_n_s32" type="checkbox"><label for="vqshrun_n_s32"><div>uint16x4_t <b><b>vqshrun_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrun_n_s64" type="checkbox"><label for="vqshrun_n_s64"><div>uint32x2_t <b><b>vqshrun_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrunh_n_s16" type="checkbox"><label for="vqshrunh_n_s16"><div>uint8_t <b><b>vqshrunh_n_s16</b></b> (int16_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN</a> Bd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshruns_n_s32" type="checkbox"><label for="vqshruns_n_s32"><div>uint16_t <b><b>vqshruns_n_s32</b></b> (int32_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN</a> Hd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrund_n_s64" type="checkbox"><label for="vqshrund_n_s64"><div>uint32_t <b><b>vqshrund_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN</a> Sd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrun_high_n_s16" type="checkbox"><label for="vqshrun_high_n_s16"><div>uint8x16_t <b><b>vqshrun_high_n_s16</b></b> (uint8x8_t r, int16x8_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrun_high_n_s32" type="checkbox"><label for="vqshrun_high_n_s32"><div>uint16x8_t <b><b>vqshrun_high_n_s32</b></b> (uint16x4_t r, int32x4_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrun_high_n_s64" type="checkbox"><label for="vqshrun_high_n_s64"><div>uint32x4_t <b><b>vqshrun_high_n_s64</b></b> (uint32x2_t r, int64x2_t a, const int n)<span class="right">Signed saturating shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrun-sqshrun2-signed-saturating-shift-right-unsigned-narrow-immediate">SQSHRUN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrun_n_s16" type="checkbox"><label for="vqrshrun_n_s16"><div>uint8x8_t <b><b>vqrshrun_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrun_n_s32" type="checkbox"><label for="vqrshrun_n_s32"><div>uint16x4_t <b><b>vqrshrun_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrun_n_s64" type="checkbox"><label for="vqrshrun_n_s64"><div>uint32x2_t <b><b>vqrshrun_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrunh_n_s16" type="checkbox"><label for="vqrshrunh_n_s16"><div>uint8_t <b><b>vqrshrunh_n_s16</b></b> (int16_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN</a> Bd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshruns_n_s32" type="checkbox"><label for="vqrshruns_n_s32"><div>uint16_t <b><b>vqrshruns_n_s32</b></b> (int32_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN</a> Hd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrund_n_s64" type="checkbox"><label for="vqrshrund_n_s64"><div>uint32_t <b><b>vqrshrund_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN</a> Sd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrun_high_n_s16" type="checkbox"><label for="vqrshrun_high_n_s16"><div>uint8x16_t <b><b>vqrshrun_high_n_s16</b></b> (uint8x8_t r, int16x8_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrun_high_n_s32" type="checkbox"><label for="vqrshrun_high_n_s32"><div>uint16x8_t <b><b>vqrshrun_high_n_s32</b></b> (uint16x4_t r, int32x4_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrun_high_n_s64" type="checkbox"><label for="vqrshrun_high_n_s64"><div>uint32x4_t <b><b>vqrshrun_high_n_s64</b></b> (uint32x2_t r, int64x2_t a, const int n)<span class="right">Signed saturating rounded shift right unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&amp;FP register. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRUN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrun-sqrshrun2-signed-saturating-rounded-shift-right-unsigned-narrow-immediate">SQRSHRUN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_n_s16" type="checkbox"><label for="vqshrn_n_s16"><div>int8x8_t <b><b>vqshrn_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_n_s32" type="checkbox"><label for="vqshrn_n_s32"><div>int16x4_t <b><b>vqshrn_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_n_s64" type="checkbox"><label for="vqshrn_n_s64"><div>int32x2_t <b><b>vqshrn_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_n_u16" type="checkbox"><label for="vqshrn_n_u16"><div>uint8x8_t <b><b>vqshrn_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_n_u32" type="checkbox"><label for="vqshrn_n_u32"><div>uint16x4_t <b><b>vqshrn_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_n_u64" type="checkbox"><label for="vqshrn_n_u64"><div>uint32x2_t <b><b>vqshrn_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqshrnh_n_s16" type="checkbox"><label for="vqshrnh_n_s16"><div>int8_t <b><b>vqshrnh_n_s16</b></b> (int16_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN</a> Bd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrns_n_s32" type="checkbox"><label for="vqshrns_n_s32"><div>int16_t <b><b>vqshrns_n_s32</b></b> (int32_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN</a> Hd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrnd_n_s64" type="checkbox"><label for="vqshrnd_n_s64"><div>int32_t <b><b>vqshrnd_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN</a> Sd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrnh_n_u16" type="checkbox"><label for="vqshrnh_n_u16"><div>uint8_t <b><b>vqshrnh_n_u16</b></b> (uint16_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN</a> Bd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrns_n_u32" type="checkbox"><label for="vqshrns_n_u32"><div>uint16_t <b><b>vqshrns_n_u32</b></b> (uint32_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN</a> Hd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrnd_n_u64" type="checkbox"><label for="vqshrnd_n_u64"><div>uint32_t <b><b>vqshrnd_n_u64</b></b> (uint64_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN</a> Sd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_high_n_s16" type="checkbox"><label for="vqshrn_high_n_s16"><div>int8x16_t <b><b>vqshrn_high_n_s16</b></b> (int8x8_t r, int16x8_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_high_n_s32" type="checkbox"><label for="vqshrn_high_n_s32"><div>int16x8_t <b><b>vqshrn_high_n_s32</b></b> (int16x4_t r, int32x4_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_high_n_s64" type="checkbox"><label for="vqshrn_high_n_s64"><div>int32x4_t <b><b>vqshrn_high_n_s64</b></b> (int32x2_t r, int64x2_t a, const int n)<span class="right">Signed saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqshrn-sqshrn2-signed-saturating-shift-right-narrow-immediate">SQSHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_high_n_u16" type="checkbox"><label for="vqshrn_high_n_u16"><div>uint8x16_t <b><b>vqshrn_high_n_u16</b></b> (uint8x8_t r, uint16x8_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_high_n_u32" type="checkbox"><label for="vqshrn_high_n_u32"><div>uint16x8_t <b><b>vqshrn_high_n_u32</b></b> (uint16x4_t r, uint32x4_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqshrn_high_n_u64" type="checkbox"><label for="vqshrn_high_n_u64"><div>uint32x4_t <b><b>vqshrn_high_n_u64</b></b> (uint32x2_t r, uint64x2_t a, const int n)<span class="right">Unsigned saturating shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQRSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqshrn-uqshrn2-unsigned-saturating-shift-right-narrow-immediate">UQSHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_n_s16" type="checkbox"><label for="vrshrn_n_s16"><div>int8x8_t <b><b>vrshrn_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_n_s32" type="checkbox"><label for="vrshrn_n_s32"><div>int16x4_t <b><b>vrshrn_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_n_s64" type="checkbox"><label for="vrshrn_n_s64"><div>int32x2_t <b><b>vrshrn_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_n_u16" type="checkbox"><label for="vrshrn_n_u16"><div>uint8x8_t <b><b>vrshrn_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_n_u32" type="checkbox"><label for="vrshrn_n_u32"><div>uint16x4_t <b><b>vrshrn_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_n_u64" type="checkbox"><label for="vrshrn_n_u64"><div>uint32x2_t <b><b>vrshrn_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_high_n_s16" type="checkbox"><label for="vrshrn_high_n_s16"><div>int8x16_t <b><b>vrshrn_high_n_s16</b></b> (int8x8_t r, int16x8_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_high_n_s32" type="checkbox"><label for="vrshrn_high_n_s32"><div>int16x8_t <b><b>vrshrn_high_n_s32</b></b> (int16x4_t r, int32x4_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_high_n_s64" type="checkbox"><label for="vrshrn_high_n_s64"><div>int32x4_t <b><b>vrshrn_high_n_s64</b></b> (int32x2_t r, int64x2_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_high_n_u16" type="checkbox"><label for="vrshrn_high_n_u16"><div>uint8x16_t <b><b>vrshrn_high_n_u16</b></b> (uint8x8_t r, uint16x8_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_high_n_u32" type="checkbox"><label for="vrshrn_high_n_u32"><div>uint16x8_t <b><b>vrshrn_high_n_u32</b></b> (uint16x4_t r, uint32x4_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrshrn_high_n_u64" type="checkbox"><label for="vrshrn_high_n_u64"><div>uint32x4_t <b><b>vrshrn_high_n_u64</b></b> (uint32x2_t r, uint64x2_t a, const int n)<span class="right">Rounding shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&amp;FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rshrn-rshrn2-rounding-shift-right-narrow-immediate">RSHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; 32(Vd) <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize]) + round_const) &gt;&gt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_n_s16" type="checkbox"><label for="vqrshrn_n_s16"><div>int8x8_t <b><b>vqrshrn_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_n_s32" type="checkbox"><label for="vqrshrn_n_s32"><div>int16x4_t <b><b>vqrshrn_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_n_s64" type="checkbox"><label for="vqrshrn_n_s64"><div>int32x2_t <b><b>vqrshrn_n_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_n_u16" type="checkbox"><label for="vqrshrn_n_u16"><div>uint8x8_t <b><b>vqrshrn_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN</a> Vd.8B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_n_u32" type="checkbox"><label for="vqrshrn_n_u32"><div>uint16x4_t <b><b>vqrshrn_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN</a> Vd.4H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_n_u64" type="checkbox"><label for="vqrshrn_n_u64"><div>uint32x2_t <b><b>vqrshrn_n_u64</b></b> (uint64x2_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN</a> Vd.2S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrnh_n_s16" type="checkbox"><label for="vqrshrnh_n_s16"><div>int8_t <b><b>vqrshrnh_n_s16</b></b> (int16_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN</a> Bd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrns_n_s32" type="checkbox"><label for="vqrshrns_n_s32"><div>int16_t <b><b>vqrshrns_n_s32</b></b> (int32_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN</a> Hd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrnd_n_s64" type="checkbox"><label for="vqrshrnd_n_s64"><div>int32_t <b><b>vqrshrnd_n_s64</b></b> (int64_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN</a> Sd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrnh_n_u16" type="checkbox"><label for="vqrshrnh_n_u16"><div>uint8_t <b><b>vqrshrnh_n_u16</b></b> (uint16_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN</a> Bd,Hn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrns_n_u32" type="checkbox"><label for="vqrshrns_n_u32"><div>uint16_t <b><b>vqrshrns_n_u32</b></b> (uint32_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN</a> Hd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrnd_n_u64" type="checkbox"><label for="vqrshrnd_n_u64"><div>uint32_t <b><b>vqrshrnd_n_u64</b></b> (uint64_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN</a> Sd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_high_n_s16" type="checkbox"><label for="vqrshrn_high_n_s16"><div>int8x16_t <b><b>vqrshrn_high_n_s16</b></b> (int8x8_t r, int16x8_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_high_n_s32" type="checkbox"><label for="vqrshrn_high_n_s32"><div>int16x8_t <b><b>vqrshrn_high_n_s32</b></b> (int16x4_t r, int32x4_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_high_n_s64" type="checkbox"><label for="vqrshrn_high_n_s64"><div>int32x4_t <b><b>vqrshrn_high_n_s64</b></b> (int32x2_t r, int64x2_t a, const int n)<span class="right">Signed saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">SQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrshrn-sqrshrn2-signed-saturating-rounded-shift-right-narrow-immediate">SQRSHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_high_n_u16" type="checkbox"><label for="vqrshrn_high_n_u16"><div>uint8x16_t <b><b>vqrshrn_high_n_u16</b></b> (uint8x8_t r, uint16x8_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN2</a> Vd.16B,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_high_n_u32" type="checkbox"><label for="vqrshrn_high_n_u32"><div>uint16x8_t <b><b>vqrshrn_high_n_u32</b></b> (uint16x4_t r, uint32x4_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN2</a> Vd.8H,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrshrn_high_n_u64" type="checkbox"><label for="vqrshrn_high_n_u64"><div>uint32x4_t <b><b>vqrshrn_high_n_u64</b></b> (uint32x2_t r, uint64x2_t a, const int n)<span class="right">Unsigned saturating rounded shift right narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to ARM ARM section">UQSHRN</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqrshrn-uqrshrn2-unsigned-saturating-rounded-shift-right-narrow-immediate">UQRSHRN2</a> Vd.4S,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize*2) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_s8" type="checkbox"><label for="vshll_n_s8"><div>int16x8_t <b><b>vshll_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL</a> Vd.8H,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_s16" type="checkbox"><label for="vshll_n_s16"><div>int32x4_t <b><b>vshll_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL</a> Vd.4S,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_s32" type="checkbox"><label for="vshll_n_s32"><div>int64x2_t <b><b>vshll_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL</a> Vd.2D,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_u8" type="checkbox"><label for="vshll_n_u8"><div>uint16x8_t <b><b>vshll_n_u8</b></b> (uint8x8_t a, const int n)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL</a> Vd.8H,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_u16" type="checkbox"><label for="vshll_n_u16"><div>uint32x4_t <b><b>vshll_n_u16</b></b> (uint16x4_t a, const int n)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL</a> Vd.4S,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_u32" type="checkbox"><label for="vshll_n_u32"><div>uint64x2_t <b><b>vshll_n_u32</b></b> (uint32x2_t a, const int n)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL</a> Vd.2D,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_s8" type="checkbox"><label for="vshll_high_n_s8"><div>int16x8_t <b><b>vshll_high_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL2</a> Vd.8H,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_s16" type="checkbox"><label for="vshll_high_n_s16"><div>int32x4_t <b><b>vshll_high_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL2</a> Vd.4S,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_s32" type="checkbox"><label for="vshll_high_n_s32"><div>int64x2_t <b><b>vshll_high_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL2</a> Vd.2D,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_u8" type="checkbox"><label for="vshll_high_n_u8"><div>uint16x8_t <b><b>vshll_high_n_u8</b></b> (uint8x16_t a, const int n)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL2</a> Vd.8H,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_u16" type="checkbox"><label for="vshll_high_n_u16"><div>uint32x4_t <b><b>vshll_high_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL2</a> Vd.4S,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_u32" type="checkbox"><label for="vshll_high_n_u32"><div>uint64x2_t <b><b>vshll_high_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL2</a> Vd.2D,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_s8" type="checkbox"><label for="vshll_n_s8"><div>int16x8_t <b><b>vshll_n_s8</b></b> (int8x8_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL</a> Vd.8H,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 8 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_s16" type="checkbox"><label for="vshll_n_s16"><div>int32x4_t <b><b>vshll_n_s16</b></b> (int16x4_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL</a> Vd.4S,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 16 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_s32" type="checkbox"><label for="vshll_n_s32"><div>int64x2_t <b><b>vshll_n_s32</b></b> (int32x2_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL</a> Vd.2D,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 32 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_u8" type="checkbox"><label for="vshll_n_u8"><div>uint16x8_t <b><b>vshll_n_u8</b></b> (uint8x8_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL</a> Vd.8H,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ 8 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_u16" type="checkbox"><label for="vshll_n_u16"><div>uint32x4_t <b><b>vshll_n_u16</b></b> (uint16x4_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL</a> Vd.4S,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ 16 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_n_u32" type="checkbox"><label for="vshll_n_u32"><div>uint64x2_t <b><b>vshll_n_u32</b></b> (uint32x2_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL</a> Vd.2D,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 32 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_s8" type="checkbox"><label for="vshll_high_n_s8"><div>int16x8_t <b><b>vshll_high_n_s8</b></b> (int8x16_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL2</a> Vd.8H,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 8 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_s16" type="checkbox"><label for="vshll_high_n_s16"><div>int32x4_t <b><b>vshll_high_n_s16</b></b> (int16x8_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL2</a> Vd.4S,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 16 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_s32" type="checkbox"><label for="vshll_high_n_s32"><div>int64x2_t <b><b>vshll_high_n_s32</b></b> (int32x4_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL2</a> Vd.2D,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 32 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_u8" type="checkbox"><label for="vshll_high_n_u8"><div>uint16x8_t <b><b>vshll_high_n_u8</b></b> (uint8x16_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL2</a> Vd.8H,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ 8 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_u16" type="checkbox"><label for="vshll_high_n_u16"><div>uint32x4_t <b><b>vshll_high_n_u16</b></b> (uint16x8_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL2</a> Vd.4S,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ 16 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vshll_high_n_u32" type="checkbox"><label for="vshll_high_n_u32"><div>uint64x2_t <b><b>vshll_high_n_u32</b></b> (uint32x4_t a, const int n)<span class="right">Shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/shll-shll2-shift-left-long-by-element-size">SHLL2</a> Vd.2D,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 32 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_s8" type="checkbox"><label for="vsri_n_s8"><div>int8x8_t <b><b>vsri_n_s8</b></b> (int8x8_t a, int8x8_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_s8" type="checkbox"><label for="vsriq_n_s8"><div>int8x16_t <b><b>vsriq_n_s8</b></b> (int8x16_t a, int8x16_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_s16" type="checkbox"><label for="vsri_n_s16"><div>int16x4_t <b><b>vsri_n_s16</b></b> (int16x4_t a, int16x4_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_s16" type="checkbox"><label for="vsriq_n_s16"><div>int16x8_t <b><b>vsriq_n_s16</b></b> (int16x8_t a, int16x8_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_s32" type="checkbox"><label for="vsri_n_s32"><div>int32x2_t <b><b>vsri_n_s32</b></b> (int32x2_t a, int32x2_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_s32" type="checkbox"><label for="vsriq_n_s32"><div>int32x4_t <b><b>vsriq_n_s32</b></b> (int32x4_t a, int32x4_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_s64" type="checkbox"><label for="vsri_n_s64"><div>int64x1_t <b><b>vsri_n_s64</b></b> (int64x1_t a, int64x1_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_s64" type="checkbox"><label for="vsriq_n_s64"><div>int64x2_t <b><b>vsriq_n_s64</b></b> (int64x2_t a, int64x2_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_u8" type="checkbox"><label for="vsri_n_u8"><div>uint8x8_t <b><b>vsri_n_u8</b></b> (uint8x8_t a, uint8x8_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_u8" type="checkbox"><label for="vsriq_n_u8"><div>uint8x16_t <b><b>vsriq_n_u8</b></b> (uint8x16_t a, uint8x16_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_u16" type="checkbox"><label for="vsri_n_u16"><div>uint16x4_t <b><b>vsri_n_u16</b></b> (uint16x4_t a, uint16x4_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_u16" type="checkbox"><label for="vsriq_n_u16"><div>uint16x8_t <b><b>vsriq_n_u16</b></b> (uint16x8_t a, uint16x8_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_u32" type="checkbox"><label for="vsri_n_u32"><div>uint32x2_t <b><b>vsri_n_u32</b></b> (uint32x2_t a, uint32x2_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_u32" type="checkbox"><label for="vsriq_n_u32"><div>uint32x4_t <b><b>vsriq_n_u32</b></b> (uint32x4_t a, uint32x4_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_u64" type="checkbox"><label for="vsri_n_u64"><div>uint64x1_t <b><b>vsri_n_u64</b></b> (uint64x1_t a, uint64x1_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_u64" type="checkbox"><label for="vsriq_n_u64"><div>uint64x2_t <b><b>vsriq_n_u64</b></b> (uint64x2_t a, uint64x2_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_p64" type="checkbox"><label for="vsri_n_p64"><div>poly64x1_t <b><b>vsri_n_p64</b></b> (poly64x1_t a, poly64x1_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_p64" type="checkbox"><label for="vsriq_n_p64"><div>poly64x2_t <b><b>vsriq_n_p64</b></b> (poly64x2_t a, poly64x2_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_p8" type="checkbox"><label for="vsri_n_p8"><div>poly8x8_t <b><b>vsri_n_p8</b></b> (poly8x8_t a, poly8x8_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_p8" type="checkbox"><label for="vsriq_n_p8"><div>poly8x16_t <b><b>vsriq_n_p8</b></b> (poly8x16_t a, poly8x16_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 1 &lt;&lt; n &lt;&lt; 8 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsri_n_p16" type="checkbox"><label for="vsri_n_p16"><div>poly16x4_t <b><b>vsri_n_p16</b></b> (poly16x4_t a, poly16x4_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsriq_n_p16" type="checkbox"><label for="vsriq_n_p16"><div>poly16x8_t <b><b>vsriq_n_p16</b></b> (poly16x8_t a, poly16x8_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 1 &lt;&lt; n &lt;&lt; 16 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsrid_n_s64" type="checkbox"><label for="vsrid_n_s64"><div>int64_t <b><b>vsrid_n_s64</b></b> (int64_t a, int64_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsrid_n_u64" type="checkbox"><label for="vsrid_n_u64"><div>uint64_t <b><b>vsrid_n_u64</b></b> (uint64_t a, uint64_t b, const int n)<span class="right">Shift right and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sri-shift-right-and-insert-immediate">SRI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_s8" type="checkbox"><label for="vsli_n_s8"><div>int8x8_t <b><b>vsli_n_s8</b></b> (int8x8_t a, int8x8_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_s8" type="checkbox"><label for="vsliq_n_s8"><div>int8x16_t <b><b>vsliq_n_s8</b></b> (int8x16_t a, int8x16_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_s16" type="checkbox"><label for="vsli_n_s16"><div>int16x4_t <b><b>vsli_n_s16</b></b> (int16x4_t a, int16x4_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_s16" type="checkbox"><label for="vsliq_n_s16"><div>int16x8_t <b><b>vsliq_n_s16</b></b> (int16x8_t a, int16x8_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_s32" type="checkbox"><label for="vsli_n_s32"><div>int32x2_t <b><b>vsli_n_s32</b></b> (int32x2_t a, int32x2_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_s32" type="checkbox"><label for="vsliq_n_s32"><div>int32x4_t <b><b>vsliq_n_s32</b></b> (int32x4_t a, int32x4_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_s64" type="checkbox"><label for="vsli_n_s64"><div>int64x1_t <b><b>vsli_n_s64</b></b> (int64x1_t a, int64x1_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_s64" type="checkbox"><label for="vsliq_n_s64"><div>int64x2_t <b><b>vsliq_n_s64</b></b> (int64x2_t a, int64x2_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_u8" type="checkbox"><label for="vsli_n_u8"><div>uint8x8_t <b><b>vsli_n_u8</b></b> (uint8x8_t a, uint8x8_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_u8" type="checkbox"><label for="vsliq_n_u8"><div>uint8x16_t <b><b>vsliq_n_u8</b></b> (uint8x16_t a, uint8x16_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_u16" type="checkbox"><label for="vsli_n_u16"><div>uint16x4_t <b><b>vsli_n_u16</b></b> (uint16x4_t a, uint16x4_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_u16" type="checkbox"><label for="vsliq_n_u16"><div>uint16x8_t <b><b>vsliq_n_u16</b></b> (uint16x8_t a, uint16x8_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_u32" type="checkbox"><label for="vsli_n_u32"><div>uint32x2_t <b><b>vsli_n_u32</b></b> (uint32x2_t a, uint32x2_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_u32" type="checkbox"><label for="vsliq_n_u32"><div>uint32x4_t <b><b>vsliq_n_u32</b></b> (uint32x4_t a, uint32x4_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; n &lt;&lt; 31 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_u64" type="checkbox"><label for="vsli_n_u64"><div>uint64x1_t <b><b>vsli_n_u64</b></b> (uint64x1_t a, uint64x1_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_u64" type="checkbox"><label for="vsliq_n_u64"><div>uint64x2_t <b><b>vsliq_n_u64</b></b> (uint64x2_t a, uint64x2_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_p64" type="checkbox"><label for="vsli_n_p64"><div>poly64x1_t <b><b>vsli_n_p64</b></b> (poly64x1_t a, poly64x1_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_p64" type="checkbox"><label for="vsliq_n_p64"><div>poly64x2_t <b><b>vsliq_n_p64</b></b> (poly64x2_t a, poly64x2_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_p8" type="checkbox"><label for="vsli_n_p8"><div>poly8x8_t <b><b>vsli_n_p8</b></b> (poly8x8_t a, poly8x8_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.8B,Vn.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_p8" type="checkbox"><label for="vsliq_n_p8"><div>poly8x16_t <b><b>vsliq_n_p8</b></b> (poly8x16_t a, poly8x16_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.16B,Vn.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsli_n_p16" type="checkbox"><label for="vsli_n_p16"><div>poly16x4_t <b><b>vsli_n_p16</b></b> (poly16x4_t a, poly16x4_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.4H,Vn.4H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsliq_n_p16" type="checkbox"><label for="vsliq_n_p16"><div>poly16x8_t <b><b>vsliq_n_p16</b></b> (poly16x8_t a, poly16x8_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Vd.8H,Vn.8H,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vslid_n_s64" type="checkbox"><label for="vslid_n_s64"><div>int64_t <b><b>vslid_n_s64</b></b> (int64_t a, int64_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vslid_n_u64" type="checkbox"><label for="vslid_n_u64"><div>uint64_t <b><b>vslid_n_u64</b></b> (uint64_t a, uint64_t b, const int n)<span class="right">Shift left and insert</span></div></label><article>      <h4>Description</h4><p><p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sli-shift-left-and-insert-immediate">SLI</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Dn <br />
+ 0 &lt;&lt; n &lt;&lt; 63 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) mask = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
+ bits(esize) shifted;
+ 
+ for e = 0 to elements-1
+     shifted = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_s32_f32" type="checkbox"><label for="vcvt_s32_f32"><div>int32x2_t <b><b>vcvt_s32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_s32_f32" type="checkbox"><label for="vcvtq_s32_f32"><div>int32x4_t <b><b>vcvtq_s32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_u32_f32" type="checkbox"><label for="vcvt_u32_f32"><div>uint32x2_t <b><b>vcvt_u32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_u32_f32" type="checkbox"><label for="vcvtq_u32_f32"><div>uint32x4_t <b><b>vcvtq_u32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtn_s32_f32" type="checkbox"><label for="vcvtn_s32_f32"><div>int32x2_t <b><b>vcvtn_s32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtns-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtnq_s32_f32" type="checkbox"><label for="vcvtnq_s32_f32"><div>int32x4_t <b><b>vcvtnq_s32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtns-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtn_u32_f32" type="checkbox"><label for="vcvtn_u32_f32"><div>uint32x2_t <b><b>vcvtn_u32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtnu-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNU</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtnq_u32_f32" type="checkbox"><label for="vcvtnq_u32_f32"><div>uint32x4_t <b><b>vcvtnq_u32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtnu-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNU</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtm_s32_f32" type="checkbox"><label for="vcvtm_s32_f32"><div>int32x2_t <b><b>vcvtm_s32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to signed integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtms-vector-floating-point-convert-to-signed-integer-rounding-toward-minus-infinity-vector">FCVTMS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtmq_s32_f32" type="checkbox"><label for="vcvtmq_s32_f32"><div>int32x4_t <b><b>vcvtmq_s32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to signed integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtms-vector-floating-point-convert-to-signed-integer-rounding-toward-minus-infinity-vector">FCVTMS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtm_u32_f32" type="checkbox"><label for="vcvtm_u32_f32"><div>uint32x2_t <b><b>vcvtm_u32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtmu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-minus-infinity-vector">FCVTMU</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtmq_u32_f32" type="checkbox"><label for="vcvtmq_u32_f32"><div>uint32x4_t <b><b>vcvtmq_u32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtmu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-minus-infinity-vector">FCVTMU</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtp_s32_f32" type="checkbox"><label for="vcvtp_s32_f32"><div>int32x2_t <b><b>vcvtp_s32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to signed integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtps-vector-floating-point-convert-to-signed-integer-rounding-toward-plus-infinity-vector">FCVTPS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtpq_s32_f32" type="checkbox"><label for="vcvtpq_s32_f32"><div>int32x4_t <b><b>vcvtpq_s32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to signed integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtps-vector-floating-point-convert-to-signed-integer-rounding-toward-plus-infinity-vector">FCVTPS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtp_u32_f32" type="checkbox"><label for="vcvtp_u32_f32"><div>uint32x2_t <b><b>vcvtp_u32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtpu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-plus-infinity-vector">FCVTPU</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtpq_u32_f32" type="checkbox"><label for="vcvtpq_u32_f32"><div>uint32x4_t <b><b>vcvtpq_u32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtpu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-plus-infinity-vector">FCVTPU</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvta_s32_f32" type="checkbox"><label for="vcvta_s32_f32"><div>int32x2_t <b><b>vcvta_s32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtas-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtaq_s32_f32" type="checkbox"><label for="vcvtaq_s32_f32"><div>int32x4_t <b><b>vcvtaq_s32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtas-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvta_u32_f32" type="checkbox"><label for="vcvta_u32_f32"><div>uint32x2_t <b><b>vcvta_u32_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtau-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAU</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtaq_u32_f32" type="checkbox"><label for="vcvtaq_u32_f32"><div>uint32x4_t <b><b>vcvtaq_u32_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtau-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAU</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_s32_f32" type="checkbox"><label for="vcvts_s32_f32"><div>int32_t <b><b>vcvts_s32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_u32_f32" type="checkbox"><label for="vcvts_u32_f32"><div>uint32_t <b><b>vcvts_u32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtns_s32_f32" type="checkbox"><label for="vcvtns_s32_f32"><div>int32_t <b><b>vcvtns_s32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtns-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNS</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtns_u32_f32" type="checkbox"><label for="vcvtns_u32_f32"><div>uint32_t <b><b>vcvtns_u32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtnu-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNU</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtms_s32_f32" type="checkbox"><label for="vcvtms_s32_f32"><div>int32_t <b><b>vcvtms_s32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to signed integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtms-vector-floating-point-convert-to-signed-integer-rounding-toward-minus-infinity-vector">FCVTMS</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtms_u32_f32" type="checkbox"><label for="vcvtms_u32_f32"><div>uint32_t <b><b>vcvtms_u32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtmu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-minus-infinity-vector">FCVTMU</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtps_s32_f32" type="checkbox"><label for="vcvtps_s32_f32"><div>int32_t <b><b>vcvtps_s32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to signed integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtps-vector-floating-point-convert-to-signed-integer-rounding-toward-plus-infinity-vector">FCVTPS</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtps_u32_f32" type="checkbox"><label for="vcvtps_u32_f32"><div>uint32_t <b><b>vcvtps_u32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtpu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-plus-infinity-vector">FCVTPU</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtas_s32_f32" type="checkbox"><label for="vcvtas_s32_f32"><div>int32_t <b><b>vcvtas_s32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtas-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAS</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtas_u32_f32" type="checkbox"><label for="vcvtas_u32_f32"><div>uint32_t <b><b>vcvtas_u32_f32</b></b> (float32_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtau-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAU</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_s64_f64" type="checkbox"><label for="vcvt_s64_f64"><div>int64x1_t <b><b>vcvt_s64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_s64_f64" type="checkbox"><label for="vcvtq_s64_f64"><div>int64x2_t <b><b>vcvtq_s64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_u64_f64" type="checkbox"><label for="vcvt_u64_f64"><div>uint64x1_t <b><b>vcvt_u64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_u64_f64" type="checkbox"><label for="vcvtq_u64_f64"><div>uint64x2_t <b><b>vcvtq_u64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtn_s64_f64" type="checkbox"><label for="vcvtn_s64_f64"><div>int64x1_t <b><b>vcvtn_s64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtns-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtnq_s64_f64" type="checkbox"><label for="vcvtnq_s64_f64"><div>int64x2_t <b><b>vcvtnq_s64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtns-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtn_u64_f64" type="checkbox"><label for="vcvtn_u64_f64"><div>uint64x1_t <b><b>vcvtn_u64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtnu-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtnq_u64_f64" type="checkbox"><label for="vcvtnq_u64_f64"><div>uint64x2_t <b><b>vcvtnq_u64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtnu-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNU</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtm_s64_f64" type="checkbox"><label for="vcvtm_s64_f64"><div>int64x1_t <b><b>vcvtm_s64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to signed integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtms-vector-floating-point-convert-to-signed-integer-rounding-toward-minus-infinity-vector">FCVTMS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtmq_s64_f64" type="checkbox"><label for="vcvtmq_s64_f64"><div>int64x2_t <b><b>vcvtmq_s64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to signed integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtms-vector-floating-point-convert-to-signed-integer-rounding-toward-minus-infinity-vector">FCVTMS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtm_u64_f64" type="checkbox"><label for="vcvtm_u64_f64"><div>uint64x1_t <b><b>vcvtm_u64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtmu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-minus-infinity-vector">FCVTMU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtmq_u64_f64" type="checkbox"><label for="vcvtmq_u64_f64"><div>uint64x2_t <b><b>vcvtmq_u64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtmu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-minus-infinity-vector">FCVTMU</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtp_s64_f64" type="checkbox"><label for="vcvtp_s64_f64"><div>int64x1_t <b><b>vcvtp_s64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to signed integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtps-vector-floating-point-convert-to-signed-integer-rounding-toward-plus-infinity-vector">FCVTPS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtpq_s64_f64" type="checkbox"><label for="vcvtpq_s64_f64"><div>int64x2_t <b><b>vcvtpq_s64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to signed integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtps-vector-floating-point-convert-to-signed-integer-rounding-toward-plus-infinity-vector">FCVTPS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtp_u64_f64" type="checkbox"><label for="vcvtp_u64_f64"><div>uint64x1_t <b><b>vcvtp_u64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtpu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-plus-infinity-vector">FCVTPU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtpq_u64_f64" type="checkbox"><label for="vcvtpq_u64_f64"><div>uint64x2_t <b><b>vcvtpq_u64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtpu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-plus-infinity-vector">FCVTPU</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvta_s64_f64" type="checkbox"><label for="vcvta_s64_f64"><div>int64x1_t <b><b>vcvta_s64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtas-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtaq_s64_f64" type="checkbox"><label for="vcvtaq_s64_f64"><div>int64x2_t <b><b>vcvtaq_s64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtas-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvta_u64_f64" type="checkbox"><label for="vcvta_u64_f64"><div>uint64x1_t <b><b>vcvta_u64_f64</b></b> (float64x1_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtau-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtaq_u64_f64" type="checkbox"><label for="vcvtaq_u64_f64"><div>uint64x2_t <b><b>vcvtaq_u64_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtau-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAU</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_s64_f64" type="checkbox"><label for="vcvtd_s64_f64"><div>int64_t <b><b>vcvtd_s64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_u64_f64" type="checkbox"><label for="vcvtd_u64_f64"><div>uint64_t <b><b>vcvtd_u64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtnd_s64_f64" type="checkbox"><label for="vcvtnd_s64_f64"><div>int64_t <b><b>vcvtnd_s64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtns-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtnd_u64_f64" type="checkbox"><label for="vcvtnd_u64_f64"><div>uint64_t <b><b>vcvtnd_u64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtnu-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-even-vector">FCVTNU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtmd_s64_f64" type="checkbox"><label for="vcvtmd_s64_f64"><div>int64_t <b><b>vcvtmd_s64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to signed integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtms-vector-floating-point-convert-to-signed-integer-rounding-toward-minus-infinity-vector">FCVTMS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtmd_u64_f64" type="checkbox"><label for="vcvtmd_u64_f64"><div>uint64_t <b><b>vcvtmd_u64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtmu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-minus-infinity-vector">FCVTMU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtpd_s64_f64" type="checkbox"><label for="vcvtpd_s64_f64"><div>int64_t <b><b>vcvtpd_s64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to signed integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtps-vector-floating-point-convert-to-signed-integer-rounding-toward-plus-infinity-vector">FCVTPS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtpd_u64_f64" type="checkbox"><label for="vcvtpd_u64_f64"><div>uint64_t <b><b>vcvtpd_u64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to unsigned integer, rounding toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtpu-vector-floating-point-convert-to-unsigned-integer-rounding-toward-plus-infinity-vector">FCVTPU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtad_s64_f64" type="checkbox"><label for="vcvtad_s64_f64"><div>int64_t <b><b>vcvtad_s64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to signed integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtas-vector-floating-point-convert-to-signed-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtad_u64_f64" type="checkbox"><label for="vcvtad_u64_f64"><div>uint64_t <b><b>vcvtad_u64_f64</b></b> (float64_t a)<span class="right">Floating-point convert to unsigned integer, rounding to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtau-vector-floating-point-convert-to-unsigned-integer-rounding-to-nearest-with-ties-to-away-vector">FCVTAU</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_s32_f32" type="checkbox"><label for="vcvt_n_s32_f32"><div>int32x2_t <b><b>vcvt_n_s32_f32</b></b> (float32x2_t a, const int n)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_s32_f32" type="checkbox"><label for="vcvtq_n_s32_f32"><div>int32x4_t <b><b>vcvtq_n_s32_f32</b></b> (float32x4_t a, const int n)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_u32_f32" type="checkbox"><label for="vcvt_n_u32_f32"><div>uint32x2_t <b><b>vcvt_n_u32_f32</b></b> (float32x2_t a, const int n)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_u32_f32" type="checkbox"><label for="vcvtq_n_u32_f32"><div>uint32x4_t <b><b>vcvtq_n_u32_f32</b></b> (float32x4_t a, const int n)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_n_s32_f32" type="checkbox"><label for="vcvts_n_s32_f32"><div>int32_t <b><b>vcvts_n_s32_f32</b></b> (float32_t a, const int n)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_n_u32_f32" type="checkbox"><label for="vcvts_n_u32_f32"><div>uint32_t <b><b>vcvts_n_u32_f32</b></b> (float32_t a, const int n)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_s64_f64" type="checkbox"><label for="vcvt_n_s64_f64"><div>int64x1_t <b><b>vcvt_n_s64_f64</b></b> (float64x1_t a, const int n)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_s64_f64" type="checkbox"><label for="vcvtq_n_s64_f64"><div>int64x2_t <b><b>vcvtq_n_s64_f64</b></b> (float64x2_t a, const int n)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_u64_f64" type="checkbox"><label for="vcvt_n_u64_f64"><div>uint64x1_t <b><b>vcvt_n_u64_f64</b></b> (float64x1_t a, const int n)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_u64_f64" type="checkbox"><label for="vcvtq_n_u64_f64"><div>uint64x2_t <b><b>vcvtq_n_u64_f64</b></b> (float64x2_t a, const int n)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_n_s64_f64" type="checkbox"><label for="vcvtd_n_s64_f64"><div>int64_t <b><b>vcvtd_n_s64_f64</b></b> (float64_t a, const int n)<span class="right">Floating-point convert to signed integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzs-vector-integer-floating-point-convert-to-signed-integer-rounding-toward-zero-vector">FCVTZS</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_n_u64_f64" type="checkbox"><label for="vcvtd_n_u64_f64"><div>uint64_t <b><b>vcvtd_n_u64_f64</b></b> (float64_t a, const int n)<span class="right">Floating-point convert to unsigned integer, rounding toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtzu-vector-integer-floating-point-convert-to-unsigned-integer-rounding-toward-zero-vector">FCVTZU</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPToFixed.5" title="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FPToFixed</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f32_s32" type="checkbox"><label for="vcvt_f32_s32"><div>float32x2_t <b><b>vcvt_f32_s32</b></b> (int32x2_t a)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_f32_s32" type="checkbox"><label for="vcvtq_f32_s32"><div>float32x4_t <b><b>vcvtq_f32_s32</b></b> (int32x4_t a)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f32_u32" type="checkbox"><label for="vcvt_f32_u32"><div>float32x2_t <b><b>vcvt_f32_u32</b></b> (uint32x2_t a)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_f32_u32" type="checkbox"><label for="vcvtq_f32_u32"><div>float32x4_t <b><b>vcvtq_f32_u32</b></b> (uint32x4_t a)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_f32_s32" type="checkbox"><label for="vcvts_f32_s32"><div>float32_t <b><b>vcvts_f32_s32</b></b> (int32_t a)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_f32_u32" type="checkbox"><label for="vcvts_f32_u32"><div>float32_t <b><b>vcvts_f32_u32</b></b> (uint32_t a)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f64_s64" type="checkbox"><label for="vcvt_f64_s64"><div>float64x1_t <b><b>vcvt_f64_s64</b></b> (int64x1_t a)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_f64_s64" type="checkbox"><label for="vcvtq_f64_s64"><div>float64x2_t <b><b>vcvtq_f64_s64</b></b> (int64x2_t a)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f64_u64" type="checkbox"><label for="vcvt_f64_u64"><div>float64x1_t <b><b>vcvt_f64_u64</b></b> (uint64x1_t a)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_f64_u64" type="checkbox"><label for="vcvtq_f64_u64"><div>float64x2_t <b><b>vcvtq_f64_u64</b></b> (uint64x2_t a)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_f64_s64" type="checkbox"><label for="vcvtd_f64_s64"><div>float64_t <b><b>vcvtd_f64_s64</b></b> (int64_t a)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_f64_u64" type="checkbox"><label for="vcvtd_f64_u64"><div>float64_t <b><b>vcvtd_f64_u64</b></b> (uint64_t a)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_f32_s32" type="checkbox"><label for="vcvt_n_f32_s32"><div>float32x2_t <b><b>vcvt_n_f32_s32</b></b> (int32x2_t a, const int n)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_f32_s32" type="checkbox"><label for="vcvtq_n_f32_s32"><div>float32x4_t <b><b>vcvtq_n_f32_s32</b></b> (int32x4_t a, const int n)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_f32_u32" type="checkbox"><label for="vcvt_n_f32_u32"><div>float32x2_t <b><b>vcvt_n_f32_u32</b></b> (uint32x2_t a, const int n)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Vd.2S,Vn.2S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_f32_u32" type="checkbox"><label for="vcvtq_n_f32_u32"><div>float32x4_t <b><b>vcvtq_n_f32_u32</b></b> (uint32x4_t a, const int n)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Vd.4S,Vn.4S,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_n_f32_s32" type="checkbox"><label for="vcvts_n_f32_s32"><div>float32_t <b><b>vcvts_n_f32_s32</b></b> (int32_t a, const int n)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvts_n_f32_u32" type="checkbox"><label for="vcvts_n_f32_u32"><div>float32_t <b><b>vcvts_n_f32_u32</b></b> (uint32_t a, const int n)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Sd,Sn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ 1 &lt;&lt; n &lt;&lt; 32 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_f64_s64" type="checkbox"><label for="vcvt_n_f64_s64"><div>float64x1_t <b><b>vcvt_n_f64_s64</b></b> (int64x1_t a, const int n)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_f64_s64" type="checkbox"><label for="vcvtq_n_f64_s64"><div>float64x2_t <b><b>vcvtq_n_f64_s64</b></b> (int64x2_t a, const int n)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_n_f64_u64" type="checkbox"><label for="vcvt_n_f64_u64"><div>float64x1_t <b><b>vcvt_n_f64_u64</b></b> (uint64x1_t a, const int n)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtq_n_f64_u64" type="checkbox"><label for="vcvtq_n_f64_u64"><div>float64x2_t <b><b>vcvtq_n_f64_u64</b></b> (uint64x2_t a, const int n)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Vd.2D,Vn.2D,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_n_f64_s64" type="checkbox"><label for="vcvtd_n_f64_s64"><div>float64_t <b><b>vcvtd_n_f64_s64</b></b> (int64_t a, const int n)<span class="right">Signed integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/scvtf-vector-integer-signed-integer-convert-to-floating-point-vector">SCVTF</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtd_n_f64_u64" type="checkbox"><label for="vcvtd_n_f64_u64"><div>float64_t <b><b>vcvtd_n_f64_u64</b></b> (uint64_t a, const int n)<span class="right">Unsigned integer convert to floating-point</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ucvtf-vector-integer-unsigned-integer-convert-to-floating-point-vector">UCVTF</a> Dd,Dn,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ 1 &lt;&lt; n &lt;&lt; 64 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundingMode.1" title="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR);
+ bits(esize) element;
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FixedToFP.5" title="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding)">FixedToFP</a>(element, 0, unsigned, FPCR, rounding);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f16_f32" type="checkbox"><label for="vcvt_f16_f32"><div>float16x4_t <b><b>vcvt_f16_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to lower precision narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&amp;FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtn-fcvtn2-floating-point-convert-to-lower-precision-narrow-vector">FCVTN</a> Vd.4H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_high_f16_f32" type="checkbox"><label for="vcvt_high_f16_f32"><div>float16x8_t <b><b>vcvt_high_f16_f32</b></b> (float16x4_t r, float32x4_t a)<span class="right">Floating-point convert to lower precision narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&amp;FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtn-fcvtn2-floating-point-convert-to-lower-precision-narrow-vector">FCVTN2</a> Vd.8H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f32_f64" type="checkbox"><label for="vcvt_f32_f64"><div>float32x2_t <b><b>vcvt_f32_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to lower precision narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&amp;FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtn-fcvtn2-floating-point-convert-to-lower-precision-narrow-vector">FCVTN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_high_f32_f64" type="checkbox"><label for="vcvt_high_f32_f64"><div>float32x4_t <b><b>vcvt_high_f32_f64</b></b> (float32x2_t r, float64x2_t a)<span class="right">Floating-point convert to lower precision narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&amp;FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtn-fcvtn2-floating-point-convert-to-lower-precision-narrow-vector">FCVTN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f32_f16" type="checkbox"><label for="vcvt_f32_f16"><div>float32x4_t <b><b>vcvt_f32_f16</b></b> (float16x4_t a)<span class="right">Floating-point convert to higher precision long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&amp;FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes each result to the equivalent element of the vector in the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtl-fcvtl2-floating-point-convert-to-higher-precision-long-vector">FCVTL</a> Vd.4S,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_high_f32_f16" type="checkbox"><label for="vcvt_high_f32_f16"><div>float32x4_t <b><b>vcvt_high_f32_f16</b></b> (float16x8_t a)<span class="right">Floating-point convert to higher precision long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&amp;FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes each result to the equivalent element of the vector in the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtl-fcvtl2-floating-point-convert-to-higher-precision-long-vector">FCVTL2</a> Vd.4S,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_f64_f32" type="checkbox"><label for="vcvt_f64_f32"><div>float64x2_t <b><b>vcvt_f64_f32</b></b> (float32x2_t a)<span class="right">Floating-point convert to higher precision long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&amp;FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes each result to the equivalent element of the vector in the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtl-fcvtl2-floating-point-convert-to-higher-precision-long-vector">FCVTL</a> Vd.2D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvt_high_f64_f32" type="checkbox"><label for="vcvt_high_f64_f32"><div>float64x2_t <b><b>vcvt_high_f64_f32</b></b> (float32x4_t a)<span class="right">Floating-point convert to higher precision long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&amp;FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes each result to the equivalent element of the vector in the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtl-fcvtl2-floating-point-convert-to-higher-precision-long-vector">FCVTL2</a> Vd.2D,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(2*datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.2" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtx_f32_f64" type="checkbox"><label for="vcvtx_f32_f64"><div>float32x2_t <b><b>vcvtx_f32_f64</b></b> (float64x2_t a)<span class="right">Floating-point convert to lower precision narrow, rounding to odd</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&amp;FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtxn-fcvtxn2-floating-point-convert-to-lower-precision-narrow-rounding-to-odd-vector">FCVTXN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.3" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding_ODD" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtxd_f32_f64" type="checkbox"><label for="vcvtxd_f32_f64"><div>float32_t <b><b>vcvtxd_f32_f64</b></b> (float64_t a)<span class="right">Floating-point convert to lower precision narrow, rounding to odd</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&amp;FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtxn-fcvtxn2-floating-point-convert-to-lower-precision-narrow-rounding-to-odd-vector">FCVTXN</a> Sd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.3" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding_ODD" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcvtx_high_f32_f64" type="checkbox"><label for="vcvtx_high_f32_f64"><div>float32x4_t <b><b>vcvtx_high_f32_f64</b></b> (float32x2_t r, float64x2_t a)<span class="right">Floating-point convert to lower precision narrow, rounding to odd</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&amp;FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fcvtxn-fcvtxn2-floating-point-convert-to-lower-precision-narrow-rounding-to-odd-vector">FCVTXN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPConvert.3" title="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding)">FPConvert</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#FPRounding_ODD" title="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF,
+  FPRounding_NEGINF,  FPRounding_ZERO,
+  FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrnd_f32" type="checkbox"><label for="vrnd_f32"><div>float32x2_t <b><b>vrnd_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral, toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintz-vector-floating-point-round-to-integral-toward-zero-vector">FRINTZ</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndq_f32" type="checkbox"><label for="vrndq_f32"><div>float32x4_t <b><b>vrndq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral, toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintz-vector-floating-point-round-to-integral-toward-zero-vector">FRINTZ</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrnd_f64" type="checkbox"><label for="vrnd_f64"><div>float64x1_t <b><b>vrnd_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral, toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintz-vector-floating-point-round-to-integral-toward-zero-vector">FRINTZ</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndq_f64" type="checkbox"><label for="vrndq_f64"><div>float64x2_t <b><b>vrndq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral, toward zero</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintz-vector-floating-point-round-to-integral-toward-zero-vector">FRINTZ</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndn_f32" type="checkbox"><label for="vrndn_f32"><div>float32x2_t <b><b>vrndn_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral, to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintn-vector-floating-point-round-to-integral-to-nearest-with-ties-to-even-vector">FRINTN</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndnq_f32" type="checkbox"><label for="vrndnq_f32"><div>float32x4_t <b><b>vrndnq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral, to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintn-vector-floating-point-round-to-integral-to-nearest-with-ties-to-even-vector">FRINTN</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndn_f64" type="checkbox"><label for="vrndn_f64"><div>float64x1_t <b><b>vrndn_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral, to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintn-vector-floating-point-round-to-integral-to-nearest-with-ties-to-even-vector">FRINTN</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndnq_f64" type="checkbox"><label for="vrndnq_f64"><div>float64x2_t <b><b>vrndnq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral, to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintn-vector-floating-point-round-to-integral-to-nearest-with-ties-to-even-vector">FRINTN</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndns_f32" type="checkbox"><label for="vrndns_f32"><div>float32_t <b><b>vrndns_f32</b></b> (float32_t a)<span class="right">Floating-point round to integral, to nearest with ties to even</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintn-vector-floating-point-round-to-integral-to-nearest-with-ties-to-even-vector">FRINTN</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndm_f32" type="checkbox"><label for="vrndm_f32"><div>float32x2_t <b><b>vrndm_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral, toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintm-vector-floating-point-round-to-integral-toward-minus-infinity-vector">FRINTM</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndmq_f32" type="checkbox"><label for="vrndmq_f32"><div>float32x4_t <b><b>vrndmq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral, toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintm-vector-floating-point-round-to-integral-toward-minus-infinity-vector">FRINTM</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndm_f64" type="checkbox"><label for="vrndm_f64"><div>float64x1_t <b><b>vrndm_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral, toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintm-vector-floating-point-round-to-integral-toward-minus-infinity-vector">FRINTM</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndmq_f64" type="checkbox"><label for="vrndmq_f64"><div>float64x2_t <b><b>vrndmq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral, toward minus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintm-vector-floating-point-round-to-integral-toward-minus-infinity-vector">FRINTM</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndp_f32" type="checkbox"><label for="vrndp_f32"><div>float32x2_t <b><b>vrndp_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral, toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintp-vector-floating-point-round-to-integral-toward-plus-infinity-vector">FRINTP</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndpq_f32" type="checkbox"><label for="vrndpq_f32"><div>float32x4_t <b><b>vrndpq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral, toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintp-vector-floating-point-round-to-integral-toward-plus-infinity-vector">FRINTP</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndp_f64" type="checkbox"><label for="vrndp_f64"><div>float64x1_t <b><b>vrndp_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral, toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintp-vector-floating-point-round-to-integral-toward-plus-infinity-vector">FRINTP</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndpq_f64" type="checkbox"><label for="vrndpq_f64"><div>float64x2_t <b><b>vrndpq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral, toward plus infinity</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintp-vector-floating-point-round-to-integral-toward-plus-infinity-vector">FRINTP</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrnda_f32" type="checkbox"><label for="vrnda_f32"><div>float32x2_t <b><b>vrnda_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral, to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinta-vector-floating-point-round-to-integral-to-nearest-with-ties-to-away-vector">FRINTA</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndaq_f32" type="checkbox"><label for="vrndaq_f32"><div>float32x4_t <b><b>vrndaq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral, to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinta-vector-floating-point-round-to-integral-to-nearest-with-ties-to-away-vector">FRINTA</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrnda_f64" type="checkbox"><label for="vrnda_f64"><div>float64x1_t <b><b>vrnda_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral, to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinta-vector-floating-point-round-to-integral-to-nearest-with-ties-to-away-vector">FRINTA</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndaq_f64" type="checkbox"><label for="vrndaq_f64"><div>float64x2_t <b><b>vrndaq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral, to nearest with ties to away</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinta-vector-floating-point-round-to-integral-to-nearest-with-ties-to-away-vector">FRINTA</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndi_f32" type="checkbox"><label for="vrndi_f32"><div>float32x2_t <b><b>vrndi_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinti-vector-floating-point-round-to-integral-using-current-rounding-mode-vector">FRINTI</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndiq_f32" type="checkbox"><label for="vrndiq_f32"><div>float32x4_t <b><b>vrndiq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinti-vector-floating-point-round-to-integral-using-current-rounding-mode-vector">FRINTI</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndi_f64" type="checkbox"><label for="vrndi_f64"><div>float64x1_t <b><b>vrndi_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinti-vector-floating-point-round-to-integral-using-current-rounding-mode-vector">FRINTI</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndiq_f64" type="checkbox"><label for="vrndiq_f64"><div>float64x2_t <b><b>vrndiq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frinti-vector-floating-point-round-to-integral-using-current-rounding-mode-vector">FRINTI</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndx_f32" type="checkbox"><label for="vrndx_f32"><div>float32x2_t <b><b>vrndx_f32</b></b> (float32x2_t a)<span class="right">Floating-point round to integral exact, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintx-vector-floating-point-round-to-integral-exact-using-current-rounding-mode-vector">FRINTX</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndxq_f32" type="checkbox"><label for="vrndxq_f32"><div>float32x4_t <b><b>vrndxq_f32</b></b> (float32x4_t a)<span class="right">Floating-point round to integral exact, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintx-vector-floating-point-round-to-integral-exact-using-current-rounding-mode-vector">FRINTX</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrndx_f64" type="checkbox"><label for="vrndx_f64"><div>float64x1_t <b><b>vrndx_f64</b></b> (float64x1_t a)<span class="right">Floating-point round to integral exact, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintx-vector-floating-point-round-to-integral-exact-using-current-rounding-mode-vector">FRINTX</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrndxq_f64" type="checkbox"><label for="vrndxq_f64"><div>float64x2_t <b><b>vrndxq_f64</b></b> (float64x2_t a)<span class="right">Floating-point round to integral exact, using current rounding mode</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values of the same size using the rounding mode that is determined by the <a class="armarm-xref" title="Reference to ARM ARM section">FPCR</a>, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frintx-vector-floating-point-round-to-integral-exact-using-current-rounding-mode-vector">FRINTX</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRoundInt.4" title="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(element, FPCR, rounding, exact);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_s16" type="checkbox"><label for="vmovn_s16"><div>int8x8_t <b><b>vmovn_s16</b></b> (int16x8_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN</a> Vd.8B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_s32" type="checkbox"><label for="vmovn_s32"><div>int16x4_t <b><b>vmovn_s32</b></b> (int32x4_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN</a> Vd.4H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_s64" type="checkbox"><label for="vmovn_s64"><div>int32x2_t <b><b>vmovn_s64</b></b> (int64x2_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_u16" type="checkbox"><label for="vmovn_u16"><div>uint8x8_t <b><b>vmovn_u16</b></b> (uint16x8_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN</a> Vd.8B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_u32" type="checkbox"><label for="vmovn_u32"><div>uint16x4_t <b><b>vmovn_u32</b></b> (uint32x4_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN</a> Vd.4H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_u64" type="checkbox"><label for="vmovn_u64"><div>uint32x2_t <b><b>vmovn_u64</b></b> (uint64x2_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_high_s16" type="checkbox"><label for="vmovn_high_s16"><div>int8x16_t <b><b>vmovn_high_s16</b></b> (int8x8_t r, int16x8_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN2</a> Vd.16B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_high_s32" type="checkbox"><label for="vmovn_high_s32"><div>int16x8_t <b><b>vmovn_high_s32</b></b> (int16x4_t r, int32x4_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN2</a> Vd.8H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_high_s64" type="checkbox"><label for="vmovn_high_s64"><div>int32x4_t <b><b>vmovn_high_s64</b></b> (int32x2_t r, int64x2_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_high_u16" type="checkbox"><label for="vmovn_high_u16"><div>uint8x16_t <b><b>vmovn_high_u16</b></b> (uint8x8_t r, uint16x8_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN2</a> Vd.16B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_high_u32" type="checkbox"><label for="vmovn_high_u32"><div>uint16x8_t <b><b>vmovn_high_u32</b></b> (uint16x4_t r, uint32x4_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN2</a> Vd.8H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovn_high_u64" type="checkbox"><label for="vmovn_high_u64"><div>uint32x4_t <b><b>vmovn_high_u64</b></b> (uint32x2_t r, uint64x2_t a)<span class="right">Extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/xtn-xtn2-extract-narrow">XTN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_s8" type="checkbox"><label for="vmovl_s8"><div>int16x8_t <b><b>vmovl_s8</b></b> (int8x8_t a)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL</a> Vd.8H,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_s16" type="checkbox"><label for="vmovl_s16"><div>int32x4_t <b><b>vmovl_s16</b></b> (int16x4_t a)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL</a> Vd.4S,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_s32" type="checkbox"><label for="vmovl_s32"><div>int64x2_t <b><b>vmovl_s32</b></b> (int32x2_t a)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL</a> Vd.2D,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_u8" type="checkbox"><label for="vmovl_u8"><div>uint16x8_t <b><b>vmovl_u8</b></b> (uint8x8_t a)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL</a> Vd.8H,Vn.8B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_u16" type="checkbox"><label for="vmovl_u16"><div>uint32x4_t <b><b>vmovl_u16</b></b> (uint16x4_t a)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL</a> Vd.4S,Vn.4H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_u32" type="checkbox"><label for="vmovl_u32"><div>uint64x2_t <b><b>vmovl_u32</b></b> (uint32x2_t a)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL</a> Vd.2D,Vn.2S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_high_s8" type="checkbox"><label for="vmovl_high_s8"><div>int16x8_t <b><b>vmovl_high_s8</b></b> (int8x16_t a)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL2</a> Vd.8H,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_high_s16" type="checkbox"><label for="vmovl_high_s16"><div>int32x4_t <b><b>vmovl_high_s16</b></b> (int16x8_t a)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL2</a> Vd.4S,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_high_s32" type="checkbox"><label for="vmovl_high_s32"><div>int64x2_t <b><b>vmovl_high_s32</b></b> (int32x4_t a)<span class="right">Signed shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&amp;FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sshll-sshll2-signed-shift-left-long-immediate">SSHLL2</a> Vd.2D,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_high_u8" type="checkbox"><label for="vmovl_high_u8"><div>uint16x8_t <b><b>vmovl_high_u8</b></b> (uint8x16_t a)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL2</a> Vd.8H,Vn.16B,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_high_u16" type="checkbox"><label for="vmovl_high_u16"><div>uint32x4_t <b><b>vmovl_high_u16</b></b> (uint16x8_t a)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL2</a> Vd.4S,Vn.8H,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovl_high_u32" type="checkbox"><label for="vmovl_high_u32"><div>uint64x2_t <b><b>vmovl_high_u32</b></b> (uint32x4_t a)<span class="right">Unsigned shift left long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&amp;FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ushll-ushll2-unsigned-shift-left-long-immediate">USHLL2</a> Vd.2D,Vn.4S,#0
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize*2) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) &lt;&lt; shift;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_s16" type="checkbox"><label for="vqmovn_s16"><div>int8x8_t <b><b>vqmovn_s16</b></b> (int16x8_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN</a> Vd.8B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_s32" type="checkbox"><label for="vqmovn_s32"><div>int16x4_t <b><b>vqmovn_s32</b></b> (int32x4_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN</a> Vd.4H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_s64" type="checkbox"><label for="vqmovn_s64"><div>int32x2_t <b><b>vqmovn_s64</b></b> (int64x2_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_u16" type="checkbox"><label for="vqmovn_u16"><div>uint8x8_t <b><b>vqmovn_u16</b></b> (uint16x8_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN</a> Vd.8B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_u32" type="checkbox"><label for="vqmovn_u32"><div>uint16x4_t <b><b>vqmovn_u32</b></b> (uint32x4_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN</a> Vd.4H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_u64" type="checkbox"><label for="vqmovn_u64"><div>uint32x2_t <b><b>vqmovn_u64</b></b> (uint64x2_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovnh_s16" type="checkbox"><label for="vqmovnh_s16"><div>int8_t <b><b>vqmovnh_s16</b></b> (int16_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN</a> Bd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovns_s32" type="checkbox"><label for="vqmovns_s32"><div>int16_t <b><b>vqmovns_s32</b></b> (int32_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN</a> Hd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovnd_s64" type="checkbox"><label for="vqmovnd_s64"><div>int32_t <b><b>vqmovnd_s64</b></b> (int64_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN</a> Sd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovnh_u16" type="checkbox"><label for="vqmovnh_u16"><div>uint8_t <b><b>vqmovnh_u16</b></b> (uint16_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN</a> Bd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovns_u32" type="checkbox"><label for="vqmovns_u32"><div>uint16_t <b><b>vqmovns_u32</b></b> (uint32_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN</a> Hd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovnd_u64" type="checkbox"><label for="vqmovnd_u64"><div>uint32_t <b><b>vqmovnd_u64</b></b> (uint64_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN</a> Sd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_high_s16" type="checkbox"><label for="vqmovn_high_s16"><div>int8x16_t <b><b>vqmovn_high_s16</b></b> (int8x8_t r, int16x8_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN2</a> Vd.16B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_high_s32" type="checkbox"><label for="vqmovn_high_s32"><div>int16x8_t <b><b>vqmovn_high_s32</b></b> (int16x4_t r, int32x4_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN2</a> Vd.8H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_high_s64" type="checkbox"><label for="vqmovn_high_s64"><div>int32x4_t <b><b>vqmovn_high_s64</b></b> (int32x2_t r, int64x2_t a)<span class="right">Signed saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtn-sqxtn2-signed-saturating-extract-narrow">SQXTN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_high_u16" type="checkbox"><label for="vqmovn_high_u16"><div>uint8x16_t <b><b>vqmovn_high_u16</b></b> (uint8x8_t r, uint16x8_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN2</a> Vd.16B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_high_u32" type="checkbox"><label for="vqmovn_high_u32"><div>uint16x8_t <b><b>vqmovn_high_u32</b></b> (uint16x4_t r, uint32x4_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN2</a> Vd.8H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovn_high_u64" type="checkbox"><label for="vqmovn_high_u64"><div>uint32x4_t <b><b>vqmovn_high_u64</b></b> (uint32x2_t r, uint64x2_t a)<span class="right">Unsigned saturating extract narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&amp;FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uqxtn-uqxtn2-unsigned-saturating-extract-narrow">UQXTN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(element, unsigned), esize, unsigned);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovun_s16" type="checkbox"><label for="vqmovun_s16"><div>uint8x8_t <b><b>vqmovun_s16</b></b> (int16x8_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN</a> Vd.8B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovun_s32" type="checkbox"><label for="vqmovun_s32"><div>uint16x4_t <b><b>vqmovun_s32</b></b> (int32x4_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN</a> Vd.4H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovun_s64" type="checkbox"><label for="vqmovun_s64"><div>uint32x2_t <b><b>vqmovun_s64</b></b> (int64x2_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN</a> Vd.2S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqmovunh_s16" type="checkbox"><label for="vqmovunh_s16"><div>uint8_t <b><b>vqmovunh_s16</b></b> (int16_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN</a> Bd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovuns_s32" type="checkbox"><label for="vqmovuns_s32"><div>uint16_t <b><b>vqmovuns_s32</b></b> (int32_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN</a> Hd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovund_s64" type="checkbox"><label for="vqmovund_s64"><div>uint32_t <b><b>vqmovund_s64</b></b> (int64_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN</a> Sd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovun_high_s16" type="checkbox"><label for="vqmovun_high_s16"><div>uint8x16_t <b><b>vqmovun_high_s16</b></b> (uint8x8_t r, int16x8_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN2</a> Vd.16B,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.8B <br />
+ a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovun_high_s32" type="checkbox"><label for="vqmovun_high_s32"><div>uint16x8_t <b><b>vqmovun_high_s32</b></b> (uint16x4_t r, int32x4_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN2</a> Vd.8H,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.4H <br />
+ a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqmovun_high_s64" type="checkbox"><label for="vqmovun_high_s64"><div>uint32x4_t <b><b>vqmovun_high_s64</b></b> (uint32x2_t r, int64x2_t a)<span class="right">Signed saturating extract unsigned narrow</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&amp;FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. The destination vector elements are half as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqxtun-sqxtun2-signed-saturating-extract-unsigned-narrow">SQXTUN2</a> Vd.4S,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>r &rarr; Vd.2S <br />
+ a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(2*datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(2*esize) element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize];
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedSatQ.2" title="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(element), esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.write.2" title="accessor: Vpart[integer n, integer part] = bits(width) value">Vpart</a>[d, part] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_lane_s16" type="checkbox"><label for="vmla_lane_s16"><div>int16x4_t <b><b>vmla_lane_s16</b></b> (int16x4_t a, int16x4_t b, int16x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_lane_s16" type="checkbox"><label for="vmlaq_lane_s16"><div>int16x8_t <b><b>vmlaq_lane_s16</b></b> (int16x8_t a, int16x8_t b, int16x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_lane_s32" type="checkbox"><label for="vmla_lane_s32"><div>int32x2_t <b><b>vmla_lane_s32</b></b> (int32x2_t a, int32x2_t b, int32x2_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_lane_s32" type="checkbox"><label for="vmlaq_lane_s32"><div>int32x4_t <b><b>vmlaq_lane_s32</b></b> (int32x4_t a, int32x4_t b, int32x2_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_lane_u16" type="checkbox"><label for="vmla_lane_u16"><div>uint16x4_t <b><b>vmla_lane_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_lane_u16" type="checkbox"><label for="vmlaq_lane_u16"><div>uint16x8_t <b><b>vmlaq_lane_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_lane_u32" type="checkbox"><label for="vmla_lane_u32"><div>uint32x2_t <b><b>vmla_lane_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_lane_u32" type="checkbox"><label for="vmlaq_lane_u32"><div>uint32x4_t <b><b>vmlaq_lane_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_lane_f32" type="checkbox"><label for="vmla_lane_f32"><div>float32x2_t <b><b>vmla_lane_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)<span class="right">Undefined</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_lane_f32" type="checkbox"><label for="vmlaq_lane_f32"><div>float32x4_t <b><b>vmlaq_lane_f32</b></b> (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)<span class="right">Undefined</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_laneq_s16" type="checkbox"><label for="vmla_laneq_s16"><div>int16x4_t <b><b>vmla_laneq_s16</b></b> (int16x4_t a, int16x4_t b, int16x8_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_laneq_s16" type="checkbox"><label for="vmlaq_laneq_s16"><div>int16x8_t <b><b>vmlaq_laneq_s16</b></b> (int16x8_t a, int16x8_t b, int16x8_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_laneq_s32" type="checkbox"><label for="vmla_laneq_s32"><div>int32x2_t <b><b>vmla_laneq_s32</b></b> (int32x2_t a, int32x2_t b, int32x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_laneq_s32" type="checkbox"><label for="vmlaq_laneq_s32"><div>int32x4_t <b><b>vmlaq_laneq_s32</b></b> (int32x4_t a, int32x4_t b, int32x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_laneq_u16" type="checkbox"><label for="vmla_laneq_u16"><div>uint16x4_t <b><b>vmla_laneq_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_laneq_u16" type="checkbox"><label for="vmlaq_laneq_u16"><div>uint16x8_t <b><b>vmlaq_laneq_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_laneq_u32" type="checkbox"><label for="vmla_laneq_u32"><div>uint32x2_t <b><b>vmla_laneq_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_laneq_u32" type="checkbox"><label for="vmlaq_laneq_u32"><div>uint32x4_t <b><b>vmlaq_laneq_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_laneq_f32" type="checkbox"><label for="vmla_laneq_f32"><div>float32x2_t <b><b>vmla_laneq_f32</b></b> (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)<span class="right">Undefined</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_laneq_f32" type="checkbox"><label for="vmlaq_laneq_f32"><div>float32x4_t <b><b>vmlaq_laneq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)<span class="right">Undefined</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_lane_s16" type="checkbox"><label for="vmlal_lane_s16"><div>int32x4_t <b><b>vmlal_lane_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_lane_s32" type="checkbox"><label for="vmlal_lane_s32"><div>int64x2_t <b><b>vmlal_lane_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_lane_u16" type="checkbox"><label for="vmlal_lane_u16"><div>uint32x4_t <b><b>vmlal_lane_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_lane_u32" type="checkbox"><label for="vmlal_lane_u32"><div>uint64x2_t <b><b>vmlal_lane_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_lane_s16" type="checkbox"><label for="vmlal_high_lane_s16"><div>int32x4_t <b><b>vmlal_high_lane_s16</b></b> (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_lane_s32" type="checkbox"><label for="vmlal_high_lane_s32"><div>int64x2_t <b><b>vmlal_high_lane_s32</b></b> (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_lane_u16" type="checkbox"><label for="vmlal_high_lane_u16"><div>uint32x4_t <b><b>vmlal_high_lane_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_lane_u32" type="checkbox"><label for="vmlal_high_lane_u32"><div>uint64x2_t <b><b>vmlal_high_lane_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_laneq_s16" type="checkbox"><label for="vmlal_laneq_s16"><div>int32x4_t <b><b>vmlal_laneq_s16</b></b> (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_laneq_s32" type="checkbox"><label for="vmlal_laneq_s32"><div>int64x2_t <b><b>vmlal_laneq_s32</b></b> (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_laneq_u16" type="checkbox"><label for="vmlal_laneq_u16"><div>uint32x4_t <b><b>vmlal_laneq_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_laneq_u32" type="checkbox"><label for="vmlal_laneq_u32"><div>uint64x2_t <b><b>vmlal_laneq_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_laneq_s16" type="checkbox"><label for="vmlal_high_laneq_s16"><div>int32x4_t <b><b>vmlal_high_laneq_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_laneq_s32" type="checkbox"><label for="vmlal_high_laneq_s32"><div>int64x2_t <b><b>vmlal_high_laneq_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_laneq_u16" type="checkbox"><label for="vmlal_high_laneq_u16"><div>uint32x4_t <b><b>vmlal_high_laneq_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_laneq_u32" type="checkbox"><label for="vmlal_high_laneq_u32"><div>uint64x2_t <b><b>vmlal_high_laneq_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_lane_s16" type="checkbox"><label for="vqdmlal_lane_s16"><div>int32x4_t <b><b>vqdmlal_lane_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_lane_s32" type="checkbox"><label for="vqdmlal_lane_s32"><div>int64x2_t <b><b>vqdmlal_lane_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlalh_lane_s16" type="checkbox"><label for="vqdmlalh_lane_s16"><div>int32_t <b><b>vqdmlalh_lane_s16</b></b> (int32_t a, int16_t b, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Sd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Hn <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlals_lane_s32" type="checkbox"><label for="vqdmlals_lane_s32"><div>int64_t <b><b>vqdmlals_lane_s32</b></b> (int64_t a, int32_t b, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Dd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_lane_s16" type="checkbox"><label for="vqdmlal_high_lane_s16"><div>int32x4_t <b><b>vqdmlal_high_lane_s16</b></b> (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_lane_s32" type="checkbox"><label for="vqdmlal_high_lane_s32"><div>int64x2_t <b><b>vqdmlal_high_lane_s32</b></b> (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_laneq_s16" type="checkbox"><label for="vqdmlal_laneq_s16"><div>int32x4_t <b><b>vqdmlal_laneq_s16</b></b> (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_laneq_s32" type="checkbox"><label for="vqdmlal_laneq_s32"><div>int64x2_t <b><b>vqdmlal_laneq_s32</b></b> (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlalh_laneq_s16" type="checkbox"><label for="vqdmlalh_laneq_s16"><div>int32_t <b><b>vqdmlalh_laneq_s16</b></b> (int32_t a, int16_t b, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Sd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Hn <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlals_laneq_s32" type="checkbox"><label for="vqdmlals_laneq_s32"><div>int64_t <b><b>vqdmlals_laneq_s32</b></b> (int64_t a, int32_t b, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Dd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_laneq_s16" type="checkbox"><label for="vqdmlal_high_laneq_s16"><div>int32x4_t <b><b>vqdmlal_high_laneq_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_laneq_s32" type="checkbox"><label for="vqdmlal_high_laneq_s32"><div>int64x2_t <b><b>vqdmlal_high_laneq_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_lane_s16" type="checkbox"><label for="vmls_lane_s16"><div>int16x4_t <b><b>vmls_lane_s16</b></b> (int16x4_t a, int16x4_t b, int16x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_lane_s16" type="checkbox"><label for="vmlsq_lane_s16"><div>int16x8_t <b><b>vmlsq_lane_s16</b></b> (int16x8_t a, int16x8_t b, int16x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_lane_s32" type="checkbox"><label for="vmls_lane_s32"><div>int32x2_t <b><b>vmls_lane_s32</b></b> (int32x2_t a, int32x2_t b, int32x2_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_lane_s32" type="checkbox"><label for="vmlsq_lane_s32"><div>int32x4_t <b><b>vmlsq_lane_s32</b></b> (int32x4_t a, int32x4_t b, int32x2_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_lane_u16" type="checkbox"><label for="vmls_lane_u16"><div>uint16x4_t <b><b>vmls_lane_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_lane_u16" type="checkbox"><label for="vmlsq_lane_u16"><div>uint16x8_t <b><b>vmlsq_lane_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_lane_u32" type="checkbox"><label for="vmls_lane_u32"><div>uint32x2_t <b><b>vmls_lane_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_lane_u32" type="checkbox"><label for="vmlsq_lane_u32"><div>uint32x4_t <b><b>vmlsq_lane_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_lane_f32" type="checkbox"><label for="vmls_lane_f32"><div>float32x2_t <b><b>vmls_lane_f32</b></b> (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_lane_f32" type="checkbox"><label for="vmlsq_lane_f32"><div>float32x4_t <b><b>vmlsq_lane_f32</b></b> (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_laneq_s16" type="checkbox"><label for="vmls_laneq_s16"><div>int16x4_t <b><b>vmls_laneq_s16</b></b> (int16x4_t a, int16x4_t b, int16x8_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_laneq_s16" type="checkbox"><label for="vmlsq_laneq_s16"><div>int16x8_t <b><b>vmlsq_laneq_s16</b></b> (int16x8_t a, int16x8_t b, int16x8_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_laneq_s32" type="checkbox"><label for="vmls_laneq_s32"><div>int32x2_t <b><b>vmls_laneq_s32</b></b> (int32x2_t a, int32x2_t b, int32x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_laneq_s32" type="checkbox"><label for="vmlsq_laneq_s32"><div>int32x4_t <b><b>vmlsq_laneq_s32</b></b> (int32x4_t a, int32x4_t b, int32x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_laneq_u16" type="checkbox"><label for="vmls_laneq_u16"><div>uint16x4_t <b><b>vmls_laneq_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_laneq_u16" type="checkbox"><label for="vmlsq_laneq_u16"><div>uint16x8_t <b><b>vmlsq_laneq_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_laneq_u32" type="checkbox"><label for="vmls_laneq_u32"><div>uint32x2_t <b><b>vmls_laneq_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_laneq_u32" type="checkbox"><label for="vmlsq_laneq_u32"><div>uint32x4_t <b><b>vmlsq_laneq_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_laneq_f32" type="checkbox"><label for="vmls_laneq_f32"><div>float32x2_t <b><b>vmls_laneq_f32</b></b> (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_laneq_f32" type="checkbox"><label for="vmlsq_laneq_f32"><div>float32x4_t <b><b>vmlsq_laneq_f32</b></b> (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_lane_s16" type="checkbox"><label for="vmlsl_lane_s16"><div>int32x4_t <b><b>vmlsl_lane_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_lane_s32" type="checkbox"><label for="vmlsl_lane_s32"><div>int64x2_t <b><b>vmlsl_lane_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_lane_u16" type="checkbox"><label for="vmlsl_lane_u16"><div>uint32x4_t <b><b>vmlsl_lane_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_lane_u32" type="checkbox"><label for="vmlsl_lane_u32"><div>uint64x2_t <b><b>vmlsl_lane_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_lane_s16" type="checkbox"><label for="vmlsl_high_lane_s16"><div>int32x4_t <b><b>vmlsl_high_lane_s16</b></b> (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_lane_s32" type="checkbox"><label for="vmlsl_high_lane_s32"><div>int64x2_t <b><b>vmlsl_high_lane_s32</b></b> (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_lane_u16" type="checkbox"><label for="vmlsl_high_lane_u16"><div>uint32x4_t <b><b>vmlsl_high_lane_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_lane_u32" type="checkbox"><label for="vmlsl_high_lane_u32"><div>uint64x2_t <b><b>vmlsl_high_lane_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_laneq_s16" type="checkbox"><label for="vmlsl_laneq_s16"><div>int32x4_t <b><b>vmlsl_laneq_s16</b></b> (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_laneq_s32" type="checkbox"><label for="vmlsl_laneq_s32"><div>int64x2_t <b><b>vmlsl_laneq_s32</b></b> (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_laneq_u16" type="checkbox"><label for="vmlsl_laneq_u16"><div>uint32x4_t <b><b>vmlsl_laneq_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_laneq_u32" type="checkbox"><label for="vmlsl_laneq_u32"><div>uint64x2_t <b><b>vmlsl_laneq_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_laneq_s16" type="checkbox"><label for="vmlsl_high_laneq_s16"><div>int32x4_t <b><b>vmlsl_high_laneq_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_laneq_s32" type="checkbox"><label for="vmlsl_high_laneq_s32"><div>int64x2_t <b><b>vmlsl_high_laneq_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_laneq_u16" type="checkbox"><label for="vmlsl_high_laneq_u16"><div>uint32x4_t <b><b>vmlsl_high_laneq_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_laneq_u32" type="checkbox"><label for="vmlsl_high_laneq_u32"><div>uint64x2_t <b><b>vmlsl_high_laneq_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_lane_s16" type="checkbox"><label for="vqdmlsl_lane_s16"><div>int32x4_t <b><b>vqdmlsl_lane_s16</b></b> (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_lane_s32" type="checkbox"><label for="vqdmlsl_lane_s32"><div>int64x2_t <b><b>vqdmlsl_lane_s32</b></b> (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlslh_lane_s16" type="checkbox"><label for="vqdmlslh_lane_s16"><div>int32_t <b><b>vqdmlslh_lane_s16</b></b> (int32_t a, int16_t b, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Sd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Hn <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsls_lane_s32" type="checkbox"><label for="vqdmlsls_lane_s32"><div>int64_t <b><b>vqdmlsls_lane_s32</b></b> (int64_t a, int32_t b, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Dd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_lane_s16" type="checkbox"><label for="vqdmlsl_high_lane_s16"><div>int32x4_t <b><b>vqdmlsl_high_lane_s16</b></b> (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_lane_s32" type="checkbox"><label for="vqdmlsl_high_lane_s32"><div>int64x2_t <b><b>vqdmlsl_high_lane_s32</b></b> (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_laneq_s16" type="checkbox"><label for="vqdmlsl_laneq_s16"><div>int32x4_t <b><b>vqdmlsl_laneq_s16</b></b> (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_laneq_s32" type="checkbox"><label for="vqdmlsl_laneq_s32"><div>int64x2_t <b><b>vqdmlsl_laneq_s32</b></b> (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlslh_laneq_s16" type="checkbox"><label for="vqdmlslh_laneq_s16"><div>int32_t <b><b>vqdmlslh_laneq_s16</b></b> (int32_t a, int16_t b, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Sd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sd <br />
+ b &rarr; Hn <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsls_laneq_s32" type="checkbox"><label for="vqdmlsls_laneq_s32"><div>int64_t <b><b>vqdmlsls_laneq_s32</b></b> (int64_t a, int32_t b, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Dd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dd <br />
+ b &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_laneq_s16" type="checkbox"><label for="vqdmlsl_high_laneq_s16"><div>int32x4_t <b><b>vqdmlsl_high_laneq_s16</b></b> (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_laneq_s32" type="checkbox"><label for="vqdmlsl_high_laneq_s32"><div>int64x2_t <b><b>vqdmlsl_high_laneq_s32</b></b> (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_n_s16" type="checkbox"><label for="vmul_n_s16"><div>int16x4_t <b><b>vmul_n_s16</b></b> (int16x4_t a, int16_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_n_s16" type="checkbox"><label for="vmulq_n_s16"><div>int16x8_t <b><b>vmulq_n_s16</b></b> (int16x8_t a, int16_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_n_s32" type="checkbox"><label for="vmul_n_s32"><div>int32x2_t <b><b>vmul_n_s32</b></b> (int32x2_t a, int32_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_n_s32" type="checkbox"><label for="vmulq_n_s32"><div>int32x4_t <b><b>vmulq_n_s32</b></b> (int32x4_t a, int32_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_n_u16" type="checkbox"><label for="vmul_n_u16"><div>uint16x4_t <b><b>vmul_n_u16</b></b> (uint16x4_t a, uint16_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_n_u16" type="checkbox"><label for="vmulq_n_u16"><div>uint16x8_t <b><b>vmulq_n_u16</b></b> (uint16x8_t a, uint16_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_n_u32" type="checkbox"><label for="vmul_n_u32"><div>uint32x2_t <b><b>vmul_n_u32</b></b> (uint32x2_t a, uint32_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_n_u32" type="checkbox"><label for="vmulq_n_u32"><div>uint32x4_t <b><b>vmulq_n_u32</b></b> (uint32x4_t a, uint32_t b)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_n_f32" type="checkbox"><label for="vmul_n_f32"><div>float32x2_t <b><b>vmul_n_f32</b></b> (float32x2_t a, float32_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_n_f32" type="checkbox"><label for="vmulq_n_f32"><div>float32x4_t <b><b>vmulq_n_f32</b></b> (float32x4_t a, float32_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_n_f64" type="checkbox"><label for="vmul_n_f64"><div>float64x1_t <b><b>vmul_n_f64</b></b> (float64x1_t a, float64_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Dd,Dn,Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Vm.D[0] </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_n_f64" type="checkbox"><label for="vmulq_n_f64"><div>float64x2_t <b><b>vmulq_n_f64</b></b> (float64x2_t a, float64_t b)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2D,Vn.2D,Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.D[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_lane_s16" type="checkbox"><label for="vmul_lane_s16"><div>int16x4_t <b><b>vmul_lane_s16</b></b> (int16x4_t a, int16x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_lane_s16" type="checkbox"><label for="vmulq_lane_s16"><div>int16x8_t <b><b>vmulq_lane_s16</b></b> (int16x8_t a, int16x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_lane_s32" type="checkbox"><label for="vmul_lane_s32"><div>int32x2_t <b><b>vmul_lane_s32</b></b> (int32x2_t a, int32x2_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_lane_s32" type="checkbox"><label for="vmulq_lane_s32"><div>int32x4_t <b><b>vmulq_lane_s32</b></b> (int32x4_t a, int32x2_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_lane_u16" type="checkbox"><label for="vmul_lane_u16"><div>uint16x4_t <b><b>vmul_lane_u16</b></b> (uint16x4_t a, uint16x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_lane_u16" type="checkbox"><label for="vmulq_lane_u16"><div>uint16x8_t <b><b>vmulq_lane_u16</b></b> (uint16x8_t a, uint16x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_lane_u32" type="checkbox"><label for="vmul_lane_u32"><div>uint32x2_t <b><b>vmul_lane_u32</b></b> (uint32x2_t a, uint32x2_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_lane_u32" type="checkbox"><label for="vmulq_lane_u32"><div>uint32x4_t <b><b>vmulq_lane_u32</b></b> (uint32x4_t a, uint32x2_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_lane_f32" type="checkbox"><label for="vmul_lane_f32"><div>float32x2_t <b><b>vmul_lane_f32</b></b> (float32x2_t a, float32x2_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_lane_f32" type="checkbox"><label for="vmulq_lane_f32"><div>float32x4_t <b><b>vmulq_lane_f32</b></b> (float32x4_t a, float32x2_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmul_lane_f64" type="checkbox"><label for="vmul_lane_f64"><div>float64x1_t <b><b>vmul_lane_f64</b></b> (float64x1_t a, float64x1_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_lane_f64" type="checkbox"><label for="vmulq_lane_f64"><div>float64x2_t <b><b>vmulq_lane_f64</b></b> (float64x2_t a, float64x1_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmuls_lane_f32" type="checkbox"><label for="vmuls_lane_f32"><div>float32_t <b><b>vmuls_lane_f32</b></b> (float32_t a, float32x2_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmuld_lane_f64" type="checkbox"><label for="vmuld_lane_f64"><div>float64_t <b><b>vmuld_lane_f64</b></b> (float64_t a, float64x1_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Dd,Dn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_laneq_s16" type="checkbox"><label for="vmul_laneq_s16"><div>int16x4_t <b><b>vmul_laneq_s16</b></b> (int16x4_t a, int16x8_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_laneq_s16" type="checkbox"><label for="vmulq_laneq_s16"><div>int16x8_t <b><b>vmulq_laneq_s16</b></b> (int16x8_t a, int16x8_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_laneq_s32" type="checkbox"><label for="vmul_laneq_s32"><div>int32x2_t <b><b>vmul_laneq_s32</b></b> (int32x2_t a, int32x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_laneq_s32" type="checkbox"><label for="vmulq_laneq_s32"><div>int32x4_t <b><b>vmulq_laneq_s32</b></b> (int32x4_t a, int32x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_laneq_u16" type="checkbox"><label for="vmul_laneq_u16"><div>uint16x4_t <b><b>vmul_laneq_u16</b></b> (uint16x4_t a, uint16x8_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_laneq_u16" type="checkbox"><label for="vmulq_laneq_u16"><div>uint16x8_t <b><b>vmulq_laneq_u16</b></b> (uint16x8_t a, uint16x8_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_laneq_u32" type="checkbox"><label for="vmul_laneq_u32"><div>uint32x2_t <b><b>vmul_laneq_u32</b></b> (uint32x2_t a, uint32x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_laneq_u32" type="checkbox"><label for="vmulq_laneq_u32"><div>uint32x4_t <b><b>vmulq_laneq_u32</b></b> (uint32x4_t a, uint32x4_t v, const int lane)<span class="right">Multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mul-vector-multiply-vector">MUL</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if poly then
+         product = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2)&lt;esize-1:0&gt;;
+     else
+         product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_laneq_f32" type="checkbox"><label for="vmul_laneq_f32"><div>float32x2_t <b><b>vmul_laneq_f32</b></b> (float32x2_t a, float32x4_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_laneq_f32" type="checkbox"><label for="vmulq_laneq_f32"><div>float32x4_t <b><b>vmulq_laneq_f32</b></b> (float32x4_t a, float32x4_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmul_laneq_f64" type="checkbox"><label for="vmul_laneq_f64"><div>float64x1_t <b><b>vmul_laneq_f64</b></b> (float64x1_t a, float64x2_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmulq_laneq_f64" type="checkbox"><label for="vmulq_laneq_f64"><div>float64x2_t <b><b>vmulq_laneq_f64</b></b> (float64x2_t a, float64x2_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Vd.2D,Vn.2D,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmuls_laneq_f32" type="checkbox"><label for="vmuls_laneq_f32"><div>float32_t <b><b>vmuls_laneq_f32</b></b> (float32_t a, float32x4_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmuld_laneq_f64" type="checkbox"><label for="vmuld_laneq_f64"><div>float64_t <b><b>vmuld_laneq_f64</b></b> (float64_t a, float64x2_t v, const int lane)<span class="right">Floating-point multiply</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmul-vector-floating-point-multiply-vector">FMUL</a> Dd,Dn,Vm.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ v &rarr; Vm.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMul.3" title="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_n_s16" type="checkbox"><label for="vmull_n_s16"><div>int32x4_t <b><b>vmull_n_s16</b></b> (int16x4_t a, int16_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_n_s32" type="checkbox"><label for="vmull_n_s32"><div>int64x2_t <b><b>vmull_n_s32</b></b> (int32x2_t a, int32_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_n_u16" type="checkbox"><label for="vmull_n_u16"><div>uint32x4_t <b><b>vmull_n_u16</b></b> (uint16x4_t a, uint16_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_n_u32" type="checkbox"><label for="vmull_n_u32"><div>uint64x2_t <b><b>vmull_n_u32</b></b> (uint32x2_t a, uint32_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_n_s16" type="checkbox"><label for="vmull_high_n_s16"><div>int32x4_t <b><b>vmull_high_n_s16</b></b> (int16x8_t a, int16_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_n_s32" type="checkbox"><label for="vmull_high_n_s32"><div>int64x2_t <b><b>vmull_high_n_s32</b></b> (int32x4_t a, int32_t b)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_n_u16" type="checkbox"><label for="vmull_high_n_u16"><div>uint32x4_t <b><b>vmull_high_n_u16</b></b> (uint16x8_t a, uint16_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_n_u32" type="checkbox"><label for="vmull_high_n_u32"><div>uint64x2_t <b><b>vmull_high_n_u32</b></b> (uint32x4_t a, uint32_t b)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_lane_s16" type="checkbox"><label for="vmull_lane_s16"><div>int32x4_t <b><b>vmull_lane_s16</b></b> (int16x4_t a, int16x4_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_lane_s32" type="checkbox"><label for="vmull_lane_s32"><div>int64x2_t <b><b>vmull_lane_s32</b></b> (int32x2_t a, int32x2_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_lane_u16" type="checkbox"><label for="vmull_lane_u16"><div>uint32x4_t <b><b>vmull_lane_u16</b></b> (uint16x4_t a, uint16x4_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_lane_u32" type="checkbox"><label for="vmull_lane_u32"><div>uint64x2_t <b><b>vmull_lane_u32</b></b> (uint32x2_t a, uint32x2_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_lane_s16" type="checkbox"><label for="vmull_high_lane_s16"><div>int32x4_t <b><b>vmull_high_lane_s16</b></b> (int16x8_t a, int16x4_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_lane_s32" type="checkbox"><label for="vmull_high_lane_s32"><div>int64x2_t <b><b>vmull_high_lane_s32</b></b> (int32x4_t a, int32x2_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_lane_u16" type="checkbox"><label for="vmull_high_lane_u16"><div>uint32x4_t <b><b>vmull_high_lane_u16</b></b> (uint16x8_t a, uint16x4_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_lane_u32" type="checkbox"><label for="vmull_high_lane_u32"><div>uint64x2_t <b><b>vmull_high_lane_u32</b></b> (uint32x4_t a, uint32x2_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_laneq_s16" type="checkbox"><label for="vmull_laneq_s16"><div>int32x4_t <b><b>vmull_laneq_s16</b></b> (int16x4_t a, int16x8_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_laneq_s32" type="checkbox"><label for="vmull_laneq_s32"><div>int64x2_t <b><b>vmull_laneq_s32</b></b> (int32x2_t a, int32x4_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_laneq_u16" type="checkbox"><label for="vmull_laneq_u16"><div>uint32x4_t <b><b>vmull_laneq_u16</b></b> (uint16x4_t a, uint16x8_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_laneq_u32" type="checkbox"><label for="vmull_laneq_u32"><div>uint64x2_t <b><b>vmull_laneq_u32</b></b> (uint32x2_t a, uint32x4_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_laneq_s16" type="checkbox"><label for="vmull_high_laneq_s16"><div>int32x4_t <b><b>vmull_high_laneq_s16</b></b> (int16x8_t a, int16x8_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_laneq_s32" type="checkbox"><label for="vmull_high_laneq_s32"><div>int64x2_t <b><b>vmull_high_laneq_s32</b></b> (int32x4_t a, int32x4_t v, const int lane)<span class="right">Signed multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smull-smull2-vector-signed-multiply-long-vector">SMULL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_laneq_u16" type="checkbox"><label for="vmull_high_laneq_u16"><div>uint32x4_t <b><b>vmull_high_laneq_u16</b></b> (uint16x8_t a, uint16x8_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_laneq_u32" type="checkbox"><label for="vmull_high_laneq_u32"><div>uint64x2_t <b><b>vmull_high_laneq_u32</b></b> (uint32x4_t a, uint32x4_t v, const int lane)<span class="right">Unsigned multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umull-umull2-vector-unsigned-multiply-long-vector">UMULL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = (element1*element2)&lt;2*esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_n_s16" type="checkbox"><label for="vqdmull_n_s16"><div>int32x4_t <b><b>vqdmull_n_s16</b></b> (int16x4_t a, int16_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_n_s32" type="checkbox"><label for="vqdmull_n_s32"><div>int64x2_t <b><b>vqdmull_n_s32</b></b> (int32x2_t a, int32_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_n_s16" type="checkbox"><label for="vqdmull_high_n_s16"><div>int32x4_t <b><b>vqdmull_high_n_s16</b></b> (int16x8_t a, int16_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_n_s32" type="checkbox"><label for="vqdmull_high_n_s32"><div>int64x2_t <b><b>vqdmull_high_n_s32</b></b> (int32x4_t a, int32_t b)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_lane_s16" type="checkbox"><label for="vqdmull_lane_s16"><div>int32x4_t <b><b>vqdmull_lane_s16</b></b> (int16x4_t a, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_lane_s32" type="checkbox"><label for="vqdmull_lane_s32"><div>int64x2_t <b><b>vqdmull_lane_s32</b></b> (int32x2_t a, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmullh_lane_s16" type="checkbox"><label for="vqdmullh_lane_s16"><div>int32_t <b><b>vqdmullh_lane_s16</b></b> (int16_t a, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Sd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulls_lane_s32" type="checkbox"><label for="vqdmulls_lane_s32"><div>int64_t <b><b>vqdmulls_lane_s32</b></b> (int32_t a, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Dd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_lane_s16" type="checkbox"><label for="vqdmull_high_lane_s16"><div>int32x4_t <b><b>vqdmull_high_lane_s16</b></b> (int16x8_t a, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_lane_s32" type="checkbox"><label for="vqdmull_high_lane_s32"><div>int64x2_t <b><b>vqdmull_high_lane_s32</b></b> (int32x4_t a, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_laneq_s16" type="checkbox"><label for="vqdmull_laneq_s16"><div>int32x4_t <b><b>vqdmull_laneq_s16</b></b> (int16x4_t a, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.4S,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_laneq_s32" type="checkbox"><label for="vqdmull_laneq_s32"><div>int64x2_t <b><b>vqdmull_laneq_s32</b></b> (int32x2_t a, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Vd.2D,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmullh_laneq_s16" type="checkbox"><label for="vqdmullh_laneq_s16"><div>int32_t <b><b>vqdmullh_laneq_s16</b></b> (int16_t a, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Sd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulls_laneq_s32" type="checkbox"><label for="vqdmulls_laneq_s32"><div>int64_t <b><b>vqdmulls_laneq_s32</b></b> (int32_t a, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL</a> Dd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_laneq_s16" type="checkbox"><label for="vqdmull_high_laneq_s16"><div>int32x4_t <b><b>vqdmull_high_laneq_s16</b></b> (int16x8_t a, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.4S,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmull_high_laneq_s32" type="checkbox"><label for="vqdmull_high_laneq_s32"><div>int64x2_t <b><b>vqdmull_high_laneq_s32</b></b> (int32x4_t a, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmull-sqdmull2-vector-signed-saturating-doubling-multiply-long">SQDMULL2</a> Vd.2D,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = product;
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_n_s16" type="checkbox"><label for="vqdmulh_n_s16"><div>int16x4_t <b><b>vqdmulh_n_s16</b></b> (int16x4_t a, int16_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_n_s16" type="checkbox"><label for="vqdmulhq_n_s16"><div>int16x8_t <b><b>vqdmulhq_n_s16</b></b> (int16x8_t a, int16_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_n_s32" type="checkbox"><label for="vqdmulh_n_s32"><div>int32x2_t <b><b>vqdmulh_n_s32</b></b> (int32x2_t a, int32_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_n_s32" type="checkbox"><label for="vqdmulhq_n_s32"><div>int32x4_t <b><b>vqdmulhq_n_s32</b></b> (int32x4_t a, int32_t b)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_lane_s16" type="checkbox"><label for="vqdmulh_lane_s16"><div>int16x4_t <b><b>vqdmulh_lane_s16</b></b> (int16x4_t a, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_lane_s16" type="checkbox"><label for="vqdmulhq_lane_s16"><div>int16x8_t <b><b>vqdmulhq_lane_s16</b></b> (int16x8_t a, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_lane_s32" type="checkbox"><label for="vqdmulh_lane_s32"><div>int32x2_t <b><b>vqdmulh_lane_s32</b></b> (int32x2_t a, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_lane_s32" type="checkbox"><label for="vqdmulhq_lane_s32"><div>int32x4_t <b><b>vqdmulhq_lane_s32</b></b> (int32x4_t a, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhh_lane_s16" type="checkbox"><label for="vqdmulhh_lane_s16"><div>int16_t <b><b>vqdmulhh_lane_s16</b></b> (int16_t a, int16x4_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Hd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhs_lane_s32" type="checkbox"><label for="vqdmulhs_lane_s32"><div>int32_t <b><b>vqdmulhs_lane_s32</b></b> (int32_t a, int32x2_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Sd,Sn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_laneq_s16" type="checkbox"><label for="vqdmulh_laneq_s16"><div>int16x4_t <b><b>vqdmulh_laneq_s16</b></b> (int16x4_t a, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_laneq_s16" type="checkbox"><label for="vqdmulhq_laneq_s16"><div>int16x8_t <b><b>vqdmulhq_laneq_s16</b></b> (int16x8_t a, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulh_laneq_s32" type="checkbox"><label for="vqdmulh_laneq_s32"><div>int32x2_t <b><b>vqdmulh_laneq_s32</b></b> (int32x2_t a, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhq_laneq_s32" type="checkbox"><label for="vqdmulhq_laneq_s32"><div>int32x4_t <b><b>vqdmulhq_laneq_s32</b></b> (int32x4_t a, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhh_laneq_s16" type="checkbox"><label for="vqdmulhh_laneq_s16"><div>int16_t <b><b>vqdmulhh_laneq_s16</b></b> (int16_t a, int16x8_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Hd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmulhs_laneq_s32" type="checkbox"><label for="vqdmulhs_laneq_s32"><div>int32_t <b><b>vqdmulhs_laneq_s32</b></b> (int32_t a, int32x4_t v, const int lane)<span class="right">Signed saturating doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmulh-vector-signed-saturating-doubling-multiply-returning-high-half">SQDMULH</a> Sd,Sn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_n_s16" type="checkbox"><label for="vqrdmulh_n_s16"><div>int16x4_t <b><b>vqrdmulh_n_s16</b></b> (int16x4_t a, int16_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_n_s16" type="checkbox"><label for="vqrdmulhq_n_s16"><div>int16x8_t <b><b>vqrdmulhq_n_s16</b></b> (int16x8_t a, int16_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_n_s32" type="checkbox"><label for="vqrdmulh_n_s32"><div>int32x2_t <b><b>vqrdmulh_n_s32</b></b> (int32x2_t a, int32_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_n_s32" type="checkbox"><label for="vqrdmulhq_n_s32"><div>int32x4_t <b><b>vqrdmulhq_n_s32</b></b> (int32x4_t a, int32_t b)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_lane_s16" type="checkbox"><label for="vqrdmulh_lane_s16"><div>int16x4_t <b><b>vqrdmulh_lane_s16</b></b> (int16x4_t a, int16x4_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_lane_s16" type="checkbox"><label for="vqrdmulhq_lane_s16"><div>int16x8_t <b><b>vqrdmulhq_lane_s16</b></b> (int16x8_t a, int16x4_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_lane_s32" type="checkbox"><label for="vqrdmulh_lane_s32"><div>int32x2_t <b><b>vqrdmulh_lane_s32</b></b> (int32x2_t a, int32x2_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_lane_s32" type="checkbox"><label for="vqrdmulhq_lane_s32"><div>int32x4_t <b><b>vqrdmulhq_lane_s32</b></b> (int32x4_t a, int32x2_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhh_lane_s16" type="checkbox"><label for="vqrdmulhh_lane_s16"><div>int16_t <b><b>vqrdmulhh_lane_s16</b></b> (int16_t a, int16x4_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Hd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ v &rarr; Vm.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhs_lane_s32" type="checkbox"><label for="vqrdmulhs_lane_s32"><div>int32_t <b><b>vqrdmulhs_lane_s32</b></b> (int32_t a, int32x2_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_laneq_s16" type="checkbox"><label for="vqrdmulh_laneq_s16"><div>int16x4_t <b><b>vqrdmulh_laneq_s16</b></b> (int16x4_t a, int16x8_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4H,Vn.4H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_laneq_s16" type="checkbox"><label for="vqrdmulhq_laneq_s16"><div>int16x8_t <b><b>vqrdmulhq_laneq_s16</b></b> (int16x8_t a, int16x8_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.8H,Vn.8H,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulh_laneq_s32" type="checkbox"><label for="vqrdmulh_laneq_s32"><div>int32x2_t <b><b>vqrdmulh_laneq_s32</b></b> (int32x2_t a, int32x4_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.2S,Vn.2S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhq_laneq_s32" type="checkbox"><label for="vqrdmulhq_laneq_s32"><div>int32x4_t <b><b>vqrdmulhq_laneq_s32</b></b> (int32x4_t a, int32x4_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Vd.4S,Vn.4S,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhh_laneq_s16" type="checkbox"><label for="vqrdmulhh_laneq_s16"><div>int16_t <b><b>vqrdmulhh_laneq_s16</b></b> (int16_t a, int16x8_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Hd,Hn,Vm.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn <br />
+ v &rarr; Vm.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqrdmulhs_laneq_s32" type="checkbox"><label for="vqrdmulhs_laneq_s32"><div>int32_t <b><b>vqrdmulhs_laneq_s32</b></b> (int32_t a, int32x4_t v, const int lane)<span class="right">Signed saturating rounding doubling multiply returning high half</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&amp;FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqrdmulh-vector-signed-saturating-rounding-doubling-multiply-returning-high-half">SQRDMULH</a> Sd,Sn,Vm.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ v &rarr; Vm.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ integer round_const = if rounding then 1 &lt;&lt; (esize - 1) else 0;
+ integer element1;
+ integer element2;
+ integer product;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     product = (2 * element1 * element2) + round_const;
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(product &gt;&gt; esize, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmla_n_s16" type="checkbox"><label for="vmla_n_s16"><div>int16x4_t <b><b>vmla_n_s16</b></b> (int16x4_t a, int16x4_t b, int16_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_n_s16" type="checkbox"><label for="vmlaq_n_s16"><div>int16x8_t <b><b>vmlaq_n_s16</b></b> (int16x8_t a, int16x8_t b, int16_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_n_s32" type="checkbox"><label for="vmla_n_s32"><div>int32x2_t <b><b>vmla_n_s32</b></b> (int32x2_t a, int32x2_t b, int32_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_n_s32" type="checkbox"><label for="vmlaq_n_s32"><div>int32x4_t <b><b>vmlaq_n_s32</b></b> (int32x4_t a, int32x4_t b, int32_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_n_u16" type="checkbox"><label for="vmla_n_u16"><div>uint16x4_t <b><b>vmla_n_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_n_u16" type="checkbox"><label for="vmlaq_n_u16"><div>uint16x8_t <b><b>vmlaq_n_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_n_u32" type="checkbox"><label for="vmla_n_u32"><div>uint32x2_t <b><b>vmla_n_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_n_u32" type="checkbox"><label for="vmlaq_n_u32"><div>uint32x4_t <b><b>vmlaq_n_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32_t c)<span class="right">Multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mla-vector-multiply-add-to-accumulator-vector">MLA</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmla_n_f32" type="checkbox"><label for="vmla_n_f32"><div>float32x2_t <b><b>vmla_n_f32</b></b> (float32x2_t a, float32x2_t b, float32_t c)<span class="right">Undefined</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * c) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlaq_n_f32" type="checkbox"><label for="vmlaq_n_f32"><div>float32x4_t <b><b>vmlaq_n_f32</b></b> (float32x4_t a, float32x4_t b, float32_t c)<span class="right">Undefined</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] + (b[i] * c) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_n_s16" type="checkbox"><label for="vmlal_n_s16"><div>int32x4_t <b><b>vmlal_n_s16</b></b> (int32x4_t a, int16x4_t b, int16_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_n_s32" type="checkbox"><label for="vmlal_n_s32"><div>int64x2_t <b><b>vmlal_n_s32</b></b> (int64x2_t a, int32x2_t b, int32_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_n_u16" type="checkbox"><label for="vmlal_n_u16"><div>uint32x4_t <b><b>vmlal_n_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_n_u32" type="checkbox"><label for="vmlal_n_u32"><div>uint64x2_t <b><b>vmlal_n_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_n_s16" type="checkbox"><label for="vmlal_high_n_s16"><div>int32x4_t <b><b>vmlal_high_n_s16</b></b> (int32x4_t a, int16x8_t b, int16_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_n_s32" type="checkbox"><label for="vmlal_high_n_s32"><div>int64x2_t <b><b>vmlal_high_n_s32</b></b> (int64x2_t a, int32x4_t b, int32_t c)<span class="right">Signed multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlal-smlal2-vector-signed-multiply-add-long-vector">SMLAL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_n_u16" type="checkbox"><label for="vmlal_high_n_u16"><div>uint32x4_t <b><b>vmlal_high_n_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlal_high_n_u32" type="checkbox"><label for="vmlal_high_n_u32"><div>uint64x2_t <b><b>vmlal_high_n_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32_t c)<span class="right">Unsigned multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&amp;FP register by the corresponding vector elements of the second source SIMD&amp;FP register, and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlal-umlal2-vector-unsigned-multiply-add-long-vector">UMLAL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_n_s16" type="checkbox"><label for="vqdmlal_n_s16"><div>int32x4_t <b><b>vqdmlal_n_s16</b></b> (int32x4_t a, int16x4_t b, int16_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_n_s32" type="checkbox"><label for="vqdmlal_n_s32"><div>int64x2_t <b><b>vqdmlal_n_s32</b></b> (int64x2_t a, int32x2_t b, int32_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_n_s16" type="checkbox"><label for="vqdmlal_high_n_s16"><div>int32x4_t <b><b>vqdmlal_high_n_s16</b></b> (int32x4_t a, int16x8_t b, int16_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlal_high_n_s32" type="checkbox"><label for="vqdmlal_high_n_s32"><div>int64x2_t <b><b>vqdmlal_high_n_s32</b></b> (int64x2_t a, int32x4_t b, int32_t c)<span class="right">Signed saturating doubling multiply-add long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlal-sqdmlal2-vector-signed-saturating-doubling-multiply-add-long">SQDMLAL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmls_n_s16" type="checkbox"><label for="vmls_n_s16"><div>int16x4_t <b><b>vmls_n_s16</b></b> (int16x4_t a, int16x4_t b, int16_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_n_s16" type="checkbox"><label for="vmlsq_n_s16"><div>int16x8_t <b><b>vmlsq_n_s16</b></b> (int16x8_t a, int16x8_t b, int16_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_n_s32" type="checkbox"><label for="vmls_n_s32"><div>int32x2_t <b><b>vmls_n_s32</b></b> (int32x2_t a, int32x2_t b, int32_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_n_s32" type="checkbox"><label for="vmlsq_n_s32"><div>int32x4_t <b><b>vmlsq_n_s32</b></b> (int32x4_t a, int32x4_t b, int32_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_n_u16" type="checkbox"><label for="vmls_n_u16"><div>uint16x4_t <b><b>vmls_n_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4H,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_n_u16" type="checkbox"><label for="vmlsq_n_u16"><div>uint16x8_t <b><b>vmlsq_n_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.8H,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_n_u32" type="checkbox"><label for="vmls_n_u32"><div>uint32x2_t <b><b>vmls_n_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_n_u32" type="checkbox"><label for="vmlsq_n_u32"><div>uint32x4_t <b><b>vmlsq_n_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mls-vector-multiply-subtract-from-accumulator-vector">MLS</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ bits(esize) product;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     product = (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1)*<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2))&lt;esize-1:0&gt;;
+     if sub_op then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmls_n_f32" type="checkbox"><label for="vmls_n_f32"><div>float32x2_t <b><b>vmls_n_f32</b></b> (float32x2_t a, float32x2_t b, float32_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * c) for i = 0 to 1
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsq_n_f32" type="checkbox"><label for="vmlsq_n_f32"><div>float32x4_t <b><b>vmlsq_n_f32</b></b> (float32x4_t a, float32x4_t b, float32_t c)<span class="right">Multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre>RESULT[I] = a[i] - (b[i] * c) for i = 0 to 3
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; N/A <br />
+ b &rarr; N/A <br />
+ c &rarr; N/A </pre>      <h4>Results</h4>      <pre>N/A &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_n_s16" type="checkbox"><label for="vmlsl_n_s16"><div>int32x4_t <b><b>vmlsl_n_s16</b></b> (int32x4_t a, int16x4_t b, int16_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_n_s32" type="checkbox"><label for="vmlsl_n_s32"><div>int64x2_t <b><b>vmlsl_n_s32</b></b> (int64x2_t a, int32x2_t b, int32_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_n_u16" type="checkbox"><label for="vmlsl_n_u16"><div>uint32x4_t <b><b>vmlsl_n_u16</b></b> (uint32x4_t a, uint16x4_t b, uint16_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_n_u32" type="checkbox"><label for="vmlsl_n_u32"><div>uint64x2_t <b><b>vmlsl_n_u32</b></b> (uint64x2_t a, uint32x2_t b, uint32_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_n_s16" type="checkbox"><label for="vmlsl_high_n_s16"><div>int32x4_t <b><b>vmlsl_high_n_s16</b></b> (int32x4_t a, int16x8_t b, int16_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_n_s32" type="checkbox"><label for="vmlsl_high_n_s32"><div>int64x2_t <b><b>vmlsl_high_n_s32</b></b> (int64x2_t a, int32x4_t b, int32_t c)<span class="right">Signed multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smlsl-smlsl2-vector-signed-multiply-subtract-long-vector">SMLSL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_n_u16" type="checkbox"><label for="vmlsl_high_n_u16"><div>uint32x4_t <b><b>vmlsl_high_n_u16</b></b> (uint32x4_t a, uint16x8_t b, uint16_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmlsl_high_n_u32" type="checkbox"><label for="vmlsl_high_n_u32"><div>uint64x2_t <b><b>vmlsl_high_n_u32</b></b> (uint64x2_t a, uint32x4_t b, uint32_t c)<span class="right">Unsigned multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&amp;FP registers, and subtracts the results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umlsl-umlsl2-vector-unsigned-multiply-subtract-long-vector">UMLSL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ bits(2*esize) accum;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
+     product = (element1*element2)&lt;2*esize-1:0&gt;;
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] - product;
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize] + product;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = accum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_n_s16" type="checkbox"><label for="vqdmlsl_n_s16"><div>int32x4_t <b><b>vqdmlsl_n_s16</b></b> (int32x4_t a, int16x4_t b, int16_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.4S,Vn.4H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_n_s32" type="checkbox"><label for="vqdmlsl_n_s32"><div>int64x2_t <b><b>vqdmlsl_n_s32</b></b> (int64x2_t a, int32x2_t b, int32_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL</a> Vd.2D,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_n_s16" type="checkbox"><label for="vqdmlsl_high_n_s16"><div>int32x4_t <b><b>vqdmlsl_high_n_s16</b></b> (int32x4_t a, int16x8_t b, int16_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.4S,Vn.8H,Vm.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H <br />
+ c &rarr; Vm.H[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqdmlsl_high_n_s32" type="checkbox"><label for="vqdmlsl_high_n_s32"><div>int64x2_t <b><b>vqdmlsl_high_n_s32</b></b> (int64x2_t a, int32x4_t b, int32_t c)<span class="right">Signed saturating doubling multiply-subtract long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqdmlsl-sqdmlsl2-vector-signed-saturating-doubling-multiply-subtract-long">SQDMLSL2</a> Vd.2D,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S <br />
+ c &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(2*datasize) result;
+ integer element1;
+ integer element2;
+ bits(2*esize) product;
+ integer accum;
+ boolean sat1;
+ boolean sat2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
+     (product, sat1) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * element1 * element2, 2 * esize);
+     if sub_op then
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) - <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     else
+         accum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 2*esize]) + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(product);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize], sat2) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(accum, 2 * esize);
+     if sat1 || sat2 then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabs_s8" type="checkbox"><label for="vabs_s8"><div>int8x8_t <b><b>vabs_s8</b></b> (int8x8_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabsq_s8" type="checkbox"><label for="vabsq_s8"><div>int8x16_t <b><b>vabsq_s8</b></b> (int8x16_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabs_s16" type="checkbox"><label for="vabs_s16"><div>int16x4_t <b><b>vabs_s16</b></b> (int16x4_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabsq_s16" type="checkbox"><label for="vabsq_s16"><div>int16x8_t <b><b>vabsq_s16</b></b> (int16x8_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabs_s32" type="checkbox"><label for="vabs_s32"><div>int32x2_t <b><b>vabs_s32</b></b> (int32x2_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabsq_s32" type="checkbox"><label for="vabsq_s32"><div>int32x4_t <b><b>vabsq_s32</b></b> (int32x4_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabs_f32" type="checkbox"><label for="vabs_f32"><div>float32x2_t <b><b>vabs_f32</b></b> (float32x2_t a)<span class="right">Floating-point absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabs-vector-floating-point-absolute-value-vector">FABS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabsq_f32" type="checkbox"><label for="vabsq_f32"><div>float32x4_t <b><b>vabsq_f32</b></b> (float32x4_t a)<span class="right">Floating-point absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabs-vector-floating-point-absolute-value-vector">FABS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vabs_s64" type="checkbox"><label for="vabs_s64"><div>int64x1_t <b><b>vabs_s64</b></b> (int64x1_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabsd_s64" type="checkbox"><label for="vabsd_s64"><div>int64_t <b><b>vabsd_s64</b></b> (int64_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabsq_s64" type="checkbox"><label for="vabsq_s64"><div>int64x2_t <b><b>vabsq_s64</b></b> (int64x2_t a)<span class="right">Absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/abs-absolute-value-vector">ABS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabs_f64" type="checkbox"><label for="vabs_f64"><div>float64x1_t <b><b>vabs_f64</b></b> (float64x1_t a)<span class="right">Floating-point absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabs-vector-floating-point-absolute-value-vector">FABS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vabsq_f64" type="checkbox"><label for="vabsq_f64"><div>float64x2_t <b><b>vabsq_f64</b></b> (float64x2_t a)<span class="right">Floating-point absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fabs-vector-floating-point-absolute-value-vector">FABS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqabs_s8" type="checkbox"><label for="vqabs_s8"><div>int8x8_t <b><b>vqabs_s8</b></b> (int8x8_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqabsq_s8" type="checkbox"><label for="vqabsq_s8"><div>int8x16_t <b><b>vqabsq_s8</b></b> (int8x16_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqabs_s16" type="checkbox"><label for="vqabs_s16"><div>int16x4_t <b><b>vqabs_s16</b></b> (int16x4_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqabsq_s16" type="checkbox"><label for="vqabsq_s16"><div>int16x8_t <b><b>vqabsq_s16</b></b> (int16x8_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqabs_s32" type="checkbox"><label for="vqabs_s32"><div>int32x2_t <b><b>vqabs_s32</b></b> (int32x2_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqabsq_s32" type="checkbox"><label for="vqabsq_s32"><div>int32x4_t <b><b>vqabsq_s32</b></b> (int32x4_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqabs_s64" type="checkbox"><label for="vqabs_s64"><div>int64x1_t <b><b>vqabs_s64</b></b> (int64x1_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqabsq_s64" type="checkbox"><label for="vqabsq_s64"><div>int64x2_t <b><b>vqabsq_s64</b></b> (int64x2_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqabsb_s8" type="checkbox"><label for="vqabsb_s8"><div>int8_t <b><b>vqabsb_s8</b></b> (int8_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Bd,Bn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqabsh_s16" type="checkbox"><label for="vqabsh_s16"><div>int16_t <b><b>vqabsh_s16</b></b> (int16_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Hd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqabss_s32" type="checkbox"><label for="vqabss_s32"><div>int32_t <b><b>vqabss_s32</b></b> (int32_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqabsd_s64" type="checkbox"><label for="vqabsd_s64"><div>int64_t <b><b>vqabsd_s64</b></b> (int64_t a)<span class="right">Signed saturating absolute value</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&amp;FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqabs-signed-saturating-absolute-value">SQABS</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vneg_s8" type="checkbox"><label for="vneg_s8"><div>int8x8_t <b><b>vneg_s8</b></b> (int8x8_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vnegq_s8" type="checkbox"><label for="vnegq_s8"><div>int8x16_t <b><b>vnegq_s8</b></b> (int8x16_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vneg_s16" type="checkbox"><label for="vneg_s16"><div>int16x4_t <b><b>vneg_s16</b></b> (int16x4_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vnegq_s16" type="checkbox"><label for="vnegq_s16"><div>int16x8_t <b><b>vnegq_s16</b></b> (int16x8_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vneg_s32" type="checkbox"><label for="vneg_s32"><div>int32x2_t <b><b>vneg_s32</b></b> (int32x2_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vnegq_s32" type="checkbox"><label for="vnegq_s32"><div>int32x4_t <b><b>vnegq_s32</b></b> (int32x4_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vneg_f32" type="checkbox"><label for="vneg_f32"><div>float32x2_t <b><b>vneg_f32</b></b> (float32x2_t a)<span class="right">Floating-point negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fneg-vector-floating-point-negate-vector">FNEG</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vnegq_f32" type="checkbox"><label for="vnegq_f32"><div>float32x4_t <b><b>vnegq_f32</b></b> (float32x4_t a)<span class="right">Floating-point negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fneg-vector-floating-point-negate-vector">FNEG</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vneg_s64" type="checkbox"><label for="vneg_s64"><div>int64x1_t <b><b>vneg_s64</b></b> (int64x1_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vnegd_s64" type="checkbox"><label for="vnegd_s64"><div>int64_t <b><b>vnegd_s64</b></b> (int64_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vnegq_s64" type="checkbox"><label for="vnegq_s64"><div>int64x2_t <b><b>vnegq_s64</b></b> (int64x2_t a)<span class="right">Negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Negate (vector). This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/neg-vector-negate-vector">NEG</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vneg_f64" type="checkbox"><label for="vneg_f64"><div>float64x1_t <b><b>vneg_f64</b></b> (float64x1_t a)<span class="right">Floating-point negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fneg-vector-floating-point-negate-vector">FNEG</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vnegq_f64" type="checkbox"><label for="vnegq_f64"><div>float64x2_t <b><b>vnegq_f64</b></b> (float64x2_t a)<span class="right">Floating-point negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&amp;FP register, writes the result to a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fneg-vector-floating-point-negate-vector">FNEG</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     if neg then
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element);
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAbs.1" title="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(element);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqneg_s8" type="checkbox"><label for="vqneg_s8"><div>int8x8_t <b><b>vqneg_s8</b></b> (int8x8_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqnegq_s8" type="checkbox"><label for="vqnegq_s8"><div>int8x16_t <b><b>vqnegq_s8</b></b> (int8x16_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqneg_s16" type="checkbox"><label for="vqneg_s16"><div>int16x4_t <b><b>vqneg_s16</b></b> (int16x4_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqnegq_s16" type="checkbox"><label for="vqnegq_s16"><div>int16x8_t <b><b>vqnegq_s16</b></b> (int16x8_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqneg_s32" type="checkbox"><label for="vqneg_s32"><div>int32x2_t <b><b>vqneg_s32</b></b> (int32x2_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqnegq_s32" type="checkbox"><label for="vqnegq_s32"><div>int32x4_t <b><b>vqnegq_s32</b></b> (int32x4_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqneg_s64" type="checkbox"><label for="vqneg_s64"><div>int64x1_t <b><b>vqneg_s64</b></b> (int64x1_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqnegq_s64" type="checkbox"><label for="vqnegq_s64"><div>int64x2_t <b><b>vqnegq_s64</b></b> (int64x2_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqnegb_s8" type="checkbox"><label for="vqnegb_s8"><div>int8_t <b><b>vqnegb_s8</b></b> (int8_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Bd,Bn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Bn </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqnegh_s16" type="checkbox"><label for="vqnegh_s16"><div>int16_t <b><b>vqnegh_s16</b></b> (int16_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Hd,Hn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Hn </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqnegs_s32" type="checkbox"><label for="vqnegs_s32"><div>int32_t <b><b>vqnegs_s32</b></b> (int32_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqnegd_s64" type="checkbox"><label for="vqnegd_s64"><div>int64_t <b><b>vqnegd_s64</b></b> (int64_t a)<span class="right">Signed saturating negate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed saturating Negate. This instruction reads each vector element from the source SIMD&amp;FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sqneg-signed-saturating-negate">SQNEG</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element;
+ boolean sat;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     if neg then
+         element = -element;
+     else
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
+     (<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignedSatQ.2" title="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(element, esize);
+     if sat then FPSR.QC = '1';
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcls_s8" type="checkbox"><label for="vcls_s8"><div>int8x8_t <b><b>vcls_s8</b></b> (int8x8_t a)<span class="right">Count leading sign bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The count does not include the most significant bit itself.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cls-vector-count-leading-sign-bits-vector">CLS</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclsq_s8" type="checkbox"><label for="vclsq_s8"><div>int8x16_t <b><b>vclsq_s8</b></b> (int8x16_t a)<span class="right">Count leading sign bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The count does not include the most significant bit itself.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cls-vector-count-leading-sign-bits-vector">CLS</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcls_s16" type="checkbox"><label for="vcls_s16"><div>int16x4_t <b><b>vcls_s16</b></b> (int16x4_t a)<span class="right">Count leading sign bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The count does not include the most significant bit itself.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cls-vector-count-leading-sign-bits-vector">CLS</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclsq_s16" type="checkbox"><label for="vclsq_s16"><div>int16x8_t <b><b>vclsq_s16</b></b> (int16x8_t a)<span class="right">Count leading sign bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The count does not include the most significant bit itself.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cls-vector-count-leading-sign-bits-vector">CLS</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcls_s32" type="checkbox"><label for="vcls_s32"><div>int32x2_t <b><b>vcls_s32</b></b> (int32x2_t a)<span class="right">Count leading sign bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The count does not include the most significant bit itself.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cls-vector-count-leading-sign-bits-vector">CLS</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclsq_s32" type="checkbox"><label for="vclsq_s32"><div>int32x4_t <b><b>vclsq_s32</b></b> (int32x4_t a)<span class="right">Count leading sign bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The count does not include the most significant bit itself.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cls-vector-count-leading-sign-bits-vector">CLS</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclz_s8" type="checkbox"><label for="vclz_s8"><div>int8x8_t <b><b>vclz_s8</b></b> (int8x8_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclzq_s8" type="checkbox"><label for="vclzq_s8"><div>int8x16_t <b><b>vclzq_s8</b></b> (int8x16_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclz_s16" type="checkbox"><label for="vclz_s16"><div>int16x4_t <b><b>vclz_s16</b></b> (int16x4_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclzq_s16" type="checkbox"><label for="vclzq_s16"><div>int16x8_t <b><b>vclzq_s16</b></b> (int16x8_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclz_s32" type="checkbox"><label for="vclz_s32"><div>int32x2_t <b><b>vclz_s32</b></b> (int32x2_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclzq_s32" type="checkbox"><label for="vclzq_s32"><div>int32x4_t <b><b>vclzq_s32</b></b> (int32x4_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclz_u8" type="checkbox"><label for="vclz_u8"><div>uint8x8_t <b><b>vclz_u8</b></b> (uint8x8_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclzq_u8" type="checkbox"><label for="vclzq_u8"><div>uint8x16_t <b><b>vclzq_u8</b></b> (uint8x16_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclz_u16" type="checkbox"><label for="vclz_u16"><div>uint16x4_t <b><b>vclz_u16</b></b> (uint16x4_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclzq_u16" type="checkbox"><label for="vclzq_u16"><div>uint16x8_t <b><b>vclzq_u16</b></b> (uint16x8_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclz_u32" type="checkbox"><label for="vclz_u32"><div>uint32x2_t <b><b>vclz_u32</b></b> (uint32x2_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vclzq_u32" type="checkbox"><label for="vclzq_u32"><div>uint32x4_t <b><b>vclzq_u32</b></b> (uint32x4_t a)<span class="right">Count leading zero bits</span></div></label><article>      <h4>Description</h4><p><p class="aml">Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/clz-vector-count-leading-zero-bits-vector">CLZ</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     if countop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#CountOp_CLS" title="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</a> then
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     else
+         count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcnt_s8" type="checkbox"><label for="vcnt_s8"><div>int8x8_t <b><b>vcnt_s8</b></b> (int8x8_t a)<span class="right">Population count per byte</span></div></label><article>      <h4>Description</h4><p><p class="aml">Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cnt-population-count-per-byte">CNT</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcntq_s8" type="checkbox"><label for="vcntq_s8"><div>int8x16_t <b><b>vcntq_s8</b></b> (int8x16_t a)<span class="right">Population count per byte</span></div></label><article>      <h4>Description</h4><p><p class="aml">Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cnt-population-count-per-byte">CNT</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcnt_u8" type="checkbox"><label for="vcnt_u8"><div>uint8x8_t <b><b>vcnt_u8</b></b> (uint8x8_t a)<span class="right">Population count per byte</span></div></label><article>      <h4>Description</h4><p><p class="aml">Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cnt-population-count-per-byte">CNT</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcntq_u8" type="checkbox"><label for="vcntq_u8"><div>uint8x16_t <b><b>vcntq_u8</b></b> (uint8x16_t a)<span class="right">Population count per byte</span></div></label><article>      <h4>Description</h4><p><p class="aml">Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cnt-population-count-per-byte">CNT</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcnt_p8" type="checkbox"><label for="vcnt_p8"><div>poly8x8_t <b><b>vcnt_p8</b></b> (poly8x8_t a)<span class="right">Population count per byte</span></div></label><article>      <h4>Description</h4><p><p class="aml">Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cnt-population-count-per-byte">CNT</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcntq_p8" type="checkbox"><label for="vcntq_p8"><div>poly8x16_t <b><b>vcntq_p8</b></b> (poly8x16_t a)<span class="right">Population count per byte</span></div></label><article>      <h4>Description</h4><p><p class="aml">Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cnt-population-count-per-byte">CNT</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ integer count;
+ for e = 0 to elements-1
+     count = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = count&lt;esize-1:0&gt;;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecpe_u32" type="checkbox"><label for="vrecpe_u32"><div>uint32x2_t <b><b>vrecpe_u32</b></b> (uint32x2_t a)<span class="right">Unsigned reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&amp;FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urecpe-unsigned-reciprocal-estimate">URECPE</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(32) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 32];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedRecipEstimate.1" title="function: bits(N) UnsignedRecipEstimate(bits(N) operand)">UnsignedRecipEstimate</a>(element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecpeq_u32" type="checkbox"><label for="vrecpeq_u32"><div>uint32x4_t <b><b>vrecpeq_u32</b></b> (uint32x4_t a)<span class="right">Unsigned reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&amp;FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/urecpe-unsigned-reciprocal-estimate">URECPE</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(32) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 32];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedRecipEstimate.1" title="function: bits(N) UnsignedRecipEstimate(bits(N) operand)">UnsignedRecipEstimate</a>(element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecpe_f32" type="checkbox"><label for="vrecpe_f32"><div>float32x2_t <b><b>vrecpe_f32</b></b> (float32x2_t a)<span class="right">Floating-point reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpe-floating-point-reciprocal-estimate">FRECPE</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecipEstimate.2" title="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr)">FPRecipEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecpeq_f32" type="checkbox"><label for="vrecpeq_f32"><div>float32x4_t <b><b>vrecpeq_f32</b></b> (float32x4_t a)<span class="right">Floating-point reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpe-floating-point-reciprocal-estimate">FRECPE</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecipEstimate.2" title="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr)">FPRecipEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecpe_f64" type="checkbox"><label for="vrecpe_f64"><div>float64x1_t <b><b>vrecpe_f64</b></b> (float64x1_t a)<span class="right">Floating-point reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpe-floating-point-reciprocal-estimate">FRECPE</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecipEstimate.2" title="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr)">FPRecipEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpeq_f64" type="checkbox"><label for="vrecpeq_f64"><div>float64x2_t <b><b>vrecpeq_f64</b></b> (float64x2_t a)<span class="right">Floating-point reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpe-floating-point-reciprocal-estimate">FRECPE</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecipEstimate.2" title="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr)">FPRecipEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpes_f32" type="checkbox"><label for="vrecpes_f32"><div>float32_t <b><b>vrecpes_f32</b></b> (float32_t a)<span class="right">Floating-point reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpe-floating-point-reciprocal-estimate">FRECPE</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecipEstimate.2" title="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr)">FPRecipEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecped_f64" type="checkbox"><label for="vrecped_f64"><div>float64_t <b><b>vrecped_f64</b></b> (float64_t a)<span class="right">Floating-point reciprocal estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpe-floating-point-reciprocal-estimate">FRECPE</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecipEstimate.2" title="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr)">FPRecipEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecps_f32" type="checkbox"><label for="vrecps_f32"><div>float32x2_t <b><b>vrecps_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point reciprocal step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecps-floating-point-reciprocal-step">FRECPS</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRecipStepFused.2" title="function: bits(N) FPRecipStepFused(bits(N) op1, bits(N) op2)">FPRecipStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecpsq_f32" type="checkbox"><label for="vrecpsq_f32"><div>float32x4_t <b><b>vrecpsq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point reciprocal step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecps-floating-point-reciprocal-step">FRECPS</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRecipStepFused.2" title="function: bits(N) FPRecipStepFused(bits(N) op1, bits(N) op2)">FPRecipStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrecps_f64" type="checkbox"><label for="vrecps_f64"><div>float64x1_t <b><b>vrecps_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point reciprocal step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecps-floating-point-reciprocal-step">FRECPS</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRecipStepFused.2" title="function: bits(N) FPRecipStepFused(bits(N) op1, bits(N) op2)">FPRecipStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpsq_f64" type="checkbox"><label for="vrecpsq_f64"><div>float64x2_t <b><b>vrecpsq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point reciprocal step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecps-floating-point-reciprocal-step">FRECPS</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRecipStepFused.2" title="function: bits(N) FPRecipStepFused(bits(N) op1, bits(N) op2)">FPRecipStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpss_f32" type="checkbox"><label for="vrecpss_f32"><div>float32_t <b><b>vrecpss_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point reciprocal step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecps-floating-point-reciprocal-step">FRECPS</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRecipStepFused.2" title="function: bits(N) FPRecipStepFused(bits(N) op1, bits(N) op2)">FPRecipStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpsd_f64" type="checkbox"><label for="vrecpsd_f64"><div>float64_t <b><b>vrecpsd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point reciprocal step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecps-floating-point-reciprocal-step">FRECPS</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRecipStepFused.2" title="function: bits(N) FPRecipStepFused(bits(N) op1, bits(N) op2)">FPRecipStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqrt_f32" type="checkbox"><label for="vsqrt_f32"><div>float32x2_t <b><b>vsqrt_f32</b></b> (float32x2_t a)<span class="right">Floating-point square root</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsqrt-vector-floating-point-square-root-vector">FSQRT</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSqrt.2" title="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqrtq_f32" type="checkbox"><label for="vsqrtq_f32"><div>float32x4_t <b><b>vsqrtq_f32</b></b> (float32x4_t a)<span class="right">Floating-point square root</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsqrt-vector-floating-point-square-root-vector">FSQRT</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSqrt.2" title="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqrt_f64" type="checkbox"><label for="vsqrt_f64"><div>float64x1_t <b><b>vsqrt_f64</b></b> (float64x1_t a)<span class="right">Floating-point square root</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsqrt-vector-floating-point-square-root-vector">FSQRT</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSqrt.2" title="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsqrtq_f64" type="checkbox"><label for="vsqrtq_f64"><div>float64x2_t <b><b>vsqrtq_f64</b></b> (float64x2_t a)<span class="right">Floating-point square root</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fsqrt-vector-floating-point-square-root-vector">FSQRT</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPSqrt.2" title="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrte_u32" type="checkbox"><label for="vrsqrte_u32"><div>uint32x2_t <b><b>vrsqrte_u32</b></b> (uint32x2_t a)<span class="right">Unsigned reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&amp;FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursqrte-unsigned-reciprocal-square-root-estimate">URSQRTE</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(32) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 32];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedRSqrtEstimate.1" title="function: bits(N) UnsignedRSqrtEstimate(bits(N) operand)">UnsignedRSqrtEstimate</a>(element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrteq_u32" type="checkbox"><label for="vrsqrteq_u32"><div>uint32x4_t <b><b>vrsqrteq_u32</b></b> (uint32x4_t a)<span class="right">Unsigned reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&amp;FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ursqrte-unsigned-reciprocal-square-root-estimate">URSQRTE</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(32) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 32];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UnsignedRSqrtEstimate.1" title="function: bits(N) UnsignedRSqrtEstimate(bits(N) operand)">UnsignedRSqrtEstimate</a>(element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrte_f32" type="checkbox"><label for="vrsqrte_f32"><div>float32x2_t <b><b>vrsqrte_f32</b></b> (float32x2_t a)<span class="right">Floating-point reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrte-floating-point-reciprocal-square-root-estimate">FRSQRTE</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRSqrtEstimate.2" title="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr)">FPRSqrtEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrteq_f32" type="checkbox"><label for="vrsqrteq_f32"><div>float32x4_t <b><b>vrsqrteq_f32</b></b> (float32x4_t a)<span class="right">Floating-point reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrte-floating-point-reciprocal-square-root-estimate">FRSQRTE</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRSqrtEstimate.2" title="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr)">FPRSqrtEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrte_f64" type="checkbox"><label for="vrsqrte_f64"><div>float64x1_t <b><b>vrsqrte_f64</b></b> (float64x1_t a)<span class="right">Floating-point reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrte-floating-point-reciprocal-square-root-estimate">FRSQRTE</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRSqrtEstimate.2" title="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr)">FPRSqrtEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrteq_f64" type="checkbox"><label for="vrsqrteq_f64"><div>float64x2_t <b><b>vrsqrteq_f64</b></b> (float64x2_t a)<span class="right">Floating-point reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrte-floating-point-reciprocal-square-root-estimate">FRSQRTE</a> Vd.2D,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRSqrtEstimate.2" title="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr)">FPRSqrtEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrtes_f32" type="checkbox"><label for="vrsqrtes_f32"><div>float32_t <b><b>vrsqrtes_f32</b></b> (float32_t a)<span class="right">Floating-point reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrte-floating-point-reciprocal-square-root-estimate">FRSQRTE</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRSqrtEstimate.2" title="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr)">FPRSqrtEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrted_f64" type="checkbox"><label for="vrsqrted_f64"><div>float64_t <b><b>vrsqrted_f64</b></b> (float64_t a)<span class="right">Floating-point reciprocal square root estimate</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrte-floating-point-reciprocal-square-root-estimate">FRSQRTE</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRSqrtEstimate.2" title="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr)">FPRSqrtEstimate</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrts_f32" type="checkbox"><label for="vrsqrts_f32"><div>float32x2_t <b><b>vrsqrts_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point reciprocal square root step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrts-floating-point-reciprocal-square-root-step">FRSQRTS</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRSqrtStepFused.2" title="function: bits(N) FPRSqrtStepFused(bits(N) op1, bits(N) op2)">FPRSqrtStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrtsq_f32" type="checkbox"><label for="vrsqrtsq_f32"><div>float32x4_t <b><b>vrsqrtsq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point reciprocal square root step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrts-floating-point-reciprocal-square-root-step">FRSQRTS</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRSqrtStepFused.2" title="function: bits(N) FPRSqrtStepFused(bits(N) op1, bits(N) op2)">FPRSqrtStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrts_f64" type="checkbox"><label for="vrsqrts_f64"><div>float64x1_t <b><b>vrsqrts_f64</b></b> (float64x1_t a, float64x1_t b)<span class="right">Floating-point reciprocal square root step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrts-floating-point-reciprocal-square-root-step">FRSQRTS</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRSqrtStepFused.2" title="function: bits(N) FPRSqrtStepFused(bits(N) op1, bits(N) op2)">FPRSqrtStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrtsq_f64" type="checkbox"><label for="vrsqrtsq_f64"><div>float64x2_t <b><b>vrsqrtsq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point reciprocal square root step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrts-floating-point-reciprocal-square-root-step">FRSQRTS</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRSqrtStepFused.2" title="function: bits(N) FPRSqrtStepFused(bits(N) op1, bits(N) op2)">FPRSqrtStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrtss_f32" type="checkbox"><label for="vrsqrtss_f32"><div>float32_t <b><b>vrsqrtss_f32</b></b> (float32_t a, float32_t b)<span class="right">Floating-point reciprocal square root step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrts-floating-point-reciprocal-square-root-step">FRSQRTS</a> Sd,Sn,Sm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn <br />
+ b &rarr; Sm </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRSqrtStepFused.2" title="function: bits(N) FPRSqrtStepFused(bits(N) op1, bits(N) op2)">FPRSqrtStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrsqrtsd_f64" type="checkbox"><label for="vrsqrtsd_f64"><div>float64_t <b><b>vrsqrtsd_f64</b></b> (float64_t a, float64_t b)<span class="right">Floating-point reciprocal square root step</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frsqrts-floating-point-reciprocal-square-root-step">FRSQRTS</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.FPRSqrtStepFused.2" title="function: bits(N) FPRSqrtStepFused(bits(N) op1, bits(N) op2)">FPRSqrtStepFused</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_s8" type="checkbox"><label for="vmvn_s8"><div>int8x8_t <b><b>vmvn_s8</b></b> (int8x8_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_s8" type="checkbox"><label for="vmvnq_s8"><div>int8x16_t <b><b>vmvnq_s8</b></b> (int8x16_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_s16" type="checkbox"><label for="vmvn_s16"><div>int16x4_t <b><b>vmvn_s16</b></b> (int16x4_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_s16" type="checkbox"><label for="vmvnq_s16"><div>int16x8_t <b><b>vmvnq_s16</b></b> (int16x8_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_s32" type="checkbox"><label for="vmvn_s32"><div>int32x2_t <b><b>vmvn_s32</b></b> (int32x2_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_s32" type="checkbox"><label for="vmvnq_s32"><div>int32x4_t <b><b>vmvnq_s32</b></b> (int32x4_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_u8" type="checkbox"><label for="vmvn_u8"><div>uint8x8_t <b><b>vmvn_u8</b></b> (uint8x8_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_u8" type="checkbox"><label for="vmvnq_u8"><div>uint8x16_t <b><b>vmvnq_u8</b></b> (uint8x16_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_u16" type="checkbox"><label for="vmvn_u16"><div>uint16x4_t <b><b>vmvn_u16</b></b> (uint16x4_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_u16" type="checkbox"><label for="vmvnq_u16"><div>uint16x8_t <b><b>vmvnq_u16</b></b> (uint16x8_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_u32" type="checkbox"><label for="vmvn_u32"><div>uint32x2_t <b><b>vmvn_u32</b></b> (uint32x2_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_u32" type="checkbox"><label for="vmvnq_u32"><div>uint32x4_t <b><b>vmvnq_u32</b></b> (uint32x4_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvn_p8" type="checkbox"><label for="vmvn_p8"><div>poly8x8_t <b><b>vmvn_p8</b></b> (poly8x8_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmvnq_p8" type="checkbox"><label for="vmvnq_p8"><div>poly8x16_t <b><b>vmvnq_p8</b></b> (poly8x16_t a)<span class="right">Bitwise NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&amp;FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/mvn-bitwise-not-vector-an-alias-of-not">MVN</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4><p>The description of 
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-simd-and-floating-point-instructions-alphabetic-order/not-bitwise-not-vector">NOT</a> 
+         gives the operational pseudocode for this instruction.</p>      <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_s8" type="checkbox"><label for="vand_s8"><div>int8x8_t <b><b>vand_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_s8" type="checkbox"><label for="vandq_s8"><div>int8x16_t <b><b>vandq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_s16" type="checkbox"><label for="vand_s16"><div>int16x4_t <b><b>vand_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_s16" type="checkbox"><label for="vandq_s16"><div>int16x8_t <b><b>vandq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_s32" type="checkbox"><label for="vand_s32"><div>int32x2_t <b><b>vand_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_s32" type="checkbox"><label for="vandq_s32"><div>int32x4_t <b><b>vandq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_s64" type="checkbox"><label for="vand_s64"><div>int64x1_t <b><b>vand_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Dd,Dn,Dm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn <br />
+ b &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_s64" type="checkbox"><label for="vandq_s64"><div>int64x2_t <b><b>vandq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_u8" type="checkbox"><label for="vand_u8"><div>uint8x8_t <b><b>vand_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_u8" type="checkbox"><label for="vandq_u8"><div>uint8x16_t <b><b>vandq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_u16" type="checkbox"><label for="vand_u16"><div>uint16x4_t <b><b>vand_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_u16" type="checkbox"><label for="vandq_u16"><div>uint16x8_t <b><b>vandq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_u32" type="checkbox"><label for="vand_u32"><div>uint32x2_t <b><b>vand_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_u32" type="checkbox"><label for="vandq_u32"><div>uint32x4_t <b><b>vandq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vand_u64" type="checkbox"><label for="vand_u64"><div>uint64x1_t <b><b>vand_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vandq_u64" type="checkbox"><label for="vandq_u64"><div>uint64x2_t <b><b>vandq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Bitwise AND</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/and-vector-bitwise-and-vector">AND</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_s8" type="checkbox"><label for="vorr_s8"><div>int8x8_t <b><b>vorr_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_s8" type="checkbox"><label for="vorrq_s8"><div>int8x16_t <b><b>vorrq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_s16" type="checkbox"><label for="vorr_s16"><div>int16x4_t <b><b>vorr_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_s16" type="checkbox"><label for="vorrq_s16"><div>int16x8_t <b><b>vorrq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_s32" type="checkbox"><label for="vorr_s32"><div>int32x2_t <b><b>vorr_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_s32" type="checkbox"><label for="vorrq_s32"><div>int32x4_t <b><b>vorrq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_s64" type="checkbox"><label for="vorr_s64"><div>int64x1_t <b><b>vorr_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_s64" type="checkbox"><label for="vorrq_s64"><div>int64x2_t <b><b>vorrq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_u8" type="checkbox"><label for="vorr_u8"><div>uint8x8_t <b><b>vorr_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_u8" type="checkbox"><label for="vorrq_u8"><div>uint8x16_t <b><b>vorrq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_u16" type="checkbox"><label for="vorr_u16"><div>uint16x4_t <b><b>vorr_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_u16" type="checkbox"><label for="vorrq_u16"><div>uint16x8_t <b><b>vorrq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_u32" type="checkbox"><label for="vorr_u32"><div>uint32x2_t <b><b>vorr_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_u32" type="checkbox"><label for="vorrq_u32"><div>uint32x4_t <b><b>vorrq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorr_u64" type="checkbox"><label for="vorr_u64"><div>uint64x1_t <b><b>vorr_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorrq_u64" type="checkbox"><label for="vorrq_u64"><div>uint64x2_t <b><b>vorrq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Bitwise inclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orr-vector-register-bitwise-inclusive-or-vector-register">ORR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_s8" type="checkbox"><label for="veor_s8"><div>int8x8_t <b><b>veor_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_s8" type="checkbox"><label for="veorq_s8"><div>int8x16_t <b><b>veorq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_s16" type="checkbox"><label for="veor_s16"><div>int16x4_t <b><b>veor_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_s16" type="checkbox"><label for="veorq_s16"><div>int16x8_t <b><b>veorq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_s32" type="checkbox"><label for="veor_s32"><div>int32x2_t <b><b>veor_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_s32" type="checkbox"><label for="veorq_s32"><div>int32x4_t <b><b>veorq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_s64" type="checkbox"><label for="veor_s64"><div>int64x1_t <b><b>veor_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_s64" type="checkbox"><label for="veorq_s64"><div>int64x2_t <b><b>veorq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_u8" type="checkbox"><label for="veor_u8"><div>uint8x8_t <b><b>veor_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_u8" type="checkbox"><label for="veorq_u8"><div>uint8x16_t <b><b>veorq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_u16" type="checkbox"><label for="veor_u16"><div>uint16x4_t <b><b>veor_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_u16" type="checkbox"><label for="veorq_u16"><div>uint16x8_t <b><b>veorq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_u32" type="checkbox"><label for="veor_u32"><div>uint32x2_t <b><b>veor_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_u32" type="checkbox"><label for="veorq_u32"><div>uint32x4_t <b><b>veorq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veor_u64" type="checkbox"><label for="veor_u64"><div>uint64x1_t <b><b>veor_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="veorq_u64" type="checkbox"><label for="veorq_u64"><div>uint64x2_t <b><b>veorq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Bitwise exclusive OR</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&amp;FP registers, and places the result in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/eor-vector-bitwise-exclusive-or-vector">EOR</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand2;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Ones.0" title="function: bits(N) Ones()">Ones</a>();
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_s8" type="checkbox"><label for="vbic_s8"><div>int8x8_t <b><b>vbic_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_s8" type="checkbox"><label for="vbicq_s8"><div>int8x16_t <b><b>vbicq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_s16" type="checkbox"><label for="vbic_s16"><div>int16x4_t <b><b>vbic_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_s16" type="checkbox"><label for="vbicq_s16"><div>int16x8_t <b><b>vbicq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_s32" type="checkbox"><label for="vbic_s32"><div>int32x2_t <b><b>vbic_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_s32" type="checkbox"><label for="vbicq_s32"><div>int32x4_t <b><b>vbicq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_s64" type="checkbox"><label for="vbic_s64"><div>int64x1_t <b><b>vbic_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_s64" type="checkbox"><label for="vbicq_s64"><div>int64x2_t <b><b>vbicq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_u8" type="checkbox"><label for="vbic_u8"><div>uint8x8_t <b><b>vbic_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_u8" type="checkbox"><label for="vbicq_u8"><div>uint8x16_t <b><b>vbicq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_u16" type="checkbox"><label for="vbic_u16"><div>uint16x4_t <b><b>vbic_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_u16" type="checkbox"><label for="vbicq_u16"><div>uint16x8_t <b><b>vbicq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_u32" type="checkbox"><label for="vbic_u32"><div>uint32x2_t <b><b>vbic_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_u32" type="checkbox"><label for="vbicq_u32"><div>uint32x4_t <b><b>vbicq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbic_u64" type="checkbox"><label for="vbic_u64"><div>uint64x1_t <b><b>vbic_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbicq_u64" type="checkbox"><label for="vbicq_u64"><div>uint64x2_t <b><b>vbicq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Bitwise bit clear</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&amp;FP register and the complement of the second source SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bic-vector-register-bitwise-bit-clear-vector-register">BIC</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 AND operand2;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_s8" type="checkbox"><label for="vorn_s8"><div>int8x8_t <b><b>vorn_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_s8" type="checkbox"><label for="vornq_s8"><div>int8x16_t <b><b>vornq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_s16" type="checkbox"><label for="vorn_s16"><div>int16x4_t <b><b>vorn_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_s16" type="checkbox"><label for="vornq_s16"><div>int16x8_t <b><b>vornq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_s32" type="checkbox"><label for="vorn_s32"><div>int32x2_t <b><b>vorn_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_s32" type="checkbox"><label for="vornq_s32"><div>int32x4_t <b><b>vornq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_s64" type="checkbox"><label for="vorn_s64"><div>int64x1_t <b><b>vorn_s64</b></b> (int64x1_t a, int64x1_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_s64" type="checkbox"><label for="vornq_s64"><div>int64x2_t <b><b>vornq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_u8" type="checkbox"><label for="vorn_u8"><div>uint8x8_t <b><b>vorn_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_u8" type="checkbox"><label for="vornq_u8"><div>uint8x16_t <b><b>vornq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_u16" type="checkbox"><label for="vorn_u16"><div>uint16x4_t <b><b>vorn_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_u16" type="checkbox"><label for="vornq_u16"><div>uint16x8_t <b><b>vornq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_u32" type="checkbox"><label for="vorn_u32"><div>uint32x2_t <b><b>vorn_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_u32" type="checkbox"><label for="vornq_u32"><div>uint32x4_t <b><b>vornq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vorn_u64" type="checkbox"><label for="vorn_u64"><div>uint64x1_t <b><b>vorn_u64</b></b> (uint64x1_t a, uint64x1_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vornq_u64" type="checkbox"><label for="vornq_u64"><div>uint64x2_t <b><b>vornq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Bitwise inclusive OR NOT</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&amp;FP registers, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/orn-vector-bitwise-inclusive-or-not-vector">ORN</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ operand2 = NOT(operand2);
+ 
+ result = operand1 OR operand2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_s8" type="checkbox"><label for="vbsl_s8"><div>int8x8_t <b><b>vbsl_s8</b></b> (uint8x8_t a, int8x8_t b, int8x8_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_s8" type="checkbox"><label for="vbslq_s8"><div>int8x16_t <b><b>vbslq_s8</b></b> (uint8x16_t a, int8x16_t b, int8x16_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_s16" type="checkbox"><label for="vbsl_s16"><div>int16x4_t <b><b>vbsl_s16</b></b> (uint16x4_t a, int16x4_t b, int16x4_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_s16" type="checkbox"><label for="vbslq_s16"><div>int16x8_t <b><b>vbslq_s16</b></b> (uint16x8_t a, int16x8_t b, int16x8_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_s32" type="checkbox"><label for="vbsl_s32"><div>int32x2_t <b><b>vbsl_s32</b></b> (uint32x2_t a, int32x2_t b, int32x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_s32" type="checkbox"><label for="vbslq_s32"><div>int32x4_t <b><b>vbslq_s32</b></b> (uint32x4_t a, int32x4_t b, int32x4_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_s64" type="checkbox"><label for="vbsl_s64"><div>int64x1_t <b><b>vbsl_s64</b></b> (uint64x1_t a, int64x1_t b, int64x1_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_s64" type="checkbox"><label for="vbslq_s64"><div>int64x2_t <b><b>vbslq_s64</b></b> (uint64x2_t a, int64x2_t b, int64x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_u8" type="checkbox"><label for="vbsl_u8"><div>uint8x8_t <b><b>vbsl_u8</b></b> (uint8x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_u8" type="checkbox"><label for="vbslq_u8"><div>uint8x16_t <b><b>vbslq_u8</b></b> (uint8x16_t a, uint8x16_t b, uint8x16_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_u16" type="checkbox"><label for="vbsl_u16"><div>uint16x4_t <b><b>vbsl_u16</b></b> (uint16x4_t a, uint16x4_t b, uint16x4_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_u16" type="checkbox"><label for="vbslq_u16"><div>uint16x8_t <b><b>vbslq_u16</b></b> (uint16x8_t a, uint16x8_t b, uint16x8_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_u32" type="checkbox"><label for="vbsl_u32"><div>uint32x2_t <b><b>vbsl_u32</b></b> (uint32x2_t a, uint32x2_t b, uint32x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_u32" type="checkbox"><label for="vbslq_u32"><div>uint32x4_t <b><b>vbslq_u32</b></b> (uint32x4_t a, uint32x4_t b, uint32x4_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_u64" type="checkbox"><label for="vbsl_u64"><div>uint64x1_t <b><b>vbsl_u64</b></b> (uint64x1_t a, uint64x1_t b, uint64x1_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_u64" type="checkbox"><label for="vbslq_u64"><div>uint64x2_t <b><b>vbslq_u64</b></b> (uint64x2_t a, uint64x2_t b, uint64x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_p64" type="checkbox"><label for="vbsl_p64"><div>poly64x1_t <b><b>vbsl_p64</b></b> (poly64x1_t a, poly64x1_t b, poly64x1_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_p64" type="checkbox"><label for="vbslq_p64"><div>poly64x2_t <b><b>vbslq_p64</b></b> (poly64x2_t a, poly64x2_t b, poly64x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_f32" type="checkbox"><label for="vbsl_f32"><div>float32x2_t <b><b>vbsl_f32</b></b> (uint32x2_t a, float32x2_t b, float32x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_f32" type="checkbox"><label for="vbslq_f32"><div>float32x4_t <b><b>vbslq_f32</b></b> (uint32x4_t a, float32x4_t b, float32x4_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_p8" type="checkbox"><label for="vbsl_p8"><div>poly8x8_t <b><b>vbsl_p8</b></b> (uint8x8_t a, poly8x8_t b, poly8x8_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_p8" type="checkbox"><label for="vbslq_p8"><div>poly8x16_t <b><b>vbslq_p8</b></b> (uint8x16_t a, poly8x16_t b, poly8x16_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_p16" type="checkbox"><label for="vbsl_p16"><div>poly16x4_t <b><b>vbsl_p16</b></b> (uint16x4_t a, poly16x4_t b, poly16x4_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_p16" type="checkbox"><label for="vbslq_p16"><div>poly16x8_t <b><b>vbslq_p16</b></b> (uint16x8_t a, poly16x8_t b, poly16x8_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vbsl_f64" type="checkbox"><label for="vbsl_f64"><div>float64x1_t <b><b>vbsl_f64</b></b> (uint64x1_t a, float64x1_t b, float64x1_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ b &rarr; Vn.8B <br />
+ c &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vbslq_f64" type="checkbox"><label for="vbslq_f64"><div>float64x2_t <b><b>vbslq_f64</b></b> (uint64x2_t a, float64x2_t b, float64x2_t c)<span class="right">Bitwise select</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Select. This instruction sets each bit in the destination SIMD&amp;FP register to the corresponding bit from the first source SIMD&amp;FP register when the original destination bit was 1, otherwise from the second source SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bsl-bitwise-select">BSL</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ b &rarr; Vn.16B <br />
+ c &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_s8" type="checkbox"><label for="vcopy_lane_s8"><div>int8x8_t <b><b>vcopy_lane_s8</b></b> (int8x8_t a, const int lane1, int8x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_s8" type="checkbox"><label for="vcopyq_lane_s8"><div>int8x16_t <b><b>vcopyq_lane_s8</b></b> (int8x16_t a, const int lane1, int8x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 15 <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_s16" type="checkbox"><label for="vcopy_lane_s16"><div>int16x4_t <b><b>vcopy_lane_s16</b></b> (int16x4_t a, const int lane1, int16x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_s16" type="checkbox"><label for="vcopyq_lane_s16"><div>int16x8_t <b><b>vcopyq_lane_s16</b></b> (int16x8_t a, const int lane1, int16x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_s32" type="checkbox"><label for="vcopy_lane_s32"><div>int32x2_t <b><b>vcopy_lane_s32</b></b> (int32x2_t a, const int lane1, int32x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_s32" type="checkbox"><label for="vcopyq_lane_s32"><div>int32x4_t <b><b>vcopyq_lane_s32</b></b> (int32x4_t a, const int lane1, int32x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_s64" type="checkbox"><label for="vcopy_lane_s64"><div>int64x1_t <b><b>vcopy_lane_s64</b></b> (int64x1_t a, const int lane1, int64x1_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_s64" type="checkbox"><label for="vcopyq_lane_s64"><div>int64x2_t <b><b>vcopyq_lane_s64</b></b> (int64x2_t a, const int lane1, int64x1_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_u8" type="checkbox"><label for="vcopy_lane_u8"><div>uint8x8_t <b><b>vcopy_lane_u8</b></b> (uint8x8_t a, const int lane1, uint8x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_u8" type="checkbox"><label for="vcopyq_lane_u8"><div>uint8x16_t <b><b>vcopyq_lane_u8</b></b> (uint8x16_t a, const int lane1, uint8x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 15 <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_u16" type="checkbox"><label for="vcopy_lane_u16"><div>uint16x4_t <b><b>vcopy_lane_u16</b></b> (uint16x4_t a, const int lane1, uint16x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_u16" type="checkbox"><label for="vcopyq_lane_u16"><div>uint16x8_t <b><b>vcopyq_lane_u16</b></b> (uint16x8_t a, const int lane1, uint16x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_u32" type="checkbox"><label for="vcopy_lane_u32"><div>uint32x2_t <b><b>vcopy_lane_u32</b></b> (uint32x2_t a, const int lane1, uint32x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_u32" type="checkbox"><label for="vcopyq_lane_u32"><div>uint32x4_t <b><b>vcopyq_lane_u32</b></b> (uint32x4_t a, const int lane1, uint32x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_u64" type="checkbox"><label for="vcopy_lane_u64"><div>uint64x1_t <b><b>vcopy_lane_u64</b></b> (uint64x1_t a, const int lane1, uint64x1_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_u64" type="checkbox"><label for="vcopyq_lane_u64"><div>uint64x2_t <b><b>vcopyq_lane_u64</b></b> (uint64x2_t a, const int lane1, uint64x1_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_p64" type="checkbox"><label for="vcopy_lane_p64"><div>poly64x1_t <b><b>vcopy_lane_p64</b></b> (poly64x1_t a, const int lane1, poly64x1_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_p64" type="checkbox"><label for="vcopyq_lane_p64"><div>poly64x2_t <b><b>vcopyq_lane_p64</b></b> (poly64x2_t a, const int lane1, poly64x1_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_f32" type="checkbox"><label for="vcopy_lane_f32"><div>float32x2_t <b><b>vcopy_lane_f32</b></b> (float32x2_t a, const int lane1, float32x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_f32" type="checkbox"><label for="vcopyq_lane_f32"><div>float32x4_t <b><b>vcopyq_lane_f32</b></b> (float32x4_t a, const int lane1, float32x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_f64" type="checkbox"><label for="vcopy_lane_f64"><div>float64x1_t <b><b>vcopy_lane_f64</b></b> (float64x1_t a, const int lane1, float64x1_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_f64" type="checkbox"><label for="vcopyq_lane_f64"><div>float64x2_t <b><b>vcopyq_lane_f64</b></b> (float64x2_t a, const int lane1, float64x1_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_p8" type="checkbox"><label for="vcopy_lane_p8"><div>poly8x8_t <b><b>vcopy_lane_p8</b></b> (poly8x8_t a, const int lane1, poly8x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_p8" type="checkbox"><label for="vcopyq_lane_p8"><div>poly8x16_t <b><b>vcopyq_lane_p8</b></b> (poly8x16_t a, const int lane1, poly8x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 15 <br />
+ b &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_lane_p16" type="checkbox"><label for="vcopy_lane_p16"><div>poly16x4_t <b><b>vcopy_lane_p16</b></b> (poly16x4_t a, const int lane1, poly16x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_lane_p16" type="checkbox"><label for="vcopyq_lane_p16"><div>poly16x8_t <b><b>vcopyq_lane_p16</b></b> (poly16x8_t a, const int lane1, poly16x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_s8" type="checkbox"><label for="vcopy_laneq_s8"><div>int8x8_t <b><b>vcopy_laneq_s8</b></b> (int8x8_t a, const int lane1, int8x16_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_s8" type="checkbox"><label for="vcopyq_laneq_s8"><div>int8x16_t <b><b>vcopyq_laneq_s8</b></b> (int8x16_t a, const int lane1, int8x16_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 15 <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_s16" type="checkbox"><label for="vcopy_laneq_s16"><div>int16x4_t <b><b>vcopy_laneq_s16</b></b> (int16x4_t a, const int lane1, int16x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_s16" type="checkbox"><label for="vcopyq_laneq_s16"><div>int16x8_t <b><b>vcopyq_laneq_s16</b></b> (int16x8_t a, const int lane1, int16x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_s32" type="checkbox"><label for="vcopy_laneq_s32"><div>int32x2_t <b><b>vcopy_laneq_s32</b></b> (int32x2_t a, const int lane1, int32x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_s32" type="checkbox"><label for="vcopyq_laneq_s32"><div>int32x4_t <b><b>vcopyq_laneq_s32</b></b> (int32x4_t a, const int lane1, int32x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_s64" type="checkbox"><label for="vcopy_laneq_s64"><div>int64x1_t <b><b>vcopy_laneq_s64</b></b> (int64x1_t a, const int lane1, int64x2_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_s64" type="checkbox"><label for="vcopyq_laneq_s64"><div>int64x2_t <b><b>vcopyq_laneq_s64</b></b> (int64x2_t a, const int lane1, int64x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_u8" type="checkbox"><label for="vcopy_laneq_u8"><div>uint8x8_t <b><b>vcopy_laneq_u8</b></b> (uint8x8_t a, const int lane1, uint8x16_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_u8" type="checkbox"><label for="vcopyq_laneq_u8"><div>uint8x16_t <b><b>vcopyq_laneq_u8</b></b> (uint8x16_t a, const int lane1, uint8x16_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 15 <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_u16" type="checkbox"><label for="vcopy_laneq_u16"><div>uint16x4_t <b><b>vcopy_laneq_u16</b></b> (uint16x4_t a, const int lane1, uint16x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_u16" type="checkbox"><label for="vcopyq_laneq_u16"><div>uint16x8_t <b><b>vcopyq_laneq_u16</b></b> (uint16x8_t a, const int lane1, uint16x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_u32" type="checkbox"><label for="vcopy_laneq_u32"><div>uint32x2_t <b><b>vcopy_laneq_u32</b></b> (uint32x2_t a, const int lane1, uint32x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_u32" type="checkbox"><label for="vcopyq_laneq_u32"><div>uint32x4_t <b><b>vcopyq_laneq_u32</b></b> (uint32x4_t a, const int lane1, uint32x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_u64" type="checkbox"><label for="vcopy_laneq_u64"><div>uint64x1_t <b><b>vcopy_laneq_u64</b></b> (uint64x1_t a, const int lane1, uint64x2_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_u64" type="checkbox"><label for="vcopyq_laneq_u64"><div>uint64x2_t <b><b>vcopyq_laneq_u64</b></b> (uint64x2_t a, const int lane1, uint64x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_p64" type="checkbox"><label for="vcopy_laneq_p64"><div>poly64x1_t <b><b>vcopy_laneq_p64</b></b> (poly64x1_t a, const int lane1, poly64x2_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_p64" type="checkbox"><label for="vcopyq_laneq_p64"><div>poly64x2_t <b><b>vcopyq_laneq_p64</b></b> (poly64x2_t a, const int lane1, poly64x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_f32" type="checkbox"><label for="vcopy_laneq_f32"><div>float32x2_t <b><b>vcopy_laneq_f32</b></b> (float32x2_t a, const int lane1, float32x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_f32" type="checkbox"><label for="vcopyq_laneq_f32"><div>float32x4_t <b><b>vcopyq_laneq_f32</b></b> (float32x4_t a, const int lane1, float32x4_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane1],Vn.S[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_f64" type="checkbox"><label for="vcopy_laneq_f64"><div>float64x1_t <b><b>vcopy_laneq_f64</b></b> (float64x1_t a, const int lane1, float64x2_t b, const int lane2)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; UNUSED <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 0 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_f64" type="checkbox"><label for="vcopyq_laneq_f64"><div>float64x2_t <b><b>vcopyq_laneq_f64</b></b> (float64x2_t a, const int lane1, float64x2_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane1],Vn.D[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 1 <br />
+ b &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_p8" type="checkbox"><label for="vcopy_laneq_p8"><div>poly8x8_t <b><b>vcopy_laneq_p8</b></b> (poly8x8_t a, const int lane1, poly8x16_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_p8" type="checkbox"><label for="vcopyq_laneq_p8"><div>poly8x16_t <b><b>vcopyq_laneq_p8</b></b> (poly8x16_t a, const int lane1, poly8x16_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane1],Vn.B[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 15 <br />
+ b &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopy_laneq_p16" type="checkbox"><label for="vcopy_laneq_p16"><div>poly16x4_t <b><b>vcopy_laneq_p16</b></b> (poly16x4_t a, const int lane1, poly16x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 3 <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcopyq_laneq_p16" type="checkbox"><label for="vcopyq_laneq_p16"><div>poly16x8_t <b><b>vcopyq_laneq_p16</b></b> (poly16x8_t a, const int lane1, poly16x8_t b, const int lane2)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane1],Vn.H[lane2]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane1 &lt;&lt; 7 <br />
+ b &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane2 &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrbit_s8" type="checkbox"><label for="vrbit_s8"><div>int8x8_t <b><b>vrbit_s8</b></b> (int8x8_t a)<span class="right">Reverse bit order</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&amp;FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rbit-vector-reverse-bit-order-vector">RBIT</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ bits(esize) rev;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     for i = 0 to esize-1
+         rev&lt;esize-1-i&gt; = element&lt;i&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = rev;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrbitq_s8" type="checkbox"><label for="vrbitq_s8"><div>int8x16_t <b><b>vrbitq_s8</b></b> (int8x16_t a)<span class="right">Reverse bit order</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&amp;FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rbit-vector-reverse-bit-order-vector">RBIT</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ bits(esize) rev;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     for i = 0 to esize-1
+         rev&lt;esize-1-i&gt; = element&lt;i&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = rev;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrbit_u8" type="checkbox"><label for="vrbit_u8"><div>uint8x8_t <b><b>vrbit_u8</b></b> (uint8x8_t a)<span class="right">Reverse bit order</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&amp;FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rbit-vector-reverse-bit-order-vector">RBIT</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ bits(esize) rev;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     for i = 0 to esize-1
+         rev&lt;esize-1-i&gt; = element&lt;i&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = rev;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrbitq_u8" type="checkbox"><label for="vrbitq_u8"><div>uint8x16_t <b><b>vrbitq_u8</b></b> (uint8x16_t a)<span class="right">Reverse bit order</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&amp;FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rbit-vector-reverse-bit-order-vector">RBIT</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ bits(esize) rev;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     for i = 0 to esize-1
+         rev&lt;esize-1-i&gt; = element&lt;i&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = rev;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrbit_p8" type="checkbox"><label for="vrbit_p8"><div>poly8x8_t <b><b>vrbit_p8</b></b> (poly8x8_t a)<span class="right">Reverse bit order</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&amp;FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rbit-vector-reverse-bit-order-vector">RBIT</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ bits(esize) rev;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     for i = 0 to esize-1
+         rev&lt;esize-1-i&gt; = element&lt;i&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = rev;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrbitq_p8" type="checkbox"><label for="vrbitq_p8"><div>poly8x16_t <b><b>vrbitq_p8</b></b> (poly8x16_t a)<span class="right">Reverse bit order</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&amp;FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rbit-vector-reverse-bit-order-vector">RBIT</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ bits(esize) rev;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     for i = 0 to esize-1
+         rev&lt;esize-1-i&gt; = element&lt;i&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = rev;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_s8" type="checkbox"><label for="vcreate_s8"><div>int8x8_t <b><b>vcreate_s8</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_s16" type="checkbox"><label for="vcreate_s16"><div>int16x4_t <b><b>vcreate_s16</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_s32" type="checkbox"><label for="vcreate_s32"><div>int32x2_t <b><b>vcreate_s32</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_s64" type="checkbox"><label for="vcreate_s64"><div>int64x1_t <b><b>vcreate_s64</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_u8" type="checkbox"><label for="vcreate_u8"><div>uint8x8_t <b><b>vcreate_u8</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_u16" type="checkbox"><label for="vcreate_u16"><div>uint16x4_t <b><b>vcreate_u16</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_u32" type="checkbox"><label for="vcreate_u32"><div>uint32x2_t <b><b>vcreate_u32</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_u64" type="checkbox"><label for="vcreate_u64"><div>uint64x1_t <b><b>vcreate_u64</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_p64" type="checkbox"><label for="vcreate_p64"><div>poly64x1_t <b><b>vcreate_p64</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_f16" type="checkbox"><label for="vcreate_f16"><div>float16x4_t <b><b>vcreate_f16</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_f32" type="checkbox"><label for="vcreate_f32"><div>float32x2_t <b><b>vcreate_f32</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_p8" type="checkbox"><label for="vcreate_p8"><div>poly8x8_t <b><b>vcreate_p8</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_p16" type="checkbox"><label for="vcreate_p16"><div>poly16x4_t <b><b>vcreate_p16</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcreate_f64" type="checkbox"><label for="vcreate_f64"><div>float64x1_t <b><b>vcreate_f64</b></b> (uint64_t a)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[0],Xn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_s8" type="checkbox"><label for="vdup_n_s8"><div>int8x8_t <b><b>vdup_n_s8</b></b> (int8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_s8" type="checkbox"><label for="vdupq_n_s8"><div>int8x16_t <b><b>vdupq_n_s8</b></b> (int8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_s16" type="checkbox"><label for="vdup_n_s16"><div>int16x4_t <b><b>vdup_n_s16</b></b> (int16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_s16" type="checkbox"><label for="vdupq_n_s16"><div>int16x8_t <b><b>vdupq_n_s16</b></b> (int16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_s32" type="checkbox"><label for="vdup_n_s32"><div>int32x2_t <b><b>vdup_n_s32</b></b> (int32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_s32" type="checkbox"><label for="vdupq_n_s32"><div>int32x4_t <b><b>vdupq_n_s32</b></b> (int32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_s64" type="checkbox"><label for="vdup_n_s64"><div>int64x1_t <b><b>vdup_n_s64</b></b> (int64_t value)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Dd.D[0],xn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_s64" type="checkbox"><label for="vdupq_n_s64"><div>int64x2_t <b><b>vdupq_n_s64</b></b> (int64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_u8" type="checkbox"><label for="vdup_n_u8"><div>uint8x8_t <b><b>vdup_n_u8</b></b> (uint8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_u8" type="checkbox"><label for="vdupq_n_u8"><div>uint8x16_t <b><b>vdupq_n_u8</b></b> (uint8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_u16" type="checkbox"><label for="vdup_n_u16"><div>uint16x4_t <b><b>vdup_n_u16</b></b> (uint16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_u16" type="checkbox"><label for="vdupq_n_u16"><div>uint16x8_t <b><b>vdupq_n_u16</b></b> (uint16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_u32" type="checkbox"><label for="vdup_n_u32"><div>uint32x2_t <b><b>vdup_n_u32</b></b> (uint32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_u32" type="checkbox"><label for="vdupq_n_u32"><div>uint32x4_t <b><b>vdupq_n_u32</b></b> (uint32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_u64" type="checkbox"><label for="vdup_n_u64"><div>uint64x1_t <b><b>vdup_n_u64</b></b> (uint64_t value)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Dd.D[0],xn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_u64" type="checkbox"><label for="vdupq_n_u64"><div>uint64x2_t <b><b>vdupq_n_u64</b></b> (uint64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_p64" type="checkbox"><label for="vdup_n_p64"><div>poly64x1_t <b><b>vdup_n_p64</b></b> (poly64_t value)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Dd.D[0],xn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_p64" type="checkbox"><label for="vdupq_n_p64"><div>poly64x2_t <b><b>vdupq_n_p64</b></b> (poly64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_f32" type="checkbox"><label for="vdup_n_f32"><div>float32x2_t <b><b>vdup_n_f32</b></b> (float32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_f32" type="checkbox"><label for="vdupq_n_f32"><div>float32x4_t <b><b>vdupq_n_f32</b></b> (float32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_p8" type="checkbox"><label for="vdup_n_p8"><div>poly8x8_t <b><b>vdup_n_p8</b></b> (poly8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_p8" type="checkbox"><label for="vdupq_n_p8"><div>poly8x16_t <b><b>vdupq_n_p8</b></b> (poly8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_p16" type="checkbox"><label for="vdup_n_p16"><div>poly16x4_t <b><b>vdup_n_p16</b></b> (poly16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_p16" type="checkbox"><label for="vdupq_n_p16"><div>poly16x8_t <b><b>vdupq_n_p16</b></b> (poly16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_n_f64" type="checkbox"><label for="vdup_n_f64"><div>float64x1_t <b><b>vdup_n_f64</b></b> (float64_t value)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Dd.D[0],xn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_n_f64" type="checkbox"><label for="vdupq_n_f64"><div>float64x2_t <b><b>vdupq_n_f64</b></b> (float64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_s8" type="checkbox"><label for="vmov_n_s8"><div>int8x8_t <b><b>vmov_n_s8</b></b> (int8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_s8" type="checkbox"><label for="vmovq_n_s8"><div>int8x16_t <b><b>vmovq_n_s8</b></b> (int8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_s16" type="checkbox"><label for="vmov_n_s16"><div>int16x4_t <b><b>vmov_n_s16</b></b> (int16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_s16" type="checkbox"><label for="vmovq_n_s16"><div>int16x8_t <b><b>vmovq_n_s16</b></b> (int16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_s32" type="checkbox"><label for="vmov_n_s32"><div>int32x2_t <b><b>vmov_n_s32</b></b> (int32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_s32" type="checkbox"><label for="vmovq_n_s32"><div>int32x4_t <b><b>vmovq_n_s32</b></b> (int32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_s64" type="checkbox"><label for="vmov_n_s64"><div>int64x1_t <b><b>vmov_n_s64</b></b> (int64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_s64" type="checkbox"><label for="vmovq_n_s64"><div>int64x2_t <b><b>vmovq_n_s64</b></b> (int64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_u8" type="checkbox"><label for="vmov_n_u8"><div>uint8x8_t <b><b>vmov_n_u8</b></b> (uint8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_u8" type="checkbox"><label for="vmovq_n_u8"><div>uint8x16_t <b><b>vmovq_n_u8</b></b> (uint8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_u16" type="checkbox"><label for="vmov_n_u16"><div>uint16x4_t <b><b>vmov_n_u16</b></b> (uint16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_u16" type="checkbox"><label for="vmovq_n_u16"><div>uint16x8_t <b><b>vmovq_n_u16</b></b> (uint16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_u32" type="checkbox"><label for="vmov_n_u32"><div>uint32x2_t <b><b>vmov_n_u32</b></b> (uint32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_u32" type="checkbox"><label for="vmovq_n_u32"><div>uint32x4_t <b><b>vmovq_n_u32</b></b> (uint32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_u64" type="checkbox"><label for="vmov_n_u64"><div>uint64x1_t <b><b>vmov_n_u64</b></b> (uint64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_u64" type="checkbox"><label for="vmovq_n_u64"><div>uint64x2_t <b><b>vmovq_n_u64</b></b> (uint64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_f32" type="checkbox"><label for="vmov_n_f32"><div>float32x2_t <b><b>vmov_n_f32</b></b> (float32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_f32" type="checkbox"><label for="vmovq_n_f32"><div>float32x4_t <b><b>vmovq_n_f32</b></b> (float32_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_p8" type="checkbox"><label for="vmov_n_p8"><div>poly8x8_t <b><b>vmov_n_p8</b></b> (poly8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_p8" type="checkbox"><label for="vmovq_n_p8"><div>poly8x16_t <b><b>vmovq_n_p8</b></b> (poly8_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_p16" type="checkbox"><label for="vmov_n_p16"><div>poly16x4_t <b><b>vmov_n_p16</b></b> (poly16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_p16" type="checkbox"><label for="vmovq_n_p16"><div>poly16x8_t <b><b>vmovq_n_p16</b></b> (poly16_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmov_n_f64" type="checkbox"><label for="vmov_n_f64"><div>float64x1_t <b><b>vmov_n_f64</b></b> (float64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmovq_n_f64" type="checkbox"><label for="vmovq_n_f64"><div>float64x2_t <b><b>vmovq_n_f64</b></b> (float64_t value)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,rn
+ </pre>      <h4>Argument Preparation</h4><pre>value &rarr; rn </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_s8" type="checkbox"><label for="vdup_lane_s8"><div>int8x8_t <b><b>vdup_lane_s8</b></b> (int8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_s8" type="checkbox"><label for="vdupq_lane_s8"><div>int8x16_t <b><b>vdupq_lane_s8</b></b> (int8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_s16" type="checkbox"><label for="vdup_lane_s16"><div>int16x4_t <b><b>vdup_lane_s16</b></b> (int16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_s16" type="checkbox"><label for="vdupq_lane_s16"><div>int16x8_t <b><b>vdupq_lane_s16</b></b> (int16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_s32" type="checkbox"><label for="vdup_lane_s32"><div>int32x2_t <b><b>vdup_lane_s32</b></b> (int32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_s32" type="checkbox"><label for="vdupq_lane_s32"><div>int32x4_t <b><b>vdupq_lane_s32</b></b> (int32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_s64" type="checkbox"><label for="vdup_lane_s64"><div>int64x1_t <b><b>vdup_lane_s64</b></b> (int64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_s64" type="checkbox"><label for="vdupq_lane_s64"><div>int64x2_t <b><b>vdupq_lane_s64</b></b> (int64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_u8" type="checkbox"><label for="vdup_lane_u8"><div>uint8x8_t <b><b>vdup_lane_u8</b></b> (uint8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_u8" type="checkbox"><label for="vdupq_lane_u8"><div>uint8x16_t <b><b>vdupq_lane_u8</b></b> (uint8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_u16" type="checkbox"><label for="vdup_lane_u16"><div>uint16x4_t <b><b>vdup_lane_u16</b></b> (uint16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_u16" type="checkbox"><label for="vdupq_lane_u16"><div>uint16x8_t <b><b>vdupq_lane_u16</b></b> (uint16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_u32" type="checkbox"><label for="vdup_lane_u32"><div>uint32x2_t <b><b>vdup_lane_u32</b></b> (uint32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_u32" type="checkbox"><label for="vdupq_lane_u32"><div>uint32x4_t <b><b>vdupq_lane_u32</b></b> (uint32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_u64" type="checkbox"><label for="vdup_lane_u64"><div>uint64x1_t <b><b>vdup_lane_u64</b></b> (uint64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_u64" type="checkbox"><label for="vdupq_lane_u64"><div>uint64x2_t <b><b>vdupq_lane_u64</b></b> (uint64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_p64" type="checkbox"><label for="vdup_lane_p64"><div>poly64x1_t <b><b>vdup_lane_p64</b></b> (poly64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_p64" type="checkbox"><label for="vdupq_lane_p64"><div>poly64x2_t <b><b>vdupq_lane_p64</b></b> (poly64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_f32" type="checkbox"><label for="vdup_lane_f32"><div>float32x2_t <b><b>vdup_lane_f32</b></b> (float32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_f32" type="checkbox"><label for="vdupq_lane_f32"><div>float32x4_t <b><b>vdupq_lane_f32</b></b> (float32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_p8" type="checkbox"><label for="vdup_lane_p8"><div>poly8x8_t <b><b>vdup_lane_p8</b></b> (poly8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_p8" type="checkbox"><label for="vdupq_lane_p8"><div>poly8x16_t <b><b>vdupq_lane_p8</b></b> (poly8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_p16" type="checkbox"><label for="vdup_lane_p16"><div>poly16x4_t <b><b>vdup_lane_p16</b></b> (poly16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_p16" type="checkbox"><label for="vdupq_lane_p16"><div>poly16x8_t <b><b>vdupq_lane_p16</b></b> (poly16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_lane_f64" type="checkbox"><label for="vdup_lane_f64"><div>float64x1_t <b><b>vdup_lane_f64</b></b> (float64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_lane_f64" type="checkbox"><label for="vdupq_lane_f64"><div>float64x2_t <b><b>vdupq_lane_f64</b></b> (float64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_s8" type="checkbox"><label for="vdup_laneq_s8"><div>int8x8_t <b><b>vdup_laneq_s8</b></b> (int8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_s8" type="checkbox"><label for="vdupq_laneq_s8"><div>int8x16_t <b><b>vdupq_laneq_s8</b></b> (int8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_s16" type="checkbox"><label for="vdup_laneq_s16"><div>int16x4_t <b><b>vdup_laneq_s16</b></b> (int16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_s16" type="checkbox"><label for="vdupq_laneq_s16"><div>int16x8_t <b><b>vdupq_laneq_s16</b></b> (int16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_s32" type="checkbox"><label for="vdup_laneq_s32"><div>int32x2_t <b><b>vdup_laneq_s32</b></b> (int32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_s32" type="checkbox"><label for="vdupq_laneq_s32"><div>int32x4_t <b><b>vdupq_laneq_s32</b></b> (int32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_s64" type="checkbox"><label for="vdup_laneq_s64"><div>int64x1_t <b><b>vdup_laneq_s64</b></b> (int64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_s64" type="checkbox"><label for="vdupq_laneq_s64"><div>int64x2_t <b><b>vdupq_laneq_s64</b></b> (int64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_u8" type="checkbox"><label for="vdup_laneq_u8"><div>uint8x8_t <b><b>vdup_laneq_u8</b></b> (uint8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_u8" type="checkbox"><label for="vdupq_laneq_u8"><div>uint8x16_t <b><b>vdupq_laneq_u8</b></b> (uint8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_u16" type="checkbox"><label for="vdup_laneq_u16"><div>uint16x4_t <b><b>vdup_laneq_u16</b></b> (uint16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_u16" type="checkbox"><label for="vdupq_laneq_u16"><div>uint16x8_t <b><b>vdupq_laneq_u16</b></b> (uint16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_u32" type="checkbox"><label for="vdup_laneq_u32"><div>uint32x2_t <b><b>vdup_laneq_u32</b></b> (uint32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_u32" type="checkbox"><label for="vdupq_laneq_u32"><div>uint32x4_t <b><b>vdupq_laneq_u32</b></b> (uint32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_u64" type="checkbox"><label for="vdup_laneq_u64"><div>uint64x1_t <b><b>vdup_laneq_u64</b></b> (uint64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_u64" type="checkbox"><label for="vdupq_laneq_u64"><div>uint64x2_t <b><b>vdupq_laneq_u64</b></b> (uint64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_p64" type="checkbox"><label for="vdup_laneq_p64"><div>poly64x1_t <b><b>vdup_laneq_p64</b></b> (poly64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_p64" type="checkbox"><label for="vdupq_laneq_p64"><div>poly64x2_t <b><b>vdupq_laneq_p64</b></b> (poly64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_f32" type="checkbox"><label for="vdup_laneq_f32"><div>float32x2_t <b><b>vdup_laneq_f32</b></b> (float32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_f32" type="checkbox"><label for="vdupq_laneq_f32"><div>float32x4_t <b><b>vdupq_laneq_f32</b></b> (float32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4S,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_p8" type="checkbox"><label for="vdup_laneq_p8"><div>poly8x8_t <b><b>vdup_laneq_p8</b></b> (poly8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_p8" type="checkbox"><label for="vdupq_laneq_p8"><div>poly8x16_t <b><b>vdupq_laneq_p8</b></b> (poly8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.16B,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_p16" type="checkbox"><label for="vdup_laneq_p16"><div>poly16x4_t <b><b>vdup_laneq_p16</b></b> (poly16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.4H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_p16" type="checkbox"><label for="vdupq_laneq_p16"><div>poly16x8_t <b><b>vdupq_laneq_p16</b></b> (poly16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.8H,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdup_laneq_f64" type="checkbox"><label for="vdup_laneq_f64"><div>float64x1_t <b><b>vdup_laneq_f64</b></b> (float64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupq_laneq_f64" type="checkbox"><label for="vdupq_laneq_f64"><div>float64x2_t <b><b>vdupq_laneq_f64</b></b> (float64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.2D,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_s8" type="checkbox"><label for="vcombine_s8"><div>int8x16_t <b><b>vcombine_s8</b></b> (int8x8_t low, int8x8_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.8B <br />
+ high &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_s16" type="checkbox"><label for="vcombine_s16"><div>int16x8_t <b><b>vcombine_s16</b></b> (int16x4_t low, int16x4_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.4H <br />
+ high &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_s32" type="checkbox"><label for="vcombine_s32"><div>int32x4_t <b><b>vcombine_s32</b></b> (int32x2_t low, int32x2_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.2S <br />
+ high &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_s64" type="checkbox"><label for="vcombine_s64"><div>int64x2_t <b><b>vcombine_s64</b></b> (int64x1_t low, int64x1_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.1D <br />
+ high &rarr; Vm.1D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_u8" type="checkbox"><label for="vcombine_u8"><div>uint8x16_t <b><b>vcombine_u8</b></b> (uint8x8_t low, uint8x8_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.8B <br />
+ high &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_u16" type="checkbox"><label for="vcombine_u16"><div>uint16x8_t <b><b>vcombine_u16</b></b> (uint16x4_t low, uint16x4_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.4H <br />
+ high &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_u32" type="checkbox"><label for="vcombine_u32"><div>uint32x4_t <b><b>vcombine_u32</b></b> (uint32x2_t low, uint32x2_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.2S <br />
+ high &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_u64" type="checkbox"><label for="vcombine_u64"><div>uint64x2_t <b><b>vcombine_u64</b></b> (uint64x1_t low, uint64x1_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.1D <br />
+ high &rarr; Vm.1D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_p64" type="checkbox"><label for="vcombine_p64"><div>poly64x2_t <b><b>vcombine_p64</b></b> (poly64x1_t low, poly64x1_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.1D <br />
+ high &rarr; Vm.1D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_f16" type="checkbox"><label for="vcombine_f16"><div>float16x8_t <b><b>vcombine_f16</b></b> (float16x4_t low, float16x4_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.4H <br />
+ high &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_f32" type="checkbox"><label for="vcombine_f32"><div>float32x4_t <b><b>vcombine_f32</b></b> (float32x2_t low, float32x2_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.2S <br />
+ high &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_p8" type="checkbox"><label for="vcombine_p8"><div>poly8x16_t <b><b>vcombine_p8</b></b> (poly8x8_t low, poly8x8_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.8B <br />
+ high &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_p16" type="checkbox"><label for="vcombine_p16"><div>poly16x8_t <b><b>vcombine_p16</b></b> (poly16x4_t low, poly16x4_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.4H <br />
+ high &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vcombine_f64" type="checkbox"><label for="vcombine_f64"><div>float64x2_t <b><b>vcombine_f64</b></b> (float64x1_t low, float64x1_t high)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[1],Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>low &rarr; Vn.1D <br />
+ high &rarr; Vm.1D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_s8" type="checkbox"><label for="vget_high_s8"><div>int8x8_t <b><b>vget_high_s8</b></b> (int8x16_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_s16" type="checkbox"><label for="vget_high_s16"><div>int16x4_t <b><b>vget_high_s16</b></b> (int16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_s32" type="checkbox"><label for="vget_high_s32"><div>int32x2_t <b><b>vget_high_s32</b></b> (int32x4_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_s64" type="checkbox"><label for="vget_high_s64"><div>int64x1_t <b><b>vget_high_s64</b></b> (int64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_u8" type="checkbox"><label for="vget_high_u8"><div>uint8x8_t <b><b>vget_high_u8</b></b> (uint8x16_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_u16" type="checkbox"><label for="vget_high_u16"><div>uint16x4_t <b><b>vget_high_u16</b></b> (uint16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_u32" type="checkbox"><label for="vget_high_u32"><div>uint32x2_t <b><b>vget_high_u32</b></b> (uint32x4_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_u64" type="checkbox"><label for="vget_high_u64"><div>uint64x1_t <b><b>vget_high_u64</b></b> (uint64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_p64" type="checkbox"><label for="vget_high_p64"><div>poly64x1_t <b><b>vget_high_p64</b></b> (poly64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_f16" type="checkbox"><label for="vget_high_f16"><div>float16x4_t <b><b>vget_high_f16</b></b> (float16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_f32" type="checkbox"><label for="vget_high_f32"><div>float32x2_t <b><b>vget_high_f32</b></b> (float32x4_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_p8" type="checkbox"><label for="vget_high_p8"><div>poly8x8_t <b><b>vget_high_p8</b></b> (poly8x16_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_p16" type="checkbox"><label for="vget_high_p16"><div>poly16x4_t <b><b>vget_high_p16</b></b> (poly16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_high_f64" type="checkbox"><label for="vget_high_f64"><div>float64x1_t <b><b>vget_high_f64</b></b> (float64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[1]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_s8" type="checkbox"><label for="vget_low_s8"><div>int8x8_t <b><b>vget_low_s8</b></b> (int8x16_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_s16" type="checkbox"><label for="vget_low_s16"><div>int16x4_t <b><b>vget_low_s16</b></b> (int16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_s32" type="checkbox"><label for="vget_low_s32"><div>int32x2_t <b><b>vget_low_s32</b></b> (int32x4_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_s64" type="checkbox"><label for="vget_low_s64"><div>int64x1_t <b><b>vget_low_s64</b></b> (int64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_u8" type="checkbox"><label for="vget_low_u8"><div>uint8x8_t <b><b>vget_low_u8</b></b> (uint8x16_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_u16" type="checkbox"><label for="vget_low_u16"><div>uint16x4_t <b><b>vget_low_u16</b></b> (uint16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_u32" type="checkbox"><label for="vget_low_u32"><div>uint32x2_t <b><b>vget_low_u32</b></b> (uint32x4_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_u64" type="checkbox"><label for="vget_low_u64"><div>uint64x1_t <b><b>vget_low_u64</b></b> (uint64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_p64" type="checkbox"><label for="vget_low_p64"><div>poly64x1_t <b><b>vget_low_p64</b></b> (poly64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_f16" type="checkbox"><label for="vget_low_f16"><div>float16x4_t <b><b>vget_low_f16</b></b> (float16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_f32" type="checkbox"><label for="vget_low_f32"><div>float32x2_t <b><b>vget_low_f32</b></b> (float32x4_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_p8" type="checkbox"><label for="vget_low_p8"><div>poly8x8_t <b><b>vget_low_p8</b></b> (poly8x16_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_p16" type="checkbox"><label for="vget_low_p16"><div>poly16x4_t <b><b>vget_low_p16</b></b> (poly16x8_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_low_f64" type="checkbox"><label for="vget_low_f64"><div>float64x1_t <b><b>vget_low_f64</b></b> (float64x2_t a)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Vd.1D,Vn.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupb_lane_s8" type="checkbox"><label for="vdupb_lane_s8"><div>int8_t <b><b>vdupb_lane_s8</b></b> (int8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Bd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vduph_lane_s16" type="checkbox"><label for="vduph_lane_s16"><div>int16_t <b><b>vduph_lane_s16</b></b> (int16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdups_lane_s32" type="checkbox"><label for="vdups_lane_s32"><div>int32_t <b><b>vdups_lane_s32</b></b> (int32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupd_lane_s64" type="checkbox"><label for="vdupd_lane_s64"><div>int64_t <b><b>vdupd_lane_s64</b></b> (int64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupb_lane_u8" type="checkbox"><label for="vdupb_lane_u8"><div>uint8_t <b><b>vdupb_lane_u8</b></b> (uint8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Bd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vduph_lane_u16" type="checkbox"><label for="vduph_lane_u16"><div>uint16_t <b><b>vduph_lane_u16</b></b> (uint16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdups_lane_u32" type="checkbox"><label for="vdups_lane_u32"><div>uint32_t <b><b>vdups_lane_u32</b></b> (uint32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupd_lane_u64" type="checkbox"><label for="vdupd_lane_u64"><div>uint64_t <b><b>vdupd_lane_u64</b></b> (uint64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdups_lane_f32" type="checkbox"><label for="vdups_lane_f32"><div>float32_t <b><b>vdups_lane_f32</b></b> (float32x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupd_lane_f64" type="checkbox"><label for="vdupd_lane_f64"><div>float64_t <b><b>vdupd_lane_f64</b></b> (float64x1_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupb_lane_p8" type="checkbox"><label for="vdupb_lane_p8"><div>poly8_t <b><b>vdupb_lane_p8</b></b> (poly8x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Bd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vduph_lane_p16" type="checkbox"><label for="vduph_lane_p16"><div>poly16_t <b><b>vduph_lane_p16</b></b> (poly16x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupb_laneq_s8" type="checkbox"><label for="vdupb_laneq_s8"><div>int8_t <b><b>vdupb_laneq_s8</b></b> (int8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Bd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vduph_laneq_s16" type="checkbox"><label for="vduph_laneq_s16"><div>int16_t <b><b>vduph_laneq_s16</b></b> (int16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdups_laneq_s32" type="checkbox"><label for="vdups_laneq_s32"><div>int32_t <b><b>vdups_laneq_s32</b></b> (int32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupd_laneq_s64" type="checkbox"><label for="vdupd_laneq_s64"><div>int64_t <b><b>vdupd_laneq_s64</b></b> (int64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupb_laneq_u8" type="checkbox"><label for="vdupb_laneq_u8"><div>uint8_t <b><b>vdupb_laneq_u8</b></b> (uint8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Bd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vduph_laneq_u16" type="checkbox"><label for="vduph_laneq_u16"><div>uint16_t <b><b>vduph_laneq_u16</b></b> (uint16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdups_laneq_u32" type="checkbox"><label for="vdups_laneq_u32"><div>uint32_t <b><b>vdups_laneq_u32</b></b> (uint32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupd_laneq_u64" type="checkbox"><label for="vdupd_laneq_u64"><div>uint64_t <b><b>vdupd_laneq_u64</b></b> (uint64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdups_laneq_f32" type="checkbox"><label for="vdups_laneq_f32"><div>float32_t <b><b>vdups_laneq_f32</b></b> (float32x4_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupd_laneq_f64" type="checkbox"><label for="vdupd_laneq_f64"><div>float64_t <b><b>vdupd_laneq_f64</b></b> (float64x2_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vdupb_laneq_p8" type="checkbox"><label for="vdupb_laneq_p8"><div>poly8_t <b><b>vdupb_laneq_p8</b></b> (poly8x16_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Bd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vduph_laneq_p16" type="checkbox"><label for="vduph_laneq_p16"><div>poly16_t <b><b>vduph_laneq_p16</b></b> (poly16x8_t vec, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s8" type="checkbox"><label for="vld1_s8"><div>int8x8_t <b><b>vld1_s8</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s8" type="checkbox"><label for="vld1q_s8"><div>int8x16_t <b><b>vld1q_s8</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s16" type="checkbox"><label for="vld1_s16"><div>int16x4_t <b><b>vld1_s16</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s16" type="checkbox"><label for="vld1q_s16"><div>int16x8_t <b><b>vld1q_s16</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s32" type="checkbox"><label for="vld1_s32"><div>int32x2_t <b><b>vld1_s32</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s32" type="checkbox"><label for="vld1q_s32"><div>int32x4_t <b><b>vld1q_s32</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s64" type="checkbox"><label for="vld1_s64"><div>int64x1_t <b><b>vld1_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s64" type="checkbox"><label for="vld1q_s64"><div>int64x2_t <b><b>vld1q_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u8" type="checkbox"><label for="vld1_u8"><div>uint8x8_t <b><b>vld1_u8</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u8" type="checkbox"><label for="vld1q_u8"><div>uint8x16_t <b><b>vld1q_u8</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u16" type="checkbox"><label for="vld1_u16"><div>uint16x4_t <b><b>vld1_u16</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u16" type="checkbox"><label for="vld1q_u16"><div>uint16x8_t <b><b>vld1q_u16</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u32" type="checkbox"><label for="vld1_u32"><div>uint32x2_t <b><b>vld1_u32</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u32" type="checkbox"><label for="vld1q_u32"><div>uint32x4_t <b><b>vld1q_u32</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u64" type="checkbox"><label for="vld1_u64"><div>uint64x1_t <b><b>vld1_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u64" type="checkbox"><label for="vld1q_u64"><div>uint64x2_t <b><b>vld1q_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p64" type="checkbox"><label for="vld1_p64"><div>poly64x1_t <b><b>vld1_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p64" type="checkbox"><label for="vld1q_p64"><div>poly64x2_t <b><b>vld1q_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f16" type="checkbox"><label for="vld1_f16"><div>float16x4_t <b><b>vld1_f16</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f16" type="checkbox"><label for="vld1q_f16"><div>float16x8_t <b><b>vld1q_f16</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f32" type="checkbox"><label for="vld1_f32"><div>float32x2_t <b><b>vld1_f32</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f32" type="checkbox"><label for="vld1q_f32"><div>float32x4_t <b><b>vld1q_f32</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p8" type="checkbox"><label for="vld1_p8"><div>poly8x8_t <b><b>vld1_p8</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p8" type="checkbox"><label for="vld1q_p8"><div>poly8x16_t <b><b>vld1q_p8</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p16" type="checkbox"><label for="vld1_p16"><div>poly16x4_t <b><b>vld1_p16</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p16" type="checkbox"><label for="vld1q_p16"><div>poly16x8_t <b><b>vld1q_p16</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f64" type="checkbox"><label for="vld1_f64"><div>float64x1_t <b><b>vld1_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f64" type="checkbox"><label for="vld1q_f64"><div>float64x2_t <b><b>vld1q_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_s8" type="checkbox"><label for="vld1_lane_s8"><div>int8x8_t <b><b>vld1_lane_s8</b></b> (int8_t const * ptr, int8x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_s8" type="checkbox"><label for="vld1q_lane_s8"><div>int8x16_t <b><b>vld1q_lane_s8</b></b> (int8_t const * ptr, int8x16_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_s16" type="checkbox"><label for="vld1_lane_s16"><div>int16x4_t <b><b>vld1_lane_s16</b></b> (int16_t const * ptr, int16x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_s16" type="checkbox"><label for="vld1q_lane_s16"><div>int16x8_t <b><b>vld1q_lane_s16</b></b> (int16_t const * ptr, int16x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_s32" type="checkbox"><label for="vld1_lane_s32"><div>int32x2_t <b><b>vld1_lane_s32</b></b> (int32_t const * ptr, int32x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.S}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_s32" type="checkbox"><label for="vld1q_lane_s32"><div>int32x4_t <b><b>vld1q_lane_s32</b></b> (int32_t const * ptr, int32x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.S}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_s64" type="checkbox"><label for="vld1_lane_s64"><div>int64x1_t <b><b>vld1_lane_s64</b></b> (int64_t const * ptr, int64x1_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_s64" type="checkbox"><label for="vld1q_lane_s64"><div>int64x2_t <b><b>vld1q_lane_s64</b></b> (int64_t const * ptr, int64x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_u8" type="checkbox"><label for="vld1_lane_u8"><div>uint8x8_t <b><b>vld1_lane_u8</b></b> (uint8_t const * ptr, uint8x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.B}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_u8" type="checkbox"><label for="vld1q_lane_u8"><div>uint8x16_t <b><b>vld1q_lane_u8</b></b> (uint8_t const * ptr, uint8x16_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.B}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_u16" type="checkbox"><label for="vld1_lane_u16"><div>uint16x4_t <b><b>vld1_lane_u16</b></b> (uint16_t const * ptr, uint16x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_u16" type="checkbox"><label for="vld1q_lane_u16"><div>uint16x8_t <b><b>vld1q_lane_u16</b></b> (uint16_t const * ptr, uint16x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_u32" type="checkbox"><label for="vld1_lane_u32"><div>uint32x2_t <b><b>vld1_lane_u32</b></b> (uint32_t const * ptr, uint32x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.S}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_u32" type="checkbox"><label for="vld1q_lane_u32"><div>uint32x4_t <b><b>vld1q_lane_u32</b></b> (uint32_t const * ptr, uint32x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.S}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_u64" type="checkbox"><label for="vld1_lane_u64"><div>uint64x1_t <b><b>vld1_lane_u64</b></b> (uint64_t const * ptr, uint64x1_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_u64" type="checkbox"><label for="vld1q_lane_u64"><div>uint64x2_t <b><b>vld1q_lane_u64</b></b> (uint64_t const * ptr, uint64x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_p64" type="checkbox"><label for="vld1_lane_p64"><div>poly64x1_t <b><b>vld1_lane_p64</b></b> (poly64_t const * ptr, poly64x1_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_p64" type="checkbox"><label for="vld1q_lane_p64"><div>poly64x2_t <b><b>vld1q_lane_p64</b></b> (poly64_t const * ptr, poly64x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_f16" type="checkbox"><label for="vld1_lane_f16"><div>float16x4_t <b><b>vld1_lane_f16</b></b> (float16_t const * ptr, float16x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_f16" type="checkbox"><label for="vld1q_lane_f16"><div>float16x8_t <b><b>vld1q_lane_f16</b></b> (float16_t const * ptr, float16x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_f32" type="checkbox"><label for="vld1_lane_f32"><div>float32x2_t <b><b>vld1_lane_f32</b></b> (float32_t const * ptr, float32x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.S}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_f32" type="checkbox"><label for="vld1q_lane_f32"><div>float32x4_t <b><b>vld1q_lane_f32</b></b> (float32_t const * ptr, float32x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.S}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_p8" type="checkbox"><label for="vld1_lane_p8"><div>poly8x8_t <b><b>vld1_lane_p8</b></b> (poly8_t const * ptr, poly8x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.B}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_p8" type="checkbox"><label for="vld1q_lane_p8"><div>poly8x16_t <b><b>vld1q_lane_p8</b></b> (poly8_t const * ptr, poly8x16_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.B}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_p16" type="checkbox"><label for="vld1_lane_p16"><div>poly16x4_t <b><b>vld1_lane_p16</b></b> (poly16_t const * ptr, poly16x4_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_p16" type="checkbox"><label for="vld1q_lane_p16"><div>poly16x8_t <b><b>vld1q_lane_p16</b></b> (poly16_t const * ptr, poly16x8_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.H}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_lane_f64" type="checkbox"><label for="vld1_lane_f64"><div>float64x1_t <b><b>vld1_lane_f64</b></b> (float64_t const * ptr, float64x1_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_lane_f64" type="checkbox"><label for="vld1q_lane_f64"><div>float64x2_t <b><b>vld1q_lane_f64</b></b> (float64_t const * ptr, float64x2_t src, const int lane)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.D}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_s8" type="checkbox"><label for="vld1_dup_s8"><div>int8x8_t <b><b>vld1_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_s8" type="checkbox"><label for="vld1q_dup_s8"><div>int8x16_t <b><b>vld1q_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_s16" type="checkbox"><label for="vld1_dup_s16"><div>int16x4_t <b><b>vld1_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_s16" type="checkbox"><label for="vld1q_dup_s16"><div>int16x8_t <b><b>vld1q_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_s32" type="checkbox"><label for="vld1_dup_s32"><div>int32x2_t <b><b>vld1_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_s32" type="checkbox"><label for="vld1q_dup_s32"><div>int32x4_t <b><b>vld1q_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_s64" type="checkbox"><label for="vld1_dup_s64"><div>int64x1_t <b><b>vld1_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_s64" type="checkbox"><label for="vld1q_dup_s64"><div>int64x2_t <b><b>vld1q_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_u8" type="checkbox"><label for="vld1_dup_u8"><div>uint8x8_t <b><b>vld1_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_u8" type="checkbox"><label for="vld1q_dup_u8"><div>uint8x16_t <b><b>vld1q_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_u16" type="checkbox"><label for="vld1_dup_u16"><div>uint16x4_t <b><b>vld1_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_u16" type="checkbox"><label for="vld1q_dup_u16"><div>uint16x8_t <b><b>vld1q_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_u32" type="checkbox"><label for="vld1_dup_u32"><div>uint32x2_t <b><b>vld1_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_u32" type="checkbox"><label for="vld1q_dup_u32"><div>uint32x4_t <b><b>vld1q_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_u64" type="checkbox"><label for="vld1_dup_u64"><div>uint64x1_t <b><b>vld1_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_u64" type="checkbox"><label for="vld1q_dup_u64"><div>uint64x2_t <b><b>vld1q_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_p64" type="checkbox"><label for="vld1_dup_p64"><div>poly64x1_t <b><b>vld1_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_p64" type="checkbox"><label for="vld1q_dup_p64"><div>poly64x2_t <b><b>vld1q_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_f16" type="checkbox"><label for="vld1_dup_f16"><div>float16x4_t <b><b>vld1_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_f16" type="checkbox"><label for="vld1q_dup_f16"><div>float16x8_t <b><b>vld1q_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_f32" type="checkbox"><label for="vld1_dup_f32"><div>float32x2_t <b><b>vld1_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_f32" type="checkbox"><label for="vld1q_dup_f32"><div>float32x4_t <b><b>vld1q_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_p8" type="checkbox"><label for="vld1_dup_p8"><div>poly8x8_t <b><b>vld1_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_p8" type="checkbox"><label for="vld1q_dup_p8"><div>poly8x16_t <b><b>vld1q_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_p16" type="checkbox"><label for="vld1_dup_p16"><div>poly16x4_t <b><b>vld1_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_p16" type="checkbox"><label for="vld1q_dup_p16"><div>poly16x8_t <b><b>vld1q_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_dup_f64" type="checkbox"><label for="vld1_dup_f64"><div>float64x1_t <b><b>vld1_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_dup_f64" type="checkbox"><label for="vld1q_dup_f64"><div>float64x2_t <b><b>vld1q_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure and replicate to all lanes (of one register)</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1r-load-one-single-element-structure-and-replicate-to-all-lanes-of-one-register">LD1R</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s8" type="checkbox"><label for="vst1_s8"><div>void <b><b>vst1_s8</b></b> (int8_t * ptr, int8x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s8" type="checkbox"><label for="vst1q_s8"><div>void <b><b>vst1q_s8</b></b> (int8_t * ptr, int8x16_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s16" type="checkbox"><label for="vst1_s16"><div>void <b><b>vst1_s16</b></b> (int16_t * ptr, int16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s16" type="checkbox"><label for="vst1q_s16"><div>void <b><b>vst1q_s16</b></b> (int16_t * ptr, int16x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s32" type="checkbox"><label for="vst1_s32"><div>void <b><b>vst1_s32</b></b> (int32_t * ptr, int32x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s32" type="checkbox"><label for="vst1q_s32"><div>void <b><b>vst1q_s32</b></b> (int32_t * ptr, int32x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s64" type="checkbox"><label for="vst1_s64"><div>void <b><b>vst1_s64</b></b> (int64_t * ptr, int64x1_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s64" type="checkbox"><label for="vst1q_s64"><div>void <b><b>vst1q_s64</b></b> (int64_t * ptr, int64x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u8" type="checkbox"><label for="vst1_u8"><div>void <b><b>vst1_u8</b></b> (uint8_t * ptr, uint8x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u8" type="checkbox"><label for="vst1q_u8"><div>void <b><b>vst1q_u8</b></b> (uint8_t * ptr, uint8x16_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u16" type="checkbox"><label for="vst1_u16"><div>void <b><b>vst1_u16</b></b> (uint16_t * ptr, uint16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u16" type="checkbox"><label for="vst1q_u16"><div>void <b><b>vst1q_u16</b></b> (uint16_t * ptr, uint16x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u32" type="checkbox"><label for="vst1_u32"><div>void <b><b>vst1_u32</b></b> (uint32_t * ptr, uint32x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u32" type="checkbox"><label for="vst1q_u32"><div>void <b><b>vst1q_u32</b></b> (uint32_t * ptr, uint32x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u64" type="checkbox"><label for="vst1_u64"><div>void <b><b>vst1_u64</b></b> (uint64_t * ptr, uint64x1_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u64" type="checkbox"><label for="vst1q_u64"><div>void <b><b>vst1q_u64</b></b> (uint64_t * ptr, uint64x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p64" type="checkbox"><label for="vst1_p64"><div>void <b><b>vst1_p64</b></b> (poly64_t * ptr, poly64x1_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p64" type="checkbox"><label for="vst1q_p64"><div>void <b><b>vst1q_p64</b></b> (poly64_t * ptr, poly64x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f16" type="checkbox"><label for="vst1_f16"><div>void <b><b>vst1_f16</b></b> (float16_t * ptr, float16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f16" type="checkbox"><label for="vst1q_f16"><div>void <b><b>vst1q_f16</b></b> (float16_t * ptr, float16x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f32" type="checkbox"><label for="vst1_f32"><div>void <b><b>vst1_f32</b></b> (float32_t * ptr, float32x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f32" type="checkbox"><label for="vst1q_f32"><div>void <b><b>vst1q_f32</b></b> (float32_t * ptr, float32x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p8" type="checkbox"><label for="vst1_p8"><div>void <b><b>vst1_p8</b></b> (poly8_t * ptr, poly8x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p8" type="checkbox"><label for="vst1q_p8"><div>void <b><b>vst1q_p8</b></b> (poly8_t * ptr, poly8x16_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p16" type="checkbox"><label for="vst1_p16"><div>void <b><b>vst1_p16</b></b> (poly16_t * ptr, poly16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p16" type="checkbox"><label for="vst1q_p16"><div>void <b><b>vst1q_p16</b></b> (poly16_t * ptr, poly16x8_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f64" type="checkbox"><label for="vst1_f64"><div>void <b><b>vst1_f64</b></b> (float64_t * ptr, float64x1_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f64" type="checkbox"><label for="vst1q_f64"><div>void <b><b>vst1q_f64</b></b> (float64_t * ptr, float64x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_s8" type="checkbox"><label for="vst1_lane_s8"><div>void <b><b>vst1_lane_s8</b></b> (int8_t * ptr, int8x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_s8" type="checkbox"><label for="vst1q_lane_s8"><div>void <b><b>vst1q_lane_s8</b></b> (int8_t * ptr, int8x16_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_s16" type="checkbox"><label for="vst1_lane_s16"><div>void <b><b>vst1_lane_s16</b></b> (int16_t * ptr, int16x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_s16" type="checkbox"><label for="vst1q_lane_s16"><div>void <b><b>vst1q_lane_s16</b></b> (int16_t * ptr, int16x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_s32" type="checkbox"><label for="vst1_lane_s32"><div>void <b><b>vst1_lane_s32</b></b> (int32_t * ptr, int32x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_s32" type="checkbox"><label for="vst1q_lane_s32"><div>void <b><b>vst1q_lane_s32</b></b> (int32_t * ptr, int32x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_s64" type="checkbox"><label for="vst1_lane_s64"><div>void <b><b>vst1_lane_s64</b></b> (int64_t * ptr, int64x1_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_s64" type="checkbox"><label for="vst1q_lane_s64"><div>void <b><b>vst1q_lane_s64</b></b> (int64_t * ptr, int64x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_u8" type="checkbox"><label for="vst1_lane_u8"><div>void <b><b>vst1_lane_u8</b></b> (uint8_t * ptr, uint8x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_u8" type="checkbox"><label for="vst1q_lane_u8"><div>void <b><b>vst1q_lane_u8</b></b> (uint8_t * ptr, uint8x16_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_u16" type="checkbox"><label for="vst1_lane_u16"><div>void <b><b>vst1_lane_u16</b></b> (uint16_t * ptr, uint16x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_u16" type="checkbox"><label for="vst1q_lane_u16"><div>void <b><b>vst1q_lane_u16</b></b> (uint16_t * ptr, uint16x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_u32" type="checkbox"><label for="vst1_lane_u32"><div>void <b><b>vst1_lane_u32</b></b> (uint32_t * ptr, uint32x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_u32" type="checkbox"><label for="vst1q_lane_u32"><div>void <b><b>vst1q_lane_u32</b></b> (uint32_t * ptr, uint32x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_u64" type="checkbox"><label for="vst1_lane_u64"><div>void <b><b>vst1_lane_u64</b></b> (uint64_t * ptr, uint64x1_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_u64" type="checkbox"><label for="vst1q_lane_u64"><div>void <b><b>vst1q_lane_u64</b></b> (uint64_t * ptr, uint64x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_p64" type="checkbox"><label for="vst1_lane_p64"><div>void <b><b>vst1_lane_p64</b></b> (poly64_t * ptr, poly64x1_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_p64" type="checkbox"><label for="vst1q_lane_p64"><div>void <b><b>vst1q_lane_p64</b></b> (poly64_t * ptr, poly64x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_f16" type="checkbox"><label for="vst1_lane_f16"><div>void <b><b>vst1_lane_f16</b></b> (float16_t * ptr, float16x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_f16" type="checkbox"><label for="vst1q_lane_f16"><div>void <b><b>vst1q_lane_f16</b></b> (float16_t * ptr, float16x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_f32" type="checkbox"><label for="vst1_lane_f32"><div>void <b><b>vst1_lane_f32</b></b> (float32_t * ptr, float32x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_f32" type="checkbox"><label for="vst1q_lane_f32"><div>void <b><b>vst1q_lane_f32</b></b> (float32_t * ptr, float32x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_p8" type="checkbox"><label for="vst1_lane_p8"><div>void <b><b>vst1_lane_p8</b></b> (poly8_t * ptr, poly8x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_p8" type="checkbox"><label for="vst1q_lane_p8"><div>void <b><b>vst1q_lane_p8</b></b> (poly8_t * ptr, poly8x16_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_p16" type="checkbox"><label for="vst1_lane_p16"><div>void <b><b>vst1_lane_p16</b></b> (poly16_t * ptr, poly16x4_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_p16" type="checkbox"><label for="vst1q_lane_p16"><div>void <b><b>vst1q_lane_p16</b></b> (poly16_t * ptr, poly16x8_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_lane_f64" type="checkbox"><label for="vst1_lane_f64"><div>void <b><b>vst1_lane_f64</b></b> (float64_t * ptr, float64x1_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_lane_f64" type="checkbox"><label for="vst1q_lane_f64"><div>void <b><b>vst1q_lane_f64</b></b> (float64_t * ptr, float64x2_t val, const int lane)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_s8" type="checkbox"><label for="vld2_s8"><div>int8x8x2_t <b><b>vld2_s8</b></b> (int8_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_s8" type="checkbox"><label for="vld2q_s8"><div>int8x16x2_t <b><b>vld2q_s8</b></b> (int8_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_s16" type="checkbox"><label for="vld2_s16"><div>int16x4x2_t <b><b>vld2_s16</b></b> (int16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_s16" type="checkbox"><label for="vld2q_s16"><div>int16x8x2_t <b><b>vld2q_s16</b></b> (int16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_s32" type="checkbox"><label for="vld2_s32"><div>int32x2x2_t <b><b>vld2_s32</b></b> (int32_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_s32" type="checkbox"><label for="vld2q_s32"><div>int32x4x2_t <b><b>vld2q_s32</b></b> (int32_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_u8" type="checkbox"><label for="vld2_u8"><div>uint8x8x2_t <b><b>vld2_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_u8" type="checkbox"><label for="vld2q_u8"><div>uint8x16x2_t <b><b>vld2q_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_u16" type="checkbox"><label for="vld2_u16"><div>uint16x4x2_t <b><b>vld2_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_u16" type="checkbox"><label for="vld2q_u16"><div>uint16x8x2_t <b><b>vld2q_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_u32" type="checkbox"><label for="vld2_u32"><div>uint32x2x2_t <b><b>vld2_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_u32" type="checkbox"><label for="vld2q_u32"><div>uint32x4x2_t <b><b>vld2q_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_f16" type="checkbox"><label for="vld2_f16"><div>float16x4x2_t <b><b>vld2_f16</b></b> (float16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_f16" type="checkbox"><label for="vld2q_f16"><div>float16x8x2_t <b><b>vld2q_f16</b></b> (float16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_f32" type="checkbox"><label for="vld2_f32"><div>float32x2x2_t <b><b>vld2_f32</b></b> (float32_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_f32" type="checkbox"><label for="vld2q_f32"><div>float32x4x2_t <b><b>vld2q_f32</b></b> (float32_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_p8" type="checkbox"><label for="vld2_p8"><div>poly8x8x2_t <b><b>vld2_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_p8" type="checkbox"><label for="vld2q_p8"><div>poly8x16x2_t <b><b>vld2q_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_p16" type="checkbox"><label for="vld2_p16"><div>poly16x4x2_t <b><b>vld2_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_p16" type="checkbox"><label for="vld2q_p16"><div>poly16x8x2_t <b><b>vld2q_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_s64" type="checkbox"><label for="vld2_s64"><div>int64x1x2_t <b><b>vld2_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_u64" type="checkbox"><label for="vld2_u64"><div>uint64x1x2_t <b><b>vld2_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_p64" type="checkbox"><label for="vld2_p64"><div>poly64x1x2_t <b><b>vld2_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_s64" type="checkbox"><label for="vld2q_s64"><div>int64x2x2_t <b><b>vld2q_s64</b></b> (int64_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_u64" type="checkbox"><label for="vld2q_u64"><div>uint64x2x2_t <b><b>vld2q_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_p64" type="checkbox"><label for="vld2q_p64"><div>poly64x2x2_t <b><b>vld2q_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_f64" type="checkbox"><label for="vld2_f64"><div>float64x1x2_t <b><b>vld2_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_f64" type="checkbox"><label for="vld2q_f64"><div>float64x2x2_t <b><b>vld2q_f64</b></b> (float64_t const * ptr)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_s8" type="checkbox"><label for="vld3_s8"><div>int8x8x3_t <b><b>vld3_s8</b></b> (int8_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_s8" type="checkbox"><label for="vld3q_s8"><div>int8x16x3_t <b><b>vld3q_s8</b></b> (int8_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_s16" type="checkbox"><label for="vld3_s16"><div>int16x4x3_t <b><b>vld3_s16</b></b> (int16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_s16" type="checkbox"><label for="vld3q_s16"><div>int16x8x3_t <b><b>vld3q_s16</b></b> (int16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_s32" type="checkbox"><label for="vld3_s32"><div>int32x2x3_t <b><b>vld3_s32</b></b> (int32_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_s32" type="checkbox"><label for="vld3q_s32"><div>int32x4x3_t <b><b>vld3q_s32</b></b> (int32_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_u8" type="checkbox"><label for="vld3_u8"><div>uint8x8x3_t <b><b>vld3_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_u8" type="checkbox"><label for="vld3q_u8"><div>uint8x16x3_t <b><b>vld3q_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_u16" type="checkbox"><label for="vld3_u16"><div>uint16x4x3_t <b><b>vld3_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_u16" type="checkbox"><label for="vld3q_u16"><div>uint16x8x3_t <b><b>vld3q_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_u32" type="checkbox"><label for="vld3_u32"><div>uint32x2x3_t <b><b>vld3_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_u32" type="checkbox"><label for="vld3q_u32"><div>uint32x4x3_t <b><b>vld3q_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_f16" type="checkbox"><label for="vld3_f16"><div>float16x4x3_t <b><b>vld3_f16</b></b> (float16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_f16" type="checkbox"><label for="vld3q_f16"><div>float16x8x3_t <b><b>vld3q_f16</b></b> (float16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_f32" type="checkbox"><label for="vld3_f32"><div>float32x2x3_t <b><b>vld3_f32</b></b> (float32_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_f32" type="checkbox"><label for="vld3q_f32"><div>float32x4x3_t <b><b>vld3q_f32</b></b> (float32_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_p8" type="checkbox"><label for="vld3_p8"><div>poly8x8x3_t <b><b>vld3_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_p8" type="checkbox"><label for="vld3q_p8"><div>poly8x16x3_t <b><b>vld3q_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_p16" type="checkbox"><label for="vld3_p16"><div>poly16x4x3_t <b><b>vld3_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_p16" type="checkbox"><label for="vld3q_p16"><div>poly16x8x3_t <b><b>vld3q_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_s64" type="checkbox"><label for="vld3_s64"><div>int64x1x3_t <b><b>vld3_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_u64" type="checkbox"><label for="vld3_u64"><div>uint64x1x3_t <b><b>vld3_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_p64" type="checkbox"><label for="vld3_p64"><div>poly64x1x3_t <b><b>vld3_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_s64" type="checkbox"><label for="vld3q_s64"><div>int64x2x3_t <b><b>vld3q_s64</b></b> (int64_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_u64" type="checkbox"><label for="vld3q_u64"><div>uint64x2x3_t <b><b>vld3q_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_p64" type="checkbox"><label for="vld3q_p64"><div>poly64x2x3_t <b><b>vld3q_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_f64" type="checkbox"><label for="vld3_f64"><div>float64x1x3_t <b><b>vld3_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_f64" type="checkbox"><label for="vld3q_f64"><div>float64x2x3_t <b><b>vld3q_f64</b></b> (float64_t const * ptr)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_s8" type="checkbox"><label for="vld4_s8"><div>int8x8x4_t <b><b>vld4_s8</b></b> (int8_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_s8" type="checkbox"><label for="vld4q_s8"><div>int8x16x4_t <b><b>vld4q_s8</b></b> (int8_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_s16" type="checkbox"><label for="vld4_s16"><div>int16x4x4_t <b><b>vld4_s16</b></b> (int16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_s16" type="checkbox"><label for="vld4q_s16"><div>int16x8x4_t <b><b>vld4q_s16</b></b> (int16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_s32" type="checkbox"><label for="vld4_s32"><div>int32x2x4_t <b><b>vld4_s32</b></b> (int32_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_s32" type="checkbox"><label for="vld4q_s32"><div>int32x4x4_t <b><b>vld4q_s32</b></b> (int32_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_u8" type="checkbox"><label for="vld4_u8"><div>uint8x8x4_t <b><b>vld4_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_u8" type="checkbox"><label for="vld4q_u8"><div>uint8x16x4_t <b><b>vld4q_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_u16" type="checkbox"><label for="vld4_u16"><div>uint16x4x4_t <b><b>vld4_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_u16" type="checkbox"><label for="vld4q_u16"><div>uint16x8x4_t <b><b>vld4q_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_u32" type="checkbox"><label for="vld4_u32"><div>uint32x2x4_t <b><b>vld4_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_u32" type="checkbox"><label for="vld4q_u32"><div>uint32x4x4_t <b><b>vld4q_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_f16" type="checkbox"><label for="vld4_f16"><div>float16x4x4_t <b><b>vld4_f16</b></b> (float16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_f16" type="checkbox"><label for="vld4q_f16"><div>float16x8x4_t <b><b>vld4q_f16</b></b> (float16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_f32" type="checkbox"><label for="vld4_f32"><div>float32x2x4_t <b><b>vld4_f32</b></b> (float32_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_f32" type="checkbox"><label for="vld4q_f32"><div>float32x4x4_t <b><b>vld4q_f32</b></b> (float32_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_p8" type="checkbox"><label for="vld4_p8"><div>poly8x8x4_t <b><b>vld4_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_p8" type="checkbox"><label for="vld4q_p8"><div>poly8x16x4_t <b><b>vld4q_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_p16" type="checkbox"><label for="vld4_p16"><div>poly16x4x4_t <b><b>vld4_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_p16" type="checkbox"><label for="vld4q_p16"><div>poly16x8x4_t <b><b>vld4q_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_s64" type="checkbox"><label for="vld4_s64"><div>int64x1x4_t <b><b>vld4_s64</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_u64" type="checkbox"><label for="vld4_u64"><div>uint64x1x4_t <b><b>vld4_u64</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_p64" type="checkbox"><label for="vld4_p64"><div>poly64x1x4_t <b><b>vld4_p64</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_s64" type="checkbox"><label for="vld4q_s64"><div>int64x2x4_t <b><b>vld4q_s64</b></b> (int64_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_u64" type="checkbox"><label for="vld4q_u64"><div>uint64x2x4_t <b><b>vld4q_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_p64" type="checkbox"><label for="vld4q_p64"><div>poly64x2x4_t <b><b>vld4q_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_f64" type="checkbox"><label for="vld4_f64"><div>float64x1x4_t <b><b>vld4_f64</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_f64" type="checkbox"><label for="vld4q_f64"><div>float64x2x4_t <b><b>vld4q_f64</b></b> (float64_t const * ptr)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_s8" type="checkbox"><label for="vld2_dup_s8"><div>int8x8x2_t <b><b>vld2_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_s8" type="checkbox"><label for="vld2q_dup_s8"><div>int8x16x2_t <b><b>vld2q_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_s16" type="checkbox"><label for="vld2_dup_s16"><div>int16x4x2_t <b><b>vld2_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_s16" type="checkbox"><label for="vld2q_dup_s16"><div>int16x8x2_t <b><b>vld2q_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_s32" type="checkbox"><label for="vld2_dup_s32"><div>int32x2x2_t <b><b>vld2_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_s32" type="checkbox"><label for="vld2q_dup_s32"><div>int32x4x2_t <b><b>vld2q_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_u8" type="checkbox"><label for="vld2_dup_u8"><div>uint8x8x2_t <b><b>vld2_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_u8" type="checkbox"><label for="vld2q_dup_u8"><div>uint8x16x2_t <b><b>vld2q_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_u16" type="checkbox"><label for="vld2_dup_u16"><div>uint16x4x2_t <b><b>vld2_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_u16" type="checkbox"><label for="vld2q_dup_u16"><div>uint16x8x2_t <b><b>vld2q_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_u32" type="checkbox"><label for="vld2_dup_u32"><div>uint32x2x2_t <b><b>vld2_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_u32" type="checkbox"><label for="vld2q_dup_u32"><div>uint32x4x2_t <b><b>vld2q_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_f16" type="checkbox"><label for="vld2_dup_f16"><div>float16x4x2_t <b><b>vld2_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_f16" type="checkbox"><label for="vld2q_dup_f16"><div>float16x8x2_t <b><b>vld2q_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_f32" type="checkbox"><label for="vld2_dup_f32"><div>float32x2x2_t <b><b>vld2_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_f32" type="checkbox"><label for="vld2q_dup_f32"><div>float32x4x2_t <b><b>vld2q_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_p8" type="checkbox"><label for="vld2_dup_p8"><div>poly8x8x2_t <b><b>vld2_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_p8" type="checkbox"><label for="vld2q_dup_p8"><div>poly8x16x2_t <b><b>vld2q_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_p16" type="checkbox"><label for="vld2_dup_p16"><div>poly16x4x2_t <b><b>vld2_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_p16" type="checkbox"><label for="vld2q_dup_p16"><div>poly16x8x2_t <b><b>vld2q_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_s64" type="checkbox"><label for="vld2_dup_s64"><div>int64x1x2_t <b><b>vld2_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_u64" type="checkbox"><label for="vld2_dup_u64"><div>uint64x1x2_t <b><b>vld2_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_p64" type="checkbox"><label for="vld2_dup_p64"><div>poly64x1x2_t <b><b>vld2_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_s64" type="checkbox"><label for="vld2q_dup_s64"><div>int64x2x2_t <b><b>vld2q_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_u64" type="checkbox"><label for="vld2q_dup_u64"><div>uint64x2x2_t <b><b>vld2q_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_p64" type="checkbox"><label for="vld2q_dup_p64"><div>poly64x2x2_t <b><b>vld2q_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_dup_f64" type="checkbox"><label for="vld2_dup_f64"><div>float64x1x2_t <b><b>vld2_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_dup_f64" type="checkbox"><label for="vld2q_dup_f64"><div>float64x2x2_t <b><b>vld2q_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load single 2-element structure and replicate to all lanes of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2r-load-single-2-element-structure-and-replicate-to-all-lanes-of-two-registers">LD2R</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_s8" type="checkbox"><label for="vld3_dup_s8"><div>int8x8x3_t <b><b>vld3_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_s8" type="checkbox"><label for="vld3q_dup_s8"><div>int8x16x3_t <b><b>vld3q_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_s16" type="checkbox"><label for="vld3_dup_s16"><div>int16x4x3_t <b><b>vld3_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_s16" type="checkbox"><label for="vld3q_dup_s16"><div>int16x8x3_t <b><b>vld3q_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_s32" type="checkbox"><label for="vld3_dup_s32"><div>int32x2x3_t <b><b>vld3_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_s32" type="checkbox"><label for="vld3q_dup_s32"><div>int32x4x3_t <b><b>vld3q_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_u8" type="checkbox"><label for="vld3_dup_u8"><div>uint8x8x3_t <b><b>vld3_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_u8" type="checkbox"><label for="vld3q_dup_u8"><div>uint8x16x3_t <b><b>vld3q_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_u16" type="checkbox"><label for="vld3_dup_u16"><div>uint16x4x3_t <b><b>vld3_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_u16" type="checkbox"><label for="vld3q_dup_u16"><div>uint16x8x3_t <b><b>vld3q_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_u32" type="checkbox"><label for="vld3_dup_u32"><div>uint32x2x3_t <b><b>vld3_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_u32" type="checkbox"><label for="vld3q_dup_u32"><div>uint32x4x3_t <b><b>vld3q_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_f16" type="checkbox"><label for="vld3_dup_f16"><div>float16x4x3_t <b><b>vld3_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_f16" type="checkbox"><label for="vld3q_dup_f16"><div>float16x8x3_t <b><b>vld3q_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_f32" type="checkbox"><label for="vld3_dup_f32"><div>float32x2x3_t <b><b>vld3_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_f32" type="checkbox"><label for="vld3q_dup_f32"><div>float32x4x3_t <b><b>vld3q_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_p8" type="checkbox"><label for="vld3_dup_p8"><div>poly8x8x3_t <b><b>vld3_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_p8" type="checkbox"><label for="vld3q_dup_p8"><div>poly8x16x3_t <b><b>vld3q_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_p16" type="checkbox"><label for="vld3_dup_p16"><div>poly16x4x3_t <b><b>vld3_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_p16" type="checkbox"><label for="vld3q_dup_p16"><div>poly16x8x3_t <b><b>vld3q_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_s64" type="checkbox"><label for="vld3_dup_s64"><div>int64x1x3_t <b><b>vld3_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_u64" type="checkbox"><label for="vld3_dup_u64"><div>uint64x1x3_t <b><b>vld3_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_p64" type="checkbox"><label for="vld3_dup_p64"><div>poly64x1x3_t <b><b>vld3_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_s64" type="checkbox"><label for="vld3q_dup_s64"><div>int64x2x3_t <b><b>vld3q_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_u64" type="checkbox"><label for="vld3q_dup_u64"><div>uint64x2x3_t <b><b>vld3q_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_p64" type="checkbox"><label for="vld3q_dup_p64"><div>poly64x2x3_t <b><b>vld3q_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_dup_f64" type="checkbox"><label for="vld3_dup_f64"><div>float64x1x3_t <b><b>vld3_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_dup_f64" type="checkbox"><label for="vld3q_dup_f64"><div>float64x2x3_t <b><b>vld3q_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load single 3-element structure and replicate to all lanes of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3r-load-single-3-element-structure-and-replicate-to-all-lanes-of-three-registers">LD3R</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_s8" type="checkbox"><label for="vld4_dup_s8"><div>int8x8x4_t <b><b>vld4_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_s8" type="checkbox"><label for="vld4q_dup_s8"><div>int8x16x4_t <b><b>vld4q_dup_s8</b></b> (int8_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_s16" type="checkbox"><label for="vld4_dup_s16"><div>int16x4x4_t <b><b>vld4_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_s16" type="checkbox"><label for="vld4q_dup_s16"><div>int16x8x4_t <b><b>vld4q_dup_s16</b></b> (int16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_s32" type="checkbox"><label for="vld4_dup_s32"><div>int32x2x4_t <b><b>vld4_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_s32" type="checkbox"><label for="vld4q_dup_s32"><div>int32x4x4_t <b><b>vld4q_dup_s32</b></b> (int32_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_u8" type="checkbox"><label for="vld4_dup_u8"><div>uint8x8x4_t <b><b>vld4_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_u8" type="checkbox"><label for="vld4q_dup_u8"><div>uint8x16x4_t <b><b>vld4q_dup_u8</b></b> (uint8_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_u16" type="checkbox"><label for="vld4_dup_u16"><div>uint16x4x4_t <b><b>vld4_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_u16" type="checkbox"><label for="vld4q_dup_u16"><div>uint16x8x4_t <b><b>vld4q_dup_u16</b></b> (uint16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_u32" type="checkbox"><label for="vld4_dup_u32"><div>uint32x2x4_t <b><b>vld4_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_u32" type="checkbox"><label for="vld4q_dup_u32"><div>uint32x4x4_t <b><b>vld4q_dup_u32</b></b> (uint32_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_f16" type="checkbox"><label for="vld4_dup_f16"><div>float16x4x4_t <b><b>vld4_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_f16" type="checkbox"><label for="vld4q_dup_f16"><div>float16x8x4_t <b><b>vld4q_dup_f16</b></b> (float16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_f32" type="checkbox"><label for="vld4_dup_f32"><div>float32x2x4_t <b><b>vld4_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_f32" type="checkbox"><label for="vld4q_dup_f32"><div>float32x4x4_t <b><b>vld4q_dup_f32</b></b> (float32_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_p8" type="checkbox"><label for="vld4_dup_p8"><div>poly8x8x4_t <b><b>vld4_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_p8" type="checkbox"><label for="vld4q_dup_p8"><div>poly8x16x4_t <b><b>vld4q_dup_p8</b></b> (poly8_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_p16" type="checkbox"><label for="vld4_dup_p16"><div>poly16x4x4_t <b><b>vld4_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_p16" type="checkbox"><label for="vld4q_dup_p16"><div>poly16x8x4_t <b><b>vld4q_dup_p16</b></b> (poly16_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_s64" type="checkbox"><label for="vld4_dup_s64"><div>int64x1x4_t <b><b>vld4_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_u64" type="checkbox"><label for="vld4_dup_u64"><div>uint64x1x4_t <b><b>vld4_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_p64" type="checkbox"><label for="vld4_dup_p64"><div>poly64x1x4_t <b><b>vld4_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_s64" type="checkbox"><label for="vld4q_dup_s64"><div>int64x2x4_t <b><b>vld4q_dup_s64</b></b> (int64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_u64" type="checkbox"><label for="vld4q_dup_u64"><div>uint64x2x4_t <b><b>vld4q_dup_u64</b></b> (uint64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_p64" type="checkbox"><label for="vld4q_dup_p64"><div>poly64x2x4_t <b><b>vld4q_dup_p64</b></b> (poly64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_dup_f64" type="checkbox"><label for="vld4_dup_f64"><div>float64x1x4_t <b><b>vld4_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_dup_f64" type="checkbox"><label for="vld4q_dup_f64"><div>float64x2x4_t <b><b>vld4q_dup_f64</b></b> (float64_t const * ptr)<span class="right">Load single 4-element structure and replicate to all lanes of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4r-load-single-4-element-structure-and-replicate-to-all-lanes-of-four-registers">LD4R</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_s8" type="checkbox"><label for="vst2_s8"><div>void <b><b>vst2_s8</b></b> (int8_t * ptr, int8x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_s8" type="checkbox"><label for="vst2q_s8"><div>void <b><b>vst2q_s8</b></b> (int8_t * ptr, int8x16x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_s16" type="checkbox"><label for="vst2_s16"><div>void <b><b>vst2_s16</b></b> (int16_t * ptr, int16x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_s16" type="checkbox"><label for="vst2q_s16"><div>void <b><b>vst2q_s16</b></b> (int16_t * ptr, int16x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_s32" type="checkbox"><label for="vst2_s32"><div>void <b><b>vst2_s32</b></b> (int32_t * ptr, int32x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_s32" type="checkbox"><label for="vst2q_s32"><div>void <b><b>vst2q_s32</b></b> (int32_t * ptr, int32x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_u8" type="checkbox"><label for="vst2_u8"><div>void <b><b>vst2_u8</b></b> (uint8_t * ptr, uint8x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_u8" type="checkbox"><label for="vst2q_u8"><div>void <b><b>vst2q_u8</b></b> (uint8_t * ptr, uint8x16x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_u16" type="checkbox"><label for="vst2_u16"><div>void <b><b>vst2_u16</b></b> (uint16_t * ptr, uint16x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_u16" type="checkbox"><label for="vst2q_u16"><div>void <b><b>vst2q_u16</b></b> (uint16_t * ptr, uint16x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_u32" type="checkbox"><label for="vst2_u32"><div>void <b><b>vst2_u32</b></b> (uint32_t * ptr, uint32x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_u32" type="checkbox"><label for="vst2q_u32"><div>void <b><b>vst2q_u32</b></b> (uint32_t * ptr, uint32x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_f16" type="checkbox"><label for="vst2_f16"><div>void <b><b>vst2_f16</b></b> (float16_t * ptr, float16x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_f16" type="checkbox"><label for="vst2q_f16"><div>void <b><b>vst2q_f16</b></b> (float16_t * ptr, float16x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_f32" type="checkbox"><label for="vst2_f32"><div>void <b><b>vst2_f32</b></b> (float32_t * ptr, float32x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_f32" type="checkbox"><label for="vst2q_f32"><div>void <b><b>vst2q_f32</b></b> (float32_t * ptr, float32x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_p8" type="checkbox"><label for="vst2_p8"><div>void <b><b>vst2_p8</b></b> (poly8_t * ptr, poly8x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_p8" type="checkbox"><label for="vst2q_p8"><div>void <b><b>vst2q_p8</b></b> (poly8_t * ptr, poly8x16x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_p16" type="checkbox"><label for="vst2_p16"><div>void <b><b>vst2_p16</b></b> (poly16_t * ptr, poly16x4x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_p16" type="checkbox"><label for="vst2q_p16"><div>void <b><b>vst2q_p16</b></b> (poly16_t * ptr, poly16x8x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_s64" type="checkbox"><label for="vst2_s64"><div>void <b><b>vst2_s64</b></b> (int64_t * ptr, int64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_u64" type="checkbox"><label for="vst2_u64"><div>void <b><b>vst2_u64</b></b> (uint64_t * ptr, uint64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_p64" type="checkbox"><label for="vst2_p64"><div>void <b><b>vst2_p64</b></b> (poly64_t * ptr, poly64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_s64" type="checkbox"><label for="vst2q_s64"><div>void <b><b>vst2q_s64</b></b> (int64_t * ptr, int64x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_u64" type="checkbox"><label for="vst2q_u64"><div>void <b><b>vst2q_u64</b></b> (uint64_t * ptr, uint64x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_p64" type="checkbox"><label for="vst2q_p64"><div>void <b><b>vst2q_p64</b></b> (poly64_t * ptr, poly64x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_f64" type="checkbox"><label for="vst2_f64"><div>void <b><b>vst2_f64</b></b> (float64_t * ptr, float64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_f64" type="checkbox"><label for="vst2q_f64"><div>void <b><b>vst2q_f64</b></b> (float64_t * ptr, float64x2x2_t val)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3_s8" type="checkbox"><label for="vst3_s8"><div>void <b><b>vst3_s8</b></b> (int8_t * ptr, int8x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_s8" type="checkbox"><label for="vst3q_s8"><div>void <b><b>vst3q_s8</b></b> (int8_t * ptr, int8x16x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_s16" type="checkbox"><label for="vst3_s16"><div>void <b><b>vst3_s16</b></b> (int16_t * ptr, int16x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_s16" type="checkbox"><label for="vst3q_s16"><div>void <b><b>vst3q_s16</b></b> (int16_t * ptr, int16x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_s32" type="checkbox"><label for="vst3_s32"><div>void <b><b>vst3_s32</b></b> (int32_t * ptr, int32x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_s32" type="checkbox"><label for="vst3q_s32"><div>void <b><b>vst3q_s32</b></b> (int32_t * ptr, int32x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_u8" type="checkbox"><label for="vst3_u8"><div>void <b><b>vst3_u8</b></b> (uint8_t * ptr, uint8x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_u8" type="checkbox"><label for="vst3q_u8"><div>void <b><b>vst3q_u8</b></b> (uint8_t * ptr, uint8x16x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_u16" type="checkbox"><label for="vst3_u16"><div>void <b><b>vst3_u16</b></b> (uint16_t * ptr, uint16x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_u16" type="checkbox"><label for="vst3q_u16"><div>void <b><b>vst3q_u16</b></b> (uint16_t * ptr, uint16x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_u32" type="checkbox"><label for="vst3_u32"><div>void <b><b>vst3_u32</b></b> (uint32_t * ptr, uint32x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_u32" type="checkbox"><label for="vst3q_u32"><div>void <b><b>vst3q_u32</b></b> (uint32_t * ptr, uint32x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_f16" type="checkbox"><label for="vst3_f16"><div>void <b><b>vst3_f16</b></b> (float16_t * ptr, float16x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_f16" type="checkbox"><label for="vst3q_f16"><div>void <b><b>vst3q_f16</b></b> (float16_t * ptr, float16x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_f32" type="checkbox"><label for="vst3_f32"><div>void <b><b>vst3_f32</b></b> (float32_t * ptr, float32x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_f32" type="checkbox"><label for="vst3q_f32"><div>void <b><b>vst3q_f32</b></b> (float32_t * ptr, float32x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_p8" type="checkbox"><label for="vst3_p8"><div>void <b><b>vst3_p8</b></b> (poly8_t * ptr, poly8x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_p8" type="checkbox"><label for="vst3q_p8"><div>void <b><b>vst3q_p8</b></b> (poly8_t * ptr, poly8x16x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_p16" type="checkbox"><label for="vst3_p16"><div>void <b><b>vst3_p16</b></b> (poly16_t * ptr, poly16x4x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_p16" type="checkbox"><label for="vst3q_p16"><div>void <b><b>vst3q_p16</b></b> (poly16_t * ptr, poly16x8x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_s64" type="checkbox"><label for="vst3_s64"><div>void <b><b>vst3_s64</b></b> (int64_t * ptr, int64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_u64" type="checkbox"><label for="vst3_u64"><div>void <b><b>vst3_u64</b></b> (uint64_t * ptr, uint64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_p64" type="checkbox"><label for="vst3_p64"><div>void <b><b>vst3_p64</b></b> (poly64_t * ptr, poly64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_s64" type="checkbox"><label for="vst3q_s64"><div>void <b><b>vst3q_s64</b></b> (int64_t * ptr, int64x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_u64" type="checkbox"><label for="vst3q_u64"><div>void <b><b>vst3q_u64</b></b> (uint64_t * ptr, uint64x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_p64" type="checkbox"><label for="vst3q_p64"><div>void <b><b>vst3q_p64</b></b> (poly64_t * ptr, poly64x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3_f64" type="checkbox"><label for="vst3_f64"><div>void <b><b>vst3_f64</b></b> (float64_t * ptr, float64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_f64" type="checkbox"><label for="vst3q_f64"><div>void <b><b>vst3q_f64</b></b> (float64_t * ptr, float64x2x3_t val)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_s8" type="checkbox"><label for="vst4_s8"><div>void <b><b>vst4_s8</b></b> (int8_t * ptr, int8x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_s8" type="checkbox"><label for="vst4q_s8"><div>void <b><b>vst4q_s8</b></b> (int8_t * ptr, int8x16x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_s16" type="checkbox"><label for="vst4_s16"><div>void <b><b>vst4_s16</b></b> (int16_t * ptr, int16x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_s16" type="checkbox"><label for="vst4q_s16"><div>void <b><b>vst4q_s16</b></b> (int16_t * ptr, int16x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_s32" type="checkbox"><label for="vst4_s32"><div>void <b><b>vst4_s32</b></b> (int32_t * ptr, int32x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_s32" type="checkbox"><label for="vst4q_s32"><div>void <b><b>vst4q_s32</b></b> (int32_t * ptr, int32x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_u8" type="checkbox"><label for="vst4_u8"><div>void <b><b>vst4_u8</b></b> (uint8_t * ptr, uint8x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_u8" type="checkbox"><label for="vst4q_u8"><div>void <b><b>vst4q_u8</b></b> (uint8_t * ptr, uint8x16x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_u16" type="checkbox"><label for="vst4_u16"><div>void <b><b>vst4_u16</b></b> (uint16_t * ptr, uint16x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_u16" type="checkbox"><label for="vst4q_u16"><div>void <b><b>vst4q_u16</b></b> (uint16_t * ptr, uint16x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_u32" type="checkbox"><label for="vst4_u32"><div>void <b><b>vst4_u32</b></b> (uint32_t * ptr, uint32x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_u32" type="checkbox"><label for="vst4q_u32"><div>void <b><b>vst4q_u32</b></b> (uint32_t * ptr, uint32x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_f16" type="checkbox"><label for="vst4_f16"><div>void <b><b>vst4_f16</b></b> (float16_t * ptr, float16x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_f16" type="checkbox"><label for="vst4q_f16"><div>void <b><b>vst4q_f16</b></b> (float16_t * ptr, float16x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_f32" type="checkbox"><label for="vst4_f32"><div>void <b><b>vst4_f32</b></b> (float32_t * ptr, float32x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_f32" type="checkbox"><label for="vst4q_f32"><div>void <b><b>vst4q_f32</b></b> (float32_t * ptr, float32x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_p8" type="checkbox"><label for="vst4_p8"><div>void <b><b>vst4_p8</b></b> (poly8_t * ptr, poly8x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_p8" type="checkbox"><label for="vst4q_p8"><div>void <b><b>vst4q_p8</b></b> (poly8_t * ptr, poly8x16x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_p16" type="checkbox"><label for="vst4_p16"><div>void <b><b>vst4_p16</b></b> (poly16_t * ptr, poly16x4x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_p16" type="checkbox"><label for="vst4q_p16"><div>void <b><b>vst4q_p16</b></b> (poly16_t * ptr, poly16x8x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_s64" type="checkbox"><label for="vst4_s64"><div>void <b><b>vst4_s64</b></b> (int64_t * ptr, int64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_u64" type="checkbox"><label for="vst4_u64"><div>void <b><b>vst4_u64</b></b> (uint64_t * ptr, uint64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_p64" type="checkbox"><label for="vst4_p64"><div>void <b><b>vst4_p64</b></b> (poly64_t * ptr, poly64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_s64" type="checkbox"><label for="vst4q_s64"><div>void <b><b>vst4q_s64</b></b> (int64_t * ptr, int64x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_u64" type="checkbox"><label for="vst4q_u64"><div>void <b><b>vst4q_u64</b></b> (uint64_t * ptr, uint64x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_p64" type="checkbox"><label for="vst4q_p64"><div>void <b><b>vst4q_p64</b></b> (poly64_t * ptr, poly64x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_f64" type="checkbox"><label for="vst4_f64"><div>void <b><b>vst4_f64</b></b> (float64_t * ptr, float64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_f64" type="checkbox"><label for="vst4q_f64"><div>void <b><b>vst4q_f64</b></b> (float64_t * ptr, float64x2x4_t val)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_s16" type="checkbox"><label for="vld2_lane_s16"><div>int16x4x2_t <b><b>vld2_lane_s16</b></b> (int16_t const * ptr, int16x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_s16" type="checkbox"><label for="vld2q_lane_s16"><div>int16x8x2_t <b><b>vld2q_lane_s16</b></b> (int16_t const * ptr, int16x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_s32" type="checkbox"><label for="vld2_lane_s32"><div>int32x2x2_t <b><b>vld2_lane_s32</b></b> (int32_t const * ptr, int32x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_s32" type="checkbox"><label for="vld2q_lane_s32"><div>int32x4x2_t <b><b>vld2q_lane_s32</b></b> (int32_t const * ptr, int32x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_u16" type="checkbox"><label for="vld2_lane_u16"><div>uint16x4x2_t <b><b>vld2_lane_u16</b></b> (uint16_t const * ptr, uint16x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_u16" type="checkbox"><label for="vld2q_lane_u16"><div>uint16x8x2_t <b><b>vld2q_lane_u16</b></b> (uint16_t const * ptr, uint16x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_u32" type="checkbox"><label for="vld2_lane_u32"><div>uint32x2x2_t <b><b>vld2_lane_u32</b></b> (uint32_t const * ptr, uint32x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_u32" type="checkbox"><label for="vld2q_lane_u32"><div>uint32x4x2_t <b><b>vld2q_lane_u32</b></b> (uint32_t const * ptr, uint32x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_f16" type="checkbox"><label for="vld2_lane_f16"><div>float16x4x2_t <b><b>vld2_lane_f16</b></b> (float16_t const * ptr, float16x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_f16" type="checkbox"><label for="vld2q_lane_f16"><div>float16x8x2_t <b><b>vld2q_lane_f16</b></b> (float16_t const * ptr, float16x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_f32" type="checkbox"><label for="vld2_lane_f32"><div>float32x2x2_t <b><b>vld2_lane_f32</b></b> (float32_t const * ptr, float32x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_f32" type="checkbox"><label for="vld2q_lane_f32"><div>float32x4x2_t <b><b>vld2q_lane_f32</b></b> (float32_t const * ptr, float32x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_p16" type="checkbox"><label for="vld2_lane_p16"><div>poly16x4x2_t <b><b>vld2_lane_p16</b></b> (poly16_t const * ptr, poly16x4x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_p16" type="checkbox"><label for="vld2q_lane_p16"><div>poly16x8x2_t <b><b>vld2q_lane_p16</b></b> (poly16_t const * ptr, poly16x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_s8" type="checkbox"><label for="vld2_lane_s8"><div>int8x8x2_t <b><b>vld2_lane_s8</b></b> (int8_t const * ptr, int8x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_u8" type="checkbox"><label for="vld2_lane_u8"><div>uint8x8x2_t <b><b>vld2_lane_u8</b></b> (uint8_t const * ptr, uint8x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_p8" type="checkbox"><label for="vld2_lane_p8"><div>poly8x8x2_t <b><b>vld2_lane_p8</b></b> (poly8_t const * ptr, poly8x8x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_s8" type="checkbox"><label for="vld2q_lane_s8"><div>int8x16x2_t <b><b>vld2q_lane_s8</b></b> (int8_t const * ptr, int8x16x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_u8" type="checkbox"><label for="vld2q_lane_u8"><div>uint8x16x2_t <b><b>vld2q_lane_u8</b></b> (uint8_t const * ptr, uint8x16x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_p8" type="checkbox"><label for="vld2q_lane_p8"><div>poly8x16x2_t <b><b>vld2q_lane_p8</b></b> (poly8_t const * ptr, poly8x16x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_s64" type="checkbox"><label for="vld2_lane_s64"><div>int64x1x2_t <b><b>vld2_lane_s64</b></b> (int64_t const * ptr, int64x1x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>ptr &rarr; Xn
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_s64" type="checkbox"><label for="vld2q_lane_s64"><div>int64x2x2_t <b><b>vld2q_lane_s64</b></b> (int64_t const * ptr, int64x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>ptr &rarr; Xn
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_u64" type="checkbox"><label for="vld2_lane_u64"><div>uint64x1x2_t <b><b>vld2_lane_u64</b></b> (uint64_t const * ptr, uint64x1x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_u64" type="checkbox"><label for="vld2q_lane_u64"><div>uint64x2x2_t <b><b>vld2q_lane_u64</b></b> (uint64_t const * ptr, uint64x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_p64" type="checkbox"><label for="vld2_lane_p64"><div>poly64x1x2_t <b><b>vld2_lane_p64</b></b> (poly64_t const * ptr, poly64x1x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_p64" type="checkbox"><label for="vld2q_lane_p64"><div>poly64x2x2_t <b><b>vld2q_lane_p64</b></b> (poly64_t const * ptr, poly64x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2_lane_f64" type="checkbox"><label for="vld2_lane_f64"><div>float64x1x2_t <b><b>vld2_lane_f64</b></b> (float64_t const * ptr, float64x1x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld2q_lane_f64" type="checkbox"><label for="vld2q_lane_f64"><div>float64x2x2_t <b><b>vld2q_lane_f64</b></b> (float64_t const * ptr, float64x2x2_t src, const int lane)<span class="right">Load single 2-element structure to one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld2-single-structure-load-single-2-element-structure-to-one-lane-of-two-registers">LD2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_s16" type="checkbox"><label for="vld3_lane_s16"><div>int16x4x3_t <b><b>vld3_lane_s16</b></b> (int16_t const * ptr, int16x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_s16" type="checkbox"><label for="vld3q_lane_s16"><div>int16x8x3_t <b><b>vld3q_lane_s16</b></b> (int16_t const * ptr, int16x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_s32" type="checkbox"><label for="vld3_lane_s32"><div>int32x2x3_t <b><b>vld3_lane_s32</b></b> (int32_t const * ptr, int32x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2S <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_s32" type="checkbox"><label for="vld3q_lane_s32"><div>int32x4x3_t <b><b>vld3q_lane_s32</b></b> (int32_t const * ptr, int32x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4S <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_u16" type="checkbox"><label for="vld3_lane_u16"><div>uint16x4x3_t <b><b>vld3_lane_u16</b></b> (uint16_t const * ptr, uint16x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_u16" type="checkbox"><label for="vld3q_lane_u16"><div>uint16x8x3_t <b><b>vld3q_lane_u16</b></b> (uint16_t const * ptr, uint16x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_u32" type="checkbox"><label for="vld3_lane_u32"><div>uint32x2x3_t <b><b>vld3_lane_u32</b></b> (uint32_t const * ptr, uint32x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2S <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_u32" type="checkbox"><label for="vld3q_lane_u32"><div>uint32x4x3_t <b><b>vld3q_lane_u32</b></b> (uint32_t const * ptr, uint32x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4S <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_f16" type="checkbox"><label for="vld3_lane_f16"><div>float16x4x3_t <b><b>vld3_lane_f16</b></b> (float16_t const * ptr, float16x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_f16" type="checkbox"><label for="vld3q_lane_f16"><div>float16x8x3_t <b><b>vld3q_lane_f16</b></b> (float16_t const * ptr, float16x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_f32" type="checkbox"><label for="vld3_lane_f32"><div>float32x2x3_t <b><b>vld3_lane_f32</b></b> (float32_t const * ptr, float32x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2S <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_f32" type="checkbox"><label for="vld3q_lane_f32"><div>float32x4x3_t <b><b>vld3q_lane_f32</b></b> (float32_t const * ptr, float32x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4S <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_p16" type="checkbox"><label for="vld3_lane_p16"><div>poly16x4x3_t <b><b>vld3_lane_p16</b></b> (poly16_t const * ptr, poly16x4x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_p16" type="checkbox"><label for="vld3q_lane_p16"><div>poly16x8x3_t <b><b>vld3q_lane_p16</b></b> (poly16_t const * ptr, poly16x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_s8" type="checkbox"><label for="vld3_lane_s8"><div>int8x8x3_t <b><b>vld3_lane_s8</b></b> (int8_t const * ptr, int8x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8B <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_u8" type="checkbox"><label for="vld3_lane_u8"><div>uint8x8x3_t <b><b>vld3_lane_u8</b></b> (uint8_t const * ptr, uint8x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8B <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_p8" type="checkbox"><label for="vld3_lane_p8"><div>poly8x8x3_t <b><b>vld3_lane_p8</b></b> (poly8_t const * ptr, poly8x8x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.8B <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_s8" type="checkbox"><label for="vld3q_lane_s8"><div>int8x16x3_t <b><b>vld3q_lane_s8</b></b> (int8_t const * ptr, int8x16x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.16B <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_u8" type="checkbox"><label for="vld3q_lane_u8"><div>uint8x16x3_t <b><b>vld3q_lane_u8</b></b> (uint8_t const * ptr, uint8x16x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.16B <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_p8" type="checkbox"><label for="vld3q_lane_p8"><div>poly8x16x3_t <b><b>vld3q_lane_p8</b></b> (poly8_t const * ptr, poly8x16x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.16B <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_s64" type="checkbox"><label for="vld3_lane_s64"><div>int64x1x3_t <b><b>vld3_lane_s64</b></b> (int64_t const * ptr, int64x1x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_s64" type="checkbox"><label for="vld3q_lane_s64"><div>int64x2x3_t <b><b>vld3q_lane_s64</b></b> (int64_t const * ptr, int64x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_u64" type="checkbox"><label for="vld3_lane_u64"><div>uint64x1x3_t <b><b>vld3_lane_u64</b></b> (uint64_t const * ptr, uint64x1x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_u64" type="checkbox"><label for="vld3q_lane_u64"><div>uint64x2x3_t <b><b>vld3q_lane_u64</b></b> (uint64_t const * ptr, uint64x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_p64" type="checkbox"><label for="vld3_lane_p64"><div>poly64x1x3_t <b><b>vld3_lane_p64</b></b> (poly64_t const * ptr, poly64x1x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_p64" type="checkbox"><label for="vld3q_lane_p64"><div>poly64x2x3_t <b><b>vld3q_lane_p64</b></b> (poly64_t const * ptr, poly64x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3_lane_f64" type="checkbox"><label for="vld3_lane_f64"><div>float64x1x3_t <b><b>vld3_lane_f64</b></b> (float64_t const * ptr, float64x1x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld3q_lane_f64" type="checkbox"><label for="vld3q_lane_f64"><div>float64x2x3_t <b><b>vld3q_lane_f64</b></b> (float64_t const * ptr, float64x2x3_t src, const int lane)<span class="right">Load single 3-element structure to one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld3-single-structure-load-single-3-element-structure-to-one-lane-of-three-registers">LD3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_s16" type="checkbox"><label for="vld4_lane_s16"><div>int16x4x4_t <b><b>vld4_lane_s16</b></b> (int16_t const * ptr, int16x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4H <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_s16" type="checkbox"><label for="vld4q_lane_s16"><div>int16x8x4_t <b><b>vld4q_lane_s16</b></b> (int16_t const * ptr, int16x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8H <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_s32" type="checkbox"><label for="vld4_lane_s32"><div>int32x2x4_t <b><b>vld4_lane_s32</b></b> (int32_t const * ptr, int32x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2S <br />
+ src.val[2] &rarr; Vt3.2S <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_s32" type="checkbox"><label for="vld4q_lane_s32"><div>int32x4x4_t <b><b>vld4q_lane_s32</b></b> (int32_t const * ptr, int32x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4S <br />
+ src.val[2] &rarr; Vt3.4S <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_u16" type="checkbox"><label for="vld4_lane_u16"><div>uint16x4x4_t <b><b>vld4_lane_u16</b></b> (uint16_t const * ptr, uint16x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4H <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_u16" type="checkbox"><label for="vld4q_lane_u16"><div>uint16x8x4_t <b><b>vld4q_lane_u16</b></b> (uint16_t const * ptr, uint16x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8H <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_u32" type="checkbox"><label for="vld4_lane_u32"><div>uint32x2x4_t <b><b>vld4_lane_u32</b></b> (uint32_t const * ptr, uint32x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2S <br />
+ src.val[2] &rarr; Vt3.2S <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_u32" type="checkbox"><label for="vld4q_lane_u32"><div>uint32x4x4_t <b><b>vld4q_lane_u32</b></b> (uint32_t const * ptr, uint32x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4S <br />
+ src.val[2] &rarr; Vt3.4S <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_f16" type="checkbox"><label for="vld4_lane_f16"><div>float16x4x4_t <b><b>vld4_lane_f16</b></b> (float16_t const * ptr, float16x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4H <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_f16" type="checkbox"><label for="vld4q_lane_f16"><div>float16x8x4_t <b><b>vld4q_lane_f16</b></b> (float16_t const * ptr, float16x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8H <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_f32" type="checkbox"><label for="vld4_lane_f32"><div>float32x2x4_t <b><b>vld4_lane_f32</b></b> (float32_t const * ptr, float32x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2S <br />
+ src.val[2] &rarr; Vt3.2S <br />
+ src.val[1] &rarr; Vt2.2S <br />
+ src.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_f32" type="checkbox"><label for="vld4q_lane_f32"><div>float32x4x4_t <b><b>vld4q_lane_f32</b></b> (float32_t const * ptr, float32x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4S <br />
+ src.val[2] &rarr; Vt3.4S <br />
+ src.val[1] &rarr; Vt2.4S <br />
+ src.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_p16" type="checkbox"><label for="vld4_lane_p16"><div>poly16x4x4_t <b><b>vld4_lane_p16</b></b> (poly16_t const * ptr, poly16x4x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.4H <br />
+ src.val[2] &rarr; Vt3.4H <br />
+ src.val[1] &rarr; Vt2.4H <br />
+ src.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_p16" type="checkbox"><label for="vld4q_lane_p16"><div>poly16x8x4_t <b><b>vld4q_lane_p16</b></b> (poly16_t const * ptr, poly16x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8H <br />
+ src.val[2] &rarr; Vt3.8H <br />
+ src.val[1] &rarr; Vt2.8H <br />
+ src.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_s8" type="checkbox"><label for="vld4_lane_s8"><div>int8x8x4_t <b><b>vld4_lane_s8</b></b> (int8_t const * ptr, int8x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8B <br />
+ src.val[2] &rarr; Vt3.8B <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_u8" type="checkbox"><label for="vld4_lane_u8"><div>uint8x8x4_t <b><b>vld4_lane_u8</b></b> (uint8_t const * ptr, uint8x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8B <br />
+ src.val[2] &rarr; Vt3.8B <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_p8" type="checkbox"><label for="vld4_lane_p8"><div>poly8x8x4_t <b><b>vld4_lane_p8</b></b> (poly8_t const * ptr, poly8x8x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.8B <br />
+ src.val[2] &rarr; Vt3.8B <br />
+ src.val[1] &rarr; Vt2.8B <br />
+ src.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_s8" type="checkbox"><label for="vld4q_lane_s8"><div>int8x16x4_t <b><b>vld4q_lane_s8</b></b> (int8_t const * ptr, int8x16x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.16B <br />
+ src.val[2] &rarr; Vt3.16B <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_u8" type="checkbox"><label for="vld4q_lane_u8"><div>uint8x16x4_t <b><b>vld4q_lane_u8</b></b> (uint8_t const * ptr, uint8x16x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.16B <br />
+ src.val[2] &rarr; Vt3.16B <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_p8" type="checkbox"><label for="vld4q_lane_p8"><div>poly8x16x4_t <b><b>vld4q_lane_p8</b></b> (poly8_t const * ptr, poly8x16x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.16B <br />
+ src.val[2] &rarr; Vt3.16B <br />
+ src.val[1] &rarr; Vt2.16B <br />
+ src.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_s64" type="checkbox"><label for="vld4_lane_s64"><div>int64x1x4_t <b><b>vld4_lane_s64</b></b> (int64_t const * ptr, int64x1x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.1D <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_s64" type="checkbox"><label for="vld4q_lane_s64"><div>int64x2x4_t <b><b>vld4q_lane_s64</b></b> (int64_t const * ptr, int64x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2D <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_u64" type="checkbox"><label for="vld4_lane_u64"><div>uint64x1x4_t <b><b>vld4_lane_u64</b></b> (uint64_t const * ptr, uint64x1x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.1D <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_u64" type="checkbox"><label for="vld4q_lane_u64"><div>uint64x2x4_t <b><b>vld4q_lane_u64</b></b> (uint64_t const * ptr, uint64x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2D <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_p64" type="checkbox"><label for="vld4_lane_p64"><div>poly64x1x4_t <b><b>vld4_lane_p64</b></b> (poly64_t const * ptr, poly64x1x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.1D <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_p64" type="checkbox"><label for="vld4q_lane_p64"><div>poly64x2x4_t <b><b>vld4q_lane_p64</b></b> (poly64_t const * ptr, poly64x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2D <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4_lane_f64" type="checkbox"><label for="vld4_lane_f64"><div>float64x1x4_t <b><b>vld4_lane_f64</b></b> (float64_t const * ptr, float64x1x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.1D <br />
+ src.val[2] &rarr; Vt3.1D <br />
+ src.val[1] &rarr; Vt2.1D <br />
+ src.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld4q_lane_f64" type="checkbox"><label for="vld4q_lane_f64"><div>float64x2x4_t <b><b>vld4q_lane_f64</b></b> (float64_t const * ptr, float64x2x4_t src, const int lane)<span class="right">Load single 4-element structure to one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&amp;FP registers without affecting the other bits of the registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld4-single-structure-load-single-4-element-structure-to-one-lane-of-four-registers">LD4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ src.val[3] &rarr; Vt4.2D <br />
+ src.val[2] &rarr; Vt3.2D <br />
+ src.val[1] &rarr; Vt2.2D <br />
+ src.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_s8" type="checkbox"><label for="vst2_lane_s8"><div>void <b><b>vst2_lane_s8</b></b> (int8_t * ptr, int8x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_u8" type="checkbox"><label for="vst2_lane_u8"><div>void <b><b>vst2_lane_u8</b></b> (uint8_t * ptr, uint8x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_p8" type="checkbox"><label for="vst2_lane_p8"><div>void <b><b>vst2_lane_p8</b></b> (poly8_t * ptr, poly8x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_s8" type="checkbox"><label for="vst3_lane_s8"><div>void <b><b>vst3_lane_s8</b></b> (int8_t * ptr, int8x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_u8" type="checkbox"><label for="vst3_lane_u8"><div>void <b><b>vst3_lane_u8</b></b> (uint8_t * ptr, uint8x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_p8" type="checkbox"><label for="vst3_lane_p8"><div>void <b><b>vst3_lane_p8</b></b> (poly8_t * ptr, poly8x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_s8" type="checkbox"><label for="vst4_lane_s8"><div>void <b><b>vst4_lane_s8</b></b> (int8_t * ptr, int8x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_u8" type="checkbox"><label for="vst4_lane_u8"><div>void <b><b>vst4_lane_u8</b></b> (uint8_t * ptr, uint8x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_p8" type="checkbox"><label for="vst4_lane_p8"><div>void <b><b>vst4_lane_p8</b></b> (poly8_t * ptr, poly8x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_s16" type="checkbox"><label for="vst2_lane_s16"><div>void <b><b>vst2_lane_s16</b></b> (int16_t * ptr, int16x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_s16" type="checkbox"><label for="vst2q_lane_s16"><div>void <b><b>vst2q_lane_s16</b></b> (int16_t * ptr, int16x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_s32" type="checkbox"><label for="vst2_lane_s32"><div>void <b><b>vst2_lane_s32</b></b> (int32_t * ptr, int32x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_s32" type="checkbox"><label for="vst2q_lane_s32"><div>void <b><b>vst2q_lane_s32</b></b> (int32_t * ptr, int32x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_u16" type="checkbox"><label for="vst2_lane_u16"><div>void <b><b>vst2_lane_u16</b></b> (uint16_t * ptr, uint16x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_u16" type="checkbox"><label for="vst2q_lane_u16"><div>void <b><b>vst2q_lane_u16</b></b> (uint16_t * ptr, uint16x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_u32" type="checkbox"><label for="vst2_lane_u32"><div>void <b><b>vst2_lane_u32</b></b> (uint32_t * ptr, uint32x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_u32" type="checkbox"><label for="vst2q_lane_u32"><div>void <b><b>vst2q_lane_u32</b></b> (uint32_t * ptr, uint32x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_f16" type="checkbox"><label for="vst2_lane_f16"><div>void <b><b>vst2_lane_f16</b></b> (float16_t * ptr, float16x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_f16" type="checkbox"><label for="vst2q_lane_f16"><div>void <b><b>vst2q_lane_f16</b></b> (float16_t * ptr, float16x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_f32" type="checkbox"><label for="vst2_lane_f32"><div>void <b><b>vst2_lane_f32</b></b> (float32_t * ptr, float32x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_f32" type="checkbox"><label for="vst2q_lane_f32"><div>void <b><b>vst2q_lane_f32</b></b> (float32_t * ptr, float32x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.s - Vt2.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_p16" type="checkbox"><label for="vst2_lane_p16"><div>void <b><b>vst2_lane_p16</b></b> (poly16_t * ptr, poly16x4x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_p16" type="checkbox"><label for="vst2q_lane_p16"><div>void <b><b>vst2q_lane_p16</b></b> (poly16_t * ptr, poly16x8x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.h - Vt2.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_s8" type="checkbox"><label for="vst2q_lane_s8"><div>void <b><b>vst2q_lane_s8</b></b> (int8_t * ptr, int8x16x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_u8" type="checkbox"><label for="vst2q_lane_u8"><div>void <b><b>vst2q_lane_u8</b></b> (uint8_t * ptr, uint8x16x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_p8" type="checkbox"><label for="vst2q_lane_p8"><div>void <b><b>vst2q_lane_p8</b></b> (poly8_t * ptr, poly8x16x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.b - Vt2.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_s64" type="checkbox"><label for="vst2_lane_s64"><div>void <b><b>vst2_lane_s64</b></b> (int64_t * ptr, int64x1x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_s64" type="checkbox"><label for="vst2q_lane_s64"><div>void <b><b>vst2q_lane_s64</b></b> (int64_t * ptr, int64x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_u64" type="checkbox"><label for="vst2_lane_u64"><div>void <b><b>vst2_lane_u64</b></b> (uint64_t * ptr, uint64x1x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_u64" type="checkbox"><label for="vst2q_lane_u64"><div>void <b><b>vst2q_lane_u64</b></b> (uint64_t * ptr, uint64x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_p64" type="checkbox"><label for="vst2_lane_p64"><div>void <b><b>vst2_lane_p64</b></b> (poly64_t * ptr, poly64x1x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_p64" type="checkbox"><label for="vst2q_lane_p64"><div>void <b><b>vst2q_lane_p64</b></b> (poly64_t * ptr, poly64x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2_lane_f64" type="checkbox"><label for="vst2_lane_f64"><div>void <b><b>vst2_lane_f64</b></b> (float64_t * ptr, float64x1x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst2q_lane_f64" type="checkbox"><label for="vst2q_lane_f64"><div>void <b><b>vst2q_lane_f64</b></b> (float64_t * ptr, float64x2x2_t val, const int lane)<span class="right">Store single 2-element structure from one lane of two registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st2-single-structure-store-single-2-element-structure-from-one-lane-of-two-registers">ST2</a> {Vt.d - Vt2.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 2 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_s16" type="checkbox"><label for="vst3_lane_s16"><div>void <b><b>vst3_lane_s16</b></b> (int16_t * ptr, int16x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_s16" type="checkbox"><label for="vst3q_lane_s16"><div>void <b><b>vst3q_lane_s16</b></b> (int16_t * ptr, int16x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_s32" type="checkbox"><label for="vst3_lane_s32"><div>void <b><b>vst3_lane_s32</b></b> (int32_t * ptr, int32x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_s32" type="checkbox"><label for="vst3q_lane_s32"><div>void <b><b>vst3q_lane_s32</b></b> (int32_t * ptr, int32x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_u16" type="checkbox"><label for="vst3_lane_u16"><div>void <b><b>vst3_lane_u16</b></b> (uint16_t * ptr, uint16x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_u16" type="checkbox"><label for="vst3q_lane_u16"><div>void <b><b>vst3q_lane_u16</b></b> (uint16_t * ptr, uint16x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_u32" type="checkbox"><label for="vst3_lane_u32"><div>void <b><b>vst3_lane_u32</b></b> (uint32_t * ptr, uint32x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_u32" type="checkbox"><label for="vst3q_lane_u32"><div>void <b><b>vst3q_lane_u32</b></b> (uint32_t * ptr, uint32x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_f16" type="checkbox"><label for="vst3_lane_f16"><div>void <b><b>vst3_lane_f16</b></b> (float16_t * ptr, float16x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_f16" type="checkbox"><label for="vst3q_lane_f16"><div>void <b><b>vst3q_lane_f16</b></b> (float16_t * ptr, float16x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_f32" type="checkbox"><label for="vst3_lane_f32"><div>void <b><b>vst3_lane_f32</b></b> (float32_t * ptr, float32x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_f32" type="checkbox"><label for="vst3q_lane_f32"><div>void <b><b>vst3q_lane_f32</b></b> (float32_t * ptr, float32x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.s - Vt3.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_p16" type="checkbox"><label for="vst3_lane_p16"><div>void <b><b>vst3_lane_p16</b></b> (poly16_t * ptr, poly16x4x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_p16" type="checkbox"><label for="vst3q_lane_p16"><div>void <b><b>vst3q_lane_p16</b></b> (poly16_t * ptr, poly16x8x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.h - Vt3.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_s8" type="checkbox"><label for="vst3q_lane_s8"><div>void <b><b>vst3q_lane_s8</b></b> (int8_t * ptr, int8x16x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_u8" type="checkbox"><label for="vst3q_lane_u8"><div>void <b><b>vst3q_lane_u8</b></b> (uint8_t * ptr, uint8x16x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_p8" type="checkbox"><label for="vst3q_lane_p8"><div>void <b><b>vst3q_lane_p8</b></b> (poly8_t * ptr, poly8x16x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.b - Vt3.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_s64" type="checkbox"><label for="vst3_lane_s64"><div>void <b><b>vst3_lane_s64</b></b> (int64_t * ptr, int64x1x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_s64" type="checkbox"><label for="vst3q_lane_s64"><div>void <b><b>vst3q_lane_s64</b></b> (int64_t * ptr, int64x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_u64" type="checkbox"><label for="vst3_lane_u64"><div>void <b><b>vst3_lane_u64</b></b> (uint64_t * ptr, uint64x1x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_u64" type="checkbox"><label for="vst3q_lane_u64"><div>void <b><b>vst3q_lane_u64</b></b> (uint64_t * ptr, uint64x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_p64" type="checkbox"><label for="vst3_lane_p64"><div>void <b><b>vst3_lane_p64</b></b> (poly64_t * ptr, poly64x1x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_p64" type="checkbox"><label for="vst3q_lane_p64"><div>void <b><b>vst3q_lane_p64</b></b> (poly64_t * ptr, poly64x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3_lane_f64" type="checkbox"><label for="vst3_lane_f64"><div>void <b><b>vst3_lane_f64</b></b> (float64_t * ptr, float64x1x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst3q_lane_f64" type="checkbox"><label for="vst3q_lane_f64"><div>void <b><b>vst3q_lane_f64</b></b> (float64_t * ptr, float64x2x3_t val, const int lane)<span class="right">Store single 3-element structure from one lane of three registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st3-single-structure-store-single-3-element-structure-from-one-lane-of-three-registers">ST3</a> {Vt.d - Vt3.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_s16" type="checkbox"><label for="vst4_lane_s16"><div>void <b><b>vst4_lane_s16</b></b> (int16_t * ptr, int16x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_s16" type="checkbox"><label for="vst4q_lane_s16"><div>void <b><b>vst4q_lane_s16</b></b> (int16_t * ptr, int16x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_s32" type="checkbox"><label for="vst4_lane_s32"><div>void <b><b>vst4_lane_s32</b></b> (int32_t * ptr, int32x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_s32" type="checkbox"><label for="vst4q_lane_s32"><div>void <b><b>vst4q_lane_s32</b></b> (int32_t * ptr, int32x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_u16" type="checkbox"><label for="vst4_lane_u16"><div>void <b><b>vst4_lane_u16</b></b> (uint16_t * ptr, uint16x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_u16" type="checkbox"><label for="vst4q_lane_u16"><div>void <b><b>vst4q_lane_u16</b></b> (uint16_t * ptr, uint16x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_u32" type="checkbox"><label for="vst4_lane_u32"><div>void <b><b>vst4_lane_u32</b></b> (uint32_t * ptr, uint32x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_u32" type="checkbox"><label for="vst4q_lane_u32"><div>void <b><b>vst4q_lane_u32</b></b> (uint32_t * ptr, uint32x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_f16" type="checkbox"><label for="vst4_lane_f16"><div>void <b><b>vst4_lane_f16</b></b> (float16_t * ptr, float16x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_f16" type="checkbox"><label for="vst4q_lane_f16"><div>void <b><b>vst4q_lane_f16</b></b> (float16_t * ptr, float16x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_f32" type="checkbox"><label for="vst4_lane_f32"><div>void <b><b>vst4_lane_f32</b></b> (float32_t * ptr, float32x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_f32" type="checkbox"><label for="vst4q_lane_f32"><div>void <b><b>vst4q_lane_f32</b></b> (float32_t * ptr, float32x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.s - Vt4.s}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_p16" type="checkbox"><label for="vst4_lane_p16"><div>void <b><b>vst4_lane_p16</b></b> (poly16_t * ptr, poly16x4x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_p16" type="checkbox"><label for="vst4q_lane_p16"><div>void <b><b>vst4q_lane_p16</b></b> (poly16_t * ptr, poly16x8x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.h - Vt4.h}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_s8" type="checkbox"><label for="vst4q_lane_s8"><div>void <b><b>vst4q_lane_s8</b></b> (int8_t * ptr, int8x16x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_u8" type="checkbox"><label for="vst4q_lane_u8"><div>void <b><b>vst4q_lane_u8</b></b> (uint8_t * ptr, uint8x16x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_p8" type="checkbox"><label for="vst4q_lane_p8"><div>void <b><b>vst4q_lane_p8</b></b> (poly8_t * ptr, poly8x16x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.b - Vt4.b}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_s64" type="checkbox"><label for="vst4_lane_s64"><div>void <b><b>vst4_lane_s64</b></b> (int64_t * ptr, int64x1x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_s64" type="checkbox"><label for="vst4q_lane_s64"><div>void <b><b>vst4q_lane_s64</b></b> (int64_t * ptr, int64x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_u64" type="checkbox"><label for="vst4_lane_u64"><div>void <b><b>vst4_lane_u64</b></b> (uint64_t * ptr, uint64x1x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_u64" type="checkbox"><label for="vst4q_lane_u64"><div>void <b><b>vst4q_lane_u64</b></b> (uint64_t * ptr, uint64x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_p64" type="checkbox"><label for="vst4_lane_p64"><div>void <b><b>vst4_lane_p64</b></b> (poly64_t * ptr, poly64x1x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_p64" type="checkbox"><label for="vst4q_lane_p64"><div>void <b><b>vst4q_lane_p64</b></b> (poly64_t * ptr, poly64x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4_lane_f64" type="checkbox"><label for="vst4_lane_f64"><div>void <b><b>vst4_lane_f64</b></b> (float64_t * ptr, float64x1x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst4q_lane_f64" type="checkbox"><label for="vst4q_lane_f64"><div>void <b><b>vst4q_lane_f64</b></b> (float64_t * ptr, float64x2x4_t val, const int lane)<span class="right">Store single 4-element structure from one lane of four registers</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&amp;FP registers.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st4-single-structure-store-single-4-element-structure-from-one-lane-of-four-registers">ST4</a> {Vt.d - Vt4.d}[lane],[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s8_x2" type="checkbox"><label for="vst1_s8_x2"><div>void <b><b>vst1_s8_x2</b></b> (int8_t * ptr, int8x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s8_x2" type="checkbox"><label for="vst1q_s8_x2"><div>void <b><b>vst1q_s8_x2</b></b> (int8_t * ptr, int8x16x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s16_x2" type="checkbox"><label for="vst1_s16_x2"><div>void <b><b>vst1_s16_x2</b></b> (int16_t * ptr, int16x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s16_x2" type="checkbox"><label for="vst1q_s16_x2"><div>void <b><b>vst1q_s16_x2</b></b> (int16_t * ptr, int16x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s32_x2" type="checkbox"><label for="vst1_s32_x2"><div>void <b><b>vst1_s32_x2</b></b> (int32_t * ptr, int32x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s32_x2" type="checkbox"><label for="vst1q_s32_x2"><div>void <b><b>vst1q_s32_x2</b></b> (int32_t * ptr, int32x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u8_x2" type="checkbox"><label for="vst1_u8_x2"><div>void <b><b>vst1_u8_x2</b></b> (uint8_t * ptr, uint8x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u8_x2" type="checkbox"><label for="vst1q_u8_x2"><div>void <b><b>vst1q_u8_x2</b></b> (uint8_t * ptr, uint8x16x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u16_x2" type="checkbox"><label for="vst1_u16_x2"><div>void <b><b>vst1_u16_x2</b></b> (uint16_t * ptr, uint16x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u16_x2" type="checkbox"><label for="vst1q_u16_x2"><div>void <b><b>vst1q_u16_x2</b></b> (uint16_t * ptr, uint16x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u32_x2" type="checkbox"><label for="vst1_u32_x2"><div>void <b><b>vst1_u32_x2</b></b> (uint32_t * ptr, uint32x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u32_x2" type="checkbox"><label for="vst1q_u32_x2"><div>void <b><b>vst1q_u32_x2</b></b> (uint32_t * ptr, uint32x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f16_x2" type="checkbox"><label for="vst1_f16_x2"><div>void <b><b>vst1_f16_x2</b></b> (float16_t * ptr, float16x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f16_x2" type="checkbox"><label for="vst1q_f16_x2"><div>void <b><b>vst1q_f16_x2</b></b> (float16_t * ptr, float16x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f32_x2" type="checkbox"><label for="vst1_f32_x2"><div>void <b><b>vst1_f32_x2</b></b> (float32_t * ptr, float32x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f32_x2" type="checkbox"><label for="vst1q_f32_x2"><div>void <b><b>vst1q_f32_x2</b></b> (float32_t * ptr, float32x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p8_x2" type="checkbox"><label for="vst1_p8_x2"><div>void <b><b>vst1_p8_x2</b></b> (poly8_t * ptr, poly8x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p8_x2" type="checkbox"><label for="vst1q_p8_x2"><div>void <b><b>vst1q_p8_x2</b></b> (poly8_t * ptr, poly8x16x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p16_x2" type="checkbox"><label for="vst1_p16_x2"><div>void <b><b>vst1_p16_x2</b></b> (poly16_t * ptr, poly16x4x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p16_x2" type="checkbox"><label for="vst1q_p16_x2"><div>void <b><b>vst1q_p16_x2</b></b> (poly16_t * ptr, poly16x8x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s64_x2" type="checkbox"><label for="vst1_s64_x2"><div>void <b><b>vst1_s64_x2</b></b> (int64_t * ptr, int64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u64_x2" type="checkbox"><label for="vst1_u64_x2"><div>void <b><b>vst1_u64_x2</b></b> (uint64_t * ptr, uint64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p64_x2" type="checkbox"><label for="vst1_p64_x2"><div>void <b><b>vst1_p64_x2</b></b> (poly64_t * ptr, poly64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s64_x2" type="checkbox"><label for="vst1q_s64_x2"><div>void <b><b>vst1q_s64_x2</b></b> (int64_t * ptr, int64x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u64_x2" type="checkbox"><label for="vst1q_u64_x2"><div>void <b><b>vst1q_u64_x2</b></b> (uint64_t * ptr, uint64x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p64_x2" type="checkbox"><label for="vst1q_p64_x2"><div>void <b><b>vst1q_p64_x2</b></b> (poly64_t * ptr, poly64x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f64_x2" type="checkbox"><label for="vst1_f64_x2"><div>void <b><b>vst1_f64_x2</b></b> (float64_t * ptr, float64x1x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f64_x2" type="checkbox"><label for="vst1q_f64_x2"><div>void <b><b>vst1q_f64_x2</b></b> (float64_t * ptr, float64x2x2_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s8_x3" type="checkbox"><label for="vst1_s8_x3"><div>void <b><b>vst1_s8_x3</b></b> (int8_t * ptr, int8x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s8_x3" type="checkbox"><label for="vst1q_s8_x3"><div>void <b><b>vst1q_s8_x3</b></b> (int8_t * ptr, int8x16x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s16_x3" type="checkbox"><label for="vst1_s16_x3"><div>void <b><b>vst1_s16_x3</b></b> (int16_t * ptr, int16x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s16_x3" type="checkbox"><label for="vst1q_s16_x3"><div>void <b><b>vst1q_s16_x3</b></b> (int16_t * ptr, int16x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s32_x3" type="checkbox"><label for="vst1_s32_x3"><div>void <b><b>vst1_s32_x3</b></b> (int32_t * ptr, int32x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s32_x3" type="checkbox"><label for="vst1q_s32_x3"><div>void <b><b>vst1q_s32_x3</b></b> (int32_t * ptr, int32x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u8_x3" type="checkbox"><label for="vst1_u8_x3"><div>void <b><b>vst1_u8_x3</b></b> (uint8_t * ptr, uint8x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u8_x3" type="checkbox"><label for="vst1q_u8_x3"><div>void <b><b>vst1q_u8_x3</b></b> (uint8_t * ptr, uint8x16x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u16_x3" type="checkbox"><label for="vst1_u16_x3"><div>void <b><b>vst1_u16_x3</b></b> (uint16_t * ptr, uint16x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u16_x3" type="checkbox"><label for="vst1q_u16_x3"><div>void <b><b>vst1q_u16_x3</b></b> (uint16_t * ptr, uint16x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u32_x3" type="checkbox"><label for="vst1_u32_x3"><div>void <b><b>vst1_u32_x3</b></b> (uint32_t * ptr, uint32x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u32_x3" type="checkbox"><label for="vst1q_u32_x3"><div>void <b><b>vst1q_u32_x3</b></b> (uint32_t * ptr, uint32x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f16_x3" type="checkbox"><label for="vst1_f16_x3"><div>void <b><b>vst1_f16_x3</b></b> (float16_t * ptr, float16x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f16_x3" type="checkbox"><label for="vst1q_f16_x3"><div>void <b><b>vst1q_f16_x3</b></b> (float16_t * ptr, float16x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f32_x3" type="checkbox"><label for="vst1_f32_x3"><div>void <b><b>vst1_f32_x3</b></b> (float32_t * ptr, float32x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f32_x3" type="checkbox"><label for="vst1q_f32_x3"><div>void <b><b>vst1q_f32_x3</b></b> (float32_t * ptr, float32x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p8_x3" type="checkbox"><label for="vst1_p8_x3"><div>void <b><b>vst1_p8_x3</b></b> (poly8_t * ptr, poly8x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p8_x3" type="checkbox"><label for="vst1q_p8_x3"><div>void <b><b>vst1q_p8_x3</b></b> (poly8_t * ptr, poly8x16x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p16_x3" type="checkbox"><label for="vst1_p16_x3"><div>void <b><b>vst1_p16_x3</b></b> (poly16_t * ptr, poly16x4x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p16_x3" type="checkbox"><label for="vst1q_p16_x3"><div>void <b><b>vst1q_p16_x3</b></b> (poly16_t * ptr, poly16x8x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s64_x3" type="checkbox"><label for="vst1_s64_x3"><div>void <b><b>vst1_s64_x3</b></b> (int64_t * ptr, int64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u64_x3" type="checkbox"><label for="vst1_u64_x3"><div>void <b><b>vst1_u64_x3</b></b> (uint64_t * ptr, uint64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p64_x3" type="checkbox"><label for="vst1_p64_x3"><div>void <b><b>vst1_p64_x3</b></b> (poly64_t * ptr, poly64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s64_x3" type="checkbox"><label for="vst1q_s64_x3"><div>void <b><b>vst1q_s64_x3</b></b> (int64_t * ptr, int64x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u64_x3" type="checkbox"><label for="vst1q_u64_x3"><div>void <b><b>vst1q_u64_x3</b></b> (uint64_t * ptr, uint64x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p64_x3" type="checkbox"><label for="vst1q_p64_x3"><div>void <b><b>vst1q_p64_x3</b></b> (poly64_t * ptr, poly64x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f64_x3" type="checkbox"><label for="vst1_f64_x3"><div>void <b><b>vst1_f64_x3</b></b> (float64_t * ptr, float64x1x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f64_x3" type="checkbox"><label for="vst1q_f64_x3"><div>void <b><b>vst1q_f64_x3</b></b> (float64_t * ptr, float64x2x3_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s8_x4" type="checkbox"><label for="vst1_s8_x4"><div>void <b><b>vst1_s8_x4</b></b> (int8_t * ptr, int8x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s8_x4" type="checkbox"><label for="vst1q_s8_x4"><div>void <b><b>vst1q_s8_x4</b></b> (int8_t * ptr, int8x16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s16_x4" type="checkbox"><label for="vst1_s16_x4"><div>void <b><b>vst1_s16_x4</b></b> (int16_t * ptr, int16x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s16_x4" type="checkbox"><label for="vst1q_s16_x4"><div>void <b><b>vst1q_s16_x4</b></b> (int16_t * ptr, int16x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s32_x4" type="checkbox"><label for="vst1_s32_x4"><div>void <b><b>vst1_s32_x4</b></b> (int32_t * ptr, int32x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s32_x4" type="checkbox"><label for="vst1q_s32_x4"><div>void <b><b>vst1q_s32_x4</b></b> (int32_t * ptr, int32x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u8_x4" type="checkbox"><label for="vst1_u8_x4"><div>void <b><b>vst1_u8_x4</b></b> (uint8_t * ptr, uint8x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u8_x4" type="checkbox"><label for="vst1q_u8_x4"><div>void <b><b>vst1q_u8_x4</b></b> (uint8_t * ptr, uint8x16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u16_x4" type="checkbox"><label for="vst1_u16_x4"><div>void <b><b>vst1_u16_x4</b></b> (uint16_t * ptr, uint16x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u16_x4" type="checkbox"><label for="vst1q_u16_x4"><div>void <b><b>vst1q_u16_x4</b></b> (uint16_t * ptr, uint16x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u32_x4" type="checkbox"><label for="vst1_u32_x4"><div>void <b><b>vst1_u32_x4</b></b> (uint32_t * ptr, uint32x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u32_x4" type="checkbox"><label for="vst1q_u32_x4"><div>void <b><b>vst1q_u32_x4</b></b> (uint32_t * ptr, uint32x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f16_x4" type="checkbox"><label for="vst1_f16_x4"><div>void <b><b>vst1_f16_x4</b></b> (float16_t * ptr, float16x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f16_x4" type="checkbox"><label for="vst1q_f16_x4"><div>void <b><b>vst1q_f16_x4</b></b> (float16_t * ptr, float16x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f32_x4" type="checkbox"><label for="vst1_f32_x4"><div>void <b><b>vst1_f32_x4</b></b> (float32_t * ptr, float32x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2S <br />
+ val.val[2] &rarr; Vt3.2S <br />
+ val.val[1] &rarr; Vt2.2S <br />
+ val.val[0] &rarr; Vt.2S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f32_x4" type="checkbox"><label for="vst1q_f32_x4"><div>void <b><b>vst1q_f32_x4</b></b> (float32_t * ptr, float32x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4S <br />
+ val.val[2] &rarr; Vt3.4S <br />
+ val.val[1] &rarr; Vt2.4S <br />
+ val.val[0] &rarr; Vt.4S </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p8_x4" type="checkbox"><label for="vst1_p8_x4"><div>void <b><b>vst1_p8_x4</b></b> (poly8_t * ptr, poly8x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8B <br />
+ val.val[2] &rarr; Vt3.8B <br />
+ val.val[1] &rarr; Vt2.8B <br />
+ val.val[0] &rarr; Vt.8B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p8_x4" type="checkbox"><label for="vst1q_p8_x4"><div>void <b><b>vst1q_p8_x4</b></b> (poly8_t * ptr, poly8x16x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.16B <br />
+ val.val[2] &rarr; Vt3.16B <br />
+ val.val[1] &rarr; Vt2.16B <br />
+ val.val[0] &rarr; Vt.16B </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p16_x4" type="checkbox"><label for="vst1_p16_x4"><div>void <b><b>vst1_p16_x4</b></b> (poly16_t * ptr, poly16x4x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.4H <br />
+ val.val[2] &rarr; Vt3.4H <br />
+ val.val[1] &rarr; Vt2.4H <br />
+ val.val[0] &rarr; Vt.4H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p16_x4" type="checkbox"><label for="vst1q_p16_x4"><div>void <b><b>vst1q_p16_x4</b></b> (poly16_t * ptr, poly16x8x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.8H <br />
+ val.val[2] &rarr; Vt3.8H <br />
+ val.val[1] &rarr; Vt2.8H <br />
+ val.val[0] &rarr; Vt.8H </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_s64_x4" type="checkbox"><label for="vst1_s64_x4"><div>void <b><b>vst1_s64_x4</b></b> (int64_t * ptr, int64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_u64_x4" type="checkbox"><label for="vst1_u64_x4"><div>void <b><b>vst1_u64_x4</b></b> (uint64_t * ptr, uint64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_p64_x4" type="checkbox"><label for="vst1_p64_x4"><div>void <b><b>vst1_p64_x4</b></b> (poly64_t * ptr, poly64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_s64_x4" type="checkbox"><label for="vst1q_s64_x4"><div>void <b><b>vst1q_s64_x4</b></b> (int64_t * ptr, int64x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_u64_x4" type="checkbox"><label for="vst1q_u64_x4"><div>void <b><b>vst1q_u64_x4</b></b> (uint64_t * ptr, uint64x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_p64_x4" type="checkbox"><label for="vst1q_p64_x4"><div>void <b><b>vst1q_p64_x4</b></b> (poly64_t * ptr, poly64x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vst1_f64_x4" type="checkbox"><label for="vst1_f64_x4"><div>void <b><b>vst1_f64_x4</b></b> (float64_t * ptr, float64x1x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.1D <br />
+ val.val[2] &rarr; Vt3.1D <br />
+ val.val[1] &rarr; Vt2.1D <br />
+ val.val[0] &rarr; Vt.1D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vst1q_f64_x4" type="checkbox"><label for="vst1q_f64_x4"><div>void <b><b>vst1q_f64_x4</b></b> (float64_t * ptr, float64x2x4_t val)<span class="right">Store a single-element structure from one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/st1-single-structure-store-a-single-element-structure-from-one-lane-of-one-register">ST1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val.val[3] &rarr; Vt4.2D <br />
+ val.val[2] &rarr; Vt3.2D <br />
+ val.val[1] &rarr; Vt2.2D <br />
+ val.val[0] &rarr; Vt.2D </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s8_x2" type="checkbox"><label for="vld1_s8_x2"><div>int8x8x2_t <b><b>vld1_s8_x2</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s8_x2" type="checkbox"><label for="vld1q_s8_x2"><div>int8x16x2_t <b><b>vld1q_s8_x2</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s16_x2" type="checkbox"><label for="vld1_s16_x2"><div>int16x4x2_t <b><b>vld1_s16_x2</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s16_x2" type="checkbox"><label for="vld1q_s16_x2"><div>int16x8x2_t <b><b>vld1q_s16_x2</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s32_x2" type="checkbox"><label for="vld1_s32_x2"><div>int32x2x2_t <b><b>vld1_s32_x2</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s32_x2" type="checkbox"><label for="vld1q_s32_x2"><div>int32x4x2_t <b><b>vld1q_s32_x2</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u8_x2" type="checkbox"><label for="vld1_u8_x2"><div>uint8x8x2_t <b><b>vld1_u8_x2</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u8_x2" type="checkbox"><label for="vld1q_u8_x2"><div>uint8x16x2_t <b><b>vld1q_u8_x2</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u16_x2" type="checkbox"><label for="vld1_u16_x2"><div>uint16x4x2_t <b><b>vld1_u16_x2</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u16_x2" type="checkbox"><label for="vld1q_u16_x2"><div>uint16x8x2_t <b><b>vld1q_u16_x2</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u32_x2" type="checkbox"><label for="vld1_u32_x2"><div>uint32x2x2_t <b><b>vld1_u32_x2</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u32_x2" type="checkbox"><label for="vld1q_u32_x2"><div>uint32x4x2_t <b><b>vld1q_u32_x2</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f16_x2" type="checkbox"><label for="vld1_f16_x2"><div>float16x4x2_t <b><b>vld1_f16_x2</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f16_x2" type="checkbox"><label for="vld1q_f16_x2"><div>float16x8x2_t <b><b>vld1q_f16_x2</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f32_x2" type="checkbox"><label for="vld1_f32_x2"><div>float32x2x2_t <b><b>vld1_f32_x2</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt2.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f32_x2" type="checkbox"><label for="vld1q_f32_x2"><div>float32x4x2_t <b><b>vld1q_f32_x2</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt2.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p8_x2" type="checkbox"><label for="vld1_p8_x2"><div>poly8x8x2_t <b><b>vld1_p8_x2</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt2.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p8_x2" type="checkbox"><label for="vld1q_p8_x2"><div>poly8x16x2_t <b><b>vld1q_p8_x2</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt2.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p16_x2" type="checkbox"><label for="vld1_p16_x2"><div>poly16x4x2_t <b><b>vld1_p16_x2</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt2.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p16_x2" type="checkbox"><label for="vld1q_p16_x2"><div>poly16x8x2_t <b><b>vld1q_p16_x2</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt2.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s64_x2" type="checkbox"><label for="vld1_s64_x2"><div>int64x1x2_t <b><b>vld1_s64_x2</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u64_x2" type="checkbox"><label for="vld1_u64_x2"><div>uint64x1x2_t <b><b>vld1_u64_x2</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p64_x2" type="checkbox"><label for="vld1_p64_x2"><div>poly64x1x2_t <b><b>vld1_p64_x2</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s64_x2" type="checkbox"><label for="vld1q_s64_x2"><div>int64x2x2_t <b><b>vld1q_s64_x2</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u64_x2" type="checkbox"><label for="vld1q_u64_x2"><div>uint64x2x2_t <b><b>vld1q_u64_x2</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p64_x2" type="checkbox"><label for="vld1q_p64_x2"><div>poly64x2x2_t <b><b>vld1q_p64_x2</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f64_x2" type="checkbox"><label for="vld1_f64_x2"><div>float64x1x2_t <b><b>vld1_f64_x2</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt2.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f64_x2" type="checkbox"><label for="vld1q_f64_x2"><div>float64x2x2_t <b><b>vld1q_f64_x2</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt2.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s8_x3" type="checkbox"><label for="vld1_s8_x3"><div>int8x8x3_t <b><b>vld1_s8_x3</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s8_x3" type="checkbox"><label for="vld1q_s8_x3"><div>int8x16x3_t <b><b>vld1q_s8_x3</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s16_x3" type="checkbox"><label for="vld1_s16_x3"><div>int16x4x3_t <b><b>vld1_s16_x3</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s16_x3" type="checkbox"><label for="vld1q_s16_x3"><div>int16x8x3_t <b><b>vld1q_s16_x3</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s32_x3" type="checkbox"><label for="vld1_s32_x3"><div>int32x2x3_t <b><b>vld1_s32_x3</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s32_x3" type="checkbox"><label for="vld1q_s32_x3"><div>int32x4x3_t <b><b>vld1q_s32_x3</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u8_x3" type="checkbox"><label for="vld1_u8_x3"><div>uint8x8x3_t <b><b>vld1_u8_x3</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u8_x3" type="checkbox"><label for="vld1q_u8_x3"><div>uint8x16x3_t <b><b>vld1q_u8_x3</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u16_x3" type="checkbox"><label for="vld1_u16_x3"><div>uint16x4x3_t <b><b>vld1_u16_x3</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u16_x3" type="checkbox"><label for="vld1q_u16_x3"><div>uint16x8x3_t <b><b>vld1q_u16_x3</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u32_x3" type="checkbox"><label for="vld1_u32_x3"><div>uint32x2x3_t <b><b>vld1_u32_x3</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u32_x3" type="checkbox"><label for="vld1q_u32_x3"><div>uint32x4x3_t <b><b>vld1q_u32_x3</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f16_x3" type="checkbox"><label for="vld1_f16_x3"><div>float16x4x3_t <b><b>vld1_f16_x3</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f16_x3" type="checkbox"><label for="vld1q_f16_x3"><div>float16x8x3_t <b><b>vld1q_f16_x3</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f32_x3" type="checkbox"><label for="vld1_f32_x3"><div>float32x2x3_t <b><b>vld1_f32_x3</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt3.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f32_x3" type="checkbox"><label for="vld1q_f32_x3"><div>float32x4x3_t <b><b>vld1q_f32_x3</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt3.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p8_x3" type="checkbox"><label for="vld1_p8_x3"><div>poly8x8x3_t <b><b>vld1_p8_x3</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt3.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p8_x3" type="checkbox"><label for="vld1q_p8_x3"><div>poly8x16x3_t <b><b>vld1q_p8_x3</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt3.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p16_x3" type="checkbox"><label for="vld1_p16_x3"><div>poly16x4x3_t <b><b>vld1_p16_x3</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt3.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p16_x3" type="checkbox"><label for="vld1q_p16_x3"><div>poly16x8x3_t <b><b>vld1q_p16_x3</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt3.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s64_x3" type="checkbox"><label for="vld1_s64_x3"><div>int64x1x3_t <b><b>vld1_s64_x3</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u64_x3" type="checkbox"><label for="vld1_u64_x3"><div>uint64x1x3_t <b><b>vld1_u64_x3</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p64_x3" type="checkbox"><label for="vld1_p64_x3"><div>poly64x1x3_t <b><b>vld1_p64_x3</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s64_x3" type="checkbox"><label for="vld1q_s64_x3"><div>int64x2x3_t <b><b>vld1q_s64_x3</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u64_x3" type="checkbox"><label for="vld1q_u64_x3"><div>uint64x2x3_t <b><b>vld1q_u64_x3</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p64_x3" type="checkbox"><label for="vld1q_p64_x3"><div>poly64x2x3_t <b><b>vld1q_p64_x3</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f64_x3" type="checkbox"><label for="vld1_f64_x3"><div>float64x1x3_t <b><b>vld1_f64_x3</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt3.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f64_x3" type="checkbox"><label for="vld1q_f64_x3"><div>float64x2x3_t <b><b>vld1q_f64_x3</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt3.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s8_x4" type="checkbox"><label for="vld1_s8_x4"><div>int8x8x4_t <b><b>vld1_s8_x4</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s8_x4" type="checkbox"><label for="vld1q_s8_x4"><div>int8x16x4_t <b><b>vld1q_s8_x4</b></b> (int8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s16_x4" type="checkbox"><label for="vld1_s16_x4"><div>int16x4x4_t <b><b>vld1_s16_x4</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s16_x4" type="checkbox"><label for="vld1q_s16_x4"><div>int16x8x4_t <b><b>vld1q_s16_x4</b></b> (int16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s32_x4" type="checkbox"><label for="vld1_s32_x4"><div>int32x2x4_t <b><b>vld1_s32_x4</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s32_x4" type="checkbox"><label for="vld1q_s32_x4"><div>int32x4x4_t <b><b>vld1q_s32_x4</b></b> (int32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u8_x4" type="checkbox"><label for="vld1_u8_x4"><div>uint8x8x4_t <b><b>vld1_u8_x4</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u8_x4" type="checkbox"><label for="vld1q_u8_x4"><div>uint8x16x4_t <b><b>vld1q_u8_x4</b></b> (uint8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u16_x4" type="checkbox"><label for="vld1_u16_x4"><div>uint16x4x4_t <b><b>vld1_u16_x4</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u16_x4" type="checkbox"><label for="vld1q_u16_x4"><div>uint16x8x4_t <b><b>vld1q_u16_x4</b></b> (uint16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u32_x4" type="checkbox"><label for="vld1_u32_x4"><div>uint32x2x4_t <b><b>vld1_u32_x4</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u32_x4" type="checkbox"><label for="vld1q_u32_x4"><div>uint32x4x4_t <b><b>vld1q_u32_x4</b></b> (uint32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f16_x4" type="checkbox"><label for="vld1_f16_x4"><div>float16x4x4_t <b><b>vld1_f16_x4</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f16_x4" type="checkbox"><label for="vld1q_f16_x4"><div>float16x8x4_t <b><b>vld1q_f16_x4</b></b> (float16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f32_x4" type="checkbox"><label for="vld1_f32_x4"><div>float32x2x4_t <b><b>vld1_f32_x4</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2S - Vt4.2S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2S &rarr; result.val[3]
+ Vt3.2S &rarr; result.val[2]
+ Vt2.2S &rarr; result.val[1]
+ Vt.2S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f32_x4" type="checkbox"><label for="vld1q_f32_x4"><div>float32x4x4_t <b><b>vld1q_f32_x4</b></b> (float32_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4S - Vt4.4S},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4S &rarr; result.val[3]
+ Vt3.4S &rarr; result.val[2]
+ Vt2.4S &rarr; result.val[1]
+ Vt.4S &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p8_x4" type="checkbox"><label for="vld1_p8_x4"><div>poly8x8x4_t <b><b>vld1_p8_x4</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8B - Vt4.8B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8B &rarr; result.val[3]
+ Vt3.8B &rarr; result.val[2]
+ Vt2.8B &rarr; result.val[1]
+ Vt.8B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p8_x4" type="checkbox"><label for="vld1q_p8_x4"><div>poly8x16x4_t <b><b>vld1q_p8_x4</b></b> (poly8_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.16B - Vt4.16B},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.16B &rarr; result.val[3]
+ Vt3.16B &rarr; result.val[2]
+ Vt2.16B &rarr; result.val[1]
+ Vt.16B &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p16_x4" type="checkbox"><label for="vld1_p16_x4"><div>poly16x4x4_t <b><b>vld1_p16_x4</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.4H - Vt4.4H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.4H &rarr; result.val[3]
+ Vt3.4H &rarr; result.val[2]
+ Vt2.4H &rarr; result.val[1]
+ Vt.4H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p16_x4" type="checkbox"><label for="vld1q_p16_x4"><div>poly16x8x4_t <b><b>vld1q_p16_x4</b></b> (poly16_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.8H - Vt4.8H},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.8H &rarr; result.val[3]
+ Vt3.8H &rarr; result.val[2]
+ Vt2.8H &rarr; result.val[1]
+ Vt.8H &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_s64_x4" type="checkbox"><label for="vld1_s64_x4"><div>int64x1x4_t <b><b>vld1_s64_x4</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_u64_x4" type="checkbox"><label for="vld1_u64_x4"><div>uint64x1x4_t <b><b>vld1_u64_x4</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_p64_x4" type="checkbox"><label for="vld1_p64_x4"><div>poly64x1x4_t <b><b>vld1_p64_x4</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_s64_x4" type="checkbox"><label for="vld1q_s64_x4"><div>int64x2x4_t <b><b>vld1q_s64_x4</b></b> (int64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_u64_x4" type="checkbox"><label for="vld1q_u64_x4"><div>uint64x2x4_t <b><b>vld1q_u64_x4</b></b> (uint64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_p64_x4" type="checkbox"><label for="vld1q_p64_x4"><div>poly64x2x4_t <b><b>vld1q_p64_x4</b></b> (poly64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vld1_f64_x4" type="checkbox"><label for="vld1_f64_x4"><div>float64x1x4_t <b><b>vld1_f64_x4</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.1D - Vt4.1D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.1D &rarr; result.val[3]
+ Vt3.1D &rarr; result.val[2]
+ Vt2.1D &rarr; result.val[1]
+ Vt.1D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vld1q_f64_x4" type="checkbox"><label for="vld1q_f64_x4"><div>float64x2x4_t <b><b>vld1q_f64_x4</b></b> (float64_t const * ptr)<span class="right">Load one single-element structure to one lane of one register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&amp;FP register without affecting the other bits of the register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ld1-single-structure-load-one-single-element-structure-to-one-lane-of-one-register">LD1</a> {Vt.2D - Vt4.2D},[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Vt4.2D &rarr; result.val[3]
+ Vt3.2D &rarr; result.val[2]
+ Vt2.2D &rarr; result.val[1]
+ Vt.2D &rarr; result.val[0]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     SetNotTagCheckedInstruction(!wback &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ 
+ bits(64) address;
+ bits(64) offs;
+ bits(128) rval;
+ bits(esize) element;
+ constant integer ebytes = esize DIV 8;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ if replicate then
+     // load and replicate to all elements
+     for s = 0 to selem-1
+         element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         // replicate to fill 128- or 64-bit register
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ else
+     // load/store one element per register
+     for s = 0 to selem-1
+         rval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         if memop == <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
+             // insert into one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = rval;
+         else // memop == MemOp_STORE
+             // extract from one lane of 128-bit register
+             <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address+offs, ebytes, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
+         offs = offs + ebytes;
+         t = (t + 1) MOD 32;
+ 
+ if wback then
+     if m != 31 then
+         offs = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];
+     if n == 31 then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(width) value">SP</a>[] = address + offs;
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[n] = address + offs;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_s8" type="checkbox"><label for="vpadd_s8"><div>int8x8_t <b><b>vpadd_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_s16" type="checkbox"><label for="vpadd_s16"><div>int16x4_t <b><b>vpadd_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_s32" type="checkbox"><label for="vpadd_s32"><div>int32x2_t <b><b>vpadd_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_u8" type="checkbox"><label for="vpadd_u8"><div>uint8x8_t <b><b>vpadd_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_u16" type="checkbox"><label for="vpadd_u16"><div>uint16x4_t <b><b>vpadd_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_u32" type="checkbox"><label for="vpadd_u32"><div>uint32x2_t <b><b>vpadd_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadd_f32" type="checkbox"><label for="vpadd_f32"><div>float32x2_t <b><b>vpadd_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_s8" type="checkbox"><label for="vpaddq_s8"><div>int8x16_t <b><b>vpaddq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_s16" type="checkbox"><label for="vpaddq_s16"><div>int16x8_t <b><b>vpaddq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_s32" type="checkbox"><label for="vpaddq_s32"><div>int32x4_t <b><b>vpaddq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_s64" type="checkbox"><label for="vpaddq_s64"><div>int64x2_t <b><b>vpaddq_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_u8" type="checkbox"><label for="vpaddq_u8"><div>uint8x16_t <b><b>vpaddq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_u16" type="checkbox"><label for="vpaddq_u16"><div>uint16x8_t <b><b>vpaddq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_u32" type="checkbox"><label for="vpaddq_u32"><div>uint32x4_t <b><b>vpaddq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_u64" type="checkbox"><label for="vpaddq_u64"><div>uint64x2_t <b><b>vpaddq_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_f32" type="checkbox"><label for="vpaddq_f32"><div>float32x4_t <b><b>vpaddq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddq_f64" type="checkbox"><label for="vpaddq_f64"><div>float64x2_t <b><b>vpaddq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddl_s8" type="checkbox"><label for="vpaddl_s8"><div>int16x4_t <b><b>vpaddl_s8</b></b> (int8x8_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.4H,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddlq_s8" type="checkbox"><label for="vpaddlq_s8"><div>int16x8_t <b><b>vpaddlq_s8</b></b> (int8x16_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.8H,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddl_s16" type="checkbox"><label for="vpaddl_s16"><div>int32x2_t <b><b>vpaddl_s16</b></b> (int16x4_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.2S,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddlq_s16" type="checkbox"><label for="vpaddlq_s16"><div>int32x4_t <b><b>vpaddlq_s16</b></b> (int16x8_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.4S,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddl_s32" type="checkbox"><label for="vpaddl_s32"><div>int64x1_t <b><b>vpaddl_s32</b></b> (int32x2_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.1D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddlq_s32" type="checkbox"><label for="vpaddlq_s32"><div>int64x2_t <b><b>vpaddlq_s32</b></b> (int32x4_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.2D,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddl_u8" type="checkbox"><label for="vpaddl_u8"><div>uint16x4_t <b><b>vpaddl_u8</b></b> (uint8x8_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.4H,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddlq_u8" type="checkbox"><label for="vpaddlq_u8"><div>uint16x8_t <b><b>vpaddlq_u8</b></b> (uint8x16_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.8H,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddl_u16" type="checkbox"><label for="vpaddl_u16"><div>uint32x2_t <b><b>vpaddl_u16</b></b> (uint16x4_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.2S,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddlq_u16" type="checkbox"><label for="vpaddlq_u16"><div>uint32x4_t <b><b>vpaddlq_u16</b></b> (uint16x8_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.4S,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddl_u32" type="checkbox"><label for="vpaddl_u32"><div>uint64x1_t <b><b>vpaddl_u32</b></b> (uint32x2_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.1D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpaddlq_u32" type="checkbox"><label for="vpaddlq_u32"><div>uint64x2_t <b><b>vpaddlq_u32</b></b> (uint32x4_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.2D,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadal_s8" type="checkbox"><label for="vpadal_s8"><div>int16x4_t <b><b>vpadal_s8</b></b> (int16x4_t a, int8x8_t b)<span class="right">Signed add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register and accumulates the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sadalp-signed-add-and-accumulate-long-pairwise">SADALP</a> Vd.4H,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadalq_s8" type="checkbox"><label for="vpadalq_s8"><div>int16x8_t <b><b>vpadalq_s8</b></b> (int16x8_t a, int8x16_t b)<span class="right">Signed add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register and accumulates the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sadalp-signed-add-and-accumulate-long-pairwise">SADALP</a> Vd.8H,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadal_s16" type="checkbox"><label for="vpadal_s16"><div>int32x2_t <b><b>vpadal_s16</b></b> (int32x2_t a, int16x4_t b)<span class="right">Signed add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register and accumulates the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sadalp-signed-add-and-accumulate-long-pairwise">SADALP</a> Vd.2S,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadalq_s16" type="checkbox"><label for="vpadalq_s16"><div>int32x4_t <b><b>vpadalq_s16</b></b> (int32x4_t a, int16x8_t b)<span class="right">Signed add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register and accumulates the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sadalp-signed-add-and-accumulate-long-pairwise">SADALP</a> Vd.4S,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadal_s32" type="checkbox"><label for="vpadal_s32"><div>int64x1_t <b><b>vpadal_s32</b></b> (int64x1_t a, int32x2_t b)<span class="right">Signed add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register and accumulates the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sadalp-signed-add-and-accumulate-long-pairwise">SADALP</a> Vd.1D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D <br />
+ b &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadalq_s32" type="checkbox"><label for="vpadalq_s32"><div>int64x2_t <b><b>vpadalq_s32</b></b> (int64x2_t a, int32x4_t b)<span class="right">Signed add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register and accumulates the results into the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sadalp-signed-add-and-accumulate-long-pairwise">SADALP</a> Vd.2D,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadal_u8" type="checkbox"><label for="vpadal_u8"><div>uint16x4_t <b><b>vpadal_u8</b></b> (uint16x4_t a, uint8x8_t b)<span class="right">Unsigned add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uadalp-unsigned-add-and-accumulate-long-pairwise">UADALP</a> Vd.4H,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H <br />
+ b &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadalq_u8" type="checkbox"><label for="vpadalq_u8"><div>uint16x8_t <b><b>vpadalq_u8</b></b> (uint16x8_t a, uint8x16_t b)<span class="right">Unsigned add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uadalp-unsigned-add-and-accumulate-long-pairwise">UADALP</a> Vd.8H,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H <br />
+ b &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadal_u16" type="checkbox"><label for="vpadal_u16"><div>uint32x2_t <b><b>vpadal_u16</b></b> (uint32x2_t a, uint16x4_t b)<span class="right">Unsigned add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uadalp-unsigned-add-and-accumulate-long-pairwise">UADALP</a> Vd.2S,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadalq_u16" type="checkbox"><label for="vpadalq_u16"><div>uint32x4_t <b><b>vpadalq_u16</b></b> (uint32x4_t a, uint16x8_t b)<span class="right">Unsigned add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uadalp-unsigned-add-and-accumulate-long-pairwise">UADALP</a> Vd.4S,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadal_u32" type="checkbox"><label for="vpadal_u32"><div>uint64x1_t <b><b>vpadal_u32</b></b> (uint64x1_t a, uint32x2_t b)<span class="right">Unsigned add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uadalp-unsigned-add-and-accumulate-long-pairwise">UADALP</a> Vd.1D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D <br />
+ b &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpadalq_u32" type="checkbox"><label for="vpadalq_u32"><div>uint64x2_t <b><b>vpadalq_u32</b></b> (uint64x2_t a, uint32x4_t b)<span class="right">Unsigned add and accumulate long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register and accumulates the results with the vector elements of the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uadalp-unsigned-add-and-accumulate-long-pairwise">UADALP</a> Vd.2D,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_s8" type="checkbox"><label for="vpmax_s8"><div>int8x8_t <b><b>vpmax_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_s16" type="checkbox"><label for="vpmax_s16"><div>int16x4_t <b><b>vpmax_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_s32" type="checkbox"><label for="vpmax_s32"><div>int32x2_t <b><b>vpmax_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_u8" type="checkbox"><label for="vpmax_u8"><div>uint8x8_t <b><b>vpmax_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_u16" type="checkbox"><label for="vpmax_u16"><div>uint16x4_t <b><b>vpmax_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_u32" type="checkbox"><label for="vpmax_u32"><div>uint32x2_t <b><b>vpmax_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmax_f32" type="checkbox"><label for="vpmax_f32"><div>float32x2_t <b><b>vpmax_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_s8" type="checkbox"><label for="vpmaxq_s8"><div>int8x16_t <b><b>vpmaxq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_s16" type="checkbox"><label for="vpmaxq_s16"><div>int16x8_t <b><b>vpmaxq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_s32" type="checkbox"><label for="vpmaxq_s32"><div>int32x4_t <b><b>vpmaxq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_u8" type="checkbox"><label for="vpmaxq_u8"><div>uint8x16_t <b><b>vpmaxq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_u16" type="checkbox"><label for="vpmaxq_u16"><div>uint16x8_t <b><b>vpmaxq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_u32" type="checkbox"><label for="vpmaxq_u32"><div>uint32x4_t <b><b>vpmaxq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_f32" type="checkbox"><label for="vpmaxq_f32"><div>float32x4_t <b><b>vpmaxq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxq_f64" type="checkbox"><label for="vpmaxq_f64"><div>float64x2_t <b><b>vpmaxq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_s8" type="checkbox"><label for="vpmin_s8"><div>int8x8_t <b><b>vpmin_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_s16" type="checkbox"><label for="vpmin_s16"><div>int16x4_t <b><b>vpmin_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_s32" type="checkbox"><label for="vpmin_s32"><div>int32x2_t <b><b>vpmin_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_u8" type="checkbox"><label for="vpmin_u8"><div>uint8x8_t <b><b>vpmin_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_u16" type="checkbox"><label for="vpmin_u16"><div>uint16x4_t <b><b>vpmin_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_u32" type="checkbox"><label for="vpmin_u32"><div>uint32x2_t <b><b>vpmin_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpmin_f32" type="checkbox"><label for="vpmin_f32"><div>float32x2_t <b><b>vpmin_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_s8" type="checkbox"><label for="vpminq_s8"><div>int8x16_t <b><b>vpminq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_s16" type="checkbox"><label for="vpminq_s16"><div>int16x8_t <b><b>vpminq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_s32" type="checkbox"><label for="vpminq_s32"><div>int32x4_t <b><b>vpminq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_u8" type="checkbox"><label for="vpminq_u8"><div>uint8x16_t <b><b>vpminq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_u16" type="checkbox"><label for="vpminq_u16"><div>uint16x8_t <b><b>vpminq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_u32" type="checkbox"><label for="vpminq_u32"><div>uint32x4_t <b><b>vpminq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_f32" type="checkbox"><label for="vpminq_f32"><div>float32x4_t <b><b>vpminq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminq_f64" type="checkbox"><label for="vpminq_f64"><div>float64x2_t <b><b>vpminq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxnm_f32" type="checkbox"><label for="vpmaxnm_f32"><div>float32x2_t <b><b>vpmaxnm_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxnmq_f32" type="checkbox"><label for="vpmaxnmq_f32"><div>float32x4_t <b><b>vpmaxnmq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxnmq_f64" type="checkbox"><label for="vpmaxnmq_f64"><div>float64x2_t <b><b>vpmaxnmq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminnm_f32" type="checkbox"><label for="vpminnm_f32"><div>float32x2_t <b><b>vpminnm_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminnmq_f32" type="checkbox"><label for="vpminnmq_f32"><div>float32x4_t <b><b>vpminnmq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminnmq_f64" type="checkbox"><label for="vpminnmq_f64"><div>float64x2_t <b><b>vpminnmq_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddd_s64" type="checkbox"><label for="vpaddd_s64"><div>int64_t <b><b>vpaddd_s64</b></b> (int64x2_t a)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddd_u64" type="checkbox"><label for="vpaddd_u64"><div>uint64_t <b><b>vpaddd_u64</b></b> (uint64x2_t a)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpadds_f32" type="checkbox"><label for="vpadds_f32"><div>float32_t <b><b>vpadds_f32</b></b> (float32x2_t a)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpaddd_f64" type="checkbox"><label for="vpaddd_f64"><div>float64_t <b><b>vpaddd_f64</b></b> (float64x2_t a)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxs_f32" type="checkbox"><label for="vpmaxs_f32"><div>float32_t <b><b>vpmaxs_f32</b></b> (float32x2_t a)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxqd_f64" type="checkbox"><label for="vpmaxqd_f64"><div>float64_t <b><b>vpmaxqd_f64</b></b> (float64x2_t a)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmins_f32" type="checkbox"><label for="vpmins_f32"><div>float32_t <b><b>vpmins_f32</b></b> (float32x2_t a)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminqd_f64" type="checkbox"><label for="vpminqd_f64"><div>float64_t <b><b>vpminqd_f64</b></b> (float64x2_t a)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxnms_f32" type="checkbox"><label for="vpmaxnms_f32"><div>float32_t <b><b>vpmaxnms_f32</b></b> (float32x2_t a)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpmaxnmqd_f64" type="checkbox"><label for="vpmaxnmqd_f64"><div>float64_t <b><b>vpmaxnmqd_f64</b></b> (float64x2_t a)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminnms_f32" type="checkbox"><label for="vpminnms_f32"><div>float32_t <b><b>vpminnms_f32</b></b> (float32x2_t a)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vpminnmqd_f64" type="checkbox"><label for="vpminnmqd_f64"><div>float64_t <b><b>vpminnmqd_f64</b></b> (float64x2_t a)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_s8" type="checkbox"><label for="vaddv_s8"><div>int8_t <b><b>vaddv_s8</b></b> (int8x8_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Bd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_s8" type="checkbox"><label for="vaddvq_s8"><div>int8_t <b><b>vaddvq_s8</b></b> (int8x16_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Bd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_s16" type="checkbox"><label for="vaddv_s16"><div>int16_t <b><b>vaddv_s16</b></b> (int16x4_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Hd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_s16" type="checkbox"><label for="vaddvq_s16"><div>int16_t <b><b>vaddvq_s16</b></b> (int16x8_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Hd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_s32" type="checkbox"><label for="vaddv_s32"><div>int32_t <b><b>vaddv_s32</b></b> (int32x2_t a)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a>  Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ a &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.S[0] &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_s32" type="checkbox"><label for="vaddvq_s32"><div>int32_t <b><b>vaddvq_s32</b></b> (int32x4_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_s64" type="checkbox"><label for="vaddvq_s64"><div>int64_t <b><b>vaddvq_s64</b></b> (int64x2_t a)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_u8" type="checkbox"><label for="vaddv_u8"><div>uint8_t <b><b>vaddv_u8</b></b> (uint8x8_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Bd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_u8" type="checkbox"><label for="vaddvq_u8"><div>uint8_t <b><b>vaddvq_u8</b></b> (uint8x16_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Bd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_u16" type="checkbox"><label for="vaddv_u16"><div>uint16_t <b><b>vaddv_u16</b></b> (uint16x4_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Hd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_u16" type="checkbox"><label for="vaddvq_u16"><div>uint16_t <b><b>vaddvq_u16</b></b> (uint16x8_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Hd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_u32" type="checkbox"><label for="vaddv_u32"><div>uint32_t <b><b>vaddv_u32</b></b> (uint32x2_t a)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a>  Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ a &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.S[0] &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_u32" type="checkbox"><label for="vaddvq_u32"><div>uint32_t <b><b>vaddvq_u32</b></b> (uint32x4_t a)<span class="right">Add across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addv-add-across-vector">ADDV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_ADD" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_u64" type="checkbox"><label for="vaddvq_u64"><div>uint64_t <b><b>vaddvq_u64</b></b> (uint64x2_t a)<span class="right">Add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/addp-vector-add-pairwise-vector">ADDP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddv_f32" type="checkbox"><label for="vaddv_f32"><div>float32_t <b><b>vaddv_f32</b></b> (float32x2_t a)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_f32" type="checkbox"><label for="vaddvq_f32"><div>float32_t <b><b>vaddvq_f32</b></b> (float32x4_t a)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Vt.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Sd,Vt.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ a &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddvq_f64" type="checkbox"><label for="vaddvq_f64"><div>float64_t <b><b>vaddvq_f64</b></b> (float64x2_t a)<span class="right">Floating-point add pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/faddp-vector-floating-point-add-pairwise-vector">FADDP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPAdd.3" title="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlv_s8" type="checkbox"><label for="vaddlv_s8"><div>int16_t <b><b>vaddlv_s8</b></b> (int8x8_t a)<span class="right">Signed add long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlv-signed-add-long-across-vector">SADDLV</a> Hd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlvq_s8" type="checkbox"><label for="vaddlvq_s8"><div>int16_t <b><b>vaddlvq_s8</b></b> (int8x16_t a)<span class="right">Signed add long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlv-signed-add-long-across-vector">SADDLV</a> Hd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlv_s16" type="checkbox"><label for="vaddlv_s16"><div>int32_t <b><b>vaddlv_s16</b></b> (int16x4_t a)<span class="right">Signed add long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlv-signed-add-long-across-vector">SADDLV</a> Sd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlvq_s16" type="checkbox"><label for="vaddlvq_s16"><div>int32_t <b><b>vaddlvq_s16</b></b> (int16x8_t a)<span class="right">Signed add long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlv-signed-add-long-across-vector">SADDLV</a> Sd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlv_s32" type="checkbox"><label for="vaddlv_s32"><div>int64_t <b><b>vaddlv_s32</b></b> (int32x2_t a)<span class="right">Signed add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlp-signed-add-long-pairwise">SADDLP</a> Vd.1D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlvq_s32" type="checkbox"><label for="vaddlvq_s32"><div>int64_t <b><b>vaddlvq_s32</b></b> (int32x4_t a)<span class="right">Signed add long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/saddlv-signed-add-long-across-vector">SADDLV</a> Dd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlv_u8" type="checkbox"><label for="vaddlv_u8"><div>uint16_t <b><b>vaddlv_u8</b></b> (uint8x8_t a)<span class="right">Unsigned sum long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlv-unsigned-sum-long-across-vector">UADDLV</a> Hd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlvq_u8" type="checkbox"><label for="vaddlvq_u8"><div>uint16_t <b><b>vaddlvq_u8</b></b> (uint8x16_t a)<span class="right">Unsigned sum long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlv-unsigned-sum-long-across-vector">UADDLV</a> Hd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlv_u16" type="checkbox"><label for="vaddlv_u16"><div>uint32_t <b><b>vaddlv_u16</b></b> (uint16x4_t a)<span class="right">Unsigned sum long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlv-unsigned-sum-long-across-vector">UADDLV</a> Sd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlvq_u16" type="checkbox"><label for="vaddlvq_u16"><div>uint32_t <b><b>vaddlvq_u16</b></b> (uint16x8_t a)<span class="right">Unsigned sum long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlv-unsigned-sum-long-across-vector">UADDLV</a> Sd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlv_u32" type="checkbox"><label for="vaddlv_u32"><div>uint64_t <b><b>vaddlv_u32</b></b> (uint32x2_t a)<span class="right">Unsigned add long pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&amp;FP register, places the result into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlp-unsigned-add-long-pairwise">UADDLP</a> Vd.1D,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ 
+ bits(2*esize) sum;
+ integer op1;
+ integer op2;
+ 
+ result = if acc then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d] else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ for e = 0 to elements-1
+     op1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+0, esize], unsigned);
+     op2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e+1, esize], unsigned);
+     sum = (op1+op2)&lt;2*esize-1:0&gt;;
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + sum;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vaddlvq_u32" type="checkbox"><label for="vaddlvq_u32"><div>uint64_t <b><b>vaddlvq_u32</b></b> (uint32x4_t a)<span class="right">Unsigned sum long across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&amp;FP register together, and writes the scalar result to the destination SIMD&amp;FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uaddlv-unsigned-sum-long-across-vector">UADDLV</a> Dd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer sum;
+ 
+ sum = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     sum = sum + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = sum&lt;2*esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_s8" type="checkbox"><label for="vmaxv_s8"><div>int8_t <b><b>vmaxv_s8</b></b> (int8x8_t a)<span class="right">Signed maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxv-signed-maximum-across-vector">SMAXV</a> Bd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_s8" type="checkbox"><label for="vmaxvq_s8"><div>int8_t <b><b>vmaxvq_s8</b></b> (int8x16_t a)<span class="right">Signed maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxv-signed-maximum-across-vector">SMAXV</a> Bd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_s16" type="checkbox"><label for="vmaxv_s16"><div>int16_t <b><b>vmaxv_s16</b></b> (int16x4_t a)<span class="right">Signed maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxv-signed-maximum-across-vector">SMAXV</a> Hd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_s16" type="checkbox"><label for="vmaxvq_s16"><div>int16_t <b><b>vmaxvq_s16</b></b> (int16x8_t a)<span class="right">Signed maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxv-signed-maximum-across-vector">SMAXV</a> Hd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_s32" type="checkbox"><label for="vmaxv_s32"><div>int32_t <b><b>vmaxv_s32</b></b> (int32x2_t a)<span class="right">Signed maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxp-signed-maximum-pairwise">SMAXP</a>  Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ a &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.S[0] &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_s32" type="checkbox"><label for="vmaxvq_s32"><div>int32_t <b><b>vmaxvq_s32</b></b> (int32x4_t a)<span class="right">Signed maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smaxv-signed-maximum-across-vector">SMAXV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_u8" type="checkbox"><label for="vmaxv_u8"><div>uint8_t <b><b>vmaxv_u8</b></b> (uint8x8_t a)<span class="right">Unsigned maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxv-unsigned-maximum-across-vector">UMAXV</a> Bd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_u8" type="checkbox"><label for="vmaxvq_u8"><div>uint8_t <b><b>vmaxvq_u8</b></b> (uint8x16_t a)<span class="right">Unsigned maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxv-unsigned-maximum-across-vector">UMAXV</a> Bd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_u16" type="checkbox"><label for="vmaxv_u16"><div>uint16_t <b><b>vmaxv_u16</b></b> (uint16x4_t a)<span class="right">Unsigned maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxv-unsigned-maximum-across-vector">UMAXV</a> Hd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_u16" type="checkbox"><label for="vmaxvq_u16"><div>uint16_t <b><b>vmaxvq_u16</b></b> (uint16x8_t a)<span class="right">Unsigned maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxv-unsigned-maximum-across-vector">UMAXV</a> Hd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_u32" type="checkbox"><label for="vmaxv_u32"><div>uint32_t <b><b>vmaxv_u32</b></b> (uint32x2_t a)<span class="right">Unsigned maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxp-unsigned-maximum-pairwise">UMAXP</a>  Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ a &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.S[0] &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_u32" type="checkbox"><label for="vmaxvq_u32"><div>uint32_t <b><b>vmaxvq_u32</b></b> (uint32x4_t a)<span class="right">Unsigned maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umaxv-unsigned-maximum-across-vector">UMAXV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxv_f32" type="checkbox"><label for="vmaxv_f32"><div>float32_t <b><b>vmaxv_f32</b></b> (float32x2_t a)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_f32" type="checkbox"><label for="vmaxvq_f32"><div>float32_t <b><b>vmaxvq_f32</b></b> (float32x4_t a)<span class="right">Floating-point maximum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxv-floating-point-maximum-across-vector">FMAXV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_FMAX" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMAX</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxvq_f64" type="checkbox"><label for="vmaxvq_f64"><div>float64_t <b><b>vmaxvq_f64</b></b> (float64x2_t a)<span class="right">Floating-point maximum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxp-vector-floating-point-maximum-pairwise-vector">FMAXP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_s8" type="checkbox"><label for="vminv_s8"><div>int8_t <b><b>vminv_s8</b></b> (int8x8_t a)<span class="right">Signed minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminv-signed-minimum-across-vector">SMINV</a> Bd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_s8" type="checkbox"><label for="vminvq_s8"><div>int8_t <b><b>vminvq_s8</b></b> (int8x16_t a)<span class="right">Signed minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminv-signed-minimum-across-vector">SMINV</a> Bd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_s16" type="checkbox"><label for="vminv_s16"><div>int16_t <b><b>vminv_s16</b></b> (int16x4_t a)<span class="right">Signed minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminv-signed-minimum-across-vector">SMINV</a> Hd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_s16" type="checkbox"><label for="vminvq_s16"><div>int16_t <b><b>vminvq_s16</b></b> (int16x8_t a)<span class="right">Signed minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminv-signed-minimum-across-vector">SMINV</a> Hd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_s32" type="checkbox"><label for="vminv_s32"><div>int32_t <b><b>vminv_s32</b></b> (int32x2_t a)<span class="right">Signed minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminp-signed-minimum-pairwise">SMINP</a>  Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ a &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.S[0] &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_s32" type="checkbox"><label for="vminvq_s32"><div>int32_t <b><b>vminvq_s32</b></b> (int32x4_t a)<span class="right">Signed minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are signed integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sminv-signed-minimum-across-vector">SMINV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_u8" type="checkbox"><label for="vminv_u8"><div>uint8_t <b><b>vminv_u8</b></b> (uint8x8_t a)<span class="right">Unsigned minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminv-unsigned-minimum-across-vector">UMINV</a> Bd,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_u8" type="checkbox"><label for="vminvq_u8"><div>uint8_t <b><b>vminvq_u8</b></b> (uint8x16_t a)<span class="right">Unsigned minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminv-unsigned-minimum-across-vector">UMINV</a> Bd,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Bd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_u16" type="checkbox"><label for="vminv_u16"><div>uint16_t <b><b>vminv_u16</b></b> (uint16x4_t a)<span class="right">Unsigned minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminv-unsigned-minimum-across-vector">UMINV</a> Hd,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_u16" type="checkbox"><label for="vminvq_u16"><div>uint16_t <b><b>vminvq_u16</b></b> (uint16x8_t a)<span class="right">Unsigned minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminv-unsigned-minimum-across-vector">UMINV</a> Hd,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_u32" type="checkbox"><label for="vminv_u32"><div>uint32_t <b><b>vminv_u32</b></b> (uint32x2_t a)<span class="right">Unsigned minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminp-unsigned-minimum-pairwise">UMINP</a>  Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ a &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.S[0] &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ integer element1;
+ integer element2;
+ integer maxmin;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize], unsigned);
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize], unsigned);
+     maxmin = if minimum then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(element1, element2) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(element1, element2);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = maxmin&lt;esize-1:0&gt;;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_u32" type="checkbox"><label for="vminvq_u32"><div>uint32_t <b><b>vminvq_u32</b></b> (uint32x4_t a)<span class="right">Unsigned minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are unsigned integer values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uminv-unsigned-minimum-across-vector">UMINV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ integer maxmin;
+ integer element;
+ 
+ maxmin = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 0, esize], unsigned);
+ for e = 1 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned);
+     maxmin = if min then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(maxmin, element) else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Max.2" title="function: integer Max(integer a, integer b)">Max</a>(maxmin, element);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = maxmin&lt;esize-1:0&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminv_f32" type="checkbox"><label for="vminv_f32"><div>float32_t <b><b>vminv_f32</b></b> (float32x2_t a)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_f32" type="checkbox"><label for="vminvq_f32"><div>float32_t <b><b>vminvq_f32</b></b> (float32x4_t a)<span class="right">Floating-point minimum across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminv-floating-point-minimum-across-vector">FMINV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_FMIN" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMIN</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminvq_f64" type="checkbox"><label for="vminvq_f64"><div>float64_t <b><b>vminvq_f64</b></b> (float64x2_t a)<span class="right">Floating-point minimum pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminp-vector-floating-point-minimum-pairwise-vector">FMINP</a> Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMin.3" title="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnmv_f32" type="checkbox"><label for="vmaxnmv_f32"><div>float32_t <b><b>vmaxnmv_f32</b></b> (float32x2_t a)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a> Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnmvq_f32" type="checkbox"><label for="vmaxnmvq_f32"><div>float32_t <b><b>vmaxnmvq_f32</b></b> (float32x4_t a)<span class="right">Floating-point maximum number across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the largest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmv-floating-point-maximum-number-across-vector">FMAXNMV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_FMAXNUM" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMAXNUM</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vmaxnmvq_f64" type="checkbox"><label for="vmaxnmvq_f64"><div>float64_t <b><b>vmaxnmvq_f64</b></b> (float64x2_t a)<span class="right">Floating-point maximum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmaxnmp-vector-floating-point-maximum-number-pairwise-vector">FMAXNMP</a>  Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminnmv_f32" type="checkbox"><label for="vminnmv_f32"><div>float32_t <b><b>vminnmv_f32</b></b> (float32x2_t a)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a>  Sd,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminnmvq_f32" type="checkbox"><label for="vminnmvq_f32"><div>float32_t <b><b>vminnmvq_f32</b></b> (float32x4_t a)<span class="right">Floating-point minimum number across vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&amp;FP register, and writes the smallest of the values as a scalar to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmv-floating-point-minimum-number-across-vector">FMINNMV</a> Sd,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.Reduce.3" title="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#ReduceOp_FMINNUM" title="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
+  ReduceOp_FMIN, ReduceOp_FMAX,
+  ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMINNUM</a>, operand, esize);</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vminnmvq_f64" type="checkbox"><label for="vminnmvq_f64"><div>float64_t <b><b>vminnmvq_f64</b></b> (float64x2_t a)<span class="right">Floating-point minimum number pairwise</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&amp;FP register after the vector elements of the second source SIMD&amp;FP register, reads each pair of adjacent vector elements in the two source SIMD&amp;FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fminnmp-vector-floating-point-minimum-number-pairwise-vector">FMINNMP</a>  Dd,Vn.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ bits(2*datasize) concat = operand2:operand1;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     if pair then
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
+     else
+         element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+         element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+ 
+     if minimum then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMinNum.3" title="function: bits(N) FPMinNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMinNum</a>(element1, element2, FPCR);
+     else
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMaxNum.3" title="function: bits(N) FPMaxNum(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMaxNum</a>(element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vext_s8" type="checkbox"><label for="vext_s8"><div>int8x8_t <b><b>vext_s8</b></b> (int8x8_t a, int8x8_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_s8" type="checkbox"><label for="vextq_s8"><div>int8x16_t <b><b>vextq_s8</b></b> (int8x16_t a, int8x16_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_s16" type="checkbox"><label for="vext_s16"><div>int16x4_t <b><b>vext_s16</b></b> (int16x4_t a, int16x4_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_s16" type="checkbox"><label for="vextq_s16"><div>int16x8_t <b><b>vextq_s16</b></b> (int16x8_t a, int16x8_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_s32" type="checkbox"><label for="vext_s32"><div>int32x2_t <b><b>vext_s32</b></b> (int32x2_t a, int32x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_s32" type="checkbox"><label for="vextq_s32"><div>int32x4_t <b><b>vextq_s32</b></b> (int32x4_t a, int32x4_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_s64" type="checkbox"><label for="vext_s64"><div>int64x1_t <b><b>vext_s64</b></b> (int64x1_t a, int64x1_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_s64" type="checkbox"><label for="vextq_s64"><div>int64x2_t <b><b>vextq_s64</b></b> (int64x2_t a, int64x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_u8" type="checkbox"><label for="vext_u8"><div>uint8x8_t <b><b>vext_u8</b></b> (uint8x8_t a, uint8x8_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_u8" type="checkbox"><label for="vextq_u8"><div>uint8x16_t <b><b>vextq_u8</b></b> (uint8x16_t a, uint8x16_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_u16" type="checkbox"><label for="vext_u16"><div>uint16x4_t <b><b>vext_u16</b></b> (uint16x4_t a, uint16x4_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_u16" type="checkbox"><label for="vextq_u16"><div>uint16x8_t <b><b>vextq_u16</b></b> (uint16x8_t a, uint16x8_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_u32" type="checkbox"><label for="vext_u32"><div>uint32x2_t <b><b>vext_u32</b></b> (uint32x2_t a, uint32x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_u32" type="checkbox"><label for="vextq_u32"><div>uint32x4_t <b><b>vextq_u32</b></b> (uint32x4_t a, uint32x4_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_u64" type="checkbox"><label for="vext_u64"><div>uint64x1_t <b><b>vext_u64</b></b> (uint64x1_t a, uint64x1_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_u64" type="checkbox"><label for="vextq_u64"><div>uint64x2_t <b><b>vextq_u64</b></b> (uint64x2_t a, uint64x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_p64" type="checkbox"><label for="vext_p64"><div>poly64x1_t <b><b>vext_p64</b></b> (poly64x1_t a, poly64x1_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_p64" type="checkbox"><label for="vextq_p64"><div>poly64x2_t <b><b>vextq_p64</b></b> (poly64x2_t a, poly64x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_f32" type="checkbox"><label for="vext_f32"><div>float32x2_t <b><b>vext_f32</b></b> (float32x2_t a, float32x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_f32" type="checkbox"><label for="vextq_f32"><div>float32x4_t <b><b>vextq_f32</b></b> (float32x4_t a, float32x4_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_f64" type="checkbox"><label for="vext_f64"><div>float64x1_t <b><b>vext_f64</b></b> (float64x1_t a, float64x1_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vextq_f64" type="checkbox"><label for="vextq_f64"><div>float64x2_t <b><b>vextq_f64</b></b> (float64x2_t a, float64x2_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vext_p8" type="checkbox"><label for="vext_p8"><div>poly8x8_t <b><b>vext_p8</b></b> (poly8x8_t a, poly8x8_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_p8" type="checkbox"><label for="vextq_p8"><div>poly8x16_t <b><b>vextq_p8</b></b> (poly8x16_t a, poly8x16_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#n
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vext_p16" type="checkbox"><label for="vext_p16"><div>poly16x4_t <b><b>vext_p16</b></b> (poly16x4_t a, poly16x4_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B <br />
+ 0 &lt;&lt; n &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vextq_p16" type="checkbox"><label for="vextq_p16"><div>poly16x8_t <b><b>vextq_p16</b></b> (poly16x8_t a, poly16x8_t b, const int n)<span class="right">Extract vector from pair of vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&amp;FP register and the highest vector elements from the first source SIMD&amp;FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&amp;FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ext-extract-vector-from-pair-of-vectors">EXT</a> Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B <br />
+ 0 &lt;&lt; n &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) hi = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) lo = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize*2) concat = hi:lo;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = concat&lt;position+datasize-1:position&gt;;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_s8" type="checkbox"><label for="vrev64_s8"><div>int8x8_t <b><b>vrev64_s8</b></b> (int8x8_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_s8" type="checkbox"><label for="vrev64q_s8"><div>int8x16_t <b><b>vrev64q_s8</b></b> (int8x16_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_s16" type="checkbox"><label for="vrev64_s16"><div>int16x4_t <b><b>vrev64_s16</b></b> (int16x4_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_s16" type="checkbox"><label for="vrev64q_s16"><div>int16x8_t <b><b>vrev64q_s16</b></b> (int16x8_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_s32" type="checkbox"><label for="vrev64_s32"><div>int32x2_t <b><b>vrev64_s32</b></b> (int32x2_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_s32" type="checkbox"><label for="vrev64q_s32"><div>int32x4_t <b><b>vrev64q_s32</b></b> (int32x4_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_u8" type="checkbox"><label for="vrev64_u8"><div>uint8x8_t <b><b>vrev64_u8</b></b> (uint8x8_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_u8" type="checkbox"><label for="vrev64q_u8"><div>uint8x16_t <b><b>vrev64q_u8</b></b> (uint8x16_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_u16" type="checkbox"><label for="vrev64_u16"><div>uint16x4_t <b><b>vrev64_u16</b></b> (uint16x4_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_u16" type="checkbox"><label for="vrev64q_u16"><div>uint16x8_t <b><b>vrev64q_u16</b></b> (uint16x8_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_u32" type="checkbox"><label for="vrev64_u32"><div>uint32x2_t <b><b>vrev64_u32</b></b> (uint32x2_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_u32" type="checkbox"><label for="vrev64q_u32"><div>uint32x4_t <b><b>vrev64q_u32</b></b> (uint32x4_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_f32" type="checkbox"><label for="vrev64_f32"><div>float32x2_t <b><b>vrev64_f32</b></b> (float32x2_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.2S,Vn.2S
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_f32" type="checkbox"><label for="vrev64q_f32"><div>float32x4_t <b><b>vrev64q_f32</b></b> (float32x4_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_p8" type="checkbox"><label for="vrev64_p8"><div>poly8x8_t <b><b>vrev64_p8</b></b> (poly8x8_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_p8" type="checkbox"><label for="vrev64q_p8"><div>poly8x16_t <b><b>vrev64q_p8</b></b> (poly8x16_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64_p16" type="checkbox"><label for="vrev64_p16"><div>poly16x4_t <b><b>vrev64_p16</b></b> (poly16x4_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev64q_p16" type="checkbox"><label for="vrev64q_p16"><div>poly16x8_t <b><b>vrev64q_p16</b></b> (poly16x8_t vec)<span class="right">Reverse elements in 64-bit doublewords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev64-reverse-elements-in-64-bit-doublewords-vector">REV64</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32_s8" type="checkbox"><label for="vrev32_s8"><div>int8x8_t <b><b>vrev32_s8</b></b> (int8x8_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32q_s8" type="checkbox"><label for="vrev32q_s8"><div>int8x16_t <b><b>vrev32q_s8</b></b> (int8x16_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32_s16" type="checkbox"><label for="vrev32_s16"><div>int16x4_t <b><b>vrev32_s16</b></b> (int16x4_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32q_s16" type="checkbox"><label for="vrev32q_s16"><div>int16x8_t <b><b>vrev32q_s16</b></b> (int16x8_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32_u8" type="checkbox"><label for="vrev32_u8"><div>uint8x8_t <b><b>vrev32_u8</b></b> (uint8x8_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32q_u8" type="checkbox"><label for="vrev32q_u8"><div>uint8x16_t <b><b>vrev32q_u8</b></b> (uint8x16_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32_u16" type="checkbox"><label for="vrev32_u16"><div>uint16x4_t <b><b>vrev32_u16</b></b> (uint16x4_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32q_u16" type="checkbox"><label for="vrev32q_u16"><div>uint16x8_t <b><b>vrev32q_u16</b></b> (uint16x8_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32_p8" type="checkbox"><label for="vrev32_p8"><div>poly8x8_t <b><b>vrev32_p8</b></b> (poly8x8_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32q_p8" type="checkbox"><label for="vrev32q_p8"><div>poly8x16_t <b><b>vrev32q_p8</b></b> (poly8x16_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32_p16" type="checkbox"><label for="vrev32_p16"><div>poly16x4_t <b><b>vrev32_p16</b></b> (poly16x4_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.4H,Vn.4H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev32q_p16" type="checkbox"><label for="vrev32q_p16"><div>poly16x8_t <b><b>vrev32q_p16</b></b> (poly16x8_t vec)<span class="right">Reverse elements in 32-bit words</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev32-vector-reverse-elements-in-32-bit-words-vector">REV32</a> Vd.8H,Vn.8H
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev16_s8" type="checkbox"><label for="vrev16_s8"><div>int8x8_t <b><b>vrev16_s8</b></b> (int8x8_t vec)<span class="right">Reverse elements in 16-bit halfwords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev16-vector-reverse-elements-in-16-bit-halfwords-vector">REV16</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev16q_s8" type="checkbox"><label for="vrev16q_s8"><div>int8x16_t <b><b>vrev16q_s8</b></b> (int8x16_t vec)<span class="right">Reverse elements in 16-bit halfwords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev16-vector-reverse-elements-in-16-bit-halfwords-vector">REV16</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev16_u8" type="checkbox"><label for="vrev16_u8"><div>uint8x8_t <b><b>vrev16_u8</b></b> (uint8x8_t vec)<span class="right">Reverse elements in 16-bit halfwords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev16-vector-reverse-elements-in-16-bit-halfwords-vector">REV16</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev16q_u8" type="checkbox"><label for="vrev16q_u8"><div>uint8x16_t <b><b>vrev16q_u8</b></b> (uint8x16_t vec)<span class="right">Reverse elements in 16-bit halfwords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev16-vector-reverse-elements-in-16-bit-halfwords-vector">REV16</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev16_p8" type="checkbox"><label for="vrev16_p8"><div>poly8x8_t <b><b>vrev16_p8</b></b> (poly8x8_t vec)<span class="right">Reverse elements in 16-bit halfwords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev16-vector-reverse-elements-in-16-bit-halfwords-vector">REV16</a> Vd.8B,Vn.8B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vrev16q_p8" type="checkbox"><label for="vrev16q_p8"><div>poly8x16_t <b><b>vrev16q_p8</b></b> (poly8x16_t vec)<span class="right">Reverse elements in 16-bit halfwords</span></div></label><article>      <h4>Description</h4><p><p class="aml">Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&amp;FP register, places the results into a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/rev16-vector-reverse-elements-in-16-bit-halfwords-vector">REV16</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>vec &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ integer element = 0;
+ integer rev_element;
+ for c = 0 to containers-1
+     rev_element = element + elements_per_container - 1;
+     for e = 0 to elements_per_container-1
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
+         element = element + 1;
+         rev_element = rev_element - 1;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_s8" type="checkbox"><label for="vzip1_s8"><div>int8x8_t <b><b>vzip1_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_s8" type="checkbox"><label for="vzip1q_s8"><div>int8x16_t <b><b>vzip1q_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_s16" type="checkbox"><label for="vzip1_s16"><div>int16x4_t <b><b>vzip1_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_s16" type="checkbox"><label for="vzip1q_s16"><div>int16x8_t <b><b>vzip1q_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_s32" type="checkbox"><label for="vzip1_s32"><div>int32x2_t <b><b>vzip1_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_s32" type="checkbox"><label for="vzip1q_s32"><div>int32x4_t <b><b>vzip1q_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_s64" type="checkbox"><label for="vzip1q_s64"><div>int64x2_t <b><b>vzip1q_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_u8" type="checkbox"><label for="vzip1_u8"><div>uint8x8_t <b><b>vzip1_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_u8" type="checkbox"><label for="vzip1q_u8"><div>uint8x16_t <b><b>vzip1q_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_u16" type="checkbox"><label for="vzip1_u16"><div>uint16x4_t <b><b>vzip1_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_u16" type="checkbox"><label for="vzip1q_u16"><div>uint16x8_t <b><b>vzip1q_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_u32" type="checkbox"><label for="vzip1_u32"><div>uint32x2_t <b><b>vzip1_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_u32" type="checkbox"><label for="vzip1q_u32"><div>uint32x4_t <b><b>vzip1q_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_u64" type="checkbox"><label for="vzip1q_u64"><div>uint64x2_t <b><b>vzip1q_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_p64" type="checkbox"><label for="vzip1q_p64"><div>poly64x2_t <b><b>vzip1q_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_f32" type="checkbox"><label for="vzip1_f32"><div>float32x2_t <b><b>vzip1_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_f32" type="checkbox"><label for="vzip1q_f32"><div>float32x4_t <b><b>vzip1q_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_f64" type="checkbox"><label for="vzip1q_f64"><div>float64x2_t <b><b>vzip1q_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_p8" type="checkbox"><label for="vzip1_p8"><div>poly8x8_t <b><b>vzip1_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_p8" type="checkbox"><label for="vzip1q_p8"><div>poly8x16_t <b><b>vzip1q_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1_p16" type="checkbox"><label for="vzip1_p16"><div>poly16x4_t <b><b>vzip1_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip1q_p16" type="checkbox"><label for="vzip1q_p16"><div>poly16x8_t <b><b>vzip1q_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_s8" type="checkbox"><label for="vzip2_s8"><div>int8x8_t <b><b>vzip2_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_s8" type="checkbox"><label for="vzip2q_s8"><div>int8x16_t <b><b>vzip2q_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_s16" type="checkbox"><label for="vzip2_s16"><div>int16x4_t <b><b>vzip2_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_s16" type="checkbox"><label for="vzip2q_s16"><div>int16x8_t <b><b>vzip2q_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_s32" type="checkbox"><label for="vzip2_s32"><div>int32x2_t <b><b>vzip2_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_s32" type="checkbox"><label for="vzip2q_s32"><div>int32x4_t <b><b>vzip2q_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_s64" type="checkbox"><label for="vzip2q_s64"><div>int64x2_t <b><b>vzip2q_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_u8" type="checkbox"><label for="vzip2_u8"><div>uint8x8_t <b><b>vzip2_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_u8" type="checkbox"><label for="vzip2q_u8"><div>uint8x16_t <b><b>vzip2q_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_u16" type="checkbox"><label for="vzip2_u16"><div>uint16x4_t <b><b>vzip2_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_u16" type="checkbox"><label for="vzip2q_u16"><div>uint16x8_t <b><b>vzip2q_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_u32" type="checkbox"><label for="vzip2_u32"><div>uint32x2_t <b><b>vzip2_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_u32" type="checkbox"><label for="vzip2q_u32"><div>uint32x4_t <b><b>vzip2q_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_u64" type="checkbox"><label for="vzip2q_u64"><div>uint64x2_t <b><b>vzip2q_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_p64" type="checkbox"><label for="vzip2q_p64"><div>poly64x2_t <b><b>vzip2q_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_f32" type="checkbox"><label for="vzip2_f32"><div>float32x2_t <b><b>vzip2_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_f32" type="checkbox"><label for="vzip2q_f32"><div>float32x4_t <b><b>vzip2q_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_f64" type="checkbox"><label for="vzip2q_f64"><div>float64x2_t <b><b>vzip2q_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_p8" type="checkbox"><label for="vzip2_p8"><div>poly8x8_t <b><b>vzip2_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_p8" type="checkbox"><label for="vzip2q_p8"><div>poly8x16_t <b><b>vzip2q_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2_p16" type="checkbox"><label for="vzip2_p16"><div>poly16x4_t <b><b>vzip2_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vzip2q_p16" type="checkbox"><label for="vzip2q_p16"><div>poly16x8_t <b><b>vzip2q_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_s8" type="checkbox"><label for="vuzp1_s8"><div>int8x8_t <b><b>vuzp1_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_s8" type="checkbox"><label for="vuzp1q_s8"><div>int8x16_t <b><b>vuzp1q_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_s16" type="checkbox"><label for="vuzp1_s16"><div>int16x4_t <b><b>vuzp1_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_s16" type="checkbox"><label for="vuzp1q_s16"><div>int16x8_t <b><b>vuzp1q_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_s32" type="checkbox"><label for="vuzp1_s32"><div>int32x2_t <b><b>vuzp1_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_s32" type="checkbox"><label for="vuzp1q_s32"><div>int32x4_t <b><b>vuzp1q_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_s64" type="checkbox"><label for="vuzp1q_s64"><div>int64x2_t <b><b>vuzp1q_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_u8" type="checkbox"><label for="vuzp1_u8"><div>uint8x8_t <b><b>vuzp1_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_u8" type="checkbox"><label for="vuzp1q_u8"><div>uint8x16_t <b><b>vuzp1q_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_u16" type="checkbox"><label for="vuzp1_u16"><div>uint16x4_t <b><b>vuzp1_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_u16" type="checkbox"><label for="vuzp1q_u16"><div>uint16x8_t <b><b>vuzp1q_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_u32" type="checkbox"><label for="vuzp1_u32"><div>uint32x2_t <b><b>vuzp1_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_u32" type="checkbox"><label for="vuzp1q_u32"><div>uint32x4_t <b><b>vuzp1q_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_u64" type="checkbox"><label for="vuzp1q_u64"><div>uint64x2_t <b><b>vuzp1q_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_p64" type="checkbox"><label for="vuzp1q_p64"><div>poly64x2_t <b><b>vuzp1q_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_f32" type="checkbox"><label for="vuzp1_f32"><div>float32x2_t <b><b>vuzp1_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_f32" type="checkbox"><label for="vuzp1q_f32"><div>float32x4_t <b><b>vuzp1q_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_f64" type="checkbox"><label for="vuzp1q_f64"><div>float64x2_t <b><b>vuzp1q_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_p8" type="checkbox"><label for="vuzp1_p8"><div>poly8x8_t <b><b>vuzp1_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_p8" type="checkbox"><label for="vuzp1q_p8"><div>poly8x16_t <b><b>vuzp1q_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1_p16" type="checkbox"><label for="vuzp1_p16"><div>poly16x4_t <b><b>vuzp1_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp1q_p16" type="checkbox"><label for="vuzp1q_p16"><div>poly16x8_t <b><b>vuzp1q_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_s8" type="checkbox"><label for="vuzp2_s8"><div>int8x8_t <b><b>vuzp2_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_s8" type="checkbox"><label for="vuzp2q_s8"><div>int8x16_t <b><b>vuzp2q_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_s16" type="checkbox"><label for="vuzp2_s16"><div>int16x4_t <b><b>vuzp2_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_s16" type="checkbox"><label for="vuzp2q_s16"><div>int16x8_t <b><b>vuzp2q_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_s32" type="checkbox"><label for="vuzp2_s32"><div>int32x2_t <b><b>vuzp2_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_s32" type="checkbox"><label for="vuzp2q_s32"><div>int32x4_t <b><b>vuzp2q_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_s64" type="checkbox"><label for="vuzp2q_s64"><div>int64x2_t <b><b>vuzp2q_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_u8" type="checkbox"><label for="vuzp2_u8"><div>uint8x8_t <b><b>vuzp2_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_u8" type="checkbox"><label for="vuzp2q_u8"><div>uint8x16_t <b><b>vuzp2q_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_u16" type="checkbox"><label for="vuzp2_u16"><div>uint16x4_t <b><b>vuzp2_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_u16" type="checkbox"><label for="vuzp2q_u16"><div>uint16x8_t <b><b>vuzp2q_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_u32" type="checkbox"><label for="vuzp2_u32"><div>uint32x2_t <b><b>vuzp2_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_u32" type="checkbox"><label for="vuzp2q_u32"><div>uint32x4_t <b><b>vuzp2q_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_u64" type="checkbox"><label for="vuzp2q_u64"><div>uint64x2_t <b><b>vuzp2q_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_p64" type="checkbox"><label for="vuzp2q_p64"><div>poly64x2_t <b><b>vuzp2q_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_f32" type="checkbox"><label for="vuzp2_f32"><div>float32x2_t <b><b>vuzp2_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_f32" type="checkbox"><label for="vuzp2q_f32"><div>float32x4_t <b><b>vuzp2q_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_f64" type="checkbox"><label for="vuzp2q_f64"><div>float64x2_t <b><b>vuzp2q_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_p8" type="checkbox"><label for="vuzp2_p8"><div>poly8x8_t <b><b>vuzp2_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_p8" type="checkbox"><label for="vuzp2q_p8"><div>poly8x16_t <b><b>vuzp2q_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2_p16" type="checkbox"><label for="vuzp2_p16"><div>poly16x4_t <b><b>vuzp2_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vuzp2q_p16" type="checkbox"><label for="vuzp2q_p16"><div>poly16x8_t <b><b>vuzp2q_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_s8" type="checkbox"><label for="vtrn1_s8"><div>int8x8_t <b><b>vtrn1_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_s8" type="checkbox"><label for="vtrn1q_s8"><div>int8x16_t <b><b>vtrn1q_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_s16" type="checkbox"><label for="vtrn1_s16"><div>int16x4_t <b><b>vtrn1_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_s16" type="checkbox"><label for="vtrn1q_s16"><div>int16x8_t <b><b>vtrn1q_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_s32" type="checkbox"><label for="vtrn1_s32"><div>int32x2_t <b><b>vtrn1_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_s32" type="checkbox"><label for="vtrn1q_s32"><div>int32x4_t <b><b>vtrn1q_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_s64" type="checkbox"><label for="vtrn1q_s64"><div>int64x2_t <b><b>vtrn1q_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_u8" type="checkbox"><label for="vtrn1_u8"><div>uint8x8_t <b><b>vtrn1_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_u8" type="checkbox"><label for="vtrn1q_u8"><div>uint8x16_t <b><b>vtrn1q_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_u16" type="checkbox"><label for="vtrn1_u16"><div>uint16x4_t <b><b>vtrn1_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_u16" type="checkbox"><label for="vtrn1q_u16"><div>uint16x8_t <b><b>vtrn1q_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_u32" type="checkbox"><label for="vtrn1_u32"><div>uint32x2_t <b><b>vtrn1_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_u32" type="checkbox"><label for="vtrn1q_u32"><div>uint32x4_t <b><b>vtrn1q_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_u64" type="checkbox"><label for="vtrn1q_u64"><div>uint64x2_t <b><b>vtrn1q_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_p64" type="checkbox"><label for="vtrn1q_p64"><div>poly64x2_t <b><b>vtrn1q_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_f32" type="checkbox"><label for="vtrn1_f32"><div>float32x2_t <b><b>vtrn1_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_f32" type="checkbox"><label for="vtrn1q_f32"><div>float32x4_t <b><b>vtrn1q_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_f64" type="checkbox"><label for="vtrn1q_f64"><div>float64x2_t <b><b>vtrn1q_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_p8" type="checkbox"><label for="vtrn1_p8"><div>poly8x8_t <b><b>vtrn1_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_p8" type="checkbox"><label for="vtrn1q_p8"><div>poly8x16_t <b><b>vtrn1q_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1_p16" type="checkbox"><label for="vtrn1_p16"><div>poly16x4_t <b><b>vtrn1_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn1q_p16" type="checkbox"><label for="vtrn1q_p16"><div>poly16x8_t <b><b>vtrn1q_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&amp;FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_s8" type="checkbox"><label for="vtrn2_s8"><div>int8x8_t <b><b>vtrn2_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_s8" type="checkbox"><label for="vtrn2q_s8"><div>int8x16_t <b><b>vtrn2q_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_s16" type="checkbox"><label for="vtrn2_s16"><div>int16x4_t <b><b>vtrn2_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_s16" type="checkbox"><label for="vtrn2q_s16"><div>int16x8_t <b><b>vtrn2q_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_s32" type="checkbox"><label for="vtrn2_s32"><div>int32x2_t <b><b>vtrn2_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_s32" type="checkbox"><label for="vtrn2q_s32"><div>int32x4_t <b><b>vtrn2q_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_s64" type="checkbox"><label for="vtrn2q_s64"><div>int64x2_t <b><b>vtrn2q_s64</b></b> (int64x2_t a, int64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_u8" type="checkbox"><label for="vtrn2_u8"><div>uint8x8_t <b><b>vtrn2_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_u8" type="checkbox"><label for="vtrn2q_u8"><div>uint8x16_t <b><b>vtrn2q_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_u16" type="checkbox"><label for="vtrn2_u16"><div>uint16x4_t <b><b>vtrn2_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_u16" type="checkbox"><label for="vtrn2q_u16"><div>uint16x8_t <b><b>vtrn2q_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_u32" type="checkbox"><label for="vtrn2_u32"><div>uint32x2_t <b><b>vtrn2_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_u32" type="checkbox"><label for="vtrn2q_u32"><div>uint32x4_t <b><b>vtrn2q_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_u64" type="checkbox"><label for="vtrn2q_u64"><div>uint64x2_t <b><b>vtrn2q_u64</b></b> (uint64x2_t a, uint64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_p64" type="checkbox"><label for="vtrn2q_p64"><div>poly64x2_t <b><b>vtrn2q_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_f32" type="checkbox"><label for="vtrn2_f32"><div>float32x2_t <b><b>vtrn2_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_f32" type="checkbox"><label for="vtrn2q_f32"><div>float32x4_t <b><b>vtrn2q_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_f64" type="checkbox"><label for="vtrn2q_f64"><div>float64x2_t <b><b>vtrn2q_f64</b></b> (float64x2_t a, float64x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.2D,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_p8" type="checkbox"><label for="vtrn2_p8"><div>poly8x8_t <b><b>vtrn2_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_p8" type="checkbox"><label for="vtrn2q_p8"><div>poly8x16_t <b><b>vtrn2q_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2_p16" type="checkbox"><label for="vtrn2_p16"><div>poly16x4_t <b><b>vtrn2_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn2q_p16" type="checkbox"><label for="vtrn2q_p16"><div>poly16x8_t <b><b>vtrn2q_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtbl1_s8" type="checkbox"><label for="vtbl1_s8"><div>int8x8_t <b><b>vtbl1_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; Zeros(64):a <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl1_u8" type="checkbox"><label for="vtbl1_u8"><div>uint8x8_t <b><b>vtbl1_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; Zeros(64):a <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl1_p8" type="checkbox"><label for="vtbl1_p8"><div>poly8x8_t <b><b>vtbl1_p8</b></b> (poly8x8_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; Zeros(64):a <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx1_s8" type="checkbox"><label for="vtbx1_s8"><div>int8x8_t <b><b>vtbx1_s8</b></b> (int8x8_t a, int8x8_t b, int8x8_t c)<span class="right">Bitwise insert if false</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&amp;FP register into the destination SIMD&amp;FP register if the corresponding bit of the second source SIMD&amp;FP register is 0, otherwise leaves the bit in the destination register unchanged.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/movi-move-immediate-vector">MOVI</a> Vtmp.8B,#8
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vtmp.8B,Vm.8B,Vtmp.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vtmp1.8B,{Vn.16B},Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bif-bitwise-insert-if-false">BIF</a> Vd.8B,Vtmp1.8B,Vtmp.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; Zeros(64):b <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ operand3 = NOT(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m]);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx1_u8" type="checkbox"><label for="vtbx1_u8"><div>uint8x8_t <b><b>vtbx1_u8</b></b> (uint8x8_t a, uint8x8_t b, uint8x8_t c)<span class="right">Bitwise insert if false</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&amp;FP register into the destination SIMD&amp;FP register if the corresponding bit of the second source SIMD&amp;FP register is 0, otherwise leaves the bit in the destination register unchanged.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/movi-move-immediate-vector">MOVI</a> Vtmp.8B,#8
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vtmp.8B,Vm.8B,Vtmp.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vtmp1.8B,{Vn.16B},Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bif-bitwise-insert-if-false">BIF</a> Vd.8B,Vtmp1.8B,Vtmp.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; Zeros(64):b <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ operand3 = NOT(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m]);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx1_p8" type="checkbox"><label for="vtbx1_p8"><div>poly8x8_t <b><b>vtbx1_p8</b></b> (poly8x8_t a, poly8x8_t b, uint8x8_t c)<span class="right">Bitwise insert if false</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&amp;FP register into the destination SIMD&amp;FP register if the corresponding bit of the second source SIMD&amp;FP register is 0, otherwise leaves the bit in the destination register unchanged.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/movi-move-immediate-vector">MOVI</a> Vtmp.8B,#8
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vtmp.8B,Vm.8B,Vtmp.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vtmp1.8B,{Vn.16B},Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bif-bitwise-insert-if-false">BIF</a> Vd.8B,Vtmp1.8B, Vtmp.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; Zeros(64):b <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ operand3 = NOT(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m]);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl2_s8" type="checkbox"><label for="vtbl2_s8"><div>int8x8_t <b><b>vtbl2_s8</b></b> (int8x8x2_t a, int8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl2_u8" type="checkbox"><label for="vtbl2_u8"><div>uint8x8_t <b><b>vtbl2_u8</b></b> (uint8x8x2_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl2_p8" type="checkbox"><label for="vtbl2_p8"><div>poly8x8_t <b><b>vtbl2_p8</b></b> (poly8x8x2_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl3_s8" type="checkbox"><label for="vtbl3_s8"><div>int8x8_t <b><b>vtbl3_s8</b></b> (int8x8x3_t a, int8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ Vn+1 &rarr; Zeros(64):a.val[2] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl3_u8" type="checkbox"><label for="vtbl3_u8"><div>uint8x8_t <b><b>vtbl3_u8</b></b> (uint8x8x3_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ Vn+1 &rarr; Zeros(64):a.val[2] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl3_p8" type="checkbox"><label for="vtbl3_p8"><div>poly8x8_t <b><b>vtbl3_p8</b></b> (poly8x8x3_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ Vn+1 &rarr; Zeros(64):a.val[2] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl4_s8" type="checkbox"><label for="vtbl4_s8"><div>int8x8_t <b><b>vtbl4_s8</b></b> (int8x8x4_t a, int8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ Vn+1 &rarr; a.val[3]:a.val[2] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl4_u8" type="checkbox"><label for="vtbl4_u8"><div>uint8x8_t <b><b>vtbl4_u8</b></b> (uint8x8x4_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ Vn+1 &rarr; a.val[3]:a.val[2] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbl4_p8" type="checkbox"><label for="vtbl4_p8"><div>poly8x8_t <b><b>vtbl4_p8</b></b> (poly8x8x4_t a, uint8x8_t b)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>Vn &rarr; a.val[1]:a.val[0] <br />
+ Vn+1 &rarr; a.val[3]:a.val[2] <br />
+ b &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx2_s8" type="checkbox"><label for="vtbx2_s8"><div>int8x8_t <b><b>vtbx2_s8</b></b> (int8x8_t a, int8x8x2_t b, int8x8_t c)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx2_u8" type="checkbox"><label for="vtbx2_u8"><div>uint8x8_t <b><b>vtbx2_u8</b></b> (uint8x8_t a, uint8x8x2_t b, uint8x8_t c)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx2_p8" type="checkbox"><label for="vtbx2_p8"><div>poly8x8_t <b><b>vtbx2_p8</b></b> (poly8x8_t a, poly8x8x2_t b, uint8x8_t c)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx3_s8" type="checkbox"><label for="vtbx3_s8"><div>int8x8_t <b><b>vtbx3_s8</b></b> (int8x8_t a, int8x8x3_t b, int8x8_t c)<span class="right">Bitwise insert if false</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&amp;FP register into the destination SIMD&amp;FP register if the corresponding bit of the second source SIMD&amp;FP register is 0, otherwise leaves the bit in the destination register unchanged.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/movi-move-immediate-vector">MOVI</a> Vtmp.8B,#24
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vtmp.8B,Vm.8B,Vtmp.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bif-bitwise-insert-if-false">BIF</a> Vd.8B,Vtmp1.8B,Vtmp.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ Vn+1 &rarr; Zeros(64):b.val[2] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ operand3 = NOT(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m]);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx3_u8" type="checkbox"><label for="vtbx3_u8"><div>uint8x8_t <b><b>vtbx3_u8</b></b> (uint8x8_t a, uint8x8x3_t b, uint8x8_t c)<span class="right">Bitwise insert if false</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&amp;FP register into the destination SIMD&amp;FP register if the corresponding bit of the second source SIMD&amp;FP register is 0, otherwise leaves the bit in the destination register unchanged.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/movi-move-immediate-vector">MOVI</a> Vtmp.8B,#24
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vtmp.8B,Vm.8B,Vtmp.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bif-bitwise-insert-if-false">BIF</a> Vd.8B,Vtmp1.8B,Vtmp.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ Vn+1 &rarr; Zeros(64):b.val[2] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ operand3 = NOT(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m]);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx3_p8" type="checkbox"><label for="vtbx3_p8"><div>poly8x8_t <b><b>vtbx3_p8</b></b> (poly8x8_t a, poly8x8x3_t b, uint8x8_t c)<span class="right">Bitwise insert if false</span></div></label><article>      <h4>Description</h4><p><p class="aml">Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&amp;FP register into the destination SIMD&amp;FP register if the corresponding bit of the second source SIMD&amp;FP register is 0, otherwise leaves the bit in the destination register unchanged.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/movi-move-immediate-vector">MOVI</a> Vtmp.8B,#24
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/cmhs-register-compare-unsigned-higher-or-same-vector">CMHS</a> Vtmp.8B,Vm.8B,Vtmp.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/bif-bitwise-insert-if-false">BIF</a> Vd.8B,Vtmp1.8B,Vtmp.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ Vn+1 &rarr; Zeros(64):b.val[2] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1;
+ bits(datasize) operand3;
+ bits(datasize) operand4 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ operand3 = NOT(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m]);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx4_s8" type="checkbox"><label for="vtbx4_s8"><div>int8x8_t <b><b>vtbx4_s8</b></b> (int8x8_t a, int8x8x4_t b, int8x8_t c)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ Vn+1 &rarr; b.val[3]:b.val[2] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx4_u8" type="checkbox"><label for="vtbx4_u8"><div>uint8x8_t <b><b>vtbx4_u8</b></b> (uint8x8_t a, uint8x8x4_t b, uint8x8_t c)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ Vn+1 &rarr; b.val[3]:b.val[2] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtbx4_p8" type="checkbox"><label for="vtbx4_p8"><div>poly8x8_t <b><b>vtbx4_p8</b></b> (poly8x8_t a, poly8x8x4_t b, uint8x8_t c)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd <br />
+ Vn &rarr; b.val[1]:b.val[0] <br />
+ Vn+1 &rarr; b.val[3]:b.val[2] <br />
+ c &rarr; Vm </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl1_s8" type="checkbox"><label for="vqtbl1_s8"><div>int8x8_t <b><b>vqtbl1_s8</b></b> (int8x16_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t &rarr; Vn.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl1q_s8" type="checkbox"><label for="vqtbl1q_s8"><div>int8x16_t <b><b>vqtbl1q_s8</b></b> (int8x16_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t &rarr; Vn.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl1_u8" type="checkbox"><label for="vqtbl1_u8"><div>uint8x8_t <b><b>vqtbl1_u8</b></b> (uint8x16_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t &rarr; Vn.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl1q_u8" type="checkbox"><label for="vqtbl1q_u8"><div>uint8x16_t <b><b>vqtbl1q_u8</b></b> (uint8x16_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t &rarr; Vn.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl1_p8" type="checkbox"><label for="vqtbl1_p8"><div>poly8x8_t <b><b>vqtbl1_p8</b></b> (poly8x16_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t &rarr; Vn.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl1q_p8" type="checkbox"><label for="vqtbl1q_p8"><div>poly8x16_t <b><b>vqtbl1q_p8</b></b> (poly8x16_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t &rarr; Vn.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx1_s8" type="checkbox"><label for="vqtbx1_s8"><div>int8x8_t <b><b>vqtbx1_s8</b></b> (int8x8_t a, int8x16_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t &rarr; Vn.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx1q_s8" type="checkbox"><label for="vqtbx1q_s8"><div>int8x16_t <b><b>vqtbx1q_s8</b></b> (int8x16_t a, int8x16_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t &rarr; Vn.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx1_u8" type="checkbox"><label for="vqtbx1_u8"><div>uint8x8_t <b><b>vqtbx1_u8</b></b> (uint8x8_t a, uint8x16_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t &rarr; Vn.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx1q_u8" type="checkbox"><label for="vqtbx1q_u8"><div>uint8x16_t <b><b>vqtbx1q_u8</b></b> (uint8x16_t a, uint8x16_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t &rarr; Vn.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx1_p8" type="checkbox"><label for="vqtbx1_p8"><div>poly8x8_t <b><b>vqtbx1_p8</b></b> (poly8x8_t a, poly8x16_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t &rarr; Vn.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx1q_p8" type="checkbox"><label for="vqtbx1q_p8"><div>poly8x16_t <b><b>vqtbx1q_p8</b></b> (poly8x16_t a, poly8x16_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t &rarr; Vn.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl2_s8" type="checkbox"><label for="vqtbl2_s8"><div>int8x8_t <b><b>vqtbl2_s8</b></b> (int8x16x2_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl2q_s8" type="checkbox"><label for="vqtbl2q_s8"><div>int8x16_t <b><b>vqtbl2q_s8</b></b> (int8x16x2_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl2_u8" type="checkbox"><label for="vqtbl2_u8"><div>uint8x8_t <b><b>vqtbl2_u8</b></b> (uint8x16x2_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl2q_u8" type="checkbox"><label for="vqtbl2q_u8"><div>uint8x16_t <b><b>vqtbl2q_u8</b></b> (uint8x16x2_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl2_p8" type="checkbox"><label for="vqtbl2_p8"><div>poly8x8_t <b><b>vqtbl2_p8</b></b> (poly8x16x2_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl2q_p8" type="checkbox"><label for="vqtbl2q_p8"><div>poly8x16_t <b><b>vqtbl2q_p8</b></b> (poly8x16x2_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl3_s8" type="checkbox"><label for="vqtbl3_s8"><div>int8x8_t <b><b>vqtbl3_s8</b></b> (int8x16x3_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl3q_s8" type="checkbox"><label for="vqtbl3q_s8"><div>int8x16_t <b><b>vqtbl3q_s8</b></b> (int8x16x3_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl3_u8" type="checkbox"><label for="vqtbl3_u8"><div>uint8x8_t <b><b>vqtbl3_u8</b></b> (uint8x16x3_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl3q_u8" type="checkbox"><label for="vqtbl3q_u8"><div>uint8x16_t <b><b>vqtbl3q_u8</b></b> (uint8x16x3_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl3_p8" type="checkbox"><label for="vqtbl3_p8"><div>poly8x8_t <b><b>vqtbl3_p8</b></b> (poly8x16x3_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl3q_p8" type="checkbox"><label for="vqtbl3q_p8"><div>poly8x16_t <b><b>vqtbl3q_p8</b></b> (poly8x16x3_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl4_s8" type="checkbox"><label for="vqtbl4_s8"><div>int8x8_t <b><b>vqtbl4_s8</b></b> (int8x16x4_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl4q_s8" type="checkbox"><label for="vqtbl4q_s8"><div>int8x16_t <b><b>vqtbl4q_s8</b></b> (int8x16x4_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl4_u8" type="checkbox"><label for="vqtbl4_u8"><div>uint8x8_t <b><b>vqtbl4_u8</b></b> (uint8x16x4_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl4q_u8" type="checkbox"><label for="vqtbl4q_u8"><div>uint8x16_t <b><b>vqtbl4q_u8</b></b> (uint8x16x4_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl4_p8" type="checkbox"><label for="vqtbl4_p8"><div>poly8x8_t <b><b>vqtbl4_p8</b></b> (poly8x16x4_t t, uint8x8_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbl4q_p8" type="checkbox"><label for="vqtbl4q_p8"><div>poly8x16_t <b><b>vqtbl4q_p8</b></b> (poly8x16x4_t t, uint8x16_t idx)<span class="right">Table vector lookup</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbl-table-vector-lookup">TBL</a> Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx2_s8" type="checkbox"><label for="vqtbx2_s8"><div>int8x8_t <b><b>vqtbx2_s8</b></b> (int8x8_t a, int8x16x2_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx2q_s8" type="checkbox"><label for="vqtbx2q_s8"><div>int8x16_t <b><b>vqtbx2q_s8</b></b> (int8x16_t a, int8x16x2_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx2_u8" type="checkbox"><label for="vqtbx2_u8"><div>uint8x8_t <b><b>vqtbx2_u8</b></b> (uint8x8_t a, uint8x16x2_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx2q_u8" type="checkbox"><label for="vqtbx2q_u8"><div>uint8x16_t <b><b>vqtbx2q_u8</b></b> (uint8x16_t a, uint8x16x2_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx2_p8" type="checkbox"><label for="vqtbx2_p8"><div>poly8x8_t <b><b>vqtbx2_p8</b></b> (poly8x8_t a, poly8x16x2_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx2q_p8" type="checkbox"><label for="vqtbx2q_p8"><div>poly8x16_t <b><b>vqtbx2q_p8</b></b> (poly8x16_t a, poly8x16x2_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx3_s8" type="checkbox"><label for="vqtbx3_s8"><div>int8x8_t <b><b>vqtbx3_s8</b></b> (int8x8_t a, int8x16x3_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx3q_s8" type="checkbox"><label for="vqtbx3q_s8"><div>int8x16_t <b><b>vqtbx3q_s8</b></b> (int8x16_t a, int8x16x3_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx3_u8" type="checkbox"><label for="vqtbx3_u8"><div>uint8x8_t <b><b>vqtbx3_u8</b></b> (uint8x8_t a, uint8x16x3_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx3q_u8" type="checkbox"><label for="vqtbx3q_u8"><div>uint8x16_t <b><b>vqtbx3q_u8</b></b> (uint8x16_t a, uint8x16x3_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx3_p8" type="checkbox"><label for="vqtbx3_p8"><div>poly8x8_t <b><b>vqtbx3_p8</b></b> (poly8x8_t a, poly8x16x3_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx3q_p8" type="checkbox"><label for="vqtbx3q_p8"><div>poly8x16_t <b><b>vqtbx3q_p8</b></b> (poly8x16_t a, poly8x16x3_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx4_s8" type="checkbox"><label for="vqtbx4_s8"><div>int8x8_t <b><b>vqtbx4_s8</b></b> (int8x8_t a, int8x16x4_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx4q_s8" type="checkbox"><label for="vqtbx4q_s8"><div>int8x16_t <b><b>vqtbx4q_s8</b></b> (int8x16_t a, int8x16x4_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx4_u8" type="checkbox"><label for="vqtbx4_u8"><div>uint8x8_t <b><b>vqtbx4_u8</b></b> (uint8x8_t a, uint8x16x4_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx4q_u8" type="checkbox"><label for="vqtbx4q_u8"><div>uint8x16_t <b><b>vqtbx4q_u8</b></b> (uint8x16_t a, uint8x16x4_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx4_p8" type="checkbox"><label for="vqtbx4_p8"><div>poly8x8_t <b><b>vqtbx4_p8</b></b> (poly8x8_t a, poly8x16x4_t t, uint8x8_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vqtbx4q_p8" type="checkbox"><label for="vqtbx4q_p8"><div>poly8x16_t <b><b>vqtbx4q_p8</b></b> (poly8x16_t a, poly8x16x4_t t, uint8x16_t idx)<span class="right">Table vector lookup extension</span></div></label><article>      <h4>Description</h4><p><p class="aml">Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&amp;FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&amp;FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&amp;FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/tbx-table-vector-lookup-extension">TBX</a> Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B <br />
+ t.val[0] &rarr; Vn.16B <br />
+ t.val[1] &rarr; Vn+1.16B <br />
+ t.val[2] &rarr; Vn+2.16B <br />
+ t.val[3] &rarr; Vn+3.16B <br />
+ idx &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) indices = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128*regs) table = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>();
+ bits(datasize) result;
+ integer index;
+ 
+ // Create table from registers
+ for i = 0 to regs-1
+     table&lt;128*i+127:128*i&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+     n = (n + 1) MOD 32;
+ 
+ result = if is_tbl then <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.0" title="function: bits(N) Zeros()">Zeros</a>() else <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ for i = 0 to elements-1
+     index = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
+     if index &lt; 16 * regs then
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_u8" type="checkbox"><label for="vget_lane_u8"><div>uint8_t <b><b>vget_lane_u8</b></b> (uint8x8_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_u16" type="checkbox"><label for="vget_lane_u16"><div>uint16_t <b><b>vget_lane_u16</b></b> (uint16x4_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_u32" type="checkbox"><label for="vget_lane_u32"><div>uint32_t <b><b>vget_lane_u32</b></b> (uint32x2_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_u64" type="checkbox"><label for="vget_lane_u64"><div>uint64_t <b><b>vget_lane_u64</b></b> (uint64x1_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_p64" type="checkbox"><label for="vget_lane_p64"><div>poly64_t <b><b>vget_lane_p64</b></b> (poly64x1_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_s8" type="checkbox"><label for="vget_lane_s8"><div>int8_t <b><b>vget_lane_s8</b></b> (int8x8_t v, const int lane)<span class="right">Signed move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smov-signed-move-vector-element-to-general-purpose-register">SMOV</a> Rd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_s16" type="checkbox"><label for="vget_lane_s16"><div>int16_t <b><b>vget_lane_s16</b></b> (int16x4_t v, const int lane)<span class="right">Signed move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smov-signed-move-vector-element-to-general-purpose-register">SMOV</a> Rd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_s32" type="checkbox"><label for="vget_lane_s32"><div>int32_t <b><b>vget_lane_s32</b></b> (int32x2_t v, const int lane)<span class="right">Signed move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smov-signed-move-vector-element-to-general-purpose-register">SMOV</a> Rd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_s64" type="checkbox"><label for="vget_lane_s64"><div>int64_t <b><b>vget_lane_s64</b></b> (int64x1_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_p8" type="checkbox"><label for="vget_lane_p8"><div>poly8_t <b><b>vget_lane_p8</b></b> (poly8x8_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_p16" type="checkbox"><label for="vget_lane_p16"><div>poly16_t <b><b>vget_lane_p16</b></b> (poly16x4_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_f32" type="checkbox"><label for="vget_lane_f32"><div>float32_t <b><b>vget_lane_f32</b></b> (float32x2_t v, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_f64" type="checkbox"><label for="vget_lane_f64"><div>float64_t <b><b>vget_lane_f64</b></b> (float64x1_t v, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_u8" type="checkbox"><label for="vgetq_lane_u8"><div>uint8_t <b><b>vgetq_lane_u8</b></b> (uint8x16_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_u16" type="checkbox"><label for="vgetq_lane_u16"><div>uint16_t <b><b>vgetq_lane_u16</b></b> (uint16x8_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_u32" type="checkbox"><label for="vgetq_lane_u32"><div>uint32_t <b><b>vgetq_lane_u32</b></b> (uint32x4_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_u64" type="checkbox"><label for="vgetq_lane_u64"><div>uint64_t <b><b>vgetq_lane_u64</b></b> (uint64x2_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_p64" type="checkbox"><label for="vgetq_lane_p64"><div>poly64_t <b><b>vgetq_lane_p64</b></b> (poly64x2_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_s8" type="checkbox"><label for="vgetq_lane_s8"><div>int8_t <b><b>vgetq_lane_s8</b></b> (int8x16_t v, const int lane)<span class="right">Signed move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smov-signed-move-vector-element-to-general-purpose-register">SMOV</a> Rd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_s16" type="checkbox"><label for="vgetq_lane_s16"><div>int16_t <b><b>vgetq_lane_s16</b></b> (int16x8_t v, const int lane)<span class="right">Signed move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smov-signed-move-vector-element-to-general-purpose-register">SMOV</a> Rd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_s32" type="checkbox"><label for="vgetq_lane_s32"><div>int32_t <b><b>vgetq_lane_s32</b></b> (int32x4_t v, const int lane)<span class="right">Signed move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/smov-signed-move-vector-element-to-general-purpose-register">SMOV</a> Rd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_s64" type="checkbox"><label for="vgetq_lane_s64"><div>int64_t <b><b>vgetq_lane_s64</b></b> (int64x2_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_p8" type="checkbox"><label for="vgetq_lane_p8"><div>poly8_t <b><b>vgetq_lane_p8</b></b> (poly8x16_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.B[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_p16" type="checkbox"><label for="vgetq_lane_p16"><div>poly16_t <b><b>vgetq_lane_p16</b></b> (poly16x8_t v, const int lane)<span class="right">Unsigned move vector element to general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&amp;FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/umov-unsigned-move-vector-element-to-general-purpose-register">UMOV</a> Rd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Rd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(idxdsize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vget_lane_f16" type="checkbox"><label for="vget_lane_f16"><div>float16_t <b><b>vget_lane_f16</b></b> (float16x4_t v, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_f16" type="checkbox"><label for="vgetq_lane_f16"><div>float16_t <b><b>vgetq_lane_f16</b></b> (float16x8_t v, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Hd,Vn.H[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Hd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_f32" type="checkbox"><label for="vgetq_lane_f32"><div>float32_t <b><b>vgetq_lane_f32</b></b> (float32x4_t v, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Sd,Vn.S[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vgetq_lane_f64" type="checkbox"><label for="vgetq_lane_f64"><div>float64_t <b><b>vgetq_lane_f64</b></b> (float64x2_t v, const int lane)<span class="right">Duplicate general-purpose register to vector</span></div></label><article>      <h4>Description</h4><p><p class="aml">Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/dup-general-duplicate-general-purpose-register-to-vector">DUP</a> Dd,Vn.D[lane]
+ </pre>      <h4>Argument Preparation</h4><pre>v &rarr; Vn.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(datasize) result;
+ 
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_u8" type="checkbox"><label for="vset_lane_u8"><div>uint8x8_t <b><b>vset_lane_u8</b></b> (uint8_t a, uint8x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_u16" type="checkbox"><label for="vset_lane_u16"><div>uint16x4_t <b><b>vset_lane_u16</b></b> (uint16_t a, uint16x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_u32" type="checkbox"><label for="vset_lane_u32"><div>uint32x2_t <b><b>vset_lane_u32</b></b> (uint32_t a, uint32x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_u64" type="checkbox"><label for="vset_lane_u64"><div>uint64x1_t <b><b>vset_lane_u64</b></b> (uint64_t a, uint64x1_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_p64" type="checkbox"><label for="vset_lane_p64"><div>poly64x1_t <b><b>vset_lane_p64</b></b> (poly64_t a, poly64x1_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_s8" type="checkbox"><label for="vset_lane_s8"><div>int8x8_t <b><b>vset_lane_s8</b></b> (int8_t a, int8x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_s16" type="checkbox"><label for="vset_lane_s16"><div>int16x4_t <b><b>vset_lane_s16</b></b> (int16_t a, int16x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_s32" type="checkbox"><label for="vset_lane_s32"><div>int32x2_t <b><b>vset_lane_s32</b></b> (int32_t a, int32x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_s64" type="checkbox"><label for="vset_lane_s64"><div>int64x1_t <b><b>vset_lane_s64</b></b> (int64_t a, int64x1_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_p8" type="checkbox"><label for="vset_lane_p8"><div>poly8x8_t <b><b>vset_lane_p8</b></b> (poly8_t a, poly8x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.8B <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_p16" type="checkbox"><label for="vset_lane_p16"><div>poly16x4_t <b><b>vset_lane_p16</b></b> (poly16_t a, poly16x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_f16" type="checkbox"><label for="vset_lane_f16"><div>float16x4_t <b><b>vset_lane_f16</b></b> (float16_t a, float16x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Vn.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; VnH <br />
+ v &rarr; Vd.4H <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_f16" type="checkbox"><label for="vsetq_lane_f16"><div>float16x8_t <b><b>vsetq_lane_f16</b></b> (float16_t a, float16x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Vn.H[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; VnH <br />
+ v &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_f32" type="checkbox"><label for="vset_lane_f32"><div>float32x2_t <b><b>vset_lane_f32</b></b> (float32_t a, float32x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2S <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vset_lane_f64" type="checkbox"><label for="vset_lane_f64"><div>float64x1_t <b><b>vset_lane_f64</b></b> (float64_t a, float64x1_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.1D <br />
+ 0 &lt;&lt; lane &lt;&lt; 0 </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_u8" type="checkbox"><label for="vsetq_lane_u8"><div>uint8x16_t <b><b>vsetq_lane_u8</b></b> (uint8_t a, uint8x16_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_u16" type="checkbox"><label for="vsetq_lane_u16"><div>uint16x8_t <b><b>vsetq_lane_u16</b></b> (uint16_t a, uint16x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_u32" type="checkbox"><label for="vsetq_lane_u32"><div>uint32x4_t <b><b>vsetq_lane_u32</b></b> (uint32_t a, uint32x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_u64" type="checkbox"><label for="vsetq_lane_u64"><div>uint64x2_t <b><b>vsetq_lane_u64</b></b> (uint64_t a, uint64x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_p64" type="checkbox"><label for="vsetq_lane_p64"><div>poly64x2_t <b><b>vsetq_lane_p64</b></b> (poly64_t a, poly64x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_s8" type="checkbox"><label for="vsetq_lane_s8"><div>int8x16_t <b><b>vsetq_lane_s8</b></b> (int8_t a, int8x16_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_s16" type="checkbox"><label for="vsetq_lane_s16"><div>int16x8_t <b><b>vsetq_lane_s16</b></b> (int16_t a, int16x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_s32" type="checkbox"><label for="vsetq_lane_s32"><div>int32x4_t <b><b>vsetq_lane_s32</b></b> (int32_t a, int32x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_s64" type="checkbox"><label for="vsetq_lane_s64"><div>int64x2_t <b><b>vsetq_lane_s64</b></b> (int64_t a, int64x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_p8" type="checkbox"><label for="vsetq_lane_p8"><div>poly8x16_t <b><b>vsetq_lane_p8</b></b> (poly8_t a, poly8x16_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.B[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.16B <br />
+ 0 &lt;&lt; lane &lt;&lt; 15 </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_p16" type="checkbox"><label for="vsetq_lane_p16"><div>poly16x8_t <b><b>vsetq_lane_p16</b></b> (poly16_t a, poly16x8_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.H[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.8H <br />
+ 0 &lt;&lt; lane &lt;&lt; 7 </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_f32" type="checkbox"><label for="vsetq_lane_f32"><div>float32x4_t <b><b>vsetq_lane_f32</b></b> (float32_t a, float32x4_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.S[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.4S <br />
+ 0 &lt;&lt; lane &lt;&lt; 3 </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsetq_lane_f64" type="checkbox"><label for="vsetq_lane_f64"><div>float64x2_t <b><b>vsetq_lane_f64</b></b> (float64_t a, float64x2_t v, const int lane)<span class="right">Insert vector element from general-purpose register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ins-general-insert-vector-element-from-general-purpose-register">INS</a> Vd.D[lane],Rn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Rn <br />
+ v &rarr; Vd.2D <br />
+ 0 &lt;&lt; lane &lt;&lt; 1 </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(esize) element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ bits(128) result;
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, index, esize] = element;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpxs_f32" type="checkbox"><label for="vrecpxs_f32"><div>float32_t <b><b>vrecpxs_f32</b></b> (float32_t a)<span class="right">Floating-point reciprocal exponent</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpx-floating-point-reciprocal-exponent-scalar">FRECPX</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecpX.2" title="function: bits(N) FPRecpX(bits(N) op, FPCRType fpcr)">FPRecpX</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vrecpxd_f64" type="checkbox"><label for="vrecpxd_f64"><div>float64_t <b><b>vrecpxd_f64</b></b> (float64_t a)<span class="right">Floating-point reciprocal exponent</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&amp;FP register, places the result in a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/frecpx-floating-point-reciprocal-exponent-scalar">FRECPX</a> Dd,Dn
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Dn </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) result;
+ bits(esize) element;
+ 
+ for e = 0 to elements-1
+     element = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPRecpX.2" title="function: bits(N) FPRecpX(bits(N) op, FPCRType fpcr)">FPRecpX</a>(element, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_n_f32" type="checkbox"><label for="vfma_n_f32"><div>float32x2_t <b><b>vfma_n_f32</b></b> (float32x2_t a, float32x2_t b, float32_t n)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ n &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_n_f32" type="checkbox"><label for="vfmaq_n_f32"><div>float32x4_t <b><b>vfmaq_n_f32</b></b> (float32x4_t a, float32x4_t b, float32_t n)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ n &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vfms_n_f32" type="checkbox"><label for="vfms_n_f32"><div>float32x2_t <b><b>vfms_n_f32</b></b> (float32x2_t a, float32x2_t b, float32_t n)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2S,Vn.2S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S <br />
+ b &rarr; Vn.2S <br />
+ n &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_n_f32" type="checkbox"><label for="vfmsq_n_f32"><div>float32x4_t <b><b>vfmsq_n_f32</b></b> (float32x4_t a, float32x4_t b, float32_t n)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.4S,Vn.4S,Vm.S[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S <br />
+ b &rarr; Vn.4S <br />
+ n &rarr; Vm.S[0] </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfma_n_f64" type="checkbox"><label for="vfma_n_f64"><div>float64x1_t <b><b>vfma_n_f64</b></b> (float64x1_t a, float64x1_t b, float64_t n)<span class="right">Floating-point fused multiply-add</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&amp;FP source registers, adds the product to the value of the third SIMD&amp;FP source register, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmadd-floating-point-fused-multiply-add-scalar">FMADD</a> Dd,Dn,Dm,Da
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Da <br />
+ b &rarr; Dn <br />
+ n &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) result;
+ bits(datasize) operanda = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[a];
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ 
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(operanda, operand1, operand2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmaq_n_f64" type="checkbox"><label for="vfmaq_n_f64"><div>float64x2_t <b><b>vfmaq_n_f64</b></b> (float64x2_t a, float64x2_t b, float64_t n)<span class="right">Floating-point fused multiply-add to accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, adds the product to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmla-vector-floating-point-fused-multiply-add-to-accumulator-vector">FMLA</a> Vd.2D,Vn.2D,Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ n &rarr; Vm.D[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfms_n_f64" type="checkbox"><label for="vfms_n_f64"><div>float64x1_t <b><b>vfms_n_f64</b></b> (float64x1_t a, float64x1_t b, float64_t n)<span class="right">Floating-point fused multiply-subtract</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&amp;FP source registers, negates the product, adds that to the value of the third SIMD&amp;FP source register, and writes the result to the SIMD&amp;FP destination register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmsub-floating-point-fused-multiply-subtract-scalar">FMSUB</a> Dd,Dn,Dm,Da
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Da <br />
+ b &rarr; Dn <br />
+ n &rarr; Dm </pre>      <h4>Results</h4>      <pre>Dd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) result;
+ bits(datasize) operanda = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[a];
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ 
+ operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(operand1);
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(operanda, operand1, operand2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vfmsq_n_f64" type="checkbox"><label for="vfmsq_n_f64"><div>float64x2_t <b><b>vfmsq_n_f64</b></b> (float64x2_t a, float64x2_t b, float64_t n)<span class="right">Floating-point fused multiply-subtract from accumulator</span></div></label><article>      <h4>Description</h4><p><p class="aml">Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&amp;FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&amp;FP register, and writes the result to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/fmls-vector-floating-point-fused-multiply-subtract-from-accumulator-vector">FMLS</a> Vd.2D,Vn.2D,Vm.D[0]
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D <br />
+ b &rarr; Vn.2D <br />
+ n &rarr; Vm.D[0] </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     if sub_op then element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_s8" type="checkbox"><label for="vtrn_s8"><div>int8x8x2_t <b><b>vtrn_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_s16" type="checkbox"><label for="vtrn_s16"><div>int16x4x2_t <b><b>vtrn_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_u8" type="checkbox"><label for="vtrn_u8"><div>uint8x8x2_t <b><b>vtrn_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_u16" type="checkbox"><label for="vtrn_u16"><div>uint16x4x2_t <b><b>vtrn_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_p8" type="checkbox"><label for="vtrn_p8"><div>poly8x8x2_t <b><b>vtrn_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_p16" type="checkbox"><label for="vtrn_p16"><div>poly16x4x2_t <b><b>vtrn_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_s32" type="checkbox"><label for="vtrn_s32"><div>int32x2x2_t <b><b>vtrn_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_f32" type="checkbox"><label for="vtrn_f32"><div>float32x2x2_t <b><b>vtrn_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrn_u32" type="checkbox"><label for="vtrn_u32"><div>uint32x2x2_t <b><b>vtrn_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_s8" type="checkbox"><label for="vtrnq_s8"><div>int8x16x2_t <b><b>vtrnq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_s16" type="checkbox"><label for="vtrnq_s16"><div>int16x8x2_t <b><b>vtrnq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_s32" type="checkbox"><label for="vtrnq_s32"><div>int32x4x2_t <b><b>vtrnq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_f32" type="checkbox"><label for="vtrnq_f32"><div>float32x4x2_t <b><b>vtrnq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_u8" type="checkbox"><label for="vtrnq_u8"><div>uint8x16x2_t <b><b>vtrnq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_u16" type="checkbox"><label for="vtrnq_u16"><div>uint16x8x2_t <b><b>vtrnq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_u32" type="checkbox"><label for="vtrnq_u32"><div>uint32x4x2_t <b><b>vtrnq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_p8" type="checkbox"><label for="vtrnq_p8"><div>poly8x16x2_t <b><b>vtrnq_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vtrnq_p16" type="checkbox"><label for="vtrnq_p16"><div>poly16x8x2_t <b><b>vtrnq_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Transpose vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&amp;FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn1-transpose-vectors-primary">TRN1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/trn2-transpose-vectors-secondary">TRN2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_s8" type="checkbox"><label for="vzip_s8"><div>int8x8x2_t <b><b>vzip_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_s16" type="checkbox"><label for="vzip_s16"><div>int16x4x2_t <b><b>vzip_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_u8" type="checkbox"><label for="vzip_u8"><div>uint8x8x2_t <b><b>vzip_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_u16" type="checkbox"><label for="vzip_u16"><div>uint16x4x2_t <b><b>vzip_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_p8" type="checkbox"><label for="vzip_p8"><div>poly8x8x2_t <b><b>vzip_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_p16" type="checkbox"><label for="vzip_p16"><div>poly16x4x2_t <b><b>vzip_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_s32" type="checkbox"><label for="vzip_s32"><div>int32x2x2_t <b><b>vzip_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_f32" type="checkbox"><label for="vzip_f32"><div>float32x2x2_t <b><b>vzip_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzip_u32" type="checkbox"><label for="vzip_u32"><div>uint32x2x2_t <b><b>vzip_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_s8" type="checkbox"><label for="vzipq_s8"><div>int8x16x2_t <b><b>vzipq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_s16" type="checkbox"><label for="vzipq_s16"><div>int16x8x2_t <b><b>vzipq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_s32" type="checkbox"><label for="vzipq_s32"><div>int32x4x2_t <b><b>vzipq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_f32" type="checkbox"><label for="vzipq_f32"><div>float32x4x2_t <b><b>vzipq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_u8" type="checkbox"><label for="vzipq_u8"><div>uint8x16x2_t <b><b>vzipq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_u16" type="checkbox"><label for="vzipq_u16"><div>uint16x8x2_t <b><b>vzipq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_u32" type="checkbox"><label for="vzipq_u32"><div>uint32x4x2_t <b><b>vzipq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_p8" type="checkbox"><label for="vzipq_p8"><div>poly8x16x2_t <b><b>vzipq_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vzipq_p16" type="checkbox"><label for="vzipq_p16"><div>poly16x8x2_t <b><b>vzipq_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Zip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&amp;FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&amp;FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip1-zip-vectors-primary">ZIP1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/zip2-zip-vectors-secondary">ZIP2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ integer base = part * pairs;
+ 
+ for p = 0 to pairs-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, base+p, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, base+p, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_s8" type="checkbox"><label for="vuzp_s8"><div>int8x8x2_t <b><b>vuzp_s8</b></b> (int8x8_t a, int8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_s16" type="checkbox"><label for="vuzp_s16"><div>int16x4x2_t <b><b>vuzp_s16</b></b> (int16x4_t a, int16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_s32" type="checkbox"><label for="vuzp_s32"><div>int32x2x2_t <b><b>vuzp_s32</b></b> (int32x2_t a, int32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_f32" type="checkbox"><label for="vuzp_f32"><div>float32x2x2_t <b><b>vuzp_f32</b></b> (float32x2_t a, float32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_u8" type="checkbox"><label for="vuzp_u8"><div>uint8x8x2_t <b><b>vuzp_u8</b></b> (uint8x8_t a, uint8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_u16" type="checkbox"><label for="vuzp_u16"><div>uint16x4x2_t <b><b>vuzp_u16</b></b> (uint16x4_t a, uint16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_u32" type="checkbox"><label for="vuzp_u32"><div>uint32x2x2_t <b><b>vuzp_u32</b></b> (uint32x2_t a, uint32x2_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.2S,Vn.2S,Vm.2S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.2S,Vn.2S,Vm.2S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2S <br />
+ b &rarr; Vm.2S </pre>      <h4>Results</h4>      <pre>Vd1.2S &rarr; result.val[0]
+ Vd2.2S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_p8" type="checkbox"><label for="vuzp_p8"><div>poly8x8x2_t <b><b>vuzp_p8</b></b> (poly8x8_t a, poly8x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.8B,Vn.8B,Vm.8B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.8B,Vn.8B,Vm.8B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8B <br />
+ b &rarr; Vm.8B </pre>      <h4>Results</h4>      <pre>Vd1.8B &rarr; result.val[0]
+ Vd2.8B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzp_p16" type="checkbox"><label for="vuzp_p16"><div>poly16x4x2_t <b><b>vuzp_p16</b></b> (poly16x4_t a, poly16x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.4H,Vn.4H,Vm.4H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.4H,Vn.4H,Vm.4H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4H <br />
+ b &rarr; Vm.4H </pre>      <h4>Results</h4>      <pre>Vd1.4H &rarr; result.val[0]
+ Vd2.4H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_s8" type="checkbox"><label for="vuzpq_s8"><div>int8x16x2_t <b><b>vuzpq_s8</b></b> (int8x16_t a, int8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_s16" type="checkbox"><label for="vuzpq_s16"><div>int16x8x2_t <b><b>vuzpq_s16</b></b> (int16x8_t a, int16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_s32" type="checkbox"><label for="vuzpq_s32"><div>int32x4x2_t <b><b>vuzpq_s32</b></b> (int32x4_t a, int32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_f32" type="checkbox"><label for="vuzpq_f32"><div>float32x4x2_t <b><b>vuzpq_f32</b></b> (float32x4_t a, float32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_u8" type="checkbox"><label for="vuzpq_u8"><div>uint8x16x2_t <b><b>vuzpq_u8</b></b> (uint8x16_t a, uint8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_u16" type="checkbox"><label for="vuzpq_u16"><div>uint16x8x2_t <b><b>vuzpq_u16</b></b> (uint16x8_t a, uint16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_u32" type="checkbox"><label for="vuzpq_u32"><div>uint32x4x2_t <b><b>vuzpq_u32</b></b> (uint32x4_t a, uint32x4_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.4S,Vn.4S,Vm.4S
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.4S <br />
+ b &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd1.4S &rarr; result.val[0]
+ Vd2.4S &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_p8" type="checkbox"><label for="vuzpq_p8"><div>poly8x16x2_t <b><b>vuzpq_p8</b></b> (poly8x16_t a, poly8x16_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.16B,Vn.16B,Vm.16B
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.16B,Vn.16B,Vm.16B
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.16B <br />
+ b &rarr; Vm.16B </pre>      <h4>Results</h4>      <pre>Vd1.16B &rarr; result.val[0]
+ Vd2.16B &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vuzpq_p16" type="checkbox"><label for="vuzpq_p16"><div>poly16x8x2_t <b><b>vuzpq_p16</b></b> (poly16x8_t a, poly16x8_t b)<span class="right">Unzip vectors</span></div></label><article>      <h4>Description</h4><p><p class="aml">Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&amp;FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&amp;FP register.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp1-unzip-vectors-primary">UZP1</a> Vd1.8H,Vn.8H,Vm.8H
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/uzp2-unzip-vectors-secondary">UZP2</a> Vd2.8H,Vn.8H,Vm.8H
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.8H <br />
+ b &rarr; Vm.8H </pre>      <h4>Results</h4>      <pre>Vd1.8H &rarr; result.val[0]
+ Vd2.8H &rarr; result.val[1]
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operandl = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(datasize) operandh = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(datasize) result;
+ 
+ bits(datasize*2) zipped = operandh:operandl;
+ for e = 0 to elements-1
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped, 2*e+part, esize];
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_s8" type="checkbox"><label for="vreinterpret_s16_s8"><div>int16x4_t <b><b>vreinterpret_s16_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_s8" type="checkbox"><label for="vreinterpret_s32_s8"><div>int32x2_t <b><b>vreinterpret_s32_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_s8" type="checkbox"><label for="vreinterpret_f32_s8"><div>float32x2_t <b><b>vreinterpret_f32_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_s8" type="checkbox"><label for="vreinterpret_u8_s8"><div>uint8x8_t <b><b>vreinterpret_u8_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_s8" type="checkbox"><label for="vreinterpret_u16_s8"><div>uint16x4_t <b><b>vreinterpret_u16_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_s8" type="checkbox"><label for="vreinterpret_u32_s8"><div>uint32x2_t <b><b>vreinterpret_u32_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_s8" type="checkbox"><label for="vreinterpret_p8_s8"><div>poly8x8_t <b><b>vreinterpret_p8_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_s8" type="checkbox"><label for="vreinterpret_p16_s8"><div>poly16x4_t <b><b>vreinterpret_p16_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_s8" type="checkbox"><label for="vreinterpret_u64_s8"><div>uint64x1_t <b><b>vreinterpret_u64_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_s8" type="checkbox"><label for="vreinterpret_s64_s8"><div>int64x1_t <b><b>vreinterpret_s64_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_s8" type="checkbox"><label for="vreinterpret_f64_s8"><div>float64x1_t <b><b>vreinterpret_f64_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_s8" type="checkbox"><label for="vreinterpret_p64_s8"><div>poly64x1_t <b><b>vreinterpret_p64_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_s8" type="checkbox"><label for="vreinterpret_f16_s8"><div>float16x4_t <b><b>vreinterpret_f16_s8</b></b> (int8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_s16" type="checkbox"><label for="vreinterpret_s8_s16"><div>int8x8_t <b><b>vreinterpret_s8_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_s16" type="checkbox"><label for="vreinterpret_s32_s16"><div>int32x2_t <b><b>vreinterpret_s32_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_s16" type="checkbox"><label for="vreinterpret_f32_s16"><div>float32x2_t <b><b>vreinterpret_f32_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_s16" type="checkbox"><label for="vreinterpret_u8_s16"><div>uint8x8_t <b><b>vreinterpret_u8_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_s16" type="checkbox"><label for="vreinterpret_u16_s16"><div>uint16x4_t <b><b>vreinterpret_u16_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_s16" type="checkbox"><label for="vreinterpret_u32_s16"><div>uint32x2_t <b><b>vreinterpret_u32_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_s16" type="checkbox"><label for="vreinterpret_p8_s16"><div>poly8x8_t <b><b>vreinterpret_p8_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_s16" type="checkbox"><label for="vreinterpret_p16_s16"><div>poly16x4_t <b><b>vreinterpret_p16_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_s16" type="checkbox"><label for="vreinterpret_u64_s16"><div>uint64x1_t <b><b>vreinterpret_u64_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_s16" type="checkbox"><label for="vreinterpret_s64_s16"><div>int64x1_t <b><b>vreinterpret_s64_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_s16" type="checkbox"><label for="vreinterpret_f64_s16"><div>float64x1_t <b><b>vreinterpret_f64_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_s16" type="checkbox"><label for="vreinterpret_p64_s16"><div>poly64x1_t <b><b>vreinterpret_p64_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_s16" type="checkbox"><label for="vreinterpret_f16_s16"><div>float16x4_t <b><b>vreinterpret_f16_s16</b></b> (int16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_s32" type="checkbox"><label for="vreinterpret_s8_s32"><div>int8x8_t <b><b>vreinterpret_s8_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_s32" type="checkbox"><label for="vreinterpret_s16_s32"><div>int16x4_t <b><b>vreinterpret_s16_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_s32" type="checkbox"><label for="vreinterpret_f32_s32"><div>float32x2_t <b><b>vreinterpret_f32_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_s32" type="checkbox"><label for="vreinterpret_u8_s32"><div>uint8x8_t <b><b>vreinterpret_u8_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_s32" type="checkbox"><label for="vreinterpret_u16_s32"><div>uint16x4_t <b><b>vreinterpret_u16_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_s32" type="checkbox"><label for="vreinterpret_u32_s32"><div>uint32x2_t <b><b>vreinterpret_u32_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_s32" type="checkbox"><label for="vreinterpret_p8_s32"><div>poly8x8_t <b><b>vreinterpret_p8_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_s32" type="checkbox"><label for="vreinterpret_p16_s32"><div>poly16x4_t <b><b>vreinterpret_p16_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_s32" type="checkbox"><label for="vreinterpret_u64_s32"><div>uint64x1_t <b><b>vreinterpret_u64_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_s32" type="checkbox"><label for="vreinterpret_s64_s32"><div>int64x1_t <b><b>vreinterpret_s64_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_s32" type="checkbox"><label for="vreinterpret_f64_s32"><div>float64x1_t <b><b>vreinterpret_f64_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_s32" type="checkbox"><label for="vreinterpret_p64_s32"><div>poly64x1_t <b><b>vreinterpret_p64_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_s32" type="checkbox"><label for="vreinterpret_f16_s32"><div>float16x4_t <b><b>vreinterpret_f16_s32</b></b> (int32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_f32" type="checkbox"><label for="vreinterpret_s8_f32"><div>int8x8_t <b><b>vreinterpret_s8_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_f32" type="checkbox"><label for="vreinterpret_s16_f32"><div>int16x4_t <b><b>vreinterpret_s16_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_f32" type="checkbox"><label for="vreinterpret_s32_f32"><div>int32x2_t <b><b>vreinterpret_s32_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_f32" type="checkbox"><label for="vreinterpret_u8_f32"><div>uint8x8_t <b><b>vreinterpret_u8_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_f32" type="checkbox"><label for="vreinterpret_u16_f32"><div>uint16x4_t <b><b>vreinterpret_u16_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_f32" type="checkbox"><label for="vreinterpret_u32_f32"><div>uint32x2_t <b><b>vreinterpret_u32_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_f32" type="checkbox"><label for="vreinterpret_p8_f32"><div>poly8x8_t <b><b>vreinterpret_p8_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_f32" type="checkbox"><label for="vreinterpret_p16_f32"><div>poly16x4_t <b><b>vreinterpret_p16_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_f32" type="checkbox"><label for="vreinterpret_u64_f32"><div>uint64x1_t <b><b>vreinterpret_u64_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_f32" type="checkbox"><label for="vreinterpret_s64_f32"><div>int64x1_t <b><b>vreinterpret_s64_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_f32" type="checkbox"><label for="vreinterpret_f64_f32"><div>float64x1_t <b><b>vreinterpret_f64_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_f32" type="checkbox"><label for="vreinterpret_p64_f32"><div>poly64x1_t <b><b>vreinterpret_p64_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_f64" type="checkbox"><label for="vreinterpret_p64_f64"><div>poly64x1_t <b><b>vreinterpret_p64_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_f32" type="checkbox"><label for="vreinterpret_f16_f32"><div>float16x4_t <b><b>vreinterpret_f16_f32</b></b> (float32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_u8" type="checkbox"><label for="vreinterpret_s8_u8"><div>int8x8_t <b><b>vreinterpret_s8_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_u8" type="checkbox"><label for="vreinterpret_s16_u8"><div>int16x4_t <b><b>vreinterpret_s16_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_u8" type="checkbox"><label for="vreinterpret_s32_u8"><div>int32x2_t <b><b>vreinterpret_s32_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_u8" type="checkbox"><label for="vreinterpret_f32_u8"><div>float32x2_t <b><b>vreinterpret_f32_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_u8" type="checkbox"><label for="vreinterpret_u16_u8"><div>uint16x4_t <b><b>vreinterpret_u16_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_u8" type="checkbox"><label for="vreinterpret_u32_u8"><div>uint32x2_t <b><b>vreinterpret_u32_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_u8" type="checkbox"><label for="vreinterpret_p8_u8"><div>poly8x8_t <b><b>vreinterpret_p8_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_u8" type="checkbox"><label for="vreinterpret_p16_u8"><div>poly16x4_t <b><b>vreinterpret_p16_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_u8" type="checkbox"><label for="vreinterpret_u64_u8"><div>uint64x1_t <b><b>vreinterpret_u64_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_u8" type="checkbox"><label for="vreinterpret_s64_u8"><div>int64x1_t <b><b>vreinterpret_s64_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_u8" type="checkbox"><label for="vreinterpret_f64_u8"><div>float64x1_t <b><b>vreinterpret_f64_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_u8" type="checkbox"><label for="vreinterpret_p64_u8"><div>poly64x1_t <b><b>vreinterpret_p64_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_u8" type="checkbox"><label for="vreinterpret_f16_u8"><div>float16x4_t <b><b>vreinterpret_f16_u8</b></b> (uint8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_u16" type="checkbox"><label for="vreinterpret_s8_u16"><div>int8x8_t <b><b>vreinterpret_s8_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_u16" type="checkbox"><label for="vreinterpret_s16_u16"><div>int16x4_t <b><b>vreinterpret_s16_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_u16" type="checkbox"><label for="vreinterpret_s32_u16"><div>int32x2_t <b><b>vreinterpret_s32_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_u16" type="checkbox"><label for="vreinterpret_f32_u16"><div>float32x2_t <b><b>vreinterpret_f32_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_u16" type="checkbox"><label for="vreinterpret_u8_u16"><div>uint8x8_t <b><b>vreinterpret_u8_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_u16" type="checkbox"><label for="vreinterpret_u32_u16"><div>uint32x2_t <b><b>vreinterpret_u32_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_u16" type="checkbox"><label for="vreinterpret_p8_u16"><div>poly8x8_t <b><b>vreinterpret_p8_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_u16" type="checkbox"><label for="vreinterpret_p16_u16"><div>poly16x4_t <b><b>vreinterpret_p16_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_u16" type="checkbox"><label for="vreinterpret_u64_u16"><div>uint64x1_t <b><b>vreinterpret_u64_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_u16" type="checkbox"><label for="vreinterpret_s64_u16"><div>int64x1_t <b><b>vreinterpret_s64_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_u16" type="checkbox"><label for="vreinterpret_f64_u16"><div>float64x1_t <b><b>vreinterpret_f64_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_u16" type="checkbox"><label for="vreinterpret_p64_u16"><div>poly64x1_t <b><b>vreinterpret_p64_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_u16" type="checkbox"><label for="vreinterpret_f16_u16"><div>float16x4_t <b><b>vreinterpret_f16_u16</b></b> (uint16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_u32" type="checkbox"><label for="vreinterpret_s8_u32"><div>int8x8_t <b><b>vreinterpret_s8_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_u32" type="checkbox"><label for="vreinterpret_s16_u32"><div>int16x4_t <b><b>vreinterpret_s16_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_u32" type="checkbox"><label for="vreinterpret_s32_u32"><div>int32x2_t <b><b>vreinterpret_s32_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_u32" type="checkbox"><label for="vreinterpret_f32_u32"><div>float32x2_t <b><b>vreinterpret_f32_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_u32" type="checkbox"><label for="vreinterpret_u8_u32"><div>uint8x8_t <b><b>vreinterpret_u8_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_u32" type="checkbox"><label for="vreinterpret_u16_u32"><div>uint16x4_t <b><b>vreinterpret_u16_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_u32" type="checkbox"><label for="vreinterpret_p8_u32"><div>poly8x8_t <b><b>vreinterpret_p8_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_u32" type="checkbox"><label for="vreinterpret_p16_u32"><div>poly16x4_t <b><b>vreinterpret_p16_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_u32" type="checkbox"><label for="vreinterpret_u64_u32"><div>uint64x1_t <b><b>vreinterpret_u64_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_u32" type="checkbox"><label for="vreinterpret_s64_u32"><div>int64x1_t <b><b>vreinterpret_s64_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_u32" type="checkbox"><label for="vreinterpret_f64_u32"><div>float64x1_t <b><b>vreinterpret_f64_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_u32" type="checkbox"><label for="vreinterpret_p64_u32"><div>poly64x1_t <b><b>vreinterpret_p64_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_u32" type="checkbox"><label for="vreinterpret_f16_u32"><div>float16x4_t <b><b>vreinterpret_f16_u32</b></b> (uint32x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2S </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_p8" type="checkbox"><label for="vreinterpret_s8_p8"><div>int8x8_t <b><b>vreinterpret_s8_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_p8" type="checkbox"><label for="vreinterpret_s16_p8"><div>int16x4_t <b><b>vreinterpret_s16_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_p8" type="checkbox"><label for="vreinterpret_s32_p8"><div>int32x2_t <b><b>vreinterpret_s32_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_p8" type="checkbox"><label for="vreinterpret_f32_p8"><div>float32x2_t <b><b>vreinterpret_f32_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_p8" type="checkbox"><label for="vreinterpret_u8_p8"><div>uint8x8_t <b><b>vreinterpret_u8_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_p8" type="checkbox"><label for="vreinterpret_u16_p8"><div>uint16x4_t <b><b>vreinterpret_u16_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_p8" type="checkbox"><label for="vreinterpret_u32_p8"><div>uint32x2_t <b><b>vreinterpret_u32_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_p8" type="checkbox"><label for="vreinterpret_p16_p8"><div>poly16x4_t <b><b>vreinterpret_p16_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_p8" type="checkbox"><label for="vreinterpret_u64_p8"><div>uint64x1_t <b><b>vreinterpret_u64_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_p8" type="checkbox"><label for="vreinterpret_s64_p8"><div>int64x1_t <b><b>vreinterpret_s64_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_p8" type="checkbox"><label for="vreinterpret_f64_p8"><div>float64x1_t <b><b>vreinterpret_f64_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_p8" type="checkbox"><label for="vreinterpret_p64_p8"><div>poly64x1_t <b><b>vreinterpret_p64_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_p8" type="checkbox"><label for="vreinterpret_f16_p8"><div>float16x4_t <b><b>vreinterpret_f16_p8</b></b> (poly8x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8B </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_p16" type="checkbox"><label for="vreinterpret_s8_p16"><div>int8x8_t <b><b>vreinterpret_s8_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_p16" type="checkbox"><label for="vreinterpret_s16_p16"><div>int16x4_t <b><b>vreinterpret_s16_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_p16" type="checkbox"><label for="vreinterpret_s32_p16"><div>int32x2_t <b><b>vreinterpret_s32_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_p16" type="checkbox"><label for="vreinterpret_f32_p16"><div>float32x2_t <b><b>vreinterpret_f32_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_p16" type="checkbox"><label for="vreinterpret_u8_p16"><div>uint8x8_t <b><b>vreinterpret_u8_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_p16" type="checkbox"><label for="vreinterpret_u16_p16"><div>uint16x4_t <b><b>vreinterpret_u16_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_p16" type="checkbox"><label for="vreinterpret_u32_p16"><div>uint32x2_t <b><b>vreinterpret_u32_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_p16" type="checkbox"><label for="vreinterpret_p8_p16"><div>poly8x8_t <b><b>vreinterpret_p8_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_p16" type="checkbox"><label for="vreinterpret_u64_p16"><div>uint64x1_t <b><b>vreinterpret_u64_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_p16" type="checkbox"><label for="vreinterpret_s64_p16"><div>int64x1_t <b><b>vreinterpret_s64_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_p16" type="checkbox"><label for="vreinterpret_f64_p16"><div>float64x1_t <b><b>vreinterpret_f64_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_p16" type="checkbox"><label for="vreinterpret_p64_p16"><div>poly64x1_t <b><b>vreinterpret_p64_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_p16" type="checkbox"><label for="vreinterpret_f16_p16"><div>float16x4_t <b><b>vreinterpret_f16_p16</b></b> (poly16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_u64" type="checkbox"><label for="vreinterpret_s8_u64"><div>int8x8_t <b><b>vreinterpret_s8_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_u64" type="checkbox"><label for="vreinterpret_s16_u64"><div>int16x4_t <b><b>vreinterpret_s16_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_u64" type="checkbox"><label for="vreinterpret_s32_u64"><div>int32x2_t <b><b>vreinterpret_s32_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_u64" type="checkbox"><label for="vreinterpret_f32_u64"><div>float32x2_t <b><b>vreinterpret_f32_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_u64" type="checkbox"><label for="vreinterpret_u8_u64"><div>uint8x8_t <b><b>vreinterpret_u8_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_u64" type="checkbox"><label for="vreinterpret_u16_u64"><div>uint16x4_t <b><b>vreinterpret_u16_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_u64" type="checkbox"><label for="vreinterpret_u32_u64"><div>uint32x2_t <b><b>vreinterpret_u32_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_u64" type="checkbox"><label for="vreinterpret_p8_u64"><div>poly8x8_t <b><b>vreinterpret_p8_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_u64" type="checkbox"><label for="vreinterpret_p16_u64"><div>poly16x4_t <b><b>vreinterpret_p16_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_u64" type="checkbox"><label for="vreinterpret_s64_u64"><div>int64x1_t <b><b>vreinterpret_s64_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_u64" type="checkbox"><label for="vreinterpret_f64_u64"><div>float64x1_t <b><b>vreinterpret_f64_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_u64" type="checkbox"><label for="vreinterpret_p64_u64"><div>poly64x1_t <b><b>vreinterpret_p64_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_u64" type="checkbox"><label for="vreinterpret_f16_u64"><div>float16x4_t <b><b>vreinterpret_f16_u64</b></b> (uint64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_s64" type="checkbox"><label for="vreinterpret_s8_s64"><div>int8x8_t <b><b>vreinterpret_s8_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_s64" type="checkbox"><label for="vreinterpret_s16_s64"><div>int16x4_t <b><b>vreinterpret_s16_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_s64" type="checkbox"><label for="vreinterpret_s32_s64"><div>int32x2_t <b><b>vreinterpret_s32_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_s64" type="checkbox"><label for="vreinterpret_f32_s64"><div>float32x2_t <b><b>vreinterpret_f32_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_s64" type="checkbox"><label for="vreinterpret_u8_s64"><div>uint8x8_t <b><b>vreinterpret_u8_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_s64" type="checkbox"><label for="vreinterpret_u16_s64"><div>uint16x4_t <b><b>vreinterpret_u16_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_s64" type="checkbox"><label for="vreinterpret_u32_s64"><div>uint32x2_t <b><b>vreinterpret_u32_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_s64" type="checkbox"><label for="vreinterpret_p8_s64"><div>poly8x8_t <b><b>vreinterpret_p8_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_s64" type="checkbox"><label for="vreinterpret_p16_s64"><div>poly16x4_t <b><b>vreinterpret_p16_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_s64" type="checkbox"><label for="vreinterpret_u64_s64"><div>uint64x1_t <b><b>vreinterpret_u64_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_s64" type="checkbox"><label for="vreinterpret_f64_s64"><div>float64x1_t <b><b>vreinterpret_f64_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_p64" type="checkbox"><label for="vreinterpret_u64_p64"><div>uint64x1_t <b><b>vreinterpret_u64_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_s64" type="checkbox"><label for="vreinterpret_f16_s64"><div>float16x4_t <b><b>vreinterpret_f16_s64</b></b> (int64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_f16" type="checkbox"><label for="vreinterpret_s8_f16"><div>int8x8_t <b><b>vreinterpret_s8_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_f16" type="checkbox"><label for="vreinterpret_s16_f16"><div>int16x4_t <b><b>vreinterpret_s16_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_f16" type="checkbox"><label for="vreinterpret_s32_f16"><div>int32x2_t <b><b>vreinterpret_s32_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_f16" type="checkbox"><label for="vreinterpret_f32_f16"><div>float32x2_t <b><b>vreinterpret_f32_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_f16" type="checkbox"><label for="vreinterpret_u8_f16"><div>uint8x8_t <b><b>vreinterpret_u8_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_f16" type="checkbox"><label for="vreinterpret_u16_f16"><div>uint16x4_t <b><b>vreinterpret_u16_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_f16" type="checkbox"><label for="vreinterpret_u32_f16"><div>uint32x2_t <b><b>vreinterpret_u32_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_f16" type="checkbox"><label for="vreinterpret_p8_f16"><div>poly8x8_t <b><b>vreinterpret_p8_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_f16" type="checkbox"><label for="vreinterpret_p16_f16"><div>poly16x4_t <b><b>vreinterpret_p16_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_f16" type="checkbox"><label for="vreinterpret_u64_f16"><div>uint64x1_t <b><b>vreinterpret_u64_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_f16" type="checkbox"><label for="vreinterpret_s64_f16"><div>int64x1_t <b><b>vreinterpret_s64_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_f16" type="checkbox"><label for="vreinterpret_f64_f16"><div>float64x1_t <b><b>vreinterpret_f64_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p64_f16" type="checkbox"><label for="vreinterpret_p64_f16"><div>poly64x1_t <b><b>vreinterpret_p64_f16</b></b> (float16x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4H </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_s8" type="checkbox"><label for="vreinterpretq_s16_s8"><div>int16x8_t <b><b>vreinterpretq_s16_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_s8" type="checkbox"><label for="vreinterpretq_s32_s8"><div>int32x4_t <b><b>vreinterpretq_s32_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_s8" type="checkbox"><label for="vreinterpretq_f32_s8"><div>float32x4_t <b><b>vreinterpretq_f32_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_s8" type="checkbox"><label for="vreinterpretq_u8_s8"><div>uint8x16_t <b><b>vreinterpretq_u8_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_s8" type="checkbox"><label for="vreinterpretq_u16_s8"><div>uint16x8_t <b><b>vreinterpretq_u16_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_s8" type="checkbox"><label for="vreinterpretq_u32_s8"><div>uint32x4_t <b><b>vreinterpretq_u32_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_s8" type="checkbox"><label for="vreinterpretq_p8_s8"><div>poly8x16_t <b><b>vreinterpretq_p8_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_s8" type="checkbox"><label for="vreinterpretq_p16_s8"><div>poly16x8_t <b><b>vreinterpretq_p16_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_s8" type="checkbox"><label for="vreinterpretq_u64_s8"><div>uint64x2_t <b><b>vreinterpretq_u64_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_s8" type="checkbox"><label for="vreinterpretq_s64_s8"><div>int64x2_t <b><b>vreinterpretq_s64_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_s8" type="checkbox"><label for="vreinterpretq_f64_s8"><div>float64x2_t <b><b>vreinterpretq_f64_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_s8" type="checkbox"><label for="vreinterpretq_p64_s8"><div>poly64x2_t <b><b>vreinterpretq_p64_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_s8" type="checkbox"><label for="vreinterpretq_p128_s8"><div>poly128_t <b><b>vreinterpretq_p128_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_s8" type="checkbox"><label for="vreinterpretq_f16_s8"><div>float16x8_t <b><b>vreinterpretq_f16_s8</b></b> (int8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_s16" type="checkbox"><label for="vreinterpretq_s8_s16"><div>int8x16_t <b><b>vreinterpretq_s8_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_s16" type="checkbox"><label for="vreinterpretq_s32_s16"><div>int32x4_t <b><b>vreinterpretq_s32_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_s16" type="checkbox"><label for="vreinterpretq_f32_s16"><div>float32x4_t <b><b>vreinterpretq_f32_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_s16" type="checkbox"><label for="vreinterpretq_u8_s16"><div>uint8x16_t <b><b>vreinterpretq_u8_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_s16" type="checkbox"><label for="vreinterpretq_u16_s16"><div>uint16x8_t <b><b>vreinterpretq_u16_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_s16" type="checkbox"><label for="vreinterpretq_u32_s16"><div>uint32x4_t <b><b>vreinterpretq_u32_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_s16" type="checkbox"><label for="vreinterpretq_p8_s16"><div>poly8x16_t <b><b>vreinterpretq_p8_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_s16" type="checkbox"><label for="vreinterpretq_p16_s16"><div>poly16x8_t <b><b>vreinterpretq_p16_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_s16" type="checkbox"><label for="vreinterpretq_u64_s16"><div>uint64x2_t <b><b>vreinterpretq_u64_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_s16" type="checkbox"><label for="vreinterpretq_s64_s16"><div>int64x2_t <b><b>vreinterpretq_s64_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_s16" type="checkbox"><label for="vreinterpretq_f64_s16"><div>float64x2_t <b><b>vreinterpretq_f64_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_s16" type="checkbox"><label for="vreinterpretq_p64_s16"><div>poly64x2_t <b><b>vreinterpretq_p64_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_s16" type="checkbox"><label for="vreinterpretq_p128_s16"><div>poly128_t <b><b>vreinterpretq_p128_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_s16" type="checkbox"><label for="vreinterpretq_f16_s16"><div>float16x8_t <b><b>vreinterpretq_f16_s16</b></b> (int16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_s32" type="checkbox"><label for="vreinterpretq_s8_s32"><div>int8x16_t <b><b>vreinterpretq_s8_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_s32" type="checkbox"><label for="vreinterpretq_s16_s32"><div>int16x8_t <b><b>vreinterpretq_s16_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_s32" type="checkbox"><label for="vreinterpretq_f32_s32"><div>float32x4_t <b><b>vreinterpretq_f32_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_s32" type="checkbox"><label for="vreinterpretq_u8_s32"><div>uint8x16_t <b><b>vreinterpretq_u8_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_s32" type="checkbox"><label for="vreinterpretq_u16_s32"><div>uint16x8_t <b><b>vreinterpretq_u16_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_s32" type="checkbox"><label for="vreinterpretq_u32_s32"><div>uint32x4_t <b><b>vreinterpretq_u32_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_s32" type="checkbox"><label for="vreinterpretq_p8_s32"><div>poly8x16_t <b><b>vreinterpretq_p8_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_s32" type="checkbox"><label for="vreinterpretq_p16_s32"><div>poly16x8_t <b><b>vreinterpretq_p16_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_s32" type="checkbox"><label for="vreinterpretq_u64_s32"><div>uint64x2_t <b><b>vreinterpretq_u64_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_s32" type="checkbox"><label for="vreinterpretq_s64_s32"><div>int64x2_t <b><b>vreinterpretq_s64_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_s32" type="checkbox"><label for="vreinterpretq_f64_s32"><div>float64x2_t <b><b>vreinterpretq_f64_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_s32" type="checkbox"><label for="vreinterpretq_p64_s32"><div>poly64x2_t <b><b>vreinterpretq_p64_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_s32" type="checkbox"><label for="vreinterpretq_p128_s32"><div>poly128_t <b><b>vreinterpretq_p128_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_s32" type="checkbox"><label for="vreinterpretq_f16_s32"><div>float16x8_t <b><b>vreinterpretq_f16_s32</b></b> (int32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_f32" type="checkbox"><label for="vreinterpretq_s8_f32"><div>int8x16_t <b><b>vreinterpretq_s8_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_f32" type="checkbox"><label for="vreinterpretq_s16_f32"><div>int16x8_t <b><b>vreinterpretq_s16_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_f32" type="checkbox"><label for="vreinterpretq_s32_f32"><div>int32x4_t <b><b>vreinterpretq_s32_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_f32" type="checkbox"><label for="vreinterpretq_u8_f32"><div>uint8x16_t <b><b>vreinterpretq_u8_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_f32" type="checkbox"><label for="vreinterpretq_u16_f32"><div>uint16x8_t <b><b>vreinterpretq_u16_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_f32" type="checkbox"><label for="vreinterpretq_u32_f32"><div>uint32x4_t <b><b>vreinterpretq_u32_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_f32" type="checkbox"><label for="vreinterpretq_p8_f32"><div>poly8x16_t <b><b>vreinterpretq_p8_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_f32" type="checkbox"><label for="vreinterpretq_p16_f32"><div>poly16x8_t <b><b>vreinterpretq_p16_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_f32" type="checkbox"><label for="vreinterpretq_u64_f32"><div>uint64x2_t <b><b>vreinterpretq_u64_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_f32" type="checkbox"><label for="vreinterpretq_s64_f32"><div>int64x2_t <b><b>vreinterpretq_s64_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_f32" type="checkbox"><label for="vreinterpretq_f64_f32"><div>float64x2_t <b><b>vreinterpretq_f64_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_f32" type="checkbox"><label for="vreinterpretq_p64_f32"><div>poly64x2_t <b><b>vreinterpretq_p64_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_f32" type="checkbox"><label for="vreinterpretq_p128_f32"><div>poly128_t <b><b>vreinterpretq_p128_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_f64" type="checkbox"><label for="vreinterpretq_p64_f64"><div>poly64x2_t <b><b>vreinterpretq_p64_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_f64" type="checkbox"><label for="vreinterpretq_p128_f64"><div>poly128_t <b><b>vreinterpretq_p128_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_f32" type="checkbox"><label for="vreinterpretq_f16_f32"><div>float16x8_t <b><b>vreinterpretq_f16_f32</b></b> (float32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_u8" type="checkbox"><label for="vreinterpretq_s8_u8"><div>int8x16_t <b><b>vreinterpretq_s8_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_u8" type="checkbox"><label for="vreinterpretq_s16_u8"><div>int16x8_t <b><b>vreinterpretq_s16_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_u8" type="checkbox"><label for="vreinterpretq_s32_u8"><div>int32x4_t <b><b>vreinterpretq_s32_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_u8" type="checkbox"><label for="vreinterpretq_f32_u8"><div>float32x4_t <b><b>vreinterpretq_f32_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_u8" type="checkbox"><label for="vreinterpretq_u16_u8"><div>uint16x8_t <b><b>vreinterpretq_u16_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_u8" type="checkbox"><label for="vreinterpretq_u32_u8"><div>uint32x4_t <b><b>vreinterpretq_u32_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_u8" type="checkbox"><label for="vreinterpretq_p8_u8"><div>poly8x16_t <b><b>vreinterpretq_p8_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_u8" type="checkbox"><label for="vreinterpretq_p16_u8"><div>poly16x8_t <b><b>vreinterpretq_p16_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_u8" type="checkbox"><label for="vreinterpretq_u64_u8"><div>uint64x2_t <b><b>vreinterpretq_u64_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_u8" type="checkbox"><label for="vreinterpretq_s64_u8"><div>int64x2_t <b><b>vreinterpretq_s64_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_u8" type="checkbox"><label for="vreinterpretq_f64_u8"><div>float64x2_t <b><b>vreinterpretq_f64_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_u8" type="checkbox"><label for="vreinterpretq_p64_u8"><div>poly64x2_t <b><b>vreinterpretq_p64_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_u8" type="checkbox"><label for="vreinterpretq_p128_u8"><div>poly128_t <b><b>vreinterpretq_p128_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_u8" type="checkbox"><label for="vreinterpretq_f16_u8"><div>float16x8_t <b><b>vreinterpretq_f16_u8</b></b> (uint8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_u16" type="checkbox"><label for="vreinterpretq_s8_u16"><div>int8x16_t <b><b>vreinterpretq_s8_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_u16" type="checkbox"><label for="vreinterpretq_s16_u16"><div>int16x8_t <b><b>vreinterpretq_s16_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_u16" type="checkbox"><label for="vreinterpretq_s32_u16"><div>int32x4_t <b><b>vreinterpretq_s32_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_u16" type="checkbox"><label for="vreinterpretq_f32_u16"><div>float32x4_t <b><b>vreinterpretq_f32_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_u16" type="checkbox"><label for="vreinterpretq_u8_u16"><div>uint8x16_t <b><b>vreinterpretq_u8_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_u16" type="checkbox"><label for="vreinterpretq_u32_u16"><div>uint32x4_t <b><b>vreinterpretq_u32_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_u16" type="checkbox"><label for="vreinterpretq_p8_u16"><div>poly8x16_t <b><b>vreinterpretq_p8_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_u16" type="checkbox"><label for="vreinterpretq_p16_u16"><div>poly16x8_t <b><b>vreinterpretq_p16_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_u16" type="checkbox"><label for="vreinterpretq_u64_u16"><div>uint64x2_t <b><b>vreinterpretq_u64_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_u16" type="checkbox"><label for="vreinterpretq_s64_u16"><div>int64x2_t <b><b>vreinterpretq_s64_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_u16" type="checkbox"><label for="vreinterpretq_f64_u16"><div>float64x2_t <b><b>vreinterpretq_f64_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_u16" type="checkbox"><label for="vreinterpretq_p64_u16"><div>poly64x2_t <b><b>vreinterpretq_p64_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_u16" type="checkbox"><label for="vreinterpretq_p128_u16"><div>poly128_t <b><b>vreinterpretq_p128_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_u16" type="checkbox"><label for="vreinterpretq_f16_u16"><div>float16x8_t <b><b>vreinterpretq_f16_u16</b></b> (uint16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_u32" type="checkbox"><label for="vreinterpretq_s8_u32"><div>int8x16_t <b><b>vreinterpretq_s8_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_u32" type="checkbox"><label for="vreinterpretq_s16_u32"><div>int16x8_t <b><b>vreinterpretq_s16_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_u32" type="checkbox"><label for="vreinterpretq_s32_u32"><div>int32x4_t <b><b>vreinterpretq_s32_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_u32" type="checkbox"><label for="vreinterpretq_f32_u32"><div>float32x4_t <b><b>vreinterpretq_f32_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_u32" type="checkbox"><label for="vreinterpretq_u8_u32"><div>uint8x16_t <b><b>vreinterpretq_u8_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_u32" type="checkbox"><label for="vreinterpretq_u16_u32"><div>uint16x8_t <b><b>vreinterpretq_u16_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_u32" type="checkbox"><label for="vreinterpretq_p8_u32"><div>poly8x16_t <b><b>vreinterpretq_p8_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_u32" type="checkbox"><label for="vreinterpretq_p16_u32"><div>poly16x8_t <b><b>vreinterpretq_p16_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_u32" type="checkbox"><label for="vreinterpretq_u64_u32"><div>uint64x2_t <b><b>vreinterpretq_u64_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_u32" type="checkbox"><label for="vreinterpretq_s64_u32"><div>int64x2_t <b><b>vreinterpretq_s64_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_u32" type="checkbox"><label for="vreinterpretq_f64_u32"><div>float64x2_t <b><b>vreinterpretq_f64_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_u32" type="checkbox"><label for="vreinterpretq_p64_u32"><div>poly64x2_t <b><b>vreinterpretq_p64_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_u32" type="checkbox"><label for="vreinterpretq_p128_u32"><div>poly128_t <b><b>vreinterpretq_p128_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_u32" type="checkbox"><label for="vreinterpretq_f16_u32"><div>float16x8_t <b><b>vreinterpretq_f16_u32</b></b> (uint32x4_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.4S </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_p8" type="checkbox"><label for="vreinterpretq_s8_p8"><div>int8x16_t <b><b>vreinterpretq_s8_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_p8" type="checkbox"><label for="vreinterpretq_s16_p8"><div>int16x8_t <b><b>vreinterpretq_s16_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_p8" type="checkbox"><label for="vreinterpretq_s32_p8"><div>int32x4_t <b><b>vreinterpretq_s32_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_p8" type="checkbox"><label for="vreinterpretq_f32_p8"><div>float32x4_t <b><b>vreinterpretq_f32_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_p8" type="checkbox"><label for="vreinterpretq_u8_p8"><div>uint8x16_t <b><b>vreinterpretq_u8_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_p8" type="checkbox"><label for="vreinterpretq_u16_p8"><div>uint16x8_t <b><b>vreinterpretq_u16_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_p8" type="checkbox"><label for="vreinterpretq_u32_p8"><div>uint32x4_t <b><b>vreinterpretq_u32_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_p8" type="checkbox"><label for="vreinterpretq_p16_p8"><div>poly16x8_t <b><b>vreinterpretq_p16_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_p8" type="checkbox"><label for="vreinterpretq_u64_p8"><div>uint64x2_t <b><b>vreinterpretq_u64_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_p8" type="checkbox"><label for="vreinterpretq_s64_p8"><div>int64x2_t <b><b>vreinterpretq_s64_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_p8" type="checkbox"><label for="vreinterpretq_f64_p8"><div>float64x2_t <b><b>vreinterpretq_f64_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_p8" type="checkbox"><label for="vreinterpretq_p64_p8"><div>poly64x2_t <b><b>vreinterpretq_p64_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_p8" type="checkbox"><label for="vreinterpretq_p128_p8"><div>poly128_t <b><b>vreinterpretq_p128_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_p8" type="checkbox"><label for="vreinterpretq_f16_p8"><div>float16x8_t <b><b>vreinterpretq_f16_p8</b></b> (poly8x16_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.16B </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_p16" type="checkbox"><label for="vreinterpretq_s8_p16"><div>int8x16_t <b><b>vreinterpretq_s8_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_p16" type="checkbox"><label for="vreinterpretq_s16_p16"><div>int16x8_t <b><b>vreinterpretq_s16_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_p16" type="checkbox"><label for="vreinterpretq_s32_p16"><div>int32x4_t <b><b>vreinterpretq_s32_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_p16" type="checkbox"><label for="vreinterpretq_f32_p16"><div>float32x4_t <b><b>vreinterpretq_f32_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_p16" type="checkbox"><label for="vreinterpretq_u8_p16"><div>uint8x16_t <b><b>vreinterpretq_u8_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_p16" type="checkbox"><label for="vreinterpretq_u16_p16"><div>uint16x8_t <b><b>vreinterpretq_u16_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_p16" type="checkbox"><label for="vreinterpretq_u32_p16"><div>uint32x4_t <b><b>vreinterpretq_u32_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_p16" type="checkbox"><label for="vreinterpretq_p8_p16"><div>poly8x16_t <b><b>vreinterpretq_p8_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_p16" type="checkbox"><label for="vreinterpretq_u64_p16"><div>uint64x2_t <b><b>vreinterpretq_u64_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_p16" type="checkbox"><label for="vreinterpretq_s64_p16"><div>int64x2_t <b><b>vreinterpretq_s64_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_p16" type="checkbox"><label for="vreinterpretq_f64_p16"><div>float64x2_t <b><b>vreinterpretq_f64_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_p16" type="checkbox"><label for="vreinterpretq_p64_p16"><div>poly64x2_t <b><b>vreinterpretq_p64_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_p16" type="checkbox"><label for="vreinterpretq_p128_p16"><div>poly128_t <b><b>vreinterpretq_p128_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_p16" type="checkbox"><label for="vreinterpretq_f16_p16"><div>float16x8_t <b><b>vreinterpretq_f16_p16</b></b> (poly16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_u64" type="checkbox"><label for="vreinterpretq_s8_u64"><div>int8x16_t <b><b>vreinterpretq_s8_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_u64" type="checkbox"><label for="vreinterpretq_s16_u64"><div>int16x8_t <b><b>vreinterpretq_s16_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_u64" type="checkbox"><label for="vreinterpretq_s32_u64"><div>int32x4_t <b><b>vreinterpretq_s32_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_u64" type="checkbox"><label for="vreinterpretq_f32_u64"><div>float32x4_t <b><b>vreinterpretq_f32_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_u64" type="checkbox"><label for="vreinterpretq_u8_u64"><div>uint8x16_t <b><b>vreinterpretq_u8_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_u64" type="checkbox"><label for="vreinterpretq_u16_u64"><div>uint16x8_t <b><b>vreinterpretq_u16_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_u64" type="checkbox"><label for="vreinterpretq_u32_u64"><div>uint32x4_t <b><b>vreinterpretq_u32_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_u64" type="checkbox"><label for="vreinterpretq_p8_u64"><div>poly8x16_t <b><b>vreinterpretq_p8_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_u64" type="checkbox"><label for="vreinterpretq_p16_u64"><div>poly16x8_t <b><b>vreinterpretq_p16_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_u64" type="checkbox"><label for="vreinterpretq_s64_u64"><div>int64x2_t <b><b>vreinterpretq_s64_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_u64" type="checkbox"><label for="vreinterpretq_f64_u64"><div>float64x2_t <b><b>vreinterpretq_f64_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_s64" type="checkbox"><label for="vreinterpretq_f64_s64"><div>float64x2_t <b><b>vreinterpretq_f64_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_s64" type="checkbox"><label for="vreinterpretq_p64_s64"><div>poly64x2_t <b><b>vreinterpretq_p64_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_s64" type="checkbox"><label for="vreinterpretq_p128_s64"><div>poly128_t <b><b>vreinterpretq_p128_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_u64" type="checkbox"><label for="vreinterpretq_p64_u64"><div>poly64x2_t <b><b>vreinterpretq_p64_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_u64" type="checkbox"><label for="vreinterpretq_p128_u64"><div>poly128_t <b><b>vreinterpretq_p128_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_u64" type="checkbox"><label for="vreinterpretq_f16_u64"><div>float16x8_t <b><b>vreinterpretq_f16_u64</b></b> (uint64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_s64" type="checkbox"><label for="vreinterpretq_s8_s64"><div>int8x16_t <b><b>vreinterpretq_s8_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_s64" type="checkbox"><label for="vreinterpretq_s16_s64"><div>int16x8_t <b><b>vreinterpretq_s16_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_s64" type="checkbox"><label for="vreinterpretq_s32_s64"><div>int32x4_t <b><b>vreinterpretq_s32_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_s64" type="checkbox"><label for="vreinterpretq_f32_s64"><div>float32x4_t <b><b>vreinterpretq_f32_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_s64" type="checkbox"><label for="vreinterpretq_u8_s64"><div>uint8x16_t <b><b>vreinterpretq_u8_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_s64" type="checkbox"><label for="vreinterpretq_u16_s64"><div>uint16x8_t <b><b>vreinterpretq_u16_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_s64" type="checkbox"><label for="vreinterpretq_u32_s64"><div>uint32x4_t <b><b>vreinterpretq_u32_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_s64" type="checkbox"><label for="vreinterpretq_p8_s64"><div>poly8x16_t <b><b>vreinterpretq_p8_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_s64" type="checkbox"><label for="vreinterpretq_p16_s64"><div>poly16x8_t <b><b>vreinterpretq_p16_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_s64" type="checkbox"><label for="vreinterpretq_u64_s64"><div>uint64x2_t <b><b>vreinterpretq_u64_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_p64" type="checkbox"><label for="vreinterpretq_u64_p64"><div>uint64x2_t <b><b>vreinterpretq_u64_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_s64" type="checkbox"><label for="vreinterpretq_f16_s64"><div>float16x8_t <b><b>vreinterpretq_f16_s64</b></b> (int64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_f16" type="checkbox"><label for="vreinterpretq_s8_f16"><div>int8x16_t <b><b>vreinterpretq_s8_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_f16" type="checkbox"><label for="vreinterpretq_s16_f16"><div>int16x8_t <b><b>vreinterpretq_s16_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_f16" type="checkbox"><label for="vreinterpretq_s32_f16"><div>int32x4_t <b><b>vreinterpretq_s32_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_f16" type="checkbox"><label for="vreinterpretq_f32_f16"><div>float32x4_t <b><b>vreinterpretq_f32_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_f16" type="checkbox"><label for="vreinterpretq_u8_f16"><div>uint8x16_t <b><b>vreinterpretq_u8_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_f16" type="checkbox"><label for="vreinterpretq_u16_f16"><div>uint16x8_t <b><b>vreinterpretq_u16_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_f16" type="checkbox"><label for="vreinterpretq_u32_f16"><div>uint32x4_t <b><b>vreinterpretq_u32_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_f16" type="checkbox"><label for="vreinterpretq_p8_f16"><div>poly8x16_t <b><b>vreinterpretq_p8_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_f16" type="checkbox"><label for="vreinterpretq_p16_f16"><div>poly16x8_t <b><b>vreinterpretq_p16_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_f16" type="checkbox"><label for="vreinterpretq_u64_f16"><div>uint64x2_t <b><b>vreinterpretq_u64_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_f16" type="checkbox"><label for="vreinterpretq_s64_f16"><div>int64x2_t <b><b>vreinterpretq_s64_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>v7/A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_f16" type="checkbox"><label for="vreinterpretq_f64_f16"><div>float64x2_t <b><b>vreinterpretq_f64_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p64_f16" type="checkbox"><label for="vreinterpretq_p64_f16"><div>poly64x2_t <b><b>vreinterpretq_p64_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p128_f16" type="checkbox"><label for="vreinterpretq_p128_f16"><div>poly128_t <b><b>vreinterpretq_p128_f16</b></b> (float16x8_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.8H </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_f64" type="checkbox"><label for="vreinterpret_s8_f64"><div>int8x8_t <b><b>vreinterpret_s8_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_f64" type="checkbox"><label for="vreinterpret_s16_f64"><div>int16x4_t <b><b>vreinterpret_s16_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_f64" type="checkbox"><label for="vreinterpret_s32_f64"><div>int32x2_t <b><b>vreinterpret_s32_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_f64" type="checkbox"><label for="vreinterpret_u8_f64"><div>uint8x8_t <b><b>vreinterpret_u8_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_f64" type="checkbox"><label for="vreinterpret_u16_f64"><div>uint16x4_t <b><b>vreinterpret_u16_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_f64" type="checkbox"><label for="vreinterpret_u32_f64"><div>uint32x2_t <b><b>vreinterpret_u32_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_f64" type="checkbox"><label for="vreinterpret_p8_f64"><div>poly8x8_t <b><b>vreinterpret_p8_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_f64" type="checkbox"><label for="vreinterpret_p16_f64"><div>poly16x4_t <b><b>vreinterpret_p16_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_f64" type="checkbox"><label for="vreinterpret_u64_f64"><div>uint64x1_t <b><b>vreinterpret_u64_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_f64" type="checkbox"><label for="vreinterpret_s64_f64"><div>int64x1_t <b><b>vreinterpret_s64_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_f64" type="checkbox"><label for="vreinterpret_f16_f64"><div>float16x4_t <b><b>vreinterpret_f16_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f32_f64" type="checkbox"><label for="vreinterpret_f32_f64"><div>float32x2_t <b><b>vreinterpret_f32_f64</b></b> (float64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_f64" type="checkbox"><label for="vreinterpretq_s8_f64"><div>int8x16_t <b><b>vreinterpretq_s8_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_f64" type="checkbox"><label for="vreinterpretq_s16_f64"><div>int16x8_t <b><b>vreinterpretq_s16_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_f64" type="checkbox"><label for="vreinterpretq_s32_f64"><div>int32x4_t <b><b>vreinterpretq_s32_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_f64" type="checkbox"><label for="vreinterpretq_u8_f64"><div>uint8x16_t <b><b>vreinterpretq_u8_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_f64" type="checkbox"><label for="vreinterpretq_u16_f64"><div>uint16x8_t <b><b>vreinterpretq_u16_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_f64" type="checkbox"><label for="vreinterpretq_u32_f64"><div>uint32x4_t <b><b>vreinterpretq_u32_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_f64" type="checkbox"><label for="vreinterpretq_p8_f64"><div>poly8x16_t <b><b>vreinterpretq_p8_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_f64" type="checkbox"><label for="vreinterpretq_p16_f64"><div>poly16x8_t <b><b>vreinterpretq_p16_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_f64" type="checkbox"><label for="vreinterpretq_u64_f64"><div>uint64x2_t <b><b>vreinterpretq_u64_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_f64" type="checkbox"><label for="vreinterpretq_s64_f64"><div>int64x2_t <b><b>vreinterpretq_s64_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_f64" type="checkbox"><label for="vreinterpretq_f16_f64"><div>float16x8_t <b><b>vreinterpretq_f16_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f32_f64" type="checkbox"><label for="vreinterpretq_f32_f64"><div>float32x4_t <b><b>vreinterpretq_f32_f64</b></b> (float64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s8_p64" type="checkbox"><label for="vreinterpret_s8_p64"><div>int8x8_t <b><b>vreinterpret_s8_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s16_p64" type="checkbox"><label for="vreinterpret_s16_p64"><div>int16x4_t <b><b>vreinterpret_s16_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s32_p64" type="checkbox"><label for="vreinterpret_s32_p64"><div>int32x2_t <b><b>vreinterpret_s32_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u8_p64" type="checkbox"><label for="vreinterpret_u8_p64"><div>uint8x8_t <b><b>vreinterpret_u8_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u16_p64" type="checkbox"><label for="vreinterpret_u16_p64"><div>uint16x4_t <b><b>vreinterpret_u16_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u32_p64" type="checkbox"><label for="vreinterpret_u32_p64"><div>uint32x2_t <b><b>vreinterpret_u32_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.2S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p8_p64" type="checkbox"><label for="vreinterpret_p8_p64"><div>poly8x8_t <b><b>vreinterpret_p8_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.8B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_p16_p64" type="checkbox"><label for="vreinterpret_p16_p64"><div>poly16x4_t <b><b>vreinterpret_p16_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_u64_p64" type="checkbox"><label for="vreinterpret_u64_p64"><div>uint64x1_t <b><b>vreinterpret_u64_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_s64_p64" type="checkbox"><label for="vreinterpret_s64_p64"><div>int64x1_t <b><b>vreinterpret_s64_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f64_p64" type="checkbox"><label for="vreinterpret_f64_p64"><div>float64x1_t <b><b>vreinterpret_f64_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.1D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpret_f16_p64" type="checkbox"><label for="vreinterpret_f16_p64"><div>float16x4_t <b><b>vreinterpret_f16_p64</b></b> (poly64x1_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1D </pre>      <h4>Results</h4>      <pre>Vd.4H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_p64" type="checkbox"><label for="vreinterpretq_s8_p64"><div>int8x16_t <b><b>vreinterpretq_s8_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_p64" type="checkbox"><label for="vreinterpretq_s16_p64"><div>int16x8_t <b><b>vreinterpretq_s16_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_p64" type="checkbox"><label for="vreinterpretq_s32_p64"><div>int32x4_t <b><b>vreinterpretq_s32_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_p64" type="checkbox"><label for="vreinterpretq_u8_p64"><div>uint8x16_t <b><b>vreinterpretq_u8_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_p64" type="checkbox"><label for="vreinterpretq_u16_p64"><div>uint16x8_t <b><b>vreinterpretq_u16_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_p64" type="checkbox"><label for="vreinterpretq_u32_p64"><div>uint32x4_t <b><b>vreinterpretq_u32_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_p64" type="checkbox"><label for="vreinterpretq_p8_p64"><div>poly8x16_t <b><b>vreinterpretq_p8_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_p64" type="checkbox"><label for="vreinterpretq_p16_p64"><div>poly16x8_t <b><b>vreinterpretq_p16_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_p64" type="checkbox"><label for="vreinterpretq_u64_p64"><div>uint64x2_t <b><b>vreinterpretq_u64_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_p64" type="checkbox"><label for="vreinterpretq_s64_p64"><div>int64x2_t <b><b>vreinterpretq_s64_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_p64" type="checkbox"><label for="vreinterpretq_f64_p64"><div>float64x2_t <b><b>vreinterpretq_f64_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_p64" type="checkbox"><label for="vreinterpretq_f16_p64"><div>float16x8_t <b><b>vreinterpretq_f16_p64</b></b> (poly64x2_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.2D </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s8_p128" type="checkbox"><label for="vreinterpretq_s8_p128"><div>int8x16_t <b><b>vreinterpretq_s8_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s16_p128" type="checkbox"><label for="vreinterpretq_s16_p128"><div>int16x8_t <b><b>vreinterpretq_s16_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s32_p128" type="checkbox"><label for="vreinterpretq_s32_p128"><div>int32x4_t <b><b>vreinterpretq_s32_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u8_p128" type="checkbox"><label for="vreinterpretq_u8_p128"><div>uint8x16_t <b><b>vreinterpretq_u8_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u16_p128" type="checkbox"><label for="vreinterpretq_u16_p128"><div>uint16x8_t <b><b>vreinterpretq_u16_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u32_p128" type="checkbox"><label for="vreinterpretq_u32_p128"><div>uint32x4_t <b><b>vreinterpretq_u32_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p8_p128" type="checkbox"><label for="vreinterpretq_p8_p128"><div>poly8x16_t <b><b>vreinterpretq_p8_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_p16_p128" type="checkbox"><label for="vreinterpretq_p16_p128"><div>poly16x8_t <b><b>vreinterpretq_p16_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_u64_p128" type="checkbox"><label for="vreinterpretq_u64_p128"><div>uint64x2_t <b><b>vreinterpretq_u64_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_s64_p128" type="checkbox"><label for="vreinterpretq_s64_p128"><div>int64x2_t <b><b>vreinterpretq_s64_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f64_p128" type="checkbox"><label for="vreinterpretq_f64_p128"><div>float64x2_t <b><b>vreinterpretq_f64_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.2D &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A64</p> </article>  </div><div class="intrinsic"><input id="vreinterpretq_f16_p128" type="checkbox"><label for="vreinterpretq_f16_p128"><div>float16x8_t <b><b>vreinterpretq_f16_p128</b></b> (poly128_t a)<span class="right">Vector reinterpret cast operation</span></div></label><article>      <h4>Description</h4><p></p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/nop-no-operation">NOP</a> 
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vd.1Q </pre>      <h4>Results</h4>      <pre>Vd.8H &rarr; result
+ </pre>       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vldrq_p128" type="checkbox"><label for="vldrq_p128"><div>poly128_t <b><b>vldrq_p128</b></b> (poly128_t const * ptr)<span class="right">Load SIMD&amp;FP register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Load SIMD&amp;FP Register (register offset). This instruction loads a SIMD&amp;FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/ldr-register-simdfp-load-simdfp-register-register-offset">LDR</a> Qd,[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn </pre>      <h4>Results</h4>      <pre>Qd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(64) offset = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.ExtendReg.3" title="function: bits(N) ExtendReg(integer reg, ExtendType type, integer shift)">ExtendReg</a>(m, extend_type, shift);
+ if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     boolean is_load_store = memop IN {<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>};
+     SetNotTagCheckedInstruction(is_load_store &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(64) address;
+ bits(datasize) data;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ address = address + offset;
+ 
+ case memop of
+     when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
+         data = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address, datasize DIV 8, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = data;
+ 
+     when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
+         data = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address, datasize DIV 8, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = data;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vstrq_p128" type="checkbox"><label for="vstrq_p128"><div>void <b><b>vstrq_p128</b></b> (poly128_t * ptr, poly128_t val)<span class="right">Store SIMD&amp;FP register</span></div></label><article>      <h4>Description</h4><p><p class="aml">Store SIMD&amp;FP register (register offset). This instruction stores a single SIMD&amp;FP register to memory. The address that is used for the store is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/str-register-simdfp-store-simdfp-register-register-offset">STR</a> Qt,[Xn]
+ </pre>      <h4>Argument Preparation</h4><pre>ptr &rarr; Xn <br />
+ val &rarr; Qt </pre>      <h4>Results</h4>      <pre>void &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(64) offset = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#impl-aarch64.ExtendReg.3" title="function: bits(N) ExtendReg(integer reg, ExtendType type, integer shift)">ExtendReg</a>(m, extend_type, shift);
+ if <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.HaveMTEExt.0" title="function: boolean HaveMTEExt()">HaveMTEExt</a>() then
+     boolean is_load_store = memop IN {<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>};
+     SetNotTagCheckedInstruction(is_load_store &amp;&amp; n == 31);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(64) address;
+ bits(datasize) data;
+ 
+ if n == 31 then
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.SP.read.0" title="accessor: bits(width) SP[]">SP</a>[];
+ else
+     address = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];
+ 
+ address = address + offset;
+ 
+ case memop of
+     when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
+         data = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[t];
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccType acctype] = bits(size*8) value">Mem</a>[address, datasize DIV 8, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>] = data;
+ 
+     when <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-instrs-pseudocode#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
+         data = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccType acctype]">Mem</a>[address, datasize DIV 8, <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#AccType_VEC" title="enumeration AccType {AccType_NORMAL, AccType_VEC, AccType_STREAM, AccType_VECSTREAM, AccType_ATOMIC, AccType_ATOMICRW, AccType_ORDERED, AccType_ORDEREDRW, AccType_ORDEREDATOMIC, AccType_ORDEREDATOMICRW,
+  AccType_LIMITEDORDERED, AccType_UNPRIV, AccType_IFETCH, AccType_PTW, AccType_NONFAULT, AccType_CNOTFIRST, AccType_NV2REGISTER,   AccType_DC, AccType_DC_UNPRIV, AccType_IC, AccType_DCZVA, AccType_AT}">AccType_VEC</a>];
+         <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[t] = data;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaeseq_u8" type="checkbox"><label for="vaeseq_u8"><div>uint8x16_t <b><b>vaeseq_u8</b></b> (uint8x16_t data, uint8x16_t key)<span class="right">AES single round encryption</span></div></label><article>      <h4>Description</h4><p><p class="aml">AES single round encryption.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/aese-aes-single-round-encryption">AESE</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>data &rarr; Vd.16B <br />
+ key &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(128) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) result;
+ result = operand1 EOR operand2;
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.AESSubBytes.1" title="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.AESShiftRows.1" title="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</a>(result));
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaesdq_u8" type="checkbox"><label for="vaesdq_u8"><div>uint8x16_t <b><b>vaesdq_u8</b></b> (uint8x16_t data, uint8x16_t key)<span class="right">AES single round decryption</span></div></label><article>      <h4>Description</h4><p><p class="aml">AES single round decryption.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/aesd-aes-single-round-decryption">AESD</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>data &rarr; Vd.16B <br />
+ key &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(128) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) result;
+ result = operand1 EOR operand2;
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.AESInvSubBytes.1" title="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.AESInvShiftRows.1" title="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</a>(result));
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaesmcq_u8" type="checkbox"><label for="vaesmcq_u8"><div>uint8x16_t <b><b>vaesmcq_u8</b></b> (uint8x16_t data)<span class="right">AES mix columns</span></div></label><article>      <h4>Description</h4><p><p class="aml">AES mix columns.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/aesmc-aes-mix-columns">AESMC</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>data &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) result;
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.AESMixColumns.1" title="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(operand);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vaesimcq_u8" type="checkbox"><label for="vaesimcq_u8"><div>uint8x16_t <b><b>vaesimcq_u8</b></b> (uint8x16_t data)<span class="right">AES inverse mix columns</span></div></label><article>      <h4>Description</h4><p><p class="aml">AES inverse mix columns.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/aesimc-aes-inverse-mix-columns">AESIMC</a> Vd.16B,Vn.16B
+ </pre>      <h4>Argument Preparation</h4><pre>data &rarr; Vn.16B </pre>      <h4>Results</h4>      <pre>Vd.16B &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) result;
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.AESInvMixColumns.1" title="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(operand);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha1cq_u32" type="checkbox"><label for="vsha1cq_u32"><div>uint32x4_t <b><b>vsha1cq_u32</b></b> (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)<span class="right">SHA1 hash update (choose)</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA1 hash update (choose).</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha1c-sha1-hash-update-choose">SHA1C</a> Qd,Sn,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>hash_abcd &rarr; Qd <br />
+ hash_e &rarr; Sn <br />
+ wk &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Qd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) X = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(32) Y = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];    // Note: 32 not 128 bits wide
+ bits(128) W = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(32) t;
+ 
+ for e = 0 to 3
+     t = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SHAchoose.3" title="function: bits(32) SHAchoose(bits(32) x, bits(32) y, bits(32) z)">SHAchoose</a>(X&lt;63:32&gt;, X&lt;95:64&gt;, X&lt;127:96&gt;);
+     Y = Y + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(X&lt;31:0&gt;, 5) + t + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[W, e, 32];
+     X&lt;63:32&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(X&lt;63:32&gt;, 30);
+     &lt;Y, X&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Y:X, 32);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = X;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha1pq_u32" type="checkbox"><label for="vsha1pq_u32"><div>uint32x4_t <b><b>vsha1pq_u32</b></b> (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)<span class="right">SHA1 hash update (parity)</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA1 hash update (parity).</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha1p-sha1-hash-update-parity">SHA1P</a> Qd,Sn,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>hash_abcd &rarr; Qd <br />
+ hash_e &rarr; Sn <br />
+ wk &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Qd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) X = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(32) Y = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];    // Note: 32 not 128 bits wide
+ bits(128) W = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(32) t;
+ 
+ for e = 0 to 3
+     t = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SHAparity.3" title="function: bits(32) SHAparity(bits(32) x, bits(32) y, bits(32) z)">SHAparity</a>(X&lt;63:32&gt;, X&lt;95:64&gt;, X&lt;127:96&gt;);
+     Y = Y + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(X&lt;31:0&gt;, 5) + t + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[W, e, 32];
+     X&lt;63:32&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(X&lt;63:32&gt;, 30);
+     &lt;Y, X&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Y:X, 32);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = X;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha1mq_u32" type="checkbox"><label for="vsha1mq_u32"><div>uint32x4_t <b><b>vsha1mq_u32</b></b> (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)<span class="right">SHA1 hash update (majority)</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA1 hash update (majority).</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha1m-sha1-hash-update-majority">SHA1M</a> Qd,Sn,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>hash_abcd &rarr; Qd <br />
+ hash_e &rarr; Sn <br />
+ wk &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Qd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) X = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(32) Y = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];    // Note: 32 not 128 bits wide
+ bits(128) W = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(32) t;
+ 
+ for e = 0 to 3
+     t = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SHAmajority.3" title="function: bits(32) SHAmajority(bits(32) x, bits(32) y, bits(32) z)">SHAmajority</a>(X&lt;63:32&gt;, X&lt;95:64&gt;, X&lt;127:96&gt;);
+     Y = Y + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(X&lt;31:0&gt;, 5) + t + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[W, e, 32];
+     X&lt;63:32&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(X&lt;63:32&gt;, 30);
+     &lt;Y, X&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Y:X, 32);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = X;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha1h_u32" type="checkbox"><label for="vsha1h_u32"><div>uint32_t <b><b>vsha1h_u32</b></b> (uint32_t hash_e)<span class="right">SHA1 fixed rotate</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA1 fixed rotate.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha1h-sha1-fixed-rotate">SHA1H</a> Sd,Sn
+ </pre>      <h4>Argument Preparation</h4><pre>hash_e &rarr; Sn </pre>      <h4>Results</h4>      <pre>Sd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(32) operand = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];    // read element [0] only,  [1-3] zeroed
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(operand, 30);</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha1su0q_u32" type="checkbox"><label for="vsha1su0q_u32"><div>uint32x4_t <b><b>vsha1su0q_u32</b></b> (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)<span class="right">SHA1 schedule update 0</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA1 schedule update 0.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha1su0-sha1-schedule-update-0">SHA1SU0</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>w0_3 &rarr; Vd.4S <br />
+ w4_7 &rarr; Vn.4S <br />
+ w8_11 &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(128) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128) result;
+ 
+ result = operand2&lt;63:0&gt;:operand1&lt;127:64&gt;;
+ result = result EOR operand1 EOR operand3;
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha1su1q_u32" type="checkbox"><label for="vsha1su1q_u32"><div>uint32x4_t <b><b>vsha1su1q_u32</b></b> (uint32x4_t tw0_3, uint32x4_t w12_15)<span class="right">SHA1 schedule update 1</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA1 schedule update 1.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha1su1-sha1-schedule-update-1">SHA1SU1</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>tw0_3 &rarr; Vd.4S <br />
+ w12_15 &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(128) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) result;
+ bits(128) T = operand1 EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(operand2, 32);
+ result&lt;31:0&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;31:0&gt;, 1);
+ result&lt;63:32&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;63:32&gt;, 1);
+ result&lt;95:64&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;95:64&gt;, 1);
+ result&lt;127:96&gt; = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;127:96&gt;, 1) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROL.2" title="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;31:0&gt;, 2);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha256hq_u32" type="checkbox"><label for="vsha256hq_u32"><div>uint32x4_t <b><b>vsha256hq_u32</b></b> (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)<span class="right">SHA256 hash update (part 1)</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA256 hash update (part 1).</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha256h-sha256-hash-update-part-1">SHA256H</a> Qd,Qn,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>hash_abcd &rarr; Qd <br />
+ hash_efgh &rarr; Qn <br />
+ wk &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Qd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) result;
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SHA256hash.4" title="function: bits(128) SHA256hash(bits (128) X, bits(128) Y, bits(128) W, boolean part1)">SHA256hash</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d], <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n], <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m], TRUE);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha256h2q_u32" type="checkbox"><label for="vsha256h2q_u32"><div>uint32x4_t <b><b>vsha256h2q_u32</b></b> (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)<span class="right">SHA256 hash update (part 2)</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA256 hash update (part 2).</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha256h2-sha256-hash-update-part-2">SHA256H2</a> Qd,Qn,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>hash_efgh &rarr; Qd <br />
+ hash_abcd &rarr; Qn <br />
+ wk &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Qd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) result;
+ result = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.SHA256hash.4" title="function: bits(128) SHA256hash(bits (128) X, bits(128) Y, bits(128) W, boolean part1)">SHA256hash</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n], <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d], <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m], FALSE);
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha256su0q_u32" type="checkbox"><label for="vsha256su0q_u32"><div>uint32x4_t <b><b>vsha256su0q_u32</b></b> (uint32x4_t w0_3, uint32x4_t w4_7)<span class="right">SHA256 schedule update 0</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA256 schedule update 0.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha256su0-sha256-schedule-update-0">SHA256SU0</a> Vd.4S,Vn.4S
+ </pre>      <h4>Argument Preparation</h4><pre>w0_3 &rarr; Vd.4S <br />
+ w4_7 &rarr; Vn.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(128) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) result;
+ bits(128) T = operand2&lt;31:0&gt;:operand1&lt;127:32&gt;;
+ bits(32) elt;
+ 
+ for e = 0 to 3
+     elt = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T, e, 32];
+     elt = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROR.2" title="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 7) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROR.2" title="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 18) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(elt, 3);
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = elt + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 32];
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vsha256su1q_u32" type="checkbox"><label for="vsha256su1q_u32"><div>uint32x4_t <b><b>vsha256su1q_u32</b></b> (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)<span class="right">SHA256 schedule update 1</span></div></label><article>      <h4>Description</h4><p><p class="aml">SHA256 schedule update 1.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/sha256su1-sha256-schedule-update-1">SHA256SU1</a> Vd.4S,Vn.4S,Vm.4S
+ </pre>      <h4>Argument Preparation</h4><pre>tw0_3 &rarr; Vd.4S <br />
+ w8_11 &rarr; Vn.4S <br />
+ w12_15 &rarr; Vm.4S </pre>      <h4>Results</h4>      <pre>Vd.4S &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
+ 
+ bits(128) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[d];
+ bits(128) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[n];
+ bits(128) operand3 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.read.1" title="accessor: bits(width) V[integer n]">V</a>[m];
+ bits(128) result;
+ bits(128) T0 = operand3&lt;31:0&gt;:operand2&lt;127:32&gt;;
+ bits(64) T1;
+ bits(32) elt;
+ 
+ T1 = operand3&lt;127:64&gt;;
+ for e = 0 to 1
+     elt = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T1, e, 32];
+     elt = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROR.2" title="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 17) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROR.2" title="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 19) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(elt, 10);
+     elt = elt + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 32] + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T0, e, 32];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = elt;
+ 
+ T1 = result&lt;63:0&gt;;
+ for e = 2 to 3
+     elt = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T1, e-2, 32];
+     elt = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROR.2" title="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 17) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.ROR.2" title="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 19) EOR <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.LSR.2" title="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(elt, 10);
+     elt = elt + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 32] + <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T0, e, 32];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = elt;
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_p64" type="checkbox"><label for="vmull_p64"><div>poly128_t <b><b>vmull_p64</b></b> (poly64_t a, poly64_t b)<span class="right">Polynomial multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/pmull-pmull2-polynomial-multiply-long">PMULL</a> Vd.1Q,Vn.1D,Vm.1D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.1D <br />
+ b &rarr; Vm.1D </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="vmull_high_p64" type="checkbox"><label for="vmull_high_p64"><div>poly128_t <b><b>vmull_high_p64</b></b> (poly64x2_t a, poly64x2_t b)<span class="right">Polynomial multiply long</span></div></label><article>      <h4>Description</h4><p><p class="aml">Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&amp;FP registers, places the results in a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the elements that are multiplied.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/pmull-pmull2-polynomial-multiply-long">PMULL2</a> Vd.1Q,Vn.2D,Vm.2D
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Vn.2D <br />
+ b &rarr; Vm.2D </pre>      <h4>Results</h4>      <pre>Vd.1Q &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock"><a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-exceptions-pseudocode#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
+ bits(datasize) operand1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[n, part];
+ bits(datasize) operand2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.Vpart.read.2" title="accessor: bits(width) Vpart[integer n, integer part]">Vpart</a>[m, part];
+ bits(2*datasize) result;
+ bits(esize) element1;
+ bits(esize) element2;
+ 
+ for e = 0 to elements-1
+     element1 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
+     element2 = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
+     <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.PolynomialMult.2" title="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(element1, element2);
+ 
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-simd-and-floating-point-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.V.write.1" title="accessor: V[integer n] = bits(width) value">V</a>[d] = result;</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32b" type="checkbox"><label for="__crc32b"><div>uint32_t <b><b>__crc32b</b></b> (uint32_t a, uint8_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32b-crc32h-crc32w-crc32x-crc32-checksum">CRC32B</a> Wd,Wn,Wm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Wm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x04C11DB7&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32h" type="checkbox"><label for="__crc32h"><div>uint32_t <b><b>__crc32h</b></b> (uint32_t a, uint16_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32b-crc32h-crc32w-crc32x-crc32-checksum">CRC32H</a> Wd,Wn,Wm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Wm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x04C11DB7&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32w" type="checkbox"><label for="__crc32w"><div>uint32_t <b><b>__crc32w</b></b> (uint32_t a, uint32_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32b-crc32h-crc32w-crc32x-crc32-checksum">CRC32W</a> Wd,Wn,Wm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Wm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x04C11DB7&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32d" type="checkbox"><label for="__crc32d"><div>uint32_t <b><b>__crc32d</b></b> (uint32_t a, uint64_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32b-crc32h-crc32w-crc32x-crc32-checksum">CRC32X</a> Wd,Wn,Xm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Xm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x04C11DB7&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32cb" type="checkbox"><label for="__crc32cb"><div>uint32_t <b><b>__crc32cb</b></b> (uint32_t a, uint8_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32cb-crc32ch-crc32cw-crc32cx-crc32c-checksum">CRC32CB</a> Wd,Wn,Wm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Wm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x1EDC6F41&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32ch" type="checkbox"><label for="__crc32ch"><div>uint32_t <b><b>__crc32ch</b></b> (uint32_t a, uint16_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32cb-crc32ch-crc32cw-crc32cx-crc32c-checksum">CRC32CH</a> Wd,Wn,Wm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Wm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x1EDC6F41&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32cw" type="checkbox"><label for="__crc32cw"><div>uint32_t <b><b>__crc32cw</b></b> (uint32_t a, uint32_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32cb-crc32ch-crc32cw-crc32cx-crc32c-checksum">CRC32CW</a> Wd,Wn,Wm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Wm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x1EDC6F41&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div><div class="intrinsic"><input id="__crc32cd" type="checkbox"><label for="__crc32cd"><div>uint32_t <b><b>__crc32cd</b></b> (uint32_t a, uint64_t b)<span class="right"><span class="asm-code">CRC32 checksum</span></div></label><article>      <h4>Description</h4><p><p class="aml"><span class="asm-code">CRC32</span> checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.</p>
+ </p>      <h4>A64 Instruction</h4><pre><a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/crc32cb-crc32ch-crc32cw-crc32cx-crc32c-checksum">CRC32CX</a> Wd,Wn,Xm
+ </pre>      <h4>Argument Preparation</h4><pre>a &rarr; Wn <br />
+ b &rarr; Xm </pre>      <h4>Results</h4>      <pre>Wd &rarr; result
+ </pre>  <h4>Operation</h4>
+ <pre class="codeblock">bits(32) acc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[n];    // accumulator
+ bits(size) val = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.read.1" title="accessor: bits(width) X[integer n]">X</a>[m];    // input value
+ bits(32) poly = 0x1EDC6F41&lt;31:0&gt;;
+ 
+ bits(32+size) tempacc = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(size);
+ bits(size+32) tempval = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(32);
+ 
+ // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+ <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/aarch64-functions-pseudocode#impl-aarch64.X.write.1" title="accessor: X[integer n] = bits(width) value">X</a>[d] = <a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.BitReverse.1" title="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a href="https://developer.arm.com/docs/ddi0596/a/a64-base-instructions-alphabetic-order/../a64-shared-pseudocode-functions/shared-functions-pseudocode#impl-shared.Poly32Mod2.2" title="function: bits(32) Poly32Mod2(bits(N) data, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</pre>
+       <h4>Supported architectures</h4>      <p>A32/A64</p> </article>  </div>
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diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/build.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/build.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/build.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/build.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,28 ----
+ use std::path::Path;
+ 
+ fn main() {
+     let dir = Path::new(env!("CARGO_MANIFEST_DIR"));
+     let root = dir.parent().unwrap();
+     eprintln!("root: {}", root.display());
+     walk(&root.join("core_arch/src/x86"));
+     walk(&root.join("core_arch/src/x86_64"));
+     walk(&root.join("core_arch/src/arm"));
+     walk(&root.join("core_arch/src/aarch64"));
+ }
+ 
+ fn walk(root: &Path) {
+     for file in root.read_dir().unwrap() {
+         eprintln!("root: {}", root.display());
+         let file = file.unwrap();
+         if file.file_type().unwrap().is_dir() {
+             walk(&file.path());
+             continue;
+         }
+         let path = file.path();
+         if path.extension().and_then(|s| s.to_str()) != Some("rs") {
+             continue;
+         }
+ 
+         println!("cargo:rerun-if-changed={}", path.display());
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,707 ----
+ v16i8 __builtin_msa_add_a_b (v16i8, v16i8);
+ v8i16 __builtin_msa_add_a_h (v8i16, v8i16);
+ v4i32 __builtin_msa_add_a_w (v4i32, v4i32);
+ v2i64 __builtin_msa_add_a_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_adds_a_b (v16i8, v16i8);
+ v8i16 __builtin_msa_adds_a_h (v8i16, v8i16);
+ v4i32 __builtin_msa_adds_a_w (v4i32, v4i32);
+ v2i64 __builtin_msa_adds_a_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_adds_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_adds_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_adds_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_adds_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_adds_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_adds_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_adds_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_adds_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_addv_b (v16i8, v16i8);
+ v8i16 __builtin_msa_addv_h (v8i16, v8i16);
+ v4i32 __builtin_msa_addv_w (v4i32, v4i32);
+ v2i64 __builtin_msa_addv_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_addvi_b (v16i8, imm0_31);
+ v8i16 __builtin_msa_addvi_h (v8i16, imm0_31);
+ v4i32 __builtin_msa_addvi_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_addvi_d (v2i64, imm0_31);
+ 
+ v16u8 __builtin_msa_and_v (v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_andi_b (v16u8, imm0_255);
+ 
+ v16i8 __builtin_msa_asub_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_asub_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_asub_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_asub_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_asub_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_asub_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_asub_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_asub_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_ave_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_ave_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_ave_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_ave_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_ave_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_ave_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_ave_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_ave_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_aver_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_aver_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_aver_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_aver_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_aver_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_aver_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_aver_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_aver_u_d (v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_bclr_b (v16u8, v16u8);
+ v8u16 __builtin_msa_bclr_h (v8u16, v8u16);
+ v4u32 __builtin_msa_bclr_w (v4u32, v4u32);
+ v2u64 __builtin_msa_bclr_d (v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_bclri_b (v16u8, imm0_7);
+ v8u16 __builtin_msa_bclri_h (v8u16, imm0_15);
+ v4u32 __builtin_msa_bclri_w (v4u32, imm0_31);
+ v2u64 __builtin_msa_bclri_d (v2u64, imm0_63);
+ 
+ v16u8 __builtin_msa_binsl_b (v16u8, v16u8, v16u8);
+ v8u16 __builtin_msa_binsl_h (v8u16, v8u16, v8u16);
+ v4u32 __builtin_msa_binsl_w (v4u32, v4u32, v4u32);
+ v2u64 __builtin_msa_binsl_d (v2u64, v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_binsli_b (v16u8, v16u8, imm0_7);
+ v8u16 __builtin_msa_binsli_h (v8u16, v8u16, imm0_15);
+ v4u32 __builtin_msa_binsli_w (v4u32, v4u32, imm0_31);
+ v2u64 __builtin_msa_binsli_d (v2u64, v2u64, imm0_63);
+ 
+ v16u8 __builtin_msa_binsr_b (v16u8, v16u8, v16u8);
+ v8u16 __builtin_msa_binsr_h (v8u16, v8u16, v8u16);
+ v4u32 __builtin_msa_binsr_w (v4u32, v4u32, v4u32);
+ v2u64 __builtin_msa_binsr_d (v2u64, v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_binsri_b (v16u8, v16u8, imm0_7);
+ v8u16 __builtin_msa_binsri_h (v8u16, v8u16, imm0_15);
+ v4u32 __builtin_msa_binsri_w (v4u32, v4u32, imm0_31);
+ v2u64 __builtin_msa_binsri_d (v2u64, v2u64, imm0_63);
+ 
+ v16u8 __builtin_msa_bmnz_v (v16u8, v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_bmnzi_b (v16u8, v16u8, imm0_255);
+ 
+ v16u8 __builtin_msa_bmz_v (v16u8, v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_bmzi_b (v16u8, v16u8, imm0_255);
+ 
+ v16u8 __builtin_msa_bneg_b (v16u8, v16u8);
+ v8u16 __builtin_msa_bneg_h (v8u16, v8u16);
+ v4u32 __builtin_msa_bneg_w (v4u32, v4u32);
+ v2u64 __builtin_msa_bneg_d (v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_bnegi_b (v16u8, imm0_7);
+ v8u16 __builtin_msa_bnegi_h (v8u16, imm0_15);
+ v4u32 __builtin_msa_bnegi_w (v4u32, imm0_31);
+ v2u64 __builtin_msa_bnegi_d (v2u64, imm0_63);
+ 
+ i32 __builtin_msa_bnz_b (v16u8);
+ i32 __builtin_msa_bnz_h (v8u16);
+ i32 __builtin_msa_bnz_w (v4u32);
+ i32 __builtin_msa_bnz_d (v2u64);
+ 
+ i32 __builtin_msa_bnz_v (v16u8);
+ 
+ v16u8 __builtin_msa_bsel_v (v16u8, v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_bseli_b (v16u8, v16u8, imm0_255);
+ 
+ v16u8 __builtin_msa_bset_b (v16u8, v16u8);
+ v8u16 __builtin_msa_bset_h (v8u16, v8u16);
+ v4u32 __builtin_msa_bset_w (v4u32, v4u32);
+ v2u64 __builtin_msa_bset_d (v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_bseti_b (v16u8, imm0_7);
+ v8u16 __builtin_msa_bseti_h (v8u16, imm0_15);
+ v4u32 __builtin_msa_bseti_w (v4u32, imm0_31);
+ v2u64 __builtin_msa_bseti_d (v2u64, imm0_63);
+ 
+ i32 __builtin_msa_bz_b (v16u8);
+ i32 __builtin_msa_bz_h (v8u16);
+ i32 __builtin_msa_bz_w (v4u32);
+ i32 __builtin_msa_bz_d (v2u64);
+ 
+ i32 __builtin_msa_bz_v (v16u8);
+ 
+ v16i8 __builtin_msa_ceq_b (v16i8, v16i8);
+ v8i16 __builtin_msa_ceq_h (v8i16, v8i16);
+ v4i32 __builtin_msa_ceq_w (v4i32, v4i32);
+ v2i64 __builtin_msa_ceq_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_ceqi_b (v16i8, imm_n16_15);
+ v8i16 __builtin_msa_ceqi_h (v8i16, imm_n16_15);
+ v4i32 __builtin_msa_ceqi_w (v4i32, imm_n16_15);
+ v2i64 __builtin_msa_ceqi_d (v2i64, imm_n16_15);
+ 
+ i32 __builtin_msa_cfcmsa (imm0_31);
+ 
+ v16i8 __builtin_msa_cle_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_cle_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_cle_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_cle_s_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_cle_u_b (v16u8, v16u8);
+ v8i16 __builtin_msa_cle_u_h (v8u16, v8u16);
+ v4i32 __builtin_msa_cle_u_w (v4u32, v4u32);
+ v2i64 __builtin_msa_cle_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_clei_s_b (v16i8, imm_n16_15);
+ v8i16 __builtin_msa_clei_s_h (v8i16, imm_n16_15);
+ v4i32 __builtin_msa_clei_s_w (v4i32, imm_n16_15);
+ v2i64 __builtin_msa_clei_s_d (v2i64, imm_n16_15);
+ 
+ v16i8 __builtin_msa_clei_u_b (v16u8, imm0_31);
+ v8i16 __builtin_msa_clei_u_h (v8u16, imm0_31);
+ v4i32 __builtin_msa_clei_u_w (v4u32, imm0_31);
+ v2i64 __builtin_msa_clei_u_d (v2u64, imm0_31);
+ 
+ v16i8 __builtin_msa_clt_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_clt_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_clt_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_clt_s_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_clt_u_b (v16u8, v16u8);
+ v8i16 __builtin_msa_clt_u_h (v8u16, v8u16);
+ v4i32 __builtin_msa_clt_u_w (v4u32, v4u32);
+ v2i64 __builtin_msa_clt_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_clti_s_b (v16i8, imm_n16_15);
+ v8i16 __builtin_msa_clti_s_h (v8i16, imm_n16_15);
+ v4i32 __builtin_msa_clti_s_w (v4i32, imm_n16_15);
+ v2i64 __builtin_msa_clti_s_d (v2i64, imm_n16_15);
+ 
+ v16i8 __builtin_msa_clti_u_b (v16u8, imm0_31);
+ v8i16 __builtin_msa_clti_u_h (v8u16, imm0_31);
+ v4i32 __builtin_msa_clti_u_w (v4u32, imm0_31);
+ v2i64 __builtin_msa_clti_u_d (v2u64, imm0_31);
+ 
+ i32 __builtin_msa_copy_s_b (v16i8, imm0_15);
+ i32 __builtin_msa_copy_s_h (v8i16, imm0_7);
+ i32 __builtin_msa_copy_s_w (v4i32, imm0_3);
+ i64 __builtin_msa_copy_s_d (v2i64, imm0_1);
+ 
+ u32 __builtin_msa_copy_u_b (v16i8, imm0_15);
+ u32 __builtin_msa_copy_u_h (v8i16, imm0_7);
+ u32 __builtin_msa_copy_u_w (v4i32, imm0_3);
+ u64 __builtin_msa_copy_u_d (v2i64, imm0_1);
+ 
+ void __builtin_msa_ctcmsa (imm0_31, i32);
+ 
+ v16i8 __builtin_msa_div_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_div_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_div_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_div_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_div_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_div_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_div_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_div_u_d (v2u64, v2u64);
+ 
+ v8i16 __builtin_msa_dotp_s_h (v16i8, v16i8);
+ v4i32 __builtin_msa_dotp_s_w (v8i16, v8i16);
+ v2i64 __builtin_msa_dotp_s_d (v4i32, v4i32);
+ 
+ v8u16 __builtin_msa_dotp_u_h (v16u8, v16u8);
+ v4u32 __builtin_msa_dotp_u_w (v8u16, v8u16);
+ v2u64 __builtin_msa_dotp_u_d (v4u32, v4u32);
+ 
+ v8i16 __builtin_msa_dpadd_s_h (v8i16, v16i8, v16i8);
+ v4i32 __builtin_msa_dpadd_s_w (v4i32, v8i16, v8i16);
+ v2i64 __builtin_msa_dpadd_s_d (v2i64, v4i32, v4i32);
+ 
+ v8u16 __builtin_msa_dpadd_u_h (v8u16, v16u8, v16u8);
+ v4u32 __builtin_msa_dpadd_u_w (v4u32, v8u16, v8u16);
+ v2u64 __builtin_msa_dpadd_u_d (v2u64, v4u32, v4u32);
+ 
+ v8i16 __builtin_msa_dpsub_s_h (v8i16, v16i8, v16i8);
+ v4i32 __builtin_msa_dpsub_s_w (v4i32, v8i16, v8i16);
+ v2i64 __builtin_msa_dpsub_s_d (v2i64, v4i32, v4i32);
+ 
+ v8i16 __builtin_msa_dpsub_u_h (v8i16, v16u8, v16u8);
+ v4i32 __builtin_msa_dpsub_u_w (v4i32, v8u16, v8u16);
+ v2i64 __builtin_msa_dpsub_u_d (v2i64, v4u32, v4u32);
+ 
+ v4f32 __builtin_msa_fadd_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fadd_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcaf_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcaf_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fceq_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fceq_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fclass_w (v4f32);
+ v2i64 __builtin_msa_fclass_d (v2f64);
+ 
+ v4i32 __builtin_msa_fcle_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcle_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fclt_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fclt_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcne_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcne_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcor_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcor_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcueq_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcueq_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcule_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcule_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcult_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcult_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcun_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcun_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fcune_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fcune_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fdiv_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fdiv_d (v2f64, v2f64);
+ 
+ v8i16 __builtin_msa_fexdo_h (v4f32, v4f32);
+ v4f32 __builtin_msa_fexdo_w (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fexp2_w (v4f32, v4i32);
+ v2f64 __builtin_msa_fexp2_d (v2f64, v2i64);
+ 
+ v4f32 __builtin_msa_fexupl_w (v8i16);
+ v2f64 __builtin_msa_fexupl_d (v4f32);
+ 
+ v4f32 __builtin_msa_fexupr_w (v8i16);
+ v2f64 __builtin_msa_fexupr_d (v4f32);
+ 
+ v4f32 __builtin_msa_ffint_s_w (v4i32);
+ v2f64 __builtin_msa_ffint_s_d (v2i64);
+ 
+ v4f32 __builtin_msa_ffint_u_w (v4u32);
+ v2f64 __builtin_msa_ffint_u_d (v2u64);
+ 
+ v4f32 __builtin_msa_ffql_w (v8i16);
+ v2f64 __builtin_msa_ffql_d (v4i32);
+ 
+ v4f32 __builtin_msa_ffqr_w (v8i16);
+ v2f64 __builtin_msa_ffqr_d (v4i32);
+ 
+ v16i8 __builtin_msa_fill_b (i32);
+ v8i16 __builtin_msa_fill_h (i32);
+ v4i32 __builtin_msa_fill_w (i32);
+ v2i64 __builtin_msa_fill_d (i64);
+ 
+ v4f32 __builtin_msa_flog2_w (v4f32);
+ v2f64 __builtin_msa_flog2_d (v2f64);
+ 
+ v4f32 __builtin_msa_fmadd_w (v4f32, v4f32, v4f32);
+ v2f64 __builtin_msa_fmadd_d (v2f64, v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fmax_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fmax_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fmax_a_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fmax_a_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fmin_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fmin_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fmin_a_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fmin_a_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fmsub_w (v4f32, v4f32, v4f32);
+ v2f64 __builtin_msa_fmsub_d (v2f64, v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fmul_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fmul_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_frint_w (v4f32);
+ v2f64 __builtin_msa_frint_d (v2f64);
+ 
+ v4f32 __builtin_msa_frcp_w (v4f32);
+ v2f64 __builtin_msa_frcp_d (v2f64);
+ 
+ v4f32 __builtin_msa_frsqrt_w (v4f32);
+ v2f64 __builtin_msa_frsqrt_d (v2f64);
+ 
+ v4i32 __builtin_msa_fsaf_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsaf_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fseq_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fseq_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsle_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsle_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fslt_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fslt_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsne_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsne_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsor_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsor_d (v2f64, v2f64);
+ 
+ v4f32 __builtin_msa_fsqrt_w (v4f32);
+ v2f64 __builtin_msa_fsqrt_d (v2f64);
+ 
+ v4f32 __builtin_msa_fsub_w (v4f32, v4f32);
+ v2f64 __builtin_msa_fsub_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsueq_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsueq_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsule_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsule_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsult_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsult_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsun_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsun_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_fsune_w (v4f32, v4f32);
+ v2i64 __builtin_msa_fsune_d (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_ftint_s_w (v4f32);
+ v2i64 __builtin_msa_ftint_s_d (v2f64);
+ 
+ v4u32 __builtin_msa_ftint_u_w (v4f32);
+ v2u64 __builtin_msa_ftint_u_d (v2f64);
+ 
+ v8i16 __builtin_msa_ftq_h (v4f32, v4f32);
+ v4i32 __builtin_msa_ftq_w (v2f64, v2f64);
+ 
+ v4i32 __builtin_msa_ftrunc_s_w (v4f32);
+ v2i64 __builtin_msa_ftrunc_s_d (v2f64);
+ 
+ v4u32 __builtin_msa_ftrunc_u_w (v4f32);
+ v2u64 __builtin_msa_ftrunc_u_d (v2f64);
+ 
+ v8i16 __builtin_msa_hadd_s_h (v16i8, v16i8);
+ v4i32 __builtin_msa_hadd_s_w (v8i16, v8i16);
+ v2i64 __builtin_msa_hadd_s_d (v4i32, v4i32);
+ 
+ v8u16 __builtin_msa_hadd_u_h (v16u8, v16u8);
+ v4u32 __builtin_msa_hadd_u_w (v8u16, v8u16);
+ v2u64 __builtin_msa_hadd_u_d (v4u32, v4u32);
+ 
+ v8i16 __builtin_msa_hsub_s_h (v16i8, v16i8);
+ v4i32 __builtin_msa_hsub_s_w (v8i16, v8i16);
+ v2i64 __builtin_msa_hsub_s_d (v4i32, v4i32);
+ 
+ v8i16 __builtin_msa_hsub_u_h (v16u8, v16u8);
+ v4i32 __builtin_msa_hsub_u_w (v8u16, v8u16);
+ v2i64 __builtin_msa_hsub_u_d (v4u32, v4u32);
+ 
+ v16i8 __builtin_msa_ilvev_b (v16i8, v16i8);
+ v8i16 __builtin_msa_ilvev_h (v8i16, v8i16);
+ v4i32 __builtin_msa_ilvev_w (v4i32, v4i32);
+ v2i64 __builtin_msa_ilvev_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_ilvl_b (v16i8, v16i8);
+ v8i16 __builtin_msa_ilvl_h (v8i16, v8i16);
+ v4i32 __builtin_msa_ilvl_w (v4i32, v4i32);
+ v2i64 __builtin_msa_ilvl_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_ilvod_b (v16i8, v16i8);
+ v8i16 __builtin_msa_ilvod_h (v8i16, v8i16);
+ v4i32 __builtin_msa_ilvod_w (v4i32, v4i32);
+ v2i64 __builtin_msa_ilvod_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_ilvr_b (v16i8, v16i8);
+ v8i16 __builtin_msa_ilvr_h (v8i16, v8i16);
+ v4i32 __builtin_msa_ilvr_w (v4i32, v4i32);
+ v2i64 __builtin_msa_ilvr_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_insert_b (v16i8, imm0_15, i32);
+ v8i16 __builtin_msa_insert_h (v8i16, imm0_7, i32);
+ v4i32 __builtin_msa_insert_w (v4i32, imm0_3, i32);
+ v2i64 __builtin_msa_insert_d (v2i64, imm0_1, i64);
+ 
+ v16i8 __builtin_msa_insve_b (v16i8, imm0_15, v16i8);
+ v8i16 __builtin_msa_insve_h (v8i16, imm0_7, v8i16);
+ v4i32 __builtin_msa_insve_w (v4i32, imm0_3, v4i32);
+ v2i64 __builtin_msa_insve_d (v2i64, imm0_1, v2i64);
+ 
+ v16i8 __builtin_msa_ld_b (void *, imm_n512_511);
+ v8i16 __builtin_msa_ld_h (void *, imm_n1024_1022);
+ v4i32 __builtin_msa_ld_w (void *, imm_n2048_2044);
+ v2i64 __builtin_msa_ld_d (void *, imm_n4096_4088);
+ 
+ v16i8 __builtin_msa_ldi_b (imm_n512_511);
+ v8i16 __builtin_msa_ldi_h (imm_n512_511);
+ v4i32 __builtin_msa_ldi_w (imm_n512_511);
+ v2i64 __builtin_msa_ldi_d (imm_n512_511);
+ 
+ v8i16 __builtin_msa_madd_q_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_madd_q_w (v4i32, v4i32, v4i32);
+ 
+ v8i16 __builtin_msa_maddr_q_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_maddr_q_w (v4i32, v4i32, v4i32);
+ 
+ v16i8 __builtin_msa_maddv_b (v16i8, v16i8, v16i8);
+ v8i16 __builtin_msa_maddv_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_maddv_w (v4i32, v4i32, v4i32);
+ v2i64 __builtin_msa_maddv_d (v2i64, v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_max_a_b (v16i8, v16i8);
+ v8i16 __builtin_msa_max_a_h (v8i16, v8i16);
+ v4i32 __builtin_msa_max_a_w (v4i32, v4i32);
+ v2i64 __builtin_msa_max_a_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_max_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_max_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_max_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_max_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_max_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_max_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_max_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_max_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_maxi_s_b (v16i8, imm_n16_15);
+ v8i16 __builtin_msa_maxi_s_h (v8i16, imm_n16_15);
+ v4i32 __builtin_msa_maxi_s_w (v4i32, imm_n16_15);
+ v2i64 __builtin_msa_maxi_s_d (v2i64, imm_n16_15);
+ 
+ v16u8 __builtin_msa_maxi_u_b (v16u8, imm0_31);
+ v8u16 __builtin_msa_maxi_u_h (v8u16, imm0_31);
+ v4u32 __builtin_msa_maxi_u_w (v4u32, imm0_31);
+ v2u64 __builtin_msa_maxi_u_d (v2u64, imm0_31);
+ 
+ v16i8 __builtin_msa_min_a_b (v16i8, v16i8);
+ v8i16 __builtin_msa_min_a_h (v8i16, v8i16);
+ v4i32 __builtin_msa_min_a_w (v4i32, v4i32);
+ v2i64 __builtin_msa_min_a_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_min_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_min_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_min_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_min_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_min_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_min_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_min_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_min_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_mini_s_b (v16i8, imm_n16_15);
+ v8i16 __builtin_msa_mini_s_h (v8i16, imm_n16_15);
+ v4i32 __builtin_msa_mini_s_w (v4i32, imm_n16_15);
+ v2i64 __builtin_msa_mini_s_d (v2i64, imm_n16_15);
+ 
+ v16u8 __builtin_msa_mini_u_b (v16u8, imm0_31);
+ v8u16 __builtin_msa_mini_u_h (v8u16, imm0_31);
+ v4u32 __builtin_msa_mini_u_w (v4u32, imm0_31);
+ v2u64 __builtin_msa_mini_u_d (v2u64, imm0_31);
+ 
+ v16i8 __builtin_msa_mod_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_mod_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_mod_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_mod_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_mod_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_mod_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_mod_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_mod_u_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_move_v (v16i8);
+ 
+ v8i16 __builtin_msa_msub_q_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_msub_q_w (v4i32, v4i32, v4i32);
+ 
+ v8i16 __builtin_msa_msubr_q_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_msubr_q_w (v4i32, v4i32, v4i32);
+ 
+ v16i8 __builtin_msa_msubv_b (v16i8, v16i8, v16i8);
+ v8i16 __builtin_msa_msubv_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_msubv_w (v4i32, v4i32, v4i32);
+ v2i64 __builtin_msa_msubv_d (v2i64, v2i64, v2i64);
+ 
+ v8i16 __builtin_msa_mul_q_h (v8i16, v8i16);
+ v4i32 __builtin_msa_mul_q_w (v4i32, v4i32);
+ 
+ v8i16 __builtin_msa_mulr_q_h (v8i16, v8i16);
+ v4i32 __builtin_msa_mulr_q_w (v4i32, v4i32);
+ 
+ v16i8 __builtin_msa_mulv_b (v16i8, v16i8);
+ v8i16 __builtin_msa_mulv_h (v8i16, v8i16);
+ v4i32 __builtin_msa_mulv_w (v4i32, v4i32);
+ v2i64 __builtin_msa_mulv_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_nloc_b (v16i8);
+ v8i16 __builtin_msa_nloc_h (v8i16);
+ v4i32 __builtin_msa_nloc_w (v4i32);
+ v2i64 __builtin_msa_nloc_d (v2i64);
+ 
+ v16i8 __builtin_msa_nlzc_b (v16i8);
+ v8i16 __builtin_msa_nlzc_h (v8i16);
+ v4i32 __builtin_msa_nlzc_w (v4i32);
+ v2i64 __builtin_msa_nlzc_d (v2i64);
+ 
+ v16u8 __builtin_msa_nor_v (v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_nori_b (v16u8, imm0_255);
+ 
+ v16u8 __builtin_msa_or_v (v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_ori_b (v16u8, imm0_255);
+ 
+ v16i8 __builtin_msa_pckev_b (v16i8, v16i8);
+ v8i16 __builtin_msa_pckev_h (v8i16, v8i16);
+ v4i32 __builtin_msa_pckev_w (v4i32, v4i32);
+ v2i64 __builtin_msa_pckev_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_pckod_b (v16i8, v16i8);
+ v8i16 __builtin_msa_pckod_h (v8i16, v8i16);
+ v4i32 __builtin_msa_pckod_w (v4i32, v4i32);
+ v2i64 __builtin_msa_pckod_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_pcnt_b (v16i8);
+ v8i16 __builtin_msa_pcnt_h (v8i16);
+ v4i32 __builtin_msa_pcnt_w (v4i32);
+ v2i64 __builtin_msa_pcnt_d (v2i64);
+ 
+ v16i8 __builtin_msa_sat_s_b (v16i8, imm0_7);
+ v8i16 __builtin_msa_sat_s_h (v8i16, imm0_15);
+ v4i32 __builtin_msa_sat_s_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_sat_s_d (v2i64, imm0_63);
+ 
+ v16u8 __builtin_msa_sat_u_b (v16u8, imm0_7);
+ v8u16 __builtin_msa_sat_u_h (v8u16, imm0_15);
+ v4u32 __builtin_msa_sat_u_w (v4u32, imm0_31);
+ v2u64 __builtin_msa_sat_u_d (v2u64, imm0_63);
+ 
+ v16i8 __builtin_msa_shf_b (v16i8, imm0_255);
+ v8i16 __builtin_msa_shf_h (v8i16, imm0_255);
+ v4i32 __builtin_msa_shf_w (v4i32, imm0_255);
+ 
+ v16i8 __builtin_msa_sld_b (v16i8, v16i8, i32);
+ v8i16 __builtin_msa_sld_h (v8i16, v8i16, i32);
+ v4i32 __builtin_msa_sld_w (v4i32, v4i32, i32);
+ v2i64 __builtin_msa_sld_d (v2i64, v2i64, i32);
+ 
+ v16i8 __builtin_msa_sldi_b (v16i8, v16i8, imm0_15);
+ v8i16 __builtin_msa_sldi_h (v8i16, v8i16, imm0_7);
+ v4i32 __builtin_msa_sldi_w (v4i32, v4i32, imm0_3);
+ v2i64 __builtin_msa_sldi_d (v2i64, v2i64, imm0_1);
+ 
+ v16i8 __builtin_msa_sll_b (v16i8, v16i8);
+ v8i16 __builtin_msa_sll_h (v8i16, v8i16);
+ v4i32 __builtin_msa_sll_w (v4i32, v4i32);
+ v2i64 __builtin_msa_sll_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_slli_b (v16i8, imm0_7);
+ v8i16 __builtin_msa_slli_h (v8i16, imm0_15);
+ v4i32 __builtin_msa_slli_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_slli_d (v2i64, imm0_63);
+ 
+ v16i8 __builtin_msa_splat_b (v16i8, i32);
+ v8i16 __builtin_msa_splat_h (v8i16, i32);
+ v4i32 __builtin_msa_splat_w (v4i32, i32);
+ v2i64 __builtin_msa_splat_d (v2i64, i32);
+ 
+ v16i8 __builtin_msa_splati_b (v16i8, imm0_15);
+ v8i16 __builtin_msa_splati_h (v8i16, imm0_7);
+ v4i32 __builtin_msa_splati_w (v4i32, imm0_3);
+ v2i64 __builtin_msa_splati_d (v2i64, imm0_1);
+ 
+ v16i8 __builtin_msa_sra_b (v16i8, v16i8);
+ v8i16 __builtin_msa_sra_h (v8i16, v8i16);
+ v4i32 __builtin_msa_sra_w (v4i32, v4i32);
+ v2i64 __builtin_msa_sra_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_srai_b (v16i8, imm0_7);
+ v8i16 __builtin_msa_srai_h (v8i16, imm0_15);
+ v4i32 __builtin_msa_srai_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_srai_d (v2i64, imm0_63);
+ 
+ v16i8 __builtin_msa_srar_b (v16i8, v16i8);
+ v8i16 __builtin_msa_srar_h (v8i16, v8i16);
+ v4i32 __builtin_msa_srar_w (v4i32, v4i32);
+ v2i64 __builtin_msa_srar_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_srari_b (v16i8, imm0_7);
+ v8i16 __builtin_msa_srari_h (v8i16, imm0_15);
+ v4i32 __builtin_msa_srari_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_srari_d (v2i64, imm0_63);
+ 
+ v16i8 __builtin_msa_srl_b (v16i8, v16i8);
+ v8i16 __builtin_msa_srl_h (v8i16, v8i16);
+ v4i32 __builtin_msa_srl_w (v4i32, v4i32);
+ v2i64 __builtin_msa_srl_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_srli_b (v16i8, imm0_7);
+ v8i16 __builtin_msa_srli_h (v8i16, imm0_15);
+ v4i32 __builtin_msa_srli_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_srli_d (v2i64, imm0_63);
+ 
+ v16i8 __builtin_msa_srlr_b (v16i8, v16i8);
+ v8i16 __builtin_msa_srlr_h (v8i16, v8i16);
+ v4i32 __builtin_msa_srlr_w (v4i32, v4i32);
+ v2i64 __builtin_msa_srlr_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_srlri_b (v16i8, imm0_7);
+ v8i16 __builtin_msa_srlri_h (v8i16, imm0_15);
+ v4i32 __builtin_msa_srlri_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_srlri_d (v2i64, imm0_63);
+ 
+ void __builtin_msa_st_b (v16i8, void *, imm_n512_511);
+ void __builtin_msa_st_h (v8i16, void *, imm_n1024_1022);
+ void __builtin_msa_st_w (v4i32, void *, imm_n2048_2044);
+ void __builtin_msa_st_d (v2i64, void *, imm_n4096_4088);
+ 
+ v16i8 __builtin_msa_subs_s_b (v16i8, v16i8);
+ v8i16 __builtin_msa_subs_s_h (v8i16, v8i16);
+ v4i32 __builtin_msa_subs_s_w (v4i32, v4i32);
+ v2i64 __builtin_msa_subs_s_d (v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_subs_u_b (v16u8, v16u8);
+ v8u16 __builtin_msa_subs_u_h (v8u16, v8u16);
+ v4u32 __builtin_msa_subs_u_w (v4u32, v4u32);
+ v2u64 __builtin_msa_subs_u_d (v2u64, v2u64);
+ 
+ v16u8 __builtin_msa_subsus_u_b (v16u8, v16i8);
+ v8u16 __builtin_msa_subsus_u_h (v8u16, v8i16);
+ v4u32 __builtin_msa_subsus_u_w (v4u32, v4i32);
+ v2u64 __builtin_msa_subsus_u_d (v2u64, v2i64);
+ 
+ v16i8 __builtin_msa_subsuu_s_b (v16u8, v16u8);
+ v8i16 __builtin_msa_subsuu_s_h (v8u16, v8u16);
+ v4i32 __builtin_msa_subsuu_s_w (v4u32, v4u32);
+ v2i64 __builtin_msa_subsuu_s_d (v2u64, v2u64);
+ 
+ v16i8 __builtin_msa_subv_b (v16i8, v16i8);
+ v8i16 __builtin_msa_subv_h (v8i16, v8i16);
+ v4i32 __builtin_msa_subv_w (v4i32, v4i32);
+ v2i64 __builtin_msa_subv_d (v2i64, v2i64);
+ 
+ v16i8 __builtin_msa_subvi_b (v16i8, imm0_31);
+ v8i16 __builtin_msa_subvi_h (v8i16, imm0_31);
+ v4i32 __builtin_msa_subvi_w (v4i32, imm0_31);
+ v2i64 __builtin_msa_subvi_d (v2i64, imm0_31);
+ 
+ v16i8 __builtin_msa_vshf_b (v16i8, v16i8, v16i8);
+ v8i16 __builtin_msa_vshf_h (v8i16, v8i16, v8i16);
+ v4i32 __builtin_msa_vshf_w (v4i32, v4i32, v4i32);
+ v2i64 __builtin_msa_vshf_d (v2i64, v2i64, v2i64);
+ 
+ v16u8 __builtin_msa_xor_v (v16u8, v16u8);
+ 
+ v16u8 __builtin_msa_xori_b (v16u8, imm0_255);
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,418 ----
+ extern crate proc_macro;
+ extern crate proc_macro2;
+ #[macro_use]
+ extern crate quote;
+ #[macro_use]
+ extern crate syn;
+ 
+ use proc_macro::TokenStream;
+ use std::{fs::File, io::Read, path::Path};
+ use syn::ext::IdentExt;
+ 
+ #[proc_macro]
+ pub fn x86_functions(input: TokenStream) -> TokenStream {
+     functions(input, &["core_arch/src/x86", "core_arch/src/x86_64"])
+ }
+ 
+ #[proc_macro]
+ pub fn arm_functions(input: TokenStream) -> TokenStream {
+     functions(input, &["core_arch/src/arm", "core_arch/src/aarch64"])
+ }
+ 
+ #[proc_macro]
+ pub fn mips_functions(input: TokenStream) -> TokenStream {
+     functions(input, &["core_arch/src/mips"])
+ }
+ 
+ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
+     let dir = Path::new(env!("CARGO_MANIFEST_DIR"));
+     let root = dir.parent().expect("root-dir not found");
+ 
+     let mut files = Vec::new();
+     for dir in dirs {
+         walk(&root.join(dir), &mut files);
+     }
+     assert!(!files.is_empty());
+ 
+     let mut functions = Vec::new();
+     for &mut (ref mut file, ref path) in &mut files {
+         for mut item in file.items.drain(..) {
+             match item {
+                 syn::Item::Fn(f) => functions.push((f, path)),
+                 syn::Item::Mod(ref mut m) => {
+                     if let Some(ref mut m) = m.content {
+                         for i in m.1.drain(..) {
+                             if let syn::Item::Fn(f) = i {
+                                 functions.push((f, path))
+                             }
+                         }
+                     }
+                 }
+                 _ => (),
+             }
+         }
+     }
+     assert!(!functions.is_empty());
+ 
+     let mut tests = std::collections::HashSet::<String>::new();
+     for f in &functions {
+         let id = format!("{}", f.0.sig.ident);
+         if id.starts_with("test_") {
+             tests.insert(id);
+         }
+     }
+     assert!(!tests.is_empty());
+ 
+     functions.retain(|&(ref f, _)| {
+         if let syn::Visibility::Public(_) = f.vis {
+             if f.sig.unsafety.is_some() {
+                 return true;
+             }
+         }
+         false
+     });
+     assert!(!functions.is_empty());
+ 
+     let input = proc_macro2::TokenStream::from(input);
+ 
+     let functions = functions
+         .iter()
+         .map(|&(ref f, path)| {
+             let name = &f.sig.ident;
+             // println!("{}", name);
+             let mut arguments = Vec::new();
+             for input in f.sig.inputs.iter() {
+                 let ty = match *input {
+                     syn::FnArg::Typed(ref c) => &c.ty,
+                     _ => panic!("invalid argument on {}", name),
+                 };
+                 arguments.push(to_type(ty));
+             }
+             let ret = match f.sig.output {
+                 syn::ReturnType::Default => quote! { None },
+                 syn::ReturnType::Type(_, ref t) => {
+                     let ty = to_type(t);
+                     quote! { Some(#ty) }
+                 }
+             };
+             let instrs = find_instrs(&f.attrs);
+             let target_feature = if let Some(i) = find_target_feature(&f.attrs) {
+                 quote! { Some(#i) }
+             } else {
+                 quote! { None }
+             };
+             let required_const = find_required_const(&f.attrs);
+ 
+             // strip leading underscore from fn name when building a test
+             // _mm_foo -> mm_foo such that the test name is test_mm_foo.
+             let test_name_string = format!("{}", name);
+             let mut test_name_id = test_name_string.as_str();
+             while test_name_id.starts_with('_') {
+                 test_name_id = &test_name_id[1..];
+             }
+             let has_test = tests.contains(&format!("test_{}", test_name_id));
+ 
+             quote! {
+                 Function {
+                     name: stringify!(#name),
+                     arguments: &[#(#arguments),*],
+                     ret: #ret,
+                     target_feature: #target_feature,
+                     instrs: &[#(#instrs),*],
+                     file: stringify!(#path),
+                     required_const: &[#(#required_const),*],
+                     has_test: #has_test,
+                 }
+             }
+         })
+         .collect::<Vec<_>>();
+ 
+     let ret = quote! { #input: &[Function] = &[#(#functions),*]; };
+     // println!("{}", ret);
+     ret.into()
+ }
+ 
+ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream {
+     match *t {
+         syn::Type::Path(ref p) => match extract_path_ident(&p.path).to_string().as_ref() {
+             // x86 ...
+             "__m128" => quote! { &M128 },
+             "__m128d" => quote! { &M128D },
+             "__m128i" => quote! { &M128I },
+             "__m256" => quote! { &M256 },
+             "__m256d" => quote! { &M256D },
+             "__m256i" => quote! { &M256I },
+             "__m512" => quote! { &M512 },
+             "__m512d" => quote! { &M512D },
+             "__m512i" => quote! { &M512I },
+             "__mmask8" => quote! { &MMASK8 },
+             "__mmask16" => quote! { &MMASK16 },
+             "_MM_CMPINT_ENUM" => quote! { &MM_CMPINT_ENUM },
+             "_MM_MANTISSA_NORM_ENUM" => quote! { &MM_MANTISSA_NORM_ENUM },
+             "_MM_MANTISSA_SIGN_ENUM" => quote! { &MM_MANTISSA_SIGN_ENUM },
+             "_MM_PERM_ENUM" => quote! { &MM_PERM_ENUM },
+             "__m64" => quote! { &M64 },
+             "bool" => quote! { &BOOL },
+             "f32" => quote! { &F32 },
+             "f64" => quote! { &F64 },
+             "i16" => quote! { &I16 },
+             "i32" => quote! { &I32 },
+             "i64" => quote! { &I64 },
+             "i8" => quote! { &I8 },
+             "u16" => quote! { &U16 },
+             "u32" => quote! { &U32 },
+             "u64" => quote! { &U64 },
+             "u128" => quote! { &U128 },
+             "u8" => quote! { &U8 },
+             "Ordering" => quote! { &ORDERING },
+             "CpuidResult" => quote! { &CPUID },
+ 
+             // arm ...
+             "int8x4_t" => quote! { &I8X4 },
+             "int8x8_t" => quote! { &I8X8 },
+             "int8x8x2_t" => quote! { &I8X8X2 },
+             "int8x8x3_t" => quote! { &I8X8X3 },
+             "int8x8x4_t" => quote! { &I8X8X4 },
+             "int8x16x2_t" => quote! { &I8X16X2 },
+             "int8x16x3_t" => quote! { &I8X16X3 },
+             "int8x16x4_t" => quote! { &I8X16X4 },
+             "int8x16_t" => quote! { &I8X16 },
+             "int16x2_t" => quote! { &I16X2 },
+             "int16x4_t" => quote! { &I16X4 },
+             "int16x8_t" => quote! { &I16X8 },
+             "int32x2_t" => quote! { &I32X2 },
+             "int32x4_t" => quote! { &I32X4 },
+             "int64x1_t" => quote! { &I64X1 },
+             "int64x2_t" => quote! { &I64X2 },
+             "uint8x8_t" => quote! { &U8X8 },
+             "uint8x8x2_t" => quote! { &U8X8X2 },
+             "uint8x16x2_t" => quote! { &U8X16X2 },
+             "uint8x16x3_t" => quote! { &U8X16X3 },
+             "uint8x16x4_t" => quote! { &U8X16X4 },
+             "uint8x8x3_t" => quote! { &U8X8X3 },
+             "uint8x8x4_t" => quote! { &U8X8X4 },
+             "uint8x16_t" => quote! { &U8X16 },
+             "uint16x4_t" => quote! { &U16X4 },
+             "uint16x8_t" => quote! { &U16X8 },
+             "uint32x2_t" => quote! { &U32X2 },
+             "uint32x4_t" => quote! { &U32X4 },
+             "uint64x1_t" => quote! { &U64X1 },
+             "uint64x2_t" => quote! { &U64X2 },
+             "float32x2_t" => quote! { &F32X2 },
+             "float32x4_t" => quote! { &F32X4 },
+             "float64x1_t" => quote! { &F64X1 },
+             "float64x2_t" => quote! { &F64X2 },
+             "poly8x8_t" => quote! { &POLY8X8 },
+             "poly8x8x2_t" => quote! { &POLY8X8X2 },
+             "poly8x8x3_t" => quote! { &POLY8X8X3 },
+             "poly8x8x4_t" => quote! { &POLY8X8X4 },
+             "poly8x16x2_t" => quote! { &POLY8X16X2 },
+             "poly8x16x3_t" => quote! { &POLY8X16X3 },
+             "poly8x16x4_t" => quote! { &POLY8X16X4 },
+             "poly64_t" => quote! { &P64 },
+             "poly64x1_t" => quote! { &POLY64X1 },
+             "poly64x2_t" => quote! { &POLY64X2 },
+             "poly8x16_t" => quote! { &POLY8X16 },
+             "poly16x4_t" => quote! { &POLY16X4 },
+             "poly16x8_t" => quote! { &POLY16X8 },
+             "poly128_t" => quote! { &P128 },
+ 
+             "v16i8" => quote! { &v16i8 },
+             "v8i16" => quote! { &v8i16 },
+             "v4i32" => quote! { &v4i32 },
+             "v2i64" => quote! { &v2i64 },
+             "v16u8" => quote! { &v16u8 },
+             "v8u16" => quote! { &v8u16 },
+             "v4u32" => quote! { &v4u32 },
+             "v2u64" => quote! { &v2u64 },
+             "v8f16" => quote! { &v8f16 },
+             "v4f32" => quote! { &v4f32 },
+             "v2f64" => quote! { &v2f64 },
+ 
+             s => panic!("unsupported type: \"{}\"", s),
+         },
+         syn::Type::Ptr(syn::TypePtr {
+             ref elem,
+             ref mutability,
+             ..
+         })
+         | syn::Type::Reference(syn::TypeReference {
+             ref elem,
+             ref mutability,
+             ..
+         }) => {
+             // Both pointers and references can have a mut token (*mut and &mut)
+             if mutability.is_some() {
+                 let tokens = to_type(&elem);
+                 quote! { &Type::MutPtr(#tokens) }
+             } else {
+                 // If they don't (*const or &) then they are "const"
+                 let tokens = to_type(&elem);
+                 quote! { &Type::ConstPtr(#tokens) }
+             }
+         }
+ 
+         syn::Type::Slice(_) => panic!("unsupported slice"),
+         syn::Type::Array(_) => panic!("unsupported array"),
+         syn::Type::Tuple(_) => quote! { &TUPLE },
+         syn::Type::Never(_) => quote! { &NEVER },
+         _ => panic!("unsupported type"),
+     }
+ }
+ 
+ fn extract_path_ident(path: &syn::Path) -> syn::Ident {
+     if path.leading_colon.is_some() {
+         panic!("unsupported leading colon in path")
+     }
+     if path.segments.len() != 1 {
+         panic!("unsupported path that needs name resolution")
+     }
+     match path.segments.first().expect("segment not found").arguments {
+         syn::PathArguments::None => {}
+         _ => panic!("unsupported path that has path arguments"),
+     }
+     path.segments
+         .first()
+         .expect("segment not found")
+         .ident
+         .clone()
+ }
+ 
+ fn walk(root: &Path, files: &mut Vec<(syn::File, String)>) {
+     for file in root.read_dir().unwrap() {
+         let file = file.unwrap();
+         if file.file_type().unwrap().is_dir() {
+             walk(&file.path(), files);
+             continue;
+         }
+         let path = file.path();
+         if path.extension().and_then(std::ffi::OsStr::to_str) != Some("rs") {
+             continue;
+         }
+ 
+         if path.file_name().and_then(std::ffi::OsStr::to_str) == Some("test.rs") {
+             continue;
+         }
+ 
+         let mut contents = String::new();
+         File::open(&path)
+             .unwrap_or_else(|_| panic!("can't open file at path: {}", path.display()))
+             .read_to_string(&mut contents)
+             .expect("failed to read file to string");
+ 
+         files.push((
+             syn::parse_str::<syn::File>(&contents).expect("failed to parse"),
+             path.display().to_string(),
+         ));
+     }
+ }
+ 
+ fn find_instrs(attrs: &[syn::Attribute]) -> Vec<String> {
+     struct AssertInstr {
+         instr: String,
+     }
+ 
+     // A small custom parser to parse out the instruction in `assert_instr`.
+     //
+     // TODO: should probably just reuse `Invoc` from the `assert-instr-macro`
+     // crate.
+     impl syn::parse::Parse for AssertInstr {
+         fn parse(content: syn::parse::ParseStream) -> syn::Result<Self> {
+             let input;
+             parenthesized!(input in content);
+             let _ = input.parse::<syn::Meta>()?;
+             let _ = input.parse::<Token![,]>()?;
+             let ident = input.parse::<syn::Ident>()?;
+             if ident != "assert_instr" {
+                 return Err(input.error("expected `assert_instr`"));
+             }
+             let instrs;
+             parenthesized!(instrs in input);
+ 
+             let mut instr = String::new();
+             while !instrs.is_empty() {
+                 if let Ok(lit) = instrs.parse::<syn::LitStr>() {
+                     instr.push_str(&lit.value());
+                 } else if let Ok(ident) = instrs.call(syn::Ident::parse_any) {
+                     instr.push_str(&ident.to_string());
+                 } else if instrs.parse::<Token![.]>().is_ok() {
+                     instr.push_str(".");
+                 } else if instrs.parse::<Token![,]>().is_ok() {
+                     // consume everything remaining
+                     drop(instrs.parse::<proc_macro2::TokenStream>());
+                     break;
+                 } else {
+                     return Err(input.error("failed to parse instruction"));
+                 }
+             }
+             Ok(Self { instr })
+         }
+     }
+ 
+     attrs
+         .iter()
+         .filter(|a| a.path.is_ident("cfg_attr"))
+         .filter_map(|a| {
+             syn::parse2::<AssertInstr>(a.tokens.clone())
+                 .ok()
+                 .map(|a| a.instr)
+         })
+         .collect()
+ }
+ 
+ fn find_target_feature(attrs: &[syn::Attribute]) -> Option<syn::Lit> {
+     attrs
+         .iter()
+         .flat_map(|a| {
+             if let Ok(a) = a.parse_meta() {
+                 if let syn::Meta::List(i) = a {
+                     if i.path.is_ident("target_feature") {
+                         return i.nested;
+                     }
+                 }
+             }
+             syn::punctuated::Punctuated::new()
+         })
+         .filter_map(|nested| match nested {
+             syn::NestedMeta::Meta(m) => Some(m),
+             syn::NestedMeta::Lit(_) => None,
+         })
+         .find_map(|m| match m {
+             syn::Meta::NameValue(ref i) if i.path.is_ident("enable") => Some(i.clone().lit),
+             _ => None,
+         })
+ }
+ 
+ fn find_required_const(attrs: &[syn::Attribute]) -> Vec<usize> {
+     attrs
+         .iter()
+         .flat_map(|a| {
+             if a.path.segments[0].ident == "rustc_args_required_const" {
+                 syn::parse::<RustcArgsRequiredConst>(a.tokens.clone().into())
+                     .unwrap()
+                     .args
+             } else {
+                 Vec::new()
+             }
+         })
+         .collect()
+ }
+ 
+ struct RustcArgsRequiredConst {
+     args: Vec<usize>,
+ }
+ 
+ impl syn::parse::Parse for RustcArgsRequiredConst {
+     fn parse(input: syn::parse::ParseStream) -> syn::Result<Self> {
+         let content;
+         parenthesized!(content in input);
+         let list =
+             syn::punctuated::Punctuated::<syn::LitInt, Token![,]>::parse_terminated(&content)?;
+         Ok(Self {
+             args: list
+                 .into_iter()
+                 .map(|a| a.base10_parse::<usize>())
+                 .collect::<syn::Result<_>>()?,
+         })
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,744 ----
+ #![allow(bad_style)]
+ #![allow(unused)]
+ use std::{collections::HashMap, rc::Rc};
+ 
+ use html5ever::{
+     driver::ParseOpts,
+     parse_document,
+     rcdom::{Node, NodeData, RcDom},
+     tendril::TendrilSink,
+     tree_builder::TreeBuilderOpts,
+ };
+ 
+ struct Function {
+     name: &'static str,
+     arguments: &'static [&'static Type],
+     ret: Option<&'static Type>,
+     target_feature: Option<&'static str>,
+     instrs: &'static [&'static str],
+     file: &'static str,
+     required_const: &'static [usize],
+     has_test: bool,
+ }
+ 
+ static F16: Type = Type::PrimFloat(16);
+ static F32: Type = Type::PrimFloat(32);
+ static F64: Type = Type::PrimFloat(64);
+ static I16: Type = Type::PrimSigned(16);
+ static I32: Type = Type::PrimSigned(32);
+ static I64: Type = Type::PrimSigned(64);
+ static I8: Type = Type::PrimSigned(8);
+ static U16: Type = Type::PrimUnsigned(16);
+ static U32: Type = Type::PrimUnsigned(32);
+ static U64: Type = Type::PrimUnsigned(64);
+ static U8: Type = Type::PrimUnsigned(8);
+ static NEVER: Type = Type::Never;
+ 
+ static F16X4: Type = Type::F(16, 4, 1);
+ static F16X4X2: Type = Type::F(16, 4, 2);
+ static F16X4X3: Type = Type::F(16, 4, 3);
+ static F16X4X4: Type = Type::F(16, 4, 4);
+ static F16X8: Type = Type::F(16, 8, 1);
+ static F16X8X2: Type = Type::F(16, 8, 2);
+ static F16X8X3: Type = Type::F(16, 8, 3);
+ static F16X8X4: Type = Type::F(16, 8, 4);
+ static F32X2: Type = Type::F(32, 2, 1);
+ static F32X2X2: Type = Type::F(32, 2, 2);
+ static F32X2X3: Type = Type::F(32, 2, 3);
+ static F32X2X4: Type = Type::F(32, 2, 4);
+ static F32X4: Type = Type::F(32, 4, 1);
+ static F32X4X2: Type = Type::F(32, 4, 2);
+ static F32X4X3: Type = Type::F(32, 4, 3);
+ static F32X4X4: Type = Type::F(32, 4, 4);
+ static F64X1: Type = Type::F(64, 1, 1);
+ static F64X1X2: Type = Type::F(64, 1, 2);
+ static F64X1X3: Type = Type::F(64, 1, 3);
+ static F64X1X4: Type = Type::F(64, 1, 4);
+ static F64X2: Type = Type::F(64, 2, 1);
+ static F64X2X2: Type = Type::F(64, 2, 2);
+ static F64X2X3: Type = Type::F(64, 2, 3);
+ static F64X2X4: Type = Type::F(64, 2, 4);
+ static I16X2: Type = Type::I(16, 2, 1);
+ static I16X4: Type = Type::I(16, 4, 1);
+ static I16X4X2: Type = Type::I(16, 4, 2);
+ static I16X4X3: Type = Type::I(16, 4, 3);
+ static I16X4X4: Type = Type::I(16, 4, 4);
+ static I16X8: Type = Type::I(16, 8, 1);
+ static I16X8X2: Type = Type::I(16, 8, 2);
+ static I16X8X3: Type = Type::I(16, 8, 3);
+ static I16X8X4: Type = Type::I(16, 8, 4);
+ static I32X2: Type = Type::I(32, 2, 1);
+ static I32X2X2: Type = Type::I(32, 2, 2);
+ static I32X2X3: Type = Type::I(32, 2, 3);
+ static I32X2X4: Type = Type::I(32, 2, 4);
+ static I32X4: Type = Type::I(32, 4, 1);
+ static I32X4X2: Type = Type::I(32, 4, 2);
+ static I32X4X3: Type = Type::I(32, 4, 3);
+ static I32X4X4: Type = Type::I(32, 4, 4);
+ static I64X1: Type = Type::I(64, 1, 1);
+ static I64X1X2: Type = Type::I(64, 1, 2);
+ static I64X1X3: Type = Type::I(64, 1, 3);
+ static I64X1X4: Type = Type::I(64, 1, 4);
+ static I64X2: Type = Type::I(64, 2, 1);
+ static I64X2X2: Type = Type::I(64, 2, 2);
+ static I64X2X3: Type = Type::I(64, 2, 3);
+ static I64X2X4: Type = Type::I(64, 2, 4);
+ static I8X16: Type = Type::I(8, 16, 1);
+ static I8X16X2: Type = Type::I(8, 16, 2);
+ static I8X16X3: Type = Type::I(8, 16, 3);
+ static I8X16X4: Type = Type::I(8, 16, 4);
+ static I8X4: Type = Type::I(8, 4, 1);
+ static I8X8: Type = Type::I(8, 8, 1);
+ static I8X8X2: Type = Type::I(8, 8, 2);
+ static I8X8X3: Type = Type::I(8, 8, 3);
+ static I8X8X4: Type = Type::I(8, 8, 4);
+ static P128: Type = Type::PrimPoly(128);
+ static P16: Type = Type::PrimPoly(16);
+ static P16X4X2: Type = Type::P(16, 4, 2);
+ static P16X4X3: Type = Type::P(16, 4, 3);
+ static P16X4X4: Type = Type::P(16, 4, 4);
+ static P16X8X2: Type = Type::P(16, 8, 2);
+ static P16X8X3: Type = Type::P(16, 8, 3);
+ static P16X8X4: Type = Type::P(16, 8, 4);
+ static P64: Type = Type::PrimPoly(64);
+ static P64X1X2: Type = Type::P(64, 1, 2);
+ static P64X1X3: Type = Type::P(64, 1, 3);
+ static P64X1X4: Type = Type::P(64, 1, 4);
+ static P64X2X2: Type = Type::P(64, 2, 2);
+ static P64X2X3: Type = Type::P(64, 2, 3);
+ static P64X2X4: Type = Type::P(64, 2, 4);
+ static P8: Type = Type::PrimPoly(8);
+ static POLY16X4: Type = Type::P(16, 4, 1);
+ static POLY16X8: Type = Type::P(16, 8, 1);
+ static POLY64X1: Type = Type::P(64, 1, 1);
+ static POLY64X2: Type = Type::P(64, 2, 1);
+ static POLY8X16: Type = Type::P(8, 16, 1);
+ static POLY8X16X2: Type = Type::P(8, 16, 2);
+ static POLY8X16X3: Type = Type::P(8, 16, 3);
+ static POLY8X16X4: Type = Type::P(8, 16, 4);
+ static POLY8X8: Type = Type::P(8, 8, 1);
+ static POLY8X8X2: Type = Type::P(8, 8, 2);
+ static POLY8X8X3: Type = Type::P(8, 8, 3);
+ static POLY8X8X4: Type = Type::P(8, 8, 4);
+ static U16X4: Type = Type::U(16, 4, 1);
+ static U16X4X2: Type = Type::U(16, 4, 2);
+ static U16X4X3: Type = Type::U(16, 4, 3);
+ static U16X4X4: Type = Type::U(16, 4, 4);
+ static U16X8: Type = Type::U(16, 8, 1);
+ static U16X8X2: Type = Type::U(16, 8, 2);
+ static U16X8X3: Type = Type::U(16, 8, 3);
+ static U16X8X4: Type = Type::U(16, 8, 4);
+ static U32X2: Type = Type::U(32, 2, 1);
+ static U32X2X2: Type = Type::U(32, 2, 2);
+ static U32X2X3: Type = Type::U(32, 2, 3);
+ static U32X2X4: Type = Type::U(32, 2, 4);
+ static U32X4: Type = Type::U(32, 4, 1);
+ static U32X4X2: Type = Type::U(32, 4, 2);
+ static U32X4X3: Type = Type::U(32, 4, 3);
+ static U32X4X4: Type = Type::U(32, 4, 4);
+ static U64X1: Type = Type::U(64, 1, 1);
+ static U64X1X2: Type = Type::U(64, 1, 2);
+ static U64X1X3: Type = Type::U(64, 1, 3);
+ static U64X1X4: Type = Type::U(64, 1, 4);
+ static U64X2: Type = Type::U(64, 2, 1);
+ static U64X2X2: Type = Type::U(64, 2, 2);
+ static U64X2X3: Type = Type::U(64, 2, 3);
+ static U64X2X4: Type = Type::U(64, 2, 4);
+ static U8X16: Type = Type::U(8, 16, 1);
+ static U8X16X2: Type = Type::U(8, 16, 2);
+ static U8X16X3: Type = Type::U(8, 16, 3);
+ static U8X16X4: Type = Type::U(8, 16, 4);
+ static U8X8: Type = Type::U(8, 8, 1);
+ static U8X8X2: Type = Type::U(8, 8, 2);
+ static U8X8X3: Type = Type::U(8, 8, 3);
+ static U8X8X4: Type = Type::U(8, 8, 4);
+ 
+ #[derive(Debug, Copy, Clone, PartialEq)]
+ enum Type {
+     PrimFloat(u8),
+     PrimSigned(u8),
+     PrimUnsigned(u8),
+     PrimPoly(u8),
+     MutPtr(&'static Type),
+     ConstPtr(&'static Type),
+     I(u8, u8, u8),
+     U(u8, u8, u8),
+     P(u8, u8, u8),
+     F(u8, u8, u8),
+     Never,
+ }
+ 
+ stdarch_verify::arm_functions!(static FUNCTIONS);
+ 
+ macro_rules! bail {
+     ($($t:tt)*) => (return Err(format!($($t)*)))
+ }
+ 
+ #[test]
+ fn verify_all_signatures() {
+     // This is a giant HTML blob downloaded from
+     // https://developer.arm.com/technologies/neon/intrinsics which contains all
+     // NEON intrinsics at least. We do manual HTML parsing below.
+     let html = include_bytes!("../arm-intrinsics.html");
+     let mut html = &html[..];
+     let opts = ParseOpts {
+         tree_builder: TreeBuilderOpts {
+             drop_doctype: true,
+             ..Default::default()
+         },
+         ..Default::default()
+     };
+     let dom = parse_document(RcDom::default(), opts)
+         .from_utf8()
+         .read_from(&mut html)
+         .unwrap();
+ 
+     let accordion = find_accordion(&dom.document).unwrap();
+     let map = parse_intrinsics(&accordion);
+ 
+     let mut all_valid = true;
+     'outer: for rust in FUNCTIONS {
+         if !rust.has_test {
+             let skip = [
+                 "vaddq_s64",
+                 "vaddq_u64",
+                 "vrsqrte_f32",
+                 "vtbl1_s8",
+                 "vtbl1_u8",
+                 "vtbl1_p8",
+                 "vtbl2_s8",
+                 "vtbl2_u8",
+                 "vtbl2_p8",
+                 "vtbl3_s8",
+                 "vtbl3_u8",
+                 "vtbl3_p8",
+                 "vtbl4_s8",
+                 "vtbl4_u8",
+                 "vtbl4_p8",
+                 "vtbx1_s8",
+                 "vtbx1_u8",
+                 "vtbx1_p8",
+                 "vtbx2_s8",
+                 "vtbx2_u8",
+                 "vtbx2_p8",
+                 "vtbx3_s8",
+                 "vtbx3_u8",
+                 "vtbx3_p8",
+                 "vtbx4_s8",
+                 "vtbx4_u8",
+                 "vtbx4_p8",
+                 "udf",
+                 "_clz_u8",
+                 "_clz_u16",
+                 "_clz_u32",
+                 "_rbit_u32",
+                 "_rev_u16",
+                 "_rev_u32",
+                 "__breakpoint",
+                 "vpminq_f32",
+                 "vpminq_f64",
+                 "vpmaxq_f32",
+                 "vpmaxq_f64",
+                 "vcombine_s8",
+                 "vcombine_s16",
+                 "vcombine_s32",
+                 "vcombine_s64",
+                 "vcombine_u8",
+                 "vcombine_u16",
+                 "vcombine_u32",
+                 "vcombine_u64",
+                 "vcombine_p64",
+                 "vcombine_f32",
+                 "vcombine_p8",
+                 "vcombine_p16",
+                 "vcombine_f64",
+                 "vtbl1_s8",
+                 "vtbl1_u8",
+                 "vtbl1_p8",
+                 "vtbl2_s8",
+                 "vtbl2_u8",
+                 "vtbl2_p8",
+                 "vtbl3_s8",
+                 "vtbl3_u8",
+                 "vtbl3_p8",
+                 "vtbl4_s8",
+                 "vtbl4_u8",
+                 "vtbl4_p8",
+                 "vtbx1_s8",
+                 "vtbx1_u8",
+                 "vtbx1_p8",
+                 "vtbx2_s8",
+                 "vtbx2_u8",
+                 "vtbx2_p8",
+                 "vtbx3_s8",
+                 "vtbx3_u8",
+                 "vtbx3_p8",
+                 "vtbx4_s8",
+                 "vtbx4_u8",
+                 "vtbx4_p8",
+                 "vqtbl1_s8",
+                 "vqtbl1q_s8",
+                 "vqtbl1_u8",
+                 "vqtbl1q_u8",
+                 "vqtbl1_p8",
+                 "vqtbl1q_p8",
+                 "vqtbx1_s8",
+                 "vqtbx1q_s8",
+                 "vqtbx1_u8",
+                 "vqtbx1q_u8",
+                 "vqtbx1_p8",
+                 "vqtbx1q_p8",
+                 "vqtbl2_s8",
+                 "vqtbl2q_s8",
+                 "vqtbl2_u8",
+                 "vqtbl2q_u8",
+                 "vqtbl2_p8",
+                 "vqtbl2q_p8",
+                 "vqtbx2_s8",
+                 "vqtbx2q_s8",
+                 "vqtbx2_u8",
+                 "vqtbx2q_u8",
+                 "vqtbx2_p8",
+                 "vqtbx2q_p8",
+                 "vqtbl3_s8",
+                 "vqtbl3q_s8",
+                 "vqtbl3_u8",
+                 "vqtbl3q_u8",
+                 "vqtbl3_p8",
+                 "vqtbl3q_p8",
+                 "vqtbx3_s8",
+                 "vqtbx3q_s8",
+                 "vqtbx3_u8",
+                 "vqtbx3q_u8",
+                 "vqtbx3_p8",
+                 "vqtbx3q_p8",
+                 "vqtbl4_s8",
+                 "vqtbl4q_s8",
+                 "vqtbl4_u8",
+                 "vqtbl4q_u8",
+                 "vqtbl4_p8",
+                 "vqtbl4q_p8",
+                 "vqtbx4_s8",
+                 "vqtbx4q_s8",
+                 "vqtbx4_u8",
+                 "vqtbx4q_u8",
+                 "vqtbx4_p8",
+                 "vqtbx4q_p8",
+                 "brk",
+                 "_rev_u64",
+                 "_clz_u64",
+                 "_rbit_u64",
+                 "_cls_u32",
+                 "_cls_u64",
+                 "_prefetch",
+             ];
+             if !skip.contains(&rust.name) {
+                 println!(
+                     "missing run-time test named `test_{}` for `{}`",
+                     {
+                         let mut id = rust.name;
+                         while id.starts_with('_') {
+                             id = &id[1..];
+                         }
+                         id
+                     },
+                     rust.name
+                 );
+                 all_valid = false;
+             }
+         }
+ 
+         // Skip some intrinsics that aren't NEON and are located in different
+         // places than the whitelists below.
+         match rust.name {
+             "brk" | "__breakpoint" | "udf" | "_prefetch" => continue,
+             _ => {}
+         }
+         let arm = match map.get(rust.name) {
+             Some(i) => i,
+             None => {
+                 // Skip all these intrinsics as they're not listed in NEON
+                 // descriptions online.
+                 //
+                 // TODO: we still need to verify these intrinsics or find a
+                 // reference for them, need to figure out where though!
+                 if !rust.file.ends_with("dsp.rs\"")
+                     && !rust.file.ends_with("cmsis.rs\"")
+                     && !rust.file.ends_with("v6.rs\"")
+                     && !rust.file.ends_with("v7.rs\"")
+                     && !rust.file.ends_with("v8.rs\"")
+                     && !rust.file.ends_with("tme.rs\"")
+                 {
+                     println!(
+                         "missing arm definition for {:?} in {}",
+                         rust.name, rust.file
+                     );
+                     all_valid = false;
+                 }
+                 continue;
+             }
+         };
+ 
+         if let Err(e) = matches(rust, arm) {
+             println!("failed to verify `{}`", rust.name);
+             println!("  * {}", e);
+             all_valid = false;
+         }
+     }
+     assert!(all_valid);
+ }
+ 
+ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
+     if rust.ret != arm.ret.as_ref() {
+         bail!("mismatched return value")
+     }
+     if rust.arguments.len() != arm.arguments.len() {
+         bail!("mismatched argument lengths");
+     }
+ 
+     let mut nconst = 0;
+     let iter = rust.arguments.iter().zip(&arm.arguments).enumerate();
+     for (i, (rust_ty, (arm, arm_const))) in iter {
+         if *rust_ty != arm {
+             bail!("mismatched arguments")
+         }
+         if *arm_const {
+             nconst += 1;
+             if !rust.required_const.contains(&i) {
+                 bail!("argument const mismatch");
+             }
+         }
+     }
+     if nconst != rust.required_const.len() {
+         bail!("wrong number of const arguments");
+     }
+ 
+     if rust.instrs.is_empty() {
+         bail!(
+             "instruction not listed for `{}`, but arm lists {:?}",
+             rust.name,
+             arm.instruction
+         );
+     } else if false
+     /* not super reliable, but can be used to manually check */
+     {
+         for instr in rust.instrs {
+             if arm.instruction.starts_with(instr) {
+                 continue;
+             }
+             // sometimes arm says `foo` and disassemblers say `vfoo`, or
+             // sometimes disassemblers say `vfoo` and arm says `sfoo` or `ffoo`
+             if instr.starts_with("v")
+                 && (arm.instruction.starts_with(&instr[1..])
+                     || arm.instruction[1..].starts_with(&instr[1..]))
+             {
+                 continue;
+             }
+             bail!(
+                 "arm failed to list `{}` as an instruction for `{}` in {:?}",
+                 instr,
+                 rust.name,
+                 arm.instruction,
+             );
+         }
+     }
+ 
+     // TODO: verify `target_feature`.
+ 
+     Ok(())
+ }
+ 
+ fn find_accordion(node: &Rc<Node>) -> Option<Rc<Node>> {
+     if let NodeData::Element { attrs, .. } = &node.data {
+         for attr in attrs.borrow().iter() {
+             if attr.name.local.eq_str_ignore_ascii_case("class") {
+                 if attr.value.to_string() == "intrinsic-accordion" {
+                     return Some(node.clone());
+                 }
+             }
+         }
+     }
+ 
+     node.children
+         .borrow()
+         .iter()
+         .filter_map(|node| find_accordion(node))
+         .next()
+ }
+ 
+ #[derive(PartialEq)]
+ struct Intrinsic {
+     name: String,
+     ret: Option<Type>,
+     arguments: Vec<(Type, bool)>,
+     instruction: String,
+ }
+ 
+ fn parse_intrinsics(node: &Rc<Node>) -> HashMap<String, Intrinsic> {
+     let mut ret = HashMap::new();
+     for child in node.children.borrow().iter() {
+         if let NodeData::Element { .. } = child.data {
+             let f = parse_intrinsic(child);
+             ret.insert(f.name.clone(), f);
+         }
+     }
+     return ret;
+ }
+ 
+ fn parse_intrinsic(node: &Rc<Node>) -> Intrinsic {
+     // <div class='intrinsic'>
+     //  <input>...</input>
+     //  <label for=$name>
+     //    <div>
+     //      $signature...
+     //  <article>
+     //    ...
+ 
+     let children = node.children.borrow();
+     let mut children = children.iter().filter(|node| match node.data {
+         NodeData::Element { .. } => true,
+         _ => false,
+     });
+     let _input = children.next().expect("no <input>");
+     let label = children.next().expect("no <label>");
+     let article = children.next().expect("no <article>");
+     assert!(children.next().is_none());
+ 
+     // Find `for="..."` in `<label>`
+     let name = match &label.data {
+         NodeData::Element { attrs, .. } => attrs
+             .borrow()
+             .iter()
+             .filter(|attr| attr.name.local.eq_str_ignore_ascii_case("for"))
+             .map(|attr| attr.value.to_string())
+             .next()
+             .expect("no `for` attribute"),
+         _ => panic!(),
+     };
+ 
+     // Find contents of inner `<div>` in `<label>`
+     let label_children = label.children.borrow();
+     let mut label_children = label_children.iter().filter(|node| match node.data {
+         NodeData::Element { .. } => true,
+         _ => false,
+     });
+     let label_div = label_children.next().expect("no <div> in <label>");
+     assert!(label_children.next().is_none());
+     let text = label_div.children.borrow();
+     let mut text = text.iter().filter_map(|node| match &node.data {
+         NodeData::Text { contents } => Some(contents.borrow().to_string()),
+         _ => None,
+     });
+     let ret = text.next().unwrap();
+     let ret = ret.trim();
+     let args = text.next().unwrap();
+     let args = args.trim();
+     assert!(text.next().is_none());
+ 
+     // Find the instruction within the article
+     let article_children = article.children.borrow();
+     let mut article_children = article_children.iter().filter(|node| match node.data {
+         NodeData::Element { .. } => true,
+         _ => false,
+     });
+     let mut instruction = None;
+     while let Some(child) = article_children.next() {
+         let mut header = String::new();
+         collect_text(&mut header, child);
+         if !header.ends_with(" Instruction") {
+             continue;
+         }
+         let next = article_children.next().expect("no next child");
+         assert!(instruction.is_none());
+         let mut instr = String::new();
+         collect_text(&mut instr, &next);
+         instruction = Some(instr);
+     }
+ 
+     let instruction = match instruction {
+         Some(s) => s.trim().to_lowercase(),
+         None => panic!("can't find instruction for `{}`", name),
+     };
+ 
+     Intrinsic {
+         name,
+         ret: if ret == "void" {
+             None
+         } else {
+             Some(parse_ty(ret))
+         },
+         instruction,
+         arguments: args // "(...)"
+             .trim_start_matches("(") // "...)"
+             .trim_end_matches(")") // "..."
+             .split(",") // " Type name ", ".."
+             .map(|s| s.trim()) // "Type name"
+             .map(|s| s.rsplitn(2, ' ').nth(1).unwrap()) // "Type"
+             .map(|s| {
+                 let const_ = "const ";
+                 if s.starts_with(const_) {
+                     (parse_ty(&s[const_.len()..]), true)
+                 } else {
+                     (parse_ty(s), false)
+                 }
+             })
+             .collect(),
+     }
+ }
+ 
+ fn parse_ty(s: &str) -> Type {
+     let suffix = " const *";
+     if s.ends_with(suffix) {
+         Type::ConstPtr(parse_ty_base(&s[..s.len() - suffix.len()]))
+     } else if s.ends_with(" *") {
+         Type::MutPtr(parse_ty_base(&s[..s.len() - 2]))
+     } else {
+         *parse_ty_base(s)
+     }
+ }
+ 
+ fn parse_ty_base(s: &str) -> &'static Type {
+     match s {
+         "float16_t" => &F16,
+         "float16x4_t" => &F16X4,
+         "float16x4x2_t" => &F16X4X2,
+         "float16x4x3_t" => &F16X4X3,
+         "float16x4x4_t" => &F16X4X4,
+         "float16x8_t" => &F16X8,
+         "float16x8x2_t" => &F16X8X2,
+         "float16x8x3_t" => &F16X8X3,
+         "float16x8x4_t" => &F16X8X4,
+         "float32_t" => &F32,
+         "float32x2_t" => &F32X2,
+         "float32x2x2_t" => &F32X2X2,
+         "float32x2x3_t" => &F32X2X3,
+         "float32x2x4_t" => &F32X2X4,
+         "float32x4_t" => &F32X4,
+         "float32x4x2_t" => &F32X4X2,
+         "float32x4x3_t" => &F32X4X3,
+         "float32x4x4_t" => &F32X4X4,
+         "float64_t" => &F64,
+         "float64x1_t" => &F64X1,
+         "float64x1x2_t" => &F64X1X2,
+         "float64x1x3_t" => &F64X1X3,
+         "float64x1x4_t" => &F64X1X4,
+         "float64x2_t" => &F64X2,
+         "float64x2x2_t" => &F64X2X2,
+         "float64x2x3_t" => &F64X2X3,
+         "float64x2x4_t" => &F64X2X4,
+         "int16_t" => &I16,
+         "int16x2_t" => &I16X2,
+         "int16x4_t" => &I16X4,
+         "int16x4x2_t" => &I16X4X2,
+         "int16x4x3_t" => &I16X4X3,
+         "int16x4x4_t" => &I16X4X4,
+         "int16x8_t" => &I16X8,
+         "int16x8x2_t" => &I16X8X2,
+         "int16x8x3_t" => &I16X8X3,
+         "int16x8x4_t" => &I16X8X4,
+         "int32_t" | "int" => &I32,
+         "int32x2_t" => &I32X2,
+         "int32x2x2_t" => &I32X2X2,
+         "int32x2x3_t" => &I32X2X3,
+         "int32x2x4_t" => &I32X2X4,
+         "int32x4_t" => &I32X4,
+         "int32x4x2_t" => &I32X4X2,
+         "int32x4x3_t" => &I32X4X3,
+         "int32x4x4_t" => &I32X4X4,
+         "int64_t" => &I64,
+         "int64x1_t" => &I64X1,
+         "int64x1x2_t" => &I64X1X2,
+         "int64x1x3_t" => &I64X1X3,
+         "int64x1x4_t" => &I64X1X4,
+         "int64x2_t" => &I64X2,
+         "int64x2x2_t" => &I64X2X2,
+         "int64x2x3_t" => &I64X2X3,
+         "int64x2x4_t" => &I64X2X4,
+         "int8_t" => &I8,
+         "int8x16_t" => &I8X16,
+         "int8x16x2_t" => &I8X16X2,
+         "int8x16x3_t" => &I8X16X3,
+         "int8x16x4_t" => &I8X16X4,
+         "int8x4_t" => &I8X4,
+         "int8x8_t" => &I8X8,
+         "int8x8x2_t" => &I8X8X2,
+         "int8x8x3_t" => &I8X8X3,
+         "int8x8x4_t" => &I8X8X4,
+         "poly128_t" => &P128,
+         "poly16_t" => &P16,
+         "poly16x4_t" => &POLY16X4,
+         "poly16x4x2_t" => &P16X4X2,
+         "poly16x4x3_t" => &P16X4X3,
+         "poly16x4x4_t" => &P16X4X4,
+         "poly16x8_t" => &POLY16X8,
+         "poly16x8x2_t" => &P16X8X2,
+         "poly16x8x3_t" => &P16X8X3,
+         "poly16x8x4_t" => &P16X8X4,
+         "poly64_t" => &P64,
+         "poly64x1_t" => &POLY64X1,
+         "poly64x1x2_t" => &P64X1X2,
+         "poly64x1x3_t" => &P64X1X3,
+         "poly64x1x4_t" => &P64X1X4,
+         "poly64x2_t" => &POLY64X2,
+         "poly64x2x2_t" => &P64X2X2,
+         "poly64x2x3_t" => &P64X2X3,
+         "poly64x2x4_t" => &P64X2X4,
+         "poly8_t" => &P8,
+         "poly8x16_t" => &POLY8X16,
+         "poly8x16x2_t" => &POLY8X16X2,
+         "poly8x16x3_t" => &POLY8X16X3,
+         "poly8x16x4_t" => &POLY8X16X4,
+         "poly8x8_t" => &POLY8X8,
+         "poly8x8x2_t" => &POLY8X8X2,
+         "poly8x8x3_t" => &POLY8X8X3,
+         "poly8x8x4_t" => &POLY8X8X4,
+         "uint16_t" => &U16,
+         "uint16x4_t" => &U16X4,
+         "uint16x4x2_t" => &U16X4X2,
+         "uint16x4x3_t" => &U16X4X3,
+         "uint16x4x4_t" => &U16X4X4,
+         "uint16x8_t" => &U16X8,
+         "uint16x8x2_t" => &U16X8X2,
+         "uint16x8x3_t" => &U16X8X3,
+         "uint16x8x4_t" => &U16X8X4,
+         "uint32_t" => &U32,
+         "uint32x2_t" => &U32X2,
+         "uint32x2x2_t" => &U32X2X2,
+         "uint32x2x3_t" => &U32X2X3,
+         "uint32x2x4_t" => &U32X2X4,
+         "uint32x4_t" => &U32X4,
+         "uint32x4x2_t" => &U32X4X2,
+         "uint32x4x3_t" => &U32X4X3,
+         "uint32x4x4_t" => &U32X4X4,
+         "uint64_t" => &U64,
+         "uint64x1_t" => &U64X1,
+         "uint64x1x2_t" => &U64X1X2,
+         "uint64x1x3_t" => &U64X1X3,
+         "uint64x1x4_t" => &U64X1X4,
+         "uint64x2_t" => &U64X2,
+         "uint64x2x2_t" => &U64X2X2,
+         "uint64x2x3_t" => &U64X2X3,
+         "uint64x2x4_t" => &U64X2X4,
+         "uint8_t" => &U8,
+         "uint8x16_t" => &U8X16,
+         "uint8x16x2_t" => &U8X16X2,
+         "uint8x16x3_t" => &U8X16X3,
+         "uint8x16x4_t" => &U8X16X4,
+         "uint8x8_t" => &U8X8,
+         "uint8x8x2_t" => &U8X8X2,
+         "uint8x8x3_t" => &U8X8X3,
+         "uint8x8x4_t" => &U8X8X4,
+ 
+         _ => panic!("failed to parse html type {:?}", s),
+     }
+ }
+ 
+ fn collect_text(s: &mut String, node: &Node) {
+     if let NodeData::Text { contents } = &node.data {
+         s.push_str(" ");
+         s.push_str(&contents.borrow().to_string());
+     }
+     for child in node.children.borrow().iter() {
+         collect_text(s, child);
+     }
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,364 ----
+ //! Verification of MIPS MSA intrinsics
+ #![feature(try_trait)]
+ #![allow(bad_style, unused)]
+ 
+ // This file is obtained from
+ // https://gcc.gnu.org/onlinedocs//gcc/MIPS-SIMD-Architecture-Built-in-Functions.html
+ static HEADER: &str = include_str!("../mips-msa.h");
+ 
+ stdarch_verify::mips_functions!(static FUNCTIONS);
+ 
+ struct Function {
+     name: &'static str,
+     arguments: &'static [&'static Type],
+     ret: Option<&'static Type>,
+     target_feature: Option<&'static str>,
+     instrs: &'static [&'static str],
+     file: &'static str,
+     required_const: &'static [usize],
+     has_test: bool,
+ }
+ 
+ static F16: Type = Type::PrimFloat(16);
+ static F32: Type = Type::PrimFloat(32);
+ static F64: Type = Type::PrimFloat(64);
+ static I8: Type = Type::PrimSigned(8);
+ static I16: Type = Type::PrimSigned(16);
+ static I32: Type = Type::PrimSigned(32);
+ static I64: Type = Type::PrimSigned(64);
+ static U8: Type = Type::PrimUnsigned(8);
+ static U16: Type = Type::PrimUnsigned(16);
+ static U32: Type = Type::PrimUnsigned(32);
+ static U64: Type = Type::PrimUnsigned(64);
+ static NEVER: Type = Type::Never;
+ static TUPLE: Type = Type::Tuple;
+ static v16i8: Type = Type::I(8, 16, 1);
+ static v8i16: Type = Type::I(16, 8, 1);
+ static v4i32: Type = Type::I(32, 4, 1);
+ static v2i64: Type = Type::I(64, 2, 1);
+ static v16u8: Type = Type::U(8, 16, 1);
+ static v8u16: Type = Type::U(16, 8, 1);
+ static v4u32: Type = Type::U(32, 4, 1);
+ static v2u64: Type = Type::U(64, 2, 1);
+ static v8f16: Type = Type::F(16, 8, 1);
+ static v4f32: Type = Type::F(32, 4, 1);
+ static v2f64: Type = Type::F(64, 2, 1);
+ 
+ #[derive(Debug, Copy, Clone, PartialEq)]
+ enum Type {
+     PrimFloat(u8),
+     PrimSigned(u8),
+     PrimUnsigned(u8),
+     PrimPoly(u8),
+     MutPtr(&'static Type),
+     ConstPtr(&'static Type),
+     Tuple,
+     I(u8, u8, u8),
+     U(u8, u8, u8),
+     P(u8, u8, u8),
+     F(u8, u8, u8),
+     Never,
+ }
+ 
+ #[derive(Copy, Clone, Debug, PartialEq)]
+ #[allow(non_camel_case_types)]
+ enum MsaTy {
+     v16i8,
+     v8i16,
+     v4i32,
+     v2i64,
+     v16u8,
+     v8u16,
+     v4u32,
+     v2u64,
+     v8f16,
+     v4f32,
+     v2f64,
+     imm0_1,
+     imm0_3,
+     imm0_7,
+     imm0_15,
+     imm0_31,
+     imm0_63,
+     imm0_255,
+     imm_n16_15,
+     imm_n512_511,
+     imm_n1024_1022,
+     imm_n2048_2044,
+     imm_n4096_4088,
+     i32,
+     u32,
+     i64,
+     u64,
+     Void,
+     MutVoidPtr,
+ }
+ 
+ impl<'a> From<&'a str> for MsaTy {
+     fn from(s: &'a str) -> MsaTy {
+         match s {
+             "v16i8" => MsaTy::v16i8,
+             "v8i16" => MsaTy::v8i16,
+             "v4i32" => MsaTy::v4i32,
+             "v2i64" => MsaTy::v2i64,
+             "v16u8" => MsaTy::v16u8,
+             "v8u16" => MsaTy::v8u16,
+             "v4u32" => MsaTy::v4u32,
+             "v2u64" => MsaTy::v2u64,
+             "v8f16" => MsaTy::v8f16,
+             "v4f32" => MsaTy::v4f32,
+             "v2f64" => MsaTy::v2f64,
+             "imm0_1" => MsaTy::imm0_1,
+             "imm0_3" => MsaTy::imm0_3,
+             "imm0_7" => MsaTy::imm0_7,
+             "imm0_15" => MsaTy::imm0_15,
+             "imm0_31" => MsaTy::imm0_31,
+             "imm0_63" => MsaTy::imm0_63,
+             "imm0_255" => MsaTy::imm0_255,
+             "imm_n16_15" => MsaTy::imm_n16_15,
+             "imm_n512_511" => MsaTy::imm_n512_511,
+             "imm_n1024_1022" => MsaTy::imm_n1024_1022,
+             "imm_n2048_2044" => MsaTy::imm_n2048_2044,
+             "imm_n4096_4088" => MsaTy::imm_n4096_4088,
+             "i32" => MsaTy::i32,
+             "u32" => MsaTy::u32,
+             "i64" => MsaTy::i64,
+             "u64" => MsaTy::u64,
+             "void" => MsaTy::Void,
+             "void *" => MsaTy::MutVoidPtr,
+             v => panic!("unknown ty: \"{}\"", v),
+         }
+     }
+ }
+ 
+ #[derive(Debug, Clone)]
+ struct MsaIntrinsic {
+     id: String,
+     arg_tys: Vec<MsaTy>,
+     ret_ty: MsaTy,
+     instruction: String,
+ }
+ 
+ impl std::convert::TryFrom<&'static str> for MsaIntrinsic {
+     // The intrinsics are just C function declarations of the form:
+     // $ret_ty __builtin_${fn_id}($($arg_ty),*);
+     type Error = std::option::NoneError;
+     fn try_from(line: &'static str) -> Result<Self, Self::Error> {
+         let first_whitespace = line.find(char::is_whitespace)?;
+         let ret_ty = &line[0..first_whitespace];
+         let ret_ty = MsaTy::from(ret_ty);
+ 
+         let first_parentheses = line.find('(')?;
+         assert!(first_parentheses > first_whitespace);
+         let id = &line[first_whitespace + 1..first_parentheses].trim();
+         assert!(id.starts_with("__builtin"));
+         let mut id_str = "_".to_string();
+         id_str += &id[9..];
+         let id = id_str;
+ 
+         let mut arg_tys = Vec::new();
+ 
+         let last_parentheses = line.find(')')?;
+         for arg in (&line[first_parentheses + 1..last_parentheses]).split(',') {
+             let arg = arg.trim();
+             arg_tys.push(MsaTy::from(arg));
+         }
+ 
+         // The instruction is the intrinsic name without the __msa_ prefix.
+         let instruction = &id[6..];
+         let mut instruction = instruction.to_string();
+         // With all underscores but the first one replaced with a `.`
+         if let Some(first_underscore) = instruction.find('_') {
+             let postfix = instruction[first_underscore + 1..].replace('_', ".");
+             instruction = instruction[0..=first_underscore].to_string();
+             instruction += &postfix;
+         }
+ 
+         Ok(MsaIntrinsic {
+             id,
+             ret_ty,
+             arg_tys,
+             instruction,
+         })
+     }
+ }
+ 
+ #[test]
+ fn verify_all_signatures() {
+     // Parse the C intrinsic header file:
+     let mut intrinsics = std::collections::HashMap::<String, MsaIntrinsic>::new();
+     for line in HEADER.lines() {
+         if line.is_empty() {
+             continue;
+         }
+ 
+         use std::convert::TryFrom;
+         let intrinsic: MsaIntrinsic =
+             TryFrom::try_from(line).expect(&format!("failed to parse line: \"{}\"", line));
+         assert!(!intrinsics.contains_key(&intrinsic.id));
+         intrinsics.insert(intrinsic.id.clone(), intrinsic);
+     }
+ 
+     let mut all_valid = true;
+     for rust in FUNCTIONS {
+         if !rust.has_test {
+             let skip = [
+                 "__msa_ceqi_d",
+                 "__msa_cfcmsa",
+                 "__msa_clei_s_d",
+                 "__msa_clti_s_d",
+                 "__msa_ctcmsa",
+                 "__msa_ldi_d",
+                 "__msa_maxi_s_d",
+                 "__msa_mini_s_d",
+                 "break_",
+             ];
+             if !skip.contains(&rust.name) {
+                 println!(
+                     "missing run-time test named `test_{}` for `{}`",
+                     {
+                         let mut id = rust.name;
+                         while id.starts_with('_') {
+                             id = &id[1..];
+                         }
+                         id
+                     },
+                     rust.name
+                 );
+                 all_valid = false;
+             }
+         }
+ 
+         // Skip some intrinsics that aren't part of MSA
+         match rust.name {
+             "break_" => continue,
+             _ => {}
+         }
+         let mips = match intrinsics.get(rust.name) {
+             Some(i) => i,
+             None => {
+                 eprintln!(
+                     "missing mips definition for {:?} in {}",
+                     rust.name, rust.file
+                 );
+                 all_valid = false;
+                 continue;
+             }
+         };
+ 
+         if let Err(e) = matches(rust, mips) {
+             println!("failed to verify `{}`", rust.name);
+             println!("  * {}", e);
+             all_valid = false;
+         }
+     }
+     assert!(all_valid);
+ }
+ 
+ fn matches(rust: &Function, mips: &MsaIntrinsic) -> Result<(), String> {
+     macro_rules! bail {
+         ($($t:tt)*) => (return Err(format!($($t)*)))
+     }
+ 
+     if rust.ret.is_none() && mips.ret_ty != MsaTy::Void {
+         bail!("mismatched return value")
+     }
+ 
+     if rust.arguments.len() != mips.arg_tys.len() {
+         bail!("mismatched argument lengths");
+     }
+ 
+     let mut nconst = 0;
+     for (i, (rust_arg, mips_arg)) in rust.arguments.iter().zip(mips.arg_tys.iter()).enumerate() {
+         match mips_arg {
+             MsaTy::v16i8 if **rust_arg == v16i8 => (),
+             MsaTy::v8i16 if **rust_arg == v8i16 => (),
+             MsaTy::v4i32 if **rust_arg == v4i32 => (),
+             MsaTy::v2i64 if **rust_arg == v2i64 => (),
+             MsaTy::v16u8 if **rust_arg == v16u8 => (),
+             MsaTy::v8u16 if **rust_arg == v8u16 => (),
+             MsaTy::v4u32 if **rust_arg == v4u32 => (),
+             MsaTy::v2u64 if **rust_arg == v2u64 => (),
+             MsaTy::v4f32 if **rust_arg == v4f32 => (),
+             MsaTy::v2f64 if **rust_arg == v2f64 => (),
+             MsaTy::imm0_1
+             | MsaTy::imm0_3
+             | MsaTy::imm0_7
+             | MsaTy::imm0_15
+             | MsaTy::imm0_31
+             | MsaTy::imm0_63
+             | MsaTy::imm0_255
+             | MsaTy::imm_n16_15
+             | MsaTy::imm_n512_511
+             | MsaTy::imm_n1024_1022
+             | MsaTy::imm_n2048_2044
+             | MsaTy::imm_n4096_4088
+                 if **rust_arg == I32 =>
+             {
+                 ()
+             }
+             MsaTy::i32 if **rust_arg == I32 => (),
+             MsaTy::i64 if **rust_arg == I64 => (),
+             MsaTy::u32 if **rust_arg == U32 => (),
+             MsaTy::u64 if **rust_arg == U64 => (),
+             MsaTy::MutVoidPtr if **rust_arg == Type::MutPtr(&U8) => (),
+             m => bail!(
+                 "mismatched argument \"{}\"= \"{:?}\" != \"{:?}\"",
+                 i,
+                 m,
+                 *rust_arg
+             ),
+         }
+ 
+         let is_const = match mips_arg {
+             MsaTy::imm0_1
+             | MsaTy::imm0_3
+             | MsaTy::imm0_7
+             | MsaTy::imm0_15
+             | MsaTy::imm0_31
+             | MsaTy::imm0_63
+             | MsaTy::imm0_255
+             | MsaTy::imm_n16_15
+             | MsaTy::imm_n512_511
+             | MsaTy::imm_n1024_1022
+             | MsaTy::imm_n2048_2044
+             | MsaTy::imm_n4096_4088 => true,
+             _ => false,
+         };
+         if is_const {
+             nconst += 1;
+             if !rust.required_const.contains(&i) {
+                 bail!("argument const mismatch");
+             }
+         }
+     }
+ 
+     if nconst != rust.required_const.len() {
+         bail!("wrong number of const arguments");
+     }
+ 
+     if rust.target_feature != Some("msa") {
+         bail!("wrong target_feature");
+     }
+ 
+     if !rust.instrs.is_empty() {
+         // Normalize slightly to get rid of assembler differences
+         let actual = rust.instrs[0].replace(".", "_");
+         let expected = mips.instruction.replace(".", "_");
+         if actual != expected {
+             bail!(
+                 "wrong instruction: \"{}\" != \"{}\"",
+                 rust.instrs[0],
+                 mips.instruction
+             );
+         }
+     } else {
+         bail!(
+             "missing assert_instr for \"{}\" (should be \"{}\")",
+             mips.id,
+             mips.instruction
+         );
+     }
+ 
+     Ok(())
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,718 ----
+ #![allow(bad_style)]
+ #![allow(unused)]
+ #![allow(
+     clippy::shadow_reuse,
+     clippy::cast_lossless,
+     clippy::match_same_arms,
+     clippy::nonminimal_bool,
+     clippy::print_stdout,
+     clippy::use_debug,
+     clippy::eq_op,
+     clippy::useless_format
+ )]
+ 
+ use std::collections::{BTreeMap, HashMap};
+ 
+ use serde::Deserialize;
+ 
+ const PRINT_INSTRUCTION_VIOLATIONS: bool = false;
+ const PRINT_MISSING_LISTS: bool = false;
+ const PRINT_MISSING_LISTS_MARKDOWN: bool = false;
+ 
+ struct Function {
+     name: &'static str,
+     arguments: &'static [&'static Type],
+     ret: Option<&'static Type>,
+     target_feature: Option<&'static str>,
+     instrs: &'static [&'static str],
+     file: &'static str,
+     required_const: &'static [usize],
+     has_test: bool,
+ }
+ 
+ static F32: Type = Type::PrimFloat(32);
+ static F64: Type = Type::PrimFloat(64);
+ static I16: Type = Type::PrimSigned(16);
+ static I32: Type = Type::PrimSigned(32);
+ static I64: Type = Type::PrimSigned(64);
+ static I8: Type = Type::PrimSigned(8);
+ static U16: Type = Type::PrimUnsigned(16);
+ static U32: Type = Type::PrimUnsigned(32);
+ static U64: Type = Type::PrimUnsigned(64);
+ static U128: Type = Type::PrimUnsigned(128);
+ static U8: Type = Type::PrimUnsigned(8);
+ static ORDERING: Type = Type::Ordering;
+ 
+ static M64: Type = Type::M64;
+ static M128: Type = Type::M128;
+ static M128I: Type = Type::M128I;
+ static M128D: Type = Type::M128D;
+ static M256: Type = Type::M256;
+ static M256I: Type = Type::M256I;
+ static M256D: Type = Type::M256D;
+ static M512: Type = Type::M512;
+ static M512I: Type = Type::M512I;
+ static M512D: Type = Type::M512D;
+ static MMASK8: Type = Type::MMASK8;
+ static MMASK16: Type = Type::MMASK16;
+ static MM_CMPINT_ENUM: Type = Type::MM_CMPINT_ENUM;
+ static MM_MANTISSA_NORM_ENUM: Type = Type::MM_MANTISSA_NORM_ENUM;
+ static MM_MANTISSA_SIGN_ENUM: Type = Type::MM_MANTISSA_SIGN_ENUM;
+ static MM_PERM_ENUM: Type = Type::MM_PERM_ENUM;
+ 
+ static TUPLE: Type = Type::Tuple;
+ static CPUID: Type = Type::CpuidResult;
+ static NEVER: Type = Type::Never;
+ 
+ #[derive(Debug)]
+ enum Type {
+     PrimFloat(u8),
+     PrimSigned(u8),
+     PrimUnsigned(u8),
+     MutPtr(&'static Type),
+     ConstPtr(&'static Type),
+     M64,
+     M128,
+     M128D,
+     M128I,
+     M256,
+     M256D,
+     M256I,
+     M512,
+     M512D,
+     M512I,
+     MMASK8,
+     MMASK16,
+     MM_CMPINT_ENUM,
+     MM_MANTISSA_NORM_ENUM,
+     MM_MANTISSA_SIGN_ENUM,
+     MM_PERM_ENUM,
+     Tuple,
+     CpuidResult,
+     Never,
+     Ordering,
+ }
+ 
+ stdarch_verify::x86_functions!(static FUNCTIONS);
+ 
+ #[derive(Deserialize)]
+ struct Data {
+     #[serde(rename = "intrinsic", default)]
+     intrinsics: Vec<Intrinsic>,
+ }
+ 
+ #[derive(Deserialize)]
+ struct Intrinsic {
+     #[serde(rename = "return")]
+     return_: Return,
+     name: String,
+     #[serde(rename = "CPUID", default)]
+     cpuid: Vec<String>,
+     #[serde(rename = "parameter", default)]
+     parameters: Vec<Parameter>,
+     #[serde(default)]
+     instruction: Vec<Instruction>,
+ }
+ 
+ #[derive(Deserialize)]
+ struct Parameter {
+     #[serde(rename = "type")]
+     type_: String,
+ }
+ 
+ #[derive(Deserialize)]
+ struct Return {
+     #[serde(rename = "type")]
+     type_: String,
+ }
+ 
+ #[derive(Deserialize, Debug)]
+ struct Instruction {
+     name: String,
+ }
+ 
+ macro_rules! bail {
+     ($($t:tt)*) => (return Err(format!($($t)*)))
+ }
+ 
+ #[test]
+ fn verify_all_signatures() {
+     // This XML document was downloaded from Intel's site. To update this you
+     // can visit intel's intrinsics guide online documentation:
+     //
+     //   https://software.intel.com/sites/landingpage/IntrinsicsGuide/#
+     //
+     // Open up the network console and you'll see an xml file was downloaded
+     // (currently called data-3.4.xml). That's the file we downloaded
+     // here.
+     let xml = include_bytes!("../x86-intel.xml");
+ 
+     let xml = &xml[..];
+     let data: Data = serde_xml_rs::from_reader(xml).expect("failed to deserialize xml");
+     let mut map = HashMap::new();
+     for intrinsic in &data.intrinsics {
+         map.entry(&intrinsic.name[..])
+             .or_insert_with(Vec::new)
+             .push(intrinsic);
+     }
+ 
+     let mut all_valid = true;
+     'outer: for rust in FUNCTIONS {
+         if !rust.has_test {
+             // FIXME: this list should be almost empty
+             let skip = [
+                 "__readeflags",
+                 "__readeflags",
+                 "__writeeflags",
+                 "__writeeflags",
+                 "_mm_comige_ss",
+                 "_mm_cvt_ss2si",
+                 "_mm_cvtt_ss2si",
+                 "_mm_cvt_si2ss",
+                 "_mm_set_ps1",
+                 "_mm_load_ps1",
+                 "_mm_store_ps1",
+                 "_mm_getcsr",
+                 "_mm_setcsr",
+                 "_MM_GET_EXCEPTION_MASK",
+                 "_MM_GET_EXCEPTION_STATE",
+                 "_MM_GET_FLUSH_ZERO_MODE",
+                 "_MM_GET_ROUNDING_MODE",
+                 "_MM_SET_EXCEPTION_MASK",
+                 "_MM_SET_EXCEPTION_STATE",
+                 "_MM_SET_FLUSH_ZERO_MODE",
+                 "_MM_SET_ROUNDING_MODE",
+                 "_mm_prefetch",
+                 "_mm_undefined_ps",
+                 "_m_pmaxsw",
+                 "_m_pmaxub",
+                 "_m_pminsw",
+                 "_m_pminub",
+                 "_m_pavgb",
+                 "_m_pavgw",
+                 "_m_psadbw",
+                 "_mm_cvt_pi2ps",
+                 "_m_maskmovq",
+                 "_m_pextrw",
+                 "_m_pinsrw",
+                 "_m_pmovmskb",
+                 "_m_pshufw",
+                 "_mm_cvtt_ps2pi",
+                 "_mm_cvt_ps2pi",
+                 "__cpuid_count",
+                 "__cpuid",
+                 "__get_cpuid_max",
+                 "_xsave",
+                 "_xrstor",
+                 "_xsetbv",
+                 "_xgetbv",
+                 "_xsaveopt",
+                 "_xsavec",
+                 "_xsaves",
+                 "_xrstors",
+                 "_mm_bslli_si128",
+                 "_mm_bsrli_si128",
+                 "_mm_undefined_pd",
+                 "_mm_undefined_si128",
+                 "_mm_cvtps_ph",
+                 "_mm256_cvtps_ph",
+                 "_rdtsc",
+                 "__rdtscp",
+                 "_mm256_castps128_ps256",
+                 "_mm256_castpd128_pd256",
+                 "_mm256_castsi128_si256",
+                 "_mm256_undefined_ps",
+                 "_mm256_undefined_pd",
+                 "_mm256_undefined_si256",
+                 "_bextr2_u32",
+                 "_mm_tzcnt_32",
+                 "_m_paddb",
+                 "_m_paddw",
+                 "_m_paddd",
+                 "_m_paddsb",
+                 "_m_paddsw",
+                 "_m_paddusb",
+                 "_m_paddusw",
+                 "_m_psubb",
+                 "_m_psubw",
+                 "_m_psubd",
+                 "_m_psubsb",
+                 "_m_psubsw",
+                 "_m_psubusb",
+                 "_m_psubusw",
+                 "_mm_set_pi16",
+                 "_mm_set_pi32",
+                 "_mm_set_pi8",
+                 "_mm_set1_pi16",
+                 "_mm_set1_pi32",
+                 "_mm_set1_pi8",
+                 "_mm_setr_pi16",
+                 "_mm_setr_pi32",
+                 "_mm_setr_pi8",
+                 "ud2",
+                 "_mm_min_epi8",
+                 "_mm_min_epi32",
+                 "_xbegin",
+                 "_xend",
+                 "_rdrand16_step",
+                 "_rdrand32_step",
+                 "_rdseed16_step",
+                 "_rdseed32_step",
+                 "_fxsave",
+                 "_fxrstor",
+                 "_t1mskc_u64",
+                 "_mm256_shuffle_epi32",
+                 "_mm256_bslli_epi128",
+                 "_mm256_bsrli_epi128",
+                 "_mm256_unpackhi_epi8",
+                 "_mm256_unpacklo_epi8",
+                 "_mm256_unpackhi_epi16",
+                 "_mm256_unpacklo_epi16",
+                 "_mm256_unpackhi_epi32",
+                 "_mm256_unpacklo_epi32",
+                 "_mm256_unpackhi_epi64",
+                 "_mm256_unpacklo_epi64",
+                 "_xsave64",
+                 "_xrstor64",
+                 "_xsaveopt64",
+                 "_xsavec64",
+                 "_xsaves64",
+                 "_xrstors64",
+                 "_mm_cvtsi64x_si128",
+                 "_mm_cvtsi128_si64x",
+                 "_mm_cvtsi64x_sd",
+                 "cmpxchg16b",
+                 "_rdrand64_step",
+                 "_rdseed64_step",
+                 "_bextr2_u64",
+                 "_mm_tzcnt_64",
+                 "_fxsave64",
+                 "_fxrstor64",
+                 "_mm512_undefined_ps",
+                 "_mm512_undefined_pd",
+             ];
+             if !skip.contains(&rust.name) {
+                 println!(
+                     "missing run-time test named `test_{}` for `{}`",
+                     {
+                         let mut id = rust.name;
+                         while id.starts_with('_') {
+                             id = &id[1..];
+                         }
+                         id
+                     },
+                     rust.name
+                 );
+                 all_valid = false;
+             }
+         }
+ 
+         match rust.name {
+             // These aren't defined by Intel but they're defined by what appears
+             // to be all other compilers. For more information see
+             // rust-lang/stdarch#307, and otherwise these signatures
+             // have all been manually verified.
+             "__readeflags" |
+             "__writeeflags" |
+             "__cpuid_count" |
+             "__cpuid" |
+             "__get_cpuid_max" |
+             // Not listed with intel, but manually verified
+             "cmpxchg16b" |
+             // The UD2 intrinsic is not defined by Intel, but it was agreed on
+             // in the RFC Issue 2512:
+             // https://github.com/rust-lang/rfcs/issues/2512
+             "ud2"
+                 => continue,
+             // Intel requires the mask argument for _mm_shuffle_ps to be an
+             // unsigned integer, but all other _mm_shuffle_.. intrinsics
+             // take a signed-integer. This breaks `_MM_SHUFFLE` for
+             // `_mm_shuffle_ps`:
+             "_mm_shuffle_ps" => continue,
+             _ => {}
+         }
+ 
+         // these are all AMD-specific intrinsics
+         if let Some(feature) = rust.target_feature {
+             if feature.contains("sse4a") || feature.contains("tbm") {
+                 continue;
+             }
+         }
+ 
+         let intel = match map.remove(rust.name) {
+             Some(i) => i,
+             None => panic!("missing intel definition for {}", rust.name),
+         };
+ 
+         let mut errors = Vec::new();
+         for intel in intel {
+             match matches(rust, intel) {
+                 Ok(()) => continue 'outer,
+                 Err(e) => errors.push(e),
+             }
+         }
+         println!("failed to verify `{}`", rust.name);
+         for error in errors {
+             println!("  * {}", error);
+         }
+         all_valid = false;
+     }
+     assert!(all_valid);
+ 
+     let mut missing = BTreeMap::new();
+     for (name, intel) in &map {
+         // currently focused mainly on missing SIMD intrinsics, but there's
+         // definitely some other assorted ones that we're missing.
+         if !name.starts_with("_mm") {
+             continue;
+         }
+ 
+         // we'll get to avx-512 later
+         // let avx512 = intel.iter().any(|i| {
+         //     i.name.starts_with("_mm512") || i.cpuid.iter().any(|c| {
+         //         c.contains("512")
+         //     })
+         // });
+         // if avx512 {
+         //     continue
+         // }
+ 
+         for intel in intel {
+             missing
+                 .entry(&intel.cpuid)
+                 .or_insert_with(Vec::new)
+                 .push(intel);
+         }
+     }
+ 
+     // generate a bulleted list of missing intrinsics
+     if PRINT_MISSING_LISTS || PRINT_MISSING_LISTS_MARKDOWN {
+         for (k, v) in missing {
+             if PRINT_MISSING_LISTS_MARKDOWN {
+                 println!("\n<details><summary>{:?}</summary><p>\n", k);
+                 for intel in v {
+                     let url = format!(
+                         "https://software.intel.com/sites/landingpage\
+                          /IntrinsicsGuide/#text={}&expand=5236",
+                         intel.name
+                     );
+                     println!("  * [ ] [`{}`]({})", intel.name, url);
+                 }
+                 println!("</p></details>\n");
+             } else {
+                 println!("\n{:?}\n", k);
+                 for intel in v {
+                     println!("\t{}", intel.name);
+                 }
+             }
+         }
+     }
+ }
+ 
+ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
+     // Verify that all `#[target_feature]` annotations are correct,
+     // ensuring that we've actually enabled the right instruction
+     // set for this intrinsic.
+     match rust.name {
+         "_bswap" | "_bswap64" => {}
+ 
+         // These don't actually have a target feature unlike their brethren with
+         // the `x` inside the name which requires adx
+         "_addcarry_u32" | "_addcarry_u64" | "_subborrow_u32" | "_subborrow_u64" => {}
+ 
+         "_bittest"
+         | "_bittestandset"
+         | "_bittestandreset"
+         | "_bittestandcomplement"
+         | "_bittest64"
+         | "_bittestandset64"
+         | "_bittestandreset64"
+         | "_bittestandcomplement64" => {}
+ 
+         _ => {
+             if intel.cpuid.is_empty() {
+                 bail!("missing cpuid for {}", rust.name);
+             }
+         }
+     }
+ 
+     for cpuid in &intel.cpuid {
+         // The pause intrinsic is in the SSE2 module, but it is backwards
+         // compatible with CPUs without SSE2, and it therefore does not need the
+         // target-feature attribute.
+         if rust.name == "_mm_pause" {
+             continue;
+         }
+         // this is needed by _xsave and probably some related intrinsics,
+         // but let's just skip it for now.
+         if *cpuid == "XSS" {
+             continue;
+         }
+ 
+         // these flags on the rdtsc/rtdscp intrinsics we don't test for right
+         // now, but we may wish to add these one day!
+         //
+         // For more info see #308
+         if *cpuid == "TSC" || *cpuid == "RDTSCP" {
+             continue;
+         }
+ 
+         let cpuid = cpuid
+             .chars()
+             .flat_map(|c| c.to_lowercase())
+             .collect::<String>();
+ 
+         // Fix mismatching feature names:
+         let fixup_cpuid = |cpuid: String| match cpuid.as_ref() {
+             // The XML file names IFMA as "avx512ifma52", while Rust calls
+             // it "avx512ifma".
+             "avx512ifma52" => String::from("avx512ifma"),
+             // Some AVX512f intrinsics are also supported by Knight's Corner.
+             // The XML lists them as avx512f/kncni, but we are solely gating
+             // them behind avx512f since we don't have a KNC feature yet.
+             "avx512f/kncni" => String::from("avx512f"),
+             // See: https://github.com/rust-lang/stdarch/issues/738
+             // The intrinsics guide calls `f16c` `fp16c` in disagreement with
+             // Intel's architecture manuals.
+             "fp16c" => String::from("f16c"),
+             _ => cpuid,
+         };
+         let fixed_cpuid = fixup_cpuid(cpuid);
+ 
+         let rust_feature = rust
+             .target_feature
+             .expect(&format!("no target feature listed for {}", rust.name));
+ 
+         if rust_feature.contains(&fixed_cpuid) {
+             continue;
+         }
+         bail!(
+             "intel cpuid `{}` not in `{}` for {}",
+             fixed_cpuid,
+             rust_feature,
+             rust.name
+         )
+     }
+ 
+     if PRINT_INSTRUCTION_VIOLATIONS {
+         if rust.instrs.is_empty() {
+             if !intel.instruction.is_empty() {
+                 println!(
+                     "instruction not listed for `{}`, but intel lists {:?}",
+                     rust.name, intel.instruction
+                 );
+             }
+ 
+         // If intel doesn't list any instructions and we do then don't
+         // bother trying to look for instructions in intel, we've just got
+         // some extra assertions on our end.
+         } else if !intel.instruction.is_empty() {
+             for instr in rust.instrs {
+                 let asserting = intel.instruction.iter().any(|a| a.name.starts_with(instr));
+                 if !asserting {
+                     println!(
+                         "intel failed to list `{}` as an instruction for `{}`",
+                         instr, rust.name
+                     );
+                 }
+             }
+         }
+     }
+ 
+     // Make sure we've got the right return type.
+     if let Some(t) = rust.ret {
+         equate(t, &intel.return_.type_, rust.name, false)?;
+     } else if intel.return_.type_ != "" && intel.return_.type_ != "void" {
+         bail!(
+             "{} returns `{}` with intel, void in rust",
+             rust.name,
+             intel.return_.type_
+         )
+     }
+ 
+     // If there's no arguments on Rust's side intel may list one "void"
+     // argument, so handle that here.
+     if rust.arguments.is_empty() && intel.parameters.len() == 1 {
+         if intel.parameters[0].type_ != "void" {
+             bail!("rust has 0 arguments, intel has one for")
+         }
+     } else {
+         // Otherwise we want all parameters to be exactly the same
+         if rust.arguments.len() != intel.parameters.len() {
+             bail!("wrong number of arguments on {}", rust.name)
+         }
+         for (i, (a, b)) in intel.parameters.iter().zip(rust.arguments).enumerate() {
+             let is_const = rust.required_const.contains(&i);
+             equate(b, &a.type_, &intel.name, is_const)?;
+         }
+     }
+ 
+     let any_i64 = rust
+         .arguments
+         .iter()
+         .cloned()
+         .chain(rust.ret)
+         .any(|arg| match *arg {
+             Type::PrimSigned(64) | Type::PrimUnsigned(64) => true,
+             _ => false,
+         });
+     let any_i64_exempt = match rust.name {
+         // These intrinsics have all been manually verified against Clang's
+         // headers to be available on x86, and the u64 arguments seem
+         // spurious I guess?
+         "_xsave" | "_xrstor" | "_xsetbv" | "_xgetbv" | "_xsaveopt" | "_xsavec" | "_xsaves"
+         | "_xrstors" => true,
+ 
+         // Apparently all of clang/msvc/gcc accept these intrinsics on
+         // 32-bit, so let's do the same
+         "_mm_set_epi64x" | "_mm_set1_epi64x" | "_mm256_set_epi64x" | "_mm256_setr_epi64x"
+         | "_mm256_set1_epi64x" | "_mm512_set1_epi64" => true,
+ 
+         // These return a 64-bit argument but they're assembled from other
+         // 32-bit registers, so these work on 32-bit just fine. See #308 for
+         // more info.
+         "_rdtsc" | "__rdtscp" => true,
+ 
+         _ => false,
+     };
+     if any_i64 && !any_i64_exempt && !rust.file.contains("x86_64") {
+         bail!(
+             "intrinsic `{}` uses a 64-bit bare type but may be \
+              available on 32-bit platforms",
+             rust.name
+         )
+     }
+     Ok(())
+ }
+ 
+ fn equate(t: &Type, intel: &str, intrinsic: &str, is_const: bool) -> Result<(), String> {
+     // Make pointer adjacent to the type: float * foo => float* foo
+     let mut intel = intel.replace(" *", "*");
+     // Make mutability modifier adjacent to the pointer:
+     // float const * foo => float const* foo
+     intel = intel.replace("const *", "const*");
+     // Normalize mutability modifier to after the type:
+     // const float* foo => float const*
+     if intel.starts_with("const") && intel.ends_with("*") {
+         intel = intel.replace("const ", "");
+         intel = intel.replace("*", " const*");
+     }
+     let require_const = || {
+         if is_const {
+             return Ok(());
+         }
+         Err(format!("argument required to be const but isn't"))
+     };
+     match (t, &intel[..]) {
+         (&Type::PrimFloat(32), "float") => {}
+         (&Type::PrimFloat(64), "double") => {}
+         (&Type::PrimSigned(16), "__int16") => {}
+         (&Type::PrimSigned(16), "short") => {}
+         (&Type::PrimSigned(32), "__int32") => {}
+         (&Type::PrimSigned(32), "const int") => require_const()?,
+         (&Type::PrimSigned(32), "int") => {}
+         (&Type::PrimSigned(64), "__int64") => {}
+         (&Type::PrimSigned(64), "long long") => {}
+         (&Type::PrimSigned(8), "__int8") => {}
+         (&Type::PrimSigned(8), "char") => {}
+         (&Type::PrimUnsigned(16), "unsigned short") => {}
+         (&Type::PrimUnsigned(32), "unsigned int") => {}
+         (&Type::PrimUnsigned(32), "const unsigned int") => {}
+         (&Type::PrimUnsigned(64), "unsigned __int64") => {}
+         (&Type::PrimUnsigned(8), "unsigned char") => {}
+         (&Type::M64, "__m64") => {}
+         (&Type::M128, "__m128") => {}
+         (&Type::M128I, "__m128i") => {}
+         (&Type::M128D, "__m128d") => {}
+         (&Type::M256, "__m256") => {}
+         (&Type::M256I, "__m256i") => {}
+         (&Type::M256D, "__m256d") => {}
+         (&Type::M512, "__m512") => {}
+         (&Type::M512I, "__m512i") => {}
+         (&Type::M512D, "__m512d") => {}
+ 
+         (&Type::MutPtr(&Type::PrimFloat(32)), "float*") => {}
+         (&Type::MutPtr(&Type::PrimFloat(64)), "double*") => {}
+         (&Type::MutPtr(&Type::PrimFloat(32)), "void*") => {}
+         (&Type::MutPtr(&Type::PrimFloat(64)), "void*") => {}
+         (&Type::MutPtr(&Type::PrimSigned(32)), "int*") => {}
+         (&Type::MutPtr(&Type::PrimSigned(32)), "__int32*") => {}
+         (&Type::MutPtr(&Type::PrimSigned(64)), "__int64*") => {}
+         (&Type::MutPtr(&Type::PrimSigned(8)), "char*") => {}
+         (&Type::MutPtr(&Type::PrimUnsigned(16)), "unsigned short*") => {}
+         (&Type::MutPtr(&Type::PrimUnsigned(32)), "unsigned int*") => {}
+         (&Type::MutPtr(&Type::PrimUnsigned(64)), "unsigned __int64*") => {}
+         (&Type::MutPtr(&Type::PrimUnsigned(8)), "void*") => {}
+         (&Type::MutPtr(&Type::M64), "__m64*") => {}
+         (&Type::MutPtr(&Type::M128), "__m128*") => {}
+         (&Type::MutPtr(&Type::M128I), "__m128i*") => {}
+         (&Type::MutPtr(&Type::M128D), "__m128d*") => {}
+         (&Type::MutPtr(&Type::M256), "__m256*") => {}
+         (&Type::MutPtr(&Type::M256I), "__m256i*") => {}
+         (&Type::MutPtr(&Type::M256D), "__m256d*") => {}
+         (&Type::MutPtr(&Type::M512), "__m512*") => {}
+         (&Type::MutPtr(&Type::M512I), "__m512i*") => {}
+         (&Type::MutPtr(&Type::M512D), "__m512d*") => {}
+ 
+         (&Type::ConstPtr(&Type::PrimFloat(32)), "float const*") => {}
+         (&Type::ConstPtr(&Type::PrimFloat(64)), "double const*") => {}
+         (&Type::ConstPtr(&Type::PrimFloat(32)), "void const*") => {}
+         (&Type::ConstPtr(&Type::PrimFloat(64)), "void const*") => {}
+         (&Type::ConstPtr(&Type::PrimSigned(32)), "int const*") => {}
+         (&Type::ConstPtr(&Type::PrimSigned(32)), "__int32 const*") => {}
+         (&Type::ConstPtr(&Type::PrimSigned(64)), "__int64 const*") => {}
+         (&Type::ConstPtr(&Type::PrimSigned(8)), "char const*") => {}
+         (&Type::ConstPtr(&Type::PrimUnsigned(16)), "unsigned short const*") => {}
+         (&Type::ConstPtr(&Type::PrimUnsigned(32)), "unsigned int const*") => {}
+         (&Type::ConstPtr(&Type::PrimUnsigned(64)), "unsigned __int64 const*") => {}
+         (&Type::ConstPtr(&Type::PrimUnsigned(8)), "void const*") => {}
+         (&Type::ConstPtr(&Type::M64), "__m64 const*") => {}
+         (&Type::ConstPtr(&Type::M128), "__m128 const*") => {}
+         (&Type::ConstPtr(&Type::M128I), "__m128i const*") => {}
+         (&Type::ConstPtr(&Type::M128D), "__m128d const*") => {}
+         (&Type::ConstPtr(&Type::M256), "__m256 const*") => {}
+         (&Type::ConstPtr(&Type::M256I), "__m256i const*") => {}
+         (&Type::ConstPtr(&Type::M256D), "__m256d const*") => {}
+         (&Type::ConstPtr(&Type::M512), "__m512 const*") => {}
+         (&Type::ConstPtr(&Type::M512I), "__m512i const*") => {}
+         (&Type::ConstPtr(&Type::M512D), "__m512d const*") => {}
+ 
+         (&Type::MMASK8, "__mmask8") => {}
+         (&Type::MMASK16, "__mmask16") => {}
+         (&Type::MM_CMPINT_ENUM, "_MM_CMPINT_ENUM") => {}
+         (&Type::MM_MANTISSA_NORM_ENUM, "_MM_MANTISSA_NORM_ENUM") => {}
+         (&Type::MM_MANTISSA_SIGN_ENUM, "_MM_MANTISSA_SIGN_ENUM") => {}
+         (&Type::MM_PERM_ENUM, "_MM_PERM_ENUM") => {}
+ 
+         // This is a macro (?) in C which seems to mutate its arguments, but
+         // that means that we're taking pointers to arguments in rust
+         // as we're not exposing it as a macro.
+         (&Type::MutPtr(&Type::M128), "__m128") if intrinsic == "_MM_TRANSPOSE4_PS" => {}
+ 
+         // The _rdtsc intrinsic uses a __int64 return type, but this is a bug in
+         // the intrinsics guide: https://github.com/rust-lang/stdarch/issues/559
+         // We have manually fixed the bug by changing the return type to `u64`.
+         (&Type::PrimUnsigned(64), "__int64") if intrinsic == "_rdtsc" => {}
+ 
+         // The _bittest and _bittest64 intrinsics takes a mutable pointer in the
+         // intrinsics guide even though it never writes through the pointer:
+         (&Type::ConstPtr(&Type::PrimSigned(32)), "__int32*") if intrinsic == "_bittest" => {}
+         (&Type::ConstPtr(&Type::PrimSigned(64)), "__int64*") if intrinsic == "_bittest64" => {}
+         // The _xrstor, _fxrstor, _xrstor64, _fxrstor64 intrinsics take a
+         // mutable pointer in the intrinsics guide even though they never write
+         // through the pointer:
+         (&Type::ConstPtr(&Type::PrimUnsigned(8)), "void*")
+             if intrinsic == "_xrstor"
+                 || intrinsic == "_xrstor64"
+                 || intrinsic == "_fxrstor"
+                 || intrinsic == "_fxrstor64" => {}
+ 
+         _ => bail!(
+             "failed to equate: `{}` and {:?} for {}",
+             intel,
+             t,
+             intrinsic
+         ),
+     }
+     Ok(())
+ }
diff -Nrcpad gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml
*** gcc-16-20251026/libgrust/rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml	Thu Jan  1 00:00:00 1970
--- gcc-16-20251102/libgrust/rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml	Sun Nov  2 22:34:21 2025
***************
*** 0 ****
--- 1,147835 ----
+ <intrinsics_list version="3.5.2" date="06/05/2020">
+ <intrinsic tech="Other" name="_addcarryx_u32">
+ 	<type>Integer</type>
+ 	<type>Flag</type>
+ 	<CPUID>ADX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="unsigned char" varname="c_in" etype="UI8"/>
+ 	<parameter type="unsigned int" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="b" etype="UI32"/>
+ 	<parameter type="unsigned int *" varname="out" etype="UI32" memwidth="32"/>
+ 	<description>Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+ 	<operation>
+ tmp[32:0] := a[31:0] + b[31:0] + (c_in &gt; 0 ? 1 : 0)
+ MEM[out+31:out] := tmp[31:0]
+ dst[0] := tmp[32]
+ dst[7:1] := 0
+ 	</operation>
+ 	<instruction name="ADCX" form="r32, r32" xed="ADCX_GPR32d_GPR32d"/>
+ 	<instruction name="ADOX" form="r32, r32" xed="ADOX_GPR32d_GPR32d"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" name="_addcarryx_u64">
+ 	<type>Integer</type>
+ 	<type>Flag</type>
+ 	<CPUID>ADX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="unsigned char" varname="c_in" etype="UI8"/>
+ 	<parameter type="unsigned __int64" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned __int64" varname="b" etype="UI64"/>
+ 	<parameter type="unsigned __int64 *" varname="out" etype="UI64" memwidth="64"/>
+ 	<description>Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+ 	<operation>
+ tmp[64:0] := a[63:0] + b[63:0] + (c_in &gt; 0 ? 1 : 0)
+ MEM[out+63:out] := tmp[63:0]
+ dst[0] := tmp[64]
+ dst[7:1] := 0
+ 	</operation>
+ 	<instruction name="ADCX" form="r64, r64" xed="ADCX_GPR64q_GPR64q"/>
+ 	<instruction name="ADOX" form="r64, r64" xed="ADOX_GPR64q_GPR64q"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" vexEq="TRUE" name="_mm_aesenc_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<parameter type="__m128i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."</description>
+ 	<operation>a[127:0] := ShiftRows(a[127:0])
+ a[127:0] := SubBytes(a[127:0])
+ a[127:0] := MixColumns(a[127:0])
+ dst[127:0] := a[127:0] XOR RoundKey[127:0]
+ 	</operation>
+ 	<instruction name="AESENC" form="xmm, xmm" xed="AESENC_XMMdq_XMMdq"/>
+ 	<header>wmmintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" vexEq="TRUE" name="_mm_aesenclast_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<parameter type="__m128i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."</description>
+ 	<operation>a[127:0] := ShiftRows(a[127:0])
+ a[127:0] := SubBytes(a[127:0])
+ dst[127:0] := a[127:0] XOR RoundKey[127:0]
+ 	</operation>
+ 	<instruction name="AESENCLAST" form="xmm, xmm" xed="AESENCLAST_XMMdq_XMMdq"/>
+ 	<header>wmmintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" vexEq="TRUE" name="_mm_aesdec_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<parameter type="__m128i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".</description>
+ 	<operation>a[127:0] := InvShiftRows(a[127:0])
+ a[127:0] := InvSubBytes(a[127:0])
+ a[127:0] := InvMixColumns(a[127:0])
+ dst[127:0] := a[127:0] XOR RoundKey[127:0]
+ 	</operation>
+ 	<instruction name="AESDEC" form="xmm, xmm" xed="AESDEC_XMMdq_XMMdq"/>
+ 	<header>wmmintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" vexEq="TRUE" name="_mm_aesdeclast_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<parameter type="__m128i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".</description>
+ 	<operation>a[127:0] := InvShiftRows(a[127:0])
+ a[127:0] := InvSubBytes(a[127:0])
+ dst[127:0] := a[127:0] XOR RoundKey[127:0]
+ 	</operation>
+ 	<instruction name="AESDECLAST" form="xmm, xmm" xed="AESDECLAST_XMMdq_XMMdq"/>
+ 	<header>wmmintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" vexEq="TRUE" name="_mm_aesimc_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<description>Perform the InvMixColumns transformation on "a" and store the result in "dst".</description>
+ 	<operation>dst[127:0] := InvMixColumns(a[127:0])
+ 	</operation>
+ 	<instruction name="AESIMC" form="xmm, xmm" xed="AESIMC_XMMdq_XMMdq"/>
+ 	<header>wmmintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" vexEq="TRUE" name="_mm_aeskeygenassist_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8", and store the result in "dst"."</description>
+ 	<operation>X3[31:0] := a[127:96]
+ X2[31:0] := a[95:64]
+ X1[31:0] := a[63:32]
+ X0[31:0] := a[31:0]
+ RCON[31:0] := ZeroExtend32(imm8[7:0])
+ dst[31:0] := SubWord(X1)
+ dst[63:32] := RotWord(SubWord(X1)) XOR RCON
+ dst[95:64] := SubWord(X3)
+ dst[127:96] := RotWord(SubWord(X3)) XOR RCON
+ 	</operation>
+ 	<instruction name="AESKEYGENASSIST" form="xmm, xmm, imm8" xed="AESKEYGENASSIST_XMMdq_XMMdq_IMMb"/>
+ 	<header>wmmintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_add_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDPD" form="ymm, ymm, ymm" xed="VADDPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_add_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDPS" form="ymm, ymm, ymm" xed="VADDPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_addsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF ((j &amp; 1) == 0)
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDSUBPD" form="ymm, ymm, ymm" xed="VADDSUBPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_addsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF ((j &amp; 1) == 0)
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDSUBPS" form="ymm, ymm, ymm" xed="VADDSUBPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="ymm, ymm, ymm" xed="VANDPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="ymm, ymm, ymm" xed="VANDPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="ymm, ymm, ymm" xed="VANDNPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="ymm, ymm, ymm" xed="VANDNPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_blend_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF imm8[j]
+ 		dst[i+63:i] := b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBLENDPD" form="ymm, ymm, ymm, imm8" xed="VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_blend_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF imm8[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBLENDPS" form="ymm, ymm, ymm, imm8" xed="VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_blendv_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="mask" etype="MASK"/>
+ 	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF mask[i+63]
+ 		dst[i+63:i] := b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBLENDVPD" form="ymm, ymm, ymm, ymm" xed="VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_blendv_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="mask" etype="MASK"/>
+ 	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF mask[i+31]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBLENDVPS" form="ymm, ymm, ymm, ymm" xed="VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_div_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDIVPD" form="ymm, ymm, ymm" xed="VDIVPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_div_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDIVPS" form="ymm, ymm, ymm" xed="VDIVPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_dp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
+ 	<operation>
+ DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
+ 	FOR j := 0 to 3
+ 		i := j*32
+ 		IF imm8[(4+j)%8]
+ 			temp[i+31:i] := a[i+31:i] * b[i+31:i]
+ 		ELSE
+ 			temp[i+31:i] := FP32(0.0)
+ 		FI
+ 	ENDFOR
+ 	
+ 	sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])
+ 	
+ 	FOR j := 0 to 3
+ 		i := j*32
+ 		IF imm8[j%8]
+ 			tmpdst[i+31:i] := sum[31:0]
+ 		ELSE
+ 			tmpdst[i+31:i] := FP32(0.0)
+ 		FI
+ 	ENDFOR
+ 	RETURN tmpdst[127:0]
+ }
+ dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
+ dst[255:128] := DP(a[255:128], b[255:128], imm8[7:0])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDPPS" form="ymm, ymm, ymm, imm8" xed="VDPPS_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_hadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+ 	<operation>
+ dst[63:0] := a[127:64] + a[63:0]
+ dst[127:64] := b[127:64] + b[63:0]
+ dst[191:128] := a[255:192] + a[191:128]
+ dst[255:192] := b[255:192] + b[191:128]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VHADDPD" form="ymm, ymm, ymm" xed="VHADDPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_hadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+ 	<operation>
+ dst[31:0] := a[63:32] + a[31:0]
+ dst[63:32] := a[127:96] + a[95:64]
+ dst[95:64] := b[63:32] + b[31:0]
+ dst[127:96] := b[127:96] + b[95:64]
+ dst[159:128] := a[191:160] + a[159:128]
+ dst[191:160] := a[255:224] + a[223:192]
+ dst[223:192] := b[191:160] + b[159:128]
+ dst[255:224] := b[255:224] + b[223:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VHADDPS" form="ymm, ymm, ymm" xed="VHADDPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_hsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+ 	<operation>
+ dst[63:0] := a[63:0] - a[127:64]
+ dst[127:64] := b[63:0] - b[127:64]
+ dst[191:128] := a[191:128] - a[255:192]
+ dst[255:192] := b[191:128] - b[255:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VHSUBPD" form="ymm, ymm, ymm" xed="VHSUBPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_hsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+ 	<operation>
+ dst[31:0] := a[31:0] - a[63:32]
+ dst[63:32] := a[95:64] - a[127:96]
+ dst[95:64] := b[31:0] - b[63:32]
+ dst[127:96] := b[95:64] - b[127:96]
+ dst[159:128] := a[159:128] - a[191:160]
+ dst[191:160] := a[223:192] - a[255:224]
+ dst[223:192] := b[159:128] - b[191:160]
+ dst[255:224] := b[223:192] - b[255:224]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VHSUBPS" form="ymm, ymm, ymm" xed="VHSUBPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_max_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMAXPD" form="ymm, ymm, ymm" xed="VMAXPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_max_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMAXPS" form="ymm, ymm, ymm" xed="VMAXPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_min_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMINPD" form="ymm, ymm, ymm" xed="VMINPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_min_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMINPS" form="ymm, ymm, ymm" xed="VMINPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_mul_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMULPD" form="ymm, ymm, ymm" xed="VMULPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_mul_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMULPS" form="ymm, ymm, ymm" xed="VMULPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="ymm, ymm, ymm" xed="VORPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="ymm, ymm, ymm" xed="VORPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_shuffle_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+ dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+ dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+ dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPD" form="ymm, ymm, ymm, imm8" xed="VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_shuffle_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+ dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+ dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+ dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPS" form="ymm, ymm, ymm, imm8" xed="VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_sub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSUBPD" form="ymm, ymm, ymm" xed="VSUBPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_sub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSUBPS" form="ymm, ymm, ymm" xed="VSUBPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="ymm, ymm, ymm" xed="VXORPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="ymm, ymm, ymm" xed="VXORPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_cmp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCMPPD" form="xmm, xmm, xmm, imm8" xed="VCMPPD_XMMdq_XMMdq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cmp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCMPPD" form="ymm, ymm, ymm, imm8" xed="VCMPPD_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_cmp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCMPPS" form="xmm, xmm, xmm, imm8" xed="VCMPPS_XMMdq_XMMdq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cmp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCMPPS" form="ymm, ymm, ymm, imm8" xed="VCMPPS_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_cmp_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ dst[63:0] := ( a[63:0] OP b[63:0] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCMPSD" form="xmm, xmm, xmm, imm8" xed="VCMPSD_XMMdq_XMMdq_XMMq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_cmp_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ dst[31:0] := ( a[31:0] OP b[31:0] ) ? 0xFFFFFFFF : 0
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCMPSS" form="xmm, xmm, xmm, imm8" xed="VCMPSS_XMMdq_XMMdq_XMMd_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvtepi32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PD" form="ymm, xmm" xed="VCVTDQ2PD_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvtepi32_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PS" form="ymm, ymm" xed="VCVTDQ2PS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvtpd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2PS" form="xmm, ymm" xed="VCVTPD2PS_XMMdq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvtps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2DQ" form="ymm, ymm" xed="VCVTPS2DQ_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvtps_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PD" form="ymm, xmm" xed="VCVTPS2PD_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvttpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2DQ" form="xmm, ymm" xed="VCVTTPD2DQ_XMMdq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvtpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2DQ" form="xmm, ymm" xed="VCVTPD2DQ_XMMdq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_cvttps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2DQ" form="ymm, ymm" xed="VCVTTPS2DQ_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_extractf128_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF128" form="xmm, ymm, imm8" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_extractf128_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF128" form="xmm, ymm, imm8" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_extractf128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF128" form="xmm, ymm, imm8" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_extract_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__int32" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="3"/>
+ 	<description>Extract a 32-bit integer from "a", selected with "index", and store the result in "dst".</description>
+ 	<operation>
+ dst[31:0] := (a[255:0] &gt;&gt; (index[2:0] * 32))[31:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_extract_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__int64" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="2"/>
+ 	<description>Extract a 64-bit integer from "a", selected with "index", and store the result in "dst".</description>
+ 	<operation>
+ dst[63:0] := (a[255:0] &gt;&gt; (index[1:0] * 64))[63:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_zeroall">
+ 	<CPUID>AVX</CPUID>
+ 	<category>General Support</category>
+ 	<return type="void"/>
+ 	<parameter type="void"/>
+ 	<description>Zero the contents of all XMM or YMM registers.</description>
+ 	<operation>YMM0[MAX:0] := 0
+ YMM1[MAX:0] := 0
+ YMM2[MAX:0] := 0
+ YMM3[MAX:0] := 0
+ YMM4[MAX:0] := 0
+ YMM5[MAX:0] := 0
+ YMM6[MAX:0] := 0
+ YMM7[MAX:0] := 0
+ IF _64_BIT_MODE
+ 	YMM8[MAX:0] := 0
+ 	YMM9[MAX:0] := 0
+ 	YMM10[MAX:0] := 0
+ 	YMM11[MAX:0] := 0
+ 	YMM12[MAX:0] := 0
+ 	YMM13[MAX:0] := 0
+ 	YMM14[MAX:0] := 0
+ 	YMM15[MAX:0] := 0
+ FI
+ 	</operation>
+ 	<instruction name="VZEROALL" xed="VZEROALL"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_zeroupper">
+ 	<CPUID>AVX</CPUID>
+ 	<category>General Support</category>
+ 	<return type="void"/>
+ 	<parameter type="void"/>
+ 	<description>Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified.</description>
+ 	<operation>YMM0[MAX:128] := 0
+ YMM1[MAX:128] := 0
+ YMM2[MAX:128] := 0
+ YMM3[MAX:128] := 0
+ YMM4[MAX:128] := 0
+ YMM5[MAX:128] := 0
+ YMM6[MAX:128] := 0
+ YMM7[MAX:128] := 0
+ IF _64_BIT_MODE
+ 	YMM8[MAX:128] := 0
+ 	YMM9[MAX:128] := 0
+ 	YMM10[MAX:128] := 0
+ 	YMM11[MAX:128] := 0
+ 	YMM12[MAX:128] := 0
+ 	YMM13[MAX:128] := 0
+ 	YMM14[MAX:128] := 0
+ 	YMM15[MAX:128] := 0
+ FI
+ 	</operation>
+ 	<instruction name="VZEROUPPER" xed="VZEROUPPER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permutevar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := SELECT4(a[127:0], b[1:0])
+ dst[63:32] := SELECT4(a[127:0], b[33:32])
+ dst[95:64] := SELECT4(a[127:0], b[65:64])
+ dst[127:96] := SELECT4(a[127:0], b[97:96])
+ dst[159:128] := SELECT4(a[255:128], b[129:128])
+ dst[191:160] := SELECT4(a[255:128], b[161:160])
+ dst[223:192] := SELECT4(a[255:128], b[193:192])
+ dst[255:224] := SELECT4(a[255:128], b[225:224])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="ymm, ymm, ymm" xed="VPERMILPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_permutevar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := SELECT4(a[127:0], b[1:0])
+ dst[63:32] := SELECT4(a[127:0], b[33:32])
+ dst[95:64] := SELECT4(a[127:0], b[65:64])
+ dst[127:96] := SELECT4(a[127:0], b[97:96])
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="xmm, xmm, xmm" xed="VPERMILPS_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permute_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+ dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="ymm, ymm, imm8" xed="VPERMILPS_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_permute_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="xmm, xmm, imm8" xed="VPERMILPS_XMMdq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permutevar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
+ 	<operation>
+ IF (b[1] == 0) dst[63:0] := a[63:0]; FI
+ IF (b[1] == 1) dst[63:0] := a[127:64]; FI
+ IF (b[65] == 0) dst[127:64] := a[63:0]; FI
+ IF (b[65] == 1) dst[127:64] := a[127:64]; FI
+ IF (b[129] == 0) dst[191:128] := a[191:128]; FI
+ IF (b[129] == 1) dst[191:128] := a[255:192]; FI
+ IF (b[193] == 0) dst[255:192] := a[191:128]; FI
+ IF (b[193] == 1) dst[255:192] := a[255:192]; FI
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="ymm, ymm, ymm" xed="VPERMILPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_permutevar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".</description>
+ 	<operation>
+ IF (b[1] == 0) dst[63:0] := a[63:0]; FI
+ IF (b[1] == 1) dst[63:0] := a[127:64]; FI
+ IF (b[65] == 0) dst[127:64] := a[63:0]; FI
+ IF (b[65] == 1) dst[127:64] := a[127:64]; FI
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="xmm, xmm, xmm" xed="VPERMILPD_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permute_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
+ IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
+ IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
+ IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
+ IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI
+ IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI
+ IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI
+ IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="ymm, ymm, imm8" xed="VPERMILPD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_permute_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
+ IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
+ IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
+ IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="xmm, xmm, imm8" xed="VPERMILPD_XMMdq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permute2f128_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src1, src2, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[127:0] := src1[127:0]
+ 	1:	tmp[127:0] := src1[255:128]
+ 	2:	tmp[127:0] := src2[127:0]
+ 	3:	tmp[127:0] := src2[255:128]
+ 	ESAC
+ 	IF control[3]
+ 		tmp[127:0] := 0
+ 	FI
+ 	RETURN tmp[127:0]
+ }
+ dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+ dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERM2F128" form="ymm, ymm, ymm, imm8" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permute2f128_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src1, src2, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[127:0] := src1[127:0]
+ 	1:	tmp[127:0] := src1[255:128]
+ 	2:	tmp[127:0] := src2[127:0]
+ 	3:	tmp[127:0] := src2[255:128]
+ 	ESAC
+ 	IF control[3]
+ 		tmp[127:0] := 0
+ 	FI
+ 	RETURN tmp[127:0]
+ }
+ dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+ dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERM2F128" form="ymm, ymm, ymm, imm8" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_permute2f128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src1, src2, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[127:0] := src1[127:0]
+ 	1:	tmp[127:0] := src1[255:128]
+ 	2:	tmp[127:0] := src2[127:0]
+ 	3:	tmp[127:0] := src2[255:128]
+ 	ESAC
+ 	IF control[3]
+ 		tmp[127:0] := 0
+ 	FI
+ 	RETURN tmp[127:0]
+ }
+ dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+ dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERM2F128" form="ymm, ymm, ymm, imm8" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_broadcast_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float const *" varname="mem_addr" etype="FP32" memwidth="32"/>
+ 	<description>Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".</description>
+ 	<operation>
+ tmp[31:0] := MEM[mem_addr+31:mem_addr]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := tmp[31:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="ymm, m32" xed="VBROADCASTSS_YMMqq_MEMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_broadcast_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<category>Swizzle</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="float const *" varname="mem_addr" etype="FP32" memwidth="32"/>
+ 	<description>Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".</description>
+ 	<operation>
+ tmp[31:0] := MEM[mem_addr+31:mem_addr]
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := tmp[31:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="xmm, m32" xed="VBROADCASTSS_XMMdq_MEMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_broadcast_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const *" varname="mem_addr" etype="FP64" memwidth="64"/>
+ 	<description>Broadcast a double-precision (64-bit) floating-point element from memory to all elements of "dst".</description>
+ 	<operation>
+ tmp[63:0] := MEM[mem_addr+63:mem_addr]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := tmp[63:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSD" form="ymm, m64" xed="VBROADCASTSD_YMMqq_MEMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_broadcast_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128 const *" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Broadcast 128 bits from memory (composed of 4 packed single-precision (32-bit) floating-point elements) to all elements of "dst".</description>
+ 	<operation>
+ tmp[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[127:0] := tmp[127:0]
+ dst[255:128] := tmp[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF128" form="ymm, m128" xed="VBROADCASTF128_YMMqq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_broadcast_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d const *" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Broadcast 128 bits from memory (composed of 2 packed double-precision (64-bit) floating-point elements) to all elements of "dst".</description>
+ 	<operation>
+ tmp[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[127:0] := tmp[127:0]
+ dst[255:128] := tmp[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF128" form="ymm, m128" xed="VBROADCASTF128_YMMqq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_insertf128_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_insertf128_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE imm8[0] OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_insertf128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m128i" varname="b" etype="M128"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_insert_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__int8" varname="i" etype="UI8"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="5"/>
+ 	<description>Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ sel := index[4:0]*8
+ dst[sel+7:sel] := i[7:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_insert_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__int16" varname="i" etype="UI16"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="4"/>
+ 	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ sel := index[3:0]*16
+ dst[sel+15:sel] := i[15:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_insert_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__int32" varname="i" etype="UI32"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="3"/>
+ 	<description>Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ sel := index[2:0]*32
+ dst[sel+31:sel] := i[31:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_insert_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__int64" varname="i" etype="UI64"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ sel := index[1:0]*64
+ dst[sel+63:sel] := i[63:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_load_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="ymm, m256" xed="VMOVAPD_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_store_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="double *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="m256, ymm" xed="VMOVAPD_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_load_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float const *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="ymm, m256" xed="VMOVAPS_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_store_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="float *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="m256, ymm" xed="VMOVAPS_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_loadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="ymm, m256" xed="VMOVUPD_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_storeu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="double *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="m256, ymm" xed="VMOVUPD_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_loadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float const *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="ymm, m256" xed="VMOVUPS_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_storeu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="float *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory.
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="m256, ymm" xed="VMOVUPS_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_load_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i const *" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<description>Load 256-bits of integer data from memory into "dst".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA" form="ymm, m256" xed="VMOVDQA_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_store_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__m256i *" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<description>Store 256-bits of integer data from "a" into memory.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQA" form="m256, ymm" xed="VMOVDQA_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_loadu_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i const *" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<description>Load 256-bits of integer data from memory into "dst".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU" form="ymm, m256" xed="VMOVDQU_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_storeu_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__m256i *" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<description>Store 256-bits of integer data from "a" into memory.
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU" form="m256, ymm" xed="VMOVDQU_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_maskload_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF mask[i+63]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMASKMOVPD" form="ymm, ymm, m256" xed="VMASKMOVPD_YMMqq_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_maskstore_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="double *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF mask[i+63]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMASKMOVPD" form="m256, ymm, ymm" xed="VMASKMOVPD_MEMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_maskload_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const *" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF mask[i+63]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMASKMOVPD" form="xmm, xmm, m128" xed="VMASKMOVPD_XMMdq_XMMdq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_maskstore_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="double *" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF mask[i+63]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMASKMOVPD" form="m128, xmm, xmm" xed="VMASKMOVPD_MEMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_maskload_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float const *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF mask[i+31]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMASKMOVPS" form="ymm, ymm, m256" xed="VMASKMOVPS_YMMqq_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_maskstore_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="float *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF mask[i+31]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMASKMOVPS" form="m256, ymm, ymm" xed="VMASKMOVPS_MEMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_maskload_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="float const *" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF mask[i+31]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMASKMOVPS" form="xmm, xmm, m128" xed="VMASKMOVPS_XMMdq_XMMdq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_maskstore_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="float *" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF mask[i+31]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMASKMOVPS" form="m128, xmm, xmm" xed="VMASKMOVPS_MEMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_movehdup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+ 	<operation>
+ dst[31:0] := a[63:32] 
+ dst[63:32] := a[63:32] 
+ dst[95:64] := a[127:96] 
+ dst[127:96] := a[127:96]
+ dst[159:128] := a[191:160] 
+ dst[191:160] := a[191:160] 
+ dst[223:192] := a[255:224] 
+ dst[255:224] := a[255:224]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVSHDUP" form="ymm, ymm" xed="VMOVSHDUP_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_moveldup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+ 	<operation>
+ dst[31:0] := a[31:0] 
+ dst[63:32] := a[31:0] 
+ dst[95:64] := a[95:64] 
+ dst[127:96] := a[95:64]
+ dst[159:128] := a[159:128] 
+ dst[191:160] := a[159:128] 
+ dst[223:192] := a[223:192] 
+ dst[255:224] := a[223:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVSLDUP" form="ymm, ymm" xed="VMOVSLDUP_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_movedup_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst".</description>
+ 	<operation>
+ dst[63:0] := a[63:0]
+ dst[127:64] := a[63:0]
+ dst[191:128] := a[191:128]
+ dst[255:192] := a[191:128]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDDUP" form="ymm, ymm" xed="VMOVDDUP_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_lddqu_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i const *" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<description>Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VLDDQU" form="ymm, m256" xed="VLDDQU_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_stream_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__m256i *" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<description>Store 256-bits of integer data from "a" into memory using a non-temporal memory hint.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVNTDQ" form="m256, ymm" xed="VMOVNTDQ_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_stream_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="double *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVNTPD" form="m256, ymm" xed="VMOVNTPD_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_stream_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="float *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVNTPS" form="m256, ymm" xed="VMOVNTPS_MEMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_rcp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := 1.0 / a[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCPPS" form="ymm, ymm" xed="VRCPPS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_rsqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRSQRTPS" form="ymm, ymm" xed="VRSQRTPS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_sqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SQRT(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPD" form="ymm, ymm" xed="VSQRTPD_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_sqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SQRT(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPS" form="ymm, ymm" xed="VSQRTPS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" immtype="_MM_FROUND"/>
+ 	<description>Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst".
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ROUND(a[i+63:i], rounding)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VROUNDPD" form="ymm, ymm, imm8" xed="VROUNDPD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" immtype="_MM_FROUND"/>
+ 	<description>Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst".
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ROUND(a[i+31:i], rounding)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VROUNDPS" form="ymm, ymm, imm8" xed="VROUNDPS_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_unpackhi_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPD" form="ymm, ymm, ymm" xed="VUNPCKHPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_unpackhi_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPS" form="ymm, ymm, ymm" xed="VUNPCKHPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_unpacklo_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPD" form="ymm, ymm, ymm" xed="VUNPCKLPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_unpacklo_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPS" form="ymm, ymm, ymm" xed="VUNPCKLPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testz_si256">
+ 	<type>Integer</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="k" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+ 	<operation>
+ IF ((a[255:0] AND b[255:0]) == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ IF (((NOT a[255:0]) AND b[255:0]) == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ RETURN ZF
+ 	</operation>
+ 	<instruction name="VPTEST" form="ymm, ymm" xed="VPTEST_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testc_si256">
+ 	<type>Integer</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="k" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+ 	<operation>
+ IF ((a[255:0] AND b[255:0]) == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ IF (((NOT a[255:0]) AND b[255:0]) == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ RETURN CF
+ 	</operation>
+ 	<instruction name="VPTEST" form="ymm, ymm" xed="VPTEST_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testnzc_si256">
+ 	<type>Integer</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+ 	<operation>
+ IF ((a[255:0] AND b[255:0]) == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ IF (((NOT a[255:0]) AND b[255:0]) == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ IF (ZF == 0 &amp;&amp; CF == 0)
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="VPTEST" form="ymm, ymm" xed="VPTEST_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testz_pd">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+ 	<operation>
+ tmp[255:0] := a[255:0] AND b[255:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := ZF
+ 	</operation>
+ 	<instruction name="VTESTPD" form="ymm, ymm" xed="VTESTPD_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testc_pd">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+ 	<operation>
+ tmp[255:0] := a[255:0] AND b[255:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := CF
+ 	</operation>
+ 	<instruction name="VTESTPD" form="ymm, ymm" xed="VTESTPD_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testnzc_pd">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+ 	<operation>
+ tmp[255:0] := a[255:0] AND b[255:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ IF (ZF == 0 &amp;&amp; CF == 0)
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="VTESTPD" form="ymm, ymm" xed="VTESTPD_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_testz_pd">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+ 	<operation>
+ tmp[127:0] := a[127:0] AND b[127:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := ZF
+ 	</operation>
+ 	<instruction name="VTESTPD" form="xmm, xmm" xed="VTESTPD_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_testc_pd">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+ 	<operation>
+ tmp[127:0] := a[127:0] AND b[127:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := CF
+ 	</operation>
+ 	<instruction name="VTESTPD" form="xmm, xmm" xed="VTESTPD_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_testnzc_pd">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+ 	<operation>
+ tmp[127:0] := a[127:0] AND b[127:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+ IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ IF (ZF == 0 &amp;&amp; CF == 0)
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="VTESTPD" form="xmm, xmm" xed="VTESTPD_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testz_ps">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+ 	<operation>
+ tmp[255:0] := a[255:0] AND b[255:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+     tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+     tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := ZF
+ 	</operation>
+ 	<instruction name="VTESTPS" form="ymm, ymm" xed="VTESTPS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testc_ps">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+ 	<operation>
+ tmp[255:0] := a[255:0] AND b[255:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+     tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+     tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := CF
+ 	</operation>
+ 	<instruction name="VTESTPS" form="ymm, ymm" xed="VTESTPS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_testnzc_ps">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+ 	<operation>
+ tmp[255:0] := a[255:0] AND b[255:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+     tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+     tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ IF (ZF == 0 &amp;&amp; CF == 0)
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="VTESTPS" form="ymm, ymm" xed="VTESTPS_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_testz_ps">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+ 	<operation>
+ tmp[127:0] := a[127:0] AND b[127:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := ZF
+ 	</operation>
+ 	<instruction name="VTESTPS" form="xmm, xmm" xed="VTESTPS_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_testc_ps">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+ 	<operation>
+ tmp[127:0] := a[127:0] AND b[127:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ dst := CF
+ 	</operation>
+ 	<instruction name="VTESTPS" form="xmm, xmm" xed="VTESTPS_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm_testnzc_ps">
+ 	<type>Floating Point</type>
+ 	<type>Flag</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Logical</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+ 	<operation>
+ tmp[127:0] := a[127:0] AND b[127:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+ 	ZF := 1
+ ELSE
+ 	ZF := 0
+ FI
+ tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+ IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+ 	CF := 1
+ ELSE
+ 	CF := 0
+ FI
+ IF (ZF == 0 &amp;&amp; CF == 0)
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="VTESTPS" form="xmm, xmm" xed="VTESTPS_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_movemask_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF a[i+63]
+ 		dst[j] := 1
+ 	ELSE
+ 		dst[j] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VMOVMSKPD" form="r32, ymm" xed="VMOVMSKPD_GPR32d_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_movemask_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF a[i+31]
+ 		dst[j] := 1
+ 	ELSE
+ 		dst[j] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VMOVMSKPS" form="r32, ymm" xed="VMOVMSKPS_GPR32d_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_setzero_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="void"/>
+ 	<description>Return vector of type __m256d with all elements set to zero.</description>
+ 	<operation>
+ dst[MAX:0] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="ymm, ymm, ymm" xed="VXORPD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_setzero_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="void"/>
+ 	<description>Return vector of type __m256 with all elements set to zero.</description>
+ 	<operation>
+ dst[MAX:0] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="ymm, ymm, ymm" xed="VXORPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_setzero_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="void"/>
+ 	<description>Return vector of type __m256i with all elements set to zero.</description>
+ 	<operation>
+ dst[MAX:0] := 0
+ 	</operation>
+ 	<instruction name="VPXOR" form="ymm, ymm, ymm" xed="VPXOR_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double" varname="e3" etype="FP64"/>
+ 	<parameter type="double" varname="e2" etype="FP64"/>
+ 	<parameter type="double" varname="e1" etype="FP64"/>
+ 	<parameter type="double" varname="e0" etype="FP64"/>
+ 	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
+ 	<operation>
+ dst[63:0] := e0
+ dst[127:64] := e1
+ dst[191:128] := e2
+ dst[255:192] := e3
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float" varname="e7" etype="FP32"/>
+ 	<parameter type="float" varname="e6" etype="FP32"/>
+ 	<parameter type="float" varname="e5" etype="FP32"/>
+ 	<parameter type="float" varname="e4" etype="FP32"/>
+ 	<parameter type="float" varname="e3" etype="FP32"/>
+ 	<parameter type="float" varname="e2" etype="FP32"/>
+ 	<parameter type="float" varname="e1" etype="FP32"/>
+ 	<parameter type="float" varname="e0" etype="FP32"/>
+ 	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
+ 	<operation>
+ dst[31:0] := e0
+ dst[63:32] := e1
+ dst[95:64] := e2
+ dst[127:96] := e3
+ dst[159:128] := e4
+ dst[191:160] := e5
+ dst[223:192] := e6
+ dst[255:224] := e7
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="char" varname="e31" etype="UI8"/>
+ 	<parameter type="char" varname="e30" etype="UI8"/>
+ 	<parameter type="char" varname="e29" etype="UI8"/>
+ 	<parameter type="char" varname="e28" etype="UI8"/>
+ 	<parameter type="char" varname="e27" etype="UI8"/>
+ 	<parameter type="char" varname="e26" etype="UI8"/>
+ 	<parameter type="char" varname="e25" etype="UI8"/>
+ 	<parameter type="char" varname="e24" etype="UI8"/>
+ 	<parameter type="char" varname="e23" etype="UI8"/>
+ 	<parameter type="char" varname="e22" etype="UI8"/>
+ 	<parameter type="char" varname="e21" etype="UI8"/>
+ 	<parameter type="char" varname="e20" etype="UI8"/>
+ 	<parameter type="char" varname="e19" etype="UI8"/>
+ 	<parameter type="char" varname="e18" etype="UI8"/>
+ 	<parameter type="char" varname="e17" etype="UI8"/>
+ 	<parameter type="char" varname="e16" etype="UI8"/>
+ 	<parameter type="char" varname="e15" etype="UI8"/>
+ 	<parameter type="char" varname="e14" etype="UI8"/>
+ 	<parameter type="char" varname="e13" etype="UI8"/>
+ 	<parameter type="char" varname="e12" etype="UI8"/>
+ 	<parameter type="char" varname="e11" etype="UI8"/>
+ 	<parameter type="char" varname="e10" etype="UI8"/>
+ 	<parameter type="char" varname="e9" etype="UI8"/>
+ 	<parameter type="char" varname="e8" etype="UI8"/>
+ 	<parameter type="char" varname="e7" etype="UI8"/>
+ 	<parameter type="char" varname="e6" etype="UI8"/>
+ 	<parameter type="char" varname="e5" etype="UI8"/>
+ 	<parameter type="char" varname="e4" etype="UI8"/>
+ 	<parameter type="char" varname="e3" etype="UI8"/>
+ 	<parameter type="char" varname="e2" etype="UI8"/>
+ 	<parameter type="char" varname="e1" etype="UI8"/>
+ 	<parameter type="char" varname="e0" etype="UI8"/>
+ 	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
+ 	<operation>
+ dst[7:0] := e0
+ dst[15:8] := e1
+ dst[23:16] := e2
+ dst[31:24] := e3
+ dst[39:32] := e4
+ dst[47:40] := e5
+ dst[55:48] := e6
+ dst[63:56] := e7
+ dst[71:64] := e8
+ dst[79:72] := e9
+ dst[87:80] := e10
+ dst[95:88] := e11
+ dst[103:96] := e12
+ dst[111:104] := e13
+ dst[119:112] := e14
+ dst[127:120] := e15
+ dst[135:128] := e16
+ dst[143:136] := e17
+ dst[151:144] := e18
+ dst[159:152] := e19
+ dst[167:160] := e20
+ dst[175:168] := e21
+ dst[183:176] := e22
+ dst[191:184] := e23
+ dst[199:192] := e24
+ dst[207:200] := e25
+ dst[215:208] := e26
+ dst[223:216] := e27
+ dst[231:224] := e28
+ dst[239:232] := e29
+ dst[247:240] := e30
+ dst[255:248] := e31
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="short" varname="e15" etype="UI16"/>
+ 	<parameter type="short" varname="e14" etype="UI16"/>
+ 	<parameter type="short" varname="e13" etype="UI16"/>
+ 	<parameter type="short" varname="e12" etype="UI16"/>
+ 	<parameter type="short" varname="e11" etype="UI16"/>
+ 	<parameter type="short" varname="e10" etype="UI16"/>
+ 	<parameter type="short" varname="e9" etype="UI16"/>
+ 	<parameter type="short" varname="e8" etype="UI16"/>
+ 	<parameter type="short" varname="e7" etype="UI16"/>
+ 	<parameter type="short" varname="e6" etype="UI16"/>
+ 	<parameter type="short" varname="e5" etype="UI16"/>
+ 	<parameter type="short" varname="e4" etype="UI16"/>
+ 	<parameter type="short" varname="e3" etype="UI16"/>
+ 	<parameter type="short" varname="e2" etype="UI16"/>
+ 	<parameter type="short" varname="e1" etype="UI16"/>
+ 	<parameter type="short" varname="e0" etype="UI16"/>
+ 	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
+ 	<operation>
+ dst[15:0] := e0
+ dst[31:16] := e1
+ dst[47:32] := e2
+ dst[63:48] := e3
+ dst[79:64] := e4
+ dst[95:80] := e5
+ dst[111:96] := e6
+ dst[127:112] := e7
+ dst[143:128] := e8
+ dst[159:144] := e9
+ dst[175:160] := e10
+ dst[191:176] := e11
+ dst[207:192] := e12
+ dst[223:208] := e13
+ dst[239:224] := e14
+ dst[255:240] := e15
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="int" varname="e7" etype="UI32"/>
+ 	<parameter type="int" varname="e6" etype="UI32"/>
+ 	<parameter type="int" varname="e5" etype="UI32"/>
+ 	<parameter type="int" varname="e4" etype="UI32"/>
+ 	<parameter type="int" varname="e3" etype="UI32"/>
+ 	<parameter type="int" varname="e2" etype="UI32"/>
+ 	<parameter type="int" varname="e1" etype="UI32"/>
+ 	<parameter type="int" varname="e0" etype="UI32"/>
+ 	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
+ 	<operation>
+ dst[31:0] := e0
+ dst[63:32] := e1
+ dst[95:64] := e2
+ dst[127:96] := e3
+ dst[159:128] := e4
+ dst[191:160] := e5
+ dst[223:192] := e6
+ dst[255:224] := e7
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set_epi64x">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64" varname="e3" etype="UI64"/>
+ 	<parameter type="__int64" varname="e2" etype="UI64"/>
+ 	<parameter type="__int64" varname="e1" etype="UI64"/>
+ 	<parameter type="__int64" varname="e0" etype="UI64"/>
+ 	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
+ 	<operation>
+ dst[63:0] := e0
+ dst[127:64] := e1
+ dst[191:128] := e2
+ dst[255:192] := e3
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_setr_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double" varname="e3" etype="FP64"/>
+ 	<parameter type="double" varname="e2" etype="FP64"/>
+ 	<parameter type="double" varname="e1" etype="FP64"/>
+ 	<parameter type="double" varname="e0" etype="FP64"/>
+ 	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+ 	<operation>
+ dst[63:0] := e3
+ dst[127:64] := e2
+ dst[191:128] := e1
+ dst[255:192] := e0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_setr_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float" varname="e7" etype="FP32"/>
+ 	<parameter type="float" varname="e6" etype="FP32"/>
+ 	<parameter type="float" varname="e5" etype="FP32"/>
+ 	<parameter type="float" varname="e4" etype="FP32"/>
+ 	<parameter type="float" varname="e3" etype="FP32"/>
+ 	<parameter type="float" varname="e2" etype="FP32"/>
+ 	<parameter type="float" varname="e1" etype="FP32"/>
+ 	<parameter type="float" varname="e0" etype="FP32"/>
+ 	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+ 	<operation>
+ dst[31:0] := e7
+ dst[63:32] := e6
+ dst[95:64] := e5
+ dst[127:96] := e4
+ dst[159:128] := e3
+ dst[191:160] := e2
+ dst[223:192] := e1
+ dst[255:224] := e0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_setr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="char" varname="e31" etype="UI8"/>
+ 	<parameter type="char" varname="e30" etype="UI8"/>
+ 	<parameter type="char" varname="e29" etype="UI8"/>
+ 	<parameter type="char" varname="e28" etype="UI8"/>
+ 	<parameter type="char" varname="e27" etype="UI8"/>
+ 	<parameter type="char" varname="e26" etype="UI8"/>
+ 	<parameter type="char" varname="e25" etype="UI8"/>
+ 	<parameter type="char" varname="e24" etype="UI8"/>
+ 	<parameter type="char" varname="e23" etype="UI8"/>
+ 	<parameter type="char" varname="e22" etype="UI8"/>
+ 	<parameter type="char" varname="e21" etype="UI8"/>
+ 	<parameter type="char" varname="e20" etype="UI8"/>
+ 	<parameter type="char" varname="e19" etype="UI8"/>
+ 	<parameter type="char" varname="e18" etype="UI8"/>
+ 	<parameter type="char" varname="e17" etype="UI8"/>
+ 	<parameter type="char" varname="e16" etype="UI8"/>
+ 	<parameter type="char" varname="e15" etype="UI8"/>
+ 	<parameter type="char" varname="e14" etype="UI8"/>
+ 	<parameter type="char" varname="e13" etype="UI8"/>
+ 	<parameter type="char" varname="e12" etype="UI8"/>
+ 	<parameter type="char" varname="e11" etype="UI8"/>
+ 	<parameter type="char" varname="e10" etype="UI8"/>
+ 	<parameter type="char" varname="e9" etype="UI8"/>
+ 	<parameter type="char" varname="e8" etype="UI8"/>
+ 	<parameter type="char" varname="e7" etype="UI8"/>
+ 	<parameter type="char" varname="e6" etype="UI8"/>
+ 	<parameter type="char" varname="e5" etype="UI8"/>
+ 	<parameter type="char" varname="e4" etype="UI8"/>
+ 	<parameter type="char" varname="e3" etype="UI8"/>
+ 	<parameter type="char" varname="e2" etype="UI8"/>
+ 	<parameter type="char" varname="e1" etype="UI8"/>
+ 	<parameter type="char" varname="e0" etype="UI8"/>
+ 	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
+ 	<operation>
+ dst[7:0] := e31
+ dst[15:8] := e30
+ dst[23:16] := e29
+ dst[31:24] := e28
+ dst[39:32] := e27
+ dst[47:40] := e26
+ dst[55:48] := e25
+ dst[63:56] := e24
+ dst[71:64] := e23
+ dst[79:72] := e22
+ dst[87:80] := e21
+ dst[95:88] := e20
+ dst[103:96] := e19
+ dst[111:104] := e18
+ dst[119:112] := e17
+ dst[127:120] := e16
+ dst[135:128] := e15
+ dst[143:136] := e14
+ dst[151:144] := e13
+ dst[159:152] := e12
+ dst[167:160] := e11
+ dst[175:168] := e10
+ dst[183:176] := e9
+ dst[191:184] := e8
+ dst[199:192] := e7
+ dst[207:200] := e6
+ dst[215:208] := e5
+ dst[223:216] := e4
+ dst[231:224] := e3
+ dst[239:232] := e2
+ dst[247:240] := e1
+ dst[255:248] := e0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_setr_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="short" varname="e15" etype="UI16"/>
+ 	<parameter type="short" varname="e14" etype="UI16"/>
+ 	<parameter type="short" varname="e13" etype="UI16"/>
+ 	<parameter type="short" varname="e12" etype="UI16"/>
+ 	<parameter type="short" varname="e11" etype="UI16"/>
+ 	<parameter type="short" varname="e10" etype="UI16"/>
+ 	<parameter type="short" varname="e9" etype="UI16"/>
+ 	<parameter type="short" varname="e8" etype="UI16"/>
+ 	<parameter type="short" varname="e7" etype="UI16"/>
+ 	<parameter type="short" varname="e6" etype="UI16"/>
+ 	<parameter type="short" varname="e5" etype="UI16"/>
+ 	<parameter type="short" varname="e4" etype="UI16"/>
+ 	<parameter type="short" varname="e3" etype="UI16"/>
+ 	<parameter type="short" varname="e2" etype="UI16"/>
+ 	<parameter type="short" varname="e1" etype="UI16"/>
+ 	<parameter type="short" varname="e0" etype="UI16"/>
+ 	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
+ 	<operation>
+ dst[15:0] := e15
+ dst[31:16] := e14
+ dst[47:32] := e13
+ dst[63:48] := e12
+ dst[79:64] := e11
+ dst[95:80] := e10
+ dst[111:96] := e9
+ dst[127:112] := e8
+ dst[143:128] := e7
+ dst[159:144] := e6
+ dst[175:160] := e5
+ dst[191:176] := e4
+ dst[207:192] := e3
+ dst[223:208] := e2
+ dst[239:224] := e1
+ dst[255:240] := e0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_setr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="int" varname="e7" etype="UI32"/>
+ 	<parameter type="int" varname="e6" etype="UI32"/>
+ 	<parameter type="int" varname="e5" etype="UI32"/>
+ 	<parameter type="int" varname="e4" etype="UI32"/>
+ 	<parameter type="int" varname="e3" etype="UI32"/>
+ 	<parameter type="int" varname="e2" etype="UI32"/>
+ 	<parameter type="int" varname="e1" etype="UI32"/>
+ 	<parameter type="int" varname="e0" etype="UI32"/>
+ 	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
+ 	<operation>
+ dst[31:0] := e7
+ dst[63:32] := e6
+ dst[95:64] := e5
+ dst[127:96] := e4
+ dst[159:128] := e3
+ dst[191:160] := e2
+ dst[223:192] := e1
+ dst[255:224] := e0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_setr_epi64x">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64" varname="e3" etype="UI64"/>
+ 	<parameter type="__int64" varname="e2" etype="UI64"/>
+ 	<parameter type="__int64" varname="e1" etype="UI64"/>
+ 	<parameter type="__int64" varname="e0" etype="UI64"/>
+ 	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
+ 	<operation>
+ dst[63:0] := e3
+ dst[127:64] := e2
+ dst[191:128] := e1
+ dst[255:192] := e0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set1_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double" varname="a" etype="FP64"/>
+ 	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[63:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set1_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float" varname="a" etype="FP32"/>
+ 	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[31:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := a[7:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := a[15:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set1_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="int" varname="a" etype="UI32"/>
+ 	<description>Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[31:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_set1_epi64x">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="long long" varname="a" etype="UI64"/>
+ 	<description>Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[63:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castpd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Cast vector of type __m256d to type __m256.
+ 	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castps_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Cast vector of type __m256 to type __m256d.
+ 	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castps_si256">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Cast vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castpd_si256">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Cast vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castsi256_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Cast vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castsi256_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Cast vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castps256_ps128">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Cast vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castpd256_pd128">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Cast vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castsi256_si128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<description>Cast vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castps128_ps256">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Cast vector of type __m128 to type __m256; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castpd128_pd256">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_castsi128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m128i" varname="a" etype="M256"/>
+ 	<description>Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_zextps128_ps256">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Cast vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_zextpd128_pd256">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_zextsi128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Cast</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m128i" varname="a" etype="M256"/>
+ 	<description>Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_floor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := FLOOR(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VROUNDPS" form="ymm, ymm, imm8" xed="VROUNDPS_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_ceil_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := CEIL(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VROUNDPS" form="ymm, ymm, imm8" xed="VROUNDPS_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_floor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := FLOOR(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VROUNDPD" form="ymm, ymm, imm8" xed="VROUNDPD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_ceil_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CEIL(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VROUNDPD" form="ymm, ymm, imm8" xed="VROUNDPD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_undefined_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>General Support</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="void"/>
+ 	<description>Return vector of type __m256 with undefined elements.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_undefined_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>General Support</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="void"/>
+ 	<description>Return vector of type __m256d with undefined elements.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_undefined_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>General Support</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="void"/>
+ 	<description>Return vector of type __m256i with undefined elements.</description>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_set_m128">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="hi" etype="FP32"/>
+ 	<parameter type="__m128" varname="lo" etype="FP32"/>
+ 	<description>Set packed __m256 vector "dst" with the supplied values.</description>
+ 	<operation>
+ dst[127:0] := lo[127:0]
+ dst[255:128] := hi[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_set_m128d">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="hi" etype="FP64"/>
+ 	<parameter type="__m128d" varname="lo" etype="FP64"/>
+ 	<description>Set packed __m256d vector "dst" with the supplied values.</description>
+ 	<operation>
+ dst[127:0] := lo[127:0]
+ dst[255:128] := hi[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_set_m128i">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="hi" etype="M128"/>
+ 	<parameter type="__m128i" varname="lo" etype="M128"/>
+ 	<description>Set packed __m256i vector "dst" with the supplied values.</description>
+ 	<operation>
+ dst[127:0] := lo[127:0]
+ dst[255:128] := hi[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_setr_m128">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="lo" etype="FP32"/>
+ 	<parameter type="__m128" varname="hi" etype="FP32"/>
+ 	<description>Set packed __m256 vector "dst" with the supplied values.</description>
+ 	<operation>
+ dst[127:0] := lo[127:0]
+ dst[255:128] := hi[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_setr_m128d">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="lo" etype="FP64"/>
+ 	<parameter type="__m128d" varname="hi" etype="FP64"/>
+ 	<description>Set packed __m256d vector "dst" with the supplied values.</description>
+ 	<operation>
+ dst[127:0] := lo[127:0]
+ dst[255:128] := hi[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" name="_mm256_setr_m128i">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="lo" etype="M128"/>
+ 	<parameter type="__m128i" varname="hi" etype="M128"/>
+ 	<description>Set packed __m256i vector "dst" with the supplied values.</description>
+ 	<operation>
+ dst[127:0] := lo[127:0]
+ dst[255:128] := hi[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF128" form="ymm, ymm, xmm, imm8" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_loadu2_m128">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float const*" varname="hiaddr" etype="FP32" memwidth="128"/>
+ 	<parameter type="float const*" varname="loaddr" etype="FP32" memwidth="128"/>
+ 	<description>Load two 128-bit values (composed of 4 packed single-precision (32-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst".
+ 	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[loaddr+127:loaddr]
+ dst[255:128] := MEM[hiaddr+127:hiaddr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_loadu2_m128d">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const*" varname="hiaddr" etype="FP64" memwidth="128"/>
+ 	<parameter type="double const*" varname="loaddr" etype="FP64" memwidth="128"/>
+ 	<description>Load two 128-bit values (composed of 2 packed double-precision (64-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst".
+ 	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[loaddr+127:loaddr]
+ dst[255:128] := MEM[hiaddr+127:hiaddr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_loadu2_m128i">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i const*" varname="hiaddr" etype="M128" memwidth="128"/>
+ 	<parameter type="__m128i const*" varname="loaddr" etype="M128" memwidth="128"/>
+ 	<description>Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst".
+ 	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[loaddr+127:loaddr]
+ dst[255:128] := MEM[hiaddr+127:hiaddr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_storeu2_m128">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="float*" varname="hiaddr" etype="FP32" memwidth="128"/>
+ 	<parameter type="float*" varname="loaddr" etype="FP32" memwidth="128"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store the high and low 128-bit halves (each composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory two different 128-bit locations.
+ 	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[loaddr+127:loaddr] := a[127:0]
+ MEM[hiaddr+127:hiaddr] := a[255:128]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_storeu2_m128d">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="double*" varname="hiaddr" etype="FP64" memwidth="128"/>
+ 	<parameter type="double*" varname="loaddr" etype="FP64" memwidth="128"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store the high and low 128-bit halves (each composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory two different 128-bit locations.
+ 	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[loaddr+127:loaddr] := a[127:0]
+ MEM[hiaddr+127:hiaddr] := a[255:128]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" sequence="TRUE" name="_mm256_storeu2_m128i">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__m128i*" varname="hiaddr" etype="M128" memwidth="128"/>
+ 	<parameter type="__m128i*" varname="loaddr" etype="M128" memwidth="128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<description>Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations.
+ 	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[loaddr+127:loaddr] := a[127:0]
+ MEM[hiaddr+127:hiaddr] := a[255:128]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_acos_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ACOS(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_acos_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ACOS(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_acosh_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ACOSH(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_acosh_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ACOSH(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_asin_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ASIN(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_asin_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ASIN(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_asinh_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ASINH(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_asinh_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ASINH(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_atan_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ATAN(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_atan_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ATAN(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_atan2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_atan2_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_atanh_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ATANH(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_atanh_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ATANH(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cbrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CubeRoot(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cbrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := CubeRoot(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cdfnorm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CDFNormal(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cdfnorm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := CDFNormal(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cdfnorminv_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cdfnorminv_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+ 	<operation>
+ DEFINE CEXP(a[31:0], b[31:0]) {
+ 	result[31:0]  := POW(FP32(e), a[31:0]) * COS(b[31:0])
+ 	result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0])
+ 	RETURN result
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_clog_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+ 	<operation>
+ DEFINE CLOG(a[31:0], b[31:0]) {
+ 	result[31:0]  := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0)))
+ 	result[63:32] := ATAN2(b, a)
+ 	RETURN result
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cos_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := COS(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cos_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := COS(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cosd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := COSD(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cosd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := COSD(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cosh_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := COSH(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_cosh_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := COSH(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_csqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+ 	<operation>
+ DEFINE CSQRT(a[31:0], b[31:0]) {
+ 	sign[31:0] := (b &lt; 0.0) ? -FP32(1.0) : FP32(1.0)
+ 	result[31:0]  := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
+ 	result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
+ 	RETURN result
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 8*j
+ 	IF b[i+7:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	IF b[i+15:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF b[i+31:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	IF b[i+63:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 8*j
+ 	IF b[i+7:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	IF b[i+15:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF b[i+31:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_div_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	IF b[i+63:i] == 0
+ 		#DE
+ 	FI
+ 	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erf_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ERF(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erf_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ERF(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erfc_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erfc_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erfcinv_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erfcinv_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erfinv_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_erfinv_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_exp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := POW(e, a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_exp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := POW(FP32(e), a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_exp10_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := POW(10.0, a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_exp10_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_exp2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := POW(2.0, a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_exp2_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_expm1_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_expm1_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_hypot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_hypot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_idiv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_idivrem_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i *" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ 	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_invcbrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := InvCubeRoot(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_invcbrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := InvCubeRoot(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_invsqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := InvSQRT(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_invsqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := InvSQRT(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_irem_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := LOG(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := LOG(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log10_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log10_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log1p_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := LOG(1.0 + a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log1p_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := LOG(1.0 + a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_log2_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_logb_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_logb_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_pow_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_pow_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 31
+ 	i := 8*j
+ 	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 15
+ 	i := 16*j
+ 	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := 64*j
+ 	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 31
+ 	i := 8*j
+ 	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 15
+ 	i := 16*j
+ 	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_rem_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := 64*j
+ 	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sin_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SIN(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sin_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SIN(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sincos_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d *" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SIN(a[i+63:i])
+ 	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sincos_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256 *" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SIN(a[i+31:i])
+ 	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sind_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SIND(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sind_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SIND(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sinh_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SINH(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_sinh_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SINH(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_ceil_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := CEIL(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_ceil_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := CEIL(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_floor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := FLOOR(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_floor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := FLOOR(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ROUND(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ROUND(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_sqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SQRT(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_svml_sqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SQRT(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_tan_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := TAN(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_tan_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := TAN(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_tand_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := TAND(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_tand_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := TAND(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_tanh_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := TANH(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_tanh_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Trigonometry</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := TANH(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_trunc_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := TRUNCATE(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_trunc_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := TRUNCATE(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_udiv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_udivrem_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i *" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ 	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="SVML" sequence="TRUE" name="_mm256_urem_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" vexEq="TRUE" name="_mm256_cvtss_f32">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="float" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
+ 	<operation>
+ dst[31:0] := a[31:0]
+ 	</operation>
+ 	<instruction name="VMOVSS" form="m32, xmm" xed="VMOVSS_MEMd_XMMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" vexEq="TRUE" name="_mm256_cvtsd_f64">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="double" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
+ 	<operation>
+ dst[63:0] := a[63:0]
+ 	</operation>
+ 	<instruction name="VMOVSD" form="m64, xmm" xed="VMOVSD_MEMq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX" vexEq="TRUE" name="_mm256_cvtsi256_si32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX</CPUID>
+ 	<category>Convert</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
+ 	<operation>
+ dst[31:0] := a[31:0]
+ 	</operation>
+ 	<instruction name="VMOVD" form="r32, xmm" xed="VMOVD_GPR32d_XMMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" sequence="TRUE" name="_mm256_extract_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="int" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="5"/>
+ 	<description>Extract an 8-bit integer from "a", selected with "index", and store the result in "dst".</description>
+ 	<operation>
+ dst[7:0] := (a[255:0] &gt;&gt; (index[4:0] * 8))[7:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" sequence="TRUE" name="_mm256_extract_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="int" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="const int" varname="index" etype="IMM" immwidth="4"/>
+ 	<description>Extract a 16-bit integer from "a", selected with "index", and store the result in "dst".</description>
+ 	<operation>
+ dst[15:0] := (a[255:0] &gt;&gt; (index[3:0] * 16))[15:0]
+ 	</operation>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := ABS(a[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="ymm, ymm" xed="VPABSB_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := ABS(a[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="ymm, ymm" xed="VPABSW_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_abs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ABS(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSD" form="ymm, ymm" xed="VPABSD_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="ymm, ymm, ymm" xed="VPADDB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="ymm, ymm, ymm" xed="VPADDW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_add_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDD" form="ymm, ymm, ymm" xed="VPADDD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_add_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDQ" form="ymm, ymm, ymm" xed="VPADDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="ymm, ymm, ymm" xed="VPADDSB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="ymm, ymm, ymm" xed="VPADDSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="ymm, ymm, ymm" xed="VPADDUSB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="ymm, ymm, ymm" xed="VPADDUSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*128
+ 	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+ 	dst[i+127:i] := tmp[127:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="ymm, ymm, ymm, imm8" xed="VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_and_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+ 	<operation>
+ dst[255:0] := (a[255:0] AND b[255:0])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAND" form="ymm, ymm, ymm" xed="VPAND_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_andnot_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
+ 	<operation>
+ dst[255:0] := ((NOT a[255:0]) AND b[255:0])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDN" form="ymm, ymm, ymm" xed="VPANDN_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="ymm, ymm, ymm" xed="VPAVGB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Probability/Statistics</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="ymm, ymm, ymm" xed="VPAVGW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_blend_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF imm8[j%8]
+ 		dst[i+15:i] := b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDW" form="ymm, ymm, ymm, imm8" xed="VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_blend_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF imm8[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDD" form="xmm, xmm, xmm, imm8" xed="VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_blend_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF imm8[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDD" form="ymm, ymm, ymm, imm8" xed="VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_blendv_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<description>Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF mask[i+7]
+ 		dst[i+7:i] := b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDVB" form="ymm, ymm, ymm, ymm" xed="VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	dst[i+7:i] := a[7:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="xmm, xmm" xed="VPBROADCASTB_XMMdq_XMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := a[7:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="ymm, xmm" xed="VPBROADCASTB_YMMqq_XMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_broadcastd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := a[31:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="xmm, xmm" xed="VPBROADCASTD_XMMdq_XMMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[31:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="ymm, xmm" xed="VPBROADCASTD_YMMqq_XMMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_broadcastq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := a[63:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="xmm, xmm" xed="VPBROADCASTQ_XMMdq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[63:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="ymm, xmm" xed="VPBROADCASTQ_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" vexEq="TRUE" name="_mm_broadcastsd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := a[63:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="MOVDDUP" form="xmm, xmm" xed="MOVDDUP_XMMdq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastsd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[63:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSD" form="ymm, xmm" xed="VBROADCASTSD_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_broadcastsi128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<description>Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".</description>
+ 	<operation>
+ dst[127:0] := a[127:0]
+ dst[255:128] := a[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI128" form="ymm, m128" xed="VBROADCASTI128_YMMqq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastsi128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m128i" varname="a" etype="M128"/>
+ 	<description>Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".</description>
+ 	<operation>
+ dst[127:0] := a[127:0]
+ dst[255:128] := a[127:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI128" form="ymm, m128" xed="VBROADCASTI128_YMMqq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_broadcastss_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := a[31:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="xmm, xmm" xed="VBROADCASTSS_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastss_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[31:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="ymm, xmm" xed="VBROADCASTSS_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	dst[i+15:i] := a[15:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="xmm, xmm" xed="VPBROADCASTW_XMMdq_XMMw"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := a[15:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="ymm, xmm" xed="VPBROADCASTW_YMMqq_XMMw"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpeq_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPEQB" form="ymm, ymm, ymm" xed="VPCMPEQB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpeq_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPEQW" form="ymm, ymm, ymm" xed="VPCMPEQW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpeq_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPEQD" form="ymm, ymm, ymm" xed="VPCMPEQD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpeq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPEQQ" form="ymm, ymm, ymm" xed="VPCMPEQQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpgt_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPGTB" form="ymm, ymm, ymm" xed="VPCMPGTB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpgt_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPGTW" form="ymm, ymm, ymm" xed="VPCMPGTW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpgt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPGTD" form="ymm, ymm, ymm" xed="VPCMPGTD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cmpgt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ( a[i+63:i] &gt; b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCMPGTQ" form="ymm, ymm, ymm" xed="VPCMPGTQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepi16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j:= 0 to 7
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[i+31:i] := SignExtend32(a[k+15:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWD" form="ymm, xmm" xed="VPMOVSXWD_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepi16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j:= 0 to 3
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[i+63:i] := SignExtend64(a[k+15:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWQ" form="ymm, xmm" xed="VPMOVSXWQ_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepi32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j:= 0 to 3
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[i+63:i] := SignExtend64(a[k+31:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXDQ" form="ymm, xmm" xed="VPMOVSXDQ_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	l := j*16
+ 	dst[l+15:l] := SignExtend16(a[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="ymm, xmm" xed="VPMOVSXBW_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepi8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[i+31:i] := SignExtend32(a[k+7:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBD" form="ymm, xmm" xed="VPMOVSXBD_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepi8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[i+63:i] := SignExtend64(a[k+7:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBQ" form="ymm, xmm" xed="VPMOVSXBQ_YMMqq_XMMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepu16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[i+31:i] := ZeroExtend32(a[k+15:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWD" form="ymm, xmm" xed="VPMOVZXWD_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepu16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j:= 0 to 3
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[i+63:i] := ZeroExtend64(a[k+15:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWQ" form="ymm, xmm" xed="VPMOVZXWQ_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepu32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j:= 0 to 3
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[i+63:i] := ZeroExtend64(a[k+31:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXDQ" form="ymm, xmm" xed="VPMOVZXDQ_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	l := j*16
+ 	dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="ymm, xmm" xed="VPMOVZXBW_YMMqq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepu8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[i+31:i] := ZeroExtend32(a[k+7:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBD" form="ymm, xmm" xed="VPMOVZXBD_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_cvtepu8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[i+63:i] := ZeroExtend64(a[k+7:k])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBQ" form="ymm, xmm" xed="VPMOVZXBQ_YMMqq_XMMd"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_extracti128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m128i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI128" form="xmm, ymm, imm8" xed="VEXTRACTI128_XMMdq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_hadd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+ 	<operation>
+ dst[15:0] := a[31:16] + a[15:0]
+ dst[31:16] := a[63:48] + a[47:32]
+ dst[47:32] := a[95:80] + a[79:64]
+ dst[63:48] := a[127:112] + a[111:96]
+ dst[79:64] := b[31:16] + b[15:0]
+ dst[95:80] := b[63:48] + b[47:32]
+ dst[111:96] := b[95:80] + b[79:64]
+ dst[127:112] := b[127:112] + b[111:96]
+ dst[143:128] := a[159:144] + a[143:128]
+ dst[159:144] := a[191:176] + a[175:160]
+ dst[175:160] := a[223:208] + a[207:192]
+ dst[191:176] := a[255:240] + a[239:224]
+ dst[207:192] := b[159:144] + b[143:128]
+ dst[223:208] := b[191:176] + b[175:160]
+ dst[239:224] := b[223:208] + b[207:192]
+ dst[255:240] := b[255:240] + b[239:224]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPHADDW" form="ymm, ymm, ymm" xed="VPHADDW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_hadd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+ 	<operation>
+ dst[31:0] := a[63:32] + a[31:0]
+ dst[63:32] := a[127:96] + a[95:64]
+ dst[95:64] := b[63:32] + b[31:0]
+ dst[127:96] := b[127:96] + b[95:64]
+ dst[159:128] := a[191:160] + a[159:128]
+ dst[191:160] := a[255:224] + a[223:192]
+ dst[223:192] := b[191:160] + b[159:128]
+ dst[255:224] := b[255:224] + b[223:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPHADDD" form="ymm, ymm, ymm" xed="VPHADDD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_hadds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+ 	<operation>
+ dst[15:0] := Saturate16(a[31:16] + a[15:0])
+ dst[31:16] := Saturate16(a[63:48] + a[47:32])
+ dst[47:32] := Saturate16(a[95:80] + a[79:64])
+ dst[63:48] := Saturate16(a[127:112] + a[111:96])
+ dst[79:64] := Saturate16(b[31:16] + b[15:0])
+ dst[95:80] := Saturate16(b[63:48] + b[47:32])
+ dst[111:96] := Saturate16(b[95:80] + b[79:64])
+ dst[127:112] := Saturate16(b[127:112] + b[111:96])
+ dst[143:128] := Saturate16(a[159:144] + a[143:128])
+ dst[159:144] := Saturate16(a[191:176] + a[175:160])
+ dst[175:160] := Saturate16(a[223:208] + a[207:192])
+ dst[191:176] := Saturate16(a[255:240] + a[239:224])
+ dst[207:192] := Saturate16(b[159:144] + b[143:128])
+ dst[223:208] := Saturate16(b[191:176] + b[175:160])
+ dst[239:224] := Saturate16(b[223:208] + b[207:192])
+ dst[255:240] := Saturate16(b[255:240] + b[239:224])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPHADDSW" form="ymm, ymm, ymm" xed="VPHADDSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_hsub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+ 	<operation>
+ dst[15:0] := a[15:0] - a[31:16]
+ dst[31:16] := a[47:32] - a[63:48]
+ dst[47:32] := a[79:64] - a[95:80]
+ dst[63:48] := a[111:96] - a[127:112]
+ dst[79:64] := b[15:0] - b[31:16]
+ dst[95:80] := b[47:32] - b[63:48]
+ dst[111:96] := b[79:64] - b[95:80]
+ dst[127:112] := b[111:96] - b[127:112]
+ dst[143:128] := a[143:128] - a[159:144]
+ dst[159:144] := a[175:160] - a[191:176]
+ dst[175:160] := a[207:192] - a[223:208]
+ dst[191:176] := a[239:224] - a[255:240]
+ dst[207:192] := b[143:128] - b[159:144]
+ dst[223:208] := b[175:160] - b[191:176]
+ dst[239:224] := b[207:192] - b[223:208]
+ dst[255:240] := b[239:224] - b[255:240]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPHSUBW" form="ymm, ymm, ymm" xed="VPHSUBW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_hsub_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+ 	<operation>
+ dst[31:0] := a[31:0] - a[63:32]
+ dst[63:32] := a[95:64] - a[127:96]
+ dst[95:64] := b[31:0] - b[63:32]
+ dst[127:96] := b[95:64] - b[127:96]
+ dst[159:128] := a[159:128] - a[191:160]
+ dst[191:160] := a[223:192] - a[255:224]
+ dst[223:192] := b[159:128] - b[191:160]
+ dst[255:224] := b[223:192] - b[255:224]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPHSUBD" form="ymm, ymm, ymm" xed="VPHSUBD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_hsubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+ 	<operation>
+ dst[15:0] := Saturate16(a[15:0] - a[31:16])
+ dst[31:16] := Saturate16(a[47:32] - a[63:48])
+ dst[47:32] := Saturate16(a[79:64] - a[95:80])
+ dst[63:48] := Saturate16(a[111:96] - a[127:112])
+ dst[79:64] := Saturate16(b[15:0] - b[31:16])
+ dst[95:80] := Saturate16(b[47:32] - b[63:48])
+ dst[111:96] := Saturate16(b[79:64] - b[95:80])
+ dst[127:112] := Saturate16(b[111:96] - b[127:112])
+ dst[143:128] := Saturate16(a[143:128] - a[159:144])
+ dst[159:144] := Saturate16(a[175:160] - a[191:176])
+ dst[175:160] := Saturate16(a[207:192] - a[223:208])
+ dst[191:176] := Saturate16(a[239:224] - a[255:240])
+ dst[207:192] := Saturate16(b[143:128] - b[159:144])
+ dst[223:208] := Saturate16(b[175:160] - b[191:176])
+ dst[239:224] := Saturate16(b[207:192] - b[223:208])
+ dst[255:240] := Saturate16(b[239:224] - b[255:240])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPHSUBSW" form="ymm, ymm, ymm" xed="VPHSUBSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i32gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPD" form="xmm, vm32x, xmm" xed="VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i32gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPD" form="ymm, vm32x, ymm" xed="VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i32gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPS" form="xmm, vm32x, xmm" xed="VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i32gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPS" form="ymm, vm32x, ymm" xed="VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i32gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDD" form="xmm, vm32x, xmm" xed="VPGATHERDD_XMMu32_MEMd_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i32gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDD" form="ymm, vm32x, ymm" xed="VPGATHERDD_YMMu32_MEMd_YMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i32gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDQ" form="xmm, vm32x, xmm" xed="VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i32gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDQ" form="ymm, vm32x, ymm" xed="VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i64gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPD" form="xmm, vm64x, xmm" xed="VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i64gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPD" form="ymm, vm64x, ymm" xed="VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i64gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPS" form="xmm, vm64x, xmm" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i64gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPS" form="xmm, vm64y, xmm" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i64gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQD" form="xmm, vm64x, xmm" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i64gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+31:i] := MEM[addr+31:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQD" form="xmm, vm64y, xmm" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_i64gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQQ" form="xmm, vm64x, xmm" xed="VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_i64gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	dst[i+63:i] := MEM[addr+63:addr]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQQ" form="ymm, vm64x, ymm" xed="VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_inserti128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m128i" varname="b" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI128" form="ymm, ymm, xmm, imm8" xed="VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="ymm, ymm, ymm" xed="VPMADDWD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="ymm, ymm, ymm" xed="VPMADDUBSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i32gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128d" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	IF mask[i+63]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPD" form="xmm, vm32x, xmm" xed="VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i32gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256d" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	IF mask[i+63]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:256] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPD" form="ymm, vm32x, ymm" xed="VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i32gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	IF mask[i+31]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPS" form="xmm, vm32x, xmm" xed="VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i32gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	IF mask[i+31]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:256] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPS" form="ymm, vm32x, ymm" xed="VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i32gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	IF mask[i+31]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDD" form="xmm, vm32x, xmm" xed="VPGATHERDD_XMMu32_MEMd_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i32gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	IF mask[i+31]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:256] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDD" form="ymm, vm32x, ymm" xed="VPGATHERDD_YMMu32_MEMd_YMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i32gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	IF mask[i+63]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDQ" form="xmm, vm32x, xmm" xed="VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i32gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	IF mask[i+63]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:256] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDQ" form="ymm, vm32x, ymm" xed="VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i64gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128d" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	IF mask[i+63]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPD" form="xmm, vm64x, xmm" xed="VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i64gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="double const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m256d" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	IF mask[i+63]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:256] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPD" form="ymm, vm64x, ymm" xed="VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i64gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF mask[i+31]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:64] := 0
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPS" form="xmm, vm64x, xmm" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i64gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="float const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF mask[i+31]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPS" form="xmm, vm64y, xmm" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i64gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF mask[i+31]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:64] := 0
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQD" form="xmm, vm64x, xmm" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i64gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="int const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF mask[i+31]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQD" form="xmm, vm64y, xmm" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_mask_i64gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	IF mask[i+63]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:128] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQQ" form="xmm, vm64x, xmm" xed="VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mask_i64gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	IF mask[i+63]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ mask[MAX:256] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQQ" form="ymm, vm64x, ymm" xed="VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_maskload_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="int const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF mask[i+31]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMASKMOVD" form="xmm, xmm, m128" xed="VPMASKMOVD_XMMdq_XMMdq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_maskload_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="int const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF mask[i+31]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMASKMOVD" form="ymm, ymm, m256" xed="VPMASKMOVD_YMMqq_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_maskload_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF mask[i+63]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMASKMOVQ" form="xmm, xmm, m128" xed="VPMASKMOVQ_XMMdq_XMMdq_MEMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_maskload_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__int64 const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF mask[i+63]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMASKMOVQ" form="ymm, ymm, m256" xed="VPMASKMOVQ_YMMqq_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_maskstore_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="int*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF mask[i+31]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMASKMOVD" form="m128, xmm, xmm" xed="VPMASKMOVD_MEMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_maskstore_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="int*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF mask[i+31]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMASKMOVD" form="m256, ymm, ymm" xed="VPMASKMOVD_MEMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_maskstore_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__int64*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__m128i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF mask[i+63]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMASKMOVQ" form="m128, xmm, xmm" xed="VPMASKMOVQ_MEMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_maskstore_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__int64*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__m256i" varname="mask" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF mask[i+63]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMASKMOVQ" form="m256, ymm, ymm" xed="VPMASKMOVQ_MEMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="ymm, ymm, ymm" xed="VPMAXSB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="ymm, ymm, ymm" xed="VPMAXSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_max_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSD" form="ymm, ymm, ymm" xed="VPMAXSD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="ymm, ymm, ymm" xed="VPMAXUB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="ymm, ymm, ymm" xed="VPMAXUW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_max_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUD" form="ymm, ymm, ymm" xed="VPMAXUD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="ymm, ymm, ymm" xed="VPMINSB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="ymm, ymm, ymm" xed="VPMINSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_min_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSD" form="ymm, ymm, ymm" xed="VPMINSD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="ymm, ymm, ymm" xed="VPMINUB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="ymm, ymm, ymm" xed="VPMINUW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_min_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Special Math Functions</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUD" form="ymm, ymm, ymm" xed="VPMINUD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_movemask_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="int" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[j] := a[i+7]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVMSKB" form="r32, ymm" xed="VPMOVMSKB_GPR32d_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mpsadbw_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+ 	Eight SADs are performed for each 128-bit lane using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".</description>
+ 	<operation>
+ DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
+ 	a_offset := imm8[2]*32
+ 	b_offset := imm8[1:0]*32
+ 	FOR j := 0 to 7
+ 		i := j*8
+ 		k := a_offset+i
+ 		l := b_offset
+ 		tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \
+ 		                   ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24]))
+ 	ENDFOR
+ 	RETURN tmp[127:0]
+ }
+ dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])
+ dst[255:128] := MPSADBW(a[255:128], b[255:128], imm8[5:3])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMPSADBW" form="ymm, ymm, ymm, imm8" xed="VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mul_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULDQ" form="ymm, ymm, ymm" xed="VPMULDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mul_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULUDQ" form="ymm, ymm, ymm" xed="VPMULUDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 	dst[i+15:i] := tmp[31:16]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="ymm, ymm, ymm" xed="VPMULHW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 	dst[i+15:i] := tmp[31:16]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="ymm, ymm, ymm" xed="VPMULHUW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 	dst[i+15:i] := tmp[16:1]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="ymm, ymm, ymm" xed="VPMULHRSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 	dst[i+15:i] := tmp[15:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="ymm, ymm, ymm" xed="VPMULLW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_mullo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Multiply the packed signed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	tmp[63:0] := a[i+31:i] * b[i+31:i]
+ 	dst[i+31:i] := tmp[31:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLD" form="ymm, ymm, ymm" xed="VPMULLD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_or_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+ 	<operation>
+ dst[255:0] := (a[255:0] OR b[255:0])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPOR" form="ymm, ymm, ymm" xed="VPOR_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[7:0] := Saturate8(a[15:0])
+ dst[15:8] := Saturate8(a[31:16])
+ dst[23:16] := Saturate8(a[47:32])
+ dst[31:24] := Saturate8(a[63:48])
+ dst[39:32] := Saturate8(a[79:64])
+ dst[47:40] := Saturate8(a[95:80])
+ dst[55:48] := Saturate8(a[111:96])
+ dst[63:56] := Saturate8(a[127:112])
+ dst[71:64] := Saturate8(b[15:0])
+ dst[79:72] := Saturate8(b[31:16])
+ dst[87:80] := Saturate8(b[47:32])
+ dst[95:88] := Saturate8(b[63:48])
+ dst[103:96] := Saturate8(b[79:64])
+ dst[111:104] := Saturate8(b[95:80])
+ dst[119:112] := Saturate8(b[111:96])
+ dst[127:120] := Saturate8(b[127:112])
+ dst[135:128] := Saturate8(a[143:128])
+ dst[143:136] := Saturate8(a[159:144])
+ dst[151:144] := Saturate8(a[175:160])
+ dst[159:152] := Saturate8(a[191:176])
+ dst[167:160] := Saturate8(a[207:192])
+ dst[175:168] := Saturate8(a[223:208])
+ dst[183:176] := Saturate8(a[239:224])
+ dst[191:184] := Saturate8(a[255:240])
+ dst[199:192] := Saturate8(b[143:128])
+ dst[207:200] := Saturate8(b[159:144])
+ dst[215:208] := Saturate8(b[175:160])
+ dst[223:216] := Saturate8(b[191:176])
+ dst[231:224] := Saturate8(b[207:192])
+ dst[239:232] := Saturate8(b[223:208])
+ dst[247:240] := Saturate8(b[239:224])
+ dst[255:248] := Saturate8(b[255:240])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="ymm, ymm, ymm" xed="VPACKSSWB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[15:0] := Saturate16(a[31:0])
+ dst[31:16] := Saturate16(a[63:32])
+ dst[47:32] := Saturate16(a[95:64])
+ dst[63:48] := Saturate16(a[127:96])
+ dst[79:64] := Saturate16(b[31:0])
+ dst[95:80] := Saturate16(b[63:32])
+ dst[111:96] := Saturate16(b[95:64])
+ dst[127:112] := Saturate16(b[127:96])
+ dst[143:128] := Saturate16(a[159:128])
+ dst[159:144] := Saturate16(a[191:160])
+ dst[175:160] := Saturate16(a[223:192])
+ dst[191:176] := Saturate16(a[255:224])
+ dst[207:192] := Saturate16(b[159:128])
+ dst[223:208] := Saturate16(b[191:160])
+ dst[239:224] := Saturate16(b[223:192])
+ dst[255:240] := Saturate16(b[255:224])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="ymm, ymm, ymm" xed="VPACKSSDW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[7:0] := SaturateU8(a[15:0])
+ dst[15:8] := SaturateU8(a[31:16])
+ dst[23:16] := SaturateU8(a[47:32])
+ dst[31:24] := SaturateU8(a[63:48])
+ dst[39:32] := SaturateU8(a[79:64])
+ dst[47:40] := SaturateU8(a[95:80])
+ dst[55:48] := SaturateU8(a[111:96])
+ dst[63:56] := SaturateU8(a[127:112])
+ dst[71:64] := SaturateU8(b[15:0])
+ dst[79:72] := SaturateU8(b[31:16])
+ dst[87:80] := SaturateU8(b[47:32])
+ dst[95:88] := SaturateU8(b[63:48])
+ dst[103:96] := SaturateU8(b[79:64])
+ dst[111:104] := SaturateU8(b[95:80])
+ dst[119:112] := SaturateU8(b[111:96])
+ dst[127:120] := SaturateU8(b[127:112])
+ dst[135:128] := SaturateU8(a[143:128])
+ dst[143:136] := SaturateU8(a[159:144])
+ dst[151:144] := SaturateU8(a[175:160])
+ dst[159:152] := SaturateU8(a[191:176])
+ dst[167:160] := SaturateU8(a[207:192])
+ dst[175:168] := SaturateU8(a[223:208])
+ dst[183:176] := SaturateU8(a[239:224])
+ dst[191:184] := SaturateU8(a[255:240])
+ dst[199:192] := SaturateU8(b[143:128])
+ dst[207:200] := SaturateU8(b[159:144])
+ dst[215:208] := SaturateU8(b[175:160])
+ dst[223:216] := SaturateU8(b[191:176])
+ dst[231:224] := SaturateU8(b[207:192])
+ dst[239:232] := SaturateU8(b[223:208])
+ dst[247:240] := SaturateU8(b[239:224])
+ dst[255:248] := SaturateU8(b[255:240])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="ymm, ymm, ymm" xed="VPACKUSWB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[15:0] := SaturateU16(a[31:0])
+ dst[31:16] := SaturateU16(a[63:32])
+ dst[47:32] := SaturateU16(a[95:64])
+ dst[63:48] := SaturateU16(a[127:96])
+ dst[79:64] := SaturateU16(b[31:0])
+ dst[95:80] := SaturateU16(b[63:32])
+ dst[111:96] := SaturateU16(b[95:64])
+ dst[127:112] := SaturateU16(b[127:96])
+ dst[143:128] := SaturateU16(a[159:128])
+ dst[159:144] := SaturateU16(a[191:160])
+ dst[175:160] := SaturateU16(a[223:192])
+ dst[191:176] := SaturateU16(a[255:224])
+ dst[207:192] := SaturateU16(b[159:128])
+ dst[223:208] := SaturateU16(b[191:160])
+ dst[239:224] := SaturateU16(b[223:192])
+ dst[255:240] := SaturateU16(b[255:224])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="ymm, ymm, ymm" xed="VPACKUSDW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_permute2x128_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src1, src2, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[127:0] := src1[127:0]
+ 	1:	tmp[127:0] := src1[255:128]
+ 	2:	tmp[127:0] := src2[127:0]
+ 	3:	tmp[127:0] := src2[255:128]
+ 	ESAC
+ 	IF control[3]
+ 		tmp[127:0] := 0
+ 	FI
+ 	RETURN tmp[127:0]
+ }
+ dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+ dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERM2I128" form="ymm, ymm, ymm, imm8" xed="VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_permute4x64_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm, ymm, imm8" xed="VPERMQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_permute4x64_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm, ymm, imm8" xed="VPERMPD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_permutevar8x32_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	dst[i+31:i] := a[id+31:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMD" form="ymm, ymm, ymm" xed="VPERMD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_permutevar8x32_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	dst[i+31:i] := a[id+31:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPS" form="ymm, ymm, ymm" xed="VPERMPS_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ ENDFOR
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
+ 	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
+ 	dst[i+63:i+16] := 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSADBW" form="ymm, ymm, ymm" xed="VPSADBW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_shuffle_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+ dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFD" form="ymm, ymm, imm8" xed="VPSHUFD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF b[i+7] == 1
+ 		dst[i+7:i] := 0
+ 	ELSE
+ 		index[3:0] := b[i+3:i]
+ 		dst[i+7:i] := a[index*8+7:index*8]
+ 	FI
+ 	IF b[128+i+7] == 1
+ 		dst[128+i+7:128+i] := 0
+ 	ELSE
+ 		index[3:0] := b[128+i+3:128+i]
+ 		dst[128+i+7:128+i] := a[128+index*8+7:128+index*8]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="ymm, ymm, ymm" xed="VPSHUFB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+ 	<operation>
+ dst[63:0] := a[63:0]
+ dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ dst[191:128] := a[191:128]
+ dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+ dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+ dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+ dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="ymm, ymm, imm8" xed="VPSHUFHW_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+ 	<operation>
+ dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ dst[127:64] := a[127:64]
+ dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+ dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+ dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+ dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+ dst[255:192] := a[255:192]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="ymm, ymm, imm8" xed="VPSHUFLW_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sign_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Negate packed signed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF b[i+7:i] &lt; 0
+ 		dst[i+7:i] := -(a[i+7:i])
+ 	ELSE IF b[i+7:i] == 0
+ 		dst[i+7:i] := 0
+ 	ELSE
+ 		dst[i+7:i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSIGNB" form="ymm, ymm, ymm" xed="VPSIGNB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sign_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Negate packed signed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF b[i+15:i] &lt; 0
+ 		dst[i+15:i] := -(a[i+15:i])
+ 	ELSE IF b[i+15:i] == 0
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSIGNW" form="ymm, ymm, ymm" xed="VPSIGNW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sign_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Negate packed signed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF b[i+31:i] &lt; 0
+ 		dst[i+31:i] := -(a[i+31:i])
+ 	ELSE IF b[i+31:i] == 0
+ 		dst[i+31:i] := 0
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSIGND" form="ymm, ymm, ymm" xed="VPSIGND_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_slli_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ tmp := imm8[7:0]
+ IF tmp &gt; 15
+ 	tmp := 16
+ FI
+ dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+ dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLDQ" form="ymm, ymm, imm8" xed="VPSLLDQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_bslli_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ tmp := imm8[7:0]
+ IF tmp &gt; 15
+ 	tmp := 16
+ FI
+ dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+ dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLDQ" form="ymm, ymm, imm8" xed="VPSLLDQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF count[63:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="ymm, ymm, xmm" xed="VPSLLW_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF imm8[7:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="ymm, ymm, imm8" xed="VPSLLW_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sll_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF count[63:0] &gt; 31
+ 		dst[i+31:i] := 0
+ 	ELSE
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="ymm, ymm, xmm" xed="VPSLLD_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_slli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF imm8[7:0] &gt; 31
+ 		dst[i+31:i] := 0
+ 	ELSE
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="ymm, ymm, imm8" xed="VPSLLD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sll_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF count[63:0] &gt; 63
+ 		dst[i+63:i] := 0
+ 	ELSE
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="ymm, ymm, xmm" xed="VPSLLQ_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_slli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF imm8[7:0] &gt; 63
+ 		dst[i+63:i] := 0
+ 	ELSE
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="ymm, ymm, imm8" xed="VPSLLQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_sllv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF count[i+31:i] &lt; 32
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVD" form="xmm, xmm, xmm" xed="VPSLLVD_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sllv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF count[i+31:i] &lt; 32
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVD" form="ymm, ymm, ymm" xed="VPSLLVD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_sllv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF count[i+63:i] &lt; 64
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVQ" form="xmm, xmm, xmm" xed="VPSLLVQ_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sllv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF count[i+63:i] &lt; 64
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVQ" form="ymm, ymm, ymm" xed="VPSLLVQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF count[63:0] &gt; 15
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 	ELSE
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="ymm, ymm, xmm" xed="VPSRAW_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF imm8[7:0] &gt; 15
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 	ELSE
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="ymm, ymm, imm8" xed="VPSRAW_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sra_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF count[63:0] &gt; 31
+ 		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 	ELSE
+ 		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="ymm, ymm, xmm" xed="VPSRAD_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srai_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF imm8[7:0] &gt; 31
+ 		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 	ELSE
+ 		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="ymm, ymm, imm8" xed="VPSRAD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_srav_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF count[i+31:i] &lt; 32
+ 		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVD" form="xmm, xmm, xmm" xed="VPSRAVD_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srav_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF count[i+31:i] &lt; 32
+ 		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVD" form="ymm, ymm, ymm" xed="VPSRAVD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srli_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ tmp := imm8[7:0]
+ IF tmp &gt; 15
+ 	tmp := 16
+ FI
+ dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+ dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLDQ" form="ymm, ymm, imm8" xed="VPSRLDQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_bsrli_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="M128"/>
+ 	<parameter type="__m256i" varname="a" etype="M128"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ tmp := imm8[7:0]
+ IF tmp &gt; 15
+ 	tmp := 16
+ FI
+ dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+ dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLDQ" form="ymm, ymm, imm8" xed="VPSRLDQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF count[63:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="ymm, ymm, xmm" xed="VPSRLW_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF imm8[7:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="ymm, ymm, imm8" xed="VPSRLW_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srl_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF count[63:0] &gt; 31
+ 		dst[i+31:i] := 0
+ 	ELSE
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="ymm, ymm, xmm" xed="VPSRLD_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF imm8[7:0] &gt; 31
+ 		dst[i+31:i] := 0
+ 	ELSE
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="ymm, ymm, imm8" xed="VPSRLD_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srl_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF count[63:0] &gt; 63
+ 		dst[i+63:i] := 0
+ 	ELSE
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="ymm, ymm, xmm" xed="VPSRLQ_YMMqq_YMMqq_XMMq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF imm8[7:0] &gt; 63
+ 		dst[i+63:i] := 0
+ 	ELSE
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="ymm, ymm, imm8" xed="VPSRLQ_YMMqq_YMMqq_IMMb"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_srlv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF count[i+31:i] &lt; 32
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVD" form="xmm, xmm, xmm" xed="VPSRLVD_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srlv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF count[i+31:i] &lt; 32
+ 		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVD" form="ymm, ymm, ymm" xed="VPSRLVD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm_srlv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF count[i+63:i] &lt; 64
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVQ" form="xmm, xmm, xmm" xed="VPSRLVQ_XMMdq_XMMdq_XMMdq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_srlv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF count[i+63:i] &lt; 64
+ 		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVQ" form="ymm, ymm, ymm" xed="VPSRLVQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_stream_load_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i const*" varname="mem_addr" etype="M256" memwidth="256"/>
+ 	<description>Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint.
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVNTDQA" form="ymm, m256" xed="VMOVNTDQA_YMMqq_MEMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="ymm, ymm, ymm" xed="VPSUBB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="ymm, ymm, ymm" xed="VPSUBW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sub_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBD" form="ymm, ymm, ymm" xed="VPSUBD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_sub_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBQ" form="ymm, ymm, ymm" xed="VPSUBQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="ymm, ymm, ymm" xed="VPSUBSB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="ymm, ymm, ymm" xed="VPSUBSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="ymm, ymm, ymm" xed="VPSUBUSB_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="ymm, ymm, ymm" xed="VPSUBUSW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_xor_si256">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="M256"/>
+ 	<parameter type="__m256i" varname="a" etype="M256"/>
+ 	<parameter type="__m256i" varname="b" etype="M256"/>
+ 	<description>Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+ 	<operation>
+ dst[255:0] := (a[255:0] XOR b[255:0])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXOR" form="ymm, ymm, ymm" xed="VPXOR_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="ymm, ymm, ymm" xed="VPUNPCKHBW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="ymm, ymm, ymm" xed="VPUNPCKHWD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpackhi_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHDQ" form="ymm, ymm, ymm" xed="VPUNPCKHDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpackhi_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHQDQ" form="ymm, ymm, ymm" xed="VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="ymm, ymm, ymm" xed="VPUNPCKLBW_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="ymm, ymm, ymm" xed="VPUNPCKLWD_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpacklo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]	
+ }
+ dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLDQ" form="ymm, ymm, ymm" xed="VPUNPCKLDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX2" name="_mm256_unpacklo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX2</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLQDQ" form="ymm, ymm, ymm" xed="VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_kunpackd">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask64" varname="dst" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Unpack and interleave 32 bits from masks "a" and "b", and store the 64-bit result in "dst".</description>
+ 	<operation>
+ dst[31:0] := b[31:0]
+ dst[63:32] := a[31:0]
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KUNPCKDQ" form="k, k, k" xed="KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_kunpackw">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask32" varname="dst" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Unpack and interleave 16 bits from masks "a" and "b", and store the 32-bit result in "dst".</description>
+ 	<operation>
+ dst[15:0] := b[15:0]
+ dst[31:16] := a[15:0]
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KUNPCKWD" form="k, k, k" xed="KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ FOR i := 0 to 1
+ 	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+ 	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+ 	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+ 	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ ENDFOR
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="ymm, ymm, ymm, imm8" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ FOR i := 0 to 1
+ 	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+ 	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+ 	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+ 	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ ENDFOR
+ FOR j := 0 to 3
+ 	i := j*64
+ 	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="ymm {k}, ymm, ymm, imm8" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ FOR i := 0 to 1
+ 	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+ 	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+ 	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+ 	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ ENDFOR
+ FOR j := 0 to 3
+ 	i := j*64
+ 	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="ymm {z}, ymm, ymm, imm8" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ FOR i := 0 to 3
+ 	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+ 	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+ 	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+ 	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ ENDFOR
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="zmm, zmm, zmm, imm8" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ FOR i := 0 to 3
+ 	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+ 	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+ 	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+ 	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ ENDFOR
+ FOR j := 0 to 7
+ 	i := j*64
+ 	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="zmm {k}, zmm, zmm, imm8" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ FOR i := 0 to 3
+ 	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+ 	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+ 	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+ 	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ ENDFOR
+ FOR j := 0 to 7
+ 	i := j*64
+ 	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="zmm {z}, zmm, zmm, imm8" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ tmp.dword[0] := b.dword[ imm8[1:0] ]
+ tmp.dword[1] := b.dword[ imm8[3:2] ]
+ tmp.dword[2] := b.dword[ imm8[5:4] ]
+ tmp.dword[3] := b.dword[ imm8[7:6] ]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="xmm, xmm, xmm, imm8" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ tmp.dword[0] := b.dword[ imm8[1:0] ]
+ tmp.dword[1] := b.dword[ imm8[3:2] ]
+ tmp.dword[2] := b.dword[ imm8[5:4] ]
+ tmp.dword[3] := b.dword[ imm8[7:6] ]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="xmm {k}, xmm, xmm, imm8" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_dbsad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+ 	<operation>
+ tmp.dword[0] := b.dword[ imm8[1:0] ]
+ tmp.dword[1] := b.dword[ imm8[3:2] ]
+ tmp.dword[2] := b.dword[ imm8[5:4] ]
+ tmp.dword[3] := b.dword[ imm8[7:6] ]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+ 	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+ 	
+ 	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+ 	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+ 	
+ 	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+ 	
+ 	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+ 	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ ENDFOR
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDBPSADBW" form="xmm {z}, xmm, xmm, imm8" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="256"/>
+ 	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="ymm {k}, m256" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mov_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="ymm {k}, ymm" xed="VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI16" memwidth="256"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="m256 {k}, ymm" xed="VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="256"/>
+ 	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="ymm {z}, m256" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mov_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="ymm {z}, ymm" xed="VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="512"/>
+ 	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="zmm {k}, m512" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mov_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="zmm {k}, zmm" xed="VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI16" memwidth="512"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="m512 {k}, zmm" xed="VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="512"/>
+ 	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="zmm {z}, m512" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mov_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="zmm {z}, zmm" xed="VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="128"/>
+ 	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="xmm {k}, m128" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mov_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="xmm {k}, xmm" xed="VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI16" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="m128 {k}, xmm" xed="VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="128"/>
+ 	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="xmm {z}, m128" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mov_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="xmm {z}, xmm" xed="VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="256"/>
+ 	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="ymm {k}, m256" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mov_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="ymm {k}, ymm" xed="VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI8" memwidth="256"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="m256 {k}, ymm" xed="VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="256"/>
+ 	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="ymm {z}, m256" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mov_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="ymm {z}, ymm" xed="VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="512"/>
+ 	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="zmm {k}, m512" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mov_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="zmm {k}, zmm" xed="VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI8" memwidth="512"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="m512 {k}, zmm" xed="VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="512"/>
+ 	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="zmm {z}, m512" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mov_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="zmm {z}, zmm" xed="VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="128"/>
+ 	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="xmm {k}, m128" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mov_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="xmm {k}, xmm" xed="VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI8" memwidth="128"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="m128 {k}, xmm" xed="VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="128"/>
+ 	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="xmm {z}, m128" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mov_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="xmm {z}, xmm" xed="VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := ABS(a[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="ymm {k}, ymm" xed="VPABSB_YMMi8_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := ABS(a[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="ymm {z}, ymm" xed="VPABSB_YMMi8_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := ABS(a[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="zmm, zmm" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := ABS(a[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="zmm {k}, zmm" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := ABS(a[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="zmm {z}, zmm" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := ABS(a[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="xmm {k}, xmm" xed="VPABSB_XMMi8_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_abs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := ABS(a[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSB" form="xmm {z}, xmm" xed="VPABSB_XMMi8_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := ABS(a[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="ymm {k}, ymm" xed="VPABSW_YMMi16_MASKmskw_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := ABS(a[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="ymm {z}, ymm" xed="VPABSW_YMMi16_MASKmskw_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := ABS(a[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="zmm, zmm" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := ABS(a[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="zmm {k}, zmm" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := ABS(a[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="zmm {z}, zmm" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := ABS(a[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="xmm {k}, xmm" xed="VPABSW_XMMi16_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_abs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := ABS(a[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSW" form="xmm {z}, xmm" xed="VPABSW_XMMi16_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := Saturate16(a[31:0])
+ tmp_dst[31:16] := Saturate16(a[63:32])
+ tmp_dst[47:32] := Saturate16(a[95:64])
+ tmp_dst[63:48] := Saturate16(a[127:96])
+ tmp_dst[79:64] := Saturate16(b[31:0])
+ tmp_dst[95:80] := Saturate16(b[63:32])
+ tmp_dst[111:96] := Saturate16(b[95:64])
+ tmp_dst[127:112] := Saturate16(b[127:96])
+ tmp_dst[143:128] := Saturate16(a[159:128])
+ tmp_dst[159:144] := Saturate16(a[191:160])
+ tmp_dst[175:160] := Saturate16(a[223:192])
+ tmp_dst[191:176] := Saturate16(a[255:224])
+ tmp_dst[207:192] := Saturate16(b[159:128])
+ tmp_dst[223:208] := Saturate16(b[191:160])
+ tmp_dst[239:224] := Saturate16(b[223:192])
+ tmp_dst[255:240] := Saturate16(b[255:224])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="ymm {k}, ymm, ymm" xed="VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := Saturate16(a[31:0])
+ tmp_dst[31:16] := Saturate16(a[63:32])
+ tmp_dst[47:32] := Saturate16(a[95:64])
+ tmp_dst[63:48] := Saturate16(a[127:96])
+ tmp_dst[79:64] := Saturate16(b[31:0])
+ tmp_dst[95:80] := Saturate16(b[63:32])
+ tmp_dst[111:96] := Saturate16(b[95:64])
+ tmp_dst[127:112] := Saturate16(b[127:96])
+ tmp_dst[143:128] := Saturate16(a[159:128])
+ tmp_dst[159:144] := Saturate16(a[191:160])
+ tmp_dst[175:160] := Saturate16(a[223:192])
+ tmp_dst[191:176] := Saturate16(a[255:224])
+ tmp_dst[207:192] := Saturate16(b[159:128])
+ tmp_dst[223:208] := Saturate16(b[191:160])
+ tmp_dst[239:224] := Saturate16(b[223:192])
+ tmp_dst[255:240] := Saturate16(b[255:224])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="ymm {z}, ymm, ymm" xed="VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m512i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI32"/>
+ 	<parameter type="__m512i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := Saturate16(a[31:0])
+ tmp_dst[31:16] := Saturate16(a[63:32])
+ tmp_dst[47:32] := Saturate16(a[95:64])
+ tmp_dst[63:48] := Saturate16(a[127:96])
+ tmp_dst[79:64] := Saturate16(b[31:0])
+ tmp_dst[95:80] := Saturate16(b[63:32])
+ tmp_dst[111:96] := Saturate16(b[95:64])
+ tmp_dst[127:112] := Saturate16(b[127:96])
+ tmp_dst[143:128] := Saturate16(a[159:128])
+ tmp_dst[159:144] := Saturate16(a[191:160])
+ tmp_dst[175:160] := Saturate16(a[223:192])
+ tmp_dst[191:176] := Saturate16(a[255:224])
+ tmp_dst[207:192] := Saturate16(b[159:128])
+ tmp_dst[223:208] := Saturate16(b[191:160])
+ tmp_dst[239:224] := Saturate16(b[223:192])
+ tmp_dst[255:240] := Saturate16(b[255:224])
+ tmp_dst[271:256] := Saturate16(a[287:256])
+ tmp_dst[287:272] := Saturate16(a[319:288])
+ tmp_dst[303:288] := Saturate16(a[351:320])
+ tmp_dst[319:304] := Saturate16(a[383:352])
+ tmp_dst[335:320] := Saturate16(b[287:256])
+ tmp_dst[351:336] := Saturate16(b[319:288])
+ tmp_dst[367:352] := Saturate16(b[351:320])
+ tmp_dst[383:368] := Saturate16(b[383:352])
+ tmp_dst[399:384] := Saturate16(a[415:384])
+ tmp_dst[415:400] := Saturate16(a[447:416])
+ tmp_dst[431:416] := Saturate16(a[479:448])
+ tmp_dst[447:432] := Saturate16(a[511:480])
+ tmp_dst[463:448] := Saturate16(b[415:384])
+ tmp_dst[479:464] := Saturate16(b[447:416])
+ tmp_dst[495:480] := Saturate16(b[479:448])
+ tmp_dst[511:496] := Saturate16(b[511:480])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="zmm {k}, zmm, zmm" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI32"/>
+ 	<parameter type="__m512i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := Saturate16(a[31:0])
+ tmp_dst[31:16] := Saturate16(a[63:32])
+ tmp_dst[47:32] := Saturate16(a[95:64])
+ tmp_dst[63:48] := Saturate16(a[127:96])
+ tmp_dst[79:64] := Saturate16(b[31:0])
+ tmp_dst[95:80] := Saturate16(b[63:32])
+ tmp_dst[111:96] := Saturate16(b[95:64])
+ tmp_dst[127:112] := Saturate16(b[127:96])
+ tmp_dst[143:128] := Saturate16(a[159:128])
+ tmp_dst[159:144] := Saturate16(a[191:160])
+ tmp_dst[175:160] := Saturate16(a[223:192])
+ tmp_dst[191:176] := Saturate16(a[255:224])
+ tmp_dst[207:192] := Saturate16(b[159:128])
+ tmp_dst[223:208] := Saturate16(b[191:160])
+ tmp_dst[239:224] := Saturate16(b[223:192])
+ tmp_dst[255:240] := Saturate16(b[255:224])
+ tmp_dst[271:256] := Saturate16(a[287:256])
+ tmp_dst[287:272] := Saturate16(a[319:288])
+ tmp_dst[303:288] := Saturate16(a[351:320])
+ tmp_dst[319:304] := Saturate16(a[383:352])
+ tmp_dst[335:320] := Saturate16(b[287:256])
+ tmp_dst[351:336] := Saturate16(b[319:288])
+ tmp_dst[367:352] := Saturate16(b[351:320])
+ tmp_dst[383:368] := Saturate16(b[383:352])
+ tmp_dst[399:384] := Saturate16(a[415:384])
+ tmp_dst[415:400] := Saturate16(a[447:416])
+ tmp_dst[431:416] := Saturate16(a[479:448])
+ tmp_dst[447:432] := Saturate16(a[511:480])
+ tmp_dst[463:448] := Saturate16(b[415:384])
+ tmp_dst[479:464] := Saturate16(b[447:416])
+ tmp_dst[495:480] := Saturate16(b[479:448])
+ tmp_dst[511:496] := Saturate16(b[511:480])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="zmm {z}, zmm, zmm" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI32"/>
+ 	<parameter type="__m512i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[15:0] := Saturate16(a[31:0])
+ dst[31:16] := Saturate16(a[63:32])
+ dst[47:32] := Saturate16(a[95:64])
+ dst[63:48] := Saturate16(a[127:96])
+ dst[79:64] := Saturate16(b[31:0])
+ dst[95:80] := Saturate16(b[63:32])
+ dst[111:96] := Saturate16(b[95:64])
+ dst[127:112] := Saturate16(b[127:96])
+ dst[143:128] := Saturate16(a[159:128])
+ dst[159:144] := Saturate16(a[191:160])
+ dst[175:160] := Saturate16(a[223:192])
+ dst[191:176] := Saturate16(a[255:224])
+ dst[207:192] := Saturate16(b[159:128])
+ dst[223:208] := Saturate16(b[191:160])
+ dst[239:224] := Saturate16(b[223:192])
+ dst[255:240] := Saturate16(b[255:224])
+ dst[271:256] := Saturate16(a[287:256])
+ dst[287:272] := Saturate16(a[319:288])
+ dst[303:288] := Saturate16(a[351:320])
+ dst[319:304] := Saturate16(a[383:352])
+ dst[335:320] := Saturate16(b[287:256])
+ dst[351:336] := Saturate16(b[319:288])
+ dst[367:352] := Saturate16(b[351:320])
+ dst[383:368] := Saturate16(b[383:352])
+ dst[399:384] := Saturate16(a[415:384])
+ dst[415:400] := Saturate16(a[447:416])
+ dst[431:416] := Saturate16(a[479:448])
+ dst[447:432] := Saturate16(a[511:480])
+ dst[463:448] := Saturate16(b[415:384])
+ dst[479:464] := Saturate16(b[447:416])
+ dst[495:480] := Saturate16(b[479:448])
+ dst[511:496] := Saturate16(b[511:480])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="zmm, zmm, zmm" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := Saturate16(a[31:0])
+ tmp_dst[31:16] := Saturate16(a[63:32])
+ tmp_dst[47:32] := Saturate16(a[95:64])
+ tmp_dst[63:48] := Saturate16(a[127:96])
+ tmp_dst[79:64] := Saturate16(b[31:0])
+ tmp_dst[95:80] := Saturate16(b[63:32])
+ tmp_dst[111:96] := Saturate16(b[95:64])
+ tmp_dst[127:112] := Saturate16(b[127:96])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="xmm {k}, xmm, xmm" xed="VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_packs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := Saturate16(a[31:0])
+ tmp_dst[31:16] := Saturate16(a[63:32])
+ tmp_dst[47:32] := Saturate16(a[95:64])
+ tmp_dst[63:48] := Saturate16(a[127:96])
+ tmp_dst[79:64] := Saturate16(b[31:0])
+ tmp_dst[95:80] := Saturate16(b[63:32])
+ tmp_dst[111:96] := Saturate16(b[95:64])
+ tmp_dst[127:112] := Saturate16(b[127:96])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSDW" form="xmm {z}, xmm, xmm" xed="VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m256i" varname="src" etype="SI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := Saturate8(a[15:0])
+ tmp_dst[15:8] := Saturate8(a[31:16])
+ tmp_dst[23:16] := Saturate8(a[47:32])
+ tmp_dst[31:24] := Saturate8(a[63:48])
+ tmp_dst[39:32] := Saturate8(a[79:64])
+ tmp_dst[47:40] := Saturate8(a[95:80])
+ tmp_dst[55:48] := Saturate8(a[111:96])
+ tmp_dst[63:56] := Saturate8(a[127:112])
+ tmp_dst[71:64] := Saturate8(b[15:0])
+ tmp_dst[79:72] := Saturate8(b[31:16])
+ tmp_dst[87:80] := Saturate8(b[47:32])
+ tmp_dst[95:88] := Saturate8(b[63:48])
+ tmp_dst[103:96] := Saturate8(b[79:64])
+ tmp_dst[111:104] := Saturate8(b[95:80])
+ tmp_dst[119:112] := Saturate8(b[111:96])
+ tmp_dst[127:120] := Saturate8(b[127:112])
+ tmp_dst[135:128] := Saturate8(a[143:128])
+ tmp_dst[143:136] := Saturate8(a[159:144])
+ tmp_dst[151:144] := Saturate8(a[175:160])
+ tmp_dst[159:152] := Saturate8(a[191:176])
+ tmp_dst[167:160] := Saturate8(a[207:192])
+ tmp_dst[175:168] := Saturate8(a[223:208])
+ tmp_dst[183:176] := Saturate8(a[239:224])
+ tmp_dst[191:184] := Saturate8(a[255:240])
+ tmp_dst[199:192] := Saturate8(b[143:128])
+ tmp_dst[207:200] := Saturate8(b[159:144])
+ tmp_dst[215:208] := Saturate8(b[175:160])
+ tmp_dst[223:216] := Saturate8(b[191:176])
+ tmp_dst[231:224] := Saturate8(b[207:192])
+ tmp_dst[239:232] := Saturate8(b[223:208])
+ tmp_dst[247:240] := Saturate8(b[239:224])
+ tmp_dst[255:248] := Saturate8(b[255:240])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="ymm {k}, ymm, ymm" xed="VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := Saturate8(a[15:0])
+ tmp_dst[15:8] := Saturate8(a[31:16])
+ tmp_dst[23:16] := Saturate8(a[47:32])
+ tmp_dst[31:24] := Saturate8(a[63:48])
+ tmp_dst[39:32] := Saturate8(a[79:64])
+ tmp_dst[47:40] := Saturate8(a[95:80])
+ tmp_dst[55:48] := Saturate8(a[111:96])
+ tmp_dst[63:56] := Saturate8(a[127:112])
+ tmp_dst[71:64] := Saturate8(b[15:0])
+ tmp_dst[79:72] := Saturate8(b[31:16])
+ tmp_dst[87:80] := Saturate8(b[47:32])
+ tmp_dst[95:88] := Saturate8(b[63:48])
+ tmp_dst[103:96] := Saturate8(b[79:64])
+ tmp_dst[111:104] := Saturate8(b[95:80])
+ tmp_dst[119:112] := Saturate8(b[111:96])
+ tmp_dst[127:120] := Saturate8(b[127:112])
+ tmp_dst[135:128] := Saturate8(a[143:128])
+ tmp_dst[143:136] := Saturate8(a[159:144])
+ tmp_dst[151:144] := Saturate8(a[175:160])
+ tmp_dst[159:152] := Saturate8(a[191:176])
+ tmp_dst[167:160] := Saturate8(a[207:192])
+ tmp_dst[175:168] := Saturate8(a[223:208])
+ tmp_dst[183:176] := Saturate8(a[239:224])
+ tmp_dst[191:184] := Saturate8(a[255:240])
+ tmp_dst[199:192] := Saturate8(b[143:128])
+ tmp_dst[207:200] := Saturate8(b[159:144])
+ tmp_dst[215:208] := Saturate8(b[175:160])
+ tmp_dst[223:216] := Saturate8(b[191:176])
+ tmp_dst[231:224] := Saturate8(b[207:192])
+ tmp_dst[239:232] := Saturate8(b[223:208])
+ tmp_dst[247:240] := Saturate8(b[239:224])
+ tmp_dst[255:248] := Saturate8(b[255:240])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="ymm {z}, ymm, ymm" xed="VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m512i" varname="src" etype="SI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := Saturate8(a[15:0])
+ tmp_dst[15:8] := Saturate8(a[31:16])
+ tmp_dst[23:16] := Saturate8(a[47:32])
+ tmp_dst[31:24] := Saturate8(a[63:48])
+ tmp_dst[39:32] := Saturate8(a[79:64])
+ tmp_dst[47:40] := Saturate8(a[95:80])
+ tmp_dst[55:48] := Saturate8(a[111:96])
+ tmp_dst[63:56] := Saturate8(a[127:112])
+ tmp_dst[71:64] := Saturate8(b[15:0])
+ tmp_dst[79:72] := Saturate8(b[31:16])
+ tmp_dst[87:80] := Saturate8(b[47:32])
+ tmp_dst[95:88] := Saturate8(b[63:48])
+ tmp_dst[103:96] := Saturate8(b[79:64])
+ tmp_dst[111:104] := Saturate8(b[95:80])
+ tmp_dst[119:112] := Saturate8(b[111:96])
+ tmp_dst[127:120] := Saturate8(b[127:112])
+ tmp_dst[135:128] := Saturate8(a[143:128])
+ tmp_dst[143:136] := Saturate8(a[159:144])
+ tmp_dst[151:144] := Saturate8(a[175:160])
+ tmp_dst[159:152] := Saturate8(a[191:176])
+ tmp_dst[167:160] := Saturate8(a[207:192])
+ tmp_dst[175:168] := Saturate8(a[223:208])
+ tmp_dst[183:176] := Saturate8(a[239:224])
+ tmp_dst[191:184] := Saturate8(a[255:240])
+ tmp_dst[199:192] := Saturate8(b[143:128])
+ tmp_dst[207:200] := Saturate8(b[159:144])
+ tmp_dst[215:208] := Saturate8(b[175:160])
+ tmp_dst[223:216] := Saturate8(b[191:176])
+ tmp_dst[231:224] := Saturate8(b[207:192])
+ tmp_dst[239:232] := Saturate8(b[223:208])
+ tmp_dst[247:240] := Saturate8(b[239:224])
+ tmp_dst[255:248] := Saturate8(b[255:240])
+ tmp_dst[263:256] := Saturate8(a[271:256])
+ tmp_dst[271:264] := Saturate8(a[287:272])
+ tmp_dst[279:272] := Saturate8(a[303:288])
+ tmp_dst[287:280] := Saturate8(a[319:304])
+ tmp_dst[295:288] := Saturate8(a[335:320])
+ tmp_dst[303:296] := Saturate8(a[351:336])
+ tmp_dst[311:304] := Saturate8(a[367:352])
+ tmp_dst[319:312] := Saturate8(a[383:368])
+ tmp_dst[327:320] := Saturate8(b[271:256])
+ tmp_dst[335:328] := Saturate8(b[287:272])
+ tmp_dst[343:336] := Saturate8(b[303:288])
+ tmp_dst[351:344] := Saturate8(b[319:304])
+ tmp_dst[359:352] := Saturate8(b[335:320])
+ tmp_dst[367:360] := Saturate8(b[351:336])
+ tmp_dst[375:368] := Saturate8(b[367:352])
+ tmp_dst[383:376] := Saturate8(b[383:368])
+ tmp_dst[391:384] := Saturate8(a[399:384])
+ tmp_dst[399:392] := Saturate8(a[415:400])
+ tmp_dst[407:400] := Saturate8(a[431:416])
+ tmp_dst[415:408] := Saturate8(a[447:432])
+ tmp_dst[423:416] := Saturate8(a[463:448])
+ tmp_dst[431:424] := Saturate8(a[479:464])
+ tmp_dst[439:432] := Saturate8(a[495:480])
+ tmp_dst[447:440] := Saturate8(a[511:496])
+ tmp_dst[455:448] := Saturate8(b[399:384])
+ tmp_dst[463:456] := Saturate8(b[415:400])
+ tmp_dst[471:464] := Saturate8(b[431:416])
+ tmp_dst[479:472] := Saturate8(b[447:432])
+ tmp_dst[487:480] := Saturate8(b[463:448])
+ tmp_dst[495:488] := Saturate8(b[479:464])
+ tmp_dst[503:496] := Saturate8(b[495:480])
+ tmp_dst[511:504] := Saturate8(b[511:496])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="zmm {k}, zmm, zmm" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := Saturate8(a[15:0])
+ tmp_dst[15:8] := Saturate8(a[31:16])
+ tmp_dst[23:16] := Saturate8(a[47:32])
+ tmp_dst[31:24] := Saturate8(a[63:48])
+ tmp_dst[39:32] := Saturate8(a[79:64])
+ tmp_dst[47:40] := Saturate8(a[95:80])
+ tmp_dst[55:48] := Saturate8(a[111:96])
+ tmp_dst[63:56] := Saturate8(a[127:112])
+ tmp_dst[71:64] := Saturate8(b[15:0])
+ tmp_dst[79:72] := Saturate8(b[31:16])
+ tmp_dst[87:80] := Saturate8(b[47:32])
+ tmp_dst[95:88] := Saturate8(b[63:48])
+ tmp_dst[103:96] := Saturate8(b[79:64])
+ tmp_dst[111:104] := Saturate8(b[95:80])
+ tmp_dst[119:112] := Saturate8(b[111:96])
+ tmp_dst[127:120] := Saturate8(b[127:112])
+ tmp_dst[135:128] := Saturate8(a[143:128])
+ tmp_dst[143:136] := Saturate8(a[159:144])
+ tmp_dst[151:144] := Saturate8(a[175:160])
+ tmp_dst[159:152] := Saturate8(a[191:176])
+ tmp_dst[167:160] := Saturate8(a[207:192])
+ tmp_dst[175:168] := Saturate8(a[223:208])
+ tmp_dst[183:176] := Saturate8(a[239:224])
+ tmp_dst[191:184] := Saturate8(a[255:240])
+ tmp_dst[199:192] := Saturate8(b[143:128])
+ tmp_dst[207:200] := Saturate8(b[159:144])
+ tmp_dst[215:208] := Saturate8(b[175:160])
+ tmp_dst[223:216] := Saturate8(b[191:176])
+ tmp_dst[231:224] := Saturate8(b[207:192])
+ tmp_dst[239:232] := Saturate8(b[223:208])
+ tmp_dst[247:240] := Saturate8(b[239:224])
+ tmp_dst[255:248] := Saturate8(b[255:240])
+ tmp_dst[263:256] := Saturate8(a[271:256])
+ tmp_dst[271:264] := Saturate8(a[287:272])
+ tmp_dst[279:272] := Saturate8(a[303:288])
+ tmp_dst[287:280] := Saturate8(a[319:304])
+ tmp_dst[295:288] := Saturate8(a[335:320])
+ tmp_dst[303:296] := Saturate8(a[351:336])
+ tmp_dst[311:304] := Saturate8(a[367:352])
+ tmp_dst[319:312] := Saturate8(a[383:368])
+ tmp_dst[327:320] := Saturate8(b[271:256])
+ tmp_dst[335:328] := Saturate8(b[287:272])
+ tmp_dst[343:336] := Saturate8(b[303:288])
+ tmp_dst[351:344] := Saturate8(b[319:304])
+ tmp_dst[359:352] := Saturate8(b[335:320])
+ tmp_dst[367:360] := Saturate8(b[351:336])
+ tmp_dst[375:368] := Saturate8(b[367:352])
+ tmp_dst[383:376] := Saturate8(b[383:368])
+ tmp_dst[391:384] := Saturate8(a[399:384])
+ tmp_dst[399:392] := Saturate8(a[415:400])
+ tmp_dst[407:400] := Saturate8(a[431:416])
+ tmp_dst[415:408] := Saturate8(a[447:432])
+ tmp_dst[423:416] := Saturate8(a[463:448])
+ tmp_dst[431:424] := Saturate8(a[479:464])
+ tmp_dst[439:432] := Saturate8(a[495:480])
+ tmp_dst[447:440] := Saturate8(a[511:496])
+ tmp_dst[455:448] := Saturate8(b[399:384])
+ tmp_dst[463:456] := Saturate8(b[415:400])
+ tmp_dst[471:464] := Saturate8(b[431:416])
+ tmp_dst[479:472] := Saturate8(b[447:432])
+ tmp_dst[487:480] := Saturate8(b[463:448])
+ tmp_dst[495:488] := Saturate8(b[479:464])
+ tmp_dst[503:496] := Saturate8(b[495:480])
+ tmp_dst[511:504] := Saturate8(b[511:496])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="zmm {z}, zmm, zmm" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[7:0] := Saturate8(a[15:0])
+ dst[15:8] := Saturate8(a[31:16])
+ dst[23:16] := Saturate8(a[47:32])
+ dst[31:24] := Saturate8(a[63:48])
+ dst[39:32] := Saturate8(a[79:64])
+ dst[47:40] := Saturate8(a[95:80])
+ dst[55:48] := Saturate8(a[111:96])
+ dst[63:56] := Saturate8(a[127:112])
+ dst[71:64] := Saturate8(b[15:0])
+ dst[79:72] := Saturate8(b[31:16])
+ dst[87:80] := Saturate8(b[47:32])
+ dst[95:88] := Saturate8(b[63:48])
+ dst[103:96] := Saturate8(b[79:64])
+ dst[111:104] := Saturate8(b[95:80])
+ dst[119:112] := Saturate8(b[111:96])
+ dst[127:120] := Saturate8(b[127:112])
+ dst[135:128] := Saturate8(a[143:128])
+ dst[143:136] := Saturate8(a[159:144])
+ dst[151:144] := Saturate8(a[175:160])
+ dst[159:152] := Saturate8(a[191:176])
+ dst[167:160] := Saturate8(a[207:192])
+ dst[175:168] := Saturate8(a[223:208])
+ dst[183:176] := Saturate8(a[239:224])
+ dst[191:184] := Saturate8(a[255:240])
+ dst[199:192] := Saturate8(b[143:128])
+ dst[207:200] := Saturate8(b[159:144])
+ dst[215:208] := Saturate8(b[175:160])
+ dst[223:216] := Saturate8(b[191:176])
+ dst[231:224] := Saturate8(b[207:192])
+ dst[239:232] := Saturate8(b[223:208])
+ dst[247:240] := Saturate8(b[239:224])
+ dst[255:248] := Saturate8(b[255:240])
+ dst[263:256] := Saturate8(a[271:256])
+ dst[271:264] := Saturate8(a[287:272])
+ dst[279:272] := Saturate8(a[303:288])
+ dst[287:280] := Saturate8(a[319:304])
+ dst[295:288] := Saturate8(a[335:320])
+ dst[303:296] := Saturate8(a[351:336])
+ dst[311:304] := Saturate8(a[367:352])
+ dst[319:312] := Saturate8(a[383:368])
+ dst[327:320] := Saturate8(b[271:256])
+ dst[335:328] := Saturate8(b[287:272])
+ dst[343:336] := Saturate8(b[303:288])
+ dst[351:344] := Saturate8(b[319:304])
+ dst[359:352] := Saturate8(b[335:320])
+ dst[367:360] := Saturate8(b[351:336])
+ dst[375:368] := Saturate8(b[367:352])
+ dst[383:376] := Saturate8(b[383:368])
+ dst[391:384] := Saturate8(a[399:384])
+ dst[399:392] := Saturate8(a[415:400])
+ dst[407:400] := Saturate8(a[431:416])
+ dst[415:408] := Saturate8(a[447:432])
+ dst[423:416] := Saturate8(a[463:448])
+ dst[431:424] := Saturate8(a[479:464])
+ dst[439:432] := Saturate8(a[495:480])
+ dst[447:440] := Saturate8(a[511:496])
+ dst[455:448] := Saturate8(b[399:384])
+ dst[463:456] := Saturate8(b[415:400])
+ dst[471:464] := Saturate8(b[431:416])
+ dst[479:472] := Saturate8(b[447:432])
+ dst[487:480] := Saturate8(b[463:448])
+ dst[495:488] := Saturate8(b[479:464])
+ dst[503:496] := Saturate8(b[495:480])
+ dst[511:504] := Saturate8(b[511:496])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="zmm, zmm, zmm" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="SI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := Saturate8(a[15:0])
+ tmp_dst[15:8] := Saturate8(a[31:16])
+ tmp_dst[23:16] := Saturate8(a[47:32])
+ tmp_dst[31:24] := Saturate8(a[63:48])
+ tmp_dst[39:32] := Saturate8(a[79:64])
+ tmp_dst[47:40] := Saturate8(a[95:80])
+ tmp_dst[55:48] := Saturate8(a[111:96])
+ tmp_dst[63:56] := Saturate8(a[127:112])
+ tmp_dst[71:64] := Saturate8(b[15:0])
+ tmp_dst[79:72] := Saturate8(b[31:16])
+ tmp_dst[87:80] := Saturate8(b[47:32])
+ tmp_dst[95:88] := Saturate8(b[63:48])
+ tmp_dst[103:96] := Saturate8(b[79:64])
+ tmp_dst[111:104] := Saturate8(b[95:80])
+ tmp_dst[119:112] := Saturate8(b[111:96])
+ tmp_dst[127:120] := Saturate8(b[127:112])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="xmm {k}, xmm, xmm" xed="VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_packs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := Saturate8(a[15:0])
+ tmp_dst[15:8] := Saturate8(a[31:16])
+ tmp_dst[23:16] := Saturate8(a[47:32])
+ tmp_dst[31:24] := Saturate8(a[63:48])
+ tmp_dst[39:32] := Saturate8(a[79:64])
+ tmp_dst[47:40] := Saturate8(a[95:80])
+ tmp_dst[55:48] := Saturate8(a[111:96])
+ tmp_dst[63:56] := Saturate8(a[127:112])
+ tmp_dst[71:64] := Saturate8(b[15:0])
+ tmp_dst[79:72] := Saturate8(b[31:16])
+ tmp_dst[87:80] := Saturate8(b[47:32])
+ tmp_dst[95:88] := Saturate8(b[63:48])
+ tmp_dst[103:96] := Saturate8(b[79:64])
+ tmp_dst[111:104] := Saturate8(b[95:80])
+ tmp_dst[119:112] := Saturate8(b[111:96])
+ tmp_dst[127:120] := Saturate8(b[127:112])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKSSWB" form="xmm {z}, xmm, xmm" xed="VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := SaturateU16(a[31:0])
+ tmp_dst[31:16] := SaturateU16(a[63:32])
+ tmp_dst[47:32] := SaturateU16(a[95:64])
+ tmp_dst[63:48] := SaturateU16(a[127:96])
+ tmp_dst[79:64] := SaturateU16(b[31:0])
+ tmp_dst[95:80] := SaturateU16(b[63:32])
+ tmp_dst[111:96] := SaturateU16(b[95:64])
+ tmp_dst[127:112] := SaturateU16(b[127:96])
+ tmp_dst[143:128] := SaturateU16(a[159:128])
+ tmp_dst[159:144] := SaturateU16(a[191:160])
+ tmp_dst[175:160] := SaturateU16(a[223:192])
+ tmp_dst[191:176] := SaturateU16(a[255:224])
+ tmp_dst[207:192] := SaturateU16(b[159:128])
+ tmp_dst[223:208] := SaturateU16(b[191:160])
+ tmp_dst[239:224] := SaturateU16(b[223:192])
+ tmp_dst[255:240] := SaturateU16(b[255:224])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="ymm {k}, ymm, ymm" xed="VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := SaturateU16(a[31:0])
+ tmp_dst[31:16] := SaturateU16(a[63:32])
+ tmp_dst[47:32] := SaturateU16(a[95:64])
+ tmp_dst[63:48] := SaturateU16(a[127:96])
+ tmp_dst[79:64] := SaturateU16(b[31:0])
+ tmp_dst[95:80] := SaturateU16(b[63:32])
+ tmp_dst[111:96] := SaturateU16(b[95:64])
+ tmp_dst[127:112] := SaturateU16(b[127:96])
+ tmp_dst[143:128] := SaturateU16(a[159:128])
+ tmp_dst[159:144] := SaturateU16(a[191:160])
+ tmp_dst[175:160] := SaturateU16(a[223:192])
+ tmp_dst[191:176] := SaturateU16(a[255:224])
+ tmp_dst[207:192] := SaturateU16(b[159:128])
+ tmp_dst[223:208] := SaturateU16(b[191:160])
+ tmp_dst[239:224] := SaturateU16(b[223:192])
+ tmp_dst[255:240] := SaturateU16(b[255:224])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="ymm {z}, ymm, ymm" xed="VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI32"/>
+ 	<parameter type="__m512i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := SaturateU16(a[31:0])
+ tmp_dst[31:16] := SaturateU16(a[63:32])
+ tmp_dst[47:32] := SaturateU16(a[95:64])
+ tmp_dst[63:48] := SaturateU16(a[127:96])
+ tmp_dst[79:64] := SaturateU16(b[31:0])
+ tmp_dst[95:80] := SaturateU16(b[63:32])
+ tmp_dst[111:96] := SaturateU16(b[95:64])
+ tmp_dst[127:112] := SaturateU16(b[127:96])
+ tmp_dst[143:128] := SaturateU16(a[159:128])
+ tmp_dst[159:144] := SaturateU16(a[191:160])
+ tmp_dst[175:160] := SaturateU16(a[223:192])
+ tmp_dst[191:176] := SaturateU16(a[255:224])
+ tmp_dst[207:192] := SaturateU16(b[159:128])
+ tmp_dst[223:208] := SaturateU16(b[191:160])
+ tmp_dst[239:224] := SaturateU16(b[223:192])
+ tmp_dst[255:240] := SaturateU16(b[255:224])
+ tmp_dst[271:256] := SaturateU16(a[287:256])
+ tmp_dst[287:272] := SaturateU16(a[319:288])
+ tmp_dst[303:288] := SaturateU16(a[351:320])
+ tmp_dst[319:304] := SaturateU16(a[383:352])
+ tmp_dst[335:320] := SaturateU16(b[287:256])
+ tmp_dst[351:336] := SaturateU16(b[319:288])
+ tmp_dst[367:352] := SaturateU16(b[351:320])
+ tmp_dst[383:368] := SaturateU16(b[383:352])
+ tmp_dst[399:384] := SaturateU16(a[415:384])
+ tmp_dst[415:400] := SaturateU16(a[447:416])
+ tmp_dst[431:416] := SaturateU16(a[479:448])
+ tmp_dst[447:432] := SaturateU16(a[511:480])
+ tmp_dst[463:448] := SaturateU16(b[415:384])
+ tmp_dst[479:464] := SaturateU16(b[447:416])
+ tmp_dst[495:480] := SaturateU16(b[479:448])
+ tmp_dst[511:496] := SaturateU16(b[511:480])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="zmm {k}, zmm, zmm" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI32"/>
+ 	<parameter type="__m512i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := SaturateU16(a[31:0])
+ tmp_dst[31:16] := SaturateU16(a[63:32])
+ tmp_dst[47:32] := SaturateU16(a[95:64])
+ tmp_dst[63:48] := SaturateU16(a[127:96])
+ tmp_dst[79:64] := SaturateU16(b[31:0])
+ tmp_dst[95:80] := SaturateU16(b[63:32])
+ tmp_dst[111:96] := SaturateU16(b[95:64])
+ tmp_dst[127:112] := SaturateU16(b[127:96])
+ tmp_dst[143:128] := SaturateU16(a[159:128])
+ tmp_dst[159:144] := SaturateU16(a[191:160])
+ tmp_dst[175:160] := SaturateU16(a[223:192])
+ tmp_dst[191:176] := SaturateU16(a[255:224])
+ tmp_dst[207:192] := SaturateU16(b[159:128])
+ tmp_dst[223:208] := SaturateU16(b[191:160])
+ tmp_dst[239:224] := SaturateU16(b[223:192])
+ tmp_dst[255:240] := SaturateU16(b[255:224])
+ tmp_dst[271:256] := SaturateU16(a[287:256])
+ tmp_dst[287:272] := SaturateU16(a[319:288])
+ tmp_dst[303:288] := SaturateU16(a[351:320])
+ tmp_dst[319:304] := SaturateU16(a[383:352])
+ tmp_dst[335:320] := SaturateU16(b[287:256])
+ tmp_dst[351:336] := SaturateU16(b[319:288])
+ tmp_dst[367:352] := SaturateU16(b[351:320])
+ tmp_dst[383:368] := SaturateU16(b[383:352])
+ tmp_dst[399:384] := SaturateU16(a[415:384])
+ tmp_dst[415:400] := SaturateU16(a[447:416])
+ tmp_dst[431:416] := SaturateU16(a[479:448])
+ tmp_dst[447:432] := SaturateU16(a[511:480])
+ tmp_dst[463:448] := SaturateU16(b[415:384])
+ tmp_dst[479:464] := SaturateU16(b[447:416])
+ tmp_dst[495:480] := SaturateU16(b[479:448])
+ tmp_dst[511:496] := SaturateU16(b[511:480])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="zmm {z}, zmm, zmm" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI32"/>
+ 	<parameter type="__m512i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[15:0] := SaturateU16(a[31:0])
+ dst[31:16] := SaturateU16(a[63:32])
+ dst[47:32] := SaturateU16(a[95:64])
+ dst[63:48] := SaturateU16(a[127:96])
+ dst[79:64] := SaturateU16(b[31:0])
+ dst[95:80] := SaturateU16(b[63:32])
+ dst[111:96] := SaturateU16(b[95:64])
+ dst[127:112] := SaturateU16(b[127:96])
+ dst[143:128] := SaturateU16(a[159:128])
+ dst[159:144] := SaturateU16(a[191:160])
+ dst[175:160] := SaturateU16(a[223:192])
+ dst[191:176] := SaturateU16(a[255:224])
+ dst[207:192] := SaturateU16(b[159:128])
+ dst[223:208] := SaturateU16(b[191:160])
+ dst[239:224] := SaturateU16(b[223:192])
+ dst[255:240] := SaturateU16(b[255:224])
+ dst[271:256] := SaturateU16(a[287:256])
+ dst[287:272] := SaturateU16(a[319:288])
+ dst[303:288] := SaturateU16(a[351:320])
+ dst[319:304] := SaturateU16(a[383:352])
+ dst[335:320] := SaturateU16(b[287:256])
+ dst[351:336] := SaturateU16(b[319:288])
+ dst[367:352] := SaturateU16(b[351:320])
+ dst[383:368] := SaturateU16(b[383:352])
+ dst[399:384] := SaturateU16(a[415:384])
+ dst[415:400] := SaturateU16(a[447:416])
+ dst[431:416] := SaturateU16(a[479:448])
+ dst[447:432] := SaturateU16(a[511:480])
+ dst[463:448] := SaturateU16(b[415:384])
+ dst[479:464] := SaturateU16(b[447:416])
+ dst[495:480] := SaturateU16(b[479:448])
+ dst[511:496] := SaturateU16(b[511:480])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="zmm, zmm, zmm" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := SaturateU16(a[31:0])
+ tmp_dst[31:16] := SaturateU16(a[63:32])
+ tmp_dst[47:32] := SaturateU16(a[95:64])
+ tmp_dst[63:48] := SaturateU16(a[127:96])
+ tmp_dst[79:64] := SaturateU16(b[31:0])
+ tmp_dst[95:80] := SaturateU16(b[63:32])
+ tmp_dst[111:96] := SaturateU16(b[95:64])
+ tmp_dst[127:112] := SaturateU16(b[127:96])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="xmm {k}, xmm, xmm" xed="VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_packus_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := SaturateU16(a[31:0])
+ tmp_dst[31:16] := SaturateU16(a[63:32])
+ tmp_dst[47:32] := SaturateU16(a[95:64])
+ tmp_dst[63:48] := SaturateU16(a[127:96])
+ tmp_dst[79:64] := SaturateU16(b[31:0])
+ tmp_dst[95:80] := SaturateU16(b[63:32])
+ tmp_dst[111:96] := SaturateU16(b[95:64])
+ tmp_dst[127:112] := SaturateU16(b[127:96])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSDW" form="xmm {z}, xmm, xmm" xed="VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := SaturateU8(a[15:0])
+ tmp_dst[15:8] := SaturateU8(a[31:16])
+ tmp_dst[23:16] := SaturateU8(a[47:32])
+ tmp_dst[31:24] := SaturateU8(a[63:48])
+ tmp_dst[39:32] := SaturateU8(a[79:64])
+ tmp_dst[47:40] := SaturateU8(a[95:80])
+ tmp_dst[55:48] := SaturateU8(a[111:96])
+ tmp_dst[63:56] := SaturateU8(a[127:112])
+ tmp_dst[71:64] := SaturateU8(b[15:0])
+ tmp_dst[79:72] := SaturateU8(b[31:16])
+ tmp_dst[87:80] := SaturateU8(b[47:32])
+ tmp_dst[95:88] := SaturateU8(b[63:48])
+ tmp_dst[103:96] := SaturateU8(b[79:64])
+ tmp_dst[111:104] := SaturateU8(b[95:80])
+ tmp_dst[119:112] := SaturateU8(b[111:96])
+ tmp_dst[127:120] := SaturateU8(b[127:112])
+ tmp_dst[135:128] := SaturateU8(a[143:128])
+ tmp_dst[143:136] := SaturateU8(a[159:144])
+ tmp_dst[151:144] := SaturateU8(a[175:160])
+ tmp_dst[159:152] := SaturateU8(a[191:176])
+ tmp_dst[167:160] := SaturateU8(a[207:192])
+ tmp_dst[175:168] := SaturateU8(a[223:208])
+ tmp_dst[183:176] := SaturateU8(a[239:224])
+ tmp_dst[191:184] := SaturateU8(a[255:240])
+ tmp_dst[199:192] := SaturateU8(b[143:128])
+ tmp_dst[207:200] := SaturateU8(b[159:144])
+ tmp_dst[215:208] := SaturateU8(b[175:160])
+ tmp_dst[223:216] := SaturateU8(b[191:176])
+ tmp_dst[231:224] := SaturateU8(b[207:192])
+ tmp_dst[239:232] := SaturateU8(b[223:208])
+ tmp_dst[247:240] := SaturateU8(b[239:224])
+ tmp_dst[255:248] := SaturateU8(b[255:240])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="ymm {k}, ymm, ymm" xed="VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := SaturateU8(a[15:0])
+ tmp_dst[15:8] := SaturateU8(a[31:16])
+ tmp_dst[23:16] := SaturateU8(a[47:32])
+ tmp_dst[31:24] := SaturateU8(a[63:48])
+ tmp_dst[39:32] := SaturateU8(a[79:64])
+ tmp_dst[47:40] := SaturateU8(a[95:80])
+ tmp_dst[55:48] := SaturateU8(a[111:96])
+ tmp_dst[63:56] := SaturateU8(a[127:112])
+ tmp_dst[71:64] := SaturateU8(b[15:0])
+ tmp_dst[79:72] := SaturateU8(b[31:16])
+ tmp_dst[87:80] := SaturateU8(b[47:32])
+ tmp_dst[95:88] := SaturateU8(b[63:48])
+ tmp_dst[103:96] := SaturateU8(b[79:64])
+ tmp_dst[111:104] := SaturateU8(b[95:80])
+ tmp_dst[119:112] := SaturateU8(b[111:96])
+ tmp_dst[127:120] := SaturateU8(b[127:112])
+ tmp_dst[135:128] := SaturateU8(a[143:128])
+ tmp_dst[143:136] := SaturateU8(a[159:144])
+ tmp_dst[151:144] := SaturateU8(a[175:160])
+ tmp_dst[159:152] := SaturateU8(a[191:176])
+ tmp_dst[167:160] := SaturateU8(a[207:192])
+ tmp_dst[175:168] := SaturateU8(a[223:208])
+ tmp_dst[183:176] := SaturateU8(a[239:224])
+ tmp_dst[191:184] := SaturateU8(a[255:240])
+ tmp_dst[199:192] := SaturateU8(b[143:128])
+ tmp_dst[207:200] := SaturateU8(b[159:144])
+ tmp_dst[215:208] := SaturateU8(b[175:160])
+ tmp_dst[223:216] := SaturateU8(b[191:176])
+ tmp_dst[231:224] := SaturateU8(b[207:192])
+ tmp_dst[239:232] := SaturateU8(b[223:208])
+ tmp_dst[247:240] := SaturateU8(b[239:224])
+ tmp_dst[255:248] := SaturateU8(b[255:240])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="ymm {z}, ymm, ymm" xed="VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := SaturateU8(a[15:0])
+ tmp_dst[15:8] := SaturateU8(a[31:16])
+ tmp_dst[23:16] := SaturateU8(a[47:32])
+ tmp_dst[31:24] := SaturateU8(a[63:48])
+ tmp_dst[39:32] := SaturateU8(a[79:64])
+ tmp_dst[47:40] := SaturateU8(a[95:80])
+ tmp_dst[55:48] := SaturateU8(a[111:96])
+ tmp_dst[63:56] := SaturateU8(a[127:112])
+ tmp_dst[71:64] := SaturateU8(b[15:0])
+ tmp_dst[79:72] := SaturateU8(b[31:16])
+ tmp_dst[87:80] := SaturateU8(b[47:32])
+ tmp_dst[95:88] := SaturateU8(b[63:48])
+ tmp_dst[103:96] := SaturateU8(b[79:64])
+ tmp_dst[111:104] := SaturateU8(b[95:80])
+ tmp_dst[119:112] := SaturateU8(b[111:96])
+ tmp_dst[127:120] := SaturateU8(b[127:112])
+ tmp_dst[135:128] := SaturateU8(a[143:128])
+ tmp_dst[143:136] := SaturateU8(a[159:144])
+ tmp_dst[151:144] := SaturateU8(a[175:160])
+ tmp_dst[159:152] := SaturateU8(a[191:176])
+ tmp_dst[167:160] := SaturateU8(a[207:192])
+ tmp_dst[175:168] := SaturateU8(a[223:208])
+ tmp_dst[183:176] := SaturateU8(a[239:224])
+ tmp_dst[191:184] := SaturateU8(a[255:240])
+ tmp_dst[199:192] := SaturateU8(b[143:128])
+ tmp_dst[207:200] := SaturateU8(b[159:144])
+ tmp_dst[215:208] := SaturateU8(b[175:160])
+ tmp_dst[223:216] := SaturateU8(b[191:176])
+ tmp_dst[231:224] := SaturateU8(b[207:192])
+ tmp_dst[239:232] := SaturateU8(b[223:208])
+ tmp_dst[247:240] := SaturateU8(b[239:224])
+ tmp_dst[255:248] := SaturateU8(b[255:240])
+ tmp_dst[263:256] := SaturateU8(a[271:256])
+ tmp_dst[271:264] := SaturateU8(a[287:272])
+ tmp_dst[279:272] := SaturateU8(a[303:288])
+ tmp_dst[287:280] := SaturateU8(a[319:304])
+ tmp_dst[295:288] := SaturateU8(a[335:320])
+ tmp_dst[303:296] := SaturateU8(a[351:336])
+ tmp_dst[311:304] := SaturateU8(a[367:352])
+ tmp_dst[319:312] := SaturateU8(a[383:368])
+ tmp_dst[327:320] := SaturateU8(b[271:256])
+ tmp_dst[335:328] := SaturateU8(b[287:272])
+ tmp_dst[343:336] := SaturateU8(b[303:288])
+ tmp_dst[351:344] := SaturateU8(b[319:304])
+ tmp_dst[359:352] := SaturateU8(b[335:320])
+ tmp_dst[367:360] := SaturateU8(b[351:336])
+ tmp_dst[375:368] := SaturateU8(b[367:352])
+ tmp_dst[383:376] := SaturateU8(b[383:368])
+ tmp_dst[391:384] := SaturateU8(a[399:384])
+ tmp_dst[399:392] := SaturateU8(a[415:400])
+ tmp_dst[407:400] := SaturateU8(a[431:416])
+ tmp_dst[415:408] := SaturateU8(a[447:432])
+ tmp_dst[423:416] := SaturateU8(a[463:448])
+ tmp_dst[431:424] := SaturateU8(a[479:464])
+ tmp_dst[439:432] := SaturateU8(a[495:480])
+ tmp_dst[447:440] := SaturateU8(a[511:496])
+ tmp_dst[455:448] := SaturateU8(b[399:384])
+ tmp_dst[463:456] := SaturateU8(b[415:400])
+ tmp_dst[471:464] := SaturateU8(b[431:416])
+ tmp_dst[479:472] := SaturateU8(b[447:432])
+ tmp_dst[487:480] := SaturateU8(b[463:448])
+ tmp_dst[495:488] := SaturateU8(b[479:464])
+ tmp_dst[503:496] := SaturateU8(b[495:480])
+ tmp_dst[511:504] := SaturateU8(b[511:496])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="zmm {k}, zmm, zmm" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := SaturateU8(a[15:0])
+ tmp_dst[15:8] := SaturateU8(a[31:16])
+ tmp_dst[23:16] := SaturateU8(a[47:32])
+ tmp_dst[31:24] := SaturateU8(a[63:48])
+ tmp_dst[39:32] := SaturateU8(a[79:64])
+ tmp_dst[47:40] := SaturateU8(a[95:80])
+ tmp_dst[55:48] := SaturateU8(a[111:96])
+ tmp_dst[63:56] := SaturateU8(a[127:112])
+ tmp_dst[71:64] := SaturateU8(b[15:0])
+ tmp_dst[79:72] := SaturateU8(b[31:16])
+ tmp_dst[87:80] := SaturateU8(b[47:32])
+ tmp_dst[95:88] := SaturateU8(b[63:48])
+ tmp_dst[103:96] := SaturateU8(b[79:64])
+ tmp_dst[111:104] := SaturateU8(b[95:80])
+ tmp_dst[119:112] := SaturateU8(b[111:96])
+ tmp_dst[127:120] := SaturateU8(b[127:112])
+ tmp_dst[135:128] := SaturateU8(a[143:128])
+ tmp_dst[143:136] := SaturateU8(a[159:144])
+ tmp_dst[151:144] := SaturateU8(a[175:160])
+ tmp_dst[159:152] := SaturateU8(a[191:176])
+ tmp_dst[167:160] := SaturateU8(a[207:192])
+ tmp_dst[175:168] := SaturateU8(a[223:208])
+ tmp_dst[183:176] := SaturateU8(a[239:224])
+ tmp_dst[191:184] := SaturateU8(a[255:240])
+ tmp_dst[199:192] := SaturateU8(b[143:128])
+ tmp_dst[207:200] := SaturateU8(b[159:144])
+ tmp_dst[215:208] := SaturateU8(b[175:160])
+ tmp_dst[223:216] := SaturateU8(b[191:176])
+ tmp_dst[231:224] := SaturateU8(b[207:192])
+ tmp_dst[239:232] := SaturateU8(b[223:208])
+ tmp_dst[247:240] := SaturateU8(b[239:224])
+ tmp_dst[255:248] := SaturateU8(b[255:240])
+ tmp_dst[263:256] := SaturateU8(a[271:256])
+ tmp_dst[271:264] := SaturateU8(a[287:272])
+ tmp_dst[279:272] := SaturateU8(a[303:288])
+ tmp_dst[287:280] := SaturateU8(a[319:304])
+ tmp_dst[295:288] := SaturateU8(a[335:320])
+ tmp_dst[303:296] := SaturateU8(a[351:336])
+ tmp_dst[311:304] := SaturateU8(a[367:352])
+ tmp_dst[319:312] := SaturateU8(a[383:368])
+ tmp_dst[327:320] := SaturateU8(b[271:256])
+ tmp_dst[335:328] := SaturateU8(b[287:272])
+ tmp_dst[343:336] := SaturateU8(b[303:288])
+ tmp_dst[351:344] := SaturateU8(b[319:304])
+ tmp_dst[359:352] := SaturateU8(b[335:320])
+ tmp_dst[367:360] := SaturateU8(b[351:336])
+ tmp_dst[375:368] := SaturateU8(b[367:352])
+ tmp_dst[383:376] := SaturateU8(b[383:368])
+ tmp_dst[391:384] := SaturateU8(a[399:384])
+ tmp_dst[399:392] := SaturateU8(a[415:400])
+ tmp_dst[407:400] := SaturateU8(a[431:416])
+ tmp_dst[415:408] := SaturateU8(a[447:432])
+ tmp_dst[423:416] := SaturateU8(a[463:448])
+ tmp_dst[431:424] := SaturateU8(a[479:464])
+ tmp_dst[439:432] := SaturateU8(a[495:480])
+ tmp_dst[447:440] := SaturateU8(a[511:496])
+ tmp_dst[455:448] := SaturateU8(b[399:384])
+ tmp_dst[463:456] := SaturateU8(b[415:400])
+ tmp_dst[471:464] := SaturateU8(b[431:416])
+ tmp_dst[479:472] := SaturateU8(b[447:432])
+ tmp_dst[487:480] := SaturateU8(b[463:448])
+ tmp_dst[495:488] := SaturateU8(b[479:464])
+ tmp_dst[503:496] := SaturateU8(b[495:480])
+ tmp_dst[511:504] := SaturateU8(b[511:496])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="zmm {z}, zmm, zmm" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ dst[7:0] := SaturateU8(a[15:0])
+ dst[15:8] := SaturateU8(a[31:16])
+ dst[23:16] := SaturateU8(a[47:32])
+ dst[31:24] := SaturateU8(a[63:48])
+ dst[39:32] := SaturateU8(a[79:64])
+ dst[47:40] := SaturateU8(a[95:80])
+ dst[55:48] := SaturateU8(a[111:96])
+ dst[63:56] := SaturateU8(a[127:112])
+ dst[71:64] := SaturateU8(b[15:0])
+ dst[79:72] := SaturateU8(b[31:16])
+ dst[87:80] := SaturateU8(b[47:32])
+ dst[95:88] := SaturateU8(b[63:48])
+ dst[103:96] := SaturateU8(b[79:64])
+ dst[111:104] := SaturateU8(b[95:80])
+ dst[119:112] := SaturateU8(b[111:96])
+ dst[127:120] := SaturateU8(b[127:112])
+ dst[135:128] := SaturateU8(a[143:128])
+ dst[143:136] := SaturateU8(a[159:144])
+ dst[151:144] := SaturateU8(a[175:160])
+ dst[159:152] := SaturateU8(a[191:176])
+ dst[167:160] := SaturateU8(a[207:192])
+ dst[175:168] := SaturateU8(a[223:208])
+ dst[183:176] := SaturateU8(a[239:224])
+ dst[191:184] := SaturateU8(a[255:240])
+ dst[199:192] := SaturateU8(b[143:128])
+ dst[207:200] := SaturateU8(b[159:144])
+ dst[215:208] := SaturateU8(b[175:160])
+ dst[223:216] := SaturateU8(b[191:176])
+ dst[231:224] := SaturateU8(b[207:192])
+ dst[239:232] := SaturateU8(b[223:208])
+ dst[247:240] := SaturateU8(b[239:224])
+ dst[255:248] := SaturateU8(b[255:240])
+ dst[263:256] := SaturateU8(a[271:256])
+ dst[271:264] := SaturateU8(a[287:272])
+ dst[279:272] := SaturateU8(a[303:288])
+ dst[287:280] := SaturateU8(a[319:304])
+ dst[295:288] := SaturateU8(a[335:320])
+ dst[303:296] := SaturateU8(a[351:336])
+ dst[311:304] := SaturateU8(a[367:352])
+ dst[319:312] := SaturateU8(a[383:368])
+ dst[327:320] := SaturateU8(b[271:256])
+ dst[335:328] := SaturateU8(b[287:272])
+ dst[343:336] := SaturateU8(b[303:288])
+ dst[351:344] := SaturateU8(b[319:304])
+ dst[359:352] := SaturateU8(b[335:320])
+ dst[367:360] := SaturateU8(b[351:336])
+ dst[375:368] := SaturateU8(b[367:352])
+ dst[383:376] := SaturateU8(b[383:368])
+ dst[391:384] := SaturateU8(a[399:384])
+ dst[399:392] := SaturateU8(a[415:400])
+ dst[407:400] := SaturateU8(a[431:416])
+ dst[415:408] := SaturateU8(a[447:432])
+ dst[423:416] := SaturateU8(a[463:448])
+ dst[431:424] := SaturateU8(a[479:464])
+ dst[439:432] := SaturateU8(a[495:480])
+ dst[447:440] := SaturateU8(a[511:496])
+ dst[455:448] := SaturateU8(b[399:384])
+ dst[463:456] := SaturateU8(b[415:400])
+ dst[471:464] := SaturateU8(b[431:416])
+ dst[479:472] := SaturateU8(b[447:432])
+ dst[487:480] := SaturateU8(b[463:448])
+ dst[495:488] := SaturateU8(b[479:464])
+ dst[503:496] := SaturateU8(b[495:480])
+ dst[511:504] := SaturateU8(b[511:496])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="zmm, zmm, zmm" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := SaturateU8(a[15:0])
+ tmp_dst[15:8] := SaturateU8(a[31:16])
+ tmp_dst[23:16] := SaturateU8(a[47:32])
+ tmp_dst[31:24] := SaturateU8(a[63:48])
+ tmp_dst[39:32] := SaturateU8(a[79:64])
+ tmp_dst[47:40] := SaturateU8(a[95:80])
+ tmp_dst[55:48] := SaturateU8(a[111:96])
+ tmp_dst[63:56] := SaturateU8(a[127:112])
+ tmp_dst[71:64] := SaturateU8(b[15:0])
+ tmp_dst[79:72] := SaturateU8(b[31:16])
+ tmp_dst[87:80] := SaturateU8(b[47:32])
+ tmp_dst[95:88] := SaturateU8(b[63:48])
+ tmp_dst[103:96] := SaturateU8(b[79:64])
+ tmp_dst[111:104] := SaturateU8(b[95:80])
+ tmp_dst[119:112] := SaturateU8(b[111:96])
+ tmp_dst[127:120] := SaturateU8(b[127:112])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="xmm {k}, xmm, xmm" xed="VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_packus_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[7:0] := SaturateU8(a[15:0])
+ tmp_dst[15:8] := SaturateU8(a[31:16])
+ tmp_dst[23:16] := SaturateU8(a[47:32])
+ tmp_dst[31:24] := SaturateU8(a[63:48])
+ tmp_dst[39:32] := SaturateU8(a[79:64])
+ tmp_dst[47:40] := SaturateU8(a[95:80])
+ tmp_dst[55:48] := SaturateU8(a[111:96])
+ tmp_dst[63:56] := SaturateU8(a[127:112])
+ tmp_dst[71:64] := SaturateU8(b[15:0])
+ tmp_dst[79:72] := SaturateU8(b[31:16])
+ tmp_dst[87:80] := SaturateU8(b[47:32])
+ tmp_dst[95:88] := SaturateU8(b[63:48])
+ tmp_dst[103:96] := SaturateU8(b[79:64])
+ tmp_dst[111:104] := SaturateU8(b[95:80])
+ tmp_dst[119:112] := SaturateU8(b[111:96])
+ tmp_dst[127:120] := SaturateU8(b[127:112])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPACKUSWB" form="xmm {z}, xmm, xmm" xed="VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="ymm {k}, ymm, ymm" xed="VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="ymm {z}, ymm, ymm" xed="VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="zmm, zmm, zmm" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="zmm {k}, zmm, zmm" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="zmm {z}, zmm, zmm" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="xmm {k}, xmm, xmm" xed="VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_add_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDB" form="xmm {z}, xmm, xmm" xed="VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="ymm {k}, ymm, ymm" xed="VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="ymm {z}, ymm, ymm" xed="VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="zmm, zmm, zmm" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="zmm {k}, zmm, zmm" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="zmm {z}, zmm, zmm" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="xmm {k}, xmm, xmm" xed="VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_adds_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDSB" form="xmm {z}, xmm, xmm" xed="VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="ymm {k}, ymm, ymm" xed="VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="ymm {z}, ymm, ymm" xed="VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="zmm, zmm, zmm" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="zmm {k}, zmm, zmm" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="zmm {z}, zmm, zmm" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="xmm {k}, xmm, xmm" xed="VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_adds_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDSW" form="xmm {z}, xmm, xmm" xed="VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="ymm {k}, ymm, ymm" xed="VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="ymm {z}, ymm, ymm" xed="VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="zmm, zmm, zmm" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="zmm {k}, zmm, zmm" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="zmm {z}, zmm, zmm" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="xmm {k}, xmm, xmm" xed="VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_adds_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSB" form="xmm {z}, xmm, xmm" xed="VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="ymm {k}, ymm, ymm" xed="VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="ymm {z}, ymm, ymm" xed="VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="zmm, zmm, zmm" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="zmm {k}, zmm, zmm" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="zmm {z}, zmm, zmm" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="xmm {k}, xmm, xmm" xed="VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_adds_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDUSW" form="xmm {z}, xmm, xmm" xed="VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="ymm {k}, ymm, ymm" xed="VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="ymm {z}, ymm, ymm" xed="VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="zmm, zmm, zmm" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="zmm {k}, zmm, zmm" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="zmm {z}, zmm, zmm" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="xmm {k}, xmm, xmm" xed="VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_add_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDW" form="xmm {z}, xmm, xmm" xed="VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*128
+ 	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+ 	tmp_dst[i+127:i] := tmp[127:0]
+ ENDFOR
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="ymm {k}, ymm, ymm, imm8" xed="VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*128
+ 	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+ 	tmp_dst[i+127:i] := tmp[127:0]
+ ENDFOR
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="ymm {z}, ymm, ymm, imm8" xed="VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*128
+ 	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+ 	dst[i+127:i] := tmp[127:0]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="zmm, zmm, zmm, imm8" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*128
+ 	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+ 	tmp_dst[i+127:i] := tmp[127:0]
+ ENDFOR
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="zmm {k}, zmm, zmm, imm8" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*128
+ 	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+ 	tmp_dst[i+127:i] := tmp[127:0]
+ ENDFOR
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="zmm {z}, zmm, zmm, imm8" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="xmm {k}, xmm, xmm, imm8" xed="VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_alignr_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPALIGNR" form="xmm {z}, xmm, xmm, imm8" xed="VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="ymm {k}, ymm, ymm" xed="VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="ymm {z}, ymm, ymm" xed="VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="zmm, zmm, zmm" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="zmm {k}, zmm, zmm" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="zmm {z}, zmm, zmm" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="xmm {k}, xmm, xmm" xed="VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_avg_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPAVGB" form="xmm {z}, xmm, xmm" xed="VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="ymm {k}, ymm, ymm" xed="VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="ymm {z}, ymm, ymm" xed="VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="zmm, zmm, zmm" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="zmm {k}, zmm, zmm" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="zmm {z}, zmm, zmm" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="xmm {k}, xmm, xmm" xed="VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_avg_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPAVGW" form="xmm {z}, xmm, xmm" xed="VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_blend_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMB" form="ymm {k}, ymm, ymm" xed="VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_blend_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMB" form="zmm {k}, zmm, zmm" xed="VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_blend_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := a[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMB" form="xmm {k}, xmm, xmm" xed="VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_blend_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMW" form="ymm {k}, ymm, ymm" xed="VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_blend_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMW" form="zmm {k}, zmm, zmm" xed="VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_blend_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMW" form="xmm {k}, xmm, xmm" xed="VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="ymm {k}, xmm" xed="VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="ymm {k}, r8" xed="VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="ymm {z}, xmm" xed="VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="ymm {z}, r8" xed="VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := a[7:0]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="zmm, xmm" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="zmm {k}, xmm" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="zmm {k}, r8" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="zmm {z}, xmm" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="zmm {z}, r8" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="xmm {k}, xmm" xed="VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="xmm {k}, r8" xed="VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_broadcastb_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="xmm {z}, xmm" xed="VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_set1_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="char" varname="a" etype="UI8"/>
+ 	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[7:0]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTB" form="xmm {z}, r8" xed="VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="ymm {k}, xmm" xed="VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="ymm {k}, r16" xed="VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="ymm {z}, xmm" xed="VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast 16-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="ymm {z}, r16" xed="VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := a[15:0]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="zmm, xmm" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="zmm {k}, xmm" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast 16-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="zmm {k}, r16" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="zmm {z}, xmm" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="zmm {z}, r16" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="xmm {k}, xmm" xed="VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="xmm {k}, r16" xed="VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_broadcastw_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="xmm {z}, xmm" xed="VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_set1_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="short" varname="a" etype="UI16"/>
+ 	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTW" form="xmm {z}, r16" xed="VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm, imm8" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm, imm8" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, ymm, ymm" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmp_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm, imm8" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpeq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpge_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpgt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmple_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmplt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpneq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmp_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm, imm8" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpeq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpge_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpgt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmple_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmplt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpneq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, zmm, zmm" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm, imm8" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm, imm8" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPB" form="k {k}, xmm, xmm" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm, imm8" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm, imm8" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, ymm, ymm" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmp_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm, imm8" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpeq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpge_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpgt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmple_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmplt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpneq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmp_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm, imm8" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpeq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpge_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpgt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmple_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmplt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpneq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, zmm, zmm" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm, imm8" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm, imm8" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epu8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUB" form="k {k}, xmm, xmm" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm, imm8" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm, imm8" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, ymm, ymm" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmp_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm, imm8" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpeq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpge_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpgt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmple_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmplt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpneq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmp_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm, imm8" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpeq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpge_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpgt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmple_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmplt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpneq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, zmm, zmm" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm, imm8" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm, imm8" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epu16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUW" form="k {k}, xmm, xmm" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm, imm8" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm, imm8" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, ymm, ymm" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmp_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm, imm8" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpeq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpge_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpgt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmple_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmplt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cmpneq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmp_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm, imm8" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpeq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpge_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpgt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmple_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmplt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cmpneq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, zmm, zmm" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm, imm8" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm, imm8" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPW" form="k {k}, xmm, xmm" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask2_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+3:i]
+ 		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := idx[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="ymm {k}, ymm, ymm" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+3:i]
+ 		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2W" form="ymm {k}, ymm, ymm" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+3:i]
+ 		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="ymm {z}, ymm, ymm" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<instruction name="VPERMT2W" form="ymm {z}, ymm, ymm" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	off := 16*idx[i+3:i]
+ 	dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="ymm, ymm, ymm" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<instruction name="VPERMT2W" form="ymm, ymm, ymm" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask2_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+4:i]
+ 		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := idx[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="zmm {k}, zmm, zmm" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+4:i]
+ 		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2W" form="zmm {k}, zmm, zmm" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+4:i]
+ 		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="zmm {z}, zmm, zmm" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<instruction name="VPERMT2W" form="zmm {z}, zmm, zmm" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	off := 16*idx[i+4:i]
+ 	dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="zmm, zmm, zmm" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<instruction name="VPERMT2W" form="zmm, zmm, zmm" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask2_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+2:i]
+ 		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := idx[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="xmm {k}, xmm, xmm" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+2:i]
+ 		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := a[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2W" form="xmm {k}, xmm, xmm" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		off := 16*idx[i+2:i]
+ 		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="xmm {z}, xmm, xmm" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<instruction name="VPERMT2W" form="xmm {z}, xmm, xmm" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_permutex2var_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	off := 16*idx[i+2:i]
+ 	dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2W" form="xmm, xmm, xmm" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<instruction name="VPERMT2W" form="xmm, xmm, xmm" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	id := idx[i+3:i]*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[id+15:id]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="ymm {k}, ymm, ymm" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	id := idx[i+3:i]*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[id+15:id]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="ymm {z}, ymm, ymm" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	id := idx[i+3:i]*16
+ 	dst[i+15:i] := a[id+15:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="ymm, ymm, ymm" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	id := idx[i+4:i]*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[id+15:id]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="zmm {k}, zmm, zmm" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	id := idx[i+4:i]*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[id+15:id]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="zmm {z}, zmm, zmm" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	id := idx[i+4:i]*16
+ 	dst[i+15:i] := a[id+15:id]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="zmm, zmm, zmm" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	id := idx[i+2:i]*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[id+15:id]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="xmm {k}, xmm, xmm" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	id := idx[i+2:i]*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[id+15:id]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="xmm {z}, xmm, xmm" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_permutexvar_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	id := idx[i+2:i]*16
+ 	dst[i+15:i] := a[id+15:id]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMW" form="xmm, xmm, xmm" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="ymm {k}, ymm, ymm" xed="VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="ymm {z}, ymm, ymm" xed="VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="zmm, zmm, zmm" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m512i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="zmm {k}, zmm, zmm" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="zmm {z}, zmm, zmm" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="xmm {k}, xmm, xmm" xed="VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_maddubs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMADDUBSW" form="xmm {z}, xmm, xmm" xed="VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m256i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="ymm {k}, ymm, ymm" xed="VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="ymm {z}, ymm, ymm" xed="VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="zmm, zmm, zmm" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m512i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="zmm {k}, zmm, zmm" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="zmm {z}, zmm, zmm" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="xmm {k}, xmm, xmm" xed="VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_madd_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMADDWD" form="xmm {z}, xmm, xmm" xed="VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="ymm {k}, ymm, ymm" xed="VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="ymm {z}, ymm, ymm" xed="VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="zmm {k}, zmm, zmm" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="zmm {z}, zmm, zmm" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="zmm, zmm, zmm" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="xmm {k}, xmm, xmm" xed="VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSB" form="xmm {z}, xmm, xmm" xed="VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="ymm {k}, ymm, ymm" xed="VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="ymm {z}, ymm, ymm" xed="VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="zmm {k}, zmm, zmm" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="zmm {z}, zmm, zmm" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="zmm, zmm, zmm" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="xmm {k}, xmm, xmm" xed="VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSW" form="xmm {z}, xmm, xmm" xed="VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="ymm {k}, ymm, ymm" xed="VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="ymm {z}, ymm, ymm" xed="VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="zmm {k}, zmm, zmm" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="zmm {z}, zmm, zmm" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="zmm, zmm, zmm" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="xmm {k}, xmm, xmm" xed="VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUB" form="xmm {z}, xmm, xmm" xed="VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="ymm {k}, ymm, ymm" xed="VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="ymm {z}, ymm, ymm" xed="VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="zmm {k}, zmm, zmm" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="zmm {z}, zmm, zmm" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="zmm, zmm, zmm" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="xmm {k}, xmm, xmm" xed="VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUW" form="xmm {z}, xmm, xmm" xed="VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="ymm {k}, ymm, ymm" xed="VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="ymm {z}, ymm, ymm" xed="VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="zmm {k}, zmm, zmm" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="zmm {z}, zmm, zmm" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="zmm, zmm, zmm" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="xmm {k}, xmm, xmm" xed="VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSB" form="xmm {z}, xmm, xmm" xed="VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="ymm {k}, ymm, ymm" xed="VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="ymm {z}, ymm, ymm" xed="VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="zmm {k}, zmm, zmm" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="zmm {z}, zmm, zmm" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="zmm, zmm, zmm" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="xmm {k}, xmm, xmm" xed="VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSW" form="xmm {z}, xmm, xmm" xed="VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="ymm {k}, ymm, ymm" xed="VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="ymm {z}, ymm, ymm" xed="VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="zmm {k}, zmm, zmm" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="zmm {z}, zmm, zmm" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="zmm, zmm, zmm" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="xmm {k}, xmm, xmm" xed="VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUB" form="xmm {z}, xmm, xmm" xed="VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="ymm {k}, ymm, ymm" xed="VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="ymm {z}, ymm, ymm" xed="VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="zmm {k}, zmm, zmm" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="zmm {z}, zmm, zmm" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="zmm, zmm, zmm" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="xmm {k}, xmm, xmm" xed="VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUW" form="xmm {z}, xmm, xmm" xed="VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movepi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF a[i+7]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVB2M" form="k, ymm" xed="VPMOVB2M_MASKmskw_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movepi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF a[i+7]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVB2M" form="k, zmm" xed="VPMOVB2M_MASKmskw_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movepi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF a[i+7]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVB2M" form="k, xmm" xed="VPMOVB2M_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movm_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := 0xFF
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2B" form="ymm" xed="VPMOVM2B_YMMu8_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movm_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := 0xFF
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2B" form="zmm" xed="VPMOVM2B_ZMMu8_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movm_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := 0xFF
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2B" form="xmm" xed="VPMOVM2B_XMMu8_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movm_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := 0xFFFF
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2W" form="ymm" xed="VPMOVM2W_YMMu16_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movm_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := 0xFFFF
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2W" form="zmm" xed="VPMOVM2W_ZMMu16_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movm_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := 0xFFFF
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2W" form="xmm" xed="VPMOVM2W_XMMu16_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := Saturate8(a[i+15:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="xmm, ymm" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="SI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="xmm {k}, ymm" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="128"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="m128 {k}, ymm" xed="VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="xmm {z}, ymm" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := Saturate8(a[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="ymm, zmm" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m256i" varname="src" etype="SI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="ymm {k}, zmm" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtsepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="256"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="m256 {k}, zmm" xed="VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="ymm {z}, zmm" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := Saturate8(a[i+15:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="xmm, xmm" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="SI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="xmm {k}, xmm" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="m64 {k}, xmm" xed="VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtsepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSWB" form="xmm {z}, xmm" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := SignExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="ymm {k}, xmm" xed="VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := SignExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="ymm {z}, xmm" xed="VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	l := j*16
+ 	dst[l+15:l] := SignExtend16(a[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="zmm, ymm" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m512i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := SignExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="zmm {k}, ymm" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := SignExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="zmm {z}, ymm" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := SignExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="xmm {k}, xmm" xed="VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := SignExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBW" form="xmm {z}, xmm" xed="VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := SaturateU8(a[i+15:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="xmm, ymm" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="xmm {k}, ymm" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="128"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="m128 {k}, ymm" xed="VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="xmm {z}, ymm" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := SaturateU8(a[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="ymm, zmm" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="ymm {k}, zmm" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtusepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="256"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="m256 {k}, zmm" xed="VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="ymm {z}, zmm" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := SaturateU8(a[i+15:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="xmm, xmm" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="xmm {k}, xmm" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="m64 {k}, xmm" xed="VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtusepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSWB" form="xmm {z}, xmm" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movepi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF a[i+15]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVW2M" form="k, ymm" xed="VPMOVW2M_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movepi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF a[i+15]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVW2M" form="k, zmm" xed="VPMOVW2M_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movepi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF a[i+15]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPMOVW2M" form="k, xmm" xed="VPMOVW2M_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := Truncate8(a[i+15:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="xmm, ymm" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="xmm {k}, ymm" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="128"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="m128 {k}, ymm" xed="VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="xmm {z}, ymm" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := Truncate8(a[i+15:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="ymm, zmm" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="ymm {k}, zmm" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="256"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="m256 {k}, zmm" xed="VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="ymm {z}, zmm" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	dst[l+7:l] := Truncate8(a[i+15:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="xmm, xmm" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="xmm {k}, xmm" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi16_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="m64 {k}, xmm" xed="VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi16_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+15:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVWB" form="xmm {z}, xmm" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="ymm {k}, xmm" xed="VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="ymm {z}, xmm" xed="VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	l := j*16
+ 	dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="zmm, ymm" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="zmm {k}, ymm" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="zmm {z}, ymm" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="xmm {k}, xmm" xed="VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu8_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*8
+ 	l := j*16
+ 	IF k[j]
+ 		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBW" form="xmm {z}, xmm" xed="VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 		dst[i+15:i] := tmp[16:1]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="ymm {k}, ymm, ymm" xed="VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 		dst[i+15:i] := tmp[16:1]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="ymm {z}, ymm, ymm" xed="VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 		dst[i+15:i] := tmp[16:1]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="zmm {k}, zmm, zmm" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 		dst[i+15:i] := tmp[16:1]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="zmm {z}, zmm, zmm" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 	dst[i+15:i] := tmp[16:1]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="zmm, zmm, zmm" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 		dst[i+15:i] := tmp[16:1]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="xmm {k}, xmm, xmm" xed="VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mulhrs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+ 		dst[i+15:i] := tmp[16:1]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULHRSW" form="xmm {z}, xmm, xmm" xed="VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="ymm {k}, ymm, ymm" xed="VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="ymm {z}, ymm, ymm" xed="VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="zmm {k}, zmm, zmm" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="zmm {z}, zmm, zmm" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 	dst[i+15:i] := tmp[31:16]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="zmm, zmm, zmm" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="xmm {k}, xmm, xmm" xed="VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mulhi_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := a[i+15:i] * b[i+15:i]
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULHUW" form="xmm {z}, xmm, xmm" xed="VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="ymm {k}, ymm, ymm" xed="VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="ymm {z}, ymm, ymm" xed="VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="zmm {k}, zmm, zmm" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="zmm {z}, zmm, zmm" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 	dst[i+15:i] := tmp[31:16]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="zmm, zmm, zmm" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="xmm {k}, xmm, xmm" xed="VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mulhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[31:16]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULHW" form="xmm {z}, xmm, xmm" xed="VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="ymm {k}, ymm, ymm" xed="VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="ymm {z}, ymm, ymm" xed="VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="zmm {k}, zmm, zmm" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="zmm {z}, zmm, zmm" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 	dst[i+15:i] := tmp[15:0]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="zmm, zmm, zmm" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[15:0]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="xmm {k}, xmm, xmm" xed="VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mullo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+ 		dst[i+15:i] := tmp[15:0]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLW" form="xmm {z}, xmm, xmm" xed="VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_sad_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce eight unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ ENDFOR
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
+ 	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
+ 	dst[i+63:i+16] := 0
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSADBW" form="zmm, zmm, zmm" xed="VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		IF b[i+7] == 1
+ 			dst[i+7:i] := 0
+ 		ELSE
+ 			index[4:0] := b[i+3:i] + (j &amp; 0x10)
+ 			dst[i+7:i] := a[index*8+7:index*8]
+ 		FI
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="ymm {k}, ymm, ymm" xed="VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		IF b[i+7] == 1
+ 			dst[i+7:i] := 0
+ 		ELSE
+ 			index[4:0] := b[i+3:i] + (j &amp; 0x10)
+ 			dst[i+7:i] := a[index*8+7:index*8]
+ 		FI
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="ymm {z}, ymm, ymm" xed="VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Shuffle 8-bit integers in "a" within 128-bit lanes using the control in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		IF b[i+7] == 1
+ 			dst[i+7:i] := 0
+ 		ELSE
+ 			index[5:0] := b[i+3:i] + (j &amp; 0x30)
+ 			dst[i+7:i] := a[index*8+7:index*8]
+ 		FI
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="zmm {k}, zmm, zmm" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		IF b[i+7] == 1
+ 			dst[i+7:i] := 0
+ 		ELSE
+ 			index[5:0] := b[i+3:i] + (j &amp; 0x30)
+ 			dst[i+7:i] := a[index*8+7:index*8]
+ 		FI
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="zmm {z}, zmm, zmm" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF b[i+7] == 1
+ 		dst[i+7:i] := 0
+ 	ELSE
+ 		index[5:0] := b[i+3:i] + (j &amp; 0x30)
+ 		dst[i+7:i] := a[index*8+7:index*8]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="zmm, zmm, zmm" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		IF b[i+7] == 1
+ 			dst[i+7:i] := 0
+ 		ELSE
+ 			index[3:0] := b[i+3:i]
+ 			dst[i+7:i] := a[index*8+7:index*8]
+ 		FI
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="xmm {k}, xmm, xmm" xed="VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_shuffle_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		IF b[i+7] == 1
+ 			dst[i+7:i] := 0
+ 		ELSE
+ 			index[3:0] := b[i+3:i]
+ 			dst[i+7:i] := a[index*8+7:index*8]
+ 		FI
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFB" form="xmm {z}, xmm, xmm" xed="VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := a[63:0]
+ tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ tmp_dst[191:128] := a[191:128]
+ tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+ tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+ tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+ tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="ymm {k}, ymm, imm8" xed="VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := a[63:0]
+ tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ tmp_dst[191:128] := a[191:128]
+ tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+ tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+ tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+ tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="ymm {z}, ymm, imm8" xed="VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := a[63:0]
+ tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ tmp_dst[191:128] := a[191:128]
+ tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+ tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+ tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+ tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+ tmp_dst[319:256] := a[319:256]
+ tmp_dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
+ tmp_dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
+ tmp_dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
+ tmp_dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
+ tmp_dst[447:384] := a[447:384]
+ tmp_dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
+ tmp_dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
+ tmp_dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
+ tmp_dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="zmm {k}, zmm, imm8" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := a[63:0]
+ tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ tmp_dst[191:128] := a[191:128]
+ tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+ tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+ tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+ tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+ tmp_dst[319:256] := a[319:256]
+ tmp_dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
+ tmp_dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
+ tmp_dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
+ tmp_dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
+ tmp_dst[447:384] := a[447:384]
+ tmp_dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
+ tmp_dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
+ tmp_dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
+ tmp_dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="zmm {z}, zmm, imm8" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+ 	<operation>
+ dst[63:0] := a[63:0]
+ dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ dst[191:128] := a[191:128]
+ dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+ dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+ dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+ dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+ dst[319:256] := a[319:256]
+ dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
+ dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
+ dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
+ dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
+ dst[447:384] := a[447:384]
+ dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
+ dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
+ dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
+ dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="zmm, zmm, imm8" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := a[63:0]
+ tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="xmm {k}, xmm, imm8" xed="VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_shufflehi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := a[63:0]
+ tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+ tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+ tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+ tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFHW" form="xmm {z}, xmm, imm8" xed="VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ tmp_dst[127:64] := a[127:64]
+ tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+ tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+ tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+ tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+ tmp_dst[255:192] := a[255:192]
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="ymm {k}, ymm, imm8" xed="VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ tmp_dst[127:64] := a[127:64]
+ tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+ tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+ tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+ tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+ tmp_dst[255:192] := a[255:192]
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="ymm {z}, ymm, imm8" xed="VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ tmp_dst[127:64] := a[127:64]
+ tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+ tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+ tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+ tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+ tmp_dst[255:192] := a[255:192]
+ tmp_dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
+ tmp_dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
+ tmp_dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
+ tmp_dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
+ tmp_dst[383:320] := a[383:320]
+ tmp_dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
+ tmp_dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
+ tmp_dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
+ tmp_dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
+ tmp_dst[511:448] := a[511:448]
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="zmm {k}, zmm, imm8" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ tmp_dst[127:64] := a[127:64]
+ tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+ tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+ tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+ tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+ tmp_dst[255:192] := a[255:192]
+ tmp_dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
+ tmp_dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
+ tmp_dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
+ tmp_dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
+ tmp_dst[383:320] := a[383:320]
+ tmp_dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
+ tmp_dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
+ tmp_dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
+ tmp_dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
+ tmp_dst[511:448] := a[511:448]
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="zmm {z}, zmm, imm8" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+ 	<operation>
+ dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ dst[127:64] := a[127:64]
+ dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+ dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+ dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+ dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+ dst[255:192] := a[255:192]
+ dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
+ dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
+ dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
+ dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
+ dst[383:320] := a[383:320]
+ dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
+ dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
+ dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
+ dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
+ dst[511:448] := a[511:448]
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="zmm, zmm, imm8" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ tmp_dst[127:64] := a[127:64]
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="xmm {k}, xmm, imm8" xed="VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_shufflelo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+ tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+ tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+ tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+ tmp_dst[127:64] := a[127:64]
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFLW" form="xmm {z}, xmm, imm8" xed="VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_bslli_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="M128"/>
+ 	<parameter type="__m512i" varname="a" etype="M128"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ tmp := imm8[7:0]
+ IF tmp &gt; 15
+ 	tmp := 16
+ FI
+ dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+ dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
+ dst[383:256] := a[383:256] &lt;&lt; (tmp*8)
+ dst[511:384] := a[511:384] &lt;&lt; (tmp*8)
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLDQ" form="zmm, zmm, imm8" xed="VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="ymm {k}, ymm, ymm" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="ymm {z}, ymm, ymm" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="ymm, ymm, ymm" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="zmm {k}, zmm, zmm" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="zmm {z}, zmm, zmm" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="zmm, zmm, zmm" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="xmm {k}, xmm, xmm" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="xmm {z}, xmm, xmm" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_sllv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVW" form="xmm, xmm, xmm" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="ymm {k}, ymm, xmm" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="ymm {k}, ymm, imm8" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="ymm {z}, ymm, xmm" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="ymm {z}, ymm, imm8" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="zmm {k}, zmm, xmm" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="zmm {k}, zmm, imm8" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="zmm {z}, zmm, xmm" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="zmm {z}, zmm, imm8" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF count[63:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="zmm, zmm, xmm" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF imm8[7:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="zmm, zmm, imm8" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="xmm {k}, xmm, xmm" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="xmm {k}, xmm, imm8" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sll_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="xmm {z}, xmm, xmm" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_slli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLW" form="xmm {z}, xmm, imm8" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="ymm {k}, ymm, ymm" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="ymm {z}, ymm, ymm" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="ymm, ymm, ymm" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="zmm {k}, zmm, zmm" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="zmm {z}, zmm, zmm" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="zmm, zmm, zmm" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="xmm {k}, xmm, xmm" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="xmm {z}, xmm, xmm" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_srav_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVW" form="xmm, xmm, xmm" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="ymm {k}, ymm, xmm" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="ymm {k}, ymm, imm8" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="ymm {z}, ymm, xmm" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="ymm {z}, ymm, imm8" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="zmm {k}, zmm, xmm" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="zmm {k}, zmm, imm8" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="zmm {z}, zmm, xmm" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="zmm {z}, zmm, imm8" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF count[63:0] &gt; 15
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 	ELSE
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="zmm, zmm, xmm" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF imm8[7:0] &gt; 15
+ 		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 	ELSE
+ 		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="zmm, zmm, imm8" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="xmm {k}, xmm, xmm" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="xmm {k}, xmm, imm8" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sra_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="xmm {z}, xmm, xmm" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srai_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+ 		ELSE
+ 			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAW" form="xmm {z}, xmm, imm8" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_bsrli_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="M128"/>
+ 	<parameter type="__m512i" varname="a" etype="M128"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ tmp := imm8[7:0]
+ IF tmp &gt; 15
+ 	tmp := 16
+ FI
+ dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+ dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
+ dst[383:256] := a[383:256] &gt;&gt; (tmp*8)
+ dst[511:384] := a[511:384] &gt;&gt; (tmp*8)
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLDQ" form="zmm, zmm, imm8" xed="VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="ymm {k}, ymm, ymm" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="ymm {z}, ymm, ymm" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="ymm, ymm, ymm" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="zmm {k}, zmm, zmm" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="zmm {z}, zmm, zmm" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="zmm, zmm, zmm" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="xmm {k}, xmm, xmm" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[i+15:i] &lt; 16
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 		ELSE
+ 			dst[i+15:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="xmm {z}, xmm, xmm" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_srlv_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF count[i+15:i] &lt; 16
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVW" form="xmm, xmm, xmm" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="ymm {k}, ymm, xmm" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="ymm {k}, ymm, imm8" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="ymm {z}, ymm, xmm" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="ymm {z}, ymm, imm8" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="zmm {k}, zmm, xmm" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="zmm {k}, zmm, imm8" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="zmm {z}, zmm, xmm" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="zmm {z}, zmm, imm8" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF count[63:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="zmm, zmm, xmm" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF imm8[7:0] &gt; 15
+ 		dst[i+15:i] := 0
+ 	ELSE
+ 		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="zmm, zmm, imm8" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="xmm {k}, xmm, xmm" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="xmm {k}, xmm, imm8" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srl_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="count" etype="UI16"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF count[63:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="xmm {z}, xmm, xmm" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srli_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 15
+ 			dst[i+15:i] := 0
+ 		ELSE
+ 			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLW" form="xmm {z}, xmm, imm8" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="ymm {k}, ymm, ymm" xed="VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="ymm {z}, ymm, ymm" xed="VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="zmm {k}, zmm, zmm" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="zmm {z}, zmm, zmm" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="zmm, zmm, zmm" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="xmm {k}, xmm, xmm" xed="VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sub_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBB" form="xmm {z}, xmm, xmm" xed="VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="ymm {k}, ymm, ymm" xed="VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI8"/>
+ 	<parameter type="__m256i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="ymm {z}, ymm, ymm" xed="VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="zmm {k}, zmm, zmm" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="zmm {z}, zmm, zmm" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="SI8"/>
+ 	<parameter type="__m512i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="zmm, zmm, zmm" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="xmm {k}, xmm, xmm" xed="VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_subs_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<parameter type="__m128i" varname="b" etype="SI8"/>
+ 	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSB" form="xmm {z}, xmm, xmm" xed="VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="ymm {k}, ymm, ymm" xed="VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI16"/>
+ 	<parameter type="__m256i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="ymm {z}, ymm, ymm" xed="VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="zmm {k}, zmm, zmm" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="zmm {z}, zmm, zmm" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="SI16"/>
+ 	<parameter type="__m512i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="zmm, zmm, zmm" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="xmm {k}, xmm, xmm" xed="VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_subs_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<parameter type="__m128i" varname="b" etype="SI16"/>
+ 	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBSW" form="xmm {z}, xmm, xmm" xed="VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="ymm {k}, ymm, ymm" xed="VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="ymm {z}, ymm, ymm" xed="VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="zmm {k}, zmm, zmm" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="zmm {z}, zmm, zmm" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="zmm, zmm, zmm" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="xmm {k}, xmm, xmm" xed="VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_subs_epu8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSB" form="xmm {z}, xmm, xmm" xed="VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="ymm {k}, ymm, ymm" xed="VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="ymm {z}, ymm, ymm" xed="VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="zmm {k}, zmm, zmm" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="zmm {z}, zmm, zmm" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="zmm, zmm, zmm" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="xmm {k}, xmm, xmm" xed="VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_subs_epu16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBUSW" form="xmm {z}, xmm, xmm" xed="VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="ymm {k}, ymm, ymm" xed="VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="ymm {z}, ymm, ymm" xed="VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="zmm {k}, zmm, zmm" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="zmm {z}, zmm, zmm" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="zmm, zmm, zmm" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="xmm {k}, xmm, xmm" xed="VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sub_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBW" form="xmm {z}, xmm, xmm" xed="VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_test_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMB" form="k {k}, ymm, ymm" xed="VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_test_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMB" form="k, ymm, ymm" xed="VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_test_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMB" form="k {k}, zmm, zmm" xed="VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_test_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMB" form="k, zmm, zmm" xed="VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_test_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMB" form="k {k}, xmm, xmm" xed="VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_test_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMB" form="k, xmm, xmm" xed="VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_test_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMW" form="k {k}, ymm, ymm" xed="VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_test_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMW" form="k, ymm, ymm" xed="VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_test_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMW" form="k {k}, zmm, zmm" xed="VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_test_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMW" form="k, zmm, zmm" xed="VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_test_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMW" form="k {k}, xmm, xmm" xed="VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_test_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMW" form="k, xmm, xmm" xed="VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_testn_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMB" form="k {k}, ymm, ymm" xed="VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_testn_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*8
+ 	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMB" form="k, ymm, ymm" xed="VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_testn_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMB" form="k {k}, zmm, zmm" xed="VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_testn_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 63
+ 	i := j*8
+ 	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMB" form="k, zmm, zmm" xed="VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_testn_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k1[j]
+ 		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMB" form="k {k}, xmm, xmm" xed="VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_testn_epi8_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*8
+ 	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMB" form="k, xmm, xmm" xed="VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_testn_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMW" form="k {k}, ymm, ymm" xed="VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_testn_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*16
+ 	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMW" form="k, ymm, ymm" xed="VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_testn_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMW" form="k {k}, zmm, zmm" xed="VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_testn_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 31
+ 	i := j*16
+ 	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMW" form="k, zmm, zmm" xed="VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_testn_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k1[j]
+ 		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMW" form="k {k}, xmm, xmm" xed="VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_testn_epi16_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*16
+ 	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMW" form="k, xmm, xmm" xed="VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="ymm {k}, ymm, ymm" xed="VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="ymm {z}, ymm, ymm" xed="VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="zmm {k}, zmm, zmm" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="zmm {z}, zmm, zmm" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+ dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
+ dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="zmm, zmm, zmm" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="xmm {k}, xmm, xmm" xed="VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpackhi_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[71:64] 
+ 	dst[15:8] := src2[71:64] 
+ 	dst[23:16] := src1[79:72] 
+ 	dst[31:24] := src2[79:72] 
+ 	dst[39:32] := src1[87:80] 
+ 	dst[47:40] := src2[87:80] 
+ 	dst[55:48] := src1[95:88] 
+ 	dst[63:56] := src2[95:88] 
+ 	dst[71:64] := src1[103:96] 
+ 	dst[79:72] := src2[103:96] 
+ 	dst[87:80] := src1[111:104] 
+ 	dst[95:88] := src2[111:104] 
+ 	dst[103:96] := src1[119:112] 
+ 	dst[111:104] := src2[119:112] 
+ 	dst[119:112] := src1[127:120] 
+ 	dst[127:120] := src2[127:120] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHBW" form="xmm {z}, xmm, xmm" xed="VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="ymm {k}, ymm, ymm" xed="VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="ymm {z}, ymm, ymm" xed="VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="zmm {k}, zmm, zmm" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="zmm {z}, zmm, zmm" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+ dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
+ dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="zmm, zmm, zmm" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="xmm {k}, xmm, xmm" xed="VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpackhi_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[79:64]
+ 	dst[31:16] := src2[79:64] 
+ 	dst[47:32] := src1[95:80] 
+ 	dst[63:48] := src2[95:80] 
+ 	dst[79:64] := src1[111:96] 
+ 	dst[95:80] := src2[111:96] 
+ 	dst[111:96] := src1[127:112] 
+ 	dst[127:112] := src2[127:112] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHWD" form="xmm {z}, xmm, xmm" xed="VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="ymm {k}, ymm, ymm" xed="VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<parameter type="__m256i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+ FOR j := 0 to 31
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="ymm {z}, ymm, ymm" xed="VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="zmm {k}, zmm, zmm" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
+ FOR j := 0 to 63
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="zmm {z}, zmm, zmm" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<parameter type="__m512i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+ dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
+ dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="zmm, zmm, zmm" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := src[i+7:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="xmm {k}, xmm, xmm" xed="VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpacklo_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<parameter type="__m128i" varname="b" etype="UI8"/>
+ 	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+ 	dst[7:0] := src1[7:0] 
+ 	dst[15:8] := src2[7:0] 
+ 	dst[23:16] := src1[15:8] 
+ 	dst[31:24] := src2[15:8] 
+ 	dst[39:32] := src1[23:16] 
+ 	dst[47:40] := src2[23:16] 
+ 	dst[55:48] := src1[31:24] 
+ 	dst[63:56] := src2[31:24] 
+ 	dst[71:64] := src1[39:32]
+ 	dst[79:72] := src2[39:32] 
+ 	dst[87:80] := src1[47:40] 
+ 	dst[95:88] := src2[47:40] 
+ 	dst[103:96] := src1[55:48] 
+ 	dst[111:104] := src2[55:48] 
+ 	dst[119:112] := src1[63:56] 
+ 	dst[127:120] := src2[63:56] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+ FOR j := 0 to 15
+ 	i := j*8
+ 	IF k[j]
+ 		dst[i+7:i] := tmp_dst[i+7:i]
+ 	ELSE
+ 		dst[i+7:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLBW" form="xmm {z}, xmm, xmm" xed="VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="ymm {k}, ymm, ymm" xed="VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<parameter type="__m256i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+ FOR j := 0 to 15
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="ymm {z}, ymm, ymm" xed="VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="zmm {k}, zmm, zmm" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+ tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
+ tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
+ FOR j := 0 to 31
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="zmm {z}, zmm, zmm" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<parameter type="__m512i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+ dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
+ dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="zmm, zmm, zmm" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="xmm {k}, xmm, xmm" xed="VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpacklo_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<parameter type="__m128i" varname="b" etype="UI16"/>
+ 	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+ 	dst[15:0] := src1[15:0] 
+ 	dst[31:16] := src2[15:0] 
+ 	dst[47:32] := src1[31:16] 
+ 	dst[63:48] := src2[31:16] 
+ 	dst[79:64] := src1[47:32] 
+ 	dst[95:80] := src2[47:32] 
+ 	dst[111:96] := src1[63:48] 
+ 	dst[127:112] := src2[63:48] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+ FOR j := 0 to 7
+ 	i := j*16
+ 	IF k[j]
+ 		dst[i+15:i] := tmp_dst[i+15:i]
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLWD" form="xmm {z}, xmm, xmm" xed="VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI16" memwidth="512"/>
+ 	<parameter type="__m512i" varname="a" etype="UI16"/>
+ 	<description>Store 512-bits (composed of 32 packed 16-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+511:mem_addr] := a[511:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="m512, zmm" xed="VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI8" memwidth="512"/>
+ 	<parameter type="__m512i" varname="a" etype="UI8"/>
+ 	<description>Store 512-bits (composed of 64 packed 8-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+511:mem_addr] := a[511:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="m512, zmm" xed="VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI16" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI16"/>
+ 	<description>Store 256-bits (composed of 16 packed 16-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="m256, ymm" xed="VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI8" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI8"/>
+ 	<description>Store 256-bits (composed of 32 packed 8-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="m256, ymm" xed="VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI16" memwidth="128"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Store 128-bits (composed of 8 packed 16-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+127:mem_addr] := a[127:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="m128, xmm" xed="VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI8" memwidth="128"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Store 128-bits (composed of 16 packed 8-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+127:mem_addr] := a[127:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="m128, xmm" xed="VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI16"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="512"/>
+ 	<description>Load 512-bits (composed of 32 packed 16-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[511:0] := MEM[mem_addr+511:mem_addr]
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="zmm, m512" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI8"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="512"/>
+ 	<description>Load 512-bits (composed of 64 packed 8-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[511:0] := MEM[mem_addr+511:mem_addr]
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="zmm, m512" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI16"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 16 packed 16-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="ymm, m256" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI8"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 32 packed 8-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="ymm, m256" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_loadu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI16" memwidth="128"/>
+ 	<description>Load 128-bits (composed of 8 packed 16-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU16" form="xmm, m128" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_loadu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI8" memwidth="128"/>
+ 	<description>Load 128-bits (composed of 16 packed 8-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU8" form="xmm, m128" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kadd_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Add 32-bit masks in "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := a[31:0] + b[31:0]
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KADDD" form="k, k, k" xed="KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kadd_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Add 64-bit masks in "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := a[63:0] + b[63:0]
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KADDQ" form="k, k, k" xed="KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kand_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := a[31:0] AND b[31:0]
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KANDD" form="k, k, k" xed="KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kand_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := a[63:0] AND b[63:0]
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KANDQ" form="k, k, k" xed="KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kandn_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 32-bit masks "a" and then AND with "b", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := (NOT a[31:0]) AND b[31:0]
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KANDND" form="k, k, k" xed="KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kandn_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 64-bit masks "a" and then AND with "b", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := (NOT a[63:0]) AND b[63:0]
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KANDNQ" form="k, k, k" xed="KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_knot_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 32-bit mask "a", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := NOT a[31:0]
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KNOTD" form="k, k" xed="KNOTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_knot_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 64-bit mask "a", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := NOT a[63:0]
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KNOTQ" form="k, k" xed="KNOTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kor_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 32-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := a[31:0] OR b[31:0]
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KORD" form="k, k, k" xed="KORD_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kor_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 64-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := a[63:0] OR b[63:0]
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KORQ" form="k, k, k" xed="KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxnor_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XNOR of 32-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := NOT (a[31:0] XOR b[31:0])
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KXNORD" form="k, k, k" xed="KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxnor_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XNOR of 64-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := NOT (a[63:0] XOR b[63:0])
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KXNORQ" form="k, k, k" xed="KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxor_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XOR of 32-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[31:0] := a[31:0] XOR b[31:0]
+ k[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="KXORD" form="k, k, k" xed="KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxor_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XOR of 64-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[63:0] := a[63:0] XOR b[63:0]
+ k[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="KXORQ" form="k, k, k" xed="KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftli_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 32-bit mask "a" left by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 31
+ 	k[31:0] := a[31:0] &lt;&lt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTLD" form="k, k, imm8" xed="KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftli_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 64-bit mask "a" left by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 63
+ 	k[63:0] := a[63:0] &lt;&lt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTLQ" form="k, k, imm8" xed="KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftri_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 32-bit mask "a" right by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 31
+ 	k[31:0] := a[31:0] &gt;&gt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTRD" form="k, k, imm8" xed="KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftri_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 64-bit mask "a" right by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 63
+ 	k[63:0] := a[63:0] &gt;&gt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTRQ" form="k, k, imm8" xed="KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_load_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask32*" varname="mem_addr" etype="MASK" memwidth="32"/>
+ 	<description>Load 32-bit mask from memory into "k".</description>
+ 	<operation>
+ k[31:0] := MEM[mem_addr+31:mem_addr]
+ 	</operation>
+ 	<instruction name="KMOVD" form="k, m32" xed="KMOVD_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_load_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Load</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask64*" varname="mem_addr" etype="MASK" memwidth="64"/>
+ 	<description>Load 64-bit mask from memory into "k".</description>
+ 	<operation>
+ k[63:0] := MEM[mem_addr+63:mem_addr]
+ 	</operation>
+ 	<instruction name="KMOVQ" form="k, m64" xed="KMOVQ_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_store_mask32">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__mmask32*" varname="mem_addr" etype="MASK" memwidth="32"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<description>Store 32-bit mask from "a" into memory.</description>
+ 	<operation>
+ MEM[mem_addr+31:mem_addr] := a[31:0]
+ 	</operation>
+ 	<instruction name="KMOVD" form="m32, k" xed="KMOVD_MEMu32_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_store_mask64">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__mmask64*" varname="mem_addr" etype="MASK" memwidth="64"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<description>Store 64-bit mask from "a" into memory.</description>
+ 	<operation>
+ MEM[mem_addr+63:mem_addr] := a[63:0]
+ 	</operation>
+ 	<instruction name="KMOVQ" form="m64, k" xed="KMOVQ_MEMu64_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortest_mask32_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="all_ones" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] OR b[31:0]
+ IF tmp[31:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ IF tmp[31:0] == 0xFFFFFFFF
+ 	MEM[all_ones+7:all_ones] := 1
+ ELSE
+ 	MEM[all_ones+7:all_ones] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTD" form="k, k" xed="KORTESTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortestz_mask32_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] OR b[31:0]
+ IF tmp[31:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTD" form="k, k" xed="KORTESTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortestc_mask32_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] OR b[31:0]
+ IF tmp[31:0] == 0xFFFFFFFF
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTD" form="k, k" xed="KORTESTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortest_mask64_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="all_ones" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+ 	<operation>
+ tmp[63:0] := a[63:0] OR b[63:0]
+ IF tmp[63:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ IF tmp[7:0] == 0xFFFFFFFFFFFFFFFF
+ 	MEM[all_ones+7:all_ones] := 1
+ ELSE
+ 	MEM[all_ones+7:all_ones] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTQ" form="k, k" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortestz_mask64_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[63:0] := a[63:0] OR b[63:0]
+ IF tmp[63:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTQ" form="k, k" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortestc_mask64_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[63:0] := a[63:0] OR b[63:0]
+ IF tmp[63:0] == 0xFFFFFFFFFFFFFFFF
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTQ" form="k, k" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktest_mask32_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="and_not" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+ 	<operation>
+ tmp1[31:0] := a[31:0] AND b[31:0]
+ IF tmp1[31:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ tmp2[31:0] := (NOT a[31:0]) AND b[31:0]
+ IF tmp2[31:0] == 0x0
+ 	MEM[and_not+7:and_not] := 1
+ ELSE
+ 	MEM[and_not+7:and_not] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTD" form="k, k" xed="KTESTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestz_mask32_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] AND b[31:0]
+ IF tmp[31:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTD" form="k, k" xed="KTESTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestc_mask32_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask32" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 32-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[31:0] := (NOT a[31:0]) AND b[31:0]
+ IF tmp[31:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTD" form="k, k" xed="KTESTD_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktest_mask64_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="and_not" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+ 	<operation>
+ tmp1[63:0] := a[63:0] AND b[63:0]
+ IF tmp1[63:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ tmp2[63:0] := (NOT a[63:0]) AND b[63:0]
+ IF tmp2[63:0] == 0x0
+ 	MEM[and_not+7:and_not] := 1
+ ELSE
+ 	MEM[and_not+7:and_not] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTQ" form="k, k" xed="KTESTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestz_mask64_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[63:0] := a[63:0] AND b[63:0]
+ IF tmp[63:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTQ" form="k, k" xed="KTESTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestc_mask64_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask64" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 64-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[63:0] := (NOT a[63:0]) AND b[63:0]
+ IF tmp[63:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTQ" form="k, k" xed="KTESTQ_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_cvtmask32_u32">
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned int" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask32" varname="a" etype="MASK"/>
+ 	<description>Convert 32-bit mask "a" into an integer value, and store the result in "dst".</description>
+ 	<operation>
+ dst := ZeroExtend32(a[31:0])
+ 	</operation>
+ 	<instruction name="KMOVD" form="r32, k" xed="KMOVD_GPR32u32_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_cvtmask64_u64">
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned __int64" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask64" varname="a" etype="MASK"/>
+ 	<description>Convert 64-bit mask "a" into an integer value, and store the result in "dst".</description>
+ 	<operation>
+ dst := ZeroExtend64(a[63:0])
+ 	</operation>
+ 	<instruction name="KMOVQ" form="r64, k" xed="KMOVQ_GPR64u64_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_cvtu32_mask32">
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask32" varname="k" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="a" etype="UI32"/>
+ 	<description>Convert integer value "a" into an 32-bit mask, and store the result in "k".</description>
+ 	<operation>
+ k := ZeroExtend32(a[31:0])
+ 	</operation>
+ 	<instruction name="KMOVD" form="k, r32" xed="KMOVD_MASKmskw_GPR32u32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_cvtu64_mask64">
+ 	<CPUID>AVX512BW</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask64" varname="k" etype="MASK"/>
+ 	<parameter type="unsigned __int64" varname="a" etype="UI64"/>
+ 	<description>Convert integer value "a" into an 64-bit mask, and store the result in "k".</description>
+ 	<operation>
+ k := ZeroExtend64(a[63:0])
+ 	</operation>
+ 	<instruction name="KMOVQ" form="k, r64" xed="KMOVQ_MASKmskw_GPR64u64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_broadcastmb_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ZeroExtend64(k[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTMB2Q" form="ymm" xed="VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_broadcastmb_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := ZeroExtend64(k[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTMB2Q" form="xmm" xed="VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_broadcastmw_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ZeroExtend32(k[15:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTMW2D" form="ymm" xed="VPBROADCASTMW2D_YMMu32_MASKu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_broadcastmw_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := ZeroExtend32(k[15:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTMW2D" form="xmm" xed="VPBROADCASTMW2D_XMMu32_MASKu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	FOR k := 0 to j-1
+ 		m := k*32
+ 		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 	ENDFOR
+ 	dst[i+31:i+j] := 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="ymm, ymm" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*32
+ 			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+31:i+j] := 0
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="ymm {k}, ymm" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*32
+ 			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+31:i+j] := 0
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="ymm {z}, ymm" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	FOR k := 0 to j-1
+ 		m := k*32
+ 		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 	ENDFOR
+ 	dst[i+31:i+j] := 0
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="xmm, xmm" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*32
+ 			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+31:i+j] := 0
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="xmm {k}, xmm" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*32
+ 			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+31:i+j] := 0
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="xmm {z}, xmm" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	FOR k := 0 to j-1
+ 		m := k*64
+ 		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 	ENDFOR
+ 	dst[i+63:i+j] := 0
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="ymm, ymm" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*64
+ 			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+63:i+j] := 0
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="ymm {k}, ymm" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*64
+ 			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+63:i+j] := 0
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="ymm {z}, ymm" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	FOR k := 0 to j-1
+ 		m := k*64
+ 		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 	ENDFOR
+ 	dst[i+63:i+j] := 0
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="xmm, xmm" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*64
+ 			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+63:i+j] := 0
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="xmm {k}, xmm" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*64
+ 			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+63:i+j] := 0
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="xmm {z}, xmm" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	tmp := 31
+ 	dst[i+31:i] := 0
+ 	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 		tmp := tmp - 1
+ 		dst[i+31:i] := dst[i+31:i] + 1
+ 	OD
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="ymm, ymm" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		tmp := 31
+ 		dst[i+31:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+31:i] := dst[i+31:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="ymm {k}, ymm" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		tmp := 31
+ 		dst[i+31:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+31:i] := dst[i+31:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="ymm {z}, ymm" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	tmp := 31
+ 	dst[i+31:i] := 0
+ 	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 		tmp := tmp - 1
+ 		dst[i+31:i] := dst[i+31:i] + 1
+ 	OD
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="xmm, xmm" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		tmp := 31
+ 		dst[i+31:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+31:i] := dst[i+31:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="xmm {k}, xmm" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		tmp := 31
+ 		dst[i+31:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+31:i] := dst[i+31:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="xmm {z}, xmm" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	tmp := 63
+ 	dst[i+63:i] := 0
+ 	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 		tmp := tmp - 1
+ 		dst[i+63:i] := dst[i+63:i] + 1
+ 	OD
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="ymm, ymm" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		tmp := 63
+ 		dst[i+63:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+63:i] := dst[i+63:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="ymm {k}, ymm" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		tmp := 63
+ 		dst[i+63:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+63:i] := dst[i+63:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="ymm {z}, ymm" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	tmp := 63
+ 	dst[i+63:i] := 0
+ 	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 		tmp := tmp - 1
+ 		dst[i+63:i] := dst[i+63:i] + 1
+ 	OD
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="xmm, xmm" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		tmp := 63
+ 		dst[i+63:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+63:i] := dst[i+63:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="xmm {k}, xmm" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		tmp := 63
+ 		dst[i+63:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+63:i] := dst[i+63:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="xmm {z}, xmm" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_broadcastmb_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := ZeroExtend64(k[7:0])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTMB2Q" form="zmm" xed="VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_broadcastmw_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Swizzle</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := ZeroExtend32(k[15:0])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTMW2D" form="zmm" xed="VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	FOR k := 0 to j-1
+ 		m := k*32
+ 		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 	ENDFOR
+ 	dst[i+31:i+j] := 0
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="zmm, zmm" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*32
+ 			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+31:i+j] := 0
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="zmm {k}, zmm" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_conflict_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*32
+ 			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+31:i+j] := 0
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTD" form="zmm {z}, zmm" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	FOR k := 0 to j-1
+ 		m := k*64
+ 		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 	ENDFOR
+ 	dst[i+63:i+j] := 0
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="zmm, zmm" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*64
+ 			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+63:i+j] := 0
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="zmm {k}, zmm" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_conflict_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		FOR l := 0 to j-1
+ 			m := l*64
+ 			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+ 		ENDFOR
+ 		dst[i+63:i+j] := 0
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPCONFLICTQ" form="zmm {z}, zmm" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	tmp := 31
+ 	dst[i+31:i] := 0
+ 	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 		tmp := tmp - 1
+ 		dst[i+31:i] := dst[i+31:i] + 1
+ 	OD
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="zmm, zmm" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		tmp := 31
+ 		dst[i+31:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+31:i] := dst[i+31:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="zmm {k}, zmm" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_lzcnt_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		tmp := 31
+ 		dst[i+31:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+31:i] := dst[i+31:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTD" form="zmm {z}, zmm" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	tmp := 63
+ 	dst[i+63:i] := 0
+ 	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 		tmp := tmp - 1
+ 		dst[i+63:i] := dst[i+63:i] + 1
+ 	OD
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="zmm, zmm" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		tmp := 63
+ 		dst[i+63:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+63:i] := dst[i+63:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="zmm {k}, zmm" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_lzcnt_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512CD</CPUID>
+ 	<category>Bit Manipulation</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		tmp := 63
+ 		dst[i+63:i] := 0
+ 		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+ 			tmp := tmp - 1
+ 			dst[i+63:i] := dst[i+63:i] + 1
+ 		OD
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPLZCNTQ" form="zmm {z}, zmm" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="ymm {k}, ymm, ymm" xed="VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="ymm {z}, ymm, ymm" xed="VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="zmm, zmm, zmm" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="zmm {k}, zmm, zmm" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="zmm {z}, zmm, zmm" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="xmm {k}, xmm, xmm" xed="VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_andnot_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDNPD" form="xmm {z}, xmm, xmm" xed="VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="ymm {k}, ymm, ymm" xed="VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="ymm {z}, ymm, ymm" xed="VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="zmm, zmm, zmm" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="zmm {k}, zmm, zmm" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="zmm {z}, zmm, zmm" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="xmm {k}, xmm, xmm" xed="VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_andnot_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDNPS" form="xmm {z}, xmm, xmm" xed="VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="ymm {k}, ymm, ymm" xed="VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0 
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="ymm {z}, ymm, ymm" xed="VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="zmm, zmm, zmm" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="zmm {k}, zmm, zmm" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="zmm {z}, zmm, zmm" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="xmm {k}, xmm, xmm" xed="VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_and_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDPD" form="xmm {z}, xmm, xmm" xed="VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="ymm {k}, ymm, ymm" xed="VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="ymm {z}, ymm, ymm" xed="VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="zmm, zmm, zmm" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="zmm {k}, zmm, zmm" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="zmm {z}, zmm, zmm" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="xmm {k}, xmm, xmm" xed="VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_and_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VANDPS" form="xmm {z}, xmm, xmm" xed="VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_broadcast_f32x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X2" form="ymm, xmm" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcast_f32x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X2" form="ymm {k}, xmm" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcast_f32x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X2" form="ymm {z}, xmm" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_broadcast_f32x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X2" form="zmm, xmm" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_broadcast_f32x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X2" form="zmm {k}, xmm" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_broadcast_f32x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X2" form="zmm {z}, xmm" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_broadcast_f32x8">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 8)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X8" form="zmm, m256" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_mask_broadcast_f32x8">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 8)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X8" form="zmm {k}, m256" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_maskz_broadcast_f32x8">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 8)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X8" form="zmm {z}, m256" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_broadcast_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	dst[i+63:i] := a[n+63:n]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF64X2" form="ymm, m128" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_mask_broadcast_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF64X2" form="ymm {k}, m128" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_maskz_broadcast_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF64X2" form="ymm {z}, m128" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_broadcast_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	dst[i+63:i] := a[n+63:n]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF64X2" form="zmm, m128" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_mask_broadcast_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF64X2" form="zmm {k}, m128" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_maskz_broadcast_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF64X2" form="zmm {z}, m128" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_broadcast_i32x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="ymm, xmm" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcast_i32x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="ymm {k}, xmm" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcast_i32x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="ymm {z}, xmm" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_broadcast_i32x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="zmm, xmm" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_broadcast_i32x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="zmm {k}, xmm" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_broadcast_i32x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="zmm {z}, xmm" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_broadcast_i32x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="xmm, xmm" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_broadcast_i32x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="xmm {k}, xmm" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_broadcast_i32x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	n := (j % 2)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X2" form="xmm {z}, xmm" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_broadcast_i32x8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 8)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X8" form="zmm, m256" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_mask_broadcast_i32x8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 8)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X8" form="zmm {k}, m256" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_maskz_broadcast_i32x8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	n := (j % 8)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X8" form="zmm {z}, m256" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_broadcast_i64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	dst[i+63:i] := a[n+63:n]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI64X2" form="ymm, m128" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_mask_broadcast_i64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI64X2" form="ymm {k}, m128" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_maskz_broadcast_i64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI64X2" form="ymm {z}, m128" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_broadcast_i64x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	dst[i+63:i] := a[n+63:n]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI64X2" form="zmm, m128" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_mask_broadcast_i64x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI64X2" form="zmm {k}, m128" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm512_maskz_broadcast_i64x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	n := (j % 2)*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[n+63:n]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI64X2" form="zmm {z}, m128" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="ymm, ymm" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="ymm {k}, ymm" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="ymm {z}, ymm" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="zmm, zmm {er}" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="zmm, zmm" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="zmm {k}, zmm {er}" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="zmm {k}, zmm" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="zmm {z}, zmm {er}" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="zmm {z}, zmm" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="xmm, xmm" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="xmm {k}, xmm" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2QQ" form="xmm {z}, xmm" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="ymm, ymm" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="ymm {k}, ymm" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="ymm {z}, ymm" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="zmm, zmm {er}" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="zmm, zmm" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="zmm {k}, zmm {er}" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="zmm {k}, zmm" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="zmm {z}, zmm {er}" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="zmm {z}, zmm" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="xmm, xmm" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="xmm {k}, xmm" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UQQ" form="xmm {z}, xmm" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="ymm, xmm" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="ymm {k}, xmm" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="ymm {z}, xmm" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="zmm, ymm {er}" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="zmm, ymm" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	 [round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="zmm {k}, ymm {er}" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="zmm {k}, ymm" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="zmm {z}, ymm {er}" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="zmm {z}, ymm" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="xmm, xmm" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="xmm {k}, xmm" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2QQ" form="xmm {z}, xmm" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="ymm, xmm" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="ymm {k}, xmm" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="ymm {z}, xmm" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="zmm, ymm {er}" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="zmm, ymm" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="zmm {k}, ymm {er}" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="zmm {k}, ymm" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="zmm {z}, ymm {er}" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="zmm {z}, ymm" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="xmm, xmm" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="xmm {k}, xmm" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UQQ" form="xmm {z}, xmm" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="ymm, ymm" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="ymm {k}, ymm" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="ymm {z}, ymm" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="zmm, zmm {er}" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="zmm, zmm" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="zmm {k}, zmm {er}" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="zmm {k}, zmm" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="zmm {z}, zmm {er}" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="zmm {z}, zmm" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="xmm, xmm" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="xmm {k}, xmm" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PD" form="xmm {z}, xmm" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="xmm, ymm" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="xmm {k}, ymm" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="xmm {z}, ymm" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="ymm, zmm {er}" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="ymm, zmm" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="ymm {k}, zmm {er}" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="ymm {k}, zmm" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="ymm {z}, zmm {er}" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="ymm {z}, zmm" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="xmm, xmm" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="xmm {k}, xmm" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTQQ2PS" form="xmm {z}, xmm" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="ymm, ymm" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="ymm {k}, ymm" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="ymm {z}, ymm" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtt_roundpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="zmm, zmm {sae}" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="zmm, zmm" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtt_roundpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="zmm {k}, zmm {sae}" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="zmm {k}, zmm" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtt_roundpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="zmm {z}, zmm {sae}" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="zmm {z}, zmm" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="xmm, xmm" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="xmm {k}, xmm" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttpd_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2QQ" form="xmm {z}, xmm" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="ymm, ymm" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="ymm {k}, ymm" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="ymm {z}, ymm" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtt_roundpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="zmm, zmm {sae}" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="zmm, zmm" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtt_roundpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="zmm {k}, zmm {sae}" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="zmm {k}, zmm" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtt_roundpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="zmm {z}, zmm {sae}" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="zmm {z}, zmm" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="xmm, xmm" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="xmm {k}, xmm" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttpd_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UQQ" form="xmm {z}, xmm" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="ymm, xmm" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="ymm {k}, xmm" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="ymm {z}, xmm" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtt_roundps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="zmm, ymm {sae}" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="zmm, ymm" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtt_roundps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="zmm {k}, ymm {sae}" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="zmm {k}, ymm" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtt_roundps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="zmm {z}, ymm {sae}" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="zmm {z}, ymm" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="xmm, xmm" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="xmm {k}, xmm" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttps_epi64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2QQ" form="xmm {z}, xmm" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="ymm, xmm" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="ymm {k}, xmm" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="ymm {z}, xmm" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtt_roundps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="zmm, ymm {sae}" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="zmm, ymm" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtt_roundps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="zmm {k}, ymm {sae}" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="zmm {k}, ymm" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtt_roundps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="zmm {z}, ymm {sae}" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="zmm {z}, ymm" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="xmm, xmm" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="xmm {k}, xmm" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttps_epu64">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UQQ" form="xmm {z}, xmm" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="ymm, ymm" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="ymm {k}, ymm" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="ymm {z}, ymm" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="zmm, zmm {er}" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="zmm, zmm" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="zmm {k}, zmm {er}" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="zmm {k}, zmm" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="zmm {z}, zmm {er}" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="zmm {z}, zmm" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="xmm, xmm" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="xmm {k}, xmm" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu64_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PD" form="xmm {z}, xmm" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="xmm, ymm" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="xmm {k}, ymm" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="xmm {z}, ymm" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvt_roundepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="ymm, zmm {er}" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="ymm, zmm" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvt_roundepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="ymm {k}, zmm {er}" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="ymm {k}, zmm" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvt_roundepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="rounding" etype="IMM" hint="TRUE" immtype="_MM_FROUND"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[round_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="ymm {z}, zmm {er}" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="ymm {z}, zmm" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="xmm, xmm" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="xmm {k}, xmm" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu64_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTUQQ2PS" form="xmm {z}, xmm" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_extractf32x8_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[255:0] := a[255:0]
+ 1: dst[255:0] := a[511:256]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF32X8" form="ymm, zmm, imm8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_extractf32x8_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[255:0] := a[255:0]
+ 1: tmp[255:0] := a[511:256]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF32X8" form="ymm {k}, zmm, imm8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_extractf32x8_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[255:0] := a[255:0]
+ 1: tmp[255:0] := a[511:256]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF32X8" form="ymm {z}, zmm, imm8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_extractf64x2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF64X2" form="xmm, ymm, imm8" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_extractf64x2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF64X2" form="xmm {k}, ymm, imm8" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_extractf64x2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF64X2" form="xmm {z}, ymm, imm8" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_extractf64x2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[1:0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ 2: dst[127:0] := a[383:256]
+ 3: dst[127:0] := a[511:384]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF64X2" form="xmm, zmm, imm8" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_extractf64x2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[1:0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ 2: tmp[127:0] := a[383:256]
+ 3: tmp[127:0] := a[511:384]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF64X2" form="xmm {k}, zmm, imm8" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_extractf64x2_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[1:0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ 2: tmp[127:0] := a[383:256]
+ 3: tmp[127:0] := a[511:384]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF64X2" form="xmm {z}, zmm, imm8" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_extracti32x8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[255:0] := a[255:0]
+ 1: dst[255:0] := a[511:256]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI32X8" form="ymm, zmm, imm8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_extracti32x8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[255:0] := a[255:0]
+ 1: tmp[255:0] := a[511:256]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI32X8" form="ymm {k}, zmm, imm8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_extracti32x8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[255:0] := a[255:0]
+ 1: tmp[255:0] := a[511:256]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI32X8" form="ymm {z}, zmm, imm8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_extracti64x2_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI64X2" form="xmm, ymm, imm8" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_extracti64x2_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI64X2" form="xmm {k}, ymm, imm8" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_extracti64x2_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI64X2" form="xmm {z}, ymm, imm8" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_extracti64x2_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[1:0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ 2: dst[127:0] := a[383:256]
+ 3: dst[127:0] := a[511:384]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI64X2" form="xmm, zmm, imm8" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_extracti64x2_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[1:0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ 2: tmp[127:0] := a[383:256]
+ 3: tmp[127:0] := a[511:384]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI64X2" form="xmm {k}, zmm, imm8" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_extracti64x2_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[1:0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ 2: tmp[127:0] := a[383:256]
+ 3: tmp[127:0] := a[511:384]
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI64X2" form="xmm {z}, zmm, imm8" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_fpclass_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPD" form="k, ymm, imm8" xed="VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fpclass_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPD" form="k {k}, ymm, imm8" xed="VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_fpclass_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*64
+ 	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPD" form="k, zmm, imm8" xed="VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_fpclass_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPD" form="k {k}, zmm, imm8" xed="VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_fpclass_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPD" form="k, xmm, imm8" xed="VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fpclass_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPD" form="k {k}, xmm, imm8" xed="VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_fpclass_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPS" form="k, ymm, imm8" xed="VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fpclass_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPS" form="k {k}, ymm, imm8" xed="VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_fpclass_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 15
+ 	i := j*32
+ 	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPS" form="k, zmm, imm8" xed="VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_fpclass_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="k1" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 15
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPS" form="k {k}, zmm, imm8" xed="VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_fpclass_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPS" form="k, xmm, imm8" xed="VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fpclass_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+ 	[fpclass_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSPS" form="k {k}, xmm, imm8" xed="VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_fpclass_sd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k".
+ 	[fpclass_note]</description>
+ 	<operation>k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0])
+ k[MAX:1] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSSD" form="k, xmm, imm8" xed="VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fpclass_sd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
+ 	[fpclass_note]</description>
+ 	<operation>IF k1[0]
+ 	k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0])
+ ELSE
+ 	k[0] := 0
+ FI
+ k[MAX:1] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSSD" form="k {k}, xmm, imm8" xed="VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_fpclass_ss_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k.
+ 	[fpclass_note]</description>
+ 	<operation>k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0])
+ k[MAX:1] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSSS" form="k, xmm, imm8" xed="VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fpclass_ss_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
+ 	[fpclass_note]</description>
+ 	<operation>IF k1[0]
+ 	k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0])
+ ELSE
+ 	k[0] := 0
+ FI
+ k[MAX:1] := 0
+ 	</operation>
+ 	<instruction name="VFPCLASSSS" form="k {k}, xmm, imm8" xed="VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_insertf32x8">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[511:0] := a[511:0]
+ CASE (imm8[0]) OF
+ 0: dst[255:0] := b[255:0]
+ 1: dst[511:256] := b[255:0]
+ ESAC
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF32X8" form="zmm, zmm, ymm, imm8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_insertf32x8">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[0]) OF
+ 0: tmp[255:0] := b[255:0]
+ 1: tmp[511:256] := b[255:0]
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF32X8" form="zmm {k}, zmm, ymm, imm8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_insertf32x8">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[0]) OF
+ 0: tmp[255:0] := b[255:0]
+ 1: tmp[511:256] := b[255:0]
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF32X8" form="zmm {z}, zmm, ymm, imm8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_insertf64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE imm8[0] OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF64X2" form="ymm, ymm, xmm, imm8" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_insertf64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF64X2" form="ymm {k}, ymm, xmm, imm8" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_insertf64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF64X2" form="ymm {z}, ymm, xmm, imm8" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_insertf64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[511:0] := a[511:0]
+ CASE imm8[1:0] OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ 2: dst[383:256] := b[127:0]
+ 3: dst[511:384] := b[127:0]
+ ESAC
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF64X2" form="zmm, zmm, xmm, imm8" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_insertf64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[1:0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ 2: tmp[383:256] := b[127:0]
+ 3: tmp[511:384] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF64X2" form="zmm {k}, zmm, xmm, imm8" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_insertf64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[1:0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ 2: tmp[383:256] := b[127:0]
+ 3: tmp[511:384] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF64X2" form="zmm {z}, zmm, xmm, imm8" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_inserti32x8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[511:0] := a[511:0]
+ CASE imm8[0] OF
+ 0: dst[255:0] := b[255:0]
+ 1: dst[511:256] := b[255:0]
+ ESAC
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI32X8" form="zmm, zmm, ymm, imm8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_inserti32x8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m512i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[0]) OF
+ 0: tmp[255:0] := b[255:0]
+ 1: tmp[511:256] := b[255:0]
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI32X8" form="zmm {k}, zmm, ymm, imm8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_inserti32x8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[0]) OF
+ 0: tmp[255:0] := b[255:0]
+ 1: tmp[511:256] := b[255:0]
+ ESAC
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI32X8" form="zmm {z}, zmm, ymm, imm8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_inserti64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE imm8[0] OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI64X2" form="ymm, ymm, xmm, imm8" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_inserti64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI64X2" form="ymm {k}, ymm, xmm, imm8" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_inserti64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI64X2" form="ymm {z}, ymm, xmm, imm8" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_inserti64x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[511:0] := a[511:0]
+ CASE imm8[1:0] OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ 2: dst[383:256] := b[127:0]
+ 3: dst[511:384] := b[127:0]
+ ESAC
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI64X2" form="zmm, zmm, xmm, imm8" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_inserti64x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[1:0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ 2: tmp[383:256] := b[127:0]
+ 3: tmp[511:384] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI64X2" form="zmm {k}, zmm, xmm, imm8" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_inserti64x2">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[511:0] := a[511:0]
+ CASE (imm8[1:0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ 2: tmp[383:256] := b[127:0]
+ 3: tmp[511:384] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI64X2" form="zmm {z}, zmm, xmm, imm8" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="ymm {k}, ymm, ymm" xed="VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="ymm {z}, ymm, ymm" xed="VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="zmm {k}, zmm, zmm" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="zmm {z}, zmm, zmm" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="zmm, zmm, zmm" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="xmm {k}, xmm, xmm" xed="VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_or_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VORPD" form="xmm {z}, xmm, xmm" xed="VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="ymm {k}, ymm, ymm" xed="VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="ymm {z}, ymm, ymm" xed="VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="zmm {k}, zmm, zmm" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="zmm {z}, zmm, zmm" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="zmm, zmm, zmm" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="xmm {k}, xmm, xmm" xed="VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_or_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VORPS" form="xmm {z}, xmm, xmm" xed="VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movepi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF a[i+31]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPMOVD2M" form="k, ymm" xed="VPMOVD2M_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movepi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF a[i+31]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVD2M" form="k, zmm" xed="VPMOVD2M_MASKmskw_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movepi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF a[i+31]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPMOVD2M" form="k, xmm" xed="VPMOVD2M_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movm_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := 0xFFFFFFFF
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2D" form="ymm" xed="VPMOVM2D_YMMu32_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movm_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := 0xFFFFFFFF
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2D" form="zmm" xed="VPMOVM2D_ZMMu32_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movm_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := 0xFFFFFFFF
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2D" form="xmm" xed="VPMOVM2D_XMMu32_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movm_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2Q" form="ymm" xed="VPMOVM2Q_YMMu64_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movm_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2Q" form="zmm" xed="VPMOVM2Q_ZMMu64_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movm_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVM2Q" form="xmm" xed="VPMOVM2Q_XMMu64_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_movepi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF a[i+63]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQ2M" form="k, ymm" xed="VPMOVQ2M_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_movepi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF a[i+63]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQ2M" form="k, zmm" xed="VPMOVQ2M_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_movepi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF a[i+63]
+ 		k[j] := 1
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQ2M" form="k, xmm" xed="VPMOVQ2M_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 		dst[i+63:i] := tmp[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="ymm {k}, ymm, ymm" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 		dst[i+63:i] := tmp[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="ymm {z}, ymm, ymm" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 	dst[i+63:i] := tmp[63:0]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="ymm, ymm, ymm" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="__m512i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 		dst[i+63:i] := tmp[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="zmm {k}, zmm, zmm" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="__m512i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 		dst[i+63:i] := tmp[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="zmm {z}, zmm, zmm" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<parameter type="__m512i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 	dst[i+63:i] := tmp[63:0]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="zmm, zmm, zmm" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 		dst[i+63:i] := tmp[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="xmm {k}, xmm, xmm" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 		dst[i+63:i] := tmp[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="xmm {z}, xmm, xmm" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mullo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	tmp[127:0] := a[i+63:i] * b[i+63:i]
+ 	dst[i+63:i] := tmp[63:0]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLQ" form="xmm, xmm, xmm" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="ymm {k}, ymm, ymm, imm8" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="ymm {z}, ymm, ymm, imm8" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="ymm, ymm, ymm, imm8" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="zmm {k}, zmm, zmm, imm8" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_range_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="zmm {k}, zmm, zmm {sae}, imm8" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="zmm {z}, zmm, zmm, imm8" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_range_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="zmm {z}, zmm, zmm {sae}, imm8" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="zmm, zmm, zmm, imm8" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_range_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="zmm, zmm, zmm {sae}, imm8" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="xmm {k}, xmm, xmm, imm8" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="xmm {z}, xmm, xmm, imm8" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_range_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPD" form="xmm, xmm, xmm, imm8" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="ymm {k}, ymm, ymm, imm8" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="ymm {z}, ymm, ymm, imm8" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="ymm, ymm, ymm, imm8" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="zmm {k}, zmm, zmm, imm8" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_range_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="zmm {k}, zmm, zmm {sae}, imm8" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="zmm {z}, zmm, zmm, imm8" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_range_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="zmm {z}, zmm, zmm {sae}, imm8" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="zmm, zmm, zmm, imm8" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_range_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="zmm, zmm, zmm {sae}, imm8" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="xmm {k}, xmm, xmm, imm8" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="xmm {z}, xmm, xmm, imm8" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_range_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[63:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGEPS" form="xmm, xmm, xmm, imm8" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_range_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESD" form="xmm {k}, xmm, xmm {sae}, imm8" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_range_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESD" form="xmm {k}, xmm, xmm, imm8" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_range_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESD" form="xmm {z}, xmm, xmm {sae}, imm8" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_range_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESD" form="xmm {z}, xmm, xmm, imm8" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_range_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+ 	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+ 	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+ 	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+ 	1: dst[63:0] := tmp[63:0]
+ 	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+ 	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESD" form="xmm, xmm, xmm {sae}, imm8" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_range_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[31:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESS" form="xmm {k}, xmm, xmm {sae}, imm8" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_range_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[31:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESS" form="xmm {k}, xmm, xmm, imm8" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_range_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[31:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESS" form="xmm {z}, xmm, xmm {sae}, imm8" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_range_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[31:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ IF k[0]
+ 	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESS" form="xmm {z}, xmm, xmm, imm8" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_range_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+ 	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min.
+ 	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+ 	<operation>
+ DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+ 	CASE opCtl[1:0] OF
+ 	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+ 	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+ 	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+ 	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+ 	ESAC
+ 	
+ 	CASE signSelCtl[1:0] OF
+ 	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+ 	1: dst[31:0] := tmp[31:0]
+ 	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+ 	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+ 	ESAC
+ 	
+ 	RETURN dst
+ }
+ dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRANGESS" form="xmm, xmm, xmm {sae}, imm8" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="ymm {k}, ymm, imm8" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="ymm {z}, ymm, imm8" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="ymm, ymm, imm8" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="zmm {k}, zmm, imm8" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_reduce_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="zmm {k}, zmm {sae}, imm8" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="zmm {z}, zmm, imm8" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_reduce_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="zmm {z}, zmm {sae}, imm8" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="zmm, zmm, imm8" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_reduce_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="zmm, zmm {sae}, imm8" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="xmm {k}, xmm, imm8" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="xmm {z}, xmm, imm8" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_reduce_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPD" form="xmm, xmm, imm8" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="ymm {k}, ymm, imm8" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="ymm {z}, ymm, imm8" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	RETURN tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="ymm, ymm, imm8" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="zmm {k}, zmm, imm8" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_reduce_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="zmm {k}, zmm {sae}, imm8" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="zmm {z}, zmm, imm8" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_reduce_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="zmm {z}, zmm {sae}, imm8" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="zmm, zmm, imm8" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_reduce_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="zmm, zmm {sae}, imm8" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="xmm {k}, xmm, imm8" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="xmm {z}, xmm, imm8" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_reduce_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCEPS" form="xmm, xmm, imm8" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_reduce_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ IF k[0]
+ 	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESD" form="xmm {k}, xmm, xmm, imm8" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_reduce_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ IF k[0]
+ 	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESD" form="xmm {k}, xmm, xmm {sae}, imm8" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_reduce_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ IF k[0]
+ 	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESD" form="xmm {z}, xmm, xmm, imm8" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_reduce_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ IF k[0]
+ 	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESD" form="xmm {z}, xmm, xmm {sae}, imm8" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_reduce_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESD" form="xmm, xmm, xmm, imm8" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_reduce_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	tmp[63:0] := src1[63:0] - tmp[63:0]
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := FP64(0.0)
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESD" form="xmm, xmm, xmm {sae}, imm8" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_reduce_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ IF k[0]
+ 	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESS" form="xmm {k}, xmm, xmm, imm8" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_reduce_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ IF k[0]
+ 	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESS" form="xmm {k}, xmm, xmm {sae}, imm8" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_reduce_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ IF k[0]
+ 	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESS" form="xmm {z}, xmm, xmm, imm8" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_reduce_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ IF k[0]
+ 	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESS" form="xmm {z}, xmm, xmm {sae}, imm8" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_reduce_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESS" form="xmm, xmm, xmm, imm8" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_reduce_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+ 	<operation>
+ DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	tmp[31:0] := src1[31:0] - tmp[31:0]
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := FP32(0.0)
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VREDUCESS" form="xmm, xmm, xmm {sae}, imm8" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="ymm {k}, ymm, ymm" xed="VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="ymm {z}, ymm, ymm" xed="VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="zmm {k}, zmm, zmm" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="zmm {z}, zmm, zmm" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="__m512d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="zmm, zmm, zmm" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="xmm {k}, xmm, xmm" xed="VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_xor_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VXORPD" form="xmm {z}, xmm, xmm" xed="VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="ymm {k}, ymm, ymm" xed="VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="ymm {z}, ymm, ymm" xed="VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="zmm {k}, zmm, zmm" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="zmm {z}, zmm, zmm" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="__m512" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="zmm, zmm, zmm" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="xmm {k}, xmm, xmm" xed="VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_xor_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VXORPS" form="xmm {z}, xmm, xmm" xed="VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kadd_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Add 8-bit masks in "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := a[7:0] + b[7:0]
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KADDB" form="k, k, k" xed="KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kadd_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Add 16-bit masks in "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := a[15:0] + b[15:0]
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KADDW" form="k, k, k" xed="KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kand_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := a[7:0] AND b[7:0]
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KANDB" form="k, k, k" xed="KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kandn_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 8-bit masks "a" and then AND with "b", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := (NOT a[7:0]) AND b[7:0]
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KANDNB" form="k, k, k" xed="KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_knot_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 8-bit mask "a", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := NOT a[7:0]
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KNOTB" form="k, k" xed="KNOTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kor_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 8-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := a[7:0] OR b[7:0]
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KORB" form="k, k, k" xed="KORB_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxnor_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XNOR of 8-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := NOT (a[7:0] XOR b[7:0])
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KXNORB" form="k, k, k" xed="KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxor_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XOR of 8-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[7:0] := a[7:0] XOR b[7:0]
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="KXORB" form="k, k, k" xed="KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftli_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 8-bit mask "a" left by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 7
+ 	k[7:0] := a[7:0] &lt;&lt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTLB" form="k, k, imm8" xed="KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftri_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 8-bit mask "a" right by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 7
+ 	k[7:0] := a[7:0] &gt;&gt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTRB" form="k, k, imm8" xed="KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_load_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Load</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8*" varname="mem_addr" etype="MASK" memwidth="8"/>
+ 	<description>Load 8-bit mask from memory into "k".</description>
+ 	<operation>
+ k[7:0] := MEM[mem_addr+7:mem_addr]
+ 	</operation>
+ 	<instruction name="KMOVB" form="k, m8" xed="KMOVB_MASKmskw_MEMu8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_store_mask8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="__mmask8*" varname="mem_addr" etype="MASK" memwidth="8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<description>Store 8-bit mask from "a" into memory.</description>
+ 	<operation>
+ MEM[mem_addr+7:mem_addr] := a[7:0]
+ 	</operation>
+ 	<instruction name="KMOVB" form="m8, k" xed="KMOVB_MEMu8_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortest_mask8_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="all_ones" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+ 	<operation>
+ tmp[7:0] := a[7:0] OR b[7:0]
+ IF tmp[7:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ IF tmp[7:0] == 0xFF
+ 	MEM[all_ones+7:all_ones] := 1
+ ELSE
+ 	MEM[all_ones+7:all_ones] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTB" form="k, k" xed="KORTESTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortestz_mask8_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[7:0] := a[7:0] OR b[7:0]
+ IF tmp[7:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTB" form="k, k" xed="KORTESTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kortestc_mask8_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[7:0] := a[7:0] OR b[7:0]
+ IF tmp[7:0] == 0xFF
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KORTESTB" form="k, k" xed="KORTESTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktest_mask8_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="and_not" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+ 	<operation>
+ tmp1[7:0] := a[7:0] AND b[7:0]
+ IF tmp1[7:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ tmp2[7:0] := (NOT a[7:0]) AND b[7:0]
+ IF tmp2[7:0] == 0x0
+ 	MEM[and_not+7:and_not] := 1
+ ELSE
+ 	MEM[and_not+7:and_not] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTB" form="k, k" xed="KTESTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestz_mask8_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[7:0] := a[7:0] AND b[7:0]
+ IF tmp[7:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTB" form="k, k" xed="KTESTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestc_mask8_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 8-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[7:0] := (NOT a[7:0]) AND b[7:0]
+ IF tmp[7:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTB" form="k, k" xed="KTESTB_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktest_mask16_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<parameter type="unsigned char*" varname="and_not" etype="UI8" memwidth="8"/>
+ 	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+ 	<operation>
+ tmp1[15:0] := a[15:0] AND b[15:0]
+ IF tmp1[15:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ tmp2[15:0] := (NOT a[15:0]) AND b[15:0]
+ IF tmp2[15:0] == 0x0
+ 	MEM[and_not+7:and_not] := 1
+ ELSE
+ 	MEM[and_not+7:and_not] := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTW" form="k, k" xed="KTESTW_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestz_mask16_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[15:0] := a[15:0] AND b[15:0]
+ IF tmp[15:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTW" form="k, k" xed="KTESTW_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_ktestc_mask16_u8">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned char" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 16-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+ 	<operation>
+ tmp[15:0] := (NOT a[15:0]) AND b[15:0]
+ IF tmp[15:0] == 0x0
+ 	dst := 1
+ ELSE
+ 	dst := 0
+ FI
+ 	</operation>
+ 	<instruction name="KTESTW" form="k, k" xed="KTESTW_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_cvtmask8_u32">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="unsigned int" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="a" etype="MASK"/>
+ 	<description>Convert 8-bit mask "a" into an integer value, and store the result in "dst".</description>
+ 	<operation>
+ dst := ZeroExtend32(a[7:0])
+ 	</operation>
+ 	<instruction name="KMOVB" form="r32, k" xed="KMOVB_GPR32u32_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_cvtu32_mask8">
+ 	<CPUID>AVX512DQ</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="a" etype="UI8"/>
+ 	<description>Convert integer value "a" into an 8-bit mask, and store the result in "k".</description>
+ 	<operation>
+ k := a[7:0]
+ 	</operation>
+ 	<instruction name="KMOVB" form="k, r32" xed="KMOVB_MASKmskw_GPR32u32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_exp2a23_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PS" form="zmm, zmm {sae}" xed="VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_exp2a23_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PS" form="zmm, zmm" xed="VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_exp2a23_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PS" form="zmm {k}, zmm {sae}" xed="VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_exp2a23_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PS" form="zmm {k}, zmm" xed="VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_exp2a23_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PS" form="zmm {z}, zmm {sae}" xed="VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_exp2a23_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PS" form="zmm {z}, zmm" xed="VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_exp2a23_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := POW(2.0, a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PD" form="zmm, zmm {sae}" xed="VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_exp2a23_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := POW(2.0, a[i+63:i])
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PD" form="zmm, zmm" xed="VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_exp2a23_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := POW(2.0, a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PD" form="zmm {k}, zmm {sae}" xed="VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_exp2a23_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := POW(2.0, a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PD" form="zmm {k}, zmm" xed="VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_exp2a23_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := POW(2.0, a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PD" form="zmm {z}, zmm {sae}" xed="VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_exp2a23_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := POW(2.0, a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VEXP2PD" form="zmm {z}, zmm" xed="VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rcp28_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ dst[63:0] := (1.0 / b[63:0])
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SD" form="xmm, xmm, xmm {sae}" xed="VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rcp28_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ dst[63:0] := (1.0 / b[63:0])
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SD" form="xmm, xmm, xmm" xed="VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rcp28_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / b[63:0])
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SD" form="xmm {k}, xmm, xmm {sae}" xed="VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rcp28_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / b[63:0])
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SD" form="xmm {k}, xmm, xmm" xed="VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rcp28_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / b[63:0])
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SD" form="xmm {z}, xmm, xmm {sae}" xed="VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rcp28_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / b[63:0])
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SD" form="xmm {z}, xmm, xmm" xed="VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rcp28_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst". The maximum relative error for this approximation is less than 2^-28, and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
+ 	<operation>
+ dst[31:0] := (1.0 / b[31:0])
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SS" form="xmm, xmm, xmm {sae}" xed="VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rcp28_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ dst[31:0] := (1.0 / b[31:0])
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SS" form="xmm, xmm, xmm" xed="VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rcp28_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / b[31:0])
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SS" form="xmm {k}, xmm, xmm {sae}" xed="VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rcp28_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / b[31:0])
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SS" form="xmm {k}, xmm, xmm" xed="VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rcp28_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / b[31:0])
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SS" form="xmm {z}, xmm, xmm {sae}" xed="VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rcp28_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / b[31:0])
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP28SS" form="xmm {z}, xmm, xmm" xed="VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rcp28_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / a[i+31:i])
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PS" form="zmm, zmm {sae}" xed="VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rcp28_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / a[i+31:i])
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PS" form="zmm, zmm" xed="VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rcp28_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PS" form="zmm {k}, zmm {sae}" xed="VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rcp28_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PS" form="zmm {k}, zmm" xed="VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rcp28_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PS" form="zmm {z}, zmm {sae}" xed="VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rcp28_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PS" form="zmm {z}, zmm" xed="VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rcp28_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := (1.0 / a[i+63:i])
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PD" form="zmm, zmm {sae}" xed="VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rcp28_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := (1.0 / a[i+63:i])
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PD" form="zmm, zmm" xed="VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rcp28_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PD" form="zmm {k}, zmm {sae}" xed="VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rcp28_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PD" form="zmm {k}, zmm" xed="VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rcp28_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PD" form="zmm {z}, zmm {sae}" xed="VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rcp28_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRCP28PD" form="zmm {z}, zmm" xed="VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rsqrt28_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ dst[63:0] := (1.0 / SQRT(b[63:0]))
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SD" form="xmm, xmm, xmm {sae}" xed="VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rsqrt28_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ dst[63:0] := (1.0 / SQRT(b[63:0]))
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SD" form="xmm, xmm, xmm" xed="VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rsqrt28_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / SQRT(b[63:0]))
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SD" form="xmm {k}, xmm, xmm {sae}" xed="VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rsqrt28_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / SQRT(b[63:0]))
+ ELSE
+ 	dst[63:0] := src[63:0]
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SD" form="xmm {k}, xmm, xmm" xed="VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rsqrt28_round_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / SQRT(b[63:0]))
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SD" form="xmm {z}, xmm, xmm {sae}" xed="VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rsqrt28_sd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[63:0] := (1.0 / SQRT(b[63:0]))
+ ELSE
+ 	dst[63:0] := 0
+ FI
+ dst[127:64] := a[127:64]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SD" form="xmm {z}, xmm, xmm" xed="VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rsqrt28_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ dst[31:0] := (1.0 / SQRT(b[31:0]))
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SS" form="xmm, xmm, xmm {sae}" xed="VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rsqrt28_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ dst[31:0] := (1.0 / SQRT(b[31:0]))
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SS" form="xmm, xmm, xmm" xed="VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rsqrt28_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / SQRT(b[31:0]))
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SS" form="xmm {k}, xmm, xmm {sae}" xed="VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rsqrt28_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / SQRT(b[31:0]))
+ ELSE
+ 	dst[31:0] := src[31:0]
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SS" form="xmm {k}, xmm, xmm" xed="VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rsqrt28_round_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / SQRT(b[31:0]))
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SS" form="xmm {z}, xmm, xmm {sae}" xed="VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rsqrt28_ss">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ IF k[0]
+ 	dst[31:0] := (1.0 / SQRT(b[31:0]))
+ ELSE
+ 	dst[31:0] := 0
+ FI
+ dst[127:32] := a[127:32]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT28SS" form="xmm {z}, xmm, xmm" xed="VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rsqrt28_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PS" form="zmm, zmm {sae}" xed="VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rsqrt28_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PS" form="zmm, zmm" xed="VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rsqrt28_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PS" form="zmm {k}, zmm {sae}" xed="VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rsqrt28_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__m512" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PS" form="zmm {k}, zmm" xed="VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rsqrt28_round_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PS" form="zmm {z}, zmm {sae}" xed="VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rsqrt28_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PS" form="zmm {z}, zmm" xed="VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rsqrt28_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PD" form="zmm, zmm {sae}" xed="VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_rsqrt28_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PD" form="zmm, zmm" xed="VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rsqrt28_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PD" form="zmm {k}, zmm {sae}" xed="VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_mask_rsqrt28_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m512d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PD" form="zmm {k}, zmm" xed="VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rsqrt28_round_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="sae" etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PD" form="zmm {z}, zmm {sae}" xed="VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_rsqrt28_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512ER</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m512d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m512d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VRSQRT28PD" form="zmm {z}, zmm" xed="VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_add_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDPD" form="ymm {k}, ymm, ymm" xed="VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_add_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDPD" form="ymm {z}, ymm, ymm" xed="VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_add_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VADDPD" form="xmm {k}, xmm, xmm" xed="VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_add_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VADDPD" form="xmm {z}, xmm, xmm" xed="VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_add_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDPS" form="ymm {k}, ymm, ymm" xed="VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_add_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VADDPS" form="ymm {z}, ymm, ymm" xed="VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_add_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VADDPS" form="xmm {k}, xmm, xmm" xed="VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_add_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VADDPS" form="xmm {z}, xmm, xmm" xed="VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_alignr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="3"/>
+ 	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst".</description>
+ 	<operation>
+ temp[511:256] := a[255:0]
+ temp[255:0] := b[255:0]
+ temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
+ dst[255:0] := temp[255:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VALIGND" form="ymm, ymm, ymm, imm8" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_alignr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="3"/>
+ 	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[511:256] := a[255:0]
+ temp[255:0] := b[255:0]
+ temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := temp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VALIGND" form="ymm {k}, ymm, ymm, imm8" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_alignr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="3"/>
+ 	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[511:256] := a[255:0]
+ temp[255:0] := b[255:0]
+ temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := temp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VALIGND" form="ymm {z}, ymm, ymm, imm8" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_alignr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst".</description>
+ 	<operation>
+ temp[255:128] := a[127:0]
+ temp[127:0] := b[127:0]
+ temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
+ dst[127:0] := temp[127:0]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VALIGND" form="xmm, xmm, xmm, imm8" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_alignr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[255:128] := a[127:0]
+ temp[127:0] := b[127:0]
+ temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := temp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VALIGND" form="xmm {k}, xmm, xmm, imm8" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_alignr_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[255:128] := a[127:0]
+ temp[127:0] := b[127:0]
+ temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := temp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VALIGND" form="xmm {z}, xmm, xmm, imm8" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_alignr_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst".</description>
+ 	<operation>
+ temp[511:256] := a[255:0]
+ temp[255:0] := b[255:0]
+ temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
+ dst[255:0] := temp[255:0]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VALIGNQ" form="ymm, ymm, ymm, imm8" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_alignr_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[511:256] := a[255:0]
+ temp[255:0] := b[255:0]
+ temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := temp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VALIGNQ" form="ymm {k}, ymm, ymm, imm8" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_alignr_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[511:256] := a[255:0]
+ temp[255:0] := b[255:0]
+ temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := temp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VALIGNQ" form="ymm {z}, ymm, ymm, imm8" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_alignr_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst".</description>
+ 	<operation>
+ temp[255:128] := a[127:0]
+ temp[127:0] := b[127:0]
+ temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
+ dst[127:0] := temp[127:0]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VALIGNQ" form="xmm, xmm, xmm, imm8" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_alignr_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[255:128] := a[127:0]
+ temp[127:0] := b[127:0]
+ temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := temp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VALIGNQ" form="xmm {k}, xmm, xmm, imm8" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_alignr_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ temp[255:128] := a[127:0]
+ temp[127:0] := b[127:0]
+ temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := temp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VALIGNQ" form="xmm {z}, xmm, xmm, imm8" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_blend_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBLENDMPD" form="ymm {k}, ymm, ymm" xed="VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_blend_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBLENDMPD" form="xmm {k}, xmm, xmm" xed="VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_blend_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBLENDMPS" form="ymm {k}, ymm, ymm" xed="VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_blend_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBLENDMPS" form="xmm {k}, xmm, xmm" xed="VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_broadcast_f32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 4)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X4" form="ymm, m128" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_mask_broadcast_f32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 4)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X4" form="ymm {k}, m128" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_maskz_broadcast_f32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 4)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTF32X4" form="ymm {z}, m128" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_broadcast_i32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 4)*32
+ 	dst[i+31:i] := a[n+31:n]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X4" form="ymm, m128" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_mask_broadcast_i32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 4)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X4" form="ymm {k}, m128" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" sequence="TRUE" name="_mm256_maskz_broadcast_i32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	n := (j % 4)*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[n+31:n]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTI32X4" form="ymm {z}, m128" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcastsd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSD" form="ymm {k}, xmm" xed="VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcastsd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSD" form="ymm {z}, xmm" xed="VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcastss_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="ymm {k}, xmm" xed="VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcastss_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="ymm {z}, xmm" xed="VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_broadcastss_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="xmm {k}, xmm" xed="VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_broadcastss_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VBROADCASTSS" form="xmm {z}, xmm" xed="VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VCMPPD" form="k, ymm, ymm, imm8" xed="VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VCMPPD" form="k {k}, ymm, ymm, imm8" xed="VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VCMPPD" form="k, xmm, xmm, imm8" xed="VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_pd_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VCMPPD" form="k {k}, xmm, xmm, imm8" xed="VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VCMPPS" form="k, ymm, ymm, imm8" xed="VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VCMPPS" form="k {k}, ymm, ymm, imm8" xed="VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VCMPPS" form="k, xmm, xmm, imm8" xed="VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_ps_mask">
+ 	<type>Floating Point</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="5"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[4:0]) OF
+ 0: OP := _CMP_EQ_OQ
+ 1: OP := _CMP_LT_OS
+ 2: OP := _CMP_LE_OS
+ 3: OP := _CMP_UNORD_Q 
+ 4: OP := _CMP_NEQ_UQ
+ 5: OP := _CMP_NLT_US
+ 6: OP := _CMP_NLE_US
+ 7: OP := _CMP_ORD_Q
+ 8: OP := _CMP_EQ_UQ
+ 9: OP := _CMP_NGE_US
+ 10: OP := _CMP_NGT_US
+ 11: OP := _CMP_FALSE_OQ
+ 12: OP := _CMP_NEQ_OQ
+ 13: OP := _CMP_GE_OS
+ 14: OP := _CMP_GT_OS
+ 15: OP := _CMP_TRUE_UQ
+ 16: OP := _CMP_EQ_OS
+ 17: OP := _CMP_LT_OQ
+ 18: OP := _CMP_LE_OQ
+ 19: OP := _CMP_UNORD_S
+ 20: OP := _CMP_NEQ_US
+ 21: OP := _CMP_NLT_UQ
+ 22: OP := _CMP_NLE_UQ
+ 23: OP := _CMP_ORD_S
+ 24: OP := _CMP_EQ_US
+ 25: OP := _CMP_NGE_UQ 
+ 26: OP := _CMP_NGT_UQ 
+ 27: OP := _CMP_FALSE_OS 
+ 28: OP := _CMP_NEQ_OS 
+ 29: OP := _CMP_GE_OQ
+ 30: OP := _CMP_GT_OQ
+ 31: OP := _CMP_TRUE_US
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VCMPPS" form="k {k}, xmm, xmm, imm8" xed="VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compress_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := src[255:m]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPD" form="ymm {k}, ymm" xed="VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compressstoreu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 64
+ m := base_addr
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VCOMPRESSPD" form="m256 {k}, ymm" xed="VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_compress_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPD" form="ymm {z}, ymm" xed="VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compress_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := src[127:m]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPD" form="xmm {k}, xmm" xed="VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compressstoreu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 64
+ m := base_addr
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VCOMPRESSPD" form="m128 {k}, xmm" xed="VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_compress_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPD" form="xmm {z}, xmm" xed="VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compress_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := src[255:m]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPS" form="ymm {k}, ymm" xed="VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compressstoreu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 32
+ m := base_addr
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VCOMPRESSPS" form="m256 {k}, ymm" xed="VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_compress_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPS" form="ymm {z}, ymm" xed="VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compress_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := src[127:m]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPS" form="xmm {k}, xmm" xed="VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compressstoreu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 32
+ m := base_addr
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VCOMPRESSPS" form="m128 {k}, xmm" xed="VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_compress_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCOMPRESSPS" form="xmm {z}, xmm" xed="VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ 	ELSE
+ 		dst[m+63:m] := src[m+63:m]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PD" form="ymm {k}, xmm" xed="VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ 	ELSE
+ 		dst[m+63:m] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PD" form="ymm {z}, xmm" xed="VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ 	ELSE
+ 		dst[m+63:m] := src[m+63:m]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PD" form="xmm {k}, xmm" xed="VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ 	ELSE
+ 		dst[m+63:m] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PD" form="xmm {z}, xmm" xed="VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PS" form="ymm {k}, ymm" xed="VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi32_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PS" form="ymm {z}, ymm" xed="VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PS" form="xmm {k}, xmm" xed="VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi32_ps">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTDQ2PS" form="xmm {z}, xmm" xed="VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	l := j*64
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2DQ" form="xmm {k}, ymm" xed="VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2DQ" form="xmm {z}, ymm" xed="VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	l := j*64
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2DQ" form="xmm {k}, xmm" xed="VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2DQ" form="xmm {z}, xmm" xed="VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtpd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2PS" form="xmm {k}, ymm" xed="VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtpd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	l := j*64
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2PS" form="xmm {z}, ymm" xed="VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtpd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2PS" form="xmm {k}, xmm" xed="VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtpd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	l := j*64
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2PS" form="xmm {z}, xmm" xed="VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UDQ" form="xmm, ymm" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	l := j*64
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UDQ" form="xmm {k}, ymm" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UDQ" form="xmm {z}, ymm" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UDQ" form="xmm, xmm" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	l := j*64
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UDQ" form="xmm {k}, xmm" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPD2UDQ" form="xmm {z}, xmm" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtph_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="FP16"/>
+ 	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*16
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPH2PS" form="ymm {k}, xmm" xed="VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtph_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="FP16"/>
+ 	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*16
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPH2PS" form="ymm {z}, xmm" xed="VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtph_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="FP16"/>
+ 	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*16
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPH2PS" form="xmm {k}, xmm" xed="VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtph_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="FP16"/>
+ 	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*16
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPH2PS" form="xmm {z}, xmm" xed="VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2DQ" form="ymm {k}, ymm" xed="VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2DQ" form="ymm {z}, ymm" xed="VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2DQ" form="xmm {k}, xmm" xed="VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2DQ" form="xmm {z}, xmm" xed="VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvt_roundps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {k}, ymm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {k}, ymm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvt_roundps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {z}, ymm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {z}, ymm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvt_roundps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {k}, xmm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := src[i+15:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {k}, xmm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvt_roundps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {z}, xmm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtps_ph">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_ROUND_MODE"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 16*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ 	ELSE
+ 		dst[i+15:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2PH" form="xmm {z}, xmm, imm8" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UDQ" form="ymm, ymm" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UDQ" form="ymm {k}, ymm" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UDQ" form="ymm {z}, ymm" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UDQ" form="xmm, xmm" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UDQ" form="xmm {k}, xmm" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTPS2UDQ" form="xmm {z}, xmm" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2DQ" form="xmm {k}, ymm" xed="VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2DQ" form="xmm {z}, ymm" xed="VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2DQ" form="xmm {k}, xmm" xed="VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttpd_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2DQ" form="xmm {z}, xmm" xed="VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvttpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UDQ" form="xmm, ymm" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UDQ" form="xmm {k}, ymm" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UDQ" form="xmm {z}, ymm" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvttpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	k := 64*j
+ 	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UDQ" form="xmm, xmm" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UDQ" form="xmm {k}, xmm" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttpd_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 32*j
+ 	l := 64*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPD2UDQ" form="xmm {z}, xmm" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2DQ" form="ymm {k}, ymm" xed="VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2DQ" form="ymm {z}, ymm" xed="VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2DQ" form="xmm {k}, xmm" xed="VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttps_epi32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2DQ" form="xmm {z}, xmm" xed="VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvttps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UDQ" form="ymm, ymm" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvttps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UDQ" form="ymm {k}, ymm" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvttps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UDQ" form="ymm {z}, ymm" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvttps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UDQ" form="xmm, xmm" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvttps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UDQ" form="xmm {k}, xmm" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvttps_epu32">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTTPS2UDQ" form="xmm {z}, xmm" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepu32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUDQ2PD" form="ymm, xmm" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUDQ2PD" form="ymm {k}, xmm" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VCVTUDQ2PD" form="ymm {z}, xmm" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepu32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUDQ2PD" form="xmm, xmm" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUDQ2PD" form="xmm {k}, xmm" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu32_pd">
+ 	<type>Floating Point</type>
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	l := j*32
+ 	IF k[j]
+ 		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VCVTUDQ2PD" form="xmm {z}, xmm" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_div_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDIVPD" form="ymm {k}, ymm, ymm" xed="VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_div_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDIVPD" form="ymm {z}, ymm, ymm" xed="VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_div_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDIVPD" form="xmm {k}, xmm, xmm" xed="VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_div_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDIVPD" form="xmm {z}, xmm, xmm" xed="VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_div_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDIVPS" form="ymm {k}, ymm, ymm" xed="VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_div_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VDIVPS" form="ymm {z}, ymm, ymm" xed="VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_div_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDIVPS" form="xmm {k}, xmm, xmm" xed="VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_div_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VDIVPS" form="xmm {z}, xmm, xmm" xed="VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expand_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="ymm {k}, ymm" xed="VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expandloadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="ymm {k}, m256" xed="VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expand_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="ymm {z}, ymm" xed="VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expandloadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="ymm {z}, m256" xed="VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expand_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="xmm {k}, xmm" xed="VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expandloadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="xmm {k}, m128" xed="VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expand_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="xmm {z}, xmm " xed="VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expandloadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPD" form="xmm {z}, m128" xed="VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expand_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="ymm {k}, ymm" xed="VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expandloadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="ymm {k}, m256" xed="VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expand_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="ymm {z}, ymm" xed="VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expandloadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="ymm {z}, m256" xed="VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expand_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="xmm {k}, xmm" xed="VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expandloadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="xmm {k}, m128" xed="VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expand_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="xmm {z}, xmm" xed="VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expandloadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXPANDPS" form="xmm {z}, m128" xed="VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_extractf32x4_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF32X4" form="xmm, ymm, imm8" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_extractf32x4_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF32X4" form="xmm {k}, ymm, imm8" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_extractf32x4_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTF32X4" form="xmm {z}, ymm, imm8" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_extracti32x4_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: dst[127:0] := a[127:0]
+ 1: dst[127:0] := a[255:128]
+ ESAC
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI32X4" form="xmm, ymm, imm8" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_extracti32x4_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI32X4" form="xmm {k}, ymm, imm8" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_extracti32x4_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ CASE imm8[0] OF
+ 0: tmp[127:0] := a[127:0]
+ 1: tmp[127:0] := a[255:128]
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VEXTRACTI32X4" form="xmm {z}, ymm, imm8" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_fixupimm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+ 	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+ 	CASE(tsrc[63:0]) OF
+ 	QNAN_TOKEN: j := 0
+ 	SNAN_TOKEN: j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[63:0] := src1[63:0]
+ 	1 : dest[63:0] := tsrc[63:0]
+ 	2 : dest[63:0] := QNaN(tsrc[63:0])
+ 	3 : dest[63:0] := QNAN_Indefinite
+ 	4 : dest[63:0] := -INF
+ 	5 : dest[63:0] := +INF
+ 	6 : dest[63:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[63:0] := -0
+ 	8 : dest[63:0] := +0
+ 	9 : dest[63:0] := -1
+ 	10: dest[63:0] := +1
+ 	11: dest[63:0] := 1/2
+ 	12: dest[63:0] := 90.0
+ 	13: dest[63:0] := PI/2
+ 	14: dest[63:0] := MAX_FLOAT
+ 	15: dest[63:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPD" form="ymm, ymm, ymm, imm8" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fixupimm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+ 	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+ 	CASE(tsrc[63:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[63:0] := src1[63:0]
+ 	1 : dest[63:0] := tsrc[63:0]
+ 	2 : dest[63:0] := QNaN(tsrc[63:0])
+ 	3 : dest[63:0] := QNAN_Indefinite
+ 	4 : dest[63:0] := -INF
+ 	5 : dest[63:0] := +INF
+ 	6 : dest[63:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[63:0] := -0
+ 	8 : dest[63:0] := +0
+ 	9 : dest[63:0] := -1
+ 	10: dest[63:0] := +1
+ 	11: dest[63:0] := 1/2
+ 	12: dest[63:0] := 90.0
+ 	13: dest[63:0] := PI/2
+ 	14: dest[63:0] := MAX_FLOAT
+ 	15: dest[63:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPD" form="ymm {k}, ymm, ymm, imm8" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fixupimm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+ 	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+ 	CASE(tsrc[63:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[63:0] := src1[63:0]
+ 	1 : dest[63:0] := tsrc[63:0]
+ 	2 : dest[63:0] := QNaN(tsrc[63:0])
+ 	3 : dest[63:0] := QNAN_Indefinite
+ 	4 : dest[63:0] := -INF
+ 	5 : dest[63:0] := +INF
+ 	6 : dest[63:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[63:0] := -0
+ 	8 : dest[63:0] := +0
+ 	9 : dest[63:0] := -1
+ 	10: dest[63:0] := +1
+ 	11: dest[63:0] := 1/2
+ 	12: dest[63:0] := 90.0
+ 	13: dest[63:0] := PI/2
+ 	14: dest[63:0] := MAX_FLOAT
+ 	15: dest[63:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPD" form="ymm {z}, ymm, ymm, imm8" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_fixupimm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+ 	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+ 	CASE(tsrc[63:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[63:0] := src1[63:0]
+ 	1 : dest[63:0] := tsrc[63:0]
+ 	2 : dest[63:0] := QNaN(tsrc[63:0])
+ 	3 : dest[63:0] := QNAN_Indefinite
+ 	4 : dest[63:0] := -INF
+ 	5 : dest[63:0] := +INF
+ 	6 : dest[63:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[63:0] := -0
+ 	8 : dest[63:0] := +0
+ 	9 : dest[63:0] := -1
+ 	10: dest[63:0] := +1
+ 	11: dest[63:0] := 1/2
+ 	12: dest[63:0] := 90.0
+ 	13: dest[63:0] := PI/2
+ 	14: dest[63:0] := MAX_FLOAT
+ 	15: dest[63:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPD" form="xmm, xmm, xmm, imm8" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fixupimm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+ 	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+ 	CASE(tsrc[63:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[63:0] := src1[63:0]
+ 	1 : dest[63:0] := tsrc[63:0]
+ 	2 : dest[63:0] := QNaN(tsrc[63:0])
+ 	3 : dest[63:0] := QNAN_Indefinite
+ 	4 : dest[63:0] := -INF
+ 	5 : dest[63:0] := +INF
+ 	6 : dest[63:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[63:0] := -0
+ 	8 : dest[63:0] := +0
+ 	9 : dest[63:0] := -1
+ 	10: dest[63:0] := +1
+ 	11: dest[63:0] := 1/2
+ 	12: dest[63:0] := 90.0
+ 	13: dest[63:0] := PI/2
+ 	14: dest[63:0] := MAX_FLOAT
+ 	15: dest[63:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPD" form="xmm {k}, xmm, xmm, imm8" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fixupimm_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+ 	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+ 	CASE(tsrc[63:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[63:0] := src1[63:0]
+ 	1 : dest[63:0] := tsrc[63:0]
+ 	2 : dest[63:0] := QNaN(tsrc[63:0])
+ 	3 : dest[63:0] := QNAN_Indefinite
+ 	4 : dest[63:0] := -INF
+ 	5 : dest[63:0] := +INF
+ 	6 : dest[63:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[63:0] := -0
+ 	8 : dest[63:0] := +0
+ 	9 : dest[63:0] := -1
+ 	10: dest[63:0] := +1
+ 	11: dest[63:0] := 1/2
+ 	12: dest[63:0] := 90.0
+ 	13: dest[63:0] := PI/2
+ 	14: dest[63:0] := MAX_FLOAT
+ 	15: dest[63:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPD" form="xmm {z}, xmm, xmm, imm8" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_fixupimm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+ 	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+ 	CASE(tsrc[31:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[31:0] := src1[31:0]
+ 	1 : dest[31:0] := tsrc[31:0]
+ 	2 : dest[31:0] := QNaN(tsrc[31:0])
+ 	3 : dest[31:0] := QNAN_Indefinite
+ 	4 : dest[31:0] := -INF
+ 	5 : dest[31:0] := +INF
+ 	6 : dest[31:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[31:0] := -0
+ 	8 : dest[31:0] := +0
+ 	9 : dest[31:0] := -1
+ 	10: dest[31:0] := +1
+ 	11: dest[31:0] := 1/2
+ 	12: dest[31:0] := 90.0
+ 	13: dest[31:0] := PI/2
+ 	14: dest[31:0] := MAX_FLOAT
+ 	15: dest[31:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPS" form="ymm, ymm, ymm, imm8" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fixupimm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+ 	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+ 	CASE(tsrc[31:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[31:0] := src1[31:0]
+ 	1 : dest[31:0] := tsrc[31:0]
+ 	2 : dest[31:0] := QNaN(tsrc[31:0])
+ 	3 : dest[31:0] := QNAN_Indefinite
+ 	4 : dest[31:0] := -INF
+ 	5 : dest[31:0] := +INF
+ 	6 : dest[31:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[31:0] := -0
+ 	8 : dest[31:0] := +0
+ 	9 : dest[31:0] := -1
+ 	10: dest[31:0] := +1
+ 	11: dest[31:0] := 1/2
+ 	12: dest[31:0] := 90.0
+ 	13: dest[31:0] := PI/2
+ 	14: dest[31:0] := MAX_FLOAT
+ 	15: dest[31:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPS" form="ymm {k}, ymm, ymm, imm8" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fixupimm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+ 	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+ 	CASE(tsrc[31:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[31:0] := src1[31:0]
+ 	1 : dest[31:0] := tsrc[31:0]
+ 	2 : dest[31:0] := QNaN(tsrc[31:0])
+ 	3 : dest[31:0] := QNAN_Indefinite
+ 	4 : dest[31:0] := -INF
+ 	5 : dest[31:0] := +INF
+ 	6 : dest[31:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[31:0] := -0
+ 	8 : dest[31:0] := +0
+ 	9 : dest[31:0] := -1
+ 	10: dest[31:0] := +1
+ 	11: dest[31:0] := 1/2
+ 	12: dest[31:0] := 90.0
+ 	13: dest[31:0] := PI/2
+ 	14: dest[31:0] := MAX_FLOAT
+ 	15: dest[31:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPS" form="ymm {z}, ymm, ymm, imm8" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_fixupimm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+ 	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+ 	CASE(tsrc[31:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[31:0] := src1[31:0]
+ 	1 : dest[31:0] := tsrc[31:0]
+ 	2 : dest[31:0] := QNaN(tsrc[31:0])
+ 	3 : dest[31:0] := QNAN_Indefinite
+ 	4 : dest[31:0] := -INF
+ 	5 : dest[31:0] := +INF
+ 	6 : dest[31:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[31:0] := -0
+ 	8 : dest[31:0] := +0
+ 	9 : dest[31:0] := -1
+ 	10: dest[31:0] := +1
+ 	11: dest[31:0] := 1/2
+ 	12: dest[31:0] := 90.0
+ 	13: dest[31:0] := PI/2
+ 	14: dest[31:0] := MAX_FLOAT
+ 	15: dest[31:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPS" form="xmm, xmm, xmm, imm8" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fixupimm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+ 	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+ 	CASE(tsrc[31:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[31:0] := src1[31:0]
+ 	1 : dest[31:0] := tsrc[31:0]
+ 	2 : dest[31:0] := QNaN(tsrc[31:0])
+ 	3 : dest[31:0] := QNAN_Indefinite
+ 	4 : dest[31:0] := -INF
+ 	5 : dest[31:0] := +INF
+ 	6 : dest[31:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[31:0] := -0
+ 	8 : dest[31:0] := +0
+ 	9 : dest[31:0] := -1
+ 	10: dest[31:0] := +1
+ 	11: dest[31:0] := 1/2
+ 	12: dest[31:0] := 90.0
+ 	13: dest[31:0] := PI/2
+ 	14: dest[31:0] := MAX_FLOAT
+ 	15: dest[31:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPS" form="xmm {k}, xmm, xmm, imm8" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fixupimm_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+ 	<operation>enum TOKEN_TYPE {
+ 	QNAN_TOKEN := 0, \
+ 	SNAN_TOKEN := 1, \
+ 	ZERO_VALUE_TOKEN := 2, \
+ 	ONE_VALUE_TOKEN := 3, \
+ 	NEG_INF_TOKEN := 4, \
+ 	POS_INF_TOKEN := 5, \
+ 	NEG_VALUE_TOKEN := 6, \
+ 	POS_VALUE_TOKEN := 7
+ }
+ DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+ 	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+ 	CASE(tsrc[31:0]) OF
+ 	QNAN_TOKEN:j := 0
+ 	SNAN_TOKEN:j := 1
+ 	ZERO_VALUE_TOKEN: j := 2
+ 	ONE_VALUE_TOKEN: j := 3
+ 	NEG_INF_TOKEN: j := 4
+ 	POS_INF_TOKEN: j := 5
+ 	NEG_VALUE_TOKEN: j := 6
+ 	POS_VALUE_TOKEN: j := 7
+ 	ESAC
+ 	
+ 	token_response[3:0] := src3[3+4*j:4*j]
+ 	
+ 	CASE(token_response[3:0]) OF
+ 	0 : dest[31:0] := src1[31:0]
+ 	1 : dest[31:0] := tsrc[31:0]
+ 	2 : dest[31:0] := QNaN(tsrc[31:0])
+ 	3 : dest[31:0] := QNAN_Indefinite
+ 	4 : dest[31:0] := -INF
+ 	5 : dest[31:0] := +INF
+ 	6 : dest[31:0] := tsrc.sign? -INF : +INF
+ 	7 : dest[31:0] := -0
+ 	8 : dest[31:0] := +0
+ 	9 : dest[31:0] := -1
+ 	10: dest[31:0] := +1
+ 	11: dest[31:0] := 1/2
+ 	12: dest[31:0] := 90.0
+ 	13: dest[31:0] := PI/2
+ 	14: dest[31:0] := MAX_FLOAT
+ 	15: dest[31:0] := -MAX_FLOAT
+ 	ESAC
+ 	
+ 	CASE(tsrc[31:0]) OF
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[0]) #ZE; FI
+ 	ZERO_VALUE_TOKEN:
+ 		IF (imm8[1]) #IE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[2]) #ZE; FI
+ 	ONE_VALUE_TOKEN:
+ 		IF (imm8[3]) #IE; FI
+ 	SNAN_TOKEN:
+ 		IF (imm8[4]) #IE; FI
+ 	NEG_INF_TOKEN:
+ 		IF (imm8[5]) #IE; FI
+ 	NEG_VALUE_TOKEN:
+ 		IF (imm8[6]) #IE; FI
+ 	POS_INF_TOKEN:
+ 		IF (imm8[7]) #IE; FI
+ 	ESAC
+ 	RETURN dest[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFIXUPIMMPS" form="xmm {z}, xmm, xmm, imm8" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PD" form="ymm {k}, ymm, ymm" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADD213PD" form="ymm {k}, ymm, ymm" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADD231PD" form="ymm {k}, ymm, ymm" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PD" form="ymm {k}, ymm, ymm" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADD213PD" form="ymm {k}, ymm, ymm" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADD231PD" form="ymm {k}, ymm, ymm" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PD" form="ymm {z}, ymm, ymm" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADD213PD" form="ymm {z}, ymm, ymm" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADD231PD" form="ymm {z}, ymm, ymm" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PD" form="xmm {k}, xmm, xmm" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADD213PD" form="xmm {k}, xmm, xmm" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADD231PD" form="xmm {k}, xmm, xmm" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PD" form="xmm {k}, xmm, xmm" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADD213PD" form="xmm {k}, xmm, xmm" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADD231PD" form="xmm {k}, xmm, xmm" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PD" form="xmm {z}, xmm, xmm" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADD213PD" form="xmm {z}, xmm, xmm" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADD231PD" form="xmm {z}, xmm, xmm" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PS" form="ymm {k}, ymm, ymm" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADD213PS" form="ymm {k}, ymm, ymm" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADD231PS" form="ymm {k}, ymm, ymm" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PS" form="ymm {k}, ymm, ymm" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADD213PS" form="ymm {k}, ymm, ymm" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADD231PS" form="ymm {k}, ymm, ymm" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PS" form="ymm {z}, ymm, ymm" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADD213PS" form="ymm {z}, ymm, ymm" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADD231PS" form="ymm {z}, ymm, ymm" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PS" form="xmm {k}, xmm, xmm" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADD213PS" form="xmm {k}, xmm, xmm" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADD231PS" form="xmm {k}, xmm, xmm" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PS" form="xmm {k}, xmm, xmm" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADD213PS" form="xmm {k}, xmm, xmm" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADD231PS" form="xmm {k}, xmm, xmm" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADD132PS" form="xmm {z}, xmm, xmm" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADD213PS" form="xmm {z}, xmm, xmm" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADD231PS" form="xmm {z}, xmm, xmm" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmaddsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PD" form="ymm {k}, ymm, ymm" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB213PD" form="ymm {k}, ymm, ymm" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB231PD" form="ymm {k}, ymm, ymm" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmaddsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PD" form="ymm {k}, ymm, ymm" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB213PD" form="ymm {k}, ymm, ymm" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB231PD" form="ymm {k}, ymm, ymm" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmaddsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PD" form="ymm {z}, ymm, ymm" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB213PD" form="ymm {z}, ymm, ymm" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB231PD" form="ymm {z}, ymm, ymm" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmaddsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PD" form="xmm {k}, xmm, xmm" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB213PD" form="xmm {k}, xmm, xmm" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB231PD" form="xmm {k}, xmm, xmm" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmaddsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PD" form="xmm {k}, xmm, xmm" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB213PD" form="xmm {k}, xmm, xmm" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB231PD" form="xmm {k}, xmm, xmm" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmaddsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PD" form="xmm {z}, xmm, xmm" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB213PD" form="xmm {z}, xmm, xmm" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMADDSUB231PD" form="xmm {z}, xmm, xmm" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmaddsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PS" form="ymm {k}, ymm, ymm" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB213PS" form="ymm {k}, ymm, ymm" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB231PS" form="ymm {k}, ymm, ymm" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmaddsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PS" form="ymm {k}, ymm, ymm" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB213PS" form="ymm {k}, ymm, ymm" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB231PS" form="ymm {k}, ymm, ymm" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmaddsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PS" form="ymm {z}, ymm, ymm" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB213PS" form="ymm {z}, ymm, ymm" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB231PS" form="ymm {z}, ymm, ymm" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmaddsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PS" form="xmm {k}, xmm, xmm" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB213PS" form="xmm {k}, xmm, xmm" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB231PS" form="xmm {k}, xmm, xmm" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmaddsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PS" form="xmm {k}, xmm, xmm" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB213PS" form="xmm {k}, xmm, xmm" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB231PS" form="xmm {k}, xmm, xmm" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmaddsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMADDSUB132PS" form="xmm {z}, xmm, xmm" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB213PS" form="xmm {z}, xmm, xmm" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMADDSUB231PS" form="xmm {z}, xmm, xmm" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PD" form="ymm {k}, ymm, ymm" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUB213PD" form="ymm {k}, ymm, ymm" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUB231PD" form="ymm {k}, ymm, ymm" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PD" form="ymm {k}, ymm, ymm" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUB213PD" form="ymm {k}, ymm, ymm" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUB231PD" form="ymm {k}, ymm, ymm" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PD" form="ymm {z}, ymm, ymm" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUB213PD" form="ymm {z}, ymm, ymm" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUB231PD" form="ymm {z}, ymm, ymm" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PD" form="xmm {k}, xmm, xmm" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUB213PD" form="xmm {k}, xmm, xmm" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUB231PD" form="xmm {k}, xmm, xmm" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PD" form="xmm {k}, xmm, xmm" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUB213PD" form="xmm {k}, xmm, xmm" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUB231PD" form="xmm {k}, xmm, xmm" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PD" form="xmm {z}, xmm, xmm" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUB213PD" form="xmm {z}, xmm, xmm" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUB231PD" form="xmm {z}, xmm, xmm" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PS" form="ymm {k}, ymm, ymm" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUB213PS" form="ymm {k}, ymm, ymm" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUB231PS" form="ymm {k}, ymm, ymm" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PS" form="ymm {k}, ymm, ymm" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUB213PS" form="ymm {k}, ymm, ymm" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUB231PS" form="ymm {k}, ymm, ymm" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PS" form="ymm {z}, ymm, ymm" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUB213PS" form="ymm {z}, ymm, ymm" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUB231PS" form="ymm {z}, ymm, ymm" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PS" form="xmm {k}, xmm, xmm" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUB213PS" form="xmm {k}, xmm, xmm" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUB231PS" form="xmm {k}, xmm, xmm" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PS" form="xmm {k}, xmm, xmm" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUB213PS" form="xmm {k}, xmm, xmm" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUB231PS" form="xmm {k}, xmm, xmm" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUB132PS" form="xmm {z}, xmm, xmm" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUB213PS" form="xmm {z}, xmm, xmm" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUB231PS" form="xmm {z}, xmm, xmm" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmsubadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PD" form="ymm {k}, ymm, ymm" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD213PD" form="ymm {k}, ymm, ymm" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD231PD" form="ymm {k}, ymm, ymm" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmsubadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PD" form="ymm {k}, ymm, ymm" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD213PD" form="ymm {k}, ymm, ymm" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD231PD" form="ymm {k}, ymm, ymm" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmsubadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PD" form="ymm {z}, ymm, ymm" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD213PD" form="ymm {z}, ymm, ymm" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD231PD" form="ymm {z}, ymm, ymm" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmsubadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PD" form="xmm {k}, xmm, xmm" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD213PD" form="xmm {k}, xmm, xmm" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD231PD" form="xmm {k}, xmm, xmm" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmsubadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1 
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PD" form="xmm {k}, xmm, xmm" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD213PD" form="xmm {k}, xmm, xmm" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD231PD" form="xmm {k}, xmm, xmm" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmsubadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PD" form="xmm {z}, xmm, xmm" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD213PD" form="xmm {z}, xmm, xmm" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFMSUBADD231PD" form="xmm {z}, xmm, xmm" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fmsubadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PS" form="ymm {k}, ymm, ymm" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD213PS" form="ymm {k}, ymm, ymm" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD231PS" form="ymm {k}, ymm, ymm" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fmsubadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PS" form="ymm {k}, ymm, ymm" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD213PS" form="ymm {k}, ymm, ymm" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD231PS" form="ymm {k}, ymm, ymm" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fmsubadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PS" form="ymm {z}, ymm, ymm" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD213PS" form="ymm {z}, ymm, ymm" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD231PS" form="ymm {z}, ymm, ymm" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fmsubadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PS" form="xmm {k}, xmm, xmm" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD213PS" form="xmm {k}, xmm, xmm" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD231PS" form="xmm {k}, xmm, xmm" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fmsubadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PS" form="xmm {k}, xmm, xmm" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD213PS" form="xmm {k}, xmm, xmm" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD231PS" form="xmm {k}, xmm, xmm" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fmsubadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF ((j &amp; 1) == 0) 
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFMSUBADD132PS" form="xmm {z}, xmm, xmm" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD213PS" form="xmm {z}, xmm, xmm" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFMSUBADD231PS" form="xmm {z}, xmm, xmm" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fnmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PD" form="ymm {k}, ymm, ymm" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMADD213PD" form="ymm {k}, ymm, ymm" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMADD231PD" form="ymm {k}, ymm, ymm" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fnmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PD" form="ymm {k}, ymm, ymm" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMADD213PD" form="ymm {k}, ymm, ymm" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMADD231PD" form="ymm {k}, ymm, ymm" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fnmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PD" form="ymm {z}, ymm, ymm" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMADD213PD" form="ymm {z}, ymm, ymm" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMADD231PD" form="ymm {z}, ymm, ymm" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fnmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PD" form="xmm {k}, xmm, xmm" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMADD213PD" form="xmm {k}, xmm, xmm" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMADD231PD" form="xmm {k}, xmm, xmm" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fnmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PD" form="xmm {k}, xmm, xmm" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMADD213PD" form="xmm {k}, xmm, xmm" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMADD231PD" form="xmm {k}, xmm, xmm" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fnmadd_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PD" form="xmm {z}, xmm, xmm" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMADD213PD" form="xmm {z}, xmm, xmm" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMADD231PD" form="xmm {z}, xmm, xmm" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fnmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PS" form="ymm {k}, ymm, ymm" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMADD213PS" form="ymm {k}, ymm, ymm" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMADD231PS" form="ymm {k}, ymm, ymm" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fnmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PS" form="ymm {k}, ymm, ymm" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMADD213PS" form="ymm {k}, ymm, ymm" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMADD231PS" form="ymm {k}, ymm, ymm" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fnmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PS" form="ymm {z}, ymm, ymm" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMADD213PS" form="ymm {z}, ymm, ymm" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMADD231PS" form="ymm {z}, ymm, ymm" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fnmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PS" form="xmm {k}, xmm, xmm" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMADD213PS" form="xmm {k}, xmm, xmm" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMADD231PS" form="xmm {k}, xmm, xmm" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fnmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PS" form="xmm {k}, xmm, xmm" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMADD213PS" form="xmm {k}, xmm, xmm" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMADD231PS" form="xmm {k}, xmm, xmm" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fnmadd_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMADD132PS" form="xmm {z}, xmm, xmm" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMADD213PS" form="xmm {z}, xmm, xmm" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMADD231PS" form="xmm {z}, xmm, xmm" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fnmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PD" form="ymm {k}, ymm, ymm" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB213PD" form="ymm {k}, ymm, ymm" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB231PD" form="ymm {k}, ymm, ymm" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fnmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PD" form="ymm {k}, ymm, ymm" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB213PD" form="ymm {k}, ymm, ymm" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB231PD" form="ymm {k}, ymm, ymm" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fnmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="__m256d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PD" form="ymm {z}, ymm, ymm" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB213PD" form="ymm {z}, ymm, ymm" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB231PD" form="ymm {z}, ymm, ymm" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fnmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := c[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PD" form="xmm {k}, xmm, xmm" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB213PD" form="xmm {k}, xmm, xmm" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB231PD" form="xmm {k}, xmm, xmm" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fnmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PD" form="xmm {k}, xmm, xmm" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB213PD" form="xmm {k}, xmm, xmm" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB231PD" form="xmm {k}, xmm, xmm" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fnmsub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="__m128d" varname="c" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PD" form="xmm {z}, xmm, xmm" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB213PD" form="xmm {z}, xmm, xmm" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VFNMSUB231PD" form="xmm {z}, xmm, xmm" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask3_fnmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PS" form="ymm {k}, ymm, ymm" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB213PS" form="ymm {k}, ymm, ymm" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB231PS" form="ymm {k}, ymm, ymm" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_fnmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PS" form="ymm {k}, ymm, ymm" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB213PS" form="ymm {k}, ymm, ymm" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB231PS" form="ymm {k}, ymm, ymm" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_fnmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="__m256" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PS" form="ymm {z}, ymm, ymm" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB213PS" form="ymm {z}, ymm, ymm" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB231PS" form="ymm {z}, ymm, ymm" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask3_fnmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := c[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PS" form="xmm {k}, xmm, xmm" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB213PS" form="xmm {k}, xmm, xmm" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB231PS" form="xmm {k}, xmm, xmm" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_fnmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PS" form="xmm {k}, xmm, xmm" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB213PS" form="xmm {k}, xmm, xmm" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB231PS" form="xmm {k}, xmm, xmm" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_fnmsub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="__m128" varname="c" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VFNMSUB132PS" form="xmm {z}, xmm, xmm" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB213PS" form="xmm {z}, xmm, xmm" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VFNMSUB231PS" form="xmm {z}, xmm, xmm" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i32gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPD" form="ymm {k}, vm32x" xed="VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i32gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPD" form="xmm {k}, vm32x" xed="VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i32gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPS" form="ymm {k}, vm32y" xed="VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i32gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERDPS" form="xmm {k}, vm32x" xed="VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i64gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPD" form="ymm {k}, vm64y" xed="VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i64gather_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPD" form="xmm {k}, vm64x" xed="VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i64gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPS" form="ymm {k}, vm64y" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i64gather_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VGATHERQPS" form="xmm {k}, vm64x" xed="VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_getexp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPD" form="ymm, ymm" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_getexp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPD" form="ymm {k}, ymm" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_getexp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPD" form="ymm {z}, ymm" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_getexp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPD" form="xmm, xmm" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_getexp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPD" form="xmm {k}, xmm" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_getexp_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPD" form="xmm {z}, xmm" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_getexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPS" form="ymm, ymm" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_getexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPS" form="ymm {k}, ymm" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_getexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPS" form="ymm {z}, ymm" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_getexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPS" form="xmm, xmm" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_getexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPS" form="xmm {k}, xmm" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_getexp_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETEXPPS" form="xmm {z}, xmm" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_getmant_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPD" form="ymm, ymm, imm8" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_getmant_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPD" form="ymm {k}, ymm, imm8" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_getmant_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPD" form="ymm {z}, ymm, imm8" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_getmant_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPD" form="xmm, xmm, imm8" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_getmant_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPD" form="xmm {k}, xmm, imm8" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_getmant_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPD" form="xmm {z}, xmm, imm8" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_getmant_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPS" form="ymm, ymm, imm8" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_getmant_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPS" form="ymm {k}, ymm, imm8" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_getmant_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPS" form="ymm {z}, ymm, imm8" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_getmant_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPS" form="xmm, xmm, imm8" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_getmant_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPS" form="xmm {k}, xmm, imm8" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_getmant_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="_MM_MANTISSA_NORM_ENUM" varname="interv" etype="IMM" immtype="_MM_MANTISSA_NORM"/>
+ 	<parameter type="_MM_MANTISSA_SIGN_ENUM" varname="sc" etype="IMM" immtype="_MM_MANTISSA_SIGN"/>
+ 	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+ 	[getmant_note]</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VGETMANTPS" form="xmm {z}, xmm, imm8" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_insertf32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF32X4" form="ymm, ymm, xmm, imm8" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_insertf32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF32X4" form="ymm {k}, ymm, xmm, imm8" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_insertf32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTF32X4" form="ymm {z}, ymm, xmm, imm8" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_inserti32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+ 	<operation>
+ dst[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: dst[127:0] := b[127:0]
+ 1: dst[255:128] := b[127:0]
+ ESAC
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI32X4" form="ymm, ymm, xmm, imm8" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_inserti32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI32X4" form="ymm {k}, ymm, xmm, imm8" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_inserti32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="1"/>
+ 	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[255:0] := a[255:0]
+ CASE (imm8[0]) OF
+ 0: tmp[127:0] := b[127:0]
+ 1: tmp[255:128] := b[127:0]
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VINSERTI32X4" form="ymm {z}, ymm, xmm, imm8" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMAXPD" form="ymm {k}, ymm, ymm" xed="VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMAXPD" form="ymm {z}, ymm, ymm" xed="VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMAXPD" form="xmm {k}, xmm, xmm" xed="VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMAXPD" form="xmm {z}, xmm, xmm" xed="VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMAXPS" form="ymm {k}, ymm, ymm" xed="VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMAXPS" form="ymm {z}, ymm, ymm" xed="VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMAXPS" form="xmm {k}, xmm, xmm" xed="VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMAXPS" form="xmm {z}, xmm, xmm" xed="VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMINPD" form="ymm {k}, ymm, ymm" xed="VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMINPD" form="ymm {z}, ymm, ymm" xed="VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMINPD" form="xmm {k}, xmm, xmm" xed="VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMINPD" form="xmm {z}, xmm, xmm" xed="VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMINPS" form="ymm {k}, ymm, ymm" xed="VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMINPS" form="ymm {z}, ymm, ymm" xed="VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMINPS" form="xmm {k}, xmm, xmm" xed="VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMINPS" form="xmm {z}, xmm, xmm" xed="VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_load_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="ymm {k}, m64" xed="VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mov_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="ymm {k}, ymm" xed="VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_store_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="m256 {k}, ymm" xed="VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_load_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="ymm {z}, m256" xed="VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mov_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="ymm {z}, ymm" xed="VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_load_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="xmm {k}, m128" xed="VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mov_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="xmm {k}, xmm" xed="VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_store_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="m128 {k}, xmm" xed="VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_load_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="xmm {z}, m128" xed="VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mov_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPD" form="xmm {z}, xmm" xed="VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_load_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="ymm {k}, m256" xed="VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mov_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="ymm {k}, ymm" xed="VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_store_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="m256 {k}, ymm" xed="VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_load_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="ymm {z}, m256" xed="VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mov_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="ymm {z}, ymm" xed="VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_load_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="xmm {k}, m128" xed="VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mov_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="xmm {k}, xmm" xed="VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_store_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="m128 {k}, xmm" xed="VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_load_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="xmm {z}, m128" xed="VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mov_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVAPS" form="xmm {z}, xmm" xed="VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_movedup_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[63:0] := a[63:0]
+ tmp[127:64] := a[63:0]
+ tmp[191:128] := a[191:128]
+ tmp[255:192] := a[191:128]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDDUP" form="ymm {k}, ymm" xed="VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_movedup_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[63:0] := a[63:0]
+ tmp[127:64] := a[63:0]
+ tmp[191:128] := a[191:128]
+ tmp[255:192] := a[191:128]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDDUP" form="ymm {z}, ymm" xed="VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_movedup_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[63:0] := a[63:0]
+ tmp[127:64] := a[63:0]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDDUP" form="xmm {k}, xmm" xed="VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_movedup_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[63:0] := a[63:0]
+ tmp[127:64] := a[63:0]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDDUP" form="xmm {z}, xmm" xed="VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_load_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="ymm {k}, m64" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mov_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="ymm {k}, ymm" xed="VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_store_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="m256 {k}, ymm" xed="VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_load_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="ymm {z}, m64" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mov_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="ymm {z}, ymm" xed="VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_load_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="xmm {k}, m64" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mov_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="xmm {k}, xmm" xed="VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_store_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="m128 {k}, xmm" xed="VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_load_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="xmm {z}, m64" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mov_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="xmm {z}, xmm" xed="VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_load_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="ymm {k}, m64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mov_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="ymm {k}, ymm" xed="VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_store_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="m256 {k}, ymm" xed="VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_load_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="ymm {z}, m64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mov_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="ymm {z}, ymm" xed="VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_load_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="xmm {k}, m64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mov_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="xmm {k}, xmm" xed="VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_store_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="m128 {k}, xmm" xed="VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_load_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+ 	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="xmm {z}, m64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mov_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="xmm {z}, xmm" xed="VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="ymm {k}, m64" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="m256 {k}, ymm" xed="VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="ymm {z}, m64" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="xmm {k}, m64" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="m128 {k}, xmm" xed="VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="xmm {z}, m64" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="ymm {k}, m64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_storeu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="m256 {k}, ymm" xed="VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="ymm {z}, m64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="xmm {k}, m64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_storeu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="m128 {k}, xmm" xed="VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="xmm {z}, m64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_movehdup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[63:32] 
+ tmp[63:32] := a[63:32] 
+ tmp[95:64] := a[127:96] 
+ tmp[127:96] := a[127:96]
+ tmp[159:128] := a[191:160] 
+ tmp[191:160] := a[191:160] 
+ tmp[223:192] := a[255:224] 
+ tmp[255:224] := a[255:224]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVSHDUP" form="ymm {k}, ymm" xed="VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_movehdup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[63:32] 
+ tmp[63:32] := a[63:32] 
+ tmp[95:64] := a[127:96] 
+ tmp[127:96] := a[127:96]
+ tmp[159:128] := a[191:160] 
+ tmp[191:160] := a[191:160] 
+ tmp[223:192] := a[255:224] 
+ tmp[255:224] := a[255:224]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVSHDUP" form="ymm {z}, ymm" xed="VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_movehdup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[63:32] 
+ tmp[63:32] := a[63:32] 
+ tmp[95:64] := a[127:96] 
+ tmp[127:96] := a[127:96]
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVSHDUP" form="xmm {k}, xmm" xed="VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_movehdup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[63:32] 
+ tmp[63:32] := a[63:32] 
+ tmp[95:64] := a[127:96] 
+ tmp[127:96] := a[127:96]
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVSHDUP" form="xmm {z}, xmm" xed="VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_moveldup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] 
+ tmp[63:32] := a[31:0] 
+ tmp[95:64] := a[95:64] 
+ tmp[127:96] := a[95:64]
+ tmp[159:128] := a[159:128] 
+ tmp[191:160] := a[159:128] 
+ tmp[223:192] := a[223:192] 
+ tmp[255:224] := a[223:192]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVSLDUP" form="ymm {k}, ymm" xed="VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_moveldup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] 
+ tmp[63:32] := a[31:0] 
+ tmp[95:64] := a[95:64] 
+ tmp[127:96] := a[95:64]
+ tmp[159:128] := a[159:128] 
+ tmp[191:160] := a[159:128] 
+ tmp[223:192] := a[223:192] 
+ tmp[255:224] := a[223:192]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVSLDUP" form="ymm {z}, ymm" xed="VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_moveldup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] 
+ tmp[63:32] := a[31:0] 
+ tmp[95:64] := a[95:64] 
+ tmp[127:96] := a[95:64]
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR	
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVSLDUP" form="xmm {k}, xmm" xed="VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_moveldup_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Move</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp[31:0] := a[31:0] 
+ tmp[63:32] := a[31:0] 
+ tmp[95:64] := a[95:64] 
+ tmp[127:96] := a[95:64]
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVSLDUP" form="xmm {z}, xmm" xed="VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_loadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="ymm {k}, m64" xed="VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_storeu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="m256 {k}, ymm" xed="VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_loadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="256"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="ymm {z}, m64" xed="VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_loadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="xmm {k}, m64" xed="VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_storeu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="m128 {k}, xmm" xed="VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_loadu_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP64" memwidth="128"/>
+ 	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPD" form="xmm {z}, m64" xed="VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_loadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="ymm {k}, m64" xed="VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_storeu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="m256 {k}, ymm" xed="VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_loadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="256"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="ymm {z}, m64" xed="VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_loadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="xmm {k}, m64" xed="VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_storeu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="m128 {k}, xmm" xed="VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_loadu_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="FP32" memwidth="128"/>
+ 	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+ 	"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVUPS" form="xmm {z}, m64" xed="VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mul_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMULPD" form="ymm {k}, ymm, ymm" xed="VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mul_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMULPD" form="ymm {z}, ymm, ymm" xed="VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mul_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMULPD" form="xmm {k}, xmm, xmm" xed="VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mul_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMULPD" form="xmm {z}, xmm, xmm" xed="VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mul_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMULPS" form="ymm {k}, ymm, ymm" xed="VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mul_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMULPS" form="ymm {z}, ymm, ymm" xed="VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mul_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMULPS" form="xmm {k}, xmm, xmm" xed="VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mul_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMULPS" form="xmm {z}, xmm, xmm" xed="VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_abs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ABS(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSD" form="ymm {k}, ymm" xed="VPABSD_YMMi32_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_abs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ABS(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSD" form="ymm {z}, ymm" xed="VPABSD_YMMi32_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_abs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ABS(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSD" form="xmm {k}, xmm" xed="VPABSD_XMMi32_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_abs_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ABS(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSD" form="xmm {z}, xmm" xed="VPABSD_XMMi32_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_abs_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := ABS(a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSQ" form="ymm, ymm" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_abs_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ABS(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSQ" form="ymm {k}, ymm" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_abs_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ABS(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPABSQ" form="ymm {z}, ymm" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_abs_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := ABS(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSQ" form="xmm, xmm" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_abs_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ABS(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSQ" form="xmm {k}, xmm" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_abs_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ABS(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPABSQ" form="xmm {z}, xmm" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_add_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDD" form="ymm {k}, ymm, ymm" xed="VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_add_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDD" form="ymm {z}, ymm, ymm" xed="VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_add_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDD" form="xmm {k}, xmm, xmm" xed="VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_add_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDD" form="xmm {z}, xmm, xmm" xed="VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_add_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDQ" form="ymm {k}, ymm, ymm" xed="VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_add_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] :=0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPADDQ" form="ymm {z}, ymm, ymm" xed="VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_add_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDQ" form="xmm {k}, xmm, xmm" xed="VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_add_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPADDQ" form="xmm {z}, xmm, xmm" xed="VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_and_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDD" form="ymm {k}, ymm, ymm" xed="VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_and_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDD" form="ymm {z}, ymm, ymm" xed="VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_and_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDD" form="xmm {k}, xmm, xmm" xed="VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_and_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDD" form="xmm {z}, xmm, xmm" xed="VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_andnot_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDND" form="ymm {k}, ymm, ymm" xed="VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_andnot_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDND" form="ymm {z}, ymm, ymm" xed="VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_andnot_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDND" form="xmm {k}, xmm, xmm" xed="VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_andnot_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDND" form="xmm {z}, xmm, xmm" xed="VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_andnot_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDNQ" form="ymm {k}, ymm, ymm" xed="VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_andnot_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDNQ" form="ymm {z}, ymm, ymm" xed="VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_andnot_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDNQ" form="xmm {k}, xmm, xmm" xed="VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_andnot_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDNQ" form="xmm {z}, xmm, xmm" xed="VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_and_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDQ" form="ymm {k}, ymm, ymm" xed="VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_and_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPANDQ" form="ymm {z}, ymm, ymm" xed="VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_and_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDQ" form="xmm {k}, xmm, xmm" xed="VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_and_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPANDQ" form="xmm {z}, xmm, xmm" xed="VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_blend_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMD" form="ymm {k}, ymm, ymm" xed="VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_blend_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMD" form="xmm {k}, xmm, xmm" xed="VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_blend_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMQ" form="ymm {k}, ymm, ymm" xed="VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_blend_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBLENDMQ" form="xmm {k}, xmm, xmm" xed="VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcastd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="ymm {k}, xmm" xed="VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_set1_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="int" varname="a" etype="UI32"/>
+ 	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="ymm {k}, r32" xed="VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcastd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="ymm {z}, xmm" xed="VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_set1_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="int" varname="a" etype="UI32"/>
+ 	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="ymm {z}, r32" xed="VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_broadcastd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="xmm {k}, xmm" xed="VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_set1_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="int" varname="a" etype="UI32"/>
+ 	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="xmm {k}, r32" xed="VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_broadcastd_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="xmm {z}, xmm" xed="VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_set1_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="int" varname="a" etype="UI32"/>
+ 	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTD" form="xmm {z}, r32" xed="VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_broadcastq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="ymm {k}, xmm" xed="VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_set1_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__int64" varname="a" etype="UI64"/>
+ 	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="ymm {k}, r64" xed="VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_broadcastq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="ymm {z}, xmm" xed="VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_set1_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__int64" varname="a" etype="UI64"/>
+ 	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="ymm {z}, r64" xed="VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_broadcastq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="xmm {k}, xmm" xed="VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_set1_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__int64" varname="a" etype="UI64"/>
+ 	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="xmm {k}, r64" xed="VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_broadcastq_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="xmm {z}, xmm" xed="VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_set1_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Set</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__int64" varname="a" etype="UI64"/>
+ 	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[63:0]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPBROADCASTQ" form="xmm {z}, r64" xed="VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm, imm8" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm, imm8" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, ymm, ymm" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm, imm8" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm, imm8" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPD" form="k {k}, xmm, xmm" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm, imm8" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm, imm8" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, ymm, ymm" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm, imm8" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm, imm8" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPQ" form="k {k}, xmm, xmm" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm, imm8" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm, imm8" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, ymm, ymm" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm, imm8" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm, imm8" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epu32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUD" form="k {k}, xmm, xmm" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmp_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm, imm8" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpeq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpge_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpgt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmple_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmplt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cmpneq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmp_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm, imm8" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpeq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpge_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpgt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmple_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmplt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cmpneq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, ymm, ymm" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmp_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm, imm8" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpeq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpge_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpgt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmple_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmplt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cmpneq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmp_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="_MM_CMPINT_ENUM" varname="imm8" etype="IMM" immtype="_MM_CMPINT"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>CASE (imm8[2:0]) OF
+ 0: OP := _MM_CMPINT_EQ
+ 1: OP := _MM_CMPINT_LT
+ 2: OP := _MM_CMPINT_LE
+ 3: OP := _MM_CMPINT_FALSE
+ 4: OP := _MM_CMPINT_NE
+ 5: OP := _MM_CMPINT_NLT
+ 6: OP := _MM_CMPINT_NLE
+ 7: OP := _MM_CMPINT_TRUE
+ ESAC
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm, imm8" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpeq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpge_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpgt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmple_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmplt_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cmpneq_epu64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ 	ELSE 
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPCMPUQ" form="k {k}, xmm, xmm" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compress_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := src[255:m]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSD" form="ymm {k}, ymm" xed="VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compressstoreu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 32
+ m := base_addr
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPCOMPRESSD" form="m256 {k}, ymm" xed="VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_compress_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSD" form="ymm {z}, ymm" xed="VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compress_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := src[127:m]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSD" form="xmm {k}, xmm" xed="VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compressstoreu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 32
+ m := base_addr
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPCOMPRESSD" form="m128 {k}, xmm" xed="VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_compress_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 32
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+31:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSD" form="xmm {z}, xmm" xed="VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compress_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := src[255:m]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSQ" form="ymm {k}, ymm" xed="VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_compressstoreu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 64
+ m := base_addr
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPCOMPRESSQ" form="m256 {k}, ymm" xed="VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_compress_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[255:m] := 0
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSQ" form="ymm {z}, ymm" xed="VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compress_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := src[127:m]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSQ" form="xmm {k}, xmm" xed="VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_compressstoreu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ size := 64
+ m := base_addr
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		MEM[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPCOMPRESSQ" form="m128 {k}, xmm" xed="VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_compress_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+ 	<operation>
+ size := 64
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[m+size-1:m] := a[i+63:i]
+ 		m := m + size
+ 	FI
+ ENDFOR
+ dst[127:m] := 0
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPCOMPRESSQ" form="xmm {z}, xmm" xed="VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutexvar_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[id+31:id]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMD" form="ymm {k}, ymm, ymm" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutexvar_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[id+31:id]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMD" form="ymm {z}, ymm, ymm" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutexvar_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	dst[i+31:i] := a[id+31:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMD" form="ymm, ymm, ymm" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask2_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := idx[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2D" form="ymm {k}, ymm, ymm" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2D" form="ymm {k}, ymm, ymm" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2D" form="ymm {z}, ymm, ymm" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<instruction name="VPERMT2D" form="ymm {z}, ymm, ymm" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2D" form="ymm, ymm, ymm" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<instruction name="VPERMT2D" form="ymm, ymm, ymm" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask2_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := idx[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2D" form="xmm {k}, xmm, xmm" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2D" form="xmm {k}, xmm, xmm" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2D" form="xmm {z}, xmm, xmm" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<instruction name="VPERMT2D" form="xmm {z}, xmm, xmm" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_permutex2var_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2D" form="xmm, xmm, xmm" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<instruction name="VPERMT2D" form="xmm, xmm, xmm" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask2_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := idx[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PD" form="ymm {k}, ymm, ymm" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2PD" form="ymm {k}, ymm, ymm" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PD" form="ymm {z}, ymm, ymm" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VPERMT2PD" form="ymm {z}, ymm, ymm" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PD" form="ymm, ymm, ymm" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<instruction name="VPERMT2PD" form="ymm, ymm, ymm" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask2_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set)</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := idx[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PD" form="xmm {k}, xmm, xmm" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2PD" form="xmm {k}, xmm, xmm" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PD" form="xmm {z}, xmm, xmm" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VPERMT2PD" form="xmm {z}, xmm, xmm" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_permutex2var_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PD" form="xmm, xmm, xmm" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<instruction name="VPERMT2PD" form="xmm, xmm, xmm" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask2_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := idx[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PS" form="ymm {k}, ymm, ymm" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2PS" form="ymm {k}, ymm, ymm" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PS" form="ymm {z}, ymm, ymm" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VPERMT2PS" form="ymm {z}, ymm, ymm" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	off := idx[i+2:i]*32
+ 	dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PS" form="ymm, ymm, ymm" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<instruction name="VPERMT2PS" form="ymm, ymm, ymm" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask2_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := idx[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PS" form="xmm {k}, xmm, xmm" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := a[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2PS" form="xmm {k}, xmm, xmm" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PS" form="xmm {z}, xmm, xmm" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VPERMT2PS" form="xmm {z}, xmm, xmm" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_permutex2var_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	off := idx[i+1:i]*32
+ 	dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2PS" form="xmm, xmm, xmm" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<instruction name="VPERMT2PS" form="xmm, xmm, xmm" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask2_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := idx[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2Q" form="ymm {k}, ymm, ymm" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2Q" form="ymm {k}, ymm, ymm" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2Q" form="ymm {z}, ymm, ymm" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<instruction name="VPERMT2Q" form="ymm {z}, ymm, ymm" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	off := idx[i+1:i]*64
+ 	dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2Q" form="ymm, ymm, ymm" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<instruction name="VPERMT2Q" form="ymm, ymm, ymm" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask2_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := idx[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2Q" form="xmm {k}, xmm, xmm" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := a[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMT2Q" form="xmm {k}, xmm, xmm" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2Q" form="xmm {z}, xmm, xmm" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<instruction name="VPERMT2Q" form="xmm {z}, xmm, xmm" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_permutex2var_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	off := idx[i]*64
+ 	dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMI2Q" form="xmm, xmm, xmm" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<instruction name="VPERMT2Q" form="xmm, xmm, xmm" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permute_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+ IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
+ IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
+ IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
+ IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="ymm {k}, ymm, imm8" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutevar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+ IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
+ IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
+ IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
+ IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="ymm {k}, ymm, ymm" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permute_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+ IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
+ IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
+ IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
+ IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="ymm {z}, ymm, imm8" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutevar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+ IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
+ IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
+ IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
+ IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="ymm {z}, ymm, ymm" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permute_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="xmm {k}, xmm, imm8" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutevar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="xmm {k}, xmm, xmm" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permute_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="xmm {z}, xmm, imm8" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutevar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+ IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+ IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+ IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPD" form="xmm {z}, xmm, xmm" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permute_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+ tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="ymm {k}, ymm, imm8" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutevar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+ tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+ tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+ tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
+ tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
+ tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
+ tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="ymm {k}, ymm, ymm" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permute_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+ tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="ymm {z}, ymm, imm8" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutevar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+ tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+ tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+ tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
+ tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
+ tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
+ tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="ymm {z}, ymm, ymm" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permute_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="xmm {k}, xmm, imm8" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_permutevar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+ tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+ tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="xmm {k}, xmm, xmm" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permute_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="xmm {z}, xmm, imm8" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_permutevar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+ tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+ tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPERMILPS" form="xmm {z}, xmm, xmm" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm {k}, ymm, imm8" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutexvar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	id := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[id+63:id]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm {k}, ymm, ymm" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm {z}, ymm, imm8" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutexvar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	id := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[id+63:id]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm {z}, ymm, ymm" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm, ymm, imm8" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutexvar_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	id := idx[i+1:i]*64
+ 	dst[i+63:i] := a[id+63:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPD" form="ymm, ymm, ymm" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutexvar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[id+31:id]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPS" form="ymm {k}, ymm, ymm" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutexvar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[id+31:id]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPS" form="ymm {z}, ymm, ymm" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutexvar_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	id := idx[i+2:i]*32
+ 	dst[i+31:i] := a[id+31:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMPS" form="ymm, ymm, ymm" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutex_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm {k}, ymm, imm8" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_permutexvar_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	id := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[id+63:id]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm {k}, ymm, ymm" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutex_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm {z}, ymm, imm8" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_permutexvar_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	id := idx[i+1:i]*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[id+63:id]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm {z}, ymm, ymm" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutex_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[63:0] := src[63:0]
+ 	1:	tmp[63:0] := src[127:64]
+ 	2:	tmp[63:0] := src[191:128]
+ 	3:	tmp[63:0] := src[255:192]
+ 	ESAC
+ 	RETURN tmp[63:0]
+ }
+ dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+ dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+ dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+ dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm, ymm, imm8" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_permutexvar_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="idx" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	id := idx[i+1:i]*64
+ 	dst[i+63:i] := a[id+63:id]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPERMQ" form="ymm, ymm, ymm" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expand_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="ymm {k}, ymm" xed="VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expandloadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="ymm {k}, m64" xed="VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expand_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="ymm {z}, ymm" xed="VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expandloadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="ymm {z}, m64" xed="VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expand_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="xmm {k}, xmm" xed="VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expandloadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="xmm {k}, m64" xed="VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expand_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[m+31:m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="xmm {z}, xmm" xed="VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expandloadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+ 		m := m + 32
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDD" form="xmm {z}, m64" xed="VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expand_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="ymm {k}, ymm" xed="VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_expandloadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="ymm {k}, m64" xed="VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expand_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="ymm {z}, ymm" xed="VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_expandloadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="ymm {z}, m64" xed="VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expand_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="xmm {k}, xmm" xed="VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_expandloadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="xmm {k}, m64" xed="VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expand_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[m+63:m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="xmm {z}, xmm" xed="VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_expandloadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ m := 0
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+ 		m := m + 64
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPEXPANDQ" form="xmm {z}, m64" xed="VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i32gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDD" form="ymm {k}, vm32y" xed="VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i32gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDD" form="xmm {k}, vm32x" xed="VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i32gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDQ" form="ymm {k}, vm32x" xed="VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i32gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERDQ" form="xmm {k}, vm32x" xed="VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i64gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQD" form="xmm {k}, vm64y" xed="VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i64gather_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+31:i] := MEM[addr+31:addr]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQD" form="xmm {k}, vm64x" xed="VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mmask_i64gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQQ" form="ymm {k}, vm64y" xed="VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mmask_i64gather_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="void const*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		dst[i+63:i] := MEM[addr+63:addr]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPGATHERQQ" form="xmm {k}, vm64x" xed="VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSD" form="ymm {k}, ymm, ymm" xed="VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSD" form="ymm {z}, ymm, ymm" xed="VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSD" form="xmm {k}, xmm, xmm" xed="VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSD" form="xmm {z}, xmm, xmm" xed="VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSQ" form="ymm {k}, ymm, ymm" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSQ" form="ymm {z}, ymm, ymm" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_max_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSQ" form="ymm, ymm, ymm" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSQ" form="xmm {k}, xmm, xmm" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSQ" form="xmm {z}, xmm, xmm" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_max_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXSQ" form="xmm, xmm, xmm" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUD" form="ymm {k}, ymm, ymm" xed="VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUD" form="ymm {z}, ymm, ymm" xed="VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUD" form="xmm {k}, xmm, xmm" xed="VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUD" form="xmm {z}, xmm, xmm" xed="VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_max_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUQ" form="ymm {k}, ymm, ymm" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_max_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUQ" form="ymm {z}, ymm, ymm" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_max_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUQ" form="ymm, ymm, ymm" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_max_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUQ" form="xmm {k}, xmm, xmm" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_max_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUQ" form="xmm {z}, xmm, xmm" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_max_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMAXUQ" form="xmm, xmm, xmm" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSD" form="ymm {k}, ymm, ymm" xed="VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSD" form="ymm {z}, ymm, ymm" xed="VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSD" form="xmm {k}, xmm, xmm" xed="VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSD" form="xmm {z}, xmm, xmm" xed="VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSQ" form="ymm {k}, ymm, ymm" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSQ" form="ymm {z}, ymm, ymm" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_min_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINSQ" form="ymm, ymm, ymm" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSQ" form="xmm {k}, xmm, xmm" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSQ" form="xmm {z}, xmm, xmm" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_min_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="b" etype="SI64"/>
+ 	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINSQ" form="xmm, xmm, xmm" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUD" form="ymm {k}, ymm, ymm" xed="VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUD" form="ymm {z}, ymm, ymm" xed="VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUD" form="xmm {k}, xmm, xmm" xed="VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUD" form="xmm {z}, xmm, xmm" xed="VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_min_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUQ" form="ymm {k}, ymm, ymm" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_min_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUQ" form="ymm {z}, ymm, ymm" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_min_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMINUQ" form="ymm, ymm, ymm" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_min_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUQ" form="xmm {k}, xmm, xmm" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_min_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUQ" form="xmm {z}, xmm, xmm" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_min_epu64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMINUQ" form="xmm, xmm, xmm" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[k+7:k] := Truncate8(a[i+31:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="xmm, ymm" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="xmm {k}, ymm" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="m64 {k}, ymm" xed="VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="xmm {z}, ymm" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[k+7:k] := Truncate8(a[i+31:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="xmm, xmm" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="xmm {k}, xmm" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="m64 {k}, xmm" xed="VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDB" form="xmm {z}, xmm" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[k+15:k] := Truncate16(a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="xmm, ymm" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="xmm {k}, ymm" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="m128 {k}, ymm" xed="VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="xmm {z}, ymm" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[k+15:k] := Truncate16(a[i+31:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="xmm, xmm" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="xmm {k}, xmm" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="m64 {k}, xmm" xed="VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVDW" form="xmm {z}, xmm" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[k+7:k] := Truncate8(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="xmm, ymm" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="xmm {k}, ymm" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="m32 {k}, ymm" xed="VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="xmm {z}, ymm" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[k+7:k] := Truncate8(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="xmm, xmm" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="xmm {k}, xmm" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="m16 {k}, xmm" xed="VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Truncate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQB" form="xmm {z}, xmm" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[k+31:k] := Truncate32(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="xmm, ymm" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Truncate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="xmm {k}, ymm" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="m128 {k}, ymm" xed="VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Truncate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="xmm {z}, ymm" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[k+31:k] := Truncate32(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="xmm, xmm" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Truncate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="xmm {k}, xmm" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="m64 {k}, xmm" xed="VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Truncate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQD" form="xmm {z}, xmm" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[k+15:k] := Truncate16(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="xmm, ymm" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="xmm {k}, ymm" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi64_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="m64 {k}, ymm" xed="VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="xmm {z}, ymm" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[k+15:k] := Truncate16(a[i+63:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="xmm, xmm" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="xmm {k}, xmm" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi64_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="m32 {k}, xmm" xed="VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Truncate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVQW" form="xmm {z}, xmm" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtsepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[k+7:k] := Saturate8(a[i+31:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="xmm, ymm" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="xmm {k}, ymm" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi32_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="m64 {k}, ymm" xed="VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtsepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="xmm {z}, ymm" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtsepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[k+7:k] := Saturate8(a[i+31:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="xmm, xmm" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="xmm {k}, xmm" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi32_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="m32 {k}, xmm" xed="VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtsepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDB" form="xmm {z}, xmm" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtsepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[k+15:k] := Saturate16(a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="xmm, ymm" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="xmm {k}, ymm" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi32_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI16" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="m128 {k}, ymm" xed="VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtsepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="xmm {z}, ymm" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtsepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[k+15:k] := Saturate16(a[i+31:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="xmm, xmm" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="xmm {k}, xmm" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi32_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI16" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="m64 {k}, xmm" xed="VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtsepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSDW" form="xmm {z}, xmm" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtsepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[k+7:k] := Saturate8(a[i+63:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="xmm, ymm" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="xmm {k}, ymm" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi64_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="m32 {k}, ymm" xed="VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtsepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="xmm {z}, ymm" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtsepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[k+7:k] := Saturate8(a[i+63:i])
+ ENDFOR
+ dst[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="xmm, xmm" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="xmm {k}, xmm" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi64_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI8" memwidth="16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="m16 {k}, xmm" xed="VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtsepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := Saturate8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQB" form="xmm {z}, xmm" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtsepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[k+31:k] := Saturate32(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="xmm, ymm" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Saturate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="xmm {k}, ymm" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi64_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="m128 {k}, ymm" xed="VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtsepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Saturate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="xmm {z}, ymm" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtsepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[k+31:k] := Saturate32(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="xmm, xmm" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Saturate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="xmm {k}, xmm" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi64_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI32" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="m64 {k}, xmm" xed="VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtsepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := Saturate32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQD" form="xmm {z}, xmm" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtsepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[k+15:k] := Saturate16(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="xmm, ymm" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="xmm {k}, ymm" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtsepi64_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI16" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="m64 {k}, ymm" xed="VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtsepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="xmm {z}, ymm" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtsepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[k+15:k] := Saturate16(a[i+63:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="xmm, xmm" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__m128i" varname="src" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="xmm {k}, xmm" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtsepi64_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="SI16" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="m32 {k}, xmm" xed="VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtsepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := Saturate16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSQW" form="xmm {z}, xmm" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m256i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBD" form="ymm {k}, xmm" xed="VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBD" form="ymm {z}, xmm" xed="VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBD" form="xmm {k}, xmm" xed="VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBD" form="xmm {z}, xmm" xed="VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m256i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBQ" form="ymm {k}, xmm" xed="VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBQ" form="ymm {z}, xmm" xed="VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBQ" form="xmm {k}, xmm" xed="VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI8"/>
+ 	<description>Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXBQ" form="xmm {z}, xmm" xed="VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXDQ" form="ymm {k}, xmm" xed="VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXDQ" form="ymm {z}, xmm" xed="VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXDQ" form="xmm {k}, xmm" xed="VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXDQ" form="xmm {z}, xmm" xed="VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m256i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	l := j*16
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWD" form="ymm {k}, xmm" xed="VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWD" form="ymm {z}, xmm" xed="VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__m128i" varname="src" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	l := j*16
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWD" form="xmm {k}, xmm" xed="VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+31:i] := SignExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWD" form="xmm {z}, xmm" xed="VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepi16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m256i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWQ" form="ymm {k}, xmm" xed="VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepi16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWQ" form="ymm {z}, xmm" xed="VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepi16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWQ" form="xmm {k}, xmm" xed="VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepi16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI16"/>
+ 	<description>Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVSXWQ" form="xmm {z}, xmm" xed="VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtusepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[k+7:k] := SaturateU8(a[i+31:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="xmm, ymm" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="xmm {k}, ymm" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi32_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="m64 {k}, ymm" xed="VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtusepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="xmm {z}, ymm" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtusepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 8*j
+ 	dst[k+7:k] := SaturateU8(a[i+31:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="xmm, xmm" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="xmm {k}, xmm" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi32_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="m32 {k}, xmm" xed="VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtusepi32_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+31:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDB" form="xmm {z}, xmm" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtusepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[k+15:k] := SaturateU16(a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="xmm, ymm" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="xmm {k}, ymm" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi32_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="m128 {k}, ymm" xed="VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtusepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="xmm {z}, ymm" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtusepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	k := 16*j
+ 	dst[k+15:k] := SaturateU16(a[i+31:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="xmm, xmm" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="xmm {k}, xmm" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi32_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="m64 {k}, xmm" xed="VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtusepi32_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+31:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSDW" form="xmm {z}, xmm" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtusepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[k+7:k] := SaturateU8(a[i+63:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="xmm, ymm" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="xmm {k}, ymm" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi64_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="m32 {k}, ymm" xed="VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtusepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="xmm {z}, ymm" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtusepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 8*j
+ 	dst[k+7:k] := SaturateU8(a[i+63:i])
+ ENDFOR
+ dst[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="xmm, xmm" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__m128i" varname="src" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := src[l+7:l]
+ 	FI
+ ENDFOR
+ dst[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="xmm {k}, xmm" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi64_storeu_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI8" memwidth="16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="m16 {k}, xmm" xed="VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtusepi64_epi8">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI8"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[l+7:l] := SaturateU8(a[i+63:i])
+ 	ELSE
+ 		dst[l+7:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQB" form="xmm {z}, xmm" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtusepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[k+31:k] := SaturateU32(a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="xmm, ymm" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := SaturateU32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="xmm {k}, ymm" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi64_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="m128 {k}, ymm" xed="VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtusepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := SaturateU32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="xmm {z}, ymm" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtusepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 32*j
+ 	dst[k+31:k] := SaturateU32(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="xmm, xmm" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := SaturateU32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := src[l+31:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="xmm {k}, xmm" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi64_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="m64 {k}, xmm" xed="VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtusepi64_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[l+31:l] := SaturateU32(a[i+63:i])
+ 	ELSE
+ 		dst[l+31:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQD" form="xmm {z}, xmm" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_cvtusepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[k+15:k] := SaturateU16(a[i+63:i])
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="xmm, ymm" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="xmm {k}, ymm" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtusepi64_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="m64 {k}, ymm" xed="VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtusepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:64] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="xmm {z}, ymm" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_cvtusepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	k := 16*j
+ 	dst[k+15:k] := SaturateU16(a[i+63:i])
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="xmm, xmm" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__m128i" varname="src" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := src[l+15:l]
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="xmm {k}, xmm" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtusepi64_storeu_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI16" memwidth="32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="m32 {k}, xmm" xed="VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtusepi64_epi16">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI16"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[l+15:l] := SaturateU16(a[i+63:i])
+ 	ELSE
+ 		dst[l+15:l] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:32] := 0
+ 	</operation>
+ 	<instruction name="VPMOVUSQW" form="xmm {z}, xmm" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBD" form="ymm {k}, xmm" xed="VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBD" form="ymm {z}, xmm" xed="VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBD" form="xmm {k}, xmm" xed="VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu8_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in th elow 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBD" form="xmm {z}, xmm" xed="VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBQ" form="ymm {k}, xmm" xed="VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBQ" form="ymm {z}, xmm" xed="VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBQ" form="xmm {k}, xmm" xed="VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu8_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI8"/>
+ 	<description>Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 8*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXBQ" form="xmm {z}, xmm" xed="VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXDQ" form="ymm {k}, xmm" xed="VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+ 	ELSE 
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXDQ" form="ymm {z}, xmm" xed="VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXDQ" form="xmm {k}, xmm" xed="VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu32_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 32*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+ 	ELSE 
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXDQ" form="xmm {z}, xmm" xed="VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWD" form="ymm {k}, xmm" xed="VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWD" form="ymm {z}, xmm" xed="VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWD" form="xmm {k}, xmm" xed="VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu16_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 32*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWD" form="xmm {z}, xmm" xed="VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_cvtepu16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWQ" form="ymm {k}, xmm" xed="VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_cvtepu16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWQ" form="ymm {z}, xmm" xed="VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_cvtepu16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWQ" form="xmm {k}, xmm" xed="VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_cvtepu16_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Convert</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI16"/>
+ 	<description>Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := 64*j
+ 	l := 16*j
+ 	IF k[j]
+ 		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMOVZXWQ" form="xmm {z}, xmm" xed="VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mul_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m256i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULDQ" form="ymm {k}, ymm, ymm" xed="VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mul_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="b" etype="SI32"/>
+ 	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULDQ" form="ymm {z}, ymm, ymm" xed="VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mul_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__m128i" varname="src" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULDQ" form="xmm {k}, xmm, xmm" xed="VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mul_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="SI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="b" etype="SI32"/>
+ 	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULDQ" form="xmm {z}, xmm, xmm" xed="VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mullo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		tmp[63:0] := a[i+31:i] * b[i+31:i]
+ 		dst[i+31:i] := tmp[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLD" form="ymm {k}, ymm, ymm" xed="VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mullo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		tmp[63:0] := a[i+31:i] * b[i+31:i]
+ 		dst[i+31:i] := tmp[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULLD" form="ymm {z}, ymm, ymm" xed="VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_maskz_mullo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<parameter type="__m512i" varname="b" etype="UI32"/>
+ 	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 15
+ 	i := j*32
+ 	IF k[j]
+ 		tmp[63:0] := a[i+31:i] * b[i+31:i]
+ 		dst[i+31:i] := tmp[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VPMULLD" form="zmm {z}, zmm, zmm" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mullo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		tmp[63:0] := a[i+31:i] * b[i+31:i]
+ 		dst[i+31:i] := tmp[31:0]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLD" form="xmm {k}, xmm, xmm" xed="VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mullo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		tmp[63:0] := a[i+31:i] * b[i+31:i]
+ 		dst[i+31:i] := tmp[31:0]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULLD" form="xmm {z}, xmm, xmm" xed="VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_mul_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULUDQ" form="ymm {k}, ymm, ymm" xed="VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_mul_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPMULUDQ" form="ymm {z}, ymm, ymm" xed="VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_mul_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULUDQ" form="xmm {k}, xmm, xmm" xed="VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_mul_epu32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPMULUDQ" form="xmm {z}, xmm, xmm" xed="VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_or_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPORD" form="ymm {k}, ymm, ymm" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_or_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPORD" form="ymm {z}, ymm, ymm" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_or_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPORD" form="xmm {k}, xmm, xmm" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_or_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPORD" form="xmm {z}, xmm, xmm" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_or_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPORQ" form="ymm {k}, ymm, ymm" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_or_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPORQ" form="ymm {z}, ymm, ymm" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_or_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPORQ" form="xmm {k}, xmm, xmm" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_or_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPORQ" form="xmm {z}, xmm, xmm" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rol_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLD" form="ymm {k}, ymm, imm8" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rol_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLD" form="ymm {z}, ymm, imm8" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rol_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLD" form="ymm, ymm, imm8" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rol_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLD" form="xmm {k}, xmm, imm8" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rol_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLD" form="xmm {z}, xmm, imm8" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rol_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLD" form="xmm, xmm, imm8" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rol_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLQ" form="ymm {k}, ymm, imm8" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rol_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLQ" form="ymm {z}, ymm, imm8" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rol_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLQ" form="ymm, ymm, imm8" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rol_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLQ" form="xmm {k}, xmm, imm8" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rol_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLQ" form="xmm {z}, xmm, imm8" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rol_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLQ" form="xmm, xmm, imm8" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rolv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLVD" form="ymm {k}, ymm, ymm" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rolv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLVD" form="ymm {z}, ymm, ymm" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rolv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLVD" form="ymm, ymm, ymm" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rolv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLVD" form="xmm {k}, xmm, xmm" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rolv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLVD" form="xmm {z}, xmm, xmm" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rolv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLVD" form="xmm, xmm, xmm" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rolv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLVQ" form="ymm {k}, ymm, ymm" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rolv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLVQ" form="ymm {z}, ymm, ymm" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rolv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPROLVQ" form="ymm, ymm, ymm" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rolv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLVQ" form="xmm {k}, xmm, xmm" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rolv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLVQ" form="xmm {z}, xmm, xmm" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rolv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPROLVQ" form="xmm, xmm, xmm" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_ror_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORD" form="ymm {k}, ymm, imm8" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_ror_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORD" form="ymm {z}, ymm, imm8" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_ror_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORD" form="ymm, ymm, imm8" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_ror_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORD" form="xmm {k}, xmm, imm8" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_ror_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORD" form="xmm {z}, xmm, imm8" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_ror_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORD" form="xmm, xmm, imm8" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_ror_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORQ" form="ymm {k}, ymm, imm8" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_ror_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORQ" form="ymm {z}, ymm, imm8" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_ror_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORQ" form="ymm, ymm, imm8" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_ror_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORQ" form="xmm {k}, xmm, imm8" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_ror_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORQ" form="xmm {z}, xmm, imm8" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_ror_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORQ" form="xmm, xmm, imm8" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rorv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORVD" form="ymm {k}, ymm, ymm" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rorv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORVD" form="ymm {z}, ymm, ymm" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rorv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORVD" form="ymm, ymm, ymm" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rorv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORVD" form="xmm {k}, xmm, xmm" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rorv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORVD" form="xmm {z}, xmm, xmm" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rorv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+ 	count := count_src % 32
+ 	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORVD" form="xmm, xmm, xmm" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rorv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORVQ" form="ymm {k}, ymm, ymm" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rorv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORVQ" form="ymm {z}, ymm, ymm" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rorv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPRORVQ" form="ymm, ymm, ymm" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rorv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORVQ" form="xmm {k}, xmm, xmm" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rorv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORVQ" form="xmm {z}, xmm, xmm" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rorv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+ 	<operation>
+ DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+ 	count := count_src % 64
+ 	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPRORVQ" form="xmm, xmm, xmm" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i32scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDD" form="vm32y, ymm" xed="VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i32scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDD" form="vm32y {k}, ymm" xed="VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i32scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDD" form="vm32x, xmm" xed="VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i32scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDD" form="vm32x {k}, xmm" xed="VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i32scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDQ" form="vm32x, ymm" xed="VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i32scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDQ" form="vm32x {k}, ymm" xed="VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i32scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDQ" form="vm32x, xmm" xed="VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i32scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERDQ" form="vm32x {k}, xmm" xed="VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i64scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQD" form="vm64y, xmm" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i64scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQD" form="vm64y {k}, xmm" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i64scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQD" form="vm64x, xmm" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i64scatter_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQD" form="vm64x {k}, xmm" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i64scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQQ" form="vm64y, ymm" xed="VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i64scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQQ" form="vm64y {k}, ymm" xed="VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i64scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQQ" form="vm64x, xmm" xed="VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i64scatter_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VPSCATTERQQ" form="vm64x {k}, xmm" xed="VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="_MM_PERM_ENUM" varname="imm8" etype="IMM" immtype="_MM_PERM"/>
+ 	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+ tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFD" form="ymm {k}, ymm, imm8" xed="VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="_MM_PERM_ENUM" varname="imm8" etype="IMM" immtype="_MM_PERM"/>
+ 	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+ tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFD" form="ymm {z}, ymm, imm8" xed="VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_shuffle_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="_MM_PERM_ENUM" varname="imm8" etype="IMM" immtype="_MM_PERM"/>
+ 	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFD" form="xmm {k}, xmm, imm8" xed="VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_shuffle_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="_MM_PERM_ENUM" varname="imm8" etype="IMM" immtype="_MM_PERM"/>
+ 	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSHUFD" form="xmm {z}, xmm, imm8" xed="VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sll_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="ymm {k}, ymm, xmm" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_slli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="ymm {k}, ymm, imm8" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sll_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="ymm {z}, ymm, xmm" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_slli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="ymm {z}, ymm, imm8" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sll_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="xmm {k}, xmm, xmm" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_slli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="xmm {k}, xmm, imm8" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sll_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="xmm {z}, xmm, xmm" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_slli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLD" form="xmm {z}, xmm, imm8" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sll_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="ymm {k}, ymm, xmm" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_slli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="ymm {k}, ymm, imm8" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sll_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="ymm {z}, ymm, xmm" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_slli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="ymm {z}, ymm, imm8" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sll_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="xmm {k}, xmm, xmm" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_slli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="xmm {k}, xmm, imm8" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sll_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="xmm {z}, xmm, xmm" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_slli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLQ" form="xmm {z}, xmm, imm8" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sllv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVD" form="ymm {k}, ymm, ymm" xed="VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sllv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVD" form="ymm {z}, ymm, ymm" xed="VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sllv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVD" form="xmm {k}, xmm, xmm" xed="VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sllv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVD" form="xmm {z}, xmm, xmm" xed="VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sllv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVQ" form="ymm {k}, ymm, ymm" xed="VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sllv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVQ" form="ymm {z}, ymm, ymm" xed="VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sllv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVQ" form="xmm {k}, xmm, xmm" xed="VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sllv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSLLVQ" form="xmm {z}, xmm, xmm" xed="VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sra_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="ymm {k}, ymm, xmm" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srai_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="ymm {k}, ymm, imm8" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sra_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="ymm {z}, ymm, xmm" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srai_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="ymm {z}, ymm, imm8" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sra_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="xmm {k}, xmm, xmm" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srai_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="xmm {k}, xmm, imm8" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sra_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="xmm {z}, xmm, xmm" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srai_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="6"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAD" form="xmm {z}, xmm, imm8" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sra_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="ymm {k}, ymm, xmm" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srai_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="ymm {k}, ymm, imm8" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sra_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="ymm {z}, ymm, xmm" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srai_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="ymm {z}, ymm, imm8" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_sra_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF count[63:0] &gt; 63
+ 		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 	ELSE
+ 		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="ymm, ymm, xmm" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_srai_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF imm8[7:0] &gt; 63
+ 		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 	ELSE
+ 		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="ymm, ymm, imm8" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sra_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="xmm {k}, xmm, xmm" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srai_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="xmm {k}, xmm, imm8" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sra_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="xmm {z}, xmm, xmm" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srai_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="7"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 		ELSE
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="xmm {z}, xmm, imm8" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_sra_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF count[63:0] &gt; 63
+ 		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 	ELSE
+ 		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="xmm, xmm, xmm" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_srai_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="7"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF imm8[7:0] &gt; 63
+ 		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+ 	ELSE
+ 		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAQ" form="xmm, xmm, imm8" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srav_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVD" form="ymm {k}, ymm, ymm" xed="VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srav_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVD" form="ymm {z}, ymm, ymm" xed="VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srav_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVD" form="xmm {k}, xmm, xmm" xed="VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srav_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVD" form="xmm {z}, xmm, xmm" xed="VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srav_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVQ" form="ymm {k}, ymm, ymm" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srav_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVQ" form="ymm {z}, ymm, ymm" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_srav_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="SI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF count[i+63:i] &lt; 64
+ 		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVQ" form="ymm, ymm, ymm" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srav_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVQ" form="xmm {k}, xmm, xmm" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srav_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVQ" form="xmm {z}, xmm, xmm" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_srav_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="SI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF count[i+63:i] &lt; 64
+ 		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRAVQ" form="xmm, xmm, xmm" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srl_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="ymm {k}, ymm, xmm" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="ymm {k}, ymm, imm8" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srl_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="ymm {z}, ymm, xmm" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="ymm {z}, ymm, imm8" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srl_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="xmm {k}, xmm, xmm" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="xmm {k}, xmm, imm8" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srl_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[63:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="xmm {z}, xmm, xmm" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srli_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 31
+ 			dst[i+31:i] := 0
+ 		ELSE
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLD" form="xmm {z}, xmm, imm8" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srl_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="ymm {k}, ymm, xmm" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="ymm {k}, ymm, imm8" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srl_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="ymm {z}, ymm, xmm" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="ymm {z}, ymm, imm8" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srl_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="xmm {k}, xmm, xmm" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="xmm {k}, xmm, imm8" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srl_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[63:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="xmm {z}, xmm, xmm" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srli_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="unsigned int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF imm8[7:0] &gt; 63
+ 			dst[i+63:i] := 0
+ 		ELSE
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLQ" form="xmm {z}, xmm, imm8" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srlv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVD" form="ymm {k}, ymm, ymm" xed="VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srlv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVD" form="ymm {z}, ymm, ymm" xed="VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srlv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVD" form="xmm {k}, xmm, xmm" xed="VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srlv_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="count" etype="UI32"/>
+ 	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		IF count[i+31:i] &lt; 32
+ 			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+ 		ELSE
+ 			dst[i+31:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVD" form="xmm {z}, xmm, xmm" xed="VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_srlv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVQ" form="ymm {k}, ymm, ymm" xed="VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_srlv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVQ" form="ymm {z}, ymm, ymm" xed="VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_srlv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVQ" form="xmm {k}, xmm, xmm" xed="VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_srlv_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Shift</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="count" etype="UI64"/>
+ 	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		IF count[i+63:i] &lt; 64
+ 			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+ 		ELSE
+ 			dst[i+63:i] := 0
+ 		FI
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSRLVQ" form="xmm {z}, xmm, xmm" xed="VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sub_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBD" form="ymm {k}, ymm, ymm" xed="VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sub_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBD" form="ymm {z}, ymm, ymm" xed="VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sub_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBD" form="xmm {k}, xmm, xmm" xed="VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sub_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBD" form="xmm {z}, xmm, xmm" xed="VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sub_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBQ" form="ymm {k}, ymm, ymm" xed="VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sub_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPSUBQ" form="ymm {z}, ymm, ymm" xed="VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sub_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBQ" form="xmm {k}, xmm, xmm" xed="VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sub_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPSUBQ" form="xmm {z}, xmm, xmm" xed="VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_ternarylogic_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		FOR h := 0 to 31
+ 			index[2:0] := (src[i+h] &lt;&lt; 2) OR (a[i+h] &lt;&lt; 1) OR b[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGD" form="ymm {k}, ymm, ymm, imm8" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_ternarylogic_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="__m256i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		FOR h := 0 to 31
+ 			index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGD" form="ymm {z}, ymm, ymm, imm8" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_ternarylogic_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="__m256i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	FOR h := 0 to 31
+ 		index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 		dst[i+h] := imm8[index[2:0]]
+ 	ENDFOR
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGD" form="ymm, ymm, ymm, imm8" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_ternarylogic_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		FOR h := 0 to 31
+ 			index[2:0] := (src[i+h] &lt;&lt; 2) OR (a[i+h] &lt;&lt; 1) OR b[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGD" form="xmm {k}, xmm, xmm, imm8" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_ternarylogic_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="__m128i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		FOR h := 0 to 31
+ 			index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGD" form="xmm {z}, xmm, xmm, imm8" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_ternarylogic_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<parameter type="__m128i" varname="c" etype="UI32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	FOR h := 0 to 31
+ 		index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 		dst[i+h] := imm8[index[2:0]]
+ 	ENDFOR
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGD" form="xmm, xmm, xmm, imm8" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_ternarylogic_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		FOR h := 0 to 63
+ 			index[2:0] := (src[i+h] &lt;&lt; 2) OR (a[i+h] &lt;&lt; 1) OR b[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGQ" form="ymm {k}, ymm, ymm, imm8" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_ternarylogic_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="__m256i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		FOR h := 0 to 63
+ 			index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGQ" form="ymm {z}, ymm, ymm, imm8" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_ternarylogic_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="__m256i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	FOR h := 0 to 63
+ 		index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 		dst[i+h] := imm8[index[2:0]]
+ 	ENDFOR
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGQ" form="ymm, ymm, ymm, imm8" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_ternarylogic_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		FOR h := 0 to 63
+ 			index[2:0] := (src[i+h] &lt;&lt; 2) OR (a[i+h] &lt;&lt; 1) OR b[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGQ" form="xmm {k}, xmm, xmm, imm8" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_ternarylogic_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="__m128i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		FOR h := 0 to 63
+ 			index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 			dst[i+h] := imm8[index[2:0]]
+ 		ENDFOR
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGQ" form="xmm {z}, xmm, xmm, imm8" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_ternarylogic_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<parameter type="__m128i" varname="c" etype="UI64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	FOR h := 0 to 63
+ 		index[2:0] := (a[i+h] &lt;&lt; 2) OR (b[i+h] &lt;&lt; 1) OR c[i+h]
+ 		dst[i+h] := imm8[index[2:0]]
+ 	ENDFOR
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPTERNLOGQ" form="xmm, xmm, xmm, imm8" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_test_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMD" form="k {k}, ymm, ymm" xed="VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_test_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMD" form="k, ymm, ymm" xed="VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_test_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMD" form="k {k}, xmm, xmm" xed="VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_test_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMD" form="k, xmm, xmm" xed="VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_test_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMQ" form="k {k}, ymm, ymm" xed="VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_test_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMQ" form="k, ymm, ymm" xed="VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_test_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMQ" form="k {k}, xmm, xmm" xed="VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_test_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPTESTMQ" form="k, xmm, xmm" xed="VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_testn_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMD" form="k {k}, ymm, ymm" xed="VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_testn_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:8] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMD" form="k, ymm, ymm" xed="VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_testn_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k1[j]
+ 		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMD" form="k {k}, xmm, xmm" xed="VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_testn_epi32_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMD" form="k, xmm, xmm" xed="VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_testn_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMQ" form="k {k}, ymm, ymm" xed="VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_testn_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:4] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMQ" form="k, ymm, ymm" xed="VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_testn_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask8" varname="k1" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k1[j]
+ 		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ 	ELSE
+ 		k[j] := 0
+ 	FI
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMQ" form="k {k}, xmm, xmm" xed="VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_testn_epi64_mask">
+ 	<type>Integer</type>
+ 	<type>Mask</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Compare</category>
+ 	<return type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ ENDFOR
+ k[MAX:2] := 0
+ 	</operation>
+ 	<instruction name="VPTESTNMQ" form="k, xmm, xmm" xed="VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpackhi_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHDQ" form="ymm {k}, ymm, ymm" xed="VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpackhi_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHDQ" form="ymm {z}, ymm, ymm" xed="VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpackhi_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHDQ" form="xmm {k}, xmm, xmm" xed="VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpackhi_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHDQ" form="xmm {z}, xmm, xmm" xed="VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpackhi_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHQDQ" form="ymm {k}, ymm, ymm" xed="VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpackhi_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHQDQ" form="ymm {z}, ymm, ymm" xed="VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpackhi_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHQDQ" form="xmm {k}, xmm, xmm" xed="VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpackhi_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKHQDQ" form="xmm {z}, xmm, xmm" xed="VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpacklo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLDQ" form="ymm {k}, ymm, ymm" xed="VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpacklo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLDQ" form="ymm {z}, ymm, ymm" xed="VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpacklo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLDQ" form="xmm {k}, xmm, xmm" xed="VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpacklo_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLDQ" form="xmm {z}, xmm, xmm" xed="VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpacklo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLQDQ" form="ymm {k}, ymm, ymm" xed="VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpacklo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLQDQ" form="ymm {z}, ymm, ymm" xed="VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpacklo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLQDQ" form="xmm {k}, xmm, xmm" xed="VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpacklo_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPUNPCKLQDQ" form="xmm {z}, xmm, xmm" xed="VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_xor_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXORD" form="ymm {k}, ymm, ymm" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_xor_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXORD" form="ymm {z}, ymm, ymm" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_xor_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPXORD" form="xmm {k}, xmm, xmm" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_xor_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPXORD" form="xmm {z}, xmm, xmm" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_xor_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXORQ" form="ymm {k}, ymm, ymm" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_xor_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXORQ" form="ymm {z}, ymm, ymm" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_xor_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPXORQ" form="xmm {k}, xmm, xmm" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_xor_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPXORQ" form="xmm {z}, xmm, xmm" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rcp14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PD" form="ymm {k}, ymm" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rcp14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PD" form="ymm {z}, ymm" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rcp14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := (1.0 / a[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PD" form="ymm, ymm" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rcp14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PD" form="xmm {k}, xmm" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rcp14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PD" form="xmm {z}, xmm" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rcp14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := (1.0 / a[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PD" form="xmm, xmm" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rcp14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PS" form="ymm {k}, ymm" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rcp14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PS" form="ymm {z}, ymm" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_rcp14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / a[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PS" form="ymm, ymm" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rcp14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PS" form="xmm {k}, xmm" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rcp14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PS" form="xmm {z}, xmm" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_rcp14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := (1.0 / a[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRCP14PS" form="xmm, xmm" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_roundscale_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := src1[63:0]
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPD" form="ymm {k}, ymm, imm8" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_roundscale_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := src1[63:0]
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPD" form="ymm {z}, ymm, imm8" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_roundscale_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := src1[63:0]
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPD" form="ymm, ymm, imm8" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_roundscale_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := src1[63:0]
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPD" form="xmm {k}, xmm, imm8" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_roundscale_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := src1[63:0]
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPD" form="xmm {z}, xmm, imm8" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_roundscale_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+ 	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+ 	IF IsInf(tmp[63:0])
+ 		tmp[63:0] := src1[63:0]
+ 	FI
+ 	RETURN tmp[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPD" form="xmm, xmm, imm8" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_roundscale_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := src1[31:0]
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPS" form="ymm {k}, ymm, imm8" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_roundscale_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := src1[31:0]
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPS" form="ymm {z}, ymm, imm8" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_roundscale_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := src1[31:0]
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPS" form="ymm, ymm, imm8" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_roundscale_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := src1[31:0]
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPS" form="xmm {k}, xmm, imm8" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_roundscale_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := src1[31:0]
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPS" form="xmm {z}, xmm, imm8" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_roundscale_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="int" varname="imm8" etype="IMM" immtype="_MM_REDUCE"/>
+ 	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+ 	<operation>
+ DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+ 	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+ 	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+ 	IF IsInf(tmp[31:0])
+ 		tmp[31:0] := src1[31:0]
+ 	FI
+ 	RETURN tmp[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRNDSCALEPS" form="xmm, xmm, imm8" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rsqrt14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PD" form="ymm {k}, ymm" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rsqrt14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PD" form="ymm {z}, ymm" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rsqrt14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PD" form="xmm {k}, xmm" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rsqrt14_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PD" form="xmm {z}, xmm" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_rsqrt14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PS" form="ymm {k}, ymm" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_rsqrt14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PS" form="ymm {z}, ymm" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_rsqrt14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PS" form="xmm {k}, xmm" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_rsqrt14_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VRSQRT14PS" form="xmm {z}, xmm" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_scalef_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+ 	RETURN dst[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPD" form="ymm {k}, ymm, ymm" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_scalef_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+ 	RETURN dst[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPD" form="ymm {z}, ymm, ymm" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_scalef_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+ 	RETURN dst[63:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPD" form="ymm, ymm, ymm" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_scalef_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+ 	RETURN dst[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPD" form="xmm {k}, xmm, xmm" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_scalef_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+ 	RETURN dst[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPD" form="xmm {z}, xmm, xmm" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_scalef_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+ 	RETURN dst[63:0]
+ }
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPD" form="xmm, xmm, xmm" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_scalef_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+ 	RETURN dst[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPS" form="ymm {k}, ymm, ymm" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_scalef_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+ 	RETURN dst[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPS" form="ymm {z}, ymm, ymm" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_scalef_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+ 	RETURN dst[31:0]
+ }
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPS" form="ymm, ymm, ymm" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_scalef_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+ 	RETURN dst[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPS" form="xmm {k}, xmm, xmm" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_scalef_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+ 	RETURN dst[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPS" form="xmm {z}, xmm, xmm" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_scalef_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+ 	<operation>DEFINE SCALE(src1, src2) {
+ 	IF (src2 == NaN)
+ 		IF (src2 == SNaN)
+ 			RETURN QNAN(src2)
+ 		FI
+ 	ELSE IF (src1 == NaN)
+ 		IF (src1 == SNaN)
+ 			RETURN QNAN(src1)
+ 		FI
+ 		IF (src2 != INF)
+ 			RETURN QNAN(src1)
+ 		FI
+ 	ELSE
+ 		tmp_src2 := src2
+ 		tmp_src1 := src1
+ 		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+ 			tmp_src2 := 0
+ 		FI
+ 		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+ 			tmp_src1 := 0
+ 		FI
+ 	FI
+ 	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+ 	RETURN dst[31:0]
+ }
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSCALEFPS" form="xmm, xmm, xmm" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i32scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPD" form="vm32x, ymm" xed="VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i32scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPD" form="vm32x {k}, ymm" xed="VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i32scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPD" form="vm32x, xmm" xed="VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i32scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPD" form="vm32x {k}, xmm" xed="VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i32scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPS" form="vm32y, ymm" xed="VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i32scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPS" form="vm32y {k}, ymm" xed="VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i32scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPS" form="vm32x, xmm" xed="VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i32scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI32"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*32
+ 	IF k[j]
+ 		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERDPS" form="vm32x {k}, xmm" xed="VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i64scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPD" form="vm64y, ymm" xed="VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i64scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPD" form="vm64y {k}, ymm" xed="VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i64scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+63:addr] := a[i+63:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPD" form="vm64x, xmm" xed="VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i64scatter_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+63:addr] := a[i+63:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPD" form="vm64x {k}, xmm" xed="VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_i64scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPS" form="vm64y, xmm" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_i64scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPS" form="vm64y {k}, xmm" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_i64scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 	MEM[addr+31:addr] := a[i+31:i]
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPS" form="vm64x, xmm" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_i64scatter_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="base_addr" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128i" varname="vindex" etype="SI64"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="const int" varname="scale" etype="IMM" immtype="_MM_INDEX_SCALE"/>
+ 	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*32
+ 	m := j*64
+ 	IF k[j]
+ 		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+ 		MEM[addr+31:addr] := a[i+31:i]
+ 	FI
+ ENDFOR
+ 	</operation>
+ 	<instruction name="VSCATTERQPS" form="vm64x {k}, xmm" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_f32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFF32X4" form="ymm {k}, ymm, ymm, imm8" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_f32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFF32X4" form="ymm {z}, ymm, ymm, imm8" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_shuffle_f32x4">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ dst.m128[0] := a.m128[imm8[0]]
+ dst.m128[1] := b.m128[imm8[1]]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFF32X4" form="ymm, ymm, ymm, imm8" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFF64X2" form="ymm {k}, ymm, ymm, imm8" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFF64X2" form="ymm {z}, ymm, ymm, imm8" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_shuffle_f64x2">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ dst.m128[0] := a.m128[imm8[0]]
+ dst.m128[1] := b.m128[imm8[1]]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFF64X2" form="ymm, ymm, ymm, imm8" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_i32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="src" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFI32X4" form="ymm {k}, ymm, ymm, imm8" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_i32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFI32X4" form="ymm {z}, ymm, ymm, imm8" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_shuffle_i32x4">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ dst.m128[0] := a.m128[imm8[0]]
+ dst.m128[1] := b.m128[imm8[1]]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFI32X4" form="ymm, ymm, ymm, imm8" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_i64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="src" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFI64X2" form="ymm {k}, ymm, ymm, imm8" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_i64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst.m128[0] := a.m128[imm8[0]]
+ tmp_dst.m128[1] := b.m128[imm8[1]]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFI64X2" form="ymm {z}, ymm, ymm, imm8" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_shuffle_i64x2">
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ dst.m128[0] := a.m128[imm8[0]]
+ dst.m128[1] := b.m128[imm8[1]]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFI64X2" form="ymm, ymm, ymm, imm8" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+ tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+ tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+ tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPD" form="ymm {k}, ymm, ymm, imm8" xed="VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="4"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+ tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+ tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+ tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPD" form="ymm {z}, ymm, ymm, imm8" xed="VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_shuffle_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+ tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPD" form="xmm {k}, xmm, xmm, imm8" xed="VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_shuffle_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="2"/>
+ 	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+ tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPD" form="xmm {z}, xmm, xmm, imm8" xed="VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_shuffle_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+ tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+ tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPS" form="ymm {k}, ymm, ymm, imm8" xed="VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_shuffle_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+ tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+ tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+ tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+ tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPS" form="ymm {z}, ymm, ymm, imm8" xed="VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_shuffle_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPS" form="xmm {k}, xmm, xmm, imm8" xed="VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_shuffle_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<parameter type="const int" varname="imm8" etype="IMM" immwidth="8"/>
+ 	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE SELECT4(src, control) {
+ 	CASE(control[1:0]) OF
+ 	0:	tmp[31:0] := src[31:0]
+ 	1:	tmp[31:0] := src[63:32]
+ 	2:	tmp[31:0] := src[95:64]
+ 	3:	tmp[31:0] := src[127:96]
+ 	ESAC
+ 	RETURN tmp[31:0]
+ }
+ tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+ tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+ tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+ tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSHUFPS" form="xmm {z}, xmm, xmm, imm8" xed="VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SQRT(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPD" form="ymm {k}, ymm" xed="VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SQRT(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPD" form="ymm {z}, ymm" xed="VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SQRT(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPD" form="xmm {k}, xmm" xed="VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sqrt_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := SQRT(a[i+63:i])
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPD" form="xmm {z}, xmm" xed="VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SQRT(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPS" form="ymm {k}, ymm" xed="VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SQRT(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPS" form="ymm {z}, ymm" xed="VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SQRT(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPS" form="xmm {k}, xmm" xed="VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sqrt_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Elementary Math Functions</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := SQRT(a[i+31:i])
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSQRTPS" form="xmm {z}, xmm" xed="VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSUBPD" form="ymm {k}, ymm, ymm" xed="VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSUBPD" form="ymm {z}, ymm, ymm" xed="VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSUBPD" form="xmm {k}, xmm, xmm" xed="VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sub_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSUBPD" form="xmm {z}, xmm, xmm" xed="VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_sub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSUBPS" form="ymm {k}, ymm, ymm" xed="VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_sub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VSUBPS" form="ymm {z}, ymm, ymm" xed="VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_sub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSUBPS" form="xmm {k}, xmm, xmm" xed="VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_sub_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Arithmetic</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI	
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VSUBPS" form="xmm {z}, xmm, xmm" xed="VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpackhi_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPD" form="ymm {k}, ymm, ymm" xed="VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpackhi_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPD" form="ymm {z}, ymm, ymm" xed="VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpackhi_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPD" form="xmm {k}, xmm, xmm" xed="VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpackhi_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[127:64] 
+ 	dst[127:64] := src2[127:64] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPD" form="xmm {z}, xmm, xmm" xed="VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpackhi_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPS" form="ymm {k}, ymm, ymm" xed="VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpackhi_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPS" form="ymm {z}, ymm, ymm" xed="VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpackhi_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPS" form="xmm {k}, xmm, xmm" xed="VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpackhi_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[95:64] 
+ 	dst[63:32] := src2[95:64] 
+ 	dst[95:64] := src1[127:96] 
+ 	dst[127:96] := src2[127:96] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKHPS" form="xmm {z}, xmm, xmm" xed="VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpacklo_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m256d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPD" form="ymm {k}, ymm, ymm" xed="VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpacklo_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256d" varname="a" etype="FP64"/>
+ 	<parameter type="__m256d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 3
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPD" form="ymm {z}, ymm, ymm" xed="VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpacklo_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__m128d" varname="src" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := src[i+63:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPD" form="xmm {k}, xmm, xmm" xed="VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpacklo_pd">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128d" varname="dst" etype="FP64"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128d" varname="a" etype="FP64"/>
+ 	<parameter type="__m128d" varname="b" etype="FP64"/>
+ 	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+ 	dst[63:0] := src1[63:0] 
+ 	dst[127:64] := src2[63:0] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 1
+ 	i := j*64
+ 	IF k[j]
+ 		dst[i+63:i] := tmp_dst[i+63:i]
+ 	ELSE
+ 		dst[i+63:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPD" form="xmm {z}, xmm, xmm" xed="VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_mask_unpacklo_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__m256" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPS" form="ymm {k}, ymm, ymm" xed="VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_maskz_unpacklo_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m256" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m256" varname="a" etype="FP32"/>
+ 	<parameter type="__m256" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+ FOR j := 0 to 7
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPS" form="ymm {z}, ymm, ymm" xed="VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_mask_unpacklo_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__m128" varname="src" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := src[i+31:i]
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPS" form="xmm {k}, xmm, xmm" xed="VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_maskz_unpacklo_ps">
+ 	<type>Floating Point</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Miscellaneous</category>
+ 	<return type="__m128" varname="dst" etype="FP32"/>
+ 	<parameter type="__mmask8" varname="k" etype="MASK"/>
+ 	<parameter type="__m128" varname="a" etype="FP32"/>
+ 	<parameter type="__m128" varname="b" etype="FP32"/>
+ 	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+ 	<operation>
+ DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+ 	dst[31:0] := src1[31:0] 
+ 	dst[63:32] := src2[31:0] 
+ 	dst[95:64] := src1[63:32] 
+ 	dst[127:96] := src2[63:32] 
+ 	RETURN dst[127:0]
+ }
+ tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+ FOR j := 0 to 3
+ 	i := j*32
+ 	IF k[j]
+ 		dst[i+31:i] := tmp_dst[i+31:i]
+ 	ELSE
+ 		dst[i+31:i] := 0
+ 	FI
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VUNPCKLPS" form="xmm {z}, xmm, xmm" xed="VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_storeu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="512"/>
+ 	<parameter type="__m512i" varname="a" etype="UI64"/>
+ 	<description>Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+511:mem_addr] := a[511:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="m512, zmm" xed="VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="512"/>
+ 	<parameter type="__m512i" varname="a" etype="UI32"/>
+ 	<description>Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+511:mem_addr] := a[511:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="m512, zmm" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_storeu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="m256, ymm" xed="VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="m256, ymm" xed="VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_storeu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+127:mem_addr] := a[127:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="m128, xmm" xed="VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_storeu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory.
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ MEM[mem_addr+127:mem_addr] := a[127:0]
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="m128, xmm" xed="VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_store_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<description>Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory.
+ 		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="m256, ymm" xed="VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_store_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<description>Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory.
+ 		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+255:mem_addr] := a[255:0]
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="m256, ymm" xed="VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_store_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<description>Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory.
+ 		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+127:mem_addr] := a[127:0]
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="m128, xmm" xed="VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_store_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Store</category>
+ 	<return type="void"/>
+ 	<parameter type="void*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<description>Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory.
+ 		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ MEM[mem_addr+127:mem_addr] := a[127:0]
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="m128, xmm" xed="VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI64"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="512"/>
+ 	<description>Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[511:0] := MEM[mem_addr+511:mem_addr]
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="zmm, m512" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm512_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m512i" varname="dst" etype="UI32"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="512"/>
+ 	<description>Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[511:0] := MEM[mem_addr+511:mem_addr]
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="zmm, m512" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="ymm, m256" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="ymm, m256" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_loadu_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU64" form="xmm, m128" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_loadu_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst".
+ 		"mem_addr" does not need to be aligned on any particular boundary.</description>
+ 	<operation>
+ dst[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQU32" form="xmm, m128" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_load_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst".
+ 		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="ymm, m256" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_load_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="256"/>
+ 	<description>Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst".
+ 		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[255:0] := MEM[mem_addr+255:mem_addr]
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="ymm, m256" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_load_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI64" memwidth="128"/>
+ 	<description>Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst".
+ 		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA64" form="xmm, m128" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_load_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Load</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="void const*" varname="mem_addr" etype="UI32" memwidth="128"/>
+ 	<description>Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst".
+ 		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+ 	<operation>
+ dst[127:0] := MEM[mem_addr+127:mem_addr]
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VMOVDQA32" form="xmm, m128" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_xor_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXORQ" form="ymm, ymm" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_xor_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPXORD" form="ymm, ymm" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_xor_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPXORQ" form="xmm, xmm" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_xor_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPXORD" form="xmm, xmm" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_or_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m256i" varname="a" etype="UI64"/>
+ 	<parameter type="__m256i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPORQ" form="ymm, ymm" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm256_or_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m256i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m256i" varname="a" etype="UI32"/>
+ 	<parameter type="__m256i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 7
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ ENDFOR
+ dst[MAX:256] := 0
+ 	</operation>
+ 	<instruction name="VPORD" form="ymm, ymm" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_or_epi64">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI64"/>
+ 	<parameter type="__m128i" varname="a" etype="UI64"/>
+ 	<parameter type="__m128i" varname="b" etype="UI64"/>
+ 	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 1
+ 	i := j*64
+ 	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPORQ" form="xmm, xmm" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_mm_or_epi32">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512VL</CPUID>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Logical</category>
+ 	<return type="__m128i" varname="dst" etype="UI32"/>
+ 	<parameter type="__m128i" varname="a" etype="UI32"/>
+ 	<parameter type="__m128i" varname="b" etype="UI32"/>
+ 	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+ 	<operation>
+ FOR j := 0 to 3
+ 	i := j*32
+ 	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ ENDFOR
+ dst[MAX:128] := 0
+ 	</operation>
+ 	<instruction name="VPORD" form="xmm, xmm" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" name="_mm512_aesenclast_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>VAES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m512i" varname="dst" etype="M128"/>
+ 	<parameter type="__m512i" varname="a" etype="M128"/>
+ 	<parameter type="__m512i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*128
+ 	a[i+127:i] := ShiftRows(a[i+127:i])
+ 	a[i+127:i] := SubBytes(a[i+127:i])
+ 	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VAESENCLAST" form="zmm, zmm" xed="VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" name="_mm512_aesenc_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>VAES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m512i" varname="dst" etype="M128"/>
+ 	<parameter type="__m512i" varname="a" etype="M128"/>
+ 	<parameter type="__m512i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*128
+ 	a[i+127:i] := ShiftRows(a[i+127:i])
+ 	a[i+127:i] := SubBytes(a[i+127:i])
+ 	a[i+127:i] := MixColumns(a[i+127:i])
+ 	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VAESENC" form="zmm, zmm" xed="VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" name="_mm512_aesdeclast_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>VAES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m512i" varname="dst" etype="M128"/>
+ 	<parameter type="__m512i" varname="a" etype="M128"/>
+ 	<parameter type="__m512i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*128
+ 	a[i+127:i] := InvShiftRows(a[i+127:i])
+ 	a[i+127:i] := InvSubBytes(a[i+127:i])
+ 	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VAESDECLAST" form="zmm, zmm" xed="VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="Other" name="_mm512_aesdec_epi128">
+ 	<type>Integer</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<CPUID>VAES</CPUID>
+ 	<category>Cryptography</category>
+ 	<return type="__m512i" varname="dst" etype="M128"/>
+ 	<parameter type="__m512i" varname="a" etype="M128"/>
+ 	<parameter type="__m512i" varname="RoundKey" etype="M128"/>
+ 	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
+ 	<operation>FOR j := 0 to 3
+ 	i := j*128
+ 	a[i+127:i] := InvShiftRows(a[i+127:i])
+ 	a[i+127:i] := InvSubBytes(a[i+127:i])
+ 	a[i+127:i] := InvMixColumns(a[i+127:i])
+ 	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ ENDFOR
+ dst[MAX:512] := 0
+ 	</operation>
+ 	<instruction name="VAESDEC" form="zmm, zmm" xed="VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kand_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := a[15:0] AND b[15:0]
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KANDW" form="k, k, k" xed="KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kandn_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := (NOT a[15:0]) AND b[15:0]
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KANDNW" form="k, k, k" xed="KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_knot_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<description>Compute the bitwise NOT of 16-bit mask "a", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := NOT a[15:0]
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KNOTW" form="k, k" xed="KNOTW_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kor_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := a[15:0] OR b[15:0]
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KORW" form="k, k, k" xed="KORW_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxnor_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := NOT (a[15:0] XOR b[15:0])
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KXNORW" form="k, k, k" xed="KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kxor_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="b" etype="MASK"/>
+ 	<description>Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k".</description>
+ 	<operation>
+ k[15:0] := a[15:0] XOR b[15:0]
+ k[MAX:16] := 0
+ 	</operation>
+ 	<instruction name="KXORW" form="k, k, k" xed="KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name="_kshiftli_mask16">
+ 	<type>Mask</type>
+ 	<CPUID>AVX512F</CPUID>
+ 	<category>Mask</category>
+ 	<return type="__mmask16" varname="k" etype="MASK"/>
+ 	<parameter type="__mmask16" varname="a" etype="MASK"/>
+ 	<parameter type="unsigned int" varname="count" etype="IMM" immwidth="8"/>
+ 	<description>Shift the bits of 16-bit mask "a" left by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k".</description>
+ 	<operation>
+ k[MAX:0] := 0
+ IF count[7:0] &lt;= 15
+ 	k[15:0] := a[15:0] &lt;&lt; count[7:0]
+ FI
+ 	</operation>
+ 	<instruction name="KSHIFTLW" form="k, k, imm8" xed="KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512"/>
+ 	<header>immintrin.h</header>
+ </intrinsic>
+ <intrinsic tech="AVX-512" name